| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Global Instruction Selector for the ARM target *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 10 | |
| 11 | const unsigned MAX_SUBTARGET_PREDICATES = 82; |
| 12 | using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>; |
| 13 | |
| 14 | #endif // GET_GLOBALISEL_PREDICATE_BITSET |
| 15 | |
| 16 | #ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 17 | |
| 18 | mutable MatcherState State; |
| 19 | typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; |
| 20 | typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; |
| 21 | const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo; |
| 22 | static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; |
| 23 | static ARMInstructionSelector::CustomRendererFn CustomRenderers[]; |
| 24 | bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; |
| 25 | bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; |
| 26 | bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; |
| 27 | const uint8_t *getMatchTable() const override; |
| 28 | bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override; |
| 29 | bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override; |
| 30 | bool testSimplePredicate(unsigned PredicateID) const override; |
| 31 | bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override; |
| 32 | |
| 33 | #endif // GET_GLOBALISEL_TEMPORARIES_DECL |
| 34 | |
| 35 | #ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 36 | |
| 37 | , State(0), |
| 38 | ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) |
| 39 | |
| 40 | #endif // GET_GLOBALISEL_TEMPORARIES_INIT |
| 41 | |
| 42 | #ifdef GET_GLOBALISEL_IMPL |
| 43 | |
| 44 | // LLT Objects. |
| 45 | enum { |
| 46 | GILLT_s16, |
| 47 | GILLT_s32, |
| 48 | GILLT_s64, |
| 49 | GILLT_v2s1, |
| 50 | GILLT_v4s1, |
| 51 | GILLT_v8s1, |
| 52 | GILLT_v16s1, |
| 53 | GILLT_v8s8, |
| 54 | GILLT_v16s8, |
| 55 | GILLT_v4s16, |
| 56 | GILLT_v8s16, |
| 57 | GILLT_v2s32, |
| 58 | GILLT_v4s32, |
| 59 | GILLT_v2s64, |
| 60 | GILLT_v4s64, |
| 61 | GILLT_v8s64, |
| 62 | }; |
| 63 | const static size_t NumTypeObjects = 16; |
| 64 | const static LLT TypeObjects[] = { |
| 65 | LLT::scalar(16), |
| 66 | LLT::scalar(32), |
| 67 | LLT::scalar(64), |
| 68 | LLT::vector(ElementCount::getFixed(2), LLT::scalar(1)), |
| 69 | LLT::vector(ElementCount::getFixed(4), LLT::scalar(1)), |
| 70 | LLT::vector(ElementCount::getFixed(8), LLT::scalar(1)), |
| 71 | LLT::vector(ElementCount::getFixed(16), LLT::scalar(1)), |
| 72 | LLT::vector(ElementCount::getFixed(8), LLT::scalar(8)), |
| 73 | LLT::vector(ElementCount::getFixed(16), LLT::scalar(8)), |
| 74 | LLT::vector(ElementCount::getFixed(4), LLT::scalar(16)), |
| 75 | LLT::vector(ElementCount::getFixed(8), LLT::scalar(16)), |
| 76 | LLT::vector(ElementCount::getFixed(2), LLT::scalar(32)), |
| 77 | LLT::vector(ElementCount::getFixed(4), LLT::scalar(32)), |
| 78 | LLT::vector(ElementCount::getFixed(2), LLT::scalar(64)), |
| 79 | LLT::vector(ElementCount::getFixed(4), LLT::scalar(64)), |
| 80 | LLT::vector(ElementCount::getFixed(8), LLT::scalar(64)), |
| 81 | }; |
| 82 | |
| 83 | // Bits for subtarget features that participate in instruction matching. |
| 84 | enum SubtargetFeatureBits : uint8_t { |
| 85 | Feature_HasV4TBit = 4, |
| 86 | Feature_NoV4TBit = 5, |
| 87 | Feature_HasV5TBit = 11, |
| 88 | Feature_NoV5TBit = 63, |
| 89 | Feature_HasV5TEBit = 9, |
| 90 | Feature_HasV6Bit = 0, |
| 91 | Feature_NoV6Bit = 7, |
| 92 | Feature_HasV6MBit = 26, |
| 93 | Feature_HasV8MBaselineBit = 33, |
| 94 | Feature_HasV8_1MMainlineBit = 39, |
| 95 | Feature_HasMVEIntBit = 61, |
| 96 | Feature_HasMVEFloatBit = 62, |
| 97 | Feature_HasCDEBit = 81, |
| 98 | Feature_HasFPRegsBit = 40, |
| 99 | Feature_HasFPRegs16Bit = 41, |
| 100 | Feature_HasFPRegs64Bit = 73, |
| 101 | Feature_HasV6T2Bit = 6, |
| 102 | Feature_HasV6KBit = 16, |
| 103 | Feature_HasV7Bit = 3, |
| 104 | Feature_HasV8Bit = 53, |
| 105 | Feature_PreV8Bit = 17, |
| 106 | Feature_HasV8_1aBit = 75, |
| 107 | Feature_HasV8_3aBit = 76, |
| 108 | Feature_NoVFPBit = 20, |
| 109 | Feature_HasVFP2Bit = 19, |
| 110 | Feature_HasVFP3Bit = 50, |
| 111 | Feature_HasVFP4Bit = 48, |
| 112 | Feature_HasDPVFPBit = 42, |
| 113 | Feature_HasFPARMv8Bit = 45, |
| 114 | Feature_HasNEONBit = 51, |
| 115 | Feature_HasSHA2Bit = 60, |
| 116 | Feature_HasAESBit = 52, |
| 117 | Feature_HasDotProdBit = 54, |
| 118 | Feature_HasCRCBit = 12, |
| 119 | Feature_HasLOBBit = 38, |
| 120 | Feature_HasFP16Bit = 59, |
| 121 | Feature_HasFullFP16Bit = 44, |
| 122 | Feature_HasMatMulInt8Bit = 55, |
| 123 | Feature_HasDivideInThumbBit = 35, |
| 124 | Feature_HasDivideInARMBit = 10, |
| 125 | Feature_HasDSPBit = 34, |
| 126 | Feature_HasDBBit = 13, |
| 127 | Feature_HasV7ClrexBit = 15, |
| 128 | Feature_HasAcquireReleaseBit = 14, |
| 129 | Feature_HasMPBit = 2, |
| 130 | Feature_Has8MSecExtBit = 27, |
| 131 | Feature_HasZCZBit = 56, |
| 132 | Feature_UseNEONForFPBit = 79, |
| 133 | Feature_DontUseNEONForFPBit = 43, |
| 134 | Feature_IsThumbBit = 24, |
| 135 | Feature_IsThumb1OnlyBit = 25, |
| 136 | Feature_IsThumb2Bit = 32, |
| 137 | Feature_IsNotMClassBit = 36, |
| 138 | Feature_IsARMBit = 1, |
| 139 | Feature_IsWindowsBit = 28, |
| 140 | Feature_IsNotWindowsBit = 29, |
| 141 | Feature_IsReadTPTPIDRURWBit = 66, |
| 142 | Feature_IsReadTPTPIDRUROBit = 67, |
| 143 | Feature_IsReadTPTPIDRPRWBit = 68, |
| 144 | Feature_IsReadTPSoftBit = 18, |
| 145 | Feature_UseMovtBit = 37, |
| 146 | Feature_DontUseMovtBit = 21, |
| 147 | Feature_UseMovtInPicBit = 22, |
| 148 | Feature_DontUseMovtInPicBit = 23, |
| 149 | Feature_UseFPVMLxBit = 47, |
| 150 | Feature_SLSBLRMitigationBit = 65, |
| 151 | Feature_NoSLSBLRMitigationBit = 64, |
| 152 | Feature_UseMulOpsBit = 8, |
| 153 | Feature_UseFusedMACBit = 49, |
| 154 | Feature_HasFastVGETLNi32Bit = 57, |
| 155 | Feature_HasSlowVGETLNi32Bit = 77, |
| 156 | Feature_HasFastVDUP32Bit = 58, |
| 157 | Feature_HasSlowVDUP32Bit = 78, |
| 158 | Feature_UseVMOVSRBit = 46, |
| 159 | Feature_DontUseVMOVSRBit = 80, |
| 160 | Feature_IsLEBit = 72, |
| 161 | Feature_IsBEBit = 74, |
| 162 | Feature_GenExecuteOnlyBit = 31, |
| 163 | Feature_DontGenExecuteOnlyBit = 30, |
| 164 | Feature_GenT1ExecuteOnlyBit = 71, |
| 165 | Feature_SignRetAddrBit = 70, |
| 166 | Feature_NoSignRetAddrBit = 69, |
| 167 | }; |
| 168 | |
| 169 | PredicateBitset ARMInstructionSelector:: |
| 170 | computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const { |
| 171 | PredicateBitset Features{}; |
| 172 | if (Subtarget->hasV4TOps()) |
| 173 | Features.set(Feature_HasV4TBit); |
| 174 | if (!Subtarget->hasV4TOps()) |
| 175 | Features.set(Feature_NoV4TBit); |
| 176 | if (Subtarget->hasV5TOps()) |
| 177 | Features.set(Feature_HasV5TBit); |
| 178 | if (!Subtarget->hasV5TOps()) |
| 179 | Features.set(Feature_NoV5TBit); |
| 180 | if (Subtarget->hasV5TEOps()) |
| 181 | Features.set(Feature_HasV5TEBit); |
| 182 | if (Subtarget->hasV6Ops()) |
| 183 | Features.set(Feature_HasV6Bit); |
| 184 | if (!Subtarget->hasV6Ops()) |
| 185 | Features.set(Feature_NoV6Bit); |
| 186 | if (Subtarget->hasV6MOps()) |
| 187 | Features.set(Feature_HasV6MBit); |
| 188 | if (Subtarget->hasV8MBaselineOps()) |
| 189 | Features.set(Feature_HasV8MBaselineBit); |
| 190 | if (Subtarget->hasV8_1MMainlineOps()) |
| 191 | Features.set(Feature_HasV8_1MMainlineBit); |
| 192 | if (Subtarget->hasMVEIntegerOps()) |
| 193 | Features.set(Feature_HasMVEIntBit); |
| 194 | if (Subtarget->hasMVEFloatOps()) |
| 195 | Features.set(Feature_HasMVEFloatBit); |
| 196 | if (Subtarget->hasCDEOps()) |
| 197 | Features.set(Feature_HasCDEBit); |
| 198 | if (Subtarget->hasFPRegs()) |
| 199 | Features.set(Feature_HasFPRegsBit); |
| 200 | if (Subtarget->hasFPRegs16()) |
| 201 | Features.set(Feature_HasFPRegs16Bit); |
| 202 | if (Subtarget->hasFPRegs64()) |
| 203 | Features.set(Feature_HasFPRegs64Bit); |
| 204 | if (Subtarget->hasV6T2Ops()) |
| 205 | Features.set(Feature_HasV6T2Bit); |
| 206 | if (Subtarget->hasV6KOps()) |
| 207 | Features.set(Feature_HasV6KBit); |
| 208 | if (Subtarget->hasV7Ops()) |
| 209 | Features.set(Feature_HasV7Bit); |
| 210 | if (Subtarget->hasV8Ops()) |
| 211 | Features.set(Feature_HasV8Bit); |
| 212 | if (!Subtarget->hasV8Ops()) |
| 213 | Features.set(Feature_PreV8Bit); |
| 214 | if (Subtarget->hasV8_1aOps()) |
| 215 | Features.set(Feature_HasV8_1aBit); |
| 216 | if (Subtarget->hasV8_3aOps()) |
| 217 | Features.set(Feature_HasV8_3aBit); |
| 218 | if (!Subtarget->hasVFP2Base()) |
| 219 | Features.set(Feature_NoVFPBit); |
| 220 | if (Subtarget->hasVFP2Base()) |
| 221 | Features.set(Feature_HasVFP2Bit); |
| 222 | if (Subtarget->hasVFP3Base()) |
| 223 | Features.set(Feature_HasVFP3Bit); |
| 224 | if (Subtarget->hasVFP4Base()) |
| 225 | Features.set(Feature_HasVFP4Bit); |
| 226 | if (Subtarget->hasFP64()) |
| 227 | Features.set(Feature_HasDPVFPBit); |
| 228 | if (Subtarget->hasFPARMv8Base()) |
| 229 | Features.set(Feature_HasFPARMv8Bit); |
| 230 | if (Subtarget->hasNEON()) |
| 231 | Features.set(Feature_HasNEONBit); |
| 232 | if (Subtarget->hasSHA2()) |
| 233 | Features.set(Feature_HasSHA2Bit); |
| 234 | if (Subtarget->hasAES()) |
| 235 | Features.set(Feature_HasAESBit); |
| 236 | if (Subtarget->hasDotProd()) |
| 237 | Features.set(Feature_HasDotProdBit); |
| 238 | if (Subtarget->hasCRC()) |
| 239 | Features.set(Feature_HasCRCBit); |
| 240 | if (Subtarget->hasLOB()) |
| 241 | Features.set(Feature_HasLOBBit); |
| 242 | if (Subtarget->hasFP16()) |
| 243 | Features.set(Feature_HasFP16Bit); |
| 244 | if (Subtarget->hasFullFP16()) |
| 245 | Features.set(Feature_HasFullFP16Bit); |
| 246 | if (Subtarget->hasMatMulInt8()) |
| 247 | Features.set(Feature_HasMatMulInt8Bit); |
| 248 | if (Subtarget->hasDivideInThumbMode()) |
| 249 | Features.set(Feature_HasDivideInThumbBit); |
| 250 | if (Subtarget->hasDivideInARMMode()) |
| 251 | Features.set(Feature_HasDivideInARMBit); |
| 252 | if (Subtarget->hasDSP()) |
| 253 | Features.set(Feature_HasDSPBit); |
| 254 | if (Subtarget->hasDataBarrier()) |
| 255 | Features.set(Feature_HasDBBit); |
| 256 | if (Subtarget->hasV7Clrex()) |
| 257 | Features.set(Feature_HasV7ClrexBit); |
| 258 | if (Subtarget->hasAcquireRelease()) |
| 259 | Features.set(Feature_HasAcquireReleaseBit); |
| 260 | if (Subtarget->hasMPExtension()) |
| 261 | Features.set(Feature_HasMPBit); |
| 262 | if (Subtarget->has8MSecExt()) |
| 263 | Features.set(Feature_Has8MSecExtBit); |
| 264 | if (Subtarget->hasZeroCycleZeroing()) |
| 265 | Features.set(Feature_HasZCZBit); |
| 266 | if (Subtarget->useNEONForSinglePrecisionFP()) |
| 267 | Features.set(Feature_UseNEONForFPBit); |
| 268 | if (!Subtarget->useNEONForSinglePrecisionFP()) |
| 269 | Features.set(Feature_DontUseNEONForFPBit); |
| 270 | if (Subtarget->isThumb()) |
| 271 | Features.set(Feature_IsThumbBit); |
| 272 | if (Subtarget->isThumb1Only()) |
| 273 | Features.set(Feature_IsThumb1OnlyBit); |
| 274 | if (Subtarget->isThumb2()) |
| 275 | Features.set(Feature_IsThumb2Bit); |
| 276 | if (!Subtarget->isMClass()) |
| 277 | Features.set(Feature_IsNotMClassBit); |
| 278 | if (!Subtarget->isThumb()) |
| 279 | Features.set(Feature_IsARMBit); |
| 280 | if (Subtarget->isTargetWindows()) |
| 281 | Features.set(Feature_IsWindowsBit); |
| 282 | if (!Subtarget->isTargetWindows()) |
| 283 | Features.set(Feature_IsNotWindowsBit); |
| 284 | if (Subtarget->isReadTPTPIDRURW()) |
| 285 | Features.set(Feature_IsReadTPTPIDRURWBit); |
| 286 | if (Subtarget->isReadTPTPIDRURO()) |
| 287 | Features.set(Feature_IsReadTPTPIDRUROBit); |
| 288 | if (Subtarget->isReadTPTPIDRPRW()) |
| 289 | Features.set(Feature_IsReadTPTPIDRPRWBit); |
| 290 | if (Subtarget->isReadTPSoft()) |
| 291 | Features.set(Feature_IsReadTPSoftBit); |
| 292 | if (Subtarget->useMulOps()) |
| 293 | Features.set(Feature_UseMulOpsBit); |
| 294 | if (Subtarget->useFPVFMx()) |
| 295 | Features.set(Feature_UseFusedMACBit); |
| 296 | if (!Subtarget->hasSlowVGETLNi32()) |
| 297 | Features.set(Feature_HasFastVGETLNi32Bit); |
| 298 | if (Subtarget->hasSlowVGETLNi32()) |
| 299 | Features.set(Feature_HasSlowVGETLNi32Bit); |
| 300 | if (!Subtarget->hasSlowVDUP32()) |
| 301 | Features.set(Feature_HasFastVDUP32Bit); |
| 302 | if (Subtarget->hasSlowVDUP32()) |
| 303 | Features.set(Feature_HasSlowVDUP32Bit); |
| 304 | if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP()) |
| 305 | Features.set(Feature_UseVMOVSRBit); |
| 306 | if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP()) |
| 307 | Features.set(Feature_DontUseVMOVSRBit); |
| 308 | if (Subtarget->genExecuteOnly()) |
| 309 | Features.set(Feature_GenExecuteOnlyBit); |
| 310 | if (!Subtarget->genExecuteOnly()) |
| 311 | Features.set(Feature_DontGenExecuteOnlyBit); |
| 312 | if (Subtarget->genExecuteOnly() && Subtarget->isThumb1Only() && !Subtarget->hasV8MBaselineOps()) |
| 313 | Features.set(Feature_GenT1ExecuteOnlyBit); |
| 314 | return Features; |
| 315 | } |
| 316 | |
| 317 | void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { |
| 318 | AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget *)&MF.getSubtarget(), &MF); |
| 319 | } |
| 320 | PredicateBitset ARMInstructionSelector:: |
| 321 | computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const { |
| 322 | PredicateBitset Features{}; |
| 323 | if (Subtarget->useMovt()) |
| 324 | Features.set(Feature_UseMovtBit); |
| 325 | if (!Subtarget->useMovt()) |
| 326 | Features.set(Feature_DontUseMovtBit); |
| 327 | if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt()) |
| 328 | Features.set(Feature_UseMovtInPicBit); |
| 329 | if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt()) |
| 330 | Features.set(Feature_DontUseMovtInPicBit); |
| 331 | if (Subtarget->useFPVMLx() || Subtarget->hasMinSize()) |
| 332 | Features.set(Feature_UseFPVMLxBit); |
| 333 | if ( MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() ) |
| 334 | Features.set(Feature_SLSBLRMitigationBit); |
| 335 | if ( !MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() ) |
| 336 | Features.set(Feature_NoSLSBLRMitigationBit); |
| 337 | if (MF->getDataLayout().isLittleEndian()) |
| 338 | Features.set(Feature_IsLEBit); |
| 339 | if (MF->getDataLayout().isBigEndian()) |
| 340 | Features.set(Feature_IsBEBit); |
| 341 | if ( MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) ) |
| 342 | Features.set(Feature_SignRetAddrBit); |
| 343 | if ( !MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) ) |
| 344 | Features.set(Feature_NoSignRetAddrBit); |
| 345 | return Features; |
| 346 | } |
| 347 | |
| 348 | // Feature bitsets. |
| 349 | enum { |
| 350 | GIFBS_Invalid, |
| 351 | GIFBS_HasDPVFP, |
| 352 | GIFBS_HasDotProd, |
| 353 | GIFBS_HasFP16, |
| 354 | GIFBS_HasFPARMv8, |
| 355 | GIFBS_HasFPRegs, |
| 356 | GIFBS_HasFullFP16, |
| 357 | GIFBS_HasMVEFloat, |
| 358 | GIFBS_HasMVEInt, |
| 359 | GIFBS_HasMatMulInt8, |
| 360 | GIFBS_HasNEON, |
| 361 | GIFBS_HasVFP2, |
| 362 | GIFBS_HasVFP3, |
| 363 | GIFBS_HasVFP4, |
| 364 | GIFBS_IsARM, |
| 365 | GIFBS_IsThumb, |
| 366 | GIFBS_IsThumb2, |
| 367 | GIFBS_DontUseNEONForFP_HasVFP2, |
| 368 | GIFBS_DontUseVMOVSR_HasNEON, |
| 369 | GIFBS_Has8MSecExt_IsThumb, |
| 370 | GIFBS_HasAES_HasV8, |
| 371 | GIFBS_HasCRC_IsARM, |
| 372 | GIFBS_HasCRC_IsThumb2, |
| 373 | GIFBS_HasDB_IsARM, |
| 374 | GIFBS_HasDB_IsThumb, |
| 375 | GIFBS_HasDPVFP_HasFPARMv8, |
| 376 | GIFBS_HasDPVFP_HasVFP2, |
| 377 | GIFBS_HasDPVFP_HasVFP3, |
| 378 | GIFBS_HasDPVFP_HasVFP4, |
| 379 | GIFBS_HasDSP_IsThumb2, |
| 380 | GIFBS_HasDivideInARM_IsARM, |
| 381 | GIFBS_HasFP16_HasNEON, |
| 382 | GIFBS_HasFPARMv8_HasNEON, |
| 383 | GIFBS_HasFPRegs_HasFastVGETLNi32, |
| 384 | GIFBS_HasFPRegs_UseVMOVSR, |
| 385 | GIFBS_HasFullFP16_HasNEON, |
| 386 | GIFBS_HasMVEInt_HasV8_1MMainline, |
| 387 | GIFBS_HasMVEInt_IsBE, |
| 388 | GIFBS_HasMVEInt_IsLE, |
| 389 | GIFBS_HasNEON_HasV8, |
| 390 | GIFBS_HasNEON_HasV8_1a, |
| 391 | GIFBS_HasNEON_HasV8_3a, |
| 392 | GIFBS_HasNEON_HasVFP4, |
| 393 | GIFBS_HasNEON_IsBE, |
| 394 | GIFBS_HasNEON_IsLE, |
| 395 | GIFBS_HasNEON_UseNEONForFP, |
| 396 | GIFBS_HasSHA2_HasV8, |
| 397 | GIFBS_HasV5T_IsARM, |
| 398 | GIFBS_HasV5T_IsThumb, |
| 399 | GIFBS_HasV5TE_IsARM, |
| 400 | GIFBS_HasV6_IsARM, |
| 401 | GIFBS_HasV6K_IsARM, |
| 402 | GIFBS_HasV6M_IsThumb, |
| 403 | GIFBS_HasV6T2_IsARM, |
| 404 | GIFBS_HasV7_IsARM, |
| 405 | GIFBS_HasV7Clrex_IsThumb, |
| 406 | GIFBS_HasV8MBaseline_IsThumb, |
| 407 | GIFBS_IsARM_NoV5T, |
| 408 | GIFBS_IsARM_NoV6, |
| 409 | GIFBS_IsARM_PreV8, |
| 410 | GIFBS_IsThumb_IsThumb1Only, |
| 411 | GIFBS_IsThumb_IsWindows, |
| 412 | GIFBS_IsThumb_NoV5T, |
| 413 | GIFBS_IsThumb_UseMovt, |
| 414 | GIFBS_IsThumb2_PreV8, |
| 415 | GIFBS_IsThumb2_UseMulOps, |
| 416 | GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only, |
| 417 | GIFBS_HasDSP_IsThumb2_UseMulOps, |
| 418 | GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb, |
| 419 | GIFBS_HasFPARMv8_HasFullFP16_HasNEON, |
| 420 | GIFBS_HasFullFP16_HasNEON_HasV8, |
| 421 | GIFBS_HasFullFP16_HasNEON_HasV8_3a, |
| 422 | GIFBS_HasFullFP16_HasNEON_UseFPVMLx, |
| 423 | GIFBS_HasFullFP16_HasNEON_UseFusedMAC, |
| 424 | GIFBS_HasLOB_HasV8_1MMainline_IsThumb2, |
| 425 | GIFBS_HasNEON_UseFPVMLx_UseNEONForFP, |
| 426 | GIFBS_HasV5TE_IsARM_UseMulOps, |
| 427 | GIFBS_HasV6_IsARM_UseMulOps, |
| 428 | GIFBS_HasV6_IsThumb_IsThumb1Only, |
| 429 | GIFBS_HasV6T2_IsARM_UseMulOps, |
| 430 | GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP, |
| 431 | GIFBS_IsARM_NoV6_UseMulOps, |
| 432 | }; |
| 433 | constexpr static PredicateBitset FeatureBitsets[] { |
| 434 | {}, // GIFBS_Invalid |
| 435 | {Feature_HasDPVFPBit, }, |
| 436 | {Feature_HasDotProdBit, }, |
| 437 | {Feature_HasFP16Bit, }, |
| 438 | {Feature_HasFPARMv8Bit, }, |
| 439 | {Feature_HasFPRegsBit, }, |
| 440 | {Feature_HasFullFP16Bit, }, |
| 441 | {Feature_HasMVEFloatBit, }, |
| 442 | {Feature_HasMVEIntBit, }, |
| 443 | {Feature_HasMatMulInt8Bit, }, |
| 444 | {Feature_HasNEONBit, }, |
| 445 | {Feature_HasVFP2Bit, }, |
| 446 | {Feature_HasVFP3Bit, }, |
| 447 | {Feature_HasVFP4Bit, }, |
| 448 | {Feature_IsARMBit, }, |
| 449 | {Feature_IsThumbBit, }, |
| 450 | {Feature_IsThumb2Bit, }, |
| 451 | {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, }, |
| 452 | {Feature_DontUseVMOVSRBit, Feature_HasNEONBit, }, |
| 453 | {Feature_Has8MSecExtBit, Feature_IsThumbBit, }, |
| 454 | {Feature_HasAESBit, Feature_HasV8Bit, }, |
| 455 | {Feature_HasCRCBit, Feature_IsARMBit, }, |
| 456 | {Feature_HasCRCBit, Feature_IsThumb2Bit, }, |
| 457 | {Feature_HasDBBit, Feature_IsARMBit, }, |
| 458 | {Feature_HasDBBit, Feature_IsThumbBit, }, |
| 459 | {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, }, |
| 460 | {Feature_HasDPVFPBit, Feature_HasVFP2Bit, }, |
| 461 | {Feature_HasDPVFPBit, Feature_HasVFP3Bit, }, |
| 462 | {Feature_HasDPVFPBit, Feature_HasVFP4Bit, }, |
| 463 | {Feature_HasDSPBit, Feature_IsThumb2Bit, }, |
| 464 | {Feature_HasDivideInARMBit, Feature_IsARMBit, }, |
| 465 | {Feature_HasFP16Bit, Feature_HasNEONBit, }, |
| 466 | {Feature_HasFPARMv8Bit, Feature_HasNEONBit, }, |
| 467 | {Feature_HasFPRegsBit, Feature_HasFastVGETLNi32Bit, }, |
| 468 | {Feature_HasFPRegsBit, Feature_UseVMOVSRBit, }, |
| 469 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, }, |
| 470 | {Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, }, |
| 471 | {Feature_HasMVEIntBit, Feature_IsBEBit, }, |
| 472 | {Feature_HasMVEIntBit, Feature_IsLEBit, }, |
| 473 | {Feature_HasNEONBit, Feature_HasV8Bit, }, |
| 474 | {Feature_HasNEONBit, Feature_HasV8_1aBit, }, |
| 475 | {Feature_HasNEONBit, Feature_HasV8_3aBit, }, |
| 476 | {Feature_HasNEONBit, Feature_HasVFP4Bit, }, |
| 477 | {Feature_HasNEONBit, Feature_IsBEBit, }, |
| 478 | {Feature_HasNEONBit, Feature_IsLEBit, }, |
| 479 | {Feature_HasNEONBit, Feature_UseNEONForFPBit, }, |
| 480 | {Feature_HasSHA2Bit, Feature_HasV8Bit, }, |
| 481 | {Feature_HasV5TBit, Feature_IsARMBit, }, |
| 482 | {Feature_HasV5TBit, Feature_IsThumbBit, }, |
| 483 | {Feature_HasV5TEBit, Feature_IsARMBit, }, |
| 484 | {Feature_HasV6Bit, Feature_IsARMBit, }, |
| 485 | {Feature_HasV6KBit, Feature_IsARMBit, }, |
| 486 | {Feature_HasV6MBit, Feature_IsThumbBit, }, |
| 487 | {Feature_HasV6T2Bit, Feature_IsARMBit, }, |
| 488 | {Feature_HasV7Bit, Feature_IsARMBit, }, |
| 489 | {Feature_HasV7ClrexBit, Feature_IsThumbBit, }, |
| 490 | {Feature_HasV8MBaselineBit, Feature_IsThumbBit, }, |
| 491 | {Feature_IsARMBit, Feature_NoV5TBit, }, |
| 492 | {Feature_IsARMBit, Feature_NoV6Bit, }, |
| 493 | {Feature_IsARMBit, Feature_PreV8Bit, }, |
| 494 | {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, }, |
| 495 | {Feature_IsThumbBit, Feature_IsWindowsBit, }, |
| 496 | {Feature_IsThumbBit, Feature_NoV5TBit, }, |
| 497 | {Feature_IsThumbBit, Feature_UseMovtBit, }, |
| 498 | {Feature_IsThumb2Bit, Feature_PreV8Bit, }, |
| 499 | {Feature_IsThumb2Bit, Feature_UseMulOpsBit, }, |
| 500 | {Feature_DontUseMovtBit, Feature_GenExecuteOnlyBit, Feature_IsThumb1OnlyBit, }, |
| 501 | {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, }, |
| 502 | {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, }, |
| 503 | {Feature_HasFPARMv8Bit, Feature_HasFullFP16Bit, Feature_HasNEONBit, }, |
| 504 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, }, |
| 505 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, }, |
| 506 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, }, |
| 507 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, }, |
| 508 | {Feature_HasLOBBit, Feature_HasV8_1MMainlineBit, Feature_IsThumb2Bit, }, |
| 509 | {Feature_HasNEONBit, Feature_UseFPVMLxBit, Feature_UseNEONForFPBit, }, |
| 510 | {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, }, |
| 511 | {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, }, |
| 512 | {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, }, |
| 513 | {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, }, |
| 514 | {Feature_HasVFP4Bit, Feature_UseFusedMACBit, Feature_UseNEONForFPBit, }, |
| 515 | {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, }, |
| 516 | }; |
| 517 | |
| 518 | // ComplexPattern predicates. |
| 519 | enum { |
| 520 | GICP_Invalid, |
| 521 | }; |
| 522 | // See constructor for table contents |
| 523 | |
| 524 | ARMInstructionSelector::ComplexMatcherMemFn |
| 525 | ARMInstructionSelector::ComplexPredicateFns[] = { |
| 526 | nullptr, // GICP_Invalid |
| 527 | }; |
| 528 | |
| 529 | // PatFrag predicates. |
| 530 | enum { |
| 531 | GICXXPred_MI_Predicate_bf_inv_mask_imm = GICXXPred_Invalid + 1, |
| 532 | GICXXPred_MI_Predicate_fadd_contract, |
| 533 | GICXXPred_MI_Predicate_ffloor_nnan, |
| 534 | GICXXPred_MI_Predicate_fmul_contract, |
| 535 | GICXXPred_MI_Predicate_fsub_contract, |
| 536 | GICXXPred_MI_Predicate_or_disjoint, |
| 537 | GICXXPred_MI_Predicate_vfp_f32imm, |
| 538 | GICXXPred_MI_Predicate_vfp_f64imm, |
| 539 | }; |
| 540 | bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const { |
| 541 | const MachineFunction &MF = *MI.getParent()->getParent(); |
| 542 | const MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 543 | const auto &Operands = State.RecordedOperands; |
| 544 | (void)Operands; |
| 545 | (void)MRI; |
| 546 | switch (PredicateID) { |
| 547 | case GICXXPred_MI_Predicate_bf_inv_mask_imm: { |
| 548 | |
| 549 | // There's better methods of implementing this check. IntImmLeaf<> would be |
| 550 | // equivalent and have less boilerplate but we need a test for C++ |
| 551 | // predicates and this one causes new rules to be imported into GlobalISel |
| 552 | // without requiring additional features first. |
| 553 | const auto &MO = MI.getOperand(1); |
| 554 | if (!MO.isCImm()) |
| 555 | return false; |
| 556 | return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); |
| 557 | |
| 558 | llvm_unreachable("bf_inv_mask_imm should have returned"); |
| 559 | } |
| 560 | case GICXXPred_MI_Predicate_fadd_contract: { |
| 561 | |
| 562 | return MI.getFlag(MachineInstr::FmContract); |
| 563 | |
| 564 | } |
| 565 | case GICXXPred_MI_Predicate_ffloor_nnan: { |
| 566 | |
| 567 | return MI.getFlag(MachineInstr::FmNoNans); |
| 568 | |
| 569 | } |
| 570 | case GICXXPred_MI_Predicate_fmul_contract: { |
| 571 | |
| 572 | return MI.getFlag(MachineInstr::FmContract); |
| 573 | |
| 574 | } |
| 575 | case GICXXPred_MI_Predicate_fsub_contract: { |
| 576 | |
| 577 | return MI.getFlag(MachineInstr::FmContract); |
| 578 | |
| 579 | } |
| 580 | case GICXXPred_MI_Predicate_or_disjoint: { |
| 581 | |
| 582 | return MI.getFlag(MachineInstr::Disjoint); |
| 583 | |
| 584 | } |
| 585 | case GICXXPred_MI_Predicate_vfp_f32imm: { |
| 586 | |
| 587 | const auto &MO = MI.getOperand(1); |
| 588 | if (!MO.isFPImm()) |
| 589 | return false; |
| 590 | return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1; |
| 591 | |
| 592 | llvm_unreachable("vfp_f32imm should have returned"); |
| 593 | } |
| 594 | case GICXXPred_MI_Predicate_vfp_f64imm: { |
| 595 | |
| 596 | const auto &MO = MI.getOperand(1); |
| 597 | if (!MO.isFPImm()) |
| 598 | return false; |
| 599 | return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1; |
| 600 | |
| 601 | llvm_unreachable("vfp_f64imm should have returned"); |
| 602 | } |
| 603 | } |
| 604 | llvm_unreachable("Unknown predicate"); |
| 605 | return false; |
| 606 | } |
| 607 | // PatFrag predicates. |
| 608 | bool ARMInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const { |
| 609 | const auto &Operands = State.RecordedOperands; |
| 610 | Register Reg = MO.getReg(); |
| 611 | (void)Operands; |
| 612 | (void)Reg; |
| 613 | llvm_unreachable("Unknown predicate"); |
| 614 | return false; |
| 615 | } |
| 616 | // PatFrag predicates. |
| 617 | enum { |
| 618 | GICXXPred_I64_Predicate_FPNoSaturation = GICXXPred_Invalid + 1, |
| 619 | GICXXPred_I64_Predicate_Float8E4M3FN, |
| 620 | GICXXPred_I64_Predicate_Float8E5M2, |
| 621 | GICXXPred_I64_Predicate_NearestTiesToEven, |
| 622 | GICXXPred_I64_Predicate_VectorIndex8, |
| 623 | GICXXPred_I64_Predicate_VectorIndex16, |
| 624 | GICXXPred_I64_Predicate_VectorIndex32, |
| 625 | GICXXPred_I64_Predicate_VectorIndex32_Hi, |
| 626 | GICXXPred_I64_Predicate_VectorIndex64, |
| 627 | GICXXPred_I64_Predicate_asr_imm, |
| 628 | GICXXPred_I64_Predicate_imm0_7, |
| 629 | GICXXPred_I64_Predicate_imm0_15, |
| 630 | GICXXPred_I64_Predicate_imm0_31, |
| 631 | GICXXPred_I64_Predicate_imm0_32, |
| 632 | GICXXPred_I64_Predicate_imm0_63, |
| 633 | GICXXPred_I64_Predicate_imm0_239, |
| 634 | GICXXPred_I64_Predicate_imm0_255, |
| 635 | GICXXPred_I64_Predicate_imm0_255_expr, |
| 636 | GICXXPred_I64_Predicate_imm0_4095, |
| 637 | GICXXPred_I64_Predicate_imm0_65535, |
| 638 | GICXXPred_I64_Predicate_imm0_65535_expr, |
| 639 | GICXXPred_I64_Predicate_imm0_65535_neg, |
| 640 | GICXXPred_I64_Predicate_imm1_7, |
| 641 | GICXXPred_I64_Predicate_imm1_15, |
| 642 | GICXXPred_I64_Predicate_imm1_16, |
| 643 | GICXXPred_I64_Predicate_imm1_31, |
| 644 | GICXXPred_I64_Predicate_imm8, |
| 645 | GICXXPred_I64_Predicate_imm8_255, |
| 646 | GICXXPred_I64_Predicate_imm8_or_16, |
| 647 | GICXXPred_I64_Predicate_imm16, |
| 648 | GICXXPred_I64_Predicate_imm16_31, |
| 649 | GICXXPred_I64_Predicate_imm24b, |
| 650 | GICXXPred_I64_Predicate_imm32, |
| 651 | GICXXPred_I64_Predicate_imm256_510, |
| 652 | GICXXPred_I64_Predicate_imm_3b, |
| 653 | GICXXPred_I64_Predicate_imm_4b, |
| 654 | GICXXPred_I64_Predicate_imm_6b, |
| 655 | GICXXPred_I64_Predicate_imm_7b, |
| 656 | GICXXPred_I64_Predicate_imm_9b, |
| 657 | GICXXPred_I64_Predicate_imm_11b, |
| 658 | GICXXPred_I64_Predicate_imm_12b, |
| 659 | GICXXPred_I64_Predicate_imm_13b, |
| 660 | GICXXPred_I64_Predicate_imm_even, |
| 661 | GICXXPred_I64_Predicate_imm_odd, |
| 662 | GICXXPred_I64_Predicate_imm_sr, |
| 663 | GICXXPred_I64_Predicate_long_shift, |
| 664 | GICXXPred_I64_Predicate_mod_imm, |
| 665 | GICXXPred_I64_Predicate_mod_imm_not, |
| 666 | GICXXPred_I64_Predicate_pkh_asr_amt, |
| 667 | GICXXPred_I64_Predicate_pkh_lsl_amt, |
| 668 | GICXXPred_I64_Predicate_shr_imm8, |
| 669 | GICXXPred_I64_Predicate_shr_imm16, |
| 670 | GICXXPred_I64_Predicate_shr_imm32, |
| 671 | GICXXPred_I64_Predicate_shr_imm64, |
| 672 | GICXXPred_I64_Predicate_t2_so_imm, |
| 673 | GICXXPred_I64_Predicate_t2_so_imm_neg, |
| 674 | }; |
| 675 | bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { |
| 676 | switch (PredicateID) { |
| 677 | case GICXXPred_I64_Predicate_FPNoSaturation: { |
| 678 | return Imm == 0; |
| 679 | } |
| 680 | case GICXXPred_I64_Predicate_Float8E4M3FN: { |
| 681 | return Imm == APFloatBase::S_Float8E4M3FN; |
| 682 | } |
| 683 | case GICXXPred_I64_Predicate_Float8E5M2: { |
| 684 | return Imm == APFloatBase::S_Float8E5M2; |
| 685 | } |
| 686 | case GICXXPred_I64_Predicate_NearestTiesToEven: { |
| 687 | return Imm == static_cast<int>(RoundingMode::NearestTiesToEven); |
| 688 | } |
| 689 | case GICXXPred_I64_Predicate_VectorIndex8: { |
| 690 | |
| 691 | return ((uint64_t)Imm) < 8; |
| 692 | |
| 693 | } |
| 694 | case GICXXPred_I64_Predicate_VectorIndex16: { |
| 695 | |
| 696 | return ((uint64_t)Imm) < 4; |
| 697 | |
| 698 | } |
| 699 | case GICXXPred_I64_Predicate_VectorIndex32: { |
| 700 | |
| 701 | return ((uint64_t)Imm) < 2; |
| 702 | |
| 703 | } |
| 704 | case GICXXPred_I64_Predicate_VectorIndex32_Hi: { |
| 705 | |
| 706 | return ((uint64_t)Imm) >= 2 && ((uint64_t)Imm) < 4; |
| 707 | |
| 708 | } |
| 709 | case GICXXPred_I64_Predicate_VectorIndex64: { |
| 710 | |
| 711 | return ((uint64_t)Imm) < 1; |
| 712 | |
| 713 | } |
| 714 | case GICXXPred_I64_Predicate_asr_imm: { |
| 715 | return Imm > 0 && Imm <= 32; |
| 716 | } |
| 717 | case GICXXPred_I64_Predicate_imm0_7: { |
| 718 | |
| 719 | return Imm >= 0 && Imm < 8; |
| 720 | |
| 721 | } |
| 722 | case GICXXPred_I64_Predicate_imm0_15: { |
| 723 | |
| 724 | return Imm >= 0 && Imm < 16; |
| 725 | |
| 726 | } |
| 727 | case GICXXPred_I64_Predicate_imm0_31: { |
| 728 | |
| 729 | return Imm >= 0 && Imm < 32; |
| 730 | |
| 731 | } |
| 732 | case GICXXPred_I64_Predicate_imm0_32: { |
| 733 | |
| 734 | return Imm >= 0 && Imm < 33; |
| 735 | |
| 736 | } |
| 737 | case GICXXPred_I64_Predicate_imm0_63: { |
| 738 | |
| 739 | return Imm >= 0 && Imm < 64; |
| 740 | |
| 741 | } |
| 742 | case GICXXPred_I64_Predicate_imm0_239: { |
| 743 | return Imm >= 0 && Imm < 240; |
| 744 | } |
| 745 | case GICXXPred_I64_Predicate_imm0_255: { |
| 746 | return Imm >= 0 && Imm < 256; |
| 747 | } |
| 748 | case GICXXPred_I64_Predicate_imm0_255_expr: { |
| 749 | return Imm >= 0 && Imm < 256; |
| 750 | } |
| 751 | case GICXXPred_I64_Predicate_imm0_4095: { |
| 752 | |
| 753 | return Imm >= 0 && Imm < 4096; |
| 754 | |
| 755 | } |
| 756 | case GICXXPred_I64_Predicate_imm0_65535: { |
| 757 | |
| 758 | return Imm >= 0 && Imm < 65536; |
| 759 | |
| 760 | } |
| 761 | case GICXXPred_I64_Predicate_imm0_65535_expr: { |
| 762 | |
| 763 | return Imm >= 0 && Imm < 65536; |
| 764 | |
| 765 | } |
| 766 | case GICXXPred_I64_Predicate_imm0_65535_neg: { |
| 767 | |
| 768 | return -Imm >= 0 && -Imm < 65536; |
| 769 | |
| 770 | } |
| 771 | case GICXXPred_I64_Predicate_imm1_7: { |
| 772 | return Imm > 0 && Imm < 8; |
| 773 | } |
| 774 | case GICXXPred_I64_Predicate_imm1_15: { |
| 775 | return Imm > 0 && Imm < 16; |
| 776 | } |
| 777 | case GICXXPred_I64_Predicate_imm1_16: { |
| 778 | |
| 779 | return Imm > 0 && Imm <= 16; |
| 780 | |
| 781 | } |
| 782 | case GICXXPred_I64_Predicate_imm1_31: { |
| 783 | return Imm > 0 && Imm < 32; |
| 784 | } |
| 785 | case GICXXPred_I64_Predicate_imm8: { |
| 786 | return Imm == 8; |
| 787 | } |
| 788 | case GICXXPred_I64_Predicate_imm8_255: { |
| 789 | |
| 790 | return Imm >= 8 && Imm < 256; |
| 791 | |
| 792 | } |
| 793 | case GICXXPred_I64_Predicate_imm8_or_16: { |
| 794 | return Imm == 8 || Imm == 16; |
| 795 | } |
| 796 | case GICXXPred_I64_Predicate_imm16: { |
| 797 | return Imm == 16; |
| 798 | } |
| 799 | case GICXXPred_I64_Predicate_imm16_31: { |
| 800 | |
| 801 | return (int32_t)Imm >= 16 && (int32_t)Imm < 32; |
| 802 | |
| 803 | } |
| 804 | case GICXXPred_I64_Predicate_imm24b: { |
| 805 | |
| 806 | return Imm >= 0 && Imm <= 0xffffff; |
| 807 | |
| 808 | } |
| 809 | case GICXXPred_I64_Predicate_imm32: { |
| 810 | return Imm == 32; |
| 811 | } |
| 812 | case GICXXPred_I64_Predicate_imm256_510: { |
| 813 | |
| 814 | return Imm >= 256 && Imm < 511; |
| 815 | |
| 816 | } |
| 817 | case GICXXPred_I64_Predicate_imm_3b: { |
| 818 | { return Imm >= 0 && Imm < (1 << 3); } |
| 819 | llvm_unreachable("imm_3b should have returned"); |
| 820 | } |
| 821 | case GICXXPred_I64_Predicate_imm_4b: { |
| 822 | { return Imm >= 0 && Imm < (1 << 4); } |
| 823 | llvm_unreachable("imm_4b should have returned"); |
| 824 | } |
| 825 | case GICXXPred_I64_Predicate_imm_6b: { |
| 826 | { return Imm >= 0 && Imm < (1 << 6); } |
| 827 | llvm_unreachable("imm_6b should have returned"); |
| 828 | } |
| 829 | case GICXXPred_I64_Predicate_imm_7b: { |
| 830 | { return Imm >= 0 && Imm < (1 << 7); } |
| 831 | llvm_unreachable("imm_7b should have returned"); |
| 832 | } |
| 833 | case GICXXPred_I64_Predicate_imm_9b: { |
| 834 | { return Imm >= 0 && Imm < (1 << 9); } |
| 835 | llvm_unreachable("imm_9b should have returned"); |
| 836 | } |
| 837 | case GICXXPred_I64_Predicate_imm_11b: { |
| 838 | { return Imm >= 0 && Imm < (1 << 11); } |
| 839 | llvm_unreachable("imm_11b should have returned"); |
| 840 | } |
| 841 | case GICXXPred_I64_Predicate_imm_12b: { |
| 842 | { return Imm >= 0 && Imm < (1 << 12); } |
| 843 | llvm_unreachable("imm_12b should have returned"); |
| 844 | } |
| 845 | case GICXXPred_I64_Predicate_imm_13b: { |
| 846 | { return Imm >= 0 && Imm < (1 << 13); } |
| 847 | llvm_unreachable("imm_13b should have returned"); |
| 848 | } |
| 849 | case GICXXPred_I64_Predicate_imm_even: { |
| 850 | return (Imm & 1) == 0; |
| 851 | } |
| 852 | case GICXXPred_I64_Predicate_imm_odd: { |
| 853 | return (Imm & 1) == 1; |
| 854 | } |
| 855 | case GICXXPred_I64_Predicate_imm_sr: { |
| 856 | |
| 857 | return Imm > 0 && Imm <= 32; |
| 858 | |
| 859 | } |
| 860 | case GICXXPred_I64_Predicate_long_shift: { |
| 861 | return Imm > 0 && Imm <= 32; |
| 862 | } |
| 863 | case GICXXPred_I64_Predicate_mod_imm: { |
| 864 | |
| 865 | return ARM_AM::getSOImmVal(Imm) != -1; |
| 866 | |
| 867 | } |
| 868 | case GICXXPred_I64_Predicate_mod_imm_not: { |
| 869 | |
| 870 | return ARM_AM::getSOImmVal(~(uint32_t)Imm) != -1; |
| 871 | |
| 872 | } |
| 873 | case GICXXPred_I64_Predicate_pkh_asr_amt: { |
| 874 | return Imm > 0 && Imm <= 32; |
| 875 | } |
| 876 | case GICXXPred_I64_Predicate_pkh_lsl_amt: { |
| 877 | return Imm >= 0 && Imm < 32; |
| 878 | } |
| 879 | case GICXXPred_I64_Predicate_shr_imm8: { |
| 880 | return Imm > 0 && Imm <= 8; |
| 881 | } |
| 882 | case GICXXPred_I64_Predicate_shr_imm16: { |
| 883 | return Imm > 0 && Imm <= 16; |
| 884 | } |
| 885 | case GICXXPred_I64_Predicate_shr_imm32: { |
| 886 | return Imm > 0 && Imm <= 32; |
| 887 | } |
| 888 | case GICXXPred_I64_Predicate_shr_imm64: { |
| 889 | return Imm > 0 && Imm <= 64; |
| 890 | } |
| 891 | case GICXXPred_I64_Predicate_t2_so_imm: { |
| 892 | |
| 893 | return ARM_AM::getT2SOImmVal(Imm) != -1; |
| 894 | |
| 895 | } |
| 896 | case GICXXPred_I64_Predicate_t2_so_imm_neg: { |
| 897 | |
| 898 | return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1; |
| 899 | |
| 900 | } |
| 901 | } |
| 902 | llvm_unreachable("Unknown predicate"); |
| 903 | return false; |
| 904 | } |
| 905 | // PatFrag predicates. |
| 906 | bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { |
| 907 | llvm_unreachable("Unknown predicate"); |
| 908 | return false; |
| 909 | } |
| 910 | // PatFrag predicates. |
| 911 | enum { |
| 912 | GICXXPred_APInt_Predicate_arm_i32imm = GICXXPred_Invalid + 1, |
| 913 | }; |
| 914 | bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { |
| 915 | switch (PredicateID) { |
| 916 | case GICXXPred_APInt_Predicate_arm_i32imm: { |
| 917 | |
| 918 | if (Subtarget->useMovt()) |
| 919 | return true; |
| 920 | if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue())) |
| 921 | return true; |
| 922 | return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue()); |
| 923 | |
| 924 | llvm_unreachable("arm_i32imm should have returned"); |
| 925 | } |
| 926 | } |
| 927 | llvm_unreachable("Unknown predicate"); |
| 928 | return false; |
| 929 | } |
| 930 | bool ARMInstructionSelector::testSimplePredicate(unsigned) const { |
| 931 | llvm_unreachable("ARMInstructionSelector does not support simple predicates!"); |
| 932 | return false; |
| 933 | } |
| 934 | // Custom renderers. |
| 935 | enum { |
| 936 | GICR_Invalid, |
| 937 | GICR_renderFrameIndex, |
| 938 | GICR_renderInvertedImm, |
| 939 | GICR_renderVFPF32Imm, |
| 940 | GICR_renderVFPF64Imm, |
| 941 | }; |
| 942 | ARMInstructionSelector::CustomRendererFn |
| 943 | ARMInstructionSelector::CustomRenderers[] = { |
| 944 | nullptr, // GICR_Invalid |
| 945 | &ARMInstructionSelector::renderFrameIndex, |
| 946 | &ARMInstructionSelector::renderInvertedImm, |
| 947 | &ARMInstructionSelector::renderVFPF32Imm, |
| 948 | &ARMInstructionSelector::renderVFPF64Imm, |
| 949 | }; |
| 950 | |
| 951 | bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { |
| 952 | const PredicateBitset AvailableFeatures = getAvailableFeatures(); |
| 953 | MachineIRBuilder B(I); |
| 954 | State.MIs.clear(); |
| 955 | State.MIs.push_back(&I); |
| 956 | |
| 957 | if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) { |
| 958 | return true; |
| 959 | } |
| 960 | |
| 961 | return false; |
| 962 | } |
| 963 | |
| 964 | bool ARMInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const { |
| 965 | llvm_unreachable("ARMInstructionSelector does not support custom C++ actions!"); |
| 966 | } |
| 967 | #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ |
| 968 | #define GIMT_Encode2(Val) uint8_t(Val), uint8_t((Val) >> 8) |
| 969 | #define GIMT_Encode4(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24) |
| 970 | #define GIMT_Encode8(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24), uint8_t(uint64_t(Val) >> 32), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 56) |
| 971 | #else |
| 972 | #define GIMT_Encode2(Val) uint8_t((Val) >> 8), uint8_t(Val) |
| 973 | #define GIMT_Encode4(Val) uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val) |
| 974 | #define GIMT_Encode8(Val) uint8_t(uint64_t(Val) >> 56), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 32), uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val) |
| 975 | #endif |
| 976 | const uint8_t *ARMInstructionSelector::getMatchTable() const { |
| 977 | constexpr static uint8_t MatchTable0[] = { |
| 978 | /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(55), GIMT_Encode2(332), /*)*//*default:*//*Label 94*/ GIMT_Encode4(132457), |
| 979 | /* 10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(1118), |
| 980 | /* 14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(12546), |
| 981 | /* 18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(15644), |
| 982 | /* 22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(17307), |
| 983 | /* 26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(17401), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 984 | /* 46 */ /*TargetOpcode::G_AND*//*Label 5*/ GIMT_Encode4(17495), |
| 985 | /* 50 */ /*TargetOpcode::G_OR*//*Label 6*/ GIMT_Encode4(20595), |
| 986 | /* 54 */ /*TargetOpcode::G_XOR*//*Label 7*/ GIMT_Encode4(26321), |
| 987 | /* 58 */ /*TargetOpcode::G_ABDS*//*Label 8*/ GIMT_Encode4(27980), |
| 988 | /* 62 */ /*TargetOpcode::G_ABDU*//*Label 9*/ GIMT_Encode4(28490), |
| 989 | /* 66 */ /*TargetOpcode::G_UAVGFLOOR*//*Label 10*/ GIMT_Encode4(29000), |
| 990 | /* 70 */ /*TargetOpcode::G_UAVGCEIL*//*Label 11*/ GIMT_Encode4(29227), |
| 991 | /* 74 */ /*TargetOpcode::G_SAVGFLOOR*//*Label 12*/ GIMT_Encode4(29454), |
| 992 | /* 78 */ /*TargetOpcode::G_SAVGCEIL*//*Label 13*/ GIMT_Encode4(29681), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 993 | /* 130 */ /*TargetOpcode::G_CONCAT_VECTORS*//*Label 14*/ GIMT_Encode4(29908), GIMT_Encode4(0), GIMT_Encode4(0), |
| 994 | /* 142 */ /*TargetOpcode::G_BITCAST*//*Label 15*/ GIMT_Encode4(30575), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 995 | /* 158 */ /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 16*/ GIMT_Encode4(37762), |
| 996 | /* 162 */ /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 17*/ GIMT_Encode4(38161), GIMT_Encode4(0), GIMT_Encode4(0), |
| 997 | /* 174 */ /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 18*/ GIMT_Encode4(38527), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 998 | /* 190 */ /*TargetOpcode::G_SEXTLOAD*//*Label 19*/ GIMT_Encode4(38893), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 999 | /* 326 */ /*TargetOpcode::G_FENCE*//*Label 20*/ GIMT_Encode4(39054), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1000 | /* 346 */ /*TargetOpcode::G_INTRINSIC*//*Label 21*/ GIMT_Encode4(39075), |
| 1001 | /* 350 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 22*/ GIMT_Encode4(90371), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1002 | /* 362 */ /*TargetOpcode::G_ANYEXT*//*Label 23*/ GIMT_Encode4(96151), |
| 1003 | /* 366 */ /*TargetOpcode::G_TRUNC*//*Label 24*/ GIMT_Encode4(96290), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1004 | /* 382 */ /*TargetOpcode::G_CONSTANT*//*Label 25*/ GIMT_Encode4(96433), |
| 1005 | /* 386 */ /*TargetOpcode::G_FCONSTANT*//*Label 26*/ GIMT_Encode4(96745), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1006 | /* 398 */ /*TargetOpcode::G_SEXT*//*Label 27*/ GIMT_Encode4(96839), |
| 1007 | /* 402 */ /*TargetOpcode::G_SEXT_INREG*//*Label 28*/ GIMT_Encode4(96978), |
| 1008 | /* 406 */ /*TargetOpcode::G_ZEXT*//*Label 29*/ GIMT_Encode4(97568), |
| 1009 | /* 410 */ /*TargetOpcode::G_SHL*//*Label 30*/ GIMT_Encode4(98256), |
| 1010 | /* 414 */ /*TargetOpcode::G_LSHR*//*Label 31*/ GIMT_Encode4(98468), |
| 1011 | /* 418 */ /*TargetOpcode::G_ASHR*//*Label 32*/ GIMT_Encode4(98574), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1012 | /* 430 */ /*TargetOpcode::G_ROTR*//*Label 33*/ GIMT_Encode4(98842), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1013 | /* 498 */ /*TargetOpcode::G_UMULH*//*Label 34*/ GIMT_Encode4(99168), |
| 1014 | /* 502 */ /*TargetOpcode::G_SMULH*//*Label 35*/ GIMT_Encode4(99401), |
| 1015 | /* 506 */ /*TargetOpcode::G_UADDSAT*//*Label 36*/ GIMT_Encode4(99753), |
| 1016 | /* 510 */ /*TargetOpcode::G_SADDSAT*//*Label 37*/ GIMT_Encode4(100379), |
| 1017 | /* 514 */ /*TargetOpcode::G_USUBSAT*//*Label 38*/ GIMT_Encode4(101652), |
| 1018 | /* 518 */ /*TargetOpcode::G_SSUBSAT*//*Label 39*/ GIMT_Encode4(102278), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1019 | /* 562 */ /*TargetOpcode::G_FADD*//*Label 40*/ GIMT_Encode4(103271), |
| 1020 | /* 566 */ /*TargetOpcode::G_FSUB*//*Label 41*/ GIMT_Encode4(106076), |
| 1021 | /* 570 */ /*TargetOpcode::G_FMUL*//*Label 42*/ GIMT_Encode4(107789), |
| 1022 | /* 574 */ /*TargetOpcode::G_FMA*//*Label 43*/ GIMT_Encode4(108754), GIMT_Encode4(0), |
| 1023 | /* 582 */ /*TargetOpcode::G_FDIV*//*Label 44*/ GIMT_Encode4(110817), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1024 | /* 634 */ /*TargetOpcode::G_FNEG*//*Label 45*/ GIMT_Encode4(110979), |
| 1025 | /* 638 */ /*TargetOpcode::G_FPEXT*//*Label 46*/ GIMT_Encode4(113387), |
| 1026 | /* 642 */ /*TargetOpcode::G_FPTRUNC*//*Label 47*/ GIMT_Encode4(113651), |
| 1027 | /* 646 */ /*TargetOpcode::G_FPTOSI*//*Label 48*/ GIMT_Encode4(113943), |
| 1028 | /* 650 */ /*TargetOpcode::G_FPTOUI*//*Label 49*/ GIMT_Encode4(115225), |
| 1029 | /* 654 */ /*TargetOpcode::G_SITOFP*//*Label 50*/ GIMT_Encode4(116507), |
| 1030 | /* 658 */ /*TargetOpcode::G_UITOFP*//*Label 51*/ GIMT_Encode4(117149), |
| 1031 | /* 662 */ /*TargetOpcode::G_FPTOSI_SAT*//*Label 52*/ GIMT_Encode4(117791), |
| 1032 | /* 666 */ /*TargetOpcode::G_FPTOUI_SAT*//*Label 53*/ GIMT_Encode4(118154), |
| 1033 | /* 670 */ /*TargetOpcode::G_FABS*//*Label 54*/ GIMT_Encode4(118517), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1034 | /* 686 */ /*TargetOpcode::G_FMINNUM*//*Label 55*/ GIMT_Encode4(119281), |
| 1035 | /* 690 */ /*TargetOpcode::G_FMAXNUM*//*Label 56*/ GIMT_Encode4(119862), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1036 | /* 702 */ /*TargetOpcode::G_FMINIMUM*//*Label 57*/ GIMT_Encode4(120443), |
| 1037 | /* 706 */ /*TargetOpcode::G_FMAXIMUM*//*Label 58*/ GIMT_Encode4(121171), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1038 | /* 718 */ /*TargetOpcode::G_GET_FPENV*//*Label 59*/ GIMT_Encode4(121899), |
| 1039 | /* 722 */ /*TargetOpcode::G_SET_FPENV*//*Label 60*/ GIMT_Encode4(121932), |
| 1040 | /* 726 */ /*TargetOpcode::G_RESET_FPENV*//*Label 61*/ GIMT_Encode4(121968), |
| 1041 | /* 730 */ /*TargetOpcode::G_GET_FPMODE*//*Label 62*/ GIMT_Encode4(122095), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1042 | /* 758 */ /*TargetOpcode::G_SMIN*//*Label 63*/ GIMT_Encode4(122128), |
| 1043 | /* 762 */ /*TargetOpcode::G_SMAX*//*Label 64*/ GIMT_Encode4(122638), |
| 1044 | /* 766 */ /*TargetOpcode::G_UMIN*//*Label 65*/ GIMT_Encode4(123148), |
| 1045 | /* 770 */ /*TargetOpcode::G_UMAX*//*Label 66*/ GIMT_Encode4(124036), |
| 1046 | /* 774 */ /*TargetOpcode::G_ABS*//*Label 67*/ GIMT_Encode4(124924), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1047 | /* 786 */ /*TargetOpcode::G_BR*//*Label 68*/ GIMT_Encode4(125362), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1048 | /* 806 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 69*/ GIMT_Encode4(125432), |
| 1049 | /* 810 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 70*/ GIMT_Encode4(125708), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1050 | /* 838 */ /*TargetOpcode::G_CTLZ*//*Label 71*/ GIMT_Encode4(125764), GIMT_Encode4(0), |
| 1051 | /* 846 */ /*TargetOpcode::G_CTLS*//*Label 72*/ GIMT_Encode4(126302), |
| 1052 | /* 850 */ /*TargetOpcode::G_CTPOP*//*Label 73*/ GIMT_Encode4(126740), |
| 1053 | /* 854 */ /*TargetOpcode::G_BSWAP*//*Label 74*/ GIMT_Encode4(126834), |
| 1054 | /* 858 */ /*TargetOpcode::G_BITREVERSE*//*Label 75*/ GIMT_Encode4(127119), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1055 | /* 870 */ /*TargetOpcode::G_FCEIL*//*Label 76*/ GIMT_Encode4(127534), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1056 | /* 918 */ /*TargetOpcode::G_FSQRT*//*Label 77*/ GIMT_Encode4(127900), |
| 1057 | /* 922 */ /*TargetOpcode::G_FFLOOR*//*Label 78*/ GIMT_Encode4(128035), |
| 1058 | /* 926 */ /*TargetOpcode::G_FRINT*//*Label 79*/ GIMT_Encode4(128401), |
| 1059 | /* 930 */ /*TargetOpcode::G_FNEARBYINT*//*Label 80*/ GIMT_Encode4(128800), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1060 | /* 958 */ /*TargetOpcode::G_STRICT_FADD*//*Label 81*/ GIMT_Encode4(128935), |
| 1061 | /* 962 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 82*/ GIMT_Encode4(129097), |
| 1062 | /* 966 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 83*/ GIMT_Encode4(129259), |
| 1063 | /* 970 */ /*TargetOpcode::G_STRICT_FDIV*//*Label 84*/ GIMT_Encode4(129421), GIMT_Encode4(0), |
| 1064 | /* 978 */ /*TargetOpcode::G_STRICT_FMA*//*Label 85*/ GIMT_Encode4(129583), |
| 1065 | /* 982 */ /*TargetOpcode::G_STRICT_FSQRT*//*Label 86*/ GIMT_Encode4(130750), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1066 | /* 1030 */ /*TargetOpcode::G_TRAP*//*Label 87*/ GIMT_Encode4(130885), |
| 1067 | /* 1034 */ /*TargetOpcode::G_DEBUGTRAP*//*Label 88*/ GIMT_Encode4(130914), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1068 | /* 1082 */ /*TargetOpcode::G_VECREDUCE_ADD*//*Label 89*/ GIMT_Encode4(130997), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1069 | /* 1102 */ /*TargetOpcode::G_VECREDUCE_SMAX*//*Label 90*/ GIMT_Encode4(131371), |
| 1070 | /* 1106 */ /*TargetOpcode::G_VECREDUCE_SMIN*//*Label 91*/ GIMT_Encode4(131636), |
| 1071 | /* 1110 */ /*TargetOpcode::G_VECREDUCE_UMAX*//*Label 92*/ GIMT_Encode4(131910), |
| 1072 | /* 1114 */ /*TargetOpcode::G_VECREDUCE_UMIN*//*Label 93*/ GIMT_Encode4(132176), |
| 1073 | /* 1118 */ // Label 0: @1118 |
| 1074 | /* 1118 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 104*/ GIMT_Encode4(12545), |
| 1075 | /* 1129 */ /*GILLT_s32*//*Label 95*/ GIMT_Encode4(1181), |
| 1076 | /* 1133 */ /*GILLT_s64*//*Label 96*/ GIMT_Encode4(6824), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1077 | /* 1153 */ /*GILLT_v8s8*//*Label 97*/ GIMT_Encode4(6870), |
| 1078 | /* 1157 */ /*GILLT_v16s8*//*Label 98*/ GIMT_Encode4(7304), |
| 1079 | /* 1161 */ /*GILLT_v4s16*//*Label 99*/ GIMT_Encode4(7804), |
| 1080 | /* 1165 */ /*GILLT_v8s16*//*Label 100*/ GIMT_Encode4(8238), |
| 1081 | /* 1169 */ /*GILLT_v2s32*//*Label 101*/ GIMT_Encode4(9673), |
| 1082 | /* 1173 */ /*GILLT_v4s32*//*Label 102*/ GIMT_Encode4(10107), |
| 1083 | /* 1177 */ /*GILLT_v2s64*//*Label 103*/ GIMT_Encode4(11542), |
| 1084 | /* 1181 */ // Label 95: @1181 |
| 1085 | /* 1181 */ GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(6823), |
| 1086 | /* 1186 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 1087 | /* 1189 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 1088 | /* 1192 */ GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(1338), |
| 1089 | /* 1197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1090 | /* 1201 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1091 | /* 1205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 107*/ GIMT_Encode4(1271), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6275 // |
| 1092 | /* 1212 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1093 | /* 1216 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1094 | /* 1220 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1095 | /* 1224 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1096 | /* 1228 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1097 | /* 1233 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1098 | /* 1244 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1099 | /* 1246 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1100 | /* 1246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB), |
| 1101 | /* 1249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1102 | /* 1251 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1103 | /* 1253 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1104 | /* 1257 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1105 | /* 1260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1106 | /* 1263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1107 | /* 1269 */ GIR_RootConstrainSelectedInstOperands, |
| 1108 | /* 1270 */ // GIR_Coverage, 6275, |
| 1109 | /* 1270 */ GIR_EraseRootFromParent_Done, |
| 1110 | /* 1271 */ // Label 107: @1271 |
| 1111 | /* 1271 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 108*/ GIMT_Encode4(1337), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6276 // |
| 1112 | /* 1278 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1113 | /* 1282 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1114 | /* 1286 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1115 | /* 1290 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1116 | /* 1294 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1117 | /* 1299 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1118 | /* 1310 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1119 | /* 1312 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1120 | /* 1312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH), |
| 1121 | /* 1315 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1122 | /* 1317 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1123 | /* 1319 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1124 | /* 1323 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1125 | /* 1326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1126 | /* 1329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1127 | /* 1335 */ GIR_RootConstrainSelectedInstOperands, |
| 1128 | /* 1336 */ // GIR_Coverage, 6276, |
| 1129 | /* 1336 */ GIR_EraseRootFromParent_Done, |
| 1130 | /* 1337 */ // Label 108: @1337 |
| 1131 | /* 1337 */ GIM_Reject, |
| 1132 | /* 1338 */ // Label 106: @1338 |
| 1133 | /* 1338 */ GIM_Try, /*On fail goto*//*Label 109*/ GIMT_Encode4(1484), |
| 1134 | /* 1343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1135 | /* 1347 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1136 | /* 1351 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 110*/ GIMT_Encode4(1417), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6314 // |
| 1137 | /* 1358 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1138 | /* 1362 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1139 | /* 1366 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1140 | /* 1370 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1141 | /* 1374 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1142 | /* 1379 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1143 | /* 1390 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1144 | /* 1392 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1145 | /* 1392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB), |
| 1146 | /* 1395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1147 | /* 1397 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1148 | /* 1399 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1149 | /* 1403 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1150 | /* 1406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1151 | /* 1409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1152 | /* 1415 */ GIR_RootConstrainSelectedInstOperands, |
| 1153 | /* 1416 */ // GIR_Coverage, 6314, |
| 1154 | /* 1416 */ GIR_EraseRootFromParent_Done, |
| 1155 | /* 1417 */ // Label 110: @1417 |
| 1156 | /* 1417 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 111*/ GIMT_Encode4(1483), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6315 // |
| 1157 | /* 1424 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1158 | /* 1428 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1159 | /* 1432 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1160 | /* 1436 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1161 | /* 1440 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1162 | /* 1445 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1163 | /* 1456 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1164 | /* 1458 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1165 | /* 1458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH), |
| 1166 | /* 1461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1167 | /* 1463 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1168 | /* 1465 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1169 | /* 1469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1170 | /* 1472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1171 | /* 1475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1172 | /* 1481 */ GIR_RootConstrainSelectedInstOperands, |
| 1173 | /* 1482 */ // GIR_Coverage, 6315, |
| 1174 | /* 1482 */ GIR_EraseRootFromParent_Done, |
| 1175 | /* 1483 */ // Label 111: @1483 |
| 1176 | /* 1483 */ GIM_Reject, |
| 1177 | /* 1484 */ // Label 109: @1484 |
| 1178 | /* 1484 */ GIM_Try, /*On fail goto*//*Label 112*/ GIMT_Encode4(1630), |
| 1179 | /* 1489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1180 | /* 1493 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1181 | /* 1497 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 113*/ GIMT_Encode4(1563), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2195 // |
| 1182 | /* 1504 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1183 | /* 1508 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1184 | /* 1512 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1185 | /* 1516 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1186 | /* 1520 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1187 | /* 1525 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1188 | /* 1536 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1189 | /* 1538 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1190 | /* 1538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB), |
| 1191 | /* 1541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1192 | /* 1543 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1193 | /* 1545 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1194 | /* 1549 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1195 | /* 1552 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1196 | /* 1555 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1197 | /* 1561 */ GIR_RootConstrainSelectedInstOperands, |
| 1198 | /* 1562 */ // GIR_Coverage, 2195, |
| 1199 | /* 1562 */ GIR_EraseRootFromParent_Done, |
| 1200 | /* 1563 */ // Label 113: @1563 |
| 1201 | /* 1563 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 114*/ GIMT_Encode4(1629), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2196 // |
| 1202 | /* 1570 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1203 | /* 1574 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1204 | /* 1578 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1205 | /* 1582 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1206 | /* 1586 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1207 | /* 1591 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1208 | /* 1602 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1209 | /* 1604 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1210 | /* 1604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH), |
| 1211 | /* 1607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1212 | /* 1609 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1213 | /* 1611 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1214 | /* 1615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1215 | /* 1618 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1216 | /* 1621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1217 | /* 1627 */ GIR_RootConstrainSelectedInstOperands, |
| 1218 | /* 1628 */ // GIR_Coverage, 2196, |
| 1219 | /* 1628 */ GIR_EraseRootFromParent_Done, |
| 1220 | /* 1629 */ // Label 114: @1629 |
| 1221 | /* 1629 */ GIM_Reject, |
| 1222 | /* 1630 */ // Label 112: @1630 |
| 1223 | /* 1630 */ GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(2278), |
| 1224 | /* 1635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1225 | /* 1639 */ GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(1781), |
| 1226 | /* 1644 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1227 | /* 1648 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 117*/ GIMT_Encode4(1714), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2439 // |
| 1228 | /* 1655 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1229 | /* 1659 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1230 | /* 1663 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1231 | /* 1667 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1232 | /* 1671 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1233 | /* 1676 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1234 | /* 1687 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1235 | /* 1689 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1236 | /* 1689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB), |
| 1237 | /* 1692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1238 | /* 1694 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1239 | /* 1696 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1240 | /* 1700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1241 | /* 1703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1242 | /* 1706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1243 | /* 1712 */ GIR_RootConstrainSelectedInstOperands, |
| 1244 | /* 1713 */ // GIR_Coverage, 2439, |
| 1245 | /* 1713 */ GIR_EraseRootFromParent_Done, |
| 1246 | /* 1714 */ // Label 117: @1714 |
| 1247 | /* 1714 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 118*/ GIMT_Encode4(1780), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2440 // |
| 1248 | /* 1721 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1249 | /* 1725 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1250 | /* 1729 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1251 | /* 1733 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1252 | /* 1737 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1253 | /* 1742 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1254 | /* 1753 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1255 | /* 1755 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1256 | /* 1755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH), |
| 1257 | /* 1758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1258 | /* 1760 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1259 | /* 1762 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1260 | /* 1766 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1261 | /* 1769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1262 | /* 1772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1263 | /* 1778 */ GIR_RootConstrainSelectedInstOperands, |
| 1264 | /* 1779 */ // GIR_Coverage, 2440, |
| 1265 | /* 1779 */ GIR_EraseRootFromParent_Done, |
| 1266 | /* 1780 */ // Label 118: @1780 |
| 1267 | /* 1780 */ GIM_Reject, |
| 1268 | /* 1781 */ // Label 116: @1781 |
| 1269 | /* 1781 */ GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(2029), |
| 1270 | /* 1786 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1271 | /* 1790 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 120*/ GIMT_Encode4(1909), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6287 // |
| 1272 | /* 1797 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1273 | /* 1801 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1274 | /* 1805 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1275 | /* 1809 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1276 | /* 1813 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1277 | /* 1817 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1278 | /* 1821 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1279 | /* 1825 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1280 | /* 1829 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1281 | /* 1833 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1282 | /* 1837 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1283 | /* 1841 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1284 | /* 1846 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24, |
| 1285 | /* 1850 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1286 | /* 1854 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1287 | /* 1858 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1288 | /* 1862 */ // MIs[4] Rm |
| 1289 | /* 1862 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1290 | /* 1867 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 1291 | /* 1871 */ // MIs[1] Operand 2 |
| 1292 | /* 1871 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1293 | /* 1882 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1294 | /* 1884 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1295 | /* 1884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1296 | /* 1887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1297 | /* 1889 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1298 | /* 1891 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1299 | /* 1895 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1300 | /* 1898 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1301 | /* 1901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1302 | /* 1907 */ GIR_RootConstrainSelectedInstOperands, |
| 1303 | /* 1908 */ // GIR_Coverage, 6287, |
| 1304 | /* 1908 */ GIR_EraseRootFromParent_Done, |
| 1305 | /* 1909 */ // Label 120: @1909 |
| 1306 | /* 1909 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 121*/ GIMT_Encode4(2028), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6288 // |
| 1307 | /* 1916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1308 | /* 1920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1309 | /* 1924 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1310 | /* 1928 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1311 | /* 1932 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1312 | /* 1936 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1313 | /* 1940 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1314 | /* 1944 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1315 | /* 1948 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1316 | /* 1952 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1317 | /* 1956 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1318 | /* 1960 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1319 | /* 1965 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8, |
| 1320 | /* 1969 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1321 | /* 1973 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1322 | /* 1977 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1323 | /* 1981 */ // MIs[4] Rm |
| 1324 | /* 1981 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1325 | /* 1986 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 1326 | /* 1990 */ // MIs[1] Operand 2 |
| 1327 | /* 1990 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1328 | /* 2001 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1329 | /* 2003 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1330 | /* 2003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1331 | /* 2006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1332 | /* 2008 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1333 | /* 2010 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1334 | /* 2014 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1335 | /* 2017 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1336 | /* 2020 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1337 | /* 2026 */ GIR_RootConstrainSelectedInstOperands, |
| 1338 | /* 2027 */ // GIR_Coverage, 6288, |
| 1339 | /* 2027 */ GIR_EraseRootFromParent_Done, |
| 1340 | /* 2028 */ // Label 121: @2028 |
| 1341 | /* 2028 */ GIM_Reject, |
| 1342 | /* 2029 */ // Label 119: @2029 |
| 1343 | /* 2029 */ GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(2277), |
| 1344 | /* 2034 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1345 | /* 2038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 123*/ GIMT_Encode4(2157), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2302 // |
| 1346 | /* 2045 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1347 | /* 2049 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1348 | /* 2053 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1349 | /* 2057 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1350 | /* 2061 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1351 | /* 2065 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1352 | /* 2069 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1353 | /* 2073 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1354 | /* 2077 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1355 | /* 2081 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1356 | /* 2085 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1357 | /* 2089 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1358 | /* 2094 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24, |
| 1359 | /* 2098 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1360 | /* 2102 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1361 | /* 2106 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1362 | /* 2110 */ // MIs[4] Rm |
| 1363 | /* 2110 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1364 | /* 2115 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 1365 | /* 2119 */ // MIs[1] Operand 2 |
| 1366 | /* 2119 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1367 | /* 2130 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1368 | /* 2132 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1369 | /* 2132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1370 | /* 2135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1371 | /* 2137 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1372 | /* 2139 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1373 | /* 2143 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1374 | /* 2146 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1375 | /* 2149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1376 | /* 2155 */ GIR_RootConstrainSelectedInstOperands, |
| 1377 | /* 2156 */ // GIR_Coverage, 2302, |
| 1378 | /* 2156 */ GIR_EraseRootFromParent_Done, |
| 1379 | /* 2157 */ // Label 123: @2157 |
| 1380 | /* 2157 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 124*/ GIMT_Encode4(2276), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6286 // |
| 1381 | /* 2164 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1382 | /* 2168 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1383 | /* 2172 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1384 | /* 2176 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1385 | /* 2180 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1386 | /* 2184 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1387 | /* 2188 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1388 | /* 2192 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1389 | /* 2196 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1390 | /* 2200 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1391 | /* 2204 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1392 | /* 2208 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1393 | /* 2213 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8, |
| 1394 | /* 2217 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1395 | /* 2221 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1396 | /* 2225 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1397 | /* 2229 */ // MIs[4] Rm |
| 1398 | /* 2229 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1399 | /* 2234 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 1400 | /* 2238 */ // MIs[1] Operand 2 |
| 1401 | /* 2238 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1402 | /* 2249 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1403 | /* 2251 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1404 | /* 2251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1405 | /* 2254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1406 | /* 2256 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1407 | /* 2258 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1408 | /* 2262 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1409 | /* 2265 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1410 | /* 2268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1411 | /* 2274 */ GIR_RootConstrainSelectedInstOperands, |
| 1412 | /* 2275 */ // GIR_Coverage, 6286, |
| 1413 | /* 2275 */ GIR_EraseRootFromParent_Done, |
| 1414 | /* 2276 */ // Label 124: @2276 |
| 1415 | /* 2276 */ GIM_Reject, |
| 1416 | /* 2277 */ // Label 122: @2277 |
| 1417 | /* 2277 */ GIM_Reject, |
| 1418 | /* 2278 */ // Label 115: @2278 |
| 1419 | /* 2278 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 125*/ GIMT_Encode4(2387), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5984 // |
| 1420 | /* 2285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1421 | /* 2289 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1422 | /* 2293 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1423 | /* 2297 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1424 | /* 2301 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1425 | /* 2305 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1426 | /* 2309 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1427 | /* 2313 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1428 | /* 2317 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1429 | /* 2321 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1430 | /* 2326 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1431 | /* 2330 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1432 | /* 2334 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1433 | /* 2338 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1434 | /* 2342 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1435 | /* 2346 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1436 | /* 2351 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1437 | /* 2355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1438 | /* 2359 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1439 | /* 2361 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1440 | /* 2361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), |
| 1441 | /* 2364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1442 | /* 2366 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1443 | /* 2370 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1444 | /* 2374 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1445 | /* 2376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1446 | /* 2379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1447 | /* 2385 */ GIR_RootConstrainSelectedInstOperands, |
| 1448 | /* 2386 */ // GIR_Coverage, 5984, |
| 1449 | /* 2386 */ GIR_EraseRootFromParent_Done, |
| 1450 | /* 2387 */ // Label 125: @2387 |
| 1451 | /* 2387 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 126*/ GIMT_Encode4(2496), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6019 // |
| 1452 | /* 2394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1453 | /* 2398 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1454 | /* 2402 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1455 | /* 2406 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1456 | /* 2410 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1457 | /* 2414 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1458 | /* 2418 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1459 | /* 2422 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1460 | /* 2426 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1461 | /* 2430 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1462 | /* 2435 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1463 | /* 2439 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1464 | /* 2443 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1465 | /* 2447 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1466 | /* 2451 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1467 | /* 2455 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1468 | /* 2460 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1469 | /* 2464 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1470 | /* 2468 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1471 | /* 2470 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1472 | /* 2470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), |
| 1473 | /* 2473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1474 | /* 2475 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1475 | /* 2479 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1476 | /* 2483 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1477 | /* 2485 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1478 | /* 2488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1479 | /* 2494 */ GIR_RootConstrainSelectedInstOperands, |
| 1480 | /* 2495 */ // GIR_Coverage, 6019, |
| 1481 | /* 2495 */ GIR_EraseRootFromParent_Done, |
| 1482 | /* 2496 */ // Label 126: @2496 |
| 1483 | /* 2496 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 127*/ GIMT_Encode4(2605), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 191 // |
| 1484 | /* 2503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1485 | /* 2507 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1486 | /* 2511 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1487 | /* 2515 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1488 | /* 2519 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1489 | /* 2523 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1490 | /* 2527 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1491 | /* 2531 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1492 | /* 2535 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1493 | /* 2539 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1494 | /* 2543 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1495 | /* 2548 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1496 | /* 2552 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1497 | /* 2556 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1498 | /* 2560 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1499 | /* 2564 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1500 | /* 2568 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1501 | /* 2573 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1502 | /* 2577 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1503 | /* 2579 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1504 | /* 2579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), |
| 1505 | /* 2582 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1506 | /* 2584 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1507 | /* 2588 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1508 | /* 2592 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1509 | /* 2594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1510 | /* 2597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1511 | /* 2603 */ GIR_RootConstrainSelectedInstOperands, |
| 1512 | /* 2604 */ // GIR_Coverage, 191, |
| 1513 | /* 2604 */ GIR_EraseRootFromParent_Done, |
| 1514 | /* 2605 */ // Label 127: @2605 |
| 1515 | /* 2605 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 128*/ GIMT_Encode4(2714), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 520 // |
| 1516 | /* 2612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1517 | /* 2616 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1518 | /* 2620 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1519 | /* 2624 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1520 | /* 2628 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1521 | /* 2632 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1522 | /* 2636 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1523 | /* 2640 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1524 | /* 2644 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1525 | /* 2648 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1526 | /* 2652 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1527 | /* 2657 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1528 | /* 2661 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1529 | /* 2665 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1530 | /* 2669 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1531 | /* 2673 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1532 | /* 2677 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1533 | /* 2682 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1534 | /* 2686 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1535 | /* 2688 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1536 | /* 2688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), |
| 1537 | /* 2691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1538 | /* 2693 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1539 | /* 2697 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1540 | /* 2701 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1541 | /* 2703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1542 | /* 2706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1543 | /* 2712 */ GIR_RootConstrainSelectedInstOperands, |
| 1544 | /* 2713 */ // GIR_Coverage, 520, |
| 1545 | /* 2713 */ GIR_EraseRootFromParent_Done, |
| 1546 | /* 2714 */ // Label 128: @2714 |
| 1547 | /* 2714 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 129*/ GIMT_Encode4(2826), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5983 // |
| 1548 | /* 2721 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1549 | /* 2725 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1550 | /* 2729 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1551 | /* 2733 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1552 | /* 2737 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1553 | /* 2741 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1554 | /* 2745 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1555 | /* 2749 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1556 | /* 2753 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1557 | /* 2757 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1558 | /* 2762 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1559 | /* 2766 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1560 | /* 2770 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1561 | /* 2774 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1562 | /* 2778 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1563 | /* 2783 */ // MIs[3] Operand 2 |
| 1564 | /* 2783 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1565 | /* 2794 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1566 | /* 2798 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1567 | /* 2800 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1568 | /* 2800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 1569 | /* 2803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1570 | /* 2805 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 1571 | /* 2809 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1572 | /* 2813 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1573 | /* 2815 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1574 | /* 2818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1575 | /* 2824 */ GIR_RootConstrainSelectedInstOperands, |
| 1576 | /* 2825 */ // GIR_Coverage, 5983, |
| 1577 | /* 2825 */ GIR_EraseRootFromParent_Done, |
| 1578 | /* 2826 */ // Label 129: @2826 |
| 1579 | /* 2826 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 130*/ GIMT_Encode4(2938), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6018 // |
| 1580 | /* 2833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1581 | /* 2837 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1582 | /* 2841 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1583 | /* 2845 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1584 | /* 2849 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1585 | /* 2853 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1586 | /* 2857 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1587 | /* 2861 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1588 | /* 2865 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1589 | /* 2869 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1590 | /* 2874 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1591 | /* 2878 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1592 | /* 2882 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1593 | /* 2886 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1594 | /* 2890 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1595 | /* 2895 */ // MIs[3] Operand 2 |
| 1596 | /* 2895 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1597 | /* 2906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1598 | /* 2910 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1599 | /* 2912 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1600 | /* 2912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 1601 | /* 2915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1602 | /* 2917 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 1603 | /* 2921 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1604 | /* 2925 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1605 | /* 2927 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1606 | /* 2930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1607 | /* 2936 */ GIR_RootConstrainSelectedInstOperands, |
| 1608 | /* 2937 */ // GIR_Coverage, 6018, |
| 1609 | /* 2937 */ GIR_EraseRootFromParent_Done, |
| 1610 | /* 2938 */ // Label 130: @2938 |
| 1611 | /* 2938 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 131*/ GIMT_Encode4(3050), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5982 // |
| 1612 | /* 2945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1613 | /* 2949 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1614 | /* 2953 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1615 | /* 2957 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1616 | /* 2961 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1617 | /* 2965 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1618 | /* 2969 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1619 | /* 2973 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1620 | /* 2977 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1621 | /* 2982 */ // MIs[2] Operand 2 |
| 1622 | /* 2982 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1623 | /* 2993 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1624 | /* 2997 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1625 | /* 3001 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1626 | /* 3005 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1627 | /* 3009 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1628 | /* 3014 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1629 | /* 3018 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1630 | /* 3022 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1631 | /* 3024 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1632 | /* 3024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 1633 | /* 3027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1634 | /* 3029 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1635 | /* 3033 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1636 | /* 3037 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1637 | /* 3039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1638 | /* 3042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1639 | /* 3048 */ GIR_RootConstrainSelectedInstOperands, |
| 1640 | /* 3049 */ // GIR_Coverage, 5982, |
| 1641 | /* 3049 */ GIR_EraseRootFromParent_Done, |
| 1642 | /* 3050 */ // Label 131: @3050 |
| 1643 | /* 3050 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 132*/ GIMT_Encode4(3162), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6017 // |
| 1644 | /* 3057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1645 | /* 3061 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1646 | /* 3065 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1647 | /* 3069 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1648 | /* 3073 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1649 | /* 3077 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1650 | /* 3081 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1651 | /* 3085 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1652 | /* 3089 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1653 | /* 3094 */ // MIs[2] Operand 2 |
| 1654 | /* 3094 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1655 | /* 3105 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1656 | /* 3109 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1657 | /* 3113 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1658 | /* 3117 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1659 | /* 3121 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1660 | /* 3126 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1661 | /* 3130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1662 | /* 3134 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1663 | /* 3136 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1664 | /* 3136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 1665 | /* 3139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1666 | /* 3141 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1667 | /* 3145 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1668 | /* 3149 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1669 | /* 3151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1670 | /* 3154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1671 | /* 3160 */ GIR_RootConstrainSelectedInstOperands, |
| 1672 | /* 3161 */ // GIR_Coverage, 6017, |
| 1673 | /* 3161 */ GIR_EraseRootFromParent_Done, |
| 1674 | /* 3162 */ // Label 132: @3162 |
| 1675 | /* 3162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 133*/ GIMT_Encode4(3274), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 190 // |
| 1676 | /* 3169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1677 | /* 3173 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1678 | /* 3177 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1679 | /* 3181 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1680 | /* 3185 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1681 | /* 3189 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1682 | /* 3193 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1683 | /* 3197 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1684 | /* 3201 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1685 | /* 3205 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1686 | /* 3209 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1687 | /* 3214 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1688 | /* 3218 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1689 | /* 3222 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1690 | /* 3226 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1691 | /* 3230 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1692 | /* 3235 */ // MIs[3] Operand 2 |
| 1693 | /* 3235 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1694 | /* 3246 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1695 | /* 3248 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLATB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1696 | /* 3248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB), |
| 1697 | /* 3251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1698 | /* 3253 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1699 | /* 3257 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1700 | /* 3261 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1701 | /* 3263 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1702 | /* 3266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1703 | /* 3272 */ GIR_RootConstrainSelectedInstOperands, |
| 1704 | /* 3273 */ // GIR_Coverage, 190, |
| 1705 | /* 3273 */ GIR_EraseRootFromParent_Done, |
| 1706 | /* 3274 */ // Label 133: @3274 |
| 1707 | /* 3274 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 134*/ GIMT_Encode4(3386), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 519 // |
| 1708 | /* 3281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1709 | /* 3285 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1710 | /* 3289 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1711 | /* 3293 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1712 | /* 3297 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1713 | /* 3301 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1714 | /* 3305 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1715 | /* 3309 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1716 | /* 3313 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1717 | /* 3317 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1718 | /* 3321 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1719 | /* 3326 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1720 | /* 3330 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1721 | /* 3334 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1722 | /* 3338 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1723 | /* 3342 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1724 | /* 3347 */ // MIs[3] Operand 2 |
| 1725 | /* 3347 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1726 | /* 3358 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1727 | /* 3360 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLATB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1728 | /* 3360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB), |
| 1729 | /* 3363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1730 | /* 3365 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1731 | /* 3369 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1732 | /* 3373 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1733 | /* 3375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1734 | /* 3378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1735 | /* 3384 */ GIR_RootConstrainSelectedInstOperands, |
| 1736 | /* 3385 */ // GIR_Coverage, 519, |
| 1737 | /* 3385 */ GIR_EraseRootFromParent_Done, |
| 1738 | /* 3386 */ // Label 134: @3386 |
| 1739 | /* 3386 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 135*/ GIMT_Encode4(3498), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 189 // |
| 1740 | /* 3393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1741 | /* 3397 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1742 | /* 3401 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1743 | /* 3405 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1744 | /* 3409 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1745 | /* 3413 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1746 | /* 3417 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1747 | /* 3421 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1748 | /* 3425 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1749 | /* 3429 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1750 | /* 3434 */ // MIs[2] Operand 2 |
| 1751 | /* 3434 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1752 | /* 3445 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1753 | /* 3449 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1754 | /* 3453 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1755 | /* 3457 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1756 | /* 3461 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1757 | /* 3466 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1758 | /* 3470 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1759 | /* 3472 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1760 | /* 3472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 1761 | /* 3475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1762 | /* 3477 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1763 | /* 3481 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1764 | /* 3485 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1765 | /* 3487 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1766 | /* 3490 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1767 | /* 3496 */ GIR_RootConstrainSelectedInstOperands, |
| 1768 | /* 3497 */ // GIR_Coverage, 189, |
| 1769 | /* 3497 */ GIR_EraseRootFromParent_Done, |
| 1770 | /* 3498 */ // Label 135: @3498 |
| 1771 | /* 3498 */ GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(3788), |
| 1772 | /* 3503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1773 | /* 3507 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 137*/ GIMT_Encode4(3615), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 518 // |
| 1774 | /* 3514 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1775 | /* 3518 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1776 | /* 3522 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1777 | /* 3526 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1778 | /* 3530 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1779 | /* 3534 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1780 | /* 3538 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1781 | /* 3542 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1782 | /* 3546 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1783 | /* 3551 */ // MIs[2] Operand 2 |
| 1784 | /* 3551 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1785 | /* 3562 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1786 | /* 3566 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1787 | /* 3570 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1788 | /* 3574 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1789 | /* 3578 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1790 | /* 3583 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1791 | /* 3587 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1792 | /* 3589 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1793 | /* 3589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 1794 | /* 3592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1795 | /* 3594 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1796 | /* 3598 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1797 | /* 3602 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1798 | /* 3604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1799 | /* 3607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1800 | /* 3613 */ GIR_RootConstrainSelectedInstOperands, |
| 1801 | /* 3614 */ // GIR_Coverage, 518, |
| 1802 | /* 3614 */ GIR_EraseRootFromParent_Done, |
| 1803 | /* 3615 */ // Label 137: @3615 |
| 1804 | /* 3615 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 138*/ GIMT_Encode4(3701), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6285 // |
| 1805 | /* 3622 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1806 | /* 3626 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1807 | /* 3630 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1808 | /* 3634 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1809 | /* 3638 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR), |
| 1810 | /* 3642 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1811 | /* 3646 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1812 | /* 3650 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1813 | /* 3655 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 1814 | /* 3659 */ // MIs[1] Operand 2 |
| 1815 | /* 3659 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1816 | /* 3670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1817 | /* 3674 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1818 | /* 3676 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1819 | /* 3676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1820 | /* 3679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1821 | /* 3681 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1822 | /* 3683 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1823 | /* 3687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1824 | /* 3690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1825 | /* 3693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1826 | /* 3699 */ GIR_RootConstrainSelectedInstOperands, |
| 1827 | /* 3700 */ // GIR_Coverage, 6285, |
| 1828 | /* 3700 */ GIR_EraseRootFromParent_Done, |
| 1829 | /* 3701 */ // Label 138: @3701 |
| 1830 | /* 3701 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 139*/ GIMT_Encode4(3787), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2301 // |
| 1831 | /* 3708 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1832 | /* 3712 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1833 | /* 3716 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1834 | /* 3720 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1835 | /* 3724 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1836 | /* 3728 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR), |
| 1837 | /* 3732 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1838 | /* 3736 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1839 | /* 3740 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1840 | /* 3745 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 1841 | /* 3749 */ // MIs[1] Operand 2 |
| 1842 | /* 3749 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1843 | /* 3760 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1844 | /* 3762 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1845 | /* 3762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1846 | /* 3765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1847 | /* 3767 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1848 | /* 3769 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1849 | /* 3773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1850 | /* 3776 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1851 | /* 3779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1852 | /* 3785 */ GIR_RootConstrainSelectedInstOperands, |
| 1853 | /* 3786 */ // GIR_Coverage, 2301, |
| 1854 | /* 3786 */ GIR_EraseRootFromParent_Done, |
| 1855 | /* 3787 */ // Label 139: @3787 |
| 1856 | /* 3787 */ GIM_Reject, |
| 1857 | /* 3788 */ // Label 136: @3788 |
| 1858 | /* 3788 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 140*/ GIMT_Encode4(3903), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5981 // |
| 1859 | /* 3795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1860 | /* 3799 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1861 | /* 3803 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1862 | /* 3807 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1863 | /* 3811 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1864 | /* 3815 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1865 | /* 3819 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1866 | /* 3823 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1867 | /* 3827 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1868 | /* 3832 */ // MIs[2] Operand 2 |
| 1869 | /* 3832 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1870 | /* 3843 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1871 | /* 3847 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1872 | /* 3851 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1873 | /* 3855 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1874 | /* 3860 */ // MIs[3] Operand 2 |
| 1875 | /* 3860 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1876 | /* 3871 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1877 | /* 3875 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1878 | /* 3877 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1879 | /* 3877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB), |
| 1880 | /* 3880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1881 | /* 3882 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1882 | /* 3886 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1883 | /* 3890 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1884 | /* 3892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1885 | /* 3895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1886 | /* 3901 */ GIR_RootConstrainSelectedInstOperands, |
| 1887 | /* 3902 */ // GIR_Coverage, 5981, |
| 1888 | /* 3902 */ GIR_EraseRootFromParent_Done, |
| 1889 | /* 3903 */ // Label 140: @3903 |
| 1890 | /* 3903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 141*/ GIMT_Encode4(4018), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6016 // |
| 1891 | /* 3910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1892 | /* 3914 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1893 | /* 3918 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1894 | /* 3922 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1895 | /* 3926 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1896 | /* 3930 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1897 | /* 3934 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1898 | /* 3938 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1899 | /* 3942 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1900 | /* 3947 */ // MIs[2] Operand 2 |
| 1901 | /* 3947 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1902 | /* 3958 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1903 | /* 3962 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1904 | /* 3966 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1905 | /* 3970 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1906 | /* 3975 */ // MIs[3] Operand 2 |
| 1907 | /* 3975 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1908 | /* 3986 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1909 | /* 3990 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1910 | /* 3992 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1911 | /* 3992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB), |
| 1912 | /* 3995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1913 | /* 3997 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1914 | /* 4001 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1915 | /* 4005 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1916 | /* 4007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1917 | /* 4010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1918 | /* 4016 */ GIR_RootConstrainSelectedInstOperands, |
| 1919 | /* 4017 */ // GIR_Coverage, 6016, |
| 1920 | /* 4017 */ GIR_EraseRootFromParent_Done, |
| 1921 | /* 4018 */ // Label 141: @4018 |
| 1922 | /* 4018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 142*/ GIMT_Encode4(4133), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 188 // |
| 1923 | /* 4025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1924 | /* 4029 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1925 | /* 4033 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1926 | /* 4037 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1927 | /* 4041 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1928 | /* 4045 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1929 | /* 4049 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1930 | /* 4053 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1931 | /* 4057 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1932 | /* 4061 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1933 | /* 4066 */ // MIs[2] Operand 2 |
| 1934 | /* 4066 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1935 | /* 4077 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1936 | /* 4081 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1937 | /* 4085 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1938 | /* 4089 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1939 | /* 4094 */ // MIs[3] Operand 2 |
| 1940 | /* 4094 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1941 | /* 4105 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1942 | /* 4107 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1943 | /* 4107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB), |
| 1944 | /* 4110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1945 | /* 4112 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1946 | /* 4116 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1947 | /* 4120 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1948 | /* 4122 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1949 | /* 4125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1950 | /* 4131 */ GIR_RootConstrainSelectedInstOperands, |
| 1951 | /* 4132 */ // GIR_Coverage, 188, |
| 1952 | /* 4132 */ GIR_EraseRootFromParent_Done, |
| 1953 | /* 4133 */ // Label 142: @4133 |
| 1954 | /* 4133 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 143*/ GIMT_Encode4(4248), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 517 // |
| 1955 | /* 4140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1956 | /* 4144 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1957 | /* 4148 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1958 | /* 4152 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1959 | /* 4156 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1960 | /* 4160 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1961 | /* 4164 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1962 | /* 4168 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1963 | /* 4172 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1964 | /* 4176 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1965 | /* 4181 */ // MIs[2] Operand 2 |
| 1966 | /* 4181 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1967 | /* 4192 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1968 | /* 4196 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1969 | /* 4200 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1970 | /* 4204 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1971 | /* 4209 */ // MIs[3] Operand 2 |
| 1972 | /* 4209 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1973 | /* 4220 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1974 | /* 4222 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1975 | /* 4222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB), |
| 1976 | /* 4225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1977 | /* 4227 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1978 | /* 4231 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1979 | /* 4235 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1980 | /* 4237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1981 | /* 4240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1982 | /* 4246 */ GIR_RootConstrainSelectedInstOperands, |
| 1983 | /* 4247 */ // GIR_Coverage, 517, |
| 1984 | /* 4247 */ GIR_EraseRootFromParent_Done, |
| 1985 | /* 4248 */ // Label 143: @4248 |
| 1986 | /* 4248 */ GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(4752), |
| 1987 | /* 4253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 1988 | /* 4257 */ GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(4504), |
| 1989 | /* 4262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 1990 | /* 4266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 146*/ GIMT_Encode4(4345), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3639 // |
| 1991 | /* 4273 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1992 | /* 4277 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 1993 | /* 4281 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1994 | /* 4285 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1995 | /* 4289 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1996 | /* 4293 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1997 | /* 4297 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1998 | /* 4301 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 1999 | /* 4306 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2000 | /* 4311 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2001 | /* 4313 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 2002 | /* 4313 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32), |
| 2003 | /* 4316 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2004 | /* 4318 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3 |
| 2005 | /* 4320 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2006 | /* 4324 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2007 | /* 4328 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2008 | /* 4331 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2009 | /* 4337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2010 | /* 4343 */ GIR_RootConstrainSelectedInstOperands, |
| 2011 | /* 4344 */ // GIR_Coverage, 3639, |
| 2012 | /* 4344 */ GIR_EraseRootFromParent_Done, |
| 2013 | /* 4345 */ // Label 146: @4345 |
| 2014 | /* 4345 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 147*/ GIMT_Encode4(4424), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3640 // |
| 2015 | /* 4352 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2016 | /* 4356 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2017 | /* 4360 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2018 | /* 4364 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2019 | /* 4368 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2020 | /* 4372 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2021 | /* 4376 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 2022 | /* 4380 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2023 | /* 4385 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2024 | /* 4390 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2025 | /* 4392 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 2026 | /* 4392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16), |
| 2027 | /* 4395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2028 | /* 4397 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3 |
| 2029 | /* 4399 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2030 | /* 4403 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2031 | /* 4407 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2032 | /* 4410 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2033 | /* 4416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2034 | /* 4422 */ GIR_RootConstrainSelectedInstOperands, |
| 2035 | /* 4423 */ // GIR_Coverage, 3640, |
| 2036 | /* 4423 */ GIR_EraseRootFromParent_Done, |
| 2037 | /* 4424 */ // Label 147: @4424 |
| 2038 | /* 4424 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 148*/ GIMT_Encode4(4503), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3643 // |
| 2039 | /* 4431 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2040 | /* 4435 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2041 | /* 4439 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2042 | /* 4443 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2043 | /* 4447 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2044 | /* 4451 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2045 | /* 4455 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2046 | /* 4459 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2047 | /* 4464 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2048 | /* 4469 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2049 | /* 4471 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 2050 | /* 4471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8), |
| 2051 | /* 4474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2052 | /* 4476 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3 |
| 2053 | /* 4478 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2054 | /* 4482 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2055 | /* 4486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2056 | /* 4489 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2057 | /* 4495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2058 | /* 4501 */ GIR_RootConstrainSelectedInstOperands, |
| 2059 | /* 4502 */ // GIR_Coverage, 3643, |
| 2060 | /* 4502 */ GIR_EraseRootFromParent_Done, |
| 2061 | /* 4503 */ // Label 148: @4503 |
| 2062 | /* 4503 */ GIM_Reject, |
| 2063 | /* 4504 */ // Label 145: @4504 |
| 2064 | /* 4504 */ GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(4751), |
| 2065 | /* 4509 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2066 | /* 4513 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 150*/ GIMT_Encode4(4592), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6586 // |
| 2067 | /* 4520 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2068 | /* 4524 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2069 | /* 4528 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2070 | /* 4532 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2071 | /* 4536 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2072 | /* 4540 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2073 | /* 4544 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2074 | /* 4548 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2075 | /* 4553 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2076 | /* 4558 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2077 | /* 4560 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2))) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 2078 | /* 4560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32), |
| 2079 | /* 4563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2080 | /* 4565 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3 |
| 2081 | /* 4567 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2082 | /* 4571 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2083 | /* 4575 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2084 | /* 4578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2085 | /* 4584 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2086 | /* 4590 */ GIR_RootConstrainSelectedInstOperands, |
| 2087 | /* 4591 */ // GIR_Coverage, 6586, |
| 2088 | /* 4591 */ GIR_EraseRootFromParent_Done, |
| 2089 | /* 4592 */ // Label 150: @4592 |
| 2090 | /* 4592 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 151*/ GIMT_Encode4(4671), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6587 // |
| 2091 | /* 4599 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2092 | /* 4603 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2093 | /* 4607 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2094 | /* 4611 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2095 | /* 4615 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2096 | /* 4619 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2097 | /* 4623 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 2098 | /* 4627 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2099 | /* 4632 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2100 | /* 4637 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2101 | /* 4639 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2))) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 2102 | /* 4639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16), |
| 2103 | /* 4642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2104 | /* 4644 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3 |
| 2105 | /* 4646 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2106 | /* 4650 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2107 | /* 4654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2108 | /* 4657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2109 | /* 4663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2110 | /* 4669 */ GIR_RootConstrainSelectedInstOperands, |
| 2111 | /* 4670 */ // GIR_Coverage, 6587, |
| 2112 | /* 4670 */ GIR_EraseRootFromParent_Done, |
| 2113 | /* 4671 */ // Label 151: @4671 |
| 2114 | /* 4671 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 152*/ GIMT_Encode4(4750), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6590 // |
| 2115 | /* 4678 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2116 | /* 4682 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2117 | /* 4686 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2118 | /* 4690 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2119 | /* 4694 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2120 | /* 4698 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2121 | /* 4702 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2122 | /* 4706 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2123 | /* 4711 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2124 | /* 4716 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2125 | /* 4718 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2))) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 2126 | /* 4718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8), |
| 2127 | /* 4721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2128 | /* 4723 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3 |
| 2129 | /* 4725 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2130 | /* 4729 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2131 | /* 4733 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2132 | /* 4736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2133 | /* 4742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2134 | /* 4748 */ GIR_RootConstrainSelectedInstOperands, |
| 2135 | /* 4749 */ // GIR_Coverage, 6590, |
| 2136 | /* 4749 */ GIR_EraseRootFromParent_Done, |
| 2137 | /* 4750 */ // Label 152: @4750 |
| 2138 | /* 4750 */ GIM_Reject, |
| 2139 | /* 4751 */ // Label 149: @4751 |
| 2140 | /* 4751 */ GIM_Reject, |
| 2141 | /* 4752 */ // Label 144: @4752 |
| 2142 | /* 4752 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 153*/ GIMT_Encode4(4808), GIMT_Encode2(GIFBS_IsARM), // Rule ID 71 // |
| 2143 | /* 4759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2144 | /* 4763 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2145 | /* 4767 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2146 | /* 4771 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2147 | /* 4775 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 2148 | /* 4779 */ // MIs[1] Operand 1 |
| 2149 | /* 4779 */ // No operand predicates |
| 2150 | /* 4779 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2151 | /* 4781 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2152 | /* 4781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDri), |
| 2153 | /* 4784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2154 | /* 4786 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2155 | /* 4788 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2156 | /* 4791 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2157 | /* 4794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2158 | /* 4800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2159 | /* 4806 */ GIR_RootConstrainSelectedInstOperands, |
| 2160 | /* 4807 */ // GIR_Coverage, 71, |
| 2161 | /* 4807 */ GIR_EraseRootFromParent_Done, |
| 2162 | /* 4808 */ // Label 153: @4808 |
| 2163 | /* 4808 */ GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(4918), |
| 2164 | /* 4813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2165 | /* 4817 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2166 | /* 4821 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 155*/ GIMT_Encode4(4869), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 302 // |
| 2167 | /* 4828 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2168 | /* 4832 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2169 | /* 4836 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 2170 | /* 4840 */ // MIs[1] Operand 1 |
| 2171 | /* 4840 */ // No operand predicates |
| 2172 | /* 4840 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2173 | /* 4842 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm3) => (tADDi3:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm3) |
| 2174 | /* 4842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi3), |
| 2175 | /* 4845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2176 | /* 4847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 2177 | /* 4853 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 2178 | /* 4855 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm3 |
| 2179 | /* 4858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2180 | /* 4861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2181 | /* 4867 */ GIR_RootConstrainSelectedInstOperands, |
| 2182 | /* 4868 */ // GIR_Coverage, 302, |
| 2183 | /* 4868 */ GIR_EraseRootFromParent_Done, |
| 2184 | /* 4869 */ // Label 155: @4869 |
| 2185 | /* 4869 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 156*/ GIMT_Encode4(4917), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 303 // |
| 2186 | /* 4876 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2187 | /* 4880 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2188 | /* 4884 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr), |
| 2189 | /* 4888 */ // MIs[1] Operand 1 |
| 2190 | /* 4888 */ // No operand predicates |
| 2191 | /* 4888 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2192 | /* 4890 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8) => (tADDi8:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm8) |
| 2193 | /* 4890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi8), |
| 2194 | /* 4893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 2195 | /* 4895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 2196 | /* 4901 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2197 | /* 4903 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8 |
| 2198 | /* 4906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2199 | /* 4909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2200 | /* 4915 */ GIR_RootConstrainSelectedInstOperands, |
| 2201 | /* 4916 */ // GIR_Coverage, 303, |
| 2202 | /* 4916 */ GIR_EraseRootFromParent_Done, |
| 2203 | /* 4917 */ // Label 156: @4917 |
| 2204 | /* 4917 */ GIM_Reject, |
| 2205 | /* 4918 */ // Label 154: @4918 |
| 2206 | /* 4918 */ GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(5026), |
| 2207 | /* 4923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2208 | /* 4927 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 158*/ GIMT_Encode4(4979), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 406 // |
| 2209 | /* 4934 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2210 | /* 4938 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2211 | /* 4942 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2212 | /* 4946 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 2213 | /* 4950 */ // MIs[1] Operand 1 |
| 2214 | /* 4950 */ // No operand predicates |
| 2215 | /* 4950 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2216 | /* 4952 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2217 | /* 4952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri), |
| 2218 | /* 4955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2219 | /* 4957 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2220 | /* 4959 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2221 | /* 4962 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2222 | /* 4965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2223 | /* 4971 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2224 | /* 4977 */ GIR_RootConstrainSelectedInstOperands, |
| 2225 | /* 4978 */ // GIR_Coverage, 406, |
| 2226 | /* 4978 */ GIR_EraseRootFromParent_Done, |
| 2227 | /* 4979 */ // Label 158: @4979 |
| 2228 | /* 4979 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 159*/ GIMT_Encode4(5025), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 407 // |
| 2229 | /* 4986 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2230 | /* 4990 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2231 | /* 4994 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2232 | /* 4998 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095), |
| 2233 | /* 5002 */ // MIs[1] Operand 1 |
| 2234 | /* 5002 */ // No operand predicates |
| 2235 | /* 5002 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2236 | /* 5004 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2237 | /* 5004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri12), |
| 2238 | /* 5007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2239 | /* 5009 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2240 | /* 5011 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2241 | /* 5014 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2242 | /* 5017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2243 | /* 5023 */ GIR_RootConstrainSelectedInstOperands, |
| 2244 | /* 5024 */ // GIR_Coverage, 407, |
| 2245 | /* 5024 */ GIR_EraseRootFromParent_Done, |
| 2246 | /* 5025 */ // Label 159: @5025 |
| 2247 | /* 5025 */ GIM_Reject, |
| 2248 | /* 5026 */ // Label 157: @5026 |
| 2249 | /* 5026 */ GIM_Try, /*On fail goto*//*Label 160*/ GIMT_Encode4(5174), |
| 2250 | /* 5031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2251 | /* 5035 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2252 | /* 5039 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 161*/ GIMT_Encode4(5106), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 170 // |
| 2253 | /* 5046 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2254 | /* 5050 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2255 | /* 5054 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2256 | /* 5058 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2257 | /* 5062 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2258 | /* 5067 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2259 | /* 5072 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2260 | /* 5074 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2261 | /* 5074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA), |
| 2262 | /* 5077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2263 | /* 5079 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2264 | /* 5083 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2265 | /* 5087 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2266 | /* 5089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2267 | /* 5092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2268 | /* 5098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2269 | /* 5104 */ GIR_RootConstrainSelectedInstOperands, |
| 2270 | /* 5105 */ // GIR_Coverage, 170, |
| 2271 | /* 5105 */ GIR_EraseRootFromParent_Done, |
| 2272 | /* 5106 */ // Label 161: @5106 |
| 2273 | /* 5106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 162*/ GIMT_Encode4(5173), GIMT_Encode2(GIFBS_IsARM_NoV6), // Rule ID 171 // |
| 2274 | /* 5113 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2275 | /* 5117 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2276 | /* 5121 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2277 | /* 5125 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2278 | /* 5129 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2279 | /* 5134 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2280 | /* 5139 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2281 | /* 5141 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2282 | /* 5141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5), |
| 2283 | /* 5144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2284 | /* 5146 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2285 | /* 5150 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2286 | /* 5154 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2287 | /* 5156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2288 | /* 5159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2289 | /* 5165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2290 | /* 5171 */ GIR_RootConstrainSelectedInstOperands, |
| 2291 | /* 5172 */ // GIR_Coverage, 171, |
| 2292 | /* 5172 */ GIR_EraseRootFromParent_Done, |
| 2293 | /* 5173 */ // Label 162: @5173 |
| 2294 | /* 5173 */ GIM_Reject, |
| 2295 | /* 5174 */ // Label 160: @5174 |
| 2296 | /* 5174 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 163*/ GIMT_Encode4(5243), GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), // Rule ID 502 // |
| 2297 | /* 5181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2298 | /* 5185 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2299 | /* 5189 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2300 | /* 5193 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2301 | /* 5197 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2302 | /* 5201 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2303 | /* 5206 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2304 | /* 5211 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2305 | /* 5215 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2306 | /* 5217 */ // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2307 | /* 5217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA), |
| 2308 | /* 5220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2309 | /* 5222 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2310 | /* 5226 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2311 | /* 5230 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2312 | /* 5232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2313 | /* 5235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2314 | /* 5241 */ GIR_RootConstrainSelectedInstOperands, |
| 2315 | /* 5242 */ // GIR_Coverage, 502, |
| 2316 | /* 5242 */ GIR_EraseRootFromParent_Done, |
| 2317 | /* 5243 */ // Label 163: @5243 |
| 2318 | /* 5243 */ GIM_Try, /*On fail goto*//*Label 164*/ GIMT_Encode4(5381), |
| 2319 | /* 5248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2320 | /* 5252 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2321 | /* 5256 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 165*/ GIMT_Encode4(5318), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6277 // |
| 2322 | /* 5263 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2323 | /* 5267 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2324 | /* 5271 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2325 | /* 5275 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2326 | /* 5280 */ // MIs[1] Operand 2 |
| 2327 | /* 5280 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2328 | /* 5291 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2329 | /* 5293 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2330 | /* 5293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB), |
| 2331 | /* 5296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2332 | /* 5298 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2333 | /* 5300 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2334 | /* 5304 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2335 | /* 5307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2336 | /* 5310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2337 | /* 5316 */ GIR_RootConstrainSelectedInstOperands, |
| 2338 | /* 5317 */ // GIR_Coverage, 6277, |
| 2339 | /* 5317 */ GIR_EraseRootFromParent_Done, |
| 2340 | /* 5318 */ // Label 165: @5318 |
| 2341 | /* 5318 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 166*/ GIMT_Encode4(5380), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6278 // |
| 2342 | /* 5325 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2343 | /* 5329 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2344 | /* 5333 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2345 | /* 5337 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2346 | /* 5342 */ // MIs[1] Operand 2 |
| 2347 | /* 5342 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2348 | /* 5353 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2349 | /* 5355 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2350 | /* 5355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH), |
| 2351 | /* 5358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2352 | /* 5360 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2353 | /* 5362 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2354 | /* 5366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2355 | /* 5369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2356 | /* 5372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2357 | /* 5378 */ GIR_RootConstrainSelectedInstOperands, |
| 2358 | /* 5379 */ // GIR_Coverage, 6278, |
| 2359 | /* 5379 */ GIR_EraseRootFromParent_Done, |
| 2360 | /* 5380 */ // Label 166: @5380 |
| 2361 | /* 5380 */ GIM_Reject, |
| 2362 | /* 5381 */ // Label 164: @5381 |
| 2363 | /* 5381 */ GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(5519), |
| 2364 | /* 5386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2365 | /* 5390 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2366 | /* 5394 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 168*/ GIMT_Encode4(5456), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6316 // |
| 2367 | /* 5401 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2368 | /* 5405 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2369 | /* 5409 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2370 | /* 5413 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2371 | /* 5418 */ // MIs[1] Operand 2 |
| 2372 | /* 5418 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2373 | /* 5429 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2374 | /* 5431 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2375 | /* 5431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB), |
| 2376 | /* 5434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2377 | /* 5436 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2378 | /* 5438 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2379 | /* 5442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2380 | /* 5445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2381 | /* 5448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2382 | /* 5454 */ GIR_RootConstrainSelectedInstOperands, |
| 2383 | /* 5455 */ // GIR_Coverage, 6316, |
| 2384 | /* 5455 */ GIR_EraseRootFromParent_Done, |
| 2385 | /* 5456 */ // Label 168: @5456 |
| 2386 | /* 5456 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 169*/ GIMT_Encode4(5518), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6317 // |
| 2387 | /* 5463 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2388 | /* 5467 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2389 | /* 5471 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2390 | /* 5475 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2391 | /* 5480 */ // MIs[1] Operand 2 |
| 2392 | /* 5480 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2393 | /* 5491 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2394 | /* 5493 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2395 | /* 5493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 2396 | /* 5496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2397 | /* 5498 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2398 | /* 5500 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2399 | /* 5504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2400 | /* 5507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2401 | /* 5510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2402 | /* 5516 */ GIR_RootConstrainSelectedInstOperands, |
| 2403 | /* 5517 */ // GIR_Coverage, 6317, |
| 2404 | /* 5517 */ GIR_EraseRootFromParent_Done, |
| 2405 | /* 5518 */ // Label 169: @5518 |
| 2406 | /* 5518 */ GIM_Reject, |
| 2407 | /* 5519 */ // Label 167: @5519 |
| 2408 | /* 5519 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 170*/ GIMT_Encode4(5588), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 179 // |
| 2409 | /* 5526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2410 | /* 5530 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2411 | /* 5534 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2412 | /* 5538 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2413 | /* 5542 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2414 | /* 5546 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2415 | /* 5551 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2416 | /* 5556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2417 | /* 5560 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2418 | /* 5562 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 2419 | /* 5562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA), |
| 2420 | /* 5565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2421 | /* 5567 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2422 | /* 5571 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2423 | /* 5575 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2424 | /* 5577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2425 | /* 5580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2426 | /* 5586 */ GIR_RootConstrainSelectedInstOperands, |
| 2427 | /* 5587 */ // GIR_Coverage, 179, |
| 2428 | /* 5587 */ GIR_EraseRootFromParent_Done, |
| 2429 | /* 5588 */ // Label 170: @5588 |
| 2430 | /* 5588 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 171*/ GIMT_Encode4(5657), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 508 // |
| 2431 | /* 5595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2432 | /* 5599 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2433 | /* 5603 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2434 | /* 5607 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2435 | /* 5611 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2436 | /* 5615 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2437 | /* 5620 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2438 | /* 5625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2439 | /* 5629 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2440 | /* 5631 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2441 | /* 5631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA), |
| 2442 | /* 5634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2443 | /* 5636 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2444 | /* 5640 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2445 | /* 5644 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2446 | /* 5646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2447 | /* 5649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2448 | /* 5655 */ GIR_RootConstrainSelectedInstOperands, |
| 2449 | /* 5656 */ // GIR_Coverage, 508, |
| 2450 | /* 5656 */ GIR_EraseRootFromParent_Done, |
| 2451 | /* 5657 */ // Label 171: @5657 |
| 2452 | /* 5657 */ GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(5833), |
| 2453 | /* 5662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2454 | /* 5666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2455 | /* 5670 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 173*/ GIMT_Encode4(5724), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3444 // |
| 2456 | /* 5677 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2457 | /* 5681 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2458 | /* 5685 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2459 | /* 5689 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2460 | /* 5694 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2461 | /* 5696 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec) |
| 2462 | /* 5696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc), |
| 2463 | /* 5699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2464 | /* 5701 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc |
| 2465 | /* 5703 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2466 | /* 5707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2467 | /* 5710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2468 | /* 5716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2469 | /* 5722 */ GIR_RootConstrainSelectedInstOperands, |
| 2470 | /* 5723 */ // GIR_Coverage, 3444, |
| 2471 | /* 5723 */ GIR_EraseRootFromParent_Done, |
| 2472 | /* 5724 */ // Label 173: @5724 |
| 2473 | /* 5724 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 174*/ GIMT_Encode4(5778), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3472 // |
| 2474 | /* 5731 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2475 | /* 5735 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2476 | /* 5739 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2477 | /* 5743 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2478 | /* 5748 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2479 | /* 5750 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec) |
| 2480 | /* 5750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc), |
| 2481 | /* 5753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2482 | /* 5755 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc |
| 2483 | /* 5757 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2484 | /* 5761 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2485 | /* 5764 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2486 | /* 5770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2487 | /* 5776 */ GIR_RootConstrainSelectedInstOperands, |
| 2488 | /* 5777 */ // GIR_Coverage, 3472, |
| 2489 | /* 5777 */ GIR_EraseRootFromParent_Done, |
| 2490 | /* 5778 */ // Label 174: @5778 |
| 2491 | /* 5778 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 175*/ GIMT_Encode4(5832), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3482 // |
| 2492 | /* 5785 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2493 | /* 5789 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2494 | /* 5793 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2495 | /* 5797 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2496 | /* 5802 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2497 | /* 5804 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec) |
| 2498 | /* 5804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc), |
| 2499 | /* 5807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2500 | /* 5809 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc |
| 2501 | /* 5811 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2502 | /* 5815 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2503 | /* 5818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2504 | /* 5824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2505 | /* 5830 */ GIR_RootConstrainSelectedInstOperands, |
| 2506 | /* 5831 */ // GIR_Coverage, 3482, |
| 2507 | /* 5831 */ GIR_EraseRootFromParent_Done, |
| 2508 | /* 5832 */ // Label 175: @5832 |
| 2509 | /* 5832 */ GIM_Reject, |
| 2510 | /* 5833 */ // Label 172: @5833 |
| 2511 | /* 5833 */ GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(5981), |
| 2512 | /* 5838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2513 | /* 5842 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2514 | /* 5846 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 177*/ GIMT_Encode4(5913), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 5978 // |
| 2515 | /* 5853 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2516 | /* 5857 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2517 | /* 5861 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2518 | /* 5865 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2519 | /* 5869 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2520 | /* 5874 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2521 | /* 5879 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2522 | /* 5881 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2523 | /* 5881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA), |
| 2524 | /* 5884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2525 | /* 5886 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2526 | /* 5890 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2527 | /* 5894 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2528 | /* 5896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2529 | /* 5899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2530 | /* 5905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2531 | /* 5911 */ GIR_RootConstrainSelectedInstOperands, |
| 2532 | /* 5912 */ // GIR_Coverage, 5978, |
| 2533 | /* 5912 */ GIR_EraseRootFromParent_Done, |
| 2534 | /* 5913 */ // Label 177: @5913 |
| 2535 | /* 5913 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 178*/ GIMT_Encode4(5980), GIMT_Encode2(GIFBS_IsARM_NoV6), // Rule ID 5979 // |
| 2536 | /* 5920 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2537 | /* 5924 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2538 | /* 5928 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2539 | /* 5932 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2540 | /* 5936 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2541 | /* 5941 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2542 | /* 5946 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2543 | /* 5948 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2544 | /* 5948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5), |
| 2545 | /* 5951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2546 | /* 5953 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2547 | /* 5957 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2548 | /* 5961 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2549 | /* 5963 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2550 | /* 5966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2551 | /* 5972 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2552 | /* 5978 */ GIR_RootConstrainSelectedInstOperands, |
| 2553 | /* 5979 */ // GIR_Coverage, 5979, |
| 2554 | /* 5979 */ GIR_EraseRootFromParent_Done, |
| 2555 | /* 5980 */ // Label 178: @5980 |
| 2556 | /* 5980 */ GIM_Reject, |
| 2557 | /* 5981 */ // Label 176: @5981 |
| 2558 | /* 5981 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 179*/ GIMT_Encode4(6050), GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), // Rule ID 6014 // |
| 2559 | /* 5988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2560 | /* 5992 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2561 | /* 5996 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2562 | /* 6000 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2563 | /* 6004 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2564 | /* 6008 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2565 | /* 6012 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2566 | /* 6017 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2567 | /* 6022 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2568 | /* 6024 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2569 | /* 6024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA), |
| 2570 | /* 6027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2571 | /* 6029 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2572 | /* 6033 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2573 | /* 6037 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2574 | /* 6039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2575 | /* 6042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2576 | /* 6048 */ GIR_RootConstrainSelectedInstOperands, |
| 2577 | /* 6049 */ // GIR_Coverage, 6014, |
| 2578 | /* 6049 */ GIR_EraseRootFromParent_Done, |
| 2579 | /* 6050 */ // Label 179: @6050 |
| 2580 | /* 6050 */ GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(6188), |
| 2581 | /* 6055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2582 | /* 6059 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2583 | /* 6063 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 181*/ GIMT_Encode4(6125), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2199 // |
| 2584 | /* 6070 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2585 | /* 6074 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2586 | /* 6078 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2587 | /* 6082 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2588 | /* 6087 */ // MIs[1] Operand 2 |
| 2589 | /* 6087 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2590 | /* 6098 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2591 | /* 6100 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2592 | /* 6100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB), |
| 2593 | /* 6103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2594 | /* 6105 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2595 | /* 6107 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2596 | /* 6111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2597 | /* 6114 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2598 | /* 6117 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2599 | /* 6123 */ GIR_RootConstrainSelectedInstOperands, |
| 2600 | /* 6124 */ // GIR_Coverage, 2199, |
| 2601 | /* 6124 */ GIR_EraseRootFromParent_Done, |
| 2602 | /* 6125 */ // Label 181: @6125 |
| 2603 | /* 6125 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 182*/ GIMT_Encode4(6187), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2200 // |
| 2604 | /* 6132 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2605 | /* 6136 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2606 | /* 6140 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2607 | /* 6144 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2608 | /* 6149 */ // MIs[1] Operand 2 |
| 2609 | /* 6149 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2610 | /* 6160 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2611 | /* 6162 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2612 | /* 6162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH), |
| 2613 | /* 6165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2614 | /* 6167 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2615 | /* 6169 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2616 | /* 6173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2617 | /* 6176 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2618 | /* 6179 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2619 | /* 6185 */ GIR_RootConstrainSelectedInstOperands, |
| 2620 | /* 6186 */ // GIR_Coverage, 2200, |
| 2621 | /* 6186 */ GIR_EraseRootFromParent_Done, |
| 2622 | /* 6187 */ // Label 182: @6187 |
| 2623 | /* 6187 */ GIM_Reject, |
| 2624 | /* 6188 */ // Label 180: @6188 |
| 2625 | /* 6188 */ GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(6326), |
| 2626 | /* 6193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2627 | /* 6197 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2628 | /* 6201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 184*/ GIMT_Encode4(6263), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2443 // |
| 2629 | /* 6208 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2630 | /* 6212 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2631 | /* 6216 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2632 | /* 6220 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2633 | /* 6225 */ // MIs[1] Operand 2 |
| 2634 | /* 6225 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2635 | /* 6236 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2636 | /* 6238 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2637 | /* 6238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB), |
| 2638 | /* 6241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2639 | /* 6243 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2640 | /* 6245 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2641 | /* 6249 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2642 | /* 6252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2643 | /* 6255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2644 | /* 6261 */ GIR_RootConstrainSelectedInstOperands, |
| 2645 | /* 6262 */ // GIR_Coverage, 2443, |
| 2646 | /* 6262 */ GIR_EraseRootFromParent_Done, |
| 2647 | /* 6263 */ // Label 184: @6263 |
| 2648 | /* 6263 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 185*/ GIMT_Encode4(6325), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2444 // |
| 2649 | /* 6270 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2650 | /* 6274 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2651 | /* 6278 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2652 | /* 6282 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2653 | /* 6287 */ // MIs[1] Operand 2 |
| 2654 | /* 6287 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2655 | /* 6298 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2656 | /* 6300 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2657 | /* 6300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 2658 | /* 6303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2659 | /* 6305 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2660 | /* 6307 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2661 | /* 6311 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2662 | /* 6314 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2663 | /* 6317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2664 | /* 6323 */ GIR_RootConstrainSelectedInstOperands, |
| 2665 | /* 6324 */ // GIR_Coverage, 2444, |
| 2666 | /* 6324 */ GIR_EraseRootFromParent_Done, |
| 2667 | /* 6325 */ // Label 185: @6325 |
| 2668 | /* 6325 */ GIM_Reject, |
| 2669 | /* 6326 */ // Label 183: @6326 |
| 2670 | /* 6326 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 186*/ GIMT_Encode4(6395), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 5980 // |
| 2671 | /* 6333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2672 | /* 6337 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2673 | /* 6341 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2674 | /* 6345 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2675 | /* 6349 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2676 | /* 6353 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2677 | /* 6357 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2678 | /* 6362 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2679 | /* 6367 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2680 | /* 6369 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 2681 | /* 6369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA), |
| 2682 | /* 6372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2683 | /* 6374 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2684 | /* 6378 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2685 | /* 6382 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2686 | /* 6384 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2687 | /* 6387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2688 | /* 6393 */ GIR_RootConstrainSelectedInstOperands, |
| 2689 | /* 6394 */ // GIR_Coverage, 5980, |
| 2690 | /* 6394 */ GIR_EraseRootFromParent_Done, |
| 2691 | /* 6395 */ // Label 186: @6395 |
| 2692 | /* 6395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 187*/ GIMT_Encode4(6464), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6015 // |
| 2693 | /* 6402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2694 | /* 6406 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2695 | /* 6410 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2696 | /* 6414 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2697 | /* 6418 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2698 | /* 6422 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2699 | /* 6426 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2700 | /* 6431 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2701 | /* 6436 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2702 | /* 6438 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2703 | /* 6438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA), |
| 2704 | /* 6441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2705 | /* 6443 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2706 | /* 6447 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2707 | /* 6451 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2708 | /* 6453 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2709 | /* 6456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2710 | /* 6462 */ GIR_RootConstrainSelectedInstOperands, |
| 2711 | /* 6463 */ // GIR_Coverage, 6015, |
| 2712 | /* 6463 */ GIR_EraseRootFromParent_Done, |
| 2713 | /* 6464 */ // Label 187: @6464 |
| 2714 | /* 6464 */ GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(6640), |
| 2715 | /* 6469 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2716 | /* 6473 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2717 | /* 6477 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 189*/ GIMT_Encode4(6531), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6562 // |
| 2718 | /* 6484 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2719 | /* 6488 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2720 | /* 6492 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2721 | /* 6496 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2722 | /* 6501 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2723 | /* 6503 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec)) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec) |
| 2724 | /* 6503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc), |
| 2725 | /* 6506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2726 | /* 6508 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc |
| 2727 | /* 6510 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2728 | /* 6514 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2729 | /* 6517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2730 | /* 6523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2731 | /* 6529 */ GIR_RootConstrainSelectedInstOperands, |
| 2732 | /* 6530 */ // GIR_Coverage, 6562, |
| 2733 | /* 6530 */ GIR_EraseRootFromParent_Done, |
| 2734 | /* 6531 */ // Label 189: @6531 |
| 2735 | /* 6531 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 190*/ GIMT_Encode4(6585), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6576 // |
| 2736 | /* 6538 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2737 | /* 6542 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2738 | /* 6546 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2739 | /* 6550 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2740 | /* 6555 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2741 | /* 6557 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec)) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec) |
| 2742 | /* 6557 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc), |
| 2743 | /* 6560 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2744 | /* 6562 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc |
| 2745 | /* 6564 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2746 | /* 6568 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2747 | /* 6571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2748 | /* 6577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2749 | /* 6583 */ GIR_RootConstrainSelectedInstOperands, |
| 2750 | /* 6584 */ // GIR_Coverage, 6576, |
| 2751 | /* 6584 */ GIR_EraseRootFromParent_Done, |
| 2752 | /* 6585 */ // Label 190: @6585 |
| 2753 | /* 6585 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 191*/ GIMT_Encode4(6639), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6581 // |
| 2754 | /* 6592 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2755 | /* 6596 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2756 | /* 6600 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2757 | /* 6604 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2758 | /* 6609 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2759 | /* 6611 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec)) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec) |
| 2760 | /* 6611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc), |
| 2761 | /* 6614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2762 | /* 6616 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc |
| 2763 | /* 6618 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2764 | /* 6622 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2765 | /* 6625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2766 | /* 6631 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2767 | /* 6637 */ GIR_RootConstrainSelectedInstOperands, |
| 2768 | /* 6638 */ // GIR_Coverage, 6581, |
| 2769 | /* 6638 */ GIR_EraseRootFromParent_Done, |
| 2770 | /* 6639 */ // Label 191: @6639 |
| 2771 | /* 6639 */ GIM_Reject, |
| 2772 | /* 6640 */ // Label 188: @6640 |
| 2773 | /* 6640 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 192*/ GIMT_Encode4(6685), GIMT_Encode2(GIFBS_IsARM), // Rule ID 72 // |
| 2774 | /* 6647 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2775 | /* 6651 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2776 | /* 6655 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2777 | /* 6659 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 2778 | /* 6659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDrr), |
| 2779 | /* 6662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2780 | /* 6664 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2781 | /* 6666 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 2782 | /* 6668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2783 | /* 6671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2784 | /* 6677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2785 | /* 6683 */ GIR_RootConstrainSelectedInstOperands, |
| 2786 | /* 6684 */ // GIR_Coverage, 72, |
| 2787 | /* 6684 */ GIR_EraseRootFromParent_Done, |
| 2788 | /* 6685 */ // Label 192: @6685 |
| 2789 | /* 6685 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 193*/ GIMT_Encode4(6730), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 304 // |
| 2790 | /* 6692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2791 | /* 6696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2792 | /* 6700 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2793 | /* 6704 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tADDrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 2794 | /* 6704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDrr), |
| 2795 | /* 6707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2796 | /* 6709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 2797 | /* 6715 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2798 | /* 6717 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 2799 | /* 6719 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2800 | /* 6722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2801 | /* 6728 */ GIR_RootConstrainSelectedInstOperands, |
| 2802 | /* 6729 */ // GIR_Coverage, 304, |
| 2803 | /* 6729 */ GIR_EraseRootFromParent_Done, |
| 2804 | /* 6730 */ // Label 193: @6730 |
| 2805 | /* 6730 */ GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(6822), |
| 2806 | /* 6735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2807 | /* 6739 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 195*/ GIMT_Encode4(6780), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 408 // |
| 2808 | /* 6746 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2809 | /* 6750 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2810 | /* 6754 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 2811 | /* 6754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr), |
| 2812 | /* 6757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2813 | /* 6759 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2814 | /* 6761 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 2815 | /* 6763 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2816 | /* 6766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2817 | /* 6772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2818 | /* 6778 */ GIR_RootConstrainSelectedInstOperands, |
| 2819 | /* 6779 */ // GIR_Coverage, 408, |
| 2820 | /* 6779 */ GIR_EraseRootFromParent_Done, |
| 2821 | /* 6780 */ // Label 195: @6780 |
| 2822 | /* 6780 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 196*/ GIMT_Encode4(6821), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 5996 // |
| 2823 | /* 6787 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2824 | /* 6791 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2825 | /* 6795 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 2826 | /* 6795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr), |
| 2827 | /* 6798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2828 | /* 6800 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2829 | /* 6802 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 2830 | /* 6804 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2831 | /* 6807 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2832 | /* 6813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2833 | /* 6819 */ GIR_RootConstrainSelectedInstOperands, |
| 2834 | /* 6820 */ // GIR_Coverage, 5996, |
| 2835 | /* 6820 */ GIR_EraseRootFromParent_Done, |
| 2836 | /* 6821 */ // Label 196: @6821 |
| 2837 | /* 6821 */ GIM_Reject, |
| 2838 | /* 6822 */ // Label 194: @6822 |
| 2839 | /* 6822 */ GIM_Reject, |
| 2840 | /* 6823 */ // Label 105: @6823 |
| 2841 | /* 6823 */ GIM_Reject, |
| 2842 | /* 6824 */ // Label 96: @6824 |
| 2843 | /* 6824 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 197*/ GIMT_Encode4(6869), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 882 // |
| 2844 | /* 6831 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 2845 | /* 6834 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 2846 | /* 6837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2847 | /* 6841 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2848 | /* 6845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2849 | /* 6849 */ // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 2850 | /* 6849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv1i64), |
| 2851 | /* 6852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2852 | /* 6854 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2853 | /* 6856 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 2854 | /* 6858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2855 | /* 6861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2856 | /* 6867 */ GIR_RootConstrainSelectedInstOperands, |
| 2857 | /* 6868 */ // GIR_Coverage, 882, |
| 2858 | /* 6868 */ GIR_EraseRootFromParent_Done, |
| 2859 | /* 6869 */ // Label 197: @6869 |
| 2860 | /* 6869 */ GIM_Reject, |
| 2861 | /* 6870 */ // Label 97: @6870 |
| 2862 | /* 6870 */ GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(7303), |
| 2863 | /* 6875 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2864 | /* 6878 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2865 | /* 6881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2866 | /* 6885 */ GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(7078), |
| 2867 | /* 6890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2868 | /* 6894 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 200*/ GIMT_Encode4(6955), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6200 // |
| 2869 | /* 6901 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2870 | /* 6905 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 2871 | /* 6909 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2872 | /* 6913 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2873 | /* 6917 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2874 | /* 6922 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2875 | /* 6927 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2876 | /* 6929 */ // (add:{ *:[v8i8] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2877 | /* 6929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8), |
| 2878 | /* 6932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2879 | /* 6934 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2880 | /* 6936 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2881 | /* 6940 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2882 | /* 6944 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2883 | /* 6947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2884 | /* 6953 */ GIR_RootConstrainSelectedInstOperands, |
| 2885 | /* 6954 */ // GIR_Coverage, 6200, |
| 2886 | /* 6954 */ GIR_EraseRootFromParent_Done, |
| 2887 | /* 6955 */ // Label 200: @6955 |
| 2888 | /* 6955 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 201*/ GIMT_Encode4(7016), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6206 // |
| 2889 | /* 6962 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2890 | /* 6966 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 2891 | /* 6970 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2892 | /* 6974 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2893 | /* 6978 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2894 | /* 6983 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2895 | /* 6988 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2896 | /* 6990 */ // (add:{ *:[v8i8] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2897 | /* 6990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8), |
| 2898 | /* 6993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2899 | /* 6995 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2900 | /* 6997 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2901 | /* 7001 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2902 | /* 7005 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2903 | /* 7008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2904 | /* 7014 */ GIR_RootConstrainSelectedInstOperands, |
| 2905 | /* 7015 */ // GIR_Coverage, 6206, |
| 2906 | /* 7015 */ GIR_EraseRootFromParent_Done, |
| 2907 | /* 7016 */ // Label 201: @7016 |
| 2908 | /* 7016 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 202*/ GIMT_Encode4(7077), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6088 // |
| 2909 | /* 7023 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2910 | /* 7027 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2911 | /* 7031 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2912 | /* 7035 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2913 | /* 7039 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2914 | /* 7044 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2915 | /* 7049 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2916 | /* 7051 */ // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2917 | /* 7051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8), |
| 2918 | /* 7054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2919 | /* 7056 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2920 | /* 7058 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2921 | /* 7062 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2922 | /* 7066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2923 | /* 7069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2924 | /* 7075 */ GIR_RootConstrainSelectedInstOperands, |
| 2925 | /* 7076 */ // GIR_Coverage, 6088, |
| 2926 | /* 7076 */ GIR_EraseRootFromParent_Done, |
| 2927 | /* 7077 */ // Label 202: @7077 |
| 2928 | /* 7077 */ GIM_Reject, |
| 2929 | /* 7078 */ // Label 199: @7078 |
| 2930 | /* 7078 */ GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(7302), |
| 2931 | /* 7083 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2932 | /* 7087 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 204*/ GIMT_Encode4(7148), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1341 // |
| 2933 | /* 7094 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2934 | /* 7098 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 2935 | /* 7102 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2936 | /* 7106 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2937 | /* 7110 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2938 | /* 7115 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2939 | /* 7120 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2940 | /* 7122 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2941 | /* 7122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8), |
| 2942 | /* 7125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2943 | /* 7127 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2944 | /* 7129 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2945 | /* 7133 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2946 | /* 7137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2947 | /* 7140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2948 | /* 7146 */ GIR_RootConstrainSelectedInstOperands, |
| 2949 | /* 7147 */ // GIR_Coverage, 1341, |
| 2950 | /* 7147 */ GIR_EraseRootFromParent_Done, |
| 2951 | /* 7148 */ // Label 204: @7148 |
| 2952 | /* 7148 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 205*/ GIMT_Encode4(7209), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1347 // |
| 2953 | /* 7155 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2954 | /* 7159 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 2955 | /* 7163 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2956 | /* 7167 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2957 | /* 7171 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2958 | /* 7176 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2959 | /* 7181 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2960 | /* 7183 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2961 | /* 7183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8), |
| 2962 | /* 7186 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2963 | /* 7188 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2964 | /* 7190 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2965 | /* 7194 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2966 | /* 7198 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2967 | /* 7201 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2968 | /* 7207 */ GIR_RootConstrainSelectedInstOperands, |
| 2969 | /* 7208 */ // GIR_Coverage, 1347, |
| 2970 | /* 7208 */ GIR_EraseRootFromParent_Done, |
| 2971 | /* 7209 */ // Label 205: @7209 |
| 2972 | /* 7209 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 206*/ GIMT_Encode4(7270), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1007 // |
| 2973 | /* 7216 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2974 | /* 7220 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2975 | /* 7224 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2976 | /* 7228 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2977 | /* 7232 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2978 | /* 7237 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2979 | /* 7242 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2980 | /* 7244 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2981 | /* 7244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8), |
| 2982 | /* 7247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2983 | /* 7249 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2984 | /* 7251 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2985 | /* 7255 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2986 | /* 7259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2987 | /* 7262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2988 | /* 7268 */ GIR_RootConstrainSelectedInstOperands, |
| 2989 | /* 7269 */ // GIR_Coverage, 1007, |
| 2990 | /* 7269 */ GIR_EraseRootFromParent_Done, |
| 2991 | /* 7270 */ // Label 206: @7270 |
| 2992 | /* 7270 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 207*/ GIMT_Encode4(7301), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 876 // |
| 2993 | /* 7277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2994 | /* 7281 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2995 | /* 7281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i8), |
| 2996 | /* 7284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2997 | /* 7286 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2998 | /* 7288 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 2999 | /* 7290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3000 | /* 7293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3001 | /* 7299 */ GIR_RootConstrainSelectedInstOperands, |
| 3002 | /* 7300 */ // GIR_Coverage, 876, |
| 3003 | /* 7300 */ GIR_EraseRootFromParent_Done, |
| 3004 | /* 7301 */ // Label 207: @7301 |
| 3005 | /* 7301 */ GIM_Reject, |
| 3006 | /* 7302 */ // Label 203: @7302 |
| 3007 | /* 7302 */ GIM_Reject, |
| 3008 | /* 7303 */ // Label 198: @7303 |
| 3009 | /* 7303 */ GIM_Reject, |
| 3010 | /* 7304 */ // Label 98: @7304 |
| 3011 | /* 7304 */ GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(7803), |
| 3012 | /* 7309 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3013 | /* 7312 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3014 | /* 7315 */ GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(7742), |
| 3015 | /* 7320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3016 | /* 7324 */ GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(7517), |
| 3017 | /* 7329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3018 | /* 7333 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 211*/ GIMT_Encode4(7394), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6203 // |
| 3019 | /* 7340 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3020 | /* 7344 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3021 | /* 7348 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3022 | /* 7352 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3023 | /* 7356 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3024 | /* 7361 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3025 | /* 7366 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3026 | /* 7368 */ // (add:{ *:[v16i8] } (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3027 | /* 7368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8), |
| 3028 | /* 7371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3029 | /* 7373 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3030 | /* 7375 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3031 | /* 7379 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3032 | /* 7383 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3033 | /* 7386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3034 | /* 7392 */ GIR_RootConstrainSelectedInstOperands, |
| 3035 | /* 7393 */ // GIR_Coverage, 6203, |
| 3036 | /* 7393 */ GIR_EraseRootFromParent_Done, |
| 3037 | /* 7394 */ // Label 211: @7394 |
| 3038 | /* 7394 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 212*/ GIMT_Encode4(7455), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6209 // |
| 3039 | /* 7401 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3040 | /* 7405 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3041 | /* 7409 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3042 | /* 7413 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3043 | /* 7417 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3044 | /* 7422 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3045 | /* 7427 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3046 | /* 7429 */ // (add:{ *:[v16i8] } (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3047 | /* 7429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8), |
| 3048 | /* 7432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3049 | /* 7434 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3050 | /* 7436 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3051 | /* 7440 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3052 | /* 7444 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3053 | /* 7447 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3054 | /* 7453 */ GIR_RootConstrainSelectedInstOperands, |
| 3055 | /* 7454 */ // GIR_Coverage, 6209, |
| 3056 | /* 7454 */ GIR_EraseRootFromParent_Done, |
| 3057 | /* 7455 */ // Label 212: @7455 |
| 3058 | /* 7455 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 213*/ GIMT_Encode4(7516), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6091 // |
| 3059 | /* 7462 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3060 | /* 7466 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3061 | /* 7470 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3062 | /* 7474 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3063 | /* 7478 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3064 | /* 7483 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3065 | /* 7488 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3066 | /* 7490 */ // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3067 | /* 7490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8), |
| 3068 | /* 7493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3069 | /* 7495 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3070 | /* 7497 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3071 | /* 7501 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3072 | /* 7505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3073 | /* 7508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3074 | /* 7514 */ GIR_RootConstrainSelectedInstOperands, |
| 3075 | /* 7515 */ // GIR_Coverage, 6091, |
| 3076 | /* 7515 */ GIR_EraseRootFromParent_Done, |
| 3077 | /* 7516 */ // Label 213: @7516 |
| 3078 | /* 7516 */ GIM_Reject, |
| 3079 | /* 7517 */ // Label 210: @7517 |
| 3080 | /* 7517 */ GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(7741), |
| 3081 | /* 7522 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3082 | /* 7526 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 215*/ GIMT_Encode4(7587), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1344 // |
| 3083 | /* 7533 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3084 | /* 7537 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3085 | /* 7541 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3086 | /* 7545 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3087 | /* 7549 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3088 | /* 7554 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3089 | /* 7559 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3090 | /* 7561 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3091 | /* 7561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8), |
| 3092 | /* 7564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3093 | /* 7566 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3094 | /* 7568 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3095 | /* 7572 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3096 | /* 7576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3097 | /* 7579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3098 | /* 7585 */ GIR_RootConstrainSelectedInstOperands, |
| 3099 | /* 7586 */ // GIR_Coverage, 1344, |
| 3100 | /* 7586 */ GIR_EraseRootFromParent_Done, |
| 3101 | /* 7587 */ // Label 215: @7587 |
| 3102 | /* 7587 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 216*/ GIMT_Encode4(7648), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1350 // |
| 3103 | /* 7594 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3104 | /* 7598 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3105 | /* 7602 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3106 | /* 7606 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3107 | /* 7610 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3108 | /* 7615 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3109 | /* 7620 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3110 | /* 7622 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3111 | /* 7622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8), |
| 3112 | /* 7625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3113 | /* 7627 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3114 | /* 7629 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3115 | /* 7633 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3116 | /* 7637 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3117 | /* 7640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3118 | /* 7646 */ GIR_RootConstrainSelectedInstOperands, |
| 3119 | /* 7647 */ // GIR_Coverage, 1350, |
| 3120 | /* 7647 */ GIR_EraseRootFromParent_Done, |
| 3121 | /* 7648 */ // Label 216: @7648 |
| 3122 | /* 7648 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 217*/ GIMT_Encode4(7709), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1010 // |
| 3123 | /* 7655 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3124 | /* 7659 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3125 | /* 7663 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3126 | /* 7667 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3127 | /* 7671 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3128 | /* 7676 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3129 | /* 7681 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3130 | /* 7683 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3131 | /* 7683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8), |
| 3132 | /* 7686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3133 | /* 7688 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3134 | /* 7690 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3135 | /* 7694 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3136 | /* 7698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3137 | /* 7701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3138 | /* 7707 */ GIR_RootConstrainSelectedInstOperands, |
| 3139 | /* 7708 */ // GIR_Coverage, 1010, |
| 3140 | /* 7708 */ GIR_EraseRootFromParent_Done, |
| 3141 | /* 7709 */ // Label 217: @7709 |
| 3142 | /* 7709 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 218*/ GIMT_Encode4(7740), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 879 // |
| 3143 | /* 7716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3144 | /* 7720 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3145 | /* 7720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv16i8), |
| 3146 | /* 7723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3147 | /* 7725 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3148 | /* 7727 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3149 | /* 7729 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3150 | /* 7732 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3151 | /* 7738 */ GIR_RootConstrainSelectedInstOperands, |
| 3152 | /* 7739 */ // GIR_Coverage, 879, |
| 3153 | /* 7739 */ GIR_EraseRootFromParent_Done, |
| 3154 | /* 7740 */ // Label 218: @7740 |
| 3155 | /* 7740 */ GIM_Reject, |
| 3156 | /* 7741 */ // Label 214: @7741 |
| 3157 | /* 7741 */ GIM_Reject, |
| 3158 | /* 7742 */ // Label 209: @7742 |
| 3159 | /* 7742 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 219*/ GIMT_Encode4(7802), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3885 // |
| 3160 | /* 7749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3161 | /* 7753 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3162 | /* 7757 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3163 | /* 7761 */ // (add:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 3164 | /* 7761 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3165 | /* 7764 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3166 | /* 7768 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 3167 | /* 7773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi8), |
| 3168 | /* 7776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 3169 | /* 7778 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 3170 | /* 7780 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 3171 | /* 7782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3172 | /* 7785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3173 | /* 7791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3174 | /* 7797 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3175 | /* 7800 */ GIR_RootConstrainSelectedInstOperands, |
| 3176 | /* 7801 */ // GIR_Coverage, 3885, |
| 3177 | /* 7801 */ GIR_EraseRootFromParent_Done, |
| 3178 | /* 7802 */ // Label 219: @7802 |
| 3179 | /* 7802 */ GIM_Reject, |
| 3180 | /* 7803 */ // Label 208: @7803 |
| 3181 | /* 7803 */ GIM_Reject, |
| 3182 | /* 7804 */ // Label 99: @7804 |
| 3183 | /* 7804 */ GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(8237), |
| 3184 | /* 7809 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3185 | /* 7812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3186 | /* 7815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3187 | /* 7819 */ GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(8012), |
| 3188 | /* 7824 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3189 | /* 7828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 222*/ GIMT_Encode4(7889), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6201 // |
| 3190 | /* 7835 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3191 | /* 7839 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3192 | /* 7843 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3193 | /* 7847 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3194 | /* 7851 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3195 | /* 7856 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3196 | /* 7861 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3197 | /* 7863 */ // (add:{ *:[v4i16] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3198 | /* 7863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16), |
| 3199 | /* 7866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3200 | /* 7868 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3201 | /* 7870 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3202 | /* 7874 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3203 | /* 7878 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3204 | /* 7881 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3205 | /* 7887 */ GIR_RootConstrainSelectedInstOperands, |
| 3206 | /* 7888 */ // GIR_Coverage, 6201, |
| 3207 | /* 7888 */ GIR_EraseRootFromParent_Done, |
| 3208 | /* 7889 */ // Label 222: @7889 |
| 3209 | /* 7889 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 223*/ GIMT_Encode4(7950), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6207 // |
| 3210 | /* 7896 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3211 | /* 7900 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3212 | /* 7904 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3213 | /* 7908 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3214 | /* 7912 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3215 | /* 7917 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3216 | /* 7922 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3217 | /* 7924 */ // (add:{ *:[v4i16] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3218 | /* 7924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16), |
| 3219 | /* 7927 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3220 | /* 7929 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3221 | /* 7931 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3222 | /* 7935 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3223 | /* 7939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3224 | /* 7942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3225 | /* 7948 */ GIR_RootConstrainSelectedInstOperands, |
| 3226 | /* 7949 */ // GIR_Coverage, 6207, |
| 3227 | /* 7949 */ GIR_EraseRootFromParent_Done, |
| 3228 | /* 7950 */ // Label 223: @7950 |
| 3229 | /* 7950 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 224*/ GIMT_Encode4(8011), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6089 // |
| 3230 | /* 7957 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3231 | /* 7961 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3232 | /* 7965 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3233 | /* 7969 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3234 | /* 7973 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3235 | /* 7978 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3236 | /* 7983 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3237 | /* 7985 */ // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3238 | /* 7985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16), |
| 3239 | /* 7988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3240 | /* 7990 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3241 | /* 7992 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3242 | /* 7996 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3243 | /* 8000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3244 | /* 8003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3245 | /* 8009 */ GIR_RootConstrainSelectedInstOperands, |
| 3246 | /* 8010 */ // GIR_Coverage, 6089, |
| 3247 | /* 8010 */ GIR_EraseRootFromParent_Done, |
| 3248 | /* 8011 */ // Label 224: @8011 |
| 3249 | /* 8011 */ GIM_Reject, |
| 3250 | /* 8012 */ // Label 221: @8012 |
| 3251 | /* 8012 */ GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(8236), |
| 3252 | /* 8017 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3253 | /* 8021 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 226*/ GIMT_Encode4(8082), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1342 // |
| 3254 | /* 8028 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3255 | /* 8032 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3256 | /* 8036 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3257 | /* 8040 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3258 | /* 8044 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3259 | /* 8049 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3260 | /* 8054 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3261 | /* 8056 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3262 | /* 8056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16), |
| 3263 | /* 8059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3264 | /* 8061 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3265 | /* 8063 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3266 | /* 8067 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3267 | /* 8071 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3268 | /* 8074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3269 | /* 8080 */ GIR_RootConstrainSelectedInstOperands, |
| 3270 | /* 8081 */ // GIR_Coverage, 1342, |
| 3271 | /* 8081 */ GIR_EraseRootFromParent_Done, |
| 3272 | /* 8082 */ // Label 226: @8082 |
| 3273 | /* 8082 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 227*/ GIMT_Encode4(8143), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1348 // |
| 3274 | /* 8089 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3275 | /* 8093 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3276 | /* 8097 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3277 | /* 8101 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3278 | /* 8105 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3279 | /* 8110 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3280 | /* 8115 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3281 | /* 8117 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3282 | /* 8117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16), |
| 3283 | /* 8120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3284 | /* 8122 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3285 | /* 8124 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3286 | /* 8128 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3287 | /* 8132 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3288 | /* 8135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3289 | /* 8141 */ GIR_RootConstrainSelectedInstOperands, |
| 3290 | /* 8142 */ // GIR_Coverage, 1348, |
| 3291 | /* 8142 */ GIR_EraseRootFromParent_Done, |
| 3292 | /* 8143 */ // Label 227: @8143 |
| 3293 | /* 8143 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 228*/ GIMT_Encode4(8204), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1008 // |
| 3294 | /* 8150 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3295 | /* 8154 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3296 | /* 8158 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3297 | /* 8162 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3298 | /* 8166 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3299 | /* 8171 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3300 | /* 8176 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3301 | /* 8178 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3302 | /* 8178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16), |
| 3303 | /* 8181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3304 | /* 8183 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3305 | /* 8185 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3306 | /* 8189 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3307 | /* 8193 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3308 | /* 8196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3309 | /* 8202 */ GIR_RootConstrainSelectedInstOperands, |
| 3310 | /* 8203 */ // GIR_Coverage, 1008, |
| 3311 | /* 8203 */ GIR_EraseRootFromParent_Done, |
| 3312 | /* 8204 */ // Label 228: @8204 |
| 3313 | /* 8204 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 229*/ GIMT_Encode4(8235), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 877 // |
| 3314 | /* 8211 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3315 | /* 8215 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3316 | /* 8215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i16), |
| 3317 | /* 8218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3318 | /* 8220 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3319 | /* 8222 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3320 | /* 8224 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3321 | /* 8227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3322 | /* 8233 */ GIR_RootConstrainSelectedInstOperands, |
| 3323 | /* 8234 */ // GIR_Coverage, 877, |
| 3324 | /* 8234 */ GIR_EraseRootFromParent_Done, |
| 3325 | /* 8235 */ // Label 229: @8235 |
| 3326 | /* 8235 */ GIM_Reject, |
| 3327 | /* 8236 */ // Label 225: @8236 |
| 3328 | /* 8236 */ GIM_Reject, |
| 3329 | /* 8237 */ // Label 220: @8237 |
| 3330 | /* 8237 */ GIM_Reject, |
| 3331 | /* 8238 */ // Label 100: @8238 |
| 3332 | /* 8238 */ GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(9672), |
| 3333 | /* 8243 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3334 | /* 8246 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3335 | /* 8249 */ GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(9611), |
| 3336 | /* 8254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3337 | /* 8258 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 232*/ GIMT_Encode4(8325), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 894 // |
| 3338 | /* 8265 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3339 | /* 8269 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3340 | /* 8273 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3341 | /* 8277 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3342 | /* 8282 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3343 | /* 8286 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3344 | /* 8290 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3345 | /* 8294 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3346 | /* 8299 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3347 | /* 8301 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3348 | /* 8301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 3349 | /* 8304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3350 | /* 8306 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3351 | /* 8310 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3352 | /* 8314 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3353 | /* 8317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3354 | /* 8323 */ GIR_RootConstrainSelectedInstOperands, |
| 3355 | /* 8324 */ // GIR_Coverage, 894, |
| 3356 | /* 8324 */ GIR_EraseRootFromParent_Done, |
| 3357 | /* 8325 */ // Label 232: @8325 |
| 3358 | /* 8325 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 233*/ GIMT_Encode4(8392), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 893 // |
| 3359 | /* 8332 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3360 | /* 8336 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3361 | /* 8340 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3362 | /* 8344 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3363 | /* 8349 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3364 | /* 8353 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3365 | /* 8357 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3366 | /* 8361 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3367 | /* 8366 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3368 | /* 8368 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3369 | /* 8368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 3370 | /* 8371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3371 | /* 8373 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3372 | /* 8377 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3373 | /* 8381 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3374 | /* 8384 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3375 | /* 8390 */ GIR_RootConstrainSelectedInstOperands, |
| 3376 | /* 8391 */ // GIR_Coverage, 893, |
| 3377 | /* 8391 */ GIR_EraseRootFromParent_Done, |
| 3378 | /* 8392 */ // Label 233: @8392 |
| 3379 | /* 8392 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 234*/ GIMT_Encode4(8459), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 888 // |
| 3380 | /* 8399 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3381 | /* 8403 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3382 | /* 8407 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3383 | /* 8411 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3384 | /* 8416 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3385 | /* 8420 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3386 | /* 8424 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3387 | /* 8428 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3388 | /* 8433 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3389 | /* 8435 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3390 | /* 8435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv8i16), |
| 3391 | /* 8438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3392 | /* 8440 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3393 | /* 8444 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3394 | /* 8448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3395 | /* 8451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3396 | /* 8457 */ GIR_RootConstrainSelectedInstOperands, |
| 3397 | /* 8458 */ // GIR_Coverage, 888, |
| 3398 | /* 8458 */ GIR_EraseRootFromParent_Done, |
| 3399 | /* 8459 */ // Label 234: @8459 |
| 3400 | /* 8459 */ GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(8615), |
| 3401 | /* 8464 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3402 | /* 8468 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 236*/ GIMT_Encode4(8541), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6212 // |
| 3403 | /* 8475 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3404 | /* 8479 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3405 | /* 8483 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3406 | /* 8487 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3407 | /* 8491 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3408 | /* 8495 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3409 | /* 8499 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3410 | /* 8503 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3411 | /* 8508 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3412 | /* 8513 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3413 | /* 8515 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3414 | /* 8515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16), |
| 3415 | /* 8518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3416 | /* 8520 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3417 | /* 8522 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3418 | /* 8526 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3419 | /* 8530 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3420 | /* 8533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3421 | /* 8539 */ GIR_RootConstrainSelectedInstOperands, |
| 3422 | /* 8540 */ // GIR_Coverage, 6212, |
| 3423 | /* 8540 */ GIR_EraseRootFromParent_Done, |
| 3424 | /* 8541 */ // Label 236: @8541 |
| 3425 | /* 8541 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 237*/ GIMT_Encode4(8614), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6215 // |
| 3426 | /* 8548 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3427 | /* 8552 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3428 | /* 8556 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3429 | /* 8560 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3430 | /* 8564 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3431 | /* 8568 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3432 | /* 8572 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3433 | /* 8576 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3434 | /* 8581 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3435 | /* 8586 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3436 | /* 8588 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3437 | /* 8588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16), |
| 3438 | /* 8591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3439 | /* 8593 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3440 | /* 8595 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3441 | /* 8599 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3442 | /* 8603 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3443 | /* 8606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3444 | /* 8612 */ GIR_RootConstrainSelectedInstOperands, |
| 3445 | /* 8613 */ // GIR_Coverage, 6215, |
| 3446 | /* 8613 */ GIR_EraseRootFromParent_Done, |
| 3447 | /* 8614 */ // Label 237: @8614 |
| 3448 | /* 8614 */ GIM_Reject, |
| 3449 | /* 8615 */ // Label 235: @8615 |
| 3450 | /* 8615 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 238*/ GIMT_Encode4(8682), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 892 // |
| 3451 | /* 8622 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3452 | /* 8626 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3453 | /* 8630 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3454 | /* 8634 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3455 | /* 8639 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3456 | /* 8643 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3457 | /* 8647 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3458 | /* 8651 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3459 | /* 8656 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3460 | /* 8658 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3461 | /* 8658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 3462 | /* 8661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3463 | /* 8663 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3464 | /* 8667 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3465 | /* 8671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3466 | /* 8674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3467 | /* 8680 */ GIR_RootConstrainSelectedInstOperands, |
| 3468 | /* 8681 */ // GIR_Coverage, 892, |
| 3469 | /* 8681 */ GIR_EraseRootFromParent_Done, |
| 3470 | /* 8682 */ // Label 238: @8682 |
| 3471 | /* 8682 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 239*/ GIMT_Encode4(8749), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 891 // |
| 3472 | /* 8689 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3473 | /* 8693 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3474 | /* 8697 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3475 | /* 8701 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3476 | /* 8706 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3477 | /* 8710 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3478 | /* 8714 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3479 | /* 8718 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3480 | /* 8723 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3481 | /* 8725 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3482 | /* 8725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 3483 | /* 8728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3484 | /* 8730 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3485 | /* 8734 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3486 | /* 8738 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3487 | /* 8741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3488 | /* 8747 */ GIR_RootConstrainSelectedInstOperands, |
| 3489 | /* 8748 */ // GIR_Coverage, 891, |
| 3490 | /* 8748 */ GIR_EraseRootFromParent_Done, |
| 3491 | /* 8749 */ // Label 239: @8749 |
| 3492 | /* 8749 */ GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(8905), |
| 3493 | /* 8754 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3494 | /* 8758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 241*/ GIMT_Encode4(8831), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1353 // |
| 3495 | /* 8765 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3496 | /* 8769 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3497 | /* 8773 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3498 | /* 8777 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3499 | /* 8781 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3500 | /* 8785 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3501 | /* 8789 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3502 | /* 8793 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3503 | /* 8798 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3504 | /* 8803 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3505 | /* 8805 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3506 | /* 8805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16), |
| 3507 | /* 8808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3508 | /* 8810 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3509 | /* 8812 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3510 | /* 8816 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3511 | /* 8820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3512 | /* 8823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3513 | /* 8829 */ GIR_RootConstrainSelectedInstOperands, |
| 3514 | /* 8830 */ // GIR_Coverage, 1353, |
| 3515 | /* 8830 */ GIR_EraseRootFromParent_Done, |
| 3516 | /* 8831 */ // Label 241: @8831 |
| 3517 | /* 8831 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 242*/ GIMT_Encode4(8904), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1356 // |
| 3518 | /* 8838 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3519 | /* 8842 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3520 | /* 8846 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3521 | /* 8850 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3522 | /* 8854 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3523 | /* 8858 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3524 | /* 8862 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3525 | /* 8866 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3526 | /* 8871 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3527 | /* 8876 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3528 | /* 8878 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3529 | /* 8878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16), |
| 3530 | /* 8881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3531 | /* 8883 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3532 | /* 8885 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3533 | /* 8889 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3534 | /* 8893 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3535 | /* 8896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3536 | /* 8902 */ GIR_RootConstrainSelectedInstOperands, |
| 3537 | /* 8903 */ // GIR_Coverage, 1356, |
| 3538 | /* 8903 */ GIR_EraseRootFromParent_Done, |
| 3539 | /* 8904 */ // Label 242: @8904 |
| 3540 | /* 8904 */ GIM_Reject, |
| 3541 | /* 8905 */ // Label 240: @8905 |
| 3542 | /* 8905 */ GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(9242), |
| 3543 | /* 8910 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3544 | /* 8914 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 244*/ GIMT_Encode4(8975), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6204 // |
| 3545 | /* 8921 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3546 | /* 8925 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3547 | /* 8929 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3548 | /* 8933 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3549 | /* 8937 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3550 | /* 8942 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3551 | /* 8947 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3552 | /* 8949 */ // (add:{ *:[v8i16] } (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3553 | /* 8949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16), |
| 3554 | /* 8952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3555 | /* 8954 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3556 | /* 8956 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3557 | /* 8960 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3558 | /* 8964 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3559 | /* 8967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3560 | /* 8973 */ GIR_RootConstrainSelectedInstOperands, |
| 3561 | /* 8974 */ // GIR_Coverage, 6204, |
| 3562 | /* 8974 */ GIR_EraseRootFromParent_Done, |
| 3563 | /* 8975 */ // Label 244: @8975 |
| 3564 | /* 8975 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 245*/ GIMT_Encode4(9036), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6210 // |
| 3565 | /* 8982 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3566 | /* 8986 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3567 | /* 8990 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3568 | /* 8994 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3569 | /* 8998 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3570 | /* 9003 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3571 | /* 9008 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3572 | /* 9010 */ // (add:{ *:[v8i16] } (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3573 | /* 9010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16), |
| 3574 | /* 9013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3575 | /* 9015 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3576 | /* 9017 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3577 | /* 9021 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3578 | /* 9025 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3579 | /* 9028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3580 | /* 9034 */ GIR_RootConstrainSelectedInstOperands, |
| 3581 | /* 9035 */ // GIR_Coverage, 6210, |
| 3582 | /* 9035 */ GIR_EraseRootFromParent_Done, |
| 3583 | /* 9036 */ // Label 245: @9036 |
| 3584 | /* 9036 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 246*/ GIMT_Encode4(9097), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6092 // |
| 3585 | /* 9043 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3586 | /* 9047 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3587 | /* 9051 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3588 | /* 9055 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3589 | /* 9059 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3590 | /* 9064 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3591 | /* 9069 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3592 | /* 9071 */ // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3593 | /* 9071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16), |
| 3594 | /* 9074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3595 | /* 9076 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3596 | /* 9078 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3597 | /* 9082 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3598 | /* 9086 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3599 | /* 9089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3600 | /* 9095 */ GIR_RootConstrainSelectedInstOperands, |
| 3601 | /* 9096 */ // GIR_Coverage, 6092, |
| 3602 | /* 9096 */ GIR_EraseRootFromParent_Done, |
| 3603 | /* 9097 */ // Label 246: @9097 |
| 3604 | /* 9097 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 247*/ GIMT_Encode4(9145), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6065 // |
| 3605 | /* 9104 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3606 | /* 9108 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3607 | /* 9112 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3608 | /* 9116 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3609 | /* 9121 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3610 | /* 9123 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3611 | /* 9123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 3612 | /* 9126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3613 | /* 9128 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3614 | /* 9130 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3615 | /* 9134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3616 | /* 9137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3617 | /* 9143 */ GIR_RootConstrainSelectedInstOperands, |
| 3618 | /* 9144 */ // GIR_Coverage, 6065, |
| 3619 | /* 9144 */ GIR_EraseRootFromParent_Done, |
| 3620 | /* 9145 */ // Label 247: @9145 |
| 3621 | /* 9145 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 248*/ GIMT_Encode4(9193), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6061 // |
| 3622 | /* 9152 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3623 | /* 9156 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3624 | /* 9160 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3625 | /* 9164 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3626 | /* 9169 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3627 | /* 9171 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3628 | /* 9171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16), |
| 3629 | /* 9174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3630 | /* 9176 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3631 | /* 9178 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3632 | /* 9182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3633 | /* 9185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3634 | /* 9191 */ GIR_RootConstrainSelectedInstOperands, |
| 3635 | /* 9192 */ // GIR_Coverage, 6061, |
| 3636 | /* 9192 */ GIR_EraseRootFromParent_Done, |
| 3637 | /* 9193 */ // Label 248: @9193 |
| 3638 | /* 9193 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 249*/ GIMT_Encode4(9241), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6064 // |
| 3639 | /* 9200 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3640 | /* 9204 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3641 | /* 9208 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3642 | /* 9212 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3643 | /* 9217 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3644 | /* 9219 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3645 | /* 9219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 3646 | /* 9222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3647 | /* 9224 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3648 | /* 9226 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3649 | /* 9230 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3650 | /* 9233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3651 | /* 9239 */ GIR_RootConstrainSelectedInstOperands, |
| 3652 | /* 9240 */ // GIR_Coverage, 6064, |
| 3653 | /* 9240 */ GIR_EraseRootFromParent_Done, |
| 3654 | /* 9241 */ // Label 249: @9241 |
| 3655 | /* 9241 */ GIM_Reject, |
| 3656 | /* 9242 */ // Label 243: @9242 |
| 3657 | /* 9242 */ GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(9610), |
| 3658 | /* 9247 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3659 | /* 9251 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 251*/ GIMT_Encode4(9312), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1345 // |
| 3660 | /* 9258 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3661 | /* 9262 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3662 | /* 9266 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3663 | /* 9270 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3664 | /* 9274 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3665 | /* 9279 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3666 | /* 9284 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3667 | /* 9286 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3668 | /* 9286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16), |
| 3669 | /* 9289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3670 | /* 9291 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3671 | /* 9293 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3672 | /* 9297 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3673 | /* 9301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3674 | /* 9304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3675 | /* 9310 */ GIR_RootConstrainSelectedInstOperands, |
| 3676 | /* 9311 */ // GIR_Coverage, 1345, |
| 3677 | /* 9311 */ GIR_EraseRootFromParent_Done, |
| 3678 | /* 9312 */ // Label 251: @9312 |
| 3679 | /* 9312 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 252*/ GIMT_Encode4(9373), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1351 // |
| 3680 | /* 9319 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3681 | /* 9323 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3682 | /* 9327 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3683 | /* 9331 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3684 | /* 9335 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3685 | /* 9340 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3686 | /* 9345 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3687 | /* 9347 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3688 | /* 9347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16), |
| 3689 | /* 9350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3690 | /* 9352 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3691 | /* 9354 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3692 | /* 9358 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3693 | /* 9362 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3694 | /* 9365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3695 | /* 9371 */ GIR_RootConstrainSelectedInstOperands, |
| 3696 | /* 9372 */ // GIR_Coverage, 1351, |
| 3697 | /* 9372 */ GIR_EraseRootFromParent_Done, |
| 3698 | /* 9373 */ // Label 252: @9373 |
| 3699 | /* 9373 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 253*/ GIMT_Encode4(9434), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1011 // |
| 3700 | /* 9380 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3701 | /* 9384 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3702 | /* 9388 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3703 | /* 9392 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3704 | /* 9396 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3705 | /* 9401 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3706 | /* 9406 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3707 | /* 9408 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3708 | /* 9408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16), |
| 3709 | /* 9411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3710 | /* 9413 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3711 | /* 9415 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3712 | /* 9419 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3713 | /* 9423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3714 | /* 9426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3715 | /* 9432 */ GIR_RootConstrainSelectedInstOperands, |
| 3716 | /* 9433 */ // GIR_Coverage, 1011, |
| 3717 | /* 9433 */ GIR_EraseRootFromParent_Done, |
| 3718 | /* 9434 */ // Label 253: @9434 |
| 3719 | /* 9434 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 254*/ GIMT_Encode4(9482), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 907 // |
| 3720 | /* 9441 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3721 | /* 9445 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3722 | /* 9449 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3723 | /* 9453 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3724 | /* 9458 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3725 | /* 9460 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3726 | /* 9460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 3727 | /* 9463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3728 | /* 9465 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3729 | /* 9467 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3730 | /* 9471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3731 | /* 9474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3732 | /* 9480 */ GIR_RootConstrainSelectedInstOperands, |
| 3733 | /* 9481 */ // GIR_Coverage, 907, |
| 3734 | /* 9481 */ GIR_EraseRootFromParent_Done, |
| 3735 | /* 9482 */ // Label 254: @9482 |
| 3736 | /* 9482 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 255*/ GIMT_Encode4(9530), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 903 // |
| 3737 | /* 9489 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3738 | /* 9493 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3739 | /* 9497 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3740 | /* 9501 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3741 | /* 9506 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3742 | /* 9508 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3743 | /* 9508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16), |
| 3744 | /* 9511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3745 | /* 9513 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3746 | /* 9515 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3747 | /* 9519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3748 | /* 9522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3749 | /* 9528 */ GIR_RootConstrainSelectedInstOperands, |
| 3750 | /* 9529 */ // GIR_Coverage, 903, |
| 3751 | /* 9529 */ GIR_EraseRootFromParent_Done, |
| 3752 | /* 9530 */ // Label 255: @9530 |
| 3753 | /* 9530 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 256*/ GIMT_Encode4(9578), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 906 // |
| 3754 | /* 9537 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3755 | /* 9541 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3756 | /* 9545 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3757 | /* 9549 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3758 | /* 9554 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3759 | /* 9556 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3760 | /* 9556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 3761 | /* 9559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3762 | /* 9561 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3763 | /* 9563 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3764 | /* 9567 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3765 | /* 9570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3766 | /* 9576 */ GIR_RootConstrainSelectedInstOperands, |
| 3767 | /* 9577 */ // GIR_Coverage, 906, |
| 3768 | /* 9577 */ GIR_EraseRootFromParent_Done, |
| 3769 | /* 9578 */ // Label 256: @9578 |
| 3770 | /* 9578 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 257*/ GIMT_Encode4(9609), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 880 // |
| 3771 | /* 9585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3772 | /* 9589 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3773 | /* 9589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i16), |
| 3774 | /* 9592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3775 | /* 9594 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3776 | /* 9596 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3777 | /* 9598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3778 | /* 9601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3779 | /* 9607 */ GIR_RootConstrainSelectedInstOperands, |
| 3780 | /* 9608 */ // GIR_Coverage, 880, |
| 3781 | /* 9608 */ GIR_EraseRootFromParent_Done, |
| 3782 | /* 9609 */ // Label 257: @9609 |
| 3783 | /* 9609 */ GIM_Reject, |
| 3784 | /* 9610 */ // Label 250: @9610 |
| 3785 | /* 9610 */ GIM_Reject, |
| 3786 | /* 9611 */ // Label 231: @9611 |
| 3787 | /* 9611 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 258*/ GIMT_Encode4(9671), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3889 // |
| 3788 | /* 9618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3789 | /* 9622 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3790 | /* 9626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3791 | /* 9630 */ // (add:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 3792 | /* 9630 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3793 | /* 9633 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3794 | /* 9637 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 3795 | /* 9642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi16), |
| 3796 | /* 9645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 3797 | /* 9647 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 3798 | /* 9649 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 3799 | /* 9651 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3800 | /* 9654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3801 | /* 9660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3802 | /* 9666 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3803 | /* 9669 */ GIR_RootConstrainSelectedInstOperands, |
| 3804 | /* 9670 */ // GIR_Coverage, 3889, |
| 3805 | /* 9670 */ GIR_EraseRootFromParent_Done, |
| 3806 | /* 9671 */ // Label 258: @9671 |
| 3807 | /* 9671 */ GIM_Reject, |
| 3808 | /* 9672 */ // Label 230: @9672 |
| 3809 | /* 9672 */ GIM_Reject, |
| 3810 | /* 9673 */ // Label 101: @9673 |
| 3811 | /* 9673 */ GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(10106), |
| 3812 | /* 9678 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3813 | /* 9681 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3814 | /* 9684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3815 | /* 9688 */ GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(9881), |
| 3816 | /* 9693 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3817 | /* 9697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 261*/ GIMT_Encode4(9758), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6202 // |
| 3818 | /* 9704 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3819 | /* 9708 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3820 | /* 9712 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3821 | /* 9716 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3822 | /* 9720 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3823 | /* 9725 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3824 | /* 9730 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3825 | /* 9732 */ // (add:{ *:[v2i32] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3826 | /* 9732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32), |
| 3827 | /* 9735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3828 | /* 9737 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3829 | /* 9739 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3830 | /* 9743 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3831 | /* 9747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3832 | /* 9750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3833 | /* 9756 */ GIR_RootConstrainSelectedInstOperands, |
| 3834 | /* 9757 */ // GIR_Coverage, 6202, |
| 3835 | /* 9757 */ GIR_EraseRootFromParent_Done, |
| 3836 | /* 9758 */ // Label 261: @9758 |
| 3837 | /* 9758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 262*/ GIMT_Encode4(9819), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6208 // |
| 3838 | /* 9765 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3839 | /* 9769 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3840 | /* 9773 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3841 | /* 9777 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3842 | /* 9781 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3843 | /* 9786 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3844 | /* 9791 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3845 | /* 9793 */ // (add:{ *:[v2i32] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3846 | /* 9793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32), |
| 3847 | /* 9796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3848 | /* 9798 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3849 | /* 9800 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3850 | /* 9804 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3851 | /* 9808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3852 | /* 9811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3853 | /* 9817 */ GIR_RootConstrainSelectedInstOperands, |
| 3854 | /* 9818 */ // GIR_Coverage, 6208, |
| 3855 | /* 9818 */ GIR_EraseRootFromParent_Done, |
| 3856 | /* 9819 */ // Label 262: @9819 |
| 3857 | /* 9819 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 263*/ GIMT_Encode4(9880), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6090 // |
| 3858 | /* 9826 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3859 | /* 9830 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3860 | /* 9834 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3861 | /* 9838 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3862 | /* 9842 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3863 | /* 9847 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3864 | /* 9852 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3865 | /* 9854 */ // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3866 | /* 9854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32), |
| 3867 | /* 9857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3868 | /* 9859 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3869 | /* 9861 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3870 | /* 9865 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3871 | /* 9869 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3872 | /* 9872 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3873 | /* 9878 */ GIR_RootConstrainSelectedInstOperands, |
| 3874 | /* 9879 */ // GIR_Coverage, 6090, |
| 3875 | /* 9879 */ GIR_EraseRootFromParent_Done, |
| 3876 | /* 9880 */ // Label 263: @9880 |
| 3877 | /* 9880 */ GIM_Reject, |
| 3878 | /* 9881 */ // Label 260: @9881 |
| 3879 | /* 9881 */ GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(10105), |
| 3880 | /* 9886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3881 | /* 9890 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 265*/ GIMT_Encode4(9951), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1343 // |
| 3882 | /* 9897 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3883 | /* 9901 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3884 | /* 9905 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3885 | /* 9909 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3886 | /* 9913 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3887 | /* 9918 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3888 | /* 9923 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3889 | /* 9925 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3890 | /* 9925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32), |
| 3891 | /* 9928 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3892 | /* 9930 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3893 | /* 9932 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3894 | /* 9936 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3895 | /* 9940 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3896 | /* 9943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3897 | /* 9949 */ GIR_RootConstrainSelectedInstOperands, |
| 3898 | /* 9950 */ // GIR_Coverage, 1343, |
| 3899 | /* 9950 */ GIR_EraseRootFromParent_Done, |
| 3900 | /* 9951 */ // Label 265: @9951 |
| 3901 | /* 9951 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 266*/ GIMT_Encode4(10012), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1349 // |
| 3902 | /* 9958 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3903 | /* 9962 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3904 | /* 9966 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3905 | /* 9970 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3906 | /* 9974 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3907 | /* 9979 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3908 | /* 9984 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3909 | /* 9986 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3910 | /* 9986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32), |
| 3911 | /* 9989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3912 | /* 9991 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3913 | /* 9993 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3914 | /* 9997 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3915 | /* 10001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3916 | /* 10004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3917 | /* 10010 */ GIR_RootConstrainSelectedInstOperands, |
| 3918 | /* 10011 */ // GIR_Coverage, 1349, |
| 3919 | /* 10011 */ GIR_EraseRootFromParent_Done, |
| 3920 | /* 10012 */ // Label 266: @10012 |
| 3921 | /* 10012 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 267*/ GIMT_Encode4(10073), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1009 // |
| 3922 | /* 10019 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3923 | /* 10023 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3924 | /* 10027 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3925 | /* 10031 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3926 | /* 10035 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3927 | /* 10040 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3928 | /* 10045 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3929 | /* 10047 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3930 | /* 10047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32), |
| 3931 | /* 10050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3932 | /* 10052 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3933 | /* 10054 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3934 | /* 10058 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3935 | /* 10062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3936 | /* 10065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3937 | /* 10071 */ GIR_RootConstrainSelectedInstOperands, |
| 3938 | /* 10072 */ // GIR_Coverage, 1009, |
| 3939 | /* 10072 */ GIR_EraseRootFromParent_Done, |
| 3940 | /* 10073 */ // Label 267: @10073 |
| 3941 | /* 10073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 268*/ GIMT_Encode4(10104), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 878 // |
| 3942 | /* 10080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3943 | /* 10084 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3944 | /* 10084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i32), |
| 3945 | /* 10087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3946 | /* 10089 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3947 | /* 10091 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3948 | /* 10093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3949 | /* 10096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3950 | /* 10102 */ GIR_RootConstrainSelectedInstOperands, |
| 3951 | /* 10103 */ // GIR_Coverage, 878, |
| 3952 | /* 10103 */ GIR_EraseRootFromParent_Done, |
| 3953 | /* 10104 */ // Label 268: @10104 |
| 3954 | /* 10104 */ GIM_Reject, |
| 3955 | /* 10105 */ // Label 264: @10105 |
| 3956 | /* 10105 */ GIM_Reject, |
| 3957 | /* 10106 */ // Label 259: @10106 |
| 3958 | /* 10106 */ GIM_Reject, |
| 3959 | /* 10107 */ // Label 102: @10107 |
| 3960 | /* 10107 */ GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(11541), |
| 3961 | /* 10112 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3962 | /* 10115 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3963 | /* 10118 */ GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(11480), |
| 3964 | /* 10123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3965 | /* 10127 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 271*/ GIMT_Encode4(10194), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 898 // |
| 3966 | /* 10134 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3967 | /* 10138 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3968 | /* 10142 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3969 | /* 10146 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3970 | /* 10151 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3971 | /* 10155 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3972 | /* 10159 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3973 | /* 10163 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3974 | /* 10168 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3975 | /* 10170 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3976 | /* 10170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 3977 | /* 10173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3978 | /* 10175 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3979 | /* 10179 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3980 | /* 10183 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3981 | /* 10186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3982 | /* 10192 */ GIR_RootConstrainSelectedInstOperands, |
| 3983 | /* 10193 */ // GIR_Coverage, 898, |
| 3984 | /* 10193 */ GIR_EraseRootFromParent_Done, |
| 3985 | /* 10194 */ // Label 271: @10194 |
| 3986 | /* 10194 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 272*/ GIMT_Encode4(10261), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 897 // |
| 3987 | /* 10201 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3988 | /* 10205 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3989 | /* 10209 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3990 | /* 10213 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3991 | /* 10218 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3992 | /* 10222 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3993 | /* 10226 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3994 | /* 10230 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3995 | /* 10235 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3996 | /* 10237 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3997 | /* 10237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 3998 | /* 10240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3999 | /* 10242 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4000 | /* 10246 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4001 | /* 10250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4002 | /* 10253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4003 | /* 10259 */ GIR_RootConstrainSelectedInstOperands, |
| 4004 | /* 10260 */ // GIR_Coverage, 897, |
| 4005 | /* 10260 */ GIR_EraseRootFromParent_Done, |
| 4006 | /* 10261 */ // Label 272: @10261 |
| 4007 | /* 10261 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 273*/ GIMT_Encode4(10328), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 889 // |
| 4008 | /* 10268 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4009 | /* 10272 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4010 | /* 10276 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4011 | /* 10280 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4012 | /* 10285 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4013 | /* 10289 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4014 | /* 10293 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4015 | /* 10297 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4016 | /* 10302 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4017 | /* 10304 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4018 | /* 10304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv4i32), |
| 4019 | /* 10307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4020 | /* 10309 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4021 | /* 10313 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4022 | /* 10317 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4023 | /* 10320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4024 | /* 10326 */ GIR_RootConstrainSelectedInstOperands, |
| 4025 | /* 10327 */ // GIR_Coverage, 889, |
| 4026 | /* 10327 */ GIR_EraseRootFromParent_Done, |
| 4027 | /* 10328 */ // Label 273: @10328 |
| 4028 | /* 10328 */ GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(10484), |
| 4029 | /* 10333 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4030 | /* 10337 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 275*/ GIMT_Encode4(10410), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6213 // |
| 4031 | /* 10344 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4032 | /* 10348 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4033 | /* 10352 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4034 | /* 10356 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4035 | /* 10360 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4036 | /* 10364 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4037 | /* 10368 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4038 | /* 10372 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4039 | /* 10377 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4040 | /* 10382 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4041 | /* 10384 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4042 | /* 10384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32), |
| 4043 | /* 10387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4044 | /* 10389 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4045 | /* 10391 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4046 | /* 10395 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4047 | /* 10399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4048 | /* 10402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4049 | /* 10408 */ GIR_RootConstrainSelectedInstOperands, |
| 4050 | /* 10409 */ // GIR_Coverage, 6213, |
| 4051 | /* 10409 */ GIR_EraseRootFromParent_Done, |
| 4052 | /* 10410 */ // Label 275: @10410 |
| 4053 | /* 10410 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 276*/ GIMT_Encode4(10483), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6216 // |
| 4054 | /* 10417 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4055 | /* 10421 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4056 | /* 10425 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4057 | /* 10429 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4058 | /* 10433 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4059 | /* 10437 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4060 | /* 10441 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4061 | /* 10445 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4062 | /* 10450 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4063 | /* 10455 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4064 | /* 10457 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4065 | /* 10457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32), |
| 4066 | /* 10460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4067 | /* 10462 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4068 | /* 10464 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4069 | /* 10468 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4070 | /* 10472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4071 | /* 10475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4072 | /* 10481 */ GIR_RootConstrainSelectedInstOperands, |
| 4073 | /* 10482 */ // GIR_Coverage, 6216, |
| 4074 | /* 10482 */ GIR_EraseRootFromParent_Done, |
| 4075 | /* 10483 */ // Label 276: @10483 |
| 4076 | /* 10483 */ GIM_Reject, |
| 4077 | /* 10484 */ // Label 274: @10484 |
| 4078 | /* 10484 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 277*/ GIMT_Encode4(10551), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 896 // |
| 4079 | /* 10491 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4080 | /* 10495 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4081 | /* 10499 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4082 | /* 10503 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4083 | /* 10508 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4084 | /* 10512 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4085 | /* 10516 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4086 | /* 10520 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4087 | /* 10525 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4088 | /* 10527 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4089 | /* 10527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 4090 | /* 10530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4091 | /* 10532 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4092 | /* 10536 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4093 | /* 10540 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4094 | /* 10543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4095 | /* 10549 */ GIR_RootConstrainSelectedInstOperands, |
| 4096 | /* 10550 */ // GIR_Coverage, 896, |
| 4097 | /* 10550 */ GIR_EraseRootFromParent_Done, |
| 4098 | /* 10551 */ // Label 277: @10551 |
| 4099 | /* 10551 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 278*/ GIMT_Encode4(10618), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 895 // |
| 4100 | /* 10558 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4101 | /* 10562 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4102 | /* 10566 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4103 | /* 10570 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4104 | /* 10575 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4105 | /* 10579 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4106 | /* 10583 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4107 | /* 10587 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4108 | /* 10592 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4109 | /* 10594 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4110 | /* 10594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 4111 | /* 10597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4112 | /* 10599 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4113 | /* 10603 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4114 | /* 10607 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4115 | /* 10610 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4116 | /* 10616 */ GIR_RootConstrainSelectedInstOperands, |
| 4117 | /* 10617 */ // GIR_Coverage, 895, |
| 4118 | /* 10617 */ GIR_EraseRootFromParent_Done, |
| 4119 | /* 10618 */ // Label 278: @10618 |
| 4120 | /* 10618 */ GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(10774), |
| 4121 | /* 10623 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4122 | /* 10627 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 280*/ GIMT_Encode4(10700), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1354 // |
| 4123 | /* 10634 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4124 | /* 10638 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4125 | /* 10642 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4126 | /* 10646 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4127 | /* 10650 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4128 | /* 10654 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4129 | /* 10658 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4130 | /* 10662 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4131 | /* 10667 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4132 | /* 10672 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4133 | /* 10674 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4134 | /* 10674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32), |
| 4135 | /* 10677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4136 | /* 10679 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4137 | /* 10681 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4138 | /* 10685 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4139 | /* 10689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4140 | /* 10692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4141 | /* 10698 */ GIR_RootConstrainSelectedInstOperands, |
| 4142 | /* 10699 */ // GIR_Coverage, 1354, |
| 4143 | /* 10699 */ GIR_EraseRootFromParent_Done, |
| 4144 | /* 10700 */ // Label 280: @10700 |
| 4145 | /* 10700 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 281*/ GIMT_Encode4(10773), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1357 // |
| 4146 | /* 10707 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4147 | /* 10711 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4148 | /* 10715 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4149 | /* 10719 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4150 | /* 10723 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4151 | /* 10727 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4152 | /* 10731 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4153 | /* 10735 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4154 | /* 10740 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4155 | /* 10745 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4156 | /* 10747 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4157 | /* 10747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32), |
| 4158 | /* 10750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4159 | /* 10752 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4160 | /* 10754 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4161 | /* 10758 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4162 | /* 10762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4163 | /* 10765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4164 | /* 10771 */ GIR_RootConstrainSelectedInstOperands, |
| 4165 | /* 10772 */ // GIR_Coverage, 1357, |
| 4166 | /* 10772 */ GIR_EraseRootFromParent_Done, |
| 4167 | /* 10773 */ // Label 281: @10773 |
| 4168 | /* 10773 */ GIM_Reject, |
| 4169 | /* 10774 */ // Label 279: @10774 |
| 4170 | /* 10774 */ GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(11111), |
| 4171 | /* 10779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4172 | /* 10783 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 283*/ GIMT_Encode4(10844), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6205 // |
| 4173 | /* 10790 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4174 | /* 10794 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4175 | /* 10798 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4176 | /* 10802 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4177 | /* 10806 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4178 | /* 10811 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4179 | /* 10816 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4180 | /* 10818 */ // (add:{ *:[v4i32] } (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4181 | /* 10818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32), |
| 4182 | /* 10821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4183 | /* 10823 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4184 | /* 10825 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4185 | /* 10829 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4186 | /* 10833 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4187 | /* 10836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4188 | /* 10842 */ GIR_RootConstrainSelectedInstOperands, |
| 4189 | /* 10843 */ // GIR_Coverage, 6205, |
| 4190 | /* 10843 */ GIR_EraseRootFromParent_Done, |
| 4191 | /* 10844 */ // Label 283: @10844 |
| 4192 | /* 10844 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 284*/ GIMT_Encode4(10905), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6211 // |
| 4193 | /* 10851 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4194 | /* 10855 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4195 | /* 10859 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4196 | /* 10863 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4197 | /* 10867 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4198 | /* 10872 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4199 | /* 10877 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4200 | /* 10879 */ // (add:{ *:[v4i32] } (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4201 | /* 10879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32), |
| 4202 | /* 10882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4203 | /* 10884 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4204 | /* 10886 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4205 | /* 10890 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4206 | /* 10894 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4207 | /* 10897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4208 | /* 10903 */ GIR_RootConstrainSelectedInstOperands, |
| 4209 | /* 10904 */ // GIR_Coverage, 6211, |
| 4210 | /* 10904 */ GIR_EraseRootFromParent_Done, |
| 4211 | /* 10905 */ // Label 284: @10905 |
| 4212 | /* 10905 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 285*/ GIMT_Encode4(10966), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6093 // |
| 4213 | /* 10912 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4214 | /* 10916 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4215 | /* 10920 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4216 | /* 10924 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4217 | /* 10928 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4218 | /* 10933 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4219 | /* 10938 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4220 | /* 10940 */ // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4221 | /* 10940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32), |
| 4222 | /* 10943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4223 | /* 10945 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4224 | /* 10947 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4225 | /* 10951 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4226 | /* 10955 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4227 | /* 10958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4228 | /* 10964 */ GIR_RootConstrainSelectedInstOperands, |
| 4229 | /* 10965 */ // GIR_Coverage, 6093, |
| 4230 | /* 10965 */ GIR_EraseRootFromParent_Done, |
| 4231 | /* 10966 */ // Label 285: @10966 |
| 4232 | /* 10966 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 286*/ GIMT_Encode4(11014), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6067 // |
| 4233 | /* 10973 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4234 | /* 10977 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4235 | /* 10981 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4236 | /* 10985 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4237 | /* 10990 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4238 | /* 10992 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4239 | /* 10992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 4240 | /* 10995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4241 | /* 10997 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 4242 | /* 10999 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4243 | /* 11003 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4244 | /* 11006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4245 | /* 11012 */ GIR_RootConstrainSelectedInstOperands, |
| 4246 | /* 11013 */ // GIR_Coverage, 6067, |
| 4247 | /* 11013 */ GIR_EraseRootFromParent_Done, |
| 4248 | /* 11014 */ // Label 286: @11014 |
| 4249 | /* 11014 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 287*/ GIMT_Encode4(11062), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6062 // |
| 4250 | /* 11021 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4251 | /* 11025 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4252 | /* 11029 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4253 | /* 11033 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4254 | /* 11038 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4255 | /* 11040 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4256 | /* 11040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32), |
| 4257 | /* 11043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4258 | /* 11045 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 4259 | /* 11047 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4260 | /* 11051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4261 | /* 11054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4262 | /* 11060 */ GIR_RootConstrainSelectedInstOperands, |
| 4263 | /* 11061 */ // GIR_Coverage, 6062, |
| 4264 | /* 11061 */ GIR_EraseRootFromParent_Done, |
| 4265 | /* 11062 */ // Label 287: @11062 |
| 4266 | /* 11062 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 288*/ GIMT_Encode4(11110), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6066 // |
| 4267 | /* 11069 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4268 | /* 11073 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4269 | /* 11077 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4270 | /* 11081 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4271 | /* 11086 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4272 | /* 11088 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4273 | /* 11088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 4274 | /* 11091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4275 | /* 11093 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 4276 | /* 11095 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4277 | /* 11099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4278 | /* 11102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4279 | /* 11108 */ GIR_RootConstrainSelectedInstOperands, |
| 4280 | /* 11109 */ // GIR_Coverage, 6066, |
| 4281 | /* 11109 */ GIR_EraseRootFromParent_Done, |
| 4282 | /* 11110 */ // Label 288: @11110 |
| 4283 | /* 11110 */ GIM_Reject, |
| 4284 | /* 11111 */ // Label 282: @11111 |
| 4285 | /* 11111 */ GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(11479), |
| 4286 | /* 11116 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4287 | /* 11120 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 290*/ GIMT_Encode4(11181), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1346 // |
| 4288 | /* 11127 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4289 | /* 11131 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4290 | /* 11135 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4291 | /* 11139 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4292 | /* 11143 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4293 | /* 11148 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4294 | /* 11153 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4295 | /* 11155 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4296 | /* 11155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32), |
| 4297 | /* 11158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4298 | /* 11160 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4299 | /* 11162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4300 | /* 11166 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4301 | /* 11170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4302 | /* 11173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4303 | /* 11179 */ GIR_RootConstrainSelectedInstOperands, |
| 4304 | /* 11180 */ // GIR_Coverage, 1346, |
| 4305 | /* 11180 */ GIR_EraseRootFromParent_Done, |
| 4306 | /* 11181 */ // Label 290: @11181 |
| 4307 | /* 11181 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 291*/ GIMT_Encode4(11242), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1352 // |
| 4308 | /* 11188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4309 | /* 11192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4310 | /* 11196 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4311 | /* 11200 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4312 | /* 11204 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4313 | /* 11209 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4314 | /* 11214 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4315 | /* 11216 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4316 | /* 11216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32), |
| 4317 | /* 11219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4318 | /* 11221 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4319 | /* 11223 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4320 | /* 11227 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4321 | /* 11231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4322 | /* 11234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4323 | /* 11240 */ GIR_RootConstrainSelectedInstOperands, |
| 4324 | /* 11241 */ // GIR_Coverage, 1352, |
| 4325 | /* 11241 */ GIR_EraseRootFromParent_Done, |
| 4326 | /* 11242 */ // Label 291: @11242 |
| 4327 | /* 11242 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 292*/ GIMT_Encode4(11303), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1012 // |
| 4328 | /* 11249 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4329 | /* 11253 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4330 | /* 11257 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4331 | /* 11261 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4332 | /* 11265 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4333 | /* 11270 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4334 | /* 11275 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4335 | /* 11277 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4336 | /* 11277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32), |
| 4337 | /* 11280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4338 | /* 11282 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4339 | /* 11284 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4340 | /* 11288 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4341 | /* 11292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4342 | /* 11295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4343 | /* 11301 */ GIR_RootConstrainSelectedInstOperands, |
| 4344 | /* 11302 */ // GIR_Coverage, 1012, |
| 4345 | /* 11302 */ GIR_EraseRootFromParent_Done, |
| 4346 | /* 11303 */ // Label 292: @11303 |
| 4347 | /* 11303 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 293*/ GIMT_Encode4(11351), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 909 // |
| 4348 | /* 11310 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4349 | /* 11314 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4350 | /* 11318 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4351 | /* 11322 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4352 | /* 11327 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4353 | /* 11329 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4354 | /* 11329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 4355 | /* 11332 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4356 | /* 11334 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4357 | /* 11336 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4358 | /* 11340 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4359 | /* 11343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4360 | /* 11349 */ GIR_RootConstrainSelectedInstOperands, |
| 4361 | /* 11350 */ // GIR_Coverage, 909, |
| 4362 | /* 11350 */ GIR_EraseRootFromParent_Done, |
| 4363 | /* 11351 */ // Label 293: @11351 |
| 4364 | /* 11351 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 294*/ GIMT_Encode4(11399), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 904 // |
| 4365 | /* 11358 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4366 | /* 11362 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4367 | /* 11366 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4368 | /* 11370 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4369 | /* 11375 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4370 | /* 11377 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4371 | /* 11377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32), |
| 4372 | /* 11380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4373 | /* 11382 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4374 | /* 11384 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4375 | /* 11388 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4376 | /* 11391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4377 | /* 11397 */ GIR_RootConstrainSelectedInstOperands, |
| 4378 | /* 11398 */ // GIR_Coverage, 904, |
| 4379 | /* 11398 */ GIR_EraseRootFromParent_Done, |
| 4380 | /* 11399 */ // Label 294: @11399 |
| 4381 | /* 11399 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 295*/ GIMT_Encode4(11447), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 908 // |
| 4382 | /* 11406 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4383 | /* 11410 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4384 | /* 11414 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4385 | /* 11418 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4386 | /* 11423 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4387 | /* 11425 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4388 | /* 11425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 4389 | /* 11428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4390 | /* 11430 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4391 | /* 11432 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4392 | /* 11436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4393 | /* 11439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4394 | /* 11445 */ GIR_RootConstrainSelectedInstOperands, |
| 4395 | /* 11446 */ // GIR_Coverage, 908, |
| 4396 | /* 11446 */ GIR_EraseRootFromParent_Done, |
| 4397 | /* 11447 */ // Label 295: @11447 |
| 4398 | /* 11447 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 296*/ GIMT_Encode4(11478), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 881 // |
| 4399 | /* 11454 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4400 | /* 11458 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4401 | /* 11458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i32), |
| 4402 | /* 11461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4403 | /* 11463 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4404 | /* 11465 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4405 | /* 11467 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4406 | /* 11470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4407 | /* 11476 */ GIR_RootConstrainSelectedInstOperands, |
| 4408 | /* 11477 */ // GIR_Coverage, 881, |
| 4409 | /* 11477 */ GIR_EraseRootFromParent_Done, |
| 4410 | /* 11478 */ // Label 296: @11478 |
| 4411 | /* 11478 */ GIM_Reject, |
| 4412 | /* 11479 */ // Label 289: @11479 |
| 4413 | /* 11479 */ GIM_Reject, |
| 4414 | /* 11480 */ // Label 270: @11480 |
| 4415 | /* 11480 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 297*/ GIMT_Encode4(11540), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3893 // |
| 4416 | /* 11487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4417 | /* 11491 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4418 | /* 11495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4419 | /* 11499 */ // (add:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 4420 | /* 11499 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 4421 | /* 11502 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4422 | /* 11506 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 4423 | /* 11511 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi32), |
| 4424 | /* 11514 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 4425 | /* 11516 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 4426 | /* 11518 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 4427 | /* 11520 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4428 | /* 11523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4429 | /* 11529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4430 | /* 11535 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4431 | /* 11538 */ GIR_RootConstrainSelectedInstOperands, |
| 4432 | /* 11539 */ // GIR_Coverage, 3893, |
| 4433 | /* 11539 */ GIR_EraseRootFromParent_Done, |
| 4434 | /* 11540 */ // Label 297: @11540 |
| 4435 | /* 11540 */ GIM_Reject, |
| 4436 | /* 11541 */ // Label 269: @11541 |
| 4437 | /* 11541 */ GIM_Reject, |
| 4438 | /* 11542 */ // Label 103: @11542 |
| 4439 | /* 11542 */ GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(12544), |
| 4440 | /* 11547 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 4441 | /* 11550 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 4442 | /* 11553 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4443 | /* 11557 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 299*/ GIMT_Encode4(11624), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 902 // |
| 4444 | /* 11564 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4445 | /* 11568 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4446 | /* 11572 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4447 | /* 11576 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4448 | /* 11581 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4449 | /* 11585 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4450 | /* 11589 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4451 | /* 11593 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4452 | /* 11598 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4453 | /* 11600 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4454 | /* 11600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 4455 | /* 11603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4456 | /* 11605 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4457 | /* 11609 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4458 | /* 11613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4459 | /* 11616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4460 | /* 11622 */ GIR_RootConstrainSelectedInstOperands, |
| 4461 | /* 11623 */ // GIR_Coverage, 902, |
| 4462 | /* 11623 */ GIR_EraseRootFromParent_Done, |
| 4463 | /* 11624 */ // Label 299: @11624 |
| 4464 | /* 11624 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 300*/ GIMT_Encode4(11691), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 901 // |
| 4465 | /* 11631 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4466 | /* 11635 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4467 | /* 11639 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4468 | /* 11643 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4469 | /* 11648 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4470 | /* 11652 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4471 | /* 11656 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4472 | /* 11660 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4473 | /* 11665 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4474 | /* 11667 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4475 | /* 11667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 4476 | /* 11670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4477 | /* 11672 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4478 | /* 11676 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4479 | /* 11680 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4480 | /* 11683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4481 | /* 11689 */ GIR_RootConstrainSelectedInstOperands, |
| 4482 | /* 11690 */ // GIR_Coverage, 901, |
| 4483 | /* 11690 */ GIR_EraseRootFromParent_Done, |
| 4484 | /* 11691 */ // Label 300: @11691 |
| 4485 | /* 11691 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 301*/ GIMT_Encode4(11758), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 890 // |
| 4486 | /* 11698 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4487 | /* 11702 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4488 | /* 11706 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4489 | /* 11710 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4490 | /* 11715 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4491 | /* 11719 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4492 | /* 11723 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4493 | /* 11727 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4494 | /* 11732 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4495 | /* 11734 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4496 | /* 11734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv2i64), |
| 4497 | /* 11737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4498 | /* 11739 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4499 | /* 11743 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4500 | /* 11747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4501 | /* 11750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4502 | /* 11756 */ GIR_RootConstrainSelectedInstOperands, |
| 4503 | /* 11757 */ // GIR_Coverage, 890, |
| 4504 | /* 11757 */ GIR_EraseRootFromParent_Done, |
| 4505 | /* 11758 */ // Label 301: @11758 |
| 4506 | /* 11758 */ GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(11914), |
| 4507 | /* 11763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4508 | /* 11767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 303*/ GIMT_Encode4(11840), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6214 // |
| 4509 | /* 11774 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4510 | /* 11778 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4511 | /* 11782 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4512 | /* 11786 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4513 | /* 11790 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4514 | /* 11794 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4515 | /* 11798 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 4516 | /* 11802 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4517 | /* 11807 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4518 | /* 11812 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4519 | /* 11814 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4520 | /* 11814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64), |
| 4521 | /* 11817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4522 | /* 11819 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4523 | /* 11821 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4524 | /* 11825 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4525 | /* 11829 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4526 | /* 11832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4527 | /* 11838 */ GIR_RootConstrainSelectedInstOperands, |
| 4528 | /* 11839 */ // GIR_Coverage, 6214, |
| 4529 | /* 11839 */ GIR_EraseRootFromParent_Done, |
| 4530 | /* 11840 */ // Label 303: @11840 |
| 4531 | /* 11840 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 304*/ GIMT_Encode4(11913), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6217 // |
| 4532 | /* 11847 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4533 | /* 11851 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4534 | /* 11855 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4535 | /* 11859 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4536 | /* 11863 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4537 | /* 11867 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4538 | /* 11871 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 4539 | /* 11875 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4540 | /* 11880 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4541 | /* 11885 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4542 | /* 11887 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4543 | /* 11887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64), |
| 4544 | /* 11890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4545 | /* 11892 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4546 | /* 11894 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4547 | /* 11898 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4548 | /* 11902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4549 | /* 11905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4550 | /* 11911 */ GIR_RootConstrainSelectedInstOperands, |
| 4551 | /* 11912 */ // GIR_Coverage, 6217, |
| 4552 | /* 11912 */ GIR_EraseRootFromParent_Done, |
| 4553 | /* 11913 */ // Label 304: @11913 |
| 4554 | /* 11913 */ GIM_Reject, |
| 4555 | /* 11914 */ // Label 302: @11914 |
| 4556 | /* 11914 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 305*/ GIMT_Encode4(11981), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 900 // |
| 4557 | /* 11921 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4558 | /* 11925 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4559 | /* 11929 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4560 | /* 11933 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4561 | /* 11938 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4562 | /* 11942 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4563 | /* 11946 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4564 | /* 11950 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4565 | /* 11955 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4566 | /* 11957 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4567 | /* 11957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 4568 | /* 11960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4569 | /* 11962 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4570 | /* 11966 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4571 | /* 11970 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4572 | /* 11973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4573 | /* 11979 */ GIR_RootConstrainSelectedInstOperands, |
| 4574 | /* 11980 */ // GIR_Coverage, 900, |
| 4575 | /* 11980 */ GIR_EraseRootFromParent_Done, |
| 4576 | /* 11981 */ // Label 305: @11981 |
| 4577 | /* 11981 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 306*/ GIMT_Encode4(12048), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 899 // |
| 4578 | /* 11988 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4579 | /* 11992 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4580 | /* 11996 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4581 | /* 12000 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4582 | /* 12005 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4583 | /* 12009 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4584 | /* 12013 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4585 | /* 12017 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4586 | /* 12022 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4587 | /* 12024 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4588 | /* 12024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 4589 | /* 12027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4590 | /* 12029 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4591 | /* 12033 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4592 | /* 12037 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4593 | /* 12040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4594 | /* 12046 */ GIR_RootConstrainSelectedInstOperands, |
| 4595 | /* 12047 */ // GIR_Coverage, 899, |
| 4596 | /* 12047 */ GIR_EraseRootFromParent_Done, |
| 4597 | /* 12048 */ // Label 306: @12048 |
| 4598 | /* 12048 */ GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(12204), |
| 4599 | /* 12053 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4600 | /* 12057 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 308*/ GIMT_Encode4(12130), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1355 // |
| 4601 | /* 12064 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4602 | /* 12068 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4603 | /* 12072 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4604 | /* 12076 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4605 | /* 12080 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4606 | /* 12084 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4607 | /* 12088 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 4608 | /* 12092 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4609 | /* 12097 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4610 | /* 12102 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4611 | /* 12104 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4612 | /* 12104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64), |
| 4613 | /* 12107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4614 | /* 12109 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4615 | /* 12111 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4616 | /* 12115 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4617 | /* 12119 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4618 | /* 12122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4619 | /* 12128 */ GIR_RootConstrainSelectedInstOperands, |
| 4620 | /* 12129 */ // GIR_Coverage, 1355, |
| 4621 | /* 12129 */ GIR_EraseRootFromParent_Done, |
| 4622 | /* 12130 */ // Label 308: @12130 |
| 4623 | /* 12130 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 309*/ GIMT_Encode4(12203), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1358 // |
| 4624 | /* 12137 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4625 | /* 12141 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4626 | /* 12145 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4627 | /* 12149 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4628 | /* 12153 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4629 | /* 12157 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4630 | /* 12161 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 4631 | /* 12165 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4632 | /* 12170 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4633 | /* 12175 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4634 | /* 12177 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4635 | /* 12177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64), |
| 4636 | /* 12180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4637 | /* 12182 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4638 | /* 12184 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4639 | /* 12188 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4640 | /* 12192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4641 | /* 12195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4642 | /* 12201 */ GIR_RootConstrainSelectedInstOperands, |
| 4643 | /* 12202 */ // GIR_Coverage, 1358, |
| 4644 | /* 12202 */ GIR_EraseRootFromParent_Done, |
| 4645 | /* 12203 */ // Label 309: @12203 |
| 4646 | /* 12203 */ GIM_Reject, |
| 4647 | /* 12204 */ // Label 307: @12204 |
| 4648 | /* 12204 */ GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(12358), |
| 4649 | /* 12209 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4650 | /* 12213 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 311*/ GIMT_Encode4(12261), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6069 // |
| 4651 | /* 12220 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4652 | /* 12224 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4653 | /* 12228 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4654 | /* 12232 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4655 | /* 12237 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4656 | /* 12239 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4657 | /* 12239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 4658 | /* 12242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4659 | /* 12244 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 4660 | /* 12246 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4661 | /* 12250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4662 | /* 12253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4663 | /* 12259 */ GIR_RootConstrainSelectedInstOperands, |
| 4664 | /* 12260 */ // GIR_Coverage, 6069, |
| 4665 | /* 12260 */ GIR_EraseRootFromParent_Done, |
| 4666 | /* 12261 */ // Label 311: @12261 |
| 4667 | /* 12261 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 312*/ GIMT_Encode4(12309), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6063 // |
| 4668 | /* 12268 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4669 | /* 12272 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4670 | /* 12276 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4671 | /* 12280 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4672 | /* 12285 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4673 | /* 12287 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4674 | /* 12287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64), |
| 4675 | /* 12290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4676 | /* 12292 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 4677 | /* 12294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4678 | /* 12298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4679 | /* 12301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4680 | /* 12307 */ GIR_RootConstrainSelectedInstOperands, |
| 4681 | /* 12308 */ // GIR_Coverage, 6063, |
| 4682 | /* 12308 */ GIR_EraseRootFromParent_Done, |
| 4683 | /* 12309 */ // Label 312: @12309 |
| 4684 | /* 12309 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 313*/ GIMT_Encode4(12357), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6068 // |
| 4685 | /* 12316 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4686 | /* 12320 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4687 | /* 12324 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4688 | /* 12328 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4689 | /* 12333 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4690 | /* 12335 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4691 | /* 12335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 4692 | /* 12338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4693 | /* 12340 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 4694 | /* 12342 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4695 | /* 12346 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4696 | /* 12349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4697 | /* 12355 */ GIR_RootConstrainSelectedInstOperands, |
| 4698 | /* 12356 */ // GIR_Coverage, 6068, |
| 4699 | /* 12356 */ GIR_EraseRootFromParent_Done, |
| 4700 | /* 12357 */ // Label 313: @12357 |
| 4701 | /* 12357 */ GIM_Reject, |
| 4702 | /* 12358 */ // Label 310: @12358 |
| 4703 | /* 12358 */ GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(12543), |
| 4704 | /* 12363 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4705 | /* 12367 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 315*/ GIMT_Encode4(12415), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 911 // |
| 4706 | /* 12374 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4707 | /* 12378 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4708 | /* 12382 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4709 | /* 12386 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4710 | /* 12391 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4711 | /* 12393 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4712 | /* 12393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 4713 | /* 12396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4714 | /* 12398 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4715 | /* 12400 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4716 | /* 12404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4717 | /* 12407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4718 | /* 12413 */ GIR_RootConstrainSelectedInstOperands, |
| 4719 | /* 12414 */ // GIR_Coverage, 911, |
| 4720 | /* 12414 */ GIR_EraseRootFromParent_Done, |
| 4721 | /* 12415 */ // Label 315: @12415 |
| 4722 | /* 12415 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 316*/ GIMT_Encode4(12463), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 905 // |
| 4723 | /* 12422 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4724 | /* 12426 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4725 | /* 12430 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4726 | /* 12434 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4727 | /* 12439 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4728 | /* 12441 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4729 | /* 12441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64), |
| 4730 | /* 12444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4731 | /* 12446 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4732 | /* 12448 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4733 | /* 12452 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4734 | /* 12455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4735 | /* 12461 */ GIR_RootConstrainSelectedInstOperands, |
| 4736 | /* 12462 */ // GIR_Coverage, 905, |
| 4737 | /* 12462 */ GIR_EraseRootFromParent_Done, |
| 4738 | /* 12463 */ // Label 316: @12463 |
| 4739 | /* 12463 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 317*/ GIMT_Encode4(12511), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 910 // |
| 4740 | /* 12470 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4741 | /* 12474 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4742 | /* 12478 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4743 | /* 12482 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4744 | /* 12487 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4745 | /* 12489 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4746 | /* 12489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 4747 | /* 12492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4748 | /* 12494 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4749 | /* 12496 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4750 | /* 12500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4751 | /* 12503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4752 | /* 12509 */ GIR_RootConstrainSelectedInstOperands, |
| 4753 | /* 12510 */ // GIR_Coverage, 910, |
| 4754 | /* 12510 */ GIR_EraseRootFromParent_Done, |
| 4755 | /* 12511 */ // Label 317: @12511 |
| 4756 | /* 12511 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 318*/ GIMT_Encode4(12542), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 883 // |
| 4757 | /* 12518 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4758 | /* 12522 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 4759 | /* 12522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i64), |
| 4760 | /* 12525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4761 | /* 12527 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4762 | /* 12529 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4763 | /* 12531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4764 | /* 12534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4765 | /* 12540 */ GIR_RootConstrainSelectedInstOperands, |
| 4766 | /* 12541 */ // GIR_Coverage, 883, |
| 4767 | /* 12541 */ GIR_EraseRootFromParent_Done, |
| 4768 | /* 12542 */ // Label 318: @12542 |
| 4769 | /* 12542 */ GIM_Reject, |
| 4770 | /* 12543 */ // Label 314: @12543 |
| 4771 | /* 12543 */ GIM_Reject, |
| 4772 | /* 12544 */ // Label 298: @12544 |
| 4773 | /* 12544 */ GIM_Reject, |
| 4774 | /* 12545 */ // Label 104: @12545 |
| 4775 | /* 12545 */ GIM_Reject, |
| 4776 | /* 12546 */ // Label 1: @12546 |
| 4777 | /* 12546 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 328*/ GIMT_Encode4(15643), |
| 4778 | /* 12557 */ /*GILLT_s32*//*Label 319*/ GIMT_Encode4(12609), |
| 4779 | /* 12561 */ /*GILLT_s64*//*Label 320*/ GIMT_Encode4(13214), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 4780 | /* 12581 */ /*GILLT_v8s8*//*Label 321*/ GIMT_Encode4(13260), |
| 4781 | /* 12585 */ /*GILLT_v16s8*//*Label 322*/ GIMT_Encode4(13373), |
| 4782 | /* 12589 */ /*GILLT_v4s16*//*Label 323*/ GIMT_Encode4(13552), |
| 4783 | /* 12593 */ /*GILLT_v8s16*//*Label 324*/ GIMT_Encode4(13665), |
| 4784 | /* 12597 */ /*GILLT_v2s32*//*Label 325*/ GIMT_Encode4(14329), |
| 4785 | /* 12601 */ /*GILLT_v4s32*//*Label 326*/ GIMT_Encode4(14442), |
| 4786 | /* 12605 */ /*GILLT_v2s64*//*Label 327*/ GIMT_Encode4(15106), |
| 4787 | /* 12609 */ // Label 319: @12609 |
| 4788 | /* 12609 */ GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(13213), |
| 4789 | /* 12614 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 4790 | /* 12617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4791 | /* 12620 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 330*/ GIMT_Encode4(12663), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 329 // |
| 4792 | /* 12627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4793 | /* 12631 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, |
| 4794 | /* 12635 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4795 | /* 12639 */ // (sub:{ *:[i32] } 0:{ *:[i32] }, tGPR:{ *:[i32] }:$Rn) => (tRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn) |
| 4796 | /* 12639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tRSB), |
| 4797 | /* 12642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4798 | /* 12644 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 4799 | /* 12650 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4800 | /* 12652 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4801 | /* 12655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4802 | /* 12661 */ GIR_RootConstrainSelectedInstOperands, |
| 4803 | /* 12662 */ // GIR_Coverage, 329, |
| 4804 | /* 12662 */ GIR_EraseRootFromParent_Done, |
| 4805 | /* 12663 */ // Label 330: @12663 |
| 4806 | /* 12663 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 331*/ GIMT_Encode4(12719), GIMT_Encode2(GIFBS_IsARM), // Rule ID 95 // |
| 4807 | /* 12670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4808 | /* 12674 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4809 | /* 12678 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4810 | /* 12682 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 4811 | /* 12686 */ // MIs[1] Operand 1 |
| 4812 | /* 12686 */ // No operand predicates |
| 4813 | /* 12686 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4814 | /* 12690 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4815 | /* 12692 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn) => (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4816 | /* 12692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RSBri), |
| 4817 | /* 12695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4818 | /* 12697 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4819 | /* 12699 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4820 | /* 12702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4821 | /* 12705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4822 | /* 12711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4823 | /* 12717 */ GIR_RootConstrainSelectedInstOperands, |
| 4824 | /* 12718 */ // GIR_Coverage, 95, |
| 4825 | /* 12718 */ GIR_EraseRootFromParent_Done, |
| 4826 | /* 12719 */ // Label 331: @12719 |
| 4827 | /* 12719 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 332*/ GIMT_Encode4(12775), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 426 // |
| 4828 | /* 12726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4829 | /* 12730 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4830 | /* 12734 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4831 | /* 12738 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 4832 | /* 12742 */ // MIs[1] Operand 1 |
| 4833 | /* 12742 */ // No operand predicates |
| 4834 | /* 12742 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4835 | /* 12746 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4836 | /* 12748 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn) => (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4837 | /* 12748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RSBri), |
| 4838 | /* 12751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4839 | /* 12753 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4840 | /* 12755 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4841 | /* 12758 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4842 | /* 12761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4843 | /* 12767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4844 | /* 12773 */ GIR_RootConstrainSelectedInstOperands, |
| 4845 | /* 12774 */ // GIR_Coverage, 426, |
| 4846 | /* 12774 */ GIR_EraseRootFromParent_Done, |
| 4847 | /* 12775 */ // Label 332: @12775 |
| 4848 | /* 12775 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 333*/ GIMT_Encode4(12831), GIMT_Encode2(GIFBS_IsARM), // Rule ID 75 // |
| 4849 | /* 12782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4850 | /* 12786 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4851 | /* 12790 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4852 | /* 12794 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4853 | /* 12798 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 4854 | /* 12802 */ // MIs[1] Operand 1 |
| 4855 | /* 12802 */ // No operand predicates |
| 4856 | /* 12802 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4857 | /* 12804 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4858 | /* 12804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBri), |
| 4859 | /* 12807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4860 | /* 12809 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4861 | /* 12811 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4862 | /* 12814 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4863 | /* 12817 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4864 | /* 12823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4865 | /* 12829 */ GIR_RootConstrainSelectedInstOperands, |
| 4866 | /* 12830 */ // GIR_Coverage, 75, |
| 4867 | /* 12830 */ GIR_EraseRootFromParent_Done, |
| 4868 | /* 12831 */ // Label 333: @12831 |
| 4869 | /* 12831 */ GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(12939), |
| 4870 | /* 12836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4871 | /* 12840 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 335*/ GIMT_Encode4(12892), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 410 // |
| 4872 | /* 12847 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4873 | /* 12851 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4874 | /* 12855 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4875 | /* 12859 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 4876 | /* 12863 */ // MIs[1] Operand 1 |
| 4877 | /* 12863 */ // No operand predicates |
| 4878 | /* 12863 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4879 | /* 12865 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4880 | /* 12865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri), |
| 4881 | /* 12868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4882 | /* 12870 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4883 | /* 12872 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4884 | /* 12875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4885 | /* 12878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4886 | /* 12884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4887 | /* 12890 */ GIR_RootConstrainSelectedInstOperands, |
| 4888 | /* 12891 */ // GIR_Coverage, 410, |
| 4889 | /* 12891 */ GIR_EraseRootFromParent_Done, |
| 4890 | /* 12892 */ // Label 335: @12892 |
| 4891 | /* 12892 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 336*/ GIMT_Encode4(12938), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 411 // |
| 4892 | /* 12899 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4893 | /* 12903 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4894 | /* 12907 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4895 | /* 12911 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095), |
| 4896 | /* 12915 */ // MIs[1] Operand 1 |
| 4897 | /* 12915 */ // No operand predicates |
| 4898 | /* 12915 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4899 | /* 12917 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4900 | /* 12917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri12), |
| 4901 | /* 12920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4902 | /* 12922 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4903 | /* 12924 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4904 | /* 12927 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4905 | /* 12930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4906 | /* 12936 */ GIR_RootConstrainSelectedInstOperands, |
| 4907 | /* 12937 */ // GIR_Coverage, 411, |
| 4908 | /* 12937 */ GIR_EraseRootFromParent_Done, |
| 4909 | /* 12938 */ // Label 336: @12938 |
| 4910 | /* 12938 */ GIM_Reject, |
| 4911 | /* 12939 */ // Label 334: @12939 |
| 4912 | /* 12939 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 337*/ GIMT_Encode4(13008), GIMT_Encode2(GIFBS_HasV6T2_IsARM_UseMulOps), // Rule ID 172 // |
| 4913 | /* 12946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4914 | /* 12950 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4915 | /* 12954 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4916 | /* 12958 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4917 | /* 12962 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4918 | /* 12966 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4919 | /* 12970 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4920 | /* 12975 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4921 | /* 12980 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4922 | /* 12982 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 4923 | /* 12982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLS), |
| 4924 | /* 12985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4925 | /* 12987 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4926 | /* 12991 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 4927 | /* 12995 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 4928 | /* 12997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4929 | /* 13000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4930 | /* 13006 */ GIR_RootConstrainSelectedInstOperands, |
| 4931 | /* 13007 */ // GIR_Coverage, 172, |
| 4932 | /* 13007 */ GIR_EraseRootFromParent_Done, |
| 4933 | /* 13008 */ // Label 337: @13008 |
| 4934 | /* 13008 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 338*/ GIMT_Encode4(13077), GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), // Rule ID 503 // |
| 4935 | /* 13015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4936 | /* 13019 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4937 | /* 13023 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4938 | /* 13027 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4939 | /* 13031 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4940 | /* 13035 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4941 | /* 13039 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4942 | /* 13044 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4943 | /* 13049 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4944 | /* 13051 */ // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 4945 | /* 13051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLS), |
| 4946 | /* 13054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4947 | /* 13056 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4948 | /* 13060 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 4949 | /* 13064 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 4950 | /* 13066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4951 | /* 13069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4952 | /* 13075 */ GIR_RootConstrainSelectedInstOperands, |
| 4953 | /* 13076 */ // GIR_Coverage, 503, |
| 4954 | /* 13076 */ GIR_EraseRootFromParent_Done, |
| 4955 | /* 13077 */ // Label 338: @13077 |
| 4956 | /* 13077 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 339*/ GIMT_Encode4(13122), GIMT_Encode2(GIFBS_IsARM), // Rule ID 76 // |
| 4957 | /* 13084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4958 | /* 13088 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4959 | /* 13092 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4960 | /* 13096 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 4961 | /* 13096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBrr), |
| 4962 | /* 13099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4963 | /* 13101 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4964 | /* 13103 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4965 | /* 13105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4966 | /* 13108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4967 | /* 13114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4968 | /* 13120 */ GIR_RootConstrainSelectedInstOperands, |
| 4969 | /* 13121 */ // GIR_Coverage, 76, |
| 4970 | /* 13121 */ GIR_EraseRootFromParent_Done, |
| 4971 | /* 13122 */ // Label 339: @13122 |
| 4972 | /* 13122 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 340*/ GIMT_Encode4(13167), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 332 // |
| 4973 | /* 13129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4974 | /* 13133 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4975 | /* 13137 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4976 | /* 13141 */ // (sub:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tSUBrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 4977 | /* 13141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSUBrr), |
| 4978 | /* 13144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4979 | /* 13146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 4980 | /* 13152 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4981 | /* 13154 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4982 | /* 13156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4983 | /* 13159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4984 | /* 13165 */ GIR_RootConstrainSelectedInstOperands, |
| 4985 | /* 13166 */ // GIR_Coverage, 332, |
| 4986 | /* 13166 */ GIR_EraseRootFromParent_Done, |
| 4987 | /* 13167 */ // Label 340: @13167 |
| 4988 | /* 13167 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 341*/ GIMT_Encode4(13212), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 412 // |
| 4989 | /* 13174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4990 | /* 13178 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4991 | /* 13182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4992 | /* 13186 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 4993 | /* 13186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBrr), |
| 4994 | /* 13189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4995 | /* 13191 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4996 | /* 13193 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4997 | /* 13195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4998 | /* 13198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4999 | /* 13204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5000 | /* 13210 */ GIR_RootConstrainSelectedInstOperands, |
| 5001 | /* 13211 */ // GIR_Coverage, 412, |
| 5002 | /* 13211 */ GIR_EraseRootFromParent_Done, |
| 5003 | /* 13212 */ // Label 341: @13212 |
| 5004 | /* 13212 */ GIM_Reject, |
| 5005 | /* 13213 */ // Label 329: @13213 |
| 5006 | /* 13213 */ GIM_Reject, |
| 5007 | /* 13214 */ // Label 320: @13214 |
| 5008 | /* 13214 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 342*/ GIMT_Encode4(13259), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1128 // |
| 5009 | /* 13221 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 5010 | /* 13224 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 5011 | /* 13227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5012 | /* 13231 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5013 | /* 13235 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5014 | /* 13239 */ // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 5015 | /* 13239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv1i64), |
| 5016 | /* 13242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5017 | /* 13244 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5018 | /* 13246 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5019 | /* 13248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5020 | /* 13251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5021 | /* 13257 */ GIR_RootConstrainSelectedInstOperands, |
| 5022 | /* 13258 */ // GIR_Coverage, 1128, |
| 5023 | /* 13258 */ GIR_EraseRootFromParent_Done, |
| 5024 | /* 13259 */ // Label 342: @13259 |
| 5025 | /* 13259 */ GIM_Reject, |
| 5026 | /* 13260 */ // Label 321: @13260 |
| 5027 | /* 13260 */ GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(13372), |
| 5028 | /* 13265 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5029 | /* 13268 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 5030 | /* 13271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5031 | /* 13275 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5032 | /* 13279 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 344*/ GIMT_Encode4(13340), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1053 // |
| 5033 | /* 13286 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5034 | /* 13290 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5035 | /* 13294 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5036 | /* 13298 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 5037 | /* 13302 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5038 | /* 13307 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5039 | /* 13312 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5040 | /* 13314 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5041 | /* 13314 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i8), |
| 5042 | /* 13317 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5043 | /* 13319 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5044 | /* 13321 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5045 | /* 13325 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5046 | /* 13329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5047 | /* 13332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5048 | /* 13338 */ GIR_RootConstrainSelectedInstOperands, |
| 5049 | /* 13339 */ // GIR_Coverage, 1053, |
| 5050 | /* 13339 */ GIR_EraseRootFromParent_Done, |
| 5051 | /* 13340 */ // Label 344: @13340 |
| 5052 | /* 13340 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 345*/ GIMT_Encode4(13371), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1122 // |
| 5053 | /* 13347 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5054 | /* 13351 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5055 | /* 13351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i8), |
| 5056 | /* 13354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5057 | /* 13356 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5058 | /* 13358 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5059 | /* 13360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5060 | /* 13363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5061 | /* 13369 */ GIR_RootConstrainSelectedInstOperands, |
| 5062 | /* 13370 */ // GIR_Coverage, 1122, |
| 5063 | /* 13370 */ GIR_EraseRootFromParent_Done, |
| 5064 | /* 13371 */ // Label 345: @13371 |
| 5065 | /* 13371 */ GIM_Reject, |
| 5066 | /* 13372 */ // Label 343: @13372 |
| 5067 | /* 13372 */ GIM_Reject, |
| 5068 | /* 13373 */ // Label 322: @13373 |
| 5069 | /* 13373 */ GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(13551), |
| 5070 | /* 13378 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 5071 | /* 13381 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5072 | /* 13384 */ GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(13490), |
| 5073 | /* 13389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5074 | /* 13393 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5075 | /* 13397 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 348*/ GIMT_Encode4(13458), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1056 // |
| 5076 | /* 13404 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5077 | /* 13408 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5078 | /* 13412 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 5079 | /* 13416 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5080 | /* 13420 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5081 | /* 13425 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5082 | /* 13430 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5083 | /* 13432 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 5084 | /* 13432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv16i8), |
| 5085 | /* 13435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5086 | /* 13437 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5087 | /* 13439 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5088 | /* 13443 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5089 | /* 13447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5090 | /* 13450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5091 | /* 13456 */ GIR_RootConstrainSelectedInstOperands, |
| 5092 | /* 13457 */ // GIR_Coverage, 1056, |
| 5093 | /* 13457 */ GIR_EraseRootFromParent_Done, |
| 5094 | /* 13458 */ // Label 348: @13458 |
| 5095 | /* 13458 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 349*/ GIMT_Encode4(13489), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1125 // |
| 5096 | /* 13465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5097 | /* 13469 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 5098 | /* 13469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv16i8), |
| 5099 | /* 13472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5100 | /* 13474 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5101 | /* 13476 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5102 | /* 13478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5103 | /* 13481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5104 | /* 13487 */ GIR_RootConstrainSelectedInstOperands, |
| 5105 | /* 13488 */ // GIR_Coverage, 1125, |
| 5106 | /* 13488 */ GIR_EraseRootFromParent_Done, |
| 5107 | /* 13489 */ // Label 349: @13489 |
| 5108 | /* 13489 */ GIM_Reject, |
| 5109 | /* 13490 */ // Label 347: @13490 |
| 5110 | /* 13490 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 350*/ GIMT_Encode4(13550), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3897 // |
| 5111 | /* 13497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5112 | /* 13501 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5113 | /* 13505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5114 | /* 13509 */ // (sub:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VSUBi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 5115 | /* 13509 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5116 | /* 13512 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5117 | /* 13516 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 5118 | /* 13521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi8), |
| 5119 | /* 13524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5120 | /* 13526 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5121 | /* 13528 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5122 | /* 13530 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5123 | /* 13533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5124 | /* 13539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5125 | /* 13545 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5126 | /* 13548 */ GIR_RootConstrainSelectedInstOperands, |
| 5127 | /* 13549 */ // GIR_Coverage, 3897, |
| 5128 | /* 13549 */ GIR_EraseRootFromParent_Done, |
| 5129 | /* 13550 */ // Label 350: @13550 |
| 5130 | /* 13550 */ GIM_Reject, |
| 5131 | /* 13551 */ // Label 346: @13551 |
| 5132 | /* 13551 */ GIM_Reject, |
| 5133 | /* 13552 */ // Label 323: @13552 |
| 5134 | /* 13552 */ GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(13664), |
| 5135 | /* 13557 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5136 | /* 13560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 5137 | /* 13563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5138 | /* 13567 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5139 | /* 13571 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 352*/ GIMT_Encode4(13632), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1054 // |
| 5140 | /* 13578 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5141 | /* 13582 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5142 | /* 13586 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5143 | /* 13590 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 5144 | /* 13594 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5145 | /* 13599 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5146 | /* 13604 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5147 | /* 13606 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5148 | /* 13606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i16), |
| 5149 | /* 13609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5150 | /* 13611 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5151 | /* 13613 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5152 | /* 13617 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5153 | /* 13621 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5154 | /* 13624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5155 | /* 13630 */ GIR_RootConstrainSelectedInstOperands, |
| 5156 | /* 13631 */ // GIR_Coverage, 1054, |
| 5157 | /* 13631 */ GIR_EraseRootFromParent_Done, |
| 5158 | /* 13632 */ // Label 352: @13632 |
| 5159 | /* 13632 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 353*/ GIMT_Encode4(13663), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1123 // |
| 5160 | /* 13639 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5161 | /* 13643 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5162 | /* 13643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i16), |
| 5163 | /* 13646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5164 | /* 13648 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5165 | /* 13650 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5166 | /* 13652 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5167 | /* 13655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5168 | /* 13661 */ GIR_RootConstrainSelectedInstOperands, |
| 5169 | /* 13662 */ // GIR_Coverage, 1123, |
| 5170 | /* 13662 */ GIR_EraseRootFromParent_Done, |
| 5171 | /* 13663 */ // Label 353: @13663 |
| 5172 | /* 13663 */ GIM_Reject, |
| 5173 | /* 13664 */ // Label 351: @13664 |
| 5174 | /* 13664 */ GIM_Reject, |
| 5175 | /* 13665 */ // Label 324: @13665 |
| 5176 | /* 13665 */ GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(14328), |
| 5177 | /* 13670 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 5178 | /* 13673 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5179 | /* 13676 */ GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(14267), |
| 5180 | /* 13681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5181 | /* 13685 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 356*/ GIMT_Encode4(13752), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1140 // |
| 5182 | /* 13692 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5183 | /* 13696 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5184 | /* 13700 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5185 | /* 13704 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5186 | /* 13709 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5187 | /* 13713 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5188 | /* 13717 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5189 | /* 13721 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5190 | /* 13726 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5191 | /* 13728 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5192 | /* 13728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 5193 | /* 13731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5194 | /* 13733 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5195 | /* 13737 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5196 | /* 13741 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5197 | /* 13744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5198 | /* 13750 */ GIR_RootConstrainSelectedInstOperands, |
| 5199 | /* 13751 */ // GIR_Coverage, 1140, |
| 5200 | /* 13751 */ GIR_EraseRootFromParent_Done, |
| 5201 | /* 13752 */ // Label 356: @13752 |
| 5202 | /* 13752 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 357*/ GIMT_Encode4(13819), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1139 // |
| 5203 | /* 13759 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5204 | /* 13763 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5205 | /* 13767 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5206 | /* 13771 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5207 | /* 13776 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5208 | /* 13780 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5209 | /* 13784 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5210 | /* 13788 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5211 | /* 13793 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5212 | /* 13795 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5213 | /* 13795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 5214 | /* 13798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5215 | /* 13800 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5216 | /* 13804 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5217 | /* 13808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5218 | /* 13811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5219 | /* 13817 */ GIR_RootConstrainSelectedInstOperands, |
| 5220 | /* 13818 */ // GIR_Coverage, 1139, |
| 5221 | /* 13818 */ GIR_EraseRootFromParent_Done, |
| 5222 | /* 13819 */ // Label 357: @13819 |
| 5223 | /* 13819 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 358*/ GIMT_Encode4(13886), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1134 // |
| 5224 | /* 13826 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5225 | /* 13830 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5226 | /* 13834 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5227 | /* 13838 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5228 | /* 13843 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5229 | /* 13847 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5230 | /* 13851 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5231 | /* 13855 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5232 | /* 13860 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5233 | /* 13862 */ // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5234 | /* 13862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv8i16), |
| 5235 | /* 13865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5236 | /* 13867 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5237 | /* 13871 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5238 | /* 13875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5239 | /* 13878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5240 | /* 13884 */ GIR_RootConstrainSelectedInstOperands, |
| 5241 | /* 13885 */ // GIR_Coverage, 1134, |
| 5242 | /* 13885 */ GIR_EraseRootFromParent_Done, |
| 5243 | /* 13886 */ // Label 358: @13886 |
| 5244 | /* 13886 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 359*/ GIMT_Encode4(13953), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1138 // |
| 5245 | /* 13893 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5246 | /* 13897 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5247 | /* 13901 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5248 | /* 13905 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5249 | /* 13910 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5250 | /* 13914 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5251 | /* 13918 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5252 | /* 13922 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5253 | /* 13927 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5254 | /* 13929 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5255 | /* 13929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 5256 | /* 13932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5257 | /* 13934 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5258 | /* 13938 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5259 | /* 13942 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5260 | /* 13945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5261 | /* 13951 */ GIR_RootConstrainSelectedInstOperands, |
| 5262 | /* 13952 */ // GIR_Coverage, 1138, |
| 5263 | /* 13952 */ GIR_EraseRootFromParent_Done, |
| 5264 | /* 13953 */ // Label 359: @13953 |
| 5265 | /* 13953 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 360*/ GIMT_Encode4(14020), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1137 // |
| 5266 | /* 13960 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5267 | /* 13964 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5268 | /* 13968 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5269 | /* 13972 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5270 | /* 13977 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5271 | /* 13981 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5272 | /* 13985 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5273 | /* 13989 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5274 | /* 13994 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5275 | /* 13996 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5276 | /* 13996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 5277 | /* 13999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5278 | /* 14001 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5279 | /* 14005 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5280 | /* 14009 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5281 | /* 14012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5282 | /* 14018 */ GIR_RootConstrainSelectedInstOperands, |
| 5283 | /* 14019 */ // GIR_Coverage, 1137, |
| 5284 | /* 14019 */ GIR_EraseRootFromParent_Done, |
| 5285 | /* 14020 */ // Label 360: @14020 |
| 5286 | /* 14020 */ GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(14266), |
| 5287 | /* 14025 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5288 | /* 14029 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 362*/ GIMT_Encode4(14090), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1057 // |
| 5289 | /* 14036 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5290 | /* 14040 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5291 | /* 14044 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 5292 | /* 14048 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5293 | /* 14052 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5294 | /* 14057 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5295 | /* 14062 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5296 | /* 14064 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 5297 | /* 14064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i16), |
| 5298 | /* 14067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5299 | /* 14069 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5300 | /* 14071 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5301 | /* 14075 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5302 | /* 14079 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5303 | /* 14082 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5304 | /* 14088 */ GIR_RootConstrainSelectedInstOperands, |
| 5305 | /* 14089 */ // GIR_Coverage, 1057, |
| 5306 | /* 14089 */ GIR_EraseRootFromParent_Done, |
| 5307 | /* 14090 */ // Label 362: @14090 |
| 5308 | /* 14090 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 363*/ GIMT_Encode4(14138), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1153 // |
| 5309 | /* 14097 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5310 | /* 14101 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5311 | /* 14105 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5312 | /* 14109 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5313 | /* 14114 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5314 | /* 14116 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5315 | /* 14116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16), |
| 5316 | /* 14119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5317 | /* 14121 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5318 | /* 14123 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5319 | /* 14127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5320 | /* 14130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5321 | /* 14136 */ GIR_RootConstrainSelectedInstOperands, |
| 5322 | /* 14137 */ // GIR_Coverage, 1153, |
| 5323 | /* 14137 */ GIR_EraseRootFromParent_Done, |
| 5324 | /* 14138 */ // Label 363: @14138 |
| 5325 | /* 14138 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 364*/ GIMT_Encode4(14186), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1149 // |
| 5326 | /* 14145 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5327 | /* 14149 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5328 | /* 14153 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5329 | /* 14157 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5330 | /* 14162 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5331 | /* 14164 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5332 | /* 14164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv8i16), |
| 5333 | /* 14167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5334 | /* 14169 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5335 | /* 14171 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5336 | /* 14175 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5337 | /* 14178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5338 | /* 14184 */ GIR_RootConstrainSelectedInstOperands, |
| 5339 | /* 14185 */ // GIR_Coverage, 1149, |
| 5340 | /* 14185 */ GIR_EraseRootFromParent_Done, |
| 5341 | /* 14186 */ // Label 364: @14186 |
| 5342 | /* 14186 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 365*/ GIMT_Encode4(14234), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1152 // |
| 5343 | /* 14193 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5344 | /* 14197 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5345 | /* 14201 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5346 | /* 14205 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5347 | /* 14210 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5348 | /* 14212 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5349 | /* 14212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16), |
| 5350 | /* 14215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5351 | /* 14217 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5352 | /* 14219 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5353 | /* 14223 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5354 | /* 14226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5355 | /* 14232 */ GIR_RootConstrainSelectedInstOperands, |
| 5356 | /* 14233 */ // GIR_Coverage, 1152, |
| 5357 | /* 14233 */ GIR_EraseRootFromParent_Done, |
| 5358 | /* 14234 */ // Label 365: @14234 |
| 5359 | /* 14234 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 366*/ GIMT_Encode4(14265), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1126 // |
| 5360 | /* 14241 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5361 | /* 14245 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 5362 | /* 14245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i16), |
| 5363 | /* 14248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5364 | /* 14250 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5365 | /* 14252 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5366 | /* 14254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5367 | /* 14257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5368 | /* 14263 */ GIR_RootConstrainSelectedInstOperands, |
| 5369 | /* 14264 */ // GIR_Coverage, 1126, |
| 5370 | /* 14264 */ GIR_EraseRootFromParent_Done, |
| 5371 | /* 14265 */ // Label 366: @14265 |
| 5372 | /* 14265 */ GIM_Reject, |
| 5373 | /* 14266 */ // Label 361: @14266 |
| 5374 | /* 14266 */ GIM_Reject, |
| 5375 | /* 14267 */ // Label 355: @14267 |
| 5376 | /* 14267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 367*/ GIMT_Encode4(14327), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3901 // |
| 5377 | /* 14274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5378 | /* 14278 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5379 | /* 14282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5380 | /* 14286 */ // (sub:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VSUBi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 5381 | /* 14286 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5382 | /* 14289 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5383 | /* 14293 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 5384 | /* 14298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi16), |
| 5385 | /* 14301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5386 | /* 14303 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5387 | /* 14305 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5388 | /* 14307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5389 | /* 14310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5390 | /* 14316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5391 | /* 14322 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5392 | /* 14325 */ GIR_RootConstrainSelectedInstOperands, |
| 5393 | /* 14326 */ // GIR_Coverage, 3901, |
| 5394 | /* 14326 */ GIR_EraseRootFromParent_Done, |
| 5395 | /* 14327 */ // Label 367: @14327 |
| 5396 | /* 14327 */ GIM_Reject, |
| 5397 | /* 14328 */ // Label 354: @14328 |
| 5398 | /* 14328 */ GIM_Reject, |
| 5399 | /* 14329 */ // Label 325: @14329 |
| 5400 | /* 14329 */ GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(14441), |
| 5401 | /* 14334 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5402 | /* 14337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 5403 | /* 14340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5404 | /* 14344 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5405 | /* 14348 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 369*/ GIMT_Encode4(14409), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1055 // |
| 5406 | /* 14355 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5407 | /* 14359 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5408 | /* 14363 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5409 | /* 14367 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 5410 | /* 14371 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5411 | /* 14376 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5412 | /* 14381 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5413 | /* 14383 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5414 | /* 14383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv2i32), |
| 5415 | /* 14386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5416 | /* 14388 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5417 | /* 14390 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5418 | /* 14394 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5419 | /* 14398 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5420 | /* 14401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5421 | /* 14407 */ GIR_RootConstrainSelectedInstOperands, |
| 5422 | /* 14408 */ // GIR_Coverage, 1055, |
| 5423 | /* 14408 */ GIR_EraseRootFromParent_Done, |
| 5424 | /* 14409 */ // Label 369: @14409 |
| 5425 | /* 14409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 370*/ GIMT_Encode4(14440), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1124 // |
| 5426 | /* 14416 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5427 | /* 14420 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5428 | /* 14420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i32), |
| 5429 | /* 14423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5430 | /* 14425 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5431 | /* 14427 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5432 | /* 14429 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5433 | /* 14432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5434 | /* 14438 */ GIR_RootConstrainSelectedInstOperands, |
| 5435 | /* 14439 */ // GIR_Coverage, 1124, |
| 5436 | /* 14439 */ GIR_EraseRootFromParent_Done, |
| 5437 | /* 14440 */ // Label 370: @14440 |
| 5438 | /* 14440 */ GIM_Reject, |
| 5439 | /* 14441 */ // Label 368: @14441 |
| 5440 | /* 14441 */ GIM_Reject, |
| 5441 | /* 14442 */ // Label 326: @14442 |
| 5442 | /* 14442 */ GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(15105), |
| 5443 | /* 14447 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 5444 | /* 14450 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5445 | /* 14453 */ GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(15044), |
| 5446 | /* 14458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5447 | /* 14462 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 373*/ GIMT_Encode4(14529), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1144 // |
| 5448 | /* 14469 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5449 | /* 14473 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5450 | /* 14477 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5451 | /* 14481 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5452 | /* 14486 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5453 | /* 14490 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5454 | /* 14494 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5455 | /* 14498 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5456 | /* 14503 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5457 | /* 14505 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5458 | /* 14505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 5459 | /* 14508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5460 | /* 14510 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5461 | /* 14514 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5462 | /* 14518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5463 | /* 14521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5464 | /* 14527 */ GIR_RootConstrainSelectedInstOperands, |
| 5465 | /* 14528 */ // GIR_Coverage, 1144, |
| 5466 | /* 14528 */ GIR_EraseRootFromParent_Done, |
| 5467 | /* 14529 */ // Label 373: @14529 |
| 5468 | /* 14529 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 374*/ GIMT_Encode4(14596), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1143 // |
| 5469 | /* 14536 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5470 | /* 14540 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5471 | /* 14544 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5472 | /* 14548 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5473 | /* 14553 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5474 | /* 14557 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5475 | /* 14561 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5476 | /* 14565 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5477 | /* 14570 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5478 | /* 14572 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5479 | /* 14572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 5480 | /* 14575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5481 | /* 14577 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5482 | /* 14581 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5483 | /* 14585 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5484 | /* 14588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5485 | /* 14594 */ GIR_RootConstrainSelectedInstOperands, |
| 5486 | /* 14595 */ // GIR_Coverage, 1143, |
| 5487 | /* 14595 */ GIR_EraseRootFromParent_Done, |
| 5488 | /* 14596 */ // Label 374: @14596 |
| 5489 | /* 14596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 375*/ GIMT_Encode4(14663), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1135 // |
| 5490 | /* 14603 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5491 | /* 14607 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5492 | /* 14611 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5493 | /* 14615 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5494 | /* 14620 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5495 | /* 14624 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5496 | /* 14628 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5497 | /* 14632 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5498 | /* 14637 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5499 | /* 14639 */ // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5500 | /* 14639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv4i32), |
| 5501 | /* 14642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5502 | /* 14644 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5503 | /* 14648 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5504 | /* 14652 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5505 | /* 14655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5506 | /* 14661 */ GIR_RootConstrainSelectedInstOperands, |
| 5507 | /* 14662 */ // GIR_Coverage, 1135, |
| 5508 | /* 14662 */ GIR_EraseRootFromParent_Done, |
| 5509 | /* 14663 */ // Label 375: @14663 |
| 5510 | /* 14663 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 376*/ GIMT_Encode4(14730), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1142 // |
| 5511 | /* 14670 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5512 | /* 14674 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5513 | /* 14678 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5514 | /* 14682 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5515 | /* 14687 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5516 | /* 14691 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5517 | /* 14695 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5518 | /* 14699 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5519 | /* 14704 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5520 | /* 14706 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5521 | /* 14706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 5522 | /* 14709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5523 | /* 14711 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5524 | /* 14715 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5525 | /* 14719 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5526 | /* 14722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5527 | /* 14728 */ GIR_RootConstrainSelectedInstOperands, |
| 5528 | /* 14729 */ // GIR_Coverage, 1142, |
| 5529 | /* 14729 */ GIR_EraseRootFromParent_Done, |
| 5530 | /* 14730 */ // Label 376: @14730 |
| 5531 | /* 14730 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 377*/ GIMT_Encode4(14797), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1141 // |
| 5532 | /* 14737 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5533 | /* 14741 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5534 | /* 14745 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5535 | /* 14749 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5536 | /* 14754 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5537 | /* 14758 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5538 | /* 14762 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5539 | /* 14766 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5540 | /* 14771 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5541 | /* 14773 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5542 | /* 14773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 5543 | /* 14776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5544 | /* 14778 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5545 | /* 14782 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5546 | /* 14786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5547 | /* 14789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5548 | /* 14795 */ GIR_RootConstrainSelectedInstOperands, |
| 5549 | /* 14796 */ // GIR_Coverage, 1141, |
| 5550 | /* 14796 */ GIR_EraseRootFromParent_Done, |
| 5551 | /* 14797 */ // Label 377: @14797 |
| 5552 | /* 14797 */ GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(15043), |
| 5553 | /* 14802 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5554 | /* 14806 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 379*/ GIMT_Encode4(14867), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1058 // |
| 5555 | /* 14813 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5556 | /* 14817 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5557 | /* 14821 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 5558 | /* 14825 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5559 | /* 14829 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5560 | /* 14834 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5561 | /* 14839 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5562 | /* 14841 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 5563 | /* 14841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i32), |
| 5564 | /* 14844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5565 | /* 14846 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5566 | /* 14848 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5567 | /* 14852 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5568 | /* 14856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5569 | /* 14859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5570 | /* 14865 */ GIR_RootConstrainSelectedInstOperands, |
| 5571 | /* 14866 */ // GIR_Coverage, 1058, |
| 5572 | /* 14866 */ GIR_EraseRootFromParent_Done, |
| 5573 | /* 14867 */ // Label 379: @14867 |
| 5574 | /* 14867 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 380*/ GIMT_Encode4(14915), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1155 // |
| 5575 | /* 14874 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5576 | /* 14878 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5577 | /* 14882 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5578 | /* 14886 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5579 | /* 14891 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5580 | /* 14893 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5581 | /* 14893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32), |
| 5582 | /* 14896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5583 | /* 14898 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5584 | /* 14900 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5585 | /* 14904 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5586 | /* 14907 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5587 | /* 14913 */ GIR_RootConstrainSelectedInstOperands, |
| 5588 | /* 14914 */ // GIR_Coverage, 1155, |
| 5589 | /* 14914 */ GIR_EraseRootFromParent_Done, |
| 5590 | /* 14915 */ // Label 380: @14915 |
| 5591 | /* 14915 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 381*/ GIMT_Encode4(14963), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1150 // |
| 5592 | /* 14922 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5593 | /* 14926 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5594 | /* 14930 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5595 | /* 14934 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5596 | /* 14939 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5597 | /* 14941 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5598 | /* 14941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv4i32), |
| 5599 | /* 14944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5600 | /* 14946 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5601 | /* 14948 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5602 | /* 14952 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5603 | /* 14955 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5604 | /* 14961 */ GIR_RootConstrainSelectedInstOperands, |
| 5605 | /* 14962 */ // GIR_Coverage, 1150, |
| 5606 | /* 14962 */ GIR_EraseRootFromParent_Done, |
| 5607 | /* 14963 */ // Label 381: @14963 |
| 5608 | /* 14963 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 382*/ GIMT_Encode4(15011), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1154 // |
| 5609 | /* 14970 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5610 | /* 14974 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5611 | /* 14978 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5612 | /* 14982 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5613 | /* 14987 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5614 | /* 14989 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5615 | /* 14989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32), |
| 5616 | /* 14992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5617 | /* 14994 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5618 | /* 14996 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5619 | /* 15000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5620 | /* 15003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5621 | /* 15009 */ GIR_RootConstrainSelectedInstOperands, |
| 5622 | /* 15010 */ // GIR_Coverage, 1154, |
| 5623 | /* 15010 */ GIR_EraseRootFromParent_Done, |
| 5624 | /* 15011 */ // Label 382: @15011 |
| 5625 | /* 15011 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 383*/ GIMT_Encode4(15042), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1127 // |
| 5626 | /* 15018 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5627 | /* 15022 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 5628 | /* 15022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i32), |
| 5629 | /* 15025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5630 | /* 15027 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5631 | /* 15029 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5632 | /* 15031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5633 | /* 15034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5634 | /* 15040 */ GIR_RootConstrainSelectedInstOperands, |
| 5635 | /* 15041 */ // GIR_Coverage, 1127, |
| 5636 | /* 15041 */ GIR_EraseRootFromParent_Done, |
| 5637 | /* 15042 */ // Label 383: @15042 |
| 5638 | /* 15042 */ GIM_Reject, |
| 5639 | /* 15043 */ // Label 378: @15043 |
| 5640 | /* 15043 */ GIM_Reject, |
| 5641 | /* 15044 */ // Label 372: @15044 |
| 5642 | /* 15044 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 384*/ GIMT_Encode4(15104), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3905 // |
| 5643 | /* 15051 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5644 | /* 15055 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5645 | /* 15059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5646 | /* 15063 */ // (sub:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VSUBi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 5647 | /* 15063 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5648 | /* 15066 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5649 | /* 15070 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 5650 | /* 15075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi32), |
| 5651 | /* 15078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5652 | /* 15080 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5653 | /* 15082 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5654 | /* 15084 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5655 | /* 15087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5656 | /* 15093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5657 | /* 15099 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5658 | /* 15102 */ GIR_RootConstrainSelectedInstOperands, |
| 5659 | /* 15103 */ // GIR_Coverage, 3905, |
| 5660 | /* 15103 */ GIR_EraseRootFromParent_Done, |
| 5661 | /* 15104 */ // Label 384: @15104 |
| 5662 | /* 15104 */ GIM_Reject, |
| 5663 | /* 15105 */ // Label 371: @15105 |
| 5664 | /* 15105 */ GIM_Reject, |
| 5665 | /* 15106 */ // Label 327: @15106 |
| 5666 | /* 15106 */ GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(15642), |
| 5667 | /* 15111 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 5668 | /* 15114 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5669 | /* 15117 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5670 | /* 15121 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 386*/ GIMT_Encode4(15188), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1148 // |
| 5671 | /* 15128 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5672 | /* 15132 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5673 | /* 15136 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5674 | /* 15140 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5675 | /* 15145 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5676 | /* 15149 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5677 | /* 15153 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5678 | /* 15157 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5679 | /* 15162 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5680 | /* 15164 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5681 | /* 15164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 5682 | /* 15167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5683 | /* 15169 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5684 | /* 15173 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5685 | /* 15177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5686 | /* 15180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5687 | /* 15186 */ GIR_RootConstrainSelectedInstOperands, |
| 5688 | /* 15187 */ // GIR_Coverage, 1148, |
| 5689 | /* 15187 */ GIR_EraseRootFromParent_Done, |
| 5690 | /* 15188 */ // Label 386: @15188 |
| 5691 | /* 15188 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 387*/ GIMT_Encode4(15255), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1147 // |
| 5692 | /* 15195 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5693 | /* 15199 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5694 | /* 15203 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5695 | /* 15207 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5696 | /* 15212 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5697 | /* 15216 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5698 | /* 15220 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5699 | /* 15224 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5700 | /* 15229 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5701 | /* 15231 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5702 | /* 15231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 5703 | /* 15234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5704 | /* 15236 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5705 | /* 15240 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5706 | /* 15244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5707 | /* 15247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5708 | /* 15253 */ GIR_RootConstrainSelectedInstOperands, |
| 5709 | /* 15254 */ // GIR_Coverage, 1147, |
| 5710 | /* 15254 */ GIR_EraseRootFromParent_Done, |
| 5711 | /* 15255 */ // Label 387: @15255 |
| 5712 | /* 15255 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 388*/ GIMT_Encode4(15322), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1136 // |
| 5713 | /* 15262 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5714 | /* 15266 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5715 | /* 15270 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5716 | /* 15274 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5717 | /* 15279 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5718 | /* 15283 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5719 | /* 15287 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5720 | /* 15291 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5721 | /* 15296 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5722 | /* 15298 */ // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5723 | /* 15298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv2i64), |
| 5724 | /* 15301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5725 | /* 15303 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5726 | /* 15307 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5727 | /* 15311 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5728 | /* 15314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5729 | /* 15320 */ GIR_RootConstrainSelectedInstOperands, |
| 5730 | /* 15321 */ // GIR_Coverage, 1136, |
| 5731 | /* 15321 */ GIR_EraseRootFromParent_Done, |
| 5732 | /* 15322 */ // Label 388: @15322 |
| 5733 | /* 15322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 389*/ GIMT_Encode4(15389), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1146 // |
| 5734 | /* 15329 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5735 | /* 15333 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5736 | /* 15337 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5737 | /* 15341 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5738 | /* 15346 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5739 | /* 15350 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5740 | /* 15354 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5741 | /* 15358 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5742 | /* 15363 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5743 | /* 15365 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5744 | /* 15365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 5745 | /* 15368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5746 | /* 15370 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5747 | /* 15374 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5748 | /* 15378 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5749 | /* 15381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5750 | /* 15387 */ GIR_RootConstrainSelectedInstOperands, |
| 5751 | /* 15388 */ // GIR_Coverage, 1146, |
| 5752 | /* 15388 */ GIR_EraseRootFromParent_Done, |
| 5753 | /* 15389 */ // Label 389: @15389 |
| 5754 | /* 15389 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 390*/ GIMT_Encode4(15456), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1145 // |
| 5755 | /* 15396 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5756 | /* 15400 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5757 | /* 15404 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5758 | /* 15408 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5759 | /* 15413 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5760 | /* 15417 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5761 | /* 15421 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5762 | /* 15425 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5763 | /* 15430 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5764 | /* 15432 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5765 | /* 15432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 5766 | /* 15435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5767 | /* 15437 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5768 | /* 15441 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5769 | /* 15445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5770 | /* 15448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5771 | /* 15454 */ GIR_RootConstrainSelectedInstOperands, |
| 5772 | /* 15455 */ // GIR_Coverage, 1145, |
| 5773 | /* 15455 */ GIR_EraseRootFromParent_Done, |
| 5774 | /* 15456 */ // Label 390: @15456 |
| 5775 | /* 15456 */ GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(15641), |
| 5776 | /* 15461 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5777 | /* 15465 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 392*/ GIMT_Encode4(15513), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1157 // |
| 5778 | /* 15472 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5779 | /* 15476 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5780 | /* 15480 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5781 | /* 15484 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5782 | /* 15489 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5783 | /* 15491 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5784 | /* 15491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64), |
| 5785 | /* 15494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5786 | /* 15496 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5787 | /* 15498 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5788 | /* 15502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5789 | /* 15505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5790 | /* 15511 */ GIR_RootConstrainSelectedInstOperands, |
| 5791 | /* 15512 */ // GIR_Coverage, 1157, |
| 5792 | /* 15512 */ GIR_EraseRootFromParent_Done, |
| 5793 | /* 15513 */ // Label 392: @15513 |
| 5794 | /* 15513 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 393*/ GIMT_Encode4(15561), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1151 // |
| 5795 | /* 15520 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5796 | /* 15524 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5797 | /* 15528 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5798 | /* 15532 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5799 | /* 15537 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5800 | /* 15539 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5801 | /* 15539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv2i64), |
| 5802 | /* 15542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5803 | /* 15544 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5804 | /* 15546 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5805 | /* 15550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5806 | /* 15553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5807 | /* 15559 */ GIR_RootConstrainSelectedInstOperands, |
| 5808 | /* 15560 */ // GIR_Coverage, 1151, |
| 5809 | /* 15560 */ GIR_EraseRootFromParent_Done, |
| 5810 | /* 15561 */ // Label 393: @15561 |
| 5811 | /* 15561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 394*/ GIMT_Encode4(15609), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1156 // |
| 5812 | /* 15568 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5813 | /* 15572 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5814 | /* 15576 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5815 | /* 15580 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5816 | /* 15585 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5817 | /* 15587 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5818 | /* 15587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64), |
| 5819 | /* 15590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5820 | /* 15592 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5821 | /* 15594 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5822 | /* 15598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5823 | /* 15601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5824 | /* 15607 */ GIR_RootConstrainSelectedInstOperands, |
| 5825 | /* 15608 */ // GIR_Coverage, 1156, |
| 5826 | /* 15608 */ GIR_EraseRootFromParent_Done, |
| 5827 | /* 15609 */ // Label 394: @15609 |
| 5828 | /* 15609 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 395*/ GIMT_Encode4(15640), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1129 // |
| 5829 | /* 15616 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5830 | /* 15620 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 5831 | /* 15620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i64), |
| 5832 | /* 15623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5833 | /* 15625 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5834 | /* 15627 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5835 | /* 15629 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5836 | /* 15632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5837 | /* 15638 */ GIR_RootConstrainSelectedInstOperands, |
| 5838 | /* 15639 */ // GIR_Coverage, 1129, |
| 5839 | /* 15639 */ GIR_EraseRootFromParent_Done, |
| 5840 | /* 15640 */ // Label 395: @15640 |
| 5841 | /* 15640 */ GIM_Reject, |
| 5842 | /* 15641 */ // Label 391: @15641 |
| 5843 | /* 15641 */ GIM_Reject, |
| 5844 | /* 15642 */ // Label 385: @15642 |
| 5845 | /* 15642 */ GIM_Reject, |
| 5846 | /* 15643 */ // Label 328: @15643 |
| 5847 | /* 15643 */ GIM_Reject, |
| 5848 | /* 15644 */ // Label 2: @15644 |
| 5849 | /* 15644 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 403*/ GIMT_Encode4(17306), |
| 5850 | /* 15655 */ /*GILLT_s32*//*Label 396*/ GIMT_Encode4(15703), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 5851 | /* 15679 */ /*GILLT_v8s8*//*Label 397*/ GIMT_Encode4(16604), |
| 5852 | /* 15683 */ /*GILLT_v16s8*//*Label 398*/ GIMT_Encode4(16650), |
| 5853 | /* 15687 */ /*GILLT_v4s16*//*Label 399*/ GIMT_Encode4(16762), |
| 5854 | /* 15691 */ /*GILLT_v8s16*//*Label 400*/ GIMT_Encode4(16808), |
| 5855 | /* 15695 */ /*GILLT_v2s32*//*Label 401*/ GIMT_Encode4(17034), |
| 5856 | /* 15699 */ /*GILLT_v4s32*//*Label 402*/ GIMT_Encode4(17080), |
| 5857 | /* 15703 */ // Label 396: @15703 |
| 5858 | /* 15703 */ GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(16603), |
| 5859 | /* 15708 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 5860 | /* 15711 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 5861 | /* 15714 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 405*/ GIMT_Encode4(15801), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 185 // |
| 5862 | /* 15721 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5863 | /* 15725 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5864 | /* 15729 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5865 | /* 15733 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5866 | /* 15737 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5867 | /* 15741 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5868 | /* 15746 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 5869 | /* 15750 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5870 | /* 15754 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5871 | /* 15758 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5872 | /* 15762 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5873 | /* 15766 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5874 | /* 15771 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 5875 | /* 15775 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5876 | /* 15777 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 5877 | /* 15777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT), |
| 5878 | /* 15780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5879 | /* 15782 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5880 | /* 15786 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5881 | /* 15790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5882 | /* 15793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5883 | /* 15799 */ GIR_RootConstrainSelectedInstOperands, |
| 5884 | /* 15800 */ // GIR_Coverage, 185, |
| 5885 | /* 15800 */ GIR_EraseRootFromParent_Done, |
| 5886 | /* 15801 */ // Label 405: @15801 |
| 5887 | /* 15801 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 406*/ GIMT_Encode4(15888), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 514 // |
| 5888 | /* 15808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5889 | /* 15812 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5890 | /* 15816 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5891 | /* 15820 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5892 | /* 15824 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5893 | /* 15828 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5894 | /* 15833 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 5895 | /* 15837 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5896 | /* 15841 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5897 | /* 15845 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5898 | /* 15849 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5899 | /* 15853 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5900 | /* 15858 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 5901 | /* 15862 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5902 | /* 15864 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 5903 | /* 15864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT), |
| 5904 | /* 15867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5905 | /* 15869 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5906 | /* 15873 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5907 | /* 15877 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5908 | /* 15880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5909 | /* 15886 */ GIR_RootConstrainSelectedInstOperands, |
| 5910 | /* 15887 */ // GIR_Coverage, 514, |
| 5911 | /* 15887 */ GIR_EraseRootFromParent_Done, |
| 5912 | /* 15888 */ // Label 406: @15888 |
| 5913 | /* 15888 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 407*/ GIMT_Encode4(15978), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 184 // |
| 5914 | /* 15895 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5915 | /* 15899 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5916 | /* 15903 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5917 | /* 15907 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5918 | /* 15911 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5919 | /* 15915 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5920 | /* 15920 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 5921 | /* 15924 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5922 | /* 15928 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5923 | /* 15932 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5924 | /* 15936 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5925 | /* 15941 */ // MIs[2] Operand 2 |
| 5926 | /* 15941 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 5927 | /* 15952 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5928 | /* 15954 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 5929 | /* 15954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB), |
| 5930 | /* 15957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5931 | /* 15959 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5932 | /* 15963 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5933 | /* 15967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5934 | /* 15970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5935 | /* 15976 */ GIR_RootConstrainSelectedInstOperands, |
| 5936 | /* 15977 */ // GIR_Coverage, 184, |
| 5937 | /* 15977 */ GIR_EraseRootFromParent_Done, |
| 5938 | /* 15978 */ // Label 407: @15978 |
| 5939 | /* 15978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 408*/ GIMT_Encode4(16068), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 513 // |
| 5940 | /* 15985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5941 | /* 15989 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5942 | /* 15993 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5943 | /* 15997 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5944 | /* 16001 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5945 | /* 16005 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5946 | /* 16010 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 5947 | /* 16014 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5948 | /* 16018 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5949 | /* 16022 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5950 | /* 16026 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5951 | /* 16031 */ // MIs[2] Operand 2 |
| 5952 | /* 16031 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 5953 | /* 16042 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5954 | /* 16044 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 5955 | /* 16044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB), |
| 5956 | /* 16047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5957 | /* 16049 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5958 | /* 16053 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5959 | /* 16057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5960 | /* 16060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5961 | /* 16066 */ GIR_RootConstrainSelectedInstOperands, |
| 5962 | /* 16067 */ // GIR_Coverage, 513, |
| 5963 | /* 16067 */ GIR_EraseRootFromParent_Done, |
| 5964 | /* 16068 */ // Label 408: @16068 |
| 5965 | /* 16068 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 409*/ GIMT_Encode4(16158), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 183 // |
| 5966 | /* 16075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5967 | /* 16079 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5968 | /* 16083 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5969 | /* 16087 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5970 | /* 16091 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5971 | /* 16096 */ // MIs[1] Operand 2 |
| 5972 | /* 16096 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 5973 | /* 16107 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5974 | /* 16111 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5975 | /* 16115 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5976 | /* 16119 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5977 | /* 16123 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5978 | /* 16128 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 5979 | /* 16132 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5980 | /* 16134 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 5981 | /* 16134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT), |
| 5982 | /* 16137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5983 | /* 16139 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5984 | /* 16143 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5985 | /* 16147 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5986 | /* 16150 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5987 | /* 16156 */ GIR_RootConstrainSelectedInstOperands, |
| 5988 | /* 16157 */ // GIR_Coverage, 183, |
| 5989 | /* 16157 */ GIR_EraseRootFromParent_Done, |
| 5990 | /* 16158 */ // Label 409: @16158 |
| 5991 | /* 16158 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 410*/ GIMT_Encode4(16248), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 512 // |
| 5992 | /* 16165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5993 | /* 16169 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5994 | /* 16173 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5995 | /* 16177 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5996 | /* 16181 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5997 | /* 16186 */ // MIs[1] Operand 2 |
| 5998 | /* 16186 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 5999 | /* 16197 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6000 | /* 16201 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 6001 | /* 16205 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6002 | /* 16209 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 6003 | /* 16213 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6004 | /* 16218 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 6005 | /* 16222 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6006 | /* 16224 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6007 | /* 16224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT), |
| 6008 | /* 16227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6009 | /* 16229 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6010 | /* 16233 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6011 | /* 16237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6012 | /* 16240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6013 | /* 16246 */ GIR_RootConstrainSelectedInstOperands, |
| 6014 | /* 16247 */ // GIR_Coverage, 512, |
| 6015 | /* 16247 */ GIR_EraseRootFromParent_Done, |
| 6016 | /* 16248 */ // Label 410: @16248 |
| 6017 | /* 16248 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 411*/ GIMT_Encode4(16341), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 182 // |
| 6018 | /* 16255 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6019 | /* 16259 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6020 | /* 16263 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6021 | /* 16267 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6022 | /* 16271 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6023 | /* 16276 */ // MIs[1] Operand 2 |
| 6024 | /* 16276 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 6025 | /* 16287 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6026 | /* 16291 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6027 | /* 16295 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6028 | /* 16299 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6029 | /* 16304 */ // MIs[2] Operand 2 |
| 6030 | /* 16304 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 6031 | /* 16315 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6032 | /* 16317 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6033 | /* 16317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB), |
| 6034 | /* 16320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6035 | /* 16322 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6036 | /* 16326 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6037 | /* 16330 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6038 | /* 16333 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6039 | /* 16339 */ GIR_RootConstrainSelectedInstOperands, |
| 6040 | /* 16340 */ // GIR_Coverage, 182, |
| 6041 | /* 16340 */ GIR_EraseRootFromParent_Done, |
| 6042 | /* 16341 */ // Label 411: @16341 |
| 6043 | /* 16341 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 412*/ GIMT_Encode4(16434), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 511 // |
| 6044 | /* 16348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6045 | /* 16352 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6046 | /* 16356 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6047 | /* 16360 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6048 | /* 16364 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6049 | /* 16369 */ // MIs[1] Operand 2 |
| 6050 | /* 16369 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 6051 | /* 16380 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6052 | /* 16384 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6053 | /* 16388 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6054 | /* 16392 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6055 | /* 16397 */ // MIs[2] Operand 2 |
| 6056 | /* 16397 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 6057 | /* 16408 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6058 | /* 16410 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6059 | /* 16410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB), |
| 6060 | /* 16413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6061 | /* 16415 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6062 | /* 16419 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6063 | /* 16423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6064 | /* 16426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6065 | /* 16432 */ GIR_RootConstrainSelectedInstOperands, |
| 6066 | /* 16433 */ // GIR_Coverage, 511, |
| 6067 | /* 16433 */ GIR_EraseRootFromParent_Done, |
| 6068 | /* 16434 */ // Label 412: @16434 |
| 6069 | /* 16434 */ GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(16518), |
| 6070 | /* 16439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6071 | /* 16443 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6072 | /* 16447 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6073 | /* 16451 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 414*/ GIMT_Encode4(16484), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 168 // |
| 6074 | /* 16458 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 6075 | /* 16458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MUL), |
| 6076 | /* 16461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6077 | /* 16463 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6078 | /* 16465 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6079 | /* 16467 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6080 | /* 16470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6081 | /* 16476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6082 | /* 16482 */ GIR_RootConstrainSelectedInstOperands, |
| 6083 | /* 16483 */ // GIR_Coverage, 168, |
| 6084 | /* 16483 */ GIR_EraseRootFromParent_Done, |
| 6085 | /* 16484 */ // Label 414: @16484 |
| 6086 | /* 16484 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 415*/ GIMT_Encode4(16517), GIMT_Encode2(GIFBS_IsARM_NoV6_UseMulOps), // Rule ID 169 // |
| 6087 | /* 16491 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 6088 | /* 16491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MULv5), |
| 6089 | /* 16494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6090 | /* 16496 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6091 | /* 16498 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6092 | /* 16500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6093 | /* 16503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6094 | /* 16509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6095 | /* 16515 */ GIR_RootConstrainSelectedInstOperands, |
| 6096 | /* 16516 */ // GIR_Coverage, 169, |
| 6097 | /* 16516 */ GIR_EraseRootFromParent_Done, |
| 6098 | /* 16517 */ // Label 415: @16517 |
| 6099 | /* 16517 */ GIM_Reject, |
| 6100 | /* 16518 */ // Label 413: @16518 |
| 6101 | /* 16518 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 416*/ GIMT_Encode4(16563), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 322 // |
| 6102 | /* 16525 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6103 | /* 16529 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6104 | /* 16533 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6105 | /* 16537 */ // (mul:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tMUL:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 6106 | /* 16537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMUL), |
| 6107 | /* 16540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6108 | /* 16542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 6109 | /* 16548 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6110 | /* 16550 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6111 | /* 16552 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6112 | /* 16555 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6113 | /* 16561 */ GIR_RootConstrainSelectedInstOperands, |
| 6114 | /* 16562 */ // GIR_Coverage, 322, |
| 6115 | /* 16562 */ GIR_EraseRootFromParent_Done, |
| 6116 | /* 16563 */ // Label 416: @16563 |
| 6117 | /* 16563 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 417*/ GIMT_Encode4(16602), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 501 // |
| 6118 | /* 16570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6119 | /* 16574 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6120 | /* 16578 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6121 | /* 16582 */ // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6122 | /* 16582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MUL), |
| 6123 | /* 16585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6124 | /* 16587 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6125 | /* 16589 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6126 | /* 16591 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6127 | /* 16594 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6128 | /* 16600 */ GIR_RootConstrainSelectedInstOperands, |
| 6129 | /* 16601 */ // GIR_Coverage, 501, |
| 6130 | /* 16601 */ GIR_EraseRootFromParent_Done, |
| 6131 | /* 16602 */ // Label 417: @16602 |
| 6132 | /* 16602 */ GIM_Reject, |
| 6133 | /* 16603 */ // Label 404: @16603 |
| 6134 | /* 16603 */ GIM_Reject, |
| 6135 | /* 16604 */ // Label 397: @16604 |
| 6136 | /* 16604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 418*/ GIMT_Encode4(16649), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 955 // |
| 6137 | /* 16611 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 6138 | /* 16614 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 6139 | /* 16617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6140 | /* 16621 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6141 | /* 16625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6142 | /* 16629 */ // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 6143 | /* 16629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i8), |
| 6144 | /* 16632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6145 | /* 16634 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6146 | /* 16636 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6147 | /* 16638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6148 | /* 16641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6149 | /* 16647 */ GIR_RootConstrainSelectedInstOperands, |
| 6150 | /* 16648 */ // GIR_Coverage, 955, |
| 6151 | /* 16648 */ GIR_EraseRootFromParent_Done, |
| 6152 | /* 16649 */ // Label 418: @16649 |
| 6153 | /* 16649 */ GIM_Reject, |
| 6154 | /* 16650 */ // Label 398: @16650 |
| 6155 | /* 16650 */ GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(16761), |
| 6156 | /* 16655 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 6157 | /* 16658 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6158 | /* 16661 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 420*/ GIMT_Encode4(16700), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 958 // |
| 6159 | /* 16668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6160 | /* 16672 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6161 | /* 16676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6162 | /* 16680 */ // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 6163 | /* 16680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv16i8), |
| 6164 | /* 16683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6165 | /* 16685 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6166 | /* 16687 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6167 | /* 16689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6168 | /* 16692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6169 | /* 16698 */ GIR_RootConstrainSelectedInstOperands, |
| 6170 | /* 16699 */ // GIR_Coverage, 958, |
| 6171 | /* 16699 */ GIR_EraseRootFromParent_Done, |
| 6172 | /* 16700 */ // Label 420: @16700 |
| 6173 | /* 16700 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 421*/ GIMT_Encode4(16760), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3855 // |
| 6174 | /* 16707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6175 | /* 16711 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6176 | /* 16715 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6177 | /* 16719 */ // (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 6178 | /* 16719 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6179 | /* 16722 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6180 | /* 16726 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6181 | /* 16731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi8), |
| 6182 | /* 16734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6183 | /* 16736 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 6184 | /* 16738 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 6185 | /* 16740 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6186 | /* 16743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6187 | /* 16749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6188 | /* 16755 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6189 | /* 16758 */ GIR_RootConstrainSelectedInstOperands, |
| 6190 | /* 16759 */ // GIR_Coverage, 3855, |
| 6191 | /* 16759 */ GIR_EraseRootFromParent_Done, |
| 6192 | /* 16760 */ // Label 421: @16760 |
| 6193 | /* 16760 */ GIM_Reject, |
| 6194 | /* 16761 */ // Label 419: @16761 |
| 6195 | /* 16761 */ GIM_Reject, |
| 6196 | /* 16762 */ // Label 399: @16762 |
| 6197 | /* 16762 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 422*/ GIMT_Encode4(16807), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 956 // |
| 6198 | /* 16769 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6199 | /* 16772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 6200 | /* 16775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6201 | /* 16779 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6202 | /* 16783 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6203 | /* 16787 */ // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 6204 | /* 16787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i16), |
| 6205 | /* 16790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6206 | /* 16792 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6207 | /* 16794 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6208 | /* 16796 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6209 | /* 16799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6210 | /* 16805 */ GIR_RootConstrainSelectedInstOperands, |
| 6211 | /* 16806 */ // GIR_Coverage, 956, |
| 6212 | /* 16806 */ GIR_EraseRootFromParent_Done, |
| 6213 | /* 16807 */ // Label 422: @16807 |
| 6214 | /* 16807 */ GIM_Reject, |
| 6215 | /* 16808 */ // Label 400: @16808 |
| 6216 | /* 16808 */ GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(17033), |
| 6217 | /* 16813 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 6218 | /* 16816 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6219 | /* 16819 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 424*/ GIMT_Encode4(16933), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4937 // |
| 6220 | /* 16826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6221 | /* 16830 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6222 | /* 16834 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6223 | /* 16838 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 6224 | /* 16842 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6225 | /* 16847 */ // MIs[1] Operand 2 |
| 6226 | /* 16847 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 6227 | /* 16858 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6228 | /* 16862 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6229 | /* 16866 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 6230 | /* 16870 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6231 | /* 16875 */ // MIs[2] Operand 2 |
| 6232 | /* 16875 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8), |
| 6233 | /* 16886 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6234 | /* 16888 */ // (mul:{ *:[v8i16] } (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, v8i8:{ *:[Other] }), (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src2, v8i8:{ *:[Other] })) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2) |
| 6235 | /* 16888 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6236 | /* 16891 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6237 | /* 16895 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6238 | /* 16900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8), |
| 6239 | /* 16903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6240 | /* 16905 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 6241 | /* 16909 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 6242 | /* 16913 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6243 | /* 16916 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6244 | /* 16922 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6245 | /* 16928 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6246 | /* 16931 */ GIR_RootConstrainSelectedInstOperands, |
| 6247 | /* 16932 */ // GIR_Coverage, 4937, |
| 6248 | /* 16932 */ GIR_EraseRootFromParent_Done, |
| 6249 | /* 16933 */ // Label 424: @16933 |
| 6250 | /* 16933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 425*/ GIMT_Encode4(16972), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 959 // |
| 6251 | /* 16940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6252 | /* 16944 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6253 | /* 16948 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6254 | /* 16952 */ // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 6255 | /* 16952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i16), |
| 6256 | /* 16955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6257 | /* 16957 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6258 | /* 16959 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6259 | /* 16961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6260 | /* 16964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6261 | /* 16970 */ GIR_RootConstrainSelectedInstOperands, |
| 6262 | /* 16971 */ // GIR_Coverage, 959, |
| 6263 | /* 16971 */ GIR_EraseRootFromParent_Done, |
| 6264 | /* 16972 */ // Label 425: @16972 |
| 6265 | /* 16972 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 426*/ GIMT_Encode4(17032), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3859 // |
| 6266 | /* 16979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6267 | /* 16983 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6268 | /* 16987 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6269 | /* 16991 */ // (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 6270 | /* 16991 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6271 | /* 16994 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6272 | /* 16998 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6273 | /* 17003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi16), |
| 6274 | /* 17006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6275 | /* 17008 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 6276 | /* 17010 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 6277 | /* 17012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6278 | /* 17015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6279 | /* 17021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6280 | /* 17027 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6281 | /* 17030 */ GIR_RootConstrainSelectedInstOperands, |
| 6282 | /* 17031 */ // GIR_Coverage, 3859, |
| 6283 | /* 17031 */ GIR_EraseRootFromParent_Done, |
| 6284 | /* 17032 */ // Label 426: @17032 |
| 6285 | /* 17032 */ GIM_Reject, |
| 6286 | /* 17033 */ // Label 423: @17033 |
| 6287 | /* 17033 */ GIM_Reject, |
| 6288 | /* 17034 */ // Label 401: @17034 |
| 6289 | /* 17034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 427*/ GIMT_Encode4(17079), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 957 // |
| 6290 | /* 17041 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6291 | /* 17044 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 6292 | /* 17047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6293 | /* 17051 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6294 | /* 17055 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6295 | /* 17059 */ // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 6296 | /* 17059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv2i32), |
| 6297 | /* 17062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6298 | /* 17064 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6299 | /* 17066 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6300 | /* 17068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6301 | /* 17071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6302 | /* 17077 */ GIR_RootConstrainSelectedInstOperands, |
| 6303 | /* 17078 */ // GIR_Coverage, 957, |
| 6304 | /* 17078 */ GIR_EraseRootFromParent_Done, |
| 6305 | /* 17079 */ // Label 427: @17079 |
| 6306 | /* 17079 */ GIM_Reject, |
| 6307 | /* 17080 */ // Label 402: @17080 |
| 6308 | /* 17080 */ GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(17305), |
| 6309 | /* 17085 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 6310 | /* 17088 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6311 | /* 17091 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 429*/ GIMT_Encode4(17205), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4932 // |
| 6312 | /* 17098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6313 | /* 17102 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6314 | /* 17106 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6315 | /* 17110 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 6316 | /* 17114 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6317 | /* 17119 */ // MIs[1] Operand 2 |
| 6318 | /* 17119 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 6319 | /* 17130 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6320 | /* 17134 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6321 | /* 17138 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 6322 | /* 17142 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6323 | /* 17147 */ // MIs[2] Operand 2 |
| 6324 | /* 17147 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 6325 | /* 17158 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6326 | /* 17160 */ // (mul:{ *:[v4i32] } (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, v4i16:{ *:[Other] }), (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src2, v4i16:{ *:[Other] })) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2) |
| 6327 | /* 17160 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6328 | /* 17163 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6329 | /* 17167 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6330 | /* 17172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16), |
| 6331 | /* 17175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6332 | /* 17177 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 6333 | /* 17181 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 6334 | /* 17185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6335 | /* 17188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6336 | /* 17194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6337 | /* 17200 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6338 | /* 17203 */ GIR_RootConstrainSelectedInstOperands, |
| 6339 | /* 17204 */ // GIR_Coverage, 4932, |
| 6340 | /* 17204 */ GIR_EraseRootFromParent_Done, |
| 6341 | /* 17205 */ // Label 429: @17205 |
| 6342 | /* 17205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 430*/ GIMT_Encode4(17244), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 960 // |
| 6343 | /* 17212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6344 | /* 17216 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6345 | /* 17220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6346 | /* 17224 */ // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 6347 | /* 17224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i32), |
| 6348 | /* 17227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6349 | /* 17229 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6350 | /* 17231 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6351 | /* 17233 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6352 | /* 17236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6353 | /* 17242 */ GIR_RootConstrainSelectedInstOperands, |
| 6354 | /* 17243 */ // GIR_Coverage, 960, |
| 6355 | /* 17243 */ GIR_EraseRootFromParent_Done, |
| 6356 | /* 17244 */ // Label 430: @17244 |
| 6357 | /* 17244 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 431*/ GIMT_Encode4(17304), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3863 // |
| 6358 | /* 17251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6359 | /* 17255 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6360 | /* 17259 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6361 | /* 17263 */ // (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 6362 | /* 17263 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6363 | /* 17266 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6364 | /* 17270 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6365 | /* 17275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi32), |
| 6366 | /* 17278 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6367 | /* 17280 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 6368 | /* 17282 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 6369 | /* 17284 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6370 | /* 17287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6371 | /* 17293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6372 | /* 17299 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6373 | /* 17302 */ GIR_RootConstrainSelectedInstOperands, |
| 6374 | /* 17303 */ // GIR_Coverage, 3863, |
| 6375 | /* 17303 */ GIR_EraseRootFromParent_Done, |
| 6376 | /* 17304 */ // Label 431: @17304 |
| 6377 | /* 17304 */ GIM_Reject, |
| 6378 | /* 17305 */ // Label 428: @17305 |
| 6379 | /* 17305 */ GIM_Reject, |
| 6380 | /* 17306 */ // Label 403: @17306 |
| 6381 | /* 17306 */ GIM_Reject, |
| 6382 | /* 17307 */ // Label 3: @17307 |
| 6383 | /* 17307 */ GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(17400), |
| 6384 | /* 17312 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 6385 | /* 17315 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 6386 | /* 17318 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6387 | /* 17321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 433*/ GIMT_Encode4(17360), GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), // Rule ID 194 // |
| 6388 | /* 17328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6389 | /* 17332 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6390 | /* 17336 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6391 | /* 17340 */ // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6392 | /* 17340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SDIV), |
| 6393 | /* 17343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6394 | /* 17345 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6395 | /* 17347 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6396 | /* 17349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6397 | /* 17352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6398 | /* 17358 */ GIR_RootConstrainSelectedInstOperands, |
| 6399 | /* 17359 */ // GIR_Coverage, 194, |
| 6400 | /* 17359 */ GIR_EraseRootFromParent_Done, |
| 6401 | /* 17360 */ // Label 433: @17360 |
| 6402 | /* 17360 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 434*/ GIMT_Encode4(17399), GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), // Rule ID 531 // |
| 6403 | /* 17367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6404 | /* 17371 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6405 | /* 17375 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6406 | /* 17379 */ // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6407 | /* 17379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SDIV), |
| 6408 | /* 17382 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6409 | /* 17384 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6410 | /* 17386 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6411 | /* 17388 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6412 | /* 17391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6413 | /* 17397 */ GIR_RootConstrainSelectedInstOperands, |
| 6414 | /* 17398 */ // GIR_Coverage, 531, |
| 6415 | /* 17398 */ GIR_EraseRootFromParent_Done, |
| 6416 | /* 17399 */ // Label 434: @17399 |
| 6417 | /* 17399 */ GIM_Reject, |
| 6418 | /* 17400 */ // Label 432: @17400 |
| 6419 | /* 17400 */ GIM_Reject, |
| 6420 | /* 17401 */ // Label 4: @17401 |
| 6421 | /* 17401 */ GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(17494), |
| 6422 | /* 17406 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 6423 | /* 17409 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 6424 | /* 17412 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6425 | /* 17415 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 436*/ GIMT_Encode4(17454), GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), // Rule ID 195 // |
| 6426 | /* 17422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6427 | /* 17426 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6428 | /* 17430 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6429 | /* 17434 */ // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6430 | /* 17434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDIV), |
| 6431 | /* 17437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6432 | /* 17439 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6433 | /* 17441 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6434 | /* 17443 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6435 | /* 17446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6436 | /* 17452 */ GIR_RootConstrainSelectedInstOperands, |
| 6437 | /* 17453 */ // GIR_Coverage, 195, |
| 6438 | /* 17453 */ GIR_EraseRootFromParent_Done, |
| 6439 | /* 17454 */ // Label 436: @17454 |
| 6440 | /* 17454 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 437*/ GIMT_Encode4(17493), GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), // Rule ID 532 // |
| 6441 | /* 17461 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6442 | /* 17465 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6443 | /* 17469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6444 | /* 17473 */ // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6445 | /* 17473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDIV), |
| 6446 | /* 17476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6447 | /* 17478 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6448 | /* 17480 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6449 | /* 17482 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6450 | /* 17485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6451 | /* 17491 */ GIR_RootConstrainSelectedInstOperands, |
| 6452 | /* 17492 */ // GIR_Coverage, 532, |
| 6453 | /* 17492 */ GIR_EraseRootFromParent_Done, |
| 6454 | /* 17493 */ // Label 437: @17493 |
| 6455 | /* 17493 */ GIM_Reject, |
| 6456 | /* 17494 */ // Label 435: @17494 |
| 6457 | /* 17494 */ GIM_Reject, |
| 6458 | /* 17495 */ // Label 5: @17495 |
| 6459 | /* 17495 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 451*/ GIMT_Encode4(20594), |
| 6460 | /* 17506 */ /*GILLT_s32*//*Label 438*/ GIMT_Encode4(17558), |
| 6461 | /* 17510 */ /*GILLT_s64*//*Label 439*/ GIMT_Encode4(19494), |
| 6462 | /* 17514 */ /*GILLT_v2s1*//*Label 440*/ GIMT_Encode4(19540), |
| 6463 | /* 17518 */ /*GILLT_v4s1*//*Label 441*/ GIMT_Encode4(19657), |
| 6464 | /* 17522 */ /*GILLT_v8s1*//*Label 442*/ GIMT_Encode4(19774), |
| 6465 | /* 17526 */ /*GILLT_v16s1*//*Label 443*/ GIMT_Encode4(19891), |
| 6466 | /* 17530 */ /*GILLT_v8s8*//*Label 444*/ GIMT_Encode4(20008), |
| 6467 | /* 17534 */ /*GILLT_v16s8*//*Label 445*/ GIMT_Encode4(20054), |
| 6468 | /* 17538 */ /*GILLT_v4s16*//*Label 446*/ GIMT_Encode4(20166), |
| 6469 | /* 17542 */ /*GILLT_v8s16*//*Label 447*/ GIMT_Encode4(20212), |
| 6470 | /* 17546 */ /*GILLT_v2s32*//*Label 448*/ GIMT_Encode4(20324), |
| 6471 | /* 17550 */ /*GILLT_v4s32*//*Label 449*/ GIMT_Encode4(20370), |
| 6472 | /* 17554 */ /*GILLT_v2s64*//*Label 450*/ GIMT_Encode4(20482), |
| 6473 | /* 17558 */ // Label 438: @17558 |
| 6474 | /* 17558 */ GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(19493), |
| 6475 | /* 17563 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 6476 | /* 17566 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6477 | /* 17569 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 453*/ GIMT_Encode4(17641), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2043 // |
| 6478 | /* 17576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6479 | /* 17580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6480 | /* 17584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 6481 | /* 17588 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6482 | /* 17592 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6483 | /* 17596 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6484 | /* 17601 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8, |
| 6485 | /* 17605 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 6486 | /* 17616 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6487 | /* 17618 */ // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] }) |
| 6488 | /* 17618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), |
| 6489 | /* 17621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6490 | /* 17623 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src |
| 6491 | /* 17627 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 6492 | /* 17630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6493 | /* 17633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6494 | /* 17639 */ GIR_RootConstrainSelectedInstOperands, |
| 6495 | /* 17640 */ // GIR_Coverage, 2043, |
| 6496 | /* 17640 */ GIR_EraseRootFromParent_Done, |
| 6497 | /* 17641 */ // Label 453: @17641 |
| 6498 | /* 17641 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 454*/ GIMT_Encode4(17713), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2308 // |
| 6499 | /* 17648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6500 | /* 17652 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6501 | /* 17656 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 6502 | /* 17660 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6503 | /* 17664 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6504 | /* 17668 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6505 | /* 17673 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8, |
| 6506 | /* 17677 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 6507 | /* 17688 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6508 | /* 17690 */ // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] }) |
| 6509 | /* 17690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), |
| 6510 | /* 17693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6511 | /* 17695 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src |
| 6512 | /* 17699 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 6513 | /* 17702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6514 | /* 17705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6515 | /* 17711 */ GIR_RootConstrainSelectedInstOperands, |
| 6516 | /* 17712 */ // GIR_Coverage, 2308, |
| 6517 | /* 17712 */ GIR_EraseRootFromParent_Done, |
| 6518 | /* 17713 */ // Label 454: @17713 |
| 6519 | /* 17713 */ GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(17844), |
| 6520 | /* 17718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6521 | /* 17722 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6522 | /* 17726 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 456*/ GIMT_Encode4(17765), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2192 // |
| 6523 | /* 17733 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), |
| 6524 | /* 17744 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] }) => (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 6525 | /* 17744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB), |
| 6526 | /* 17747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6527 | /* 17749 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 6528 | /* 17751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6529 | /* 17754 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6530 | /* 17757 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6531 | /* 17763 */ GIR_RootConstrainSelectedInstOperands, |
| 6532 | /* 17764 */ // GIR_Coverage, 2192, |
| 6533 | /* 17764 */ GIR_EraseRootFromParent_Done, |
| 6534 | /* 17765 */ // Label 456: @17765 |
| 6535 | /* 17765 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 457*/ GIMT_Encode4(17804), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2193 // |
| 6536 | /* 17772 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 6537 | /* 17783 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] }) => (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 6538 | /* 17783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTH), |
| 6539 | /* 17786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6540 | /* 17788 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 6541 | /* 17790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6542 | /* 17793 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6543 | /* 17796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6544 | /* 17802 */ GIR_RootConstrainSelectedInstOperands, |
| 6545 | /* 17803 */ // GIR_Coverage, 2193, |
| 6546 | /* 17803 */ GIR_EraseRootFromParent_Done, |
| 6547 | /* 17804 */ // Label 457: @17804 |
| 6548 | /* 17804 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 458*/ GIMT_Encode4(17843), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2194 // |
| 6549 | /* 17811 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 6550 | /* 17822 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 6551 | /* 17822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), |
| 6552 | /* 17825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6553 | /* 17827 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 6554 | /* 17829 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6555 | /* 17832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6556 | /* 17835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6557 | /* 17841 */ GIR_RootConstrainSelectedInstOperands, |
| 6558 | /* 17842 */ // GIR_Coverage, 2194, |
| 6559 | /* 17842 */ GIR_EraseRootFromParent_Done, |
| 6560 | /* 17843 */ // Label 458: @17843 |
| 6561 | /* 17843 */ GIM_Reject, |
| 6562 | /* 17844 */ // Label 455: @17844 |
| 6563 | /* 17844 */ GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(17975), |
| 6564 | /* 17849 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6565 | /* 17853 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6566 | /* 17857 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 460*/ GIMT_Encode4(17896), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2436 // |
| 6567 | /* 17864 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), |
| 6568 | /* 17875 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 6569 | /* 17875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB), |
| 6570 | /* 17878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6571 | /* 17880 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 6572 | /* 17882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6573 | /* 17885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6574 | /* 17888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6575 | /* 17894 */ GIR_RootConstrainSelectedInstOperands, |
| 6576 | /* 17895 */ // GIR_Coverage, 2436, |
| 6577 | /* 17895 */ GIR_EraseRootFromParent_Done, |
| 6578 | /* 17896 */ // Label 460: @17896 |
| 6579 | /* 17896 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 461*/ GIMT_Encode4(17935), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2437 // |
| 6580 | /* 17903 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 6581 | /* 17914 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 6582 | /* 17914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTH), |
| 6583 | /* 17917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6584 | /* 17919 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 6585 | /* 17921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6586 | /* 17924 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6587 | /* 17927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6588 | /* 17933 */ GIR_RootConstrainSelectedInstOperands, |
| 6589 | /* 17934 */ // GIR_Coverage, 2437, |
| 6590 | /* 17934 */ GIR_EraseRootFromParent_Done, |
| 6591 | /* 17935 */ // Label 461: @17935 |
| 6592 | /* 17935 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 462*/ GIMT_Encode4(17974), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2438 // |
| 6593 | /* 17942 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 6594 | /* 17953 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 6595 | /* 17953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), |
| 6596 | /* 17956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6597 | /* 17958 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 6598 | /* 17960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6599 | /* 17963 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6600 | /* 17966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6601 | /* 17972 */ GIR_RootConstrainSelectedInstOperands, |
| 6602 | /* 17973 */ // GIR_Coverage, 2438, |
| 6603 | /* 17973 */ GIR_EraseRootFromParent_Done, |
| 6604 | /* 17974 */ // Label 462: @17974 |
| 6605 | /* 17974 */ GIM_Reject, |
| 6606 | /* 17975 */ // Label 459: @17975 |
| 6607 | /* 17975 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 463*/ GIMT_Encode4(18051), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5974 // |
| 6608 | /* 17982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6609 | /* 17986 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6610 | /* 17990 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6611 | /* 17994 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6612 | /* 17998 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6613 | /* 18002 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 6614 | /* 18006 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6615 | /* 18010 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6616 | /* 18014 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6617 | /* 18018 */ // MIs[2] Operand 1 |
| 6618 | /* 18018 */ // No operand predicates |
| 6619 | /* 18018 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6620 | /* 18022 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6621 | /* 18024 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6622 | /* 18024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6623 | /* 18027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6624 | /* 18029 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6625 | /* 18031 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6626 | /* 18034 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6627 | /* 18037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6628 | /* 18043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6629 | /* 18049 */ GIR_RootConstrainSelectedInstOperands, |
| 6630 | /* 18050 */ // GIR_Coverage, 5974, |
| 6631 | /* 18050 */ GIR_EraseRootFromParent_Done, |
| 6632 | /* 18051 */ // Label 463: @18051 |
| 6633 | /* 18051 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 464*/ GIMT_Encode4(18127), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6005 // |
| 6634 | /* 18058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6635 | /* 18062 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6636 | /* 18066 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6637 | /* 18070 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6638 | /* 18074 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6639 | /* 18078 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 6640 | /* 18082 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6641 | /* 18086 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6642 | /* 18090 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6643 | /* 18094 */ // MIs[2] Operand 1 |
| 6644 | /* 18094 */ // No operand predicates |
| 6645 | /* 18094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6646 | /* 18098 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6647 | /* 18100 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6648 | /* 18100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 6649 | /* 18103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6650 | /* 18105 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6651 | /* 18107 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6652 | /* 18110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6653 | /* 18113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6654 | /* 18119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6655 | /* 18125 */ GIR_RootConstrainSelectedInstOperands, |
| 6656 | /* 18126 */ // GIR_Coverage, 6005, |
| 6657 | /* 18126 */ GIR_EraseRootFromParent_Done, |
| 6658 | /* 18127 */ // Label 464: @18127 |
| 6659 | /* 18127 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 465*/ GIMT_Encode4(18203), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5973 // |
| 6660 | /* 18134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6661 | /* 18138 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6662 | /* 18142 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6663 | /* 18146 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6664 | /* 18150 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6665 | /* 18154 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6666 | /* 18158 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6667 | /* 18162 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6668 | /* 18166 */ // MIs[2] Operand 1 |
| 6669 | /* 18166 */ // No operand predicates |
| 6670 | /* 18166 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6671 | /* 18170 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6672 | /* 18174 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6673 | /* 18176 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6674 | /* 18176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6675 | /* 18179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6676 | /* 18181 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6677 | /* 18183 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6678 | /* 18186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6679 | /* 18189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6680 | /* 18195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6681 | /* 18201 */ GIR_RootConstrainSelectedInstOperands, |
| 6682 | /* 18202 */ // GIR_Coverage, 5973, |
| 6683 | /* 18202 */ GIR_EraseRootFromParent_Done, |
| 6684 | /* 18203 */ // Label 465: @18203 |
| 6685 | /* 18203 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 466*/ GIMT_Encode4(18279), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6004 // |
| 6686 | /* 18210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6687 | /* 18214 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6688 | /* 18218 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6689 | /* 18222 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6690 | /* 18226 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6691 | /* 18230 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6692 | /* 18234 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6693 | /* 18238 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6694 | /* 18242 */ // MIs[2] Operand 1 |
| 6695 | /* 18242 */ // No operand predicates |
| 6696 | /* 18242 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6697 | /* 18246 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6698 | /* 18250 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6699 | /* 18252 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6700 | /* 18252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 6701 | /* 18255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6702 | /* 18257 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6703 | /* 18259 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6704 | /* 18262 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6705 | /* 18265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6706 | /* 18271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6707 | /* 18277 */ GIR_RootConstrainSelectedInstOperands, |
| 6708 | /* 18278 */ // GIR_Coverage, 6004, |
| 6709 | /* 18278 */ GIR_EraseRootFromParent_Done, |
| 6710 | /* 18279 */ // Label 466: @18279 |
| 6711 | /* 18279 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 467*/ GIMT_Encode4(18355), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5972 // |
| 6712 | /* 18286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6713 | /* 18290 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6714 | /* 18294 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6715 | /* 18298 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6716 | /* 18302 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6717 | /* 18306 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6718 | /* 18310 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 6719 | /* 18314 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6720 | /* 18318 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6721 | /* 18322 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6722 | /* 18326 */ // MIs[2] Operand 1 |
| 6723 | /* 18326 */ // No operand predicates |
| 6724 | /* 18326 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6725 | /* 18328 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6726 | /* 18328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6727 | /* 18331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6728 | /* 18333 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6729 | /* 18335 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6730 | /* 18338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6731 | /* 18341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6732 | /* 18347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6733 | /* 18353 */ GIR_RootConstrainSelectedInstOperands, |
| 6734 | /* 18354 */ // GIR_Coverage, 5972, |
| 6735 | /* 18354 */ GIR_EraseRootFromParent_Done, |
| 6736 | /* 18355 */ // Label 467: @18355 |
| 6737 | /* 18355 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 468*/ GIMT_Encode4(18431), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6003 // |
| 6738 | /* 18362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6739 | /* 18366 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6740 | /* 18370 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6741 | /* 18374 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6742 | /* 18378 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6743 | /* 18382 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6744 | /* 18386 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 6745 | /* 18390 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6746 | /* 18394 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6747 | /* 18398 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6748 | /* 18402 */ // MIs[2] Operand 1 |
| 6749 | /* 18402 */ // No operand predicates |
| 6750 | /* 18402 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6751 | /* 18404 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6752 | /* 18404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 6753 | /* 18407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6754 | /* 18409 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6755 | /* 18411 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6756 | /* 18414 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6757 | /* 18417 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6758 | /* 18423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6759 | /* 18429 */ GIR_RootConstrainSelectedInstOperands, |
| 6760 | /* 18430 */ // GIR_Coverage, 6003, |
| 6761 | /* 18430 */ GIR_EraseRootFromParent_Done, |
| 6762 | /* 18431 */ // Label 468: @18431 |
| 6763 | /* 18431 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 469*/ GIMT_Encode4(18507), GIMT_Encode2(GIFBS_IsARM), // Rule ID 158 // |
| 6764 | /* 18438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6765 | /* 18442 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6766 | /* 18446 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6767 | /* 18450 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6768 | /* 18454 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6769 | /* 18458 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6770 | /* 18462 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6771 | /* 18466 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6772 | /* 18470 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6773 | /* 18474 */ // MIs[2] Operand 1 |
| 6774 | /* 18474 */ // No operand predicates |
| 6775 | /* 18474 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6776 | /* 18478 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6777 | /* 18480 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] })) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6778 | /* 18480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6779 | /* 18483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6780 | /* 18485 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6781 | /* 18487 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6782 | /* 18490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6783 | /* 18493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6784 | /* 18499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6785 | /* 18505 */ GIR_RootConstrainSelectedInstOperands, |
| 6786 | /* 18506 */ // GIR_Coverage, 158, |
| 6787 | /* 18506 */ GIR_EraseRootFromParent_Done, |
| 6788 | /* 18507 */ // Label 469: @18507 |
| 6789 | /* 18507 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 470*/ GIMT_Encode4(18583), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 489 // |
| 6790 | /* 18514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6791 | /* 18518 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6792 | /* 18522 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6793 | /* 18526 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6794 | /* 18530 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6795 | /* 18534 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6796 | /* 18538 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6797 | /* 18542 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6798 | /* 18546 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6799 | /* 18550 */ // MIs[2] Operand 1 |
| 6800 | /* 18550 */ // No operand predicates |
| 6801 | /* 18550 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6802 | /* 18554 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6803 | /* 18556 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6804 | /* 18556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 6805 | /* 18559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6806 | /* 18561 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6807 | /* 18563 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6808 | /* 18566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6809 | /* 18569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6810 | /* 18575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6811 | /* 18581 */ GIR_RootConstrainSelectedInstOperands, |
| 6812 | /* 18582 */ // GIR_Coverage, 489, |
| 6813 | /* 18582 */ GIR_EraseRootFromParent_Done, |
| 6814 | /* 18583 */ // Label 470: @18583 |
| 6815 | /* 18583 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 471*/ GIMT_Encode4(18653), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5975 // |
| 6816 | /* 18590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6817 | /* 18594 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6818 | /* 18598 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6819 | /* 18602 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6820 | /* 18606 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6821 | /* 18610 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6822 | /* 18615 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6823 | /* 18619 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6824 | /* 18623 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6825 | /* 18625 */ // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6826 | /* 18625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr), |
| 6827 | /* 18628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6828 | /* 18630 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6829 | /* 18632 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6830 | /* 18636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6831 | /* 18639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6832 | /* 18645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6833 | /* 18651 */ GIR_RootConstrainSelectedInstOperands, |
| 6834 | /* 18652 */ // GIR_Coverage, 5975, |
| 6835 | /* 18652 */ GIR_EraseRootFromParent_Done, |
| 6836 | /* 18653 */ // Label 471: @18653 |
| 6837 | /* 18653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 472*/ GIMT_Encode4(18723), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 5995 // |
| 6838 | /* 18660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6839 | /* 18664 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6840 | /* 18668 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6841 | /* 18672 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6842 | /* 18676 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6843 | /* 18680 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6844 | /* 18685 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6845 | /* 18689 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6846 | /* 18693 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6847 | /* 18695 */ // (and:{ *:[i32] } (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), tGPR:{ *:[i32] }:$Rn) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 6848 | /* 18695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC), |
| 6849 | /* 18698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 6850 | /* 18700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 6851 | /* 18706 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6852 | /* 18708 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6853 | /* 18712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6854 | /* 18715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6855 | /* 18721 */ GIR_RootConstrainSelectedInstOperands, |
| 6856 | /* 18722 */ // GIR_Coverage, 5995, |
| 6857 | /* 18722 */ GIR_EraseRootFromParent_Done, |
| 6858 | /* 18723 */ // Label 472: @18723 |
| 6859 | /* 18723 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 473*/ GIMT_Encode4(18793), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6006 // |
| 6860 | /* 18730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6861 | /* 18734 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6862 | /* 18738 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6863 | /* 18742 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6864 | /* 18746 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6865 | /* 18750 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6866 | /* 18755 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6867 | /* 18759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6868 | /* 18763 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6869 | /* 18765 */ // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6870 | /* 18765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr), |
| 6871 | /* 18768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6872 | /* 18770 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6873 | /* 18772 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6874 | /* 18776 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6875 | /* 18779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6876 | /* 18785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6877 | /* 18791 */ GIR_RootConstrainSelectedInstOperands, |
| 6878 | /* 18792 */ // GIR_Coverage, 6006, |
| 6879 | /* 18792 */ GIR_EraseRootFromParent_Done, |
| 6880 | /* 18793 */ // Label 473: @18793 |
| 6881 | /* 18793 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 474*/ GIMT_Encode4(18863), GIMT_Encode2(GIFBS_IsARM), // Rule ID 159 // |
| 6882 | /* 18800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6883 | /* 18804 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6884 | /* 18808 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6885 | /* 18812 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6886 | /* 18816 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6887 | /* 18820 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6888 | /* 18824 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6889 | /* 18829 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6890 | /* 18833 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6891 | /* 18835 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6892 | /* 18835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr), |
| 6893 | /* 18838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6894 | /* 18840 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6895 | /* 18842 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6896 | /* 18846 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6897 | /* 18849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6898 | /* 18855 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6899 | /* 18861 */ GIR_RootConstrainSelectedInstOperands, |
| 6900 | /* 18862 */ // GIR_Coverage, 159, |
| 6901 | /* 18862 */ GIR_EraseRootFromParent_Done, |
| 6902 | /* 18863 */ // Label 474: @18863 |
| 6903 | /* 18863 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 475*/ GIMT_Encode4(18933), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 312 // |
| 6904 | /* 18870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6905 | /* 18874 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6906 | /* 18878 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6907 | /* 18882 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6908 | /* 18886 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6909 | /* 18890 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6910 | /* 18894 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6911 | /* 18899 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6912 | /* 18903 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6913 | /* 18905 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 6914 | /* 18905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC), |
| 6915 | /* 18908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 6916 | /* 18910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 6917 | /* 18916 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6918 | /* 18918 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6919 | /* 18922 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6920 | /* 18925 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6921 | /* 18931 */ GIR_RootConstrainSelectedInstOperands, |
| 6922 | /* 18932 */ // GIR_Coverage, 312, |
| 6923 | /* 18932 */ GIR_EraseRootFromParent_Done, |
| 6924 | /* 18933 */ // Label 475: @18933 |
| 6925 | /* 18933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 476*/ GIMT_Encode4(19003), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 490 // |
| 6926 | /* 18940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6927 | /* 18944 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6928 | /* 18948 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6929 | /* 18952 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6930 | /* 18956 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6931 | /* 18960 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6932 | /* 18964 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6933 | /* 18969 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6934 | /* 18973 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6935 | /* 18975 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6936 | /* 18975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr), |
| 6937 | /* 18978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6938 | /* 18980 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6939 | /* 18982 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6940 | /* 18986 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6941 | /* 18989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6942 | /* 18995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6943 | /* 19001 */ GIR_RootConstrainSelectedInstOperands, |
| 6944 | /* 19002 */ // GIR_Coverage, 490, |
| 6945 | /* 19002 */ GIR_EraseRootFromParent_Done, |
| 6946 | /* 19003 */ // Label 476: @19003 |
| 6947 | /* 19003 */ GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(19089), |
| 6948 | /* 19008 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6949 | /* 19012 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6950 | /* 19016 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 478*/ GIMT_Encode4(19052), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 344 // |
| 6951 | /* 19023 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), |
| 6952 | /* 19034 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 6953 | /* 19034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTB), |
| 6954 | /* 19037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6955 | /* 19039 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 6956 | /* 19041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6957 | /* 19044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6958 | /* 19050 */ GIR_RootConstrainSelectedInstOperands, |
| 6959 | /* 19051 */ // GIR_Coverage, 344, |
| 6960 | /* 19051 */ GIR_EraseRootFromParent_Done, |
| 6961 | /* 19052 */ // Label 478: @19052 |
| 6962 | /* 19052 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 479*/ GIMT_Encode4(19088), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 345 // |
| 6963 | /* 19059 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 6964 | /* 19070 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 6965 | /* 19070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTH), |
| 6966 | /* 19073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6967 | /* 19075 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 6968 | /* 19077 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6969 | /* 19080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6970 | /* 19086 */ GIR_RootConstrainSelectedInstOperands, |
| 6971 | /* 19087 */ // GIR_Coverage, 345, |
| 6972 | /* 19087 */ GIR_EraseRootFromParent_Done, |
| 6973 | /* 19088 */ // Label 479: @19088 |
| 6974 | /* 19088 */ GIM_Reject, |
| 6975 | /* 19089 */ // Label 477: @19089 |
| 6976 | /* 19089 */ GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(19201), |
| 6977 | /* 19094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6978 | /* 19098 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6979 | /* 19102 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 481*/ GIMT_Encode4(19152), GIMT_Encode2(GIFBS_IsARM), // Rule ID 2082 // |
| 6980 | /* 19109 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6981 | /* 19113 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6982 | /* 19117 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not), |
| 6983 | /* 19121 */ // MIs[1] Operand 1 |
| 6984 | /* 19121 */ // No operand predicates |
| 6985 | /* 19121 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6986 | /* 19123 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>>:$imm)) |
| 6987 | /* 19123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6988 | /* 19126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6989 | /* 19128 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 6990 | /* 19130 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm |
| 6991 | /* 19135 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6992 | /* 19138 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6993 | /* 19144 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6994 | /* 19150 */ GIR_RootConstrainSelectedInstOperands, |
| 6995 | /* 19151 */ // GIR_Coverage, 2082, |
| 6996 | /* 19151 */ GIR_EraseRootFromParent_Done, |
| 6997 | /* 19152 */ // Label 481: @19152 |
| 6998 | /* 19152 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 482*/ GIMT_Encode4(19200), GIMT_Encode2(GIFBS_IsARM), // Rule ID 146 // |
| 6999 | /* 19159 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7000 | /* 19163 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7001 | /* 19167 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 7002 | /* 19171 */ // MIs[1] Operand 1 |
| 7003 | /* 19171 */ // No operand predicates |
| 7004 | /* 19171 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7005 | /* 19173 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 7006 | /* 19173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDri), |
| 7007 | /* 19176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7008 | /* 19178 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7009 | /* 19180 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 7010 | /* 19183 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7011 | /* 19186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7012 | /* 19192 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7013 | /* 19198 */ GIR_RootConstrainSelectedInstOperands, |
| 7014 | /* 19199 */ // GIR_Coverage, 146, |
| 7015 | /* 19199 */ GIR_EraseRootFromParent_Done, |
| 7016 | /* 19200 */ // Label 482: @19200 |
| 7017 | /* 19200 */ GIM_Reject, |
| 7018 | /* 19201 */ // Label 480: @19201 |
| 7019 | /* 19201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 483*/ GIMT_Encode4(19257), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 480 // |
| 7020 | /* 19208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7021 | /* 19212 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7022 | /* 19216 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7023 | /* 19220 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7024 | /* 19224 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 7025 | /* 19228 */ // MIs[1] Operand 1 |
| 7026 | /* 19228 */ // No operand predicates |
| 7027 | /* 19228 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7028 | /* 19230 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 7029 | /* 19230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDri), |
| 7030 | /* 19233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7031 | /* 19235 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7032 | /* 19237 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 7033 | /* 19240 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7034 | /* 19243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7035 | /* 19249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7036 | /* 19255 */ GIR_RootConstrainSelectedInstOperands, |
| 7037 | /* 19256 */ // GIR_Coverage, 480, |
| 7038 | /* 19256 */ GIR_EraseRootFromParent_Done, |
| 7039 | /* 19257 */ // Label 483: @19257 |
| 7040 | /* 19257 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 484*/ GIMT_Encode4(19307), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 162 // |
| 7041 | /* 19264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7042 | /* 19268 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7043 | /* 19272 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7044 | /* 19276 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7045 | /* 19280 */ // MIs[1] Operand 1 |
| 7046 | /* 19280 */ // No operand predicates |
| 7047 | /* 19280 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm), |
| 7048 | /* 19284 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7049 | /* 19286 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm) |
| 7050 | /* 19286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BFC), |
| 7051 | /* 19289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7052 | /* 19291 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 7053 | /* 19293 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 7054 | /* 19296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7055 | /* 19299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7056 | /* 19305 */ GIR_RootConstrainSelectedInstOperands, |
| 7057 | /* 19306 */ // GIR_Coverage, 162, |
| 7058 | /* 19306 */ GIR_EraseRootFromParent_Done, |
| 7059 | /* 19307 */ // Label 484: @19307 |
| 7060 | /* 19307 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 485*/ GIMT_Encode4(19357), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 492 // |
| 7061 | /* 19314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7062 | /* 19318 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7063 | /* 19322 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7064 | /* 19326 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7065 | /* 19330 */ // MIs[1] Operand 1 |
| 7066 | /* 19330 */ // No operand predicates |
| 7067 | /* 19330 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm), |
| 7068 | /* 19334 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7069 | /* 19336 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm) |
| 7070 | /* 19336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BFC), |
| 7071 | /* 19339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7072 | /* 19341 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 7073 | /* 19343 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 7074 | /* 19346 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7075 | /* 19349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7076 | /* 19355 */ GIR_RootConstrainSelectedInstOperands, |
| 7077 | /* 19356 */ // GIR_Coverage, 492, |
| 7078 | /* 19356 */ GIR_EraseRootFromParent_Done, |
| 7079 | /* 19357 */ // Label 485: @19357 |
| 7080 | /* 19357 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 486*/ GIMT_Encode4(19402), GIMT_Encode2(GIFBS_IsARM), // Rule ID 147 // |
| 7081 | /* 19364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7082 | /* 19368 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7083 | /* 19372 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7084 | /* 19376 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 7085 | /* 19376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDrr), |
| 7086 | /* 19379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7087 | /* 19381 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7088 | /* 19383 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 7089 | /* 19385 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7090 | /* 19388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7091 | /* 19394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7092 | /* 19400 */ GIR_RootConstrainSelectedInstOperands, |
| 7093 | /* 19401 */ // GIR_Coverage, 147, |
| 7094 | /* 19401 */ GIR_EraseRootFromParent_Done, |
| 7095 | /* 19402 */ // Label 486: @19402 |
| 7096 | /* 19402 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 487*/ GIMT_Encode4(19447), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 309 // |
| 7097 | /* 19409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7098 | /* 19413 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7099 | /* 19417 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7100 | /* 19421 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tAND:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 7101 | /* 19421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tAND), |
| 7102 | /* 19424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 7103 | /* 19426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 7104 | /* 19432 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7105 | /* 19434 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 7106 | /* 19436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7107 | /* 19439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7108 | /* 19445 */ GIR_RootConstrainSelectedInstOperands, |
| 7109 | /* 19446 */ // GIR_Coverage, 309, |
| 7110 | /* 19446 */ GIR_EraseRootFromParent_Done, |
| 7111 | /* 19447 */ // Label 487: @19447 |
| 7112 | /* 19447 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 488*/ GIMT_Encode4(19492), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 481 // |
| 7113 | /* 19454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7114 | /* 19458 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7115 | /* 19462 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7116 | /* 19466 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 7117 | /* 19466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 7118 | /* 19469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7119 | /* 19471 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7120 | /* 19473 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 7121 | /* 19475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7122 | /* 19478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7123 | /* 19484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7124 | /* 19490 */ GIR_RootConstrainSelectedInstOperands, |
| 7125 | /* 19491 */ // GIR_Coverage, 481, |
| 7126 | /* 19491 */ GIR_EraseRootFromParent_Done, |
| 7127 | /* 19492 */ // Label 488: @19492 |
| 7128 | /* 19492 */ GIM_Reject, |
| 7129 | /* 19493 */ // Label 452: @19493 |
| 7130 | /* 19493 */ GIM_Reject, |
| 7131 | /* 19494 */ // Label 439: @19494 |
| 7132 | /* 19494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 489*/ GIMT_Encode4(19539), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2915 // |
| 7133 | /* 19501 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 7134 | /* 19504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 7135 | /* 19507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7136 | /* 19511 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7137 | /* 19515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7138 | /* 19519 */ // (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VANDd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) |
| 7139 | /* 19519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 7140 | /* 19522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7141 | /* 19524 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7142 | /* 19526 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7143 | /* 19528 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7144 | /* 19531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7145 | /* 19537 */ GIR_RootConstrainSelectedInstOperands, |
| 7146 | /* 19538 */ // GIR_Coverage, 2915, |
| 7147 | /* 19538 */ GIR_EraseRootFromParent_Done, |
| 7148 | /* 19539 */ // Label 489: @19539 |
| 7149 | /* 19539 */ GIM_Reject, |
| 7150 | /* 19540 */ // Label 440: @19540 |
| 7151 | /* 19540 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 490*/ GIMT_Encode4(19656), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2014 // |
| 7152 | /* 19547 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, |
| 7153 | /* 19550 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, |
| 7154 | /* 19553 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7155 | /* 19557 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7156 | /* 19561 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7157 | /* 19565 */ // (and:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7158 | /* 19565 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7159 | /* 19568 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7160 | /* 19572 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7161 | /* 19577 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7162 | /* 19581 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7163 | /* 19586 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7164 | /* 19589 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7165 | /* 19593 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7166 | /* 19598 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7167 | /* 19602 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7168 | /* 19607 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7169 | /* 19610 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 7170 | /* 19614 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7171 | /* 19619 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7172 | /* 19622 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7173 | /* 19625 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7174 | /* 19628 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7175 | /* 19634 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7176 | /* 19640 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7177 | /* 19642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7178 | /* 19645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7179 | /* 19647 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7180 | /* 19650 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7181 | /* 19655 */ // GIR_Coverage, 2014, |
| 7182 | /* 19655 */ GIR_EraseRootFromParent_Done, |
| 7183 | /* 19656 */ // Label 490: @19656 |
| 7184 | /* 19656 */ GIM_Reject, |
| 7185 | /* 19657 */ // Label 441: @19657 |
| 7186 | /* 19657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 491*/ GIMT_Encode4(19773), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2015 // |
| 7187 | /* 19664 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, |
| 7188 | /* 19667 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, |
| 7189 | /* 19670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7190 | /* 19674 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7191 | /* 19678 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7192 | /* 19682 */ // (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7193 | /* 19682 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7194 | /* 19685 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7195 | /* 19689 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7196 | /* 19694 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7197 | /* 19698 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7198 | /* 19703 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7199 | /* 19706 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7200 | /* 19710 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7201 | /* 19715 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7202 | /* 19719 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7203 | /* 19724 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7204 | /* 19727 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 7205 | /* 19731 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7206 | /* 19736 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7207 | /* 19739 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7208 | /* 19742 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7209 | /* 19745 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7210 | /* 19751 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7211 | /* 19757 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7212 | /* 19759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7213 | /* 19762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7214 | /* 19764 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7215 | /* 19767 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7216 | /* 19772 */ // GIR_Coverage, 2015, |
| 7217 | /* 19772 */ GIR_EraseRootFromParent_Done, |
| 7218 | /* 19773 */ // Label 491: @19773 |
| 7219 | /* 19773 */ GIM_Reject, |
| 7220 | /* 19774 */ // Label 442: @19774 |
| 7221 | /* 19774 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 492*/ GIMT_Encode4(19890), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2016 // |
| 7222 | /* 19781 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, |
| 7223 | /* 19784 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, |
| 7224 | /* 19787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7225 | /* 19791 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7226 | /* 19795 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7227 | /* 19799 */ // (and:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7228 | /* 19799 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7229 | /* 19802 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7230 | /* 19806 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7231 | /* 19811 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7232 | /* 19815 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7233 | /* 19820 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7234 | /* 19823 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7235 | /* 19827 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7236 | /* 19832 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7237 | /* 19836 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7238 | /* 19841 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7239 | /* 19844 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 7240 | /* 19848 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7241 | /* 19853 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7242 | /* 19856 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7243 | /* 19859 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7244 | /* 19862 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7245 | /* 19868 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7246 | /* 19874 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7247 | /* 19876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7248 | /* 19879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7249 | /* 19881 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7250 | /* 19884 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7251 | /* 19889 */ // GIR_Coverage, 2016, |
| 7252 | /* 19889 */ GIR_EraseRootFromParent_Done, |
| 7253 | /* 19890 */ // Label 492: @19890 |
| 7254 | /* 19890 */ GIM_Reject, |
| 7255 | /* 19891 */ // Label 443: @19891 |
| 7256 | /* 19891 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 493*/ GIMT_Encode4(20007), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2017 // |
| 7257 | /* 19898 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, |
| 7258 | /* 19901 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, |
| 7259 | /* 19904 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7260 | /* 19908 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7261 | /* 19912 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7262 | /* 19916 */ // (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7263 | /* 19916 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7264 | /* 19919 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7265 | /* 19923 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7266 | /* 19928 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7267 | /* 19932 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7268 | /* 19937 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7269 | /* 19940 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7270 | /* 19944 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7271 | /* 19949 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7272 | /* 19953 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7273 | /* 19958 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7274 | /* 19961 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 7275 | /* 19965 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7276 | /* 19970 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7277 | /* 19973 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7278 | /* 19976 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7279 | /* 19979 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7280 | /* 19985 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7281 | /* 19991 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7282 | /* 19993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7283 | /* 19996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7284 | /* 19998 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7285 | /* 20001 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7286 | /* 20006 */ // GIR_Coverage, 2017, |
| 7287 | /* 20006 */ GIR_EraseRootFromParent_Done, |
| 7288 | /* 20007 */ // Label 493: @20007 |
| 7289 | /* 20007 */ GIM_Reject, |
| 7290 | /* 20008 */ // Label 444: @20008 |
| 7291 | /* 20008 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 494*/ GIMT_Encode4(20053), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2913 // |
| 7292 | /* 20015 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 7293 | /* 20018 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 7294 | /* 20021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7295 | /* 20025 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7296 | /* 20029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7297 | /* 20033 */ // (and:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VANDd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) |
| 7298 | /* 20033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 7299 | /* 20036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7300 | /* 20038 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7301 | /* 20040 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7302 | /* 20042 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7303 | /* 20045 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7304 | /* 20051 */ GIR_RootConstrainSelectedInstOperands, |
| 7305 | /* 20052 */ // GIR_Coverage, 2913, |
| 7306 | /* 20052 */ GIR_EraseRootFromParent_Done, |
| 7307 | /* 20053 */ // Label 494: @20053 |
| 7308 | /* 20053 */ GIM_Reject, |
| 7309 | /* 20054 */ // Label 445: @20054 |
| 7310 | /* 20054 */ GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(20165), |
| 7311 | /* 20059 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 7312 | /* 20062 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7313 | /* 20065 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 496*/ GIMT_Encode4(20104), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2916 // |
| 7314 | /* 20072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7315 | /* 20076 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7316 | /* 20080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7317 | /* 20084 */ // (and:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VANDq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) |
| 7318 | /* 20084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 7319 | /* 20087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7320 | /* 20089 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7321 | /* 20091 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7322 | /* 20093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7323 | /* 20096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7324 | /* 20102 */ GIR_RootConstrainSelectedInstOperands, |
| 7325 | /* 20103 */ // GIR_Coverage, 2916, |
| 7326 | /* 20103 */ GIR_EraseRootFromParent_Done, |
| 7327 | /* 20104 */ // Label 496: @20104 |
| 7328 | /* 20104 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 497*/ GIMT_Encode4(20164), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3755 // |
| 7329 | /* 20111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7330 | /* 20115 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7331 | /* 20119 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7332 | /* 20123 */ // (and:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VAND:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 7333 | /* 20123 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7334 | /* 20126 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7335 | /* 20130 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7336 | /* 20135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 7337 | /* 20138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7338 | /* 20140 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7339 | /* 20142 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7340 | /* 20144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7341 | /* 20147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7342 | /* 20153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7343 | /* 20159 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7344 | /* 20162 */ GIR_RootConstrainSelectedInstOperands, |
| 7345 | /* 20163 */ // GIR_Coverage, 3755, |
| 7346 | /* 20163 */ GIR_EraseRootFromParent_Done, |
| 7347 | /* 20164 */ // Label 497: @20164 |
| 7348 | /* 20164 */ GIM_Reject, |
| 7349 | /* 20165 */ // Label 495: @20165 |
| 7350 | /* 20165 */ GIM_Reject, |
| 7351 | /* 20166 */ // Label 446: @20166 |
| 7352 | /* 20166 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 498*/ GIMT_Encode4(20211), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2914 // |
| 7353 | /* 20173 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 7354 | /* 20176 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 7355 | /* 20179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7356 | /* 20183 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7357 | /* 20187 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7358 | /* 20191 */ // (and:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VANDd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) |
| 7359 | /* 20191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 7360 | /* 20194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7361 | /* 20196 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7362 | /* 20198 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7363 | /* 20200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7364 | /* 20203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7365 | /* 20209 */ GIR_RootConstrainSelectedInstOperands, |
| 7366 | /* 20210 */ // GIR_Coverage, 2914, |
| 7367 | /* 20210 */ GIR_EraseRootFromParent_Done, |
| 7368 | /* 20211 */ // Label 498: @20211 |
| 7369 | /* 20211 */ GIM_Reject, |
| 7370 | /* 20212 */ // Label 447: @20212 |
| 7371 | /* 20212 */ GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(20323), |
| 7372 | /* 20217 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 7373 | /* 20220 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7374 | /* 20223 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 500*/ GIMT_Encode4(20262), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2917 // |
| 7375 | /* 20230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7376 | /* 20234 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7377 | /* 20238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7378 | /* 20242 */ // (and:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VANDq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) |
| 7379 | /* 20242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 7380 | /* 20245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7381 | /* 20247 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7382 | /* 20249 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7383 | /* 20251 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7384 | /* 20254 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7385 | /* 20260 */ GIR_RootConstrainSelectedInstOperands, |
| 7386 | /* 20261 */ // GIR_Coverage, 2917, |
| 7387 | /* 20261 */ GIR_EraseRootFromParent_Done, |
| 7388 | /* 20262 */ // Label 500: @20262 |
| 7389 | /* 20262 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 501*/ GIMT_Encode4(20322), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3759 // |
| 7390 | /* 20269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7391 | /* 20273 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7392 | /* 20277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7393 | /* 20281 */ // (and:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VAND:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 7394 | /* 20281 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7395 | /* 20284 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7396 | /* 20288 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7397 | /* 20293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 7398 | /* 20296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7399 | /* 20298 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7400 | /* 20300 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7401 | /* 20302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7402 | /* 20305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7403 | /* 20311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7404 | /* 20317 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7405 | /* 20320 */ GIR_RootConstrainSelectedInstOperands, |
| 7406 | /* 20321 */ // GIR_Coverage, 3759, |
| 7407 | /* 20321 */ GIR_EraseRootFromParent_Done, |
| 7408 | /* 20322 */ // Label 501: @20322 |
| 7409 | /* 20322 */ GIM_Reject, |
| 7410 | /* 20323 */ // Label 499: @20323 |
| 7411 | /* 20323 */ GIM_Reject, |
| 7412 | /* 20324 */ // Label 448: @20324 |
| 7413 | /* 20324 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 502*/ GIMT_Encode4(20369), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1295 // |
| 7414 | /* 20331 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 7415 | /* 20334 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 7416 | /* 20337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7417 | /* 20341 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7418 | /* 20345 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7419 | /* 20349 */ // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 7420 | /* 20349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 7421 | /* 20352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7422 | /* 20354 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 7423 | /* 20356 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 7424 | /* 20358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7425 | /* 20361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7426 | /* 20367 */ GIR_RootConstrainSelectedInstOperands, |
| 7427 | /* 20368 */ // GIR_Coverage, 1295, |
| 7428 | /* 20368 */ GIR_EraseRootFromParent_Done, |
| 7429 | /* 20369 */ // Label 502: @20369 |
| 7430 | /* 20369 */ GIM_Reject, |
| 7431 | /* 20370 */ // Label 449: @20370 |
| 7432 | /* 20370 */ GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(20481), |
| 7433 | /* 20375 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 7434 | /* 20378 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7435 | /* 20381 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 504*/ GIMT_Encode4(20420), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1296 // |
| 7436 | /* 20388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7437 | /* 20392 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7438 | /* 20396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7439 | /* 20400 */ // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 7440 | /* 20400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 7441 | /* 20403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7442 | /* 20405 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 7443 | /* 20407 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 7444 | /* 20409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7445 | /* 20412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7446 | /* 20418 */ GIR_RootConstrainSelectedInstOperands, |
| 7447 | /* 20419 */ // GIR_Coverage, 1296, |
| 7448 | /* 20419 */ GIR_EraseRootFromParent_Done, |
| 7449 | /* 20420 */ // Label 504: @20420 |
| 7450 | /* 20420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 505*/ GIMT_Encode4(20480), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3763 // |
| 7451 | /* 20427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7452 | /* 20431 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7453 | /* 20435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7454 | /* 20439 */ // (and:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VAND:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 7455 | /* 20439 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7456 | /* 20442 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7457 | /* 20446 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7458 | /* 20451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 7459 | /* 20454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7460 | /* 20456 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7461 | /* 20458 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7462 | /* 20460 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7463 | /* 20463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7464 | /* 20469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7465 | /* 20475 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7466 | /* 20478 */ GIR_RootConstrainSelectedInstOperands, |
| 7467 | /* 20479 */ // GIR_Coverage, 3763, |
| 7468 | /* 20479 */ GIR_EraseRootFromParent_Done, |
| 7469 | /* 20480 */ // Label 505: @20480 |
| 7470 | /* 20480 */ GIM_Reject, |
| 7471 | /* 20481 */ // Label 503: @20481 |
| 7472 | /* 20481 */ GIM_Reject, |
| 7473 | /* 20482 */ // Label 450: @20482 |
| 7474 | /* 20482 */ GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(20593), |
| 7475 | /* 20487 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 7476 | /* 20490 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7477 | /* 20493 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 507*/ GIMT_Encode4(20532), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2918 // |
| 7478 | /* 20500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7479 | /* 20504 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7480 | /* 20508 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7481 | /* 20512 */ // (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VANDq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) |
| 7482 | /* 20512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 7483 | /* 20515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7484 | /* 20517 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7485 | /* 20519 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7486 | /* 20521 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7487 | /* 20524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7488 | /* 20530 */ GIR_RootConstrainSelectedInstOperands, |
| 7489 | /* 20531 */ // GIR_Coverage, 2918, |
| 7490 | /* 20531 */ GIR_EraseRootFromParent_Done, |
| 7491 | /* 20532 */ // Label 507: @20532 |
| 7492 | /* 20532 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 508*/ GIMT_Encode4(20592), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3767 // |
| 7493 | /* 20539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7494 | /* 20543 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7495 | /* 20547 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7496 | /* 20551 */ // (and:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VAND:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) |
| 7497 | /* 20551 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7498 | /* 20554 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7499 | /* 20558 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7500 | /* 20563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 7501 | /* 20566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7502 | /* 20568 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7503 | /* 20570 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7504 | /* 20572 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7505 | /* 20575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7506 | /* 20581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7507 | /* 20587 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7508 | /* 20590 */ GIR_RootConstrainSelectedInstOperands, |
| 7509 | /* 20591 */ // GIR_Coverage, 3767, |
| 7510 | /* 20591 */ GIR_EraseRootFromParent_Done, |
| 7511 | /* 20592 */ // Label 508: @20592 |
| 7512 | /* 20592 */ GIM_Reject, |
| 7513 | /* 20593 */ // Label 506: @20593 |
| 7514 | /* 20593 */ GIM_Reject, |
| 7515 | /* 20594 */ // Label 451: @20594 |
| 7516 | /* 20594 */ GIM_Reject, |
| 7517 | /* 20595 */ // Label 6: @20595 |
| 7518 | /* 20595 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 522*/ GIMT_Encode4(26320), |
| 7519 | /* 20606 */ /*GILLT_s32*//*Label 509*/ GIMT_Encode4(20658), |
| 7520 | /* 20610 */ /*GILLT_s64*//*Label 510*/ GIMT_Encode4(25220), |
| 7521 | /* 20614 */ /*GILLT_v2s1*//*Label 511*/ GIMT_Encode4(25266), |
| 7522 | /* 20618 */ /*GILLT_v4s1*//*Label 512*/ GIMT_Encode4(25383), |
| 7523 | /* 20622 */ /*GILLT_v8s1*//*Label 513*/ GIMT_Encode4(25500), |
| 7524 | /* 20626 */ /*GILLT_v16s1*//*Label 514*/ GIMT_Encode4(25617), |
| 7525 | /* 20630 */ /*GILLT_v8s8*//*Label 515*/ GIMT_Encode4(25734), |
| 7526 | /* 20634 */ /*GILLT_v16s8*//*Label 516*/ GIMT_Encode4(25780), |
| 7527 | /* 20638 */ /*GILLT_v4s16*//*Label 517*/ GIMT_Encode4(25892), |
| 7528 | /* 20642 */ /*GILLT_v8s16*//*Label 518*/ GIMT_Encode4(25938), |
| 7529 | /* 20646 */ /*GILLT_v2s32*//*Label 519*/ GIMT_Encode4(26050), |
| 7530 | /* 20650 */ /*GILLT_v4s32*//*Label 520*/ GIMT_Encode4(26096), |
| 7531 | /* 20654 */ /*GILLT_v2s64*//*Label 521*/ GIMT_Encode4(26208), |
| 7532 | /* 20658 */ // Label 509: @20658 |
| 7533 | /* 20658 */ GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(25219), |
| 7534 | /* 20663 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 7535 | /* 20666 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 7536 | /* 20669 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 524*/ GIMT_Encode4(20795), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6255 // |
| 7537 | /* 20676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7538 | /* 20680 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7539 | /* 20684 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7540 | /* 20688 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7541 | /* 20692 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7542 | /* 20696 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7543 | /* 20700 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7544 | /* 20704 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7545 | /* 20708 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7546 | /* 20712 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7547 | /* 20717 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8, |
| 7548 | /* 20721 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 7549 | /* 20732 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7550 | /* 20736 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7551 | /* 20740 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7552 | /* 20744 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7553 | /* 20748 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 7554 | /* 20752 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7555 | /* 20756 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7556 | /* 20760 */ // MIs[4] Rm |
| 7557 | /* 20760 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7558 | /* 20765 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 7559 | /* 20769 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 7560 | /* 20773 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7561 | /* 20775 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 7562 | /* 20775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), |
| 7563 | /* 20778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7564 | /* 20780 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7565 | /* 20784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7566 | /* 20787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7567 | /* 20793 */ GIR_RootConstrainSelectedInstOperands, |
| 7568 | /* 20794 */ // GIR_Coverage, 6255, |
| 7569 | /* 20794 */ GIR_EraseRootFromParent_Done, |
| 7570 | /* 20795 */ // Label 524: @20795 |
| 7571 | /* 20795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 525*/ GIMT_Encode4(20921), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6303 // |
| 7572 | /* 20802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7573 | /* 20806 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7574 | /* 20810 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7575 | /* 20814 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7576 | /* 20818 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7577 | /* 20822 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7578 | /* 20826 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7579 | /* 20830 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7580 | /* 20834 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7581 | /* 20838 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7582 | /* 20843 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8, |
| 7583 | /* 20847 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 7584 | /* 20858 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7585 | /* 20862 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7586 | /* 20866 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7587 | /* 20870 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7588 | /* 20874 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 7589 | /* 20878 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7590 | /* 20882 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7591 | /* 20886 */ // MIs[4] Rm |
| 7592 | /* 20886 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7593 | /* 20891 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 7594 | /* 20895 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 7595 | /* 20899 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7596 | /* 20901 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 7597 | /* 20901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), |
| 7598 | /* 20904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7599 | /* 20906 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7600 | /* 20910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7601 | /* 20913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7602 | /* 20919 */ GIR_RootConstrainSelectedInstOperands, |
| 7603 | /* 20920 */ // GIR_Coverage, 6303, |
| 7604 | /* 20920 */ GIR_EraseRootFromParent_Done, |
| 7605 | /* 20921 */ // Label 525: @20921 |
| 7606 | /* 20921 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 526*/ GIMT_Encode4(21047), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2102 // |
| 7607 | /* 20928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7608 | /* 20932 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7609 | /* 20936 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7610 | /* 20940 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7611 | /* 20944 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7612 | /* 20948 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7613 | /* 20952 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7614 | /* 20956 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7615 | /* 20960 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7616 | /* 20964 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7617 | /* 20969 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 7618 | /* 20973 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 7619 | /* 20977 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7620 | /* 20981 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7621 | /* 20985 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7622 | /* 20989 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7623 | /* 20993 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 7624 | /* 20997 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7625 | /* 21001 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7626 | /* 21005 */ // MIs[4] Rm |
| 7627 | /* 21005 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7628 | /* 21010 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 7629 | /* 21014 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255), |
| 7630 | /* 21025 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7631 | /* 21027 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 7632 | /* 21027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), |
| 7633 | /* 21030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7634 | /* 21032 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7635 | /* 21036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7636 | /* 21039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7637 | /* 21045 */ GIR_RootConstrainSelectedInstOperands, |
| 7638 | /* 21046 */ // GIR_Coverage, 2102, |
| 7639 | /* 21046 */ GIR_EraseRootFromParent_Done, |
| 7640 | /* 21047 */ // Label 526: @21047 |
| 7641 | /* 21047 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 527*/ GIMT_Encode4(21173), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2392 // |
| 7642 | /* 21054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7643 | /* 21058 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7644 | /* 21062 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7645 | /* 21066 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7646 | /* 21070 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7647 | /* 21074 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7648 | /* 21078 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7649 | /* 21082 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7650 | /* 21086 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7651 | /* 21090 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7652 | /* 21095 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 7653 | /* 21099 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 7654 | /* 21103 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7655 | /* 21107 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7656 | /* 21111 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7657 | /* 21115 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7658 | /* 21119 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 7659 | /* 21123 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7660 | /* 21127 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7661 | /* 21131 */ // MIs[4] Rm |
| 7662 | /* 21131 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7663 | /* 21136 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 7664 | /* 21140 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255), |
| 7665 | /* 21151 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7666 | /* 21153 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 7667 | /* 21153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), |
| 7668 | /* 21156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7669 | /* 21158 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7670 | /* 21162 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7671 | /* 21165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7672 | /* 21171 */ GIR_RootConstrainSelectedInstOperands, |
| 7673 | /* 21172 */ // GIR_Coverage, 2392, |
| 7674 | /* 21172 */ GIR_EraseRootFromParent_Done, |
| 7675 | /* 21173 */ // Label 527: @21173 |
| 7676 | /* 21173 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 528*/ GIMT_Encode4(21305), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 5988 // |
| 7677 | /* 21180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7678 | /* 21184 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7679 | /* 21188 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7680 | /* 21192 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7681 | /* 21196 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7682 | /* 21200 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7683 | /* 21204 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7684 | /* 21208 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7685 | /* 21212 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7686 | /* 21216 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7687 | /* 21221 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7688 | /* 21225 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7689 | /* 21229 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 7690 | /* 21233 */ // MIs[3] Operand 1 |
| 7691 | /* 21233 */ // No operand predicates |
| 7692 | /* 21233 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7693 | /* 21244 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7694 | /* 21248 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7695 | /* 21252 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7696 | /* 21256 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7697 | /* 21260 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7698 | /* 21265 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 7699 | /* 21276 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7700 | /* 21278 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7701 | /* 21278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7702 | /* 21281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7703 | /* 21283 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 7704 | /* 21287 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7705 | /* 21291 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7706 | /* 21294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7707 | /* 21297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7708 | /* 21303 */ GIR_RootConstrainSelectedInstOperands, |
| 7709 | /* 21304 */ // GIR_Coverage, 5988, |
| 7710 | /* 21304 */ GIR_EraseRootFromParent_Done, |
| 7711 | /* 21305 */ // Label 528: @21305 |
| 7712 | /* 21305 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 529*/ GIMT_Encode4(21437), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6023 // |
| 7713 | /* 21312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7714 | /* 21316 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7715 | /* 21320 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7716 | /* 21324 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7717 | /* 21328 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7718 | /* 21332 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7719 | /* 21336 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7720 | /* 21340 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7721 | /* 21344 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7722 | /* 21348 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7723 | /* 21353 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7724 | /* 21357 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7725 | /* 21361 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 7726 | /* 21365 */ // MIs[3] Operand 1 |
| 7727 | /* 21365 */ // No operand predicates |
| 7728 | /* 21365 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7729 | /* 21376 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7730 | /* 21380 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7731 | /* 21384 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7732 | /* 21388 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7733 | /* 21392 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7734 | /* 21397 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 7735 | /* 21408 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7736 | /* 21410 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7737 | /* 21410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 7738 | /* 21413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7739 | /* 21415 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 7740 | /* 21419 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7741 | /* 21423 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7742 | /* 21426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7743 | /* 21429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7744 | /* 21435 */ GIR_RootConstrainSelectedInstOperands, |
| 7745 | /* 21436 */ // GIR_Coverage, 6023, |
| 7746 | /* 21436 */ GIR_EraseRootFromParent_Done, |
| 7747 | /* 21437 */ // Label 529: @21437 |
| 7748 | /* 21437 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 530*/ GIMT_Encode4(21569), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6260 // |
| 7749 | /* 21444 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7750 | /* 21448 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7751 | /* 21452 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7752 | /* 21456 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7753 | /* 21460 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7754 | /* 21464 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7755 | /* 21468 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7756 | /* 21472 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7757 | /* 21476 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7758 | /* 21480 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7759 | /* 21485 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7760 | /* 21489 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7761 | /* 21493 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 7762 | /* 21497 */ // MIs[3] Operand 1 |
| 7763 | /* 21497 */ // No operand predicates |
| 7764 | /* 21497 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7765 | /* 21508 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7766 | /* 21512 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7767 | /* 21516 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7768 | /* 21520 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7769 | /* 21524 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7770 | /* 21529 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 7771 | /* 21540 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7772 | /* 21542 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 7773 | /* 21542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7774 | /* 21545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7775 | /* 21547 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1 |
| 7776 | /* 21551 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 7777 | /* 21555 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7778 | /* 21558 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7779 | /* 21561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7780 | /* 21567 */ GIR_RootConstrainSelectedInstOperands, |
| 7781 | /* 21568 */ // GIR_Coverage, 6260, |
| 7782 | /* 21568 */ GIR_EraseRootFromParent_Done, |
| 7783 | /* 21569 */ // Label 530: @21569 |
| 7784 | /* 21569 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 531*/ GIMT_Encode4(21701), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6308 // |
| 7785 | /* 21576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7786 | /* 21580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7787 | /* 21584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7788 | /* 21588 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7789 | /* 21592 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7790 | /* 21596 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7791 | /* 21600 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7792 | /* 21604 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7793 | /* 21608 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7794 | /* 21612 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7795 | /* 21617 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7796 | /* 21621 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7797 | /* 21625 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 7798 | /* 21629 */ // MIs[3] Operand 1 |
| 7799 | /* 21629 */ // No operand predicates |
| 7800 | /* 21629 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7801 | /* 21640 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7802 | /* 21644 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7803 | /* 21648 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7804 | /* 21652 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7805 | /* 21656 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7806 | /* 21661 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 7807 | /* 21672 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7808 | /* 21674 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 7809 | /* 21674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 7810 | /* 21677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7811 | /* 21679 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1 |
| 7812 | /* 21683 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 7813 | /* 21687 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7814 | /* 21690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7815 | /* 21693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7816 | /* 21699 */ GIR_RootConstrainSelectedInstOperands, |
| 7817 | /* 21700 */ // GIR_Coverage, 6308, |
| 7818 | /* 21700 */ GIR_EraseRootFromParent_Done, |
| 7819 | /* 21701 */ // Label 531: @21701 |
| 7820 | /* 21701 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 532*/ GIMT_Encode4(21833), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 5987 // |
| 7821 | /* 21708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7822 | /* 21712 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7823 | /* 21716 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7824 | /* 21720 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7825 | /* 21724 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7826 | /* 21728 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7827 | /* 21732 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7828 | /* 21736 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7829 | /* 21740 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7830 | /* 21744 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7831 | /* 21749 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7832 | /* 21753 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7833 | /* 21757 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 7834 | /* 21761 */ // MIs[3] Operand 1 |
| 7835 | /* 21761 */ // No operand predicates |
| 7836 | /* 21761 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7837 | /* 21772 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7838 | /* 21776 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7839 | /* 21780 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7840 | /* 21784 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7841 | /* 21788 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7842 | /* 21793 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535), |
| 7843 | /* 21804 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7844 | /* 21806 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7845 | /* 21806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 7846 | /* 21809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7847 | /* 21811 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 7848 | /* 21815 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7849 | /* 21819 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7850 | /* 21822 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7851 | /* 21825 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7852 | /* 21831 */ GIR_RootConstrainSelectedInstOperands, |
| 7853 | /* 21832 */ // GIR_Coverage, 5987, |
| 7854 | /* 21832 */ GIR_EraseRootFromParent_Done, |
| 7855 | /* 21833 */ // Label 532: @21833 |
| 7856 | /* 21833 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 533*/ GIMT_Encode4(21965), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6022 // |
| 7857 | /* 21840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7858 | /* 21844 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7859 | /* 21848 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7860 | /* 21852 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7861 | /* 21856 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7862 | /* 21860 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7863 | /* 21864 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7864 | /* 21868 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7865 | /* 21872 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7866 | /* 21876 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7867 | /* 21881 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7868 | /* 21885 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7869 | /* 21889 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 7870 | /* 21893 */ // MIs[3] Operand 1 |
| 7871 | /* 21893 */ // No operand predicates |
| 7872 | /* 21893 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7873 | /* 21904 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7874 | /* 21908 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7875 | /* 21912 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7876 | /* 21916 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7877 | /* 21920 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7878 | /* 21925 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535), |
| 7879 | /* 21936 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7880 | /* 21938 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7881 | /* 21938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 7882 | /* 21941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7883 | /* 21943 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 7884 | /* 21947 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7885 | /* 21951 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7886 | /* 21954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7887 | /* 21957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7888 | /* 21963 */ GIR_RootConstrainSelectedInstOperands, |
| 7889 | /* 21964 */ // GIR_Coverage, 6022, |
| 7890 | /* 21964 */ GIR_EraseRootFromParent_Done, |
| 7891 | /* 21965 */ // Label 533: @21965 |
| 7892 | /* 21965 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 534*/ GIMT_Encode4(22097), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 202 // |
| 7893 | /* 21972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7894 | /* 21976 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7895 | /* 21980 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7896 | /* 21984 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7897 | /* 21988 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7898 | /* 21992 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7899 | /* 21997 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7900 | /* 22008 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7901 | /* 22012 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7902 | /* 22016 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7903 | /* 22020 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7904 | /* 22024 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7905 | /* 22028 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7906 | /* 22032 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7907 | /* 22036 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7908 | /* 22040 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7909 | /* 22045 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 7910 | /* 22049 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7911 | /* 22053 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 7912 | /* 22057 */ // MIs[4] Operand 1 |
| 7913 | /* 22057 */ // No operand predicates |
| 7914 | /* 22057 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 7915 | /* 22068 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7916 | /* 22070 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7917 | /* 22070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7918 | /* 22073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7919 | /* 22075 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7920 | /* 22079 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 7921 | /* 22083 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 7922 | /* 22086 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7923 | /* 22089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7924 | /* 22095 */ GIR_RootConstrainSelectedInstOperands, |
| 7925 | /* 22096 */ // GIR_Coverage, 202, |
| 7926 | /* 22096 */ GIR_EraseRootFromParent_Done, |
| 7927 | /* 22097 */ // Label 534: @22097 |
| 7928 | /* 22097 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 535*/ GIMT_Encode4(22229), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 539 // |
| 7929 | /* 22104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7930 | /* 22108 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7931 | /* 22112 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7932 | /* 22116 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7933 | /* 22120 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7934 | /* 22124 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7935 | /* 22129 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7936 | /* 22140 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7937 | /* 22144 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7938 | /* 22148 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7939 | /* 22152 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7940 | /* 22156 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7941 | /* 22160 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7942 | /* 22164 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7943 | /* 22168 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7944 | /* 22172 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7945 | /* 22177 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 7946 | /* 22181 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7947 | /* 22185 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 7948 | /* 22189 */ // MIs[4] Operand 1 |
| 7949 | /* 22189 */ // No operand predicates |
| 7950 | /* 22189 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 7951 | /* 22200 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7952 | /* 22202 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7953 | /* 22202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 7954 | /* 22205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7955 | /* 22207 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7956 | /* 22211 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 7957 | /* 22215 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 7958 | /* 22218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7959 | /* 22221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7960 | /* 22227 */ GIR_RootConstrainSelectedInstOperands, |
| 7961 | /* 22228 */ // GIR_Coverage, 539, |
| 7962 | /* 22228 */ GIR_EraseRootFromParent_Done, |
| 7963 | /* 22229 */ // Label 535: @22229 |
| 7964 | /* 22229 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 536*/ GIMT_Encode4(22361), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2107 // |
| 7965 | /* 22236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7966 | /* 22240 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7967 | /* 22244 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7968 | /* 22248 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7969 | /* 22252 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7970 | /* 22256 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7971 | /* 22261 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7972 | /* 22272 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7973 | /* 22276 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7974 | /* 22280 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7975 | /* 22284 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7976 | /* 22288 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7977 | /* 22292 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7978 | /* 22296 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7979 | /* 22300 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7980 | /* 22304 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7981 | /* 22309 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 7982 | /* 22313 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7983 | /* 22317 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 7984 | /* 22321 */ // MIs[4] Operand 1 |
| 7985 | /* 22321 */ // No operand predicates |
| 7986 | /* 22321 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 7987 | /* 22332 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7988 | /* 22334 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 7989 | /* 22334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7990 | /* 22337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7991 | /* 22339 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 7992 | /* 22343 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2 |
| 7993 | /* 22347 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 7994 | /* 22350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7995 | /* 22353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7996 | /* 22359 */ GIR_RootConstrainSelectedInstOperands, |
| 7997 | /* 22360 */ // GIR_Coverage, 2107, |
| 7998 | /* 22360 */ GIR_EraseRootFromParent_Done, |
| 7999 | /* 22361 */ // Label 536: @22361 |
| 8000 | /* 22361 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 537*/ GIMT_Encode4(22493), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2397 // |
| 8001 | /* 22368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8002 | /* 22372 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8003 | /* 22376 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8004 | /* 22380 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8005 | /* 22384 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8006 | /* 22388 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8007 | /* 22393 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8008 | /* 22404 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8009 | /* 22408 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8010 | /* 22412 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8011 | /* 22416 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8012 | /* 22420 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 8013 | /* 22424 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8014 | /* 22428 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8015 | /* 22432 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8016 | /* 22436 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8017 | /* 22441 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 8018 | /* 22445 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8019 | /* 22449 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 8020 | /* 22453 */ // MIs[4] Operand 1 |
| 8021 | /* 22453 */ // No operand predicates |
| 8022 | /* 22453 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 8023 | /* 22464 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8024 | /* 22466 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 8025 | /* 22466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8026 | /* 22469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8027 | /* 22471 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8028 | /* 22475 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2 |
| 8029 | /* 22479 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 8030 | /* 22482 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8031 | /* 22485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8032 | /* 22491 */ GIR_RootConstrainSelectedInstOperands, |
| 8033 | /* 22492 */ // GIR_Coverage, 2397, |
| 8034 | /* 22492 */ GIR_EraseRootFromParent_Done, |
| 8035 | /* 22493 */ // Label 537: @22493 |
| 8036 | /* 22493 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 538*/ GIMT_Encode4(22625), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 201 // |
| 8037 | /* 22500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8038 | /* 22504 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8039 | /* 22508 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8040 | /* 22512 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8041 | /* 22516 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8042 | /* 22520 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8043 | /* 22525 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8044 | /* 22536 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8045 | /* 22540 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8046 | /* 22544 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8047 | /* 22548 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8048 | /* 22552 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 8049 | /* 22556 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8050 | /* 22560 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8051 | /* 22564 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8052 | /* 22568 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8053 | /* 22573 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 8054 | /* 22577 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8055 | /* 22581 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 8056 | /* 22585 */ // MIs[4] Operand 1 |
| 8057 | /* 22585 */ // No operand predicates |
| 8058 | /* 22585 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 8059 | /* 22596 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8060 | /* 22598 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 8061 | /* 22598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8062 | /* 22601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8063 | /* 22603 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 8064 | /* 22607 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 8065 | /* 22611 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 8066 | /* 22614 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8067 | /* 22617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8068 | /* 22623 */ GIR_RootConstrainSelectedInstOperands, |
| 8069 | /* 22624 */ // GIR_Coverage, 201, |
| 8070 | /* 22624 */ GIR_EraseRootFromParent_Done, |
| 8071 | /* 22625 */ // Label 538: @22625 |
| 8072 | /* 22625 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 539*/ GIMT_Encode4(22757), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 538 // |
| 8073 | /* 22632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8074 | /* 22636 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8075 | /* 22640 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8076 | /* 22644 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8077 | /* 22648 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8078 | /* 22652 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8079 | /* 22657 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8080 | /* 22668 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8081 | /* 22672 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8082 | /* 22676 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8083 | /* 22680 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8084 | /* 22684 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 8085 | /* 22688 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8086 | /* 22692 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8087 | /* 22696 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8088 | /* 22700 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8089 | /* 22705 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 8090 | /* 22709 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8091 | /* 22713 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 8092 | /* 22717 */ // MIs[4] Operand 1 |
| 8093 | /* 22717 */ // No operand predicates |
| 8094 | /* 22717 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 8095 | /* 22728 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8096 | /* 22730 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 8097 | /* 22730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8098 | /* 22733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8099 | /* 22735 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 8100 | /* 22739 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 8101 | /* 22743 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 8102 | /* 22746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8103 | /* 22749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8104 | /* 22755 */ GIR_RootConstrainSelectedInstOperands, |
| 8105 | /* 22756 */ // GIR_Coverage, 538, |
| 8106 | /* 22756 */ GIR_EraseRootFromParent_Done, |
| 8107 | /* 22757 */ // Label 539: @22757 |
| 8108 | /* 22757 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 540*/ GIMT_Encode4(22861), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2103 // |
| 8109 | /* 22764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8110 | /* 22768 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8111 | /* 22772 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8112 | /* 22776 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8113 | /* 22780 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8114 | /* 22784 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8115 | /* 22789 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8116 | /* 22800 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8117 | /* 22804 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8118 | /* 22808 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8119 | /* 22812 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8120 | /* 22816 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8121 | /* 22821 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 8122 | /* 22832 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8123 | /* 22834 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 8124 | /* 22834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8125 | /* 22837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8126 | /* 22839 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 8127 | /* 22843 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 8128 | /* 22847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8129 | /* 22850 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8130 | /* 22853 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8131 | /* 22859 */ GIR_RootConstrainSelectedInstOperands, |
| 8132 | /* 22860 */ // GIR_Coverage, 2103, |
| 8133 | /* 22860 */ GIR_EraseRootFromParent_Done, |
| 8134 | /* 22861 */ // Label 540: @22861 |
| 8135 | /* 22861 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 541*/ GIMT_Encode4(22965), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2393 // |
| 8136 | /* 22868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8137 | /* 22872 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8138 | /* 22876 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8139 | /* 22880 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8140 | /* 22884 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8141 | /* 22888 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8142 | /* 22893 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8143 | /* 22904 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8144 | /* 22908 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8145 | /* 22912 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8146 | /* 22916 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8147 | /* 22920 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8148 | /* 22925 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 8149 | /* 22936 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8150 | /* 22938 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] }) |
| 8151 | /* 22938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8152 | /* 22941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8153 | /* 22943 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8154 | /* 22947 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8155 | /* 22951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8156 | /* 22954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8157 | /* 22957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8158 | /* 22963 */ GIR_RootConstrainSelectedInstOperands, |
| 8159 | /* 22964 */ // GIR_Coverage, 2393, |
| 8160 | /* 22964 */ GIR_EraseRootFromParent_Done, |
| 8161 | /* 22965 */ // Label 541: @22965 |
| 8162 | /* 22965 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 542*/ GIMT_Encode4(23069), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6256 // |
| 8163 | /* 22972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8164 | /* 22976 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8165 | /* 22980 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8166 | /* 22984 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8167 | /* 22988 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8168 | /* 22992 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8169 | /* 22997 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8170 | /* 23008 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8171 | /* 23012 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8172 | /* 23016 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8173 | /* 23020 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8174 | /* 23024 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8175 | /* 23029 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 8176 | /* 23040 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8177 | /* 23042 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 8178 | /* 23042 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8179 | /* 23045 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8180 | /* 23047 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 8181 | /* 23051 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8182 | /* 23055 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8183 | /* 23058 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8184 | /* 23061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8185 | /* 23067 */ GIR_RootConstrainSelectedInstOperands, |
| 8186 | /* 23068 */ // GIR_Coverage, 6256, |
| 8187 | /* 23068 */ GIR_EraseRootFromParent_Done, |
| 8188 | /* 23069 */ // Label 542: @23069 |
| 8189 | /* 23069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 543*/ GIMT_Encode4(23173), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6304 // |
| 8190 | /* 23076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8191 | /* 23080 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8192 | /* 23084 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8193 | /* 23088 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8194 | /* 23092 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8195 | /* 23096 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8196 | /* 23101 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8197 | /* 23112 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8198 | /* 23116 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8199 | /* 23120 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8200 | /* 23124 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8201 | /* 23128 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8202 | /* 23133 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 8203 | /* 23144 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8204 | /* 23146 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] }) |
| 8205 | /* 23146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8206 | /* 23149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8207 | /* 23151 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 8208 | /* 23155 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8209 | /* 23159 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8210 | /* 23162 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8211 | /* 23165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8212 | /* 23171 */ GIR_RootConstrainSelectedInstOperands, |
| 8213 | /* 23172 */ // GIR_Coverage, 6304, |
| 8214 | /* 23172 */ GIR_EraseRootFromParent_Done, |
| 8215 | /* 23173 */ // Label 543: @23173 |
| 8216 | /* 23173 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 544*/ GIMT_Encode4(23278), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2106 // |
| 8217 | /* 23180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8218 | /* 23184 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8219 | /* 23188 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8220 | /* 23192 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8221 | /* 23196 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8222 | /* 23200 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8223 | /* 23205 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8224 | /* 23216 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8225 | /* 23220 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 8226 | /* 23224 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8227 | /* 23228 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8228 | /* 23232 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8229 | /* 23237 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8230 | /* 23241 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8231 | /* 23245 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8232 | /* 23249 */ // MIs[3] Operand 1 |
| 8233 | /* 23249 */ // No operand predicates |
| 8234 | /* 23249 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8235 | /* 23251 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8236 | /* 23251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 8237 | /* 23254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8238 | /* 23256 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8239 | /* 23260 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8240 | /* 23264 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8241 | /* 23267 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8242 | /* 23270 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8243 | /* 23276 */ GIR_RootConstrainSelectedInstOperands, |
| 8244 | /* 23277 */ // GIR_Coverage, 2106, |
| 8245 | /* 23277 */ GIR_EraseRootFromParent_Done, |
| 8246 | /* 23278 */ // Label 544: @23278 |
| 8247 | /* 23278 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 545*/ GIMT_Encode4(23383), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2396 // |
| 8248 | /* 23285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8249 | /* 23289 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8250 | /* 23293 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8251 | /* 23297 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8252 | /* 23301 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8253 | /* 23305 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8254 | /* 23310 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8255 | /* 23321 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8256 | /* 23325 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 8257 | /* 23329 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8258 | /* 23333 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8259 | /* 23337 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8260 | /* 23342 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8261 | /* 23346 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8262 | /* 23350 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8263 | /* 23354 */ // MIs[3] Operand 1 |
| 8264 | /* 23354 */ // No operand predicates |
| 8265 | /* 23354 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8266 | /* 23356 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8267 | /* 23356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8268 | /* 23359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8269 | /* 23361 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8270 | /* 23365 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8271 | /* 23369 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8272 | /* 23372 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8273 | /* 23375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8274 | /* 23381 */ GIR_RootConstrainSelectedInstOperands, |
| 8275 | /* 23382 */ // GIR_Coverage, 2396, |
| 8276 | /* 23382 */ GIR_EraseRootFromParent_Done, |
| 8277 | /* 23383 */ // Label 545: @23383 |
| 8278 | /* 23383 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 546*/ GIMT_Encode4(23488), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2105 // |
| 8279 | /* 23390 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8280 | /* 23394 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8281 | /* 23398 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8282 | /* 23402 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8283 | /* 23406 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8284 | /* 23410 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8285 | /* 23415 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8286 | /* 23426 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8287 | /* 23430 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8288 | /* 23434 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8289 | /* 23438 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8290 | /* 23442 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8291 | /* 23447 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8292 | /* 23451 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8293 | /* 23455 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 8294 | /* 23459 */ // MIs[3] Operand 1 |
| 8295 | /* 23459 */ // No operand predicates |
| 8296 | /* 23459 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8297 | /* 23461 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 8298 | /* 23461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 8299 | /* 23464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8300 | /* 23466 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8301 | /* 23470 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8302 | /* 23474 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8303 | /* 23477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8304 | /* 23480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8305 | /* 23486 */ GIR_RootConstrainSelectedInstOperands, |
| 8306 | /* 23487 */ // GIR_Coverage, 2105, |
| 8307 | /* 23487 */ GIR_EraseRootFromParent_Done, |
| 8308 | /* 23488 */ // Label 546: @23488 |
| 8309 | /* 23488 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 547*/ GIMT_Encode4(23593), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2395 // |
| 8310 | /* 23495 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8311 | /* 23499 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8312 | /* 23503 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8313 | /* 23507 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8314 | /* 23511 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8315 | /* 23515 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8316 | /* 23520 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8317 | /* 23531 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8318 | /* 23535 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8319 | /* 23539 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8320 | /* 23543 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8321 | /* 23547 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8322 | /* 23552 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8323 | /* 23556 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8324 | /* 23560 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 8325 | /* 23564 */ // MIs[3] Operand 1 |
| 8326 | /* 23564 */ // No operand predicates |
| 8327 | /* 23564 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8328 | /* 23566 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 8329 | /* 23566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8330 | /* 23569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8331 | /* 23571 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8332 | /* 23575 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8333 | /* 23579 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8334 | /* 23582 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8335 | /* 23585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8336 | /* 23591 */ GIR_RootConstrainSelectedInstOperands, |
| 8337 | /* 23592 */ // GIR_Coverage, 2395, |
| 8338 | /* 23592 */ GIR_EraseRootFromParent_Done, |
| 8339 | /* 23593 */ // Label 547: @23593 |
| 8340 | /* 23593 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 548*/ GIMT_Encode4(23698), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2104 // |
| 8341 | /* 23600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8342 | /* 23604 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8343 | /* 23608 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8344 | /* 23612 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8345 | /* 23616 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8346 | /* 23620 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8347 | /* 23625 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8348 | /* 23636 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8349 | /* 23640 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8350 | /* 23644 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8351 | /* 23648 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8352 | /* 23652 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8353 | /* 23657 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8354 | /* 23661 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8355 | /* 23665 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8356 | /* 23669 */ // MIs[3] Operand 1 |
| 8357 | /* 23669 */ // No operand predicates |
| 8358 | /* 23669 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8359 | /* 23671 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8360 | /* 23671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8361 | /* 23674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8362 | /* 23676 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 8363 | /* 23680 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 8364 | /* 23684 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8365 | /* 23687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8366 | /* 23690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8367 | /* 23696 */ GIR_RootConstrainSelectedInstOperands, |
| 8368 | /* 23697 */ // GIR_Coverage, 2104, |
| 8369 | /* 23697 */ GIR_EraseRootFromParent_Done, |
| 8370 | /* 23698 */ // Label 548: @23698 |
| 8371 | /* 23698 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 549*/ GIMT_Encode4(23803), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2394 // |
| 8372 | /* 23705 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8373 | /* 23709 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8374 | /* 23713 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8375 | /* 23717 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8376 | /* 23721 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8377 | /* 23725 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8378 | /* 23730 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8379 | /* 23741 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8380 | /* 23745 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8381 | /* 23749 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8382 | /* 23753 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8383 | /* 23757 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8384 | /* 23762 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8385 | /* 23766 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8386 | /* 23770 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8387 | /* 23774 */ // MIs[3] Operand 1 |
| 8388 | /* 23774 */ // No operand predicates |
| 8389 | /* 23774 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8390 | /* 23776 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8391 | /* 23776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8392 | /* 23779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8393 | /* 23781 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8394 | /* 23785 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8395 | /* 23789 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8396 | /* 23792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8397 | /* 23795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8398 | /* 23801 */ GIR_RootConstrainSelectedInstOperands, |
| 8399 | /* 23802 */ // GIR_Coverage, 2394, |
| 8400 | /* 23802 */ GIR_EraseRootFromParent_Done, |
| 8401 | /* 23803 */ // Label 549: @23803 |
| 8402 | /* 23803 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 550*/ GIMT_Encode4(23908), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6259 // |
| 8403 | /* 23810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8404 | /* 23814 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8405 | /* 23818 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 8406 | /* 23822 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8407 | /* 23826 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8408 | /* 23830 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8409 | /* 23835 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8410 | /* 23839 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8411 | /* 23843 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8412 | /* 23847 */ // MIs[2] Operand 1 |
| 8413 | /* 23847 */ // No operand predicates |
| 8414 | /* 23847 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8415 | /* 23851 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8416 | /* 23855 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8417 | /* 23859 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8418 | /* 23863 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8419 | /* 23868 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 8420 | /* 23879 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8421 | /* 23881 */ // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8422 | /* 23881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 8423 | /* 23884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8424 | /* 23886 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8425 | /* 23890 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8426 | /* 23894 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8427 | /* 23897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8428 | /* 23900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8429 | /* 23906 */ GIR_RootConstrainSelectedInstOperands, |
| 8430 | /* 23907 */ // GIR_Coverage, 6259, |
| 8431 | /* 23907 */ GIR_EraseRootFromParent_Done, |
| 8432 | /* 23908 */ // Label 550: @23908 |
| 8433 | /* 23908 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 551*/ GIMT_Encode4(24013), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6307 // |
| 8434 | /* 23915 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8435 | /* 23919 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8436 | /* 23923 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 8437 | /* 23927 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8438 | /* 23931 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8439 | /* 23935 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8440 | /* 23940 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8441 | /* 23944 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8442 | /* 23948 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8443 | /* 23952 */ // MIs[2] Operand 1 |
| 8444 | /* 23952 */ // No operand predicates |
| 8445 | /* 23952 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8446 | /* 23956 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8447 | /* 23960 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8448 | /* 23964 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8449 | /* 23968 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8450 | /* 23973 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 8451 | /* 23984 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8452 | /* 23986 */ // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8453 | /* 23986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8454 | /* 23989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8455 | /* 23991 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8456 | /* 23995 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8457 | /* 23999 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8458 | /* 24002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8459 | /* 24005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8460 | /* 24011 */ GIR_RootConstrainSelectedInstOperands, |
| 8461 | /* 24012 */ // GIR_Coverage, 6307, |
| 8462 | /* 24012 */ GIR_EraseRootFromParent_Done, |
| 8463 | /* 24013 */ // Label 551: @24013 |
| 8464 | /* 24013 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 552*/ GIMT_Encode4(24118), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6258 // |
| 8465 | /* 24020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8466 | /* 24024 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8467 | /* 24028 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8468 | /* 24032 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8469 | /* 24036 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8470 | /* 24040 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8471 | /* 24045 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8472 | /* 24049 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8473 | /* 24053 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 8474 | /* 24057 */ // MIs[2] Operand 1 |
| 8475 | /* 24057 */ // No operand predicates |
| 8476 | /* 24057 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8477 | /* 24061 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8478 | /* 24065 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8479 | /* 24069 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8480 | /* 24073 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8481 | /* 24078 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 8482 | /* 24089 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8483 | /* 24091 */ // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 8484 | /* 24091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 8485 | /* 24094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8486 | /* 24096 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8487 | /* 24100 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8488 | /* 24104 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8489 | /* 24107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8490 | /* 24110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8491 | /* 24116 */ GIR_RootConstrainSelectedInstOperands, |
| 8492 | /* 24117 */ // GIR_Coverage, 6258, |
| 8493 | /* 24117 */ GIR_EraseRootFromParent_Done, |
| 8494 | /* 24118 */ // Label 552: @24118 |
| 8495 | /* 24118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 553*/ GIMT_Encode4(24223), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6306 // |
| 8496 | /* 24125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8497 | /* 24129 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8498 | /* 24133 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8499 | /* 24137 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8500 | /* 24141 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8501 | /* 24145 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8502 | /* 24150 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8503 | /* 24154 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8504 | /* 24158 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 8505 | /* 24162 */ // MIs[2] Operand 1 |
| 8506 | /* 24162 */ // No operand predicates |
| 8507 | /* 24162 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8508 | /* 24166 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8509 | /* 24170 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8510 | /* 24174 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8511 | /* 24178 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8512 | /* 24183 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 8513 | /* 24194 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8514 | /* 24196 */ // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 8515 | /* 24196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8516 | /* 24199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8517 | /* 24201 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8518 | /* 24205 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8519 | /* 24209 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8520 | /* 24212 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8521 | /* 24215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8522 | /* 24221 */ GIR_RootConstrainSelectedInstOperands, |
| 8523 | /* 24222 */ // GIR_Coverage, 6306, |
| 8524 | /* 24222 */ GIR_EraseRootFromParent_Done, |
| 8525 | /* 24223 */ // Label 553: @24223 |
| 8526 | /* 24223 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 554*/ GIMT_Encode4(24328), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6257 // |
| 8527 | /* 24230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8528 | /* 24234 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8529 | /* 24238 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8530 | /* 24242 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8531 | /* 24246 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8532 | /* 24250 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8533 | /* 24255 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8534 | /* 24259 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8535 | /* 24263 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8536 | /* 24267 */ // MIs[2] Operand 1 |
| 8537 | /* 24267 */ // No operand predicates |
| 8538 | /* 24267 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8539 | /* 24271 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8540 | /* 24275 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8541 | /* 24279 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8542 | /* 24283 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8543 | /* 24288 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535), |
| 8544 | /* 24299 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8545 | /* 24301 */ // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8546 | /* 24301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8547 | /* 24304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8548 | /* 24306 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 8549 | /* 24310 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8550 | /* 24314 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8551 | /* 24317 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8552 | /* 24320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8553 | /* 24326 */ GIR_RootConstrainSelectedInstOperands, |
| 8554 | /* 24327 */ // GIR_Coverage, 6257, |
| 8555 | /* 24327 */ GIR_EraseRootFromParent_Done, |
| 8556 | /* 24328 */ // Label 554: @24328 |
| 8557 | /* 24328 */ GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(24863), |
| 8558 | /* 24333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8559 | /* 24337 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 556*/ GIMT_Encode4(24438), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6305 // |
| 8560 | /* 24344 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8561 | /* 24348 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8562 | /* 24352 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8563 | /* 24356 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8564 | /* 24360 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8565 | /* 24365 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8566 | /* 24369 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8567 | /* 24373 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8568 | /* 24377 */ // MIs[2] Operand 1 |
| 8569 | /* 24377 */ // No operand predicates |
| 8570 | /* 24377 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8571 | /* 24381 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8572 | /* 24385 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8573 | /* 24389 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8574 | /* 24393 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8575 | /* 24398 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535), |
| 8576 | /* 24409 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8577 | /* 24411 */ // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8578 | /* 24411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8579 | /* 24414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8580 | /* 24416 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8581 | /* 24420 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8582 | /* 24424 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8583 | /* 24427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8584 | /* 24430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8585 | /* 24436 */ GIR_RootConstrainSelectedInstOperands, |
| 8586 | /* 24437 */ // GIR_Coverage, 6305, |
| 8587 | /* 24437 */ GIR_EraseRootFromParent_Done, |
| 8588 | /* 24438 */ // Label 556: @24438 |
| 8589 | /* 24438 */ GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(24584), |
| 8590 | /* 24443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8591 | /* 24447 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 558*/ GIMT_Encode4(24515), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6010 // |
| 8592 | /* 24454 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8593 | /* 24458 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8594 | /* 24462 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8595 | /* 24466 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8596 | /* 24470 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 8597 | /* 24474 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8598 | /* 24478 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8599 | /* 24482 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8600 | /* 24486 */ // MIs[2] Operand 1 |
| 8601 | /* 24486 */ // No operand predicates |
| 8602 | /* 24486 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8603 | /* 24488 */ // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8604 | /* 24488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8605 | /* 24491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8606 | /* 24493 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 8607 | /* 24495 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 8608 | /* 24498 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8609 | /* 24501 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8610 | /* 24507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8611 | /* 24513 */ GIR_RootConstrainSelectedInstOperands, |
| 8612 | /* 24514 */ // GIR_Coverage, 6010, |
| 8613 | /* 24514 */ GIR_EraseRootFromParent_Done, |
| 8614 | /* 24515 */ // Label 558: @24515 |
| 8615 | /* 24515 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 559*/ GIMT_Encode4(24583), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6009 // |
| 8616 | /* 24522 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8617 | /* 24526 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8618 | /* 24530 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8619 | /* 24534 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8620 | /* 24538 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8621 | /* 24542 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8622 | /* 24546 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8623 | /* 24550 */ // MIs[2] Operand 1 |
| 8624 | /* 24550 */ // No operand predicates |
| 8625 | /* 24550 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 8626 | /* 24554 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8627 | /* 24556 */ // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8628 | /* 24556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8629 | /* 24559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8630 | /* 24561 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 8631 | /* 24563 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 8632 | /* 24566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8633 | /* 24569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8634 | /* 24575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8635 | /* 24581 */ GIR_RootConstrainSelectedInstOperands, |
| 8636 | /* 24582 */ // GIR_Coverage, 6009, |
| 8637 | /* 24582 */ GIR_EraseRootFromParent_Done, |
| 8638 | /* 24583 */ // Label 559: @24583 |
| 8639 | /* 24583 */ GIM_Reject, |
| 8640 | /* 24584 */ // Label 557: @24584 |
| 8641 | /* 24584 */ GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(24730), |
| 8642 | /* 24589 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8643 | /* 24593 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 561*/ GIMT_Encode4(24661), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6008 // |
| 8644 | /* 24600 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8645 | /* 24604 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8646 | /* 24608 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8647 | /* 24612 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8648 | /* 24616 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 8649 | /* 24620 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8650 | /* 24624 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8651 | /* 24628 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8652 | /* 24632 */ // MIs[2] Operand 1 |
| 8653 | /* 24632 */ // No operand predicates |
| 8654 | /* 24632 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8655 | /* 24634 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8656 | /* 24634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8657 | /* 24637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8658 | /* 24639 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8659 | /* 24641 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 8660 | /* 24644 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8661 | /* 24647 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8662 | /* 24653 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8663 | /* 24659 */ GIR_RootConstrainSelectedInstOperands, |
| 8664 | /* 24660 */ // GIR_Coverage, 6008, |
| 8665 | /* 24660 */ GIR_EraseRootFromParent_Done, |
| 8666 | /* 24661 */ // Label 561: @24661 |
| 8667 | /* 24661 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 562*/ GIMT_Encode4(24729), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 495 // |
| 8668 | /* 24668 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8669 | /* 24672 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8670 | /* 24676 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8671 | /* 24680 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8672 | /* 24684 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8673 | /* 24688 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8674 | /* 24692 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8675 | /* 24696 */ // MIs[2] Operand 1 |
| 8676 | /* 24696 */ // No operand predicates |
| 8677 | /* 24696 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 8678 | /* 24700 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8679 | /* 24702 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8680 | /* 24702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8681 | /* 24705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8682 | /* 24707 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8683 | /* 24709 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 8684 | /* 24712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8685 | /* 24715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8686 | /* 24721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8687 | /* 24727 */ GIR_RootConstrainSelectedInstOperands, |
| 8688 | /* 24728 */ // GIR_Coverage, 495, |
| 8689 | /* 24728 */ GIR_EraseRootFromParent_Done, |
| 8690 | /* 24729 */ // Label 562: @24729 |
| 8691 | /* 24729 */ GIM_Reject, |
| 8692 | /* 24730 */ // Label 560: @24730 |
| 8693 | /* 24730 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 563*/ GIMT_Encode4(24796), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6011 // |
| 8694 | /* 24737 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8695 | /* 24741 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8696 | /* 24745 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8697 | /* 24749 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8698 | /* 24753 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8699 | /* 24758 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 8700 | /* 24762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8701 | /* 24766 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8702 | /* 24768 */ // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 8703 | /* 24768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr), |
| 8704 | /* 24771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8705 | /* 24773 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 8706 | /* 24775 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8707 | /* 24779 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8708 | /* 24782 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8709 | /* 24788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8710 | /* 24794 */ GIR_RootConstrainSelectedInstOperands, |
| 8711 | /* 24795 */ // GIR_Coverage, 6011, |
| 8712 | /* 24795 */ GIR_EraseRootFromParent_Done, |
| 8713 | /* 24796 */ // Label 563: @24796 |
| 8714 | /* 24796 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 564*/ GIMT_Encode4(24862), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 496 // |
| 8715 | /* 24803 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8716 | /* 24807 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8717 | /* 24811 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8718 | /* 24815 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8719 | /* 24819 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8720 | /* 24823 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8721 | /* 24828 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 8722 | /* 24832 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8723 | /* 24834 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 8724 | /* 24834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr), |
| 8725 | /* 24837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8726 | /* 24839 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8727 | /* 24841 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8728 | /* 24845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8729 | /* 24848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8730 | /* 24854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8731 | /* 24860 */ GIR_RootConstrainSelectedInstOperands, |
| 8732 | /* 24861 */ // GIR_Coverage, 496, |
| 8733 | /* 24861 */ GIR_EraseRootFromParent_Done, |
| 8734 | /* 24862 */ // Label 564: @24862 |
| 8735 | /* 24862 */ GIM_Reject, |
| 8736 | /* 24863 */ // Label 555: @24863 |
| 8737 | /* 24863 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 565*/ GIMT_Encode4(24917), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 2036 // |
| 8738 | /* 24870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8739 | /* 24874 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8740 | /* 24878 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760), |
| 8741 | /* 24889 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] }) |
| 8742 | /* 24889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVTi16), |
| 8743 | /* 24892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8744 | /* 24894 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8745 | /* 24896 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535), |
| 8746 | /* 24906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8747 | /* 24909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8748 | /* 24915 */ GIR_RootConstrainSelectedInstOperands, |
| 8749 | /* 24916 */ // GIR_Coverage, 2036, |
| 8750 | /* 24916 */ GIR_EraseRootFromParent_Done, |
| 8751 | /* 24917 */ // Label 565: @24917 |
| 8752 | /* 24917 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 566*/ GIMT_Encode4(24971), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2290 // |
| 8753 | /* 24924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8754 | /* 24928 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8755 | /* 24932 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760), |
| 8756 | /* 24943 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] }) |
| 8757 | /* 24943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVTi16), |
| 8758 | /* 24946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8759 | /* 24948 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8760 | /* 24950 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535), |
| 8761 | /* 24960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8762 | /* 24963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8763 | /* 24969 */ GIR_RootConstrainSelectedInstOperands, |
| 8764 | /* 24970 */ // GIR_Coverage, 2290, |
| 8765 | /* 24970 */ GIR_EraseRootFromParent_Done, |
| 8766 | /* 24971 */ // Label 566: @24971 |
| 8767 | /* 24971 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 567*/ GIMT_Encode4(25027), GIMT_Encode2(GIFBS_IsARM), // Rule ID 150 // |
| 8768 | /* 24978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8769 | /* 24982 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8770 | /* 24986 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8771 | /* 24990 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8772 | /* 24994 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 8773 | /* 24998 */ // MIs[1] Operand 1 |
| 8774 | /* 24998 */ // No operand predicates |
| 8775 | /* 24998 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8776 | /* 25000 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8777 | /* 25000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRri), |
| 8778 | /* 25003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8779 | /* 25005 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8780 | /* 25007 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 8781 | /* 25010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8782 | /* 25013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8783 | /* 25019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8784 | /* 25025 */ GIR_RootConstrainSelectedInstOperands, |
| 8785 | /* 25026 */ // GIR_Coverage, 150, |
| 8786 | /* 25026 */ GIR_EraseRootFromParent_Done, |
| 8787 | /* 25027 */ // Label 567: @25027 |
| 8788 | /* 25027 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 568*/ GIMT_Encode4(25083), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 483 // |
| 8789 | /* 25034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8790 | /* 25038 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8791 | /* 25042 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8792 | /* 25046 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8793 | /* 25050 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8794 | /* 25054 */ // MIs[1] Operand 1 |
| 8795 | /* 25054 */ // No operand predicates |
| 8796 | /* 25054 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8797 | /* 25056 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8798 | /* 25056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRri), |
| 8799 | /* 25059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8800 | /* 25061 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8801 | /* 25063 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 8802 | /* 25066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8803 | /* 25069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8804 | /* 25075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8805 | /* 25081 */ GIR_RootConstrainSelectedInstOperands, |
| 8806 | /* 25082 */ // GIR_Coverage, 483, |
| 8807 | /* 25082 */ GIR_EraseRootFromParent_Done, |
| 8808 | /* 25083 */ // Label 568: @25083 |
| 8809 | /* 25083 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 569*/ GIMT_Encode4(25128), GIMT_Encode2(GIFBS_IsARM), // Rule ID 151 // |
| 8810 | /* 25090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8811 | /* 25094 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8812 | /* 25098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8813 | /* 25102 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 8814 | /* 25102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRrr), |
| 8815 | /* 25105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8816 | /* 25107 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8817 | /* 25109 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 8818 | /* 25111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8819 | /* 25114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8820 | /* 25120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8821 | /* 25126 */ GIR_RootConstrainSelectedInstOperands, |
| 8822 | /* 25127 */ // GIR_Coverage, 151, |
| 8823 | /* 25127 */ GIR_EraseRootFromParent_Done, |
| 8824 | /* 25128 */ // Label 569: @25128 |
| 8825 | /* 25128 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 570*/ GIMT_Encode4(25173), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 324 // |
| 8826 | /* 25135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 8827 | /* 25139 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 8828 | /* 25143 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 8829 | /* 25147 */ // (or:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tORR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 8830 | /* 25147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tORR), |
| 8831 | /* 25150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 8832 | /* 25152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 8833 | /* 25158 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8834 | /* 25160 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 8835 | /* 25162 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8836 | /* 25165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8837 | /* 25171 */ GIR_RootConstrainSelectedInstOperands, |
| 8838 | /* 25172 */ // GIR_Coverage, 324, |
| 8839 | /* 25172 */ GIR_EraseRootFromParent_Done, |
| 8840 | /* 25173 */ // Label 570: @25173 |
| 8841 | /* 25173 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 571*/ GIMT_Encode4(25218), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 484 // |
| 8842 | /* 25180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8843 | /* 25184 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8844 | /* 25188 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8845 | /* 25192 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 8846 | /* 25192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 8847 | /* 25195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8848 | /* 25197 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8849 | /* 25199 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 8850 | /* 25201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8851 | /* 25204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8852 | /* 25210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8853 | /* 25216 */ GIR_RootConstrainSelectedInstOperands, |
| 8854 | /* 25217 */ // GIR_Coverage, 484, |
| 8855 | /* 25217 */ GIR_EraseRootFromParent_Done, |
| 8856 | /* 25218 */ // Label 571: @25218 |
| 8857 | /* 25218 */ GIM_Reject, |
| 8858 | /* 25219 */ // Label 523: @25219 |
| 8859 | /* 25219 */ GIM_Reject, |
| 8860 | /* 25220 */ // Label 510: @25220 |
| 8861 | /* 25220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 572*/ GIMT_Encode4(25265), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2921 // |
| 8862 | /* 25227 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 8863 | /* 25230 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 8864 | /* 25233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8865 | /* 25237 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8866 | /* 25241 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8867 | /* 25245 */ // (or:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VORRd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) |
| 8868 | /* 25245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 8869 | /* 25248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8870 | /* 25250 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 8871 | /* 25252 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 8872 | /* 25254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8873 | /* 25257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8874 | /* 25263 */ GIR_RootConstrainSelectedInstOperands, |
| 8875 | /* 25264 */ // GIR_Coverage, 2921, |
| 8876 | /* 25264 */ GIR_EraseRootFromParent_Done, |
| 8877 | /* 25265 */ // Label 572: @25265 |
| 8878 | /* 25265 */ GIM_Reject, |
| 8879 | /* 25266 */ // Label 511: @25266 |
| 8880 | /* 25266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 573*/ GIMT_Encode4(25382), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2022 // |
| 8881 | /* 25273 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, |
| 8882 | /* 25276 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, |
| 8883 | /* 25279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8884 | /* 25283 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8885 | /* 25287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8886 | /* 25291 */ // (or:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 8887 | /* 25291 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8888 | /* 25294 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8889 | /* 25298 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8890 | /* 25303 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 8891 | /* 25307 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8892 | /* 25312 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 8893 | /* 25315 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8894 | /* 25319 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8895 | /* 25324 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 8896 | /* 25328 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8897 | /* 25333 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8898 | /* 25336 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 8899 | /* 25340 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8900 | /* 25345 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8901 | /* 25348 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 8902 | /* 25351 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 8903 | /* 25354 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8904 | /* 25360 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8905 | /* 25366 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8906 | /* 25368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8907 | /* 25371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8908 | /* 25373 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8909 | /* 25376 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 8910 | /* 25381 */ // GIR_Coverage, 2022, |
| 8911 | /* 25381 */ GIR_EraseRootFromParent_Done, |
| 8912 | /* 25382 */ // Label 573: @25382 |
| 8913 | /* 25382 */ GIM_Reject, |
| 8914 | /* 25383 */ // Label 512: @25383 |
| 8915 | /* 25383 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 574*/ GIMT_Encode4(25499), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2023 // |
| 8916 | /* 25390 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, |
| 8917 | /* 25393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, |
| 8918 | /* 25396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8919 | /* 25400 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8920 | /* 25404 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8921 | /* 25408 */ // (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 8922 | /* 25408 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8923 | /* 25411 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8924 | /* 25415 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8925 | /* 25420 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 8926 | /* 25424 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8927 | /* 25429 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 8928 | /* 25432 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8929 | /* 25436 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8930 | /* 25441 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 8931 | /* 25445 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8932 | /* 25450 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8933 | /* 25453 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 8934 | /* 25457 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8935 | /* 25462 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8936 | /* 25465 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 8937 | /* 25468 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 8938 | /* 25471 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8939 | /* 25477 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8940 | /* 25483 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8941 | /* 25485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8942 | /* 25488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8943 | /* 25490 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8944 | /* 25493 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 8945 | /* 25498 */ // GIR_Coverage, 2023, |
| 8946 | /* 25498 */ GIR_EraseRootFromParent_Done, |
| 8947 | /* 25499 */ // Label 574: @25499 |
| 8948 | /* 25499 */ GIM_Reject, |
| 8949 | /* 25500 */ // Label 513: @25500 |
| 8950 | /* 25500 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 575*/ GIMT_Encode4(25616), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2024 // |
| 8951 | /* 25507 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, |
| 8952 | /* 25510 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, |
| 8953 | /* 25513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8954 | /* 25517 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8955 | /* 25521 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8956 | /* 25525 */ // (or:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 8957 | /* 25525 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8958 | /* 25528 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8959 | /* 25532 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8960 | /* 25537 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 8961 | /* 25541 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8962 | /* 25546 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 8963 | /* 25549 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8964 | /* 25553 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8965 | /* 25558 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 8966 | /* 25562 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8967 | /* 25567 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8968 | /* 25570 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 8969 | /* 25574 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8970 | /* 25579 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8971 | /* 25582 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 8972 | /* 25585 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 8973 | /* 25588 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8974 | /* 25594 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8975 | /* 25600 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8976 | /* 25602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8977 | /* 25605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8978 | /* 25607 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8979 | /* 25610 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 8980 | /* 25615 */ // GIR_Coverage, 2024, |
| 8981 | /* 25615 */ GIR_EraseRootFromParent_Done, |
| 8982 | /* 25616 */ // Label 575: @25616 |
| 8983 | /* 25616 */ GIM_Reject, |
| 8984 | /* 25617 */ // Label 514: @25617 |
| 8985 | /* 25617 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 576*/ GIMT_Encode4(25733), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2025 // |
| 8986 | /* 25624 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, |
| 8987 | /* 25627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, |
| 8988 | /* 25630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8989 | /* 25634 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8990 | /* 25638 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8991 | /* 25642 */ // (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 8992 | /* 25642 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8993 | /* 25645 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8994 | /* 25649 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8995 | /* 25654 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 8996 | /* 25658 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8997 | /* 25663 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 8998 | /* 25666 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8999 | /* 25670 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9000 | /* 25675 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9001 | /* 25679 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9002 | /* 25684 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9003 | /* 25687 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 9004 | /* 25691 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9005 | /* 25696 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9006 | /* 25699 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9007 | /* 25702 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9008 | /* 25705 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9009 | /* 25711 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9010 | /* 25717 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9011 | /* 25719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9012 | /* 25722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9013 | /* 25724 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9014 | /* 25727 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9015 | /* 25732 */ // GIR_Coverage, 2025, |
| 9016 | /* 25732 */ GIR_EraseRootFromParent_Done, |
| 9017 | /* 25733 */ // Label 576: @25733 |
| 9018 | /* 25733 */ GIM_Reject, |
| 9019 | /* 25734 */ // Label 515: @25734 |
| 9020 | /* 25734 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 577*/ GIMT_Encode4(25779), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2919 // |
| 9021 | /* 25741 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9022 | /* 25744 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 9023 | /* 25747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9024 | /* 25751 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9025 | /* 25755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9026 | /* 25759 */ // (or:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VORRd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) |
| 9027 | /* 25759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 9028 | /* 25762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9029 | /* 25764 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9030 | /* 25766 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9031 | /* 25768 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9032 | /* 25771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9033 | /* 25777 */ GIR_RootConstrainSelectedInstOperands, |
| 9034 | /* 25778 */ // GIR_Coverage, 2919, |
| 9035 | /* 25778 */ GIR_EraseRootFromParent_Done, |
| 9036 | /* 25779 */ // Label 577: @25779 |
| 9037 | /* 25779 */ GIM_Reject, |
| 9038 | /* 25780 */ // Label 516: @25780 |
| 9039 | /* 25780 */ GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(25891), |
| 9040 | /* 25785 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9041 | /* 25788 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9042 | /* 25791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 579*/ GIMT_Encode4(25830), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2922 // |
| 9043 | /* 25798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9044 | /* 25802 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9045 | /* 25806 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9046 | /* 25810 */ // (or:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VORRq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) |
| 9047 | /* 25810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 9048 | /* 25813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9049 | /* 25815 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9050 | /* 25817 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9051 | /* 25819 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9052 | /* 25822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9053 | /* 25828 */ GIR_RootConstrainSelectedInstOperands, |
| 9054 | /* 25829 */ // GIR_Coverage, 2922, |
| 9055 | /* 25829 */ GIR_EraseRootFromParent_Done, |
| 9056 | /* 25830 */ // Label 579: @25830 |
| 9057 | /* 25830 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 580*/ GIMT_Encode4(25890), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3769 // |
| 9058 | /* 25837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9059 | /* 25841 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9060 | /* 25845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9061 | /* 25849 */ // (or:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VORR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 9062 | /* 25849 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9063 | /* 25852 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9064 | /* 25856 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9065 | /* 25861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 9066 | /* 25864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9067 | /* 25866 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9068 | /* 25868 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9069 | /* 25870 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9070 | /* 25873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9071 | /* 25879 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9072 | /* 25885 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9073 | /* 25888 */ GIR_RootConstrainSelectedInstOperands, |
| 9074 | /* 25889 */ // GIR_Coverage, 3769, |
| 9075 | /* 25889 */ GIR_EraseRootFromParent_Done, |
| 9076 | /* 25890 */ // Label 580: @25890 |
| 9077 | /* 25890 */ GIM_Reject, |
| 9078 | /* 25891 */ // Label 578: @25891 |
| 9079 | /* 25891 */ GIM_Reject, |
| 9080 | /* 25892 */ // Label 517: @25892 |
| 9081 | /* 25892 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 581*/ GIMT_Encode4(25937), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2920 // |
| 9082 | /* 25899 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9083 | /* 25902 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 9084 | /* 25905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9085 | /* 25909 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9086 | /* 25913 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9087 | /* 25917 */ // (or:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VORRd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) |
| 9088 | /* 25917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 9089 | /* 25920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9090 | /* 25922 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9091 | /* 25924 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9092 | /* 25926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9093 | /* 25929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9094 | /* 25935 */ GIR_RootConstrainSelectedInstOperands, |
| 9095 | /* 25936 */ // GIR_Coverage, 2920, |
| 9096 | /* 25936 */ GIR_EraseRootFromParent_Done, |
| 9097 | /* 25937 */ // Label 581: @25937 |
| 9098 | /* 25937 */ GIM_Reject, |
| 9099 | /* 25938 */ // Label 518: @25938 |
| 9100 | /* 25938 */ GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(26049), |
| 9101 | /* 25943 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9102 | /* 25946 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9103 | /* 25949 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 583*/ GIMT_Encode4(25988), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2923 // |
| 9104 | /* 25956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9105 | /* 25960 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9106 | /* 25964 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9107 | /* 25968 */ // (or:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VORRq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) |
| 9108 | /* 25968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 9109 | /* 25971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9110 | /* 25973 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9111 | /* 25975 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9112 | /* 25977 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9113 | /* 25980 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9114 | /* 25986 */ GIR_RootConstrainSelectedInstOperands, |
| 9115 | /* 25987 */ // GIR_Coverage, 2923, |
| 9116 | /* 25987 */ GIR_EraseRootFromParent_Done, |
| 9117 | /* 25988 */ // Label 583: @25988 |
| 9118 | /* 25988 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 584*/ GIMT_Encode4(26048), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3773 // |
| 9119 | /* 25995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9120 | /* 25999 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9121 | /* 26003 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9122 | /* 26007 */ // (or:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VORR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 9123 | /* 26007 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9124 | /* 26010 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9125 | /* 26014 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9126 | /* 26019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 9127 | /* 26022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9128 | /* 26024 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9129 | /* 26026 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9130 | /* 26028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9131 | /* 26031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9132 | /* 26037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9133 | /* 26043 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9134 | /* 26046 */ GIR_RootConstrainSelectedInstOperands, |
| 9135 | /* 26047 */ // GIR_Coverage, 3773, |
| 9136 | /* 26047 */ GIR_EraseRootFromParent_Done, |
| 9137 | /* 26048 */ // Label 584: @26048 |
| 9138 | /* 26048 */ GIM_Reject, |
| 9139 | /* 26049 */ // Label 582: @26049 |
| 9140 | /* 26049 */ GIM_Reject, |
| 9141 | /* 26050 */ // Label 519: @26050 |
| 9142 | /* 26050 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 585*/ GIMT_Encode4(26095), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1299 // |
| 9143 | /* 26057 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9144 | /* 26060 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 9145 | /* 26063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9146 | /* 26067 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9147 | /* 26071 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9148 | /* 26075 */ // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 9149 | /* 26075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 9150 | /* 26078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9151 | /* 26080 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9152 | /* 26082 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9153 | /* 26084 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9154 | /* 26087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9155 | /* 26093 */ GIR_RootConstrainSelectedInstOperands, |
| 9156 | /* 26094 */ // GIR_Coverage, 1299, |
| 9157 | /* 26094 */ GIR_EraseRootFromParent_Done, |
| 9158 | /* 26095 */ // Label 585: @26095 |
| 9159 | /* 26095 */ GIM_Reject, |
| 9160 | /* 26096 */ // Label 520: @26096 |
| 9161 | /* 26096 */ GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(26207), |
| 9162 | /* 26101 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9163 | /* 26104 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9164 | /* 26107 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 587*/ GIMT_Encode4(26146), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1300 // |
| 9165 | /* 26114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9166 | /* 26118 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9167 | /* 26122 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9168 | /* 26126 */ // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 9169 | /* 26126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 9170 | /* 26129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9171 | /* 26131 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9172 | /* 26133 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9173 | /* 26135 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9174 | /* 26138 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9175 | /* 26144 */ GIR_RootConstrainSelectedInstOperands, |
| 9176 | /* 26145 */ // GIR_Coverage, 1300, |
| 9177 | /* 26145 */ GIR_EraseRootFromParent_Done, |
| 9178 | /* 26146 */ // Label 587: @26146 |
| 9179 | /* 26146 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 588*/ GIMT_Encode4(26206), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3777 // |
| 9180 | /* 26153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9181 | /* 26157 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9182 | /* 26161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9183 | /* 26165 */ // (or:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VORR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 9184 | /* 26165 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9185 | /* 26168 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9186 | /* 26172 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9187 | /* 26177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 9188 | /* 26180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9189 | /* 26182 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9190 | /* 26184 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9191 | /* 26186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9192 | /* 26189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9193 | /* 26195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9194 | /* 26201 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9195 | /* 26204 */ GIR_RootConstrainSelectedInstOperands, |
| 9196 | /* 26205 */ // GIR_Coverage, 3777, |
| 9197 | /* 26205 */ GIR_EraseRootFromParent_Done, |
| 9198 | /* 26206 */ // Label 588: @26206 |
| 9199 | /* 26206 */ GIM_Reject, |
| 9200 | /* 26207 */ // Label 586: @26207 |
| 9201 | /* 26207 */ GIM_Reject, |
| 9202 | /* 26208 */ // Label 521: @26208 |
| 9203 | /* 26208 */ GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(26319), |
| 9204 | /* 26213 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 9205 | /* 26216 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9206 | /* 26219 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 590*/ GIMT_Encode4(26258), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2924 // |
| 9207 | /* 26226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9208 | /* 26230 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9209 | /* 26234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9210 | /* 26238 */ // (or:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VORRq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) |
| 9211 | /* 26238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 9212 | /* 26241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9213 | /* 26243 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9214 | /* 26245 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9215 | /* 26247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9216 | /* 26250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9217 | /* 26256 */ GIR_RootConstrainSelectedInstOperands, |
| 9218 | /* 26257 */ // GIR_Coverage, 2924, |
| 9219 | /* 26257 */ GIR_EraseRootFromParent_Done, |
| 9220 | /* 26258 */ // Label 590: @26258 |
| 9221 | /* 26258 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 591*/ GIMT_Encode4(26318), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3781 // |
| 9222 | /* 26265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9223 | /* 26269 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9224 | /* 26273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9225 | /* 26277 */ // (or:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VORR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) |
| 9226 | /* 26277 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9227 | /* 26280 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9228 | /* 26284 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9229 | /* 26289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 9230 | /* 26292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9231 | /* 26294 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9232 | /* 26296 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9233 | /* 26298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9234 | /* 26301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9235 | /* 26307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9236 | /* 26313 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9237 | /* 26316 */ GIR_RootConstrainSelectedInstOperands, |
| 9238 | /* 26317 */ // GIR_Coverage, 3781, |
| 9239 | /* 26317 */ GIR_EraseRootFromParent_Done, |
| 9240 | /* 26318 */ // Label 591: @26318 |
| 9241 | /* 26318 */ GIM_Reject, |
| 9242 | /* 26319 */ // Label 589: @26319 |
| 9243 | /* 26319 */ GIM_Reject, |
| 9244 | /* 26320 */ // Label 522: @26320 |
| 9245 | /* 26320 */ GIM_Reject, |
| 9246 | /* 26321 */ // Label 7: @26321 |
| 9247 | /* 26321 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 605*/ GIMT_Encode4(27979), |
| 9248 | /* 26332 */ /*GILLT_s32*//*Label 592*/ GIMT_Encode4(26384), |
| 9249 | /* 26336 */ /*GILLT_s64*//*Label 593*/ GIMT_Encode4(26879), |
| 9250 | /* 26340 */ /*GILLT_v2s1*//*Label 594*/ GIMT_Encode4(26925), |
| 9251 | /* 26344 */ /*GILLT_v4s1*//*Label 595*/ GIMT_Encode4(27042), |
| 9252 | /* 26348 */ /*GILLT_v8s1*//*Label 596*/ GIMT_Encode4(27159), |
| 9253 | /* 26352 */ /*GILLT_v16s1*//*Label 597*/ GIMT_Encode4(27276), |
| 9254 | /* 26356 */ /*GILLT_v8s8*//*Label 598*/ GIMT_Encode4(27393), |
| 9255 | /* 26360 */ /*GILLT_v16s8*//*Label 599*/ GIMT_Encode4(27439), |
| 9256 | /* 26364 */ /*GILLT_v4s16*//*Label 600*/ GIMT_Encode4(27551), |
| 9257 | /* 26368 */ /*GILLT_v8s16*//*Label 601*/ GIMT_Encode4(27597), |
| 9258 | /* 26372 */ /*GILLT_v2s32*//*Label 602*/ GIMT_Encode4(27709), |
| 9259 | /* 26376 */ /*GILLT_v4s32*//*Label 603*/ GIMT_Encode4(27755), |
| 9260 | /* 26380 */ /*GILLT_v2s64*//*Label 604*/ GIMT_Encode4(27867), |
| 9261 | /* 26384 */ // Label 592: @26384 |
| 9262 | /* 26384 */ GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(26878), |
| 9263 | /* 26389 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 9264 | /* 26392 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 9265 | /* 26395 */ GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(26544), |
| 9266 | /* 26400 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9267 | /* 26404 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 608*/ GIMT_Encode4(26454), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6013 // |
| 9268 | /* 26411 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 255, |
| 9269 | /* 26415 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9270 | /* 26419 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 9271 | /* 26423 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 9272 | /* 26427 */ // MIs[1] Operand 1 |
| 9273 | /* 26427 */ // No operand predicates |
| 9274 | /* 26427 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9275 | /* 26429 */ // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 9276 | /* 26429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 9277 | /* 26432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9278 | /* 26434 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 9279 | /* 26437 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9280 | /* 26440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9281 | /* 26446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9282 | /* 26452 */ GIR_RootConstrainSelectedInstOperands, |
| 9283 | /* 26453 */ // GIR_Coverage, 6013, |
| 9284 | /* 26453 */ GIR_EraseRootFromParent_Done, |
| 9285 | /* 26454 */ // Label 608: @26454 |
| 9286 | /* 26454 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 609*/ GIMT_Encode4(26504), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 498 // |
| 9287 | /* 26461 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9288 | /* 26465 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 9289 | /* 26469 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 9290 | /* 26473 */ // MIs[1] Operand 1 |
| 9291 | /* 26473 */ // No operand predicates |
| 9292 | /* 26473 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255, |
| 9293 | /* 26477 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9294 | /* 26479 */ // (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 9295 | /* 26479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 9296 | /* 26482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9297 | /* 26484 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 9298 | /* 26487 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9299 | /* 26490 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9300 | /* 26496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9301 | /* 26502 */ GIR_RootConstrainSelectedInstOperands, |
| 9302 | /* 26503 */ // GIR_Coverage, 498, |
| 9303 | /* 26503 */ GIR_EraseRootFromParent_Done, |
| 9304 | /* 26504 */ // Label 609: @26504 |
| 9305 | /* 26504 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 610*/ GIMT_Encode4(26543), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 499 // |
| 9306 | /* 26511 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9307 | /* 26515 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255, |
| 9308 | /* 26519 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 9309 | /* 26519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNr), |
| 9310 | /* 26522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9311 | /* 26524 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 9312 | /* 26526 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9313 | /* 26529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9314 | /* 26535 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9315 | /* 26541 */ GIR_RootConstrainSelectedInstOperands, |
| 9316 | /* 26542 */ // GIR_Coverage, 499, |
| 9317 | /* 26542 */ GIR_EraseRootFromParent_Done, |
| 9318 | /* 26543 */ // Label 610: @26543 |
| 9319 | /* 26543 */ GIM_Reject, |
| 9320 | /* 26544 */ // Label 607: @26544 |
| 9321 | /* 26544 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 611*/ GIMT_Encode4(26587), GIMT_Encode2(GIFBS_IsARM), // Rule ID 164 // |
| 9322 | /* 26551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9323 | /* 26555 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9324 | /* 26559 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255, |
| 9325 | /* 26563 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 9326 | /* 26563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNr), |
| 9327 | /* 26566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9328 | /* 26568 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 9329 | /* 26570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9330 | /* 26573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9331 | /* 26579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9332 | /* 26585 */ GIR_RootConstrainSelectedInstOperands, |
| 9333 | /* 26586 */ // GIR_Coverage, 164, |
| 9334 | /* 26586 */ GIR_EraseRootFromParent_Done, |
| 9335 | /* 26587 */ // Label 611: @26587 |
| 9336 | /* 26587 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 612*/ GIMT_Encode4(26630), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 323 // |
| 9337 | /* 26594 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9338 | /* 26598 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9339 | /* 26602 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255, |
| 9340 | /* 26606 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, -1:{ *:[i32] }) => (tMVN:{ *:[i32] } tGPR:{ *:[i32] }:$Rn) |
| 9341 | /* 26606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMVN), |
| 9342 | /* 26609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9343 | /* 26611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 9344 | /* 26617 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9345 | /* 26619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9346 | /* 26622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9347 | /* 26628 */ GIR_RootConstrainSelectedInstOperands, |
| 9348 | /* 26629 */ // GIR_Coverage, 323, |
| 9349 | /* 26629 */ GIR_EraseRootFromParent_Done, |
| 9350 | /* 26630 */ // Label 612: @26630 |
| 9351 | /* 26630 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 613*/ GIMT_Encode4(26686), GIMT_Encode2(GIFBS_IsARM), // Rule ID 154 // |
| 9352 | /* 26637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9353 | /* 26641 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9354 | /* 26645 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9355 | /* 26649 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 9356 | /* 26653 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 9357 | /* 26657 */ // MIs[1] Operand 1 |
| 9358 | /* 26657 */ // No operand predicates |
| 9359 | /* 26657 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9360 | /* 26659 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 9361 | /* 26659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORri), |
| 9362 | /* 26662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9363 | /* 26664 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9364 | /* 26666 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 9365 | /* 26669 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9366 | /* 26672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9367 | /* 26678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9368 | /* 26684 */ GIR_RootConstrainSelectedInstOperands, |
| 9369 | /* 26685 */ // GIR_Coverage, 154, |
| 9370 | /* 26685 */ GIR_EraseRootFromParent_Done, |
| 9371 | /* 26686 */ // Label 613: @26686 |
| 9372 | /* 26686 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 614*/ GIMT_Encode4(26742), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 486 // |
| 9373 | /* 26693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9374 | /* 26697 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9375 | /* 26701 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9376 | /* 26705 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 9377 | /* 26709 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 9378 | /* 26713 */ // MIs[1] Operand 1 |
| 9379 | /* 26713 */ // No operand predicates |
| 9380 | /* 26713 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9381 | /* 26715 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 9382 | /* 26715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORri), |
| 9383 | /* 26718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9384 | /* 26720 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9385 | /* 26722 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 9386 | /* 26725 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9387 | /* 26728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9388 | /* 26734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9389 | /* 26740 */ GIR_RootConstrainSelectedInstOperands, |
| 9390 | /* 26741 */ // GIR_Coverage, 486, |
| 9391 | /* 26741 */ GIR_EraseRootFromParent_Done, |
| 9392 | /* 26742 */ // Label 614: @26742 |
| 9393 | /* 26742 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 615*/ GIMT_Encode4(26787), GIMT_Encode2(GIFBS_IsARM), // Rule ID 155 // |
| 9394 | /* 26749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9395 | /* 26753 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9396 | /* 26757 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9397 | /* 26761 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 9398 | /* 26761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORrr), |
| 9399 | /* 26764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9400 | /* 26766 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9401 | /* 26768 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 9402 | /* 26770 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9403 | /* 26773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9404 | /* 26779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9405 | /* 26785 */ GIR_RootConstrainSelectedInstOperands, |
| 9406 | /* 26786 */ // GIR_Coverage, 155, |
| 9407 | /* 26786 */ GIR_EraseRootFromParent_Done, |
| 9408 | /* 26787 */ // Label 615: @26787 |
| 9409 | /* 26787 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 616*/ GIMT_Encode4(26832), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 316 // |
| 9410 | /* 26794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9411 | /* 26798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9412 | /* 26802 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9413 | /* 26806 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tEOR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 9414 | /* 26806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tEOR), |
| 9415 | /* 26809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 9416 | /* 26811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 9417 | /* 26817 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9418 | /* 26819 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 9419 | /* 26821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9420 | /* 26824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9421 | /* 26830 */ GIR_RootConstrainSelectedInstOperands, |
| 9422 | /* 26831 */ // GIR_Coverage, 316, |
| 9423 | /* 26831 */ GIR_EraseRootFromParent_Done, |
| 9424 | /* 26832 */ // Label 616: @26832 |
| 9425 | /* 26832 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 617*/ GIMT_Encode4(26877), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 487 // |
| 9426 | /* 26839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9427 | /* 26843 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9428 | /* 26847 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9429 | /* 26851 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 9430 | /* 26851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9431 | /* 26854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9432 | /* 26856 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9433 | /* 26858 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 9434 | /* 26860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9435 | /* 26863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9436 | /* 26869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9437 | /* 26875 */ GIR_RootConstrainSelectedInstOperands, |
| 9438 | /* 26876 */ // GIR_Coverage, 487, |
| 9439 | /* 26876 */ GIR_EraseRootFromParent_Done, |
| 9440 | /* 26877 */ // Label 617: @26877 |
| 9441 | /* 26877 */ GIM_Reject, |
| 9442 | /* 26878 */ // Label 606: @26878 |
| 9443 | /* 26878 */ GIM_Reject, |
| 9444 | /* 26879 */ // Label 593: @26879 |
| 9445 | /* 26879 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 618*/ GIMT_Encode4(26924), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2927 // |
| 9446 | /* 26886 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9447 | /* 26889 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9448 | /* 26892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9449 | /* 26896 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9450 | /* 26900 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9451 | /* 26904 */ // (xor:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VEORd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) |
| 9452 | /* 26904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 9453 | /* 26907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9454 | /* 26909 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9455 | /* 26911 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9456 | /* 26913 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9457 | /* 26916 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9458 | /* 26922 */ GIR_RootConstrainSelectedInstOperands, |
| 9459 | /* 26923 */ // GIR_Coverage, 2927, |
| 9460 | /* 26923 */ GIR_EraseRootFromParent_Done, |
| 9461 | /* 26924 */ // Label 618: @26924 |
| 9462 | /* 26924 */ GIM_Reject, |
| 9463 | /* 26925 */ // Label 594: @26925 |
| 9464 | /* 26925 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 619*/ GIMT_Encode4(27041), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2018 // |
| 9465 | /* 26932 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, |
| 9466 | /* 26935 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, |
| 9467 | /* 26938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9468 | /* 26942 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9469 | /* 26946 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9470 | /* 26950 */ // (xor:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9471 | /* 26950 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9472 | /* 26953 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9473 | /* 26957 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9474 | /* 26962 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9475 | /* 26966 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9476 | /* 26971 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9477 | /* 26974 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9478 | /* 26978 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9479 | /* 26983 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9480 | /* 26987 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9481 | /* 26992 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9482 | /* 26995 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9483 | /* 26999 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9484 | /* 27004 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9485 | /* 27007 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9486 | /* 27010 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9487 | /* 27013 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9488 | /* 27019 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9489 | /* 27025 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9490 | /* 27027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9491 | /* 27030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9492 | /* 27032 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9493 | /* 27035 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9494 | /* 27040 */ // GIR_Coverage, 2018, |
| 9495 | /* 27040 */ GIR_EraseRootFromParent_Done, |
| 9496 | /* 27041 */ // Label 619: @27041 |
| 9497 | /* 27041 */ GIM_Reject, |
| 9498 | /* 27042 */ // Label 595: @27042 |
| 9499 | /* 27042 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 620*/ GIMT_Encode4(27158), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2019 // |
| 9500 | /* 27049 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, |
| 9501 | /* 27052 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, |
| 9502 | /* 27055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9503 | /* 27059 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9504 | /* 27063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9505 | /* 27067 */ // (xor:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9506 | /* 27067 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9507 | /* 27070 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9508 | /* 27074 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9509 | /* 27079 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9510 | /* 27083 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9511 | /* 27088 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9512 | /* 27091 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9513 | /* 27095 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9514 | /* 27100 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9515 | /* 27104 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9516 | /* 27109 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9517 | /* 27112 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9518 | /* 27116 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9519 | /* 27121 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9520 | /* 27124 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9521 | /* 27127 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9522 | /* 27130 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9523 | /* 27136 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9524 | /* 27142 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9525 | /* 27144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9526 | /* 27147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9527 | /* 27149 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9528 | /* 27152 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9529 | /* 27157 */ // GIR_Coverage, 2019, |
| 9530 | /* 27157 */ GIR_EraseRootFromParent_Done, |
| 9531 | /* 27158 */ // Label 620: @27158 |
| 9532 | /* 27158 */ GIM_Reject, |
| 9533 | /* 27159 */ // Label 596: @27159 |
| 9534 | /* 27159 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 621*/ GIMT_Encode4(27275), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2020 // |
| 9535 | /* 27166 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, |
| 9536 | /* 27169 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, |
| 9537 | /* 27172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9538 | /* 27176 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9539 | /* 27180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9540 | /* 27184 */ // (xor:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9541 | /* 27184 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9542 | /* 27187 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9543 | /* 27191 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9544 | /* 27196 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9545 | /* 27200 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9546 | /* 27205 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9547 | /* 27208 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9548 | /* 27212 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9549 | /* 27217 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9550 | /* 27221 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9551 | /* 27226 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9552 | /* 27229 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9553 | /* 27233 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9554 | /* 27238 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9555 | /* 27241 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9556 | /* 27244 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9557 | /* 27247 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9558 | /* 27253 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9559 | /* 27259 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9560 | /* 27261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9561 | /* 27264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9562 | /* 27266 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9563 | /* 27269 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9564 | /* 27274 */ // GIR_Coverage, 2020, |
| 9565 | /* 27274 */ GIR_EraseRootFromParent_Done, |
| 9566 | /* 27275 */ // Label 621: @27275 |
| 9567 | /* 27275 */ GIM_Reject, |
| 9568 | /* 27276 */ // Label 597: @27276 |
| 9569 | /* 27276 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 622*/ GIMT_Encode4(27392), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2021 // |
| 9570 | /* 27283 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, |
| 9571 | /* 27286 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, |
| 9572 | /* 27289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9573 | /* 27293 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9574 | /* 27297 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9575 | /* 27301 */ // (xor:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9576 | /* 27301 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9577 | /* 27304 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9578 | /* 27308 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9579 | /* 27313 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9580 | /* 27317 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9581 | /* 27322 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9582 | /* 27325 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9583 | /* 27329 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9584 | /* 27334 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9585 | /* 27338 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9586 | /* 27343 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9587 | /* 27346 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9588 | /* 27350 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9589 | /* 27355 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9590 | /* 27358 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9591 | /* 27361 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9592 | /* 27364 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9593 | /* 27370 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9594 | /* 27376 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9595 | /* 27378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9596 | /* 27381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9597 | /* 27383 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9598 | /* 27386 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9599 | /* 27391 */ // GIR_Coverage, 2021, |
| 9600 | /* 27391 */ GIR_EraseRootFromParent_Done, |
| 9601 | /* 27392 */ // Label 622: @27392 |
| 9602 | /* 27392 */ GIM_Reject, |
| 9603 | /* 27393 */ // Label 598: @27393 |
| 9604 | /* 27393 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 623*/ GIMT_Encode4(27438), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2925 // |
| 9605 | /* 27400 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9606 | /* 27403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 9607 | /* 27406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9608 | /* 27410 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9609 | /* 27414 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9610 | /* 27418 */ // (xor:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VEORd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) |
| 9611 | /* 27418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 9612 | /* 27421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9613 | /* 27423 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9614 | /* 27425 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9615 | /* 27427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9616 | /* 27430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9617 | /* 27436 */ GIR_RootConstrainSelectedInstOperands, |
| 9618 | /* 27437 */ // GIR_Coverage, 2925, |
| 9619 | /* 27437 */ GIR_EraseRootFromParent_Done, |
| 9620 | /* 27438 */ // Label 623: @27438 |
| 9621 | /* 27438 */ GIM_Reject, |
| 9622 | /* 27439 */ // Label 599: @27439 |
| 9623 | /* 27439 */ GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(27550), |
| 9624 | /* 27444 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9625 | /* 27447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9626 | /* 27450 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 625*/ GIMT_Encode4(27489), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2928 // |
| 9627 | /* 27457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9628 | /* 27461 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9629 | /* 27465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9630 | /* 27469 */ // (xor:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VEORq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) |
| 9631 | /* 27469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 9632 | /* 27472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9633 | /* 27474 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9634 | /* 27476 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9635 | /* 27478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9636 | /* 27481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9637 | /* 27487 */ GIR_RootConstrainSelectedInstOperands, |
| 9638 | /* 27488 */ // GIR_Coverage, 2928, |
| 9639 | /* 27488 */ GIR_EraseRootFromParent_Done, |
| 9640 | /* 27489 */ // Label 625: @27489 |
| 9641 | /* 27489 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 626*/ GIMT_Encode4(27549), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3783 // |
| 9642 | /* 27496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9643 | /* 27500 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9644 | /* 27504 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9645 | /* 27508 */ // (xor:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VEOR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 9646 | /* 27508 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9647 | /* 27511 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9648 | /* 27515 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9649 | /* 27520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 9650 | /* 27523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9651 | /* 27525 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9652 | /* 27527 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9653 | /* 27529 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9654 | /* 27532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9655 | /* 27538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9656 | /* 27544 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9657 | /* 27547 */ GIR_RootConstrainSelectedInstOperands, |
| 9658 | /* 27548 */ // GIR_Coverage, 3783, |
| 9659 | /* 27548 */ GIR_EraseRootFromParent_Done, |
| 9660 | /* 27549 */ // Label 626: @27549 |
| 9661 | /* 27549 */ GIM_Reject, |
| 9662 | /* 27550 */ // Label 624: @27550 |
| 9663 | /* 27550 */ GIM_Reject, |
| 9664 | /* 27551 */ // Label 600: @27551 |
| 9665 | /* 27551 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 627*/ GIMT_Encode4(27596), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2926 // |
| 9666 | /* 27558 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9667 | /* 27561 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 9668 | /* 27564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9669 | /* 27568 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9670 | /* 27572 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9671 | /* 27576 */ // (xor:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VEORd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) |
| 9672 | /* 27576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 9673 | /* 27579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9674 | /* 27581 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9675 | /* 27583 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9676 | /* 27585 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9677 | /* 27588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9678 | /* 27594 */ GIR_RootConstrainSelectedInstOperands, |
| 9679 | /* 27595 */ // GIR_Coverage, 2926, |
| 9680 | /* 27595 */ GIR_EraseRootFromParent_Done, |
| 9681 | /* 27596 */ // Label 627: @27596 |
| 9682 | /* 27596 */ GIM_Reject, |
| 9683 | /* 27597 */ // Label 601: @27597 |
| 9684 | /* 27597 */ GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(27708), |
| 9685 | /* 27602 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9686 | /* 27605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9687 | /* 27608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 629*/ GIMT_Encode4(27647), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2929 // |
| 9688 | /* 27615 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9689 | /* 27619 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9690 | /* 27623 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9691 | /* 27627 */ // (xor:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VEORq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) |
| 9692 | /* 27627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 9693 | /* 27630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9694 | /* 27632 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9695 | /* 27634 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9696 | /* 27636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9697 | /* 27639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9698 | /* 27645 */ GIR_RootConstrainSelectedInstOperands, |
| 9699 | /* 27646 */ // GIR_Coverage, 2929, |
| 9700 | /* 27646 */ GIR_EraseRootFromParent_Done, |
| 9701 | /* 27647 */ // Label 629: @27647 |
| 9702 | /* 27647 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 630*/ GIMT_Encode4(27707), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3787 // |
| 9703 | /* 27654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9704 | /* 27658 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9705 | /* 27662 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9706 | /* 27666 */ // (xor:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VEOR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 9707 | /* 27666 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9708 | /* 27669 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9709 | /* 27673 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9710 | /* 27678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 9711 | /* 27681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9712 | /* 27683 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9713 | /* 27685 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9714 | /* 27687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9715 | /* 27690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9716 | /* 27696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9717 | /* 27702 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9718 | /* 27705 */ GIR_RootConstrainSelectedInstOperands, |
| 9719 | /* 27706 */ // GIR_Coverage, 3787, |
| 9720 | /* 27706 */ GIR_EraseRootFromParent_Done, |
| 9721 | /* 27707 */ // Label 630: @27707 |
| 9722 | /* 27707 */ GIM_Reject, |
| 9723 | /* 27708 */ // Label 628: @27708 |
| 9724 | /* 27708 */ GIM_Reject, |
| 9725 | /* 27709 */ // Label 602: @27709 |
| 9726 | /* 27709 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 631*/ GIMT_Encode4(27754), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1297 // |
| 9727 | /* 27716 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9728 | /* 27719 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 9729 | /* 27722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9730 | /* 27726 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9731 | /* 27730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9732 | /* 27734 */ // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 9733 | /* 27734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 9734 | /* 27737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9735 | /* 27739 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9736 | /* 27741 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9737 | /* 27743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9738 | /* 27746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9739 | /* 27752 */ GIR_RootConstrainSelectedInstOperands, |
| 9740 | /* 27753 */ // GIR_Coverage, 1297, |
| 9741 | /* 27753 */ GIR_EraseRootFromParent_Done, |
| 9742 | /* 27754 */ // Label 631: @27754 |
| 9743 | /* 27754 */ GIM_Reject, |
| 9744 | /* 27755 */ // Label 603: @27755 |
| 9745 | /* 27755 */ GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(27866), |
| 9746 | /* 27760 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9747 | /* 27763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9748 | /* 27766 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 633*/ GIMT_Encode4(27805), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1298 // |
| 9749 | /* 27773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9750 | /* 27777 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9751 | /* 27781 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9752 | /* 27785 */ // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 9753 | /* 27785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 9754 | /* 27788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9755 | /* 27790 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9756 | /* 27792 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9757 | /* 27794 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9758 | /* 27797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9759 | /* 27803 */ GIR_RootConstrainSelectedInstOperands, |
| 9760 | /* 27804 */ // GIR_Coverage, 1298, |
| 9761 | /* 27804 */ GIR_EraseRootFromParent_Done, |
| 9762 | /* 27805 */ // Label 633: @27805 |
| 9763 | /* 27805 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 634*/ GIMT_Encode4(27865), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3791 // |
| 9764 | /* 27812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9765 | /* 27816 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9766 | /* 27820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9767 | /* 27824 */ // (xor:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VEOR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 9768 | /* 27824 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9769 | /* 27827 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9770 | /* 27831 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9771 | /* 27836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 9772 | /* 27839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9773 | /* 27841 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9774 | /* 27843 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9775 | /* 27845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9776 | /* 27848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9777 | /* 27854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9778 | /* 27860 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9779 | /* 27863 */ GIR_RootConstrainSelectedInstOperands, |
| 9780 | /* 27864 */ // GIR_Coverage, 3791, |
| 9781 | /* 27864 */ GIR_EraseRootFromParent_Done, |
| 9782 | /* 27865 */ // Label 634: @27865 |
| 9783 | /* 27865 */ GIM_Reject, |
| 9784 | /* 27866 */ // Label 632: @27866 |
| 9785 | /* 27866 */ GIM_Reject, |
| 9786 | /* 27867 */ // Label 604: @27867 |
| 9787 | /* 27867 */ GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(27978), |
| 9788 | /* 27872 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 9789 | /* 27875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9790 | /* 27878 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 636*/ GIMT_Encode4(27917), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2930 // |
| 9791 | /* 27885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9792 | /* 27889 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9793 | /* 27893 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9794 | /* 27897 */ // (xor:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VEORq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) |
| 9795 | /* 27897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 9796 | /* 27900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9797 | /* 27902 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9798 | /* 27904 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9799 | /* 27906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9800 | /* 27909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9801 | /* 27915 */ GIR_RootConstrainSelectedInstOperands, |
| 9802 | /* 27916 */ // GIR_Coverage, 2930, |
| 9803 | /* 27916 */ GIR_EraseRootFromParent_Done, |
| 9804 | /* 27917 */ // Label 636: @27917 |
| 9805 | /* 27917 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 637*/ GIMT_Encode4(27977), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3795 // |
| 9806 | /* 27924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9807 | /* 27928 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9808 | /* 27932 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9809 | /* 27936 */ // (xor:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VEOR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) |
| 9810 | /* 27936 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9811 | /* 27939 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9812 | /* 27943 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9813 | /* 27948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 9814 | /* 27951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9815 | /* 27953 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9816 | /* 27955 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9817 | /* 27957 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9818 | /* 27960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9819 | /* 27966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9820 | /* 27972 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9821 | /* 27975 */ GIR_RootConstrainSelectedInstOperands, |
| 9822 | /* 27976 */ // GIR_Coverage, 3795, |
| 9823 | /* 27976 */ GIR_EraseRootFromParent_Done, |
| 9824 | /* 27977 */ // Label 637: @27977 |
| 9825 | /* 27977 */ GIM_Reject, |
| 9826 | /* 27978 */ // Label 635: @27978 |
| 9827 | /* 27978 */ GIM_Reject, |
| 9828 | /* 27979 */ // Label 605: @27979 |
| 9829 | /* 27979 */ GIM_Reject, |
| 9830 | /* 27980 */ // Label 8: @27980 |
| 9831 | /* 27980 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 644*/ GIMT_Encode4(28489), |
| 9832 | /* 27991 */ /*GILLT_v8s8*//*Label 638*/ GIMT_Encode4(28015), |
| 9833 | /* 27995 */ /*GILLT_v16s8*//*Label 639*/ GIMT_Encode4(28061), |
| 9834 | /* 27999 */ /*GILLT_v4s16*//*Label 640*/ GIMT_Encode4(28173), |
| 9835 | /* 28003 */ /*GILLT_v8s16*//*Label 641*/ GIMT_Encode4(28219), |
| 9836 | /* 28007 */ /*GILLT_v2s32*//*Label 642*/ GIMT_Encode4(28331), |
| 9837 | /* 28011 */ /*GILLT_v4s32*//*Label 643*/ GIMT_Encode4(28377), |
| 9838 | /* 28015 */ // Label 638: @28015 |
| 9839 | /* 28015 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 645*/ GIMT_Encode4(28060), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1323 // |
| 9840 | /* 28022 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9841 | /* 28025 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 9842 | /* 28028 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9843 | /* 28032 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9844 | /* 28036 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9845 | /* 28040 */ // (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 9846 | /* 28040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i8), |
| 9847 | /* 28043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9848 | /* 28045 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9849 | /* 28047 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9850 | /* 28049 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9851 | /* 28052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9852 | /* 28058 */ GIR_RootConstrainSelectedInstOperands, |
| 9853 | /* 28059 */ // GIR_Coverage, 1323, |
| 9854 | /* 28059 */ GIR_EraseRootFromParent_Done, |
| 9855 | /* 28060 */ // Label 645: @28060 |
| 9856 | /* 28060 */ GIM_Reject, |
| 9857 | /* 28061 */ // Label 639: @28061 |
| 9858 | /* 28061 */ GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(28172), |
| 9859 | /* 28066 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9860 | /* 28069 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9861 | /* 28072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 647*/ GIMT_Encode4(28111), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1324 // |
| 9862 | /* 28079 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9863 | /* 28083 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9864 | /* 28087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9865 | /* 28091 */ // (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 9866 | /* 28091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv16i8), |
| 9867 | /* 28094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9868 | /* 28096 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9869 | /* 28098 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9870 | /* 28100 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9871 | /* 28103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9872 | /* 28109 */ GIR_RootConstrainSelectedInstOperands, |
| 9873 | /* 28110 */ // GIR_Coverage, 1324, |
| 9874 | /* 28110 */ GIR_EraseRootFromParent_Done, |
| 9875 | /* 28111 */ // Label 647: @28111 |
| 9876 | /* 28111 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 648*/ GIMT_Encode4(28171), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3946 // |
| 9877 | /* 28118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9878 | /* 28122 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9879 | /* 28126 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9880 | /* 28130 */ // (abds:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 9881 | /* 28130 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9882 | /* 28133 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9883 | /* 28137 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9884 | /* 28142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8), |
| 9885 | /* 28145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9886 | /* 28147 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9887 | /* 28149 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9888 | /* 28151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9889 | /* 28154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9890 | /* 28160 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9891 | /* 28166 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9892 | /* 28169 */ GIR_RootConstrainSelectedInstOperands, |
| 9893 | /* 28170 */ // GIR_Coverage, 3946, |
| 9894 | /* 28170 */ GIR_EraseRootFromParent_Done, |
| 9895 | /* 28171 */ // Label 648: @28171 |
| 9896 | /* 28171 */ GIM_Reject, |
| 9897 | /* 28172 */ // Label 646: @28172 |
| 9898 | /* 28172 */ GIM_Reject, |
| 9899 | /* 28173 */ // Label 640: @28173 |
| 9900 | /* 28173 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 649*/ GIMT_Encode4(28218), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1319 // |
| 9901 | /* 28180 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9902 | /* 28183 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 9903 | /* 28186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9904 | /* 28190 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9905 | /* 28194 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9906 | /* 28198 */ // (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 9907 | /* 28198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i16), |
| 9908 | /* 28201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9909 | /* 28203 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9910 | /* 28205 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9911 | /* 28207 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9912 | /* 28210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9913 | /* 28216 */ GIR_RootConstrainSelectedInstOperands, |
| 9914 | /* 28217 */ // GIR_Coverage, 1319, |
| 9915 | /* 28217 */ GIR_EraseRootFromParent_Done, |
| 9916 | /* 28218 */ // Label 649: @28218 |
| 9917 | /* 28218 */ GIM_Reject, |
| 9918 | /* 28219 */ // Label 641: @28219 |
| 9919 | /* 28219 */ GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(28330), |
| 9920 | /* 28224 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9921 | /* 28227 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9922 | /* 28230 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 651*/ GIMT_Encode4(28269), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1321 // |
| 9923 | /* 28237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9924 | /* 28241 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9925 | /* 28245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9926 | /* 28249 */ // (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 9927 | /* 28249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i16), |
| 9928 | /* 28252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9929 | /* 28254 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9930 | /* 28256 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9931 | /* 28258 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9932 | /* 28261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9933 | /* 28267 */ GIR_RootConstrainSelectedInstOperands, |
| 9934 | /* 28268 */ // GIR_Coverage, 1321, |
| 9935 | /* 28268 */ GIR_EraseRootFromParent_Done, |
| 9936 | /* 28269 */ // Label 651: @28269 |
| 9937 | /* 28269 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 652*/ GIMT_Encode4(28329), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3949 // |
| 9938 | /* 28276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9939 | /* 28280 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9940 | /* 28284 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9941 | /* 28288 */ // (abds:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 9942 | /* 28288 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9943 | /* 28291 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9944 | /* 28295 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9945 | /* 28300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16), |
| 9946 | /* 28303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9947 | /* 28305 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9948 | /* 28307 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9949 | /* 28309 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9950 | /* 28312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9951 | /* 28318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9952 | /* 28324 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9953 | /* 28327 */ GIR_RootConstrainSelectedInstOperands, |
| 9954 | /* 28328 */ // GIR_Coverage, 3949, |
| 9955 | /* 28328 */ GIR_EraseRootFromParent_Done, |
| 9956 | /* 28329 */ // Label 652: @28329 |
| 9957 | /* 28329 */ GIM_Reject, |
| 9958 | /* 28330 */ // Label 650: @28330 |
| 9959 | /* 28330 */ GIM_Reject, |
| 9960 | /* 28331 */ // Label 642: @28331 |
| 9961 | /* 28331 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 653*/ GIMT_Encode4(28376), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1320 // |
| 9962 | /* 28338 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9963 | /* 28341 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 9964 | /* 28344 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9965 | /* 28348 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9966 | /* 28352 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9967 | /* 28356 */ // (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 9968 | /* 28356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv2i32), |
| 9969 | /* 28359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9970 | /* 28361 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9971 | /* 28363 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9972 | /* 28365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9973 | /* 28368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9974 | /* 28374 */ GIR_RootConstrainSelectedInstOperands, |
| 9975 | /* 28375 */ // GIR_Coverage, 1320, |
| 9976 | /* 28375 */ GIR_EraseRootFromParent_Done, |
| 9977 | /* 28376 */ // Label 653: @28376 |
| 9978 | /* 28376 */ GIM_Reject, |
| 9979 | /* 28377 */ // Label 643: @28377 |
| 9980 | /* 28377 */ GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(28488), |
| 9981 | /* 28382 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9982 | /* 28385 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9983 | /* 28388 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 655*/ GIMT_Encode4(28427), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1322 // |
| 9984 | /* 28395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9985 | /* 28399 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9986 | /* 28403 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9987 | /* 28407 */ // (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 9988 | /* 28407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i32), |
| 9989 | /* 28410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9990 | /* 28412 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9991 | /* 28414 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9992 | /* 28416 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9993 | /* 28419 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9994 | /* 28425 */ GIR_RootConstrainSelectedInstOperands, |
| 9995 | /* 28426 */ // GIR_Coverage, 1322, |
| 9996 | /* 28426 */ GIR_EraseRootFromParent_Done, |
| 9997 | /* 28427 */ // Label 655: @28427 |
| 9998 | /* 28427 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 656*/ GIMT_Encode4(28487), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3953 // |
| 9999 | /* 28434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10000 | /* 28438 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10001 | /* 28442 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10002 | /* 28446 */ // (abds:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10003 | /* 28446 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10004 | /* 28449 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10005 | /* 28453 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10006 | /* 28458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32), |
| 10007 | /* 28461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10008 | /* 28463 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10009 | /* 28465 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10010 | /* 28467 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10011 | /* 28470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10012 | /* 28476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10013 | /* 28482 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10014 | /* 28485 */ GIR_RootConstrainSelectedInstOperands, |
| 10015 | /* 28486 */ // GIR_Coverage, 3953, |
| 10016 | /* 28486 */ GIR_EraseRootFromParent_Done, |
| 10017 | /* 28487 */ // Label 656: @28487 |
| 10018 | /* 28487 */ GIM_Reject, |
| 10019 | /* 28488 */ // Label 654: @28488 |
| 10020 | /* 28488 */ GIM_Reject, |
| 10021 | /* 28489 */ // Label 644: @28489 |
| 10022 | /* 28489 */ GIM_Reject, |
| 10023 | /* 28490 */ // Label 9: @28490 |
| 10024 | /* 28490 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 663*/ GIMT_Encode4(28999), |
| 10025 | /* 28501 */ /*GILLT_v8s8*//*Label 657*/ GIMT_Encode4(28525), |
| 10026 | /* 28505 */ /*GILLT_v16s8*//*Label 658*/ GIMT_Encode4(28571), |
| 10027 | /* 28509 */ /*GILLT_v4s16*//*Label 659*/ GIMT_Encode4(28683), |
| 10028 | /* 28513 */ /*GILLT_v8s16*//*Label 660*/ GIMT_Encode4(28729), |
| 10029 | /* 28517 */ /*GILLT_v2s32*//*Label 661*/ GIMT_Encode4(28841), |
| 10030 | /* 28521 */ /*GILLT_v4s32*//*Label 662*/ GIMT_Encode4(28887), |
| 10031 | /* 28525 */ // Label 657: @28525 |
| 10032 | /* 28525 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 664*/ GIMT_Encode4(28570), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1329 // |
| 10033 | /* 28532 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 10034 | /* 28535 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 10035 | /* 28538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10036 | /* 28542 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10037 | /* 28546 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10038 | /* 28550 */ // (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 10039 | /* 28550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i8), |
| 10040 | /* 28553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10041 | /* 28555 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10042 | /* 28557 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10043 | /* 28559 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10044 | /* 28562 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10045 | /* 28568 */ GIR_RootConstrainSelectedInstOperands, |
| 10046 | /* 28569 */ // GIR_Coverage, 1329, |
| 10047 | /* 28569 */ GIR_EraseRootFromParent_Done, |
| 10048 | /* 28570 */ // Label 664: @28570 |
| 10049 | /* 28570 */ GIM_Reject, |
| 10050 | /* 28571 */ // Label 658: @28571 |
| 10051 | /* 28571 */ GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(28682), |
| 10052 | /* 28576 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10053 | /* 28579 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10054 | /* 28582 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 666*/ GIMT_Encode4(28621), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1330 // |
| 10055 | /* 28589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10056 | /* 28593 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10057 | /* 28597 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10058 | /* 28601 */ // (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 10059 | /* 28601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv16i8), |
| 10060 | /* 28604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10061 | /* 28606 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10062 | /* 28608 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10063 | /* 28610 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10064 | /* 28613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10065 | /* 28619 */ GIR_RootConstrainSelectedInstOperands, |
| 10066 | /* 28620 */ // GIR_Coverage, 1330, |
| 10067 | /* 28620 */ GIR_EraseRootFromParent_Done, |
| 10068 | /* 28621 */ // Label 666: @28621 |
| 10069 | /* 28621 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 667*/ GIMT_Encode4(28681), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3957 // |
| 10070 | /* 28628 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10071 | /* 28632 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10072 | /* 28636 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10073 | /* 28640 */ // (abdu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10074 | /* 28640 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10075 | /* 28643 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10076 | /* 28647 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10077 | /* 28652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8), |
| 10078 | /* 28655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10079 | /* 28657 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10080 | /* 28659 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10081 | /* 28661 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10082 | /* 28664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10083 | /* 28670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10084 | /* 28676 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10085 | /* 28679 */ GIR_RootConstrainSelectedInstOperands, |
| 10086 | /* 28680 */ // GIR_Coverage, 3957, |
| 10087 | /* 28680 */ GIR_EraseRootFromParent_Done, |
| 10088 | /* 28681 */ // Label 667: @28681 |
| 10089 | /* 28681 */ GIM_Reject, |
| 10090 | /* 28682 */ // Label 665: @28682 |
| 10091 | /* 28682 */ GIM_Reject, |
| 10092 | /* 28683 */ // Label 659: @28683 |
| 10093 | /* 28683 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 668*/ GIMT_Encode4(28728), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1325 // |
| 10094 | /* 28690 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10095 | /* 28693 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 10096 | /* 28696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10097 | /* 28700 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10098 | /* 28704 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10099 | /* 28708 */ // (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 10100 | /* 28708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i16), |
| 10101 | /* 28711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10102 | /* 28713 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10103 | /* 28715 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10104 | /* 28717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10105 | /* 28720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10106 | /* 28726 */ GIR_RootConstrainSelectedInstOperands, |
| 10107 | /* 28727 */ // GIR_Coverage, 1325, |
| 10108 | /* 28727 */ GIR_EraseRootFromParent_Done, |
| 10109 | /* 28728 */ // Label 668: @28728 |
| 10110 | /* 28728 */ GIM_Reject, |
| 10111 | /* 28729 */ // Label 660: @28729 |
| 10112 | /* 28729 */ GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(28840), |
| 10113 | /* 28734 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10114 | /* 28737 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10115 | /* 28740 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 670*/ GIMT_Encode4(28779), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1327 // |
| 10116 | /* 28747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10117 | /* 28751 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10118 | /* 28755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10119 | /* 28759 */ // (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 10120 | /* 28759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i16), |
| 10121 | /* 28762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10122 | /* 28764 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10123 | /* 28766 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10124 | /* 28768 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10125 | /* 28771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10126 | /* 28777 */ GIR_RootConstrainSelectedInstOperands, |
| 10127 | /* 28778 */ // GIR_Coverage, 1327, |
| 10128 | /* 28778 */ GIR_EraseRootFromParent_Done, |
| 10129 | /* 28779 */ // Label 670: @28779 |
| 10130 | /* 28779 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 671*/ GIMT_Encode4(28839), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3961 // |
| 10131 | /* 28786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10132 | /* 28790 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10133 | /* 28794 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10134 | /* 28798 */ // (abdu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10135 | /* 28798 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10136 | /* 28801 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10137 | /* 28805 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10138 | /* 28810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16), |
| 10139 | /* 28813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10140 | /* 28815 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10141 | /* 28817 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10142 | /* 28819 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10143 | /* 28822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10144 | /* 28828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10145 | /* 28834 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10146 | /* 28837 */ GIR_RootConstrainSelectedInstOperands, |
| 10147 | /* 28838 */ // GIR_Coverage, 3961, |
| 10148 | /* 28838 */ GIR_EraseRootFromParent_Done, |
| 10149 | /* 28839 */ // Label 671: @28839 |
| 10150 | /* 28839 */ GIM_Reject, |
| 10151 | /* 28840 */ // Label 669: @28840 |
| 10152 | /* 28840 */ GIM_Reject, |
| 10153 | /* 28841 */ // Label 661: @28841 |
| 10154 | /* 28841 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 672*/ GIMT_Encode4(28886), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1326 // |
| 10155 | /* 28848 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10156 | /* 28851 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10157 | /* 28854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10158 | /* 28858 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10159 | /* 28862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10160 | /* 28866 */ // (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 10161 | /* 28866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv2i32), |
| 10162 | /* 28869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10163 | /* 28871 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10164 | /* 28873 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10165 | /* 28875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10166 | /* 28878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10167 | /* 28884 */ GIR_RootConstrainSelectedInstOperands, |
| 10168 | /* 28885 */ // GIR_Coverage, 1326, |
| 10169 | /* 28885 */ GIR_EraseRootFromParent_Done, |
| 10170 | /* 28886 */ // Label 672: @28886 |
| 10171 | /* 28886 */ GIM_Reject, |
| 10172 | /* 28887 */ // Label 662: @28887 |
| 10173 | /* 28887 */ GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(28998), |
| 10174 | /* 28892 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10175 | /* 28895 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10176 | /* 28898 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 674*/ GIMT_Encode4(28937), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1328 // |
| 10177 | /* 28905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10178 | /* 28909 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10179 | /* 28913 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10180 | /* 28917 */ // (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 10181 | /* 28917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i32), |
| 10182 | /* 28920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10183 | /* 28922 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10184 | /* 28924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10185 | /* 28926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10186 | /* 28929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10187 | /* 28935 */ GIR_RootConstrainSelectedInstOperands, |
| 10188 | /* 28936 */ // GIR_Coverage, 1328, |
| 10189 | /* 28936 */ GIR_EraseRootFromParent_Done, |
| 10190 | /* 28937 */ // Label 674: @28937 |
| 10191 | /* 28937 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 675*/ GIMT_Encode4(28997), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3965 // |
| 10192 | /* 28944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10193 | /* 28948 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10194 | /* 28952 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10195 | /* 28956 */ // (abdu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10196 | /* 28956 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10197 | /* 28959 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10198 | /* 28963 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10199 | /* 28968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32), |
| 10200 | /* 28971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10201 | /* 28973 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10202 | /* 28975 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10203 | /* 28977 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10204 | /* 28980 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10205 | /* 28986 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10206 | /* 28992 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10207 | /* 28995 */ GIR_RootConstrainSelectedInstOperands, |
| 10208 | /* 28996 */ // GIR_Coverage, 3965, |
| 10209 | /* 28996 */ GIR_EraseRootFromParent_Done, |
| 10210 | /* 28997 */ // Label 675: @28997 |
| 10211 | /* 28997 */ GIM_Reject, |
| 10212 | /* 28998 */ // Label 673: @28998 |
| 10213 | /* 28998 */ GIM_Reject, |
| 10214 | /* 28999 */ // Label 663: @28999 |
| 10215 | /* 28999 */ GIM_Reject, |
| 10216 | /* 29000 */ // Label 10: @29000 |
| 10217 | /* 29000 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 679*/ GIMT_Encode4(29226), |
| 10218 | /* 29011 */ /*GILLT_v16s8*//*Label 676*/ GIMT_Encode4(29031), GIMT_Encode4(0), |
| 10219 | /* 29019 */ /*GILLT_v8s16*//*Label 677*/ GIMT_Encode4(29096), GIMT_Encode4(0), |
| 10220 | /* 29027 */ /*GILLT_v4s32*//*Label 678*/ GIMT_Encode4(29161), |
| 10221 | /* 29031 */ // Label 676: @29031 |
| 10222 | /* 29031 */ GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(29095), // Rule ID 4005 // |
| 10223 | /* 29036 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10224 | /* 29039 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10225 | /* 29042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10226 | /* 29046 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10227 | /* 29050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10228 | /* 29054 */ // (avgflooru:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10229 | /* 29054 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10230 | /* 29057 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10231 | /* 29061 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10232 | /* 29066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8), |
| 10233 | /* 29069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10234 | /* 29071 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10235 | /* 29073 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10236 | /* 29075 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10237 | /* 29078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10238 | /* 29084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10239 | /* 29090 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10240 | /* 29093 */ GIR_RootConstrainSelectedInstOperands, |
| 10241 | /* 29094 */ // GIR_Coverage, 4005, |
| 10242 | /* 29094 */ GIR_EraseRootFromParent_Done, |
| 10243 | /* 29095 */ // Label 680: @29095 |
| 10244 | /* 29095 */ GIM_Reject, |
| 10245 | /* 29096 */ // Label 677: @29096 |
| 10246 | /* 29096 */ GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(29160), // Rule ID 4009 // |
| 10247 | /* 29101 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10248 | /* 29104 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10249 | /* 29107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10250 | /* 29111 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10251 | /* 29115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10252 | /* 29119 */ // (avgflooru:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10253 | /* 29119 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10254 | /* 29122 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10255 | /* 29126 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10256 | /* 29131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16), |
| 10257 | /* 29134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10258 | /* 29136 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10259 | /* 29138 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10260 | /* 29140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10261 | /* 29143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10262 | /* 29149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10263 | /* 29155 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10264 | /* 29158 */ GIR_RootConstrainSelectedInstOperands, |
| 10265 | /* 29159 */ // GIR_Coverage, 4009, |
| 10266 | /* 29159 */ GIR_EraseRootFromParent_Done, |
| 10267 | /* 29160 */ // Label 681: @29160 |
| 10268 | /* 29160 */ GIM_Reject, |
| 10269 | /* 29161 */ // Label 678: @29161 |
| 10270 | /* 29161 */ GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(29225), // Rule ID 4013 // |
| 10271 | /* 29166 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10272 | /* 29169 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10273 | /* 29172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10274 | /* 29176 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10275 | /* 29180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10276 | /* 29184 */ // (avgflooru:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10277 | /* 29184 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10278 | /* 29187 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10279 | /* 29191 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10280 | /* 29196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32), |
| 10281 | /* 29199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10282 | /* 29201 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10283 | /* 29203 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10284 | /* 29205 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10285 | /* 29208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10286 | /* 29214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10287 | /* 29220 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10288 | /* 29223 */ GIR_RootConstrainSelectedInstOperands, |
| 10289 | /* 29224 */ // GIR_Coverage, 4013, |
| 10290 | /* 29224 */ GIR_EraseRootFromParent_Done, |
| 10291 | /* 29225 */ // Label 682: @29225 |
| 10292 | /* 29225 */ GIM_Reject, |
| 10293 | /* 29226 */ // Label 679: @29226 |
| 10294 | /* 29226 */ GIM_Reject, |
| 10295 | /* 29227 */ // Label 11: @29227 |
| 10296 | /* 29227 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 686*/ GIMT_Encode4(29453), |
| 10297 | /* 29238 */ /*GILLT_v16s8*//*Label 683*/ GIMT_Encode4(29258), GIMT_Encode4(0), |
| 10298 | /* 29246 */ /*GILLT_v8s16*//*Label 684*/ GIMT_Encode4(29323), GIMT_Encode4(0), |
| 10299 | /* 29254 */ /*GILLT_v4s32*//*Label 685*/ GIMT_Encode4(29388), |
| 10300 | /* 29258 */ // Label 683: @29258 |
| 10301 | /* 29258 */ GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(29322), // Rule ID 3981 // |
| 10302 | /* 29263 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10303 | /* 29266 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10304 | /* 29269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10305 | /* 29273 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10306 | /* 29277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10307 | /* 29281 */ // (avgceilu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10308 | /* 29281 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10309 | /* 29284 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10310 | /* 29288 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10311 | /* 29293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8), |
| 10312 | /* 29296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10313 | /* 29298 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10314 | /* 29300 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10315 | /* 29302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10316 | /* 29305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10317 | /* 29311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10318 | /* 29317 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10319 | /* 29320 */ GIR_RootConstrainSelectedInstOperands, |
| 10320 | /* 29321 */ // GIR_Coverage, 3981, |
| 10321 | /* 29321 */ GIR_EraseRootFromParent_Done, |
| 10322 | /* 29322 */ // Label 687: @29322 |
| 10323 | /* 29322 */ GIM_Reject, |
| 10324 | /* 29323 */ // Label 684: @29323 |
| 10325 | /* 29323 */ GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(29387), // Rule ID 3985 // |
| 10326 | /* 29328 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10327 | /* 29331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10328 | /* 29334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10329 | /* 29338 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10330 | /* 29342 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10331 | /* 29346 */ // (avgceilu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10332 | /* 29346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10333 | /* 29349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10334 | /* 29353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10335 | /* 29358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16), |
| 10336 | /* 29361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10337 | /* 29363 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10338 | /* 29365 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10339 | /* 29367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10340 | /* 29370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10341 | /* 29376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10342 | /* 29382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10343 | /* 29385 */ GIR_RootConstrainSelectedInstOperands, |
| 10344 | /* 29386 */ // GIR_Coverage, 3985, |
| 10345 | /* 29386 */ GIR_EraseRootFromParent_Done, |
| 10346 | /* 29387 */ // Label 688: @29387 |
| 10347 | /* 29387 */ GIM_Reject, |
| 10348 | /* 29388 */ // Label 685: @29388 |
| 10349 | /* 29388 */ GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(29452), // Rule ID 3989 // |
| 10350 | /* 29393 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10351 | /* 29396 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10352 | /* 29399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10353 | /* 29403 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10354 | /* 29407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10355 | /* 29411 */ // (avgceilu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10356 | /* 29411 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10357 | /* 29414 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10358 | /* 29418 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10359 | /* 29423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32), |
| 10360 | /* 29426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10361 | /* 29428 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10362 | /* 29430 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10363 | /* 29432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10364 | /* 29435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10365 | /* 29441 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10366 | /* 29447 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10367 | /* 29450 */ GIR_RootConstrainSelectedInstOperands, |
| 10368 | /* 29451 */ // GIR_Coverage, 3989, |
| 10369 | /* 29451 */ GIR_EraseRootFromParent_Done, |
| 10370 | /* 29452 */ // Label 689: @29452 |
| 10371 | /* 29452 */ GIM_Reject, |
| 10372 | /* 29453 */ // Label 686: @29453 |
| 10373 | /* 29453 */ GIM_Reject, |
| 10374 | /* 29454 */ // Label 12: @29454 |
| 10375 | /* 29454 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 693*/ GIMT_Encode4(29680), |
| 10376 | /* 29465 */ /*GILLT_v16s8*//*Label 690*/ GIMT_Encode4(29485), GIMT_Encode4(0), |
| 10377 | /* 29473 */ /*GILLT_v8s16*//*Label 691*/ GIMT_Encode4(29550), GIMT_Encode4(0), |
| 10378 | /* 29481 */ /*GILLT_v4s32*//*Label 692*/ GIMT_Encode4(29615), |
| 10379 | /* 29485 */ // Label 690: @29485 |
| 10380 | /* 29485 */ GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(29549), // Rule ID 3994 // |
| 10381 | /* 29490 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10382 | /* 29493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10383 | /* 29496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10384 | /* 29500 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10385 | /* 29504 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10386 | /* 29508 */ // (avgfloors:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10387 | /* 29508 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10388 | /* 29511 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10389 | /* 29515 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10390 | /* 29520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8), |
| 10391 | /* 29523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10392 | /* 29525 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10393 | /* 29527 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10394 | /* 29529 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10395 | /* 29532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10396 | /* 29538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10397 | /* 29544 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10398 | /* 29547 */ GIR_RootConstrainSelectedInstOperands, |
| 10399 | /* 29548 */ // GIR_Coverage, 3994, |
| 10400 | /* 29548 */ GIR_EraseRootFromParent_Done, |
| 10401 | /* 29549 */ // Label 694: @29549 |
| 10402 | /* 29549 */ GIM_Reject, |
| 10403 | /* 29550 */ // Label 691: @29550 |
| 10404 | /* 29550 */ GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(29614), // Rule ID 3997 // |
| 10405 | /* 29555 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10406 | /* 29558 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10407 | /* 29561 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10408 | /* 29565 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10409 | /* 29569 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10410 | /* 29573 */ // (avgfloors:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10411 | /* 29573 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10412 | /* 29576 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10413 | /* 29580 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10414 | /* 29585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16), |
| 10415 | /* 29588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10416 | /* 29590 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10417 | /* 29592 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10418 | /* 29594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10419 | /* 29597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10420 | /* 29603 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10421 | /* 29609 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10422 | /* 29612 */ GIR_RootConstrainSelectedInstOperands, |
| 10423 | /* 29613 */ // GIR_Coverage, 3997, |
| 10424 | /* 29613 */ GIR_EraseRootFromParent_Done, |
| 10425 | /* 29614 */ // Label 695: @29614 |
| 10426 | /* 29614 */ GIM_Reject, |
| 10427 | /* 29615 */ // Label 692: @29615 |
| 10428 | /* 29615 */ GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(29679), // Rule ID 4001 // |
| 10429 | /* 29620 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10430 | /* 29623 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10431 | /* 29626 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10432 | /* 29630 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10433 | /* 29634 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10434 | /* 29638 */ // (avgfloors:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10435 | /* 29638 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10436 | /* 29641 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10437 | /* 29645 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10438 | /* 29650 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32), |
| 10439 | /* 29653 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10440 | /* 29655 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10441 | /* 29657 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10442 | /* 29659 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10443 | /* 29662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10444 | /* 29668 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10445 | /* 29674 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10446 | /* 29677 */ GIR_RootConstrainSelectedInstOperands, |
| 10447 | /* 29678 */ // GIR_Coverage, 4001, |
| 10448 | /* 29678 */ GIR_EraseRootFromParent_Done, |
| 10449 | /* 29679 */ // Label 696: @29679 |
| 10450 | /* 29679 */ GIM_Reject, |
| 10451 | /* 29680 */ // Label 693: @29680 |
| 10452 | /* 29680 */ GIM_Reject, |
| 10453 | /* 29681 */ // Label 13: @29681 |
| 10454 | /* 29681 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 700*/ GIMT_Encode4(29907), |
| 10455 | /* 29692 */ /*GILLT_v16s8*//*Label 697*/ GIMT_Encode4(29712), GIMT_Encode4(0), |
| 10456 | /* 29700 */ /*GILLT_v8s16*//*Label 698*/ GIMT_Encode4(29777), GIMT_Encode4(0), |
| 10457 | /* 29708 */ /*GILLT_v4s32*//*Label 699*/ GIMT_Encode4(29842), |
| 10458 | /* 29712 */ // Label 697: @29712 |
| 10459 | /* 29712 */ GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(29776), // Rule ID 3970 // |
| 10460 | /* 29717 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10461 | /* 29720 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10462 | /* 29723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10463 | /* 29727 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10464 | /* 29731 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10465 | /* 29735 */ // (avgceils:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10466 | /* 29735 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10467 | /* 29738 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10468 | /* 29742 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10469 | /* 29747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8), |
| 10470 | /* 29750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10471 | /* 29752 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10472 | /* 29754 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10473 | /* 29756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10474 | /* 29759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10475 | /* 29765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10476 | /* 29771 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10477 | /* 29774 */ GIR_RootConstrainSelectedInstOperands, |
| 10478 | /* 29775 */ // GIR_Coverage, 3970, |
| 10479 | /* 29775 */ GIR_EraseRootFromParent_Done, |
| 10480 | /* 29776 */ // Label 701: @29776 |
| 10481 | /* 29776 */ GIM_Reject, |
| 10482 | /* 29777 */ // Label 698: @29777 |
| 10483 | /* 29777 */ GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(29841), // Rule ID 3973 // |
| 10484 | /* 29782 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10485 | /* 29785 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10486 | /* 29788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10487 | /* 29792 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10488 | /* 29796 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10489 | /* 29800 */ // (avgceils:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10490 | /* 29800 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10491 | /* 29803 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10492 | /* 29807 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10493 | /* 29812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16), |
| 10494 | /* 29815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10495 | /* 29817 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10496 | /* 29819 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10497 | /* 29821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10498 | /* 29824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10499 | /* 29830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10500 | /* 29836 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10501 | /* 29839 */ GIR_RootConstrainSelectedInstOperands, |
| 10502 | /* 29840 */ // GIR_Coverage, 3973, |
| 10503 | /* 29840 */ GIR_EraseRootFromParent_Done, |
| 10504 | /* 29841 */ // Label 702: @29841 |
| 10505 | /* 29841 */ GIM_Reject, |
| 10506 | /* 29842 */ // Label 699: @29842 |
| 10507 | /* 29842 */ GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(29906), // Rule ID 3977 // |
| 10508 | /* 29847 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10509 | /* 29850 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10510 | /* 29853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10511 | /* 29857 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10512 | /* 29861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10513 | /* 29865 */ // (avgceils:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10514 | /* 29865 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10515 | /* 29868 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10516 | /* 29872 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10517 | /* 29877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32), |
| 10518 | /* 29880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10519 | /* 29882 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10520 | /* 29884 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10521 | /* 29886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10522 | /* 29889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10523 | /* 29895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10524 | /* 29901 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10525 | /* 29904 */ GIR_RootConstrainSelectedInstOperands, |
| 10526 | /* 29905 */ // GIR_Coverage, 3977, |
| 10527 | /* 29905 */ GIR_EraseRootFromParent_Done, |
| 10528 | /* 29906 */ // Label 703: @29906 |
| 10529 | /* 29906 */ GIM_Reject, |
| 10530 | /* 29907 */ // Label 700: @29907 |
| 10531 | /* 29907 */ GIM_Reject, |
| 10532 | /* 29908 */ // Label 14: @29908 |
| 10533 | /* 29908 */ GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(30574), |
| 10534 | /* 29913 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 10535 | /* 29916 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 709*/ GIMT_Encode4(30573), |
| 10536 | /* 29927 */ /*GILLT_v16s8*//*Label 705*/ GIMT_Encode4(29951), GIMT_Encode4(0), |
| 10537 | /* 29935 */ /*GILLT_v8s16*//*Label 706*/ GIMT_Encode4(30057), GIMT_Encode4(0), |
| 10538 | /* 29943 */ /*GILLT_v4s32*//*Label 707*/ GIMT_Encode4(30268), |
| 10539 | /* 29947 */ /*GILLT_v2s64*//*Label 708*/ GIMT_Encode4(30467), |
| 10540 | /* 29951 */ // Label 705: @29951 |
| 10541 | /* 29951 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 710*/ GIMT_Encode4(30056), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3416 // |
| 10542 | /* 29958 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 10543 | /* 29961 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 10544 | /* 29964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID), |
| 10545 | /* 29968 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10546 | /* 29972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10547 | /* 29976 */ // (concat_vectors:{ *:[v16i8] } DPR:{ *:[v8i8] }:$Dn, DPR:{ *:[v8i8] }:$Dm) => (INSERT_SUBREG:{ *:[v16i8] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), DPR:{ *:[v8i8] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v8i8] }:$Dm, dsub_1:{ *:[i32] }) |
| 10548 | /* 29976 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 10549 | /* 29979 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10550 | /* 29983 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10551 | /* 29988 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10552 | /* 29990 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 10553 | /* 29993 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10554 | /* 29997 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10555 | /* 30002 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10556 | /* 30005 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn |
| 10557 | /* 30009 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 10558 | /* 30012 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10559 | /* 30017 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10560 | /* 30022 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10561 | /* 30027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10562 | /* 30030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10563 | /* 30032 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10564 | /* 30035 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 10565 | /* 30037 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 10566 | /* 30040 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10567 | /* 30045 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10568 | /* 30050 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10569 | /* 30055 */ // GIR_Coverage, 3416, |
| 10570 | /* 30055 */ GIR_EraseRootFromParent_Done, |
| 10571 | /* 30056 */ // Label 710: @30056 |
| 10572 | /* 30056 */ GIM_Reject, |
| 10573 | /* 30057 */ // Label 706: @30057 |
| 10574 | /* 30057 */ GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(30267), |
| 10575 | /* 30062 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10576 | /* 30065 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 10577 | /* 30068 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 712*/ GIMT_Encode4(30167), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3415 // |
| 10578 | /* 30075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID), |
| 10579 | /* 30079 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10580 | /* 30083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10581 | /* 30087 */ // (concat_vectors:{ *:[v8i16] } DPR:{ *:[v4i16] }:$Dn, DPR:{ *:[v4i16] }:$Dm) => (INSERT_SUBREG:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), DPR:{ *:[v4i16] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v4i16] }:$Dm, dsub_1:{ *:[i32] }) |
| 10582 | /* 30087 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 10583 | /* 30090 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10584 | /* 30094 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10585 | /* 30099 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10586 | /* 30101 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 10587 | /* 30104 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10588 | /* 30108 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10589 | /* 30113 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10590 | /* 30116 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn |
| 10591 | /* 30120 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 10592 | /* 30123 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10593 | /* 30128 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10594 | /* 30133 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10595 | /* 30138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10596 | /* 30141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10597 | /* 30143 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10598 | /* 30146 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 10599 | /* 30148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 10600 | /* 30151 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10601 | /* 30156 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10602 | /* 30161 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10603 | /* 30166 */ // GIR_Coverage, 3415, |
| 10604 | /* 30166 */ GIR_EraseRootFromParent_Done, |
| 10605 | /* 30167 */ // Label 712: @30167 |
| 10606 | /* 30167 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 713*/ GIMT_Encode4(30266), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3418 // |
| 10607 | /* 30174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10608 | /* 30178 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10609 | /* 30182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10610 | /* 30186 */ // (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm) => (INSERT_SUBREG:{ *:[v8f16] } (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), DPR:{ *:[v4f16] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v4f16] }:$Dm, dsub_1:{ *:[i32] }) |
| 10611 | /* 30186 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 10612 | /* 30189 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10613 | /* 30193 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10614 | /* 30198 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10615 | /* 30200 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 10616 | /* 30203 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10617 | /* 30207 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10618 | /* 30212 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10619 | /* 30215 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn |
| 10620 | /* 30219 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 10621 | /* 30222 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10622 | /* 30227 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::QPRRegClassID), |
| 10623 | /* 30232 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10624 | /* 30237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10625 | /* 30240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10626 | /* 30242 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10627 | /* 30245 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 10628 | /* 30247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 10629 | /* 30250 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10630 | /* 30255 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::QPRRegClassID), |
| 10631 | /* 30260 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10632 | /* 30265 */ // GIR_Coverage, 3418, |
| 10633 | /* 30265 */ GIR_EraseRootFromParent_Done, |
| 10634 | /* 30266 */ // Label 713: @30266 |
| 10635 | /* 30266 */ GIM_Reject, |
| 10636 | /* 30267 */ // Label 711: @30267 |
| 10637 | /* 30267 */ GIM_Reject, |
| 10638 | /* 30268 */ // Label 707: @30268 |
| 10639 | /* 30268 */ GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(30466), |
| 10640 | /* 30273 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10641 | /* 30276 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10642 | /* 30279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID), |
| 10643 | /* 30283 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10644 | /* 30287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10645 | /* 30291 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 715*/ GIMT_Encode4(30378), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3414 // |
| 10646 | /* 30298 */ // (concat_vectors:{ *:[v4i32] } DPR:{ *:[v2i32] }:$Dn, DPR:{ *:[v2i32] }:$Dm) => (INSERT_SUBREG:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), DPR:{ *:[v2i32] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v2i32] }:$Dm, dsub_1:{ *:[i32] }) |
| 10647 | /* 30298 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10648 | /* 30301 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10649 | /* 30305 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10650 | /* 30310 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10651 | /* 30312 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10652 | /* 30315 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10653 | /* 30319 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10654 | /* 30324 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10655 | /* 30327 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn |
| 10656 | /* 30331 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 10657 | /* 30334 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10658 | /* 30339 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10659 | /* 30344 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10660 | /* 30349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10661 | /* 30352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10662 | /* 30354 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10663 | /* 30357 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 10664 | /* 30359 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 10665 | /* 30362 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10666 | /* 30367 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10667 | /* 30372 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10668 | /* 30377 */ // GIR_Coverage, 3414, |
| 10669 | /* 30377 */ GIR_EraseRootFromParent_Done, |
| 10670 | /* 30378 */ // Label 715: @30378 |
| 10671 | /* 30378 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 716*/ GIMT_Encode4(30465), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3417 // |
| 10672 | /* 30385 */ // (concat_vectors:{ *:[v4f32] } DPR:{ *:[v2f32] }:$Dn, DPR:{ *:[v2f32] }:$Dm) => (INSERT_SUBREG:{ *:[v4f32] } (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), DPR:{ *:[v2f32] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v2f32] }:$Dm, dsub_1:{ *:[i32] }) |
| 10673 | /* 30385 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10674 | /* 30388 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10675 | /* 30392 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10676 | /* 30397 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10677 | /* 30399 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10678 | /* 30402 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10679 | /* 30406 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10680 | /* 30411 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10681 | /* 30414 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn |
| 10682 | /* 30418 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 10683 | /* 30421 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10684 | /* 30426 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10685 | /* 30431 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10686 | /* 30436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10687 | /* 30439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10688 | /* 30441 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10689 | /* 30444 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 10690 | /* 30446 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 10691 | /* 30449 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10692 | /* 30454 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10693 | /* 30459 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10694 | /* 30464 */ // GIR_Coverage, 3417, |
| 10695 | /* 30464 */ GIR_EraseRootFromParent_Done, |
| 10696 | /* 30465 */ // Label 716: @30465 |
| 10697 | /* 30465 */ GIM_Reject, |
| 10698 | /* 30466 */ // Label 714: @30466 |
| 10699 | /* 30466 */ GIM_Reject, |
| 10700 | /* 30467 */ // Label 708: @30467 |
| 10701 | /* 30467 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 717*/ GIMT_Encode4(30572), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3413 // |
| 10702 | /* 30474 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10703 | /* 30477 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 10704 | /* 30480 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID), |
| 10705 | /* 30484 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10706 | /* 30488 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10707 | /* 30492 */ // (concat_vectors:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm) => (INSERT_SUBREG:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), DPR:{ *:[v1i64] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v1i64] }:$Dm, dsub_1:{ *:[i32] }) |
| 10708 | /* 30492 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64, |
| 10709 | /* 30495 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10710 | /* 30499 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10711 | /* 30504 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10712 | /* 30506 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64, |
| 10713 | /* 30509 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10714 | /* 30513 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10715 | /* 30518 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10716 | /* 30521 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn |
| 10717 | /* 30525 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 10718 | /* 30528 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10719 | /* 30533 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10720 | /* 30538 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10721 | /* 30543 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10722 | /* 30546 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10723 | /* 30548 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10724 | /* 30551 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 10725 | /* 30553 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 10726 | /* 30556 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10727 | /* 30561 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10728 | /* 30566 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10729 | /* 30571 */ // GIR_Coverage, 3413, |
| 10730 | /* 30571 */ GIR_EraseRootFromParent_Done, |
| 10731 | /* 30572 */ // Label 717: @30572 |
| 10732 | /* 30572 */ GIM_Reject, |
| 10733 | /* 30573 */ // Label 709: @30573 |
| 10734 | /* 30573 */ GIM_Reject, |
| 10735 | /* 30574 */ // Label 704: @30574 |
| 10736 | /* 30574 */ GIM_Reject, |
| 10737 | /* 30575 */ // Label 15: @30575 |
| 10738 | /* 30575 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 727*/ GIMT_Encode4(37761), |
| 10739 | /* 30586 */ /*GILLT_s32*//*Label 718*/ GIMT_Encode4(30638), |
| 10740 | /* 30590 */ /*GILLT_s64*//*Label 719*/ GIMT_Encode4(30781), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10741 | /* 30610 */ /*GILLT_v8s8*//*Label 720*/ GIMT_Encode4(31383), |
| 10742 | /* 30614 */ /*GILLT_v16s8*//*Label 721*/ GIMT_Encode4(31750), |
| 10743 | /* 30618 */ /*GILLT_v4s16*//*Label 722*/ GIMT_Encode4(32531), |
| 10744 | /* 30622 */ /*GILLT_v8s16*//*Label 723*/ GIMT_Encode4(33133), |
| 10745 | /* 30626 */ /*GILLT_v2s32*//*Label 724*/ GIMT_Encode4(34475), |
| 10746 | /* 30630 */ /*GILLT_v4s32*//*Label 725*/ GIMT_Encode4(35077), |
| 10747 | /* 30634 */ /*GILLT_v2s64*//*Label 726*/ GIMT_Encode4(36419), |
| 10748 | /* 30638 */ // Label 718: @30638 |
| 10749 | /* 30638 */ GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(30780), |
| 10750 | /* 30643 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 10751 | /* 30646 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 729*/ GIMT_Encode4(30679), GIMT_Encode2(GIFBS_HasFPRegs), // Rule ID 740 // |
| 10752 | /* 30653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 10753 | /* 30657 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 10754 | /* 30661 */ // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn) => (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn) |
| 10755 | /* 30661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVRS), |
| 10756 | /* 30664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 10757 | /* 30666 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 10758 | /* 30668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10759 | /* 30671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10760 | /* 30677 */ GIR_RootConstrainSelectedInstOperands, |
| 10761 | /* 30678 */ // GIR_Coverage, 740, |
| 10762 | /* 30678 */ GIR_EraseRootFromParent_Done, |
| 10763 | /* 30679 */ // Label 729: @30679 |
| 10764 | /* 30679 */ GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(30779), |
| 10765 | /* 30684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 10766 | /* 30688 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 10767 | /* 30692 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 731*/ GIMT_Encode4(30717), GIMT_Encode2(GIFBS_HasFPRegs_UseVMOVSR), // Rule ID 741 // |
| 10768 | /* 30699 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt) => (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt) |
| 10769 | /* 30699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVSR), |
| 10770 | /* 30702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sn] |
| 10771 | /* 30704 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt |
| 10772 | /* 30706 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10773 | /* 30709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10774 | /* 30715 */ GIR_RootConstrainSelectedInstOperands, |
| 10775 | /* 30716 */ // GIR_Coverage, 741, |
| 10776 | /* 30716 */ GIR_EraseRootFromParent_Done, |
| 10777 | /* 30717 */ // Label 731: @30717 |
| 10778 | /* 30717 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 732*/ GIMT_Encode4(30778), GIMT_Encode2(GIFBS_DontUseVMOVSR_HasNEON), // Rule ID 3107 // |
| 10779 | /* 30724 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VMOVDRR:{ *:[f64] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$a), ssub_0:{ *:[i32] }) |
| 10780 | /* 30724 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 10781 | /* 30727 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VMOVDRR), |
| 10782 | /* 30731 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10783 | /* 30736 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 10784 | /* 30740 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 10785 | /* 30744 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 10786 | /* 30747 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10787 | /* 30753 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10788 | /* 30755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10789 | /* 30758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10790 | /* 30760 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 10791 | /* 30767 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 10792 | /* 30772 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 10793 | /* 30777 */ // GIR_Coverage, 3107, |
| 10794 | /* 30777 */ GIR_EraseRootFromParent_Done, |
| 10795 | /* 30778 */ // Label 732: @30778 |
| 10796 | /* 30778 */ GIM_Reject, |
| 10797 | /* 30779 */ // Label 730: @30779 |
| 10798 | /* 30779 */ GIM_Reject, |
| 10799 | /* 30780 */ // Label 728: @30780 |
| 10800 | /* 30780 */ GIM_Reject, |
| 10801 | /* 30781 */ // Label 719: @30781 |
| 10802 | /* 30781 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 737*/ GIMT_Encode4(31382), |
| 10803 | /* 30792 */ /*GILLT_s64*//*Label 733*/ GIMT_Encode4(30832), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10804 | /* 30812 */ /*GILLT_v8s8*//*Label 734*/ GIMT_Encode4(30887), GIMT_Encode4(0), |
| 10805 | /* 30820 */ /*GILLT_v4s16*//*Label 735*/ GIMT_Encode4(30992), GIMT_Encode4(0), |
| 10806 | /* 30828 */ /*GILLT_v2s32*//*Label 736*/ GIMT_Encode4(31187), |
| 10807 | /* 30832 */ // Label 733: @30832 |
| 10808 | /* 30832 */ GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(30886), |
| 10809 | /* 30837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10810 | /* 30841 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10811 | /* 30845 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 739*/ GIMT_Encode4(30865), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3109 // |
| 10812 | /* 30852 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[f64] }:$src |
| 10813 | /* 30852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10814 | /* 30855 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10815 | /* 30857 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10816 | /* 30859 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10817 | /* 30864 */ // GIR_Coverage, 3109, |
| 10818 | /* 30864 */ GIR_EraseRootFromParent_Done, |
| 10819 | /* 30865 */ // Label 739: @30865 |
| 10820 | /* 30865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 740*/ GIMT_Encode4(30885), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3110 // |
| 10821 | /* 30872 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v1i64] }:$src |
| 10822 | /* 30872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10823 | /* 30875 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10824 | /* 30877 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10825 | /* 30879 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10826 | /* 30884 */ // GIR_Coverage, 3110, |
| 10827 | /* 30884 */ GIR_EraseRootFromParent_Done, |
| 10828 | /* 30885 */ // Label 740: @30885 |
| 10829 | /* 30885 */ GIM_Reject, |
| 10830 | /* 30886 */ // Label 738: @30886 |
| 10831 | /* 30886 */ GIM_Reject, |
| 10832 | /* 30887 */ // Label 734: @30887 |
| 10833 | /* 30887 */ GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(30991), |
| 10834 | /* 30892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10835 | /* 30896 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10836 | /* 30900 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 742*/ GIMT_Encode4(30920), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3125 // |
| 10837 | /* 30907 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[f64] }:$src |
| 10838 | /* 30907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10839 | /* 30910 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10840 | /* 30912 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10841 | /* 30914 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10842 | /* 30919 */ // GIR_Coverage, 3125, |
| 10843 | /* 30919 */ GIR_EraseRootFromParent_Done, |
| 10844 | /* 30920 */ // Label 742: @30920 |
| 10845 | /* 30920 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 743*/ GIMT_Encode4(30940), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3130 // |
| 10846 | /* 30927 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v1i64] }:$src |
| 10847 | /* 30927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10848 | /* 30930 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10849 | /* 30932 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10850 | /* 30934 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10851 | /* 30939 */ // GIR_Coverage, 3130, |
| 10852 | /* 30939 */ GIR_EraseRootFromParent_Done, |
| 10853 | /* 30940 */ // Label 743: @30940 |
| 10854 | /* 30940 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 744*/ GIMT_Encode4(30965), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3197 // |
| 10855 | /* 30947 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src) |
| 10856 | /* 30947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 10857 | /* 30950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10858 | /* 30952 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10859 | /* 30954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10860 | /* 30957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10861 | /* 30963 */ GIR_RootConstrainSelectedInstOperands, |
| 10862 | /* 30964 */ // GIR_Coverage, 3197, |
| 10863 | /* 30964 */ GIR_EraseRootFromParent_Done, |
| 10864 | /* 30965 */ // Label 744: @30965 |
| 10865 | /* 30965 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 745*/ GIMT_Encode4(30990), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3202 // |
| 10866 | /* 30972 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) |
| 10867 | /* 30972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 10868 | /* 30975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10869 | /* 30977 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10870 | /* 30979 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10871 | /* 30982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10872 | /* 30988 */ GIR_RootConstrainSelectedInstOperands, |
| 10873 | /* 30989 */ // GIR_Coverage, 3202, |
| 10874 | /* 30989 */ GIR_EraseRootFromParent_Done, |
| 10875 | /* 30990 */ // Label 745: @30990 |
| 10876 | /* 30990 */ GIM_Reject, |
| 10877 | /* 30991 */ // Label 741: @30991 |
| 10878 | /* 30991 */ GIM_Reject, |
| 10879 | /* 30992 */ // Label 735: @30992 |
| 10880 | /* 30992 */ GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(31186), |
| 10881 | /* 30997 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10882 | /* 31001 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10883 | /* 31005 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 747*/ GIMT_Encode4(31025), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3123 // |
| 10884 | /* 31012 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[f64] }:$src |
| 10885 | /* 31012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10886 | /* 31015 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10887 | /* 31017 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10888 | /* 31019 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10889 | /* 31024 */ // GIR_Coverage, 3123, |
| 10890 | /* 31024 */ GIR_EraseRootFromParent_Done, |
| 10891 | /* 31025 */ // Label 747: @31025 |
| 10892 | /* 31025 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 748*/ GIMT_Encode4(31045), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3124 // |
| 10893 | /* 31032 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[f64] }:$src |
| 10894 | /* 31032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10895 | /* 31035 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10896 | /* 31037 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10897 | /* 31039 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10898 | /* 31044 */ // GIR_Coverage, 3124, |
| 10899 | /* 31044 */ GIR_EraseRootFromParent_Done, |
| 10900 | /* 31045 */ // Label 748: @31045 |
| 10901 | /* 31045 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 749*/ GIMT_Encode4(31065), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3128 // |
| 10902 | /* 31052 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v1i64] }:$src |
| 10903 | /* 31052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10904 | /* 31055 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10905 | /* 31057 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10906 | /* 31059 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10907 | /* 31064 */ // GIR_Coverage, 3128, |
| 10908 | /* 31064 */ GIR_EraseRootFromParent_Done, |
| 10909 | /* 31065 */ // Label 749: @31065 |
| 10910 | /* 31065 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 750*/ GIMT_Encode4(31085), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3129 // |
| 10911 | /* 31072 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v1i64] }:$src |
| 10912 | /* 31072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10913 | /* 31075 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10914 | /* 31077 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10915 | /* 31079 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10916 | /* 31084 */ // GIR_Coverage, 3129, |
| 10917 | /* 31084 */ GIR_EraseRootFromParent_Done, |
| 10918 | /* 31085 */ // Label 750: @31085 |
| 10919 | /* 31085 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 751*/ GIMT_Encode4(31110), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3195 // |
| 10920 | /* 31092 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src) |
| 10921 | /* 31092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 10922 | /* 31095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10923 | /* 31097 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10924 | /* 31099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10925 | /* 31102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10926 | /* 31108 */ GIR_RootConstrainSelectedInstOperands, |
| 10927 | /* 31109 */ // GIR_Coverage, 3195, |
| 10928 | /* 31109 */ GIR_EraseRootFromParent_Done, |
| 10929 | /* 31110 */ // Label 751: @31110 |
| 10930 | /* 31110 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 752*/ GIMT_Encode4(31135), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3196 // |
| 10931 | /* 31117 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src) |
| 10932 | /* 31117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 10933 | /* 31120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10934 | /* 31122 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10935 | /* 31124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10936 | /* 31127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10937 | /* 31133 */ GIR_RootConstrainSelectedInstOperands, |
| 10938 | /* 31134 */ // GIR_Coverage, 3196, |
| 10939 | /* 31134 */ GIR_EraseRootFromParent_Done, |
| 10940 | /* 31135 */ // Label 752: @31135 |
| 10941 | /* 31135 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 753*/ GIMT_Encode4(31160), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3200 // |
| 10942 | /* 31142 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) |
| 10943 | /* 31142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 10944 | /* 31145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10945 | /* 31147 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10946 | /* 31149 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10947 | /* 31152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10948 | /* 31158 */ GIR_RootConstrainSelectedInstOperands, |
| 10949 | /* 31159 */ // GIR_Coverage, 3200, |
| 10950 | /* 31159 */ GIR_EraseRootFromParent_Done, |
| 10951 | /* 31160 */ // Label 753: @31160 |
| 10952 | /* 31160 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 754*/ GIMT_Encode4(31185), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3201 // |
| 10953 | /* 31167 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) |
| 10954 | /* 31167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 10955 | /* 31170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10956 | /* 31172 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10957 | /* 31174 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10958 | /* 31177 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10959 | /* 31183 */ GIR_RootConstrainSelectedInstOperands, |
| 10960 | /* 31184 */ // GIR_Coverage, 3201, |
| 10961 | /* 31184 */ GIR_EraseRootFromParent_Done, |
| 10962 | /* 31185 */ // Label 754: @31185 |
| 10963 | /* 31185 */ GIM_Reject, |
| 10964 | /* 31186 */ // Label 746: @31186 |
| 10965 | /* 31186 */ GIM_Reject, |
| 10966 | /* 31187 */ // Label 736: @31187 |
| 10967 | /* 31187 */ GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(31381), |
| 10968 | /* 31192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10969 | /* 31196 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10970 | /* 31200 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 756*/ GIMT_Encode4(31220), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3121 // |
| 10971 | /* 31207 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[f64] }:$src |
| 10972 | /* 31207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10973 | /* 31210 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10974 | /* 31212 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10975 | /* 31214 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10976 | /* 31219 */ // GIR_Coverage, 3121, |
| 10977 | /* 31219 */ GIR_EraseRootFromParent_Done, |
| 10978 | /* 31220 */ // Label 756: @31220 |
| 10979 | /* 31220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 757*/ GIMT_Encode4(31240), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3122 // |
| 10980 | /* 31227 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[f64] }:$src |
| 10981 | /* 31227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10982 | /* 31230 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10983 | /* 31232 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10984 | /* 31234 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10985 | /* 31239 */ // GIR_Coverage, 3122, |
| 10986 | /* 31239 */ GIR_EraseRootFromParent_Done, |
| 10987 | /* 31240 */ // Label 757: @31240 |
| 10988 | /* 31240 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 758*/ GIMT_Encode4(31260), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3126 // |
| 10989 | /* 31247 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v1i64] }:$src |
| 10990 | /* 31247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10991 | /* 31250 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10992 | /* 31252 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10993 | /* 31254 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10994 | /* 31259 */ // GIR_Coverage, 3126, |
| 10995 | /* 31259 */ GIR_EraseRootFromParent_Done, |
| 10996 | /* 31260 */ // Label 758: @31260 |
| 10997 | /* 31260 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 759*/ GIMT_Encode4(31280), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3127 // |
| 10998 | /* 31267 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v1i64] }:$src |
| 10999 | /* 31267 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11000 | /* 31270 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11001 | /* 31272 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11002 | /* 31274 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11003 | /* 31279 */ // GIR_Coverage, 3127, |
| 11004 | /* 31279 */ GIR_EraseRootFromParent_Done, |
| 11005 | /* 31280 */ // Label 759: @31280 |
| 11006 | /* 31280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 760*/ GIMT_Encode4(31305), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3193 // |
| 11007 | /* 31287 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src) |
| 11008 | /* 31287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 11009 | /* 31290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11010 | /* 31292 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11011 | /* 31294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11012 | /* 31297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11013 | /* 31303 */ GIR_RootConstrainSelectedInstOperands, |
| 11014 | /* 31304 */ // GIR_Coverage, 3193, |
| 11015 | /* 31304 */ GIR_EraseRootFromParent_Done, |
| 11016 | /* 31305 */ // Label 760: @31305 |
| 11017 | /* 31305 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 761*/ GIMT_Encode4(31330), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3194 // |
| 11018 | /* 31312 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src) |
| 11019 | /* 31312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 11020 | /* 31315 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11021 | /* 31317 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11022 | /* 31319 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11023 | /* 31322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11024 | /* 31328 */ GIR_RootConstrainSelectedInstOperands, |
| 11025 | /* 31329 */ // GIR_Coverage, 3194, |
| 11026 | /* 31329 */ GIR_EraseRootFromParent_Done, |
| 11027 | /* 31330 */ // Label 761: @31330 |
| 11028 | /* 31330 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 762*/ GIMT_Encode4(31355), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3198 // |
| 11029 | /* 31337 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) |
| 11030 | /* 31337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 11031 | /* 31340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11032 | /* 31342 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11033 | /* 31344 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11034 | /* 31347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11035 | /* 31353 */ GIR_RootConstrainSelectedInstOperands, |
| 11036 | /* 31354 */ // GIR_Coverage, 3198, |
| 11037 | /* 31354 */ GIR_EraseRootFromParent_Done, |
| 11038 | /* 31355 */ // Label 762: @31355 |
| 11039 | /* 31355 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 763*/ GIMT_Encode4(31380), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3199 // |
| 11040 | /* 31362 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) |
| 11041 | /* 31362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 11042 | /* 31365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11043 | /* 31367 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11044 | /* 31369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11045 | /* 31372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11046 | /* 31378 */ GIR_RootConstrainSelectedInstOperands, |
| 11047 | /* 31379 */ // GIR_Coverage, 3199, |
| 11048 | /* 31379 */ GIR_EraseRootFromParent_Done, |
| 11049 | /* 31380 */ // Label 763: @31380 |
| 11050 | /* 31380 */ GIM_Reject, |
| 11051 | /* 31381 */ // Label 755: @31381 |
| 11052 | /* 31381 */ GIM_Reject, |
| 11053 | /* 31382 */ // Label 737: @31382 |
| 11054 | /* 31382 */ GIM_Reject, |
| 11055 | /* 31383 */ // Label 720: @31383 |
| 11056 | /* 31383 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 767*/ GIMT_Encode4(31749), |
| 11057 | /* 31394 */ /*GILLT_s64*//*Label 764*/ GIMT_Encode4(31434), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 11058 | /* 31422 */ /*GILLT_v4s16*//*Label 765*/ GIMT_Encode4(31539), GIMT_Encode4(0), |
| 11059 | /* 31430 */ /*GILLT_v2s32*//*Label 766*/ GIMT_Encode4(31644), |
| 11060 | /* 31434 */ // Label 764: @31434 |
| 11061 | /* 31434 */ GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(31538), |
| 11062 | /* 31439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11063 | /* 31443 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11064 | /* 31447 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 769*/ GIMT_Encode4(31467), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3151 // |
| 11065 | /* 31454 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11066 | /* 31454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11067 | /* 31457 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11068 | /* 31459 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11069 | /* 31461 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11070 | /* 31466 */ // GIR_Coverage, 3151, |
| 11071 | /* 31466 */ GIR_EraseRootFromParent_Done, |
| 11072 | /* 31467 */ // Label 769: @31467 |
| 11073 | /* 31467 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 770*/ GIMT_Encode4(31487), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3152 // |
| 11074 | /* 31474 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11075 | /* 31474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11076 | /* 31477 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11077 | /* 31479 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11078 | /* 31481 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11079 | /* 31486 */ // GIR_Coverage, 3152, |
| 11080 | /* 31486 */ GIR_EraseRootFromParent_Done, |
| 11081 | /* 31487 */ // Label 770: @31487 |
| 11082 | /* 31487 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 771*/ GIMT_Encode4(31512), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3223 // |
| 11083 | /* 31494 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src) |
| 11084 | /* 31494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 11085 | /* 31497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11086 | /* 31499 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11087 | /* 31501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11088 | /* 31504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11089 | /* 31510 */ GIR_RootConstrainSelectedInstOperands, |
| 11090 | /* 31511 */ // GIR_Coverage, 3223, |
| 11091 | /* 31511 */ GIR_EraseRootFromParent_Done, |
| 11092 | /* 31512 */ // Label 771: @31512 |
| 11093 | /* 31512 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 772*/ GIMT_Encode4(31537), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3224 // |
| 11094 | /* 31519 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) |
| 11095 | /* 31519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 11096 | /* 31522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11097 | /* 31524 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11098 | /* 31526 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11099 | /* 31529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11100 | /* 31535 */ GIR_RootConstrainSelectedInstOperands, |
| 11101 | /* 31536 */ // GIR_Coverage, 3224, |
| 11102 | /* 31536 */ GIR_EraseRootFromParent_Done, |
| 11103 | /* 31537 */ // Label 772: @31537 |
| 11104 | /* 31537 */ GIM_Reject, |
| 11105 | /* 31538 */ // Label 768: @31538 |
| 11106 | /* 31538 */ GIM_Reject, |
| 11107 | /* 31539 */ // Label 765: @31539 |
| 11108 | /* 31539 */ GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(31643), |
| 11109 | /* 31544 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11110 | /* 31548 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11111 | /* 31552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 774*/ GIMT_Encode4(31572), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3155 // |
| 11112 | /* 31559 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11113 | /* 31559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11114 | /* 31562 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11115 | /* 31564 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11116 | /* 31566 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11117 | /* 31571 */ // GIR_Coverage, 3155, |
| 11118 | /* 31571 */ GIR_EraseRootFromParent_Done, |
| 11119 | /* 31572 */ // Label 774: @31572 |
| 11120 | /* 31572 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 775*/ GIMT_Encode4(31592), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3156 // |
| 11121 | /* 31579 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11122 | /* 31579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11123 | /* 31582 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11124 | /* 31584 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11125 | /* 31586 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11126 | /* 31591 */ // GIR_Coverage, 3156, |
| 11127 | /* 31591 */ GIR_EraseRootFromParent_Done, |
| 11128 | /* 31592 */ // Label 775: @31592 |
| 11129 | /* 31592 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 776*/ GIMT_Encode4(31617), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3227 // |
| 11130 | /* 31599 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) |
| 11131 | /* 31599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 11132 | /* 31602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11133 | /* 31604 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11134 | /* 31606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11135 | /* 31609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11136 | /* 31615 */ GIR_RootConstrainSelectedInstOperands, |
| 11137 | /* 31616 */ // GIR_Coverage, 3227, |
| 11138 | /* 31616 */ GIR_EraseRootFromParent_Done, |
| 11139 | /* 31617 */ // Label 776: @31617 |
| 11140 | /* 31617 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 777*/ GIMT_Encode4(31642), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3228 // |
| 11141 | /* 31624 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) |
| 11142 | /* 31624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 11143 | /* 31627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11144 | /* 31629 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11145 | /* 31631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11146 | /* 31634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11147 | /* 31640 */ GIR_RootConstrainSelectedInstOperands, |
| 11148 | /* 31641 */ // GIR_Coverage, 3228, |
| 11149 | /* 31641 */ GIR_EraseRootFromParent_Done, |
| 11150 | /* 31642 */ // Label 777: @31642 |
| 11151 | /* 31642 */ GIM_Reject, |
| 11152 | /* 31643 */ // Label 773: @31643 |
| 11153 | /* 31643 */ GIM_Reject, |
| 11154 | /* 31644 */ // Label 766: @31644 |
| 11155 | /* 31644 */ GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(31748), |
| 11156 | /* 31649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11157 | /* 31653 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11158 | /* 31657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 779*/ GIMT_Encode4(31677), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3153 // |
| 11159 | /* 31664 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11160 | /* 31664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11161 | /* 31667 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11162 | /* 31669 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11163 | /* 31671 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11164 | /* 31676 */ // GIR_Coverage, 3153, |
| 11165 | /* 31676 */ GIR_EraseRootFromParent_Done, |
| 11166 | /* 31677 */ // Label 779: @31677 |
| 11167 | /* 31677 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 780*/ GIMT_Encode4(31697), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3154 // |
| 11168 | /* 31684 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11169 | /* 31684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11170 | /* 31687 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11171 | /* 31689 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11172 | /* 31691 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11173 | /* 31696 */ // GIR_Coverage, 3154, |
| 11174 | /* 31696 */ GIR_EraseRootFromParent_Done, |
| 11175 | /* 31697 */ // Label 780: @31697 |
| 11176 | /* 31697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 781*/ GIMT_Encode4(31722), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3225 // |
| 11177 | /* 31704 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) |
| 11178 | /* 31704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 11179 | /* 31707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11180 | /* 31709 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11181 | /* 31711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11182 | /* 31714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11183 | /* 31720 */ GIR_RootConstrainSelectedInstOperands, |
| 11184 | /* 31721 */ // GIR_Coverage, 3225, |
| 11185 | /* 31721 */ GIR_EraseRootFromParent_Done, |
| 11186 | /* 31722 */ // Label 781: @31722 |
| 11187 | /* 31722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 782*/ GIMT_Encode4(31747), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3226 // |
| 11188 | /* 31729 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) |
| 11189 | /* 31729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 11190 | /* 31732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11191 | /* 31734 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11192 | /* 31736 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11193 | /* 31739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11194 | /* 31745 */ GIR_RootConstrainSelectedInstOperands, |
| 11195 | /* 31746 */ // GIR_Coverage, 3226, |
| 11196 | /* 31746 */ GIR_EraseRootFromParent_Done, |
| 11197 | /* 31747 */ // Label 782: @31747 |
| 11198 | /* 31747 */ GIM_Reject, |
| 11199 | /* 31748 */ // Label 778: @31748 |
| 11200 | /* 31748 */ GIM_Reject, |
| 11201 | /* 31749 */ // Label 767: @31749 |
| 11202 | /* 31749 */ GIM_Reject, |
| 11203 | /* 31750 */ // Label 721: @31750 |
| 11204 | /* 31750 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 786*/ GIMT_Encode4(32530), |
| 11205 | /* 31761 */ /*GILLT_v8s16*//*Label 783*/ GIMT_Encode4(31777), GIMT_Encode4(0), |
| 11206 | /* 31769 */ /*GILLT_v4s32*//*Label 784*/ GIMT_Encode4(32028), |
| 11207 | /* 31773 */ /*GILLT_v2s64*//*Label 785*/ GIMT_Encode4(32279), |
| 11208 | /* 31777 */ // Label 783: @31777 |
| 11209 | /* 31777 */ GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(31881), |
| 11210 | /* 31782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11211 | /* 31786 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11212 | /* 31790 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 788*/ GIMT_Encode4(31810), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3191 // |
| 11213 | /* 31797 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11214 | /* 31797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11215 | /* 31800 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11216 | /* 31802 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11217 | /* 31804 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11218 | /* 31809 */ // GIR_Coverage, 3191, |
| 11219 | /* 31809 */ GIR_EraseRootFromParent_Done, |
| 11220 | /* 31810 */ // Label 788: @31810 |
| 11221 | /* 31810 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 789*/ GIMT_Encode4(31830), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3192 // |
| 11222 | /* 31817 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11223 | /* 31817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11224 | /* 31820 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11225 | /* 31822 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11226 | /* 31824 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11227 | /* 31829 */ // GIR_Coverage, 3192, |
| 11228 | /* 31829 */ GIR_EraseRootFromParent_Done, |
| 11229 | /* 31830 */ // Label 789: @31830 |
| 11230 | /* 31830 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 790*/ GIMT_Encode4(31855), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3263 // |
| 11231 | /* 31837 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) |
| 11232 | /* 31837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 11233 | /* 31840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11234 | /* 31842 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11235 | /* 31844 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11236 | /* 31847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11237 | /* 31853 */ GIR_RootConstrainSelectedInstOperands, |
| 11238 | /* 31854 */ // GIR_Coverage, 3263, |
| 11239 | /* 31854 */ GIR_EraseRootFromParent_Done, |
| 11240 | /* 31855 */ // Label 790: @31855 |
| 11241 | /* 31855 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 791*/ GIMT_Encode4(31880), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3264 // |
| 11242 | /* 31862 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) |
| 11243 | /* 31862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 11244 | /* 31865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11245 | /* 31867 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11246 | /* 31869 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11247 | /* 31872 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11248 | /* 31878 */ GIR_RootConstrainSelectedInstOperands, |
| 11249 | /* 31879 */ // GIR_Coverage, 3264, |
| 11250 | /* 31879 */ GIR_EraseRootFromParent_Done, |
| 11251 | /* 31880 */ // Label 791: @31880 |
| 11252 | /* 31880 */ GIM_Reject, |
| 11253 | /* 31881 */ // Label 787: @31881 |
| 11254 | /* 31881 */ GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(32027), |
| 11255 | /* 31886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11256 | /* 31890 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11257 | /* 31894 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 793*/ GIMT_Encode4(31914), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5858 // |
| 11258 | /* 31901 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11259 | /* 31901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11260 | /* 31904 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11261 | /* 31906 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11262 | /* 31908 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11263 | /* 31913 */ // GIR_Coverage, 5858, |
| 11264 | /* 31913 */ GIR_EraseRootFromParent_Done, |
| 11265 | /* 31914 */ // Label 793: @31914 |
| 11266 | /* 31914 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 794*/ GIMT_Encode4(31934), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5859 // |
| 11267 | /* 31921 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11268 | /* 31921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11269 | /* 31924 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11270 | /* 31926 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11271 | /* 31928 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11272 | /* 31933 */ // GIR_Coverage, 5859, |
| 11273 | /* 31933 */ GIR_EraseRootFromParent_Done, |
| 11274 | /* 31934 */ // Label 794: @31934 |
| 11275 | /* 31934 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 795*/ GIMT_Encode4(31980), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5894 // |
| 11276 | /* 31941 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) |
| 11277 | /* 31941 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11278 | /* 31944 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11279 | /* 31948 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11280 | /* 31953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 11281 | /* 31956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11282 | /* 31958 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11283 | /* 31960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11284 | /* 31963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11285 | /* 31969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11286 | /* 31975 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11287 | /* 31978 */ GIR_RootConstrainSelectedInstOperands, |
| 11288 | /* 31979 */ // GIR_Coverage, 5894, |
| 11289 | /* 31979 */ GIR_EraseRootFromParent_Done, |
| 11290 | /* 31980 */ // Label 795: @31980 |
| 11291 | /* 31980 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 796*/ GIMT_Encode4(32026), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5895 // |
| 11292 | /* 31987 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) |
| 11293 | /* 31987 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11294 | /* 31990 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11295 | /* 31994 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11296 | /* 31999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 11297 | /* 32002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11298 | /* 32004 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11299 | /* 32006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11300 | /* 32009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11301 | /* 32015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11302 | /* 32021 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11303 | /* 32024 */ GIR_RootConstrainSelectedInstOperands, |
| 11304 | /* 32025 */ // GIR_Coverage, 5895, |
| 11305 | /* 32025 */ GIR_EraseRootFromParent_Done, |
| 11306 | /* 32026 */ // Label 796: @32026 |
| 11307 | /* 32026 */ GIM_Reject, |
| 11308 | /* 32027 */ // Label 792: @32027 |
| 11309 | /* 32027 */ GIM_Reject, |
| 11310 | /* 32028 */ // Label 784: @32028 |
| 11311 | /* 32028 */ GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(32132), |
| 11312 | /* 32033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11313 | /* 32037 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11314 | /* 32041 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 798*/ GIMT_Encode4(32061), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3189 // |
| 11315 | /* 32048 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11316 | /* 32048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11317 | /* 32051 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11318 | /* 32053 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11319 | /* 32055 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11320 | /* 32060 */ // GIR_Coverage, 3189, |
| 11321 | /* 32060 */ GIR_EraseRootFromParent_Done, |
| 11322 | /* 32061 */ // Label 798: @32061 |
| 11323 | /* 32061 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 799*/ GIMT_Encode4(32081), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3190 // |
| 11324 | /* 32068 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11325 | /* 32068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11326 | /* 32071 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11327 | /* 32073 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11328 | /* 32075 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11329 | /* 32080 */ // GIR_Coverage, 3190, |
| 11330 | /* 32080 */ GIR_EraseRootFromParent_Done, |
| 11331 | /* 32081 */ // Label 799: @32081 |
| 11332 | /* 32081 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 800*/ GIMT_Encode4(32106), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3261 // |
| 11333 | /* 32088 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) |
| 11334 | /* 32088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 11335 | /* 32091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11336 | /* 32093 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11337 | /* 32095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11338 | /* 32098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11339 | /* 32104 */ GIR_RootConstrainSelectedInstOperands, |
| 11340 | /* 32105 */ // GIR_Coverage, 3261, |
| 11341 | /* 32105 */ GIR_EraseRootFromParent_Done, |
| 11342 | /* 32106 */ // Label 800: @32106 |
| 11343 | /* 32106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 801*/ GIMT_Encode4(32131), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3262 // |
| 11344 | /* 32113 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) |
| 11345 | /* 32113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 11346 | /* 32116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11347 | /* 32118 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11348 | /* 32120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11349 | /* 32123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11350 | /* 32129 */ GIR_RootConstrainSelectedInstOperands, |
| 11351 | /* 32130 */ // GIR_Coverage, 3262, |
| 11352 | /* 32130 */ GIR_EraseRootFromParent_Done, |
| 11353 | /* 32131 */ // Label 801: @32131 |
| 11354 | /* 32131 */ GIM_Reject, |
| 11355 | /* 32132 */ // Label 797: @32132 |
| 11356 | /* 32132 */ GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(32278), |
| 11357 | /* 32137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11358 | /* 32141 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11359 | /* 32145 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 803*/ GIMT_Encode4(32165), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5856 // |
| 11360 | /* 32152 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11361 | /* 32152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11362 | /* 32155 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11363 | /* 32157 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11364 | /* 32159 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11365 | /* 32164 */ // GIR_Coverage, 5856, |
| 11366 | /* 32164 */ GIR_EraseRootFromParent_Done, |
| 11367 | /* 32165 */ // Label 803: @32165 |
| 11368 | /* 32165 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 804*/ GIMT_Encode4(32185), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5857 // |
| 11369 | /* 32172 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11370 | /* 32172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11371 | /* 32175 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11372 | /* 32177 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11373 | /* 32179 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11374 | /* 32184 */ // GIR_Coverage, 5857, |
| 11375 | /* 32184 */ GIR_EraseRootFromParent_Done, |
| 11376 | /* 32185 */ // Label 804: @32185 |
| 11377 | /* 32185 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 805*/ GIMT_Encode4(32231), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5892 // |
| 11378 | /* 32192 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) |
| 11379 | /* 32192 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11380 | /* 32195 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11381 | /* 32199 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11382 | /* 32204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 11383 | /* 32207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11384 | /* 32209 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11385 | /* 32211 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11386 | /* 32214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11387 | /* 32220 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11388 | /* 32226 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11389 | /* 32229 */ GIR_RootConstrainSelectedInstOperands, |
| 11390 | /* 32230 */ // GIR_Coverage, 5892, |
| 11391 | /* 32230 */ GIR_EraseRootFromParent_Done, |
| 11392 | /* 32231 */ // Label 805: @32231 |
| 11393 | /* 32231 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 806*/ GIMT_Encode4(32277), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5893 // |
| 11394 | /* 32238 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) |
| 11395 | /* 32238 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11396 | /* 32241 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11397 | /* 32245 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11398 | /* 32250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 11399 | /* 32253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11400 | /* 32255 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11401 | /* 32257 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11402 | /* 32260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11403 | /* 32266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11404 | /* 32272 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11405 | /* 32275 */ GIR_RootConstrainSelectedInstOperands, |
| 11406 | /* 32276 */ // GIR_Coverage, 5893, |
| 11407 | /* 32276 */ GIR_EraseRootFromParent_Done, |
| 11408 | /* 32277 */ // Label 806: @32277 |
| 11409 | /* 32277 */ GIM_Reject, |
| 11410 | /* 32278 */ // Label 802: @32278 |
| 11411 | /* 32278 */ GIM_Reject, |
| 11412 | /* 32279 */ // Label 785: @32279 |
| 11413 | /* 32279 */ GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(32383), |
| 11414 | /* 32284 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11415 | /* 32288 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11416 | /* 32292 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 808*/ GIMT_Encode4(32312), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3187 // |
| 11417 | /* 32299 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11418 | /* 32299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11419 | /* 32302 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11420 | /* 32304 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11421 | /* 32306 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11422 | /* 32311 */ // GIR_Coverage, 3187, |
| 11423 | /* 32311 */ GIR_EraseRootFromParent_Done, |
| 11424 | /* 32312 */ // Label 808: @32312 |
| 11425 | /* 32312 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 809*/ GIMT_Encode4(32332), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3188 // |
| 11426 | /* 32319 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11427 | /* 32319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11428 | /* 32322 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11429 | /* 32324 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11430 | /* 32326 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11431 | /* 32331 */ // GIR_Coverage, 3188, |
| 11432 | /* 32331 */ GIR_EraseRootFromParent_Done, |
| 11433 | /* 32332 */ // Label 809: @32332 |
| 11434 | /* 32332 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 810*/ GIMT_Encode4(32357), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3259 // |
| 11435 | /* 32339 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) |
| 11436 | /* 32339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 11437 | /* 32342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11438 | /* 32344 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11439 | /* 32346 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11440 | /* 32349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11441 | /* 32355 */ GIR_RootConstrainSelectedInstOperands, |
| 11442 | /* 32356 */ // GIR_Coverage, 3259, |
| 11443 | /* 32356 */ GIR_EraseRootFromParent_Done, |
| 11444 | /* 32357 */ // Label 810: @32357 |
| 11445 | /* 32357 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 811*/ GIMT_Encode4(32382), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3260 // |
| 11446 | /* 32364 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) |
| 11447 | /* 32364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 11448 | /* 32367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11449 | /* 32369 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11450 | /* 32371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11451 | /* 32374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11452 | /* 32380 */ GIR_RootConstrainSelectedInstOperands, |
| 11453 | /* 32381 */ // GIR_Coverage, 3260, |
| 11454 | /* 32381 */ GIR_EraseRootFromParent_Done, |
| 11455 | /* 32382 */ // Label 811: @32382 |
| 11456 | /* 32382 */ GIM_Reject, |
| 11457 | /* 32383 */ // Label 807: @32383 |
| 11458 | /* 32383 */ GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(32529), |
| 11459 | /* 32388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11460 | /* 32392 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11461 | /* 32396 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 813*/ GIMT_Encode4(32416), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5854 // |
| 11462 | /* 32403 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11463 | /* 32403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11464 | /* 32406 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11465 | /* 32408 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11466 | /* 32410 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11467 | /* 32415 */ // GIR_Coverage, 5854, |
| 11468 | /* 32415 */ GIR_EraseRootFromParent_Done, |
| 11469 | /* 32416 */ // Label 813: @32416 |
| 11470 | /* 32416 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 814*/ GIMT_Encode4(32436), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5855 // |
| 11471 | /* 32423 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11472 | /* 32423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11473 | /* 32426 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11474 | /* 32428 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11475 | /* 32430 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11476 | /* 32435 */ // GIR_Coverage, 5855, |
| 11477 | /* 32435 */ GIR_EraseRootFromParent_Done, |
| 11478 | /* 32436 */ // Label 814: @32436 |
| 11479 | /* 32436 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 815*/ GIMT_Encode4(32482), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5890 // |
| 11480 | /* 32443 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) |
| 11481 | /* 32443 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11482 | /* 32446 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11483 | /* 32450 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11484 | /* 32455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 11485 | /* 32458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11486 | /* 32460 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11487 | /* 32462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11488 | /* 32465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11489 | /* 32471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11490 | /* 32477 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11491 | /* 32480 */ GIR_RootConstrainSelectedInstOperands, |
| 11492 | /* 32481 */ // GIR_Coverage, 5890, |
| 11493 | /* 32481 */ GIR_EraseRootFromParent_Done, |
| 11494 | /* 32482 */ // Label 815: @32482 |
| 11495 | /* 32482 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 816*/ GIMT_Encode4(32528), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5891 // |
| 11496 | /* 32489 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) |
| 11497 | /* 32489 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11498 | /* 32492 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11499 | /* 32496 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11500 | /* 32501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 11501 | /* 32504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11502 | /* 32506 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11503 | /* 32508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11504 | /* 32511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11505 | /* 32517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11506 | /* 32523 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11507 | /* 32526 */ GIR_RootConstrainSelectedInstOperands, |
| 11508 | /* 32527 */ // GIR_Coverage, 5891, |
| 11509 | /* 32527 */ GIR_EraseRootFromParent_Done, |
| 11510 | /* 32528 */ // Label 816: @32528 |
| 11511 | /* 32528 */ GIM_Reject, |
| 11512 | /* 32529 */ // Label 812: @32529 |
| 11513 | /* 32529 */ GIM_Reject, |
| 11514 | /* 32530 */ // Label 786: @32530 |
| 11515 | /* 32530 */ GIM_Reject, |
| 11516 | /* 32531 */ // Label 722: @32531 |
| 11517 | /* 32531 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 821*/ GIMT_Encode4(33132), |
| 11518 | /* 32542 */ /*GILLT_s64*//*Label 817*/ GIMT_Encode4(32582), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 11519 | /* 32562 */ /*GILLT_v8s8*//*Label 818*/ GIMT_Encode4(32777), GIMT_Encode4(0), |
| 11520 | /* 32570 */ /*GILLT_v4s16*//*Label 819*/ GIMT_Encode4(32882), GIMT_Encode4(0), |
| 11521 | /* 32578 */ /*GILLT_v2s32*//*Label 820*/ GIMT_Encode4(32937), |
| 11522 | /* 32582 */ // Label 817: @32582 |
| 11523 | /* 32582 */ GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(32776), |
| 11524 | /* 32587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11525 | /* 32591 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11526 | /* 32595 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 823*/ GIMT_Encode4(32615), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3141 // |
| 11527 | /* 32602 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4f16] }:$src |
| 11528 | /* 32602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11529 | /* 32605 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11530 | /* 32607 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11531 | /* 32609 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11532 | /* 32614 */ // GIR_Coverage, 3141, |
| 11533 | /* 32614 */ GIR_EraseRootFromParent_Done, |
| 11534 | /* 32615 */ // Label 823: @32615 |
| 11535 | /* 32615 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 824*/ GIMT_Encode4(32635), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3142 // |
| 11536 | /* 32622 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4f16] }:$src |
| 11537 | /* 32622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11538 | /* 32625 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11539 | /* 32627 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11540 | /* 32629 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11541 | /* 32634 */ // GIR_Coverage, 3142, |
| 11542 | /* 32634 */ GIR_EraseRootFromParent_Done, |
| 11543 | /* 32635 */ // Label 824: @32635 |
| 11544 | /* 32635 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 825*/ GIMT_Encode4(32655), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3146 // |
| 11545 | /* 32642 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4i16] }:$src |
| 11546 | /* 32642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11547 | /* 32645 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11548 | /* 32647 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11549 | /* 32649 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11550 | /* 32654 */ // GIR_Coverage, 3146, |
| 11551 | /* 32654 */ GIR_EraseRootFromParent_Done, |
| 11552 | /* 32655 */ // Label 825: @32655 |
| 11553 | /* 32655 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 826*/ GIMT_Encode4(32675), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3147 // |
| 11554 | /* 32662 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4i16] }:$src |
| 11555 | /* 32662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11556 | /* 32665 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11557 | /* 32667 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11558 | /* 32669 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11559 | /* 32674 */ // GIR_Coverage, 3147, |
| 11560 | /* 32674 */ GIR_EraseRootFromParent_Done, |
| 11561 | /* 32675 */ // Label 826: @32675 |
| 11562 | /* 32675 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 827*/ GIMT_Encode4(32700), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3213 // |
| 11563 | /* 32682 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[f64] }:$src) |
| 11564 | /* 32682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 11565 | /* 32685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11566 | /* 32687 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11567 | /* 32689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11568 | /* 32692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11569 | /* 32698 */ GIR_RootConstrainSelectedInstOperands, |
| 11570 | /* 32699 */ // GIR_Coverage, 3213, |
| 11571 | /* 32699 */ GIR_EraseRootFromParent_Done, |
| 11572 | /* 32700 */ // Label 827: @32700 |
| 11573 | /* 32700 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 828*/ GIMT_Encode4(32725), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3214 // |
| 11574 | /* 32707 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) |
| 11575 | /* 32707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 11576 | /* 32710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11577 | /* 32712 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11578 | /* 32714 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11579 | /* 32717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11580 | /* 32723 */ GIR_RootConstrainSelectedInstOperands, |
| 11581 | /* 32724 */ // GIR_Coverage, 3214, |
| 11582 | /* 32724 */ GIR_EraseRootFromParent_Done, |
| 11583 | /* 32725 */ // Label 828: @32725 |
| 11584 | /* 32725 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 829*/ GIMT_Encode4(32750), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3218 // |
| 11585 | /* 32732 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src) |
| 11586 | /* 32732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 11587 | /* 32735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11588 | /* 32737 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11589 | /* 32739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11590 | /* 32742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11591 | /* 32748 */ GIR_RootConstrainSelectedInstOperands, |
| 11592 | /* 32749 */ // GIR_Coverage, 3218, |
| 11593 | /* 32749 */ GIR_EraseRootFromParent_Done, |
| 11594 | /* 32750 */ // Label 829: @32750 |
| 11595 | /* 32750 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 830*/ GIMT_Encode4(32775), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3219 // |
| 11596 | /* 32757 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) |
| 11597 | /* 32757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 11598 | /* 32760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11599 | /* 32762 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11600 | /* 32764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11601 | /* 32767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11602 | /* 32773 */ GIR_RootConstrainSelectedInstOperands, |
| 11603 | /* 32774 */ // GIR_Coverage, 3219, |
| 11604 | /* 32774 */ GIR_EraseRootFromParent_Done, |
| 11605 | /* 32775 */ // Label 830: @32775 |
| 11606 | /* 32775 */ GIM_Reject, |
| 11607 | /* 32776 */ // Label 822: @32776 |
| 11608 | /* 32776 */ GIM_Reject, |
| 11609 | /* 32777 */ // Label 818: @32777 |
| 11610 | /* 32777 */ GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(32881), |
| 11611 | /* 32782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11612 | /* 32786 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11613 | /* 32790 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 832*/ GIMT_Encode4(32810), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3145 // |
| 11614 | /* 32797 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4f16] }:$src |
| 11615 | /* 32797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11616 | /* 32800 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11617 | /* 32802 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11618 | /* 32804 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11619 | /* 32809 */ // GIR_Coverage, 3145, |
| 11620 | /* 32809 */ GIR_EraseRootFromParent_Done, |
| 11621 | /* 32810 */ // Label 832: @32810 |
| 11622 | /* 32810 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 833*/ GIMT_Encode4(32830), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3150 // |
| 11623 | /* 32817 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4i16] }:$src |
| 11624 | /* 32817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11625 | /* 32820 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11626 | /* 32822 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11627 | /* 32824 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11628 | /* 32829 */ // GIR_Coverage, 3150, |
| 11629 | /* 32829 */ GIR_EraseRootFromParent_Done, |
| 11630 | /* 32830 */ // Label 833: @32830 |
| 11631 | /* 32830 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 834*/ GIMT_Encode4(32855), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3217 // |
| 11632 | /* 32837 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) |
| 11633 | /* 32837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 11634 | /* 32840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11635 | /* 32842 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11636 | /* 32844 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11637 | /* 32847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11638 | /* 32853 */ GIR_RootConstrainSelectedInstOperands, |
| 11639 | /* 32854 */ // GIR_Coverage, 3217, |
| 11640 | /* 32854 */ GIR_EraseRootFromParent_Done, |
| 11641 | /* 32855 */ // Label 834: @32855 |
| 11642 | /* 32855 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 835*/ GIMT_Encode4(32880), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3222 // |
| 11643 | /* 32862 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) |
| 11644 | /* 32862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 11645 | /* 32865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11646 | /* 32867 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11647 | /* 32869 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11648 | /* 32872 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11649 | /* 32878 */ GIR_RootConstrainSelectedInstOperands, |
| 11650 | /* 32879 */ // GIR_Coverage, 3222, |
| 11651 | /* 32879 */ GIR_EraseRootFromParent_Done, |
| 11652 | /* 32880 */ // Label 835: @32880 |
| 11653 | /* 32880 */ GIM_Reject, |
| 11654 | /* 32881 */ // Label 831: @32881 |
| 11655 | /* 32881 */ GIM_Reject, |
| 11656 | /* 32882 */ // Label 819: @32882 |
| 11657 | /* 32882 */ GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(32936), |
| 11658 | /* 32887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11659 | /* 32891 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11660 | /* 32895 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 837*/ GIMT_Encode4(32915), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3113 // |
| 11661 | /* 32902 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v4i16] }:$src |
| 11662 | /* 32902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11663 | /* 32905 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11664 | /* 32907 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11665 | /* 32909 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11666 | /* 32914 */ // GIR_Coverage, 3113, |
| 11667 | /* 32914 */ GIR_EraseRootFromParent_Done, |
| 11668 | /* 32915 */ // Label 837: @32915 |
| 11669 | /* 32915 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 838*/ GIMT_Encode4(32935), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3114 // |
| 11670 | /* 32922 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v4f16] }:$src |
| 11671 | /* 32922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11672 | /* 32925 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11673 | /* 32927 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11674 | /* 32929 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11675 | /* 32934 */ // GIR_Coverage, 3114, |
| 11676 | /* 32934 */ GIR_EraseRootFromParent_Done, |
| 11677 | /* 32935 */ // Label 838: @32935 |
| 11678 | /* 32935 */ GIM_Reject, |
| 11679 | /* 32936 */ // Label 836: @32936 |
| 11680 | /* 32936 */ GIM_Reject, |
| 11681 | /* 32937 */ // Label 820: @32937 |
| 11682 | /* 32937 */ GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(33131), |
| 11683 | /* 32942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11684 | /* 32946 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11685 | /* 32950 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 840*/ GIMT_Encode4(32970), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3143 // |
| 11686 | /* 32957 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4f16] }:$src |
| 11687 | /* 32957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11688 | /* 32960 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11689 | /* 32962 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11690 | /* 32964 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11691 | /* 32969 */ // GIR_Coverage, 3143, |
| 11692 | /* 32969 */ GIR_EraseRootFromParent_Done, |
| 11693 | /* 32970 */ // Label 840: @32970 |
| 11694 | /* 32970 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 841*/ GIMT_Encode4(32990), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3144 // |
| 11695 | /* 32977 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4f16] }:$src |
| 11696 | /* 32977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11697 | /* 32980 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11698 | /* 32982 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11699 | /* 32984 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11700 | /* 32989 */ // GIR_Coverage, 3144, |
| 11701 | /* 32989 */ GIR_EraseRootFromParent_Done, |
| 11702 | /* 32990 */ // Label 841: @32990 |
| 11703 | /* 32990 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 842*/ GIMT_Encode4(33010), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3148 // |
| 11704 | /* 32997 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4i16] }:$src |
| 11705 | /* 32997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11706 | /* 33000 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11707 | /* 33002 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11708 | /* 33004 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11709 | /* 33009 */ // GIR_Coverage, 3148, |
| 11710 | /* 33009 */ GIR_EraseRootFromParent_Done, |
| 11711 | /* 33010 */ // Label 842: @33010 |
| 11712 | /* 33010 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 843*/ GIMT_Encode4(33030), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3149 // |
| 11713 | /* 33017 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4i16] }:$src |
| 11714 | /* 33017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11715 | /* 33020 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11716 | /* 33022 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11717 | /* 33024 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11718 | /* 33029 */ // GIR_Coverage, 3149, |
| 11719 | /* 33029 */ GIR_EraseRootFromParent_Done, |
| 11720 | /* 33030 */ // Label 843: @33030 |
| 11721 | /* 33030 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 844*/ GIMT_Encode4(33055), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3215 // |
| 11722 | /* 33037 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) |
| 11723 | /* 33037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 11724 | /* 33040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11725 | /* 33042 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11726 | /* 33044 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11727 | /* 33047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11728 | /* 33053 */ GIR_RootConstrainSelectedInstOperands, |
| 11729 | /* 33054 */ // GIR_Coverage, 3215, |
| 11730 | /* 33054 */ GIR_EraseRootFromParent_Done, |
| 11731 | /* 33055 */ // Label 844: @33055 |
| 11732 | /* 33055 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 845*/ GIMT_Encode4(33080), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3216 // |
| 11733 | /* 33062 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) |
| 11734 | /* 33062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 11735 | /* 33065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11736 | /* 33067 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11737 | /* 33069 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11738 | /* 33072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11739 | /* 33078 */ GIR_RootConstrainSelectedInstOperands, |
| 11740 | /* 33079 */ // GIR_Coverage, 3216, |
| 11741 | /* 33079 */ GIR_EraseRootFromParent_Done, |
| 11742 | /* 33080 */ // Label 845: @33080 |
| 11743 | /* 33080 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 846*/ GIMT_Encode4(33105), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3220 // |
| 11744 | /* 33087 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) |
| 11745 | /* 33087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 11746 | /* 33090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11747 | /* 33092 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11748 | /* 33094 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11749 | /* 33097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11750 | /* 33103 */ GIR_RootConstrainSelectedInstOperands, |
| 11751 | /* 33104 */ // GIR_Coverage, 3220, |
| 11752 | /* 33104 */ GIR_EraseRootFromParent_Done, |
| 11753 | /* 33105 */ // Label 846: @33105 |
| 11754 | /* 33105 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 847*/ GIMT_Encode4(33130), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3221 // |
| 11755 | /* 33112 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) |
| 11756 | /* 33112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 11757 | /* 33115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11758 | /* 33117 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11759 | /* 33119 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11760 | /* 33122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11761 | /* 33128 */ GIR_RootConstrainSelectedInstOperands, |
| 11762 | /* 33129 */ // GIR_Coverage, 3221, |
| 11763 | /* 33129 */ GIR_EraseRootFromParent_Done, |
| 11764 | /* 33130 */ // Label 847: @33130 |
| 11765 | /* 33130 */ GIM_Reject, |
| 11766 | /* 33131 */ // Label 839: @33131 |
| 11767 | /* 33131 */ GIM_Reject, |
| 11768 | /* 33132 */ // Label 821: @33132 |
| 11769 | /* 33132 */ GIM_Reject, |
| 11770 | /* 33133 */ // Label 723: @33133 |
| 11771 | /* 33133 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 852*/ GIMT_Encode4(34474), |
| 11772 | /* 33144 */ /*GILLT_v16s8*//*Label 848*/ GIMT_Encode4(33168), GIMT_Encode4(0), |
| 11773 | /* 33152 */ /*GILLT_v8s16*//*Label 849*/ GIMT_Encode4(33419), GIMT_Encode4(0), |
| 11774 | /* 33160 */ /*GILLT_v4s32*//*Label 850*/ GIMT_Encode4(33528), |
| 11775 | /* 33164 */ /*GILLT_v2s64*//*Label 851*/ GIMT_Encode4(34001), |
| 11776 | /* 33168 */ // Label 848: @33168 |
| 11777 | /* 33168 */ GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(33272), |
| 11778 | /* 33173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11779 | /* 33177 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11780 | /* 33181 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 854*/ GIMT_Encode4(33201), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3181 // |
| 11781 | /* 33188 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8f16] }:$src |
| 11782 | /* 33188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11783 | /* 33191 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11784 | /* 33193 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11785 | /* 33195 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11786 | /* 33200 */ // GIR_Coverage, 3181, |
| 11787 | /* 33200 */ GIR_EraseRootFromParent_Done, |
| 11788 | /* 33201 */ // Label 854: @33201 |
| 11789 | /* 33201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 855*/ GIMT_Encode4(33221), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3186 // |
| 11790 | /* 33208 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8i16] }:$src |
| 11791 | /* 33208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11792 | /* 33211 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11793 | /* 33213 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11794 | /* 33215 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11795 | /* 33220 */ // GIR_Coverage, 3186, |
| 11796 | /* 33220 */ GIR_EraseRootFromParent_Done, |
| 11797 | /* 33221 */ // Label 855: @33221 |
| 11798 | /* 33221 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 856*/ GIMT_Encode4(33246), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3253 // |
| 11799 | /* 33228 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) |
| 11800 | /* 33228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 11801 | /* 33231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11802 | /* 33233 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11803 | /* 33235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11804 | /* 33238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11805 | /* 33244 */ GIR_RootConstrainSelectedInstOperands, |
| 11806 | /* 33245 */ // GIR_Coverage, 3253, |
| 11807 | /* 33245 */ GIR_EraseRootFromParent_Done, |
| 11808 | /* 33246 */ // Label 856: @33246 |
| 11809 | /* 33246 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 857*/ GIMT_Encode4(33271), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3258 // |
| 11810 | /* 33253 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) |
| 11811 | /* 33253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 11812 | /* 33256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11813 | /* 33258 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11814 | /* 33260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11815 | /* 33263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11816 | /* 33269 */ GIR_RootConstrainSelectedInstOperands, |
| 11817 | /* 33270 */ // GIR_Coverage, 3258, |
| 11818 | /* 33270 */ GIR_EraseRootFromParent_Done, |
| 11819 | /* 33271 */ // Label 857: @33271 |
| 11820 | /* 33271 */ GIM_Reject, |
| 11821 | /* 33272 */ // Label 853: @33272 |
| 11822 | /* 33272 */ GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(33418), |
| 11823 | /* 33277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11824 | /* 33281 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11825 | /* 33285 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 859*/ GIMT_Encode4(33305), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5848 // |
| 11826 | /* 33292 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 11827 | /* 33292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11828 | /* 33295 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11829 | /* 33297 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11830 | /* 33299 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11831 | /* 33304 */ // GIR_Coverage, 5848, |
| 11832 | /* 33304 */ GIR_EraseRootFromParent_Done, |
| 11833 | /* 33305 */ // Label 859: @33305 |
| 11834 | /* 33305 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 860*/ GIMT_Encode4(33325), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5853 // |
| 11835 | /* 33312 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 11836 | /* 33312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11837 | /* 33315 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11838 | /* 33317 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11839 | /* 33319 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11840 | /* 33324 */ // GIR_Coverage, 5853, |
| 11841 | /* 33324 */ GIR_EraseRootFromParent_Done, |
| 11842 | /* 33325 */ // Label 860: @33325 |
| 11843 | /* 33325 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 861*/ GIMT_Encode4(33371), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5884 // |
| 11844 | /* 33332 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) |
| 11845 | /* 33332 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11846 | /* 33335 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11847 | /* 33339 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11848 | /* 33344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 11849 | /* 33347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11850 | /* 33349 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11851 | /* 33351 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11852 | /* 33354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11853 | /* 33360 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11854 | /* 33366 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11855 | /* 33369 */ GIR_RootConstrainSelectedInstOperands, |
| 11856 | /* 33370 */ // GIR_Coverage, 5884, |
| 11857 | /* 33370 */ GIR_EraseRootFromParent_Done, |
| 11858 | /* 33371 */ // Label 861: @33371 |
| 11859 | /* 33371 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 862*/ GIMT_Encode4(33417), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5889 // |
| 11860 | /* 33378 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 11861 | /* 33378 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11862 | /* 33381 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11863 | /* 33385 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11864 | /* 33390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 11865 | /* 33393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11866 | /* 33395 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11867 | /* 33397 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11868 | /* 33400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11869 | /* 33406 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11870 | /* 33412 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11871 | /* 33415 */ GIR_RootConstrainSelectedInstOperands, |
| 11872 | /* 33416 */ // GIR_Coverage, 5889, |
| 11873 | /* 33416 */ GIR_EraseRootFromParent_Done, |
| 11874 | /* 33417 */ // Label 862: @33417 |
| 11875 | /* 33417 */ GIM_Reject, |
| 11876 | /* 33418 */ // Label 858: @33418 |
| 11877 | /* 33418 */ GIM_Reject, |
| 11878 | /* 33419 */ // Label 849: @33419 |
| 11879 | /* 33419 */ GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(33473), |
| 11880 | /* 33424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11881 | /* 33428 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11882 | /* 33432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 864*/ GIMT_Encode4(33452), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3119 // |
| 11883 | /* 33439 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v8i16] }:$src |
| 11884 | /* 33439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11885 | /* 33442 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11886 | /* 33444 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11887 | /* 33446 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11888 | /* 33451 */ // GIR_Coverage, 3119, |
| 11889 | /* 33451 */ GIR_EraseRootFromParent_Done, |
| 11890 | /* 33452 */ // Label 864: @33452 |
| 11891 | /* 33452 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 865*/ GIMT_Encode4(33472), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3120 // |
| 11892 | /* 33459 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v8f16] }:$src |
| 11893 | /* 33459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11894 | /* 33462 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11895 | /* 33464 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11896 | /* 33466 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11897 | /* 33471 */ // GIR_Coverage, 3120, |
| 11898 | /* 33471 */ GIR_EraseRootFromParent_Done, |
| 11899 | /* 33472 */ // Label 865: @33472 |
| 11900 | /* 33472 */ GIM_Reject, |
| 11901 | /* 33473 */ // Label 863: @33473 |
| 11902 | /* 33473 */ GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(33527), |
| 11903 | /* 33478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11904 | /* 33482 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11905 | /* 33486 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 867*/ GIMT_Encode4(33506), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5822 // |
| 11906 | /* 33493 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 11907 | /* 33493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11908 | /* 33496 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11909 | /* 33498 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11910 | /* 33500 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11911 | /* 33505 */ // GIR_Coverage, 5822, |
| 11912 | /* 33505 */ GIR_EraseRootFromParent_Done, |
| 11913 | /* 33506 */ // Label 867: @33506 |
| 11914 | /* 33506 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 868*/ GIMT_Encode4(33526), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5823 // |
| 11915 | /* 33513 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 11916 | /* 33513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11917 | /* 33516 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11918 | /* 33518 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11919 | /* 33520 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11920 | /* 33525 */ // GIR_Coverage, 5823, |
| 11921 | /* 33525 */ GIR_EraseRootFromParent_Done, |
| 11922 | /* 33526 */ // Label 868: @33526 |
| 11923 | /* 33526 */ GIM_Reject, |
| 11924 | /* 33527 */ // Label 866: @33527 |
| 11925 | /* 33527 */ GIM_Reject, |
| 11926 | /* 33528 */ // Label 850: @33528 |
| 11927 | /* 33528 */ GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(33722), |
| 11928 | /* 33533 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11929 | /* 33537 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11930 | /* 33541 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 870*/ GIMT_Encode4(33561), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3179 // |
| 11931 | /* 33548 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8f16] }:$src |
| 11932 | /* 33548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11933 | /* 33551 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11934 | /* 33553 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11935 | /* 33555 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11936 | /* 33560 */ // GIR_Coverage, 3179, |
| 11937 | /* 33560 */ GIR_EraseRootFromParent_Done, |
| 11938 | /* 33561 */ // Label 870: @33561 |
| 11939 | /* 33561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 871*/ GIMT_Encode4(33581), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3180 // |
| 11940 | /* 33568 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8f16] }:$src |
| 11941 | /* 33568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11942 | /* 33571 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11943 | /* 33573 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11944 | /* 33575 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11945 | /* 33580 */ // GIR_Coverage, 3180, |
| 11946 | /* 33580 */ GIR_EraseRootFromParent_Done, |
| 11947 | /* 33581 */ // Label 871: @33581 |
| 11948 | /* 33581 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 872*/ GIMT_Encode4(33601), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3184 // |
| 11949 | /* 33588 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8i16] }:$src |
| 11950 | /* 33588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11951 | /* 33591 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11952 | /* 33593 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11953 | /* 33595 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11954 | /* 33600 */ // GIR_Coverage, 3184, |
| 11955 | /* 33600 */ GIR_EraseRootFromParent_Done, |
| 11956 | /* 33601 */ // Label 872: @33601 |
| 11957 | /* 33601 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 873*/ GIMT_Encode4(33621), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3185 // |
| 11958 | /* 33608 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8i16] }:$src |
| 11959 | /* 33608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11960 | /* 33611 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11961 | /* 33613 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11962 | /* 33615 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11963 | /* 33620 */ // GIR_Coverage, 3185, |
| 11964 | /* 33620 */ GIR_EraseRootFromParent_Done, |
| 11965 | /* 33621 */ // Label 873: @33621 |
| 11966 | /* 33621 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 874*/ GIMT_Encode4(33646), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3251 // |
| 11967 | /* 33628 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) |
| 11968 | /* 33628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11969 | /* 33631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11970 | /* 33633 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11971 | /* 33635 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11972 | /* 33638 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11973 | /* 33644 */ GIR_RootConstrainSelectedInstOperands, |
| 11974 | /* 33645 */ // GIR_Coverage, 3251, |
| 11975 | /* 33645 */ GIR_EraseRootFromParent_Done, |
| 11976 | /* 33646 */ // Label 874: @33646 |
| 11977 | /* 33646 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 875*/ GIMT_Encode4(33671), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3252 // |
| 11978 | /* 33653 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) |
| 11979 | /* 33653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11980 | /* 33656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11981 | /* 33658 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11982 | /* 33660 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11983 | /* 33663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11984 | /* 33669 */ GIR_RootConstrainSelectedInstOperands, |
| 11985 | /* 33670 */ // GIR_Coverage, 3252, |
| 11986 | /* 33670 */ GIR_EraseRootFromParent_Done, |
| 11987 | /* 33671 */ // Label 875: @33671 |
| 11988 | /* 33671 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 876*/ GIMT_Encode4(33696), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3256 // |
| 11989 | /* 33678 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) |
| 11990 | /* 33678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11991 | /* 33681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11992 | /* 33683 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11993 | /* 33685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11994 | /* 33688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11995 | /* 33694 */ GIR_RootConstrainSelectedInstOperands, |
| 11996 | /* 33695 */ // GIR_Coverage, 3256, |
| 11997 | /* 33695 */ GIR_EraseRootFromParent_Done, |
| 11998 | /* 33696 */ // Label 876: @33696 |
| 11999 | /* 33696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 877*/ GIMT_Encode4(33721), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3257 // |
| 12000 | /* 33703 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) |
| 12001 | /* 33703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12002 | /* 33706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12003 | /* 33708 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12004 | /* 33710 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12005 | /* 33713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12006 | /* 33719 */ GIR_RootConstrainSelectedInstOperands, |
| 12007 | /* 33720 */ // GIR_Coverage, 3257, |
| 12008 | /* 33720 */ GIR_EraseRootFromParent_Done, |
| 12009 | /* 33721 */ // Label 877: @33721 |
| 12010 | /* 33721 */ GIM_Reject, |
| 12011 | /* 33722 */ // Label 869: @33722 |
| 12012 | /* 33722 */ GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(34000), |
| 12013 | /* 33727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12014 | /* 33731 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12015 | /* 33735 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 879*/ GIMT_Encode4(33755), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5846 // |
| 12016 | /* 33742 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 12017 | /* 33742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12018 | /* 33745 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12019 | /* 33747 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12020 | /* 33749 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12021 | /* 33754 */ // GIR_Coverage, 5846, |
| 12022 | /* 33754 */ GIR_EraseRootFromParent_Done, |
| 12023 | /* 33755 */ // Label 879: @33755 |
| 12024 | /* 33755 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 880*/ GIMT_Encode4(33775), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5847 // |
| 12025 | /* 33762 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 12026 | /* 33762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12027 | /* 33765 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12028 | /* 33767 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12029 | /* 33769 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12030 | /* 33774 */ // GIR_Coverage, 5847, |
| 12031 | /* 33774 */ GIR_EraseRootFromParent_Done, |
| 12032 | /* 33775 */ // Label 880: @33775 |
| 12033 | /* 33775 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 881*/ GIMT_Encode4(33795), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5851 // |
| 12034 | /* 33782 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 12035 | /* 33782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12036 | /* 33785 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12037 | /* 33787 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12038 | /* 33789 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12039 | /* 33794 */ // GIR_Coverage, 5851, |
| 12040 | /* 33794 */ GIR_EraseRootFromParent_Done, |
| 12041 | /* 33795 */ // Label 881: @33795 |
| 12042 | /* 33795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 882*/ GIMT_Encode4(33815), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5852 // |
| 12043 | /* 33802 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 12044 | /* 33802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12045 | /* 33805 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12046 | /* 33807 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12047 | /* 33809 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12048 | /* 33814 */ // GIR_Coverage, 5852, |
| 12049 | /* 33814 */ GIR_EraseRootFromParent_Done, |
| 12050 | /* 33815 */ // Label 882: @33815 |
| 12051 | /* 33815 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 883*/ GIMT_Encode4(33861), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5882 // |
| 12052 | /* 33822 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) |
| 12053 | /* 33822 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12054 | /* 33825 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12055 | /* 33829 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12056 | /* 33834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12057 | /* 33837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12058 | /* 33839 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12059 | /* 33841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12060 | /* 33844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12061 | /* 33850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12062 | /* 33856 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12063 | /* 33859 */ GIR_RootConstrainSelectedInstOperands, |
| 12064 | /* 33860 */ // GIR_Coverage, 5882, |
| 12065 | /* 33860 */ GIR_EraseRootFromParent_Done, |
| 12066 | /* 33861 */ // Label 883: @33861 |
| 12067 | /* 33861 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 884*/ GIMT_Encode4(33907), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5883 // |
| 12068 | /* 33868 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) |
| 12069 | /* 33868 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12070 | /* 33871 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12071 | /* 33875 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12072 | /* 33880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12073 | /* 33883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12074 | /* 33885 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12075 | /* 33887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12076 | /* 33890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12077 | /* 33896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12078 | /* 33902 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12079 | /* 33905 */ GIR_RootConstrainSelectedInstOperands, |
| 12080 | /* 33906 */ // GIR_Coverage, 5883, |
| 12081 | /* 33906 */ GIR_EraseRootFromParent_Done, |
| 12082 | /* 33907 */ // Label 884: @33907 |
| 12083 | /* 33907 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 885*/ GIMT_Encode4(33953), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5887 // |
| 12084 | /* 33914 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) |
| 12085 | /* 33914 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12086 | /* 33917 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12087 | /* 33921 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12088 | /* 33926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12089 | /* 33929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12090 | /* 33931 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12091 | /* 33933 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12092 | /* 33936 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12093 | /* 33942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12094 | /* 33948 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12095 | /* 33951 */ GIR_RootConstrainSelectedInstOperands, |
| 12096 | /* 33952 */ // GIR_Coverage, 5887, |
| 12097 | /* 33952 */ GIR_EraseRootFromParent_Done, |
| 12098 | /* 33953 */ // Label 885: @33953 |
| 12099 | /* 33953 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 886*/ GIMT_Encode4(33999), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5888 // |
| 12100 | /* 33960 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) |
| 12101 | /* 33960 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12102 | /* 33963 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12103 | /* 33967 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12104 | /* 33972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12105 | /* 33975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12106 | /* 33977 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12107 | /* 33979 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12108 | /* 33982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12109 | /* 33988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12110 | /* 33994 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12111 | /* 33997 */ GIR_RootConstrainSelectedInstOperands, |
| 12112 | /* 33998 */ // GIR_Coverage, 5888, |
| 12113 | /* 33998 */ GIR_EraseRootFromParent_Done, |
| 12114 | /* 33999 */ // Label 886: @33999 |
| 12115 | /* 33999 */ GIM_Reject, |
| 12116 | /* 34000 */ // Label 878: @34000 |
| 12117 | /* 34000 */ GIM_Reject, |
| 12118 | /* 34001 */ // Label 851: @34001 |
| 12119 | /* 34001 */ GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(34195), |
| 12120 | /* 34006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12121 | /* 34010 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12122 | /* 34014 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 888*/ GIMT_Encode4(34034), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3177 // |
| 12123 | /* 34021 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8f16] }:$src |
| 12124 | /* 34021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12125 | /* 34024 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12126 | /* 34026 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12127 | /* 34028 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12128 | /* 34033 */ // GIR_Coverage, 3177, |
| 12129 | /* 34033 */ GIR_EraseRootFromParent_Done, |
| 12130 | /* 34034 */ // Label 888: @34034 |
| 12131 | /* 34034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 889*/ GIMT_Encode4(34054), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3178 // |
| 12132 | /* 34041 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8f16] }:$src |
| 12133 | /* 34041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12134 | /* 34044 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12135 | /* 34046 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12136 | /* 34048 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12137 | /* 34053 */ // GIR_Coverage, 3178, |
| 12138 | /* 34053 */ GIR_EraseRootFromParent_Done, |
| 12139 | /* 34054 */ // Label 889: @34054 |
| 12140 | /* 34054 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 890*/ GIMT_Encode4(34074), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3182 // |
| 12141 | /* 34061 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8i16] }:$src |
| 12142 | /* 34061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12143 | /* 34064 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12144 | /* 34066 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12145 | /* 34068 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12146 | /* 34073 */ // GIR_Coverage, 3182, |
| 12147 | /* 34073 */ GIR_EraseRootFromParent_Done, |
| 12148 | /* 34074 */ // Label 890: @34074 |
| 12149 | /* 34074 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 891*/ GIMT_Encode4(34094), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3183 // |
| 12150 | /* 34081 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8i16] }:$src |
| 12151 | /* 34081 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12152 | /* 34084 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12153 | /* 34086 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12154 | /* 34088 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12155 | /* 34093 */ // GIR_Coverage, 3183, |
| 12156 | /* 34093 */ GIR_EraseRootFromParent_Done, |
| 12157 | /* 34094 */ // Label 891: @34094 |
| 12158 | /* 34094 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 892*/ GIMT_Encode4(34119), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3249 // |
| 12159 | /* 34101 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) |
| 12160 | /* 34101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 12161 | /* 34104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12162 | /* 34106 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12163 | /* 34108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12164 | /* 34111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12165 | /* 34117 */ GIR_RootConstrainSelectedInstOperands, |
| 12166 | /* 34118 */ // GIR_Coverage, 3249, |
| 12167 | /* 34118 */ GIR_EraseRootFromParent_Done, |
| 12168 | /* 34119 */ // Label 892: @34119 |
| 12169 | /* 34119 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 893*/ GIMT_Encode4(34144), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3250 // |
| 12170 | /* 34126 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) |
| 12171 | /* 34126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 12172 | /* 34129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12173 | /* 34131 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12174 | /* 34133 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12175 | /* 34136 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12176 | /* 34142 */ GIR_RootConstrainSelectedInstOperands, |
| 12177 | /* 34143 */ // GIR_Coverage, 3250, |
| 12178 | /* 34143 */ GIR_EraseRootFromParent_Done, |
| 12179 | /* 34144 */ // Label 893: @34144 |
| 12180 | /* 34144 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 894*/ GIMT_Encode4(34169), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3254 // |
| 12181 | /* 34151 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) |
| 12182 | /* 34151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 12183 | /* 34154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12184 | /* 34156 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12185 | /* 34158 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12186 | /* 34161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12187 | /* 34167 */ GIR_RootConstrainSelectedInstOperands, |
| 12188 | /* 34168 */ // GIR_Coverage, 3254, |
| 12189 | /* 34168 */ GIR_EraseRootFromParent_Done, |
| 12190 | /* 34169 */ // Label 894: @34169 |
| 12191 | /* 34169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 895*/ GIMT_Encode4(34194), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3255 // |
| 12192 | /* 34176 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) |
| 12193 | /* 34176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 12194 | /* 34179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12195 | /* 34181 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12196 | /* 34183 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12197 | /* 34186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12198 | /* 34192 */ GIR_RootConstrainSelectedInstOperands, |
| 12199 | /* 34193 */ // GIR_Coverage, 3255, |
| 12200 | /* 34193 */ GIR_EraseRootFromParent_Done, |
| 12201 | /* 34194 */ // Label 895: @34194 |
| 12202 | /* 34194 */ GIM_Reject, |
| 12203 | /* 34195 */ // Label 887: @34195 |
| 12204 | /* 34195 */ GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(34473), |
| 12205 | /* 34200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12206 | /* 34204 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12207 | /* 34208 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 897*/ GIMT_Encode4(34228), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5844 // |
| 12208 | /* 34215 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 12209 | /* 34215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12210 | /* 34218 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12211 | /* 34220 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12212 | /* 34222 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12213 | /* 34227 */ // GIR_Coverage, 5844, |
| 12214 | /* 34227 */ GIR_EraseRootFromParent_Done, |
| 12215 | /* 34228 */ // Label 897: @34228 |
| 12216 | /* 34228 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 898*/ GIMT_Encode4(34248), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5845 // |
| 12217 | /* 34235 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 12218 | /* 34235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12219 | /* 34238 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12220 | /* 34240 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12221 | /* 34242 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12222 | /* 34247 */ // GIR_Coverage, 5845, |
| 12223 | /* 34247 */ GIR_EraseRootFromParent_Done, |
| 12224 | /* 34248 */ // Label 898: @34248 |
| 12225 | /* 34248 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 899*/ GIMT_Encode4(34268), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5849 // |
| 12226 | /* 34255 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 12227 | /* 34255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12228 | /* 34258 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12229 | /* 34260 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12230 | /* 34262 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12231 | /* 34267 */ // GIR_Coverage, 5849, |
| 12232 | /* 34267 */ GIR_EraseRootFromParent_Done, |
| 12233 | /* 34268 */ // Label 899: @34268 |
| 12234 | /* 34268 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 900*/ GIMT_Encode4(34288), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5850 // |
| 12235 | /* 34275 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 12236 | /* 34275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12237 | /* 34278 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12238 | /* 34280 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12239 | /* 34282 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12240 | /* 34287 */ // GIR_Coverage, 5850, |
| 12241 | /* 34287 */ GIR_EraseRootFromParent_Done, |
| 12242 | /* 34288 */ // Label 900: @34288 |
| 12243 | /* 34288 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 901*/ GIMT_Encode4(34334), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5880 // |
| 12244 | /* 34295 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) |
| 12245 | /* 34295 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12246 | /* 34298 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12247 | /* 34302 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12248 | /* 34307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12249 | /* 34310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12250 | /* 34312 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12251 | /* 34314 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12252 | /* 34317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12253 | /* 34323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12254 | /* 34329 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12255 | /* 34332 */ GIR_RootConstrainSelectedInstOperands, |
| 12256 | /* 34333 */ // GIR_Coverage, 5880, |
| 12257 | /* 34333 */ GIR_EraseRootFromParent_Done, |
| 12258 | /* 34334 */ // Label 901: @34334 |
| 12259 | /* 34334 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 902*/ GIMT_Encode4(34380), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5881 // |
| 12260 | /* 34341 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) |
| 12261 | /* 34341 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12262 | /* 34344 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12263 | /* 34348 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12264 | /* 34353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12265 | /* 34356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12266 | /* 34358 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12267 | /* 34360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12268 | /* 34363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12269 | /* 34369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12270 | /* 34375 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12271 | /* 34378 */ GIR_RootConstrainSelectedInstOperands, |
| 12272 | /* 34379 */ // GIR_Coverage, 5881, |
| 12273 | /* 34379 */ GIR_EraseRootFromParent_Done, |
| 12274 | /* 34380 */ // Label 902: @34380 |
| 12275 | /* 34380 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 903*/ GIMT_Encode4(34426), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5885 // |
| 12276 | /* 34387 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) |
| 12277 | /* 34387 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12278 | /* 34390 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12279 | /* 34394 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12280 | /* 34399 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12281 | /* 34402 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12282 | /* 34404 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12283 | /* 34406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12284 | /* 34409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12285 | /* 34415 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12286 | /* 34421 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12287 | /* 34424 */ GIR_RootConstrainSelectedInstOperands, |
| 12288 | /* 34425 */ // GIR_Coverage, 5885, |
| 12289 | /* 34425 */ GIR_EraseRootFromParent_Done, |
| 12290 | /* 34426 */ // Label 903: @34426 |
| 12291 | /* 34426 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 904*/ GIMT_Encode4(34472), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5886 // |
| 12292 | /* 34433 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) |
| 12293 | /* 34433 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12294 | /* 34436 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12295 | /* 34440 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12296 | /* 34445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12297 | /* 34448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12298 | /* 34450 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12299 | /* 34452 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12300 | /* 34455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12301 | /* 34461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12302 | /* 34467 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12303 | /* 34470 */ GIR_RootConstrainSelectedInstOperands, |
| 12304 | /* 34471 */ // GIR_Coverage, 5886, |
| 12305 | /* 34471 */ GIR_EraseRootFromParent_Done, |
| 12306 | /* 34472 */ // Label 904: @34472 |
| 12307 | /* 34472 */ GIM_Reject, |
| 12308 | /* 34473 */ // Label 896: @34473 |
| 12309 | /* 34473 */ GIM_Reject, |
| 12310 | /* 34474 */ // Label 852: @34474 |
| 12311 | /* 34474 */ GIM_Reject, |
| 12312 | /* 34475 */ // Label 724: @34475 |
| 12313 | /* 34475 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 909*/ GIMT_Encode4(35076), |
| 12314 | /* 34486 */ /*GILLT_s64*//*Label 905*/ GIMT_Encode4(34526), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 12315 | /* 34506 */ /*GILLT_v8s8*//*Label 906*/ GIMT_Encode4(34721), GIMT_Encode4(0), |
| 12316 | /* 34514 */ /*GILLT_v4s16*//*Label 907*/ GIMT_Encode4(34826), GIMT_Encode4(0), |
| 12317 | /* 34522 */ /*GILLT_v2s32*//*Label 908*/ GIMT_Encode4(35021), |
| 12318 | /* 34526 */ // Label 905: @34526 |
| 12319 | /* 34526 */ GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(34720), |
| 12320 | /* 34531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12321 | /* 34535 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12322 | /* 34539 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 911*/ GIMT_Encode4(34559), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3131 // |
| 12323 | /* 34546 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2f32] }:$src |
| 12324 | /* 34546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12325 | /* 34549 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12326 | /* 34551 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12327 | /* 34553 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12328 | /* 34558 */ // GIR_Coverage, 3131, |
| 12329 | /* 34558 */ GIR_EraseRootFromParent_Done, |
| 12330 | /* 34559 */ // Label 911: @34559 |
| 12331 | /* 34559 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 912*/ GIMT_Encode4(34579), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3132 // |
| 12332 | /* 34566 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2f32] }:$src |
| 12333 | /* 34566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12334 | /* 34569 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12335 | /* 34571 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12336 | /* 34573 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12337 | /* 34578 */ // GIR_Coverage, 3132, |
| 12338 | /* 34578 */ GIR_EraseRootFromParent_Done, |
| 12339 | /* 34579 */ // Label 912: @34579 |
| 12340 | /* 34579 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 913*/ GIMT_Encode4(34599), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3136 // |
| 12341 | /* 34586 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2i32] }:$src |
| 12342 | /* 34586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12343 | /* 34589 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12344 | /* 34591 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12345 | /* 34593 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12346 | /* 34598 */ // GIR_Coverage, 3136, |
| 12347 | /* 34598 */ GIR_EraseRootFromParent_Done, |
| 12348 | /* 34599 */ // Label 913: @34599 |
| 12349 | /* 34599 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 914*/ GIMT_Encode4(34619), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3137 // |
| 12350 | /* 34606 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2i32] }:$src |
| 12351 | /* 34606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12352 | /* 34609 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12353 | /* 34611 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12354 | /* 34613 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12355 | /* 34618 */ // GIR_Coverage, 3137, |
| 12356 | /* 34618 */ GIR_EraseRootFromParent_Done, |
| 12357 | /* 34619 */ // Label 914: @34619 |
| 12358 | /* 34619 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 915*/ GIMT_Encode4(34644), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3203 // |
| 12359 | /* 34626 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src) |
| 12360 | /* 34626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 12361 | /* 34629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12362 | /* 34631 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12363 | /* 34633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12364 | /* 34636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12365 | /* 34642 */ GIR_RootConstrainSelectedInstOperands, |
| 12366 | /* 34643 */ // GIR_Coverage, 3203, |
| 12367 | /* 34643 */ GIR_EraseRootFromParent_Done, |
| 12368 | /* 34644 */ // Label 915: @34644 |
| 12369 | /* 34644 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 916*/ GIMT_Encode4(34669), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3204 // |
| 12370 | /* 34651 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) |
| 12371 | /* 34651 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 12372 | /* 34654 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12373 | /* 34656 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12374 | /* 34658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12375 | /* 34661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12376 | /* 34667 */ GIR_RootConstrainSelectedInstOperands, |
| 12377 | /* 34668 */ // GIR_Coverage, 3204, |
| 12378 | /* 34668 */ GIR_EraseRootFromParent_Done, |
| 12379 | /* 34669 */ // Label 916: @34669 |
| 12380 | /* 34669 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 917*/ GIMT_Encode4(34694), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3208 // |
| 12381 | /* 34676 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src) |
| 12382 | /* 34676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 12383 | /* 34679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12384 | /* 34681 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12385 | /* 34683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12386 | /* 34686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12387 | /* 34692 */ GIR_RootConstrainSelectedInstOperands, |
| 12388 | /* 34693 */ // GIR_Coverage, 3208, |
| 12389 | /* 34693 */ GIR_EraseRootFromParent_Done, |
| 12390 | /* 34694 */ // Label 917: @34694 |
| 12391 | /* 34694 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 918*/ GIMT_Encode4(34719), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3209 // |
| 12392 | /* 34701 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) |
| 12393 | /* 34701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 12394 | /* 34704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12395 | /* 34706 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12396 | /* 34708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12397 | /* 34711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12398 | /* 34717 */ GIR_RootConstrainSelectedInstOperands, |
| 12399 | /* 34718 */ // GIR_Coverage, 3209, |
| 12400 | /* 34718 */ GIR_EraseRootFromParent_Done, |
| 12401 | /* 34719 */ // Label 918: @34719 |
| 12402 | /* 34719 */ GIM_Reject, |
| 12403 | /* 34720 */ // Label 910: @34720 |
| 12404 | /* 34720 */ GIM_Reject, |
| 12405 | /* 34721 */ // Label 906: @34721 |
| 12406 | /* 34721 */ GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(34825), |
| 12407 | /* 34726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12408 | /* 34730 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12409 | /* 34734 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 920*/ GIMT_Encode4(34754), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3135 // |
| 12410 | /* 34741 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2f32] }:$src |
| 12411 | /* 34741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12412 | /* 34744 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12413 | /* 34746 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12414 | /* 34748 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12415 | /* 34753 */ // GIR_Coverage, 3135, |
| 12416 | /* 34753 */ GIR_EraseRootFromParent_Done, |
| 12417 | /* 34754 */ // Label 920: @34754 |
| 12418 | /* 34754 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 921*/ GIMT_Encode4(34774), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3140 // |
| 12419 | /* 34761 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2i32] }:$src |
| 12420 | /* 34761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12421 | /* 34764 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12422 | /* 34766 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12423 | /* 34768 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12424 | /* 34773 */ // GIR_Coverage, 3140, |
| 12425 | /* 34773 */ GIR_EraseRootFromParent_Done, |
| 12426 | /* 34774 */ // Label 921: @34774 |
| 12427 | /* 34774 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 922*/ GIMT_Encode4(34799), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3207 // |
| 12428 | /* 34781 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) |
| 12429 | /* 34781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 12430 | /* 34784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12431 | /* 34786 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12432 | /* 34788 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12433 | /* 34791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12434 | /* 34797 */ GIR_RootConstrainSelectedInstOperands, |
| 12435 | /* 34798 */ // GIR_Coverage, 3207, |
| 12436 | /* 34798 */ GIR_EraseRootFromParent_Done, |
| 12437 | /* 34799 */ // Label 922: @34799 |
| 12438 | /* 34799 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 923*/ GIMT_Encode4(34824), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3212 // |
| 12439 | /* 34806 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) |
| 12440 | /* 34806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 12441 | /* 34809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12442 | /* 34811 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12443 | /* 34813 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12444 | /* 34816 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12445 | /* 34822 */ GIR_RootConstrainSelectedInstOperands, |
| 12446 | /* 34823 */ // GIR_Coverage, 3212, |
| 12447 | /* 34823 */ GIR_EraseRootFromParent_Done, |
| 12448 | /* 34824 */ // Label 923: @34824 |
| 12449 | /* 34824 */ GIM_Reject, |
| 12450 | /* 34825 */ // Label 919: @34825 |
| 12451 | /* 34825 */ GIM_Reject, |
| 12452 | /* 34826 */ // Label 907: @34826 |
| 12453 | /* 34826 */ GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(35020), |
| 12454 | /* 34831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12455 | /* 34835 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12456 | /* 34839 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 925*/ GIMT_Encode4(34859), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3133 // |
| 12457 | /* 34846 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2f32] }:$src |
| 12458 | /* 34846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12459 | /* 34849 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12460 | /* 34851 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12461 | /* 34853 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12462 | /* 34858 */ // GIR_Coverage, 3133, |
| 12463 | /* 34858 */ GIR_EraseRootFromParent_Done, |
| 12464 | /* 34859 */ // Label 925: @34859 |
| 12465 | /* 34859 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 926*/ GIMT_Encode4(34879), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3134 // |
| 12466 | /* 34866 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2f32] }:$src |
| 12467 | /* 34866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12468 | /* 34869 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12469 | /* 34871 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12470 | /* 34873 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12471 | /* 34878 */ // GIR_Coverage, 3134, |
| 12472 | /* 34878 */ GIR_EraseRootFromParent_Done, |
| 12473 | /* 34879 */ // Label 926: @34879 |
| 12474 | /* 34879 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 927*/ GIMT_Encode4(34899), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3138 // |
| 12475 | /* 34886 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2i32] }:$src |
| 12476 | /* 34886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12477 | /* 34889 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12478 | /* 34891 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12479 | /* 34893 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12480 | /* 34898 */ // GIR_Coverage, 3138, |
| 12481 | /* 34898 */ GIR_EraseRootFromParent_Done, |
| 12482 | /* 34899 */ // Label 927: @34899 |
| 12483 | /* 34899 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 928*/ GIMT_Encode4(34919), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3139 // |
| 12484 | /* 34906 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2i32] }:$src |
| 12485 | /* 34906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12486 | /* 34909 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12487 | /* 34911 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12488 | /* 34913 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12489 | /* 34918 */ // GIR_Coverage, 3139, |
| 12490 | /* 34918 */ GIR_EraseRootFromParent_Done, |
| 12491 | /* 34919 */ // Label 928: @34919 |
| 12492 | /* 34919 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 929*/ GIMT_Encode4(34944), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3205 // |
| 12493 | /* 34926 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) |
| 12494 | /* 34926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 12495 | /* 34929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12496 | /* 34931 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12497 | /* 34933 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12498 | /* 34936 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12499 | /* 34942 */ GIR_RootConstrainSelectedInstOperands, |
| 12500 | /* 34943 */ // GIR_Coverage, 3205, |
| 12501 | /* 34943 */ GIR_EraseRootFromParent_Done, |
| 12502 | /* 34944 */ // Label 929: @34944 |
| 12503 | /* 34944 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 930*/ GIMT_Encode4(34969), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3206 // |
| 12504 | /* 34951 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) |
| 12505 | /* 34951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 12506 | /* 34954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12507 | /* 34956 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12508 | /* 34958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12509 | /* 34961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12510 | /* 34967 */ GIR_RootConstrainSelectedInstOperands, |
| 12511 | /* 34968 */ // GIR_Coverage, 3206, |
| 12512 | /* 34968 */ GIR_EraseRootFromParent_Done, |
| 12513 | /* 34969 */ // Label 930: @34969 |
| 12514 | /* 34969 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 931*/ GIMT_Encode4(34994), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3210 // |
| 12515 | /* 34976 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) |
| 12516 | /* 34976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 12517 | /* 34979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12518 | /* 34981 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12519 | /* 34983 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12520 | /* 34986 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12521 | /* 34992 */ GIR_RootConstrainSelectedInstOperands, |
| 12522 | /* 34993 */ // GIR_Coverage, 3210, |
| 12523 | /* 34993 */ GIR_EraseRootFromParent_Done, |
| 12524 | /* 34994 */ // Label 931: @34994 |
| 12525 | /* 34994 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 932*/ GIMT_Encode4(35019), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3211 // |
| 12526 | /* 35001 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) |
| 12527 | /* 35001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 12528 | /* 35004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12529 | /* 35006 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12530 | /* 35008 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12531 | /* 35011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12532 | /* 35017 */ GIR_RootConstrainSelectedInstOperands, |
| 12533 | /* 35018 */ // GIR_Coverage, 3211, |
| 12534 | /* 35018 */ GIR_EraseRootFromParent_Done, |
| 12535 | /* 35019 */ // Label 932: @35019 |
| 12536 | /* 35019 */ GIM_Reject, |
| 12537 | /* 35020 */ // Label 924: @35020 |
| 12538 | /* 35020 */ GIM_Reject, |
| 12539 | /* 35021 */ // Label 908: @35021 |
| 12540 | /* 35021 */ GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(35075), |
| 12541 | /* 35026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12542 | /* 35030 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12543 | /* 35034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 934*/ GIMT_Encode4(35054), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3111 // |
| 12544 | /* 35041 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v2f32] }:$src |
| 12545 | /* 35041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12546 | /* 35044 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12547 | /* 35046 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12548 | /* 35048 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12549 | /* 35053 */ // GIR_Coverage, 3111, |
| 12550 | /* 35053 */ GIR_EraseRootFromParent_Done, |
| 12551 | /* 35054 */ // Label 934: @35054 |
| 12552 | /* 35054 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 935*/ GIMT_Encode4(35074), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3112 // |
| 12553 | /* 35061 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v2i32] }:$src |
| 12554 | /* 35061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12555 | /* 35064 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12556 | /* 35066 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12557 | /* 35068 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12558 | /* 35073 */ // GIR_Coverage, 3112, |
| 12559 | /* 35073 */ GIR_EraseRootFromParent_Done, |
| 12560 | /* 35074 */ // Label 935: @35074 |
| 12561 | /* 35074 */ GIM_Reject, |
| 12562 | /* 35075 */ // Label 933: @35075 |
| 12563 | /* 35075 */ GIM_Reject, |
| 12564 | /* 35076 */ // Label 909: @35076 |
| 12565 | /* 35076 */ GIM_Reject, |
| 12566 | /* 35077 */ // Label 725: @35077 |
| 12567 | /* 35077 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 940*/ GIMT_Encode4(36418), |
| 12568 | /* 35088 */ /*GILLT_v16s8*//*Label 936*/ GIMT_Encode4(35112), GIMT_Encode4(0), |
| 12569 | /* 35096 */ /*GILLT_v8s16*//*Label 937*/ GIMT_Encode4(35363), GIMT_Encode4(0), |
| 12570 | /* 35104 */ /*GILLT_v4s32*//*Label 938*/ GIMT_Encode4(35836), |
| 12571 | /* 35108 */ /*GILLT_v2s64*//*Label 939*/ GIMT_Encode4(35945), |
| 12572 | /* 35112 */ // Label 936: @35112 |
| 12573 | /* 35112 */ GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(35216), |
| 12574 | /* 35117 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12575 | /* 35121 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12576 | /* 35125 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 942*/ GIMT_Encode4(35145), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3171 // |
| 12577 | /* 35132 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12578 | /* 35132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12579 | /* 35135 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12580 | /* 35137 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12581 | /* 35139 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12582 | /* 35144 */ // GIR_Coverage, 3171, |
| 12583 | /* 35144 */ GIR_EraseRootFromParent_Done, |
| 12584 | /* 35145 */ // Label 942: @35145 |
| 12585 | /* 35145 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 943*/ GIMT_Encode4(35165), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3176 // |
| 12586 | /* 35152 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12587 | /* 35152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12588 | /* 35155 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12589 | /* 35157 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12590 | /* 35159 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12591 | /* 35164 */ // GIR_Coverage, 3176, |
| 12592 | /* 35164 */ GIR_EraseRootFromParent_Done, |
| 12593 | /* 35165 */ // Label 943: @35165 |
| 12594 | /* 35165 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 944*/ GIMT_Encode4(35190), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3243 // |
| 12595 | /* 35172 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) |
| 12596 | /* 35172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 12597 | /* 35175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12598 | /* 35177 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12599 | /* 35179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12600 | /* 35182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12601 | /* 35188 */ GIR_RootConstrainSelectedInstOperands, |
| 12602 | /* 35189 */ // GIR_Coverage, 3243, |
| 12603 | /* 35189 */ GIR_EraseRootFromParent_Done, |
| 12604 | /* 35190 */ // Label 944: @35190 |
| 12605 | /* 35190 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 945*/ GIMT_Encode4(35215), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3248 // |
| 12606 | /* 35197 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) |
| 12607 | /* 35197 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 12608 | /* 35200 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12609 | /* 35202 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12610 | /* 35204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12611 | /* 35207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12612 | /* 35213 */ GIR_RootConstrainSelectedInstOperands, |
| 12613 | /* 35214 */ // GIR_Coverage, 3248, |
| 12614 | /* 35214 */ GIR_EraseRootFromParent_Done, |
| 12615 | /* 35215 */ // Label 945: @35215 |
| 12616 | /* 35215 */ GIM_Reject, |
| 12617 | /* 35216 */ // Label 941: @35216 |
| 12618 | /* 35216 */ GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(35362), |
| 12619 | /* 35221 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12620 | /* 35225 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12621 | /* 35229 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 947*/ GIMT_Encode4(35249), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5838 // |
| 12622 | /* 35236 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 12623 | /* 35236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12624 | /* 35239 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12625 | /* 35241 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12626 | /* 35243 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12627 | /* 35248 */ // GIR_Coverage, 5838, |
| 12628 | /* 35248 */ GIR_EraseRootFromParent_Done, |
| 12629 | /* 35249 */ // Label 947: @35249 |
| 12630 | /* 35249 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 948*/ GIMT_Encode4(35269), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5843 // |
| 12631 | /* 35256 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 12632 | /* 35256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12633 | /* 35259 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12634 | /* 35261 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12635 | /* 35263 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12636 | /* 35268 */ // GIR_Coverage, 5843, |
| 12637 | /* 35268 */ GIR_EraseRootFromParent_Done, |
| 12638 | /* 35269 */ // Label 948: @35269 |
| 12639 | /* 35269 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 949*/ GIMT_Encode4(35315), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5874 // |
| 12640 | /* 35276 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) |
| 12641 | /* 35276 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12642 | /* 35279 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12643 | /* 35283 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12644 | /* 35288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 12645 | /* 35291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12646 | /* 35293 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12647 | /* 35295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12648 | /* 35298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12649 | /* 35304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12650 | /* 35310 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12651 | /* 35313 */ GIR_RootConstrainSelectedInstOperands, |
| 12652 | /* 35314 */ // GIR_Coverage, 5874, |
| 12653 | /* 35314 */ GIR_EraseRootFromParent_Done, |
| 12654 | /* 35315 */ // Label 949: @35315 |
| 12655 | /* 35315 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 950*/ GIMT_Encode4(35361), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5879 // |
| 12656 | /* 35322 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) |
| 12657 | /* 35322 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12658 | /* 35325 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12659 | /* 35329 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12660 | /* 35334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 12661 | /* 35337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12662 | /* 35339 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12663 | /* 35341 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12664 | /* 35344 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12665 | /* 35350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12666 | /* 35356 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12667 | /* 35359 */ GIR_RootConstrainSelectedInstOperands, |
| 12668 | /* 35360 */ // GIR_Coverage, 5879, |
| 12669 | /* 35360 */ GIR_EraseRootFromParent_Done, |
| 12670 | /* 35361 */ // Label 950: @35361 |
| 12671 | /* 35361 */ GIM_Reject, |
| 12672 | /* 35362 */ // Label 946: @35362 |
| 12673 | /* 35362 */ GIM_Reject, |
| 12674 | /* 35363 */ // Label 937: @35363 |
| 12675 | /* 35363 */ GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(35557), |
| 12676 | /* 35368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12677 | /* 35372 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12678 | /* 35376 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 952*/ GIMT_Encode4(35396), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3169 // |
| 12679 | /* 35383 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12680 | /* 35383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12681 | /* 35386 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12682 | /* 35388 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12683 | /* 35390 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12684 | /* 35395 */ // GIR_Coverage, 3169, |
| 12685 | /* 35395 */ GIR_EraseRootFromParent_Done, |
| 12686 | /* 35396 */ // Label 952: @35396 |
| 12687 | /* 35396 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 953*/ GIMT_Encode4(35416), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3170 // |
| 12688 | /* 35403 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12689 | /* 35403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12690 | /* 35406 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12691 | /* 35408 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12692 | /* 35410 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12693 | /* 35415 */ // GIR_Coverage, 3170, |
| 12694 | /* 35415 */ GIR_EraseRootFromParent_Done, |
| 12695 | /* 35416 */ // Label 953: @35416 |
| 12696 | /* 35416 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 954*/ GIMT_Encode4(35436), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3174 // |
| 12697 | /* 35423 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12698 | /* 35423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12699 | /* 35426 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12700 | /* 35428 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12701 | /* 35430 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12702 | /* 35435 */ // GIR_Coverage, 3174, |
| 12703 | /* 35435 */ GIR_EraseRootFromParent_Done, |
| 12704 | /* 35436 */ // Label 954: @35436 |
| 12705 | /* 35436 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 955*/ GIMT_Encode4(35456), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3175 // |
| 12706 | /* 35443 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12707 | /* 35443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12708 | /* 35446 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12709 | /* 35448 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12710 | /* 35450 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12711 | /* 35455 */ // GIR_Coverage, 3175, |
| 12712 | /* 35455 */ GIR_EraseRootFromParent_Done, |
| 12713 | /* 35456 */ // Label 955: @35456 |
| 12714 | /* 35456 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 956*/ GIMT_Encode4(35481), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3241 // |
| 12715 | /* 35463 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) |
| 12716 | /* 35463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12717 | /* 35466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12718 | /* 35468 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12719 | /* 35470 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12720 | /* 35473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12721 | /* 35479 */ GIR_RootConstrainSelectedInstOperands, |
| 12722 | /* 35480 */ // GIR_Coverage, 3241, |
| 12723 | /* 35480 */ GIR_EraseRootFromParent_Done, |
| 12724 | /* 35481 */ // Label 956: @35481 |
| 12725 | /* 35481 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 957*/ GIMT_Encode4(35506), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3242 // |
| 12726 | /* 35488 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) |
| 12727 | /* 35488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12728 | /* 35491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12729 | /* 35493 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12730 | /* 35495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12731 | /* 35498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12732 | /* 35504 */ GIR_RootConstrainSelectedInstOperands, |
| 12733 | /* 35505 */ // GIR_Coverage, 3242, |
| 12734 | /* 35505 */ GIR_EraseRootFromParent_Done, |
| 12735 | /* 35506 */ // Label 957: @35506 |
| 12736 | /* 35506 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 958*/ GIMT_Encode4(35531), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3246 // |
| 12737 | /* 35513 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) |
| 12738 | /* 35513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12739 | /* 35516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12740 | /* 35518 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12741 | /* 35520 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12742 | /* 35523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12743 | /* 35529 */ GIR_RootConstrainSelectedInstOperands, |
| 12744 | /* 35530 */ // GIR_Coverage, 3246, |
| 12745 | /* 35530 */ GIR_EraseRootFromParent_Done, |
| 12746 | /* 35531 */ // Label 958: @35531 |
| 12747 | /* 35531 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 959*/ GIMT_Encode4(35556), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3247 // |
| 12748 | /* 35538 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) |
| 12749 | /* 35538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12750 | /* 35541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12751 | /* 35543 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12752 | /* 35545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12753 | /* 35548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12754 | /* 35554 */ GIR_RootConstrainSelectedInstOperands, |
| 12755 | /* 35555 */ // GIR_Coverage, 3247, |
| 12756 | /* 35555 */ GIR_EraseRootFromParent_Done, |
| 12757 | /* 35556 */ // Label 959: @35556 |
| 12758 | /* 35556 */ GIM_Reject, |
| 12759 | /* 35557 */ // Label 951: @35557 |
| 12760 | /* 35557 */ GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(35835), |
| 12761 | /* 35562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12762 | /* 35566 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12763 | /* 35570 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 961*/ GIMT_Encode4(35590), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5836 // |
| 12764 | /* 35577 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 12765 | /* 35577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12766 | /* 35580 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12767 | /* 35582 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12768 | /* 35584 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12769 | /* 35589 */ // GIR_Coverage, 5836, |
| 12770 | /* 35589 */ GIR_EraseRootFromParent_Done, |
| 12771 | /* 35590 */ // Label 961: @35590 |
| 12772 | /* 35590 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 962*/ GIMT_Encode4(35610), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5837 // |
| 12773 | /* 35597 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 12774 | /* 35597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12775 | /* 35600 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12776 | /* 35602 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12777 | /* 35604 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12778 | /* 35609 */ // GIR_Coverage, 5837, |
| 12779 | /* 35609 */ GIR_EraseRootFromParent_Done, |
| 12780 | /* 35610 */ // Label 962: @35610 |
| 12781 | /* 35610 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 963*/ GIMT_Encode4(35630), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5841 // |
| 12782 | /* 35617 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 12783 | /* 35617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12784 | /* 35620 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12785 | /* 35622 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12786 | /* 35624 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12787 | /* 35629 */ // GIR_Coverage, 5841, |
| 12788 | /* 35629 */ GIR_EraseRootFromParent_Done, |
| 12789 | /* 35630 */ // Label 963: @35630 |
| 12790 | /* 35630 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 964*/ GIMT_Encode4(35650), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5842 // |
| 12791 | /* 35637 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 12792 | /* 35637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12793 | /* 35640 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12794 | /* 35642 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12795 | /* 35644 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12796 | /* 35649 */ // GIR_Coverage, 5842, |
| 12797 | /* 35649 */ GIR_EraseRootFromParent_Done, |
| 12798 | /* 35650 */ // Label 964: @35650 |
| 12799 | /* 35650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 965*/ GIMT_Encode4(35696), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5872 // |
| 12800 | /* 35657 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) |
| 12801 | /* 35657 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12802 | /* 35660 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12803 | /* 35664 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12804 | /* 35669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12805 | /* 35672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12806 | /* 35674 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12807 | /* 35676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12808 | /* 35679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12809 | /* 35685 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12810 | /* 35691 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12811 | /* 35694 */ GIR_RootConstrainSelectedInstOperands, |
| 12812 | /* 35695 */ // GIR_Coverage, 5872, |
| 12813 | /* 35695 */ GIR_EraseRootFromParent_Done, |
| 12814 | /* 35696 */ // Label 965: @35696 |
| 12815 | /* 35696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 966*/ GIMT_Encode4(35742), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5873 // |
| 12816 | /* 35703 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) |
| 12817 | /* 35703 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12818 | /* 35706 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12819 | /* 35710 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12820 | /* 35715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12821 | /* 35718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12822 | /* 35720 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12823 | /* 35722 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12824 | /* 35725 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12825 | /* 35731 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12826 | /* 35737 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12827 | /* 35740 */ GIR_RootConstrainSelectedInstOperands, |
| 12828 | /* 35741 */ // GIR_Coverage, 5873, |
| 12829 | /* 35741 */ GIR_EraseRootFromParent_Done, |
| 12830 | /* 35742 */ // Label 966: @35742 |
| 12831 | /* 35742 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 967*/ GIMT_Encode4(35788), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5877 // |
| 12832 | /* 35749 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) |
| 12833 | /* 35749 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12834 | /* 35752 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12835 | /* 35756 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12836 | /* 35761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12837 | /* 35764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12838 | /* 35766 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12839 | /* 35768 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12840 | /* 35771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12841 | /* 35777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12842 | /* 35783 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12843 | /* 35786 */ GIR_RootConstrainSelectedInstOperands, |
| 12844 | /* 35787 */ // GIR_Coverage, 5877, |
| 12845 | /* 35787 */ GIR_EraseRootFromParent_Done, |
| 12846 | /* 35788 */ // Label 967: @35788 |
| 12847 | /* 35788 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 968*/ GIMT_Encode4(35834), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5878 // |
| 12848 | /* 35795 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 12849 | /* 35795 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12850 | /* 35798 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12851 | /* 35802 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12852 | /* 35807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12853 | /* 35810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12854 | /* 35812 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12855 | /* 35814 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12856 | /* 35817 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12857 | /* 35823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12858 | /* 35829 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12859 | /* 35832 */ GIR_RootConstrainSelectedInstOperands, |
| 12860 | /* 35833 */ // GIR_Coverage, 5878, |
| 12861 | /* 35833 */ GIR_EraseRootFromParent_Done, |
| 12862 | /* 35834 */ // Label 968: @35834 |
| 12863 | /* 35834 */ GIM_Reject, |
| 12864 | /* 35835 */ // Label 960: @35835 |
| 12865 | /* 35835 */ GIM_Reject, |
| 12866 | /* 35836 */ // Label 938: @35836 |
| 12867 | /* 35836 */ GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(35890), |
| 12868 | /* 35841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12869 | /* 35845 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12870 | /* 35849 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 970*/ GIMT_Encode4(35869), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3117 // |
| 12871 | /* 35856 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12872 | /* 35856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12873 | /* 35859 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12874 | /* 35861 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12875 | /* 35863 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12876 | /* 35868 */ // GIR_Coverage, 3117, |
| 12877 | /* 35868 */ GIR_EraseRootFromParent_Done, |
| 12878 | /* 35869 */ // Label 970: @35869 |
| 12879 | /* 35869 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 971*/ GIMT_Encode4(35889), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3118 // |
| 12880 | /* 35876 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12881 | /* 35876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12882 | /* 35879 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12883 | /* 35881 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12884 | /* 35883 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12885 | /* 35888 */ // GIR_Coverage, 3118, |
| 12886 | /* 35888 */ GIR_EraseRootFromParent_Done, |
| 12887 | /* 35889 */ // Label 971: @35889 |
| 12888 | /* 35889 */ GIM_Reject, |
| 12889 | /* 35890 */ // Label 969: @35890 |
| 12890 | /* 35890 */ GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(35944), |
| 12891 | /* 35895 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12892 | /* 35899 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12893 | /* 35903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 973*/ GIMT_Encode4(35923), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5820 // |
| 12894 | /* 35910 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 12895 | /* 35910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12896 | /* 35913 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12897 | /* 35915 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12898 | /* 35917 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12899 | /* 35922 */ // GIR_Coverage, 5820, |
| 12900 | /* 35922 */ GIR_EraseRootFromParent_Done, |
| 12901 | /* 35923 */ // Label 973: @35923 |
| 12902 | /* 35923 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 974*/ GIMT_Encode4(35943), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5821 // |
| 12903 | /* 35930 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 12904 | /* 35930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12905 | /* 35933 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12906 | /* 35935 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12907 | /* 35937 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12908 | /* 35942 */ // GIR_Coverage, 5821, |
| 12909 | /* 35942 */ GIR_EraseRootFromParent_Done, |
| 12910 | /* 35943 */ // Label 974: @35943 |
| 12911 | /* 35943 */ GIM_Reject, |
| 12912 | /* 35944 */ // Label 972: @35944 |
| 12913 | /* 35944 */ GIM_Reject, |
| 12914 | /* 35945 */ // Label 939: @35945 |
| 12915 | /* 35945 */ GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(36139), |
| 12916 | /* 35950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12917 | /* 35954 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12918 | /* 35958 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 976*/ GIMT_Encode4(35978), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3167 // |
| 12919 | /* 35965 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12920 | /* 35965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12921 | /* 35968 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12922 | /* 35970 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12923 | /* 35972 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12924 | /* 35977 */ // GIR_Coverage, 3167, |
| 12925 | /* 35977 */ GIR_EraseRootFromParent_Done, |
| 12926 | /* 35978 */ // Label 976: @35978 |
| 12927 | /* 35978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 977*/ GIMT_Encode4(35998), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3168 // |
| 12928 | /* 35985 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12929 | /* 35985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12930 | /* 35988 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12931 | /* 35990 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12932 | /* 35992 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12933 | /* 35997 */ // GIR_Coverage, 3168, |
| 12934 | /* 35997 */ GIR_EraseRootFromParent_Done, |
| 12935 | /* 35998 */ // Label 977: @35998 |
| 12936 | /* 35998 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 978*/ GIMT_Encode4(36018), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3172 // |
| 12937 | /* 36005 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12938 | /* 36005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12939 | /* 36008 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12940 | /* 36010 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12941 | /* 36012 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12942 | /* 36017 */ // GIR_Coverage, 3172, |
| 12943 | /* 36017 */ GIR_EraseRootFromParent_Done, |
| 12944 | /* 36018 */ // Label 978: @36018 |
| 12945 | /* 36018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 979*/ GIMT_Encode4(36038), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3173 // |
| 12946 | /* 36025 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12947 | /* 36025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12948 | /* 36028 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12949 | /* 36030 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12950 | /* 36032 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12951 | /* 36037 */ // GIR_Coverage, 3173, |
| 12952 | /* 36037 */ GIR_EraseRootFromParent_Done, |
| 12953 | /* 36038 */ // Label 979: @36038 |
| 12954 | /* 36038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 980*/ GIMT_Encode4(36063), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3239 // |
| 12955 | /* 36045 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) |
| 12956 | /* 36045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 12957 | /* 36048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12958 | /* 36050 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12959 | /* 36052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12960 | /* 36055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12961 | /* 36061 */ GIR_RootConstrainSelectedInstOperands, |
| 12962 | /* 36062 */ // GIR_Coverage, 3239, |
| 12963 | /* 36062 */ GIR_EraseRootFromParent_Done, |
| 12964 | /* 36063 */ // Label 980: @36063 |
| 12965 | /* 36063 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 981*/ GIMT_Encode4(36088), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3240 // |
| 12966 | /* 36070 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) |
| 12967 | /* 36070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 12968 | /* 36073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12969 | /* 36075 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12970 | /* 36077 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12971 | /* 36080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12972 | /* 36086 */ GIR_RootConstrainSelectedInstOperands, |
| 12973 | /* 36087 */ // GIR_Coverage, 3240, |
| 12974 | /* 36087 */ GIR_EraseRootFromParent_Done, |
| 12975 | /* 36088 */ // Label 981: @36088 |
| 12976 | /* 36088 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 982*/ GIMT_Encode4(36113), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3244 // |
| 12977 | /* 36095 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) |
| 12978 | /* 36095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 12979 | /* 36098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12980 | /* 36100 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12981 | /* 36102 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12982 | /* 36105 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12983 | /* 36111 */ GIR_RootConstrainSelectedInstOperands, |
| 12984 | /* 36112 */ // GIR_Coverage, 3244, |
| 12985 | /* 36112 */ GIR_EraseRootFromParent_Done, |
| 12986 | /* 36113 */ // Label 982: @36113 |
| 12987 | /* 36113 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 983*/ GIMT_Encode4(36138), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3245 // |
| 12988 | /* 36120 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) |
| 12989 | /* 36120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 12990 | /* 36123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12991 | /* 36125 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12992 | /* 36127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12993 | /* 36130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12994 | /* 36136 */ GIR_RootConstrainSelectedInstOperands, |
| 12995 | /* 36137 */ // GIR_Coverage, 3245, |
| 12996 | /* 36137 */ GIR_EraseRootFromParent_Done, |
| 12997 | /* 36138 */ // Label 983: @36138 |
| 12998 | /* 36138 */ GIM_Reject, |
| 12999 | /* 36139 */ // Label 975: @36139 |
| 13000 | /* 36139 */ GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(36417), |
| 13001 | /* 36144 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13002 | /* 36148 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13003 | /* 36152 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 985*/ GIMT_Encode4(36172), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5834 // |
| 13004 | /* 36159 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 13005 | /* 36159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13006 | /* 36162 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13007 | /* 36164 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13008 | /* 36166 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13009 | /* 36171 */ // GIR_Coverage, 5834, |
| 13010 | /* 36171 */ GIR_EraseRootFromParent_Done, |
| 13011 | /* 36172 */ // Label 985: @36172 |
| 13012 | /* 36172 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 986*/ GIMT_Encode4(36192), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5835 // |
| 13013 | /* 36179 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 13014 | /* 36179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13015 | /* 36182 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13016 | /* 36184 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13017 | /* 36186 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13018 | /* 36191 */ // GIR_Coverage, 5835, |
| 13019 | /* 36191 */ GIR_EraseRootFromParent_Done, |
| 13020 | /* 36192 */ // Label 986: @36192 |
| 13021 | /* 36192 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 987*/ GIMT_Encode4(36212), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5839 // |
| 13022 | /* 36199 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 13023 | /* 36199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13024 | /* 36202 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13025 | /* 36204 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13026 | /* 36206 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13027 | /* 36211 */ // GIR_Coverage, 5839, |
| 13028 | /* 36211 */ GIR_EraseRootFromParent_Done, |
| 13029 | /* 36212 */ // Label 987: @36212 |
| 13030 | /* 36212 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 988*/ GIMT_Encode4(36232), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5840 // |
| 13031 | /* 36219 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 13032 | /* 36219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13033 | /* 36222 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13034 | /* 36224 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13035 | /* 36226 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13036 | /* 36231 */ // GIR_Coverage, 5840, |
| 13037 | /* 36231 */ GIR_EraseRootFromParent_Done, |
| 13038 | /* 36232 */ // Label 988: @36232 |
| 13039 | /* 36232 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 989*/ GIMT_Encode4(36278), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5870 // |
| 13040 | /* 36239 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) |
| 13041 | /* 36239 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13042 | /* 36242 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13043 | /* 36246 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13044 | /* 36251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13045 | /* 36254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13046 | /* 36256 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13047 | /* 36258 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13048 | /* 36261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13049 | /* 36267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13050 | /* 36273 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13051 | /* 36276 */ GIR_RootConstrainSelectedInstOperands, |
| 13052 | /* 36277 */ // GIR_Coverage, 5870, |
| 13053 | /* 36277 */ GIR_EraseRootFromParent_Done, |
| 13054 | /* 36278 */ // Label 989: @36278 |
| 13055 | /* 36278 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 990*/ GIMT_Encode4(36324), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5871 // |
| 13056 | /* 36285 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) |
| 13057 | /* 36285 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13058 | /* 36288 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13059 | /* 36292 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13060 | /* 36297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13061 | /* 36300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13062 | /* 36302 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13063 | /* 36304 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13064 | /* 36307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13065 | /* 36313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13066 | /* 36319 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13067 | /* 36322 */ GIR_RootConstrainSelectedInstOperands, |
| 13068 | /* 36323 */ // GIR_Coverage, 5871, |
| 13069 | /* 36323 */ GIR_EraseRootFromParent_Done, |
| 13070 | /* 36324 */ // Label 990: @36324 |
| 13071 | /* 36324 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 991*/ GIMT_Encode4(36370), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5875 // |
| 13072 | /* 36331 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) |
| 13073 | /* 36331 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13074 | /* 36334 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13075 | /* 36338 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13076 | /* 36343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13077 | /* 36346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13078 | /* 36348 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13079 | /* 36350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13080 | /* 36353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13081 | /* 36359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13082 | /* 36365 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13083 | /* 36368 */ GIR_RootConstrainSelectedInstOperands, |
| 13084 | /* 36369 */ // GIR_Coverage, 5875, |
| 13085 | /* 36369 */ GIR_EraseRootFromParent_Done, |
| 13086 | /* 36370 */ // Label 991: @36370 |
| 13087 | /* 36370 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 992*/ GIMT_Encode4(36416), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5876 // |
| 13088 | /* 36377 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) |
| 13089 | /* 36377 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13090 | /* 36380 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13091 | /* 36384 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13092 | /* 36389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13093 | /* 36392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13094 | /* 36394 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13095 | /* 36396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13096 | /* 36399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13097 | /* 36405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13098 | /* 36411 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13099 | /* 36414 */ GIR_RootConstrainSelectedInstOperands, |
| 13100 | /* 36415 */ // GIR_Coverage, 5876, |
| 13101 | /* 36415 */ GIR_EraseRootFromParent_Done, |
| 13102 | /* 36416 */ // Label 992: @36416 |
| 13103 | /* 36416 */ GIM_Reject, |
| 13104 | /* 36417 */ // Label 984: @36417 |
| 13105 | /* 36417 */ GIM_Reject, |
| 13106 | /* 36418 */ // Label 940: @36418 |
| 13107 | /* 36418 */ GIM_Reject, |
| 13108 | /* 36419 */ // Label 726: @36419 |
| 13109 | /* 36419 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 997*/ GIMT_Encode4(37760), |
| 13110 | /* 36430 */ /*GILLT_v16s8*//*Label 993*/ GIMT_Encode4(36454), GIMT_Encode4(0), |
| 13111 | /* 36438 */ /*GILLT_v8s16*//*Label 994*/ GIMT_Encode4(36705), GIMT_Encode4(0), |
| 13112 | /* 36446 */ /*GILLT_v4s32*//*Label 995*/ GIMT_Encode4(37178), |
| 13113 | /* 36450 */ /*GILLT_v2s64*//*Label 996*/ GIMT_Encode4(37651), |
| 13114 | /* 36454 */ // Label 993: @36454 |
| 13115 | /* 36454 */ GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(36558), |
| 13116 | /* 36459 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13117 | /* 36463 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13118 | /* 36467 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 999*/ GIMT_Encode4(36487), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3161 // |
| 13119 | /* 36474 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2f64] }:$src |
| 13120 | /* 36474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13121 | /* 36477 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13122 | /* 36479 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13123 | /* 36481 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13124 | /* 36486 */ // GIR_Coverage, 3161, |
| 13125 | /* 36486 */ GIR_EraseRootFromParent_Done, |
| 13126 | /* 36487 */ // Label 999: @36487 |
| 13127 | /* 36487 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1000*/ GIMT_Encode4(36507), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3166 // |
| 13128 | /* 36494 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2i64] }:$src |
| 13129 | /* 36494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13130 | /* 36497 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13131 | /* 36499 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13132 | /* 36501 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13133 | /* 36506 */ // GIR_Coverage, 3166, |
| 13134 | /* 36506 */ GIR_EraseRootFromParent_Done, |
| 13135 | /* 36507 */ // Label 1000: @36507 |
| 13136 | /* 36507 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1001*/ GIMT_Encode4(36532), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3233 // |
| 13137 | /* 36514 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) |
| 13138 | /* 36514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 13139 | /* 36517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13140 | /* 36519 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13141 | /* 36521 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13142 | /* 36524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13143 | /* 36530 */ GIR_RootConstrainSelectedInstOperands, |
| 13144 | /* 36531 */ // GIR_Coverage, 3233, |
| 13145 | /* 36531 */ GIR_EraseRootFromParent_Done, |
| 13146 | /* 36532 */ // Label 1001: @36532 |
| 13147 | /* 36532 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1002*/ GIMT_Encode4(36557), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3238 // |
| 13148 | /* 36539 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) |
| 13149 | /* 36539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 13150 | /* 36542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13151 | /* 36544 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13152 | /* 36546 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13153 | /* 36549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13154 | /* 36555 */ GIR_RootConstrainSelectedInstOperands, |
| 13155 | /* 36556 */ // GIR_Coverage, 3238, |
| 13156 | /* 36556 */ GIR_EraseRootFromParent_Done, |
| 13157 | /* 36557 */ // Label 1002: @36557 |
| 13158 | /* 36557 */ GIM_Reject, |
| 13159 | /* 36558 */ // Label 998: @36558 |
| 13160 | /* 36558 */ GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(36704), |
| 13161 | /* 36563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13162 | /* 36567 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13163 | /* 36571 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1004*/ GIMT_Encode4(36591), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5828 // |
| 13164 | /* 36578 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 13165 | /* 36578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13166 | /* 36581 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13167 | /* 36583 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13168 | /* 36585 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13169 | /* 36590 */ // GIR_Coverage, 5828, |
| 13170 | /* 36590 */ GIR_EraseRootFromParent_Done, |
| 13171 | /* 36591 */ // Label 1004: @36591 |
| 13172 | /* 36591 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1005*/ GIMT_Encode4(36611), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5833 // |
| 13173 | /* 36598 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 13174 | /* 36598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13175 | /* 36601 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13176 | /* 36603 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13177 | /* 36605 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13178 | /* 36610 */ // GIR_Coverage, 5833, |
| 13179 | /* 36610 */ GIR_EraseRootFromParent_Done, |
| 13180 | /* 36611 */ // Label 1005: @36611 |
| 13181 | /* 36611 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1006*/ GIMT_Encode4(36657), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5864 // |
| 13182 | /* 36618 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) |
| 13183 | /* 36618 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13184 | /* 36621 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13185 | /* 36625 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13186 | /* 36630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 13187 | /* 36633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13188 | /* 36635 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13189 | /* 36637 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13190 | /* 36640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13191 | /* 36646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13192 | /* 36652 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13193 | /* 36655 */ GIR_RootConstrainSelectedInstOperands, |
| 13194 | /* 36656 */ // GIR_Coverage, 5864, |
| 13195 | /* 36656 */ GIR_EraseRootFromParent_Done, |
| 13196 | /* 36657 */ // Label 1006: @36657 |
| 13197 | /* 36657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1007*/ GIMT_Encode4(36703), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5869 // |
| 13198 | /* 36664 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) |
| 13199 | /* 36664 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13200 | /* 36667 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13201 | /* 36671 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13202 | /* 36676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 13203 | /* 36679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13204 | /* 36681 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13205 | /* 36683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13206 | /* 36686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13207 | /* 36692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13208 | /* 36698 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13209 | /* 36701 */ GIR_RootConstrainSelectedInstOperands, |
| 13210 | /* 36702 */ // GIR_Coverage, 5869, |
| 13211 | /* 36702 */ GIR_EraseRootFromParent_Done, |
| 13212 | /* 36703 */ // Label 1007: @36703 |
| 13213 | /* 36703 */ GIM_Reject, |
| 13214 | /* 36704 */ // Label 1003: @36704 |
| 13215 | /* 36704 */ GIM_Reject, |
| 13216 | /* 36705 */ // Label 994: @36705 |
| 13217 | /* 36705 */ GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(36899), |
| 13218 | /* 36710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13219 | /* 36714 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13220 | /* 36718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1009*/ GIMT_Encode4(36738), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3159 // |
| 13221 | /* 36725 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2f64] }:$src |
| 13222 | /* 36725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13223 | /* 36728 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13224 | /* 36730 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13225 | /* 36732 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13226 | /* 36737 */ // GIR_Coverage, 3159, |
| 13227 | /* 36737 */ GIR_EraseRootFromParent_Done, |
| 13228 | /* 36738 */ // Label 1009: @36738 |
| 13229 | /* 36738 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1010*/ GIMT_Encode4(36758), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3160 // |
| 13230 | /* 36745 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2f64] }:$src |
| 13231 | /* 36745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13232 | /* 36748 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13233 | /* 36750 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13234 | /* 36752 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13235 | /* 36757 */ // GIR_Coverage, 3160, |
| 13236 | /* 36757 */ GIR_EraseRootFromParent_Done, |
| 13237 | /* 36758 */ // Label 1010: @36758 |
| 13238 | /* 36758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1011*/ GIMT_Encode4(36778), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3164 // |
| 13239 | /* 36765 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2i64] }:$src |
| 13240 | /* 36765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13241 | /* 36768 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13242 | /* 36770 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13243 | /* 36772 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13244 | /* 36777 */ // GIR_Coverage, 3164, |
| 13245 | /* 36777 */ GIR_EraseRootFromParent_Done, |
| 13246 | /* 36778 */ // Label 1011: @36778 |
| 13247 | /* 36778 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1012*/ GIMT_Encode4(36798), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3165 // |
| 13248 | /* 36785 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2i64] }:$src |
| 13249 | /* 36785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13250 | /* 36788 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13251 | /* 36790 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13252 | /* 36792 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13253 | /* 36797 */ // GIR_Coverage, 3165, |
| 13254 | /* 36797 */ GIR_EraseRootFromParent_Done, |
| 13255 | /* 36798 */ // Label 1012: @36798 |
| 13256 | /* 36798 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1013*/ GIMT_Encode4(36823), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3231 // |
| 13257 | /* 36805 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) |
| 13258 | /* 36805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 13259 | /* 36808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13260 | /* 36810 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13261 | /* 36812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13262 | /* 36815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13263 | /* 36821 */ GIR_RootConstrainSelectedInstOperands, |
| 13264 | /* 36822 */ // GIR_Coverage, 3231, |
| 13265 | /* 36822 */ GIR_EraseRootFromParent_Done, |
| 13266 | /* 36823 */ // Label 1013: @36823 |
| 13267 | /* 36823 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1014*/ GIMT_Encode4(36848), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3232 // |
| 13268 | /* 36830 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) |
| 13269 | /* 36830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 13270 | /* 36833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13271 | /* 36835 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13272 | /* 36837 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13273 | /* 36840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13274 | /* 36846 */ GIR_RootConstrainSelectedInstOperands, |
| 13275 | /* 36847 */ // GIR_Coverage, 3232, |
| 13276 | /* 36847 */ GIR_EraseRootFromParent_Done, |
| 13277 | /* 36848 */ // Label 1014: @36848 |
| 13278 | /* 36848 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1015*/ GIMT_Encode4(36873), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3236 // |
| 13279 | /* 36855 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) |
| 13280 | /* 36855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 13281 | /* 36858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13282 | /* 36860 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13283 | /* 36862 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13284 | /* 36865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13285 | /* 36871 */ GIR_RootConstrainSelectedInstOperands, |
| 13286 | /* 36872 */ // GIR_Coverage, 3236, |
| 13287 | /* 36872 */ GIR_EraseRootFromParent_Done, |
| 13288 | /* 36873 */ // Label 1015: @36873 |
| 13289 | /* 36873 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1016*/ GIMT_Encode4(36898), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3237 // |
| 13290 | /* 36880 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) |
| 13291 | /* 36880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 13292 | /* 36883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13293 | /* 36885 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13294 | /* 36887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13295 | /* 36890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13296 | /* 36896 */ GIR_RootConstrainSelectedInstOperands, |
| 13297 | /* 36897 */ // GIR_Coverage, 3237, |
| 13298 | /* 36897 */ GIR_EraseRootFromParent_Done, |
| 13299 | /* 36898 */ // Label 1016: @36898 |
| 13300 | /* 36898 */ GIM_Reject, |
| 13301 | /* 36899 */ // Label 1008: @36899 |
| 13302 | /* 36899 */ GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(37177), |
| 13303 | /* 36904 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13304 | /* 36908 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13305 | /* 36912 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1018*/ GIMT_Encode4(36932), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5826 // |
| 13306 | /* 36919 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 13307 | /* 36919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13308 | /* 36922 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13309 | /* 36924 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13310 | /* 36926 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13311 | /* 36931 */ // GIR_Coverage, 5826, |
| 13312 | /* 36931 */ GIR_EraseRootFromParent_Done, |
| 13313 | /* 36932 */ // Label 1018: @36932 |
| 13314 | /* 36932 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1019*/ GIMT_Encode4(36952), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5827 // |
| 13315 | /* 36939 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 13316 | /* 36939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13317 | /* 36942 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13318 | /* 36944 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13319 | /* 36946 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13320 | /* 36951 */ // GIR_Coverage, 5827, |
| 13321 | /* 36951 */ GIR_EraseRootFromParent_Done, |
| 13322 | /* 36952 */ // Label 1019: @36952 |
| 13323 | /* 36952 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1020*/ GIMT_Encode4(36972), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5831 // |
| 13324 | /* 36959 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 13325 | /* 36959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13326 | /* 36962 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13327 | /* 36964 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13328 | /* 36966 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13329 | /* 36971 */ // GIR_Coverage, 5831, |
| 13330 | /* 36971 */ GIR_EraseRootFromParent_Done, |
| 13331 | /* 36972 */ // Label 1020: @36972 |
| 13332 | /* 36972 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1021*/ GIMT_Encode4(36992), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5832 // |
| 13333 | /* 36979 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 13334 | /* 36979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13335 | /* 36982 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13336 | /* 36984 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13337 | /* 36986 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13338 | /* 36991 */ // GIR_Coverage, 5832, |
| 13339 | /* 36991 */ GIR_EraseRootFromParent_Done, |
| 13340 | /* 36992 */ // Label 1021: @36992 |
| 13341 | /* 36992 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1022*/ GIMT_Encode4(37038), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5862 // |
| 13342 | /* 36999 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) |
| 13343 | /* 36999 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13344 | /* 37002 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13345 | /* 37006 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13346 | /* 37011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 13347 | /* 37014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13348 | /* 37016 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13349 | /* 37018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13350 | /* 37021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13351 | /* 37027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13352 | /* 37033 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13353 | /* 37036 */ GIR_RootConstrainSelectedInstOperands, |
| 13354 | /* 37037 */ // GIR_Coverage, 5862, |
| 13355 | /* 37037 */ GIR_EraseRootFromParent_Done, |
| 13356 | /* 37038 */ // Label 1022: @37038 |
| 13357 | /* 37038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1023*/ GIMT_Encode4(37084), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5863 // |
| 13358 | /* 37045 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) |
| 13359 | /* 37045 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13360 | /* 37048 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13361 | /* 37052 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13362 | /* 37057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 13363 | /* 37060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13364 | /* 37062 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13365 | /* 37064 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13366 | /* 37067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13367 | /* 37073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13368 | /* 37079 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13369 | /* 37082 */ GIR_RootConstrainSelectedInstOperands, |
| 13370 | /* 37083 */ // GIR_Coverage, 5863, |
| 13371 | /* 37083 */ GIR_EraseRootFromParent_Done, |
| 13372 | /* 37084 */ // Label 1023: @37084 |
| 13373 | /* 37084 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1024*/ GIMT_Encode4(37130), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5867 // |
| 13374 | /* 37091 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) |
| 13375 | /* 37091 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13376 | /* 37094 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13377 | /* 37098 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13378 | /* 37103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 13379 | /* 37106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13380 | /* 37108 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13381 | /* 37110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13382 | /* 37113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13383 | /* 37119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13384 | /* 37125 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13385 | /* 37128 */ GIR_RootConstrainSelectedInstOperands, |
| 13386 | /* 37129 */ // GIR_Coverage, 5867, |
| 13387 | /* 37129 */ GIR_EraseRootFromParent_Done, |
| 13388 | /* 37130 */ // Label 1024: @37130 |
| 13389 | /* 37130 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1025*/ GIMT_Encode4(37176), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5868 // |
| 13390 | /* 37137 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) |
| 13391 | /* 37137 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13392 | /* 37140 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13393 | /* 37144 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13394 | /* 37149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 13395 | /* 37152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13396 | /* 37154 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13397 | /* 37156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13398 | /* 37159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13399 | /* 37165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13400 | /* 37171 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13401 | /* 37174 */ GIR_RootConstrainSelectedInstOperands, |
| 13402 | /* 37175 */ // GIR_Coverage, 5868, |
| 13403 | /* 37175 */ GIR_EraseRootFromParent_Done, |
| 13404 | /* 37176 */ // Label 1025: @37176 |
| 13405 | /* 37176 */ GIM_Reject, |
| 13406 | /* 37177 */ // Label 1017: @37177 |
| 13407 | /* 37177 */ GIM_Reject, |
| 13408 | /* 37178 */ // Label 995: @37178 |
| 13409 | /* 37178 */ GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(37372), |
| 13410 | /* 37183 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13411 | /* 37187 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13412 | /* 37191 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1027*/ GIMT_Encode4(37211), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3157 // |
| 13413 | /* 37198 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2f64] }:$src |
| 13414 | /* 37198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13415 | /* 37201 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13416 | /* 37203 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13417 | /* 37205 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13418 | /* 37210 */ // GIR_Coverage, 3157, |
| 13419 | /* 37210 */ GIR_EraseRootFromParent_Done, |
| 13420 | /* 37211 */ // Label 1027: @37211 |
| 13421 | /* 37211 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1028*/ GIMT_Encode4(37231), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3158 // |
| 13422 | /* 37218 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2f64] }:$src |
| 13423 | /* 37218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13424 | /* 37221 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13425 | /* 37223 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13426 | /* 37225 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13427 | /* 37230 */ // GIR_Coverage, 3158, |
| 13428 | /* 37230 */ GIR_EraseRootFromParent_Done, |
| 13429 | /* 37231 */ // Label 1028: @37231 |
| 13430 | /* 37231 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1029*/ GIMT_Encode4(37251), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3162 // |
| 13431 | /* 37238 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2i64] }:$src |
| 13432 | /* 37238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13433 | /* 37241 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13434 | /* 37243 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13435 | /* 37245 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13436 | /* 37250 */ // GIR_Coverage, 3162, |
| 13437 | /* 37250 */ GIR_EraseRootFromParent_Done, |
| 13438 | /* 37251 */ // Label 1029: @37251 |
| 13439 | /* 37251 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1030*/ GIMT_Encode4(37271), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3163 // |
| 13440 | /* 37258 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2i64] }:$src |
| 13441 | /* 37258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13442 | /* 37261 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13443 | /* 37263 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13444 | /* 37265 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13445 | /* 37270 */ // GIR_Coverage, 3163, |
| 13446 | /* 37270 */ GIR_EraseRootFromParent_Done, |
| 13447 | /* 37271 */ // Label 1030: @37271 |
| 13448 | /* 37271 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1031*/ GIMT_Encode4(37296), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3229 // |
| 13449 | /* 37278 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) |
| 13450 | /* 37278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 13451 | /* 37281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13452 | /* 37283 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13453 | /* 37285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13454 | /* 37288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13455 | /* 37294 */ GIR_RootConstrainSelectedInstOperands, |
| 13456 | /* 37295 */ // GIR_Coverage, 3229, |
| 13457 | /* 37295 */ GIR_EraseRootFromParent_Done, |
| 13458 | /* 37296 */ // Label 1031: @37296 |
| 13459 | /* 37296 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1032*/ GIMT_Encode4(37321), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3230 // |
| 13460 | /* 37303 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) |
| 13461 | /* 37303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 13462 | /* 37306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13463 | /* 37308 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13464 | /* 37310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13465 | /* 37313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13466 | /* 37319 */ GIR_RootConstrainSelectedInstOperands, |
| 13467 | /* 37320 */ // GIR_Coverage, 3230, |
| 13468 | /* 37320 */ GIR_EraseRootFromParent_Done, |
| 13469 | /* 37321 */ // Label 1032: @37321 |
| 13470 | /* 37321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1033*/ GIMT_Encode4(37346), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3234 // |
| 13471 | /* 37328 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) |
| 13472 | /* 37328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 13473 | /* 37331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13474 | /* 37333 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13475 | /* 37335 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13476 | /* 37338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13477 | /* 37344 */ GIR_RootConstrainSelectedInstOperands, |
| 13478 | /* 37345 */ // GIR_Coverage, 3234, |
| 13479 | /* 37345 */ GIR_EraseRootFromParent_Done, |
| 13480 | /* 37346 */ // Label 1033: @37346 |
| 13481 | /* 37346 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1034*/ GIMT_Encode4(37371), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3235 // |
| 13482 | /* 37353 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) |
| 13483 | /* 37353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 13484 | /* 37356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13485 | /* 37358 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13486 | /* 37360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13487 | /* 37363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13488 | /* 37369 */ GIR_RootConstrainSelectedInstOperands, |
| 13489 | /* 37370 */ // GIR_Coverage, 3235, |
| 13490 | /* 37370 */ GIR_EraseRootFromParent_Done, |
| 13491 | /* 37371 */ // Label 1034: @37371 |
| 13492 | /* 37371 */ GIM_Reject, |
| 13493 | /* 37372 */ // Label 1026: @37372 |
| 13494 | /* 37372 */ GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(37650), |
| 13495 | /* 37377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13496 | /* 37381 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13497 | /* 37385 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1036*/ GIMT_Encode4(37405), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5824 // |
| 13498 | /* 37392 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 13499 | /* 37392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13500 | /* 37395 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13501 | /* 37397 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13502 | /* 37399 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13503 | /* 37404 */ // GIR_Coverage, 5824, |
| 13504 | /* 37404 */ GIR_EraseRootFromParent_Done, |
| 13505 | /* 37405 */ // Label 1036: @37405 |
| 13506 | /* 37405 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1037*/ GIMT_Encode4(37425), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5825 // |
| 13507 | /* 37412 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 13508 | /* 37412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13509 | /* 37415 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13510 | /* 37417 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13511 | /* 37419 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13512 | /* 37424 */ // GIR_Coverage, 5825, |
| 13513 | /* 37424 */ GIR_EraseRootFromParent_Done, |
| 13514 | /* 37425 */ // Label 1037: @37425 |
| 13515 | /* 37425 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1038*/ GIMT_Encode4(37445), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5829 // |
| 13516 | /* 37432 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 13517 | /* 37432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13518 | /* 37435 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13519 | /* 37437 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13520 | /* 37439 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13521 | /* 37444 */ // GIR_Coverage, 5829, |
| 13522 | /* 37444 */ GIR_EraseRootFromParent_Done, |
| 13523 | /* 37445 */ // Label 1038: @37445 |
| 13524 | /* 37445 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1039*/ GIMT_Encode4(37465), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5830 // |
| 13525 | /* 37452 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 13526 | /* 37452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13527 | /* 37455 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13528 | /* 37457 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13529 | /* 37459 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13530 | /* 37464 */ // GIR_Coverage, 5830, |
| 13531 | /* 37464 */ GIR_EraseRootFromParent_Done, |
| 13532 | /* 37465 */ // Label 1039: @37465 |
| 13533 | /* 37465 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1040*/ GIMT_Encode4(37511), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5860 // |
| 13534 | /* 37472 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) |
| 13535 | /* 37472 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13536 | /* 37475 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13537 | /* 37479 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13538 | /* 37484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13539 | /* 37487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13540 | /* 37489 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13541 | /* 37491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13542 | /* 37494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13543 | /* 37500 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13544 | /* 37506 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13545 | /* 37509 */ GIR_RootConstrainSelectedInstOperands, |
| 13546 | /* 37510 */ // GIR_Coverage, 5860, |
| 13547 | /* 37510 */ GIR_EraseRootFromParent_Done, |
| 13548 | /* 37511 */ // Label 1040: @37511 |
| 13549 | /* 37511 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1041*/ GIMT_Encode4(37557), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5861 // |
| 13550 | /* 37518 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) |
| 13551 | /* 37518 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13552 | /* 37521 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13553 | /* 37525 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13554 | /* 37530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13555 | /* 37533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13556 | /* 37535 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13557 | /* 37537 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13558 | /* 37540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13559 | /* 37546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13560 | /* 37552 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13561 | /* 37555 */ GIR_RootConstrainSelectedInstOperands, |
| 13562 | /* 37556 */ // GIR_Coverage, 5861, |
| 13563 | /* 37556 */ GIR_EraseRootFromParent_Done, |
| 13564 | /* 37557 */ // Label 1041: @37557 |
| 13565 | /* 37557 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1042*/ GIMT_Encode4(37603), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5865 // |
| 13566 | /* 37564 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) |
| 13567 | /* 37564 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13568 | /* 37567 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13569 | /* 37571 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13570 | /* 37576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13571 | /* 37579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13572 | /* 37581 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13573 | /* 37583 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13574 | /* 37586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13575 | /* 37592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13576 | /* 37598 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13577 | /* 37601 */ GIR_RootConstrainSelectedInstOperands, |
| 13578 | /* 37602 */ // GIR_Coverage, 5865, |
| 13579 | /* 37602 */ GIR_EraseRootFromParent_Done, |
| 13580 | /* 37603 */ // Label 1042: @37603 |
| 13581 | /* 37603 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1043*/ GIMT_Encode4(37649), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5866 // |
| 13582 | /* 37610 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) |
| 13583 | /* 37610 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13584 | /* 37613 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13585 | /* 37617 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13586 | /* 37622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13587 | /* 37625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13588 | /* 37627 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13589 | /* 37629 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13590 | /* 37632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13591 | /* 37638 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13592 | /* 37644 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13593 | /* 37647 */ GIR_RootConstrainSelectedInstOperands, |
| 13594 | /* 37648 */ // GIR_Coverage, 5866, |
| 13595 | /* 37648 */ GIR_EraseRootFromParent_Done, |
| 13596 | /* 37649 */ // Label 1043: @37649 |
| 13597 | /* 37649 */ GIM_Reject, |
| 13598 | /* 37650 */ // Label 1035: @37650 |
| 13599 | /* 37650 */ GIM_Reject, |
| 13600 | /* 37651 */ // Label 996: @37651 |
| 13601 | /* 37651 */ GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(37705), |
| 13602 | /* 37656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13603 | /* 37660 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13604 | /* 37664 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1045*/ GIMT_Encode4(37684), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3115 // |
| 13605 | /* 37671 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v2f64] }:$src |
| 13606 | /* 37671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13607 | /* 37674 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13608 | /* 37676 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13609 | /* 37678 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13610 | /* 37683 */ // GIR_Coverage, 3115, |
| 13611 | /* 37683 */ GIR_EraseRootFromParent_Done, |
| 13612 | /* 37684 */ // Label 1045: @37684 |
| 13613 | /* 37684 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1046*/ GIMT_Encode4(37704), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3116 // |
| 13614 | /* 37691 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v2i64] }:$src |
| 13615 | /* 37691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13616 | /* 37694 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13617 | /* 37696 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13618 | /* 37698 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13619 | /* 37703 */ // GIR_Coverage, 3116, |
| 13620 | /* 37703 */ GIR_EraseRootFromParent_Done, |
| 13621 | /* 37704 */ // Label 1046: @37704 |
| 13622 | /* 37704 */ GIM_Reject, |
| 13623 | /* 37705 */ // Label 1044: @37705 |
| 13624 | /* 37705 */ GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(37759), |
| 13625 | /* 37710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13626 | /* 37714 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13627 | /* 37718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1048*/ GIMT_Encode4(37738), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5818 // |
| 13628 | /* 37725 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 13629 | /* 37725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13630 | /* 37728 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13631 | /* 37730 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13632 | /* 37732 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13633 | /* 37737 */ // GIR_Coverage, 5818, |
| 13634 | /* 37737 */ GIR_EraseRootFromParent_Done, |
| 13635 | /* 37738 */ // Label 1048: @37738 |
| 13636 | /* 37738 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1049*/ GIMT_Encode4(37758), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5819 // |
| 13637 | /* 37745 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 13638 | /* 37745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13639 | /* 37748 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13640 | /* 37750 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13641 | /* 37752 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13642 | /* 37757 */ // GIR_Coverage, 5819, |
| 13643 | /* 37757 */ GIR_EraseRootFromParent_Done, |
| 13644 | /* 37758 */ // Label 1049: @37758 |
| 13645 | /* 37758 */ GIM_Reject, |
| 13646 | /* 37759 */ // Label 1047: @37759 |
| 13647 | /* 37759 */ GIM_Reject, |
| 13648 | /* 37760 */ // Label 997: @37760 |
| 13649 | /* 37760 */ GIM_Reject, |
| 13650 | /* 37761 */ // Label 727: @37761 |
| 13651 | /* 37761 */ GIM_Reject, |
| 13652 | /* 37762 */ // Label 16: @37762 |
| 13653 | /* 37762 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 1057*/ GIMT_Encode4(38160), |
| 13654 | /* 37773 */ /*GILLT_s16*//*Label 1050*/ GIMT_Encode4(37825), |
| 13655 | /* 37777 */ /*GILLT_s32*//*Label 1051*/ GIMT_Encode4(37862), |
| 13656 | /* 37781 */ /*GILLT_s64*//*Label 1052*/ GIMT_Encode4(37899), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 13657 | /* 37809 */ /*GILLT_v4s16*//*Label 1053*/ GIMT_Encode4(37936), |
| 13658 | /* 37813 */ /*GILLT_v8s16*//*Label 1054*/ GIMT_Encode4(37962), |
| 13659 | /* 37817 */ /*GILLT_v2s32*//*Label 1055*/ GIMT_Encode4(38048), |
| 13660 | /* 37821 */ /*GILLT_v4s32*//*Label 1056*/ GIMT_Encode4(38074), |
| 13661 | /* 37825 */ // Label 1050: @37825 |
| 13662 | /* 37825 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1058*/ GIMT_Encode4(37861), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 693 // |
| 13663 | /* 37832 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 13664 | /* 37835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13665 | /* 37839 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13666 | /* 37843 */ // (ftrunc:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTZH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 13667 | /* 37843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZH), |
| 13668 | /* 37846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 13669 | /* 37848 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 13670 | /* 37850 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13671 | /* 37853 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13672 | /* 37859 */ GIR_RootConstrainSelectedInstOperands, |
| 13673 | /* 37860 */ // GIR_Coverage, 693, |
| 13674 | /* 37860 */ GIR_EraseRootFromParent_Done, |
| 13675 | /* 37861 */ // Label 1058: @37861 |
| 13676 | /* 37861 */ GIM_Reject, |
| 13677 | /* 37862 */ // Label 1051: @37862 |
| 13678 | /* 37862 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1059*/ GIMT_Encode4(37898), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 695 // |
| 13679 | /* 37869 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 13680 | /* 37872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13681 | /* 37876 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13682 | /* 37880 */ // (ftrunc:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTZS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 13683 | /* 37880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZS), |
| 13684 | /* 37883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 13685 | /* 37885 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 13686 | /* 37887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13687 | /* 37890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13688 | /* 37896 */ GIR_RootConstrainSelectedInstOperands, |
| 13689 | /* 37897 */ // GIR_Coverage, 695, |
| 13690 | /* 37897 */ GIR_EraseRootFromParent_Done, |
| 13691 | /* 37898 */ // Label 1059: @37898 |
| 13692 | /* 37898 */ GIM_Reject, |
| 13693 | /* 37899 */ // Label 1052: @37899 |
| 13694 | /* 37899 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1060*/ GIMT_Encode4(37935), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 697 // |
| 13695 | /* 37906 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 13696 | /* 37909 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13697 | /* 37913 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13698 | /* 37917 */ // (ftrunc:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTZD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 13699 | /* 37917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZD), |
| 13700 | /* 37920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 13701 | /* 37922 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 13702 | /* 37924 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13703 | /* 37927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13704 | /* 37933 */ GIR_RootConstrainSelectedInstOperands, |
| 13705 | /* 37934 */ // GIR_Coverage, 697, |
| 13706 | /* 37934 */ GIR_EraseRootFromParent_Done, |
| 13707 | /* 37935 */ // Label 1060: @37935 |
| 13708 | /* 37935 */ GIM_Reject, |
| 13709 | /* 37936 */ // Label 1053: @37936 |
| 13710 | /* 37936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1061*/ GIMT_Encode4(37961), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1882 // |
| 13711 | /* 37943 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 13712 | /* 37946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13713 | /* 37950 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13714 | /* 37954 */ // (ftrunc:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTZNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 13715 | /* 37954 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDh), |
| 13716 | /* 37959 */ GIR_RootConstrainSelectedInstOperands, |
| 13717 | /* 37960 */ // GIR_Coverage, 1882, |
| 13718 | /* 37960 */ GIR_Done, |
| 13719 | /* 37961 */ // Label 1061: @37961 |
| 13720 | /* 37961 */ GIM_Reject, |
| 13721 | /* 37962 */ // Label 1054: @37962 |
| 13722 | /* 37962 */ GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(38047), |
| 13723 | /* 37967 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13724 | /* 37970 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1063*/ GIMT_Encode4(37992), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1884 // |
| 13725 | /* 37977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13726 | /* 37981 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13727 | /* 37985 */ // (ftrunc:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTZNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 13728 | /* 37985 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQh), |
| 13729 | /* 37990 */ GIR_RootConstrainSelectedInstOperands, |
| 13730 | /* 37991 */ // GIR_Coverage, 1884, |
| 13731 | /* 37991 */ GIR_Done, |
| 13732 | /* 37992 */ // Label 1063: @37992 |
| 13733 | /* 37992 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1064*/ GIMT_Encode4(38046), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4380 // |
| 13734 | /* 37999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13735 | /* 38003 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13736 | /* 38007 */ // (ftrunc:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 13737 | /* 38007 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13738 | /* 38010 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13739 | /* 38014 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13740 | /* 38019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z), |
| 13741 | /* 38022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13742 | /* 38024 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 13743 | /* 38026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13744 | /* 38029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13745 | /* 38035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13746 | /* 38041 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13747 | /* 38044 */ GIR_RootConstrainSelectedInstOperands, |
| 13748 | /* 38045 */ // GIR_Coverage, 4380, |
| 13749 | /* 38045 */ GIR_EraseRootFromParent_Done, |
| 13750 | /* 38046 */ // Label 1064: @38046 |
| 13751 | /* 38046 */ GIM_Reject, |
| 13752 | /* 38047 */ // Label 1062: @38047 |
| 13753 | /* 38047 */ GIM_Reject, |
| 13754 | /* 38048 */ // Label 1055: @38048 |
| 13755 | /* 38048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1065*/ GIMT_Encode4(38073), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1878 // |
| 13756 | /* 38055 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 13757 | /* 38058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13758 | /* 38062 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13759 | /* 38066 */ // (ftrunc:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTZNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 13760 | /* 38066 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDf), |
| 13761 | /* 38071 */ GIR_RootConstrainSelectedInstOperands, |
| 13762 | /* 38072 */ // GIR_Coverage, 1878, |
| 13763 | /* 38072 */ GIR_Done, |
| 13764 | /* 38073 */ // Label 1065: @38073 |
| 13765 | /* 38073 */ GIM_Reject, |
| 13766 | /* 38074 */ // Label 1056: @38074 |
| 13767 | /* 38074 */ GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(38159), |
| 13768 | /* 38079 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13769 | /* 38082 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1067*/ GIMT_Encode4(38104), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1880 // |
| 13770 | /* 38089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13771 | /* 38093 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13772 | /* 38097 */ // (ftrunc:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTZNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 13773 | /* 38097 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQf), |
| 13774 | /* 38102 */ GIR_RootConstrainSelectedInstOperands, |
| 13775 | /* 38103 */ // GIR_Coverage, 1880, |
| 13776 | /* 38103 */ GIR_Done, |
| 13777 | /* 38104 */ // Label 1067: @38104 |
| 13778 | /* 38104 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1068*/ GIMT_Encode4(38158), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4404 // |
| 13779 | /* 38111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13780 | /* 38115 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13781 | /* 38119 */ // (ftrunc:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 13782 | /* 38119 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13783 | /* 38122 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13784 | /* 38126 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13785 | /* 38131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z), |
| 13786 | /* 38134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13787 | /* 38136 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 13788 | /* 38138 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13789 | /* 38141 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13790 | /* 38147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13791 | /* 38153 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13792 | /* 38156 */ GIR_RootConstrainSelectedInstOperands, |
| 13793 | /* 38157 */ // GIR_Coverage, 4404, |
| 13794 | /* 38157 */ GIR_EraseRootFromParent_Done, |
| 13795 | /* 38158 */ // Label 1068: @38158 |
| 13796 | /* 38158 */ GIM_Reject, |
| 13797 | /* 38159 */ // Label 1066: @38159 |
| 13798 | /* 38159 */ GIM_Reject, |
| 13799 | /* 38160 */ // Label 1057: @38160 |
| 13800 | /* 38160 */ GIM_Reject, |
| 13801 | /* 38161 */ // Label 17: @38161 |
| 13802 | /* 38161 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 1076*/ GIMT_Encode4(38526), |
| 13803 | /* 38172 */ /*GILLT_s16*//*Label 1069*/ GIMT_Encode4(38224), |
| 13804 | /* 38176 */ /*GILLT_s32*//*Label 1070*/ GIMT_Encode4(38250), |
| 13805 | /* 38180 */ /*GILLT_s64*//*Label 1071*/ GIMT_Encode4(38276), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 13806 | /* 38208 */ /*GILLT_v4s16*//*Label 1072*/ GIMT_Encode4(38302), |
| 13807 | /* 38212 */ /*GILLT_v8s16*//*Label 1073*/ GIMT_Encode4(38328), |
| 13808 | /* 38216 */ /*GILLT_v2s32*//*Label 1074*/ GIMT_Encode4(38414), |
| 13809 | /* 38220 */ /*GILLT_v4s32*//*Label 1075*/ GIMT_Encode4(38440), |
| 13810 | /* 38224 */ // Label 1069: @38224 |
| 13811 | /* 38224 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1077*/ GIMT_Encode4(38249), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 711 // |
| 13812 | /* 38231 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 13813 | /* 38234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13814 | /* 38238 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13815 | /* 38242 */ // (fround:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTAH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 13816 | /* 38242 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAH), |
| 13817 | /* 38247 */ GIR_RootConstrainSelectedInstOperands, |
| 13818 | /* 38248 */ // GIR_Coverage, 711, |
| 13819 | /* 38248 */ GIR_Done, |
| 13820 | /* 38249 */ // Label 1077: @38249 |
| 13821 | /* 38249 */ GIM_Reject, |
| 13822 | /* 38250 */ // Label 1070: @38250 |
| 13823 | /* 38250 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1078*/ GIMT_Encode4(38275), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 713 // |
| 13824 | /* 38257 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 13825 | /* 38260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13826 | /* 38264 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13827 | /* 38268 */ // (fround:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTAS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 13828 | /* 38268 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAS), |
| 13829 | /* 38273 */ GIR_RootConstrainSelectedInstOperands, |
| 13830 | /* 38274 */ // GIR_Coverage, 713, |
| 13831 | /* 38274 */ GIR_Done, |
| 13832 | /* 38275 */ // Label 1078: @38275 |
| 13833 | /* 38275 */ GIM_Reject, |
| 13834 | /* 38276 */ // Label 1071: @38276 |
| 13835 | /* 38276 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1079*/ GIMT_Encode4(38301), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 715 // |
| 13836 | /* 38283 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 13837 | /* 38286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13838 | /* 38290 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13839 | /* 38294 */ // (fround:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTAD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 13840 | /* 38294 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAD), |
| 13841 | /* 38299 */ GIR_RootConstrainSelectedInstOperands, |
| 13842 | /* 38300 */ // GIR_Coverage, 715, |
| 13843 | /* 38300 */ GIR_Done, |
| 13844 | /* 38301 */ // Label 1079: @38301 |
| 13845 | /* 38301 */ GIM_Reject, |
| 13846 | /* 38302 */ // Label 1072: @38302 |
| 13847 | /* 38302 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1080*/ GIMT_Encode4(38327), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1874 // |
| 13848 | /* 38309 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 13849 | /* 38312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13850 | /* 38316 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13851 | /* 38320 */ // (fround:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTANDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 13852 | /* 38320 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDh), |
| 13853 | /* 38325 */ GIR_RootConstrainSelectedInstOperands, |
| 13854 | /* 38326 */ // GIR_Coverage, 1874, |
| 13855 | /* 38326 */ GIR_Done, |
| 13856 | /* 38327 */ // Label 1080: @38327 |
| 13857 | /* 38327 */ GIM_Reject, |
| 13858 | /* 38328 */ // Label 1073: @38328 |
| 13859 | /* 38328 */ GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(38413), |
| 13860 | /* 38333 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13861 | /* 38336 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1082*/ GIMT_Encode4(38358), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1876 // |
| 13862 | /* 38343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13863 | /* 38347 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13864 | /* 38351 */ // (fround:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTANQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 13865 | /* 38351 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQh), |
| 13866 | /* 38356 */ GIR_RootConstrainSelectedInstOperands, |
| 13867 | /* 38357 */ // GIR_Coverage, 1876, |
| 13868 | /* 38357 */ GIR_Done, |
| 13869 | /* 38358 */ // Label 1082: @38358 |
| 13870 | /* 38358 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1083*/ GIMT_Encode4(38412), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4376 // |
| 13871 | /* 38365 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13872 | /* 38369 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13873 | /* 38373 */ // (fround:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 13874 | /* 38373 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13875 | /* 38376 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13876 | /* 38380 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13877 | /* 38385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A), |
| 13878 | /* 38388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13879 | /* 38390 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 13880 | /* 38392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13881 | /* 38395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13882 | /* 38401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13883 | /* 38407 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13884 | /* 38410 */ GIR_RootConstrainSelectedInstOperands, |
| 13885 | /* 38411 */ // GIR_Coverage, 4376, |
| 13886 | /* 38411 */ GIR_EraseRootFromParent_Done, |
| 13887 | /* 38412 */ // Label 1083: @38412 |
| 13888 | /* 38412 */ GIM_Reject, |
| 13889 | /* 38413 */ // Label 1081: @38413 |
| 13890 | /* 38413 */ GIM_Reject, |
| 13891 | /* 38414 */ // Label 1074: @38414 |
| 13892 | /* 38414 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1084*/ GIMT_Encode4(38439), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1870 // |
| 13893 | /* 38421 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 13894 | /* 38424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13895 | /* 38428 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13896 | /* 38432 */ // (fround:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTANDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 13897 | /* 38432 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDf), |
| 13898 | /* 38437 */ GIR_RootConstrainSelectedInstOperands, |
| 13899 | /* 38438 */ // GIR_Coverage, 1870, |
| 13900 | /* 38438 */ GIR_Done, |
| 13901 | /* 38439 */ // Label 1084: @38439 |
| 13902 | /* 38439 */ GIM_Reject, |
| 13903 | /* 38440 */ // Label 1075: @38440 |
| 13904 | /* 38440 */ GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(38525), |
| 13905 | /* 38445 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13906 | /* 38448 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1086*/ GIMT_Encode4(38470), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1872 // |
| 13907 | /* 38455 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13908 | /* 38459 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13909 | /* 38463 */ // (fround:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTANQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 13910 | /* 38463 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQf), |
| 13911 | /* 38468 */ GIR_RootConstrainSelectedInstOperands, |
| 13912 | /* 38469 */ // GIR_Coverage, 1872, |
| 13913 | /* 38469 */ GIR_Done, |
| 13914 | /* 38470 */ // Label 1086: @38470 |
| 13915 | /* 38470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1087*/ GIMT_Encode4(38524), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4400 // |
| 13916 | /* 38477 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13917 | /* 38481 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13918 | /* 38485 */ // (fround:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 13919 | /* 38485 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13920 | /* 38488 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13921 | /* 38492 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13922 | /* 38497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A), |
| 13923 | /* 38500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13924 | /* 38502 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 13925 | /* 38504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13926 | /* 38507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13927 | /* 38513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13928 | /* 38519 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13929 | /* 38522 */ GIR_RootConstrainSelectedInstOperands, |
| 13930 | /* 38523 */ // GIR_Coverage, 4400, |
| 13931 | /* 38523 */ GIR_EraseRootFromParent_Done, |
| 13932 | /* 38524 */ // Label 1087: @38524 |
| 13933 | /* 38524 */ GIM_Reject, |
| 13934 | /* 38525 */ // Label 1085: @38525 |
| 13935 | /* 38525 */ GIM_Reject, |
| 13936 | /* 38526 */ // Label 1076: @38526 |
| 13937 | /* 38526 */ GIM_Reject, |
| 13938 | /* 38527 */ // Label 18: @38527 |
| 13939 | /* 38527 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 1095*/ GIMT_Encode4(38892), |
| 13940 | /* 38538 */ /*GILLT_s16*//*Label 1088*/ GIMT_Encode4(38590), |
| 13941 | /* 38542 */ /*GILLT_s32*//*Label 1089*/ GIMT_Encode4(38616), |
| 13942 | /* 38546 */ /*GILLT_s64*//*Label 1090*/ GIMT_Encode4(38642), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 13943 | /* 38574 */ /*GILLT_v4s16*//*Label 1091*/ GIMT_Encode4(38668), |
| 13944 | /* 38578 */ /*GILLT_v8s16*//*Label 1092*/ GIMT_Encode4(38694), |
| 13945 | /* 38582 */ /*GILLT_v2s32*//*Label 1093*/ GIMT_Encode4(38780), |
| 13946 | /* 38586 */ /*GILLT_v4s32*//*Label 1094*/ GIMT_Encode4(38806), |
| 13947 | /* 38590 */ // Label 1088: @38590 |
| 13948 | /* 38590 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1096*/ GIMT_Encode4(38615), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 717 // |
| 13949 | /* 38597 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 13950 | /* 38600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13951 | /* 38604 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13952 | /* 38608 */ // (froundeven:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 13953 | /* 38608 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNH), |
| 13954 | /* 38613 */ GIR_RootConstrainSelectedInstOperands, |
| 13955 | /* 38614 */ // GIR_Coverage, 717, |
| 13956 | /* 38614 */ GIR_Done, |
| 13957 | /* 38615 */ // Label 1096: @38615 |
| 13958 | /* 38615 */ GIM_Reject, |
| 13959 | /* 38616 */ // Label 1089: @38616 |
| 13960 | /* 38616 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1097*/ GIMT_Encode4(38641), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 719 // |
| 13961 | /* 38623 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 13962 | /* 38626 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13963 | /* 38630 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13964 | /* 38634 */ // (froundeven:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 13965 | /* 38634 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNS), |
| 13966 | /* 38639 */ GIR_RootConstrainSelectedInstOperands, |
| 13967 | /* 38640 */ // GIR_Coverage, 719, |
| 13968 | /* 38640 */ GIR_Done, |
| 13969 | /* 38641 */ // Label 1097: @38641 |
| 13970 | /* 38641 */ GIM_Reject, |
| 13971 | /* 38642 */ // Label 1090: @38642 |
| 13972 | /* 38642 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1098*/ GIMT_Encode4(38667), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 721 // |
| 13973 | /* 38649 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 13974 | /* 38652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13975 | /* 38656 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13976 | /* 38660 */ // (froundeven:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 13977 | /* 38660 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTND), |
| 13978 | /* 38665 */ GIR_RootConstrainSelectedInstOperands, |
| 13979 | /* 38666 */ // GIR_Coverage, 721, |
| 13980 | /* 38666 */ GIR_Done, |
| 13981 | /* 38667 */ // Label 1098: @38667 |
| 13982 | /* 38667 */ GIM_Reject, |
| 13983 | /* 38668 */ // Label 1091: @38668 |
| 13984 | /* 38668 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1099*/ GIMT_Encode4(38693), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1858 // |
| 13985 | /* 38675 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 13986 | /* 38678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13987 | /* 38682 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13988 | /* 38686 */ // (froundeven:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 13989 | /* 38686 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDh), |
| 13990 | /* 38691 */ GIR_RootConstrainSelectedInstOperands, |
| 13991 | /* 38692 */ // GIR_Coverage, 1858, |
| 13992 | /* 38692 */ GIR_Done, |
| 13993 | /* 38693 */ // Label 1099: @38693 |
| 13994 | /* 38693 */ GIM_Reject, |
| 13995 | /* 38694 */ // Label 1092: @38694 |
| 13996 | /* 38694 */ GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(38779), |
| 13997 | /* 38699 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13998 | /* 38702 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1101*/ GIMT_Encode4(38724), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1860 // |
| 13999 | /* 38709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14000 | /* 38713 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14001 | /* 38717 */ // (froundeven:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 14002 | /* 38717 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQh), |
| 14003 | /* 38722 */ GIR_RootConstrainSelectedInstOperands, |
| 14004 | /* 38723 */ // GIR_Coverage, 1860, |
| 14005 | /* 38723 */ GIR_Done, |
| 14006 | /* 38724 */ // Label 1101: @38724 |
| 14007 | /* 38724 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1102*/ GIMT_Encode4(38778), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4368 // |
| 14008 | /* 38731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14009 | /* 38735 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14010 | /* 38739 */ // (froundeven:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 14011 | /* 38739 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14012 | /* 38742 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14013 | /* 38746 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14014 | /* 38751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N), |
| 14015 | /* 38754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14016 | /* 38756 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 14017 | /* 38758 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14018 | /* 38761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14019 | /* 38767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14020 | /* 38773 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14021 | /* 38776 */ GIR_RootConstrainSelectedInstOperands, |
| 14022 | /* 38777 */ // GIR_Coverage, 4368, |
| 14023 | /* 38777 */ GIR_EraseRootFromParent_Done, |
| 14024 | /* 38778 */ // Label 1102: @38778 |
| 14025 | /* 38778 */ GIM_Reject, |
| 14026 | /* 38779 */ // Label 1100: @38779 |
| 14027 | /* 38779 */ GIM_Reject, |
| 14028 | /* 38780 */ // Label 1093: @38780 |
| 14029 | /* 38780 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1103*/ GIMT_Encode4(38805), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1854 // |
| 14030 | /* 38787 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 14031 | /* 38790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14032 | /* 38794 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14033 | /* 38798 */ // (froundeven:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTNNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 14034 | /* 38798 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDf), |
| 14035 | /* 38803 */ GIR_RootConstrainSelectedInstOperands, |
| 14036 | /* 38804 */ // GIR_Coverage, 1854, |
| 14037 | /* 38804 */ GIR_Done, |
| 14038 | /* 38805 */ // Label 1103: @38805 |
| 14039 | /* 38805 */ GIM_Reject, |
| 14040 | /* 38806 */ // Label 1094: @38806 |
| 14041 | /* 38806 */ GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(38891), |
| 14042 | /* 38811 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14043 | /* 38814 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1105*/ GIMT_Encode4(38836), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1856 // |
| 14044 | /* 38821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14045 | /* 38825 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14046 | /* 38829 */ // (froundeven:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTNNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 14047 | /* 38829 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQf), |
| 14048 | /* 38834 */ GIR_RootConstrainSelectedInstOperands, |
| 14049 | /* 38835 */ // GIR_Coverage, 1856, |
| 14050 | /* 38835 */ GIR_Done, |
| 14051 | /* 38836 */ // Label 1105: @38836 |
| 14052 | /* 38836 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1106*/ GIMT_Encode4(38890), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4392 // |
| 14053 | /* 38843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14054 | /* 38847 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14055 | /* 38851 */ // (froundeven:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 14056 | /* 38851 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14057 | /* 38854 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14058 | /* 38858 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14059 | /* 38863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N), |
| 14060 | /* 38866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14061 | /* 38868 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 14062 | /* 38870 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14063 | /* 38873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14064 | /* 38879 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14065 | /* 38885 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14066 | /* 38888 */ GIR_RootConstrainSelectedInstOperands, |
| 14067 | /* 38889 */ // GIR_Coverage, 4392, |
| 14068 | /* 38889 */ GIR_EraseRootFromParent_Done, |
| 14069 | /* 38890 */ // Label 1106: @38890 |
| 14070 | /* 38890 */ GIM_Reject, |
| 14071 | /* 38891 */ // Label 1104: @38891 |
| 14072 | /* 38891 */ GIM_Reject, |
| 14073 | /* 38892 */ // Label 1095: @38892 |
| 14074 | /* 38892 */ GIM_Reject, |
| 14075 | /* 38893 */ // Label 19: @38893 |
| 14076 | /* 38893 */ GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(39053), |
| 14077 | /* 38898 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14078 | /* 38901 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 14079 | /* 38904 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1108*/ GIMT_Encode4(38978), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 2249 // |
| 14080 | /* 38911 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 14081 | /* 38918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 14082 | /* 38922 */ // MIs[0] Rn |
| 14083 | /* 38922 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 14084 | /* 38926 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 14085 | /* 38930 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (tLDRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] })) |
| 14086 | /* 38930 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 14087 | /* 38933 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 14088 | /* 38937 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14089 | /* 38942 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 14090 | /* 38948 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 14091 | /* 38951 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 14092 | /* 38954 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14093 | /* 38960 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14094 | /* 38962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSB), |
| 14095 | /* 38965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 14096 | /* 38967 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 14097 | /* 38969 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14098 | /* 38972 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14099 | /* 38976 */ GIR_RootConstrainSelectedInstOperands, |
| 14100 | /* 38977 */ // GIR_Coverage, 2249, |
| 14101 | /* 38977 */ GIR_EraseRootFromParent_Done, |
| 14102 | /* 38978 */ // Label 1108: @38978 |
| 14103 | /* 38978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1109*/ GIMT_Encode4(39052), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 2250 // |
| 14104 | /* 38985 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 14105 | /* 38992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 14106 | /* 38996 */ // MIs[0] Rn |
| 14107 | /* 38996 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 14108 | /* 39000 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 14109 | /* 39004 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (tLDRSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] })) |
| 14110 | /* 39004 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 14111 | /* 39007 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 14112 | /* 39011 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14113 | /* 39016 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 14114 | /* 39022 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 14115 | /* 39025 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 14116 | /* 39028 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14117 | /* 39034 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14118 | /* 39036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSH), |
| 14119 | /* 39039 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 14120 | /* 39041 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 14121 | /* 39043 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14122 | /* 39046 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14123 | /* 39050 */ GIR_RootConstrainSelectedInstOperands, |
| 14124 | /* 39051 */ // GIR_Coverage, 2250, |
| 14125 | /* 39051 */ GIR_EraseRootFromParent_Done, |
| 14126 | /* 39052 */ // Label 1109: @39052 |
| 14127 | /* 39052 */ GIM_Reject, |
| 14128 | /* 39053 */ // Label 1107: @39053 |
| 14129 | /* 39053 */ GIM_Reject, |
| 14130 | /* 39054 */ // Label 20: @39054 |
| 14131 | /* 39054 */ GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(39074), // Rule ID 5956 // |
| 14132 | /* 39059 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 14133 | /* 39062 */ // MIs[0] Operand 0 |
| 14134 | /* 39062 */ GIM_CheckIsImm, /*MI*/0, /*Op*/0, |
| 14135 | /* 39065 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, |
| 14136 | /* 39069 */ // (atomic_fence (timm:{ *:[i32] }), 0:{ *:[i32] }) => (MEMBARRIER) |
| 14137 | /* 39069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::MEMBARRIER), |
| 14138 | /* 39072 */ GIR_RootConstrainSelectedInstOperands, |
| 14139 | /* 39073 */ // GIR_Coverage, 5956, |
| 14140 | /* 39073 */ GIR_EraseRootFromParent_Done, |
| 14141 | /* 39074 */ // Label 1110: @39074 |
| 14142 | /* 39074 */ GIM_Reject, |
| 14143 | /* 39075 */ // Label 21: @39075 |
| 14144 | /* 39075 */ GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(44386), |
| 14145 | /* 39080 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 14146 | /* 39083 */ GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(39172), |
| 14147 | /* 39088 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16), |
| 14148 | /* 39093 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14149 | /* 39096 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14150 | /* 39099 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1113*/ GIMT_Encode4(39135), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2044 // |
| 14151 | /* 39106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14152 | /* 39110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 14153 | /* 39114 */ // (intrinsic_wo_chain:{ *:[i32] } 4178:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 14154 | /* 39114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), |
| 14155 | /* 39117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 14156 | /* 39119 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src |
| 14157 | /* 39121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14158 | /* 39124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14159 | /* 39127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14160 | /* 39133 */ GIR_RootConstrainSelectedInstOperands, |
| 14161 | /* 39134 */ // GIR_Coverage, 2044, |
| 14162 | /* 39134 */ GIR_EraseRootFromParent_Done, |
| 14163 | /* 39135 */ // Label 1113: @39135 |
| 14164 | /* 39135 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1114*/ GIMT_Encode4(39171), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2306 // |
| 14165 | /* 39142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14166 | /* 39146 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14167 | /* 39150 */ // (intrinsic_wo_chain:{ *:[i32] } 4178:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 14168 | /* 39150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), |
| 14169 | /* 39153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 14170 | /* 39155 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 14171 | /* 39157 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14172 | /* 39160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14173 | /* 39163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14174 | /* 39169 */ GIR_RootConstrainSelectedInstOperands, |
| 14175 | /* 39170 */ // GIR_Coverage, 2306, |
| 14176 | /* 39170 */ GIR_EraseRootFromParent_Done, |
| 14177 | /* 39171 */ // Label 1114: @39171 |
| 14178 | /* 39171 */ GIM_Reject, |
| 14179 | /* 39172 */ // Label 1112: @39172 |
| 14180 | /* 39172 */ GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(39273), |
| 14181 | /* 39177 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr), |
| 14182 | /* 39182 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14183 | /* 39185 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1118*/ GIMT_Encode4(39272), |
| 14184 | /* 39196 */ /*GILLT_s32*//*Label 1116*/ GIMT_Encode4(39204), |
| 14185 | /* 39200 */ /*GILLT_s64*//*Label 1117*/ GIMT_Encode4(39238), |
| 14186 | /* 39204 */ // Label 1116: @39204 |
| 14187 | /* 39204 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1119*/ GIMT_Encode4(39237), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 745 // |
| 14188 | /* 39211 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14189 | /* 39215 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14190 | /* 39219 */ // (intrinsic_wo_chain:{ *:[f32] } 4179:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 14191 | /* 39219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRS), |
| 14192 | /* 39222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 14193 | /* 39224 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 14194 | /* 39226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14195 | /* 39229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14196 | /* 39235 */ GIR_RootConstrainSelectedInstOperands, |
| 14197 | /* 39236 */ // GIR_Coverage, 745, |
| 14198 | /* 39236 */ GIR_EraseRootFromParent_Done, |
| 14199 | /* 39237 */ // Label 1119: @39237 |
| 14200 | /* 39237 */ GIM_Reject, |
| 14201 | /* 39238 */ // Label 1117: @39238 |
| 14202 | /* 39238 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1120*/ GIMT_Encode4(39271), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 744 // |
| 14203 | /* 39245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14204 | /* 39249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14205 | /* 39253 */ // (intrinsic_wo_chain:{ *:[f32] } 4179:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) |
| 14206 | /* 39253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRD), |
| 14207 | /* 39256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 14208 | /* 39258 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 14209 | /* 39260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14210 | /* 39263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14211 | /* 39269 */ GIR_RootConstrainSelectedInstOperands, |
| 14212 | /* 39270 */ // GIR_Coverage, 744, |
| 14213 | /* 39270 */ GIR_EraseRootFromParent_Done, |
| 14214 | /* 39271 */ // Label 1120: @39271 |
| 14215 | /* 39271 */ GIM_Reject, |
| 14216 | /* 39272 */ // Label 1118: @39272 |
| 14217 | /* 39272 */ GIM_Reject, |
| 14218 | /* 39273 */ // Label 1115: @39273 |
| 14219 | /* 39273 */ GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(39374), |
| 14220 | /* 39278 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru), |
| 14221 | /* 39283 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14222 | /* 39286 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1124*/ GIMT_Encode4(39373), |
| 14223 | /* 39297 */ /*GILLT_s32*//*Label 1122*/ GIMT_Encode4(39305), |
| 14224 | /* 39301 */ /*GILLT_s64*//*Label 1123*/ GIMT_Encode4(39339), |
| 14225 | /* 39305 */ // Label 1122: @39305 |
| 14226 | /* 39305 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1125*/ GIMT_Encode4(39338), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 747 // |
| 14227 | /* 39312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14228 | /* 39316 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14229 | /* 39320 */ // (intrinsic_wo_chain:{ *:[f32] } 4180:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 14230 | /* 39320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRS), |
| 14231 | /* 39323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 14232 | /* 39325 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 14233 | /* 39327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14234 | /* 39330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14235 | /* 39336 */ GIR_RootConstrainSelectedInstOperands, |
| 14236 | /* 39337 */ // GIR_Coverage, 747, |
| 14237 | /* 39337 */ GIR_EraseRootFromParent_Done, |
| 14238 | /* 39338 */ // Label 1125: @39338 |
| 14239 | /* 39338 */ GIM_Reject, |
| 14240 | /* 39339 */ // Label 1123: @39339 |
| 14241 | /* 39339 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1126*/ GIMT_Encode4(39372), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 746 // |
| 14242 | /* 39346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14243 | /* 39350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14244 | /* 39354 */ // (intrinsic_wo_chain:{ *:[f32] } 4180:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) |
| 14245 | /* 39354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRD), |
| 14246 | /* 39357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 14247 | /* 39359 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 14248 | /* 39361 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14249 | /* 39364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14250 | /* 39370 */ GIR_RootConstrainSelectedInstOperands, |
| 14251 | /* 39371 */ // GIR_Coverage, 746, |
| 14252 | /* 39371 */ GIR_EraseRootFromParent_Done, |
| 14253 | /* 39372 */ // Label 1126: @39372 |
| 14254 | /* 39372 */ GIM_Reject, |
| 14255 | /* 39373 */ // Label 1124: @39373 |
| 14256 | /* 39373 */ GIM_Reject, |
| 14257 | /* 39374 */ // Label 1121: @39374 |
| 14258 | /* 39374 */ GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(39666), |
| 14259 | /* 39379 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 14260 | /* 39384 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1134*/ GIMT_Encode4(39665), |
| 14261 | /* 39395 */ /*GILLT_s64*//*Label 1128*/ GIMT_Encode4(39443), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 14262 | /* 39423 */ /*GILLT_v4s16*//*Label 1129*/ GIMT_Encode4(39480), |
| 14263 | /* 39427 */ /*GILLT_v8s16*//*Label 1130*/ GIMT_Encode4(39517), |
| 14264 | /* 39431 */ /*GILLT_v2s32*//*Label 1131*/ GIMT_Encode4(39554), |
| 14265 | /* 39435 */ /*GILLT_v4s32*//*Label 1132*/ GIMT_Encode4(39591), |
| 14266 | /* 39439 */ /*GILLT_v2s64*//*Label 1133*/ GIMT_Encode4(39628), |
| 14267 | /* 39443 */ // Label 1128: @39443 |
| 14268 | /* 39443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1135*/ GIMT_Encode4(39479), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1406 // |
| 14269 | /* 39450 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14270 | /* 39453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14271 | /* 39457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14272 | /* 39461 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4036:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm) |
| 14273 | /* 39461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv2i32), |
| 14274 | /* 39464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14275 | /* 39466 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14276 | /* 39468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14277 | /* 39471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14278 | /* 39477 */ GIR_RootConstrainSelectedInstOperands, |
| 14279 | /* 39478 */ // GIR_Coverage, 1406, |
| 14280 | /* 39478 */ GIR_EraseRootFromParent_Done, |
| 14281 | /* 39479 */ // Label 1135: @39479 |
| 14282 | /* 39479 */ GIM_Reject, |
| 14283 | /* 39480 */ // Label 1129: @39480 |
| 14284 | /* 39480 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1136*/ GIMT_Encode4(39516), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1404 // |
| 14285 | /* 39487 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 14286 | /* 39490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14287 | /* 39494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14288 | /* 39498 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4036:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm) |
| 14289 | /* 39498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i8), |
| 14290 | /* 39501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14291 | /* 39503 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14292 | /* 39505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14293 | /* 39508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14294 | /* 39514 */ GIR_RootConstrainSelectedInstOperands, |
| 14295 | /* 39515 */ // GIR_Coverage, 1404, |
| 14296 | /* 39515 */ GIR_EraseRootFromParent_Done, |
| 14297 | /* 39516 */ // Label 1136: @39516 |
| 14298 | /* 39516 */ GIM_Reject, |
| 14299 | /* 39517 */ // Label 1130: @39517 |
| 14300 | /* 39517 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1137*/ GIMT_Encode4(39553), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1407 // |
| 14301 | /* 39524 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14302 | /* 39527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14303 | /* 39531 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14304 | /* 39535 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4036:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm) |
| 14305 | /* 39535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv16i8), |
| 14306 | /* 39538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14307 | /* 39540 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14308 | /* 39542 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14309 | /* 39545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14310 | /* 39551 */ GIR_RootConstrainSelectedInstOperands, |
| 14311 | /* 39552 */ // GIR_Coverage, 1407, |
| 14312 | /* 39552 */ GIR_EraseRootFromParent_Done, |
| 14313 | /* 39553 */ // Label 1137: @39553 |
| 14314 | /* 39553 */ GIM_Reject, |
| 14315 | /* 39554 */ // Label 1131: @39554 |
| 14316 | /* 39554 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1138*/ GIMT_Encode4(39590), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1405 // |
| 14317 | /* 39561 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14318 | /* 39564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14319 | /* 39568 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14320 | /* 39572 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4036:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm) |
| 14321 | /* 39572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i16), |
| 14322 | /* 39575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14323 | /* 39577 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14324 | /* 39579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14325 | /* 39582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14326 | /* 39588 */ GIR_RootConstrainSelectedInstOperands, |
| 14327 | /* 39589 */ // GIR_Coverage, 1405, |
| 14328 | /* 39589 */ GIR_EraseRootFromParent_Done, |
| 14329 | /* 39590 */ // Label 1138: @39590 |
| 14330 | /* 39590 */ GIM_Reject, |
| 14331 | /* 39591 */ // Label 1132: @39591 |
| 14332 | /* 39591 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1139*/ GIMT_Encode4(39627), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1408 // |
| 14333 | /* 39598 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14334 | /* 39601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14335 | /* 39605 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14336 | /* 39609 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4036:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm) |
| 14337 | /* 39609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i16), |
| 14338 | /* 39612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14339 | /* 39614 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14340 | /* 39616 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14341 | /* 39619 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14342 | /* 39625 */ GIR_RootConstrainSelectedInstOperands, |
| 14343 | /* 39626 */ // GIR_Coverage, 1408, |
| 14344 | /* 39626 */ GIR_EraseRootFromParent_Done, |
| 14345 | /* 39627 */ // Label 1139: @39627 |
| 14346 | /* 39627 */ GIM_Reject, |
| 14347 | /* 39628 */ // Label 1133: @39628 |
| 14348 | /* 39628 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1140*/ GIMT_Encode4(39664), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1409 // |
| 14349 | /* 39635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14350 | /* 39638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14351 | /* 39642 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14352 | /* 39646 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4036:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm) |
| 14353 | /* 39646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i32), |
| 14354 | /* 39649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14355 | /* 39651 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14356 | /* 39653 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14357 | /* 39656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14358 | /* 39662 */ GIR_RootConstrainSelectedInstOperands, |
| 14359 | /* 39663 */ // GIR_Coverage, 1409, |
| 14360 | /* 39663 */ GIR_EraseRootFromParent_Done, |
| 14361 | /* 39664 */ // Label 1140: @39664 |
| 14362 | /* 39664 */ GIM_Reject, |
| 14363 | /* 39665 */ // Label 1134: @39665 |
| 14364 | /* 39665 */ GIM_Reject, |
| 14365 | /* 39666 */ // Label 1127: @39666 |
| 14366 | /* 39666 */ GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(39958), |
| 14367 | /* 39671 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 14368 | /* 39676 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1148*/ GIMT_Encode4(39957), |
| 14369 | /* 39687 */ /*GILLT_s64*//*Label 1142*/ GIMT_Encode4(39735), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 14370 | /* 39715 */ /*GILLT_v4s16*//*Label 1143*/ GIMT_Encode4(39772), |
| 14371 | /* 39719 */ /*GILLT_v8s16*//*Label 1144*/ GIMT_Encode4(39809), |
| 14372 | /* 39723 */ /*GILLT_v2s32*//*Label 1145*/ GIMT_Encode4(39846), |
| 14373 | /* 39727 */ /*GILLT_v4s32*//*Label 1146*/ GIMT_Encode4(39883), |
| 14374 | /* 39731 */ /*GILLT_v2s64*//*Label 1147*/ GIMT_Encode4(39920), |
| 14375 | /* 39735 */ // Label 1142: @39735 |
| 14376 | /* 39735 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1149*/ GIMT_Encode4(39771), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1412 // |
| 14377 | /* 39742 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14378 | /* 39745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14379 | /* 39749 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14380 | /* 39753 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4037:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm) |
| 14381 | /* 39753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv2i32), |
| 14382 | /* 39756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14383 | /* 39758 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14384 | /* 39760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14385 | /* 39763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14386 | /* 39769 */ GIR_RootConstrainSelectedInstOperands, |
| 14387 | /* 39770 */ // GIR_Coverage, 1412, |
| 14388 | /* 39770 */ GIR_EraseRootFromParent_Done, |
| 14389 | /* 39771 */ // Label 1149: @39771 |
| 14390 | /* 39771 */ GIM_Reject, |
| 14391 | /* 39772 */ // Label 1143: @39772 |
| 14392 | /* 39772 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1150*/ GIMT_Encode4(39808), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1410 // |
| 14393 | /* 39779 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 14394 | /* 39782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14395 | /* 39786 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14396 | /* 39790 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4037:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm) |
| 14397 | /* 39790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i8), |
| 14398 | /* 39793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14399 | /* 39795 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14400 | /* 39797 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14401 | /* 39800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14402 | /* 39806 */ GIR_RootConstrainSelectedInstOperands, |
| 14403 | /* 39807 */ // GIR_Coverage, 1410, |
| 14404 | /* 39807 */ GIR_EraseRootFromParent_Done, |
| 14405 | /* 39808 */ // Label 1150: @39808 |
| 14406 | /* 39808 */ GIM_Reject, |
| 14407 | /* 39809 */ // Label 1144: @39809 |
| 14408 | /* 39809 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1151*/ GIMT_Encode4(39845), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1413 // |
| 14409 | /* 39816 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14410 | /* 39819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14411 | /* 39823 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14412 | /* 39827 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4037:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm) |
| 14413 | /* 39827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv16i8), |
| 14414 | /* 39830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14415 | /* 39832 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14416 | /* 39834 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14417 | /* 39837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14418 | /* 39843 */ GIR_RootConstrainSelectedInstOperands, |
| 14419 | /* 39844 */ // GIR_Coverage, 1413, |
| 14420 | /* 39844 */ GIR_EraseRootFromParent_Done, |
| 14421 | /* 39845 */ // Label 1151: @39845 |
| 14422 | /* 39845 */ GIM_Reject, |
| 14423 | /* 39846 */ // Label 1145: @39846 |
| 14424 | /* 39846 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1152*/ GIMT_Encode4(39882), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1411 // |
| 14425 | /* 39853 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14426 | /* 39856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14427 | /* 39860 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14428 | /* 39864 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4037:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm) |
| 14429 | /* 39864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i16), |
| 14430 | /* 39867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14431 | /* 39869 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14432 | /* 39871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14433 | /* 39874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14434 | /* 39880 */ GIR_RootConstrainSelectedInstOperands, |
| 14435 | /* 39881 */ // GIR_Coverage, 1411, |
| 14436 | /* 39881 */ GIR_EraseRootFromParent_Done, |
| 14437 | /* 39882 */ // Label 1152: @39882 |
| 14438 | /* 39882 */ GIM_Reject, |
| 14439 | /* 39883 */ // Label 1146: @39883 |
| 14440 | /* 39883 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1153*/ GIMT_Encode4(39919), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1414 // |
| 14441 | /* 39890 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14442 | /* 39893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14443 | /* 39897 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14444 | /* 39901 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4037:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm) |
| 14445 | /* 39901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i16), |
| 14446 | /* 39904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14447 | /* 39906 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14448 | /* 39908 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14449 | /* 39911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14450 | /* 39917 */ GIR_RootConstrainSelectedInstOperands, |
| 14451 | /* 39918 */ // GIR_Coverage, 1414, |
| 14452 | /* 39918 */ GIR_EraseRootFromParent_Done, |
| 14453 | /* 39919 */ // Label 1153: @39919 |
| 14454 | /* 39919 */ GIM_Reject, |
| 14455 | /* 39920 */ // Label 1147: @39920 |
| 14456 | /* 39920 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1154*/ GIMT_Encode4(39956), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1415 // |
| 14457 | /* 39927 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14458 | /* 39930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14459 | /* 39934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14460 | /* 39938 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4037:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm) |
| 14461 | /* 39938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i32), |
| 14462 | /* 39941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14463 | /* 39943 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14464 | /* 39945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14465 | /* 39948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14466 | /* 39954 */ GIR_RootConstrainSelectedInstOperands, |
| 14467 | /* 39955 */ // GIR_Coverage, 1415, |
| 14468 | /* 39955 */ GIR_EraseRootFromParent_Done, |
| 14469 | /* 39956 */ // Label 1154: @39956 |
| 14470 | /* 39956 */ GIM_Reject, |
| 14471 | /* 39957 */ // Label 1148: @39957 |
| 14472 | /* 39957 */ GIM_Reject, |
| 14473 | /* 39958 */ // Label 1141: @39958 |
| 14474 | /* 39958 */ GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(40206), |
| 14475 | /* 39963 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 14476 | /* 39968 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1160*/ GIMT_Encode4(40205), |
| 14477 | /* 39979 */ /*GILLT_v4s16*//*Label 1156*/ GIMT_Encode4(39995), |
| 14478 | /* 39983 */ /*GILLT_v8s16*//*Label 1157*/ GIMT_Encode4(40032), |
| 14479 | /* 39987 */ /*GILLT_v2s32*//*Label 1158*/ GIMT_Encode4(40069), |
| 14480 | /* 39991 */ /*GILLT_v4s32*//*Label 1159*/ GIMT_Encode4(40137), |
| 14481 | /* 39995 */ // Label 1156: @39995 |
| 14482 | /* 39995 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1161*/ GIMT_Encode4(40031), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1448 // |
| 14483 | /* 40002 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14484 | /* 40005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14485 | /* 40009 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14486 | /* 40013 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4064:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 14487 | /* 40013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhd), |
| 14488 | /* 40016 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14489 | /* 40018 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14490 | /* 40020 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14491 | /* 40023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14492 | /* 40029 */ GIR_RootConstrainSelectedInstOperands, |
| 14493 | /* 40030 */ // GIR_Coverage, 1448, |
| 14494 | /* 40030 */ GIR_EraseRootFromParent_Done, |
| 14495 | /* 40031 */ // Label 1161: @40031 |
| 14496 | /* 40031 */ GIM_Reject, |
| 14497 | /* 40032 */ // Label 1157: @40032 |
| 14498 | /* 40032 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1162*/ GIMT_Encode4(40068), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1449 // |
| 14499 | /* 40039 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14500 | /* 40042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14501 | /* 40046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14502 | /* 40050 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4064:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 14503 | /* 40050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhq), |
| 14504 | /* 40053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14505 | /* 40055 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14506 | /* 40057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14507 | /* 40060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14508 | /* 40066 */ GIR_RootConstrainSelectedInstOperands, |
| 14509 | /* 40067 */ // GIR_Coverage, 1449, |
| 14510 | /* 40067 */ GIR_EraseRootFromParent_Done, |
| 14511 | /* 40068 */ // Label 1162: @40068 |
| 14512 | /* 40068 */ GIM_Reject, |
| 14513 | /* 40069 */ // Label 1158: @40069 |
| 14514 | /* 40069 */ GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(40136), |
| 14515 | /* 40074 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14516 | /* 40077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14517 | /* 40081 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14518 | /* 40085 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1164*/ GIMT_Encode4(40110), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1444 // |
| 14519 | /* 40092 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4064:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 14520 | /* 40092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEd), |
| 14521 | /* 40095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14522 | /* 40097 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14523 | /* 40099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14524 | /* 40102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14525 | /* 40108 */ GIR_RootConstrainSelectedInstOperands, |
| 14526 | /* 40109 */ // GIR_Coverage, 1444, |
| 14527 | /* 40109 */ GIR_EraseRootFromParent_Done, |
| 14528 | /* 40110 */ // Label 1164: @40110 |
| 14529 | /* 40110 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1165*/ GIMT_Encode4(40135), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1446 // |
| 14530 | /* 40117 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4064:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 14531 | /* 40117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfd), |
| 14532 | /* 40120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14533 | /* 40122 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14534 | /* 40124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14535 | /* 40127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14536 | /* 40133 */ GIR_RootConstrainSelectedInstOperands, |
| 14537 | /* 40134 */ // GIR_Coverage, 1446, |
| 14538 | /* 40134 */ GIR_EraseRootFromParent_Done, |
| 14539 | /* 40135 */ // Label 1165: @40135 |
| 14540 | /* 40135 */ GIM_Reject, |
| 14541 | /* 40136 */ // Label 1163: @40136 |
| 14542 | /* 40136 */ GIM_Reject, |
| 14543 | /* 40137 */ // Label 1159: @40137 |
| 14544 | /* 40137 */ GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(40204), |
| 14545 | /* 40142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14546 | /* 40145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14547 | /* 40149 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14548 | /* 40153 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1167*/ GIMT_Encode4(40178), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1445 // |
| 14549 | /* 40160 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4064:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 14550 | /* 40160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEq), |
| 14551 | /* 40163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14552 | /* 40165 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14553 | /* 40167 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14554 | /* 40170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14555 | /* 40176 */ GIR_RootConstrainSelectedInstOperands, |
| 14556 | /* 40177 */ // GIR_Coverage, 1445, |
| 14557 | /* 40177 */ GIR_EraseRootFromParent_Done, |
| 14558 | /* 40178 */ // Label 1167: @40178 |
| 14559 | /* 40178 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1168*/ GIMT_Encode4(40203), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1447 // |
| 14560 | /* 40185 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4064:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 14561 | /* 40185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfq), |
| 14562 | /* 40188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14563 | /* 40190 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14564 | /* 40192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14565 | /* 40195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14566 | /* 40201 */ GIR_RootConstrainSelectedInstOperands, |
| 14567 | /* 40202 */ // GIR_Coverage, 1447, |
| 14568 | /* 40202 */ GIR_EraseRootFromParent_Done, |
| 14569 | /* 40203 */ // Label 1168: @40203 |
| 14570 | /* 40203 */ GIM_Reject, |
| 14571 | /* 40204 */ // Label 1166: @40204 |
| 14572 | /* 40204 */ GIM_Reject, |
| 14573 | /* 40205 */ // Label 1160: @40205 |
| 14574 | /* 40205 */ GIM_Reject, |
| 14575 | /* 40206 */ // Label 1155: @40206 |
| 14576 | /* 40206 */ GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(40454), |
| 14577 | /* 40211 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 14578 | /* 40216 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1174*/ GIMT_Encode4(40453), |
| 14579 | /* 40227 */ /*GILLT_v4s16*//*Label 1170*/ GIMT_Encode4(40243), |
| 14580 | /* 40231 */ /*GILLT_v8s16*//*Label 1171*/ GIMT_Encode4(40280), |
| 14581 | /* 40235 */ /*GILLT_v2s32*//*Label 1172*/ GIMT_Encode4(40317), |
| 14582 | /* 40239 */ /*GILLT_v4s32*//*Label 1173*/ GIMT_Encode4(40385), |
| 14583 | /* 40243 */ // Label 1170: @40243 |
| 14584 | /* 40243 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1175*/ GIMT_Encode4(40279), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1458 // |
| 14585 | /* 40250 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14586 | /* 40253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14587 | /* 40257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14588 | /* 40261 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4071:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 14589 | /* 40261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhd), |
| 14590 | /* 40264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14591 | /* 40266 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14592 | /* 40268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14593 | /* 40271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14594 | /* 40277 */ GIR_RootConstrainSelectedInstOperands, |
| 14595 | /* 40278 */ // GIR_Coverage, 1458, |
| 14596 | /* 40278 */ GIR_EraseRootFromParent_Done, |
| 14597 | /* 40279 */ // Label 1175: @40279 |
| 14598 | /* 40279 */ GIM_Reject, |
| 14599 | /* 40280 */ // Label 1171: @40280 |
| 14600 | /* 40280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1176*/ GIMT_Encode4(40316), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1459 // |
| 14601 | /* 40287 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14602 | /* 40290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14603 | /* 40294 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14604 | /* 40298 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4071:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 14605 | /* 40298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhq), |
| 14606 | /* 40301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14607 | /* 40303 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14608 | /* 40305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14609 | /* 40308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14610 | /* 40314 */ GIR_RootConstrainSelectedInstOperands, |
| 14611 | /* 40315 */ // GIR_Coverage, 1459, |
| 14612 | /* 40315 */ GIR_EraseRootFromParent_Done, |
| 14613 | /* 40316 */ // Label 1176: @40316 |
| 14614 | /* 40316 */ GIM_Reject, |
| 14615 | /* 40317 */ // Label 1172: @40317 |
| 14616 | /* 40317 */ GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(40384), |
| 14617 | /* 40322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14618 | /* 40325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14619 | /* 40329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14620 | /* 40333 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1178*/ GIMT_Encode4(40358), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1454 // |
| 14621 | /* 40340 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4071:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 14622 | /* 40340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEd), |
| 14623 | /* 40343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14624 | /* 40345 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14625 | /* 40347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14626 | /* 40350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14627 | /* 40356 */ GIR_RootConstrainSelectedInstOperands, |
| 14628 | /* 40357 */ // GIR_Coverage, 1454, |
| 14629 | /* 40357 */ GIR_EraseRootFromParent_Done, |
| 14630 | /* 40358 */ // Label 1178: @40358 |
| 14631 | /* 40358 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1179*/ GIMT_Encode4(40383), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1456 // |
| 14632 | /* 40365 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4071:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 14633 | /* 40365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfd), |
| 14634 | /* 40368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14635 | /* 40370 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14636 | /* 40372 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14637 | /* 40375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14638 | /* 40381 */ GIR_RootConstrainSelectedInstOperands, |
| 14639 | /* 40382 */ // GIR_Coverage, 1456, |
| 14640 | /* 40382 */ GIR_EraseRootFromParent_Done, |
| 14641 | /* 40383 */ // Label 1179: @40383 |
| 14642 | /* 40383 */ GIM_Reject, |
| 14643 | /* 40384 */ // Label 1177: @40384 |
| 14644 | /* 40384 */ GIM_Reject, |
| 14645 | /* 40385 */ // Label 1173: @40385 |
| 14646 | /* 40385 */ GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(40452), |
| 14647 | /* 40390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14648 | /* 40393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14649 | /* 40397 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14650 | /* 40401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1181*/ GIMT_Encode4(40426), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1455 // |
| 14651 | /* 40408 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4071:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 14652 | /* 40408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEq), |
| 14653 | /* 40411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14654 | /* 40413 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14655 | /* 40415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14656 | /* 40418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14657 | /* 40424 */ GIR_RootConstrainSelectedInstOperands, |
| 14658 | /* 40425 */ // GIR_Coverage, 1455, |
| 14659 | /* 40425 */ GIR_EraseRootFromParent_Done, |
| 14660 | /* 40426 */ // Label 1181: @40426 |
| 14661 | /* 40426 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1182*/ GIMT_Encode4(40451), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1457 // |
| 14662 | /* 40433 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4071:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 14663 | /* 40433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfq), |
| 14664 | /* 40436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14665 | /* 40438 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14666 | /* 40440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14667 | /* 40443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14668 | /* 40449 */ GIR_RootConstrainSelectedInstOperands, |
| 14669 | /* 40450 */ // GIR_Coverage, 1457, |
| 14670 | /* 40450 */ GIR_EraseRootFromParent_Done, |
| 14671 | /* 40451 */ // Label 1182: @40451 |
| 14672 | /* 40451 */ GIM_Reject, |
| 14673 | /* 40452 */ // Label 1180: @40452 |
| 14674 | /* 40452 */ GIM_Reject, |
| 14675 | /* 40453 */ // Label 1174: @40453 |
| 14676 | /* 40453 */ GIM_Reject, |
| 14677 | /* 40454 */ // Label 1169: @40454 |
| 14678 | /* 40454 */ GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(40722), |
| 14679 | /* 40459 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 14680 | /* 40464 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1190*/ GIMT_Encode4(40721), |
| 14681 | /* 40475 */ /*GILLT_v8s8*//*Label 1184*/ GIMT_Encode4(40499), |
| 14682 | /* 40479 */ /*GILLT_v16s8*//*Label 1185*/ GIMT_Encode4(40536), |
| 14683 | /* 40483 */ /*GILLT_v4s16*//*Label 1186*/ GIMT_Encode4(40573), |
| 14684 | /* 40487 */ /*GILLT_v8s16*//*Label 1187*/ GIMT_Encode4(40610), |
| 14685 | /* 40491 */ /*GILLT_v2s32*//*Label 1188*/ GIMT_Encode4(40647), |
| 14686 | /* 40495 */ /*GILLT_v4s32*//*Label 1189*/ GIMT_Encode4(40684), |
| 14687 | /* 40499 */ // Label 1184: @40499 |
| 14688 | /* 40499 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1191*/ GIMT_Encode4(40535), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1680 // |
| 14689 | /* 40506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 14690 | /* 40509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14691 | /* 40513 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14692 | /* 40517 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4042:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 14693 | /* 40517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i8), |
| 14694 | /* 40520 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14695 | /* 40522 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14696 | /* 40524 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14697 | /* 40527 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14698 | /* 40533 */ GIR_RootConstrainSelectedInstOperands, |
| 14699 | /* 40534 */ // GIR_Coverage, 1680, |
| 14700 | /* 40534 */ GIR_EraseRootFromParent_Done, |
| 14701 | /* 40535 */ // Label 1191: @40535 |
| 14702 | /* 40535 */ GIM_Reject, |
| 14703 | /* 40536 */ // Label 1185: @40536 |
| 14704 | /* 40536 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1192*/ GIMT_Encode4(40572), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1683 // |
| 14705 | /* 40543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14706 | /* 40546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14707 | /* 40550 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14708 | /* 40554 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4042:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 14709 | /* 40554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv16i8), |
| 14710 | /* 40557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14711 | /* 40559 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14712 | /* 40561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14713 | /* 40564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14714 | /* 40570 */ GIR_RootConstrainSelectedInstOperands, |
| 14715 | /* 40571 */ // GIR_Coverage, 1683, |
| 14716 | /* 40571 */ GIR_EraseRootFromParent_Done, |
| 14717 | /* 40572 */ // Label 1192: @40572 |
| 14718 | /* 40572 */ GIM_Reject, |
| 14719 | /* 40573 */ // Label 1186: @40573 |
| 14720 | /* 40573 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1193*/ GIMT_Encode4(40609), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1681 // |
| 14721 | /* 40580 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14722 | /* 40583 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14723 | /* 40587 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14724 | /* 40591 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4042:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 14725 | /* 40591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i16), |
| 14726 | /* 40594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14727 | /* 40596 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14728 | /* 40598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14729 | /* 40601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14730 | /* 40607 */ GIR_RootConstrainSelectedInstOperands, |
| 14731 | /* 40608 */ // GIR_Coverage, 1681, |
| 14732 | /* 40608 */ GIR_EraseRootFromParent_Done, |
| 14733 | /* 40609 */ // Label 1193: @40609 |
| 14734 | /* 40609 */ GIM_Reject, |
| 14735 | /* 40610 */ // Label 1187: @40610 |
| 14736 | /* 40610 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1194*/ GIMT_Encode4(40646), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1684 // |
| 14737 | /* 40617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14738 | /* 40620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14739 | /* 40624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14740 | /* 40628 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4042:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 14741 | /* 40628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i16), |
| 14742 | /* 40631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14743 | /* 40633 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14744 | /* 40635 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14745 | /* 40638 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14746 | /* 40644 */ GIR_RootConstrainSelectedInstOperands, |
| 14747 | /* 40645 */ // GIR_Coverage, 1684, |
| 14748 | /* 40645 */ GIR_EraseRootFromParent_Done, |
| 14749 | /* 40646 */ // Label 1194: @40646 |
| 14750 | /* 40646 */ GIM_Reject, |
| 14751 | /* 40647 */ // Label 1188: @40647 |
| 14752 | /* 40647 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1195*/ GIMT_Encode4(40683), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1682 // |
| 14753 | /* 40654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14754 | /* 40657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14755 | /* 40661 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14756 | /* 40665 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4042:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 14757 | /* 40665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv2i32), |
| 14758 | /* 40668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14759 | /* 40670 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14760 | /* 40672 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14761 | /* 40675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14762 | /* 40681 */ GIR_RootConstrainSelectedInstOperands, |
| 14763 | /* 40682 */ // GIR_Coverage, 1682, |
| 14764 | /* 40682 */ GIR_EraseRootFromParent_Done, |
| 14765 | /* 40683 */ // Label 1195: @40683 |
| 14766 | /* 40683 */ GIM_Reject, |
| 14767 | /* 40684 */ // Label 1189: @40684 |
| 14768 | /* 40684 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1196*/ GIMT_Encode4(40720), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1685 // |
| 14769 | /* 40691 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14770 | /* 40694 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14771 | /* 40698 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14772 | /* 40702 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4042:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 14773 | /* 40702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i32), |
| 14774 | /* 40705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14775 | /* 40707 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14776 | /* 40709 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14777 | /* 40712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14778 | /* 40718 */ GIR_RootConstrainSelectedInstOperands, |
| 14779 | /* 40719 */ // GIR_Coverage, 1685, |
| 14780 | /* 40719 */ GIR_EraseRootFromParent_Done, |
| 14781 | /* 40720 */ // Label 1196: @40720 |
| 14782 | /* 40720 */ GIM_Reject, |
| 14783 | /* 40721 */ // Label 1190: @40721 |
| 14784 | /* 40721 */ GIM_Reject, |
| 14785 | /* 40722 */ // Label 1183: @40722 |
| 14786 | /* 40722 */ GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(40990), |
| 14787 | /* 40727 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 14788 | /* 40732 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1204*/ GIMT_Encode4(40989), |
| 14789 | /* 40743 */ /*GILLT_v8s8*//*Label 1198*/ GIMT_Encode4(40767), |
| 14790 | /* 40747 */ /*GILLT_v16s8*//*Label 1199*/ GIMT_Encode4(40804), |
| 14791 | /* 40751 */ /*GILLT_v4s16*//*Label 1200*/ GIMT_Encode4(40841), |
| 14792 | /* 40755 */ /*GILLT_v8s16*//*Label 1201*/ GIMT_Encode4(40878), |
| 14793 | /* 40759 */ /*GILLT_v2s32*//*Label 1202*/ GIMT_Encode4(40915), |
| 14794 | /* 40763 */ /*GILLT_v4s32*//*Label 1203*/ GIMT_Encode4(40952), |
| 14795 | /* 40767 */ // Label 1198: @40767 |
| 14796 | /* 40767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1205*/ GIMT_Encode4(40803), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1696 // |
| 14797 | /* 40774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 14798 | /* 40777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14799 | /* 40781 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14800 | /* 40785 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4048:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQNEGv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 14801 | /* 40785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i8), |
| 14802 | /* 40788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14803 | /* 40790 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14804 | /* 40792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14805 | /* 40795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14806 | /* 40801 */ GIR_RootConstrainSelectedInstOperands, |
| 14807 | /* 40802 */ // GIR_Coverage, 1696, |
| 14808 | /* 40802 */ GIR_EraseRootFromParent_Done, |
| 14809 | /* 40803 */ // Label 1205: @40803 |
| 14810 | /* 40803 */ GIM_Reject, |
| 14811 | /* 40804 */ // Label 1199: @40804 |
| 14812 | /* 40804 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1206*/ GIMT_Encode4(40840), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1699 // |
| 14813 | /* 40811 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14814 | /* 40814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14815 | /* 40818 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14816 | /* 40822 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4048:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQNEGv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 14817 | /* 40822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv16i8), |
| 14818 | /* 40825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14819 | /* 40827 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14820 | /* 40829 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14821 | /* 40832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14822 | /* 40838 */ GIR_RootConstrainSelectedInstOperands, |
| 14823 | /* 40839 */ // GIR_Coverage, 1699, |
| 14824 | /* 40839 */ GIR_EraseRootFromParent_Done, |
| 14825 | /* 40840 */ // Label 1206: @40840 |
| 14826 | /* 40840 */ GIM_Reject, |
| 14827 | /* 40841 */ // Label 1200: @40841 |
| 14828 | /* 40841 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1207*/ GIMT_Encode4(40877), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1697 // |
| 14829 | /* 40848 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14830 | /* 40851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14831 | /* 40855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14832 | /* 40859 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4048:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQNEGv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 14833 | /* 40859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i16), |
| 14834 | /* 40862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14835 | /* 40864 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14836 | /* 40866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14837 | /* 40869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14838 | /* 40875 */ GIR_RootConstrainSelectedInstOperands, |
| 14839 | /* 40876 */ // GIR_Coverage, 1697, |
| 14840 | /* 40876 */ GIR_EraseRootFromParent_Done, |
| 14841 | /* 40877 */ // Label 1207: @40877 |
| 14842 | /* 40877 */ GIM_Reject, |
| 14843 | /* 40878 */ // Label 1201: @40878 |
| 14844 | /* 40878 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1208*/ GIMT_Encode4(40914), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1700 // |
| 14845 | /* 40885 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14846 | /* 40888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14847 | /* 40892 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14848 | /* 40896 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4048:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQNEGv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 14849 | /* 40896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i16), |
| 14850 | /* 40899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14851 | /* 40901 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14852 | /* 40903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14853 | /* 40906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14854 | /* 40912 */ GIR_RootConstrainSelectedInstOperands, |
| 14855 | /* 40913 */ // GIR_Coverage, 1700, |
| 14856 | /* 40913 */ GIR_EraseRootFromParent_Done, |
| 14857 | /* 40914 */ // Label 1208: @40914 |
| 14858 | /* 40914 */ GIM_Reject, |
| 14859 | /* 40915 */ // Label 1202: @40915 |
| 14860 | /* 40915 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1209*/ GIMT_Encode4(40951), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1698 // |
| 14861 | /* 40922 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14862 | /* 40925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14863 | /* 40929 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14864 | /* 40933 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4048:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQNEGv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 14865 | /* 40933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv2i32), |
| 14866 | /* 40936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14867 | /* 40938 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14868 | /* 40940 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14869 | /* 40943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14870 | /* 40949 */ GIR_RootConstrainSelectedInstOperands, |
| 14871 | /* 40950 */ // GIR_Coverage, 1698, |
| 14872 | /* 40950 */ GIR_EraseRootFromParent_Done, |
| 14873 | /* 40951 */ // Label 1209: @40951 |
| 14874 | /* 40951 */ GIM_Reject, |
| 14875 | /* 40952 */ // Label 1203: @40952 |
| 14876 | /* 40952 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1210*/ GIMT_Encode4(40988), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1701 // |
| 14877 | /* 40959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14878 | /* 40962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14879 | /* 40966 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14880 | /* 40970 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4048:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQNEGv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 14881 | /* 40970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i32), |
| 14882 | /* 40973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14883 | /* 40975 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14884 | /* 40977 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14885 | /* 40980 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14886 | /* 40986 */ GIR_RootConstrainSelectedInstOperands, |
| 14887 | /* 40987 */ // GIR_Coverage, 1701, |
| 14888 | /* 40987 */ GIR_EraseRootFromParent_Done, |
| 14889 | /* 40988 */ // Label 1210: @40988 |
| 14890 | /* 40988 */ GIM_Reject, |
| 14891 | /* 40989 */ // Label 1204: @40989 |
| 14892 | /* 40989 */ GIM_Reject, |
| 14893 | /* 40990 */ // Label 1197: @40990 |
| 14894 | /* 40990 */ GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(41143), |
| 14895 | /* 40995 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns), |
| 14896 | /* 41000 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1215*/ GIMT_Encode4(41142), |
| 14897 | /* 41011 */ /*GILLT_v8s8*//*Label 1212*/ GIMT_Encode4(41031), GIMT_Encode4(0), |
| 14898 | /* 41019 */ /*GILLT_v4s16*//*Label 1213*/ GIMT_Encode4(41068), GIMT_Encode4(0), |
| 14899 | /* 41027 */ /*GILLT_v2s32*//*Label 1214*/ GIMT_Encode4(41105), |
| 14900 | /* 41031 */ // Label 1212: @41031 |
| 14901 | /* 41031 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1216*/ GIMT_Encode4(41067), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1751 // |
| 14902 | /* 41038 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14903 | /* 41041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14904 | /* 41045 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14905 | /* 41049 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4045:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 14906 | /* 41049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv8i8), |
| 14907 | /* 41052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14908 | /* 41054 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14909 | /* 41056 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14910 | /* 41059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14911 | /* 41065 */ GIR_RootConstrainSelectedInstOperands, |
| 14912 | /* 41066 */ // GIR_Coverage, 1751, |
| 14913 | /* 41066 */ GIR_EraseRootFromParent_Done, |
| 14914 | /* 41067 */ // Label 1216: @41067 |
| 14915 | /* 41067 */ GIM_Reject, |
| 14916 | /* 41068 */ // Label 1213: @41068 |
| 14917 | /* 41068 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1217*/ GIMT_Encode4(41104), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1752 // |
| 14918 | /* 41075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14919 | /* 41078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14920 | /* 41082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14921 | /* 41086 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4045:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 14922 | /* 41086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv4i16), |
| 14923 | /* 41089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14924 | /* 41091 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14925 | /* 41093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14926 | /* 41096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14927 | /* 41102 */ GIR_RootConstrainSelectedInstOperands, |
| 14928 | /* 41103 */ // GIR_Coverage, 1752, |
| 14929 | /* 41103 */ GIR_EraseRootFromParent_Done, |
| 14930 | /* 41104 */ // Label 1217: @41104 |
| 14931 | /* 41104 */ GIM_Reject, |
| 14932 | /* 41105 */ // Label 1214: @41105 |
| 14933 | /* 41105 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1218*/ GIMT_Encode4(41141), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1753 // |
| 14934 | /* 41112 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 14935 | /* 41115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14936 | /* 41119 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14937 | /* 41123 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4045:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 14938 | /* 41123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv2i32), |
| 14939 | /* 41126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14940 | /* 41128 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14941 | /* 41130 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14942 | /* 41133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14943 | /* 41139 */ GIR_RootConstrainSelectedInstOperands, |
| 14944 | /* 41140 */ // GIR_Coverage, 1753, |
| 14945 | /* 41140 */ GIR_EraseRootFromParent_Done, |
| 14946 | /* 41141 */ // Label 1218: @41141 |
| 14947 | /* 41141 */ GIM_Reject, |
| 14948 | /* 41142 */ // Label 1215: @41142 |
| 14949 | /* 41142 */ GIM_Reject, |
| 14950 | /* 41143 */ // Label 1211: @41143 |
| 14951 | /* 41143 */ GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(41296), |
| 14952 | /* 41148 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu), |
| 14953 | /* 41153 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1223*/ GIMT_Encode4(41295), |
| 14954 | /* 41164 */ /*GILLT_v8s8*//*Label 1220*/ GIMT_Encode4(41184), GIMT_Encode4(0), |
| 14955 | /* 41172 */ /*GILLT_v4s16*//*Label 1221*/ GIMT_Encode4(41221), GIMT_Encode4(0), |
| 14956 | /* 41180 */ /*GILLT_v2s32*//*Label 1222*/ GIMT_Encode4(41258), |
| 14957 | /* 41184 */ // Label 1220: @41184 |
| 14958 | /* 41184 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1224*/ GIMT_Encode4(41220), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1754 // |
| 14959 | /* 41191 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14960 | /* 41194 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14961 | /* 41198 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14962 | /* 41202 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4047:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 14963 | /* 41202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv8i8), |
| 14964 | /* 41205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14965 | /* 41207 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14966 | /* 41209 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14967 | /* 41212 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14968 | /* 41218 */ GIR_RootConstrainSelectedInstOperands, |
| 14969 | /* 41219 */ // GIR_Coverage, 1754, |
| 14970 | /* 41219 */ GIR_EraseRootFromParent_Done, |
| 14971 | /* 41220 */ // Label 1224: @41220 |
| 14972 | /* 41220 */ GIM_Reject, |
| 14973 | /* 41221 */ // Label 1221: @41221 |
| 14974 | /* 41221 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1225*/ GIMT_Encode4(41257), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1755 // |
| 14975 | /* 41228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14976 | /* 41231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14977 | /* 41235 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14978 | /* 41239 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4047:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 14979 | /* 41239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv4i16), |
| 14980 | /* 41242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14981 | /* 41244 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14982 | /* 41246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14983 | /* 41249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14984 | /* 41255 */ GIR_RootConstrainSelectedInstOperands, |
| 14985 | /* 41256 */ // GIR_Coverage, 1755, |
| 14986 | /* 41256 */ GIR_EraseRootFromParent_Done, |
| 14987 | /* 41257 */ // Label 1225: @41257 |
| 14988 | /* 41257 */ GIM_Reject, |
| 14989 | /* 41258 */ // Label 1222: @41258 |
| 14990 | /* 41258 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1226*/ GIMT_Encode4(41294), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1756 // |
| 14991 | /* 41265 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 14992 | /* 41268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14993 | /* 41272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14994 | /* 41276 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4047:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 14995 | /* 41276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv2i32), |
| 14996 | /* 41279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14997 | /* 41281 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14998 | /* 41283 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14999 | /* 41286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15000 | /* 41292 */ GIR_RootConstrainSelectedInstOperands, |
| 15001 | /* 41293 */ // GIR_Coverage, 1756, |
| 15002 | /* 41293 */ GIR_EraseRootFromParent_Done, |
| 15003 | /* 41294 */ // Label 1226: @41294 |
| 15004 | /* 41294 */ GIM_Reject, |
| 15005 | /* 41295 */ // Label 1223: @41295 |
| 15006 | /* 41295 */ GIM_Reject, |
| 15007 | /* 41296 */ // Label 1219: @41296 |
| 15008 | /* 41296 */ GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(41449), |
| 15009 | /* 41301 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu), |
| 15010 | /* 41306 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1231*/ GIMT_Encode4(41448), |
| 15011 | /* 41317 */ /*GILLT_v8s8*//*Label 1228*/ GIMT_Encode4(41337), GIMT_Encode4(0), |
| 15012 | /* 41325 */ /*GILLT_v4s16*//*Label 1229*/ GIMT_Encode4(41374), GIMT_Encode4(0), |
| 15013 | /* 41333 */ /*GILLT_v2s32*//*Label 1230*/ GIMT_Encode4(41411), |
| 15014 | /* 41337 */ // Label 1228: @41337 |
| 15015 | /* 41337 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1232*/ GIMT_Encode4(41373), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1757 // |
| 15016 | /* 41344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15017 | /* 41347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15018 | /* 41351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15019 | /* 41355 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4046:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 15020 | /* 41355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv8i8), |
| 15021 | /* 41358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15022 | /* 41360 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15023 | /* 41362 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15024 | /* 41365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15025 | /* 41371 */ GIR_RootConstrainSelectedInstOperands, |
| 15026 | /* 41372 */ // GIR_Coverage, 1757, |
| 15027 | /* 41372 */ GIR_EraseRootFromParent_Done, |
| 15028 | /* 41373 */ // Label 1232: @41373 |
| 15029 | /* 41373 */ GIM_Reject, |
| 15030 | /* 41374 */ // Label 1229: @41374 |
| 15031 | /* 41374 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1233*/ GIMT_Encode4(41410), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1758 // |
| 15032 | /* 41381 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15033 | /* 41384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15034 | /* 41388 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15035 | /* 41392 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4046:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 15036 | /* 41392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv4i16), |
| 15037 | /* 41395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15038 | /* 41397 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15039 | /* 41399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15040 | /* 41402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15041 | /* 41408 */ GIR_RootConstrainSelectedInstOperands, |
| 15042 | /* 41409 */ // GIR_Coverage, 1758, |
| 15043 | /* 41409 */ GIR_EraseRootFromParent_Done, |
| 15044 | /* 41410 */ // Label 1233: @41410 |
| 15045 | /* 41410 */ GIM_Reject, |
| 15046 | /* 41411 */ // Label 1230: @41411 |
| 15047 | /* 41411 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1234*/ GIMT_Encode4(41447), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1759 // |
| 15048 | /* 41418 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 15049 | /* 41421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15050 | /* 41425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15051 | /* 41429 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4046:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 15052 | /* 41429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv2i32), |
| 15053 | /* 41432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15054 | /* 41434 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15055 | /* 41436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15056 | /* 41439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15057 | /* 41445 */ GIR_RootConstrainSelectedInstOperands, |
| 15058 | /* 41446 */ // GIR_Coverage, 1759, |
| 15059 | /* 41446 */ GIR_EraseRootFromParent_Done, |
| 15060 | /* 41447 */ // Label 1234: @41447 |
| 15061 | /* 41447 */ GIM_Reject, |
| 15062 | /* 41448 */ // Label 1231: @41448 |
| 15063 | /* 41448 */ GIM_Reject, |
| 15064 | /* 41449 */ // Label 1227: @41449 |
| 15065 | /* 41449 */ GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(41535), |
| 15066 | /* 41454 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 15067 | /* 41459 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1238*/ GIMT_Encode4(41534), |
| 15068 | /* 41470 */ /*GILLT_v2s32*//*Label 1236*/ GIMT_Encode4(41478), |
| 15069 | /* 41474 */ /*GILLT_v4s32*//*Label 1237*/ GIMT_Encode4(41506), |
| 15070 | /* 41478 */ // Label 1236: @41478 |
| 15071 | /* 41478 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1239*/ GIMT_Encode4(41505), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1782 // |
| 15072 | /* 41485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15073 | /* 41488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15074 | /* 41492 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15075 | /* 41496 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3990:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15076 | /* 41496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDf), |
| 15077 | /* 41499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15078 | /* 41501 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15079 | /* 41503 */ GIR_RootConstrainSelectedInstOperands, |
| 15080 | /* 41504 */ // GIR_Coverage, 1782, |
| 15081 | /* 41504 */ GIR_EraseRootFromParent_Done, |
| 15082 | /* 41505 */ // Label 1239: @41505 |
| 15083 | /* 41505 */ GIM_Reject, |
| 15084 | /* 41506 */ // Label 1237: @41506 |
| 15085 | /* 41506 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1240*/ GIMT_Encode4(41533), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1783 // |
| 15086 | /* 41513 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15087 | /* 41516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15088 | /* 41520 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15089 | /* 41524 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3990:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15090 | /* 41524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQf), |
| 15091 | /* 41527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15092 | /* 41529 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15093 | /* 41531 */ GIR_RootConstrainSelectedInstOperands, |
| 15094 | /* 41532 */ // GIR_Coverage, 1783, |
| 15095 | /* 41532 */ GIR_EraseRootFromParent_Done, |
| 15096 | /* 41533 */ // Label 1240: @41533 |
| 15097 | /* 41533 */ GIM_Reject, |
| 15098 | /* 41534 */ // Label 1238: @41534 |
| 15099 | /* 41534 */ GIM_Reject, |
| 15100 | /* 41535 */ // Label 1235: @41535 |
| 15101 | /* 41535 */ GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(41621), |
| 15102 | /* 41540 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 15103 | /* 41545 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1244*/ GIMT_Encode4(41620), |
| 15104 | /* 41556 */ /*GILLT_v2s32*//*Label 1242*/ GIMT_Encode4(41564), |
| 15105 | /* 41560 */ /*GILLT_v4s32*//*Label 1243*/ GIMT_Encode4(41592), |
| 15106 | /* 41564 */ // Label 1242: @41564 |
| 15107 | /* 41564 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1245*/ GIMT_Encode4(41591), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1784 // |
| 15108 | /* 41571 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15109 | /* 41574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15110 | /* 41578 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15111 | /* 41582 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3991:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15112 | /* 41582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDf), |
| 15113 | /* 41585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15114 | /* 41587 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15115 | /* 41589 */ GIR_RootConstrainSelectedInstOperands, |
| 15116 | /* 41590 */ // GIR_Coverage, 1784, |
| 15117 | /* 41590 */ GIR_EraseRootFromParent_Done, |
| 15118 | /* 41591 */ // Label 1245: @41591 |
| 15119 | /* 41591 */ GIM_Reject, |
| 15120 | /* 41592 */ // Label 1243: @41592 |
| 15121 | /* 41592 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1246*/ GIMT_Encode4(41619), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1785 // |
| 15122 | /* 41599 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15123 | /* 41602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15124 | /* 41606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15125 | /* 41610 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3991:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15126 | /* 41610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQf), |
| 15127 | /* 41613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15128 | /* 41615 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15129 | /* 41617 */ GIR_RootConstrainSelectedInstOperands, |
| 15130 | /* 41618 */ // GIR_Coverage, 1785, |
| 15131 | /* 41618 */ GIR_EraseRootFromParent_Done, |
| 15132 | /* 41619 */ // Label 1246: @41619 |
| 15133 | /* 41619 */ GIM_Reject, |
| 15134 | /* 41620 */ // Label 1244: @41620 |
| 15135 | /* 41620 */ GIM_Reject, |
| 15136 | /* 41621 */ // Label 1241: @41621 |
| 15137 | /* 41621 */ GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(41707), |
| 15138 | /* 41626 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 15139 | /* 41631 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1250*/ GIMT_Encode4(41706), |
| 15140 | /* 41642 */ /*GILLT_v4s16*//*Label 1248*/ GIMT_Encode4(41650), |
| 15141 | /* 41646 */ /*GILLT_v8s16*//*Label 1249*/ GIMT_Encode4(41678), |
| 15142 | /* 41650 */ // Label 1248: @41650 |
| 15143 | /* 41650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1251*/ GIMT_Encode4(41677), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1786 // |
| 15144 | /* 41657 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15145 | /* 41660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15146 | /* 41664 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15147 | /* 41668 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3990:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15148 | /* 41668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDh), |
| 15149 | /* 41671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15150 | /* 41673 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15151 | /* 41675 */ GIR_RootConstrainSelectedInstOperands, |
| 15152 | /* 41676 */ // GIR_Coverage, 1786, |
| 15153 | /* 41676 */ GIR_EraseRootFromParent_Done, |
| 15154 | /* 41677 */ // Label 1251: @41677 |
| 15155 | /* 41677 */ GIM_Reject, |
| 15156 | /* 41678 */ // Label 1249: @41678 |
| 15157 | /* 41678 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1252*/ GIMT_Encode4(41705), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1787 // |
| 15158 | /* 41685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15159 | /* 41688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15160 | /* 41692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15161 | /* 41696 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3990:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15162 | /* 41696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQh), |
| 15163 | /* 41699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15164 | /* 41701 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15165 | /* 41703 */ GIR_RootConstrainSelectedInstOperands, |
| 15166 | /* 41704 */ // GIR_Coverage, 1787, |
| 15167 | /* 41704 */ GIR_EraseRootFromParent_Done, |
| 15168 | /* 41705 */ // Label 1252: @41705 |
| 15169 | /* 41705 */ GIM_Reject, |
| 15170 | /* 41706 */ // Label 1250: @41706 |
| 15171 | /* 41706 */ GIM_Reject, |
| 15172 | /* 41707 */ // Label 1247: @41707 |
| 15173 | /* 41707 */ GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(41793), |
| 15174 | /* 41712 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 15175 | /* 41717 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1256*/ GIMT_Encode4(41792), |
| 15176 | /* 41728 */ /*GILLT_v4s16*//*Label 1254*/ GIMT_Encode4(41736), |
| 15177 | /* 41732 */ /*GILLT_v8s16*//*Label 1255*/ GIMT_Encode4(41764), |
| 15178 | /* 41736 */ // Label 1254: @41736 |
| 15179 | /* 41736 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1257*/ GIMT_Encode4(41763), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1788 // |
| 15180 | /* 41743 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15181 | /* 41746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15182 | /* 41750 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15183 | /* 41754 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3991:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15184 | /* 41754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDh), |
| 15185 | /* 41757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15186 | /* 41759 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15187 | /* 41761 */ GIR_RootConstrainSelectedInstOperands, |
| 15188 | /* 41762 */ // GIR_Coverage, 1788, |
| 15189 | /* 41762 */ GIR_EraseRootFromParent_Done, |
| 15190 | /* 41763 */ // Label 1257: @41763 |
| 15191 | /* 41763 */ GIM_Reject, |
| 15192 | /* 41764 */ // Label 1255: @41764 |
| 15193 | /* 41764 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1258*/ GIMT_Encode4(41791), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1789 // |
| 15194 | /* 41771 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15195 | /* 41774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15196 | /* 41778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15197 | /* 41782 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3991:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15198 | /* 41782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQh), |
| 15199 | /* 41785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15200 | /* 41787 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15201 | /* 41789 */ GIR_RootConstrainSelectedInstOperands, |
| 15202 | /* 41790 */ // GIR_Coverage, 1789, |
| 15203 | /* 41790 */ GIR_EraseRootFromParent_Done, |
| 15204 | /* 41791 */ // Label 1258: @41791 |
| 15205 | /* 41791 */ GIM_Reject, |
| 15206 | /* 41792 */ // Label 1256: @41792 |
| 15207 | /* 41792 */ GIM_Reject, |
| 15208 | /* 41793 */ // Label 1253: @41793 |
| 15209 | /* 41793 */ GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(41879), |
| 15210 | /* 41798 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 15211 | /* 41803 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1262*/ GIMT_Encode4(41878), |
| 15212 | /* 41814 */ /*GILLT_v2s32*//*Label 1260*/ GIMT_Encode4(41822), |
| 15213 | /* 41818 */ /*GILLT_v4s32*//*Label 1261*/ GIMT_Encode4(41850), |
| 15214 | /* 41822 */ // Label 1260: @41822 |
| 15215 | /* 41822 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1263*/ GIMT_Encode4(41849), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1790 // |
| 15216 | /* 41829 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15217 | /* 41832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15218 | /* 41836 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15219 | /* 41840 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4002:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15220 | /* 41840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDf), |
| 15221 | /* 41843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15222 | /* 41845 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15223 | /* 41847 */ GIR_RootConstrainSelectedInstOperands, |
| 15224 | /* 41848 */ // GIR_Coverage, 1790, |
| 15225 | /* 41848 */ GIR_EraseRootFromParent_Done, |
| 15226 | /* 41849 */ // Label 1263: @41849 |
| 15227 | /* 41849 */ GIM_Reject, |
| 15228 | /* 41850 */ // Label 1261: @41850 |
| 15229 | /* 41850 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1264*/ GIMT_Encode4(41877), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1791 // |
| 15230 | /* 41857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15231 | /* 41860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15232 | /* 41864 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15233 | /* 41868 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4002:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15234 | /* 41868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQf), |
| 15235 | /* 41871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15236 | /* 41873 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15237 | /* 41875 */ GIR_RootConstrainSelectedInstOperands, |
| 15238 | /* 41876 */ // GIR_Coverage, 1791, |
| 15239 | /* 41876 */ GIR_EraseRootFromParent_Done, |
| 15240 | /* 41877 */ // Label 1264: @41877 |
| 15241 | /* 41877 */ GIM_Reject, |
| 15242 | /* 41878 */ // Label 1262: @41878 |
| 15243 | /* 41878 */ GIM_Reject, |
| 15244 | /* 41879 */ // Label 1259: @41879 |
| 15245 | /* 41879 */ GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(41965), |
| 15246 | /* 41884 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 15247 | /* 41889 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1268*/ GIMT_Encode4(41964), |
| 15248 | /* 41900 */ /*GILLT_v2s32*//*Label 1266*/ GIMT_Encode4(41908), |
| 15249 | /* 41904 */ /*GILLT_v4s32*//*Label 1267*/ GIMT_Encode4(41936), |
| 15250 | /* 41908 */ // Label 1266: @41908 |
| 15251 | /* 41908 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1269*/ GIMT_Encode4(41935), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1792 // |
| 15252 | /* 41915 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15253 | /* 41918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15254 | /* 41922 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15255 | /* 41926 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4003:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15256 | /* 41926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDf), |
| 15257 | /* 41929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15258 | /* 41931 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15259 | /* 41933 */ GIR_RootConstrainSelectedInstOperands, |
| 15260 | /* 41934 */ // GIR_Coverage, 1792, |
| 15261 | /* 41934 */ GIR_EraseRootFromParent_Done, |
| 15262 | /* 41935 */ // Label 1269: @41935 |
| 15263 | /* 41935 */ GIM_Reject, |
| 15264 | /* 41936 */ // Label 1267: @41936 |
| 15265 | /* 41936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1270*/ GIMT_Encode4(41963), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1793 // |
| 15266 | /* 41943 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15267 | /* 41946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15268 | /* 41950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15269 | /* 41954 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4003:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15270 | /* 41954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQf), |
| 15271 | /* 41957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15272 | /* 41959 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15273 | /* 41961 */ GIR_RootConstrainSelectedInstOperands, |
| 15274 | /* 41962 */ // GIR_Coverage, 1793, |
| 15275 | /* 41962 */ GIR_EraseRootFromParent_Done, |
| 15276 | /* 41963 */ // Label 1270: @41963 |
| 15277 | /* 41963 */ GIM_Reject, |
| 15278 | /* 41964 */ // Label 1268: @41964 |
| 15279 | /* 41964 */ GIM_Reject, |
| 15280 | /* 41965 */ // Label 1265: @41965 |
| 15281 | /* 41965 */ GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(42051), |
| 15282 | /* 41970 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 15283 | /* 41975 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1274*/ GIMT_Encode4(42050), |
| 15284 | /* 41986 */ /*GILLT_v4s16*//*Label 1272*/ GIMT_Encode4(41994), |
| 15285 | /* 41990 */ /*GILLT_v8s16*//*Label 1273*/ GIMT_Encode4(42022), |
| 15286 | /* 41994 */ // Label 1272: @41994 |
| 15287 | /* 41994 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1275*/ GIMT_Encode4(42021), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1794 // |
| 15288 | /* 42001 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15289 | /* 42004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15290 | /* 42008 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15291 | /* 42012 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4002:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15292 | /* 42012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDh), |
| 15293 | /* 42015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15294 | /* 42017 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15295 | /* 42019 */ GIR_RootConstrainSelectedInstOperands, |
| 15296 | /* 42020 */ // GIR_Coverage, 1794, |
| 15297 | /* 42020 */ GIR_EraseRootFromParent_Done, |
| 15298 | /* 42021 */ // Label 1275: @42021 |
| 15299 | /* 42021 */ GIM_Reject, |
| 15300 | /* 42022 */ // Label 1273: @42022 |
| 15301 | /* 42022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1276*/ GIMT_Encode4(42049), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1795 // |
| 15302 | /* 42029 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15303 | /* 42032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15304 | /* 42036 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15305 | /* 42040 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4002:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15306 | /* 42040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQh), |
| 15307 | /* 42043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15308 | /* 42045 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15309 | /* 42047 */ GIR_RootConstrainSelectedInstOperands, |
| 15310 | /* 42048 */ // GIR_Coverage, 1795, |
| 15311 | /* 42048 */ GIR_EraseRootFromParent_Done, |
| 15312 | /* 42049 */ // Label 1276: @42049 |
| 15313 | /* 42049 */ GIM_Reject, |
| 15314 | /* 42050 */ // Label 1274: @42050 |
| 15315 | /* 42050 */ GIM_Reject, |
| 15316 | /* 42051 */ // Label 1271: @42051 |
| 15317 | /* 42051 */ GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(42137), |
| 15318 | /* 42056 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 15319 | /* 42061 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1280*/ GIMT_Encode4(42136), |
| 15320 | /* 42072 */ /*GILLT_v4s16*//*Label 1278*/ GIMT_Encode4(42080), |
| 15321 | /* 42076 */ /*GILLT_v8s16*//*Label 1279*/ GIMT_Encode4(42108), |
| 15322 | /* 42080 */ // Label 1278: @42080 |
| 15323 | /* 42080 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1281*/ GIMT_Encode4(42107), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1796 // |
| 15324 | /* 42087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15325 | /* 42090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15326 | /* 42094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15327 | /* 42098 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4003:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15328 | /* 42098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDh), |
| 15329 | /* 42101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15330 | /* 42103 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15331 | /* 42105 */ GIR_RootConstrainSelectedInstOperands, |
| 15332 | /* 42106 */ // GIR_Coverage, 1796, |
| 15333 | /* 42106 */ GIR_EraseRootFromParent_Done, |
| 15334 | /* 42107 */ // Label 1281: @42107 |
| 15335 | /* 42107 */ GIM_Reject, |
| 15336 | /* 42108 */ // Label 1279: @42108 |
| 15337 | /* 42108 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1282*/ GIMT_Encode4(42135), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1797 // |
| 15338 | /* 42115 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15339 | /* 42118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15340 | /* 42122 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15341 | /* 42126 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4003:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15342 | /* 42126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQh), |
| 15343 | /* 42129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15344 | /* 42131 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15345 | /* 42133 */ GIR_RootConstrainSelectedInstOperands, |
| 15346 | /* 42134 */ // GIR_Coverage, 1797, |
| 15347 | /* 42134 */ GIR_EraseRootFromParent_Done, |
| 15348 | /* 42135 */ // Label 1282: @42135 |
| 15349 | /* 42135 */ GIM_Reject, |
| 15350 | /* 42136 */ // Label 1280: @42136 |
| 15351 | /* 42136 */ GIM_Reject, |
| 15352 | /* 42137 */ // Label 1277: @42137 |
| 15353 | /* 42137 */ GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(42223), |
| 15354 | /* 42142 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 15355 | /* 42147 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1286*/ GIMT_Encode4(42222), |
| 15356 | /* 42158 */ /*GILLT_v2s32*//*Label 1284*/ GIMT_Encode4(42166), |
| 15357 | /* 42162 */ /*GILLT_v4s32*//*Label 1285*/ GIMT_Encode4(42194), |
| 15358 | /* 42166 */ // Label 1284: @42166 |
| 15359 | /* 42166 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1287*/ GIMT_Encode4(42193), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1798 // |
| 15360 | /* 42173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15361 | /* 42176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15362 | /* 42180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15363 | /* 42184 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4004:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15364 | /* 42184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDf), |
| 15365 | /* 42187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15366 | /* 42189 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15367 | /* 42191 */ GIR_RootConstrainSelectedInstOperands, |
| 15368 | /* 42192 */ // GIR_Coverage, 1798, |
| 15369 | /* 42192 */ GIR_EraseRootFromParent_Done, |
| 15370 | /* 42193 */ // Label 1287: @42193 |
| 15371 | /* 42193 */ GIM_Reject, |
| 15372 | /* 42194 */ // Label 1285: @42194 |
| 15373 | /* 42194 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1288*/ GIMT_Encode4(42221), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1799 // |
| 15374 | /* 42201 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15375 | /* 42204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15376 | /* 42208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15377 | /* 42212 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4004:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15378 | /* 42212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQf), |
| 15379 | /* 42215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15380 | /* 42217 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15381 | /* 42219 */ GIR_RootConstrainSelectedInstOperands, |
| 15382 | /* 42220 */ // GIR_Coverage, 1799, |
| 15383 | /* 42220 */ GIR_EraseRootFromParent_Done, |
| 15384 | /* 42221 */ // Label 1288: @42221 |
| 15385 | /* 42221 */ GIM_Reject, |
| 15386 | /* 42222 */ // Label 1286: @42222 |
| 15387 | /* 42222 */ GIM_Reject, |
| 15388 | /* 42223 */ // Label 1283: @42223 |
| 15389 | /* 42223 */ GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(42309), |
| 15390 | /* 42228 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 15391 | /* 42233 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1292*/ GIMT_Encode4(42308), |
| 15392 | /* 42244 */ /*GILLT_v2s32*//*Label 1290*/ GIMT_Encode4(42252), |
| 15393 | /* 42248 */ /*GILLT_v4s32*//*Label 1291*/ GIMT_Encode4(42280), |
| 15394 | /* 42252 */ // Label 1290: @42252 |
| 15395 | /* 42252 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1293*/ GIMT_Encode4(42279), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1800 // |
| 15396 | /* 42259 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15397 | /* 42262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15398 | /* 42266 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15399 | /* 42270 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4005:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15400 | /* 42270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDf), |
| 15401 | /* 42273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15402 | /* 42275 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15403 | /* 42277 */ GIR_RootConstrainSelectedInstOperands, |
| 15404 | /* 42278 */ // GIR_Coverage, 1800, |
| 15405 | /* 42278 */ GIR_EraseRootFromParent_Done, |
| 15406 | /* 42279 */ // Label 1293: @42279 |
| 15407 | /* 42279 */ GIM_Reject, |
| 15408 | /* 42280 */ // Label 1291: @42280 |
| 15409 | /* 42280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1294*/ GIMT_Encode4(42307), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1801 // |
| 15410 | /* 42287 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15411 | /* 42290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15412 | /* 42294 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15413 | /* 42298 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4005:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15414 | /* 42298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQf), |
| 15415 | /* 42301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15416 | /* 42303 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15417 | /* 42305 */ GIR_RootConstrainSelectedInstOperands, |
| 15418 | /* 42306 */ // GIR_Coverage, 1801, |
| 15419 | /* 42306 */ GIR_EraseRootFromParent_Done, |
| 15420 | /* 42307 */ // Label 1294: @42307 |
| 15421 | /* 42307 */ GIM_Reject, |
| 15422 | /* 42308 */ // Label 1292: @42308 |
| 15423 | /* 42308 */ GIM_Reject, |
| 15424 | /* 42309 */ // Label 1289: @42309 |
| 15425 | /* 42309 */ GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(42395), |
| 15426 | /* 42314 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 15427 | /* 42319 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1298*/ GIMT_Encode4(42394), |
| 15428 | /* 42330 */ /*GILLT_v4s16*//*Label 1296*/ GIMT_Encode4(42338), |
| 15429 | /* 42334 */ /*GILLT_v8s16*//*Label 1297*/ GIMT_Encode4(42366), |
| 15430 | /* 42338 */ // Label 1296: @42338 |
| 15431 | /* 42338 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1299*/ GIMT_Encode4(42365), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1802 // |
| 15432 | /* 42345 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15433 | /* 42348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15434 | /* 42352 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15435 | /* 42356 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4004:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15436 | /* 42356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDh), |
| 15437 | /* 42359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15438 | /* 42361 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15439 | /* 42363 */ GIR_RootConstrainSelectedInstOperands, |
| 15440 | /* 42364 */ // GIR_Coverage, 1802, |
| 15441 | /* 42364 */ GIR_EraseRootFromParent_Done, |
| 15442 | /* 42365 */ // Label 1299: @42365 |
| 15443 | /* 42365 */ GIM_Reject, |
| 15444 | /* 42366 */ // Label 1297: @42366 |
| 15445 | /* 42366 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1300*/ GIMT_Encode4(42393), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1803 // |
| 15446 | /* 42373 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15447 | /* 42376 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15448 | /* 42380 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15449 | /* 42384 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4004:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15450 | /* 42384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQh), |
| 15451 | /* 42387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15452 | /* 42389 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15453 | /* 42391 */ GIR_RootConstrainSelectedInstOperands, |
| 15454 | /* 42392 */ // GIR_Coverage, 1803, |
| 15455 | /* 42392 */ GIR_EraseRootFromParent_Done, |
| 15456 | /* 42393 */ // Label 1300: @42393 |
| 15457 | /* 42393 */ GIM_Reject, |
| 15458 | /* 42394 */ // Label 1298: @42394 |
| 15459 | /* 42394 */ GIM_Reject, |
| 15460 | /* 42395 */ // Label 1295: @42395 |
| 15461 | /* 42395 */ GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(42481), |
| 15462 | /* 42400 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 15463 | /* 42405 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1304*/ GIMT_Encode4(42480), |
| 15464 | /* 42416 */ /*GILLT_v4s16*//*Label 1302*/ GIMT_Encode4(42424), |
| 15465 | /* 42420 */ /*GILLT_v8s16*//*Label 1303*/ GIMT_Encode4(42452), |
| 15466 | /* 42424 */ // Label 1302: @42424 |
| 15467 | /* 42424 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1305*/ GIMT_Encode4(42451), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1804 // |
| 15468 | /* 42431 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15469 | /* 42434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15470 | /* 42438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15471 | /* 42442 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4005:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15472 | /* 42442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDh), |
| 15473 | /* 42445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15474 | /* 42447 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15475 | /* 42449 */ GIR_RootConstrainSelectedInstOperands, |
| 15476 | /* 42450 */ // GIR_Coverage, 1804, |
| 15477 | /* 42450 */ GIR_EraseRootFromParent_Done, |
| 15478 | /* 42451 */ // Label 1305: @42451 |
| 15479 | /* 42451 */ GIM_Reject, |
| 15480 | /* 42452 */ // Label 1303: @42452 |
| 15481 | /* 42452 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1306*/ GIMT_Encode4(42479), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1805 // |
| 15482 | /* 42459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15483 | /* 42462 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15484 | /* 42466 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15485 | /* 42470 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4005:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15486 | /* 42470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQh), |
| 15487 | /* 42473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15488 | /* 42475 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15489 | /* 42477 */ GIR_RootConstrainSelectedInstOperands, |
| 15490 | /* 42478 */ // GIR_Coverage, 1805, |
| 15491 | /* 42478 */ GIR_EraseRootFromParent_Done, |
| 15492 | /* 42479 */ // Label 1306: @42479 |
| 15493 | /* 42479 */ GIM_Reject, |
| 15494 | /* 42480 */ // Label 1304: @42480 |
| 15495 | /* 42480 */ GIM_Reject, |
| 15496 | /* 42481 */ // Label 1301: @42481 |
| 15497 | /* 42481 */ GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(42567), |
| 15498 | /* 42486 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 15499 | /* 42491 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1310*/ GIMT_Encode4(42566), |
| 15500 | /* 42502 */ /*GILLT_v2s32*//*Label 1308*/ GIMT_Encode4(42510), |
| 15501 | /* 42506 */ /*GILLT_v4s32*//*Label 1309*/ GIMT_Encode4(42538), |
| 15502 | /* 42510 */ // Label 1308: @42510 |
| 15503 | /* 42510 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1311*/ GIMT_Encode4(42537), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1806 // |
| 15504 | /* 42517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15505 | /* 42520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15506 | /* 42524 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15507 | /* 42528 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4000:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15508 | /* 42528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDf), |
| 15509 | /* 42531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15510 | /* 42533 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15511 | /* 42535 */ GIR_RootConstrainSelectedInstOperands, |
| 15512 | /* 42536 */ // GIR_Coverage, 1806, |
| 15513 | /* 42536 */ GIR_EraseRootFromParent_Done, |
| 15514 | /* 42537 */ // Label 1311: @42537 |
| 15515 | /* 42537 */ GIM_Reject, |
| 15516 | /* 42538 */ // Label 1309: @42538 |
| 15517 | /* 42538 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1312*/ GIMT_Encode4(42565), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1807 // |
| 15518 | /* 42545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15519 | /* 42548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15520 | /* 42552 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15521 | /* 42556 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4000:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15522 | /* 42556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQf), |
| 15523 | /* 42559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15524 | /* 42561 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15525 | /* 42563 */ GIR_RootConstrainSelectedInstOperands, |
| 15526 | /* 42564 */ // GIR_Coverage, 1807, |
| 15527 | /* 42564 */ GIR_EraseRootFromParent_Done, |
| 15528 | /* 42565 */ // Label 1312: @42565 |
| 15529 | /* 42565 */ GIM_Reject, |
| 15530 | /* 42566 */ // Label 1310: @42566 |
| 15531 | /* 42566 */ GIM_Reject, |
| 15532 | /* 42567 */ // Label 1307: @42567 |
| 15533 | /* 42567 */ GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(42653), |
| 15534 | /* 42572 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 15535 | /* 42577 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1316*/ GIMT_Encode4(42652), |
| 15536 | /* 42588 */ /*GILLT_v2s32*//*Label 1314*/ GIMT_Encode4(42596), |
| 15537 | /* 42592 */ /*GILLT_v4s32*//*Label 1315*/ GIMT_Encode4(42624), |
| 15538 | /* 42596 */ // Label 1314: @42596 |
| 15539 | /* 42596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1317*/ GIMT_Encode4(42623), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1808 // |
| 15540 | /* 42603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15541 | /* 42606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15542 | /* 42610 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15543 | /* 42614 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4001:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15544 | /* 42614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDf), |
| 15545 | /* 42617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15546 | /* 42619 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15547 | /* 42621 */ GIR_RootConstrainSelectedInstOperands, |
| 15548 | /* 42622 */ // GIR_Coverage, 1808, |
| 15549 | /* 42622 */ GIR_EraseRootFromParent_Done, |
| 15550 | /* 42623 */ // Label 1317: @42623 |
| 15551 | /* 42623 */ GIM_Reject, |
| 15552 | /* 42624 */ // Label 1315: @42624 |
| 15553 | /* 42624 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1318*/ GIMT_Encode4(42651), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1809 // |
| 15554 | /* 42631 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15555 | /* 42634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15556 | /* 42638 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15557 | /* 42642 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4001:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15558 | /* 42642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQf), |
| 15559 | /* 42645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15560 | /* 42647 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15561 | /* 42649 */ GIR_RootConstrainSelectedInstOperands, |
| 15562 | /* 42650 */ // GIR_Coverage, 1809, |
| 15563 | /* 42650 */ GIR_EraseRootFromParent_Done, |
| 15564 | /* 42651 */ // Label 1318: @42651 |
| 15565 | /* 42651 */ GIM_Reject, |
| 15566 | /* 42652 */ // Label 1316: @42652 |
| 15567 | /* 42652 */ GIM_Reject, |
| 15568 | /* 42653 */ // Label 1313: @42653 |
| 15569 | /* 42653 */ GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(42739), |
| 15570 | /* 42658 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 15571 | /* 42663 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1322*/ GIMT_Encode4(42738), |
| 15572 | /* 42674 */ /*GILLT_v4s16*//*Label 1320*/ GIMT_Encode4(42682), |
| 15573 | /* 42678 */ /*GILLT_v8s16*//*Label 1321*/ GIMT_Encode4(42710), |
| 15574 | /* 42682 */ // Label 1320: @42682 |
| 15575 | /* 42682 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1323*/ GIMT_Encode4(42709), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1810 // |
| 15576 | /* 42689 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15577 | /* 42692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15578 | /* 42696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15579 | /* 42700 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4000:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15580 | /* 42700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDh), |
| 15581 | /* 42703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15582 | /* 42705 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15583 | /* 42707 */ GIR_RootConstrainSelectedInstOperands, |
| 15584 | /* 42708 */ // GIR_Coverage, 1810, |
| 15585 | /* 42708 */ GIR_EraseRootFromParent_Done, |
| 15586 | /* 42709 */ // Label 1323: @42709 |
| 15587 | /* 42709 */ GIM_Reject, |
| 15588 | /* 42710 */ // Label 1321: @42710 |
| 15589 | /* 42710 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1324*/ GIMT_Encode4(42737), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1811 // |
| 15590 | /* 42717 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15591 | /* 42720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15592 | /* 42724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15593 | /* 42728 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4000:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15594 | /* 42728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQh), |
| 15595 | /* 42731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15596 | /* 42733 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15597 | /* 42735 */ GIR_RootConstrainSelectedInstOperands, |
| 15598 | /* 42736 */ // GIR_Coverage, 1811, |
| 15599 | /* 42736 */ GIR_EraseRootFromParent_Done, |
| 15600 | /* 42737 */ // Label 1324: @42737 |
| 15601 | /* 42737 */ GIM_Reject, |
| 15602 | /* 42738 */ // Label 1322: @42738 |
| 15603 | /* 42738 */ GIM_Reject, |
| 15604 | /* 42739 */ // Label 1319: @42739 |
| 15605 | /* 42739 */ GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(42825), |
| 15606 | /* 42744 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 15607 | /* 42749 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1328*/ GIMT_Encode4(42824), |
| 15608 | /* 42760 */ /*GILLT_v4s16*//*Label 1326*/ GIMT_Encode4(42768), |
| 15609 | /* 42764 */ /*GILLT_v8s16*//*Label 1327*/ GIMT_Encode4(42796), |
| 15610 | /* 42768 */ // Label 1326: @42768 |
| 15611 | /* 42768 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1329*/ GIMT_Encode4(42795), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1812 // |
| 15612 | /* 42775 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15613 | /* 42778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15614 | /* 42782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15615 | /* 42786 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4001:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15616 | /* 42786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDh), |
| 15617 | /* 42789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15618 | /* 42791 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15619 | /* 42793 */ GIR_RootConstrainSelectedInstOperands, |
| 15620 | /* 42794 */ // GIR_Coverage, 1812, |
| 15621 | /* 42794 */ GIR_EraseRootFromParent_Done, |
| 15622 | /* 42795 */ // Label 1329: @42795 |
| 15623 | /* 42795 */ GIM_Reject, |
| 15624 | /* 42796 */ // Label 1327: @42796 |
| 15625 | /* 42796 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1330*/ GIMT_Encode4(42823), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1813 // |
| 15626 | /* 42803 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15627 | /* 42806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15628 | /* 42810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15629 | /* 42814 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4001:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15630 | /* 42814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQh), |
| 15631 | /* 42817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15632 | /* 42819 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15633 | /* 42821 */ GIR_RootConstrainSelectedInstOperands, |
| 15634 | /* 42822 */ // GIR_Coverage, 1813, |
| 15635 | /* 42822 */ GIR_EraseRootFromParent_Done, |
| 15636 | /* 42823 */ // Label 1330: @42823 |
| 15637 | /* 42823 */ GIM_Reject, |
| 15638 | /* 42824 */ // Label 1328: @42824 |
| 15639 | /* 42824 */ GIM_Reject, |
| 15640 | /* 42825 */ // Label 1325: @42825 |
| 15641 | /* 42825 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1331*/ GIMT_Encode4(42869), GIMT_Encode2(GIFBS_HasFP16_HasNEON), // Rule ID 1830 // |
| 15642 | /* 42832 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2hf), |
| 15643 | /* 42837 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15644 | /* 42840 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15645 | /* 42843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15646 | /* 42847 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15647 | /* 42851 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3996:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTf2h:{ *:[v4i16] } QPR:{ *:[v4f32] }:$Vm) |
| 15648 | /* 42851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h), |
| 15649 | /* 42854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15650 | /* 42856 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15651 | /* 42858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15652 | /* 42861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15653 | /* 42867 */ GIR_RootConstrainSelectedInstOperands, |
| 15654 | /* 42868 */ // GIR_Coverage, 1830, |
| 15655 | /* 42868 */ GIR_EraseRootFromParent_Done, |
| 15656 | /* 42869 */ // Label 1331: @42869 |
| 15657 | /* 42869 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1332*/ GIMT_Encode4(42913), GIMT_Encode2(GIFBS_HasFP16_HasNEON), // Rule ID 1831 // |
| 15658 | /* 42876 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvthf2fp), |
| 15659 | /* 42881 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15660 | /* 42884 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15661 | /* 42887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15662 | /* 42891 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15663 | /* 42895 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3999:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4i16] }:$Vm) |
| 15664 | /* 42895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f), |
| 15665 | /* 42898 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15666 | /* 42900 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15667 | /* 42902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15668 | /* 42905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15669 | /* 42911 */ GIR_RootConstrainSelectedInstOperands, |
| 15670 | /* 42912 */ // GIR_Coverage, 1831, |
| 15671 | /* 42912 */ GIR_EraseRootFromParent_Done, |
| 15672 | /* 42913 */ // Label 1332: @42913 |
| 15673 | /* 42913 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1333*/ GIMT_Encode4(42948), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1903 // |
| 15674 | /* 42920 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesimc), |
| 15675 | /* 42925 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 15676 | /* 42928 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15677 | /* 42931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15678 | /* 42935 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15679 | /* 42939 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESIMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 15680 | /* 42939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESIMC), |
| 15681 | /* 42942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15682 | /* 42944 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15683 | /* 42946 */ GIR_RootConstrainSelectedInstOperands, |
| 15684 | /* 42947 */ // GIR_Coverage, 1903, |
| 15685 | /* 42947 */ GIR_EraseRootFromParent_Done, |
| 15686 | /* 42948 */ // Label 1333: @42948 |
| 15687 | /* 42948 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1334*/ GIMT_Encode4(42983), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1904 // |
| 15688 | /* 42955 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesmc), |
| 15689 | /* 42960 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 15690 | /* 42963 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15691 | /* 42966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15692 | /* 42970 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15693 | /* 42974 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3960:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 15694 | /* 42974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESMC), |
| 15695 | /* 42977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15696 | /* 42979 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15697 | /* 42981 */ GIR_RootConstrainSelectedInstOperands, |
| 15698 | /* 42982 */ // GIR_Coverage, 1904, |
| 15699 | /* 42982 */ GIR_EraseRootFromParent_Done, |
| 15700 | /* 42983 */ // Label 1334: @42983 |
| 15701 | /* 42983 */ GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(43072), |
| 15702 | /* 42988 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16), |
| 15703 | /* 42993 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15704 | /* 42996 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15705 | /* 42999 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1336*/ GIMT_Encode4(43035), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2039 // |
| 15706 | /* 43006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15707 | /* 43010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 15708 | /* 43014 */ // (intrinsic_wo_chain:{ *:[i32] } 4153:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (SXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 15709 | /* 43014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB16), |
| 15710 | /* 43017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15711 | /* 43019 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src |
| 15712 | /* 43021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15713 | /* 43024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15714 | /* 43027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15715 | /* 43033 */ GIR_RootConstrainSelectedInstOperands, |
| 15716 | /* 43034 */ // GIR_Coverage, 2039, |
| 15717 | /* 43034 */ GIR_EraseRootFromParent_Done, |
| 15718 | /* 43035 */ // Label 1336: @43035 |
| 15719 | /* 43035 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1337*/ GIMT_Encode4(43071), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2295 // |
| 15720 | /* 43042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15721 | /* 43046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15722 | /* 43050 */ // (intrinsic_wo_chain:{ *:[i32] } 4153:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (t2SXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 0:{ *:[i32] }) |
| 15723 | /* 43050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB16), |
| 15724 | /* 43053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15725 | /* 43055 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15726 | /* 43057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15727 | /* 43060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15728 | /* 43063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15729 | /* 43069 */ GIR_RootConstrainSelectedInstOperands, |
| 15730 | /* 43070 */ // GIR_Coverage, 2295, |
| 15731 | /* 43070 */ GIR_EraseRootFromParent_Done, |
| 15732 | /* 43071 */ // Label 1337: @43071 |
| 15733 | /* 43071 */ GIM_Reject, |
| 15734 | /* 43072 */ // Label 1335: @43072 |
| 15735 | /* 43072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1338*/ GIMT_Encode4(43137), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4369 // |
| 15736 | /* 43079 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn), |
| 15737 | /* 43084 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15738 | /* 43087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15739 | /* 43090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15740 | /* 43094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15741 | /* 43098 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3919:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 15742 | /* 43098 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15743 | /* 43101 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15744 | /* 43105 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15745 | /* 43110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N), |
| 15746 | /* 43113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15747 | /* 43115 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15748 | /* 43117 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15749 | /* 43120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15750 | /* 43126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15751 | /* 43132 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15752 | /* 43135 */ GIR_RootConstrainSelectedInstOperands, |
| 15753 | /* 43136 */ // GIR_Coverage, 4369, |
| 15754 | /* 43136 */ GIR_EraseRootFromParent_Done, |
| 15755 | /* 43137 */ // Label 1338: @43137 |
| 15756 | /* 43137 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1339*/ GIMT_Encode4(43202), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4373 // |
| 15757 | /* 43144 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintx), |
| 15758 | /* 43149 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15759 | /* 43152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15760 | /* 43155 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15761 | /* 43159 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15762 | /* 43163 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3923:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 15763 | /* 43163 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15764 | /* 43166 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15765 | /* 43170 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15766 | /* 43175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X), |
| 15767 | /* 43178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15768 | /* 43180 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15769 | /* 43182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15770 | /* 43185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15771 | /* 43191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15772 | /* 43197 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15773 | /* 43200 */ GIR_RootConstrainSelectedInstOperands, |
| 15774 | /* 43201 */ // GIR_Coverage, 4373, |
| 15775 | /* 43201 */ GIR_EraseRootFromParent_Done, |
| 15776 | /* 43202 */ // Label 1339: @43202 |
| 15777 | /* 43202 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1340*/ GIMT_Encode4(43267), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4377 // |
| 15778 | /* 43209 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrinta), |
| 15779 | /* 43214 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15780 | /* 43217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15781 | /* 43220 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15782 | /* 43224 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15783 | /* 43228 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3915:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 15784 | /* 43228 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15785 | /* 43231 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15786 | /* 43235 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15787 | /* 43240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A), |
| 15788 | /* 43243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15789 | /* 43245 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15790 | /* 43247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15791 | /* 43250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15792 | /* 43256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15793 | /* 43262 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15794 | /* 43265 */ GIR_RootConstrainSelectedInstOperands, |
| 15795 | /* 43266 */ // GIR_Coverage, 4377, |
| 15796 | /* 43266 */ GIR_EraseRootFromParent_Done, |
| 15797 | /* 43267 */ // Label 1340: @43267 |
| 15798 | /* 43267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1341*/ GIMT_Encode4(43332), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4381 // |
| 15799 | /* 43274 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintz), |
| 15800 | /* 43279 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15801 | /* 43282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15802 | /* 43285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15803 | /* 43289 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15804 | /* 43293 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3925:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 15805 | /* 43293 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15806 | /* 43296 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15807 | /* 43300 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15808 | /* 43305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z), |
| 15809 | /* 43308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15810 | /* 43310 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15811 | /* 43312 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15812 | /* 43315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15813 | /* 43321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15814 | /* 43327 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15815 | /* 43330 */ GIR_RootConstrainSelectedInstOperands, |
| 15816 | /* 43331 */ // GIR_Coverage, 4381, |
| 15817 | /* 43331 */ GIR_EraseRootFromParent_Done, |
| 15818 | /* 43332 */ // Label 1341: @43332 |
| 15819 | /* 43332 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1342*/ GIMT_Encode4(43397), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4385 // |
| 15820 | /* 43339 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintm), |
| 15821 | /* 43344 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15822 | /* 43347 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15823 | /* 43350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15824 | /* 43354 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15825 | /* 43358 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3917:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 15826 | /* 43358 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15827 | /* 43361 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15828 | /* 43365 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15829 | /* 43370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M), |
| 15830 | /* 43373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15831 | /* 43375 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15832 | /* 43377 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15833 | /* 43380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15834 | /* 43386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15835 | /* 43392 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15836 | /* 43395 */ GIR_RootConstrainSelectedInstOperands, |
| 15837 | /* 43396 */ // GIR_Coverage, 4385, |
| 15838 | /* 43396 */ GIR_EraseRootFromParent_Done, |
| 15839 | /* 43397 */ // Label 1342: @43397 |
| 15840 | /* 43397 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1343*/ GIMT_Encode4(43462), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4389 // |
| 15841 | /* 43404 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintp), |
| 15842 | /* 43409 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15843 | /* 43412 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15844 | /* 43415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15845 | /* 43419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15846 | /* 43423 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3921:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 15847 | /* 43423 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15848 | /* 43426 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15849 | /* 43430 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15850 | /* 43435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P), |
| 15851 | /* 43438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15852 | /* 43440 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15853 | /* 43442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15854 | /* 43445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15855 | /* 43451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15856 | /* 43457 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15857 | /* 43460 */ GIR_RootConstrainSelectedInstOperands, |
| 15858 | /* 43461 */ // GIR_Coverage, 4389, |
| 15859 | /* 43461 */ GIR_EraseRootFromParent_Done, |
| 15860 | /* 43462 */ // Label 1343: @43462 |
| 15861 | /* 43462 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1344*/ GIMT_Encode4(43527), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4393 // |
| 15862 | /* 43469 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn), |
| 15863 | /* 43474 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15864 | /* 43477 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15865 | /* 43480 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15866 | /* 43484 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15867 | /* 43488 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3919:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 15868 | /* 43488 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15869 | /* 43491 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15870 | /* 43495 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15871 | /* 43500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N), |
| 15872 | /* 43503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15873 | /* 43505 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15874 | /* 43507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15875 | /* 43510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15876 | /* 43516 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15877 | /* 43522 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15878 | /* 43525 */ GIR_RootConstrainSelectedInstOperands, |
| 15879 | /* 43526 */ // GIR_Coverage, 4393, |
| 15880 | /* 43526 */ GIR_EraseRootFromParent_Done, |
| 15881 | /* 43527 */ // Label 1344: @43527 |
| 15882 | /* 43527 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1345*/ GIMT_Encode4(43592), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4397 // |
| 15883 | /* 43534 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintx), |
| 15884 | /* 43539 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15885 | /* 43542 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15886 | /* 43545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15887 | /* 43549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15888 | /* 43553 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3923:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 15889 | /* 43553 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15890 | /* 43556 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15891 | /* 43560 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15892 | /* 43565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X), |
| 15893 | /* 43568 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15894 | /* 43570 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15895 | /* 43572 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15896 | /* 43575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15897 | /* 43581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15898 | /* 43587 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15899 | /* 43590 */ GIR_RootConstrainSelectedInstOperands, |
| 15900 | /* 43591 */ // GIR_Coverage, 4397, |
| 15901 | /* 43591 */ GIR_EraseRootFromParent_Done, |
| 15902 | /* 43592 */ // Label 1345: @43592 |
| 15903 | /* 43592 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1346*/ GIMT_Encode4(43657), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4401 // |
| 15904 | /* 43599 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrinta), |
| 15905 | /* 43604 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15906 | /* 43607 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15907 | /* 43610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15908 | /* 43614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15909 | /* 43618 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3915:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 15910 | /* 43618 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15911 | /* 43621 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15912 | /* 43625 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15913 | /* 43630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A), |
| 15914 | /* 43633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15915 | /* 43635 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15916 | /* 43637 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15917 | /* 43640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15918 | /* 43646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15919 | /* 43652 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15920 | /* 43655 */ GIR_RootConstrainSelectedInstOperands, |
| 15921 | /* 43656 */ // GIR_Coverage, 4401, |
| 15922 | /* 43656 */ GIR_EraseRootFromParent_Done, |
| 15923 | /* 43657 */ // Label 1346: @43657 |
| 15924 | /* 43657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1347*/ GIMT_Encode4(43722), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4405 // |
| 15925 | /* 43664 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintz), |
| 15926 | /* 43669 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15927 | /* 43672 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15928 | /* 43675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15929 | /* 43679 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15930 | /* 43683 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3925:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 15931 | /* 43683 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15932 | /* 43686 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15933 | /* 43690 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15934 | /* 43695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z), |
| 15935 | /* 43698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15936 | /* 43700 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15937 | /* 43702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15938 | /* 43705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15939 | /* 43711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15940 | /* 43717 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15941 | /* 43720 */ GIR_RootConstrainSelectedInstOperands, |
| 15942 | /* 43721 */ // GIR_Coverage, 4405, |
| 15943 | /* 43721 */ GIR_EraseRootFromParent_Done, |
| 15944 | /* 43722 */ // Label 1347: @43722 |
| 15945 | /* 43722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1348*/ GIMT_Encode4(43787), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4409 // |
| 15946 | /* 43729 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintm), |
| 15947 | /* 43734 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15948 | /* 43737 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15949 | /* 43740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15950 | /* 43744 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15951 | /* 43748 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3917:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 15952 | /* 43748 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15953 | /* 43751 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15954 | /* 43755 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15955 | /* 43760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M), |
| 15956 | /* 43763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15957 | /* 43765 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15958 | /* 43767 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15959 | /* 43770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15960 | /* 43776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15961 | /* 43782 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15962 | /* 43785 */ GIR_RootConstrainSelectedInstOperands, |
| 15963 | /* 43786 */ // GIR_Coverage, 4409, |
| 15964 | /* 43786 */ GIR_EraseRootFromParent_Done, |
| 15965 | /* 43787 */ // Label 1348: @43787 |
| 15966 | /* 43787 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1349*/ GIMT_Encode4(43852), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4413 // |
| 15967 | /* 43794 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintp), |
| 15968 | /* 43799 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15969 | /* 43802 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15970 | /* 43805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15971 | /* 43809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15972 | /* 43813 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3921:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 15973 | /* 43813 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15974 | /* 43816 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15975 | /* 43820 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15976 | /* 43825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P), |
| 15977 | /* 43828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15978 | /* 43830 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15979 | /* 43832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15980 | /* 43835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15981 | /* 43841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15982 | /* 43847 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15983 | /* 43850 */ GIR_RootConstrainSelectedInstOperands, |
| 15984 | /* 43851 */ // GIR_Coverage, 4413, |
| 15985 | /* 43851 */ GIR_EraseRootFromParent_Done, |
| 15986 | /* 43852 */ // Label 1349: @43852 |
| 15987 | /* 43852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1350*/ GIMT_Encode4(43902), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5399 // |
| 15988 | /* 43859 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp8), |
| 15989 | /* 43864 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s1, |
| 15990 | /* 43867 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15991 | /* 43870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 15992 | /* 43874 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15993 | /* 43878 */ // (intrinsic_wo_chain:{ *:[v16i1] } 3838:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP8:{ *:[v16i1] } rGPR:{ *:[i32] }:$Rn) |
| 15994 | /* 43878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP8), |
| 15995 | /* 43881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 15996 | /* 43883 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15997 | /* 43885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15998 | /* 43888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15999 | /* 43894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16000 | /* 43900 */ GIR_RootConstrainSelectedInstOperands, |
| 16001 | /* 43901 */ // GIR_Coverage, 5399, |
| 16002 | /* 43901 */ GIR_EraseRootFromParent_Done, |
| 16003 | /* 43902 */ // Label 1350: @43902 |
| 16004 | /* 43902 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1351*/ GIMT_Encode4(43952), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5401 // |
| 16005 | /* 43909 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp16), |
| 16006 | /* 43914 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1, |
| 16007 | /* 43917 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16008 | /* 43920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 16009 | /* 43924 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16010 | /* 43928 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3835:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP16:{ *:[v8i1] } rGPR:{ *:[i32] }:$Rn) |
| 16011 | /* 43928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP16), |
| 16012 | /* 43931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 16013 | /* 43933 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16014 | /* 43935 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16015 | /* 43938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16016 | /* 43944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16017 | /* 43950 */ GIR_RootConstrainSelectedInstOperands, |
| 16018 | /* 43951 */ // GIR_Coverage, 5401, |
| 16019 | /* 43951 */ GIR_EraseRootFromParent_Done, |
| 16020 | /* 43952 */ // Label 1351: @43952 |
| 16021 | /* 43952 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1352*/ GIMT_Encode4(44002), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5403 // |
| 16022 | /* 43959 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp32), |
| 16023 | /* 43964 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1, |
| 16024 | /* 43967 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16025 | /* 43970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 16026 | /* 43974 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16027 | /* 43978 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3836:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP32:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn) |
| 16028 | /* 43978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP32), |
| 16029 | /* 43981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 16030 | /* 43983 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16031 | /* 43985 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16032 | /* 43988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16033 | /* 43994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16034 | /* 44000 */ GIR_RootConstrainSelectedInstOperands, |
| 16035 | /* 44001 */ // GIR_Coverage, 5403, |
| 16036 | /* 44001 */ GIR_EraseRootFromParent_Done, |
| 16037 | /* 44002 */ // Label 1352: @44002 |
| 16038 | /* 44002 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1353*/ GIMT_Encode4(44052), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5405 // |
| 16039 | /* 44009 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp64), |
| 16040 | /* 44014 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s1, |
| 16041 | /* 44017 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16042 | /* 44020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 16043 | /* 44024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16044 | /* 44028 */ // (intrinsic_wo_chain:{ *:[v2i1] } 3837:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP64:{ *:[v2i1] } rGPR:{ *:[i32] }:$Rn) |
| 16045 | /* 44028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP64), |
| 16046 | /* 44031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 16047 | /* 44033 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16048 | /* 44035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16049 | /* 44038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16050 | /* 44044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16051 | /* 44050 */ GIR_RootConstrainSelectedInstOperands, |
| 16052 | /* 44051 */ // GIR_Coverage, 5405, |
| 16053 | /* 44051 */ GIR_EraseRootFromParent_Done, |
| 16054 | /* 44052 */ // Label 1353: @44052 |
| 16055 | /* 44052 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1354*/ GIMT_Encode4(44097), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 599 // |
| 16056 | /* 44059 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tt), |
| 16057 | /* 44064 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16058 | /* 44067 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16059 | /* 44071 */ // MIs[0] Rn |
| 16060 | /* 44071 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 16061 | /* 44075 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16062 | /* 44079 */ // (intrinsic_wo_chain:{ *:[i32] } 3712:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 16063 | /* 44079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TT), |
| 16064 | /* 44082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 16065 | /* 44084 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16066 | /* 44086 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16067 | /* 44089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16068 | /* 44095 */ GIR_RootConstrainSelectedInstOperands, |
| 16069 | /* 44096 */ // GIR_Coverage, 599, |
| 16070 | /* 44096 */ GIR_EraseRootFromParent_Done, |
| 16071 | /* 44097 */ // Label 1354: @44097 |
| 16072 | /* 44097 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1355*/ GIMT_Encode4(44142), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 600 // |
| 16073 | /* 44104 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttt), |
| 16074 | /* 44109 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16075 | /* 44112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16076 | /* 44116 */ // MIs[0] Rn |
| 16077 | /* 44116 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 16078 | /* 44120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16079 | /* 44124 */ // (intrinsic_wo_chain:{ *:[i32] } 3715:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 16080 | /* 44124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTT), |
| 16081 | /* 44127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 16082 | /* 44129 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16083 | /* 44131 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16084 | /* 44134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16085 | /* 44140 */ GIR_RootConstrainSelectedInstOperands, |
| 16086 | /* 44141 */ // GIR_Coverage, 600, |
| 16087 | /* 44141 */ GIR_EraseRootFromParent_Done, |
| 16088 | /* 44142 */ // Label 1355: @44142 |
| 16089 | /* 44142 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1356*/ GIMT_Encode4(44187), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 601 // |
| 16090 | /* 44149 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tta), |
| 16091 | /* 44154 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16092 | /* 44157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16093 | /* 44161 */ // MIs[0] Rn |
| 16094 | /* 44161 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 16095 | /* 44165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16096 | /* 44169 */ // (intrinsic_wo_chain:{ *:[i32] } 3713:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 16097 | /* 44169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTA), |
| 16098 | /* 44172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 16099 | /* 44174 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16100 | /* 44176 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16101 | /* 44179 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16102 | /* 44185 */ GIR_RootConstrainSelectedInstOperands, |
| 16103 | /* 44186 */ // GIR_Coverage, 601, |
| 16104 | /* 44186 */ GIR_EraseRootFromParent_Done, |
| 16105 | /* 44187 */ // Label 1356: @44187 |
| 16106 | /* 44187 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1357*/ GIMT_Encode4(44232), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 602 // |
| 16107 | /* 44194 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttat), |
| 16108 | /* 44199 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16109 | /* 44202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16110 | /* 44206 */ // MIs[0] Rn |
| 16111 | /* 44206 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 16112 | /* 44210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16113 | /* 44214 */ // (intrinsic_wo_chain:{ *:[i32] } 3714:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTAT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 16114 | /* 44214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTAT), |
| 16115 | /* 44217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 16116 | /* 44219 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16117 | /* 44221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16118 | /* 44224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16119 | /* 44230 */ GIR_RootConstrainSelectedInstOperands, |
| 16120 | /* 44231 */ // GIR_Coverage, 602, |
| 16121 | /* 44231 */ GIR_EraseRootFromParent_Done, |
| 16122 | /* 44232 */ // Label 1357: @44232 |
| 16123 | /* 44232 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1358*/ GIMT_Encode4(44385), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3082 // |
| 16124 | /* 44239 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1h), |
| 16125 | /* 44244 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16126 | /* 44247 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16127 | /* 44250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 16128 | /* 44254 */ // (intrinsic_wo_chain:{ *:[i32] } 3967:{ *:[iPTR] }, i32:{ *:[i32] }:$Rn) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[f32] } (SHA1H:{ *:[v16i8] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$Rn, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }), GPR:{ *:[i32] }) |
| 16129 | /* 44254 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 16130 | /* 44257 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16131 | /* 44261 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16132 | /* 44266 */ GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 16133 | /* 44270 */ GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 16134 | /* 44275 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8, |
| 16135 | /* 44278 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16136 | /* 44282 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16137 | /* 44287 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 16138 | /* 44289 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, |
| 16139 | /* 44292 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 16140 | /* 44296 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16141 | /* 44301 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 16142 | /* 44304 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4, |
| 16143 | /* 44307 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 16144 | /* 44310 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 16145 | /* 44315 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 16146 | /* 44320 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 16147 | /* 44325 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 16148 | /* 44328 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::SHA1H), |
| 16149 | /* 44332 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16150 | /* 44337 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 16151 | /* 44340 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16152 | /* 44342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16153 | /* 44345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16154 | /* 44349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16155 | /* 44354 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 16156 | /* 44361 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 16157 | /* 44366 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::MQPRRegClassID), |
| 16158 | /* 44371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16159 | /* 44374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 16160 | /* 44376 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16161 | /* 44379 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 16162 | /* 44384 */ // GIR_Coverage, 3082, |
| 16163 | /* 44384 */ GIR_EraseRootFromParent_Done, |
| 16164 | /* 44385 */ // Label 1358: @44385 |
| 16165 | /* 44385 */ GIM_Reject, |
| 16166 | /* 44386 */ // Label 1111: @44386 |
| 16167 | /* 44386 */ GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(67749), |
| 16168 | /* 44391 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 16169 | /* 44394 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1360*/ GIMT_Encode4(44450), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2313 // |
| 16170 | /* 44401 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16), |
| 16171 | /* 44406 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16172 | /* 44409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16173 | /* 44412 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16174 | /* 44415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16175 | /* 44419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16176 | /* 44423 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16177 | /* 44427 */ // (intrinsic_wo_chain:{ *:[i32] } 4177:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 16178 | /* 44427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB16), |
| 16179 | /* 44430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16180 | /* 44432 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16181 | /* 44434 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16182 | /* 44436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16183 | /* 44439 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16184 | /* 44442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16185 | /* 44448 */ GIR_RootConstrainSelectedInstOperands, |
| 16186 | /* 44449 */ // GIR_Coverage, 2313, |
| 16187 | /* 44449 */ GIR_EraseRootFromParent_Done, |
| 16188 | /* 44450 */ // Label 1360: @44450 |
| 16189 | /* 44450 */ GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(44638), |
| 16190 | /* 44455 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 16191 | /* 44460 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16192 | /* 44463 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16193 | /* 44466 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16194 | /* 44469 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1362*/ GIMT_Encode4(44553), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2076 // |
| 16195 | /* 44476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16196 | /* 44480 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16197 | /* 44484 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 16198 | /* 44488 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 16199 | /* 44492 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16200 | /* 44496 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16201 | /* 44501 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 16202 | /* 44505 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16203 | /* 44509 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 16204 | /* 44513 */ // MIs[2] Operand 1 |
| 16205 | /* 44513 */ // No operand predicates |
| 16206 | /* 44513 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3] |
| 16207 | /* 44517 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16208 | /* 44521 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 16209 | /* 44525 */ // MIs[3] Operand 1 |
| 16210 | /* 44525 */ // No operand predicates |
| 16211 | /* 44525 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 16212 | /* 44527 */ // (intrinsic_wo_chain:{ *:[i32] } 4172:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft) |
| 16213 | /* 44527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT), |
| 16214 | /* 44530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16215 | /* 44532 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos |
| 16216 | /* 44535 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 16217 | /* 44539 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft |
| 16218 | /* 44542 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16219 | /* 44545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16220 | /* 44551 */ GIR_RootConstrainSelectedInstOperands, |
| 16221 | /* 44552 */ // GIR_Coverage, 2076, |
| 16222 | /* 44552 */ GIR_EraseRootFromParent_Done, |
| 16223 | /* 44553 */ // Label 1362: @44553 |
| 16224 | /* 44553 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1363*/ GIMT_Encode4(44637), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2350 // |
| 16225 | /* 44560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16226 | /* 44564 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16227 | /* 44568 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 16228 | /* 44572 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 16229 | /* 44576 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16230 | /* 44580 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16231 | /* 44585 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 16232 | /* 44589 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16233 | /* 44593 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 16234 | /* 44597 */ // MIs[2] Operand 1 |
| 16235 | /* 44597 */ // No operand predicates |
| 16236 | /* 44597 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3] |
| 16237 | /* 44601 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16238 | /* 44605 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 16239 | /* 44609 */ // MIs[3] Operand 1 |
| 16240 | /* 44609 */ // No operand predicates |
| 16241 | /* 44609 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 16242 | /* 44611 */ // (intrinsic_wo_chain:{ *:[i32] } 4172:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft) |
| 16243 | /* 44611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT), |
| 16244 | /* 44614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16245 | /* 44616 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos |
| 16246 | /* 44619 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 16247 | /* 44623 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft |
| 16248 | /* 44626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16249 | /* 44629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16250 | /* 44635 */ GIR_RootConstrainSelectedInstOperands, |
| 16251 | /* 44636 */ // GIR_Coverage, 2350, |
| 16252 | /* 44636 */ GIR_EraseRootFromParent_Done, |
| 16253 | /* 44637 */ // Label 1363: @44637 |
| 16254 | /* 44637 */ GIM_Reject, |
| 16255 | /* 44638 */ // Label 1361: @44638 |
| 16256 | /* 44638 */ GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(44865), |
| 16257 | /* 44643 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16258 | /* 44648 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16259 | /* 44651 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16260 | /* 44654 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16261 | /* 44657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1365*/ GIMT_Encode4(44726), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5965 // |
| 16262 | /* 44664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16263 | /* 44668 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16264 | /* 44672 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 16265 | /* 44676 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16266 | /* 44679 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16267 | /* 44684 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16268 | /* 44688 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16269 | /* 44693 */ // MIs[1] Rn |
| 16270 | /* 44693 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 16271 | /* 44698 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16272 | /* 44702 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16273 | /* 44704 */ // (intrinsic_wo_chain:{ *:[i32] } 4095:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 4095:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn), GPRnopc:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 16274 | /* 44704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 16275 | /* 44707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16276 | /* 44709 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16277 | /* 44711 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16278 | /* 44715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16279 | /* 44718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16280 | /* 44724 */ GIR_RootConstrainSelectedInstOperands, |
| 16281 | /* 44725 */ // GIR_Coverage, 5965, |
| 16282 | /* 44725 */ GIR_EraseRootFromParent_Done, |
| 16283 | /* 44726 */ // Label 1365: @44726 |
| 16284 | /* 44726 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1366*/ GIMT_Encode4(44795), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6293 // |
| 16285 | /* 44733 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16286 | /* 44737 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16287 | /* 44741 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 16288 | /* 44745 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16289 | /* 44748 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16290 | /* 44753 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16291 | /* 44757 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16292 | /* 44762 */ // MIs[1] Rn |
| 16293 | /* 44762 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 16294 | /* 44767 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16295 | /* 44771 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16296 | /* 44773 */ // (intrinsic_wo_chain:{ *:[i32] } 4095:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 4095:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 16297 | /* 44773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 16298 | /* 44776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16299 | /* 44778 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16300 | /* 44780 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16301 | /* 44784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16302 | /* 44787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16303 | /* 44793 */ GIR_RootConstrainSelectedInstOperands, |
| 16304 | /* 44794 */ // GIR_Coverage, 6293, |
| 16305 | /* 44794 */ GIR_EraseRootFromParent_Done, |
| 16306 | /* 44795 */ // Label 1366: @44795 |
| 16307 | /* 44795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1367*/ GIMT_Encode4(44864), GIMT_Encode2(GIFBS_IsARM), // Rule ID 108 // |
| 16308 | /* 44802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16309 | /* 44806 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16310 | /* 44810 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16311 | /* 44814 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 16312 | /* 44818 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16313 | /* 44821 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16314 | /* 44826 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16315 | /* 44830 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16316 | /* 44835 */ // MIs[1] Rn |
| 16317 | /* 44835 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 16318 | /* 44840 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16319 | /* 44842 */ // (intrinsic_wo_chain:{ *:[i32] } 4095:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4095:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 16320 | /* 44842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 16321 | /* 44845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16322 | /* 44847 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 16323 | /* 44849 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16324 | /* 44853 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16325 | /* 44856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16326 | /* 44862 */ GIR_RootConstrainSelectedInstOperands, |
| 16327 | /* 44863 */ // GIR_Coverage, 108, |
| 16328 | /* 44863 */ GIR_EraseRootFromParent_Done, |
| 16329 | /* 44864 */ // Label 1367: @44864 |
| 16330 | /* 44864 */ GIM_Reject, |
| 16331 | /* 44865 */ // Label 1364: @44865 |
| 16332 | /* 44865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1368*/ GIMT_Encode4(44948), GIMT_Encode2(GIFBS_IsARM), // Rule ID 109 // |
| 16333 | /* 44872 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 16334 | /* 44877 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16335 | /* 44880 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16336 | /* 44883 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16337 | /* 44886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16338 | /* 44890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16339 | /* 44894 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16340 | /* 44898 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 16341 | /* 44902 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16342 | /* 44905 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16343 | /* 44910 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16344 | /* 44914 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16345 | /* 44919 */ // MIs[1] Rn |
| 16346 | /* 44919 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 16347 | /* 44924 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16348 | /* 44926 */ // (intrinsic_wo_chain:{ *:[i32] } 4100:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4095:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 16349 | /* 44926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB), |
| 16350 | /* 44929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16351 | /* 44931 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 16352 | /* 44933 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16353 | /* 44937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16354 | /* 44940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16355 | /* 44946 */ GIR_RootConstrainSelectedInstOperands, |
| 16356 | /* 44947 */ // GIR_Coverage, 109, |
| 16357 | /* 44947 */ GIR_EraseRootFromParent_Done, |
| 16358 | /* 44948 */ // Label 1368: @44948 |
| 16359 | /* 44948 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1369*/ GIMT_Encode4(45031), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2328 // |
| 16360 | /* 44955 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16361 | /* 44960 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16362 | /* 44963 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16363 | /* 44966 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16364 | /* 44969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16365 | /* 44973 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16366 | /* 44977 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16367 | /* 44981 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 16368 | /* 44985 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16369 | /* 44988 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16370 | /* 44993 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16371 | /* 44997 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16372 | /* 45002 */ // MIs[1] Rn |
| 16373 | /* 45002 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 16374 | /* 45007 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16375 | /* 45009 */ // (intrinsic_wo_chain:{ *:[i32] } 4095:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4095:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 16376 | /* 45009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 16377 | /* 45012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16378 | /* 45014 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 16379 | /* 45016 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16380 | /* 45020 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16381 | /* 45023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16382 | /* 45029 */ GIR_RootConstrainSelectedInstOperands, |
| 16383 | /* 45030 */ // GIR_Coverage, 2328, |
| 16384 | /* 45030 */ GIR_EraseRootFromParent_Done, |
| 16385 | /* 45031 */ // Label 1369: @45031 |
| 16386 | /* 45031 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1370*/ GIMT_Encode4(45114), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2329 // |
| 16387 | /* 45038 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 16388 | /* 45043 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16389 | /* 45046 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16390 | /* 45049 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16391 | /* 45052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16392 | /* 45056 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16393 | /* 45060 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16394 | /* 45064 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 16395 | /* 45068 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16396 | /* 45071 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16397 | /* 45076 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16398 | /* 45080 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16399 | /* 45085 */ // MIs[1] Rn |
| 16400 | /* 45085 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 16401 | /* 45090 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16402 | /* 45092 */ // (intrinsic_wo_chain:{ *:[i32] } 4100:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4095:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 16403 | /* 45092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB), |
| 16404 | /* 45095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16405 | /* 45097 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 16406 | /* 45099 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16407 | /* 45103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16408 | /* 45106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16409 | /* 45112 */ GIR_RootConstrainSelectedInstOperands, |
| 16410 | /* 45113 */ // GIR_Coverage, 2329, |
| 16411 | /* 45113 */ GIR_EraseRootFromParent_Done, |
| 16412 | /* 45114 */ // Label 1370: @45114 |
| 16413 | /* 45114 */ GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(45316), |
| 16414 | /* 45119 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm), |
| 16415 | /* 45124 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1374*/ GIMT_Encode4(45315), |
| 16416 | /* 45135 */ /*GILLT_v8s16*//*Label 1372*/ GIMT_Encode4(45147), GIMT_Encode4(0), |
| 16417 | /* 45143 */ /*GILLT_v4s32*//*Label 1373*/ GIMT_Encode4(45231), |
| 16418 | /* 45147 */ // Label 1372: @45147 |
| 16419 | /* 45147 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1375*/ GIMT_Encode4(45230), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4581 // |
| 16420 | /* 45154 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16421 | /* 45157 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16422 | /* 45160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16423 | /* 45164 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16424 | /* 45168 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16425 | /* 45172 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 16426 | /* 45176 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16427 | /* 45181 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 16428 | /* 45185 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16429 | /* 45189 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 16430 | /* 45193 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16431 | /* 45198 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16432 | /* 45200 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3875:{ *:[iPTR] }, (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 16433 | /* 45200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16), |
| 16434 | /* 45203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16435 | /* 45205 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 16436 | /* 45209 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 16437 | /* 45213 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16438 | /* 45216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16439 | /* 45222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16440 | /* 45228 */ GIR_RootConstrainSelectedInstOperands, |
| 16441 | /* 45229 */ // GIR_Coverage, 4581, |
| 16442 | /* 45229 */ GIR_EraseRootFromParent_Done, |
| 16443 | /* 45230 */ // Label 1375: @45230 |
| 16444 | /* 45230 */ GIM_Reject, |
| 16445 | /* 45231 */ // Label 1373: @45231 |
| 16446 | /* 45231 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1376*/ GIMT_Encode4(45314), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4578 // |
| 16447 | /* 45238 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16448 | /* 45241 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16449 | /* 45244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16450 | /* 45248 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16451 | /* 45252 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16452 | /* 45256 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 16453 | /* 45260 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16454 | /* 45265 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 16455 | /* 45269 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16456 | /* 45273 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 16457 | /* 45277 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16458 | /* 45282 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16459 | /* 45284 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3875:{ *:[iPTR] }, (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 16460 | /* 45284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32), |
| 16461 | /* 45287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16462 | /* 45289 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 16463 | /* 45293 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 16464 | /* 45297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16465 | /* 45300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16466 | /* 45306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16467 | /* 45312 */ GIR_RootConstrainSelectedInstOperands, |
| 16468 | /* 45313 */ // GIR_Coverage, 4578, |
| 16469 | /* 45313 */ GIR_EraseRootFromParent_Done, |
| 16470 | /* 45314 */ // Label 1376: @45314 |
| 16471 | /* 45314 */ GIM_Reject, |
| 16472 | /* 45315 */ // Label 1374: @45315 |
| 16473 | /* 45315 */ GIM_Reject, |
| 16474 | /* 45316 */ // Label 1371: @45316 |
| 16475 | /* 45316 */ GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(45518), |
| 16476 | /* 45321 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm), |
| 16477 | /* 45326 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1380*/ GIMT_Encode4(45517), |
| 16478 | /* 45337 */ /*GILLT_v8s16*//*Label 1378*/ GIMT_Encode4(45349), GIMT_Encode4(0), |
| 16479 | /* 45345 */ /*GILLT_v4s32*//*Label 1379*/ GIMT_Encode4(45433), |
| 16480 | /* 45349 */ // Label 1378: @45349 |
| 16481 | /* 45349 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1381*/ GIMT_Encode4(45432), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4587 // |
| 16482 | /* 45356 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16483 | /* 45359 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16484 | /* 45362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16485 | /* 45366 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16486 | /* 45370 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16487 | /* 45374 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 16488 | /* 45378 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16489 | /* 45383 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 16490 | /* 45387 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16491 | /* 45391 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 16492 | /* 45395 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16493 | /* 45400 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16494 | /* 45402 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3878:{ *:[iPTR] }, (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 16495 | /* 45402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16), |
| 16496 | /* 45405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16497 | /* 45407 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 16498 | /* 45411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 16499 | /* 45415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16500 | /* 45418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16501 | /* 45424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16502 | /* 45430 */ GIR_RootConstrainSelectedInstOperands, |
| 16503 | /* 45431 */ // GIR_Coverage, 4587, |
| 16504 | /* 45431 */ GIR_EraseRootFromParent_Done, |
| 16505 | /* 45432 */ // Label 1381: @45432 |
| 16506 | /* 45432 */ GIM_Reject, |
| 16507 | /* 45433 */ // Label 1379: @45433 |
| 16508 | /* 45433 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1382*/ GIMT_Encode4(45516), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4584 // |
| 16509 | /* 45440 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16510 | /* 45443 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16511 | /* 45446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16512 | /* 45450 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16513 | /* 45454 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16514 | /* 45458 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 16515 | /* 45462 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16516 | /* 45467 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 16517 | /* 45471 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16518 | /* 45475 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 16519 | /* 45479 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16520 | /* 45484 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16521 | /* 45486 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3878:{ *:[iPTR] }, (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 16522 | /* 45486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32), |
| 16523 | /* 45489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16524 | /* 45491 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 16525 | /* 45495 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 16526 | /* 45499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16527 | /* 45502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16528 | /* 45508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16529 | /* 45514 */ GIR_RootConstrainSelectedInstOperands, |
| 16530 | /* 45515 */ // GIR_Coverage, 4584, |
| 16531 | /* 45515 */ GIR_EraseRootFromParent_Done, |
| 16532 | /* 45516 */ // Label 1382: @45516 |
| 16533 | /* 45516 */ GIM_Reject, |
| 16534 | /* 45517 */ // Label 1380: @45517 |
| 16535 | /* 45517 */ GIM_Reject, |
| 16536 | /* 45518 */ // Label 1377: @45518 |
| 16537 | /* 45518 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1383*/ GIMT_Encode4(45590), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4509 // |
| 16538 | /* 45525 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 16539 | /* 45530 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16540 | /* 45533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16541 | /* 45536 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16542 | /* 45539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16543 | /* 45543 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16544 | /* 45547 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16545 | /* 45551 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3848:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16546 | /* 45551 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16547 | /* 45554 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16548 | /* 45558 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16549 | /* 45563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16a), |
| 16550 | /* 45566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16551 | /* 45568 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16552 | /* 45570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16553 | /* 45573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16554 | /* 45579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16555 | /* 45585 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16556 | /* 45588 */ GIR_RootConstrainSelectedInstOperands, |
| 16557 | /* 45589 */ // GIR_Coverage, 4509, |
| 16558 | /* 45589 */ GIR_EraseRootFromParent_Done, |
| 16559 | /* 45590 */ // Label 1383: @45590 |
| 16560 | /* 45590 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1384*/ GIMT_Encode4(45662), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4511 // |
| 16561 | /* 45597 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 16562 | /* 45602 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16563 | /* 45605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16564 | /* 45608 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16565 | /* 45611 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16566 | /* 45615 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16567 | /* 45619 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16568 | /* 45623 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3852:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16569 | /* 45623 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16570 | /* 45626 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16571 | /* 45630 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16572 | /* 45635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16n), |
| 16573 | /* 45638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16574 | /* 45640 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16575 | /* 45642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16576 | /* 45645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16577 | /* 45651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16578 | /* 45657 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16579 | /* 45660 */ GIR_RootConstrainSelectedInstOperands, |
| 16580 | /* 45661 */ // GIR_Coverage, 4511, |
| 16581 | /* 45661 */ GIR_EraseRootFromParent_Done, |
| 16582 | /* 45662 */ // Label 1384: @45662 |
| 16583 | /* 45662 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1385*/ GIMT_Encode4(45734), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4513 // |
| 16584 | /* 45669 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 16585 | /* 45674 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16586 | /* 45677 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16587 | /* 45680 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16588 | /* 45683 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16589 | /* 45687 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16590 | /* 45691 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16591 | /* 45695 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3854:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16592 | /* 45695 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16593 | /* 45698 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16594 | /* 45702 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16595 | /* 45707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16p), |
| 16596 | /* 45710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16597 | /* 45712 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16598 | /* 45714 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16599 | /* 45717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16600 | /* 45723 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16601 | /* 45729 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16602 | /* 45732 */ GIR_RootConstrainSelectedInstOperands, |
| 16603 | /* 45733 */ // GIR_Coverage, 4513, |
| 16604 | /* 45733 */ GIR_EraseRootFromParent_Done, |
| 16605 | /* 45734 */ // Label 1385: @45734 |
| 16606 | /* 45734 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1386*/ GIMT_Encode4(45806), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4515 // |
| 16607 | /* 45741 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 16608 | /* 45746 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16609 | /* 45749 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16610 | /* 45752 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16611 | /* 45755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16612 | /* 45759 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16613 | /* 45763 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16614 | /* 45767 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3850:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16615 | /* 45767 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16616 | /* 45770 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16617 | /* 45774 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16618 | /* 45779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16m), |
| 16619 | /* 45782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16620 | /* 45784 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16621 | /* 45786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16622 | /* 45789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16623 | /* 45795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16624 | /* 45801 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16625 | /* 45804 */ GIR_RootConstrainSelectedInstOperands, |
| 16626 | /* 45805 */ // GIR_Coverage, 4515, |
| 16627 | /* 45805 */ GIR_EraseRootFromParent_Done, |
| 16628 | /* 45806 */ // Label 1386: @45806 |
| 16629 | /* 45806 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1387*/ GIMT_Encode4(45878), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4517 // |
| 16630 | /* 45813 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 16631 | /* 45818 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16632 | /* 45821 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16633 | /* 45824 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16634 | /* 45827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16635 | /* 45831 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16636 | /* 45835 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16637 | /* 45839 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3848:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16638 | /* 45839 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16639 | /* 45842 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16640 | /* 45846 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16641 | /* 45851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16a), |
| 16642 | /* 45854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16643 | /* 45856 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16644 | /* 45858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16645 | /* 45861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16646 | /* 45867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16647 | /* 45873 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16648 | /* 45876 */ GIR_RootConstrainSelectedInstOperands, |
| 16649 | /* 45877 */ // GIR_Coverage, 4517, |
| 16650 | /* 45877 */ GIR_EraseRootFromParent_Done, |
| 16651 | /* 45878 */ // Label 1387: @45878 |
| 16652 | /* 45878 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1388*/ GIMT_Encode4(45950), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4519 // |
| 16653 | /* 45885 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 16654 | /* 45890 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16655 | /* 45893 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16656 | /* 45896 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16657 | /* 45899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16658 | /* 45903 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16659 | /* 45907 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16660 | /* 45911 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3852:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16661 | /* 45911 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16662 | /* 45914 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16663 | /* 45918 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16664 | /* 45923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16n), |
| 16665 | /* 45926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16666 | /* 45928 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16667 | /* 45930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16668 | /* 45933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16669 | /* 45939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16670 | /* 45945 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16671 | /* 45948 */ GIR_RootConstrainSelectedInstOperands, |
| 16672 | /* 45949 */ // GIR_Coverage, 4519, |
| 16673 | /* 45949 */ GIR_EraseRootFromParent_Done, |
| 16674 | /* 45950 */ // Label 1388: @45950 |
| 16675 | /* 45950 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1389*/ GIMT_Encode4(46022), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4521 // |
| 16676 | /* 45957 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 16677 | /* 45962 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16678 | /* 45965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16679 | /* 45968 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16680 | /* 45971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16681 | /* 45975 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16682 | /* 45979 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16683 | /* 45983 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3854:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16684 | /* 45983 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16685 | /* 45986 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16686 | /* 45990 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16687 | /* 45995 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16p), |
| 16688 | /* 45998 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16689 | /* 46000 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16690 | /* 46002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16691 | /* 46005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16692 | /* 46011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16693 | /* 46017 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16694 | /* 46020 */ GIR_RootConstrainSelectedInstOperands, |
| 16695 | /* 46021 */ // GIR_Coverage, 4521, |
| 16696 | /* 46021 */ GIR_EraseRootFromParent_Done, |
| 16697 | /* 46022 */ // Label 1389: @46022 |
| 16698 | /* 46022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1390*/ GIMT_Encode4(46094), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4523 // |
| 16699 | /* 46029 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 16700 | /* 46034 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16701 | /* 46037 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16702 | /* 46040 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16703 | /* 46043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16704 | /* 46047 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16705 | /* 46051 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16706 | /* 46055 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3850:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16707 | /* 46055 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16708 | /* 46058 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16709 | /* 46062 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16710 | /* 46067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16m), |
| 16711 | /* 46070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16712 | /* 46072 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16713 | /* 46074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16714 | /* 46077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16715 | /* 46083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16716 | /* 46089 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16717 | /* 46092 */ GIR_RootConstrainSelectedInstOperands, |
| 16718 | /* 46093 */ // GIR_Coverage, 4523, |
| 16719 | /* 46093 */ GIR_EraseRootFromParent_Done, |
| 16720 | /* 46094 */ // Label 1390: @46094 |
| 16721 | /* 46094 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1391*/ GIMT_Encode4(46166), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4525 // |
| 16722 | /* 46101 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 16723 | /* 46106 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16724 | /* 46109 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16725 | /* 46112 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16726 | /* 46115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16727 | /* 46119 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16728 | /* 46123 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16729 | /* 46127 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3848:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16730 | /* 46127 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16731 | /* 46130 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16732 | /* 46134 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16733 | /* 46139 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32a), |
| 16734 | /* 46142 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16735 | /* 46144 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16736 | /* 46146 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16737 | /* 46149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16738 | /* 46155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16739 | /* 46161 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16740 | /* 46164 */ GIR_RootConstrainSelectedInstOperands, |
| 16741 | /* 46165 */ // GIR_Coverage, 4525, |
| 16742 | /* 46165 */ GIR_EraseRootFromParent_Done, |
| 16743 | /* 46166 */ // Label 1391: @46166 |
| 16744 | /* 46166 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1392*/ GIMT_Encode4(46238), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4527 // |
| 16745 | /* 46173 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 16746 | /* 46178 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16747 | /* 46181 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16748 | /* 46184 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16749 | /* 46187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16750 | /* 46191 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16751 | /* 46195 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16752 | /* 46199 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3852:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16753 | /* 46199 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16754 | /* 46202 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16755 | /* 46206 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16756 | /* 46211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32n), |
| 16757 | /* 46214 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16758 | /* 46216 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16759 | /* 46218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16760 | /* 46221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16761 | /* 46227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16762 | /* 46233 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16763 | /* 46236 */ GIR_RootConstrainSelectedInstOperands, |
| 16764 | /* 46237 */ // GIR_Coverage, 4527, |
| 16765 | /* 46237 */ GIR_EraseRootFromParent_Done, |
| 16766 | /* 46238 */ // Label 1392: @46238 |
| 16767 | /* 46238 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1393*/ GIMT_Encode4(46310), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4529 // |
| 16768 | /* 46245 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 16769 | /* 46250 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16770 | /* 46253 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16771 | /* 46256 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16772 | /* 46259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16773 | /* 46263 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16774 | /* 46267 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16775 | /* 46271 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3854:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16776 | /* 46271 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16777 | /* 46274 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16778 | /* 46278 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16779 | /* 46283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32p), |
| 16780 | /* 46286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16781 | /* 46288 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16782 | /* 46290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16783 | /* 46293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16784 | /* 46299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16785 | /* 46305 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16786 | /* 46308 */ GIR_RootConstrainSelectedInstOperands, |
| 16787 | /* 46309 */ // GIR_Coverage, 4529, |
| 16788 | /* 46309 */ GIR_EraseRootFromParent_Done, |
| 16789 | /* 46310 */ // Label 1393: @46310 |
| 16790 | /* 46310 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1394*/ GIMT_Encode4(46382), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4531 // |
| 16791 | /* 46317 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 16792 | /* 46322 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16793 | /* 46325 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16794 | /* 46328 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16795 | /* 46331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16796 | /* 46335 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16797 | /* 46339 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16798 | /* 46343 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3850:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16799 | /* 46343 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16800 | /* 46346 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16801 | /* 46350 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16802 | /* 46355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32m), |
| 16803 | /* 46358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16804 | /* 46360 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16805 | /* 46362 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16806 | /* 46365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16807 | /* 46371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16808 | /* 46377 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16809 | /* 46380 */ GIR_RootConstrainSelectedInstOperands, |
| 16810 | /* 46381 */ // GIR_Coverage, 4531, |
| 16811 | /* 46381 */ GIR_EraseRootFromParent_Done, |
| 16812 | /* 46382 */ // Label 1394: @46382 |
| 16813 | /* 46382 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1395*/ GIMT_Encode4(46454), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4533 // |
| 16814 | /* 46389 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 16815 | /* 46394 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16816 | /* 46397 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16817 | /* 46400 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16818 | /* 46403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16819 | /* 46407 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16820 | /* 46411 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16821 | /* 46415 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3848:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16822 | /* 46415 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16823 | /* 46418 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16824 | /* 46422 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16825 | /* 46427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32a), |
| 16826 | /* 46430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16827 | /* 46432 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16828 | /* 46434 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16829 | /* 46437 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16830 | /* 46443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16831 | /* 46449 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16832 | /* 46452 */ GIR_RootConstrainSelectedInstOperands, |
| 16833 | /* 46453 */ // GIR_Coverage, 4533, |
| 16834 | /* 46453 */ GIR_EraseRootFromParent_Done, |
| 16835 | /* 46454 */ // Label 1395: @46454 |
| 16836 | /* 46454 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1396*/ GIMT_Encode4(46526), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4535 // |
| 16837 | /* 46461 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 16838 | /* 46466 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16839 | /* 46469 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16840 | /* 46472 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16841 | /* 46475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16842 | /* 46479 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16843 | /* 46483 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16844 | /* 46487 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3852:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16845 | /* 46487 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16846 | /* 46490 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16847 | /* 46494 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16848 | /* 46499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32n), |
| 16849 | /* 46502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16850 | /* 46504 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16851 | /* 46506 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16852 | /* 46509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16853 | /* 46515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16854 | /* 46521 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16855 | /* 46524 */ GIR_RootConstrainSelectedInstOperands, |
| 16856 | /* 46525 */ // GIR_Coverage, 4535, |
| 16857 | /* 46525 */ GIR_EraseRootFromParent_Done, |
| 16858 | /* 46526 */ // Label 1396: @46526 |
| 16859 | /* 46526 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1397*/ GIMT_Encode4(46598), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4537 // |
| 16860 | /* 46533 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 16861 | /* 46538 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16862 | /* 46541 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16863 | /* 46544 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16864 | /* 46547 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16865 | /* 46551 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16866 | /* 46555 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16867 | /* 46559 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3854:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16868 | /* 46559 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16869 | /* 46562 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16870 | /* 46566 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16871 | /* 46571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32p), |
| 16872 | /* 46574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16873 | /* 46576 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16874 | /* 46578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16875 | /* 46581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16876 | /* 46587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16877 | /* 46593 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16878 | /* 46596 */ GIR_RootConstrainSelectedInstOperands, |
| 16879 | /* 46597 */ // GIR_Coverage, 4537, |
| 16880 | /* 46597 */ GIR_EraseRootFromParent_Done, |
| 16881 | /* 46598 */ // Label 1397: @46598 |
| 16882 | /* 46598 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1398*/ GIMT_Encode4(46670), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4539 // |
| 16883 | /* 46605 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 16884 | /* 46610 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16885 | /* 46613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16886 | /* 46616 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16887 | /* 46619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16888 | /* 46623 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16889 | /* 46627 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16890 | /* 46631 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3850:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16891 | /* 46631 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16892 | /* 46634 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16893 | /* 46638 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16894 | /* 46643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32m), |
| 16895 | /* 46646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16896 | /* 46648 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16897 | /* 46650 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16898 | /* 46653 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16899 | /* 46659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16900 | /* 46665 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16901 | /* 46668 */ GIR_RootConstrainSelectedInstOperands, |
| 16902 | /* 46669 */ // GIR_Coverage, 4539, |
| 16903 | /* 46669 */ GIR_EraseRootFromParent_Done, |
| 16904 | /* 46670 */ // Label 1398: @46670 |
| 16905 | /* 46670 */ GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(46946), |
| 16906 | /* 46675 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp), |
| 16907 | /* 46680 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1402*/ GIMT_Encode4(46945), |
| 16908 | /* 46691 */ /*GILLT_v8s16*//*Label 1400*/ GIMT_Encode4(46703), GIMT_Encode4(0), |
| 16909 | /* 46699 */ /*GILLT_v4s32*//*Label 1401*/ GIMT_Encode4(46824), |
| 16910 | /* 46703 */ // Label 1400: @46703 |
| 16911 | /* 46703 */ GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(46823), |
| 16912 | /* 46708 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16913 | /* 46711 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16914 | /* 46714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16915 | /* 46718 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16916 | /* 46722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1404*/ GIMT_Encode4(46772), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4542 // |
| 16917 | /* 46729 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 16918 | /* 46733 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3843:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$src, 0:{ *:[i32] }) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 16919 | /* 46733 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16920 | /* 46736 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16921 | /* 46740 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16922 | /* 46745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z), |
| 16923 | /* 46748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16924 | /* 46750 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 16925 | /* 46752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16926 | /* 46755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16927 | /* 46761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16928 | /* 46767 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16929 | /* 46770 */ GIR_RootConstrainSelectedInstOperands, |
| 16930 | /* 46771 */ // GIR_Coverage, 4542, |
| 16931 | /* 46771 */ GIR_EraseRootFromParent_Done, |
| 16932 | /* 46772 */ // Label 1404: @46772 |
| 16933 | /* 46772 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1405*/ GIMT_Encode4(46822), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4545 // |
| 16934 | /* 46779 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 16935 | /* 46783 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3843:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$src, 1:{ *:[i32] }) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 16936 | /* 46783 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16937 | /* 46786 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16938 | /* 46790 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16939 | /* 46795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z), |
| 16940 | /* 46798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16941 | /* 46800 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 16942 | /* 46802 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16943 | /* 46805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16944 | /* 46811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16945 | /* 46817 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16946 | /* 46820 */ GIR_RootConstrainSelectedInstOperands, |
| 16947 | /* 46821 */ // GIR_Coverage, 4545, |
| 16948 | /* 46821 */ GIR_EraseRootFromParent_Done, |
| 16949 | /* 46822 */ // Label 1405: @46822 |
| 16950 | /* 46822 */ GIM_Reject, |
| 16951 | /* 46823 */ // Label 1403: @46823 |
| 16952 | /* 46823 */ GIM_Reject, |
| 16953 | /* 46824 */ // Label 1401: @46824 |
| 16954 | /* 46824 */ GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(46944), |
| 16955 | /* 46829 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16956 | /* 46832 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16957 | /* 46835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16958 | /* 46839 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16959 | /* 46843 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1407*/ GIMT_Encode4(46893), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4548 // |
| 16960 | /* 46850 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 16961 | /* 46854 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3843:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$src, 0:{ *:[i32] }) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 16962 | /* 46854 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16963 | /* 46857 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16964 | /* 46861 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16965 | /* 46866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z), |
| 16966 | /* 46869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16967 | /* 46871 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 16968 | /* 46873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16969 | /* 46876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16970 | /* 46882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16971 | /* 46888 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16972 | /* 46891 */ GIR_RootConstrainSelectedInstOperands, |
| 16973 | /* 46892 */ // GIR_Coverage, 4548, |
| 16974 | /* 46892 */ GIR_EraseRootFromParent_Done, |
| 16975 | /* 46893 */ // Label 1407: @46893 |
| 16976 | /* 46893 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1408*/ GIMT_Encode4(46943), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4551 // |
| 16977 | /* 46900 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 16978 | /* 46904 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3843:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$src, 1:{ *:[i32] }) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 16979 | /* 46904 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16980 | /* 46907 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16981 | /* 46911 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16982 | /* 46916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z), |
| 16983 | /* 46919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16984 | /* 46921 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 16985 | /* 46923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16986 | /* 46926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16987 | /* 46932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16988 | /* 46938 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16989 | /* 46941 */ GIR_RootConstrainSelectedInstOperands, |
| 16990 | /* 46942 */ // GIR_Coverage, 4551, |
| 16991 | /* 46942 */ GIR_EraseRootFromParent_Done, |
| 16992 | /* 46943 */ // Label 1408: @46943 |
| 16993 | /* 46943 */ GIM_Reject, |
| 16994 | /* 46944 */ // Label 1406: @46944 |
| 16995 | /* 46944 */ GIM_Reject, |
| 16996 | /* 46945 */ // Label 1402: @46945 |
| 16997 | /* 46945 */ GIM_Reject, |
| 16998 | /* 46946 */ // Label 1399: @46946 |
| 16999 | /* 46946 */ GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(47222), |
| 17000 | /* 46951 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int), |
| 17001 | /* 46956 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1412*/ GIMT_Encode4(47221), |
| 17002 | /* 46967 */ /*GILLT_v8s16*//*Label 1410*/ GIMT_Encode4(46979), GIMT_Encode4(0), |
| 17003 | /* 46975 */ /*GILLT_v4s32*//*Label 1411*/ GIMT_Encode4(47100), |
| 17004 | /* 46979 */ // Label 1410: @46979 |
| 17005 | /* 46979 */ GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(47099), |
| 17006 | /* 46984 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17007 | /* 46987 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17008 | /* 46990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17009 | /* 46994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17010 | /* 46998 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1414*/ GIMT_Encode4(47048), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4554 // |
| 17011 | /* 47005 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 17012 | /* 47009 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3841:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 0:{ *:[i32] }) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 17013 | /* 47009 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17014 | /* 47012 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17015 | /* 47016 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17016 | /* 47021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n), |
| 17017 | /* 47024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17018 | /* 47026 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17019 | /* 47028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17020 | /* 47031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17021 | /* 47037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17022 | /* 47043 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17023 | /* 47046 */ GIR_RootConstrainSelectedInstOperands, |
| 17024 | /* 47047 */ // GIR_Coverage, 4554, |
| 17025 | /* 47047 */ GIR_EraseRootFromParent_Done, |
| 17026 | /* 47048 */ // Label 1414: @47048 |
| 17027 | /* 47048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1415*/ GIMT_Encode4(47098), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4557 // |
| 17028 | /* 47055 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 17029 | /* 47059 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3841:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 1:{ *:[i32] }) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 17030 | /* 47059 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17031 | /* 47062 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17032 | /* 47066 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17033 | /* 47071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n), |
| 17034 | /* 47074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17035 | /* 47076 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17036 | /* 47078 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17037 | /* 47081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17038 | /* 47087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17039 | /* 47093 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17040 | /* 47096 */ GIR_RootConstrainSelectedInstOperands, |
| 17041 | /* 47097 */ // GIR_Coverage, 4557, |
| 17042 | /* 47097 */ GIR_EraseRootFromParent_Done, |
| 17043 | /* 47098 */ // Label 1415: @47098 |
| 17044 | /* 47098 */ GIM_Reject, |
| 17045 | /* 47099 */ // Label 1413: @47099 |
| 17046 | /* 47099 */ GIM_Reject, |
| 17047 | /* 47100 */ // Label 1411: @47100 |
| 17048 | /* 47100 */ GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(47220), |
| 17049 | /* 47105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17050 | /* 47108 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17051 | /* 47111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17052 | /* 47115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17053 | /* 47119 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1417*/ GIMT_Encode4(47169), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4560 // |
| 17054 | /* 47126 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 17055 | /* 47130 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3841:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, 0:{ *:[i32] }) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 17056 | /* 47130 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17057 | /* 47133 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17058 | /* 47137 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17059 | /* 47142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n), |
| 17060 | /* 47145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17061 | /* 47147 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17062 | /* 47149 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17063 | /* 47152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17064 | /* 47158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17065 | /* 47164 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17066 | /* 47167 */ GIR_RootConstrainSelectedInstOperands, |
| 17067 | /* 47168 */ // GIR_Coverage, 4560, |
| 17068 | /* 47168 */ GIR_EraseRootFromParent_Done, |
| 17069 | /* 47169 */ // Label 1417: @47169 |
| 17070 | /* 47169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1418*/ GIMT_Encode4(47219), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4563 // |
| 17071 | /* 47176 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 17072 | /* 47180 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3841:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, 1:{ *:[i32] }) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 17073 | /* 47180 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17074 | /* 47183 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17075 | /* 47187 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17076 | /* 47192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n), |
| 17077 | /* 47195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17078 | /* 47197 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17079 | /* 47199 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17080 | /* 47202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17081 | /* 47208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17082 | /* 47214 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17083 | /* 47217 */ GIR_RootConstrainSelectedInstOperands, |
| 17084 | /* 47218 */ // GIR_Coverage, 4563, |
| 17085 | /* 47218 */ GIR_EraseRootFromParent_Done, |
| 17086 | /* 47219 */ // Label 1418: @47219 |
| 17087 | /* 47219 */ GIM_Reject, |
| 17088 | /* 47220 */ // Label 1416: @47220 |
| 17089 | /* 47220 */ GIM_Reject, |
| 17090 | /* 47221 */ // Label 1412: @47221 |
| 17091 | /* 47221 */ GIM_Reject, |
| 17092 | /* 47222 */ // Label 1409: @47222 |
| 17093 | /* 47222 */ GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(47350), |
| 17094 | /* 47227 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen), |
| 17095 | /* 47232 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17096 | /* 47235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17097 | /* 47238 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17098 | /* 47241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17099 | /* 47245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17100 | /* 47249 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1420*/ GIMT_Encode4(47299), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5043 // |
| 17101 | /* 47256 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 17102 | /* 47260 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3846:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf32f16bh:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm) |
| 17103 | /* 47260 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17104 | /* 47263 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17105 | /* 47267 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17106 | /* 47272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16bh), |
| 17107 | /* 47275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17108 | /* 47277 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 17109 | /* 47279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17110 | /* 47282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17111 | /* 47288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17112 | /* 47294 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17113 | /* 47297 */ GIR_RootConstrainSelectedInstOperands, |
| 17114 | /* 47298 */ // GIR_Coverage, 5043, |
| 17115 | /* 47298 */ GIR_EraseRootFromParent_Done, |
| 17116 | /* 47299 */ // Label 1420: @47299 |
| 17117 | /* 47299 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1421*/ GIMT_Encode4(47349), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5049 // |
| 17118 | /* 47306 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 17119 | /* 47310 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3846:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf32f16th:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm) |
| 17120 | /* 47310 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17121 | /* 47313 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17122 | /* 47317 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17123 | /* 47322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16th), |
| 17124 | /* 47325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17125 | /* 47327 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 17126 | /* 47329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17127 | /* 47332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17128 | /* 47338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17129 | /* 47344 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17130 | /* 47347 */ GIR_RootConstrainSelectedInstOperands, |
| 17131 | /* 47348 */ // GIR_Coverage, 5049, |
| 17132 | /* 47348 */ GIR_EraseRootFromParent_Done, |
| 17133 | /* 47349 */ // Label 1421: @47349 |
| 17134 | /* 47349 */ GIM_Reject, |
| 17135 | /* 47350 */ // Label 1419: @47350 |
| 17136 | /* 47350 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1422*/ GIMT_Encode4(47417), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2069 // |
| 17137 | /* 47357 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 17138 | /* 47362 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17139 | /* 47365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17140 | /* 47368 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17141 | /* 47371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17142 | /* 47375 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17143 | /* 47379 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17144 | /* 47383 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17145 | /* 47387 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 17146 | /* 47391 */ // MIs[1] Operand 1 |
| 17147 | /* 47391 */ // No operand predicates |
| 17148 | /* 47391 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17149 | /* 47393 */ // (intrinsic_wo_chain:{ *:[i32] } 4172:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, 0:{ *:[i32] }) |
| 17150 | /* 47393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT), |
| 17151 | /* 47396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17152 | /* 47398 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 17153 | /* 47401 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 17154 | /* 47403 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17155 | /* 47406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17156 | /* 47409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17157 | /* 47415 */ GIR_RootConstrainSelectedInstOperands, |
| 17158 | /* 47416 */ // GIR_Coverage, 2069, |
| 17159 | /* 47416 */ GIR_EraseRootFromParent_Done, |
| 17160 | /* 47417 */ // Label 1422: @47417 |
| 17161 | /* 47417 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1423*/ GIMT_Encode4(47481), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2073 // |
| 17162 | /* 47424 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16), |
| 17163 | /* 47429 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17164 | /* 47432 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17165 | /* 47435 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17166 | /* 47438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17167 | /* 47442 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17168 | /* 47446 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17169 | /* 47450 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17170 | /* 47454 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 17171 | /* 47458 */ // MIs[1] Operand 1 |
| 17172 | /* 47458 */ // No operand predicates |
| 17173 | /* 47458 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17174 | /* 47460 */ // (intrinsic_wo_chain:{ *:[i32] } 4173:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPRnopc:{ *:[i32] }:$a) |
| 17175 | /* 47460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT16), |
| 17176 | /* 47463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17177 | /* 47465 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 17178 | /* 47468 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 17179 | /* 47470 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17180 | /* 47473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17181 | /* 47479 */ GIR_RootConstrainSelectedInstOperands, |
| 17182 | /* 47480 */ // GIR_Coverage, 2073, |
| 17183 | /* 47480 */ GIR_EraseRootFromParent_Done, |
| 17184 | /* 47481 */ // Label 1423: @47481 |
| 17185 | /* 47481 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1424*/ GIMT_Encode4(47548), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2345 // |
| 17186 | /* 47488 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 17187 | /* 47493 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17188 | /* 47496 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17189 | /* 47499 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17190 | /* 47502 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17191 | /* 47506 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 17192 | /* 47510 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17193 | /* 47514 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17194 | /* 47518 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 17195 | /* 47522 */ // MIs[1] Operand 1 |
| 17196 | /* 47522 */ // No operand predicates |
| 17197 | /* 47522 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17198 | /* 47524 */ // (intrinsic_wo_chain:{ *:[i32] } 4172:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPR:{ *:[i32] }:$a, 0:{ *:[i32] }) |
| 17199 | /* 47524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT), |
| 17200 | /* 47527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17201 | /* 47529 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 17202 | /* 47532 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 17203 | /* 47534 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17204 | /* 47537 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17205 | /* 47540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17206 | /* 47546 */ GIR_RootConstrainSelectedInstOperands, |
| 17207 | /* 47547 */ // GIR_Coverage, 2345, |
| 17208 | /* 47547 */ GIR_EraseRootFromParent_Done, |
| 17209 | /* 47548 */ // Label 1424: @47548 |
| 17210 | /* 47548 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1425*/ GIMT_Encode4(47612), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2347 // |
| 17211 | /* 47555 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16), |
| 17212 | /* 47560 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17213 | /* 47563 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17214 | /* 47566 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17215 | /* 47569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17216 | /* 47573 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 17217 | /* 47577 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17218 | /* 47581 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17219 | /* 47585 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 17220 | /* 47589 */ // MIs[1] Operand 1 |
| 17221 | /* 47589 */ // No operand predicates |
| 17222 | /* 47589 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17223 | /* 47591 */ // (intrinsic_wo_chain:{ *:[i32] } 4173:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (t2USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPR:{ *:[i32] }:$a) |
| 17224 | /* 47591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT16), |
| 17225 | /* 47594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17226 | /* 47596 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 17227 | /* 47599 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 17228 | /* 47601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17229 | /* 47604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17230 | /* 47610 */ GIR_RootConstrainSelectedInstOperands, |
| 17231 | /* 47611 */ // GIR_Coverage, 2347, |
| 17232 | /* 47611 */ GIR_EraseRootFromParent_Done, |
| 17233 | /* 47612 */ // Label 1425: @47612 |
| 17234 | /* 47612 */ GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(47882), |
| 17235 | /* 47617 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm), |
| 17236 | /* 47622 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 1430*/ GIMT_Encode4(47881), |
| 17237 | /* 47633 */ /*GILLT_v16s8*//*Label 1427*/ GIMT_Encode4(47653), GIMT_Encode4(0), |
| 17238 | /* 47641 */ /*GILLT_v8s16*//*Label 1428*/ GIMT_Encode4(47729), GIMT_Encode4(0), |
| 17239 | /* 47649 */ /*GILLT_v4s32*//*Label 1429*/ GIMT_Encode4(47805), |
| 17240 | /* 47653 */ // Label 1427: @47653 |
| 17241 | /* 47653 */ GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(47728), // Rule ID 4331 // |
| 17242 | /* 47658 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 17243 | /* 47661 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17244 | /* 47664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17245 | /* 47668 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17246 | /* 47672 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17247 | /* 47676 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17248 | /* 47680 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 17249 | /* 47684 */ // MIs[1] Operand 1 |
| 17250 | /* 47684 */ // No operand predicates |
| 17251 | /* 47684 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17252 | /* 47686 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3910:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) => (MVE_VQSHLU_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 17253 | /* 47686 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17254 | /* 47689 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17255 | /* 47693 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17256 | /* 47698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms8), |
| 17257 | /* 47701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17258 | /* 47703 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17259 | /* 47705 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 17260 | /* 47708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17261 | /* 47711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17262 | /* 47717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17263 | /* 47723 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17264 | /* 47726 */ GIR_RootConstrainSelectedInstOperands, |
| 17265 | /* 47727 */ // GIR_Coverage, 4331, |
| 17266 | /* 47727 */ GIR_EraseRootFromParent_Done, |
| 17267 | /* 47728 */ // Label 1431: @47728 |
| 17268 | /* 47728 */ GIM_Reject, |
| 17269 | /* 47729 */ // Label 1428: @47729 |
| 17270 | /* 47729 */ GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(47804), // Rule ID 4333 // |
| 17271 | /* 47734 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17272 | /* 47737 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17273 | /* 47740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17274 | /* 47744 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17275 | /* 47748 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17276 | /* 47752 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17277 | /* 47756 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 17278 | /* 47760 */ // MIs[1] Operand 1 |
| 17279 | /* 47760 */ // No operand predicates |
| 17280 | /* 47760 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17281 | /* 47762 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3910:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (MVE_VQSHLU_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 17282 | /* 47762 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17283 | /* 47765 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17284 | /* 47769 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17285 | /* 47774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms16), |
| 17286 | /* 47777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17287 | /* 47779 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17288 | /* 47781 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 17289 | /* 47784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17290 | /* 47787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17291 | /* 47793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17292 | /* 47799 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17293 | /* 47802 */ GIR_RootConstrainSelectedInstOperands, |
| 17294 | /* 47803 */ // GIR_Coverage, 4333, |
| 17295 | /* 47803 */ GIR_EraseRootFromParent_Done, |
| 17296 | /* 47804 */ // Label 1432: @47804 |
| 17297 | /* 47804 */ GIM_Reject, |
| 17298 | /* 47805 */ // Label 1429: @47805 |
| 17299 | /* 47805 */ GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(47880), // Rule ID 4335 // |
| 17300 | /* 47810 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17301 | /* 47813 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17302 | /* 47816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17303 | /* 47820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17304 | /* 47824 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17305 | /* 47828 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17306 | /* 47832 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 17307 | /* 47836 */ // MIs[1] Operand 1 |
| 17308 | /* 47836 */ // No operand predicates |
| 17309 | /* 47836 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17310 | /* 47838 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3910:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) => (MVE_VQSHLU_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 17311 | /* 47838 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17312 | /* 47841 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17313 | /* 47845 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17314 | /* 47850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms32), |
| 17315 | /* 47853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17316 | /* 47855 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17317 | /* 47857 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 17318 | /* 47860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17319 | /* 47863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17320 | /* 47869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17321 | /* 47875 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17322 | /* 47878 */ GIR_RootConstrainSelectedInstOperands, |
| 17323 | /* 47879 */ // GIR_Coverage, 4335, |
| 17324 | /* 47879 */ GIR_EraseRootFromParent_Done, |
| 17325 | /* 47880 */ // Label 1433: @47880 |
| 17326 | /* 47880 */ GIM_Reject, |
| 17327 | /* 47881 */ // Label 1430: @47881 |
| 17328 | /* 47881 */ GIM_Reject, |
| 17329 | /* 47882 */ // Label 1426: @47882 |
| 17330 | /* 47882 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1434*/ GIMT_Encode4(47942), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1814 // |
| 17331 | /* 47889 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 17332 | /* 47894 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 17333 | /* 47897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 17334 | /* 47900 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17335 | /* 47903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17336 | /* 47907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17337 | /* 47911 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17338 | /* 47915 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17339 | /* 47919 */ // MIs[1] Operand 1 |
| 17340 | /* 47919 */ // No operand predicates |
| 17341 | /* 47919 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17342 | /* 47921 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3994:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17343 | /* 47921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsd), |
| 17344 | /* 47924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17345 | /* 47926 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17346 | /* 47928 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17347 | /* 47931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17348 | /* 47934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17349 | /* 47940 */ GIR_RootConstrainSelectedInstOperands, |
| 17350 | /* 47941 */ // GIR_Coverage, 1814, |
| 17351 | /* 47941 */ GIR_EraseRootFromParent_Done, |
| 17352 | /* 47942 */ // Label 1434: @47942 |
| 17353 | /* 47942 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1435*/ GIMT_Encode4(48002), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1815 // |
| 17354 | /* 47949 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 17355 | /* 47954 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 17356 | /* 47957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 17357 | /* 47960 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17358 | /* 47963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17359 | /* 47967 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17360 | /* 47971 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17361 | /* 47975 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17362 | /* 47979 */ // MIs[1] Operand 1 |
| 17363 | /* 47979 */ // No operand predicates |
| 17364 | /* 47979 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17365 | /* 47981 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3995:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17366 | /* 47981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xud), |
| 17367 | /* 47984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17368 | /* 47986 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17369 | /* 47988 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17370 | /* 47991 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17371 | /* 47994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17372 | /* 48000 */ GIR_RootConstrainSelectedInstOperands, |
| 17373 | /* 48001 */ // GIR_Coverage, 1815, |
| 17374 | /* 48001 */ GIR_EraseRootFromParent_Done, |
| 17375 | /* 48002 */ // Label 1435: @48002 |
| 17376 | /* 48002 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1436*/ GIMT_Encode4(48062), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1816 // |
| 17377 | /* 48009 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 17378 | /* 48014 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 17379 | /* 48017 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 17380 | /* 48020 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17381 | /* 48023 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17382 | /* 48027 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17383 | /* 48031 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17384 | /* 48035 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17385 | /* 48039 */ // MIs[1] Operand 1 |
| 17386 | /* 48039 */ // No operand predicates |
| 17387 | /* 48039 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17388 | /* 48041 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3997:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17389 | /* 48041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fd), |
| 17390 | /* 48044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17391 | /* 48046 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17392 | /* 48048 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17393 | /* 48051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17394 | /* 48054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17395 | /* 48060 */ GIR_RootConstrainSelectedInstOperands, |
| 17396 | /* 48061 */ // GIR_Coverage, 1816, |
| 17397 | /* 48061 */ GIR_EraseRootFromParent_Done, |
| 17398 | /* 48062 */ // Label 1436: @48062 |
| 17399 | /* 48062 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1437*/ GIMT_Encode4(48122), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1817 // |
| 17400 | /* 48069 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 17401 | /* 48074 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 17402 | /* 48077 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 17403 | /* 48080 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17404 | /* 48083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17405 | /* 48087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17406 | /* 48091 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17407 | /* 48095 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17408 | /* 48099 */ // MIs[1] Operand 1 |
| 17409 | /* 48099 */ // No operand predicates |
| 17410 | /* 48099 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17411 | /* 48101 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3998:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17412 | /* 48101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fd), |
| 17413 | /* 48104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17414 | /* 48106 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17415 | /* 48108 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17416 | /* 48111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17417 | /* 48114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17418 | /* 48120 */ GIR_RootConstrainSelectedInstOperands, |
| 17419 | /* 48121 */ // GIR_Coverage, 1817, |
| 17420 | /* 48121 */ GIR_EraseRootFromParent_Done, |
| 17421 | /* 48122 */ // Label 1437: @48122 |
| 17422 | /* 48122 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1438*/ GIMT_Encode4(48182), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1818 // |
| 17423 | /* 48129 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 17424 | /* 48134 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 17425 | /* 48137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 17426 | /* 48140 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17427 | /* 48143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17428 | /* 48147 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17429 | /* 48151 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17430 | /* 48155 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17431 | /* 48159 */ // MIs[1] Operand 1 |
| 17432 | /* 48159 */ // No operand predicates |
| 17433 | /* 48159 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17434 | /* 48161 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3994:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17435 | /* 48161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsd), |
| 17436 | /* 48164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17437 | /* 48166 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17438 | /* 48168 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17439 | /* 48171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17440 | /* 48174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17441 | /* 48180 */ GIR_RootConstrainSelectedInstOperands, |
| 17442 | /* 48181 */ // GIR_Coverage, 1818, |
| 17443 | /* 48181 */ GIR_EraseRootFromParent_Done, |
| 17444 | /* 48182 */ // Label 1438: @48182 |
| 17445 | /* 48182 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1439*/ GIMT_Encode4(48242), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1819 // |
| 17446 | /* 48189 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 17447 | /* 48194 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 17448 | /* 48197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 17449 | /* 48200 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17450 | /* 48203 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17451 | /* 48207 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17452 | /* 48211 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17453 | /* 48215 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17454 | /* 48219 */ // MIs[1] Operand 1 |
| 17455 | /* 48219 */ // No operand predicates |
| 17456 | /* 48219 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17457 | /* 48221 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3995:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17458 | /* 48221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xud), |
| 17459 | /* 48224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17460 | /* 48226 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17461 | /* 48228 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17462 | /* 48231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17463 | /* 48234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17464 | /* 48240 */ GIR_RootConstrainSelectedInstOperands, |
| 17465 | /* 48241 */ // GIR_Coverage, 1819, |
| 17466 | /* 48241 */ GIR_EraseRootFromParent_Done, |
| 17467 | /* 48242 */ // Label 1439: @48242 |
| 17468 | /* 48242 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1440*/ GIMT_Encode4(48302), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1820 // |
| 17469 | /* 48249 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 17470 | /* 48254 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 17471 | /* 48257 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 17472 | /* 48260 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17473 | /* 48263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17474 | /* 48267 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17475 | /* 48271 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17476 | /* 48275 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17477 | /* 48279 */ // MIs[1] Operand 1 |
| 17478 | /* 48279 */ // No operand predicates |
| 17479 | /* 48279 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17480 | /* 48281 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3997:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17481 | /* 48281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hd), |
| 17482 | /* 48284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17483 | /* 48286 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17484 | /* 48288 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17485 | /* 48291 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17486 | /* 48294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17487 | /* 48300 */ GIR_RootConstrainSelectedInstOperands, |
| 17488 | /* 48301 */ // GIR_Coverage, 1820, |
| 17489 | /* 48301 */ GIR_EraseRootFromParent_Done, |
| 17490 | /* 48302 */ // Label 1440: @48302 |
| 17491 | /* 48302 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1441*/ GIMT_Encode4(48362), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1821 // |
| 17492 | /* 48309 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 17493 | /* 48314 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 17494 | /* 48317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 17495 | /* 48320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17496 | /* 48323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17497 | /* 48327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17498 | /* 48331 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17499 | /* 48335 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17500 | /* 48339 */ // MIs[1] Operand 1 |
| 17501 | /* 48339 */ // No operand predicates |
| 17502 | /* 48339 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17503 | /* 48341 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3998:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17504 | /* 48341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hd), |
| 17505 | /* 48344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17506 | /* 48346 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17507 | /* 48348 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17508 | /* 48351 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17509 | /* 48354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17510 | /* 48360 */ GIR_RootConstrainSelectedInstOperands, |
| 17511 | /* 48361 */ // GIR_Coverage, 1821, |
| 17512 | /* 48361 */ GIR_EraseRootFromParent_Done, |
| 17513 | /* 48362 */ // Label 1441: @48362 |
| 17514 | /* 48362 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1442*/ GIMT_Encode4(48422), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1822 // |
| 17515 | /* 48369 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 17516 | /* 48374 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17517 | /* 48377 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17518 | /* 48380 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17519 | /* 48383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17520 | /* 48387 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17521 | /* 48391 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17522 | /* 48395 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17523 | /* 48399 */ // MIs[1] Operand 1 |
| 17524 | /* 48399 */ // No operand predicates |
| 17525 | /* 48399 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17526 | /* 48401 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3994:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17527 | /* 48401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsq), |
| 17528 | /* 48404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17529 | /* 48406 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17530 | /* 48408 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17531 | /* 48411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17532 | /* 48414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17533 | /* 48420 */ GIR_RootConstrainSelectedInstOperands, |
| 17534 | /* 48421 */ // GIR_Coverage, 1822, |
| 17535 | /* 48421 */ GIR_EraseRootFromParent_Done, |
| 17536 | /* 48422 */ // Label 1442: @48422 |
| 17537 | /* 48422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1443*/ GIMT_Encode4(48482), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1823 // |
| 17538 | /* 48429 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 17539 | /* 48434 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17540 | /* 48437 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17541 | /* 48440 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17542 | /* 48443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17543 | /* 48447 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17544 | /* 48451 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17545 | /* 48455 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17546 | /* 48459 */ // MIs[1] Operand 1 |
| 17547 | /* 48459 */ // No operand predicates |
| 17548 | /* 48459 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17549 | /* 48461 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3995:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xuq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17550 | /* 48461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xuq), |
| 17551 | /* 48464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17552 | /* 48466 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17553 | /* 48468 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17554 | /* 48471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17555 | /* 48474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17556 | /* 48480 */ GIR_RootConstrainSelectedInstOperands, |
| 17557 | /* 48481 */ // GIR_Coverage, 1823, |
| 17558 | /* 48481 */ GIR_EraseRootFromParent_Done, |
| 17559 | /* 48482 */ // Label 1443: @48482 |
| 17560 | /* 48482 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1444*/ GIMT_Encode4(48542), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1824 // |
| 17561 | /* 48489 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 17562 | /* 48494 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17563 | /* 48497 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17564 | /* 48500 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17565 | /* 48503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17566 | /* 48507 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17567 | /* 48511 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17568 | /* 48515 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17569 | /* 48519 */ // MIs[1] Operand 1 |
| 17570 | /* 48519 */ // No operand predicates |
| 17571 | /* 48519 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17572 | /* 48521 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3997:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17573 | /* 48521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fq), |
| 17574 | /* 48524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17575 | /* 48526 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17576 | /* 48528 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17577 | /* 48531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17578 | /* 48534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17579 | /* 48540 */ GIR_RootConstrainSelectedInstOperands, |
| 17580 | /* 48541 */ // GIR_Coverage, 1824, |
| 17581 | /* 48541 */ GIR_EraseRootFromParent_Done, |
| 17582 | /* 48542 */ // Label 1444: @48542 |
| 17583 | /* 48542 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1445*/ GIMT_Encode4(48602), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1825 // |
| 17584 | /* 48549 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 17585 | /* 48554 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17586 | /* 48557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17587 | /* 48560 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17588 | /* 48563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17589 | /* 48567 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17590 | /* 48571 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17591 | /* 48575 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17592 | /* 48579 */ // MIs[1] Operand 1 |
| 17593 | /* 48579 */ // No operand predicates |
| 17594 | /* 48579 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17595 | /* 48581 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3998:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17596 | /* 48581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fq), |
| 17597 | /* 48584 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17598 | /* 48586 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17599 | /* 48588 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17600 | /* 48591 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17601 | /* 48594 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17602 | /* 48600 */ GIR_RootConstrainSelectedInstOperands, |
| 17603 | /* 48601 */ // GIR_Coverage, 1825, |
| 17604 | /* 48601 */ GIR_EraseRootFromParent_Done, |
| 17605 | /* 48602 */ // Label 1445: @48602 |
| 17606 | /* 48602 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1446*/ GIMT_Encode4(48662), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1826 // |
| 17607 | /* 48609 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 17608 | /* 48614 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17609 | /* 48617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17610 | /* 48620 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17611 | /* 48623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17612 | /* 48627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17613 | /* 48631 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17614 | /* 48635 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17615 | /* 48639 */ // MIs[1] Operand 1 |
| 17616 | /* 48639 */ // No operand predicates |
| 17617 | /* 48639 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17618 | /* 48641 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3994:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17619 | /* 48641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsq), |
| 17620 | /* 48644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17621 | /* 48646 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17622 | /* 48648 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17623 | /* 48651 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17624 | /* 48654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17625 | /* 48660 */ GIR_RootConstrainSelectedInstOperands, |
| 17626 | /* 48661 */ // GIR_Coverage, 1826, |
| 17627 | /* 48661 */ GIR_EraseRootFromParent_Done, |
| 17628 | /* 48662 */ // Label 1446: @48662 |
| 17629 | /* 48662 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1447*/ GIMT_Encode4(48722), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1827 // |
| 17630 | /* 48669 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 17631 | /* 48674 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17632 | /* 48677 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17633 | /* 48680 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17634 | /* 48683 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17635 | /* 48687 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17636 | /* 48691 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17637 | /* 48695 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17638 | /* 48699 */ // MIs[1] Operand 1 |
| 17639 | /* 48699 */ // No operand predicates |
| 17640 | /* 48699 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17641 | /* 48701 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xuq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17642 | /* 48701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xuq), |
| 17643 | /* 48704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17644 | /* 48706 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17645 | /* 48708 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17646 | /* 48711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17647 | /* 48714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17648 | /* 48720 */ GIR_RootConstrainSelectedInstOperands, |
| 17649 | /* 48721 */ // GIR_Coverage, 1827, |
| 17650 | /* 48721 */ GIR_EraseRootFromParent_Done, |
| 17651 | /* 48722 */ // Label 1447: @48722 |
| 17652 | /* 48722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1448*/ GIMT_Encode4(48782), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1828 // |
| 17653 | /* 48729 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 17654 | /* 48734 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17655 | /* 48737 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17656 | /* 48740 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17657 | /* 48743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17658 | /* 48747 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17659 | /* 48751 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17660 | /* 48755 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17661 | /* 48759 */ // MIs[1] Operand 1 |
| 17662 | /* 48759 */ // No operand predicates |
| 17663 | /* 48759 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17664 | /* 48761 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3997:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17665 | /* 48761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hq), |
| 17666 | /* 48764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17667 | /* 48766 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17668 | /* 48768 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17669 | /* 48771 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17670 | /* 48774 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17671 | /* 48780 */ GIR_RootConstrainSelectedInstOperands, |
| 17672 | /* 48781 */ // GIR_Coverage, 1828, |
| 17673 | /* 48781 */ GIR_EraseRootFromParent_Done, |
| 17674 | /* 48782 */ // Label 1448: @48782 |
| 17675 | /* 48782 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1449*/ GIMT_Encode4(48842), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1829 // |
| 17676 | /* 48789 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 17677 | /* 48794 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17678 | /* 48797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17679 | /* 48800 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17680 | /* 48803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17681 | /* 48807 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17682 | /* 48811 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17683 | /* 48815 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17684 | /* 48819 */ // MIs[1] Operand 1 |
| 17685 | /* 48819 */ // No operand predicates |
| 17686 | /* 48819 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17687 | /* 48821 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3998:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17688 | /* 48821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hq), |
| 17689 | /* 48824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17690 | /* 48826 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17691 | /* 48828 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17692 | /* 48831 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17693 | /* 48834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17694 | /* 48840 */ GIR_RootConstrainSelectedInstOperands, |
| 17695 | /* 48841 */ // GIR_Coverage, 1829, |
| 17696 | /* 48841 */ GIR_EraseRootFromParent_Done, |
| 17697 | /* 48842 */ // Label 1449: @48842 |
| 17698 | /* 48842 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1450*/ GIMT_Encode4(48902), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1911 // |
| 17699 | /* 48849 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqshl), |
| 17700 | /* 48854 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17701 | /* 48857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17702 | /* 48860 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17703 | /* 48863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17704 | /* 48867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17705 | /* 48871 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17706 | /* 48875 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17707 | /* 48879 */ // MIs[1] Operand 1 |
| 17708 | /* 48879 */ // No operand predicates |
| 17709 | /* 48879 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17710 | /* 48881 */ // (intrinsic_wo_chain:{ *:[i32] } 3809:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 17711 | /* 48881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQSHL), |
| 17712 | /* 48884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 17713 | /* 48886 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 17714 | /* 48888 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 17715 | /* 48891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17716 | /* 48894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17717 | /* 48900 */ GIR_RootConstrainSelectedInstOperands, |
| 17718 | /* 48901 */ // GIR_Coverage, 1911, |
| 17719 | /* 48901 */ GIR_EraseRootFromParent_Done, |
| 17720 | /* 48902 */ // Label 1450: @48902 |
| 17721 | /* 48902 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1451*/ GIMT_Encode4(48962), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1912 // |
| 17722 | /* 48909 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_srshr), |
| 17723 | /* 48914 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17724 | /* 48917 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17725 | /* 48920 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17726 | /* 48923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17727 | /* 48927 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17728 | /* 48931 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17729 | /* 48935 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17730 | /* 48939 */ // MIs[1] Operand 1 |
| 17731 | /* 48939 */ // No operand predicates |
| 17732 | /* 48939 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17733 | /* 48941 */ // (intrinsic_wo_chain:{ *:[i32] } 3811:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 17734 | /* 48941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SRSHR), |
| 17735 | /* 48944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 17736 | /* 48946 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 17737 | /* 48948 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 17738 | /* 48951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17739 | /* 48954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17740 | /* 48960 */ GIR_RootConstrainSelectedInstOperands, |
| 17741 | /* 48961 */ // GIR_Coverage, 1912, |
| 17742 | /* 48961 */ GIR_EraseRootFromParent_Done, |
| 17743 | /* 48962 */ // Label 1451: @48962 |
| 17744 | /* 48962 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1452*/ GIMT_Encode4(49022), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1913 // |
| 17745 | /* 48969 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqshl), |
| 17746 | /* 48974 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17747 | /* 48977 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17748 | /* 48980 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17749 | /* 48983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17750 | /* 48987 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17751 | /* 48991 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17752 | /* 48995 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17753 | /* 48999 */ // MIs[1] Operand 1 |
| 17754 | /* 48999 */ // No operand predicates |
| 17755 | /* 48999 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17756 | /* 49001 */ // (intrinsic_wo_chain:{ *:[i32] } 3816:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_UQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 17757 | /* 49001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQSHL), |
| 17758 | /* 49004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 17759 | /* 49006 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 17760 | /* 49008 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 17761 | /* 49011 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17762 | /* 49014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17763 | /* 49020 */ GIR_RootConstrainSelectedInstOperands, |
| 17764 | /* 49021 */ // GIR_Coverage, 1913, |
| 17765 | /* 49021 */ GIR_EraseRootFromParent_Done, |
| 17766 | /* 49022 */ // Label 1452: @49022 |
| 17767 | /* 49022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1453*/ GIMT_Encode4(49082), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1914 // |
| 17768 | /* 49029 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_urshr), |
| 17769 | /* 49034 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17770 | /* 49037 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17771 | /* 49040 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17772 | /* 49043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17773 | /* 49047 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17774 | /* 49051 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17775 | /* 49055 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17776 | /* 49059 */ // MIs[1] Operand 1 |
| 17777 | /* 49059 */ // No operand predicates |
| 17778 | /* 49059 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17779 | /* 49061 */ // (intrinsic_wo_chain:{ *:[i32] } 3818:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_URSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 17780 | /* 49061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_URSHR), |
| 17781 | /* 49064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 17782 | /* 49066 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 17783 | /* 49068 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 17784 | /* 49071 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17785 | /* 49074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17786 | /* 49080 */ GIR_RootConstrainSelectedInstOperands, |
| 17787 | /* 49081 */ // GIR_Coverage, 1914, |
| 17788 | /* 49081 */ GIR_EraseRootFromParent_Done, |
| 17789 | /* 49082 */ // Label 1453: @49082 |
| 17790 | /* 49082 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1454*/ GIMT_Encode4(49135), GIMT_Encode2(GIFBS_IsARM), // Rule ID 104 // |
| 17791 | /* 49089 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8), |
| 17792 | /* 49094 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17793 | /* 49097 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17794 | /* 49100 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17795 | /* 49103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17796 | /* 49107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17797 | /* 49111 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17798 | /* 49115 */ // (intrinsic_wo_chain:{ *:[i32] } 4097:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17799 | /* 49115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD8), |
| 17800 | /* 49118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17801 | /* 49120 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17802 | /* 49122 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17803 | /* 49124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17804 | /* 49127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17805 | /* 49133 */ GIR_RootConstrainSelectedInstOperands, |
| 17806 | /* 49134 */ // GIR_Coverage, 104, |
| 17807 | /* 49134 */ GIR_EraseRootFromParent_Done, |
| 17808 | /* 49135 */ // Label 1454: @49135 |
| 17809 | /* 49135 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1455*/ GIMT_Encode4(49188), GIMT_Encode2(GIFBS_IsARM), // Rule ID 105 // |
| 17810 | /* 49142 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16), |
| 17811 | /* 49147 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17812 | /* 49150 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17813 | /* 49153 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17814 | /* 49156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17815 | /* 49160 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17816 | /* 49164 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17817 | /* 49168 */ // (intrinsic_wo_chain:{ *:[i32] } 4096:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17818 | /* 49168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD16), |
| 17819 | /* 49171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17820 | /* 49173 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17821 | /* 49175 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17822 | /* 49177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17823 | /* 49180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17824 | /* 49186 */ GIR_RootConstrainSelectedInstOperands, |
| 17825 | /* 49187 */ // GIR_Coverage, 105, |
| 17826 | /* 49187 */ GIR_EraseRootFromParent_Done, |
| 17827 | /* 49188 */ // Label 1455: @49188 |
| 17828 | /* 49188 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1456*/ GIMT_Encode4(49241), GIMT_Encode2(GIFBS_IsARM), // Rule ID 106 // |
| 17829 | /* 49195 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16), |
| 17830 | /* 49200 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17831 | /* 49203 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17832 | /* 49206 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17833 | /* 49209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17834 | /* 49213 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17835 | /* 49217 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17836 | /* 49221 */ // (intrinsic_wo_chain:{ *:[i32] } 4101:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17837 | /* 49221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB16), |
| 17838 | /* 49224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17839 | /* 49226 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17840 | /* 49228 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17841 | /* 49230 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17842 | /* 49233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17843 | /* 49239 */ GIR_RootConstrainSelectedInstOperands, |
| 17844 | /* 49240 */ // GIR_Coverage, 106, |
| 17845 | /* 49240 */ GIR_EraseRootFromParent_Done, |
| 17846 | /* 49241 */ // Label 1456: @49241 |
| 17847 | /* 49241 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1457*/ GIMT_Encode4(49294), GIMT_Encode2(GIFBS_IsARM), // Rule ID 107 // |
| 17848 | /* 49248 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8), |
| 17849 | /* 49253 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17850 | /* 49256 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17851 | /* 49259 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17852 | /* 49262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17853 | /* 49266 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17854 | /* 49270 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17855 | /* 49274 */ // (intrinsic_wo_chain:{ *:[i32] } 4102:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17856 | /* 49274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB8), |
| 17857 | /* 49277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17858 | /* 49279 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17859 | /* 49281 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17860 | /* 49283 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17861 | /* 49286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17862 | /* 49292 */ GIR_RootConstrainSelectedInstOperands, |
| 17863 | /* 49293 */ // GIR_Coverage, 107, |
| 17864 | /* 49293 */ GIR_EraseRootFromParent_Done, |
| 17865 | /* 49294 */ // Label 1457: @49294 |
| 17866 | /* 49294 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1458*/ GIMT_Encode4(49347), GIMT_Encode2(GIFBS_IsARM), // Rule ID 110 // |
| 17867 | /* 49301 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 17868 | /* 49306 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17869 | /* 49309 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17870 | /* 49312 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17871 | /* 49315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17872 | /* 49319 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17873 | /* 49323 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17874 | /* 49327 */ // (intrinsic_wo_chain:{ *:[i32] } 4100:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 17875 | /* 49327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB), |
| 17876 | /* 49330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17877 | /* 49332 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 17878 | /* 49334 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 17879 | /* 49336 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17880 | /* 49339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17881 | /* 49345 */ GIR_RootConstrainSelectedInstOperands, |
| 17882 | /* 49346 */ // GIR_Coverage, 110, |
| 17883 | /* 49346 */ GIR_EraseRootFromParent_Done, |
| 17884 | /* 49347 */ // Label 1458: @49347 |
| 17885 | /* 49347 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1459*/ GIMT_Encode4(49400), GIMT_Encode2(GIFBS_IsARM), // Rule ID 111 // |
| 17886 | /* 49354 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 17887 | /* 49359 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17888 | /* 49362 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17889 | /* 49365 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17890 | /* 49368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17891 | /* 49372 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17892 | /* 49376 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17893 | /* 49380 */ // (intrinsic_wo_chain:{ *:[i32] } 4095:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 17894 | /* 49380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD), |
| 17895 | /* 49383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17896 | /* 49385 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 17897 | /* 49387 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 17898 | /* 49389 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17899 | /* 49392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17900 | /* 49398 */ GIR_RootConstrainSelectedInstOperands, |
| 17901 | /* 49399 */ // GIR_Coverage, 111, |
| 17902 | /* 49399 */ GIR_EraseRootFromParent_Done, |
| 17903 | /* 49400 */ // Label 1459: @49400 |
| 17904 | /* 49400 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1460*/ GIMT_Encode4(49453), GIMT_Encode2(GIFBS_IsARM), // Rule ID 112 // |
| 17905 | /* 49407 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16), |
| 17906 | /* 49412 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17907 | /* 49415 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17908 | /* 49418 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17909 | /* 49421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17910 | /* 49425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17911 | /* 49429 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17912 | /* 49433 */ // (intrinsic_wo_chain:{ *:[i32] } 4164:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17913 | /* 49433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD16), |
| 17914 | /* 49436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17915 | /* 49438 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17916 | /* 49440 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17917 | /* 49442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17918 | /* 49445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17919 | /* 49451 */ GIR_RootConstrainSelectedInstOperands, |
| 17920 | /* 49452 */ // GIR_Coverage, 112, |
| 17921 | /* 49452 */ GIR_EraseRootFromParent_Done, |
| 17922 | /* 49453 */ // Label 1460: @49453 |
| 17923 | /* 49453 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1461*/ GIMT_Encode4(49506), GIMT_Encode2(GIFBS_IsARM), // Rule ID 113 // |
| 17924 | /* 49460 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8), |
| 17925 | /* 49465 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17926 | /* 49468 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17927 | /* 49471 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17928 | /* 49474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17929 | /* 49478 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17930 | /* 49482 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17931 | /* 49486 */ // (intrinsic_wo_chain:{ *:[i32] } 4165:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17932 | /* 49486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD8), |
| 17933 | /* 49489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17934 | /* 49491 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17935 | /* 49493 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17936 | /* 49495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17937 | /* 49498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17938 | /* 49504 */ GIR_RootConstrainSelectedInstOperands, |
| 17939 | /* 49505 */ // GIR_Coverage, 113, |
| 17940 | /* 49505 */ GIR_EraseRootFromParent_Done, |
| 17941 | /* 49506 */ // Label 1461: @49506 |
| 17942 | /* 49506 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1462*/ GIMT_Encode4(49559), GIMT_Encode2(GIFBS_IsARM), // Rule ID 114 // |
| 17943 | /* 49513 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16), |
| 17944 | /* 49518 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17945 | /* 49521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17946 | /* 49524 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17947 | /* 49527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17948 | /* 49531 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17949 | /* 49535 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17950 | /* 49539 */ // (intrinsic_wo_chain:{ *:[i32] } 4168:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17951 | /* 49539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB16), |
| 17952 | /* 49542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17953 | /* 49544 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17954 | /* 49546 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17955 | /* 49548 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17956 | /* 49551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17957 | /* 49557 */ GIR_RootConstrainSelectedInstOperands, |
| 17958 | /* 49558 */ // GIR_Coverage, 114, |
| 17959 | /* 49558 */ GIR_EraseRootFromParent_Done, |
| 17960 | /* 49559 */ // Label 1462: @49559 |
| 17961 | /* 49559 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1463*/ GIMT_Encode4(49612), GIMT_Encode2(GIFBS_IsARM), // Rule ID 115 // |
| 17962 | /* 49566 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8), |
| 17963 | /* 49571 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17964 | /* 49574 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17965 | /* 49577 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17966 | /* 49580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17967 | /* 49584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17968 | /* 49588 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17969 | /* 49592 */ // (intrinsic_wo_chain:{ *:[i32] } 4169:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17970 | /* 49592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB8), |
| 17971 | /* 49595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17972 | /* 49597 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17973 | /* 49599 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17974 | /* 49601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17975 | /* 49604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17976 | /* 49610 */ GIR_RootConstrainSelectedInstOperands, |
| 17977 | /* 49611 */ // GIR_Coverage, 115, |
| 17978 | /* 49611 */ GIR_EraseRootFromParent_Done, |
| 17979 | /* 49612 */ // Label 1463: @49612 |
| 17980 | /* 49612 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1464*/ GIMT_Encode4(49665), GIMT_Encode2(GIFBS_IsARM), // Rule ID 116 // |
| 17981 | /* 49619 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx), |
| 17982 | /* 49624 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17983 | /* 49627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17984 | /* 49630 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17985 | /* 49633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17986 | /* 49637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17987 | /* 49641 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17988 | /* 49645 */ // (intrinsic_wo_chain:{ *:[i32] } 4098:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17989 | /* 49645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QASX), |
| 17990 | /* 49648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17991 | /* 49650 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17992 | /* 49652 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17993 | /* 49654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17994 | /* 49657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17995 | /* 49663 */ GIR_RootConstrainSelectedInstOperands, |
| 17996 | /* 49664 */ // GIR_Coverage, 116, |
| 17997 | /* 49664 */ GIR_EraseRootFromParent_Done, |
| 17998 | /* 49665 */ // Label 1464: @49665 |
| 17999 | /* 49665 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1465*/ GIMT_Encode4(49718), GIMT_Encode2(GIFBS_IsARM), // Rule ID 117 // |
| 18000 | /* 49672 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax), |
| 18001 | /* 49677 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18002 | /* 49680 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18003 | /* 49683 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18004 | /* 49686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18005 | /* 49690 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18006 | /* 49694 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18007 | /* 49698 */ // (intrinsic_wo_chain:{ *:[i32] } 4099:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18008 | /* 49698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSAX), |
| 18009 | /* 49701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18010 | /* 49703 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18011 | /* 49705 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18012 | /* 49707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18013 | /* 49710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18014 | /* 49716 */ GIR_RootConstrainSelectedInstOperands, |
| 18015 | /* 49717 */ // GIR_Coverage, 117, |
| 18016 | /* 49717 */ GIR_EraseRootFromParent_Done, |
| 18017 | /* 49718 */ // Label 1465: @49718 |
| 18018 | /* 49718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1466*/ GIMT_Encode4(49771), GIMT_Encode2(GIFBS_IsARM), // Rule ID 118 // |
| 18019 | /* 49725 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx), |
| 18020 | /* 49730 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18021 | /* 49733 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18022 | /* 49736 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18023 | /* 49739 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18024 | /* 49743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18025 | /* 49747 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18026 | /* 49751 */ // (intrinsic_wo_chain:{ *:[i32] } 4166:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18027 | /* 49751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQASX), |
| 18028 | /* 49754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18029 | /* 49756 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18030 | /* 49758 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18031 | /* 49760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18032 | /* 49763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18033 | /* 49769 */ GIR_RootConstrainSelectedInstOperands, |
| 18034 | /* 49770 */ // GIR_Coverage, 118, |
| 18035 | /* 49770 */ GIR_EraseRootFromParent_Done, |
| 18036 | /* 49771 */ // Label 1466: @49771 |
| 18037 | /* 49771 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1467*/ GIMT_Encode4(49824), GIMT_Encode2(GIFBS_IsARM), // Rule ID 119 // |
| 18038 | /* 49778 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax), |
| 18039 | /* 49783 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18040 | /* 49786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18041 | /* 49789 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18042 | /* 49792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18043 | /* 49796 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18044 | /* 49800 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18045 | /* 49804 */ // (intrinsic_wo_chain:{ *:[i32] } 4167:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18046 | /* 49804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSAX), |
| 18047 | /* 49807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18048 | /* 49809 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18049 | /* 49811 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18050 | /* 49813 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18051 | /* 49816 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18052 | /* 49822 */ GIR_RootConstrainSelectedInstOperands, |
| 18053 | /* 49823 */ // GIR_Coverage, 119, |
| 18054 | /* 49823 */ GIR_EraseRootFromParent_Done, |
| 18055 | /* 49824 */ // Label 1467: @49824 |
| 18056 | /* 49824 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1468*/ GIMT_Encode4(49877), GIMT_Encode2(GIFBS_IsARM), // Rule ID 132 // |
| 18057 | /* 49831 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx), |
| 18058 | /* 49836 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18059 | /* 49839 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18060 | /* 49842 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18061 | /* 49845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18062 | /* 49849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18063 | /* 49853 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18064 | /* 49857 */ // (intrinsic_wo_chain:{ *:[i32] } 4110:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18065 | /* 49857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHASX), |
| 18066 | /* 49860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18067 | /* 49862 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18068 | /* 49864 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18069 | /* 49866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18070 | /* 49869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18071 | /* 49875 */ GIR_RootConstrainSelectedInstOperands, |
| 18072 | /* 49876 */ // GIR_Coverage, 132, |
| 18073 | /* 49876 */ GIR_EraseRootFromParent_Done, |
| 18074 | /* 49877 */ // Label 1468: @49877 |
| 18075 | /* 49877 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1469*/ GIMT_Encode4(49930), GIMT_Encode2(GIFBS_IsARM), // Rule ID 133 // |
| 18076 | /* 49884 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16), |
| 18077 | /* 49889 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18078 | /* 49892 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18079 | /* 49895 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18080 | /* 49898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18081 | /* 49902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18082 | /* 49906 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18083 | /* 49910 */ // (intrinsic_wo_chain:{ *:[i32] } 4108:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18084 | /* 49910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD16), |
| 18085 | /* 49913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18086 | /* 49915 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18087 | /* 49917 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18088 | /* 49919 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18089 | /* 49922 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18090 | /* 49928 */ GIR_RootConstrainSelectedInstOperands, |
| 18091 | /* 49929 */ // GIR_Coverage, 133, |
| 18092 | /* 49929 */ GIR_EraseRootFromParent_Done, |
| 18093 | /* 49930 */ // Label 1469: @49930 |
| 18094 | /* 49930 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1470*/ GIMT_Encode4(49983), GIMT_Encode2(GIFBS_IsARM), // Rule ID 134 // |
| 18095 | /* 49937 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8), |
| 18096 | /* 49942 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18097 | /* 49945 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18098 | /* 49948 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18099 | /* 49951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18100 | /* 49955 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18101 | /* 49959 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18102 | /* 49963 */ // (intrinsic_wo_chain:{ *:[i32] } 4109:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18103 | /* 49963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD8), |
| 18104 | /* 49966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18105 | /* 49968 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18106 | /* 49970 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18107 | /* 49972 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18108 | /* 49975 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18109 | /* 49981 */ GIR_RootConstrainSelectedInstOperands, |
| 18110 | /* 49982 */ // GIR_Coverage, 134, |
| 18111 | /* 49982 */ GIR_EraseRootFromParent_Done, |
| 18112 | /* 49983 */ // Label 1470: @49983 |
| 18113 | /* 49983 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1471*/ GIMT_Encode4(50036), GIMT_Encode2(GIFBS_IsARM), // Rule ID 135 // |
| 18114 | /* 49990 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax), |
| 18115 | /* 49995 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18116 | /* 49998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18117 | /* 50001 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18118 | /* 50004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18119 | /* 50008 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18120 | /* 50012 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18121 | /* 50016 */ // (intrinsic_wo_chain:{ *:[i32] } 4111:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18122 | /* 50016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSAX), |
| 18123 | /* 50019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18124 | /* 50021 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18125 | /* 50023 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18126 | /* 50025 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18127 | /* 50028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18128 | /* 50034 */ GIR_RootConstrainSelectedInstOperands, |
| 18129 | /* 50035 */ // GIR_Coverage, 135, |
| 18130 | /* 50035 */ GIR_EraseRootFromParent_Done, |
| 18131 | /* 50036 */ // Label 1471: @50036 |
| 18132 | /* 50036 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1472*/ GIMT_Encode4(50089), GIMT_Encode2(GIFBS_IsARM), // Rule ID 136 // |
| 18133 | /* 50043 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16), |
| 18134 | /* 50048 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18135 | /* 50051 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18136 | /* 50054 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18137 | /* 50057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18138 | /* 50061 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18139 | /* 50065 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18140 | /* 50069 */ // (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18141 | /* 50069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB16), |
| 18142 | /* 50072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18143 | /* 50074 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18144 | /* 50076 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18145 | /* 50078 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18146 | /* 50081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18147 | /* 50087 */ GIR_RootConstrainSelectedInstOperands, |
| 18148 | /* 50088 */ // GIR_Coverage, 136, |
| 18149 | /* 50088 */ GIR_EraseRootFromParent_Done, |
| 18150 | /* 50089 */ // Label 1472: @50089 |
| 18151 | /* 50089 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1473*/ GIMT_Encode4(50142), GIMT_Encode2(GIFBS_IsARM), // Rule ID 137 // |
| 18152 | /* 50096 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8), |
| 18153 | /* 50101 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18154 | /* 50104 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18155 | /* 50107 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18156 | /* 50110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18157 | /* 50114 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18158 | /* 50118 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18159 | /* 50122 */ // (intrinsic_wo_chain:{ *:[i32] } 4113:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18160 | /* 50122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB8), |
| 18161 | /* 50125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18162 | /* 50127 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18163 | /* 50129 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18164 | /* 50131 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18165 | /* 50134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18166 | /* 50140 */ GIR_RootConstrainSelectedInstOperands, |
| 18167 | /* 50141 */ // GIR_Coverage, 137, |
| 18168 | /* 50141 */ GIR_EraseRootFromParent_Done, |
| 18169 | /* 50142 */ // Label 1473: @50142 |
| 18170 | /* 50142 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1474*/ GIMT_Encode4(50195), GIMT_Encode2(GIFBS_IsARM), // Rule ID 138 // |
| 18171 | /* 50149 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx), |
| 18172 | /* 50154 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18173 | /* 50157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18174 | /* 50160 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18175 | /* 50163 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18176 | /* 50167 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18177 | /* 50171 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18178 | /* 50175 */ // (intrinsic_wo_chain:{ *:[i32] } 4159:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18179 | /* 50175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHASX), |
| 18180 | /* 50178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18181 | /* 50180 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18182 | /* 50182 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18183 | /* 50184 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18184 | /* 50187 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18185 | /* 50193 */ GIR_RootConstrainSelectedInstOperands, |
| 18186 | /* 50194 */ // GIR_Coverage, 138, |
| 18187 | /* 50194 */ GIR_EraseRootFromParent_Done, |
| 18188 | /* 50195 */ // Label 1474: @50195 |
| 18189 | /* 50195 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1475*/ GIMT_Encode4(50248), GIMT_Encode2(GIFBS_IsARM), // Rule ID 139 // |
| 18190 | /* 50202 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16), |
| 18191 | /* 50207 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18192 | /* 50210 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18193 | /* 50213 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18194 | /* 50216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18195 | /* 50220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18196 | /* 50224 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18197 | /* 50228 */ // (intrinsic_wo_chain:{ *:[i32] } 4157:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18198 | /* 50228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD16), |
| 18199 | /* 50231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18200 | /* 50233 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18201 | /* 50235 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18202 | /* 50237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18203 | /* 50240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18204 | /* 50246 */ GIR_RootConstrainSelectedInstOperands, |
| 18205 | /* 50247 */ // GIR_Coverage, 139, |
| 18206 | /* 50247 */ GIR_EraseRootFromParent_Done, |
| 18207 | /* 50248 */ // Label 1475: @50248 |
| 18208 | /* 50248 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1476*/ GIMT_Encode4(50301), GIMT_Encode2(GIFBS_IsARM), // Rule ID 140 // |
| 18209 | /* 50255 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8), |
| 18210 | /* 50260 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18211 | /* 50263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18212 | /* 50266 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18213 | /* 50269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18214 | /* 50273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18215 | /* 50277 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18216 | /* 50281 */ // (intrinsic_wo_chain:{ *:[i32] } 4158:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18217 | /* 50281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD8), |
| 18218 | /* 50284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18219 | /* 50286 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18220 | /* 50288 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18221 | /* 50290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18222 | /* 50293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18223 | /* 50299 */ GIR_RootConstrainSelectedInstOperands, |
| 18224 | /* 50300 */ // GIR_Coverage, 140, |
| 18225 | /* 50300 */ GIR_EraseRootFromParent_Done, |
| 18226 | /* 50301 */ // Label 1476: @50301 |
| 18227 | /* 50301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1477*/ GIMT_Encode4(50354), GIMT_Encode2(GIFBS_IsARM), // Rule ID 141 // |
| 18228 | /* 50308 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax), |
| 18229 | /* 50313 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18230 | /* 50316 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18231 | /* 50319 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18232 | /* 50322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18233 | /* 50326 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18234 | /* 50330 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18235 | /* 50334 */ // (intrinsic_wo_chain:{ *:[i32] } 4160:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18236 | /* 50334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSAX), |
| 18237 | /* 50337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18238 | /* 50339 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18239 | /* 50341 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18240 | /* 50343 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18241 | /* 50346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18242 | /* 50352 */ GIR_RootConstrainSelectedInstOperands, |
| 18243 | /* 50353 */ // GIR_Coverage, 141, |
| 18244 | /* 50353 */ GIR_EraseRootFromParent_Done, |
| 18245 | /* 50354 */ // Label 1477: @50354 |
| 18246 | /* 50354 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1478*/ GIMT_Encode4(50407), GIMT_Encode2(GIFBS_IsARM), // Rule ID 142 // |
| 18247 | /* 50361 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16), |
| 18248 | /* 50366 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18249 | /* 50369 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18250 | /* 50372 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18251 | /* 50375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18252 | /* 50379 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18253 | /* 50383 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18254 | /* 50387 */ // (intrinsic_wo_chain:{ *:[i32] } 4161:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18255 | /* 50387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB16), |
| 18256 | /* 50390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18257 | /* 50392 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18258 | /* 50394 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18259 | /* 50396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18260 | /* 50399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18261 | /* 50405 */ GIR_RootConstrainSelectedInstOperands, |
| 18262 | /* 50406 */ // GIR_Coverage, 142, |
| 18263 | /* 50406 */ GIR_EraseRootFromParent_Done, |
| 18264 | /* 50407 */ // Label 1478: @50407 |
| 18265 | /* 50407 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1479*/ GIMT_Encode4(50460), GIMT_Encode2(GIFBS_IsARM), // Rule ID 143 // |
| 18266 | /* 50414 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8), |
| 18267 | /* 50419 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18268 | /* 50422 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18269 | /* 50425 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18270 | /* 50428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18271 | /* 50432 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18272 | /* 50436 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18273 | /* 50440 */ // (intrinsic_wo_chain:{ *:[i32] } 4162:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18274 | /* 50440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB8), |
| 18275 | /* 50443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18276 | /* 50445 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18277 | /* 50447 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18278 | /* 50449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18279 | /* 50452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18280 | /* 50458 */ GIR_RootConstrainSelectedInstOperands, |
| 18281 | /* 50459 */ // GIR_Coverage, 143, |
| 18282 | /* 50459 */ GIR_EraseRootFromParent_Done, |
| 18283 | /* 50460 */ // Label 1479: @50460 |
| 18284 | /* 50460 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1480*/ GIMT_Encode4(50513), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 144 // |
| 18285 | /* 50467 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8), |
| 18286 | /* 50472 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18287 | /* 50475 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18288 | /* 50478 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18289 | /* 50481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 18290 | /* 50485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 18291 | /* 50489 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 18292 | /* 50493 */ // (intrinsic_wo_chain:{ *:[i32] } 4170:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (USAD8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 18293 | /* 50493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAD8), |
| 18294 | /* 50496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18295 | /* 50498 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18296 | /* 50500 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18297 | /* 50502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18298 | /* 50505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18299 | /* 50511 */ GIR_RootConstrainSelectedInstOperands, |
| 18300 | /* 50512 */ // GIR_Coverage, 144, |
| 18301 | /* 50512 */ GIR_EraseRootFromParent_Done, |
| 18302 | /* 50513 */ // Label 1480: @50513 |
| 18303 | /* 50513 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1481*/ GIMT_Encode4(50557), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 203 // |
| 18304 | /* 50520 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b), |
| 18305 | /* 50525 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18306 | /* 50528 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18307 | /* 50531 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18308 | /* 50534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18309 | /* 50538 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18310 | /* 50542 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18311 | /* 50546 */ // (intrinsic_wo_chain:{ *:[i32] } 3716:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32B:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18312 | /* 50546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32B), |
| 18313 | /* 50549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18314 | /* 50551 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18315 | /* 50553 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18316 | /* 50555 */ GIR_RootConstrainSelectedInstOperands, |
| 18317 | /* 50556 */ // GIR_Coverage, 203, |
| 18318 | /* 50556 */ GIR_EraseRootFromParent_Done, |
| 18319 | /* 50557 */ // Label 1481: @50557 |
| 18320 | /* 50557 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1482*/ GIMT_Encode4(50601), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 204 // |
| 18321 | /* 50564 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb), |
| 18322 | /* 50569 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18323 | /* 50572 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18324 | /* 50575 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18325 | /* 50578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18326 | /* 50582 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18327 | /* 50586 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18328 | /* 50590 */ // (intrinsic_wo_chain:{ *:[i32] } 3717:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18329 | /* 50590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CB), |
| 18330 | /* 50593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18331 | /* 50595 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18332 | /* 50597 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18333 | /* 50599 */ GIR_RootConstrainSelectedInstOperands, |
| 18334 | /* 50600 */ // GIR_Coverage, 204, |
| 18335 | /* 50600 */ GIR_EraseRootFromParent_Done, |
| 18336 | /* 50601 */ // Label 1482: @50601 |
| 18337 | /* 50601 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1483*/ GIMT_Encode4(50645), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 205 // |
| 18338 | /* 50608 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h), |
| 18339 | /* 50613 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18340 | /* 50616 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18341 | /* 50619 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18342 | /* 50622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18343 | /* 50626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18344 | /* 50630 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18345 | /* 50634 */ // (intrinsic_wo_chain:{ *:[i32] } 3720:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32H:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18346 | /* 50634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32H), |
| 18347 | /* 50637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18348 | /* 50639 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18349 | /* 50641 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18350 | /* 50643 */ GIR_RootConstrainSelectedInstOperands, |
| 18351 | /* 50644 */ // GIR_Coverage, 205, |
| 18352 | /* 50644 */ GIR_EraseRootFromParent_Done, |
| 18353 | /* 50645 */ // Label 1483: @50645 |
| 18354 | /* 50645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1484*/ GIMT_Encode4(50689), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 206 // |
| 18355 | /* 50652 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch), |
| 18356 | /* 50657 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18357 | /* 50660 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18358 | /* 50663 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18359 | /* 50666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18360 | /* 50670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18361 | /* 50674 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18362 | /* 50678 */ // (intrinsic_wo_chain:{ *:[i32] } 3718:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CH:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18363 | /* 50678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CH), |
| 18364 | /* 50681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18365 | /* 50683 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18366 | /* 50685 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18367 | /* 50687 */ GIR_RootConstrainSelectedInstOperands, |
| 18368 | /* 50688 */ // GIR_Coverage, 206, |
| 18369 | /* 50688 */ GIR_EraseRootFromParent_Done, |
| 18370 | /* 50689 */ // Label 1484: @50689 |
| 18371 | /* 50689 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1485*/ GIMT_Encode4(50733), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 207 // |
| 18372 | /* 50696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w), |
| 18373 | /* 50701 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18374 | /* 50704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18375 | /* 50707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18376 | /* 50710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18377 | /* 50714 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18378 | /* 50718 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18379 | /* 50722 */ // (intrinsic_wo_chain:{ *:[i32] } 3721:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32W:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18380 | /* 50722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32W), |
| 18381 | /* 50725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18382 | /* 50727 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18383 | /* 50729 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18384 | /* 50731 */ GIR_RootConstrainSelectedInstOperands, |
| 18385 | /* 50732 */ // GIR_Coverage, 207, |
| 18386 | /* 50732 */ GIR_EraseRootFromParent_Done, |
| 18387 | /* 50733 */ // Label 1485: @50733 |
| 18388 | /* 50733 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1486*/ GIMT_Encode4(50777), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 208 // |
| 18389 | /* 50740 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw), |
| 18390 | /* 50745 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18391 | /* 50748 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18392 | /* 50751 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18393 | /* 50754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18394 | /* 50758 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18395 | /* 50762 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18396 | /* 50766 */ // (intrinsic_wo_chain:{ *:[i32] } 3719:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CW:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18397 | /* 50766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CW), |
| 18398 | /* 50769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18399 | /* 50771 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18400 | /* 50773 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18401 | /* 50775 */ GIR_RootConstrainSelectedInstOperands, |
| 18402 | /* 50776 */ // GIR_Coverage, 208, |
| 18403 | /* 50776 */ GIR_EraseRootFromParent_Done, |
| 18404 | /* 50777 */ // Label 1486: @50777 |
| 18405 | /* 50777 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1487*/ GIMT_Encode4(50830), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 431 // |
| 18406 | /* 50784 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16), |
| 18407 | /* 50789 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18408 | /* 50792 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18409 | /* 50795 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18410 | /* 50798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18411 | /* 50802 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18412 | /* 50806 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18413 | /* 50810 */ // (intrinsic_wo_chain:{ *:[i32] } 4096:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18414 | /* 50810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD16), |
| 18415 | /* 50813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18416 | /* 50815 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18417 | /* 50817 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18418 | /* 50819 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18419 | /* 50822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18420 | /* 50828 */ GIR_RootConstrainSelectedInstOperands, |
| 18421 | /* 50829 */ // GIR_Coverage, 431, |
| 18422 | /* 50829 */ GIR_EraseRootFromParent_Done, |
| 18423 | /* 50830 */ // Label 1487: @50830 |
| 18424 | /* 50830 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1488*/ GIMT_Encode4(50883), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 432 // |
| 18425 | /* 50837 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8), |
| 18426 | /* 50842 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18427 | /* 50845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18428 | /* 50848 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18429 | /* 50851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18430 | /* 50855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18431 | /* 50859 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18432 | /* 50863 */ // (intrinsic_wo_chain:{ *:[i32] } 4097:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18433 | /* 50863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD8), |
| 18434 | /* 50866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18435 | /* 50868 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18436 | /* 50870 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18437 | /* 50872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18438 | /* 50875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18439 | /* 50881 */ GIR_RootConstrainSelectedInstOperands, |
| 18440 | /* 50882 */ // GIR_Coverage, 432, |
| 18441 | /* 50882 */ GIR_EraseRootFromParent_Done, |
| 18442 | /* 50883 */ // Label 1488: @50883 |
| 18443 | /* 50883 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1489*/ GIMT_Encode4(50936), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 433 // |
| 18444 | /* 50890 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx), |
| 18445 | /* 50895 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18446 | /* 50898 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18447 | /* 50901 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18448 | /* 50904 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18449 | /* 50908 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18450 | /* 50912 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18451 | /* 50916 */ // (intrinsic_wo_chain:{ *:[i32] } 4098:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18452 | /* 50916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QASX), |
| 18453 | /* 50919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18454 | /* 50921 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18455 | /* 50923 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18456 | /* 50925 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18457 | /* 50928 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18458 | /* 50934 */ GIR_RootConstrainSelectedInstOperands, |
| 18459 | /* 50935 */ // GIR_Coverage, 433, |
| 18460 | /* 50935 */ GIR_EraseRootFromParent_Done, |
| 18461 | /* 50936 */ // Label 1489: @50936 |
| 18462 | /* 50936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1490*/ GIMT_Encode4(50989), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 434 // |
| 18463 | /* 50943 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8), |
| 18464 | /* 50948 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18465 | /* 50951 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18466 | /* 50954 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18467 | /* 50957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18468 | /* 50961 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18469 | /* 50965 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18470 | /* 50969 */ // (intrinsic_wo_chain:{ *:[i32] } 4169:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18471 | /* 50969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB8), |
| 18472 | /* 50972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18473 | /* 50974 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18474 | /* 50976 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18475 | /* 50978 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18476 | /* 50981 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18477 | /* 50987 */ GIR_RootConstrainSelectedInstOperands, |
| 18478 | /* 50988 */ // GIR_Coverage, 434, |
| 18479 | /* 50988 */ GIR_EraseRootFromParent_Done, |
| 18480 | /* 50989 */ // Label 1490: @50989 |
| 18481 | /* 50989 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1491*/ GIMT_Encode4(51042), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 435 // |
| 18482 | /* 50996 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax), |
| 18483 | /* 51001 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18484 | /* 51004 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18485 | /* 51007 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18486 | /* 51010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18487 | /* 51014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18488 | /* 51018 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18489 | /* 51022 */ // (intrinsic_wo_chain:{ *:[i32] } 4099:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18490 | /* 51022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSAX), |
| 18491 | /* 51025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18492 | /* 51027 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18493 | /* 51029 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18494 | /* 51031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18495 | /* 51034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18496 | /* 51040 */ GIR_RootConstrainSelectedInstOperands, |
| 18497 | /* 51041 */ // GIR_Coverage, 435, |
| 18498 | /* 51041 */ GIR_EraseRootFromParent_Done, |
| 18499 | /* 51042 */ // Label 1491: @51042 |
| 18500 | /* 51042 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1492*/ GIMT_Encode4(51095), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 436 // |
| 18501 | /* 51049 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16), |
| 18502 | /* 51054 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18503 | /* 51057 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18504 | /* 51060 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18505 | /* 51063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18506 | /* 51067 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18507 | /* 51071 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18508 | /* 51075 */ // (intrinsic_wo_chain:{ *:[i32] } 4101:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18509 | /* 51075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB16), |
| 18510 | /* 51078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18511 | /* 51080 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18512 | /* 51082 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18513 | /* 51084 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18514 | /* 51087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18515 | /* 51093 */ GIR_RootConstrainSelectedInstOperands, |
| 18516 | /* 51094 */ // GIR_Coverage, 436, |
| 18517 | /* 51094 */ GIR_EraseRootFromParent_Done, |
| 18518 | /* 51095 */ // Label 1492: @51095 |
| 18519 | /* 51095 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1493*/ GIMT_Encode4(51148), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 437 // |
| 18520 | /* 51102 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8), |
| 18521 | /* 51107 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18522 | /* 51110 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18523 | /* 51113 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18524 | /* 51116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18525 | /* 51120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18526 | /* 51124 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18527 | /* 51128 */ // (intrinsic_wo_chain:{ *:[i32] } 4102:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18528 | /* 51128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB8), |
| 18529 | /* 51131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18530 | /* 51133 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18531 | /* 51135 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18532 | /* 51137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18533 | /* 51140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18534 | /* 51146 */ GIR_RootConstrainSelectedInstOperands, |
| 18535 | /* 51147 */ // GIR_Coverage, 437, |
| 18536 | /* 51147 */ GIR_EraseRootFromParent_Done, |
| 18537 | /* 51148 */ // Label 1493: @51148 |
| 18538 | /* 51148 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1494*/ GIMT_Encode4(51201), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 438 // |
| 18539 | /* 51155 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16), |
| 18540 | /* 51160 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18541 | /* 51163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18542 | /* 51166 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18543 | /* 51169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18544 | /* 51173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18545 | /* 51177 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18546 | /* 51181 */ // (intrinsic_wo_chain:{ *:[i32] } 4164:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18547 | /* 51181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD16), |
| 18548 | /* 51184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18549 | /* 51186 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18550 | /* 51188 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18551 | /* 51190 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18552 | /* 51193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18553 | /* 51199 */ GIR_RootConstrainSelectedInstOperands, |
| 18554 | /* 51200 */ // GIR_Coverage, 438, |
| 18555 | /* 51200 */ GIR_EraseRootFromParent_Done, |
| 18556 | /* 51201 */ // Label 1494: @51201 |
| 18557 | /* 51201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1495*/ GIMT_Encode4(51254), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 439 // |
| 18558 | /* 51208 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8), |
| 18559 | /* 51213 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18560 | /* 51216 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18561 | /* 51219 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18562 | /* 51222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18563 | /* 51226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18564 | /* 51230 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18565 | /* 51234 */ // (intrinsic_wo_chain:{ *:[i32] } 4165:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18566 | /* 51234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD8), |
| 18567 | /* 51237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18568 | /* 51239 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18569 | /* 51241 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18570 | /* 51243 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18571 | /* 51246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18572 | /* 51252 */ GIR_RootConstrainSelectedInstOperands, |
| 18573 | /* 51253 */ // GIR_Coverage, 439, |
| 18574 | /* 51253 */ GIR_EraseRootFromParent_Done, |
| 18575 | /* 51254 */ // Label 1495: @51254 |
| 18576 | /* 51254 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1496*/ GIMT_Encode4(51307), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 440 // |
| 18577 | /* 51261 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx), |
| 18578 | /* 51266 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18579 | /* 51269 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18580 | /* 51272 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18581 | /* 51275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18582 | /* 51279 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18583 | /* 51283 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18584 | /* 51287 */ // (intrinsic_wo_chain:{ *:[i32] } 4166:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18585 | /* 51287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQASX), |
| 18586 | /* 51290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18587 | /* 51292 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18588 | /* 51294 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18589 | /* 51296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18590 | /* 51299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18591 | /* 51305 */ GIR_RootConstrainSelectedInstOperands, |
| 18592 | /* 51306 */ // GIR_Coverage, 440, |
| 18593 | /* 51306 */ GIR_EraseRootFromParent_Done, |
| 18594 | /* 51307 */ // Label 1496: @51307 |
| 18595 | /* 51307 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1497*/ GIMT_Encode4(51360), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 441 // |
| 18596 | /* 51314 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax), |
| 18597 | /* 51319 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18598 | /* 51322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18599 | /* 51325 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18600 | /* 51328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18601 | /* 51332 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18602 | /* 51336 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18603 | /* 51340 */ // (intrinsic_wo_chain:{ *:[i32] } 4167:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18604 | /* 51340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSAX), |
| 18605 | /* 51343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18606 | /* 51345 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18607 | /* 51347 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18608 | /* 51349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18609 | /* 51352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18610 | /* 51358 */ GIR_RootConstrainSelectedInstOperands, |
| 18611 | /* 51359 */ // GIR_Coverage, 441, |
| 18612 | /* 51359 */ GIR_EraseRootFromParent_Done, |
| 18613 | /* 51360 */ // Label 1497: @51360 |
| 18614 | /* 51360 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1498*/ GIMT_Encode4(51413), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 442 // |
| 18615 | /* 51367 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16), |
| 18616 | /* 51372 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18617 | /* 51375 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18618 | /* 51378 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18619 | /* 51381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18620 | /* 51385 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18621 | /* 51389 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18622 | /* 51393 */ // (intrinsic_wo_chain:{ *:[i32] } 4168:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18623 | /* 51393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB16), |
| 18624 | /* 51396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18625 | /* 51398 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18626 | /* 51400 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18627 | /* 51402 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18628 | /* 51405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18629 | /* 51411 */ GIR_RootConstrainSelectedInstOperands, |
| 18630 | /* 51412 */ // GIR_Coverage, 442, |
| 18631 | /* 51412 */ GIR_EraseRootFromParent_Done, |
| 18632 | /* 51413 */ // Label 1498: @51413 |
| 18633 | /* 51413 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1499*/ GIMT_Encode4(51466), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 455 // |
| 18634 | /* 51420 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx), |
| 18635 | /* 51425 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18636 | /* 51428 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18637 | /* 51431 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18638 | /* 51434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18639 | /* 51438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18640 | /* 51442 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18641 | /* 51446 */ // (intrinsic_wo_chain:{ *:[i32] } 4110:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18642 | /* 51446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHASX), |
| 18643 | /* 51449 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18644 | /* 51451 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18645 | /* 51453 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18646 | /* 51455 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18647 | /* 51458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18648 | /* 51464 */ GIR_RootConstrainSelectedInstOperands, |
| 18649 | /* 51465 */ // GIR_Coverage, 455, |
| 18650 | /* 51465 */ GIR_EraseRootFromParent_Done, |
| 18651 | /* 51466 */ // Label 1499: @51466 |
| 18652 | /* 51466 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1500*/ GIMT_Encode4(51519), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 456 // |
| 18653 | /* 51473 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16), |
| 18654 | /* 51478 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18655 | /* 51481 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18656 | /* 51484 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18657 | /* 51487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18658 | /* 51491 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18659 | /* 51495 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18660 | /* 51499 */ // (intrinsic_wo_chain:{ *:[i32] } 4108:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18661 | /* 51499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD16), |
| 18662 | /* 51502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18663 | /* 51504 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18664 | /* 51506 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18665 | /* 51508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18666 | /* 51511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18667 | /* 51517 */ GIR_RootConstrainSelectedInstOperands, |
| 18668 | /* 51518 */ // GIR_Coverage, 456, |
| 18669 | /* 51518 */ GIR_EraseRootFromParent_Done, |
| 18670 | /* 51519 */ // Label 1500: @51519 |
| 18671 | /* 51519 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1501*/ GIMT_Encode4(51572), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 457 // |
| 18672 | /* 51526 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8), |
| 18673 | /* 51531 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18674 | /* 51534 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18675 | /* 51537 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18676 | /* 51540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18677 | /* 51544 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18678 | /* 51548 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18679 | /* 51552 */ // (intrinsic_wo_chain:{ *:[i32] } 4109:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18680 | /* 51552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD8), |
| 18681 | /* 51555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18682 | /* 51557 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18683 | /* 51559 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18684 | /* 51561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18685 | /* 51564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18686 | /* 51570 */ GIR_RootConstrainSelectedInstOperands, |
| 18687 | /* 51571 */ // GIR_Coverage, 457, |
| 18688 | /* 51571 */ GIR_EraseRootFromParent_Done, |
| 18689 | /* 51572 */ // Label 1501: @51572 |
| 18690 | /* 51572 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1502*/ GIMT_Encode4(51625), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 458 // |
| 18691 | /* 51579 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax), |
| 18692 | /* 51584 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18693 | /* 51587 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18694 | /* 51590 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18695 | /* 51593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18696 | /* 51597 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18697 | /* 51601 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18698 | /* 51605 */ // (intrinsic_wo_chain:{ *:[i32] } 4111:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18699 | /* 51605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSAX), |
| 18700 | /* 51608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18701 | /* 51610 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18702 | /* 51612 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18703 | /* 51614 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18704 | /* 51617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18705 | /* 51623 */ GIR_RootConstrainSelectedInstOperands, |
| 18706 | /* 51624 */ // GIR_Coverage, 458, |
| 18707 | /* 51624 */ GIR_EraseRootFromParent_Done, |
| 18708 | /* 51625 */ // Label 1502: @51625 |
| 18709 | /* 51625 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1503*/ GIMT_Encode4(51678), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 459 // |
| 18710 | /* 51632 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16), |
| 18711 | /* 51637 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18712 | /* 51640 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18713 | /* 51643 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18714 | /* 51646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18715 | /* 51650 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18716 | /* 51654 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18717 | /* 51658 */ // (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18718 | /* 51658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB16), |
| 18719 | /* 51661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18720 | /* 51663 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18721 | /* 51665 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18722 | /* 51667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18723 | /* 51670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18724 | /* 51676 */ GIR_RootConstrainSelectedInstOperands, |
| 18725 | /* 51677 */ // GIR_Coverage, 459, |
| 18726 | /* 51677 */ GIR_EraseRootFromParent_Done, |
| 18727 | /* 51678 */ // Label 1503: @51678 |
| 18728 | /* 51678 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1504*/ GIMT_Encode4(51731), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 460 // |
| 18729 | /* 51685 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8), |
| 18730 | /* 51690 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18731 | /* 51693 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18732 | /* 51696 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18733 | /* 51699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18734 | /* 51703 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18735 | /* 51707 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18736 | /* 51711 */ // (intrinsic_wo_chain:{ *:[i32] } 4113:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18737 | /* 51711 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB8), |
| 18738 | /* 51714 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18739 | /* 51716 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18740 | /* 51718 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18741 | /* 51720 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18742 | /* 51723 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18743 | /* 51729 */ GIR_RootConstrainSelectedInstOperands, |
| 18744 | /* 51730 */ // GIR_Coverage, 460, |
| 18745 | /* 51730 */ GIR_EraseRootFromParent_Done, |
| 18746 | /* 51731 */ // Label 1504: @51731 |
| 18747 | /* 51731 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1505*/ GIMT_Encode4(51784), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 461 // |
| 18748 | /* 51738 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx), |
| 18749 | /* 51743 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18750 | /* 51746 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18751 | /* 51749 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18752 | /* 51752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18753 | /* 51756 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18754 | /* 51760 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18755 | /* 51764 */ // (intrinsic_wo_chain:{ *:[i32] } 4159:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18756 | /* 51764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHASX), |
| 18757 | /* 51767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18758 | /* 51769 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18759 | /* 51771 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18760 | /* 51773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18761 | /* 51776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18762 | /* 51782 */ GIR_RootConstrainSelectedInstOperands, |
| 18763 | /* 51783 */ // GIR_Coverage, 461, |
| 18764 | /* 51783 */ GIR_EraseRootFromParent_Done, |
| 18765 | /* 51784 */ // Label 1505: @51784 |
| 18766 | /* 51784 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1506*/ GIMT_Encode4(51837), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 462 // |
| 18767 | /* 51791 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16), |
| 18768 | /* 51796 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18769 | /* 51799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18770 | /* 51802 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18771 | /* 51805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18772 | /* 51809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18773 | /* 51813 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18774 | /* 51817 */ // (intrinsic_wo_chain:{ *:[i32] } 4157:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18775 | /* 51817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD16), |
| 18776 | /* 51820 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18777 | /* 51822 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18778 | /* 51824 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18779 | /* 51826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18780 | /* 51829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18781 | /* 51835 */ GIR_RootConstrainSelectedInstOperands, |
| 18782 | /* 51836 */ // GIR_Coverage, 462, |
| 18783 | /* 51836 */ GIR_EraseRootFromParent_Done, |
| 18784 | /* 51837 */ // Label 1506: @51837 |
| 18785 | /* 51837 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1507*/ GIMT_Encode4(51890), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 463 // |
| 18786 | /* 51844 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8), |
| 18787 | /* 51849 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18788 | /* 51852 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18789 | /* 51855 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18790 | /* 51858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18791 | /* 51862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18792 | /* 51866 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18793 | /* 51870 */ // (intrinsic_wo_chain:{ *:[i32] } 4158:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18794 | /* 51870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD8), |
| 18795 | /* 51873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18796 | /* 51875 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18797 | /* 51877 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18798 | /* 51879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18799 | /* 51882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18800 | /* 51888 */ GIR_RootConstrainSelectedInstOperands, |
| 18801 | /* 51889 */ // GIR_Coverage, 463, |
| 18802 | /* 51889 */ GIR_EraseRootFromParent_Done, |
| 18803 | /* 51890 */ // Label 1507: @51890 |
| 18804 | /* 51890 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1508*/ GIMT_Encode4(51943), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 464 // |
| 18805 | /* 51897 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax), |
| 18806 | /* 51902 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18807 | /* 51905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18808 | /* 51908 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18809 | /* 51911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18810 | /* 51915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18811 | /* 51919 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18812 | /* 51923 */ // (intrinsic_wo_chain:{ *:[i32] } 4160:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18813 | /* 51923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSAX), |
| 18814 | /* 51926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18815 | /* 51928 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18816 | /* 51930 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18817 | /* 51932 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18818 | /* 51935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18819 | /* 51941 */ GIR_RootConstrainSelectedInstOperands, |
| 18820 | /* 51942 */ // GIR_Coverage, 464, |
| 18821 | /* 51942 */ GIR_EraseRootFromParent_Done, |
| 18822 | /* 51943 */ // Label 1508: @51943 |
| 18823 | /* 51943 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1509*/ GIMT_Encode4(51996), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 465 // |
| 18824 | /* 51950 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16), |
| 18825 | /* 51955 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18826 | /* 51958 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18827 | /* 51961 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18828 | /* 51964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18829 | /* 51968 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18830 | /* 51972 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18831 | /* 51976 */ // (intrinsic_wo_chain:{ *:[i32] } 4161:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18832 | /* 51976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB16), |
| 18833 | /* 51979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18834 | /* 51981 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18835 | /* 51983 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18836 | /* 51985 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18837 | /* 51988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18838 | /* 51994 */ GIR_RootConstrainSelectedInstOperands, |
| 18839 | /* 51995 */ // GIR_Coverage, 465, |
| 18840 | /* 51995 */ GIR_EraseRootFromParent_Done, |
| 18841 | /* 51996 */ // Label 1509: @51996 |
| 18842 | /* 51996 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1510*/ GIMT_Encode4(52049), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 466 // |
| 18843 | /* 52003 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8), |
| 18844 | /* 52008 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18845 | /* 52011 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18846 | /* 52014 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18847 | /* 52017 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18848 | /* 52021 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18849 | /* 52025 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18850 | /* 52029 */ // (intrinsic_wo_chain:{ *:[i32] } 4162:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18851 | /* 52029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB8), |
| 18852 | /* 52032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18853 | /* 52034 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18854 | /* 52036 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18855 | /* 52038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18856 | /* 52041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18857 | /* 52047 */ GIR_RootConstrainSelectedInstOperands, |
| 18858 | /* 52048 */ // GIR_Coverage, 466, |
| 18859 | /* 52048 */ GIR_EraseRootFromParent_Done, |
| 18860 | /* 52049 */ // Label 1510: @52049 |
| 18861 | /* 52049 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1511*/ GIMT_Encode4(52102), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 467 // |
| 18862 | /* 52056 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8), |
| 18863 | /* 52061 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18864 | /* 52064 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18865 | /* 52067 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18866 | /* 52070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18867 | /* 52074 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18868 | /* 52078 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18869 | /* 52082 */ // (intrinsic_wo_chain:{ *:[i32] } 4170:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18870 | /* 52082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAD8), |
| 18871 | /* 52085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18872 | /* 52087 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18873 | /* 52089 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18874 | /* 52091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18875 | /* 52094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18876 | /* 52100 */ GIR_RootConstrainSelectedInstOperands, |
| 18877 | /* 52101 */ // GIR_Coverage, 467, |
| 18878 | /* 52101 */ GIR_EraseRootFromParent_Done, |
| 18879 | /* 52102 */ // Label 1511: @52102 |
| 18880 | /* 52102 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1512*/ GIMT_Encode4(52155), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 523 // |
| 18881 | /* 52109 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad), |
| 18882 | /* 52114 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18883 | /* 52117 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18884 | /* 52120 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18885 | /* 52123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18886 | /* 52127 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18887 | /* 52131 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18888 | /* 52135 */ // (intrinsic_wo_chain:{ *:[i32] } 4128:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18889 | /* 52135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUAD), |
| 18890 | /* 52138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18891 | /* 52140 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18892 | /* 52142 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18893 | /* 52144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18894 | /* 52147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18895 | /* 52153 */ GIR_RootConstrainSelectedInstOperands, |
| 18896 | /* 52154 */ // GIR_Coverage, 523, |
| 18897 | /* 52154 */ GIR_EraseRootFromParent_Done, |
| 18898 | /* 52155 */ // Label 1512: @52155 |
| 18899 | /* 52155 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1513*/ GIMT_Encode4(52208), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 524 // |
| 18900 | /* 52162 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx), |
| 18901 | /* 52167 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18902 | /* 52170 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18903 | /* 52173 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18904 | /* 52176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18905 | /* 52180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18906 | /* 52184 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18907 | /* 52188 */ // (intrinsic_wo_chain:{ *:[i32] } 4129:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18908 | /* 52188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUADX), |
| 18909 | /* 52191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18910 | /* 52193 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18911 | /* 52195 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18912 | /* 52197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18913 | /* 52200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18914 | /* 52206 */ GIR_RootConstrainSelectedInstOperands, |
| 18915 | /* 52207 */ // GIR_Coverage, 524, |
| 18916 | /* 52207 */ GIR_EraseRootFromParent_Done, |
| 18917 | /* 52208 */ // Label 1513: @52208 |
| 18918 | /* 52208 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1514*/ GIMT_Encode4(52261), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 525 // |
| 18919 | /* 52215 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd), |
| 18920 | /* 52220 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18921 | /* 52223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18922 | /* 52226 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18923 | /* 52229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18924 | /* 52233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18925 | /* 52237 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18926 | /* 52241 */ // (intrinsic_wo_chain:{ *:[i32] } 4136:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18927 | /* 52241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSD), |
| 18928 | /* 52244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18929 | /* 52246 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18930 | /* 52248 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18931 | /* 52250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18932 | /* 52253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18933 | /* 52259 */ GIR_RootConstrainSelectedInstOperands, |
| 18934 | /* 52260 */ // GIR_Coverage, 525, |
| 18935 | /* 52260 */ GIR_EraseRootFromParent_Done, |
| 18936 | /* 52261 */ // Label 1514: @52261 |
| 18937 | /* 52261 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1515*/ GIMT_Encode4(52314), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 526 // |
| 18938 | /* 52268 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx), |
| 18939 | /* 52273 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18940 | /* 52276 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18941 | /* 52279 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18942 | /* 52282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18943 | /* 52286 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18944 | /* 52290 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18945 | /* 52294 */ // (intrinsic_wo_chain:{ *:[i32] } 4137:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18946 | /* 52294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSDX), |
| 18947 | /* 52297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18948 | /* 52299 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18949 | /* 52301 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18950 | /* 52303 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18951 | /* 52306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18952 | /* 52312 */ GIR_RootConstrainSelectedInstOperands, |
| 18953 | /* 52313 */ // GIR_Coverage, 526, |
| 18954 | /* 52313 */ GIR_EraseRootFromParent_Done, |
| 18955 | /* 52314 */ // Label 1515: @52314 |
| 18956 | /* 52314 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1516*/ GIMT_Encode4(52358), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 540 // |
| 18957 | /* 52321 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b), |
| 18958 | /* 52326 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18959 | /* 52329 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18960 | /* 52332 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18961 | /* 52335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18962 | /* 52339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18963 | /* 52343 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18964 | /* 52347 */ // (intrinsic_wo_chain:{ *:[i32] } 3716:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32B:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18965 | /* 52347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32B), |
| 18966 | /* 52350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18967 | /* 52352 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18968 | /* 52354 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18969 | /* 52356 */ GIR_RootConstrainSelectedInstOperands, |
| 18970 | /* 52357 */ // GIR_Coverage, 540, |
| 18971 | /* 52357 */ GIR_EraseRootFromParent_Done, |
| 18972 | /* 52358 */ // Label 1516: @52358 |
| 18973 | /* 52358 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1517*/ GIMT_Encode4(52402), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 541 // |
| 18974 | /* 52365 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb), |
| 18975 | /* 52370 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18976 | /* 52373 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18977 | /* 52376 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18978 | /* 52379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18979 | /* 52383 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18980 | /* 52387 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18981 | /* 52391 */ // (intrinsic_wo_chain:{ *:[i32] } 3717:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18982 | /* 52391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CB), |
| 18983 | /* 52394 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18984 | /* 52396 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18985 | /* 52398 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18986 | /* 52400 */ GIR_RootConstrainSelectedInstOperands, |
| 18987 | /* 52401 */ // GIR_Coverage, 541, |
| 18988 | /* 52401 */ GIR_EraseRootFromParent_Done, |
| 18989 | /* 52402 */ // Label 1517: @52402 |
| 18990 | /* 52402 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1518*/ GIMT_Encode4(52446), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 542 // |
| 18991 | /* 52409 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h), |
| 18992 | /* 52414 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18993 | /* 52417 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18994 | /* 52420 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18995 | /* 52423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18996 | /* 52427 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18997 | /* 52431 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18998 | /* 52435 */ // (intrinsic_wo_chain:{ *:[i32] } 3720:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32H:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18999 | /* 52435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32H), |
| 19000 | /* 52438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19001 | /* 52440 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19002 | /* 52442 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19003 | /* 52444 */ GIR_RootConstrainSelectedInstOperands, |
| 19004 | /* 52445 */ // GIR_Coverage, 542, |
| 19005 | /* 52445 */ GIR_EraseRootFromParent_Done, |
| 19006 | /* 52446 */ // Label 1518: @52446 |
| 19007 | /* 52446 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1519*/ GIMT_Encode4(52490), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 543 // |
| 19008 | /* 52453 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch), |
| 19009 | /* 52458 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19010 | /* 52461 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19011 | /* 52464 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19012 | /* 52467 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19013 | /* 52471 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19014 | /* 52475 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19015 | /* 52479 */ // (intrinsic_wo_chain:{ *:[i32] } 3718:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19016 | /* 52479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CH), |
| 19017 | /* 52482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19018 | /* 52484 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19019 | /* 52486 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19020 | /* 52488 */ GIR_RootConstrainSelectedInstOperands, |
| 19021 | /* 52489 */ // GIR_Coverage, 543, |
| 19022 | /* 52489 */ GIR_EraseRootFromParent_Done, |
| 19023 | /* 52490 */ // Label 1519: @52490 |
| 19024 | /* 52490 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1520*/ GIMT_Encode4(52534), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 544 // |
| 19025 | /* 52497 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w), |
| 19026 | /* 52502 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19027 | /* 52505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19028 | /* 52508 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19029 | /* 52511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19030 | /* 52515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19031 | /* 52519 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19032 | /* 52523 */ // (intrinsic_wo_chain:{ *:[i32] } 3721:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32W:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19033 | /* 52523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32W), |
| 19034 | /* 52526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19035 | /* 52528 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19036 | /* 52530 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19037 | /* 52532 */ GIR_RootConstrainSelectedInstOperands, |
| 19038 | /* 52533 */ // GIR_Coverage, 544, |
| 19039 | /* 52533 */ GIR_EraseRootFromParent_Done, |
| 19040 | /* 52534 */ // Label 1520: @52534 |
| 19041 | /* 52534 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1521*/ GIMT_Encode4(52578), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 545 // |
| 19042 | /* 52541 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw), |
| 19043 | /* 52546 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19044 | /* 52549 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19045 | /* 52552 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19046 | /* 52555 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19047 | /* 52559 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19048 | /* 52563 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19049 | /* 52567 */ // (intrinsic_wo_chain:{ *:[i32] } 3719:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CW:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19050 | /* 52567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CW), |
| 19051 | /* 52570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19052 | /* 52572 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19053 | /* 52574 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19054 | /* 52576 */ GIR_RootConstrainSelectedInstOperands, |
| 19055 | /* 52577 */ // GIR_Coverage, 545, |
| 19056 | /* 52577 */ GIR_EraseRootFromParent_Done, |
| 19057 | /* 52578 */ // Label 1521: @52578 |
| 19058 | /* 52578 */ GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(52900), |
| 19059 | /* 52583 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 19060 | /* 52588 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1529*/ GIMT_Encode4(52899), |
| 19061 | /* 52599 */ /*GILLT_v8s8*//*Label 1523*/ GIMT_Encode4(52623), |
| 19062 | /* 52603 */ /*GILLT_v16s8*//*Label 1524*/ GIMT_Encode4(52669), |
| 19063 | /* 52607 */ /*GILLT_v4s16*//*Label 1525*/ GIMT_Encode4(52715), |
| 19064 | /* 52611 */ /*GILLT_v8s16*//*Label 1526*/ GIMT_Encode4(52761), |
| 19065 | /* 52615 */ /*GILLT_v2s32*//*Label 1527*/ GIMT_Encode4(52807), |
| 19066 | /* 52619 */ /*GILLT_v4s32*//*Label 1528*/ GIMT_Encode4(52853), |
| 19067 | /* 52623 */ // Label 1523: @52623 |
| 19068 | /* 52623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1530*/ GIMT_Encode4(52668), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 916 // |
| 19069 | /* 52630 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19070 | /* 52633 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19071 | /* 52636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19072 | /* 52640 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19073 | /* 52644 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19074 | /* 52648 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4006:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19075 | /* 52648 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i8), |
| 19076 | /* 52651 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19077 | /* 52653 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19078 | /* 52655 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19079 | /* 52657 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19080 | /* 52660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19081 | /* 52666 */ GIR_RootConstrainSelectedInstOperands, |
| 19082 | /* 52667 */ // GIR_Coverage, 916, |
| 19083 | /* 52667 */ GIR_EraseRootFromParent_Done, |
| 19084 | /* 52668 */ // Label 1530: @52668 |
| 19085 | /* 52668 */ GIM_Reject, |
| 19086 | /* 52669 */ // Label 1524: @52669 |
| 19087 | /* 52669 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1531*/ GIMT_Encode4(52714), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 917 // |
| 19088 | /* 52676 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19089 | /* 52679 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19090 | /* 52682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19091 | /* 52686 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19092 | /* 52690 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19093 | /* 52694 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4006:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 19094 | /* 52694 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv16i8), |
| 19095 | /* 52697 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19096 | /* 52699 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19097 | /* 52701 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19098 | /* 52703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19099 | /* 52706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19100 | /* 52712 */ GIR_RootConstrainSelectedInstOperands, |
| 19101 | /* 52713 */ // GIR_Coverage, 917, |
| 19102 | /* 52713 */ GIR_EraseRootFromParent_Done, |
| 19103 | /* 52714 */ // Label 1531: @52714 |
| 19104 | /* 52714 */ GIM_Reject, |
| 19105 | /* 52715 */ // Label 1525: @52715 |
| 19106 | /* 52715 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1532*/ GIMT_Encode4(52760), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 912 // |
| 19107 | /* 52722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19108 | /* 52725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19109 | /* 52728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19110 | /* 52732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19111 | /* 52736 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19112 | /* 52740 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4006:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19113 | /* 52740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i16), |
| 19114 | /* 52743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19115 | /* 52745 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19116 | /* 52747 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19117 | /* 52749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19118 | /* 52752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19119 | /* 52758 */ GIR_RootConstrainSelectedInstOperands, |
| 19120 | /* 52759 */ // GIR_Coverage, 912, |
| 19121 | /* 52759 */ GIR_EraseRootFromParent_Done, |
| 19122 | /* 52760 */ // Label 1532: @52760 |
| 19123 | /* 52760 */ GIM_Reject, |
| 19124 | /* 52761 */ // Label 1526: @52761 |
| 19125 | /* 52761 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1533*/ GIMT_Encode4(52806), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 914 // |
| 19126 | /* 52768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19127 | /* 52771 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19128 | /* 52774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19129 | /* 52778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19130 | /* 52782 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19131 | /* 52786 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4006:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19132 | /* 52786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i16), |
| 19133 | /* 52789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19134 | /* 52791 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19135 | /* 52793 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19136 | /* 52795 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19137 | /* 52798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19138 | /* 52804 */ GIR_RootConstrainSelectedInstOperands, |
| 19139 | /* 52805 */ // GIR_Coverage, 914, |
| 19140 | /* 52805 */ GIR_EraseRootFromParent_Done, |
| 19141 | /* 52806 */ // Label 1533: @52806 |
| 19142 | /* 52806 */ GIM_Reject, |
| 19143 | /* 52807 */ // Label 1527: @52807 |
| 19144 | /* 52807 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1534*/ GIMT_Encode4(52852), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 913 // |
| 19145 | /* 52814 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19146 | /* 52817 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19147 | /* 52820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19148 | /* 52824 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19149 | /* 52828 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19150 | /* 52832 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4006:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19151 | /* 52832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv2i32), |
| 19152 | /* 52835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19153 | /* 52837 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19154 | /* 52839 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19155 | /* 52841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19156 | /* 52844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19157 | /* 52850 */ GIR_RootConstrainSelectedInstOperands, |
| 19158 | /* 52851 */ // GIR_Coverage, 913, |
| 19159 | /* 52851 */ GIR_EraseRootFromParent_Done, |
| 19160 | /* 52852 */ // Label 1534: @52852 |
| 19161 | /* 52852 */ GIM_Reject, |
| 19162 | /* 52853 */ // Label 1528: @52853 |
| 19163 | /* 52853 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1535*/ GIMT_Encode4(52898), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 915 // |
| 19164 | /* 52860 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19165 | /* 52863 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19166 | /* 52866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19167 | /* 52870 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19168 | /* 52874 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19169 | /* 52878 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4006:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19170 | /* 52878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i32), |
| 19171 | /* 52881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19172 | /* 52883 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19173 | /* 52885 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19174 | /* 52887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19175 | /* 52890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19176 | /* 52896 */ GIR_RootConstrainSelectedInstOperands, |
| 19177 | /* 52897 */ // GIR_Coverage, 915, |
| 19178 | /* 52897 */ GIR_EraseRootFromParent_Done, |
| 19179 | /* 52898 */ // Label 1535: @52898 |
| 19180 | /* 52898 */ GIM_Reject, |
| 19181 | /* 52899 */ // Label 1529: @52899 |
| 19182 | /* 52899 */ GIM_Reject, |
| 19183 | /* 52900 */ // Label 1522: @52900 |
| 19184 | /* 52900 */ GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(53222), |
| 19185 | /* 52905 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 19186 | /* 52910 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1543*/ GIMT_Encode4(53221), |
| 19187 | /* 52921 */ /*GILLT_v8s8*//*Label 1537*/ GIMT_Encode4(52945), |
| 19188 | /* 52925 */ /*GILLT_v16s8*//*Label 1538*/ GIMT_Encode4(52991), |
| 19189 | /* 52929 */ /*GILLT_v4s16*//*Label 1539*/ GIMT_Encode4(53037), |
| 19190 | /* 52933 */ /*GILLT_v8s16*//*Label 1540*/ GIMT_Encode4(53083), |
| 19191 | /* 52937 */ /*GILLT_v2s32*//*Label 1541*/ GIMT_Encode4(53129), |
| 19192 | /* 52941 */ /*GILLT_v4s32*//*Label 1542*/ GIMT_Encode4(53175), |
| 19193 | /* 52945 */ // Label 1537: @52945 |
| 19194 | /* 52945 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1544*/ GIMT_Encode4(52990), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 922 // |
| 19195 | /* 52952 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19196 | /* 52955 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19197 | /* 52958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19198 | /* 52962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19199 | /* 52966 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19200 | /* 52970 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4007:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19201 | /* 52970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i8), |
| 19202 | /* 52973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19203 | /* 52975 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19204 | /* 52977 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19205 | /* 52979 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19206 | /* 52982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19207 | /* 52988 */ GIR_RootConstrainSelectedInstOperands, |
| 19208 | /* 52989 */ // GIR_Coverage, 922, |
| 19209 | /* 52989 */ GIR_EraseRootFromParent_Done, |
| 19210 | /* 52990 */ // Label 1544: @52990 |
| 19211 | /* 52990 */ GIM_Reject, |
| 19212 | /* 52991 */ // Label 1538: @52991 |
| 19213 | /* 52991 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1545*/ GIMT_Encode4(53036), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 923 // |
| 19214 | /* 52998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19215 | /* 53001 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19216 | /* 53004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19217 | /* 53008 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19218 | /* 53012 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19219 | /* 53016 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4007:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 19220 | /* 53016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv16i8), |
| 19221 | /* 53019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19222 | /* 53021 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19223 | /* 53023 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19224 | /* 53025 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19225 | /* 53028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19226 | /* 53034 */ GIR_RootConstrainSelectedInstOperands, |
| 19227 | /* 53035 */ // GIR_Coverage, 923, |
| 19228 | /* 53035 */ GIR_EraseRootFromParent_Done, |
| 19229 | /* 53036 */ // Label 1545: @53036 |
| 19230 | /* 53036 */ GIM_Reject, |
| 19231 | /* 53037 */ // Label 1539: @53037 |
| 19232 | /* 53037 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1546*/ GIMT_Encode4(53082), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 918 // |
| 19233 | /* 53044 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19234 | /* 53047 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19235 | /* 53050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19236 | /* 53054 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19237 | /* 53058 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19238 | /* 53062 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4007:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19239 | /* 53062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i16), |
| 19240 | /* 53065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19241 | /* 53067 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19242 | /* 53069 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19243 | /* 53071 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19244 | /* 53074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19245 | /* 53080 */ GIR_RootConstrainSelectedInstOperands, |
| 19246 | /* 53081 */ // GIR_Coverage, 918, |
| 19247 | /* 53081 */ GIR_EraseRootFromParent_Done, |
| 19248 | /* 53082 */ // Label 1546: @53082 |
| 19249 | /* 53082 */ GIM_Reject, |
| 19250 | /* 53083 */ // Label 1540: @53083 |
| 19251 | /* 53083 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1547*/ GIMT_Encode4(53128), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 920 // |
| 19252 | /* 53090 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19253 | /* 53093 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19254 | /* 53096 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19255 | /* 53100 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19256 | /* 53104 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19257 | /* 53108 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4007:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19258 | /* 53108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i16), |
| 19259 | /* 53111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19260 | /* 53113 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19261 | /* 53115 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19262 | /* 53117 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19263 | /* 53120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19264 | /* 53126 */ GIR_RootConstrainSelectedInstOperands, |
| 19265 | /* 53127 */ // GIR_Coverage, 920, |
| 19266 | /* 53127 */ GIR_EraseRootFromParent_Done, |
| 19267 | /* 53128 */ // Label 1547: @53128 |
| 19268 | /* 53128 */ GIM_Reject, |
| 19269 | /* 53129 */ // Label 1541: @53129 |
| 19270 | /* 53129 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1548*/ GIMT_Encode4(53174), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 919 // |
| 19271 | /* 53136 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19272 | /* 53139 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19273 | /* 53142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19274 | /* 53146 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19275 | /* 53150 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19276 | /* 53154 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4007:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19277 | /* 53154 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv2i32), |
| 19278 | /* 53157 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19279 | /* 53159 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19280 | /* 53161 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19281 | /* 53163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19282 | /* 53166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19283 | /* 53172 */ GIR_RootConstrainSelectedInstOperands, |
| 19284 | /* 53173 */ // GIR_Coverage, 919, |
| 19285 | /* 53173 */ GIR_EraseRootFromParent_Done, |
| 19286 | /* 53174 */ // Label 1548: @53174 |
| 19287 | /* 53174 */ GIM_Reject, |
| 19288 | /* 53175 */ // Label 1542: @53175 |
| 19289 | /* 53175 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1549*/ GIMT_Encode4(53220), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 921 // |
| 19290 | /* 53182 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19291 | /* 53185 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19292 | /* 53188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19293 | /* 53192 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19294 | /* 53196 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19295 | /* 53200 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4007:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19296 | /* 53200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i32), |
| 19297 | /* 53203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19298 | /* 53205 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19299 | /* 53207 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19300 | /* 53209 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19301 | /* 53212 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19302 | /* 53218 */ GIR_RootConstrainSelectedInstOperands, |
| 19303 | /* 53219 */ // GIR_Coverage, 921, |
| 19304 | /* 53219 */ GIR_EraseRootFromParent_Done, |
| 19305 | /* 53220 */ // Label 1549: @53220 |
| 19306 | /* 53220 */ GIM_Reject, |
| 19307 | /* 53221 */ // Label 1543: @53221 |
| 19308 | /* 53221 */ GIM_Reject, |
| 19309 | /* 53222 */ // Label 1536: @53222 |
| 19310 | /* 53222 */ GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(53544), |
| 19311 | /* 53227 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 19312 | /* 53232 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1557*/ GIMT_Encode4(53543), |
| 19313 | /* 53243 */ /*GILLT_v8s8*//*Label 1551*/ GIMT_Encode4(53267), |
| 19314 | /* 53247 */ /*GILLT_v16s8*//*Label 1552*/ GIMT_Encode4(53313), |
| 19315 | /* 53251 */ /*GILLT_v4s16*//*Label 1553*/ GIMT_Encode4(53359), |
| 19316 | /* 53255 */ /*GILLT_v8s16*//*Label 1554*/ GIMT_Encode4(53405), |
| 19317 | /* 53259 */ /*GILLT_v2s32*//*Label 1555*/ GIMT_Encode4(53451), |
| 19318 | /* 53263 */ /*GILLT_v4s32*//*Label 1556*/ GIMT_Encode4(53497), |
| 19319 | /* 53267 */ // Label 1551: @53267 |
| 19320 | /* 53267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1558*/ GIMT_Encode4(53312), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 928 // |
| 19321 | /* 53274 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19322 | /* 53277 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19323 | /* 53280 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19324 | /* 53284 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19325 | /* 53288 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19326 | /* 53292 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4066:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19327 | /* 53292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i8), |
| 19328 | /* 53295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19329 | /* 53297 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19330 | /* 53299 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19331 | /* 53301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19332 | /* 53304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19333 | /* 53310 */ GIR_RootConstrainSelectedInstOperands, |
| 19334 | /* 53311 */ // GIR_Coverage, 928, |
| 19335 | /* 53311 */ GIR_EraseRootFromParent_Done, |
| 19336 | /* 53312 */ // Label 1558: @53312 |
| 19337 | /* 53312 */ GIM_Reject, |
| 19338 | /* 53313 */ // Label 1552: @53313 |
| 19339 | /* 53313 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1559*/ GIMT_Encode4(53358), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 929 // |
| 19340 | /* 53320 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19341 | /* 53323 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19342 | /* 53326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19343 | /* 53330 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19344 | /* 53334 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19345 | /* 53338 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4066:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 19346 | /* 53338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv16i8), |
| 19347 | /* 53341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19348 | /* 53343 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19349 | /* 53345 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19350 | /* 53347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19351 | /* 53350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19352 | /* 53356 */ GIR_RootConstrainSelectedInstOperands, |
| 19353 | /* 53357 */ // GIR_Coverage, 929, |
| 19354 | /* 53357 */ GIR_EraseRootFromParent_Done, |
| 19355 | /* 53358 */ // Label 1559: @53358 |
| 19356 | /* 53358 */ GIM_Reject, |
| 19357 | /* 53359 */ // Label 1553: @53359 |
| 19358 | /* 53359 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1560*/ GIMT_Encode4(53404), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 924 // |
| 19359 | /* 53366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19360 | /* 53369 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19361 | /* 53372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19362 | /* 53376 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19363 | /* 53380 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19364 | /* 53384 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4066:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19365 | /* 53384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i16), |
| 19366 | /* 53387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19367 | /* 53389 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19368 | /* 53391 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19369 | /* 53393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19370 | /* 53396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19371 | /* 53402 */ GIR_RootConstrainSelectedInstOperands, |
| 19372 | /* 53403 */ // GIR_Coverage, 924, |
| 19373 | /* 53403 */ GIR_EraseRootFromParent_Done, |
| 19374 | /* 53404 */ // Label 1560: @53404 |
| 19375 | /* 53404 */ GIM_Reject, |
| 19376 | /* 53405 */ // Label 1554: @53405 |
| 19377 | /* 53405 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1561*/ GIMT_Encode4(53450), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 926 // |
| 19378 | /* 53412 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19379 | /* 53415 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19380 | /* 53418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19381 | /* 53422 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19382 | /* 53426 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19383 | /* 53430 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4066:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19384 | /* 53430 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i16), |
| 19385 | /* 53433 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19386 | /* 53435 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19387 | /* 53437 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19388 | /* 53439 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19389 | /* 53442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19390 | /* 53448 */ GIR_RootConstrainSelectedInstOperands, |
| 19391 | /* 53449 */ // GIR_Coverage, 926, |
| 19392 | /* 53449 */ GIR_EraseRootFromParent_Done, |
| 19393 | /* 53450 */ // Label 1561: @53450 |
| 19394 | /* 53450 */ GIM_Reject, |
| 19395 | /* 53451 */ // Label 1555: @53451 |
| 19396 | /* 53451 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1562*/ GIMT_Encode4(53496), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 925 // |
| 19397 | /* 53458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19398 | /* 53461 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19399 | /* 53464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19400 | /* 53468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19401 | /* 53472 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19402 | /* 53476 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4066:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19403 | /* 53476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv2i32), |
| 19404 | /* 53479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19405 | /* 53481 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19406 | /* 53483 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19407 | /* 53485 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19408 | /* 53488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19409 | /* 53494 */ GIR_RootConstrainSelectedInstOperands, |
| 19410 | /* 53495 */ // GIR_Coverage, 925, |
| 19411 | /* 53495 */ GIR_EraseRootFromParent_Done, |
| 19412 | /* 53496 */ // Label 1562: @53496 |
| 19413 | /* 53496 */ GIM_Reject, |
| 19414 | /* 53497 */ // Label 1556: @53497 |
| 19415 | /* 53497 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1563*/ GIMT_Encode4(53542), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 927 // |
| 19416 | /* 53504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19417 | /* 53507 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19418 | /* 53510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19419 | /* 53514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19420 | /* 53518 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19421 | /* 53522 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4066:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19422 | /* 53522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i32), |
| 19423 | /* 53525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19424 | /* 53527 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19425 | /* 53529 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19426 | /* 53531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19427 | /* 53534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19428 | /* 53540 */ GIR_RootConstrainSelectedInstOperands, |
| 19429 | /* 53541 */ // GIR_Coverage, 927, |
| 19430 | /* 53541 */ GIR_EraseRootFromParent_Done, |
| 19431 | /* 53542 */ // Label 1563: @53542 |
| 19432 | /* 53542 */ GIM_Reject, |
| 19433 | /* 53543 */ // Label 1557: @53543 |
| 19434 | /* 53543 */ GIM_Reject, |
| 19435 | /* 53544 */ // Label 1550: @53544 |
| 19436 | /* 53544 */ GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(53866), |
| 19437 | /* 53549 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 19438 | /* 53554 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1571*/ GIMT_Encode4(53865), |
| 19439 | /* 53565 */ /*GILLT_v8s8*//*Label 1565*/ GIMT_Encode4(53589), |
| 19440 | /* 53569 */ /*GILLT_v16s8*//*Label 1566*/ GIMT_Encode4(53635), |
| 19441 | /* 53573 */ /*GILLT_v4s16*//*Label 1567*/ GIMT_Encode4(53681), |
| 19442 | /* 53577 */ /*GILLT_v8s16*//*Label 1568*/ GIMT_Encode4(53727), |
| 19443 | /* 53581 */ /*GILLT_v2s32*//*Label 1569*/ GIMT_Encode4(53773), |
| 19444 | /* 53585 */ /*GILLT_v4s32*//*Label 1570*/ GIMT_Encode4(53819), |
| 19445 | /* 53589 */ // Label 1565: @53589 |
| 19446 | /* 53589 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1572*/ GIMT_Encode4(53634), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 934 // |
| 19447 | /* 53596 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19448 | /* 53599 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19449 | /* 53602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19450 | /* 53606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19451 | /* 53610 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19452 | /* 53614 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4067:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19453 | /* 53614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i8), |
| 19454 | /* 53617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19455 | /* 53619 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19456 | /* 53621 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19457 | /* 53623 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19458 | /* 53626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19459 | /* 53632 */ GIR_RootConstrainSelectedInstOperands, |
| 19460 | /* 53633 */ // GIR_Coverage, 934, |
| 19461 | /* 53633 */ GIR_EraseRootFromParent_Done, |
| 19462 | /* 53634 */ // Label 1572: @53634 |
| 19463 | /* 53634 */ GIM_Reject, |
| 19464 | /* 53635 */ // Label 1566: @53635 |
| 19465 | /* 53635 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1573*/ GIMT_Encode4(53680), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 935 // |
| 19466 | /* 53642 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19467 | /* 53645 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19468 | /* 53648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19469 | /* 53652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19470 | /* 53656 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19471 | /* 53660 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4067:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 19472 | /* 53660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv16i8), |
| 19473 | /* 53663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19474 | /* 53665 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19475 | /* 53667 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19476 | /* 53669 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19477 | /* 53672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19478 | /* 53678 */ GIR_RootConstrainSelectedInstOperands, |
| 19479 | /* 53679 */ // GIR_Coverage, 935, |
| 19480 | /* 53679 */ GIR_EraseRootFromParent_Done, |
| 19481 | /* 53680 */ // Label 1573: @53680 |
| 19482 | /* 53680 */ GIM_Reject, |
| 19483 | /* 53681 */ // Label 1567: @53681 |
| 19484 | /* 53681 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1574*/ GIMT_Encode4(53726), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 930 // |
| 19485 | /* 53688 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19486 | /* 53691 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19487 | /* 53694 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19488 | /* 53698 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19489 | /* 53702 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19490 | /* 53706 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4067:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19491 | /* 53706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i16), |
| 19492 | /* 53709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19493 | /* 53711 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19494 | /* 53713 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19495 | /* 53715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19496 | /* 53718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19497 | /* 53724 */ GIR_RootConstrainSelectedInstOperands, |
| 19498 | /* 53725 */ // GIR_Coverage, 930, |
| 19499 | /* 53725 */ GIR_EraseRootFromParent_Done, |
| 19500 | /* 53726 */ // Label 1574: @53726 |
| 19501 | /* 53726 */ GIM_Reject, |
| 19502 | /* 53727 */ // Label 1568: @53727 |
| 19503 | /* 53727 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1575*/ GIMT_Encode4(53772), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 932 // |
| 19504 | /* 53734 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19505 | /* 53737 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19506 | /* 53740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19507 | /* 53744 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19508 | /* 53748 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19509 | /* 53752 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4067:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19510 | /* 53752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i16), |
| 19511 | /* 53755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19512 | /* 53757 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19513 | /* 53759 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19514 | /* 53761 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19515 | /* 53764 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19516 | /* 53770 */ GIR_RootConstrainSelectedInstOperands, |
| 19517 | /* 53771 */ // GIR_Coverage, 932, |
| 19518 | /* 53771 */ GIR_EraseRootFromParent_Done, |
| 19519 | /* 53772 */ // Label 1575: @53772 |
| 19520 | /* 53772 */ GIM_Reject, |
| 19521 | /* 53773 */ // Label 1569: @53773 |
| 19522 | /* 53773 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1576*/ GIMT_Encode4(53818), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 931 // |
| 19523 | /* 53780 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19524 | /* 53783 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19525 | /* 53786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19526 | /* 53790 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19527 | /* 53794 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19528 | /* 53798 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4067:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19529 | /* 53798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv2i32), |
| 19530 | /* 53801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19531 | /* 53803 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19532 | /* 53805 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19533 | /* 53807 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19534 | /* 53810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19535 | /* 53816 */ GIR_RootConstrainSelectedInstOperands, |
| 19536 | /* 53817 */ // GIR_Coverage, 931, |
| 19537 | /* 53817 */ GIR_EraseRootFromParent_Done, |
| 19538 | /* 53818 */ // Label 1576: @53818 |
| 19539 | /* 53818 */ GIM_Reject, |
| 19540 | /* 53819 */ // Label 1570: @53819 |
| 19541 | /* 53819 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1577*/ GIMT_Encode4(53864), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 933 // |
| 19542 | /* 53826 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19543 | /* 53829 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19544 | /* 53832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19545 | /* 53836 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19546 | /* 53840 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19547 | /* 53844 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4067:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19548 | /* 53844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i32), |
| 19549 | /* 53847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19550 | /* 53849 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19551 | /* 53851 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19552 | /* 53853 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19553 | /* 53856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19554 | /* 53862 */ GIR_RootConstrainSelectedInstOperands, |
| 19555 | /* 53863 */ // GIR_Coverage, 933, |
| 19556 | /* 53863 */ GIR_EraseRootFromParent_Done, |
| 19557 | /* 53864 */ // Label 1577: @53864 |
| 19558 | /* 53864 */ GIM_Reject, |
| 19559 | /* 53865 */ // Label 1571: @53865 |
| 19560 | /* 53865 */ GIM_Reject, |
| 19561 | /* 53866 */ // Label 1564: @53866 |
| 19562 | /* 53866 */ GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(54046), |
| 19563 | /* 53871 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn), |
| 19564 | /* 53876 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1582*/ GIMT_Encode4(54045), |
| 19565 | /* 53887 */ /*GILLT_v8s8*//*Label 1579*/ GIMT_Encode4(53907), GIMT_Encode4(0), |
| 19566 | /* 53895 */ /*GILLT_v4s16*//*Label 1580*/ GIMT_Encode4(53953), GIMT_Encode4(0), |
| 19567 | /* 53903 */ /*GILLT_v2s32*//*Label 1581*/ GIMT_Encode4(53999), |
| 19568 | /* 53907 */ // Label 1579: @53907 |
| 19569 | /* 53907 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1583*/ GIMT_Encode4(53952), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 952 // |
| 19570 | /* 53914 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19571 | /* 53917 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19572 | /* 53920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19573 | /* 53924 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19574 | /* 53928 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19575 | /* 53932 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4063:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRADDHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19576 | /* 53932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv8i8), |
| 19577 | /* 53935 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19578 | /* 53937 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19579 | /* 53939 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19580 | /* 53941 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19581 | /* 53944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19582 | /* 53950 */ GIR_RootConstrainSelectedInstOperands, |
| 19583 | /* 53951 */ // GIR_Coverage, 952, |
| 19584 | /* 53951 */ GIR_EraseRootFromParent_Done, |
| 19585 | /* 53952 */ // Label 1583: @53952 |
| 19586 | /* 53952 */ GIM_Reject, |
| 19587 | /* 53953 */ // Label 1580: @53953 |
| 19588 | /* 53953 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1584*/ GIMT_Encode4(53998), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 953 // |
| 19589 | /* 53960 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19590 | /* 53963 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19591 | /* 53966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19592 | /* 53970 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19593 | /* 53974 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19594 | /* 53978 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4063:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRADDHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19595 | /* 53978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv4i16), |
| 19596 | /* 53981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19597 | /* 53983 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19598 | /* 53985 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19599 | /* 53987 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19600 | /* 53990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19601 | /* 53996 */ GIR_RootConstrainSelectedInstOperands, |
| 19602 | /* 53997 */ // GIR_Coverage, 953, |
| 19603 | /* 53997 */ GIR_EraseRootFromParent_Done, |
| 19604 | /* 53998 */ // Label 1584: @53998 |
| 19605 | /* 53998 */ GIM_Reject, |
| 19606 | /* 53999 */ // Label 1581: @53999 |
| 19607 | /* 53999 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1585*/ GIMT_Encode4(54044), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 954 // |
| 19608 | /* 54006 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19609 | /* 54009 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 19610 | /* 54012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19611 | /* 54016 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19612 | /* 54020 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19613 | /* 54024 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4063:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRADDHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 19614 | /* 54024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv2i32), |
| 19615 | /* 54027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19616 | /* 54029 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19617 | /* 54031 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19618 | /* 54033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19619 | /* 54036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19620 | /* 54042 */ GIR_RootConstrainSelectedInstOperands, |
| 19621 | /* 54043 */ // GIR_Coverage, 954, |
| 19622 | /* 54043 */ GIR_EraseRootFromParent_Done, |
| 19623 | /* 54044 */ // Label 1585: @54044 |
| 19624 | /* 54044 */ GIM_Reject, |
| 19625 | /* 54045 */ // Label 1582: @54045 |
| 19626 | /* 54045 */ GIM_Reject, |
| 19627 | /* 54046 */ // Label 1578: @54046 |
| 19628 | /* 54046 */ GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(54168), |
| 19629 | /* 54051 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp), |
| 19630 | /* 54056 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 1589*/ GIMT_Encode4(54167), |
| 19631 | /* 54067 */ /*GILLT_v8s8*//*Label 1587*/ GIMT_Encode4(54075), |
| 19632 | /* 54071 */ /*GILLT_v16s8*//*Label 1588*/ GIMT_Encode4(54121), |
| 19633 | /* 54075 */ // Label 1587: @54075 |
| 19634 | /* 54075 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1590*/ GIMT_Encode4(54120), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 961 // |
| 19635 | /* 54082 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19636 | /* 54085 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19637 | /* 54088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19638 | /* 54092 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19639 | /* 54096 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19640 | /* 54100 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4032:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULpd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19641 | /* 54100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpd), |
| 19642 | /* 54103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19643 | /* 54105 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19644 | /* 54107 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19645 | /* 54109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19646 | /* 54112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19647 | /* 54118 */ GIR_RootConstrainSelectedInstOperands, |
| 19648 | /* 54119 */ // GIR_Coverage, 961, |
| 19649 | /* 54119 */ GIR_EraseRootFromParent_Done, |
| 19650 | /* 54120 */ // Label 1590: @54120 |
| 19651 | /* 54120 */ GIM_Reject, |
| 19652 | /* 54121 */ // Label 1588: @54121 |
| 19653 | /* 54121 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1591*/ GIMT_Encode4(54166), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 962 // |
| 19654 | /* 54128 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19655 | /* 54131 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19656 | /* 54134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19657 | /* 54138 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19658 | /* 54142 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19659 | /* 54146 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4032:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULpq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 19660 | /* 54146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpq), |
| 19661 | /* 54149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19662 | /* 54151 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19663 | /* 54153 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19664 | /* 54155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19665 | /* 54158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19666 | /* 54164 */ GIR_RootConstrainSelectedInstOperands, |
| 19667 | /* 54165 */ // GIR_Coverage, 962, |
| 19668 | /* 54165 */ GIR_EraseRootFromParent_Done, |
| 19669 | /* 54166 */ // Label 1591: @54166 |
| 19670 | /* 54166 */ GIM_Reject, |
| 19671 | /* 54167 */ // Label 1589: @54167 |
| 19672 | /* 54167 */ GIM_Reject, |
| 19673 | /* 54168 */ // Label 1586: @54168 |
| 19674 | /* 54168 */ GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(54390), |
| 19675 | /* 54173 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh), |
| 19676 | /* 54178 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1597*/ GIMT_Encode4(54389), |
| 19677 | /* 54189 */ /*GILLT_v4s16*//*Label 1593*/ GIMT_Encode4(54205), |
| 19678 | /* 54193 */ /*GILLT_v8s16*//*Label 1594*/ GIMT_Encode4(54251), |
| 19679 | /* 54197 */ /*GILLT_v2s32*//*Label 1595*/ GIMT_Encode4(54297), |
| 19680 | /* 54201 */ /*GILLT_v4s32*//*Label 1596*/ GIMT_Encode4(54343), |
| 19681 | /* 54205 */ // Label 1593: @54205 |
| 19682 | /* 54205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1598*/ GIMT_Encode4(54250), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 975 // |
| 19683 | /* 54212 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19684 | /* 54215 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19685 | /* 54218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19686 | /* 54222 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19687 | /* 54226 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19688 | /* 54230 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4043:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19689 | /* 54230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i16), |
| 19690 | /* 54233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19691 | /* 54235 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19692 | /* 54237 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19693 | /* 54239 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19694 | /* 54242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19695 | /* 54248 */ GIR_RootConstrainSelectedInstOperands, |
| 19696 | /* 54249 */ // GIR_Coverage, 975, |
| 19697 | /* 54249 */ GIR_EraseRootFromParent_Done, |
| 19698 | /* 54250 */ // Label 1598: @54250 |
| 19699 | /* 54250 */ GIM_Reject, |
| 19700 | /* 54251 */ // Label 1594: @54251 |
| 19701 | /* 54251 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1599*/ GIMT_Encode4(54296), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 977 // |
| 19702 | /* 54258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19703 | /* 54261 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19704 | /* 54264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19705 | /* 54268 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19706 | /* 54272 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19707 | /* 54276 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4043:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19708 | /* 54276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv8i16), |
| 19709 | /* 54279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19710 | /* 54281 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19711 | /* 54283 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19712 | /* 54285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19713 | /* 54288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19714 | /* 54294 */ GIR_RootConstrainSelectedInstOperands, |
| 19715 | /* 54295 */ // GIR_Coverage, 977, |
| 19716 | /* 54295 */ GIR_EraseRootFromParent_Done, |
| 19717 | /* 54296 */ // Label 1599: @54296 |
| 19718 | /* 54296 */ GIM_Reject, |
| 19719 | /* 54297 */ // Label 1595: @54297 |
| 19720 | /* 54297 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1600*/ GIMT_Encode4(54342), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 976 // |
| 19721 | /* 54304 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19722 | /* 54307 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19723 | /* 54310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19724 | /* 54314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19725 | /* 54318 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19726 | /* 54322 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4043:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19727 | /* 54322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv2i32), |
| 19728 | /* 54325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19729 | /* 54327 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19730 | /* 54329 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19731 | /* 54331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19732 | /* 54334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19733 | /* 54340 */ GIR_RootConstrainSelectedInstOperands, |
| 19734 | /* 54341 */ // GIR_Coverage, 976, |
| 19735 | /* 54341 */ GIR_EraseRootFromParent_Done, |
| 19736 | /* 54342 */ // Label 1600: @54342 |
| 19737 | /* 54342 */ GIM_Reject, |
| 19738 | /* 54343 */ // Label 1596: @54343 |
| 19739 | /* 54343 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1601*/ GIMT_Encode4(54388), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 978 // |
| 19740 | /* 54350 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19741 | /* 54353 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19742 | /* 54356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19743 | /* 54360 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19744 | /* 54364 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19745 | /* 54368 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4043:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19746 | /* 54368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i32), |
| 19747 | /* 54371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19748 | /* 54373 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19749 | /* 54375 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19750 | /* 54377 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19751 | /* 54380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19752 | /* 54386 */ GIR_RootConstrainSelectedInstOperands, |
| 19753 | /* 54387 */ // GIR_Coverage, 978, |
| 19754 | /* 54387 */ GIR_EraseRootFromParent_Done, |
| 19755 | /* 54388 */ // Label 1601: @54388 |
| 19756 | /* 54388 */ GIM_Reject, |
| 19757 | /* 54389 */ // Label 1597: @54389 |
| 19758 | /* 54389 */ GIM_Reject, |
| 19759 | /* 54390 */ // Label 1592: @54390 |
| 19760 | /* 54390 */ GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(54612), |
| 19761 | /* 54395 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh), |
| 19762 | /* 54400 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1607*/ GIMT_Encode4(54611), |
| 19763 | /* 54411 */ /*GILLT_v4s16*//*Label 1603*/ GIMT_Encode4(54427), |
| 19764 | /* 54415 */ /*GILLT_v8s16*//*Label 1604*/ GIMT_Encode4(54473), |
| 19765 | /* 54419 */ /*GILLT_v2s32*//*Label 1605*/ GIMT_Encode4(54519), |
| 19766 | /* 54423 */ /*GILLT_v4s32*//*Label 1606*/ GIMT_Encode4(54565), |
| 19767 | /* 54427 */ // Label 1603: @54427 |
| 19768 | /* 54427 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1608*/ GIMT_Encode4(54472), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 983 // |
| 19769 | /* 54434 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19770 | /* 54437 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19771 | /* 54440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19772 | /* 54444 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19773 | /* 54448 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19774 | /* 54452 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4051:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19775 | /* 54452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i16), |
| 19776 | /* 54455 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19777 | /* 54457 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19778 | /* 54459 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19779 | /* 54461 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19780 | /* 54464 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19781 | /* 54470 */ GIR_RootConstrainSelectedInstOperands, |
| 19782 | /* 54471 */ // GIR_Coverage, 983, |
| 19783 | /* 54471 */ GIR_EraseRootFromParent_Done, |
| 19784 | /* 54472 */ // Label 1608: @54472 |
| 19785 | /* 54472 */ GIM_Reject, |
| 19786 | /* 54473 */ // Label 1604: @54473 |
| 19787 | /* 54473 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1609*/ GIMT_Encode4(54518), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 985 // |
| 19788 | /* 54480 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19789 | /* 54483 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19790 | /* 54486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19791 | /* 54490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19792 | /* 54494 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19793 | /* 54498 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4051:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19794 | /* 54498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv8i16), |
| 19795 | /* 54501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19796 | /* 54503 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19797 | /* 54505 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19798 | /* 54507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19799 | /* 54510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19800 | /* 54516 */ GIR_RootConstrainSelectedInstOperands, |
| 19801 | /* 54517 */ // GIR_Coverage, 985, |
| 19802 | /* 54517 */ GIR_EraseRootFromParent_Done, |
| 19803 | /* 54518 */ // Label 1609: @54518 |
| 19804 | /* 54518 */ GIM_Reject, |
| 19805 | /* 54519 */ // Label 1605: @54519 |
| 19806 | /* 54519 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1610*/ GIMT_Encode4(54564), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 984 // |
| 19807 | /* 54526 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19808 | /* 54529 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19809 | /* 54532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19810 | /* 54536 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19811 | /* 54540 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19812 | /* 54544 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4051:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19813 | /* 54544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv2i32), |
| 19814 | /* 54547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19815 | /* 54549 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19816 | /* 54551 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19817 | /* 54553 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19818 | /* 54556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19819 | /* 54562 */ GIR_RootConstrainSelectedInstOperands, |
| 19820 | /* 54563 */ // GIR_Coverage, 984, |
| 19821 | /* 54563 */ GIR_EraseRootFromParent_Done, |
| 19822 | /* 54564 */ // Label 1610: @54564 |
| 19823 | /* 54564 */ GIM_Reject, |
| 19824 | /* 54565 */ // Label 1606: @54565 |
| 19825 | /* 54565 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1611*/ GIMT_Encode4(54610), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 986 // |
| 19826 | /* 54572 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19827 | /* 54575 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19828 | /* 54578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19829 | /* 54582 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19830 | /* 54586 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19831 | /* 54590 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4051:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19832 | /* 54590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i32), |
| 19833 | /* 54593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19834 | /* 54595 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19835 | /* 54597 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19836 | /* 54599 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19837 | /* 54602 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19838 | /* 54608 */ GIR_RootConstrainSelectedInstOperands, |
| 19839 | /* 54609 */ // GIR_Coverage, 986, |
| 19840 | /* 54609 */ GIR_EraseRootFromParent_Done, |
| 19841 | /* 54610 */ // Label 1611: @54610 |
| 19842 | /* 54610 */ GIM_Reject, |
| 19843 | /* 54611 */ // Label 1607: @54611 |
| 19844 | /* 54611 */ GIM_Reject, |
| 19845 | /* 54612 */ // Label 1602: @54612 |
| 19846 | /* 54612 */ GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(54733), |
| 19847 | /* 54617 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp), |
| 19848 | /* 54622 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 1615*/ GIMT_Encode4(54732), |
| 19849 | /* 54633 */ /*GILLT_v8s16*//*Label 1613*/ GIMT_Encode4(54649), GIMT_Encode4(0), GIMT_Encode4(0), |
| 19850 | /* 54645 */ /*GILLT_v2s64*//*Label 1614*/ GIMT_Encode4(54695), |
| 19851 | /* 54649 */ // Label 1613: @54649 |
| 19852 | /* 54649 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1616*/ GIMT_Encode4(54694), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 997 // |
| 19853 | /* 54656 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19854 | /* 54659 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19855 | /* 54662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19856 | /* 54666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19857 | /* 54670 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19858 | /* 54674 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4029:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULLp8:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19859 | /* 54674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp8), |
| 19860 | /* 54677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19861 | /* 54679 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19862 | /* 54681 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19863 | /* 54683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19864 | /* 54686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19865 | /* 54692 */ GIR_RootConstrainSelectedInstOperands, |
| 19866 | /* 54693 */ // GIR_Coverage, 997, |
| 19867 | /* 54693 */ GIR_EraseRootFromParent_Done, |
| 19868 | /* 54694 */ // Label 1616: @54694 |
| 19869 | /* 54694 */ GIM_Reject, |
| 19870 | /* 54695 */ // Label 1614: @54695 |
| 19871 | /* 54695 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1617*/ GIMT_Encode4(54731), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 998 // |
| 19872 | /* 54702 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 19873 | /* 54705 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 19874 | /* 54708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19875 | /* 54712 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19876 | /* 54716 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19877 | /* 54720 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4029:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VMULLp64:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 19878 | /* 54720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp64), |
| 19879 | /* 54723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19880 | /* 54725 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19881 | /* 54727 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19882 | /* 54729 */ GIR_RootConstrainSelectedInstOperands, |
| 19883 | /* 54730 */ // GIR_Coverage, 998, |
| 19884 | /* 54730 */ GIR_EraseRootFromParent_Done, |
| 19885 | /* 54731 */ // Label 1617: @54731 |
| 19886 | /* 54731 */ GIM_Reject, |
| 19887 | /* 54732 */ // Label 1615: @54732 |
| 19888 | /* 54732 */ GIM_Reject, |
| 19889 | /* 54733 */ // Label 1612: @54733 |
| 19890 | /* 54733 */ GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(54855), |
| 19891 | /* 54738 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 19892 | /* 54743 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 1621*/ GIMT_Encode4(54854), |
| 19893 | /* 54754 */ /*GILLT_v4s32*//*Label 1619*/ GIMT_Encode4(54762), |
| 19894 | /* 54758 */ /*GILLT_v2s64*//*Label 1620*/ GIMT_Encode4(54808), |
| 19895 | /* 54762 */ // Label 1619: @54762 |
| 19896 | /* 54762 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1622*/ GIMT_Encode4(54807), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1003 // |
| 19897 | /* 54769 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19898 | /* 54772 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19899 | /* 54775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19900 | /* 54779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19901 | /* 54783 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19902 | /* 54787 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4044:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULLv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19903 | /* 54787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv4i32), |
| 19904 | /* 54790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19905 | /* 54792 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19906 | /* 54794 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19907 | /* 54796 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19908 | /* 54799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19909 | /* 54805 */ GIR_RootConstrainSelectedInstOperands, |
| 19910 | /* 54806 */ // GIR_Coverage, 1003, |
| 19911 | /* 54806 */ GIR_EraseRootFromParent_Done, |
| 19912 | /* 54807 */ // Label 1622: @54807 |
| 19913 | /* 54807 */ GIM_Reject, |
| 19914 | /* 54808 */ // Label 1620: @54808 |
| 19915 | /* 54808 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1623*/ GIMT_Encode4(54853), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1004 // |
| 19916 | /* 54815 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19917 | /* 54818 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19918 | /* 54821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19919 | /* 54825 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19920 | /* 54829 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19921 | /* 54833 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4044:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULLv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19922 | /* 54833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv2i64), |
| 19923 | /* 54836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19924 | /* 54838 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19925 | /* 54840 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19926 | /* 54842 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19927 | /* 54845 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19928 | /* 54851 */ GIR_RootConstrainSelectedInstOperands, |
| 19929 | /* 54852 */ // GIR_Coverage, 1004, |
| 19930 | /* 54852 */ GIR_EraseRootFromParent_Done, |
| 19931 | /* 54853 */ // Label 1623: @54853 |
| 19932 | /* 54853 */ GIM_Reject, |
| 19933 | /* 54854 */ // Label 1621: @54854 |
| 19934 | /* 54854 */ GIM_Reject, |
| 19935 | /* 54855 */ // Label 1618: @54855 |
| 19936 | /* 54855 */ GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(55177), |
| 19937 | /* 54860 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 19938 | /* 54865 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1631*/ GIMT_Encode4(55176), |
| 19939 | /* 54876 */ /*GILLT_v8s8*//*Label 1625*/ GIMT_Encode4(54900), |
| 19940 | /* 54880 */ /*GILLT_v16s8*//*Label 1626*/ GIMT_Encode4(54946), |
| 19941 | /* 54884 */ /*GILLT_v4s16*//*Label 1627*/ GIMT_Encode4(54992), |
| 19942 | /* 54888 */ /*GILLT_v8s16*//*Label 1628*/ GIMT_Encode4(55038), |
| 19943 | /* 54892 */ /*GILLT_v2s32*//*Label 1629*/ GIMT_Encode4(55084), |
| 19944 | /* 54896 */ /*GILLT_v4s32*//*Label 1630*/ GIMT_Encode4(55130), |
| 19945 | /* 54900 */ // Label 1625: @54900 |
| 19946 | /* 54900 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1632*/ GIMT_Encode4(54945), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1162 // |
| 19947 | /* 54907 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19948 | /* 54910 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19949 | /* 54913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19950 | /* 54917 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19951 | /* 54921 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19952 | /* 54925 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4008:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19953 | /* 54925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i8), |
| 19954 | /* 54928 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19955 | /* 54930 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19956 | /* 54932 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19957 | /* 54934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19958 | /* 54937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19959 | /* 54943 */ GIR_RootConstrainSelectedInstOperands, |
| 19960 | /* 54944 */ // GIR_Coverage, 1162, |
| 19961 | /* 54944 */ GIR_EraseRootFromParent_Done, |
| 19962 | /* 54945 */ // Label 1632: @54945 |
| 19963 | /* 54945 */ GIM_Reject, |
| 19964 | /* 54946 */ // Label 1626: @54946 |
| 19965 | /* 54946 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1633*/ GIMT_Encode4(54991), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1163 // |
| 19966 | /* 54953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19967 | /* 54956 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19968 | /* 54959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19969 | /* 54963 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19970 | /* 54967 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19971 | /* 54971 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4008:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 19972 | /* 54971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv16i8), |
| 19973 | /* 54974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19974 | /* 54976 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19975 | /* 54978 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19976 | /* 54980 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19977 | /* 54983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19978 | /* 54989 */ GIR_RootConstrainSelectedInstOperands, |
| 19979 | /* 54990 */ // GIR_Coverage, 1163, |
| 19980 | /* 54990 */ GIR_EraseRootFromParent_Done, |
| 19981 | /* 54991 */ // Label 1633: @54991 |
| 19982 | /* 54991 */ GIM_Reject, |
| 19983 | /* 54992 */ // Label 1627: @54992 |
| 19984 | /* 54992 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1634*/ GIMT_Encode4(55037), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1158 // |
| 19985 | /* 54999 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19986 | /* 55002 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19987 | /* 55005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19988 | /* 55009 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19989 | /* 55013 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19990 | /* 55017 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4008:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19991 | /* 55017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i16), |
| 19992 | /* 55020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19993 | /* 55022 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19994 | /* 55024 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19995 | /* 55026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19996 | /* 55029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19997 | /* 55035 */ GIR_RootConstrainSelectedInstOperands, |
| 19998 | /* 55036 */ // GIR_Coverage, 1158, |
| 19999 | /* 55036 */ GIR_EraseRootFromParent_Done, |
| 20000 | /* 55037 */ // Label 1634: @55037 |
| 20001 | /* 55037 */ GIM_Reject, |
| 20002 | /* 55038 */ // Label 1628: @55038 |
| 20003 | /* 55038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1635*/ GIMT_Encode4(55083), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1160 // |
| 20004 | /* 55045 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20005 | /* 55048 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20006 | /* 55051 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20007 | /* 55055 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20008 | /* 55059 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20009 | /* 55063 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4008:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 20010 | /* 55063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i16), |
| 20011 | /* 55066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20012 | /* 55068 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20013 | /* 55070 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20014 | /* 55072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20015 | /* 55075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20016 | /* 55081 */ GIR_RootConstrainSelectedInstOperands, |
| 20017 | /* 55082 */ // GIR_Coverage, 1160, |
| 20018 | /* 55082 */ GIR_EraseRootFromParent_Done, |
| 20019 | /* 55083 */ // Label 1635: @55083 |
| 20020 | /* 55083 */ GIM_Reject, |
| 20021 | /* 55084 */ // Label 1629: @55084 |
| 20022 | /* 55084 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1636*/ GIMT_Encode4(55129), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1159 // |
| 20023 | /* 55091 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20024 | /* 55094 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20025 | /* 55097 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20026 | /* 55101 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20027 | /* 55105 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20028 | /* 55109 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4008:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20029 | /* 55109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv2i32), |
| 20030 | /* 55112 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20031 | /* 55114 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20032 | /* 55116 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20033 | /* 55118 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20034 | /* 55121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20035 | /* 55127 */ GIR_RootConstrainSelectedInstOperands, |
| 20036 | /* 55128 */ // GIR_Coverage, 1159, |
| 20037 | /* 55128 */ GIR_EraseRootFromParent_Done, |
| 20038 | /* 55129 */ // Label 1636: @55129 |
| 20039 | /* 55129 */ GIM_Reject, |
| 20040 | /* 55130 */ // Label 1630: @55130 |
| 20041 | /* 55130 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1637*/ GIMT_Encode4(55175), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1161 // |
| 20042 | /* 55137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20043 | /* 55140 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20044 | /* 55143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20045 | /* 55147 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20046 | /* 55151 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20047 | /* 55155 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4008:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 20048 | /* 55155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i32), |
| 20049 | /* 55158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20050 | /* 55160 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20051 | /* 55162 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20052 | /* 55164 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20053 | /* 55167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20054 | /* 55173 */ GIR_RootConstrainSelectedInstOperands, |
| 20055 | /* 55174 */ // GIR_Coverage, 1161, |
| 20056 | /* 55174 */ GIR_EraseRootFromParent_Done, |
| 20057 | /* 55175 */ // Label 1637: @55175 |
| 20058 | /* 55175 */ GIM_Reject, |
| 20059 | /* 55176 */ // Label 1631: @55176 |
| 20060 | /* 55176 */ GIM_Reject, |
| 20061 | /* 55177 */ // Label 1624: @55177 |
| 20062 | /* 55177 */ GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(55499), |
| 20063 | /* 55182 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 20064 | /* 55187 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1645*/ GIMT_Encode4(55498), |
| 20065 | /* 55198 */ /*GILLT_v8s8*//*Label 1639*/ GIMT_Encode4(55222), |
| 20066 | /* 55202 */ /*GILLT_v16s8*//*Label 1640*/ GIMT_Encode4(55268), |
| 20067 | /* 55206 */ /*GILLT_v4s16*//*Label 1641*/ GIMT_Encode4(55314), |
| 20068 | /* 55210 */ /*GILLT_v8s16*//*Label 1642*/ GIMT_Encode4(55360), |
| 20069 | /* 55214 */ /*GILLT_v2s32*//*Label 1643*/ GIMT_Encode4(55406), |
| 20070 | /* 55218 */ /*GILLT_v4s32*//*Label 1644*/ GIMT_Encode4(55452), |
| 20071 | /* 55222 */ // Label 1639: @55222 |
| 20072 | /* 55222 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1646*/ GIMT_Encode4(55267), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1168 // |
| 20073 | /* 55229 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20074 | /* 55232 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20075 | /* 55235 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20076 | /* 55239 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20077 | /* 55243 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20078 | /* 55247 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4009:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 20079 | /* 55247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i8), |
| 20080 | /* 55250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20081 | /* 55252 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20082 | /* 55254 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20083 | /* 55256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20084 | /* 55259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20085 | /* 55265 */ GIR_RootConstrainSelectedInstOperands, |
| 20086 | /* 55266 */ // GIR_Coverage, 1168, |
| 20087 | /* 55266 */ GIR_EraseRootFromParent_Done, |
| 20088 | /* 55267 */ // Label 1646: @55267 |
| 20089 | /* 55267 */ GIM_Reject, |
| 20090 | /* 55268 */ // Label 1640: @55268 |
| 20091 | /* 55268 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1647*/ GIMT_Encode4(55313), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1169 // |
| 20092 | /* 55275 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20093 | /* 55278 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20094 | /* 55281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20095 | /* 55285 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20096 | /* 55289 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20097 | /* 55293 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4009:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 20098 | /* 55293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv16i8), |
| 20099 | /* 55296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20100 | /* 55298 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20101 | /* 55300 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20102 | /* 55302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20103 | /* 55305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20104 | /* 55311 */ GIR_RootConstrainSelectedInstOperands, |
| 20105 | /* 55312 */ // GIR_Coverage, 1169, |
| 20106 | /* 55312 */ GIR_EraseRootFromParent_Done, |
| 20107 | /* 55313 */ // Label 1647: @55313 |
| 20108 | /* 55313 */ GIM_Reject, |
| 20109 | /* 55314 */ // Label 1641: @55314 |
| 20110 | /* 55314 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1648*/ GIMT_Encode4(55359), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1164 // |
| 20111 | /* 55321 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20112 | /* 55324 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20113 | /* 55327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20114 | /* 55331 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20115 | /* 55335 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20116 | /* 55339 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4009:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20117 | /* 55339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i16), |
| 20118 | /* 55342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20119 | /* 55344 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20120 | /* 55346 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20121 | /* 55348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20122 | /* 55351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20123 | /* 55357 */ GIR_RootConstrainSelectedInstOperands, |
| 20124 | /* 55358 */ // GIR_Coverage, 1164, |
| 20125 | /* 55358 */ GIR_EraseRootFromParent_Done, |
| 20126 | /* 55359 */ // Label 1648: @55359 |
| 20127 | /* 55359 */ GIM_Reject, |
| 20128 | /* 55360 */ // Label 1642: @55360 |
| 20129 | /* 55360 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1649*/ GIMT_Encode4(55405), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1166 // |
| 20130 | /* 55367 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20131 | /* 55370 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20132 | /* 55373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20133 | /* 55377 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20134 | /* 55381 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20135 | /* 55385 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4009:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 20136 | /* 55385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i16), |
| 20137 | /* 55388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20138 | /* 55390 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20139 | /* 55392 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20140 | /* 55394 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20141 | /* 55397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20142 | /* 55403 */ GIR_RootConstrainSelectedInstOperands, |
| 20143 | /* 55404 */ // GIR_Coverage, 1166, |
| 20144 | /* 55404 */ GIR_EraseRootFromParent_Done, |
| 20145 | /* 55405 */ // Label 1649: @55405 |
| 20146 | /* 55405 */ GIM_Reject, |
| 20147 | /* 55406 */ // Label 1643: @55406 |
| 20148 | /* 55406 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1650*/ GIMT_Encode4(55451), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1165 // |
| 20149 | /* 55413 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20150 | /* 55416 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20151 | /* 55419 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20152 | /* 55423 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20153 | /* 55427 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20154 | /* 55431 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4009:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20155 | /* 55431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv2i32), |
| 20156 | /* 55434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20157 | /* 55436 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20158 | /* 55438 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20159 | /* 55440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20160 | /* 55443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20161 | /* 55449 */ GIR_RootConstrainSelectedInstOperands, |
| 20162 | /* 55450 */ // GIR_Coverage, 1165, |
| 20163 | /* 55450 */ GIR_EraseRootFromParent_Done, |
| 20164 | /* 55451 */ // Label 1650: @55451 |
| 20165 | /* 55451 */ GIM_Reject, |
| 20166 | /* 55452 */ // Label 1644: @55452 |
| 20167 | /* 55452 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1651*/ GIMT_Encode4(55497), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1167 // |
| 20168 | /* 55459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20169 | /* 55462 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20170 | /* 55465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20171 | /* 55469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20172 | /* 55473 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20173 | /* 55477 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4009:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 20174 | /* 55477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i32), |
| 20175 | /* 55480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20176 | /* 55482 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20177 | /* 55484 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20178 | /* 55486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20179 | /* 55489 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20180 | /* 55495 */ GIR_RootConstrainSelectedInstOperands, |
| 20181 | /* 55496 */ // GIR_Coverage, 1167, |
| 20182 | /* 55496 */ GIR_EraseRootFromParent_Done, |
| 20183 | /* 55497 */ // Label 1651: @55497 |
| 20184 | /* 55497 */ GIM_Reject, |
| 20185 | /* 55498 */ // Label 1645: @55498 |
| 20186 | /* 55498 */ GIM_Reject, |
| 20187 | /* 55499 */ // Label 1638: @55499 |
| 20188 | /* 55499 */ GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(55679), |
| 20189 | /* 55504 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn), |
| 20190 | /* 55509 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1656*/ GIMT_Encode4(55678), |
| 20191 | /* 55520 */ /*GILLT_v8s8*//*Label 1653*/ GIMT_Encode4(55540), GIMT_Encode4(0), |
| 20192 | /* 55528 */ /*GILLT_v4s16*//*Label 1654*/ GIMT_Encode4(55586), GIMT_Encode4(0), |
| 20193 | /* 55536 */ /*GILLT_v2s32*//*Label 1655*/ GIMT_Encode4(55632), |
| 20194 | /* 55540 */ // Label 1653: @55540 |
| 20195 | /* 55540 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1657*/ GIMT_Encode4(55585), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1186 // |
| 20196 | /* 55547 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20197 | /* 55550 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20198 | /* 55553 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20199 | /* 55557 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20200 | /* 55561 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20201 | /* 55565 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4073:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRSUBHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 20202 | /* 55565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv8i8), |
| 20203 | /* 55568 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20204 | /* 55570 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20205 | /* 55572 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20206 | /* 55574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20207 | /* 55577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20208 | /* 55583 */ GIR_RootConstrainSelectedInstOperands, |
| 20209 | /* 55584 */ // GIR_Coverage, 1186, |
| 20210 | /* 55584 */ GIR_EraseRootFromParent_Done, |
| 20211 | /* 55585 */ // Label 1657: @55585 |
| 20212 | /* 55585 */ GIM_Reject, |
| 20213 | /* 55586 */ // Label 1654: @55586 |
| 20214 | /* 55586 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1658*/ GIMT_Encode4(55631), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1187 // |
| 20215 | /* 55593 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20216 | /* 55596 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20217 | /* 55599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20218 | /* 55603 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20219 | /* 55607 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20220 | /* 55611 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4073:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRSUBHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 20221 | /* 55611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv4i16), |
| 20222 | /* 55614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20223 | /* 55616 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20224 | /* 55618 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20225 | /* 55620 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20226 | /* 55623 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20227 | /* 55629 */ GIR_RootConstrainSelectedInstOperands, |
| 20228 | /* 55630 */ // GIR_Coverage, 1187, |
| 20229 | /* 55630 */ GIR_EraseRootFromParent_Done, |
| 20230 | /* 55631 */ // Label 1658: @55631 |
| 20231 | /* 55631 */ GIM_Reject, |
| 20232 | /* 55632 */ // Label 1655: @55632 |
| 20233 | /* 55632 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1659*/ GIMT_Encode4(55677), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1188 // |
| 20234 | /* 55639 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20235 | /* 55642 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 20236 | /* 55645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20237 | /* 55649 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20238 | /* 55653 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20239 | /* 55657 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4073:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRSUBHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 20240 | /* 55657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv2i32), |
| 20241 | /* 55660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20242 | /* 55662 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20243 | /* 55664 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20244 | /* 55666 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20245 | /* 55669 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20246 | /* 55675 */ GIR_RootConstrainSelectedInstOperands, |
| 20247 | /* 55676 */ // GIR_Coverage, 1188, |
| 20248 | /* 55676 */ GIR_EraseRootFromParent_Done, |
| 20249 | /* 55677 */ // Label 1659: @55677 |
| 20250 | /* 55677 */ GIM_Reject, |
| 20251 | /* 55678 */ // Label 1656: @55678 |
| 20252 | /* 55678 */ GIM_Reject, |
| 20253 | /* 55679 */ // Label 1652: @55679 |
| 20254 | /* 55679 */ GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(55901), |
| 20255 | /* 55684 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge), |
| 20256 | /* 55689 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1665*/ GIMT_Encode4(55900), |
| 20257 | /* 55700 */ /*GILLT_v4s16*//*Label 1661*/ GIMT_Encode4(55716), |
| 20258 | /* 55704 */ /*GILLT_v8s16*//*Label 1662*/ GIMT_Encode4(55762), |
| 20259 | /* 55708 */ /*GILLT_v2s32*//*Label 1663*/ GIMT_Encode4(55808), |
| 20260 | /* 55712 */ /*GILLT_v4s32*//*Label 1664*/ GIMT_Encode4(55854), |
| 20261 | /* 55716 */ // Label 1661: @55716 |
| 20262 | /* 55716 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1666*/ GIMT_Encode4(55761), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1283 // |
| 20263 | /* 55723 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20264 | /* 55726 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20265 | /* 55729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20266 | /* 55733 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20267 | /* 55737 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20268 | /* 55741 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3984:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGEhd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 20269 | /* 55741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhd), |
| 20270 | /* 55744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20271 | /* 55746 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20272 | /* 55748 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20273 | /* 55750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20274 | /* 55753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20275 | /* 55759 */ GIR_RootConstrainSelectedInstOperands, |
| 20276 | /* 55760 */ // GIR_Coverage, 1283, |
| 20277 | /* 55760 */ GIR_EraseRootFromParent_Done, |
| 20278 | /* 55761 */ // Label 1666: @55761 |
| 20279 | /* 55761 */ GIM_Reject, |
| 20280 | /* 55762 */ // Label 1662: @55762 |
| 20281 | /* 55762 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1667*/ GIMT_Encode4(55807), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1284 // |
| 20282 | /* 55769 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20283 | /* 55772 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20284 | /* 55775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20285 | /* 55779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20286 | /* 55783 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20287 | /* 55787 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3984:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGEhq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 20288 | /* 55787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhq), |
| 20289 | /* 55790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20290 | /* 55792 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20291 | /* 55794 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20292 | /* 55796 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20293 | /* 55799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20294 | /* 55805 */ GIR_RootConstrainSelectedInstOperands, |
| 20295 | /* 55806 */ // GIR_Coverage, 1284, |
| 20296 | /* 55806 */ GIR_EraseRootFromParent_Done, |
| 20297 | /* 55807 */ // Label 1667: @55807 |
| 20298 | /* 55807 */ GIM_Reject, |
| 20299 | /* 55808 */ // Label 1663: @55808 |
| 20300 | /* 55808 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1668*/ GIMT_Encode4(55853), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1281 // |
| 20301 | /* 55815 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20302 | /* 55818 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20303 | /* 55821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20304 | /* 55825 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20305 | /* 55829 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20306 | /* 55833 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3984:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGEfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 20307 | /* 55833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfd), |
| 20308 | /* 55836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20309 | /* 55838 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20310 | /* 55840 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20311 | /* 55842 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20312 | /* 55845 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20313 | /* 55851 */ GIR_RootConstrainSelectedInstOperands, |
| 20314 | /* 55852 */ // GIR_Coverage, 1281, |
| 20315 | /* 55852 */ GIR_EraseRootFromParent_Done, |
| 20316 | /* 55853 */ // Label 1668: @55853 |
| 20317 | /* 55853 */ GIM_Reject, |
| 20318 | /* 55854 */ // Label 1664: @55854 |
| 20319 | /* 55854 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1669*/ GIMT_Encode4(55899), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1282 // |
| 20320 | /* 55861 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20321 | /* 55864 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20322 | /* 55867 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20323 | /* 55871 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20324 | /* 55875 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20325 | /* 55879 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3984:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGEfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 20326 | /* 55879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfq), |
| 20327 | /* 55882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20328 | /* 55884 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20329 | /* 55886 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20330 | /* 55888 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20331 | /* 55891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20332 | /* 55897 */ GIR_RootConstrainSelectedInstOperands, |
| 20333 | /* 55898 */ // GIR_Coverage, 1282, |
| 20334 | /* 55898 */ GIR_EraseRootFromParent_Done, |
| 20335 | /* 55899 */ // Label 1669: @55899 |
| 20336 | /* 55899 */ GIM_Reject, |
| 20337 | /* 55900 */ // Label 1665: @55900 |
| 20338 | /* 55900 */ GIM_Reject, |
| 20339 | /* 55901 */ // Label 1660: @55901 |
| 20340 | /* 55901 */ GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(56123), |
| 20341 | /* 55906 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt), |
| 20342 | /* 55911 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1675*/ GIMT_Encode4(56122), |
| 20343 | /* 55922 */ /*GILLT_v4s16*//*Label 1671*/ GIMT_Encode4(55938), |
| 20344 | /* 55926 */ /*GILLT_v8s16*//*Label 1672*/ GIMT_Encode4(55984), |
| 20345 | /* 55930 */ /*GILLT_v2s32*//*Label 1673*/ GIMT_Encode4(56030), |
| 20346 | /* 55934 */ /*GILLT_v4s32*//*Label 1674*/ GIMT_Encode4(56076), |
| 20347 | /* 55938 */ // Label 1671: @55938 |
| 20348 | /* 55938 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1676*/ GIMT_Encode4(55983), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1287 // |
| 20349 | /* 55945 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20350 | /* 55948 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20351 | /* 55951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20352 | /* 55955 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20353 | /* 55959 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20354 | /* 55963 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3985:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGThd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 20355 | /* 55963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThd), |
| 20356 | /* 55966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20357 | /* 55968 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20358 | /* 55970 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20359 | /* 55972 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20360 | /* 55975 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20361 | /* 55981 */ GIR_RootConstrainSelectedInstOperands, |
| 20362 | /* 55982 */ // GIR_Coverage, 1287, |
| 20363 | /* 55982 */ GIR_EraseRootFromParent_Done, |
| 20364 | /* 55983 */ // Label 1676: @55983 |
| 20365 | /* 55983 */ GIM_Reject, |
| 20366 | /* 55984 */ // Label 1672: @55984 |
| 20367 | /* 55984 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1677*/ GIMT_Encode4(56029), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1288 // |
| 20368 | /* 55991 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20369 | /* 55994 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20370 | /* 55997 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20371 | /* 56001 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20372 | /* 56005 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20373 | /* 56009 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3985:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGThq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 20374 | /* 56009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThq), |
| 20375 | /* 56012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20376 | /* 56014 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20377 | /* 56016 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20378 | /* 56018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20379 | /* 56021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20380 | /* 56027 */ GIR_RootConstrainSelectedInstOperands, |
| 20381 | /* 56028 */ // GIR_Coverage, 1288, |
| 20382 | /* 56028 */ GIR_EraseRootFromParent_Done, |
| 20383 | /* 56029 */ // Label 1677: @56029 |
| 20384 | /* 56029 */ GIM_Reject, |
| 20385 | /* 56030 */ // Label 1673: @56030 |
| 20386 | /* 56030 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1678*/ GIMT_Encode4(56075), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1285 // |
| 20387 | /* 56037 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20388 | /* 56040 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20389 | /* 56043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20390 | /* 56047 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20391 | /* 56051 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20392 | /* 56055 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3985:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGTfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 20393 | /* 56055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfd), |
| 20394 | /* 56058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20395 | /* 56060 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20396 | /* 56062 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20397 | /* 56064 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20398 | /* 56067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20399 | /* 56073 */ GIR_RootConstrainSelectedInstOperands, |
| 20400 | /* 56074 */ // GIR_Coverage, 1285, |
| 20401 | /* 56074 */ GIR_EraseRootFromParent_Done, |
| 20402 | /* 56075 */ // Label 1678: @56075 |
| 20403 | /* 56075 */ GIM_Reject, |
| 20404 | /* 56076 */ // Label 1674: @56076 |
| 20405 | /* 56076 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1679*/ GIMT_Encode4(56121), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1286 // |
| 20406 | /* 56083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20407 | /* 56086 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20408 | /* 56089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20409 | /* 56093 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20410 | /* 56097 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20411 | /* 56101 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3985:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGTfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 20412 | /* 56101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfq), |
| 20413 | /* 56104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20414 | /* 56106 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20415 | /* 56108 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20416 | /* 56110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20417 | /* 56113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20418 | /* 56119 */ GIR_RootConstrainSelectedInstOperands, |
| 20419 | /* 56120 */ // GIR_Coverage, 1286, |
| 20420 | /* 56120 */ GIR_EraseRootFromParent_Done, |
| 20421 | /* 56121 */ // Label 1679: @56121 |
| 20422 | /* 56121 */ GIM_Reject, |
| 20423 | /* 56122 */ // Label 1675: @56122 |
| 20424 | /* 56122 */ GIM_Reject, |
| 20425 | /* 56123 */ // Label 1670: @56123 |
| 20426 | /* 56123 */ GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(56345), |
| 20427 | /* 56128 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds), |
| 20428 | /* 56133 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1685*/ GIMT_Encode4(56344), |
| 20429 | /* 56144 */ /*GILLT_v4s16*//*Label 1681*/ GIMT_Encode4(56160), |
| 20430 | /* 56148 */ /*GILLT_v8s16*//*Label 1682*/ GIMT_Encode4(56206), |
| 20431 | /* 56152 */ /*GILLT_v2s32*//*Label 1683*/ GIMT_Encode4(56252), |
| 20432 | /* 56156 */ /*GILLT_v4s32*//*Label 1684*/ GIMT_Encode4(56298), |
| 20433 | /* 56160 */ // Label 1681: @56160 |
| 20434 | /* 56160 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1686*/ GIMT_Encode4(56205), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1333 // |
| 20435 | /* 56167 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20436 | /* 56170 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20437 | /* 56173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20438 | /* 56177 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20439 | /* 56181 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20440 | /* 56185 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3981:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VABDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 20441 | /* 56185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhd), |
| 20442 | /* 56188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20443 | /* 56190 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20444 | /* 56192 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20445 | /* 56194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20446 | /* 56197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20447 | /* 56203 */ GIR_RootConstrainSelectedInstOperands, |
| 20448 | /* 56204 */ // GIR_Coverage, 1333, |
| 20449 | /* 56204 */ GIR_EraseRootFromParent_Done, |
| 20450 | /* 56205 */ // Label 1686: @56205 |
| 20451 | /* 56205 */ GIM_Reject, |
| 20452 | /* 56206 */ // Label 1682: @56206 |
| 20453 | /* 56206 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1687*/ GIMT_Encode4(56251), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1334 // |
| 20454 | /* 56213 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20455 | /* 56216 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20456 | /* 56219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20457 | /* 56223 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20458 | /* 56227 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20459 | /* 56231 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3981:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VABDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 20460 | /* 56231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhq), |
| 20461 | /* 56234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20462 | /* 56236 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20463 | /* 56238 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20464 | /* 56240 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20465 | /* 56243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20466 | /* 56249 */ GIR_RootConstrainSelectedInstOperands, |
| 20467 | /* 56250 */ // GIR_Coverage, 1334, |
| 20468 | /* 56250 */ GIR_EraseRootFromParent_Done, |
| 20469 | /* 56251 */ // Label 1687: @56251 |
| 20470 | /* 56251 */ GIM_Reject, |
| 20471 | /* 56252 */ // Label 1683: @56252 |
| 20472 | /* 56252 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1688*/ GIMT_Encode4(56297), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1331 // |
| 20473 | /* 56259 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20474 | /* 56262 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20475 | /* 56265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20476 | /* 56269 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20477 | /* 56273 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20478 | /* 56277 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3981:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VABDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 20479 | /* 56277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfd), |
| 20480 | /* 56280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20481 | /* 56282 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20482 | /* 56284 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20483 | /* 56286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20484 | /* 56289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20485 | /* 56295 */ GIR_RootConstrainSelectedInstOperands, |
| 20486 | /* 56296 */ // GIR_Coverage, 1331, |
| 20487 | /* 56296 */ GIR_EraseRootFromParent_Done, |
| 20488 | /* 56297 */ // Label 1688: @56297 |
| 20489 | /* 56297 */ GIM_Reject, |
| 20490 | /* 56298 */ // Label 1684: @56298 |
| 20491 | /* 56298 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1689*/ GIMT_Encode4(56343), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1332 // |
| 20492 | /* 56305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20493 | /* 56308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20494 | /* 56311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20495 | /* 56315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20496 | /* 56319 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20497 | /* 56323 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3981:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VABDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 20498 | /* 56323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfq), |
| 20499 | /* 56326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20500 | /* 56328 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20501 | /* 56330 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20502 | /* 56332 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20503 | /* 56335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20504 | /* 56341 */ GIR_RootConstrainSelectedInstOperands, |
| 20505 | /* 56342 */ // GIR_Coverage, 1332, |
| 20506 | /* 56342 */ GIR_EraseRootFromParent_Done, |
| 20507 | /* 56343 */ // Label 1689: @56343 |
| 20508 | /* 56343 */ GIM_Reject, |
| 20509 | /* 56344 */ // Label 1685: @56344 |
| 20510 | /* 56344 */ GIM_Reject, |
| 20511 | /* 56345 */ // Label 1680: @56345 |
| 20512 | /* 56345 */ GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(56591), |
| 20513 | /* 56350 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 20514 | /* 56355 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1694*/ GIMT_Encode4(56590), |
| 20515 | /* 56366 */ /*GILLT_v8s8*//*Label 1691*/ GIMT_Encode4(56386), GIMT_Encode4(0), |
| 20516 | /* 56374 */ /*GILLT_v4s16*//*Label 1692*/ GIMT_Encode4(56432), GIMT_Encode4(0), |
| 20517 | /* 56382 */ /*GILLT_v2s32*//*Label 1693*/ GIMT_Encode4(56511), |
| 20518 | /* 56386 */ // Label 1691: @56386 |
| 20519 | /* 56386 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1695*/ GIMT_Encode4(56431), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1399 // |
| 20520 | /* 56393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20521 | /* 56396 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20522 | /* 56399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20523 | /* 56403 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20524 | /* 56407 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20525 | /* 56411 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4035:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPADDi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 20526 | /* 56411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi8), |
| 20527 | /* 56414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20528 | /* 56416 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20529 | /* 56418 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20530 | /* 56420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20531 | /* 56423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20532 | /* 56429 */ GIR_RootConstrainSelectedInstOperands, |
| 20533 | /* 56430 */ // GIR_Coverage, 1399, |
| 20534 | /* 56430 */ GIR_EraseRootFromParent_Done, |
| 20535 | /* 56431 */ // Label 1695: @56431 |
| 20536 | /* 56431 */ GIM_Reject, |
| 20537 | /* 56432 */ // Label 1692: @56432 |
| 20538 | /* 56432 */ GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(56510), |
| 20539 | /* 56437 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20540 | /* 56440 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20541 | /* 56443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20542 | /* 56447 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20543 | /* 56451 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20544 | /* 56455 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1697*/ GIMT_Encode4(56482), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1400 // |
| 20545 | /* 56462 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4035:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPADDi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20546 | /* 56462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi16), |
| 20547 | /* 56465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20548 | /* 56467 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20549 | /* 56469 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20550 | /* 56471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20551 | /* 56474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20552 | /* 56480 */ GIR_RootConstrainSelectedInstOperands, |
| 20553 | /* 56481 */ // GIR_Coverage, 1400, |
| 20554 | /* 56481 */ GIR_EraseRootFromParent_Done, |
| 20555 | /* 56482 */ // Label 1697: @56482 |
| 20556 | /* 56482 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1698*/ GIMT_Encode4(56509), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1403 // |
| 20557 | /* 56489 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4035:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPADDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 20558 | /* 56489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDh), |
| 20559 | /* 56492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20560 | /* 56494 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20561 | /* 56496 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20562 | /* 56498 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20563 | /* 56501 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20564 | /* 56507 */ GIR_RootConstrainSelectedInstOperands, |
| 20565 | /* 56508 */ // GIR_Coverage, 1403, |
| 20566 | /* 56508 */ GIR_EraseRootFromParent_Done, |
| 20567 | /* 56509 */ // Label 1698: @56509 |
| 20568 | /* 56509 */ GIM_Reject, |
| 20569 | /* 56510 */ // Label 1696: @56510 |
| 20570 | /* 56510 */ GIM_Reject, |
| 20571 | /* 56511 */ // Label 1693: @56511 |
| 20572 | /* 56511 */ GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(56589), |
| 20573 | /* 56516 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20574 | /* 56519 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20575 | /* 56522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20576 | /* 56526 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20577 | /* 56530 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20578 | /* 56534 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1700*/ GIMT_Encode4(56561), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1401 // |
| 20579 | /* 56541 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4035:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPADDi32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20580 | /* 56541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi32), |
| 20581 | /* 56544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20582 | /* 56546 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20583 | /* 56548 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20584 | /* 56550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20585 | /* 56553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20586 | /* 56559 */ GIR_RootConstrainSelectedInstOperands, |
| 20587 | /* 56560 */ // GIR_Coverage, 1401, |
| 20588 | /* 56560 */ GIR_EraseRootFromParent_Done, |
| 20589 | /* 56561 */ // Label 1700: @56561 |
| 20590 | /* 56561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1701*/ GIMT_Encode4(56588), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1402 // |
| 20591 | /* 56568 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4035:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPADDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 20592 | /* 56568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDf), |
| 20593 | /* 56571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20594 | /* 56573 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20595 | /* 56575 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20596 | /* 56577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20597 | /* 56580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20598 | /* 56586 */ GIR_RootConstrainSelectedInstOperands, |
| 20599 | /* 56587 */ // GIR_Coverage, 1402, |
| 20600 | /* 56587 */ GIR_EraseRootFromParent_Done, |
| 20601 | /* 56588 */ // Label 1701: @56588 |
| 20602 | /* 56588 */ GIM_Reject, |
| 20603 | /* 56589 */ // Label 1699: @56589 |
| 20604 | /* 56589 */ GIM_Reject, |
| 20605 | /* 56590 */ // Label 1694: @56590 |
| 20606 | /* 56590 */ GIM_Reject, |
| 20607 | /* 56591 */ // Label 1690: @56591 |
| 20608 | /* 56591 */ GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(56937), |
| 20609 | /* 56596 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 20610 | /* 56601 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1709*/ GIMT_Encode4(56936), |
| 20611 | /* 56612 */ /*GILLT_s64*//*Label 1703*/ GIMT_Encode4(56660), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 20612 | /* 56640 */ /*GILLT_v4s16*//*Label 1704*/ GIMT_Encode4(56706), |
| 20613 | /* 56644 */ /*GILLT_v8s16*//*Label 1705*/ GIMT_Encode4(56752), |
| 20614 | /* 56648 */ /*GILLT_v2s32*//*Label 1706*/ GIMT_Encode4(56798), |
| 20615 | /* 56652 */ /*GILLT_v4s32*//*Label 1707*/ GIMT_Encode4(56844), |
| 20616 | /* 56656 */ /*GILLT_v2s64*//*Label 1708*/ GIMT_Encode4(56890), |
| 20617 | /* 56660 */ // Label 1703: @56660 |
| 20618 | /* 56660 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1710*/ GIMT_Encode4(56705), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1418 // |
| 20619 | /* 56667 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20620 | /* 56670 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20621 | /* 56673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20622 | /* 56677 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20623 | /* 56681 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20624 | /* 56685 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4033:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALsv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) |
| 20625 | /* 56685 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv2i32), |
| 20626 | /* 56688 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20627 | /* 56690 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20628 | /* 56692 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20629 | /* 56694 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20630 | /* 56697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20631 | /* 56703 */ GIR_RootConstrainSelectedInstOperands, |
| 20632 | /* 56704 */ // GIR_Coverage, 1418, |
| 20633 | /* 56704 */ GIR_EraseRootFromParent_Done, |
| 20634 | /* 56705 */ // Label 1710: @56705 |
| 20635 | /* 56705 */ GIM_Reject, |
| 20636 | /* 56706 */ // Label 1704: @56706 |
| 20637 | /* 56706 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1711*/ GIMT_Encode4(56751), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1416 // |
| 20638 | /* 56713 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20639 | /* 56716 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20640 | /* 56719 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20641 | /* 56723 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20642 | /* 56727 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20643 | /* 56731 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4033:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALsv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) |
| 20644 | /* 56731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i8), |
| 20645 | /* 56734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20646 | /* 56736 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20647 | /* 56738 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20648 | /* 56740 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20649 | /* 56743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20650 | /* 56749 */ GIR_RootConstrainSelectedInstOperands, |
| 20651 | /* 56750 */ // GIR_Coverage, 1416, |
| 20652 | /* 56750 */ GIR_EraseRootFromParent_Done, |
| 20653 | /* 56751 */ // Label 1711: @56751 |
| 20654 | /* 56751 */ GIM_Reject, |
| 20655 | /* 56752 */ // Label 1705: @56752 |
| 20656 | /* 56752 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1712*/ GIMT_Encode4(56797), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1419 // |
| 20657 | /* 56759 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20658 | /* 56762 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20659 | /* 56765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20660 | /* 56769 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20661 | /* 56773 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20662 | /* 56777 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4033:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALsv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) |
| 20663 | /* 56777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv16i8), |
| 20664 | /* 56780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20665 | /* 56782 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20666 | /* 56784 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20667 | /* 56786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20668 | /* 56789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20669 | /* 56795 */ GIR_RootConstrainSelectedInstOperands, |
| 20670 | /* 56796 */ // GIR_Coverage, 1419, |
| 20671 | /* 56796 */ GIR_EraseRootFromParent_Done, |
| 20672 | /* 56797 */ // Label 1712: @56797 |
| 20673 | /* 56797 */ GIM_Reject, |
| 20674 | /* 56798 */ // Label 1706: @56798 |
| 20675 | /* 56798 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1713*/ GIMT_Encode4(56843), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1417 // |
| 20676 | /* 56805 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20677 | /* 56808 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20678 | /* 56811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20679 | /* 56815 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20680 | /* 56819 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20681 | /* 56823 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4033:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALsv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) |
| 20682 | /* 56823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i16), |
| 20683 | /* 56826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20684 | /* 56828 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20685 | /* 56830 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20686 | /* 56832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20687 | /* 56835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20688 | /* 56841 */ GIR_RootConstrainSelectedInstOperands, |
| 20689 | /* 56842 */ // GIR_Coverage, 1417, |
| 20690 | /* 56842 */ GIR_EraseRootFromParent_Done, |
| 20691 | /* 56843 */ // Label 1713: @56843 |
| 20692 | /* 56843 */ GIM_Reject, |
| 20693 | /* 56844 */ // Label 1707: @56844 |
| 20694 | /* 56844 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1714*/ GIMT_Encode4(56889), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1420 // |
| 20695 | /* 56851 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20696 | /* 56854 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20697 | /* 56857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20698 | /* 56861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20699 | /* 56865 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20700 | /* 56869 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4033:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALsv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) |
| 20701 | /* 56869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i16), |
| 20702 | /* 56872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20703 | /* 56874 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20704 | /* 56876 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20705 | /* 56878 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20706 | /* 56881 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20707 | /* 56887 */ GIR_RootConstrainSelectedInstOperands, |
| 20708 | /* 56888 */ // GIR_Coverage, 1420, |
| 20709 | /* 56888 */ GIR_EraseRootFromParent_Done, |
| 20710 | /* 56889 */ // Label 1714: @56889 |
| 20711 | /* 56889 */ GIM_Reject, |
| 20712 | /* 56890 */ // Label 1708: @56890 |
| 20713 | /* 56890 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1715*/ GIMT_Encode4(56935), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1421 // |
| 20714 | /* 56897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20715 | /* 56900 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20716 | /* 56903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20717 | /* 56907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20718 | /* 56911 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20719 | /* 56915 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4033:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALsv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) |
| 20720 | /* 56915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i32), |
| 20721 | /* 56918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20722 | /* 56920 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20723 | /* 56922 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20724 | /* 56924 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20725 | /* 56927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20726 | /* 56933 */ GIR_RootConstrainSelectedInstOperands, |
| 20727 | /* 56934 */ // GIR_Coverage, 1421, |
| 20728 | /* 56934 */ GIR_EraseRootFromParent_Done, |
| 20729 | /* 56935 */ // Label 1715: @56935 |
| 20730 | /* 56935 */ GIM_Reject, |
| 20731 | /* 56936 */ // Label 1709: @56936 |
| 20732 | /* 56936 */ GIM_Reject, |
| 20733 | /* 56937 */ // Label 1702: @56937 |
| 20734 | /* 56937 */ GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(57283), |
| 20735 | /* 56942 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 20736 | /* 56947 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1723*/ GIMT_Encode4(57282), |
| 20737 | /* 56958 */ /*GILLT_s64*//*Label 1717*/ GIMT_Encode4(57006), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 20738 | /* 56986 */ /*GILLT_v4s16*//*Label 1718*/ GIMT_Encode4(57052), |
| 20739 | /* 56990 */ /*GILLT_v8s16*//*Label 1719*/ GIMT_Encode4(57098), |
| 20740 | /* 56994 */ /*GILLT_v2s32*//*Label 1720*/ GIMT_Encode4(57144), |
| 20741 | /* 56998 */ /*GILLT_v4s32*//*Label 1721*/ GIMT_Encode4(57190), |
| 20742 | /* 57002 */ /*GILLT_v2s64*//*Label 1722*/ GIMT_Encode4(57236), |
| 20743 | /* 57006 */ // Label 1717: @57006 |
| 20744 | /* 57006 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1724*/ GIMT_Encode4(57051), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1424 // |
| 20745 | /* 57013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20746 | /* 57016 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20747 | /* 57019 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20748 | /* 57023 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20749 | /* 57027 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20750 | /* 57031 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4034:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALuv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) |
| 20751 | /* 57031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv2i32), |
| 20752 | /* 57034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20753 | /* 57036 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20754 | /* 57038 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20755 | /* 57040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20756 | /* 57043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20757 | /* 57049 */ GIR_RootConstrainSelectedInstOperands, |
| 20758 | /* 57050 */ // GIR_Coverage, 1424, |
| 20759 | /* 57050 */ GIR_EraseRootFromParent_Done, |
| 20760 | /* 57051 */ // Label 1724: @57051 |
| 20761 | /* 57051 */ GIM_Reject, |
| 20762 | /* 57052 */ // Label 1718: @57052 |
| 20763 | /* 57052 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1725*/ GIMT_Encode4(57097), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1422 // |
| 20764 | /* 57059 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20765 | /* 57062 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20766 | /* 57065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20767 | /* 57069 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20768 | /* 57073 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20769 | /* 57077 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4034:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALuv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) |
| 20770 | /* 57077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i8), |
| 20771 | /* 57080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20772 | /* 57082 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20773 | /* 57084 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20774 | /* 57086 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20775 | /* 57089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20776 | /* 57095 */ GIR_RootConstrainSelectedInstOperands, |
| 20777 | /* 57096 */ // GIR_Coverage, 1422, |
| 20778 | /* 57096 */ GIR_EraseRootFromParent_Done, |
| 20779 | /* 57097 */ // Label 1725: @57097 |
| 20780 | /* 57097 */ GIM_Reject, |
| 20781 | /* 57098 */ // Label 1719: @57098 |
| 20782 | /* 57098 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1726*/ GIMT_Encode4(57143), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1425 // |
| 20783 | /* 57105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20784 | /* 57108 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20785 | /* 57111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20786 | /* 57115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20787 | /* 57119 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20788 | /* 57123 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4034:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALuv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) |
| 20789 | /* 57123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv16i8), |
| 20790 | /* 57126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20791 | /* 57128 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20792 | /* 57130 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20793 | /* 57132 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20794 | /* 57135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20795 | /* 57141 */ GIR_RootConstrainSelectedInstOperands, |
| 20796 | /* 57142 */ // GIR_Coverage, 1425, |
| 20797 | /* 57142 */ GIR_EraseRootFromParent_Done, |
| 20798 | /* 57143 */ // Label 1726: @57143 |
| 20799 | /* 57143 */ GIM_Reject, |
| 20800 | /* 57144 */ // Label 1720: @57144 |
| 20801 | /* 57144 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1727*/ GIMT_Encode4(57189), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1423 // |
| 20802 | /* 57151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20803 | /* 57154 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20804 | /* 57157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20805 | /* 57161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20806 | /* 57165 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20807 | /* 57169 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4034:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALuv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) |
| 20808 | /* 57169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i16), |
| 20809 | /* 57172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20810 | /* 57174 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20811 | /* 57176 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20812 | /* 57178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20813 | /* 57181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20814 | /* 57187 */ GIR_RootConstrainSelectedInstOperands, |
| 20815 | /* 57188 */ // GIR_Coverage, 1423, |
| 20816 | /* 57188 */ GIR_EraseRootFromParent_Done, |
| 20817 | /* 57189 */ // Label 1727: @57189 |
| 20818 | /* 57189 */ GIM_Reject, |
| 20819 | /* 57190 */ // Label 1721: @57190 |
| 20820 | /* 57190 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1728*/ GIMT_Encode4(57235), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1426 // |
| 20821 | /* 57197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20822 | /* 57200 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20823 | /* 57203 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20824 | /* 57207 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20825 | /* 57211 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20826 | /* 57215 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4034:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALuv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) |
| 20827 | /* 57215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i16), |
| 20828 | /* 57218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20829 | /* 57220 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20830 | /* 57222 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20831 | /* 57224 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20832 | /* 57227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20833 | /* 57233 */ GIR_RootConstrainSelectedInstOperands, |
| 20834 | /* 57234 */ // GIR_Coverage, 1426, |
| 20835 | /* 57234 */ GIR_EraseRootFromParent_Done, |
| 20836 | /* 57235 */ // Label 1728: @57235 |
| 20837 | /* 57235 */ GIM_Reject, |
| 20838 | /* 57236 */ // Label 1722: @57236 |
| 20839 | /* 57236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1729*/ GIMT_Encode4(57281), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1427 // |
| 20840 | /* 57243 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20841 | /* 57246 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20842 | /* 57249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20843 | /* 57253 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20844 | /* 57257 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20845 | /* 57261 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4034:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALuv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) |
| 20846 | /* 57261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i32), |
| 20847 | /* 57264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20848 | /* 57266 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20849 | /* 57268 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20850 | /* 57270 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20851 | /* 57273 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20852 | /* 57279 */ GIR_RootConstrainSelectedInstOperands, |
| 20853 | /* 57280 */ // GIR_Coverage, 1427, |
| 20854 | /* 57280 */ GIR_EraseRootFromParent_Done, |
| 20855 | /* 57281 */ // Label 1729: @57281 |
| 20856 | /* 57281 */ GIM_Reject, |
| 20857 | /* 57282 */ // Label 1723: @57282 |
| 20858 | /* 57282 */ GIM_Reject, |
| 20859 | /* 57283 */ // Label 1716: @57283 |
| 20860 | /* 57283 */ GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(57463), |
| 20861 | /* 57288 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 20862 | /* 57293 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1734*/ GIMT_Encode4(57462), |
| 20863 | /* 57304 */ /*GILLT_v8s8*//*Label 1731*/ GIMT_Encode4(57324), GIMT_Encode4(0), |
| 20864 | /* 57312 */ /*GILLT_v4s16*//*Label 1732*/ GIMT_Encode4(57370), GIMT_Encode4(0), |
| 20865 | /* 57320 */ /*GILLT_v2s32*//*Label 1733*/ GIMT_Encode4(57416), |
| 20866 | /* 57324 */ // Label 1731: @57324 |
| 20867 | /* 57324 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1735*/ GIMT_Encode4(57369), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1428 // |
| 20868 | /* 57331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20869 | /* 57334 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20870 | /* 57337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20871 | /* 57341 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20872 | /* 57345 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20873 | /* 57349 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4038:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 20874 | /* 57349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs8), |
| 20875 | /* 57352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20876 | /* 57354 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20877 | /* 57356 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20878 | /* 57358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20879 | /* 57361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20880 | /* 57367 */ GIR_RootConstrainSelectedInstOperands, |
| 20881 | /* 57368 */ // GIR_Coverage, 1428, |
| 20882 | /* 57368 */ GIR_EraseRootFromParent_Done, |
| 20883 | /* 57369 */ // Label 1735: @57369 |
| 20884 | /* 57369 */ GIM_Reject, |
| 20885 | /* 57370 */ // Label 1732: @57370 |
| 20886 | /* 57370 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1736*/ GIMT_Encode4(57415), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1429 // |
| 20887 | /* 57377 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20888 | /* 57380 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20889 | /* 57383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20890 | /* 57387 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20891 | /* 57391 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20892 | /* 57395 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4038:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20893 | /* 57395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs16), |
| 20894 | /* 57398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20895 | /* 57400 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20896 | /* 57402 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20897 | /* 57404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20898 | /* 57407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20899 | /* 57413 */ GIR_RootConstrainSelectedInstOperands, |
| 20900 | /* 57414 */ // GIR_Coverage, 1429, |
| 20901 | /* 57414 */ GIR_EraseRootFromParent_Done, |
| 20902 | /* 57415 */ // Label 1736: @57415 |
| 20903 | /* 57415 */ GIM_Reject, |
| 20904 | /* 57416 */ // Label 1733: @57416 |
| 20905 | /* 57416 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1737*/ GIMT_Encode4(57461), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1430 // |
| 20906 | /* 57423 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20907 | /* 57426 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20908 | /* 57429 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20909 | /* 57433 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20910 | /* 57437 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20911 | /* 57441 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4038:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20912 | /* 57441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs32), |
| 20913 | /* 57444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20914 | /* 57446 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20915 | /* 57448 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20916 | /* 57450 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20917 | /* 57453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20918 | /* 57459 */ GIR_RootConstrainSelectedInstOperands, |
| 20919 | /* 57460 */ // GIR_Coverage, 1430, |
| 20920 | /* 57460 */ GIR_EraseRootFromParent_Done, |
| 20921 | /* 57461 */ // Label 1737: @57461 |
| 20922 | /* 57461 */ GIM_Reject, |
| 20923 | /* 57462 */ // Label 1734: @57462 |
| 20924 | /* 57462 */ GIM_Reject, |
| 20925 | /* 57463 */ // Label 1730: @57463 |
| 20926 | /* 57463 */ GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(57643), |
| 20927 | /* 57468 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu), |
| 20928 | /* 57473 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1742*/ GIMT_Encode4(57642), |
| 20929 | /* 57484 */ /*GILLT_v8s8*//*Label 1739*/ GIMT_Encode4(57504), GIMT_Encode4(0), |
| 20930 | /* 57492 */ /*GILLT_v4s16*//*Label 1740*/ GIMT_Encode4(57550), GIMT_Encode4(0), |
| 20931 | /* 57500 */ /*GILLT_v2s32*//*Label 1741*/ GIMT_Encode4(57596), |
| 20932 | /* 57504 */ // Label 1739: @57504 |
| 20933 | /* 57504 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1743*/ GIMT_Encode4(57549), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1431 // |
| 20934 | /* 57511 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20935 | /* 57514 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20936 | /* 57517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20937 | /* 57521 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20938 | /* 57525 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20939 | /* 57529 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4039:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 20940 | /* 57529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu8), |
| 20941 | /* 57532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20942 | /* 57534 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20943 | /* 57536 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20944 | /* 57538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20945 | /* 57541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20946 | /* 57547 */ GIR_RootConstrainSelectedInstOperands, |
| 20947 | /* 57548 */ // GIR_Coverage, 1431, |
| 20948 | /* 57548 */ GIR_EraseRootFromParent_Done, |
| 20949 | /* 57549 */ // Label 1743: @57549 |
| 20950 | /* 57549 */ GIM_Reject, |
| 20951 | /* 57550 */ // Label 1740: @57550 |
| 20952 | /* 57550 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1744*/ GIMT_Encode4(57595), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1432 // |
| 20953 | /* 57557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20954 | /* 57560 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20955 | /* 57563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20956 | /* 57567 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20957 | /* 57571 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20958 | /* 57575 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4039:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20959 | /* 57575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu16), |
| 20960 | /* 57578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20961 | /* 57580 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20962 | /* 57582 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20963 | /* 57584 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20964 | /* 57587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20965 | /* 57593 */ GIR_RootConstrainSelectedInstOperands, |
| 20966 | /* 57594 */ // GIR_Coverage, 1432, |
| 20967 | /* 57594 */ GIR_EraseRootFromParent_Done, |
| 20968 | /* 57595 */ // Label 1744: @57595 |
| 20969 | /* 57595 */ GIM_Reject, |
| 20970 | /* 57596 */ // Label 1741: @57596 |
| 20971 | /* 57596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1745*/ GIMT_Encode4(57641), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1433 // |
| 20972 | /* 57603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20973 | /* 57606 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20974 | /* 57609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20975 | /* 57613 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20976 | /* 57617 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20977 | /* 57621 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4039:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20978 | /* 57621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu32), |
| 20979 | /* 57624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20980 | /* 57626 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20981 | /* 57628 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20982 | /* 57630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20983 | /* 57633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20984 | /* 57639 */ GIR_RootConstrainSelectedInstOperands, |
| 20985 | /* 57640 */ // GIR_Coverage, 1433, |
| 20986 | /* 57640 */ GIR_EraseRootFromParent_Done, |
| 20987 | /* 57641 */ // Label 1745: @57641 |
| 20988 | /* 57641 */ GIM_Reject, |
| 20989 | /* 57642 */ // Label 1742: @57642 |
| 20990 | /* 57642 */ GIM_Reject, |
| 20991 | /* 57643 */ // Label 1738: @57643 |
| 20992 | /* 57643 */ GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(57769), |
| 20993 | /* 57648 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 20994 | /* 57653 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 1749*/ GIMT_Encode4(57768), |
| 20995 | /* 57664 */ /*GILLT_v4s16*//*Label 1747*/ GIMT_Encode4(57676), GIMT_Encode4(0), |
| 20996 | /* 57672 */ /*GILLT_v2s32*//*Label 1748*/ GIMT_Encode4(57722), |
| 20997 | /* 57676 */ // Label 1747: @57676 |
| 20998 | /* 57676 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1750*/ GIMT_Encode4(57721), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1435 // |
| 20999 | /* 57683 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21000 | /* 57686 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21001 | /* 57689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21002 | /* 57693 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21003 | /* 57697 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21004 | /* 57701 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4038:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMAXh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 21005 | /* 57701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXh), |
| 21006 | /* 57704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21007 | /* 57706 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21008 | /* 57708 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21009 | /* 57710 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21010 | /* 57713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21011 | /* 57719 */ GIR_RootConstrainSelectedInstOperands, |
| 21012 | /* 57720 */ // GIR_Coverage, 1435, |
| 21013 | /* 57720 */ GIR_EraseRootFromParent_Done, |
| 21014 | /* 57721 */ // Label 1750: @57721 |
| 21015 | /* 57721 */ GIM_Reject, |
| 21016 | /* 57722 */ // Label 1748: @57722 |
| 21017 | /* 57722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1751*/ GIMT_Encode4(57767), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1434 // |
| 21018 | /* 57729 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21019 | /* 57732 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21020 | /* 57735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21021 | /* 57739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21022 | /* 57743 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21023 | /* 57747 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4038:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMAXf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 21024 | /* 57747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXf), |
| 21025 | /* 57750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21026 | /* 57752 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21027 | /* 57754 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21028 | /* 57756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21029 | /* 57759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21030 | /* 57765 */ GIR_RootConstrainSelectedInstOperands, |
| 21031 | /* 57766 */ // GIR_Coverage, 1434, |
| 21032 | /* 57766 */ GIR_EraseRootFromParent_Done, |
| 21033 | /* 57767 */ // Label 1751: @57767 |
| 21034 | /* 57767 */ GIM_Reject, |
| 21035 | /* 57768 */ // Label 1749: @57768 |
| 21036 | /* 57768 */ GIM_Reject, |
| 21037 | /* 57769 */ // Label 1746: @57769 |
| 21038 | /* 57769 */ GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(57949), |
| 21039 | /* 57774 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 21040 | /* 57779 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1756*/ GIMT_Encode4(57948), |
| 21041 | /* 57790 */ /*GILLT_v8s8*//*Label 1753*/ GIMT_Encode4(57810), GIMT_Encode4(0), |
| 21042 | /* 57798 */ /*GILLT_v4s16*//*Label 1754*/ GIMT_Encode4(57856), GIMT_Encode4(0), |
| 21043 | /* 57806 */ /*GILLT_v2s32*//*Label 1755*/ GIMT_Encode4(57902), |
| 21044 | /* 57810 */ // Label 1753: @57810 |
| 21045 | /* 57810 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1757*/ GIMT_Encode4(57855), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1436 // |
| 21046 | /* 57817 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21047 | /* 57820 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21048 | /* 57823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21049 | /* 57827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21050 | /* 57831 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21051 | /* 57835 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4040:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 21052 | /* 57835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs8), |
| 21053 | /* 57838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21054 | /* 57840 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21055 | /* 57842 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21056 | /* 57844 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21057 | /* 57847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21058 | /* 57853 */ GIR_RootConstrainSelectedInstOperands, |
| 21059 | /* 57854 */ // GIR_Coverage, 1436, |
| 21060 | /* 57854 */ GIR_EraseRootFromParent_Done, |
| 21061 | /* 57855 */ // Label 1757: @57855 |
| 21062 | /* 57855 */ GIM_Reject, |
| 21063 | /* 57856 */ // Label 1754: @57856 |
| 21064 | /* 57856 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1758*/ GIMT_Encode4(57901), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1437 // |
| 21065 | /* 57863 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21066 | /* 57866 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21067 | /* 57869 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21068 | /* 57873 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21069 | /* 57877 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21070 | /* 57881 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4040:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 21071 | /* 57881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs16), |
| 21072 | /* 57884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21073 | /* 57886 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21074 | /* 57888 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21075 | /* 57890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21076 | /* 57893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21077 | /* 57899 */ GIR_RootConstrainSelectedInstOperands, |
| 21078 | /* 57900 */ // GIR_Coverage, 1437, |
| 21079 | /* 57900 */ GIR_EraseRootFromParent_Done, |
| 21080 | /* 57901 */ // Label 1758: @57901 |
| 21081 | /* 57901 */ GIM_Reject, |
| 21082 | /* 57902 */ // Label 1755: @57902 |
| 21083 | /* 57902 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1759*/ GIMT_Encode4(57947), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1438 // |
| 21084 | /* 57909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21085 | /* 57912 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21086 | /* 57915 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21087 | /* 57919 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21088 | /* 57923 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21089 | /* 57927 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4040:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 21090 | /* 57927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs32), |
| 21091 | /* 57930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21092 | /* 57932 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21093 | /* 57934 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21094 | /* 57936 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21095 | /* 57939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21096 | /* 57945 */ GIR_RootConstrainSelectedInstOperands, |
| 21097 | /* 57946 */ // GIR_Coverage, 1438, |
| 21098 | /* 57946 */ GIR_EraseRootFromParent_Done, |
| 21099 | /* 57947 */ // Label 1759: @57947 |
| 21100 | /* 57947 */ GIM_Reject, |
| 21101 | /* 57948 */ // Label 1756: @57948 |
| 21102 | /* 57948 */ GIM_Reject, |
| 21103 | /* 57949 */ // Label 1752: @57949 |
| 21104 | /* 57949 */ GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(58129), |
| 21105 | /* 57954 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu), |
| 21106 | /* 57959 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1764*/ GIMT_Encode4(58128), |
| 21107 | /* 57970 */ /*GILLT_v8s8*//*Label 1761*/ GIMT_Encode4(57990), GIMT_Encode4(0), |
| 21108 | /* 57978 */ /*GILLT_v4s16*//*Label 1762*/ GIMT_Encode4(58036), GIMT_Encode4(0), |
| 21109 | /* 57986 */ /*GILLT_v2s32*//*Label 1763*/ GIMT_Encode4(58082), |
| 21110 | /* 57990 */ // Label 1761: @57990 |
| 21111 | /* 57990 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1765*/ GIMT_Encode4(58035), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1439 // |
| 21112 | /* 57997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21113 | /* 58000 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21114 | /* 58003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21115 | /* 58007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21116 | /* 58011 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21117 | /* 58015 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4041:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 21118 | /* 58015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu8), |
| 21119 | /* 58018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21120 | /* 58020 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21121 | /* 58022 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21122 | /* 58024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21123 | /* 58027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21124 | /* 58033 */ GIR_RootConstrainSelectedInstOperands, |
| 21125 | /* 58034 */ // GIR_Coverage, 1439, |
| 21126 | /* 58034 */ GIR_EraseRootFromParent_Done, |
| 21127 | /* 58035 */ // Label 1765: @58035 |
| 21128 | /* 58035 */ GIM_Reject, |
| 21129 | /* 58036 */ // Label 1762: @58036 |
| 21130 | /* 58036 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1766*/ GIMT_Encode4(58081), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1440 // |
| 21131 | /* 58043 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21132 | /* 58046 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21133 | /* 58049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21134 | /* 58053 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21135 | /* 58057 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21136 | /* 58061 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4041:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 21137 | /* 58061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu16), |
| 21138 | /* 58064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21139 | /* 58066 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21140 | /* 58068 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21141 | /* 58070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21142 | /* 58073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21143 | /* 58079 */ GIR_RootConstrainSelectedInstOperands, |
| 21144 | /* 58080 */ // GIR_Coverage, 1440, |
| 21145 | /* 58080 */ GIR_EraseRootFromParent_Done, |
| 21146 | /* 58081 */ // Label 1766: @58081 |
| 21147 | /* 58081 */ GIM_Reject, |
| 21148 | /* 58082 */ // Label 1763: @58082 |
| 21149 | /* 58082 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1767*/ GIMT_Encode4(58127), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1441 // |
| 21150 | /* 58089 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21151 | /* 58092 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21152 | /* 58095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21153 | /* 58099 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21154 | /* 58103 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21155 | /* 58107 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4041:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 21156 | /* 58107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu32), |
| 21157 | /* 58110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21158 | /* 58112 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21159 | /* 58114 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21160 | /* 58116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21161 | /* 58119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21162 | /* 58125 */ GIR_RootConstrainSelectedInstOperands, |
| 21163 | /* 58126 */ // GIR_Coverage, 1441, |
| 21164 | /* 58126 */ GIR_EraseRootFromParent_Done, |
| 21165 | /* 58127 */ // Label 1767: @58127 |
| 21166 | /* 58127 */ GIM_Reject, |
| 21167 | /* 58128 */ // Label 1764: @58128 |
| 21168 | /* 58128 */ GIM_Reject, |
| 21169 | /* 58129 */ // Label 1760: @58129 |
| 21170 | /* 58129 */ GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(58255), |
| 21171 | /* 58134 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 21172 | /* 58139 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 1771*/ GIMT_Encode4(58254), |
| 21173 | /* 58150 */ /*GILLT_v4s16*//*Label 1769*/ GIMT_Encode4(58162), GIMT_Encode4(0), |
| 21174 | /* 58158 */ /*GILLT_v2s32*//*Label 1770*/ GIMT_Encode4(58208), |
| 21175 | /* 58162 */ // Label 1769: @58162 |
| 21176 | /* 58162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1772*/ GIMT_Encode4(58207), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1443 // |
| 21177 | /* 58169 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21178 | /* 58172 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21179 | /* 58175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21180 | /* 58179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21181 | /* 58183 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21182 | /* 58187 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4040:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMINh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 21183 | /* 58187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINh), |
| 21184 | /* 58190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21185 | /* 58192 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21186 | /* 58194 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21187 | /* 58196 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21188 | /* 58199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21189 | /* 58205 */ GIR_RootConstrainSelectedInstOperands, |
| 21190 | /* 58206 */ // GIR_Coverage, 1443, |
| 21191 | /* 58206 */ GIR_EraseRootFromParent_Done, |
| 21192 | /* 58207 */ // Label 1772: @58207 |
| 21193 | /* 58207 */ GIM_Reject, |
| 21194 | /* 58208 */ // Label 1770: @58208 |
| 21195 | /* 58208 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1773*/ GIMT_Encode4(58253), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1442 // |
| 21196 | /* 58215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21197 | /* 58218 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21198 | /* 58221 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21199 | /* 58225 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21200 | /* 58229 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21201 | /* 58233 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4040:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMINf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 21202 | /* 58233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINf), |
| 21203 | /* 58236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21204 | /* 58238 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21205 | /* 58240 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21206 | /* 58242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21207 | /* 58245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21208 | /* 58251 */ GIR_RootConstrainSelectedInstOperands, |
| 21209 | /* 58252 */ // GIR_Coverage, 1442, |
| 21210 | /* 58252 */ GIR_EraseRootFromParent_Done, |
| 21211 | /* 58253 */ // Label 1773: @58253 |
| 21212 | /* 58253 */ GIM_Reject, |
| 21213 | /* 58254 */ // Label 1771: @58254 |
| 21214 | /* 58254 */ GIM_Reject, |
| 21215 | /* 58255 */ // Label 1768: @58255 |
| 21216 | /* 58255 */ GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(58477), |
| 21217 | /* 58260 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps), |
| 21218 | /* 58265 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1779*/ GIMT_Encode4(58476), |
| 21219 | /* 58276 */ /*GILLT_v4s16*//*Label 1775*/ GIMT_Encode4(58292), |
| 21220 | /* 58280 */ /*GILLT_v8s16*//*Label 1776*/ GIMT_Encode4(58338), |
| 21221 | /* 58284 */ /*GILLT_v2s32*//*Label 1777*/ GIMT_Encode4(58384), |
| 21222 | /* 58288 */ /*GILLT_v4s32*//*Label 1778*/ GIMT_Encode4(58430), |
| 21223 | /* 58292 */ // Label 1775: @58292 |
| 21224 | /* 58292 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1780*/ GIMT_Encode4(58337), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1452 // |
| 21225 | /* 58299 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21226 | /* 58302 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21227 | /* 58305 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21228 | /* 58309 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21229 | /* 58313 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21230 | /* 58317 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4065:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRECPShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 21231 | /* 58317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShd), |
| 21232 | /* 58320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21233 | /* 58322 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21234 | /* 58324 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21235 | /* 58326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21236 | /* 58329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21237 | /* 58335 */ GIR_RootConstrainSelectedInstOperands, |
| 21238 | /* 58336 */ // GIR_Coverage, 1452, |
| 21239 | /* 58336 */ GIR_EraseRootFromParent_Done, |
| 21240 | /* 58337 */ // Label 1780: @58337 |
| 21241 | /* 58337 */ GIM_Reject, |
| 21242 | /* 58338 */ // Label 1776: @58338 |
| 21243 | /* 58338 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1781*/ GIMT_Encode4(58383), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1453 // |
| 21244 | /* 58345 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21245 | /* 58348 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21246 | /* 58351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21247 | /* 58355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21248 | /* 58359 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21249 | /* 58363 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4065:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRECPShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 21250 | /* 58363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShq), |
| 21251 | /* 58366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21252 | /* 58368 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21253 | /* 58370 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21254 | /* 58372 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21255 | /* 58375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21256 | /* 58381 */ GIR_RootConstrainSelectedInstOperands, |
| 21257 | /* 58382 */ // GIR_Coverage, 1453, |
| 21258 | /* 58382 */ GIR_EraseRootFromParent_Done, |
| 21259 | /* 58383 */ // Label 1781: @58383 |
| 21260 | /* 58383 */ GIM_Reject, |
| 21261 | /* 58384 */ // Label 1777: @58384 |
| 21262 | /* 58384 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1782*/ GIMT_Encode4(58429), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1450 // |
| 21263 | /* 58391 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21264 | /* 58394 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21265 | /* 58397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21266 | /* 58401 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21267 | /* 58405 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21268 | /* 58409 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4065:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRECPSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 21269 | /* 58409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfd), |
| 21270 | /* 58412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21271 | /* 58414 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21272 | /* 58416 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21273 | /* 58418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21274 | /* 58421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21275 | /* 58427 */ GIR_RootConstrainSelectedInstOperands, |
| 21276 | /* 58428 */ // GIR_Coverage, 1450, |
| 21277 | /* 58428 */ GIR_EraseRootFromParent_Done, |
| 21278 | /* 58429 */ // Label 1782: @58429 |
| 21279 | /* 58429 */ GIM_Reject, |
| 21280 | /* 58430 */ // Label 1778: @58430 |
| 21281 | /* 58430 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1783*/ GIMT_Encode4(58475), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1451 // |
| 21282 | /* 58437 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21283 | /* 58440 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21284 | /* 58443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21285 | /* 58447 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21286 | /* 58451 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21287 | /* 58455 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4065:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRECPSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 21288 | /* 58455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfq), |
| 21289 | /* 58458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21290 | /* 58460 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21291 | /* 58462 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21292 | /* 58464 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21293 | /* 58467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21294 | /* 58473 */ GIR_RootConstrainSelectedInstOperands, |
| 21295 | /* 58474 */ // GIR_Coverage, 1451, |
| 21296 | /* 58474 */ GIR_EraseRootFromParent_Done, |
| 21297 | /* 58475 */ // Label 1783: @58475 |
| 21298 | /* 58475 */ GIM_Reject, |
| 21299 | /* 58476 */ // Label 1779: @58476 |
| 21300 | /* 58476 */ GIM_Reject, |
| 21301 | /* 58477 */ // Label 1774: @58477 |
| 21302 | /* 58477 */ GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(58699), |
| 21303 | /* 58482 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts), |
| 21304 | /* 58487 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1789*/ GIMT_Encode4(58698), |
| 21305 | /* 58498 */ /*GILLT_v4s16*//*Label 1785*/ GIMT_Encode4(58514), |
| 21306 | /* 58502 */ /*GILLT_v8s16*//*Label 1786*/ GIMT_Encode4(58560), |
| 21307 | /* 58506 */ /*GILLT_v2s32*//*Label 1787*/ GIMT_Encode4(58606), |
| 21308 | /* 58510 */ /*GILLT_v4s32*//*Label 1788*/ GIMT_Encode4(58652), |
| 21309 | /* 58514 */ // Label 1785: @58514 |
| 21310 | /* 58514 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1790*/ GIMT_Encode4(58559), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1462 // |
| 21311 | /* 58521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21312 | /* 58524 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21313 | /* 58527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21314 | /* 58531 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21315 | /* 58535 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21316 | /* 58539 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4072:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 21317 | /* 58539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShd), |
| 21318 | /* 58542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21319 | /* 58544 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21320 | /* 58546 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21321 | /* 58548 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21322 | /* 58551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21323 | /* 58557 */ GIR_RootConstrainSelectedInstOperands, |
| 21324 | /* 58558 */ // GIR_Coverage, 1462, |
| 21325 | /* 58558 */ GIR_EraseRootFromParent_Done, |
| 21326 | /* 58559 */ // Label 1790: @58559 |
| 21327 | /* 58559 */ GIM_Reject, |
| 21328 | /* 58560 */ // Label 1786: @58560 |
| 21329 | /* 58560 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1791*/ GIMT_Encode4(58605), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1463 // |
| 21330 | /* 58567 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21331 | /* 58570 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21332 | /* 58573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21333 | /* 58577 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21334 | /* 58581 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21335 | /* 58585 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4072:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 21336 | /* 58585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShq), |
| 21337 | /* 58588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21338 | /* 58590 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21339 | /* 58592 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21340 | /* 58594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21341 | /* 58597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21342 | /* 58603 */ GIR_RootConstrainSelectedInstOperands, |
| 21343 | /* 58604 */ // GIR_Coverage, 1463, |
| 21344 | /* 58604 */ GIR_EraseRootFromParent_Done, |
| 21345 | /* 58605 */ // Label 1791: @58605 |
| 21346 | /* 58605 */ GIM_Reject, |
| 21347 | /* 58606 */ // Label 1787: @58606 |
| 21348 | /* 58606 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1792*/ GIMT_Encode4(58651), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1460 // |
| 21349 | /* 58613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21350 | /* 58616 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21351 | /* 58619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21352 | /* 58623 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21353 | /* 58627 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21354 | /* 58631 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4072:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 21355 | /* 58631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfd), |
| 21356 | /* 58634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21357 | /* 58636 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21358 | /* 58638 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21359 | /* 58640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21360 | /* 58643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21361 | /* 58649 */ GIR_RootConstrainSelectedInstOperands, |
| 21362 | /* 58650 */ // GIR_Coverage, 1460, |
| 21363 | /* 58650 */ GIR_EraseRootFromParent_Done, |
| 21364 | /* 58651 */ // Label 1792: @58651 |
| 21365 | /* 58651 */ GIM_Reject, |
| 21366 | /* 58652 */ // Label 1788: @58652 |
| 21367 | /* 58652 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1793*/ GIMT_Encode4(58697), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1461 // |
| 21368 | /* 58659 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21369 | /* 58662 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21370 | /* 58665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21371 | /* 58669 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21372 | /* 58673 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21373 | /* 58677 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4072:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 21374 | /* 58677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfq), |
| 21375 | /* 58680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21376 | /* 58682 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21377 | /* 58684 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21378 | /* 58686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21379 | /* 58689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21380 | /* 58695 */ GIR_RootConstrainSelectedInstOperands, |
| 21381 | /* 58696 */ // GIR_Coverage, 1461, |
| 21382 | /* 58696 */ GIR_EraseRootFromParent_Done, |
| 21383 | /* 58697 */ // Label 1793: @58697 |
| 21384 | /* 58697 */ GIM_Reject, |
| 21385 | /* 58698 */ // Label 1789: @58698 |
| 21386 | /* 58698 */ GIM_Reject, |
| 21387 | /* 58699 */ // Label 1784: @58699 |
| 21388 | /* 58699 */ GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(59137), |
| 21389 | /* 58704 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 21390 | /* 58709 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1803*/ GIMT_Encode4(59136), |
| 21391 | /* 58720 */ /*GILLT_s64*//*Label 1795*/ GIMT_Encode4(58768), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 21392 | /* 58740 */ /*GILLT_v8s8*//*Label 1796*/ GIMT_Encode4(58814), |
| 21393 | /* 58744 */ /*GILLT_v16s8*//*Label 1797*/ GIMT_Encode4(58860), |
| 21394 | /* 58748 */ /*GILLT_v4s16*//*Label 1798*/ GIMT_Encode4(58906), |
| 21395 | /* 58752 */ /*GILLT_v8s16*//*Label 1799*/ GIMT_Encode4(58952), |
| 21396 | /* 58756 */ /*GILLT_v2s32*//*Label 1800*/ GIMT_Encode4(58998), |
| 21397 | /* 58760 */ /*GILLT_v4s32*//*Label 1801*/ GIMT_Encode4(59044), |
| 21398 | /* 58764 */ /*GILLT_v2s64*//*Label 1802*/ GIMT_Encode4(59090), |
| 21399 | /* 58768 */ // Label 1795: @58768 |
| 21400 | /* 58768 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1804*/ GIMT_Encode4(58813), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1470 // |
| 21401 | /* 58775 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 21402 | /* 58778 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 21403 | /* 58781 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21404 | /* 58785 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21405 | /* 58789 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21406 | /* 58793 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4075:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 21407 | /* 58793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv1i64), |
| 21408 | /* 58796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21409 | /* 58798 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21410 | /* 58800 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21411 | /* 58802 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21412 | /* 58805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21413 | /* 58811 */ GIR_RootConstrainSelectedInstOperands, |
| 21414 | /* 58812 */ // GIR_Coverage, 1470, |
| 21415 | /* 58812 */ GIR_EraseRootFromParent_Done, |
| 21416 | /* 58813 */ // Label 1804: @58813 |
| 21417 | /* 58813 */ GIM_Reject, |
| 21418 | /* 58814 */ // Label 1796: @58814 |
| 21419 | /* 58814 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1805*/ GIMT_Encode4(58859), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1468 // |
| 21420 | /* 58821 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21421 | /* 58824 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21422 | /* 58827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21423 | /* 58831 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21424 | /* 58835 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21425 | /* 58839 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4075:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 21426 | /* 58839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i8), |
| 21427 | /* 58842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21428 | /* 58844 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21429 | /* 58846 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21430 | /* 58848 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21431 | /* 58851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21432 | /* 58857 */ GIR_RootConstrainSelectedInstOperands, |
| 21433 | /* 58858 */ // GIR_Coverage, 1468, |
| 21434 | /* 58858 */ GIR_EraseRootFromParent_Done, |
| 21435 | /* 58859 */ // Label 1805: @58859 |
| 21436 | /* 58859 */ GIM_Reject, |
| 21437 | /* 58860 */ // Label 1797: @58860 |
| 21438 | /* 58860 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1806*/ GIMT_Encode4(58905), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1469 // |
| 21439 | /* 58867 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21440 | /* 58870 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21441 | /* 58873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21442 | /* 58877 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21443 | /* 58881 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21444 | /* 58885 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4075:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 21445 | /* 58885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv16i8), |
| 21446 | /* 58888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21447 | /* 58890 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21448 | /* 58892 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21449 | /* 58894 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21450 | /* 58897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21451 | /* 58903 */ GIR_RootConstrainSelectedInstOperands, |
| 21452 | /* 58904 */ // GIR_Coverage, 1469, |
| 21453 | /* 58904 */ GIR_EraseRootFromParent_Done, |
| 21454 | /* 58905 */ // Label 1806: @58905 |
| 21455 | /* 58905 */ GIM_Reject, |
| 21456 | /* 58906 */ // Label 1798: @58906 |
| 21457 | /* 58906 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1807*/ GIMT_Encode4(58951), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1464 // |
| 21458 | /* 58913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21459 | /* 58916 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21460 | /* 58919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21461 | /* 58923 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21462 | /* 58927 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21463 | /* 58931 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4075:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 21464 | /* 58931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i16), |
| 21465 | /* 58934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21466 | /* 58936 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21467 | /* 58938 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21468 | /* 58940 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21469 | /* 58943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21470 | /* 58949 */ GIR_RootConstrainSelectedInstOperands, |
| 21471 | /* 58950 */ // GIR_Coverage, 1464, |
| 21472 | /* 58950 */ GIR_EraseRootFromParent_Done, |
| 21473 | /* 58951 */ // Label 1807: @58951 |
| 21474 | /* 58951 */ GIM_Reject, |
| 21475 | /* 58952 */ // Label 1799: @58952 |
| 21476 | /* 58952 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1808*/ GIMT_Encode4(58997), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1466 // |
| 21477 | /* 58959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21478 | /* 58962 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21479 | /* 58965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21480 | /* 58969 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21481 | /* 58973 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21482 | /* 58977 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4075:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 21483 | /* 58977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i16), |
| 21484 | /* 58980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21485 | /* 58982 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21486 | /* 58984 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21487 | /* 58986 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21488 | /* 58989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21489 | /* 58995 */ GIR_RootConstrainSelectedInstOperands, |
| 21490 | /* 58996 */ // GIR_Coverage, 1466, |
| 21491 | /* 58996 */ GIR_EraseRootFromParent_Done, |
| 21492 | /* 58997 */ // Label 1808: @58997 |
| 21493 | /* 58997 */ GIM_Reject, |
| 21494 | /* 58998 */ // Label 1800: @58998 |
| 21495 | /* 58998 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1809*/ GIMT_Encode4(59043), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1465 // |
| 21496 | /* 59005 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21497 | /* 59008 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21498 | /* 59011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21499 | /* 59015 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21500 | /* 59019 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21501 | /* 59023 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4075:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 21502 | /* 59023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i32), |
| 21503 | /* 59026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21504 | /* 59028 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21505 | /* 59030 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21506 | /* 59032 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21507 | /* 59035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21508 | /* 59041 */ GIR_RootConstrainSelectedInstOperands, |
| 21509 | /* 59042 */ // GIR_Coverage, 1465, |
| 21510 | /* 59042 */ GIR_EraseRootFromParent_Done, |
| 21511 | /* 59043 */ // Label 1809: @59043 |
| 21512 | /* 59043 */ GIM_Reject, |
| 21513 | /* 59044 */ // Label 1801: @59044 |
| 21514 | /* 59044 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1810*/ GIMT_Encode4(59089), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1467 // |
| 21515 | /* 59051 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21516 | /* 59054 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21517 | /* 59057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21518 | /* 59061 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21519 | /* 59065 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21520 | /* 59069 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4075:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 21521 | /* 59069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i32), |
| 21522 | /* 59072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21523 | /* 59074 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21524 | /* 59076 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21525 | /* 59078 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21526 | /* 59081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21527 | /* 59087 */ GIR_RootConstrainSelectedInstOperands, |
| 21528 | /* 59088 */ // GIR_Coverage, 1467, |
| 21529 | /* 59088 */ GIR_EraseRootFromParent_Done, |
| 21530 | /* 59089 */ // Label 1810: @59089 |
| 21531 | /* 59089 */ GIM_Reject, |
| 21532 | /* 59090 */ // Label 1802: @59090 |
| 21533 | /* 59090 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1811*/ GIMT_Encode4(59135), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1471 // |
| 21534 | /* 59097 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21535 | /* 59100 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 21536 | /* 59103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21537 | /* 59107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21538 | /* 59111 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21539 | /* 59115 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4075:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 21540 | /* 59115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i64), |
| 21541 | /* 59118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21542 | /* 59120 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21543 | /* 59122 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21544 | /* 59124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21545 | /* 59127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21546 | /* 59133 */ GIR_RootConstrainSelectedInstOperands, |
| 21547 | /* 59134 */ // GIR_Coverage, 1471, |
| 21548 | /* 59134 */ GIR_EraseRootFromParent_Done, |
| 21549 | /* 59135 */ // Label 1811: @59135 |
| 21550 | /* 59135 */ GIM_Reject, |
| 21551 | /* 59136 */ // Label 1803: @59136 |
| 21552 | /* 59136 */ GIM_Reject, |
| 21553 | /* 59137 */ // Label 1794: @59137 |
| 21554 | /* 59137 */ GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(59575), |
| 21555 | /* 59142 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 21556 | /* 59147 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1821*/ GIMT_Encode4(59574), |
| 21557 | /* 59158 */ /*GILLT_s64*//*Label 1813*/ GIMT_Encode4(59206), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 21558 | /* 59178 */ /*GILLT_v8s8*//*Label 1814*/ GIMT_Encode4(59252), |
| 21559 | /* 59182 */ /*GILLT_v16s8*//*Label 1815*/ GIMT_Encode4(59298), |
| 21560 | /* 59186 */ /*GILLT_v4s16*//*Label 1816*/ GIMT_Encode4(59344), |
| 21561 | /* 59190 */ /*GILLT_v8s16*//*Label 1817*/ GIMT_Encode4(59390), |
| 21562 | /* 59194 */ /*GILLT_v2s32*//*Label 1818*/ GIMT_Encode4(59436), |
| 21563 | /* 59198 */ /*GILLT_v4s32*//*Label 1819*/ GIMT_Encode4(59482), |
| 21564 | /* 59202 */ /*GILLT_v2s64*//*Label 1820*/ GIMT_Encode4(59528), |
| 21565 | /* 59206 */ // Label 1813: @59206 |
| 21566 | /* 59206 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1822*/ GIMT_Encode4(59251), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1478 // |
| 21567 | /* 59213 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 21568 | /* 59216 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 21569 | /* 59219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21570 | /* 59223 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21571 | /* 59227 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21572 | /* 59231 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4076:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 21573 | /* 59231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv1i64), |
| 21574 | /* 59234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21575 | /* 59236 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21576 | /* 59238 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21577 | /* 59240 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21578 | /* 59243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21579 | /* 59249 */ GIR_RootConstrainSelectedInstOperands, |
| 21580 | /* 59250 */ // GIR_Coverage, 1478, |
| 21581 | /* 59250 */ GIR_EraseRootFromParent_Done, |
| 21582 | /* 59251 */ // Label 1822: @59251 |
| 21583 | /* 59251 */ GIM_Reject, |
| 21584 | /* 59252 */ // Label 1814: @59252 |
| 21585 | /* 59252 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1823*/ GIMT_Encode4(59297), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1476 // |
| 21586 | /* 59259 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21587 | /* 59262 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21588 | /* 59265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21589 | /* 59269 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21590 | /* 59273 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21591 | /* 59277 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4076:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 21592 | /* 59277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i8), |
| 21593 | /* 59280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21594 | /* 59282 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21595 | /* 59284 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21596 | /* 59286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21597 | /* 59289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21598 | /* 59295 */ GIR_RootConstrainSelectedInstOperands, |
| 21599 | /* 59296 */ // GIR_Coverage, 1476, |
| 21600 | /* 59296 */ GIR_EraseRootFromParent_Done, |
| 21601 | /* 59297 */ // Label 1823: @59297 |
| 21602 | /* 59297 */ GIM_Reject, |
| 21603 | /* 59298 */ // Label 1815: @59298 |
| 21604 | /* 59298 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1824*/ GIMT_Encode4(59343), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1477 // |
| 21605 | /* 59305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21606 | /* 59308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21607 | /* 59311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21608 | /* 59315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21609 | /* 59319 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21610 | /* 59323 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4076:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 21611 | /* 59323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv16i8), |
| 21612 | /* 59326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21613 | /* 59328 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21614 | /* 59330 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21615 | /* 59332 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21616 | /* 59335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21617 | /* 59341 */ GIR_RootConstrainSelectedInstOperands, |
| 21618 | /* 59342 */ // GIR_Coverage, 1477, |
| 21619 | /* 59342 */ GIR_EraseRootFromParent_Done, |
| 21620 | /* 59343 */ // Label 1824: @59343 |
| 21621 | /* 59343 */ GIM_Reject, |
| 21622 | /* 59344 */ // Label 1816: @59344 |
| 21623 | /* 59344 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1825*/ GIMT_Encode4(59389), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1472 // |
| 21624 | /* 59351 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21625 | /* 59354 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21626 | /* 59357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21627 | /* 59361 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21628 | /* 59365 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21629 | /* 59369 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4076:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 21630 | /* 59369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i16), |
| 21631 | /* 59372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21632 | /* 59374 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21633 | /* 59376 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21634 | /* 59378 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21635 | /* 59381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21636 | /* 59387 */ GIR_RootConstrainSelectedInstOperands, |
| 21637 | /* 59388 */ // GIR_Coverage, 1472, |
| 21638 | /* 59388 */ GIR_EraseRootFromParent_Done, |
| 21639 | /* 59389 */ // Label 1825: @59389 |
| 21640 | /* 59389 */ GIM_Reject, |
| 21641 | /* 59390 */ // Label 1817: @59390 |
| 21642 | /* 59390 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1826*/ GIMT_Encode4(59435), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1474 // |
| 21643 | /* 59397 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21644 | /* 59400 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21645 | /* 59403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21646 | /* 59407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21647 | /* 59411 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21648 | /* 59415 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4076:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 21649 | /* 59415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i16), |
| 21650 | /* 59418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21651 | /* 59420 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21652 | /* 59422 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21653 | /* 59424 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21654 | /* 59427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21655 | /* 59433 */ GIR_RootConstrainSelectedInstOperands, |
| 21656 | /* 59434 */ // GIR_Coverage, 1474, |
| 21657 | /* 59434 */ GIR_EraseRootFromParent_Done, |
| 21658 | /* 59435 */ // Label 1826: @59435 |
| 21659 | /* 59435 */ GIM_Reject, |
| 21660 | /* 59436 */ // Label 1818: @59436 |
| 21661 | /* 59436 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1827*/ GIMT_Encode4(59481), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1473 // |
| 21662 | /* 59443 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21663 | /* 59446 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21664 | /* 59449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21665 | /* 59453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21666 | /* 59457 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21667 | /* 59461 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4076:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 21668 | /* 59461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i32), |
| 21669 | /* 59464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21670 | /* 59466 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21671 | /* 59468 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21672 | /* 59470 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21673 | /* 59473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21674 | /* 59479 */ GIR_RootConstrainSelectedInstOperands, |
| 21675 | /* 59480 */ // GIR_Coverage, 1473, |
| 21676 | /* 59480 */ GIR_EraseRootFromParent_Done, |
| 21677 | /* 59481 */ // Label 1827: @59481 |
| 21678 | /* 59481 */ GIM_Reject, |
| 21679 | /* 59482 */ // Label 1819: @59482 |
| 21680 | /* 59482 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1828*/ GIMT_Encode4(59527), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1475 // |
| 21681 | /* 59489 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21682 | /* 59492 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21683 | /* 59495 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21684 | /* 59499 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21685 | /* 59503 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21686 | /* 59507 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4076:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 21687 | /* 59507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i32), |
| 21688 | /* 59510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21689 | /* 59512 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21690 | /* 59514 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21691 | /* 59516 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21692 | /* 59519 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21693 | /* 59525 */ GIR_RootConstrainSelectedInstOperands, |
| 21694 | /* 59526 */ // GIR_Coverage, 1475, |
| 21695 | /* 59526 */ GIR_EraseRootFromParent_Done, |
| 21696 | /* 59527 */ // Label 1828: @59527 |
| 21697 | /* 59527 */ GIM_Reject, |
| 21698 | /* 59528 */ // Label 1820: @59528 |
| 21699 | /* 59528 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1829*/ GIMT_Encode4(59573), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1479 // |
| 21700 | /* 59535 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21701 | /* 59538 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 21702 | /* 59541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21703 | /* 59545 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21704 | /* 59549 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21705 | /* 59553 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4076:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 21706 | /* 59553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i64), |
| 21707 | /* 59556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21708 | /* 59558 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21709 | /* 59560 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21710 | /* 59562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21711 | /* 59565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21712 | /* 59571 */ GIR_RootConstrainSelectedInstOperands, |
| 21713 | /* 59572 */ // GIR_Coverage, 1479, |
| 21714 | /* 59572 */ GIR_EraseRootFromParent_Done, |
| 21715 | /* 59573 */ // Label 1829: @59573 |
| 21716 | /* 59573 */ GIM_Reject, |
| 21717 | /* 59574 */ // Label 1821: @59574 |
| 21718 | /* 59574 */ GIM_Reject, |
| 21719 | /* 59575 */ // Label 1812: @59575 |
| 21720 | /* 59575 */ GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(60013), |
| 21721 | /* 59580 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 21722 | /* 59585 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1839*/ GIMT_Encode4(60012), |
| 21723 | /* 59596 */ /*GILLT_s64*//*Label 1831*/ GIMT_Encode4(59644), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 21724 | /* 59616 */ /*GILLT_v8s8*//*Label 1832*/ GIMT_Encode4(59690), |
| 21725 | /* 59620 */ /*GILLT_v16s8*//*Label 1833*/ GIMT_Encode4(59736), |
| 21726 | /* 59624 */ /*GILLT_v4s16*//*Label 1834*/ GIMT_Encode4(59782), |
| 21727 | /* 59628 */ /*GILLT_v8s16*//*Label 1835*/ GIMT_Encode4(59828), |
| 21728 | /* 59632 */ /*GILLT_v2s32*//*Label 1836*/ GIMT_Encode4(59874), |
| 21729 | /* 59636 */ /*GILLT_v4s32*//*Label 1837*/ GIMT_Encode4(59920), |
| 21730 | /* 59640 */ /*GILLT_v2s64*//*Label 1838*/ GIMT_Encode4(59966), |
| 21731 | /* 59644 */ // Label 1831: @59644 |
| 21732 | /* 59644 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1840*/ GIMT_Encode4(59689), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1519 // |
| 21733 | /* 59651 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 21734 | /* 59654 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 21735 | /* 59657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21736 | /* 59661 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21737 | /* 59665 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21738 | /* 59669 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4069:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 21739 | /* 59669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv1i64), |
| 21740 | /* 59672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21741 | /* 59674 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21742 | /* 59676 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21743 | /* 59678 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21744 | /* 59681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21745 | /* 59687 */ GIR_RootConstrainSelectedInstOperands, |
| 21746 | /* 59688 */ // GIR_Coverage, 1519, |
| 21747 | /* 59688 */ GIR_EraseRootFromParent_Done, |
| 21748 | /* 59689 */ // Label 1840: @59689 |
| 21749 | /* 59689 */ GIM_Reject, |
| 21750 | /* 59690 */ // Label 1832: @59690 |
| 21751 | /* 59690 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1841*/ GIMT_Encode4(59735), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1517 // |
| 21752 | /* 59697 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21753 | /* 59700 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21754 | /* 59703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21755 | /* 59707 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21756 | /* 59711 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21757 | /* 59715 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4069:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 21758 | /* 59715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i8), |
| 21759 | /* 59718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21760 | /* 59720 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21761 | /* 59722 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21762 | /* 59724 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21763 | /* 59727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21764 | /* 59733 */ GIR_RootConstrainSelectedInstOperands, |
| 21765 | /* 59734 */ // GIR_Coverage, 1517, |
| 21766 | /* 59734 */ GIR_EraseRootFromParent_Done, |
| 21767 | /* 59735 */ // Label 1841: @59735 |
| 21768 | /* 59735 */ GIM_Reject, |
| 21769 | /* 59736 */ // Label 1833: @59736 |
| 21770 | /* 59736 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1842*/ GIMT_Encode4(59781), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1518 // |
| 21771 | /* 59743 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21772 | /* 59746 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21773 | /* 59749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21774 | /* 59753 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21775 | /* 59757 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21776 | /* 59761 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4069:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 21777 | /* 59761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv16i8), |
| 21778 | /* 59764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21779 | /* 59766 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21780 | /* 59768 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21781 | /* 59770 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21782 | /* 59773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21783 | /* 59779 */ GIR_RootConstrainSelectedInstOperands, |
| 21784 | /* 59780 */ // GIR_Coverage, 1518, |
| 21785 | /* 59780 */ GIR_EraseRootFromParent_Done, |
| 21786 | /* 59781 */ // Label 1842: @59781 |
| 21787 | /* 59781 */ GIM_Reject, |
| 21788 | /* 59782 */ // Label 1834: @59782 |
| 21789 | /* 59782 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1843*/ GIMT_Encode4(59827), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1513 // |
| 21790 | /* 59789 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21791 | /* 59792 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21792 | /* 59795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21793 | /* 59799 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21794 | /* 59803 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21795 | /* 59807 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4069:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 21796 | /* 59807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i16), |
| 21797 | /* 59810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21798 | /* 59812 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21799 | /* 59814 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21800 | /* 59816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21801 | /* 59819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21802 | /* 59825 */ GIR_RootConstrainSelectedInstOperands, |
| 21803 | /* 59826 */ // GIR_Coverage, 1513, |
| 21804 | /* 59826 */ GIR_EraseRootFromParent_Done, |
| 21805 | /* 59827 */ // Label 1843: @59827 |
| 21806 | /* 59827 */ GIM_Reject, |
| 21807 | /* 59828 */ // Label 1835: @59828 |
| 21808 | /* 59828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1844*/ GIMT_Encode4(59873), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1515 // |
| 21809 | /* 59835 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21810 | /* 59838 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21811 | /* 59841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21812 | /* 59845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21813 | /* 59849 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21814 | /* 59853 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4069:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 21815 | /* 59853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i16), |
| 21816 | /* 59856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21817 | /* 59858 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21818 | /* 59860 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21819 | /* 59862 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21820 | /* 59865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21821 | /* 59871 */ GIR_RootConstrainSelectedInstOperands, |
| 21822 | /* 59872 */ // GIR_Coverage, 1515, |
| 21823 | /* 59872 */ GIR_EraseRootFromParent_Done, |
| 21824 | /* 59873 */ // Label 1844: @59873 |
| 21825 | /* 59873 */ GIM_Reject, |
| 21826 | /* 59874 */ // Label 1836: @59874 |
| 21827 | /* 59874 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1845*/ GIMT_Encode4(59919), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1514 // |
| 21828 | /* 59881 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21829 | /* 59884 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21830 | /* 59887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21831 | /* 59891 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21832 | /* 59895 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21833 | /* 59899 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4069:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 21834 | /* 59899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i32), |
| 21835 | /* 59902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21836 | /* 59904 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21837 | /* 59906 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21838 | /* 59908 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21839 | /* 59911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21840 | /* 59917 */ GIR_RootConstrainSelectedInstOperands, |
| 21841 | /* 59918 */ // GIR_Coverage, 1514, |
| 21842 | /* 59918 */ GIR_EraseRootFromParent_Done, |
| 21843 | /* 59919 */ // Label 1845: @59919 |
| 21844 | /* 59919 */ GIM_Reject, |
| 21845 | /* 59920 */ // Label 1837: @59920 |
| 21846 | /* 59920 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1846*/ GIMT_Encode4(59965), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1516 // |
| 21847 | /* 59927 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21848 | /* 59930 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21849 | /* 59933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21850 | /* 59937 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21851 | /* 59941 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21852 | /* 59945 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4069:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 21853 | /* 59945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i32), |
| 21854 | /* 59948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21855 | /* 59950 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21856 | /* 59952 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21857 | /* 59954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21858 | /* 59957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21859 | /* 59963 */ GIR_RootConstrainSelectedInstOperands, |
| 21860 | /* 59964 */ // GIR_Coverage, 1516, |
| 21861 | /* 59964 */ GIR_EraseRootFromParent_Done, |
| 21862 | /* 59965 */ // Label 1846: @59965 |
| 21863 | /* 59965 */ GIM_Reject, |
| 21864 | /* 59966 */ // Label 1838: @59966 |
| 21865 | /* 59966 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1847*/ GIMT_Encode4(60011), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1520 // |
| 21866 | /* 59973 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21867 | /* 59976 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 21868 | /* 59979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21869 | /* 59983 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21870 | /* 59987 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21871 | /* 59991 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4069:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 21872 | /* 59991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i64), |
| 21873 | /* 59994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21874 | /* 59996 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21875 | /* 59998 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21876 | /* 60000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21877 | /* 60003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21878 | /* 60009 */ GIR_RootConstrainSelectedInstOperands, |
| 21879 | /* 60010 */ // GIR_Coverage, 1520, |
| 21880 | /* 60010 */ GIR_EraseRootFromParent_Done, |
| 21881 | /* 60011 */ // Label 1847: @60011 |
| 21882 | /* 60011 */ GIM_Reject, |
| 21883 | /* 60012 */ // Label 1839: @60012 |
| 21884 | /* 60012 */ GIM_Reject, |
| 21885 | /* 60013 */ // Label 1830: @60013 |
| 21886 | /* 60013 */ GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(60451), |
| 21887 | /* 60018 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 21888 | /* 60023 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1857*/ GIMT_Encode4(60450), |
| 21889 | /* 60034 */ /*GILLT_s64*//*Label 1849*/ GIMT_Encode4(60082), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 21890 | /* 60054 */ /*GILLT_v8s8*//*Label 1850*/ GIMT_Encode4(60128), |
| 21891 | /* 60058 */ /*GILLT_v16s8*//*Label 1851*/ GIMT_Encode4(60174), |
| 21892 | /* 60062 */ /*GILLT_v4s16*//*Label 1852*/ GIMT_Encode4(60220), |
| 21893 | /* 60066 */ /*GILLT_v8s16*//*Label 1853*/ GIMT_Encode4(60266), |
| 21894 | /* 60070 */ /*GILLT_v2s32*//*Label 1854*/ GIMT_Encode4(60312), |
| 21895 | /* 60074 */ /*GILLT_v4s32*//*Label 1855*/ GIMT_Encode4(60358), |
| 21896 | /* 60078 */ /*GILLT_v2s64*//*Label 1856*/ GIMT_Encode4(60404), |
| 21897 | /* 60082 */ // Label 1849: @60082 |
| 21898 | /* 60082 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1858*/ GIMT_Encode4(60127), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1527 // |
| 21899 | /* 60089 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 21900 | /* 60092 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 21901 | /* 60095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21902 | /* 60099 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21903 | /* 60103 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21904 | /* 60107 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4070:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 21905 | /* 60107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv1i64), |
| 21906 | /* 60110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21907 | /* 60112 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21908 | /* 60114 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21909 | /* 60116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21910 | /* 60119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21911 | /* 60125 */ GIR_RootConstrainSelectedInstOperands, |
| 21912 | /* 60126 */ // GIR_Coverage, 1527, |
| 21913 | /* 60126 */ GIR_EraseRootFromParent_Done, |
| 21914 | /* 60127 */ // Label 1858: @60127 |
| 21915 | /* 60127 */ GIM_Reject, |
| 21916 | /* 60128 */ // Label 1850: @60128 |
| 21917 | /* 60128 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1859*/ GIMT_Encode4(60173), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1525 // |
| 21918 | /* 60135 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21919 | /* 60138 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21920 | /* 60141 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21921 | /* 60145 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21922 | /* 60149 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21923 | /* 60153 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4070:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 21924 | /* 60153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i8), |
| 21925 | /* 60156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21926 | /* 60158 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21927 | /* 60160 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21928 | /* 60162 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21929 | /* 60165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21930 | /* 60171 */ GIR_RootConstrainSelectedInstOperands, |
| 21931 | /* 60172 */ // GIR_Coverage, 1525, |
| 21932 | /* 60172 */ GIR_EraseRootFromParent_Done, |
| 21933 | /* 60173 */ // Label 1859: @60173 |
| 21934 | /* 60173 */ GIM_Reject, |
| 21935 | /* 60174 */ // Label 1851: @60174 |
| 21936 | /* 60174 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1860*/ GIMT_Encode4(60219), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1526 // |
| 21937 | /* 60181 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21938 | /* 60184 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21939 | /* 60187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21940 | /* 60191 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21941 | /* 60195 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21942 | /* 60199 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4070:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 21943 | /* 60199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv16i8), |
| 21944 | /* 60202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21945 | /* 60204 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21946 | /* 60206 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21947 | /* 60208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21948 | /* 60211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21949 | /* 60217 */ GIR_RootConstrainSelectedInstOperands, |
| 21950 | /* 60218 */ // GIR_Coverage, 1526, |
| 21951 | /* 60218 */ GIR_EraseRootFromParent_Done, |
| 21952 | /* 60219 */ // Label 1860: @60219 |
| 21953 | /* 60219 */ GIM_Reject, |
| 21954 | /* 60220 */ // Label 1852: @60220 |
| 21955 | /* 60220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1861*/ GIMT_Encode4(60265), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1521 // |
| 21956 | /* 60227 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21957 | /* 60230 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21958 | /* 60233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21959 | /* 60237 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21960 | /* 60241 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21961 | /* 60245 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4070:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 21962 | /* 60245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i16), |
| 21963 | /* 60248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21964 | /* 60250 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21965 | /* 60252 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21966 | /* 60254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21967 | /* 60257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21968 | /* 60263 */ GIR_RootConstrainSelectedInstOperands, |
| 21969 | /* 60264 */ // GIR_Coverage, 1521, |
| 21970 | /* 60264 */ GIR_EraseRootFromParent_Done, |
| 21971 | /* 60265 */ // Label 1861: @60265 |
| 21972 | /* 60265 */ GIM_Reject, |
| 21973 | /* 60266 */ // Label 1853: @60266 |
| 21974 | /* 60266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1862*/ GIMT_Encode4(60311), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1523 // |
| 21975 | /* 60273 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21976 | /* 60276 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21977 | /* 60279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21978 | /* 60283 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21979 | /* 60287 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21980 | /* 60291 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4070:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 21981 | /* 60291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i16), |
| 21982 | /* 60294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21983 | /* 60296 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21984 | /* 60298 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21985 | /* 60300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21986 | /* 60303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21987 | /* 60309 */ GIR_RootConstrainSelectedInstOperands, |
| 21988 | /* 60310 */ // GIR_Coverage, 1523, |
| 21989 | /* 60310 */ GIR_EraseRootFromParent_Done, |
| 21990 | /* 60311 */ // Label 1862: @60311 |
| 21991 | /* 60311 */ GIM_Reject, |
| 21992 | /* 60312 */ // Label 1854: @60312 |
| 21993 | /* 60312 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1863*/ GIMT_Encode4(60357), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1522 // |
| 21994 | /* 60319 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21995 | /* 60322 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21996 | /* 60325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21997 | /* 60329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21998 | /* 60333 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21999 | /* 60337 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4070:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 22000 | /* 60337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i32), |
| 22001 | /* 60340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22002 | /* 60342 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22003 | /* 60344 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22004 | /* 60346 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22005 | /* 60349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22006 | /* 60355 */ GIR_RootConstrainSelectedInstOperands, |
| 22007 | /* 60356 */ // GIR_Coverage, 1522, |
| 22008 | /* 60356 */ GIR_EraseRootFromParent_Done, |
| 22009 | /* 60357 */ // Label 1863: @60357 |
| 22010 | /* 60357 */ GIM_Reject, |
| 22011 | /* 60358 */ // Label 1855: @60358 |
| 22012 | /* 60358 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1864*/ GIMT_Encode4(60403), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1524 // |
| 22013 | /* 60365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22014 | /* 60368 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22015 | /* 60371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22016 | /* 60375 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22017 | /* 60379 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22018 | /* 60383 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4070:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 22019 | /* 60383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i32), |
| 22020 | /* 60386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22021 | /* 60388 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22022 | /* 60390 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22023 | /* 60392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22024 | /* 60395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22025 | /* 60401 */ GIR_RootConstrainSelectedInstOperands, |
| 22026 | /* 60402 */ // GIR_Coverage, 1524, |
| 22027 | /* 60402 */ GIR_EraseRootFromParent_Done, |
| 22028 | /* 60403 */ // Label 1864: @60403 |
| 22029 | /* 60403 */ GIM_Reject, |
| 22030 | /* 60404 */ // Label 1856: @60404 |
| 22031 | /* 60404 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1865*/ GIMT_Encode4(60449), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1528 // |
| 22032 | /* 60411 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22033 | /* 60414 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22034 | /* 60417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22035 | /* 60421 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22036 | /* 60425 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22037 | /* 60429 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4070:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 22038 | /* 60429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i64), |
| 22039 | /* 60432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22040 | /* 60434 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22041 | /* 60436 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22042 | /* 60438 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22043 | /* 60441 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22044 | /* 60447 */ GIR_RootConstrainSelectedInstOperands, |
| 22045 | /* 60448 */ // GIR_Coverage, 1528, |
| 22046 | /* 60448 */ GIR_EraseRootFromParent_Done, |
| 22047 | /* 60449 */ // Label 1865: @60449 |
| 22048 | /* 60449 */ GIM_Reject, |
| 22049 | /* 60450 */ // Label 1857: @60450 |
| 22050 | /* 60450 */ GIM_Reject, |
| 22051 | /* 60451 */ // Label 1848: @60451 |
| 22052 | /* 60451 */ GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(60889), |
| 22053 | /* 60456 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 22054 | /* 60461 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1875*/ GIMT_Encode4(60888), |
| 22055 | /* 60472 */ /*GILLT_s64*//*Label 1867*/ GIMT_Encode4(60520), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 22056 | /* 60492 */ /*GILLT_v8s8*//*Label 1868*/ GIMT_Encode4(60566), |
| 22057 | /* 60496 */ /*GILLT_v16s8*//*Label 1869*/ GIMT_Encode4(60612), |
| 22058 | /* 60500 */ /*GILLT_v4s16*//*Label 1870*/ GIMT_Encode4(60658), |
| 22059 | /* 60504 */ /*GILLT_v8s16*//*Label 1871*/ GIMT_Encode4(60704), |
| 22060 | /* 60508 */ /*GILLT_v2s32*//*Label 1872*/ GIMT_Encode4(60750), |
| 22061 | /* 60512 */ /*GILLT_v4s32*//*Label 1873*/ GIMT_Encode4(60796), |
| 22062 | /* 60516 */ /*GILLT_v2s64*//*Label 1874*/ GIMT_Encode4(60842), |
| 22063 | /* 60520 */ // Label 1867: @60520 |
| 22064 | /* 60520 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1876*/ GIMT_Encode4(60565), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1554 // |
| 22065 | /* 60527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22066 | /* 60530 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 22067 | /* 60533 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22068 | /* 60537 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22069 | /* 60541 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22070 | /* 60545 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4060:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 22071 | /* 60545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv1i64), |
| 22072 | /* 60548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22073 | /* 60550 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22074 | /* 60552 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22075 | /* 60554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22076 | /* 60557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22077 | /* 60563 */ GIR_RootConstrainSelectedInstOperands, |
| 22078 | /* 60564 */ // GIR_Coverage, 1554, |
| 22079 | /* 60564 */ GIR_EraseRootFromParent_Done, |
| 22080 | /* 60565 */ // Label 1876: @60565 |
| 22081 | /* 60565 */ GIM_Reject, |
| 22082 | /* 60566 */ // Label 1868: @60566 |
| 22083 | /* 60566 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1877*/ GIMT_Encode4(60611), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1552 // |
| 22084 | /* 60573 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 22085 | /* 60576 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 22086 | /* 60579 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22087 | /* 60583 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22088 | /* 60587 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22089 | /* 60591 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4060:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 22090 | /* 60591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i8), |
| 22091 | /* 60594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22092 | /* 60596 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22093 | /* 60598 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22094 | /* 60600 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22095 | /* 60603 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22096 | /* 60609 */ GIR_RootConstrainSelectedInstOperands, |
| 22097 | /* 60610 */ // GIR_Coverage, 1552, |
| 22098 | /* 60610 */ GIR_EraseRootFromParent_Done, |
| 22099 | /* 60611 */ // Label 1877: @60611 |
| 22100 | /* 60611 */ GIM_Reject, |
| 22101 | /* 60612 */ // Label 1869: @60612 |
| 22102 | /* 60612 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1878*/ GIMT_Encode4(60657), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1553 // |
| 22103 | /* 60619 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22104 | /* 60622 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22105 | /* 60625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22106 | /* 60629 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22107 | /* 60633 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22108 | /* 60637 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4060:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 22109 | /* 60637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv16i8), |
| 22110 | /* 60640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22111 | /* 60642 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22112 | /* 60644 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22113 | /* 60646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22114 | /* 60649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22115 | /* 60655 */ GIR_RootConstrainSelectedInstOperands, |
| 22116 | /* 60656 */ // GIR_Coverage, 1553, |
| 22117 | /* 60656 */ GIR_EraseRootFromParent_Done, |
| 22118 | /* 60657 */ // Label 1878: @60657 |
| 22119 | /* 60657 */ GIM_Reject, |
| 22120 | /* 60658 */ // Label 1870: @60658 |
| 22121 | /* 60658 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1879*/ GIMT_Encode4(60703), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1548 // |
| 22122 | /* 60665 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22123 | /* 60668 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22124 | /* 60671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22125 | /* 60675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22126 | /* 60679 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22127 | /* 60683 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4060:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 22128 | /* 60683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i16), |
| 22129 | /* 60686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22130 | /* 60688 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22131 | /* 60690 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22132 | /* 60692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22133 | /* 60695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22134 | /* 60701 */ GIR_RootConstrainSelectedInstOperands, |
| 22135 | /* 60702 */ // GIR_Coverage, 1548, |
| 22136 | /* 60702 */ GIR_EraseRootFromParent_Done, |
| 22137 | /* 60703 */ // Label 1879: @60703 |
| 22138 | /* 60703 */ GIM_Reject, |
| 22139 | /* 60704 */ // Label 1871: @60704 |
| 22140 | /* 60704 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1880*/ GIMT_Encode4(60749), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1550 // |
| 22141 | /* 60711 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22142 | /* 60714 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22143 | /* 60717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22144 | /* 60721 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22145 | /* 60725 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22146 | /* 60729 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4060:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 22147 | /* 60729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i16), |
| 22148 | /* 60732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22149 | /* 60734 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22150 | /* 60736 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22151 | /* 60738 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22152 | /* 60741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22153 | /* 60747 */ GIR_RootConstrainSelectedInstOperands, |
| 22154 | /* 60748 */ // GIR_Coverage, 1550, |
| 22155 | /* 60748 */ GIR_EraseRootFromParent_Done, |
| 22156 | /* 60749 */ // Label 1880: @60749 |
| 22157 | /* 60749 */ GIM_Reject, |
| 22158 | /* 60750 */ // Label 1872: @60750 |
| 22159 | /* 60750 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1881*/ GIMT_Encode4(60795), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1549 // |
| 22160 | /* 60757 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22161 | /* 60760 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22162 | /* 60763 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22163 | /* 60767 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22164 | /* 60771 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22165 | /* 60775 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4060:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 22166 | /* 60775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i32), |
| 22167 | /* 60778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22168 | /* 60780 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22169 | /* 60782 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22170 | /* 60784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22171 | /* 60787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22172 | /* 60793 */ GIR_RootConstrainSelectedInstOperands, |
| 22173 | /* 60794 */ // GIR_Coverage, 1549, |
| 22174 | /* 60794 */ GIR_EraseRootFromParent_Done, |
| 22175 | /* 60795 */ // Label 1881: @60795 |
| 22176 | /* 60795 */ GIM_Reject, |
| 22177 | /* 60796 */ // Label 1873: @60796 |
| 22178 | /* 60796 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1882*/ GIMT_Encode4(60841), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1551 // |
| 22179 | /* 60803 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22180 | /* 60806 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22181 | /* 60809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22182 | /* 60813 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22183 | /* 60817 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22184 | /* 60821 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4060:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 22185 | /* 60821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i32), |
| 22186 | /* 60824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22187 | /* 60826 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22188 | /* 60828 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22189 | /* 60830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22190 | /* 60833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22191 | /* 60839 */ GIR_RootConstrainSelectedInstOperands, |
| 22192 | /* 60840 */ // GIR_Coverage, 1551, |
| 22193 | /* 60840 */ GIR_EraseRootFromParent_Done, |
| 22194 | /* 60841 */ // Label 1882: @60841 |
| 22195 | /* 60841 */ GIM_Reject, |
| 22196 | /* 60842 */ // Label 1874: @60842 |
| 22197 | /* 60842 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1883*/ GIMT_Encode4(60887), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1555 // |
| 22198 | /* 60849 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22199 | /* 60852 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22200 | /* 60855 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22201 | /* 60859 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22202 | /* 60863 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22203 | /* 60867 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4060:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 22204 | /* 60867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i64), |
| 22205 | /* 60870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22206 | /* 60872 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22207 | /* 60874 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22208 | /* 60876 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22209 | /* 60879 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22210 | /* 60885 */ GIR_RootConstrainSelectedInstOperands, |
| 22211 | /* 60886 */ // GIR_Coverage, 1555, |
| 22212 | /* 60886 */ GIR_EraseRootFromParent_Done, |
| 22213 | /* 60887 */ // Label 1883: @60887 |
| 22214 | /* 60887 */ GIM_Reject, |
| 22215 | /* 60888 */ // Label 1875: @60888 |
| 22216 | /* 60888 */ GIM_Reject, |
| 22217 | /* 60889 */ // Label 1866: @60889 |
| 22218 | /* 60889 */ GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(61327), |
| 22219 | /* 60894 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 22220 | /* 60899 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1893*/ GIMT_Encode4(61326), |
| 22221 | /* 60910 */ /*GILLT_s64*//*Label 1885*/ GIMT_Encode4(60958), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 22222 | /* 60930 */ /*GILLT_v8s8*//*Label 1886*/ GIMT_Encode4(61004), |
| 22223 | /* 60934 */ /*GILLT_v16s8*//*Label 1887*/ GIMT_Encode4(61050), |
| 22224 | /* 60938 */ /*GILLT_v4s16*//*Label 1888*/ GIMT_Encode4(61096), |
| 22225 | /* 60942 */ /*GILLT_v8s16*//*Label 1889*/ GIMT_Encode4(61142), |
| 22226 | /* 60946 */ /*GILLT_v2s32*//*Label 1890*/ GIMT_Encode4(61188), |
| 22227 | /* 60950 */ /*GILLT_v4s32*//*Label 1891*/ GIMT_Encode4(61234), |
| 22228 | /* 60954 */ /*GILLT_v2s64*//*Label 1892*/ GIMT_Encode4(61280), |
| 22229 | /* 60958 */ // Label 1885: @60958 |
| 22230 | /* 60958 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1894*/ GIMT_Encode4(61003), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1562 // |
| 22231 | /* 60965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22232 | /* 60968 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 22233 | /* 60971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22234 | /* 60975 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22235 | /* 60979 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22236 | /* 60983 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4062:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 22237 | /* 60983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv1i64), |
| 22238 | /* 60986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22239 | /* 60988 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22240 | /* 60990 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22241 | /* 60992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22242 | /* 60995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22243 | /* 61001 */ GIR_RootConstrainSelectedInstOperands, |
| 22244 | /* 61002 */ // GIR_Coverage, 1562, |
| 22245 | /* 61002 */ GIR_EraseRootFromParent_Done, |
| 22246 | /* 61003 */ // Label 1894: @61003 |
| 22247 | /* 61003 */ GIM_Reject, |
| 22248 | /* 61004 */ // Label 1886: @61004 |
| 22249 | /* 61004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1895*/ GIMT_Encode4(61049), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1560 // |
| 22250 | /* 61011 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 22251 | /* 61014 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 22252 | /* 61017 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22253 | /* 61021 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22254 | /* 61025 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22255 | /* 61029 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4062:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 22256 | /* 61029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i8), |
| 22257 | /* 61032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22258 | /* 61034 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22259 | /* 61036 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22260 | /* 61038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22261 | /* 61041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22262 | /* 61047 */ GIR_RootConstrainSelectedInstOperands, |
| 22263 | /* 61048 */ // GIR_Coverage, 1560, |
| 22264 | /* 61048 */ GIR_EraseRootFromParent_Done, |
| 22265 | /* 61049 */ // Label 1895: @61049 |
| 22266 | /* 61049 */ GIM_Reject, |
| 22267 | /* 61050 */ // Label 1887: @61050 |
| 22268 | /* 61050 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1896*/ GIMT_Encode4(61095), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1561 // |
| 22269 | /* 61057 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22270 | /* 61060 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22271 | /* 61063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22272 | /* 61067 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22273 | /* 61071 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22274 | /* 61075 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4062:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 22275 | /* 61075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv16i8), |
| 22276 | /* 61078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22277 | /* 61080 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22278 | /* 61082 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22279 | /* 61084 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22280 | /* 61087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22281 | /* 61093 */ GIR_RootConstrainSelectedInstOperands, |
| 22282 | /* 61094 */ // GIR_Coverage, 1561, |
| 22283 | /* 61094 */ GIR_EraseRootFromParent_Done, |
| 22284 | /* 61095 */ // Label 1896: @61095 |
| 22285 | /* 61095 */ GIM_Reject, |
| 22286 | /* 61096 */ // Label 1888: @61096 |
| 22287 | /* 61096 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1897*/ GIMT_Encode4(61141), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1556 // |
| 22288 | /* 61103 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22289 | /* 61106 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22290 | /* 61109 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22291 | /* 61113 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22292 | /* 61117 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22293 | /* 61121 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4062:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 22294 | /* 61121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i16), |
| 22295 | /* 61124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22296 | /* 61126 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22297 | /* 61128 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22298 | /* 61130 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22299 | /* 61133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22300 | /* 61139 */ GIR_RootConstrainSelectedInstOperands, |
| 22301 | /* 61140 */ // GIR_Coverage, 1556, |
| 22302 | /* 61140 */ GIR_EraseRootFromParent_Done, |
| 22303 | /* 61141 */ // Label 1897: @61141 |
| 22304 | /* 61141 */ GIM_Reject, |
| 22305 | /* 61142 */ // Label 1889: @61142 |
| 22306 | /* 61142 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1898*/ GIMT_Encode4(61187), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1558 // |
| 22307 | /* 61149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22308 | /* 61152 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22309 | /* 61155 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22310 | /* 61159 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22311 | /* 61163 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22312 | /* 61167 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4062:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 22313 | /* 61167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i16), |
| 22314 | /* 61170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22315 | /* 61172 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22316 | /* 61174 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22317 | /* 61176 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22318 | /* 61179 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22319 | /* 61185 */ GIR_RootConstrainSelectedInstOperands, |
| 22320 | /* 61186 */ // GIR_Coverage, 1558, |
| 22321 | /* 61186 */ GIR_EraseRootFromParent_Done, |
| 22322 | /* 61187 */ // Label 1898: @61187 |
| 22323 | /* 61187 */ GIM_Reject, |
| 22324 | /* 61188 */ // Label 1890: @61188 |
| 22325 | /* 61188 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1899*/ GIMT_Encode4(61233), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1557 // |
| 22326 | /* 61195 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22327 | /* 61198 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22328 | /* 61201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22329 | /* 61205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22330 | /* 61209 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22331 | /* 61213 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4062:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 22332 | /* 61213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i32), |
| 22333 | /* 61216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22334 | /* 61218 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22335 | /* 61220 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22336 | /* 61222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22337 | /* 61225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22338 | /* 61231 */ GIR_RootConstrainSelectedInstOperands, |
| 22339 | /* 61232 */ // GIR_Coverage, 1557, |
| 22340 | /* 61232 */ GIR_EraseRootFromParent_Done, |
| 22341 | /* 61233 */ // Label 1899: @61233 |
| 22342 | /* 61233 */ GIM_Reject, |
| 22343 | /* 61234 */ // Label 1891: @61234 |
| 22344 | /* 61234 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1900*/ GIMT_Encode4(61279), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1559 // |
| 22345 | /* 61241 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22346 | /* 61244 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22347 | /* 61247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22348 | /* 61251 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22349 | /* 61255 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22350 | /* 61259 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4062:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 22351 | /* 61259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i32), |
| 22352 | /* 61262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22353 | /* 61264 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22354 | /* 61266 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22355 | /* 61268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22356 | /* 61271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22357 | /* 61277 */ GIR_RootConstrainSelectedInstOperands, |
| 22358 | /* 61278 */ // GIR_Coverage, 1559, |
| 22359 | /* 61278 */ GIR_EraseRootFromParent_Done, |
| 22360 | /* 61279 */ // Label 1900: @61279 |
| 22361 | /* 61279 */ GIM_Reject, |
| 22362 | /* 61280 */ // Label 1892: @61280 |
| 22363 | /* 61280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1901*/ GIMT_Encode4(61325), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1563 // |
| 22364 | /* 61287 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22365 | /* 61290 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22366 | /* 61293 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22367 | /* 61297 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22368 | /* 61301 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22369 | /* 61305 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4062:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 22370 | /* 61305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i64), |
| 22371 | /* 61308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22372 | /* 61310 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22373 | /* 61312 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22374 | /* 61314 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22375 | /* 61317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22376 | /* 61323 */ GIR_RootConstrainSelectedInstOperands, |
| 22377 | /* 61324 */ // GIR_Coverage, 1563, |
| 22378 | /* 61324 */ GIR_EraseRootFromParent_Done, |
| 22379 | /* 61325 */ // Label 1901: @61325 |
| 22380 | /* 61325 */ GIM_Reject, |
| 22381 | /* 61326 */ // Label 1893: @61326 |
| 22382 | /* 61326 */ GIM_Reject, |
| 22383 | /* 61327 */ // Label 1884: @61327 |
| 22384 | /* 61327 */ GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(61765), |
| 22385 | /* 61332 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 22386 | /* 61337 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1911*/ GIMT_Encode4(61764), |
| 22387 | /* 61348 */ /*GILLT_s64*//*Label 1903*/ GIMT_Encode4(61396), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 22388 | /* 61368 */ /*GILLT_v8s8*//*Label 1904*/ GIMT_Encode4(61442), |
| 22389 | /* 61372 */ /*GILLT_v16s8*//*Label 1905*/ GIMT_Encode4(61488), |
| 22390 | /* 61376 */ /*GILLT_v4s16*//*Label 1906*/ GIMT_Encode4(61534), |
| 22391 | /* 61380 */ /*GILLT_v8s16*//*Label 1907*/ GIMT_Encode4(61580), |
| 22392 | /* 61384 */ /*GILLT_v2s32*//*Label 1908*/ GIMT_Encode4(61626), |
| 22393 | /* 61388 */ /*GILLT_v4s32*//*Label 1909*/ GIMT_Encode4(61672), |
| 22394 | /* 61392 */ /*GILLT_v2s64*//*Label 1910*/ GIMT_Encode4(61718), |
| 22395 | /* 61396 */ // Label 1903: @61396 |
| 22396 | /* 61396 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1912*/ GIMT_Encode4(61441), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1603 // |
| 22397 | /* 61403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22398 | /* 61406 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 22399 | /* 61409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22400 | /* 61413 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22401 | /* 61417 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22402 | /* 61421 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4055:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 22403 | /* 61421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv1i64), |
| 22404 | /* 61424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22405 | /* 61426 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22406 | /* 61428 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22407 | /* 61430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22408 | /* 61433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22409 | /* 61439 */ GIR_RootConstrainSelectedInstOperands, |
| 22410 | /* 61440 */ // GIR_Coverage, 1603, |
| 22411 | /* 61440 */ GIR_EraseRootFromParent_Done, |
| 22412 | /* 61441 */ // Label 1912: @61441 |
| 22413 | /* 61441 */ GIM_Reject, |
| 22414 | /* 61442 */ // Label 1904: @61442 |
| 22415 | /* 61442 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1913*/ GIMT_Encode4(61487), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1601 // |
| 22416 | /* 61449 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 22417 | /* 61452 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 22418 | /* 61455 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22419 | /* 61459 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22420 | /* 61463 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22421 | /* 61467 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4055:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 22422 | /* 61467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i8), |
| 22423 | /* 61470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22424 | /* 61472 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22425 | /* 61474 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22426 | /* 61476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22427 | /* 61479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22428 | /* 61485 */ GIR_RootConstrainSelectedInstOperands, |
| 22429 | /* 61486 */ // GIR_Coverage, 1601, |
| 22430 | /* 61486 */ GIR_EraseRootFromParent_Done, |
| 22431 | /* 61487 */ // Label 1913: @61487 |
| 22432 | /* 61487 */ GIM_Reject, |
| 22433 | /* 61488 */ // Label 1905: @61488 |
| 22434 | /* 61488 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1914*/ GIMT_Encode4(61533), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1602 // |
| 22435 | /* 61495 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22436 | /* 61498 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22437 | /* 61501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22438 | /* 61505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22439 | /* 61509 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22440 | /* 61513 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4055:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 22441 | /* 61513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv16i8), |
| 22442 | /* 61516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22443 | /* 61518 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22444 | /* 61520 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22445 | /* 61522 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22446 | /* 61525 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22447 | /* 61531 */ GIR_RootConstrainSelectedInstOperands, |
| 22448 | /* 61532 */ // GIR_Coverage, 1602, |
| 22449 | /* 61532 */ GIR_EraseRootFromParent_Done, |
| 22450 | /* 61533 */ // Label 1914: @61533 |
| 22451 | /* 61533 */ GIM_Reject, |
| 22452 | /* 61534 */ // Label 1906: @61534 |
| 22453 | /* 61534 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1915*/ GIMT_Encode4(61579), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1597 // |
| 22454 | /* 61541 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22455 | /* 61544 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22456 | /* 61547 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22457 | /* 61551 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22458 | /* 61555 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22459 | /* 61559 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4055:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 22460 | /* 61559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i16), |
| 22461 | /* 61562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22462 | /* 61564 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22463 | /* 61566 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22464 | /* 61568 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22465 | /* 61571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22466 | /* 61577 */ GIR_RootConstrainSelectedInstOperands, |
| 22467 | /* 61578 */ // GIR_Coverage, 1597, |
| 22468 | /* 61578 */ GIR_EraseRootFromParent_Done, |
| 22469 | /* 61579 */ // Label 1915: @61579 |
| 22470 | /* 61579 */ GIM_Reject, |
| 22471 | /* 61580 */ // Label 1907: @61580 |
| 22472 | /* 61580 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1916*/ GIMT_Encode4(61625), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1599 // |
| 22473 | /* 61587 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22474 | /* 61590 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22475 | /* 61593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22476 | /* 61597 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22477 | /* 61601 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22478 | /* 61605 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4055:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 22479 | /* 61605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i16), |
| 22480 | /* 61608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22481 | /* 61610 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22482 | /* 61612 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22483 | /* 61614 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22484 | /* 61617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22485 | /* 61623 */ GIR_RootConstrainSelectedInstOperands, |
| 22486 | /* 61624 */ // GIR_Coverage, 1599, |
| 22487 | /* 61624 */ GIR_EraseRootFromParent_Done, |
| 22488 | /* 61625 */ // Label 1916: @61625 |
| 22489 | /* 61625 */ GIM_Reject, |
| 22490 | /* 61626 */ // Label 1908: @61626 |
| 22491 | /* 61626 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1917*/ GIMT_Encode4(61671), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1598 // |
| 22492 | /* 61633 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22493 | /* 61636 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22494 | /* 61639 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22495 | /* 61643 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22496 | /* 61647 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22497 | /* 61651 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4055:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 22498 | /* 61651 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i32), |
| 22499 | /* 61654 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22500 | /* 61656 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22501 | /* 61658 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22502 | /* 61660 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22503 | /* 61663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22504 | /* 61669 */ GIR_RootConstrainSelectedInstOperands, |
| 22505 | /* 61670 */ // GIR_Coverage, 1598, |
| 22506 | /* 61670 */ GIR_EraseRootFromParent_Done, |
| 22507 | /* 61671 */ // Label 1917: @61671 |
| 22508 | /* 61671 */ GIM_Reject, |
| 22509 | /* 61672 */ // Label 1909: @61672 |
| 22510 | /* 61672 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1918*/ GIMT_Encode4(61717), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1600 // |
| 22511 | /* 61679 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22512 | /* 61682 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22513 | /* 61685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22514 | /* 61689 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22515 | /* 61693 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22516 | /* 61697 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4055:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 22517 | /* 61697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i32), |
| 22518 | /* 61700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22519 | /* 61702 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22520 | /* 61704 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22521 | /* 61706 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22522 | /* 61709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22523 | /* 61715 */ GIR_RootConstrainSelectedInstOperands, |
| 22524 | /* 61716 */ // GIR_Coverage, 1600, |
| 22525 | /* 61716 */ GIR_EraseRootFromParent_Done, |
| 22526 | /* 61717 */ // Label 1918: @61717 |
| 22527 | /* 61717 */ GIM_Reject, |
| 22528 | /* 61718 */ // Label 1910: @61718 |
| 22529 | /* 61718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1919*/ GIMT_Encode4(61763), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1604 // |
| 22530 | /* 61725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22531 | /* 61728 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22532 | /* 61731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22533 | /* 61735 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22534 | /* 61739 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22535 | /* 61743 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4055:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 22536 | /* 61743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i64), |
| 22537 | /* 61746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22538 | /* 61748 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22539 | /* 61750 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22540 | /* 61752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22541 | /* 61755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22542 | /* 61761 */ GIR_RootConstrainSelectedInstOperands, |
| 22543 | /* 61762 */ // GIR_Coverage, 1604, |
| 22544 | /* 61762 */ GIR_EraseRootFromParent_Done, |
| 22545 | /* 61763 */ // Label 1919: @61763 |
| 22546 | /* 61763 */ GIM_Reject, |
| 22547 | /* 61764 */ // Label 1911: @61764 |
| 22548 | /* 61764 */ GIM_Reject, |
| 22549 | /* 61765 */ // Label 1902: @61765 |
| 22550 | /* 61765 */ GIM_Try, /*On fail goto*//*Label 1920*/ GIMT_Encode4(62203), |
| 22551 | /* 61770 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 22552 | /* 61775 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1929*/ GIMT_Encode4(62202), |
| 22553 | /* 61786 */ /*GILLT_s64*//*Label 1921*/ GIMT_Encode4(61834), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 22554 | /* 61806 */ /*GILLT_v8s8*//*Label 1922*/ GIMT_Encode4(61880), |
| 22555 | /* 61810 */ /*GILLT_v16s8*//*Label 1923*/ GIMT_Encode4(61926), |
| 22556 | /* 61814 */ /*GILLT_v4s16*//*Label 1924*/ GIMT_Encode4(61972), |
| 22557 | /* 61818 */ /*GILLT_v8s16*//*Label 1925*/ GIMT_Encode4(62018), |
| 22558 | /* 61822 */ /*GILLT_v2s32*//*Label 1926*/ GIMT_Encode4(62064), |
| 22559 | /* 61826 */ /*GILLT_v4s32*//*Label 1927*/ GIMT_Encode4(62110), |
| 22560 | /* 61830 */ /*GILLT_v2s64*//*Label 1928*/ GIMT_Encode4(62156), |
| 22561 | /* 61834 */ // Label 1921: @61834 |
| 22562 | /* 61834 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1930*/ GIMT_Encode4(61879), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1611 // |
| 22563 | /* 61841 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22564 | /* 61844 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 22565 | /* 61847 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22566 | /* 61851 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22567 | /* 61855 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22568 | /* 61859 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4056:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 22569 | /* 61859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv1i64), |
| 22570 | /* 61862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22571 | /* 61864 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22572 | /* 61866 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22573 | /* 61868 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22574 | /* 61871 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22575 | /* 61877 */ GIR_RootConstrainSelectedInstOperands, |
| 22576 | /* 61878 */ // GIR_Coverage, 1611, |
| 22577 | /* 61878 */ GIR_EraseRootFromParent_Done, |
| 22578 | /* 61879 */ // Label 1930: @61879 |
| 22579 | /* 61879 */ GIM_Reject, |
| 22580 | /* 61880 */ // Label 1922: @61880 |
| 22581 | /* 61880 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1931*/ GIMT_Encode4(61925), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1609 // |
| 22582 | /* 61887 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 22583 | /* 61890 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 22584 | /* 61893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22585 | /* 61897 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22586 | /* 61901 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22587 | /* 61905 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4056:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 22588 | /* 61905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i8), |
| 22589 | /* 61908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22590 | /* 61910 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22591 | /* 61912 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22592 | /* 61914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22593 | /* 61917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22594 | /* 61923 */ GIR_RootConstrainSelectedInstOperands, |
| 22595 | /* 61924 */ // GIR_Coverage, 1609, |
| 22596 | /* 61924 */ GIR_EraseRootFromParent_Done, |
| 22597 | /* 61925 */ // Label 1931: @61925 |
| 22598 | /* 61925 */ GIM_Reject, |
| 22599 | /* 61926 */ // Label 1923: @61926 |
| 22600 | /* 61926 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1932*/ GIMT_Encode4(61971), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1610 // |
| 22601 | /* 61933 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22602 | /* 61936 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22603 | /* 61939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22604 | /* 61943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22605 | /* 61947 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22606 | /* 61951 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4056:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 22607 | /* 61951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv16i8), |
| 22608 | /* 61954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22609 | /* 61956 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22610 | /* 61958 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22611 | /* 61960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22612 | /* 61963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22613 | /* 61969 */ GIR_RootConstrainSelectedInstOperands, |
| 22614 | /* 61970 */ // GIR_Coverage, 1610, |
| 22615 | /* 61970 */ GIR_EraseRootFromParent_Done, |
| 22616 | /* 61971 */ // Label 1932: @61971 |
| 22617 | /* 61971 */ GIM_Reject, |
| 22618 | /* 61972 */ // Label 1924: @61972 |
| 22619 | /* 61972 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1933*/ GIMT_Encode4(62017), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1605 // |
| 22620 | /* 61979 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22621 | /* 61982 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22622 | /* 61985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22623 | /* 61989 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22624 | /* 61993 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22625 | /* 61997 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4056:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 22626 | /* 61997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i16), |
| 22627 | /* 62000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22628 | /* 62002 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22629 | /* 62004 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22630 | /* 62006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22631 | /* 62009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22632 | /* 62015 */ GIR_RootConstrainSelectedInstOperands, |
| 22633 | /* 62016 */ // GIR_Coverage, 1605, |
| 22634 | /* 62016 */ GIR_EraseRootFromParent_Done, |
| 22635 | /* 62017 */ // Label 1933: @62017 |
| 22636 | /* 62017 */ GIM_Reject, |
| 22637 | /* 62018 */ // Label 1925: @62018 |
| 22638 | /* 62018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1934*/ GIMT_Encode4(62063), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1607 // |
| 22639 | /* 62025 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22640 | /* 62028 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22641 | /* 62031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22642 | /* 62035 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22643 | /* 62039 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22644 | /* 62043 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4056:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 22645 | /* 62043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i16), |
| 22646 | /* 62046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22647 | /* 62048 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22648 | /* 62050 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22649 | /* 62052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22650 | /* 62055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22651 | /* 62061 */ GIR_RootConstrainSelectedInstOperands, |
| 22652 | /* 62062 */ // GIR_Coverage, 1607, |
| 22653 | /* 62062 */ GIR_EraseRootFromParent_Done, |
| 22654 | /* 62063 */ // Label 1934: @62063 |
| 22655 | /* 62063 */ GIM_Reject, |
| 22656 | /* 62064 */ // Label 1926: @62064 |
| 22657 | /* 62064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1935*/ GIMT_Encode4(62109), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1606 // |
| 22658 | /* 62071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22659 | /* 62074 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22660 | /* 62077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22661 | /* 62081 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22662 | /* 62085 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22663 | /* 62089 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4056:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 22664 | /* 62089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i32), |
| 22665 | /* 62092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22666 | /* 62094 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22667 | /* 62096 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22668 | /* 62098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22669 | /* 62101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22670 | /* 62107 */ GIR_RootConstrainSelectedInstOperands, |
| 22671 | /* 62108 */ // GIR_Coverage, 1606, |
| 22672 | /* 62108 */ GIR_EraseRootFromParent_Done, |
| 22673 | /* 62109 */ // Label 1935: @62109 |
| 22674 | /* 62109 */ GIM_Reject, |
| 22675 | /* 62110 */ // Label 1927: @62110 |
| 22676 | /* 62110 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1936*/ GIMT_Encode4(62155), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1608 // |
| 22677 | /* 62117 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22678 | /* 62120 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22679 | /* 62123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22680 | /* 62127 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22681 | /* 62131 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22682 | /* 62135 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4056:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 22683 | /* 62135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i32), |
| 22684 | /* 62138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22685 | /* 62140 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22686 | /* 62142 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22687 | /* 62144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22688 | /* 62147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22689 | /* 62153 */ GIR_RootConstrainSelectedInstOperands, |
| 22690 | /* 62154 */ // GIR_Coverage, 1608, |
| 22691 | /* 62154 */ GIR_EraseRootFromParent_Done, |
| 22692 | /* 62155 */ // Label 1936: @62155 |
| 22693 | /* 62155 */ GIM_Reject, |
| 22694 | /* 62156 */ // Label 1928: @62156 |
| 22695 | /* 62156 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1937*/ GIMT_Encode4(62201), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1612 // |
| 22696 | /* 62163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22697 | /* 62166 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22698 | /* 62169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22699 | /* 62173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22700 | /* 62177 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22701 | /* 62181 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4056:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 22702 | /* 62181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i64), |
| 22703 | /* 62184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22704 | /* 62186 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22705 | /* 62188 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22706 | /* 62190 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22707 | /* 62193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22708 | /* 62199 */ GIR_RootConstrainSelectedInstOperands, |
| 22709 | /* 62200 */ // GIR_Coverage, 1612, |
| 22710 | /* 62200 */ GIR_EraseRootFromParent_Done, |
| 22711 | /* 62201 */ // Label 1937: @62201 |
| 22712 | /* 62201 */ GIM_Reject, |
| 22713 | /* 62202 */ // Label 1929: @62202 |
| 22714 | /* 62202 */ GIM_Reject, |
| 22715 | /* 62203 */ // Label 1920: @62203 |
| 22716 | /* 62203 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1938*/ GIMT_Encode4(62247), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1901 // |
| 22717 | /* 62210 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesd), |
| 22718 | /* 62215 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22719 | /* 62218 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22720 | /* 62221 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22721 | /* 62224 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22722 | /* 62228 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22723 | /* 62232 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22724 | /* 62236 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3957:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESD:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) |
| 22725 | /* 62236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESD), |
| 22726 | /* 62239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22727 | /* 62241 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22728 | /* 62243 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22729 | /* 62245 */ GIR_RootConstrainSelectedInstOperands, |
| 22730 | /* 62246 */ // GIR_Coverage, 1901, |
| 22731 | /* 62246 */ GIR_EraseRootFromParent_Done, |
| 22732 | /* 62247 */ // Label 1938: @62247 |
| 22733 | /* 62247 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1939*/ GIMT_Encode4(62291), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1902 // |
| 22734 | /* 62254 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aese), |
| 22735 | /* 62259 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22736 | /* 62262 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22737 | /* 62265 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22738 | /* 62268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22739 | /* 62272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22740 | /* 62276 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22741 | /* 62280 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3958:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESE:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) |
| 22742 | /* 62280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESE), |
| 22743 | /* 62283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22744 | /* 62285 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22745 | /* 62287 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22746 | /* 62289 */ GIR_RootConstrainSelectedInstOperands, |
| 22747 | /* 62290 */ // GIR_Coverage, 1902, |
| 22748 | /* 62290 */ GIR_EraseRootFromParent_Done, |
| 22749 | /* 62291 */ // Label 1939: @62291 |
| 22750 | /* 62291 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1940*/ GIMT_Encode4(62335), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1905 // |
| 22751 | /* 62298 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su1), |
| 22752 | /* 62303 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22753 | /* 62306 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22754 | /* 62309 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22755 | /* 62312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22756 | /* 62316 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22757 | /* 62320 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22758 | /* 62324 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3971:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) |
| 22759 | /* 62324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU1), |
| 22760 | /* 62327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22761 | /* 62329 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22762 | /* 62331 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22763 | /* 62333 */ GIR_RootConstrainSelectedInstOperands, |
| 22764 | /* 62334 */ // GIR_Coverage, 1905, |
| 22765 | /* 62334 */ GIR_EraseRootFromParent_Done, |
| 22766 | /* 62335 */ // Label 1940: @62335 |
| 22767 | /* 62335 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1941*/ GIMT_Encode4(62379), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1906 // |
| 22768 | /* 62342 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su0), |
| 22769 | /* 62347 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22770 | /* 62350 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22771 | /* 62353 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22772 | /* 62356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22773 | /* 62360 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22774 | /* 62364 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22775 | /* 62368 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3974:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) |
| 22776 | /* 62368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU0), |
| 22777 | /* 62371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22778 | /* 62373 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22779 | /* 62375 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22780 | /* 62377 */ GIR_RootConstrainSelectedInstOperands, |
| 22781 | /* 62378 */ // GIR_Coverage, 1906, |
| 22782 | /* 62378 */ GIR_EraseRootFromParent_Done, |
| 22783 | /* 62379 */ // Label 1941: @62379 |
| 22784 | /* 62379 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1942*/ GIMT_Encode4(62432), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1915 // |
| 22785 | /* 62386 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqrshr), |
| 22786 | /* 62391 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22787 | /* 62394 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22788 | /* 62397 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22789 | /* 62400 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22790 | /* 62404 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22791 | /* 62408 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22792 | /* 62412 */ // (intrinsic_wo_chain:{ *:[i32] } 3807:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_SQRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) |
| 22793 | /* 62412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQRSHR), |
| 22794 | /* 62415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22795 | /* 62417 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 22796 | /* 62419 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22797 | /* 62421 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22798 | /* 62424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22799 | /* 62430 */ GIR_RootConstrainSelectedInstOperands, |
| 22800 | /* 62431 */ // GIR_Coverage, 1915, |
| 22801 | /* 62431 */ GIR_EraseRootFromParent_Done, |
| 22802 | /* 62432 */ // Label 1942: @62432 |
| 22803 | /* 62432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1943*/ GIMT_Encode4(62485), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1916 // |
| 22804 | /* 62439 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqrshl), |
| 22805 | /* 62444 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22806 | /* 62447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22807 | /* 62450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22808 | /* 62453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22809 | /* 62457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22810 | /* 62461 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22811 | /* 62465 */ // (intrinsic_wo_chain:{ *:[i32] } 3814:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_UQRSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) |
| 22812 | /* 62465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQRSHL), |
| 22813 | /* 62468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22814 | /* 62470 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 22815 | /* 62472 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22816 | /* 62474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22817 | /* 62477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22818 | /* 62483 */ GIR_RootConstrainSelectedInstOperands, |
| 22819 | /* 62484 */ // GIR_Coverage, 1916, |
| 22820 | /* 62484 */ GIR_EraseRootFromParent_Done, |
| 22821 | /* 62485 */ // Label 1943: @62485 |
| 22822 | /* 62485 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1944*/ GIMT_Encode4(62541), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2041 // |
| 22823 | /* 62492 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16), |
| 22824 | /* 62497 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22825 | /* 62500 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22826 | /* 62503 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22827 | /* 62506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22828 | /* 62510 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22829 | /* 62514 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22830 | /* 62518 */ // (intrinsic_wo_chain:{ *:[i32] } 4152:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (SXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] }) |
| 22831 | /* 62518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB16), |
| 22832 | /* 62521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22833 | /* 62523 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS |
| 22834 | /* 62525 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS |
| 22835 | /* 62527 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22836 | /* 62530 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22837 | /* 62533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22838 | /* 62539 */ GIR_RootConstrainSelectedInstOperands, |
| 22839 | /* 62540 */ // GIR_Coverage, 2041, |
| 22840 | /* 62540 */ GIR_EraseRootFromParent_Done, |
| 22841 | /* 62541 */ // Label 1944: @62541 |
| 22842 | /* 62541 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1945*/ GIMT_Encode4(62597), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2048 // |
| 22843 | /* 62548 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16), |
| 22844 | /* 62553 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22845 | /* 62556 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22846 | /* 62559 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22847 | /* 62562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22848 | /* 62566 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22849 | /* 62570 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22850 | /* 62574 */ // (intrinsic_wo_chain:{ *:[i32] } 4177:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (UXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] }) |
| 22851 | /* 62574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB16), |
| 22852 | /* 62577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22853 | /* 62579 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS |
| 22854 | /* 62581 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS |
| 22855 | /* 62583 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22856 | /* 62586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22857 | /* 62589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22858 | /* 62595 */ GIR_RootConstrainSelectedInstOperands, |
| 22859 | /* 62596 */ // GIR_Coverage, 2048, |
| 22860 | /* 62596 */ GIR_EraseRootFromParent_Done, |
| 22861 | /* 62597 */ // Label 1945: @62597 |
| 22862 | /* 62597 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1946*/ GIMT_Encode4(62650), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2095 // |
| 22863 | /* 62604 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad), |
| 22864 | /* 62609 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22865 | /* 62612 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22866 | /* 62615 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22867 | /* 62618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22868 | /* 62622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22869 | /* 62626 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22870 | /* 62630 */ // (intrinsic_wo_chain:{ *:[i32] } 4128:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 22871 | /* 62630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUAD), |
| 22872 | /* 62633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22873 | /* 62635 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22874 | /* 62637 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22875 | /* 62639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22876 | /* 62642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22877 | /* 62648 */ GIR_RootConstrainSelectedInstOperands, |
| 22878 | /* 62649 */ // GIR_Coverage, 2095, |
| 22879 | /* 62649 */ GIR_EraseRootFromParent_Done, |
| 22880 | /* 62650 */ // Label 1946: @62650 |
| 22881 | /* 62650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1947*/ GIMT_Encode4(62703), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2096 // |
| 22882 | /* 62657 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx), |
| 22883 | /* 62662 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22884 | /* 62665 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22885 | /* 62668 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22886 | /* 62671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22887 | /* 62675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22888 | /* 62679 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22889 | /* 62683 */ // (intrinsic_wo_chain:{ *:[i32] } 4129:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 22890 | /* 62683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUADX), |
| 22891 | /* 62686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22892 | /* 62688 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22893 | /* 62690 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22894 | /* 62692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22895 | /* 62695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22896 | /* 62701 */ GIR_RootConstrainSelectedInstOperands, |
| 22897 | /* 62702 */ // GIR_Coverage, 2096, |
| 22898 | /* 62702 */ GIR_EraseRootFromParent_Done, |
| 22899 | /* 62703 */ // Label 1947: @62703 |
| 22900 | /* 62703 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1948*/ GIMT_Encode4(62756), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2097 // |
| 22901 | /* 62710 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd), |
| 22902 | /* 62715 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22903 | /* 62718 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22904 | /* 62721 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22905 | /* 62724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22906 | /* 62728 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22907 | /* 62732 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22908 | /* 62736 */ // (intrinsic_wo_chain:{ *:[i32] } 4136:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 22909 | /* 62736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSD), |
| 22910 | /* 62739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22911 | /* 62741 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22912 | /* 62743 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22913 | /* 62745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22914 | /* 62748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22915 | /* 62754 */ GIR_RootConstrainSelectedInstOperands, |
| 22916 | /* 62755 */ // GIR_Coverage, 2097, |
| 22917 | /* 62755 */ GIR_EraseRootFromParent_Done, |
| 22918 | /* 62756 */ // Label 1948: @62756 |
| 22919 | /* 62756 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1949*/ GIMT_Encode4(62809), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2098 // |
| 22920 | /* 62763 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx), |
| 22921 | /* 62768 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22922 | /* 62771 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22923 | /* 62774 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22924 | /* 62777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22925 | /* 62781 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22926 | /* 62785 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22927 | /* 62789 */ // (intrinsic_wo_chain:{ *:[i32] } 4137:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 22928 | /* 62789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSDX), |
| 22929 | /* 62792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22930 | /* 62794 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22931 | /* 62796 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22932 | /* 62798 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22933 | /* 62801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22934 | /* 62807 */ GIR_RootConstrainSelectedInstOperands, |
| 22935 | /* 62808 */ // GIR_Coverage, 2098, |
| 22936 | /* 62808 */ GIR_EraseRootFromParent_Done, |
| 22937 | /* 62809 */ // Label 1949: @62809 |
| 22938 | /* 62809 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1950*/ GIMT_Encode4(62862), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2179 // |
| 22939 | /* 62816 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb), |
| 22940 | /* 62821 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22941 | /* 62824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22942 | /* 62827 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22943 | /* 62830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22944 | /* 62834 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22945 | /* 62838 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22946 | /* 62842 */ // (intrinsic_wo_chain:{ *:[i32] } 4130:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 22947 | /* 62842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB), |
| 22948 | /* 62845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22949 | /* 62847 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 22950 | /* 62849 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 22951 | /* 62851 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22952 | /* 62854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22953 | /* 62860 */ GIR_RootConstrainSelectedInstOperands, |
| 22954 | /* 62861 */ // GIR_Coverage, 2179, |
| 22955 | /* 62861 */ GIR_EraseRootFromParent_Done, |
| 22956 | /* 62862 */ // Label 1950: @62862 |
| 22957 | /* 62862 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1951*/ GIMT_Encode4(62915), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2180 // |
| 22958 | /* 62869 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt), |
| 22959 | /* 62874 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22960 | /* 62877 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22961 | /* 62880 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22962 | /* 62883 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22963 | /* 62887 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22964 | /* 62891 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22965 | /* 62895 */ // (intrinsic_wo_chain:{ *:[i32] } 4131:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 22966 | /* 62895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT), |
| 22967 | /* 62898 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22968 | /* 62900 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 22969 | /* 62902 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 22970 | /* 62904 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22971 | /* 62907 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22972 | /* 62913 */ GIR_RootConstrainSelectedInstOperands, |
| 22973 | /* 62914 */ // GIR_Coverage, 2180, |
| 22974 | /* 62914 */ GIR_EraseRootFromParent_Done, |
| 22975 | /* 62915 */ // Label 1951: @62915 |
| 22976 | /* 62915 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1952*/ GIMT_Encode4(62968), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2181 // |
| 22977 | /* 62922 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb), |
| 22978 | /* 62927 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22979 | /* 62930 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22980 | /* 62933 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22981 | /* 62936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22982 | /* 62940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22983 | /* 62944 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22984 | /* 62948 */ // (intrinsic_wo_chain:{ *:[i32] } 4132:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 22985 | /* 62948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB), |
| 22986 | /* 62951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22987 | /* 62953 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 22988 | /* 62955 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 22989 | /* 62957 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22990 | /* 62960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22991 | /* 62966 */ GIR_RootConstrainSelectedInstOperands, |
| 22992 | /* 62967 */ // GIR_Coverage, 2181, |
| 22993 | /* 62967 */ GIR_EraseRootFromParent_Done, |
| 22994 | /* 62968 */ // Label 1952: @62968 |
| 22995 | /* 62968 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1953*/ GIMT_Encode4(63021), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2182 // |
| 22996 | /* 62975 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt), |
| 22997 | /* 62980 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22998 | /* 62983 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22999 | /* 62986 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23000 | /* 62989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23001 | /* 62993 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23002 | /* 62997 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23003 | /* 63001 */ // (intrinsic_wo_chain:{ *:[i32] } 4133:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 23004 | /* 63001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT), |
| 23005 | /* 63004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23006 | /* 63006 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 23007 | /* 63008 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 23008 | /* 63010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23009 | /* 63013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23010 | /* 63019 */ GIR_RootConstrainSelectedInstOperands, |
| 23011 | /* 63020 */ // GIR_Coverage, 2182, |
| 23012 | /* 63020 */ GIR_EraseRootFromParent_Done, |
| 23013 | /* 63021 */ // Label 1953: @63021 |
| 23014 | /* 63021 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1954*/ GIMT_Encode4(63074), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2183 // |
| 23015 | /* 63028 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb), |
| 23016 | /* 63033 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23017 | /* 63036 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23018 | /* 63039 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23019 | /* 63042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23020 | /* 63046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23021 | /* 63050 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23022 | /* 63054 */ // (intrinsic_wo_chain:{ *:[i32] } 4134:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 23023 | /* 63054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWB), |
| 23024 | /* 63057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23025 | /* 63059 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 23026 | /* 63061 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 23027 | /* 63063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23028 | /* 63066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23029 | /* 63072 */ GIR_RootConstrainSelectedInstOperands, |
| 23030 | /* 63073 */ // GIR_Coverage, 2183, |
| 23031 | /* 63073 */ GIR_EraseRootFromParent_Done, |
| 23032 | /* 63074 */ // Label 1954: @63074 |
| 23033 | /* 63074 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1955*/ GIMT_Encode4(63127), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2184 // |
| 23034 | /* 63081 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt), |
| 23035 | /* 63086 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23036 | /* 63089 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23037 | /* 63092 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23038 | /* 63095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23039 | /* 63099 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23040 | /* 63103 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23041 | /* 63107 */ // (intrinsic_wo_chain:{ *:[i32] } 4135:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 23042 | /* 63107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWT), |
| 23043 | /* 63110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23044 | /* 63112 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 23045 | /* 63114 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 23046 | /* 63116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23047 | /* 63119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23048 | /* 63125 */ GIR_RootConstrainSelectedInstOperands, |
| 23049 | /* 63126 */ // GIR_Coverage, 2184, |
| 23050 | /* 63126 */ GIR_EraseRootFromParent_Done, |
| 23051 | /* 63127 */ // Label 1955: @63127 |
| 23052 | /* 63127 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1956*/ GIMT_Encode4(63183), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2296 // |
| 23053 | /* 63134 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16), |
| 23054 | /* 63139 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23055 | /* 63142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23056 | /* 63145 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23057 | /* 63148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23058 | /* 63152 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23059 | /* 63156 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23060 | /* 63160 */ // (intrinsic_wo_chain:{ *:[i32] } 4152:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 23061 | /* 63160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB16), |
| 23062 | /* 63163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23063 | /* 63165 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23064 | /* 63167 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23065 | /* 63169 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23066 | /* 63172 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23067 | /* 63175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23068 | /* 63181 */ GIR_RootConstrainSelectedInstOperands, |
| 23069 | /* 63182 */ // GIR_Coverage, 2296, |
| 23070 | /* 63182 */ GIR_EraseRootFromParent_Done, |
| 23071 | /* 63183 */ // Label 1956: @63183 |
| 23072 | /* 63183 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1957*/ GIMT_Encode4(63236), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2326 // |
| 23073 | /* 63190 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 23074 | /* 63195 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23075 | /* 63198 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23076 | /* 63201 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23077 | /* 63204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23078 | /* 63208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23079 | /* 63212 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23080 | /* 63216 */ // (intrinsic_wo_chain:{ *:[i32] } 4095:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 23081 | /* 63216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD), |
| 23082 | /* 63219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23083 | /* 63221 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 23084 | /* 63223 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 23085 | /* 63225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23086 | /* 63228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23087 | /* 63234 */ GIR_RootConstrainSelectedInstOperands, |
| 23088 | /* 63235 */ // GIR_Coverage, 2326, |
| 23089 | /* 63235 */ GIR_EraseRootFromParent_Done, |
| 23090 | /* 63236 */ // Label 1957: @63236 |
| 23091 | /* 63236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1958*/ GIMT_Encode4(63289), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2327 // |
| 23092 | /* 63243 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 23093 | /* 63248 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23094 | /* 63251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23095 | /* 63254 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23096 | /* 63257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23097 | /* 63261 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23098 | /* 63265 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23099 | /* 63269 */ // (intrinsic_wo_chain:{ *:[i32] } 4100:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 23100 | /* 63269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB), |
| 23101 | /* 63272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23102 | /* 63274 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 23103 | /* 63276 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 23104 | /* 63278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23105 | /* 63281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23106 | /* 63287 */ GIR_RootConstrainSelectedInstOperands, |
| 23107 | /* 63288 */ // GIR_Coverage, 2327, |
| 23108 | /* 63288 */ GIR_EraseRootFromParent_Done, |
| 23109 | /* 63289 */ // Label 1958: @63289 |
| 23110 | /* 63289 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1959*/ GIMT_Encode4(63342), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2367 // |
| 23111 | /* 63296 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb), |
| 23112 | /* 63301 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23113 | /* 63304 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23114 | /* 63307 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23115 | /* 63310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23116 | /* 63314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23117 | /* 63318 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23118 | /* 63322 */ // (intrinsic_wo_chain:{ *:[i32] } 4130:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23119 | /* 63322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB), |
| 23120 | /* 63325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23121 | /* 63327 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23122 | /* 63329 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23123 | /* 63331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23124 | /* 63334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23125 | /* 63340 */ GIR_RootConstrainSelectedInstOperands, |
| 23126 | /* 63341 */ // GIR_Coverage, 2367, |
| 23127 | /* 63341 */ GIR_EraseRootFromParent_Done, |
| 23128 | /* 63342 */ // Label 1959: @63342 |
| 23129 | /* 63342 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1960*/ GIMT_Encode4(63395), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2368 // |
| 23130 | /* 63349 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt), |
| 23131 | /* 63354 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23132 | /* 63357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23133 | /* 63360 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23134 | /* 63363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23135 | /* 63367 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23136 | /* 63371 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23137 | /* 63375 */ // (intrinsic_wo_chain:{ *:[i32] } 4131:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23138 | /* 63375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT), |
| 23139 | /* 63378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23140 | /* 63380 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23141 | /* 63382 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23142 | /* 63384 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23143 | /* 63387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23144 | /* 63393 */ GIR_RootConstrainSelectedInstOperands, |
| 23145 | /* 63394 */ // GIR_Coverage, 2368, |
| 23146 | /* 63394 */ GIR_EraseRootFromParent_Done, |
| 23147 | /* 63395 */ // Label 1960: @63395 |
| 23148 | /* 63395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1961*/ GIMT_Encode4(63448), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2369 // |
| 23149 | /* 63402 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb), |
| 23150 | /* 63407 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23151 | /* 63410 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23152 | /* 63413 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23153 | /* 63416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23154 | /* 63420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23155 | /* 63424 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23156 | /* 63428 */ // (intrinsic_wo_chain:{ *:[i32] } 4132:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23157 | /* 63428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB), |
| 23158 | /* 63431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23159 | /* 63433 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23160 | /* 63435 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23161 | /* 63437 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23162 | /* 63440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23163 | /* 63446 */ GIR_RootConstrainSelectedInstOperands, |
| 23164 | /* 63447 */ // GIR_Coverage, 2369, |
| 23165 | /* 63447 */ GIR_EraseRootFromParent_Done, |
| 23166 | /* 63448 */ // Label 1961: @63448 |
| 23167 | /* 63448 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1962*/ GIMT_Encode4(63501), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2370 // |
| 23168 | /* 63455 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt), |
| 23169 | /* 63460 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23170 | /* 63463 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23171 | /* 63466 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23172 | /* 63469 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23173 | /* 63473 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23174 | /* 63477 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23175 | /* 63481 */ // (intrinsic_wo_chain:{ *:[i32] } 4133:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23176 | /* 63481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT), |
| 23177 | /* 63484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23178 | /* 63486 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23179 | /* 63488 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23180 | /* 63490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23181 | /* 63493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23182 | /* 63499 */ GIR_RootConstrainSelectedInstOperands, |
| 23183 | /* 63500 */ // GIR_Coverage, 2370, |
| 23184 | /* 63500 */ GIR_EraseRootFromParent_Done, |
| 23185 | /* 63501 */ // Label 1962: @63501 |
| 23186 | /* 63501 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1963*/ GIMT_Encode4(63554), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2371 // |
| 23187 | /* 63508 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb), |
| 23188 | /* 63513 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23189 | /* 63516 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23190 | /* 63519 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23191 | /* 63522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23192 | /* 63526 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23193 | /* 63530 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23194 | /* 63534 */ // (intrinsic_wo_chain:{ *:[i32] } 4134:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23195 | /* 63534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWB), |
| 23196 | /* 63537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23197 | /* 63539 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23198 | /* 63541 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23199 | /* 63543 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23200 | /* 63546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23201 | /* 63552 */ GIR_RootConstrainSelectedInstOperands, |
| 23202 | /* 63553 */ // GIR_Coverage, 2371, |
| 23203 | /* 63553 */ GIR_EraseRootFromParent_Done, |
| 23204 | /* 63554 */ // Label 1963: @63554 |
| 23205 | /* 63554 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1964*/ GIMT_Encode4(63607), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2372 // |
| 23206 | /* 63561 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt), |
| 23207 | /* 63566 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23208 | /* 63569 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23209 | /* 63572 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23210 | /* 63575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23211 | /* 63579 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23212 | /* 63583 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23213 | /* 63587 */ // (intrinsic_wo_chain:{ *:[i32] } 4135:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23214 | /* 63587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWT), |
| 23215 | /* 63590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23216 | /* 63592 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23217 | /* 63594 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23218 | /* 63596 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23219 | /* 63599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23220 | /* 63605 */ GIR_RootConstrainSelectedInstOperands, |
| 23221 | /* 63606 */ // GIR_Coverage, 2372, |
| 23222 | /* 63606 */ GIR_EraseRootFromParent_Done, |
| 23223 | /* 63607 */ // Label 1964: @63607 |
| 23224 | /* 63607 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1965*/ GIMT_Encode4(63654), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2902 // |
| 23225 | /* 63614 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 23226 | /* 63619 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 23227 | /* 63622 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 23228 | /* 63625 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 23229 | /* 63628 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23230 | /* 63632 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23231 | /* 63636 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23232 | /* 63640 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3988:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 0:{ *:[i32] }) |
| 23233 | /* 63640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16), |
| 23234 | /* 63643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23235 | /* 63645 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23236 | /* 63647 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23237 | /* 63649 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23238 | /* 63652 */ GIR_RootConstrainSelectedInstOperands, |
| 23239 | /* 63653 */ // GIR_Coverage, 2902, |
| 23240 | /* 63653 */ GIR_EraseRootFromParent_Done, |
| 23241 | /* 63654 */ // Label 1965: @63654 |
| 23242 | /* 63654 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1966*/ GIMT_Encode4(63701), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2903 // |
| 23243 | /* 63661 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 23244 | /* 63666 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 23245 | /* 63669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 23246 | /* 63672 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 23247 | /* 63675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23248 | /* 63679 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23249 | /* 63683 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23250 | /* 63687 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3987:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 1:{ *:[i32] }) |
| 23251 | /* 63687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16), |
| 23252 | /* 63690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23253 | /* 63692 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23254 | /* 63694 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23255 | /* 63696 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 23256 | /* 63699 */ GIR_RootConstrainSelectedInstOperands, |
| 23257 | /* 63700 */ // GIR_Coverage, 2903, |
| 23258 | /* 63700 */ GIR_EraseRootFromParent_Done, |
| 23259 | /* 63701 */ // Label 1966: @63701 |
| 23260 | /* 63701 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1967*/ GIMT_Encode4(63748), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2904 // |
| 23261 | /* 63708 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 23262 | /* 63713 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23263 | /* 63716 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23264 | /* 63719 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23265 | /* 63722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23266 | /* 63726 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23267 | /* 63730 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23268 | /* 63734 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3988:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 0:{ *:[i32] }) |
| 23269 | /* 63734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16), |
| 23270 | /* 63737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23271 | /* 63739 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23272 | /* 63741 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23273 | /* 63743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23274 | /* 63746 */ GIR_RootConstrainSelectedInstOperands, |
| 23275 | /* 63747 */ // GIR_Coverage, 2904, |
| 23276 | /* 63747 */ GIR_EraseRootFromParent_Done, |
| 23277 | /* 63748 */ // Label 1967: @63748 |
| 23278 | /* 63748 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1968*/ GIMT_Encode4(63795), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2905 // |
| 23279 | /* 63755 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 23280 | /* 63760 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23281 | /* 63763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23282 | /* 63766 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23283 | /* 63769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23284 | /* 63773 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23285 | /* 63777 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23286 | /* 63781 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3987:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 1:{ *:[i32] }) |
| 23287 | /* 63781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16), |
| 23288 | /* 63784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23289 | /* 63786 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23290 | /* 63788 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23291 | /* 63790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 23292 | /* 63793 */ GIR_RootConstrainSelectedInstOperands, |
| 23293 | /* 63794 */ // GIR_Coverage, 2905, |
| 23294 | /* 63794 */ GIR_EraseRootFromParent_Done, |
| 23295 | /* 63795 */ // Label 1968: @63795 |
| 23296 | /* 63795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1969*/ GIMT_Encode4(63842), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2906 // |
| 23297 | /* 63802 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 23298 | /* 63807 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 23299 | /* 63810 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 23300 | /* 63813 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 23301 | /* 63816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23302 | /* 63820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23303 | /* 63824 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23304 | /* 63828 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3988:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 0:{ *:[i32] }) |
| 23305 | /* 63828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32), |
| 23306 | /* 63831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23307 | /* 63833 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23308 | /* 63835 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23309 | /* 63837 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23310 | /* 63840 */ GIR_RootConstrainSelectedInstOperands, |
| 23311 | /* 63841 */ // GIR_Coverage, 2906, |
| 23312 | /* 63841 */ GIR_EraseRootFromParent_Done, |
| 23313 | /* 63842 */ // Label 1969: @63842 |
| 23314 | /* 63842 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1970*/ GIMT_Encode4(63889), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2907 // |
| 23315 | /* 63849 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 23316 | /* 63854 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 23317 | /* 63857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 23318 | /* 63860 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 23319 | /* 63863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23320 | /* 63867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23321 | /* 63871 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23322 | /* 63875 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3987:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 1:{ *:[i32] }) |
| 23323 | /* 63875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32), |
| 23324 | /* 63878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23325 | /* 63880 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23326 | /* 63882 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23327 | /* 63884 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 23328 | /* 63887 */ GIR_RootConstrainSelectedInstOperands, |
| 23329 | /* 63888 */ // GIR_Coverage, 2907, |
| 23330 | /* 63888 */ GIR_EraseRootFromParent_Done, |
| 23331 | /* 63889 */ // Label 1970: @63889 |
| 23332 | /* 63889 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1971*/ GIMT_Encode4(63936), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2908 // |
| 23333 | /* 63896 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 23334 | /* 63901 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23335 | /* 63904 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23336 | /* 63907 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23337 | /* 63910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23338 | /* 63914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23339 | /* 63918 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23340 | /* 63922 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3988:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 0:{ *:[i32] }) |
| 23341 | /* 63922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32), |
| 23342 | /* 63925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23343 | /* 63927 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23344 | /* 63929 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23345 | /* 63931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23346 | /* 63934 */ GIR_RootConstrainSelectedInstOperands, |
| 23347 | /* 63935 */ // GIR_Coverage, 2908, |
| 23348 | /* 63935 */ GIR_EraseRootFromParent_Done, |
| 23349 | /* 63936 */ // Label 1971: @63936 |
| 23350 | /* 63936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1972*/ GIMT_Encode4(63983), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2909 // |
| 23351 | /* 63943 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 23352 | /* 63948 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23353 | /* 63951 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23354 | /* 63954 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23355 | /* 63957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23356 | /* 63961 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23357 | /* 63965 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23358 | /* 63969 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3987:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 1:{ *:[i32] }) |
| 23359 | /* 63969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32), |
| 23360 | /* 63972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23361 | /* 63974 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23362 | /* 63976 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23363 | /* 63978 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 23364 | /* 63981 */ GIR_RootConstrainSelectedInstOperands, |
| 23365 | /* 63982 */ // GIR_Coverage, 2909, |
| 23366 | /* 63982 */ GIR_EraseRootFromParent_Done, |
| 23367 | /* 63983 */ // Label 1972: @63983 |
| 23368 | /* 63983 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1973*/ GIMT_Encode4(64057), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3420 // |
| 23369 | /* 63990 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm), |
| 23370 | /* 63995 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23371 | /* 63998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23372 | /* 64001 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23373 | /* 64004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23374 | /* 64008 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23375 | /* 64012 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23376 | /* 64016 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3875:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 23377 | /* 64016 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23378 | /* 64019 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23379 | /* 64023 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23380 | /* 64028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32), |
| 23381 | /* 64031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23382 | /* 64033 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23383 | /* 64035 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23384 | /* 64037 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23385 | /* 64040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23386 | /* 64046 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23387 | /* 64052 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23388 | /* 64055 */ GIR_RootConstrainSelectedInstOperands, |
| 23389 | /* 64056 */ // GIR_Coverage, 3420, |
| 23390 | /* 64056 */ GIR_EraseRootFromParent_Done, |
| 23391 | /* 64057 */ // Label 1973: @64057 |
| 23392 | /* 64057 */ GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(64281), |
| 23393 | /* 64062 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv), |
| 23394 | /* 64067 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1977*/ GIMT_Encode4(64280), |
| 23395 | /* 64078 */ /*GILLT_s16*//*Label 1975*/ GIMT_Encode4(64086), |
| 23396 | /* 64082 */ /*GILLT_s32*//*Label 1976*/ GIMT_Encode4(64183), |
| 23397 | /* 64086 */ // Label 1975: @64086 |
| 23398 | /* 64086 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1978*/ GIMT_Encode4(64182), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3498 // |
| 23399 | /* 64093 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 23400 | /* 64096 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23401 | /* 64099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23402 | /* 64103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23403 | /* 64107 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23404 | /* 64111 */ // (intrinsic_wo_chain:{ *:[f16] } 3783:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 23405 | /* 64111 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23406 | /* 64114 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23407 | /* 64118 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23408 | /* 64123 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23409 | /* 64127 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23410 | /* 64132 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23411 | /* 64135 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf16), |
| 23412 | /* 64139 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23413 | /* 64144 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23414 | /* 64147 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23415 | /* 64151 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23416 | /* 64154 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23417 | /* 64160 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23418 | /* 64166 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23419 | /* 64168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23420 | /* 64171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23421 | /* 64173 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23422 | /* 64176 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 23423 | /* 64181 */ // GIR_Coverage, 3498, |
| 23424 | /* 64181 */ GIR_EraseRootFromParent_Done, |
| 23425 | /* 64182 */ // Label 1978: @64182 |
| 23426 | /* 64182 */ GIM_Reject, |
| 23427 | /* 64183 */ // Label 1976: @64183 |
| 23428 | /* 64183 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1979*/ GIMT_Encode4(64279), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3496 // |
| 23429 | /* 64190 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23430 | /* 64193 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23431 | /* 64196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23432 | /* 64200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23433 | /* 64204 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23434 | /* 64208 */ // (intrinsic_wo_chain:{ *:[f32] } 3783:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 23435 | /* 64208 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23436 | /* 64211 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23437 | /* 64215 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23438 | /* 64220 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23439 | /* 64224 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23440 | /* 64229 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23441 | /* 64232 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf32), |
| 23442 | /* 64236 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23443 | /* 64241 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23444 | /* 64244 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23445 | /* 64248 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23446 | /* 64251 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23447 | /* 64257 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23448 | /* 64263 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23449 | /* 64265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23450 | /* 64268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23451 | /* 64270 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23452 | /* 64273 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 23453 | /* 64278 */ // GIR_Coverage, 3496, |
| 23454 | /* 64278 */ GIR_EraseRootFromParent_Done, |
| 23455 | /* 64279 */ // Label 1979: @64279 |
| 23456 | /* 64279 */ GIM_Reject, |
| 23457 | /* 64280 */ // Label 1977: @64280 |
| 23458 | /* 64280 */ GIM_Reject, |
| 23459 | /* 64281 */ // Label 1974: @64281 |
| 23460 | /* 64281 */ GIM_Try, /*On fail goto*//*Label 1980*/ GIMT_Encode4(64505), |
| 23461 | /* 64286 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv), |
| 23462 | /* 64291 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1983*/ GIMT_Encode4(64504), |
| 23463 | /* 64302 */ /*GILLT_s16*//*Label 1981*/ GIMT_Encode4(64310), |
| 23464 | /* 64306 */ /*GILLT_s32*//*Label 1982*/ GIMT_Encode4(64407), |
| 23465 | /* 64310 */ // Label 1981: @64310 |
| 23466 | /* 64310 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1984*/ GIMT_Encode4(64406), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3502 // |
| 23467 | /* 64317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 23468 | /* 64320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23469 | /* 64323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23470 | /* 64327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23471 | /* 64331 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23472 | /* 64335 */ // (intrinsic_wo_chain:{ *:[f16] } 3774:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 23473 | /* 64335 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23474 | /* 64338 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23475 | /* 64342 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23476 | /* 64347 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23477 | /* 64351 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23478 | /* 64356 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23479 | /* 64359 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf16), |
| 23480 | /* 64363 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23481 | /* 64368 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23482 | /* 64371 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23483 | /* 64375 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23484 | /* 64378 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23485 | /* 64384 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23486 | /* 64390 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23487 | /* 64392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23488 | /* 64395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23489 | /* 64397 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23490 | /* 64400 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 23491 | /* 64405 */ // GIR_Coverage, 3502, |
| 23492 | /* 64405 */ GIR_EraseRootFromParent_Done, |
| 23493 | /* 64406 */ // Label 1984: @64406 |
| 23494 | /* 64406 */ GIM_Reject, |
| 23495 | /* 64407 */ // Label 1982: @64407 |
| 23496 | /* 64407 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1985*/ GIMT_Encode4(64503), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3500 // |
| 23497 | /* 64414 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23498 | /* 64417 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23499 | /* 64420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23500 | /* 64424 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23501 | /* 64428 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23502 | /* 64432 */ // (intrinsic_wo_chain:{ *:[f32] } 3774:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 23503 | /* 64432 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23504 | /* 64435 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23505 | /* 64439 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23506 | /* 64444 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23507 | /* 64448 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23508 | /* 64453 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23509 | /* 64456 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf32), |
| 23510 | /* 64460 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23511 | /* 64465 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23512 | /* 64468 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23513 | /* 64472 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23514 | /* 64475 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23515 | /* 64481 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23516 | /* 64487 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23517 | /* 64489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23518 | /* 64492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23519 | /* 64494 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23520 | /* 64497 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 23521 | /* 64502 */ // GIR_Coverage, 3500, |
| 23522 | /* 64502 */ GIR_EraseRootFromParent_Done, |
| 23523 | /* 64503 */ // Label 1985: @64503 |
| 23524 | /* 64503 */ GIM_Reject, |
| 23525 | /* 64504 */ // Label 1983: @64504 |
| 23526 | /* 64504 */ GIM_Reject, |
| 23527 | /* 64505 */ // Label 1980: @64505 |
| 23528 | /* 64505 */ GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(64729), |
| 23529 | /* 64510 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav), |
| 23530 | /* 64515 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1989*/ GIMT_Encode4(64728), |
| 23531 | /* 64526 */ /*GILLT_s16*//*Label 1987*/ GIMT_Encode4(64534), |
| 23532 | /* 64530 */ /*GILLT_s32*//*Label 1988*/ GIMT_Encode4(64631), |
| 23533 | /* 64534 */ // Label 1987: @64534 |
| 23534 | /* 64534 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1990*/ GIMT_Encode4(64630), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3506 // |
| 23535 | /* 64541 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 23536 | /* 64544 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23537 | /* 64547 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23538 | /* 64551 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23539 | /* 64555 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23540 | /* 64559 */ // (intrinsic_wo_chain:{ *:[f16] } 3781:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 23541 | /* 64559 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23542 | /* 64562 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23543 | /* 64566 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23544 | /* 64571 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23545 | /* 64575 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23546 | /* 64580 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23547 | /* 64583 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf16), |
| 23548 | /* 64587 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23549 | /* 64592 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23550 | /* 64595 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23551 | /* 64599 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23552 | /* 64602 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23553 | /* 64608 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23554 | /* 64614 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23555 | /* 64616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23556 | /* 64619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23557 | /* 64621 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23558 | /* 64624 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 23559 | /* 64629 */ // GIR_Coverage, 3506, |
| 23560 | /* 64629 */ GIR_EraseRootFromParent_Done, |
| 23561 | /* 64630 */ // Label 1990: @64630 |
| 23562 | /* 64630 */ GIM_Reject, |
| 23563 | /* 64631 */ // Label 1988: @64631 |
| 23564 | /* 64631 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1991*/ GIMT_Encode4(64727), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3504 // |
| 23565 | /* 64638 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23566 | /* 64641 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23567 | /* 64644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23568 | /* 64648 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23569 | /* 64652 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23570 | /* 64656 */ // (intrinsic_wo_chain:{ *:[f32] } 3781:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 23571 | /* 64656 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23572 | /* 64659 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23573 | /* 64663 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23574 | /* 64668 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23575 | /* 64672 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23576 | /* 64677 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23577 | /* 64680 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf32), |
| 23578 | /* 64684 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23579 | /* 64689 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23580 | /* 64692 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23581 | /* 64696 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23582 | /* 64699 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23583 | /* 64705 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23584 | /* 64711 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23585 | /* 64713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23586 | /* 64716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23587 | /* 64718 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23588 | /* 64721 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 23589 | /* 64726 */ // GIR_Coverage, 3504, |
| 23590 | /* 64726 */ GIR_EraseRootFromParent_Done, |
| 23591 | /* 64727 */ // Label 1991: @64727 |
| 23592 | /* 64727 */ GIM_Reject, |
| 23593 | /* 64728 */ // Label 1989: @64728 |
| 23594 | /* 64728 */ GIM_Reject, |
| 23595 | /* 64729 */ // Label 1986: @64729 |
| 23596 | /* 64729 */ GIM_Try, /*On fail goto*//*Label 1992*/ GIMT_Encode4(64953), |
| 23597 | /* 64734 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav), |
| 23598 | /* 64739 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1995*/ GIMT_Encode4(64952), |
| 23599 | /* 64750 */ /*GILLT_s16*//*Label 1993*/ GIMT_Encode4(64758), |
| 23600 | /* 64754 */ /*GILLT_s32*//*Label 1994*/ GIMT_Encode4(64855), |
| 23601 | /* 64758 */ // Label 1993: @64758 |
| 23602 | /* 64758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1996*/ GIMT_Encode4(64854), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3510 // |
| 23603 | /* 64765 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 23604 | /* 64768 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23605 | /* 64771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23606 | /* 64775 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23607 | /* 64779 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23608 | /* 64783 */ // (intrinsic_wo_chain:{ *:[f16] } 3772:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 23609 | /* 64783 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23610 | /* 64786 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23611 | /* 64790 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23612 | /* 64795 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23613 | /* 64799 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23614 | /* 64804 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23615 | /* 64807 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf16), |
| 23616 | /* 64811 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23617 | /* 64816 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23618 | /* 64819 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23619 | /* 64823 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23620 | /* 64826 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23621 | /* 64832 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23622 | /* 64838 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23623 | /* 64840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23624 | /* 64843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23625 | /* 64845 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23626 | /* 64848 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 23627 | /* 64853 */ // GIR_Coverage, 3510, |
| 23628 | /* 64853 */ GIR_EraseRootFromParent_Done, |
| 23629 | /* 64854 */ // Label 1996: @64854 |
| 23630 | /* 64854 */ GIM_Reject, |
| 23631 | /* 64855 */ // Label 1994: @64855 |
| 23632 | /* 64855 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1997*/ GIMT_Encode4(64951), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3508 // |
| 23633 | /* 64862 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23634 | /* 64865 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23635 | /* 64868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23636 | /* 64872 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23637 | /* 64876 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23638 | /* 64880 */ // (intrinsic_wo_chain:{ *:[f32] } 3772:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 23639 | /* 64880 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23640 | /* 64883 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23641 | /* 64887 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23642 | /* 64892 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23643 | /* 64896 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23644 | /* 64901 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23645 | /* 64904 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf32), |
| 23646 | /* 64908 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23647 | /* 64913 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23648 | /* 64916 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23649 | /* 64920 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23650 | /* 64923 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23651 | /* 64929 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23652 | /* 64935 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23653 | /* 64937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23654 | /* 64940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23655 | /* 64942 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23656 | /* 64945 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 23657 | /* 64950 */ // GIR_Coverage, 3508, |
| 23658 | /* 64950 */ GIR_EraseRootFromParent_Done, |
| 23659 | /* 64951 */ // Label 1997: @64951 |
| 23660 | /* 64951 */ GIM_Reject, |
| 23661 | /* 64952 */ // Label 1995: @64952 |
| 23662 | /* 64952 */ GIM_Reject, |
| 23663 | /* 64953 */ // Label 1992: @64953 |
| 23664 | /* 64953 */ GIM_Try, /*On fail goto*//*Label 1998*/ GIMT_Encode4(65139), |
| 23665 | /* 64958 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav), |
| 23666 | /* 64963 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23667 | /* 64966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23668 | /* 64969 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2002*/ GIMT_Encode4(65138), |
| 23669 | /* 64980 */ /*GILLT_v16s8*//*Label 1999*/ GIMT_Encode4(65000), GIMT_Encode4(0), |
| 23670 | /* 64988 */ /*GILLT_v8s16*//*Label 2000*/ GIMT_Encode4(65046), GIMT_Encode4(0), |
| 23671 | /* 64996 */ /*GILLT_v4s32*//*Label 2001*/ GIMT_Encode4(65092), |
| 23672 | /* 65000 */ // Label 1999: @65000 |
| 23673 | /* 65000 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2003*/ GIMT_Encode4(65045), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3560 // |
| 23674 | /* 65007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23675 | /* 65011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23676 | /* 65015 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23677 | /* 65019 */ // (intrinsic_wo_chain:{ *:[i32] } 3779:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMINAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 23678 | /* 65019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs8), |
| 23679 | /* 65022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23680 | /* 65024 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23681 | /* 65026 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23682 | /* 65028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23683 | /* 65031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23684 | /* 65037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23685 | /* 65043 */ GIR_RootConstrainSelectedInstOperands, |
| 23686 | /* 65044 */ // GIR_Coverage, 3560, |
| 23687 | /* 65044 */ GIR_EraseRootFromParent_Done, |
| 23688 | /* 65045 */ // Label 2003: @65045 |
| 23689 | /* 65045 */ GIM_Reject, |
| 23690 | /* 65046 */ // Label 2000: @65046 |
| 23691 | /* 65046 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2004*/ GIMT_Encode4(65091), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3562 // |
| 23692 | /* 65053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23693 | /* 65057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23694 | /* 65061 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23695 | /* 65065 */ // (intrinsic_wo_chain:{ *:[i32] } 3779:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMINAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 23696 | /* 65065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs16), |
| 23697 | /* 65068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23698 | /* 65070 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23699 | /* 65072 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23700 | /* 65074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23701 | /* 65077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23702 | /* 65083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23703 | /* 65089 */ GIR_RootConstrainSelectedInstOperands, |
| 23704 | /* 65090 */ // GIR_Coverage, 3562, |
| 23705 | /* 65090 */ GIR_EraseRootFromParent_Done, |
| 23706 | /* 65091 */ // Label 2004: @65091 |
| 23707 | /* 65091 */ GIM_Reject, |
| 23708 | /* 65092 */ // Label 2001: @65092 |
| 23709 | /* 65092 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2005*/ GIMT_Encode4(65137), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3564 // |
| 23710 | /* 65099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23711 | /* 65103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23712 | /* 65107 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23713 | /* 65111 */ // (intrinsic_wo_chain:{ *:[i32] } 3779:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMINAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 23714 | /* 65111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs32), |
| 23715 | /* 65114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23716 | /* 65116 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23717 | /* 65118 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23718 | /* 65120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23719 | /* 65123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23720 | /* 65129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23721 | /* 65135 */ GIR_RootConstrainSelectedInstOperands, |
| 23722 | /* 65136 */ // GIR_Coverage, 3564, |
| 23723 | /* 65136 */ GIR_EraseRootFromParent_Done, |
| 23724 | /* 65137 */ // Label 2005: @65137 |
| 23725 | /* 65137 */ GIM_Reject, |
| 23726 | /* 65138 */ // Label 2002: @65138 |
| 23727 | /* 65138 */ GIM_Reject, |
| 23728 | /* 65139 */ // Label 1998: @65139 |
| 23729 | /* 65139 */ GIM_Try, /*On fail goto*//*Label 2006*/ GIMT_Encode4(65325), |
| 23730 | /* 65144 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav), |
| 23731 | /* 65149 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23732 | /* 65152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23733 | /* 65155 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2010*/ GIMT_Encode4(65324), |
| 23734 | /* 65166 */ /*GILLT_v16s8*//*Label 2007*/ GIMT_Encode4(65186), GIMT_Encode4(0), |
| 23735 | /* 65174 */ /*GILLT_v8s16*//*Label 2008*/ GIMT_Encode4(65232), GIMT_Encode4(0), |
| 23736 | /* 65182 */ /*GILLT_v4s32*//*Label 2009*/ GIMT_Encode4(65278), |
| 23737 | /* 65186 */ // Label 2007: @65186 |
| 23738 | /* 65186 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2011*/ GIMT_Encode4(65231), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3566 // |
| 23739 | /* 65193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23740 | /* 65197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23741 | /* 65201 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23742 | /* 65205 */ // (intrinsic_wo_chain:{ *:[i32] } 3770:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMAXAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 23743 | /* 65205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs8), |
| 23744 | /* 65208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23745 | /* 65210 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23746 | /* 65212 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23747 | /* 65214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23748 | /* 65217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23749 | /* 65223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23750 | /* 65229 */ GIR_RootConstrainSelectedInstOperands, |
| 23751 | /* 65230 */ // GIR_Coverage, 3566, |
| 23752 | /* 65230 */ GIR_EraseRootFromParent_Done, |
| 23753 | /* 65231 */ // Label 2011: @65231 |
| 23754 | /* 65231 */ GIM_Reject, |
| 23755 | /* 65232 */ // Label 2008: @65232 |
| 23756 | /* 65232 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2012*/ GIMT_Encode4(65277), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3568 // |
| 23757 | /* 65239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23758 | /* 65243 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23759 | /* 65247 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23760 | /* 65251 */ // (intrinsic_wo_chain:{ *:[i32] } 3770:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMAXAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 23761 | /* 65251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs16), |
| 23762 | /* 65254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23763 | /* 65256 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23764 | /* 65258 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23765 | /* 65260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23766 | /* 65263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23767 | /* 65269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23768 | /* 65275 */ GIR_RootConstrainSelectedInstOperands, |
| 23769 | /* 65276 */ // GIR_Coverage, 3568, |
| 23770 | /* 65276 */ GIR_EraseRootFromParent_Done, |
| 23771 | /* 65277 */ // Label 2012: @65277 |
| 23772 | /* 65277 */ GIM_Reject, |
| 23773 | /* 65278 */ // Label 2009: @65278 |
| 23774 | /* 65278 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2013*/ GIMT_Encode4(65323), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3570 // |
| 23775 | /* 65285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23776 | /* 65289 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23777 | /* 65293 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23778 | /* 65297 */ // (intrinsic_wo_chain:{ *:[i32] } 3770:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMAXAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 23779 | /* 65297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs32), |
| 23780 | /* 65300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23781 | /* 65302 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23782 | /* 65304 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23783 | /* 65306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23784 | /* 65309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23785 | /* 65315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23786 | /* 65321 */ GIR_RootConstrainSelectedInstOperands, |
| 23787 | /* 65322 */ // GIR_Coverage, 3570, |
| 23788 | /* 65322 */ GIR_EraseRootFromParent_Done, |
| 23789 | /* 65323 */ // Label 2013: @65323 |
| 23790 | /* 65323 */ GIM_Reject, |
| 23791 | /* 65324 */ // Label 2010: @65324 |
| 23792 | /* 65324 */ GIM_Reject, |
| 23793 | /* 65325 */ // Label 2006: @65325 |
| 23794 | /* 65325 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2014*/ GIMT_Encode4(65399), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3677 // |
| 23795 | /* 65332 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm), |
| 23796 | /* 65337 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23797 | /* 65340 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23798 | /* 65343 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23799 | /* 65346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23800 | /* 65350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23801 | /* 65354 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23802 | /* 65358 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3875:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 23803 | /* 65358 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23804 | /* 65361 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23805 | /* 65365 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23806 | /* 65370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16), |
| 23807 | /* 65373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23808 | /* 65375 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23809 | /* 65377 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23810 | /* 65379 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23811 | /* 65382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23812 | /* 65388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23813 | /* 65394 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23814 | /* 65397 */ GIR_RootConstrainSelectedInstOperands, |
| 23815 | /* 65398 */ // GIR_Coverage, 3677, |
| 23816 | /* 65398 */ GIR_EraseRootFromParent_Done, |
| 23817 | /* 65399 */ // Label 2014: @65399 |
| 23818 | /* 65399 */ GIM_Try, /*On fail goto*//*Label 2015*/ GIMT_Encode4(65567), |
| 23819 | /* 65404 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm), |
| 23820 | /* 65409 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2018*/ GIMT_Encode4(65566), |
| 23821 | /* 65420 */ /*GILLT_v8s16*//*Label 2016*/ GIMT_Encode4(65432), GIMT_Encode4(0), |
| 23822 | /* 65428 */ /*GILLT_v4s32*//*Label 2017*/ GIMT_Encode4(65499), |
| 23823 | /* 65432 */ // Label 2016: @65432 |
| 23824 | /* 65432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2019*/ GIMT_Encode4(65498), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3687 // |
| 23825 | /* 65439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23826 | /* 65442 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23827 | /* 65445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23828 | /* 65449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23829 | /* 65453 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23830 | /* 65457 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3878:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 23831 | /* 65457 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23832 | /* 65460 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23833 | /* 65464 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23834 | /* 65469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16), |
| 23835 | /* 65472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23836 | /* 65474 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23837 | /* 65476 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23838 | /* 65478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23839 | /* 65481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23840 | /* 65487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23841 | /* 65493 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23842 | /* 65496 */ GIR_RootConstrainSelectedInstOperands, |
| 23843 | /* 65497 */ // GIR_Coverage, 3687, |
| 23844 | /* 65497 */ GIR_EraseRootFromParent_Done, |
| 23845 | /* 65498 */ // Label 2019: @65498 |
| 23846 | /* 65498 */ GIM_Reject, |
| 23847 | /* 65499 */ // Label 2017: @65499 |
| 23848 | /* 65499 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2020*/ GIMT_Encode4(65565), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3682 // |
| 23849 | /* 65506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23850 | /* 65509 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23851 | /* 65512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23852 | /* 65516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23853 | /* 65520 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23854 | /* 65524 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3878:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 23855 | /* 65524 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23856 | /* 65527 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23857 | /* 65531 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23858 | /* 65536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32), |
| 23859 | /* 65539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23860 | /* 65541 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23861 | /* 65543 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23862 | /* 65545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23863 | /* 65548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23864 | /* 65554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23865 | /* 65560 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23866 | /* 65563 */ GIR_RootConstrainSelectedInstOperands, |
| 23867 | /* 65564 */ // GIR_Coverage, 3682, |
| 23868 | /* 65564 */ GIR_EraseRootFromParent_Done, |
| 23869 | /* 65565 */ // Label 2020: @65565 |
| 23870 | /* 65565 */ GIM_Reject, |
| 23871 | /* 65566 */ // Label 2018: @65566 |
| 23872 | /* 65566 */ GIM_Reject, |
| 23873 | /* 65567 */ // Label 2015: @65567 |
| 23874 | /* 65567 */ GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(65810), |
| 23875 | /* 65572 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh), |
| 23876 | /* 65577 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2025*/ GIMT_Encode4(65809), |
| 23877 | /* 65588 */ /*GILLT_v16s8*//*Label 2022*/ GIMT_Encode4(65608), GIMT_Encode4(0), |
| 23878 | /* 65596 */ /*GILLT_v8s16*//*Label 2023*/ GIMT_Encode4(65675), GIMT_Encode4(0), |
| 23879 | /* 65604 */ /*GILLT_v4s32*//*Label 2024*/ GIMT_Encode4(65742), |
| 23880 | /* 65608 */ // Label 2022: @65608 |
| 23881 | /* 65608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2026*/ GIMT_Encode4(65674), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3867 // |
| 23882 | /* 65615 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23883 | /* 65618 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23884 | /* 65621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23885 | /* 65625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23886 | /* 65629 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23887 | /* 65633 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3898:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23888 | /* 65633 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23889 | /* 65636 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23890 | /* 65640 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23891 | /* 65645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi8), |
| 23892 | /* 65648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23893 | /* 65650 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23894 | /* 65652 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23895 | /* 65654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23896 | /* 65657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23897 | /* 65663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23898 | /* 65669 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23899 | /* 65672 */ GIR_RootConstrainSelectedInstOperands, |
| 23900 | /* 65673 */ // GIR_Coverage, 3867, |
| 23901 | /* 65673 */ GIR_EraseRootFromParent_Done, |
| 23902 | /* 65674 */ // Label 2026: @65674 |
| 23903 | /* 65674 */ GIM_Reject, |
| 23904 | /* 65675 */ // Label 2023: @65675 |
| 23905 | /* 65675 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2027*/ GIMT_Encode4(65741), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3874 // |
| 23906 | /* 65682 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23907 | /* 65685 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23908 | /* 65688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23909 | /* 65692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23910 | /* 65696 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23911 | /* 65700 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3898:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23912 | /* 65700 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23913 | /* 65703 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23914 | /* 65707 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23915 | /* 65712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi16), |
| 23916 | /* 65715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23917 | /* 65717 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23918 | /* 65719 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23919 | /* 65721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23920 | /* 65724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23921 | /* 65730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23922 | /* 65736 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23923 | /* 65739 */ GIR_RootConstrainSelectedInstOperands, |
| 23924 | /* 65740 */ // GIR_Coverage, 3874, |
| 23925 | /* 65740 */ GIR_EraseRootFromParent_Done, |
| 23926 | /* 65741 */ // Label 2027: @65741 |
| 23927 | /* 65741 */ GIM_Reject, |
| 23928 | /* 65742 */ // Label 2024: @65742 |
| 23929 | /* 65742 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2028*/ GIMT_Encode4(65808), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3878 // |
| 23930 | /* 65749 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23931 | /* 65752 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23932 | /* 65755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23933 | /* 65759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23934 | /* 65763 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23935 | /* 65767 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3898:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23936 | /* 65767 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23937 | /* 65770 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23938 | /* 65774 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23939 | /* 65779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi32), |
| 23940 | /* 65782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23941 | /* 65784 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23942 | /* 65786 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23943 | /* 65788 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23944 | /* 65791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23945 | /* 65797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23946 | /* 65803 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23947 | /* 65806 */ GIR_RootConstrainSelectedInstOperands, |
| 23948 | /* 65807 */ // GIR_Coverage, 3878, |
| 23949 | /* 65807 */ GIR_EraseRootFromParent_Done, |
| 23950 | /* 65808 */ // Label 2028: @65808 |
| 23951 | /* 65808 */ GIM_Reject, |
| 23952 | /* 65809 */ // Label 2025: @65809 |
| 23953 | /* 65809 */ GIM_Reject, |
| 23954 | /* 65810 */ // Label 2021: @65810 |
| 23955 | /* 65810 */ GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(66053), |
| 23956 | /* 65815 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh), |
| 23957 | /* 65820 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2033*/ GIMT_Encode4(66052), |
| 23958 | /* 65831 */ /*GILLT_v16s8*//*Label 2030*/ GIMT_Encode4(65851), GIMT_Encode4(0), |
| 23959 | /* 65839 */ /*GILLT_v8s16*//*Label 2031*/ GIMT_Encode4(65918), GIMT_Encode4(0), |
| 23960 | /* 65847 */ /*GILLT_v4s32*//*Label 2032*/ GIMT_Encode4(65985), |
| 23961 | /* 65851 */ // Label 2030: @65851 |
| 23962 | /* 65851 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2034*/ GIMT_Encode4(65917), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3880 // |
| 23963 | /* 65858 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23964 | /* 65861 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23965 | /* 65864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23966 | /* 65868 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23967 | /* 65872 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23968 | /* 65876 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3907:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQRDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23969 | /* 65876 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23970 | /* 65879 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23971 | /* 65883 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23972 | /* 65888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi8), |
| 23973 | /* 65891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23974 | /* 65893 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23975 | /* 65895 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23976 | /* 65897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23977 | /* 65900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23978 | /* 65906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23979 | /* 65912 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23980 | /* 65915 */ GIR_RootConstrainSelectedInstOperands, |
| 23981 | /* 65916 */ // GIR_Coverage, 3880, |
| 23982 | /* 65916 */ GIR_EraseRootFromParent_Done, |
| 23983 | /* 65917 */ // Label 2034: @65917 |
| 23984 | /* 65917 */ GIM_Reject, |
| 23985 | /* 65918 */ // Label 2031: @65918 |
| 23986 | /* 65918 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2035*/ GIMT_Encode4(65984), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3882 // |
| 23987 | /* 65925 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23988 | /* 65928 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23989 | /* 65931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23990 | /* 65935 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23991 | /* 65939 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23992 | /* 65943 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3907:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQRDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23993 | /* 65943 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23994 | /* 65946 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23995 | /* 65950 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23996 | /* 65955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi16), |
| 23997 | /* 65958 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23998 | /* 65960 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23999 | /* 65962 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24000 | /* 65964 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24001 | /* 65967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24002 | /* 65973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24003 | /* 65979 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24004 | /* 65982 */ GIR_RootConstrainSelectedInstOperands, |
| 24005 | /* 65983 */ // GIR_Coverage, 3882, |
| 24006 | /* 65983 */ GIR_EraseRootFromParent_Done, |
| 24007 | /* 65984 */ // Label 2035: @65984 |
| 24008 | /* 65984 */ GIM_Reject, |
| 24009 | /* 65985 */ // Label 2032: @65985 |
| 24010 | /* 65985 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2036*/ GIMT_Encode4(66051), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3884 // |
| 24011 | /* 65992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24012 | /* 65995 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24013 | /* 65998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24014 | /* 66002 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24015 | /* 66006 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24016 | /* 66010 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3907:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQRDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 24017 | /* 66010 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24018 | /* 66013 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24019 | /* 66017 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24020 | /* 66022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi32), |
| 24021 | /* 66025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24022 | /* 66027 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24023 | /* 66029 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24024 | /* 66031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24025 | /* 66034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24026 | /* 66040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24027 | /* 66046 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24028 | /* 66049 */ GIR_RootConstrainSelectedInstOperands, |
| 24029 | /* 66050 */ // GIR_Coverage, 3884, |
| 24030 | /* 66050 */ GIR_EraseRootFromParent_Done, |
| 24031 | /* 66051 */ // Label 2036: @66051 |
| 24032 | /* 66051 */ GIM_Reject, |
| 24033 | /* 66052 */ // Label 2033: @66052 |
| 24034 | /* 66052 */ GIM_Reject, |
| 24035 | /* 66053 */ // Label 2029: @66053 |
| 24036 | /* 66053 */ GIM_Try, /*On fail goto*//*Label 2037*/ GIMT_Encode4(66221), |
| 24037 | /* 66058 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmul), |
| 24038 | /* 66063 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2040*/ GIMT_Encode4(66220), |
| 24039 | /* 66074 */ /*GILLT_v8s16*//*Label 2038*/ GIMT_Encode4(66086), GIMT_Encode4(0), |
| 24040 | /* 66082 */ /*GILLT_v4s32*//*Label 2039*/ GIMT_Encode4(66153), |
| 24041 | /* 66086 */ // Label 2038: @66086 |
| 24042 | /* 66086 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2041*/ GIMT_Encode4(66152), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4423 // |
| 24043 | /* 66093 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24044 | /* 66096 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24045 | /* 66099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24046 | /* 66103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24047 | /* 66107 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24048 | /* 66111 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3888:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 24049 | /* 66111 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24050 | /* 66114 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24051 | /* 66118 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24052 | /* 66123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16), |
| 24053 | /* 66126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24054 | /* 66128 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24055 | /* 66130 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24056 | /* 66132 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24057 | /* 66135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24058 | /* 66141 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24059 | /* 66147 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24060 | /* 66150 */ GIR_RootConstrainSelectedInstOperands, |
| 24061 | /* 66151 */ // GIR_Coverage, 4423, |
| 24062 | /* 66151 */ GIR_EraseRootFromParent_Done, |
| 24063 | /* 66152 */ // Label 2041: @66152 |
| 24064 | /* 66152 */ GIM_Reject, |
| 24065 | /* 66153 */ // Label 2039: @66153 |
| 24066 | /* 66153 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2042*/ GIMT_Encode4(66219), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4416 // |
| 24067 | /* 66160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24068 | /* 66163 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24069 | /* 66166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24070 | /* 66170 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24071 | /* 66174 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24072 | /* 66178 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3888:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 24073 | /* 66178 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24074 | /* 66181 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24075 | /* 66185 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24076 | /* 66190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32), |
| 24077 | /* 66193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24078 | /* 66195 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24079 | /* 66197 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24080 | /* 66199 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24081 | /* 66202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24082 | /* 66208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24083 | /* 66214 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24084 | /* 66217 */ GIR_RootConstrainSelectedInstOperands, |
| 24085 | /* 66218 */ // GIR_Coverage, 4416, |
| 24086 | /* 66218 */ GIR_EraseRootFromParent_Done, |
| 24087 | /* 66219 */ // Label 2042: @66219 |
| 24088 | /* 66219 */ GIM_Reject, |
| 24089 | /* 66220 */ // Label 2040: @66220 |
| 24090 | /* 66220 */ GIM_Reject, |
| 24091 | /* 66221 */ // Label 2037: @66221 |
| 24092 | /* 66221 */ GIM_Try, /*On fail goto*//*Label 2043*/ GIMT_Encode4(66389), |
| 24093 | /* 66226 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vadd), |
| 24094 | /* 66231 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2046*/ GIMT_Encode4(66388), |
| 24095 | /* 66242 */ /*GILLT_v8s16*//*Label 2044*/ GIMT_Encode4(66254), GIMT_Encode4(0), |
| 24096 | /* 66250 */ /*GILLT_v4s32*//*Label 2045*/ GIMT_Encode4(66321), |
| 24097 | /* 66254 */ // Label 2044: @66254 |
| 24098 | /* 66254 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2047*/ GIMT_Encode4(66320), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4463 // |
| 24099 | /* 66261 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24100 | /* 66264 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24101 | /* 66267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24102 | /* 66271 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24103 | /* 66275 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24104 | /* 66279 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3825:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 24105 | /* 66279 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24106 | /* 66282 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24107 | /* 66286 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24108 | /* 66291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16), |
| 24109 | /* 66294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24110 | /* 66296 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24111 | /* 66298 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24112 | /* 66300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24113 | /* 66303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24114 | /* 66309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24115 | /* 66315 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24116 | /* 66318 */ GIR_RootConstrainSelectedInstOperands, |
| 24117 | /* 66319 */ // GIR_Coverage, 4463, |
| 24118 | /* 66319 */ GIR_EraseRootFromParent_Done, |
| 24119 | /* 66320 */ // Label 2047: @66320 |
| 24120 | /* 66320 */ GIM_Reject, |
| 24121 | /* 66321 */ // Label 2045: @66321 |
| 24122 | /* 66321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2048*/ GIMT_Encode4(66387), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4456 // |
| 24123 | /* 66328 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24124 | /* 66331 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24125 | /* 66334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24126 | /* 66338 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24127 | /* 66342 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24128 | /* 66346 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3825:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 24129 | /* 66346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24130 | /* 66349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24131 | /* 66353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24132 | /* 66358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32), |
| 24133 | /* 66361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24134 | /* 66363 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24135 | /* 66365 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24136 | /* 66367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24137 | /* 66370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24138 | /* 66376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24139 | /* 66382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24140 | /* 66385 */ GIR_RootConstrainSelectedInstOperands, |
| 24141 | /* 66386 */ // GIR_Coverage, 4456, |
| 24142 | /* 66386 */ GIR_EraseRootFromParent_Done, |
| 24143 | /* 66387 */ // Label 2048: @66387 |
| 24144 | /* 66387 */ GIM_Reject, |
| 24145 | /* 66388 */ // Label 2046: @66388 |
| 24146 | /* 66388 */ GIM_Reject, |
| 24147 | /* 66389 */ // Label 2043: @66389 |
| 24148 | /* 66389 */ GIM_Try, /*On fail goto*//*Label 2049*/ GIMT_Encode4(66557), |
| 24149 | /* 66394 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsub), |
| 24150 | /* 66399 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2052*/ GIMT_Encode4(66556), |
| 24151 | /* 66410 */ /*GILLT_v8s16*//*Label 2050*/ GIMT_Encode4(66422), GIMT_Encode4(0), |
| 24152 | /* 66418 */ /*GILLT_v4s32*//*Label 2051*/ GIMT_Encode4(66489), |
| 24153 | /* 66422 */ // Label 2050: @66422 |
| 24154 | /* 66422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2053*/ GIMT_Encode4(66488), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4477 // |
| 24155 | /* 66429 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24156 | /* 66432 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24157 | /* 66435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24158 | /* 66439 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24159 | /* 66443 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24160 | /* 66447 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3956:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 24161 | /* 66447 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24162 | /* 66450 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24163 | /* 66454 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24164 | /* 66459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16), |
| 24165 | /* 66462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24166 | /* 66464 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24167 | /* 66466 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24168 | /* 66468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24169 | /* 66471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24170 | /* 66477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24171 | /* 66483 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24172 | /* 66486 */ GIR_RootConstrainSelectedInstOperands, |
| 24173 | /* 66487 */ // GIR_Coverage, 4477, |
| 24174 | /* 66487 */ GIR_EraseRootFromParent_Done, |
| 24175 | /* 66488 */ // Label 2053: @66488 |
| 24176 | /* 66488 */ GIM_Reject, |
| 24177 | /* 66489 */ // Label 2051: @66489 |
| 24178 | /* 66489 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2054*/ GIMT_Encode4(66555), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4470 // |
| 24179 | /* 66496 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24180 | /* 66499 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24181 | /* 66502 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24182 | /* 66506 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24183 | /* 66510 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24184 | /* 66514 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3956:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 24185 | /* 66514 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24186 | /* 66517 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24187 | /* 66521 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24188 | /* 66526 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32), |
| 24189 | /* 66529 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24190 | /* 66531 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24191 | /* 66533 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24192 | /* 66535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24193 | /* 66538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24194 | /* 66544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24195 | /* 66550 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24196 | /* 66553 */ GIR_RootConstrainSelectedInstOperands, |
| 24197 | /* 66554 */ // GIR_Coverage, 4470, |
| 24198 | /* 66554 */ GIR_EraseRootFromParent_Done, |
| 24199 | /* 66555 */ // Label 2054: @66555 |
| 24200 | /* 66555 */ GIM_Reject, |
| 24201 | /* 66556 */ // Label 2052: @66556 |
| 24202 | /* 66556 */ GIM_Reject, |
| 24203 | /* 66557 */ // Label 2049: @66557 |
| 24204 | /* 66557 */ GIM_Try, /*On fail goto*//*Label 2055*/ GIMT_Encode4(66697), |
| 24205 | /* 66562 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_eq), |
| 24206 | /* 66567 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2058*/ GIMT_Encode4(66696), |
| 24207 | /* 66578 */ /*GILLT_v4s1*//*Label 2056*/ GIMT_Encode4(66586), |
| 24208 | /* 66582 */ /*GILLT_v8s1*//*Label 2057*/ GIMT_Encode4(66641), |
| 24209 | /* 66586 */ // Label 2056: @66586 |
| 24210 | /* 66586 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2059*/ GIMT_Encode4(66640), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4603 // |
| 24211 | /* 66593 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24212 | /* 66596 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24213 | /* 66599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24214 | /* 66603 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24215 | /* 66607 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24216 | /* 66611 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3757:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 0:{ *:[i32] }) |
| 24217 | /* 66611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 24218 | /* 66614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24219 | /* 66616 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24220 | /* 66618 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24221 | /* 66620 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24222 | /* 66623 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24223 | /* 66626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24224 | /* 66632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24225 | /* 66638 */ GIR_RootConstrainSelectedInstOperands, |
| 24226 | /* 66639 */ // GIR_Coverage, 4603, |
| 24227 | /* 66639 */ GIR_EraseRootFromParent_Done, |
| 24228 | /* 66640 */ // Label 2059: @66640 |
| 24229 | /* 66640 */ GIM_Reject, |
| 24230 | /* 66641 */ // Label 2057: @66641 |
| 24231 | /* 66641 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2060*/ GIMT_Encode4(66695), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4601 // |
| 24232 | /* 66648 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24233 | /* 66651 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24234 | /* 66654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24235 | /* 66658 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24236 | /* 66662 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24237 | /* 66666 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3757:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 0:{ *:[i32] }) |
| 24238 | /* 66666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 24239 | /* 66669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24240 | /* 66671 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24241 | /* 66673 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24242 | /* 66675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24243 | /* 66678 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24244 | /* 66681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24245 | /* 66687 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24246 | /* 66693 */ GIR_RootConstrainSelectedInstOperands, |
| 24247 | /* 66694 */ // GIR_Coverage, 4601, |
| 24248 | /* 66694 */ GIR_EraseRootFromParent_Done, |
| 24249 | /* 66695 */ // Label 2060: @66695 |
| 24250 | /* 66695 */ GIM_Reject, |
| 24251 | /* 66696 */ // Label 2058: @66696 |
| 24252 | /* 66696 */ GIM_Reject, |
| 24253 | /* 66697 */ // Label 2055: @66697 |
| 24254 | /* 66697 */ GIM_Try, /*On fail goto*//*Label 2061*/ GIMT_Encode4(66837), |
| 24255 | /* 66702 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ne), |
| 24256 | /* 66707 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2064*/ GIMT_Encode4(66836), |
| 24257 | /* 66718 */ /*GILLT_v4s1*//*Label 2062*/ GIMT_Encode4(66726), |
| 24258 | /* 66722 */ /*GILLT_v8s1*//*Label 2063*/ GIMT_Encode4(66781), |
| 24259 | /* 66726 */ // Label 2062: @66726 |
| 24260 | /* 66726 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2065*/ GIMT_Encode4(66780), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4692 // |
| 24261 | /* 66733 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24262 | /* 66736 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24263 | /* 66739 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24264 | /* 66743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24265 | /* 66747 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24266 | /* 66751 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3762:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 1:{ *:[i32] }) |
| 24267 | /* 66751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 24268 | /* 66754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24269 | /* 66756 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24270 | /* 66758 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24271 | /* 66760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 24272 | /* 66763 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24273 | /* 66766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24274 | /* 66772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24275 | /* 66778 */ GIR_RootConstrainSelectedInstOperands, |
| 24276 | /* 66779 */ // GIR_Coverage, 4692, |
| 24277 | /* 66779 */ GIR_EraseRootFromParent_Done, |
| 24278 | /* 66780 */ // Label 2065: @66780 |
| 24279 | /* 66780 */ GIM_Reject, |
| 24280 | /* 66781 */ // Label 2063: @66781 |
| 24281 | /* 66781 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2066*/ GIMT_Encode4(66835), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4690 // |
| 24282 | /* 66788 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24283 | /* 66791 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24284 | /* 66794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24285 | /* 66798 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24286 | /* 66802 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24287 | /* 66806 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3762:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 1:{ *:[i32] }) |
| 24288 | /* 66806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 24289 | /* 66809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24290 | /* 66811 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24291 | /* 66813 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24292 | /* 66815 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 24293 | /* 66818 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24294 | /* 66821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24295 | /* 66827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24296 | /* 66833 */ GIR_RootConstrainSelectedInstOperands, |
| 24297 | /* 66834 */ // GIR_Coverage, 4690, |
| 24298 | /* 66834 */ GIR_EraseRootFromParent_Done, |
| 24299 | /* 66835 */ // Label 2066: @66835 |
| 24300 | /* 66835 */ GIM_Reject, |
| 24301 | /* 66836 */ // Label 2064: @66836 |
| 24302 | /* 66836 */ GIM_Reject, |
| 24303 | /* 66837 */ // Label 2061: @66837 |
| 24304 | /* 66837 */ GIM_Try, /*On fail goto*//*Label 2067*/ GIMT_Encode4(66977), |
| 24305 | /* 66842 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ge), |
| 24306 | /* 66847 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2070*/ GIMT_Encode4(66976), |
| 24307 | /* 66858 */ /*GILLT_v4s1*//*Label 2068*/ GIMT_Encode4(66866), |
| 24308 | /* 66862 */ /*GILLT_v8s1*//*Label 2069*/ GIMT_Encode4(66921), |
| 24309 | /* 66866 */ // Label 2068: @66866 |
| 24310 | /* 66866 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2071*/ GIMT_Encode4(66920), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4708 // |
| 24311 | /* 66873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24312 | /* 66876 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24313 | /* 66879 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24314 | /* 66883 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24315 | /* 66887 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24316 | /* 66891 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3758:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 10:{ *:[i32] }) |
| 24317 | /* 66891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 24318 | /* 66894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24319 | /* 66896 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24320 | /* 66898 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24321 | /* 66900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/10, |
| 24322 | /* 66903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24323 | /* 66906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24324 | /* 66912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24325 | /* 66918 */ GIR_RootConstrainSelectedInstOperands, |
| 24326 | /* 66919 */ // GIR_Coverage, 4708, |
| 24327 | /* 66919 */ GIR_EraseRootFromParent_Done, |
| 24328 | /* 66920 */ // Label 2071: @66920 |
| 24329 | /* 66920 */ GIM_Reject, |
| 24330 | /* 66921 */ // Label 2069: @66921 |
| 24331 | /* 66921 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2072*/ GIMT_Encode4(66975), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4706 // |
| 24332 | /* 66928 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24333 | /* 66931 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24334 | /* 66934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24335 | /* 66938 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24336 | /* 66942 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24337 | /* 66946 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3758:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 10:{ *:[i32] }) |
| 24338 | /* 66946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 24339 | /* 66949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24340 | /* 66951 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24341 | /* 66953 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24342 | /* 66955 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/10, |
| 24343 | /* 66958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24344 | /* 66961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24345 | /* 66967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24346 | /* 66973 */ GIR_RootConstrainSelectedInstOperands, |
| 24347 | /* 66974 */ // GIR_Coverage, 4706, |
| 24348 | /* 66974 */ GIR_EraseRootFromParent_Done, |
| 24349 | /* 66975 */ // Label 2072: @66975 |
| 24350 | /* 66975 */ GIM_Reject, |
| 24351 | /* 66976 */ // Label 2070: @66976 |
| 24352 | /* 66976 */ GIM_Reject, |
| 24353 | /* 66977 */ // Label 2067: @66977 |
| 24354 | /* 66977 */ GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(67117), |
| 24355 | /* 66982 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_lt), |
| 24356 | /* 66987 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2076*/ GIMT_Encode4(67116), |
| 24357 | /* 66998 */ /*GILLT_v4s1*//*Label 2074*/ GIMT_Encode4(67006), |
| 24358 | /* 67002 */ /*GILLT_v8s1*//*Label 2075*/ GIMT_Encode4(67061), |
| 24359 | /* 67006 */ // Label 2074: @67006 |
| 24360 | /* 67006 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2077*/ GIMT_Encode4(67060), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4724 // |
| 24361 | /* 67013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24362 | /* 67016 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24363 | /* 67019 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24364 | /* 67023 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24365 | /* 67027 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24366 | /* 67031 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3761:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 11:{ *:[i32] }) |
| 24367 | /* 67031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 24368 | /* 67034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24369 | /* 67036 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24370 | /* 67038 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24371 | /* 67040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/11, |
| 24372 | /* 67043 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24373 | /* 67046 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24374 | /* 67052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24375 | /* 67058 */ GIR_RootConstrainSelectedInstOperands, |
| 24376 | /* 67059 */ // GIR_Coverage, 4724, |
| 24377 | /* 67059 */ GIR_EraseRootFromParent_Done, |
| 24378 | /* 67060 */ // Label 2077: @67060 |
| 24379 | /* 67060 */ GIM_Reject, |
| 24380 | /* 67061 */ // Label 2075: @67061 |
| 24381 | /* 67061 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2078*/ GIMT_Encode4(67115), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4722 // |
| 24382 | /* 67068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24383 | /* 67071 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24384 | /* 67074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24385 | /* 67078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24386 | /* 67082 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24387 | /* 67086 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3761:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 11:{ *:[i32] }) |
| 24388 | /* 67086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 24389 | /* 67089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24390 | /* 67091 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24391 | /* 67093 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24392 | /* 67095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/11, |
| 24393 | /* 67098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24394 | /* 67101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24395 | /* 67107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24396 | /* 67113 */ GIR_RootConstrainSelectedInstOperands, |
| 24397 | /* 67114 */ // GIR_Coverage, 4722, |
| 24398 | /* 67114 */ GIR_EraseRootFromParent_Done, |
| 24399 | /* 67115 */ // Label 2078: @67115 |
| 24400 | /* 67115 */ GIM_Reject, |
| 24401 | /* 67116 */ // Label 2076: @67116 |
| 24402 | /* 67116 */ GIM_Reject, |
| 24403 | /* 67117 */ // Label 2073: @67117 |
| 24404 | /* 67117 */ GIM_Try, /*On fail goto*//*Label 2079*/ GIMT_Encode4(67257), |
| 24405 | /* 67122 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_gt), |
| 24406 | /* 67127 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2082*/ GIMT_Encode4(67256), |
| 24407 | /* 67138 */ /*GILLT_v4s1*//*Label 2080*/ GIMT_Encode4(67146), |
| 24408 | /* 67142 */ /*GILLT_v8s1*//*Label 2081*/ GIMT_Encode4(67201), |
| 24409 | /* 67146 */ // Label 2080: @67146 |
| 24410 | /* 67146 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2083*/ GIMT_Encode4(67200), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4740 // |
| 24411 | /* 67153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24412 | /* 67156 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24413 | /* 67159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24414 | /* 67163 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24415 | /* 67167 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24416 | /* 67171 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3759:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 12:{ *:[i32] }) |
| 24417 | /* 67171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 24418 | /* 67174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24419 | /* 67176 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24420 | /* 67178 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24421 | /* 67180 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/12, |
| 24422 | /* 67183 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24423 | /* 67186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24424 | /* 67192 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24425 | /* 67198 */ GIR_RootConstrainSelectedInstOperands, |
| 24426 | /* 67199 */ // GIR_Coverage, 4740, |
| 24427 | /* 67199 */ GIR_EraseRootFromParent_Done, |
| 24428 | /* 67200 */ // Label 2083: @67200 |
| 24429 | /* 67200 */ GIM_Reject, |
| 24430 | /* 67201 */ // Label 2081: @67201 |
| 24431 | /* 67201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2084*/ GIMT_Encode4(67255), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4738 // |
| 24432 | /* 67208 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24433 | /* 67211 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24434 | /* 67214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24435 | /* 67218 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24436 | /* 67222 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24437 | /* 67226 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3759:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 12:{ *:[i32] }) |
| 24438 | /* 67226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 24439 | /* 67229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24440 | /* 67231 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24441 | /* 67233 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24442 | /* 67235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/12, |
| 24443 | /* 67238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24444 | /* 67241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24445 | /* 67247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24446 | /* 67253 */ GIR_RootConstrainSelectedInstOperands, |
| 24447 | /* 67254 */ // GIR_Coverage, 4738, |
| 24448 | /* 67254 */ GIR_EraseRootFromParent_Done, |
| 24449 | /* 67255 */ // Label 2084: @67255 |
| 24450 | /* 67255 */ GIM_Reject, |
| 24451 | /* 67256 */ // Label 2082: @67256 |
| 24452 | /* 67256 */ GIM_Reject, |
| 24453 | /* 67257 */ // Label 2079: @67257 |
| 24454 | /* 67257 */ GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(67397), |
| 24455 | /* 67262 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_le), |
| 24456 | /* 67267 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2088*/ GIMT_Encode4(67396), |
| 24457 | /* 67278 */ /*GILLT_v4s1*//*Label 2086*/ GIMT_Encode4(67286), |
| 24458 | /* 67282 */ /*GILLT_v8s1*//*Label 2087*/ GIMT_Encode4(67341), |
| 24459 | /* 67286 */ // Label 2086: @67286 |
| 24460 | /* 67286 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2089*/ GIMT_Encode4(67340), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4756 // |
| 24461 | /* 67293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24462 | /* 67296 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24463 | /* 67299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24464 | /* 67303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24465 | /* 67307 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24466 | /* 67311 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3760:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 13:{ *:[i32] }) |
| 24467 | /* 67311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 24468 | /* 67314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24469 | /* 67316 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24470 | /* 67318 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24471 | /* 67320 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/13, |
| 24472 | /* 67323 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24473 | /* 67326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24474 | /* 67332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24475 | /* 67338 */ GIR_RootConstrainSelectedInstOperands, |
| 24476 | /* 67339 */ // GIR_Coverage, 4756, |
| 24477 | /* 67339 */ GIR_EraseRootFromParent_Done, |
| 24478 | /* 67340 */ // Label 2089: @67340 |
| 24479 | /* 67340 */ GIM_Reject, |
| 24480 | /* 67341 */ // Label 2087: @67341 |
| 24481 | /* 67341 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2090*/ GIMT_Encode4(67395), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4754 // |
| 24482 | /* 67348 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24483 | /* 67351 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24484 | /* 67354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24485 | /* 67358 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24486 | /* 67362 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24487 | /* 67366 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3760:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 13:{ *:[i32] }) |
| 24488 | /* 67366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 24489 | /* 67369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24490 | /* 67371 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24491 | /* 67373 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24492 | /* 67375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/13, |
| 24493 | /* 67378 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24494 | /* 67381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24495 | /* 67387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24496 | /* 67393 */ GIR_RootConstrainSelectedInstOperands, |
| 24497 | /* 67394 */ // GIR_Coverage, 4754, |
| 24498 | /* 67394 */ GIR_EraseRootFromParent_Done, |
| 24499 | /* 67395 */ // Label 2090: @67395 |
| 24500 | /* 67395 */ GIM_Reject, |
| 24501 | /* 67396 */ // Label 2088: @67396 |
| 24502 | /* 67396 */ GIM_Reject, |
| 24503 | /* 67397 */ // Label 2085: @67397 |
| 24504 | /* 67397 */ GIM_Try, /*On fail goto*//*Label 2091*/ GIMT_Encode4(67748), |
| 24505 | /* 67402 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 24506 | /* 67407 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2095*/ GIMT_Encode4(67747), |
| 24507 | /* 67418 */ /*GILLT_v16s8*//*Label 2092*/ GIMT_Encode4(67438), GIMT_Encode4(0), |
| 24508 | /* 67426 */ /*GILLT_v8s16*//*Label 2093*/ GIMT_Encode4(67505), GIMT_Encode4(0), |
| 24509 | /* 67434 */ /*GILLT_v4s32*//*Label 2094*/ GIMT_Encode4(67626), |
| 24510 | /* 67438 */ // Label 2092: @67438 |
| 24511 | /* 67438 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2096*/ GIMT_Encode4(67504), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5278 // |
| 24512 | /* 67445 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24513 | /* 67448 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24514 | /* 67451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24515 | /* 67455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24516 | /* 67459 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24517 | /* 67463 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3826:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 24518 | /* 67463 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24519 | /* 67466 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24520 | /* 67470 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24521 | /* 67475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8), |
| 24522 | /* 67478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24523 | /* 67480 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 24524 | /* 67482 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24525 | /* 67484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24526 | /* 67487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24527 | /* 67493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24528 | /* 67499 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24529 | /* 67502 */ GIR_RootConstrainSelectedInstOperands, |
| 24530 | /* 67503 */ // GIR_Coverage, 5278, |
| 24531 | /* 67503 */ GIR_EraseRootFromParent_Done, |
| 24532 | /* 67504 */ // Label 2096: @67504 |
| 24533 | /* 67504 */ GIM_Reject, |
| 24534 | /* 67505 */ // Label 2093: @67505 |
| 24535 | /* 67505 */ GIM_Try, /*On fail goto*//*Label 2097*/ GIMT_Encode4(67625), |
| 24536 | /* 67510 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24537 | /* 67513 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24538 | /* 67516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24539 | /* 67520 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24540 | /* 67524 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24541 | /* 67528 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2098*/ GIMT_Encode4(67576), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5283 // |
| 24542 | /* 67535 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3826:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 24543 | /* 67535 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24544 | /* 67538 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24545 | /* 67542 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24546 | /* 67547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16), |
| 24547 | /* 67550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24548 | /* 67552 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 24549 | /* 67554 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24550 | /* 67556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24551 | /* 67559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24552 | /* 67565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24553 | /* 67571 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24554 | /* 67574 */ GIR_RootConstrainSelectedInstOperands, |
| 24555 | /* 67575 */ // GIR_Coverage, 5283, |
| 24556 | /* 67575 */ GIR_EraseRootFromParent_Done, |
| 24557 | /* 67576 */ // Label 2098: @67576 |
| 24558 | /* 67576 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2099*/ GIMT_Encode4(67624), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5287 // |
| 24559 | /* 67583 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3826:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 24560 | /* 67583 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24561 | /* 67586 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24562 | /* 67590 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24563 | /* 67595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16), |
| 24564 | /* 67598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24565 | /* 67600 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 24566 | /* 67602 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24567 | /* 67604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24568 | /* 67607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24569 | /* 67613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24570 | /* 67619 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24571 | /* 67622 */ GIR_RootConstrainSelectedInstOperands, |
| 24572 | /* 67623 */ // GIR_Coverage, 5287, |
| 24573 | /* 67623 */ GIR_EraseRootFromParent_Done, |
| 24574 | /* 67624 */ // Label 2099: @67624 |
| 24575 | /* 67624 */ GIM_Reject, |
| 24576 | /* 67625 */ // Label 2097: @67625 |
| 24577 | /* 67625 */ GIM_Reject, |
| 24578 | /* 67626 */ // Label 2094: @67626 |
| 24579 | /* 67626 */ GIM_Try, /*On fail goto*//*Label 2100*/ GIMT_Encode4(67746), |
| 24580 | /* 67631 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24581 | /* 67634 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24582 | /* 67637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24583 | /* 67641 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24584 | /* 67645 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24585 | /* 67649 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2101*/ GIMT_Encode4(67697), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5285 // |
| 24586 | /* 67656 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3826:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 24587 | /* 67656 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24588 | /* 67659 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24589 | /* 67663 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24590 | /* 67668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32), |
| 24591 | /* 67671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24592 | /* 67673 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 24593 | /* 67675 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24594 | /* 67677 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24595 | /* 67680 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24596 | /* 67686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24597 | /* 67692 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24598 | /* 67695 */ GIR_RootConstrainSelectedInstOperands, |
| 24599 | /* 67696 */ // GIR_Coverage, 5285, |
| 24600 | /* 67696 */ GIR_EraseRootFromParent_Done, |
| 24601 | /* 67697 */ // Label 2101: @67697 |
| 24602 | /* 67697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2102*/ GIMT_Encode4(67745), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5289 // |
| 24603 | /* 67704 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3826:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 24604 | /* 67704 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24605 | /* 67707 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24606 | /* 67711 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24607 | /* 67716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32), |
| 24608 | /* 67719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24609 | /* 67721 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 24610 | /* 67723 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24611 | /* 67725 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24612 | /* 67728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24613 | /* 67734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24614 | /* 67740 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24615 | /* 67743 */ GIR_RootConstrainSelectedInstOperands, |
| 24616 | /* 67744 */ // GIR_Coverage, 5289, |
| 24617 | /* 67744 */ GIR_EraseRootFromParent_Done, |
| 24618 | /* 67745 */ // Label 2102: @67745 |
| 24619 | /* 67745 */ GIM_Reject, |
| 24620 | /* 67746 */ // Label 2100: @67746 |
| 24621 | /* 67746 */ GIM_Reject, |
| 24622 | /* 67747 */ // Label 2095: @67747 |
| 24623 | /* 67747 */ GIM_Reject, |
| 24624 | /* 67748 */ // Label 2091: @67748 |
| 24625 | /* 67748 */ GIM_Reject, |
| 24626 | /* 67749 */ // Label 1359: @67749 |
| 24627 | /* 67749 */ GIM_Try, /*On fail goto*//*Label 2103*/ GIMT_Encode4(78162), |
| 24628 | /* 67754 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 24629 | /* 67757 */ GIM_Try, /*On fail goto*//*Label 2104*/ GIMT_Encode4(68261), |
| 24630 | /* 67762 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 24631 | /* 67767 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2108*/ GIMT_Encode4(68260), |
| 24632 | /* 67778 */ /*GILLT_v16s8*//*Label 2105*/ GIMT_Encode4(67798), GIMT_Encode4(0), |
| 24633 | /* 67786 */ /*GILLT_v8s16*//*Label 2106*/ GIMT_Encode4(67952), GIMT_Encode4(0), |
| 24634 | /* 67794 */ /*GILLT_v4s32*//*Label 2107*/ GIMT_Encode4(68106), |
| 24635 | /* 67798 */ // Label 2105: @67798 |
| 24636 | /* 67798 */ GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(67951), |
| 24637 | /* 67803 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24638 | /* 67806 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24639 | /* 67809 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24640 | /* 67812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24641 | /* 67816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24642 | /* 67820 */ GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(67885), // Rule ID 4319 // |
| 24643 | /* 67825 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24644 | /* 67829 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24645 | /* 67833 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 24646 | /* 67837 */ // MIs[1] Operand 1 |
| 24647 | /* 67837 */ // No operand predicates |
| 24648 | /* 67837 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24649 | /* 67841 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24650 | /* 67843 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3908:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 24651 | /* 67843 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24652 | /* 67846 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24653 | /* 67850 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24654 | /* 67855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms8), |
| 24655 | /* 67858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24656 | /* 67860 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24657 | /* 67862 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24658 | /* 67865 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24659 | /* 67868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24660 | /* 67874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24661 | /* 67880 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24662 | /* 67883 */ GIR_RootConstrainSelectedInstOperands, |
| 24663 | /* 67884 */ // GIR_Coverage, 4319, |
| 24664 | /* 67884 */ GIR_EraseRootFromParent_Done, |
| 24665 | /* 67885 */ // Label 2110: @67885 |
| 24666 | /* 67885 */ GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(67950), // Rule ID 4321 // |
| 24667 | /* 67890 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24668 | /* 67894 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24669 | /* 67898 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 24670 | /* 67902 */ // MIs[1] Operand 1 |
| 24671 | /* 67902 */ // No operand predicates |
| 24672 | /* 67902 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24673 | /* 67906 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24674 | /* 67908 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3908:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 24675 | /* 67908 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24676 | /* 67911 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24677 | /* 67915 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24678 | /* 67920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu8), |
| 24679 | /* 67923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24680 | /* 67925 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24681 | /* 67927 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24682 | /* 67930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24683 | /* 67933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24684 | /* 67939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24685 | /* 67945 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24686 | /* 67948 */ GIR_RootConstrainSelectedInstOperands, |
| 24687 | /* 67949 */ // GIR_Coverage, 4321, |
| 24688 | /* 67949 */ GIR_EraseRootFromParent_Done, |
| 24689 | /* 67950 */ // Label 2111: @67950 |
| 24690 | /* 67950 */ GIM_Reject, |
| 24691 | /* 67951 */ // Label 2109: @67951 |
| 24692 | /* 67951 */ GIM_Reject, |
| 24693 | /* 67952 */ // Label 2106: @67952 |
| 24694 | /* 67952 */ GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(68105), |
| 24695 | /* 67957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24696 | /* 67960 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24697 | /* 67963 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24698 | /* 67966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24699 | /* 67970 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24700 | /* 67974 */ GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(68039), // Rule ID 4323 // |
| 24701 | /* 67979 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24702 | /* 67983 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24703 | /* 67987 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 24704 | /* 67991 */ // MIs[1] Operand 1 |
| 24705 | /* 67991 */ // No operand predicates |
| 24706 | /* 67991 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24707 | /* 67995 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24708 | /* 67997 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3908:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 24709 | /* 67997 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24710 | /* 68000 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24711 | /* 68004 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24712 | /* 68009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms16), |
| 24713 | /* 68012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24714 | /* 68014 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24715 | /* 68016 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24716 | /* 68019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24717 | /* 68022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24718 | /* 68028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24719 | /* 68034 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24720 | /* 68037 */ GIR_RootConstrainSelectedInstOperands, |
| 24721 | /* 68038 */ // GIR_Coverage, 4323, |
| 24722 | /* 68038 */ GIR_EraseRootFromParent_Done, |
| 24723 | /* 68039 */ // Label 2113: @68039 |
| 24724 | /* 68039 */ GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(68104), // Rule ID 4325 // |
| 24725 | /* 68044 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24726 | /* 68048 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24727 | /* 68052 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 24728 | /* 68056 */ // MIs[1] Operand 1 |
| 24729 | /* 68056 */ // No operand predicates |
| 24730 | /* 68056 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24731 | /* 68060 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24732 | /* 68062 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3908:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 24733 | /* 68062 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24734 | /* 68065 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24735 | /* 68069 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24736 | /* 68074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu16), |
| 24737 | /* 68077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24738 | /* 68079 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24739 | /* 68081 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24740 | /* 68084 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24741 | /* 68087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24742 | /* 68093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24743 | /* 68099 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24744 | /* 68102 */ GIR_RootConstrainSelectedInstOperands, |
| 24745 | /* 68103 */ // GIR_Coverage, 4325, |
| 24746 | /* 68103 */ GIR_EraseRootFromParent_Done, |
| 24747 | /* 68104 */ // Label 2114: @68104 |
| 24748 | /* 68104 */ GIM_Reject, |
| 24749 | /* 68105 */ // Label 2112: @68105 |
| 24750 | /* 68105 */ GIM_Reject, |
| 24751 | /* 68106 */ // Label 2107: @68106 |
| 24752 | /* 68106 */ GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(68259), |
| 24753 | /* 68111 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24754 | /* 68114 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24755 | /* 68117 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24756 | /* 68120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24757 | /* 68124 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24758 | /* 68128 */ GIM_Try, /*On fail goto*//*Label 2116*/ GIMT_Encode4(68193), // Rule ID 4327 // |
| 24759 | /* 68133 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24760 | /* 68137 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24761 | /* 68141 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 24762 | /* 68145 */ // MIs[1] Operand 1 |
| 24763 | /* 68145 */ // No operand predicates |
| 24764 | /* 68145 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24765 | /* 68149 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24766 | /* 68151 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3908:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 24767 | /* 68151 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24768 | /* 68154 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24769 | /* 68158 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24770 | /* 68163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms32), |
| 24771 | /* 68166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24772 | /* 68168 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24773 | /* 68170 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24774 | /* 68173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24775 | /* 68176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24776 | /* 68182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24777 | /* 68188 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24778 | /* 68191 */ GIR_RootConstrainSelectedInstOperands, |
| 24779 | /* 68192 */ // GIR_Coverage, 4327, |
| 24780 | /* 68192 */ GIR_EraseRootFromParent_Done, |
| 24781 | /* 68193 */ // Label 2116: @68193 |
| 24782 | /* 68193 */ GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(68258), // Rule ID 4329 // |
| 24783 | /* 68198 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24784 | /* 68202 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24785 | /* 68206 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 24786 | /* 68210 */ // MIs[1] Operand 1 |
| 24787 | /* 68210 */ // No operand predicates |
| 24788 | /* 68210 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24789 | /* 68214 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24790 | /* 68216 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3908:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 24791 | /* 68216 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24792 | /* 68219 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24793 | /* 68223 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24794 | /* 68228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu32), |
| 24795 | /* 68231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24796 | /* 68233 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24797 | /* 68235 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24798 | /* 68238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24799 | /* 68241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24800 | /* 68247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24801 | /* 68253 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24802 | /* 68256 */ GIR_RootConstrainSelectedInstOperands, |
| 24803 | /* 68257 */ // GIR_Coverage, 4329, |
| 24804 | /* 68257 */ GIR_EraseRootFromParent_Done, |
| 24805 | /* 68258 */ // Label 2117: @68258 |
| 24806 | /* 68258 */ GIM_Reject, |
| 24807 | /* 68259 */ // Label 2115: @68259 |
| 24808 | /* 68259 */ GIM_Reject, |
| 24809 | /* 68260 */ // Label 2108: @68260 |
| 24810 | /* 68260 */ GIM_Reject, |
| 24811 | /* 68261 */ // Label 2104: @68261 |
| 24812 | /* 68261 */ GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(68765), |
| 24813 | /* 68266 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 24814 | /* 68271 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2122*/ GIMT_Encode4(68764), |
| 24815 | /* 68282 */ /*GILLT_v16s8*//*Label 2119*/ GIMT_Encode4(68302), GIMT_Encode4(0), |
| 24816 | /* 68290 */ /*GILLT_v8s16*//*Label 2120*/ GIMT_Encode4(68456), GIMT_Encode4(0), |
| 24817 | /* 68298 */ /*GILLT_v4s32*//*Label 2121*/ GIMT_Encode4(68610), |
| 24818 | /* 68302 */ // Label 2119: @68302 |
| 24819 | /* 68302 */ GIM_Try, /*On fail goto*//*Label 2123*/ GIMT_Encode4(68455), |
| 24820 | /* 68307 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24821 | /* 68310 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24822 | /* 68313 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24823 | /* 68316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24824 | /* 68320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24825 | /* 68324 */ GIM_Try, /*On fail goto*//*Label 2124*/ GIMT_Encode4(68389), // Rule ID 4337 // |
| 24826 | /* 68329 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24827 | /* 68333 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24828 | /* 68337 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 24829 | /* 68341 */ // MIs[1] Operand 1 |
| 24830 | /* 68341 */ // No operand predicates |
| 24831 | /* 68341 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24832 | /* 68345 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24833 | /* 68347 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3930:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) |
| 24834 | /* 68347 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24835 | /* 68350 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24836 | /* 68354 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24837 | /* 68359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms8), |
| 24838 | /* 68362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24839 | /* 68364 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24840 | /* 68366 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24841 | /* 68369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24842 | /* 68372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24843 | /* 68378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24844 | /* 68384 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24845 | /* 68387 */ GIR_RootConstrainSelectedInstOperands, |
| 24846 | /* 68388 */ // GIR_Coverage, 4337, |
| 24847 | /* 68388 */ GIR_EraseRootFromParent_Done, |
| 24848 | /* 68389 */ // Label 2124: @68389 |
| 24849 | /* 68389 */ GIM_Try, /*On fail goto*//*Label 2125*/ GIMT_Encode4(68454), // Rule ID 4339 // |
| 24850 | /* 68394 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24851 | /* 68398 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24852 | /* 68402 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 24853 | /* 68406 */ // MIs[1] Operand 1 |
| 24854 | /* 68406 */ // No operand predicates |
| 24855 | /* 68406 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24856 | /* 68410 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24857 | /* 68412 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3930:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) |
| 24858 | /* 68412 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24859 | /* 68415 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24860 | /* 68419 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24861 | /* 68424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu8), |
| 24862 | /* 68427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24863 | /* 68429 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24864 | /* 68431 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24865 | /* 68434 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24866 | /* 68437 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24867 | /* 68443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24868 | /* 68449 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24869 | /* 68452 */ GIR_RootConstrainSelectedInstOperands, |
| 24870 | /* 68453 */ // GIR_Coverage, 4339, |
| 24871 | /* 68453 */ GIR_EraseRootFromParent_Done, |
| 24872 | /* 68454 */ // Label 2125: @68454 |
| 24873 | /* 68454 */ GIM_Reject, |
| 24874 | /* 68455 */ // Label 2123: @68455 |
| 24875 | /* 68455 */ GIM_Reject, |
| 24876 | /* 68456 */ // Label 2120: @68456 |
| 24877 | /* 68456 */ GIM_Try, /*On fail goto*//*Label 2126*/ GIMT_Encode4(68609), |
| 24878 | /* 68461 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24879 | /* 68464 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24880 | /* 68467 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24881 | /* 68470 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24882 | /* 68474 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24883 | /* 68478 */ GIM_Try, /*On fail goto*//*Label 2127*/ GIMT_Encode4(68543), // Rule ID 4341 // |
| 24884 | /* 68483 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24885 | /* 68487 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24886 | /* 68491 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 24887 | /* 68495 */ // MIs[1] Operand 1 |
| 24888 | /* 68495 */ // No operand predicates |
| 24889 | /* 68495 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24890 | /* 68499 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24891 | /* 68501 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3930:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) |
| 24892 | /* 68501 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24893 | /* 68504 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24894 | /* 68508 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24895 | /* 68513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms16), |
| 24896 | /* 68516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24897 | /* 68518 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24898 | /* 68520 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24899 | /* 68523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24900 | /* 68526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24901 | /* 68532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24902 | /* 68538 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24903 | /* 68541 */ GIR_RootConstrainSelectedInstOperands, |
| 24904 | /* 68542 */ // GIR_Coverage, 4341, |
| 24905 | /* 68542 */ GIR_EraseRootFromParent_Done, |
| 24906 | /* 68543 */ // Label 2127: @68543 |
| 24907 | /* 68543 */ GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(68608), // Rule ID 4343 // |
| 24908 | /* 68548 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24909 | /* 68552 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24910 | /* 68556 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 24911 | /* 68560 */ // MIs[1] Operand 1 |
| 24912 | /* 68560 */ // No operand predicates |
| 24913 | /* 68560 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24914 | /* 68564 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24915 | /* 68566 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3930:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) |
| 24916 | /* 68566 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24917 | /* 68569 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24918 | /* 68573 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24919 | /* 68578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu16), |
| 24920 | /* 68581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24921 | /* 68583 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24922 | /* 68585 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24923 | /* 68588 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24924 | /* 68591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24925 | /* 68597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24926 | /* 68603 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24927 | /* 68606 */ GIR_RootConstrainSelectedInstOperands, |
| 24928 | /* 68607 */ // GIR_Coverage, 4343, |
| 24929 | /* 68607 */ GIR_EraseRootFromParent_Done, |
| 24930 | /* 68608 */ // Label 2128: @68608 |
| 24931 | /* 68608 */ GIM_Reject, |
| 24932 | /* 68609 */ // Label 2126: @68609 |
| 24933 | /* 68609 */ GIM_Reject, |
| 24934 | /* 68610 */ // Label 2121: @68610 |
| 24935 | /* 68610 */ GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(68763), |
| 24936 | /* 68615 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24937 | /* 68618 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24938 | /* 68621 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24939 | /* 68624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24940 | /* 68628 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24941 | /* 68632 */ GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(68697), // Rule ID 4345 // |
| 24942 | /* 68637 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24943 | /* 68641 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24944 | /* 68645 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32), |
| 24945 | /* 68649 */ // MIs[1] Operand 1 |
| 24946 | /* 68649 */ // No operand predicates |
| 24947 | /* 68649 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24948 | /* 68653 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24949 | /* 68655 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3930:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) |
| 24950 | /* 68655 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24951 | /* 68658 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24952 | /* 68662 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24953 | /* 68667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms32), |
| 24954 | /* 68670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24955 | /* 68672 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24956 | /* 68674 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24957 | /* 68677 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24958 | /* 68680 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24959 | /* 68686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24960 | /* 68692 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24961 | /* 68695 */ GIR_RootConstrainSelectedInstOperands, |
| 24962 | /* 68696 */ // GIR_Coverage, 4345, |
| 24963 | /* 68696 */ GIR_EraseRootFromParent_Done, |
| 24964 | /* 68697 */ // Label 2130: @68697 |
| 24965 | /* 68697 */ GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(68762), // Rule ID 4347 // |
| 24966 | /* 68702 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24967 | /* 68706 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24968 | /* 68710 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32), |
| 24969 | /* 68714 */ // MIs[1] Operand 1 |
| 24970 | /* 68714 */ // No operand predicates |
| 24971 | /* 68714 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24972 | /* 68718 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24973 | /* 68720 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3930:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) |
| 24974 | /* 68720 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24975 | /* 68723 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24976 | /* 68727 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24977 | /* 68732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu32), |
| 24978 | /* 68735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24979 | /* 68737 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24980 | /* 68739 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24981 | /* 68742 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24982 | /* 68745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24983 | /* 68751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24984 | /* 68757 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24985 | /* 68760 */ GIR_RootConstrainSelectedInstOperands, |
| 24986 | /* 68761 */ // GIR_Coverage, 4347, |
| 24987 | /* 68761 */ GIR_EraseRootFromParent_Done, |
| 24988 | /* 68762 */ // Label 2131: @68762 |
| 24989 | /* 68762 */ GIM_Reject, |
| 24990 | /* 68763 */ // Label 2129: @68763 |
| 24991 | /* 68763 */ GIM_Reject, |
| 24992 | /* 68764 */ // Label 2122: @68764 |
| 24993 | /* 68764 */ GIM_Reject, |
| 24994 | /* 68765 */ // Label 2118: @68765 |
| 24995 | /* 68765 */ GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(69367), |
| 24996 | /* 68770 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 24997 | /* 68775 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2135*/ GIMT_Encode4(69366), |
| 24998 | /* 68786 */ /*GILLT_v8s16*//*Label 2133*/ GIMT_Encode4(68798), GIMT_Encode4(0), |
| 24999 | /* 68794 */ /*GILLT_v4s32*//*Label 2134*/ GIMT_Encode4(69082), |
| 25000 | /* 68798 */ // Label 2133: @68798 |
| 25001 | /* 68798 */ GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(69081), |
| 25002 | /* 68803 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25003 | /* 68806 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25004 | /* 68809 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25005 | /* 68812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25006 | /* 68816 */ GIM_Try, /*On fail goto*//*Label 2137*/ GIMT_Encode4(68948), |
| 25007 | /* 68821 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 25008 | /* 68825 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25009 | /* 68829 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2138*/ GIMT_Encode4(68888), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4493 // |
| 25010 | /* 68836 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25011 | /* 68840 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25012 | /* 68844 */ // MIs[1] Operand 1 |
| 25013 | /* 68844 */ // No operand predicates |
| 25014 | /* 68844 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25015 | /* 68846 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3839:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16s16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25016 | /* 68846 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25017 | /* 68849 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25018 | /* 68853 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25019 | /* 68858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16_fix), |
| 25020 | /* 68861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25021 | /* 68863 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25022 | /* 68865 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25023 | /* 68868 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25024 | /* 68871 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25025 | /* 68877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25026 | /* 68883 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25027 | /* 68886 */ GIR_RootConstrainSelectedInstOperands, |
| 25028 | /* 68887 */ // GIR_Coverage, 4493, |
| 25029 | /* 68887 */ GIR_EraseRootFromParent_Done, |
| 25030 | /* 68888 */ // Label 2138: @68888 |
| 25031 | /* 68888 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2139*/ GIMT_Encode4(68947), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4495 // |
| 25032 | /* 68895 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25033 | /* 68899 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25034 | /* 68903 */ // MIs[1] Operand 1 |
| 25035 | /* 68903 */ // No operand predicates |
| 25036 | /* 68903 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25037 | /* 68905 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3839:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25038 | /* 68905 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25039 | /* 68908 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25040 | /* 68912 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25041 | /* 68917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16_fix), |
| 25042 | /* 68920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25043 | /* 68922 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25044 | /* 68924 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25045 | /* 68927 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25046 | /* 68930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25047 | /* 68936 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25048 | /* 68942 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25049 | /* 68945 */ GIR_RootConstrainSelectedInstOperands, |
| 25050 | /* 68946 */ // GIR_Coverage, 4495, |
| 25051 | /* 68946 */ GIR_EraseRootFromParent_Done, |
| 25052 | /* 68947 */ // Label 2139: @68947 |
| 25053 | /* 68947 */ GIM_Reject, |
| 25054 | /* 68948 */ // Label 2137: @68948 |
| 25055 | /* 68948 */ GIM_Try, /*On fail goto*//*Label 2140*/ GIMT_Encode4(69080), |
| 25056 | /* 68953 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 25057 | /* 68957 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25058 | /* 68961 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2141*/ GIMT_Encode4(69020), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4497 // |
| 25059 | /* 68968 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25060 | /* 68972 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25061 | /* 68976 */ // MIs[1] Operand 1 |
| 25062 | /* 68976 */ // No operand predicates |
| 25063 | /* 68976 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25064 | /* 68978 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3839:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16u16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25065 | /* 68978 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25066 | /* 68981 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25067 | /* 68985 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25068 | /* 68990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16_fix), |
| 25069 | /* 68993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25070 | /* 68995 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25071 | /* 68997 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25072 | /* 69000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25073 | /* 69003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25074 | /* 69009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25075 | /* 69015 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25076 | /* 69018 */ GIR_RootConstrainSelectedInstOperands, |
| 25077 | /* 69019 */ // GIR_Coverage, 4497, |
| 25078 | /* 69019 */ GIR_EraseRootFromParent_Done, |
| 25079 | /* 69020 */ // Label 2141: @69020 |
| 25080 | /* 69020 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2142*/ GIMT_Encode4(69079), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4499 // |
| 25081 | /* 69027 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25082 | /* 69031 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25083 | /* 69035 */ // MIs[1] Operand 1 |
| 25084 | /* 69035 */ // No operand predicates |
| 25085 | /* 69035 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25086 | /* 69037 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3839:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25087 | /* 69037 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25088 | /* 69040 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25089 | /* 69044 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25090 | /* 69049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16_fix), |
| 25091 | /* 69052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25092 | /* 69054 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25093 | /* 69056 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25094 | /* 69059 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25095 | /* 69062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25096 | /* 69068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25097 | /* 69074 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25098 | /* 69077 */ GIR_RootConstrainSelectedInstOperands, |
| 25099 | /* 69078 */ // GIR_Coverage, 4499, |
| 25100 | /* 69078 */ GIR_EraseRootFromParent_Done, |
| 25101 | /* 69079 */ // Label 2142: @69079 |
| 25102 | /* 69079 */ GIM_Reject, |
| 25103 | /* 69080 */ // Label 2140: @69080 |
| 25104 | /* 69080 */ GIM_Reject, |
| 25105 | /* 69081 */ // Label 2136: @69081 |
| 25106 | /* 69081 */ GIM_Reject, |
| 25107 | /* 69082 */ // Label 2134: @69082 |
| 25108 | /* 69082 */ GIM_Try, /*On fail goto*//*Label 2143*/ GIMT_Encode4(69365), |
| 25109 | /* 69087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25110 | /* 69090 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25111 | /* 69093 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25112 | /* 69096 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25113 | /* 69100 */ GIM_Try, /*On fail goto*//*Label 2144*/ GIMT_Encode4(69232), |
| 25114 | /* 69105 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 25115 | /* 69109 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25116 | /* 69113 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2145*/ GIMT_Encode4(69172), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4501 // |
| 25117 | /* 69120 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25118 | /* 69124 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25119 | /* 69128 */ // MIs[1] Operand 1 |
| 25120 | /* 69128 */ // No operand predicates |
| 25121 | /* 69128 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25122 | /* 69130 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3839:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32s32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25123 | /* 69130 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25124 | /* 69133 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25125 | /* 69137 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25126 | /* 69142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32_fix), |
| 25127 | /* 69145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25128 | /* 69147 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25129 | /* 69149 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25130 | /* 69152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25131 | /* 69155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25132 | /* 69161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25133 | /* 69167 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25134 | /* 69170 */ GIR_RootConstrainSelectedInstOperands, |
| 25135 | /* 69171 */ // GIR_Coverage, 4501, |
| 25136 | /* 69171 */ GIR_EraseRootFromParent_Done, |
| 25137 | /* 69172 */ // Label 2145: @69172 |
| 25138 | /* 69172 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2146*/ GIMT_Encode4(69231), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4503 // |
| 25139 | /* 69179 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25140 | /* 69183 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25141 | /* 69187 */ // MIs[1] Operand 1 |
| 25142 | /* 69187 */ // No operand predicates |
| 25143 | /* 69187 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25144 | /* 69189 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3839:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25145 | /* 69189 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25146 | /* 69192 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25147 | /* 69196 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25148 | /* 69201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32_fix), |
| 25149 | /* 69204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25150 | /* 69206 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25151 | /* 69208 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25152 | /* 69211 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25153 | /* 69214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25154 | /* 69220 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25155 | /* 69226 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25156 | /* 69229 */ GIR_RootConstrainSelectedInstOperands, |
| 25157 | /* 69230 */ // GIR_Coverage, 4503, |
| 25158 | /* 69230 */ GIR_EraseRootFromParent_Done, |
| 25159 | /* 69231 */ // Label 2146: @69231 |
| 25160 | /* 69231 */ GIM_Reject, |
| 25161 | /* 69232 */ // Label 2144: @69232 |
| 25162 | /* 69232 */ GIM_Try, /*On fail goto*//*Label 2147*/ GIMT_Encode4(69364), |
| 25163 | /* 69237 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 25164 | /* 69241 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25165 | /* 69245 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2148*/ GIMT_Encode4(69304), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4505 // |
| 25166 | /* 69252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25167 | /* 69256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25168 | /* 69260 */ // MIs[1] Operand 1 |
| 25169 | /* 69260 */ // No operand predicates |
| 25170 | /* 69260 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25171 | /* 69262 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3839:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32u32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25172 | /* 69262 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25173 | /* 69265 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25174 | /* 69269 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25175 | /* 69274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32_fix), |
| 25176 | /* 69277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25177 | /* 69279 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25178 | /* 69281 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25179 | /* 69284 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25180 | /* 69287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25181 | /* 69293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25182 | /* 69299 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25183 | /* 69302 */ GIR_RootConstrainSelectedInstOperands, |
| 25184 | /* 69303 */ // GIR_Coverage, 4505, |
| 25185 | /* 69303 */ GIR_EraseRootFromParent_Done, |
| 25186 | /* 69304 */ // Label 2148: @69304 |
| 25187 | /* 69304 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2149*/ GIMT_Encode4(69363), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4507 // |
| 25188 | /* 69311 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25189 | /* 69315 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25190 | /* 69319 */ // MIs[1] Operand 1 |
| 25191 | /* 69319 */ // No operand predicates |
| 25192 | /* 69319 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25193 | /* 69321 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3839:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25194 | /* 69321 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25195 | /* 69324 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25196 | /* 69328 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25197 | /* 69333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32_fix), |
| 25198 | /* 69336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25199 | /* 69338 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25200 | /* 69340 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25201 | /* 69343 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25202 | /* 69346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25203 | /* 69352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25204 | /* 69358 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25205 | /* 69361 */ GIR_RootConstrainSelectedInstOperands, |
| 25206 | /* 69362 */ // GIR_Coverage, 4507, |
| 25207 | /* 69362 */ GIR_EraseRootFromParent_Done, |
| 25208 | /* 69363 */ // Label 2149: @69363 |
| 25209 | /* 69363 */ GIM_Reject, |
| 25210 | /* 69364 */ // Label 2147: @69364 |
| 25211 | /* 69364 */ GIM_Reject, |
| 25212 | /* 69365 */ // Label 2143: @69365 |
| 25213 | /* 69365 */ GIM_Reject, |
| 25214 | /* 69366 */ // Label 2135: @69366 |
| 25215 | /* 69366 */ GIM_Reject, |
| 25216 | /* 69367 */ // Label 2132: @69367 |
| 25217 | /* 69367 */ GIM_Try, /*On fail goto*//*Label 2150*/ GIMT_Encode4(69703), |
| 25218 | /* 69372 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 25219 | /* 69377 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25220 | /* 69380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25221 | /* 69383 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2154*/ GIMT_Encode4(69702), |
| 25222 | /* 69394 */ /*GILLT_v16s8*//*Label 2151*/ GIMT_Encode4(69414), GIMT_Encode4(0), |
| 25223 | /* 69402 */ /*GILLT_v8s16*//*Label 2152*/ GIMT_Encode4(69510), GIMT_Encode4(0), |
| 25224 | /* 69410 */ /*GILLT_v4s32*//*Label 2153*/ GIMT_Encode4(69606), |
| 25225 | /* 69414 */ // Label 2151: @69414 |
| 25226 | /* 69414 */ GIM_Try, /*On fail goto*//*Label 2155*/ GIMT_Encode4(69509), |
| 25227 | /* 69419 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25228 | /* 69422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25229 | /* 69426 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25230 | /* 69430 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25231 | /* 69434 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2156*/ GIMT_Encode4(69471), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3512 // |
| 25232 | /* 69441 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25233 | /* 69445 */ // (intrinsic_wo_chain:{ *:[i32] } 3785:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 25234 | /* 69445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8), |
| 25235 | /* 69448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25236 | /* 69450 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25237 | /* 69452 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25238 | /* 69454 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25239 | /* 69457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25240 | /* 69463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25241 | /* 69469 */ GIR_RootConstrainSelectedInstOperands, |
| 25242 | /* 69470 */ // GIR_Coverage, 3512, |
| 25243 | /* 69470 */ GIR_EraseRootFromParent_Done, |
| 25244 | /* 69471 */ // Label 2156: @69471 |
| 25245 | /* 69471 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2157*/ GIMT_Encode4(69508), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3518 // |
| 25246 | /* 69478 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25247 | /* 69482 */ // (intrinsic_wo_chain:{ *:[i32] } 3785:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 25248 | /* 69482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8), |
| 25249 | /* 69485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25250 | /* 69487 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25251 | /* 69489 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25252 | /* 69491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25253 | /* 69494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25254 | /* 69500 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25255 | /* 69506 */ GIR_RootConstrainSelectedInstOperands, |
| 25256 | /* 69507 */ // GIR_Coverage, 3518, |
| 25257 | /* 69507 */ GIR_EraseRootFromParent_Done, |
| 25258 | /* 69508 */ // Label 2157: @69508 |
| 25259 | /* 69508 */ GIM_Reject, |
| 25260 | /* 69509 */ // Label 2155: @69509 |
| 25261 | /* 69509 */ GIM_Reject, |
| 25262 | /* 69510 */ // Label 2152: @69510 |
| 25263 | /* 69510 */ GIM_Try, /*On fail goto*//*Label 2158*/ GIMT_Encode4(69605), |
| 25264 | /* 69515 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25265 | /* 69518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25266 | /* 69522 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25267 | /* 69526 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25268 | /* 69530 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2159*/ GIMT_Encode4(69567), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3514 // |
| 25269 | /* 69537 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25270 | /* 69541 */ // (intrinsic_wo_chain:{ *:[i32] } 3785:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 25271 | /* 69541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16), |
| 25272 | /* 69544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25273 | /* 69546 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25274 | /* 69548 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25275 | /* 69550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25276 | /* 69553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25277 | /* 69559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25278 | /* 69565 */ GIR_RootConstrainSelectedInstOperands, |
| 25279 | /* 69566 */ // GIR_Coverage, 3514, |
| 25280 | /* 69566 */ GIR_EraseRootFromParent_Done, |
| 25281 | /* 69567 */ // Label 2159: @69567 |
| 25282 | /* 69567 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2160*/ GIMT_Encode4(69604), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3520 // |
| 25283 | /* 69574 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25284 | /* 69578 */ // (intrinsic_wo_chain:{ *:[i32] } 3785:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 25285 | /* 69578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16), |
| 25286 | /* 69581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25287 | /* 69583 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25288 | /* 69585 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25289 | /* 69587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25290 | /* 69590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25291 | /* 69596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25292 | /* 69602 */ GIR_RootConstrainSelectedInstOperands, |
| 25293 | /* 69603 */ // GIR_Coverage, 3520, |
| 25294 | /* 69603 */ GIR_EraseRootFromParent_Done, |
| 25295 | /* 69604 */ // Label 2160: @69604 |
| 25296 | /* 69604 */ GIM_Reject, |
| 25297 | /* 69605 */ // Label 2158: @69605 |
| 25298 | /* 69605 */ GIM_Reject, |
| 25299 | /* 69606 */ // Label 2153: @69606 |
| 25300 | /* 69606 */ GIM_Try, /*On fail goto*//*Label 2161*/ GIMT_Encode4(69701), |
| 25301 | /* 69611 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25302 | /* 69614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25303 | /* 69618 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25304 | /* 69622 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25305 | /* 69626 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2162*/ GIMT_Encode4(69663), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3516 // |
| 25306 | /* 69633 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25307 | /* 69637 */ // (intrinsic_wo_chain:{ *:[i32] } 3785:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 25308 | /* 69637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32), |
| 25309 | /* 69640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25310 | /* 69642 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25311 | /* 69644 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25312 | /* 69646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25313 | /* 69649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25314 | /* 69655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25315 | /* 69661 */ GIR_RootConstrainSelectedInstOperands, |
| 25316 | /* 69662 */ // GIR_Coverage, 3516, |
| 25317 | /* 69662 */ GIR_EraseRootFromParent_Done, |
| 25318 | /* 69663 */ // Label 2162: @69663 |
| 25319 | /* 69663 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2163*/ GIMT_Encode4(69700), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3522 // |
| 25320 | /* 69670 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25321 | /* 69674 */ // (intrinsic_wo_chain:{ *:[i32] } 3785:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 25322 | /* 69674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32), |
| 25323 | /* 69677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25324 | /* 69679 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25325 | /* 69681 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25326 | /* 69683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25327 | /* 69686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25328 | /* 69692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25329 | /* 69698 */ GIR_RootConstrainSelectedInstOperands, |
| 25330 | /* 69699 */ // GIR_Coverage, 3522, |
| 25331 | /* 69699 */ GIR_EraseRootFromParent_Done, |
| 25332 | /* 69700 */ // Label 2163: @69700 |
| 25333 | /* 69700 */ GIM_Reject, |
| 25334 | /* 69701 */ // Label 2161: @69701 |
| 25335 | /* 69701 */ GIM_Reject, |
| 25336 | /* 69702 */ // Label 2154: @69702 |
| 25337 | /* 69702 */ GIM_Reject, |
| 25338 | /* 69703 */ // Label 2150: @69703 |
| 25339 | /* 69703 */ GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(70039), |
| 25340 | /* 69708 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 25341 | /* 69713 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25342 | /* 69716 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25343 | /* 69719 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2168*/ GIMT_Encode4(70038), |
| 25344 | /* 69730 */ /*GILLT_v16s8*//*Label 2165*/ GIMT_Encode4(69750), GIMT_Encode4(0), |
| 25345 | /* 69738 */ /*GILLT_v8s16*//*Label 2166*/ GIMT_Encode4(69846), GIMT_Encode4(0), |
| 25346 | /* 69746 */ /*GILLT_v4s32*//*Label 2167*/ GIMT_Encode4(69942), |
| 25347 | /* 69750 */ // Label 2165: @69750 |
| 25348 | /* 69750 */ GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(69845), |
| 25349 | /* 69755 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25350 | /* 69758 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25351 | /* 69762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25352 | /* 69766 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25353 | /* 69770 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2170*/ GIMT_Encode4(69807), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3524 // |
| 25354 | /* 69777 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25355 | /* 69781 */ // (intrinsic_wo_chain:{ *:[i32] } 3776:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 25356 | /* 69781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8), |
| 25357 | /* 69784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25358 | /* 69786 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25359 | /* 69788 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25360 | /* 69790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25361 | /* 69793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25362 | /* 69799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25363 | /* 69805 */ GIR_RootConstrainSelectedInstOperands, |
| 25364 | /* 69806 */ // GIR_Coverage, 3524, |
| 25365 | /* 69806 */ GIR_EraseRootFromParent_Done, |
| 25366 | /* 69807 */ // Label 2170: @69807 |
| 25367 | /* 69807 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2171*/ GIMT_Encode4(69844), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3530 // |
| 25368 | /* 69814 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25369 | /* 69818 */ // (intrinsic_wo_chain:{ *:[i32] } 3776:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 25370 | /* 69818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8), |
| 25371 | /* 69821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25372 | /* 69823 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25373 | /* 69825 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25374 | /* 69827 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25375 | /* 69830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25376 | /* 69836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25377 | /* 69842 */ GIR_RootConstrainSelectedInstOperands, |
| 25378 | /* 69843 */ // GIR_Coverage, 3530, |
| 25379 | /* 69843 */ GIR_EraseRootFromParent_Done, |
| 25380 | /* 69844 */ // Label 2171: @69844 |
| 25381 | /* 69844 */ GIM_Reject, |
| 25382 | /* 69845 */ // Label 2169: @69845 |
| 25383 | /* 69845 */ GIM_Reject, |
| 25384 | /* 69846 */ // Label 2166: @69846 |
| 25385 | /* 69846 */ GIM_Try, /*On fail goto*//*Label 2172*/ GIMT_Encode4(69941), |
| 25386 | /* 69851 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25387 | /* 69854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25388 | /* 69858 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25389 | /* 69862 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25390 | /* 69866 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2173*/ GIMT_Encode4(69903), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3526 // |
| 25391 | /* 69873 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25392 | /* 69877 */ // (intrinsic_wo_chain:{ *:[i32] } 3776:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 25393 | /* 69877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16), |
| 25394 | /* 69880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25395 | /* 69882 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25396 | /* 69884 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25397 | /* 69886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25398 | /* 69889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25399 | /* 69895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25400 | /* 69901 */ GIR_RootConstrainSelectedInstOperands, |
| 25401 | /* 69902 */ // GIR_Coverage, 3526, |
| 25402 | /* 69902 */ GIR_EraseRootFromParent_Done, |
| 25403 | /* 69903 */ // Label 2173: @69903 |
| 25404 | /* 69903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2174*/ GIMT_Encode4(69940), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3532 // |
| 25405 | /* 69910 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25406 | /* 69914 */ // (intrinsic_wo_chain:{ *:[i32] } 3776:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 25407 | /* 69914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16), |
| 25408 | /* 69917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25409 | /* 69919 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25410 | /* 69921 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25411 | /* 69923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25412 | /* 69926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25413 | /* 69932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25414 | /* 69938 */ GIR_RootConstrainSelectedInstOperands, |
| 25415 | /* 69939 */ // GIR_Coverage, 3532, |
| 25416 | /* 69939 */ GIR_EraseRootFromParent_Done, |
| 25417 | /* 69940 */ // Label 2174: @69940 |
| 25418 | /* 69940 */ GIM_Reject, |
| 25419 | /* 69941 */ // Label 2172: @69941 |
| 25420 | /* 69941 */ GIM_Reject, |
| 25421 | /* 69942 */ // Label 2167: @69942 |
| 25422 | /* 69942 */ GIM_Try, /*On fail goto*//*Label 2175*/ GIMT_Encode4(70037), |
| 25423 | /* 69947 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25424 | /* 69950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25425 | /* 69954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25426 | /* 69958 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25427 | /* 69962 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2176*/ GIMT_Encode4(69999), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3528 // |
| 25428 | /* 69969 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25429 | /* 69973 */ // (intrinsic_wo_chain:{ *:[i32] } 3776:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 25430 | /* 69973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32), |
| 25431 | /* 69976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25432 | /* 69978 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25433 | /* 69980 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25434 | /* 69982 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25435 | /* 69985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25436 | /* 69991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25437 | /* 69997 */ GIR_RootConstrainSelectedInstOperands, |
| 25438 | /* 69998 */ // GIR_Coverage, 3528, |
| 25439 | /* 69998 */ GIR_EraseRootFromParent_Done, |
| 25440 | /* 69999 */ // Label 2176: @69999 |
| 25441 | /* 69999 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2177*/ GIMT_Encode4(70036), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3534 // |
| 25442 | /* 70006 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25443 | /* 70010 */ // (intrinsic_wo_chain:{ *:[i32] } 3776:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 25444 | /* 70010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32), |
| 25445 | /* 70013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25446 | /* 70015 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25447 | /* 70017 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25448 | /* 70019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25449 | /* 70022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25450 | /* 70028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25451 | /* 70034 */ GIR_RootConstrainSelectedInstOperands, |
| 25452 | /* 70035 */ // GIR_Coverage, 3534, |
| 25453 | /* 70035 */ GIR_EraseRootFromParent_Done, |
| 25454 | /* 70036 */ // Label 2177: @70036 |
| 25455 | /* 70036 */ GIM_Reject, |
| 25456 | /* 70037 */ // Label 2175: @70037 |
| 25457 | /* 70037 */ GIM_Reject, |
| 25458 | /* 70038 */ // Label 2168: @70038 |
| 25459 | /* 70038 */ GIM_Reject, |
| 25460 | /* 70039 */ // Label 2164: @70039 |
| 25461 | /* 70039 */ GIM_Try, /*On fail goto*//*Label 2178*/ GIMT_Encode4(70477), |
| 25462 | /* 70044 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 25463 | /* 70049 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2182*/ GIMT_Encode4(70476), |
| 25464 | /* 70060 */ /*GILLT_v16s8*//*Label 2179*/ GIMT_Encode4(70080), GIMT_Encode4(0), |
| 25465 | /* 70068 */ /*GILLT_v8s16*//*Label 2180*/ GIMT_Encode4(70212), GIMT_Encode4(0), |
| 25466 | /* 70076 */ /*GILLT_v4s32*//*Label 2181*/ GIMT_Encode4(70344), |
| 25467 | /* 70080 */ // Label 2179: @70080 |
| 25468 | /* 70080 */ GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(70211), |
| 25469 | /* 70085 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25470 | /* 70088 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25471 | /* 70091 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25472 | /* 70094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25473 | /* 70098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25474 | /* 70102 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25475 | /* 70106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2184*/ GIMT_Encode4(70158), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3945 // |
| 25476 | /* 70113 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25477 | /* 70117 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3822:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25478 | /* 70117 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25479 | /* 70120 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25480 | /* 70124 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25481 | /* 70129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8), |
| 25482 | /* 70132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25483 | /* 70134 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25484 | /* 70136 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25485 | /* 70138 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25486 | /* 70141 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25487 | /* 70147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25488 | /* 70153 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25489 | /* 70156 */ GIR_RootConstrainSelectedInstOperands, |
| 25490 | /* 70157 */ // GIR_Coverage, 3945, |
| 25491 | /* 70157 */ GIR_EraseRootFromParent_Done, |
| 25492 | /* 70158 */ // Label 2184: @70158 |
| 25493 | /* 70158 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2185*/ GIMT_Encode4(70210), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3960 // |
| 25494 | /* 70165 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25495 | /* 70169 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3822:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25496 | /* 70169 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25497 | /* 70172 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25498 | /* 70176 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25499 | /* 70181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8), |
| 25500 | /* 70184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25501 | /* 70186 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25502 | /* 70188 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25503 | /* 70190 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25504 | /* 70193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25505 | /* 70199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25506 | /* 70205 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25507 | /* 70208 */ GIR_RootConstrainSelectedInstOperands, |
| 25508 | /* 70209 */ // GIR_Coverage, 3960, |
| 25509 | /* 70209 */ GIR_EraseRootFromParent_Done, |
| 25510 | /* 70210 */ // Label 2185: @70210 |
| 25511 | /* 70210 */ GIM_Reject, |
| 25512 | /* 70211 */ // Label 2183: @70211 |
| 25513 | /* 70211 */ GIM_Reject, |
| 25514 | /* 70212 */ // Label 2180: @70212 |
| 25515 | /* 70212 */ GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(70343), |
| 25516 | /* 70217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25517 | /* 70220 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25518 | /* 70223 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25519 | /* 70226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25520 | /* 70230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25521 | /* 70234 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25522 | /* 70238 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2187*/ GIMT_Encode4(70290), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3952 // |
| 25523 | /* 70245 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25524 | /* 70249 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3822:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25525 | /* 70249 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25526 | /* 70252 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25527 | /* 70256 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25528 | /* 70261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16), |
| 25529 | /* 70264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25530 | /* 70266 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25531 | /* 70268 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25532 | /* 70270 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25533 | /* 70273 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25534 | /* 70279 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25535 | /* 70285 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25536 | /* 70288 */ GIR_RootConstrainSelectedInstOperands, |
| 25537 | /* 70289 */ // GIR_Coverage, 3952, |
| 25538 | /* 70289 */ GIR_EraseRootFromParent_Done, |
| 25539 | /* 70290 */ // Label 2187: @70290 |
| 25540 | /* 70290 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2188*/ GIMT_Encode4(70342), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3964 // |
| 25541 | /* 70297 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25542 | /* 70301 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3822:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25543 | /* 70301 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25544 | /* 70304 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25545 | /* 70308 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25546 | /* 70313 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16), |
| 25547 | /* 70316 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25548 | /* 70318 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25549 | /* 70320 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25550 | /* 70322 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25551 | /* 70325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25552 | /* 70331 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25553 | /* 70337 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25554 | /* 70340 */ GIR_RootConstrainSelectedInstOperands, |
| 25555 | /* 70341 */ // GIR_Coverage, 3964, |
| 25556 | /* 70341 */ GIR_EraseRootFromParent_Done, |
| 25557 | /* 70342 */ // Label 2188: @70342 |
| 25558 | /* 70342 */ GIM_Reject, |
| 25559 | /* 70343 */ // Label 2186: @70343 |
| 25560 | /* 70343 */ GIM_Reject, |
| 25561 | /* 70344 */ // Label 2181: @70344 |
| 25562 | /* 70344 */ GIM_Try, /*On fail goto*//*Label 2189*/ GIMT_Encode4(70475), |
| 25563 | /* 70349 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25564 | /* 70352 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25565 | /* 70355 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25566 | /* 70358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25567 | /* 70362 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25568 | /* 70366 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25569 | /* 70370 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2190*/ GIMT_Encode4(70422), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3956 // |
| 25570 | /* 70377 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25571 | /* 70381 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3822:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 25572 | /* 70381 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25573 | /* 70384 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25574 | /* 70388 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25575 | /* 70393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32), |
| 25576 | /* 70396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25577 | /* 70398 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25578 | /* 70400 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25579 | /* 70402 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25580 | /* 70405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25581 | /* 70411 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25582 | /* 70417 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25583 | /* 70420 */ GIR_RootConstrainSelectedInstOperands, |
| 25584 | /* 70421 */ // GIR_Coverage, 3956, |
| 25585 | /* 70421 */ GIR_EraseRootFromParent_Done, |
| 25586 | /* 70422 */ // Label 2190: @70422 |
| 25587 | /* 70422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2191*/ GIMT_Encode4(70474), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3968 // |
| 25588 | /* 70429 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25589 | /* 70433 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3822:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 25590 | /* 70433 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25591 | /* 70436 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25592 | /* 70440 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25593 | /* 70445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32), |
| 25594 | /* 70448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25595 | /* 70450 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25596 | /* 70452 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25597 | /* 70454 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25598 | /* 70457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25599 | /* 70463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25600 | /* 70469 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25601 | /* 70472 */ GIR_RootConstrainSelectedInstOperands, |
| 25602 | /* 70473 */ // GIR_Coverage, 3968, |
| 25603 | /* 70473 */ GIR_EraseRootFromParent_Done, |
| 25604 | /* 70474 */ // Label 2191: @70474 |
| 25605 | /* 70474 */ GIM_Reject, |
| 25606 | /* 70475 */ // Label 2189: @70475 |
| 25607 | /* 70475 */ GIM_Reject, |
| 25608 | /* 70476 */ // Label 2182: @70476 |
| 25609 | /* 70476 */ GIM_Reject, |
| 25610 | /* 70477 */ // Label 2178: @70477 |
| 25611 | /* 70477 */ GIM_Try, /*On fail goto*//*Label 2192*/ GIMT_Encode4(70915), |
| 25612 | /* 70482 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 25613 | /* 70487 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2196*/ GIMT_Encode4(70914), |
| 25614 | /* 70498 */ /*GILLT_v16s8*//*Label 2193*/ GIMT_Encode4(70518), GIMT_Encode4(0), |
| 25615 | /* 70506 */ /*GILLT_v8s16*//*Label 2194*/ GIMT_Encode4(70650), GIMT_Encode4(0), |
| 25616 | /* 70514 */ /*GILLT_v4s32*//*Label 2195*/ GIMT_Encode4(70782), |
| 25617 | /* 70518 */ // Label 2193: @70518 |
| 25618 | /* 70518 */ GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(70649), |
| 25619 | /* 70523 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25620 | /* 70526 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25621 | /* 70529 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25622 | /* 70532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25623 | /* 70536 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25624 | /* 70540 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25625 | /* 70544 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2198*/ GIMT_Encode4(70596), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3969 // |
| 25626 | /* 70551 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25627 | /* 70555 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3914:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25628 | /* 70555 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25629 | /* 70558 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25630 | /* 70562 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25631 | /* 70567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8), |
| 25632 | /* 70570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25633 | /* 70572 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25634 | /* 70574 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25635 | /* 70576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25636 | /* 70579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25637 | /* 70585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25638 | /* 70591 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25639 | /* 70594 */ GIR_RootConstrainSelectedInstOperands, |
| 25640 | /* 70595 */ // GIR_Coverage, 3969, |
| 25641 | /* 70595 */ GIR_EraseRootFromParent_Done, |
| 25642 | /* 70596 */ // Label 2198: @70596 |
| 25643 | /* 70596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2199*/ GIMT_Encode4(70648), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3984 // |
| 25644 | /* 70603 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25645 | /* 70607 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3914:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25646 | /* 70607 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25647 | /* 70610 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25648 | /* 70614 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25649 | /* 70619 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8), |
| 25650 | /* 70622 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25651 | /* 70624 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25652 | /* 70626 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25653 | /* 70628 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25654 | /* 70631 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25655 | /* 70637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25656 | /* 70643 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25657 | /* 70646 */ GIR_RootConstrainSelectedInstOperands, |
| 25658 | /* 70647 */ // GIR_Coverage, 3984, |
| 25659 | /* 70647 */ GIR_EraseRootFromParent_Done, |
| 25660 | /* 70648 */ // Label 2199: @70648 |
| 25661 | /* 70648 */ GIM_Reject, |
| 25662 | /* 70649 */ // Label 2197: @70649 |
| 25663 | /* 70649 */ GIM_Reject, |
| 25664 | /* 70650 */ // Label 2194: @70650 |
| 25665 | /* 70650 */ GIM_Try, /*On fail goto*//*Label 2200*/ GIMT_Encode4(70781), |
| 25666 | /* 70655 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25667 | /* 70658 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25668 | /* 70661 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25669 | /* 70664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25670 | /* 70668 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25671 | /* 70672 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25672 | /* 70676 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2201*/ GIMT_Encode4(70728), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3976 // |
| 25673 | /* 70683 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25674 | /* 70687 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3914:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25675 | /* 70687 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25676 | /* 70690 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25677 | /* 70694 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25678 | /* 70699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16), |
| 25679 | /* 70702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25680 | /* 70704 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25681 | /* 70706 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25682 | /* 70708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25683 | /* 70711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25684 | /* 70717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25685 | /* 70723 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25686 | /* 70726 */ GIR_RootConstrainSelectedInstOperands, |
| 25687 | /* 70727 */ // GIR_Coverage, 3976, |
| 25688 | /* 70727 */ GIR_EraseRootFromParent_Done, |
| 25689 | /* 70728 */ // Label 2201: @70728 |
| 25690 | /* 70728 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2202*/ GIMT_Encode4(70780), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3988 // |
| 25691 | /* 70735 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25692 | /* 70739 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3914:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25693 | /* 70739 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25694 | /* 70742 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25695 | /* 70746 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25696 | /* 70751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16), |
| 25697 | /* 70754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25698 | /* 70756 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25699 | /* 70758 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25700 | /* 70760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25701 | /* 70763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25702 | /* 70769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25703 | /* 70775 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25704 | /* 70778 */ GIR_RootConstrainSelectedInstOperands, |
| 25705 | /* 70779 */ // GIR_Coverage, 3988, |
| 25706 | /* 70779 */ GIR_EraseRootFromParent_Done, |
| 25707 | /* 70780 */ // Label 2202: @70780 |
| 25708 | /* 70780 */ GIM_Reject, |
| 25709 | /* 70781 */ // Label 2200: @70781 |
| 25710 | /* 70781 */ GIM_Reject, |
| 25711 | /* 70782 */ // Label 2195: @70782 |
| 25712 | /* 70782 */ GIM_Try, /*On fail goto*//*Label 2203*/ GIMT_Encode4(70913), |
| 25713 | /* 70787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25714 | /* 70790 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25715 | /* 70793 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25716 | /* 70796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25717 | /* 70800 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25718 | /* 70804 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25719 | /* 70808 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2204*/ GIMT_Encode4(70860), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3980 // |
| 25720 | /* 70815 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25721 | /* 70819 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3914:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 25722 | /* 70819 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25723 | /* 70822 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25724 | /* 70826 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25725 | /* 70831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32), |
| 25726 | /* 70834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25727 | /* 70836 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25728 | /* 70838 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25729 | /* 70840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25730 | /* 70843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25731 | /* 70849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25732 | /* 70855 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25733 | /* 70858 */ GIR_RootConstrainSelectedInstOperands, |
| 25734 | /* 70859 */ // GIR_Coverage, 3980, |
| 25735 | /* 70859 */ GIR_EraseRootFromParent_Done, |
| 25736 | /* 70860 */ // Label 2204: @70860 |
| 25737 | /* 70860 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2205*/ GIMT_Encode4(70912), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3992 // |
| 25738 | /* 70867 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25739 | /* 70871 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3914:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 25740 | /* 70871 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25741 | /* 70874 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25742 | /* 70878 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25743 | /* 70883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32), |
| 25744 | /* 70886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25745 | /* 70888 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25746 | /* 70890 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25747 | /* 70892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25748 | /* 70895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25749 | /* 70901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25750 | /* 70907 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25751 | /* 70910 */ GIR_RootConstrainSelectedInstOperands, |
| 25752 | /* 70911 */ // GIR_Coverage, 3992, |
| 25753 | /* 70911 */ GIR_EraseRootFromParent_Done, |
| 25754 | /* 70912 */ // Label 2205: @70912 |
| 25755 | /* 70912 */ GIM_Reject, |
| 25756 | /* 70913 */ // Label 2203: @70913 |
| 25757 | /* 70913 */ GIM_Reject, |
| 25758 | /* 70914 */ // Label 2196: @70914 |
| 25759 | /* 70914 */ GIM_Reject, |
| 25760 | /* 70915 */ // Label 2192: @70915 |
| 25761 | /* 70915 */ GIM_Try, /*On fail goto*//*Label 2206*/ GIMT_Encode4(71353), |
| 25762 | /* 70920 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 25763 | /* 70925 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2210*/ GIMT_Encode4(71352), |
| 25764 | /* 70936 */ /*GILLT_v16s8*//*Label 2207*/ GIMT_Encode4(70956), GIMT_Encode4(0), |
| 25765 | /* 70944 */ /*GILLT_v8s16*//*Label 2208*/ GIMT_Encode4(71088), GIMT_Encode4(0), |
| 25766 | /* 70952 */ /*GILLT_v4s32*//*Label 2209*/ GIMT_Encode4(71220), |
| 25767 | /* 70956 */ // Label 2207: @70956 |
| 25768 | /* 70956 */ GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(71087), |
| 25769 | /* 70961 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25770 | /* 70964 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25771 | /* 70967 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25772 | /* 70970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25773 | /* 70974 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25774 | /* 70978 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25775 | /* 70982 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2212*/ GIMT_Encode4(71034), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3993 // |
| 25776 | /* 70989 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25777 | /* 70993 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3860:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25778 | /* 70993 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25779 | /* 70996 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25780 | /* 71000 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25781 | /* 71005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8), |
| 25782 | /* 71008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25783 | /* 71010 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25784 | /* 71012 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25785 | /* 71014 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25786 | /* 71017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25787 | /* 71023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25788 | /* 71029 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25789 | /* 71032 */ GIR_RootConstrainSelectedInstOperands, |
| 25790 | /* 71033 */ // GIR_Coverage, 3993, |
| 25791 | /* 71033 */ GIR_EraseRootFromParent_Done, |
| 25792 | /* 71034 */ // Label 2212: @71034 |
| 25793 | /* 71034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2213*/ GIMT_Encode4(71086), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4008 // |
| 25794 | /* 71041 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25795 | /* 71045 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3860:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25796 | /* 71045 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25797 | /* 71048 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25798 | /* 71052 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25799 | /* 71057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8), |
| 25800 | /* 71060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25801 | /* 71062 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25802 | /* 71064 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25803 | /* 71066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25804 | /* 71069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25805 | /* 71075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25806 | /* 71081 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25807 | /* 71084 */ GIR_RootConstrainSelectedInstOperands, |
| 25808 | /* 71085 */ // GIR_Coverage, 4008, |
| 25809 | /* 71085 */ GIR_EraseRootFromParent_Done, |
| 25810 | /* 71086 */ // Label 2213: @71086 |
| 25811 | /* 71086 */ GIM_Reject, |
| 25812 | /* 71087 */ // Label 2211: @71087 |
| 25813 | /* 71087 */ GIM_Reject, |
| 25814 | /* 71088 */ // Label 2208: @71088 |
| 25815 | /* 71088 */ GIM_Try, /*On fail goto*//*Label 2214*/ GIMT_Encode4(71219), |
| 25816 | /* 71093 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25817 | /* 71096 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25818 | /* 71099 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25819 | /* 71102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25820 | /* 71106 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25821 | /* 71110 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25822 | /* 71114 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2215*/ GIMT_Encode4(71166), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4000 // |
| 25823 | /* 71121 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25824 | /* 71125 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3860:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25825 | /* 71125 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25826 | /* 71128 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25827 | /* 71132 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25828 | /* 71137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16), |
| 25829 | /* 71140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25830 | /* 71142 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25831 | /* 71144 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25832 | /* 71146 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25833 | /* 71149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25834 | /* 71155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25835 | /* 71161 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25836 | /* 71164 */ GIR_RootConstrainSelectedInstOperands, |
| 25837 | /* 71165 */ // GIR_Coverage, 4000, |
| 25838 | /* 71165 */ GIR_EraseRootFromParent_Done, |
| 25839 | /* 71166 */ // Label 2215: @71166 |
| 25840 | /* 71166 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2216*/ GIMT_Encode4(71218), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4012 // |
| 25841 | /* 71173 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25842 | /* 71177 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3860:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25843 | /* 71177 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25844 | /* 71180 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25845 | /* 71184 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25846 | /* 71189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16), |
| 25847 | /* 71192 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25848 | /* 71194 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25849 | /* 71196 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25850 | /* 71198 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25851 | /* 71201 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25852 | /* 71207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25853 | /* 71213 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25854 | /* 71216 */ GIR_RootConstrainSelectedInstOperands, |
| 25855 | /* 71217 */ // GIR_Coverage, 4012, |
| 25856 | /* 71217 */ GIR_EraseRootFromParent_Done, |
| 25857 | /* 71218 */ // Label 2216: @71218 |
| 25858 | /* 71218 */ GIM_Reject, |
| 25859 | /* 71219 */ // Label 2214: @71219 |
| 25860 | /* 71219 */ GIM_Reject, |
| 25861 | /* 71220 */ // Label 2209: @71220 |
| 25862 | /* 71220 */ GIM_Try, /*On fail goto*//*Label 2217*/ GIMT_Encode4(71351), |
| 25863 | /* 71225 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25864 | /* 71228 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25865 | /* 71231 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25866 | /* 71234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25867 | /* 71238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25868 | /* 71242 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25869 | /* 71246 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2218*/ GIMT_Encode4(71298), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4004 // |
| 25870 | /* 71253 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25871 | /* 71257 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3860:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 25872 | /* 71257 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25873 | /* 71260 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25874 | /* 71264 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25875 | /* 71269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32), |
| 25876 | /* 71272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25877 | /* 71274 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25878 | /* 71276 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25879 | /* 71278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25880 | /* 71281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25881 | /* 71287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25882 | /* 71293 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25883 | /* 71296 */ GIR_RootConstrainSelectedInstOperands, |
| 25884 | /* 71297 */ // GIR_Coverage, 4004, |
| 25885 | /* 71297 */ GIR_EraseRootFromParent_Done, |
| 25886 | /* 71298 */ // Label 2218: @71298 |
| 25887 | /* 71298 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2219*/ GIMT_Encode4(71350), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4016 // |
| 25888 | /* 71305 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25889 | /* 71309 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3860:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 25890 | /* 71309 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25891 | /* 71312 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25892 | /* 71316 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25893 | /* 71321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32), |
| 25894 | /* 71324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25895 | /* 71326 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25896 | /* 71328 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25897 | /* 71330 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25898 | /* 71333 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25899 | /* 71339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25900 | /* 71345 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25901 | /* 71348 */ GIR_RootConstrainSelectedInstOperands, |
| 25902 | /* 71349 */ // GIR_Coverage, 4016, |
| 25903 | /* 71349 */ GIR_EraseRootFromParent_Done, |
| 25904 | /* 71350 */ // Label 2219: @71350 |
| 25905 | /* 71350 */ GIM_Reject, |
| 25906 | /* 71351 */ // Label 2217: @71351 |
| 25907 | /* 71351 */ GIM_Reject, |
| 25908 | /* 71352 */ // Label 2210: @71352 |
| 25909 | /* 71352 */ GIM_Reject, |
| 25910 | /* 71353 */ // Label 2206: @71353 |
| 25911 | /* 71353 */ GIM_Try, /*On fail goto*//*Label 2220*/ GIMT_Encode4(71791), |
| 25912 | /* 71358 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 25913 | /* 71363 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2224*/ GIMT_Encode4(71790), |
| 25914 | /* 71374 */ /*GILLT_v16s8*//*Label 2221*/ GIMT_Encode4(71394), GIMT_Encode4(0), |
| 25915 | /* 71382 */ /*GILLT_v8s16*//*Label 2222*/ GIMT_Encode4(71526), GIMT_Encode4(0), |
| 25916 | /* 71390 */ /*GILLT_v4s32*//*Label 2223*/ GIMT_Encode4(71658), |
| 25917 | /* 71394 */ // Label 2221: @71394 |
| 25918 | /* 71394 */ GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(71525), |
| 25919 | /* 71399 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25920 | /* 71402 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25921 | /* 71405 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25922 | /* 71408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25923 | /* 71412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25924 | /* 71416 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25925 | /* 71420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2226*/ GIMT_Encode4(71472), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4017 // |
| 25926 | /* 71427 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25927 | /* 71431 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3861:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25928 | /* 71431 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25929 | /* 71434 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25930 | /* 71438 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25931 | /* 71443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs8), |
| 25932 | /* 71446 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25933 | /* 71448 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25934 | /* 71450 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25935 | /* 71452 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25936 | /* 71455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25937 | /* 71461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25938 | /* 71467 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25939 | /* 71470 */ GIR_RootConstrainSelectedInstOperands, |
| 25940 | /* 71471 */ // GIR_Coverage, 4017, |
| 25941 | /* 71471 */ GIR_EraseRootFromParent_Done, |
| 25942 | /* 71472 */ // Label 2226: @71472 |
| 25943 | /* 71472 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2227*/ GIMT_Encode4(71524), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4026 // |
| 25944 | /* 71479 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25945 | /* 71483 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3861:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25946 | /* 71483 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25947 | /* 71486 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25948 | /* 71490 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25949 | /* 71495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu8), |
| 25950 | /* 71498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25951 | /* 71500 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25952 | /* 71502 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25953 | /* 71504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25954 | /* 71507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25955 | /* 71513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25956 | /* 71519 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25957 | /* 71522 */ GIR_RootConstrainSelectedInstOperands, |
| 25958 | /* 71523 */ // GIR_Coverage, 4026, |
| 25959 | /* 71523 */ GIR_EraseRootFromParent_Done, |
| 25960 | /* 71524 */ // Label 2227: @71524 |
| 25961 | /* 71524 */ GIM_Reject, |
| 25962 | /* 71525 */ // Label 2225: @71525 |
| 25963 | /* 71525 */ GIM_Reject, |
| 25964 | /* 71526 */ // Label 2222: @71526 |
| 25965 | /* 71526 */ GIM_Try, /*On fail goto*//*Label 2228*/ GIMT_Encode4(71657), |
| 25966 | /* 71531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25967 | /* 71534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25968 | /* 71537 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25969 | /* 71540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25970 | /* 71544 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25971 | /* 71548 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25972 | /* 71552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2229*/ GIMT_Encode4(71604), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4020 // |
| 25973 | /* 71559 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25974 | /* 71563 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3861:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25975 | /* 71563 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25976 | /* 71566 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25977 | /* 71570 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25978 | /* 71575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs16), |
| 25979 | /* 71578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25980 | /* 71580 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25981 | /* 71582 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25982 | /* 71584 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25983 | /* 71587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25984 | /* 71593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25985 | /* 71599 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25986 | /* 71602 */ GIR_RootConstrainSelectedInstOperands, |
| 25987 | /* 71603 */ // GIR_Coverage, 4020, |
| 25988 | /* 71603 */ GIR_EraseRootFromParent_Done, |
| 25989 | /* 71604 */ // Label 2229: @71604 |
| 25990 | /* 71604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2230*/ GIMT_Encode4(71656), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4029 // |
| 25991 | /* 71611 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25992 | /* 71615 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3861:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25993 | /* 71615 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25994 | /* 71618 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25995 | /* 71622 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25996 | /* 71627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu16), |
| 25997 | /* 71630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25998 | /* 71632 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25999 | /* 71634 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26000 | /* 71636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26001 | /* 71639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26002 | /* 71645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26003 | /* 71651 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26004 | /* 71654 */ GIR_RootConstrainSelectedInstOperands, |
| 26005 | /* 71655 */ // GIR_Coverage, 4029, |
| 26006 | /* 71655 */ GIR_EraseRootFromParent_Done, |
| 26007 | /* 71656 */ // Label 2230: @71656 |
| 26008 | /* 71656 */ GIM_Reject, |
| 26009 | /* 71657 */ // Label 2228: @71657 |
| 26010 | /* 71657 */ GIM_Reject, |
| 26011 | /* 71658 */ // Label 2223: @71658 |
| 26012 | /* 71658 */ GIM_Try, /*On fail goto*//*Label 2231*/ GIMT_Encode4(71789), |
| 26013 | /* 71663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26014 | /* 71666 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26015 | /* 71669 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26016 | /* 71672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26017 | /* 71676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26018 | /* 71680 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26019 | /* 71684 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2232*/ GIMT_Encode4(71736), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4023 // |
| 26020 | /* 71691 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26021 | /* 71695 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3861:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26022 | /* 71695 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26023 | /* 71698 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26024 | /* 71702 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26025 | /* 71707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs32), |
| 26026 | /* 71710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26027 | /* 71712 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26028 | /* 71714 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26029 | /* 71716 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26030 | /* 71719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26031 | /* 71725 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26032 | /* 71731 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26033 | /* 71734 */ GIR_RootConstrainSelectedInstOperands, |
| 26034 | /* 71735 */ // GIR_Coverage, 4023, |
| 26035 | /* 71735 */ GIR_EraseRootFromParent_Done, |
| 26036 | /* 71736 */ // Label 2232: @71736 |
| 26037 | /* 71736 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2233*/ GIMT_Encode4(71788), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4032 // |
| 26038 | /* 71743 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26039 | /* 71747 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3861:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26040 | /* 71747 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26041 | /* 71750 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26042 | /* 71754 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26043 | /* 71759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu32), |
| 26044 | /* 71762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26045 | /* 71764 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26046 | /* 71766 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26047 | /* 71768 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26048 | /* 71771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26049 | /* 71777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26050 | /* 71783 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26051 | /* 71786 */ GIR_RootConstrainSelectedInstOperands, |
| 26052 | /* 71787 */ // GIR_Coverage, 4032, |
| 26053 | /* 71787 */ GIR_EraseRootFromParent_Done, |
| 26054 | /* 71788 */ // Label 2233: @71788 |
| 26055 | /* 71788 */ GIM_Reject, |
| 26056 | /* 71789 */ // Label 2231: @71789 |
| 26057 | /* 71789 */ GIM_Reject, |
| 26058 | /* 71790 */ // Label 2224: @71790 |
| 26059 | /* 71790 */ GIM_Reject, |
| 26060 | /* 71791 */ // Label 2220: @71791 |
| 26061 | /* 71791 */ GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(71973), |
| 26062 | /* 71796 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 26063 | /* 71801 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2237*/ GIMT_Encode4(71972), |
| 26064 | /* 71812 */ /*GILLT_v8s16*//*Label 2235*/ GIMT_Encode4(71824), GIMT_Encode4(0), |
| 26065 | /* 71820 */ /*GILLT_v4s32*//*Label 2236*/ GIMT_Encode4(71898), |
| 26066 | /* 71824 */ // Label 2235: @71824 |
| 26067 | /* 71824 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2238*/ GIMT_Encode4(71897), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4489 // |
| 26068 | /* 71831 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26069 | /* 71834 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26070 | /* 71837 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26071 | /* 71840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26072 | /* 71844 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26073 | /* 71848 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26074 | /* 71852 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26075 | /* 71856 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3822:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 26076 | /* 71856 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26077 | /* 71859 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26078 | /* 71863 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26079 | /* 71868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16), |
| 26080 | /* 71871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26081 | /* 71873 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26082 | /* 71875 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26083 | /* 71877 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26084 | /* 71880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26085 | /* 71886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26086 | /* 71892 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26087 | /* 71895 */ GIR_RootConstrainSelectedInstOperands, |
| 26088 | /* 71896 */ // GIR_Coverage, 4489, |
| 26089 | /* 71896 */ GIR_EraseRootFromParent_Done, |
| 26090 | /* 71897 */ // Label 2238: @71897 |
| 26091 | /* 71897 */ GIM_Reject, |
| 26092 | /* 71898 */ // Label 2236: @71898 |
| 26093 | /* 71898 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2239*/ GIMT_Encode4(71971), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4487 // |
| 26094 | /* 71905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26095 | /* 71908 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26096 | /* 71911 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26097 | /* 71914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26098 | /* 71918 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26099 | /* 71922 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26100 | /* 71926 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26101 | /* 71930 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3822:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 26102 | /* 71930 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26103 | /* 71933 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26104 | /* 71937 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26105 | /* 71942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32), |
| 26106 | /* 71945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26107 | /* 71947 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26108 | /* 71949 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26109 | /* 71951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26110 | /* 71954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26111 | /* 71960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26112 | /* 71966 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26113 | /* 71969 */ GIR_RootConstrainSelectedInstOperands, |
| 26114 | /* 71970 */ // GIR_Coverage, 4487, |
| 26115 | /* 71970 */ GIR_EraseRootFromParent_Done, |
| 26116 | /* 71971 */ // Label 2239: @71971 |
| 26117 | /* 71971 */ GIM_Reject, |
| 26118 | /* 71972 */ // Label 2237: @71972 |
| 26119 | /* 71972 */ GIM_Reject, |
| 26120 | /* 71973 */ // Label 2234: @71973 |
| 26121 | /* 71973 */ GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(72271), |
| 26122 | /* 71978 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly), |
| 26123 | /* 71983 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2243*/ GIMT_Encode4(72270), |
| 26124 | /* 71994 */ /*GILLT_v8s16*//*Label 2241*/ GIMT_Encode4(72006), GIMT_Encode4(0), |
| 26125 | /* 72002 */ /*GILLT_v4s32*//*Label 2242*/ GIMT_Encode4(72138), |
| 26126 | /* 72006 */ // Label 2241: @72006 |
| 26127 | /* 72006 */ GIM_Try, /*On fail goto*//*Label 2244*/ GIMT_Encode4(72137), |
| 26128 | /* 72011 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26129 | /* 72014 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26130 | /* 72017 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26131 | /* 72020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26132 | /* 72024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26133 | /* 72028 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26134 | /* 72032 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2245*/ GIMT_Encode4(72084), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4922 // |
| 26135 | /* 72039 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26136 | /* 72043 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3891:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26137 | /* 72043 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26138 | /* 72046 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26139 | /* 72050 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26140 | /* 72055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp8), |
| 26141 | /* 72058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26142 | /* 72060 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26143 | /* 72062 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26144 | /* 72064 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26145 | /* 72067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26146 | /* 72073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26147 | /* 72079 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26148 | /* 72082 */ GIR_RootConstrainSelectedInstOperands, |
| 26149 | /* 72083 */ // GIR_Coverage, 4922, |
| 26150 | /* 72083 */ GIR_EraseRootFromParent_Done, |
| 26151 | /* 72084 */ // Label 2245: @72084 |
| 26152 | /* 72084 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2246*/ GIMT_Encode4(72136), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4924 // |
| 26153 | /* 72091 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26154 | /* 72095 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3891:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26155 | /* 72095 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26156 | /* 72098 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26157 | /* 72102 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26158 | /* 72107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp8), |
| 26159 | /* 72110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26160 | /* 72112 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26161 | /* 72114 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26162 | /* 72116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26163 | /* 72119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26164 | /* 72125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26165 | /* 72131 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26166 | /* 72134 */ GIR_RootConstrainSelectedInstOperands, |
| 26167 | /* 72135 */ // GIR_Coverage, 4924, |
| 26168 | /* 72135 */ GIR_EraseRootFromParent_Done, |
| 26169 | /* 72136 */ // Label 2246: @72136 |
| 26170 | /* 72136 */ GIM_Reject, |
| 26171 | /* 72137 */ // Label 2244: @72137 |
| 26172 | /* 72137 */ GIM_Reject, |
| 26173 | /* 72138 */ // Label 2242: @72138 |
| 26174 | /* 72138 */ GIM_Try, /*On fail goto*//*Label 2247*/ GIMT_Encode4(72269), |
| 26175 | /* 72143 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26176 | /* 72146 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26177 | /* 72149 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26178 | /* 72152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26179 | /* 72156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26180 | /* 72160 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26181 | /* 72164 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2248*/ GIMT_Encode4(72216), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4926 // |
| 26182 | /* 72171 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26183 | /* 72175 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26184 | /* 72175 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26185 | /* 72178 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26186 | /* 72182 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26187 | /* 72187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp16), |
| 26188 | /* 72190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26189 | /* 72192 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26190 | /* 72194 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26191 | /* 72196 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26192 | /* 72199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26193 | /* 72205 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26194 | /* 72211 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26195 | /* 72214 */ GIR_RootConstrainSelectedInstOperands, |
| 26196 | /* 72215 */ // GIR_Coverage, 4926, |
| 26197 | /* 72215 */ GIR_EraseRootFromParent_Done, |
| 26198 | /* 72216 */ // Label 2248: @72216 |
| 26199 | /* 72216 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2249*/ GIMT_Encode4(72268), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4928 // |
| 26200 | /* 72223 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26201 | /* 72227 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26202 | /* 72227 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26203 | /* 72230 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26204 | /* 72234 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26205 | /* 72239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp16), |
| 26206 | /* 72242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26207 | /* 72244 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26208 | /* 72246 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26209 | /* 72248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26210 | /* 72251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26211 | /* 72257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26212 | /* 72263 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26213 | /* 72266 */ GIR_RootConstrainSelectedInstOperands, |
| 26214 | /* 72267 */ // GIR_Coverage, 4928, |
| 26215 | /* 72267 */ GIR_EraseRootFromParent_Done, |
| 26216 | /* 72268 */ // Label 2249: @72268 |
| 26217 | /* 72268 */ GIM_Reject, |
| 26218 | /* 72269 */ // Label 2247: @72269 |
| 26219 | /* 72269 */ GIM_Reject, |
| 26220 | /* 72270 */ // Label 2243: @72270 |
| 26221 | /* 72270 */ GIM_Reject, |
| 26222 | /* 72271 */ // Label 2240: @72271 |
| 26223 | /* 72271 */ GIM_Try, /*On fail goto*//*Label 2250*/ GIMT_Encode4(72709), |
| 26224 | /* 72276 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 26225 | /* 72281 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2254*/ GIMT_Encode4(72708), |
| 26226 | /* 72292 */ /*GILLT_v16s8*//*Label 2251*/ GIMT_Encode4(72312), GIMT_Encode4(0), |
| 26227 | /* 72300 */ /*GILLT_v8s16*//*Label 2252*/ GIMT_Encode4(72444), GIMT_Encode4(0), |
| 26228 | /* 72308 */ /*GILLT_v4s32*//*Label 2253*/ GIMT_Encode4(72576), |
| 26229 | /* 72312 */ // Label 2251: @72312 |
| 26230 | /* 72312 */ GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(72443), |
| 26231 | /* 72317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26232 | /* 72320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26233 | /* 72323 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26234 | /* 72326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26235 | /* 72330 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26236 | /* 72334 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26237 | /* 72338 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2256*/ GIMT_Encode4(72390), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4955 // |
| 26238 | /* 72345 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26239 | /* 72349 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3889:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26240 | /* 72349 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26241 | /* 72352 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26242 | /* 72356 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26243 | /* 72361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8), |
| 26244 | /* 72364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26245 | /* 72366 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26246 | /* 72368 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26247 | /* 72370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26248 | /* 72373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26249 | /* 72379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26250 | /* 72385 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26251 | /* 72388 */ GIR_RootConstrainSelectedInstOperands, |
| 26252 | /* 72389 */ // GIR_Coverage, 4955, |
| 26253 | /* 72389 */ GIR_EraseRootFromParent_Done, |
| 26254 | /* 72390 */ // Label 2256: @72390 |
| 26255 | /* 72390 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2257*/ GIMT_Encode4(72442), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4970 // |
| 26256 | /* 72397 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26257 | /* 72401 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3889:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26258 | /* 72401 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26259 | /* 72404 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26260 | /* 72408 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26261 | /* 72413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8), |
| 26262 | /* 72416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26263 | /* 72418 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26264 | /* 72420 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26265 | /* 72422 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26266 | /* 72425 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26267 | /* 72431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26268 | /* 72437 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26269 | /* 72440 */ GIR_RootConstrainSelectedInstOperands, |
| 26270 | /* 72441 */ // GIR_Coverage, 4970, |
| 26271 | /* 72441 */ GIR_EraseRootFromParent_Done, |
| 26272 | /* 72442 */ // Label 2257: @72442 |
| 26273 | /* 72442 */ GIM_Reject, |
| 26274 | /* 72443 */ // Label 2255: @72443 |
| 26275 | /* 72443 */ GIM_Reject, |
| 26276 | /* 72444 */ // Label 2252: @72444 |
| 26277 | /* 72444 */ GIM_Try, /*On fail goto*//*Label 2258*/ GIMT_Encode4(72575), |
| 26278 | /* 72449 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26279 | /* 72452 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26280 | /* 72455 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26281 | /* 72458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26282 | /* 72462 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26283 | /* 72466 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26284 | /* 72470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2259*/ GIMT_Encode4(72522), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4962 // |
| 26285 | /* 72477 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26286 | /* 72481 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26287 | /* 72481 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26288 | /* 72484 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26289 | /* 72488 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26290 | /* 72493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16), |
| 26291 | /* 72496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26292 | /* 72498 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26293 | /* 72500 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26294 | /* 72502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26295 | /* 72505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26296 | /* 72511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26297 | /* 72517 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26298 | /* 72520 */ GIR_RootConstrainSelectedInstOperands, |
| 26299 | /* 72521 */ // GIR_Coverage, 4962, |
| 26300 | /* 72521 */ GIR_EraseRootFromParent_Done, |
| 26301 | /* 72522 */ // Label 2259: @72522 |
| 26302 | /* 72522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2260*/ GIMT_Encode4(72574), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4974 // |
| 26303 | /* 72529 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26304 | /* 72533 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26305 | /* 72533 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26306 | /* 72536 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26307 | /* 72540 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26308 | /* 72545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16), |
| 26309 | /* 72548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26310 | /* 72550 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26311 | /* 72552 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26312 | /* 72554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26313 | /* 72557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26314 | /* 72563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26315 | /* 72569 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26316 | /* 72572 */ GIR_RootConstrainSelectedInstOperands, |
| 26317 | /* 72573 */ // GIR_Coverage, 4974, |
| 26318 | /* 72573 */ GIR_EraseRootFromParent_Done, |
| 26319 | /* 72574 */ // Label 2260: @72574 |
| 26320 | /* 72574 */ GIM_Reject, |
| 26321 | /* 72575 */ // Label 2258: @72575 |
| 26322 | /* 72575 */ GIM_Reject, |
| 26323 | /* 72576 */ // Label 2253: @72576 |
| 26324 | /* 72576 */ GIM_Try, /*On fail goto*//*Label 2261*/ GIMT_Encode4(72707), |
| 26325 | /* 72581 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26326 | /* 72584 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26327 | /* 72587 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26328 | /* 72590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26329 | /* 72594 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26330 | /* 72598 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26331 | /* 72602 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2262*/ GIMT_Encode4(72654), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4966 // |
| 26332 | /* 72609 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26333 | /* 72613 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26334 | /* 72613 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26335 | /* 72616 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26336 | /* 72620 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26337 | /* 72625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32), |
| 26338 | /* 72628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26339 | /* 72630 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26340 | /* 72632 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26341 | /* 72634 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26342 | /* 72637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26343 | /* 72643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26344 | /* 72649 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26345 | /* 72652 */ GIR_RootConstrainSelectedInstOperands, |
| 26346 | /* 72653 */ // GIR_Coverage, 4966, |
| 26347 | /* 72653 */ GIR_EraseRootFromParent_Done, |
| 26348 | /* 72654 */ // Label 2262: @72654 |
| 26349 | /* 72654 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2263*/ GIMT_Encode4(72706), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4978 // |
| 26350 | /* 72661 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26351 | /* 72665 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26352 | /* 72665 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26353 | /* 72668 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26354 | /* 72672 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26355 | /* 72677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32), |
| 26356 | /* 72680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26357 | /* 72682 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26358 | /* 72684 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26359 | /* 72686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26360 | /* 72689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26361 | /* 72695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26362 | /* 72701 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26363 | /* 72704 */ GIR_RootConstrainSelectedInstOperands, |
| 26364 | /* 72705 */ // GIR_Coverage, 4978, |
| 26365 | /* 72705 */ GIR_EraseRootFromParent_Done, |
| 26366 | /* 72706 */ // Label 2263: @72706 |
| 26367 | /* 72706 */ GIM_Reject, |
| 26368 | /* 72707 */ // Label 2261: @72707 |
| 26369 | /* 72707 */ GIM_Reject, |
| 26370 | /* 72708 */ // Label 2254: @72708 |
| 26371 | /* 72708 */ GIM_Reject, |
| 26372 | /* 72709 */ // Label 2250: @72709 |
| 26373 | /* 72709 */ GIM_Try, /*On fail goto*//*Label 2264*/ GIMT_Encode4(73147), |
| 26374 | /* 72714 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 26375 | /* 72719 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2268*/ GIMT_Encode4(73146), |
| 26376 | /* 72730 */ /*GILLT_v16s8*//*Label 2265*/ GIMT_Encode4(72750), GIMT_Encode4(0), |
| 26377 | /* 72738 */ /*GILLT_v8s16*//*Label 2266*/ GIMT_Encode4(72882), GIMT_Encode4(0), |
| 26378 | /* 72746 */ /*GILLT_v4s32*//*Label 2267*/ GIMT_Encode4(73014), |
| 26379 | /* 72750 */ // Label 2265: @72750 |
| 26380 | /* 72750 */ GIM_Try, /*On fail goto*//*Label 2269*/ GIMT_Encode4(72881), |
| 26381 | /* 72755 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26382 | /* 72758 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26383 | /* 72761 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26384 | /* 72764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26385 | /* 72768 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26386 | /* 72772 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26387 | /* 72776 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2270*/ GIMT_Encode4(72828), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4979 // |
| 26388 | /* 72783 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26389 | /* 72787 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3929:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26390 | /* 72787 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26391 | /* 72790 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26392 | /* 72794 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26393 | /* 72799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs8), |
| 26394 | /* 72802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26395 | /* 72804 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26396 | /* 72806 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26397 | /* 72808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26398 | /* 72811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26399 | /* 72817 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26400 | /* 72823 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26401 | /* 72826 */ GIR_RootConstrainSelectedInstOperands, |
| 26402 | /* 72827 */ // GIR_Coverage, 4979, |
| 26403 | /* 72827 */ GIR_EraseRootFromParent_Done, |
| 26404 | /* 72828 */ // Label 2270: @72828 |
| 26405 | /* 72828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2271*/ GIMT_Encode4(72880), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4985 // |
| 26406 | /* 72835 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26407 | /* 72839 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3929:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26408 | /* 72839 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26409 | /* 72842 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26410 | /* 72846 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26411 | /* 72851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu8), |
| 26412 | /* 72854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26413 | /* 72856 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26414 | /* 72858 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26415 | /* 72860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26416 | /* 72863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26417 | /* 72869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26418 | /* 72875 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26419 | /* 72878 */ GIR_RootConstrainSelectedInstOperands, |
| 26420 | /* 72879 */ // GIR_Coverage, 4985, |
| 26421 | /* 72879 */ GIR_EraseRootFromParent_Done, |
| 26422 | /* 72880 */ // Label 2271: @72880 |
| 26423 | /* 72880 */ GIM_Reject, |
| 26424 | /* 72881 */ // Label 2269: @72881 |
| 26425 | /* 72881 */ GIM_Reject, |
| 26426 | /* 72882 */ // Label 2266: @72882 |
| 26427 | /* 72882 */ GIM_Try, /*On fail goto*//*Label 2272*/ GIMT_Encode4(73013), |
| 26428 | /* 72887 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26429 | /* 72890 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26430 | /* 72893 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26431 | /* 72896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26432 | /* 72900 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26433 | /* 72904 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26434 | /* 72908 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2273*/ GIMT_Encode4(72960), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4981 // |
| 26435 | /* 72915 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26436 | /* 72919 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3929:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26437 | /* 72919 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26438 | /* 72922 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26439 | /* 72926 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26440 | /* 72931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs16), |
| 26441 | /* 72934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26442 | /* 72936 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26443 | /* 72938 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26444 | /* 72940 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26445 | /* 72943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26446 | /* 72949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26447 | /* 72955 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26448 | /* 72958 */ GIR_RootConstrainSelectedInstOperands, |
| 26449 | /* 72959 */ // GIR_Coverage, 4981, |
| 26450 | /* 72959 */ GIR_EraseRootFromParent_Done, |
| 26451 | /* 72960 */ // Label 2273: @72960 |
| 26452 | /* 72960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2274*/ GIMT_Encode4(73012), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4987 // |
| 26453 | /* 72967 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26454 | /* 72971 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3929:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26455 | /* 72971 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26456 | /* 72974 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26457 | /* 72978 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26458 | /* 72983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu16), |
| 26459 | /* 72986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26460 | /* 72988 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26461 | /* 72990 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26462 | /* 72992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26463 | /* 72995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26464 | /* 73001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26465 | /* 73007 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26466 | /* 73010 */ GIR_RootConstrainSelectedInstOperands, |
| 26467 | /* 73011 */ // GIR_Coverage, 4987, |
| 26468 | /* 73011 */ GIR_EraseRootFromParent_Done, |
| 26469 | /* 73012 */ // Label 2274: @73012 |
| 26470 | /* 73012 */ GIM_Reject, |
| 26471 | /* 73013 */ // Label 2272: @73013 |
| 26472 | /* 73013 */ GIM_Reject, |
| 26473 | /* 73014 */ // Label 2267: @73014 |
| 26474 | /* 73014 */ GIM_Try, /*On fail goto*//*Label 2275*/ GIMT_Encode4(73145), |
| 26475 | /* 73019 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26476 | /* 73022 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26477 | /* 73025 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26478 | /* 73028 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26479 | /* 73032 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26480 | /* 73036 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26481 | /* 73040 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2276*/ GIMT_Encode4(73092), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4983 // |
| 26482 | /* 73047 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26483 | /* 73051 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3929:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26484 | /* 73051 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26485 | /* 73054 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26486 | /* 73058 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26487 | /* 73063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs32), |
| 26488 | /* 73066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26489 | /* 73068 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26490 | /* 73070 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26491 | /* 73072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26492 | /* 73075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26493 | /* 73081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26494 | /* 73087 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26495 | /* 73090 */ GIR_RootConstrainSelectedInstOperands, |
| 26496 | /* 73091 */ // GIR_Coverage, 4983, |
| 26497 | /* 73091 */ GIR_EraseRootFromParent_Done, |
| 26498 | /* 73092 */ // Label 2276: @73092 |
| 26499 | /* 73092 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2277*/ GIMT_Encode4(73144), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4989 // |
| 26500 | /* 73099 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26501 | /* 73103 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3929:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26502 | /* 73103 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26503 | /* 73106 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26504 | /* 73110 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26505 | /* 73115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu32), |
| 26506 | /* 73118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26507 | /* 73120 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26508 | /* 73122 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26509 | /* 73124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26510 | /* 73127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26511 | /* 73133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26512 | /* 73139 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26513 | /* 73142 */ GIR_RootConstrainSelectedInstOperands, |
| 26514 | /* 73143 */ // GIR_Coverage, 4989, |
| 26515 | /* 73143 */ GIR_EraseRootFromParent_Done, |
| 26516 | /* 73144 */ // Label 2277: @73144 |
| 26517 | /* 73144 */ GIM_Reject, |
| 26518 | /* 73145 */ // Label 2275: @73145 |
| 26519 | /* 73145 */ GIM_Reject, |
| 26520 | /* 73146 */ // Label 2268: @73146 |
| 26521 | /* 73146 */ GIM_Reject, |
| 26522 | /* 73147 */ // Label 2264: @73147 |
| 26523 | /* 73147 */ GIM_Try, /*On fail goto*//*Label 2278*/ GIMT_Encode4(73256), |
| 26524 | /* 73152 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow), |
| 26525 | /* 73157 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26526 | /* 73160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26527 | /* 73163 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26528 | /* 73166 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26529 | /* 73169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26530 | /* 73173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26531 | /* 73177 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26532 | /* 73181 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2279*/ GIMT_Encode4(73218), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5040 // |
| 26533 | /* 73188 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26534 | /* 73192 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3844:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf16f32bh:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm) |
| 26535 | /* 73192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32bh), |
| 26536 | /* 73195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26537 | /* 73197 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 26538 | /* 73199 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 26539 | /* 73201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26540 | /* 73204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26541 | /* 73210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26542 | /* 73216 */ GIR_RootConstrainSelectedInstOperands, |
| 26543 | /* 73217 */ // GIR_Coverage, 5040, |
| 26544 | /* 73217 */ GIR_EraseRootFromParent_Done, |
| 26545 | /* 73218 */ // Label 2279: @73218 |
| 26546 | /* 73218 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2280*/ GIMT_Encode4(73255), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5046 // |
| 26547 | /* 73225 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26548 | /* 73229 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3844:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf16f32th:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm) |
| 26549 | /* 73229 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32th), |
| 26550 | /* 73232 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26551 | /* 73234 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 26552 | /* 73236 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 26553 | /* 73238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26554 | /* 73241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26555 | /* 73247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26556 | /* 73253 */ GIR_RootConstrainSelectedInstOperands, |
| 26557 | /* 73254 */ // GIR_Coverage, 5046, |
| 26558 | /* 73254 */ GIR_EraseRootFromParent_Done, |
| 26559 | /* 73255 */ // Label 2280: @73255 |
| 26560 | /* 73255 */ GIM_Reject, |
| 26561 | /* 73256 */ // Label 2278: @73256 |
| 26562 | /* 73256 */ GIM_Try, /*On fail goto*//*Label 2281*/ GIMT_Encode4(73550), |
| 26563 | /* 73261 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull), |
| 26564 | /* 73266 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2284*/ GIMT_Encode4(73549), |
| 26565 | /* 73277 */ /*GILLT_v4s32*//*Label 2282*/ GIMT_Encode4(73285), |
| 26566 | /* 73281 */ /*GILLT_v2s64*//*Label 2283*/ GIMT_Encode4(73417), |
| 26567 | /* 73285 */ // Label 2282: @73285 |
| 26568 | /* 73285 */ GIM_Try, /*On fail goto*//*Label 2285*/ GIMT_Encode4(73416), |
| 26569 | /* 73290 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26570 | /* 73293 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26571 | /* 73296 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26572 | /* 73299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26573 | /* 73303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26574 | /* 73307 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26575 | /* 73311 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2286*/ GIMT_Encode4(73363), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5064 // |
| 26576 | /* 73318 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26577 | /* 73322 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3899:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26578 | /* 73322 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26579 | /* 73325 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26580 | /* 73329 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26581 | /* 73334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16bh), |
| 26582 | /* 73337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26583 | /* 73339 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26584 | /* 73341 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26585 | /* 73343 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26586 | /* 73346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26587 | /* 73352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26588 | /* 73358 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26589 | /* 73361 */ GIR_RootConstrainSelectedInstOperands, |
| 26590 | /* 73362 */ // GIR_Coverage, 5064, |
| 26591 | /* 73362 */ GIR_EraseRootFromParent_Done, |
| 26592 | /* 73363 */ // Label 2286: @73363 |
| 26593 | /* 73363 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2287*/ GIMT_Encode4(73415), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5066 // |
| 26594 | /* 73370 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26595 | /* 73374 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3899:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26596 | /* 73374 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26597 | /* 73377 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26598 | /* 73381 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26599 | /* 73386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16th), |
| 26600 | /* 73389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26601 | /* 73391 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26602 | /* 73393 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26603 | /* 73395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26604 | /* 73398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26605 | /* 73404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26606 | /* 73410 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26607 | /* 73413 */ GIR_RootConstrainSelectedInstOperands, |
| 26608 | /* 73414 */ // GIR_Coverage, 5066, |
| 26609 | /* 73414 */ GIR_EraseRootFromParent_Done, |
| 26610 | /* 73415 */ // Label 2287: @73415 |
| 26611 | /* 73415 */ GIM_Reject, |
| 26612 | /* 73416 */ // Label 2285: @73416 |
| 26613 | /* 73416 */ GIM_Reject, |
| 26614 | /* 73417 */ // Label 2283: @73417 |
| 26615 | /* 73417 */ GIM_Try, /*On fail goto*//*Label 2288*/ GIMT_Encode4(73548), |
| 26616 | /* 73422 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26617 | /* 73425 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26618 | /* 73428 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26619 | /* 73431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26620 | /* 73435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26621 | /* 73439 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26622 | /* 73443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2289*/ GIMT_Encode4(73495), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5068 // |
| 26623 | /* 73450 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26624 | /* 73454 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3899:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs32bh:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26625 | /* 73454 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26626 | /* 73457 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26627 | /* 73461 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26628 | /* 73466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32bh), |
| 26629 | /* 73469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26630 | /* 73471 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26631 | /* 73473 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26632 | /* 73475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26633 | /* 73478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26634 | /* 73484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26635 | /* 73490 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26636 | /* 73493 */ GIR_RootConstrainSelectedInstOperands, |
| 26637 | /* 73494 */ // GIR_Coverage, 5068, |
| 26638 | /* 73494 */ GIR_EraseRootFromParent_Done, |
| 26639 | /* 73495 */ // Label 2289: @73495 |
| 26640 | /* 73495 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2290*/ GIMT_Encode4(73547), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5070 // |
| 26641 | /* 73502 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26642 | /* 73506 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3899:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs32th:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26643 | /* 73506 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26644 | /* 73509 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26645 | /* 73513 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26646 | /* 73518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32th), |
| 26647 | /* 73521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26648 | /* 73523 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26649 | /* 73525 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26650 | /* 73527 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26651 | /* 73530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26652 | /* 73536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26653 | /* 73542 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26654 | /* 73545 */ GIR_RootConstrainSelectedInstOperands, |
| 26655 | /* 73546 */ // GIR_Coverage, 5070, |
| 26656 | /* 73546 */ GIR_EraseRootFromParent_Done, |
| 26657 | /* 73547 */ // Label 2290: @73547 |
| 26658 | /* 73547 */ GIM_Reject, |
| 26659 | /* 73548 */ // Label 2288: @73548 |
| 26660 | /* 73548 */ GIM_Reject, |
| 26661 | /* 73549 */ // Label 2284: @73549 |
| 26662 | /* 73549 */ GIM_Reject, |
| 26663 | /* 73550 */ // Label 2281: @73550 |
| 26664 | /* 73550 */ GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(73740), |
| 26665 | /* 73555 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma), |
| 26666 | /* 73560 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2294*/ GIMT_Encode4(73739), |
| 26667 | /* 73571 */ /*GILLT_v8s16*//*Label 2292*/ GIMT_Encode4(73583), GIMT_Encode4(0), |
| 26668 | /* 73579 */ /*GILLT_v4s32*//*Label 2293*/ GIMT_Encode4(73661), |
| 26669 | /* 73583 */ // Label 2292: @73583 |
| 26670 | /* 73583 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2295*/ GIMT_Encode4(73660), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4450 // |
| 26671 | /* 73590 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26672 | /* 73593 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26673 | /* 73596 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 26674 | /* 73599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26675 | /* 73603 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 26676 | /* 73607 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 26677 | /* 73611 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 26678 | /* 73615 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26679 | /* 73620 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26680 | /* 73624 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26681 | /* 73628 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26682 | /* 73630 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3764:{ *:[iPTR] }, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 26683 | /* 73630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16), |
| 26684 | /* 73633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26685 | /* 73635 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 26686 | /* 73637 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 26687 | /* 73641 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2 |
| 26688 | /* 73643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26689 | /* 73646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26690 | /* 73652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26691 | /* 73658 */ GIR_RootConstrainSelectedInstOperands, |
| 26692 | /* 73659 */ // GIR_Coverage, 4450, |
| 26693 | /* 73659 */ GIR_EraseRootFromParent_Done, |
| 26694 | /* 73660 */ // Label 2295: @73660 |
| 26695 | /* 73660 */ GIM_Reject, |
| 26696 | /* 73661 */ // Label 2293: @73661 |
| 26697 | /* 73661 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2296*/ GIMT_Encode4(73738), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4436 // |
| 26698 | /* 73668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26699 | /* 73671 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26700 | /* 73674 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26701 | /* 73677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26702 | /* 73681 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 26703 | /* 73685 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 26704 | /* 73689 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 26705 | /* 73693 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26706 | /* 73698 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26707 | /* 73702 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26708 | /* 73706 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26709 | /* 73708 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3764:{ *:[iPTR] }, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 26710 | /* 73708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32), |
| 26711 | /* 73711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26712 | /* 73713 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 26713 | /* 73715 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 26714 | /* 73719 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2 |
| 26715 | /* 73721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26716 | /* 73724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26717 | /* 73730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26718 | /* 73736 */ GIR_RootConstrainSelectedInstOperands, |
| 26719 | /* 73737 */ // GIR_Coverage, 4436, |
| 26720 | /* 73737 */ GIR_EraseRootFromParent_Done, |
| 26721 | /* 73738 */ // Label 2296: @73738 |
| 26722 | /* 73738 */ GIM_Reject, |
| 26723 | /* 73739 */ // Label 2294: @73739 |
| 26724 | /* 73739 */ GIM_Reject, |
| 26725 | /* 73740 */ // Label 2291: @73740 |
| 26726 | /* 73740 */ GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(73940), |
| 26727 | /* 73745 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq), |
| 26728 | /* 73750 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2300*/ GIMT_Encode4(73939), |
| 26729 | /* 73761 */ /*GILLT_v8s16*//*Label 2298*/ GIMT_Encode4(73773), GIMT_Encode4(0), |
| 26730 | /* 73769 */ /*GILLT_v4s32*//*Label 2299*/ GIMT_Encode4(73856), |
| 26731 | /* 73773 */ // Label 2298: @73773 |
| 26732 | /* 73773 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2301*/ GIMT_Encode4(73855), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4894 // |
| 26733 | /* 73780 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26734 | /* 73783 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26735 | /* 73786 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 26736 | /* 73789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26737 | /* 73793 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 26738 | /* 73797 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 26739 | /* 73801 */ // MIs[1] Operand 1 |
| 26740 | /* 73801 */ // No operand predicates |
| 26741 | /* 73801 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26742 | /* 73805 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26743 | /* 73809 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26744 | /* 73811 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3833:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 26745 | /* 73811 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26746 | /* 73814 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26747 | /* 73818 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26748 | /* 73823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf16), |
| 26749 | /* 73826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26750 | /* 73828 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26751 | /* 73830 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm |
| 26752 | /* 73832 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 26753 | /* 73835 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26754 | /* 73838 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26755 | /* 73844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26756 | /* 73850 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26757 | /* 73853 */ GIR_RootConstrainSelectedInstOperands, |
| 26758 | /* 73854 */ // GIR_Coverage, 4894, |
| 26759 | /* 73854 */ GIR_EraseRootFromParent_Done, |
| 26760 | /* 73855 */ // Label 2301: @73855 |
| 26761 | /* 73855 */ GIM_Reject, |
| 26762 | /* 73856 */ // Label 2299: @73856 |
| 26763 | /* 73856 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2302*/ GIMT_Encode4(73938), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4896 // |
| 26764 | /* 73863 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26765 | /* 73866 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26766 | /* 73869 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26767 | /* 73872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26768 | /* 73876 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 26769 | /* 73880 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 26770 | /* 73884 */ // MIs[1] Operand 1 |
| 26771 | /* 73884 */ // No operand predicates |
| 26772 | /* 73884 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26773 | /* 73888 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26774 | /* 73892 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26775 | /* 73894 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3833:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 26776 | /* 73894 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26777 | /* 73897 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26778 | /* 73901 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26779 | /* 73906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf32), |
| 26780 | /* 73909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26781 | /* 73911 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26782 | /* 73913 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm |
| 26783 | /* 73915 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 26784 | /* 73918 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26785 | /* 73921 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26786 | /* 73927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26787 | /* 73933 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26788 | /* 73936 */ GIR_RootConstrainSelectedInstOperands, |
| 26789 | /* 73937 */ // GIR_Coverage, 4896, |
| 26790 | /* 73937 */ GIR_EraseRootFromParent_Done, |
| 26791 | /* 73938 */ // Label 2302: @73938 |
| 26792 | /* 73938 */ GIM_Reject, |
| 26793 | /* 73939 */ // Label 2300: @73939 |
| 26794 | /* 73939 */ GIM_Reject, |
| 26795 | /* 73940 */ // Label 2297: @73940 |
| 26796 | /* 73940 */ GIM_Try, /*On fail goto*//*Label 2303*/ GIMT_Encode4(74130), |
| 26797 | /* 73945 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma), |
| 26798 | /* 73950 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2306*/ GIMT_Encode4(74129), |
| 26799 | /* 73961 */ /*GILLT_v8s16*//*Label 2304*/ GIMT_Encode4(73973), GIMT_Encode4(0), |
| 26800 | /* 73969 */ /*GILLT_v4s32*//*Label 2305*/ GIMT_Encode4(74051), |
| 26801 | /* 73973 */ // Label 2304: @73973 |
| 26802 | /* 73973 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2307*/ GIMT_Encode4(74050), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4451 // |
| 26803 | /* 73980 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26804 | /* 73983 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26805 | /* 73986 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 26806 | /* 73989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26807 | /* 73993 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26808 | /* 73997 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 26809 | /* 74001 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 26810 | /* 74005 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 26811 | /* 74009 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26812 | /* 74014 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26813 | /* 74018 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26814 | /* 74020 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3764:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$m1, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m2), MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 26815 | /* 74020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16), |
| 26816 | /* 74023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26817 | /* 74025 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 26818 | /* 74027 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1 |
| 26819 | /* 74029 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m2 |
| 26820 | /* 74033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26821 | /* 74036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26822 | /* 74042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26823 | /* 74048 */ GIR_RootConstrainSelectedInstOperands, |
| 26824 | /* 74049 */ // GIR_Coverage, 4451, |
| 26825 | /* 74049 */ GIR_EraseRootFromParent_Done, |
| 26826 | /* 74050 */ // Label 2307: @74050 |
| 26827 | /* 74050 */ GIM_Reject, |
| 26828 | /* 74051 */ // Label 2305: @74051 |
| 26829 | /* 74051 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2308*/ GIMT_Encode4(74128), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4437 // |
| 26830 | /* 74058 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26831 | /* 74061 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26832 | /* 74064 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26833 | /* 74067 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26834 | /* 74071 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26835 | /* 74075 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 26836 | /* 74079 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 26837 | /* 74083 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 26838 | /* 74087 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26839 | /* 74092 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26840 | /* 74096 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26841 | /* 74098 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3764:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$m1, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m2), MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 26842 | /* 74098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32), |
| 26843 | /* 74101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26844 | /* 74103 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 26845 | /* 74105 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1 |
| 26846 | /* 74107 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m2 |
| 26847 | /* 74111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26848 | /* 74114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26849 | /* 74120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26850 | /* 74126 */ GIR_RootConstrainSelectedInstOperands, |
| 26851 | /* 74127 */ // GIR_Coverage, 4437, |
| 26852 | /* 74127 */ GIR_EraseRootFromParent_Done, |
| 26853 | /* 74128 */ // Label 2308: @74128 |
| 26854 | /* 74128 */ GIM_Reject, |
| 26855 | /* 74129 */ // Label 2306: @74129 |
| 26856 | /* 74129 */ GIM_Reject, |
| 26857 | /* 74130 */ // Label 2303: @74130 |
| 26858 | /* 74130 */ GIM_Try, /*On fail goto*//*Label 2309*/ GIMT_Encode4(74243), |
| 26859 | /* 74135 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8), |
| 26860 | /* 74140 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26861 | /* 74143 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26862 | /* 74146 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26863 | /* 74149 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26864 | /* 74152 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2310*/ GIMT_Encode4(74197), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 145 // |
| 26865 | /* 74159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26866 | /* 74163 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26867 | /* 74167 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26868 | /* 74171 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26869 | /* 74175 */ // (intrinsic_wo_chain:{ *:[i32] } 4171:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (USADA8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 26870 | /* 74175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USADA8), |
| 26871 | /* 74178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 26872 | /* 74180 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 26873 | /* 74182 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 26874 | /* 74184 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 26875 | /* 74186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26876 | /* 74189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26877 | /* 74195 */ GIR_RootConstrainSelectedInstOperands, |
| 26878 | /* 74196 */ // GIR_Coverage, 145, |
| 26879 | /* 74196 */ GIR_EraseRootFromParent_Done, |
| 26880 | /* 74197 */ // Label 2310: @74197 |
| 26881 | /* 74197 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2311*/ GIMT_Encode4(74242), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 468 // |
| 26882 | /* 74204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26883 | /* 74208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26884 | /* 74212 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26885 | /* 74216 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26886 | /* 74220 */ // (intrinsic_wo_chain:{ *:[i32] } 4171:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2USADA8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 26887 | /* 74220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USADA8), |
| 26888 | /* 74223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 26889 | /* 74225 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 26890 | /* 74227 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 26891 | /* 74229 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 26892 | /* 74231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26893 | /* 74234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26894 | /* 74240 */ GIR_RootConstrainSelectedInstOperands, |
| 26895 | /* 74241 */ // GIR_Coverage, 468, |
| 26896 | /* 74241 */ GIR_EraseRootFromParent_Done, |
| 26897 | /* 74242 */ // Label 2311: @74242 |
| 26898 | /* 74242 */ GIM_Reject, |
| 26899 | /* 74243 */ // Label 2309: @74243 |
| 26900 | /* 74243 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2312*/ GIMT_Encode4(74305), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 527 // |
| 26901 | /* 74250 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad), |
| 26902 | /* 74255 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26903 | /* 74258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26904 | /* 74261 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26905 | /* 74264 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26906 | /* 74267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26907 | /* 74271 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26908 | /* 74275 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26909 | /* 74279 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26910 | /* 74283 */ // (intrinsic_wo_chain:{ *:[i32] } 4116:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 26911 | /* 74283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAD), |
| 26912 | /* 74286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 26913 | /* 74288 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 26914 | /* 74290 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 26915 | /* 74292 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 26916 | /* 74294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26917 | /* 74297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26918 | /* 74303 */ GIR_RootConstrainSelectedInstOperands, |
| 26919 | /* 74304 */ // GIR_Coverage, 527, |
| 26920 | /* 74304 */ GIR_EraseRootFromParent_Done, |
| 26921 | /* 74305 */ // Label 2312: @74305 |
| 26922 | /* 74305 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2313*/ GIMT_Encode4(74367), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 528 // |
| 26923 | /* 74312 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx), |
| 26924 | /* 74317 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26925 | /* 74320 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26926 | /* 74323 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26927 | /* 74326 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26928 | /* 74329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26929 | /* 74333 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26930 | /* 74337 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26931 | /* 74341 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26932 | /* 74345 */ // (intrinsic_wo_chain:{ *:[i32] } 4117:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 26933 | /* 74345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLADX), |
| 26934 | /* 74348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 26935 | /* 74350 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 26936 | /* 74352 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 26937 | /* 74354 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 26938 | /* 74356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26939 | /* 74359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26940 | /* 74365 */ GIR_RootConstrainSelectedInstOperands, |
| 26941 | /* 74366 */ // GIR_Coverage, 528, |
| 26942 | /* 74366 */ GIR_EraseRootFromParent_Done, |
| 26943 | /* 74367 */ // Label 2313: @74367 |
| 26944 | /* 74367 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2314*/ GIMT_Encode4(74429), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 529 // |
| 26945 | /* 74374 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd), |
| 26946 | /* 74379 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26947 | /* 74382 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26948 | /* 74385 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26949 | /* 74388 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26950 | /* 74391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26951 | /* 74395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26952 | /* 74399 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26953 | /* 74403 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26954 | /* 74407 */ // (intrinsic_wo_chain:{ *:[i32] } 4124:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 26955 | /* 74407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSD), |
| 26956 | /* 74410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 26957 | /* 74412 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 26958 | /* 74414 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 26959 | /* 74416 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 26960 | /* 74418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26961 | /* 74421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26962 | /* 74427 */ GIR_RootConstrainSelectedInstOperands, |
| 26963 | /* 74428 */ // GIR_Coverage, 529, |
| 26964 | /* 74428 */ GIR_EraseRootFromParent_Done, |
| 26965 | /* 74429 */ // Label 2314: @74429 |
| 26966 | /* 74429 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2315*/ GIMT_Encode4(74491), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 530 // |
| 26967 | /* 74436 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx), |
| 26968 | /* 74441 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26969 | /* 74444 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26970 | /* 74447 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26971 | /* 74450 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26972 | /* 74453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26973 | /* 74457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26974 | /* 74461 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26975 | /* 74465 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26976 | /* 74469 */ // (intrinsic_wo_chain:{ *:[i32] } 4125:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 26977 | /* 74469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSDX), |
| 26978 | /* 74472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 26979 | /* 74474 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 26980 | /* 74476 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 26981 | /* 74478 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 26982 | /* 74480 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26983 | /* 74483 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26984 | /* 74489 */ GIR_RootConstrainSelectedInstOperands, |
| 26985 | /* 74490 */ // GIR_Coverage, 530, |
| 26986 | /* 74490 */ GIR_EraseRootFromParent_Done, |
| 26987 | /* 74491 */ // Label 2315: @74491 |
| 26988 | /* 74491 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2316*/ GIMT_Encode4(74544), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1113 // |
| 26989 | /* 74498 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot), |
| 26990 | /* 74503 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 26991 | /* 74506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 26992 | /* 74509 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 26993 | /* 74512 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 26994 | /* 74515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26995 | /* 74519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26996 | /* 74523 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26997 | /* 74527 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26998 | /* 74531 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3977:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 26999 | /* 74531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTD), |
| 27000 | /* 74534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27001 | /* 74536 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27002 | /* 74538 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27003 | /* 74540 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27004 | /* 74542 */ GIR_RootConstrainSelectedInstOperands, |
| 27005 | /* 74543 */ // GIR_Coverage, 1113, |
| 27006 | /* 74543 */ GIR_EraseRootFromParent_Done, |
| 27007 | /* 74544 */ // Label 2316: @74544 |
| 27008 | /* 74544 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2317*/ GIMT_Encode4(74597), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1114 // |
| 27009 | /* 74551 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot), |
| 27010 | /* 74556 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 27011 | /* 74559 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 27012 | /* 74562 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 27013 | /* 74565 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 27014 | /* 74568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27015 | /* 74572 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27016 | /* 74576 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27017 | /* 74580 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27018 | /* 74584 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3965:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 27019 | /* 74584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTD), |
| 27020 | /* 74587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27021 | /* 74589 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27022 | /* 74591 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27023 | /* 74593 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27024 | /* 74595 */ GIR_RootConstrainSelectedInstOperands, |
| 27025 | /* 74596 */ // GIR_Coverage, 1114, |
| 27026 | /* 74596 */ GIR_EraseRootFromParent_Done, |
| 27027 | /* 74597 */ // Label 2317: @74597 |
| 27028 | /* 74597 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2318*/ GIMT_Encode4(74650), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1115 // |
| 27029 | /* 74604 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot), |
| 27030 | /* 74609 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27031 | /* 74612 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27032 | /* 74615 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27033 | /* 74618 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27034 | /* 74621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27035 | /* 74625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27036 | /* 74629 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27037 | /* 74633 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27038 | /* 74637 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3977:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 27039 | /* 74637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTQ), |
| 27040 | /* 74640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27041 | /* 74642 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27042 | /* 74644 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27043 | /* 74646 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27044 | /* 74648 */ GIR_RootConstrainSelectedInstOperands, |
| 27045 | /* 74649 */ // GIR_Coverage, 1115, |
| 27046 | /* 74649 */ GIR_EraseRootFromParent_Done, |
| 27047 | /* 74650 */ // Label 2318: @74650 |
| 27048 | /* 74650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2319*/ GIMT_Encode4(74703), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1116 // |
| 27049 | /* 74657 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot), |
| 27050 | /* 74662 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27051 | /* 74665 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27052 | /* 74668 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27053 | /* 74671 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27054 | /* 74674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27055 | /* 74678 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27056 | /* 74682 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27057 | /* 74686 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27058 | /* 74690 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3965:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 27059 | /* 74690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTQ), |
| 27060 | /* 74693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27061 | /* 74695 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27062 | /* 74697 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27063 | /* 74699 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27064 | /* 74701 */ GIR_RootConstrainSelectedInstOperands, |
| 27065 | /* 74702 */ // GIR_Coverage, 1116, |
| 27066 | /* 74702 */ GIR_EraseRootFromParent_Done, |
| 27067 | /* 74703 */ // Label 2319: @74703 |
| 27068 | /* 74703 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2320*/ GIMT_Encode4(74756), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1117 // |
| 27069 | /* 74710 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_smmla), |
| 27070 | /* 74715 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27071 | /* 74718 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27072 | /* 74721 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27073 | /* 74724 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27074 | /* 74727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27075 | /* 74731 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27076 | /* 74735 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27077 | /* 74739 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27078 | /* 74743 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3976:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 27079 | /* 74743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSMMLA), |
| 27080 | /* 74746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27081 | /* 74748 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27082 | /* 74750 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27083 | /* 74752 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27084 | /* 74754 */ GIR_RootConstrainSelectedInstOperands, |
| 27085 | /* 74755 */ // GIR_Coverage, 1117, |
| 27086 | /* 74755 */ GIR_EraseRootFromParent_Done, |
| 27087 | /* 74756 */ // Label 2320: @74756 |
| 27088 | /* 74756 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2321*/ GIMT_Encode4(74809), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1118 // |
| 27089 | /* 74763 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_ummla), |
| 27090 | /* 74768 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27091 | /* 74771 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27092 | /* 74774 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27093 | /* 74777 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27094 | /* 74780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27095 | /* 74784 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27096 | /* 74788 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27097 | /* 74792 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27098 | /* 74796 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3978:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 27099 | /* 74796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUMMLA), |
| 27100 | /* 74799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27101 | /* 74801 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27102 | /* 74803 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27103 | /* 74805 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27104 | /* 74807 */ GIR_RootConstrainSelectedInstOperands, |
| 27105 | /* 74808 */ // GIR_Coverage, 1118, |
| 27106 | /* 74808 */ GIR_EraseRootFromParent_Done, |
| 27107 | /* 74809 */ // Label 2321: @74809 |
| 27108 | /* 74809 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2322*/ GIMT_Encode4(74862), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1119 // |
| 27109 | /* 74816 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usmmla), |
| 27110 | /* 74821 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27111 | /* 74824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27112 | /* 74827 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27113 | /* 74830 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27114 | /* 74833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27115 | /* 74837 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27116 | /* 74841 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27117 | /* 74845 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27118 | /* 74849 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3980:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 27119 | /* 74849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSMMLA), |
| 27120 | /* 74852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27121 | /* 74854 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27122 | /* 74856 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27123 | /* 74858 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27124 | /* 74860 */ GIR_RootConstrainSelectedInstOperands, |
| 27125 | /* 74861 */ // GIR_Coverage, 1119, |
| 27126 | /* 74861 */ GIR_EraseRootFromParent_Done, |
| 27127 | /* 74862 */ // Label 2322: @74862 |
| 27128 | /* 74862 */ GIM_Try, /*On fail goto*//*Label 2323*/ GIMT_Encode4(74984), |
| 27129 | /* 74867 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot), |
| 27130 | /* 74872 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 2326*/ GIMT_Encode4(74983), |
| 27131 | /* 74883 */ /*GILLT_v2s32*//*Label 2324*/ GIMT_Encode4(74891), |
| 27132 | /* 74887 */ /*GILLT_v4s32*//*Label 2325*/ GIMT_Encode4(74937), |
| 27133 | /* 74891 */ // Label 2324: @74891 |
| 27134 | /* 74891 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2327*/ GIMT_Encode4(74936), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1120 // |
| 27135 | /* 74898 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 27136 | /* 74901 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 27137 | /* 74904 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 27138 | /* 74907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27139 | /* 74911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27140 | /* 74915 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27141 | /* 74919 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27142 | /* 74923 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3979:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 27143 | /* 74923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTD), |
| 27144 | /* 74926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27145 | /* 74928 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27146 | /* 74930 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27147 | /* 74932 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27148 | /* 74934 */ GIR_RootConstrainSelectedInstOperands, |
| 27149 | /* 74935 */ // GIR_Coverage, 1120, |
| 27150 | /* 74935 */ GIR_EraseRootFromParent_Done, |
| 27151 | /* 74936 */ // Label 2327: @74936 |
| 27152 | /* 74936 */ GIM_Reject, |
| 27153 | /* 74937 */ // Label 2325: @74937 |
| 27154 | /* 74937 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2328*/ GIMT_Encode4(74982), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1121 // |
| 27155 | /* 74944 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27156 | /* 74947 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27157 | /* 74950 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27158 | /* 74953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27159 | /* 74957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27160 | /* 74961 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27161 | /* 74965 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27162 | /* 74969 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3979:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 27163 | /* 74969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTQ), |
| 27164 | /* 74972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27165 | /* 74974 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27166 | /* 74976 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27167 | /* 74978 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27168 | /* 74980 */ GIR_RootConstrainSelectedInstOperands, |
| 27169 | /* 74981 */ // GIR_Coverage, 1121, |
| 27170 | /* 74981 */ GIR_EraseRootFromParent_Done, |
| 27171 | /* 74982 */ // Label 2328: @74982 |
| 27172 | /* 74982 */ GIM_Reject, |
| 27173 | /* 74983 */ // Label 2326: @74983 |
| 27174 | /* 74983 */ GIM_Reject, |
| 27175 | /* 74984 */ // Label 2323: @74984 |
| 27176 | /* 74984 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2329*/ GIMT_Encode4(75046), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1852 // |
| 27177 | /* 74991 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx1), |
| 27178 | /* 74996 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 27179 | /* 74999 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 27180 | /* 75002 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 27181 | /* 75005 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 27182 | /* 75008 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27183 | /* 75012 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27184 | /* 75016 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27185 | /* 75020 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27186 | /* 75024 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4091:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VTBX1:{ *:[v8i8] } DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 27187 | /* 75024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX1), |
| 27188 | /* 75027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27189 | /* 75029 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 27190 | /* 75031 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27191 | /* 75033 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27192 | /* 75035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27193 | /* 75038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27194 | /* 75044 */ GIR_RootConstrainSelectedInstOperands, |
| 27195 | /* 75045 */ // GIR_Coverage, 1852, |
| 27196 | /* 75045 */ GIR_EraseRootFromParent_Done, |
| 27197 | /* 75046 */ // Label 2329: @75046 |
| 27198 | /* 75046 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2330*/ GIMT_Encode4(75099), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1907 // |
| 27199 | /* 75053 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su0), |
| 27200 | /* 75058 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27201 | /* 75061 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27202 | /* 75064 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27203 | /* 75067 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27204 | /* 75070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27205 | /* 75074 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27206 | /* 75078 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27207 | /* 75082 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27208 | /* 75086 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3970:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 27209 | /* 75086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU0), |
| 27210 | /* 75089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27211 | /* 75091 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 27212 | /* 75093 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27213 | /* 75095 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27214 | /* 75097 */ GIR_RootConstrainSelectedInstOperands, |
| 27215 | /* 75098 */ // GIR_Coverage, 1907, |
| 27216 | /* 75098 */ GIR_EraseRootFromParent_Done, |
| 27217 | /* 75099 */ // Label 2330: @75099 |
| 27218 | /* 75099 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2331*/ GIMT_Encode4(75152), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1908 // |
| 27219 | /* 75106 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h), |
| 27220 | /* 75111 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27221 | /* 75114 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27222 | /* 75117 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27223 | /* 75120 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27224 | /* 75123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27225 | /* 75127 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27226 | /* 75131 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27227 | /* 75135 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27228 | /* 75139 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3972:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 27229 | /* 75139 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H), |
| 27230 | /* 75142 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27231 | /* 75144 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 27232 | /* 75146 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27233 | /* 75148 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27234 | /* 75150 */ GIR_RootConstrainSelectedInstOperands, |
| 27235 | /* 75151 */ // GIR_Coverage, 1908, |
| 27236 | /* 75151 */ GIR_EraseRootFromParent_Done, |
| 27237 | /* 75152 */ // Label 2331: @75152 |
| 27238 | /* 75152 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2332*/ GIMT_Encode4(75205), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1909 // |
| 27239 | /* 75159 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h2), |
| 27240 | /* 75164 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27241 | /* 75167 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27242 | /* 75170 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27243 | /* 75173 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27244 | /* 75176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27245 | /* 75180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27246 | /* 75184 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27247 | /* 75188 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27248 | /* 75192 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3973:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H2:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 27249 | /* 75192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H2), |
| 27250 | /* 75195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27251 | /* 75197 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 27252 | /* 75199 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27253 | /* 75201 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27254 | /* 75203 */ GIR_RootConstrainSelectedInstOperands, |
| 27255 | /* 75204 */ // GIR_Coverage, 1909, |
| 27256 | /* 75204 */ GIR_EraseRootFromParent_Done, |
| 27257 | /* 75205 */ // Label 2332: @75205 |
| 27258 | /* 75205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2333*/ GIMT_Encode4(75258), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1910 // |
| 27259 | /* 75212 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su1), |
| 27260 | /* 75217 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27261 | /* 75220 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27262 | /* 75223 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27263 | /* 75226 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27264 | /* 75229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27265 | /* 75233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27266 | /* 75237 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27267 | /* 75241 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27268 | /* 75245 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3975:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 27269 | /* 75245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU1), |
| 27270 | /* 75248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27271 | /* 75250 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 27272 | /* 75252 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27273 | /* 75254 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27274 | /* 75256 */ GIR_RootConstrainSelectedInstOperands, |
| 27275 | /* 75257 */ // GIR_Coverage, 1910, |
| 27276 | /* 75257 */ GIR_EraseRootFromParent_Done, |
| 27277 | /* 75258 */ // Label 2333: @75258 |
| 27278 | /* 75258 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2334*/ GIMT_Encode4(75320), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2087 // |
| 27279 | /* 75265 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad), |
| 27280 | /* 75270 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27281 | /* 75273 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27282 | /* 75276 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27283 | /* 75279 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27284 | /* 75282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27285 | /* 75286 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27286 | /* 75290 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27287 | /* 75294 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27288 | /* 75298 */ // (intrinsic_wo_chain:{ *:[i32] } 4116:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 27289 | /* 75298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAD), |
| 27290 | /* 75301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27291 | /* 75303 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 27292 | /* 75305 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 27293 | /* 75307 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 27294 | /* 75309 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27295 | /* 75312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27296 | /* 75318 */ GIR_RootConstrainSelectedInstOperands, |
| 27297 | /* 75319 */ // GIR_Coverage, 2087, |
| 27298 | /* 75319 */ GIR_EraseRootFromParent_Done, |
| 27299 | /* 75320 */ // Label 2334: @75320 |
| 27300 | /* 75320 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2335*/ GIMT_Encode4(75382), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2088 // |
| 27301 | /* 75327 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx), |
| 27302 | /* 75332 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27303 | /* 75335 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27304 | /* 75338 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27305 | /* 75341 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27306 | /* 75344 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27307 | /* 75348 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27308 | /* 75352 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27309 | /* 75356 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27310 | /* 75360 */ // (intrinsic_wo_chain:{ *:[i32] } 4117:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 27311 | /* 75360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLADX), |
| 27312 | /* 75363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27313 | /* 75365 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 27314 | /* 75367 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 27315 | /* 75369 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 27316 | /* 75371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27317 | /* 75374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27318 | /* 75380 */ GIR_RootConstrainSelectedInstOperands, |
| 27319 | /* 75381 */ // GIR_Coverage, 2088, |
| 27320 | /* 75381 */ GIR_EraseRootFromParent_Done, |
| 27321 | /* 75382 */ // Label 2335: @75382 |
| 27322 | /* 75382 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2336*/ GIMT_Encode4(75444), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2089 // |
| 27323 | /* 75389 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd), |
| 27324 | /* 75394 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27325 | /* 75397 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27326 | /* 75400 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27327 | /* 75403 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27328 | /* 75406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27329 | /* 75410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27330 | /* 75414 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27331 | /* 75418 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27332 | /* 75422 */ // (intrinsic_wo_chain:{ *:[i32] } 4124:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 27333 | /* 75422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSD), |
| 27334 | /* 75425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27335 | /* 75427 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 27336 | /* 75429 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 27337 | /* 75431 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 27338 | /* 75433 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27339 | /* 75436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27340 | /* 75442 */ GIR_RootConstrainSelectedInstOperands, |
| 27341 | /* 75443 */ // GIR_Coverage, 2089, |
| 27342 | /* 75443 */ GIR_EraseRootFromParent_Done, |
| 27343 | /* 75444 */ // Label 2336: @75444 |
| 27344 | /* 75444 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2337*/ GIMT_Encode4(75506), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2090 // |
| 27345 | /* 75451 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx), |
| 27346 | /* 75456 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27347 | /* 75459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27348 | /* 75462 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27349 | /* 75465 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27350 | /* 75468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27351 | /* 75472 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27352 | /* 75476 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27353 | /* 75480 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27354 | /* 75484 */ // (intrinsic_wo_chain:{ *:[i32] } 4125:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 27355 | /* 75484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSDX), |
| 27356 | /* 75487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27357 | /* 75489 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 27358 | /* 75491 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 27359 | /* 75493 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 27360 | /* 75495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27361 | /* 75498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27362 | /* 75504 */ GIR_RootConstrainSelectedInstOperands, |
| 27363 | /* 75505 */ // GIR_Coverage, 2090, |
| 27364 | /* 75505 */ GIR_EraseRootFromParent_Done, |
| 27365 | /* 75506 */ // Label 2337: @75506 |
| 27366 | /* 75506 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2338*/ GIMT_Encode4(75568), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2185 // |
| 27367 | /* 75513 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb), |
| 27368 | /* 75518 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27369 | /* 75521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27370 | /* 75524 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27371 | /* 75527 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27372 | /* 75530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27373 | /* 75534 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27374 | /* 75538 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27375 | /* 75542 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27376 | /* 75546 */ // (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27377 | /* 75546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB), |
| 27378 | /* 75549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27379 | /* 75551 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27380 | /* 75553 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27381 | /* 75555 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27382 | /* 75557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27383 | /* 75560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27384 | /* 75566 */ GIR_RootConstrainSelectedInstOperands, |
| 27385 | /* 75567 */ // GIR_Coverage, 2185, |
| 27386 | /* 75567 */ GIR_EraseRootFromParent_Done, |
| 27387 | /* 75568 */ // Label 2338: @75568 |
| 27388 | /* 75568 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2339*/ GIMT_Encode4(75630), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2186 // |
| 27389 | /* 75575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt), |
| 27390 | /* 75580 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27391 | /* 75583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27392 | /* 75586 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27393 | /* 75589 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27394 | /* 75592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27395 | /* 75596 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27396 | /* 75600 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27397 | /* 75604 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27398 | /* 75608 */ // (intrinsic_wo_chain:{ *:[i32] } 4115:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27399 | /* 75608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 27400 | /* 75611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27401 | /* 75613 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27402 | /* 75615 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27403 | /* 75617 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27404 | /* 75619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27405 | /* 75622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27406 | /* 75628 */ GIR_RootConstrainSelectedInstOperands, |
| 27407 | /* 75629 */ // GIR_Coverage, 2186, |
| 27408 | /* 75629 */ GIR_EraseRootFromParent_Done, |
| 27409 | /* 75630 */ // Label 2339: @75630 |
| 27410 | /* 75630 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2340*/ GIMT_Encode4(75692), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2187 // |
| 27411 | /* 75637 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb), |
| 27412 | /* 75642 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27413 | /* 75645 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27414 | /* 75648 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27415 | /* 75651 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27416 | /* 75654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27417 | /* 75658 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27418 | /* 75662 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27419 | /* 75666 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27420 | /* 75670 */ // (intrinsic_wo_chain:{ *:[i32] } 4120:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27421 | /* 75670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB), |
| 27422 | /* 75673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27423 | /* 75675 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27424 | /* 75677 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27425 | /* 75679 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27426 | /* 75681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27427 | /* 75684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27428 | /* 75690 */ GIR_RootConstrainSelectedInstOperands, |
| 27429 | /* 75691 */ // GIR_Coverage, 2187, |
| 27430 | /* 75691 */ GIR_EraseRootFromParent_Done, |
| 27431 | /* 75692 */ // Label 2340: @75692 |
| 27432 | /* 75692 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2341*/ GIMT_Encode4(75754), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2188 // |
| 27433 | /* 75699 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt), |
| 27434 | /* 75704 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27435 | /* 75707 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27436 | /* 75710 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27437 | /* 75713 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27438 | /* 75716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27439 | /* 75720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27440 | /* 75724 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27441 | /* 75728 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27442 | /* 75732 */ // (intrinsic_wo_chain:{ *:[i32] } 4121:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27443 | /* 75732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), |
| 27444 | /* 75735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27445 | /* 75737 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27446 | /* 75739 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27447 | /* 75741 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27448 | /* 75743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27449 | /* 75746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27450 | /* 75752 */ GIR_RootConstrainSelectedInstOperands, |
| 27451 | /* 75753 */ // GIR_Coverage, 2188, |
| 27452 | /* 75753 */ GIR_EraseRootFromParent_Done, |
| 27453 | /* 75754 */ // Label 2341: @75754 |
| 27454 | /* 75754 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2342*/ GIMT_Encode4(75816), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2189 // |
| 27455 | /* 75761 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb), |
| 27456 | /* 75766 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27457 | /* 75769 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27458 | /* 75772 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27459 | /* 75775 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27460 | /* 75778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27461 | /* 75782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27462 | /* 75786 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27463 | /* 75790 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27464 | /* 75794 */ // (intrinsic_wo_chain:{ *:[i32] } 4122:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27465 | /* 75794 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWB), |
| 27466 | /* 75797 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27467 | /* 75799 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27468 | /* 75801 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27469 | /* 75803 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27470 | /* 75805 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27471 | /* 75808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27472 | /* 75814 */ GIR_RootConstrainSelectedInstOperands, |
| 27473 | /* 75815 */ // GIR_Coverage, 2189, |
| 27474 | /* 75815 */ GIR_EraseRootFromParent_Done, |
| 27475 | /* 75816 */ // Label 2342: @75816 |
| 27476 | /* 75816 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2343*/ GIMT_Encode4(75878), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2190 // |
| 27477 | /* 75823 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt), |
| 27478 | /* 75828 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27479 | /* 75831 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27480 | /* 75834 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27481 | /* 75837 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27482 | /* 75840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27483 | /* 75844 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27484 | /* 75848 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27485 | /* 75852 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27486 | /* 75856 */ // (intrinsic_wo_chain:{ *:[i32] } 4123:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27487 | /* 75856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWT), |
| 27488 | /* 75859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27489 | /* 75861 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27490 | /* 75863 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27491 | /* 75865 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27492 | /* 75867 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27493 | /* 75870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27494 | /* 75876 */ GIR_RootConstrainSelectedInstOperands, |
| 27495 | /* 75877 */ // GIR_Coverage, 2190, |
| 27496 | /* 75877 */ GIR_EraseRootFromParent_Done, |
| 27497 | /* 75878 */ // Label 2343: @75878 |
| 27498 | /* 75878 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2344*/ GIMT_Encode4(75940), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2377 // |
| 27499 | /* 75885 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb), |
| 27500 | /* 75890 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27501 | /* 75893 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27502 | /* 75896 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27503 | /* 75899 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27504 | /* 75902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27505 | /* 75906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27506 | /* 75910 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27507 | /* 75914 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27508 | /* 75918 */ // (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27509 | /* 75918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB), |
| 27510 | /* 75921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27511 | /* 75923 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27512 | /* 75925 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27513 | /* 75927 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27514 | /* 75929 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27515 | /* 75932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27516 | /* 75938 */ GIR_RootConstrainSelectedInstOperands, |
| 27517 | /* 75939 */ // GIR_Coverage, 2377, |
| 27518 | /* 75939 */ GIR_EraseRootFromParent_Done, |
| 27519 | /* 75940 */ // Label 2344: @75940 |
| 27520 | /* 75940 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2345*/ GIMT_Encode4(76002), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2378 // |
| 27521 | /* 75947 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt), |
| 27522 | /* 75952 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27523 | /* 75955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27524 | /* 75958 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27525 | /* 75961 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27526 | /* 75964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27527 | /* 75968 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27528 | /* 75972 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27529 | /* 75976 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27530 | /* 75980 */ // (intrinsic_wo_chain:{ *:[i32] } 4115:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27531 | /* 75980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 27532 | /* 75983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27533 | /* 75985 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27534 | /* 75987 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27535 | /* 75989 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27536 | /* 75991 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27537 | /* 75994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27538 | /* 76000 */ GIR_RootConstrainSelectedInstOperands, |
| 27539 | /* 76001 */ // GIR_Coverage, 2378, |
| 27540 | /* 76001 */ GIR_EraseRootFromParent_Done, |
| 27541 | /* 76002 */ // Label 2345: @76002 |
| 27542 | /* 76002 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2346*/ GIMT_Encode4(76064), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2379 // |
| 27543 | /* 76009 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb), |
| 27544 | /* 76014 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27545 | /* 76017 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27546 | /* 76020 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27547 | /* 76023 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27548 | /* 76026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27549 | /* 76030 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27550 | /* 76034 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27551 | /* 76038 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27552 | /* 76042 */ // (intrinsic_wo_chain:{ *:[i32] } 4120:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27553 | /* 76042 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB), |
| 27554 | /* 76045 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27555 | /* 76047 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27556 | /* 76049 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27557 | /* 76051 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27558 | /* 76053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27559 | /* 76056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27560 | /* 76062 */ GIR_RootConstrainSelectedInstOperands, |
| 27561 | /* 76063 */ // GIR_Coverage, 2379, |
| 27562 | /* 76063 */ GIR_EraseRootFromParent_Done, |
| 27563 | /* 76064 */ // Label 2346: @76064 |
| 27564 | /* 76064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2347*/ GIMT_Encode4(76126), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2380 // |
| 27565 | /* 76071 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt), |
| 27566 | /* 76076 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27567 | /* 76079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27568 | /* 76082 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27569 | /* 76085 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27570 | /* 76088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27571 | /* 76092 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27572 | /* 76096 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27573 | /* 76100 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27574 | /* 76104 */ // (intrinsic_wo_chain:{ *:[i32] } 4121:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27575 | /* 76104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), |
| 27576 | /* 76107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27577 | /* 76109 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27578 | /* 76111 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27579 | /* 76113 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27580 | /* 76115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27581 | /* 76118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27582 | /* 76124 */ GIR_RootConstrainSelectedInstOperands, |
| 27583 | /* 76125 */ // GIR_Coverage, 2380, |
| 27584 | /* 76125 */ GIR_EraseRootFromParent_Done, |
| 27585 | /* 76126 */ // Label 2347: @76126 |
| 27586 | /* 76126 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2348*/ GIMT_Encode4(76188), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2381 // |
| 27587 | /* 76133 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb), |
| 27588 | /* 76138 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27589 | /* 76141 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27590 | /* 76144 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27591 | /* 76147 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27592 | /* 76150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27593 | /* 76154 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27594 | /* 76158 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27595 | /* 76162 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27596 | /* 76166 */ // (intrinsic_wo_chain:{ *:[i32] } 4122:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27597 | /* 76166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWB), |
| 27598 | /* 76169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27599 | /* 76171 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27600 | /* 76173 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27601 | /* 76175 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27602 | /* 76177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27603 | /* 76180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27604 | /* 76186 */ GIR_RootConstrainSelectedInstOperands, |
| 27605 | /* 76187 */ // GIR_Coverage, 2381, |
| 27606 | /* 76187 */ GIR_EraseRootFromParent_Done, |
| 27607 | /* 76188 */ // Label 2348: @76188 |
| 27608 | /* 76188 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2349*/ GIMT_Encode4(76250), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2382 // |
| 27609 | /* 76195 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt), |
| 27610 | /* 76200 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27611 | /* 76203 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27612 | /* 76206 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27613 | /* 76209 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27614 | /* 76212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27615 | /* 76216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27616 | /* 76220 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27617 | /* 76224 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27618 | /* 76228 */ // (intrinsic_wo_chain:{ *:[i32] } 4123:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27619 | /* 76228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWT), |
| 27620 | /* 76231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27621 | /* 76233 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27622 | /* 76235 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27623 | /* 76237 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27624 | /* 76239 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27625 | /* 76242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27626 | /* 76248 */ GIR_RootConstrainSelectedInstOperands, |
| 27627 | /* 76249 */ // GIR_Coverage, 2382, |
| 27628 | /* 76249 */ GIR_EraseRootFromParent_Done, |
| 27629 | /* 76250 */ // Label 2349: @76250 |
| 27630 | /* 76250 */ GIM_Try, /*On fail goto*//*Label 2350*/ GIMT_Encode4(76508), |
| 27631 | /* 76255 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah), |
| 27632 | /* 76260 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 2355*/ GIMT_Encode4(76507), |
| 27633 | /* 76271 */ /*GILLT_v4s16*//*Label 2351*/ GIMT_Encode4(76287), |
| 27634 | /* 76275 */ /*GILLT_v8s16*//*Label 2352*/ GIMT_Encode4(76342), |
| 27635 | /* 76279 */ /*GILLT_v2s32*//*Label 2353*/ GIMT_Encode4(76397), |
| 27636 | /* 76283 */ /*GILLT_v4s32*//*Label 2354*/ GIMT_Encode4(76452), |
| 27637 | /* 76287 */ // Label 2351: @76287 |
| 27638 | /* 76287 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2356*/ GIMT_Encode4(76341), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2856 // |
| 27639 | /* 76294 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 27640 | /* 76297 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 27641 | /* 76300 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 27642 | /* 76303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27643 | /* 76307 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27644 | /* 76311 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27645 | /* 76315 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27646 | /* 76319 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4049:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLAHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 27647 | /* 76319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i16), |
| 27648 | /* 76322 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27649 | /* 76324 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27650 | /* 76326 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27651 | /* 76328 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27652 | /* 76330 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27653 | /* 76333 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27654 | /* 76339 */ GIR_RootConstrainSelectedInstOperands, |
| 27655 | /* 76340 */ // GIR_Coverage, 2856, |
| 27656 | /* 76340 */ GIR_EraseRootFromParent_Done, |
| 27657 | /* 76341 */ // Label 2356: @76341 |
| 27658 | /* 76341 */ GIM_Reject, |
| 27659 | /* 76342 */ // Label 2352: @76342 |
| 27660 | /* 76342 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2357*/ GIMT_Encode4(76396), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2858 // |
| 27661 | /* 76349 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27662 | /* 76352 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27663 | /* 76355 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27664 | /* 76358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27665 | /* 76362 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27666 | /* 76366 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27667 | /* 76370 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27668 | /* 76374 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4049:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLAHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 27669 | /* 76374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv8i16), |
| 27670 | /* 76377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27671 | /* 76379 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27672 | /* 76381 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27673 | /* 76383 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27674 | /* 76385 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27675 | /* 76388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27676 | /* 76394 */ GIR_RootConstrainSelectedInstOperands, |
| 27677 | /* 76395 */ // GIR_Coverage, 2858, |
| 27678 | /* 76395 */ GIR_EraseRootFromParent_Done, |
| 27679 | /* 76396 */ // Label 2357: @76396 |
| 27680 | /* 76396 */ GIM_Reject, |
| 27681 | /* 76397 */ // Label 2353: @76397 |
| 27682 | /* 76397 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2358*/ GIMT_Encode4(76451), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2857 // |
| 27683 | /* 76404 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 27684 | /* 76407 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 27685 | /* 76410 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32, |
| 27686 | /* 76413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27687 | /* 76417 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27688 | /* 76421 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27689 | /* 76425 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27690 | /* 76429 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4049:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLAHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 27691 | /* 76429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv2i32), |
| 27692 | /* 76432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27693 | /* 76434 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27694 | /* 76436 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27695 | /* 76438 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27696 | /* 76440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27697 | /* 76443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27698 | /* 76449 */ GIR_RootConstrainSelectedInstOperands, |
| 27699 | /* 76450 */ // GIR_Coverage, 2857, |
| 27700 | /* 76450 */ GIR_EraseRootFromParent_Done, |
| 27701 | /* 76451 */ // Label 2358: @76451 |
| 27702 | /* 76451 */ GIM_Reject, |
| 27703 | /* 76452 */ // Label 2354: @76452 |
| 27704 | /* 76452 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2359*/ GIMT_Encode4(76506), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2859 // |
| 27705 | /* 76459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27706 | /* 76462 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27707 | /* 76465 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27708 | /* 76468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27709 | /* 76472 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27710 | /* 76476 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27711 | /* 76480 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27712 | /* 76484 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4049:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLAHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 27713 | /* 76484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i32), |
| 27714 | /* 76487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27715 | /* 76489 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27716 | /* 76491 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27717 | /* 76493 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27718 | /* 76495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27719 | /* 76498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27720 | /* 76504 */ GIR_RootConstrainSelectedInstOperands, |
| 27721 | /* 76505 */ // GIR_Coverage, 2859, |
| 27722 | /* 76505 */ GIR_EraseRootFromParent_Done, |
| 27723 | /* 76506 */ // Label 2359: @76506 |
| 27724 | /* 76506 */ GIM_Reject, |
| 27725 | /* 76507 */ // Label 2355: @76507 |
| 27726 | /* 76507 */ GIM_Reject, |
| 27727 | /* 76508 */ // Label 2350: @76508 |
| 27728 | /* 76508 */ GIM_Try, /*On fail goto*//*Label 2360*/ GIMT_Encode4(76766), |
| 27729 | /* 76513 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh), |
| 27730 | /* 76518 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 2365*/ GIMT_Encode4(76765), |
| 27731 | /* 76529 */ /*GILLT_v4s16*//*Label 2361*/ GIMT_Encode4(76545), |
| 27732 | /* 76533 */ /*GILLT_v8s16*//*Label 2362*/ GIMT_Encode4(76600), |
| 27733 | /* 76537 */ /*GILLT_v2s32*//*Label 2363*/ GIMT_Encode4(76655), |
| 27734 | /* 76541 */ /*GILLT_v4s32*//*Label 2364*/ GIMT_Encode4(76710), |
| 27735 | /* 76545 */ // Label 2361: @76545 |
| 27736 | /* 76545 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2366*/ GIMT_Encode4(76599), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2864 // |
| 27737 | /* 76552 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 27738 | /* 76555 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 27739 | /* 76558 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 27740 | /* 76561 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27741 | /* 76565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27742 | /* 76569 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27743 | /* 76573 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27744 | /* 76577 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4050:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLSHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 27745 | /* 76577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i16), |
| 27746 | /* 76580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27747 | /* 76582 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27748 | /* 76584 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27749 | /* 76586 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27750 | /* 76588 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27751 | /* 76591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27752 | /* 76597 */ GIR_RootConstrainSelectedInstOperands, |
| 27753 | /* 76598 */ // GIR_Coverage, 2864, |
| 27754 | /* 76598 */ GIR_EraseRootFromParent_Done, |
| 27755 | /* 76599 */ // Label 2366: @76599 |
| 27756 | /* 76599 */ GIM_Reject, |
| 27757 | /* 76600 */ // Label 2362: @76600 |
| 27758 | /* 76600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2367*/ GIMT_Encode4(76654), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2866 // |
| 27759 | /* 76607 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27760 | /* 76610 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27761 | /* 76613 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27762 | /* 76616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27763 | /* 76620 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27764 | /* 76624 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27765 | /* 76628 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27766 | /* 76632 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4050:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLSHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 27767 | /* 76632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv8i16), |
| 27768 | /* 76635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27769 | /* 76637 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27770 | /* 76639 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27771 | /* 76641 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27772 | /* 76643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27773 | /* 76646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27774 | /* 76652 */ GIR_RootConstrainSelectedInstOperands, |
| 27775 | /* 76653 */ // GIR_Coverage, 2866, |
| 27776 | /* 76653 */ GIR_EraseRootFromParent_Done, |
| 27777 | /* 76654 */ // Label 2367: @76654 |
| 27778 | /* 76654 */ GIM_Reject, |
| 27779 | /* 76655 */ // Label 2363: @76655 |
| 27780 | /* 76655 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2368*/ GIMT_Encode4(76709), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2865 // |
| 27781 | /* 76662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 27782 | /* 76665 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 27783 | /* 76668 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32, |
| 27784 | /* 76671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27785 | /* 76675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27786 | /* 76679 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27787 | /* 76683 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27788 | /* 76687 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4050:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLSHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 27789 | /* 76687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv2i32), |
| 27790 | /* 76690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27791 | /* 76692 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27792 | /* 76694 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27793 | /* 76696 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27794 | /* 76698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27795 | /* 76701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27796 | /* 76707 */ GIR_RootConstrainSelectedInstOperands, |
| 27797 | /* 76708 */ // GIR_Coverage, 2865, |
| 27798 | /* 76708 */ GIR_EraseRootFromParent_Done, |
| 27799 | /* 76709 */ // Label 2368: @76709 |
| 27800 | /* 76709 */ GIM_Reject, |
| 27801 | /* 76710 */ // Label 2364: @76710 |
| 27802 | /* 76710 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2369*/ GIMT_Encode4(76764), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2867 // |
| 27803 | /* 76717 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27804 | /* 76720 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27805 | /* 76723 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27806 | /* 76726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27807 | /* 76730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27808 | /* 76734 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27809 | /* 76738 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27810 | /* 76742 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4050:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLSHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 27811 | /* 76742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i32), |
| 27812 | /* 76745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27813 | /* 76747 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27814 | /* 76749 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27815 | /* 76751 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27816 | /* 76753 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27817 | /* 76756 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27818 | /* 76762 */ GIR_RootConstrainSelectedInstOperands, |
| 27819 | /* 76763 */ // GIR_Coverage, 2867, |
| 27820 | /* 76763 */ GIR_EraseRootFromParent_Done, |
| 27821 | /* 76764 */ // Label 2369: @76764 |
| 27822 | /* 76764 */ GIM_Reject, |
| 27823 | /* 76765 */ // Label 2365: @76765 |
| 27824 | /* 76765 */ GIM_Reject, |
| 27825 | /* 76766 */ // Label 2360: @76766 |
| 27826 | /* 76766 */ GIM_Try, /*On fail goto*//*Label 2370*/ GIMT_Encode4(76922), |
| 27827 | /* 76771 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma), |
| 27828 | /* 76776 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2373*/ GIMT_Encode4(76921), |
| 27829 | /* 76787 */ /*GILLT_v8s16*//*Label 2371*/ GIMT_Encode4(76799), GIMT_Encode4(0), |
| 27830 | /* 76795 */ /*GILLT_v4s32*//*Label 2372*/ GIMT_Encode4(76860), |
| 27831 | /* 76799 */ // Label 2371: @76799 |
| 27832 | /* 76799 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2374*/ GIMT_Encode4(76859), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4446 // |
| 27833 | /* 76806 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27834 | /* 76809 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27835 | /* 76812 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27836 | /* 76815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27837 | /* 76819 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27838 | /* 76823 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27839 | /* 76827 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27840 | /* 76831 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3764:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 27841 | /* 76831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16), |
| 27842 | /* 76834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27843 | /* 76836 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 27844 | /* 76838 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1 |
| 27845 | /* 76840 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2 |
| 27846 | /* 76842 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27847 | /* 76845 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27848 | /* 76851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27849 | /* 76857 */ GIR_RootConstrainSelectedInstOperands, |
| 27850 | /* 76858 */ // GIR_Coverage, 4446, |
| 27851 | /* 76858 */ GIR_EraseRootFromParent_Done, |
| 27852 | /* 76859 */ // Label 2374: @76859 |
| 27853 | /* 76859 */ GIM_Reject, |
| 27854 | /* 76860 */ // Label 2372: @76860 |
| 27855 | /* 76860 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2375*/ GIMT_Encode4(76920), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4442 // |
| 27856 | /* 76867 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27857 | /* 76870 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27858 | /* 76873 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27859 | /* 76876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27860 | /* 76880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27861 | /* 76884 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27862 | /* 76888 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27863 | /* 76892 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3764:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 27864 | /* 76892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32), |
| 27865 | /* 76895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27866 | /* 76897 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 27867 | /* 76899 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1 |
| 27868 | /* 76901 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2 |
| 27869 | /* 76903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27870 | /* 76906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27871 | /* 76912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27872 | /* 76918 */ GIR_RootConstrainSelectedInstOperands, |
| 27873 | /* 76919 */ // GIR_Coverage, 4442, |
| 27874 | /* 76919 */ GIR_EraseRootFromParent_Done, |
| 27875 | /* 76920 */ // Label 2375: @76920 |
| 27876 | /* 76920 */ GIM_Reject, |
| 27877 | /* 76921 */ // Label 2373: @76921 |
| 27878 | /* 76921 */ GIM_Reject, |
| 27879 | /* 76922 */ // Label 2370: @76922 |
| 27880 | /* 76922 */ GIM_Try, /*On fail goto*//*Label 2376*/ GIMT_Encode4(77147), |
| 27881 | /* 76927 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah), |
| 27882 | /* 76932 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2380*/ GIMT_Encode4(77146), |
| 27883 | /* 76943 */ /*GILLT_v16s8*//*Label 2377*/ GIMT_Encode4(76963), GIMT_Encode4(0), |
| 27884 | /* 76951 */ /*GILLT_v8s16*//*Label 2378*/ GIMT_Encode4(77024), GIMT_Encode4(0), |
| 27885 | /* 76959 */ /*GILLT_v4s32*//*Label 2379*/ GIMT_Encode4(77085), |
| 27886 | /* 76963 */ // Label 2377: @76963 |
| 27887 | /* 76963 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2381*/ GIMT_Encode4(77023), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5375 // |
| 27888 | /* 76970 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27889 | /* 76973 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27890 | /* 76976 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27891 | /* 76979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27892 | /* 76983 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27893 | /* 76987 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27894 | /* 76991 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27895 | /* 76995 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3894:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 27896 | /* 76995 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs8), |
| 27897 | /* 76998 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27898 | /* 77000 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 27899 | /* 77002 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 27900 | /* 77004 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 27901 | /* 77006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27902 | /* 77009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27903 | /* 77015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27904 | /* 77021 */ GIR_RootConstrainSelectedInstOperands, |
| 27905 | /* 77022 */ // GIR_Coverage, 5375, |
| 27906 | /* 77022 */ GIR_EraseRootFromParent_Done, |
| 27907 | /* 77023 */ // Label 2381: @77023 |
| 27908 | /* 77023 */ GIM_Reject, |
| 27909 | /* 77024 */ // Label 2378: @77024 |
| 27910 | /* 77024 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2382*/ GIMT_Encode4(77084), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5377 // |
| 27911 | /* 77031 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27912 | /* 77034 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27913 | /* 77037 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27914 | /* 77040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27915 | /* 77044 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27916 | /* 77048 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27917 | /* 77052 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27918 | /* 77056 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3894:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 27919 | /* 77056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs16), |
| 27920 | /* 77059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27921 | /* 77061 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 27922 | /* 77063 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 27923 | /* 77065 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 27924 | /* 77067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27925 | /* 77070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27926 | /* 77076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27927 | /* 77082 */ GIR_RootConstrainSelectedInstOperands, |
| 27928 | /* 77083 */ // GIR_Coverage, 5377, |
| 27929 | /* 77083 */ GIR_EraseRootFromParent_Done, |
| 27930 | /* 77084 */ // Label 2382: @77084 |
| 27931 | /* 77084 */ GIM_Reject, |
| 27932 | /* 77085 */ // Label 2379: @77085 |
| 27933 | /* 77085 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2383*/ GIMT_Encode4(77145), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5379 // |
| 27934 | /* 77092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27935 | /* 77095 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27936 | /* 77098 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27937 | /* 77101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27938 | /* 77105 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27939 | /* 77109 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27940 | /* 77113 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27941 | /* 77117 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3894:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 27942 | /* 77117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs32), |
| 27943 | /* 77120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27944 | /* 77122 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 27945 | /* 77124 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 27946 | /* 77126 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 27947 | /* 77128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27948 | /* 77131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27949 | /* 77137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27950 | /* 77143 */ GIR_RootConstrainSelectedInstOperands, |
| 27951 | /* 77144 */ // GIR_Coverage, 5379, |
| 27952 | /* 77144 */ GIR_EraseRootFromParent_Done, |
| 27953 | /* 77145 */ // Label 2383: @77145 |
| 27954 | /* 77145 */ GIM_Reject, |
| 27955 | /* 77146 */ // Label 2380: @77146 |
| 27956 | /* 77146 */ GIM_Reject, |
| 27957 | /* 77147 */ // Label 2376: @77147 |
| 27958 | /* 77147 */ GIM_Try, /*On fail goto*//*Label 2384*/ GIMT_Encode4(77372), |
| 27959 | /* 77152 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah), |
| 27960 | /* 77157 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2388*/ GIMT_Encode4(77371), |
| 27961 | /* 77168 */ /*GILLT_v16s8*//*Label 2385*/ GIMT_Encode4(77188), GIMT_Encode4(0), |
| 27962 | /* 77176 */ /*GILLT_v8s16*//*Label 2386*/ GIMT_Encode4(77249), GIMT_Encode4(0), |
| 27963 | /* 77184 */ /*GILLT_v4s32*//*Label 2387*/ GIMT_Encode4(77310), |
| 27964 | /* 77188 */ // Label 2385: @77188 |
| 27965 | /* 77188 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2389*/ GIMT_Encode4(77248), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5381 // |
| 27966 | /* 77195 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27967 | /* 77198 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27968 | /* 77201 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27969 | /* 77204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27970 | /* 77208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27971 | /* 77212 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27972 | /* 77216 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27973 | /* 77220 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3903:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 27974 | /* 77220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs8), |
| 27975 | /* 77223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27976 | /* 77225 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 27977 | /* 77227 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 27978 | /* 77229 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 27979 | /* 77231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27980 | /* 77234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27981 | /* 77240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27982 | /* 77246 */ GIR_RootConstrainSelectedInstOperands, |
| 27983 | /* 77247 */ // GIR_Coverage, 5381, |
| 27984 | /* 77247 */ GIR_EraseRootFromParent_Done, |
| 27985 | /* 77248 */ // Label 2389: @77248 |
| 27986 | /* 77248 */ GIM_Reject, |
| 27987 | /* 77249 */ // Label 2386: @77249 |
| 27988 | /* 77249 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2390*/ GIMT_Encode4(77309), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5383 // |
| 27989 | /* 77256 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27990 | /* 77259 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27991 | /* 77262 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27992 | /* 77265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27993 | /* 77269 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27994 | /* 77273 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27995 | /* 77277 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27996 | /* 77281 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3903:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 27997 | /* 77281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs16), |
| 27998 | /* 77284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27999 | /* 77286 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28000 | /* 77288 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28001 | /* 77290 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28002 | /* 77292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28003 | /* 77295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28004 | /* 77301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28005 | /* 77307 */ GIR_RootConstrainSelectedInstOperands, |
| 28006 | /* 77308 */ // GIR_Coverage, 5383, |
| 28007 | /* 77308 */ GIR_EraseRootFromParent_Done, |
| 28008 | /* 77309 */ // Label 2390: @77309 |
| 28009 | /* 77309 */ GIM_Reject, |
| 28010 | /* 77310 */ // Label 2387: @77310 |
| 28011 | /* 77310 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2391*/ GIMT_Encode4(77370), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5385 // |
| 28012 | /* 77317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28013 | /* 77320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28014 | /* 77323 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28015 | /* 77326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28016 | /* 77330 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28017 | /* 77334 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28018 | /* 77338 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28019 | /* 77342 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3903:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28020 | /* 77342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs32), |
| 28021 | /* 77345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28022 | /* 77347 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28023 | /* 77349 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28024 | /* 77351 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28025 | /* 77353 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28026 | /* 77356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28027 | /* 77362 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28028 | /* 77368 */ GIR_RootConstrainSelectedInstOperands, |
| 28029 | /* 77369 */ // GIR_Coverage, 5385, |
| 28030 | /* 77369 */ GIR_EraseRootFromParent_Done, |
| 28031 | /* 77370 */ // Label 2391: @77370 |
| 28032 | /* 77370 */ GIM_Reject, |
| 28033 | /* 77371 */ // Label 2388: @77371 |
| 28034 | /* 77371 */ GIM_Reject, |
| 28035 | /* 77372 */ // Label 2384: @77372 |
| 28036 | /* 77372 */ GIM_Try, /*On fail goto*//*Label 2392*/ GIMT_Encode4(77597), |
| 28037 | /* 77377 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash), |
| 28038 | /* 77382 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2396*/ GIMT_Encode4(77596), |
| 28039 | /* 77393 */ /*GILLT_v16s8*//*Label 2393*/ GIMT_Encode4(77413), GIMT_Encode4(0), |
| 28040 | /* 77401 */ /*GILLT_v8s16*//*Label 2394*/ GIMT_Encode4(77474), GIMT_Encode4(0), |
| 28041 | /* 77409 */ /*GILLT_v4s32*//*Label 2395*/ GIMT_Encode4(77535), |
| 28042 | /* 77413 */ // Label 2393: @77413 |
| 28043 | /* 77413 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2397*/ GIMT_Encode4(77473), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5387 // |
| 28044 | /* 77420 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28045 | /* 77423 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28046 | /* 77426 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28047 | /* 77429 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28048 | /* 77433 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28049 | /* 77437 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28050 | /* 77441 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28051 | /* 77445 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3896:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28052 | /* 77445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs8), |
| 28053 | /* 77448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28054 | /* 77450 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28055 | /* 77452 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28056 | /* 77454 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28057 | /* 77456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28058 | /* 77459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28059 | /* 77465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28060 | /* 77471 */ GIR_RootConstrainSelectedInstOperands, |
| 28061 | /* 77472 */ // GIR_Coverage, 5387, |
| 28062 | /* 77472 */ GIR_EraseRootFromParent_Done, |
| 28063 | /* 77473 */ // Label 2397: @77473 |
| 28064 | /* 77473 */ GIM_Reject, |
| 28065 | /* 77474 */ // Label 2394: @77474 |
| 28066 | /* 77474 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2398*/ GIMT_Encode4(77534), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5389 // |
| 28067 | /* 77481 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28068 | /* 77484 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28069 | /* 77487 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28070 | /* 77490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28071 | /* 77494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28072 | /* 77498 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28073 | /* 77502 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28074 | /* 77506 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3896:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28075 | /* 77506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs16), |
| 28076 | /* 77509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28077 | /* 77511 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28078 | /* 77513 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28079 | /* 77515 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28080 | /* 77517 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28081 | /* 77520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28082 | /* 77526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28083 | /* 77532 */ GIR_RootConstrainSelectedInstOperands, |
| 28084 | /* 77533 */ // GIR_Coverage, 5389, |
| 28085 | /* 77533 */ GIR_EraseRootFromParent_Done, |
| 28086 | /* 77534 */ // Label 2398: @77534 |
| 28087 | /* 77534 */ GIM_Reject, |
| 28088 | /* 77535 */ // Label 2395: @77535 |
| 28089 | /* 77535 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2399*/ GIMT_Encode4(77595), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5391 // |
| 28090 | /* 77542 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28091 | /* 77545 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28092 | /* 77548 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28093 | /* 77551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28094 | /* 77555 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28095 | /* 77559 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28096 | /* 77563 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28097 | /* 77567 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3896:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28098 | /* 77567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs32), |
| 28099 | /* 77570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28100 | /* 77572 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28101 | /* 77574 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28102 | /* 77576 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28103 | /* 77578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28104 | /* 77581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28105 | /* 77587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28106 | /* 77593 */ GIR_RootConstrainSelectedInstOperands, |
| 28107 | /* 77594 */ // GIR_Coverage, 5391, |
| 28108 | /* 77594 */ GIR_EraseRootFromParent_Done, |
| 28109 | /* 77595 */ // Label 2399: @77595 |
| 28110 | /* 77595 */ GIM_Reject, |
| 28111 | /* 77596 */ // Label 2396: @77596 |
| 28112 | /* 77596 */ GIM_Reject, |
| 28113 | /* 77597 */ // Label 2392: @77597 |
| 28114 | /* 77597 */ GIM_Try, /*On fail goto*//*Label 2400*/ GIMT_Encode4(77822), |
| 28115 | /* 77602 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash), |
| 28116 | /* 77607 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2404*/ GIMT_Encode4(77821), |
| 28117 | /* 77618 */ /*GILLT_v16s8*//*Label 2401*/ GIMT_Encode4(77638), GIMT_Encode4(0), |
| 28118 | /* 77626 */ /*GILLT_v8s16*//*Label 2402*/ GIMT_Encode4(77699), GIMT_Encode4(0), |
| 28119 | /* 77634 */ /*GILLT_v4s32*//*Label 2403*/ GIMT_Encode4(77760), |
| 28120 | /* 77638 */ // Label 2401: @77638 |
| 28121 | /* 77638 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2405*/ GIMT_Encode4(77698), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5393 // |
| 28122 | /* 77645 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28123 | /* 77648 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28124 | /* 77651 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28125 | /* 77654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28126 | /* 77658 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28127 | /* 77662 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28128 | /* 77666 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28129 | /* 77670 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3905:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28130 | /* 77670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs8), |
| 28131 | /* 77673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28132 | /* 77675 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28133 | /* 77677 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28134 | /* 77679 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28135 | /* 77681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28136 | /* 77684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28137 | /* 77690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28138 | /* 77696 */ GIR_RootConstrainSelectedInstOperands, |
| 28139 | /* 77697 */ // GIR_Coverage, 5393, |
| 28140 | /* 77697 */ GIR_EraseRootFromParent_Done, |
| 28141 | /* 77698 */ // Label 2405: @77698 |
| 28142 | /* 77698 */ GIM_Reject, |
| 28143 | /* 77699 */ // Label 2402: @77699 |
| 28144 | /* 77699 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2406*/ GIMT_Encode4(77759), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5395 // |
| 28145 | /* 77706 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28146 | /* 77709 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28147 | /* 77712 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28148 | /* 77715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28149 | /* 77719 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28150 | /* 77723 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28151 | /* 77727 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28152 | /* 77731 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3905:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28153 | /* 77731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs16), |
| 28154 | /* 77734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28155 | /* 77736 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28156 | /* 77738 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28157 | /* 77740 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28158 | /* 77742 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28159 | /* 77745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28160 | /* 77751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28161 | /* 77757 */ GIR_RootConstrainSelectedInstOperands, |
| 28162 | /* 77758 */ // GIR_Coverage, 5395, |
| 28163 | /* 77758 */ GIR_EraseRootFromParent_Done, |
| 28164 | /* 77759 */ // Label 2406: @77759 |
| 28165 | /* 77759 */ GIM_Reject, |
| 28166 | /* 77760 */ // Label 2403: @77760 |
| 28167 | /* 77760 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2407*/ GIMT_Encode4(77820), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5397 // |
| 28168 | /* 77767 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28169 | /* 77770 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28170 | /* 77773 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28171 | /* 77776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28172 | /* 77780 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28173 | /* 77784 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28174 | /* 77788 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28175 | /* 77792 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3905:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28176 | /* 77792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs32), |
| 28177 | /* 77795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28178 | /* 77797 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28179 | /* 77799 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28180 | /* 77801 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28181 | /* 77803 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28182 | /* 77806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28183 | /* 77812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28184 | /* 77818 */ GIR_RootConstrainSelectedInstOperands, |
| 28185 | /* 77819 */ // GIR_Coverage, 5397, |
| 28186 | /* 77819 */ GIR_EraseRootFromParent_Done, |
| 28187 | /* 77820 */ // Label 2407: @77820 |
| 28188 | /* 77820 */ GIM_Reject, |
| 28189 | /* 77821 */ // Label 2404: @77821 |
| 28190 | /* 77821 */ GIM_Reject, |
| 28191 | /* 77822 */ // Label 2400: @77822 |
| 28192 | /* 77822 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2408*/ GIMT_Encode4(77935), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3083 // |
| 28193 | /* 77829 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1c), |
| 28194 | /* 77834 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28195 | /* 77837 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28196 | /* 77840 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28197 | /* 77843 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 28198 | /* 77846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28199 | /* 77850 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3966:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1C:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) |
| 28200 | /* 77850 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 28201 | /* 77853 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 28202 | /* 77857 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28203 | /* 77862 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e |
| 28204 | /* 77866 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 28205 | /* 77871 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 28206 | /* 77874 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28207 | /* 77878 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28208 | /* 77883 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 28209 | /* 77885 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 28210 | /* 77888 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28211 | /* 77892 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28212 | /* 77897 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 28213 | /* 77900 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 28214 | /* 77903 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17, |
| 28215 | /* 77906 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 28216 | /* 77911 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 28217 | /* 77916 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 28218 | /* 77921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1C), |
| 28219 | /* 77924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28220 | /* 77926 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd |
| 28221 | /* 77928 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28222 | /* 77931 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk |
| 28223 | /* 77933 */ GIR_RootConstrainSelectedInstOperands, |
| 28224 | /* 77934 */ // GIR_Coverage, 3083, |
| 28225 | /* 77934 */ GIR_EraseRootFromParent_Done, |
| 28226 | /* 77935 */ // Label 2408: @77935 |
| 28227 | /* 77935 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2409*/ GIMT_Encode4(78048), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3084 // |
| 28228 | /* 77942 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1m), |
| 28229 | /* 77947 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28230 | /* 77950 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28231 | /* 77953 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28232 | /* 77956 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 28233 | /* 77959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28234 | /* 77963 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3968:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1M:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) |
| 28235 | /* 77963 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 28236 | /* 77966 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 28237 | /* 77970 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28238 | /* 77975 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e |
| 28239 | /* 77979 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 28240 | /* 77984 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 28241 | /* 77987 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28242 | /* 77991 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28243 | /* 77996 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 28244 | /* 77998 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 28245 | /* 78001 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28246 | /* 78005 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28247 | /* 78010 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 28248 | /* 78013 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 28249 | /* 78016 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17, |
| 28250 | /* 78019 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 28251 | /* 78024 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 28252 | /* 78029 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 28253 | /* 78034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1M), |
| 28254 | /* 78037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28255 | /* 78039 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd |
| 28256 | /* 78041 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28257 | /* 78044 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk |
| 28258 | /* 78046 */ GIR_RootConstrainSelectedInstOperands, |
| 28259 | /* 78047 */ // GIR_Coverage, 3084, |
| 28260 | /* 78047 */ GIR_EraseRootFromParent_Done, |
| 28261 | /* 78048 */ // Label 2409: @78048 |
| 28262 | /* 78048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2410*/ GIMT_Encode4(78161), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3085 // |
| 28263 | /* 78055 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1p), |
| 28264 | /* 78060 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28265 | /* 78063 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28266 | /* 78066 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28267 | /* 78069 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 28268 | /* 78072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28269 | /* 78076 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3969:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1P:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) |
| 28270 | /* 78076 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 28271 | /* 78079 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 28272 | /* 78083 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28273 | /* 78088 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e |
| 28274 | /* 78092 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 28275 | /* 78097 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 28276 | /* 78100 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28277 | /* 78104 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28278 | /* 78109 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 28279 | /* 78111 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 28280 | /* 78114 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28281 | /* 78118 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28282 | /* 78123 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 28283 | /* 78126 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 28284 | /* 78129 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17, |
| 28285 | /* 78132 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 28286 | /* 78137 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 28287 | /* 78142 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 28288 | /* 78147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1P), |
| 28289 | /* 78150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28290 | /* 78152 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd |
| 28291 | /* 78154 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28292 | /* 78157 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk |
| 28293 | /* 78159 */ GIR_RootConstrainSelectedInstOperands, |
| 28294 | /* 78160 */ // GIR_Coverage, 3085, |
| 28295 | /* 78160 */ GIR_EraseRootFromParent_Done, |
| 28296 | /* 78161 */ // Label 2410: @78161 |
| 28297 | /* 78161 */ GIM_Reject, |
| 28298 | /* 78162 */ // Label 2103: @78162 |
| 28299 | /* 78162 */ GIM_Try, /*On fail goto*//*Label 2411*/ GIMT_Encode4(81001), |
| 28300 | /* 78167 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 28301 | /* 78170 */ GIM_Try, /*On fail goto*//*Label 2412*/ GIMT_Encode4(78690), |
| 28302 | /* 78175 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 28303 | /* 78180 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2415*/ GIMT_Encode4(78689), |
| 28304 | /* 78191 */ /*GILLT_v8s16*//*Label 2413*/ GIMT_Encode4(78203), GIMT_Encode4(0), |
| 28305 | /* 78199 */ /*GILLT_v4s32*//*Label 2414*/ GIMT_Encode4(78446), |
| 28306 | /* 78203 */ // Label 2413: @78203 |
| 28307 | /* 78203 */ GIM_Try, /*On fail goto*//*Label 2416*/ GIMT_Encode4(78445), |
| 28308 | /* 78208 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28309 | /* 78211 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28310 | /* 78214 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28311 | /* 78217 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28312 | /* 78220 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28313 | /* 78224 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28314 | /* 78228 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8, |
| 28315 | /* 78232 */ GIM_Try, /*On fail goto*//*Label 2417*/ GIMT_Encode4(78338), |
| 28316 | /* 78237 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28317 | /* 78241 */ GIM_Try, /*On fail goto*//*Label 2418*/ GIMT_Encode4(78289), // Rule ID 4130 // |
| 28318 | /* 78246 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28319 | /* 78250 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3940:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 28320 | /* 78250 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28321 | /* 78253 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28322 | /* 78257 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28323 | /* 78262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8bh), |
| 28324 | /* 78265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28325 | /* 78267 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28326 | /* 78269 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28327 | /* 78272 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28328 | /* 78278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28329 | /* 78284 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28330 | /* 78287 */ GIR_RootConstrainSelectedInstOperands, |
| 28331 | /* 78288 */ // GIR_Coverage, 4130, |
| 28332 | /* 78288 */ GIR_EraseRootFromParent_Done, |
| 28333 | /* 78289 */ // Label 2418: @78289 |
| 28334 | /* 78289 */ GIM_Try, /*On fail goto*//*Label 2419*/ GIMT_Encode4(78337), // Rule ID 4134 // |
| 28335 | /* 78294 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28336 | /* 78298 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3940:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 28337 | /* 78298 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28338 | /* 78301 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28339 | /* 78305 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28340 | /* 78310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8th), |
| 28341 | /* 78313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28342 | /* 78315 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28343 | /* 78317 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28344 | /* 78320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28345 | /* 78326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28346 | /* 78332 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28347 | /* 78335 */ GIR_RootConstrainSelectedInstOperands, |
| 28348 | /* 78336 */ // GIR_Coverage, 4134, |
| 28349 | /* 78336 */ GIR_EraseRootFromParent_Done, |
| 28350 | /* 78337 */ // Label 2419: @78337 |
| 28351 | /* 78337 */ GIM_Reject, |
| 28352 | /* 78338 */ // Label 2417: @78338 |
| 28353 | /* 78338 */ GIM_Try, /*On fail goto*//*Label 2420*/ GIMT_Encode4(78444), |
| 28354 | /* 78343 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28355 | /* 78347 */ GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(78395), // Rule ID 4146 // |
| 28356 | /* 78352 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28357 | /* 78356 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3940:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 28358 | /* 78356 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28359 | /* 78359 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28360 | /* 78363 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28361 | /* 78368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8bh), |
| 28362 | /* 78371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28363 | /* 78373 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28364 | /* 78375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28365 | /* 78378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28366 | /* 78384 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28367 | /* 78390 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28368 | /* 78393 */ GIR_RootConstrainSelectedInstOperands, |
| 28369 | /* 78394 */ // GIR_Coverage, 4146, |
| 28370 | /* 78394 */ GIR_EraseRootFromParent_Done, |
| 28371 | /* 78395 */ // Label 2421: @78395 |
| 28372 | /* 78395 */ GIM_Try, /*On fail goto*//*Label 2422*/ GIMT_Encode4(78443), // Rule ID 4150 // |
| 28373 | /* 78400 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28374 | /* 78404 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3940:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 28375 | /* 78404 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28376 | /* 78407 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28377 | /* 78411 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28378 | /* 78416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8th), |
| 28379 | /* 78419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28380 | /* 78421 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28381 | /* 78423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28382 | /* 78426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28383 | /* 78432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28384 | /* 78438 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28385 | /* 78441 */ GIR_RootConstrainSelectedInstOperands, |
| 28386 | /* 78442 */ // GIR_Coverage, 4150, |
| 28387 | /* 78442 */ GIR_EraseRootFromParent_Done, |
| 28388 | /* 78443 */ // Label 2422: @78443 |
| 28389 | /* 78443 */ GIM_Reject, |
| 28390 | /* 78444 */ // Label 2420: @78444 |
| 28391 | /* 78444 */ GIM_Reject, |
| 28392 | /* 78445 */ // Label 2416: @78445 |
| 28393 | /* 78445 */ GIM_Reject, |
| 28394 | /* 78446 */ // Label 2414: @78446 |
| 28395 | /* 78446 */ GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(78688), |
| 28396 | /* 78451 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28397 | /* 78454 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28398 | /* 78457 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28399 | /* 78460 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28400 | /* 78463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28401 | /* 78467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28402 | /* 78471 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16, |
| 28403 | /* 78475 */ GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(78581), |
| 28404 | /* 78480 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28405 | /* 78484 */ GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(78532), // Rule ID 4138 // |
| 28406 | /* 78489 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28407 | /* 78493 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3940:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 28408 | /* 78493 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28409 | /* 78496 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28410 | /* 78500 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28411 | /* 78505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16bh), |
| 28412 | /* 78508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28413 | /* 78510 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28414 | /* 78512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28415 | /* 78515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28416 | /* 78521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28417 | /* 78527 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28418 | /* 78530 */ GIR_RootConstrainSelectedInstOperands, |
| 28419 | /* 78531 */ // GIR_Coverage, 4138, |
| 28420 | /* 78531 */ GIR_EraseRootFromParent_Done, |
| 28421 | /* 78532 */ // Label 2425: @78532 |
| 28422 | /* 78532 */ GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(78580), // Rule ID 4142 // |
| 28423 | /* 78537 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28424 | /* 78541 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3940:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 28425 | /* 78541 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28426 | /* 78544 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28427 | /* 78548 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28428 | /* 78553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16th), |
| 28429 | /* 78556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28430 | /* 78558 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28431 | /* 78560 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28432 | /* 78563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28433 | /* 78569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28434 | /* 78575 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28435 | /* 78578 */ GIR_RootConstrainSelectedInstOperands, |
| 28436 | /* 78579 */ // GIR_Coverage, 4142, |
| 28437 | /* 78579 */ GIR_EraseRootFromParent_Done, |
| 28438 | /* 78580 */ // Label 2426: @78580 |
| 28439 | /* 78580 */ GIM_Reject, |
| 28440 | /* 78581 */ // Label 2424: @78581 |
| 28441 | /* 78581 */ GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(78687), |
| 28442 | /* 78586 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28443 | /* 78590 */ GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(78638), // Rule ID 4154 // |
| 28444 | /* 78595 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28445 | /* 78599 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3940:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 28446 | /* 78599 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28447 | /* 78602 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28448 | /* 78606 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28449 | /* 78611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16bh), |
| 28450 | /* 78614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28451 | /* 78616 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28452 | /* 78618 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28453 | /* 78621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28454 | /* 78627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28455 | /* 78633 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28456 | /* 78636 */ GIR_RootConstrainSelectedInstOperands, |
| 28457 | /* 78637 */ // GIR_Coverage, 4154, |
| 28458 | /* 78637 */ GIR_EraseRootFromParent_Done, |
| 28459 | /* 78638 */ // Label 2428: @78638 |
| 28460 | /* 78638 */ GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(78686), // Rule ID 4158 // |
| 28461 | /* 78643 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28462 | /* 78647 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3940:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 28463 | /* 78647 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28464 | /* 78650 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28465 | /* 78654 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28466 | /* 78659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16th), |
| 28467 | /* 78662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28468 | /* 78664 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28469 | /* 78666 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28470 | /* 78669 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28471 | /* 78675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28472 | /* 78681 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28473 | /* 78684 */ GIR_RootConstrainSelectedInstOperands, |
| 28474 | /* 78685 */ // GIR_Coverage, 4158, |
| 28475 | /* 78685 */ GIR_EraseRootFromParent_Done, |
| 28476 | /* 78686 */ // Label 2429: @78686 |
| 28477 | /* 78686 */ GIM_Reject, |
| 28478 | /* 78687 */ // Label 2427: @78687 |
| 28479 | /* 78687 */ GIM_Reject, |
| 28480 | /* 78688 */ // Label 2423: @78688 |
| 28481 | /* 78688 */ GIM_Reject, |
| 28482 | /* 78689 */ // Label 2415: @78689 |
| 28483 | /* 78689 */ GIM_Reject, |
| 28484 | /* 78690 */ // Label 2412: @78690 |
| 28485 | /* 78690 */ GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(79505), |
| 28486 | /* 78695 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 28487 | /* 78700 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 2434*/ GIMT_Encode4(79504), |
| 28488 | /* 78711 */ /*GILLT_v8s16*//*Label 2431*/ GIMT_Encode4(78727), GIMT_Encode4(0), |
| 28489 | /* 78719 */ /*GILLT_v4s32*//*Label 2432*/ GIMT_Encode4(78986), |
| 28490 | /* 78723 */ /*GILLT_v2s64*//*Label 2433*/ GIMT_Encode4(79245), |
| 28491 | /* 78727 */ // Label 2431: @78727 |
| 28492 | /* 78727 */ GIM_Try, /*On fail goto*//*Label 2435*/ GIMT_Encode4(78985), |
| 28493 | /* 78732 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28494 | /* 78735 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28495 | /* 78738 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28496 | /* 78741 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28497 | /* 78744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28498 | /* 78748 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28499 | /* 78752 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28500 | /* 78756 */ GIM_Try, /*On fail goto*//*Label 2436*/ GIMT_Encode4(78870), |
| 28501 | /* 78761 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28502 | /* 78765 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2437*/ GIMT_Encode4(78817), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4898 // |
| 28503 | /* 78772 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28504 | /* 78776 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3890:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 28505 | /* 78776 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28506 | /* 78779 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28507 | /* 78783 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28508 | /* 78788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8), |
| 28509 | /* 78791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28510 | /* 78793 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28511 | /* 78795 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28512 | /* 78797 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28513 | /* 78800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28514 | /* 78806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28515 | /* 78812 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28516 | /* 78815 */ GIR_RootConstrainSelectedInstOperands, |
| 28517 | /* 78816 */ // GIR_Coverage, 4898, |
| 28518 | /* 78816 */ GIR_EraseRootFromParent_Done, |
| 28519 | /* 78817 */ // Label 2437: @78817 |
| 28520 | /* 78817 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2438*/ GIMT_Encode4(78869), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4900 // |
| 28521 | /* 78824 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28522 | /* 78828 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3890:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 28523 | /* 78828 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28524 | /* 78831 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28525 | /* 78835 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28526 | /* 78840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs8), |
| 28527 | /* 78843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28528 | /* 78845 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28529 | /* 78847 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28530 | /* 78849 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28531 | /* 78852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28532 | /* 78858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28533 | /* 78864 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28534 | /* 78867 */ GIR_RootConstrainSelectedInstOperands, |
| 28535 | /* 78868 */ // GIR_Coverage, 4900, |
| 28536 | /* 78868 */ GIR_EraseRootFromParent_Done, |
| 28537 | /* 78869 */ // Label 2438: @78869 |
| 28538 | /* 78869 */ GIM_Reject, |
| 28539 | /* 78870 */ // Label 2436: @78870 |
| 28540 | /* 78870 */ GIM_Try, /*On fail goto*//*Label 2439*/ GIMT_Encode4(78984), |
| 28541 | /* 78875 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28542 | /* 78879 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2440*/ GIMT_Encode4(78931), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4910 // |
| 28543 | /* 78886 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28544 | /* 78890 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3890:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 28545 | /* 78890 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28546 | /* 78893 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28547 | /* 78897 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28548 | /* 78902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu8), |
| 28549 | /* 78905 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28550 | /* 78907 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28551 | /* 78909 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28552 | /* 78911 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28553 | /* 78914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28554 | /* 78920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28555 | /* 78926 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28556 | /* 78929 */ GIR_RootConstrainSelectedInstOperands, |
| 28557 | /* 78930 */ // GIR_Coverage, 4910, |
| 28558 | /* 78930 */ GIR_EraseRootFromParent_Done, |
| 28559 | /* 78931 */ // Label 2440: @78931 |
| 28560 | /* 78931 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2441*/ GIMT_Encode4(78983), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4912 // |
| 28561 | /* 78938 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28562 | /* 78942 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3890:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 28563 | /* 78942 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28564 | /* 78945 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28565 | /* 78949 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28566 | /* 78954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu8), |
| 28567 | /* 78957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28568 | /* 78959 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28569 | /* 78961 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28570 | /* 78963 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28571 | /* 78966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28572 | /* 78972 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28573 | /* 78978 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28574 | /* 78981 */ GIR_RootConstrainSelectedInstOperands, |
| 28575 | /* 78982 */ // GIR_Coverage, 4912, |
| 28576 | /* 78982 */ GIR_EraseRootFromParent_Done, |
| 28577 | /* 78983 */ // Label 2441: @78983 |
| 28578 | /* 78983 */ GIM_Reject, |
| 28579 | /* 78984 */ // Label 2439: @78984 |
| 28580 | /* 78984 */ GIM_Reject, |
| 28581 | /* 78985 */ // Label 2435: @78985 |
| 28582 | /* 78985 */ GIM_Reject, |
| 28583 | /* 78986 */ // Label 2432: @78986 |
| 28584 | /* 78986 */ GIM_Try, /*On fail goto*//*Label 2442*/ GIMT_Encode4(79244), |
| 28585 | /* 78991 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28586 | /* 78994 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28587 | /* 78997 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28588 | /* 79000 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28589 | /* 79003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28590 | /* 79007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28591 | /* 79011 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28592 | /* 79015 */ GIM_Try, /*On fail goto*//*Label 2443*/ GIMT_Encode4(79129), |
| 28593 | /* 79020 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28594 | /* 79024 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2444*/ GIMT_Encode4(79076), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4902 // |
| 28595 | /* 79031 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28596 | /* 79035 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3890:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 28597 | /* 79035 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28598 | /* 79038 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28599 | /* 79042 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28600 | /* 79047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16), |
| 28601 | /* 79050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28602 | /* 79052 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28603 | /* 79054 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28604 | /* 79056 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28605 | /* 79059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28606 | /* 79065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28607 | /* 79071 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28608 | /* 79074 */ GIR_RootConstrainSelectedInstOperands, |
| 28609 | /* 79075 */ // GIR_Coverage, 4902, |
| 28610 | /* 79075 */ GIR_EraseRootFromParent_Done, |
| 28611 | /* 79076 */ // Label 2444: @79076 |
| 28612 | /* 79076 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2445*/ GIMT_Encode4(79128), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4904 // |
| 28613 | /* 79083 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28614 | /* 79087 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3890:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 28615 | /* 79087 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28616 | /* 79090 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28617 | /* 79094 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28618 | /* 79099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs16), |
| 28619 | /* 79102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28620 | /* 79104 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28621 | /* 79106 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28622 | /* 79108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28623 | /* 79111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28624 | /* 79117 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28625 | /* 79123 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28626 | /* 79126 */ GIR_RootConstrainSelectedInstOperands, |
| 28627 | /* 79127 */ // GIR_Coverage, 4904, |
| 28628 | /* 79127 */ GIR_EraseRootFromParent_Done, |
| 28629 | /* 79128 */ // Label 2445: @79128 |
| 28630 | /* 79128 */ GIM_Reject, |
| 28631 | /* 79129 */ // Label 2443: @79129 |
| 28632 | /* 79129 */ GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(79243), |
| 28633 | /* 79134 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28634 | /* 79138 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2447*/ GIMT_Encode4(79190), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4914 // |
| 28635 | /* 79145 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28636 | /* 79149 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3890:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 28637 | /* 79149 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28638 | /* 79152 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28639 | /* 79156 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28640 | /* 79161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu16), |
| 28641 | /* 79164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28642 | /* 79166 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28643 | /* 79168 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28644 | /* 79170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28645 | /* 79173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28646 | /* 79179 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28647 | /* 79185 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28648 | /* 79188 */ GIR_RootConstrainSelectedInstOperands, |
| 28649 | /* 79189 */ // GIR_Coverage, 4914, |
| 28650 | /* 79189 */ GIR_EraseRootFromParent_Done, |
| 28651 | /* 79190 */ // Label 2447: @79190 |
| 28652 | /* 79190 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2448*/ GIMT_Encode4(79242), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4916 // |
| 28653 | /* 79197 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28654 | /* 79201 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3890:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 28655 | /* 79201 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28656 | /* 79204 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28657 | /* 79208 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28658 | /* 79213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu16), |
| 28659 | /* 79216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28660 | /* 79218 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28661 | /* 79220 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28662 | /* 79222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28663 | /* 79225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28664 | /* 79231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28665 | /* 79237 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28666 | /* 79240 */ GIR_RootConstrainSelectedInstOperands, |
| 28667 | /* 79241 */ // GIR_Coverage, 4916, |
| 28668 | /* 79241 */ GIR_EraseRootFromParent_Done, |
| 28669 | /* 79242 */ // Label 2448: @79242 |
| 28670 | /* 79242 */ GIM_Reject, |
| 28671 | /* 79243 */ // Label 2446: @79243 |
| 28672 | /* 79243 */ GIM_Reject, |
| 28673 | /* 79244 */ // Label 2442: @79244 |
| 28674 | /* 79244 */ GIM_Reject, |
| 28675 | /* 79245 */ // Label 2433: @79245 |
| 28676 | /* 79245 */ GIM_Try, /*On fail goto*//*Label 2449*/ GIMT_Encode4(79503), |
| 28677 | /* 79250 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28678 | /* 79253 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28679 | /* 79256 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28680 | /* 79259 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28681 | /* 79262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28682 | /* 79266 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28683 | /* 79270 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28684 | /* 79274 */ GIM_Try, /*On fail goto*//*Label 2450*/ GIMT_Encode4(79388), |
| 28685 | /* 79279 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28686 | /* 79283 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2451*/ GIMT_Encode4(79335), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4906 // |
| 28687 | /* 79290 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28688 | /* 79294 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3890:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 28689 | /* 79294 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28690 | /* 79297 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28691 | /* 79301 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28692 | /* 79306 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs32), |
| 28693 | /* 79309 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28694 | /* 79311 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28695 | /* 79313 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28696 | /* 79315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28697 | /* 79318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28698 | /* 79324 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28699 | /* 79330 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28700 | /* 79333 */ GIR_RootConstrainSelectedInstOperands, |
| 28701 | /* 79334 */ // GIR_Coverage, 4906, |
| 28702 | /* 79334 */ GIR_EraseRootFromParent_Done, |
| 28703 | /* 79335 */ // Label 2451: @79335 |
| 28704 | /* 79335 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2452*/ GIMT_Encode4(79387), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4908 // |
| 28705 | /* 79342 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28706 | /* 79346 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3890:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 28707 | /* 79346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28708 | /* 79349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28709 | /* 79353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28710 | /* 79358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs32), |
| 28711 | /* 79361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28712 | /* 79363 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28713 | /* 79365 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28714 | /* 79367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28715 | /* 79370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28716 | /* 79376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28717 | /* 79382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28718 | /* 79385 */ GIR_RootConstrainSelectedInstOperands, |
| 28719 | /* 79386 */ // GIR_Coverage, 4908, |
| 28720 | /* 79386 */ GIR_EraseRootFromParent_Done, |
| 28721 | /* 79387 */ // Label 2452: @79387 |
| 28722 | /* 79387 */ GIM_Reject, |
| 28723 | /* 79388 */ // Label 2450: @79388 |
| 28724 | /* 79388 */ GIM_Try, /*On fail goto*//*Label 2453*/ GIMT_Encode4(79502), |
| 28725 | /* 79393 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28726 | /* 79397 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2454*/ GIMT_Encode4(79449), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4918 // |
| 28727 | /* 79404 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28728 | /* 79408 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3890:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 28729 | /* 79408 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28730 | /* 79411 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28731 | /* 79415 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28732 | /* 79420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu32), |
| 28733 | /* 79423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28734 | /* 79425 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28735 | /* 79427 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28736 | /* 79429 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28737 | /* 79432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28738 | /* 79438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28739 | /* 79444 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28740 | /* 79447 */ GIR_RootConstrainSelectedInstOperands, |
| 28741 | /* 79448 */ // GIR_Coverage, 4918, |
| 28742 | /* 79448 */ GIR_EraseRootFromParent_Done, |
| 28743 | /* 79449 */ // Label 2454: @79449 |
| 28744 | /* 79449 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2455*/ GIMT_Encode4(79501), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4920 // |
| 28745 | /* 79456 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28746 | /* 79460 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3890:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 28747 | /* 79460 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28748 | /* 79463 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28749 | /* 79467 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28750 | /* 79472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu32), |
| 28751 | /* 79475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28752 | /* 79477 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28753 | /* 79479 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28754 | /* 79481 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28755 | /* 79484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28756 | /* 79490 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28757 | /* 79496 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28758 | /* 79499 */ GIR_RootConstrainSelectedInstOperands, |
| 28759 | /* 79500 */ // GIR_Coverage, 4920, |
| 28760 | /* 79500 */ GIR_EraseRootFromParent_Done, |
| 28761 | /* 79501 */ // Label 2455: @79501 |
| 28762 | /* 79501 */ GIM_Reject, |
| 28763 | /* 79502 */ // Label 2453: @79502 |
| 28764 | /* 79502 */ GIM_Reject, |
| 28765 | /* 79503 */ // Label 2449: @79503 |
| 28766 | /* 79503 */ GIM_Reject, |
| 28767 | /* 79504 */ // Label 2434: @79504 |
| 28768 | /* 79504 */ GIM_Reject, |
| 28769 | /* 79505 */ // Label 2430: @79505 |
| 28770 | /* 79505 */ GIM_Try, /*On fail goto*//*Label 2456*/ GIMT_Encode4(80188), |
| 28771 | /* 79510 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 28772 | /* 79515 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2460*/ GIMT_Encode4(80187), |
| 28773 | /* 79526 */ /*GILLT_v16s8*//*Label 2457*/ GIMT_Encode4(79546), GIMT_Encode4(0), |
| 28774 | /* 79534 */ /*GILLT_v8s16*//*Label 2458*/ GIMT_Encode4(79715), GIMT_Encode4(0), |
| 28775 | /* 79542 */ /*GILLT_v4s32*//*Label 2459*/ GIMT_Encode4(79951), |
| 28776 | /* 79546 */ // Label 2457: @79546 |
| 28777 | /* 79546 */ GIM_Try, /*On fail goto*//*Label 2461*/ GIMT_Encode4(79714), |
| 28778 | /* 79551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28779 | /* 79554 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28780 | /* 79557 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 28781 | /* 79560 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 28782 | /* 79563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28783 | /* 79567 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2462*/ GIMT_Encode4(79640), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5052 // |
| 28784 | /* 79574 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 28785 | /* 79578 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28786 | /* 79582 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28787 | /* 79586 */ // MIs[1] Operand 1 |
| 28788 | /* 79586 */ // No operand predicates |
| 28789 | /* 79586 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28790 | /* 79590 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28791 | /* 79594 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28792 | /* 79596 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3828:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VCADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28793 | /* 79596 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28794 | /* 79599 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28795 | /* 79603 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28796 | /* 79608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi8), |
| 28797 | /* 79611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28798 | /* 79613 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 28799 | /* 79615 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 28800 | /* 79617 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 28801 | /* 79620 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28802 | /* 79623 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28803 | /* 79629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28804 | /* 79635 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28805 | /* 79638 */ GIR_RootConstrainSelectedInstOperands, |
| 28806 | /* 79639 */ // GIR_Coverage, 5052, |
| 28807 | /* 79639 */ GIR_EraseRootFromParent_Done, |
| 28808 | /* 79640 */ // Label 2462: @79640 |
| 28809 | /* 79640 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2463*/ GIMT_Encode4(79713), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5058 // |
| 28810 | /* 79647 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 28811 | /* 79651 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28812 | /* 79655 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28813 | /* 79659 */ // MIs[1] Operand 1 |
| 28814 | /* 79659 */ // No operand predicates |
| 28815 | /* 79659 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28816 | /* 79663 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28817 | /* 79667 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28818 | /* 79669 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3828:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VHCADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28819 | /* 79669 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28820 | /* 79672 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28821 | /* 79676 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28822 | /* 79681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs8), |
| 28823 | /* 79684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28824 | /* 79686 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 28825 | /* 79688 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 28826 | /* 79690 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 28827 | /* 79693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28828 | /* 79696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28829 | /* 79702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28830 | /* 79708 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28831 | /* 79711 */ GIR_RootConstrainSelectedInstOperands, |
| 28832 | /* 79712 */ // GIR_Coverage, 5058, |
| 28833 | /* 79712 */ GIR_EraseRootFromParent_Done, |
| 28834 | /* 79713 */ // Label 2463: @79713 |
| 28835 | /* 79713 */ GIM_Reject, |
| 28836 | /* 79714 */ // Label 2461: @79714 |
| 28837 | /* 79714 */ GIM_Reject, |
| 28838 | /* 79715 */ // Label 2458: @79715 |
| 28839 | /* 79715 */ GIM_Try, /*On fail goto*//*Label 2464*/ GIMT_Encode4(79950), |
| 28840 | /* 79720 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28841 | /* 79723 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28842 | /* 79726 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 28843 | /* 79729 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 28844 | /* 79732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28845 | /* 79736 */ GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(79876), |
| 28846 | /* 79741 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 28847 | /* 79745 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28848 | /* 79749 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28849 | /* 79753 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2466*/ GIMT_Encode4(79814), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4483 // |
| 28850 | /* 79760 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28851 | /* 79764 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28852 | /* 79768 */ // MIs[1] Operand 1 |
| 28853 | /* 79768 */ // No operand predicates |
| 28854 | /* 79768 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28855 | /* 79770 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3828:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28856 | /* 79770 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28857 | /* 79773 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28858 | /* 79777 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28859 | /* 79782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf16), |
| 28860 | /* 79785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28861 | /* 79787 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 28862 | /* 79789 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 28863 | /* 79791 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 28864 | /* 79794 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28865 | /* 79797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28866 | /* 79803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28867 | /* 79809 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28868 | /* 79812 */ GIR_RootConstrainSelectedInstOperands, |
| 28869 | /* 79813 */ // GIR_Coverage, 4483, |
| 28870 | /* 79813 */ GIR_EraseRootFromParent_Done, |
| 28871 | /* 79814 */ // Label 2466: @79814 |
| 28872 | /* 79814 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2467*/ GIMT_Encode4(79875), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5054 // |
| 28873 | /* 79821 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28874 | /* 79825 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28875 | /* 79829 */ // MIs[1] Operand 1 |
| 28876 | /* 79829 */ // No operand predicates |
| 28877 | /* 79829 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28878 | /* 79831 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3828:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VCADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28879 | /* 79831 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28880 | /* 79834 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28881 | /* 79838 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28882 | /* 79843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi16), |
| 28883 | /* 79846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28884 | /* 79848 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 28885 | /* 79850 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 28886 | /* 79852 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 28887 | /* 79855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28888 | /* 79858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28889 | /* 79864 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28890 | /* 79870 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28891 | /* 79873 */ GIR_RootConstrainSelectedInstOperands, |
| 28892 | /* 79874 */ // GIR_Coverage, 5054, |
| 28893 | /* 79874 */ GIR_EraseRootFromParent_Done, |
| 28894 | /* 79875 */ // Label 2467: @79875 |
| 28895 | /* 79875 */ GIM_Reject, |
| 28896 | /* 79876 */ // Label 2465: @79876 |
| 28897 | /* 79876 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2468*/ GIMT_Encode4(79949), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5060 // |
| 28898 | /* 79883 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 28899 | /* 79887 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28900 | /* 79891 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28901 | /* 79895 */ // MIs[1] Operand 1 |
| 28902 | /* 79895 */ // No operand predicates |
| 28903 | /* 79895 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28904 | /* 79899 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28905 | /* 79903 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28906 | /* 79905 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3828:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VHCADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28907 | /* 79905 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28908 | /* 79908 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28909 | /* 79912 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28910 | /* 79917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs16), |
| 28911 | /* 79920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28912 | /* 79922 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 28913 | /* 79924 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 28914 | /* 79926 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 28915 | /* 79929 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28916 | /* 79932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28917 | /* 79938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28918 | /* 79944 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28919 | /* 79947 */ GIR_RootConstrainSelectedInstOperands, |
| 28920 | /* 79948 */ // GIR_Coverage, 5060, |
| 28921 | /* 79948 */ GIR_EraseRootFromParent_Done, |
| 28922 | /* 79949 */ // Label 2468: @79949 |
| 28923 | /* 79949 */ GIM_Reject, |
| 28924 | /* 79950 */ // Label 2464: @79950 |
| 28925 | /* 79950 */ GIM_Reject, |
| 28926 | /* 79951 */ // Label 2459: @79951 |
| 28927 | /* 79951 */ GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(80186), |
| 28928 | /* 79956 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28929 | /* 79959 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28930 | /* 79962 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 28931 | /* 79965 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 28932 | /* 79968 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28933 | /* 79972 */ GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(80112), |
| 28934 | /* 79977 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 28935 | /* 79981 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28936 | /* 79985 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28937 | /* 79989 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2471*/ GIMT_Encode4(80050), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4485 // |
| 28938 | /* 79996 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28939 | /* 80000 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28940 | /* 80004 */ // MIs[1] Operand 1 |
| 28941 | /* 80004 */ // No operand predicates |
| 28942 | /* 80004 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28943 | /* 80006 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3828:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28944 | /* 80006 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28945 | /* 80009 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28946 | /* 80013 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28947 | /* 80018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf32), |
| 28948 | /* 80021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28949 | /* 80023 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 28950 | /* 80025 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 28951 | /* 80027 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 28952 | /* 80030 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28953 | /* 80033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28954 | /* 80039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28955 | /* 80045 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28956 | /* 80048 */ GIR_RootConstrainSelectedInstOperands, |
| 28957 | /* 80049 */ // GIR_Coverage, 4485, |
| 28958 | /* 80049 */ GIR_EraseRootFromParent_Done, |
| 28959 | /* 80050 */ // Label 2471: @80050 |
| 28960 | /* 80050 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2472*/ GIMT_Encode4(80111), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5056 // |
| 28961 | /* 80057 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28962 | /* 80061 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28963 | /* 80065 */ // MIs[1] Operand 1 |
| 28964 | /* 80065 */ // No operand predicates |
| 28965 | /* 80065 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28966 | /* 80067 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3828:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VCADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28967 | /* 80067 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28968 | /* 80070 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28969 | /* 80074 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28970 | /* 80079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi32), |
| 28971 | /* 80082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28972 | /* 80084 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 28973 | /* 80086 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 28974 | /* 80088 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 28975 | /* 80091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28976 | /* 80094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28977 | /* 80100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28978 | /* 80106 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28979 | /* 80109 */ GIR_RootConstrainSelectedInstOperands, |
| 28980 | /* 80110 */ // GIR_Coverage, 5056, |
| 28981 | /* 80110 */ GIR_EraseRootFromParent_Done, |
| 28982 | /* 80111 */ // Label 2472: @80111 |
| 28983 | /* 80111 */ GIM_Reject, |
| 28984 | /* 80112 */ // Label 2470: @80112 |
| 28985 | /* 80112 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2473*/ GIMT_Encode4(80185), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5062 // |
| 28986 | /* 80119 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 28987 | /* 80123 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28988 | /* 80127 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28989 | /* 80131 */ // MIs[1] Operand 1 |
| 28990 | /* 80131 */ // No operand predicates |
| 28991 | /* 80131 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28992 | /* 80135 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28993 | /* 80139 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28994 | /* 80141 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3828:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VHCADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28995 | /* 80141 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28996 | /* 80144 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28997 | /* 80148 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28998 | /* 80153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs32), |
| 28999 | /* 80156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29000 | /* 80158 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29001 | /* 80160 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29002 | /* 80162 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 29003 | /* 80165 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29004 | /* 80168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29005 | /* 80174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29006 | /* 80180 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29007 | /* 80183 */ GIR_RootConstrainSelectedInstOperands, |
| 29008 | /* 80184 */ // GIR_Coverage, 5062, |
| 29009 | /* 80184 */ GIR_EraseRootFromParent_Done, |
| 29010 | /* 80185 */ // Label 2473: @80185 |
| 29011 | /* 80185 */ GIM_Reject, |
| 29012 | /* 80186 */ // Label 2469: @80186 |
| 29013 | /* 80186 */ GIM_Reject, |
| 29014 | /* 80187 */ // Label 2460: @80187 |
| 29015 | /* 80187 */ GIM_Reject, |
| 29016 | /* 80188 */ // Label 2456: @80188 |
| 29017 | /* 80188 */ GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(80587), |
| 29018 | /* 80193 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 29019 | /* 80198 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 29020 | /* 80201 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29021 | /* 80204 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 29022 | /* 80207 */ GIM_SwitchType, /*MI*/0, /*Op*/4, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2478*/ GIMT_Encode4(80586), |
| 29023 | /* 80218 */ /*GILLT_v16s8*//*Label 2475*/ GIMT_Encode4(80238), GIMT_Encode4(0), |
| 29024 | /* 80226 */ /*GILLT_v8s16*//*Label 2476*/ GIMT_Encode4(80354), GIMT_Encode4(0), |
| 29025 | /* 80234 */ /*GILLT_v4s32*//*Label 2477*/ GIMT_Encode4(80470), |
| 29026 | /* 80238 */ // Label 2475: @80238 |
| 29027 | /* 80238 */ GIM_Try, /*On fail goto*//*Label 2479*/ GIMT_Encode4(80353), |
| 29028 | /* 80243 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 29029 | /* 80246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29030 | /* 80250 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2480*/ GIMT_Encode4(80301), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3428 // |
| 29031 | /* 80257 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29032 | /* 80261 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29033 | /* 80265 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29034 | /* 80269 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29035 | /* 80273 */ // (intrinsic_wo_chain:{ *:[i32] } 3820:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29036 | /* 80273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs8), |
| 29037 | /* 80276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 29038 | /* 80278 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 29039 | /* 80280 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29040 | /* 80282 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29041 | /* 80284 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29042 | /* 80287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29043 | /* 80293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29044 | /* 80299 */ GIR_RootConstrainSelectedInstOperands, |
| 29045 | /* 80300 */ // GIR_Coverage, 3428, |
| 29046 | /* 80300 */ GIR_EraseRootFromParent_Done, |
| 29047 | /* 80301 */ // Label 2480: @80301 |
| 29048 | /* 80301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2481*/ GIMT_Encode4(80352), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3434 // |
| 29049 | /* 80308 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29050 | /* 80312 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29051 | /* 80316 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29052 | /* 80320 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29053 | /* 80324 */ // (intrinsic_wo_chain:{ *:[i32] } 3820:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVu8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29054 | /* 80324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu8), |
| 29055 | /* 80327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 29056 | /* 80329 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 29057 | /* 80331 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29058 | /* 80333 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29059 | /* 80335 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29060 | /* 80338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29061 | /* 80344 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29062 | /* 80350 */ GIR_RootConstrainSelectedInstOperands, |
| 29063 | /* 80351 */ // GIR_Coverage, 3434, |
| 29064 | /* 80351 */ GIR_EraseRootFromParent_Done, |
| 29065 | /* 80352 */ // Label 2481: @80352 |
| 29066 | /* 80352 */ GIM_Reject, |
| 29067 | /* 80353 */ // Label 2479: @80353 |
| 29068 | /* 80353 */ GIM_Reject, |
| 29069 | /* 80354 */ // Label 2476: @80354 |
| 29070 | /* 80354 */ GIM_Try, /*On fail goto*//*Label 2482*/ GIMT_Encode4(80469), |
| 29071 | /* 80359 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 29072 | /* 80362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29073 | /* 80366 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2483*/ GIMT_Encode4(80417), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3430 // |
| 29074 | /* 80373 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29075 | /* 80377 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29076 | /* 80381 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29077 | /* 80385 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29078 | /* 80389 */ // (intrinsic_wo_chain:{ *:[i32] } 3820:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29079 | /* 80389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs16), |
| 29080 | /* 80392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 29081 | /* 80394 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 29082 | /* 80396 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29083 | /* 80398 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29084 | /* 80400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29085 | /* 80403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29086 | /* 80409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29087 | /* 80415 */ GIR_RootConstrainSelectedInstOperands, |
| 29088 | /* 80416 */ // GIR_Coverage, 3430, |
| 29089 | /* 80416 */ GIR_EraseRootFromParent_Done, |
| 29090 | /* 80417 */ // Label 2483: @80417 |
| 29091 | /* 80417 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2484*/ GIMT_Encode4(80468), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3436 // |
| 29092 | /* 80424 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29093 | /* 80428 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29094 | /* 80432 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29095 | /* 80436 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29096 | /* 80440 */ // (intrinsic_wo_chain:{ *:[i32] } 3820:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVu16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29097 | /* 80440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu16), |
| 29098 | /* 80443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 29099 | /* 80445 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 29100 | /* 80447 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29101 | /* 80449 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29102 | /* 80451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29103 | /* 80454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29104 | /* 80460 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29105 | /* 80466 */ GIR_RootConstrainSelectedInstOperands, |
| 29106 | /* 80467 */ // GIR_Coverage, 3436, |
| 29107 | /* 80467 */ GIR_EraseRootFromParent_Done, |
| 29108 | /* 80468 */ // Label 2484: @80468 |
| 29109 | /* 80468 */ GIM_Reject, |
| 29110 | /* 80469 */ // Label 2482: @80469 |
| 29111 | /* 80469 */ GIM_Reject, |
| 29112 | /* 80470 */ // Label 2477: @80470 |
| 29113 | /* 80470 */ GIM_Try, /*On fail goto*//*Label 2485*/ GIMT_Encode4(80585), |
| 29114 | /* 80475 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 29115 | /* 80478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29116 | /* 80482 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2486*/ GIMT_Encode4(80533), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3432 // |
| 29117 | /* 80489 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29118 | /* 80493 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29119 | /* 80497 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29120 | /* 80501 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29121 | /* 80505 */ // (intrinsic_wo_chain:{ *:[i32] } 3820:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29122 | /* 80505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs32), |
| 29123 | /* 80508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 29124 | /* 80510 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 29125 | /* 80512 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29126 | /* 80514 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29127 | /* 80516 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29128 | /* 80519 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29129 | /* 80525 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29130 | /* 80531 */ GIR_RootConstrainSelectedInstOperands, |
| 29131 | /* 80532 */ // GIR_Coverage, 3432, |
| 29132 | /* 80532 */ GIR_EraseRootFromParent_Done, |
| 29133 | /* 80533 */ // Label 2486: @80533 |
| 29134 | /* 80533 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2487*/ GIMT_Encode4(80584), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3438 // |
| 29135 | /* 80540 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29136 | /* 80544 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29137 | /* 80548 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29138 | /* 80552 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29139 | /* 80556 */ // (intrinsic_wo_chain:{ *:[i32] } 3820:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVu32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29140 | /* 80556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu32), |
| 29141 | /* 80559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 29142 | /* 80561 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 29143 | /* 80563 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29144 | /* 80565 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29145 | /* 80567 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29146 | /* 80570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29147 | /* 80576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29148 | /* 80582 */ GIR_RootConstrainSelectedInstOperands, |
| 29149 | /* 80583 */ // GIR_Coverage, 3438, |
| 29150 | /* 80583 */ GIR_EraseRootFromParent_Done, |
| 29151 | /* 80584 */ // Label 2487: @80584 |
| 29152 | /* 80584 */ GIM_Reject, |
| 29153 | /* 80585 */ // Label 2485: @80585 |
| 29154 | /* 80585 */ GIM_Reject, |
| 29155 | /* 80586 */ // Label 2478: @80586 |
| 29156 | /* 80586 */ GIM_Reject, |
| 29157 | /* 80587 */ // Label 2474: @80587 |
| 29158 | /* 80587 */ GIM_Try, /*On fail goto*//*Label 2488*/ GIMT_Encode4(80775), |
| 29159 | /* 80592 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq), |
| 29160 | /* 80597 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2491*/ GIMT_Encode4(80774), |
| 29161 | /* 80608 */ /*GILLT_v8s16*//*Label 2489*/ GIMT_Encode4(80620), GIMT_Encode4(0), |
| 29162 | /* 80616 */ /*GILLT_v4s32*//*Label 2490*/ GIMT_Encode4(80697), |
| 29163 | /* 80620 */ // Label 2489: @80620 |
| 29164 | /* 80620 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2492*/ GIMT_Encode4(80696), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4429 // |
| 29165 | /* 80627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29166 | /* 80630 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 29167 | /* 80633 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 29168 | /* 80636 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 29169 | /* 80639 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29170 | /* 80643 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 29171 | /* 80647 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 29172 | /* 80651 */ // MIs[1] Operand 1 |
| 29173 | /* 80651 */ // No operand predicates |
| 29174 | /* 80651 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29175 | /* 80655 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29176 | /* 80659 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29177 | /* 80663 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 29178 | /* 80665 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3831:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 29179 | /* 80665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf16), |
| 29180 | /* 80668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29181 | /* 80670 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src |
| 29182 | /* 80672 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29183 | /* 80674 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29184 | /* 80676 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 29185 | /* 80679 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29186 | /* 80682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29187 | /* 80688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29188 | /* 80694 */ GIR_RootConstrainSelectedInstOperands, |
| 29189 | /* 80695 */ // GIR_Coverage, 4429, |
| 29190 | /* 80695 */ GIR_EraseRootFromParent_Done, |
| 29191 | /* 80696 */ // Label 2492: @80696 |
| 29192 | /* 80696 */ GIM_Reject, |
| 29193 | /* 80697 */ // Label 2490: @80697 |
| 29194 | /* 80697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2493*/ GIMT_Encode4(80773), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4432 // |
| 29195 | /* 80704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29196 | /* 80707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 29197 | /* 80710 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 29198 | /* 80713 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 29199 | /* 80716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29200 | /* 80720 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 29201 | /* 80724 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 29202 | /* 80728 */ // MIs[1] Operand 1 |
| 29203 | /* 80728 */ // No operand predicates |
| 29204 | /* 80728 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29205 | /* 80732 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29206 | /* 80736 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29207 | /* 80740 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 29208 | /* 80742 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3831:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 29209 | /* 80742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf32), |
| 29210 | /* 80745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29211 | /* 80747 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src |
| 29212 | /* 80749 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29213 | /* 80751 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29214 | /* 80753 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 29215 | /* 80756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29216 | /* 80759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29217 | /* 80765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29218 | /* 80771 */ GIR_RootConstrainSelectedInstOperands, |
| 29219 | /* 80772 */ // GIR_Coverage, 4432, |
| 29220 | /* 80772 */ GIR_EraseRootFromParent_Done, |
| 29221 | /* 80773 */ // Label 2493: @80773 |
| 29222 | /* 80773 */ GIM_Reject, |
| 29223 | /* 80774 */ // Label 2491: @80774 |
| 29224 | /* 80774 */ GIM_Reject, |
| 29225 | /* 80775 */ // Label 2488: @80775 |
| 29226 | /* 80775 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2494*/ GIMT_Encode4(80870), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3077 // |
| 29227 | /* 80782 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx2), |
| 29228 | /* 80787 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 29229 | /* 80790 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 29230 | /* 80793 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 29231 | /* 80796 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 29232 | /* 80799 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 29233 | /* 80802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 29234 | /* 80806 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4092:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vm) => (VTBX2:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v16i8] } DPair:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 29235 | /* 80806 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 29236 | /* 80809 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 29237 | /* 80813 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29238 | /* 80818 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 |
| 29239 | /* 80822 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 29240 | /* 80825 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 |
| 29241 | /* 80829 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 29242 | /* 80832 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 29243 | /* 80837 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 29244 | /* 80842 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 29245 | /* 80847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX2), |
| 29246 | /* 80850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 29247 | /* 80852 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 29248 | /* 80854 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29249 | /* 80857 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm |
| 29250 | /* 80859 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 29251 | /* 80862 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29252 | /* 80868 */ GIR_RootConstrainSelectedInstOperands, |
| 29253 | /* 80869 */ // GIR_Coverage, 3077, |
| 29254 | /* 80869 */ GIR_EraseRootFromParent_Done, |
| 29255 | /* 80870 */ // Label 2494: @80870 |
| 29256 | /* 80870 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2495*/ GIMT_Encode4(81000), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3078 // |
| 29257 | /* 80877 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl3), |
| 29258 | /* 80882 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 29259 | /* 80885 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 29260 | /* 80888 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 29261 | /* 80891 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 29262 | /* 80894 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 29263 | /* 80897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 29264 | /* 80901 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4089:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBL3Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 29265 | /* 80901 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8, |
| 29266 | /* 80904 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29267 | /* 80908 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29268 | /* 80913 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 29269 | /* 80915 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 29270 | /* 80918 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 29271 | /* 80922 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29272 | /* 80927 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0 |
| 29273 | /* 80931 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 29274 | /* 80934 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1 |
| 29275 | /* 80938 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 29276 | /* 80941 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2 |
| 29277 | /* 80945 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 29278 | /* 80948 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 29279 | /* 80951 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 29280 | /* 80954 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 29281 | /* 80959 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 29282 | /* 80964 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 29283 | /* 80969 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 29284 | /* 80974 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 29285 | /* 80979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL3Pseudo), |
| 29286 | /* 80982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 29287 | /* 80984 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29288 | /* 80987 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm |
| 29289 | /* 80989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 29290 | /* 80992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29291 | /* 80998 */ GIR_RootConstrainSelectedInstOperands, |
| 29292 | /* 80999 */ // GIR_Coverage, 3078, |
| 29293 | /* 80999 */ GIR_EraseRootFromParent_Done, |
| 29294 | /* 81000 */ // Label 2495: @81000 |
| 29295 | /* 81000 */ GIM_Reject, |
| 29296 | /* 81001 */ // Label 2411: @81001 |
| 29297 | /* 81001 */ GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(84557), |
| 29298 | /* 81006 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, |
| 29299 | /* 81009 */ GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(82527), |
| 29300 | /* 81014 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 29301 | /* 81019 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2501*/ GIMT_Encode4(82526), |
| 29302 | /* 81030 */ /*GILLT_v16s8*//*Label 2498*/ GIMT_Encode4(81050), GIMT_Encode4(0), |
| 29303 | /* 81038 */ /*GILLT_v8s16*//*Label 2499*/ GIMT_Encode4(81542), GIMT_Encode4(0), |
| 29304 | /* 81046 */ /*GILLT_v4s32*//*Label 2500*/ GIMT_Encode4(82034), |
| 29305 | /* 81050 */ // Label 2498: @81050 |
| 29306 | /* 81050 */ GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(81541), |
| 29307 | /* 81055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29308 | /* 81058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 29309 | /* 81061 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29310 | /* 81064 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29311 | /* 81067 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29312 | /* 81070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29313 | /* 81074 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29314 | /* 81078 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29315 | /* 81082 */ GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(81196), |
| 29316 | /* 81087 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29317 | /* 81091 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29318 | /* 81095 */ GIM_Try, /*On fail goto*//*Label 2504*/ GIMT_Encode4(81145), // Rule ID 4241 // |
| 29319 | /* 81100 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29320 | /* 81104 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3936:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29321 | /* 81104 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29322 | /* 81107 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29323 | /* 81111 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29324 | /* 81116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs8), |
| 29325 | /* 81119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29326 | /* 81121 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29327 | /* 81123 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29328 | /* 81125 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29329 | /* 81128 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29330 | /* 81134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29331 | /* 81140 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29332 | /* 81143 */ GIR_RootConstrainSelectedInstOperands, |
| 29333 | /* 81144 */ // GIR_Coverage, 4241, |
| 29334 | /* 81144 */ GIR_EraseRootFromParent_Done, |
| 29335 | /* 81145 */ // Label 2504: @81145 |
| 29336 | /* 81145 */ GIM_Try, /*On fail goto*//*Label 2505*/ GIMT_Encode4(81195), // Rule ID 4247 // |
| 29337 | /* 81150 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29338 | /* 81154 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3936:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29339 | /* 81154 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29340 | /* 81157 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29341 | /* 81161 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29342 | /* 81166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu8), |
| 29343 | /* 81169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29344 | /* 81171 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29345 | /* 81173 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29346 | /* 81175 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29347 | /* 81178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29348 | /* 81184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29349 | /* 81190 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29350 | /* 81193 */ GIR_RootConstrainSelectedInstOperands, |
| 29351 | /* 81194 */ // GIR_Coverage, 4247, |
| 29352 | /* 81194 */ GIR_EraseRootFromParent_Done, |
| 29353 | /* 81195 */ // Label 2505: @81195 |
| 29354 | /* 81195 */ GIM_Reject, |
| 29355 | /* 81196 */ // Label 2503: @81196 |
| 29356 | /* 81196 */ GIM_Try, /*On fail goto*//*Label 2506*/ GIMT_Encode4(81426), |
| 29357 | /* 81201 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29358 | /* 81205 */ GIM_Try, /*On fail goto*//*Label 2507*/ GIMT_Encode4(81315), |
| 29359 | /* 81210 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29360 | /* 81214 */ GIM_Try, /*On fail goto*//*Label 2508*/ GIMT_Encode4(81264), // Rule ID 4253 // |
| 29361 | /* 81219 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29362 | /* 81223 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3936:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29363 | /* 81223 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29364 | /* 81226 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29365 | /* 81230 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29366 | /* 81235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs8), |
| 29367 | /* 81238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29368 | /* 81240 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29369 | /* 81242 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29370 | /* 81244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29371 | /* 81247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29372 | /* 81253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29373 | /* 81259 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29374 | /* 81262 */ GIR_RootConstrainSelectedInstOperands, |
| 29375 | /* 81263 */ // GIR_Coverage, 4253, |
| 29376 | /* 81263 */ GIR_EraseRootFromParent_Done, |
| 29377 | /* 81264 */ // Label 2508: @81264 |
| 29378 | /* 81264 */ GIM_Try, /*On fail goto*//*Label 2509*/ GIMT_Encode4(81314), // Rule ID 4259 // |
| 29379 | /* 81269 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29380 | /* 81273 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3936:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29381 | /* 81273 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29382 | /* 81276 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29383 | /* 81280 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29384 | /* 81285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu8), |
| 29385 | /* 81288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29386 | /* 81290 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29387 | /* 81292 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29388 | /* 81294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29389 | /* 81297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29390 | /* 81303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29391 | /* 81309 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29392 | /* 81312 */ GIR_RootConstrainSelectedInstOperands, |
| 29393 | /* 81313 */ // GIR_Coverage, 4259, |
| 29394 | /* 81313 */ GIR_EraseRootFromParent_Done, |
| 29395 | /* 81314 */ // Label 2509: @81314 |
| 29396 | /* 81314 */ GIM_Reject, |
| 29397 | /* 81315 */ // Label 2507: @81315 |
| 29398 | /* 81315 */ GIM_Try, /*On fail goto*//*Label 2510*/ GIMT_Encode4(81425), |
| 29399 | /* 81320 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29400 | /* 81324 */ GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(81374), // Rule ID 4265 // |
| 29401 | /* 81329 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29402 | /* 81333 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3936:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29403 | /* 81333 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29404 | /* 81336 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29405 | /* 81340 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29406 | /* 81345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs8), |
| 29407 | /* 81348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29408 | /* 81350 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29409 | /* 81352 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29410 | /* 81354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29411 | /* 81357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29412 | /* 81363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29413 | /* 81369 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29414 | /* 81372 */ GIR_RootConstrainSelectedInstOperands, |
| 29415 | /* 81373 */ // GIR_Coverage, 4265, |
| 29416 | /* 81373 */ GIR_EraseRootFromParent_Done, |
| 29417 | /* 81374 */ // Label 2511: @81374 |
| 29418 | /* 81374 */ GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(81424), // Rule ID 4271 // |
| 29419 | /* 81379 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29420 | /* 81383 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3936:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29421 | /* 81383 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29422 | /* 81386 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29423 | /* 81390 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29424 | /* 81395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu8), |
| 29425 | /* 81398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29426 | /* 81400 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29427 | /* 81402 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29428 | /* 81404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29429 | /* 81407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29430 | /* 81413 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29431 | /* 81419 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29432 | /* 81422 */ GIR_RootConstrainSelectedInstOperands, |
| 29433 | /* 81423 */ // GIR_Coverage, 4271, |
| 29434 | /* 81423 */ GIR_EraseRootFromParent_Done, |
| 29435 | /* 81424 */ // Label 2512: @81424 |
| 29436 | /* 81424 */ GIM_Reject, |
| 29437 | /* 81425 */ // Label 2510: @81425 |
| 29438 | /* 81425 */ GIM_Reject, |
| 29439 | /* 81426 */ // Label 2506: @81426 |
| 29440 | /* 81426 */ GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(81540), |
| 29441 | /* 81431 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29442 | /* 81435 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29443 | /* 81439 */ GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(81489), // Rule ID 4277 // |
| 29444 | /* 81444 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29445 | /* 81448 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3936:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29446 | /* 81448 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29447 | /* 81451 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29448 | /* 81455 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29449 | /* 81460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs8), |
| 29450 | /* 81463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29451 | /* 81465 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29452 | /* 81467 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29453 | /* 81469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29454 | /* 81472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29455 | /* 81478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29456 | /* 81484 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29457 | /* 81487 */ GIR_RootConstrainSelectedInstOperands, |
| 29458 | /* 81488 */ // GIR_Coverage, 4277, |
| 29459 | /* 81488 */ GIR_EraseRootFromParent_Done, |
| 29460 | /* 81489 */ // Label 2514: @81489 |
| 29461 | /* 81489 */ GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(81539), // Rule ID 4283 // |
| 29462 | /* 81494 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29463 | /* 81498 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3936:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29464 | /* 81498 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29465 | /* 81501 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29466 | /* 81505 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29467 | /* 81510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu8), |
| 29468 | /* 81513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29469 | /* 81515 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29470 | /* 81517 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29471 | /* 81519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29472 | /* 81522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29473 | /* 81528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29474 | /* 81534 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29475 | /* 81537 */ GIR_RootConstrainSelectedInstOperands, |
| 29476 | /* 81538 */ // GIR_Coverage, 4283, |
| 29477 | /* 81538 */ GIR_EraseRootFromParent_Done, |
| 29478 | /* 81539 */ // Label 2515: @81539 |
| 29479 | /* 81539 */ GIM_Reject, |
| 29480 | /* 81540 */ // Label 2513: @81540 |
| 29481 | /* 81540 */ GIM_Reject, |
| 29482 | /* 81541 */ // Label 2502: @81541 |
| 29483 | /* 81541 */ GIM_Reject, |
| 29484 | /* 81542 */ // Label 2499: @81542 |
| 29485 | /* 81542 */ GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(82033), |
| 29486 | /* 81547 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29487 | /* 81550 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 29488 | /* 81553 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29489 | /* 81556 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29490 | /* 81559 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29491 | /* 81562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29492 | /* 81566 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29493 | /* 81570 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29494 | /* 81574 */ GIM_Try, /*On fail goto*//*Label 2517*/ GIMT_Encode4(81688), |
| 29495 | /* 81579 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29496 | /* 81583 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29497 | /* 81587 */ GIM_Try, /*On fail goto*//*Label 2518*/ GIMT_Encode4(81637), // Rule ID 4243 // |
| 29498 | /* 81592 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29499 | /* 81596 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3936:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29500 | /* 81596 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29501 | /* 81599 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29502 | /* 81603 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29503 | /* 81608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs16), |
| 29504 | /* 81611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29505 | /* 81613 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29506 | /* 81615 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29507 | /* 81617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29508 | /* 81620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29509 | /* 81626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29510 | /* 81632 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29511 | /* 81635 */ GIR_RootConstrainSelectedInstOperands, |
| 29512 | /* 81636 */ // GIR_Coverage, 4243, |
| 29513 | /* 81636 */ GIR_EraseRootFromParent_Done, |
| 29514 | /* 81637 */ // Label 2518: @81637 |
| 29515 | /* 81637 */ GIM_Try, /*On fail goto*//*Label 2519*/ GIMT_Encode4(81687), // Rule ID 4249 // |
| 29516 | /* 81642 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29517 | /* 81646 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3936:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29518 | /* 81646 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29519 | /* 81649 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29520 | /* 81653 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29521 | /* 81658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu16), |
| 29522 | /* 81661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29523 | /* 81663 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29524 | /* 81665 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29525 | /* 81667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29526 | /* 81670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29527 | /* 81676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29528 | /* 81682 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29529 | /* 81685 */ GIR_RootConstrainSelectedInstOperands, |
| 29530 | /* 81686 */ // GIR_Coverage, 4249, |
| 29531 | /* 81686 */ GIR_EraseRootFromParent_Done, |
| 29532 | /* 81687 */ // Label 2519: @81687 |
| 29533 | /* 81687 */ GIM_Reject, |
| 29534 | /* 81688 */ // Label 2517: @81688 |
| 29535 | /* 81688 */ GIM_Try, /*On fail goto*//*Label 2520*/ GIMT_Encode4(81918), |
| 29536 | /* 81693 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29537 | /* 81697 */ GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(81807), |
| 29538 | /* 81702 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29539 | /* 81706 */ GIM_Try, /*On fail goto*//*Label 2522*/ GIMT_Encode4(81756), // Rule ID 4255 // |
| 29540 | /* 81711 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29541 | /* 81715 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3936:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29542 | /* 81715 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29543 | /* 81718 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29544 | /* 81722 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29545 | /* 81727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs16), |
| 29546 | /* 81730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29547 | /* 81732 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29548 | /* 81734 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29549 | /* 81736 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29550 | /* 81739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29551 | /* 81745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29552 | /* 81751 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29553 | /* 81754 */ GIR_RootConstrainSelectedInstOperands, |
| 29554 | /* 81755 */ // GIR_Coverage, 4255, |
| 29555 | /* 81755 */ GIR_EraseRootFromParent_Done, |
| 29556 | /* 81756 */ // Label 2522: @81756 |
| 29557 | /* 81756 */ GIM_Try, /*On fail goto*//*Label 2523*/ GIMT_Encode4(81806), // Rule ID 4261 // |
| 29558 | /* 81761 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29559 | /* 81765 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3936:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29560 | /* 81765 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29561 | /* 81768 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29562 | /* 81772 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29563 | /* 81777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu16), |
| 29564 | /* 81780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29565 | /* 81782 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29566 | /* 81784 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29567 | /* 81786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29568 | /* 81789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29569 | /* 81795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29570 | /* 81801 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29571 | /* 81804 */ GIR_RootConstrainSelectedInstOperands, |
| 29572 | /* 81805 */ // GIR_Coverage, 4261, |
| 29573 | /* 81805 */ GIR_EraseRootFromParent_Done, |
| 29574 | /* 81806 */ // Label 2523: @81806 |
| 29575 | /* 81806 */ GIM_Reject, |
| 29576 | /* 81807 */ // Label 2521: @81807 |
| 29577 | /* 81807 */ GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(81917), |
| 29578 | /* 81812 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29579 | /* 81816 */ GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(81866), // Rule ID 4267 // |
| 29580 | /* 81821 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29581 | /* 81825 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3936:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29582 | /* 81825 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29583 | /* 81828 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29584 | /* 81832 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29585 | /* 81837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs16), |
| 29586 | /* 81840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29587 | /* 81842 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29588 | /* 81844 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29589 | /* 81846 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29590 | /* 81849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29591 | /* 81855 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29592 | /* 81861 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29593 | /* 81864 */ GIR_RootConstrainSelectedInstOperands, |
| 29594 | /* 81865 */ // GIR_Coverage, 4267, |
| 29595 | /* 81865 */ GIR_EraseRootFromParent_Done, |
| 29596 | /* 81866 */ // Label 2525: @81866 |
| 29597 | /* 81866 */ GIM_Try, /*On fail goto*//*Label 2526*/ GIMT_Encode4(81916), // Rule ID 4273 // |
| 29598 | /* 81871 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29599 | /* 81875 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3936:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29600 | /* 81875 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29601 | /* 81878 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29602 | /* 81882 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29603 | /* 81887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu16), |
| 29604 | /* 81890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29605 | /* 81892 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29606 | /* 81894 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29607 | /* 81896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29608 | /* 81899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29609 | /* 81905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29610 | /* 81911 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29611 | /* 81914 */ GIR_RootConstrainSelectedInstOperands, |
| 29612 | /* 81915 */ // GIR_Coverage, 4273, |
| 29613 | /* 81915 */ GIR_EraseRootFromParent_Done, |
| 29614 | /* 81916 */ // Label 2526: @81916 |
| 29615 | /* 81916 */ GIM_Reject, |
| 29616 | /* 81917 */ // Label 2524: @81917 |
| 29617 | /* 81917 */ GIM_Reject, |
| 29618 | /* 81918 */ // Label 2520: @81918 |
| 29619 | /* 81918 */ GIM_Try, /*On fail goto*//*Label 2527*/ GIMT_Encode4(82032), |
| 29620 | /* 81923 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29621 | /* 81927 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29622 | /* 81931 */ GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(81981), // Rule ID 4279 // |
| 29623 | /* 81936 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29624 | /* 81940 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3936:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29625 | /* 81940 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29626 | /* 81943 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29627 | /* 81947 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29628 | /* 81952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs16), |
| 29629 | /* 81955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29630 | /* 81957 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29631 | /* 81959 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29632 | /* 81961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29633 | /* 81964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29634 | /* 81970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29635 | /* 81976 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29636 | /* 81979 */ GIR_RootConstrainSelectedInstOperands, |
| 29637 | /* 81980 */ // GIR_Coverage, 4279, |
| 29638 | /* 81980 */ GIR_EraseRootFromParent_Done, |
| 29639 | /* 81981 */ // Label 2528: @81981 |
| 29640 | /* 81981 */ GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(82031), // Rule ID 4285 // |
| 29641 | /* 81986 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29642 | /* 81990 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3936:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29643 | /* 81990 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29644 | /* 81993 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29645 | /* 81997 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29646 | /* 82002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu16), |
| 29647 | /* 82005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29648 | /* 82007 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29649 | /* 82009 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29650 | /* 82011 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29651 | /* 82014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29652 | /* 82020 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29653 | /* 82026 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29654 | /* 82029 */ GIR_RootConstrainSelectedInstOperands, |
| 29655 | /* 82030 */ // GIR_Coverage, 4285, |
| 29656 | /* 82030 */ GIR_EraseRootFromParent_Done, |
| 29657 | /* 82031 */ // Label 2529: @82031 |
| 29658 | /* 82031 */ GIM_Reject, |
| 29659 | /* 82032 */ // Label 2527: @82032 |
| 29660 | /* 82032 */ GIM_Reject, |
| 29661 | /* 82033 */ // Label 2516: @82033 |
| 29662 | /* 82033 */ GIM_Reject, |
| 29663 | /* 82034 */ // Label 2500: @82034 |
| 29664 | /* 82034 */ GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(82525), |
| 29665 | /* 82039 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29666 | /* 82042 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 29667 | /* 82045 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29668 | /* 82048 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29669 | /* 82051 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29670 | /* 82054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29671 | /* 82058 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29672 | /* 82062 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29673 | /* 82066 */ GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(82180), |
| 29674 | /* 82071 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29675 | /* 82075 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29676 | /* 82079 */ GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(82129), // Rule ID 4245 // |
| 29677 | /* 82084 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29678 | /* 82088 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3936:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29679 | /* 82088 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29680 | /* 82091 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29681 | /* 82095 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29682 | /* 82100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs32), |
| 29683 | /* 82103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29684 | /* 82105 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29685 | /* 82107 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29686 | /* 82109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29687 | /* 82112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29688 | /* 82118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29689 | /* 82124 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29690 | /* 82127 */ GIR_RootConstrainSelectedInstOperands, |
| 29691 | /* 82128 */ // GIR_Coverage, 4245, |
| 29692 | /* 82128 */ GIR_EraseRootFromParent_Done, |
| 29693 | /* 82129 */ // Label 2532: @82129 |
| 29694 | /* 82129 */ GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(82179), // Rule ID 4251 // |
| 29695 | /* 82134 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29696 | /* 82138 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3936:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29697 | /* 82138 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29698 | /* 82141 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29699 | /* 82145 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29700 | /* 82150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu32), |
| 29701 | /* 82153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29702 | /* 82155 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29703 | /* 82157 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29704 | /* 82159 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29705 | /* 82162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29706 | /* 82168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29707 | /* 82174 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29708 | /* 82177 */ GIR_RootConstrainSelectedInstOperands, |
| 29709 | /* 82178 */ // GIR_Coverage, 4251, |
| 29710 | /* 82178 */ GIR_EraseRootFromParent_Done, |
| 29711 | /* 82179 */ // Label 2533: @82179 |
| 29712 | /* 82179 */ GIM_Reject, |
| 29713 | /* 82180 */ // Label 2531: @82180 |
| 29714 | /* 82180 */ GIM_Try, /*On fail goto*//*Label 2534*/ GIMT_Encode4(82410), |
| 29715 | /* 82185 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29716 | /* 82189 */ GIM_Try, /*On fail goto*//*Label 2535*/ GIMT_Encode4(82299), |
| 29717 | /* 82194 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29718 | /* 82198 */ GIM_Try, /*On fail goto*//*Label 2536*/ GIMT_Encode4(82248), // Rule ID 4257 // |
| 29719 | /* 82203 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29720 | /* 82207 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3936:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29721 | /* 82207 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29722 | /* 82210 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29723 | /* 82214 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29724 | /* 82219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs32), |
| 29725 | /* 82222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29726 | /* 82224 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29727 | /* 82226 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29728 | /* 82228 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29729 | /* 82231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29730 | /* 82237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29731 | /* 82243 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29732 | /* 82246 */ GIR_RootConstrainSelectedInstOperands, |
| 29733 | /* 82247 */ // GIR_Coverage, 4257, |
| 29734 | /* 82247 */ GIR_EraseRootFromParent_Done, |
| 29735 | /* 82248 */ // Label 2536: @82248 |
| 29736 | /* 82248 */ GIM_Try, /*On fail goto*//*Label 2537*/ GIMT_Encode4(82298), // Rule ID 4263 // |
| 29737 | /* 82253 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29738 | /* 82257 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3936:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29739 | /* 82257 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29740 | /* 82260 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29741 | /* 82264 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29742 | /* 82269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu32), |
| 29743 | /* 82272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29744 | /* 82274 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29745 | /* 82276 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29746 | /* 82278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29747 | /* 82281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29748 | /* 82287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29749 | /* 82293 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29750 | /* 82296 */ GIR_RootConstrainSelectedInstOperands, |
| 29751 | /* 82297 */ // GIR_Coverage, 4263, |
| 29752 | /* 82297 */ GIR_EraseRootFromParent_Done, |
| 29753 | /* 82298 */ // Label 2537: @82298 |
| 29754 | /* 82298 */ GIM_Reject, |
| 29755 | /* 82299 */ // Label 2535: @82299 |
| 29756 | /* 82299 */ GIM_Try, /*On fail goto*//*Label 2538*/ GIMT_Encode4(82409), |
| 29757 | /* 82304 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29758 | /* 82308 */ GIM_Try, /*On fail goto*//*Label 2539*/ GIMT_Encode4(82358), // Rule ID 4269 // |
| 29759 | /* 82313 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29760 | /* 82317 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3936:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29761 | /* 82317 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29762 | /* 82320 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29763 | /* 82324 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29764 | /* 82329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs32), |
| 29765 | /* 82332 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29766 | /* 82334 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29767 | /* 82336 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29768 | /* 82338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29769 | /* 82341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29770 | /* 82347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29771 | /* 82353 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29772 | /* 82356 */ GIR_RootConstrainSelectedInstOperands, |
| 29773 | /* 82357 */ // GIR_Coverage, 4269, |
| 29774 | /* 82357 */ GIR_EraseRootFromParent_Done, |
| 29775 | /* 82358 */ // Label 2539: @82358 |
| 29776 | /* 82358 */ GIM_Try, /*On fail goto*//*Label 2540*/ GIMT_Encode4(82408), // Rule ID 4275 // |
| 29777 | /* 82363 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29778 | /* 82367 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3936:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29779 | /* 82367 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29780 | /* 82370 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29781 | /* 82374 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29782 | /* 82379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu32), |
| 29783 | /* 82382 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29784 | /* 82384 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29785 | /* 82386 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29786 | /* 82388 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29787 | /* 82391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29788 | /* 82397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29789 | /* 82403 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29790 | /* 82406 */ GIR_RootConstrainSelectedInstOperands, |
| 29791 | /* 82407 */ // GIR_Coverage, 4275, |
| 29792 | /* 82407 */ GIR_EraseRootFromParent_Done, |
| 29793 | /* 82408 */ // Label 2540: @82408 |
| 29794 | /* 82408 */ GIM_Reject, |
| 29795 | /* 82409 */ // Label 2538: @82409 |
| 29796 | /* 82409 */ GIM_Reject, |
| 29797 | /* 82410 */ // Label 2534: @82410 |
| 29798 | /* 82410 */ GIM_Try, /*On fail goto*//*Label 2541*/ GIMT_Encode4(82524), |
| 29799 | /* 82415 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29800 | /* 82419 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29801 | /* 82423 */ GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(82473), // Rule ID 4281 // |
| 29802 | /* 82428 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29803 | /* 82432 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3936:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29804 | /* 82432 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29805 | /* 82435 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29806 | /* 82439 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29807 | /* 82444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs32), |
| 29808 | /* 82447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29809 | /* 82449 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29810 | /* 82451 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29811 | /* 82453 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29812 | /* 82456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29813 | /* 82462 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29814 | /* 82468 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29815 | /* 82471 */ GIR_RootConstrainSelectedInstOperands, |
| 29816 | /* 82472 */ // GIR_Coverage, 4281, |
| 29817 | /* 82472 */ GIR_EraseRootFromParent_Done, |
| 29818 | /* 82473 */ // Label 2542: @82473 |
| 29819 | /* 82473 */ GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(82523), // Rule ID 4287 // |
| 29820 | /* 82478 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29821 | /* 82482 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3936:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29822 | /* 82482 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29823 | /* 82485 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29824 | /* 82489 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29825 | /* 82494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu32), |
| 29826 | /* 82497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29827 | /* 82499 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29828 | /* 82501 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29829 | /* 82503 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29830 | /* 82506 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29831 | /* 82512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29832 | /* 82518 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29833 | /* 82521 */ GIR_RootConstrainSelectedInstOperands, |
| 29834 | /* 82522 */ // GIR_Coverage, 4287, |
| 29835 | /* 82522 */ GIR_EraseRootFromParent_Done, |
| 29836 | /* 82523 */ // Label 2543: @82523 |
| 29837 | /* 82523 */ GIM_Reject, |
| 29838 | /* 82524 */ // Label 2541: @82524 |
| 29839 | /* 82524 */ GIM_Reject, |
| 29840 | /* 82525 */ // Label 2530: @82525 |
| 29841 | /* 82525 */ GIM_Reject, |
| 29842 | /* 82526 */ // Label 2501: @82526 |
| 29843 | /* 82526 */ GIM_Reject, |
| 29844 | /* 82527 */ // Label 2497: @82527 |
| 29845 | /* 82527 */ GIM_Try, /*On fail goto*//*Label 2544*/ GIMT_Encode4(83137), |
| 29846 | /* 82532 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 29847 | /* 82537 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 2547*/ GIMT_Encode4(83136), |
| 29848 | /* 82548 */ /*GILLT_v16s8*//*Label 2545*/ GIMT_Encode4(82560), GIMT_Encode4(0), |
| 29849 | /* 82556 */ /*GILLT_v8s16*//*Label 2546*/ GIMT_Encode4(82848), |
| 29850 | /* 82560 */ // Label 2545: @82560 |
| 29851 | /* 82560 */ GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(82847), |
| 29852 | /* 82565 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29853 | /* 82568 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 29854 | /* 82571 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29855 | /* 82574 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29856 | /* 82577 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29857 | /* 82580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29858 | /* 82584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29859 | /* 82588 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29860 | /* 82592 */ GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(82676), |
| 29861 | /* 82597 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29862 | /* 82601 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29863 | /* 82605 */ GIM_Try, /*On fail goto*//*Label 2550*/ GIMT_Encode4(82640), // Rule ID 5004 // |
| 29864 | /* 82610 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29865 | /* 82614 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3901:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 29866 | /* 82614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16bh), |
| 29867 | /* 82617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29868 | /* 82619 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29869 | /* 82621 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29870 | /* 82623 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29871 | /* 82626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29872 | /* 82632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29873 | /* 82638 */ GIR_RootConstrainSelectedInstOperands, |
| 29874 | /* 82639 */ // GIR_Coverage, 5004, |
| 29875 | /* 82639 */ GIR_EraseRootFromParent_Done, |
| 29876 | /* 82640 */ // Label 2550: @82640 |
| 29877 | /* 82640 */ GIM_Try, /*On fail goto*//*Label 2551*/ GIMT_Encode4(82675), // Rule ID 5006 // |
| 29878 | /* 82645 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29879 | /* 82649 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3901:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 29880 | /* 82649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16th), |
| 29881 | /* 82652 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29882 | /* 82654 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29883 | /* 82656 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29884 | /* 82658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29885 | /* 82661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29886 | /* 82667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29887 | /* 82673 */ GIR_RootConstrainSelectedInstOperands, |
| 29888 | /* 82674 */ // GIR_Coverage, 5006, |
| 29889 | /* 82674 */ GIR_EraseRootFromParent_Done, |
| 29890 | /* 82675 */ // Label 2551: @82675 |
| 29891 | /* 82675 */ GIM_Reject, |
| 29892 | /* 82676 */ // Label 2549: @82676 |
| 29893 | /* 82676 */ GIM_Try, /*On fail goto*//*Label 2552*/ GIMT_Encode4(82846), |
| 29894 | /* 82681 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29895 | /* 82685 */ GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(82765), |
| 29896 | /* 82690 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29897 | /* 82694 */ GIM_Try, /*On fail goto*//*Label 2554*/ GIMT_Encode4(82729), // Rule ID 5012 // |
| 29898 | /* 82699 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29899 | /* 82703 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3901:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 29900 | /* 82703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16bh), |
| 29901 | /* 82706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29902 | /* 82708 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29903 | /* 82710 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29904 | /* 82712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29905 | /* 82715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29906 | /* 82721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29907 | /* 82727 */ GIR_RootConstrainSelectedInstOperands, |
| 29908 | /* 82728 */ // GIR_Coverage, 5012, |
| 29909 | /* 82728 */ GIR_EraseRootFromParent_Done, |
| 29910 | /* 82729 */ // Label 2554: @82729 |
| 29911 | /* 82729 */ GIM_Try, /*On fail goto*//*Label 2555*/ GIMT_Encode4(82764), // Rule ID 5014 // |
| 29912 | /* 82734 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29913 | /* 82738 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3901:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 29914 | /* 82738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16th), |
| 29915 | /* 82741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29916 | /* 82743 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29917 | /* 82745 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29918 | /* 82747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29919 | /* 82750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29920 | /* 82756 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29921 | /* 82762 */ GIR_RootConstrainSelectedInstOperands, |
| 29922 | /* 82763 */ // GIR_Coverage, 5014, |
| 29923 | /* 82763 */ GIR_EraseRootFromParent_Done, |
| 29924 | /* 82764 */ // Label 2555: @82764 |
| 29925 | /* 82764 */ GIM_Reject, |
| 29926 | /* 82765 */ // Label 2553: @82765 |
| 29927 | /* 82765 */ GIM_Try, /*On fail goto*//*Label 2556*/ GIMT_Encode4(82845), |
| 29928 | /* 82770 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29929 | /* 82774 */ GIM_Try, /*On fail goto*//*Label 2557*/ GIMT_Encode4(82809), // Rule ID 5020 // |
| 29930 | /* 82779 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29931 | /* 82783 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3901:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 29932 | /* 82783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16bh), |
| 29933 | /* 82786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29934 | /* 82788 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29935 | /* 82790 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29936 | /* 82792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29937 | /* 82795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29938 | /* 82801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29939 | /* 82807 */ GIR_RootConstrainSelectedInstOperands, |
| 29940 | /* 82808 */ // GIR_Coverage, 5020, |
| 29941 | /* 82808 */ GIR_EraseRootFromParent_Done, |
| 29942 | /* 82809 */ // Label 2557: @82809 |
| 29943 | /* 82809 */ GIM_Try, /*On fail goto*//*Label 2558*/ GIMT_Encode4(82844), // Rule ID 5022 // |
| 29944 | /* 82814 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29945 | /* 82818 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3901:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 29946 | /* 82818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16th), |
| 29947 | /* 82821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29948 | /* 82823 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29949 | /* 82825 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29950 | /* 82827 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29951 | /* 82830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29952 | /* 82836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29953 | /* 82842 */ GIR_RootConstrainSelectedInstOperands, |
| 29954 | /* 82843 */ // GIR_Coverage, 5022, |
| 29955 | /* 82843 */ GIR_EraseRootFromParent_Done, |
| 29956 | /* 82844 */ // Label 2558: @82844 |
| 29957 | /* 82844 */ GIM_Reject, |
| 29958 | /* 82845 */ // Label 2556: @82845 |
| 29959 | /* 82845 */ GIM_Reject, |
| 29960 | /* 82846 */ // Label 2552: @82846 |
| 29961 | /* 82846 */ GIM_Reject, |
| 29962 | /* 82847 */ // Label 2548: @82847 |
| 29963 | /* 82847 */ GIM_Reject, |
| 29964 | /* 82848 */ // Label 2546: @82848 |
| 29965 | /* 82848 */ GIM_Try, /*On fail goto*//*Label 2559*/ GIMT_Encode4(83135), |
| 29966 | /* 82853 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29967 | /* 82856 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 29968 | /* 82859 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29969 | /* 82862 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29970 | /* 82865 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29971 | /* 82868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29972 | /* 82872 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29973 | /* 82876 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29974 | /* 82880 */ GIM_Try, /*On fail goto*//*Label 2560*/ GIMT_Encode4(82964), |
| 29975 | /* 82885 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29976 | /* 82889 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29977 | /* 82893 */ GIM_Try, /*On fail goto*//*Label 2561*/ GIMT_Encode4(82928), // Rule ID 5000 // |
| 29978 | /* 82898 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29979 | /* 82902 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3901:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 29980 | /* 82902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32bh), |
| 29981 | /* 82905 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29982 | /* 82907 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29983 | /* 82909 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29984 | /* 82911 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29985 | /* 82914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29986 | /* 82920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29987 | /* 82926 */ GIR_RootConstrainSelectedInstOperands, |
| 29988 | /* 82927 */ // GIR_Coverage, 5000, |
| 29989 | /* 82927 */ GIR_EraseRootFromParent_Done, |
| 29990 | /* 82928 */ // Label 2561: @82928 |
| 29991 | /* 82928 */ GIM_Try, /*On fail goto*//*Label 2562*/ GIMT_Encode4(82963), // Rule ID 5002 // |
| 29992 | /* 82933 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29993 | /* 82937 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3901:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 29994 | /* 82937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32th), |
| 29995 | /* 82940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29996 | /* 82942 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29997 | /* 82944 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29998 | /* 82946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29999 | /* 82949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30000 | /* 82955 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30001 | /* 82961 */ GIR_RootConstrainSelectedInstOperands, |
| 30002 | /* 82962 */ // GIR_Coverage, 5002, |
| 30003 | /* 82962 */ GIR_EraseRootFromParent_Done, |
| 30004 | /* 82963 */ // Label 2562: @82963 |
| 30005 | /* 82963 */ GIM_Reject, |
| 30006 | /* 82964 */ // Label 2560: @82964 |
| 30007 | /* 82964 */ GIM_Try, /*On fail goto*//*Label 2563*/ GIMT_Encode4(83134), |
| 30008 | /* 82969 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30009 | /* 82973 */ GIM_Try, /*On fail goto*//*Label 2564*/ GIMT_Encode4(83053), |
| 30010 | /* 82978 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30011 | /* 82982 */ GIM_Try, /*On fail goto*//*Label 2565*/ GIMT_Encode4(83017), // Rule ID 5008 // |
| 30012 | /* 82987 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30013 | /* 82991 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3901:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 30014 | /* 82991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32bh), |
| 30015 | /* 82994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30016 | /* 82996 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 30017 | /* 82998 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30018 | /* 83000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30019 | /* 83003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30020 | /* 83009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30021 | /* 83015 */ GIR_RootConstrainSelectedInstOperands, |
| 30022 | /* 83016 */ // GIR_Coverage, 5008, |
| 30023 | /* 83016 */ GIR_EraseRootFromParent_Done, |
| 30024 | /* 83017 */ // Label 2565: @83017 |
| 30025 | /* 83017 */ GIM_Try, /*On fail goto*//*Label 2566*/ GIMT_Encode4(83052), // Rule ID 5010 // |
| 30026 | /* 83022 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30027 | /* 83026 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3901:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 30028 | /* 83026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32th), |
| 30029 | /* 83029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30030 | /* 83031 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 30031 | /* 83033 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30032 | /* 83035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30033 | /* 83038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30034 | /* 83044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30035 | /* 83050 */ GIR_RootConstrainSelectedInstOperands, |
| 30036 | /* 83051 */ // GIR_Coverage, 5010, |
| 30037 | /* 83051 */ GIR_EraseRootFromParent_Done, |
| 30038 | /* 83052 */ // Label 2566: @83052 |
| 30039 | /* 83052 */ GIM_Reject, |
| 30040 | /* 83053 */ // Label 2564: @83053 |
| 30041 | /* 83053 */ GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(83133), |
| 30042 | /* 83058 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30043 | /* 83062 */ GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(83097), // Rule ID 5016 // |
| 30044 | /* 83067 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30045 | /* 83071 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3901:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 30046 | /* 83071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32bh), |
| 30047 | /* 83074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30048 | /* 83076 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 30049 | /* 83078 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30050 | /* 83080 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30051 | /* 83083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30052 | /* 83089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30053 | /* 83095 */ GIR_RootConstrainSelectedInstOperands, |
| 30054 | /* 83096 */ // GIR_Coverage, 5016, |
| 30055 | /* 83096 */ GIR_EraseRootFromParent_Done, |
| 30056 | /* 83097 */ // Label 2568: @83097 |
| 30057 | /* 83097 */ GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(83132), // Rule ID 5018 // |
| 30058 | /* 83102 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30059 | /* 83106 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3901:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 30060 | /* 83106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32th), |
| 30061 | /* 83109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30062 | /* 83111 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 30063 | /* 83113 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30064 | /* 83115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30065 | /* 83118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30066 | /* 83124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30067 | /* 83130 */ GIR_RootConstrainSelectedInstOperands, |
| 30068 | /* 83131 */ // GIR_Coverage, 5018, |
| 30069 | /* 83131 */ GIR_EraseRootFromParent_Done, |
| 30070 | /* 83132 */ // Label 2569: @83132 |
| 30071 | /* 83132 */ GIM_Reject, |
| 30072 | /* 83133 */ // Label 2567: @83133 |
| 30073 | /* 83133 */ GIM_Reject, |
| 30074 | /* 83134 */ // Label 2563: @83134 |
| 30075 | /* 83134 */ GIM_Reject, |
| 30076 | /* 83135 */ // Label 2559: @83135 |
| 30077 | /* 83135 */ GIM_Reject, |
| 30078 | /* 83136 */ // Label 2547: @83136 |
| 30079 | /* 83136 */ GIM_Reject, |
| 30080 | /* 83137 */ // Label 2544: @83137 |
| 30081 | /* 83137 */ GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(84301), |
| 30082 | /* 83142 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 30083 | /* 83147 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2574*/ GIMT_Encode4(84300), |
| 30084 | /* 83158 */ /*GILLT_v16s8*//*Label 2571*/ GIMT_Encode4(83178), GIMT_Encode4(0), |
| 30085 | /* 83166 */ /*GILLT_v8s16*//*Label 2572*/ GIMT_Encode4(83552), GIMT_Encode4(0), |
| 30086 | /* 83174 */ /*GILLT_v4s32*//*Label 2573*/ GIMT_Encode4(83926), |
| 30087 | /* 83178 */ // Label 2571: @83178 |
| 30088 | /* 83178 */ GIM_Try, /*On fail goto*//*Label 2575*/ GIMT_Encode4(83551), |
| 30089 | /* 83183 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30090 | /* 83186 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30091 | /* 83189 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30092 | /* 83192 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30093 | /* 83195 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30094 | /* 83198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30095 | /* 83202 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30096 | /* 83206 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30097 | /* 83210 */ GIM_Try, /*On fail goto*//*Label 2576*/ GIMT_Encode4(83380), |
| 30098 | /* 83215 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30099 | /* 83219 */ GIM_Try, /*On fail goto*//*Label 2577*/ GIMT_Encode4(83299), |
| 30100 | /* 83224 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30101 | /* 83228 */ GIM_Try, /*On fail goto*//*Label 2578*/ GIMT_Encode4(83263), // Rule ID 5224 // |
| 30102 | /* 83233 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30103 | /* 83237 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3934:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30104 | /* 83237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs8), |
| 30105 | /* 83240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30106 | /* 83242 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30107 | /* 83244 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30108 | /* 83246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30109 | /* 83249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30110 | /* 83255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30111 | /* 83261 */ GIR_RootConstrainSelectedInstOperands, |
| 30112 | /* 83262 */ // GIR_Coverage, 5224, |
| 30113 | /* 83262 */ GIR_EraseRootFromParent_Done, |
| 30114 | /* 83263 */ // Label 2578: @83263 |
| 30115 | /* 83263 */ GIM_Try, /*On fail goto*//*Label 2579*/ GIMT_Encode4(83298), // Rule ID 5230 // |
| 30116 | /* 83268 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30117 | /* 83272 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3934:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30118 | /* 83272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru8), |
| 30119 | /* 83275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30120 | /* 83277 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30121 | /* 83279 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30122 | /* 83281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30123 | /* 83284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30124 | /* 83290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30125 | /* 83296 */ GIR_RootConstrainSelectedInstOperands, |
| 30126 | /* 83297 */ // GIR_Coverage, 5230, |
| 30127 | /* 83297 */ GIR_EraseRootFromParent_Done, |
| 30128 | /* 83298 */ // Label 2579: @83298 |
| 30129 | /* 83298 */ GIM_Reject, |
| 30130 | /* 83299 */ // Label 2577: @83299 |
| 30131 | /* 83299 */ GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(83379), |
| 30132 | /* 83304 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30133 | /* 83308 */ GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(83343), // Rule ID 5236 // |
| 30134 | /* 83313 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30135 | /* 83317 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3934:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30136 | /* 83317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs8), |
| 30137 | /* 83320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30138 | /* 83322 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30139 | /* 83324 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30140 | /* 83326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30141 | /* 83329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30142 | /* 83335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30143 | /* 83341 */ GIR_RootConstrainSelectedInstOperands, |
| 30144 | /* 83342 */ // GIR_Coverage, 5236, |
| 30145 | /* 83342 */ GIR_EraseRootFromParent_Done, |
| 30146 | /* 83343 */ // Label 2581: @83343 |
| 30147 | /* 83343 */ GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(83378), // Rule ID 5242 // |
| 30148 | /* 83348 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30149 | /* 83352 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3934:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30150 | /* 83352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru8), |
| 30151 | /* 83355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30152 | /* 83357 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30153 | /* 83359 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30154 | /* 83361 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30155 | /* 83364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30156 | /* 83370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30157 | /* 83376 */ GIR_RootConstrainSelectedInstOperands, |
| 30158 | /* 83377 */ // GIR_Coverage, 5242, |
| 30159 | /* 83377 */ GIR_EraseRootFromParent_Done, |
| 30160 | /* 83378 */ // Label 2582: @83378 |
| 30161 | /* 83378 */ GIM_Reject, |
| 30162 | /* 83379 */ // Label 2580: @83379 |
| 30163 | /* 83379 */ GIM_Reject, |
| 30164 | /* 83380 */ // Label 2576: @83380 |
| 30165 | /* 83380 */ GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(83550), |
| 30166 | /* 83385 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30167 | /* 83389 */ GIM_Try, /*On fail goto*//*Label 2584*/ GIMT_Encode4(83469), |
| 30168 | /* 83394 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30169 | /* 83398 */ GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(83433), // Rule ID 5248 // |
| 30170 | /* 83403 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30171 | /* 83407 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3934:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30172 | /* 83407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs8), |
| 30173 | /* 83410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30174 | /* 83412 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30175 | /* 83414 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30176 | /* 83416 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30177 | /* 83419 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30178 | /* 83425 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30179 | /* 83431 */ GIR_RootConstrainSelectedInstOperands, |
| 30180 | /* 83432 */ // GIR_Coverage, 5248, |
| 30181 | /* 83432 */ GIR_EraseRootFromParent_Done, |
| 30182 | /* 83433 */ // Label 2585: @83433 |
| 30183 | /* 83433 */ GIM_Try, /*On fail goto*//*Label 2586*/ GIMT_Encode4(83468), // Rule ID 5254 // |
| 30184 | /* 83438 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30185 | /* 83442 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3934:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30186 | /* 83442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru8), |
| 30187 | /* 83445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30188 | /* 83447 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30189 | /* 83449 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30190 | /* 83451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30191 | /* 83454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30192 | /* 83460 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30193 | /* 83466 */ GIR_RootConstrainSelectedInstOperands, |
| 30194 | /* 83467 */ // GIR_Coverage, 5254, |
| 30195 | /* 83467 */ GIR_EraseRootFromParent_Done, |
| 30196 | /* 83468 */ // Label 2586: @83468 |
| 30197 | /* 83468 */ GIM_Reject, |
| 30198 | /* 83469 */ // Label 2584: @83469 |
| 30199 | /* 83469 */ GIM_Try, /*On fail goto*//*Label 2587*/ GIMT_Encode4(83549), |
| 30200 | /* 83474 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30201 | /* 83478 */ GIM_Try, /*On fail goto*//*Label 2588*/ GIMT_Encode4(83513), // Rule ID 5260 // |
| 30202 | /* 83483 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30203 | /* 83487 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3934:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30204 | /* 83487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs8), |
| 30205 | /* 83490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30206 | /* 83492 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30207 | /* 83494 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30208 | /* 83496 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30209 | /* 83499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30210 | /* 83505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30211 | /* 83511 */ GIR_RootConstrainSelectedInstOperands, |
| 30212 | /* 83512 */ // GIR_Coverage, 5260, |
| 30213 | /* 83512 */ GIR_EraseRootFromParent_Done, |
| 30214 | /* 83513 */ // Label 2588: @83513 |
| 30215 | /* 83513 */ GIM_Try, /*On fail goto*//*Label 2589*/ GIMT_Encode4(83548), // Rule ID 5266 // |
| 30216 | /* 83518 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30217 | /* 83522 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3934:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30218 | /* 83522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru8), |
| 30219 | /* 83525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30220 | /* 83527 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30221 | /* 83529 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30222 | /* 83531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30223 | /* 83534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30224 | /* 83540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30225 | /* 83546 */ GIR_RootConstrainSelectedInstOperands, |
| 30226 | /* 83547 */ // GIR_Coverage, 5266, |
| 30227 | /* 83547 */ GIR_EraseRootFromParent_Done, |
| 30228 | /* 83548 */ // Label 2589: @83548 |
| 30229 | /* 83548 */ GIM_Reject, |
| 30230 | /* 83549 */ // Label 2587: @83549 |
| 30231 | /* 83549 */ GIM_Reject, |
| 30232 | /* 83550 */ // Label 2583: @83550 |
| 30233 | /* 83550 */ GIM_Reject, |
| 30234 | /* 83551 */ // Label 2575: @83551 |
| 30235 | /* 83551 */ GIM_Reject, |
| 30236 | /* 83552 */ // Label 2572: @83552 |
| 30237 | /* 83552 */ GIM_Try, /*On fail goto*//*Label 2590*/ GIMT_Encode4(83925), |
| 30238 | /* 83557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30239 | /* 83560 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30240 | /* 83563 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30241 | /* 83566 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30242 | /* 83569 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30243 | /* 83572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30244 | /* 83576 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30245 | /* 83580 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30246 | /* 83584 */ GIM_Try, /*On fail goto*//*Label 2591*/ GIMT_Encode4(83754), |
| 30247 | /* 83589 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30248 | /* 83593 */ GIM_Try, /*On fail goto*//*Label 2592*/ GIMT_Encode4(83673), |
| 30249 | /* 83598 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30250 | /* 83602 */ GIM_Try, /*On fail goto*//*Label 2593*/ GIMT_Encode4(83637), // Rule ID 5226 // |
| 30251 | /* 83607 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30252 | /* 83611 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3934:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30253 | /* 83611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs16), |
| 30254 | /* 83614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30255 | /* 83616 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30256 | /* 83618 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30257 | /* 83620 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30258 | /* 83623 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30259 | /* 83629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30260 | /* 83635 */ GIR_RootConstrainSelectedInstOperands, |
| 30261 | /* 83636 */ // GIR_Coverage, 5226, |
| 30262 | /* 83636 */ GIR_EraseRootFromParent_Done, |
| 30263 | /* 83637 */ // Label 2593: @83637 |
| 30264 | /* 83637 */ GIM_Try, /*On fail goto*//*Label 2594*/ GIMT_Encode4(83672), // Rule ID 5232 // |
| 30265 | /* 83642 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30266 | /* 83646 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3934:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30267 | /* 83646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru16), |
| 30268 | /* 83649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30269 | /* 83651 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30270 | /* 83653 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30271 | /* 83655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30272 | /* 83658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30273 | /* 83664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30274 | /* 83670 */ GIR_RootConstrainSelectedInstOperands, |
| 30275 | /* 83671 */ // GIR_Coverage, 5232, |
| 30276 | /* 83671 */ GIR_EraseRootFromParent_Done, |
| 30277 | /* 83672 */ // Label 2594: @83672 |
| 30278 | /* 83672 */ GIM_Reject, |
| 30279 | /* 83673 */ // Label 2592: @83673 |
| 30280 | /* 83673 */ GIM_Try, /*On fail goto*//*Label 2595*/ GIMT_Encode4(83753), |
| 30281 | /* 83678 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30282 | /* 83682 */ GIM_Try, /*On fail goto*//*Label 2596*/ GIMT_Encode4(83717), // Rule ID 5238 // |
| 30283 | /* 83687 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30284 | /* 83691 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3934:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30285 | /* 83691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs16), |
| 30286 | /* 83694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30287 | /* 83696 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30288 | /* 83698 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30289 | /* 83700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30290 | /* 83703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30291 | /* 83709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30292 | /* 83715 */ GIR_RootConstrainSelectedInstOperands, |
| 30293 | /* 83716 */ // GIR_Coverage, 5238, |
| 30294 | /* 83716 */ GIR_EraseRootFromParent_Done, |
| 30295 | /* 83717 */ // Label 2596: @83717 |
| 30296 | /* 83717 */ GIM_Try, /*On fail goto*//*Label 2597*/ GIMT_Encode4(83752), // Rule ID 5244 // |
| 30297 | /* 83722 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30298 | /* 83726 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3934:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30299 | /* 83726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru16), |
| 30300 | /* 83729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30301 | /* 83731 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30302 | /* 83733 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30303 | /* 83735 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30304 | /* 83738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30305 | /* 83744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30306 | /* 83750 */ GIR_RootConstrainSelectedInstOperands, |
| 30307 | /* 83751 */ // GIR_Coverage, 5244, |
| 30308 | /* 83751 */ GIR_EraseRootFromParent_Done, |
| 30309 | /* 83752 */ // Label 2597: @83752 |
| 30310 | /* 83752 */ GIM_Reject, |
| 30311 | /* 83753 */ // Label 2595: @83753 |
| 30312 | /* 83753 */ GIM_Reject, |
| 30313 | /* 83754 */ // Label 2591: @83754 |
| 30314 | /* 83754 */ GIM_Try, /*On fail goto*//*Label 2598*/ GIMT_Encode4(83924), |
| 30315 | /* 83759 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30316 | /* 83763 */ GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(83843), |
| 30317 | /* 83768 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30318 | /* 83772 */ GIM_Try, /*On fail goto*//*Label 2600*/ GIMT_Encode4(83807), // Rule ID 5250 // |
| 30319 | /* 83777 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30320 | /* 83781 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3934:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30321 | /* 83781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs16), |
| 30322 | /* 83784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30323 | /* 83786 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30324 | /* 83788 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30325 | /* 83790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30326 | /* 83793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30327 | /* 83799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30328 | /* 83805 */ GIR_RootConstrainSelectedInstOperands, |
| 30329 | /* 83806 */ // GIR_Coverage, 5250, |
| 30330 | /* 83806 */ GIR_EraseRootFromParent_Done, |
| 30331 | /* 83807 */ // Label 2600: @83807 |
| 30332 | /* 83807 */ GIM_Try, /*On fail goto*//*Label 2601*/ GIMT_Encode4(83842), // Rule ID 5256 // |
| 30333 | /* 83812 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30334 | /* 83816 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3934:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30335 | /* 83816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru16), |
| 30336 | /* 83819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30337 | /* 83821 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30338 | /* 83823 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30339 | /* 83825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30340 | /* 83828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30341 | /* 83834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30342 | /* 83840 */ GIR_RootConstrainSelectedInstOperands, |
| 30343 | /* 83841 */ // GIR_Coverage, 5256, |
| 30344 | /* 83841 */ GIR_EraseRootFromParent_Done, |
| 30345 | /* 83842 */ // Label 2601: @83842 |
| 30346 | /* 83842 */ GIM_Reject, |
| 30347 | /* 83843 */ // Label 2599: @83843 |
| 30348 | /* 83843 */ GIM_Try, /*On fail goto*//*Label 2602*/ GIMT_Encode4(83923), |
| 30349 | /* 83848 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30350 | /* 83852 */ GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(83887), // Rule ID 5262 // |
| 30351 | /* 83857 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30352 | /* 83861 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3934:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30353 | /* 83861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs16), |
| 30354 | /* 83864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30355 | /* 83866 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30356 | /* 83868 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30357 | /* 83870 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30358 | /* 83873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30359 | /* 83879 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30360 | /* 83885 */ GIR_RootConstrainSelectedInstOperands, |
| 30361 | /* 83886 */ // GIR_Coverage, 5262, |
| 30362 | /* 83886 */ GIR_EraseRootFromParent_Done, |
| 30363 | /* 83887 */ // Label 2603: @83887 |
| 30364 | /* 83887 */ GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(83922), // Rule ID 5268 // |
| 30365 | /* 83892 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30366 | /* 83896 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3934:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30367 | /* 83896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru16), |
| 30368 | /* 83899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30369 | /* 83901 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30370 | /* 83903 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30371 | /* 83905 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30372 | /* 83908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30373 | /* 83914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30374 | /* 83920 */ GIR_RootConstrainSelectedInstOperands, |
| 30375 | /* 83921 */ // GIR_Coverage, 5268, |
| 30376 | /* 83921 */ GIR_EraseRootFromParent_Done, |
| 30377 | /* 83922 */ // Label 2604: @83922 |
| 30378 | /* 83922 */ GIM_Reject, |
| 30379 | /* 83923 */ // Label 2602: @83923 |
| 30380 | /* 83923 */ GIM_Reject, |
| 30381 | /* 83924 */ // Label 2598: @83924 |
| 30382 | /* 83924 */ GIM_Reject, |
| 30383 | /* 83925 */ // Label 2590: @83925 |
| 30384 | /* 83925 */ GIM_Reject, |
| 30385 | /* 83926 */ // Label 2573: @83926 |
| 30386 | /* 83926 */ GIM_Try, /*On fail goto*//*Label 2605*/ GIMT_Encode4(84299), |
| 30387 | /* 83931 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30388 | /* 83934 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30389 | /* 83937 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30390 | /* 83940 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30391 | /* 83943 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30392 | /* 83946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30393 | /* 83950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30394 | /* 83954 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30395 | /* 83958 */ GIM_Try, /*On fail goto*//*Label 2606*/ GIMT_Encode4(84128), |
| 30396 | /* 83963 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30397 | /* 83967 */ GIM_Try, /*On fail goto*//*Label 2607*/ GIMT_Encode4(84047), |
| 30398 | /* 83972 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30399 | /* 83976 */ GIM_Try, /*On fail goto*//*Label 2608*/ GIMT_Encode4(84011), // Rule ID 5228 // |
| 30400 | /* 83981 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30401 | /* 83985 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3934:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30402 | /* 83985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs32), |
| 30403 | /* 83988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30404 | /* 83990 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30405 | /* 83992 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30406 | /* 83994 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30407 | /* 83997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30408 | /* 84003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30409 | /* 84009 */ GIR_RootConstrainSelectedInstOperands, |
| 30410 | /* 84010 */ // GIR_Coverage, 5228, |
| 30411 | /* 84010 */ GIR_EraseRootFromParent_Done, |
| 30412 | /* 84011 */ // Label 2608: @84011 |
| 30413 | /* 84011 */ GIM_Try, /*On fail goto*//*Label 2609*/ GIMT_Encode4(84046), // Rule ID 5234 // |
| 30414 | /* 84016 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30415 | /* 84020 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3934:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30416 | /* 84020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru32), |
| 30417 | /* 84023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30418 | /* 84025 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30419 | /* 84027 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30420 | /* 84029 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30421 | /* 84032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30422 | /* 84038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30423 | /* 84044 */ GIR_RootConstrainSelectedInstOperands, |
| 30424 | /* 84045 */ // GIR_Coverage, 5234, |
| 30425 | /* 84045 */ GIR_EraseRootFromParent_Done, |
| 30426 | /* 84046 */ // Label 2609: @84046 |
| 30427 | /* 84046 */ GIM_Reject, |
| 30428 | /* 84047 */ // Label 2607: @84047 |
| 30429 | /* 84047 */ GIM_Try, /*On fail goto*//*Label 2610*/ GIMT_Encode4(84127), |
| 30430 | /* 84052 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30431 | /* 84056 */ GIM_Try, /*On fail goto*//*Label 2611*/ GIMT_Encode4(84091), // Rule ID 5240 // |
| 30432 | /* 84061 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30433 | /* 84065 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3934:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30434 | /* 84065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs32), |
| 30435 | /* 84068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30436 | /* 84070 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30437 | /* 84072 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30438 | /* 84074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30439 | /* 84077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30440 | /* 84083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30441 | /* 84089 */ GIR_RootConstrainSelectedInstOperands, |
| 30442 | /* 84090 */ // GIR_Coverage, 5240, |
| 30443 | /* 84090 */ GIR_EraseRootFromParent_Done, |
| 30444 | /* 84091 */ // Label 2611: @84091 |
| 30445 | /* 84091 */ GIM_Try, /*On fail goto*//*Label 2612*/ GIMT_Encode4(84126), // Rule ID 5246 // |
| 30446 | /* 84096 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30447 | /* 84100 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3934:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30448 | /* 84100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru32), |
| 30449 | /* 84103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30450 | /* 84105 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30451 | /* 84107 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30452 | /* 84109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30453 | /* 84112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30454 | /* 84118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30455 | /* 84124 */ GIR_RootConstrainSelectedInstOperands, |
| 30456 | /* 84125 */ // GIR_Coverage, 5246, |
| 30457 | /* 84125 */ GIR_EraseRootFromParent_Done, |
| 30458 | /* 84126 */ // Label 2612: @84126 |
| 30459 | /* 84126 */ GIM_Reject, |
| 30460 | /* 84127 */ // Label 2610: @84127 |
| 30461 | /* 84127 */ GIM_Reject, |
| 30462 | /* 84128 */ // Label 2606: @84128 |
| 30463 | /* 84128 */ GIM_Try, /*On fail goto*//*Label 2613*/ GIMT_Encode4(84298), |
| 30464 | /* 84133 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30465 | /* 84137 */ GIM_Try, /*On fail goto*//*Label 2614*/ GIMT_Encode4(84217), |
| 30466 | /* 84142 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30467 | /* 84146 */ GIM_Try, /*On fail goto*//*Label 2615*/ GIMT_Encode4(84181), // Rule ID 5252 // |
| 30468 | /* 84151 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30469 | /* 84155 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3934:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30470 | /* 84155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs32), |
| 30471 | /* 84158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30472 | /* 84160 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30473 | /* 84162 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30474 | /* 84164 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30475 | /* 84167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30476 | /* 84173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30477 | /* 84179 */ GIR_RootConstrainSelectedInstOperands, |
| 30478 | /* 84180 */ // GIR_Coverage, 5252, |
| 30479 | /* 84180 */ GIR_EraseRootFromParent_Done, |
| 30480 | /* 84181 */ // Label 2615: @84181 |
| 30481 | /* 84181 */ GIM_Try, /*On fail goto*//*Label 2616*/ GIMT_Encode4(84216), // Rule ID 5258 // |
| 30482 | /* 84186 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30483 | /* 84190 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3934:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30484 | /* 84190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru32), |
| 30485 | /* 84193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30486 | /* 84195 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30487 | /* 84197 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30488 | /* 84199 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30489 | /* 84202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30490 | /* 84208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30491 | /* 84214 */ GIR_RootConstrainSelectedInstOperands, |
| 30492 | /* 84215 */ // GIR_Coverage, 5258, |
| 30493 | /* 84215 */ GIR_EraseRootFromParent_Done, |
| 30494 | /* 84216 */ // Label 2616: @84216 |
| 30495 | /* 84216 */ GIM_Reject, |
| 30496 | /* 84217 */ // Label 2614: @84217 |
| 30497 | /* 84217 */ GIM_Try, /*On fail goto*//*Label 2617*/ GIMT_Encode4(84297), |
| 30498 | /* 84222 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30499 | /* 84226 */ GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(84261), // Rule ID 5264 // |
| 30500 | /* 84231 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30501 | /* 84235 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3934:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30502 | /* 84235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs32), |
| 30503 | /* 84238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30504 | /* 84240 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30505 | /* 84242 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30506 | /* 84244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30507 | /* 84247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30508 | /* 84253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30509 | /* 84259 */ GIR_RootConstrainSelectedInstOperands, |
| 30510 | /* 84260 */ // GIR_Coverage, 5264, |
| 30511 | /* 84260 */ GIR_EraseRootFromParent_Done, |
| 30512 | /* 84261 */ // Label 2618: @84261 |
| 30513 | /* 84261 */ GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(84296), // Rule ID 5270 // |
| 30514 | /* 84266 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30515 | /* 84270 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3934:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30516 | /* 84270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru32), |
| 30517 | /* 84273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30518 | /* 84275 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30519 | /* 84277 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30520 | /* 84279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30521 | /* 84282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30522 | /* 84288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30523 | /* 84294 */ GIR_RootConstrainSelectedInstOperands, |
| 30524 | /* 84295 */ // GIR_Coverage, 5270, |
| 30525 | /* 84295 */ GIR_EraseRootFromParent_Done, |
| 30526 | /* 84296 */ // Label 2619: @84296 |
| 30527 | /* 84296 */ GIM_Reject, |
| 30528 | /* 84297 */ // Label 2617: @84297 |
| 30529 | /* 84297 */ GIM_Reject, |
| 30530 | /* 84298 */ // Label 2613: @84298 |
| 30531 | /* 84298 */ GIM_Reject, |
| 30532 | /* 84299 */ // Label 2605: @84299 |
| 30533 | /* 84299 */ GIM_Reject, |
| 30534 | /* 84300 */ // Label 2574: @84300 |
| 30535 | /* 84300 */ GIM_Reject, |
| 30536 | /* 84301 */ // Label 2570: @84301 |
| 30537 | /* 84301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2620*/ GIMT_Encode4(84436), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3079 // |
| 30538 | /* 84308 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx3), |
| 30539 | /* 84313 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 30540 | /* 84316 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 30541 | /* 84319 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 30542 | /* 84322 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 30543 | /* 84325 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 30544 | /* 84328 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8, |
| 30545 | /* 84331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 30546 | /* 84335 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4093:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBX3Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 30547 | /* 84335 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8, |
| 30548 | /* 84338 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30549 | /* 84342 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30550 | /* 84347 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 30551 | /* 84349 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 30552 | /* 84352 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 30553 | /* 84356 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30554 | /* 84361 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 |
| 30555 | /* 84365 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 30556 | /* 84368 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 |
| 30557 | /* 84372 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 30558 | /* 84375 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2 |
| 30559 | /* 84379 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 30560 | /* 84382 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 30561 | /* 84385 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 30562 | /* 84388 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 30563 | /* 84393 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 30564 | /* 84398 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 30565 | /* 84403 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 30566 | /* 84408 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 30567 | /* 84413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX3Pseudo), |
| 30568 | /* 84416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 30569 | /* 84418 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 30570 | /* 84420 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30571 | /* 84423 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm |
| 30572 | /* 84425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 30573 | /* 84428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30574 | /* 84434 */ GIR_RootConstrainSelectedInstOperands, |
| 30575 | /* 84435 */ // GIR_Coverage, 3079, |
| 30576 | /* 84435 */ GIR_EraseRootFromParent_Done, |
| 30577 | /* 84436 */ // Label 2620: @84436 |
| 30578 | /* 84436 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2621*/ GIMT_Encode4(84556), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3080 // |
| 30579 | /* 84443 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl4), |
| 30580 | /* 84448 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 30581 | /* 84451 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 30582 | /* 84454 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 30583 | /* 84457 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 30584 | /* 84460 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 30585 | /* 84463 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8, |
| 30586 | /* 84466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 30587 | /* 84470 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4090:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBL4Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 30588 | /* 84470 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 30589 | /* 84473 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 30590 | /* 84477 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30591 | /* 84482 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0 |
| 30592 | /* 84486 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 30593 | /* 84489 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1 |
| 30594 | /* 84493 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 30595 | /* 84496 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2 |
| 30596 | /* 84500 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 30597 | /* 84503 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn3 |
| 30598 | /* 84507 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 30599 | /* 84510 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 30600 | /* 84515 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 30601 | /* 84520 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 30602 | /* 84525 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 30603 | /* 84530 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 30604 | /* 84535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL4Pseudo), |
| 30605 | /* 84538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 30606 | /* 84540 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30607 | /* 84543 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm |
| 30608 | /* 84545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 30609 | /* 84548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30610 | /* 84554 */ GIR_RootConstrainSelectedInstOperands, |
| 30611 | /* 84555 */ // GIR_Coverage, 3080, |
| 30612 | /* 84555 */ GIR_EraseRootFromParent_Done, |
| 30613 | /* 84556 */ // Label 2621: @84556 |
| 30614 | /* 84556 */ GIM_Reject, |
| 30615 | /* 84557 */ // Label 2496: @84557 |
| 30616 | /* 84557 */ GIM_Try, /*On fail goto*//*Label 2622*/ GIMT_Encode4(87751), |
| 30617 | /* 84562 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/8, |
| 30618 | /* 84565 */ GIM_Try, /*On fail goto*//*Label 2623*/ GIMT_Encode4(86380), |
| 30619 | /* 84570 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 30620 | /* 84575 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30621 | /* 84578 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30622 | /* 84581 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30623 | /* 84584 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30624 | /* 84587 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30625 | /* 84590 */ GIM_SwitchType, /*MI*/0, /*Op*/6, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2627*/ GIMT_Encode4(86379), |
| 30626 | /* 84601 */ /*GILLT_v16s8*//*Label 2624*/ GIMT_Encode4(84621), GIMT_Encode4(0), |
| 30627 | /* 84609 */ /*GILLT_v8s16*//*Label 2625*/ GIMT_Encode4(85207), GIMT_Encode4(0), |
| 30628 | /* 84617 */ /*GILLT_v4s32*//*Label 2626*/ GIMT_Encode4(85793), |
| 30629 | /* 84621 */ // Label 2624: @84621 |
| 30630 | /* 84621 */ GIM_Try, /*On fail goto*//*Label 2628*/ GIMT_Encode4(85206), |
| 30631 | /* 84626 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 30632 | /* 84629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30633 | /* 84633 */ GIM_Try, /*On fail goto*//*Label 2629*/ GIMT_Encode4(84745), |
| 30634 | /* 84638 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30635 | /* 84642 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30636 | /* 84646 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2630*/ GIMT_Encode4(84695), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3572 // |
| 30637 | /* 84653 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30638 | /* 84657 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30639 | /* 84661 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30640 | /* 84665 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30641 | /* 84669 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30642 | /* 84669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs8), |
| 30643 | /* 84672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30644 | /* 84674 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30645 | /* 84676 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30646 | /* 84678 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30647 | /* 84681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30648 | /* 84687 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30649 | /* 84693 */ GIR_RootConstrainSelectedInstOperands, |
| 30650 | /* 84694 */ // GIR_Coverage, 3572, |
| 30651 | /* 84694 */ GIR_EraseRootFromParent_Done, |
| 30652 | /* 84695 */ // Label 2630: @84695 |
| 30653 | /* 84695 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2631*/ GIMT_Encode4(84744), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3576 // |
| 30654 | /* 84702 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30655 | /* 84706 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30656 | /* 84710 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30657 | /* 84714 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30658 | /* 84718 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30659 | /* 84718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs8), |
| 30660 | /* 84721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30661 | /* 84723 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30662 | /* 84725 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30663 | /* 84727 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30664 | /* 84730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30665 | /* 84736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30666 | /* 84742 */ GIR_RootConstrainSelectedInstOperands, |
| 30667 | /* 84743 */ // GIR_Coverage, 3576, |
| 30668 | /* 84743 */ GIR_EraseRootFromParent_Done, |
| 30669 | /* 84744 */ // Label 2631: @84744 |
| 30670 | /* 84744 */ GIM_Reject, |
| 30671 | /* 84745 */ // Label 2629: @84745 |
| 30672 | /* 84745 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2632*/ GIMT_Encode4(84802), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3580 // |
| 30673 | /* 84752 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 30674 | /* 84756 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30675 | /* 84760 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30676 | /* 84764 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30677 | /* 84768 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30678 | /* 84772 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30679 | /* 84776 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVu8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30680 | /* 84776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8), |
| 30681 | /* 84779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30682 | /* 84781 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30683 | /* 84783 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30684 | /* 84785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30685 | /* 84788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30686 | /* 84794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30687 | /* 84800 */ GIR_RootConstrainSelectedInstOperands, |
| 30688 | /* 84801 */ // GIR_Coverage, 3580, |
| 30689 | /* 84801 */ GIR_EraseRootFromParent_Done, |
| 30690 | /* 84802 */ // Label 2632: @84802 |
| 30691 | /* 84802 */ GIM_Try, /*On fail goto*//*Label 2633*/ GIMT_Encode4(84914), |
| 30692 | /* 84807 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30693 | /* 84811 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 30694 | /* 84815 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2634*/ GIMT_Encode4(84864), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3608 // |
| 30695 | /* 84822 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30696 | /* 84826 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30697 | /* 84830 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30698 | /* 84834 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30699 | /* 84838 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30700 | /* 84838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs8), |
| 30701 | /* 84841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30702 | /* 84843 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30703 | /* 84845 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30704 | /* 84847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30705 | /* 84850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30706 | /* 84856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30707 | /* 84862 */ GIR_RootConstrainSelectedInstOperands, |
| 30708 | /* 84863 */ // GIR_Coverage, 3608, |
| 30709 | /* 84863 */ GIR_EraseRootFromParent_Done, |
| 30710 | /* 84864 */ // Label 2634: @84864 |
| 30711 | /* 84864 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2635*/ GIMT_Encode4(84913), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3612 // |
| 30712 | /* 84871 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30713 | /* 84875 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30714 | /* 84879 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30715 | /* 84883 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30716 | /* 84887 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30717 | /* 84887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs8), |
| 30718 | /* 84890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30719 | /* 84892 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30720 | /* 84894 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30721 | /* 84896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30722 | /* 84899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30723 | /* 84905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30724 | /* 84911 */ GIR_RootConstrainSelectedInstOperands, |
| 30725 | /* 84912 */ // GIR_Coverage, 3612, |
| 30726 | /* 84912 */ GIR_EraseRootFromParent_Done, |
| 30727 | /* 84913 */ // Label 2635: @84913 |
| 30728 | /* 84913 */ GIM_Reject, |
| 30729 | /* 84914 */ // Label 2633: @84914 |
| 30730 | /* 84914 */ GIM_Try, /*On fail goto*//*Label 2636*/ GIMT_Encode4(85030), |
| 30731 | /* 84919 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30732 | /* 84923 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30733 | /* 84927 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2637*/ GIMT_Encode4(84978), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3574 // |
| 30734 | /* 84934 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30735 | /* 84938 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30736 | /* 84942 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30737 | /* 84946 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30738 | /* 84950 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30739 | /* 84950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas8), |
| 30740 | /* 84953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30741 | /* 84955 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30742 | /* 84957 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30743 | /* 84959 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30744 | /* 84961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30745 | /* 84964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30746 | /* 84970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30747 | /* 84976 */ GIR_RootConstrainSelectedInstOperands, |
| 30748 | /* 84977 */ // GIR_Coverage, 3574, |
| 30749 | /* 84977 */ GIR_EraseRootFromParent_Done, |
| 30750 | /* 84978 */ // Label 2637: @84978 |
| 30751 | /* 84978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2638*/ GIMT_Encode4(85029), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3578 // |
| 30752 | /* 84985 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30753 | /* 84989 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30754 | /* 84993 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30755 | /* 84997 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30756 | /* 85001 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30757 | /* 85001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs8), |
| 30758 | /* 85004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30759 | /* 85006 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30760 | /* 85008 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30761 | /* 85010 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30762 | /* 85012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30763 | /* 85015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30764 | /* 85021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30765 | /* 85027 */ GIR_RootConstrainSelectedInstOperands, |
| 30766 | /* 85028 */ // GIR_Coverage, 3578, |
| 30767 | /* 85028 */ GIR_EraseRootFromParent_Done, |
| 30768 | /* 85029 */ // Label 2638: @85029 |
| 30769 | /* 85029 */ GIM_Reject, |
| 30770 | /* 85030 */ // Label 2636: @85030 |
| 30771 | /* 85030 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2639*/ GIMT_Encode4(85089), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3582 // |
| 30772 | /* 85037 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 30773 | /* 85041 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30774 | /* 85045 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30775 | /* 85049 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30776 | /* 85053 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30777 | /* 85057 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30778 | /* 85061 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVau8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30779 | /* 85061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8), |
| 30780 | /* 85064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30781 | /* 85066 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30782 | /* 85068 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30783 | /* 85070 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30784 | /* 85072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30785 | /* 85075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30786 | /* 85081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30787 | /* 85087 */ GIR_RootConstrainSelectedInstOperands, |
| 30788 | /* 85088 */ // GIR_Coverage, 3582, |
| 30789 | /* 85088 */ GIR_EraseRootFromParent_Done, |
| 30790 | /* 85089 */ // Label 2639: @85089 |
| 30791 | /* 85089 */ GIM_Try, /*On fail goto*//*Label 2640*/ GIMT_Encode4(85205), |
| 30792 | /* 85094 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30793 | /* 85098 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 30794 | /* 85102 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2641*/ GIMT_Encode4(85153), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3610 // |
| 30795 | /* 85109 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30796 | /* 85113 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30797 | /* 85117 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30798 | /* 85121 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30799 | /* 85125 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30800 | /* 85125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas8), |
| 30801 | /* 85128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30802 | /* 85130 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30803 | /* 85132 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30804 | /* 85134 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30805 | /* 85136 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30806 | /* 85139 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30807 | /* 85145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30808 | /* 85151 */ GIR_RootConstrainSelectedInstOperands, |
| 30809 | /* 85152 */ // GIR_Coverage, 3610, |
| 30810 | /* 85152 */ GIR_EraseRootFromParent_Done, |
| 30811 | /* 85153 */ // Label 2641: @85153 |
| 30812 | /* 85153 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2642*/ GIMT_Encode4(85204), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3614 // |
| 30813 | /* 85160 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30814 | /* 85164 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30815 | /* 85168 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30816 | /* 85172 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30817 | /* 85176 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30818 | /* 85176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs8), |
| 30819 | /* 85179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30820 | /* 85181 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30821 | /* 85183 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30822 | /* 85185 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30823 | /* 85187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30824 | /* 85190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30825 | /* 85196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30826 | /* 85202 */ GIR_RootConstrainSelectedInstOperands, |
| 30827 | /* 85203 */ // GIR_Coverage, 3614, |
| 30828 | /* 85203 */ GIR_EraseRootFromParent_Done, |
| 30829 | /* 85204 */ // Label 2642: @85204 |
| 30830 | /* 85204 */ GIM_Reject, |
| 30831 | /* 85205 */ // Label 2640: @85205 |
| 30832 | /* 85205 */ GIM_Reject, |
| 30833 | /* 85206 */ // Label 2628: @85206 |
| 30834 | /* 85206 */ GIM_Reject, |
| 30835 | /* 85207 */ // Label 2625: @85207 |
| 30836 | /* 85207 */ GIM_Try, /*On fail goto*//*Label 2643*/ GIMT_Encode4(85792), |
| 30837 | /* 85212 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 30838 | /* 85215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30839 | /* 85219 */ GIM_Try, /*On fail goto*//*Label 2644*/ GIMT_Encode4(85331), |
| 30840 | /* 85224 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30841 | /* 85228 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30842 | /* 85232 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2645*/ GIMT_Encode4(85281), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3584 // |
| 30843 | /* 85239 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30844 | /* 85243 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30845 | /* 85247 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30846 | /* 85251 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30847 | /* 85255 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30848 | /* 85255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs16), |
| 30849 | /* 85258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30850 | /* 85260 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30851 | /* 85262 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30852 | /* 85264 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30853 | /* 85267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30854 | /* 85273 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30855 | /* 85279 */ GIR_RootConstrainSelectedInstOperands, |
| 30856 | /* 85280 */ // GIR_Coverage, 3584, |
| 30857 | /* 85280 */ GIR_EraseRootFromParent_Done, |
| 30858 | /* 85281 */ // Label 2645: @85281 |
| 30859 | /* 85281 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2646*/ GIMT_Encode4(85330), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3588 // |
| 30860 | /* 85288 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30861 | /* 85292 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30862 | /* 85296 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30863 | /* 85300 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30864 | /* 85304 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30865 | /* 85304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs16), |
| 30866 | /* 85307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30867 | /* 85309 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30868 | /* 85311 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30869 | /* 85313 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30870 | /* 85316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30871 | /* 85322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30872 | /* 85328 */ GIR_RootConstrainSelectedInstOperands, |
| 30873 | /* 85329 */ // GIR_Coverage, 3588, |
| 30874 | /* 85329 */ GIR_EraseRootFromParent_Done, |
| 30875 | /* 85330 */ // Label 2646: @85330 |
| 30876 | /* 85330 */ GIM_Reject, |
| 30877 | /* 85331 */ // Label 2644: @85331 |
| 30878 | /* 85331 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2647*/ GIMT_Encode4(85388), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3592 // |
| 30879 | /* 85338 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 30880 | /* 85342 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30881 | /* 85346 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30882 | /* 85350 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30883 | /* 85354 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30884 | /* 85358 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30885 | /* 85362 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVu16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30886 | /* 85362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16), |
| 30887 | /* 85365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30888 | /* 85367 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30889 | /* 85369 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30890 | /* 85371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30891 | /* 85374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30892 | /* 85380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30893 | /* 85386 */ GIR_RootConstrainSelectedInstOperands, |
| 30894 | /* 85387 */ // GIR_Coverage, 3592, |
| 30895 | /* 85387 */ GIR_EraseRootFromParent_Done, |
| 30896 | /* 85388 */ // Label 2647: @85388 |
| 30897 | /* 85388 */ GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(85500), |
| 30898 | /* 85393 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30899 | /* 85397 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 30900 | /* 85401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2649*/ GIMT_Encode4(85450), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3616 // |
| 30901 | /* 85408 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30902 | /* 85412 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30903 | /* 85416 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30904 | /* 85420 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30905 | /* 85424 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30906 | /* 85424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs16), |
| 30907 | /* 85427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30908 | /* 85429 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30909 | /* 85431 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30910 | /* 85433 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30911 | /* 85436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30912 | /* 85442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30913 | /* 85448 */ GIR_RootConstrainSelectedInstOperands, |
| 30914 | /* 85449 */ // GIR_Coverage, 3616, |
| 30915 | /* 85449 */ GIR_EraseRootFromParent_Done, |
| 30916 | /* 85450 */ // Label 2649: @85450 |
| 30917 | /* 85450 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2650*/ GIMT_Encode4(85499), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3620 // |
| 30918 | /* 85457 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30919 | /* 85461 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30920 | /* 85465 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30921 | /* 85469 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30922 | /* 85473 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30923 | /* 85473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs16), |
| 30924 | /* 85476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30925 | /* 85478 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30926 | /* 85480 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30927 | /* 85482 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30928 | /* 85485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30929 | /* 85491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30930 | /* 85497 */ GIR_RootConstrainSelectedInstOperands, |
| 30931 | /* 85498 */ // GIR_Coverage, 3620, |
| 30932 | /* 85498 */ GIR_EraseRootFromParent_Done, |
| 30933 | /* 85499 */ // Label 2650: @85499 |
| 30934 | /* 85499 */ GIM_Reject, |
| 30935 | /* 85500 */ // Label 2648: @85500 |
| 30936 | /* 85500 */ GIM_Try, /*On fail goto*//*Label 2651*/ GIMT_Encode4(85616), |
| 30937 | /* 85505 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30938 | /* 85509 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30939 | /* 85513 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2652*/ GIMT_Encode4(85564), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3586 // |
| 30940 | /* 85520 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30941 | /* 85524 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30942 | /* 85528 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30943 | /* 85532 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30944 | /* 85536 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30945 | /* 85536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas16), |
| 30946 | /* 85539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30947 | /* 85541 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30948 | /* 85543 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30949 | /* 85545 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30950 | /* 85547 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30951 | /* 85550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30952 | /* 85556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30953 | /* 85562 */ GIR_RootConstrainSelectedInstOperands, |
| 30954 | /* 85563 */ // GIR_Coverage, 3586, |
| 30955 | /* 85563 */ GIR_EraseRootFromParent_Done, |
| 30956 | /* 85564 */ // Label 2652: @85564 |
| 30957 | /* 85564 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2653*/ GIMT_Encode4(85615), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3590 // |
| 30958 | /* 85571 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30959 | /* 85575 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30960 | /* 85579 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30961 | /* 85583 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30962 | /* 85587 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30963 | /* 85587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs16), |
| 30964 | /* 85590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30965 | /* 85592 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30966 | /* 85594 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30967 | /* 85596 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30968 | /* 85598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30969 | /* 85601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30970 | /* 85607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30971 | /* 85613 */ GIR_RootConstrainSelectedInstOperands, |
| 30972 | /* 85614 */ // GIR_Coverage, 3590, |
| 30973 | /* 85614 */ GIR_EraseRootFromParent_Done, |
| 30974 | /* 85615 */ // Label 2653: @85615 |
| 30975 | /* 85615 */ GIM_Reject, |
| 30976 | /* 85616 */ // Label 2651: @85616 |
| 30977 | /* 85616 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2654*/ GIMT_Encode4(85675), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3594 // |
| 30978 | /* 85623 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 30979 | /* 85627 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30980 | /* 85631 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30981 | /* 85635 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30982 | /* 85639 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30983 | /* 85643 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30984 | /* 85647 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVau16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30985 | /* 85647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16), |
| 30986 | /* 85650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30987 | /* 85652 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30988 | /* 85654 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30989 | /* 85656 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30990 | /* 85658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30991 | /* 85661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30992 | /* 85667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30993 | /* 85673 */ GIR_RootConstrainSelectedInstOperands, |
| 30994 | /* 85674 */ // GIR_Coverage, 3594, |
| 30995 | /* 85674 */ GIR_EraseRootFromParent_Done, |
| 30996 | /* 85675 */ // Label 2654: @85675 |
| 30997 | /* 85675 */ GIM_Try, /*On fail goto*//*Label 2655*/ GIMT_Encode4(85791), |
| 30998 | /* 85680 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30999 | /* 85684 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 31000 | /* 85688 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2656*/ GIMT_Encode4(85739), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3618 // |
| 31001 | /* 85695 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31002 | /* 85699 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 31003 | /* 85703 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31004 | /* 85707 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31005 | /* 85711 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 31006 | /* 85711 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas16), |
| 31007 | /* 85714 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31008 | /* 85716 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 31009 | /* 85718 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31010 | /* 85720 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31011 | /* 85722 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31012 | /* 85725 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31013 | /* 85731 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31014 | /* 85737 */ GIR_RootConstrainSelectedInstOperands, |
| 31015 | /* 85738 */ // GIR_Coverage, 3618, |
| 31016 | /* 85738 */ GIR_EraseRootFromParent_Done, |
| 31017 | /* 85739 */ // Label 2656: @85739 |
| 31018 | /* 85739 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2657*/ GIMT_Encode4(85790), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3622 // |
| 31019 | /* 85746 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31020 | /* 85750 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 31021 | /* 85754 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31022 | /* 85758 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31023 | /* 85762 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 31024 | /* 85762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs16), |
| 31025 | /* 85765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31026 | /* 85767 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 31027 | /* 85769 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31028 | /* 85771 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31029 | /* 85773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31030 | /* 85776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31031 | /* 85782 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31032 | /* 85788 */ GIR_RootConstrainSelectedInstOperands, |
| 31033 | /* 85789 */ // GIR_Coverage, 3622, |
| 31034 | /* 85789 */ GIR_EraseRootFromParent_Done, |
| 31035 | /* 85790 */ // Label 2657: @85790 |
| 31036 | /* 85790 */ GIM_Reject, |
| 31037 | /* 85791 */ // Label 2655: @85791 |
| 31038 | /* 85791 */ GIM_Reject, |
| 31039 | /* 85792 */ // Label 2643: @85792 |
| 31040 | /* 85792 */ GIM_Reject, |
| 31041 | /* 85793 */ // Label 2626: @85793 |
| 31042 | /* 85793 */ GIM_Try, /*On fail goto*//*Label 2658*/ GIMT_Encode4(86378), |
| 31043 | /* 85798 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 31044 | /* 85801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 31045 | /* 85805 */ GIM_Try, /*On fail goto*//*Label 2659*/ GIMT_Encode4(85917), |
| 31046 | /* 85810 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 31047 | /* 85814 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 31048 | /* 85818 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2660*/ GIMT_Encode4(85867), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3596 // |
| 31049 | /* 85825 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31050 | /* 85829 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31051 | /* 85833 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31052 | /* 85837 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31053 | /* 85841 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31054 | /* 85841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs32), |
| 31055 | /* 85844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31056 | /* 85846 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31057 | /* 85848 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31058 | /* 85850 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31059 | /* 85853 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31060 | /* 85859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31061 | /* 85865 */ GIR_RootConstrainSelectedInstOperands, |
| 31062 | /* 85866 */ // GIR_Coverage, 3596, |
| 31063 | /* 85866 */ GIR_EraseRootFromParent_Done, |
| 31064 | /* 85867 */ // Label 2660: @85867 |
| 31065 | /* 85867 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2661*/ GIMT_Encode4(85916), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3600 // |
| 31066 | /* 85874 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31067 | /* 85878 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31068 | /* 85882 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31069 | /* 85886 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31070 | /* 85890 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31071 | /* 85890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs32), |
| 31072 | /* 85893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31073 | /* 85895 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31074 | /* 85897 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31075 | /* 85899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31076 | /* 85902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31077 | /* 85908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31078 | /* 85914 */ GIR_RootConstrainSelectedInstOperands, |
| 31079 | /* 85915 */ // GIR_Coverage, 3600, |
| 31080 | /* 85915 */ GIR_EraseRootFromParent_Done, |
| 31081 | /* 85916 */ // Label 2661: @85916 |
| 31082 | /* 85916 */ GIM_Reject, |
| 31083 | /* 85917 */ // Label 2659: @85917 |
| 31084 | /* 85917 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2662*/ GIMT_Encode4(85974), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3604 // |
| 31085 | /* 85924 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 31086 | /* 85928 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 31087 | /* 85932 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31088 | /* 85936 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31089 | /* 85940 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31090 | /* 85944 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31091 | /* 85948 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVu32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31092 | /* 85948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32), |
| 31093 | /* 85951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31094 | /* 85953 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31095 | /* 85955 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31096 | /* 85957 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31097 | /* 85960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31098 | /* 85966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31099 | /* 85972 */ GIR_RootConstrainSelectedInstOperands, |
| 31100 | /* 85973 */ // GIR_Coverage, 3604, |
| 31101 | /* 85973 */ GIR_EraseRootFromParent_Done, |
| 31102 | /* 85974 */ // Label 2662: @85974 |
| 31103 | /* 85974 */ GIM_Try, /*On fail goto*//*Label 2663*/ GIMT_Encode4(86086), |
| 31104 | /* 85979 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 31105 | /* 85983 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 31106 | /* 85987 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2664*/ GIMT_Encode4(86036), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3624 // |
| 31107 | /* 85994 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31108 | /* 85998 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31109 | /* 86002 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31110 | /* 86006 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31111 | /* 86010 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31112 | /* 86010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs32), |
| 31113 | /* 86013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31114 | /* 86015 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31115 | /* 86017 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31116 | /* 86019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31117 | /* 86022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31118 | /* 86028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31119 | /* 86034 */ GIR_RootConstrainSelectedInstOperands, |
| 31120 | /* 86035 */ // GIR_Coverage, 3624, |
| 31121 | /* 86035 */ GIR_EraseRootFromParent_Done, |
| 31122 | /* 86036 */ // Label 2664: @86036 |
| 31123 | /* 86036 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2665*/ GIMT_Encode4(86085), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3628 // |
| 31124 | /* 86043 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31125 | /* 86047 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31126 | /* 86051 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31127 | /* 86055 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31128 | /* 86059 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31129 | /* 86059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs32), |
| 31130 | /* 86062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31131 | /* 86064 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31132 | /* 86066 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31133 | /* 86068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31134 | /* 86071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31135 | /* 86077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31136 | /* 86083 */ GIR_RootConstrainSelectedInstOperands, |
| 31137 | /* 86084 */ // GIR_Coverage, 3628, |
| 31138 | /* 86084 */ GIR_EraseRootFromParent_Done, |
| 31139 | /* 86085 */ // Label 2665: @86085 |
| 31140 | /* 86085 */ GIM_Reject, |
| 31141 | /* 86086 */ // Label 2663: @86086 |
| 31142 | /* 86086 */ GIM_Try, /*On fail goto*//*Label 2666*/ GIMT_Encode4(86202), |
| 31143 | /* 86091 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 31144 | /* 86095 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 31145 | /* 86099 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2667*/ GIMT_Encode4(86150), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3598 // |
| 31146 | /* 86106 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31147 | /* 86110 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 31148 | /* 86114 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31149 | /* 86118 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31150 | /* 86122 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31151 | /* 86122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas32), |
| 31152 | /* 86125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31153 | /* 86127 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 31154 | /* 86129 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31155 | /* 86131 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31156 | /* 86133 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31157 | /* 86136 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31158 | /* 86142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31159 | /* 86148 */ GIR_RootConstrainSelectedInstOperands, |
| 31160 | /* 86149 */ // GIR_Coverage, 3598, |
| 31161 | /* 86149 */ GIR_EraseRootFromParent_Done, |
| 31162 | /* 86150 */ // Label 2667: @86150 |
| 31163 | /* 86150 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2668*/ GIMT_Encode4(86201), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3602 // |
| 31164 | /* 86157 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31165 | /* 86161 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 31166 | /* 86165 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31167 | /* 86169 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31168 | /* 86173 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31169 | /* 86173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs32), |
| 31170 | /* 86176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31171 | /* 86178 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 31172 | /* 86180 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31173 | /* 86182 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31174 | /* 86184 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31175 | /* 86187 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31176 | /* 86193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31177 | /* 86199 */ GIR_RootConstrainSelectedInstOperands, |
| 31178 | /* 86200 */ // GIR_Coverage, 3602, |
| 31179 | /* 86200 */ GIR_EraseRootFromParent_Done, |
| 31180 | /* 86201 */ // Label 2668: @86201 |
| 31181 | /* 86201 */ GIM_Reject, |
| 31182 | /* 86202 */ // Label 2666: @86202 |
| 31183 | /* 86202 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2669*/ GIMT_Encode4(86261), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3606 // |
| 31184 | /* 86209 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 31185 | /* 86213 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 31186 | /* 86217 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31187 | /* 86221 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 31188 | /* 86225 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31189 | /* 86229 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31190 | /* 86233 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVau32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31191 | /* 86233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32), |
| 31192 | /* 86236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31193 | /* 86238 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 31194 | /* 86240 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31195 | /* 86242 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31196 | /* 86244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31197 | /* 86247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31198 | /* 86253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31199 | /* 86259 */ GIR_RootConstrainSelectedInstOperands, |
| 31200 | /* 86260 */ // GIR_Coverage, 3606, |
| 31201 | /* 86260 */ GIR_EraseRootFromParent_Done, |
| 31202 | /* 86261 */ // Label 2669: @86261 |
| 31203 | /* 86261 */ GIM_Try, /*On fail goto*//*Label 2670*/ GIMT_Encode4(86377), |
| 31204 | /* 86266 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 31205 | /* 86270 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 31206 | /* 86274 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2671*/ GIMT_Encode4(86325), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3626 // |
| 31207 | /* 86281 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31208 | /* 86285 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 31209 | /* 86289 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31210 | /* 86293 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31211 | /* 86297 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31212 | /* 86297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas32), |
| 31213 | /* 86300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31214 | /* 86302 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 31215 | /* 86304 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31216 | /* 86306 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31217 | /* 86308 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31218 | /* 86311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31219 | /* 86317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31220 | /* 86323 */ GIR_RootConstrainSelectedInstOperands, |
| 31221 | /* 86324 */ // GIR_Coverage, 3626, |
| 31222 | /* 86324 */ GIR_EraseRootFromParent_Done, |
| 31223 | /* 86325 */ // Label 2671: @86325 |
| 31224 | /* 86325 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2672*/ GIMT_Encode4(86376), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3630 // |
| 31225 | /* 86332 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31226 | /* 86336 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 31227 | /* 86340 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31228 | /* 86344 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31229 | /* 86348 */ // (intrinsic_wo_chain:{ *:[i32] } 3882:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31230 | /* 86348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs32), |
| 31231 | /* 86351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31232 | /* 86353 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 31233 | /* 86355 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31234 | /* 86357 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31235 | /* 86359 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31236 | /* 86362 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31237 | /* 86368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31238 | /* 86374 */ GIR_RootConstrainSelectedInstOperands, |
| 31239 | /* 86375 */ // GIR_Coverage, 3630, |
| 31240 | /* 86375 */ GIR_EraseRootFromParent_Done, |
| 31241 | /* 86376 */ // Label 2672: @86376 |
| 31242 | /* 86376 */ GIM_Reject, |
| 31243 | /* 86377 */ // Label 2670: @86377 |
| 31244 | /* 86377 */ GIM_Reject, |
| 31245 | /* 86378 */ // Label 2658: @86378 |
| 31246 | /* 86378 */ GIM_Reject, |
| 31247 | /* 86379 */ // Label 2627: @86379 |
| 31248 | /* 86379 */ GIM_Reject, |
| 31249 | /* 86380 */ // Label 2623: @86380 |
| 31250 | /* 86380 */ GIM_Try, /*On fail goto*//*Label 2673*/ GIMT_Encode4(87625), |
| 31251 | /* 86385 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 31252 | /* 86390 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2677*/ GIMT_Encode4(87624), |
| 31253 | /* 86401 */ /*GILLT_v16s8*//*Label 2674*/ GIMT_Encode4(86421), GIMT_Encode4(0), |
| 31254 | /* 86409 */ /*GILLT_v8s16*//*Label 2675*/ GIMT_Encode4(86822), GIMT_Encode4(0), |
| 31255 | /* 86417 */ /*GILLT_v4s32*//*Label 2676*/ GIMT_Encode4(87223), |
| 31256 | /* 86421 */ // Label 2674: @86421 |
| 31257 | /* 86421 */ GIM_Try, /*On fail goto*//*Label 2678*/ GIMT_Encode4(86821), |
| 31258 | /* 86426 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31259 | /* 86429 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 31260 | /* 86432 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 31261 | /* 86435 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31262 | /* 86438 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31263 | /* 86441 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31264 | /* 86444 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31265 | /* 86448 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31266 | /* 86452 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31267 | /* 86456 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31268 | /* 86460 */ GIM_Try, /*On fail goto*//*Label 2679*/ GIMT_Encode4(86505), // Rule ID 4846 // |
| 31269 | /* 86465 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31270 | /* 86469 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31271 | /* 86473 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31272 | /* 86477 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3892:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31273 | /* 86477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs8), |
| 31274 | /* 86480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31275 | /* 86482 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31276 | /* 86484 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31277 | /* 86486 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31278 | /* 86488 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31279 | /* 86491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31280 | /* 86497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31281 | /* 86503 */ GIR_RootConstrainSelectedInstOperands, |
| 31282 | /* 86504 */ // GIR_Coverage, 4846, |
| 31283 | /* 86504 */ GIR_EraseRootFromParent_Done, |
| 31284 | /* 86505 */ // Label 2679: @86505 |
| 31285 | /* 86505 */ GIM_Try, /*On fail goto*//*Label 2680*/ GIMT_Encode4(86550), // Rule ID 4852 // |
| 31286 | /* 86510 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31287 | /* 86514 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31288 | /* 86518 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31289 | /* 86522 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3892:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31290 | /* 86522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs8), |
| 31291 | /* 86525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31292 | /* 86527 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31293 | /* 86529 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31294 | /* 86531 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31295 | /* 86533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31296 | /* 86536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31297 | /* 86542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31298 | /* 86548 */ GIR_RootConstrainSelectedInstOperands, |
| 31299 | /* 86549 */ // GIR_Coverage, 4852, |
| 31300 | /* 86549 */ GIR_EraseRootFromParent_Done, |
| 31301 | /* 86550 */ // Label 2680: @86550 |
| 31302 | /* 86550 */ GIM_Try, /*On fail goto*//*Label 2681*/ GIMT_Encode4(86595), // Rule ID 4858 // |
| 31303 | /* 86555 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31304 | /* 86559 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31305 | /* 86563 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31306 | /* 86567 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3892:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31307 | /* 86567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs8), |
| 31308 | /* 86570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31309 | /* 86572 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31310 | /* 86574 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31311 | /* 86576 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31312 | /* 86578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31313 | /* 86581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31314 | /* 86587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31315 | /* 86593 */ GIR_RootConstrainSelectedInstOperands, |
| 31316 | /* 86594 */ // GIR_Coverage, 4858, |
| 31317 | /* 86594 */ GIR_EraseRootFromParent_Done, |
| 31318 | /* 86595 */ // Label 2681: @86595 |
| 31319 | /* 86595 */ GIM_Try, /*On fail goto*//*Label 2682*/ GIMT_Encode4(86640), // Rule ID 4864 // |
| 31320 | /* 86600 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31321 | /* 86604 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31322 | /* 86608 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31323 | /* 86612 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3892:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31324 | /* 86612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs8), |
| 31325 | /* 86615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31326 | /* 86617 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31327 | /* 86619 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31328 | /* 86621 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31329 | /* 86623 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31330 | /* 86626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31331 | /* 86632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31332 | /* 86638 */ GIR_RootConstrainSelectedInstOperands, |
| 31333 | /* 86639 */ // GIR_Coverage, 4864, |
| 31334 | /* 86639 */ GIR_EraseRootFromParent_Done, |
| 31335 | /* 86640 */ // Label 2682: @86640 |
| 31336 | /* 86640 */ GIM_Try, /*On fail goto*//*Label 2683*/ GIMT_Encode4(86685), // Rule ID 4870 // |
| 31337 | /* 86645 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31338 | /* 86649 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31339 | /* 86653 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31340 | /* 86657 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3892:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31341 | /* 86657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs8), |
| 31342 | /* 86660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31343 | /* 86662 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31344 | /* 86664 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31345 | /* 86666 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31346 | /* 86668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31347 | /* 86671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31348 | /* 86677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31349 | /* 86683 */ GIR_RootConstrainSelectedInstOperands, |
| 31350 | /* 86684 */ // GIR_Coverage, 4870, |
| 31351 | /* 86684 */ GIR_EraseRootFromParent_Done, |
| 31352 | /* 86685 */ // Label 2683: @86685 |
| 31353 | /* 86685 */ GIM_Try, /*On fail goto*//*Label 2684*/ GIMT_Encode4(86730), // Rule ID 4876 // |
| 31354 | /* 86690 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31355 | /* 86694 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31356 | /* 86698 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31357 | /* 86702 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3892:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31358 | /* 86702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs8), |
| 31359 | /* 86705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31360 | /* 86707 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31361 | /* 86709 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31362 | /* 86711 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31363 | /* 86713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31364 | /* 86716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31365 | /* 86722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31366 | /* 86728 */ GIR_RootConstrainSelectedInstOperands, |
| 31367 | /* 86729 */ // GIR_Coverage, 4876, |
| 31368 | /* 86729 */ GIR_EraseRootFromParent_Done, |
| 31369 | /* 86730 */ // Label 2684: @86730 |
| 31370 | /* 86730 */ GIM_Try, /*On fail goto*//*Label 2685*/ GIMT_Encode4(86775), // Rule ID 4882 // |
| 31371 | /* 86735 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31372 | /* 86739 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31373 | /* 86743 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31374 | /* 86747 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3892:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31375 | /* 86747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs8), |
| 31376 | /* 86750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31377 | /* 86752 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31378 | /* 86754 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31379 | /* 86756 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31380 | /* 86758 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31381 | /* 86761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31382 | /* 86767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31383 | /* 86773 */ GIR_RootConstrainSelectedInstOperands, |
| 31384 | /* 86774 */ // GIR_Coverage, 4882, |
| 31385 | /* 86774 */ GIR_EraseRootFromParent_Done, |
| 31386 | /* 86775 */ // Label 2685: @86775 |
| 31387 | /* 86775 */ GIM_Try, /*On fail goto*//*Label 2686*/ GIMT_Encode4(86820), // Rule ID 4888 // |
| 31388 | /* 86780 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31389 | /* 86784 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31390 | /* 86788 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31391 | /* 86792 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3892:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31392 | /* 86792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs8), |
| 31393 | /* 86795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31394 | /* 86797 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31395 | /* 86799 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31396 | /* 86801 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31397 | /* 86803 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31398 | /* 86806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31399 | /* 86812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31400 | /* 86818 */ GIR_RootConstrainSelectedInstOperands, |
| 31401 | /* 86819 */ // GIR_Coverage, 4888, |
| 31402 | /* 86819 */ GIR_EraseRootFromParent_Done, |
| 31403 | /* 86820 */ // Label 2686: @86820 |
| 31404 | /* 86820 */ GIM_Reject, |
| 31405 | /* 86821 */ // Label 2678: @86821 |
| 31406 | /* 86821 */ GIM_Reject, |
| 31407 | /* 86822 */ // Label 2675: @86822 |
| 31408 | /* 86822 */ GIM_Try, /*On fail goto*//*Label 2687*/ GIMT_Encode4(87222), |
| 31409 | /* 86827 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31410 | /* 86830 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31411 | /* 86833 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 31412 | /* 86836 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31413 | /* 86839 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31414 | /* 86842 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31415 | /* 86845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31416 | /* 86849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31417 | /* 86853 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31418 | /* 86857 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31419 | /* 86861 */ GIM_Try, /*On fail goto*//*Label 2688*/ GIMT_Encode4(86906), // Rule ID 4848 // |
| 31420 | /* 86866 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31421 | /* 86870 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31422 | /* 86874 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31423 | /* 86878 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3892:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31424 | /* 86878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs16), |
| 31425 | /* 86881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31426 | /* 86883 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31427 | /* 86885 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31428 | /* 86887 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31429 | /* 86889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31430 | /* 86892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31431 | /* 86898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31432 | /* 86904 */ GIR_RootConstrainSelectedInstOperands, |
| 31433 | /* 86905 */ // GIR_Coverage, 4848, |
| 31434 | /* 86905 */ GIR_EraseRootFromParent_Done, |
| 31435 | /* 86906 */ // Label 2688: @86906 |
| 31436 | /* 86906 */ GIM_Try, /*On fail goto*//*Label 2689*/ GIMT_Encode4(86951), // Rule ID 4854 // |
| 31437 | /* 86911 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31438 | /* 86915 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31439 | /* 86919 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31440 | /* 86923 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3892:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31441 | /* 86923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs16), |
| 31442 | /* 86926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31443 | /* 86928 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31444 | /* 86930 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31445 | /* 86932 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31446 | /* 86934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31447 | /* 86937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31448 | /* 86943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31449 | /* 86949 */ GIR_RootConstrainSelectedInstOperands, |
| 31450 | /* 86950 */ // GIR_Coverage, 4854, |
| 31451 | /* 86950 */ GIR_EraseRootFromParent_Done, |
| 31452 | /* 86951 */ // Label 2689: @86951 |
| 31453 | /* 86951 */ GIM_Try, /*On fail goto*//*Label 2690*/ GIMT_Encode4(86996), // Rule ID 4860 // |
| 31454 | /* 86956 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31455 | /* 86960 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31456 | /* 86964 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31457 | /* 86968 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3892:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31458 | /* 86968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs16), |
| 31459 | /* 86971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31460 | /* 86973 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31461 | /* 86975 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31462 | /* 86977 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31463 | /* 86979 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31464 | /* 86982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31465 | /* 86988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31466 | /* 86994 */ GIR_RootConstrainSelectedInstOperands, |
| 31467 | /* 86995 */ // GIR_Coverage, 4860, |
| 31468 | /* 86995 */ GIR_EraseRootFromParent_Done, |
| 31469 | /* 86996 */ // Label 2690: @86996 |
| 31470 | /* 86996 */ GIM_Try, /*On fail goto*//*Label 2691*/ GIMT_Encode4(87041), // Rule ID 4866 // |
| 31471 | /* 87001 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31472 | /* 87005 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31473 | /* 87009 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31474 | /* 87013 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3892:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31475 | /* 87013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs16), |
| 31476 | /* 87016 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31477 | /* 87018 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31478 | /* 87020 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31479 | /* 87022 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31480 | /* 87024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31481 | /* 87027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31482 | /* 87033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31483 | /* 87039 */ GIR_RootConstrainSelectedInstOperands, |
| 31484 | /* 87040 */ // GIR_Coverage, 4866, |
| 31485 | /* 87040 */ GIR_EraseRootFromParent_Done, |
| 31486 | /* 87041 */ // Label 2691: @87041 |
| 31487 | /* 87041 */ GIM_Try, /*On fail goto*//*Label 2692*/ GIMT_Encode4(87086), // Rule ID 4872 // |
| 31488 | /* 87046 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31489 | /* 87050 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31490 | /* 87054 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31491 | /* 87058 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3892:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31492 | /* 87058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs16), |
| 31493 | /* 87061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31494 | /* 87063 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31495 | /* 87065 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31496 | /* 87067 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31497 | /* 87069 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31498 | /* 87072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31499 | /* 87078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31500 | /* 87084 */ GIR_RootConstrainSelectedInstOperands, |
| 31501 | /* 87085 */ // GIR_Coverage, 4872, |
| 31502 | /* 87085 */ GIR_EraseRootFromParent_Done, |
| 31503 | /* 87086 */ // Label 2692: @87086 |
| 31504 | /* 87086 */ GIM_Try, /*On fail goto*//*Label 2693*/ GIMT_Encode4(87131), // Rule ID 4878 // |
| 31505 | /* 87091 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31506 | /* 87095 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31507 | /* 87099 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31508 | /* 87103 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3892:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31509 | /* 87103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs16), |
| 31510 | /* 87106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31511 | /* 87108 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31512 | /* 87110 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31513 | /* 87112 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31514 | /* 87114 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31515 | /* 87117 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31516 | /* 87123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31517 | /* 87129 */ GIR_RootConstrainSelectedInstOperands, |
| 31518 | /* 87130 */ // GIR_Coverage, 4878, |
| 31519 | /* 87130 */ GIR_EraseRootFromParent_Done, |
| 31520 | /* 87131 */ // Label 2693: @87131 |
| 31521 | /* 87131 */ GIM_Try, /*On fail goto*//*Label 2694*/ GIMT_Encode4(87176), // Rule ID 4884 // |
| 31522 | /* 87136 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31523 | /* 87140 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31524 | /* 87144 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31525 | /* 87148 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3892:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31526 | /* 87148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs16), |
| 31527 | /* 87151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31528 | /* 87153 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31529 | /* 87155 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31530 | /* 87157 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31531 | /* 87159 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31532 | /* 87162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31533 | /* 87168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31534 | /* 87174 */ GIR_RootConstrainSelectedInstOperands, |
| 31535 | /* 87175 */ // GIR_Coverage, 4884, |
| 31536 | /* 87175 */ GIR_EraseRootFromParent_Done, |
| 31537 | /* 87176 */ // Label 2694: @87176 |
| 31538 | /* 87176 */ GIM_Try, /*On fail goto*//*Label 2695*/ GIMT_Encode4(87221), // Rule ID 4890 // |
| 31539 | /* 87181 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31540 | /* 87185 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31541 | /* 87189 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31542 | /* 87193 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3892:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31543 | /* 87193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs16), |
| 31544 | /* 87196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31545 | /* 87198 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31546 | /* 87200 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31547 | /* 87202 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31548 | /* 87204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31549 | /* 87207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31550 | /* 87213 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31551 | /* 87219 */ GIR_RootConstrainSelectedInstOperands, |
| 31552 | /* 87220 */ // GIR_Coverage, 4890, |
| 31553 | /* 87220 */ GIR_EraseRootFromParent_Done, |
| 31554 | /* 87221 */ // Label 2695: @87221 |
| 31555 | /* 87221 */ GIM_Reject, |
| 31556 | /* 87222 */ // Label 2687: @87222 |
| 31557 | /* 87222 */ GIM_Reject, |
| 31558 | /* 87223 */ // Label 2676: @87223 |
| 31559 | /* 87223 */ GIM_Try, /*On fail goto*//*Label 2696*/ GIMT_Encode4(87623), |
| 31560 | /* 87228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31561 | /* 87231 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31562 | /* 87234 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 31563 | /* 87237 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31564 | /* 87240 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31565 | /* 87243 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31566 | /* 87246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31567 | /* 87250 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31568 | /* 87254 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31569 | /* 87258 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31570 | /* 87262 */ GIM_Try, /*On fail goto*//*Label 2697*/ GIMT_Encode4(87307), // Rule ID 4850 // |
| 31571 | /* 87267 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31572 | /* 87271 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31573 | /* 87275 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31574 | /* 87279 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3892:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31575 | /* 87279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs32), |
| 31576 | /* 87282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31577 | /* 87284 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31578 | /* 87286 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31579 | /* 87288 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31580 | /* 87290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31581 | /* 87293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31582 | /* 87299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31583 | /* 87305 */ GIR_RootConstrainSelectedInstOperands, |
| 31584 | /* 87306 */ // GIR_Coverage, 4850, |
| 31585 | /* 87306 */ GIR_EraseRootFromParent_Done, |
| 31586 | /* 87307 */ // Label 2697: @87307 |
| 31587 | /* 87307 */ GIM_Try, /*On fail goto*//*Label 2698*/ GIMT_Encode4(87352), // Rule ID 4856 // |
| 31588 | /* 87312 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31589 | /* 87316 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31590 | /* 87320 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31591 | /* 87324 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3892:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31592 | /* 87324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs32), |
| 31593 | /* 87327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31594 | /* 87329 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31595 | /* 87331 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31596 | /* 87333 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31597 | /* 87335 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31598 | /* 87338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31599 | /* 87344 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31600 | /* 87350 */ GIR_RootConstrainSelectedInstOperands, |
| 31601 | /* 87351 */ // GIR_Coverage, 4856, |
| 31602 | /* 87351 */ GIR_EraseRootFromParent_Done, |
| 31603 | /* 87352 */ // Label 2698: @87352 |
| 31604 | /* 87352 */ GIM_Try, /*On fail goto*//*Label 2699*/ GIMT_Encode4(87397), // Rule ID 4862 // |
| 31605 | /* 87357 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31606 | /* 87361 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31607 | /* 87365 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31608 | /* 87369 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3892:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31609 | /* 87369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs32), |
| 31610 | /* 87372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31611 | /* 87374 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31612 | /* 87376 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31613 | /* 87378 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31614 | /* 87380 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31615 | /* 87383 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31616 | /* 87389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31617 | /* 87395 */ GIR_RootConstrainSelectedInstOperands, |
| 31618 | /* 87396 */ // GIR_Coverage, 4862, |
| 31619 | /* 87396 */ GIR_EraseRootFromParent_Done, |
| 31620 | /* 87397 */ // Label 2699: @87397 |
| 31621 | /* 87397 */ GIM_Try, /*On fail goto*//*Label 2700*/ GIMT_Encode4(87442), // Rule ID 4868 // |
| 31622 | /* 87402 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31623 | /* 87406 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31624 | /* 87410 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31625 | /* 87414 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3892:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31626 | /* 87414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs32), |
| 31627 | /* 87417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31628 | /* 87419 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31629 | /* 87421 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31630 | /* 87423 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31631 | /* 87425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31632 | /* 87428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31633 | /* 87434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31634 | /* 87440 */ GIR_RootConstrainSelectedInstOperands, |
| 31635 | /* 87441 */ // GIR_Coverage, 4868, |
| 31636 | /* 87441 */ GIR_EraseRootFromParent_Done, |
| 31637 | /* 87442 */ // Label 2700: @87442 |
| 31638 | /* 87442 */ GIM_Try, /*On fail goto*//*Label 2701*/ GIMT_Encode4(87487), // Rule ID 4874 // |
| 31639 | /* 87447 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31640 | /* 87451 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31641 | /* 87455 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31642 | /* 87459 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3892:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31643 | /* 87459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs32), |
| 31644 | /* 87462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31645 | /* 87464 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31646 | /* 87466 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31647 | /* 87468 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31648 | /* 87470 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31649 | /* 87473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31650 | /* 87479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31651 | /* 87485 */ GIR_RootConstrainSelectedInstOperands, |
| 31652 | /* 87486 */ // GIR_Coverage, 4874, |
| 31653 | /* 87486 */ GIR_EraseRootFromParent_Done, |
| 31654 | /* 87487 */ // Label 2701: @87487 |
| 31655 | /* 87487 */ GIM_Try, /*On fail goto*//*Label 2702*/ GIMT_Encode4(87532), // Rule ID 4880 // |
| 31656 | /* 87492 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31657 | /* 87496 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31658 | /* 87500 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31659 | /* 87504 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3892:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31660 | /* 87504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs32), |
| 31661 | /* 87507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31662 | /* 87509 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31663 | /* 87511 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31664 | /* 87513 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31665 | /* 87515 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31666 | /* 87518 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31667 | /* 87524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31668 | /* 87530 */ GIR_RootConstrainSelectedInstOperands, |
| 31669 | /* 87531 */ // GIR_Coverage, 4880, |
| 31670 | /* 87531 */ GIR_EraseRootFromParent_Done, |
| 31671 | /* 87532 */ // Label 2702: @87532 |
| 31672 | /* 87532 */ GIM_Try, /*On fail goto*//*Label 2703*/ GIMT_Encode4(87577), // Rule ID 4886 // |
| 31673 | /* 87537 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31674 | /* 87541 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31675 | /* 87545 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31676 | /* 87549 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3892:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31677 | /* 87549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs32), |
| 31678 | /* 87552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31679 | /* 87554 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31680 | /* 87556 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31681 | /* 87558 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31682 | /* 87560 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31683 | /* 87563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31684 | /* 87569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31685 | /* 87575 */ GIR_RootConstrainSelectedInstOperands, |
| 31686 | /* 87576 */ // GIR_Coverage, 4886, |
| 31687 | /* 87576 */ GIR_EraseRootFromParent_Done, |
| 31688 | /* 87577 */ // Label 2703: @87577 |
| 31689 | /* 87577 */ GIM_Try, /*On fail goto*//*Label 2704*/ GIMT_Encode4(87622), // Rule ID 4892 // |
| 31690 | /* 87582 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31691 | /* 87586 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31692 | /* 87590 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31693 | /* 87594 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3892:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31694 | /* 87594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs32), |
| 31695 | /* 87597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31696 | /* 87599 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31697 | /* 87601 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31698 | /* 87603 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31699 | /* 87605 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31700 | /* 87608 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31701 | /* 87614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31702 | /* 87620 */ GIR_RootConstrainSelectedInstOperands, |
| 31703 | /* 87621 */ // GIR_Coverage, 4892, |
| 31704 | /* 87621 */ GIR_EraseRootFromParent_Done, |
| 31705 | /* 87622 */ // Label 2704: @87622 |
| 31706 | /* 87622 */ GIM_Reject, |
| 31707 | /* 87623 */ // Label 2696: @87623 |
| 31708 | /* 87623 */ GIM_Reject, |
| 31709 | /* 87624 */ // Label 2677: @87624 |
| 31710 | /* 87624 */ GIM_Reject, |
| 31711 | /* 87625 */ // Label 2673: @87625 |
| 31712 | /* 87625 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2705*/ GIMT_Encode4(87750), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3081 // |
| 31713 | /* 87632 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx4), |
| 31714 | /* 87637 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 31715 | /* 87640 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 31716 | /* 87643 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 31717 | /* 87646 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 31718 | /* 87649 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 31719 | /* 87652 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8, |
| 31720 | /* 87655 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s8, |
| 31721 | /* 87658 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 31722 | /* 87662 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4094:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBX4Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 31723 | /* 87662 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 31724 | /* 87665 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 31725 | /* 87669 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 31726 | /* 87674 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 |
| 31727 | /* 87678 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 31728 | /* 87681 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 |
| 31729 | /* 87685 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 31730 | /* 87688 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2 |
| 31731 | /* 87692 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 31732 | /* 87695 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // Vn3 |
| 31733 | /* 87699 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 31734 | /* 87702 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 31735 | /* 87707 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 31736 | /* 87712 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 31737 | /* 87717 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 31738 | /* 87722 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 31739 | /* 87727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX4Pseudo), |
| 31740 | /* 87730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 31741 | /* 87732 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 31742 | /* 87734 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 31743 | /* 87737 */ GIR_RootToRootCopy, /*OpIdx*/7, // Vm |
| 31744 | /* 87739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 31745 | /* 87742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31746 | /* 87748 */ GIR_RootConstrainSelectedInstOperands, |
| 31747 | /* 87749 */ // GIR_Coverage, 3081, |
| 31748 | /* 87749 */ GIR_EraseRootFromParent_Done, |
| 31749 | /* 87750 */ // Label 2705: @87750 |
| 31750 | /* 87750 */ GIM_Reject, |
| 31751 | /* 87751 */ // Label 2622: @87751 |
| 31752 | /* 87751 */ GIM_Try, /*On fail goto*//*Label 2706*/ GIMT_Encode4(90370), |
| 31753 | /* 87756 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/10, |
| 31754 | /* 87759 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshrn), |
| 31755 | /* 87764 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 2709*/ GIMT_Encode4(90369), |
| 31756 | /* 87775 */ /*GILLT_v16s8*//*Label 2707*/ GIMT_Encode4(87787), GIMT_Encode4(0), |
| 31757 | /* 87783 */ /*GILLT_v8s16*//*Label 2708*/ GIMT_Encode4(89078), |
| 31758 | /* 87787 */ // Label 2707: @87787 |
| 31759 | /* 87787 */ GIM_Try, /*On fail goto*//*Label 2710*/ GIMT_Encode4(89077), |
| 31760 | /* 87792 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31761 | /* 87795 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31762 | /* 87798 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31763 | /* 87801 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31764 | /* 87804 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31765 | /* 87807 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31766 | /* 87810 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31767 | /* 87813 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31768 | /* 87816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31769 | /* 87820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31770 | /* 87824 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31771 | /* 87828 */ GIM_Try, /*On fail goto*//*Label 2711*/ GIMT_Encode4(88330), |
| 31772 | /* 87833 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31773 | /* 87837 */ GIM_Try, /*On fail goto*//*Label 2712*/ GIMT_Encode4(88083), |
| 31774 | /* 87842 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31775 | /* 87846 */ GIM_Try, /*On fail goto*//*Label 2713*/ GIMT_Encode4(87964), |
| 31776 | /* 87851 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31777 | /* 87855 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31778 | /* 87859 */ GIM_Try, /*On fail goto*//*Label 2714*/ GIMT_Encode4(87911), // Rule ID 4161 // |
| 31779 | /* 87864 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31780 | /* 87868 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31781 | /* 87872 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31782 | /* 87876 */ // MIs[1] Operand 1 |
| 31783 | /* 87876 */ // No operand predicates |
| 31784 | /* 87876 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31785 | /* 87880 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31786 | /* 87882 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31787 | /* 87882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh), |
| 31788 | /* 87885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31789 | /* 87887 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31790 | /* 87889 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31791 | /* 87891 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31792 | /* 87894 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31793 | /* 87897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31794 | /* 87903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31795 | /* 87909 */ GIR_RootConstrainSelectedInstOperands, |
| 31796 | /* 87910 */ // GIR_Coverage, 4161, |
| 31797 | /* 87910 */ GIR_EraseRootFromParent_Done, |
| 31798 | /* 87911 */ // Label 2714: @87911 |
| 31799 | /* 87911 */ GIM_Try, /*On fail goto*//*Label 2715*/ GIMT_Encode4(87963), // Rule ID 4163 // |
| 31800 | /* 87916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31801 | /* 87920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31802 | /* 87924 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31803 | /* 87928 */ // MIs[1] Operand 1 |
| 31804 | /* 87928 */ // No operand predicates |
| 31805 | /* 87928 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31806 | /* 87932 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31807 | /* 87934 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31808 | /* 87934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th), |
| 31809 | /* 87937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31810 | /* 87939 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31811 | /* 87941 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31812 | /* 87943 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31813 | /* 87946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31814 | /* 87949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31815 | /* 87955 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31816 | /* 87961 */ GIR_RootConstrainSelectedInstOperands, |
| 31817 | /* 87962 */ // GIR_Coverage, 4163, |
| 31818 | /* 87962 */ GIR_EraseRootFromParent_Done, |
| 31819 | /* 87963 */ // Label 2715: @87963 |
| 31820 | /* 87963 */ GIM_Reject, |
| 31821 | /* 87964 */ // Label 2713: @87964 |
| 31822 | /* 87964 */ GIM_Try, /*On fail goto*//*Label 2716*/ GIMT_Encode4(88082), |
| 31823 | /* 87969 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31824 | /* 87973 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31825 | /* 87977 */ GIM_Try, /*On fail goto*//*Label 2717*/ GIMT_Encode4(88029), // Rule ID 4169 // |
| 31826 | /* 87982 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31827 | /* 87986 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31828 | /* 87990 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31829 | /* 87994 */ // MIs[1] Operand 1 |
| 31830 | /* 87994 */ // No operand predicates |
| 31831 | /* 87994 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31832 | /* 87998 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31833 | /* 88000 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31834 | /* 88000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh), |
| 31835 | /* 88003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31836 | /* 88005 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31837 | /* 88007 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31838 | /* 88009 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31839 | /* 88012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31840 | /* 88015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31841 | /* 88021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31842 | /* 88027 */ GIR_RootConstrainSelectedInstOperands, |
| 31843 | /* 88028 */ // GIR_Coverage, 4169, |
| 31844 | /* 88028 */ GIR_EraseRootFromParent_Done, |
| 31845 | /* 88029 */ // Label 2717: @88029 |
| 31846 | /* 88029 */ GIM_Try, /*On fail goto*//*Label 2718*/ GIMT_Encode4(88081), // Rule ID 4171 // |
| 31847 | /* 88034 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31848 | /* 88038 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31849 | /* 88042 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31850 | /* 88046 */ // MIs[1] Operand 1 |
| 31851 | /* 88046 */ // No operand predicates |
| 31852 | /* 88046 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31853 | /* 88050 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31854 | /* 88052 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31855 | /* 88052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th), |
| 31856 | /* 88055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31857 | /* 88057 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31858 | /* 88059 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31859 | /* 88061 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31860 | /* 88064 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31861 | /* 88067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31862 | /* 88073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31863 | /* 88079 */ GIR_RootConstrainSelectedInstOperands, |
| 31864 | /* 88080 */ // GIR_Coverage, 4171, |
| 31865 | /* 88080 */ GIR_EraseRootFromParent_Done, |
| 31866 | /* 88081 */ // Label 2718: @88081 |
| 31867 | /* 88081 */ GIM_Reject, |
| 31868 | /* 88082 */ // Label 2716: @88082 |
| 31869 | /* 88082 */ GIM_Reject, |
| 31870 | /* 88083 */ // Label 2712: @88083 |
| 31871 | /* 88083 */ GIM_Try, /*On fail goto*//*Label 2719*/ GIMT_Encode4(88329), |
| 31872 | /* 88088 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31873 | /* 88092 */ GIM_Try, /*On fail goto*//*Label 2720*/ GIMT_Encode4(88210), |
| 31874 | /* 88097 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31875 | /* 88101 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31876 | /* 88105 */ GIM_Try, /*On fail goto*//*Label 2721*/ GIMT_Encode4(88157), // Rule ID 4177 // |
| 31877 | /* 88110 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31878 | /* 88114 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31879 | /* 88118 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31880 | /* 88122 */ // MIs[1] Operand 1 |
| 31881 | /* 88122 */ // No operand predicates |
| 31882 | /* 88122 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31883 | /* 88126 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31884 | /* 88128 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31885 | /* 88128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh), |
| 31886 | /* 88131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31887 | /* 88133 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31888 | /* 88135 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31889 | /* 88137 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31890 | /* 88140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31891 | /* 88143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31892 | /* 88149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31893 | /* 88155 */ GIR_RootConstrainSelectedInstOperands, |
| 31894 | /* 88156 */ // GIR_Coverage, 4177, |
| 31895 | /* 88156 */ GIR_EraseRootFromParent_Done, |
| 31896 | /* 88157 */ // Label 2721: @88157 |
| 31897 | /* 88157 */ GIM_Try, /*On fail goto*//*Label 2722*/ GIMT_Encode4(88209), // Rule ID 4179 // |
| 31898 | /* 88162 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31899 | /* 88166 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31900 | /* 88170 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31901 | /* 88174 */ // MIs[1] Operand 1 |
| 31902 | /* 88174 */ // No operand predicates |
| 31903 | /* 88174 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31904 | /* 88178 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31905 | /* 88180 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31906 | /* 88180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th), |
| 31907 | /* 88183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31908 | /* 88185 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31909 | /* 88187 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31910 | /* 88189 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31911 | /* 88192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31912 | /* 88195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31913 | /* 88201 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31914 | /* 88207 */ GIR_RootConstrainSelectedInstOperands, |
| 31915 | /* 88208 */ // GIR_Coverage, 4179, |
| 31916 | /* 88208 */ GIR_EraseRootFromParent_Done, |
| 31917 | /* 88209 */ // Label 2722: @88209 |
| 31918 | /* 88209 */ GIM_Reject, |
| 31919 | /* 88210 */ // Label 2720: @88210 |
| 31920 | /* 88210 */ GIM_Try, /*On fail goto*//*Label 2723*/ GIMT_Encode4(88328), |
| 31921 | /* 88215 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31922 | /* 88219 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31923 | /* 88223 */ GIM_Try, /*On fail goto*//*Label 2724*/ GIMT_Encode4(88275), // Rule ID 4185 // |
| 31924 | /* 88228 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31925 | /* 88232 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31926 | /* 88236 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31927 | /* 88240 */ // MIs[1] Operand 1 |
| 31928 | /* 88240 */ // No operand predicates |
| 31929 | /* 88240 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31930 | /* 88244 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31931 | /* 88246 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31932 | /* 88246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh), |
| 31933 | /* 88249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31934 | /* 88251 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31935 | /* 88253 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31936 | /* 88255 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31937 | /* 88258 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31938 | /* 88261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31939 | /* 88267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31940 | /* 88273 */ GIR_RootConstrainSelectedInstOperands, |
| 31941 | /* 88274 */ // GIR_Coverage, 4185, |
| 31942 | /* 88274 */ GIR_EraseRootFromParent_Done, |
| 31943 | /* 88275 */ // Label 2724: @88275 |
| 31944 | /* 88275 */ GIM_Try, /*On fail goto*//*Label 2725*/ GIMT_Encode4(88327), // Rule ID 4187 // |
| 31945 | /* 88280 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31946 | /* 88284 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31947 | /* 88288 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31948 | /* 88292 */ // MIs[1] Operand 1 |
| 31949 | /* 88292 */ // No operand predicates |
| 31950 | /* 88292 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31951 | /* 88296 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31952 | /* 88298 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31953 | /* 88298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th), |
| 31954 | /* 88301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31955 | /* 88303 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31956 | /* 88305 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31957 | /* 88307 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31958 | /* 88310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31959 | /* 88313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31960 | /* 88319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31961 | /* 88325 */ GIR_RootConstrainSelectedInstOperands, |
| 31962 | /* 88326 */ // GIR_Coverage, 4187, |
| 31963 | /* 88326 */ GIR_EraseRootFromParent_Done, |
| 31964 | /* 88327 */ // Label 2725: @88327 |
| 31965 | /* 88327 */ GIM_Reject, |
| 31966 | /* 88328 */ // Label 2723: @88328 |
| 31967 | /* 88328 */ GIM_Reject, |
| 31968 | /* 88329 */ // Label 2719: @88329 |
| 31969 | /* 88329 */ GIM_Reject, |
| 31970 | /* 88330 */ // Label 2711: @88330 |
| 31971 | /* 88330 */ GIM_Try, /*On fail goto*//*Label 2726*/ GIMT_Encode4(89076), |
| 31972 | /* 88335 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31973 | /* 88339 */ GIM_Try, /*On fail goto*//*Label 2727*/ GIMT_Encode4(88585), |
| 31974 | /* 88344 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31975 | /* 88348 */ GIM_Try, /*On fail goto*//*Label 2728*/ GIMT_Encode4(88466), |
| 31976 | /* 88353 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31977 | /* 88357 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31978 | /* 88361 */ GIM_Try, /*On fail goto*//*Label 2729*/ GIMT_Encode4(88413), // Rule ID 4193 // |
| 31979 | /* 88366 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31980 | /* 88370 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31981 | /* 88374 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31982 | /* 88378 */ // MIs[1] Operand 1 |
| 31983 | /* 88378 */ // No operand predicates |
| 31984 | /* 88378 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31985 | /* 88382 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31986 | /* 88384 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31987 | /* 88384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs16), |
| 31988 | /* 88387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31989 | /* 88389 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31990 | /* 88391 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31991 | /* 88393 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31992 | /* 88396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31993 | /* 88399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31994 | /* 88405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31995 | /* 88411 */ GIR_RootConstrainSelectedInstOperands, |
| 31996 | /* 88412 */ // GIR_Coverage, 4193, |
| 31997 | /* 88412 */ GIR_EraseRootFromParent_Done, |
| 31998 | /* 88413 */ // Label 2729: @88413 |
| 31999 | /* 88413 */ GIM_Try, /*On fail goto*//*Label 2730*/ GIMT_Encode4(88465), // Rule ID 4195 // |
| 32000 | /* 88418 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32001 | /* 88422 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32002 | /* 88426 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32003 | /* 88430 */ // MIs[1] Operand 1 |
| 32004 | /* 88430 */ // No operand predicates |
| 32005 | /* 88430 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32006 | /* 88434 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32007 | /* 88436 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32008 | /* 88436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths16), |
| 32009 | /* 88439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32010 | /* 88441 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32011 | /* 88443 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32012 | /* 88445 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32013 | /* 88448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32014 | /* 88451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32015 | /* 88457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32016 | /* 88463 */ GIR_RootConstrainSelectedInstOperands, |
| 32017 | /* 88464 */ // GIR_Coverage, 4195, |
| 32018 | /* 88464 */ GIR_EraseRootFromParent_Done, |
| 32019 | /* 88465 */ // Label 2730: @88465 |
| 32020 | /* 88465 */ GIM_Reject, |
| 32021 | /* 88466 */ // Label 2728: @88466 |
| 32022 | /* 88466 */ GIM_Try, /*On fail goto*//*Label 2731*/ GIMT_Encode4(88584), |
| 32023 | /* 88471 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32024 | /* 88475 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32025 | /* 88479 */ GIM_Try, /*On fail goto*//*Label 2732*/ GIMT_Encode4(88531), // Rule ID 4201 // |
| 32026 | /* 88484 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32027 | /* 88488 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32028 | /* 88492 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32029 | /* 88496 */ // MIs[1] Operand 1 |
| 32030 | /* 88496 */ // No operand predicates |
| 32031 | /* 88496 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32032 | /* 88500 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32033 | /* 88502 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32034 | /* 88502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu16), |
| 32035 | /* 88505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32036 | /* 88507 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32037 | /* 88509 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32038 | /* 88511 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32039 | /* 88514 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32040 | /* 88517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32041 | /* 88523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32042 | /* 88529 */ GIR_RootConstrainSelectedInstOperands, |
| 32043 | /* 88530 */ // GIR_Coverage, 4201, |
| 32044 | /* 88530 */ GIR_EraseRootFromParent_Done, |
| 32045 | /* 88531 */ // Label 2732: @88531 |
| 32046 | /* 88531 */ GIM_Try, /*On fail goto*//*Label 2733*/ GIMT_Encode4(88583), // Rule ID 4203 // |
| 32047 | /* 88536 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32048 | /* 88540 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32049 | /* 88544 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32050 | /* 88548 */ // MIs[1] Operand 1 |
| 32051 | /* 88548 */ // No operand predicates |
| 32052 | /* 88548 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32053 | /* 88552 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32054 | /* 88554 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32055 | /* 88554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu16), |
| 32056 | /* 88557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32057 | /* 88559 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32058 | /* 88561 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32059 | /* 88563 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32060 | /* 88566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32061 | /* 88569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32062 | /* 88575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32063 | /* 88581 */ GIR_RootConstrainSelectedInstOperands, |
| 32064 | /* 88582 */ // GIR_Coverage, 4203, |
| 32065 | /* 88582 */ GIR_EraseRootFromParent_Done, |
| 32066 | /* 88583 */ // Label 2733: @88583 |
| 32067 | /* 88583 */ GIM_Reject, |
| 32068 | /* 88584 */ // Label 2731: @88584 |
| 32069 | /* 88584 */ GIM_Reject, |
| 32070 | /* 88585 */ // Label 2727: @88585 |
| 32071 | /* 88585 */ GIM_Try, /*On fail goto*//*Label 2734*/ GIMT_Encode4(88831), |
| 32072 | /* 88590 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32073 | /* 88594 */ GIM_Try, /*On fail goto*//*Label 2735*/ GIMT_Encode4(88712), |
| 32074 | /* 88599 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 32075 | /* 88603 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32076 | /* 88607 */ GIM_Try, /*On fail goto*//*Label 2736*/ GIMT_Encode4(88659), // Rule ID 4209 // |
| 32077 | /* 88612 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32078 | /* 88616 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32079 | /* 88620 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32080 | /* 88624 */ // MIs[1] Operand 1 |
| 32081 | /* 88624 */ // No operand predicates |
| 32082 | /* 88624 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32083 | /* 88628 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32084 | /* 88630 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32085 | /* 88630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs16), |
| 32086 | /* 88633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32087 | /* 88635 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32088 | /* 88637 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32089 | /* 88639 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32090 | /* 88642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32091 | /* 88645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32092 | /* 88651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32093 | /* 88657 */ GIR_RootConstrainSelectedInstOperands, |
| 32094 | /* 88658 */ // GIR_Coverage, 4209, |
| 32095 | /* 88658 */ GIR_EraseRootFromParent_Done, |
| 32096 | /* 88659 */ // Label 2736: @88659 |
| 32097 | /* 88659 */ GIM_Try, /*On fail goto*//*Label 2737*/ GIMT_Encode4(88711), // Rule ID 4211 // |
| 32098 | /* 88664 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32099 | /* 88668 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32100 | /* 88672 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32101 | /* 88676 */ // MIs[1] Operand 1 |
| 32102 | /* 88676 */ // No operand predicates |
| 32103 | /* 88676 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32104 | /* 88680 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32105 | /* 88682 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32106 | /* 88682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths16), |
| 32107 | /* 88685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32108 | /* 88687 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32109 | /* 88689 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32110 | /* 88691 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32111 | /* 88694 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32112 | /* 88697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32113 | /* 88703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32114 | /* 88709 */ GIR_RootConstrainSelectedInstOperands, |
| 32115 | /* 88710 */ // GIR_Coverage, 4211, |
| 32116 | /* 88710 */ GIR_EraseRootFromParent_Done, |
| 32117 | /* 88711 */ // Label 2737: @88711 |
| 32118 | /* 88711 */ GIM_Reject, |
| 32119 | /* 88712 */ // Label 2735: @88712 |
| 32120 | /* 88712 */ GIM_Try, /*On fail goto*//*Label 2738*/ GIMT_Encode4(88830), |
| 32121 | /* 88717 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32122 | /* 88721 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32123 | /* 88725 */ GIM_Try, /*On fail goto*//*Label 2739*/ GIMT_Encode4(88777), // Rule ID 4217 // |
| 32124 | /* 88730 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32125 | /* 88734 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32126 | /* 88738 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32127 | /* 88742 */ // MIs[1] Operand 1 |
| 32128 | /* 88742 */ // No operand predicates |
| 32129 | /* 88742 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32130 | /* 88746 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32131 | /* 88748 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32132 | /* 88748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu16), |
| 32133 | /* 88751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32134 | /* 88753 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32135 | /* 88755 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32136 | /* 88757 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32137 | /* 88760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32138 | /* 88763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32139 | /* 88769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32140 | /* 88775 */ GIR_RootConstrainSelectedInstOperands, |
| 32141 | /* 88776 */ // GIR_Coverage, 4217, |
| 32142 | /* 88776 */ GIR_EraseRootFromParent_Done, |
| 32143 | /* 88777 */ // Label 2739: @88777 |
| 32144 | /* 88777 */ GIM_Try, /*On fail goto*//*Label 2740*/ GIMT_Encode4(88829), // Rule ID 4219 // |
| 32145 | /* 88782 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32146 | /* 88786 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32147 | /* 88790 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32148 | /* 88794 */ // MIs[1] Operand 1 |
| 32149 | /* 88794 */ // No operand predicates |
| 32150 | /* 88794 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32151 | /* 88798 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32152 | /* 88800 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32153 | /* 88800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu16), |
| 32154 | /* 88803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32155 | /* 88805 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32156 | /* 88807 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32157 | /* 88809 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32158 | /* 88812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32159 | /* 88815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32160 | /* 88821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32161 | /* 88827 */ GIR_RootConstrainSelectedInstOperands, |
| 32162 | /* 88828 */ // GIR_Coverage, 4219, |
| 32163 | /* 88828 */ GIR_EraseRootFromParent_Done, |
| 32164 | /* 88829 */ // Label 2740: @88829 |
| 32165 | /* 88829 */ GIM_Reject, |
| 32166 | /* 88830 */ // Label 2738: @88830 |
| 32167 | /* 88830 */ GIM_Reject, |
| 32168 | /* 88831 */ // Label 2734: @88831 |
| 32169 | /* 88831 */ GIM_Try, /*On fail goto*//*Label 2741*/ GIMT_Encode4(88953), |
| 32170 | /* 88836 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 32171 | /* 88840 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32172 | /* 88844 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32173 | /* 88848 */ GIM_Try, /*On fail goto*//*Label 2742*/ GIMT_Encode4(88900), // Rule ID 4225 // |
| 32174 | /* 88853 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32175 | /* 88857 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32176 | /* 88861 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32177 | /* 88865 */ // MIs[1] Operand 1 |
| 32178 | /* 88865 */ // No operand predicates |
| 32179 | /* 88865 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32180 | /* 88869 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32181 | /* 88871 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32182 | /* 88871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16bh), |
| 32183 | /* 88874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32184 | /* 88876 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32185 | /* 88878 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32186 | /* 88880 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32187 | /* 88883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32188 | /* 88886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32189 | /* 88892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32190 | /* 88898 */ GIR_RootConstrainSelectedInstOperands, |
| 32191 | /* 88899 */ // GIR_Coverage, 4225, |
| 32192 | /* 88899 */ GIR_EraseRootFromParent_Done, |
| 32193 | /* 88900 */ // Label 2742: @88900 |
| 32194 | /* 88900 */ GIM_Try, /*On fail goto*//*Label 2743*/ GIMT_Encode4(88952), // Rule ID 4227 // |
| 32195 | /* 88905 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32196 | /* 88909 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32197 | /* 88913 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32198 | /* 88917 */ // MIs[1] Operand 1 |
| 32199 | /* 88917 */ // No operand predicates |
| 32200 | /* 88917 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32201 | /* 88921 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32202 | /* 88923 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32203 | /* 88923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16th), |
| 32204 | /* 88926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32205 | /* 88928 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32206 | /* 88930 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32207 | /* 88932 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32208 | /* 88935 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32209 | /* 88938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32210 | /* 88944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32211 | /* 88950 */ GIR_RootConstrainSelectedInstOperands, |
| 32212 | /* 88951 */ // GIR_Coverage, 4227, |
| 32213 | /* 88951 */ GIR_EraseRootFromParent_Done, |
| 32214 | /* 88952 */ // Label 2743: @88952 |
| 32215 | /* 88952 */ GIM_Reject, |
| 32216 | /* 88953 */ // Label 2741: @88953 |
| 32217 | /* 88953 */ GIM_Try, /*On fail goto*//*Label 2744*/ GIMT_Encode4(89075), |
| 32218 | /* 88958 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32219 | /* 88962 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32220 | /* 88966 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32221 | /* 88970 */ GIM_Try, /*On fail goto*//*Label 2745*/ GIMT_Encode4(89022), // Rule ID 4233 // |
| 32222 | /* 88975 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32223 | /* 88979 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32224 | /* 88983 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32225 | /* 88987 */ // MIs[1] Operand 1 |
| 32226 | /* 88987 */ // No operand predicates |
| 32227 | /* 88987 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32228 | /* 88991 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32229 | /* 88993 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32230 | /* 88993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16bh), |
| 32231 | /* 88996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32232 | /* 88998 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32233 | /* 89000 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32234 | /* 89002 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32235 | /* 89005 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32236 | /* 89008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32237 | /* 89014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32238 | /* 89020 */ GIR_RootConstrainSelectedInstOperands, |
| 32239 | /* 89021 */ // GIR_Coverage, 4233, |
| 32240 | /* 89021 */ GIR_EraseRootFromParent_Done, |
| 32241 | /* 89022 */ // Label 2745: @89022 |
| 32242 | /* 89022 */ GIM_Try, /*On fail goto*//*Label 2746*/ GIMT_Encode4(89074), // Rule ID 4235 // |
| 32243 | /* 89027 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32244 | /* 89031 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32245 | /* 89035 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32246 | /* 89039 */ // MIs[1] Operand 1 |
| 32247 | /* 89039 */ // No operand predicates |
| 32248 | /* 89039 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32249 | /* 89043 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32250 | /* 89045 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32251 | /* 89045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16th), |
| 32252 | /* 89048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32253 | /* 89050 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32254 | /* 89052 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32255 | /* 89054 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32256 | /* 89057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32257 | /* 89060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32258 | /* 89066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32259 | /* 89072 */ GIR_RootConstrainSelectedInstOperands, |
| 32260 | /* 89073 */ // GIR_Coverage, 4235, |
| 32261 | /* 89073 */ GIR_EraseRootFromParent_Done, |
| 32262 | /* 89074 */ // Label 2746: @89074 |
| 32263 | /* 89074 */ GIM_Reject, |
| 32264 | /* 89075 */ // Label 2744: @89075 |
| 32265 | /* 89075 */ GIM_Reject, |
| 32266 | /* 89076 */ // Label 2726: @89076 |
| 32267 | /* 89076 */ GIM_Reject, |
| 32268 | /* 89077 */ // Label 2710: @89077 |
| 32269 | /* 89077 */ GIM_Reject, |
| 32270 | /* 89078 */ // Label 2708: @89078 |
| 32271 | /* 89078 */ GIM_Try, /*On fail goto*//*Label 2747*/ GIMT_Encode4(90368), |
| 32272 | /* 89083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 32273 | /* 89086 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 32274 | /* 89089 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32275 | /* 89092 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32276 | /* 89095 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32277 | /* 89098 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32278 | /* 89101 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32279 | /* 89104 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32280 | /* 89107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32281 | /* 89111 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32282 | /* 89115 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32283 | /* 89119 */ GIM_Try, /*On fail goto*//*Label 2748*/ GIMT_Encode4(89621), |
| 32284 | /* 89124 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32285 | /* 89128 */ GIM_Try, /*On fail goto*//*Label 2749*/ GIMT_Encode4(89374), |
| 32286 | /* 89133 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 32287 | /* 89137 */ GIM_Try, /*On fail goto*//*Label 2750*/ GIMT_Encode4(89255), |
| 32288 | /* 89142 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 32289 | /* 89146 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32290 | /* 89150 */ GIM_Try, /*On fail goto*//*Label 2751*/ GIMT_Encode4(89202), // Rule ID 4165 // |
| 32291 | /* 89155 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32292 | /* 89159 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32293 | /* 89163 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32294 | /* 89167 */ // MIs[1] Operand 1 |
| 32295 | /* 89167 */ // No operand predicates |
| 32296 | /* 89167 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32297 | /* 89171 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32298 | /* 89173 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32299 | /* 89173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh), |
| 32300 | /* 89176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32301 | /* 89178 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32302 | /* 89180 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32303 | /* 89182 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32304 | /* 89185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32305 | /* 89188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32306 | /* 89194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32307 | /* 89200 */ GIR_RootConstrainSelectedInstOperands, |
| 32308 | /* 89201 */ // GIR_Coverage, 4165, |
| 32309 | /* 89201 */ GIR_EraseRootFromParent_Done, |
| 32310 | /* 89202 */ // Label 2751: @89202 |
| 32311 | /* 89202 */ GIM_Try, /*On fail goto*//*Label 2752*/ GIMT_Encode4(89254), // Rule ID 4167 // |
| 32312 | /* 89207 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32313 | /* 89211 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32314 | /* 89215 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32315 | /* 89219 */ // MIs[1] Operand 1 |
| 32316 | /* 89219 */ // No operand predicates |
| 32317 | /* 89219 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32318 | /* 89223 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32319 | /* 89225 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32320 | /* 89225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th), |
| 32321 | /* 89228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32322 | /* 89230 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32323 | /* 89232 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32324 | /* 89234 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32325 | /* 89237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32326 | /* 89240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32327 | /* 89246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32328 | /* 89252 */ GIR_RootConstrainSelectedInstOperands, |
| 32329 | /* 89253 */ // GIR_Coverage, 4167, |
| 32330 | /* 89253 */ GIR_EraseRootFromParent_Done, |
| 32331 | /* 89254 */ // Label 2752: @89254 |
| 32332 | /* 89254 */ GIM_Reject, |
| 32333 | /* 89255 */ // Label 2750: @89255 |
| 32334 | /* 89255 */ GIM_Try, /*On fail goto*//*Label 2753*/ GIMT_Encode4(89373), |
| 32335 | /* 89260 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32336 | /* 89264 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32337 | /* 89268 */ GIM_Try, /*On fail goto*//*Label 2754*/ GIMT_Encode4(89320), // Rule ID 4173 // |
| 32338 | /* 89273 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32339 | /* 89277 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32340 | /* 89281 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32341 | /* 89285 */ // MIs[1] Operand 1 |
| 32342 | /* 89285 */ // No operand predicates |
| 32343 | /* 89285 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32344 | /* 89289 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32345 | /* 89291 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32346 | /* 89291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh), |
| 32347 | /* 89294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32348 | /* 89296 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32349 | /* 89298 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32350 | /* 89300 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32351 | /* 89303 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32352 | /* 89306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32353 | /* 89312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32354 | /* 89318 */ GIR_RootConstrainSelectedInstOperands, |
| 32355 | /* 89319 */ // GIR_Coverage, 4173, |
| 32356 | /* 89319 */ GIR_EraseRootFromParent_Done, |
| 32357 | /* 89320 */ // Label 2754: @89320 |
| 32358 | /* 89320 */ GIM_Try, /*On fail goto*//*Label 2755*/ GIMT_Encode4(89372), // Rule ID 4175 // |
| 32359 | /* 89325 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32360 | /* 89329 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32361 | /* 89333 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32362 | /* 89337 */ // MIs[1] Operand 1 |
| 32363 | /* 89337 */ // No operand predicates |
| 32364 | /* 89337 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32365 | /* 89341 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32366 | /* 89343 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32367 | /* 89343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th), |
| 32368 | /* 89346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32369 | /* 89348 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32370 | /* 89350 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32371 | /* 89352 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32372 | /* 89355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32373 | /* 89358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32374 | /* 89364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32375 | /* 89370 */ GIR_RootConstrainSelectedInstOperands, |
| 32376 | /* 89371 */ // GIR_Coverage, 4175, |
| 32377 | /* 89371 */ GIR_EraseRootFromParent_Done, |
| 32378 | /* 89372 */ // Label 2755: @89372 |
| 32379 | /* 89372 */ GIM_Reject, |
| 32380 | /* 89373 */ // Label 2753: @89373 |
| 32381 | /* 89373 */ GIM_Reject, |
| 32382 | /* 89374 */ // Label 2749: @89374 |
| 32383 | /* 89374 */ GIM_Try, /*On fail goto*//*Label 2756*/ GIMT_Encode4(89620), |
| 32384 | /* 89379 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32385 | /* 89383 */ GIM_Try, /*On fail goto*//*Label 2757*/ GIMT_Encode4(89501), |
| 32386 | /* 89388 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 32387 | /* 89392 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32388 | /* 89396 */ GIM_Try, /*On fail goto*//*Label 2758*/ GIMT_Encode4(89448), // Rule ID 4181 // |
| 32389 | /* 89401 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32390 | /* 89405 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32391 | /* 89409 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32392 | /* 89413 */ // MIs[1] Operand 1 |
| 32393 | /* 89413 */ // No operand predicates |
| 32394 | /* 89413 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32395 | /* 89417 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32396 | /* 89419 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32397 | /* 89419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh), |
| 32398 | /* 89422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32399 | /* 89424 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32400 | /* 89426 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32401 | /* 89428 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32402 | /* 89431 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32403 | /* 89434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32404 | /* 89440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32405 | /* 89446 */ GIR_RootConstrainSelectedInstOperands, |
| 32406 | /* 89447 */ // GIR_Coverage, 4181, |
| 32407 | /* 89447 */ GIR_EraseRootFromParent_Done, |
| 32408 | /* 89448 */ // Label 2758: @89448 |
| 32409 | /* 89448 */ GIM_Try, /*On fail goto*//*Label 2759*/ GIMT_Encode4(89500), // Rule ID 4183 // |
| 32410 | /* 89453 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32411 | /* 89457 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32412 | /* 89461 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32413 | /* 89465 */ // MIs[1] Operand 1 |
| 32414 | /* 89465 */ // No operand predicates |
| 32415 | /* 89465 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32416 | /* 89469 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32417 | /* 89471 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32418 | /* 89471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th), |
| 32419 | /* 89474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32420 | /* 89476 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32421 | /* 89478 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32422 | /* 89480 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32423 | /* 89483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32424 | /* 89486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32425 | /* 89492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32426 | /* 89498 */ GIR_RootConstrainSelectedInstOperands, |
| 32427 | /* 89499 */ // GIR_Coverage, 4183, |
| 32428 | /* 89499 */ GIR_EraseRootFromParent_Done, |
| 32429 | /* 89500 */ // Label 2759: @89500 |
| 32430 | /* 89500 */ GIM_Reject, |
| 32431 | /* 89501 */ // Label 2757: @89501 |
| 32432 | /* 89501 */ GIM_Try, /*On fail goto*//*Label 2760*/ GIMT_Encode4(89619), |
| 32433 | /* 89506 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32434 | /* 89510 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32435 | /* 89514 */ GIM_Try, /*On fail goto*//*Label 2761*/ GIMT_Encode4(89566), // Rule ID 4189 // |
| 32436 | /* 89519 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32437 | /* 89523 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32438 | /* 89527 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32439 | /* 89531 */ // MIs[1] Operand 1 |
| 32440 | /* 89531 */ // No operand predicates |
| 32441 | /* 89531 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32442 | /* 89535 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32443 | /* 89537 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32444 | /* 89537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh), |
| 32445 | /* 89540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32446 | /* 89542 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32447 | /* 89544 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32448 | /* 89546 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32449 | /* 89549 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32450 | /* 89552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32451 | /* 89558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32452 | /* 89564 */ GIR_RootConstrainSelectedInstOperands, |
| 32453 | /* 89565 */ // GIR_Coverage, 4189, |
| 32454 | /* 89565 */ GIR_EraseRootFromParent_Done, |
| 32455 | /* 89566 */ // Label 2761: @89566 |
| 32456 | /* 89566 */ GIM_Try, /*On fail goto*//*Label 2762*/ GIMT_Encode4(89618), // Rule ID 4191 // |
| 32457 | /* 89571 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32458 | /* 89575 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32459 | /* 89579 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32460 | /* 89583 */ // MIs[1] Operand 1 |
| 32461 | /* 89583 */ // No operand predicates |
| 32462 | /* 89583 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32463 | /* 89587 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32464 | /* 89589 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32465 | /* 89589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th), |
| 32466 | /* 89592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32467 | /* 89594 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32468 | /* 89596 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32469 | /* 89598 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32470 | /* 89601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32471 | /* 89604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32472 | /* 89610 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32473 | /* 89616 */ GIR_RootConstrainSelectedInstOperands, |
| 32474 | /* 89617 */ // GIR_Coverage, 4191, |
| 32475 | /* 89617 */ GIR_EraseRootFromParent_Done, |
| 32476 | /* 89618 */ // Label 2762: @89618 |
| 32477 | /* 89618 */ GIM_Reject, |
| 32478 | /* 89619 */ // Label 2760: @89619 |
| 32479 | /* 89619 */ GIM_Reject, |
| 32480 | /* 89620 */ // Label 2756: @89620 |
| 32481 | /* 89620 */ GIM_Reject, |
| 32482 | /* 89621 */ // Label 2748: @89621 |
| 32483 | /* 89621 */ GIM_Try, /*On fail goto*//*Label 2763*/ GIMT_Encode4(90367), |
| 32484 | /* 89626 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32485 | /* 89630 */ GIM_Try, /*On fail goto*//*Label 2764*/ GIMT_Encode4(89876), |
| 32486 | /* 89635 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 32487 | /* 89639 */ GIM_Try, /*On fail goto*//*Label 2765*/ GIMT_Encode4(89757), |
| 32488 | /* 89644 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 32489 | /* 89648 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32490 | /* 89652 */ GIM_Try, /*On fail goto*//*Label 2766*/ GIMT_Encode4(89704), // Rule ID 4197 // |
| 32491 | /* 89657 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32492 | /* 89661 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32493 | /* 89665 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32494 | /* 89669 */ // MIs[1] Operand 1 |
| 32495 | /* 89669 */ // No operand predicates |
| 32496 | /* 89669 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32497 | /* 89673 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32498 | /* 89675 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32499 | /* 89675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs32), |
| 32500 | /* 89678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32501 | /* 89680 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32502 | /* 89682 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32503 | /* 89684 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32504 | /* 89687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32505 | /* 89690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32506 | /* 89696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32507 | /* 89702 */ GIR_RootConstrainSelectedInstOperands, |
| 32508 | /* 89703 */ // GIR_Coverage, 4197, |
| 32509 | /* 89703 */ GIR_EraseRootFromParent_Done, |
| 32510 | /* 89704 */ // Label 2766: @89704 |
| 32511 | /* 89704 */ GIM_Try, /*On fail goto*//*Label 2767*/ GIMT_Encode4(89756), // Rule ID 4199 // |
| 32512 | /* 89709 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32513 | /* 89713 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32514 | /* 89717 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32515 | /* 89721 */ // MIs[1] Operand 1 |
| 32516 | /* 89721 */ // No operand predicates |
| 32517 | /* 89721 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32518 | /* 89725 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32519 | /* 89727 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32520 | /* 89727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths32), |
| 32521 | /* 89730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32522 | /* 89732 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32523 | /* 89734 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32524 | /* 89736 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32525 | /* 89739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32526 | /* 89742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32527 | /* 89748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32528 | /* 89754 */ GIR_RootConstrainSelectedInstOperands, |
| 32529 | /* 89755 */ // GIR_Coverage, 4199, |
| 32530 | /* 89755 */ GIR_EraseRootFromParent_Done, |
| 32531 | /* 89756 */ // Label 2767: @89756 |
| 32532 | /* 89756 */ GIM_Reject, |
| 32533 | /* 89757 */ // Label 2765: @89757 |
| 32534 | /* 89757 */ GIM_Try, /*On fail goto*//*Label 2768*/ GIMT_Encode4(89875), |
| 32535 | /* 89762 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32536 | /* 89766 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32537 | /* 89770 */ GIM_Try, /*On fail goto*//*Label 2769*/ GIMT_Encode4(89822), // Rule ID 4205 // |
| 32538 | /* 89775 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32539 | /* 89779 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32540 | /* 89783 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32541 | /* 89787 */ // MIs[1] Operand 1 |
| 32542 | /* 89787 */ // No operand predicates |
| 32543 | /* 89787 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32544 | /* 89791 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32545 | /* 89793 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32546 | /* 89793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu32), |
| 32547 | /* 89796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32548 | /* 89798 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32549 | /* 89800 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32550 | /* 89802 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32551 | /* 89805 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32552 | /* 89808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32553 | /* 89814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32554 | /* 89820 */ GIR_RootConstrainSelectedInstOperands, |
| 32555 | /* 89821 */ // GIR_Coverage, 4205, |
| 32556 | /* 89821 */ GIR_EraseRootFromParent_Done, |
| 32557 | /* 89822 */ // Label 2769: @89822 |
| 32558 | /* 89822 */ GIM_Try, /*On fail goto*//*Label 2770*/ GIMT_Encode4(89874), // Rule ID 4207 // |
| 32559 | /* 89827 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32560 | /* 89831 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32561 | /* 89835 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32562 | /* 89839 */ // MIs[1] Operand 1 |
| 32563 | /* 89839 */ // No operand predicates |
| 32564 | /* 89839 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32565 | /* 89843 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32566 | /* 89845 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32567 | /* 89845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu32), |
| 32568 | /* 89848 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32569 | /* 89850 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32570 | /* 89852 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32571 | /* 89854 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32572 | /* 89857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32573 | /* 89860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32574 | /* 89866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32575 | /* 89872 */ GIR_RootConstrainSelectedInstOperands, |
| 32576 | /* 89873 */ // GIR_Coverage, 4207, |
| 32577 | /* 89873 */ GIR_EraseRootFromParent_Done, |
| 32578 | /* 89874 */ // Label 2770: @89874 |
| 32579 | /* 89874 */ GIM_Reject, |
| 32580 | /* 89875 */ // Label 2768: @89875 |
| 32581 | /* 89875 */ GIM_Reject, |
| 32582 | /* 89876 */ // Label 2764: @89876 |
| 32583 | /* 89876 */ GIM_Try, /*On fail goto*//*Label 2771*/ GIMT_Encode4(90122), |
| 32584 | /* 89881 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32585 | /* 89885 */ GIM_Try, /*On fail goto*//*Label 2772*/ GIMT_Encode4(90003), |
| 32586 | /* 89890 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 32587 | /* 89894 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32588 | /* 89898 */ GIM_Try, /*On fail goto*//*Label 2773*/ GIMT_Encode4(89950), // Rule ID 4213 // |
| 32589 | /* 89903 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32590 | /* 89907 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32591 | /* 89911 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32592 | /* 89915 */ // MIs[1] Operand 1 |
| 32593 | /* 89915 */ // No operand predicates |
| 32594 | /* 89915 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32595 | /* 89919 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32596 | /* 89921 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32597 | /* 89921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs32), |
| 32598 | /* 89924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32599 | /* 89926 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32600 | /* 89928 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32601 | /* 89930 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32602 | /* 89933 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32603 | /* 89936 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32604 | /* 89942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32605 | /* 89948 */ GIR_RootConstrainSelectedInstOperands, |
| 32606 | /* 89949 */ // GIR_Coverage, 4213, |
| 32607 | /* 89949 */ GIR_EraseRootFromParent_Done, |
| 32608 | /* 89950 */ // Label 2773: @89950 |
| 32609 | /* 89950 */ GIM_Try, /*On fail goto*//*Label 2774*/ GIMT_Encode4(90002), // Rule ID 4215 // |
| 32610 | /* 89955 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32611 | /* 89959 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32612 | /* 89963 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32613 | /* 89967 */ // MIs[1] Operand 1 |
| 32614 | /* 89967 */ // No operand predicates |
| 32615 | /* 89967 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32616 | /* 89971 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32617 | /* 89973 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32618 | /* 89973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths32), |
| 32619 | /* 89976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32620 | /* 89978 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32621 | /* 89980 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32622 | /* 89982 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32623 | /* 89985 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32624 | /* 89988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32625 | /* 89994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32626 | /* 90000 */ GIR_RootConstrainSelectedInstOperands, |
| 32627 | /* 90001 */ // GIR_Coverage, 4215, |
| 32628 | /* 90001 */ GIR_EraseRootFromParent_Done, |
| 32629 | /* 90002 */ // Label 2774: @90002 |
| 32630 | /* 90002 */ GIM_Reject, |
| 32631 | /* 90003 */ // Label 2772: @90003 |
| 32632 | /* 90003 */ GIM_Try, /*On fail goto*//*Label 2775*/ GIMT_Encode4(90121), |
| 32633 | /* 90008 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32634 | /* 90012 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32635 | /* 90016 */ GIM_Try, /*On fail goto*//*Label 2776*/ GIMT_Encode4(90068), // Rule ID 4221 // |
| 32636 | /* 90021 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32637 | /* 90025 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32638 | /* 90029 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32639 | /* 90033 */ // MIs[1] Operand 1 |
| 32640 | /* 90033 */ // No operand predicates |
| 32641 | /* 90033 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32642 | /* 90037 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32643 | /* 90039 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32644 | /* 90039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu32), |
| 32645 | /* 90042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32646 | /* 90044 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32647 | /* 90046 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32648 | /* 90048 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32649 | /* 90051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32650 | /* 90054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32651 | /* 90060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32652 | /* 90066 */ GIR_RootConstrainSelectedInstOperands, |
| 32653 | /* 90067 */ // GIR_Coverage, 4221, |
| 32654 | /* 90067 */ GIR_EraseRootFromParent_Done, |
| 32655 | /* 90068 */ // Label 2776: @90068 |
| 32656 | /* 90068 */ GIM_Try, /*On fail goto*//*Label 2777*/ GIMT_Encode4(90120), // Rule ID 4223 // |
| 32657 | /* 90073 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32658 | /* 90077 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32659 | /* 90081 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32660 | /* 90085 */ // MIs[1] Operand 1 |
| 32661 | /* 90085 */ // No operand predicates |
| 32662 | /* 90085 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32663 | /* 90089 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32664 | /* 90091 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32665 | /* 90091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu32), |
| 32666 | /* 90094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32667 | /* 90096 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32668 | /* 90098 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32669 | /* 90100 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32670 | /* 90103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32671 | /* 90106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32672 | /* 90112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32673 | /* 90118 */ GIR_RootConstrainSelectedInstOperands, |
| 32674 | /* 90119 */ // GIR_Coverage, 4223, |
| 32675 | /* 90119 */ GIR_EraseRootFromParent_Done, |
| 32676 | /* 90120 */ // Label 2777: @90120 |
| 32677 | /* 90120 */ GIM_Reject, |
| 32678 | /* 90121 */ // Label 2775: @90121 |
| 32679 | /* 90121 */ GIM_Reject, |
| 32680 | /* 90122 */ // Label 2771: @90122 |
| 32681 | /* 90122 */ GIM_Try, /*On fail goto*//*Label 2778*/ GIMT_Encode4(90244), |
| 32682 | /* 90127 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 32683 | /* 90131 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32684 | /* 90135 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32685 | /* 90139 */ GIM_Try, /*On fail goto*//*Label 2779*/ GIMT_Encode4(90191), // Rule ID 4229 // |
| 32686 | /* 90144 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32687 | /* 90148 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32688 | /* 90152 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32689 | /* 90156 */ // MIs[1] Operand 1 |
| 32690 | /* 90156 */ // No operand predicates |
| 32691 | /* 90156 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32692 | /* 90160 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32693 | /* 90162 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32694 | /* 90162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32bh), |
| 32695 | /* 90165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32696 | /* 90167 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32697 | /* 90169 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32698 | /* 90171 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32699 | /* 90174 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32700 | /* 90177 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32701 | /* 90183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32702 | /* 90189 */ GIR_RootConstrainSelectedInstOperands, |
| 32703 | /* 90190 */ // GIR_Coverage, 4229, |
| 32704 | /* 90190 */ GIR_EraseRootFromParent_Done, |
| 32705 | /* 90191 */ // Label 2779: @90191 |
| 32706 | /* 90191 */ GIM_Try, /*On fail goto*//*Label 2780*/ GIMT_Encode4(90243), // Rule ID 4231 // |
| 32707 | /* 90196 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32708 | /* 90200 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32709 | /* 90204 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32710 | /* 90208 */ // MIs[1] Operand 1 |
| 32711 | /* 90208 */ // No operand predicates |
| 32712 | /* 90208 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32713 | /* 90212 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32714 | /* 90214 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32715 | /* 90214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32th), |
| 32716 | /* 90217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32717 | /* 90219 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32718 | /* 90221 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32719 | /* 90223 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32720 | /* 90226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32721 | /* 90229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32722 | /* 90235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32723 | /* 90241 */ GIR_RootConstrainSelectedInstOperands, |
| 32724 | /* 90242 */ // GIR_Coverage, 4231, |
| 32725 | /* 90242 */ GIR_EraseRootFromParent_Done, |
| 32726 | /* 90243 */ // Label 2780: @90243 |
| 32727 | /* 90243 */ GIM_Reject, |
| 32728 | /* 90244 */ // Label 2778: @90244 |
| 32729 | /* 90244 */ GIM_Try, /*On fail goto*//*Label 2781*/ GIMT_Encode4(90366), |
| 32730 | /* 90249 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32731 | /* 90253 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32732 | /* 90257 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32733 | /* 90261 */ GIM_Try, /*On fail goto*//*Label 2782*/ GIMT_Encode4(90313), // Rule ID 4237 // |
| 32734 | /* 90266 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32735 | /* 90270 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32736 | /* 90274 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32737 | /* 90278 */ // MIs[1] Operand 1 |
| 32738 | /* 90278 */ // No operand predicates |
| 32739 | /* 90278 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32740 | /* 90282 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32741 | /* 90284 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32742 | /* 90284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32bh), |
| 32743 | /* 90287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32744 | /* 90289 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32745 | /* 90291 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32746 | /* 90293 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32747 | /* 90296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32748 | /* 90299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32749 | /* 90305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32750 | /* 90311 */ GIR_RootConstrainSelectedInstOperands, |
| 32751 | /* 90312 */ // GIR_Coverage, 4237, |
| 32752 | /* 90312 */ GIR_EraseRootFromParent_Done, |
| 32753 | /* 90313 */ // Label 2782: @90313 |
| 32754 | /* 90313 */ GIM_Try, /*On fail goto*//*Label 2783*/ GIMT_Encode4(90365), // Rule ID 4239 // |
| 32755 | /* 90318 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32756 | /* 90322 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32757 | /* 90326 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32758 | /* 90330 */ // MIs[1] Operand 1 |
| 32759 | /* 90330 */ // No operand predicates |
| 32760 | /* 90330 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32761 | /* 90334 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32762 | /* 90336 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32763 | /* 90336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32th), |
| 32764 | /* 90339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32765 | /* 90341 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32766 | /* 90343 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32767 | /* 90345 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32768 | /* 90348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32769 | /* 90351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32770 | /* 90357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32771 | /* 90363 */ GIR_RootConstrainSelectedInstOperands, |
| 32772 | /* 90364 */ // GIR_Coverage, 4239, |
| 32773 | /* 90364 */ GIR_EraseRootFromParent_Done, |
| 32774 | /* 90365 */ // Label 2783: @90365 |
| 32775 | /* 90365 */ GIM_Reject, |
| 32776 | /* 90366 */ // Label 2781: @90366 |
| 32777 | /* 90366 */ GIM_Reject, |
| 32778 | /* 90367 */ // Label 2763: @90367 |
| 32779 | /* 90367 */ GIM_Reject, |
| 32780 | /* 90368 */ // Label 2747: @90368 |
| 32781 | /* 90368 */ GIM_Reject, |
| 32782 | /* 90369 */ // Label 2709: @90369 |
| 32783 | /* 90369 */ GIM_Reject, |
| 32784 | /* 90370 */ // Label 2706: @90370 |
| 32785 | /* 90370 */ GIM_Reject, |
| 32786 | /* 90371 */ // Label 22: @90371 |
| 32787 | /* 90371 */ GIM_Try, /*On fail goto*//*Label 2784*/ GIMT_Encode4(90426), |
| 32788 | /* 90376 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, |
| 32789 | /* 90379 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_clrex), |
| 32790 | /* 90384 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2785*/ GIMT_Encode4(90400), GIMT_Encode2(GIFBS_HasV6K_IsARM), // Rule ID 244 // |
| 32791 | /* 90391 */ // (intrinsic_void 3709:{ *:[iPTR] }) => (CLREX) |
| 32792 | /* 90391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLREX), |
| 32793 | /* 90394 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32794 | /* 90398 */ GIR_RootConstrainSelectedInstOperands, |
| 32795 | /* 90399 */ // GIR_Coverage, 244, |
| 32796 | /* 90399 */ GIR_EraseRootFromParent_Done, |
| 32797 | /* 90400 */ // Label 2785: @90400 |
| 32798 | /* 90400 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2786*/ GIMT_Encode4(90425), GIMT_Encode2(GIFBS_HasV7Clrex_IsThumb), // Rule ID 573 // |
| 32799 | /* 90407 */ // (intrinsic_void 3709:{ *:[iPTR] }) => (t2CLREX) |
| 32800 | /* 90407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLREX), |
| 32801 | /* 90410 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32802 | /* 90413 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32803 | /* 90419 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32804 | /* 90423 */ GIR_RootConstrainSelectedInstOperands, |
| 32805 | /* 90424 */ // GIR_Coverage, 573, |
| 32806 | /* 90424 */ GIR_EraseRootFromParent_Done, |
| 32807 | /* 90425 */ // Label 2786: @90425 |
| 32808 | /* 90425 */ GIM_Reject, |
| 32809 | /* 90426 */ // Label 2784: @90426 |
| 32810 | /* 90426 */ GIM_Try, /*On fail goto*//*Label 2787*/ GIMT_Encode4(91209), |
| 32811 | /* 90431 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, |
| 32812 | /* 90434 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2788*/ GIMT_Encode4(90469), GIMT_Encode2(GIFBS_IsThumb_IsWindows), // Rule ID 343 // |
| 32813 | /* 90441 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 32814 | /* 90446 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32815 | /* 90449 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/1, GIMT_Encode8(249), |
| 32816 | /* 90460 */ // (intrinsic_void 4163:{ *:[iPTR] }, 249:{ *:[i32] }) => (t__brkdiv0) |
| 32817 | /* 90460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t__brkdiv0), |
| 32818 | /* 90463 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32819 | /* 90467 */ GIR_RootConstrainSelectedInstOperands, |
| 32820 | /* 90468 */ // GIR_Coverage, 343, |
| 32821 | /* 90468 */ GIR_EraseRootFromParent_Done, |
| 32822 | /* 90469 */ // Label 2788: @90469 |
| 32823 | /* 90469 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2789*/ GIMT_Encode4(90520), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2 // |
| 32824 | /* 90476 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint), |
| 32825 | /* 90481 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32826 | /* 90484 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32827 | /* 90488 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32828 | /* 90492 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239), |
| 32829 | /* 90496 */ // MIs[1] Operand 1 |
| 32830 | /* 90496 */ // No operand predicates |
| 32831 | /* 90496 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32832 | /* 90498 */ // (intrinsic_void 3727:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (HINT (imm:{ *:[i32] }):$imm) |
| 32833 | /* 90498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::HINT), |
| 32834 | /* 90501 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32835 | /* 90504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32836 | /* 90507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32837 | /* 90513 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32838 | /* 90518 */ GIR_RootConstrainSelectedInstOperands, |
| 32839 | /* 90519 */ // GIR_Coverage, 2, |
| 32840 | /* 90519 */ GIR_EraseRootFromParent_Done, |
| 32841 | /* 90520 */ // Label 2789: @90520 |
| 32842 | /* 90520 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2790*/ GIMT_Encode4(90571), GIMT_Encode2(GIFBS_HasV7_IsARM), // Rule ID 10 // |
| 32843 | /* 90527 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg), |
| 32844 | /* 90532 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32845 | /* 90535 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32846 | /* 90539 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32847 | /* 90543 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32848 | /* 90547 */ // MIs[1] Operand 1 |
| 32849 | /* 90547 */ // No operand predicates |
| 32850 | /* 90547 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32851 | /* 90549 */ // (intrinsic_void 3722:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DBG (imm:{ *:[i32] }):$opt) |
| 32852 | /* 90549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DBG), |
| 32853 | /* 90552 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32854 | /* 90555 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32855 | /* 90558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32856 | /* 90564 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32857 | /* 90569 */ GIR_RootConstrainSelectedInstOperands, |
| 32858 | /* 90570 */ // GIR_Coverage, 10, |
| 32859 | /* 90570 */ GIR_EraseRootFromParent_Done, |
| 32860 | /* 90571 */ // Label 2790: @90571 |
| 32861 | /* 90571 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2791*/ GIMT_Encode4(90613), GIMT_Encode2(GIFBS_IsARM), // Rule ID 11 // |
| 32862 | /* 90578 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 32863 | /* 90583 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32864 | /* 90586 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32865 | /* 90590 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32866 | /* 90594 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 32867 | /* 90598 */ // MIs[1] Operand 1 |
| 32868 | /* 90598 */ // No operand predicates |
| 32869 | /* 90598 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32870 | /* 90600 */ // (intrinsic_void 4163:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (UDF (imm:{ *:[i32] }):$imm16) |
| 32871 | /* 90600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF), |
| 32872 | /* 90603 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
| 32873 | /* 90606 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32874 | /* 90611 */ GIR_RootConstrainSelectedInstOperands, |
| 32875 | /* 90612 */ // GIR_Coverage, 11, |
| 32876 | /* 90612 */ GIR_EraseRootFromParent_Done, |
| 32877 | /* 90613 */ // Label 2791: @90613 |
| 32878 | /* 90613 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2792*/ GIMT_Encode4(90655), GIMT_Encode2(GIFBS_HasDB_IsARM), // Rule ID 227 // |
| 32879 | /* 90620 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb), |
| 32880 | /* 90625 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32881 | /* 90628 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32882 | /* 90632 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32883 | /* 90636 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32884 | /* 90640 */ // MIs[1] Operand 1 |
| 32885 | /* 90640 */ // No operand predicates |
| 32886 | /* 90640 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32887 | /* 90642 */ // (intrinsic_void 3723:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DMB (imm:{ *:[i32] }):$opt) |
| 32888 | /* 90642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DMB), |
| 32889 | /* 90645 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32890 | /* 90648 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32891 | /* 90653 */ GIR_RootConstrainSelectedInstOperands, |
| 32892 | /* 90654 */ // GIR_Coverage, 227, |
| 32893 | /* 90654 */ GIR_EraseRootFromParent_Done, |
| 32894 | /* 90655 */ // Label 2792: @90655 |
| 32895 | /* 90655 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2793*/ GIMT_Encode4(90697), GIMT_Encode2(GIFBS_HasDB_IsARM), // Rule ID 228 // |
| 32896 | /* 90662 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb), |
| 32897 | /* 90667 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32898 | /* 90670 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32899 | /* 90674 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32900 | /* 90678 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32901 | /* 90682 */ // MIs[1] Operand 1 |
| 32902 | /* 90682 */ // No operand predicates |
| 32903 | /* 90682 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32904 | /* 90684 */ // (intrinsic_void 3724:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DSB (imm:{ *:[i32] }):$opt) |
| 32905 | /* 90684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DSB), |
| 32906 | /* 90687 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32907 | /* 90690 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32908 | /* 90695 */ GIR_RootConstrainSelectedInstOperands, |
| 32909 | /* 90696 */ // GIR_Coverage, 228, |
| 32910 | /* 90696 */ GIR_EraseRootFromParent_Done, |
| 32911 | /* 90697 */ // Label 2793: @90697 |
| 32912 | /* 90697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2794*/ GIMT_Encode4(90739), GIMT_Encode2(GIFBS_HasDB_IsARM), // Rule ID 229 // |
| 32913 | /* 90704 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb), |
| 32914 | /* 90709 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32915 | /* 90712 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32916 | /* 90716 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32917 | /* 90720 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32918 | /* 90724 */ // MIs[1] Operand 1 |
| 32919 | /* 90724 */ // No operand predicates |
| 32920 | /* 90724 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32921 | /* 90726 */ // (intrinsic_void 3728:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (ISB (imm:{ *:[i32] }):$opt) |
| 32922 | /* 90726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ISB), |
| 32923 | /* 90729 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32924 | /* 90732 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32925 | /* 90737 */ GIR_RootConstrainSelectedInstOperands, |
| 32926 | /* 90738 */ // GIR_Coverage, 229, |
| 32927 | /* 90738 */ GIR_EraseRootFromParent_Done, |
| 32928 | /* 90739 */ // Label 2794: @90739 |
| 32929 | /* 90739 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2795*/ GIMT_Encode4(90790), GIMT_Encode2(GIFBS_HasV6M_IsThumb), // Rule ID 275 // |
| 32930 | /* 90746 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint), |
| 32931 | /* 90751 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32932 | /* 90754 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32933 | /* 90758 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32934 | /* 90762 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32935 | /* 90766 */ // MIs[1] Operand 1 |
| 32936 | /* 90766 */ // No operand predicates |
| 32937 | /* 90766 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32938 | /* 90768 */ // (intrinsic_void 3727:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (tHINT (imm:{ *:[i32] }):$imm) |
| 32939 | /* 90768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tHINT), |
| 32940 | /* 90771 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32941 | /* 90774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32942 | /* 90777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32943 | /* 90783 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32944 | /* 90788 */ GIR_RootConstrainSelectedInstOperands, |
| 32945 | /* 90789 */ // GIR_Coverage, 275, |
| 32946 | /* 90789 */ GIR_EraseRootFromParent_Done, |
| 32947 | /* 90790 */ // Label 2795: @90790 |
| 32948 | /* 90790 */ GIM_Try, /*On fail goto*//*Label 2796*/ GIMT_Encode4(90872), |
| 32949 | /* 90795 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 32950 | /* 90800 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32951 | /* 90803 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2797*/ GIMT_Encode4(90837), GIMT_Encode2(GIFBS_IsThumb), // Rule ID 342 // |
| 32952 | /* 90810 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32953 | /* 90814 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32954 | /* 90818 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255), |
| 32955 | /* 90822 */ // MIs[1] Operand 1 |
| 32956 | /* 90822 */ // No operand predicates |
| 32957 | /* 90822 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32958 | /* 90824 */ // (intrinsic_void 4163:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$imm8) => (tUDF (imm:{ *:[i32] }):$imm8) |
| 32959 | /* 90824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF), |
| 32960 | /* 90827 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8 |
| 32961 | /* 90830 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32962 | /* 90835 */ GIR_RootConstrainSelectedInstOperands, |
| 32963 | /* 90836 */ // GIR_Coverage, 342, |
| 32964 | /* 90836 */ GIR_EraseRootFromParent_Done, |
| 32965 | /* 90837 */ // Label 2797: @90837 |
| 32966 | /* 90837 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2798*/ GIMT_Encode4(90871), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 493 // |
| 32967 | /* 90844 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32968 | /* 90848 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32969 | /* 90852 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 32970 | /* 90856 */ // MIs[1] Operand 1 |
| 32971 | /* 90856 */ // No operand predicates |
| 32972 | /* 90856 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32973 | /* 90858 */ // (intrinsic_void 4163:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (t2UDF (imm:{ *:[i32] }):$imm16) |
| 32974 | /* 90858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDF), |
| 32975 | /* 90861 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
| 32976 | /* 90864 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32977 | /* 90869 */ GIR_RootConstrainSelectedInstOperands, |
| 32978 | /* 90870 */ // GIR_Coverage, 493, |
| 32979 | /* 90870 */ GIR_EraseRootFromParent_Done, |
| 32980 | /* 90871 */ // Label 2798: @90871 |
| 32981 | /* 90871 */ GIM_Reject, |
| 32982 | /* 90872 */ // Label 2796: @90872 |
| 32983 | /* 90872 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2799*/ GIMT_Encode4(90923), GIMT_Encode2(GIFBS_HasDB_IsThumb), // Rule ID 558 // |
| 32984 | /* 90879 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb), |
| 32985 | /* 90884 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32986 | /* 90887 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32987 | /* 90891 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32988 | /* 90895 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32989 | /* 90899 */ // MIs[1] Operand 1 |
| 32990 | /* 90899 */ // No operand predicates |
| 32991 | /* 90899 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32992 | /* 90901 */ // (intrinsic_void 3723:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DMB (imm:{ *:[i32] }):$opt) |
| 32993 | /* 90901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DMB), |
| 32994 | /* 90904 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32995 | /* 90907 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32996 | /* 90910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32997 | /* 90916 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32998 | /* 90921 */ GIR_RootConstrainSelectedInstOperands, |
| 32999 | /* 90922 */ // GIR_Coverage, 558, |
| 33000 | /* 90922 */ GIR_EraseRootFromParent_Done, |
| 33001 | /* 90923 */ // Label 2799: @90923 |
| 33002 | /* 90923 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2800*/ GIMT_Encode4(90974), GIMT_Encode2(GIFBS_HasDB_IsThumb), // Rule ID 559 // |
| 33003 | /* 90930 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb), |
| 33004 | /* 90935 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 33005 | /* 90938 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 33006 | /* 90942 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33007 | /* 90946 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 33008 | /* 90950 */ // MIs[1] Operand 1 |
| 33009 | /* 90950 */ // No operand predicates |
| 33010 | /* 90950 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33011 | /* 90952 */ // (intrinsic_void 3724:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DSB (imm:{ *:[i32] }):$opt) |
| 33012 | /* 90952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DSB), |
| 33013 | /* 90955 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 33014 | /* 90958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33015 | /* 90961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33016 | /* 90967 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33017 | /* 90972 */ GIR_RootConstrainSelectedInstOperands, |
| 33018 | /* 90973 */ // GIR_Coverage, 559, |
| 33019 | /* 90973 */ GIR_EraseRootFromParent_Done, |
| 33020 | /* 90974 */ // Label 2800: @90974 |
| 33021 | /* 90974 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2801*/ GIMT_Encode4(91025), GIMT_Encode2(GIFBS_HasDB_IsThumb), // Rule ID 560 // |
| 33022 | /* 90981 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb), |
| 33023 | /* 90986 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 33024 | /* 90989 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 33025 | /* 90993 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33026 | /* 90997 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 33027 | /* 91001 */ // MIs[1] Operand 1 |
| 33028 | /* 91001 */ // No operand predicates |
| 33029 | /* 91001 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33030 | /* 91003 */ // (intrinsic_void 3728:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2ISB (imm:{ *:[i32] }):$opt) |
| 33031 | /* 91003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ISB), |
| 33032 | /* 91006 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 33033 | /* 91009 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33034 | /* 91012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33035 | /* 91018 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33036 | /* 91023 */ GIR_RootConstrainSelectedInstOperands, |
| 33037 | /* 91024 */ // GIR_Coverage, 560, |
| 33038 | /* 91024 */ GIR_EraseRootFromParent_Done, |
| 33039 | /* 91025 */ // Label 2801: @91025 |
| 33040 | /* 91025 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2802*/ GIMT_Encode4(91076), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 578 // |
| 33041 | /* 91032 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint), |
| 33042 | /* 91037 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 33043 | /* 91040 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 33044 | /* 91044 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33045 | /* 91048 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239), |
| 33046 | /* 91052 */ // MIs[1] Operand 1 |
| 33047 | /* 91052 */ // No operand predicates |
| 33048 | /* 91052 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33049 | /* 91054 */ // (intrinsic_void 3727:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (t2HINT (imm:{ *:[i32] }):$imm) |
| 33050 | /* 91054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2HINT), |
| 33051 | /* 91057 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 33052 | /* 91060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33053 | /* 91063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33054 | /* 91069 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33055 | /* 91074 */ GIR_RootConstrainSelectedInstOperands, |
| 33056 | /* 91075 */ // GIR_Coverage, 578, |
| 33057 | /* 91075 */ GIR_EraseRootFromParent_Done, |
| 33058 | /* 91076 */ // Label 2802: @91076 |
| 33059 | /* 91076 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2803*/ GIMT_Encode4(91127), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 579 // |
| 33060 | /* 91083 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg), |
| 33061 | /* 91088 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 33062 | /* 91091 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 33063 | /* 91095 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33064 | /* 91099 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 33065 | /* 91103 */ // MIs[1] Operand 1 |
| 33066 | /* 91103 */ // No operand predicates |
| 33067 | /* 91103 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33068 | /* 91105 */ // (intrinsic_void 3722:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DBG (imm:{ *:[i32] }):$opt) |
| 33069 | /* 91105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DBG), |
| 33070 | /* 91108 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 33071 | /* 91111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33072 | /* 91114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33073 | /* 91120 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33074 | /* 91125 */ GIR_RootConstrainSelectedInstOperands, |
| 33075 | /* 91126 */ // GIR_Coverage, 579, |
| 33076 | /* 91126 */ GIR_EraseRootFromParent_Done, |
| 33077 | /* 91127 */ // Label 2803: @91127 |
| 33078 | /* 91127 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2804*/ GIMT_Encode4(91166), GIMT_Encode2(GIFBS_HasFPRegs), // Rule ID 845 // |
| 33079 | /* 91134 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_get_fpscr), |
| 33080 | /* 91139 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33081 | /* 91142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33082 | /* 91146 */ // (intrinsic_w_chain:{ *:[i32] } 3725:{ *:[iPTR] }) => (VMRS:{ *:[i32] }) |
| 33083 | /* 91146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS), |
| 33084 | /* 91149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 33085 | /* 91151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33086 | /* 91154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33087 | /* 91160 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33088 | /* 91164 */ GIR_RootConstrainSelectedInstOperands, |
| 33089 | /* 91165 */ // GIR_Coverage, 845, |
| 33090 | /* 91165 */ GIR_EraseRootFromParent_Done, |
| 33091 | /* 91166 */ // Label 2804: @91166 |
| 33092 | /* 91166 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2805*/ GIMT_Encode4(91208), GIMT_Encode2(GIFBS_HasFPRegs), // Rule ID 846 // |
| 33093 | /* 91173 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_set_fpscr), |
| 33094 | /* 91178 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 33095 | /* 91181 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33096 | /* 91185 */ // (intrinsic_void 4107:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt) |
| 33097 | /* 91185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 33098 | /* 91188 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt |
| 33099 | /* 91190 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33100 | /* 91193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33101 | /* 91199 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 33102 | /* 91202 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33103 | /* 91206 */ GIR_RootConstrainSelectedInstOperands, |
| 33104 | /* 91207 */ // GIR_Coverage, 846, |
| 33105 | /* 91207 */ GIR_EraseRootFromParent_Done, |
| 33106 | /* 91208 */ // Label 2805: @91208 |
| 33107 | /* 91208 */ GIM_Reject, |
| 33108 | /* 91209 */ // Label 2787: @91209 |
| 33109 | /* 91209 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2806*/ GIMT_Encode4(91251), GIMT_Encode2(GIFBS_HasLOB_HasV8_1MMainline_IsThumb2), // Rule ID 603 // |
| 33110 | /* 91216 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 33111 | /* 91219 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::start_loop_iterations), |
| 33112 | /* 91224 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33113 | /* 91227 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33114 | /* 91230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRlrRegClassID), |
| 33115 | /* 91234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33116 | /* 91238 */ // (intrinsic_w_chain:{ *:[i32] } 372:{ *:[iPTR] }, rGPR:{ *:[i32] }:$tc) => (t2DoLoopStart:{ *:[i32] } rGPR:{ *:[i32] }:$tc) |
| 33117 | /* 91238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DoLoopStart), |
| 33118 | /* 91241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[X] |
| 33119 | /* 91243 */ GIR_RootToRootCopy, /*OpIdx*/2, // tc |
| 33120 | /* 91245 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33121 | /* 91249 */ GIR_RootConstrainSelectedInstOperands, |
| 33122 | /* 91250 */ // GIR_Coverage, 603, |
| 33123 | /* 91250 */ GIR_EraseRootFromParent_Done, |
| 33124 | /* 91251 */ // Label 2806: @91251 |
| 33125 | /* 91251 */ GIM_Try, /*On fail goto*//*Label 2807*/ GIMT_Encode4(93184), |
| 33126 | /* 91256 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 33127 | /* 91259 */ GIM_Try, /*On fail goto*//*Label 2808*/ GIMT_Encode4(91459), |
| 33128 | /* 91264 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base), |
| 33129 | /* 91269 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2811*/ GIMT_Encode4(91458), |
| 33130 | /* 91280 */ /*GILLT_v4s32*//*Label 2809*/ GIMT_Encode4(91288), |
| 33131 | /* 91284 */ /*GILLT_v2s64*//*Label 2810*/ GIMT_Encode4(91373), |
| 33132 | /* 91288 */ // Label 2809: @91288 |
| 33133 | /* 91288 */ GIM_Try, /*On fail goto*//*Label 2812*/ GIMT_Encode4(91372), |
| 33134 | /* 91293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33135 | /* 91296 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33136 | /* 91299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33137 | /* 91303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33138 | /* 91307 */ GIM_Try, /*On fail goto*//*Label 2813*/ GIMT_Encode4(91339), // Rule ID 5586 // |
| 33139 | /* 91312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33140 | /* 91316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33141 | /* 91320 */ // MIs[1] Operand 1 |
| 33142 | /* 91320 */ // No operand predicates |
| 33143 | /* 91320 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33144 | /* 91322 */ // (intrinsic_w_chain:{ *:[v4i32] } 3868:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33145 | /* 91322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi), |
| 33146 | /* 91325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33147 | /* 91327 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33148 | /* 91329 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33149 | /* 91332 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33150 | /* 91337 */ GIR_RootConstrainSelectedInstOperands, |
| 33151 | /* 91338 */ // GIR_Coverage, 5586, |
| 33152 | /* 91338 */ GIR_EraseRootFromParent_Done, |
| 33153 | /* 91339 */ // Label 2813: @91339 |
| 33154 | /* 91339 */ GIM_Try, /*On fail goto*//*Label 2814*/ GIMT_Encode4(91371), // Rule ID 5592 // |
| 33155 | /* 91344 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33156 | /* 91348 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33157 | /* 91352 */ // MIs[1] Operand 1 |
| 33158 | /* 91352 */ // No operand predicates |
| 33159 | /* 91352 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33160 | /* 91354 */ // (intrinsic_w_chain:{ *:[v4f32] } 3868:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33161 | /* 91354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi), |
| 33162 | /* 91357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33163 | /* 91359 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33164 | /* 91361 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33165 | /* 91364 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33166 | /* 91369 */ GIR_RootConstrainSelectedInstOperands, |
| 33167 | /* 91370 */ // GIR_Coverage, 5592, |
| 33168 | /* 91370 */ GIR_EraseRootFromParent_Done, |
| 33169 | /* 91371 */ // Label 2814: @91371 |
| 33170 | /* 91371 */ GIM_Reject, |
| 33171 | /* 91372 */ // Label 2812: @91372 |
| 33172 | /* 91372 */ GIM_Reject, |
| 33173 | /* 91373 */ // Label 2810: @91373 |
| 33174 | /* 91373 */ GIM_Try, /*On fail goto*//*Label 2815*/ GIMT_Encode4(91457), |
| 33175 | /* 91378 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 33176 | /* 91381 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33177 | /* 91384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33178 | /* 91388 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33179 | /* 91392 */ GIM_Try, /*On fail goto*//*Label 2816*/ GIMT_Encode4(91424), // Rule ID 5594 // |
| 33180 | /* 91397 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33181 | /* 91401 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33182 | /* 91405 */ // MIs[1] Operand 1 |
| 33183 | /* 91405 */ // No operand predicates |
| 33184 | /* 91405 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33185 | /* 91407 */ // (intrinsic_w_chain:{ *:[v2i64] } 3868:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33186 | /* 91407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi), |
| 33187 | /* 91410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33188 | /* 91412 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33189 | /* 91414 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33190 | /* 91417 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33191 | /* 91422 */ GIR_RootConstrainSelectedInstOperands, |
| 33192 | /* 91423 */ // GIR_Coverage, 5594, |
| 33193 | /* 91423 */ GIR_EraseRootFromParent_Done, |
| 33194 | /* 91424 */ // Label 2816: @91424 |
| 33195 | /* 91424 */ GIM_Try, /*On fail goto*//*Label 2817*/ GIMT_Encode4(91456), // Rule ID 5596 // |
| 33196 | /* 91429 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33197 | /* 91433 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33198 | /* 91437 */ // MIs[1] Operand 1 |
| 33199 | /* 91437 */ // No operand predicates |
| 33200 | /* 91437 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33201 | /* 91439 */ // (intrinsic_w_chain:{ *:[v2f64] } 3868:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33202 | /* 91439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi), |
| 33203 | /* 91442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33204 | /* 91444 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33205 | /* 91446 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33206 | /* 91449 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33207 | /* 91454 */ GIR_RootConstrainSelectedInstOperands, |
| 33208 | /* 91455 */ // GIR_Coverage, 5596, |
| 33209 | /* 91455 */ GIR_EraseRootFromParent_Done, |
| 33210 | /* 91456 */ // Label 2817: @91456 |
| 33211 | /* 91456 */ GIM_Reject, |
| 33212 | /* 91457 */ // Label 2815: @91457 |
| 33213 | /* 91457 */ GIM_Reject, |
| 33214 | /* 91458 */ // Label 2811: @91458 |
| 33215 | /* 91458 */ GIM_Reject, |
| 33216 | /* 91459 */ // Label 2808: @91459 |
| 33217 | /* 91459 */ GIM_Try, /*On fail goto*//*Label 2818*/ GIMT_Encode4(91501), // Rule ID 1927 // |
| 33218 | /* 91464 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_space), |
| 33219 | /* 91469 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33220 | /* 91472 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33221 | /* 91475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33222 | /* 91479 */ // MIs[0] size |
| 33223 | /* 91479 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 33224 | /* 91482 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33225 | /* 91486 */ // (intrinsic_w_chain:{ *:[i32] } 4138:{ *:[iPTR] }, (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) => (SPACE:{ *:[i32] } (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) |
| 33226 | /* 91486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SPACE), |
| 33227 | /* 91489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33228 | /* 91491 */ GIR_RootToRootCopy, /*OpIdx*/2, // size |
| 33229 | /* 91493 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 33230 | /* 91495 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33231 | /* 91499 */ GIR_RootConstrainSelectedInstOperands, |
| 33232 | /* 91500 */ // GIR_Coverage, 1927, |
| 33233 | /* 91500 */ GIR_EraseRootFromParent_Done, |
| 33234 | /* 91501 */ // Label 2818: @91501 |
| 33235 | /* 91501 */ GIM_Try, /*On fail goto*//*Label 2819*/ GIMT_Encode4(91701), |
| 33236 | /* 91506 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base), |
| 33237 | /* 91511 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2822*/ GIMT_Encode4(91700), |
| 33238 | /* 91522 */ /*GILLT_v4s32*//*Label 2820*/ GIMT_Encode4(91530), |
| 33239 | /* 91526 */ /*GILLT_v2s64*//*Label 2821*/ GIMT_Encode4(91615), |
| 33240 | /* 91530 */ // Label 2820: @91530 |
| 33241 | /* 91530 */ GIM_Try, /*On fail goto*//*Label 2823*/ GIMT_Encode4(91614), |
| 33242 | /* 91535 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33243 | /* 91538 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33244 | /* 91541 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33245 | /* 91545 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33246 | /* 91549 */ GIM_Try, /*On fail goto*//*Label 2824*/ GIMT_Encode4(91581), // Rule ID 5588 // |
| 33247 | /* 91554 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 33248 | /* 91558 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33249 | /* 91562 */ // MIs[1] Operand 1 |
| 33250 | /* 91562 */ // No operand predicates |
| 33251 | /* 91562 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33252 | /* 91564 */ // (intrinsic_void 3950:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33253 | /* 91564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi), |
| 33254 | /* 91567 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33255 | /* 91569 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 33256 | /* 91571 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33257 | /* 91574 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33258 | /* 91579 */ GIR_RootConstrainSelectedInstOperands, |
| 33259 | /* 91580 */ // GIR_Coverage, 5588, |
| 33260 | /* 91580 */ GIR_EraseRootFromParent_Done, |
| 33261 | /* 91581 */ // Label 2824: @91581 |
| 33262 | /* 91581 */ GIM_Try, /*On fail goto*//*Label 2825*/ GIMT_Encode4(91613), // Rule ID 5598 // |
| 33263 | /* 91586 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 33264 | /* 91590 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33265 | /* 91594 */ // MIs[1] Operand 1 |
| 33266 | /* 91594 */ // No operand predicates |
| 33267 | /* 91594 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33268 | /* 91596 */ // (intrinsic_void 3950:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33269 | /* 91596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi), |
| 33270 | /* 91599 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33271 | /* 91601 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 33272 | /* 91603 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33273 | /* 91606 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33274 | /* 91611 */ GIR_RootConstrainSelectedInstOperands, |
| 33275 | /* 91612 */ // GIR_Coverage, 5598, |
| 33276 | /* 91612 */ GIR_EraseRootFromParent_Done, |
| 33277 | /* 91613 */ // Label 2825: @91613 |
| 33278 | /* 91613 */ GIM_Reject, |
| 33279 | /* 91614 */ // Label 2823: @91614 |
| 33280 | /* 91614 */ GIM_Reject, |
| 33281 | /* 91615 */ // Label 2821: @91615 |
| 33282 | /* 91615 */ GIM_Try, /*On fail goto*//*Label 2826*/ GIMT_Encode4(91699), |
| 33283 | /* 91620 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33284 | /* 91623 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 33285 | /* 91626 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33286 | /* 91630 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33287 | /* 91634 */ GIM_Try, /*On fail goto*//*Label 2827*/ GIMT_Encode4(91666), // Rule ID 5602 // |
| 33288 | /* 91639 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 33289 | /* 91643 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33290 | /* 91647 */ // MIs[1] Operand 1 |
| 33291 | /* 91647 */ // No operand predicates |
| 33292 | /* 91647 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33293 | /* 91649 */ // (intrinsic_void 3950:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33294 | /* 91649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi), |
| 33295 | /* 91652 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33296 | /* 91654 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 33297 | /* 91656 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33298 | /* 91659 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33299 | /* 91664 */ GIR_RootConstrainSelectedInstOperands, |
| 33300 | /* 91665 */ // GIR_Coverage, 5602, |
| 33301 | /* 91665 */ GIR_EraseRootFromParent_Done, |
| 33302 | /* 91666 */ // Label 2827: @91666 |
| 33303 | /* 91666 */ GIM_Try, /*On fail goto*//*Label 2828*/ GIMT_Encode4(91698), // Rule ID 5606 // |
| 33304 | /* 91671 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 33305 | /* 91675 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33306 | /* 91679 */ // MIs[1] Operand 1 |
| 33307 | /* 91679 */ // No operand predicates |
| 33308 | /* 91679 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33309 | /* 91681 */ // (intrinsic_void 3950:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33310 | /* 91681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi), |
| 33311 | /* 91684 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33312 | /* 91686 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 33313 | /* 91688 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33314 | /* 91691 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33315 | /* 91696 */ GIR_RootConstrainSelectedInstOperands, |
| 33316 | /* 91697 */ // GIR_Coverage, 5606, |
| 33317 | /* 91697 */ GIR_EraseRootFromParent_Done, |
| 33318 | /* 91698 */ // Label 2828: @91698 |
| 33319 | /* 91698 */ GIM_Reject, |
| 33320 | /* 91699 */ // Label 2826: @91699 |
| 33321 | /* 91699 */ GIM_Reject, |
| 33322 | /* 91700 */ // Label 2822: @91700 |
| 33323 | /* 91700 */ GIM_Reject, |
| 33324 | /* 91701 */ // Label 2819: @91701 |
| 33325 | /* 91701 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2829*/ GIMT_Encode4(91758), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 3 // |
| 33326 | /* 91708 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel), |
| 33327 | /* 91713 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33328 | /* 91716 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33329 | /* 91719 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33330 | /* 91722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33331 | /* 91726 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33332 | /* 91730 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33333 | /* 91734 */ // (intrinsic_w_chain:{ *:[i32] } 4106:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 33334 | /* 91734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SEL), |
| 33335 | /* 91737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33336 | /* 91739 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33337 | /* 91741 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33338 | /* 91743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33339 | /* 91746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33340 | /* 91752 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33341 | /* 91756 */ GIR_RootConstrainSelectedInstOperands, |
| 33342 | /* 91757 */ // GIR_Coverage, 3, |
| 33343 | /* 91757 */ GIR_EraseRootFromParent_Done, |
| 33344 | /* 91758 */ // Label 2829: @91758 |
| 33345 | /* 91758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2830*/ GIMT_Encode4(91815), GIMT_Encode2(GIFBS_IsARM), // Rule ID 120 // |
| 33346 | /* 91765 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx), |
| 33347 | /* 91770 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33348 | /* 91773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33349 | /* 91776 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33350 | /* 91779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33351 | /* 91783 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33352 | /* 91787 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33353 | /* 91791 */ // (intrinsic_w_chain:{ *:[i32] } 4105:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33354 | /* 91791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SASX), |
| 33355 | /* 91794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33356 | /* 91796 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33357 | /* 91798 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33358 | /* 91800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33359 | /* 91803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33360 | /* 91809 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33361 | /* 91813 */ GIR_RootConstrainSelectedInstOperands, |
| 33362 | /* 91814 */ // GIR_Coverage, 120, |
| 33363 | /* 91814 */ GIR_EraseRootFromParent_Done, |
| 33364 | /* 91815 */ // Label 2830: @91815 |
| 33365 | /* 91815 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2831*/ GIMT_Encode4(91872), GIMT_Encode2(GIFBS_IsARM), // Rule ID 121 // |
| 33366 | /* 91822 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16), |
| 33367 | /* 91827 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33368 | /* 91830 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33369 | /* 91833 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33370 | /* 91836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33371 | /* 91840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33372 | /* 91844 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33373 | /* 91848 */ // (intrinsic_w_chain:{ *:[i32] } 4103:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33374 | /* 91848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD16), |
| 33375 | /* 91851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33376 | /* 91853 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33377 | /* 91855 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33378 | /* 91857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33379 | /* 91860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33380 | /* 91866 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33381 | /* 91870 */ GIR_RootConstrainSelectedInstOperands, |
| 33382 | /* 91871 */ // GIR_Coverage, 121, |
| 33383 | /* 91871 */ GIR_EraseRootFromParent_Done, |
| 33384 | /* 91872 */ // Label 2831: @91872 |
| 33385 | /* 91872 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2832*/ GIMT_Encode4(91929), GIMT_Encode2(GIFBS_IsARM), // Rule ID 122 // |
| 33386 | /* 91879 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8), |
| 33387 | /* 91884 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33388 | /* 91887 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33389 | /* 91890 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33390 | /* 91893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33391 | /* 91897 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33392 | /* 91901 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33393 | /* 91905 */ // (intrinsic_w_chain:{ *:[i32] } 4104:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33394 | /* 91905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD8), |
| 33395 | /* 91908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33396 | /* 91910 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33397 | /* 91912 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33398 | /* 91914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33399 | /* 91917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33400 | /* 91923 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33401 | /* 91927 */ GIR_RootConstrainSelectedInstOperands, |
| 33402 | /* 91928 */ // GIR_Coverage, 122, |
| 33403 | /* 91928 */ GIR_EraseRootFromParent_Done, |
| 33404 | /* 91929 */ // Label 2832: @91929 |
| 33405 | /* 91929 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2833*/ GIMT_Encode4(91986), GIMT_Encode2(GIFBS_IsARM), // Rule ID 123 // |
| 33406 | /* 91936 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax), |
| 33407 | /* 91941 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33408 | /* 91944 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33409 | /* 91947 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33410 | /* 91950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33411 | /* 91954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33412 | /* 91958 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33413 | /* 91962 */ // (intrinsic_w_chain:{ *:[i32] } 4141:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33414 | /* 91962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSAX), |
| 33415 | /* 91965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33416 | /* 91967 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33417 | /* 91969 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33418 | /* 91971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33419 | /* 91974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33420 | /* 91980 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33421 | /* 91984 */ GIR_RootConstrainSelectedInstOperands, |
| 33422 | /* 91985 */ // GIR_Coverage, 123, |
| 33423 | /* 91985 */ GIR_EraseRootFromParent_Done, |
| 33424 | /* 91986 */ // Label 2833: @91986 |
| 33425 | /* 91986 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2834*/ GIMT_Encode4(92043), GIMT_Encode2(GIFBS_IsARM), // Rule ID 124 // |
| 33426 | /* 91993 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16), |
| 33427 | /* 91998 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33428 | /* 92001 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33429 | /* 92004 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33430 | /* 92007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33431 | /* 92011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33432 | /* 92015 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33433 | /* 92019 */ // (intrinsic_w_chain:{ *:[i32] } 4142:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33434 | /* 92019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB16), |
| 33435 | /* 92022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33436 | /* 92024 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33437 | /* 92026 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33438 | /* 92028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33439 | /* 92031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33440 | /* 92037 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33441 | /* 92041 */ GIR_RootConstrainSelectedInstOperands, |
| 33442 | /* 92042 */ // GIR_Coverage, 124, |
| 33443 | /* 92042 */ GIR_EraseRootFromParent_Done, |
| 33444 | /* 92043 */ // Label 2834: @92043 |
| 33445 | /* 92043 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2835*/ GIMT_Encode4(92100), GIMT_Encode2(GIFBS_IsARM), // Rule ID 125 // |
| 33446 | /* 92050 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8), |
| 33447 | /* 92055 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33448 | /* 92058 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33449 | /* 92061 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33450 | /* 92064 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33451 | /* 92068 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33452 | /* 92072 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33453 | /* 92076 */ // (intrinsic_w_chain:{ *:[i32] } 4143:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33454 | /* 92076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB8), |
| 33455 | /* 92079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33456 | /* 92081 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33457 | /* 92083 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33458 | /* 92085 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33459 | /* 92088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33460 | /* 92094 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33461 | /* 92098 */ GIR_RootConstrainSelectedInstOperands, |
| 33462 | /* 92099 */ // GIR_Coverage, 125, |
| 33463 | /* 92099 */ GIR_EraseRootFromParent_Done, |
| 33464 | /* 92100 */ // Label 2835: @92100 |
| 33465 | /* 92100 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2836*/ GIMT_Encode4(92157), GIMT_Encode2(GIFBS_IsARM), // Rule ID 126 // |
| 33466 | /* 92107 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx), |
| 33467 | /* 92112 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33468 | /* 92115 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33469 | /* 92118 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33470 | /* 92121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33471 | /* 92125 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33472 | /* 92129 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33473 | /* 92133 */ // (intrinsic_w_chain:{ *:[i32] } 4156:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33474 | /* 92133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UASX), |
| 33475 | /* 92136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33476 | /* 92138 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33477 | /* 92140 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33478 | /* 92142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33479 | /* 92145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33480 | /* 92151 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33481 | /* 92155 */ GIR_RootConstrainSelectedInstOperands, |
| 33482 | /* 92156 */ // GIR_Coverage, 126, |
| 33483 | /* 92156 */ GIR_EraseRootFromParent_Done, |
| 33484 | /* 92157 */ // Label 2836: @92157 |
| 33485 | /* 92157 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2837*/ GIMT_Encode4(92214), GIMT_Encode2(GIFBS_IsARM), // Rule ID 127 // |
| 33486 | /* 92164 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16), |
| 33487 | /* 92169 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33488 | /* 92172 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33489 | /* 92175 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33490 | /* 92178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33491 | /* 92182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33492 | /* 92186 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33493 | /* 92190 */ // (intrinsic_w_chain:{ *:[i32] } 4154:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33494 | /* 92190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD16), |
| 33495 | /* 92193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33496 | /* 92195 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33497 | /* 92197 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33498 | /* 92199 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33499 | /* 92202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33500 | /* 92208 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33501 | /* 92212 */ GIR_RootConstrainSelectedInstOperands, |
| 33502 | /* 92213 */ // GIR_Coverage, 127, |
| 33503 | /* 92213 */ GIR_EraseRootFromParent_Done, |
| 33504 | /* 92214 */ // Label 2837: @92214 |
| 33505 | /* 92214 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2838*/ GIMT_Encode4(92271), GIMT_Encode2(GIFBS_IsARM), // Rule ID 128 // |
| 33506 | /* 92221 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8), |
| 33507 | /* 92226 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33508 | /* 92229 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33509 | /* 92232 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33510 | /* 92235 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33511 | /* 92239 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33512 | /* 92243 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33513 | /* 92247 */ // (intrinsic_w_chain:{ *:[i32] } 4155:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33514 | /* 92247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD8), |
| 33515 | /* 92250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33516 | /* 92252 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33517 | /* 92254 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33518 | /* 92256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33519 | /* 92259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33520 | /* 92265 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33521 | /* 92269 */ GIR_RootConstrainSelectedInstOperands, |
| 33522 | /* 92270 */ // GIR_Coverage, 128, |
| 33523 | /* 92270 */ GIR_EraseRootFromParent_Done, |
| 33524 | /* 92271 */ // Label 2838: @92271 |
| 33525 | /* 92271 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2839*/ GIMT_Encode4(92328), GIMT_Encode2(GIFBS_IsARM), // Rule ID 129 // |
| 33526 | /* 92278 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax), |
| 33527 | /* 92283 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33528 | /* 92286 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33529 | /* 92289 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33530 | /* 92292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33531 | /* 92296 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33532 | /* 92300 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33533 | /* 92304 */ // (intrinsic_w_chain:{ *:[i32] } 4174:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33534 | /* 92304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAX), |
| 33535 | /* 92307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33536 | /* 92309 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33537 | /* 92311 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33538 | /* 92313 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33539 | /* 92316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33540 | /* 92322 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33541 | /* 92326 */ GIR_RootConstrainSelectedInstOperands, |
| 33542 | /* 92327 */ // GIR_Coverage, 129, |
| 33543 | /* 92327 */ GIR_EraseRootFromParent_Done, |
| 33544 | /* 92328 */ // Label 2839: @92328 |
| 33545 | /* 92328 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2840*/ GIMT_Encode4(92385), GIMT_Encode2(GIFBS_IsARM), // Rule ID 130 // |
| 33546 | /* 92335 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16), |
| 33547 | /* 92340 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33548 | /* 92343 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33549 | /* 92346 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33550 | /* 92349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33551 | /* 92353 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33552 | /* 92357 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33553 | /* 92361 */ // (intrinsic_w_chain:{ *:[i32] } 4175:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33554 | /* 92361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB16), |
| 33555 | /* 92364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33556 | /* 92366 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33557 | /* 92368 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33558 | /* 92370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33559 | /* 92373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33560 | /* 92379 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33561 | /* 92383 */ GIR_RootConstrainSelectedInstOperands, |
| 33562 | /* 92384 */ // GIR_Coverage, 130, |
| 33563 | /* 92384 */ GIR_EraseRootFromParent_Done, |
| 33564 | /* 92385 */ // Label 2840: @92385 |
| 33565 | /* 92385 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2841*/ GIMT_Encode4(92442), GIMT_Encode2(GIFBS_IsARM), // Rule ID 131 // |
| 33566 | /* 92392 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8), |
| 33567 | /* 92397 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33568 | /* 92400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33569 | /* 92403 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33570 | /* 92406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33571 | /* 92410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33572 | /* 92414 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33573 | /* 92418 */ // (intrinsic_w_chain:{ *:[i32] } 4176:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33574 | /* 92418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB8), |
| 33575 | /* 92421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33576 | /* 92423 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33577 | /* 92425 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33578 | /* 92427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33579 | /* 92430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33580 | /* 92436 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33581 | /* 92440 */ GIR_RootConstrainSelectedInstOperands, |
| 33582 | /* 92441 */ // GIR_Coverage, 131, |
| 33583 | /* 92441 */ GIR_EraseRootFromParent_Done, |
| 33584 | /* 92442 */ // Label 2841: @92442 |
| 33585 | /* 92442 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2842*/ GIMT_Encode4(92499), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 430 // |
| 33586 | /* 92449 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel), |
| 33587 | /* 92454 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33588 | /* 92457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33589 | /* 92460 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33590 | /* 92463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33591 | /* 92467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33592 | /* 92471 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33593 | /* 92475 */ // (intrinsic_w_chain:{ *:[i32] } 4106:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (t2SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 33594 | /* 92475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SEL), |
| 33595 | /* 92478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33596 | /* 92480 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33597 | /* 92482 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33598 | /* 92484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33599 | /* 92487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33600 | /* 92493 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33601 | /* 92497 */ GIR_RootConstrainSelectedInstOperands, |
| 33602 | /* 92498 */ // GIR_Coverage, 430, |
| 33603 | /* 92498 */ GIR_EraseRootFromParent_Done, |
| 33604 | /* 92499 */ // Label 2842: @92499 |
| 33605 | /* 92499 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2843*/ GIMT_Encode4(92556), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 443 // |
| 33606 | /* 92506 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx), |
| 33607 | /* 92511 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33608 | /* 92514 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33609 | /* 92517 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33610 | /* 92520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33611 | /* 92524 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33612 | /* 92528 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33613 | /* 92532 */ // (intrinsic_w_chain:{ *:[i32] } 4105:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33614 | /* 92532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SASX), |
| 33615 | /* 92535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33616 | /* 92537 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33617 | /* 92539 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33618 | /* 92541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33619 | /* 92544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33620 | /* 92550 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33621 | /* 92554 */ GIR_RootConstrainSelectedInstOperands, |
| 33622 | /* 92555 */ // GIR_Coverage, 443, |
| 33623 | /* 92555 */ GIR_EraseRootFromParent_Done, |
| 33624 | /* 92556 */ // Label 2843: @92556 |
| 33625 | /* 92556 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2844*/ GIMT_Encode4(92613), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 444 // |
| 33626 | /* 92563 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16), |
| 33627 | /* 92568 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33628 | /* 92571 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33629 | /* 92574 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33630 | /* 92577 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33631 | /* 92581 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33632 | /* 92585 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33633 | /* 92589 */ // (intrinsic_w_chain:{ *:[i32] } 4103:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33634 | /* 92589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD16), |
| 33635 | /* 92592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33636 | /* 92594 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33637 | /* 92596 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33638 | /* 92598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33639 | /* 92601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33640 | /* 92607 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33641 | /* 92611 */ GIR_RootConstrainSelectedInstOperands, |
| 33642 | /* 92612 */ // GIR_Coverage, 444, |
| 33643 | /* 92612 */ GIR_EraseRootFromParent_Done, |
| 33644 | /* 92613 */ // Label 2844: @92613 |
| 33645 | /* 92613 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2845*/ GIMT_Encode4(92670), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 445 // |
| 33646 | /* 92620 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8), |
| 33647 | /* 92625 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33648 | /* 92628 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33649 | /* 92631 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33650 | /* 92634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33651 | /* 92638 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33652 | /* 92642 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33653 | /* 92646 */ // (intrinsic_w_chain:{ *:[i32] } 4104:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33654 | /* 92646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD8), |
| 33655 | /* 92649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33656 | /* 92651 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33657 | /* 92653 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33658 | /* 92655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33659 | /* 92658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33660 | /* 92664 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33661 | /* 92668 */ GIR_RootConstrainSelectedInstOperands, |
| 33662 | /* 92669 */ // GIR_Coverage, 445, |
| 33663 | /* 92669 */ GIR_EraseRootFromParent_Done, |
| 33664 | /* 92670 */ // Label 2845: @92670 |
| 33665 | /* 92670 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2846*/ GIMT_Encode4(92727), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 446 // |
| 33666 | /* 92677 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax), |
| 33667 | /* 92682 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33668 | /* 92685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33669 | /* 92688 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33670 | /* 92691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33671 | /* 92695 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33672 | /* 92699 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33673 | /* 92703 */ // (intrinsic_w_chain:{ *:[i32] } 4141:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33674 | /* 92703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSAX), |
| 33675 | /* 92706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33676 | /* 92708 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33677 | /* 92710 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33678 | /* 92712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33679 | /* 92715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33680 | /* 92721 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33681 | /* 92725 */ GIR_RootConstrainSelectedInstOperands, |
| 33682 | /* 92726 */ // GIR_Coverage, 446, |
| 33683 | /* 92726 */ GIR_EraseRootFromParent_Done, |
| 33684 | /* 92727 */ // Label 2846: @92727 |
| 33685 | /* 92727 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2847*/ GIMT_Encode4(92784), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 447 // |
| 33686 | /* 92734 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16), |
| 33687 | /* 92739 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33688 | /* 92742 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33689 | /* 92745 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33690 | /* 92748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33691 | /* 92752 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33692 | /* 92756 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33693 | /* 92760 */ // (intrinsic_w_chain:{ *:[i32] } 4142:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33694 | /* 92760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB16), |
| 33695 | /* 92763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33696 | /* 92765 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33697 | /* 92767 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33698 | /* 92769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33699 | /* 92772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33700 | /* 92778 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33701 | /* 92782 */ GIR_RootConstrainSelectedInstOperands, |
| 33702 | /* 92783 */ // GIR_Coverage, 447, |
| 33703 | /* 92783 */ GIR_EraseRootFromParent_Done, |
| 33704 | /* 92784 */ // Label 2847: @92784 |
| 33705 | /* 92784 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2848*/ GIMT_Encode4(92841), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 448 // |
| 33706 | /* 92791 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8), |
| 33707 | /* 92796 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33708 | /* 92799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33709 | /* 92802 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33710 | /* 92805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33711 | /* 92809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33712 | /* 92813 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33713 | /* 92817 */ // (intrinsic_w_chain:{ *:[i32] } 4143:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33714 | /* 92817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB8), |
| 33715 | /* 92820 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33716 | /* 92822 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33717 | /* 92824 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33718 | /* 92826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33719 | /* 92829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33720 | /* 92835 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33721 | /* 92839 */ GIR_RootConstrainSelectedInstOperands, |
| 33722 | /* 92840 */ // GIR_Coverage, 448, |
| 33723 | /* 92840 */ GIR_EraseRootFromParent_Done, |
| 33724 | /* 92841 */ // Label 2848: @92841 |
| 33725 | /* 92841 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2849*/ GIMT_Encode4(92898), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 449 // |
| 33726 | /* 92848 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx), |
| 33727 | /* 92853 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33728 | /* 92856 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33729 | /* 92859 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33730 | /* 92862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33731 | /* 92866 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33732 | /* 92870 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33733 | /* 92874 */ // (intrinsic_w_chain:{ *:[i32] } 4156:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33734 | /* 92874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UASX), |
| 33735 | /* 92877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33736 | /* 92879 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33737 | /* 92881 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33738 | /* 92883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33739 | /* 92886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33740 | /* 92892 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33741 | /* 92896 */ GIR_RootConstrainSelectedInstOperands, |
| 33742 | /* 92897 */ // GIR_Coverage, 449, |
| 33743 | /* 92897 */ GIR_EraseRootFromParent_Done, |
| 33744 | /* 92898 */ // Label 2849: @92898 |
| 33745 | /* 92898 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2850*/ GIMT_Encode4(92955), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 450 // |
| 33746 | /* 92905 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16), |
| 33747 | /* 92910 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33748 | /* 92913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33749 | /* 92916 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33750 | /* 92919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33751 | /* 92923 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33752 | /* 92927 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33753 | /* 92931 */ // (intrinsic_w_chain:{ *:[i32] } 4154:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33754 | /* 92931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD16), |
| 33755 | /* 92934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33756 | /* 92936 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33757 | /* 92938 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33758 | /* 92940 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33759 | /* 92943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33760 | /* 92949 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33761 | /* 92953 */ GIR_RootConstrainSelectedInstOperands, |
| 33762 | /* 92954 */ // GIR_Coverage, 450, |
| 33763 | /* 92954 */ GIR_EraseRootFromParent_Done, |
| 33764 | /* 92955 */ // Label 2850: @92955 |
| 33765 | /* 92955 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2851*/ GIMT_Encode4(93012), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 451 // |
| 33766 | /* 92962 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8), |
| 33767 | /* 92967 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33768 | /* 92970 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33769 | /* 92973 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33770 | /* 92976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33771 | /* 92980 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33772 | /* 92984 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33773 | /* 92988 */ // (intrinsic_w_chain:{ *:[i32] } 4155:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33774 | /* 92988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD8), |
| 33775 | /* 92991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33776 | /* 92993 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33777 | /* 92995 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33778 | /* 92997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33779 | /* 93000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33780 | /* 93006 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33781 | /* 93010 */ GIR_RootConstrainSelectedInstOperands, |
| 33782 | /* 93011 */ // GIR_Coverage, 451, |
| 33783 | /* 93011 */ GIR_EraseRootFromParent_Done, |
| 33784 | /* 93012 */ // Label 2851: @93012 |
| 33785 | /* 93012 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2852*/ GIMT_Encode4(93069), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 452 // |
| 33786 | /* 93019 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax), |
| 33787 | /* 93024 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33788 | /* 93027 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33789 | /* 93030 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33790 | /* 93033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33791 | /* 93037 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33792 | /* 93041 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33793 | /* 93045 */ // (intrinsic_w_chain:{ *:[i32] } 4174:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33794 | /* 93045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAX), |
| 33795 | /* 93048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33796 | /* 93050 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33797 | /* 93052 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33798 | /* 93054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33799 | /* 93057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33800 | /* 93063 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33801 | /* 93067 */ GIR_RootConstrainSelectedInstOperands, |
| 33802 | /* 93068 */ // GIR_Coverage, 452, |
| 33803 | /* 93068 */ GIR_EraseRootFromParent_Done, |
| 33804 | /* 93069 */ // Label 2852: @93069 |
| 33805 | /* 93069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2853*/ GIMT_Encode4(93126), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 453 // |
| 33806 | /* 93076 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16), |
| 33807 | /* 93081 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33808 | /* 93084 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33809 | /* 93087 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33810 | /* 93090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33811 | /* 93094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33812 | /* 93098 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33813 | /* 93102 */ // (intrinsic_w_chain:{ *:[i32] } 4175:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33814 | /* 93102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB16), |
| 33815 | /* 93105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33816 | /* 93107 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33817 | /* 93109 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33818 | /* 93111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33819 | /* 93114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33820 | /* 93120 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33821 | /* 93124 */ GIR_RootConstrainSelectedInstOperands, |
| 33822 | /* 93125 */ // GIR_Coverage, 453, |
| 33823 | /* 93125 */ GIR_EraseRootFromParent_Done, |
| 33824 | /* 93126 */ // Label 2853: @93126 |
| 33825 | /* 93126 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2854*/ GIMT_Encode4(93183), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 454 // |
| 33826 | /* 93133 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8), |
| 33827 | /* 93138 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33828 | /* 93141 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33829 | /* 93144 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33830 | /* 93147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33831 | /* 93151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33832 | /* 93155 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33833 | /* 93159 */ // (intrinsic_w_chain:{ *:[i32] } 4176:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33834 | /* 93159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB8), |
| 33835 | /* 93162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33836 | /* 93164 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33837 | /* 93166 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33838 | /* 93168 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33839 | /* 93171 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33840 | /* 93177 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33841 | /* 93181 */ GIR_RootConstrainSelectedInstOperands, |
| 33842 | /* 93182 */ // GIR_Coverage, 454, |
| 33843 | /* 93182 */ GIR_EraseRootFromParent_Done, |
| 33844 | /* 93183 */ // Label 2854: @93183 |
| 33845 | /* 93183 */ GIM_Reject, |
| 33846 | /* 93184 */ // Label 2807: @93184 |
| 33847 | /* 93184 */ GIM_Try, /*On fail goto*//*Label 2855*/ GIMT_Encode4(93409), |
| 33848 | /* 93189 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 33849 | /* 93192 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base_wb), |
| 33850 | /* 93197 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2858*/ GIMT_Encode4(93408), |
| 33851 | /* 93208 */ /*GILLT_v4s32*//*Label 2856*/ GIMT_Encode4(93216), |
| 33852 | /* 93212 */ /*GILLT_v2s64*//*Label 2857*/ GIMT_Encode4(93312), |
| 33853 | /* 93216 */ // Label 2856: @93216 |
| 33854 | /* 93216 */ GIM_Try, /*On fail goto*//*Label 2859*/ GIMT_Encode4(93311), |
| 33855 | /* 93221 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33856 | /* 93224 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33857 | /* 93227 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 33858 | /* 93230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33859 | /* 93234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33860 | /* 93238 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33861 | /* 93242 */ GIM_Try, /*On fail goto*//*Label 2860*/ GIMT_Encode4(93276), // Rule ID 5590 // |
| 33862 | /* 93247 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33863 | /* 93251 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33864 | /* 93255 */ // MIs[1] Operand 1 |
| 33865 | /* 93255 */ // No operand predicates |
| 33866 | /* 93255 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33867 | /* 93257 */ // (intrinsic_w_chain:{ *:[v4i32] } 3952:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33868 | /* 93257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre), |
| 33869 | /* 93260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33870 | /* 93262 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33871 | /* 93264 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33872 | /* 93266 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33873 | /* 93269 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33874 | /* 93274 */ GIR_RootConstrainSelectedInstOperands, |
| 33875 | /* 93275 */ // GIR_Coverage, 5590, |
| 33876 | /* 93275 */ GIR_EraseRootFromParent_Done, |
| 33877 | /* 93276 */ // Label 2860: @93276 |
| 33878 | /* 93276 */ GIM_Try, /*On fail goto*//*Label 2861*/ GIMT_Encode4(93310), // Rule ID 5600 // |
| 33879 | /* 93281 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33880 | /* 93285 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33881 | /* 93289 */ // MIs[1] Operand 1 |
| 33882 | /* 93289 */ // No operand predicates |
| 33883 | /* 93289 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33884 | /* 93291 */ // (intrinsic_w_chain:{ *:[v4i32] } 3952:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33885 | /* 93291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre), |
| 33886 | /* 93294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33887 | /* 93296 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33888 | /* 93298 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33889 | /* 93300 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33890 | /* 93303 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33891 | /* 93308 */ GIR_RootConstrainSelectedInstOperands, |
| 33892 | /* 93309 */ // GIR_Coverage, 5600, |
| 33893 | /* 93309 */ GIR_EraseRootFromParent_Done, |
| 33894 | /* 93310 */ // Label 2861: @93310 |
| 33895 | /* 93310 */ GIM_Reject, |
| 33896 | /* 93311 */ // Label 2859: @93311 |
| 33897 | /* 93311 */ GIM_Reject, |
| 33898 | /* 93312 */ // Label 2857: @93312 |
| 33899 | /* 93312 */ GIM_Try, /*On fail goto*//*Label 2862*/ GIMT_Encode4(93407), |
| 33900 | /* 93317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 33901 | /* 93320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33902 | /* 93323 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64, |
| 33903 | /* 93326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33904 | /* 93330 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33905 | /* 93334 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33906 | /* 93338 */ GIM_Try, /*On fail goto*//*Label 2863*/ GIMT_Encode4(93372), // Rule ID 5604 // |
| 33907 | /* 93343 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33908 | /* 93347 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33909 | /* 93351 */ // MIs[1] Operand 1 |
| 33910 | /* 93351 */ // No operand predicates |
| 33911 | /* 93351 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33912 | /* 93353 */ // (intrinsic_w_chain:{ *:[v2i64] } 3952:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33913 | /* 93353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre), |
| 33914 | /* 93356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33915 | /* 93358 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33916 | /* 93360 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33917 | /* 93362 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33918 | /* 93365 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33919 | /* 93370 */ GIR_RootConstrainSelectedInstOperands, |
| 33920 | /* 93371 */ // GIR_Coverage, 5604, |
| 33921 | /* 93371 */ GIR_EraseRootFromParent_Done, |
| 33922 | /* 93372 */ // Label 2863: @93372 |
| 33923 | /* 93372 */ GIM_Try, /*On fail goto*//*Label 2864*/ GIMT_Encode4(93406), // Rule ID 5608 // |
| 33924 | /* 93377 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33925 | /* 93381 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33926 | /* 93385 */ // MIs[1] Operand 1 |
| 33927 | /* 93385 */ // No operand predicates |
| 33928 | /* 93385 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33929 | /* 93387 */ // (intrinsic_w_chain:{ *:[v2i64] } 3952:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33930 | /* 93387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre), |
| 33931 | /* 93390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33932 | /* 93392 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33933 | /* 93394 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33934 | /* 93396 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33935 | /* 93399 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33936 | /* 93404 */ GIR_RootConstrainSelectedInstOperands, |
| 33937 | /* 93405 */ // GIR_Coverage, 5608, |
| 33938 | /* 93405 */ GIR_EraseRootFromParent_Done, |
| 33939 | /* 93406 */ // Label 2864: @93406 |
| 33940 | /* 93406 */ GIM_Reject, |
| 33941 | /* 93407 */ // Label 2862: @93407 |
| 33942 | /* 93407 */ GIM_Reject, |
| 33943 | /* 93408 */ // Label 2858: @93408 |
| 33944 | /* 93408 */ GIM_Reject, |
| 33945 | /* 93409 */ // Label 2855: @93409 |
| 33946 | /* 93409 */ GIM_Try, /*On fail goto*//*Label 2865*/ GIMT_Encode4(94245), |
| 33947 | /* 93414 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 33948 | /* 93417 */ GIM_Try, /*On fail goto*//*Label 2866*/ GIMT_Encode4(94001), |
| 33949 | /* 93422 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33950 | /* 93427 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 2871*/ GIMT_Encode4(94000), |
| 33951 | /* 93438 */ /*GILLT_v16s8*//*Label 2867*/ GIMT_Encode4(93462), GIMT_Encode4(0), |
| 33952 | /* 93446 */ /*GILLT_v8s16*//*Label 2868*/ GIMT_Encode4(93516), GIMT_Encode4(0), |
| 33953 | /* 93454 */ /*GILLT_v4s32*//*Label 2869*/ GIMT_Encode4(93692), |
| 33954 | /* 93458 */ /*GILLT_v2s64*//*Label 2870*/ GIMT_Encode4(93916), |
| 33955 | /* 93462 */ // Label 2867: @93462 |
| 33956 | /* 93462 */ GIM_Try, /*On fail goto*//*Label 2872*/ GIMT_Encode4(93515), // Rule ID 5482 // |
| 33957 | /* 93467 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33958 | /* 93470 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33959 | /* 93473 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33960 | /* 93476 */ // MIs[0] base |
| 33961 | /* 93476 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33962 | /* 93480 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33963 | /* 93484 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33964 | /* 93488 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33965 | /* 93492 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 33966 | /* 93496 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33967 | /* 93500 */ // (intrinsic_void 3954:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, MQPR:{ *:[v16i8] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB8_rq MQPR:{ *:[v16i8] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) |
| 33968 | /* 93500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB8_rq), |
| 33969 | /* 93503 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33970 | /* 93505 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33971 | /* 93507 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33972 | /* 93509 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33973 | /* 93513 */ GIR_RootConstrainSelectedInstOperands, |
| 33974 | /* 93514 */ // GIR_Coverage, 5482, |
| 33975 | /* 93514 */ GIR_EraseRootFromParent_Done, |
| 33976 | /* 93515 */ // Label 2872: @93515 |
| 33977 | /* 93515 */ GIM_Reject, |
| 33978 | /* 93516 */ // Label 2868: @93516 |
| 33979 | /* 93516 */ GIM_Try, /*On fail goto*//*Label 2873*/ GIMT_Encode4(93691), |
| 33980 | /* 93521 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33981 | /* 93524 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33982 | /* 93527 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33983 | /* 93530 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33984 | /* 93534 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33985 | /* 93538 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33986 | /* 93542 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33987 | /* 93546 */ GIM_Try, /*On fail goto*//*Label 2874*/ GIMT_Encode4(93604), |
| 33988 | /* 93551 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33989 | /* 93555 */ GIM_Try, /*On fail goto*//*Label 2875*/ GIMT_Encode4(93579), // Rule ID 5478 // |
| 33990 | /* 93560 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33991 | /* 93564 */ // (intrinsic_void 3954:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33992 | /* 93564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u), |
| 33993 | /* 93567 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33994 | /* 93569 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33995 | /* 93571 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33996 | /* 93573 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33997 | /* 93577 */ GIR_RootConstrainSelectedInstOperands, |
| 33998 | /* 93578 */ // GIR_Coverage, 5478, |
| 33999 | /* 93578 */ GIR_EraseRootFromParent_Done, |
| 34000 | /* 93579 */ // Label 2875: @93579 |
| 34001 | /* 93579 */ GIM_Try, /*On fail goto*//*Label 2876*/ GIMT_Encode4(93603), // Rule ID 5479 // |
| 34002 | /* 93584 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34003 | /* 93588 */ // (intrinsic_void 3954:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34004 | /* 93588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq), |
| 34005 | /* 93591 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34006 | /* 93593 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34007 | /* 93595 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34008 | /* 93597 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34009 | /* 93601 */ GIR_RootConstrainSelectedInstOperands, |
| 34010 | /* 93602 */ // GIR_Coverage, 5479, |
| 34011 | /* 93602 */ GIR_EraseRootFromParent_Done, |
| 34012 | /* 93603 */ // Label 2876: @93603 |
| 34013 | /* 93603 */ GIM_Reject, |
| 34014 | /* 93604 */ // Label 2874: @93604 |
| 34015 | /* 93604 */ GIM_Try, /*On fail goto*//*Label 2877*/ GIMT_Encode4(93632), // Rule ID 5562 // |
| 34016 | /* 93609 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34017 | /* 93613 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34018 | /* 93617 */ // (intrinsic_void 3954:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34019 | /* 93617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB16_rq), |
| 34020 | /* 93620 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34021 | /* 93622 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34022 | /* 93624 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34023 | /* 93626 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34024 | /* 93630 */ GIR_RootConstrainSelectedInstOperands, |
| 34025 | /* 93631 */ // GIR_Coverage, 5562, |
| 34026 | /* 93631 */ GIR_EraseRootFromParent_Done, |
| 34027 | /* 93632 */ // Label 2877: @93632 |
| 34028 | /* 93632 */ GIM_Try, /*On fail goto*//*Label 2878*/ GIMT_Encode4(93690), |
| 34029 | /* 93637 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34030 | /* 93641 */ GIM_Try, /*On fail goto*//*Label 2879*/ GIMT_Encode4(93665), // Rule ID 5566 // |
| 34031 | /* 93646 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34032 | /* 93650 */ // (intrinsic_void 3954:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34033 | /* 93650 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u), |
| 34034 | /* 93653 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34035 | /* 93655 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34036 | /* 93657 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34037 | /* 93659 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34038 | /* 93663 */ GIR_RootConstrainSelectedInstOperands, |
| 34039 | /* 93664 */ // GIR_Coverage, 5566, |
| 34040 | /* 93664 */ GIR_EraseRootFromParent_Done, |
| 34041 | /* 93665 */ // Label 2879: @93665 |
| 34042 | /* 93665 */ GIM_Try, /*On fail goto*//*Label 2880*/ GIMT_Encode4(93689), // Rule ID 5567 // |
| 34043 | /* 93670 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34044 | /* 93674 */ // (intrinsic_void 3954:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34045 | /* 93674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq), |
| 34046 | /* 93677 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34047 | /* 93679 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34048 | /* 93681 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34049 | /* 93683 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34050 | /* 93687 */ GIR_RootConstrainSelectedInstOperands, |
| 34051 | /* 93688 */ // GIR_Coverage, 5567, |
| 34052 | /* 93688 */ GIR_EraseRootFromParent_Done, |
| 34053 | /* 93689 */ // Label 2880: @93689 |
| 34054 | /* 93689 */ GIM_Reject, |
| 34055 | /* 93690 */ // Label 2878: @93690 |
| 34056 | /* 93690 */ GIM_Reject, |
| 34057 | /* 93691 */ // Label 2873: @93691 |
| 34058 | /* 93691 */ GIM_Reject, |
| 34059 | /* 93692 */ // Label 2869: @93692 |
| 34060 | /* 93692 */ GIM_Try, /*On fail goto*//*Label 2881*/ GIMT_Encode4(93915), |
| 34061 | /* 93697 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34062 | /* 93700 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34063 | /* 93703 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34064 | /* 93706 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34065 | /* 93710 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34066 | /* 93714 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34067 | /* 93718 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34068 | /* 93722 */ GIM_Try, /*On fail goto*//*Label 2882*/ GIMT_Encode4(93750), // Rule ID 5564 // |
| 34069 | /* 93727 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34070 | /* 93731 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34071 | /* 93735 */ // (intrinsic_void 3954:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34072 | /* 93735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB32_rq), |
| 34073 | /* 93738 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34074 | /* 93740 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34075 | /* 93742 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34076 | /* 93744 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34077 | /* 93748 */ GIR_RootConstrainSelectedInstOperands, |
| 34078 | /* 93749 */ // GIR_Coverage, 5564, |
| 34079 | /* 93749 */ GIR_EraseRootFromParent_Done, |
| 34080 | /* 93750 */ // Label 2882: @93750 |
| 34081 | /* 93750 */ GIM_Try, /*On fail goto*//*Label 2883*/ GIMT_Encode4(93808), |
| 34082 | /* 93755 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34083 | /* 93759 */ GIM_Try, /*On fail goto*//*Label 2884*/ GIMT_Encode4(93783), // Rule ID 5570 // |
| 34084 | /* 93764 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34085 | /* 93768 */ // (intrinsic_void 3954:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34086 | /* 93768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq_u), |
| 34087 | /* 93771 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34088 | /* 93773 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34089 | /* 93775 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34090 | /* 93777 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34091 | /* 93781 */ GIR_RootConstrainSelectedInstOperands, |
| 34092 | /* 93782 */ // GIR_Coverage, 5570, |
| 34093 | /* 93782 */ GIR_EraseRootFromParent_Done, |
| 34094 | /* 93783 */ // Label 2884: @93783 |
| 34095 | /* 93783 */ GIM_Try, /*On fail goto*//*Label 2885*/ GIMT_Encode4(93807), // Rule ID 5571 // |
| 34096 | /* 93788 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34097 | /* 93792 */ // (intrinsic_void 3954:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34098 | /* 93792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq), |
| 34099 | /* 93795 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34100 | /* 93797 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34101 | /* 93799 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34102 | /* 93801 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34103 | /* 93805 */ GIR_RootConstrainSelectedInstOperands, |
| 34104 | /* 93806 */ // GIR_Coverage, 5571, |
| 34105 | /* 93806 */ GIR_EraseRootFromParent_Done, |
| 34106 | /* 93807 */ // Label 2885: @93807 |
| 34107 | /* 93807 */ GIM_Reject, |
| 34108 | /* 93808 */ // Label 2883: @93808 |
| 34109 | /* 93808 */ GIM_Try, /*On fail goto*//*Label 2886*/ GIMT_Encode4(93914), |
| 34110 | /* 93813 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34111 | /* 93817 */ GIM_Try, /*On fail goto*//*Label 2887*/ GIMT_Encode4(93841), // Rule ID 5574 // |
| 34112 | /* 93822 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34113 | /* 93826 */ // (intrinsic_void 3954:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34114 | /* 93826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u), |
| 34115 | /* 93829 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34116 | /* 93831 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34117 | /* 93833 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34118 | /* 93835 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34119 | /* 93839 */ GIR_RootConstrainSelectedInstOperands, |
| 34120 | /* 93840 */ // GIR_Coverage, 5574, |
| 34121 | /* 93840 */ GIR_EraseRootFromParent_Done, |
| 34122 | /* 93841 */ // Label 2887: @93841 |
| 34123 | /* 93841 */ GIM_Try, /*On fail goto*//*Label 2888*/ GIMT_Encode4(93865), // Rule ID 5575 // |
| 34124 | /* 93846 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34125 | /* 93850 */ // (intrinsic_void 3954:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34126 | /* 93850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq), |
| 34127 | /* 93853 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34128 | /* 93855 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34129 | /* 93857 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34130 | /* 93859 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34131 | /* 93863 */ GIR_RootConstrainSelectedInstOperands, |
| 34132 | /* 93864 */ // GIR_Coverage, 5575, |
| 34133 | /* 93864 */ GIR_EraseRootFromParent_Done, |
| 34134 | /* 93865 */ // Label 2888: @93865 |
| 34135 | /* 93865 */ GIM_Try, /*On fail goto*//*Label 2889*/ GIMT_Encode4(93889), // Rule ID 5578 // |
| 34136 | /* 93870 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34137 | /* 93874 */ // (intrinsic_void 3954:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34138 | /* 93874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u), |
| 34139 | /* 93877 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34140 | /* 93879 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34141 | /* 93881 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34142 | /* 93883 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34143 | /* 93887 */ GIR_RootConstrainSelectedInstOperands, |
| 34144 | /* 93888 */ // GIR_Coverage, 5578, |
| 34145 | /* 93888 */ GIR_EraseRootFromParent_Done, |
| 34146 | /* 93889 */ // Label 2889: @93889 |
| 34147 | /* 93889 */ GIM_Try, /*On fail goto*//*Label 2890*/ GIMT_Encode4(93913), // Rule ID 5579 // |
| 34148 | /* 93894 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34149 | /* 93898 */ // (intrinsic_void 3954:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34150 | /* 93898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq), |
| 34151 | /* 93901 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34152 | /* 93903 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34153 | /* 93905 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34154 | /* 93907 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34155 | /* 93911 */ GIR_RootConstrainSelectedInstOperands, |
| 34156 | /* 93912 */ // GIR_Coverage, 5579, |
| 34157 | /* 93912 */ GIR_EraseRootFromParent_Done, |
| 34158 | /* 93913 */ // Label 2890: @93913 |
| 34159 | /* 93913 */ GIM_Reject, |
| 34160 | /* 93914 */ // Label 2886: @93914 |
| 34161 | /* 93914 */ GIM_Reject, |
| 34162 | /* 93915 */ // Label 2881: @93915 |
| 34163 | /* 93915 */ GIM_Reject, |
| 34164 | /* 93916 */ // Label 2870: @93916 |
| 34165 | /* 93916 */ GIM_Try, /*On fail goto*//*Label 2891*/ GIMT_Encode4(93999), |
| 34166 | /* 93921 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 34167 | /* 93924 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34168 | /* 93927 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34169 | /* 93930 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34170 | /* 93934 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34171 | /* 93938 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34172 | /* 93942 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34173 | /* 93946 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 34174 | /* 93950 */ GIM_Try, /*On fail goto*//*Label 2892*/ GIMT_Encode4(93974), // Rule ID 5582 // |
| 34175 | /* 93955 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34176 | /* 93959 */ // (intrinsic_void 3954:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRD64_rq_u MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34177 | /* 93959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq_u), |
| 34178 | /* 93962 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34179 | /* 93964 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34180 | /* 93966 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34181 | /* 93968 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34182 | /* 93972 */ GIR_RootConstrainSelectedInstOperands, |
| 34183 | /* 93973 */ // GIR_Coverage, 5582, |
| 34184 | /* 93973 */ GIR_EraseRootFromParent_Done, |
| 34185 | /* 93974 */ // Label 2892: @93974 |
| 34186 | /* 93974 */ GIM_Try, /*On fail goto*//*Label 2893*/ GIMT_Encode4(93998), // Rule ID 5583 // |
| 34187 | /* 93979 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 34188 | /* 93983 */ // (intrinsic_void 3954:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 3:{ *:[i32] }) => (MVE_VSTRD64_rq MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34189 | /* 93983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq), |
| 34190 | /* 93986 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34191 | /* 93988 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34192 | /* 93990 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34193 | /* 93992 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34194 | /* 93996 */ GIR_RootConstrainSelectedInstOperands, |
| 34195 | /* 93997 */ // GIR_Coverage, 5583, |
| 34196 | /* 93997 */ GIR_EraseRootFromParent_Done, |
| 34197 | /* 93998 */ // Label 2893: @93998 |
| 34198 | /* 93998 */ GIM_Reject, |
| 34199 | /* 93999 */ // Label 2891: @93999 |
| 34200 | /* 93999 */ GIM_Reject, |
| 34201 | /* 94000 */ // Label 2871: @94000 |
| 34202 | /* 94000 */ GIM_Reject, |
| 34203 | /* 94001 */ // Label 2866: @94001 |
| 34204 | /* 94001 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2894*/ GIMT_Encode4(94064), GIMT_Encode2(GIFBS_IsARM), // Rule ID 257 // |
| 34205 | /* 94008 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr), |
| 34206 | /* 94013 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 34207 | /* 94016 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34208 | /* 94019 */ // MIs[0] cop |
| 34209 | /* 94019 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34210 | /* 94022 */ // MIs[0] opc1 |
| 34211 | /* 94022 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34212 | /* 94025 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 34213 | /* 94029 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 34214 | /* 94033 */ // MIs[0] CRm |
| 34215 | /* 94033 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34216 | /* 94036 */ // (intrinsic_void 3739:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 34217 | /* 94036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR), |
| 34218 | /* 94039 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34219 | /* 94041 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34220 | /* 94043 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 34221 | /* 94045 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 34222 | /* 94047 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34223 | /* 94049 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34224 | /* 94052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34225 | /* 94058 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34226 | /* 94062 */ GIR_RootConstrainSelectedInstOperands, |
| 34227 | /* 94063 */ // GIR_Coverage, 257, |
| 34228 | /* 94063 */ GIR_EraseRootFromParent_Done, |
| 34229 | /* 94064 */ // Label 2894: @94064 |
| 34230 | /* 94064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2895*/ GIMT_Encode4(94118), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 258 // |
| 34231 | /* 94071 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2), |
| 34232 | /* 94076 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 34233 | /* 94079 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34234 | /* 94082 */ // MIs[0] cop |
| 34235 | /* 94082 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34236 | /* 94085 */ // MIs[0] opc1 |
| 34237 | /* 94085 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34238 | /* 94088 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 34239 | /* 94092 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 34240 | /* 94096 */ // MIs[0] CRm |
| 34241 | /* 94096 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34242 | /* 94099 */ // (intrinsic_void 3740:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 34243 | /* 94099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR2), |
| 34244 | /* 94102 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34245 | /* 94104 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34246 | /* 94106 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 34247 | /* 94108 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 34248 | /* 94110 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34249 | /* 94112 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34250 | /* 94116 */ GIR_RootConstrainSelectedInstOperands, |
| 34251 | /* 94117 */ // GIR_Coverage, 258, |
| 34252 | /* 94117 */ GIR_EraseRootFromParent_Done, |
| 34253 | /* 94118 */ // Label 2895: @94118 |
| 34254 | /* 94118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2896*/ GIMT_Encode4(94181), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 595 // |
| 34255 | /* 94125 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr), |
| 34256 | /* 94130 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 34257 | /* 94133 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34258 | /* 94136 */ // MIs[0] cop |
| 34259 | /* 94136 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34260 | /* 94139 */ // MIs[0] opc1 |
| 34261 | /* 94139 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34262 | /* 94142 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34263 | /* 94146 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34264 | /* 94150 */ // MIs[0] CRm |
| 34265 | /* 94150 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34266 | /* 94153 */ // (intrinsic_void 3739:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 34267 | /* 94153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR), |
| 34268 | /* 94156 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34269 | /* 94158 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34270 | /* 94160 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 34271 | /* 94162 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 34272 | /* 94164 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34273 | /* 94166 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34274 | /* 94169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34275 | /* 94175 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34276 | /* 94179 */ GIR_RootConstrainSelectedInstOperands, |
| 34277 | /* 94180 */ // GIR_Coverage, 595, |
| 34278 | /* 94180 */ GIR_EraseRootFromParent_Done, |
| 34279 | /* 94181 */ // Label 2896: @94181 |
| 34280 | /* 94181 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2897*/ GIMT_Encode4(94244), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 596 // |
| 34281 | /* 94188 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2), |
| 34282 | /* 94193 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 34283 | /* 94196 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34284 | /* 94199 */ // MIs[0] cop |
| 34285 | /* 94199 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34286 | /* 94202 */ // MIs[0] opc1 |
| 34287 | /* 94202 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34288 | /* 94205 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34289 | /* 94209 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34290 | /* 94213 */ // MIs[0] CRm |
| 34291 | /* 94213 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34292 | /* 94216 */ // (intrinsic_void 3740:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 34293 | /* 94216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR2), |
| 34294 | /* 94219 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34295 | /* 94221 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34296 | /* 94223 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 34297 | /* 94225 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 34298 | /* 94227 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34299 | /* 94229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34300 | /* 94232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34301 | /* 94238 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34302 | /* 94242 */ GIR_RootConstrainSelectedInstOperands, |
| 34303 | /* 94243 */ // GIR_Coverage, 596, |
| 34304 | /* 94243 */ GIR_EraseRootFromParent_Done, |
| 34305 | /* 94244 */ // Label 2897: @94244 |
| 34306 | /* 94244 */ GIM_Reject, |
| 34307 | /* 94245 */ // Label 2865: @94245 |
| 34308 | /* 94245 */ GIM_Try, /*On fail goto*//*Label 2898*/ GIMT_Encode4(96150), |
| 34309 | /* 94250 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, |
| 34310 | /* 94253 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2899*/ GIMT_Encode4(94313), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 245 // |
| 34311 | /* 94260 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp), |
| 34312 | /* 94265 */ // MIs[0] cop |
| 34313 | /* 94265 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34314 | /* 94268 */ // MIs[0] opc1 |
| 34315 | /* 94268 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34316 | /* 94271 */ // MIs[0] CRd |
| 34317 | /* 94271 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 34318 | /* 94274 */ // MIs[0] CRn |
| 34319 | /* 94274 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 34320 | /* 94277 */ // MIs[0] CRm |
| 34321 | /* 94277 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34322 | /* 94280 */ // MIs[0] opc2 |
| 34323 | /* 94280 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 34324 | /* 94283 */ // (intrinsic_void 3707:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 34325 | /* 94283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP), |
| 34326 | /* 94286 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34327 | /* 94288 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34328 | /* 94290 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 34329 | /* 94292 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 34330 | /* 94294 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34331 | /* 94296 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 34332 | /* 94298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34333 | /* 94301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34334 | /* 94307 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34335 | /* 94311 */ GIR_RootConstrainSelectedInstOperands, |
| 34336 | /* 94312 */ // GIR_Coverage, 245, |
| 34337 | /* 94312 */ GIR_EraseRootFromParent_Done, |
| 34338 | /* 94313 */ // Label 2899: @94313 |
| 34339 | /* 94313 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2900*/ GIMT_Encode4(94364), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 246 // |
| 34340 | /* 94320 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2), |
| 34341 | /* 94325 */ // MIs[0] cop |
| 34342 | /* 94325 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34343 | /* 94328 */ // MIs[0] opc1 |
| 34344 | /* 94328 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34345 | /* 94331 */ // MIs[0] CRd |
| 34346 | /* 94331 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 34347 | /* 94334 */ // MIs[0] CRn |
| 34348 | /* 94334 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 34349 | /* 94337 */ // MIs[0] CRm |
| 34350 | /* 94337 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34351 | /* 94340 */ // MIs[0] opc2 |
| 34352 | /* 94340 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 34353 | /* 94343 */ // (intrinsic_void 3708:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 34354 | /* 94343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP2), |
| 34355 | /* 94346 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34356 | /* 94348 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34357 | /* 94350 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 34358 | /* 94352 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 34359 | /* 94354 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34360 | /* 94356 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 34361 | /* 94358 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34362 | /* 94362 */ GIR_RootConstrainSelectedInstOperands, |
| 34363 | /* 94363 */ // GIR_Coverage, 246, |
| 34364 | /* 94363 */ GIR_EraseRootFromParent_Done, |
| 34365 | /* 94364 */ // Label 2900: @94364 |
| 34366 | /* 94364 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2901*/ GIMT_Encode4(94424), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 597 // |
| 34367 | /* 94371 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp), |
| 34368 | /* 94376 */ // MIs[0] cop |
| 34369 | /* 94376 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34370 | /* 94379 */ // MIs[0] opc1 |
| 34371 | /* 94379 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34372 | /* 94382 */ // MIs[0] CRd |
| 34373 | /* 94382 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 34374 | /* 94385 */ // MIs[0] CRn |
| 34375 | /* 94385 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 34376 | /* 94388 */ // MIs[0] CRm |
| 34377 | /* 94388 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34378 | /* 94391 */ // MIs[0] opc2 |
| 34379 | /* 94391 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 34380 | /* 94394 */ // (intrinsic_void 3707:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 34381 | /* 94394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP), |
| 34382 | /* 94397 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34383 | /* 94399 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34384 | /* 94401 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 34385 | /* 94403 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 34386 | /* 94405 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34387 | /* 94407 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 34388 | /* 94409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34389 | /* 94412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34390 | /* 94418 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34391 | /* 94422 */ GIR_RootConstrainSelectedInstOperands, |
| 34392 | /* 94423 */ // GIR_Coverage, 597, |
| 34393 | /* 94423 */ GIR_EraseRootFromParent_Done, |
| 34394 | /* 94424 */ // Label 2901: @94424 |
| 34395 | /* 94424 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2902*/ GIMT_Encode4(94484), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 598 // |
| 34396 | /* 94431 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2), |
| 34397 | /* 94436 */ // MIs[0] cop |
| 34398 | /* 94436 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34399 | /* 94439 */ // MIs[0] opc1 |
| 34400 | /* 94439 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34401 | /* 94442 */ // MIs[0] CRd |
| 34402 | /* 94442 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 34403 | /* 94445 */ // MIs[0] CRn |
| 34404 | /* 94445 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 34405 | /* 94448 */ // MIs[0] CRm |
| 34406 | /* 94448 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34407 | /* 94451 */ // MIs[0] opc2 |
| 34408 | /* 94451 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 34409 | /* 94454 */ // (intrinsic_void 3708:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 34410 | /* 94454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP2), |
| 34411 | /* 94457 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34412 | /* 94459 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34413 | /* 94461 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 34414 | /* 94463 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 34415 | /* 94465 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34416 | /* 94467 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 34417 | /* 94469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34418 | /* 94472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34419 | /* 94478 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34420 | /* 94482 */ GIR_RootConstrainSelectedInstOperands, |
| 34421 | /* 94483 */ // GIR_Coverage, 598, |
| 34422 | /* 94483 */ GIR_EraseRootFromParent_Done, |
| 34423 | /* 94484 */ // Label 2902: @94484 |
| 34424 | /* 94484 */ GIM_Try, /*On fail goto*//*Label 2903*/ GIMT_Encode4(95902), |
| 34425 | /* 94489 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34426 | /* 94494 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 2908*/ GIMT_Encode4(95901), |
| 34427 | /* 94505 */ /*GILLT_v16s8*//*Label 2904*/ GIMT_Encode4(94529), GIMT_Encode4(0), |
| 34428 | /* 94513 */ /*GILLT_v8s16*//*Label 2905*/ GIMT_Encode4(94620), GIMT_Encode4(0), |
| 34429 | /* 94521 */ /*GILLT_v4s32*//*Label 2906*/ GIMT_Encode4(95073), |
| 34430 | /* 94525 */ /*GILLT_v2s64*//*Label 2907*/ GIMT_Encode4(95638), |
| 34431 | /* 94529 */ // Label 2904: @94529 |
| 34432 | /* 94529 */ GIM_Try, /*On fail goto*//*Label 2909*/ GIMT_Encode4(94619), |
| 34433 | /* 94534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 34434 | /* 94537 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34435 | /* 94540 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34436 | /* 94543 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34437 | /* 94546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34438 | /* 94550 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34439 | /* 94554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34440 | /* 94558 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34441 | /* 94562 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34442 | /* 94566 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34443 | /* 94570 */ GIM_Try, /*On fail goto*//*Label 2910*/ GIMT_Encode4(94594), // Rule ID 5476 // |
| 34444 | /* 94575 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34445 | /* 94579 */ // (intrinsic_w_chain:{ *:[v16i8] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) |
| 34446 | /* 94579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq), |
| 34447 | /* 94582 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34448 | /* 94584 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34449 | /* 94586 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34450 | /* 94588 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34451 | /* 94592 */ GIR_RootConstrainSelectedInstOperands, |
| 34452 | /* 94593 */ // GIR_Coverage, 5476, |
| 34453 | /* 94593 */ GIR_EraseRootFromParent_Done, |
| 34454 | /* 94594 */ // Label 2910: @94594 |
| 34455 | /* 94594 */ GIM_Try, /*On fail goto*//*Label 2911*/ GIMT_Encode4(94618), // Rule ID 5484 // |
| 34456 | /* 94599 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34457 | /* 94603 */ // (intrinsic_w_chain:{ *:[v16i8] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) |
| 34458 | /* 94603 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq), |
| 34459 | /* 94606 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34460 | /* 94608 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34461 | /* 94610 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34462 | /* 94612 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34463 | /* 94616 */ GIR_RootConstrainSelectedInstOperands, |
| 34464 | /* 94617 */ // GIR_Coverage, 5484, |
| 34465 | /* 94617 */ GIR_EraseRootFromParent_Done, |
| 34466 | /* 94618 */ // Label 2911: @94618 |
| 34467 | /* 94618 */ GIM_Reject, |
| 34468 | /* 94619 */ // Label 2909: @94619 |
| 34469 | /* 94619 */ GIM_Reject, |
| 34470 | /* 94620 */ // Label 2905: @94620 |
| 34471 | /* 94620 */ GIM_Try, /*On fail goto*//*Label 2912*/ GIMT_Encode4(95072), |
| 34472 | /* 94625 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34473 | /* 94628 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34474 | /* 94631 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34475 | /* 94634 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34476 | /* 94637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34477 | /* 94641 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34478 | /* 94645 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34479 | /* 94649 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34480 | /* 94653 */ GIM_Try, /*On fail goto*//*Label 2913*/ GIMT_Encode4(94719), |
| 34481 | /* 94658 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34482 | /* 94662 */ GIM_Try, /*On fail goto*//*Label 2914*/ GIMT_Encode4(94690), // Rule ID 5472 // |
| 34483 | /* 94667 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34484 | /* 94671 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34485 | /* 94675 */ // (intrinsic_w_chain:{ *:[v8i16] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34486 | /* 94675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34487 | /* 94678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34488 | /* 94680 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34489 | /* 94682 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34490 | /* 94684 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34491 | /* 94688 */ GIR_RootConstrainSelectedInstOperands, |
| 34492 | /* 94689 */ // GIR_Coverage, 5472, |
| 34493 | /* 94689 */ GIR_EraseRootFromParent_Done, |
| 34494 | /* 94690 */ // Label 2914: @94690 |
| 34495 | /* 94690 */ GIM_Try, /*On fail goto*//*Label 2915*/ GIMT_Encode4(94718), // Rule ID 5473 // |
| 34496 | /* 94695 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34497 | /* 94699 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34498 | /* 94703 */ // (intrinsic_w_chain:{ *:[v8i16] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34499 | /* 94703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34500 | /* 94706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34501 | /* 94708 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34502 | /* 94710 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34503 | /* 94712 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34504 | /* 94716 */ GIR_RootConstrainSelectedInstOperands, |
| 34505 | /* 94717 */ // GIR_Coverage, 5473, |
| 34506 | /* 94717 */ GIR_EraseRootFromParent_Done, |
| 34507 | /* 94718 */ // Label 2915: @94718 |
| 34508 | /* 94718 */ GIM_Reject, |
| 34509 | /* 94719 */ // Label 2913: @94719 |
| 34510 | /* 94719 */ GIM_Try, /*On fail goto*//*Label 2916*/ GIMT_Encode4(94781), |
| 34511 | /* 94724 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34512 | /* 94728 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34513 | /* 94732 */ GIM_Try, /*On fail goto*//*Label 2917*/ GIMT_Encode4(94756), // Rule ID 5486 // |
| 34514 | /* 94737 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34515 | /* 94741 */ // (intrinsic_w_chain:{ *:[v8i16] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34516 | /* 94741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU16_rq), |
| 34517 | /* 94744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34518 | /* 94746 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34519 | /* 94748 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34520 | /* 94750 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34521 | /* 94754 */ GIR_RootConstrainSelectedInstOperands, |
| 34522 | /* 94755 */ // GIR_Coverage, 5486, |
| 34523 | /* 94755 */ GIR_EraseRootFromParent_Done, |
| 34524 | /* 94756 */ // Label 2917: @94756 |
| 34525 | /* 94756 */ GIM_Try, /*On fail goto*//*Label 2918*/ GIMT_Encode4(94780), // Rule ID 5488 // |
| 34526 | /* 94761 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34527 | /* 94765 */ // (intrinsic_w_chain:{ *:[v8i16] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34528 | /* 94765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS16_rq), |
| 34529 | /* 94768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34530 | /* 94770 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34531 | /* 94772 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34532 | /* 94774 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34533 | /* 94778 */ GIR_RootConstrainSelectedInstOperands, |
| 34534 | /* 94779 */ // GIR_Coverage, 5488, |
| 34535 | /* 94779 */ GIR_EraseRootFromParent_Done, |
| 34536 | /* 94780 */ // Label 2918: @94780 |
| 34537 | /* 94780 */ GIM_Reject, |
| 34538 | /* 94781 */ // Label 2916: @94781 |
| 34539 | /* 94781 */ GIM_Try, /*On fail goto*//*Label 2919*/ GIMT_Encode4(95071), |
| 34540 | /* 94786 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34541 | /* 94790 */ GIM_Try, /*On fail goto*//*Label 2920*/ GIMT_Encode4(94818), // Rule ID 5494 // |
| 34542 | /* 94795 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34543 | /* 94799 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34544 | /* 94803 */ // (intrinsic_w_chain:{ *:[v8i16] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34545 | /* 94803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34546 | /* 94806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34547 | /* 94808 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34548 | /* 94810 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34549 | /* 94812 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34550 | /* 94816 */ GIR_RootConstrainSelectedInstOperands, |
| 34551 | /* 94817 */ // GIR_Coverage, 5494, |
| 34552 | /* 94817 */ GIR_EraseRootFromParent_Done, |
| 34553 | /* 94818 */ // Label 2920: @94818 |
| 34554 | /* 94818 */ GIM_Try, /*On fail goto*//*Label 2921*/ GIMT_Encode4(94846), // Rule ID 5495 // |
| 34555 | /* 94823 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34556 | /* 94827 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34557 | /* 94831 */ // (intrinsic_w_chain:{ *:[v8i16] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34558 | /* 94831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34559 | /* 94834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34560 | /* 94836 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34561 | /* 94838 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34562 | /* 94840 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34563 | /* 94844 */ GIR_RootConstrainSelectedInstOperands, |
| 34564 | /* 94845 */ // GIR_Coverage, 5495, |
| 34565 | /* 94845 */ GIR_EraseRootFromParent_Done, |
| 34566 | /* 94846 */ // Label 2921: @94846 |
| 34567 | /* 94846 */ GIM_Try, /*On fail goto*//*Label 2922*/ GIMT_Encode4(94874), // Rule ID 5498 // |
| 34568 | /* 94851 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34569 | /* 94855 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34570 | /* 94859 */ // (intrinsic_w_chain:{ *:[v8i16] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34571 | /* 94859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34572 | /* 94862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34573 | /* 94864 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34574 | /* 94866 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34575 | /* 94868 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34576 | /* 94872 */ GIR_RootConstrainSelectedInstOperands, |
| 34577 | /* 94873 */ // GIR_Coverage, 5498, |
| 34578 | /* 94873 */ GIR_EraseRootFromParent_Done, |
| 34579 | /* 94874 */ // Label 2922: @94874 |
| 34580 | /* 94874 */ GIM_Try, /*On fail goto*//*Label 2923*/ GIMT_Encode4(94902), // Rule ID 5499 // |
| 34581 | /* 94879 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34582 | /* 94883 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34583 | /* 94887 */ // (intrinsic_w_chain:{ *:[v8i16] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34584 | /* 94887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34585 | /* 94890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34586 | /* 94892 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34587 | /* 94894 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34588 | /* 94896 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34589 | /* 94900 */ GIR_RootConstrainSelectedInstOperands, |
| 34590 | /* 94901 */ // GIR_Coverage, 5499, |
| 34591 | /* 94901 */ GIR_EraseRootFromParent_Done, |
| 34592 | /* 94902 */ // Label 2923: @94902 |
| 34593 | /* 94902 */ GIM_Try, /*On fail goto*//*Label 2924*/ GIMT_Encode4(94930), // Rule ID 5502 // |
| 34594 | /* 94907 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34595 | /* 94911 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34596 | /* 94915 */ // (intrinsic_w_chain:{ *:[v8i16] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34597 | /* 94915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34598 | /* 94918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34599 | /* 94920 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34600 | /* 94922 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34601 | /* 94924 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34602 | /* 94928 */ GIR_RootConstrainSelectedInstOperands, |
| 34603 | /* 94929 */ // GIR_Coverage, 5502, |
| 34604 | /* 94929 */ GIR_EraseRootFromParent_Done, |
| 34605 | /* 94930 */ // Label 2924: @94930 |
| 34606 | /* 94930 */ GIM_Try, /*On fail goto*//*Label 2925*/ GIMT_Encode4(94958), // Rule ID 5503 // |
| 34607 | /* 94935 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34608 | /* 94939 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34609 | /* 94943 */ // (intrinsic_w_chain:{ *:[v8i16] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34610 | /* 94943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34611 | /* 94946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34612 | /* 94948 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34613 | /* 94950 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34614 | /* 94952 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34615 | /* 94956 */ GIR_RootConstrainSelectedInstOperands, |
| 34616 | /* 94957 */ // GIR_Coverage, 5503, |
| 34617 | /* 94957 */ GIR_EraseRootFromParent_Done, |
| 34618 | /* 94958 */ // Label 2925: @94958 |
| 34619 | /* 94958 */ GIM_Try, /*On fail goto*//*Label 2926*/ GIMT_Encode4(94986), // Rule ID 5506 // |
| 34620 | /* 94963 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34621 | /* 94967 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34622 | /* 94971 */ // (intrinsic_w_chain:{ *:[v8f16] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34623 | /* 94971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34624 | /* 94974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34625 | /* 94976 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34626 | /* 94978 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34627 | /* 94980 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34628 | /* 94984 */ GIR_RootConstrainSelectedInstOperands, |
| 34629 | /* 94985 */ // GIR_Coverage, 5506, |
| 34630 | /* 94985 */ GIR_EraseRootFromParent_Done, |
| 34631 | /* 94986 */ // Label 2926: @94986 |
| 34632 | /* 94986 */ GIM_Try, /*On fail goto*//*Label 2927*/ GIMT_Encode4(95014), // Rule ID 5507 // |
| 34633 | /* 94991 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34634 | /* 94995 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34635 | /* 94999 */ // (intrinsic_w_chain:{ *:[v8f16] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34636 | /* 94999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34637 | /* 95002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34638 | /* 95004 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34639 | /* 95006 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34640 | /* 95008 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34641 | /* 95012 */ GIR_RootConstrainSelectedInstOperands, |
| 34642 | /* 95013 */ // GIR_Coverage, 5507, |
| 34643 | /* 95013 */ GIR_EraseRootFromParent_Done, |
| 34644 | /* 95014 */ // Label 2927: @95014 |
| 34645 | /* 95014 */ GIM_Try, /*On fail goto*//*Label 2928*/ GIMT_Encode4(95042), // Rule ID 5510 // |
| 34646 | /* 95019 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34647 | /* 95023 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34648 | /* 95027 */ // (intrinsic_w_chain:{ *:[v8f16] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34649 | /* 95027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34650 | /* 95030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34651 | /* 95032 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34652 | /* 95034 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34653 | /* 95036 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34654 | /* 95040 */ GIR_RootConstrainSelectedInstOperands, |
| 34655 | /* 95041 */ // GIR_Coverage, 5510, |
| 34656 | /* 95041 */ GIR_EraseRootFromParent_Done, |
| 34657 | /* 95042 */ // Label 2928: @95042 |
| 34658 | /* 95042 */ GIM_Try, /*On fail goto*//*Label 2929*/ GIMT_Encode4(95070), // Rule ID 5511 // |
| 34659 | /* 95047 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34660 | /* 95051 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34661 | /* 95055 */ // (intrinsic_w_chain:{ *:[v8f16] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34662 | /* 95055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34663 | /* 95058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34664 | /* 95060 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34665 | /* 95062 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34666 | /* 95064 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34667 | /* 95068 */ GIR_RootConstrainSelectedInstOperands, |
| 34668 | /* 95069 */ // GIR_Coverage, 5511, |
| 34669 | /* 95069 */ GIR_EraseRootFromParent_Done, |
| 34670 | /* 95070 */ // Label 2929: @95070 |
| 34671 | /* 95070 */ GIM_Reject, |
| 34672 | /* 95071 */ // Label 2919: @95071 |
| 34673 | /* 95071 */ GIM_Reject, |
| 34674 | /* 95072 */ // Label 2912: @95072 |
| 34675 | /* 95072 */ GIM_Reject, |
| 34676 | /* 95073 */ // Label 2906: @95073 |
| 34677 | /* 95073 */ GIM_Try, /*On fail goto*//*Label 2930*/ GIMT_Encode4(95637), |
| 34678 | /* 95078 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34679 | /* 95081 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34680 | /* 95084 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34681 | /* 95087 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34682 | /* 95090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34683 | /* 95094 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34684 | /* 95098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34685 | /* 95102 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34686 | /* 95106 */ GIM_Try, /*On fail goto*//*Label 2931*/ GIMT_Encode4(95168), |
| 34687 | /* 95111 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34688 | /* 95115 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34689 | /* 95119 */ GIM_Try, /*On fail goto*//*Label 2932*/ GIMT_Encode4(95143), // Rule ID 5490 // |
| 34690 | /* 95124 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34691 | /* 95128 */ // (intrinsic_w_chain:{ *:[v4i32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34692 | /* 95128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU32_rq), |
| 34693 | /* 95131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34694 | /* 95133 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34695 | /* 95135 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34696 | /* 95137 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34697 | /* 95141 */ GIR_RootConstrainSelectedInstOperands, |
| 34698 | /* 95142 */ // GIR_Coverage, 5490, |
| 34699 | /* 95142 */ GIR_EraseRootFromParent_Done, |
| 34700 | /* 95143 */ // Label 2932: @95143 |
| 34701 | /* 95143 */ GIM_Try, /*On fail goto*//*Label 2933*/ GIMT_Encode4(95167), // Rule ID 5492 // |
| 34702 | /* 95148 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34703 | /* 95152 */ // (intrinsic_w_chain:{ *:[v4i32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34704 | /* 95152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS32_rq), |
| 34705 | /* 95155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34706 | /* 95157 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34707 | /* 95159 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34708 | /* 95161 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34709 | /* 95165 */ GIR_RootConstrainSelectedInstOperands, |
| 34710 | /* 95166 */ // GIR_Coverage, 5492, |
| 34711 | /* 95166 */ GIR_EraseRootFromParent_Done, |
| 34712 | /* 95167 */ // Label 2933: @95167 |
| 34713 | /* 95167 */ GIM_Reject, |
| 34714 | /* 95168 */ // Label 2931: @95168 |
| 34715 | /* 95168 */ GIM_Try, /*On fail goto*//*Label 2934*/ GIMT_Encode4(95290), |
| 34716 | /* 95173 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34717 | /* 95177 */ GIM_Try, /*On fail goto*//*Label 2935*/ GIMT_Encode4(95205), // Rule ID 5514 // |
| 34718 | /* 95182 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34719 | /* 95186 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34720 | /* 95190 */ // (intrinsic_w_chain:{ *:[v4i32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34721 | /* 95190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq_u), |
| 34722 | /* 95193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34723 | /* 95195 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34724 | /* 95197 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34725 | /* 95199 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34726 | /* 95203 */ GIR_RootConstrainSelectedInstOperands, |
| 34727 | /* 95204 */ // GIR_Coverage, 5514, |
| 34728 | /* 95204 */ GIR_EraseRootFromParent_Done, |
| 34729 | /* 95205 */ // Label 2935: @95205 |
| 34730 | /* 95205 */ GIM_Try, /*On fail goto*//*Label 2936*/ GIMT_Encode4(95233), // Rule ID 5515 // |
| 34731 | /* 95210 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34732 | /* 95214 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34733 | /* 95218 */ // (intrinsic_w_chain:{ *:[v4i32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34734 | /* 95218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq), |
| 34735 | /* 95221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34736 | /* 95223 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34737 | /* 95225 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34738 | /* 95227 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34739 | /* 95231 */ GIR_RootConstrainSelectedInstOperands, |
| 34740 | /* 95232 */ // GIR_Coverage, 5515, |
| 34741 | /* 95232 */ GIR_EraseRootFromParent_Done, |
| 34742 | /* 95233 */ // Label 2936: @95233 |
| 34743 | /* 95233 */ GIM_Try, /*On fail goto*//*Label 2937*/ GIMT_Encode4(95261), // Rule ID 5518 // |
| 34744 | /* 95238 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34745 | /* 95242 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34746 | /* 95246 */ // (intrinsic_w_chain:{ *:[v4i32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34747 | /* 95246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq_u), |
| 34748 | /* 95249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34749 | /* 95251 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34750 | /* 95253 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34751 | /* 95255 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34752 | /* 95259 */ GIR_RootConstrainSelectedInstOperands, |
| 34753 | /* 95260 */ // GIR_Coverage, 5518, |
| 34754 | /* 95260 */ GIR_EraseRootFromParent_Done, |
| 34755 | /* 95261 */ // Label 2937: @95261 |
| 34756 | /* 95261 */ GIM_Try, /*On fail goto*//*Label 2938*/ GIMT_Encode4(95289), // Rule ID 5519 // |
| 34757 | /* 95266 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34758 | /* 95270 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34759 | /* 95274 */ // (intrinsic_w_chain:{ *:[v4i32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34760 | /* 95274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq), |
| 34761 | /* 95277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34762 | /* 95279 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34763 | /* 95281 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34764 | /* 95283 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34765 | /* 95287 */ GIR_RootConstrainSelectedInstOperands, |
| 34766 | /* 95288 */ // GIR_Coverage, 5519, |
| 34767 | /* 95288 */ GIR_EraseRootFromParent_Done, |
| 34768 | /* 95289 */ // Label 2938: @95289 |
| 34769 | /* 95289 */ GIM_Reject, |
| 34770 | /* 95290 */ // Label 2934: @95290 |
| 34771 | /* 95290 */ GIM_Try, /*On fail goto*//*Label 2939*/ GIMT_Encode4(95636), |
| 34772 | /* 95295 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34773 | /* 95299 */ GIM_Try, /*On fail goto*//*Label 2940*/ GIMT_Encode4(95327), // Rule ID 5522 // |
| 34774 | /* 95304 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34775 | /* 95308 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34776 | /* 95312 */ // (intrinsic_w_chain:{ *:[v4i32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34777 | /* 95312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34778 | /* 95315 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34779 | /* 95317 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34780 | /* 95319 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34781 | /* 95321 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34782 | /* 95325 */ GIR_RootConstrainSelectedInstOperands, |
| 34783 | /* 95326 */ // GIR_Coverage, 5522, |
| 34784 | /* 95326 */ GIR_EraseRootFromParent_Done, |
| 34785 | /* 95327 */ // Label 2940: @95327 |
| 34786 | /* 95327 */ GIM_Try, /*On fail goto*//*Label 2941*/ GIMT_Encode4(95355), // Rule ID 5523 // |
| 34787 | /* 95332 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34788 | /* 95336 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34789 | /* 95340 */ // (intrinsic_w_chain:{ *:[v4i32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34790 | /* 95340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34791 | /* 95343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34792 | /* 95345 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34793 | /* 95347 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34794 | /* 95349 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34795 | /* 95353 */ GIR_RootConstrainSelectedInstOperands, |
| 34796 | /* 95354 */ // GIR_Coverage, 5523, |
| 34797 | /* 95354 */ GIR_EraseRootFromParent_Done, |
| 34798 | /* 95355 */ // Label 2941: @95355 |
| 34799 | /* 95355 */ GIM_Try, /*On fail goto*//*Label 2942*/ GIMT_Encode4(95383), // Rule ID 5526 // |
| 34800 | /* 95360 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34801 | /* 95364 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34802 | /* 95368 */ // (intrinsic_w_chain:{ *:[v4i32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34803 | /* 95368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34804 | /* 95371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34805 | /* 95373 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34806 | /* 95375 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34807 | /* 95377 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34808 | /* 95381 */ GIR_RootConstrainSelectedInstOperands, |
| 34809 | /* 95382 */ // GIR_Coverage, 5526, |
| 34810 | /* 95382 */ GIR_EraseRootFromParent_Done, |
| 34811 | /* 95383 */ // Label 2942: @95383 |
| 34812 | /* 95383 */ GIM_Try, /*On fail goto*//*Label 2943*/ GIMT_Encode4(95411), // Rule ID 5527 // |
| 34813 | /* 95388 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34814 | /* 95392 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34815 | /* 95396 */ // (intrinsic_w_chain:{ *:[v4i32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34816 | /* 95396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34817 | /* 95399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34818 | /* 95401 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34819 | /* 95403 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34820 | /* 95405 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34821 | /* 95409 */ GIR_RootConstrainSelectedInstOperands, |
| 34822 | /* 95410 */ // GIR_Coverage, 5527, |
| 34823 | /* 95410 */ GIR_EraseRootFromParent_Done, |
| 34824 | /* 95411 */ // Label 2943: @95411 |
| 34825 | /* 95411 */ GIM_Try, /*On fail goto*//*Label 2944*/ GIMT_Encode4(95439), // Rule ID 5530 // |
| 34826 | /* 95416 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34827 | /* 95420 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34828 | /* 95424 */ // (intrinsic_w_chain:{ *:[v4i32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34829 | /* 95424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34830 | /* 95427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34831 | /* 95429 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34832 | /* 95431 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34833 | /* 95433 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34834 | /* 95437 */ GIR_RootConstrainSelectedInstOperands, |
| 34835 | /* 95438 */ // GIR_Coverage, 5530, |
| 34836 | /* 95438 */ GIR_EraseRootFromParent_Done, |
| 34837 | /* 95439 */ // Label 2944: @95439 |
| 34838 | /* 95439 */ GIM_Try, /*On fail goto*//*Label 2945*/ GIMT_Encode4(95467), // Rule ID 5531 // |
| 34839 | /* 95444 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34840 | /* 95448 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34841 | /* 95452 */ // (intrinsic_w_chain:{ *:[v4i32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34842 | /* 95452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34843 | /* 95455 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34844 | /* 95457 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34845 | /* 95459 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34846 | /* 95461 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34847 | /* 95465 */ GIR_RootConstrainSelectedInstOperands, |
| 34848 | /* 95466 */ // GIR_Coverage, 5531, |
| 34849 | /* 95466 */ GIR_EraseRootFromParent_Done, |
| 34850 | /* 95467 */ // Label 2945: @95467 |
| 34851 | /* 95467 */ GIM_Try, /*On fail goto*//*Label 2946*/ GIMT_Encode4(95495), // Rule ID 5534 // |
| 34852 | /* 95472 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34853 | /* 95476 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34854 | /* 95480 */ // (intrinsic_w_chain:{ *:[v4i32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34855 | /* 95480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34856 | /* 95483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34857 | /* 95485 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34858 | /* 95487 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34859 | /* 95489 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34860 | /* 95493 */ GIR_RootConstrainSelectedInstOperands, |
| 34861 | /* 95494 */ // GIR_Coverage, 5534, |
| 34862 | /* 95494 */ GIR_EraseRootFromParent_Done, |
| 34863 | /* 95495 */ // Label 2946: @95495 |
| 34864 | /* 95495 */ GIM_Try, /*On fail goto*//*Label 2947*/ GIMT_Encode4(95523), // Rule ID 5535 // |
| 34865 | /* 95500 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34866 | /* 95504 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34867 | /* 95508 */ // (intrinsic_w_chain:{ *:[v4i32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34868 | /* 95508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34869 | /* 95511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34870 | /* 95513 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34871 | /* 95515 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34872 | /* 95517 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34873 | /* 95521 */ GIR_RootConstrainSelectedInstOperands, |
| 34874 | /* 95522 */ // GIR_Coverage, 5535, |
| 34875 | /* 95522 */ GIR_EraseRootFromParent_Done, |
| 34876 | /* 95523 */ // Label 2947: @95523 |
| 34877 | /* 95523 */ GIM_Try, /*On fail goto*//*Label 2948*/ GIMT_Encode4(95551), // Rule ID 5538 // |
| 34878 | /* 95528 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34879 | /* 95532 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34880 | /* 95536 */ // (intrinsic_w_chain:{ *:[v4f32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34881 | /* 95536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34882 | /* 95539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34883 | /* 95541 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34884 | /* 95543 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34885 | /* 95545 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34886 | /* 95549 */ GIR_RootConstrainSelectedInstOperands, |
| 34887 | /* 95550 */ // GIR_Coverage, 5538, |
| 34888 | /* 95550 */ GIR_EraseRootFromParent_Done, |
| 34889 | /* 95551 */ // Label 2948: @95551 |
| 34890 | /* 95551 */ GIM_Try, /*On fail goto*//*Label 2949*/ GIMT_Encode4(95579), // Rule ID 5539 // |
| 34891 | /* 95556 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34892 | /* 95560 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34893 | /* 95564 */ // (intrinsic_w_chain:{ *:[v4f32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34894 | /* 95564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34895 | /* 95567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34896 | /* 95569 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34897 | /* 95571 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34898 | /* 95573 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34899 | /* 95577 */ GIR_RootConstrainSelectedInstOperands, |
| 34900 | /* 95578 */ // GIR_Coverage, 5539, |
| 34901 | /* 95578 */ GIR_EraseRootFromParent_Done, |
| 34902 | /* 95579 */ // Label 2949: @95579 |
| 34903 | /* 95579 */ GIM_Try, /*On fail goto*//*Label 2950*/ GIMT_Encode4(95607), // Rule ID 5542 // |
| 34904 | /* 95584 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34905 | /* 95588 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34906 | /* 95592 */ // (intrinsic_w_chain:{ *:[v4f32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34907 | /* 95592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34908 | /* 95595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34909 | /* 95597 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34910 | /* 95599 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34911 | /* 95601 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34912 | /* 95605 */ GIR_RootConstrainSelectedInstOperands, |
| 34913 | /* 95606 */ // GIR_Coverage, 5542, |
| 34914 | /* 95606 */ GIR_EraseRootFromParent_Done, |
| 34915 | /* 95607 */ // Label 2950: @95607 |
| 34916 | /* 95607 */ GIM_Try, /*On fail goto*//*Label 2951*/ GIMT_Encode4(95635), // Rule ID 5543 // |
| 34917 | /* 95612 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34918 | /* 95616 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34919 | /* 95620 */ // (intrinsic_w_chain:{ *:[v4f32] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34920 | /* 95620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34921 | /* 95623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34922 | /* 95625 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34923 | /* 95627 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34924 | /* 95629 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34925 | /* 95633 */ GIR_RootConstrainSelectedInstOperands, |
| 34926 | /* 95634 */ // GIR_Coverage, 5543, |
| 34927 | /* 95634 */ GIR_EraseRootFromParent_Done, |
| 34928 | /* 95635 */ // Label 2951: @95635 |
| 34929 | /* 95635 */ GIM_Reject, |
| 34930 | /* 95636 */ // Label 2939: @95636 |
| 34931 | /* 95636 */ GIM_Reject, |
| 34932 | /* 95637 */ // Label 2930: @95637 |
| 34933 | /* 95637 */ GIM_Reject, |
| 34934 | /* 95638 */ // Label 2907: @95638 |
| 34935 | /* 95638 */ GIM_Try, /*On fail goto*//*Label 2952*/ GIMT_Encode4(95900), |
| 34936 | /* 95643 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 34937 | /* 95646 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34938 | /* 95649 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34939 | /* 95652 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34940 | /* 95655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34941 | /* 95659 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34942 | /* 95663 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34943 | /* 95667 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34944 | /* 95671 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 34945 | /* 95675 */ GIM_Try, /*On fail goto*//*Label 2953*/ GIMT_Encode4(95703), // Rule ID 5546 // |
| 34946 | /* 95680 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34947 | /* 95684 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34948 | /* 95688 */ // (intrinsic_w_chain:{ *:[v2i64] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34949 | /* 95688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 34950 | /* 95691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34951 | /* 95693 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34952 | /* 95695 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34953 | /* 95697 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34954 | /* 95701 */ GIR_RootConstrainSelectedInstOperands, |
| 34955 | /* 95702 */ // GIR_Coverage, 5546, |
| 34956 | /* 95702 */ GIR_EraseRootFromParent_Done, |
| 34957 | /* 95703 */ // Label 2953: @95703 |
| 34958 | /* 95703 */ GIM_Try, /*On fail goto*//*Label 2954*/ GIMT_Encode4(95731), // Rule ID 5547 // |
| 34959 | /* 95708 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 34960 | /* 95712 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34961 | /* 95716 */ // (intrinsic_w_chain:{ *:[v2i64] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34962 | /* 95716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 34963 | /* 95719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34964 | /* 95721 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34965 | /* 95723 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34966 | /* 95725 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34967 | /* 95729 */ GIR_RootConstrainSelectedInstOperands, |
| 34968 | /* 95730 */ // GIR_Coverage, 5547, |
| 34969 | /* 95730 */ GIR_EraseRootFromParent_Done, |
| 34970 | /* 95731 */ // Label 2954: @95731 |
| 34971 | /* 95731 */ GIM_Try, /*On fail goto*//*Label 2955*/ GIMT_Encode4(95759), // Rule ID 5550 // |
| 34972 | /* 95736 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34973 | /* 95740 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34974 | /* 95744 */ // (intrinsic_w_chain:{ *:[v2i64] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34975 | /* 95744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 34976 | /* 95747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34977 | /* 95749 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34978 | /* 95751 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34979 | /* 95753 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34980 | /* 95757 */ GIR_RootConstrainSelectedInstOperands, |
| 34981 | /* 95758 */ // GIR_Coverage, 5550, |
| 34982 | /* 95758 */ GIR_EraseRootFromParent_Done, |
| 34983 | /* 95759 */ // Label 2955: @95759 |
| 34984 | /* 95759 */ GIM_Try, /*On fail goto*//*Label 2956*/ GIMT_Encode4(95787), // Rule ID 5551 // |
| 34985 | /* 95764 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 34986 | /* 95768 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34987 | /* 95772 */ // (intrinsic_w_chain:{ *:[v2i64] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34988 | /* 95772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 34989 | /* 95775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34990 | /* 95777 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34991 | /* 95779 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34992 | /* 95781 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34993 | /* 95785 */ GIR_RootConstrainSelectedInstOperands, |
| 34994 | /* 95786 */ // GIR_Coverage, 5551, |
| 34995 | /* 95786 */ GIR_EraseRootFromParent_Done, |
| 34996 | /* 95787 */ // Label 2956: @95787 |
| 34997 | /* 95787 */ GIM_Try, /*On fail goto*//*Label 2957*/ GIMT_Encode4(95815), // Rule ID 5554 // |
| 34998 | /* 95792 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34999 | /* 95796 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 35000 | /* 95800 */ // (intrinsic_w_chain:{ *:[v2i64] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 35001 | /* 95800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 35002 | /* 95803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35003 | /* 95805 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35004 | /* 95807 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35005 | /* 95809 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35006 | /* 95813 */ GIR_RootConstrainSelectedInstOperands, |
| 35007 | /* 95814 */ // GIR_Coverage, 5554, |
| 35008 | /* 95814 */ GIR_EraseRootFromParent_Done, |
| 35009 | /* 95815 */ // Label 2957: @95815 |
| 35010 | /* 95815 */ GIM_Try, /*On fail goto*//*Label 2958*/ GIMT_Encode4(95843), // Rule ID 5555 // |
| 35011 | /* 95820 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 35012 | /* 95824 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 35013 | /* 95828 */ // (intrinsic_w_chain:{ *:[v2i64] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 35014 | /* 95828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 35015 | /* 95831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35016 | /* 95833 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35017 | /* 95835 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35018 | /* 95837 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35019 | /* 95841 */ GIR_RootConstrainSelectedInstOperands, |
| 35020 | /* 95842 */ // GIR_Coverage, 5555, |
| 35021 | /* 95842 */ GIR_EraseRootFromParent_Done, |
| 35022 | /* 95843 */ // Label 2958: @95843 |
| 35023 | /* 95843 */ GIM_Try, /*On fail goto*//*Label 2959*/ GIMT_Encode4(95871), // Rule ID 5558 // |
| 35024 | /* 95848 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 35025 | /* 95852 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35026 | /* 95856 */ // (intrinsic_w_chain:{ *:[v2i64] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 35027 | /* 95856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 35028 | /* 95859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35029 | /* 95861 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35030 | /* 95863 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35031 | /* 95865 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35032 | /* 95869 */ GIR_RootConstrainSelectedInstOperands, |
| 35033 | /* 95870 */ // GIR_Coverage, 5558, |
| 35034 | /* 95870 */ GIR_EraseRootFromParent_Done, |
| 35035 | /* 95871 */ // Label 2959: @95871 |
| 35036 | /* 95871 */ GIM_Try, /*On fail goto*//*Label 2960*/ GIMT_Encode4(95899), // Rule ID 5559 // |
| 35037 | /* 95876 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 35038 | /* 95880 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35039 | /* 95884 */ // (intrinsic_w_chain:{ *:[v2i64] } 3872:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 35040 | /* 95884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 35041 | /* 95887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35042 | /* 95889 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35043 | /* 95891 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35044 | /* 95893 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35045 | /* 95897 */ GIR_RootConstrainSelectedInstOperands, |
| 35046 | /* 95898 */ // GIR_Coverage, 5559, |
| 35047 | /* 95898 */ GIR_EraseRootFromParent_Done, |
| 35048 | /* 95899 */ // Label 2960: @95899 |
| 35049 | /* 95899 */ GIM_Reject, |
| 35050 | /* 95900 */ // Label 2952: @95900 |
| 35051 | /* 95900 */ GIM_Reject, |
| 35052 | /* 95901 */ // Label 2908: @95901 |
| 35053 | /* 95901 */ GIM_Reject, |
| 35054 | /* 95902 */ // Label 2903: @95902 |
| 35055 | /* 95902 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2961*/ GIMT_Encode4(95966), GIMT_Encode2(GIFBS_IsARM), // Rule ID 255 // |
| 35056 | /* 95909 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr), |
| 35057 | /* 95914 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35058 | /* 95917 */ // MIs[0] cop |
| 35059 | /* 95917 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 35060 | /* 95920 */ // MIs[0] opc1 |
| 35061 | /* 95920 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 35062 | /* 95923 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35063 | /* 95927 */ // MIs[0] CRn |
| 35064 | /* 95927 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 35065 | /* 95930 */ // MIs[0] CRm |
| 35066 | /* 95930 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 35067 | /* 95933 */ // MIs[0] opc2 |
| 35068 | /* 95933 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 35069 | /* 95936 */ // (intrinsic_void 3737:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 35070 | /* 95936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR), |
| 35071 | /* 95939 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 35072 | /* 95941 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 35073 | /* 95943 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 35074 | /* 95945 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 35075 | /* 95947 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 35076 | /* 95949 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 35077 | /* 95951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35078 | /* 95954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35079 | /* 95960 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35080 | /* 95964 */ GIR_RootConstrainSelectedInstOperands, |
| 35081 | /* 95965 */ // GIR_Coverage, 255, |
| 35082 | /* 95965 */ GIR_EraseRootFromParent_Done, |
| 35083 | /* 95966 */ // Label 2961: @95966 |
| 35084 | /* 95966 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2962*/ GIMT_Encode4(96021), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 256 // |
| 35085 | /* 95973 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2), |
| 35086 | /* 95978 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35087 | /* 95981 */ // MIs[0] cop |
| 35088 | /* 95981 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 35089 | /* 95984 */ // MIs[0] opc1 |
| 35090 | /* 95984 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 35091 | /* 95987 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35092 | /* 95991 */ // MIs[0] CRn |
| 35093 | /* 95991 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 35094 | /* 95994 */ // MIs[0] CRm |
| 35095 | /* 95994 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 35096 | /* 95997 */ // MIs[0] opc2 |
| 35097 | /* 95997 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 35098 | /* 96000 */ // (intrinsic_void 3738:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 35099 | /* 96000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR2), |
| 35100 | /* 96003 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 35101 | /* 96005 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 35102 | /* 96007 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 35103 | /* 96009 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 35104 | /* 96011 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 35105 | /* 96013 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 35106 | /* 96015 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35107 | /* 96019 */ GIR_RootConstrainSelectedInstOperands, |
| 35108 | /* 96020 */ // GIR_Coverage, 256, |
| 35109 | /* 96020 */ GIR_EraseRootFromParent_Done, |
| 35110 | /* 96021 */ // Label 2962: @96021 |
| 35111 | /* 96021 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2963*/ GIMT_Encode4(96085), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 593 // |
| 35112 | /* 96028 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr), |
| 35113 | /* 96033 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35114 | /* 96036 */ // MIs[0] cop |
| 35115 | /* 96036 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 35116 | /* 96039 */ // MIs[0] opc1 |
| 35117 | /* 96039 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 35118 | /* 96042 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35119 | /* 96046 */ // MIs[0] CRn |
| 35120 | /* 96046 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 35121 | /* 96049 */ // MIs[0] CRm |
| 35122 | /* 96049 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 35123 | /* 96052 */ // MIs[0] opc2 |
| 35124 | /* 96052 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 35125 | /* 96055 */ // (intrinsic_void 3737:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 35126 | /* 96055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR), |
| 35127 | /* 96058 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 35128 | /* 96060 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 35129 | /* 96062 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 35130 | /* 96064 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 35131 | /* 96066 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 35132 | /* 96068 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 35133 | /* 96070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35134 | /* 96073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35135 | /* 96079 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35136 | /* 96083 */ GIR_RootConstrainSelectedInstOperands, |
| 35137 | /* 96084 */ // GIR_Coverage, 593, |
| 35138 | /* 96084 */ GIR_EraseRootFromParent_Done, |
| 35139 | /* 96085 */ // Label 2963: @96085 |
| 35140 | /* 96085 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2964*/ GIMT_Encode4(96149), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 594 // |
| 35141 | /* 96092 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2), |
| 35142 | /* 96097 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35143 | /* 96100 */ // MIs[0] cop |
| 35144 | /* 96100 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 35145 | /* 96103 */ // MIs[0] opc1 |
| 35146 | /* 96103 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 35147 | /* 96106 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35148 | /* 96110 */ // MIs[0] CRn |
| 35149 | /* 96110 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 35150 | /* 96113 */ // MIs[0] CRm |
| 35151 | /* 96113 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 35152 | /* 96116 */ // MIs[0] opc2 |
| 35153 | /* 96116 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 35154 | /* 96119 */ // (intrinsic_void 3738:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 35155 | /* 96119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR2), |
| 35156 | /* 96122 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 35157 | /* 96124 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 35158 | /* 96126 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 35159 | /* 96128 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 35160 | /* 96130 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 35161 | /* 96132 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 35162 | /* 96134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35163 | /* 96137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35164 | /* 96143 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35165 | /* 96147 */ GIR_RootConstrainSelectedInstOperands, |
| 35166 | /* 96148 */ // GIR_Coverage, 594, |
| 35167 | /* 96148 */ GIR_EraseRootFromParent_Done, |
| 35168 | /* 96149 */ // Label 2964: @96149 |
| 35169 | /* 96149 */ GIM_Reject, |
| 35170 | /* 96150 */ // Label 2898: @96150 |
| 35171 | /* 96150 */ GIM_Reject, |
| 35172 | /* 96151 */ // Label 23: @96151 |
| 35173 | /* 96151 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 2968*/ GIMT_Encode4(96289), |
| 35174 | /* 96162 */ /*GILLT_v8s16*//*Label 2965*/ GIMT_Encode4(96178), GIMT_Encode4(0), |
| 35175 | /* 96170 */ /*GILLT_v4s32*//*Label 2966*/ GIMT_Encode4(96215), |
| 35176 | /* 96174 */ /*GILLT_v2s64*//*Label 2967*/ GIMT_Encode4(96252), |
| 35177 | /* 96178 */ // Label 2965: @96178 |
| 35178 | /* 96178 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2969*/ GIMT_Encode4(96214), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3055 // |
| 35179 | /* 96185 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35180 | /* 96188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35181 | /* 96192 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35182 | /* 96196 */ // (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) |
| 35183 | /* 96196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16), |
| 35184 | /* 96199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35185 | /* 96201 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35186 | /* 96203 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35187 | /* 96206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35188 | /* 96212 */ GIR_RootConstrainSelectedInstOperands, |
| 35189 | /* 96213 */ // GIR_Coverage, 3055, |
| 35190 | /* 96213 */ GIR_EraseRootFromParent_Done, |
| 35191 | /* 96214 */ // Label 2969: @96214 |
| 35192 | /* 96214 */ GIM_Reject, |
| 35193 | /* 96215 */ // Label 2966: @96215 |
| 35194 | /* 96215 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2970*/ GIMT_Encode4(96251), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3056 // |
| 35195 | /* 96222 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35196 | /* 96225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35197 | /* 96229 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35198 | /* 96233 */ // (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) |
| 35199 | /* 96233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32), |
| 35200 | /* 96236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35201 | /* 96238 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35202 | /* 96240 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35203 | /* 96243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35204 | /* 96249 */ GIR_RootConstrainSelectedInstOperands, |
| 35205 | /* 96250 */ // GIR_Coverage, 3056, |
| 35206 | /* 96250 */ GIR_EraseRootFromParent_Done, |
| 35207 | /* 96251 */ // Label 2970: @96251 |
| 35208 | /* 96251 */ GIM_Reject, |
| 35209 | /* 96252 */ // Label 2967: @96252 |
| 35210 | /* 96252 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2971*/ GIMT_Encode4(96288), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3057 // |
| 35211 | /* 96259 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35212 | /* 96262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35213 | /* 96266 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35214 | /* 96270 */ // (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) |
| 35215 | /* 96270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64), |
| 35216 | /* 96273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35217 | /* 96275 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35218 | /* 96277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35219 | /* 96280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35220 | /* 96286 */ GIR_RootConstrainSelectedInstOperands, |
| 35221 | /* 96287 */ // GIR_Coverage, 3057, |
| 35222 | /* 96287 */ GIR_EraseRootFromParent_Done, |
| 35223 | /* 96288 */ // Label 2971: @96288 |
| 35224 | /* 96288 */ GIM_Reject, |
| 35225 | /* 96289 */ // Label 2968: @96289 |
| 35226 | /* 96289 */ GIM_Reject, |
| 35227 | /* 96290 */ // Label 24: @96290 |
| 35228 | /* 96290 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 2975*/ GIMT_Encode4(96432), |
| 35229 | /* 96301 */ /*GILLT_v8s8*//*Label 2972*/ GIMT_Encode4(96321), GIMT_Encode4(0), |
| 35230 | /* 96309 */ /*GILLT_v4s16*//*Label 2973*/ GIMT_Encode4(96358), GIMT_Encode4(0), |
| 35231 | /* 96317 */ /*GILLT_v2s32*//*Label 2974*/ GIMT_Encode4(96395), |
| 35232 | /* 96321 */ // Label 2972: @96321 |
| 35233 | /* 96321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2976*/ GIMT_Encode4(96357), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1748 // |
| 35234 | /* 96328 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 35235 | /* 96331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35236 | /* 96335 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35237 | /* 96339 */ // (trunc:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) => (VMOVNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 35238 | /* 96339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv8i8), |
| 35239 | /* 96342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35240 | /* 96344 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35241 | /* 96346 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35242 | /* 96349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35243 | /* 96355 */ GIR_RootConstrainSelectedInstOperands, |
| 35244 | /* 96356 */ // GIR_Coverage, 1748, |
| 35245 | /* 96356 */ GIR_EraseRootFromParent_Done, |
| 35246 | /* 96357 */ // Label 2976: @96357 |
| 35247 | /* 96357 */ GIM_Reject, |
| 35248 | /* 96358 */ // Label 2973: @96358 |
| 35249 | /* 96358 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2977*/ GIMT_Encode4(96394), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1749 // |
| 35250 | /* 96365 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 35251 | /* 96368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35252 | /* 96372 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35253 | /* 96376 */ // (trunc:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) => (VMOVNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 35254 | /* 96376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv4i16), |
| 35255 | /* 96379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35256 | /* 96381 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35257 | /* 96383 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35258 | /* 96386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35259 | /* 96392 */ GIR_RootConstrainSelectedInstOperands, |
| 35260 | /* 96393 */ // GIR_Coverage, 1749, |
| 35261 | /* 96393 */ GIR_EraseRootFromParent_Done, |
| 35262 | /* 96394 */ // Label 2977: @96394 |
| 35263 | /* 96394 */ GIM_Reject, |
| 35264 | /* 96395 */ // Label 2974: @96395 |
| 35265 | /* 96395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2978*/ GIMT_Encode4(96431), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1750 // |
| 35266 | /* 96402 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 35267 | /* 96405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35268 | /* 96409 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35269 | /* 96413 */ // (trunc:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) => (VMOVNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 35270 | /* 96413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv2i32), |
| 35271 | /* 96416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35272 | /* 96418 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35273 | /* 96420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35274 | /* 96423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35275 | /* 96429 */ GIR_RootConstrainSelectedInstOperands, |
| 35276 | /* 96430 */ // GIR_Coverage, 1750, |
| 35277 | /* 96430 */ GIR_EraseRootFromParent_Done, |
| 35278 | /* 96431 */ // Label 2978: @96431 |
| 35279 | /* 96431 */ GIM_Reject, |
| 35280 | /* 96432 */ // Label 2975: @96432 |
| 35281 | /* 96432 */ GIM_Reject, |
| 35282 | /* 96433 */ // Label 25: @96433 |
| 35283 | /* 96433 */ GIM_Try, /*On fail goto*//*Label 2979*/ GIMT_Encode4(96744), |
| 35284 | /* 96438 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35285 | /* 96441 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2980*/ GIMT_Encode4(96481), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 403 // |
| 35286 | /* 96448 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 35287 | /* 96452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35288 | /* 96456 */ // MIs[0] Operand 1 |
| 35289 | /* 96456 */ // No operand predicates |
| 35290 | /* 96456 */ // (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm => (t2MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35291 | /* 96456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 35292 | /* 96459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35293 | /* 96461 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35294 | /* 96464 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35295 | /* 96467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35296 | /* 96473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35297 | /* 96479 */ GIR_RootConstrainSelectedInstOperands, |
| 35298 | /* 96480 */ // GIR_Coverage, 403, |
| 35299 | /* 96480 */ GIR_EraseRootFromParent_Done, |
| 35300 | /* 96481 */ // Label 2980: @96481 |
| 35301 | /* 96481 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2981*/ GIMT_Encode4(96521), GIMT_Encode2(GIFBS_IsARM), // Rule ID 56 // |
| 35302 | /* 96488 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 35303 | /* 96492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35304 | /* 96496 */ // MIs[0] Operand 1 |
| 35305 | /* 96496 */ // No operand predicates |
| 35306 | /* 96496 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm => (MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35307 | /* 96496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi), |
| 35308 | /* 96499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35309 | /* 96501 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35310 | /* 96504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35311 | /* 96507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35312 | /* 96513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35313 | /* 96519 */ GIR_RootConstrainSelectedInstOperands, |
| 35314 | /* 96520 */ // GIR_Coverage, 56, |
| 35315 | /* 96520 */ GIR_EraseRootFromParent_Done, |
| 35316 | /* 96521 */ // Label 2981: @96521 |
| 35317 | /* 96521 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2982*/ GIMT_Encode4(96555), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 57 // |
| 35318 | /* 96528 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 35319 | /* 96532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35320 | /* 96536 */ // MIs[0] Operand 1 |
| 35321 | /* 96536 */ // No operand predicates |
| 35322 | /* 96536 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35323 | /* 96536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi16), |
| 35324 | /* 96539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35325 | /* 96541 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35326 | /* 96544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35327 | /* 96547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35328 | /* 96553 */ GIR_RootConstrainSelectedInstOperands, |
| 35329 | /* 96554 */ // GIR_Coverage, 57, |
| 35330 | /* 96554 */ GIR_EraseRootFromParent_Done, |
| 35331 | /* 96555 */ // Label 2982: @96555 |
| 35332 | /* 96555 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2983*/ GIMT_Encode4(96597), GIMT_Encode2(GIFBS_IsARM), // Rule ID 167 // |
| 35333 | /* 96562 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not), |
| 35334 | /* 96566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35335 | /* 96570 */ // MIs[0] Operand 1 |
| 35336 | /* 96570 */ // No operand predicates |
| 35337 | /* 96570 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm => (MVNi:{ *:[i32] } (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm)) |
| 35338 | /* 96570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNi), |
| 35339 | /* 96573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35340 | /* 96575 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm |
| 35341 | /* 96580 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35342 | /* 96583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35343 | /* 96589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35344 | /* 96595 */ GIR_RootConstrainSelectedInstOperands, |
| 35345 | /* 96596 */ // GIR_Coverage, 167, |
| 35346 | /* 96596 */ GIR_EraseRootFromParent_Done, |
| 35347 | /* 96597 */ // Label 2983: @96597 |
| 35348 | /* 96597 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2984*/ GIMT_Encode4(96622), GIMT_Encode2(GIFBS_IsARM), // Rule ID 267 // |
| 35349 | /* 96604 */ GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_arm_i32imm), |
| 35350 | /* 96608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35351 | /* 96612 */ // MIs[0] Operand 1 |
| 35352 | /* 96612 */ // No operand predicates |
| 35353 | /* 96612 */ // (imm:{ *:[i32] })<<P:Predicate_arm_i32imm>>:$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 35354 | /* 96612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi32imm), |
| 35355 | /* 96615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 35356 | /* 96617 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 35357 | /* 96620 */ GIR_RootConstrainSelectedInstOperands, |
| 35358 | /* 96621 */ // GIR_Coverage, 267, |
| 35359 | /* 96621 */ GIR_EraseRootFromParent_Done, |
| 35360 | /* 96622 */ // Label 2984: @96622 |
| 35361 | /* 96622 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2985*/ GIMT_Encode4(96662), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 321 // |
| 35362 | /* 96629 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr), |
| 35363 | /* 96633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35364 | /* 96637 */ // MIs[0] Operand 1 |
| 35365 | /* 96637 */ // No operand predicates |
| 35366 | /* 96637 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8 => (tMOVi8:{ *:[i32] } (imm:{ *:[i32] }):$imm8) |
| 35367 | /* 96637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 35368 | /* 96640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35369 | /* 96642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 35370 | /* 96648 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm8 |
| 35371 | /* 96651 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35372 | /* 96654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35373 | /* 96660 */ GIR_RootConstrainSelectedInstOperands, |
| 35374 | /* 96661 */ // GIR_Coverage, 321, |
| 35375 | /* 96661 */ GIR_EraseRootFromParent_Done, |
| 35376 | /* 96662 */ // Label 2985: @96662 |
| 35377 | /* 96662 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2986*/ GIMT_Encode4(96696), GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb), // Rule ID 404 // |
| 35378 | /* 96669 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 35379 | /* 96673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35380 | /* 96677 */ // MIs[0] Operand 1 |
| 35381 | /* 96677 */ // No operand predicates |
| 35382 | /* 96677 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (t2MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35383 | /* 96677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16), |
| 35384 | /* 96680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35385 | /* 96682 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35386 | /* 96685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35387 | /* 96688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35388 | /* 96694 */ GIR_RootConstrainSelectedInstOperands, |
| 35389 | /* 96695 */ // GIR_Coverage, 404, |
| 35390 | /* 96695 */ GIR_EraseRootFromParent_Done, |
| 35391 | /* 96696 */ // Label 2986: @96696 |
| 35392 | /* 96696 */ GIM_Try, /*On fail goto*//*Label 2987*/ GIMT_Encode4(96743), |
| 35393 | /* 96701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35394 | /* 96705 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2988*/ GIMT_Encode4(96725), GIMT_Encode2(GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only), // Rule ID 352 // |
| 35395 | /* 96712 */ // MIs[0] Operand 1 |
| 35396 | /* 96712 */ // No operand predicates |
| 35397 | /* 96712 */ // (imm:{ *:[i32] }):$src => (tMOVi32imm:{ *:[i32] }:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 35398 | /* 96712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi32imm), |
| 35399 | /* 96715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 35400 | /* 96717 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 35401 | /* 96720 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::CPSR*/0, |
| 35402 | /* 96723 */ GIR_RootConstrainSelectedInstOperands, |
| 35403 | /* 96724 */ // GIR_Coverage, 352, |
| 35404 | /* 96724 */ GIR_EraseRootFromParent_Done, |
| 35405 | /* 96725 */ // Label 2988: @96725 |
| 35406 | /* 96725 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2989*/ GIMT_Encode4(96742), GIMT_Encode2(GIFBS_IsThumb_UseMovt), // Rule ID 581 // |
| 35407 | /* 96732 */ // MIs[0] Operand 1 |
| 35408 | /* 96732 */ // No operand predicates |
| 35409 | /* 96732 */ // (imm:{ *:[i32] }):$src => (t2MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 35410 | /* 96732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm), |
| 35411 | /* 96735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 35412 | /* 96737 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 35413 | /* 96740 */ GIR_RootConstrainSelectedInstOperands, |
| 35414 | /* 96741 */ // GIR_Coverage, 581, |
| 35415 | /* 96741 */ GIR_EraseRootFromParent_Done, |
| 35416 | /* 96742 */ // Label 2989: @96742 |
| 35417 | /* 96742 */ GIM_Reject, |
| 35418 | /* 96743 */ // Label 2987: @96743 |
| 35419 | /* 96743 */ GIM_Reject, |
| 35420 | /* 96744 */ // Label 2979: @96744 |
| 35421 | /* 96744 */ GIM_Reject, |
| 35422 | /* 96745 */ // Label 26: @96745 |
| 35423 | /* 96745 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2992*/ GIMT_Encode4(96838), |
| 35424 | /* 96756 */ /*GILLT_s32*//*Label 2990*/ GIMT_Encode4(96764), |
| 35425 | /* 96760 */ /*GILLT_s64*//*Label 2991*/ GIMT_Encode4(96801), |
| 35426 | /* 96764 */ // Label 2990: @96764 |
| 35427 | /* 96764 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2993*/ GIMT_Encode4(96800), GIMT_Encode2(GIFBS_HasVFP3), // Rule ID 848 // |
| 35428 | /* 96771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 35429 | /* 96775 */ // MIs[0] Operand 1 |
| 35430 | /* 96775 */ // No operand predicates |
| 35431 | /* 96775 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f32imm), |
| 35432 | /* 96779 */ // (fpimm:{ *:[f32] })<<P:Predicate_vfp_f32imm>><<X:vfp_f32imm_xform>>:$imm => (FCONSTS:{ *:[f32] } (vfp_f32imm_xform:{ *:[f32] } (fpimm:{ *:[f32] }):$imm)) |
| 35433 | /* 96779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTS), |
| 35434 | /* 96782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 35435 | /* 96784 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF32Imm), // imm |
| 35436 | /* 96789 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35437 | /* 96792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35438 | /* 96798 */ GIR_RootConstrainSelectedInstOperands, |
| 35439 | /* 96799 */ // GIR_Coverage, 848, |
| 35440 | /* 96799 */ GIR_EraseRootFromParent_Done, |
| 35441 | /* 96800 */ // Label 2993: @96800 |
| 35442 | /* 96800 */ GIM_Reject, |
| 35443 | /* 96801 */ // Label 2991: @96801 |
| 35444 | /* 96801 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2994*/ GIMT_Encode4(96837), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP3), // Rule ID 847 // |
| 35445 | /* 96808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35446 | /* 96812 */ // MIs[0] Operand 1 |
| 35447 | /* 96812 */ // No operand predicates |
| 35448 | /* 96812 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f64imm), |
| 35449 | /* 96816 */ // (fpimm:{ *:[f64] })<<P:Predicate_vfp_f64imm>><<X:vfp_f64imm_xform>>:$imm => (FCONSTD:{ *:[f64] } (vfp_f64imm_xform:{ *:[f64] } (fpimm:{ *:[f64] }):$imm)) |
| 35450 | /* 96816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTD), |
| 35451 | /* 96819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 35452 | /* 96821 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF64Imm), // imm |
| 35453 | /* 96826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35454 | /* 96829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35455 | /* 96835 */ GIR_RootConstrainSelectedInstOperands, |
| 35456 | /* 96836 */ // GIR_Coverage, 847, |
| 35457 | /* 96836 */ GIR_EraseRootFromParent_Done, |
| 35458 | /* 96837 */ // Label 2994: @96837 |
| 35459 | /* 96837 */ GIM_Reject, |
| 35460 | /* 96838 */ // Label 2992: @96838 |
| 35461 | /* 96838 */ GIM_Reject, |
| 35462 | /* 96839 */ // Label 27: @96839 |
| 35463 | /* 96839 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 2998*/ GIMT_Encode4(96977), |
| 35464 | /* 96850 */ /*GILLT_v8s16*//*Label 2995*/ GIMT_Encode4(96866), GIMT_Encode4(0), |
| 35465 | /* 96858 */ /*GILLT_v4s32*//*Label 2996*/ GIMT_Encode4(96903), |
| 35466 | /* 96862 */ /*GILLT_v2s64*//*Label 2997*/ GIMT_Encode4(96940), |
| 35467 | /* 96866 */ // Label 2995: @96866 |
| 35468 | /* 96866 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2999*/ GIMT_Encode4(96902), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1760 // |
| 35469 | /* 96873 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35470 | /* 96876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35471 | /* 96880 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35472 | /* 96884 */ // (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) |
| 35473 | /* 96884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv8i16), |
| 35474 | /* 96887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35475 | /* 96889 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35476 | /* 96891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35477 | /* 96894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35478 | /* 96900 */ GIR_RootConstrainSelectedInstOperands, |
| 35479 | /* 96901 */ // GIR_Coverage, 1760, |
| 35480 | /* 96901 */ GIR_EraseRootFromParent_Done, |
| 35481 | /* 96902 */ // Label 2999: @96902 |
| 35482 | /* 96902 */ GIM_Reject, |
| 35483 | /* 96903 */ // Label 2996: @96903 |
| 35484 | /* 96903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3000*/ GIMT_Encode4(96939), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1761 // |
| 35485 | /* 96910 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35486 | /* 96913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35487 | /* 96917 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35488 | /* 96921 */ // (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) |
| 35489 | /* 96921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv4i32), |
| 35490 | /* 96924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35491 | /* 96926 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35492 | /* 96928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35493 | /* 96931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35494 | /* 96937 */ GIR_RootConstrainSelectedInstOperands, |
| 35495 | /* 96938 */ // GIR_Coverage, 1761, |
| 35496 | /* 96938 */ GIR_EraseRootFromParent_Done, |
| 35497 | /* 96939 */ // Label 3000: @96939 |
| 35498 | /* 96939 */ GIM_Reject, |
| 35499 | /* 96940 */ // Label 2997: @96940 |
| 35500 | /* 96940 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3001*/ GIMT_Encode4(96976), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1762 // |
| 35501 | /* 96947 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35502 | /* 96950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35503 | /* 96954 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35504 | /* 96958 */ // (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) |
| 35505 | /* 96958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv2i64), |
| 35506 | /* 96961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35507 | /* 96963 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35508 | /* 96965 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35509 | /* 96968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35510 | /* 96974 */ GIR_RootConstrainSelectedInstOperands, |
| 35511 | /* 96975 */ // GIR_Coverage, 1762, |
| 35512 | /* 96975 */ GIR_EraseRootFromParent_Done, |
| 35513 | /* 96976 */ // Label 3001: @96976 |
| 35514 | /* 96976 */ GIM_Reject, |
| 35515 | /* 96977 */ // Label 2998: @96977 |
| 35516 | /* 96977 */ GIM_Reject, |
| 35517 | /* 96978 */ // Label 28: @96978 |
| 35518 | /* 96978 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3005*/ GIMT_Encode4(97567), |
| 35519 | /* 96989 */ /*GILLT_s32*//*Label 3002*/ GIMT_Encode4(97037), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35520 | /* 97025 */ /*GILLT_v8s16*//*Label 3003*/ GIMT_Encode4(97317), GIMT_Encode4(0), |
| 35521 | /* 97033 */ /*GILLT_v4s32*//*Label 3004*/ GIMT_Encode4(97386), |
| 35522 | /* 97037 */ // Label 3002: @97037 |
| 35523 | /* 97037 */ GIM_Try, /*On fail goto*//*Label 3006*/ GIMT_Encode4(97316), |
| 35524 | /* 97042 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35525 | /* 97045 */ GIM_Try, /*On fail goto*//*Label 3007*/ GIMT_Encode4(97131), |
| 35526 | /* 97050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35527 | /* 97054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35528 | /* 97058 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3008*/ GIMT_Encode4(97094), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 339 // |
| 35529 | /* 97065 */ // MIs[0] Operand 2 |
| 35530 | /* 97065 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 35531 | /* 97076 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }) => (tSXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 35532 | /* 97076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTB), |
| 35533 | /* 97079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35534 | /* 97081 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 35535 | /* 97083 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35536 | /* 97086 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35537 | /* 97092 */ GIR_RootConstrainSelectedInstOperands, |
| 35538 | /* 97093 */ // GIR_Coverage, 339, |
| 35539 | /* 97093 */ GIR_EraseRootFromParent_Done, |
| 35540 | /* 97094 */ // Label 3008: @97094 |
| 35541 | /* 97094 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3009*/ GIMT_Encode4(97130), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 340 // |
| 35542 | /* 97101 */ // MIs[0] Operand 2 |
| 35543 | /* 97101 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 35544 | /* 97112 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }) => (tSXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 35545 | /* 97112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTH), |
| 35546 | /* 97115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35547 | /* 97117 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 35548 | /* 97119 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35549 | /* 97122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35550 | /* 97128 */ GIR_RootConstrainSelectedInstOperands, |
| 35551 | /* 97129 */ // GIR_Coverage, 340, |
| 35552 | /* 97129 */ GIR_EraseRootFromParent_Done, |
| 35553 | /* 97130 */ // Label 3009: @97130 |
| 35554 | /* 97130 */ GIM_Reject, |
| 35555 | /* 97131 */ // Label 3007: @97131 |
| 35556 | /* 97131 */ GIM_Try, /*On fail goto*//*Label 3010*/ GIMT_Encode4(97223), |
| 35557 | /* 97136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35558 | /* 97140 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35559 | /* 97144 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3011*/ GIMT_Encode4(97183), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2197 // |
| 35560 | /* 97151 */ // MIs[0] Operand 2 |
| 35561 | /* 97151 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 35562 | /* 97162 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (SXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 35563 | /* 97162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB), |
| 35564 | /* 97165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35565 | /* 97167 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 35566 | /* 97169 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35567 | /* 97172 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35568 | /* 97175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35569 | /* 97181 */ GIR_RootConstrainSelectedInstOperands, |
| 35570 | /* 97182 */ // GIR_Coverage, 2197, |
| 35571 | /* 97182 */ GIR_EraseRootFromParent_Done, |
| 35572 | /* 97183 */ // Label 3011: @97183 |
| 35573 | /* 97183 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3012*/ GIMT_Encode4(97222), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2198 // |
| 35574 | /* 97190 */ // MIs[0] Operand 2 |
| 35575 | /* 97190 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 35576 | /* 97201 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (SXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 35577 | /* 97201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTH), |
| 35578 | /* 97204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35579 | /* 97206 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 35580 | /* 97208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35581 | /* 97211 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35582 | /* 97214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35583 | /* 97220 */ GIR_RootConstrainSelectedInstOperands, |
| 35584 | /* 97221 */ // GIR_Coverage, 2198, |
| 35585 | /* 97221 */ GIR_EraseRootFromParent_Done, |
| 35586 | /* 97222 */ // Label 3012: @97222 |
| 35587 | /* 97222 */ GIM_Reject, |
| 35588 | /* 97223 */ // Label 3010: @97223 |
| 35589 | /* 97223 */ GIM_Try, /*On fail goto*//*Label 3013*/ GIMT_Encode4(97315), |
| 35590 | /* 97228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35591 | /* 97232 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35592 | /* 97236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3014*/ GIMT_Encode4(97275), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2441 // |
| 35593 | /* 97243 */ // MIs[0] Operand 2 |
| 35594 | /* 97243 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 35595 | /* 97254 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (t2SXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 35596 | /* 97254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB), |
| 35597 | /* 97257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35598 | /* 97259 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 35599 | /* 97261 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35600 | /* 97264 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35601 | /* 97267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35602 | /* 97273 */ GIR_RootConstrainSelectedInstOperands, |
| 35603 | /* 97274 */ // GIR_Coverage, 2441, |
| 35604 | /* 97274 */ GIR_EraseRootFromParent_Done, |
| 35605 | /* 97275 */ // Label 3014: @97275 |
| 35606 | /* 97275 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3015*/ GIMT_Encode4(97314), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2442 // |
| 35607 | /* 97282 */ // MIs[0] Operand 2 |
| 35608 | /* 97282 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 35609 | /* 97293 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (t2SXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 35610 | /* 97293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTH), |
| 35611 | /* 97296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35612 | /* 97298 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 35613 | /* 97300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35614 | /* 97303 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35615 | /* 97306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35616 | /* 97312 */ GIR_RootConstrainSelectedInstOperands, |
| 35617 | /* 97313 */ // GIR_Coverage, 2442, |
| 35618 | /* 97313 */ GIR_EraseRootFromParent_Done, |
| 35619 | /* 97314 */ // Label 3015: @97314 |
| 35620 | /* 97314 */ GIM_Reject, |
| 35621 | /* 97315 */ // Label 3013: @97315 |
| 35622 | /* 97315 */ GIM_Reject, |
| 35623 | /* 97316 */ // Label 3006: @97316 |
| 35624 | /* 97316 */ GIM_Reject, |
| 35625 | /* 97317 */ // Label 3003: @97317 |
| 35626 | /* 97317 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3016*/ GIMT_Encode4(97385), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4117 // |
| 35627 | /* 97324 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 35628 | /* 97327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35629 | /* 97331 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35630 | /* 97335 */ // MIs[0] Operand 2 |
| 35631 | /* 97335 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 35632 | /* 97346 */ // (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, v8i8:{ *:[Other] }) => (MVE_VMOVLs8bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) |
| 35633 | /* 97346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 35634 | /* 97349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 35635 | /* 97353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 35636 | /* 97358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh), |
| 35637 | /* 97361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35638 | /* 97363 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 35639 | /* 97365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35640 | /* 97368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35641 | /* 97374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35642 | /* 97380 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 35643 | /* 97383 */ GIR_RootConstrainSelectedInstOperands, |
| 35644 | /* 97384 */ // GIR_Coverage, 4117, |
| 35645 | /* 97384 */ GIR_EraseRootFromParent_Done, |
| 35646 | /* 97385 */ // Label 3016: @97385 |
| 35647 | /* 97385 */ GIM_Reject, |
| 35648 | /* 97386 */ // Label 3004: @97386 |
| 35649 | /* 97386 */ GIM_Try, /*On fail goto*//*Label 3017*/ GIMT_Encode4(97566), |
| 35650 | /* 97391 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 35651 | /* 97394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35652 | /* 97398 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35653 | /* 97402 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3018*/ GIMT_Encode4(97459), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4116 // |
| 35654 | /* 97409 */ // MIs[0] Operand 2 |
| 35655 | /* 97409 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 35656 | /* 97420 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i16:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) |
| 35657 | /* 97420 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 35658 | /* 97423 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 35659 | /* 97427 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 35660 | /* 97432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh), |
| 35661 | /* 97435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35662 | /* 97437 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 35663 | /* 97439 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35664 | /* 97442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35665 | /* 97448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35666 | /* 97454 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 35667 | /* 97457 */ GIR_RootConstrainSelectedInstOperands, |
| 35668 | /* 97458 */ // GIR_Coverage, 4116, |
| 35669 | /* 97458 */ GIR_EraseRootFromParent_Done, |
| 35670 | /* 97459 */ // Label 3018: @97459 |
| 35671 | /* 97459 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3019*/ GIMT_Encode4(97565), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4118 // |
| 35672 | /* 97466 */ // MIs[0] Operand 2 |
| 35673 | /* 97466 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 35674 | /* 97477 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i8:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } (MVE_VMOVLs8bh:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)) |
| 35675 | /* 97477 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 35676 | /* 97480 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 35677 | /* 97484 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 35678 | /* 97489 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 35679 | /* 97492 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 35680 | /* 97496 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 35681 | /* 97501 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 35682 | /* 97504 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh), |
| 35683 | /* 97508 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 35684 | /* 97513 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 35685 | /* 97517 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 35686 | /* 97520 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35687 | /* 97526 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35688 | /* 97532 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 35689 | /* 97535 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 35690 | /* 97537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh), |
| 35691 | /* 97540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35692 | /* 97542 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 35693 | /* 97545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35694 | /* 97548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35695 | /* 97554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35696 | /* 97560 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 35697 | /* 97563 */ GIR_RootConstrainSelectedInstOperands, |
| 35698 | /* 97564 */ // GIR_Coverage, 4118, |
| 35699 | /* 97564 */ GIR_EraseRootFromParent_Done, |
| 35700 | /* 97565 */ // Label 3019: @97565 |
| 35701 | /* 97565 */ GIM_Reject, |
| 35702 | /* 97566 */ // Label 3017: @97566 |
| 35703 | /* 97566 */ GIM_Reject, |
| 35704 | /* 97567 */ // Label 3005: @97567 |
| 35705 | /* 97567 */ GIM_Reject, |
| 35706 | /* 97568 */ // Label 29: @97568 |
| 35707 | /* 97568 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 3023*/ GIMT_Encode4(98255), |
| 35708 | /* 97579 */ /*GILLT_v8s16*//*Label 3020*/ GIMT_Encode4(97595), GIMT_Encode4(0), |
| 35709 | /* 97587 */ /*GILLT_v4s32*//*Label 3021*/ GIMT_Encode4(97815), |
| 35710 | /* 97591 */ /*GILLT_v2s64*//*Label 3022*/ GIMT_Encode4(98035), |
| 35711 | /* 97595 */ // Label 3020: @97595 |
| 35712 | /* 97595 */ GIM_Try, /*On fail goto*//*Label 3024*/ GIMT_Encode4(97814), |
| 35713 | /* 97600 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35714 | /* 97603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35715 | /* 97607 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3025*/ GIMT_Encode4(97666), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1335 // |
| 35716 | /* 97614 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35717 | /* 97618 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 35718 | /* 97622 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35719 | /* 97626 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 35720 | /* 97630 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35721 | /* 97635 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35722 | /* 97640 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35723 | /* 97642 */ // (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 35724 | /* 97642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv8i16), |
| 35725 | /* 97645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35726 | /* 97647 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 35727 | /* 97651 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 35728 | /* 97655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35729 | /* 97658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35730 | /* 97664 */ GIR_RootConstrainSelectedInstOperands, |
| 35731 | /* 97665 */ // GIR_Coverage, 1335, |
| 35732 | /* 97665 */ GIR_EraseRootFromParent_Done, |
| 35733 | /* 97666 */ // Label 3025: @97666 |
| 35734 | /* 97666 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3026*/ GIMT_Encode4(97725), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1338 // |
| 35735 | /* 97673 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35736 | /* 97677 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 35737 | /* 97681 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35738 | /* 97685 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 35739 | /* 97689 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35740 | /* 97694 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35741 | /* 97699 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35742 | /* 97701 */ // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 35743 | /* 97701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16), |
| 35744 | /* 97704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35745 | /* 97706 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 35746 | /* 97710 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 35747 | /* 97714 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35748 | /* 97717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35749 | /* 97723 */ GIR_RootConstrainSelectedInstOperands, |
| 35750 | /* 97724 */ // GIR_Coverage, 1338, |
| 35751 | /* 97724 */ GIR_EraseRootFromParent_Done, |
| 35752 | /* 97725 */ // Label 3026: @97725 |
| 35753 | /* 97725 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3027*/ GIMT_Encode4(97784), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2967 // |
| 35754 | /* 97732 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35755 | /* 97736 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 35756 | /* 97740 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35757 | /* 97744 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 35758 | /* 97748 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35759 | /* 97753 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35760 | /* 97758 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35761 | /* 97760 */ // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB) |
| 35762 | /* 97760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16), |
| 35763 | /* 97763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35764 | /* 97765 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA |
| 35765 | /* 97769 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB |
| 35766 | /* 97773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35767 | /* 97776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35768 | /* 97782 */ GIR_RootConstrainSelectedInstOperands, |
| 35769 | /* 97783 */ // GIR_Coverage, 2967, |
| 35770 | /* 97783 */ GIR_EraseRootFromParent_Done, |
| 35771 | /* 97784 */ // Label 3027: @97784 |
| 35772 | /* 97784 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3028*/ GIMT_Encode4(97813), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1763 // |
| 35773 | /* 97791 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35774 | /* 97795 */ // (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) |
| 35775 | /* 97795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16), |
| 35776 | /* 97798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35777 | /* 97800 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35778 | /* 97802 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35779 | /* 97805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35780 | /* 97811 */ GIR_RootConstrainSelectedInstOperands, |
| 35781 | /* 97812 */ // GIR_Coverage, 1763, |
| 35782 | /* 97812 */ GIR_EraseRootFromParent_Done, |
| 35783 | /* 97813 */ // Label 3028: @97813 |
| 35784 | /* 97813 */ GIM_Reject, |
| 35785 | /* 97814 */ // Label 3024: @97814 |
| 35786 | /* 97814 */ GIM_Reject, |
| 35787 | /* 97815 */ // Label 3021: @97815 |
| 35788 | /* 97815 */ GIM_Try, /*On fail goto*//*Label 3029*/ GIMT_Encode4(98034), |
| 35789 | /* 97820 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35790 | /* 97823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35791 | /* 97827 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3030*/ GIMT_Encode4(97886), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1336 // |
| 35792 | /* 97834 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35793 | /* 97838 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 35794 | /* 97842 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35795 | /* 97846 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35796 | /* 97850 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35797 | /* 97855 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35798 | /* 97860 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35799 | /* 97862 */ // (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 35800 | /* 97862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv4i32), |
| 35801 | /* 97865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35802 | /* 97867 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 35803 | /* 97871 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 35804 | /* 97875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35805 | /* 97878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35806 | /* 97884 */ GIR_RootConstrainSelectedInstOperands, |
| 35807 | /* 97885 */ // GIR_Coverage, 1336, |
| 35808 | /* 97885 */ GIR_EraseRootFromParent_Done, |
| 35809 | /* 97886 */ // Label 3030: @97886 |
| 35810 | /* 97886 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3031*/ GIMT_Encode4(97945), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1339 // |
| 35811 | /* 97893 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35812 | /* 97897 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 35813 | /* 97901 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35814 | /* 97905 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35815 | /* 97909 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35816 | /* 97914 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35817 | /* 97919 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35818 | /* 97921 */ // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 35819 | /* 97921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32), |
| 35820 | /* 97924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35821 | /* 97926 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 35822 | /* 97930 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 35823 | /* 97934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35824 | /* 97937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35825 | /* 97943 */ GIR_RootConstrainSelectedInstOperands, |
| 35826 | /* 97944 */ // GIR_Coverage, 1339, |
| 35827 | /* 97944 */ GIR_EraseRootFromParent_Done, |
| 35828 | /* 97945 */ // Label 3031: @97945 |
| 35829 | /* 97945 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3032*/ GIMT_Encode4(98004), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2968 // |
| 35830 | /* 97952 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35831 | /* 97956 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 35832 | /* 97960 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35833 | /* 97964 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35834 | /* 97968 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35835 | /* 97973 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35836 | /* 97978 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35837 | /* 97980 */ // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB) |
| 35838 | /* 97980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32), |
| 35839 | /* 97983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35840 | /* 97985 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA |
| 35841 | /* 97989 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB |
| 35842 | /* 97993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35843 | /* 97996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35844 | /* 98002 */ GIR_RootConstrainSelectedInstOperands, |
| 35845 | /* 98003 */ // GIR_Coverage, 2968, |
| 35846 | /* 98003 */ GIR_EraseRootFromParent_Done, |
| 35847 | /* 98004 */ // Label 3032: @98004 |
| 35848 | /* 98004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3033*/ GIMT_Encode4(98033), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1764 // |
| 35849 | /* 98011 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35850 | /* 98015 */ // (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) |
| 35851 | /* 98015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32), |
| 35852 | /* 98018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35853 | /* 98020 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35854 | /* 98022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35855 | /* 98025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35856 | /* 98031 */ GIR_RootConstrainSelectedInstOperands, |
| 35857 | /* 98032 */ // GIR_Coverage, 1764, |
| 35858 | /* 98032 */ GIR_EraseRootFromParent_Done, |
| 35859 | /* 98033 */ // Label 3033: @98033 |
| 35860 | /* 98033 */ GIM_Reject, |
| 35861 | /* 98034 */ // Label 3029: @98034 |
| 35862 | /* 98034 */ GIM_Reject, |
| 35863 | /* 98035 */ // Label 3022: @98035 |
| 35864 | /* 98035 */ GIM_Try, /*On fail goto*//*Label 3034*/ GIMT_Encode4(98254), |
| 35865 | /* 98040 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35866 | /* 98043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35867 | /* 98047 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3035*/ GIMT_Encode4(98106), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1337 // |
| 35868 | /* 98054 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35869 | /* 98058 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 35870 | /* 98062 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35871 | /* 98066 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35872 | /* 98070 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35873 | /* 98075 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35874 | /* 98080 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35875 | /* 98082 */ // (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 35876 | /* 98082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv2i64), |
| 35877 | /* 98085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35878 | /* 98087 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 35879 | /* 98091 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 35880 | /* 98095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35881 | /* 98098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35882 | /* 98104 */ GIR_RootConstrainSelectedInstOperands, |
| 35883 | /* 98105 */ // GIR_Coverage, 1337, |
| 35884 | /* 98105 */ GIR_EraseRootFromParent_Done, |
| 35885 | /* 98106 */ // Label 3035: @98106 |
| 35886 | /* 98106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3036*/ GIMT_Encode4(98165), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1340 // |
| 35887 | /* 98113 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35888 | /* 98117 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 35889 | /* 98121 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35890 | /* 98125 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35891 | /* 98129 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35892 | /* 98134 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35893 | /* 98139 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35894 | /* 98141 */ // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 35895 | /* 98141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv2i64), |
| 35896 | /* 98144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35897 | /* 98146 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 35898 | /* 98150 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 35899 | /* 98154 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35900 | /* 98157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35901 | /* 98163 */ GIR_RootConstrainSelectedInstOperands, |
| 35902 | /* 98164 */ // GIR_Coverage, 1340, |
| 35903 | /* 98164 */ GIR_EraseRootFromParent_Done, |
| 35904 | /* 98165 */ // Label 3036: @98165 |
| 35905 | /* 98165 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3037*/ GIMT_Encode4(98224), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2969 // |
| 35906 | /* 98172 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35907 | /* 98176 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 35908 | /* 98180 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35909 | /* 98184 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35910 | /* 98188 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35911 | /* 98193 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35912 | /* 98198 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35913 | /* 98200 */ // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$opA, DPR:{ *:[v2i32] }:$opB)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$opA, DPR:{ *:[v2i32] }:$opB) |
| 35914 | /* 98200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv2i64), |
| 35915 | /* 98203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35916 | /* 98205 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA |
| 35917 | /* 98209 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB |
| 35918 | /* 98213 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35919 | /* 98216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35920 | /* 98222 */ GIR_RootConstrainSelectedInstOperands, |
| 35921 | /* 98223 */ // GIR_Coverage, 2969, |
| 35922 | /* 98223 */ GIR_EraseRootFromParent_Done, |
| 35923 | /* 98224 */ // Label 3037: @98224 |
| 35924 | /* 98224 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3038*/ GIMT_Encode4(98253), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1765 // |
| 35925 | /* 98231 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35926 | /* 98235 */ // (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) |
| 35927 | /* 98235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64), |
| 35928 | /* 98238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35929 | /* 98240 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35930 | /* 98242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35931 | /* 98245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35932 | /* 98251 */ GIR_RootConstrainSelectedInstOperands, |
| 35933 | /* 98252 */ // GIR_Coverage, 1765, |
| 35934 | /* 98252 */ GIR_EraseRootFromParent_Done, |
| 35935 | /* 98253 */ // Label 3038: @98253 |
| 35936 | /* 98253 */ GIM_Reject, |
| 35937 | /* 98254 */ // Label 3034: @98254 |
| 35938 | /* 98254 */ GIM_Reject, |
| 35939 | /* 98255 */ // Label 3023: @98255 |
| 35940 | /* 98255 */ GIM_Reject, |
| 35941 | /* 98256 */ // Label 30: @98256 |
| 35942 | /* 98256 */ GIM_Try, /*On fail goto*//*Label 3039*/ GIMT_Encode4(98467), |
| 35943 | /* 98261 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35944 | /* 98264 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35945 | /* 98267 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35946 | /* 98270 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3040*/ GIMT_Encode4(98326), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 469 // |
| 35947 | /* 98277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35948 | /* 98281 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35949 | /* 98285 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 35950 | /* 98289 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35951 | /* 98293 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31), |
| 35952 | /* 98297 */ // MIs[1] Operand 1 |
| 35953 | /* 98297 */ // No operand predicates |
| 35954 | /* 98297 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35955 | /* 98299 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2LSLri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 35956 | /* 98299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLri), |
| 35957 | /* 98302 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35958 | /* 98304 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 35959 | /* 98306 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 35960 | /* 98309 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35961 | /* 98312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35962 | /* 98318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35963 | /* 98324 */ GIR_RootConstrainSelectedInstOperands, |
| 35964 | /* 98325 */ // GIR_Coverage, 469, |
| 35965 | /* 98325 */ GIR_EraseRootFromParent_Done, |
| 35966 | /* 98326 */ // Label 3040: @98326 |
| 35967 | /* 98326 */ GIM_Try, /*On fail goto*//*Label 3041*/ GIMT_Encode4(98421), |
| 35968 | /* 98331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35969 | /* 98335 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35970 | /* 98339 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3042*/ GIMT_Encode4(98383), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 317 // |
| 35971 | /* 98346 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 35972 | /* 98350 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35973 | /* 98354 */ // MIs[1] Operand 1 |
| 35974 | /* 98354 */ // No operand predicates |
| 35975 | /* 98354 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35976 | /* 98356 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5) => (tLSLri:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5) |
| 35977 | /* 98356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLri), |
| 35978 | /* 98359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35979 | /* 98361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 35980 | /* 98367 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 35981 | /* 98369 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm5 |
| 35982 | /* 98372 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35983 | /* 98375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35984 | /* 98381 */ GIR_RootConstrainSelectedInstOperands, |
| 35985 | /* 98382 */ // GIR_Coverage, 317, |
| 35986 | /* 98382 */ GIR_EraseRootFromParent_Done, |
| 35987 | /* 98383 */ // Label 3042: @98383 |
| 35988 | /* 98383 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3043*/ GIMT_Encode4(98420), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 318 // |
| 35989 | /* 98390 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35990 | /* 98394 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSLrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 35991 | /* 98394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLrr), |
| 35992 | /* 98397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 35993 | /* 98399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 35994 | /* 98405 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 35995 | /* 98407 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 35996 | /* 98409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35997 | /* 98412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35998 | /* 98418 */ GIR_RootConstrainSelectedInstOperands, |
| 35999 | /* 98419 */ // GIR_Coverage, 318, |
| 36000 | /* 98419 */ GIR_EraseRootFromParent_Done, |
| 36001 | /* 98420 */ // Label 3043: @98420 |
| 36002 | /* 98420 */ GIM_Reject, |
| 36003 | /* 98421 */ // Label 3041: @98421 |
| 36004 | /* 98421 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3044*/ GIMT_Encode4(98466), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 470 // |
| 36005 | /* 98428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36006 | /* 98432 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36007 | /* 98436 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36008 | /* 98440 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSLrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36009 | /* 98440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLrr), |
| 36010 | /* 98443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36011 | /* 98445 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36012 | /* 98447 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36013 | /* 98449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36014 | /* 98452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36015 | /* 98458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36016 | /* 98464 */ GIR_RootConstrainSelectedInstOperands, |
| 36017 | /* 98465 */ // GIR_Coverage, 470, |
| 36018 | /* 98465 */ GIR_EraseRootFromParent_Done, |
| 36019 | /* 98466 */ // Label 3044: @98466 |
| 36020 | /* 98466 */ GIM_Reject, |
| 36021 | /* 98467 */ // Label 3039: @98467 |
| 36022 | /* 98467 */ GIM_Reject, |
| 36023 | /* 98468 */ // Label 31: @98468 |
| 36024 | /* 98468 */ GIM_Try, /*On fail goto*//*Label 3045*/ GIMT_Encode4(98573), |
| 36025 | /* 98473 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36026 | /* 98476 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36027 | /* 98479 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36028 | /* 98482 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3046*/ GIMT_Encode4(98527), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 320 // |
| 36029 | /* 98489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36030 | /* 98493 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36031 | /* 98497 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36032 | /* 98501 */ // (srl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 36033 | /* 98501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSRrr), |
| 36034 | /* 98504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 36035 | /* 98506 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 36036 | /* 98512 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36037 | /* 98514 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36038 | /* 98516 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36039 | /* 98519 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36040 | /* 98525 */ GIR_RootConstrainSelectedInstOperands, |
| 36041 | /* 98526 */ // GIR_Coverage, 320, |
| 36042 | /* 98526 */ GIR_EraseRootFromParent_Done, |
| 36043 | /* 98527 */ // Label 3046: @98527 |
| 36044 | /* 98527 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3047*/ GIMT_Encode4(98572), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 472 // |
| 36045 | /* 98534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36046 | /* 98538 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36047 | /* 98542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36048 | /* 98546 */ // (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36049 | /* 98546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSRrr), |
| 36050 | /* 98549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36051 | /* 98551 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36052 | /* 98553 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36053 | /* 98555 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36054 | /* 98558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36055 | /* 98564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36056 | /* 98570 */ GIR_RootConstrainSelectedInstOperands, |
| 36057 | /* 98571 */ // GIR_Coverage, 472, |
| 36058 | /* 98571 */ GIR_EraseRootFromParent_Done, |
| 36059 | /* 98572 */ // Label 3047: @98572 |
| 36060 | /* 98572 */ GIM_Reject, |
| 36061 | /* 98573 */ // Label 3045: @98573 |
| 36062 | /* 98573 */ GIM_Reject, |
| 36063 | /* 98574 */ // Label 32: @98574 |
| 36064 | /* 98574 */ GIM_Try, /*On fail goto*//*Label 3048*/ GIMT_Encode4(98841), |
| 36065 | /* 98579 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36066 | /* 98582 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36067 | /* 98585 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36068 | /* 98588 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3049*/ GIMT_Encode4(98642), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 200 // |
| 36069 | /* 98595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36070 | /* 98599 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36071 | /* 98603 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36072 | /* 98607 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36073 | /* 98611 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36074 | /* 98616 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36075 | /* 98620 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36076 | /* 98622 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 36077 | /* 98622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), |
| 36078 | /* 98625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36079 | /* 98627 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36080 | /* 98631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36081 | /* 98634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36082 | /* 98640 */ GIR_RootConstrainSelectedInstOperands, |
| 36083 | /* 98641 */ // GIR_Coverage, 200, |
| 36084 | /* 98641 */ GIR_EraseRootFromParent_Done, |
| 36085 | /* 98642 */ // Label 3049: @98642 |
| 36086 | /* 98642 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3050*/ GIMT_Encode4(98696), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 327 // |
| 36087 | /* 98649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36088 | /* 98653 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36089 | /* 98657 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36090 | /* 98661 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36091 | /* 98665 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36092 | /* 98670 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36093 | /* 98674 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36094 | /* 98676 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREVSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 36095 | /* 98676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREVSH), |
| 36096 | /* 98679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36097 | /* 98681 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36098 | /* 98685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36099 | /* 98688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36100 | /* 98694 */ GIR_RootConstrainSelectedInstOperands, |
| 36101 | /* 98695 */ // GIR_Coverage, 327, |
| 36102 | /* 98695 */ GIR_EraseRootFromParent_Done, |
| 36103 | /* 98696 */ // Label 3050: @98696 |
| 36104 | /* 98696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3051*/ GIMT_Encode4(98750), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 537 // |
| 36105 | /* 98703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36106 | /* 98707 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36107 | /* 98711 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36108 | /* 98715 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36109 | /* 98719 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36110 | /* 98724 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36111 | /* 98728 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36112 | /* 98730 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 36113 | /* 98730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), |
| 36114 | /* 98733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36115 | /* 98735 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36116 | /* 98739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36117 | /* 98742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36118 | /* 98748 */ GIR_RootConstrainSelectedInstOperands, |
| 36119 | /* 98749 */ // GIR_Coverage, 537, |
| 36120 | /* 98749 */ GIR_EraseRootFromParent_Done, |
| 36121 | /* 98750 */ // Label 3051: @98750 |
| 36122 | /* 98750 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3052*/ GIMT_Encode4(98795), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 311 // |
| 36123 | /* 98757 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36124 | /* 98761 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36125 | /* 98765 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36126 | /* 98769 */ // (sra:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tASRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 36127 | /* 98769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tASRrr), |
| 36128 | /* 98772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 36129 | /* 98774 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 36130 | /* 98780 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36131 | /* 98782 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36132 | /* 98784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36133 | /* 98787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36134 | /* 98793 */ GIR_RootConstrainSelectedInstOperands, |
| 36135 | /* 98794 */ // GIR_Coverage, 311, |
| 36136 | /* 98794 */ GIR_EraseRootFromParent_Done, |
| 36137 | /* 98795 */ // Label 3052: @98795 |
| 36138 | /* 98795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3053*/ GIMT_Encode4(98840), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 474 // |
| 36139 | /* 98802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36140 | /* 98806 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36141 | /* 98810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36142 | /* 98814 */ // (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ASRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36143 | /* 98814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ASRrr), |
| 36144 | /* 98817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36145 | /* 98819 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36146 | /* 98821 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36147 | /* 98823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36148 | /* 98826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36149 | /* 98832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36150 | /* 98838 */ GIR_RootConstrainSelectedInstOperands, |
| 36151 | /* 98839 */ // GIR_Coverage, 474, |
| 36152 | /* 98839 */ GIR_EraseRootFromParent_Done, |
| 36153 | /* 98840 */ // Label 3053: @98840 |
| 36154 | /* 98840 */ GIM_Reject, |
| 36155 | /* 98841 */ // Label 3048: @98841 |
| 36156 | /* 98841 */ GIM_Reject, |
| 36157 | /* 98842 */ // Label 33: @98842 |
| 36158 | /* 98842 */ GIM_Try, /*On fail goto*//*Label 3054*/ GIMT_Encode4(99167), |
| 36159 | /* 98847 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36160 | /* 98850 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36161 | /* 98853 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36162 | /* 98856 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3055*/ GIMT_Encode4(98910), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 199 // |
| 36163 | /* 98863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36164 | /* 98867 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36165 | /* 98871 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36166 | /* 98875 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36167 | /* 98879 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36168 | /* 98884 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36169 | /* 98888 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36170 | /* 98890 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REV16:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 36171 | /* 98890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV16), |
| 36172 | /* 98893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36173 | /* 98895 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36174 | /* 98899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36175 | /* 98902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36176 | /* 98908 */ GIR_RootConstrainSelectedInstOperands, |
| 36177 | /* 98909 */ // GIR_Coverage, 199, |
| 36178 | /* 98909 */ GIR_EraseRootFromParent_Done, |
| 36179 | /* 98910 */ // Label 3055: @98910 |
| 36180 | /* 98910 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3056*/ GIMT_Encode4(98964), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 326 // |
| 36181 | /* 98917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36182 | /* 98921 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36183 | /* 98925 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36184 | /* 98929 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36185 | /* 98933 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36186 | /* 98938 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36187 | /* 98942 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36188 | /* 98944 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREV16:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 36189 | /* 98944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV16), |
| 36190 | /* 98947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36191 | /* 98949 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36192 | /* 98953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36193 | /* 98956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36194 | /* 98962 */ GIR_RootConstrainSelectedInstOperands, |
| 36195 | /* 98963 */ // GIR_Coverage, 326, |
| 36196 | /* 98963 */ GIR_EraseRootFromParent_Done, |
| 36197 | /* 98964 */ // Label 3056: @98964 |
| 36198 | /* 98964 */ GIM_Try, /*On fail goto*//*Label 3057*/ GIMT_Encode4(99076), |
| 36199 | /* 98969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36200 | /* 98973 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3058*/ GIMT_Encode4(99023), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 536 // |
| 36201 | /* 98980 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36202 | /* 98984 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36203 | /* 98988 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36204 | /* 98992 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36205 | /* 98997 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36206 | /* 99001 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36207 | /* 99003 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REV16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 36208 | /* 99003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV16), |
| 36209 | /* 99006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36210 | /* 99008 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36211 | /* 99012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36212 | /* 99015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36213 | /* 99021 */ GIR_RootConstrainSelectedInstOperands, |
| 36214 | /* 99022 */ // GIR_Coverage, 536, |
| 36215 | /* 99022 */ GIR_EraseRootFromParent_Done, |
| 36216 | /* 99023 */ // Label 3058: @99023 |
| 36217 | /* 99023 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3059*/ GIMT_Encode4(99075), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 475 // |
| 36218 | /* 99030 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36219 | /* 99034 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36220 | /* 99038 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 36221 | /* 99042 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31), |
| 36222 | /* 99046 */ // MIs[1] Operand 1 |
| 36223 | /* 99046 */ // No operand predicates |
| 36224 | /* 99046 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36225 | /* 99048 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2RORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 36226 | /* 99048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORri), |
| 36227 | /* 99051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36228 | /* 99053 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36229 | /* 99055 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 36230 | /* 99058 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36231 | /* 99061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36232 | /* 99067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36233 | /* 99073 */ GIR_RootConstrainSelectedInstOperands, |
| 36234 | /* 99074 */ // GIR_Coverage, 475, |
| 36235 | /* 99074 */ GIR_EraseRootFromParent_Done, |
| 36236 | /* 99075 */ // Label 3059: @99075 |
| 36237 | /* 99075 */ GIM_Reject, |
| 36238 | /* 99076 */ // Label 3057: @99076 |
| 36239 | /* 99076 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3060*/ GIMT_Encode4(99121), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 328 // |
| 36240 | /* 99083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36241 | /* 99087 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36242 | /* 99091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36243 | /* 99095 */ // (rotr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tROR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 36244 | /* 99095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tROR), |
| 36245 | /* 99098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 36246 | /* 99100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 36247 | /* 99106 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36248 | /* 99108 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36249 | /* 99110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36250 | /* 99113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36251 | /* 99119 */ GIR_RootConstrainSelectedInstOperands, |
| 36252 | /* 99120 */ // GIR_Coverage, 328, |
| 36253 | /* 99120 */ GIR_EraseRootFromParent_Done, |
| 36254 | /* 99121 */ // Label 3060: @99121 |
| 36255 | /* 99121 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3061*/ GIMT_Encode4(99166), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 476 // |
| 36256 | /* 99128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36257 | /* 99132 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36258 | /* 99136 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36259 | /* 99140 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2RORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36260 | /* 99140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORrr), |
| 36261 | /* 99143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36262 | /* 99145 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36263 | /* 99147 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36264 | /* 99149 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36265 | /* 99152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36266 | /* 99158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36267 | /* 99164 */ GIR_RootConstrainSelectedInstOperands, |
| 36268 | /* 99165 */ // GIR_Coverage, 476, |
| 36269 | /* 99165 */ GIR_EraseRootFromParent_Done, |
| 36270 | /* 99166 */ // Label 3061: @99166 |
| 36271 | /* 99166 */ GIM_Reject, |
| 36272 | /* 99167 */ // Label 3054: @99167 |
| 36273 | /* 99167 */ GIM_Reject, |
| 36274 | /* 99168 */ // Label 34: @99168 |
| 36275 | /* 99168 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 3065*/ GIMT_Encode4(99400), |
| 36276 | /* 99179 */ /*GILLT_v16s8*//*Label 3062*/ GIMT_Encode4(99199), GIMT_Encode4(0), |
| 36277 | /* 99187 */ /*GILLT_v8s16*//*Label 3063*/ GIMT_Encode4(99266), GIMT_Encode4(0), |
| 36278 | /* 99195 */ /*GILLT_v4s32*//*Label 3064*/ GIMT_Encode4(99333), |
| 36279 | /* 99199 */ // Label 3062: @99199 |
| 36280 | /* 99199 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3066*/ GIMT_Encode4(99265), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4967 // |
| 36281 | /* 99206 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 36282 | /* 99209 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36283 | /* 99212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36284 | /* 99216 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36285 | /* 99220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36286 | /* 99224 */ // (mulhu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 36287 | /* 99224 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36288 | /* 99227 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36289 | /* 99231 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36290 | /* 99236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8), |
| 36291 | /* 99239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36292 | /* 99241 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36293 | /* 99243 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36294 | /* 99245 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36295 | /* 99248 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36296 | /* 99254 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36297 | /* 99260 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36298 | /* 99263 */ GIR_RootConstrainSelectedInstOperands, |
| 36299 | /* 99264 */ // GIR_Coverage, 4967, |
| 36300 | /* 99264 */ GIR_EraseRootFromParent_Done, |
| 36301 | /* 99265 */ // Label 3066: @99265 |
| 36302 | /* 99265 */ GIM_Reject, |
| 36303 | /* 99266 */ // Label 3063: @99266 |
| 36304 | /* 99266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3067*/ GIMT_Encode4(99332), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4971 // |
| 36305 | /* 99273 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 36306 | /* 99276 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36307 | /* 99279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36308 | /* 99283 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36309 | /* 99287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36310 | /* 99291 */ // (mulhu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 36311 | /* 99291 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36312 | /* 99294 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36313 | /* 99298 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36314 | /* 99303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16), |
| 36315 | /* 99306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36316 | /* 99308 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36317 | /* 99310 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36318 | /* 99312 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36319 | /* 99315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36320 | /* 99321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36321 | /* 99327 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36322 | /* 99330 */ GIR_RootConstrainSelectedInstOperands, |
| 36323 | /* 99331 */ // GIR_Coverage, 4971, |
| 36324 | /* 99331 */ GIR_EraseRootFromParent_Done, |
| 36325 | /* 99332 */ // Label 3067: @99332 |
| 36326 | /* 99332 */ GIM_Reject, |
| 36327 | /* 99333 */ // Label 3064: @99333 |
| 36328 | /* 99333 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3068*/ GIMT_Encode4(99399), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4975 // |
| 36329 | /* 99340 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 36330 | /* 99343 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36331 | /* 99346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36332 | /* 99350 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36333 | /* 99354 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36334 | /* 99358 */ // (mulhu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 36335 | /* 99358 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36336 | /* 99361 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36337 | /* 99365 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36338 | /* 99370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32), |
| 36339 | /* 99373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36340 | /* 99375 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36341 | /* 99377 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36342 | /* 99379 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36343 | /* 99382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36344 | /* 99388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36345 | /* 99394 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36346 | /* 99397 */ GIR_RootConstrainSelectedInstOperands, |
| 36347 | /* 99398 */ // GIR_Coverage, 4975, |
| 36348 | /* 99398 */ GIR_EraseRootFromParent_Done, |
| 36349 | /* 99399 */ // Label 3068: @99399 |
| 36350 | /* 99399 */ GIM_Reject, |
| 36351 | /* 99400 */ // Label 3065: @99400 |
| 36352 | /* 99400 */ GIM_Reject, |
| 36353 | /* 99401 */ // Label 35: @99401 |
| 36354 | /* 99401 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3073*/ GIMT_Encode4(99752), |
| 36355 | /* 99412 */ /*GILLT_s32*//*Label 3069*/ GIMT_Encode4(99460), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36356 | /* 99440 */ /*GILLT_v16s8*//*Label 3070*/ GIMT_Encode4(99551), GIMT_Encode4(0), |
| 36357 | /* 99448 */ /*GILLT_v8s16*//*Label 3071*/ GIMT_Encode4(99618), GIMT_Encode4(0), |
| 36358 | /* 99456 */ /*GILLT_v4s32*//*Label 3072*/ GIMT_Encode4(99685), |
| 36359 | /* 99460 */ // Label 3069: @99460 |
| 36360 | /* 99460 */ GIM_Try, /*On fail goto*//*Label 3074*/ GIMT_Encode4(99550), |
| 36361 | /* 99465 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36362 | /* 99468 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36363 | /* 99471 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3075*/ GIMT_Encode4(99510), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 177 // |
| 36364 | /* 99478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36365 | /* 99482 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36366 | /* 99486 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36367 | /* 99490 */ // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SMMUL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 36368 | /* 99490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMUL), |
| 36369 | /* 99493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36370 | /* 99495 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36371 | /* 99497 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36372 | /* 99499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36373 | /* 99502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36374 | /* 99508 */ GIR_RootConstrainSelectedInstOperands, |
| 36375 | /* 99509 */ // GIR_Coverage, 177, |
| 36376 | /* 99509 */ GIR_EraseRootFromParent_Done, |
| 36377 | /* 99510 */ // Label 3075: @99510 |
| 36378 | /* 99510 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3076*/ GIMT_Encode4(99549), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 506 // |
| 36379 | /* 99517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36380 | /* 99521 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36381 | /* 99525 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36382 | /* 99529 */ // (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMMUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36383 | /* 99529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMUL), |
| 36384 | /* 99532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36385 | /* 99534 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36386 | /* 99536 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36387 | /* 99538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36388 | /* 99541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36389 | /* 99547 */ GIR_RootConstrainSelectedInstOperands, |
| 36390 | /* 99548 */ // GIR_Coverage, 506, |
| 36391 | /* 99548 */ GIR_EraseRootFromParent_Done, |
| 36392 | /* 99549 */ // Label 3076: @99549 |
| 36393 | /* 99549 */ GIM_Reject, |
| 36394 | /* 99550 */ // Label 3074: @99550 |
| 36395 | /* 99550 */ GIM_Reject, |
| 36396 | /* 99551 */ // Label 3070: @99551 |
| 36397 | /* 99551 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3077*/ GIMT_Encode4(99617), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4956 // |
| 36398 | /* 99558 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 36399 | /* 99561 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36400 | /* 99564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36401 | /* 99568 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36402 | /* 99572 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36403 | /* 99576 */ // (mulhs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 36404 | /* 99576 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36405 | /* 99579 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36406 | /* 99583 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36407 | /* 99588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8), |
| 36408 | /* 99591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36409 | /* 99593 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36410 | /* 99595 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36411 | /* 99597 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36412 | /* 99600 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36413 | /* 99606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36414 | /* 99612 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36415 | /* 99615 */ GIR_RootConstrainSelectedInstOperands, |
| 36416 | /* 99616 */ // GIR_Coverage, 4956, |
| 36417 | /* 99616 */ GIR_EraseRootFromParent_Done, |
| 36418 | /* 99617 */ // Label 3077: @99617 |
| 36419 | /* 99617 */ GIM_Reject, |
| 36420 | /* 99618 */ // Label 3071: @99618 |
| 36421 | /* 99618 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3078*/ GIMT_Encode4(99684), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4959 // |
| 36422 | /* 99625 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 36423 | /* 99628 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36424 | /* 99631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36425 | /* 99635 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36426 | /* 99639 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36427 | /* 99643 */ // (mulhs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 36428 | /* 99643 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36429 | /* 99646 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36430 | /* 99650 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36431 | /* 99655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16), |
| 36432 | /* 99658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36433 | /* 99660 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36434 | /* 99662 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36435 | /* 99664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36436 | /* 99667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36437 | /* 99673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36438 | /* 99679 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36439 | /* 99682 */ GIR_RootConstrainSelectedInstOperands, |
| 36440 | /* 99683 */ // GIR_Coverage, 4959, |
| 36441 | /* 99683 */ GIR_EraseRootFromParent_Done, |
| 36442 | /* 99684 */ // Label 3078: @99684 |
| 36443 | /* 99684 */ GIM_Reject, |
| 36444 | /* 99685 */ // Label 3072: @99685 |
| 36445 | /* 99685 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3079*/ GIMT_Encode4(99751), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4963 // |
| 36446 | /* 99692 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 36447 | /* 99695 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36448 | /* 99698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36449 | /* 99702 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36450 | /* 99706 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36451 | /* 99710 */ // (mulhs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 36452 | /* 99710 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36453 | /* 99713 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36454 | /* 99717 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36455 | /* 99722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32), |
| 36456 | /* 99725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36457 | /* 99727 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36458 | /* 99729 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36459 | /* 99731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36460 | /* 99734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36461 | /* 99740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36462 | /* 99746 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36463 | /* 99749 */ GIR_RootConstrainSelectedInstOperands, |
| 36464 | /* 99750 */ // GIR_Coverage, 4963, |
| 36465 | /* 99750 */ GIR_EraseRootFromParent_Done, |
| 36466 | /* 99751 */ // Label 3079: @99751 |
| 36467 | /* 99751 */ GIM_Reject, |
| 36468 | /* 99752 */ // Label 3073: @99752 |
| 36469 | /* 99752 */ GIM_Reject, |
| 36470 | /* 99753 */ // Label 36: @99753 |
| 36471 | /* 99753 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 3088*/ GIMT_Encode4(100378), |
| 36472 | /* 99764 */ /*GILLT_s64*//*Label 3080*/ GIMT_Encode4(99812), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36473 | /* 99784 */ /*GILLT_v8s8*//*Label 3081*/ GIMT_Encode4(99858), |
| 36474 | /* 99788 */ /*GILLT_v16s8*//*Label 3082*/ GIMT_Encode4(99904), |
| 36475 | /* 99792 */ /*GILLT_v4s16*//*Label 3083*/ GIMT_Encode4(100016), |
| 36476 | /* 99796 */ /*GILLT_v8s16*//*Label 3084*/ GIMT_Encode4(100062), |
| 36477 | /* 99800 */ /*GILLT_v2s32*//*Label 3085*/ GIMT_Encode4(100174), |
| 36478 | /* 99804 */ /*GILLT_v4s32*//*Label 3086*/ GIMT_Encode4(100220), |
| 36479 | /* 99808 */ /*GILLT_v2s64*//*Label 3087*/ GIMT_Encode4(100332), |
| 36480 | /* 99812 */ // Label 3080: @99812 |
| 36481 | /* 99812 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3089*/ GIMT_Encode4(99857), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 950 // |
| 36482 | /* 99819 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 36483 | /* 99822 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 36484 | /* 99825 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36485 | /* 99829 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36486 | /* 99833 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36487 | /* 99837 */ // (uaddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 36488 | /* 99837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv1i64), |
| 36489 | /* 99840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36490 | /* 99842 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36491 | /* 99844 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36492 | /* 99846 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36493 | /* 99849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36494 | /* 99855 */ GIR_RootConstrainSelectedInstOperands, |
| 36495 | /* 99856 */ // GIR_Coverage, 950, |
| 36496 | /* 99856 */ GIR_EraseRootFromParent_Done, |
| 36497 | /* 99857 */ // Label 3089: @99857 |
| 36498 | /* 99857 */ GIM_Reject, |
| 36499 | /* 99858 */ // Label 3081: @99858 |
| 36500 | /* 99858 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3090*/ GIMT_Encode4(99903), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 948 // |
| 36501 | /* 99865 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 36502 | /* 99868 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 36503 | /* 99871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36504 | /* 99875 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36505 | /* 99879 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36506 | /* 99883 */ // (uaddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 36507 | /* 99883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i8), |
| 36508 | /* 99886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36509 | /* 99888 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36510 | /* 99890 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36511 | /* 99892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36512 | /* 99895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36513 | /* 99901 */ GIR_RootConstrainSelectedInstOperands, |
| 36514 | /* 99902 */ // GIR_Coverage, 948, |
| 36515 | /* 99902 */ GIR_EraseRootFromParent_Done, |
| 36516 | /* 99903 */ // Label 3090: @99903 |
| 36517 | /* 99903 */ GIM_Reject, |
| 36518 | /* 99904 */ // Label 3082: @99904 |
| 36519 | /* 99904 */ GIM_Try, /*On fail goto*//*Label 3091*/ GIMT_Encode4(100015), |
| 36520 | /* 99909 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 36521 | /* 99912 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36522 | /* 99915 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3092*/ GIMT_Encode4(99954), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 949 // |
| 36523 | /* 99922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36524 | /* 99926 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36525 | /* 99930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36526 | /* 99934 */ // (uaddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 36527 | /* 99934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv16i8), |
| 36528 | /* 99937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36529 | /* 99939 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36530 | /* 99941 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36531 | /* 99943 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36532 | /* 99946 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36533 | /* 99952 */ GIR_RootConstrainSelectedInstOperands, |
| 36534 | /* 99953 */ // GIR_Coverage, 949, |
| 36535 | /* 99953 */ GIR_EraseRootFromParent_Done, |
| 36536 | /* 99954 */ // Label 3092: @99954 |
| 36537 | /* 99954 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3093*/ GIMT_Encode4(100014), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3918 // |
| 36538 | /* 99961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36539 | /* 99965 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36540 | /* 99969 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36541 | /* 99973 */ // (uaddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 36542 | /* 99973 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36543 | /* 99976 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36544 | /* 99980 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36545 | /* 99985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu8), |
| 36546 | /* 99988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36547 | /* 99990 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36548 | /* 99992 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36549 | /* 99994 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36550 | /* 99997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36551 | /* 100003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36552 | /* 100009 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36553 | /* 100012 */ GIR_RootConstrainSelectedInstOperands, |
| 36554 | /* 100013 */ // GIR_Coverage, 3918, |
| 36555 | /* 100013 */ GIR_EraseRootFromParent_Done, |
| 36556 | /* 100014 */ // Label 3093: @100014 |
| 36557 | /* 100014 */ GIM_Reject, |
| 36558 | /* 100015 */ // Label 3091: @100015 |
| 36559 | /* 100015 */ GIM_Reject, |
| 36560 | /* 100016 */ // Label 3083: @100016 |
| 36561 | /* 100016 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3094*/ GIMT_Encode4(100061), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 944 // |
| 36562 | /* 100023 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 36563 | /* 100026 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36564 | /* 100029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36565 | /* 100033 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36566 | /* 100037 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36567 | /* 100041 */ // (uaddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 36568 | /* 100041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i16), |
| 36569 | /* 100044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36570 | /* 100046 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36571 | /* 100048 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36572 | /* 100050 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36573 | /* 100053 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36574 | /* 100059 */ GIR_RootConstrainSelectedInstOperands, |
| 36575 | /* 100060 */ // GIR_Coverage, 944, |
| 36576 | /* 100060 */ GIR_EraseRootFromParent_Done, |
| 36577 | /* 100061 */ // Label 3094: @100061 |
| 36578 | /* 100061 */ GIM_Reject, |
| 36579 | /* 100062 */ // Label 3084: @100062 |
| 36580 | /* 100062 */ GIM_Try, /*On fail goto*//*Label 3095*/ GIMT_Encode4(100173), |
| 36581 | /* 100067 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 36582 | /* 100070 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36583 | /* 100073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3096*/ GIMT_Encode4(100112), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 946 // |
| 36584 | /* 100080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36585 | /* 100084 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36586 | /* 100088 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36587 | /* 100092 */ // (uaddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 36588 | /* 100092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i16), |
| 36589 | /* 100095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36590 | /* 100097 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36591 | /* 100099 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36592 | /* 100101 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36593 | /* 100104 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36594 | /* 100110 */ GIR_RootConstrainSelectedInstOperands, |
| 36595 | /* 100111 */ // GIR_Coverage, 946, |
| 36596 | /* 100111 */ GIR_EraseRootFromParent_Done, |
| 36597 | /* 100112 */ // Label 3096: @100112 |
| 36598 | /* 100112 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3097*/ GIMT_Encode4(100172), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3921 // |
| 36599 | /* 100119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36600 | /* 100123 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36601 | /* 100127 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36602 | /* 100131 */ // (uaddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 36603 | /* 100131 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36604 | /* 100134 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36605 | /* 100138 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36606 | /* 100143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu16), |
| 36607 | /* 100146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36608 | /* 100148 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36609 | /* 100150 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36610 | /* 100152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36611 | /* 100155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36612 | /* 100161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36613 | /* 100167 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36614 | /* 100170 */ GIR_RootConstrainSelectedInstOperands, |
| 36615 | /* 100171 */ // GIR_Coverage, 3921, |
| 36616 | /* 100171 */ GIR_EraseRootFromParent_Done, |
| 36617 | /* 100172 */ // Label 3097: @100172 |
| 36618 | /* 100172 */ GIM_Reject, |
| 36619 | /* 100173 */ // Label 3095: @100173 |
| 36620 | /* 100173 */ GIM_Reject, |
| 36621 | /* 100174 */ // Label 3085: @100174 |
| 36622 | /* 100174 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3098*/ GIMT_Encode4(100219), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 945 // |
| 36623 | /* 100181 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 36624 | /* 100184 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 36625 | /* 100187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36626 | /* 100191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36627 | /* 100195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36628 | /* 100199 */ // (uaddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 36629 | /* 100199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i32), |
| 36630 | /* 100202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36631 | /* 100204 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36632 | /* 100206 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36633 | /* 100208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36634 | /* 100211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36635 | /* 100217 */ GIR_RootConstrainSelectedInstOperands, |
| 36636 | /* 100218 */ // GIR_Coverage, 945, |
| 36637 | /* 100218 */ GIR_EraseRootFromParent_Done, |
| 36638 | /* 100219 */ // Label 3098: @100219 |
| 36639 | /* 100219 */ GIM_Reject, |
| 36640 | /* 100220 */ // Label 3086: @100220 |
| 36641 | /* 100220 */ GIM_Try, /*On fail goto*//*Label 3099*/ GIMT_Encode4(100331), |
| 36642 | /* 100225 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 36643 | /* 100228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36644 | /* 100231 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3100*/ GIMT_Encode4(100270), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 947 // |
| 36645 | /* 100238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36646 | /* 100242 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36647 | /* 100246 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36648 | /* 100250 */ // (uaddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 36649 | /* 100250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i32), |
| 36650 | /* 100253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36651 | /* 100255 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36652 | /* 100257 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36653 | /* 100259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36654 | /* 100262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36655 | /* 100268 */ GIR_RootConstrainSelectedInstOperands, |
| 36656 | /* 100269 */ // GIR_Coverage, 947, |
| 36657 | /* 100269 */ GIR_EraseRootFromParent_Done, |
| 36658 | /* 100270 */ // Label 3100: @100270 |
| 36659 | /* 100270 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3101*/ GIMT_Encode4(100330), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3924 // |
| 36660 | /* 100277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36661 | /* 100281 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36662 | /* 100285 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36663 | /* 100289 */ // (uaddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 36664 | /* 100289 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36665 | /* 100292 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36666 | /* 100296 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36667 | /* 100301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu32), |
| 36668 | /* 100304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36669 | /* 100306 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36670 | /* 100308 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36671 | /* 100310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36672 | /* 100313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36673 | /* 100319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36674 | /* 100325 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36675 | /* 100328 */ GIR_RootConstrainSelectedInstOperands, |
| 36676 | /* 100329 */ // GIR_Coverage, 3924, |
| 36677 | /* 100329 */ GIR_EraseRootFromParent_Done, |
| 36678 | /* 100330 */ // Label 3101: @100330 |
| 36679 | /* 100330 */ GIM_Reject, |
| 36680 | /* 100331 */ // Label 3099: @100331 |
| 36681 | /* 100331 */ GIM_Reject, |
| 36682 | /* 100332 */ // Label 3087: @100332 |
| 36683 | /* 100332 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3102*/ GIMT_Encode4(100377), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 951 // |
| 36684 | /* 100339 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 36685 | /* 100342 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 36686 | /* 100345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36687 | /* 100349 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36688 | /* 100353 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36689 | /* 100357 */ // (uaddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 36690 | /* 100357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i64), |
| 36691 | /* 100360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36692 | /* 100362 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36693 | /* 100364 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36694 | /* 100366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36695 | /* 100369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36696 | /* 100375 */ GIR_RootConstrainSelectedInstOperands, |
| 36697 | /* 100376 */ // GIR_Coverage, 951, |
| 36698 | /* 100376 */ GIR_EraseRootFromParent_Done, |
| 36699 | /* 100377 */ // Label 3102: @100377 |
| 36700 | /* 100377 */ GIM_Reject, |
| 36701 | /* 100378 */ // Label 3088: @100378 |
| 36702 | /* 100378 */ GIM_Reject, |
| 36703 | /* 100379 */ // Label 37: @100379 |
| 36704 | /* 100379 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 3112*/ GIMT_Encode4(101651), |
| 36705 | /* 100390 */ /*GILLT_s32*//*Label 3103*/ GIMT_Encode4(100442), |
| 36706 | /* 100394 */ /*GILLT_s64*//*Label 3104*/ GIMT_Encode4(100777), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36707 | /* 100414 */ /*GILLT_v8s8*//*Label 3105*/ GIMT_Encode4(100823), |
| 36708 | /* 100418 */ /*GILLT_v16s8*//*Label 3106*/ GIMT_Encode4(100869), |
| 36709 | /* 100422 */ /*GILLT_v4s16*//*Label 3107*/ GIMT_Encode4(100981), |
| 36710 | /* 100426 */ /*GILLT_v8s16*//*Label 3108*/ GIMT_Encode4(101027), |
| 36711 | /* 100430 */ /*GILLT_v2s32*//*Label 3109*/ GIMT_Encode4(101139), |
| 36712 | /* 100434 */ /*GILLT_v4s32*//*Label 3110*/ GIMT_Encode4(101185), |
| 36713 | /* 100438 */ /*GILLT_v2s64*//*Label 3111*/ GIMT_Encode4(101451), |
| 36714 | /* 100442 */ // Label 3103: @100442 |
| 36715 | /* 100442 */ GIM_Try, /*On fail goto*//*Label 3113*/ GIMT_Encode4(100776), |
| 36716 | /* 100447 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36717 | /* 100450 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36718 | /* 100453 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3114*/ GIMT_Encode4(100514), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 6254 // |
| 36719 | /* 100460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36720 | /* 100464 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36721 | /* 100468 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 36722 | /* 100472 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36723 | /* 100476 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36724 | /* 100481 */ // MIs[1] Rn |
| 36725 | /* 100481 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 36726 | /* 100486 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36727 | /* 100490 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36728 | /* 100492 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36729 | /* 100492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 36730 | /* 100495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36731 | /* 100497 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36732 | /* 100499 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 36733 | /* 100503 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36734 | /* 100506 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36735 | /* 100512 */ GIR_RootConstrainSelectedInstOperands, |
| 36736 | /* 100513 */ // GIR_Coverage, 6254, |
| 36737 | /* 100513 */ GIR_EraseRootFromParent_Done, |
| 36738 | /* 100514 */ // Label 3114: @100514 |
| 36739 | /* 100514 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3115*/ GIMT_Encode4(100575), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6294 // |
| 36740 | /* 100521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36741 | /* 100525 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36742 | /* 100529 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 36743 | /* 100533 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36744 | /* 100537 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36745 | /* 100542 */ // MIs[1] Rn |
| 36746 | /* 100542 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 36747 | /* 100547 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36748 | /* 100551 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36749 | /* 100553 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36750 | /* 100553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 36751 | /* 100556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36752 | /* 100558 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36753 | /* 100560 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 36754 | /* 100564 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36755 | /* 100567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36756 | /* 100573 */ GIR_RootConstrainSelectedInstOperands, |
| 36757 | /* 100574 */ // GIR_Coverage, 6294, |
| 36758 | /* 100574 */ GIR_EraseRootFromParent_Done, |
| 36759 | /* 100575 */ // Label 3115: @100575 |
| 36760 | /* 100575 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3116*/ GIMT_Encode4(100636), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2058 // |
| 36761 | /* 100582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36762 | /* 100586 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36763 | /* 100590 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36764 | /* 100594 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 36765 | /* 100598 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36766 | /* 100602 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36767 | /* 100607 */ // MIs[1] Rn |
| 36768 | /* 100607 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 36769 | /* 100612 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36770 | /* 100614 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36771 | /* 100614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 36772 | /* 100617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36773 | /* 100619 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36774 | /* 100621 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 36775 | /* 100625 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36776 | /* 100628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36777 | /* 100634 */ GIR_RootConstrainSelectedInstOperands, |
| 36778 | /* 100635 */ // GIR_Coverage, 2058, |
| 36779 | /* 100635 */ GIR_EraseRootFromParent_Done, |
| 36780 | /* 100636 */ // Label 3116: @100636 |
| 36781 | /* 100636 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3117*/ GIMT_Encode4(100697), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2332 // |
| 36782 | /* 100643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36783 | /* 100647 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36784 | /* 100651 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36785 | /* 100655 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 36786 | /* 100659 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36787 | /* 100663 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36788 | /* 100668 */ // MIs[1] Rn |
| 36789 | /* 100668 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 36790 | /* 100673 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36791 | /* 100675 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36792 | /* 100675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 36793 | /* 100678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36794 | /* 100680 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36795 | /* 100682 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 36796 | /* 100686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36797 | /* 100689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36798 | /* 100695 */ GIR_RootConstrainSelectedInstOperands, |
| 36799 | /* 100696 */ // GIR_Coverage, 2332, |
| 36800 | /* 100696 */ GIR_EraseRootFromParent_Done, |
| 36801 | /* 100697 */ // Label 3117: @100697 |
| 36802 | /* 100697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3118*/ GIMT_Encode4(100736), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2056 // |
| 36803 | /* 100704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36804 | /* 100708 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36805 | /* 100712 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36806 | /* 100716 */ // (saddsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QADD:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 36807 | /* 100716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD), |
| 36808 | /* 100719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36809 | /* 100721 */ GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 36810 | /* 100723 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 36811 | /* 100725 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36812 | /* 100728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36813 | /* 100734 */ GIR_RootConstrainSelectedInstOperands, |
| 36814 | /* 100735 */ // GIR_Coverage, 2056, |
| 36815 | /* 100735 */ GIR_EraseRootFromParent_Done, |
| 36816 | /* 100736 */ // Label 3118: @100736 |
| 36817 | /* 100736 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3119*/ GIMT_Encode4(100775), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2330 // |
| 36818 | /* 100743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36819 | /* 100747 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36820 | /* 100751 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36821 | /* 100755 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36822 | /* 100755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD), |
| 36823 | /* 100758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36824 | /* 100760 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36825 | /* 100762 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36826 | /* 100764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36827 | /* 100767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36828 | /* 100773 */ GIR_RootConstrainSelectedInstOperands, |
| 36829 | /* 100774 */ // GIR_Coverage, 2330, |
| 36830 | /* 100774 */ GIR_EraseRootFromParent_Done, |
| 36831 | /* 100775 */ // Label 3119: @100775 |
| 36832 | /* 100775 */ GIM_Reject, |
| 36833 | /* 100776 */ // Label 3113: @100776 |
| 36834 | /* 100776 */ GIM_Reject, |
| 36835 | /* 100777 */ // Label 3104: @100777 |
| 36836 | /* 100777 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3120*/ GIMT_Encode4(100822), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 942 // |
| 36837 | /* 100784 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 36838 | /* 100787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 36839 | /* 100790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36840 | /* 100794 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36841 | /* 100798 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36842 | /* 100802 */ // (saddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 36843 | /* 100802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv1i64), |
| 36844 | /* 100805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36845 | /* 100807 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36846 | /* 100809 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36847 | /* 100811 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36848 | /* 100814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36849 | /* 100820 */ GIR_RootConstrainSelectedInstOperands, |
| 36850 | /* 100821 */ // GIR_Coverage, 942, |
| 36851 | /* 100821 */ GIR_EraseRootFromParent_Done, |
| 36852 | /* 100822 */ // Label 3120: @100822 |
| 36853 | /* 100822 */ GIM_Reject, |
| 36854 | /* 100823 */ // Label 3105: @100823 |
| 36855 | /* 100823 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3121*/ GIMT_Encode4(100868), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 940 // |
| 36856 | /* 100830 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 36857 | /* 100833 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 36858 | /* 100836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36859 | /* 100840 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36860 | /* 100844 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36861 | /* 100848 */ // (saddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 36862 | /* 100848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i8), |
| 36863 | /* 100851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36864 | /* 100853 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36865 | /* 100855 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36866 | /* 100857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36867 | /* 100860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36868 | /* 100866 */ GIR_RootConstrainSelectedInstOperands, |
| 36869 | /* 100867 */ // GIR_Coverage, 940, |
| 36870 | /* 100867 */ GIR_EraseRootFromParent_Done, |
| 36871 | /* 100868 */ // Label 3121: @100868 |
| 36872 | /* 100868 */ GIM_Reject, |
| 36873 | /* 100869 */ // Label 3106: @100869 |
| 36874 | /* 100869 */ GIM_Try, /*On fail goto*//*Label 3122*/ GIMT_Encode4(100980), |
| 36875 | /* 100874 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 36876 | /* 100877 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36877 | /* 100880 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3123*/ GIMT_Encode4(100919), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 941 // |
| 36878 | /* 100887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36879 | /* 100891 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36880 | /* 100895 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36881 | /* 100899 */ // (saddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 36882 | /* 100899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv16i8), |
| 36883 | /* 100902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36884 | /* 100904 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36885 | /* 100906 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36886 | /* 100908 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36887 | /* 100911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36888 | /* 100917 */ GIR_RootConstrainSelectedInstOperands, |
| 36889 | /* 100918 */ // GIR_Coverage, 941, |
| 36890 | /* 100918 */ GIR_EraseRootFromParent_Done, |
| 36891 | /* 100919 */ // Label 3123: @100919 |
| 36892 | /* 100919 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3124*/ GIMT_Encode4(100979), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3909 // |
| 36893 | /* 100926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36894 | /* 100930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36895 | /* 100934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36896 | /* 100938 */ // (saddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 36897 | /* 100938 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36898 | /* 100941 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36899 | /* 100945 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36900 | /* 100950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs8), |
| 36901 | /* 100953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36902 | /* 100955 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36903 | /* 100957 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36904 | /* 100959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36905 | /* 100962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36906 | /* 100968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36907 | /* 100974 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36908 | /* 100977 */ GIR_RootConstrainSelectedInstOperands, |
| 36909 | /* 100978 */ // GIR_Coverage, 3909, |
| 36910 | /* 100978 */ GIR_EraseRootFromParent_Done, |
| 36911 | /* 100979 */ // Label 3124: @100979 |
| 36912 | /* 100979 */ GIM_Reject, |
| 36913 | /* 100980 */ // Label 3122: @100980 |
| 36914 | /* 100980 */ GIM_Reject, |
| 36915 | /* 100981 */ // Label 3107: @100981 |
| 36916 | /* 100981 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3125*/ GIMT_Encode4(101026), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 936 // |
| 36917 | /* 100988 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 36918 | /* 100991 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36919 | /* 100994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36920 | /* 100998 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36921 | /* 101002 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36922 | /* 101006 */ // (saddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 36923 | /* 101006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i16), |
| 36924 | /* 101009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36925 | /* 101011 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36926 | /* 101013 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36927 | /* 101015 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36928 | /* 101018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36929 | /* 101024 */ GIR_RootConstrainSelectedInstOperands, |
| 36930 | /* 101025 */ // GIR_Coverage, 936, |
| 36931 | /* 101025 */ GIR_EraseRootFromParent_Done, |
| 36932 | /* 101026 */ // Label 3125: @101026 |
| 36933 | /* 101026 */ GIM_Reject, |
| 36934 | /* 101027 */ // Label 3108: @101027 |
| 36935 | /* 101027 */ GIM_Try, /*On fail goto*//*Label 3126*/ GIMT_Encode4(101138), |
| 36936 | /* 101032 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 36937 | /* 101035 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36938 | /* 101038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3127*/ GIMT_Encode4(101077), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 938 // |
| 36939 | /* 101045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36940 | /* 101049 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36941 | /* 101053 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36942 | /* 101057 */ // (saddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 36943 | /* 101057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i16), |
| 36944 | /* 101060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36945 | /* 101062 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36946 | /* 101064 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36947 | /* 101066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36948 | /* 101069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36949 | /* 101075 */ GIR_RootConstrainSelectedInstOperands, |
| 36950 | /* 101076 */ // GIR_Coverage, 938, |
| 36951 | /* 101076 */ GIR_EraseRootFromParent_Done, |
| 36952 | /* 101077 */ // Label 3127: @101077 |
| 36953 | /* 101077 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3128*/ GIMT_Encode4(101137), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3912 // |
| 36954 | /* 101084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36955 | /* 101088 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36956 | /* 101092 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36957 | /* 101096 */ // (saddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 36958 | /* 101096 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36959 | /* 101099 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36960 | /* 101103 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36961 | /* 101108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs16), |
| 36962 | /* 101111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36963 | /* 101113 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36964 | /* 101115 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36965 | /* 101117 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36966 | /* 101120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36967 | /* 101126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36968 | /* 101132 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36969 | /* 101135 */ GIR_RootConstrainSelectedInstOperands, |
| 36970 | /* 101136 */ // GIR_Coverage, 3912, |
| 36971 | /* 101136 */ GIR_EraseRootFromParent_Done, |
| 36972 | /* 101137 */ // Label 3128: @101137 |
| 36973 | /* 101137 */ GIM_Reject, |
| 36974 | /* 101138 */ // Label 3126: @101138 |
| 36975 | /* 101138 */ GIM_Reject, |
| 36976 | /* 101139 */ // Label 3109: @101139 |
| 36977 | /* 101139 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3129*/ GIMT_Encode4(101184), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 937 // |
| 36978 | /* 101146 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 36979 | /* 101149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 36980 | /* 101152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36981 | /* 101156 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36982 | /* 101160 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36983 | /* 101164 */ // (saddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 36984 | /* 101164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i32), |
| 36985 | /* 101167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36986 | /* 101169 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36987 | /* 101171 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36988 | /* 101173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36989 | /* 101176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36990 | /* 101182 */ GIR_RootConstrainSelectedInstOperands, |
| 36991 | /* 101183 */ // GIR_Coverage, 937, |
| 36992 | /* 101183 */ GIR_EraseRootFromParent_Done, |
| 36993 | /* 101184 */ // Label 3129: @101184 |
| 36994 | /* 101184 */ GIM_Reject, |
| 36995 | /* 101185 */ // Label 3110: @101185 |
| 36996 | /* 101185 */ GIM_Try, /*On fail goto*//*Label 3130*/ GIMT_Encode4(101450), |
| 36997 | /* 101190 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 36998 | /* 101193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36999 | /* 101196 */ GIM_Try, /*On fail goto*//*Label 3131*/ GIMT_Encode4(101389), |
| 37000 | /* 101201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37001 | /* 101205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3132*/ GIMT_Encode4(101278), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6377 // |
| 37002 | /* 101212 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 37003 | /* 101216 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37004 | /* 101220 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37005 | /* 101223 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37006 | /* 101228 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37007 | /* 101232 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 37008 | /* 101236 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37009 | /* 101241 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37010 | /* 101246 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37011 | /* 101250 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37012 | /* 101252 */ // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 4044:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37013 | /* 101252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32), |
| 37014 | /* 101255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37015 | /* 101257 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 37016 | /* 101259 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37017 | /* 101263 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37018 | /* 101267 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37019 | /* 101270 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37020 | /* 101276 */ GIR_RootConstrainSelectedInstOperands, |
| 37021 | /* 101277 */ // GIR_Coverage, 6377, |
| 37022 | /* 101277 */ GIR_EraseRootFromParent_Done, |
| 37023 | /* 101278 */ // Label 3132: @101278 |
| 37024 | /* 101278 */ GIM_Try, /*On fail goto*//*Label 3133*/ GIMT_Encode4(101388), |
| 37025 | /* 101283 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37026 | /* 101287 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3134*/ GIMT_Encode4(101356), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2872 // |
| 37027 | /* 101294 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37028 | /* 101298 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37029 | /* 101302 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37030 | /* 101305 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37031 | /* 101310 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37032 | /* 101314 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 37033 | /* 101318 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37034 | /* 101323 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37035 | /* 101328 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37036 | /* 101330 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 4044:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37037 | /* 101330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32), |
| 37038 | /* 101333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37039 | /* 101335 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37040 | /* 101337 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37041 | /* 101341 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37042 | /* 101345 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37043 | /* 101348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37044 | /* 101354 */ GIR_RootConstrainSelectedInstOperands, |
| 37045 | /* 101355 */ // GIR_Coverage, 2872, |
| 37046 | /* 101355 */ GIR_EraseRootFromParent_Done, |
| 37047 | /* 101356 */ // Label 3134: @101356 |
| 37048 | /* 101356 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3135*/ GIMT_Encode4(101387), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 939 // |
| 37049 | /* 101363 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37050 | /* 101367 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 37051 | /* 101367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i32), |
| 37052 | /* 101370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37053 | /* 101372 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37054 | /* 101374 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37055 | /* 101376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37056 | /* 101379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37057 | /* 101385 */ GIR_RootConstrainSelectedInstOperands, |
| 37058 | /* 101386 */ // GIR_Coverage, 939, |
| 37059 | /* 101386 */ GIR_EraseRootFromParent_Done, |
| 37060 | /* 101387 */ // Label 3135: @101387 |
| 37061 | /* 101387 */ GIM_Reject, |
| 37062 | /* 101388 */ // Label 3133: @101388 |
| 37063 | /* 101388 */ GIM_Reject, |
| 37064 | /* 101389 */ // Label 3131: @101389 |
| 37065 | /* 101389 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3136*/ GIMT_Encode4(101449), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3915 // |
| 37066 | /* 101396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37067 | /* 101400 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37068 | /* 101404 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37069 | /* 101408 */ // (saddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 37070 | /* 101408 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37071 | /* 101411 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37072 | /* 101415 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37073 | /* 101420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs32), |
| 37074 | /* 101423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37075 | /* 101425 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37076 | /* 101427 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37077 | /* 101429 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37078 | /* 101432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37079 | /* 101438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37080 | /* 101444 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37081 | /* 101447 */ GIR_RootConstrainSelectedInstOperands, |
| 37082 | /* 101448 */ // GIR_Coverage, 3915, |
| 37083 | /* 101448 */ GIR_EraseRootFromParent_Done, |
| 37084 | /* 101449 */ // Label 3136: @101449 |
| 37085 | /* 101449 */ GIM_Reject, |
| 37086 | /* 101450 */ // Label 3130: @101450 |
| 37087 | /* 101450 */ GIM_Reject, |
| 37088 | /* 101451 */ // Label 3111: @101451 |
| 37089 | /* 101451 */ GIM_Try, /*On fail goto*//*Label 3137*/ GIMT_Encode4(101650), |
| 37090 | /* 101456 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 37091 | /* 101459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 37092 | /* 101462 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37093 | /* 101466 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3138*/ GIMT_Encode4(101539), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6378 // |
| 37094 | /* 101473 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 37095 | /* 101477 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37096 | /* 101481 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37097 | /* 101484 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37098 | /* 101489 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37099 | /* 101493 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 37100 | /* 101497 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37101 | /* 101502 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37102 | /* 101507 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37103 | /* 101511 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37104 | /* 101513 */ // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 4044:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$src1) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37105 | /* 101513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64), |
| 37106 | /* 101516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37107 | /* 101518 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 37108 | /* 101520 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37109 | /* 101524 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37110 | /* 101528 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37111 | /* 101531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37112 | /* 101537 */ GIR_RootConstrainSelectedInstOperands, |
| 37113 | /* 101538 */ // GIR_Coverage, 6378, |
| 37114 | /* 101538 */ GIR_EraseRootFromParent_Done, |
| 37115 | /* 101539 */ // Label 3138: @101539 |
| 37116 | /* 101539 */ GIM_Try, /*On fail goto*//*Label 3139*/ GIMT_Encode4(101649), |
| 37117 | /* 101544 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37118 | /* 101548 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3140*/ GIMT_Encode4(101617), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2873 // |
| 37119 | /* 101555 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37120 | /* 101559 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37121 | /* 101563 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37122 | /* 101566 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37123 | /* 101571 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37124 | /* 101575 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 37125 | /* 101579 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37126 | /* 101584 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37127 | /* 101589 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37128 | /* 101591 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 4044:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37129 | /* 101591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64), |
| 37130 | /* 101594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37131 | /* 101596 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37132 | /* 101598 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37133 | /* 101602 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37134 | /* 101606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37135 | /* 101609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37136 | /* 101615 */ GIR_RootConstrainSelectedInstOperands, |
| 37137 | /* 101616 */ // GIR_Coverage, 2873, |
| 37138 | /* 101616 */ GIR_EraseRootFromParent_Done, |
| 37139 | /* 101617 */ // Label 3140: @101617 |
| 37140 | /* 101617 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3141*/ GIMT_Encode4(101648), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 943 // |
| 37141 | /* 101624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37142 | /* 101628 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 37143 | /* 101628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i64), |
| 37144 | /* 101631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37145 | /* 101633 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37146 | /* 101635 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37147 | /* 101637 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37148 | /* 101640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37149 | /* 101646 */ GIR_RootConstrainSelectedInstOperands, |
| 37150 | /* 101647 */ // GIR_Coverage, 943, |
| 37151 | /* 101647 */ GIR_EraseRootFromParent_Done, |
| 37152 | /* 101648 */ // Label 3141: @101648 |
| 37153 | /* 101648 */ GIM_Reject, |
| 37154 | /* 101649 */ // Label 3139: @101649 |
| 37155 | /* 101649 */ GIM_Reject, |
| 37156 | /* 101650 */ // Label 3137: @101650 |
| 37157 | /* 101650 */ GIM_Reject, |
| 37158 | /* 101651 */ // Label 3112: @101651 |
| 37159 | /* 101651 */ GIM_Reject, |
| 37160 | /* 101652 */ // Label 38: @101652 |
| 37161 | /* 101652 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 3150*/ GIMT_Encode4(102277), |
| 37162 | /* 101663 */ /*GILLT_s64*//*Label 3142*/ GIMT_Encode4(101711), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 37163 | /* 101683 */ /*GILLT_v8s8*//*Label 3143*/ GIMT_Encode4(101757), |
| 37164 | /* 101687 */ /*GILLT_v16s8*//*Label 3144*/ GIMT_Encode4(101803), |
| 37165 | /* 101691 */ /*GILLT_v4s16*//*Label 3145*/ GIMT_Encode4(101915), |
| 37166 | /* 101695 */ /*GILLT_v8s16*//*Label 3146*/ GIMT_Encode4(101961), |
| 37167 | /* 101699 */ /*GILLT_v2s32*//*Label 3147*/ GIMT_Encode4(102073), |
| 37168 | /* 101703 */ /*GILLT_v4s32*//*Label 3148*/ GIMT_Encode4(102119), |
| 37169 | /* 101707 */ /*GILLT_v2s64*//*Label 3149*/ GIMT_Encode4(102231), |
| 37170 | /* 101711 */ // Label 3142: @101711 |
| 37171 | /* 101711 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3151*/ GIMT_Encode4(101756), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1184 // |
| 37172 | /* 101718 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 37173 | /* 101721 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 37174 | /* 101724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37175 | /* 101728 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37176 | /* 101732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37177 | /* 101736 */ // (usubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 37178 | /* 101736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv1i64), |
| 37179 | /* 101739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37180 | /* 101741 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37181 | /* 101743 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37182 | /* 101745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37183 | /* 101748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37184 | /* 101754 */ GIR_RootConstrainSelectedInstOperands, |
| 37185 | /* 101755 */ // GIR_Coverage, 1184, |
| 37186 | /* 101755 */ GIR_EraseRootFromParent_Done, |
| 37187 | /* 101756 */ // Label 3151: @101756 |
| 37188 | /* 101756 */ GIM_Reject, |
| 37189 | /* 101757 */ // Label 3143: @101757 |
| 37190 | /* 101757 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3152*/ GIMT_Encode4(101802), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1182 // |
| 37191 | /* 101764 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 37192 | /* 101767 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 37193 | /* 101770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37194 | /* 101774 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37195 | /* 101778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37196 | /* 101782 */ // (usubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 37197 | /* 101782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i8), |
| 37198 | /* 101785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37199 | /* 101787 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37200 | /* 101789 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37201 | /* 101791 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37202 | /* 101794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37203 | /* 101800 */ GIR_RootConstrainSelectedInstOperands, |
| 37204 | /* 101801 */ // GIR_Coverage, 1182, |
| 37205 | /* 101801 */ GIR_EraseRootFromParent_Done, |
| 37206 | /* 101802 */ // Label 3152: @101802 |
| 37207 | /* 101802 */ GIM_Reject, |
| 37208 | /* 101803 */ // Label 3144: @101803 |
| 37209 | /* 101803 */ GIM_Try, /*On fail goto*//*Label 3153*/ GIMT_Encode4(101914), |
| 37210 | /* 101808 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 37211 | /* 101811 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 37212 | /* 101814 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3154*/ GIMT_Encode4(101853), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1183 // |
| 37213 | /* 101821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37214 | /* 101825 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37215 | /* 101829 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37216 | /* 101833 */ // (usubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 37217 | /* 101833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv16i8), |
| 37218 | /* 101836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37219 | /* 101838 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37220 | /* 101840 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37221 | /* 101842 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37222 | /* 101845 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37223 | /* 101851 */ GIR_RootConstrainSelectedInstOperands, |
| 37224 | /* 101852 */ // GIR_Coverage, 1183, |
| 37225 | /* 101852 */ GIR_EraseRootFromParent_Done, |
| 37226 | /* 101853 */ // Label 3154: @101853 |
| 37227 | /* 101853 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3155*/ GIMT_Encode4(101913), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3936 // |
| 37228 | /* 101860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37229 | /* 101864 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37230 | /* 101868 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37231 | /* 101872 */ // (usubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 37232 | /* 101872 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37233 | /* 101875 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37234 | /* 101879 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37235 | /* 101884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu8), |
| 37236 | /* 101887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37237 | /* 101889 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37238 | /* 101891 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37239 | /* 101893 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37240 | /* 101896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37241 | /* 101902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37242 | /* 101908 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37243 | /* 101911 */ GIR_RootConstrainSelectedInstOperands, |
| 37244 | /* 101912 */ // GIR_Coverage, 3936, |
| 37245 | /* 101912 */ GIR_EraseRootFromParent_Done, |
| 37246 | /* 101913 */ // Label 3155: @101913 |
| 37247 | /* 101913 */ GIM_Reject, |
| 37248 | /* 101914 */ // Label 3153: @101914 |
| 37249 | /* 101914 */ GIM_Reject, |
| 37250 | /* 101915 */ // Label 3145: @101915 |
| 37251 | /* 101915 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3156*/ GIMT_Encode4(101960), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1178 // |
| 37252 | /* 101922 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 37253 | /* 101925 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37254 | /* 101928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37255 | /* 101932 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37256 | /* 101936 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37257 | /* 101940 */ // (usubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37258 | /* 101940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i16), |
| 37259 | /* 101943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37260 | /* 101945 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37261 | /* 101947 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37262 | /* 101949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37263 | /* 101952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37264 | /* 101958 */ GIR_RootConstrainSelectedInstOperands, |
| 37265 | /* 101959 */ // GIR_Coverage, 1178, |
| 37266 | /* 101959 */ GIR_EraseRootFromParent_Done, |
| 37267 | /* 101960 */ // Label 3156: @101960 |
| 37268 | /* 101960 */ GIM_Reject, |
| 37269 | /* 101961 */ // Label 3146: @101961 |
| 37270 | /* 101961 */ GIM_Try, /*On fail goto*//*Label 3157*/ GIMT_Encode4(102072), |
| 37271 | /* 101966 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 37272 | /* 101969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 37273 | /* 101972 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3158*/ GIMT_Encode4(102011), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1180 // |
| 37274 | /* 101979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37275 | /* 101983 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37276 | /* 101987 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37277 | /* 101991 */ // (usubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 37278 | /* 101991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i16), |
| 37279 | /* 101994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37280 | /* 101996 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37281 | /* 101998 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37282 | /* 102000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37283 | /* 102003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37284 | /* 102009 */ GIR_RootConstrainSelectedInstOperands, |
| 37285 | /* 102010 */ // GIR_Coverage, 1180, |
| 37286 | /* 102010 */ GIR_EraseRootFromParent_Done, |
| 37287 | /* 102011 */ // Label 3158: @102011 |
| 37288 | /* 102011 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3159*/ GIMT_Encode4(102071), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3939 // |
| 37289 | /* 102018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37290 | /* 102022 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37291 | /* 102026 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37292 | /* 102030 */ // (usubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 37293 | /* 102030 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37294 | /* 102033 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37295 | /* 102037 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37296 | /* 102042 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu16), |
| 37297 | /* 102045 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37298 | /* 102047 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37299 | /* 102049 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37300 | /* 102051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37301 | /* 102054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37302 | /* 102060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37303 | /* 102066 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37304 | /* 102069 */ GIR_RootConstrainSelectedInstOperands, |
| 37305 | /* 102070 */ // GIR_Coverage, 3939, |
| 37306 | /* 102070 */ GIR_EraseRootFromParent_Done, |
| 37307 | /* 102071 */ // Label 3159: @102071 |
| 37308 | /* 102071 */ GIM_Reject, |
| 37309 | /* 102072 */ // Label 3157: @102072 |
| 37310 | /* 102072 */ GIM_Reject, |
| 37311 | /* 102073 */ // Label 3147: @102073 |
| 37312 | /* 102073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3160*/ GIMT_Encode4(102118), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1179 // |
| 37313 | /* 102080 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 37314 | /* 102083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37315 | /* 102086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37316 | /* 102090 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37317 | /* 102094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37318 | /* 102098 */ // (usubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37319 | /* 102098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i32), |
| 37320 | /* 102101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37321 | /* 102103 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37322 | /* 102105 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37323 | /* 102107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37324 | /* 102110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37325 | /* 102116 */ GIR_RootConstrainSelectedInstOperands, |
| 37326 | /* 102117 */ // GIR_Coverage, 1179, |
| 37327 | /* 102117 */ GIR_EraseRootFromParent_Done, |
| 37328 | /* 102118 */ // Label 3160: @102118 |
| 37329 | /* 102118 */ GIM_Reject, |
| 37330 | /* 102119 */ // Label 3148: @102119 |
| 37331 | /* 102119 */ GIM_Try, /*On fail goto*//*Label 3161*/ GIMT_Encode4(102230), |
| 37332 | /* 102124 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 37333 | /* 102127 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 37334 | /* 102130 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3162*/ GIMT_Encode4(102169), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1181 // |
| 37335 | /* 102137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37336 | /* 102141 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37337 | /* 102145 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37338 | /* 102149 */ // (usubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 37339 | /* 102149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i32), |
| 37340 | /* 102152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37341 | /* 102154 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37342 | /* 102156 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37343 | /* 102158 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37344 | /* 102161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37345 | /* 102167 */ GIR_RootConstrainSelectedInstOperands, |
| 37346 | /* 102168 */ // GIR_Coverage, 1181, |
| 37347 | /* 102168 */ GIR_EraseRootFromParent_Done, |
| 37348 | /* 102169 */ // Label 3162: @102169 |
| 37349 | /* 102169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3163*/ GIMT_Encode4(102229), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3942 // |
| 37350 | /* 102176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37351 | /* 102180 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37352 | /* 102184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37353 | /* 102188 */ // (usubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 37354 | /* 102188 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37355 | /* 102191 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37356 | /* 102195 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37357 | /* 102200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu32), |
| 37358 | /* 102203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37359 | /* 102205 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37360 | /* 102207 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37361 | /* 102209 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37362 | /* 102212 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37363 | /* 102218 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37364 | /* 102224 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37365 | /* 102227 */ GIR_RootConstrainSelectedInstOperands, |
| 37366 | /* 102228 */ // GIR_Coverage, 3942, |
| 37367 | /* 102228 */ GIR_EraseRootFromParent_Done, |
| 37368 | /* 102229 */ // Label 3163: @102229 |
| 37369 | /* 102229 */ GIM_Reject, |
| 37370 | /* 102230 */ // Label 3161: @102230 |
| 37371 | /* 102230 */ GIM_Reject, |
| 37372 | /* 102231 */ // Label 3149: @102231 |
| 37373 | /* 102231 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3164*/ GIMT_Encode4(102276), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1185 // |
| 37374 | /* 102238 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 37375 | /* 102241 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 37376 | /* 102244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37377 | /* 102248 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37378 | /* 102252 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37379 | /* 102256 */ // (usubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 37380 | /* 102256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i64), |
| 37381 | /* 102259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37382 | /* 102261 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37383 | /* 102263 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37384 | /* 102265 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37385 | /* 102268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37386 | /* 102274 */ GIR_RootConstrainSelectedInstOperands, |
| 37387 | /* 102275 */ // GIR_Coverage, 1185, |
| 37388 | /* 102275 */ GIR_EraseRootFromParent_Done, |
| 37389 | /* 102276 */ // Label 3164: @102276 |
| 37390 | /* 102276 */ GIM_Reject, |
| 37391 | /* 102277 */ // Label 3150: @102277 |
| 37392 | /* 102277 */ GIM_Reject, |
| 37393 | /* 102278 */ // Label 39: @102278 |
| 37394 | /* 102278 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 3174*/ GIMT_Encode4(103270), |
| 37395 | /* 102289 */ /*GILLT_s32*//*Label 3165*/ GIMT_Encode4(102341), |
| 37396 | /* 102293 */ /*GILLT_s64*//*Label 3166*/ GIMT_Encode4(102554), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 37397 | /* 102313 */ /*GILLT_v8s8*//*Label 3167*/ GIMT_Encode4(102600), |
| 37398 | /* 102317 */ /*GILLT_v16s8*//*Label 3168*/ GIMT_Encode4(102646), |
| 37399 | /* 102321 */ /*GILLT_v4s16*//*Label 3169*/ GIMT_Encode4(102758), |
| 37400 | /* 102325 */ /*GILLT_v8s16*//*Label 3170*/ GIMT_Encode4(102804), |
| 37401 | /* 102329 */ /*GILLT_v2s32*//*Label 3171*/ GIMT_Encode4(102916), |
| 37402 | /* 102333 */ /*GILLT_v4s32*//*Label 3172*/ GIMT_Encode4(102962), |
| 37403 | /* 102337 */ /*GILLT_v2s64*//*Label 3173*/ GIMT_Encode4(103149), |
| 37404 | /* 102341 */ // Label 3165: @102341 |
| 37405 | /* 102341 */ GIM_Try, /*On fail goto*//*Label 3175*/ GIMT_Encode4(102553), |
| 37406 | /* 102346 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 37407 | /* 102349 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 37408 | /* 102352 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3176*/ GIMT_Encode4(102413), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2059 // |
| 37409 | /* 102359 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 37410 | /* 102363 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37411 | /* 102367 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37412 | /* 102371 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 37413 | /* 102375 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37414 | /* 102379 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37415 | /* 102384 */ // MIs[1] Rn |
| 37416 | /* 102384 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 37417 | /* 102389 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37418 | /* 102391 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 37419 | /* 102391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB), |
| 37420 | /* 102394 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37421 | /* 102396 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 37422 | /* 102398 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 37423 | /* 102402 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37424 | /* 102405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37425 | /* 102411 */ GIR_RootConstrainSelectedInstOperands, |
| 37426 | /* 102412 */ // GIR_Coverage, 2059, |
| 37427 | /* 102412 */ GIR_EraseRootFromParent_Done, |
| 37428 | /* 102413 */ // Label 3176: @102413 |
| 37429 | /* 102413 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3177*/ GIMT_Encode4(102474), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2333 // |
| 37430 | /* 102420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37431 | /* 102424 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37432 | /* 102428 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37433 | /* 102432 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 37434 | /* 102436 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37435 | /* 102440 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37436 | /* 102445 */ // MIs[1] Rn |
| 37437 | /* 102445 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 37438 | /* 102450 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37439 | /* 102452 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 37440 | /* 102452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB), |
| 37441 | /* 102455 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37442 | /* 102457 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 37443 | /* 102459 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 37444 | /* 102463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37445 | /* 102466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37446 | /* 102472 */ GIR_RootConstrainSelectedInstOperands, |
| 37447 | /* 102473 */ // GIR_Coverage, 2333, |
| 37448 | /* 102473 */ GIR_EraseRootFromParent_Done, |
| 37449 | /* 102474 */ // Label 3177: @102474 |
| 37450 | /* 102474 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3178*/ GIMT_Encode4(102513), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2057 // |
| 37451 | /* 102481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 37452 | /* 102485 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37453 | /* 102489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37454 | /* 102493 */ // (ssubsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QSUB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 37455 | /* 102493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB), |
| 37456 | /* 102496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37457 | /* 102498 */ GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 37458 | /* 102500 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 37459 | /* 102502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37460 | /* 102505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37461 | /* 102511 */ GIR_RootConstrainSelectedInstOperands, |
| 37462 | /* 102512 */ // GIR_Coverage, 2057, |
| 37463 | /* 102512 */ GIR_EraseRootFromParent_Done, |
| 37464 | /* 102513 */ // Label 3178: @102513 |
| 37465 | /* 102513 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3179*/ GIMT_Encode4(102552), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2331 // |
| 37466 | /* 102520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37467 | /* 102524 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37468 | /* 102528 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37469 | /* 102532 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 37470 | /* 102532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB), |
| 37471 | /* 102535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37472 | /* 102537 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 37473 | /* 102539 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 37474 | /* 102541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37475 | /* 102544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37476 | /* 102550 */ GIR_RootConstrainSelectedInstOperands, |
| 37477 | /* 102551 */ // GIR_Coverage, 2331, |
| 37478 | /* 102551 */ GIR_EraseRootFromParent_Done, |
| 37479 | /* 102552 */ // Label 3179: @102552 |
| 37480 | /* 102552 */ GIM_Reject, |
| 37481 | /* 102553 */ // Label 3175: @102553 |
| 37482 | /* 102553 */ GIM_Reject, |
| 37483 | /* 102554 */ // Label 3166: @102554 |
| 37484 | /* 102554 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3180*/ GIMT_Encode4(102599), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1176 // |
| 37485 | /* 102561 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 37486 | /* 102564 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 37487 | /* 102567 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37488 | /* 102571 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37489 | /* 102575 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37490 | /* 102579 */ // (ssubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 37491 | /* 102579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv1i64), |
| 37492 | /* 102582 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37493 | /* 102584 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37494 | /* 102586 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37495 | /* 102588 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37496 | /* 102591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37497 | /* 102597 */ GIR_RootConstrainSelectedInstOperands, |
| 37498 | /* 102598 */ // GIR_Coverage, 1176, |
| 37499 | /* 102598 */ GIR_EraseRootFromParent_Done, |
| 37500 | /* 102599 */ // Label 3180: @102599 |
| 37501 | /* 102599 */ GIM_Reject, |
| 37502 | /* 102600 */ // Label 3167: @102600 |
| 37503 | /* 102600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3181*/ GIMT_Encode4(102645), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1174 // |
| 37504 | /* 102607 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 37505 | /* 102610 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 37506 | /* 102613 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37507 | /* 102617 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37508 | /* 102621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37509 | /* 102625 */ // (ssubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 37510 | /* 102625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i8), |
| 37511 | /* 102628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37512 | /* 102630 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37513 | /* 102632 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37514 | /* 102634 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37515 | /* 102637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37516 | /* 102643 */ GIR_RootConstrainSelectedInstOperands, |
| 37517 | /* 102644 */ // GIR_Coverage, 1174, |
| 37518 | /* 102644 */ GIR_EraseRootFromParent_Done, |
| 37519 | /* 102645 */ // Label 3181: @102645 |
| 37520 | /* 102645 */ GIM_Reject, |
| 37521 | /* 102646 */ // Label 3168: @102646 |
| 37522 | /* 102646 */ GIM_Try, /*On fail goto*//*Label 3182*/ GIMT_Encode4(102757), |
| 37523 | /* 102651 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 37524 | /* 102654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 37525 | /* 102657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3183*/ GIMT_Encode4(102696), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1175 // |
| 37526 | /* 102664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37527 | /* 102668 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37528 | /* 102672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37529 | /* 102676 */ // (ssubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 37530 | /* 102676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv16i8), |
| 37531 | /* 102679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37532 | /* 102681 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37533 | /* 102683 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37534 | /* 102685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37535 | /* 102688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37536 | /* 102694 */ GIR_RootConstrainSelectedInstOperands, |
| 37537 | /* 102695 */ // GIR_Coverage, 1175, |
| 37538 | /* 102695 */ GIR_EraseRootFromParent_Done, |
| 37539 | /* 102696 */ // Label 3183: @102696 |
| 37540 | /* 102696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3184*/ GIMT_Encode4(102756), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3927 // |
| 37541 | /* 102703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37542 | /* 102707 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37543 | /* 102711 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37544 | /* 102715 */ // (ssubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 37545 | /* 102715 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37546 | /* 102718 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37547 | /* 102722 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37548 | /* 102727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs8), |
| 37549 | /* 102730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37550 | /* 102732 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37551 | /* 102734 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37552 | /* 102736 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37553 | /* 102739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37554 | /* 102745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37555 | /* 102751 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37556 | /* 102754 */ GIR_RootConstrainSelectedInstOperands, |
| 37557 | /* 102755 */ // GIR_Coverage, 3927, |
| 37558 | /* 102755 */ GIR_EraseRootFromParent_Done, |
| 37559 | /* 102756 */ // Label 3184: @102756 |
| 37560 | /* 102756 */ GIM_Reject, |
| 37561 | /* 102757 */ // Label 3182: @102757 |
| 37562 | /* 102757 */ GIM_Reject, |
| 37563 | /* 102758 */ // Label 3169: @102758 |
| 37564 | /* 102758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3185*/ GIMT_Encode4(102803), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1170 // |
| 37565 | /* 102765 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 37566 | /* 102768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37567 | /* 102771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37568 | /* 102775 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37569 | /* 102779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37570 | /* 102783 */ // (ssubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37571 | /* 102783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i16), |
| 37572 | /* 102786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37573 | /* 102788 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37574 | /* 102790 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37575 | /* 102792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37576 | /* 102795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37577 | /* 102801 */ GIR_RootConstrainSelectedInstOperands, |
| 37578 | /* 102802 */ // GIR_Coverage, 1170, |
| 37579 | /* 102802 */ GIR_EraseRootFromParent_Done, |
| 37580 | /* 102803 */ // Label 3185: @102803 |
| 37581 | /* 102803 */ GIM_Reject, |
| 37582 | /* 102804 */ // Label 3170: @102804 |
| 37583 | /* 102804 */ GIM_Try, /*On fail goto*//*Label 3186*/ GIMT_Encode4(102915), |
| 37584 | /* 102809 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 37585 | /* 102812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 37586 | /* 102815 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3187*/ GIMT_Encode4(102854), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1172 // |
| 37587 | /* 102822 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37588 | /* 102826 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37589 | /* 102830 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37590 | /* 102834 */ // (ssubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 37591 | /* 102834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i16), |
| 37592 | /* 102837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37593 | /* 102839 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37594 | /* 102841 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37595 | /* 102843 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37596 | /* 102846 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37597 | /* 102852 */ GIR_RootConstrainSelectedInstOperands, |
| 37598 | /* 102853 */ // GIR_Coverage, 1172, |
| 37599 | /* 102853 */ GIR_EraseRootFromParent_Done, |
| 37600 | /* 102854 */ // Label 3187: @102854 |
| 37601 | /* 102854 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3188*/ GIMT_Encode4(102914), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3930 // |
| 37602 | /* 102861 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37603 | /* 102865 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37604 | /* 102869 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37605 | /* 102873 */ // (ssubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 37606 | /* 102873 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37607 | /* 102876 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37608 | /* 102880 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37609 | /* 102885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs16), |
| 37610 | /* 102888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37611 | /* 102890 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37612 | /* 102892 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37613 | /* 102894 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37614 | /* 102897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37615 | /* 102903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37616 | /* 102909 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37617 | /* 102912 */ GIR_RootConstrainSelectedInstOperands, |
| 37618 | /* 102913 */ // GIR_Coverage, 3930, |
| 37619 | /* 102913 */ GIR_EraseRootFromParent_Done, |
| 37620 | /* 102914 */ // Label 3188: @102914 |
| 37621 | /* 102914 */ GIM_Reject, |
| 37622 | /* 102915 */ // Label 3186: @102915 |
| 37623 | /* 102915 */ GIM_Reject, |
| 37624 | /* 102916 */ // Label 3171: @102916 |
| 37625 | /* 102916 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3189*/ GIMT_Encode4(102961), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1171 // |
| 37626 | /* 102923 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 37627 | /* 102926 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37628 | /* 102929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37629 | /* 102933 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37630 | /* 102937 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37631 | /* 102941 */ // (ssubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37632 | /* 102941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i32), |
| 37633 | /* 102944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37634 | /* 102946 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37635 | /* 102948 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37636 | /* 102950 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37637 | /* 102953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37638 | /* 102959 */ GIR_RootConstrainSelectedInstOperands, |
| 37639 | /* 102960 */ // GIR_Coverage, 1171, |
| 37640 | /* 102960 */ GIR_EraseRootFromParent_Done, |
| 37641 | /* 102961 */ // Label 3189: @102961 |
| 37642 | /* 102961 */ GIM_Reject, |
| 37643 | /* 102962 */ // Label 3172: @102962 |
| 37644 | /* 102962 */ GIM_Try, /*On fail goto*//*Label 3190*/ GIMT_Encode4(103148), |
| 37645 | /* 102967 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 37646 | /* 102970 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 37647 | /* 102973 */ GIM_Try, /*On fail goto*//*Label 3191*/ GIMT_Encode4(103087), |
| 37648 | /* 102978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37649 | /* 102982 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37650 | /* 102986 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3192*/ GIMT_Encode4(103055), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2882 // |
| 37651 | /* 102993 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37652 | /* 102997 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37653 | /* 103001 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37654 | /* 103004 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37655 | /* 103009 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37656 | /* 103013 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 37657 | /* 103017 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37658 | /* 103022 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37659 | /* 103027 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37660 | /* 103029 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 4044:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLSLv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37661 | /* 103029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv4i32), |
| 37662 | /* 103032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37663 | /* 103034 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37664 | /* 103036 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37665 | /* 103040 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37666 | /* 103044 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37667 | /* 103047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37668 | /* 103053 */ GIR_RootConstrainSelectedInstOperands, |
| 37669 | /* 103054 */ // GIR_Coverage, 2882, |
| 37670 | /* 103054 */ GIR_EraseRootFromParent_Done, |
| 37671 | /* 103055 */ // Label 3192: @103055 |
| 37672 | /* 103055 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3193*/ GIMT_Encode4(103086), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1173 // |
| 37673 | /* 103062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37674 | /* 103066 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 37675 | /* 103066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i32), |
| 37676 | /* 103069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37677 | /* 103071 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37678 | /* 103073 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37679 | /* 103075 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37680 | /* 103078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37681 | /* 103084 */ GIR_RootConstrainSelectedInstOperands, |
| 37682 | /* 103085 */ // GIR_Coverage, 1173, |
| 37683 | /* 103085 */ GIR_EraseRootFromParent_Done, |
| 37684 | /* 103086 */ // Label 3193: @103086 |
| 37685 | /* 103086 */ GIM_Reject, |
| 37686 | /* 103087 */ // Label 3191: @103087 |
| 37687 | /* 103087 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3194*/ GIMT_Encode4(103147), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3933 // |
| 37688 | /* 103094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37689 | /* 103098 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37690 | /* 103102 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37691 | /* 103106 */ // (ssubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 37692 | /* 103106 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37693 | /* 103109 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37694 | /* 103113 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37695 | /* 103118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs32), |
| 37696 | /* 103121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37697 | /* 103123 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37698 | /* 103125 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37699 | /* 103127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37700 | /* 103130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37701 | /* 103136 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37702 | /* 103142 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37703 | /* 103145 */ GIR_RootConstrainSelectedInstOperands, |
| 37704 | /* 103146 */ // GIR_Coverage, 3933, |
| 37705 | /* 103146 */ GIR_EraseRootFromParent_Done, |
| 37706 | /* 103147 */ // Label 3194: @103147 |
| 37707 | /* 103147 */ GIM_Reject, |
| 37708 | /* 103148 */ // Label 3190: @103148 |
| 37709 | /* 103148 */ GIM_Reject, |
| 37710 | /* 103149 */ // Label 3173: @103149 |
| 37711 | /* 103149 */ GIM_Try, /*On fail goto*//*Label 3195*/ GIMT_Encode4(103269), |
| 37712 | /* 103154 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 37713 | /* 103157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 37714 | /* 103160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37715 | /* 103164 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37716 | /* 103168 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3196*/ GIMT_Encode4(103237), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2883 // |
| 37717 | /* 103175 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37718 | /* 103179 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37719 | /* 103183 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37720 | /* 103186 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37721 | /* 103191 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37722 | /* 103195 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 37723 | /* 103199 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37724 | /* 103204 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37725 | /* 103209 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37726 | /* 103211 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 4044:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLSLv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37727 | /* 103211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv2i64), |
| 37728 | /* 103214 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37729 | /* 103216 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37730 | /* 103218 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37731 | /* 103222 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37732 | /* 103226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37733 | /* 103229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37734 | /* 103235 */ GIR_RootConstrainSelectedInstOperands, |
| 37735 | /* 103236 */ // GIR_Coverage, 2883, |
| 37736 | /* 103236 */ GIR_EraseRootFromParent_Done, |
| 37737 | /* 103237 */ // Label 3196: @103237 |
| 37738 | /* 103237 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3197*/ GIMT_Encode4(103268), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1177 // |
| 37739 | /* 103244 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37740 | /* 103248 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 37741 | /* 103248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i64), |
| 37742 | /* 103251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37743 | /* 103253 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37744 | /* 103255 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37745 | /* 103257 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37746 | /* 103260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37747 | /* 103266 */ GIR_RootConstrainSelectedInstOperands, |
| 37748 | /* 103267 */ // GIR_Coverage, 1177, |
| 37749 | /* 103267 */ GIR_EraseRootFromParent_Done, |
| 37750 | /* 103268 */ // Label 3197: @103268 |
| 37751 | /* 103268 */ GIM_Reject, |
| 37752 | /* 103269 */ // Label 3195: @103269 |
| 37753 | /* 103269 */ GIM_Reject, |
| 37754 | /* 103270 */ // Label 3174: @103270 |
| 37755 | /* 103270 */ GIM_Reject, |
| 37756 | /* 103271 */ // Label 40: @103271 |
| 37757 | /* 103271 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3205*/ GIMT_Encode4(106075), |
| 37758 | /* 103282 */ /*GILLT_s16*//*Label 3198*/ GIMT_Encode4(103334), |
| 37759 | /* 103286 */ /*GILLT_s32*//*Label 3199*/ GIMT_Encode4(103380), |
| 37760 | /* 103290 */ /*GILLT_s64*//*Label 3200*/ GIMT_Encode4(104997), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 37761 | /* 103318 */ /*GILLT_v4s16*//*Label 3201*/ GIMT_Encode4(105043), |
| 37762 | /* 103322 */ /*GILLT_v8s16*//*Label 3202*/ GIMT_Encode4(105247), |
| 37763 | /* 103326 */ /*GILLT_v2s32*//*Label 3203*/ GIMT_Encode4(105715), |
| 37764 | /* 103330 */ /*GILLT_v4s32*//*Label 3204*/ GIMT_Encode4(105761), |
| 37765 | /* 103334 */ // Label 3198: @103334 |
| 37766 | /* 103334 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3206*/ GIMT_Encode4(103379), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 621 // |
| 37767 | /* 103341 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 37768 | /* 103344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 37769 | /* 103347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 37770 | /* 103351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 37771 | /* 103355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 37772 | /* 103359 */ // (fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 37773 | /* 103359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH), |
| 37774 | /* 103362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 37775 | /* 103364 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 37776 | /* 103366 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 37777 | /* 103368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37778 | /* 103371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37779 | /* 103377 */ GIR_RootConstrainSelectedInstOperands, |
| 37780 | /* 103378 */ // GIR_Coverage, 621, |
| 37781 | /* 103378 */ GIR_EraseRootFromParent_Done, |
| 37782 | /* 103379 */ // Label 3206: @103379 |
| 37783 | /* 103379 */ GIM_Reject, |
| 37784 | /* 103380 */ // Label 3199: @103380 |
| 37785 | /* 103380 */ GIM_Try, /*On fail goto*//*Label 3207*/ GIMT_Encode4(104996), |
| 37786 | /* 103385 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 37787 | /* 103388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 37788 | /* 103391 */ GIM_Try, /*On fail goto*//*Label 3208*/ GIMT_Encode4(104067), |
| 37789 | /* 103396 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fadd_contract), |
| 37790 | /* 103400 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37791 | /* 103404 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3209*/ GIMT_Encode4(103735), GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), // Rule ID 6558 // |
| 37792 | /* 103411 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 37793 | /* 103415 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 37794 | /* 103419 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37795 | /* 103423 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 37796 | /* 103427 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37797 | /* 103432 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37798 | /* 103437 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract), |
| 37799 | /* 103441 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37800 | /* 103445 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37801 | /* 103447 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)<<P:Predicate_fmul_contract>>, SPR:{ *:[f32] }:$acc)<<P:Predicate_fadd_contract>> => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 37802 | /* 103447 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 37803 | /* 103450 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37804 | /* 103454 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37805 | /* 103459 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 37806 | /* 103461 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 37807 | /* 103464 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37808 | /* 103468 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37809 | /* 103473 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 37810 | /* 103476 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37811 | /* 103481 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 37812 | /* 103484 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37813 | /* 103488 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37814 | /* 103493 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 37815 | /* 103496 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 37816 | /* 103500 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 37817 | /* 103503 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37818 | /* 103508 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37819 | /* 103513 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37820 | /* 103518 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 37821 | /* 103521 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37822 | /* 103525 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37823 | /* 103530 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 37824 | /* 103532 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 37825 | /* 103535 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37826 | /* 103539 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37827 | /* 103544 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 37828 | /* 103547 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37829 | /* 103552 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 37830 | /* 103555 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37831 | /* 103559 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37832 | /* 103564 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 37833 | /* 103567 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 37834 | /* 103571 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 37835 | /* 103574 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37836 | /* 103579 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37837 | /* 103584 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37838 | /* 103589 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 37839 | /* 103592 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37840 | /* 103596 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37841 | /* 103601 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 37842 | /* 103603 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 37843 | /* 103606 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37844 | /* 103610 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37845 | /* 103615 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 37846 | /* 103618 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37847 | /* 103623 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 37848 | /* 103626 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37849 | /* 103630 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37850 | /* 103635 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 37851 | /* 103638 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc |
| 37852 | /* 103642 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 37853 | /* 103645 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37854 | /* 103650 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37855 | /* 103655 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37856 | /* 103660 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 37857 | /* 103663 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd), |
| 37858 | /* 103667 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37859 | /* 103672 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 37860 | /* 103675 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 37861 | /* 103678 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 37862 | /* 103681 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 37863 | /* 103684 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37864 | /* 103690 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37865 | /* 103692 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 37866 | /* 103695 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37867 | /* 103699 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37868 | /* 103704 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 37869 | /* 103707 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37870 | /* 103712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37871 | /* 103715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 37872 | /* 103717 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 37873 | /* 103724 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 37874 | /* 103729 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37875 | /* 103734 */ // GIR_Coverage, 6558, |
| 37876 | /* 103734 */ GIR_EraseRootFromParent_Done, |
| 37877 | /* 103735 */ // Label 3209: @103735 |
| 37878 | /* 103735 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3210*/ GIMT_Encode4(104066), GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), // Rule ID 3091 // |
| 37879 | /* 103742 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37880 | /* 103746 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37881 | /* 103750 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 37882 | /* 103754 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37883 | /* 103758 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 37884 | /* 103762 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37885 | /* 103767 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37886 | /* 103772 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract), |
| 37887 | /* 103776 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37888 | /* 103778 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)<<P:Predicate_fmul_contract>>)<<P:Predicate_fadd_contract>> => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 37889 | /* 103778 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 37890 | /* 103781 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37891 | /* 103785 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37892 | /* 103790 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 37893 | /* 103792 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 37894 | /* 103795 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37895 | /* 103799 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37896 | /* 103804 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 37897 | /* 103807 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37898 | /* 103812 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 37899 | /* 103815 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37900 | /* 103819 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37901 | /* 103824 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 37902 | /* 103827 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 37903 | /* 103831 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 37904 | /* 103834 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37905 | /* 103839 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37906 | /* 103844 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37907 | /* 103849 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 37908 | /* 103852 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37909 | /* 103856 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37910 | /* 103861 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 37911 | /* 103863 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 37912 | /* 103866 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37913 | /* 103870 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37914 | /* 103875 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 37915 | /* 103878 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37916 | /* 103883 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 37917 | /* 103886 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37918 | /* 103890 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37919 | /* 103895 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 37920 | /* 103898 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 37921 | /* 103902 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 37922 | /* 103905 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37923 | /* 103910 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37924 | /* 103915 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37925 | /* 103920 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 37926 | /* 103923 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37927 | /* 103927 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37928 | /* 103932 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 37929 | /* 103934 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 37930 | /* 103937 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37931 | /* 103941 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37932 | /* 103946 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 37933 | /* 103949 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37934 | /* 103954 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 37935 | /* 103957 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37936 | /* 103961 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37937 | /* 103966 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 37938 | /* 103969 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 37939 | /* 103973 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 37940 | /* 103976 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37941 | /* 103981 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37942 | /* 103986 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37943 | /* 103991 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 37944 | /* 103994 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd), |
| 37945 | /* 103998 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37946 | /* 104003 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 37947 | /* 104006 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 37948 | /* 104009 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 37949 | /* 104012 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 37950 | /* 104015 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37951 | /* 104021 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37952 | /* 104023 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 37953 | /* 104026 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37954 | /* 104030 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37955 | /* 104035 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 37956 | /* 104038 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37957 | /* 104043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37958 | /* 104046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 37959 | /* 104048 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 37960 | /* 104055 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 37961 | /* 104060 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37962 | /* 104065 */ // GIR_Coverage, 3091, |
| 37963 | /* 104065 */ GIR_EraseRootFromParent_Done, |
| 37964 | /* 104066 */ // Label 3210: @104066 |
| 37965 | /* 104066 */ GIM_Reject, |
| 37966 | /* 104067 */ // Label 3208: @104067 |
| 37967 | /* 104067 */ GIM_Try, /*On fail goto*//*Label 3211*/ GIMT_Encode4(104995), |
| 37968 | /* 104072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37969 | /* 104076 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3212*/ GIMT_Encode4(104403), GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), // Rule ID 6557 // |
| 37970 | /* 104083 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 37971 | /* 104087 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 37972 | /* 104091 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37973 | /* 104095 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 37974 | /* 104099 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37975 | /* 104104 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37976 | /* 104109 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37977 | /* 104113 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37978 | /* 104115 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 37979 | /* 104115 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 37980 | /* 104118 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37981 | /* 104122 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37982 | /* 104127 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 37983 | /* 104129 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 37984 | /* 104132 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37985 | /* 104136 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37986 | /* 104141 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 37987 | /* 104144 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37988 | /* 104149 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 37989 | /* 104152 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37990 | /* 104156 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37991 | /* 104161 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 37992 | /* 104164 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 37993 | /* 104168 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 37994 | /* 104171 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37995 | /* 104176 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37996 | /* 104181 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37997 | /* 104186 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 37998 | /* 104189 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37999 | /* 104193 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38000 | /* 104198 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38001 | /* 104200 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38002 | /* 104203 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38003 | /* 104207 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38004 | /* 104212 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38005 | /* 104215 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38006 | /* 104220 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38007 | /* 104223 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38008 | /* 104227 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38009 | /* 104232 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38010 | /* 104235 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38011 | /* 104239 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38012 | /* 104242 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38013 | /* 104247 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38014 | /* 104252 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38015 | /* 104257 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38016 | /* 104260 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38017 | /* 104264 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38018 | /* 104269 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38019 | /* 104271 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38020 | /* 104274 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38021 | /* 104278 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38022 | /* 104283 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38023 | /* 104286 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38024 | /* 104291 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38025 | /* 104294 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38026 | /* 104298 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38027 | /* 104303 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38028 | /* 104306 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc |
| 38029 | /* 104310 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38030 | /* 104313 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38031 | /* 104318 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38032 | /* 104323 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38033 | /* 104328 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38034 | /* 104331 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd), |
| 38035 | /* 104335 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38036 | /* 104340 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38037 | /* 104343 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38038 | /* 104346 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38039 | /* 104349 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38040 | /* 104352 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38041 | /* 104358 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38042 | /* 104360 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38043 | /* 104363 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38044 | /* 104367 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38045 | /* 104372 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38046 | /* 104375 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38047 | /* 104380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38048 | /* 104383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38049 | /* 104385 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38050 | /* 104392 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38051 | /* 104397 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38052 | /* 104402 */ // GIR_Coverage, 6557, |
| 38053 | /* 104402 */ GIR_EraseRootFromParent_Done, |
| 38054 | /* 104403 */ // Label 3212: @104403 |
| 38055 | /* 104403 */ GIM_Try, /*On fail goto*//*Label 3213*/ GIMT_Encode4(104994), |
| 38056 | /* 104408 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38057 | /* 104412 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3214*/ GIMT_Encode4(104735), GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), // Rule ID 3089 // |
| 38058 | /* 104419 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38059 | /* 104423 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38060 | /* 104427 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38061 | /* 104431 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38062 | /* 104435 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38063 | /* 104440 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38064 | /* 104445 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38065 | /* 104447 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38066 | /* 104447 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 38067 | /* 104450 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38068 | /* 104454 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38069 | /* 104459 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 38070 | /* 104461 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 38071 | /* 104464 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38072 | /* 104468 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38073 | /* 104473 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 38074 | /* 104476 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38075 | /* 104481 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 38076 | /* 104484 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38077 | /* 104488 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38078 | /* 104493 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 38079 | /* 104496 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 38080 | /* 104500 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 38081 | /* 104503 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38082 | /* 104508 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38083 | /* 104513 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38084 | /* 104518 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38085 | /* 104521 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38086 | /* 104525 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38087 | /* 104530 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38088 | /* 104532 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38089 | /* 104535 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38090 | /* 104539 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38091 | /* 104544 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38092 | /* 104547 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38093 | /* 104552 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38094 | /* 104555 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38095 | /* 104559 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38096 | /* 104564 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38097 | /* 104567 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38098 | /* 104571 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38099 | /* 104574 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38100 | /* 104579 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38101 | /* 104584 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38102 | /* 104589 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38103 | /* 104592 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38104 | /* 104596 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38105 | /* 104601 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38106 | /* 104603 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38107 | /* 104606 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38108 | /* 104610 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38109 | /* 104615 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38110 | /* 104618 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38111 | /* 104623 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38112 | /* 104626 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38113 | /* 104630 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38114 | /* 104635 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38115 | /* 104638 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 38116 | /* 104642 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38117 | /* 104645 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38118 | /* 104650 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38119 | /* 104655 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38120 | /* 104660 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38121 | /* 104663 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd), |
| 38122 | /* 104667 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38123 | /* 104672 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38124 | /* 104675 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38125 | /* 104678 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38126 | /* 104681 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38127 | /* 104684 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38128 | /* 104690 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38129 | /* 104692 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38130 | /* 104695 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38131 | /* 104699 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38132 | /* 104704 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38133 | /* 104707 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38134 | /* 104712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38135 | /* 104715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38136 | /* 104717 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38137 | /* 104724 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38138 | /* 104729 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38139 | /* 104734 */ // GIR_Coverage, 3089, |
| 38140 | /* 104734 */ GIR_EraseRootFromParent_Done, |
| 38141 | /* 104735 */ // Label 3214: @104735 |
| 38142 | /* 104735 */ GIM_Try, /*On fail goto*//*Label 3215*/ GIMT_Encode4(104993), |
| 38143 | /* 104740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38144 | /* 104744 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3216*/ GIMT_Encode4(104771), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 619 // |
| 38145 | /* 104751 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 38146 | /* 104751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS), |
| 38147 | /* 104754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38148 | /* 104756 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38149 | /* 104758 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38150 | /* 104760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38151 | /* 104763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38152 | /* 104769 */ GIR_RootConstrainSelectedInstOperands, |
| 38153 | /* 104770 */ // GIR_Coverage, 619, |
| 38154 | /* 104770 */ GIR_EraseRootFromParent_Done, |
| 38155 | /* 104771 */ // Label 3216: @104771 |
| 38156 | /* 104771 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3217*/ GIMT_Encode4(104992), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3086 // |
| 38157 | /* 104778 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VADDfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38158 | /* 104778 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38159 | /* 104781 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38160 | /* 104785 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38161 | /* 104790 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38162 | /* 104792 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38163 | /* 104795 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38164 | /* 104799 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38165 | /* 104804 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38166 | /* 104807 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38167 | /* 104812 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38168 | /* 104815 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38169 | /* 104819 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38170 | /* 104824 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38171 | /* 104827 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 38172 | /* 104831 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38173 | /* 104834 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38174 | /* 104839 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38175 | /* 104844 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38176 | /* 104849 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38177 | /* 104852 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38178 | /* 104856 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38179 | /* 104861 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38180 | /* 104863 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38181 | /* 104866 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38182 | /* 104870 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38183 | /* 104875 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38184 | /* 104878 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38185 | /* 104883 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38186 | /* 104886 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38187 | /* 104890 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38188 | /* 104895 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38189 | /* 104898 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 38190 | /* 104902 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38191 | /* 104905 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38192 | /* 104910 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38193 | /* 104915 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38194 | /* 104920 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38195 | /* 104923 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VADDfd), |
| 38196 | /* 104927 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38197 | /* 104932 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38198 | /* 104935 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38199 | /* 104938 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38200 | /* 104941 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38201 | /* 104947 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38202 | /* 104949 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38203 | /* 104952 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38204 | /* 104956 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38205 | /* 104961 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38206 | /* 104964 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38207 | /* 104969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38208 | /* 104972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38209 | /* 104974 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38210 | /* 104981 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38211 | /* 104986 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38212 | /* 104991 */ // GIR_Coverage, 3086, |
| 38213 | /* 104991 */ GIR_EraseRootFromParent_Done, |
| 38214 | /* 104992 */ // Label 3217: @104992 |
| 38215 | /* 104992 */ GIM_Reject, |
| 38216 | /* 104993 */ // Label 3215: @104993 |
| 38217 | /* 104993 */ GIM_Reject, |
| 38218 | /* 104994 */ // Label 3213: @104994 |
| 38219 | /* 104994 */ GIM_Reject, |
| 38220 | /* 104995 */ // Label 3211: @104995 |
| 38221 | /* 104995 */ GIM_Reject, |
| 38222 | /* 104996 */ // Label 3207: @104996 |
| 38223 | /* 104996 */ GIM_Reject, |
| 38224 | /* 104997 */ // Label 3200: @104997 |
| 38225 | /* 104997 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3218*/ GIMT_Encode4(105042), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 617 // |
| 38226 | /* 105004 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 38227 | /* 105007 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 38228 | /* 105010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38229 | /* 105014 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38230 | /* 105018 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38231 | /* 105022 */ // (fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 38232 | /* 105022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD), |
| 38233 | /* 105025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 38234 | /* 105027 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 38235 | /* 105029 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 38236 | /* 105031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38237 | /* 105034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38238 | /* 105040 */ GIR_RootConstrainSelectedInstOperands, |
| 38239 | /* 105041 */ // GIR_Coverage, 617, |
| 38240 | /* 105041 */ GIR_EraseRootFromParent_Done, |
| 38241 | /* 105042 */ // Label 3218: @105042 |
| 38242 | /* 105042 */ GIM_Reject, |
| 38243 | /* 105043 */ // Label 3201: @105043 |
| 38244 | /* 105043 */ GIM_Try, /*On fail goto*//*Label 3219*/ GIMT_Encode4(105246), |
| 38245 | /* 105048 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38246 | /* 105051 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38247 | /* 105054 */ GIM_Try, /*On fail goto*//*Label 3220*/ GIMT_Encode4(105206), |
| 38248 | /* 105059 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fadd_contract), |
| 38249 | /* 105063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38250 | /* 105067 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3221*/ GIMT_Encode4(105136), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 6184 // |
| 38251 | /* 105074 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38252 | /* 105078 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38253 | /* 105082 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38254 | /* 105086 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38255 | /* 105090 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38256 | /* 105095 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38257 | /* 105100 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract), |
| 38258 | /* 105104 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38259 | /* 105108 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38260 | /* 105110 */ // (fadd:{ *:[v4f16] } (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)<<P:Predicate_fmul_contract>>, DPR:{ *:[v4f16] }:$src1)<<P:Predicate_fadd_contract>> => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38261 | /* 105110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd), |
| 38262 | /* 105113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38263 | /* 105115 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 38264 | /* 105117 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38265 | /* 105121 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38266 | /* 105125 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38267 | /* 105128 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38268 | /* 105134 */ GIR_RootConstrainSelectedInstOperands, |
| 38269 | /* 105135 */ // GIR_Coverage, 6184, |
| 38270 | /* 105135 */ GIR_EraseRootFromParent_Done, |
| 38271 | /* 105136 */ // Label 3221: @105136 |
| 38272 | /* 105136 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3222*/ GIMT_Encode4(105205), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1101 // |
| 38273 | /* 105143 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38274 | /* 105147 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38275 | /* 105151 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38276 | /* 105155 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38277 | /* 105159 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38278 | /* 105163 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38279 | /* 105168 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38280 | /* 105173 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract), |
| 38281 | /* 105177 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38282 | /* 105179 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)<<P:Predicate_fmul_contract>>)<<P:Predicate_fadd_contract>> => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38283 | /* 105179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd), |
| 38284 | /* 105182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38285 | /* 105184 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38286 | /* 105186 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38287 | /* 105190 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38288 | /* 105194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38289 | /* 105197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38290 | /* 105203 */ GIR_RootConstrainSelectedInstOperands, |
| 38291 | /* 105204 */ // GIR_Coverage, 1101, |
| 38292 | /* 105204 */ GIR_EraseRootFromParent_Done, |
| 38293 | /* 105205 */ // Label 3222: @105205 |
| 38294 | /* 105205 */ GIM_Reject, |
| 38295 | /* 105206 */ // Label 3220: @105206 |
| 38296 | /* 105206 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3223*/ GIMT_Encode4(105245), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 886 // |
| 38297 | /* 105213 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38298 | /* 105217 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38299 | /* 105221 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38300 | /* 105225 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VADDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38301 | /* 105225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhd), |
| 38302 | /* 105228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38303 | /* 105230 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38304 | /* 105232 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38305 | /* 105234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38306 | /* 105237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38307 | /* 105243 */ GIR_RootConstrainSelectedInstOperands, |
| 38308 | /* 105244 */ // GIR_Coverage, 886, |
| 38309 | /* 105244 */ GIR_EraseRootFromParent_Done, |
| 38310 | /* 105245 */ // Label 3223: @105245 |
| 38311 | /* 105245 */ GIM_Reject, |
| 38312 | /* 105246 */ // Label 3219: @105246 |
| 38313 | /* 105246 */ GIM_Reject, |
| 38314 | /* 105247 */ // Label 3202: @105247 |
| 38315 | /* 105247 */ GIM_Try, /*On fail goto*//*Label 3224*/ GIMT_Encode4(105714), |
| 38316 | /* 105252 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38317 | /* 105255 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38318 | /* 105258 */ GIM_Try, /*On fail goto*//*Label 3225*/ GIMT_Encode4(105614), |
| 38319 | /* 105263 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fadd_contract), |
| 38320 | /* 105267 */ GIM_Try, /*On fail goto*//*Label 3226*/ GIMT_Encode4(105465), |
| 38321 | /* 105272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38322 | /* 105276 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3227*/ GIMT_Encode4(105370), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 6672 // |
| 38323 | /* 105283 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38324 | /* 105287 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 38325 | /* 105291 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/5, |
| 38326 | /* 105294 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq), |
| 38327 | /* 105299 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38328 | /* 105303 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, |
| 38329 | /* 105307 */ GIM_CheckType, /*MI*/1, /*Op*/4, /*Type*/GILLT_v8s16, |
| 38330 | /* 105311 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 38331 | /* 105315 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 38332 | /* 105319 */ // MIs[2] Operand 1 |
| 38333 | /* 105319 */ // No operand predicates |
| 38334 | /* 105319 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38335 | /* 105324 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38336 | /* 105329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38337 | /* 105333 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 38338 | /* 105335 */ // (fadd:{ *:[v8f16] } (intrinsic_wo_chain:{ *:[v8f16] } 3833:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm), MQPR:{ *:[v8f16] }:$Qd_src)<<P:Predicate_fadd_contract>> => (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 38339 | /* 105335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf16), |
| 38340 | /* 105338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38341 | /* 105340 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 38342 | /* 105342 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Qn |
| 38343 | /* 105346 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/4, // Qm |
| 38344 | /* 105350 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // rot |
| 38345 | /* 105353 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38346 | /* 105356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38347 | /* 105362 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38348 | /* 105368 */ GIR_RootConstrainSelectedInstOperands, |
| 38349 | /* 105369 */ // GIR_Coverage, 6672, |
| 38350 | /* 105369 */ GIR_EraseRootFromParent_Done, |
| 38351 | /* 105370 */ // Label 3227: @105370 |
| 38352 | /* 105370 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3228*/ GIMT_Encode4(105464), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4430 // |
| 38353 | /* 105377 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38354 | /* 105381 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38355 | /* 105385 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 38356 | /* 105389 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/5, |
| 38357 | /* 105392 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq), |
| 38358 | /* 105397 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38359 | /* 105401 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v8s16, |
| 38360 | /* 105405 */ GIM_CheckType, /*MI*/1, /*Op*/4, /*Type*/GILLT_v8s16, |
| 38361 | /* 105409 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 38362 | /* 105413 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 38363 | /* 105417 */ // MIs[2] Operand 1 |
| 38364 | /* 105417 */ // No operand predicates |
| 38365 | /* 105417 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38366 | /* 105422 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38367 | /* 105427 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 38368 | /* 105429 */ // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, (intrinsic_wo_chain:{ *:[v8f16] } 3833:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm))<<P:Predicate_fadd_contract>> => (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 38369 | /* 105429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf16), |
| 38370 | /* 105432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38371 | /* 105434 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd_src |
| 38372 | /* 105436 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Qn |
| 38373 | /* 105440 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/4, // Qm |
| 38374 | /* 105444 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // rot |
| 38375 | /* 105447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38376 | /* 105450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38377 | /* 105456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38378 | /* 105462 */ GIR_RootConstrainSelectedInstOperands, |
| 38379 | /* 105463 */ // GIR_Coverage, 4430, |
| 38380 | /* 105463 */ GIR_EraseRootFromParent_Done, |
| 38381 | /* 105464 */ // Label 3228: @105464 |
| 38382 | /* 105464 */ GIM_Reject, |
| 38383 | /* 105465 */ // Label 3226: @105465 |
| 38384 | /* 105465 */ GIM_Try, /*On fail goto*//*Label 3229*/ GIMT_Encode4(105613), |
| 38385 | /* 105470 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38386 | /* 105474 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3230*/ GIMT_Encode4(105543), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 6185 // |
| 38387 | /* 105481 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38388 | /* 105485 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38389 | /* 105489 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38390 | /* 105493 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38391 | /* 105497 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38392 | /* 105502 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38393 | /* 105507 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract), |
| 38394 | /* 105511 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38395 | /* 105515 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38396 | /* 105517 */ // (fadd:{ *:[v8f16] } (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)<<P:Predicate_fmul_contract>>, QPR:{ *:[v8f16] }:$src1)<<P:Predicate_fadd_contract>> => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38397 | /* 105517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq), |
| 38398 | /* 105520 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38399 | /* 105522 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 38400 | /* 105524 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38401 | /* 105528 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38402 | /* 105532 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38403 | /* 105535 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38404 | /* 105541 */ GIR_RootConstrainSelectedInstOperands, |
| 38405 | /* 105542 */ // GIR_Coverage, 6185, |
| 38406 | /* 105542 */ GIR_EraseRootFromParent_Done, |
| 38407 | /* 105543 */ // Label 3230: @105543 |
| 38408 | /* 105543 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3231*/ GIMT_Encode4(105612), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1102 // |
| 38409 | /* 105550 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38410 | /* 105554 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38411 | /* 105558 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38412 | /* 105562 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38413 | /* 105566 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38414 | /* 105570 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38415 | /* 105575 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38416 | /* 105580 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract), |
| 38417 | /* 105584 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38418 | /* 105586 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)<<P:Predicate_fmul_contract>>)<<P:Predicate_fadd_contract>> => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38419 | /* 105586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq), |
| 38420 | /* 105589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38421 | /* 105591 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38422 | /* 105593 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38423 | /* 105597 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38424 | /* 105601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38425 | /* 105604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38426 | /* 105610 */ GIR_RootConstrainSelectedInstOperands, |
| 38427 | /* 105611 */ // GIR_Coverage, 1102, |
| 38428 | /* 105611 */ GIR_EraseRootFromParent_Done, |
| 38429 | /* 105612 */ // Label 3231: @105612 |
| 38430 | /* 105612 */ GIM_Reject, |
| 38431 | /* 105613 */ // Label 3229: @105613 |
| 38432 | /* 105613 */ GIM_Reject, |
| 38433 | /* 105614 */ // Label 3225: @105614 |
| 38434 | /* 105614 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3232*/ GIMT_Encode4(105653), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 887 // |
| 38435 | /* 105621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38436 | /* 105625 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38437 | /* 105629 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38438 | /* 105633 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VADDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38439 | /* 105633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhq), |
| 38440 | /* 105636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38441 | /* 105638 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38442 | /* 105640 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38443 | /* 105642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38444 | /* 105645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38445 | /* 105651 */ GIR_RootConstrainSelectedInstOperands, |
| 38446 | /* 105652 */ // GIR_Coverage, 887, |
| 38447 | /* 105652 */ GIR_EraseRootFromParent_Done, |
| 38448 | /* 105653 */ // Label 3232: @105653 |
| 38449 | /* 105653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3233*/ GIMT_Encode4(105713), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4462 // |
| 38450 | /* 105660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38451 | /* 105664 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38452 | /* 105668 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38453 | /* 105672 */ // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 38454 | /* 105672 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38455 | /* 105675 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38456 | /* 105679 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38457 | /* 105684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16), |
| 38458 | /* 105687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38459 | /* 105689 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 38460 | /* 105691 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 38461 | /* 105693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38462 | /* 105696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38463 | /* 105702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38464 | /* 105708 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38465 | /* 105711 */ GIR_RootConstrainSelectedInstOperands, |
| 38466 | /* 105712 */ // GIR_Coverage, 4462, |
| 38467 | /* 105712 */ GIR_EraseRootFromParent_Done, |
| 38468 | /* 105713 */ // Label 3233: @105713 |
| 38469 | /* 105713 */ GIM_Reject, |
| 38470 | /* 105714 */ // Label 3224: @105714 |
| 38471 | /* 105714 */ GIM_Reject, |
| 38472 | /* 105715 */ // Label 3203: @105715 |
| 38473 | /* 105715 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3234*/ GIMT_Encode4(105760), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 884 // |
| 38474 | /* 105722 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 38475 | /* 105725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38476 | /* 105728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38477 | /* 105732 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38478 | /* 105736 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38479 | /* 105740 */ // (fadd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VADDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 38480 | /* 105740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfd), |
| 38481 | /* 105743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38482 | /* 105745 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38483 | /* 105747 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38484 | /* 105749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38485 | /* 105752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38486 | /* 105758 */ GIR_RootConstrainSelectedInstOperands, |
| 38487 | /* 105759 */ // GIR_Coverage, 884, |
| 38488 | /* 105759 */ GIR_EraseRootFromParent_Done, |
| 38489 | /* 105760 */ // Label 3234: @105760 |
| 38490 | /* 105760 */ GIM_Reject, |
| 38491 | /* 105761 */ // Label 3204: @105761 |
| 38492 | /* 105761 */ GIM_Try, /*On fail goto*//*Label 3235*/ GIMT_Encode4(106074), |
| 38493 | /* 105766 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38494 | /* 105769 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38495 | /* 105772 */ GIM_Try, /*On fail goto*//*Label 3236*/ GIMT_Encode4(105974), |
| 38496 | /* 105777 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fadd_contract), |
| 38497 | /* 105781 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38498 | /* 105785 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3237*/ GIMT_Encode4(105879), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 6673 // |
| 38499 | /* 105792 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38500 | /* 105796 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 38501 | /* 105800 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/5, |
| 38502 | /* 105803 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq), |
| 38503 | /* 105808 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38504 | /* 105812 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 38505 | /* 105816 */ GIM_CheckType, /*MI*/1, /*Op*/4, /*Type*/GILLT_v4s32, |
| 38506 | /* 105820 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 38507 | /* 105824 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 38508 | /* 105828 */ // MIs[2] Operand 1 |
| 38509 | /* 105828 */ // No operand predicates |
| 38510 | /* 105828 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38511 | /* 105833 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38512 | /* 105838 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38513 | /* 105842 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 38514 | /* 105844 */ // (fadd:{ *:[v4f32] } (intrinsic_wo_chain:{ *:[v4f32] } 3833:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm), MQPR:{ *:[v4f32] }:$Qd_src)<<P:Predicate_fadd_contract>> => (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 38515 | /* 105844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf32), |
| 38516 | /* 105847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38517 | /* 105849 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 38518 | /* 105851 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Qn |
| 38519 | /* 105855 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/4, // Qm |
| 38520 | /* 105859 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // rot |
| 38521 | /* 105862 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38522 | /* 105865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38523 | /* 105871 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38524 | /* 105877 */ GIR_RootConstrainSelectedInstOperands, |
| 38525 | /* 105878 */ // GIR_Coverage, 6673, |
| 38526 | /* 105878 */ GIR_EraseRootFromParent_Done, |
| 38527 | /* 105879 */ // Label 3237: @105879 |
| 38528 | /* 105879 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3238*/ GIMT_Encode4(105973), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4433 // |
| 38529 | /* 105886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38530 | /* 105890 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38531 | /* 105894 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 38532 | /* 105898 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/5, |
| 38533 | /* 105901 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq), |
| 38534 | /* 105906 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38535 | /* 105910 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s32, |
| 38536 | /* 105914 */ GIM_CheckType, /*MI*/1, /*Op*/4, /*Type*/GILLT_v4s32, |
| 38537 | /* 105918 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 38538 | /* 105922 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 38539 | /* 105926 */ // MIs[2] Operand 1 |
| 38540 | /* 105926 */ // No operand predicates |
| 38541 | /* 105926 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38542 | /* 105931 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38543 | /* 105936 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 38544 | /* 105938 */ // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, (intrinsic_wo_chain:{ *:[v4f32] } 3833:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm))<<P:Predicate_fadd_contract>> => (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 38545 | /* 105938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf32), |
| 38546 | /* 105941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38547 | /* 105943 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd_src |
| 38548 | /* 105945 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Qn |
| 38549 | /* 105949 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/4, // Qm |
| 38550 | /* 105953 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // rot |
| 38551 | /* 105956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38552 | /* 105959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38553 | /* 105965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38554 | /* 105971 */ GIR_RootConstrainSelectedInstOperands, |
| 38555 | /* 105972 */ // GIR_Coverage, 4433, |
| 38556 | /* 105972 */ GIR_EraseRootFromParent_Done, |
| 38557 | /* 105973 */ // Label 3238: @105973 |
| 38558 | /* 105973 */ GIM_Reject, |
| 38559 | /* 105974 */ // Label 3236: @105974 |
| 38560 | /* 105974 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3239*/ GIMT_Encode4(106013), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 885 // |
| 38561 | /* 105981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38562 | /* 105985 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38563 | /* 105989 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38564 | /* 105993 */ // (fadd:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VADDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 38565 | /* 105993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfq), |
| 38566 | /* 105996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38567 | /* 105998 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38568 | /* 106000 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38569 | /* 106002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38570 | /* 106005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38571 | /* 106011 */ GIR_RootConstrainSelectedInstOperands, |
| 38572 | /* 106012 */ // GIR_Coverage, 885, |
| 38573 | /* 106012 */ GIR_EraseRootFromParent_Done, |
| 38574 | /* 106013 */ // Label 3239: @106013 |
| 38575 | /* 106013 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3240*/ GIMT_Encode4(106073), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4455 // |
| 38576 | /* 106020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38577 | /* 106024 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38578 | /* 106028 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38579 | /* 106032 */ // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 38580 | /* 106032 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38581 | /* 106035 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38582 | /* 106039 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38583 | /* 106044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32), |
| 38584 | /* 106047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38585 | /* 106049 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 38586 | /* 106051 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 38587 | /* 106053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38588 | /* 106056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38589 | /* 106062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38590 | /* 106068 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38591 | /* 106071 */ GIR_RootConstrainSelectedInstOperands, |
| 38592 | /* 106072 */ // GIR_Coverage, 4455, |
| 38593 | /* 106072 */ GIR_EraseRootFromParent_Done, |
| 38594 | /* 106073 */ // Label 3240: @106073 |
| 38595 | /* 106073 */ GIM_Reject, |
| 38596 | /* 106074 */ // Label 3235: @106074 |
| 38597 | /* 106074 */ GIM_Reject, |
| 38598 | /* 106075 */ // Label 3205: @106075 |
| 38599 | /* 106075 */ GIM_Reject, |
| 38600 | /* 106076 */ // Label 41: @106076 |
| 38601 | /* 106076 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3248*/ GIMT_Encode4(107788), |
| 38602 | /* 106087 */ /*GILLT_s16*//*Label 3241*/ GIMT_Encode4(106139), |
| 38603 | /* 106091 */ /*GILLT_s32*//*Label 3242*/ GIMT_Encode4(106185), |
| 38604 | /* 106095 */ /*GILLT_s64*//*Label 3243*/ GIMT_Encode4(107132), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38605 | /* 106123 */ /*GILLT_v4s16*//*Label 3244*/ GIMT_Encode4(107178), |
| 38606 | /* 106127 */ /*GILLT_v8s16*//*Label 3245*/ GIMT_Encode4(107374), |
| 38607 | /* 106131 */ /*GILLT_v2s32*//*Label 3246*/ GIMT_Encode4(107630), |
| 38608 | /* 106135 */ /*GILLT_v4s32*//*Label 3247*/ GIMT_Encode4(107676), |
| 38609 | /* 106139 */ // Label 3241: @106139 |
| 38610 | /* 106139 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3249*/ GIMT_Encode4(106184), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 627 // |
| 38611 | /* 106146 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 38612 | /* 106149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 38613 | /* 106152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38614 | /* 106156 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38615 | /* 106160 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38616 | /* 106164 */ // (fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 38617 | /* 106164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH), |
| 38618 | /* 106167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38619 | /* 106169 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38620 | /* 106171 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38621 | /* 106173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38622 | /* 106176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38623 | /* 106182 */ GIR_RootConstrainSelectedInstOperands, |
| 38624 | /* 106183 */ // GIR_Coverage, 627, |
| 38625 | /* 106183 */ GIR_EraseRootFromParent_Done, |
| 38626 | /* 106184 */ // Label 3249: @106184 |
| 38627 | /* 106184 */ GIM_Reject, |
| 38628 | /* 106185 */ // Label 3242: @106185 |
| 38629 | /* 106185 */ GIM_Try, /*On fail goto*//*Label 3250*/ GIMT_Encode4(107131), |
| 38630 | /* 106190 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 38631 | /* 106193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 38632 | /* 106196 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3251*/ GIMT_Encode4(106535), GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), // Rule ID 3092 // |
| 38633 | /* 106203 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38634 | /* 106207 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38635 | /* 106211 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38636 | /* 106215 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38637 | /* 106219 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38638 | /* 106223 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38639 | /* 106227 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38640 | /* 106232 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38641 | /* 106237 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract), |
| 38642 | /* 106241 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fsub_contract), |
| 38643 | /* 106245 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38644 | /* 106247 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)<<P:Predicate_fmul_contract>>)<<P:Predicate_fsub_contract>> => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38645 | /* 106247 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 38646 | /* 106250 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38647 | /* 106254 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38648 | /* 106259 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 38649 | /* 106261 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 38650 | /* 106264 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38651 | /* 106268 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38652 | /* 106273 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 38653 | /* 106276 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38654 | /* 106281 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 38655 | /* 106284 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38656 | /* 106288 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38657 | /* 106293 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 38658 | /* 106296 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 38659 | /* 106300 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 38660 | /* 106303 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38661 | /* 106308 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38662 | /* 106313 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38663 | /* 106318 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38664 | /* 106321 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38665 | /* 106325 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38666 | /* 106330 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38667 | /* 106332 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38668 | /* 106335 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38669 | /* 106339 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38670 | /* 106344 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38671 | /* 106347 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38672 | /* 106352 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38673 | /* 106355 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38674 | /* 106359 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38675 | /* 106364 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38676 | /* 106367 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38677 | /* 106371 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38678 | /* 106374 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38679 | /* 106379 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38680 | /* 106384 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38681 | /* 106389 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38682 | /* 106392 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38683 | /* 106396 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38684 | /* 106401 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38685 | /* 106403 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38686 | /* 106406 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38687 | /* 106410 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38688 | /* 106415 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38689 | /* 106418 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38690 | /* 106423 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38691 | /* 106426 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38692 | /* 106430 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38693 | /* 106435 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38694 | /* 106438 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 38695 | /* 106442 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38696 | /* 106445 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38697 | /* 106450 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38698 | /* 106455 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38699 | /* 106460 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38700 | /* 106463 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMSfd), |
| 38701 | /* 106467 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38702 | /* 106472 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38703 | /* 106475 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38704 | /* 106478 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38705 | /* 106481 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38706 | /* 106484 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38707 | /* 106490 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38708 | /* 106492 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38709 | /* 106495 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38710 | /* 106499 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38711 | /* 106504 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38712 | /* 106507 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38713 | /* 106512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38714 | /* 106515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38715 | /* 106517 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38716 | /* 106524 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38717 | /* 106529 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38718 | /* 106534 */ // GIR_Coverage, 3092, |
| 38719 | /* 106534 */ GIR_EraseRootFromParent_Done, |
| 38720 | /* 106535 */ // Label 3251: @106535 |
| 38721 | /* 106535 */ GIM_Try, /*On fail goto*//*Label 3252*/ GIMT_Encode4(107130), |
| 38722 | /* 106540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38723 | /* 106544 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38724 | /* 106548 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3253*/ GIMT_Encode4(106871), GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), // Rule ID 3090 // |
| 38725 | /* 106555 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38726 | /* 106559 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38727 | /* 106563 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38728 | /* 106567 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38729 | /* 106571 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38730 | /* 106576 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38731 | /* 106581 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38732 | /* 106583 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38733 | /* 106583 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 38734 | /* 106586 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38735 | /* 106590 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38736 | /* 106595 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 38737 | /* 106597 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 38738 | /* 106600 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38739 | /* 106604 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38740 | /* 106609 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 38741 | /* 106612 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38742 | /* 106617 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 38743 | /* 106620 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38744 | /* 106624 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38745 | /* 106629 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 38746 | /* 106632 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 38747 | /* 106636 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 38748 | /* 106639 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38749 | /* 106644 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38750 | /* 106649 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38751 | /* 106654 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38752 | /* 106657 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38753 | /* 106661 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38754 | /* 106666 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38755 | /* 106668 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38756 | /* 106671 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38757 | /* 106675 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38758 | /* 106680 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38759 | /* 106683 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38760 | /* 106688 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38761 | /* 106691 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38762 | /* 106695 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38763 | /* 106700 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38764 | /* 106703 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38765 | /* 106707 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38766 | /* 106710 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38767 | /* 106715 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38768 | /* 106720 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38769 | /* 106725 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38770 | /* 106728 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38771 | /* 106732 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38772 | /* 106737 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38773 | /* 106739 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38774 | /* 106742 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38775 | /* 106746 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38776 | /* 106751 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38777 | /* 106754 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38778 | /* 106759 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38779 | /* 106762 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38780 | /* 106766 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38781 | /* 106771 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38782 | /* 106774 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 38783 | /* 106778 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38784 | /* 106781 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38785 | /* 106786 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38786 | /* 106791 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38787 | /* 106796 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38788 | /* 106799 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLSfd), |
| 38789 | /* 106803 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38790 | /* 106808 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38791 | /* 106811 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38792 | /* 106814 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38793 | /* 106817 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38794 | /* 106820 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38795 | /* 106826 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38796 | /* 106828 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38797 | /* 106831 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38798 | /* 106835 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38799 | /* 106840 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38800 | /* 106843 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38801 | /* 106848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38802 | /* 106851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38803 | /* 106853 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38804 | /* 106860 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38805 | /* 106865 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38806 | /* 106870 */ // GIR_Coverage, 3090, |
| 38807 | /* 106870 */ GIR_EraseRootFromParent_Done, |
| 38808 | /* 106871 */ // Label 3253: @106871 |
| 38809 | /* 106871 */ GIM_Try, /*On fail goto*//*Label 3254*/ GIMT_Encode4(107129), |
| 38810 | /* 106876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38811 | /* 106880 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3255*/ GIMT_Encode4(106907), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 625 // |
| 38812 | /* 106887 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 38813 | /* 106887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS), |
| 38814 | /* 106890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38815 | /* 106892 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38816 | /* 106894 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38817 | /* 106896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38818 | /* 106899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38819 | /* 106905 */ GIR_RootConstrainSelectedInstOperands, |
| 38820 | /* 106906 */ // GIR_Coverage, 625, |
| 38821 | /* 106906 */ GIR_EraseRootFromParent_Done, |
| 38822 | /* 106907 */ // Label 3255: @106907 |
| 38823 | /* 106907 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3256*/ GIMT_Encode4(107128), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3087 // |
| 38824 | /* 106914 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VSUBfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38825 | /* 106914 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38826 | /* 106917 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38827 | /* 106921 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38828 | /* 106926 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38829 | /* 106928 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38830 | /* 106931 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38831 | /* 106935 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38832 | /* 106940 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38833 | /* 106943 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38834 | /* 106948 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38835 | /* 106951 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38836 | /* 106955 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38837 | /* 106960 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38838 | /* 106963 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 38839 | /* 106967 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38840 | /* 106970 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38841 | /* 106975 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38842 | /* 106980 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38843 | /* 106985 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38844 | /* 106988 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38845 | /* 106992 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38846 | /* 106997 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38847 | /* 106999 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38848 | /* 107002 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38849 | /* 107006 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38850 | /* 107011 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38851 | /* 107014 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38852 | /* 107019 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38853 | /* 107022 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38854 | /* 107026 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38855 | /* 107031 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38856 | /* 107034 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 38857 | /* 107038 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38858 | /* 107041 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38859 | /* 107046 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38860 | /* 107051 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38861 | /* 107056 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38862 | /* 107059 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VSUBfd), |
| 38863 | /* 107063 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38864 | /* 107068 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38865 | /* 107071 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38866 | /* 107074 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38867 | /* 107077 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38868 | /* 107083 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38869 | /* 107085 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38870 | /* 107088 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38871 | /* 107092 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38872 | /* 107097 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38873 | /* 107100 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38874 | /* 107105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38875 | /* 107108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38876 | /* 107110 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38877 | /* 107117 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38878 | /* 107122 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38879 | /* 107127 */ // GIR_Coverage, 3087, |
| 38880 | /* 107127 */ GIR_EraseRootFromParent_Done, |
| 38881 | /* 107128 */ // Label 3256: @107128 |
| 38882 | /* 107128 */ GIM_Reject, |
| 38883 | /* 107129 */ // Label 3254: @107129 |
| 38884 | /* 107129 */ GIM_Reject, |
| 38885 | /* 107130 */ // Label 3252: @107130 |
| 38886 | /* 107130 */ GIM_Reject, |
| 38887 | /* 107131 */ // Label 3250: @107131 |
| 38888 | /* 107131 */ GIM_Reject, |
| 38889 | /* 107132 */ // Label 3243: @107132 |
| 38890 | /* 107132 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3257*/ GIMT_Encode4(107177), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 623 // |
| 38891 | /* 107139 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 38892 | /* 107142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 38893 | /* 107145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38894 | /* 107149 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38895 | /* 107153 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38896 | /* 107157 */ // (fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 38897 | /* 107157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD), |
| 38898 | /* 107160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 38899 | /* 107162 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 38900 | /* 107164 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 38901 | /* 107166 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38902 | /* 107169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38903 | /* 107175 */ GIR_RootConstrainSelectedInstOperands, |
| 38904 | /* 107176 */ // GIR_Coverage, 623, |
| 38905 | /* 107176 */ GIR_EraseRootFromParent_Done, |
| 38906 | /* 107177 */ // Label 3257: @107177 |
| 38907 | /* 107177 */ GIM_Reject, |
| 38908 | /* 107178 */ // Label 3244: @107178 |
| 38909 | /* 107178 */ GIM_Try, /*On fail goto*//*Label 3258*/ GIMT_Encode4(107373), |
| 38910 | /* 107183 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38911 | /* 107186 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38912 | /* 107189 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3259*/ GIMT_Encode4(107266), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1111 // |
| 38913 | /* 107196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38914 | /* 107200 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38915 | /* 107204 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38916 | /* 107208 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38917 | /* 107212 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38918 | /* 107216 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38919 | /* 107220 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38920 | /* 107225 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38921 | /* 107230 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract), |
| 38922 | /* 107234 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fsub_contract), |
| 38923 | /* 107238 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38924 | /* 107240 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)<<P:Predicate_fmul_contract>>)<<P:Predicate_fsub_contract>> => (VFMShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38925 | /* 107240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShd), |
| 38926 | /* 107243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38927 | /* 107245 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38928 | /* 107247 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38929 | /* 107251 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38930 | /* 107255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38931 | /* 107258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38932 | /* 107264 */ GIR_RootConstrainSelectedInstOperands, |
| 38933 | /* 107265 */ // GIR_Coverage, 1111, |
| 38934 | /* 107265 */ GIR_EraseRootFromParent_Done, |
| 38935 | /* 107266 */ // Label 3259: @107266 |
| 38936 | /* 107266 */ GIM_Try, /*On fail goto*//*Label 3260*/ GIMT_Encode4(107372), |
| 38937 | /* 107271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38938 | /* 107275 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38939 | /* 107279 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3261*/ GIMT_Encode4(107340), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx), // Rule ID 1067 // |
| 38940 | /* 107286 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38941 | /* 107290 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38942 | /* 107294 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38943 | /* 107298 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38944 | /* 107302 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38945 | /* 107307 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38946 | /* 107312 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38947 | /* 107314 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VMLShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38948 | /* 107314 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShd), |
| 38949 | /* 107317 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38950 | /* 107319 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38951 | /* 107321 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38952 | /* 107325 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38953 | /* 107329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38954 | /* 107332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38955 | /* 107338 */ GIR_RootConstrainSelectedInstOperands, |
| 38956 | /* 107339 */ // GIR_Coverage, 1067, |
| 38957 | /* 107339 */ GIR_EraseRootFromParent_Done, |
| 38958 | /* 107340 */ // Label 3261: @107340 |
| 38959 | /* 107340 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3262*/ GIMT_Encode4(107371), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1132 // |
| 38960 | /* 107347 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38961 | /* 107351 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VSUBhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38962 | /* 107351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhd), |
| 38963 | /* 107354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38964 | /* 107356 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38965 | /* 107358 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38966 | /* 107360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38967 | /* 107363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38968 | /* 107369 */ GIR_RootConstrainSelectedInstOperands, |
| 38969 | /* 107370 */ // GIR_Coverage, 1132, |
| 38970 | /* 107370 */ GIR_EraseRootFromParent_Done, |
| 38971 | /* 107371 */ // Label 3262: @107371 |
| 38972 | /* 107371 */ GIM_Reject, |
| 38973 | /* 107372 */ // Label 3260: @107372 |
| 38974 | /* 107372 */ GIM_Reject, |
| 38975 | /* 107373 */ // Label 3258: @107373 |
| 38976 | /* 107373 */ GIM_Reject, |
| 38977 | /* 107374 */ // Label 3245: @107374 |
| 38978 | /* 107374 */ GIM_Try, /*On fail goto*//*Label 3263*/ GIMT_Encode4(107629), |
| 38979 | /* 107379 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38980 | /* 107382 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38981 | /* 107385 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3264*/ GIMT_Encode4(107462), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1112 // |
| 38982 | /* 107392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38983 | /* 107396 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38984 | /* 107400 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38985 | /* 107404 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38986 | /* 107408 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38987 | /* 107412 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38988 | /* 107416 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38989 | /* 107421 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38990 | /* 107426 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmul_contract), |
| 38991 | /* 107430 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fsub_contract), |
| 38992 | /* 107434 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38993 | /* 107436 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)<<P:Predicate_fmul_contract>>)<<P:Predicate_fsub_contract>> => (VFMShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38994 | /* 107436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShq), |
| 38995 | /* 107439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38996 | /* 107441 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38997 | /* 107443 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38998 | /* 107447 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38999 | /* 107451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39000 | /* 107454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39001 | /* 107460 */ GIR_RootConstrainSelectedInstOperands, |
| 39002 | /* 107461 */ // GIR_Coverage, 1112, |
| 39003 | /* 107461 */ GIR_EraseRootFromParent_Done, |
| 39004 | /* 107462 */ // Label 3264: @107462 |
| 39005 | /* 107462 */ GIM_Try, /*On fail goto*//*Label 3265*/ GIMT_Encode4(107568), |
| 39006 | /* 107467 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39007 | /* 107471 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39008 | /* 107475 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3266*/ GIMT_Encode4(107536), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx), // Rule ID 1068 // |
| 39009 | /* 107482 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39010 | /* 107486 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 39011 | /* 107490 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39012 | /* 107494 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39013 | /* 107498 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39014 | /* 107503 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39015 | /* 107508 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39016 | /* 107510 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VMLShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 39017 | /* 107510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShq), |
| 39018 | /* 107513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39019 | /* 107515 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 39020 | /* 107517 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 39021 | /* 107521 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 39022 | /* 107525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39023 | /* 107528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39024 | /* 107534 */ GIR_RootConstrainSelectedInstOperands, |
| 39025 | /* 107535 */ // GIR_Coverage, 1068, |
| 39026 | /* 107535 */ GIR_EraseRootFromParent_Done, |
| 39027 | /* 107536 */ // Label 3266: @107536 |
| 39028 | /* 107536 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3267*/ GIMT_Encode4(107567), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1133 // |
| 39029 | /* 107543 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39030 | /* 107547 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VSUBhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 39031 | /* 107547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhq), |
| 39032 | /* 107550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39033 | /* 107552 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39034 | /* 107554 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39035 | /* 107556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39036 | /* 107559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39037 | /* 107565 */ GIR_RootConstrainSelectedInstOperands, |
| 39038 | /* 107566 */ // GIR_Coverage, 1133, |
| 39039 | /* 107566 */ GIR_EraseRootFromParent_Done, |
| 39040 | /* 107567 */ // Label 3267: @107567 |
| 39041 | /* 107567 */ GIM_Reject, |
| 39042 | /* 107568 */ // Label 3265: @107568 |
| 39043 | /* 107568 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3268*/ GIMT_Encode4(107628), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4476 // |
| 39044 | /* 107575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39045 | /* 107579 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39046 | /* 107583 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39047 | /* 107587 */ // (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 39048 | /* 107587 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39049 | /* 107590 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39050 | /* 107594 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39051 | /* 107599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16), |
| 39052 | /* 107602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39053 | /* 107604 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39054 | /* 107606 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39055 | /* 107608 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39056 | /* 107611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39057 | /* 107617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39058 | /* 107623 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39059 | /* 107626 */ GIR_RootConstrainSelectedInstOperands, |
| 39060 | /* 107627 */ // GIR_Coverage, 4476, |
| 39061 | /* 107627 */ GIR_EraseRootFromParent_Done, |
| 39062 | /* 107628 */ // Label 3268: @107628 |
| 39063 | /* 107628 */ GIM_Reject, |
| 39064 | /* 107629 */ // Label 3263: @107629 |
| 39065 | /* 107629 */ GIM_Reject, |
| 39066 | /* 107630 */ // Label 3246: @107630 |
| 39067 | /* 107630 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3269*/ GIMT_Encode4(107675), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1130 // |
| 39068 | /* 107637 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39069 | /* 107640 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39070 | /* 107643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39071 | /* 107647 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39072 | /* 107651 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39073 | /* 107655 */ // (fsub:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VSUBfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 39074 | /* 107655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfd), |
| 39075 | /* 107658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39076 | /* 107660 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39077 | /* 107662 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39078 | /* 107664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39079 | /* 107667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39080 | /* 107673 */ GIR_RootConstrainSelectedInstOperands, |
| 39081 | /* 107674 */ // GIR_Coverage, 1130, |
| 39082 | /* 107674 */ GIR_EraseRootFromParent_Done, |
| 39083 | /* 107675 */ // Label 3269: @107675 |
| 39084 | /* 107675 */ GIM_Reject, |
| 39085 | /* 107676 */ // Label 3247: @107676 |
| 39086 | /* 107676 */ GIM_Try, /*On fail goto*//*Label 3270*/ GIMT_Encode4(107787), |
| 39087 | /* 107681 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39088 | /* 107684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39089 | /* 107687 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3271*/ GIMT_Encode4(107726), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1131 // |
| 39090 | /* 107694 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39091 | /* 107698 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39092 | /* 107702 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39093 | /* 107706 */ // (fsub:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VSUBfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 39094 | /* 107706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfq), |
| 39095 | /* 107709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39096 | /* 107711 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39097 | /* 107713 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39098 | /* 107715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39099 | /* 107718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39100 | /* 107724 */ GIR_RootConstrainSelectedInstOperands, |
| 39101 | /* 107725 */ // GIR_Coverage, 1131, |
| 39102 | /* 107725 */ GIR_EraseRootFromParent_Done, |
| 39103 | /* 107726 */ // Label 3271: @107726 |
| 39104 | /* 107726 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3272*/ GIMT_Encode4(107786), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4469 // |
| 39105 | /* 107733 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39106 | /* 107737 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39107 | /* 107741 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39108 | /* 107745 */ // (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 39109 | /* 107745 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39110 | /* 107748 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39111 | /* 107752 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39112 | /* 107757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32), |
| 39113 | /* 107760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39114 | /* 107762 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39115 | /* 107764 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39116 | /* 107766 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39117 | /* 107769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39118 | /* 107775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39119 | /* 107781 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39120 | /* 107784 */ GIR_RootConstrainSelectedInstOperands, |
| 39121 | /* 107785 */ // GIR_Coverage, 4469, |
| 39122 | /* 107785 */ GIR_EraseRootFromParent_Done, |
| 39123 | /* 107786 */ // Label 3272: @107786 |
| 39124 | /* 107786 */ GIM_Reject, |
| 39125 | /* 107787 */ // Label 3270: @107787 |
| 39126 | /* 107787 */ GIM_Reject, |
| 39127 | /* 107788 */ // Label 3248: @107788 |
| 39128 | /* 107788 */ GIM_Reject, |
| 39129 | /* 107789 */ // Label 42: @107789 |
| 39130 | /* 107789 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3280*/ GIMT_Encode4(108753), |
| 39131 | /* 107800 */ /*GILLT_s16*//*Label 3273*/ GIMT_Encode4(107852), |
| 39132 | /* 107804 */ /*GILLT_s32*//*Label 3274*/ GIMT_Encode4(107898), |
| 39133 | /* 107808 */ /*GILLT_s64*//*Label 3275*/ GIMT_Encode4(108279), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39134 | /* 107836 */ /*GILLT_v4s16*//*Label 3276*/ GIMT_Encode4(108437), |
| 39135 | /* 107840 */ /*GILLT_v8s16*//*Label 3277*/ GIMT_Encode4(108483), |
| 39136 | /* 107844 */ /*GILLT_v2s32*//*Label 3278*/ GIMT_Encode4(108595), |
| 39137 | /* 107848 */ /*GILLT_v4s32*//*Label 3279*/ GIMT_Encode4(108641), |
| 39138 | /* 107852 */ // Label 3273: @107852 |
| 39139 | /* 107852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3281*/ GIMT_Encode4(107897), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 639 // |
| 39140 | /* 107859 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 39141 | /* 107862 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 39142 | /* 107865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39143 | /* 107869 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39144 | /* 107873 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39145 | /* 107877 */ // (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39146 | /* 107877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH), |
| 39147 | /* 107880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39148 | /* 107882 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39149 | /* 107884 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39150 | /* 107886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39151 | /* 107889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39152 | /* 107895 */ GIR_RootConstrainSelectedInstOperands, |
| 39153 | /* 107896 */ // GIR_Coverage, 639, |
| 39154 | /* 107896 */ GIR_EraseRootFromParent_Done, |
| 39155 | /* 107897 */ // Label 3281: @107897 |
| 39156 | /* 107897 */ GIM_Reject, |
| 39157 | /* 107898 */ // Label 3274: @107898 |
| 39158 | /* 107898 */ GIM_Try, /*On fail goto*//*Label 3282*/ GIMT_Encode4(108278), |
| 39159 | /* 107903 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 39160 | /* 107906 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 39161 | /* 107909 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39162 | /* 107913 */ GIM_Try, /*On fail goto*//*Label 3283*/ GIMT_Encode4(107963), // Rule ID 2502 // |
| 39163 | /* 107918 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39164 | /* 107922 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39165 | /* 107926 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39166 | /* 107930 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39167 | /* 107935 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39168 | /* 107939 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39169 | /* 107941 */ // (fmul:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) |
| 39170 | /* 107941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 39171 | /* 107944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39172 | /* 107946 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 39173 | /* 107950 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 39174 | /* 107952 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39175 | /* 107955 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39176 | /* 107961 */ GIR_RootConstrainSelectedInstOperands, |
| 39177 | /* 107962 */ // GIR_Coverage, 2502, |
| 39178 | /* 107962 */ GIR_EraseRootFromParent_Done, |
| 39179 | /* 107963 */ // Label 3283: @107963 |
| 39180 | /* 107963 */ GIM_Try, /*On fail goto*//*Label 3284*/ GIMT_Encode4(108277), |
| 39181 | /* 107968 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39182 | /* 107972 */ GIM_Try, /*On fail goto*//*Label 3285*/ GIMT_Encode4(108018), // Rule ID 6320 // |
| 39183 | /* 107977 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39184 | /* 107981 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39185 | /* 107985 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39186 | /* 107989 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39187 | /* 107994 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39188 | /* 107996 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) |
| 39189 | /* 107996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 39190 | /* 107999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39191 | /* 108001 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 39192 | /* 108005 */ GIR_RootToRootCopy, /*OpIdx*/1, // b |
| 39193 | /* 108007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39194 | /* 108010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39195 | /* 108016 */ GIR_RootConstrainSelectedInstOperands, |
| 39196 | /* 108017 */ // GIR_Coverage, 6320, |
| 39197 | /* 108017 */ GIR_EraseRootFromParent_Done, |
| 39198 | /* 108018 */ // Label 3285: @108018 |
| 39199 | /* 108018 */ GIM_Try, /*On fail goto*//*Label 3286*/ GIMT_Encode4(108276), |
| 39200 | /* 108023 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39201 | /* 108027 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3287*/ GIMT_Encode4(108054), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 637 // |
| 39202 | /* 108034 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39203 | /* 108034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS), |
| 39204 | /* 108037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39205 | /* 108039 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39206 | /* 108041 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39207 | /* 108043 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39208 | /* 108046 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39209 | /* 108052 */ GIR_RootConstrainSelectedInstOperands, |
| 39210 | /* 108053 */ // GIR_Coverage, 637, |
| 39211 | /* 108053 */ GIR_EraseRootFromParent_Done, |
| 39212 | /* 108054 */ // Label 3287: @108054 |
| 39213 | /* 108054 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3288*/ GIMT_Encode4(108275), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3088 // |
| 39214 | /* 108061 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMULfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 39215 | /* 108061 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 39216 | /* 108064 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39217 | /* 108068 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39218 | /* 108073 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 39219 | /* 108075 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 39220 | /* 108078 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39221 | /* 108082 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39222 | /* 108087 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 39223 | /* 108090 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39224 | /* 108095 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 39225 | /* 108098 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 39226 | /* 108102 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39227 | /* 108107 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 39228 | /* 108110 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 39229 | /* 108114 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 39230 | /* 108117 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39231 | /* 108122 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39232 | /* 108127 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 39233 | /* 108132 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 39234 | /* 108135 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39235 | /* 108139 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39236 | /* 108144 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 39237 | /* 108146 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 39238 | /* 108149 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39239 | /* 108153 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39240 | /* 108158 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 39241 | /* 108161 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39242 | /* 108166 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 39243 | /* 108169 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 39244 | /* 108173 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39245 | /* 108178 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 39246 | /* 108181 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 39247 | /* 108185 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 39248 | /* 108188 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39249 | /* 108193 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39250 | /* 108198 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 39251 | /* 108203 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 39252 | /* 108206 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMULfd), |
| 39253 | /* 108210 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39254 | /* 108215 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 39255 | /* 108218 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 39256 | /* 108221 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 39257 | /* 108224 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39258 | /* 108230 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 39259 | /* 108232 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 39260 | /* 108235 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39261 | /* 108239 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39262 | /* 108244 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 39263 | /* 108247 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39264 | /* 108252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39265 | /* 108255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 39266 | /* 108257 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 39267 | /* 108264 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 39268 | /* 108269 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39269 | /* 108274 */ // GIR_Coverage, 3088, |
| 39270 | /* 108274 */ GIR_EraseRootFromParent_Done, |
| 39271 | /* 108275 */ // Label 3288: @108275 |
| 39272 | /* 108275 */ GIM_Reject, |
| 39273 | /* 108276 */ // Label 3286: @108276 |
| 39274 | /* 108276 */ GIM_Reject, |
| 39275 | /* 108277 */ // Label 3284: @108277 |
| 39276 | /* 108277 */ GIM_Reject, |
| 39277 | /* 108278 */ // Label 3282: @108278 |
| 39278 | /* 108278 */ GIM_Reject, |
| 39279 | /* 108279 */ // Label 3275: @108279 |
| 39280 | /* 108279 */ GIM_Try, /*On fail goto*//*Label 3289*/ GIMT_Encode4(108436), |
| 39281 | /* 108284 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 39282 | /* 108287 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 39283 | /* 108290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39284 | /* 108294 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3290*/ GIMT_Encode4(108346), GIMT_Encode2(GIFBS_HasDPVFP), // Rule ID 2501 // |
| 39285 | /* 108301 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39286 | /* 108305 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39287 | /* 108309 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39288 | /* 108313 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39289 | /* 108318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39290 | /* 108322 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39291 | /* 108324 */ // (fmul:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a), DPR:{ *:[f64] }:$b) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b) |
| 39292 | /* 108324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 39293 | /* 108327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39294 | /* 108329 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 39295 | /* 108333 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 39296 | /* 108335 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39297 | /* 108338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39298 | /* 108344 */ GIR_RootConstrainSelectedInstOperands, |
| 39299 | /* 108345 */ // GIR_Coverage, 2501, |
| 39300 | /* 108345 */ GIR_EraseRootFromParent_Done, |
| 39301 | /* 108346 */ // Label 3290: @108346 |
| 39302 | /* 108346 */ GIM_Try, /*On fail goto*//*Label 3291*/ GIMT_Encode4(108435), |
| 39303 | /* 108351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39304 | /* 108355 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3292*/ GIMT_Encode4(108403), GIMT_Encode2(GIFBS_HasDPVFP), // Rule ID 6319 // |
| 39305 | /* 108362 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39306 | /* 108366 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39307 | /* 108370 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39308 | /* 108374 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39309 | /* 108379 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39310 | /* 108381 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$b, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b) |
| 39311 | /* 108381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 39312 | /* 108384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39313 | /* 108386 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 39314 | /* 108390 */ GIR_RootToRootCopy, /*OpIdx*/1, // b |
| 39315 | /* 108392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39316 | /* 108395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39317 | /* 108401 */ GIR_RootConstrainSelectedInstOperands, |
| 39318 | /* 108402 */ // GIR_Coverage, 6319, |
| 39319 | /* 108402 */ GIR_EraseRootFromParent_Done, |
| 39320 | /* 108403 */ // Label 3292: @108403 |
| 39321 | /* 108403 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3293*/ GIMT_Encode4(108434), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 635 // |
| 39322 | /* 108410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39323 | /* 108414 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39324 | /* 108414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD), |
| 39325 | /* 108417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39326 | /* 108419 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 39327 | /* 108421 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39328 | /* 108423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39329 | /* 108426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39330 | /* 108432 */ GIR_RootConstrainSelectedInstOperands, |
| 39331 | /* 108433 */ // GIR_Coverage, 635, |
| 39332 | /* 108433 */ GIR_EraseRootFromParent_Done, |
| 39333 | /* 108434 */ // Label 3293: @108434 |
| 39334 | /* 108434 */ GIM_Reject, |
| 39335 | /* 108435 */ // Label 3291: @108435 |
| 39336 | /* 108435 */ GIM_Reject, |
| 39337 | /* 108436 */ // Label 3289: @108436 |
| 39338 | /* 108436 */ GIM_Reject, |
| 39339 | /* 108437 */ // Label 3276: @108437 |
| 39340 | /* 108437 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3294*/ GIMT_Encode4(108482), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 965 // |
| 39341 | /* 108444 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 39342 | /* 108447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39343 | /* 108450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39344 | /* 108454 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39345 | /* 108458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39346 | /* 108462 */ // (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMULhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 39347 | /* 108462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhd), |
| 39348 | /* 108465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39349 | /* 108467 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39350 | /* 108469 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39351 | /* 108471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39352 | /* 108474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39353 | /* 108480 */ GIR_RootConstrainSelectedInstOperands, |
| 39354 | /* 108481 */ // GIR_Coverage, 965, |
| 39355 | /* 108481 */ GIR_EraseRootFromParent_Done, |
| 39356 | /* 108482 */ // Label 3294: @108482 |
| 39357 | /* 108482 */ GIM_Reject, |
| 39358 | /* 108483 */ // Label 3277: @108483 |
| 39359 | /* 108483 */ GIM_Try, /*On fail goto*//*Label 3295*/ GIMT_Encode4(108594), |
| 39360 | /* 108488 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39361 | /* 108491 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39362 | /* 108494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3296*/ GIMT_Encode4(108533), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 966 // |
| 39363 | /* 108501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39364 | /* 108505 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39365 | /* 108509 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39366 | /* 108513 */ // (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMULhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 39367 | /* 108513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhq), |
| 39368 | /* 108516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39369 | /* 108518 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39370 | /* 108520 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39371 | /* 108522 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39372 | /* 108525 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39373 | /* 108531 */ GIR_RootConstrainSelectedInstOperands, |
| 39374 | /* 108532 */ // GIR_Coverage, 966, |
| 39375 | /* 108532 */ GIR_EraseRootFromParent_Done, |
| 39376 | /* 108533 */ // Label 3296: @108533 |
| 39377 | /* 108533 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3297*/ GIMT_Encode4(108593), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4422 // |
| 39378 | /* 108540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39379 | /* 108544 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39380 | /* 108548 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39381 | /* 108552 */ // (fmul:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 39382 | /* 108552 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39383 | /* 108555 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39384 | /* 108559 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39385 | /* 108564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16), |
| 39386 | /* 108567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39387 | /* 108569 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39388 | /* 108571 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39389 | /* 108573 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39390 | /* 108576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39391 | /* 108582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39392 | /* 108588 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39393 | /* 108591 */ GIR_RootConstrainSelectedInstOperands, |
| 39394 | /* 108592 */ // GIR_Coverage, 4422, |
| 39395 | /* 108592 */ GIR_EraseRootFromParent_Done, |
| 39396 | /* 108593 */ // Label 3297: @108593 |
| 39397 | /* 108593 */ GIM_Reject, |
| 39398 | /* 108594 */ // Label 3295: @108594 |
| 39399 | /* 108594 */ GIM_Reject, |
| 39400 | /* 108595 */ // Label 3278: @108595 |
| 39401 | /* 108595 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3298*/ GIMT_Encode4(108640), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 963 // |
| 39402 | /* 108602 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39403 | /* 108605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39404 | /* 108608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39405 | /* 108612 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39406 | /* 108616 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39407 | /* 108620 */ // (fmul:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMULfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 39408 | /* 108620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfd), |
| 39409 | /* 108623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39410 | /* 108625 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39411 | /* 108627 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39412 | /* 108629 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39413 | /* 108632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39414 | /* 108638 */ GIR_RootConstrainSelectedInstOperands, |
| 39415 | /* 108639 */ // GIR_Coverage, 963, |
| 39416 | /* 108639 */ GIR_EraseRootFromParent_Done, |
| 39417 | /* 108640 */ // Label 3298: @108640 |
| 39418 | /* 108640 */ GIM_Reject, |
| 39419 | /* 108641 */ // Label 3279: @108641 |
| 39420 | /* 108641 */ GIM_Try, /*On fail goto*//*Label 3299*/ GIMT_Encode4(108752), |
| 39421 | /* 108646 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39422 | /* 108649 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39423 | /* 108652 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3300*/ GIMT_Encode4(108691), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 964 // |
| 39424 | /* 108659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39425 | /* 108663 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39426 | /* 108667 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39427 | /* 108671 */ // (fmul:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMULfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 39428 | /* 108671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfq), |
| 39429 | /* 108674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39430 | /* 108676 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39431 | /* 108678 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39432 | /* 108680 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39433 | /* 108683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39434 | /* 108689 */ GIR_RootConstrainSelectedInstOperands, |
| 39435 | /* 108690 */ // GIR_Coverage, 964, |
| 39436 | /* 108690 */ GIR_EraseRootFromParent_Done, |
| 39437 | /* 108691 */ // Label 3300: @108691 |
| 39438 | /* 108691 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3301*/ GIMT_Encode4(108751), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4415 // |
| 39439 | /* 108698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39440 | /* 108702 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39441 | /* 108706 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39442 | /* 108710 */ // (fmul:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 39443 | /* 108710 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39444 | /* 108713 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39445 | /* 108717 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39446 | /* 108722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32), |
| 39447 | /* 108725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39448 | /* 108727 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39449 | /* 108729 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39450 | /* 108731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39451 | /* 108734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39452 | /* 108740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39453 | /* 108746 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39454 | /* 108749 */ GIR_RootConstrainSelectedInstOperands, |
| 39455 | /* 108750 */ // GIR_Coverage, 4415, |
| 39456 | /* 108750 */ GIR_EraseRootFromParent_Done, |
| 39457 | /* 108751 */ // Label 3301: @108751 |
| 39458 | /* 108751 */ GIM_Reject, |
| 39459 | /* 108752 */ // Label 3299: @108752 |
| 39460 | /* 108752 */ GIM_Reject, |
| 39461 | /* 108753 */ // Label 3280: @108753 |
| 39462 | /* 108753 */ GIM_Reject, |
| 39463 | /* 108754 */ // Label 43: @108754 |
| 39464 | /* 108754 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3309*/ GIMT_Encode4(110816), |
| 39465 | /* 108765 */ /*GILLT_s16*//*Label 3302*/ GIMT_Encode4(108817), |
| 39466 | /* 108769 */ /*GILLT_s32*//*Label 3303*/ GIMT_Encode4(109198), |
| 39467 | /* 108773 */ /*GILLT_s64*//*Label 3304*/ GIMT_Encode4(109579), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39468 | /* 108801 */ /*GILLT_v4s16*//*Label 3305*/ GIMT_Encode4(109960), |
| 39469 | /* 108805 */ /*GILLT_v8s16*//*Label 3306*/ GIMT_Encode4(110015), |
| 39470 | /* 108809 */ /*GILLT_v2s32*//*Label 3307*/ GIMT_Encode4(110265), |
| 39471 | /* 108813 */ /*GILLT_v4s32*//*Label 3308*/ GIMT_Encode4(110444), |
| 39472 | /* 108817 */ // Label 3302: @108817 |
| 39473 | /* 108817 */ GIM_Try, /*On fail goto*//*Label 3310*/ GIMT_Encode4(109197), |
| 39474 | /* 108822 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 39475 | /* 108825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 39476 | /* 108828 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 39477 | /* 108831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39478 | /* 108835 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3311*/ GIMT_Encode4(108908), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2775 // |
| 39479 | /* 108842 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39480 | /* 108846 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39481 | /* 108850 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39482 | /* 108854 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39483 | /* 108859 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39484 | /* 108863 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39485 | /* 108867 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39486 | /* 108871 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 39487 | /* 108875 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39488 | /* 108880 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39489 | /* 108882 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39490 | /* 108882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 39491 | /* 108885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39492 | /* 108887 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 39493 | /* 108891 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39494 | /* 108895 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39495 | /* 108897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39496 | /* 108900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39497 | /* 108906 */ GIR_RootConstrainSelectedInstOperands, |
| 39498 | /* 108907 */ // GIR_Coverage, 2775, |
| 39499 | /* 108907 */ GIR_EraseRootFromParent_Done, |
| 39500 | /* 108908 */ // Label 3311: @108908 |
| 39501 | /* 108908 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3312*/ GIMT_Encode4(108981), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6340 // |
| 39502 | /* 108915 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39503 | /* 108919 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39504 | /* 108923 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39505 | /* 108927 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39506 | /* 108931 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39507 | /* 108936 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39508 | /* 108940 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39509 | /* 108944 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 39510 | /* 108948 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39511 | /* 108953 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39512 | /* 108955 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39513 | /* 108955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 39514 | /* 108958 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39515 | /* 108960 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 39516 | /* 108964 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39517 | /* 108968 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39518 | /* 108970 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39519 | /* 108973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39520 | /* 108979 */ GIR_RootConstrainSelectedInstOperands, |
| 39521 | /* 108980 */ // GIR_Coverage, 6340, |
| 39522 | /* 108980 */ GIR_EraseRootFromParent_Done, |
| 39523 | /* 108981 */ // Label 3312: @108981 |
| 39524 | /* 108981 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3313*/ GIMT_Encode4(109039), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2755 // |
| 39525 | /* 108988 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39526 | /* 108992 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39527 | /* 108996 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39528 | /* 109000 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39529 | /* 109005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39530 | /* 109009 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39531 | /* 109013 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39532 | /* 109015 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39533 | /* 109015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 39534 | /* 109018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39535 | /* 109020 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39536 | /* 109022 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39537 | /* 109026 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39538 | /* 109028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39539 | /* 109031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39540 | /* 109037 */ GIR_RootConstrainSelectedInstOperands, |
| 39541 | /* 109038 */ // GIR_Coverage, 2755, |
| 39542 | /* 109038 */ GIR_EraseRootFromParent_Done, |
| 39543 | /* 109039 */ // Label 3313: @109039 |
| 39544 | /* 109039 */ GIM_Try, /*On fail goto*//*Label 3314*/ GIMT_Encode4(109196), |
| 39545 | /* 109044 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39546 | /* 109048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3315*/ GIMT_Encode4(109102), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6334 // |
| 39547 | /* 109055 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39548 | /* 109059 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39549 | /* 109063 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39550 | /* 109067 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39551 | /* 109072 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39552 | /* 109076 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39553 | /* 109078 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39554 | /* 109078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 39555 | /* 109081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39556 | /* 109083 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39557 | /* 109085 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39558 | /* 109089 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39559 | /* 109091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39560 | /* 109094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39561 | /* 109100 */ GIR_RootConstrainSelectedInstOperands, |
| 39562 | /* 109101 */ // GIR_Coverage, 6334, |
| 39563 | /* 109101 */ GIR_EraseRootFromParent_Done, |
| 39564 | /* 109102 */ // Label 3315: @109102 |
| 39565 | /* 109102 */ GIM_Try, /*On fail goto*//*Label 3316*/ GIMT_Encode4(109195), |
| 39566 | /* 109107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39567 | /* 109111 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3317*/ GIMT_Encode4(109161), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2789 // |
| 39568 | /* 109118 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39569 | /* 109122 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39570 | /* 109126 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39571 | /* 109130 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39572 | /* 109135 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39573 | /* 109137 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39574 | /* 109137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 39575 | /* 109140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39576 | /* 109142 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 39577 | /* 109146 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39578 | /* 109148 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39579 | /* 109150 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39580 | /* 109153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39581 | /* 109159 */ GIR_RootConstrainSelectedInstOperands, |
| 39582 | /* 109160 */ // GIR_Coverage, 2789, |
| 39583 | /* 109160 */ GIR_EraseRootFromParent_Done, |
| 39584 | /* 109161 */ // Label 3317: @109161 |
| 39585 | /* 109161 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3318*/ GIMT_Encode4(109194), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2737 // |
| 39586 | /* 109168 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39587 | /* 109172 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39588 | /* 109172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH), |
| 39589 | /* 109175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39590 | /* 109177 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39591 | /* 109179 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39592 | /* 109181 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39593 | /* 109183 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39594 | /* 109186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39595 | /* 109192 */ GIR_RootConstrainSelectedInstOperands, |
| 39596 | /* 109193 */ // GIR_Coverage, 2737, |
| 39597 | /* 109193 */ GIR_EraseRootFromParent_Done, |
| 39598 | /* 109194 */ // Label 3318: @109194 |
| 39599 | /* 109194 */ GIM_Reject, |
| 39600 | /* 109195 */ // Label 3316: @109195 |
| 39601 | /* 109195 */ GIM_Reject, |
| 39602 | /* 109196 */ // Label 3314: @109196 |
| 39603 | /* 109196 */ GIM_Reject, |
| 39604 | /* 109197 */ // Label 3310: @109197 |
| 39605 | /* 109197 */ GIM_Reject, |
| 39606 | /* 109198 */ // Label 3303: @109198 |
| 39607 | /* 109198 */ GIM_Try, /*On fail goto*//*Label 3319*/ GIMT_Encode4(109578), |
| 39608 | /* 109203 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 39609 | /* 109206 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 39610 | /* 109209 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 39611 | /* 109212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39612 | /* 109216 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3320*/ GIMT_Encode4(109289), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2773 // |
| 39613 | /* 109223 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39614 | /* 109227 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39615 | /* 109231 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39616 | /* 109235 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39617 | /* 109240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39618 | /* 109244 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39619 | /* 109248 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39620 | /* 109252 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 39621 | /* 109256 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39622 | /* 109261 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39623 | /* 109263 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39624 | /* 109263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 39625 | /* 109266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39626 | /* 109268 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 39627 | /* 109272 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39628 | /* 109276 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39629 | /* 109278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39630 | /* 109281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39631 | /* 109287 */ GIR_RootConstrainSelectedInstOperands, |
| 39632 | /* 109288 */ // GIR_Coverage, 2773, |
| 39633 | /* 109288 */ GIR_EraseRootFromParent_Done, |
| 39634 | /* 109289 */ // Label 3320: @109289 |
| 39635 | /* 109289 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3321*/ GIMT_Encode4(109362), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6338 // |
| 39636 | /* 109296 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39637 | /* 109300 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39638 | /* 109304 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39639 | /* 109308 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39640 | /* 109312 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39641 | /* 109317 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39642 | /* 109321 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39643 | /* 109325 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 39644 | /* 109329 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39645 | /* 109334 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39646 | /* 109336 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39647 | /* 109336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 39648 | /* 109339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39649 | /* 109341 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 39650 | /* 109345 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39651 | /* 109349 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39652 | /* 109351 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39653 | /* 109354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39654 | /* 109360 */ GIR_RootConstrainSelectedInstOperands, |
| 39655 | /* 109361 */ // GIR_Coverage, 6338, |
| 39656 | /* 109361 */ GIR_EraseRootFromParent_Done, |
| 39657 | /* 109362 */ // Label 3321: @109362 |
| 39658 | /* 109362 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3322*/ GIMT_Encode4(109420), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2753 // |
| 39659 | /* 109369 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39660 | /* 109373 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39661 | /* 109377 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39662 | /* 109381 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39663 | /* 109386 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39664 | /* 109390 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39665 | /* 109394 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39666 | /* 109396 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39667 | /* 109396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 39668 | /* 109399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39669 | /* 109401 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39670 | /* 109403 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39671 | /* 109407 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39672 | /* 109409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39673 | /* 109412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39674 | /* 109418 */ GIR_RootConstrainSelectedInstOperands, |
| 39675 | /* 109419 */ // GIR_Coverage, 2753, |
| 39676 | /* 109419 */ GIR_EraseRootFromParent_Done, |
| 39677 | /* 109420 */ // Label 3322: @109420 |
| 39678 | /* 109420 */ GIM_Try, /*On fail goto*//*Label 3323*/ GIMT_Encode4(109577), |
| 39679 | /* 109425 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39680 | /* 109429 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3324*/ GIMT_Encode4(109483), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6332 // |
| 39681 | /* 109436 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39682 | /* 109440 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39683 | /* 109444 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39684 | /* 109448 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39685 | /* 109453 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39686 | /* 109457 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39687 | /* 109459 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39688 | /* 109459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 39689 | /* 109462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39690 | /* 109464 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39691 | /* 109466 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39692 | /* 109470 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39693 | /* 109472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39694 | /* 109475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39695 | /* 109481 */ GIR_RootConstrainSelectedInstOperands, |
| 39696 | /* 109482 */ // GIR_Coverage, 6332, |
| 39697 | /* 109482 */ GIR_EraseRootFromParent_Done, |
| 39698 | /* 109483 */ // Label 3324: @109483 |
| 39699 | /* 109483 */ GIM_Try, /*On fail goto*//*Label 3325*/ GIMT_Encode4(109576), |
| 39700 | /* 109488 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39701 | /* 109492 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3326*/ GIMT_Encode4(109542), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2787 // |
| 39702 | /* 109499 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39703 | /* 109503 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39704 | /* 109507 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39705 | /* 109511 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39706 | /* 109516 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39707 | /* 109518 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39708 | /* 109518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 39709 | /* 109521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39710 | /* 109523 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 39711 | /* 109527 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39712 | /* 109529 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39713 | /* 109531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39714 | /* 109534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39715 | /* 109540 */ GIR_RootConstrainSelectedInstOperands, |
| 39716 | /* 109541 */ // GIR_Coverage, 2787, |
| 39717 | /* 109541 */ GIR_EraseRootFromParent_Done, |
| 39718 | /* 109542 */ // Label 3326: @109542 |
| 39719 | /* 109542 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3327*/ GIMT_Encode4(109575), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2735 // |
| 39720 | /* 109549 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39721 | /* 109553 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39722 | /* 109553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS), |
| 39723 | /* 109556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39724 | /* 109558 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39725 | /* 109560 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39726 | /* 109562 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39727 | /* 109564 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39728 | /* 109567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39729 | /* 109573 */ GIR_RootConstrainSelectedInstOperands, |
| 39730 | /* 109574 */ // GIR_Coverage, 2735, |
| 39731 | /* 109574 */ GIR_EraseRootFromParent_Done, |
| 39732 | /* 109575 */ // Label 3327: @109575 |
| 39733 | /* 109575 */ GIM_Reject, |
| 39734 | /* 109576 */ // Label 3325: @109576 |
| 39735 | /* 109576 */ GIM_Reject, |
| 39736 | /* 109577 */ // Label 3323: @109577 |
| 39737 | /* 109577 */ GIM_Reject, |
| 39738 | /* 109578 */ // Label 3319: @109578 |
| 39739 | /* 109578 */ GIM_Reject, |
| 39740 | /* 109579 */ // Label 3304: @109579 |
| 39741 | /* 109579 */ GIM_Try, /*On fail goto*//*Label 3328*/ GIMT_Encode4(109959), |
| 39742 | /* 109584 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 39743 | /* 109587 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 39744 | /* 109590 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 39745 | /* 109593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39746 | /* 109597 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3329*/ GIMT_Encode4(109670), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2771 // |
| 39747 | /* 109604 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39748 | /* 109608 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39749 | /* 109612 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39750 | /* 109616 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39751 | /* 109621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39752 | /* 109625 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39753 | /* 109629 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39754 | /* 109633 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 39755 | /* 109637 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39756 | /* 109642 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39757 | /* 109644 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39758 | /* 109644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 39759 | /* 109647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39760 | /* 109649 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 39761 | /* 109653 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39762 | /* 109657 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39763 | /* 109659 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39764 | /* 109662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39765 | /* 109668 */ GIR_RootConstrainSelectedInstOperands, |
| 39766 | /* 109669 */ // GIR_Coverage, 2771, |
| 39767 | /* 109669 */ GIR_EraseRootFromParent_Done, |
| 39768 | /* 109670 */ // Label 3329: @109670 |
| 39769 | /* 109670 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3330*/ GIMT_Encode4(109743), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6336 // |
| 39770 | /* 109677 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39771 | /* 109681 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39772 | /* 109685 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39773 | /* 109689 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39774 | /* 109693 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39775 | /* 109698 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39776 | /* 109702 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39777 | /* 109706 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 39778 | /* 109710 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39779 | /* 109715 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39780 | /* 109717 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39781 | /* 109717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 39782 | /* 109720 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39783 | /* 109722 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 39784 | /* 109726 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39785 | /* 109730 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 39786 | /* 109732 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39787 | /* 109735 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39788 | /* 109741 */ GIR_RootConstrainSelectedInstOperands, |
| 39789 | /* 109742 */ // GIR_Coverage, 6336, |
| 39790 | /* 109742 */ GIR_EraseRootFromParent_Done, |
| 39791 | /* 109743 */ // Label 3330: @109743 |
| 39792 | /* 109743 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3331*/ GIMT_Encode4(109801), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2751 // |
| 39793 | /* 109750 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39794 | /* 109754 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39795 | /* 109758 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39796 | /* 109762 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39797 | /* 109767 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39798 | /* 109771 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39799 | /* 109775 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39800 | /* 109777 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39801 | /* 109777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 39802 | /* 109780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39803 | /* 109782 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 39804 | /* 109784 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39805 | /* 109788 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39806 | /* 109790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39807 | /* 109793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39808 | /* 109799 */ GIR_RootConstrainSelectedInstOperands, |
| 39809 | /* 109800 */ // GIR_Coverage, 2751, |
| 39810 | /* 109800 */ GIR_EraseRootFromParent_Done, |
| 39811 | /* 109801 */ // Label 3331: @109801 |
| 39812 | /* 109801 */ GIM_Try, /*On fail goto*//*Label 3332*/ GIMT_Encode4(109958), |
| 39813 | /* 109806 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39814 | /* 109810 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3333*/ GIMT_Encode4(109864), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6330 // |
| 39815 | /* 109817 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39816 | /* 109821 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39817 | /* 109825 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39818 | /* 109829 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39819 | /* 109834 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39820 | /* 109838 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39821 | /* 109840 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39822 | /* 109840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 39823 | /* 109843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39824 | /* 109845 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 39825 | /* 109847 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39826 | /* 109851 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 39827 | /* 109853 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39828 | /* 109856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39829 | /* 109862 */ GIR_RootConstrainSelectedInstOperands, |
| 39830 | /* 109863 */ // GIR_Coverage, 6330, |
| 39831 | /* 109863 */ GIR_EraseRootFromParent_Done, |
| 39832 | /* 109864 */ // Label 3333: @109864 |
| 39833 | /* 109864 */ GIM_Try, /*On fail goto*//*Label 3334*/ GIMT_Encode4(109957), |
| 39834 | /* 109869 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39835 | /* 109873 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3335*/ GIMT_Encode4(109923), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2785 // |
| 39836 | /* 109880 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39837 | /* 109884 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39838 | /* 109888 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39839 | /* 109892 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39840 | /* 109897 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39841 | /* 109899 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39842 | /* 109899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 39843 | /* 109902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39844 | /* 109904 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin |
| 39845 | /* 109908 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 39846 | /* 109910 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39847 | /* 109912 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39848 | /* 109915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39849 | /* 109921 */ GIR_RootConstrainSelectedInstOperands, |
| 39850 | /* 109922 */ // GIR_Coverage, 2785, |
| 39851 | /* 109922 */ GIR_EraseRootFromParent_Done, |
| 39852 | /* 109923 */ // Label 3335: @109923 |
| 39853 | /* 109923 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3336*/ GIMT_Encode4(109956), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2733 // |
| 39854 | /* 109930 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39855 | /* 109934 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39856 | /* 109934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD), |
| 39857 | /* 109937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39858 | /* 109939 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 39859 | /* 109941 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 39860 | /* 109943 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39861 | /* 109945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39862 | /* 109948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39863 | /* 109954 */ GIR_RootConstrainSelectedInstOperands, |
| 39864 | /* 109955 */ // GIR_Coverage, 2733, |
| 39865 | /* 109955 */ GIR_EraseRootFromParent_Done, |
| 39866 | /* 109956 */ // Label 3336: @109956 |
| 39867 | /* 109956 */ GIM_Reject, |
| 39868 | /* 109957 */ // Label 3334: @109957 |
| 39869 | /* 109957 */ GIM_Reject, |
| 39870 | /* 109958 */ // Label 3332: @109958 |
| 39871 | /* 109958 */ GIM_Reject, |
| 39872 | /* 109959 */ // Label 3328: @109959 |
| 39873 | /* 109959 */ GIM_Reject, |
| 39874 | /* 109960 */ // Label 3305: @109960 |
| 39875 | /* 109960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3337*/ GIMT_Encode4(110014), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 2886 // |
| 39876 | /* 109967 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 39877 | /* 109970 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39878 | /* 109973 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 39879 | /* 109976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39880 | /* 109980 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39881 | /* 109984 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39882 | /* 109988 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39883 | /* 109992 */ // (fma:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm, DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 39884 | /* 109992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd), |
| 39885 | /* 109995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39886 | /* 109997 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39887 | /* 109999 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39888 | /* 110001 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39889 | /* 110003 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39890 | /* 110006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39891 | /* 110012 */ GIR_RootConstrainSelectedInstOperands, |
| 39892 | /* 110013 */ // GIR_Coverage, 2886, |
| 39893 | /* 110013 */ GIR_EraseRootFromParent_Done, |
| 39894 | /* 110014 */ // Label 3337: @110014 |
| 39895 | /* 110014 */ GIM_Reject, |
| 39896 | /* 110015 */ // Label 3306: @110015 |
| 39897 | /* 110015 */ GIM_Try, /*On fail goto*//*Label 3338*/ GIMT_Encode4(110264), |
| 39898 | /* 110020 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39899 | /* 110023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39900 | /* 110026 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 39901 | /* 110029 */ GIM_Try, /*On fail goto*//*Label 3339*/ GIMT_Encode4(110167), |
| 39902 | /* 110034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39903 | /* 110038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3340*/ GIMT_Encode4(110102), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4449 // |
| 39904 | /* 110045 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39905 | /* 110049 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39906 | /* 110053 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39907 | /* 110057 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39908 | /* 110062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39909 | /* 110066 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39910 | /* 110070 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39911 | /* 110072 */ // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 39912 | /* 110072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16), |
| 39913 | /* 110075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39914 | /* 110077 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 39915 | /* 110079 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 39916 | /* 110083 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 39917 | /* 110085 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39918 | /* 110088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39919 | /* 110094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39920 | /* 110100 */ GIR_RootConstrainSelectedInstOperands, |
| 39921 | /* 110101 */ // GIR_Coverage, 4449, |
| 39922 | /* 110101 */ GIR_EraseRootFromParent_Done, |
| 39923 | /* 110102 */ // Label 3340: @110102 |
| 39924 | /* 110102 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3341*/ GIMT_Encode4(110166), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 6676 // |
| 39925 | /* 110109 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39926 | /* 110113 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39927 | /* 110117 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39928 | /* 110121 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39929 | /* 110125 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39930 | /* 110130 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39931 | /* 110134 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39932 | /* 110136 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m2, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 39933 | /* 110136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16), |
| 39934 | /* 110139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39935 | /* 110141 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 39936 | /* 110143 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 39937 | /* 110147 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2 |
| 39938 | /* 110149 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39939 | /* 110152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39940 | /* 110158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39941 | /* 110164 */ GIR_RootConstrainSelectedInstOperands, |
| 39942 | /* 110165 */ // GIR_Coverage, 6676, |
| 39943 | /* 110165 */ GIR_EraseRootFromParent_Done, |
| 39944 | /* 110166 */ // Label 3341: @110166 |
| 39945 | /* 110166 */ GIM_Reject, |
| 39946 | /* 110167 */ // Label 3339: @110167 |
| 39947 | /* 110167 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3342*/ GIMT_Encode4(110212), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 2887 // |
| 39948 | /* 110174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39949 | /* 110178 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39950 | /* 110182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39951 | /* 110186 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39952 | /* 110190 */ // (fma:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm, QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 39953 | /* 110190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq), |
| 39954 | /* 110193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39955 | /* 110195 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39956 | /* 110197 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39957 | /* 110199 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39958 | /* 110201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39959 | /* 110204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39960 | /* 110210 */ GIR_RootConstrainSelectedInstOperands, |
| 39961 | /* 110211 */ // GIR_Coverage, 2887, |
| 39962 | /* 110211 */ GIR_EraseRootFromParent_Done, |
| 39963 | /* 110212 */ // Label 3342: @110212 |
| 39964 | /* 110212 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3343*/ GIMT_Encode4(110263), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4445 // |
| 39965 | /* 110219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39966 | /* 110223 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39967 | /* 110227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39968 | /* 110231 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39969 | /* 110235 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 39970 | /* 110235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16), |
| 39971 | /* 110238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39972 | /* 110240 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 39973 | /* 110242 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1 |
| 39974 | /* 110244 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 39975 | /* 110246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39976 | /* 110249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39977 | /* 110255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39978 | /* 110261 */ GIR_RootConstrainSelectedInstOperands, |
| 39979 | /* 110262 */ // GIR_Coverage, 4445, |
| 39980 | /* 110262 */ GIR_EraseRootFromParent_Done, |
| 39981 | /* 110263 */ // Label 3343: @110263 |
| 39982 | /* 110263 */ GIM_Reject, |
| 39983 | /* 110264 */ // Label 3338: @110264 |
| 39984 | /* 110264 */ GIM_Reject, |
| 39985 | /* 110265 */ // Label 3307: @110265 |
| 39986 | /* 110265 */ GIM_Try, /*On fail goto*//*Label 3344*/ GIMT_Encode4(110443), |
| 39987 | /* 110270 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39988 | /* 110273 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39989 | /* 110276 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 39990 | /* 110279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39991 | /* 110283 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3345*/ GIMT_Encode4(110341), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2890 // |
| 39992 | /* 110290 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39993 | /* 110294 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39994 | /* 110298 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39995 | /* 110302 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39996 | /* 110307 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39997 | /* 110311 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39998 | /* 110315 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39999 | /* 110317 */ // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 40000 | /* 110317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd), |
| 40001 | /* 110320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40002 | /* 110322 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 40003 | /* 110324 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 40004 | /* 110328 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40005 | /* 110330 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40006 | /* 110333 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40007 | /* 110339 */ GIR_RootConstrainSelectedInstOperands, |
| 40008 | /* 110340 */ // GIR_Coverage, 2890, |
| 40009 | /* 110340 */ GIR_EraseRootFromParent_Done, |
| 40010 | /* 110341 */ // Label 3345: @110341 |
| 40011 | /* 110341 */ GIM_Try, /*On fail goto*//*Label 3346*/ GIMT_Encode4(110442), |
| 40012 | /* 110346 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40013 | /* 110350 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3347*/ GIMT_Encode4(110404), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 6393 // |
| 40014 | /* 110357 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 40015 | /* 110361 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40016 | /* 110365 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 40017 | /* 110369 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40018 | /* 110374 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40019 | /* 110378 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40020 | /* 110380 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm, (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 40021 | /* 110380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd), |
| 40022 | /* 110383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40023 | /* 110385 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 40024 | /* 110387 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 40025 | /* 110391 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40026 | /* 110393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40027 | /* 110396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40028 | /* 110402 */ GIR_RootConstrainSelectedInstOperands, |
| 40029 | /* 110403 */ // GIR_Coverage, 6393, |
| 40030 | /* 110403 */ GIR_EraseRootFromParent_Done, |
| 40031 | /* 110404 */ // Label 3347: @110404 |
| 40032 | /* 110404 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3348*/ GIMT_Encode4(110441), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2888 // |
| 40033 | /* 110411 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40034 | /* 110415 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40035 | /* 110419 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMAfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 40036 | /* 110419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfd), |
| 40037 | /* 110422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40038 | /* 110424 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 40039 | /* 110426 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40040 | /* 110428 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40041 | /* 110430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40042 | /* 110433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40043 | /* 110439 */ GIR_RootConstrainSelectedInstOperands, |
| 40044 | /* 110440 */ // GIR_Coverage, 2888, |
| 40045 | /* 110440 */ GIR_EraseRootFromParent_Done, |
| 40046 | /* 110441 */ // Label 3348: @110441 |
| 40047 | /* 110441 */ GIM_Reject, |
| 40048 | /* 110442 */ // Label 3346: @110442 |
| 40049 | /* 110442 */ GIM_Reject, |
| 40050 | /* 110443 */ // Label 3344: @110443 |
| 40051 | /* 110443 */ GIM_Reject, |
| 40052 | /* 110444 */ // Label 3308: @110444 |
| 40053 | /* 110444 */ GIM_Try, /*On fail goto*//*Label 3349*/ GIMT_Encode4(110815), |
| 40054 | /* 110449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40055 | /* 110452 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 40056 | /* 110455 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 40057 | /* 110458 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3350*/ GIMT_Encode4(110520), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2891 // |
| 40058 | /* 110465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40059 | /* 110469 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40060 | /* 110473 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40061 | /* 110477 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40062 | /* 110481 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40063 | /* 110486 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40064 | /* 110490 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40065 | /* 110494 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40066 | /* 110496 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 40067 | /* 110496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq), |
| 40068 | /* 110499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40069 | /* 110501 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 40070 | /* 110503 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 40071 | /* 110507 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40072 | /* 110509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40073 | /* 110512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40074 | /* 110518 */ GIR_RootConstrainSelectedInstOperands, |
| 40075 | /* 110519 */ // GIR_Coverage, 2891, |
| 40076 | /* 110519 */ GIR_EraseRootFromParent_Done, |
| 40077 | /* 110520 */ // Label 3350: @110520 |
| 40078 | /* 110520 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3351*/ GIMT_Encode4(110588), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4435 // |
| 40079 | /* 110527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40080 | /* 110531 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40081 | /* 110535 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40082 | /* 110539 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40083 | /* 110543 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40084 | /* 110548 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40085 | /* 110552 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40086 | /* 110556 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40087 | /* 110558 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 40088 | /* 110558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32), |
| 40089 | /* 110561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40090 | /* 110563 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 40091 | /* 110565 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 40092 | /* 110569 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 40093 | /* 110571 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40094 | /* 110574 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40095 | /* 110580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40096 | /* 110586 */ GIR_RootConstrainSelectedInstOperands, |
| 40097 | /* 110587 */ // GIR_Coverage, 4435, |
| 40098 | /* 110587 */ GIR_EraseRootFromParent_Done, |
| 40099 | /* 110588 */ // Label 3351: @110588 |
| 40100 | /* 110588 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3352*/ GIMT_Encode4(110650), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 6394 // |
| 40101 | /* 110595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40102 | /* 110599 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40103 | /* 110603 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 40104 | /* 110607 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40105 | /* 110611 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40106 | /* 110615 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40107 | /* 110620 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40108 | /* 110624 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40109 | /* 110626 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm, (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 40110 | /* 110626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq), |
| 40111 | /* 110629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40112 | /* 110631 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 40113 | /* 110633 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 40114 | /* 110637 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40115 | /* 110639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40116 | /* 110642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40117 | /* 110648 */ GIR_RootConstrainSelectedInstOperands, |
| 40118 | /* 110649 */ // GIR_Coverage, 6394, |
| 40119 | /* 110649 */ GIR_EraseRootFromParent_Done, |
| 40120 | /* 110650 */ // Label 3352: @110650 |
| 40121 | /* 110650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3353*/ GIMT_Encode4(110718), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 6674 // |
| 40122 | /* 110657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40123 | /* 110661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40124 | /* 110665 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 40125 | /* 110669 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40126 | /* 110673 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40127 | /* 110677 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40128 | /* 110682 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40129 | /* 110686 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40130 | /* 110688 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m2, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 40131 | /* 110688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32), |
| 40132 | /* 110691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40133 | /* 110693 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 40134 | /* 110695 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 40135 | /* 110699 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2 |
| 40136 | /* 110701 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40137 | /* 110704 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40138 | /* 110710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40139 | /* 110716 */ GIR_RootConstrainSelectedInstOperands, |
| 40140 | /* 110717 */ // GIR_Coverage, 6674, |
| 40141 | /* 110717 */ GIR_EraseRootFromParent_Done, |
| 40142 | /* 110718 */ // Label 3353: @110718 |
| 40143 | /* 110718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3354*/ GIMT_Encode4(110763), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2889 // |
| 40144 | /* 110725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40145 | /* 110729 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40146 | /* 110733 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40147 | /* 110737 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40148 | /* 110741 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMAfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 40149 | /* 110741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfq), |
| 40150 | /* 110744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40151 | /* 110746 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 40152 | /* 110748 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 40153 | /* 110750 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 40154 | /* 110752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40155 | /* 110755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40156 | /* 110761 */ GIR_RootConstrainSelectedInstOperands, |
| 40157 | /* 110762 */ // GIR_Coverage, 2889, |
| 40158 | /* 110762 */ GIR_EraseRootFromParent_Done, |
| 40159 | /* 110763 */ // Label 3354: @110763 |
| 40160 | /* 110763 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3355*/ GIMT_Encode4(110814), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4441 // |
| 40161 | /* 110770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40162 | /* 110774 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40163 | /* 110778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40164 | /* 110782 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40165 | /* 110786 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 40166 | /* 110786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32), |
| 40167 | /* 110789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40168 | /* 110791 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 40169 | /* 110793 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1 |
| 40170 | /* 110795 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 40171 | /* 110797 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40172 | /* 110800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40173 | /* 110806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40174 | /* 110812 */ GIR_RootConstrainSelectedInstOperands, |
| 40175 | /* 110813 */ // GIR_Coverage, 4441, |
| 40176 | /* 110813 */ GIR_EraseRootFromParent_Done, |
| 40177 | /* 110814 */ // Label 3355: @110814 |
| 40178 | /* 110814 */ GIM_Reject, |
| 40179 | /* 110815 */ // Label 3349: @110815 |
| 40180 | /* 110815 */ GIM_Reject, |
| 40181 | /* 110816 */ // Label 3309: @110816 |
| 40182 | /* 110816 */ GIM_Reject, |
| 40183 | /* 110817 */ // Label 44: @110817 |
| 40184 | /* 110817 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3359*/ GIMT_Encode4(110978), |
| 40185 | /* 110828 */ /*GILLT_s16*//*Label 3356*/ GIMT_Encode4(110840), |
| 40186 | /* 110832 */ /*GILLT_s32*//*Label 3357*/ GIMT_Encode4(110886), |
| 40187 | /* 110836 */ /*GILLT_s64*//*Label 3358*/ GIMT_Encode4(110932), |
| 40188 | /* 110840 */ // Label 3356: @110840 |
| 40189 | /* 110840 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3360*/ GIMT_Encode4(110885), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 633 // |
| 40190 | /* 110847 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40191 | /* 110850 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 40192 | /* 110853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40193 | /* 110857 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40194 | /* 110861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40195 | /* 110865 */ // (fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40196 | /* 110865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH), |
| 40197 | /* 110868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40198 | /* 110870 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 40199 | /* 110872 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 40200 | /* 110874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40201 | /* 110877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40202 | /* 110883 */ GIR_RootConstrainSelectedInstOperands, |
| 40203 | /* 110884 */ // GIR_Coverage, 633, |
| 40204 | /* 110884 */ GIR_EraseRootFromParent_Done, |
| 40205 | /* 110885 */ // Label 3360: @110885 |
| 40206 | /* 110885 */ GIM_Reject, |
| 40207 | /* 110886 */ // Label 3357: @110886 |
| 40208 | /* 110886 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3361*/ GIMT_Encode4(110931), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 631 // |
| 40209 | /* 110893 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40210 | /* 110896 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 40211 | /* 110899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40212 | /* 110903 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40213 | /* 110907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40214 | /* 110911 */ // (fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40215 | /* 110911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS), |
| 40216 | /* 110914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40217 | /* 110916 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 40218 | /* 110918 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 40219 | /* 110920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40220 | /* 110923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40221 | /* 110929 */ GIR_RootConstrainSelectedInstOperands, |
| 40222 | /* 110930 */ // GIR_Coverage, 631, |
| 40223 | /* 110930 */ GIR_EraseRootFromParent_Done, |
| 40224 | /* 110931 */ // Label 3361: @110931 |
| 40225 | /* 110931 */ GIM_Reject, |
| 40226 | /* 110932 */ // Label 3358: @110932 |
| 40227 | /* 110932 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3362*/ GIMT_Encode4(110977), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 629 // |
| 40228 | /* 110939 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40229 | /* 110942 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 40230 | /* 110945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40231 | /* 110949 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40232 | /* 110953 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40233 | /* 110957 */ // (fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40234 | /* 110957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD), |
| 40235 | /* 110960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40236 | /* 110962 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 40237 | /* 110964 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 40238 | /* 110966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40239 | /* 110969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40240 | /* 110975 */ GIR_RootConstrainSelectedInstOperands, |
| 40241 | /* 110976 */ // GIR_Coverage, 629, |
| 40242 | /* 110976 */ GIR_EraseRootFromParent_Done, |
| 40243 | /* 110977 */ // Label 3362: @110977 |
| 40244 | /* 110977 */ GIM_Reject, |
| 40245 | /* 110978 */ // Label 3359: @110978 |
| 40246 | /* 110978 */ GIM_Reject, |
| 40247 | /* 110979 */ // Label 45: @110979 |
| 40248 | /* 110979 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3370*/ GIMT_Encode4(113386), |
| 40249 | /* 110990 */ /*GILLT_s16*//*Label 3363*/ GIMT_Encode4(111042), |
| 40250 | /* 110994 */ /*GILLT_s32*//*Label 3364*/ GIMT_Encode4(111683), |
| 40251 | /* 110998 */ /*GILLT_s64*//*Label 3365*/ GIMT_Encode4(112477), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40252 | /* 111026 */ /*GILLT_v4s16*//*Label 3366*/ GIMT_Encode4(113118), |
| 40253 | /* 111030 */ /*GILLT_v8s16*//*Label 3367*/ GIMT_Encode4(113155), |
| 40254 | /* 111034 */ /*GILLT_v2s32*//*Label 3368*/ GIMT_Encode4(113252), |
| 40255 | /* 111038 */ /*GILLT_v4s32*//*Label 3369*/ GIMT_Encode4(113289), |
| 40256 | /* 111042 */ // Label 3363: @111042 |
| 40257 | /* 111042 */ GIM_Try, /*On fail goto*//*Label 3371*/ GIMT_Encode4(111682), |
| 40258 | /* 111047 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40259 | /* 111050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40260 | /* 111054 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3372*/ GIMT_Encode4(111138), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2795 // |
| 40261 | /* 111061 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40262 | /* 111065 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40263 | /* 111069 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40264 | /* 111073 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40265 | /* 111077 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 40266 | /* 111081 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 40267 | /* 111085 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40268 | /* 111089 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 40269 | /* 111093 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40270 | /* 111098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40271 | /* 111103 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40272 | /* 111108 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40273 | /* 111110 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40274 | /* 111110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 40275 | /* 111113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40276 | /* 111115 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40277 | /* 111119 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40278 | /* 111123 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40279 | /* 111127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40280 | /* 111130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40281 | /* 111136 */ GIR_RootConstrainSelectedInstOperands, |
| 40282 | /* 111137 */ // GIR_Coverage, 2795, |
| 40283 | /* 111137 */ GIR_EraseRootFromParent_Done, |
| 40284 | /* 111138 */ // Label 3372: @111138 |
| 40285 | /* 111138 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3373*/ GIMT_Encode4(111222), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6346 // |
| 40286 | /* 111145 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40287 | /* 111149 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40288 | /* 111153 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40289 | /* 111157 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40290 | /* 111161 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 40291 | /* 111165 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40292 | /* 111170 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40293 | /* 111174 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40294 | /* 111178 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 40295 | /* 111182 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40296 | /* 111187 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40297 | /* 111192 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40298 | /* 111194 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40299 | /* 111194 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 40300 | /* 111197 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40301 | /* 111199 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40302 | /* 111203 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40303 | /* 111207 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 40304 | /* 111211 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40305 | /* 111214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40306 | /* 111220 */ GIR_RootConstrainSelectedInstOperands, |
| 40307 | /* 111221 */ // GIR_Coverage, 6346, |
| 40308 | /* 111221 */ GIR_EraseRootFromParent_Done, |
| 40309 | /* 111222 */ // Label 3373: @111222 |
| 40310 | /* 111222 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3374*/ GIMT_Encode4(111306), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2794 // |
| 40311 | /* 111229 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40312 | /* 111233 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40313 | /* 111237 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40314 | /* 111241 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40315 | /* 111245 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 40316 | /* 111249 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 40317 | /* 111253 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40318 | /* 111257 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 40319 | /* 111261 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40320 | /* 111266 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40321 | /* 111271 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40322 | /* 111276 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40323 | /* 111278 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40324 | /* 111278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 40325 | /* 111281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40326 | /* 111283 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40327 | /* 111287 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40328 | /* 111291 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40329 | /* 111295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40330 | /* 111298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40331 | /* 111304 */ GIR_RootConstrainSelectedInstOperands, |
| 40332 | /* 111305 */ // GIR_Coverage, 2794, |
| 40333 | /* 111305 */ GIR_EraseRootFromParent_Done, |
| 40334 | /* 111306 */ // Label 3374: @111306 |
| 40335 | /* 111306 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3375*/ GIMT_Encode4(111390), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6345 // |
| 40336 | /* 111313 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40337 | /* 111317 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40338 | /* 111321 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40339 | /* 111325 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40340 | /* 111329 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 40341 | /* 111333 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40342 | /* 111338 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40343 | /* 111342 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40344 | /* 111346 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 40345 | /* 111350 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40346 | /* 111355 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40347 | /* 111360 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40348 | /* 111362 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40349 | /* 111362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 40350 | /* 111365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40351 | /* 111367 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40352 | /* 111371 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40353 | /* 111375 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 40354 | /* 111379 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40355 | /* 111382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40356 | /* 111388 */ GIR_RootConstrainSelectedInstOperands, |
| 40357 | /* 111389 */ // GIR_Coverage, 6345, |
| 40358 | /* 111389 */ GIR_EraseRootFromParent_Done, |
| 40359 | /* 111390 */ // Label 3375: @111390 |
| 40360 | /* 111390 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3376*/ GIMT_Encode4(111462), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2769 // |
| 40361 | /* 111397 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40362 | /* 111401 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40363 | /* 111405 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40364 | /* 111409 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40365 | /* 111413 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 40366 | /* 111417 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40367 | /* 111422 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40368 | /* 111427 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40369 | /* 111432 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40370 | /* 111434 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40371 | /* 111434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 40372 | /* 111437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40373 | /* 111439 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40374 | /* 111443 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40375 | /* 111447 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40376 | /* 111451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40377 | /* 111454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40378 | /* 111460 */ GIR_RootConstrainSelectedInstOperands, |
| 40379 | /* 111461 */ // GIR_Coverage, 2769, |
| 40380 | /* 111461 */ GIR_EraseRootFromParent_Done, |
| 40381 | /* 111462 */ // Label 3376: @111462 |
| 40382 | /* 111462 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3377*/ GIMT_Encode4(111534), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2768 // |
| 40383 | /* 111469 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40384 | /* 111473 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40385 | /* 111477 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40386 | /* 111481 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40387 | /* 111485 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 40388 | /* 111489 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40389 | /* 111494 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40390 | /* 111499 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40391 | /* 111504 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40392 | /* 111506 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40393 | /* 111506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 40394 | /* 111509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40395 | /* 111511 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40396 | /* 111515 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40397 | /* 111519 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40398 | /* 111523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40399 | /* 111526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40400 | /* 111532 */ GIR_RootConstrainSelectedInstOperands, |
| 40401 | /* 111533 */ // GIR_Coverage, 2768, |
| 40402 | /* 111533 */ GIR_EraseRootFromParent_Done, |
| 40403 | /* 111534 */ // Label 3377: @111534 |
| 40404 | /* 111534 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3378*/ GIMT_Encode4(111593), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 645 // |
| 40405 | /* 111541 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40406 | /* 111545 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 40407 | /* 111549 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40408 | /* 111553 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40409 | /* 111557 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40410 | /* 111562 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40411 | /* 111567 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40412 | /* 111569 */ // (fneg:{ *:[f16] } (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40413 | /* 111569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH), |
| 40414 | /* 111572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40415 | /* 111574 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40416 | /* 111578 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40417 | /* 111582 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40418 | /* 111585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40419 | /* 111591 */ GIR_RootConstrainSelectedInstOperands, |
| 40420 | /* 111592 */ // GIR_Coverage, 645, |
| 40421 | /* 111592 */ GIR_EraseRootFromParent_Done, |
| 40422 | /* 111593 */ // Label 3378: @111593 |
| 40423 | /* 111593 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3379*/ GIMT_Encode4(111652), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 644 // |
| 40424 | /* 111600 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40425 | /* 111604 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL), |
| 40426 | /* 111608 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40427 | /* 111612 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40428 | /* 111616 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40429 | /* 111621 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40430 | /* 111626 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40431 | /* 111628 */ // (fneg:{ *:[f16] } (strict_fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40432 | /* 111628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH), |
| 40433 | /* 111631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40434 | /* 111633 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40435 | /* 111637 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40436 | /* 111641 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40437 | /* 111644 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40438 | /* 111650 */ GIR_RootConstrainSelectedInstOperands, |
| 40439 | /* 111651 */ // GIR_Coverage, 644, |
| 40440 | /* 111651 */ GIR_EraseRootFromParent_Done, |
| 40441 | /* 111652 */ // Label 3379: @111652 |
| 40442 | /* 111652 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3380*/ GIMT_Encode4(111681), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 691 // |
| 40443 | /* 111659 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40444 | /* 111663 */ // (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VNEGH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 40445 | /* 111663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGH), |
| 40446 | /* 111666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40447 | /* 111668 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 40448 | /* 111670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40449 | /* 111673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40450 | /* 111679 */ GIR_RootConstrainSelectedInstOperands, |
| 40451 | /* 111680 */ // GIR_Coverage, 691, |
| 40452 | /* 111680 */ GIR_EraseRootFromParent_Done, |
| 40453 | /* 111681 */ // Label 3380: @111681 |
| 40454 | /* 111681 */ GIM_Reject, |
| 40455 | /* 111682 */ // Label 3371: @111682 |
| 40456 | /* 111682 */ GIM_Reject, |
| 40457 | /* 111683 */ // Label 3364: @111683 |
| 40458 | /* 111683 */ GIM_Try, /*On fail goto*//*Label 3381*/ GIMT_Encode4(112476), |
| 40459 | /* 111688 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40460 | /* 111691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40461 | /* 111695 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3382*/ GIMT_Encode4(111779), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2793 // |
| 40462 | /* 111702 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40463 | /* 111706 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40464 | /* 111710 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40465 | /* 111714 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40466 | /* 111718 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 40467 | /* 111722 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 40468 | /* 111726 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40469 | /* 111730 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 40470 | /* 111734 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40471 | /* 111739 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40472 | /* 111744 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40473 | /* 111749 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40474 | /* 111751 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40475 | /* 111751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 40476 | /* 111754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40477 | /* 111756 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40478 | /* 111760 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40479 | /* 111764 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40480 | /* 111768 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40481 | /* 111771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40482 | /* 111777 */ GIR_RootConstrainSelectedInstOperands, |
| 40483 | /* 111778 */ // GIR_Coverage, 2793, |
| 40484 | /* 111778 */ GIR_EraseRootFromParent_Done, |
| 40485 | /* 111779 */ // Label 3382: @111779 |
| 40486 | /* 111779 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3383*/ GIMT_Encode4(111863), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6344 // |
| 40487 | /* 111786 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40488 | /* 111790 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40489 | /* 111794 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40490 | /* 111798 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40491 | /* 111802 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 40492 | /* 111806 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40493 | /* 111811 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40494 | /* 111815 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40495 | /* 111819 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 40496 | /* 111823 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40497 | /* 111828 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40498 | /* 111833 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40499 | /* 111835 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40500 | /* 111835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 40501 | /* 111838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40502 | /* 111840 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40503 | /* 111844 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40504 | /* 111848 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 40505 | /* 111852 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40506 | /* 111855 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40507 | /* 111861 */ GIR_RootConstrainSelectedInstOperands, |
| 40508 | /* 111862 */ // GIR_Coverage, 6344, |
| 40509 | /* 111862 */ GIR_EraseRootFromParent_Done, |
| 40510 | /* 111863 */ // Label 3383: @111863 |
| 40511 | /* 111863 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3384*/ GIMT_Encode4(111947), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2792 // |
| 40512 | /* 111870 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40513 | /* 111874 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40514 | /* 111878 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40515 | /* 111882 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40516 | /* 111886 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 40517 | /* 111890 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 40518 | /* 111894 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40519 | /* 111898 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 40520 | /* 111902 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40521 | /* 111907 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40522 | /* 111912 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40523 | /* 111917 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40524 | /* 111919 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40525 | /* 111919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 40526 | /* 111922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40527 | /* 111924 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40528 | /* 111928 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40529 | /* 111932 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40530 | /* 111936 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40531 | /* 111939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40532 | /* 111945 */ GIR_RootConstrainSelectedInstOperands, |
| 40533 | /* 111946 */ // GIR_Coverage, 2792, |
| 40534 | /* 111946 */ GIR_EraseRootFromParent_Done, |
| 40535 | /* 111947 */ // Label 3384: @111947 |
| 40536 | /* 111947 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3385*/ GIMT_Encode4(112031), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6343 // |
| 40537 | /* 111954 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40538 | /* 111958 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40539 | /* 111962 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40540 | /* 111966 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40541 | /* 111970 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 40542 | /* 111974 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40543 | /* 111979 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40544 | /* 111983 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40545 | /* 111987 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 40546 | /* 111991 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40547 | /* 111996 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40548 | /* 112001 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40549 | /* 112003 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40550 | /* 112003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 40551 | /* 112006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40552 | /* 112008 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40553 | /* 112012 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40554 | /* 112016 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 40555 | /* 112020 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40556 | /* 112023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40557 | /* 112029 */ GIR_RootConstrainSelectedInstOperands, |
| 40558 | /* 112030 */ // GIR_Coverage, 6343, |
| 40559 | /* 112030 */ GIR_EraseRootFromParent_Done, |
| 40560 | /* 112031 */ // Label 3385: @112031 |
| 40561 | /* 112031 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3386*/ GIMT_Encode4(112103), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2767 // |
| 40562 | /* 112038 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40563 | /* 112042 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40564 | /* 112046 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40565 | /* 112050 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40566 | /* 112054 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 40567 | /* 112058 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40568 | /* 112063 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40569 | /* 112068 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40570 | /* 112073 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40571 | /* 112075 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40572 | /* 112075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 40573 | /* 112078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40574 | /* 112080 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40575 | /* 112084 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40576 | /* 112088 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40577 | /* 112092 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40578 | /* 112095 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40579 | /* 112101 */ GIR_RootConstrainSelectedInstOperands, |
| 40580 | /* 112102 */ // GIR_Coverage, 2767, |
| 40581 | /* 112102 */ GIR_EraseRootFromParent_Done, |
| 40582 | /* 112103 */ // Label 3386: @112103 |
| 40583 | /* 112103 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3387*/ GIMT_Encode4(112175), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2766 // |
| 40584 | /* 112110 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40585 | /* 112114 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40586 | /* 112118 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40587 | /* 112122 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40588 | /* 112126 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 40589 | /* 112130 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40590 | /* 112135 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40591 | /* 112140 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40592 | /* 112145 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40593 | /* 112147 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40594 | /* 112147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 40595 | /* 112150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40596 | /* 112152 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40597 | /* 112156 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40598 | /* 112160 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40599 | /* 112164 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40600 | /* 112167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40601 | /* 112173 */ GIR_RootConstrainSelectedInstOperands, |
| 40602 | /* 112174 */ // GIR_Coverage, 2766, |
| 40603 | /* 112174 */ GIR_EraseRootFromParent_Done, |
| 40604 | /* 112175 */ // Label 3387: @112175 |
| 40605 | /* 112175 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3388*/ GIMT_Encode4(112234), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 643 // |
| 40606 | /* 112182 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40607 | /* 112186 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 40608 | /* 112190 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40609 | /* 112194 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40610 | /* 112198 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40611 | /* 112203 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40612 | /* 112208 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40613 | /* 112210 */ // (fneg:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40614 | /* 112210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 40615 | /* 112213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40616 | /* 112215 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40617 | /* 112219 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40618 | /* 112223 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40619 | /* 112226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40620 | /* 112232 */ GIR_RootConstrainSelectedInstOperands, |
| 40621 | /* 112233 */ // GIR_Coverage, 643, |
| 40622 | /* 112233 */ GIR_EraseRootFromParent_Done, |
| 40623 | /* 112234 */ // Label 3388: @112234 |
| 40624 | /* 112234 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3389*/ GIMT_Encode4(112293), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 642 // |
| 40625 | /* 112241 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40626 | /* 112245 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL), |
| 40627 | /* 112249 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40628 | /* 112253 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40629 | /* 112257 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40630 | /* 112262 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40631 | /* 112267 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40632 | /* 112269 */ // (fneg:{ *:[f32] } (strict_fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40633 | /* 112269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 40634 | /* 112272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40635 | /* 112274 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40636 | /* 112278 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40637 | /* 112282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40638 | /* 112285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40639 | /* 112291 */ GIR_RootConstrainSelectedInstOperands, |
| 40640 | /* 112292 */ // GIR_Coverage, 642, |
| 40641 | /* 112292 */ GIR_EraseRootFromParent_Done, |
| 40642 | /* 112293 */ // Label 3389: @112293 |
| 40643 | /* 112293 */ GIM_Try, /*On fail goto*//*Label 3390*/ GIMT_Encode4(112475), |
| 40644 | /* 112298 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40645 | /* 112302 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3391*/ GIMT_Encode4(112327), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 690 // |
| 40646 | /* 112309 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VNEGS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 40647 | /* 112309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGS), |
| 40648 | /* 112312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40649 | /* 112314 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 40650 | /* 112316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40651 | /* 112319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40652 | /* 112325 */ GIR_RootConstrainSelectedInstOperands, |
| 40653 | /* 112326 */ // GIR_Coverage, 690, |
| 40654 | /* 112326 */ GIR_EraseRootFromParent_Done, |
| 40655 | /* 112327 */ // Label 3391: @112327 |
| 40656 | /* 112327 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3392*/ GIMT_Encode4(112474), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3094 // |
| 40657 | /* 112334 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VNEGfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 40658 | /* 112334 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 40659 | /* 112337 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40660 | /* 112341 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40661 | /* 112346 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 40662 | /* 112348 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 40663 | /* 112351 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40664 | /* 112355 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40665 | /* 112360 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 40666 | /* 112363 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40667 | /* 112368 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 40668 | /* 112371 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 40669 | /* 112375 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40670 | /* 112380 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 40671 | /* 112383 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 40672 | /* 112387 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 40673 | /* 112390 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40674 | /* 112395 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40675 | /* 112400 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 40676 | /* 112405 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 40677 | /* 112408 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VNEGfd), |
| 40678 | /* 112412 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40679 | /* 112417 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 40680 | /* 112420 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 40681 | /* 112423 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40682 | /* 112429 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 40683 | /* 112431 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 40684 | /* 112434 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40685 | /* 112438 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40686 | /* 112443 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 40687 | /* 112446 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40688 | /* 112451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40689 | /* 112454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40690 | /* 112456 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 40691 | /* 112463 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 40692 | /* 112468 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40693 | /* 112473 */ // GIR_Coverage, 3094, |
| 40694 | /* 112473 */ GIR_EraseRootFromParent_Done, |
| 40695 | /* 112474 */ // Label 3392: @112474 |
| 40696 | /* 112474 */ GIM_Reject, |
| 40697 | /* 112475 */ // Label 3390: @112475 |
| 40698 | /* 112475 */ GIM_Reject, |
| 40699 | /* 112476 */ // Label 3381: @112476 |
| 40700 | /* 112476 */ GIM_Reject, |
| 40701 | /* 112477 */ // Label 3365: @112477 |
| 40702 | /* 112477 */ GIM_Try, /*On fail goto*//*Label 3393*/ GIMT_Encode4(113117), |
| 40703 | /* 112482 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40704 | /* 112485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40705 | /* 112489 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3394*/ GIMT_Encode4(112573), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2791 // |
| 40706 | /* 112496 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40707 | /* 112500 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40708 | /* 112504 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40709 | /* 112508 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40710 | /* 112512 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 40711 | /* 112516 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 40712 | /* 112520 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40713 | /* 112524 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 40714 | /* 112528 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40715 | /* 112533 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40716 | /* 112538 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40717 | /* 112543 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40718 | /* 112545 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40719 | /* 112545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 40720 | /* 112548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40721 | /* 112550 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 40722 | /* 112554 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 40723 | /* 112558 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 40724 | /* 112562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40725 | /* 112565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40726 | /* 112571 */ GIR_RootConstrainSelectedInstOperands, |
| 40727 | /* 112572 */ // GIR_Coverage, 2791, |
| 40728 | /* 112572 */ GIR_EraseRootFromParent_Done, |
| 40729 | /* 112573 */ // Label 3394: @112573 |
| 40730 | /* 112573 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3395*/ GIMT_Encode4(112657), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6342 // |
| 40731 | /* 112580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40732 | /* 112584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40733 | /* 112588 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40734 | /* 112592 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40735 | /* 112596 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 40736 | /* 112600 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40737 | /* 112605 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40738 | /* 112609 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40739 | /* 112613 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 40740 | /* 112617 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40741 | /* 112622 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40742 | /* 112627 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40743 | /* 112629 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40744 | /* 112629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 40745 | /* 112632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40746 | /* 112634 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 40747 | /* 112638 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 40748 | /* 112642 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm |
| 40749 | /* 112646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40750 | /* 112649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40751 | /* 112655 */ GIR_RootConstrainSelectedInstOperands, |
| 40752 | /* 112656 */ // GIR_Coverage, 6342, |
| 40753 | /* 112656 */ GIR_EraseRootFromParent_Done, |
| 40754 | /* 112657 */ // Label 3395: @112657 |
| 40755 | /* 112657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3396*/ GIMT_Encode4(112741), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2790 // |
| 40756 | /* 112664 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40757 | /* 112668 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40758 | /* 112672 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40759 | /* 112676 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40760 | /* 112680 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 40761 | /* 112684 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 40762 | /* 112688 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40763 | /* 112692 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 40764 | /* 112696 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40765 | /* 112701 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40766 | /* 112706 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40767 | /* 112711 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40768 | /* 112713 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40769 | /* 112713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 40770 | /* 112716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40771 | /* 112718 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 40772 | /* 112722 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 40773 | /* 112726 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 40774 | /* 112730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40775 | /* 112733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40776 | /* 112739 */ GIR_RootConstrainSelectedInstOperands, |
| 40777 | /* 112740 */ // GIR_Coverage, 2790, |
| 40778 | /* 112740 */ GIR_EraseRootFromParent_Done, |
| 40779 | /* 112741 */ // Label 3396: @112741 |
| 40780 | /* 112741 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3397*/ GIMT_Encode4(112825), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6341 // |
| 40781 | /* 112748 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40782 | /* 112752 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40783 | /* 112756 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40784 | /* 112760 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40785 | /* 112764 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 40786 | /* 112768 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40787 | /* 112773 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40788 | /* 112777 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40789 | /* 112781 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 40790 | /* 112785 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40791 | /* 112790 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40792 | /* 112795 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40793 | /* 112797 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40794 | /* 112797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 40795 | /* 112800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40796 | /* 112802 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 40797 | /* 112806 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 40798 | /* 112810 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm |
| 40799 | /* 112814 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40800 | /* 112817 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40801 | /* 112823 */ GIR_RootConstrainSelectedInstOperands, |
| 40802 | /* 112824 */ // GIR_Coverage, 6341, |
| 40803 | /* 112824 */ GIR_EraseRootFromParent_Done, |
| 40804 | /* 112825 */ // Label 3397: @112825 |
| 40805 | /* 112825 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3398*/ GIMT_Encode4(112897), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2765 // |
| 40806 | /* 112832 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40807 | /* 112836 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40808 | /* 112840 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40809 | /* 112844 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40810 | /* 112848 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 40811 | /* 112852 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40812 | /* 112857 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40813 | /* 112862 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40814 | /* 112867 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40815 | /* 112869 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40816 | /* 112869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 40817 | /* 112872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40818 | /* 112874 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 40819 | /* 112878 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 40820 | /* 112882 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 40821 | /* 112886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40822 | /* 112889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40823 | /* 112895 */ GIR_RootConstrainSelectedInstOperands, |
| 40824 | /* 112896 */ // GIR_Coverage, 2765, |
| 40825 | /* 112896 */ GIR_EraseRootFromParent_Done, |
| 40826 | /* 112897 */ // Label 3398: @112897 |
| 40827 | /* 112897 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3399*/ GIMT_Encode4(112969), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2764 // |
| 40828 | /* 112904 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40829 | /* 112908 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40830 | /* 112912 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40831 | /* 112916 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40832 | /* 112920 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 40833 | /* 112924 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40834 | /* 112929 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40835 | /* 112934 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40836 | /* 112939 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40837 | /* 112941 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40838 | /* 112941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 40839 | /* 112944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40840 | /* 112946 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 40841 | /* 112950 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 40842 | /* 112954 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 40843 | /* 112958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40844 | /* 112961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40845 | /* 112967 */ GIR_RootConstrainSelectedInstOperands, |
| 40846 | /* 112968 */ // GIR_Coverage, 2764, |
| 40847 | /* 112968 */ GIR_EraseRootFromParent_Done, |
| 40848 | /* 112969 */ // Label 3399: @112969 |
| 40849 | /* 112969 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3400*/ GIMT_Encode4(113028), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 641 // |
| 40850 | /* 112976 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40851 | /* 112980 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 40852 | /* 112984 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40853 | /* 112988 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40854 | /* 112992 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40855 | /* 112997 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40856 | /* 113002 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40857 | /* 113004 */ // (fneg:{ *:[f64] } (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40858 | /* 113004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 40859 | /* 113007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40860 | /* 113009 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 40861 | /* 113013 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 40862 | /* 113017 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40863 | /* 113020 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40864 | /* 113026 */ GIR_RootConstrainSelectedInstOperands, |
| 40865 | /* 113027 */ // GIR_Coverage, 641, |
| 40866 | /* 113027 */ GIR_EraseRootFromParent_Done, |
| 40867 | /* 113028 */ // Label 3400: @113028 |
| 40868 | /* 113028 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3401*/ GIMT_Encode4(113087), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 640 // |
| 40869 | /* 113035 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40870 | /* 113039 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL), |
| 40871 | /* 113043 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40872 | /* 113047 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40873 | /* 113051 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40874 | /* 113056 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40875 | /* 113061 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40876 | /* 113063 */ // (fneg:{ *:[f64] } (strict_fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40877 | /* 113063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 40878 | /* 113066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40879 | /* 113068 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 40880 | /* 113072 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 40881 | /* 113076 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40882 | /* 113079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40883 | /* 113085 */ GIR_RootConstrainSelectedInstOperands, |
| 40884 | /* 113086 */ // GIR_Coverage, 640, |
| 40885 | /* 113086 */ GIR_EraseRootFromParent_Done, |
| 40886 | /* 113087 */ // Label 3401: @113087 |
| 40887 | /* 113087 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3402*/ GIMT_Encode4(113116), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 689 // |
| 40888 | /* 113094 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40889 | /* 113098 */ // (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VNEGD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 40890 | /* 113098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGD), |
| 40891 | /* 113101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40892 | /* 113103 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 40893 | /* 113105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40894 | /* 113108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40895 | /* 113114 */ GIR_RootConstrainSelectedInstOperands, |
| 40896 | /* 113115 */ // GIR_Coverage, 689, |
| 40897 | /* 113115 */ GIR_EraseRootFromParent_Done, |
| 40898 | /* 113116 */ // Label 3402: @113116 |
| 40899 | /* 113116 */ GIM_Reject, |
| 40900 | /* 113117 */ // Label 3393: @113117 |
| 40901 | /* 113117 */ GIM_Reject, |
| 40902 | /* 113118 */ // Label 3366: @113118 |
| 40903 | /* 113118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3403*/ GIMT_Encode4(113154), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1694 // |
| 40904 | /* 113125 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 40905 | /* 113128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40906 | /* 113132 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40907 | /* 113136 */ // (fneg:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VNEGhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 40908 | /* 113136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhd), |
| 40909 | /* 113139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40910 | /* 113141 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40911 | /* 113143 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40912 | /* 113146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40913 | /* 113152 */ GIR_RootConstrainSelectedInstOperands, |
| 40914 | /* 113153 */ // GIR_Coverage, 1694, |
| 40915 | /* 113153 */ GIR_EraseRootFromParent_Done, |
| 40916 | /* 113154 */ // Label 3403: @113154 |
| 40917 | /* 113154 */ GIM_Reject, |
| 40918 | /* 113155 */ // Label 3367: @113155 |
| 40919 | /* 113155 */ GIM_Try, /*On fail goto*//*Label 3404*/ GIMT_Encode4(113251), |
| 40920 | /* 113160 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 40921 | /* 113163 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3405*/ GIMT_Encode4(113196), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1695 // |
| 40922 | /* 113170 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40923 | /* 113174 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40924 | /* 113178 */ // (fneg:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VNEGhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 40925 | /* 113178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhq), |
| 40926 | /* 113181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40927 | /* 113183 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40928 | /* 113185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40929 | /* 113188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40930 | /* 113194 */ GIR_RootConstrainSelectedInstOperands, |
| 40931 | /* 113195 */ // GIR_Coverage, 1695, |
| 40932 | /* 113195 */ GIR_EraseRootFromParent_Done, |
| 40933 | /* 113196 */ // Label 3405: @113196 |
| 40934 | /* 113196 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3406*/ GIMT_Encode4(113250), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4573 // |
| 40935 | /* 113203 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40936 | /* 113207 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40937 | /* 113211 */ // (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VNEGf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v) |
| 40938 | /* 113211 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40939 | /* 113214 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40940 | /* 113218 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40941 | /* 113223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf16), |
| 40942 | /* 113226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40943 | /* 113228 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 40944 | /* 113230 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40945 | /* 113233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40946 | /* 113239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40947 | /* 113245 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40948 | /* 113248 */ GIR_RootConstrainSelectedInstOperands, |
| 40949 | /* 113249 */ // GIR_Coverage, 4573, |
| 40950 | /* 113249 */ GIR_EraseRootFromParent_Done, |
| 40951 | /* 113250 */ // Label 3406: @113250 |
| 40952 | /* 113250 */ GIM_Reject, |
| 40953 | /* 113251 */ // Label 3404: @113251 |
| 40954 | /* 113251 */ GIM_Reject, |
| 40955 | /* 113252 */ // Label 3368: @113252 |
| 40956 | /* 113252 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3407*/ GIMT_Encode4(113288), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1692 // |
| 40957 | /* 113259 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 40958 | /* 113262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40959 | /* 113266 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40960 | /* 113270 */ // (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VNEGfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 40961 | /* 113270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGfd), |
| 40962 | /* 113273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40963 | /* 113275 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40964 | /* 113277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40965 | /* 113280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40966 | /* 113286 */ GIR_RootConstrainSelectedInstOperands, |
| 40967 | /* 113287 */ // GIR_Coverage, 1692, |
| 40968 | /* 113287 */ GIR_EraseRootFromParent_Done, |
| 40969 | /* 113288 */ // Label 3407: @113288 |
| 40970 | /* 113288 */ GIM_Reject, |
| 40971 | /* 113289 */ // Label 3369: @113289 |
| 40972 | /* 113289 */ GIM_Try, /*On fail goto*//*Label 3408*/ GIMT_Encode4(113385), |
| 40973 | /* 113294 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40974 | /* 113297 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3409*/ GIMT_Encode4(113330), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1693 // |
| 40975 | /* 113304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40976 | /* 113308 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40977 | /* 113312 */ // (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VNEGf32q:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 40978 | /* 113312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGf32q), |
| 40979 | /* 113315 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40980 | /* 113317 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40981 | /* 113319 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40982 | /* 113322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40983 | /* 113328 */ GIR_RootConstrainSelectedInstOperands, |
| 40984 | /* 113329 */ // GIR_Coverage, 1693, |
| 40985 | /* 113329 */ GIR_EraseRootFromParent_Done, |
| 40986 | /* 113330 */ // Label 3409: @113330 |
| 40987 | /* 113330 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3410*/ GIMT_Encode4(113384), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4575 // |
| 40988 | /* 113337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40989 | /* 113341 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40990 | /* 113345 */ // (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VNEGf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v) |
| 40991 | /* 113345 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40992 | /* 113348 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40993 | /* 113352 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40994 | /* 113357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf32), |
| 40995 | /* 113360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40996 | /* 113362 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 40997 | /* 113364 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40998 | /* 113367 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40999 | /* 113373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41000 | /* 113379 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41001 | /* 113382 */ GIR_RootConstrainSelectedInstOperands, |
| 41002 | /* 113383 */ // GIR_Coverage, 4575, |
| 41003 | /* 113383 */ GIR_EraseRootFromParent_Done, |
| 41004 | /* 113384 */ // Label 3410: @113384 |
| 41005 | /* 113384 */ GIM_Reject, |
| 41006 | /* 113385 */ // Label 3408: @113385 |
| 41007 | /* 113385 */ GIM_Reject, |
| 41008 | /* 113386 */ // Label 3370: @113386 |
| 41009 | /* 113386 */ GIM_Reject, |
| 41010 | /* 113387 */ // Label 46: @113387 |
| 41011 | /* 113387 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3414*/ GIMT_Encode4(113650), |
| 41012 | /* 113398 */ /*GILLT_s32*//*Label 3411*/ GIMT_Encode4(113446), |
| 41013 | /* 113402 */ /*GILLT_s64*//*Label 3412*/ GIMT_Encode4(113505), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41014 | /* 113442 */ /*GILLT_v4s32*//*Label 3413*/ GIMT_Encode4(113615), |
| 41015 | /* 113446 */ // Label 3411: @113446 |
| 41016 | /* 113446 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3415*/ GIMT_Encode4(113504), GIMT_Encode2(GIFBS_HasFP16), // Rule ID 2504 // |
| 41017 | /* 113453 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 41018 | /* 113456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41019 | /* 113460 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41020 | /* 113464 */ // (fpextend:{ *:[f32] } HPR:{ *:[f16] }:$Sm) => (VCVTBHS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] })) |
| 41021 | /* 113464 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41022 | /* 113467 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41023 | /* 113471 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41024 | /* 113476 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm |
| 41025 | /* 113480 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41026 | /* 113485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHS), |
| 41027 | /* 113488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 41028 | /* 113490 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41029 | /* 113493 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41030 | /* 113496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41031 | /* 113502 */ GIR_RootConstrainSelectedInstOperands, |
| 41032 | /* 113503 */ // GIR_Coverage, 2504, |
| 41033 | /* 113503 */ GIR_EraseRootFromParent_Done, |
| 41034 | /* 113504 */ // Label 3415: @113504 |
| 41035 | /* 113504 */ GIM_Reject, |
| 41036 | /* 113505 */ // Label 3412: @113505 |
| 41037 | /* 113505 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 3418*/ GIMT_Encode4(113614), |
| 41038 | /* 113516 */ /*GILLT_s16*//*Label 3416*/ GIMT_Encode4(113524), |
| 41039 | /* 113520 */ /*GILLT_s32*//*Label 3417*/ GIMT_Encode4(113580), |
| 41040 | /* 113524 */ // Label 3416: @113524 |
| 41041 | /* 113524 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3419*/ GIMT_Encode4(113579), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2524 // |
| 41042 | /* 113531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41043 | /* 113535 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41044 | /* 113539 */ // (fpextend:{ *:[f64] } HPR:{ *:[f16] }:$Sm) => (VCVTBHD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] })) |
| 41045 | /* 113539 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41046 | /* 113542 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41047 | /* 113546 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41048 | /* 113551 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm |
| 41049 | /* 113555 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41050 | /* 113560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHD), |
| 41051 | /* 113563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 41052 | /* 113565 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41053 | /* 113568 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41054 | /* 113571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41055 | /* 113577 */ GIR_RootConstrainSelectedInstOperands, |
| 41056 | /* 113578 */ // GIR_Coverage, 2524, |
| 41057 | /* 113578 */ GIR_EraseRootFromParent_Done, |
| 41058 | /* 113579 */ // Label 3419: @113579 |
| 41059 | /* 113579 */ GIM_Reject, |
| 41060 | /* 113580 */ // Label 3417: @113580 |
| 41061 | /* 113580 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3420*/ GIMT_Encode4(113613), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 686 // |
| 41062 | /* 113587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41063 | /* 113591 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41064 | /* 113595 */ // (fpextend:{ *:[f64] } SPR:{ *:[f32] }:$Sm) => (VCVTDS:{ *:[f64] } SPR:{ *:[f32] }:$Sm) |
| 41065 | /* 113595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTDS), |
| 41066 | /* 113598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 41067 | /* 113600 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 41068 | /* 113602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41069 | /* 113605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41070 | /* 113611 */ GIR_RootConstrainSelectedInstOperands, |
| 41071 | /* 113612 */ // GIR_Coverage, 686, |
| 41072 | /* 113612 */ GIR_EraseRootFromParent_Done, |
| 41073 | /* 113613 */ // Label 3420: @113613 |
| 41074 | /* 113613 */ GIM_Reject, |
| 41075 | /* 113614 */ // Label 3418: @113614 |
| 41076 | /* 113614 */ GIM_Reject, |
| 41077 | /* 113615 */ // Label 3413: @113615 |
| 41078 | /* 113615 */ GIM_Try, /*On fail goto*//*Label 3421*/ GIMT_Encode4(113649), // Rule ID 3059 // |
| 41079 | /* 113620 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41080 | /* 113623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41081 | /* 113627 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41082 | /* 113631 */ // (fpextend:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src) |
| 41083 | /* 113631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f), |
| 41084 | /* 113634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41085 | /* 113636 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41086 | /* 113638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41087 | /* 113641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41088 | /* 113647 */ GIR_RootConstrainSelectedInstOperands, |
| 41089 | /* 113648 */ // GIR_Coverage, 3059, |
| 41090 | /* 113648 */ GIR_EraseRootFromParent_Done, |
| 41091 | /* 113649 */ // Label 3421: @113649 |
| 41092 | /* 113649 */ GIM_Reject, |
| 41093 | /* 113650 */ // Label 3414: @113650 |
| 41094 | /* 113650 */ GIM_Reject, |
| 41095 | /* 113651 */ // Label 47: @113651 |
| 41096 | /* 113651 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(10), /*)*//*default:*//*Label 3425*/ GIMT_Encode4(113942), |
| 41097 | /* 113662 */ /*GILLT_s16*//*Label 3422*/ GIMT_Encode4(113702), |
| 41098 | /* 113666 */ /*GILLT_s32*//*Label 3423*/ GIMT_Encode4(113870), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41099 | /* 113698 */ /*GILLT_v4s16*//*Label 3424*/ GIMT_Encode4(113907), |
| 41100 | /* 113702 */ // Label 3422: @113702 |
| 41101 | /* 113702 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 3428*/ GIMT_Encode4(113869), |
| 41102 | /* 113713 */ /*GILLT_s32*//*Label 3426*/ GIMT_Encode4(113721), |
| 41103 | /* 113717 */ /*GILLT_s64*//*Label 3427*/ GIMT_Encode4(113795), |
| 41104 | /* 113721 */ // Label 3426: @113721 |
| 41105 | /* 113721 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3429*/ GIMT_Encode4(113794), GIMT_Encode2(GIFBS_HasFP16), // Rule ID 2508 // |
| 41106 | /* 113728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41107 | /* 113732 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41108 | /* 113736 */ // (fpround:{ *:[f16] } SPR:{ *:[f32] }:$Sm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBSH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), SPR:{ *:[f32] }:$Sm), HPR:{ *:[i32] }) |
| 41109 | /* 113736 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 41110 | /* 113739 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41111 | /* 113743 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41112 | /* 113748 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41113 | /* 113750 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41114 | /* 113753 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBSH), |
| 41115 | /* 113757 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41116 | /* 113762 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41117 | /* 113765 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm |
| 41118 | /* 113769 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41119 | /* 113772 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41120 | /* 113778 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41121 | /* 113780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41122 | /* 113783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41123 | /* 113785 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41124 | /* 113788 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 41125 | /* 113793 */ // GIR_Coverage, 2508, |
| 41126 | /* 113793 */ GIR_EraseRootFromParent_Done, |
| 41127 | /* 113794 */ // Label 3429: @113794 |
| 41128 | /* 113794 */ GIM_Reject, |
| 41129 | /* 113795 */ // Label 3427: @113795 |
| 41130 | /* 113795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3430*/ GIMT_Encode4(113868), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2528 // |
| 41131 | /* 113802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41132 | /* 113806 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41133 | /* 113810 */ // (fpround:{ *:[f16] } DPR:{ *:[f64] }:$Dm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBDH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), DPR:{ *:[f64] }:$Dm), HPR:{ *:[i32] }) |
| 41134 | /* 113810 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 41135 | /* 113813 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41136 | /* 113817 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41137 | /* 113822 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 41138 | /* 113824 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41139 | /* 113827 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBDH), |
| 41140 | /* 113831 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41141 | /* 113836 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41142 | /* 113839 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dm |
| 41143 | /* 113843 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41144 | /* 113846 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41145 | /* 113852 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41146 | /* 113854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41147 | /* 113857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41148 | /* 113859 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41149 | /* 113862 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 41150 | /* 113867 */ // GIR_Coverage, 2528, |
| 41151 | /* 113867 */ GIR_EraseRootFromParent_Done, |
| 41152 | /* 113868 */ // Label 3430: @113868 |
| 41153 | /* 113868 */ GIM_Reject, |
| 41154 | /* 113869 */ // Label 3428: @113869 |
| 41155 | /* 113869 */ GIM_Reject, |
| 41156 | /* 113870 */ // Label 3423: @113870 |
| 41157 | /* 113870 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3431*/ GIMT_Encode4(113906), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 688 // |
| 41158 | /* 113877 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 41159 | /* 113880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41160 | /* 113884 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41161 | /* 113888 */ // (fpround:{ *:[f32] } DPR:{ *:[f64] }:$Dm) => (VCVTSD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) |
| 41162 | /* 113888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTSD), |
| 41163 | /* 113891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 41164 | /* 113893 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 41165 | /* 113895 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41166 | /* 113898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41167 | /* 113904 */ GIR_RootConstrainSelectedInstOperands, |
| 41168 | /* 113905 */ // GIR_Coverage, 688, |
| 41169 | /* 113905 */ GIR_EraseRootFromParent_Done, |
| 41170 | /* 113906 */ // Label 3431: @113906 |
| 41171 | /* 113906 */ GIM_Reject, |
| 41172 | /* 113907 */ // Label 3424: @113907 |
| 41173 | /* 113907 */ GIM_Try, /*On fail goto*//*Label 3432*/ GIMT_Encode4(113941), // Rule ID 3058 // |
| 41174 | /* 113912 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41175 | /* 113915 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41176 | /* 113919 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41177 | /* 113923 */ // (fpround:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src) => (VCVTf2h:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src) |
| 41178 | /* 113923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h), |
| 41179 | /* 113926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41180 | /* 113928 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41181 | /* 113930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41182 | /* 113933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41183 | /* 113939 */ GIR_RootConstrainSelectedInstOperands, |
| 41184 | /* 113940 */ // GIR_Coverage, 3058, |
| 41185 | /* 113940 */ GIR_EraseRootFromParent_Done, |
| 41186 | /* 113941 */ // Label 3432: @113941 |
| 41187 | /* 113941 */ GIM_Reject, |
| 41188 | /* 113942 */ // Label 3425: @113942 |
| 41189 | /* 113942 */ GIM_Reject, |
| 41190 | /* 113943 */ // Label 48: @113943 |
| 41191 | /* 113943 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3440*/ GIMT_Encode4(115224), |
| 41192 | /* 113954 */ /*GILLT_s32*//*Label 3433*/ GIMT_Encode4(114002), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41193 | /* 113966 */ /*GILLT_v4s1*//*Label 3434*/ GIMT_Encode4(114852), |
| 41194 | /* 113970 */ /*GILLT_v8s1*//*Label 3435*/ GIMT_Encode4(114904), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41195 | /* 113986 */ /*GILLT_v4s16*//*Label 3436*/ GIMT_Encode4(114956), |
| 41196 | /* 113990 */ /*GILLT_v8s16*//*Label 3437*/ GIMT_Encode4(114993), |
| 41197 | /* 113994 */ /*GILLT_v2s32*//*Label 3438*/ GIMT_Encode4(115090), |
| 41198 | /* 113998 */ /*GILLT_v4s32*//*Label 3439*/ GIMT_Encode4(115127), |
| 41199 | /* 114002 */ // Label 3433: @114002 |
| 41200 | /* 114002 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3444*/ GIMT_Encode4(114851), |
| 41201 | /* 114013 */ /*GILLT_s16*//*Label 3441*/ GIMT_Encode4(114025), |
| 41202 | /* 114017 */ /*GILLT_s32*//*Label 3442*/ GIMT_Encode4(114262), |
| 41203 | /* 114021 */ /*GILLT_s64*//*Label 3443*/ GIMT_Encode4(114614), |
| 41204 | /* 114025 */ // Label 3441: @114025 |
| 41205 | /* 114025 */ GIM_Try, /*On fail goto*//*Label 3445*/ GIMT_Encode4(114261), |
| 41206 | /* 114030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41207 | /* 114034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3446*/ GIMT_Encode4(114092), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2558 // |
| 41208 | /* 114041 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41209 | /* 114045 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41210 | /* 114049 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41211 | /* 114053 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41212 | /* 114058 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41213 | /* 114060 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41214 | /* 114060 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41215 | /* 114063 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSH), |
| 41216 | /* 114067 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41217 | /* 114072 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41218 | /* 114076 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41219 | /* 114078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41220 | /* 114081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41221 | /* 114083 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41222 | /* 114086 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41223 | /* 114091 */ // GIR_Coverage, 2558, |
| 41224 | /* 114091 */ GIR_EraseRootFromParent_Done, |
| 41225 | /* 114092 */ // Label 3446: @114092 |
| 41226 | /* 114092 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3447*/ GIMT_Encode4(114150), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2582 // |
| 41227 | /* 114099 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41228 | /* 114103 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41229 | /* 114107 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41230 | /* 114111 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41231 | /* 114116 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41232 | /* 114118 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41233 | /* 114118 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41234 | /* 114121 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSH), |
| 41235 | /* 114125 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41236 | /* 114130 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41237 | /* 114134 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41238 | /* 114136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41239 | /* 114139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41240 | /* 114141 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41241 | /* 114144 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41242 | /* 114149 */ // GIR_Coverage, 2582, |
| 41243 | /* 114149 */ GIR_EraseRootFromParent_Done, |
| 41244 | /* 114150 */ // Label 3447: @114150 |
| 41245 | /* 114150 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3448*/ GIMT_Encode4(114208), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2534 // |
| 41246 | /* 114157 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41247 | /* 114161 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41248 | /* 114165 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41249 | /* 114169 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41250 | /* 114174 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41251 | /* 114176 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41252 | /* 114176 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41253 | /* 114179 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASH), |
| 41254 | /* 114183 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41255 | /* 114188 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41256 | /* 114192 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41257 | /* 114194 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41258 | /* 114197 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41259 | /* 114199 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41260 | /* 114202 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41261 | /* 114207 */ // GIR_Coverage, 2534, |
| 41262 | /* 114207 */ GIR_EraseRootFromParent_Done, |
| 41263 | /* 114208 */ // Label 3448: @114208 |
| 41264 | /* 114208 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3449*/ GIMT_Encode4(114260), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2643 // |
| 41265 | /* 114215 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41266 | /* 114219 */ // (fp_to_sint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41267 | /* 114219 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41268 | /* 114222 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZH), |
| 41269 | /* 114226 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41270 | /* 114231 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41271 | /* 114235 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41272 | /* 114238 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41273 | /* 114244 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41274 | /* 114246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41275 | /* 114249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41276 | /* 114251 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41277 | /* 114254 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41278 | /* 114259 */ // GIR_Coverage, 2643, |
| 41279 | /* 114259 */ GIR_EraseRootFromParent_Done, |
| 41280 | /* 114260 */ // Label 3449: @114260 |
| 41281 | /* 114260 */ GIM_Reject, |
| 41282 | /* 114261 */ // Label 3445: @114261 |
| 41283 | /* 114261 */ GIM_Reject, |
| 41284 | /* 114262 */ // Label 3442: @114262 |
| 41285 | /* 114262 */ GIM_Try, /*On fail goto*//*Label 3450*/ GIMT_Encode4(114498), |
| 41286 | /* 114267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41287 | /* 114271 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3451*/ GIMT_Encode4(114329), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2566 // |
| 41288 | /* 114278 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41289 | /* 114282 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41290 | /* 114286 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41291 | /* 114290 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41292 | /* 114295 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41293 | /* 114297 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41294 | /* 114297 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41295 | /* 114300 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSS), |
| 41296 | /* 114304 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41297 | /* 114309 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41298 | /* 114313 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41299 | /* 114315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41300 | /* 114318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41301 | /* 114320 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41302 | /* 114323 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41303 | /* 114328 */ // GIR_Coverage, 2566, |
| 41304 | /* 114328 */ GIR_EraseRootFromParent_Done, |
| 41305 | /* 114329 */ // Label 3451: @114329 |
| 41306 | /* 114329 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3452*/ GIMT_Encode4(114387), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2590 // |
| 41307 | /* 114336 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41308 | /* 114340 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41309 | /* 114344 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41310 | /* 114348 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41311 | /* 114353 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41312 | /* 114355 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41313 | /* 114355 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41314 | /* 114358 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSS), |
| 41315 | /* 114362 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41316 | /* 114367 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41317 | /* 114371 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41318 | /* 114373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41319 | /* 114376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41320 | /* 114378 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41321 | /* 114381 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41322 | /* 114386 */ // GIR_Coverage, 2590, |
| 41323 | /* 114386 */ GIR_EraseRootFromParent_Done, |
| 41324 | /* 114387 */ // Label 3452: @114387 |
| 41325 | /* 114387 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3453*/ GIMT_Encode4(114445), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2542 // |
| 41326 | /* 114394 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41327 | /* 114398 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41328 | /* 114402 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41329 | /* 114406 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41330 | /* 114411 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41331 | /* 114413 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41332 | /* 114413 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41333 | /* 114416 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASS), |
| 41334 | /* 114420 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41335 | /* 114425 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41336 | /* 114429 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41337 | /* 114431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41338 | /* 114434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41339 | /* 114436 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41340 | /* 114439 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41341 | /* 114444 */ // GIR_Coverage, 2542, |
| 41342 | /* 114444 */ GIR_EraseRootFromParent_Done, |
| 41343 | /* 114445 */ // Label 3453: @114445 |
| 41344 | /* 114445 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3454*/ GIMT_Encode4(114497), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2637 // |
| 41345 | /* 114452 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41346 | /* 114456 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41347 | /* 114456 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41348 | /* 114459 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZS), |
| 41349 | /* 114463 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41350 | /* 114468 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41351 | /* 114472 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41352 | /* 114475 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41353 | /* 114481 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41354 | /* 114483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41355 | /* 114486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41356 | /* 114488 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41357 | /* 114491 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41358 | /* 114496 */ // GIR_Coverage, 2637, |
| 41359 | /* 114496 */ GIR_EraseRootFromParent_Done, |
| 41360 | /* 114497 */ // Label 3454: @114497 |
| 41361 | /* 114497 */ GIM_Reject, |
| 41362 | /* 114498 */ // Label 3450: @114498 |
| 41363 | /* 114498 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3455*/ GIMT_Encode4(114613), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3099 // |
| 41364 | /* 114505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41365 | /* 114509 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41366 | /* 114513 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2sd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 41367 | /* 114513 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41368 | /* 114516 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41369 | /* 114520 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41370 | /* 114525 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 41371 | /* 114527 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 41372 | /* 114530 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41373 | /* 114534 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41374 | /* 114539 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41375 | /* 114542 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41376 | /* 114546 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 41377 | /* 114549 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41378 | /* 114554 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41379 | /* 114559 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41380 | /* 114564 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41381 | /* 114567 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd), |
| 41382 | /* 114571 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41383 | /* 114576 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41384 | /* 114579 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41385 | /* 114582 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41386 | /* 114588 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41387 | /* 114590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41388 | /* 114593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41389 | /* 114595 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41390 | /* 114602 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41391 | /* 114607 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41392 | /* 114612 */ // GIR_Coverage, 3099, |
| 41393 | /* 114612 */ GIR_EraseRootFromParent_Done, |
| 41394 | /* 114613 */ // Label 3455: @114613 |
| 41395 | /* 114613 */ GIM_Reject, |
| 41396 | /* 114614 */ // Label 3443: @114614 |
| 41397 | /* 114614 */ GIM_Try, /*On fail goto*//*Label 3456*/ GIMT_Encode4(114850), |
| 41398 | /* 114619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41399 | /* 114623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3457*/ GIMT_Encode4(114681), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2574 // |
| 41400 | /* 114630 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41401 | /* 114634 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41402 | /* 114638 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41403 | /* 114642 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41404 | /* 114647 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41405 | /* 114649 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41406 | /* 114649 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41407 | /* 114652 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSD), |
| 41408 | /* 114656 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41409 | /* 114661 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41410 | /* 114665 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41411 | /* 114667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41412 | /* 114670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41413 | /* 114672 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41414 | /* 114675 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41415 | /* 114680 */ // GIR_Coverage, 2574, |
| 41416 | /* 114680 */ GIR_EraseRootFromParent_Done, |
| 41417 | /* 114681 */ // Label 3457: @114681 |
| 41418 | /* 114681 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3458*/ GIMT_Encode4(114739), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2598 // |
| 41419 | /* 114688 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41420 | /* 114692 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41421 | /* 114696 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41422 | /* 114700 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41423 | /* 114705 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41424 | /* 114707 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41425 | /* 114707 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41426 | /* 114710 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSD), |
| 41427 | /* 114714 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41428 | /* 114719 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41429 | /* 114723 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41430 | /* 114725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41431 | /* 114728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41432 | /* 114730 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41433 | /* 114733 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41434 | /* 114738 */ // GIR_Coverage, 2598, |
| 41435 | /* 114738 */ GIR_EraseRootFromParent_Done, |
| 41436 | /* 114739 */ // Label 3458: @114739 |
| 41437 | /* 114739 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3459*/ GIMT_Encode4(114797), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2550 // |
| 41438 | /* 114746 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41439 | /* 114750 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41440 | /* 114754 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41441 | /* 114758 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41442 | /* 114763 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41443 | /* 114765 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41444 | /* 114765 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41445 | /* 114768 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASD), |
| 41446 | /* 114772 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41447 | /* 114777 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41448 | /* 114781 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41449 | /* 114783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41450 | /* 114786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41451 | /* 114788 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41452 | /* 114791 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41453 | /* 114796 */ // GIR_Coverage, 2550, |
| 41454 | /* 114796 */ GIR_EraseRootFromParent_Done, |
| 41455 | /* 114797 */ // Label 3459: @114797 |
| 41456 | /* 114797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3460*/ GIMT_Encode4(114849), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2631 // |
| 41457 | /* 114804 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41458 | /* 114808 */ // (fp_to_sint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41459 | /* 114808 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41460 | /* 114811 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZD), |
| 41461 | /* 114815 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41462 | /* 114820 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41463 | /* 114824 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41464 | /* 114827 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41465 | /* 114833 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41466 | /* 114835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41467 | /* 114838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41468 | /* 114840 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41469 | /* 114843 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41470 | /* 114848 */ // GIR_Coverage, 2631, |
| 41471 | /* 114848 */ GIR_EraseRootFromParent_Done, |
| 41472 | /* 114849 */ // Label 3460: @114849 |
| 41473 | /* 114849 */ GIM_Reject, |
| 41474 | /* 114850 */ // Label 3456: @114850 |
| 41475 | /* 114850 */ GIM_Reject, |
| 41476 | /* 114851 */ // Label 3444: @114851 |
| 41477 | /* 114851 */ GIM_Reject, |
| 41478 | /* 114852 */ // Label 3434: @114852 |
| 41479 | /* 114852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3461*/ GIMT_Encode4(114903), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5640 // |
| 41480 | /* 114859 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41481 | /* 114862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 41482 | /* 114866 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41483 | /* 114870 */ // (fp_to_sint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 41484 | /* 114870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r), |
| 41485 | /* 114873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 41486 | /* 114875 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 41487 | /* 114877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41488 | /* 114883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 41489 | /* 114886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41490 | /* 114889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41491 | /* 114895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41492 | /* 114901 */ GIR_RootConstrainSelectedInstOperands, |
| 41493 | /* 114902 */ // GIR_Coverage, 5640, |
| 41494 | /* 114902 */ GIR_EraseRootFromParent_Done, |
| 41495 | /* 114903 */ // Label 3461: @114903 |
| 41496 | /* 114903 */ GIM_Reject, |
| 41497 | /* 114904 */ // Label 3435: @114904 |
| 41498 | /* 114904 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3462*/ GIMT_Encode4(114955), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5641 // |
| 41499 | /* 114911 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41500 | /* 114914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 41501 | /* 114918 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41502 | /* 114922 */ // (fp_to_sint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 41503 | /* 114922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r), |
| 41504 | /* 114925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 41505 | /* 114927 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 41506 | /* 114929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41507 | /* 114935 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 41508 | /* 114938 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41509 | /* 114941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41510 | /* 114947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41511 | /* 114953 */ GIR_RootConstrainSelectedInstOperands, |
| 41512 | /* 114954 */ // GIR_Coverage, 5641, |
| 41513 | /* 114954 */ GIR_EraseRootFromParent_Done, |
| 41514 | /* 114955 */ // Label 3462: @114955 |
| 41515 | /* 114955 */ GIM_Reject, |
| 41516 | /* 114956 */ // Label 3436: @114956 |
| 41517 | /* 114956 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3463*/ GIMT_Encode4(114992), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1774 // |
| 41518 | /* 114963 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41519 | /* 114966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41520 | /* 114970 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41521 | /* 114974 */ // (fp_to_sint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2sd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 41522 | /* 114974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sd), |
| 41523 | /* 114977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41524 | /* 114979 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41525 | /* 114981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41526 | /* 114984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41527 | /* 114990 */ GIR_RootConstrainSelectedInstOperands, |
| 41528 | /* 114991 */ // GIR_Coverage, 1774, |
| 41529 | /* 114991 */ GIR_EraseRootFromParent_Done, |
| 41530 | /* 114992 */ // Label 3463: @114992 |
| 41531 | /* 114992 */ GIM_Reject, |
| 41532 | /* 114993 */ // Label 3437: @114993 |
| 41533 | /* 114993 */ GIM_Try, /*On fail goto*//*Label 3464*/ GIMT_Encode4(115089), |
| 41534 | /* 114998 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41535 | /* 115001 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3465*/ GIMT_Encode4(115034), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1778 // |
| 41536 | /* 115008 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41537 | /* 115012 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41538 | /* 115016 */ // (fp_to_sint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2sq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 41539 | /* 115016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sq), |
| 41540 | /* 115019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41541 | /* 115021 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41542 | /* 115023 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41543 | /* 115026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41544 | /* 115032 */ GIR_RootConstrainSelectedInstOperands, |
| 41545 | /* 115033 */ // GIR_Coverage, 1778, |
| 41546 | /* 115033 */ GIR_EraseRootFromParent_Done, |
| 41547 | /* 115034 */ // Label 3465: @115034 |
| 41548 | /* 115034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3466*/ GIMT_Encode4(115088), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4541 // |
| 41549 | /* 115041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41550 | /* 115045 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41551 | /* 115049 */ // (fp_to_sint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 41552 | /* 115049 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41553 | /* 115052 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41554 | /* 115056 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41555 | /* 115061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z), |
| 41556 | /* 115064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41557 | /* 115066 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41558 | /* 115068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41559 | /* 115071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41560 | /* 115077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41561 | /* 115083 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41562 | /* 115086 */ GIR_RootConstrainSelectedInstOperands, |
| 41563 | /* 115087 */ // GIR_Coverage, 4541, |
| 41564 | /* 115087 */ GIR_EraseRootFromParent_Done, |
| 41565 | /* 115088 */ // Label 3466: @115088 |
| 41566 | /* 115088 */ GIM_Reject, |
| 41567 | /* 115089 */ // Label 3464: @115089 |
| 41568 | /* 115089 */ GIM_Reject, |
| 41569 | /* 115090 */ // Label 3438: @115090 |
| 41570 | /* 115090 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3467*/ GIMT_Encode4(115126), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1766 // |
| 41571 | /* 115097 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 41572 | /* 115100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41573 | /* 115104 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41574 | /* 115108 */ // (fp_to_sint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2sd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 41575 | /* 115108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd), |
| 41576 | /* 115111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41577 | /* 115113 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41578 | /* 115115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41579 | /* 115118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41580 | /* 115124 */ GIR_RootConstrainSelectedInstOperands, |
| 41581 | /* 115125 */ // GIR_Coverage, 1766, |
| 41582 | /* 115125 */ GIR_EraseRootFromParent_Done, |
| 41583 | /* 115126 */ // Label 3467: @115126 |
| 41584 | /* 115126 */ GIM_Reject, |
| 41585 | /* 115127 */ // Label 3439: @115127 |
| 41586 | /* 115127 */ GIM_Try, /*On fail goto*//*Label 3468*/ GIMT_Encode4(115223), |
| 41587 | /* 115132 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41588 | /* 115135 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3469*/ GIMT_Encode4(115168), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1770 // |
| 41589 | /* 115142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41590 | /* 115146 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41591 | /* 115150 */ // (fp_to_sint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2sq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 41592 | /* 115150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sq), |
| 41593 | /* 115153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41594 | /* 115155 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41595 | /* 115157 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41596 | /* 115160 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41597 | /* 115166 */ GIR_RootConstrainSelectedInstOperands, |
| 41598 | /* 115167 */ // GIR_Coverage, 1770, |
| 41599 | /* 115167 */ GIR_EraseRootFromParent_Done, |
| 41600 | /* 115168 */ // Label 3469: @115168 |
| 41601 | /* 115168 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3470*/ GIMT_Encode4(115222), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4547 // |
| 41602 | /* 115175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41603 | /* 115179 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41604 | /* 115183 */ // (fp_to_sint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 41605 | /* 115183 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41606 | /* 115186 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41607 | /* 115190 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41608 | /* 115195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z), |
| 41609 | /* 115198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41610 | /* 115200 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41611 | /* 115202 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41612 | /* 115205 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41613 | /* 115211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41614 | /* 115217 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41615 | /* 115220 */ GIR_RootConstrainSelectedInstOperands, |
| 41616 | /* 115221 */ // GIR_Coverage, 4547, |
| 41617 | /* 115221 */ GIR_EraseRootFromParent_Done, |
| 41618 | /* 115222 */ // Label 3470: @115222 |
| 41619 | /* 115222 */ GIM_Reject, |
| 41620 | /* 115223 */ // Label 3468: @115223 |
| 41621 | /* 115223 */ GIM_Reject, |
| 41622 | /* 115224 */ // Label 3440: @115224 |
| 41623 | /* 115224 */ GIM_Reject, |
| 41624 | /* 115225 */ // Label 49: @115225 |
| 41625 | /* 115225 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3478*/ GIMT_Encode4(116506), |
| 41626 | /* 115236 */ /*GILLT_s32*//*Label 3471*/ GIMT_Encode4(115284), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41627 | /* 115248 */ /*GILLT_v4s1*//*Label 3472*/ GIMT_Encode4(116134), |
| 41628 | /* 115252 */ /*GILLT_v8s1*//*Label 3473*/ GIMT_Encode4(116186), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41629 | /* 115268 */ /*GILLT_v4s16*//*Label 3474*/ GIMT_Encode4(116238), |
| 41630 | /* 115272 */ /*GILLT_v8s16*//*Label 3475*/ GIMT_Encode4(116275), |
| 41631 | /* 115276 */ /*GILLT_v2s32*//*Label 3476*/ GIMT_Encode4(116372), |
| 41632 | /* 115280 */ /*GILLT_v4s32*//*Label 3477*/ GIMT_Encode4(116409), |
| 41633 | /* 115284 */ // Label 3471: @115284 |
| 41634 | /* 115284 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3482*/ GIMT_Encode4(116133), |
| 41635 | /* 115295 */ /*GILLT_s16*//*Label 3479*/ GIMT_Encode4(115307), |
| 41636 | /* 115299 */ /*GILLT_s32*//*Label 3480*/ GIMT_Encode4(115544), |
| 41637 | /* 115303 */ /*GILLT_s64*//*Label 3481*/ GIMT_Encode4(115896), |
| 41638 | /* 115307 */ // Label 3479: @115307 |
| 41639 | /* 115307 */ GIM_Try, /*On fail goto*//*Label 3483*/ GIMT_Encode4(115543), |
| 41640 | /* 115312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41641 | /* 115316 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3484*/ GIMT_Encode4(115374), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2562 // |
| 41642 | /* 115323 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41643 | /* 115327 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41644 | /* 115331 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41645 | /* 115335 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41646 | /* 115340 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41647 | /* 115342 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41648 | /* 115342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41649 | /* 115345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUH), |
| 41650 | /* 115349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41651 | /* 115354 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41652 | /* 115358 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41653 | /* 115360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41654 | /* 115363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41655 | /* 115365 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41656 | /* 115368 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41657 | /* 115373 */ // GIR_Coverage, 2562, |
| 41658 | /* 115373 */ GIR_EraseRootFromParent_Done, |
| 41659 | /* 115374 */ // Label 3484: @115374 |
| 41660 | /* 115374 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3485*/ GIMT_Encode4(115432), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2586 // |
| 41661 | /* 115381 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41662 | /* 115385 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41663 | /* 115389 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41664 | /* 115393 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41665 | /* 115398 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41666 | /* 115400 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41667 | /* 115400 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41668 | /* 115403 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUH), |
| 41669 | /* 115407 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41670 | /* 115412 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41671 | /* 115416 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41672 | /* 115418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41673 | /* 115421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41674 | /* 115423 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41675 | /* 115426 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41676 | /* 115431 */ // GIR_Coverage, 2586, |
| 41677 | /* 115431 */ GIR_EraseRootFromParent_Done, |
| 41678 | /* 115432 */ // Label 3485: @115432 |
| 41679 | /* 115432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3486*/ GIMT_Encode4(115490), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2538 // |
| 41680 | /* 115439 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41681 | /* 115443 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41682 | /* 115447 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41683 | /* 115451 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41684 | /* 115456 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41685 | /* 115458 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41686 | /* 115458 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41687 | /* 115461 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUH), |
| 41688 | /* 115465 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41689 | /* 115470 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41690 | /* 115474 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41691 | /* 115476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41692 | /* 115479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41693 | /* 115481 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41694 | /* 115484 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41695 | /* 115489 */ // GIR_Coverage, 2538, |
| 41696 | /* 115489 */ GIR_EraseRootFromParent_Done, |
| 41697 | /* 115490 */ // Label 3486: @115490 |
| 41698 | /* 115490 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3487*/ GIMT_Encode4(115542), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2658 // |
| 41699 | /* 115497 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41700 | /* 115501 */ // (fp_to_uint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41701 | /* 115501 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41702 | /* 115504 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZH), |
| 41703 | /* 115508 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41704 | /* 115513 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41705 | /* 115517 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41706 | /* 115520 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41707 | /* 115526 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41708 | /* 115528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41709 | /* 115531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41710 | /* 115533 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41711 | /* 115536 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41712 | /* 115541 */ // GIR_Coverage, 2658, |
| 41713 | /* 115541 */ GIR_EraseRootFromParent_Done, |
| 41714 | /* 115542 */ // Label 3487: @115542 |
| 41715 | /* 115542 */ GIM_Reject, |
| 41716 | /* 115543 */ // Label 3483: @115543 |
| 41717 | /* 115543 */ GIM_Reject, |
| 41718 | /* 115544 */ // Label 3480: @115544 |
| 41719 | /* 115544 */ GIM_Try, /*On fail goto*//*Label 3488*/ GIMT_Encode4(115780), |
| 41720 | /* 115549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41721 | /* 115553 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3489*/ GIMT_Encode4(115611), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2570 // |
| 41722 | /* 115560 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41723 | /* 115564 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41724 | /* 115568 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41725 | /* 115572 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41726 | /* 115577 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41727 | /* 115579 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41728 | /* 115579 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41729 | /* 115582 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUS), |
| 41730 | /* 115586 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41731 | /* 115591 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41732 | /* 115595 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41733 | /* 115597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41734 | /* 115600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41735 | /* 115602 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41736 | /* 115605 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41737 | /* 115610 */ // GIR_Coverage, 2570, |
| 41738 | /* 115610 */ GIR_EraseRootFromParent_Done, |
| 41739 | /* 115611 */ // Label 3489: @115611 |
| 41740 | /* 115611 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3490*/ GIMT_Encode4(115669), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2594 // |
| 41741 | /* 115618 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41742 | /* 115622 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41743 | /* 115626 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41744 | /* 115630 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41745 | /* 115635 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41746 | /* 115637 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41747 | /* 115637 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41748 | /* 115640 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUS), |
| 41749 | /* 115644 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41750 | /* 115649 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41751 | /* 115653 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41752 | /* 115655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41753 | /* 115658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41754 | /* 115660 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41755 | /* 115663 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41756 | /* 115668 */ // GIR_Coverage, 2594, |
| 41757 | /* 115668 */ GIR_EraseRootFromParent_Done, |
| 41758 | /* 115669 */ // Label 3490: @115669 |
| 41759 | /* 115669 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3491*/ GIMT_Encode4(115727), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2546 // |
| 41760 | /* 115676 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41761 | /* 115680 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41762 | /* 115684 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41763 | /* 115688 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41764 | /* 115693 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41765 | /* 115695 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41766 | /* 115695 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41767 | /* 115698 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUS), |
| 41768 | /* 115702 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41769 | /* 115707 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41770 | /* 115711 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41771 | /* 115713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41772 | /* 115716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41773 | /* 115718 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41774 | /* 115721 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41775 | /* 115726 */ // GIR_Coverage, 2546, |
| 41776 | /* 115726 */ GIR_EraseRootFromParent_Done, |
| 41777 | /* 115727 */ // Label 3491: @115727 |
| 41778 | /* 115727 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3492*/ GIMT_Encode4(115779), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2652 // |
| 41779 | /* 115734 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41780 | /* 115738 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41781 | /* 115738 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41782 | /* 115741 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZS), |
| 41783 | /* 115745 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41784 | /* 115750 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41785 | /* 115754 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41786 | /* 115757 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41787 | /* 115763 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41788 | /* 115765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41789 | /* 115768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41790 | /* 115770 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41791 | /* 115773 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41792 | /* 115778 */ // GIR_Coverage, 2652, |
| 41793 | /* 115778 */ GIR_EraseRootFromParent_Done, |
| 41794 | /* 115779 */ // Label 3492: @115779 |
| 41795 | /* 115779 */ GIM_Reject, |
| 41796 | /* 115780 */ // Label 3488: @115780 |
| 41797 | /* 115780 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3493*/ GIMT_Encode4(115895), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3100 // |
| 41798 | /* 115787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41799 | /* 115791 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41800 | /* 115795 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2ud:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 41801 | /* 115795 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41802 | /* 115798 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41803 | /* 115802 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41804 | /* 115807 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 41805 | /* 115809 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 41806 | /* 115812 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41807 | /* 115816 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41808 | /* 115821 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41809 | /* 115824 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41810 | /* 115828 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 41811 | /* 115831 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41812 | /* 115836 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41813 | /* 115841 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41814 | /* 115846 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41815 | /* 115849 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud), |
| 41816 | /* 115853 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41817 | /* 115858 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41818 | /* 115861 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41819 | /* 115864 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41820 | /* 115870 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41821 | /* 115872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41822 | /* 115875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41823 | /* 115877 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41824 | /* 115884 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41825 | /* 115889 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41826 | /* 115894 */ // GIR_Coverage, 3100, |
| 41827 | /* 115894 */ GIR_EraseRootFromParent_Done, |
| 41828 | /* 115895 */ // Label 3493: @115895 |
| 41829 | /* 115895 */ GIM_Reject, |
| 41830 | /* 115896 */ // Label 3481: @115896 |
| 41831 | /* 115896 */ GIM_Try, /*On fail goto*//*Label 3494*/ GIMT_Encode4(116132), |
| 41832 | /* 115901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41833 | /* 115905 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3495*/ GIMT_Encode4(115963), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2578 // |
| 41834 | /* 115912 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41835 | /* 115916 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41836 | /* 115920 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41837 | /* 115924 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41838 | /* 115929 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41839 | /* 115931 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41840 | /* 115931 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41841 | /* 115934 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUD), |
| 41842 | /* 115938 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41843 | /* 115943 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41844 | /* 115947 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41845 | /* 115949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41846 | /* 115952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41847 | /* 115954 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41848 | /* 115957 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41849 | /* 115962 */ // GIR_Coverage, 2578, |
| 41850 | /* 115962 */ GIR_EraseRootFromParent_Done, |
| 41851 | /* 115963 */ // Label 3495: @115963 |
| 41852 | /* 115963 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3496*/ GIMT_Encode4(116021), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2602 // |
| 41853 | /* 115970 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41854 | /* 115974 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41855 | /* 115978 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41856 | /* 115982 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41857 | /* 115987 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41858 | /* 115989 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41859 | /* 115989 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41860 | /* 115992 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUD), |
| 41861 | /* 115996 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41862 | /* 116001 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41863 | /* 116005 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41864 | /* 116007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41865 | /* 116010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41866 | /* 116012 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41867 | /* 116015 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41868 | /* 116020 */ // GIR_Coverage, 2602, |
| 41869 | /* 116020 */ GIR_EraseRootFromParent_Done, |
| 41870 | /* 116021 */ // Label 3496: @116021 |
| 41871 | /* 116021 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3497*/ GIMT_Encode4(116079), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2554 // |
| 41872 | /* 116028 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41873 | /* 116032 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41874 | /* 116036 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41875 | /* 116040 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41876 | /* 116045 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41877 | /* 116047 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41878 | /* 116047 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41879 | /* 116050 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUD), |
| 41880 | /* 116054 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41881 | /* 116059 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41882 | /* 116063 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41883 | /* 116065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41884 | /* 116068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41885 | /* 116070 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41886 | /* 116073 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41887 | /* 116078 */ // GIR_Coverage, 2554, |
| 41888 | /* 116078 */ GIR_EraseRootFromParent_Done, |
| 41889 | /* 116079 */ // Label 3497: @116079 |
| 41890 | /* 116079 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3498*/ GIMT_Encode4(116131), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2646 // |
| 41891 | /* 116086 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41892 | /* 116090 */ // (fp_to_uint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41893 | /* 116090 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41894 | /* 116093 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZD), |
| 41895 | /* 116097 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41896 | /* 116102 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41897 | /* 116106 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41898 | /* 116109 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41899 | /* 116115 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41900 | /* 116117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41901 | /* 116120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41902 | /* 116122 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41903 | /* 116125 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41904 | /* 116130 */ // GIR_Coverage, 2646, |
| 41905 | /* 116130 */ GIR_EraseRootFromParent_Done, |
| 41906 | /* 116131 */ // Label 3498: @116131 |
| 41907 | /* 116131 */ GIM_Reject, |
| 41908 | /* 116132 */ // Label 3494: @116132 |
| 41909 | /* 116132 */ GIM_Reject, |
| 41910 | /* 116133 */ // Label 3482: @116133 |
| 41911 | /* 116133 */ GIM_Reject, |
| 41912 | /* 116134 */ // Label 3472: @116134 |
| 41913 | /* 116134 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3499*/ GIMT_Encode4(116185), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5638 // |
| 41914 | /* 116141 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41915 | /* 116144 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 41916 | /* 116148 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41917 | /* 116152 */ // (fp_to_uint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 41918 | /* 116152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r), |
| 41919 | /* 116155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 41920 | /* 116157 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 41921 | /* 116159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41922 | /* 116165 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 41923 | /* 116168 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41924 | /* 116171 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41925 | /* 116177 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41926 | /* 116183 */ GIR_RootConstrainSelectedInstOperands, |
| 41927 | /* 116184 */ // GIR_Coverage, 5638, |
| 41928 | /* 116184 */ GIR_EraseRootFromParent_Done, |
| 41929 | /* 116185 */ // Label 3499: @116185 |
| 41930 | /* 116185 */ GIM_Reject, |
| 41931 | /* 116186 */ // Label 3473: @116186 |
| 41932 | /* 116186 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3500*/ GIMT_Encode4(116237), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5639 // |
| 41933 | /* 116193 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41934 | /* 116196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 41935 | /* 116200 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41936 | /* 116204 */ // (fp_to_uint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 41937 | /* 116204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r), |
| 41938 | /* 116207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 41939 | /* 116209 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 41940 | /* 116211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41941 | /* 116217 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 41942 | /* 116220 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41943 | /* 116223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41944 | /* 116229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41945 | /* 116235 */ GIR_RootConstrainSelectedInstOperands, |
| 41946 | /* 116236 */ // GIR_Coverage, 5639, |
| 41947 | /* 116236 */ GIR_EraseRootFromParent_Done, |
| 41948 | /* 116237 */ // Label 3500: @116237 |
| 41949 | /* 116237 */ GIM_Reject, |
| 41950 | /* 116238 */ // Label 3474: @116238 |
| 41951 | /* 116238 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3501*/ GIMT_Encode4(116274), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1775 // |
| 41952 | /* 116245 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41953 | /* 116248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41954 | /* 116252 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41955 | /* 116256 */ // (fp_to_uint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2ud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 41956 | /* 116256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2ud), |
| 41957 | /* 116259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41958 | /* 116261 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41959 | /* 116263 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41960 | /* 116266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41961 | /* 116272 */ GIR_RootConstrainSelectedInstOperands, |
| 41962 | /* 116273 */ // GIR_Coverage, 1775, |
| 41963 | /* 116273 */ GIR_EraseRootFromParent_Done, |
| 41964 | /* 116274 */ // Label 3501: @116274 |
| 41965 | /* 116274 */ GIM_Reject, |
| 41966 | /* 116275 */ // Label 3475: @116275 |
| 41967 | /* 116275 */ GIM_Try, /*On fail goto*//*Label 3502*/ GIMT_Encode4(116371), |
| 41968 | /* 116280 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41969 | /* 116283 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3503*/ GIMT_Encode4(116316), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1779 // |
| 41970 | /* 116290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41971 | /* 116294 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41972 | /* 116298 */ // (fp_to_uint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2uq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 41973 | /* 116298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2uq), |
| 41974 | /* 116301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41975 | /* 116303 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41976 | /* 116305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41977 | /* 116308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41978 | /* 116314 */ GIR_RootConstrainSelectedInstOperands, |
| 41979 | /* 116315 */ // GIR_Coverage, 1779, |
| 41980 | /* 116315 */ GIR_EraseRootFromParent_Done, |
| 41981 | /* 116316 */ // Label 3503: @116316 |
| 41982 | /* 116316 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3504*/ GIMT_Encode4(116370), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4544 // |
| 41983 | /* 116323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41984 | /* 116327 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41985 | /* 116331 */ // (fp_to_uint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 41986 | /* 116331 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41987 | /* 116334 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41988 | /* 116338 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41989 | /* 116343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z), |
| 41990 | /* 116346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41991 | /* 116348 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41992 | /* 116350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41993 | /* 116353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41994 | /* 116359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41995 | /* 116365 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41996 | /* 116368 */ GIR_RootConstrainSelectedInstOperands, |
| 41997 | /* 116369 */ // GIR_Coverage, 4544, |
| 41998 | /* 116369 */ GIR_EraseRootFromParent_Done, |
| 41999 | /* 116370 */ // Label 3504: @116370 |
| 42000 | /* 116370 */ GIM_Reject, |
| 42001 | /* 116371 */ // Label 3502: @116371 |
| 42002 | /* 116371 */ GIM_Reject, |
| 42003 | /* 116372 */ // Label 3476: @116372 |
| 42004 | /* 116372 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3505*/ GIMT_Encode4(116408), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1767 // |
| 42005 | /* 116379 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42006 | /* 116382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42007 | /* 116386 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42008 | /* 116390 */ // (fp_to_uint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2ud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 42009 | /* 116390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud), |
| 42010 | /* 116393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42011 | /* 116395 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42012 | /* 116397 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42013 | /* 116400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42014 | /* 116406 */ GIR_RootConstrainSelectedInstOperands, |
| 42015 | /* 116407 */ // GIR_Coverage, 1767, |
| 42016 | /* 116407 */ GIR_EraseRootFromParent_Done, |
| 42017 | /* 116408 */ // Label 3505: @116408 |
| 42018 | /* 116408 */ GIM_Reject, |
| 42019 | /* 116409 */ // Label 3477: @116409 |
| 42020 | /* 116409 */ GIM_Try, /*On fail goto*//*Label 3506*/ GIMT_Encode4(116505), |
| 42021 | /* 116414 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42022 | /* 116417 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3507*/ GIMT_Encode4(116450), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1771 // |
| 42023 | /* 116424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42024 | /* 116428 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42025 | /* 116432 */ // (fp_to_uint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2uq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 42026 | /* 116432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2uq), |
| 42027 | /* 116435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42028 | /* 116437 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42029 | /* 116439 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42030 | /* 116442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42031 | /* 116448 */ GIR_RootConstrainSelectedInstOperands, |
| 42032 | /* 116449 */ // GIR_Coverage, 1771, |
| 42033 | /* 116449 */ GIR_EraseRootFromParent_Done, |
| 42034 | /* 116450 */ // Label 3507: @116450 |
| 42035 | /* 116450 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3508*/ GIMT_Encode4(116504), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4550 // |
| 42036 | /* 116457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42037 | /* 116461 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42038 | /* 116465 */ // (fp_to_uint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 42039 | /* 116465 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42040 | /* 116468 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42041 | /* 116472 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42042 | /* 116477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z), |
| 42043 | /* 116480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42044 | /* 116482 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42045 | /* 116484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42046 | /* 116487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42047 | /* 116493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42048 | /* 116499 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42049 | /* 116502 */ GIR_RootConstrainSelectedInstOperands, |
| 42050 | /* 116503 */ // GIR_Coverage, 4550, |
| 42051 | /* 116503 */ GIR_EraseRootFromParent_Done, |
| 42052 | /* 116504 */ // Label 3508: @116504 |
| 42053 | /* 116504 */ GIM_Reject, |
| 42054 | /* 116505 */ // Label 3506: @116505 |
| 42055 | /* 116505 */ GIM_Reject, |
| 42056 | /* 116506 */ // Label 3478: @116506 |
| 42057 | /* 116506 */ GIM_Reject, |
| 42058 | /* 116507 */ // Label 50: @116507 |
| 42059 | /* 116507 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3516*/ GIMT_Encode4(117148), |
| 42060 | /* 116518 */ /*GILLT_s16*//*Label 3509*/ GIMT_Encode4(116570), |
| 42061 | /* 116522 */ /*GILLT_s32*//*Label 3510*/ GIMT_Encode4(116629), |
| 42062 | /* 116526 */ /*GILLT_s64*//*Label 3511*/ GIMT_Encode4(116821), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42063 | /* 116554 */ /*GILLT_v4s16*//*Label 3512*/ GIMT_Encode4(116880), |
| 42064 | /* 116558 */ /*GILLT_v8s16*//*Label 3513*/ GIMT_Encode4(116917), |
| 42065 | /* 116562 */ /*GILLT_v2s32*//*Label 3514*/ GIMT_Encode4(117014), |
| 42066 | /* 116566 */ /*GILLT_v4s32*//*Label 3515*/ GIMT_Encode4(117051), |
| 42067 | /* 116570 */ // Label 3509: @116570 |
| 42068 | /* 116570 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3517*/ GIMT_Encode4(116628), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2619 // |
| 42069 | /* 116577 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42070 | /* 116580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42071 | /* 116584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42072 | /* 116588 */ // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VSITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 42073 | /* 116588 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42074 | /* 116591 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42075 | /* 116595 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42076 | /* 116600 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42077 | /* 116604 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42078 | /* 116609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOH), |
| 42079 | /* 116612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42080 | /* 116614 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42081 | /* 116617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42082 | /* 116620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42083 | /* 116626 */ GIR_RootConstrainSelectedInstOperands, |
| 42084 | /* 116627 */ // GIR_Coverage, 2619, |
| 42085 | /* 116627 */ GIR_EraseRootFromParent_Done, |
| 42086 | /* 116628 */ // Label 3517: @116628 |
| 42087 | /* 116628 */ GIM_Reject, |
| 42088 | /* 116629 */ // Label 3510: @116629 |
| 42089 | /* 116629 */ GIM_Try, /*On fail goto*//*Label 3518*/ GIMT_Encode4(116820), |
| 42090 | /* 116634 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42091 | /* 116637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42092 | /* 116641 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42093 | /* 116645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3519*/ GIMT_Encode4(116692), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2615 // |
| 42094 | /* 116652 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VSITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 42095 | /* 116652 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42096 | /* 116655 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42097 | /* 116659 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42098 | /* 116664 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42099 | /* 116668 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42100 | /* 116673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOS), |
| 42101 | /* 116676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42102 | /* 116678 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42103 | /* 116681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42104 | /* 116684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42105 | /* 116690 */ GIR_RootConstrainSelectedInstOperands, |
| 42106 | /* 116691 */ // GIR_Coverage, 2615, |
| 42107 | /* 116691 */ GIR_EraseRootFromParent_Done, |
| 42108 | /* 116692 */ // Label 3519: @116692 |
| 42109 | /* 116692 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3520*/ GIMT_Encode4(116819), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3101 // |
| 42110 | /* 116699 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTs2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 42111 | /* 116699 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 42112 | /* 116702 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42113 | /* 116706 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42114 | /* 116711 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42115 | /* 116715 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42116 | /* 116720 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 42117 | /* 116723 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42118 | /* 116727 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42119 | /* 116732 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 42120 | /* 116734 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 42121 | /* 116737 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42122 | /* 116741 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42123 | /* 116746 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 42124 | /* 116749 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 42125 | /* 116752 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 42126 | /* 116755 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42127 | /* 116760 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42128 | /* 116765 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 42129 | /* 116770 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 42130 | /* 116773 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd), |
| 42131 | /* 116777 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42132 | /* 116782 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 42133 | /* 116785 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42134 | /* 116788 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42135 | /* 116794 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42136 | /* 116796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42137 | /* 116799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42138 | /* 116801 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 42139 | /* 116808 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42140 | /* 116813 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42141 | /* 116818 */ // GIR_Coverage, 3101, |
| 42142 | /* 116818 */ GIR_EraseRootFromParent_Done, |
| 42143 | /* 116819 */ // Label 3520: @116819 |
| 42144 | /* 116819 */ GIM_Reject, |
| 42145 | /* 116820 */ // Label 3518: @116820 |
| 42146 | /* 116820 */ GIM_Reject, |
| 42147 | /* 116821 */ // Label 3511: @116821 |
| 42148 | /* 116821 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3521*/ GIMT_Encode4(116879), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2611 // |
| 42149 | /* 116828 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42150 | /* 116831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42151 | /* 116835 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42152 | /* 116839 */ // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VSITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 42153 | /* 116839 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42154 | /* 116842 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42155 | /* 116846 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42156 | /* 116851 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42157 | /* 116855 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42158 | /* 116860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOD), |
| 42159 | /* 116863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42160 | /* 116865 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42161 | /* 116868 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42162 | /* 116871 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42163 | /* 116877 */ GIR_RootConstrainSelectedInstOperands, |
| 42164 | /* 116878 */ // GIR_Coverage, 2611, |
| 42165 | /* 116878 */ GIR_EraseRootFromParent_Done, |
| 42166 | /* 116879 */ // Label 3521: @116879 |
| 42167 | /* 116879 */ GIM_Reject, |
| 42168 | /* 116880 */ // Label 3512: @116880 |
| 42169 | /* 116880 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3522*/ GIMT_Encode4(116916), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1776 // |
| 42170 | /* 116887 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42171 | /* 116890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42172 | /* 116894 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42173 | /* 116898 */ // (sint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) |
| 42174 | /* 116898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hd), |
| 42175 | /* 116901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42176 | /* 116903 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42177 | /* 116905 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42178 | /* 116908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42179 | /* 116914 */ GIR_RootConstrainSelectedInstOperands, |
| 42180 | /* 116915 */ // GIR_Coverage, 1776, |
| 42181 | /* 116915 */ GIR_EraseRootFromParent_Done, |
| 42182 | /* 116916 */ // Label 3522: @116916 |
| 42183 | /* 116916 */ GIM_Reject, |
| 42184 | /* 116917 */ // Label 3513: @116917 |
| 42185 | /* 116917 */ GIM_Try, /*On fail goto*//*Label 3523*/ GIMT_Encode4(117013), |
| 42186 | /* 116922 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42187 | /* 116925 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3524*/ GIMT_Encode4(116958), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1780 // |
| 42188 | /* 116932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42189 | /* 116936 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42190 | /* 116940 */ // (sint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) |
| 42191 | /* 116940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hq), |
| 42192 | /* 116943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42193 | /* 116945 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42194 | /* 116947 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42195 | /* 116950 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42196 | /* 116956 */ GIR_RootConstrainSelectedInstOperands, |
| 42197 | /* 116957 */ // GIR_Coverage, 1780, |
| 42198 | /* 116957 */ GIR_EraseRootFromParent_Done, |
| 42199 | /* 116958 */ // Label 3524: @116958 |
| 42200 | /* 116958 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3525*/ GIMT_Encode4(117012), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4553 // |
| 42201 | /* 116965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42202 | /* 116969 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42203 | /* 116973 */ // (sint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 42204 | /* 116973 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42205 | /* 116976 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42206 | /* 116980 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42207 | /* 116985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n), |
| 42208 | /* 116988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42209 | /* 116990 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42210 | /* 116992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42211 | /* 116995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42212 | /* 117001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42213 | /* 117007 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42214 | /* 117010 */ GIR_RootConstrainSelectedInstOperands, |
| 42215 | /* 117011 */ // GIR_Coverage, 4553, |
| 42216 | /* 117011 */ GIR_EraseRootFromParent_Done, |
| 42217 | /* 117012 */ // Label 3525: @117012 |
| 42218 | /* 117012 */ GIM_Reject, |
| 42219 | /* 117013 */ // Label 3523: @117013 |
| 42220 | /* 117013 */ GIM_Reject, |
| 42221 | /* 117014 */ // Label 3514: @117014 |
| 42222 | /* 117014 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3526*/ GIMT_Encode4(117050), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1768 // |
| 42223 | /* 117021 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42224 | /* 117024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42225 | /* 117028 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42226 | /* 117032 */ // (sint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) |
| 42227 | /* 117032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd), |
| 42228 | /* 117035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42229 | /* 117037 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42230 | /* 117039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42231 | /* 117042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42232 | /* 117048 */ GIR_RootConstrainSelectedInstOperands, |
| 42233 | /* 117049 */ // GIR_Coverage, 1768, |
| 42234 | /* 117049 */ GIR_EraseRootFromParent_Done, |
| 42235 | /* 117050 */ // Label 3526: @117050 |
| 42236 | /* 117050 */ GIM_Reject, |
| 42237 | /* 117051 */ // Label 3515: @117051 |
| 42238 | /* 117051 */ GIM_Try, /*On fail goto*//*Label 3527*/ GIMT_Encode4(117147), |
| 42239 | /* 117056 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42240 | /* 117059 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3528*/ GIMT_Encode4(117092), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1772 // |
| 42241 | /* 117066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42242 | /* 117070 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42243 | /* 117074 */ // (sint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) |
| 42244 | /* 117074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fq), |
| 42245 | /* 117077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42246 | /* 117079 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42247 | /* 117081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42248 | /* 117084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42249 | /* 117090 */ GIR_RootConstrainSelectedInstOperands, |
| 42250 | /* 117091 */ // GIR_Coverage, 1772, |
| 42251 | /* 117091 */ GIR_EraseRootFromParent_Done, |
| 42252 | /* 117092 */ // Label 3528: @117092 |
| 42253 | /* 117092 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3529*/ GIMT_Encode4(117146), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4559 // |
| 42254 | /* 117099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42255 | /* 117103 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42256 | /* 117107 */ // (sint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 42257 | /* 117107 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42258 | /* 117110 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42259 | /* 117114 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42260 | /* 117119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n), |
| 42261 | /* 117122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42262 | /* 117124 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42263 | /* 117126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42264 | /* 117129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42265 | /* 117135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42266 | /* 117141 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42267 | /* 117144 */ GIR_RootConstrainSelectedInstOperands, |
| 42268 | /* 117145 */ // GIR_Coverage, 4559, |
| 42269 | /* 117145 */ GIR_EraseRootFromParent_Done, |
| 42270 | /* 117146 */ // Label 3529: @117146 |
| 42271 | /* 117146 */ GIM_Reject, |
| 42272 | /* 117147 */ // Label 3527: @117147 |
| 42273 | /* 117147 */ GIM_Reject, |
| 42274 | /* 117148 */ // Label 3516: @117148 |
| 42275 | /* 117148 */ GIM_Reject, |
| 42276 | /* 117149 */ // Label 51: @117149 |
| 42277 | /* 117149 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3537*/ GIMT_Encode4(117790), |
| 42278 | /* 117160 */ /*GILLT_s16*//*Label 3530*/ GIMT_Encode4(117212), |
| 42279 | /* 117164 */ /*GILLT_s32*//*Label 3531*/ GIMT_Encode4(117271), |
| 42280 | /* 117168 */ /*GILLT_s64*//*Label 3532*/ GIMT_Encode4(117463), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42281 | /* 117196 */ /*GILLT_v4s16*//*Label 3533*/ GIMT_Encode4(117522), |
| 42282 | /* 117200 */ /*GILLT_v8s16*//*Label 3534*/ GIMT_Encode4(117559), |
| 42283 | /* 117204 */ /*GILLT_v2s32*//*Label 3535*/ GIMT_Encode4(117656), |
| 42284 | /* 117208 */ /*GILLT_v4s32*//*Label 3536*/ GIMT_Encode4(117693), |
| 42285 | /* 117212 */ // Label 3530: @117212 |
| 42286 | /* 117212 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3538*/ GIMT_Encode4(117270), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2629 // |
| 42287 | /* 117219 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42288 | /* 117222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42289 | /* 117226 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42290 | /* 117230 */ // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VUITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 42291 | /* 117230 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42292 | /* 117233 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42293 | /* 117237 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42294 | /* 117242 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42295 | /* 117246 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42296 | /* 117251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOH), |
| 42297 | /* 117254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42298 | /* 117256 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42299 | /* 117259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42300 | /* 117262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42301 | /* 117268 */ GIR_RootConstrainSelectedInstOperands, |
| 42302 | /* 117269 */ // GIR_Coverage, 2629, |
| 42303 | /* 117269 */ GIR_EraseRootFromParent_Done, |
| 42304 | /* 117270 */ // Label 3538: @117270 |
| 42305 | /* 117270 */ GIM_Reject, |
| 42306 | /* 117271 */ // Label 3531: @117271 |
| 42307 | /* 117271 */ GIM_Try, /*On fail goto*//*Label 3539*/ GIMT_Encode4(117462), |
| 42308 | /* 117276 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42309 | /* 117279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42310 | /* 117283 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42311 | /* 117287 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3540*/ GIMT_Encode4(117334), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2625 // |
| 42312 | /* 117294 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VUITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 42313 | /* 117294 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42314 | /* 117297 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42315 | /* 117301 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42316 | /* 117306 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42317 | /* 117310 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42318 | /* 117315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOS), |
| 42319 | /* 117318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42320 | /* 117320 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42321 | /* 117323 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42322 | /* 117326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42323 | /* 117332 */ GIR_RootConstrainSelectedInstOperands, |
| 42324 | /* 117333 */ // GIR_Coverage, 2625, |
| 42325 | /* 117333 */ GIR_EraseRootFromParent_Done, |
| 42326 | /* 117334 */ // Label 3540: @117334 |
| 42327 | /* 117334 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3541*/ GIMT_Encode4(117461), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3102 // |
| 42328 | /* 117341 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTu2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 42329 | /* 117341 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 42330 | /* 117344 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42331 | /* 117348 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42332 | /* 117353 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42333 | /* 117357 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42334 | /* 117362 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 42335 | /* 117365 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42336 | /* 117369 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42337 | /* 117374 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 42338 | /* 117376 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 42339 | /* 117379 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42340 | /* 117383 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42341 | /* 117388 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 42342 | /* 117391 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 42343 | /* 117394 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 42344 | /* 117397 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42345 | /* 117402 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42346 | /* 117407 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 42347 | /* 117412 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 42348 | /* 117415 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd), |
| 42349 | /* 117419 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42350 | /* 117424 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 42351 | /* 117427 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42352 | /* 117430 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42353 | /* 117436 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42354 | /* 117438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42355 | /* 117441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42356 | /* 117443 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 42357 | /* 117450 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42358 | /* 117455 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42359 | /* 117460 */ // GIR_Coverage, 3102, |
| 42360 | /* 117460 */ GIR_EraseRootFromParent_Done, |
| 42361 | /* 117461 */ // Label 3541: @117461 |
| 42362 | /* 117461 */ GIM_Reject, |
| 42363 | /* 117462 */ // Label 3539: @117462 |
| 42364 | /* 117462 */ GIM_Reject, |
| 42365 | /* 117463 */ // Label 3532: @117463 |
| 42366 | /* 117463 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3542*/ GIMT_Encode4(117521), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2621 // |
| 42367 | /* 117470 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42368 | /* 117473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42369 | /* 117477 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42370 | /* 117481 */ // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VUITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 42371 | /* 117481 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42372 | /* 117484 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42373 | /* 117488 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42374 | /* 117493 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42375 | /* 117497 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42376 | /* 117502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOD), |
| 42377 | /* 117505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42378 | /* 117507 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42379 | /* 117510 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42380 | /* 117513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42381 | /* 117519 */ GIR_RootConstrainSelectedInstOperands, |
| 42382 | /* 117520 */ // GIR_Coverage, 2621, |
| 42383 | /* 117520 */ GIR_EraseRootFromParent_Done, |
| 42384 | /* 117521 */ // Label 3542: @117521 |
| 42385 | /* 117521 */ GIM_Reject, |
| 42386 | /* 117522 */ // Label 3533: @117522 |
| 42387 | /* 117522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3543*/ GIMT_Encode4(117558), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1777 // |
| 42388 | /* 117529 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42389 | /* 117532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42390 | /* 117536 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42391 | /* 117540 */ // (uint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) |
| 42392 | /* 117540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hd), |
| 42393 | /* 117543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42394 | /* 117545 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42395 | /* 117547 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42396 | /* 117550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42397 | /* 117556 */ GIR_RootConstrainSelectedInstOperands, |
| 42398 | /* 117557 */ // GIR_Coverage, 1777, |
| 42399 | /* 117557 */ GIR_EraseRootFromParent_Done, |
| 42400 | /* 117558 */ // Label 3543: @117558 |
| 42401 | /* 117558 */ GIM_Reject, |
| 42402 | /* 117559 */ // Label 3534: @117559 |
| 42403 | /* 117559 */ GIM_Try, /*On fail goto*//*Label 3544*/ GIMT_Encode4(117655), |
| 42404 | /* 117564 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42405 | /* 117567 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3545*/ GIMT_Encode4(117600), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1781 // |
| 42406 | /* 117574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42407 | /* 117578 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42408 | /* 117582 */ // (uint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) |
| 42409 | /* 117582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hq), |
| 42410 | /* 117585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42411 | /* 117587 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42412 | /* 117589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42413 | /* 117592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42414 | /* 117598 */ GIR_RootConstrainSelectedInstOperands, |
| 42415 | /* 117599 */ // GIR_Coverage, 1781, |
| 42416 | /* 117599 */ GIR_EraseRootFromParent_Done, |
| 42417 | /* 117600 */ // Label 3545: @117600 |
| 42418 | /* 117600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3546*/ GIMT_Encode4(117654), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4556 // |
| 42419 | /* 117607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42420 | /* 117611 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42421 | /* 117615 */ // (uint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 42422 | /* 117615 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42423 | /* 117618 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42424 | /* 117622 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42425 | /* 117627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n), |
| 42426 | /* 117630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42427 | /* 117632 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42428 | /* 117634 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42429 | /* 117637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42430 | /* 117643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42431 | /* 117649 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42432 | /* 117652 */ GIR_RootConstrainSelectedInstOperands, |
| 42433 | /* 117653 */ // GIR_Coverage, 4556, |
| 42434 | /* 117653 */ GIR_EraseRootFromParent_Done, |
| 42435 | /* 117654 */ // Label 3546: @117654 |
| 42436 | /* 117654 */ GIM_Reject, |
| 42437 | /* 117655 */ // Label 3544: @117655 |
| 42438 | /* 117655 */ GIM_Reject, |
| 42439 | /* 117656 */ // Label 3535: @117656 |
| 42440 | /* 117656 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3547*/ GIMT_Encode4(117692), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1769 // |
| 42441 | /* 117663 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42442 | /* 117666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42443 | /* 117670 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42444 | /* 117674 */ // (uint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) |
| 42445 | /* 117674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd), |
| 42446 | /* 117677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42447 | /* 117679 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42448 | /* 117681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42449 | /* 117684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42450 | /* 117690 */ GIR_RootConstrainSelectedInstOperands, |
| 42451 | /* 117691 */ // GIR_Coverage, 1769, |
| 42452 | /* 117691 */ GIR_EraseRootFromParent_Done, |
| 42453 | /* 117692 */ // Label 3547: @117692 |
| 42454 | /* 117692 */ GIM_Reject, |
| 42455 | /* 117693 */ // Label 3536: @117693 |
| 42456 | /* 117693 */ GIM_Try, /*On fail goto*//*Label 3548*/ GIMT_Encode4(117789), |
| 42457 | /* 117698 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42458 | /* 117701 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3549*/ GIMT_Encode4(117734), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1773 // |
| 42459 | /* 117708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42460 | /* 117712 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42461 | /* 117716 */ // (uint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) |
| 42462 | /* 117716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fq), |
| 42463 | /* 117719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42464 | /* 117721 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42465 | /* 117723 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42466 | /* 117726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42467 | /* 117732 */ GIR_RootConstrainSelectedInstOperands, |
| 42468 | /* 117733 */ // GIR_Coverage, 1773, |
| 42469 | /* 117733 */ GIR_EraseRootFromParent_Done, |
| 42470 | /* 117734 */ // Label 3549: @117734 |
| 42471 | /* 117734 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3550*/ GIMT_Encode4(117788), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4562 // |
| 42472 | /* 117741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42473 | /* 117745 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42474 | /* 117749 */ // (uint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 42475 | /* 117749 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42476 | /* 117752 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42477 | /* 117756 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42478 | /* 117761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n), |
| 42479 | /* 117764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42480 | /* 117766 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42481 | /* 117768 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42482 | /* 117771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42483 | /* 117777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42484 | /* 117783 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42485 | /* 117786 */ GIR_RootConstrainSelectedInstOperands, |
| 42486 | /* 117787 */ // GIR_Coverage, 4562, |
| 42487 | /* 117787 */ GIR_EraseRootFromParent_Done, |
| 42488 | /* 117788 */ // Label 3550: @117788 |
| 42489 | /* 117788 */ GIM_Reject, |
| 42490 | /* 117789 */ // Label 3548: @117789 |
| 42491 | /* 117789 */ GIM_Reject, |
| 42492 | /* 117790 */ // Label 3537: @117790 |
| 42493 | /* 117790 */ GIM_Reject, |
| 42494 | /* 117791 */ // Label 52: @117791 |
| 42495 | /* 117791 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3554*/ GIMT_Encode4(118153), |
| 42496 | /* 117802 */ /*GILLT_s32*//*Label 3551*/ GIMT_Encode4(117850), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42497 | /* 117838 */ /*GILLT_v8s16*//*Label 3552*/ GIMT_Encode4(118045), GIMT_Encode4(0), |
| 42498 | /* 117846 */ /*GILLT_v4s32*//*Label 3553*/ GIMT_Encode4(118099), |
| 42499 | /* 117850 */ // Label 3551: @117850 |
| 42500 | /* 117850 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3558*/ GIMT_Encode4(118044), |
| 42501 | /* 117861 */ /*GILLT_s16*//*Label 3555*/ GIMT_Encode4(117873), |
| 42502 | /* 117865 */ /*GILLT_s32*//*Label 3556*/ GIMT_Encode4(117930), |
| 42503 | /* 117869 */ /*GILLT_s64*//*Label 3557*/ GIMT_Encode4(117987), |
| 42504 | /* 117873 */ // Label 3555: @117873 |
| 42505 | /* 117873 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3559*/ GIMT_Encode4(117929), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2644 // |
| 42506 | /* 117880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42507 | /* 117884 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42508 | /* 117888 */ // (fp_to_sint_sat:{ *:[i32] } HPR:{ *:[f16] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 42509 | /* 117888 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42510 | /* 117891 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZH), |
| 42511 | /* 117895 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42512 | /* 117900 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42513 | /* 117904 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42514 | /* 117907 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42515 | /* 117913 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42516 | /* 117915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42517 | /* 117918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42518 | /* 117920 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42519 | /* 117923 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 42520 | /* 117928 */ // GIR_Coverage, 2644, |
| 42521 | /* 117928 */ GIR_EraseRootFromParent_Done, |
| 42522 | /* 117929 */ // Label 3559: @117929 |
| 42523 | /* 117929 */ GIM_Reject, |
| 42524 | /* 117930 */ // Label 3556: @117930 |
| 42525 | /* 117930 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3560*/ GIMT_Encode4(117986), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2638 // |
| 42526 | /* 117937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42527 | /* 117941 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42528 | /* 117945 */ // (fp_to_sint_sat:{ *:[i32] } SPR:{ *:[f32] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 42529 | /* 117945 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42530 | /* 117948 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZS), |
| 42531 | /* 117952 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42532 | /* 117957 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42533 | /* 117961 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42534 | /* 117964 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42535 | /* 117970 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42536 | /* 117972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42537 | /* 117975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42538 | /* 117977 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42539 | /* 117980 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 42540 | /* 117985 */ // GIR_Coverage, 2638, |
| 42541 | /* 117985 */ GIR_EraseRootFromParent_Done, |
| 42542 | /* 117986 */ // Label 3560: @117986 |
| 42543 | /* 117986 */ GIM_Reject, |
| 42544 | /* 117987 */ // Label 3557: @117987 |
| 42545 | /* 117987 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3561*/ GIMT_Encode4(118043), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2632 // |
| 42546 | /* 117994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42547 | /* 117998 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42548 | /* 118002 */ // (fp_to_sint_sat:{ *:[i32] } DPR:{ *:[f64] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 42549 | /* 118002 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42550 | /* 118005 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZD), |
| 42551 | /* 118009 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42552 | /* 118014 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42553 | /* 118018 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42554 | /* 118021 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42555 | /* 118027 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42556 | /* 118029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42557 | /* 118032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42558 | /* 118034 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42559 | /* 118037 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 42560 | /* 118042 */ // GIR_Coverage, 2632, |
| 42561 | /* 118042 */ GIR_EraseRootFromParent_Done, |
| 42562 | /* 118043 */ // Label 3561: @118043 |
| 42563 | /* 118043 */ GIM_Reject, |
| 42564 | /* 118044 */ // Label 3558: @118044 |
| 42565 | /* 118044 */ GIM_Reject, |
| 42566 | /* 118045 */ // Label 3552: @118045 |
| 42567 | /* 118045 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3562*/ GIMT_Encode4(118098), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4567 // |
| 42568 | /* 118052 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42569 | /* 118055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42570 | /* 118059 */ // (fp_to_sint_sat:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, i16:{ *:[Other] }) => (MVE_VCVTs16f16z:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) |
| 42571 | /* 118059 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42572 | /* 118062 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42573 | /* 118066 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42574 | /* 118071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z), |
| 42575 | /* 118074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42576 | /* 118076 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42577 | /* 118078 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42578 | /* 118081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42579 | /* 118087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42580 | /* 118093 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42581 | /* 118096 */ GIR_RootConstrainSelectedInstOperands, |
| 42582 | /* 118097 */ // GIR_Coverage, 4567, |
| 42583 | /* 118097 */ GIR_EraseRootFromParent_Done, |
| 42584 | /* 118098 */ // Label 3562: @118098 |
| 42585 | /* 118098 */ GIM_Reject, |
| 42586 | /* 118099 */ // Label 3553: @118099 |
| 42587 | /* 118099 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3563*/ GIMT_Encode4(118152), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4565 // |
| 42588 | /* 118106 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42589 | /* 118109 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42590 | /* 118113 */ // (fp_to_sint_sat:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, i32:{ *:[Other] }) => (MVE_VCVTs32f32z:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) |
| 42591 | /* 118113 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42592 | /* 118116 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42593 | /* 118120 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42594 | /* 118125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z), |
| 42595 | /* 118128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42596 | /* 118130 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42597 | /* 118132 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42598 | /* 118135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42599 | /* 118141 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42600 | /* 118147 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42601 | /* 118150 */ GIR_RootConstrainSelectedInstOperands, |
| 42602 | /* 118151 */ // GIR_Coverage, 4565, |
| 42603 | /* 118151 */ GIR_EraseRootFromParent_Done, |
| 42604 | /* 118152 */ // Label 3563: @118152 |
| 42605 | /* 118152 */ GIM_Reject, |
| 42606 | /* 118153 */ // Label 3554: @118153 |
| 42607 | /* 118153 */ GIM_Reject, |
| 42608 | /* 118154 */ // Label 53: @118154 |
| 42609 | /* 118154 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3567*/ GIMT_Encode4(118516), |
| 42610 | /* 118165 */ /*GILLT_s32*//*Label 3564*/ GIMT_Encode4(118213), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42611 | /* 118201 */ /*GILLT_v8s16*//*Label 3565*/ GIMT_Encode4(118408), GIMT_Encode4(0), |
| 42612 | /* 118209 */ /*GILLT_v4s32*//*Label 3566*/ GIMT_Encode4(118462), |
| 42613 | /* 118213 */ // Label 3564: @118213 |
| 42614 | /* 118213 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3571*/ GIMT_Encode4(118407), |
| 42615 | /* 118224 */ /*GILLT_s16*//*Label 3568*/ GIMT_Encode4(118236), |
| 42616 | /* 118228 */ /*GILLT_s32*//*Label 3569*/ GIMT_Encode4(118293), |
| 42617 | /* 118232 */ /*GILLT_s64*//*Label 3570*/ GIMT_Encode4(118350), |
| 42618 | /* 118236 */ // Label 3568: @118236 |
| 42619 | /* 118236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3572*/ GIMT_Encode4(118292), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2659 // |
| 42620 | /* 118243 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42621 | /* 118247 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42622 | /* 118251 */ // (fp_to_uint_sat:{ *:[i32] } HPR:{ *:[f16] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 42623 | /* 118251 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42624 | /* 118254 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZH), |
| 42625 | /* 118258 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42626 | /* 118263 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42627 | /* 118267 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42628 | /* 118270 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42629 | /* 118276 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42630 | /* 118278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42631 | /* 118281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42632 | /* 118283 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42633 | /* 118286 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 42634 | /* 118291 */ // GIR_Coverage, 2659, |
| 42635 | /* 118291 */ GIR_EraseRootFromParent_Done, |
| 42636 | /* 118292 */ // Label 3572: @118292 |
| 42637 | /* 118292 */ GIM_Reject, |
| 42638 | /* 118293 */ // Label 3569: @118293 |
| 42639 | /* 118293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3573*/ GIMT_Encode4(118349), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2653 // |
| 42640 | /* 118300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42641 | /* 118304 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42642 | /* 118308 */ // (fp_to_uint_sat:{ *:[i32] } SPR:{ *:[f32] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 42643 | /* 118308 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42644 | /* 118311 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZS), |
| 42645 | /* 118315 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42646 | /* 118320 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42647 | /* 118324 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42648 | /* 118327 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42649 | /* 118333 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42650 | /* 118335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42651 | /* 118338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42652 | /* 118340 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42653 | /* 118343 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 42654 | /* 118348 */ // GIR_Coverage, 2653, |
| 42655 | /* 118348 */ GIR_EraseRootFromParent_Done, |
| 42656 | /* 118349 */ // Label 3573: @118349 |
| 42657 | /* 118349 */ GIM_Reject, |
| 42658 | /* 118350 */ // Label 3570: @118350 |
| 42659 | /* 118350 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3574*/ GIMT_Encode4(118406), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2647 // |
| 42660 | /* 118357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42661 | /* 118361 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42662 | /* 118365 */ // (fp_to_uint_sat:{ *:[i32] } DPR:{ *:[f64] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 42663 | /* 118365 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42664 | /* 118368 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZD), |
| 42665 | /* 118372 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42666 | /* 118377 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42667 | /* 118381 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42668 | /* 118384 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42669 | /* 118390 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42670 | /* 118392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42671 | /* 118395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42672 | /* 118397 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42673 | /* 118400 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 42674 | /* 118405 */ // GIR_Coverage, 2647, |
| 42675 | /* 118405 */ GIR_EraseRootFromParent_Done, |
| 42676 | /* 118406 */ // Label 3574: @118406 |
| 42677 | /* 118406 */ GIM_Reject, |
| 42678 | /* 118407 */ // Label 3571: @118407 |
| 42679 | /* 118407 */ GIM_Reject, |
| 42680 | /* 118408 */ // Label 3565: @118408 |
| 42681 | /* 118408 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3575*/ GIMT_Encode4(118461), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4568 // |
| 42682 | /* 118415 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42683 | /* 118418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42684 | /* 118422 */ // (fp_to_uint_sat:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, i16:{ *:[Other] }) => (MVE_VCVTu16f16z:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) |
| 42685 | /* 118422 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42686 | /* 118425 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42687 | /* 118429 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42688 | /* 118434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z), |
| 42689 | /* 118437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42690 | /* 118439 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42691 | /* 118441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42692 | /* 118444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42693 | /* 118450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42694 | /* 118456 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42695 | /* 118459 */ GIR_RootConstrainSelectedInstOperands, |
| 42696 | /* 118460 */ // GIR_Coverage, 4568, |
| 42697 | /* 118460 */ GIR_EraseRootFromParent_Done, |
| 42698 | /* 118461 */ // Label 3575: @118461 |
| 42699 | /* 118461 */ GIM_Reject, |
| 42700 | /* 118462 */ // Label 3566: @118462 |
| 42701 | /* 118462 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3576*/ GIMT_Encode4(118515), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4566 // |
| 42702 | /* 118469 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42703 | /* 118472 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42704 | /* 118476 */ // (fp_to_uint_sat:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, i32:{ *:[Other] }) => (MVE_VCVTu32f32z:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) |
| 42705 | /* 118476 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42706 | /* 118479 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42707 | /* 118483 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42708 | /* 118488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z), |
| 42709 | /* 118491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42710 | /* 118493 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42711 | /* 118495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42712 | /* 118498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42713 | /* 118504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42714 | /* 118510 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42715 | /* 118513 */ GIR_RootConstrainSelectedInstOperands, |
| 42716 | /* 118514 */ // GIR_Coverage, 4566, |
| 42717 | /* 118514 */ GIR_EraseRootFromParent_Done, |
| 42718 | /* 118515 */ // Label 3576: @118515 |
| 42719 | /* 118515 */ GIM_Reject, |
| 42720 | /* 118516 */ // Label 3567: @118516 |
| 42721 | /* 118516 */ GIM_Reject, |
| 42722 | /* 118517 */ // Label 54: @118517 |
| 42723 | /* 118517 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3584*/ GIMT_Encode4(119280), |
| 42724 | /* 118528 */ /*GILLT_s16*//*Label 3577*/ GIMT_Encode4(118580), |
| 42725 | /* 118532 */ /*GILLT_s32*//*Label 3578*/ GIMT_Encode4(118617), |
| 42726 | /* 118536 */ /*GILLT_s64*//*Label 3579*/ GIMT_Encode4(118807), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42727 | /* 118564 */ /*GILLT_v4s16*//*Label 3580*/ GIMT_Encode4(118844), |
| 42728 | /* 118568 */ /*GILLT_v8s16*//*Label 3581*/ GIMT_Encode4(118881), |
| 42729 | /* 118572 */ /*GILLT_v2s32*//*Label 3582*/ GIMT_Encode4(119062), |
| 42730 | /* 118576 */ /*GILLT_v4s32*//*Label 3583*/ GIMT_Encode4(119099), |
| 42731 | /* 118580 */ // Label 3577: @118580 |
| 42732 | /* 118580 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3585*/ GIMT_Encode4(118616), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 678 // |
| 42733 | /* 118587 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 42734 | /* 118590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42735 | /* 118594 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42736 | /* 118598 */ // (fabs:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VABSH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 42737 | /* 118598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSH), |
| 42738 | /* 118601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42739 | /* 118603 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 42740 | /* 118605 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42741 | /* 118608 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42742 | /* 118614 */ GIR_RootConstrainSelectedInstOperands, |
| 42743 | /* 118615 */ // GIR_Coverage, 678, |
| 42744 | /* 118615 */ GIR_EraseRootFromParent_Done, |
| 42745 | /* 118616 */ // Label 3585: @118616 |
| 42746 | /* 118616 */ GIM_Reject, |
| 42747 | /* 118617 */ // Label 3578: @118617 |
| 42748 | /* 118617 */ GIM_Try, /*On fail goto*//*Label 3586*/ GIMT_Encode4(118806), |
| 42749 | /* 118622 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42750 | /* 118625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42751 | /* 118629 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42752 | /* 118633 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3587*/ GIMT_Encode4(118658), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 677 // |
| 42753 | /* 118640 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VABSS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 42754 | /* 118640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSS), |
| 42755 | /* 118643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42756 | /* 118645 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 42757 | /* 118647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42758 | /* 118650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42759 | /* 118656 */ GIR_RootConstrainSelectedInstOperands, |
| 42760 | /* 118657 */ // GIR_Coverage, 677, |
| 42761 | /* 118657 */ GIR_EraseRootFromParent_Done, |
| 42762 | /* 118658 */ // Label 3587: @118658 |
| 42763 | /* 118658 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3588*/ GIMT_Encode4(118805), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3093 // |
| 42764 | /* 118665 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VABSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 42765 | /* 118665 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 42766 | /* 118668 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42767 | /* 118672 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42768 | /* 118677 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 42769 | /* 118679 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 42770 | /* 118682 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42771 | /* 118686 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42772 | /* 118691 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 42773 | /* 118694 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42774 | /* 118699 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 42775 | /* 118702 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42776 | /* 118706 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42777 | /* 118711 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 42778 | /* 118714 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42779 | /* 118718 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 42780 | /* 118721 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42781 | /* 118726 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42782 | /* 118731 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 42783 | /* 118736 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 42784 | /* 118739 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VABSfd), |
| 42785 | /* 118743 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42786 | /* 118748 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 42787 | /* 118751 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 42788 | /* 118754 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42789 | /* 118760 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 42790 | /* 118762 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 42791 | /* 118765 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42792 | /* 118769 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42793 | /* 118774 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 42794 | /* 118777 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42795 | /* 118782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42796 | /* 118785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42797 | /* 118787 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 42798 | /* 118794 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42799 | /* 118799 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42800 | /* 118804 */ // GIR_Coverage, 3093, |
| 42801 | /* 118804 */ GIR_EraseRootFromParent_Done, |
| 42802 | /* 118805 */ // Label 3588: @118805 |
| 42803 | /* 118805 */ GIM_Reject, |
| 42804 | /* 118806 */ // Label 3586: @118806 |
| 42805 | /* 118806 */ GIM_Reject, |
| 42806 | /* 118807 */ // Label 3579: @118807 |
| 42807 | /* 118807 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3589*/ GIMT_Encode4(118843), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 676 // |
| 42808 | /* 118814 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 42809 | /* 118817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42810 | /* 118821 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42811 | /* 118825 */ // (fabs:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VABSD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 42812 | /* 118825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSD), |
| 42813 | /* 118828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42814 | /* 118830 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 42815 | /* 118832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42816 | /* 118835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42817 | /* 118841 */ GIR_RootConstrainSelectedInstOperands, |
| 42818 | /* 118842 */ // GIR_Coverage, 676, |
| 42819 | /* 118842 */ GIR_EraseRootFromParent_Done, |
| 42820 | /* 118843 */ // Label 3589: @118843 |
| 42821 | /* 118843 */ GIM_Reject, |
| 42822 | /* 118844 */ // Label 3580: @118844 |
| 42823 | /* 118844 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3590*/ GIMT_Encode4(118880), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1678 // |
| 42824 | /* 118851 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42825 | /* 118854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42826 | /* 118858 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42827 | /* 118862 */ // (fabs:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VABShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 42828 | /* 118862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShd), |
| 42829 | /* 118865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42830 | /* 118867 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42831 | /* 118869 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42832 | /* 118872 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42833 | /* 118878 */ GIR_RootConstrainSelectedInstOperands, |
| 42834 | /* 118879 */ // GIR_Coverage, 1678, |
| 42835 | /* 118879 */ GIR_EraseRootFromParent_Done, |
| 42836 | /* 118880 */ // Label 3590: @118880 |
| 42837 | /* 118880 */ GIM_Reject, |
| 42838 | /* 118881 */ // Label 3581: @118881 |
| 42839 | /* 118881 */ GIM_Try, /*On fail goto*//*Label 3591*/ GIMT_Encode4(119061), |
| 42840 | /* 118886 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42841 | /* 118889 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3592*/ GIMT_Encode4(118973), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4491 // |
| 42842 | /* 118896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42843 | /* 118900 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42844 | /* 118904 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB), |
| 42845 | /* 118908 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42846 | /* 118912 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42847 | /* 118916 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42848 | /* 118921 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42849 | /* 118926 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42850 | /* 118928 */ // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 42851 | /* 118928 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42852 | /* 118931 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42853 | /* 118935 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42854 | /* 118940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16), |
| 42855 | /* 118943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42856 | /* 118945 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 42857 | /* 118949 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn |
| 42858 | /* 118953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42859 | /* 118956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42860 | /* 118962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42861 | /* 118968 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42862 | /* 118971 */ GIR_RootConstrainSelectedInstOperands, |
| 42863 | /* 118972 */ // GIR_Coverage, 4491, |
| 42864 | /* 118972 */ GIR_EraseRootFromParent_Done, |
| 42865 | /* 118973 */ // Label 3592: @118973 |
| 42866 | /* 118973 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3593*/ GIMT_Encode4(119006), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1679 // |
| 42867 | /* 118980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42868 | /* 118984 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42869 | /* 118988 */ // (fabs:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VABShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 42870 | /* 118988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShq), |
| 42871 | /* 118991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42872 | /* 118993 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42873 | /* 118995 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42874 | /* 118998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42875 | /* 119004 */ GIR_RootConstrainSelectedInstOperands, |
| 42876 | /* 119005 */ // GIR_Coverage, 1679, |
| 42877 | /* 119005 */ GIR_EraseRootFromParent_Done, |
| 42878 | /* 119006 */ // Label 3593: @119006 |
| 42879 | /* 119006 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3594*/ GIMT_Encode4(119060), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4569 // |
| 42880 | /* 119013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42881 | /* 119017 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42882 | /* 119021 */ // (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VABSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v) |
| 42883 | /* 119021 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42884 | /* 119024 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42885 | /* 119028 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42886 | /* 119033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf16), |
| 42887 | /* 119036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42888 | /* 119038 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 42889 | /* 119040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42890 | /* 119043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42891 | /* 119049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42892 | /* 119055 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42893 | /* 119058 */ GIR_RootConstrainSelectedInstOperands, |
| 42894 | /* 119059 */ // GIR_Coverage, 4569, |
| 42895 | /* 119059 */ GIR_EraseRootFromParent_Done, |
| 42896 | /* 119060 */ // Label 3594: @119060 |
| 42897 | /* 119060 */ GIM_Reject, |
| 42898 | /* 119061 */ // Label 3591: @119061 |
| 42899 | /* 119061 */ GIM_Reject, |
| 42900 | /* 119062 */ // Label 3582: @119062 |
| 42901 | /* 119062 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3595*/ GIMT_Encode4(119098), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1676 // |
| 42902 | /* 119069 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42903 | /* 119072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42904 | /* 119076 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42905 | /* 119080 */ // (fabs:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VABSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 42906 | /* 119080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfd), |
| 42907 | /* 119083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42908 | /* 119085 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42909 | /* 119087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42910 | /* 119090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42911 | /* 119096 */ GIR_RootConstrainSelectedInstOperands, |
| 42912 | /* 119097 */ // GIR_Coverage, 1676, |
| 42913 | /* 119097 */ GIR_EraseRootFromParent_Done, |
| 42914 | /* 119098 */ // Label 3595: @119098 |
| 42915 | /* 119098 */ GIM_Reject, |
| 42916 | /* 119099 */ // Label 3583: @119099 |
| 42917 | /* 119099 */ GIM_Try, /*On fail goto*//*Label 3596*/ GIMT_Encode4(119279), |
| 42918 | /* 119104 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42919 | /* 119107 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3597*/ GIMT_Encode4(119191), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4492 // |
| 42920 | /* 119114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42921 | /* 119118 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42922 | /* 119122 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB), |
| 42923 | /* 119126 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42924 | /* 119130 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42925 | /* 119134 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42926 | /* 119139 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42927 | /* 119144 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42928 | /* 119146 */ // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 42929 | /* 119146 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42930 | /* 119149 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42931 | /* 119153 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42932 | /* 119158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32), |
| 42933 | /* 119161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42934 | /* 119163 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 42935 | /* 119167 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn |
| 42936 | /* 119171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42937 | /* 119174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42938 | /* 119180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42939 | /* 119186 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42940 | /* 119189 */ GIR_RootConstrainSelectedInstOperands, |
| 42941 | /* 119190 */ // GIR_Coverage, 4492, |
| 42942 | /* 119190 */ GIR_EraseRootFromParent_Done, |
| 42943 | /* 119191 */ // Label 3597: @119191 |
| 42944 | /* 119191 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3598*/ GIMT_Encode4(119224), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1677 // |
| 42945 | /* 119198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42946 | /* 119202 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42947 | /* 119206 */ // (fabs:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VABSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 42948 | /* 119206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfq), |
| 42949 | /* 119209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42950 | /* 119211 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42951 | /* 119213 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42952 | /* 119216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42953 | /* 119222 */ GIR_RootConstrainSelectedInstOperands, |
| 42954 | /* 119223 */ // GIR_Coverage, 1677, |
| 42955 | /* 119223 */ GIR_EraseRootFromParent_Done, |
| 42956 | /* 119224 */ // Label 3598: @119224 |
| 42957 | /* 119224 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3599*/ GIMT_Encode4(119278), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4571 // |
| 42958 | /* 119231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42959 | /* 119235 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42960 | /* 119239 */ // (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VABSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v) |
| 42961 | /* 119239 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42962 | /* 119242 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42963 | /* 119246 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42964 | /* 119251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf32), |
| 42965 | /* 119254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42966 | /* 119256 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 42967 | /* 119258 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42968 | /* 119261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42969 | /* 119267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42970 | /* 119273 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42971 | /* 119276 */ GIR_RootConstrainSelectedInstOperands, |
| 42972 | /* 119277 */ // GIR_Coverage, 4571, |
| 42973 | /* 119277 */ GIR_EraseRootFromParent_Done, |
| 42974 | /* 119278 */ // Label 3599: @119278 |
| 42975 | /* 119278 */ GIM_Reject, |
| 42976 | /* 119279 */ // Label 3596: @119279 |
| 42977 | /* 119279 */ GIM_Reject, |
| 42978 | /* 119280 */ // Label 3584: @119280 |
| 42979 | /* 119280 */ GIM_Reject, |
| 42980 | /* 119281 */ // Label 55: @119281 |
| 42981 | /* 119281 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3607*/ GIMT_Encode4(119861), |
| 42982 | /* 119292 */ /*GILLT_s16*//*Label 3600*/ GIMT_Encode4(119344), |
| 42983 | /* 119296 */ /*GILLT_s32*//*Label 3601*/ GIMT_Encode4(119377), |
| 42984 | /* 119300 */ /*GILLT_s64*//*Label 3602*/ GIMT_Encode4(119410), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42985 | /* 119328 */ /*GILLT_v4s16*//*Label 3603*/ GIMT_Encode4(119443), |
| 42986 | /* 119332 */ /*GILLT_v8s16*//*Label 3604*/ GIMT_Encode4(119476), |
| 42987 | /* 119336 */ /*GILLT_v2s32*//*Label 3605*/ GIMT_Encode4(119652), |
| 42988 | /* 119340 */ /*GILLT_v4s32*//*Label 3606*/ GIMT_Encode4(119685), |
| 42989 | /* 119344 */ // Label 3600: @119344 |
| 42990 | /* 119344 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3608*/ GIMT_Encode4(119376), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 665 // |
| 42991 | /* 119351 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 42992 | /* 119354 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 42993 | /* 119357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42994 | /* 119361 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42995 | /* 119365 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42996 | /* 119369 */ // (fminnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMINNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 42997 | /* 119369 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMH), |
| 42998 | /* 119374 */ GIR_RootConstrainSelectedInstOperands, |
| 42999 | /* 119375 */ // GIR_Coverage, 665, |
| 43000 | /* 119375 */ GIR_Done, |
| 43001 | /* 119376 */ // Label 3608: @119376 |
| 43002 | /* 119376 */ GIM_Reject, |
| 43003 | /* 119377 */ // Label 3601: @119377 |
| 43004 | /* 119377 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3609*/ GIMT_Encode4(119409), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 667 // |
| 43005 | /* 119384 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 43006 | /* 119387 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43007 | /* 119390 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43008 | /* 119394 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43009 | /* 119398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43010 | /* 119402 */ // (fminnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMINNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 43011 | /* 119402 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMS), |
| 43012 | /* 119407 */ GIR_RootConstrainSelectedInstOperands, |
| 43013 | /* 119408 */ // GIR_Coverage, 667, |
| 43014 | /* 119408 */ GIR_Done, |
| 43015 | /* 119409 */ // Label 3609: @119409 |
| 43016 | /* 119409 */ GIM_Reject, |
| 43017 | /* 119410 */ // Label 3602: @119410 |
| 43018 | /* 119410 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3610*/ GIMT_Encode4(119442), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 669 // |
| 43019 | /* 119417 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 43020 | /* 119420 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 43021 | /* 119423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43022 | /* 119427 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43023 | /* 119431 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43024 | /* 119435 */ // (fminnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMINNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 43025 | /* 119435 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMD), |
| 43026 | /* 119440 */ GIR_RootConstrainSelectedInstOperands, |
| 43027 | /* 119441 */ // GIR_Coverage, 669, |
| 43028 | /* 119441 */ GIR_Done, |
| 43029 | /* 119442 */ // Label 3610: @119442 |
| 43030 | /* 119442 */ GIM_Reject, |
| 43031 | /* 119443 */ // Label 3603: @119443 |
| 43032 | /* 119443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3611*/ GIMT_Encode4(119475), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1397 // |
| 43033 | /* 119450 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43034 | /* 119453 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43035 | /* 119456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43036 | /* 119460 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43037 | /* 119464 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43038 | /* 119468 */ // (fminnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMINNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 43039 | /* 119468 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDh), |
| 43040 | /* 119473 */ GIR_RootConstrainSelectedInstOperands, |
| 43041 | /* 119474 */ // GIR_Coverage, 1397, |
| 43042 | /* 119474 */ GIR_Done, |
| 43043 | /* 119475 */ // Label 3611: @119475 |
| 43044 | /* 119475 */ GIM_Reject, |
| 43045 | /* 119476 */ // Label 3604: @119476 |
| 43046 | /* 119476 */ GIM_Try, /*On fail goto*//*Label 3612*/ GIMT_Encode4(119651), |
| 43047 | /* 119481 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43048 | /* 119484 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43049 | /* 119487 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3613*/ GIMT_Encode4(119564), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4586 // |
| 43050 | /* 119494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43051 | /* 119498 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43052 | /* 119502 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43053 | /* 119506 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43054 | /* 119510 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43055 | /* 119515 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 43056 | /* 119519 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43057 | /* 119523 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43058 | /* 119527 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43059 | /* 119532 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43060 | /* 119534 */ // (fminnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 43061 | /* 119534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16), |
| 43062 | /* 119537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43063 | /* 119539 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 43064 | /* 119543 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 43065 | /* 119547 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43066 | /* 119550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43067 | /* 119556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43068 | /* 119562 */ GIR_RootConstrainSelectedInstOperands, |
| 43069 | /* 119563 */ // GIR_Coverage, 4586, |
| 43070 | /* 119563 */ GIR_EraseRootFromParent_Done, |
| 43071 | /* 119564 */ // Label 3613: @119564 |
| 43072 | /* 119564 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3614*/ GIMT_Encode4(119590), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1398 // |
| 43073 | /* 119571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43074 | /* 119575 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43075 | /* 119579 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43076 | /* 119583 */ // (fminnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMINNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 43077 | /* 119583 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQh), |
| 43078 | /* 119588 */ GIR_RootConstrainSelectedInstOperands, |
| 43079 | /* 119589 */ // GIR_Coverage, 1398, |
| 43080 | /* 119589 */ GIR_Done, |
| 43081 | /* 119590 */ // Label 3614: @119590 |
| 43082 | /* 119590 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3615*/ GIMT_Encode4(119650), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3686 // |
| 43083 | /* 119597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43084 | /* 119601 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43085 | /* 119605 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43086 | /* 119609 */ // (fminnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 43087 | /* 119609 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43088 | /* 119612 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43089 | /* 119616 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43090 | /* 119621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16), |
| 43091 | /* 119624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43092 | /* 119626 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43093 | /* 119628 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43094 | /* 119630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43095 | /* 119633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43096 | /* 119639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43097 | /* 119645 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43098 | /* 119648 */ GIR_RootConstrainSelectedInstOperands, |
| 43099 | /* 119649 */ // GIR_Coverage, 3686, |
| 43100 | /* 119649 */ GIR_EraseRootFromParent_Done, |
| 43101 | /* 119650 */ // Label 3615: @119650 |
| 43102 | /* 119650 */ GIM_Reject, |
| 43103 | /* 119651 */ // Label 3612: @119651 |
| 43104 | /* 119651 */ GIM_Reject, |
| 43105 | /* 119652 */ // Label 3605: @119652 |
| 43106 | /* 119652 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3616*/ GIMT_Encode4(119684), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1395 // |
| 43107 | /* 119659 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43108 | /* 119662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43109 | /* 119665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43110 | /* 119669 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43111 | /* 119673 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43112 | /* 119677 */ // (fminnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMINNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 43113 | /* 119677 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDf), |
| 43114 | /* 119682 */ GIR_RootConstrainSelectedInstOperands, |
| 43115 | /* 119683 */ // GIR_Coverage, 1395, |
| 43116 | /* 119683 */ GIR_Done, |
| 43117 | /* 119684 */ // Label 3616: @119684 |
| 43118 | /* 119684 */ GIM_Reject, |
| 43119 | /* 119685 */ // Label 3606: @119685 |
| 43120 | /* 119685 */ GIM_Try, /*On fail goto*//*Label 3617*/ GIMT_Encode4(119860), |
| 43121 | /* 119690 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43122 | /* 119693 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43123 | /* 119696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3618*/ GIMT_Encode4(119773), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4583 // |
| 43124 | /* 119703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43125 | /* 119707 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43126 | /* 119711 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43127 | /* 119715 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43128 | /* 119719 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43129 | /* 119724 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 43130 | /* 119728 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43131 | /* 119732 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43132 | /* 119736 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43133 | /* 119741 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43134 | /* 119743 */ // (fminnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 43135 | /* 119743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32), |
| 43136 | /* 119746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43137 | /* 119748 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 43138 | /* 119752 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 43139 | /* 119756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43140 | /* 119759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43141 | /* 119765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43142 | /* 119771 */ GIR_RootConstrainSelectedInstOperands, |
| 43143 | /* 119772 */ // GIR_Coverage, 4583, |
| 43144 | /* 119772 */ GIR_EraseRootFromParent_Done, |
| 43145 | /* 119773 */ // Label 3618: @119773 |
| 43146 | /* 119773 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3619*/ GIMT_Encode4(119799), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1396 // |
| 43147 | /* 119780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43148 | /* 119784 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43149 | /* 119788 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43150 | /* 119792 */ // (fminnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMINNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 43151 | /* 119792 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQf), |
| 43152 | /* 119797 */ GIR_RootConstrainSelectedInstOperands, |
| 43153 | /* 119798 */ // GIR_Coverage, 1396, |
| 43154 | /* 119798 */ GIR_Done, |
| 43155 | /* 119799 */ // Label 3619: @119799 |
| 43156 | /* 119799 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3620*/ GIMT_Encode4(119859), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3681 // |
| 43157 | /* 119806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43158 | /* 119810 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43159 | /* 119814 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43160 | /* 119818 */ // (fminnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 43161 | /* 119818 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43162 | /* 119821 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43163 | /* 119825 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43164 | /* 119830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32), |
| 43165 | /* 119833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43166 | /* 119835 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43167 | /* 119837 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43168 | /* 119839 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43169 | /* 119842 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43170 | /* 119848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43171 | /* 119854 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43172 | /* 119857 */ GIR_RootConstrainSelectedInstOperands, |
| 43173 | /* 119858 */ // GIR_Coverage, 3681, |
| 43174 | /* 119858 */ GIR_EraseRootFromParent_Done, |
| 43175 | /* 119859 */ // Label 3620: @119859 |
| 43176 | /* 119859 */ GIM_Reject, |
| 43177 | /* 119860 */ // Label 3617: @119860 |
| 43178 | /* 119860 */ GIM_Reject, |
| 43179 | /* 119861 */ // Label 3607: @119861 |
| 43180 | /* 119861 */ GIM_Reject, |
| 43181 | /* 119862 */ // Label 56: @119862 |
| 43182 | /* 119862 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3628*/ GIMT_Encode4(120442), |
| 43183 | /* 119873 */ /*GILLT_s16*//*Label 3621*/ GIMT_Encode4(119925), |
| 43184 | /* 119877 */ /*GILLT_s32*//*Label 3622*/ GIMT_Encode4(119958), |
| 43185 | /* 119881 */ /*GILLT_s64*//*Label 3623*/ GIMT_Encode4(119991), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43186 | /* 119909 */ /*GILLT_v4s16*//*Label 3624*/ GIMT_Encode4(120024), |
| 43187 | /* 119913 */ /*GILLT_v8s16*//*Label 3625*/ GIMT_Encode4(120057), |
| 43188 | /* 119917 */ /*GILLT_v2s32*//*Label 3626*/ GIMT_Encode4(120233), |
| 43189 | /* 119921 */ /*GILLT_v4s32*//*Label 3627*/ GIMT_Encode4(120266), |
| 43190 | /* 119925 */ // Label 3621: @119925 |
| 43191 | /* 119925 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3629*/ GIMT_Encode4(119957), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 659 // |
| 43192 | /* 119932 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 43193 | /* 119935 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 43194 | /* 119938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43195 | /* 119942 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43196 | /* 119946 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43197 | /* 119950 */ // (fmaxnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMAXNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 43198 | /* 119950 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMH), |
| 43199 | /* 119955 */ GIR_RootConstrainSelectedInstOperands, |
| 43200 | /* 119956 */ // GIR_Coverage, 659, |
| 43201 | /* 119956 */ GIR_Done, |
| 43202 | /* 119957 */ // Label 3629: @119957 |
| 43203 | /* 119957 */ GIM_Reject, |
| 43204 | /* 119958 */ // Label 3622: @119958 |
| 43205 | /* 119958 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3630*/ GIMT_Encode4(119990), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 661 // |
| 43206 | /* 119965 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 43207 | /* 119968 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43208 | /* 119971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43209 | /* 119975 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43210 | /* 119979 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43211 | /* 119983 */ // (fmaxnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMAXNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 43212 | /* 119983 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMS), |
| 43213 | /* 119988 */ GIR_RootConstrainSelectedInstOperands, |
| 43214 | /* 119989 */ // GIR_Coverage, 661, |
| 43215 | /* 119989 */ GIR_Done, |
| 43216 | /* 119990 */ // Label 3630: @119990 |
| 43217 | /* 119990 */ GIM_Reject, |
| 43218 | /* 119991 */ // Label 3623: @119991 |
| 43219 | /* 119991 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3631*/ GIMT_Encode4(120023), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 663 // |
| 43220 | /* 119998 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 43221 | /* 120001 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 43222 | /* 120004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43223 | /* 120008 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43224 | /* 120012 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43225 | /* 120016 */ // (fmaxnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMAXNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 43226 | /* 120016 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMD), |
| 43227 | /* 120021 */ GIR_RootConstrainSelectedInstOperands, |
| 43228 | /* 120022 */ // GIR_Coverage, 663, |
| 43229 | /* 120022 */ GIR_Done, |
| 43230 | /* 120023 */ // Label 3631: @120023 |
| 43231 | /* 120023 */ GIM_Reject, |
| 43232 | /* 120024 */ // Label 3624: @120024 |
| 43233 | /* 120024 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3632*/ GIMT_Encode4(120056), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1377 // |
| 43234 | /* 120031 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43235 | /* 120034 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43236 | /* 120037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43237 | /* 120041 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43238 | /* 120045 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43239 | /* 120049 */ // (fmaxnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMAXNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 43240 | /* 120049 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDh), |
| 43241 | /* 120054 */ GIR_RootConstrainSelectedInstOperands, |
| 43242 | /* 120055 */ // GIR_Coverage, 1377, |
| 43243 | /* 120055 */ GIR_Done, |
| 43244 | /* 120056 */ // Label 3632: @120056 |
| 43245 | /* 120056 */ GIM_Reject, |
| 43246 | /* 120057 */ // Label 3625: @120057 |
| 43247 | /* 120057 */ GIM_Try, /*On fail goto*//*Label 3633*/ GIMT_Encode4(120232), |
| 43248 | /* 120062 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43249 | /* 120065 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43250 | /* 120068 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3634*/ GIMT_Encode4(120145), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4580 // |
| 43251 | /* 120075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43252 | /* 120079 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43253 | /* 120083 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43254 | /* 120087 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43255 | /* 120091 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43256 | /* 120096 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 43257 | /* 120100 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43258 | /* 120104 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43259 | /* 120108 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43260 | /* 120113 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43261 | /* 120115 */ // (fmaxnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 43262 | /* 120115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16), |
| 43263 | /* 120118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43264 | /* 120120 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 43265 | /* 120124 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 43266 | /* 120128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43267 | /* 120131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43268 | /* 120137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43269 | /* 120143 */ GIR_RootConstrainSelectedInstOperands, |
| 43270 | /* 120144 */ // GIR_Coverage, 4580, |
| 43271 | /* 120144 */ GIR_EraseRootFromParent_Done, |
| 43272 | /* 120145 */ // Label 3634: @120145 |
| 43273 | /* 120145 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3635*/ GIMT_Encode4(120171), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1378 // |
| 43274 | /* 120152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43275 | /* 120156 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43276 | /* 120160 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43277 | /* 120164 */ // (fmaxnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMAXNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 43278 | /* 120164 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQh), |
| 43279 | /* 120169 */ GIR_RootConstrainSelectedInstOperands, |
| 43280 | /* 120170 */ // GIR_Coverage, 1378, |
| 43281 | /* 120170 */ GIR_Done, |
| 43282 | /* 120171 */ // Label 3635: @120171 |
| 43283 | /* 120171 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3636*/ GIMT_Encode4(120231), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3676 // |
| 43284 | /* 120178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43285 | /* 120182 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43286 | /* 120186 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43287 | /* 120190 */ // (fmaxnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 43288 | /* 120190 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43289 | /* 120193 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43290 | /* 120197 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43291 | /* 120202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16), |
| 43292 | /* 120205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43293 | /* 120207 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43294 | /* 120209 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43295 | /* 120211 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43296 | /* 120214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43297 | /* 120220 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43298 | /* 120226 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43299 | /* 120229 */ GIR_RootConstrainSelectedInstOperands, |
| 43300 | /* 120230 */ // GIR_Coverage, 3676, |
| 43301 | /* 120230 */ GIR_EraseRootFromParent_Done, |
| 43302 | /* 120231 */ // Label 3636: @120231 |
| 43303 | /* 120231 */ GIM_Reject, |
| 43304 | /* 120232 */ // Label 3633: @120232 |
| 43305 | /* 120232 */ GIM_Reject, |
| 43306 | /* 120233 */ // Label 3626: @120233 |
| 43307 | /* 120233 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3637*/ GIMT_Encode4(120265), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1375 // |
| 43308 | /* 120240 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43309 | /* 120243 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43310 | /* 120246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43311 | /* 120250 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43312 | /* 120254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43313 | /* 120258 */ // (fmaxnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMAXNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 43314 | /* 120258 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDf), |
| 43315 | /* 120263 */ GIR_RootConstrainSelectedInstOperands, |
| 43316 | /* 120264 */ // GIR_Coverage, 1375, |
| 43317 | /* 120264 */ GIR_Done, |
| 43318 | /* 120265 */ // Label 3637: @120265 |
| 43319 | /* 120265 */ GIM_Reject, |
| 43320 | /* 120266 */ // Label 3627: @120266 |
| 43321 | /* 120266 */ GIM_Try, /*On fail goto*//*Label 3638*/ GIMT_Encode4(120441), |
| 43322 | /* 120271 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43323 | /* 120274 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43324 | /* 120277 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3639*/ GIMT_Encode4(120354), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4577 // |
| 43325 | /* 120284 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43326 | /* 120288 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43327 | /* 120292 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43328 | /* 120296 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43329 | /* 120300 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43330 | /* 120305 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 43331 | /* 120309 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43332 | /* 120313 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43333 | /* 120317 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43334 | /* 120322 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43335 | /* 120324 */ // (fmaxnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 43336 | /* 120324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32), |
| 43337 | /* 120327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43338 | /* 120329 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 43339 | /* 120333 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 43340 | /* 120337 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43341 | /* 120340 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43342 | /* 120346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43343 | /* 120352 */ GIR_RootConstrainSelectedInstOperands, |
| 43344 | /* 120353 */ // GIR_Coverage, 4577, |
| 43345 | /* 120353 */ GIR_EraseRootFromParent_Done, |
| 43346 | /* 120354 */ // Label 3639: @120354 |
| 43347 | /* 120354 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3640*/ GIMT_Encode4(120380), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1376 // |
| 43348 | /* 120361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43349 | /* 120365 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43350 | /* 120369 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43351 | /* 120373 */ // (fmaxnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMAXNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 43352 | /* 120373 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQf), |
| 43353 | /* 120378 */ GIR_RootConstrainSelectedInstOperands, |
| 43354 | /* 120379 */ // GIR_Coverage, 1376, |
| 43355 | /* 120379 */ GIR_Done, |
| 43356 | /* 120380 */ // Label 3640: @120380 |
| 43357 | /* 120380 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3641*/ GIMT_Encode4(120440), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3419 // |
| 43358 | /* 120387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43359 | /* 120391 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43360 | /* 120395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43361 | /* 120399 */ // (fmaxnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 43362 | /* 120399 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43363 | /* 120402 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43364 | /* 120406 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43365 | /* 120411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32), |
| 43366 | /* 120414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43367 | /* 120416 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43368 | /* 120418 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43369 | /* 120420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43370 | /* 120423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43371 | /* 120429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43372 | /* 120435 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43373 | /* 120438 */ GIR_RootConstrainSelectedInstOperands, |
| 43374 | /* 120439 */ // GIR_Coverage, 3419, |
| 43375 | /* 120439 */ GIR_EraseRootFromParent_Done, |
| 43376 | /* 120440 */ // Label 3641: @120440 |
| 43377 | /* 120440 */ GIM_Reject, |
| 43378 | /* 120441 */ // Label 3638: @120441 |
| 43379 | /* 120441 */ GIM_Reject, |
| 43380 | /* 120442 */ // Label 3628: @120442 |
| 43381 | /* 120442 */ GIM_Reject, |
| 43382 | /* 120443 */ // Label 57: @120443 |
| 43383 | /* 120443 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3648*/ GIMT_Encode4(121170), |
| 43384 | /* 120454 */ /*GILLT_s16*//*Label 3642*/ GIMT_Encode4(120506), |
| 43385 | /* 120458 */ /*GILLT_s32*//*Label 3643*/ GIMT_Encode4(120746), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43386 | /* 120490 */ /*GILLT_v4s16*//*Label 3644*/ GIMT_Encode4(120986), |
| 43387 | /* 120494 */ /*GILLT_v8s16*//*Label 3645*/ GIMT_Encode4(121032), |
| 43388 | /* 120498 */ /*GILLT_v2s32*//*Label 3646*/ GIMT_Encode4(121078), |
| 43389 | /* 120502 */ /*GILLT_v4s32*//*Label 3647*/ GIMT_Encode4(121124), |
| 43390 | /* 120506 */ // Label 3642: @120506 |
| 43391 | /* 120506 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3649*/ GIMT_Encode4(120745), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 3096 // |
| 43392 | /* 120513 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 43393 | /* 120516 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 43394 | /* 120519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43395 | /* 120523 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43396 | /* 120527 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43397 | /* 120531 */ // (fminimum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMINhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 43398 | /* 120531 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16, |
| 43399 | /* 120534 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43400 | /* 120538 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43401 | /* 120543 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 43402 | /* 120545 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16, |
| 43403 | /* 120548 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43404 | /* 120552 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43405 | /* 120557 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 43406 | /* 120560 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43407 | /* 120565 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16, |
| 43408 | /* 120568 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43409 | /* 120572 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43410 | /* 120577 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 43411 | /* 120580 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 43412 | /* 120584 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 43413 | /* 120587 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43414 | /* 120592 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43415 | /* 120597 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 43416 | /* 120602 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16, |
| 43417 | /* 120605 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43418 | /* 120609 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43419 | /* 120614 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 43420 | /* 120616 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16, |
| 43421 | /* 120619 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43422 | /* 120623 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43423 | /* 120628 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 43424 | /* 120631 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43425 | /* 120636 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16, |
| 43426 | /* 120639 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43427 | /* 120643 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43428 | /* 120648 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 43429 | /* 120651 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 43430 | /* 120655 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 43431 | /* 120658 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43432 | /* 120663 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43433 | /* 120668 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 43434 | /* 120673 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 43435 | /* 120676 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINhd), |
| 43436 | /* 120680 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43437 | /* 120685 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 43438 | /* 120688 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 43439 | /* 120691 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 43440 | /* 120694 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43441 | /* 120700 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 43442 | /* 120702 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16, |
| 43443 | /* 120705 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43444 | /* 120709 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43445 | /* 120714 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 43446 | /* 120717 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43447 | /* 120722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43448 | /* 120725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 43449 | /* 120727 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 43450 | /* 120734 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 43451 | /* 120739 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43452 | /* 120744 */ // GIR_Coverage, 3096, |
| 43453 | /* 120744 */ GIR_EraseRootFromParent_Done, |
| 43454 | /* 120745 */ // Label 3649: @120745 |
| 43455 | /* 120745 */ GIM_Reject, |
| 43456 | /* 120746 */ // Label 3643: @120746 |
| 43457 | /* 120746 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3650*/ GIMT_Encode4(120985), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3098 // |
| 43458 | /* 120753 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 43459 | /* 120756 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43460 | /* 120759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43461 | /* 120763 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43462 | /* 120767 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43463 | /* 120771 */ // (fminimum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMINfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 43464 | /* 120771 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 43465 | /* 120774 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43466 | /* 120778 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43467 | /* 120783 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 43468 | /* 120785 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 43469 | /* 120788 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43470 | /* 120792 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43471 | /* 120797 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 43472 | /* 120800 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43473 | /* 120805 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 43474 | /* 120808 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43475 | /* 120812 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43476 | /* 120817 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 43477 | /* 120820 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 43478 | /* 120824 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 43479 | /* 120827 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43480 | /* 120832 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43481 | /* 120837 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 43482 | /* 120842 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 43483 | /* 120845 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43484 | /* 120849 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43485 | /* 120854 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 43486 | /* 120856 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 43487 | /* 120859 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43488 | /* 120863 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43489 | /* 120868 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 43490 | /* 120871 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43491 | /* 120876 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 43492 | /* 120879 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43493 | /* 120883 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43494 | /* 120888 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 43495 | /* 120891 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 43496 | /* 120895 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 43497 | /* 120898 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43498 | /* 120903 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43499 | /* 120908 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 43500 | /* 120913 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 43501 | /* 120916 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINfd), |
| 43502 | /* 120920 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43503 | /* 120925 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 43504 | /* 120928 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 43505 | /* 120931 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 43506 | /* 120934 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43507 | /* 120940 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 43508 | /* 120942 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 43509 | /* 120945 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43510 | /* 120949 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43511 | /* 120954 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 43512 | /* 120957 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43513 | /* 120962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43514 | /* 120965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 43515 | /* 120967 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 43516 | /* 120974 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 43517 | /* 120979 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43518 | /* 120984 */ // GIR_Coverage, 3098, |
| 43519 | /* 120984 */ GIR_EraseRootFromParent_Done, |
| 43520 | /* 120985 */ // Label 3650: @120985 |
| 43521 | /* 120985 */ GIM_Reject, |
| 43522 | /* 120986 */ // Label 3644: @120986 |
| 43523 | /* 120986 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3651*/ GIMT_Encode4(121031), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1393 // |
| 43524 | /* 120993 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43525 | /* 120996 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43526 | /* 120999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43527 | /* 121003 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43528 | /* 121007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43529 | /* 121011 */ // (fminimum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMINhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 43530 | /* 121011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhd), |
| 43531 | /* 121014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43532 | /* 121016 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43533 | /* 121018 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43534 | /* 121020 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43535 | /* 121023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43536 | /* 121029 */ GIR_RootConstrainSelectedInstOperands, |
| 43537 | /* 121030 */ // GIR_Coverage, 1393, |
| 43538 | /* 121030 */ GIR_EraseRootFromParent_Done, |
| 43539 | /* 121031 */ // Label 3651: @121031 |
| 43540 | /* 121031 */ GIM_Reject, |
| 43541 | /* 121032 */ // Label 3645: @121032 |
| 43542 | /* 121032 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3652*/ GIMT_Encode4(121077), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1394 // |
| 43543 | /* 121039 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43544 | /* 121042 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43545 | /* 121045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43546 | /* 121049 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43547 | /* 121053 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43548 | /* 121057 */ // (fminimum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMINhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 43549 | /* 121057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhq), |
| 43550 | /* 121060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43551 | /* 121062 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43552 | /* 121064 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43553 | /* 121066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43554 | /* 121069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43555 | /* 121075 */ GIR_RootConstrainSelectedInstOperands, |
| 43556 | /* 121076 */ // GIR_Coverage, 1394, |
| 43557 | /* 121076 */ GIR_EraseRootFromParent_Done, |
| 43558 | /* 121077 */ // Label 3652: @121077 |
| 43559 | /* 121077 */ GIM_Reject, |
| 43560 | /* 121078 */ // Label 3646: @121078 |
| 43561 | /* 121078 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3653*/ GIMT_Encode4(121123), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1391 // |
| 43562 | /* 121085 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43563 | /* 121088 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43564 | /* 121091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43565 | /* 121095 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43566 | /* 121099 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43567 | /* 121103 */ // (fminimum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMINfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 43568 | /* 121103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfd), |
| 43569 | /* 121106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43570 | /* 121108 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43571 | /* 121110 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43572 | /* 121112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43573 | /* 121115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43574 | /* 121121 */ GIR_RootConstrainSelectedInstOperands, |
| 43575 | /* 121122 */ // GIR_Coverage, 1391, |
| 43576 | /* 121122 */ GIR_EraseRootFromParent_Done, |
| 43577 | /* 121123 */ // Label 3653: @121123 |
| 43578 | /* 121123 */ GIM_Reject, |
| 43579 | /* 121124 */ // Label 3647: @121124 |
| 43580 | /* 121124 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3654*/ GIMT_Encode4(121169), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1392 // |
| 43581 | /* 121131 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43582 | /* 121134 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43583 | /* 121137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43584 | /* 121141 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43585 | /* 121145 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43586 | /* 121149 */ // (fminimum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMINfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 43587 | /* 121149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfq), |
| 43588 | /* 121152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43589 | /* 121154 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43590 | /* 121156 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43591 | /* 121158 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43592 | /* 121161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43593 | /* 121167 */ GIR_RootConstrainSelectedInstOperands, |
| 43594 | /* 121168 */ // GIR_Coverage, 1392, |
| 43595 | /* 121168 */ GIR_EraseRootFromParent_Done, |
| 43596 | /* 121169 */ // Label 3654: @121169 |
| 43597 | /* 121169 */ GIM_Reject, |
| 43598 | /* 121170 */ // Label 3648: @121170 |
| 43599 | /* 121170 */ GIM_Reject, |
| 43600 | /* 121171 */ // Label 58: @121171 |
| 43601 | /* 121171 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3661*/ GIMT_Encode4(121898), |
| 43602 | /* 121182 */ /*GILLT_s16*//*Label 3655*/ GIMT_Encode4(121234), |
| 43603 | /* 121186 */ /*GILLT_s32*//*Label 3656*/ GIMT_Encode4(121474), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43604 | /* 121218 */ /*GILLT_v4s16*//*Label 3657*/ GIMT_Encode4(121714), |
| 43605 | /* 121222 */ /*GILLT_v8s16*//*Label 3658*/ GIMT_Encode4(121760), |
| 43606 | /* 121226 */ /*GILLT_v2s32*//*Label 3659*/ GIMT_Encode4(121806), |
| 43607 | /* 121230 */ /*GILLT_v4s32*//*Label 3660*/ GIMT_Encode4(121852), |
| 43608 | /* 121234 */ // Label 3655: @121234 |
| 43609 | /* 121234 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3662*/ GIMT_Encode4(121473), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 3095 // |
| 43610 | /* 121241 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 43611 | /* 121244 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 43612 | /* 121247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43613 | /* 121251 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43614 | /* 121255 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43615 | /* 121259 */ // (fmaximum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMAXhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 43616 | /* 121259 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16, |
| 43617 | /* 121262 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43618 | /* 121266 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43619 | /* 121271 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 43620 | /* 121273 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16, |
| 43621 | /* 121276 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43622 | /* 121280 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43623 | /* 121285 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 43624 | /* 121288 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43625 | /* 121293 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16, |
| 43626 | /* 121296 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43627 | /* 121300 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43628 | /* 121305 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 43629 | /* 121308 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 43630 | /* 121312 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 43631 | /* 121315 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43632 | /* 121320 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43633 | /* 121325 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 43634 | /* 121330 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16, |
| 43635 | /* 121333 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43636 | /* 121337 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43637 | /* 121342 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 43638 | /* 121344 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16, |
| 43639 | /* 121347 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43640 | /* 121351 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43641 | /* 121356 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 43642 | /* 121359 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43643 | /* 121364 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16, |
| 43644 | /* 121367 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43645 | /* 121371 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43646 | /* 121376 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 43647 | /* 121379 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 43648 | /* 121383 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 43649 | /* 121386 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43650 | /* 121391 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43651 | /* 121396 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 43652 | /* 121401 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 43653 | /* 121404 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXhd), |
| 43654 | /* 121408 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43655 | /* 121413 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 43656 | /* 121416 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 43657 | /* 121419 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 43658 | /* 121422 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43659 | /* 121428 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 43660 | /* 121430 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16, |
| 43661 | /* 121433 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43662 | /* 121437 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43663 | /* 121442 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 43664 | /* 121445 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43665 | /* 121450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43666 | /* 121453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 43667 | /* 121455 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 43668 | /* 121462 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 43669 | /* 121467 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43670 | /* 121472 */ // GIR_Coverage, 3095, |
| 43671 | /* 121472 */ GIR_EraseRootFromParent_Done, |
| 43672 | /* 121473 */ // Label 3662: @121473 |
| 43673 | /* 121473 */ GIM_Reject, |
| 43674 | /* 121474 */ // Label 3656: @121474 |
| 43675 | /* 121474 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3663*/ GIMT_Encode4(121713), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3097 // |
| 43676 | /* 121481 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 43677 | /* 121484 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43678 | /* 121487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43679 | /* 121491 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43680 | /* 121495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43681 | /* 121499 */ // (fmaximum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMAXfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 43682 | /* 121499 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 43683 | /* 121502 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43684 | /* 121506 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43685 | /* 121511 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 43686 | /* 121513 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 43687 | /* 121516 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43688 | /* 121520 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43689 | /* 121525 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 43690 | /* 121528 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43691 | /* 121533 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 43692 | /* 121536 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43693 | /* 121540 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43694 | /* 121545 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 43695 | /* 121548 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 43696 | /* 121552 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 43697 | /* 121555 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43698 | /* 121560 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43699 | /* 121565 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 43700 | /* 121570 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 43701 | /* 121573 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43702 | /* 121577 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43703 | /* 121582 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 43704 | /* 121584 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 43705 | /* 121587 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43706 | /* 121591 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43707 | /* 121596 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 43708 | /* 121599 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43709 | /* 121604 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 43710 | /* 121607 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43711 | /* 121611 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43712 | /* 121616 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 43713 | /* 121619 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 43714 | /* 121623 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 43715 | /* 121626 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43716 | /* 121631 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43717 | /* 121636 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 43718 | /* 121641 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 43719 | /* 121644 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXfd), |
| 43720 | /* 121648 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43721 | /* 121653 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 43722 | /* 121656 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 43723 | /* 121659 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 43724 | /* 121662 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43725 | /* 121668 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 43726 | /* 121670 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 43727 | /* 121673 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43728 | /* 121677 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43729 | /* 121682 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 43730 | /* 121685 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43731 | /* 121690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43732 | /* 121693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 43733 | /* 121695 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 43734 | /* 121702 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 43735 | /* 121707 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43736 | /* 121712 */ // GIR_Coverage, 3097, |
| 43737 | /* 121712 */ GIR_EraseRootFromParent_Done, |
| 43738 | /* 121713 */ // Label 3663: @121713 |
| 43739 | /* 121713 */ GIM_Reject, |
| 43740 | /* 121714 */ // Label 3657: @121714 |
| 43741 | /* 121714 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3664*/ GIMT_Encode4(121759), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1373 // |
| 43742 | /* 121721 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43743 | /* 121724 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43744 | /* 121727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43745 | /* 121731 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43746 | /* 121735 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43747 | /* 121739 */ // (fmaximum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMAXhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 43748 | /* 121739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhd), |
| 43749 | /* 121742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43750 | /* 121744 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43751 | /* 121746 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43752 | /* 121748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43753 | /* 121751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43754 | /* 121757 */ GIR_RootConstrainSelectedInstOperands, |
| 43755 | /* 121758 */ // GIR_Coverage, 1373, |
| 43756 | /* 121758 */ GIR_EraseRootFromParent_Done, |
| 43757 | /* 121759 */ // Label 3664: @121759 |
| 43758 | /* 121759 */ GIM_Reject, |
| 43759 | /* 121760 */ // Label 3658: @121760 |
| 43760 | /* 121760 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3665*/ GIMT_Encode4(121805), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1374 // |
| 43761 | /* 121767 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43762 | /* 121770 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43763 | /* 121773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43764 | /* 121777 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43765 | /* 121781 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43766 | /* 121785 */ // (fmaximum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMAXhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 43767 | /* 121785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhq), |
| 43768 | /* 121788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43769 | /* 121790 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43770 | /* 121792 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43771 | /* 121794 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43772 | /* 121797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43773 | /* 121803 */ GIR_RootConstrainSelectedInstOperands, |
| 43774 | /* 121804 */ // GIR_Coverage, 1374, |
| 43775 | /* 121804 */ GIR_EraseRootFromParent_Done, |
| 43776 | /* 121805 */ // Label 3665: @121805 |
| 43777 | /* 121805 */ GIM_Reject, |
| 43778 | /* 121806 */ // Label 3659: @121806 |
| 43779 | /* 121806 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3666*/ GIMT_Encode4(121851), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1371 // |
| 43780 | /* 121813 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43781 | /* 121816 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43782 | /* 121819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43783 | /* 121823 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43784 | /* 121827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43785 | /* 121831 */ // (fmaximum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMAXfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 43786 | /* 121831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfd), |
| 43787 | /* 121834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43788 | /* 121836 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43789 | /* 121838 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43790 | /* 121840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43791 | /* 121843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43792 | /* 121849 */ GIR_RootConstrainSelectedInstOperands, |
| 43793 | /* 121850 */ // GIR_Coverage, 1371, |
| 43794 | /* 121850 */ GIR_EraseRootFromParent_Done, |
| 43795 | /* 121851 */ // Label 3666: @121851 |
| 43796 | /* 121851 */ GIM_Reject, |
| 43797 | /* 121852 */ // Label 3660: @121852 |
| 43798 | /* 121852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3667*/ GIMT_Encode4(121897), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1372 // |
| 43799 | /* 121859 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43800 | /* 121862 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43801 | /* 121865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43802 | /* 121869 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43803 | /* 121873 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43804 | /* 121877 */ // (fmaximum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMAXfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 43805 | /* 121877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfq), |
| 43806 | /* 121880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43807 | /* 121882 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43808 | /* 121884 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43809 | /* 121886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43810 | /* 121889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43811 | /* 121895 */ GIR_RootConstrainSelectedInstOperands, |
| 43812 | /* 121896 */ // GIR_Coverage, 1372, |
| 43813 | /* 121896 */ GIR_EraseRootFromParent_Done, |
| 43814 | /* 121897 */ // Label 3667: @121897 |
| 43815 | /* 121897 */ GIM_Reject, |
| 43816 | /* 121898 */ // Label 3661: @121898 |
| 43817 | /* 121898 */ GIM_Reject, |
| 43818 | /* 121899 */ // Label 59: @121899 |
| 43819 | /* 121899 */ GIM_Try, /*On fail goto*//*Label 3668*/ GIMT_Encode4(121931), // Rule ID 2800 // |
| 43820 | /* 121904 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43821 | /* 121907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 43822 | /* 121911 */ // (get_fpenv:{ *:[i32] }) => (VMRS:{ *:[i32] }) |
| 43823 | /* 121911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS), |
| 43824 | /* 121914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 43825 | /* 121916 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43826 | /* 121919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43827 | /* 121925 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43828 | /* 121929 */ GIR_RootConstrainSelectedInstOperands, |
| 43829 | /* 121930 */ // GIR_Coverage, 2800, |
| 43830 | /* 121930 */ GIR_EraseRootFromParent_Done, |
| 43831 | /* 121931 */ // Label 3668: @121931 |
| 43832 | /* 121931 */ GIM_Reject, |
| 43833 | /* 121932 */ // Label 60: @121932 |
| 43834 | /* 121932 */ GIM_Try, /*On fail goto*//*Label 3669*/ GIMT_Encode4(121967), // Rule ID 2801 // |
| 43835 | /* 121937 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43836 | /* 121940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 43837 | /* 121944 */ // (set_fpenv GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt) |
| 43838 | /* 121944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 43839 | /* 121947 */ GIR_RootToRootCopy, /*OpIdx*/0, // Rt |
| 43840 | /* 121949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43841 | /* 121952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43842 | /* 121958 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 43843 | /* 121961 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43844 | /* 121965 */ GIR_RootConstrainSelectedInstOperands, |
| 43845 | /* 121966 */ // GIR_Coverage, 2801, |
| 43846 | /* 121966 */ GIR_EraseRootFromParent_Done, |
| 43847 | /* 121967 */ // Label 3669: @121967 |
| 43848 | /* 121967 */ GIM_Reject, |
| 43849 | /* 121968 */ // Label 61: @121968 |
| 43850 | /* 121968 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3670*/ GIMT_Encode4(122031), GIMT_Encode2(GIFBS_IsARM), // Rule ID 2802 // |
| 43851 | /* 121975 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (MOVi:{ *:[i32] } 0:{ *:[i32] })) |
| 43852 | /* 121975 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 43853 | /* 121978 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MOVi), |
| 43854 | /* 121982 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43855 | /* 121987 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 43856 | /* 121990 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 43857 | /* 121993 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43858 | /* 121999 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43859 | /* 122005 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 43860 | /* 122007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 43861 | /* 122010 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43862 | /* 122013 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43863 | /* 122016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43864 | /* 122022 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 43865 | /* 122025 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43866 | /* 122029 */ GIR_RootConstrainSelectedInstOperands, |
| 43867 | /* 122030 */ // GIR_Coverage, 2802, |
| 43868 | /* 122030 */ GIR_EraseRootFromParent_Done, |
| 43869 | /* 122031 */ // Label 3670: @122031 |
| 43870 | /* 122031 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3671*/ GIMT_Encode4(122094), GIMT_Encode2(GIFBS_IsThumb), // Rule ID 2803 // |
| 43871 | /* 122038 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (tMOVi8:{ *:[i32] } 0:{ *:[i32] })) |
| 43872 | /* 122038 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 43873 | /* 122041 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 43874 | /* 122045 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43875 | /* 122050 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 43876 | /* 122056 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 43877 | /* 122059 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 43878 | /* 122062 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43879 | /* 122068 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 43880 | /* 122070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 43881 | /* 122073 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43882 | /* 122076 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43883 | /* 122079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43884 | /* 122085 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 43885 | /* 122088 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43886 | /* 122092 */ GIR_RootConstrainSelectedInstOperands, |
| 43887 | /* 122093 */ // GIR_Coverage, 2803, |
| 43888 | /* 122093 */ GIR_EraseRootFromParent_Done, |
| 43889 | /* 122094 */ // Label 3671: @122094 |
| 43890 | /* 122094 */ GIM_Reject, |
| 43891 | /* 122095 */ // Label 62: @122095 |
| 43892 | /* 122095 */ GIM_Try, /*On fail goto*//*Label 3672*/ GIMT_Encode4(122127), // Rule ID 2804 // |
| 43893 | /* 122100 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43894 | /* 122103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 43895 | /* 122107 */ // (get_fpmode:{ *:[i32] }) => (VMRS:{ *:[i32] }) |
| 43896 | /* 122107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS), |
| 43897 | /* 122110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 43898 | /* 122112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43899 | /* 122115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43900 | /* 122121 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43901 | /* 122125 */ GIR_RootConstrainSelectedInstOperands, |
| 43902 | /* 122126 */ // GIR_Coverage, 2804, |
| 43903 | /* 122126 */ GIR_EraseRootFromParent_Done, |
| 43904 | /* 122127 */ // Label 3672: @122127 |
| 43905 | /* 122127 */ GIM_Reject, |
| 43906 | /* 122128 */ // Label 63: @122128 |
| 43907 | /* 122128 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3679*/ GIMT_Encode4(122637), |
| 43908 | /* 122139 */ /*GILLT_v8s8*//*Label 3673*/ GIMT_Encode4(122163), |
| 43909 | /* 122143 */ /*GILLT_v16s8*//*Label 3674*/ GIMT_Encode4(122209), |
| 43910 | /* 122147 */ /*GILLT_v4s16*//*Label 3675*/ GIMT_Encode4(122321), |
| 43911 | /* 122151 */ /*GILLT_v8s16*//*Label 3676*/ GIMT_Encode4(122367), |
| 43912 | /* 122155 */ /*GILLT_v2s32*//*Label 3677*/ GIMT_Encode4(122479), |
| 43913 | /* 122159 */ /*GILLT_v4s32*//*Label 3678*/ GIMT_Encode4(122525), |
| 43914 | /* 122163 */ // Label 3673: @122163 |
| 43915 | /* 122163 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3680*/ GIMT_Encode4(122208), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1383 // |
| 43916 | /* 122170 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 43917 | /* 122173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 43918 | /* 122176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43919 | /* 122180 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43920 | /* 122184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43921 | /* 122188 */ // (smin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 43922 | /* 122188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i8), |
| 43923 | /* 122191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43924 | /* 122193 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43925 | /* 122195 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43926 | /* 122197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43927 | /* 122200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43928 | /* 122206 */ GIR_RootConstrainSelectedInstOperands, |
| 43929 | /* 122207 */ // GIR_Coverage, 1383, |
| 43930 | /* 122207 */ GIR_EraseRootFromParent_Done, |
| 43931 | /* 122208 */ // Label 3680: @122208 |
| 43932 | /* 122208 */ GIM_Reject, |
| 43933 | /* 122209 */ // Label 3674: @122209 |
| 43934 | /* 122209 */ GIM_Try, /*On fail goto*//*Label 3681*/ GIMT_Encode4(122320), |
| 43935 | /* 122214 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 43936 | /* 122217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 43937 | /* 122220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3682*/ GIMT_Encode4(122259), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1384 // |
| 43938 | /* 122227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43939 | /* 122231 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43940 | /* 122235 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43941 | /* 122239 */ // (smin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 43942 | /* 122239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv16i8), |
| 43943 | /* 122242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43944 | /* 122244 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43945 | /* 122246 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43946 | /* 122248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43947 | /* 122251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43948 | /* 122257 */ GIR_RootConstrainSelectedInstOperands, |
| 43949 | /* 122258 */ // GIR_Coverage, 1384, |
| 43950 | /* 122258 */ GIR_EraseRootFromParent_Done, |
| 43951 | /* 122259 */ // Label 3682: @122259 |
| 43952 | /* 122259 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3683*/ GIMT_Encode4(122319), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3691 // |
| 43953 | /* 122266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43954 | /* 122270 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43955 | /* 122274 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43956 | /* 122278 */ // (smin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 43957 | /* 122278 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43958 | /* 122281 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43959 | /* 122285 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43960 | /* 122290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs8), |
| 43961 | /* 122293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43962 | /* 122295 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43963 | /* 122297 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43964 | /* 122299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43965 | /* 122302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43966 | /* 122308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43967 | /* 122314 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43968 | /* 122317 */ GIR_RootConstrainSelectedInstOperands, |
| 43969 | /* 122318 */ // GIR_Coverage, 3691, |
| 43970 | /* 122318 */ GIR_EraseRootFromParent_Done, |
| 43971 | /* 122319 */ // Label 3683: @122319 |
| 43972 | /* 122319 */ GIM_Reject, |
| 43973 | /* 122320 */ // Label 3681: @122320 |
| 43974 | /* 122320 */ GIM_Reject, |
| 43975 | /* 122321 */ // Label 3675: @122321 |
| 43976 | /* 122321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3684*/ GIMT_Encode4(122366), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1379 // |
| 43977 | /* 122328 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43978 | /* 122331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43979 | /* 122334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43980 | /* 122338 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43981 | /* 122342 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43982 | /* 122346 */ // (smin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 43983 | /* 122346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i16), |
| 43984 | /* 122349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43985 | /* 122351 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43986 | /* 122353 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43987 | /* 122355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43988 | /* 122358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43989 | /* 122364 */ GIR_RootConstrainSelectedInstOperands, |
| 43990 | /* 122365 */ // GIR_Coverage, 1379, |
| 43991 | /* 122365 */ GIR_EraseRootFromParent_Done, |
| 43992 | /* 122366 */ // Label 3684: @122366 |
| 43993 | /* 122366 */ GIM_Reject, |
| 43994 | /* 122367 */ // Label 3676: @122367 |
| 43995 | /* 122367 */ GIM_Try, /*On fail goto*//*Label 3685*/ GIMT_Encode4(122478), |
| 43996 | /* 122372 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43997 | /* 122375 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43998 | /* 122378 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3686*/ GIMT_Encode4(122417), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1381 // |
| 43999 | /* 122385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44000 | /* 122389 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44001 | /* 122393 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44002 | /* 122397 */ // (smin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 44003 | /* 122397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i16), |
| 44004 | /* 122400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44005 | /* 122402 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44006 | /* 122404 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44007 | /* 122406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44008 | /* 122409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44009 | /* 122415 */ GIR_RootConstrainSelectedInstOperands, |
| 44010 | /* 122416 */ // GIR_Coverage, 1381, |
| 44011 | /* 122416 */ GIR_EraseRootFromParent_Done, |
| 44012 | /* 122417 */ // Label 3686: @122417 |
| 44013 | /* 122417 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3687*/ GIMT_Encode4(122477), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3694 // |
| 44014 | /* 122424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44015 | /* 122428 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44016 | /* 122432 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44017 | /* 122436 */ // (smin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 44018 | /* 122436 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44019 | /* 122439 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44020 | /* 122443 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44021 | /* 122448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs16), |
| 44022 | /* 122451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44023 | /* 122453 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44024 | /* 122455 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44025 | /* 122457 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44026 | /* 122460 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44027 | /* 122466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44028 | /* 122472 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44029 | /* 122475 */ GIR_RootConstrainSelectedInstOperands, |
| 44030 | /* 122476 */ // GIR_Coverage, 3694, |
| 44031 | /* 122476 */ GIR_EraseRootFromParent_Done, |
| 44032 | /* 122477 */ // Label 3687: @122477 |
| 44033 | /* 122477 */ GIM_Reject, |
| 44034 | /* 122478 */ // Label 3685: @122478 |
| 44035 | /* 122478 */ GIM_Reject, |
| 44036 | /* 122479 */ // Label 3677: @122479 |
| 44037 | /* 122479 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3688*/ GIMT_Encode4(122524), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1380 // |
| 44038 | /* 122486 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 44039 | /* 122489 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44040 | /* 122492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44041 | /* 122496 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44042 | /* 122500 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44043 | /* 122504 */ // (smin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 44044 | /* 122504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv2i32), |
| 44045 | /* 122507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44046 | /* 122509 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44047 | /* 122511 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44048 | /* 122513 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44049 | /* 122516 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44050 | /* 122522 */ GIR_RootConstrainSelectedInstOperands, |
| 44051 | /* 122523 */ // GIR_Coverage, 1380, |
| 44052 | /* 122523 */ GIR_EraseRootFromParent_Done, |
| 44053 | /* 122524 */ // Label 3688: @122524 |
| 44054 | /* 122524 */ GIM_Reject, |
| 44055 | /* 122525 */ // Label 3678: @122525 |
| 44056 | /* 122525 */ GIM_Try, /*On fail goto*//*Label 3689*/ GIMT_Encode4(122636), |
| 44057 | /* 122530 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44058 | /* 122533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44059 | /* 122536 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3690*/ GIMT_Encode4(122575), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1382 // |
| 44060 | /* 122543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44061 | /* 122547 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44062 | /* 122551 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44063 | /* 122555 */ // (smin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 44064 | /* 122555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i32), |
| 44065 | /* 122558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44066 | /* 122560 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44067 | /* 122562 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44068 | /* 122564 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44069 | /* 122567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44070 | /* 122573 */ GIR_RootConstrainSelectedInstOperands, |
| 44071 | /* 122574 */ // GIR_Coverage, 1382, |
| 44072 | /* 122574 */ GIR_EraseRootFromParent_Done, |
| 44073 | /* 122575 */ // Label 3690: @122575 |
| 44074 | /* 122575 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3691*/ GIMT_Encode4(122635), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3697 // |
| 44075 | /* 122582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44076 | /* 122586 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44077 | /* 122590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44078 | /* 122594 */ // (smin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 44079 | /* 122594 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44080 | /* 122597 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44081 | /* 122601 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44082 | /* 122606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs32), |
| 44083 | /* 122609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44084 | /* 122611 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44085 | /* 122613 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44086 | /* 122615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44087 | /* 122618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44088 | /* 122624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44089 | /* 122630 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44090 | /* 122633 */ GIR_RootConstrainSelectedInstOperands, |
| 44091 | /* 122634 */ // GIR_Coverage, 3697, |
| 44092 | /* 122634 */ GIR_EraseRootFromParent_Done, |
| 44093 | /* 122635 */ // Label 3691: @122635 |
| 44094 | /* 122635 */ GIM_Reject, |
| 44095 | /* 122636 */ // Label 3689: @122636 |
| 44096 | /* 122636 */ GIM_Reject, |
| 44097 | /* 122637 */ // Label 3679: @122637 |
| 44098 | /* 122637 */ GIM_Reject, |
| 44099 | /* 122638 */ // Label 64: @122638 |
| 44100 | /* 122638 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3698*/ GIMT_Encode4(123147), |
| 44101 | /* 122649 */ /*GILLT_v8s8*//*Label 3692*/ GIMT_Encode4(122673), |
| 44102 | /* 122653 */ /*GILLT_v16s8*//*Label 3693*/ GIMT_Encode4(122719), |
| 44103 | /* 122657 */ /*GILLT_v4s16*//*Label 3694*/ GIMT_Encode4(122831), |
| 44104 | /* 122661 */ /*GILLT_v8s16*//*Label 3695*/ GIMT_Encode4(122877), |
| 44105 | /* 122665 */ /*GILLT_v2s32*//*Label 3696*/ GIMT_Encode4(122989), |
| 44106 | /* 122669 */ /*GILLT_v4s32*//*Label 3697*/ GIMT_Encode4(123035), |
| 44107 | /* 122673 */ // Label 3692: @122673 |
| 44108 | /* 122673 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3699*/ GIMT_Encode4(122718), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1363 // |
| 44109 | /* 122680 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44110 | /* 122683 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 44111 | /* 122686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44112 | /* 122690 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44113 | /* 122694 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44114 | /* 122698 */ // (smax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 44115 | /* 122698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i8), |
| 44116 | /* 122701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44117 | /* 122703 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44118 | /* 122705 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44119 | /* 122707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44120 | /* 122710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44121 | /* 122716 */ GIR_RootConstrainSelectedInstOperands, |
| 44122 | /* 122717 */ // GIR_Coverage, 1363, |
| 44123 | /* 122717 */ GIR_EraseRootFromParent_Done, |
| 44124 | /* 122718 */ // Label 3699: @122718 |
| 44125 | /* 122718 */ GIM_Reject, |
| 44126 | /* 122719 */ // Label 3693: @122719 |
| 44127 | /* 122719 */ GIM_Try, /*On fail goto*//*Label 3700*/ GIMT_Encode4(122830), |
| 44128 | /* 122724 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44129 | /* 122727 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 44130 | /* 122730 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3701*/ GIMT_Encode4(122769), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1364 // |
| 44131 | /* 122737 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44132 | /* 122741 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44133 | /* 122745 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44134 | /* 122749 */ // (smax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 44135 | /* 122749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv16i8), |
| 44136 | /* 122752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44137 | /* 122754 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44138 | /* 122756 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44139 | /* 122758 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44140 | /* 122761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44141 | /* 122767 */ GIR_RootConstrainSelectedInstOperands, |
| 44142 | /* 122768 */ // GIR_Coverage, 1364, |
| 44143 | /* 122768 */ GIR_EraseRootFromParent_Done, |
| 44144 | /* 122769 */ // Label 3701: @122769 |
| 44145 | /* 122769 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3702*/ GIMT_Encode4(122829), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3709 // |
| 44146 | /* 122776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44147 | /* 122780 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44148 | /* 122784 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44149 | /* 122788 */ // (smax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 44150 | /* 122788 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44151 | /* 122791 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44152 | /* 122795 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44153 | /* 122800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs8), |
| 44154 | /* 122803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44155 | /* 122805 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44156 | /* 122807 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44157 | /* 122809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44158 | /* 122812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44159 | /* 122818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44160 | /* 122824 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44161 | /* 122827 */ GIR_RootConstrainSelectedInstOperands, |
| 44162 | /* 122828 */ // GIR_Coverage, 3709, |
| 44163 | /* 122828 */ GIR_EraseRootFromParent_Done, |
| 44164 | /* 122829 */ // Label 3702: @122829 |
| 44165 | /* 122829 */ GIM_Reject, |
| 44166 | /* 122830 */ // Label 3700: @122830 |
| 44167 | /* 122830 */ GIM_Reject, |
| 44168 | /* 122831 */ // Label 3694: @122831 |
| 44169 | /* 122831 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3703*/ GIMT_Encode4(122876), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1359 // |
| 44170 | /* 122838 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44171 | /* 122841 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44172 | /* 122844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44173 | /* 122848 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44174 | /* 122852 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44175 | /* 122856 */ // (smax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 44176 | /* 122856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i16), |
| 44177 | /* 122859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44178 | /* 122861 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44179 | /* 122863 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44180 | /* 122865 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44181 | /* 122868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44182 | /* 122874 */ GIR_RootConstrainSelectedInstOperands, |
| 44183 | /* 122875 */ // GIR_Coverage, 1359, |
| 44184 | /* 122875 */ GIR_EraseRootFromParent_Done, |
| 44185 | /* 122876 */ // Label 3703: @122876 |
| 44186 | /* 122876 */ GIM_Reject, |
| 44187 | /* 122877 */ // Label 3695: @122877 |
| 44188 | /* 122877 */ GIM_Try, /*On fail goto*//*Label 3704*/ GIMT_Encode4(122988), |
| 44189 | /* 122882 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44190 | /* 122885 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44191 | /* 122888 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3705*/ GIMT_Encode4(122927), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1361 // |
| 44192 | /* 122895 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44193 | /* 122899 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44194 | /* 122903 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44195 | /* 122907 */ // (smax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 44196 | /* 122907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i16), |
| 44197 | /* 122910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44198 | /* 122912 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44199 | /* 122914 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44200 | /* 122916 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44201 | /* 122919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44202 | /* 122925 */ GIR_RootConstrainSelectedInstOperands, |
| 44203 | /* 122926 */ // GIR_Coverage, 1361, |
| 44204 | /* 122926 */ GIR_EraseRootFromParent_Done, |
| 44205 | /* 122927 */ // Label 3705: @122927 |
| 44206 | /* 122927 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3706*/ GIMT_Encode4(122987), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3712 // |
| 44207 | /* 122934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44208 | /* 122938 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44209 | /* 122942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44210 | /* 122946 */ // (smax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 44211 | /* 122946 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44212 | /* 122949 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44213 | /* 122953 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44214 | /* 122958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs16), |
| 44215 | /* 122961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44216 | /* 122963 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44217 | /* 122965 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44218 | /* 122967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44219 | /* 122970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44220 | /* 122976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44221 | /* 122982 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44222 | /* 122985 */ GIR_RootConstrainSelectedInstOperands, |
| 44223 | /* 122986 */ // GIR_Coverage, 3712, |
| 44224 | /* 122986 */ GIR_EraseRootFromParent_Done, |
| 44225 | /* 122987 */ // Label 3706: @122987 |
| 44226 | /* 122987 */ GIM_Reject, |
| 44227 | /* 122988 */ // Label 3704: @122988 |
| 44228 | /* 122988 */ GIM_Reject, |
| 44229 | /* 122989 */ // Label 3696: @122989 |
| 44230 | /* 122989 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3707*/ GIMT_Encode4(123034), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1360 // |
| 44231 | /* 122996 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 44232 | /* 122999 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44233 | /* 123002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44234 | /* 123006 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44235 | /* 123010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44236 | /* 123014 */ // (smax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 44237 | /* 123014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv2i32), |
| 44238 | /* 123017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44239 | /* 123019 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44240 | /* 123021 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44241 | /* 123023 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44242 | /* 123026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44243 | /* 123032 */ GIR_RootConstrainSelectedInstOperands, |
| 44244 | /* 123033 */ // GIR_Coverage, 1360, |
| 44245 | /* 123033 */ GIR_EraseRootFromParent_Done, |
| 44246 | /* 123034 */ // Label 3707: @123034 |
| 44247 | /* 123034 */ GIM_Reject, |
| 44248 | /* 123035 */ // Label 3697: @123035 |
| 44249 | /* 123035 */ GIM_Try, /*On fail goto*//*Label 3708*/ GIMT_Encode4(123146), |
| 44250 | /* 123040 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44251 | /* 123043 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44252 | /* 123046 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3709*/ GIMT_Encode4(123085), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1362 // |
| 44253 | /* 123053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44254 | /* 123057 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44255 | /* 123061 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44256 | /* 123065 */ // (smax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 44257 | /* 123065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i32), |
| 44258 | /* 123068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44259 | /* 123070 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44260 | /* 123072 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44261 | /* 123074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44262 | /* 123077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44263 | /* 123083 */ GIR_RootConstrainSelectedInstOperands, |
| 44264 | /* 123084 */ // GIR_Coverage, 1362, |
| 44265 | /* 123084 */ GIR_EraseRootFromParent_Done, |
| 44266 | /* 123085 */ // Label 3709: @123085 |
| 44267 | /* 123085 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3710*/ GIMT_Encode4(123145), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3715 // |
| 44268 | /* 123092 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44269 | /* 123096 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44270 | /* 123100 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44271 | /* 123104 */ // (smax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 44272 | /* 123104 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44273 | /* 123107 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44274 | /* 123111 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44275 | /* 123116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs32), |
| 44276 | /* 123119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44277 | /* 123121 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44278 | /* 123123 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44279 | /* 123125 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44280 | /* 123128 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44281 | /* 123134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44282 | /* 123140 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44283 | /* 123143 */ GIR_RootConstrainSelectedInstOperands, |
| 44284 | /* 123144 */ // GIR_Coverage, 3715, |
| 44285 | /* 123144 */ GIR_EraseRootFromParent_Done, |
| 44286 | /* 123145 */ // Label 3710: @123145 |
| 44287 | /* 123145 */ GIM_Reject, |
| 44288 | /* 123146 */ // Label 3708: @123146 |
| 44289 | /* 123146 */ GIM_Reject, |
| 44290 | /* 123147 */ // Label 3698: @123147 |
| 44291 | /* 123147 */ GIM_Reject, |
| 44292 | /* 123148 */ // Label 65: @123148 |
| 44293 | /* 123148 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3717*/ GIMT_Encode4(124035), |
| 44294 | /* 123159 */ /*GILLT_v8s8*//*Label 3711*/ GIMT_Encode4(123183), |
| 44295 | /* 123163 */ /*GILLT_v16s8*//*Label 3712*/ GIMT_Encode4(123229), |
| 44296 | /* 123167 */ /*GILLT_v4s16*//*Label 3713*/ GIMT_Encode4(123467), |
| 44297 | /* 123171 */ /*GILLT_v8s16*//*Label 3714*/ GIMT_Encode4(123513), |
| 44298 | /* 123175 */ /*GILLT_v2s32*//*Label 3715*/ GIMT_Encode4(123751), |
| 44299 | /* 123179 */ /*GILLT_v4s32*//*Label 3716*/ GIMT_Encode4(123797), |
| 44300 | /* 123183 */ // Label 3711: @123183 |
| 44301 | /* 123183 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3718*/ GIMT_Encode4(123228), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1389 // |
| 44302 | /* 123190 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44303 | /* 123193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 44304 | /* 123196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44305 | /* 123200 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44306 | /* 123204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44307 | /* 123208 */ // (umin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 44308 | /* 123208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i8), |
| 44309 | /* 123211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44310 | /* 123213 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44311 | /* 123215 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44312 | /* 123217 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44313 | /* 123220 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44314 | /* 123226 */ GIR_RootConstrainSelectedInstOperands, |
| 44315 | /* 123227 */ // GIR_Coverage, 1389, |
| 44316 | /* 123227 */ GIR_EraseRootFromParent_Done, |
| 44317 | /* 123228 */ // Label 3718: @123228 |
| 44318 | /* 123228 */ GIM_Reject, |
| 44319 | /* 123229 */ // Label 3712: @123229 |
| 44320 | /* 123229 */ GIM_Try, /*On fail goto*//*Label 3719*/ GIMT_Encode4(123466), |
| 44321 | /* 123234 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44322 | /* 123237 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 44323 | /* 123240 */ GIM_Try, /*On fail goto*//*Label 3720*/ GIMT_Encode4(123366), |
| 44324 | /* 123245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44325 | /* 123249 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3721*/ GIMT_Encode4(123307), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6661 // |
| 44326 | /* 123256 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44327 | /* 123260 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44328 | /* 123264 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44329 | /* 123268 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44330 | /* 123273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44331 | /* 123277 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44332 | /* 123279 */ // (umin:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 44333 | /* 123279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8), |
| 44334 | /* 123282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44335 | /* 123284 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44336 | /* 123286 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44337 | /* 123290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44338 | /* 123293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44339 | /* 123299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44340 | /* 123305 */ GIR_RootConstrainSelectedInstOperands, |
| 44341 | /* 123306 */ // GIR_Coverage, 6661, |
| 44342 | /* 123306 */ GIR_EraseRootFromParent_Done, |
| 44343 | /* 123307 */ // Label 3721: @123307 |
| 44344 | /* 123307 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3722*/ GIMT_Encode4(123365), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4096 // |
| 44345 | /* 123314 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44346 | /* 123318 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44347 | /* 123322 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44348 | /* 123326 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44349 | /* 123330 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44350 | /* 123335 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44351 | /* 123337 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 44352 | /* 123337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8), |
| 44353 | /* 123340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44354 | /* 123342 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44355 | /* 123344 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44356 | /* 123348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44357 | /* 123351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44358 | /* 123357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44359 | /* 123363 */ GIR_RootConstrainSelectedInstOperands, |
| 44360 | /* 123364 */ // GIR_Coverage, 4096, |
| 44361 | /* 123364 */ GIR_EraseRootFromParent_Done, |
| 44362 | /* 123365 */ // Label 3722: @123365 |
| 44363 | /* 123365 */ GIM_Reject, |
| 44364 | /* 123366 */ // Label 3720: @123366 |
| 44365 | /* 123366 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3723*/ GIMT_Encode4(123405), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1390 // |
| 44366 | /* 123373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44367 | /* 123377 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44368 | /* 123381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44369 | /* 123385 */ // (umin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 44370 | /* 123385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv16i8), |
| 44371 | /* 123388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44372 | /* 123390 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44373 | /* 123392 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44374 | /* 123394 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44375 | /* 123397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44376 | /* 123403 */ GIR_RootConstrainSelectedInstOperands, |
| 44377 | /* 123404 */ // GIR_Coverage, 1390, |
| 44378 | /* 123404 */ GIR_EraseRootFromParent_Done, |
| 44379 | /* 123405 */ // Label 3723: @123405 |
| 44380 | /* 123405 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3724*/ GIMT_Encode4(123465), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3700 // |
| 44381 | /* 123412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44382 | /* 123416 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44383 | /* 123420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44384 | /* 123424 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 44385 | /* 123424 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44386 | /* 123427 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44387 | /* 123431 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44388 | /* 123436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu8), |
| 44389 | /* 123439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44390 | /* 123441 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44391 | /* 123443 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44392 | /* 123445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44393 | /* 123448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44394 | /* 123454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44395 | /* 123460 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44396 | /* 123463 */ GIR_RootConstrainSelectedInstOperands, |
| 44397 | /* 123464 */ // GIR_Coverage, 3700, |
| 44398 | /* 123464 */ GIR_EraseRootFromParent_Done, |
| 44399 | /* 123465 */ // Label 3724: @123465 |
| 44400 | /* 123465 */ GIM_Reject, |
| 44401 | /* 123466 */ // Label 3719: @123466 |
| 44402 | /* 123466 */ GIM_Reject, |
| 44403 | /* 123467 */ // Label 3713: @123467 |
| 44404 | /* 123467 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3725*/ GIMT_Encode4(123512), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1385 // |
| 44405 | /* 123474 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44406 | /* 123477 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44407 | /* 123480 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44408 | /* 123484 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44409 | /* 123488 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44410 | /* 123492 */ // (umin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 44411 | /* 123492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i16), |
| 44412 | /* 123495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44413 | /* 123497 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44414 | /* 123499 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44415 | /* 123501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44416 | /* 123504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44417 | /* 123510 */ GIR_RootConstrainSelectedInstOperands, |
| 44418 | /* 123511 */ // GIR_Coverage, 1385, |
| 44419 | /* 123511 */ GIR_EraseRootFromParent_Done, |
| 44420 | /* 123512 */ // Label 3725: @123512 |
| 44421 | /* 123512 */ GIM_Reject, |
| 44422 | /* 123513 */ // Label 3714: @123513 |
| 44423 | /* 123513 */ GIM_Try, /*On fail goto*//*Label 3726*/ GIMT_Encode4(123750), |
| 44424 | /* 123518 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44425 | /* 123521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44426 | /* 123524 */ GIM_Try, /*On fail goto*//*Label 3727*/ GIMT_Encode4(123650), |
| 44427 | /* 123529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44428 | /* 123533 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3728*/ GIMT_Encode4(123591), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6662 // |
| 44429 | /* 123540 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44430 | /* 123544 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44431 | /* 123548 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44432 | /* 123552 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44433 | /* 123557 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44434 | /* 123561 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44435 | /* 123563 */ // (umin:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 44436 | /* 123563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16), |
| 44437 | /* 123566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44438 | /* 123568 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44439 | /* 123570 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44440 | /* 123574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44441 | /* 123577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44442 | /* 123583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44443 | /* 123589 */ GIR_RootConstrainSelectedInstOperands, |
| 44444 | /* 123590 */ // GIR_Coverage, 6662, |
| 44445 | /* 123590 */ GIR_EraseRootFromParent_Done, |
| 44446 | /* 123591 */ // Label 3728: @123591 |
| 44447 | /* 123591 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3729*/ GIMT_Encode4(123649), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4098 // |
| 44448 | /* 123598 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44449 | /* 123602 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44450 | /* 123606 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44451 | /* 123610 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44452 | /* 123614 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44453 | /* 123619 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44454 | /* 123621 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 44455 | /* 123621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16), |
| 44456 | /* 123624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44457 | /* 123626 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44458 | /* 123628 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44459 | /* 123632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44460 | /* 123635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44461 | /* 123641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44462 | /* 123647 */ GIR_RootConstrainSelectedInstOperands, |
| 44463 | /* 123648 */ // GIR_Coverage, 4098, |
| 44464 | /* 123648 */ GIR_EraseRootFromParent_Done, |
| 44465 | /* 123649 */ // Label 3729: @123649 |
| 44466 | /* 123649 */ GIM_Reject, |
| 44467 | /* 123650 */ // Label 3727: @123650 |
| 44468 | /* 123650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3730*/ GIMT_Encode4(123689), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1387 // |
| 44469 | /* 123657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44470 | /* 123661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44471 | /* 123665 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44472 | /* 123669 */ // (umin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 44473 | /* 123669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i16), |
| 44474 | /* 123672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44475 | /* 123674 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44476 | /* 123676 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44477 | /* 123678 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44478 | /* 123681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44479 | /* 123687 */ GIR_RootConstrainSelectedInstOperands, |
| 44480 | /* 123688 */ // GIR_Coverage, 1387, |
| 44481 | /* 123688 */ GIR_EraseRootFromParent_Done, |
| 44482 | /* 123689 */ // Label 3730: @123689 |
| 44483 | /* 123689 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3731*/ GIMT_Encode4(123749), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3703 // |
| 44484 | /* 123696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44485 | /* 123700 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44486 | /* 123704 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44487 | /* 123708 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 44488 | /* 123708 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44489 | /* 123711 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44490 | /* 123715 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44491 | /* 123720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu16), |
| 44492 | /* 123723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44493 | /* 123725 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44494 | /* 123727 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44495 | /* 123729 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44496 | /* 123732 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44497 | /* 123738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44498 | /* 123744 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44499 | /* 123747 */ GIR_RootConstrainSelectedInstOperands, |
| 44500 | /* 123748 */ // GIR_Coverage, 3703, |
| 44501 | /* 123748 */ GIR_EraseRootFromParent_Done, |
| 44502 | /* 123749 */ // Label 3731: @123749 |
| 44503 | /* 123749 */ GIM_Reject, |
| 44504 | /* 123750 */ // Label 3726: @123750 |
| 44505 | /* 123750 */ GIM_Reject, |
| 44506 | /* 123751 */ // Label 3715: @123751 |
| 44507 | /* 123751 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3732*/ GIMT_Encode4(123796), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1386 // |
| 44508 | /* 123758 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 44509 | /* 123761 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44510 | /* 123764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44511 | /* 123768 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44512 | /* 123772 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44513 | /* 123776 */ // (umin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 44514 | /* 123776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv2i32), |
| 44515 | /* 123779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44516 | /* 123781 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44517 | /* 123783 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44518 | /* 123785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44519 | /* 123788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44520 | /* 123794 */ GIR_RootConstrainSelectedInstOperands, |
| 44521 | /* 123795 */ // GIR_Coverage, 1386, |
| 44522 | /* 123795 */ GIR_EraseRootFromParent_Done, |
| 44523 | /* 123796 */ // Label 3732: @123796 |
| 44524 | /* 123796 */ GIM_Reject, |
| 44525 | /* 123797 */ // Label 3716: @123797 |
| 44526 | /* 123797 */ GIM_Try, /*On fail goto*//*Label 3733*/ GIMT_Encode4(124034), |
| 44527 | /* 123802 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44528 | /* 123805 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44529 | /* 123808 */ GIM_Try, /*On fail goto*//*Label 3734*/ GIMT_Encode4(123934), |
| 44530 | /* 123813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44531 | /* 123817 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3735*/ GIMT_Encode4(123875), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6663 // |
| 44532 | /* 123824 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44533 | /* 123828 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44534 | /* 123832 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44535 | /* 123836 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44536 | /* 123841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44537 | /* 123845 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44538 | /* 123847 */ // (umin:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 44539 | /* 123847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32), |
| 44540 | /* 123850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44541 | /* 123852 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44542 | /* 123854 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44543 | /* 123858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44544 | /* 123861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44545 | /* 123867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44546 | /* 123873 */ GIR_RootConstrainSelectedInstOperands, |
| 44547 | /* 123874 */ // GIR_Coverage, 6663, |
| 44548 | /* 123874 */ GIR_EraseRootFromParent_Done, |
| 44549 | /* 123875 */ // Label 3735: @123875 |
| 44550 | /* 123875 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3736*/ GIMT_Encode4(123933), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4100 // |
| 44551 | /* 123882 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44552 | /* 123886 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44553 | /* 123890 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44554 | /* 123894 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44555 | /* 123898 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44556 | /* 123903 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44557 | /* 123905 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 44558 | /* 123905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32), |
| 44559 | /* 123908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44560 | /* 123910 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44561 | /* 123912 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44562 | /* 123916 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44563 | /* 123919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44564 | /* 123925 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44565 | /* 123931 */ GIR_RootConstrainSelectedInstOperands, |
| 44566 | /* 123932 */ // GIR_Coverage, 4100, |
| 44567 | /* 123932 */ GIR_EraseRootFromParent_Done, |
| 44568 | /* 123933 */ // Label 3736: @123933 |
| 44569 | /* 123933 */ GIM_Reject, |
| 44570 | /* 123934 */ // Label 3734: @123934 |
| 44571 | /* 123934 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3737*/ GIMT_Encode4(123973), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1388 // |
| 44572 | /* 123941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44573 | /* 123945 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44574 | /* 123949 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44575 | /* 123953 */ // (umin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 44576 | /* 123953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i32), |
| 44577 | /* 123956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44578 | /* 123958 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44579 | /* 123960 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44580 | /* 123962 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44581 | /* 123965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44582 | /* 123971 */ GIR_RootConstrainSelectedInstOperands, |
| 44583 | /* 123972 */ // GIR_Coverage, 1388, |
| 44584 | /* 123972 */ GIR_EraseRootFromParent_Done, |
| 44585 | /* 123973 */ // Label 3737: @123973 |
| 44586 | /* 123973 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3738*/ GIMT_Encode4(124033), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3706 // |
| 44587 | /* 123980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44588 | /* 123984 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44589 | /* 123988 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44590 | /* 123992 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 44591 | /* 123992 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44592 | /* 123995 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44593 | /* 123999 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44594 | /* 124004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu32), |
| 44595 | /* 124007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44596 | /* 124009 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44597 | /* 124011 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44598 | /* 124013 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44599 | /* 124016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44600 | /* 124022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44601 | /* 124028 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44602 | /* 124031 */ GIR_RootConstrainSelectedInstOperands, |
| 44603 | /* 124032 */ // GIR_Coverage, 3706, |
| 44604 | /* 124032 */ GIR_EraseRootFromParent_Done, |
| 44605 | /* 124033 */ // Label 3738: @124033 |
| 44606 | /* 124033 */ GIM_Reject, |
| 44607 | /* 124034 */ // Label 3733: @124034 |
| 44608 | /* 124034 */ GIM_Reject, |
| 44609 | /* 124035 */ // Label 3717: @124035 |
| 44610 | /* 124035 */ GIM_Reject, |
| 44611 | /* 124036 */ // Label 66: @124036 |
| 44612 | /* 124036 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3745*/ GIMT_Encode4(124923), |
| 44613 | /* 124047 */ /*GILLT_v8s8*//*Label 3739*/ GIMT_Encode4(124071), |
| 44614 | /* 124051 */ /*GILLT_v16s8*//*Label 3740*/ GIMT_Encode4(124117), |
| 44615 | /* 124055 */ /*GILLT_v4s16*//*Label 3741*/ GIMT_Encode4(124355), |
| 44616 | /* 124059 */ /*GILLT_v8s16*//*Label 3742*/ GIMT_Encode4(124401), |
| 44617 | /* 124063 */ /*GILLT_v2s32*//*Label 3743*/ GIMT_Encode4(124639), |
| 44618 | /* 124067 */ /*GILLT_v4s32*//*Label 3744*/ GIMT_Encode4(124685), |
| 44619 | /* 124071 */ // Label 3739: @124071 |
| 44620 | /* 124071 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3746*/ GIMT_Encode4(124116), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1369 // |
| 44621 | /* 124078 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44622 | /* 124081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 44623 | /* 124084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44624 | /* 124088 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44625 | /* 124092 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44626 | /* 124096 */ // (umax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 44627 | /* 124096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i8), |
| 44628 | /* 124099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44629 | /* 124101 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44630 | /* 124103 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44631 | /* 124105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44632 | /* 124108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44633 | /* 124114 */ GIR_RootConstrainSelectedInstOperands, |
| 44634 | /* 124115 */ // GIR_Coverage, 1369, |
| 44635 | /* 124115 */ GIR_EraseRootFromParent_Done, |
| 44636 | /* 124116 */ // Label 3746: @124116 |
| 44637 | /* 124116 */ GIM_Reject, |
| 44638 | /* 124117 */ // Label 3740: @124117 |
| 44639 | /* 124117 */ GIM_Try, /*On fail goto*//*Label 3747*/ GIMT_Encode4(124354), |
| 44640 | /* 124122 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44641 | /* 124125 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 44642 | /* 124128 */ GIM_Try, /*On fail goto*//*Label 3748*/ GIMT_Encode4(124254), |
| 44643 | /* 124133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44644 | /* 124137 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3749*/ GIMT_Encode4(124195), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6664 // |
| 44645 | /* 124144 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44646 | /* 124148 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44647 | /* 124152 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44648 | /* 124156 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44649 | /* 124161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44650 | /* 124165 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44651 | /* 124167 */ // (umax:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 44652 | /* 124167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8), |
| 44653 | /* 124170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44654 | /* 124172 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44655 | /* 124174 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44656 | /* 124178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44657 | /* 124181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44658 | /* 124187 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44659 | /* 124193 */ GIR_RootConstrainSelectedInstOperands, |
| 44660 | /* 124194 */ // GIR_Coverage, 6664, |
| 44661 | /* 124194 */ GIR_EraseRootFromParent_Done, |
| 44662 | /* 124195 */ // Label 3749: @124195 |
| 44663 | /* 124195 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3750*/ GIMT_Encode4(124253), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4102 // |
| 44664 | /* 124202 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44665 | /* 124206 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44666 | /* 124210 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44667 | /* 124214 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44668 | /* 124218 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44669 | /* 124223 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44670 | /* 124225 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 44671 | /* 124225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8), |
| 44672 | /* 124228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44673 | /* 124230 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44674 | /* 124232 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44675 | /* 124236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44676 | /* 124239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44677 | /* 124245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44678 | /* 124251 */ GIR_RootConstrainSelectedInstOperands, |
| 44679 | /* 124252 */ // GIR_Coverage, 4102, |
| 44680 | /* 124252 */ GIR_EraseRootFromParent_Done, |
| 44681 | /* 124253 */ // Label 3750: @124253 |
| 44682 | /* 124253 */ GIM_Reject, |
| 44683 | /* 124254 */ // Label 3748: @124254 |
| 44684 | /* 124254 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3751*/ GIMT_Encode4(124293), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1370 // |
| 44685 | /* 124261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44686 | /* 124265 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44687 | /* 124269 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44688 | /* 124273 */ // (umax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 44689 | /* 124273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv16i8), |
| 44690 | /* 124276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44691 | /* 124278 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44692 | /* 124280 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44693 | /* 124282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44694 | /* 124285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44695 | /* 124291 */ GIR_RootConstrainSelectedInstOperands, |
| 44696 | /* 124292 */ // GIR_Coverage, 1370, |
| 44697 | /* 124292 */ GIR_EraseRootFromParent_Done, |
| 44698 | /* 124293 */ // Label 3751: @124293 |
| 44699 | /* 124293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3752*/ GIMT_Encode4(124353), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3718 // |
| 44700 | /* 124300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44701 | /* 124304 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44702 | /* 124308 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44703 | /* 124312 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 44704 | /* 124312 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44705 | /* 124315 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44706 | /* 124319 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44707 | /* 124324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu8), |
| 44708 | /* 124327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44709 | /* 124329 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44710 | /* 124331 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44711 | /* 124333 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44712 | /* 124336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44713 | /* 124342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44714 | /* 124348 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44715 | /* 124351 */ GIR_RootConstrainSelectedInstOperands, |
| 44716 | /* 124352 */ // GIR_Coverage, 3718, |
| 44717 | /* 124352 */ GIR_EraseRootFromParent_Done, |
| 44718 | /* 124353 */ // Label 3752: @124353 |
| 44719 | /* 124353 */ GIM_Reject, |
| 44720 | /* 124354 */ // Label 3747: @124354 |
| 44721 | /* 124354 */ GIM_Reject, |
| 44722 | /* 124355 */ // Label 3741: @124355 |
| 44723 | /* 124355 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3753*/ GIMT_Encode4(124400), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1365 // |
| 44724 | /* 124362 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44725 | /* 124365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44726 | /* 124368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44727 | /* 124372 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44728 | /* 124376 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44729 | /* 124380 */ // (umax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 44730 | /* 124380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i16), |
| 44731 | /* 124383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44732 | /* 124385 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44733 | /* 124387 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44734 | /* 124389 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44735 | /* 124392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44736 | /* 124398 */ GIR_RootConstrainSelectedInstOperands, |
| 44737 | /* 124399 */ // GIR_Coverage, 1365, |
| 44738 | /* 124399 */ GIR_EraseRootFromParent_Done, |
| 44739 | /* 124400 */ // Label 3753: @124400 |
| 44740 | /* 124400 */ GIM_Reject, |
| 44741 | /* 124401 */ // Label 3742: @124401 |
| 44742 | /* 124401 */ GIM_Try, /*On fail goto*//*Label 3754*/ GIMT_Encode4(124638), |
| 44743 | /* 124406 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44744 | /* 124409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44745 | /* 124412 */ GIM_Try, /*On fail goto*//*Label 3755*/ GIMT_Encode4(124538), |
| 44746 | /* 124417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44747 | /* 124421 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3756*/ GIMT_Encode4(124479), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6665 // |
| 44748 | /* 124428 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44749 | /* 124432 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44750 | /* 124436 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44751 | /* 124440 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44752 | /* 124445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44753 | /* 124449 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44754 | /* 124451 */ // (umax:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 44755 | /* 124451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16), |
| 44756 | /* 124454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44757 | /* 124456 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44758 | /* 124458 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44759 | /* 124462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44760 | /* 124465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44761 | /* 124471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44762 | /* 124477 */ GIR_RootConstrainSelectedInstOperands, |
| 44763 | /* 124478 */ // GIR_Coverage, 6665, |
| 44764 | /* 124478 */ GIR_EraseRootFromParent_Done, |
| 44765 | /* 124479 */ // Label 3756: @124479 |
| 44766 | /* 124479 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3757*/ GIMT_Encode4(124537), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4104 // |
| 44767 | /* 124486 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44768 | /* 124490 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44769 | /* 124494 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44770 | /* 124498 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44771 | /* 124502 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44772 | /* 124507 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44773 | /* 124509 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 44774 | /* 124509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16), |
| 44775 | /* 124512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44776 | /* 124514 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44777 | /* 124516 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44778 | /* 124520 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44779 | /* 124523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44780 | /* 124529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44781 | /* 124535 */ GIR_RootConstrainSelectedInstOperands, |
| 44782 | /* 124536 */ // GIR_Coverage, 4104, |
| 44783 | /* 124536 */ GIR_EraseRootFromParent_Done, |
| 44784 | /* 124537 */ // Label 3757: @124537 |
| 44785 | /* 124537 */ GIM_Reject, |
| 44786 | /* 124538 */ // Label 3755: @124538 |
| 44787 | /* 124538 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3758*/ GIMT_Encode4(124577), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1367 // |
| 44788 | /* 124545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44789 | /* 124549 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44790 | /* 124553 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44791 | /* 124557 */ // (umax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 44792 | /* 124557 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i16), |
| 44793 | /* 124560 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44794 | /* 124562 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44795 | /* 124564 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44796 | /* 124566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44797 | /* 124569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44798 | /* 124575 */ GIR_RootConstrainSelectedInstOperands, |
| 44799 | /* 124576 */ // GIR_Coverage, 1367, |
| 44800 | /* 124576 */ GIR_EraseRootFromParent_Done, |
| 44801 | /* 124577 */ // Label 3758: @124577 |
| 44802 | /* 124577 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3759*/ GIMT_Encode4(124637), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3721 // |
| 44803 | /* 124584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44804 | /* 124588 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44805 | /* 124592 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44806 | /* 124596 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 44807 | /* 124596 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44808 | /* 124599 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44809 | /* 124603 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44810 | /* 124608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu16), |
| 44811 | /* 124611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44812 | /* 124613 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44813 | /* 124615 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44814 | /* 124617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44815 | /* 124620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44816 | /* 124626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44817 | /* 124632 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44818 | /* 124635 */ GIR_RootConstrainSelectedInstOperands, |
| 44819 | /* 124636 */ // GIR_Coverage, 3721, |
| 44820 | /* 124636 */ GIR_EraseRootFromParent_Done, |
| 44821 | /* 124637 */ // Label 3759: @124637 |
| 44822 | /* 124637 */ GIM_Reject, |
| 44823 | /* 124638 */ // Label 3754: @124638 |
| 44824 | /* 124638 */ GIM_Reject, |
| 44825 | /* 124639 */ // Label 3743: @124639 |
| 44826 | /* 124639 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3760*/ GIMT_Encode4(124684), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1366 // |
| 44827 | /* 124646 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 44828 | /* 124649 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44829 | /* 124652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44830 | /* 124656 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44831 | /* 124660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44832 | /* 124664 */ // (umax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 44833 | /* 124664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv2i32), |
| 44834 | /* 124667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44835 | /* 124669 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44836 | /* 124671 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44837 | /* 124673 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44838 | /* 124676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44839 | /* 124682 */ GIR_RootConstrainSelectedInstOperands, |
| 44840 | /* 124683 */ // GIR_Coverage, 1366, |
| 44841 | /* 124683 */ GIR_EraseRootFromParent_Done, |
| 44842 | /* 124684 */ // Label 3760: @124684 |
| 44843 | /* 124684 */ GIM_Reject, |
| 44844 | /* 124685 */ // Label 3744: @124685 |
| 44845 | /* 124685 */ GIM_Try, /*On fail goto*//*Label 3761*/ GIMT_Encode4(124922), |
| 44846 | /* 124690 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44847 | /* 124693 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44848 | /* 124696 */ GIM_Try, /*On fail goto*//*Label 3762*/ GIMT_Encode4(124822), |
| 44849 | /* 124701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44850 | /* 124705 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3763*/ GIMT_Encode4(124763), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6666 // |
| 44851 | /* 124712 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44852 | /* 124716 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44853 | /* 124720 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44854 | /* 124724 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44855 | /* 124729 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44856 | /* 124733 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44857 | /* 124735 */ // (umax:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 44858 | /* 124735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32), |
| 44859 | /* 124738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44860 | /* 124740 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44861 | /* 124742 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44862 | /* 124746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44863 | /* 124749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44864 | /* 124755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44865 | /* 124761 */ GIR_RootConstrainSelectedInstOperands, |
| 44866 | /* 124762 */ // GIR_Coverage, 6666, |
| 44867 | /* 124762 */ GIR_EraseRootFromParent_Done, |
| 44868 | /* 124763 */ // Label 3763: @124763 |
| 44869 | /* 124763 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3764*/ GIMT_Encode4(124821), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4106 // |
| 44870 | /* 124770 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44871 | /* 124774 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44872 | /* 124778 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44873 | /* 124782 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44874 | /* 124786 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44875 | /* 124791 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44876 | /* 124793 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 44877 | /* 124793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32), |
| 44878 | /* 124796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44879 | /* 124798 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44880 | /* 124800 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44881 | /* 124804 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44882 | /* 124807 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44883 | /* 124813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44884 | /* 124819 */ GIR_RootConstrainSelectedInstOperands, |
| 44885 | /* 124820 */ // GIR_Coverage, 4106, |
| 44886 | /* 124820 */ GIR_EraseRootFromParent_Done, |
| 44887 | /* 124821 */ // Label 3764: @124821 |
| 44888 | /* 124821 */ GIM_Reject, |
| 44889 | /* 124822 */ // Label 3762: @124822 |
| 44890 | /* 124822 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3765*/ GIMT_Encode4(124861), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1368 // |
| 44891 | /* 124829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44892 | /* 124833 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44893 | /* 124837 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44894 | /* 124841 */ // (umax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 44895 | /* 124841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i32), |
| 44896 | /* 124844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44897 | /* 124846 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44898 | /* 124848 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44899 | /* 124850 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44900 | /* 124853 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44901 | /* 124859 */ GIR_RootConstrainSelectedInstOperands, |
| 44902 | /* 124860 */ // GIR_Coverage, 1368, |
| 44903 | /* 124860 */ GIR_EraseRootFromParent_Done, |
| 44904 | /* 124861 */ // Label 3765: @124861 |
| 44905 | /* 124861 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3766*/ GIMT_Encode4(124921), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3724 // |
| 44906 | /* 124868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44907 | /* 124872 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44908 | /* 124876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44909 | /* 124880 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 44910 | /* 124880 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44911 | /* 124883 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44912 | /* 124887 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44913 | /* 124892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu32), |
| 44914 | /* 124895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44915 | /* 124897 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44916 | /* 124899 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44917 | /* 124901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44918 | /* 124904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44919 | /* 124910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44920 | /* 124916 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44921 | /* 124919 */ GIR_RootConstrainSelectedInstOperands, |
| 44922 | /* 124920 */ // GIR_Coverage, 3724, |
| 44923 | /* 124920 */ GIR_EraseRootFromParent_Done, |
| 44924 | /* 124921 */ // Label 3766: @124921 |
| 44925 | /* 124921 */ GIM_Reject, |
| 44926 | /* 124922 */ // Label 3761: @124922 |
| 44927 | /* 124922 */ GIM_Reject, |
| 44928 | /* 124923 */ // Label 3745: @124923 |
| 44929 | /* 124923 */ GIM_Reject, |
| 44930 | /* 124924 */ // Label 67: @124924 |
| 44931 | /* 124924 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3773*/ GIMT_Encode4(125361), |
| 44932 | /* 124935 */ /*GILLT_v8s8*//*Label 3767*/ GIMT_Encode4(124959), |
| 44933 | /* 124939 */ /*GILLT_v16s8*//*Label 3768*/ GIMT_Encode4(124996), |
| 44934 | /* 124943 */ /*GILLT_v4s16*//*Label 3769*/ GIMT_Encode4(125093), |
| 44935 | /* 124947 */ /*GILLT_v8s16*//*Label 3770*/ GIMT_Encode4(125130), |
| 44936 | /* 124951 */ /*GILLT_v2s32*//*Label 3771*/ GIMT_Encode4(125227), |
| 44937 | /* 124955 */ /*GILLT_v4s32*//*Label 3772*/ GIMT_Encode4(125264), |
| 44938 | /* 124959 */ // Label 3767: @124959 |
| 44939 | /* 124959 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3774*/ GIMT_Encode4(124995), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1670 // |
| 44940 | /* 124966 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44941 | /* 124969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44942 | /* 124973 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44943 | /* 124977 */ // (abs:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 44944 | /* 124977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i8), |
| 44945 | /* 124980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44946 | /* 124982 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44947 | /* 124984 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44948 | /* 124987 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44949 | /* 124993 */ GIR_RootConstrainSelectedInstOperands, |
| 44950 | /* 124994 */ // GIR_Coverage, 1670, |
| 44951 | /* 124994 */ GIR_EraseRootFromParent_Done, |
| 44952 | /* 124995 */ // Label 3774: @124995 |
| 44953 | /* 124995 */ GIM_Reject, |
| 44954 | /* 124996 */ // Label 3768: @124996 |
| 44955 | /* 124996 */ GIM_Try, /*On fail goto*//*Label 3775*/ GIMT_Encode4(125092), |
| 44956 | /* 125001 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44957 | /* 125004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3776*/ GIMT_Encode4(125037), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1673 // |
| 44958 | /* 125011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44959 | /* 125015 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44960 | /* 125019 */ // (abs:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 44961 | /* 125019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv16i8), |
| 44962 | /* 125022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44963 | /* 125024 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44964 | /* 125026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44965 | /* 125029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44966 | /* 125035 */ GIR_RootConstrainSelectedInstOperands, |
| 44967 | /* 125036 */ // GIR_Coverage, 1673, |
| 44968 | /* 125036 */ GIR_EraseRootFromParent_Done, |
| 44969 | /* 125037 */ // Label 3776: @125037 |
| 44970 | /* 125037 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3777*/ GIMT_Encode4(125091), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4057 // |
| 44971 | /* 125044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44972 | /* 125048 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44973 | /* 125052 */ // (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v) => (MVE_VABSs8:{ *:[v16i8] } ?:{ *:[v16i8] }:$v) |
| 44974 | /* 125052 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44975 | /* 125055 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44976 | /* 125059 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44977 | /* 125064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs8), |
| 44978 | /* 125067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44979 | /* 125069 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 44980 | /* 125071 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44981 | /* 125074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44982 | /* 125080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44983 | /* 125086 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44984 | /* 125089 */ GIR_RootConstrainSelectedInstOperands, |
| 44985 | /* 125090 */ // GIR_Coverage, 4057, |
| 44986 | /* 125090 */ GIR_EraseRootFromParent_Done, |
| 44987 | /* 125091 */ // Label 3777: @125091 |
| 44988 | /* 125091 */ GIM_Reject, |
| 44989 | /* 125092 */ // Label 3775: @125092 |
| 44990 | /* 125092 */ GIM_Reject, |
| 44991 | /* 125093 */ // Label 3769: @125093 |
| 44992 | /* 125093 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3778*/ GIMT_Encode4(125129), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1671 // |
| 44993 | /* 125100 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44994 | /* 125103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44995 | /* 125107 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44996 | /* 125111 */ // (abs:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 44997 | /* 125111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i16), |
| 44998 | /* 125114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44999 | /* 125116 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45000 | /* 125118 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45001 | /* 125121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45002 | /* 125127 */ GIR_RootConstrainSelectedInstOperands, |
| 45003 | /* 125128 */ // GIR_Coverage, 1671, |
| 45004 | /* 125128 */ GIR_EraseRootFromParent_Done, |
| 45005 | /* 125129 */ // Label 3778: @125129 |
| 45006 | /* 125129 */ GIM_Reject, |
| 45007 | /* 125130 */ // Label 3770: @125130 |
| 45008 | /* 125130 */ GIM_Try, /*On fail goto*//*Label 3779*/ GIMT_Encode4(125226), |
| 45009 | /* 125135 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45010 | /* 125138 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3780*/ GIMT_Encode4(125171), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1674 // |
| 45011 | /* 125145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45012 | /* 125149 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45013 | /* 125153 */ // (abs:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 45014 | /* 125153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i16), |
| 45015 | /* 125156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45016 | /* 125158 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45017 | /* 125160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45018 | /* 125163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45019 | /* 125169 */ GIR_RootConstrainSelectedInstOperands, |
| 45020 | /* 125170 */ // GIR_Coverage, 1674, |
| 45021 | /* 125170 */ GIR_EraseRootFromParent_Done, |
| 45022 | /* 125171 */ // Label 3780: @125171 |
| 45023 | /* 125171 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3781*/ GIMT_Encode4(125225), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4063 // |
| 45024 | /* 125178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45025 | /* 125182 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45026 | /* 125186 */ // (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v) => (MVE_VABSs16:{ *:[v8i16] } ?:{ *:[v8i16] }:$v) |
| 45027 | /* 125186 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45028 | /* 125189 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45029 | /* 125193 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45030 | /* 125198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs16), |
| 45031 | /* 125201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45032 | /* 125203 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 45033 | /* 125205 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45034 | /* 125208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45035 | /* 125214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45036 | /* 125220 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45037 | /* 125223 */ GIR_RootConstrainSelectedInstOperands, |
| 45038 | /* 125224 */ // GIR_Coverage, 4063, |
| 45039 | /* 125224 */ GIR_EraseRootFromParent_Done, |
| 45040 | /* 125225 */ // Label 3781: @125225 |
| 45041 | /* 125225 */ GIM_Reject, |
| 45042 | /* 125226 */ // Label 3779: @125226 |
| 45043 | /* 125226 */ GIM_Reject, |
| 45044 | /* 125227 */ // Label 3771: @125227 |
| 45045 | /* 125227 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3782*/ GIMT_Encode4(125263), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1672 // |
| 45046 | /* 125234 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45047 | /* 125237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45048 | /* 125241 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45049 | /* 125245 */ // (abs:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 45050 | /* 125245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv2i32), |
| 45051 | /* 125248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45052 | /* 125250 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45053 | /* 125252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45054 | /* 125255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45055 | /* 125261 */ GIR_RootConstrainSelectedInstOperands, |
| 45056 | /* 125262 */ // GIR_Coverage, 1672, |
| 45057 | /* 125262 */ GIR_EraseRootFromParent_Done, |
| 45058 | /* 125263 */ // Label 3782: @125263 |
| 45059 | /* 125263 */ GIM_Reject, |
| 45060 | /* 125264 */ // Label 3772: @125264 |
| 45061 | /* 125264 */ GIM_Try, /*On fail goto*//*Label 3783*/ GIMT_Encode4(125360), |
| 45062 | /* 125269 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45063 | /* 125272 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3784*/ GIMT_Encode4(125305), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1675 // |
| 45064 | /* 125279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45065 | /* 125283 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45066 | /* 125287 */ // (abs:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 45067 | /* 125287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i32), |
| 45068 | /* 125290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45069 | /* 125292 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45070 | /* 125294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45071 | /* 125297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45072 | /* 125303 */ GIR_RootConstrainSelectedInstOperands, |
| 45073 | /* 125304 */ // GIR_Coverage, 1675, |
| 45074 | /* 125304 */ GIR_EraseRootFromParent_Done, |
| 45075 | /* 125305 */ // Label 3784: @125305 |
| 45076 | /* 125305 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3785*/ GIMT_Encode4(125359), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4069 // |
| 45077 | /* 125312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45078 | /* 125316 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45079 | /* 125320 */ // (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v) => (MVE_VABSs32:{ *:[v4i32] } ?:{ *:[v4i32] }:$v) |
| 45080 | /* 125320 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45081 | /* 125323 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45082 | /* 125327 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45083 | /* 125332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs32), |
| 45084 | /* 125335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45085 | /* 125337 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 45086 | /* 125339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45087 | /* 125342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45088 | /* 125348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45089 | /* 125354 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45090 | /* 125357 */ GIR_RootConstrainSelectedInstOperands, |
| 45091 | /* 125358 */ // GIR_Coverage, 4069, |
| 45092 | /* 125358 */ GIR_EraseRootFromParent_Done, |
| 45093 | /* 125359 */ // Label 3785: @125359 |
| 45094 | /* 125359 */ GIM_Reject, |
| 45095 | /* 125360 */ // Label 3783: @125360 |
| 45096 | /* 125360 */ GIM_Reject, |
| 45097 | /* 125361 */ // Label 3773: @125361 |
| 45098 | /* 125361 */ GIM_Reject, |
| 45099 | /* 125362 */ // Label 68: @125362 |
| 45100 | /* 125362 */ GIM_Try, /*On fail goto*//*Label 3786*/ GIMT_Encode4(125431), |
| 45101 | /* 125367 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/0, |
| 45102 | /* 125370 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3787*/ GIMT_Encode4(125384), GIMT_Encode2(GIFBS_IsARM), // Rule ID 31 // |
| 45103 | /* 125377 */ // (br (bb:{ *:[Other] }):$target) => (B (bb:{ *:[Other] }):$target) |
| 45104 | /* 125377 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::B), |
| 45105 | /* 125382 */ GIR_RootConstrainSelectedInstOperands, |
| 45106 | /* 125383 */ // GIR_Coverage, 31, |
| 45107 | /* 125383 */ GIR_Done, |
| 45108 | /* 125384 */ // Label 3787: @125384 |
| 45109 | /* 125384 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3788*/ GIMT_Encode4(125407), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 282 // |
| 45110 | /* 125391 */ // (br (bb:{ *:[Other] }):$target) => (tB (bb:{ *:[Other] }):$target) |
| 45111 | /* 125391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tB), |
| 45112 | /* 125394 */ GIR_RootToRootCopy, /*OpIdx*/0, // target |
| 45113 | /* 125396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45114 | /* 125399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45115 | /* 125405 */ GIR_RootConstrainSelectedInstOperands, |
| 45116 | /* 125406 */ // GIR_Coverage, 282, |
| 45117 | /* 125406 */ GIR_EraseRootFromParent_Done, |
| 45118 | /* 125407 */ // Label 3788: @125407 |
| 45119 | /* 125407 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3789*/ GIMT_Encode4(125430), GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb), // Rule ID 576 // |
| 45120 | /* 125414 */ // (br (bb:{ *:[Other] }):$target) => (t2B (bb:{ *:[Other] }):$target) |
| 45121 | /* 125414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2B), |
| 45122 | /* 125417 */ GIR_RootToRootCopy, /*OpIdx*/0, // target |
| 45123 | /* 125419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45124 | /* 125422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45125 | /* 125428 */ GIR_RootConstrainSelectedInstOperands, |
| 45126 | /* 125429 */ // GIR_Coverage, 576, |
| 45127 | /* 125429 */ GIR_EraseRootFromParent_Done, |
| 45128 | /* 125430 */ // Label 3789: @125430 |
| 45129 | /* 125430 */ GIM_Reject, |
| 45130 | /* 125431 */ // Label 3786: @125431 |
| 45131 | /* 125431 */ GIM_Reject, |
| 45132 | /* 125432 */ // Label 69: @125432 |
| 45133 | /* 125432 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(11), /*)*//*default:*//*Label 3794*/ GIMT_Encode4(125707), |
| 45134 | /* 125443 */ /*GILLT_v8s8*//*Label 3790*/ GIMT_Encode4(125459), |
| 45135 | /* 125447 */ /*GILLT_v16s8*//*Label 3791*/ GIMT_Encode4(125521), |
| 45136 | /* 125451 */ /*GILLT_v4s16*//*Label 3792*/ GIMT_Encode4(125583), |
| 45137 | /* 125455 */ /*GILLT_v8s16*//*Label 3793*/ GIMT_Encode4(125645), |
| 45138 | /* 125459 */ // Label 3790: @125459 |
| 45139 | /* 125459 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3795*/ GIMT_Encode4(125520), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1733 // |
| 45140 | /* 125466 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 45141 | /* 125469 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 45142 | /* 125472 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 45143 | /* 125475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45144 | /* 125479 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45145 | /* 125483 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45146 | /* 125487 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 45147 | /* 125491 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 45148 | /* 125495 */ // MIs[1] Operand 1 |
| 45149 | /* 125495 */ // No operand predicates |
| 45150 | /* 125495 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45151 | /* 125497 */ // (vector_insert:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) |
| 45152 | /* 125497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi8), |
| 45153 | /* 125500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V] |
| 45154 | /* 125502 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 45155 | /* 125504 */ GIR_RootToRootCopy, /*OpIdx*/2, // R |
| 45156 | /* 125506 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 45157 | /* 125509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45158 | /* 125512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45159 | /* 125518 */ GIR_RootConstrainSelectedInstOperands, |
| 45160 | /* 125519 */ // GIR_Coverage, 1733, |
| 45161 | /* 125519 */ GIR_EraseRootFromParent_Done, |
| 45162 | /* 125520 */ // Label 3795: @125520 |
| 45163 | /* 125520 */ GIM_Reject, |
| 45164 | /* 125521 */ // Label 3791: @125521 |
| 45165 | /* 125521 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3796*/ GIMT_Encode4(125582), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3832 // |
| 45166 | /* 125528 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 45167 | /* 125531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 45168 | /* 125534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 45169 | /* 125537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45170 | /* 125541 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45171 | /* 125545 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45172 | /* 125549 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 45173 | /* 125553 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 45174 | /* 125557 */ // MIs[1] Operand 1 |
| 45175 | /* 125557 */ // No operand predicates |
| 45176 | /* 125557 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45177 | /* 125559 */ // (vector_insert:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) |
| 45178 | /* 125559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_8), |
| 45179 | /* 125562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45180 | /* 125564 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 45181 | /* 125566 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 45182 | /* 125568 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 45183 | /* 125571 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45184 | /* 125574 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45185 | /* 125580 */ GIR_RootConstrainSelectedInstOperands, |
| 45186 | /* 125581 */ // GIR_Coverage, 3832, |
| 45187 | /* 125581 */ GIR_EraseRootFromParent_Done, |
| 45188 | /* 125582 */ // Label 3796: @125582 |
| 45189 | /* 125582 */ GIM_Reject, |
| 45190 | /* 125583 */ // Label 3792: @125583 |
| 45191 | /* 125583 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3797*/ GIMT_Encode4(125644), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1734 // |
| 45192 | /* 125590 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45193 | /* 125593 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 45194 | /* 125596 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 45195 | /* 125599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45196 | /* 125603 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45197 | /* 125607 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45198 | /* 125611 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 45199 | /* 125615 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 45200 | /* 125619 */ // MIs[1] Operand 1 |
| 45201 | /* 125619 */ // No operand predicates |
| 45202 | /* 125619 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45203 | /* 125621 */ // (vector_insert:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) |
| 45204 | /* 125621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi16), |
| 45205 | /* 125624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V] |
| 45206 | /* 125626 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 45207 | /* 125628 */ GIR_RootToRootCopy, /*OpIdx*/2, // R |
| 45208 | /* 125630 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 45209 | /* 125633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45210 | /* 125636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45211 | /* 125642 */ GIR_RootConstrainSelectedInstOperands, |
| 45212 | /* 125643 */ // GIR_Coverage, 1734, |
| 45213 | /* 125643 */ GIR_EraseRootFromParent_Done, |
| 45214 | /* 125644 */ // Label 3797: @125644 |
| 45215 | /* 125644 */ GIM_Reject, |
| 45216 | /* 125645 */ // Label 3793: @125645 |
| 45217 | /* 125645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3798*/ GIMT_Encode4(125706), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3833 // |
| 45218 | /* 125652 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45219 | /* 125655 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 45220 | /* 125658 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 45221 | /* 125661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45222 | /* 125665 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45223 | /* 125669 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45224 | /* 125673 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 45225 | /* 125677 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 45226 | /* 125681 */ // MIs[1] Operand 1 |
| 45227 | /* 125681 */ // No operand predicates |
| 45228 | /* 125681 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45229 | /* 125683 */ // (vector_insert:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) |
| 45230 | /* 125683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_16), |
| 45231 | /* 125686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45232 | /* 125688 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 45233 | /* 125690 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 45234 | /* 125692 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 45235 | /* 125695 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45236 | /* 125698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45237 | /* 125704 */ GIR_RootConstrainSelectedInstOperands, |
| 45238 | /* 125705 */ // GIR_Coverage, 3833, |
| 45239 | /* 125705 */ GIR_EraseRootFromParent_Done, |
| 45240 | /* 125706 */ // Label 3798: @125706 |
| 45241 | /* 125706 */ GIM_Reject, |
| 45242 | /* 125707 */ // Label 3794: @125707 |
| 45243 | /* 125707 */ GIM_Reject, |
| 45244 | /* 125708 */ // Label 70: @125708 |
| 45245 | /* 125708 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3799*/ GIMT_Encode4(125763), GIMT_Encode2(GIFBS_HasFPRegs_HasFastVGETLNi32), // Rule ID 1732 // |
| 45246 | /* 125715 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 45247 | /* 125718 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45248 | /* 125721 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 45249 | /* 125724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45250 | /* 125728 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45251 | /* 125732 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 45252 | /* 125736 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 45253 | /* 125740 */ // MIs[1] Operand 1 |
| 45254 | /* 125740 */ // No operand predicates |
| 45255 | /* 125740 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45256 | /* 125742 */ // (extractelt:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane) => (VGETLNi32:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane) |
| 45257 | /* 125742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VGETLNi32), |
| 45258 | /* 125745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[R] |
| 45259 | /* 125747 */ GIR_RootToRootCopy, /*OpIdx*/1, // V |
| 45260 | /* 125749 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 45261 | /* 125752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45262 | /* 125755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45263 | /* 125761 */ GIR_RootConstrainSelectedInstOperands, |
| 45264 | /* 125762 */ // GIR_Coverage, 1732, |
| 45265 | /* 125762 */ GIR_EraseRootFromParent_Done, |
| 45266 | /* 125763 */ // Label 3799: @125763 |
| 45267 | /* 125763 */ GIM_Reject, |
| 45268 | /* 125764 */ // Label 71: @125764 |
| 45269 | /* 125764 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3807*/ GIMT_Encode4(126301), |
| 45270 | /* 125775 */ /*GILLT_s32*//*Label 3800*/ GIMT_Encode4(125823), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45271 | /* 125799 */ /*GILLT_v8s8*//*Label 3801*/ GIMT_Encode4(125899), |
| 45272 | /* 125803 */ /*GILLT_v16s8*//*Label 3802*/ GIMT_Encode4(125936), |
| 45273 | /* 125807 */ /*GILLT_v4s16*//*Label 3803*/ GIMT_Encode4(126033), |
| 45274 | /* 125811 */ /*GILLT_v8s16*//*Label 3804*/ GIMT_Encode4(126070), |
| 45275 | /* 125815 */ /*GILLT_v2s32*//*Label 3805*/ GIMT_Encode4(126167), |
| 45276 | /* 125819 */ /*GILLT_v4s32*//*Label 3806*/ GIMT_Encode4(126204), |
| 45277 | /* 125823 */ // Label 3800: @125823 |
| 45278 | /* 125823 */ GIM_Try, /*On fail goto*//*Label 3808*/ GIMT_Encode4(125898), |
| 45279 | /* 125828 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45280 | /* 125831 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3809*/ GIMT_Encode4(125864), GIMT_Encode2(GIFBS_HasV5T_IsARM), // Rule ID 196 // |
| 45281 | /* 125838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45282 | /* 125842 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45283 | /* 125846 */ // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 45284 | /* 125846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLZ), |
| 45285 | /* 125849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45286 | /* 125851 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45287 | /* 125853 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45288 | /* 125856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45289 | /* 125862 */ GIR_RootConstrainSelectedInstOperands, |
| 45290 | /* 125863 */ // GIR_Coverage, 196, |
| 45291 | /* 125863 */ GIR_EraseRootFromParent_Done, |
| 45292 | /* 125864 */ // Label 3809: @125864 |
| 45293 | /* 125864 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3810*/ GIMT_Encode4(125897), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 533 // |
| 45294 | /* 125871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45295 | /* 125875 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45296 | /* 125879 */ // (ctlz:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2CLZ:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 45297 | /* 125879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLZ), |
| 45298 | /* 125882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45299 | /* 125884 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45300 | /* 125886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45301 | /* 125889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45302 | /* 125895 */ GIR_RootConstrainSelectedInstOperands, |
| 45303 | /* 125896 */ // GIR_Coverage, 533, |
| 45304 | /* 125896 */ GIR_EraseRootFromParent_Done, |
| 45305 | /* 125897 */ // Label 3810: @125897 |
| 45306 | /* 125897 */ GIM_Reject, |
| 45307 | /* 125898 */ // Label 3808: @125898 |
| 45308 | /* 125898 */ GIM_Reject, |
| 45309 | /* 125899 */ // Label 3801: @125899 |
| 45310 | /* 125899 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3811*/ GIMT_Encode4(125935), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1708 // |
| 45311 | /* 125906 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 45312 | /* 125909 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45313 | /* 125913 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45314 | /* 125917 */ // (ctlz:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLZv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 45315 | /* 125917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i8), |
| 45316 | /* 125920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45317 | /* 125922 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45318 | /* 125924 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45319 | /* 125927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45320 | /* 125933 */ GIR_RootConstrainSelectedInstOperands, |
| 45321 | /* 125934 */ // GIR_Coverage, 1708, |
| 45322 | /* 125934 */ GIR_EraseRootFromParent_Done, |
| 45323 | /* 125935 */ // Label 3811: @125935 |
| 45324 | /* 125935 */ GIM_Reject, |
| 45325 | /* 125936 */ // Label 3802: @125936 |
| 45326 | /* 125936 */ GIM_Try, /*On fail goto*//*Label 3812*/ GIMT_Encode4(126032), |
| 45327 | /* 125941 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 45328 | /* 125944 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3813*/ GIMT_Encode4(125977), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1711 // |
| 45329 | /* 125951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45330 | /* 125955 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45331 | /* 125959 */ // (ctlz:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLZv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 45332 | /* 125959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv16i8), |
| 45333 | /* 125962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45334 | /* 125964 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45335 | /* 125966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45336 | /* 125969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45337 | /* 125975 */ GIR_RootConstrainSelectedInstOperands, |
| 45338 | /* 125976 */ // GIR_Coverage, 1711, |
| 45339 | /* 125976 */ GIR_EraseRootFromParent_Done, |
| 45340 | /* 125977 */ // Label 3813: @125977 |
| 45341 | /* 125977 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3814*/ GIMT_Encode4(126031), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4051 // |
| 45342 | /* 125984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45343 | /* 125988 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45344 | /* 125992 */ // (ctlz:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLZs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) |
| 45345 | /* 125992 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45346 | /* 125995 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45347 | /* 125999 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45348 | /* 126004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs8), |
| 45349 | /* 126007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45350 | /* 126009 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45351 | /* 126011 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45352 | /* 126014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45353 | /* 126020 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45354 | /* 126026 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45355 | /* 126029 */ GIR_RootConstrainSelectedInstOperands, |
| 45356 | /* 126030 */ // GIR_Coverage, 4051, |
| 45357 | /* 126030 */ GIR_EraseRootFromParent_Done, |
| 45358 | /* 126031 */ // Label 3814: @126031 |
| 45359 | /* 126031 */ GIM_Reject, |
| 45360 | /* 126032 */ // Label 3812: @126032 |
| 45361 | /* 126032 */ GIM_Reject, |
| 45362 | /* 126033 */ // Label 3803: @126033 |
| 45363 | /* 126033 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3815*/ GIMT_Encode4(126069), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1709 // |
| 45364 | /* 126040 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45365 | /* 126043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45366 | /* 126047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45367 | /* 126051 */ // (ctlz:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLZv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 45368 | /* 126051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i16), |
| 45369 | /* 126054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45370 | /* 126056 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45371 | /* 126058 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45372 | /* 126061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45373 | /* 126067 */ GIR_RootConstrainSelectedInstOperands, |
| 45374 | /* 126068 */ // GIR_Coverage, 1709, |
| 45375 | /* 126068 */ GIR_EraseRootFromParent_Done, |
| 45376 | /* 126069 */ // Label 3815: @126069 |
| 45377 | /* 126069 */ GIM_Reject, |
| 45378 | /* 126070 */ // Label 3804: @126070 |
| 45379 | /* 126070 */ GIM_Try, /*On fail goto*//*Label 3816*/ GIMT_Encode4(126166), |
| 45380 | /* 126075 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45381 | /* 126078 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3817*/ GIMT_Encode4(126111), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1712 // |
| 45382 | /* 126085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45383 | /* 126089 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45384 | /* 126093 */ // (ctlz:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLZv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 45385 | /* 126093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i16), |
| 45386 | /* 126096 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45387 | /* 126098 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45388 | /* 126100 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45389 | /* 126103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45390 | /* 126109 */ GIR_RootConstrainSelectedInstOperands, |
| 45391 | /* 126110 */ // GIR_Coverage, 1712, |
| 45392 | /* 126110 */ GIR_EraseRootFromParent_Done, |
| 45393 | /* 126111 */ // Label 3817: @126111 |
| 45394 | /* 126111 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3818*/ GIMT_Encode4(126165), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4053 // |
| 45395 | /* 126118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45396 | /* 126122 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45397 | /* 126126 */ // (ctlz:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLZs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) |
| 45398 | /* 126126 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45399 | /* 126129 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45400 | /* 126133 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45401 | /* 126138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs16), |
| 45402 | /* 126141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45403 | /* 126143 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45404 | /* 126145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45405 | /* 126148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45406 | /* 126154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45407 | /* 126160 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45408 | /* 126163 */ GIR_RootConstrainSelectedInstOperands, |
| 45409 | /* 126164 */ // GIR_Coverage, 4053, |
| 45410 | /* 126164 */ GIR_EraseRootFromParent_Done, |
| 45411 | /* 126165 */ // Label 3818: @126165 |
| 45412 | /* 126165 */ GIM_Reject, |
| 45413 | /* 126166 */ // Label 3816: @126166 |
| 45414 | /* 126166 */ GIM_Reject, |
| 45415 | /* 126167 */ // Label 3805: @126167 |
| 45416 | /* 126167 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3819*/ GIMT_Encode4(126203), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1710 // |
| 45417 | /* 126174 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45418 | /* 126177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45419 | /* 126181 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45420 | /* 126185 */ // (ctlz:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLZv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 45421 | /* 126185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv2i32), |
| 45422 | /* 126188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45423 | /* 126190 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45424 | /* 126192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45425 | /* 126195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45426 | /* 126201 */ GIR_RootConstrainSelectedInstOperands, |
| 45427 | /* 126202 */ // GIR_Coverage, 1710, |
| 45428 | /* 126202 */ GIR_EraseRootFromParent_Done, |
| 45429 | /* 126203 */ // Label 3819: @126203 |
| 45430 | /* 126203 */ GIM_Reject, |
| 45431 | /* 126204 */ // Label 3806: @126204 |
| 45432 | /* 126204 */ GIM_Try, /*On fail goto*//*Label 3820*/ GIMT_Encode4(126300), |
| 45433 | /* 126209 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45434 | /* 126212 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3821*/ GIMT_Encode4(126245), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1713 // |
| 45435 | /* 126219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45436 | /* 126223 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45437 | /* 126227 */ // (ctlz:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLZv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 45438 | /* 126227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i32), |
| 45439 | /* 126230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45440 | /* 126232 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45441 | /* 126234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45442 | /* 126237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45443 | /* 126243 */ GIR_RootConstrainSelectedInstOperands, |
| 45444 | /* 126244 */ // GIR_Coverage, 1713, |
| 45445 | /* 126244 */ GIR_EraseRootFromParent_Done, |
| 45446 | /* 126245 */ // Label 3821: @126245 |
| 45447 | /* 126245 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3822*/ GIMT_Encode4(126299), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4055 // |
| 45448 | /* 126252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45449 | /* 126256 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45450 | /* 126260 */ // (ctlz:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLZs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) |
| 45451 | /* 126260 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45452 | /* 126263 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45453 | /* 126267 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45454 | /* 126272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs32), |
| 45455 | /* 126275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45456 | /* 126277 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45457 | /* 126279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45458 | /* 126282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45459 | /* 126288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45460 | /* 126294 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45461 | /* 126297 */ GIR_RootConstrainSelectedInstOperands, |
| 45462 | /* 126298 */ // GIR_Coverage, 4055, |
| 45463 | /* 126298 */ GIR_EraseRootFromParent_Done, |
| 45464 | /* 126299 */ // Label 3822: @126299 |
| 45465 | /* 126299 */ GIM_Reject, |
| 45466 | /* 126300 */ // Label 3820: @126300 |
| 45467 | /* 126300 */ GIM_Reject, |
| 45468 | /* 126301 */ // Label 3807: @126301 |
| 45469 | /* 126301 */ GIM_Reject, |
| 45470 | /* 126302 */ // Label 72: @126302 |
| 45471 | /* 126302 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3829*/ GIMT_Encode4(126739), |
| 45472 | /* 126313 */ /*GILLT_v8s8*//*Label 3823*/ GIMT_Encode4(126337), |
| 45473 | /* 126317 */ /*GILLT_v16s8*//*Label 3824*/ GIMT_Encode4(126374), |
| 45474 | /* 126321 */ /*GILLT_v4s16*//*Label 3825*/ GIMT_Encode4(126471), |
| 45475 | /* 126325 */ /*GILLT_v8s16*//*Label 3826*/ GIMT_Encode4(126508), |
| 45476 | /* 126329 */ /*GILLT_v2s32*//*Label 3827*/ GIMT_Encode4(126605), |
| 45477 | /* 126333 */ /*GILLT_v4s32*//*Label 3828*/ GIMT_Encode4(126642), |
| 45478 | /* 126337 */ // Label 3823: @126337 |
| 45479 | /* 126337 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3830*/ GIMT_Encode4(126373), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1702 // |
| 45480 | /* 126344 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 45481 | /* 126347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45482 | /* 126351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45483 | /* 126355 */ // (ctls:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 45484 | /* 126355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i8), |
| 45485 | /* 126358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45486 | /* 126360 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45487 | /* 126362 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45488 | /* 126365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45489 | /* 126371 */ GIR_RootConstrainSelectedInstOperands, |
| 45490 | /* 126372 */ // GIR_Coverage, 1702, |
| 45491 | /* 126372 */ GIR_EraseRootFromParent_Done, |
| 45492 | /* 126373 */ // Label 3830: @126373 |
| 45493 | /* 126373 */ GIM_Reject, |
| 45494 | /* 126374 */ // Label 3824: @126374 |
| 45495 | /* 126374 */ GIM_Try, /*On fail goto*//*Label 3831*/ GIMT_Encode4(126470), |
| 45496 | /* 126379 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 45497 | /* 126382 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3832*/ GIMT_Encode4(126415), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1705 // |
| 45498 | /* 126389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45499 | /* 126393 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45500 | /* 126397 */ // (ctls:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 45501 | /* 126397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv16i8), |
| 45502 | /* 126400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45503 | /* 126402 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45504 | /* 126404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45505 | /* 126407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45506 | /* 126413 */ GIR_RootConstrainSelectedInstOperands, |
| 45507 | /* 126414 */ // GIR_Coverage, 1705, |
| 45508 | /* 126414 */ GIR_EraseRootFromParent_Done, |
| 45509 | /* 126415 */ // Label 3832: @126415 |
| 45510 | /* 126415 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3833*/ GIMT_Encode4(126469), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4045 // |
| 45511 | /* 126422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45512 | /* 126426 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45513 | /* 126430 */ // (ctls:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLSs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) |
| 45514 | /* 126430 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45515 | /* 126433 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45516 | /* 126437 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45517 | /* 126442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs8), |
| 45518 | /* 126445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45519 | /* 126447 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45520 | /* 126449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45521 | /* 126452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45522 | /* 126458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45523 | /* 126464 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45524 | /* 126467 */ GIR_RootConstrainSelectedInstOperands, |
| 45525 | /* 126468 */ // GIR_Coverage, 4045, |
| 45526 | /* 126468 */ GIR_EraseRootFromParent_Done, |
| 45527 | /* 126469 */ // Label 3833: @126469 |
| 45528 | /* 126469 */ GIM_Reject, |
| 45529 | /* 126470 */ // Label 3831: @126470 |
| 45530 | /* 126470 */ GIM_Reject, |
| 45531 | /* 126471 */ // Label 3825: @126471 |
| 45532 | /* 126471 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3834*/ GIMT_Encode4(126507), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1703 // |
| 45533 | /* 126478 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45534 | /* 126481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45535 | /* 126485 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45536 | /* 126489 */ // (ctls:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 45537 | /* 126489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i16), |
| 45538 | /* 126492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45539 | /* 126494 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45540 | /* 126496 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45541 | /* 126499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45542 | /* 126505 */ GIR_RootConstrainSelectedInstOperands, |
| 45543 | /* 126506 */ // GIR_Coverage, 1703, |
| 45544 | /* 126506 */ GIR_EraseRootFromParent_Done, |
| 45545 | /* 126507 */ // Label 3834: @126507 |
| 45546 | /* 126507 */ GIM_Reject, |
| 45547 | /* 126508 */ // Label 3826: @126508 |
| 45548 | /* 126508 */ GIM_Try, /*On fail goto*//*Label 3835*/ GIMT_Encode4(126604), |
| 45549 | /* 126513 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45550 | /* 126516 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3836*/ GIMT_Encode4(126549), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1706 // |
| 45551 | /* 126523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45552 | /* 126527 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45553 | /* 126531 */ // (ctls:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 45554 | /* 126531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i16), |
| 45555 | /* 126534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45556 | /* 126536 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45557 | /* 126538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45558 | /* 126541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45559 | /* 126547 */ GIR_RootConstrainSelectedInstOperands, |
| 45560 | /* 126548 */ // GIR_Coverage, 1706, |
| 45561 | /* 126548 */ GIR_EraseRootFromParent_Done, |
| 45562 | /* 126549 */ // Label 3836: @126549 |
| 45563 | /* 126549 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3837*/ GIMT_Encode4(126603), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4047 // |
| 45564 | /* 126556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45565 | /* 126560 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45566 | /* 126564 */ // (ctls:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLSs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) |
| 45567 | /* 126564 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45568 | /* 126567 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45569 | /* 126571 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45570 | /* 126576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs16), |
| 45571 | /* 126579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45572 | /* 126581 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45573 | /* 126583 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45574 | /* 126586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45575 | /* 126592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45576 | /* 126598 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45577 | /* 126601 */ GIR_RootConstrainSelectedInstOperands, |
| 45578 | /* 126602 */ // GIR_Coverage, 4047, |
| 45579 | /* 126602 */ GIR_EraseRootFromParent_Done, |
| 45580 | /* 126603 */ // Label 3837: @126603 |
| 45581 | /* 126603 */ GIM_Reject, |
| 45582 | /* 126604 */ // Label 3835: @126604 |
| 45583 | /* 126604 */ GIM_Reject, |
| 45584 | /* 126605 */ // Label 3827: @126605 |
| 45585 | /* 126605 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3838*/ GIMT_Encode4(126641), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1704 // |
| 45586 | /* 126612 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45587 | /* 126615 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45588 | /* 126619 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45589 | /* 126623 */ // (ctls:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 45590 | /* 126623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv2i32), |
| 45591 | /* 126626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45592 | /* 126628 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45593 | /* 126630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45594 | /* 126633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45595 | /* 126639 */ GIR_RootConstrainSelectedInstOperands, |
| 45596 | /* 126640 */ // GIR_Coverage, 1704, |
| 45597 | /* 126640 */ GIR_EraseRootFromParent_Done, |
| 45598 | /* 126641 */ // Label 3838: @126641 |
| 45599 | /* 126641 */ GIM_Reject, |
| 45600 | /* 126642 */ // Label 3828: @126642 |
| 45601 | /* 126642 */ GIM_Try, /*On fail goto*//*Label 3839*/ GIMT_Encode4(126738), |
| 45602 | /* 126647 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45603 | /* 126650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3840*/ GIMT_Encode4(126683), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1707 // |
| 45604 | /* 126657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45605 | /* 126661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45606 | /* 126665 */ // (ctls:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 45607 | /* 126665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i32), |
| 45608 | /* 126668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45609 | /* 126670 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45610 | /* 126672 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45611 | /* 126675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45612 | /* 126681 */ GIR_RootConstrainSelectedInstOperands, |
| 45613 | /* 126682 */ // GIR_Coverage, 1707, |
| 45614 | /* 126682 */ GIR_EraseRootFromParent_Done, |
| 45615 | /* 126683 */ // Label 3840: @126683 |
| 45616 | /* 126683 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3841*/ GIMT_Encode4(126737), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4049 // |
| 45617 | /* 126690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45618 | /* 126694 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45619 | /* 126698 */ // (ctls:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLSs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) |
| 45620 | /* 126698 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45621 | /* 126701 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45622 | /* 126705 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45623 | /* 126710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs32), |
| 45624 | /* 126713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45625 | /* 126715 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45626 | /* 126717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45627 | /* 126720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45628 | /* 126726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45629 | /* 126732 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45630 | /* 126735 */ GIR_RootConstrainSelectedInstOperands, |
| 45631 | /* 126736 */ // GIR_Coverage, 4049, |
| 45632 | /* 126736 */ GIR_EraseRootFromParent_Done, |
| 45633 | /* 126737 */ // Label 3841: @126737 |
| 45634 | /* 126737 */ GIM_Reject, |
| 45635 | /* 126738 */ // Label 3839: @126738 |
| 45636 | /* 126738 */ GIM_Reject, |
| 45637 | /* 126739 */ // Label 3829: @126739 |
| 45638 | /* 126739 */ GIM_Reject, |
| 45639 | /* 126740 */ // Label 73: @126740 |
| 45640 | /* 126740 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 3844*/ GIMT_Encode4(126833), |
| 45641 | /* 126751 */ /*GILLT_v8s8*//*Label 3842*/ GIMT_Encode4(126759), |
| 45642 | /* 126755 */ /*GILLT_v16s8*//*Label 3843*/ GIMT_Encode4(126796), |
| 45643 | /* 126759 */ // Label 3842: @126759 |
| 45644 | /* 126759 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3845*/ GIMT_Encode4(126795), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1714 // |
| 45645 | /* 126766 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 45646 | /* 126769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45647 | /* 126773 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45648 | /* 126777 */ // (ctpop:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCNTd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 45649 | /* 126777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTd), |
| 45650 | /* 126780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45651 | /* 126782 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45652 | /* 126784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45653 | /* 126787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45654 | /* 126793 */ GIR_RootConstrainSelectedInstOperands, |
| 45655 | /* 126794 */ // GIR_Coverage, 1714, |
| 45656 | /* 126794 */ GIR_EraseRootFromParent_Done, |
| 45657 | /* 126795 */ // Label 3845: @126795 |
| 45658 | /* 126795 */ GIM_Reject, |
| 45659 | /* 126796 */ // Label 3843: @126796 |
| 45660 | /* 126796 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3846*/ GIMT_Encode4(126832), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1715 // |
| 45661 | /* 126803 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 45662 | /* 126806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45663 | /* 126810 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45664 | /* 126814 */ // (ctpop:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCNTq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 45665 | /* 126814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTq), |
| 45666 | /* 126817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45667 | /* 126819 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45668 | /* 126821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45669 | /* 126824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45670 | /* 126830 */ GIR_RootConstrainSelectedInstOperands, |
| 45671 | /* 126831 */ // GIR_Coverage, 1715, |
| 45672 | /* 126831 */ GIR_EraseRootFromParent_Done, |
| 45673 | /* 126832 */ // Label 3846: @126832 |
| 45674 | /* 126832 */ GIM_Reject, |
| 45675 | /* 126833 */ // Label 3844: @126833 |
| 45676 | /* 126833 */ GIM_Reject, |
| 45677 | /* 126834 */ // Label 74: @126834 |
| 45678 | /* 126834 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3850*/ GIMT_Encode4(127118), |
| 45679 | /* 126845 */ /*GILLT_s32*//*Label 3847*/ GIMT_Encode4(126893), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45680 | /* 126881 */ /*GILLT_v8s16*//*Label 3848*/ GIMT_Encode4(127002), GIMT_Encode4(0), |
| 45681 | /* 126889 */ /*GILLT_v4s32*//*Label 3849*/ GIMT_Encode4(127060), |
| 45682 | /* 126893 */ // Label 3847: @126893 |
| 45683 | /* 126893 */ GIM_Try, /*On fail goto*//*Label 3851*/ GIMT_Encode4(127001), |
| 45684 | /* 126898 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45685 | /* 126901 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3852*/ GIMT_Encode4(126934), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 198 // |
| 45686 | /* 126908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45687 | /* 126912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45688 | /* 126916 */ // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (REV:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 45689 | /* 126916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV), |
| 45690 | /* 126919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45691 | /* 126921 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45692 | /* 126923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45693 | /* 126926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45694 | /* 126932 */ GIR_RootConstrainSelectedInstOperands, |
| 45695 | /* 126933 */ // GIR_Coverage, 198, |
| 45696 | /* 126933 */ GIR_EraseRootFromParent_Done, |
| 45697 | /* 126934 */ // Label 3852: @126934 |
| 45698 | /* 126934 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3853*/ GIMT_Encode4(126967), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 325 // |
| 45699 | /* 126941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 45700 | /* 126945 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 45701 | /* 126949 */ // (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) => (tREV:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 45702 | /* 126949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV), |
| 45703 | /* 126952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45704 | /* 126954 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45705 | /* 126956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45706 | /* 126959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45707 | /* 126965 */ GIR_RootConstrainSelectedInstOperands, |
| 45708 | /* 126966 */ // GIR_Coverage, 325, |
| 45709 | /* 126966 */ GIR_EraseRootFromParent_Done, |
| 45710 | /* 126967 */ // Label 3853: @126967 |
| 45711 | /* 126967 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3854*/ GIMT_Encode4(127000), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 535 // |
| 45712 | /* 126974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45713 | /* 126978 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45714 | /* 126982 */ // (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2REV:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 45715 | /* 126982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV), |
| 45716 | /* 126985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45717 | /* 126987 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45718 | /* 126989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45719 | /* 126992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45720 | /* 126998 */ GIR_RootConstrainSelectedInstOperands, |
| 45721 | /* 126999 */ // GIR_Coverage, 535, |
| 45722 | /* 126999 */ GIR_EraseRootFromParent_Done, |
| 45723 | /* 127000 */ // Label 3854: @127000 |
| 45724 | /* 127000 */ GIM_Reject, |
| 45725 | /* 127001 */ // Label 3851: @127001 |
| 45726 | /* 127001 */ GIM_Reject, |
| 45727 | /* 127002 */ // Label 3848: @127002 |
| 45728 | /* 127002 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3855*/ GIMT_Encode4(127059), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3727 // |
| 45729 | /* 127009 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45730 | /* 127012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45731 | /* 127016 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45732 | /* 127020 */ // (bswap:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) |
| 45733 | /* 127020 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45734 | /* 127023 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45735 | /* 127027 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45736 | /* 127032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 45737 | /* 127035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45738 | /* 127037 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45739 | /* 127039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45740 | /* 127042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45741 | /* 127048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45742 | /* 127054 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45743 | /* 127057 */ GIR_RootConstrainSelectedInstOperands, |
| 45744 | /* 127058 */ // GIR_Coverage, 3727, |
| 45745 | /* 127058 */ GIR_EraseRootFromParent_Done, |
| 45746 | /* 127059 */ // Label 3855: @127059 |
| 45747 | /* 127059 */ GIM_Reject, |
| 45748 | /* 127060 */ // Label 3849: @127060 |
| 45749 | /* 127060 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3856*/ GIMT_Encode4(127117), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3728 // |
| 45750 | /* 127067 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45751 | /* 127070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45752 | /* 127074 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45753 | /* 127078 */ // (bswap:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) |
| 45754 | /* 127078 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45755 | /* 127081 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45756 | /* 127085 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45757 | /* 127090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 45758 | /* 127093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45759 | /* 127095 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45760 | /* 127097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45761 | /* 127100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45762 | /* 127106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45763 | /* 127112 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45764 | /* 127115 */ GIR_RootConstrainSelectedInstOperands, |
| 45765 | /* 127116 */ // GIR_Coverage, 3728, |
| 45766 | /* 127116 */ GIR_EraseRootFromParent_Done, |
| 45767 | /* 127117 */ // Label 3856: @127117 |
| 45768 | /* 127117 */ GIM_Reject, |
| 45769 | /* 127118 */ // Label 3850: @127118 |
| 45770 | /* 127118 */ GIM_Reject, |
| 45771 | /* 127119 */ // Label 75: @127119 |
| 45772 | /* 127119 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3861*/ GIMT_Encode4(127533), |
| 45773 | /* 127130 */ /*GILLT_s32*//*Label 3857*/ GIMT_Encode4(127178), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45774 | /* 127158 */ /*GILLT_v16s8*//*Label 3858*/ GIMT_Encode4(127254), GIMT_Encode4(0), |
| 45775 | /* 127166 */ /*GILLT_v8s16*//*Label 3859*/ GIMT_Encode4(127347), GIMT_Encode4(0), |
| 45776 | /* 127174 */ /*GILLT_v4s32*//*Label 3860*/ GIMT_Encode4(127440), |
| 45777 | /* 127178 */ // Label 3857: @127178 |
| 45778 | /* 127178 */ GIM_Try, /*On fail goto*//*Label 3862*/ GIMT_Encode4(127253), |
| 45779 | /* 127183 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45780 | /* 127186 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3863*/ GIMT_Encode4(127219), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 197 // |
| 45781 | /* 127193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45782 | /* 127197 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45783 | /* 127201 */ // (bitreverse:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (RBIT:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 45784 | /* 127201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RBIT), |
| 45785 | /* 127204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45786 | /* 127206 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45787 | /* 127208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45788 | /* 127211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45789 | /* 127217 */ GIR_RootConstrainSelectedInstOperands, |
| 45790 | /* 127218 */ // GIR_Coverage, 197, |
| 45791 | /* 127218 */ GIR_EraseRootFromParent_Done, |
| 45792 | /* 127219 */ // Label 3863: @127219 |
| 45793 | /* 127219 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3864*/ GIMT_Encode4(127252), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 534 // |
| 45794 | /* 127226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45795 | /* 127230 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45796 | /* 127234 */ // (bitreverse:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2RBIT:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 45797 | /* 127234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RBIT), |
| 45798 | /* 127237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45799 | /* 127239 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45800 | /* 127241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45801 | /* 127244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45802 | /* 127250 */ GIR_RootConstrainSelectedInstOperands, |
| 45803 | /* 127251 */ // GIR_Coverage, 534, |
| 45804 | /* 127251 */ GIR_EraseRootFromParent_Done, |
| 45805 | /* 127252 */ // Label 3864: @127252 |
| 45806 | /* 127252 */ GIM_Reject, |
| 45807 | /* 127253 */ // Label 3862: @127253 |
| 45808 | /* 127253 */ GIM_Reject, |
| 45809 | /* 127254 */ // Label 3858: @127254 |
| 45810 | /* 127254 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3865*/ GIMT_Encode4(127346), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5280 // |
| 45811 | /* 127261 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 45812 | /* 127264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45813 | /* 127268 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45814 | /* 127272 */ // (bitreverse:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1, (t2MOVi:{ *:[i32] } 8:{ *:[i32] })) |
| 45815 | /* 127272 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 45816 | /* 127275 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45817 | /* 127279 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45818 | /* 127284 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45819 | /* 127287 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45820 | /* 127291 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45821 | /* 127296 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/8, |
| 45822 | /* 127299 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45823 | /* 127302 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45824 | /* 127308 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45825 | /* 127314 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45826 | /* 127316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8), |
| 45827 | /* 127319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45828 | /* 127321 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1 |
| 45829 | /* 127323 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45830 | /* 127326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45831 | /* 127329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45832 | /* 127335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45833 | /* 127341 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 45834 | /* 127344 */ GIR_RootConstrainSelectedInstOperands, |
| 45835 | /* 127345 */ // GIR_Coverage, 5280, |
| 45836 | /* 127345 */ GIR_EraseRootFromParent_Done, |
| 45837 | /* 127346 */ // Label 3865: @127346 |
| 45838 | /* 127346 */ GIM_Reject, |
| 45839 | /* 127347 */ // Label 3859: @127347 |
| 45840 | /* 127347 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3866*/ GIMT_Encode4(127439), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5282 // |
| 45841 | /* 127354 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45842 | /* 127357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45843 | /* 127361 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45844 | /* 127365 */ // (bitreverse:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1, (t2MOVi:{ *:[i32] } 16:{ *:[i32] })) |
| 45845 | /* 127365 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 45846 | /* 127368 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45847 | /* 127372 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45848 | /* 127377 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45849 | /* 127380 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45850 | /* 127384 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45851 | /* 127389 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/16, |
| 45852 | /* 127392 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45853 | /* 127395 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45854 | /* 127401 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45855 | /* 127407 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45856 | /* 127409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16), |
| 45857 | /* 127412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45858 | /* 127414 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1 |
| 45859 | /* 127416 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45860 | /* 127419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45861 | /* 127422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45862 | /* 127428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45863 | /* 127434 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 45864 | /* 127437 */ GIR_RootConstrainSelectedInstOperands, |
| 45865 | /* 127438 */ // GIR_Coverage, 5282, |
| 45866 | /* 127438 */ GIR_EraseRootFromParent_Done, |
| 45867 | /* 127439 */ // Label 3866: @127439 |
| 45868 | /* 127439 */ GIM_Reject, |
| 45869 | /* 127440 */ // Label 3860: @127440 |
| 45870 | /* 127440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3867*/ GIMT_Encode4(127532), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5281 // |
| 45871 | /* 127447 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45872 | /* 127450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45873 | /* 127454 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45874 | /* 127458 */ // (bitreverse:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1, (t2MOVi:{ *:[i32] } 32:{ *:[i32] })) |
| 45875 | /* 127458 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 45876 | /* 127461 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45877 | /* 127465 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45878 | /* 127470 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45879 | /* 127473 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45880 | /* 127477 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45881 | /* 127482 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/32, |
| 45882 | /* 127485 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45883 | /* 127488 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45884 | /* 127494 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45885 | /* 127500 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45886 | /* 127502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32), |
| 45887 | /* 127505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45888 | /* 127507 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1 |
| 45889 | /* 127509 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45890 | /* 127512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45891 | /* 127515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45892 | /* 127521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45893 | /* 127527 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 45894 | /* 127530 */ GIR_RootConstrainSelectedInstOperands, |
| 45895 | /* 127531 */ // GIR_Coverage, 5281, |
| 45896 | /* 127531 */ GIR_EraseRootFromParent_Done, |
| 45897 | /* 127532 */ // Label 3867: @127532 |
| 45898 | /* 127532 */ GIM_Reject, |
| 45899 | /* 127533 */ // Label 3861: @127533 |
| 45900 | /* 127533 */ GIM_Reject, |
| 45901 | /* 127534 */ // Label 76: @127534 |
| 45902 | /* 127534 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3875*/ GIMT_Encode4(127899), |
| 45903 | /* 127545 */ /*GILLT_s16*//*Label 3868*/ GIMT_Encode4(127597), |
| 45904 | /* 127549 */ /*GILLT_s32*//*Label 3869*/ GIMT_Encode4(127623), |
| 45905 | /* 127553 */ /*GILLT_s64*//*Label 3870*/ GIMT_Encode4(127649), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45906 | /* 127581 */ /*GILLT_v4s16*//*Label 3871*/ GIMT_Encode4(127675), |
| 45907 | /* 127585 */ /*GILLT_v8s16*//*Label 3872*/ GIMT_Encode4(127701), |
| 45908 | /* 127589 */ /*GILLT_v2s32*//*Label 3873*/ GIMT_Encode4(127787), |
| 45909 | /* 127593 */ /*GILLT_v4s32*//*Label 3874*/ GIMT_Encode4(127813), |
| 45910 | /* 127597 */ // Label 3868: @127597 |
| 45911 | /* 127597 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3876*/ GIMT_Encode4(127622), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 723 // |
| 45912 | /* 127604 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 45913 | /* 127607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45914 | /* 127611 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45915 | /* 127615 */ // (fceil:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTPH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 45916 | /* 127615 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPH), |
| 45917 | /* 127620 */ GIR_RootConstrainSelectedInstOperands, |
| 45918 | /* 127621 */ // GIR_Coverage, 723, |
| 45919 | /* 127621 */ GIR_Done, |
| 45920 | /* 127622 */ // Label 3876: @127622 |
| 45921 | /* 127622 */ GIM_Reject, |
| 45922 | /* 127623 */ // Label 3869: @127623 |
| 45923 | /* 127623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3877*/ GIMT_Encode4(127648), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 725 // |
| 45924 | /* 127630 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45925 | /* 127633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45926 | /* 127637 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45927 | /* 127641 */ // (fceil:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTPS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 45928 | /* 127641 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPS), |
| 45929 | /* 127646 */ GIR_RootConstrainSelectedInstOperands, |
| 45930 | /* 127647 */ // GIR_Coverage, 725, |
| 45931 | /* 127647 */ GIR_Done, |
| 45932 | /* 127648 */ // Label 3877: @127648 |
| 45933 | /* 127648 */ GIM_Reject, |
| 45934 | /* 127649 */ // Label 3870: @127649 |
| 45935 | /* 127649 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3878*/ GIMT_Encode4(127674), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 727 // |
| 45936 | /* 127656 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 45937 | /* 127659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45938 | /* 127663 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45939 | /* 127667 */ // (fceil:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTPD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 45940 | /* 127667 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPD), |
| 45941 | /* 127672 */ GIR_RootConstrainSelectedInstOperands, |
| 45942 | /* 127673 */ // GIR_Coverage, 727, |
| 45943 | /* 127673 */ GIR_Done, |
| 45944 | /* 127674 */ // Label 3878: @127674 |
| 45945 | /* 127674 */ GIM_Reject, |
| 45946 | /* 127675 */ // Label 3871: @127675 |
| 45947 | /* 127675 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3879*/ GIMT_Encode4(127700), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1898 // |
| 45948 | /* 127682 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45949 | /* 127685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45950 | /* 127689 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45951 | /* 127693 */ // (fceil:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTPNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 45952 | /* 127693 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDh), |
| 45953 | /* 127698 */ GIR_RootConstrainSelectedInstOperands, |
| 45954 | /* 127699 */ // GIR_Coverage, 1898, |
| 45955 | /* 127699 */ GIR_Done, |
| 45956 | /* 127700 */ // Label 3879: @127700 |
| 45957 | /* 127700 */ GIM_Reject, |
| 45958 | /* 127701 */ // Label 3872: @127701 |
| 45959 | /* 127701 */ GIM_Try, /*On fail goto*//*Label 3880*/ GIMT_Encode4(127786), |
| 45960 | /* 127706 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45961 | /* 127709 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3881*/ GIMT_Encode4(127731), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1900 // |
| 45962 | /* 127716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45963 | /* 127720 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45964 | /* 127724 */ // (fceil:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTPNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 45965 | /* 127724 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQh), |
| 45966 | /* 127729 */ GIR_RootConstrainSelectedInstOperands, |
| 45967 | /* 127730 */ // GIR_Coverage, 1900, |
| 45968 | /* 127730 */ GIR_Done, |
| 45969 | /* 127731 */ // Label 3881: @127731 |
| 45970 | /* 127731 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3882*/ GIMT_Encode4(127785), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4388 // |
| 45971 | /* 127738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45972 | /* 127742 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45973 | /* 127746 */ // (fceil:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 45974 | /* 127746 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45975 | /* 127749 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45976 | /* 127753 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45977 | /* 127758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P), |
| 45978 | /* 127761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45979 | /* 127763 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45980 | /* 127765 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45981 | /* 127768 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45982 | /* 127774 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45983 | /* 127780 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45984 | /* 127783 */ GIR_RootConstrainSelectedInstOperands, |
| 45985 | /* 127784 */ // GIR_Coverage, 4388, |
| 45986 | /* 127784 */ GIR_EraseRootFromParent_Done, |
| 45987 | /* 127785 */ // Label 3882: @127785 |
| 45988 | /* 127785 */ GIM_Reject, |
| 45989 | /* 127786 */ // Label 3880: @127786 |
| 45990 | /* 127786 */ GIM_Reject, |
| 45991 | /* 127787 */ // Label 3873: @127787 |
| 45992 | /* 127787 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3883*/ GIMT_Encode4(127812), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1894 // |
| 45993 | /* 127794 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45994 | /* 127797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45995 | /* 127801 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45996 | /* 127805 */ // (fceil:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTPNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 45997 | /* 127805 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDf), |
| 45998 | /* 127810 */ GIR_RootConstrainSelectedInstOperands, |
| 45999 | /* 127811 */ // GIR_Coverage, 1894, |
| 46000 | /* 127811 */ GIR_Done, |
| 46001 | /* 127812 */ // Label 3883: @127812 |
| 46002 | /* 127812 */ GIM_Reject, |
| 46003 | /* 127813 */ // Label 3874: @127813 |
| 46004 | /* 127813 */ GIM_Try, /*On fail goto*//*Label 3884*/ GIMT_Encode4(127898), |
| 46005 | /* 127818 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 46006 | /* 127821 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3885*/ GIMT_Encode4(127843), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1896 // |
| 46007 | /* 127828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46008 | /* 127832 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46009 | /* 127836 */ // (fceil:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTPNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 46010 | /* 127836 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQf), |
| 46011 | /* 127841 */ GIR_RootConstrainSelectedInstOperands, |
| 46012 | /* 127842 */ // GIR_Coverage, 1896, |
| 46013 | /* 127842 */ GIR_Done, |
| 46014 | /* 127843 */ // Label 3885: @127843 |
| 46015 | /* 127843 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3886*/ GIMT_Encode4(127897), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4412 // |
| 46016 | /* 127850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46017 | /* 127854 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46018 | /* 127858 */ // (fceil:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 46019 | /* 127858 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46020 | /* 127861 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46021 | /* 127865 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46022 | /* 127870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P), |
| 46023 | /* 127873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46024 | /* 127875 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 46025 | /* 127877 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46026 | /* 127880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46027 | /* 127886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46028 | /* 127892 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46029 | /* 127895 */ GIR_RootConstrainSelectedInstOperands, |
| 46030 | /* 127896 */ // GIR_Coverage, 4412, |
| 46031 | /* 127896 */ GIR_EraseRootFromParent_Done, |
| 46032 | /* 127897 */ // Label 3886: @127897 |
| 46033 | /* 127897 */ GIM_Reject, |
| 46034 | /* 127898 */ // Label 3884: @127898 |
| 46035 | /* 127898 */ GIM_Reject, |
| 46036 | /* 127899 */ // Label 3875: @127899 |
| 46037 | /* 127899 */ GIM_Reject, |
| 46038 | /* 127900 */ // Label 77: @127900 |
| 46039 | /* 127900 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3890*/ GIMT_Encode4(128034), |
| 46040 | /* 127911 */ /*GILLT_s16*//*Label 3887*/ GIMT_Encode4(127923), |
| 46041 | /* 127915 */ /*GILLT_s32*//*Label 3888*/ GIMT_Encode4(127960), |
| 46042 | /* 127919 */ /*GILLT_s64*//*Label 3889*/ GIMT_Encode4(127997), |
| 46043 | /* 127923 */ // Label 3887: @127923 |
| 46044 | /* 127923 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3891*/ GIMT_Encode4(127959), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 739 // |
| 46045 | /* 127930 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46046 | /* 127933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46047 | /* 127937 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46048 | /* 127941 */ // (fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 46049 | /* 127941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH), |
| 46050 | /* 127944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46051 | /* 127946 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46052 | /* 127948 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46053 | /* 127951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46054 | /* 127957 */ GIR_RootConstrainSelectedInstOperands, |
| 46055 | /* 127958 */ // GIR_Coverage, 739, |
| 46056 | /* 127958 */ GIR_EraseRootFromParent_Done, |
| 46057 | /* 127959 */ // Label 3891: @127959 |
| 46058 | /* 127959 */ GIM_Reject, |
| 46059 | /* 127960 */ // Label 3888: @127960 |
| 46060 | /* 127960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3892*/ GIMT_Encode4(127996), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 737 // |
| 46061 | /* 127967 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46062 | /* 127970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46063 | /* 127974 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46064 | /* 127978 */ // (fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 46065 | /* 127978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS), |
| 46066 | /* 127981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46067 | /* 127983 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46068 | /* 127985 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46069 | /* 127988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46070 | /* 127994 */ GIR_RootConstrainSelectedInstOperands, |
| 46071 | /* 127995 */ // GIR_Coverage, 737, |
| 46072 | /* 127995 */ GIR_EraseRootFromParent_Done, |
| 46073 | /* 127996 */ // Label 3892: @127996 |
| 46074 | /* 127996 */ GIM_Reject, |
| 46075 | /* 127997 */ // Label 3889: @127997 |
| 46076 | /* 127997 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3893*/ GIMT_Encode4(128033), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 735 // |
| 46077 | /* 128004 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46078 | /* 128007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46079 | /* 128011 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46080 | /* 128015 */ // (fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 46081 | /* 128015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD), |
| 46082 | /* 128018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46083 | /* 128020 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 46084 | /* 128022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46085 | /* 128025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46086 | /* 128031 */ GIR_RootConstrainSelectedInstOperands, |
| 46087 | /* 128032 */ // GIR_Coverage, 735, |
| 46088 | /* 128032 */ GIR_EraseRootFromParent_Done, |
| 46089 | /* 128033 */ // Label 3893: @128033 |
| 46090 | /* 128033 */ GIM_Reject, |
| 46091 | /* 128034 */ // Label 3890: @128034 |
| 46092 | /* 128034 */ GIM_Reject, |
| 46093 | /* 128035 */ // Label 78: @128035 |
| 46094 | /* 128035 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3901*/ GIMT_Encode4(128400), |
| 46095 | /* 128046 */ /*GILLT_s16*//*Label 3894*/ GIMT_Encode4(128098), |
| 46096 | /* 128050 */ /*GILLT_s32*//*Label 3895*/ GIMT_Encode4(128124), |
| 46097 | /* 128054 */ /*GILLT_s64*//*Label 3896*/ GIMT_Encode4(128150), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46098 | /* 128082 */ /*GILLT_v4s16*//*Label 3897*/ GIMT_Encode4(128176), |
| 46099 | /* 128086 */ /*GILLT_v8s16*//*Label 3898*/ GIMT_Encode4(128202), |
| 46100 | /* 128090 */ /*GILLT_v2s32*//*Label 3899*/ GIMT_Encode4(128288), |
| 46101 | /* 128094 */ /*GILLT_v4s32*//*Label 3900*/ GIMT_Encode4(128314), |
| 46102 | /* 128098 */ // Label 3894: @128098 |
| 46103 | /* 128098 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3902*/ GIMT_Encode4(128123), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 729 // |
| 46104 | /* 128105 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46105 | /* 128108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46106 | /* 128112 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46107 | /* 128116 */ // (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTMH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 46108 | /* 128116 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMH), |
| 46109 | /* 128121 */ GIR_RootConstrainSelectedInstOperands, |
| 46110 | /* 128122 */ // GIR_Coverage, 729, |
| 46111 | /* 128122 */ GIR_Done, |
| 46112 | /* 128123 */ // Label 3902: @128123 |
| 46113 | /* 128123 */ GIM_Reject, |
| 46114 | /* 128124 */ // Label 3895: @128124 |
| 46115 | /* 128124 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3903*/ GIMT_Encode4(128149), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 731 // |
| 46116 | /* 128131 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46117 | /* 128134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46118 | /* 128138 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46119 | /* 128142 */ // (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTMS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 46120 | /* 128142 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMS), |
| 46121 | /* 128147 */ GIR_RootConstrainSelectedInstOperands, |
| 46122 | /* 128148 */ // GIR_Coverage, 731, |
| 46123 | /* 128148 */ GIR_Done, |
| 46124 | /* 128149 */ // Label 3903: @128149 |
| 46125 | /* 128149 */ GIM_Reject, |
| 46126 | /* 128150 */ // Label 3896: @128150 |
| 46127 | /* 128150 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3904*/ GIMT_Encode4(128175), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 733 // |
| 46128 | /* 128157 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46129 | /* 128160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46130 | /* 128164 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46131 | /* 128168 */ // (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTMD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 46132 | /* 128168 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMD), |
| 46133 | /* 128173 */ GIR_RootConstrainSelectedInstOperands, |
| 46134 | /* 128174 */ // GIR_Coverage, 733, |
| 46135 | /* 128174 */ GIR_Done, |
| 46136 | /* 128175 */ // Label 3904: @128175 |
| 46137 | /* 128175 */ GIM_Reject, |
| 46138 | /* 128176 */ // Label 3897: @128176 |
| 46139 | /* 128176 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3905*/ GIMT_Encode4(128201), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1890 // |
| 46140 | /* 128183 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 46141 | /* 128186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46142 | /* 128190 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46143 | /* 128194 */ // (ffloor:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 46144 | /* 128194 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDh), |
| 46145 | /* 128199 */ GIR_RootConstrainSelectedInstOperands, |
| 46146 | /* 128200 */ // GIR_Coverage, 1890, |
| 46147 | /* 128200 */ GIR_Done, |
| 46148 | /* 128201 */ // Label 3905: @128201 |
| 46149 | /* 128201 */ GIM_Reject, |
| 46150 | /* 128202 */ // Label 3898: @128202 |
| 46151 | /* 128202 */ GIM_Try, /*On fail goto*//*Label 3906*/ GIMT_Encode4(128287), |
| 46152 | /* 128207 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 46153 | /* 128210 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3907*/ GIMT_Encode4(128232), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1892 // |
| 46154 | /* 128217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46155 | /* 128221 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46156 | /* 128225 */ // (ffloor:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 46157 | /* 128225 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQh), |
| 46158 | /* 128230 */ GIR_RootConstrainSelectedInstOperands, |
| 46159 | /* 128231 */ // GIR_Coverage, 1892, |
| 46160 | /* 128231 */ GIR_Done, |
| 46161 | /* 128232 */ // Label 3907: @128232 |
| 46162 | /* 128232 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3908*/ GIMT_Encode4(128286), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4384 // |
| 46163 | /* 128239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46164 | /* 128243 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46165 | /* 128247 */ // (ffloor:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 46166 | /* 128247 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46167 | /* 128250 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46168 | /* 128254 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46169 | /* 128259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M), |
| 46170 | /* 128262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46171 | /* 128264 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 46172 | /* 128266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46173 | /* 128269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46174 | /* 128275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46175 | /* 128281 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46176 | /* 128284 */ GIR_RootConstrainSelectedInstOperands, |
| 46177 | /* 128285 */ // GIR_Coverage, 4384, |
| 46178 | /* 128285 */ GIR_EraseRootFromParent_Done, |
| 46179 | /* 128286 */ // Label 3908: @128286 |
| 46180 | /* 128286 */ GIM_Reject, |
| 46181 | /* 128287 */ // Label 3906: @128287 |
| 46182 | /* 128287 */ GIM_Reject, |
| 46183 | /* 128288 */ // Label 3899: @128288 |
| 46184 | /* 128288 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3909*/ GIMT_Encode4(128313), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1886 // |
| 46185 | /* 128295 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 46186 | /* 128298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46187 | /* 128302 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46188 | /* 128306 */ // (ffloor:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 46189 | /* 128306 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDf), |
| 46190 | /* 128311 */ GIR_RootConstrainSelectedInstOperands, |
| 46191 | /* 128312 */ // GIR_Coverage, 1886, |
| 46192 | /* 128312 */ GIR_Done, |
| 46193 | /* 128313 */ // Label 3909: @128313 |
| 46194 | /* 128313 */ GIM_Reject, |
| 46195 | /* 128314 */ // Label 3900: @128314 |
| 46196 | /* 128314 */ GIM_Try, /*On fail goto*//*Label 3910*/ GIMT_Encode4(128399), |
| 46197 | /* 128319 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 46198 | /* 128322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3911*/ GIMT_Encode4(128344), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1888 // |
| 46199 | /* 128329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46200 | /* 128333 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46201 | /* 128337 */ // (ffloor:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 46202 | /* 128337 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQf), |
| 46203 | /* 128342 */ GIR_RootConstrainSelectedInstOperands, |
| 46204 | /* 128343 */ // GIR_Coverage, 1888, |
| 46205 | /* 128343 */ GIR_Done, |
| 46206 | /* 128344 */ // Label 3911: @128344 |
| 46207 | /* 128344 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3912*/ GIMT_Encode4(128398), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4408 // |
| 46208 | /* 128351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46209 | /* 128355 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46210 | /* 128359 */ // (ffloor:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 46211 | /* 128359 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46212 | /* 128362 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46213 | /* 128366 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46214 | /* 128371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M), |
| 46215 | /* 128374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46216 | /* 128376 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 46217 | /* 128378 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46218 | /* 128381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46219 | /* 128387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46220 | /* 128393 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46221 | /* 128396 */ GIR_RootConstrainSelectedInstOperands, |
| 46222 | /* 128397 */ // GIR_Coverage, 4408, |
| 46223 | /* 128397 */ GIR_EraseRootFromParent_Done, |
| 46224 | /* 128398 */ // Label 3912: @128398 |
| 46225 | /* 128398 */ GIM_Reject, |
| 46226 | /* 128399 */ // Label 3910: @128399 |
| 46227 | /* 128399 */ GIM_Reject, |
| 46228 | /* 128400 */ // Label 3901: @128400 |
| 46229 | /* 128400 */ GIM_Reject, |
| 46230 | /* 128401 */ // Label 79: @128401 |
| 46231 | /* 128401 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3920*/ GIMT_Encode4(128799), |
| 46232 | /* 128412 */ /*GILLT_s16*//*Label 3913*/ GIMT_Encode4(128464), |
| 46233 | /* 128416 */ /*GILLT_s32*//*Label 3914*/ GIMT_Encode4(128501), |
| 46234 | /* 128420 */ /*GILLT_s64*//*Label 3915*/ GIMT_Encode4(128538), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46235 | /* 128448 */ /*GILLT_v4s16*//*Label 3916*/ GIMT_Encode4(128575), |
| 46236 | /* 128452 */ /*GILLT_v8s16*//*Label 3917*/ GIMT_Encode4(128601), |
| 46237 | /* 128456 */ /*GILLT_v2s32*//*Label 3918*/ GIMT_Encode4(128687), |
| 46238 | /* 128460 */ /*GILLT_v4s32*//*Label 3919*/ GIMT_Encode4(128713), |
| 46239 | /* 128464 */ // Label 3913: @128464 |
| 46240 | /* 128464 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3921*/ GIMT_Encode4(128500), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 705 // |
| 46241 | /* 128471 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46242 | /* 128474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46243 | /* 128478 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46244 | /* 128482 */ // (frint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTXH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 46245 | /* 128482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXH), |
| 46246 | /* 128485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46247 | /* 128487 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46248 | /* 128489 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46249 | /* 128492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46250 | /* 128498 */ GIR_RootConstrainSelectedInstOperands, |
| 46251 | /* 128499 */ // GIR_Coverage, 705, |
| 46252 | /* 128499 */ GIR_EraseRootFromParent_Done, |
| 46253 | /* 128500 */ // Label 3921: @128500 |
| 46254 | /* 128500 */ GIM_Reject, |
| 46255 | /* 128501 */ // Label 3914: @128501 |
| 46256 | /* 128501 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3922*/ GIMT_Encode4(128537), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 707 // |
| 46257 | /* 128508 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46258 | /* 128511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46259 | /* 128515 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46260 | /* 128519 */ // (frint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTXS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 46261 | /* 128519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXS), |
| 46262 | /* 128522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46263 | /* 128524 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46264 | /* 128526 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46265 | /* 128529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46266 | /* 128535 */ GIR_RootConstrainSelectedInstOperands, |
| 46267 | /* 128536 */ // GIR_Coverage, 707, |
| 46268 | /* 128536 */ GIR_EraseRootFromParent_Done, |
| 46269 | /* 128537 */ // Label 3922: @128537 |
| 46270 | /* 128537 */ GIM_Reject, |
| 46271 | /* 128538 */ // Label 3915: @128538 |
| 46272 | /* 128538 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3923*/ GIMT_Encode4(128574), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 709 // |
| 46273 | /* 128545 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46274 | /* 128548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46275 | /* 128552 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46276 | /* 128556 */ // (frint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTXD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 46277 | /* 128556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXD), |
| 46278 | /* 128559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46279 | /* 128561 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 46280 | /* 128563 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46281 | /* 128566 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46282 | /* 128572 */ GIR_RootConstrainSelectedInstOperands, |
| 46283 | /* 128573 */ // GIR_Coverage, 709, |
| 46284 | /* 128573 */ GIR_EraseRootFromParent_Done, |
| 46285 | /* 128574 */ // Label 3923: @128574 |
| 46286 | /* 128574 */ GIM_Reject, |
| 46287 | /* 128575 */ // Label 3916: @128575 |
| 46288 | /* 128575 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3924*/ GIMT_Encode4(128600), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1866 // |
| 46289 | /* 128582 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 46290 | /* 128585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46291 | /* 128589 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46292 | /* 128593 */ // (frint:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTXNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 46293 | /* 128593 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDh), |
| 46294 | /* 128598 */ GIR_RootConstrainSelectedInstOperands, |
| 46295 | /* 128599 */ // GIR_Coverage, 1866, |
| 46296 | /* 128599 */ GIR_Done, |
| 46297 | /* 128600 */ // Label 3924: @128600 |
| 46298 | /* 128600 */ GIM_Reject, |
| 46299 | /* 128601 */ // Label 3917: @128601 |
| 46300 | /* 128601 */ GIM_Try, /*On fail goto*//*Label 3925*/ GIMT_Encode4(128686), |
| 46301 | /* 128606 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 46302 | /* 128609 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3926*/ GIMT_Encode4(128631), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1868 // |
| 46303 | /* 128616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46304 | /* 128620 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46305 | /* 128624 */ // (frint:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTXNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 46306 | /* 128624 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQh), |
| 46307 | /* 128629 */ GIR_RootConstrainSelectedInstOperands, |
| 46308 | /* 128630 */ // GIR_Coverage, 1868, |
| 46309 | /* 128630 */ GIR_Done, |
| 46310 | /* 128631 */ // Label 3926: @128631 |
| 46311 | /* 128631 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3927*/ GIMT_Encode4(128685), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4372 // |
| 46312 | /* 128638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46313 | /* 128642 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46314 | /* 128646 */ // (frint:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 46315 | /* 128646 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46316 | /* 128649 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46317 | /* 128653 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46318 | /* 128658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X), |
| 46319 | /* 128661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46320 | /* 128663 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 46321 | /* 128665 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46322 | /* 128668 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46323 | /* 128674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46324 | /* 128680 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46325 | /* 128683 */ GIR_RootConstrainSelectedInstOperands, |
| 46326 | /* 128684 */ // GIR_Coverage, 4372, |
| 46327 | /* 128684 */ GIR_EraseRootFromParent_Done, |
| 46328 | /* 128685 */ // Label 3927: @128685 |
| 46329 | /* 128685 */ GIM_Reject, |
| 46330 | /* 128686 */ // Label 3925: @128686 |
| 46331 | /* 128686 */ GIM_Reject, |
| 46332 | /* 128687 */ // Label 3918: @128687 |
| 46333 | /* 128687 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3928*/ GIMT_Encode4(128712), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1862 // |
| 46334 | /* 128694 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 46335 | /* 128697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46336 | /* 128701 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46337 | /* 128705 */ // (frint:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTXNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 46338 | /* 128705 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDf), |
| 46339 | /* 128710 */ GIR_RootConstrainSelectedInstOperands, |
| 46340 | /* 128711 */ // GIR_Coverage, 1862, |
| 46341 | /* 128711 */ GIR_Done, |
| 46342 | /* 128712 */ // Label 3928: @128712 |
| 46343 | /* 128712 */ GIM_Reject, |
| 46344 | /* 128713 */ // Label 3919: @128713 |
| 46345 | /* 128713 */ GIM_Try, /*On fail goto*//*Label 3929*/ GIMT_Encode4(128798), |
| 46346 | /* 128718 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 46347 | /* 128721 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3930*/ GIMT_Encode4(128743), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1864 // |
| 46348 | /* 128728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46349 | /* 128732 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46350 | /* 128736 */ // (frint:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTXNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 46351 | /* 128736 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQf), |
| 46352 | /* 128741 */ GIR_RootConstrainSelectedInstOperands, |
| 46353 | /* 128742 */ // GIR_Coverage, 1864, |
| 46354 | /* 128742 */ GIR_Done, |
| 46355 | /* 128743 */ // Label 3930: @128743 |
| 46356 | /* 128743 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3931*/ GIMT_Encode4(128797), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4396 // |
| 46357 | /* 128750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46358 | /* 128754 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46359 | /* 128758 */ // (frint:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 46360 | /* 128758 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46361 | /* 128761 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46362 | /* 128765 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46363 | /* 128770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X), |
| 46364 | /* 128773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46365 | /* 128775 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 46366 | /* 128777 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46367 | /* 128780 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46368 | /* 128786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46369 | /* 128792 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46370 | /* 128795 */ GIR_RootConstrainSelectedInstOperands, |
| 46371 | /* 128796 */ // GIR_Coverage, 4396, |
| 46372 | /* 128796 */ GIR_EraseRootFromParent_Done, |
| 46373 | /* 128797 */ // Label 3931: @128797 |
| 46374 | /* 128797 */ GIM_Reject, |
| 46375 | /* 128798 */ // Label 3929: @128798 |
| 46376 | /* 128798 */ GIM_Reject, |
| 46377 | /* 128799 */ // Label 3920: @128799 |
| 46378 | /* 128799 */ GIM_Reject, |
| 46379 | /* 128800 */ // Label 80: @128800 |
| 46380 | /* 128800 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3935*/ GIMT_Encode4(128934), |
| 46381 | /* 128811 */ /*GILLT_s16*//*Label 3932*/ GIMT_Encode4(128823), |
| 46382 | /* 128815 */ /*GILLT_s32*//*Label 3933*/ GIMT_Encode4(128860), |
| 46383 | /* 128819 */ /*GILLT_s64*//*Label 3934*/ GIMT_Encode4(128897), |
| 46384 | /* 128823 */ // Label 3932: @128823 |
| 46385 | /* 128823 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3936*/ GIMT_Encode4(128859), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 699 // |
| 46386 | /* 128830 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46387 | /* 128833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46388 | /* 128837 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46389 | /* 128841 */ // (fnearbyint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTRH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 46390 | /* 128841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRH), |
| 46391 | /* 128844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46392 | /* 128846 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46393 | /* 128848 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46394 | /* 128851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46395 | /* 128857 */ GIR_RootConstrainSelectedInstOperands, |
| 46396 | /* 128858 */ // GIR_Coverage, 699, |
| 46397 | /* 128858 */ GIR_EraseRootFromParent_Done, |
| 46398 | /* 128859 */ // Label 3936: @128859 |
| 46399 | /* 128859 */ GIM_Reject, |
| 46400 | /* 128860 */ // Label 3933: @128860 |
| 46401 | /* 128860 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3937*/ GIMT_Encode4(128896), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 701 // |
| 46402 | /* 128867 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46403 | /* 128870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46404 | /* 128874 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46405 | /* 128878 */ // (fnearbyint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 46406 | /* 128878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRS), |
| 46407 | /* 128881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46408 | /* 128883 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46409 | /* 128885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46410 | /* 128888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46411 | /* 128894 */ GIR_RootConstrainSelectedInstOperands, |
| 46412 | /* 128895 */ // GIR_Coverage, 701, |
| 46413 | /* 128895 */ GIR_EraseRootFromParent_Done, |
| 46414 | /* 128896 */ // Label 3937: @128896 |
| 46415 | /* 128896 */ GIM_Reject, |
| 46416 | /* 128897 */ // Label 3934: @128897 |
| 46417 | /* 128897 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3938*/ GIMT_Encode4(128933), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 703 // |
| 46418 | /* 128904 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46419 | /* 128907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46420 | /* 128911 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46421 | /* 128915 */ // (fnearbyint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTRD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 46422 | /* 128915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRD), |
| 46423 | /* 128918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46424 | /* 128920 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 46425 | /* 128922 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46426 | /* 128925 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46427 | /* 128931 */ GIR_RootConstrainSelectedInstOperands, |
| 46428 | /* 128932 */ // GIR_Coverage, 703, |
| 46429 | /* 128932 */ GIR_EraseRootFromParent_Done, |
| 46430 | /* 128933 */ // Label 3938: @128933 |
| 46431 | /* 128933 */ GIM_Reject, |
| 46432 | /* 128934 */ // Label 3935: @128934 |
| 46433 | /* 128934 */ GIM_Reject, |
| 46434 | /* 128935 */ // Label 81: @128935 |
| 46435 | /* 128935 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3942*/ GIMT_Encode4(129096), |
| 46436 | /* 128946 */ /*GILLT_s16*//*Label 3939*/ GIMT_Encode4(128958), |
| 46437 | /* 128950 */ /*GILLT_s32*//*Label 3940*/ GIMT_Encode4(129004), |
| 46438 | /* 128954 */ /*GILLT_s64*//*Label 3941*/ GIMT_Encode4(129050), |
| 46439 | /* 128958 */ // Label 3939: @128958 |
| 46440 | /* 128958 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3943*/ GIMT_Encode4(129003), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 620 // |
| 46441 | /* 128965 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46442 | /* 128968 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 46443 | /* 128971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46444 | /* 128975 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46445 | /* 128979 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46446 | /* 128983 */ // (strict_fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46447 | /* 128983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH), |
| 46448 | /* 128986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46449 | /* 128988 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46450 | /* 128990 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46451 | /* 128992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46452 | /* 128995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46453 | /* 129001 */ GIR_RootConstrainSelectedInstOperands, |
| 46454 | /* 129002 */ // GIR_Coverage, 620, |
| 46455 | /* 129002 */ GIR_EraseRootFromParent_Done, |
| 46456 | /* 129003 */ // Label 3943: @129003 |
| 46457 | /* 129003 */ GIM_Reject, |
| 46458 | /* 129004 */ // Label 3940: @129004 |
| 46459 | /* 129004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3944*/ GIMT_Encode4(129049), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 618 // |
| 46460 | /* 129011 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46461 | /* 129014 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 46462 | /* 129017 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46463 | /* 129021 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46464 | /* 129025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46465 | /* 129029 */ // (strict_fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46466 | /* 129029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS), |
| 46467 | /* 129032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46468 | /* 129034 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46469 | /* 129036 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46470 | /* 129038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46471 | /* 129041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46472 | /* 129047 */ GIR_RootConstrainSelectedInstOperands, |
| 46473 | /* 129048 */ // GIR_Coverage, 618, |
| 46474 | /* 129048 */ GIR_EraseRootFromParent_Done, |
| 46475 | /* 129049 */ // Label 3944: @129049 |
| 46476 | /* 129049 */ GIM_Reject, |
| 46477 | /* 129050 */ // Label 3941: @129050 |
| 46478 | /* 129050 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3945*/ GIMT_Encode4(129095), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 616 // |
| 46479 | /* 129057 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46480 | /* 129060 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 46481 | /* 129063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46482 | /* 129067 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46483 | /* 129071 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46484 | /* 129075 */ // (strict_fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46485 | /* 129075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD), |
| 46486 | /* 129078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46487 | /* 129080 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 46488 | /* 129082 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 46489 | /* 129084 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46490 | /* 129087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46491 | /* 129093 */ GIR_RootConstrainSelectedInstOperands, |
| 46492 | /* 129094 */ // GIR_Coverage, 616, |
| 46493 | /* 129094 */ GIR_EraseRootFromParent_Done, |
| 46494 | /* 129095 */ // Label 3945: @129095 |
| 46495 | /* 129095 */ GIM_Reject, |
| 46496 | /* 129096 */ // Label 3942: @129096 |
| 46497 | /* 129096 */ GIM_Reject, |
| 46498 | /* 129097 */ // Label 82: @129097 |
| 46499 | /* 129097 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3949*/ GIMT_Encode4(129258), |
| 46500 | /* 129108 */ /*GILLT_s16*//*Label 3946*/ GIMT_Encode4(129120), |
| 46501 | /* 129112 */ /*GILLT_s32*//*Label 3947*/ GIMT_Encode4(129166), |
| 46502 | /* 129116 */ /*GILLT_s64*//*Label 3948*/ GIMT_Encode4(129212), |
| 46503 | /* 129120 */ // Label 3946: @129120 |
| 46504 | /* 129120 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3950*/ GIMT_Encode4(129165), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 626 // |
| 46505 | /* 129127 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46506 | /* 129130 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 46507 | /* 129133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46508 | /* 129137 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46509 | /* 129141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46510 | /* 129145 */ // (strict_fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46511 | /* 129145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH), |
| 46512 | /* 129148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46513 | /* 129150 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46514 | /* 129152 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46515 | /* 129154 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46516 | /* 129157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46517 | /* 129163 */ GIR_RootConstrainSelectedInstOperands, |
| 46518 | /* 129164 */ // GIR_Coverage, 626, |
| 46519 | /* 129164 */ GIR_EraseRootFromParent_Done, |
| 46520 | /* 129165 */ // Label 3950: @129165 |
| 46521 | /* 129165 */ GIM_Reject, |
| 46522 | /* 129166 */ // Label 3947: @129166 |
| 46523 | /* 129166 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3951*/ GIMT_Encode4(129211), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 624 // |
| 46524 | /* 129173 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46525 | /* 129176 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 46526 | /* 129179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46527 | /* 129183 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46528 | /* 129187 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46529 | /* 129191 */ // (strict_fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46530 | /* 129191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS), |
| 46531 | /* 129194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46532 | /* 129196 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46533 | /* 129198 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46534 | /* 129200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46535 | /* 129203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46536 | /* 129209 */ GIR_RootConstrainSelectedInstOperands, |
| 46537 | /* 129210 */ // GIR_Coverage, 624, |
| 46538 | /* 129210 */ GIR_EraseRootFromParent_Done, |
| 46539 | /* 129211 */ // Label 3951: @129211 |
| 46540 | /* 129211 */ GIM_Reject, |
| 46541 | /* 129212 */ // Label 3948: @129212 |
| 46542 | /* 129212 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3952*/ GIMT_Encode4(129257), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 622 // |
| 46543 | /* 129219 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46544 | /* 129222 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 46545 | /* 129225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46546 | /* 129229 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46547 | /* 129233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46548 | /* 129237 */ // (strict_fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46549 | /* 129237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD), |
| 46550 | /* 129240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46551 | /* 129242 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 46552 | /* 129244 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 46553 | /* 129246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46554 | /* 129249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46555 | /* 129255 */ GIR_RootConstrainSelectedInstOperands, |
| 46556 | /* 129256 */ // GIR_Coverage, 622, |
| 46557 | /* 129256 */ GIR_EraseRootFromParent_Done, |
| 46558 | /* 129257 */ // Label 3952: @129257 |
| 46559 | /* 129257 */ GIM_Reject, |
| 46560 | /* 129258 */ // Label 3949: @129258 |
| 46561 | /* 129258 */ GIM_Reject, |
| 46562 | /* 129259 */ // Label 83: @129259 |
| 46563 | /* 129259 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3956*/ GIMT_Encode4(129420), |
| 46564 | /* 129270 */ /*GILLT_s16*//*Label 3953*/ GIMT_Encode4(129282), |
| 46565 | /* 129274 */ /*GILLT_s32*//*Label 3954*/ GIMT_Encode4(129328), |
| 46566 | /* 129278 */ /*GILLT_s64*//*Label 3955*/ GIMT_Encode4(129374), |
| 46567 | /* 129282 */ // Label 3953: @129282 |
| 46568 | /* 129282 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3957*/ GIMT_Encode4(129327), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 638 // |
| 46569 | /* 129289 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46570 | /* 129292 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 46571 | /* 129295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46572 | /* 129299 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46573 | /* 129303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46574 | /* 129307 */ // (strict_fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46575 | /* 129307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH), |
| 46576 | /* 129310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46577 | /* 129312 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46578 | /* 129314 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46579 | /* 129316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46580 | /* 129319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46581 | /* 129325 */ GIR_RootConstrainSelectedInstOperands, |
| 46582 | /* 129326 */ // GIR_Coverage, 638, |
| 46583 | /* 129326 */ GIR_EraseRootFromParent_Done, |
| 46584 | /* 129327 */ // Label 3957: @129327 |
| 46585 | /* 129327 */ GIM_Reject, |
| 46586 | /* 129328 */ // Label 3954: @129328 |
| 46587 | /* 129328 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3958*/ GIMT_Encode4(129373), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 636 // |
| 46588 | /* 129335 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46589 | /* 129338 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 46590 | /* 129341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46591 | /* 129345 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46592 | /* 129349 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46593 | /* 129353 */ // (strict_fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46594 | /* 129353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS), |
| 46595 | /* 129356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46596 | /* 129358 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46597 | /* 129360 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46598 | /* 129362 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46599 | /* 129365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46600 | /* 129371 */ GIR_RootConstrainSelectedInstOperands, |
| 46601 | /* 129372 */ // GIR_Coverage, 636, |
| 46602 | /* 129372 */ GIR_EraseRootFromParent_Done, |
| 46603 | /* 129373 */ // Label 3958: @129373 |
| 46604 | /* 129373 */ GIM_Reject, |
| 46605 | /* 129374 */ // Label 3955: @129374 |
| 46606 | /* 129374 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3959*/ GIMT_Encode4(129419), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 634 // |
| 46607 | /* 129381 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46608 | /* 129384 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 46609 | /* 129387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46610 | /* 129391 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46611 | /* 129395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46612 | /* 129399 */ // (strict_fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46613 | /* 129399 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD), |
| 46614 | /* 129402 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46615 | /* 129404 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 46616 | /* 129406 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 46617 | /* 129408 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46618 | /* 129411 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46619 | /* 129417 */ GIR_RootConstrainSelectedInstOperands, |
| 46620 | /* 129418 */ // GIR_Coverage, 634, |
| 46621 | /* 129418 */ GIR_EraseRootFromParent_Done, |
| 46622 | /* 129419 */ // Label 3959: @129419 |
| 46623 | /* 129419 */ GIM_Reject, |
| 46624 | /* 129420 */ // Label 3956: @129420 |
| 46625 | /* 129420 */ GIM_Reject, |
| 46626 | /* 129421 */ // Label 84: @129421 |
| 46627 | /* 129421 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3963*/ GIMT_Encode4(129582), |
| 46628 | /* 129432 */ /*GILLT_s16*//*Label 3960*/ GIMT_Encode4(129444), |
| 46629 | /* 129436 */ /*GILLT_s32*//*Label 3961*/ GIMT_Encode4(129490), |
| 46630 | /* 129440 */ /*GILLT_s64*//*Label 3962*/ GIMT_Encode4(129536), |
| 46631 | /* 129444 */ // Label 3960: @129444 |
| 46632 | /* 129444 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3964*/ GIMT_Encode4(129489), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 632 // |
| 46633 | /* 129451 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46634 | /* 129454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 46635 | /* 129457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46636 | /* 129461 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46637 | /* 129465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46638 | /* 129469 */ // (strict_fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46639 | /* 129469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH), |
| 46640 | /* 129472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46641 | /* 129474 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46642 | /* 129476 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46643 | /* 129478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46644 | /* 129481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46645 | /* 129487 */ GIR_RootConstrainSelectedInstOperands, |
| 46646 | /* 129488 */ // GIR_Coverage, 632, |
| 46647 | /* 129488 */ GIR_EraseRootFromParent_Done, |
| 46648 | /* 129489 */ // Label 3964: @129489 |
| 46649 | /* 129489 */ GIM_Reject, |
| 46650 | /* 129490 */ // Label 3961: @129490 |
| 46651 | /* 129490 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3965*/ GIMT_Encode4(129535), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 630 // |
| 46652 | /* 129497 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46653 | /* 129500 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 46654 | /* 129503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46655 | /* 129507 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46656 | /* 129511 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46657 | /* 129515 */ // (strict_fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46658 | /* 129515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS), |
| 46659 | /* 129518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46660 | /* 129520 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46661 | /* 129522 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46662 | /* 129524 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46663 | /* 129527 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46664 | /* 129533 */ GIR_RootConstrainSelectedInstOperands, |
| 46665 | /* 129534 */ // GIR_Coverage, 630, |
| 46666 | /* 129534 */ GIR_EraseRootFromParent_Done, |
| 46667 | /* 129535 */ // Label 3965: @129535 |
| 46668 | /* 129535 */ GIM_Reject, |
| 46669 | /* 129536 */ // Label 3962: @129536 |
| 46670 | /* 129536 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3966*/ GIMT_Encode4(129581), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 628 // |
| 46671 | /* 129543 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46672 | /* 129546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 46673 | /* 129549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46674 | /* 129553 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46675 | /* 129557 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46676 | /* 129561 */ // (strict_fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46677 | /* 129561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD), |
| 46678 | /* 129564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46679 | /* 129566 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 46680 | /* 129568 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 46681 | /* 129570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46682 | /* 129573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46683 | /* 129579 */ GIR_RootConstrainSelectedInstOperands, |
| 46684 | /* 129580 */ // GIR_Coverage, 628, |
| 46685 | /* 129580 */ GIR_EraseRootFromParent_Done, |
| 46686 | /* 129581 */ // Label 3966: @129581 |
| 46687 | /* 129581 */ GIM_Reject, |
| 46688 | /* 129582 */ // Label 3963: @129582 |
| 46689 | /* 129582 */ GIM_Reject, |
| 46690 | /* 129583 */ // Label 85: @129583 |
| 46691 | /* 129583 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3970*/ GIMT_Encode4(130749), |
| 46692 | /* 129594 */ /*GILLT_s16*//*Label 3967*/ GIMT_Encode4(129606), |
| 46693 | /* 129598 */ /*GILLT_s32*//*Label 3968*/ GIMT_Encode4(129987), |
| 46694 | /* 129602 */ /*GILLT_s64*//*Label 3969*/ GIMT_Encode4(130368), |
| 46695 | /* 129606 */ // Label 3967: @129606 |
| 46696 | /* 129606 */ GIM_Try, /*On fail goto*//*Label 3971*/ GIMT_Encode4(129986), |
| 46697 | /* 129611 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46698 | /* 129614 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 46699 | /* 129617 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 46700 | /* 129620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46701 | /* 129624 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3972*/ GIMT_Encode4(129697), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2774 // |
| 46702 | /* 129631 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46703 | /* 129635 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46704 | /* 129639 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 46705 | /* 129643 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46706 | /* 129648 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46707 | /* 129652 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 46708 | /* 129656 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46709 | /* 129660 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 46710 | /* 129664 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46711 | /* 129669 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 46712 | /* 129671 */ // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46713 | /* 129671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 46714 | /* 129674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46715 | /* 129676 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 46716 | /* 129680 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46717 | /* 129684 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46718 | /* 129686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46719 | /* 129689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46720 | /* 129695 */ GIR_RootConstrainSelectedInstOperands, |
| 46721 | /* 129696 */ // GIR_Coverage, 2774, |
| 46722 | /* 129696 */ GIR_EraseRootFromParent_Done, |
| 46723 | /* 129697 */ // Label 3972: @129697 |
| 46724 | /* 129697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3973*/ GIMT_Encode4(129770), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6339 // |
| 46725 | /* 129704 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46726 | /* 129708 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 46727 | /* 129712 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46728 | /* 129716 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 46729 | /* 129720 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46730 | /* 129725 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 46731 | /* 129729 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46732 | /* 129733 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 46733 | /* 129737 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46734 | /* 129742 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 46735 | /* 129744 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46736 | /* 129744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 46737 | /* 129747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46738 | /* 129749 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 46739 | /* 129753 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46740 | /* 129757 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46741 | /* 129759 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46742 | /* 129762 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46743 | /* 129768 */ GIR_RootConstrainSelectedInstOperands, |
| 46744 | /* 129769 */ // GIR_Coverage, 6339, |
| 46745 | /* 129769 */ GIR_EraseRootFromParent_Done, |
| 46746 | /* 129770 */ // Label 3973: @129770 |
| 46747 | /* 129770 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3974*/ GIMT_Encode4(129828), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2754 // |
| 46748 | /* 129777 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46749 | /* 129781 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46750 | /* 129785 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 46751 | /* 129789 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46752 | /* 129794 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46753 | /* 129798 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46754 | /* 129802 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46755 | /* 129804 */ // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46756 | /* 129804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 46757 | /* 129807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46758 | /* 129809 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 46759 | /* 129811 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46760 | /* 129815 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46761 | /* 129817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46762 | /* 129820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46763 | /* 129826 */ GIR_RootConstrainSelectedInstOperands, |
| 46764 | /* 129827 */ // GIR_Coverage, 2754, |
| 46765 | /* 129827 */ GIR_EraseRootFromParent_Done, |
| 46766 | /* 129828 */ // Label 3974: @129828 |
| 46767 | /* 129828 */ GIM_Try, /*On fail goto*//*Label 3975*/ GIMT_Encode4(129985), |
| 46768 | /* 129833 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46769 | /* 129837 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3976*/ GIMT_Encode4(129891), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6333 // |
| 46770 | /* 129844 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 46771 | /* 129848 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46772 | /* 129852 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 46773 | /* 129856 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46774 | /* 129861 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46775 | /* 129865 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46776 | /* 129867 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46777 | /* 129867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 46778 | /* 129870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46779 | /* 129872 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 46780 | /* 129874 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46781 | /* 129878 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46782 | /* 129880 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46783 | /* 129883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46784 | /* 129889 */ GIR_RootConstrainSelectedInstOperands, |
| 46785 | /* 129890 */ // GIR_Coverage, 6333, |
| 46786 | /* 129890 */ GIR_EraseRootFromParent_Done, |
| 46787 | /* 129891 */ // Label 3976: @129891 |
| 46788 | /* 129891 */ GIM_Try, /*On fail goto*//*Label 3977*/ GIMT_Encode4(129984), |
| 46789 | /* 129896 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46790 | /* 129900 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3978*/ GIMT_Encode4(129950), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2788 // |
| 46791 | /* 129907 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 46792 | /* 129911 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46793 | /* 129915 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 46794 | /* 129919 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46795 | /* 129924 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46796 | /* 129926 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46797 | /* 129926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 46798 | /* 129929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46799 | /* 129931 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 46800 | /* 129935 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46801 | /* 129937 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46802 | /* 129939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46803 | /* 129942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46804 | /* 129948 */ GIR_RootConstrainSelectedInstOperands, |
| 46805 | /* 129949 */ // GIR_Coverage, 2788, |
| 46806 | /* 129949 */ GIR_EraseRootFromParent_Done, |
| 46807 | /* 129950 */ // Label 3978: @129950 |
| 46808 | /* 129950 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3979*/ GIMT_Encode4(129983), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2736 // |
| 46809 | /* 129957 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46810 | /* 129961 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46811 | /* 129961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH), |
| 46812 | /* 129964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46813 | /* 129966 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 46814 | /* 129968 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46815 | /* 129970 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46816 | /* 129972 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46817 | /* 129975 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46818 | /* 129981 */ GIR_RootConstrainSelectedInstOperands, |
| 46819 | /* 129982 */ // GIR_Coverage, 2736, |
| 46820 | /* 129982 */ GIR_EraseRootFromParent_Done, |
| 46821 | /* 129983 */ // Label 3979: @129983 |
| 46822 | /* 129983 */ GIM_Reject, |
| 46823 | /* 129984 */ // Label 3977: @129984 |
| 46824 | /* 129984 */ GIM_Reject, |
| 46825 | /* 129985 */ // Label 3975: @129985 |
| 46826 | /* 129985 */ GIM_Reject, |
| 46827 | /* 129986 */ // Label 3971: @129986 |
| 46828 | /* 129986 */ GIM_Reject, |
| 46829 | /* 129987 */ // Label 3968: @129987 |
| 46830 | /* 129987 */ GIM_Try, /*On fail goto*//*Label 3980*/ GIMT_Encode4(130367), |
| 46831 | /* 129992 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46832 | /* 129995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 46833 | /* 129998 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 46834 | /* 130001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46835 | /* 130005 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3981*/ GIMT_Encode4(130078), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2772 // |
| 46836 | /* 130012 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46837 | /* 130016 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46838 | /* 130020 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 46839 | /* 130024 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46840 | /* 130029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46841 | /* 130033 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 46842 | /* 130037 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46843 | /* 130041 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 46844 | /* 130045 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46845 | /* 130050 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 46846 | /* 130052 */ // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46847 | /* 130052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 46848 | /* 130055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46849 | /* 130057 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 46850 | /* 130061 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46851 | /* 130065 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46852 | /* 130067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46853 | /* 130070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46854 | /* 130076 */ GIR_RootConstrainSelectedInstOperands, |
| 46855 | /* 130077 */ // GIR_Coverage, 2772, |
| 46856 | /* 130077 */ GIR_EraseRootFromParent_Done, |
| 46857 | /* 130078 */ // Label 3981: @130078 |
| 46858 | /* 130078 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3982*/ GIMT_Encode4(130151), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6337 // |
| 46859 | /* 130085 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46860 | /* 130089 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 46861 | /* 130093 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46862 | /* 130097 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 46863 | /* 130101 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46864 | /* 130106 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 46865 | /* 130110 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46866 | /* 130114 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 46867 | /* 130118 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46868 | /* 130123 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 46869 | /* 130125 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46870 | /* 130125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 46871 | /* 130128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46872 | /* 130130 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 46873 | /* 130134 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46874 | /* 130138 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46875 | /* 130140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46876 | /* 130143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46877 | /* 130149 */ GIR_RootConstrainSelectedInstOperands, |
| 46878 | /* 130150 */ // GIR_Coverage, 6337, |
| 46879 | /* 130150 */ GIR_EraseRootFromParent_Done, |
| 46880 | /* 130151 */ // Label 3982: @130151 |
| 46881 | /* 130151 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3983*/ GIMT_Encode4(130209), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2752 // |
| 46882 | /* 130158 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46883 | /* 130162 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46884 | /* 130166 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 46885 | /* 130170 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46886 | /* 130175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46887 | /* 130179 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46888 | /* 130183 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46889 | /* 130185 */ // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46890 | /* 130185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 46891 | /* 130188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46892 | /* 130190 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 46893 | /* 130192 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46894 | /* 130196 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46895 | /* 130198 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46896 | /* 130201 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46897 | /* 130207 */ GIR_RootConstrainSelectedInstOperands, |
| 46898 | /* 130208 */ // GIR_Coverage, 2752, |
| 46899 | /* 130208 */ GIR_EraseRootFromParent_Done, |
| 46900 | /* 130209 */ // Label 3983: @130209 |
| 46901 | /* 130209 */ GIM_Try, /*On fail goto*//*Label 3984*/ GIMT_Encode4(130366), |
| 46902 | /* 130214 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46903 | /* 130218 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3985*/ GIMT_Encode4(130272), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6331 // |
| 46904 | /* 130225 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 46905 | /* 130229 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46906 | /* 130233 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 46907 | /* 130237 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46908 | /* 130242 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46909 | /* 130246 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46910 | /* 130248 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46911 | /* 130248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 46912 | /* 130251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46913 | /* 130253 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 46914 | /* 130255 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46915 | /* 130259 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46916 | /* 130261 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46917 | /* 130264 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46918 | /* 130270 */ GIR_RootConstrainSelectedInstOperands, |
| 46919 | /* 130271 */ // GIR_Coverage, 6331, |
| 46920 | /* 130271 */ GIR_EraseRootFromParent_Done, |
| 46921 | /* 130272 */ // Label 3985: @130272 |
| 46922 | /* 130272 */ GIM_Try, /*On fail goto*//*Label 3986*/ GIMT_Encode4(130365), |
| 46923 | /* 130277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46924 | /* 130281 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3987*/ GIMT_Encode4(130331), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2786 // |
| 46925 | /* 130288 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 46926 | /* 130292 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46927 | /* 130296 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 46928 | /* 130300 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46929 | /* 130305 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46930 | /* 130307 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46931 | /* 130307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 46932 | /* 130310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46933 | /* 130312 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 46934 | /* 130316 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46935 | /* 130318 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46936 | /* 130320 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46937 | /* 130323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46938 | /* 130329 */ GIR_RootConstrainSelectedInstOperands, |
| 46939 | /* 130330 */ // GIR_Coverage, 2786, |
| 46940 | /* 130330 */ GIR_EraseRootFromParent_Done, |
| 46941 | /* 130331 */ // Label 3987: @130331 |
| 46942 | /* 130331 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3988*/ GIMT_Encode4(130364), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2734 // |
| 46943 | /* 130338 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46944 | /* 130342 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46945 | /* 130342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS), |
| 46946 | /* 130345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46947 | /* 130347 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 46948 | /* 130349 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46949 | /* 130351 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46950 | /* 130353 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46951 | /* 130356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46952 | /* 130362 */ GIR_RootConstrainSelectedInstOperands, |
| 46953 | /* 130363 */ // GIR_Coverage, 2734, |
| 46954 | /* 130363 */ GIR_EraseRootFromParent_Done, |
| 46955 | /* 130364 */ // Label 3988: @130364 |
| 46956 | /* 130364 */ GIM_Reject, |
| 46957 | /* 130365 */ // Label 3986: @130365 |
| 46958 | /* 130365 */ GIM_Reject, |
| 46959 | /* 130366 */ // Label 3984: @130366 |
| 46960 | /* 130366 */ GIM_Reject, |
| 46961 | /* 130367 */ // Label 3980: @130367 |
| 46962 | /* 130367 */ GIM_Reject, |
| 46963 | /* 130368 */ // Label 3969: @130368 |
| 46964 | /* 130368 */ GIM_Try, /*On fail goto*//*Label 3989*/ GIMT_Encode4(130748), |
| 46965 | /* 130373 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46966 | /* 130376 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 46967 | /* 130379 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 46968 | /* 130382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46969 | /* 130386 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3990*/ GIMT_Encode4(130459), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2770 // |
| 46970 | /* 130393 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46971 | /* 130397 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46972 | /* 130401 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 46973 | /* 130405 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46974 | /* 130410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46975 | /* 130414 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 46976 | /* 130418 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46977 | /* 130422 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 46978 | /* 130426 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46979 | /* 130431 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 46980 | /* 130433 */ // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46981 | /* 130433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 46982 | /* 130436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46983 | /* 130438 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 46984 | /* 130442 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 46985 | /* 130446 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 46986 | /* 130448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46987 | /* 130451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46988 | /* 130457 */ GIR_RootConstrainSelectedInstOperands, |
| 46989 | /* 130458 */ // GIR_Coverage, 2770, |
| 46990 | /* 130458 */ GIR_EraseRootFromParent_Done, |
| 46991 | /* 130459 */ // Label 3990: @130459 |
| 46992 | /* 130459 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3991*/ GIMT_Encode4(130532), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6335 // |
| 46993 | /* 130466 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46994 | /* 130470 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 46995 | /* 130474 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46996 | /* 130478 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 46997 | /* 130482 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46998 | /* 130487 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 46999 | /* 130491 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 47000 | /* 130495 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 47001 | /* 130499 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47002 | /* 130504 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 47003 | /* 130506 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 47004 | /* 130506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 47005 | /* 130509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 47006 | /* 130511 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 47007 | /* 130515 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 47008 | /* 130519 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 47009 | /* 130521 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47010 | /* 130524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47011 | /* 130530 */ GIR_RootConstrainSelectedInstOperands, |
| 47012 | /* 130531 */ // GIR_Coverage, 6335, |
| 47013 | /* 130531 */ GIR_EraseRootFromParent_Done, |
| 47014 | /* 130532 */ // Label 3991: @130532 |
| 47015 | /* 130532 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3992*/ GIMT_Encode4(130590), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2750 // |
| 47016 | /* 130539 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 47017 | /* 130543 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 47018 | /* 130547 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 47019 | /* 130551 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47020 | /* 130556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47021 | /* 130560 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47022 | /* 130564 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47023 | /* 130566 */ // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 47024 | /* 130566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 47025 | /* 130569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 47026 | /* 130571 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 47027 | /* 130573 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 47028 | /* 130577 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 47029 | /* 130579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47030 | /* 130582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47031 | /* 130588 */ GIR_RootConstrainSelectedInstOperands, |
| 47032 | /* 130589 */ // GIR_Coverage, 2750, |
| 47033 | /* 130589 */ GIR_EraseRootFromParent_Done, |
| 47034 | /* 130590 */ // Label 3992: @130590 |
| 47035 | /* 130590 */ GIM_Try, /*On fail goto*//*Label 3993*/ GIMT_Encode4(130747), |
| 47036 | /* 130595 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47037 | /* 130599 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3994*/ GIMT_Encode4(130653), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6329 // |
| 47038 | /* 130606 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 47039 | /* 130610 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 47040 | /* 130614 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 47041 | /* 130618 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47042 | /* 130623 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47043 | /* 130627 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47044 | /* 130629 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 47045 | /* 130629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 47046 | /* 130632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 47047 | /* 130634 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 47048 | /* 130636 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 47049 | /* 130640 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 47050 | /* 130642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47051 | /* 130645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47052 | /* 130651 */ GIR_RootConstrainSelectedInstOperands, |
| 47053 | /* 130652 */ // GIR_Coverage, 6329, |
| 47054 | /* 130652 */ GIR_EraseRootFromParent_Done, |
| 47055 | /* 130653 */ // Label 3994: @130653 |
| 47056 | /* 130653 */ GIM_Try, /*On fail goto*//*Label 3995*/ GIMT_Encode4(130746), |
| 47057 | /* 130658 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47058 | /* 130662 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3996*/ GIMT_Encode4(130712), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2784 // |
| 47059 | /* 130669 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 47060 | /* 130673 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 47061 | /* 130677 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 47062 | /* 130681 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47063 | /* 130686 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47064 | /* 130688 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 47065 | /* 130688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 47066 | /* 130691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 47067 | /* 130693 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin |
| 47068 | /* 130697 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 47069 | /* 130699 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 47070 | /* 130701 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47071 | /* 130704 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47072 | /* 130710 */ GIR_RootConstrainSelectedInstOperands, |
| 47073 | /* 130711 */ // GIR_Coverage, 2784, |
| 47074 | /* 130711 */ GIR_EraseRootFromParent_Done, |
| 47075 | /* 130712 */ // Label 3996: @130712 |
| 47076 | /* 130712 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3997*/ GIMT_Encode4(130745), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2732 // |
| 47077 | /* 130719 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47078 | /* 130723 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 47079 | /* 130723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD), |
| 47080 | /* 130726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 47081 | /* 130728 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 47082 | /* 130730 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 47083 | /* 130732 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 47084 | /* 130734 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47085 | /* 130737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47086 | /* 130743 */ GIR_RootConstrainSelectedInstOperands, |
| 47087 | /* 130744 */ // GIR_Coverage, 2732, |
| 47088 | /* 130744 */ GIR_EraseRootFromParent_Done, |
| 47089 | /* 130745 */ // Label 3997: @130745 |
| 47090 | /* 130745 */ GIM_Reject, |
| 47091 | /* 130746 */ // Label 3995: @130746 |
| 47092 | /* 130746 */ GIM_Reject, |
| 47093 | /* 130747 */ // Label 3993: @130747 |
| 47094 | /* 130747 */ GIM_Reject, |
| 47095 | /* 130748 */ // Label 3989: @130748 |
| 47096 | /* 130748 */ GIM_Reject, |
| 47097 | /* 130749 */ // Label 3970: @130749 |
| 47098 | /* 130749 */ GIM_Reject, |
| 47099 | /* 130750 */ // Label 86: @130750 |
| 47100 | /* 130750 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 4001*/ GIMT_Encode4(130884), |
| 47101 | /* 130761 */ /*GILLT_s16*//*Label 3998*/ GIMT_Encode4(130773), |
| 47102 | /* 130765 */ /*GILLT_s32*//*Label 3999*/ GIMT_Encode4(130810), |
| 47103 | /* 130769 */ /*GILLT_s64*//*Label 4000*/ GIMT_Encode4(130847), |
| 47104 | /* 130773 */ // Label 3998: @130773 |
| 47105 | /* 130773 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4002*/ GIMT_Encode4(130809), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 738 // |
| 47106 | /* 130780 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 47107 | /* 130783 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 47108 | /* 130787 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 47109 | /* 130791 */ // (strict_fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 47110 | /* 130791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH), |
| 47111 | /* 130794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 47112 | /* 130796 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 47113 | /* 130798 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47114 | /* 130801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47115 | /* 130807 */ GIR_RootConstrainSelectedInstOperands, |
| 47116 | /* 130808 */ // GIR_Coverage, 738, |
| 47117 | /* 130808 */ GIR_EraseRootFromParent_Done, |
| 47118 | /* 130809 */ // Label 4002: @130809 |
| 47119 | /* 130809 */ GIM_Reject, |
| 47120 | /* 130810 */ // Label 3999: @130810 |
| 47121 | /* 130810 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4003*/ GIMT_Encode4(130846), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 736 // |
| 47122 | /* 130817 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 47123 | /* 130820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 47124 | /* 130824 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 47125 | /* 130828 */ // (strict_fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 47126 | /* 130828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS), |
| 47127 | /* 130831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 47128 | /* 130833 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 47129 | /* 130835 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47130 | /* 130838 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47131 | /* 130844 */ GIR_RootConstrainSelectedInstOperands, |
| 47132 | /* 130845 */ // GIR_Coverage, 736, |
| 47133 | /* 130845 */ GIR_EraseRootFromParent_Done, |
| 47134 | /* 130846 */ // Label 4003: @130846 |
| 47135 | /* 130846 */ GIM_Reject, |
| 47136 | /* 130847 */ // Label 4000: @130847 |
| 47137 | /* 130847 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4004*/ GIMT_Encode4(130883), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 734 // |
| 47138 | /* 130854 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 47139 | /* 130857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47140 | /* 130861 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 47141 | /* 130865 */ // (strict_fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 47142 | /* 130865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD), |
| 47143 | /* 130868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 47144 | /* 130870 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 47145 | /* 130872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 47146 | /* 130875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47147 | /* 130881 */ GIR_RootConstrainSelectedInstOperands, |
| 47148 | /* 130882 */ // GIR_Coverage, 734, |
| 47149 | /* 130882 */ GIR_EraseRootFromParent_Done, |
| 47150 | /* 130883 */ // Label 4004: @130883 |
| 47151 | /* 130883 */ GIM_Reject, |
| 47152 | /* 130884 */ // Label 4001: @130884 |
| 47153 | /* 130884 */ GIM_Reject, |
| 47154 | /* 130885 */ // Label 87: @130885 |
| 47155 | /* 130885 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4005*/ GIMT_Encode4(130899), GIMT_Encode2(GIFBS_IsARM), // Rule ID 12 // |
| 47156 | /* 130892 */ // (trap) => (TRAP) |
| 47157 | /* 130892 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::TRAP), |
| 47158 | /* 130897 */ GIR_RootConstrainSelectedInstOperands, |
| 47159 | /* 130898 */ // GIR_Coverage, 12, |
| 47160 | /* 130898 */ GIR_Done, |
| 47161 | /* 130899 */ // Label 4005: @130899 |
| 47162 | /* 130899 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4006*/ GIMT_Encode4(130913), GIMT_Encode2(GIFBS_IsThumb), // Rule ID 284 // |
| 47163 | /* 130906 */ // (trap) => (tTRAP) |
| 47164 | /* 130906 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tTRAP), |
| 47165 | /* 130911 */ GIR_RootConstrainSelectedInstOperands, |
| 47166 | /* 130912 */ // GIR_Coverage, 284, |
| 47167 | /* 130912 */ GIR_Done, |
| 47168 | /* 130913 */ // Label 4006: @130913 |
| 47169 | /* 130913 */ GIM_Reject, |
| 47170 | /* 130914 */ // Label 88: @130914 |
| 47171 | /* 130914 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4007*/ GIMT_Encode4(130929), GIMT_Encode2(GIFBS_HasV5T_IsARM), // Rule ID 2026 // |
| 47172 | /* 130921 */ // (debugtrap) => (BKPT 0:{ *:[i32] }) |
| 47173 | /* 130921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BKPT), |
| 47174 | /* 130924 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47175 | /* 130927 */ GIR_RootConstrainSelectedInstOperands, |
| 47176 | /* 130928 */ // GIR_Coverage, 2026, |
| 47177 | /* 130928 */ GIR_EraseRootFromParent_Done, |
| 47178 | /* 130929 */ // Label 4007: @130929 |
| 47179 | /* 130929 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4008*/ GIMT_Encode4(130955), GIMT_Encode2(GIFBS_IsARM_NoV5T), // Rule ID 2027 // |
| 47180 | /* 130936 */ // (debugtrap) => (UDF 254:{ *:[i32] }) |
| 47181 | /* 130936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF), |
| 47182 | /* 130939 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254), |
| 47183 | /* 130949 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47184 | /* 130953 */ GIR_RootConstrainSelectedInstOperands, |
| 47185 | /* 130954 */ // GIR_Coverage, 2027, |
| 47186 | /* 130954 */ GIR_EraseRootFromParent_Done, |
| 47187 | /* 130955 */ // Label 4008: @130955 |
| 47188 | /* 130955 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4009*/ GIMT_Encode4(130970), GIMT_Encode2(GIFBS_HasV5T_IsThumb), // Rule ID 2219 // |
| 47189 | /* 130962 */ // (debugtrap) => (tBKPT 0:{ *:[i32] }) |
| 47190 | /* 130962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBKPT), |
| 47191 | /* 130965 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47192 | /* 130968 */ GIR_RootConstrainSelectedInstOperands, |
| 47193 | /* 130969 */ // GIR_Coverage, 2219, |
| 47194 | /* 130969 */ GIR_EraseRootFromParent_Done, |
| 47195 | /* 130970 */ // Label 4009: @130970 |
| 47196 | /* 130970 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4010*/ GIMT_Encode4(130996), GIMT_Encode2(GIFBS_IsThumb_NoV5T), // Rule ID 2220 // |
| 47197 | /* 130977 */ // (debugtrap) => (tUDF 254:{ *:[i32] }) |
| 47198 | /* 130977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF), |
| 47199 | /* 130980 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254), |
| 47200 | /* 130990 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47201 | /* 130994 */ GIR_RootConstrainSelectedInstOperands, |
| 47202 | /* 130995 */ // GIR_Coverage, 2220, |
| 47203 | /* 130995 */ GIR_EraseRootFromParent_Done, |
| 47204 | /* 130996 */ // Label 4010: @130996 |
| 47205 | /* 130996 */ GIM_Reject, |
| 47206 | /* 130997 */ // Label 89: @130997 |
| 47207 | /* 130997 */ GIM_Try, /*On fail goto*//*Label 4011*/ GIMT_Encode4(131370), |
| 47208 | /* 131002 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 47209 | /* 131005 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4015*/ GIMT_Encode4(131369), |
| 47210 | /* 131016 */ /*GILLT_v16s8*//*Label 4012*/ GIMT_Encode4(131036), GIMT_Encode4(0), |
| 47211 | /* 131024 */ /*GILLT_v8s16*//*Label 4013*/ GIMT_Encode4(131147), GIMT_Encode4(0), |
| 47212 | /* 131032 */ /*GILLT_v4s32*//*Label 4014*/ GIMT_Encode4(131258), |
| 47213 | /* 131036 */ // Label 4012: @131036 |
| 47214 | /* 131036 */ GIM_Try, /*On fail goto*//*Label 4016*/ GIMT_Encode4(131146), |
| 47215 | /* 131041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 47216 | /* 131045 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4017*/ GIMT_Encode4(131110), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3636 // |
| 47217 | /* 131052 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 47218 | /* 131056 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 47219 | /* 131060 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 47220 | /* 131064 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 47221 | /* 131068 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47222 | /* 131073 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47223 | /* 131078 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47224 | /* 131080 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)) => (MVE_VMLADAVu8:{ *:[i32] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 47225 | /* 131080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8), |
| 47226 | /* 131083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47227 | /* 131085 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 47228 | /* 131089 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 47229 | /* 131093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47230 | /* 131096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47231 | /* 131102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47232 | /* 131108 */ GIR_RootConstrainSelectedInstOperands, |
| 47233 | /* 131109 */ // GIR_Coverage, 3636, |
| 47234 | /* 131109 */ GIR_EraseRootFromParent_Done, |
| 47235 | /* 131110 */ // Label 4017: @131110 |
| 47236 | /* 131110 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4018*/ GIMT_Encode4(131145), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3440 // |
| 47237 | /* 131117 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47238 | /* 131121 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec) => (MVE_VADDVu8no_acc:{ *:[i32] } ?:{ *:[v16i8] }:$vec) |
| 47239 | /* 131121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8no_acc), |
| 47240 | /* 131124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 47241 | /* 131126 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec |
| 47242 | /* 131128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47243 | /* 131131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47244 | /* 131137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47245 | /* 131143 */ GIR_RootConstrainSelectedInstOperands, |
| 47246 | /* 131144 */ // GIR_Coverage, 3440, |
| 47247 | /* 131144 */ GIR_EraseRootFromParent_Done, |
| 47248 | /* 131145 */ // Label 4018: @131145 |
| 47249 | /* 131145 */ GIM_Reject, |
| 47250 | /* 131146 */ // Label 4016: @131146 |
| 47251 | /* 131146 */ GIM_Reject, |
| 47252 | /* 131147 */ // Label 4013: @131147 |
| 47253 | /* 131147 */ GIM_Try, /*On fail goto*//*Label 4019*/ GIMT_Encode4(131257), |
| 47254 | /* 131152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 47255 | /* 131156 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4020*/ GIMT_Encode4(131221), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3633 // |
| 47256 | /* 131163 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 47257 | /* 131167 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 47258 | /* 131171 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 47259 | /* 131175 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 47260 | /* 131179 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47261 | /* 131184 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47262 | /* 131189 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47263 | /* 131191 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)) => (MVE_VMLADAVu16:{ *:[i32] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 47264 | /* 131191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16), |
| 47265 | /* 131194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47266 | /* 131196 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 47267 | /* 131200 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 47268 | /* 131204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47269 | /* 131207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47270 | /* 131213 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47271 | /* 131219 */ GIR_RootConstrainSelectedInstOperands, |
| 47272 | /* 131220 */ // GIR_Coverage, 3633, |
| 47273 | /* 131220 */ GIR_EraseRootFromParent_Done, |
| 47274 | /* 131221 */ // Label 4020: @131221 |
| 47275 | /* 131221 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4021*/ GIMT_Encode4(131256), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3468 // |
| 47276 | /* 131228 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47277 | /* 131232 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec) => (MVE_VADDVu16no_acc:{ *:[i32] } ?:{ *:[v8i16] }:$vec) |
| 47278 | /* 131232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16no_acc), |
| 47279 | /* 131235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 47280 | /* 131237 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec |
| 47281 | /* 131239 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47282 | /* 131242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47283 | /* 131248 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47284 | /* 131254 */ GIR_RootConstrainSelectedInstOperands, |
| 47285 | /* 131255 */ // GIR_Coverage, 3468, |
| 47286 | /* 131255 */ GIR_EraseRootFromParent_Done, |
| 47287 | /* 131256 */ // Label 4021: @131256 |
| 47288 | /* 131256 */ GIM_Reject, |
| 47289 | /* 131257 */ // Label 4019: @131257 |
| 47290 | /* 131257 */ GIM_Reject, |
| 47291 | /* 131258 */ // Label 4014: @131258 |
| 47292 | /* 131258 */ GIM_Try, /*On fail goto*//*Label 4022*/ GIMT_Encode4(131368), |
| 47293 | /* 131263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 47294 | /* 131267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4023*/ GIMT_Encode4(131332), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3632 // |
| 47295 | /* 131274 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 47296 | /* 131278 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 47297 | /* 131282 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 47298 | /* 131286 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 47299 | /* 131290 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47300 | /* 131295 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47301 | /* 131300 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47302 | /* 131302 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)) => (MVE_VMLADAVu32:{ *:[i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 47303 | /* 131302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32), |
| 47304 | /* 131305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47305 | /* 131307 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 47306 | /* 131311 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 47307 | /* 131315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47308 | /* 131318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47309 | /* 131324 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47310 | /* 131330 */ GIR_RootConstrainSelectedInstOperands, |
| 47311 | /* 131331 */ // GIR_Coverage, 3632, |
| 47312 | /* 131331 */ GIR_EraseRootFromParent_Done, |
| 47313 | /* 131332 */ // Label 4023: @131332 |
| 47314 | /* 131332 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4024*/ GIMT_Encode4(131367), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3478 // |
| 47315 | /* 131339 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47316 | /* 131343 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec) => (MVE_VADDVu32no_acc:{ *:[i32] } ?:{ *:[v4i32] }:$vec) |
| 47317 | /* 131343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32no_acc), |
| 47318 | /* 131346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 47319 | /* 131348 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec |
| 47320 | /* 131350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47321 | /* 131353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47322 | /* 131359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47323 | /* 131365 */ GIR_RootConstrainSelectedInstOperands, |
| 47324 | /* 131366 */ // GIR_Coverage, 3478, |
| 47325 | /* 131366 */ GIR_EraseRootFromParent_Done, |
| 47326 | /* 131367 */ // Label 4024: @131367 |
| 47327 | /* 131367 */ GIM_Reject, |
| 47328 | /* 131368 */ // Label 4022: @131368 |
| 47329 | /* 131368 */ GIM_Reject, |
| 47330 | /* 131369 */ // Label 4015: @131369 |
| 47331 | /* 131369 */ GIM_Reject, |
| 47332 | /* 131370 */ // Label 4011: @131370 |
| 47333 | /* 131370 */ GIM_Reject, |
| 47334 | /* 131371 */ // Label 90: @131371 |
| 47335 | /* 131371 */ GIM_Try, /*On fail goto*//*Label 4025*/ GIMT_Encode4(131635), |
| 47336 | /* 131376 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 47337 | /* 131379 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4029*/ GIMT_Encode4(131634), |
| 47338 | /* 131390 */ /*GILLT_v16s8*//*Label 4026*/ GIMT_Encode4(131410), GIMT_Encode4(0), |
| 47339 | /* 131398 */ /*GILLT_v8s16*//*Label 4027*/ GIMT_Encode4(131485), GIMT_Encode4(0), |
| 47340 | /* 131406 */ /*GILLT_v4s32*//*Label 4028*/ GIMT_Encode4(131552), |
| 47341 | /* 131410 */ // Label 4026: @131410 |
| 47342 | /* 131410 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4030*/ GIMT_Encode4(131484), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3536 // |
| 47343 | /* 131417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47344 | /* 131421 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47345 | /* 131425 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVs8:{ *:[i32] } (t2MVNi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 47346 | /* 131425 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47347 | /* 131428 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 47348 | /* 131432 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47349 | /* 131437 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127, |
| 47350 | /* 131440 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47351 | /* 131443 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47352 | /* 131449 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47353 | /* 131455 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47354 | /* 131457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8), |
| 47355 | /* 131460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47356 | /* 131462 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47357 | /* 131465 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47358 | /* 131467 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47359 | /* 131470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47360 | /* 131476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47361 | /* 131482 */ GIR_RootConstrainSelectedInstOperands, |
| 47362 | /* 131483 */ // GIR_Coverage, 3536, |
| 47363 | /* 131483 */ GIR_EraseRootFromParent_Done, |
| 47364 | /* 131484 */ // Label 4030: @131484 |
| 47365 | /* 131484 */ GIM_Reject, |
| 47366 | /* 131485 */ // Label 4027: @131485 |
| 47367 | /* 131485 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4031*/ GIMT_Encode4(131551), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3537 // |
| 47368 | /* 131492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47369 | /* 131496 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47370 | /* 131500 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVs16:{ *:[i32] } (t2MOVi32imm:{ *:[i32] } -32768:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 47371 | /* 131500 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47372 | /* 131503 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm), |
| 47373 | /* 131507 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47374 | /* 131512 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744073709518848u), |
| 47375 | /* 131522 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47376 | /* 131524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16), |
| 47377 | /* 131527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47378 | /* 131529 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47379 | /* 131532 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47380 | /* 131534 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47381 | /* 131537 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47382 | /* 131543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47383 | /* 131549 */ GIR_RootConstrainSelectedInstOperands, |
| 47384 | /* 131550 */ // GIR_Coverage, 3537, |
| 47385 | /* 131550 */ GIR_EraseRootFromParent_Done, |
| 47386 | /* 131551 */ // Label 4031: @131551 |
| 47387 | /* 131551 */ GIM_Reject, |
| 47388 | /* 131552 */ // Label 4028: @131552 |
| 47389 | /* 131552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4032*/ GIMT_Encode4(131633), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3538 // |
| 47390 | /* 131559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47391 | /* 131563 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47392 | /* 131567 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVs32:{ *:[i32] } (t2MOVi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 47393 | /* 131567 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47394 | /* 131570 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 47395 | /* 131574 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47396 | /* 131579 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744071562067968u), |
| 47397 | /* 131589 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47398 | /* 131592 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47399 | /* 131598 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47400 | /* 131604 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47401 | /* 131606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32), |
| 47402 | /* 131609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47403 | /* 131611 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47404 | /* 131614 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47405 | /* 131616 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47406 | /* 131619 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47407 | /* 131625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47408 | /* 131631 */ GIR_RootConstrainSelectedInstOperands, |
| 47409 | /* 131632 */ // GIR_Coverage, 3538, |
| 47410 | /* 131632 */ GIR_EraseRootFromParent_Done, |
| 47411 | /* 131633 */ // Label 4032: @131633 |
| 47412 | /* 131633 */ GIM_Reject, |
| 47413 | /* 131634 */ // Label 4029: @131634 |
| 47414 | /* 131634 */ GIM_Reject, |
| 47415 | /* 131635 */ // Label 4025: @131635 |
| 47416 | /* 131635 */ GIM_Reject, |
| 47417 | /* 131636 */ // Label 91: @131636 |
| 47418 | /* 131636 */ GIM_Try, /*On fail goto*//*Label 4033*/ GIMT_Encode4(131909), |
| 47419 | /* 131641 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 47420 | /* 131644 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4037*/ GIMT_Encode4(131908), |
| 47421 | /* 131655 */ /*GILLT_v16s8*//*Label 4034*/ GIMT_Encode4(131675), GIMT_Encode4(0), |
| 47422 | /* 131663 */ /*GILLT_v8s16*//*Label 4035*/ GIMT_Encode4(131750), GIMT_Encode4(0), |
| 47423 | /* 131671 */ /*GILLT_v4s32*//*Label 4036*/ GIMT_Encode4(131826), |
| 47424 | /* 131675 */ // Label 4034: @131675 |
| 47425 | /* 131675 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4038*/ GIMT_Encode4(131749), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3542 // |
| 47426 | /* 131682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47427 | /* 131686 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47428 | /* 131690 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVs8:{ *:[i32] } (t2MOVi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 47429 | /* 131690 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47430 | /* 131693 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 47431 | /* 131697 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47432 | /* 131702 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127, |
| 47433 | /* 131705 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47434 | /* 131708 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47435 | /* 131714 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47436 | /* 131720 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47437 | /* 131722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8), |
| 47438 | /* 131725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47439 | /* 131727 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47440 | /* 131730 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47441 | /* 131732 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47442 | /* 131735 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47443 | /* 131741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47444 | /* 131747 */ GIR_RootConstrainSelectedInstOperands, |
| 47445 | /* 131748 */ // GIR_Coverage, 3542, |
| 47446 | /* 131748 */ GIR_EraseRootFromParent_Done, |
| 47447 | /* 131749 */ // Label 4038: @131749 |
| 47448 | /* 131749 */ GIM_Reject, |
| 47449 | /* 131750 */ // Label 4035: @131750 |
| 47450 | /* 131750 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4039*/ GIMT_Encode4(131825), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3543 // |
| 47451 | /* 131757 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47452 | /* 131761 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47453 | /* 131765 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVs16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 32767:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 47454 | /* 131765 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47455 | /* 131768 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16), |
| 47456 | /* 131772 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47457 | /* 131777 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767), |
| 47458 | /* 131787 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47459 | /* 131790 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47460 | /* 131796 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47461 | /* 131798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16), |
| 47462 | /* 131801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47463 | /* 131803 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47464 | /* 131806 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47465 | /* 131808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47466 | /* 131811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47467 | /* 131817 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47468 | /* 131823 */ GIR_RootConstrainSelectedInstOperands, |
| 47469 | /* 131824 */ // GIR_Coverage, 3543, |
| 47470 | /* 131824 */ GIR_EraseRootFromParent_Done, |
| 47471 | /* 131825 */ // Label 4039: @131825 |
| 47472 | /* 131825 */ GIM_Reject, |
| 47473 | /* 131826 */ // Label 4036: @131826 |
| 47474 | /* 131826 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4040*/ GIMT_Encode4(131907), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3544 // |
| 47475 | /* 131833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47476 | /* 131837 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47477 | /* 131841 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVs32:{ *:[i32] } (t2MVNi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 47478 | /* 131841 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47479 | /* 131844 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 47480 | /* 131848 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47481 | /* 131853 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744071562067968u), |
| 47482 | /* 131863 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47483 | /* 131866 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47484 | /* 131872 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47485 | /* 131878 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47486 | /* 131880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32), |
| 47487 | /* 131883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47488 | /* 131885 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47489 | /* 131888 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47490 | /* 131890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47491 | /* 131893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47492 | /* 131899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47493 | /* 131905 */ GIR_RootConstrainSelectedInstOperands, |
| 47494 | /* 131906 */ // GIR_Coverage, 3544, |
| 47495 | /* 131906 */ GIR_EraseRootFromParent_Done, |
| 47496 | /* 131907 */ // Label 4040: @131907 |
| 47497 | /* 131907 */ GIM_Reject, |
| 47498 | /* 131908 */ // Label 4037: @131908 |
| 47499 | /* 131908 */ GIM_Reject, |
| 47500 | /* 131909 */ // Label 4033: @131909 |
| 47501 | /* 131909 */ GIM_Reject, |
| 47502 | /* 131910 */ // Label 92: @131910 |
| 47503 | /* 131910 */ GIM_Try, /*On fail goto*//*Label 4041*/ GIMT_Encode4(132175), |
| 47504 | /* 131915 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 47505 | /* 131918 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4045*/ GIMT_Encode4(132174), |
| 47506 | /* 131929 */ /*GILLT_v16s8*//*Label 4042*/ GIMT_Encode4(131949), GIMT_Encode4(0), |
| 47507 | /* 131937 */ /*GILLT_v8s16*//*Label 4043*/ GIMT_Encode4(132024), GIMT_Encode4(0), |
| 47508 | /* 131945 */ /*GILLT_v4s32*//*Label 4044*/ GIMT_Encode4(132099), |
| 47509 | /* 131949 */ // Label 4042: @131949 |
| 47510 | /* 131949 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4046*/ GIMT_Encode4(132023), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3539 // |
| 47511 | /* 131956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47512 | /* 131960 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47513 | /* 131964 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 47514 | /* 131964 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47515 | /* 131967 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 47516 | /* 131971 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47517 | /* 131976 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 47518 | /* 131979 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47519 | /* 131982 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47520 | /* 131988 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47521 | /* 131994 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47522 | /* 131996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8), |
| 47523 | /* 131999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47524 | /* 132001 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47525 | /* 132004 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47526 | /* 132006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47527 | /* 132009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47528 | /* 132015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47529 | /* 132021 */ GIR_RootConstrainSelectedInstOperands, |
| 47530 | /* 132022 */ // GIR_Coverage, 3539, |
| 47531 | /* 132022 */ GIR_EraseRootFromParent_Done, |
| 47532 | /* 132023 */ // Label 4046: @132023 |
| 47533 | /* 132023 */ GIM_Reject, |
| 47534 | /* 132024 */ // Label 4043: @132024 |
| 47535 | /* 132024 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4047*/ GIMT_Encode4(132098), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3540 // |
| 47536 | /* 132031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47537 | /* 132035 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47538 | /* 132039 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVu16:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 47539 | /* 132039 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47540 | /* 132042 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 47541 | /* 132046 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47542 | /* 132051 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 47543 | /* 132054 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47544 | /* 132057 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47545 | /* 132063 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47546 | /* 132069 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47547 | /* 132071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16), |
| 47548 | /* 132074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47549 | /* 132076 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47550 | /* 132079 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47551 | /* 132081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47552 | /* 132084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47553 | /* 132090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47554 | /* 132096 */ GIR_RootConstrainSelectedInstOperands, |
| 47555 | /* 132097 */ // GIR_Coverage, 3540, |
| 47556 | /* 132097 */ GIR_EraseRootFromParent_Done, |
| 47557 | /* 132098 */ // Label 4047: @132098 |
| 47558 | /* 132098 */ GIM_Reject, |
| 47559 | /* 132099 */ // Label 4044: @132099 |
| 47560 | /* 132099 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4048*/ GIMT_Encode4(132173), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3541 // |
| 47561 | /* 132106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47562 | /* 132110 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47563 | /* 132114 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 47564 | /* 132114 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47565 | /* 132117 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 47566 | /* 132121 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47567 | /* 132126 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 47568 | /* 132129 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47569 | /* 132132 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47570 | /* 132138 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47571 | /* 132144 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47572 | /* 132146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32), |
| 47573 | /* 132149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47574 | /* 132151 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47575 | /* 132154 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47576 | /* 132156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47577 | /* 132159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47578 | /* 132165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47579 | /* 132171 */ GIR_RootConstrainSelectedInstOperands, |
| 47580 | /* 132172 */ // GIR_Coverage, 3541, |
| 47581 | /* 132172 */ GIR_EraseRootFromParent_Done, |
| 47582 | /* 132173 */ // Label 4048: @132173 |
| 47583 | /* 132173 */ GIM_Reject, |
| 47584 | /* 132174 */ // Label 4045: @132174 |
| 47585 | /* 132174 */ GIM_Reject, |
| 47586 | /* 132175 */ // Label 4041: @132175 |
| 47587 | /* 132175 */ GIM_Reject, |
| 47588 | /* 132176 */ // Label 93: @132176 |
| 47589 | /* 132176 */ GIM_Try, /*On fail goto*//*Label 4049*/ GIMT_Encode4(132456), |
| 47590 | /* 132181 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 47591 | /* 132184 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4053*/ GIMT_Encode4(132455), |
| 47592 | /* 132195 */ /*GILLT_v16s8*//*Label 4050*/ GIMT_Encode4(132215), GIMT_Encode4(0), |
| 47593 | /* 132203 */ /*GILLT_v8s16*//*Label 4051*/ GIMT_Encode4(132297), GIMT_Encode4(0), |
| 47594 | /* 132211 */ /*GILLT_v4s32*//*Label 4052*/ GIMT_Encode4(132373), |
| 47595 | /* 132215 */ // Label 4050: @132215 |
| 47596 | /* 132215 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4054*/ GIMT_Encode4(132296), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3545 // |
| 47597 | /* 132222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47598 | /* 132226 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47599 | /* 132230 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 255:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 47600 | /* 132230 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47601 | /* 132233 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 47602 | /* 132237 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47603 | /* 132242 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(255), |
| 47604 | /* 132252 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47605 | /* 132255 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47606 | /* 132261 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47607 | /* 132267 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47608 | /* 132269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8), |
| 47609 | /* 132272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47610 | /* 132274 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47611 | /* 132277 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47612 | /* 132279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47613 | /* 132282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47614 | /* 132288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47615 | /* 132294 */ GIR_RootConstrainSelectedInstOperands, |
| 47616 | /* 132295 */ // GIR_Coverage, 3545, |
| 47617 | /* 132295 */ GIR_EraseRootFromParent_Done, |
| 47618 | /* 132296 */ // Label 4054: @132296 |
| 47619 | /* 132296 */ GIM_Reject, |
| 47620 | /* 132297 */ // Label 4051: @132297 |
| 47621 | /* 132297 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4055*/ GIMT_Encode4(132372), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3546 // |
| 47622 | /* 132304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47623 | /* 132308 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47624 | /* 132312 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVu16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 65535:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 47625 | /* 132312 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47626 | /* 132315 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16), |
| 47627 | /* 132319 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47628 | /* 132324 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535), |
| 47629 | /* 132334 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47630 | /* 132337 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47631 | /* 132343 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47632 | /* 132345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16), |
| 47633 | /* 132348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47634 | /* 132350 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47635 | /* 132353 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47636 | /* 132355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47637 | /* 132358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47638 | /* 132364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47639 | /* 132370 */ GIR_RootConstrainSelectedInstOperands, |
| 47640 | /* 132371 */ // GIR_Coverage, 3546, |
| 47641 | /* 132371 */ GIR_EraseRootFromParent_Done, |
| 47642 | /* 132372 */ // Label 4055: @132372 |
| 47643 | /* 132372 */ GIM_Reject, |
| 47644 | /* 132373 */ // Label 4052: @132373 |
| 47645 | /* 132373 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4056*/ GIMT_Encode4(132454), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3547 // |
| 47646 | /* 132380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47647 | /* 132384 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47648 | /* 132388 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 4294967295:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 47649 | /* 132388 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47650 | /* 132391 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 47651 | /* 132395 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47652 | /* 132400 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(4294967295), |
| 47653 | /* 132410 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47654 | /* 132413 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47655 | /* 132419 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47656 | /* 132425 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47657 | /* 132427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32), |
| 47658 | /* 132430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47659 | /* 132432 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47660 | /* 132435 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47661 | /* 132437 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47662 | /* 132440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47663 | /* 132446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47664 | /* 132452 */ GIR_RootConstrainSelectedInstOperands, |
| 47665 | /* 132453 */ // GIR_Coverage, 3547, |
| 47666 | /* 132453 */ GIR_EraseRootFromParent_Done, |
| 47667 | /* 132454 */ // Label 4056: @132454 |
| 47668 | /* 132454 */ GIM_Reject, |
| 47669 | /* 132455 */ // Label 4053: @132455 |
| 47670 | /* 132455 */ GIM_Reject, |
| 47671 | /* 132456 */ // Label 4049: @132456 |
| 47672 | /* 132456 */ GIM_Reject, |
| 47673 | /* 132457 */ // Label 94: @132457 |
| 47674 | /* 132457 */ GIM_Reject, |
| 47675 | /* 132458 */ }; // Size: 132458 bytes |
| 47676 | return MatchTable0; |
| 47677 | } |
| 47678 | #undef GIMT_Encode2 |
| 47679 | #undef GIMT_Encode4 |
| 47680 | #undef GIMT_Encode8 |
| 47681 | |
| 47682 | |
| 47683 | #endif // GET_GLOBALISEL_IMPL |
| 47684 | |
| 47685 | #ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 47686 | |
| 47687 | PredicateBitset AvailableModuleFeatures; |
| 47688 | mutable PredicateBitset AvailableFunctionFeatures; |
| 47689 | PredicateBitset getAvailableFeatures() const { |
| 47690 | return AvailableModuleFeatures | AvailableFunctionFeatures; |
| 47691 | } |
| 47692 | PredicateBitset |
| 47693 | computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const; |
| 47694 | PredicateBitset |
| 47695 | computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, |
| 47696 | const MachineFunction *MF) const; |
| 47697 | void setupGeneratedPerFunctionState(MachineFunction &MF) override; |
| 47698 | |
| 47699 | #endif // GET_GLOBALISEL_PREDICATES_DECL |
| 47700 | |
| 47701 | #ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 47702 | |
| 47703 | AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), |
| 47704 | AvailableFunctionFeatures() |
| 47705 | |
| 47706 | #endif // GET_GLOBALISEL_PREDICATES_INIT |
| 47707 | |
| 47708 |
Generated while processing llvm_projects/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
Generated on 2026-Sep-19 from project llvm_projects revision 8c8740bd9
Powered by 
Code Browser 2.1
Generator usage only permitted with license.