1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Global Instruction Selector for the ARM target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
11const unsigned MAX_SUBTARGET_PREDICATES = 83;
12using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
13
14#endif // GET_GLOBALISEL_PREDICATE_BITSET
15
16#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
17
18 mutable MatcherState State;
19 typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
20 typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
21 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
22 static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
23 static ARMInstructionSelector::CustomRendererFn CustomRenderers[];
24 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
25 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
26 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
27 const uint8_t *getMatchTable() const override;
28 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
29 bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override;
30 bool testSimplePredicate(unsigned PredicateID) const override;
31 bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
32
33#endif // GET_GLOBALISEL_TEMPORARIES_DECL
34
35#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
36
37, State(0),
38ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
39
40#endif // GET_GLOBALISEL_TEMPORARIES_INIT
41
42#ifdef GET_GLOBALISEL_IMPL
43
44// LLT Objects.
45enum {
46 GILLT_s16,
47 GILLT_s32,
48 GILLT_s64,
49 GILLT_v2s1,
50 GILLT_v4s1,
51 GILLT_v8s1,
52 GILLT_v16s1,
53 GILLT_v8s8,
54 GILLT_v16s8,
55 GILLT_v4s16,
56 GILLT_v8s16,
57 GILLT_v2s32,
58 GILLT_v4s32,
59 GILLT_v2s64,
60 GILLT_v4s64,
61 GILLT_v8s64,
62};
63const static size_t NumTypeObjects = 16;
64const static LLT TypeObjects[] = {
65 LLT::scalar(16),
66 LLT::scalar(32),
67 LLT::scalar(64),
68 LLT::vector(ElementCount::getFixed(2), LLT::scalar(1)),
69 LLT::vector(ElementCount::getFixed(4), LLT::scalar(1)),
70 LLT::vector(ElementCount::getFixed(8), LLT::scalar(1)),
71 LLT::vector(ElementCount::getFixed(16), LLT::scalar(1)),
72 LLT::vector(ElementCount::getFixed(8), LLT::scalar(8)),
73 LLT::vector(ElementCount::getFixed(16), LLT::scalar(8)),
74 LLT::vector(ElementCount::getFixed(4), LLT::scalar(16)),
75 LLT::vector(ElementCount::getFixed(8), LLT::scalar(16)),
76 LLT::vector(ElementCount::getFixed(2), LLT::scalar(32)),
77 LLT::vector(ElementCount::getFixed(4), LLT::scalar(32)),
78 LLT::vector(ElementCount::getFixed(2), LLT::scalar(64)),
79 LLT::vector(ElementCount::getFixed(4), LLT::scalar(64)),
80 LLT::vector(ElementCount::getFixed(8), LLT::scalar(64)),
81};
82
83// Bits for subtarget features that participate in instruction matching.
84enum SubtargetFeatureBits : uint8_t {
85 Feature_NoHonorSignDependentRoundingBit = 73,
86 Feature_HasV4TBit = 4,
87 Feature_NoV4TBit = 5,
88 Feature_HasV5TBit = 11,
89 Feature_NoV5TBit = 63,
90 Feature_HasV5TEBit = 9,
91 Feature_HasV6Bit = 0,
92 Feature_NoV6Bit = 7,
93 Feature_HasV6MBit = 26,
94 Feature_HasV8MBaselineBit = 33,
95 Feature_HasV8_1MMainlineBit = 39,
96 Feature_HasMVEIntBit = 61,
97 Feature_HasMVEFloatBit = 62,
98 Feature_HasCDEBit = 82,
99 Feature_HasFPRegsBit = 40,
100 Feature_HasFPRegs16Bit = 41,
101 Feature_HasFPRegs64Bit = 74,
102 Feature_HasV6T2Bit = 6,
103 Feature_HasV6KBit = 16,
104 Feature_HasV7Bit = 3,
105 Feature_HasV8Bit = 53,
106 Feature_PreV8Bit = 17,
107 Feature_HasV8_1aBit = 76,
108 Feature_HasV8_3aBit = 77,
109 Feature_NoVFPBit = 20,
110 Feature_HasVFP2Bit = 19,
111 Feature_HasVFP3Bit = 50,
112 Feature_HasVFP4Bit = 48,
113 Feature_HasDPVFPBit = 42,
114 Feature_HasFPARMv8Bit = 45,
115 Feature_HasNEONBit = 51,
116 Feature_HasSHA2Bit = 60,
117 Feature_HasAESBit = 52,
118 Feature_HasDotProdBit = 54,
119 Feature_HasCRCBit = 12,
120 Feature_HasLOBBit = 38,
121 Feature_HasFP16Bit = 59,
122 Feature_HasFullFP16Bit = 44,
123 Feature_HasMatMulInt8Bit = 55,
124 Feature_HasDivideInThumbBit = 35,
125 Feature_HasDivideInARMBit = 10,
126 Feature_HasDSPBit = 34,
127 Feature_HasDBBit = 13,
128 Feature_HasV7ClrexBit = 15,
129 Feature_HasAcquireReleaseBit = 14,
130 Feature_HasMPBit = 2,
131 Feature_Has8MSecExtBit = 27,
132 Feature_HasZCZBit = 56,
133 Feature_UseNEONForFPBit = 80,
134 Feature_DontUseNEONForFPBit = 43,
135 Feature_IsThumbBit = 24,
136 Feature_IsThumb1OnlyBit = 25,
137 Feature_IsThumb2Bit = 32,
138 Feature_IsNotMClassBit = 36,
139 Feature_IsARMBit = 1,
140 Feature_IsWindowsBit = 28,
141 Feature_IsNotWindowsBit = 29,
142 Feature_IsReadTPTPIDRURWBit = 66,
143 Feature_IsReadTPTPIDRUROBit = 67,
144 Feature_IsReadTPTPIDRPRWBit = 68,
145 Feature_IsReadTPSoftBit = 18,
146 Feature_UseMovtBit = 37,
147 Feature_DontUseMovtBit = 21,
148 Feature_UseMovtInPicBit = 22,
149 Feature_DontUseMovtInPicBit = 23,
150 Feature_UseFPVMLxBit = 47,
151 Feature_SLSBLRMitigationBit = 65,
152 Feature_NoSLSBLRMitigationBit = 64,
153 Feature_UseMulOpsBit = 8,
154 Feature_UseFusedMACBit = 49,
155 Feature_HasFastVGETLNi32Bit = 57,
156 Feature_HasSlowVGETLNi32Bit = 78,
157 Feature_HasFastVDUP32Bit = 58,
158 Feature_HasSlowVDUP32Bit = 79,
159 Feature_UseVMOVSRBit = 46,
160 Feature_DontUseVMOVSRBit = 81,
161 Feature_IsLEBit = 72,
162 Feature_IsBEBit = 75,
163 Feature_GenExecuteOnlyBit = 31,
164 Feature_DontGenExecuteOnlyBit = 30,
165 Feature_GenT1ExecuteOnlyBit = 71,
166 Feature_SignRetAddrBit = 70,
167 Feature_NoSignRetAddrBit = 69,
168};
169
170PredicateBitset ARMInstructionSelector::
171computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const {
172 PredicateBitset Features{};
173 if (!TM.Options.HonorSignDependentRoundingFPMath())
174 Features.set(Feature_NoHonorSignDependentRoundingBit);
175 if (Subtarget->hasV4TOps())
176 Features.set(Feature_HasV4TBit);
177 if (!Subtarget->hasV4TOps())
178 Features.set(Feature_NoV4TBit);
179 if (Subtarget->hasV5TOps())
180 Features.set(Feature_HasV5TBit);
181 if (!Subtarget->hasV5TOps())
182 Features.set(Feature_NoV5TBit);
183 if (Subtarget->hasV5TEOps())
184 Features.set(Feature_HasV5TEBit);
185 if (Subtarget->hasV6Ops())
186 Features.set(Feature_HasV6Bit);
187 if (!Subtarget->hasV6Ops())
188 Features.set(Feature_NoV6Bit);
189 if (Subtarget->hasV6MOps())
190 Features.set(Feature_HasV6MBit);
191 if (Subtarget->hasV8MBaselineOps())
192 Features.set(Feature_HasV8MBaselineBit);
193 if (Subtarget->hasV8_1MMainlineOps())
194 Features.set(Feature_HasV8_1MMainlineBit);
195 if (Subtarget->hasMVEIntegerOps())
196 Features.set(Feature_HasMVEIntBit);
197 if (Subtarget->hasMVEFloatOps())
198 Features.set(Feature_HasMVEFloatBit);
199 if (Subtarget->hasCDEOps())
200 Features.set(Feature_HasCDEBit);
201 if (Subtarget->hasFPRegs())
202 Features.set(Feature_HasFPRegsBit);
203 if (Subtarget->hasFPRegs16())
204 Features.set(Feature_HasFPRegs16Bit);
205 if (Subtarget->hasFPRegs64())
206 Features.set(Feature_HasFPRegs64Bit);
207 if (Subtarget->hasV6T2Ops())
208 Features.set(Feature_HasV6T2Bit);
209 if (Subtarget->hasV6KOps())
210 Features.set(Feature_HasV6KBit);
211 if (Subtarget->hasV7Ops())
212 Features.set(Feature_HasV7Bit);
213 if (Subtarget->hasV8Ops())
214 Features.set(Feature_HasV8Bit);
215 if (!Subtarget->hasV8Ops())
216 Features.set(Feature_PreV8Bit);
217 if (Subtarget->hasV8_1aOps())
218 Features.set(Feature_HasV8_1aBit);
219 if (Subtarget->hasV8_3aOps())
220 Features.set(Feature_HasV8_3aBit);
221 if (!Subtarget->hasVFP2Base())
222 Features.set(Feature_NoVFPBit);
223 if (Subtarget->hasVFP2Base())
224 Features.set(Feature_HasVFP2Bit);
225 if (Subtarget->hasVFP3Base())
226 Features.set(Feature_HasVFP3Bit);
227 if (Subtarget->hasVFP4Base())
228 Features.set(Feature_HasVFP4Bit);
229 if (Subtarget->hasFP64())
230 Features.set(Feature_HasDPVFPBit);
231 if (Subtarget->hasFPARMv8Base())
232 Features.set(Feature_HasFPARMv8Bit);
233 if (Subtarget->hasNEON())
234 Features.set(Feature_HasNEONBit);
235 if (Subtarget->hasSHA2())
236 Features.set(Feature_HasSHA2Bit);
237 if (Subtarget->hasAES())
238 Features.set(Feature_HasAESBit);
239 if (Subtarget->hasDotProd())
240 Features.set(Feature_HasDotProdBit);
241 if (Subtarget->hasCRC())
242 Features.set(Feature_HasCRCBit);
243 if (Subtarget->hasLOB())
244 Features.set(Feature_HasLOBBit);
245 if (Subtarget->hasFP16())
246 Features.set(Feature_HasFP16Bit);
247 if (Subtarget->hasFullFP16())
248 Features.set(Feature_HasFullFP16Bit);
249 if (Subtarget->hasMatMulInt8())
250 Features.set(Feature_HasMatMulInt8Bit);
251 if (Subtarget->hasDivideInThumbMode())
252 Features.set(Feature_HasDivideInThumbBit);
253 if (Subtarget->hasDivideInARMMode())
254 Features.set(Feature_HasDivideInARMBit);
255 if (Subtarget->hasDSP())
256 Features.set(Feature_HasDSPBit);
257 if (Subtarget->hasDataBarrier())
258 Features.set(Feature_HasDBBit);
259 if (Subtarget->hasV7Clrex())
260 Features.set(Feature_HasV7ClrexBit);
261 if (Subtarget->hasAcquireRelease())
262 Features.set(Feature_HasAcquireReleaseBit);
263 if (Subtarget->hasMPExtension())
264 Features.set(Feature_HasMPBit);
265 if (Subtarget->has8MSecExt())
266 Features.set(Feature_Has8MSecExtBit);
267 if (Subtarget->hasZeroCycleZeroing())
268 Features.set(Feature_HasZCZBit);
269 if (Subtarget->useNEONForSinglePrecisionFP())
270 Features.set(Feature_UseNEONForFPBit);
271 if (!Subtarget->useNEONForSinglePrecisionFP())
272 Features.set(Feature_DontUseNEONForFPBit);
273 if (Subtarget->isThumb())
274 Features.set(Feature_IsThumbBit);
275 if (Subtarget->isThumb1Only())
276 Features.set(Feature_IsThumb1OnlyBit);
277 if (Subtarget->isThumb2())
278 Features.set(Feature_IsThumb2Bit);
279 if (!Subtarget->isMClass())
280 Features.set(Feature_IsNotMClassBit);
281 if (!Subtarget->isThumb())
282 Features.set(Feature_IsARMBit);
283 if (Subtarget->isTargetWindows())
284 Features.set(Feature_IsWindowsBit);
285 if (!Subtarget->isTargetWindows())
286 Features.set(Feature_IsNotWindowsBit);
287 if (Subtarget->isReadTPTPIDRURW())
288 Features.set(Feature_IsReadTPTPIDRURWBit);
289 if (Subtarget->isReadTPTPIDRURO())
290 Features.set(Feature_IsReadTPTPIDRUROBit);
291 if (Subtarget->isReadTPTPIDRPRW())
292 Features.set(Feature_IsReadTPTPIDRPRWBit);
293 if (Subtarget->isReadTPSoft())
294 Features.set(Feature_IsReadTPSoftBit);
295 if (Subtarget->useMulOps())
296 Features.set(Feature_UseMulOpsBit);
297 if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast && Subtarget->useFPVFMx())
298 Features.set(Feature_UseFusedMACBit);
299 if (!Subtarget->hasSlowVGETLNi32())
300 Features.set(Feature_HasFastVGETLNi32Bit);
301 if (Subtarget->hasSlowVGETLNi32())
302 Features.set(Feature_HasSlowVGETLNi32Bit);
303 if (!Subtarget->hasSlowVDUP32())
304 Features.set(Feature_HasFastVDUP32Bit);
305 if (Subtarget->hasSlowVDUP32())
306 Features.set(Feature_HasSlowVDUP32Bit);
307 if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())
308 Features.set(Feature_UseVMOVSRBit);
309 if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP())
310 Features.set(Feature_DontUseVMOVSRBit);
311 if (Subtarget->genExecuteOnly())
312 Features.set(Feature_GenExecuteOnlyBit);
313 if (!Subtarget->genExecuteOnly())
314 Features.set(Feature_DontGenExecuteOnlyBit);
315 if (Subtarget->genExecuteOnly() && Subtarget->isThumb1Only() && !Subtarget->hasV8MBaselineOps())
316 Features.set(Feature_GenT1ExecuteOnlyBit);
317 return Features;
318}
319
320void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
321 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget *)&MF.getSubtarget(), &MF);
322}
323PredicateBitset ARMInstructionSelector::
324computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const {
325 PredicateBitset Features{};
326 if (Subtarget->useMovt())
327 Features.set(Feature_UseMovtBit);
328 if (!Subtarget->useMovt())
329 Features.set(Feature_DontUseMovtBit);
330 if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt())
331 Features.set(Feature_UseMovtInPicBit);
332 if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt())
333 Features.set(Feature_DontUseMovtInPicBit);
334 if (((Subtarget->useFPVMLx() && TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||Subtarget->hasMinSize()))
335 Features.set(Feature_UseFPVMLxBit);
336 if ( MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
337 Features.set(Feature_SLSBLRMitigationBit);
338 if ( !MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
339 Features.set(Feature_NoSLSBLRMitigationBit);
340 if (MF->getDataLayout().isLittleEndian())
341 Features.set(Feature_IsLEBit);
342 if (MF->getDataLayout().isBigEndian())
343 Features.set(Feature_IsBEBit);
344 if ( MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) )
345 Features.set(Feature_SignRetAddrBit);
346 if ( !MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) )
347 Features.set(Feature_NoSignRetAddrBit);
348 return Features;
349}
350
351// Feature bitsets.
352enum {
353 GIFBS_Invalid,
354 GIFBS_HasDotProd,
355 GIFBS_HasFP16,
356 GIFBS_HasFPARMv8,
357 GIFBS_HasFPRegs,
358 GIFBS_HasFullFP16,
359 GIFBS_HasMVEFloat,
360 GIFBS_HasMVEInt,
361 GIFBS_HasMatMulInt8,
362 GIFBS_HasNEON,
363 GIFBS_HasVFP2,
364 GIFBS_HasVFP3,
365 GIFBS_HasVFP4,
366 GIFBS_IsARM,
367 GIFBS_IsThumb,
368 GIFBS_IsThumb2,
369 GIFBS_NoHonorSignDependentRounding,
370 GIFBS_DontUseNEONForFP_HasVFP2,
371 GIFBS_DontUseVMOVSR_HasNEON,
372 GIFBS_Has8MSecExt_IsThumb,
373 GIFBS_HasAES_HasV8,
374 GIFBS_HasCRC_IsARM,
375 GIFBS_HasCRC_IsThumb2,
376 GIFBS_HasDB_IsARM,
377 GIFBS_HasDB_IsThumb,
378 GIFBS_HasDPVFP_HasFPARMv8,
379 GIFBS_HasDPVFP_HasVFP2,
380 GIFBS_HasDPVFP_HasVFP3,
381 GIFBS_HasDPVFP_HasVFP4,
382 GIFBS_HasDPVFP_NoHonorSignDependentRounding,
383 GIFBS_HasDSP_IsThumb2,
384 GIFBS_HasDivideInARM_IsARM,
385 GIFBS_HasFP16_HasNEON,
386 GIFBS_HasFPARMv8_HasNEON,
387 GIFBS_HasFPRegs_HasFastVGETLNi32,
388 GIFBS_HasFPRegs_UseVMOVSR,
389 GIFBS_HasFullFP16_HasNEON,
390 GIFBS_HasMVEInt_HasV8_1MMainline,
391 GIFBS_HasMVEInt_IsBE,
392 GIFBS_HasMVEInt_IsLE,
393 GIFBS_HasNEON_HasV8,
394 GIFBS_HasNEON_HasV8_1a,
395 GIFBS_HasNEON_HasV8_3a,
396 GIFBS_HasNEON_HasVFP4,
397 GIFBS_HasNEON_IsBE,
398 GIFBS_HasNEON_IsLE,
399 GIFBS_HasNEON_UseNEONForFP,
400 GIFBS_HasSHA2_HasV8,
401 GIFBS_HasV5T_IsARM,
402 GIFBS_HasV5T_IsThumb,
403 GIFBS_HasV5TE_IsARM,
404 GIFBS_HasV6_IsARM,
405 GIFBS_HasV6K_IsARM,
406 GIFBS_HasV6M_IsThumb,
407 GIFBS_HasV6T2_IsARM,
408 GIFBS_HasV7_IsARM,
409 GIFBS_HasV7Clrex_IsThumb,
410 GIFBS_HasV8MBaseline_IsThumb,
411 GIFBS_IsARM_NoV5T,
412 GIFBS_IsARM_NoV6,
413 GIFBS_IsARM_PreV8,
414 GIFBS_IsThumb_IsThumb1Only,
415 GIFBS_IsThumb_IsWindows,
416 GIFBS_IsThumb_NoV5T,
417 GIFBS_IsThumb_UseMovt,
418 GIFBS_IsThumb2_PreV8,
419 GIFBS_IsThumb2_UseMulOps,
420 GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only,
421 GIFBS_HasDSP_IsThumb2_UseMulOps,
422 GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
423 GIFBS_HasFPARMv8_HasFullFP16_HasNEON,
424 GIFBS_HasFullFP16_HasNEON_HasV8,
425 GIFBS_HasFullFP16_HasNEON_HasV8_3a,
426 GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
427 GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
428 GIFBS_HasLOB_HasV8_1MMainline_IsThumb2,
429 GIFBS_HasNEON_UseFPVMLx_UseNEONForFP,
430 GIFBS_HasV5TE_IsARM_UseMulOps,
431 GIFBS_HasV6_IsARM_UseMulOps,
432 GIFBS_HasV6_IsThumb_IsThumb1Only,
433 GIFBS_HasV6T2_IsARM_UseMulOps,
434 GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP,
435 GIFBS_IsARM_NoV6_UseMulOps,
436};
437constexpr static PredicateBitset FeatureBitsets[] {
438 {}, // GIFBS_Invalid
439 {Feature_HasDotProdBit, },
440 {Feature_HasFP16Bit, },
441 {Feature_HasFPARMv8Bit, },
442 {Feature_HasFPRegsBit, },
443 {Feature_HasFullFP16Bit, },
444 {Feature_HasMVEFloatBit, },
445 {Feature_HasMVEIntBit, },
446 {Feature_HasMatMulInt8Bit, },
447 {Feature_HasNEONBit, },
448 {Feature_HasVFP2Bit, },
449 {Feature_HasVFP3Bit, },
450 {Feature_HasVFP4Bit, },
451 {Feature_IsARMBit, },
452 {Feature_IsThumbBit, },
453 {Feature_IsThumb2Bit, },
454 {Feature_NoHonorSignDependentRoundingBit, },
455 {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, },
456 {Feature_DontUseVMOVSRBit, Feature_HasNEONBit, },
457 {Feature_Has8MSecExtBit, Feature_IsThumbBit, },
458 {Feature_HasAESBit, Feature_HasV8Bit, },
459 {Feature_HasCRCBit, Feature_IsARMBit, },
460 {Feature_HasCRCBit, Feature_IsThumb2Bit, },
461 {Feature_HasDBBit, Feature_IsARMBit, },
462 {Feature_HasDBBit, Feature_IsThumbBit, },
463 {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, },
464 {Feature_HasDPVFPBit, Feature_HasVFP2Bit, },
465 {Feature_HasDPVFPBit, Feature_HasVFP3Bit, },
466 {Feature_HasDPVFPBit, Feature_HasVFP4Bit, },
467 {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, },
468 {Feature_HasDSPBit, Feature_IsThumb2Bit, },
469 {Feature_HasDivideInARMBit, Feature_IsARMBit, },
470 {Feature_HasFP16Bit, Feature_HasNEONBit, },
471 {Feature_HasFPARMv8Bit, Feature_HasNEONBit, },
472 {Feature_HasFPRegsBit, Feature_HasFastVGETLNi32Bit, },
473 {Feature_HasFPRegsBit, Feature_UseVMOVSRBit, },
474 {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
475 {Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, },
476 {Feature_HasMVEIntBit, Feature_IsBEBit, },
477 {Feature_HasMVEIntBit, Feature_IsLEBit, },
478 {Feature_HasNEONBit, Feature_HasV8Bit, },
479 {Feature_HasNEONBit, Feature_HasV8_1aBit, },
480 {Feature_HasNEONBit, Feature_HasV8_3aBit, },
481 {Feature_HasNEONBit, Feature_HasVFP4Bit, },
482 {Feature_HasNEONBit, Feature_IsBEBit, },
483 {Feature_HasNEONBit, Feature_IsLEBit, },
484 {Feature_HasNEONBit, Feature_UseNEONForFPBit, },
485 {Feature_HasSHA2Bit, Feature_HasV8Bit, },
486 {Feature_HasV5TBit, Feature_IsARMBit, },
487 {Feature_HasV5TBit, Feature_IsThumbBit, },
488 {Feature_HasV5TEBit, Feature_IsARMBit, },
489 {Feature_HasV6Bit, Feature_IsARMBit, },
490 {Feature_HasV6KBit, Feature_IsARMBit, },
491 {Feature_HasV6MBit, Feature_IsThumbBit, },
492 {Feature_HasV6T2Bit, Feature_IsARMBit, },
493 {Feature_HasV7Bit, Feature_IsARMBit, },
494 {Feature_HasV7ClrexBit, Feature_IsThumbBit, },
495 {Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
496 {Feature_IsARMBit, Feature_NoV5TBit, },
497 {Feature_IsARMBit, Feature_NoV6Bit, },
498 {Feature_IsARMBit, Feature_PreV8Bit, },
499 {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
500 {Feature_IsThumbBit, Feature_IsWindowsBit, },
501 {Feature_IsThumbBit, Feature_NoV5TBit, },
502 {Feature_IsThumbBit, Feature_UseMovtBit, },
503 {Feature_IsThumb2Bit, Feature_PreV8Bit, },
504 {Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
505 {Feature_DontUseMovtBit, Feature_GenExecuteOnlyBit, Feature_IsThumb1OnlyBit, },
506 {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
507 {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
508 {Feature_HasFPARMv8Bit, Feature_HasFullFP16Bit, Feature_HasNEONBit, },
509 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, },
510 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, },
511 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, },
512 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, },
513 {Feature_HasLOBBit, Feature_HasV8_1MMainlineBit, Feature_IsThumb2Bit, },
514 {Feature_HasNEONBit, Feature_UseFPVMLxBit, Feature_UseNEONForFPBit, },
515 {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, },
516 {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
517 {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
518 {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
519 {Feature_HasVFP4Bit, Feature_UseFusedMACBit, Feature_UseNEONForFPBit, },
520 {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, },
521};
522
523// ComplexPattern predicates.
524enum {
525 GICP_Invalid,
526};
527// See constructor for table contents
528
529ARMInstructionSelector::ComplexMatcherMemFn
530ARMInstructionSelector::ComplexPredicateFns[] = {
531 nullptr, // GICP_Invalid
532};
533
534// PatFrag predicates.
535enum {
536 GICXXPred_MI_Predicate_bf_inv_mask_imm = GICXXPred_Invalid + 1,
537 GICXXPred_MI_Predicate_ffloor_nnan,
538 GICXXPred_MI_Predicate_or_disjoint,
539 GICXXPred_MI_Predicate_vfp_f32imm,
540 GICXXPred_MI_Predicate_vfp_f64imm,
541};
542bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
543 const MachineFunction &MF = *MI.getParent()->getParent();
544 const MachineRegisterInfo &MRI = MF.getRegInfo();
545 const auto &Operands = State.RecordedOperands;
546 (void)Operands;
547 (void)MRI;
548 switch (PredicateID) {
549 case GICXXPred_MI_Predicate_bf_inv_mask_imm: {
550
551 // There's better methods of implementing this check. IntImmLeaf<> would be
552 // equivalent and have less boilerplate but we need a test for C++
553 // predicates and this one causes new rules to be imported into GlobalISel
554 // without requiring additional features first.
555 const auto &MO = MI.getOperand(1);
556 if (!MO.isCImm())
557 return false;
558 return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue());
559
560 llvm_unreachable("bf_inv_mask_imm should have returned");
561 }
562 case GICXXPred_MI_Predicate_ffloor_nnan: {
563
564 return MI.getFlag(MachineInstr::FmNoNans);
565
566 }
567 case GICXXPred_MI_Predicate_or_disjoint: {
568
569 return MI.getFlag(MachineInstr::Disjoint);
570
571 }
572 case GICXXPred_MI_Predicate_vfp_f32imm: {
573
574 const auto &MO = MI.getOperand(1);
575 if (!MO.isFPImm())
576 return false;
577 return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1;
578
579 llvm_unreachable("vfp_f32imm should have returned");
580 }
581 case GICXXPred_MI_Predicate_vfp_f64imm: {
582
583 const auto &MO = MI.getOperand(1);
584 if (!MO.isFPImm())
585 return false;
586 return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1;
587
588 llvm_unreachable("vfp_f64imm should have returned");
589 }
590 }
591 llvm_unreachable("Unknown predicate");
592 return false;
593}
594// PatFrag predicates.
595bool ARMInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
596 const auto &Operands = State.RecordedOperands;
597 Register Reg = MO.getReg();
598 (void)Operands;
599 (void)Reg;
600 llvm_unreachable("Unknown predicate");
601 return false;
602}
603// PatFrag predicates.
604enum {
605 GICXXPred_I64_Predicate_VectorIndex8 = GICXXPred_Invalid + 1,
606 GICXXPred_I64_Predicate_VectorIndex16,
607 GICXXPred_I64_Predicate_VectorIndex32,
608 GICXXPred_I64_Predicate_VectorIndex32_Hi,
609 GICXXPred_I64_Predicate_VectorIndex64,
610 GICXXPred_I64_Predicate_asr_imm,
611 GICXXPred_I64_Predicate_imm0_7,
612 GICXXPred_I64_Predicate_imm0_15,
613 GICXXPred_I64_Predicate_imm0_31,
614 GICXXPred_I64_Predicate_imm0_32,
615 GICXXPred_I64_Predicate_imm0_63,
616 GICXXPred_I64_Predicate_imm0_239,
617 GICXXPred_I64_Predicate_imm0_255,
618 GICXXPred_I64_Predicate_imm0_255_expr,
619 GICXXPred_I64_Predicate_imm0_4095,
620 GICXXPred_I64_Predicate_imm0_65535,
621 GICXXPred_I64_Predicate_imm0_65535_expr,
622 GICXXPred_I64_Predicate_imm0_65535_neg,
623 GICXXPred_I64_Predicate_imm1_7,
624 GICXXPred_I64_Predicate_imm1_15,
625 GICXXPred_I64_Predicate_imm1_16,
626 GICXXPred_I64_Predicate_imm1_31,
627 GICXXPred_I64_Predicate_imm8,
628 GICXXPred_I64_Predicate_imm8_255,
629 GICXXPred_I64_Predicate_imm8_or_16,
630 GICXXPred_I64_Predicate_imm16,
631 GICXXPred_I64_Predicate_imm16_31,
632 GICXXPred_I64_Predicate_imm24b,
633 GICXXPred_I64_Predicate_imm32,
634 GICXXPred_I64_Predicate_imm256_510,
635 GICXXPred_I64_Predicate_imm_3b,
636 GICXXPred_I64_Predicate_imm_4b,
637 GICXXPred_I64_Predicate_imm_6b,
638 GICXXPred_I64_Predicate_imm_7b,
639 GICXXPred_I64_Predicate_imm_9b,
640 GICXXPred_I64_Predicate_imm_11b,
641 GICXXPred_I64_Predicate_imm_12b,
642 GICXXPred_I64_Predicate_imm_13b,
643 GICXXPred_I64_Predicate_imm_even,
644 GICXXPred_I64_Predicate_imm_odd,
645 GICXXPred_I64_Predicate_imm_sr,
646 GICXXPred_I64_Predicate_long_shift,
647 GICXXPred_I64_Predicate_mod_imm,
648 GICXXPred_I64_Predicate_mod_imm_not,
649 GICXXPred_I64_Predicate_pkh_asr_amt,
650 GICXXPred_I64_Predicate_pkh_lsl_amt,
651 GICXXPred_I64_Predicate_shr_imm8,
652 GICXXPred_I64_Predicate_shr_imm16,
653 GICXXPred_I64_Predicate_shr_imm32,
654 GICXXPred_I64_Predicate_shr_imm64,
655 GICXXPred_I64_Predicate_t2_so_imm,
656 GICXXPred_I64_Predicate_t2_so_imm_neg,
657};
658bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
659 switch (PredicateID) {
660 case GICXXPred_I64_Predicate_VectorIndex8: {
661
662 return ((uint64_t)Imm) < 8;
663
664 }
665 case GICXXPred_I64_Predicate_VectorIndex16: {
666
667 return ((uint64_t)Imm) < 4;
668
669 }
670 case GICXXPred_I64_Predicate_VectorIndex32: {
671
672 return ((uint64_t)Imm) < 2;
673
674 }
675 case GICXXPred_I64_Predicate_VectorIndex32_Hi: {
676
677 return ((uint64_t)Imm) >= 2 && ((uint64_t)Imm) < 4;
678
679 }
680 case GICXXPred_I64_Predicate_VectorIndex64: {
681
682 return ((uint64_t)Imm) < 1;
683
684 }
685 case GICXXPred_I64_Predicate_asr_imm: {
686 return Imm > 0 && Imm <= 32;
687 }
688 case GICXXPred_I64_Predicate_imm0_7: {
689
690 return Imm >= 0 && Imm < 8;
691
692 }
693 case GICXXPred_I64_Predicate_imm0_15: {
694
695 return Imm >= 0 && Imm < 16;
696
697 }
698 case GICXXPred_I64_Predicate_imm0_31: {
699
700 return Imm >= 0 && Imm < 32;
701
702 }
703 case GICXXPred_I64_Predicate_imm0_32: {
704
705 return Imm >= 0 && Imm < 33;
706
707 }
708 case GICXXPred_I64_Predicate_imm0_63: {
709
710 return Imm >= 0 && Imm < 64;
711
712 }
713 case GICXXPred_I64_Predicate_imm0_239: {
714 return Imm >= 0 && Imm < 240;
715 }
716 case GICXXPred_I64_Predicate_imm0_255: {
717 return Imm >= 0 && Imm < 256;
718 }
719 case GICXXPred_I64_Predicate_imm0_255_expr: {
720 return Imm >= 0 && Imm < 256;
721 }
722 case GICXXPred_I64_Predicate_imm0_4095: {
723
724 return Imm >= 0 && Imm < 4096;
725
726 }
727 case GICXXPred_I64_Predicate_imm0_65535: {
728
729 return Imm >= 0 && Imm < 65536;
730
731 }
732 case GICXXPred_I64_Predicate_imm0_65535_expr: {
733
734 return Imm >= 0 && Imm < 65536;
735
736 }
737 case GICXXPred_I64_Predicate_imm0_65535_neg: {
738
739 return -Imm >= 0 && -Imm < 65536;
740
741 }
742 case GICXXPred_I64_Predicate_imm1_7: {
743 return Imm > 0 && Imm < 8;
744 }
745 case GICXXPred_I64_Predicate_imm1_15: {
746 return Imm > 0 && Imm < 16;
747 }
748 case GICXXPred_I64_Predicate_imm1_16: {
749
750 return Imm > 0 && Imm <= 16;
751
752 }
753 case GICXXPred_I64_Predicate_imm1_31: {
754 return Imm > 0 && Imm < 32;
755 }
756 case GICXXPred_I64_Predicate_imm8: {
757 return Imm == 8;
758 }
759 case GICXXPred_I64_Predicate_imm8_255: {
760
761 return Imm >= 8 && Imm < 256;
762
763 }
764 case GICXXPred_I64_Predicate_imm8_or_16: {
765 return Imm == 8 || Imm == 16;
766 }
767 case GICXXPred_I64_Predicate_imm16: {
768 return Imm == 16;
769 }
770 case GICXXPred_I64_Predicate_imm16_31: {
771
772 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
773
774 }
775 case GICXXPred_I64_Predicate_imm24b: {
776
777 return Imm >= 0 && Imm <= 0xffffff;
778
779 }
780 case GICXXPred_I64_Predicate_imm32: {
781 return Imm == 32;
782 }
783 case GICXXPred_I64_Predicate_imm256_510: {
784
785 return Imm >= 256 && Imm < 511;
786
787 }
788 case GICXXPred_I64_Predicate_imm_3b: {
789 { return Imm >= 0 && Imm < (1 << 3); }
790 llvm_unreachable("imm_3b should have returned");
791 }
792 case GICXXPred_I64_Predicate_imm_4b: {
793 { return Imm >= 0 && Imm < (1 << 4); }
794 llvm_unreachable("imm_4b should have returned");
795 }
796 case GICXXPred_I64_Predicate_imm_6b: {
797 { return Imm >= 0 && Imm < (1 << 6); }
798 llvm_unreachable("imm_6b should have returned");
799 }
800 case GICXXPred_I64_Predicate_imm_7b: {
801 { return Imm >= 0 && Imm < (1 << 7); }
802 llvm_unreachable("imm_7b should have returned");
803 }
804 case GICXXPred_I64_Predicate_imm_9b: {
805 { return Imm >= 0 && Imm < (1 << 9); }
806 llvm_unreachable("imm_9b should have returned");
807 }
808 case GICXXPred_I64_Predicate_imm_11b: {
809 { return Imm >= 0 && Imm < (1 << 11); }
810 llvm_unreachable("imm_11b should have returned");
811 }
812 case GICXXPred_I64_Predicate_imm_12b: {
813 { return Imm >= 0 && Imm < (1 << 12); }
814 llvm_unreachable("imm_12b should have returned");
815 }
816 case GICXXPred_I64_Predicate_imm_13b: {
817 { return Imm >= 0 && Imm < (1 << 13); }
818 llvm_unreachable("imm_13b should have returned");
819 }
820 case GICXXPred_I64_Predicate_imm_even: {
821 return (Imm & 1) == 0;
822 }
823 case GICXXPred_I64_Predicate_imm_odd: {
824 return (Imm & 1) == 1;
825 }
826 case GICXXPred_I64_Predicate_imm_sr: {
827
828 return Imm > 0 && Imm <= 32;
829
830 }
831 case GICXXPred_I64_Predicate_long_shift: {
832 return Imm > 0 && Imm <= 32;
833 }
834 case GICXXPred_I64_Predicate_mod_imm: {
835
836 return ARM_AM::getSOImmVal(Imm) != -1;
837
838 }
839 case GICXXPred_I64_Predicate_mod_imm_not: {
840
841 return ARM_AM::getSOImmVal(~(uint32_t)Imm) != -1;
842
843 }
844 case GICXXPred_I64_Predicate_pkh_asr_amt: {
845 return Imm > 0 && Imm <= 32;
846 }
847 case GICXXPred_I64_Predicate_pkh_lsl_amt: {
848 return Imm >= 0 && Imm < 32;
849 }
850 case GICXXPred_I64_Predicate_shr_imm8: {
851 return Imm > 0 && Imm <= 8;
852 }
853 case GICXXPred_I64_Predicate_shr_imm16: {
854 return Imm > 0 && Imm <= 16;
855 }
856 case GICXXPred_I64_Predicate_shr_imm32: {
857 return Imm > 0 && Imm <= 32;
858 }
859 case GICXXPred_I64_Predicate_shr_imm64: {
860 return Imm > 0 && Imm <= 64;
861 }
862 case GICXXPred_I64_Predicate_t2_so_imm: {
863
864 return ARM_AM::getT2SOImmVal(Imm) != -1;
865
866 }
867 case GICXXPred_I64_Predicate_t2_so_imm_neg: {
868
869 return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
870
871 }
872 }
873 llvm_unreachable("Unknown predicate");
874 return false;
875}
876// PatFrag predicates.
877bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
878 llvm_unreachable("Unknown predicate");
879 return false;
880}
881// PatFrag predicates.
882enum {
883 GICXXPred_APInt_Predicate_arm_i32imm = GICXXPred_Invalid + 1,
884};
885bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
886 switch (PredicateID) {
887 case GICXXPred_APInt_Predicate_arm_i32imm: {
888
889 if (Subtarget->useMovt())
890 return true;
891 if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue()))
892 return true;
893 return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue());
894
895 llvm_unreachable("arm_i32imm should have returned");
896 }
897 }
898 llvm_unreachable("Unknown predicate");
899 return false;
900}
901bool ARMInstructionSelector::testSimplePredicate(unsigned) const {
902 llvm_unreachable("ARMInstructionSelector does not support simple predicates!");
903 return false;
904}
905// Custom renderers.
906enum {
907 GICR_Invalid,
908 GICR_renderInvertedImm,
909 GICR_renderVFPF32Imm,
910 GICR_renderVFPF64Imm,
911};
912ARMInstructionSelector::CustomRendererFn
913ARMInstructionSelector::CustomRenderers[] = {
914 nullptr, // GICR_Invalid
915 &ARMInstructionSelector::renderInvertedImm,
916 &ARMInstructionSelector::renderVFPF32Imm,
917 &ARMInstructionSelector::renderVFPF64Imm,
918};
919
920bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
921 const PredicateBitset AvailableFeatures = getAvailableFeatures();
922 MachineIRBuilder B(I);
923 State.MIs.clear();
924 State.MIs.push_back(&I);
925
926 if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
927 return true;
928 }
929
930 return false;
931}
932
933bool ARMInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
934 llvm_unreachable("ARMInstructionSelector does not support custom C++ actions!");
935}
936#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
937#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((Val) >> 8)
938#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24)
939#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24), uint8_t(uint64_t(Val) >> 32), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 56)
940#else
941#define GIMT_Encode2(Val) uint8_t((Val) >> 8), uint8_t(Val)
942#define GIMT_Encode4(Val) uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
943#define GIMT_Encode8(Val) uint8_t(uint64_t(Val) >> 56), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 32), uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
944#endif
945const uint8_t *ARMInstructionSelector::getMatchTable() const {
946 constexpr static uint8_t MatchTable0[] = {
947 /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(55), GIMT_Encode2(323), /*)*//*default:*//*Label 92*/ GIMT_Encode4(141695),
948 /* 10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(1082),
949 /* 14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(13001),
950 /* 18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(16237),
951 /* 22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(17929),
952 /* 26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(18025), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
953 /* 46 */ /*TargetOpcode::G_AND*//*Label 5*/ GIMT_Encode4(18121),
954 /* 50 */ /*TargetOpcode::G_OR*//*Label 6*/ GIMT_Encode4(21293),
955 /* 54 */ /*TargetOpcode::G_XOR*//*Label 7*/ GIMT_Encode4(27094),
956 /* 58 */ /*TargetOpcode::G_ABDS*//*Label 8*/ GIMT_Encode4(28781),
957 /* 62 */ /*TargetOpcode::G_ABDU*//*Label 9*/ GIMT_Encode4(29300),
958 /* 66 */ /*TargetOpcode::G_UAVGFLOOR*//*Label 10*/ GIMT_Encode4(29819),
959 /* 70 */ /*TargetOpcode::G_UAVGCEIL*//*Label 11*/ GIMT_Encode4(30046),
960 /* 74 */ /*TargetOpcode::G_SAVGFLOOR*//*Label 12*/ GIMT_Encode4(30273),
961 /* 78 */ /*TargetOpcode::G_SAVGCEIL*//*Label 13*/ GIMT_Encode4(30500), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
962 /* 130 */ /*TargetOpcode::G_CONCAT_VECTORS*//*Label 14*/ GIMT_Encode4(30727), GIMT_Encode4(0), GIMT_Encode4(0),
963 /* 142 */ /*TargetOpcode::G_BITCAST*//*Label 15*/ GIMT_Encode4(31094), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
964 /* 158 */ /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 16*/ GIMT_Encode4(40098),
965 /* 162 */ /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 17*/ GIMT_Encode4(40506), GIMT_Encode4(0), GIMT_Encode4(0),
966 /* 174 */ /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 18*/ GIMT_Encode4(40881), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
967 /* 190 */ /*TargetOpcode::G_SEXTLOAD*//*Label 19*/ GIMT_Encode4(41256), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
968 /* 318 */ /*TargetOpcode::G_FENCE*//*Label 20*/ GIMT_Encode4(41419), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
969 /* 338 */ /*TargetOpcode::G_INTRINSIC*//*Label 21*/ GIMT_Encode4(41440),
970 /* 342 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 22*/ GIMT_Encode4(98386), GIMT_Encode4(0), GIMT_Encode4(0),
971 /* 354 */ /*TargetOpcode::G_ANYEXT*//*Label 23*/ GIMT_Encode4(106048),
972 /* 358 */ /*TargetOpcode::G_TRUNC*//*Label 24*/ GIMT_Encode4(106190), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
973 /* 374 */ /*TargetOpcode::G_CONSTANT*//*Label 25*/ GIMT_Encode4(106336),
974 /* 378 */ /*TargetOpcode::G_FCONSTANT*//*Label 26*/ GIMT_Encode4(106657), GIMT_Encode4(0), GIMT_Encode4(0),
975 /* 390 */ /*TargetOpcode::G_SEXT*//*Label 27*/ GIMT_Encode4(106753),
976 /* 394 */ /*TargetOpcode::G_SEXT_INREG*//*Label 28*/ GIMT_Encode4(106895),
977 /* 398 */ /*TargetOpcode::G_ZEXT*//*Label 29*/ GIMT_Encode4(107500),
978 /* 402 */ /*TargetOpcode::G_SHL*//*Label 30*/ GIMT_Encode4(108200),
979 /* 406 */ /*TargetOpcode::G_LSHR*//*Label 31*/ GIMT_Encode4(108416),
980 /* 410 */ /*TargetOpcode::G_ASHR*//*Label 32*/ GIMT_Encode4(108524), GIMT_Encode4(0), GIMT_Encode4(0),
981 /* 422 */ /*TargetOpcode::G_ROTR*//*Label 33*/ GIMT_Encode4(108797), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
982 /* 490 */ /*TargetOpcode::G_UMULH*//*Label 34*/ GIMT_Encode4(109129),
983 /* 494 */ /*TargetOpcode::G_SMULH*//*Label 35*/ GIMT_Encode4(109365),
984 /* 498 */ /*TargetOpcode::G_UADDSAT*//*Label 36*/ GIMT_Encode4(109722),
985 /* 502 */ /*TargetOpcode::G_SADDSAT*//*Label 37*/ GIMT_Encode4(110359),
986 /* 506 */ /*TargetOpcode::G_USUBSAT*//*Label 38*/ GIMT_Encode4(111651),
987 /* 510 */ /*TargetOpcode::G_SSUBSAT*//*Label 39*/ GIMT_Encode4(112288), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
988 /* 554 */ /*TargetOpcode::G_FADD*//*Label 40*/ GIMT_Encode4(113300),
989 /* 558 */ /*TargetOpcode::G_FSUB*//*Label 41*/ GIMT_Encode4(115653),
990 /* 562 */ /*TargetOpcode::G_FMUL*//*Label 42*/ GIMT_Encode4(117330),
991 /* 566 */ /*TargetOpcode::G_FMA*//*Label 43*/ GIMT_Encode4(118311), GIMT_Encode4(0),
992 /* 574 */ /*TargetOpcode::G_FDIV*//*Label 44*/ GIMT_Encode4(120402), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
993 /* 626 */ /*TargetOpcode::G_FNEG*//*Label 45*/ GIMT_Encode4(120567),
994 /* 630 */ /*TargetOpcode::G_FPEXT*//*Label 46*/ GIMT_Encode4(123007),
995 /* 634 */ /*TargetOpcode::G_FPTRUNC*//*Label 47*/ GIMT_Encode4(123259),
996 /* 638 */ /*TargetOpcode::G_FPTOSI*//*Label 48*/ GIMT_Encode4(123539),
997 /* 642 */ /*TargetOpcode::G_FPTOUI*//*Label 49*/ GIMT_Encode4(124873),
998 /* 646 */ /*TargetOpcode::G_SITOFP*//*Label 50*/ GIMT_Encode4(126207),
999 /* 650 */ /*TargetOpcode::G_UITOFP*//*Label 51*/ GIMT_Encode4(126859), GIMT_Encode4(0), GIMT_Encode4(0),
1000 /* 662 */ /*TargetOpcode::G_FABS*//*Label 52*/ GIMT_Encode4(127511), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1001 /* 678 */ /*TargetOpcode::G_FMINNUM*//*Label 53*/ GIMT_Encode4(128287),
1002 /* 682 */ /*TargetOpcode::G_FMAXNUM*//*Label 54*/ GIMT_Encode4(128879), GIMT_Encode4(0), GIMT_Encode4(0),
1003 /* 694 */ /*TargetOpcode::G_FMINIMUM*//*Label 55*/ GIMT_Encode4(129471),
1004 /* 698 */ /*TargetOpcode::G_FMAXIMUM*//*Label 56*/ GIMT_Encode4(130205), GIMT_Encode4(0), GIMT_Encode4(0),
1005 /* 710 */ /*TargetOpcode::G_GET_FPENV*//*Label 57*/ GIMT_Encode4(130939),
1006 /* 714 */ /*TargetOpcode::G_SET_FPENV*//*Label 58*/ GIMT_Encode4(130972),
1007 /* 718 */ /*TargetOpcode::G_RESET_FPENV*//*Label 59*/ GIMT_Encode4(131008),
1008 /* 722 */ /*TargetOpcode::G_GET_FPMODE*//*Label 60*/ GIMT_Encode4(131137), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1009 /* 750 */ /*TargetOpcode::G_SMIN*//*Label 61*/ GIMT_Encode4(131170),
1010 /* 754 */ /*TargetOpcode::G_SMAX*//*Label 62*/ GIMT_Encode4(131689),
1011 /* 758 */ /*TargetOpcode::G_UMIN*//*Label 63*/ GIMT_Encode4(132208),
1012 /* 762 */ /*TargetOpcode::G_UMAX*//*Label 64*/ GIMT_Encode4(133105),
1013 /* 766 */ /*TargetOpcode::G_ABS*//*Label 65*/ GIMT_Encode4(134002), GIMT_Encode4(0), GIMT_Encode4(0),
1014 /* 778 */ /*TargetOpcode::G_BR*//*Label 66*/ GIMT_Encode4(134449), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1015 /* 798 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 67*/ GIMT_Encode4(134522),
1016 /* 802 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 68*/ GIMT_Encode4(134802), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1017 /* 830 */ /*TargetOpcode::G_CTLZ*//*Label 69*/ GIMT_Encode4(134859), GIMT_Encode4(0),
1018 /* 838 */ /*TargetOpcode::G_CTLS*//*Label 70*/ GIMT_Encode4(135408),
1019 /* 842 */ /*TargetOpcode::G_CTPOP*//*Label 71*/ GIMT_Encode4(135855),
1020 /* 846 */ /*TargetOpcode::G_BSWAP*//*Label 72*/ GIMT_Encode4(135951),
1021 /* 850 */ /*TargetOpcode::G_BITREVERSE*//*Label 73*/ GIMT_Encode4(136241),
1022 /* 854 */ /*TargetOpcode::G_FCEIL*//*Label 74*/ GIMT_Encode4(136661), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1023 /* 902 */ /*TargetOpcode::G_FSQRT*//*Label 75*/ GIMT_Encode4(137036),
1024 /* 906 */ /*TargetOpcode::G_FFLOOR*//*Label 76*/ GIMT_Encode4(137174),
1025 /* 910 */ /*TargetOpcode::G_FRINT*//*Label 77*/ GIMT_Encode4(137549),
1026 /* 914 */ /*TargetOpcode::G_FNEARBYINT*//*Label 78*/ GIMT_Encode4(137957), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1027 /* 942 */ /*TargetOpcode::G_STRICT_FADD*//*Label 79*/ GIMT_Encode4(138095),
1028 /* 946 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 80*/ GIMT_Encode4(138260),
1029 /* 950 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 81*/ GIMT_Encode4(138425),
1030 /* 954 */ /*TargetOpcode::G_STRICT_FDIV*//*Label 82*/ GIMT_Encode4(138590), GIMT_Encode4(0),
1031 /* 962 */ /*TargetOpcode::G_STRICT_FMA*//*Label 83*/ GIMT_Encode4(138755),
1032 /* 966 */ /*TargetOpcode::G_STRICT_FSQRT*//*Label 84*/ GIMT_Encode4(139940), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1033 /* 1002 */ /*TargetOpcode::G_TRAP*//*Label 85*/ GIMT_Encode4(140078),
1034 /* 1006 */ /*TargetOpcode::G_DEBUGTRAP*//*Label 86*/ GIMT_Encode4(140109), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1035 /* 1046 */ /*TargetOpcode::G_VECREDUCE_ADD*//*Label 87*/ GIMT_Encode4(140196), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1036 /* 1066 */ /*TargetOpcode::G_VECREDUCE_SMAX*//*Label 88*/ GIMT_Encode4(140597),
1037 /* 1070 */ /*TargetOpcode::G_VECREDUCE_SMIN*//*Label 89*/ GIMT_Encode4(140865),
1038 /* 1074 */ /*TargetOpcode::G_VECREDUCE_UMAX*//*Label 90*/ GIMT_Encode4(141142),
1039 /* 1078 */ /*TargetOpcode::G_VECREDUCE_UMIN*//*Label 91*/ GIMT_Encode4(141411),
1040 /* 1082 */ // Label 0: @1082
1041 /* 1082 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 102*/ GIMT_Encode4(13000),
1042 /* 1093 */ /*GILLT_s32*//*Label 93*/ GIMT_Encode4(1145),
1043 /* 1097 */ /*GILLT_s64*//*Label 94*/ GIMT_Encode4(6921), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1044 /* 1117 */ /*GILLT_v8s8*//*Label 95*/ GIMT_Encode4(6968),
1045 /* 1121 */ /*GILLT_v16s8*//*Label 96*/ GIMT_Encode4(7417),
1046 /* 1125 */ /*GILLT_v4s16*//*Label 97*/ GIMT_Encode4(7951),
1047 /* 1129 */ /*GILLT_v8s16*//*Label 98*/ GIMT_Encode4(8400),
1048 /* 1133 */ /*GILLT_v2s32*//*Label 99*/ GIMT_Encode4(9964),
1049 /* 1137 */ /*GILLT_v4s32*//*Label 100*/ GIMT_Encode4(10413),
1050 /* 1141 */ /*GILLT_v2s64*//*Label 101*/ GIMT_Encode4(11977),
1051 /* 1145 */ // Label 93: @1145
1052 /* 1145 */ GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(6920),
1053 /* 1150 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1054 /* 1153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1055 /* 1156 */ GIM_Try, /*On fail goto*//*Label 104*/ GIMT_Encode4(1231), // Rule ID 6251 //
1056 /* 1161 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
1057 /* 1164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1058 /* 1168 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1059 /* 1172 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1060 /* 1176 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1061 /* 1180 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1062 /* 1184 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1063 /* 1189 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1064 /* 1200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1065 /* 1204 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1066 /* 1206 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1067 /* 1206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB),
1068 /* 1209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1069 /* 1211 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1070 /* 1213 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1071 /* 1217 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1072 /* 1220 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1073 /* 1223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1074 /* 1229 */ GIR_RootConstrainSelectedInstOperands,
1075 /* 1230 */ // GIR_Coverage, 6251,
1076 /* 1230 */ GIR_EraseRootFromParent_Done,
1077 /* 1231 */ // Label 104: @1231
1078 /* 1231 */ GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(1306), // Rule ID 6252 //
1079 /* 1236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
1080 /* 1239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1081 /* 1243 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1082 /* 1247 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1083 /* 1251 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1084 /* 1255 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1085 /* 1259 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1086 /* 1264 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1087 /* 1275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1088 /* 1279 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1089 /* 1281 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1090 /* 1281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH),
1091 /* 1284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1092 /* 1286 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1093 /* 1288 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1094 /* 1292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1095 /* 1295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1096 /* 1298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1097 /* 1304 */ GIR_RootConstrainSelectedInstOperands,
1098 /* 1305 */ // GIR_Coverage, 6252,
1099 /* 1305 */ GIR_EraseRootFromParent_Done,
1100 /* 1306 */ // Label 105: @1306
1101 /* 1306 */ GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(1381), // Rule ID 6286 //
1102 /* 1311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1103 /* 1314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1104 /* 1318 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1105 /* 1322 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1106 /* 1326 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1107 /* 1330 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1108 /* 1334 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1109 /* 1339 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1110 /* 1350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1111 /* 1354 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1112 /* 1356 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1113 /* 1356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB),
1114 /* 1359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1115 /* 1361 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1116 /* 1363 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1117 /* 1367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1118 /* 1370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1119 /* 1373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1120 /* 1379 */ GIR_RootConstrainSelectedInstOperands,
1121 /* 1380 */ // GIR_Coverage, 6286,
1122 /* 1380 */ GIR_EraseRootFromParent_Done,
1123 /* 1381 */ // Label 106: @1381
1124 /* 1381 */ GIM_Try, /*On fail goto*//*Label 107*/ GIMT_Encode4(1456), // Rule ID 6287 //
1125 /* 1386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1126 /* 1389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1127 /* 1393 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1128 /* 1397 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1129 /* 1401 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1130 /* 1405 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1131 /* 1409 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1132 /* 1414 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1133 /* 1425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1134 /* 1429 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1135 /* 1431 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1136 /* 1431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH),
1137 /* 1434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1138 /* 1436 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1139 /* 1438 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1140 /* 1442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1141 /* 1445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1142 /* 1448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1143 /* 1454 */ GIR_RootConstrainSelectedInstOperands,
1144 /* 1455 */ // GIR_Coverage, 6287,
1145 /* 1455 */ GIR_EraseRootFromParent_Done,
1146 /* 1456 */ // Label 107: @1456
1147 /* 1456 */ GIM_Try, /*On fail goto*//*Label 108*/ GIMT_Encode4(1531), // Rule ID 2186 //
1148 /* 1461 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
1149 /* 1464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1150 /* 1468 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1151 /* 1472 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1152 /* 1476 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1153 /* 1480 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1154 /* 1484 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1155 /* 1488 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1156 /* 1493 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1157 /* 1504 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1158 /* 1506 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1159 /* 1506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB),
1160 /* 1509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1161 /* 1511 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1162 /* 1513 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1163 /* 1517 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1164 /* 1520 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1165 /* 1523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1166 /* 1529 */ GIR_RootConstrainSelectedInstOperands,
1167 /* 1530 */ // GIR_Coverage, 2186,
1168 /* 1530 */ GIR_EraseRootFromParent_Done,
1169 /* 1531 */ // Label 108: @1531
1170 /* 1531 */ GIM_Try, /*On fail goto*//*Label 109*/ GIMT_Encode4(1606), // Rule ID 2187 //
1171 /* 1536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
1172 /* 1539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1173 /* 1543 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1174 /* 1547 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1175 /* 1551 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1176 /* 1555 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1177 /* 1559 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1178 /* 1563 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1179 /* 1568 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1180 /* 1579 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1181 /* 1581 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1182 /* 1581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH),
1183 /* 1584 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1184 /* 1586 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1185 /* 1588 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1186 /* 1592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1187 /* 1595 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1188 /* 1598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1189 /* 1604 */ GIR_RootConstrainSelectedInstOperands,
1190 /* 1605 */ // GIR_Coverage, 2187,
1191 /* 1605 */ GIR_EraseRootFromParent_Done,
1192 /* 1606 */ // Label 109: @1606
1193 /* 1606 */ GIM_Try, /*On fail goto*//*Label 110*/ GIMT_Encode4(1681), // Rule ID 2425 //
1194 /* 1611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1195 /* 1614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1196 /* 1618 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1197 /* 1622 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1198 /* 1626 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1199 /* 1630 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1200 /* 1634 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1201 /* 1638 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1202 /* 1643 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1203 /* 1654 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1204 /* 1656 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1205 /* 1656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB),
1206 /* 1659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1207 /* 1661 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1208 /* 1663 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1209 /* 1667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1210 /* 1670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1211 /* 1673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1212 /* 1679 */ GIR_RootConstrainSelectedInstOperands,
1213 /* 1680 */ // GIR_Coverage, 2425,
1214 /* 1680 */ GIR_EraseRootFromParent_Done,
1215 /* 1681 */ // Label 110: @1681
1216 /* 1681 */ GIM_Try, /*On fail goto*//*Label 111*/ GIMT_Encode4(1756), // Rule ID 2426 //
1217 /* 1686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1218 /* 1689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1219 /* 1693 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1220 /* 1697 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1221 /* 1701 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1222 /* 1705 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1223 /* 1709 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1224 /* 1713 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1225 /* 1718 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1226 /* 1729 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1227 /* 1731 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1228 /* 1731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH),
1229 /* 1734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1230 /* 1736 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1231 /* 1738 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1232 /* 1742 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1233 /* 1745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1234 /* 1748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1235 /* 1754 */ GIR_RootConstrainSelectedInstOperands,
1236 /* 1755 */ // GIR_Coverage, 2426,
1237 /* 1755 */ GIR_EraseRootFromParent_Done,
1238 /* 1756 */ // Label 111: @1756
1239 /* 1756 */ GIM_Try, /*On fail goto*//*Label 112*/ GIMT_Encode4(1884), // Rule ID 6262 //
1240 /* 1761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1241 /* 1764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1242 /* 1768 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1243 /* 1772 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1244 /* 1776 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1245 /* 1780 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1246 /* 1784 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1247 /* 1788 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1248 /* 1792 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1249 /* 1796 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1250 /* 1800 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
1251 /* 1804 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1252 /* 1808 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1253 /* 1812 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1254 /* 1817 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
1255 /* 1821 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1256 /* 1825 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
1257 /* 1829 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1258 /* 1833 */ // MIs[4] Rm
1259 /* 1833 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1260 /* 1838 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
1261 /* 1842 */ // MIs[1] Operand 2
1262 /* 1842 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1263 /* 1853 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1264 /* 1857 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1265 /* 1859 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1266 /* 1859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1267 /* 1862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1268 /* 1864 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1269 /* 1866 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1270 /* 1870 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1271 /* 1873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1272 /* 1876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1273 /* 1882 */ GIR_RootConstrainSelectedInstOperands,
1274 /* 1883 */ // GIR_Coverage, 6262,
1275 /* 1883 */ GIR_EraseRootFromParent_Done,
1276 /* 1884 */ // Label 112: @1884
1277 /* 1884 */ GIM_Try, /*On fail goto*//*Label 113*/ GIMT_Encode4(2012), // Rule ID 6263 //
1278 /* 1889 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1279 /* 1892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1280 /* 1896 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1281 /* 1900 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1282 /* 1904 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1283 /* 1908 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1284 /* 1912 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1285 /* 1916 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1286 /* 1920 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1287 /* 1924 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1288 /* 1928 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
1289 /* 1932 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1290 /* 1936 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1291 /* 1940 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1292 /* 1945 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8,
1293 /* 1949 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1294 /* 1953 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
1295 /* 1957 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1296 /* 1961 */ // MIs[4] Rm
1297 /* 1961 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1298 /* 1966 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
1299 /* 1970 */ // MIs[1] Operand 2
1300 /* 1970 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1301 /* 1981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1302 /* 1985 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1303 /* 1987 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1304 /* 1987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1305 /* 1990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1306 /* 1992 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1307 /* 1994 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1308 /* 1998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1309 /* 2001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1310 /* 2004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1311 /* 2010 */ GIR_RootConstrainSelectedInstOperands,
1312 /* 2011 */ // GIR_Coverage, 6263,
1313 /* 2011 */ GIR_EraseRootFromParent_Done,
1314 /* 2012 */ // Label 113: @2012
1315 /* 2012 */ GIM_Try, /*On fail goto*//*Label 114*/ GIMT_Encode4(2140), // Rule ID 2292 //
1316 /* 2017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1317 /* 2020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1318 /* 2024 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1319 /* 2028 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1320 /* 2032 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1321 /* 2036 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1322 /* 2040 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1323 /* 2044 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1324 /* 2048 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1325 /* 2052 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1326 /* 2056 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1327 /* 2060 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
1328 /* 2064 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1329 /* 2068 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1330 /* 2072 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1331 /* 2077 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
1332 /* 2081 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1333 /* 2085 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
1334 /* 2089 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1335 /* 2093 */ // MIs[4] Rm
1336 /* 2093 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1337 /* 2098 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
1338 /* 2102 */ // MIs[1] Operand 2
1339 /* 2102 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1340 /* 2113 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1341 /* 2115 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1342 /* 2115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1343 /* 2118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1344 /* 2120 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1345 /* 2122 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1346 /* 2126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1347 /* 2129 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1348 /* 2132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1349 /* 2138 */ GIR_RootConstrainSelectedInstOperands,
1350 /* 2139 */ // GIR_Coverage, 2292,
1351 /* 2139 */ GIR_EraseRootFromParent_Done,
1352 /* 2140 */ // Label 114: @2140
1353 /* 2140 */ GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(2268), // Rule ID 6261 //
1354 /* 2145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1355 /* 2148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1356 /* 2152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1357 /* 2156 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1358 /* 2160 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1359 /* 2164 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1360 /* 2168 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1361 /* 2172 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1362 /* 2176 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1363 /* 2180 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1364 /* 2184 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1365 /* 2188 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
1366 /* 2192 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1367 /* 2196 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1368 /* 2200 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1369 /* 2205 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8,
1370 /* 2209 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1371 /* 2213 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
1372 /* 2217 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1373 /* 2221 */ // MIs[4] Rm
1374 /* 2221 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1375 /* 2226 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
1376 /* 2230 */ // MIs[1] Operand 2
1377 /* 2230 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1378 /* 2241 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1379 /* 2243 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1380 /* 2243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1381 /* 2246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1382 /* 2248 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1383 /* 2250 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1384 /* 2254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1385 /* 2257 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1386 /* 2260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1387 /* 2266 */ GIR_RootConstrainSelectedInstOperands,
1388 /* 2267 */ // GIR_Coverage, 6261,
1389 /* 2267 */ GIR_EraseRootFromParent_Done,
1390 /* 2268 */ // Label 115: @2268
1391 /* 2268 */ GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(2378), // Rule ID 5964 //
1392 /* 2273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1393 /* 2276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1394 /* 2280 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1395 /* 2284 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1396 /* 2288 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1397 /* 2292 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1398 /* 2296 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1399 /* 2300 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1400 /* 2304 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1401 /* 2308 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1402 /* 2312 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1403 /* 2317 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1404 /* 2321 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1405 /* 2325 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1406 /* 2329 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1407 /* 2333 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1408 /* 2337 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1409 /* 2342 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1410 /* 2346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1411 /* 2350 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1412 /* 2352 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1413 /* 2352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT),
1414 /* 2355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1415 /* 2357 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1416 /* 2361 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1417 /* 2365 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1418 /* 2367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1419 /* 2370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1420 /* 2376 */ GIR_RootConstrainSelectedInstOperands,
1421 /* 2377 */ // GIR_Coverage, 5964,
1422 /* 2377 */ GIR_EraseRootFromParent_Done,
1423 /* 2378 */ // Label 116: @2378
1424 /* 2378 */ GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(2488), // Rule ID 6001 //
1425 /* 2383 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1426 /* 2386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1427 /* 2390 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1428 /* 2394 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1429 /* 2398 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1430 /* 2402 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1431 /* 2406 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1432 /* 2410 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1433 /* 2414 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1434 /* 2418 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1435 /* 2422 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1436 /* 2427 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1437 /* 2431 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1438 /* 2435 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1439 /* 2439 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1440 /* 2443 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1441 /* 2447 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1442 /* 2452 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1443 /* 2456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1444 /* 2460 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1445 /* 2462 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1446 /* 2462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT),
1447 /* 2465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1448 /* 2467 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1449 /* 2471 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1450 /* 2475 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1451 /* 2477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1452 /* 2480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1453 /* 2486 */ GIR_RootConstrainSelectedInstOperands,
1454 /* 2487 */ // GIR_Coverage, 6001,
1455 /* 2487 */ GIR_EraseRootFromParent_Done,
1456 /* 2488 */ // Label 117: @2488
1457 /* 2488 */ GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(2598), // Rule ID 191 //
1458 /* 2493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1459 /* 2496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1460 /* 2500 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1461 /* 2504 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1462 /* 2508 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1463 /* 2512 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1464 /* 2516 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1465 /* 2520 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1466 /* 2524 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1467 /* 2528 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1468 /* 2532 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1469 /* 2536 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1470 /* 2541 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1471 /* 2545 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1472 /* 2549 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1473 /* 2553 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1474 /* 2557 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1475 /* 2561 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1476 /* 2566 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1477 /* 2570 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1478 /* 2572 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1479 /* 2572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT),
1480 /* 2575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1481 /* 2577 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1482 /* 2581 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1483 /* 2585 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1484 /* 2587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1485 /* 2590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1486 /* 2596 */ GIR_RootConstrainSelectedInstOperands,
1487 /* 2597 */ // GIR_Coverage, 191,
1488 /* 2597 */ GIR_EraseRootFromParent_Done,
1489 /* 2598 */ // Label 118: @2598
1490 /* 2598 */ GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(2708), // Rule ID 520 //
1491 /* 2603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1492 /* 2606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1493 /* 2610 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1494 /* 2614 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1495 /* 2618 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1496 /* 2622 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1497 /* 2626 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1498 /* 2630 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1499 /* 2634 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1500 /* 2638 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1501 /* 2642 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1502 /* 2646 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1503 /* 2651 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1504 /* 2655 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1505 /* 2659 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1506 /* 2663 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1507 /* 2667 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1508 /* 2671 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1509 /* 2676 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1510 /* 2680 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1511 /* 2682 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1512 /* 2682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT),
1513 /* 2685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1514 /* 2687 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1515 /* 2691 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1516 /* 2695 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1517 /* 2697 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1518 /* 2700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1519 /* 2706 */ GIR_RootConstrainSelectedInstOperands,
1520 /* 2707 */ // GIR_Coverage, 520,
1521 /* 2707 */ GIR_EraseRootFromParent_Done,
1522 /* 2708 */ // Label 119: @2708
1523 /* 2708 */ GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(2821), // Rule ID 5963 //
1524 /* 2713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1525 /* 2716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1526 /* 2720 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1527 /* 2724 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1528 /* 2728 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1529 /* 2732 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1530 /* 2736 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1531 /* 2740 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1532 /* 2744 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1533 /* 2748 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1534 /* 2752 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1535 /* 2757 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1536 /* 2761 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1537 /* 2765 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1538 /* 2769 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1539 /* 2773 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1540 /* 2778 */ // MIs[3] Operand 2
1541 /* 2778 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1542 /* 2789 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1543 /* 2793 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1544 /* 2795 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1545 /* 2795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
1546 /* 2798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1547 /* 2800 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
1548 /* 2804 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1549 /* 2808 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1550 /* 2810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1551 /* 2813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1552 /* 2819 */ GIR_RootConstrainSelectedInstOperands,
1553 /* 2820 */ // GIR_Coverage, 5963,
1554 /* 2820 */ GIR_EraseRootFromParent_Done,
1555 /* 2821 */ // Label 120: @2821
1556 /* 2821 */ GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(2934), // Rule ID 6000 //
1557 /* 2826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1558 /* 2829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1559 /* 2833 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1560 /* 2837 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1561 /* 2841 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1562 /* 2845 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1563 /* 2849 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1564 /* 2853 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1565 /* 2857 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1566 /* 2861 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1567 /* 2865 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1568 /* 2870 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1569 /* 2874 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1570 /* 2878 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1571 /* 2882 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1572 /* 2886 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1573 /* 2891 */ // MIs[3] Operand 2
1574 /* 2891 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1575 /* 2902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1576 /* 2906 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1577 /* 2908 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1578 /* 2908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
1579 /* 2911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1580 /* 2913 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
1581 /* 2917 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1582 /* 2921 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1583 /* 2923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1584 /* 2926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1585 /* 2932 */ GIR_RootConstrainSelectedInstOperands,
1586 /* 2933 */ // GIR_Coverage, 6000,
1587 /* 2933 */ GIR_EraseRootFromParent_Done,
1588 /* 2934 */ // Label 121: @2934
1589 /* 2934 */ GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(3047), // Rule ID 5962 //
1590 /* 2939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1591 /* 2942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1592 /* 2946 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1593 /* 2950 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1594 /* 2954 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1595 /* 2958 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1596 /* 2962 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1597 /* 2966 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1598 /* 2970 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1599 /* 2974 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1600 /* 2979 */ // MIs[2] Operand 2
1601 /* 2979 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1602 /* 2990 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1603 /* 2994 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1604 /* 2998 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1605 /* 3002 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1606 /* 3006 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1607 /* 3011 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1608 /* 3015 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1609 /* 3019 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1610 /* 3021 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1611 /* 3021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
1612 /* 3024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1613 /* 3026 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1614 /* 3030 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1615 /* 3034 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1616 /* 3036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1617 /* 3039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1618 /* 3045 */ GIR_RootConstrainSelectedInstOperands,
1619 /* 3046 */ // GIR_Coverage, 5962,
1620 /* 3046 */ GIR_EraseRootFromParent_Done,
1621 /* 3047 */ // Label 122: @3047
1622 /* 3047 */ GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(3160), // Rule ID 5999 //
1623 /* 3052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1624 /* 3055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1625 /* 3059 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1626 /* 3063 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1627 /* 3067 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1628 /* 3071 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1629 /* 3075 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1630 /* 3079 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1631 /* 3083 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1632 /* 3087 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1633 /* 3092 */ // MIs[2] Operand 2
1634 /* 3092 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1635 /* 3103 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1636 /* 3107 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1637 /* 3111 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1638 /* 3115 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1639 /* 3119 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1640 /* 3124 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1641 /* 3128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1642 /* 3132 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1643 /* 3134 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1644 /* 3134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
1645 /* 3137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1646 /* 3139 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1647 /* 3143 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1648 /* 3147 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1649 /* 3149 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1650 /* 3152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1651 /* 3158 */ GIR_RootConstrainSelectedInstOperands,
1652 /* 3159 */ // GIR_Coverage, 5999,
1653 /* 3159 */ GIR_EraseRootFromParent_Done,
1654 /* 3160 */ // Label 123: @3160
1655 /* 3160 */ GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(3273), // Rule ID 190 //
1656 /* 3165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1657 /* 3168 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1658 /* 3172 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1659 /* 3176 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1660 /* 3180 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1661 /* 3184 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1662 /* 3188 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1663 /* 3192 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1664 /* 3196 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1665 /* 3200 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1666 /* 3204 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1667 /* 3208 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1668 /* 3213 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1669 /* 3217 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1670 /* 3221 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1671 /* 3225 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1672 /* 3229 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1673 /* 3234 */ // MIs[3] Operand 2
1674 /* 3234 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1675 /* 3245 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1676 /* 3247 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLATB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1677 /* 3247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB),
1678 /* 3250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1679 /* 3252 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1680 /* 3256 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1681 /* 3260 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1682 /* 3262 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1683 /* 3265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1684 /* 3271 */ GIR_RootConstrainSelectedInstOperands,
1685 /* 3272 */ // GIR_Coverage, 190,
1686 /* 3272 */ GIR_EraseRootFromParent_Done,
1687 /* 3273 */ // Label 124: @3273
1688 /* 3273 */ GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(3386), // Rule ID 519 //
1689 /* 3278 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1690 /* 3281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1691 /* 3285 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1692 /* 3289 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1693 /* 3293 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1694 /* 3297 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1695 /* 3301 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1696 /* 3305 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1697 /* 3309 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1698 /* 3313 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1699 /* 3317 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1700 /* 3321 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1701 /* 3326 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1702 /* 3330 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1703 /* 3334 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1704 /* 3338 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1705 /* 3342 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1706 /* 3347 */ // MIs[3] Operand 2
1707 /* 3347 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1708 /* 3358 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1709 /* 3360 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLATB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1710 /* 3360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB),
1711 /* 3363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1712 /* 3365 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1713 /* 3369 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1714 /* 3373 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1715 /* 3375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1716 /* 3378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1717 /* 3384 */ GIR_RootConstrainSelectedInstOperands,
1718 /* 3385 */ // GIR_Coverage, 519,
1719 /* 3385 */ GIR_EraseRootFromParent_Done,
1720 /* 3386 */ // Label 125: @3386
1721 /* 3386 */ GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(3499), // Rule ID 189 //
1722 /* 3391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1723 /* 3394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1724 /* 3398 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1725 /* 3402 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1726 /* 3406 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1727 /* 3410 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1728 /* 3414 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1729 /* 3418 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1730 /* 3422 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1731 /* 3426 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1732 /* 3430 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1733 /* 3435 */ // MIs[2] Operand 2
1734 /* 3435 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1735 /* 3446 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1736 /* 3450 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1737 /* 3454 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1738 /* 3458 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1739 /* 3462 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1740 /* 3467 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1741 /* 3471 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1742 /* 3473 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1743 /* 3473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
1744 /* 3476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1745 /* 3478 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1746 /* 3482 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1747 /* 3486 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1748 /* 3488 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1749 /* 3491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1750 /* 3497 */ GIR_RootConstrainSelectedInstOperands,
1751 /* 3498 */ // GIR_Coverage, 189,
1752 /* 3498 */ GIR_EraseRootFromParent_Done,
1753 /* 3499 */ // Label 126: @3499
1754 /* 3499 */ GIM_Try, /*On fail goto*//*Label 127*/ GIMT_Encode4(3612), // Rule ID 518 //
1755 /* 3504 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1756 /* 3507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1757 /* 3511 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1758 /* 3515 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1759 /* 3519 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1760 /* 3523 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1761 /* 3527 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1762 /* 3531 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1763 /* 3535 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1764 /* 3539 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1765 /* 3543 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1766 /* 3548 */ // MIs[2] Operand 2
1767 /* 3548 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1768 /* 3559 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1769 /* 3563 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1770 /* 3567 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1771 /* 3571 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1772 /* 3575 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1773 /* 3580 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1774 /* 3584 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1775 /* 3586 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1776 /* 3586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
1777 /* 3589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1778 /* 3591 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1779 /* 3595 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1780 /* 3599 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1781 /* 3601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1782 /* 3604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1783 /* 3610 */ GIR_RootConstrainSelectedInstOperands,
1784 /* 3611 */ // GIR_Coverage, 518,
1785 /* 3611 */ GIR_EraseRootFromParent_Done,
1786 /* 3612 */ // Label 127: @3612
1787 /* 3612 */ GIM_Try, /*On fail goto*//*Label 128*/ GIMT_Encode4(3703), // Rule ID 6260 //
1788 /* 3617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1789 /* 3620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1790 /* 3624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1791 /* 3628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1792 /* 3632 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1793 /* 3636 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1794 /* 3640 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR),
1795 /* 3644 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1796 /* 3648 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1797 /* 3652 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1798 /* 3657 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
1799 /* 3661 */ // MIs[1] Operand 2
1800 /* 3661 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1801 /* 3672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1802 /* 3676 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
1803 /* 3678 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1804 /* 3678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1805 /* 3681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1806 /* 3683 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1807 /* 3685 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1808 /* 3689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1809 /* 3692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1810 /* 3695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1811 /* 3701 */ GIR_RootConstrainSelectedInstOperands,
1812 /* 3702 */ // GIR_Coverage, 6260,
1813 /* 3702 */ GIR_EraseRootFromParent_Done,
1814 /* 3703 */ // Label 128: @3703
1815 /* 3703 */ GIM_Try, /*On fail goto*//*Label 129*/ GIMT_Encode4(3794), // Rule ID 2291 //
1816 /* 3708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1817 /* 3711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1818 /* 3715 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1819 /* 3719 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1820 /* 3723 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1821 /* 3727 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1822 /* 3731 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1823 /* 3735 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR),
1824 /* 3739 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1825 /* 3743 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1826 /* 3747 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1827 /* 3752 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
1828 /* 3756 */ // MIs[1] Operand 2
1829 /* 3756 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1830 /* 3767 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
1831 /* 3769 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1832 /* 3769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1833 /* 3772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1834 /* 3774 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1835 /* 3776 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1836 /* 3780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1837 /* 3783 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1838 /* 3786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1839 /* 3792 */ GIR_RootConstrainSelectedInstOperands,
1840 /* 3793 */ // GIR_Coverage, 2291,
1841 /* 3793 */ GIR_EraseRootFromParent_Done,
1842 /* 3794 */ // Label 129: @3794
1843 /* 3794 */ GIM_Try, /*On fail goto*//*Label 130*/ GIMT_Encode4(3910), // Rule ID 5961 //
1844 /* 3799 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1845 /* 3802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1846 /* 3806 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1847 /* 3810 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1848 /* 3814 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1849 /* 3818 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1850 /* 3822 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1851 /* 3826 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1852 /* 3830 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1853 /* 3834 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1854 /* 3839 */ // MIs[2] Operand 2
1855 /* 3839 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1856 /* 3850 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1857 /* 3854 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1858 /* 3858 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1859 /* 3862 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1860 /* 3867 */ // MIs[3] Operand 2
1861 /* 3867 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1862 /* 3878 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1863 /* 3882 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1864 /* 3884 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1865 /* 3884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB),
1866 /* 3887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1867 /* 3889 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1868 /* 3893 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1869 /* 3897 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1870 /* 3899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1871 /* 3902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1872 /* 3908 */ GIR_RootConstrainSelectedInstOperands,
1873 /* 3909 */ // GIR_Coverage, 5961,
1874 /* 3909 */ GIR_EraseRootFromParent_Done,
1875 /* 3910 */ // Label 130: @3910
1876 /* 3910 */ GIM_Try, /*On fail goto*//*Label 131*/ GIMT_Encode4(4026), // Rule ID 5998 //
1877 /* 3915 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1878 /* 3918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1879 /* 3922 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1880 /* 3926 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1881 /* 3930 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1882 /* 3934 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1883 /* 3938 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1884 /* 3942 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1885 /* 3946 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1886 /* 3950 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1887 /* 3955 */ // MIs[2] Operand 2
1888 /* 3955 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1889 /* 3966 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1890 /* 3970 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1891 /* 3974 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1892 /* 3978 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1893 /* 3983 */ // MIs[3] Operand 2
1894 /* 3983 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1895 /* 3994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1896 /* 3998 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1897 /* 4000 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1898 /* 4000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB),
1899 /* 4003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1900 /* 4005 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1901 /* 4009 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1902 /* 4013 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1903 /* 4015 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1904 /* 4018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1905 /* 4024 */ GIR_RootConstrainSelectedInstOperands,
1906 /* 4025 */ // GIR_Coverage, 5998,
1907 /* 4025 */ GIR_EraseRootFromParent_Done,
1908 /* 4026 */ // Label 131: @4026
1909 /* 4026 */ GIM_Try, /*On fail goto*//*Label 132*/ GIMT_Encode4(4142), // Rule ID 188 //
1910 /* 4031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1911 /* 4034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1912 /* 4038 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1913 /* 4042 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1914 /* 4046 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1915 /* 4050 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1916 /* 4054 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1917 /* 4058 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1918 /* 4062 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1919 /* 4066 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1920 /* 4070 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1921 /* 4075 */ // MIs[2] Operand 2
1922 /* 4075 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1923 /* 4086 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1924 /* 4090 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1925 /* 4094 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1926 /* 4098 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1927 /* 4103 */ // MIs[3] Operand 2
1928 /* 4103 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1929 /* 4114 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1930 /* 4116 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1931 /* 4116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB),
1932 /* 4119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1933 /* 4121 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1934 /* 4125 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1935 /* 4129 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1936 /* 4131 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1937 /* 4134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1938 /* 4140 */ GIR_RootConstrainSelectedInstOperands,
1939 /* 4141 */ // GIR_Coverage, 188,
1940 /* 4141 */ GIR_EraseRootFromParent_Done,
1941 /* 4142 */ // Label 132: @4142
1942 /* 4142 */ GIM_Try, /*On fail goto*//*Label 133*/ GIMT_Encode4(4258), // Rule ID 517 //
1943 /* 4147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1944 /* 4150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1945 /* 4154 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1946 /* 4158 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1947 /* 4162 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1948 /* 4166 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1949 /* 4170 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1950 /* 4174 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1951 /* 4178 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1952 /* 4182 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1953 /* 4186 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1954 /* 4191 */ // MIs[2] Operand 2
1955 /* 4191 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1956 /* 4202 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1957 /* 4206 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1958 /* 4210 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1959 /* 4214 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1960 /* 4219 */ // MIs[3] Operand 2
1961 /* 4219 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1962 /* 4230 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1963 /* 4232 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1964 /* 4232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB),
1965 /* 4235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1966 /* 4237 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1967 /* 4241 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1968 /* 4245 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1969 /* 4247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1970 /* 4250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1971 /* 4256 */ GIR_RootConstrainSelectedInstOperands,
1972 /* 4257 */ // GIR_Coverage, 517,
1973 /* 4257 */ GIR_EraseRootFromParent_Done,
1974 /* 4258 */ // Label 133: @4258
1975 /* 4258 */ GIM_Try, /*On fail goto*//*Label 134*/ GIMT_Encode4(4346), // Rule ID 3625 //
1976 /* 4263 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
1977 /* 4266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
1978 /* 4270 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1979 /* 4274 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
1980 /* 4278 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1981 /* 4282 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1982 /* 4286 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
1983 /* 4290 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1984 /* 4294 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1985 /* 4298 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
1986 /* 4303 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
1987 /* 4308 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
1988 /* 4312 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
1989 /* 4314 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
1990 /* 4314 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32),
1991 /* 4317 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
1992 /* 4319 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3
1993 /* 4321 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
1994 /* 4325 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
1995 /* 4329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1996 /* 4332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1997 /* 4338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1998 /* 4344 */ GIR_RootConstrainSelectedInstOperands,
1999 /* 4345 */ // GIR_Coverage, 3625,
2000 /* 4345 */ GIR_EraseRootFromParent_Done,
2001 /* 4346 */ // Label 134: @4346
2002 /* 4346 */ GIM_Try, /*On fail goto*//*Label 135*/ GIMT_Encode4(4434), // Rule ID 3626 //
2003 /* 4351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2004 /* 4354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2005 /* 4358 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2006 /* 4362 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2007 /* 4366 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2008 /* 4370 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2009 /* 4374 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2010 /* 4378 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
2011 /* 4382 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
2012 /* 4386 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2013 /* 4391 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2014 /* 4396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2015 /* 4400 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2016 /* 4402 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
2017 /* 4402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16),
2018 /* 4405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2019 /* 4407 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3
2020 /* 4409 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2021 /* 4413 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2022 /* 4417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2023 /* 4420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2024 /* 4426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2025 /* 4432 */ GIR_RootConstrainSelectedInstOperands,
2026 /* 4433 */ // GIR_Coverage, 3626,
2027 /* 4433 */ GIR_EraseRootFromParent_Done,
2028 /* 4434 */ // Label 135: @4434
2029 /* 4434 */ GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(4522), // Rule ID 3629 //
2030 /* 4439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2031 /* 4442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2032 /* 4446 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2033 /* 4450 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2034 /* 4454 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2035 /* 4458 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2036 /* 4462 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2037 /* 4466 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
2038 /* 4470 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
2039 /* 4474 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2040 /* 4479 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2041 /* 4484 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2042 /* 4488 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2043 /* 4490 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
2044 /* 4490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8),
2045 /* 4493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2046 /* 4495 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3
2047 /* 4497 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2048 /* 4501 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2049 /* 4505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2050 /* 4508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2051 /* 4514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2052 /* 4520 */ GIR_RootConstrainSelectedInstOperands,
2053 /* 4521 */ // GIR_Coverage, 3629,
2054 /* 4521 */ GIR_EraseRootFromParent_Done,
2055 /* 4522 */ // Label 136: @4522
2056 /* 4522 */ GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(4610), // Rule ID 6558 //
2057 /* 4527 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2058 /* 4530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2059 /* 4534 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2060 /* 4538 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2061 /* 4542 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2062 /* 4546 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2063 /* 4550 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2064 /* 4554 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2065 /* 4558 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2066 /* 4562 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2067 /* 4566 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2068 /* 4571 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2069 /* 4576 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2070 /* 4578 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2))) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
2071 /* 4578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32),
2072 /* 4581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2073 /* 4583 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3
2074 /* 4585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2075 /* 4589 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2076 /* 4593 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2077 /* 4596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2078 /* 4602 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2079 /* 4608 */ GIR_RootConstrainSelectedInstOperands,
2080 /* 4609 */ // GIR_Coverage, 6558,
2081 /* 4609 */ GIR_EraseRootFromParent_Done,
2082 /* 4610 */ // Label 137: @4610
2083 /* 4610 */ GIM_Try, /*On fail goto*//*Label 138*/ GIMT_Encode4(4698), // Rule ID 6559 //
2084 /* 4615 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2085 /* 4618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2086 /* 4622 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2087 /* 4626 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2088 /* 4630 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2089 /* 4634 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2090 /* 4638 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2091 /* 4642 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2092 /* 4646 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
2093 /* 4650 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
2094 /* 4654 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2095 /* 4659 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2096 /* 4664 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2097 /* 4666 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2))) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
2098 /* 4666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16),
2099 /* 4669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2100 /* 4671 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3
2101 /* 4673 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2102 /* 4677 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2103 /* 4681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2104 /* 4684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2105 /* 4690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2106 /* 4696 */ GIR_RootConstrainSelectedInstOperands,
2107 /* 4697 */ // GIR_Coverage, 6559,
2108 /* 4697 */ GIR_EraseRootFromParent_Done,
2109 /* 4698 */ // Label 138: @4698
2110 /* 4698 */ GIM_Try, /*On fail goto*//*Label 139*/ GIMT_Encode4(4786), // Rule ID 6562 //
2111 /* 4703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2112 /* 4706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2113 /* 4710 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2114 /* 4714 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2115 /* 4718 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2116 /* 4722 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2117 /* 4726 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2118 /* 4730 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2119 /* 4734 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
2120 /* 4738 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
2121 /* 4742 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2122 /* 4747 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2123 /* 4752 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2124 /* 4754 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2))) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
2125 /* 4754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8),
2126 /* 4757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2127 /* 4759 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3
2128 /* 4761 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2129 /* 4765 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2130 /* 4769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2131 /* 4772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2132 /* 4778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2133 /* 4784 */ GIR_RootConstrainSelectedInstOperands,
2134 /* 4785 */ // GIR_Coverage, 6562,
2135 /* 4785 */ GIR_EraseRootFromParent_Done,
2136 /* 4786 */ // Label 139: @4786
2137 /* 4786 */ GIM_Try, /*On fail goto*//*Label 140*/ GIMT_Encode4(4843), // Rule ID 71 //
2138 /* 4791 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
2139 /* 4794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2140 /* 4798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2141 /* 4802 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2142 /* 4806 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2143 /* 4810 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
2144 /* 4814 */ // MIs[1] Operand 1
2145 /* 4814 */ // No operand predicates
2146 /* 4814 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2147 /* 4816 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
2148 /* 4816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDri),
2149 /* 4819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2150 /* 4821 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2151 /* 4823 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2152 /* 4826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2153 /* 4829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2154 /* 4835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2155 /* 4841 */ GIR_RootConstrainSelectedInstOperands,
2156 /* 4842 */ // GIR_Coverage, 71,
2157 /* 4842 */ GIR_EraseRootFromParent_Done,
2158 /* 4843 */ // Label 140: @4843
2159 /* 4843 */ GIM_Try, /*On fail goto*//*Label 141*/ GIMT_Encode4(4900), // Rule ID 302 //
2160 /* 4848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
2161 /* 4851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2162 /* 4855 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2163 /* 4859 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2164 /* 4863 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2165 /* 4867 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
2166 /* 4871 */ // MIs[1] Operand 1
2167 /* 4871 */ // No operand predicates
2168 /* 4871 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2169 /* 4873 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm3) => (tADDi3:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm3)
2170 /* 4873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi3),
2171 /* 4876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2172 /* 4878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
2173 /* 4884 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
2174 /* 4886 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm3
2175 /* 4889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2176 /* 4892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2177 /* 4898 */ GIR_RootConstrainSelectedInstOperands,
2178 /* 4899 */ // GIR_Coverage, 302,
2179 /* 4899 */ GIR_EraseRootFromParent_Done,
2180 /* 4900 */ // Label 141: @4900
2181 /* 4900 */ GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(4957), // Rule ID 303 //
2182 /* 4905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
2183 /* 4908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2184 /* 4912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2185 /* 4916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2186 /* 4920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2187 /* 4924 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr),
2188 /* 4928 */ // MIs[1] Operand 1
2189 /* 4928 */ // No operand predicates
2190 /* 4928 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2191 /* 4930 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8) => (tADDi8:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm8)
2192 /* 4930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi8),
2193 /* 4933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
2194 /* 4935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
2195 /* 4941 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2196 /* 4943 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8
2197 /* 4946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2198 /* 4949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2199 /* 4955 */ GIR_RootConstrainSelectedInstOperands,
2200 /* 4956 */ // GIR_Coverage, 303,
2201 /* 4956 */ GIR_EraseRootFromParent_Done,
2202 /* 4957 */ // Label 142: @4957
2203 /* 4957 */ GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(5014), // Rule ID 406 //
2204 /* 4962 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
2205 /* 4965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2206 /* 4969 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2207 /* 4973 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2208 /* 4977 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2209 /* 4981 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
2210 /* 4985 */ // MIs[1] Operand 1
2211 /* 4985 */ // No operand predicates
2212 /* 4985 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2213 /* 4987 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
2214 /* 4987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri),
2215 /* 4990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2216 /* 4992 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2217 /* 4994 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2218 /* 4997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2219 /* 5000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2220 /* 5006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2221 /* 5012 */ GIR_RootConstrainSelectedInstOperands,
2222 /* 5013 */ // GIR_Coverage, 406,
2223 /* 5013 */ GIR_EraseRootFromParent_Done,
2224 /* 5014 */ // Label 143: @5014
2225 /* 5014 */ GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(5065), // Rule ID 407 //
2226 /* 5019 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
2227 /* 5022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2228 /* 5026 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2229 /* 5030 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2230 /* 5034 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2231 /* 5038 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095),
2232 /* 5042 */ // MIs[1] Operand 1
2233 /* 5042 */ // No operand predicates
2234 /* 5042 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2235 /* 5044 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
2236 /* 5044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri12),
2237 /* 5047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2238 /* 5049 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2239 /* 5051 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2240 /* 5054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2241 /* 5057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2242 /* 5063 */ GIR_RootConstrainSelectedInstOperands,
2243 /* 5064 */ // GIR_Coverage, 407,
2244 /* 5064 */ GIR_EraseRootFromParent_Done,
2245 /* 5065 */ // Label 144: @5065
2246 /* 5065 */ GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(5141), // Rule ID 170 //
2247 /* 5070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps),
2248 /* 5073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2249 /* 5077 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2250 /* 5081 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2251 /* 5085 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2252 /* 5089 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2253 /* 5093 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2254 /* 5098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2255 /* 5103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2256 /* 5107 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2257 /* 5109 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2258 /* 5109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA),
2259 /* 5112 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2260 /* 5114 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2261 /* 5118 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2262 /* 5122 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2263 /* 5124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2264 /* 5127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2265 /* 5133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2266 /* 5139 */ GIR_RootConstrainSelectedInstOperands,
2267 /* 5140 */ // GIR_Coverage, 170,
2268 /* 5140 */ GIR_EraseRootFromParent_Done,
2269 /* 5141 */ // Label 145: @5141
2270 /* 5141 */ GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(5217), // Rule ID 171 //
2271 /* 5146 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6),
2272 /* 5149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2273 /* 5153 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2274 /* 5157 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2275 /* 5161 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2276 /* 5165 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2277 /* 5169 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2278 /* 5174 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2279 /* 5179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2280 /* 5183 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2281 /* 5185 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2282 /* 5185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5),
2283 /* 5188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2284 /* 5190 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2285 /* 5194 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2286 /* 5198 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2287 /* 5200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2288 /* 5203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2289 /* 5209 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2290 /* 5215 */ GIR_RootConstrainSelectedInstOperands,
2291 /* 5216 */ // GIR_Coverage, 171,
2292 /* 5216 */ GIR_EraseRootFromParent_Done,
2293 /* 5217 */ // Label 146: @5217
2294 /* 5217 */ GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(5287), // Rule ID 502 //
2295 /* 5222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps),
2296 /* 5225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2297 /* 5229 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2298 /* 5233 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2299 /* 5237 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2300 /* 5241 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2301 /* 5245 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2302 /* 5250 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2303 /* 5255 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2304 /* 5259 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2305 /* 5261 */ // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2306 /* 5261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA),
2307 /* 5264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2308 /* 5266 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2309 /* 5270 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2310 /* 5274 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2311 /* 5276 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2312 /* 5279 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2313 /* 5285 */ GIR_RootConstrainSelectedInstOperands,
2314 /* 5286 */ // GIR_Coverage, 502,
2315 /* 5286 */ GIR_EraseRootFromParent_Done,
2316 /* 5287 */ // Label 147: @5287
2317 /* 5287 */ GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(5358), // Rule ID 6253 //
2318 /* 5292 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
2319 /* 5295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2320 /* 5299 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2321 /* 5303 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2322 /* 5307 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2323 /* 5311 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2324 /* 5316 */ // MIs[1] Operand 2
2325 /* 5316 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2326 /* 5327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2327 /* 5331 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2328 /* 5333 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2329 /* 5333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB),
2330 /* 5336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2331 /* 5338 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2332 /* 5340 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2333 /* 5344 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2334 /* 5347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2335 /* 5350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2336 /* 5356 */ GIR_RootConstrainSelectedInstOperands,
2337 /* 5357 */ // GIR_Coverage, 6253,
2338 /* 5357 */ GIR_EraseRootFromParent_Done,
2339 /* 5358 */ // Label 148: @5358
2340 /* 5358 */ GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(5429), // Rule ID 6254 //
2341 /* 5363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
2342 /* 5366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2343 /* 5370 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2344 /* 5374 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2345 /* 5378 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2346 /* 5382 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2347 /* 5387 */ // MIs[1] Operand 2
2348 /* 5387 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2349 /* 5398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2350 /* 5402 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2351 /* 5404 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2352 /* 5404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH),
2353 /* 5407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2354 /* 5409 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2355 /* 5411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2356 /* 5415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2357 /* 5418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2358 /* 5421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2359 /* 5427 */ GIR_RootConstrainSelectedInstOperands,
2360 /* 5428 */ // GIR_Coverage, 6254,
2361 /* 5428 */ GIR_EraseRootFromParent_Done,
2362 /* 5429 */ // Label 149: @5429
2363 /* 5429 */ GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(5500), // Rule ID 6288 //
2364 /* 5434 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
2365 /* 5437 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2366 /* 5441 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2367 /* 5445 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2368 /* 5449 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2369 /* 5453 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2370 /* 5458 */ // MIs[1] Operand 2
2371 /* 5458 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2372 /* 5469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2373 /* 5473 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2374 /* 5475 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2375 /* 5475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB),
2376 /* 5478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2377 /* 5480 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2378 /* 5482 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2379 /* 5486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2380 /* 5489 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2381 /* 5492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2382 /* 5498 */ GIR_RootConstrainSelectedInstOperands,
2383 /* 5499 */ // GIR_Coverage, 6288,
2384 /* 5499 */ GIR_EraseRootFromParent_Done,
2385 /* 5500 */ // Label 150: @5500
2386 /* 5500 */ GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(5571), // Rule ID 6289 //
2387 /* 5505 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
2388 /* 5508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2389 /* 5512 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2390 /* 5516 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2391 /* 5520 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2392 /* 5524 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2393 /* 5529 */ // MIs[1] Operand 2
2394 /* 5529 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2395 /* 5540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2396 /* 5544 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2397 /* 5546 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2398 /* 5546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
2399 /* 5549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2400 /* 5551 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2401 /* 5553 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2402 /* 5557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2403 /* 5560 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2404 /* 5563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2405 /* 5569 */ GIR_RootConstrainSelectedInstOperands,
2406 /* 5570 */ // GIR_Coverage, 6289,
2407 /* 5570 */ GIR_EraseRootFromParent_Done,
2408 /* 5571 */ // Label 151: @5571
2409 /* 5571 */ GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(5641), // Rule ID 179 //
2410 /* 5576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps),
2411 /* 5579 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2412 /* 5583 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2413 /* 5587 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2414 /* 5591 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2415 /* 5595 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2416 /* 5599 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2417 /* 5604 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2418 /* 5609 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2419 /* 5613 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2420 /* 5615 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
2421 /* 5615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA),
2422 /* 5618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2423 /* 5620 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2424 /* 5624 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2425 /* 5628 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2426 /* 5630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2427 /* 5633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2428 /* 5639 */ GIR_RootConstrainSelectedInstOperands,
2429 /* 5640 */ // GIR_Coverage, 179,
2430 /* 5640 */ GIR_EraseRootFromParent_Done,
2431 /* 5641 */ // Label 152: @5641
2432 /* 5641 */ GIM_Try, /*On fail goto*//*Label 153*/ GIMT_Encode4(5711), // Rule ID 508 //
2433 /* 5646 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
2434 /* 5649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2435 /* 5653 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2436 /* 5657 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2437 /* 5661 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2438 /* 5665 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2439 /* 5669 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2440 /* 5674 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2441 /* 5679 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2442 /* 5683 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2443 /* 5685 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2444 /* 5685 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA),
2445 /* 5688 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2446 /* 5690 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2447 /* 5694 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2448 /* 5698 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2449 /* 5700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2450 /* 5703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2451 /* 5709 */ GIR_RootConstrainSelectedInstOperands,
2452 /* 5710 */ // GIR_Coverage, 508,
2453 /* 5710 */ GIR_EraseRootFromParent_Done,
2454 /* 5711 */ // Label 153: @5711
2455 /* 5711 */ GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(5774), // Rule ID 3430 //
2456 /* 5716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2457 /* 5719 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2458 /* 5723 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2459 /* 5727 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2460 /* 5731 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2461 /* 5735 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2462 /* 5740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2463 /* 5744 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2464 /* 5746 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec)
2465 /* 5746 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc),
2466 /* 5749 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2467 /* 5751 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc
2468 /* 5753 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2469 /* 5757 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2470 /* 5760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2471 /* 5766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2472 /* 5772 */ GIR_RootConstrainSelectedInstOperands,
2473 /* 5773 */ // GIR_Coverage, 3430,
2474 /* 5773 */ GIR_EraseRootFromParent_Done,
2475 /* 5774 */ // Label 154: @5774
2476 /* 5774 */ GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(5837), // Rule ID 3458 //
2477 /* 5779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2478 /* 5782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2479 /* 5786 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2480 /* 5790 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2481 /* 5794 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2482 /* 5798 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2483 /* 5803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2484 /* 5807 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2485 /* 5809 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec)
2486 /* 5809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc),
2487 /* 5812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2488 /* 5814 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc
2489 /* 5816 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2490 /* 5820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2491 /* 5823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2492 /* 5829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2493 /* 5835 */ GIR_RootConstrainSelectedInstOperands,
2494 /* 5836 */ // GIR_Coverage, 3458,
2495 /* 5836 */ GIR_EraseRootFromParent_Done,
2496 /* 5837 */ // Label 155: @5837
2497 /* 5837 */ GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(5900), // Rule ID 3468 //
2498 /* 5842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2499 /* 5845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2500 /* 5849 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2501 /* 5853 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2502 /* 5857 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2503 /* 5861 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2504 /* 5866 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2505 /* 5870 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2506 /* 5872 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec)
2507 /* 5872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc),
2508 /* 5875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2509 /* 5877 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc
2510 /* 5879 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2511 /* 5883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2512 /* 5886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2513 /* 5892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2514 /* 5898 */ GIR_RootConstrainSelectedInstOperands,
2515 /* 5899 */ // GIR_Coverage, 3468,
2516 /* 5899 */ GIR_EraseRootFromParent_Done,
2517 /* 5900 */ // Label 156: @5900
2518 /* 5900 */ GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(5976), // Rule ID 5958 //
2519 /* 5905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps),
2520 /* 5908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2521 /* 5912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2522 /* 5916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2523 /* 5920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2524 /* 5924 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2525 /* 5928 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2526 /* 5932 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2527 /* 5937 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2528 /* 5942 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2529 /* 5944 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2530 /* 5944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA),
2531 /* 5947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2532 /* 5949 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2533 /* 5953 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2534 /* 5957 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2535 /* 5959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2536 /* 5962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2537 /* 5968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2538 /* 5974 */ GIR_RootConstrainSelectedInstOperands,
2539 /* 5975 */ // GIR_Coverage, 5958,
2540 /* 5975 */ GIR_EraseRootFromParent_Done,
2541 /* 5976 */ // Label 157: @5976
2542 /* 5976 */ GIM_Try, /*On fail goto*//*Label 158*/ GIMT_Encode4(6052), // Rule ID 5959 //
2543 /* 5981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6),
2544 /* 5984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2545 /* 5988 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2546 /* 5992 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2547 /* 5996 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2548 /* 6000 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2549 /* 6004 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2550 /* 6008 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2551 /* 6013 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2552 /* 6018 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2553 /* 6020 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2554 /* 6020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5),
2555 /* 6023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2556 /* 6025 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2557 /* 6029 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2558 /* 6033 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2559 /* 6035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2560 /* 6038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2561 /* 6044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2562 /* 6050 */ GIR_RootConstrainSelectedInstOperands,
2563 /* 6051 */ // GIR_Coverage, 5959,
2564 /* 6051 */ GIR_EraseRootFromParent_Done,
2565 /* 6052 */ // Label 158: @6052
2566 /* 6052 */ GIM_Try, /*On fail goto*//*Label 159*/ GIMT_Encode4(6122), // Rule ID 5996 //
2567 /* 6057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps),
2568 /* 6060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2569 /* 6064 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2570 /* 6068 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2571 /* 6072 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2572 /* 6076 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2573 /* 6080 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2574 /* 6084 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2575 /* 6089 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2576 /* 6094 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2577 /* 6096 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2578 /* 6096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA),
2579 /* 6099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2580 /* 6101 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2581 /* 6105 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2582 /* 6109 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2583 /* 6111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2584 /* 6114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2585 /* 6120 */ GIR_RootConstrainSelectedInstOperands,
2586 /* 6121 */ // GIR_Coverage, 5996,
2587 /* 6121 */ GIR_EraseRootFromParent_Done,
2588 /* 6122 */ // Label 159: @6122
2589 /* 6122 */ GIM_Try, /*On fail goto*//*Label 160*/ GIMT_Encode4(6193), // Rule ID 2190 //
2590 /* 6127 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
2591 /* 6130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2592 /* 6134 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2593 /* 6138 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2594 /* 6142 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2595 /* 6146 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2596 /* 6150 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2597 /* 6155 */ // MIs[1] Operand 2
2598 /* 6155 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2599 /* 6166 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2600 /* 6168 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2601 /* 6168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB),
2602 /* 6171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2603 /* 6173 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2604 /* 6175 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2605 /* 6179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2606 /* 6182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2607 /* 6185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2608 /* 6191 */ GIR_RootConstrainSelectedInstOperands,
2609 /* 6192 */ // GIR_Coverage, 2190,
2610 /* 6192 */ GIR_EraseRootFromParent_Done,
2611 /* 6193 */ // Label 160: @6193
2612 /* 6193 */ GIM_Try, /*On fail goto*//*Label 161*/ GIMT_Encode4(6264), // Rule ID 2191 //
2613 /* 6198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
2614 /* 6201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2615 /* 6205 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2616 /* 6209 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2617 /* 6213 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2618 /* 6217 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2619 /* 6221 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2620 /* 6226 */ // MIs[1] Operand 2
2621 /* 6226 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2622 /* 6237 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2623 /* 6239 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2624 /* 6239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH),
2625 /* 6242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2626 /* 6244 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2627 /* 6246 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2628 /* 6250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2629 /* 6253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2630 /* 6256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2631 /* 6262 */ GIR_RootConstrainSelectedInstOperands,
2632 /* 6263 */ // GIR_Coverage, 2191,
2633 /* 6263 */ GIR_EraseRootFromParent_Done,
2634 /* 6264 */ // Label 161: @6264
2635 /* 6264 */ GIM_Try, /*On fail goto*//*Label 162*/ GIMT_Encode4(6335), // Rule ID 2429 //
2636 /* 6269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
2637 /* 6272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2638 /* 6276 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2639 /* 6280 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2640 /* 6284 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2641 /* 6288 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2642 /* 6292 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2643 /* 6297 */ // MIs[1] Operand 2
2644 /* 6297 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2645 /* 6308 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2646 /* 6310 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2647 /* 6310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB),
2648 /* 6313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2649 /* 6315 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2650 /* 6317 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2651 /* 6321 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2652 /* 6324 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2653 /* 6327 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2654 /* 6333 */ GIR_RootConstrainSelectedInstOperands,
2655 /* 6334 */ // GIR_Coverage, 2429,
2656 /* 6334 */ GIR_EraseRootFromParent_Done,
2657 /* 6335 */ // Label 162: @6335
2658 /* 6335 */ GIM_Try, /*On fail goto*//*Label 163*/ GIMT_Encode4(6406), // Rule ID 2430 //
2659 /* 6340 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
2660 /* 6343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2661 /* 6347 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2662 /* 6351 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2663 /* 6355 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2664 /* 6359 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2665 /* 6363 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2666 /* 6368 */ // MIs[1] Operand 2
2667 /* 6368 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2668 /* 6379 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2669 /* 6381 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2670 /* 6381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
2671 /* 6384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2672 /* 6386 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2673 /* 6388 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2674 /* 6392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2675 /* 6395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2676 /* 6398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2677 /* 6404 */ GIR_RootConstrainSelectedInstOperands,
2678 /* 6405 */ // GIR_Coverage, 2430,
2679 /* 6405 */ GIR_EraseRootFromParent_Done,
2680 /* 6406 */ // Label 163: @6406
2681 /* 6406 */ GIM_Try, /*On fail goto*//*Label 164*/ GIMT_Encode4(6476), // Rule ID 5960 //
2682 /* 6411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps),
2683 /* 6414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2684 /* 6418 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2685 /* 6422 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2686 /* 6426 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2687 /* 6430 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2688 /* 6434 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2689 /* 6438 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2690 /* 6443 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2691 /* 6448 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2692 /* 6450 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
2693 /* 6450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA),
2694 /* 6453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2695 /* 6455 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2696 /* 6459 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2697 /* 6463 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2698 /* 6465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2699 /* 6468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2700 /* 6474 */ GIR_RootConstrainSelectedInstOperands,
2701 /* 6475 */ // GIR_Coverage, 5960,
2702 /* 6475 */ GIR_EraseRootFromParent_Done,
2703 /* 6476 */ // Label 164: @6476
2704 /* 6476 */ GIM_Try, /*On fail goto*//*Label 165*/ GIMT_Encode4(6546), // Rule ID 5997 //
2705 /* 6481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
2706 /* 6484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2707 /* 6488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2708 /* 6492 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2709 /* 6496 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2710 /* 6500 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2711 /* 6504 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2712 /* 6508 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2713 /* 6513 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2714 /* 6518 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2715 /* 6520 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2716 /* 6520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA),
2717 /* 6523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2718 /* 6525 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2719 /* 6529 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2720 /* 6533 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2721 /* 6535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2722 /* 6538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2723 /* 6544 */ GIR_RootConstrainSelectedInstOperands,
2724 /* 6545 */ // GIR_Coverage, 5997,
2725 /* 6545 */ GIR_EraseRootFromParent_Done,
2726 /* 6546 */ // Label 165: @6546
2727 /* 6546 */ GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(6609), // Rule ID 6534 //
2728 /* 6551 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2729 /* 6554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2730 /* 6558 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2731 /* 6562 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2732 /* 6566 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2733 /* 6570 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2734 /* 6574 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2735 /* 6579 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2736 /* 6581 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec)) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec)
2737 /* 6581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc),
2738 /* 6584 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2739 /* 6586 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc
2740 /* 6588 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2741 /* 6592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2742 /* 6595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2743 /* 6601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2744 /* 6607 */ GIR_RootConstrainSelectedInstOperands,
2745 /* 6608 */ // GIR_Coverage, 6534,
2746 /* 6608 */ GIR_EraseRootFromParent_Done,
2747 /* 6609 */ // Label 166: @6609
2748 /* 6609 */ GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(6672), // Rule ID 6548 //
2749 /* 6614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2750 /* 6617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2751 /* 6621 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2752 /* 6625 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2753 /* 6629 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2754 /* 6633 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2755 /* 6637 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2756 /* 6642 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2757 /* 6644 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec)) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec)
2758 /* 6644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc),
2759 /* 6647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2760 /* 6649 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc
2761 /* 6651 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2762 /* 6655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2763 /* 6658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2764 /* 6664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2765 /* 6670 */ GIR_RootConstrainSelectedInstOperands,
2766 /* 6671 */ // GIR_Coverage, 6548,
2767 /* 6671 */ GIR_EraseRootFromParent_Done,
2768 /* 6672 */ // Label 167: @6672
2769 /* 6672 */ GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(6735), // Rule ID 6553 //
2770 /* 6677 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2771 /* 6680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2772 /* 6684 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2773 /* 6688 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2774 /* 6692 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2775 /* 6696 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2776 /* 6700 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2777 /* 6705 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2778 /* 6707 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec)) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec)
2779 /* 6707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc),
2780 /* 6710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2781 /* 6712 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc
2782 /* 6714 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2783 /* 6718 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2784 /* 6721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2785 /* 6727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2786 /* 6733 */ GIR_RootConstrainSelectedInstOperands,
2787 /* 6734 */ // GIR_Coverage, 6553,
2788 /* 6734 */ GIR_EraseRootFromParent_Done,
2789 /* 6735 */ // Label 168: @6735
2790 /* 6735 */ GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(6781), // Rule ID 72 //
2791 /* 6740 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
2792 /* 6743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2793 /* 6747 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2794 /* 6751 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2795 /* 6755 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
2796 /* 6755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDrr),
2797 /* 6758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2798 /* 6760 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2799 /* 6762 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
2800 /* 6764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2801 /* 6767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2802 /* 6773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2803 /* 6779 */ GIR_RootConstrainSelectedInstOperands,
2804 /* 6780 */ // GIR_Coverage, 72,
2805 /* 6780 */ GIR_EraseRootFromParent_Done,
2806 /* 6781 */ // Label 169: @6781
2807 /* 6781 */ GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(6827), // Rule ID 304 //
2808 /* 6786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
2809 /* 6789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2810 /* 6793 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2811 /* 6797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2812 /* 6801 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tADDrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
2813 /* 6801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDrr),
2814 /* 6804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2815 /* 6806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
2816 /* 6812 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2817 /* 6814 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
2818 /* 6816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2819 /* 6819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2820 /* 6825 */ GIR_RootConstrainSelectedInstOperands,
2821 /* 6826 */ // GIR_Coverage, 304,
2822 /* 6826 */ GIR_EraseRootFromParent_Done,
2823 /* 6827 */ // Label 170: @6827
2824 /* 6827 */ GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(6873), // Rule ID 408 //
2825 /* 6832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
2826 /* 6835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2827 /* 6839 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2828 /* 6843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2829 /* 6847 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
2830 /* 6847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr),
2831 /* 6850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2832 /* 6852 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2833 /* 6854 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
2834 /* 6856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2835 /* 6859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2836 /* 6865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2837 /* 6871 */ GIR_RootConstrainSelectedInstOperands,
2838 /* 6872 */ // GIR_Coverage, 408,
2839 /* 6872 */ GIR_EraseRootFromParent_Done,
2840 /* 6873 */ // Label 171: @6873
2841 /* 6873 */ GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(6919), // Rule ID 5978 //
2842 /* 6878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
2843 /* 6881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2844 /* 6885 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2845 /* 6889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2846 /* 6893 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
2847 /* 6893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr),
2848 /* 6896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2849 /* 6898 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2850 /* 6900 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
2851 /* 6902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2852 /* 6905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2853 /* 6911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2854 /* 6917 */ GIR_RootConstrainSelectedInstOperands,
2855 /* 6918 */ // GIR_Coverage, 5978,
2856 /* 6918 */ GIR_EraseRootFromParent_Done,
2857 /* 6919 */ // Label 172: @6919
2858 /* 6919 */ GIM_Reject,
2859 /* 6920 */ // Label 103: @6920
2860 /* 6920 */ GIM_Reject,
2861 /* 6921 */ // Label 94: @6921
2862 /* 6921 */ GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(6967), // Rule ID 882 //
2863 /* 6926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2864 /* 6929 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2865 /* 6932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2866 /* 6935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2867 /* 6939 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2868 /* 6943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2869 /* 6947 */ // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
2870 /* 6947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv1i64),
2871 /* 6950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2872 /* 6952 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
2873 /* 6954 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
2874 /* 6956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2875 /* 6959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2876 /* 6965 */ GIR_RootConstrainSelectedInstOperands,
2877 /* 6966 */ // GIR_Coverage, 882,
2878 /* 6966 */ GIR_EraseRootFromParent_Done,
2879 /* 6967 */ // Label 173: @6967
2880 /* 6967 */ GIM_Reject,
2881 /* 6968 */ // Label 95: @6968
2882 /* 6968 */ GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(7416),
2883 /* 6973 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
2884 /* 6976 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
2885 /* 6979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2886 /* 6983 */ GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(7049), // Rule ID 6181 //
2887 /* 6988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2888 /* 6991 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2889 /* 6995 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
2890 /* 6999 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2891 /* 7003 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2892 /* 7007 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2893 /* 7012 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2894 /* 7017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2895 /* 7021 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2896 /* 7023 */ // (add:{ *:[v8i8] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2897 /* 7023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8),
2898 /* 7026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2899 /* 7028 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
2900 /* 7030 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2901 /* 7034 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2902 /* 7038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2903 /* 7041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2904 /* 7047 */ GIR_RootConstrainSelectedInstOperands,
2905 /* 7048 */ // GIR_Coverage, 6181,
2906 /* 7048 */ GIR_EraseRootFromParent_Done,
2907 /* 7049 */ // Label 175: @7049
2908 /* 7049 */ GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(7115), // Rule ID 6187 //
2909 /* 7054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2910 /* 7057 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2911 /* 7061 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
2912 /* 7065 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2913 /* 7069 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2914 /* 7073 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2915 /* 7078 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2916 /* 7083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2917 /* 7087 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2918 /* 7089 */ // (add:{ *:[v8i8] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2919 /* 7089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8),
2920 /* 7092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2921 /* 7094 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
2922 /* 7096 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2923 /* 7100 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2924 /* 7104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2925 /* 7107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2926 /* 7113 */ GIR_RootConstrainSelectedInstOperands,
2927 /* 7114 */ // GIR_Coverage, 6187,
2928 /* 7114 */ GIR_EraseRootFromParent_Done,
2929 /* 7115 */ // Label 176: @7115
2930 /* 7115 */ GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(7181), // Rule ID 6069 //
2931 /* 7120 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2932 /* 7123 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2933 /* 7127 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2934 /* 7131 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2935 /* 7135 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2936 /* 7139 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2937 /* 7144 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2938 /* 7149 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2939 /* 7153 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2940 /* 7155 */ // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2941 /* 7155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8),
2942 /* 7158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2943 /* 7160 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
2944 /* 7162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2945 /* 7166 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2946 /* 7170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2947 /* 7173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2948 /* 7179 */ GIR_RootConstrainSelectedInstOperands,
2949 /* 7180 */ // GIR_Coverage, 6069,
2950 /* 7180 */ GIR_EraseRootFromParent_Done,
2951 /* 7181 */ // Label 177: @7181
2952 /* 7181 */ GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(7247), // Rule ID 1341 //
2953 /* 7186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2954 /* 7189 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2955 /* 7193 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2956 /* 7197 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
2957 /* 7201 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2958 /* 7205 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2959 /* 7209 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2960 /* 7214 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2961 /* 7219 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2962 /* 7221 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2963 /* 7221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8),
2964 /* 7224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2965 /* 7226 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
2966 /* 7228 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2967 /* 7232 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2968 /* 7236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2969 /* 7239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2970 /* 7245 */ GIR_RootConstrainSelectedInstOperands,
2971 /* 7246 */ // GIR_Coverage, 1341,
2972 /* 7246 */ GIR_EraseRootFromParent_Done,
2973 /* 7247 */ // Label 178: @7247
2974 /* 7247 */ GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(7313), // Rule ID 1347 //
2975 /* 7252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2976 /* 7255 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2977 /* 7259 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2978 /* 7263 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
2979 /* 7267 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2980 /* 7271 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2981 /* 7275 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2982 /* 7280 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2983 /* 7285 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2984 /* 7287 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2985 /* 7287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8),
2986 /* 7290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2987 /* 7292 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
2988 /* 7294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2989 /* 7298 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2990 /* 7302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2991 /* 7305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2992 /* 7311 */ GIR_RootConstrainSelectedInstOperands,
2993 /* 7312 */ // GIR_Coverage, 1347,
2994 /* 7312 */ GIR_EraseRootFromParent_Done,
2995 /* 7313 */ // Label 179: @7313
2996 /* 7313 */ GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(7379), // Rule ID 1007 //
2997 /* 7318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2998 /* 7321 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2999 /* 7325 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3000 /* 7329 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3001 /* 7333 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3002 /* 7337 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
3003 /* 7341 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3004 /* 7346 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3005 /* 7351 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3006 /* 7353 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3007 /* 7353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8),
3008 /* 7356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3009 /* 7358 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3010 /* 7360 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3011 /* 7364 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3012 /* 7368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3013 /* 7371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3014 /* 7377 */ GIR_RootConstrainSelectedInstOperands,
3015 /* 7378 */ // GIR_Coverage, 1007,
3016 /* 7378 */ GIR_EraseRootFromParent_Done,
3017 /* 7379 */ // Label 180: @7379
3018 /* 7379 */ GIM_Try, /*On fail goto*//*Label 181*/ GIMT_Encode4(7415), // Rule ID 876 //
3019 /* 7384 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3020 /* 7387 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3021 /* 7391 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3022 /* 7395 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3023 /* 7395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i8),
3024 /* 7398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3025 /* 7400 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3026 /* 7402 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3027 /* 7404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3028 /* 7407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3029 /* 7413 */ GIR_RootConstrainSelectedInstOperands,
3030 /* 7414 */ // GIR_Coverage, 876,
3031 /* 7414 */ GIR_EraseRootFromParent_Done,
3032 /* 7415 */ // Label 181: @7415
3033 /* 7415 */ GIM_Reject,
3034 /* 7416 */ // Label 174: @7416
3035 /* 7416 */ GIM_Reject,
3036 /* 7417 */ // Label 96: @7417
3037 /* 7417 */ GIM_Try, /*On fail goto*//*Label 182*/ GIMT_Encode4(7950),
3038 /* 7422 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3039 /* 7425 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
3040 /* 7428 */ GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(7498), // Rule ID 6184 //
3041 /* 7433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3042 /* 7436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3043 /* 7440 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3044 /* 7444 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3045 /* 7448 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3046 /* 7452 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3047 /* 7456 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3048 /* 7461 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3049 /* 7466 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3050 /* 7470 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3051 /* 7472 */ // (add:{ *:[v16i8] } (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3052 /* 7472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8),
3053 /* 7475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3054 /* 7477 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3055 /* 7479 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3056 /* 7483 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3057 /* 7487 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3058 /* 7490 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3059 /* 7496 */ GIR_RootConstrainSelectedInstOperands,
3060 /* 7497 */ // GIR_Coverage, 6184,
3061 /* 7497 */ GIR_EraseRootFromParent_Done,
3062 /* 7498 */ // Label 183: @7498
3063 /* 7498 */ GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(7568), // Rule ID 6190 //
3064 /* 7503 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3065 /* 7506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3066 /* 7510 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3067 /* 7514 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3068 /* 7518 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3069 /* 7522 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3070 /* 7526 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3071 /* 7531 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3072 /* 7536 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3073 /* 7540 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3074 /* 7542 */ // (add:{ *:[v16i8] } (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3075 /* 7542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8),
3076 /* 7545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3077 /* 7547 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3078 /* 7549 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3079 /* 7553 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3080 /* 7557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3081 /* 7560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3082 /* 7566 */ GIR_RootConstrainSelectedInstOperands,
3083 /* 7567 */ // GIR_Coverage, 6190,
3084 /* 7567 */ GIR_EraseRootFromParent_Done,
3085 /* 7568 */ // Label 184: @7568
3086 /* 7568 */ GIM_Try, /*On fail goto*//*Label 185*/ GIMT_Encode4(7638), // Rule ID 6072 //
3087 /* 7573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3088 /* 7576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3089 /* 7580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3090 /* 7584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3091 /* 7588 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3092 /* 7592 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3093 /* 7596 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3094 /* 7601 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3095 /* 7606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3096 /* 7610 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3097 /* 7612 */ // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3098 /* 7612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8),
3099 /* 7615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3100 /* 7617 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3101 /* 7619 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3102 /* 7623 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3103 /* 7627 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3104 /* 7630 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3105 /* 7636 */ GIR_RootConstrainSelectedInstOperands,
3106 /* 7637 */ // GIR_Coverage, 6072,
3107 /* 7637 */ GIR_EraseRootFromParent_Done,
3108 /* 7638 */ // Label 185: @7638
3109 /* 7638 */ GIM_Try, /*On fail goto*//*Label 186*/ GIMT_Encode4(7708), // Rule ID 1344 //
3110 /* 7643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3111 /* 7646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3112 /* 7650 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3113 /* 7654 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3114 /* 7658 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3115 /* 7662 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3116 /* 7666 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3117 /* 7670 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3118 /* 7675 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3119 /* 7680 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3120 /* 7682 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3121 /* 7682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8),
3122 /* 7685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3123 /* 7687 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3124 /* 7689 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3125 /* 7693 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3126 /* 7697 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3127 /* 7700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3128 /* 7706 */ GIR_RootConstrainSelectedInstOperands,
3129 /* 7707 */ // GIR_Coverage, 1344,
3130 /* 7707 */ GIR_EraseRootFromParent_Done,
3131 /* 7708 */ // Label 186: @7708
3132 /* 7708 */ GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(7778), // Rule ID 1350 //
3133 /* 7713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3134 /* 7716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3135 /* 7720 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3136 /* 7724 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3137 /* 7728 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3138 /* 7732 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3139 /* 7736 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3140 /* 7740 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3141 /* 7745 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3142 /* 7750 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3143 /* 7752 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3144 /* 7752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8),
3145 /* 7755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3146 /* 7757 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3147 /* 7759 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3148 /* 7763 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3149 /* 7767 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3150 /* 7770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3151 /* 7776 */ GIR_RootConstrainSelectedInstOperands,
3152 /* 7777 */ // GIR_Coverage, 1350,
3153 /* 7777 */ GIR_EraseRootFromParent_Done,
3154 /* 7778 */ // Label 187: @7778
3155 /* 7778 */ GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(7848), // Rule ID 1010 //
3156 /* 7783 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3157 /* 7786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3158 /* 7790 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3159 /* 7794 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3160 /* 7798 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3161 /* 7802 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3162 /* 7806 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3163 /* 7810 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3164 /* 7815 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3165 /* 7820 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3166 /* 7822 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3167 /* 7822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8),
3168 /* 7825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3169 /* 7827 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3170 /* 7829 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3171 /* 7833 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3172 /* 7837 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3173 /* 7840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3174 /* 7846 */ GIR_RootConstrainSelectedInstOperands,
3175 /* 7847 */ // GIR_Coverage, 1010,
3176 /* 7847 */ GIR_EraseRootFromParent_Done,
3177 /* 7848 */ // Label 188: @7848
3178 /* 7848 */ GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(7888), // Rule ID 879 //
3179 /* 7853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3180 /* 7856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3181 /* 7860 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3182 /* 7864 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3183 /* 7868 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3184 /* 7868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv16i8),
3185 /* 7871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3186 /* 7873 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3187 /* 7875 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3188 /* 7877 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3189 /* 7880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3190 /* 7886 */ GIR_RootConstrainSelectedInstOperands,
3191 /* 7887 */ // GIR_Coverage, 879,
3192 /* 7887 */ GIR_EraseRootFromParent_Done,
3193 /* 7888 */ // Label 189: @7888
3194 /* 7888 */ GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(7949), // Rule ID 3871 //
3195 /* 7893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
3196 /* 7896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3197 /* 7900 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3198 /* 7904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3199 /* 7908 */ // (add:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
3200 /* 7908 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3201 /* 7911 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
3202 /* 7915 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3203 /* 7920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi8),
3204 /* 7923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
3205 /* 7925 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
3206 /* 7927 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
3207 /* 7929 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
3208 /* 7932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3209 /* 7938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3210 /* 7944 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3211 /* 7947 */ GIR_RootConstrainSelectedInstOperands,
3212 /* 7948 */ // GIR_Coverage, 3871,
3213 /* 7948 */ GIR_EraseRootFromParent_Done,
3214 /* 7949 */ // Label 190: @7949
3215 /* 7949 */ GIM_Reject,
3216 /* 7950 */ // Label 182: @7950
3217 /* 7950 */ GIM_Reject,
3218 /* 7951 */ // Label 97: @7951
3219 /* 7951 */ GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(8399),
3220 /* 7956 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
3221 /* 7959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
3222 /* 7962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3223 /* 7966 */ GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(8032), // Rule ID 6182 //
3224 /* 7971 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3225 /* 7974 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3226 /* 7978 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3227 /* 7982 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3228 /* 7986 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3229 /* 7990 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3230 /* 7995 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3231 /* 8000 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3232 /* 8004 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3233 /* 8006 */ // (add:{ *:[v4i16] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3234 /* 8006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16),
3235 /* 8009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3236 /* 8011 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3237 /* 8013 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3238 /* 8017 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3239 /* 8021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3240 /* 8024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3241 /* 8030 */ GIR_RootConstrainSelectedInstOperands,
3242 /* 8031 */ // GIR_Coverage, 6182,
3243 /* 8031 */ GIR_EraseRootFromParent_Done,
3244 /* 8032 */ // Label 192: @8032
3245 /* 8032 */ GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(8098), // Rule ID 6188 //
3246 /* 8037 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3247 /* 8040 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3248 /* 8044 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3249 /* 8048 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3250 /* 8052 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3251 /* 8056 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3252 /* 8061 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3253 /* 8066 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3254 /* 8070 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3255 /* 8072 */ // (add:{ *:[v4i16] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3256 /* 8072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16),
3257 /* 8075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3258 /* 8077 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3259 /* 8079 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3260 /* 8083 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3261 /* 8087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3262 /* 8090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3263 /* 8096 */ GIR_RootConstrainSelectedInstOperands,
3264 /* 8097 */ // GIR_Coverage, 6188,
3265 /* 8097 */ GIR_EraseRootFromParent_Done,
3266 /* 8098 */ // Label 193: @8098
3267 /* 8098 */ GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(8164), // Rule ID 6070 //
3268 /* 8103 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3269 /* 8106 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3270 /* 8110 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3271 /* 8114 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3272 /* 8118 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3273 /* 8122 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3274 /* 8127 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3275 /* 8132 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3276 /* 8136 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3277 /* 8138 */ // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3278 /* 8138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16),
3279 /* 8141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3280 /* 8143 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3281 /* 8145 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3282 /* 8149 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3283 /* 8153 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3284 /* 8156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3285 /* 8162 */ GIR_RootConstrainSelectedInstOperands,
3286 /* 8163 */ // GIR_Coverage, 6070,
3287 /* 8163 */ GIR_EraseRootFromParent_Done,
3288 /* 8164 */ // Label 194: @8164
3289 /* 8164 */ GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(8230), // Rule ID 1342 //
3290 /* 8169 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3291 /* 8172 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3292 /* 8176 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3293 /* 8180 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3294 /* 8184 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3295 /* 8188 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3296 /* 8192 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3297 /* 8197 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3298 /* 8202 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3299 /* 8204 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3300 /* 8204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16),
3301 /* 8207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3302 /* 8209 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3303 /* 8211 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3304 /* 8215 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3305 /* 8219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3306 /* 8222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3307 /* 8228 */ GIR_RootConstrainSelectedInstOperands,
3308 /* 8229 */ // GIR_Coverage, 1342,
3309 /* 8229 */ GIR_EraseRootFromParent_Done,
3310 /* 8230 */ // Label 195: @8230
3311 /* 8230 */ GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(8296), // Rule ID 1348 //
3312 /* 8235 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3313 /* 8238 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3314 /* 8242 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3315 /* 8246 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3316 /* 8250 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3317 /* 8254 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3318 /* 8258 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3319 /* 8263 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3320 /* 8268 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3321 /* 8270 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3322 /* 8270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16),
3323 /* 8273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3324 /* 8275 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3325 /* 8277 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3326 /* 8281 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3327 /* 8285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3328 /* 8288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3329 /* 8294 */ GIR_RootConstrainSelectedInstOperands,
3330 /* 8295 */ // GIR_Coverage, 1348,
3331 /* 8295 */ GIR_EraseRootFromParent_Done,
3332 /* 8296 */ // Label 196: @8296
3333 /* 8296 */ GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(8362), // Rule ID 1008 //
3334 /* 8301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3335 /* 8304 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3336 /* 8308 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3337 /* 8312 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3338 /* 8316 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3339 /* 8320 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3340 /* 8324 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3341 /* 8329 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3342 /* 8334 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3343 /* 8336 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3344 /* 8336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16),
3345 /* 8339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3346 /* 8341 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3347 /* 8343 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3348 /* 8347 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3349 /* 8351 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3350 /* 8354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3351 /* 8360 */ GIR_RootConstrainSelectedInstOperands,
3352 /* 8361 */ // GIR_Coverage, 1008,
3353 /* 8361 */ GIR_EraseRootFromParent_Done,
3354 /* 8362 */ // Label 197: @8362
3355 /* 8362 */ GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(8398), // Rule ID 877 //
3356 /* 8367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3357 /* 8370 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3358 /* 8374 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3359 /* 8378 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3360 /* 8378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i16),
3361 /* 8381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3362 /* 8383 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3363 /* 8385 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3364 /* 8387 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3365 /* 8390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3366 /* 8396 */ GIR_RootConstrainSelectedInstOperands,
3367 /* 8397 */ // GIR_Coverage, 877,
3368 /* 8397 */ GIR_EraseRootFromParent_Done,
3369 /* 8398 */ // Label 198: @8398
3370 /* 8398 */ GIM_Reject,
3371 /* 8399 */ // Label 191: @8399
3372 /* 8399 */ GIM_Reject,
3373 /* 8400 */ // Label 98: @8400
3374 /* 8400 */ GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(9963),
3375 /* 8405 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3376 /* 8408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
3377 /* 8411 */ GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(8483), // Rule ID 894 //
3378 /* 8416 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3379 /* 8419 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3380 /* 8423 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3381 /* 8427 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3382 /* 8431 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3383 /* 8435 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3384 /* 8440 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3385 /* 8444 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3386 /* 8448 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3387 /* 8452 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3388 /* 8457 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3389 /* 8459 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3390 /* 8459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3391 /* 8462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3392 /* 8464 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3393 /* 8468 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3394 /* 8472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3395 /* 8475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3396 /* 8481 */ GIR_RootConstrainSelectedInstOperands,
3397 /* 8482 */ // GIR_Coverage, 894,
3398 /* 8482 */ GIR_EraseRootFromParent_Done,
3399 /* 8483 */ // Label 200: @8483
3400 /* 8483 */ GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(8555), // Rule ID 893 //
3401 /* 8488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3402 /* 8491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3403 /* 8495 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3404 /* 8499 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3405 /* 8503 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3406 /* 8507 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3407 /* 8512 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3408 /* 8516 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3409 /* 8520 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3410 /* 8524 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3411 /* 8529 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3412 /* 8531 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3413 /* 8531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3414 /* 8534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3415 /* 8536 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3416 /* 8540 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3417 /* 8544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3418 /* 8547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3419 /* 8553 */ GIR_RootConstrainSelectedInstOperands,
3420 /* 8554 */ // GIR_Coverage, 893,
3421 /* 8554 */ GIR_EraseRootFromParent_Done,
3422 /* 8555 */ // Label 201: @8555
3423 /* 8555 */ GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(8627), // Rule ID 888 //
3424 /* 8560 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3425 /* 8563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3426 /* 8567 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3427 /* 8571 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3428 /* 8575 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3429 /* 8579 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3430 /* 8584 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3431 /* 8588 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
3432 /* 8592 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3433 /* 8596 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3434 /* 8601 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3435 /* 8603 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3436 /* 8603 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv8i16),
3437 /* 8606 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3438 /* 8608 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3439 /* 8612 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3440 /* 8616 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3441 /* 8619 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3442 /* 8625 */ GIR_RootConstrainSelectedInstOperands,
3443 /* 8626 */ // GIR_Coverage, 888,
3444 /* 8626 */ GIR_EraseRootFromParent_Done,
3445 /* 8627 */ // Label 202: @8627
3446 /* 8627 */ GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(8709), // Rule ID 6193 //
3447 /* 8632 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3448 /* 8635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3449 /* 8639 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3450 /* 8643 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3451 /* 8647 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3452 /* 8651 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3453 /* 8655 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
3454 /* 8659 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3455 /* 8663 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3456 /* 8667 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3457 /* 8672 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3458 /* 8677 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3459 /* 8681 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3460 /* 8683 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3461 /* 8683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16),
3462 /* 8686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3463 /* 8688 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3464 /* 8690 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3465 /* 8694 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3466 /* 8698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3467 /* 8701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3468 /* 8707 */ GIR_RootConstrainSelectedInstOperands,
3469 /* 8708 */ // GIR_Coverage, 6193,
3470 /* 8708 */ GIR_EraseRootFromParent_Done,
3471 /* 8709 */ // Label 203: @8709
3472 /* 8709 */ GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(8791), // Rule ID 6196 //
3473 /* 8714 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3474 /* 8717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3475 /* 8721 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3476 /* 8725 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3477 /* 8729 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3478 /* 8733 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3479 /* 8737 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
3480 /* 8741 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3481 /* 8745 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3482 /* 8749 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3483 /* 8754 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3484 /* 8759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3485 /* 8763 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3486 /* 8765 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3487 /* 8765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16),
3488 /* 8768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3489 /* 8770 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3490 /* 8772 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3491 /* 8776 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3492 /* 8780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3493 /* 8783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3494 /* 8789 */ GIR_RootConstrainSelectedInstOperands,
3495 /* 8790 */ // GIR_Coverage, 6196,
3496 /* 8790 */ GIR_EraseRootFromParent_Done,
3497 /* 8791 */ // Label 204: @8791
3498 /* 8791 */ GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(8863), // Rule ID 892 //
3499 /* 8796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3500 /* 8799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3501 /* 8803 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3502 /* 8807 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3503 /* 8811 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3504 /* 8815 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3505 /* 8820 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3506 /* 8824 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3507 /* 8828 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3508 /* 8832 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3509 /* 8837 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3510 /* 8839 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3511 /* 8839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3512 /* 8842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3513 /* 8844 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3514 /* 8848 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3515 /* 8852 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3516 /* 8855 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3517 /* 8861 */ GIR_RootConstrainSelectedInstOperands,
3518 /* 8862 */ // GIR_Coverage, 892,
3519 /* 8862 */ GIR_EraseRootFromParent_Done,
3520 /* 8863 */ // Label 205: @8863
3521 /* 8863 */ GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(8935), // Rule ID 891 //
3522 /* 8868 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3523 /* 8871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3524 /* 8875 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3525 /* 8879 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3526 /* 8883 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3527 /* 8887 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3528 /* 8892 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3529 /* 8896 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3530 /* 8900 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3531 /* 8904 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3532 /* 8909 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3533 /* 8911 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3534 /* 8911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3535 /* 8914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3536 /* 8916 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3537 /* 8920 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3538 /* 8924 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3539 /* 8927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3540 /* 8933 */ GIR_RootConstrainSelectedInstOperands,
3541 /* 8934 */ // GIR_Coverage, 891,
3542 /* 8934 */ GIR_EraseRootFromParent_Done,
3543 /* 8935 */ // Label 206: @8935
3544 /* 8935 */ GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(9017), // Rule ID 1353 //
3545 /* 8940 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3546 /* 8943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3547 /* 8947 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3548 /* 8951 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3549 /* 8955 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3550 /* 8959 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3551 /* 8963 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3552 /* 8967 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
3553 /* 8971 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3554 /* 8975 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3555 /* 8979 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3556 /* 8984 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3557 /* 8989 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3558 /* 8991 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3559 /* 8991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16),
3560 /* 8994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3561 /* 8996 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3562 /* 8998 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3563 /* 9002 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3564 /* 9006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3565 /* 9009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3566 /* 9015 */ GIR_RootConstrainSelectedInstOperands,
3567 /* 9016 */ // GIR_Coverage, 1353,
3568 /* 9016 */ GIR_EraseRootFromParent_Done,
3569 /* 9017 */ // Label 207: @9017
3570 /* 9017 */ GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(9099), // Rule ID 1356 //
3571 /* 9022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3572 /* 9025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3573 /* 9029 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3574 /* 9033 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3575 /* 9037 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3576 /* 9041 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3577 /* 9045 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3578 /* 9049 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
3579 /* 9053 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3580 /* 9057 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3581 /* 9061 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3582 /* 9066 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3583 /* 9071 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3584 /* 9073 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3585 /* 9073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16),
3586 /* 9076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3587 /* 9078 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3588 /* 9080 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3589 /* 9084 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3590 /* 9088 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3591 /* 9091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3592 /* 9097 */ GIR_RootConstrainSelectedInstOperands,
3593 /* 9098 */ // GIR_Coverage, 1356,
3594 /* 9098 */ GIR_EraseRootFromParent_Done,
3595 /* 9099 */ // Label 208: @9099
3596 /* 9099 */ GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(9169), // Rule ID 6185 //
3597 /* 9104 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3598 /* 9107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3599 /* 9111 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3600 /* 9115 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3601 /* 9119 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3602 /* 9123 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3603 /* 9127 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3604 /* 9132 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3605 /* 9137 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3606 /* 9141 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3607 /* 9143 */ // (add:{ *:[v8i16] } (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3608 /* 9143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16),
3609 /* 9146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3610 /* 9148 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3611 /* 9150 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3612 /* 9154 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3613 /* 9158 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3614 /* 9161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3615 /* 9167 */ GIR_RootConstrainSelectedInstOperands,
3616 /* 9168 */ // GIR_Coverage, 6185,
3617 /* 9168 */ GIR_EraseRootFromParent_Done,
3618 /* 9169 */ // Label 209: @9169
3619 /* 9169 */ GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(9239), // Rule ID 6191 //
3620 /* 9174 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3621 /* 9177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3622 /* 9181 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3623 /* 9185 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3624 /* 9189 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3625 /* 9193 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3626 /* 9197 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3627 /* 9202 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3628 /* 9207 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3629 /* 9211 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3630 /* 9213 */ // (add:{ *:[v8i16] } (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3631 /* 9213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16),
3632 /* 9216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3633 /* 9218 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3634 /* 9220 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3635 /* 9224 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3636 /* 9228 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3637 /* 9231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3638 /* 9237 */ GIR_RootConstrainSelectedInstOperands,
3639 /* 9238 */ // GIR_Coverage, 6191,
3640 /* 9238 */ GIR_EraseRootFromParent_Done,
3641 /* 9239 */ // Label 210: @9239
3642 /* 9239 */ GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(9309), // Rule ID 6073 //
3643 /* 9244 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3644 /* 9247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3645 /* 9251 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3646 /* 9255 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3647 /* 9259 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3648 /* 9263 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3649 /* 9267 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3650 /* 9272 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3651 /* 9277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3652 /* 9281 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3653 /* 9283 */ // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3654 /* 9283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16),
3655 /* 9286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3656 /* 9288 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3657 /* 9290 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3658 /* 9294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3659 /* 9298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3660 /* 9301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3661 /* 9307 */ GIR_RootConstrainSelectedInstOperands,
3662 /* 9308 */ // GIR_Coverage, 6073,
3663 /* 9308 */ GIR_EraseRootFromParent_Done,
3664 /* 9309 */ // Label 211: @9309
3665 /* 9309 */ GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(9366), // Rule ID 6046 //
3666 /* 9314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3667 /* 9317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3668 /* 9321 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3669 /* 9325 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3670 /* 9329 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3671 /* 9333 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3672 /* 9338 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3673 /* 9342 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3674 /* 9344 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3675 /* 9344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3676 /* 9347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3677 /* 9349 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
3678 /* 9351 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3679 /* 9355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3680 /* 9358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3681 /* 9364 */ GIR_RootConstrainSelectedInstOperands,
3682 /* 9365 */ // GIR_Coverage, 6046,
3683 /* 9365 */ GIR_EraseRootFromParent_Done,
3684 /* 9366 */ // Label 212: @9366
3685 /* 9366 */ GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(9423), // Rule ID 6042 //
3686 /* 9371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3687 /* 9374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3688 /* 9378 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3689 /* 9382 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3690 /* 9386 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3691 /* 9390 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3692 /* 9395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3693 /* 9399 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3694 /* 9401 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3695 /* 9401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16),
3696 /* 9404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3697 /* 9406 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
3698 /* 9408 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3699 /* 9412 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3700 /* 9415 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3701 /* 9421 */ GIR_RootConstrainSelectedInstOperands,
3702 /* 9422 */ // GIR_Coverage, 6042,
3703 /* 9422 */ GIR_EraseRootFromParent_Done,
3704 /* 9423 */ // Label 213: @9423
3705 /* 9423 */ GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(9480), // Rule ID 6045 //
3706 /* 9428 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3707 /* 9431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3708 /* 9435 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3709 /* 9439 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3710 /* 9443 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3711 /* 9447 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3712 /* 9452 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3713 /* 9456 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3714 /* 9458 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3715 /* 9458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3716 /* 9461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3717 /* 9463 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
3718 /* 9465 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3719 /* 9469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3720 /* 9472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3721 /* 9478 */ GIR_RootConstrainSelectedInstOperands,
3722 /* 9479 */ // GIR_Coverage, 6045,
3723 /* 9479 */ GIR_EraseRootFromParent_Done,
3724 /* 9480 */ // Label 214: @9480
3725 /* 9480 */ GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(9550), // Rule ID 1345 //
3726 /* 9485 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3727 /* 9488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3728 /* 9492 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3729 /* 9496 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3730 /* 9500 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3731 /* 9504 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3732 /* 9508 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3733 /* 9512 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3734 /* 9517 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3735 /* 9522 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3736 /* 9524 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3737 /* 9524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16),
3738 /* 9527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3739 /* 9529 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3740 /* 9531 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3741 /* 9535 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3742 /* 9539 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3743 /* 9542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3744 /* 9548 */ GIR_RootConstrainSelectedInstOperands,
3745 /* 9549 */ // GIR_Coverage, 1345,
3746 /* 9549 */ GIR_EraseRootFromParent_Done,
3747 /* 9550 */ // Label 215: @9550
3748 /* 9550 */ GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(9620), // Rule ID 1351 //
3749 /* 9555 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3750 /* 9558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3751 /* 9562 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3752 /* 9566 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3753 /* 9570 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3754 /* 9574 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3755 /* 9578 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3756 /* 9582 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3757 /* 9587 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3758 /* 9592 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3759 /* 9594 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3760 /* 9594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16),
3761 /* 9597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3762 /* 9599 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3763 /* 9601 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3764 /* 9605 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3765 /* 9609 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3766 /* 9612 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3767 /* 9618 */ GIR_RootConstrainSelectedInstOperands,
3768 /* 9619 */ // GIR_Coverage, 1351,
3769 /* 9619 */ GIR_EraseRootFromParent_Done,
3770 /* 9620 */ // Label 216: @9620
3771 /* 9620 */ GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(9690), // Rule ID 1011 //
3772 /* 9625 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3773 /* 9628 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3774 /* 9632 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3775 /* 9636 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3776 /* 9640 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3777 /* 9644 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3778 /* 9648 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3779 /* 9652 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3780 /* 9657 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3781 /* 9662 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3782 /* 9664 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3783 /* 9664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16),
3784 /* 9667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3785 /* 9669 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3786 /* 9671 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3787 /* 9675 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3788 /* 9679 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3789 /* 9682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3790 /* 9688 */ GIR_RootConstrainSelectedInstOperands,
3791 /* 9689 */ // GIR_Coverage, 1011,
3792 /* 9689 */ GIR_EraseRootFromParent_Done,
3793 /* 9690 */ // Label 217: @9690
3794 /* 9690 */ GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(9747), // Rule ID 907 //
3795 /* 9695 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3796 /* 9698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3797 /* 9702 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3798 /* 9706 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3799 /* 9710 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3800 /* 9714 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3801 /* 9718 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3802 /* 9723 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3803 /* 9725 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3804 /* 9725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3805 /* 9728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3806 /* 9730 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3807 /* 9732 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3808 /* 9736 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3809 /* 9739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3810 /* 9745 */ GIR_RootConstrainSelectedInstOperands,
3811 /* 9746 */ // GIR_Coverage, 907,
3812 /* 9746 */ GIR_EraseRootFromParent_Done,
3813 /* 9747 */ // Label 218: @9747
3814 /* 9747 */ GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(9804), // Rule ID 903 //
3815 /* 9752 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3816 /* 9755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3817 /* 9759 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3818 /* 9763 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3819 /* 9767 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3820 /* 9771 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3821 /* 9775 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3822 /* 9780 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3823 /* 9782 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3824 /* 9782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16),
3825 /* 9785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3826 /* 9787 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3827 /* 9789 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3828 /* 9793 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3829 /* 9796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3830 /* 9802 */ GIR_RootConstrainSelectedInstOperands,
3831 /* 9803 */ // GIR_Coverage, 903,
3832 /* 9803 */ GIR_EraseRootFromParent_Done,
3833 /* 9804 */ // Label 219: @9804
3834 /* 9804 */ GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(9861), // Rule ID 906 //
3835 /* 9809 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3836 /* 9812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3837 /* 9816 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3838 /* 9820 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3839 /* 9824 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3840 /* 9828 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3841 /* 9832 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3842 /* 9837 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3843 /* 9839 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3844 /* 9839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3845 /* 9842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3846 /* 9844 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3847 /* 9846 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3848 /* 9850 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3849 /* 9853 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3850 /* 9859 */ GIR_RootConstrainSelectedInstOperands,
3851 /* 9860 */ // GIR_Coverage, 906,
3852 /* 9860 */ GIR_EraseRootFromParent_Done,
3853 /* 9861 */ // Label 220: @9861
3854 /* 9861 */ GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(9901), // Rule ID 880 //
3855 /* 9866 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3856 /* 9869 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3857 /* 9873 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3858 /* 9877 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3859 /* 9881 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3860 /* 9881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i16),
3861 /* 9884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3862 /* 9886 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3863 /* 9888 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3864 /* 9890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3865 /* 9893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3866 /* 9899 */ GIR_RootConstrainSelectedInstOperands,
3867 /* 9900 */ // GIR_Coverage, 880,
3868 /* 9900 */ GIR_EraseRootFromParent_Done,
3869 /* 9901 */ // Label 221: @9901
3870 /* 9901 */ GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(9962), // Rule ID 3875 //
3871 /* 9906 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
3872 /* 9909 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3873 /* 9913 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3874 /* 9917 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3875 /* 9921 */ // (add:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
3876 /* 9921 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3877 /* 9924 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
3878 /* 9928 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3879 /* 9933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi16),
3880 /* 9936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
3881 /* 9938 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
3882 /* 9940 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
3883 /* 9942 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
3884 /* 9945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3885 /* 9951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3886 /* 9957 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3887 /* 9960 */ GIR_RootConstrainSelectedInstOperands,
3888 /* 9961 */ // GIR_Coverage, 3875,
3889 /* 9961 */ GIR_EraseRootFromParent_Done,
3890 /* 9962 */ // Label 222: @9962
3891 /* 9962 */ GIM_Reject,
3892 /* 9963 */ // Label 199: @9963
3893 /* 9963 */ GIM_Reject,
3894 /* 9964 */ // Label 99: @9964
3895 /* 9964 */ GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(10412),
3896 /* 9969 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
3897 /* 9972 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
3898 /* 9975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3899 /* 9979 */ GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(10045), // Rule ID 6183 //
3900 /* 9984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3901 /* 9987 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3902 /* 9991 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3903 /* 9995 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3904 /* 9999 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3905 /* 10003 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3906 /* 10008 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3907 /* 10013 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3908 /* 10017 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3909 /* 10019 */ // (add:{ *:[v2i32] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3910 /* 10019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32),
3911 /* 10022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3912 /* 10024 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3913 /* 10026 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3914 /* 10030 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3915 /* 10034 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3916 /* 10037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3917 /* 10043 */ GIR_RootConstrainSelectedInstOperands,
3918 /* 10044 */ // GIR_Coverage, 6183,
3919 /* 10044 */ GIR_EraseRootFromParent_Done,
3920 /* 10045 */ // Label 224: @10045
3921 /* 10045 */ GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(10111), // Rule ID 6189 //
3922 /* 10050 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3923 /* 10053 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3924 /* 10057 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3925 /* 10061 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3926 /* 10065 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3927 /* 10069 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3928 /* 10074 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3929 /* 10079 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3930 /* 10083 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3931 /* 10085 */ // (add:{ *:[v2i32] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3932 /* 10085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32),
3933 /* 10088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3934 /* 10090 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3935 /* 10092 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3936 /* 10096 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3937 /* 10100 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3938 /* 10103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3939 /* 10109 */ GIR_RootConstrainSelectedInstOperands,
3940 /* 10110 */ // GIR_Coverage, 6189,
3941 /* 10110 */ GIR_EraseRootFromParent_Done,
3942 /* 10111 */ // Label 225: @10111
3943 /* 10111 */ GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(10177), // Rule ID 6071 //
3944 /* 10116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3945 /* 10119 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3946 /* 10123 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3947 /* 10127 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3948 /* 10131 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3949 /* 10135 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3950 /* 10140 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3951 /* 10145 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3952 /* 10149 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3953 /* 10151 */ // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3954 /* 10151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32),
3955 /* 10154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3956 /* 10156 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3957 /* 10158 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3958 /* 10162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3959 /* 10166 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3960 /* 10169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3961 /* 10175 */ GIR_RootConstrainSelectedInstOperands,
3962 /* 10176 */ // GIR_Coverage, 6071,
3963 /* 10176 */ GIR_EraseRootFromParent_Done,
3964 /* 10177 */ // Label 226: @10177
3965 /* 10177 */ GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(10243), // Rule ID 1343 //
3966 /* 10182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3967 /* 10185 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3968 /* 10189 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3969 /* 10193 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3970 /* 10197 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3971 /* 10201 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3972 /* 10205 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3973 /* 10210 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3974 /* 10215 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3975 /* 10217 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3976 /* 10217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32),
3977 /* 10220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3978 /* 10222 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3979 /* 10224 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3980 /* 10228 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3981 /* 10232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3982 /* 10235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3983 /* 10241 */ GIR_RootConstrainSelectedInstOperands,
3984 /* 10242 */ // GIR_Coverage, 1343,
3985 /* 10242 */ GIR_EraseRootFromParent_Done,
3986 /* 10243 */ // Label 227: @10243
3987 /* 10243 */ GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(10309), // Rule ID 1349 //
3988 /* 10248 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3989 /* 10251 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3990 /* 10255 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3991 /* 10259 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3992 /* 10263 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3993 /* 10267 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3994 /* 10271 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3995 /* 10276 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3996 /* 10281 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3997 /* 10283 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3998 /* 10283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32),
3999 /* 10286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4000 /* 10288 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4001 /* 10290 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4002 /* 10294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4003 /* 10298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4004 /* 10301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4005 /* 10307 */ GIR_RootConstrainSelectedInstOperands,
4006 /* 10308 */ // GIR_Coverage, 1349,
4007 /* 10308 */ GIR_EraseRootFromParent_Done,
4008 /* 10309 */ // Label 228: @10309
4009 /* 10309 */ GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(10375), // Rule ID 1009 //
4010 /* 10314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4011 /* 10317 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4012 /* 10321 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4013 /* 10325 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4014 /* 10329 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4015 /* 10333 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
4016 /* 10337 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4017 /* 10342 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4018 /* 10347 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4019 /* 10349 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4020 /* 10349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32),
4021 /* 10352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4022 /* 10354 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4023 /* 10356 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4024 /* 10360 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4025 /* 10364 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4026 /* 10367 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4027 /* 10373 */ GIR_RootConstrainSelectedInstOperands,
4028 /* 10374 */ // GIR_Coverage, 1009,
4029 /* 10374 */ GIR_EraseRootFromParent_Done,
4030 /* 10375 */ // Label 229: @10375
4031 /* 10375 */ GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(10411), // Rule ID 878 //
4032 /* 10380 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4033 /* 10383 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4034 /* 10387 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4035 /* 10391 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4036 /* 10391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i32),
4037 /* 10394 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4038 /* 10396 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4039 /* 10398 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
4040 /* 10400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4041 /* 10403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4042 /* 10409 */ GIR_RootConstrainSelectedInstOperands,
4043 /* 10410 */ // GIR_Coverage, 878,
4044 /* 10410 */ GIR_EraseRootFromParent_Done,
4045 /* 10411 */ // Label 230: @10411
4046 /* 10411 */ GIM_Reject,
4047 /* 10412 */ // Label 223: @10412
4048 /* 10412 */ GIM_Reject,
4049 /* 10413 */ // Label 100: @10413
4050 /* 10413 */ GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(11976),
4051 /* 10418 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
4052 /* 10421 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
4053 /* 10424 */ GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(10496), // Rule ID 898 //
4054 /* 10429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4055 /* 10432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4056 /* 10436 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4057 /* 10440 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4058 /* 10444 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4059 /* 10448 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4060 /* 10453 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4061 /* 10457 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4062 /* 10461 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4063 /* 10465 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4064 /* 10470 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4065 /* 10472 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4066 /* 10472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
4067 /* 10475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4068 /* 10477 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4069 /* 10481 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4070 /* 10485 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4071 /* 10488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4072 /* 10494 */ GIR_RootConstrainSelectedInstOperands,
4073 /* 10495 */ // GIR_Coverage, 898,
4074 /* 10495 */ GIR_EraseRootFromParent_Done,
4075 /* 10496 */ // Label 232: @10496
4076 /* 10496 */ GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(10568), // Rule ID 897 //
4077 /* 10501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4078 /* 10504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4079 /* 10508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4080 /* 10512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4081 /* 10516 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4082 /* 10520 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4083 /* 10525 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4084 /* 10529 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4085 /* 10533 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4086 /* 10537 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4087 /* 10542 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4088 /* 10544 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4089 /* 10544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
4090 /* 10547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4091 /* 10549 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4092 /* 10553 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4093 /* 10557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4094 /* 10560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4095 /* 10566 */ GIR_RootConstrainSelectedInstOperands,
4096 /* 10567 */ // GIR_Coverage, 897,
4097 /* 10567 */ GIR_EraseRootFromParent_Done,
4098 /* 10568 */ // Label 233: @10568
4099 /* 10568 */ GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(10640), // Rule ID 889 //
4100 /* 10573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4101 /* 10576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4102 /* 10580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4103 /* 10584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4104 /* 10588 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4105 /* 10592 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4106 /* 10597 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4107 /* 10601 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
4108 /* 10605 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4109 /* 10609 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4110 /* 10614 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4111 /* 10616 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4112 /* 10616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv4i32),
4113 /* 10619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4114 /* 10621 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4115 /* 10625 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4116 /* 10629 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4117 /* 10632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4118 /* 10638 */ GIR_RootConstrainSelectedInstOperands,
4119 /* 10639 */ // GIR_Coverage, 889,
4120 /* 10639 */ GIR_EraseRootFromParent_Done,
4121 /* 10640 */ // Label 234: @10640
4122 /* 10640 */ GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(10722), // Rule ID 6194 //
4123 /* 10645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4124 /* 10648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4125 /* 10652 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4126 /* 10656 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4127 /* 10660 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4128 /* 10664 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4129 /* 10668 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
4130 /* 10672 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4131 /* 10676 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
4132 /* 10680 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4133 /* 10685 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4134 /* 10690 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4135 /* 10694 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4136 /* 10696 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4137 /* 10696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32),
4138 /* 10699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4139 /* 10701 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4140 /* 10703 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4141 /* 10707 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4142 /* 10711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4143 /* 10714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4144 /* 10720 */ GIR_RootConstrainSelectedInstOperands,
4145 /* 10721 */ // GIR_Coverage, 6194,
4146 /* 10721 */ GIR_EraseRootFromParent_Done,
4147 /* 10722 */ // Label 235: @10722
4148 /* 10722 */ GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(10804), // Rule ID 6197 //
4149 /* 10727 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4150 /* 10730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4151 /* 10734 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4152 /* 10738 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4153 /* 10742 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4154 /* 10746 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4155 /* 10750 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
4156 /* 10754 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4157 /* 10758 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
4158 /* 10762 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4159 /* 10767 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4160 /* 10772 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4161 /* 10776 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4162 /* 10778 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4163 /* 10778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32),
4164 /* 10781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4165 /* 10783 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4166 /* 10785 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4167 /* 10789 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4168 /* 10793 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4169 /* 10796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4170 /* 10802 */ GIR_RootConstrainSelectedInstOperands,
4171 /* 10803 */ // GIR_Coverage, 6197,
4172 /* 10803 */ GIR_EraseRootFromParent_Done,
4173 /* 10804 */ // Label 236: @10804
4174 /* 10804 */ GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(10876), // Rule ID 896 //
4175 /* 10809 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4176 /* 10812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4177 /* 10816 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4178 /* 10820 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4179 /* 10824 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4180 /* 10828 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4181 /* 10833 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4182 /* 10837 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4183 /* 10841 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4184 /* 10845 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4185 /* 10850 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4186 /* 10852 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4187 /* 10852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
4188 /* 10855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4189 /* 10857 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4190 /* 10861 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4191 /* 10865 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4192 /* 10868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4193 /* 10874 */ GIR_RootConstrainSelectedInstOperands,
4194 /* 10875 */ // GIR_Coverage, 896,
4195 /* 10875 */ GIR_EraseRootFromParent_Done,
4196 /* 10876 */ // Label 237: @10876
4197 /* 10876 */ GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(10948), // Rule ID 895 //
4198 /* 10881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4199 /* 10884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4200 /* 10888 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4201 /* 10892 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4202 /* 10896 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4203 /* 10900 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4204 /* 10905 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4205 /* 10909 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4206 /* 10913 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4207 /* 10917 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4208 /* 10922 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4209 /* 10924 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4210 /* 10924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
4211 /* 10927 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4212 /* 10929 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4213 /* 10933 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4214 /* 10937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4215 /* 10940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4216 /* 10946 */ GIR_RootConstrainSelectedInstOperands,
4217 /* 10947 */ // GIR_Coverage, 895,
4218 /* 10947 */ GIR_EraseRootFromParent_Done,
4219 /* 10948 */ // Label 238: @10948
4220 /* 10948 */ GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(11030), // Rule ID 1354 //
4221 /* 10953 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4222 /* 10956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4223 /* 10960 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4224 /* 10964 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4225 /* 10968 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4226 /* 10972 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4227 /* 10976 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4228 /* 10980 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
4229 /* 10984 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4230 /* 10988 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
4231 /* 10992 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4232 /* 10997 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4233 /* 11002 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4234 /* 11004 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4235 /* 11004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32),
4236 /* 11007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4237 /* 11009 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4238 /* 11011 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4239 /* 11015 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4240 /* 11019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4241 /* 11022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4242 /* 11028 */ GIR_RootConstrainSelectedInstOperands,
4243 /* 11029 */ // GIR_Coverage, 1354,
4244 /* 11029 */ GIR_EraseRootFromParent_Done,
4245 /* 11030 */ // Label 239: @11030
4246 /* 11030 */ GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(11112), // Rule ID 1357 //
4247 /* 11035 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4248 /* 11038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4249 /* 11042 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4250 /* 11046 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4251 /* 11050 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4252 /* 11054 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4253 /* 11058 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4254 /* 11062 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
4255 /* 11066 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4256 /* 11070 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
4257 /* 11074 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4258 /* 11079 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4259 /* 11084 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4260 /* 11086 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4261 /* 11086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32),
4262 /* 11089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4263 /* 11091 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4264 /* 11093 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4265 /* 11097 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4266 /* 11101 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4267 /* 11104 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4268 /* 11110 */ GIR_RootConstrainSelectedInstOperands,
4269 /* 11111 */ // GIR_Coverage, 1357,
4270 /* 11111 */ GIR_EraseRootFromParent_Done,
4271 /* 11112 */ // Label 240: @11112
4272 /* 11112 */ GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(11182), // Rule ID 6186 //
4273 /* 11117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4274 /* 11120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4275 /* 11124 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4276 /* 11128 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
4277 /* 11132 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4278 /* 11136 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4279 /* 11140 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4280 /* 11145 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4281 /* 11150 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4282 /* 11154 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4283 /* 11156 */ // (add:{ *:[v4i32] } (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4284 /* 11156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32),
4285 /* 11159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4286 /* 11161 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4287 /* 11163 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4288 /* 11167 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4289 /* 11171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4290 /* 11174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4291 /* 11180 */ GIR_RootConstrainSelectedInstOperands,
4292 /* 11181 */ // GIR_Coverage, 6186,
4293 /* 11181 */ GIR_EraseRootFromParent_Done,
4294 /* 11182 */ // Label 241: @11182
4295 /* 11182 */ GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(11252), // Rule ID 6192 //
4296 /* 11187 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4297 /* 11190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4298 /* 11194 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4299 /* 11198 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
4300 /* 11202 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4301 /* 11206 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4302 /* 11210 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4303 /* 11215 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4304 /* 11220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4305 /* 11224 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4306 /* 11226 */ // (add:{ *:[v4i32] } (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4307 /* 11226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32),
4308 /* 11229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4309 /* 11231 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4310 /* 11233 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4311 /* 11237 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4312 /* 11241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4313 /* 11244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4314 /* 11250 */ GIR_RootConstrainSelectedInstOperands,
4315 /* 11251 */ // GIR_Coverage, 6192,
4316 /* 11251 */ GIR_EraseRootFromParent_Done,
4317 /* 11252 */ // Label 242: @11252
4318 /* 11252 */ GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(11322), // Rule ID 6074 //
4319 /* 11257 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4320 /* 11260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4321 /* 11264 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4322 /* 11268 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4323 /* 11272 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4324 /* 11276 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4325 /* 11280 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4326 /* 11285 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4327 /* 11290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4328 /* 11294 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4329 /* 11296 */ // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4330 /* 11296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32),
4331 /* 11299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4332 /* 11301 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4333 /* 11303 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4334 /* 11307 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4335 /* 11311 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4336 /* 11314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4337 /* 11320 */ GIR_RootConstrainSelectedInstOperands,
4338 /* 11321 */ // GIR_Coverage, 6074,
4339 /* 11321 */ GIR_EraseRootFromParent_Done,
4340 /* 11322 */ // Label 243: @11322
4341 /* 11322 */ GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(11379), // Rule ID 6048 //
4342 /* 11327 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4343 /* 11330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4344 /* 11334 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4345 /* 11338 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4346 /* 11342 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4347 /* 11346 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4348 /* 11351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4349 /* 11355 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4350 /* 11357 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4351 /* 11357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
4352 /* 11360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4353 /* 11362 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4354 /* 11364 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4355 /* 11368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4356 /* 11371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4357 /* 11377 */ GIR_RootConstrainSelectedInstOperands,
4358 /* 11378 */ // GIR_Coverage, 6048,
4359 /* 11378 */ GIR_EraseRootFromParent_Done,
4360 /* 11379 */ // Label 244: @11379
4361 /* 11379 */ GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(11436), // Rule ID 6043 //
4362 /* 11384 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4363 /* 11387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4364 /* 11391 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4365 /* 11395 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4366 /* 11399 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4367 /* 11403 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4368 /* 11408 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4369 /* 11412 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4370 /* 11414 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4371 /* 11414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32),
4372 /* 11417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4373 /* 11419 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4374 /* 11421 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4375 /* 11425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4376 /* 11428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4377 /* 11434 */ GIR_RootConstrainSelectedInstOperands,
4378 /* 11435 */ // GIR_Coverage, 6043,
4379 /* 11435 */ GIR_EraseRootFromParent_Done,
4380 /* 11436 */ // Label 245: @11436
4381 /* 11436 */ GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(11493), // Rule ID 6047 //
4382 /* 11441 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4383 /* 11444 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4384 /* 11448 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4385 /* 11452 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4386 /* 11456 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4387 /* 11460 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4388 /* 11465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4389 /* 11469 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4390 /* 11471 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4391 /* 11471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
4392 /* 11474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4393 /* 11476 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4394 /* 11478 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4395 /* 11482 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4396 /* 11485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4397 /* 11491 */ GIR_RootConstrainSelectedInstOperands,
4398 /* 11492 */ // GIR_Coverage, 6047,
4399 /* 11492 */ GIR_EraseRootFromParent_Done,
4400 /* 11493 */ // Label 246: @11493
4401 /* 11493 */ GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(11563), // Rule ID 1346 //
4402 /* 11498 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4403 /* 11501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4404 /* 11505 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4405 /* 11509 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4406 /* 11513 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
4407 /* 11517 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4408 /* 11521 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4409 /* 11525 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4410 /* 11530 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4411 /* 11535 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4412 /* 11537 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4413 /* 11537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32),
4414 /* 11540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4415 /* 11542 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4416 /* 11544 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4417 /* 11548 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4418 /* 11552 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4419 /* 11555 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4420 /* 11561 */ GIR_RootConstrainSelectedInstOperands,
4421 /* 11562 */ // GIR_Coverage, 1346,
4422 /* 11562 */ GIR_EraseRootFromParent_Done,
4423 /* 11563 */ // Label 247: @11563
4424 /* 11563 */ GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(11633), // Rule ID 1352 //
4425 /* 11568 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4426 /* 11571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4427 /* 11575 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4428 /* 11579 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4429 /* 11583 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
4430 /* 11587 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4431 /* 11591 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4432 /* 11595 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4433 /* 11600 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4434 /* 11605 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4435 /* 11607 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4436 /* 11607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32),
4437 /* 11610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4438 /* 11612 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4439 /* 11614 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4440 /* 11618 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4441 /* 11622 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4442 /* 11625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4443 /* 11631 */ GIR_RootConstrainSelectedInstOperands,
4444 /* 11632 */ // GIR_Coverage, 1352,
4445 /* 11632 */ GIR_EraseRootFromParent_Done,
4446 /* 11633 */ // Label 248: @11633
4447 /* 11633 */ GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(11703), // Rule ID 1012 //
4448 /* 11638 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4449 /* 11641 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4450 /* 11645 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4451 /* 11649 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4452 /* 11653 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4453 /* 11657 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4454 /* 11661 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4455 /* 11665 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4456 /* 11670 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4457 /* 11675 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4458 /* 11677 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4459 /* 11677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32),
4460 /* 11680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4461 /* 11682 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4462 /* 11684 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4463 /* 11688 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4464 /* 11692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4465 /* 11695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4466 /* 11701 */ GIR_RootConstrainSelectedInstOperands,
4467 /* 11702 */ // GIR_Coverage, 1012,
4468 /* 11702 */ GIR_EraseRootFromParent_Done,
4469 /* 11703 */ // Label 249: @11703
4470 /* 11703 */ GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(11760), // Rule ID 909 //
4471 /* 11708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4472 /* 11711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4473 /* 11715 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4474 /* 11719 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4475 /* 11723 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4476 /* 11727 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4477 /* 11731 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4478 /* 11736 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4479 /* 11738 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4480 /* 11738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
4481 /* 11741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4482 /* 11743 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4483 /* 11745 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4484 /* 11749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4485 /* 11752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4486 /* 11758 */ GIR_RootConstrainSelectedInstOperands,
4487 /* 11759 */ // GIR_Coverage, 909,
4488 /* 11759 */ GIR_EraseRootFromParent_Done,
4489 /* 11760 */ // Label 250: @11760
4490 /* 11760 */ GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(11817), // Rule ID 904 //
4491 /* 11765 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4492 /* 11768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4493 /* 11772 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4494 /* 11776 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4495 /* 11780 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4496 /* 11784 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4497 /* 11788 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4498 /* 11793 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4499 /* 11795 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4500 /* 11795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32),
4501 /* 11798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4502 /* 11800 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4503 /* 11802 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4504 /* 11806 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4505 /* 11809 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4506 /* 11815 */ GIR_RootConstrainSelectedInstOperands,
4507 /* 11816 */ // GIR_Coverage, 904,
4508 /* 11816 */ GIR_EraseRootFromParent_Done,
4509 /* 11817 */ // Label 251: @11817
4510 /* 11817 */ GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(11874), // Rule ID 908 //
4511 /* 11822 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4512 /* 11825 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4513 /* 11829 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4514 /* 11833 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4515 /* 11837 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4516 /* 11841 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4517 /* 11845 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4518 /* 11850 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4519 /* 11852 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4520 /* 11852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
4521 /* 11855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4522 /* 11857 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4523 /* 11859 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4524 /* 11863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4525 /* 11866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4526 /* 11872 */ GIR_RootConstrainSelectedInstOperands,
4527 /* 11873 */ // GIR_Coverage, 908,
4528 /* 11873 */ GIR_EraseRootFromParent_Done,
4529 /* 11874 */ // Label 252: @11874
4530 /* 11874 */ GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(11914), // Rule ID 881 //
4531 /* 11879 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4532 /* 11882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4533 /* 11886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4534 /* 11890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4535 /* 11894 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4536 /* 11894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i32),
4537 /* 11897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4538 /* 11899 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4539 /* 11901 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
4540 /* 11903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4541 /* 11906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4542 /* 11912 */ GIR_RootConstrainSelectedInstOperands,
4543 /* 11913 */ // GIR_Coverage, 881,
4544 /* 11913 */ GIR_EraseRootFromParent_Done,
4545 /* 11914 */ // Label 253: @11914
4546 /* 11914 */ GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(11975), // Rule ID 3879 //
4547 /* 11919 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
4548 /* 11922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4549 /* 11926 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4550 /* 11930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4551 /* 11934 */ // (add:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
4552 /* 11934 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4553 /* 11937 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
4554 /* 11941 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4555 /* 11946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi32),
4556 /* 11949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
4557 /* 11951 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
4558 /* 11953 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
4559 /* 11955 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
4560 /* 11958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4561 /* 11964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4562 /* 11970 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4563 /* 11973 */ GIR_RootConstrainSelectedInstOperands,
4564 /* 11974 */ // GIR_Coverage, 3879,
4565 /* 11974 */ GIR_EraseRootFromParent_Done,
4566 /* 11975 */ // Label 254: @11975
4567 /* 11975 */ GIM_Reject,
4568 /* 11976 */ // Label 231: @11976
4569 /* 11976 */ GIM_Reject,
4570 /* 11977 */ // Label 101: @11977
4571 /* 11977 */ GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(12999),
4572 /* 11982 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4573 /* 11985 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
4574 /* 11988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4575 /* 11992 */ GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(12060), // Rule ID 902 //
4576 /* 11997 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4577 /* 12000 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4578 /* 12004 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4579 /* 12008 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4580 /* 12012 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4581 /* 12017 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4582 /* 12021 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4583 /* 12025 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4584 /* 12029 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4585 /* 12034 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4586 /* 12036 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4587 /* 12036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
4588 /* 12039 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4589 /* 12041 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4590 /* 12045 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4591 /* 12049 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4592 /* 12052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4593 /* 12058 */ GIR_RootConstrainSelectedInstOperands,
4594 /* 12059 */ // GIR_Coverage, 902,
4595 /* 12059 */ GIR_EraseRootFromParent_Done,
4596 /* 12060 */ // Label 256: @12060
4597 /* 12060 */ GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(12128), // Rule ID 901 //
4598 /* 12065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4599 /* 12068 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4600 /* 12072 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4601 /* 12076 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4602 /* 12080 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4603 /* 12085 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4604 /* 12089 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4605 /* 12093 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4606 /* 12097 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4607 /* 12102 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4608 /* 12104 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4609 /* 12104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
4610 /* 12107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4611 /* 12109 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4612 /* 12113 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4613 /* 12117 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4614 /* 12120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4615 /* 12126 */ GIR_RootConstrainSelectedInstOperands,
4616 /* 12127 */ // GIR_Coverage, 901,
4617 /* 12127 */ GIR_EraseRootFromParent_Done,
4618 /* 12128 */ // Label 257: @12128
4619 /* 12128 */ GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(12196), // Rule ID 890 //
4620 /* 12133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4621 /* 12136 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4622 /* 12140 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4623 /* 12144 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4624 /* 12148 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4625 /* 12153 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4626 /* 12157 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
4627 /* 12161 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4628 /* 12165 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4629 /* 12170 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4630 /* 12172 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4631 /* 12172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv2i64),
4632 /* 12175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4633 /* 12177 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4634 /* 12181 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4635 /* 12185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4636 /* 12188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4637 /* 12194 */ GIR_RootConstrainSelectedInstOperands,
4638 /* 12195 */ // GIR_Coverage, 890,
4639 /* 12195 */ GIR_EraseRootFromParent_Done,
4640 /* 12196 */ // Label 258: @12196
4641 /* 12196 */ GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(12274), // Rule ID 6195 //
4642 /* 12201 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4643 /* 12204 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4644 /* 12208 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4645 /* 12212 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4646 /* 12216 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4647 /* 12220 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
4648 /* 12224 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4649 /* 12228 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
4650 /* 12232 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4651 /* 12237 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4652 /* 12242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4653 /* 12246 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4654 /* 12248 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4655 /* 12248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64),
4656 /* 12251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4657 /* 12253 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4658 /* 12255 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4659 /* 12259 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4660 /* 12263 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4661 /* 12266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4662 /* 12272 */ GIR_RootConstrainSelectedInstOperands,
4663 /* 12273 */ // GIR_Coverage, 6195,
4664 /* 12273 */ GIR_EraseRootFromParent_Done,
4665 /* 12274 */ // Label 259: @12274
4666 /* 12274 */ GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(12352), // Rule ID 6198 //
4667 /* 12279 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4668 /* 12282 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4669 /* 12286 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4670 /* 12290 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4671 /* 12294 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4672 /* 12298 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
4673 /* 12302 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4674 /* 12306 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
4675 /* 12310 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4676 /* 12315 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4677 /* 12320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4678 /* 12324 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4679 /* 12326 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4680 /* 12326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64),
4681 /* 12329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4682 /* 12331 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4683 /* 12333 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4684 /* 12337 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4685 /* 12341 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4686 /* 12344 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4687 /* 12350 */ GIR_RootConstrainSelectedInstOperands,
4688 /* 12351 */ // GIR_Coverage, 6198,
4689 /* 12351 */ GIR_EraseRootFromParent_Done,
4690 /* 12352 */ // Label 260: @12352
4691 /* 12352 */ GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(12420), // Rule ID 900 //
4692 /* 12357 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4693 /* 12360 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4694 /* 12364 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4695 /* 12368 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4696 /* 12372 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4697 /* 12377 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4698 /* 12381 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4699 /* 12385 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4700 /* 12389 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4701 /* 12394 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4702 /* 12396 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4703 /* 12396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
4704 /* 12399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4705 /* 12401 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4706 /* 12405 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4707 /* 12409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4708 /* 12412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4709 /* 12418 */ GIR_RootConstrainSelectedInstOperands,
4710 /* 12419 */ // GIR_Coverage, 900,
4711 /* 12419 */ GIR_EraseRootFromParent_Done,
4712 /* 12420 */ // Label 261: @12420
4713 /* 12420 */ GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(12488), // Rule ID 899 //
4714 /* 12425 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4715 /* 12428 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4716 /* 12432 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4717 /* 12436 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4718 /* 12440 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4719 /* 12445 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4720 /* 12449 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4721 /* 12453 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4722 /* 12457 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4723 /* 12462 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4724 /* 12464 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4725 /* 12464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
4726 /* 12467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4727 /* 12469 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4728 /* 12473 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4729 /* 12477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4730 /* 12480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4731 /* 12486 */ GIR_RootConstrainSelectedInstOperands,
4732 /* 12487 */ // GIR_Coverage, 899,
4733 /* 12487 */ GIR_EraseRootFromParent_Done,
4734 /* 12488 */ // Label 262: @12488
4735 /* 12488 */ GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(12566), // Rule ID 1355 //
4736 /* 12493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4737 /* 12496 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4738 /* 12500 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4739 /* 12504 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4740 /* 12508 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4741 /* 12512 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4742 /* 12516 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
4743 /* 12520 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4744 /* 12524 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
4745 /* 12528 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4746 /* 12533 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4747 /* 12538 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4748 /* 12540 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4749 /* 12540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64),
4750 /* 12543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4751 /* 12545 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4752 /* 12547 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4753 /* 12551 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4754 /* 12555 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4755 /* 12558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4756 /* 12564 */ GIR_RootConstrainSelectedInstOperands,
4757 /* 12565 */ // GIR_Coverage, 1355,
4758 /* 12565 */ GIR_EraseRootFromParent_Done,
4759 /* 12566 */ // Label 263: @12566
4760 /* 12566 */ GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(12644), // Rule ID 1358 //
4761 /* 12571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4762 /* 12574 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4763 /* 12578 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4764 /* 12582 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4765 /* 12586 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4766 /* 12590 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4767 /* 12594 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
4768 /* 12598 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4769 /* 12602 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
4770 /* 12606 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4771 /* 12611 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4772 /* 12616 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4773 /* 12618 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4774 /* 12618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64),
4775 /* 12621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4776 /* 12623 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4777 /* 12625 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4778 /* 12629 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4779 /* 12633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4780 /* 12636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4781 /* 12642 */ GIR_RootConstrainSelectedInstOperands,
4782 /* 12643 */ // GIR_Coverage, 1358,
4783 /* 12643 */ GIR_EraseRootFromParent_Done,
4784 /* 12644 */ // Label 264: @12644
4785 /* 12644 */ GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(12697), // Rule ID 6050 //
4786 /* 12649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4787 /* 12652 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4788 /* 12656 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4789 /* 12660 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4790 /* 12664 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4791 /* 12669 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4792 /* 12673 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4793 /* 12675 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4794 /* 12675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
4795 /* 12678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4796 /* 12680 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4797 /* 12682 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4798 /* 12686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4799 /* 12689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4800 /* 12695 */ GIR_RootConstrainSelectedInstOperands,
4801 /* 12696 */ // GIR_Coverage, 6050,
4802 /* 12696 */ GIR_EraseRootFromParent_Done,
4803 /* 12697 */ // Label 265: @12697
4804 /* 12697 */ GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(12750), // Rule ID 6044 //
4805 /* 12702 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4806 /* 12705 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4807 /* 12709 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4808 /* 12713 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4809 /* 12717 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4810 /* 12722 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4811 /* 12726 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4812 /* 12728 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4813 /* 12728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64),
4814 /* 12731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4815 /* 12733 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4816 /* 12735 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4817 /* 12739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4818 /* 12742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4819 /* 12748 */ GIR_RootConstrainSelectedInstOperands,
4820 /* 12749 */ // GIR_Coverage, 6044,
4821 /* 12749 */ GIR_EraseRootFromParent_Done,
4822 /* 12750 */ // Label 266: @12750
4823 /* 12750 */ GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(12803), // Rule ID 6049 //
4824 /* 12755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4825 /* 12758 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4826 /* 12762 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4827 /* 12766 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4828 /* 12770 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4829 /* 12775 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4830 /* 12779 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4831 /* 12781 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4832 /* 12781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
4833 /* 12784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4834 /* 12786 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4835 /* 12788 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4836 /* 12792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4837 /* 12795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4838 /* 12801 */ GIR_RootConstrainSelectedInstOperands,
4839 /* 12802 */ // GIR_Coverage, 6049,
4840 /* 12802 */ GIR_EraseRootFromParent_Done,
4841 /* 12803 */ // Label 267: @12803
4842 /* 12803 */ GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(12856), // Rule ID 911 //
4843 /* 12808 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4844 /* 12811 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4845 /* 12815 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4846 /* 12819 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4847 /* 12823 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4848 /* 12827 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4849 /* 12832 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4850 /* 12834 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4851 /* 12834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
4852 /* 12837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4853 /* 12839 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4854 /* 12841 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4855 /* 12845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4856 /* 12848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4857 /* 12854 */ GIR_RootConstrainSelectedInstOperands,
4858 /* 12855 */ // GIR_Coverage, 911,
4859 /* 12855 */ GIR_EraseRootFromParent_Done,
4860 /* 12856 */ // Label 268: @12856
4861 /* 12856 */ GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(12909), // Rule ID 905 //
4862 /* 12861 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4863 /* 12864 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4864 /* 12868 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4865 /* 12872 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4866 /* 12876 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4867 /* 12880 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4868 /* 12885 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4869 /* 12887 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4870 /* 12887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64),
4871 /* 12890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4872 /* 12892 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4873 /* 12894 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4874 /* 12898 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4875 /* 12901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4876 /* 12907 */ GIR_RootConstrainSelectedInstOperands,
4877 /* 12908 */ // GIR_Coverage, 905,
4878 /* 12908 */ GIR_EraseRootFromParent_Done,
4879 /* 12909 */ // Label 269: @12909
4880 /* 12909 */ GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(12962), // Rule ID 910 //
4881 /* 12914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4882 /* 12917 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4883 /* 12921 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4884 /* 12925 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4885 /* 12929 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4886 /* 12933 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4887 /* 12938 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4888 /* 12940 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4889 /* 12940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
4890 /* 12943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4891 /* 12945 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4892 /* 12947 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4893 /* 12951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4894 /* 12954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4895 /* 12960 */ GIR_RootConstrainSelectedInstOperands,
4896 /* 12961 */ // GIR_Coverage, 910,
4897 /* 12961 */ GIR_EraseRootFromParent_Done,
4898 /* 12962 */ // Label 270: @12962
4899 /* 12962 */ GIM_Try, /*On fail goto*//*Label 271*/ GIMT_Encode4(12998), // Rule ID 883 //
4900 /* 12967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4901 /* 12970 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4902 /* 12974 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4903 /* 12978 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
4904 /* 12978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i64),
4905 /* 12981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4906 /* 12983 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4907 /* 12985 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
4908 /* 12987 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4909 /* 12990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4910 /* 12996 */ GIR_RootConstrainSelectedInstOperands,
4911 /* 12997 */ // GIR_Coverage, 883,
4912 /* 12997 */ GIR_EraseRootFromParent_Done,
4913 /* 12998 */ // Label 271: @12998
4914 /* 12998 */ GIM_Reject,
4915 /* 12999 */ // Label 255: @12999
4916 /* 12999 */ GIM_Reject,
4917 /* 13000 */ // Label 102: @13000
4918 /* 13000 */ GIM_Reject,
4919 /* 13001 */ // Label 1: @13001
4920 /* 13001 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 281*/ GIMT_Encode4(16236),
4921 /* 13012 */ /*GILLT_s32*//*Label 272*/ GIMT_Encode4(13064),
4922 /* 13016 */ /*GILLT_s64*//*Label 273*/ GIMT_Encode4(13678), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
4923 /* 13036 */ /*GILLT_v8s8*//*Label 274*/ GIMT_Encode4(13725),
4924 /* 13040 */ /*GILLT_v16s8*//*Label 275*/ GIMT_Encode4(13840),
4925 /* 13044 */ /*GILLT_v4s16*//*Label 276*/ GIMT_Encode4(14024),
4926 /* 13048 */ /*GILLT_v8s16*//*Label 277*/ GIMT_Encode4(14139),
4927 /* 13052 */ /*GILLT_v2s32*//*Label 278*/ GIMT_Encode4(14854),
4928 /* 13056 */ /*GILLT_v4s32*//*Label 279*/ GIMT_Encode4(14969),
4929 /* 13060 */ /*GILLT_v2s64*//*Label 280*/ GIMT_Encode4(15684),
4930 /* 13064 */ // Label 272: @13064
4931 /* 13064 */ GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(13677),
4932 /* 13069 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
4933 /* 13072 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4934 /* 13075 */ GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(13119), // Rule ID 329 //
4935 /* 13080 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
4936 /* 13083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
4937 /* 13087 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
4938 /* 13091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
4939 /* 13095 */ // (sub:{ *:[i32] } 0:{ *:[i32] }, tGPR:{ *:[i32] }:$Rn) => (tRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)
4940 /* 13095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tRSB),
4941 /* 13098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4942 /* 13100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
4943 /* 13106 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4944 /* 13108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4945 /* 13111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4946 /* 13117 */ GIR_RootConstrainSelectedInstOperands,
4947 /* 13118 */ // GIR_Coverage, 329,
4948 /* 13118 */ GIR_EraseRootFromParent_Done,
4949 /* 13119 */ // Label 283: @13119
4950 /* 13119 */ GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(13176), // Rule ID 95 //
4951 /* 13124 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
4952 /* 13127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4953 /* 13131 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4954 /* 13135 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4955 /* 13139 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
4956 /* 13143 */ // MIs[1] Operand 1
4957 /* 13143 */ // No operand predicates
4958 /* 13143 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4959 /* 13147 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4960 /* 13149 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn) => (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4961 /* 13149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RSBri),
4962 /* 13152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4963 /* 13154 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4964 /* 13156 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4965 /* 13159 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4966 /* 13162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4967 /* 13168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4968 /* 13174 */ GIR_RootConstrainSelectedInstOperands,
4969 /* 13175 */ // GIR_Coverage, 95,
4970 /* 13175 */ GIR_EraseRootFromParent_Done,
4971 /* 13176 */ // Label 284: @13176
4972 /* 13176 */ GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(13233), // Rule ID 426 //
4973 /* 13181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
4974 /* 13184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4975 /* 13188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4976 /* 13192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4977 /* 13196 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
4978 /* 13200 */ // MIs[1] Operand 1
4979 /* 13200 */ // No operand predicates
4980 /* 13200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4981 /* 13204 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4982 /* 13206 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn) => (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4983 /* 13206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RSBri),
4984 /* 13209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4985 /* 13211 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4986 /* 13213 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4987 /* 13216 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4988 /* 13219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4989 /* 13225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4990 /* 13231 */ GIR_RootConstrainSelectedInstOperands,
4991 /* 13232 */ // GIR_Coverage, 426,
4992 /* 13232 */ GIR_EraseRootFromParent_Done,
4993 /* 13233 */ // Label 285: @13233
4994 /* 13233 */ GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(13290), // Rule ID 75 //
4995 /* 13238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
4996 /* 13241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4997 /* 13245 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4998 /* 13249 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4999 /* 13253 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5000 /* 13257 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
5001 /* 13261 */ // MIs[1] Operand 1
5002 /* 13261 */ // No operand predicates
5003 /* 13261 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5004 /* 13263 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5005 /* 13263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBri),
5006 /* 13266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5007 /* 13268 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5008 /* 13270 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
5009 /* 13273 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5010 /* 13276 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5011 /* 13282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5012 /* 13288 */ GIR_RootConstrainSelectedInstOperands,
5013 /* 13289 */ // GIR_Coverage, 75,
5014 /* 13289 */ GIR_EraseRootFromParent_Done,
5015 /* 13290 */ // Label 286: @13290
5016 /* 13290 */ GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(13347), // Rule ID 410 //
5017 /* 13295 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
5018 /* 13298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5019 /* 13302 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5020 /* 13306 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5021 /* 13310 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5022 /* 13314 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
5023 /* 13318 */ // MIs[1] Operand 1
5024 /* 13318 */ // No operand predicates
5025 /* 13318 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5026 /* 13320 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5027 /* 13320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri),
5028 /* 13323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5029 /* 13325 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5030 /* 13327 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
5031 /* 13330 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5032 /* 13333 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5033 /* 13339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5034 /* 13345 */ GIR_RootConstrainSelectedInstOperands,
5035 /* 13346 */ // GIR_Coverage, 410,
5036 /* 13346 */ GIR_EraseRootFromParent_Done,
5037 /* 13347 */ // Label 287: @13347
5038 /* 13347 */ GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(13398), // Rule ID 411 //
5039 /* 13352 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
5040 /* 13355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5041 /* 13359 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5042 /* 13363 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5043 /* 13367 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5044 /* 13371 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095),
5045 /* 13375 */ // MIs[1] Operand 1
5046 /* 13375 */ // No operand predicates
5047 /* 13375 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5048 /* 13377 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5049 /* 13377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri12),
5050 /* 13380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5051 /* 13382 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5052 /* 13384 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
5053 /* 13387 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5054 /* 13390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5055 /* 13396 */ GIR_RootConstrainSelectedInstOperands,
5056 /* 13397 */ // GIR_Coverage, 411,
5057 /* 13397 */ GIR_EraseRootFromParent_Done,
5058 /* 13398 */ // Label 288: @13398
5059 /* 13398 */ GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(13468), // Rule ID 172 //
5060 /* 13403 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM_UseMulOps),
5061 /* 13406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5062 /* 13410 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5063 /* 13414 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5064 /* 13418 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5065 /* 13422 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5066 /* 13426 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5067 /* 13430 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5068 /* 13435 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5069 /* 13440 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5070 /* 13442 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
5071 /* 13442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLS),
5072 /* 13445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5073 /* 13447 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5074 /* 13451 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
5075 /* 13455 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
5076 /* 13457 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5077 /* 13460 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5078 /* 13466 */ GIR_RootConstrainSelectedInstOperands,
5079 /* 13467 */ // GIR_Coverage, 172,
5080 /* 13467 */ GIR_EraseRootFromParent_Done,
5081 /* 13468 */ // Label 289: @13468
5082 /* 13468 */ GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(13538), // Rule ID 503 //
5083 /* 13473 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps),
5084 /* 13476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5085 /* 13480 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5086 /* 13484 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5087 /* 13488 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5088 /* 13492 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5089 /* 13496 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5090 /* 13500 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5091 /* 13505 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5092 /* 13510 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5093 /* 13512 */ // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
5094 /* 13512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLS),
5095 /* 13515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5096 /* 13517 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5097 /* 13521 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
5098 /* 13525 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
5099 /* 13527 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5100 /* 13530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5101 /* 13536 */ GIR_RootConstrainSelectedInstOperands,
5102 /* 13537 */ // GIR_Coverage, 503,
5103 /* 13537 */ GIR_EraseRootFromParent_Done,
5104 /* 13538 */ // Label 290: @13538
5105 /* 13538 */ GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(13584), // Rule ID 76 //
5106 /* 13543 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
5107 /* 13546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5108 /* 13550 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5109 /* 13554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5110 /* 13558 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5111 /* 13558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBrr),
5112 /* 13561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5113 /* 13563 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5114 /* 13565 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
5115 /* 13567 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5116 /* 13570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5117 /* 13576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5118 /* 13582 */ GIR_RootConstrainSelectedInstOperands,
5119 /* 13583 */ // GIR_Coverage, 76,
5120 /* 13583 */ GIR_EraseRootFromParent_Done,
5121 /* 13584 */ // Label 291: @13584
5122 /* 13584 */ GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(13630), // Rule ID 332 //
5123 /* 13589 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
5124 /* 13592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
5125 /* 13596 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
5126 /* 13600 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
5127 /* 13604 */ // (sub:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tSUBrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
5128 /* 13604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSUBrr),
5129 /* 13607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5130 /* 13609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
5131 /* 13615 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5132 /* 13617 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
5133 /* 13619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5134 /* 13622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5135 /* 13628 */ GIR_RootConstrainSelectedInstOperands,
5136 /* 13629 */ // GIR_Coverage, 332,
5137 /* 13629 */ GIR_EraseRootFromParent_Done,
5138 /* 13630 */ // Label 292: @13630
5139 /* 13630 */ GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(13676), // Rule ID 412 //
5140 /* 13635 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
5141 /* 13638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5142 /* 13642 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5143 /* 13646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5144 /* 13650 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5145 /* 13650 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBrr),
5146 /* 13653 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5147 /* 13655 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5148 /* 13657 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
5149 /* 13659 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5150 /* 13662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5151 /* 13668 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5152 /* 13674 */ GIR_RootConstrainSelectedInstOperands,
5153 /* 13675 */ // GIR_Coverage, 412,
5154 /* 13675 */ GIR_EraseRootFromParent_Done,
5155 /* 13676 */ // Label 293: @13676
5156 /* 13676 */ GIM_Reject,
5157 /* 13677 */ // Label 282: @13677
5158 /* 13677 */ GIM_Reject,
5159 /* 13678 */ // Label 273: @13678
5160 /* 13678 */ GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(13724), // Rule ID 1128 //
5161 /* 13683 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5162 /* 13686 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
5163 /* 13689 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5164 /* 13692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5165 /* 13696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5166 /* 13700 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5167 /* 13704 */ // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
5168 /* 13704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv1i64),
5169 /* 13707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5170 /* 13709 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5171 /* 13711 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5172 /* 13713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5173 /* 13716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5174 /* 13722 */ GIR_RootConstrainSelectedInstOperands,
5175 /* 13723 */ // GIR_Coverage, 1128,
5176 /* 13723 */ GIR_EraseRootFromParent_Done,
5177 /* 13724 */ // Label 294: @13724
5178 /* 13724 */ GIM_Reject,
5179 /* 13725 */ // Label 274: @13725
5180 /* 13725 */ GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(13839),
5181 /* 13730 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
5182 /* 13733 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
5183 /* 13736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5184 /* 13740 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5185 /* 13744 */ GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(13806), // Rule ID 1053 //
5186 /* 13749 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5187 /* 13752 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5188 /* 13756 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5189 /* 13760 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5190 /* 13764 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
5191 /* 13768 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5192 /* 13773 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5193 /* 13778 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5194 /* 13780 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5195 /* 13780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i8),
5196 /* 13783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5197 /* 13785 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5198 /* 13787 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5199 /* 13791 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5200 /* 13795 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5201 /* 13798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5202 /* 13804 */ GIR_RootConstrainSelectedInstOperands,
5203 /* 13805 */ // GIR_Coverage, 1053,
5204 /* 13805 */ GIR_EraseRootFromParent_Done,
5205 /* 13806 */ // Label 296: @13806
5206 /* 13806 */ GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(13838), // Rule ID 1122 //
5207 /* 13811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5208 /* 13814 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5209 /* 13818 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5210 /* 13818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i8),
5211 /* 13821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5212 /* 13823 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5213 /* 13825 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5214 /* 13827 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5215 /* 13830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5216 /* 13836 */ GIR_RootConstrainSelectedInstOperands,
5217 /* 13837 */ // GIR_Coverage, 1122,
5218 /* 13837 */ GIR_EraseRootFromParent_Done,
5219 /* 13838 */ // Label 297: @13838
5220 /* 13838 */ GIM_Reject,
5221 /* 13839 */ // Label 295: @13839
5222 /* 13839 */ GIM_Reject,
5223 /* 13840 */ // Label 275: @13840
5224 /* 13840 */ GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(14023),
5225 /* 13845 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
5226 /* 13848 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
5227 /* 13851 */ GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(13921), // Rule ID 1056 //
5228 /* 13856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5229 /* 13859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5230 /* 13863 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5231 /* 13867 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5232 /* 13871 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5233 /* 13875 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
5234 /* 13879 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
5235 /* 13883 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5236 /* 13888 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5237 /* 13893 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5238 /* 13895 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5239 /* 13895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv16i8),
5240 /* 13898 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5241 /* 13900 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5242 /* 13902 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5243 /* 13906 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5244 /* 13910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5245 /* 13913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5246 /* 13919 */ GIR_RootConstrainSelectedInstOperands,
5247 /* 13920 */ // GIR_Coverage, 1056,
5248 /* 13920 */ GIR_EraseRootFromParent_Done,
5249 /* 13921 */ // Label 299: @13921
5250 /* 13921 */ GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(13961), // Rule ID 1125 //
5251 /* 13926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5252 /* 13929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5253 /* 13933 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5254 /* 13937 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5255 /* 13941 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5256 /* 13941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv16i8),
5257 /* 13944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5258 /* 13946 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5259 /* 13948 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5260 /* 13950 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5261 /* 13953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5262 /* 13959 */ GIR_RootConstrainSelectedInstOperands,
5263 /* 13960 */ // GIR_Coverage, 1125,
5264 /* 13960 */ GIR_EraseRootFromParent_Done,
5265 /* 13961 */ // Label 300: @13961
5266 /* 13961 */ GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(14022), // Rule ID 3883 //
5267 /* 13966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
5268 /* 13969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5269 /* 13973 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5270 /* 13977 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5271 /* 13981 */ // (sub:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VSUBi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
5272 /* 13981 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5273 /* 13984 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5274 /* 13988 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
5275 /* 13993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi8),
5276 /* 13996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
5277 /* 13998 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
5278 /* 14000 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
5279 /* 14002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5280 /* 14005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5281 /* 14011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5282 /* 14017 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5283 /* 14020 */ GIR_RootConstrainSelectedInstOperands,
5284 /* 14021 */ // GIR_Coverage, 3883,
5285 /* 14021 */ GIR_EraseRootFromParent_Done,
5286 /* 14022 */ // Label 301: @14022
5287 /* 14022 */ GIM_Reject,
5288 /* 14023 */ // Label 298: @14023
5289 /* 14023 */ GIM_Reject,
5290 /* 14024 */ // Label 276: @14024
5291 /* 14024 */ GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(14138),
5292 /* 14029 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
5293 /* 14032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
5294 /* 14035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5295 /* 14039 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5296 /* 14043 */ GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(14105), // Rule ID 1054 //
5297 /* 14048 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5298 /* 14051 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5299 /* 14055 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5300 /* 14059 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5301 /* 14063 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5302 /* 14067 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5303 /* 14072 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5304 /* 14077 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5305 /* 14079 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5306 /* 14079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i16),
5307 /* 14082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5308 /* 14084 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5309 /* 14086 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5310 /* 14090 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5311 /* 14094 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5312 /* 14097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5313 /* 14103 */ GIR_RootConstrainSelectedInstOperands,
5314 /* 14104 */ // GIR_Coverage, 1054,
5315 /* 14104 */ GIR_EraseRootFromParent_Done,
5316 /* 14105 */ // Label 303: @14105
5317 /* 14105 */ GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(14137), // Rule ID 1123 //
5318 /* 14110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5319 /* 14113 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5320 /* 14117 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5321 /* 14117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i16),
5322 /* 14120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5323 /* 14122 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5324 /* 14124 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5325 /* 14126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5326 /* 14129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5327 /* 14135 */ GIR_RootConstrainSelectedInstOperands,
5328 /* 14136 */ // GIR_Coverage, 1123,
5329 /* 14136 */ GIR_EraseRootFromParent_Done,
5330 /* 14137 */ // Label 304: @14137
5331 /* 14137 */ GIM_Reject,
5332 /* 14138 */ // Label 302: @14138
5333 /* 14138 */ GIM_Reject,
5334 /* 14139 */ // Label 277: @14139
5335 /* 14139 */ GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(14853),
5336 /* 14144 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
5337 /* 14147 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
5338 /* 14150 */ GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(14222), // Rule ID 1140 //
5339 /* 14155 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5340 /* 14158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5341 /* 14162 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5342 /* 14166 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5343 /* 14170 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5344 /* 14174 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5345 /* 14179 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5346 /* 14183 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5347 /* 14187 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5348 /* 14191 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5349 /* 14196 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5350 /* 14198 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5351 /* 14198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5352 /* 14201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5353 /* 14203 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5354 /* 14207 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5355 /* 14211 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5356 /* 14214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5357 /* 14220 */ GIR_RootConstrainSelectedInstOperands,
5358 /* 14221 */ // GIR_Coverage, 1140,
5359 /* 14221 */ GIR_EraseRootFromParent_Done,
5360 /* 14222 */ // Label 306: @14222
5361 /* 14222 */ GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(14294), // Rule ID 1139 //
5362 /* 14227 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5363 /* 14230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5364 /* 14234 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5365 /* 14238 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5366 /* 14242 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5367 /* 14246 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5368 /* 14251 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5369 /* 14255 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5370 /* 14259 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5371 /* 14263 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5372 /* 14268 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5373 /* 14270 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5374 /* 14270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5375 /* 14273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5376 /* 14275 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5377 /* 14279 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5378 /* 14283 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5379 /* 14286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5380 /* 14292 */ GIR_RootConstrainSelectedInstOperands,
5381 /* 14293 */ // GIR_Coverage, 1139,
5382 /* 14293 */ GIR_EraseRootFromParent_Done,
5383 /* 14294 */ // Label 307: @14294
5384 /* 14294 */ GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(14366), // Rule ID 1134 //
5385 /* 14299 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5386 /* 14302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5387 /* 14306 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5388 /* 14310 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5389 /* 14314 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5390 /* 14318 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5391 /* 14323 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5392 /* 14327 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
5393 /* 14331 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5394 /* 14335 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5395 /* 14340 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5396 /* 14342 */ // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5397 /* 14342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv8i16),
5398 /* 14345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5399 /* 14347 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5400 /* 14351 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5401 /* 14355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5402 /* 14358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5403 /* 14364 */ GIR_RootConstrainSelectedInstOperands,
5404 /* 14365 */ // GIR_Coverage, 1134,
5405 /* 14365 */ GIR_EraseRootFromParent_Done,
5406 /* 14366 */ // Label 308: @14366
5407 /* 14366 */ GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(14438), // Rule ID 1138 //
5408 /* 14371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5409 /* 14374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5410 /* 14378 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5411 /* 14382 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5412 /* 14386 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5413 /* 14390 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5414 /* 14395 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5415 /* 14399 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5416 /* 14403 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5417 /* 14407 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5418 /* 14412 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5419 /* 14414 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5420 /* 14414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5421 /* 14417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5422 /* 14419 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5423 /* 14423 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5424 /* 14427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5425 /* 14430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5426 /* 14436 */ GIR_RootConstrainSelectedInstOperands,
5427 /* 14437 */ // GIR_Coverage, 1138,
5428 /* 14437 */ GIR_EraseRootFromParent_Done,
5429 /* 14438 */ // Label 309: @14438
5430 /* 14438 */ GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(14510), // Rule ID 1137 //
5431 /* 14443 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5432 /* 14446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5433 /* 14450 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5434 /* 14454 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5435 /* 14458 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5436 /* 14462 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5437 /* 14467 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5438 /* 14471 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5439 /* 14475 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5440 /* 14479 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5441 /* 14484 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5442 /* 14486 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5443 /* 14486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5444 /* 14489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5445 /* 14491 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5446 /* 14495 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5447 /* 14499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5448 /* 14502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5449 /* 14508 */ GIR_RootConstrainSelectedInstOperands,
5450 /* 14509 */ // GIR_Coverage, 1137,
5451 /* 14509 */ GIR_EraseRootFromParent_Done,
5452 /* 14510 */ // Label 310: @14510
5453 /* 14510 */ GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(14580), // Rule ID 1057 //
5454 /* 14515 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5455 /* 14518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5456 /* 14522 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5457 /* 14526 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5458 /* 14530 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5459 /* 14534 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
5460 /* 14538 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
5461 /* 14542 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5462 /* 14547 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5463 /* 14552 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5464 /* 14554 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
5465 /* 14554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i16),
5466 /* 14557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5467 /* 14559 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5468 /* 14561 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5469 /* 14565 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5470 /* 14569 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5471 /* 14572 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5472 /* 14578 */ GIR_RootConstrainSelectedInstOperands,
5473 /* 14579 */ // GIR_Coverage, 1057,
5474 /* 14579 */ GIR_EraseRootFromParent_Done,
5475 /* 14580 */ // Label 311: @14580
5476 /* 14580 */ GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(14637), // Rule ID 1153 //
5477 /* 14585 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5478 /* 14588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5479 /* 14592 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5480 /* 14596 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5481 /* 14600 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5482 /* 14604 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5483 /* 14608 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5484 /* 14613 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5485 /* 14615 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5486 /* 14615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16),
5487 /* 14618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5488 /* 14620 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5489 /* 14622 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5490 /* 14626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5491 /* 14629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5492 /* 14635 */ GIR_RootConstrainSelectedInstOperands,
5493 /* 14636 */ // GIR_Coverage, 1153,
5494 /* 14636 */ GIR_EraseRootFromParent_Done,
5495 /* 14637 */ // Label 312: @14637
5496 /* 14637 */ GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(14694), // Rule ID 1149 //
5497 /* 14642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5498 /* 14645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5499 /* 14649 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5500 /* 14653 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5501 /* 14657 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5502 /* 14661 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5503 /* 14665 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5504 /* 14670 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5505 /* 14672 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5506 /* 14672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv8i16),
5507 /* 14675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5508 /* 14677 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5509 /* 14679 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5510 /* 14683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5511 /* 14686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5512 /* 14692 */ GIR_RootConstrainSelectedInstOperands,
5513 /* 14693 */ // GIR_Coverage, 1149,
5514 /* 14693 */ GIR_EraseRootFromParent_Done,
5515 /* 14694 */ // Label 313: @14694
5516 /* 14694 */ GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(14751), // Rule ID 1152 //
5517 /* 14699 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5518 /* 14702 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5519 /* 14706 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5520 /* 14710 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5521 /* 14714 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5522 /* 14718 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5523 /* 14722 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5524 /* 14727 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5525 /* 14729 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5526 /* 14729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16),
5527 /* 14732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5528 /* 14734 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5529 /* 14736 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5530 /* 14740 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5531 /* 14743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5532 /* 14749 */ GIR_RootConstrainSelectedInstOperands,
5533 /* 14750 */ // GIR_Coverage, 1152,
5534 /* 14750 */ GIR_EraseRootFromParent_Done,
5535 /* 14751 */ // Label 314: @14751
5536 /* 14751 */ GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(14791), // Rule ID 1126 //
5537 /* 14756 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5538 /* 14759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5539 /* 14763 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5540 /* 14767 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5541 /* 14771 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
5542 /* 14771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i16),
5543 /* 14774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5544 /* 14776 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5545 /* 14778 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5546 /* 14780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5547 /* 14783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5548 /* 14789 */ GIR_RootConstrainSelectedInstOperands,
5549 /* 14790 */ // GIR_Coverage, 1126,
5550 /* 14790 */ GIR_EraseRootFromParent_Done,
5551 /* 14791 */ // Label 315: @14791
5552 /* 14791 */ GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(14852), // Rule ID 3887 //
5553 /* 14796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
5554 /* 14799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5555 /* 14803 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5556 /* 14807 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5557 /* 14811 */ // (sub:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VSUBi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
5558 /* 14811 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5559 /* 14814 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5560 /* 14818 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
5561 /* 14823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi16),
5562 /* 14826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
5563 /* 14828 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
5564 /* 14830 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
5565 /* 14832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5566 /* 14835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5567 /* 14841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5568 /* 14847 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5569 /* 14850 */ GIR_RootConstrainSelectedInstOperands,
5570 /* 14851 */ // GIR_Coverage, 3887,
5571 /* 14851 */ GIR_EraseRootFromParent_Done,
5572 /* 14852 */ // Label 316: @14852
5573 /* 14852 */ GIM_Reject,
5574 /* 14853 */ // Label 305: @14853
5575 /* 14853 */ GIM_Reject,
5576 /* 14854 */ // Label 278: @14854
5577 /* 14854 */ GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(14968),
5578 /* 14859 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
5579 /* 14862 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
5580 /* 14865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5581 /* 14869 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5582 /* 14873 */ GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(14935), // Rule ID 1055 //
5583 /* 14878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5584 /* 14881 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5585 /* 14885 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5586 /* 14889 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5587 /* 14893 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
5588 /* 14897 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5589 /* 14902 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5590 /* 14907 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5591 /* 14909 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5592 /* 14909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv2i32),
5593 /* 14912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5594 /* 14914 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5595 /* 14916 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5596 /* 14920 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5597 /* 14924 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5598 /* 14927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5599 /* 14933 */ GIR_RootConstrainSelectedInstOperands,
5600 /* 14934 */ // GIR_Coverage, 1055,
5601 /* 14934 */ GIR_EraseRootFromParent_Done,
5602 /* 14935 */ // Label 318: @14935
5603 /* 14935 */ GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(14967), // Rule ID 1124 //
5604 /* 14940 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5605 /* 14943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5606 /* 14947 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5607 /* 14947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i32),
5608 /* 14950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5609 /* 14952 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5610 /* 14954 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5611 /* 14956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5612 /* 14959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5613 /* 14965 */ GIR_RootConstrainSelectedInstOperands,
5614 /* 14966 */ // GIR_Coverage, 1124,
5615 /* 14966 */ GIR_EraseRootFromParent_Done,
5616 /* 14967 */ // Label 319: @14967
5617 /* 14967 */ GIM_Reject,
5618 /* 14968 */ // Label 317: @14968
5619 /* 14968 */ GIM_Reject,
5620 /* 14969 */ // Label 279: @14969
5621 /* 14969 */ GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(15683),
5622 /* 14974 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
5623 /* 14977 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
5624 /* 14980 */ GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(15052), // Rule ID 1144 //
5625 /* 14985 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5626 /* 14988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5627 /* 14992 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5628 /* 14996 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5629 /* 15000 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5630 /* 15004 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5631 /* 15009 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5632 /* 15013 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5633 /* 15017 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5634 /* 15021 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5635 /* 15026 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5636 /* 15028 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5637 /* 15028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5638 /* 15031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5639 /* 15033 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5640 /* 15037 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5641 /* 15041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5642 /* 15044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5643 /* 15050 */ GIR_RootConstrainSelectedInstOperands,
5644 /* 15051 */ // GIR_Coverage, 1144,
5645 /* 15051 */ GIR_EraseRootFromParent_Done,
5646 /* 15052 */ // Label 321: @15052
5647 /* 15052 */ GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(15124), // Rule ID 1143 //
5648 /* 15057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5649 /* 15060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5650 /* 15064 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5651 /* 15068 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5652 /* 15072 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5653 /* 15076 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5654 /* 15081 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5655 /* 15085 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5656 /* 15089 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5657 /* 15093 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5658 /* 15098 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5659 /* 15100 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5660 /* 15100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5661 /* 15103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5662 /* 15105 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5663 /* 15109 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5664 /* 15113 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5665 /* 15116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5666 /* 15122 */ GIR_RootConstrainSelectedInstOperands,
5667 /* 15123 */ // GIR_Coverage, 1143,
5668 /* 15123 */ GIR_EraseRootFromParent_Done,
5669 /* 15124 */ // Label 322: @15124
5670 /* 15124 */ GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(15196), // Rule ID 1135 //
5671 /* 15129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5672 /* 15132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5673 /* 15136 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5674 /* 15140 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5675 /* 15144 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5676 /* 15148 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5677 /* 15153 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5678 /* 15157 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
5679 /* 15161 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5680 /* 15165 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5681 /* 15170 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5682 /* 15172 */ // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5683 /* 15172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv4i32),
5684 /* 15175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5685 /* 15177 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5686 /* 15181 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5687 /* 15185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5688 /* 15188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5689 /* 15194 */ GIR_RootConstrainSelectedInstOperands,
5690 /* 15195 */ // GIR_Coverage, 1135,
5691 /* 15195 */ GIR_EraseRootFromParent_Done,
5692 /* 15196 */ // Label 323: @15196
5693 /* 15196 */ GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(15268), // Rule ID 1142 //
5694 /* 15201 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5695 /* 15204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5696 /* 15208 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5697 /* 15212 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5698 /* 15216 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5699 /* 15220 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5700 /* 15225 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5701 /* 15229 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5702 /* 15233 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5703 /* 15237 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5704 /* 15242 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5705 /* 15244 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5706 /* 15244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5707 /* 15247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5708 /* 15249 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5709 /* 15253 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5710 /* 15257 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5711 /* 15260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5712 /* 15266 */ GIR_RootConstrainSelectedInstOperands,
5713 /* 15267 */ // GIR_Coverage, 1142,
5714 /* 15267 */ GIR_EraseRootFromParent_Done,
5715 /* 15268 */ // Label 324: @15268
5716 /* 15268 */ GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(15340), // Rule ID 1141 //
5717 /* 15273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5718 /* 15276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5719 /* 15280 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5720 /* 15284 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5721 /* 15288 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5722 /* 15292 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5723 /* 15297 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5724 /* 15301 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5725 /* 15305 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5726 /* 15309 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5727 /* 15314 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5728 /* 15316 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5729 /* 15316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5730 /* 15319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5731 /* 15321 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5732 /* 15325 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5733 /* 15329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5734 /* 15332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5735 /* 15338 */ GIR_RootConstrainSelectedInstOperands,
5736 /* 15339 */ // GIR_Coverage, 1141,
5737 /* 15339 */ GIR_EraseRootFromParent_Done,
5738 /* 15340 */ // Label 325: @15340
5739 /* 15340 */ GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(15410), // Rule ID 1058 //
5740 /* 15345 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5741 /* 15348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5742 /* 15352 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5743 /* 15356 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5744 /* 15360 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5745 /* 15364 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5746 /* 15368 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5747 /* 15372 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5748 /* 15377 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5749 /* 15382 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5750 /* 15384 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
5751 /* 15384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i32),
5752 /* 15387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5753 /* 15389 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5754 /* 15391 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5755 /* 15395 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5756 /* 15399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5757 /* 15402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5758 /* 15408 */ GIR_RootConstrainSelectedInstOperands,
5759 /* 15409 */ // GIR_Coverage, 1058,
5760 /* 15409 */ GIR_EraseRootFromParent_Done,
5761 /* 15410 */ // Label 326: @15410
5762 /* 15410 */ GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(15467), // Rule ID 1155 //
5763 /* 15415 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5764 /* 15418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5765 /* 15422 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5766 /* 15426 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5767 /* 15430 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5768 /* 15434 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5769 /* 15438 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5770 /* 15443 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5771 /* 15445 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5772 /* 15445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32),
5773 /* 15448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5774 /* 15450 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5775 /* 15452 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5776 /* 15456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5777 /* 15459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5778 /* 15465 */ GIR_RootConstrainSelectedInstOperands,
5779 /* 15466 */ // GIR_Coverage, 1155,
5780 /* 15466 */ GIR_EraseRootFromParent_Done,
5781 /* 15467 */ // Label 327: @15467
5782 /* 15467 */ GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(15524), // Rule ID 1150 //
5783 /* 15472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5784 /* 15475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5785 /* 15479 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5786 /* 15483 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5787 /* 15487 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5788 /* 15491 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5789 /* 15495 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5790 /* 15500 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5791 /* 15502 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5792 /* 15502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv4i32),
5793 /* 15505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5794 /* 15507 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5795 /* 15509 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5796 /* 15513 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5797 /* 15516 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5798 /* 15522 */ GIR_RootConstrainSelectedInstOperands,
5799 /* 15523 */ // GIR_Coverage, 1150,
5800 /* 15523 */ GIR_EraseRootFromParent_Done,
5801 /* 15524 */ // Label 328: @15524
5802 /* 15524 */ GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(15581), // Rule ID 1154 //
5803 /* 15529 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5804 /* 15532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5805 /* 15536 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5806 /* 15540 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5807 /* 15544 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5808 /* 15548 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5809 /* 15552 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5810 /* 15557 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5811 /* 15559 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5812 /* 15559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32),
5813 /* 15562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5814 /* 15564 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5815 /* 15566 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5816 /* 15570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5817 /* 15573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5818 /* 15579 */ GIR_RootConstrainSelectedInstOperands,
5819 /* 15580 */ // GIR_Coverage, 1154,
5820 /* 15580 */ GIR_EraseRootFromParent_Done,
5821 /* 15581 */ // Label 329: @15581
5822 /* 15581 */ GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(15621), // Rule ID 1127 //
5823 /* 15586 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5824 /* 15589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5825 /* 15593 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5826 /* 15597 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5827 /* 15601 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
5828 /* 15601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i32),
5829 /* 15604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5830 /* 15606 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5831 /* 15608 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5832 /* 15610 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5833 /* 15613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5834 /* 15619 */ GIR_RootConstrainSelectedInstOperands,
5835 /* 15620 */ // GIR_Coverage, 1127,
5836 /* 15620 */ GIR_EraseRootFromParent_Done,
5837 /* 15621 */ // Label 330: @15621
5838 /* 15621 */ GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(15682), // Rule ID 3891 //
5839 /* 15626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
5840 /* 15629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5841 /* 15633 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5842 /* 15637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5843 /* 15641 */ // (sub:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VSUBi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
5844 /* 15641 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5845 /* 15644 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5846 /* 15648 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
5847 /* 15653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi32),
5848 /* 15656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
5849 /* 15658 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
5850 /* 15660 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
5851 /* 15662 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5852 /* 15665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5853 /* 15671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5854 /* 15677 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5855 /* 15680 */ GIR_RootConstrainSelectedInstOperands,
5856 /* 15681 */ // GIR_Coverage, 3891,
5857 /* 15681 */ GIR_EraseRootFromParent_Done,
5858 /* 15682 */ // Label 331: @15682
5859 /* 15682 */ GIM_Reject,
5860 /* 15683 */ // Label 320: @15683
5861 /* 15683 */ GIM_Reject,
5862 /* 15684 */ // Label 280: @15684
5863 /* 15684 */ GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(16235),
5864 /* 15689 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
5865 /* 15692 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
5866 /* 15695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5867 /* 15699 */ GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(15767), // Rule ID 1148 //
5868 /* 15704 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5869 /* 15707 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5870 /* 15711 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5871 /* 15715 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5872 /* 15719 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5873 /* 15724 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5874 /* 15728 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5875 /* 15732 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5876 /* 15736 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5877 /* 15741 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5878 /* 15743 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5879 /* 15743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5880 /* 15746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5881 /* 15748 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5882 /* 15752 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5883 /* 15756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5884 /* 15759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5885 /* 15765 */ GIR_RootConstrainSelectedInstOperands,
5886 /* 15766 */ // GIR_Coverage, 1148,
5887 /* 15766 */ GIR_EraseRootFromParent_Done,
5888 /* 15767 */ // Label 333: @15767
5889 /* 15767 */ GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(15835), // Rule ID 1147 //
5890 /* 15772 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5891 /* 15775 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5892 /* 15779 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5893 /* 15783 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5894 /* 15787 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5895 /* 15792 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5896 /* 15796 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5897 /* 15800 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5898 /* 15804 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5899 /* 15809 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5900 /* 15811 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5901 /* 15811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5902 /* 15814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5903 /* 15816 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5904 /* 15820 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5905 /* 15824 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5906 /* 15827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5907 /* 15833 */ GIR_RootConstrainSelectedInstOperands,
5908 /* 15834 */ // GIR_Coverage, 1147,
5909 /* 15834 */ GIR_EraseRootFromParent_Done,
5910 /* 15835 */ // Label 334: @15835
5911 /* 15835 */ GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(15903), // Rule ID 1136 //
5912 /* 15840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5913 /* 15843 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5914 /* 15847 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5915 /* 15851 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5916 /* 15855 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5917 /* 15860 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5918 /* 15864 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
5919 /* 15868 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5920 /* 15872 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5921 /* 15877 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5922 /* 15879 */ // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5923 /* 15879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv2i64),
5924 /* 15882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5925 /* 15884 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5926 /* 15888 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5927 /* 15892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5928 /* 15895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5929 /* 15901 */ GIR_RootConstrainSelectedInstOperands,
5930 /* 15902 */ // GIR_Coverage, 1136,
5931 /* 15902 */ GIR_EraseRootFromParent_Done,
5932 /* 15903 */ // Label 335: @15903
5933 /* 15903 */ GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(15971), // Rule ID 1146 //
5934 /* 15908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5935 /* 15911 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5936 /* 15915 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5937 /* 15919 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5938 /* 15923 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5939 /* 15928 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5940 /* 15932 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5941 /* 15936 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5942 /* 15940 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5943 /* 15945 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5944 /* 15947 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5945 /* 15947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5946 /* 15950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5947 /* 15952 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5948 /* 15956 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5949 /* 15960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5950 /* 15963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5951 /* 15969 */ GIR_RootConstrainSelectedInstOperands,
5952 /* 15970 */ // GIR_Coverage, 1146,
5953 /* 15970 */ GIR_EraseRootFromParent_Done,
5954 /* 15971 */ // Label 336: @15971
5955 /* 15971 */ GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(16039), // Rule ID 1145 //
5956 /* 15976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5957 /* 15979 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5958 /* 15983 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5959 /* 15987 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5960 /* 15991 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5961 /* 15996 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5962 /* 16000 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5963 /* 16004 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5964 /* 16008 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5965 /* 16013 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5966 /* 16015 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5967 /* 16015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5968 /* 16018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5969 /* 16020 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5970 /* 16024 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5971 /* 16028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5972 /* 16031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5973 /* 16037 */ GIR_RootConstrainSelectedInstOperands,
5974 /* 16038 */ // GIR_Coverage, 1145,
5975 /* 16038 */ GIR_EraseRootFromParent_Done,
5976 /* 16039 */ // Label 337: @16039
5977 /* 16039 */ GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(16092), // Rule ID 1157 //
5978 /* 16044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5979 /* 16047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5980 /* 16051 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5981 /* 16055 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5982 /* 16059 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5983 /* 16063 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5984 /* 16068 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5985 /* 16070 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5986 /* 16070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64),
5987 /* 16073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5988 /* 16075 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5989 /* 16077 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5990 /* 16081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5991 /* 16084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5992 /* 16090 */ GIR_RootConstrainSelectedInstOperands,
5993 /* 16091 */ // GIR_Coverage, 1157,
5994 /* 16091 */ GIR_EraseRootFromParent_Done,
5995 /* 16092 */ // Label 338: @16092
5996 /* 16092 */ GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(16145), // Rule ID 1151 //
5997 /* 16097 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5998 /* 16100 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5999 /* 16104 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6000 /* 16108 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
6001 /* 16112 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
6002 /* 16116 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6003 /* 16121 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6004 /* 16123 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
6005 /* 16123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv2i64),
6006 /* 16126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6007 /* 16128 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6008 /* 16130 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
6009 /* 16134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6010 /* 16137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6011 /* 16143 */ GIR_RootConstrainSelectedInstOperands,
6012 /* 16144 */ // GIR_Coverage, 1151,
6013 /* 16144 */ GIR_EraseRootFromParent_Done,
6014 /* 16145 */ // Label 339: @16145
6015 /* 16145 */ GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(16198), // Rule ID 1156 //
6016 /* 16150 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6017 /* 16153 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6018 /* 16157 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6019 /* 16161 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
6020 /* 16165 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
6021 /* 16169 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6022 /* 16174 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6023 /* 16176 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
6024 /* 16176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64),
6025 /* 16179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6026 /* 16181 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6027 /* 16183 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
6028 /* 16187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6029 /* 16190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6030 /* 16196 */ GIR_RootConstrainSelectedInstOperands,
6031 /* 16197 */ // GIR_Coverage, 1156,
6032 /* 16197 */ GIR_EraseRootFromParent_Done,
6033 /* 16198 */ // Label 340: @16198
6034 /* 16198 */ GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(16234), // Rule ID 1129 //
6035 /* 16203 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6036 /* 16206 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6037 /* 16210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6038 /* 16214 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
6039 /* 16214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i64),
6040 /* 16217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6041 /* 16219 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6042 /* 16221 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6043 /* 16223 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6044 /* 16226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6045 /* 16232 */ GIR_RootConstrainSelectedInstOperands,
6046 /* 16233 */ // GIR_Coverage, 1129,
6047 /* 16233 */ GIR_EraseRootFromParent_Done,
6048 /* 16234 */ // Label 341: @16234
6049 /* 16234 */ GIM_Reject,
6050 /* 16235 */ // Label 332: @16235
6051 /* 16235 */ GIM_Reject,
6052 /* 16236 */ // Label 281: @16236
6053 /* 16236 */ GIM_Reject,
6054 /* 16237 */ // Label 2: @16237
6055 /* 16237 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 349*/ GIMT_Encode4(17928),
6056 /* 16248 */ /*GILLT_s32*//*Label 342*/ GIMT_Encode4(16296), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
6057 /* 16272 */ /*GILLT_v8s8*//*Label 343*/ GIMT_Encode4(17215),
6058 /* 16276 */ /*GILLT_v16s8*//*Label 344*/ GIMT_Encode4(17262),
6059 /* 16280 */ /*GILLT_v4s16*//*Label 345*/ GIMT_Encode4(17376),
6060 /* 16284 */ /*GILLT_v8s16*//*Label 346*/ GIMT_Encode4(17423),
6061 /* 16288 */ /*GILLT_v2s32*//*Label 347*/ GIMT_Encode4(17652),
6062 /* 16292 */ /*GILLT_v4s32*//*Label 348*/ GIMT_Encode4(17699),
6063 /* 16296 */ // Label 342: @16296
6064 /* 16296 */ GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(17214),
6065 /* 16301 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
6066 /* 16304 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6067 /* 16307 */ GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(16395), // Rule ID 185 //
6068 /* 16312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
6069 /* 16315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6070 /* 16319 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6071 /* 16323 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
6072 /* 16327 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6073 /* 16331 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6074 /* 16335 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6075 /* 16340 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
6076 /* 16344 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6077 /* 16348 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
6078 /* 16352 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6079 /* 16356 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6080 /* 16360 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6081 /* 16365 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
6082 /* 16369 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6083 /* 16371 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6084 /* 16371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT),
6085 /* 16374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6086 /* 16376 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6087 /* 16380 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6088 /* 16384 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6089 /* 16387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6090 /* 16393 */ GIR_RootConstrainSelectedInstOperands,
6091 /* 16394 */ // GIR_Coverage, 185,
6092 /* 16394 */ GIR_EraseRootFromParent_Done,
6093 /* 16395 */ // Label 351: @16395
6094 /* 16395 */ GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(16483), // Rule ID 514 //
6095 /* 16400 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
6096 /* 16403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6097 /* 16407 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6098 /* 16411 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
6099 /* 16415 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6100 /* 16419 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6101 /* 16423 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6102 /* 16428 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
6103 /* 16432 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6104 /* 16436 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
6105 /* 16440 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6106 /* 16444 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6107 /* 16448 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6108 /* 16453 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
6109 /* 16457 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6110 /* 16459 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6111 /* 16459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT),
6112 /* 16462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6113 /* 16464 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6114 /* 16468 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6115 /* 16472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6116 /* 16475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6117 /* 16481 */ GIR_RootConstrainSelectedInstOperands,
6118 /* 16482 */ // GIR_Coverage, 514,
6119 /* 16482 */ GIR_EraseRootFromParent_Done,
6120 /* 16483 */ // Label 352: @16483
6121 /* 16483 */ GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(16574), // Rule ID 184 //
6122 /* 16488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
6123 /* 16491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6124 /* 16495 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6125 /* 16499 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
6126 /* 16503 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6127 /* 16507 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6128 /* 16511 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6129 /* 16516 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
6130 /* 16520 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6131 /* 16524 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6132 /* 16528 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6133 /* 16532 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6134 /* 16537 */ // MIs[2] Operand 2
6135 /* 16537 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6136 /* 16548 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6137 /* 16550 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6138 /* 16550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB),
6139 /* 16553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6140 /* 16555 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6141 /* 16559 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6142 /* 16563 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6143 /* 16566 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6144 /* 16572 */ GIR_RootConstrainSelectedInstOperands,
6145 /* 16573 */ // GIR_Coverage, 184,
6146 /* 16573 */ GIR_EraseRootFromParent_Done,
6147 /* 16574 */ // Label 353: @16574
6148 /* 16574 */ GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(16665), // Rule ID 513 //
6149 /* 16579 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
6150 /* 16582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6151 /* 16586 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6152 /* 16590 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
6153 /* 16594 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6154 /* 16598 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6155 /* 16602 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6156 /* 16607 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
6157 /* 16611 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6158 /* 16615 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6159 /* 16619 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6160 /* 16623 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6161 /* 16628 */ // MIs[2] Operand 2
6162 /* 16628 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6163 /* 16639 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6164 /* 16641 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6165 /* 16641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB),
6166 /* 16644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6167 /* 16646 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6168 /* 16650 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6169 /* 16654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6170 /* 16657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6171 /* 16663 */ GIR_RootConstrainSelectedInstOperands,
6172 /* 16664 */ // GIR_Coverage, 513,
6173 /* 16664 */ GIR_EraseRootFromParent_Done,
6174 /* 16665 */ // Label 354: @16665
6175 /* 16665 */ GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(16756), // Rule ID 183 //
6176 /* 16670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
6177 /* 16673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6178 /* 16677 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6179 /* 16681 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6180 /* 16685 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6181 /* 16689 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6182 /* 16694 */ // MIs[1] Operand 2
6183 /* 16694 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6184 /* 16705 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6185 /* 16709 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
6186 /* 16713 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6187 /* 16717 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6188 /* 16721 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6189 /* 16726 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
6190 /* 16730 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6191 /* 16732 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6192 /* 16732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT),
6193 /* 16735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6194 /* 16737 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6195 /* 16741 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6196 /* 16745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6197 /* 16748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6198 /* 16754 */ GIR_RootConstrainSelectedInstOperands,
6199 /* 16755 */ // GIR_Coverage, 183,
6200 /* 16755 */ GIR_EraseRootFromParent_Done,
6201 /* 16756 */ // Label 355: @16756
6202 /* 16756 */ GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(16847), // Rule ID 512 //
6203 /* 16761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
6204 /* 16764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6205 /* 16768 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6206 /* 16772 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6207 /* 16776 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6208 /* 16780 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6209 /* 16785 */ // MIs[1] Operand 2
6210 /* 16785 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6211 /* 16796 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6212 /* 16800 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
6213 /* 16804 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6214 /* 16808 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6215 /* 16812 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6216 /* 16817 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
6217 /* 16821 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6218 /* 16823 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6219 /* 16823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT),
6220 /* 16826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6221 /* 16828 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6222 /* 16832 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6223 /* 16836 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6224 /* 16839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6225 /* 16845 */ GIR_RootConstrainSelectedInstOperands,
6226 /* 16846 */ // GIR_Coverage, 512,
6227 /* 16846 */ GIR_EraseRootFromParent_Done,
6228 /* 16847 */ // Label 356: @16847
6229 /* 16847 */ GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(16941), // Rule ID 182 //
6230 /* 16852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
6231 /* 16855 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6232 /* 16859 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6233 /* 16863 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6234 /* 16867 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6235 /* 16871 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6236 /* 16876 */ // MIs[1] Operand 2
6237 /* 16876 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6238 /* 16887 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6239 /* 16891 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6240 /* 16895 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6241 /* 16899 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6242 /* 16904 */ // MIs[2] Operand 2
6243 /* 16904 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6244 /* 16915 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6245 /* 16917 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6246 /* 16917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB),
6247 /* 16920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6248 /* 16922 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6249 /* 16926 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6250 /* 16930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6251 /* 16933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6252 /* 16939 */ GIR_RootConstrainSelectedInstOperands,
6253 /* 16940 */ // GIR_Coverage, 182,
6254 /* 16940 */ GIR_EraseRootFromParent_Done,
6255 /* 16941 */ // Label 357: @16941
6256 /* 16941 */ GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(17035), // Rule ID 511 //
6257 /* 16946 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
6258 /* 16949 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6259 /* 16953 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6260 /* 16957 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6261 /* 16961 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6262 /* 16965 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6263 /* 16970 */ // MIs[1] Operand 2
6264 /* 16970 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6265 /* 16981 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6266 /* 16985 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6267 /* 16989 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6268 /* 16993 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6269 /* 16998 */ // MIs[2] Operand 2
6270 /* 16998 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6271 /* 17009 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6272 /* 17011 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6273 /* 17011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB),
6274 /* 17014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6275 /* 17016 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6276 /* 17020 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6277 /* 17024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6278 /* 17027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6279 /* 17033 */ GIR_RootConstrainSelectedInstOperands,
6280 /* 17034 */ // GIR_Coverage, 511,
6281 /* 17034 */ GIR_EraseRootFromParent_Done,
6282 /* 17035 */ // Label 358: @17035
6283 /* 17035 */ GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(17081), // Rule ID 168 //
6284 /* 17040 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
6285 /* 17043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6286 /* 17047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6287 /* 17051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6288 /* 17055 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
6289 /* 17055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MUL),
6290 /* 17058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6291 /* 17060 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6292 /* 17062 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6293 /* 17064 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6294 /* 17067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6295 /* 17073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6296 /* 17079 */ GIR_RootConstrainSelectedInstOperands,
6297 /* 17080 */ // GIR_Coverage, 168,
6298 /* 17080 */ GIR_EraseRootFromParent_Done,
6299 /* 17081 */ // Label 359: @17081
6300 /* 17081 */ GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(17127), // Rule ID 169 //
6301 /* 17086 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6_UseMulOps),
6302 /* 17089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6303 /* 17093 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6304 /* 17097 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6305 /* 17101 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
6306 /* 17101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MULv5),
6307 /* 17104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6308 /* 17106 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6309 /* 17108 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6310 /* 17110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6311 /* 17113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6312 /* 17119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6313 /* 17125 */ GIR_RootConstrainSelectedInstOperands,
6314 /* 17126 */ // GIR_Coverage, 169,
6315 /* 17126 */ GIR_EraseRootFromParent_Done,
6316 /* 17127 */ // Label 360: @17127
6317 /* 17127 */ GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(17173), // Rule ID 322 //
6318 /* 17132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
6319 /* 17135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6320 /* 17139 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6321 /* 17143 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6322 /* 17147 */ // (mul:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tMUL:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
6323 /* 17147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMUL),
6324 /* 17150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6325 /* 17152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
6326 /* 17158 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6327 /* 17160 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6328 /* 17162 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6329 /* 17165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6330 /* 17171 */ GIR_RootConstrainSelectedInstOperands,
6331 /* 17172 */ // GIR_Coverage, 322,
6332 /* 17172 */ GIR_EraseRootFromParent_Done,
6333 /* 17173 */ // Label 361: @17173
6334 /* 17173 */ GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(17213), // Rule ID 501 //
6335 /* 17178 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6336 /* 17181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6337 /* 17185 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6338 /* 17189 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6339 /* 17193 */ // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6340 /* 17193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MUL),
6341 /* 17196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6342 /* 17198 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6343 /* 17200 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6344 /* 17202 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6345 /* 17205 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6346 /* 17211 */ GIR_RootConstrainSelectedInstOperands,
6347 /* 17212 */ // GIR_Coverage, 501,
6348 /* 17212 */ GIR_EraseRootFromParent_Done,
6349 /* 17213 */ // Label 362: @17213
6350 /* 17213 */ GIM_Reject,
6351 /* 17214 */ // Label 350: @17214
6352 /* 17214 */ GIM_Reject,
6353 /* 17215 */ // Label 343: @17215
6354 /* 17215 */ GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(17261), // Rule ID 955 //
6355 /* 17220 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6356 /* 17223 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
6357 /* 17226 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
6358 /* 17229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6359 /* 17233 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6360 /* 17237 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6361 /* 17241 */ // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
6362 /* 17241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i8),
6363 /* 17244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6364 /* 17246 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6365 /* 17248 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6366 /* 17250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6367 /* 17253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6368 /* 17259 */ GIR_RootConstrainSelectedInstOperands,
6369 /* 17260 */ // GIR_Coverage, 955,
6370 /* 17260 */ GIR_EraseRootFromParent_Done,
6371 /* 17261 */ // Label 363: @17261
6372 /* 17261 */ GIM_Reject,
6373 /* 17262 */ // Label 344: @17262
6374 /* 17262 */ GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(17375),
6375 /* 17267 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
6376 /* 17270 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
6377 /* 17273 */ GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(17313), // Rule ID 958 //
6378 /* 17278 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6379 /* 17281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6380 /* 17285 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6381 /* 17289 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6382 /* 17293 */ // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
6383 /* 17293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv16i8),
6384 /* 17296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6385 /* 17298 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6386 /* 17300 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6387 /* 17302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6388 /* 17305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6389 /* 17311 */ GIR_RootConstrainSelectedInstOperands,
6390 /* 17312 */ // GIR_Coverage, 958,
6391 /* 17312 */ GIR_EraseRootFromParent_Done,
6392 /* 17313 */ // Label 365: @17313
6393 /* 17313 */ GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(17374), // Rule ID 3841 //
6394 /* 17318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6395 /* 17321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6396 /* 17325 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6397 /* 17329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6398 /* 17333 */ // (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
6399 /* 17333 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6400 /* 17336 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6401 /* 17340 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6402 /* 17345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi8),
6403 /* 17348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6404 /* 17350 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
6405 /* 17352 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
6406 /* 17354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6407 /* 17357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6408 /* 17363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6409 /* 17369 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6410 /* 17372 */ GIR_RootConstrainSelectedInstOperands,
6411 /* 17373 */ // GIR_Coverage, 3841,
6412 /* 17373 */ GIR_EraseRootFromParent_Done,
6413 /* 17374 */ // Label 366: @17374
6414 /* 17374 */ GIM_Reject,
6415 /* 17375 */ // Label 364: @17375
6416 /* 17375 */ GIM_Reject,
6417 /* 17376 */ // Label 345: @17376
6418 /* 17376 */ GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(17422), // Rule ID 956 //
6419 /* 17381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6420 /* 17384 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
6421 /* 17387 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
6422 /* 17390 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6423 /* 17394 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6424 /* 17398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6425 /* 17402 */ // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
6426 /* 17402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i16),
6427 /* 17405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6428 /* 17407 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6429 /* 17409 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6430 /* 17411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6431 /* 17414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6432 /* 17420 */ GIR_RootConstrainSelectedInstOperands,
6433 /* 17421 */ // GIR_Coverage, 956,
6434 /* 17421 */ GIR_EraseRootFromParent_Done,
6435 /* 17422 */ // Label 367: @17422
6436 /* 17422 */ GIM_Reject,
6437 /* 17423 */ // Label 346: @17423
6438 /* 17423 */ GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(17651),
6439 /* 17428 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
6440 /* 17431 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
6441 /* 17434 */ GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(17549), // Rule ID 4917 //
6442 /* 17439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6443 /* 17442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6444 /* 17446 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6445 /* 17450 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6446 /* 17454 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
6447 /* 17458 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6448 /* 17463 */ // MIs[1] Operand 2
6449 /* 17463 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
6450 /* 17474 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6451 /* 17478 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6452 /* 17482 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
6453 /* 17486 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6454 /* 17491 */ // MIs[2] Operand 2
6455 /* 17491 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
6456 /* 17502 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6457 /* 17504 */ // (mul:{ *:[v8i16] } (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, v8i8:{ *:[Other] }), (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src2, v8i8:{ *:[Other] })) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)
6458 /* 17504 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6459 /* 17507 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6460 /* 17511 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6461 /* 17516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8),
6462 /* 17519 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6463 /* 17521 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6464 /* 17525 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6465 /* 17529 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6466 /* 17532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6467 /* 17538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6468 /* 17544 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6469 /* 17547 */ GIR_RootConstrainSelectedInstOperands,
6470 /* 17548 */ // GIR_Coverage, 4917,
6471 /* 17548 */ GIR_EraseRootFromParent_Done,
6472 /* 17549 */ // Label 369: @17549
6473 /* 17549 */ GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(17589), // Rule ID 959 //
6474 /* 17554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6475 /* 17557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6476 /* 17561 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6477 /* 17565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6478 /* 17569 */ // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
6479 /* 17569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i16),
6480 /* 17572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6481 /* 17574 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6482 /* 17576 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6483 /* 17578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6484 /* 17581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6485 /* 17587 */ GIR_RootConstrainSelectedInstOperands,
6486 /* 17588 */ // GIR_Coverage, 959,
6487 /* 17588 */ GIR_EraseRootFromParent_Done,
6488 /* 17589 */ // Label 370: @17589
6489 /* 17589 */ GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(17650), // Rule ID 3845 //
6490 /* 17594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6491 /* 17597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6492 /* 17601 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6493 /* 17605 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6494 /* 17609 */ // (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
6495 /* 17609 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6496 /* 17612 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6497 /* 17616 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6498 /* 17621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi16),
6499 /* 17624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6500 /* 17626 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
6501 /* 17628 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
6502 /* 17630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6503 /* 17633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6504 /* 17639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6505 /* 17645 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6506 /* 17648 */ GIR_RootConstrainSelectedInstOperands,
6507 /* 17649 */ // GIR_Coverage, 3845,
6508 /* 17649 */ GIR_EraseRootFromParent_Done,
6509 /* 17650 */ // Label 371: @17650
6510 /* 17650 */ GIM_Reject,
6511 /* 17651 */ // Label 368: @17651
6512 /* 17651 */ GIM_Reject,
6513 /* 17652 */ // Label 347: @17652
6514 /* 17652 */ GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(17698), // Rule ID 957 //
6515 /* 17657 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6516 /* 17660 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
6517 /* 17663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
6518 /* 17666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6519 /* 17670 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6520 /* 17674 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6521 /* 17678 */ // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
6522 /* 17678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv2i32),
6523 /* 17681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6524 /* 17683 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6525 /* 17685 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6526 /* 17687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6527 /* 17690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6528 /* 17696 */ GIR_RootConstrainSelectedInstOperands,
6529 /* 17697 */ // GIR_Coverage, 957,
6530 /* 17697 */ GIR_EraseRootFromParent_Done,
6531 /* 17698 */ // Label 372: @17698
6532 /* 17698 */ GIM_Reject,
6533 /* 17699 */ // Label 348: @17699
6534 /* 17699 */ GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(17927),
6535 /* 17704 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
6536 /* 17707 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
6537 /* 17710 */ GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(17825), // Rule ID 4912 //
6538 /* 17715 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6539 /* 17718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6540 /* 17722 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6541 /* 17726 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6542 /* 17730 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6543 /* 17734 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6544 /* 17739 */ // MIs[1] Operand 2
6545 /* 17739 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6546 /* 17750 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6547 /* 17754 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6548 /* 17758 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6549 /* 17762 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6550 /* 17767 */ // MIs[2] Operand 2
6551 /* 17767 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6552 /* 17778 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6553 /* 17780 */ // (mul:{ *:[v4i32] } (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, v4i16:{ *:[Other] }), (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src2, v4i16:{ *:[Other] })) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)
6554 /* 17780 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6555 /* 17783 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6556 /* 17787 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6557 /* 17792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16),
6558 /* 17795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6559 /* 17797 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6560 /* 17801 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6561 /* 17805 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6562 /* 17808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6563 /* 17814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6564 /* 17820 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6565 /* 17823 */ GIR_RootConstrainSelectedInstOperands,
6566 /* 17824 */ // GIR_Coverage, 4912,
6567 /* 17824 */ GIR_EraseRootFromParent_Done,
6568 /* 17825 */ // Label 374: @17825
6569 /* 17825 */ GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(17865), // Rule ID 960 //
6570 /* 17830 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6571 /* 17833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6572 /* 17837 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6573 /* 17841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6574 /* 17845 */ // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
6575 /* 17845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i32),
6576 /* 17848 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6577 /* 17850 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6578 /* 17852 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6579 /* 17854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6580 /* 17857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6581 /* 17863 */ GIR_RootConstrainSelectedInstOperands,
6582 /* 17864 */ // GIR_Coverage, 960,
6583 /* 17864 */ GIR_EraseRootFromParent_Done,
6584 /* 17865 */ // Label 375: @17865
6585 /* 17865 */ GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(17926), // Rule ID 3849 //
6586 /* 17870 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6587 /* 17873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6588 /* 17877 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6589 /* 17881 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6590 /* 17885 */ // (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
6591 /* 17885 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6592 /* 17888 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6593 /* 17892 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6594 /* 17897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi32),
6595 /* 17900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6596 /* 17902 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
6597 /* 17904 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
6598 /* 17906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6599 /* 17909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6600 /* 17915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6601 /* 17921 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6602 /* 17924 */ GIR_RootConstrainSelectedInstOperands,
6603 /* 17925 */ // GIR_Coverage, 3849,
6604 /* 17925 */ GIR_EraseRootFromParent_Done,
6605 /* 17926 */ // Label 376: @17926
6606 /* 17926 */ GIM_Reject,
6607 /* 17927 */ // Label 373: @17927
6608 /* 17927 */ GIM_Reject,
6609 /* 17928 */ // Label 349: @17928
6610 /* 17928 */ GIM_Reject,
6611 /* 17929 */ // Label 3: @17929
6612 /* 17929 */ GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(18024),
6613 /* 17934 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
6614 /* 17937 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
6615 /* 17940 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6616 /* 17943 */ GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(17983), // Rule ID 194 //
6617 /* 17948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInARM_IsARM),
6618 /* 17951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6619 /* 17955 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6620 /* 17959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6621 /* 17963 */ // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6622 /* 17963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SDIV),
6623 /* 17966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6624 /* 17968 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6625 /* 17970 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6626 /* 17972 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6627 /* 17975 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6628 /* 17981 */ GIR_RootConstrainSelectedInstOperands,
6629 /* 17982 */ // GIR_Coverage, 194,
6630 /* 17982 */ GIR_EraseRootFromParent_Done,
6631 /* 17983 */ // Label 378: @17983
6632 /* 17983 */ GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(18023), // Rule ID 531 //
6633 /* 17988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb),
6634 /* 17991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6635 /* 17995 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6636 /* 17999 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6637 /* 18003 */ // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6638 /* 18003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SDIV),
6639 /* 18006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6640 /* 18008 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6641 /* 18010 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6642 /* 18012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6643 /* 18015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6644 /* 18021 */ GIR_RootConstrainSelectedInstOperands,
6645 /* 18022 */ // GIR_Coverage, 531,
6646 /* 18022 */ GIR_EraseRootFromParent_Done,
6647 /* 18023 */ // Label 379: @18023
6648 /* 18023 */ GIM_Reject,
6649 /* 18024 */ // Label 377: @18024
6650 /* 18024 */ GIM_Reject,
6651 /* 18025 */ // Label 4: @18025
6652 /* 18025 */ GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(18120),
6653 /* 18030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
6654 /* 18033 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
6655 /* 18036 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6656 /* 18039 */ GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(18079), // Rule ID 195 //
6657 /* 18044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInARM_IsARM),
6658 /* 18047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6659 /* 18051 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6660 /* 18055 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6661 /* 18059 */ // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6662 /* 18059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDIV),
6663 /* 18062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6664 /* 18064 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6665 /* 18066 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6666 /* 18068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6667 /* 18071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6668 /* 18077 */ GIR_RootConstrainSelectedInstOperands,
6669 /* 18078 */ // GIR_Coverage, 195,
6670 /* 18078 */ GIR_EraseRootFromParent_Done,
6671 /* 18079 */ // Label 381: @18079
6672 /* 18079 */ GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(18119), // Rule ID 532 //
6673 /* 18084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb),
6674 /* 18087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6675 /* 18091 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6676 /* 18095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6677 /* 18099 */ // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6678 /* 18099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDIV),
6679 /* 18102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6680 /* 18104 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6681 /* 18106 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6682 /* 18108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6683 /* 18111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6684 /* 18117 */ GIR_RootConstrainSelectedInstOperands,
6685 /* 18118 */ // GIR_Coverage, 532,
6686 /* 18118 */ GIR_EraseRootFromParent_Done,
6687 /* 18119 */ // Label 382: @18119
6688 /* 18119 */ GIM_Reject,
6689 /* 18120 */ // Label 380: @18120
6690 /* 18120 */ GIM_Reject,
6691 /* 18121 */ // Label 5: @18121
6692 /* 18121 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 396*/ GIMT_Encode4(21292),
6693 /* 18132 */ /*GILLT_s32*//*Label 383*/ GIMT_Encode4(18184),
6694 /* 18136 */ /*GILLT_s64*//*Label 384*/ GIMT_Encode4(20176),
6695 /* 18140 */ /*GILLT_v2s1*//*Label 385*/ GIMT_Encode4(20223),
6696 /* 18144 */ /*GILLT_v4s1*//*Label 386*/ GIMT_Encode4(20341),
6697 /* 18148 */ /*GILLT_v8s1*//*Label 387*/ GIMT_Encode4(20459),
6698 /* 18152 */ /*GILLT_v16s1*//*Label 388*/ GIMT_Encode4(20577),
6699 /* 18156 */ /*GILLT_v8s8*//*Label 389*/ GIMT_Encode4(20695),
6700 /* 18160 */ /*GILLT_v16s8*//*Label 390*/ GIMT_Encode4(20742),
6701 /* 18164 */ /*GILLT_v4s16*//*Label 391*/ GIMT_Encode4(20856),
6702 /* 18168 */ /*GILLT_v8s16*//*Label 392*/ GIMT_Encode4(20903),
6703 /* 18172 */ /*GILLT_v2s32*//*Label 393*/ GIMT_Encode4(21017),
6704 /* 18176 */ /*GILLT_v4s32*//*Label 394*/ GIMT_Encode4(21064),
6705 /* 18180 */ /*GILLT_v2s64*//*Label 395*/ GIMT_Encode4(21178),
6706 /* 18184 */ // Label 383: @18184
6707 /* 18184 */ GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(20175),
6708 /* 18189 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
6709 /* 18192 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6710 /* 18195 */ GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(18268), // Rule ID 2041 //
6711 /* 18200 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
6712 /* 18203 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6713 /* 18207 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6714 /* 18211 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
6715 /* 18215 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6716 /* 18219 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6717 /* 18223 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6718 /* 18228 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8,
6719 /* 18232 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6720 /* 18243 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6721 /* 18245 */ // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
6722 /* 18245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16),
6723 /* 18248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6724 /* 18250 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
6725 /* 18254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
6726 /* 18257 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6727 /* 18260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6728 /* 18266 */ GIR_RootConstrainSelectedInstOperands,
6729 /* 18267 */ // GIR_Coverage, 2041,
6730 /* 18267 */ GIR_EraseRootFromParent_Done,
6731 /* 18268 */ // Label 398: @18268
6732 /* 18268 */ GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(18341), // Rule ID 2298 //
6733 /* 18273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
6734 /* 18276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6735 /* 18280 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6736 /* 18284 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
6737 /* 18288 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6738 /* 18292 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6739 /* 18296 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6740 /* 18301 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8,
6741 /* 18305 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6742 /* 18316 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6743 /* 18318 */ // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
6744 /* 18318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16),
6745 /* 18321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6746 /* 18323 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
6747 /* 18327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
6748 /* 18330 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6749 /* 18333 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6750 /* 18339 */ GIR_RootConstrainSelectedInstOperands,
6751 /* 18340 */ // GIR_Coverage, 2298,
6752 /* 18340 */ GIR_EraseRootFromParent_Done,
6753 /* 18341 */ // Label 399: @18341
6754 /* 18341 */ GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(18389), // Rule ID 2183 //
6755 /* 18346 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
6756 /* 18349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6757 /* 18353 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6758 /* 18357 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
6759 /* 18368 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] }) => (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
6760 /* 18368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB),
6761 /* 18371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6762 /* 18373 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
6763 /* 18375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6764 /* 18378 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6765 /* 18381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6766 /* 18387 */ GIR_RootConstrainSelectedInstOperands,
6767 /* 18388 */ // GIR_Coverage, 2183,
6768 /* 18388 */ GIR_EraseRootFromParent_Done,
6769 /* 18389 */ // Label 400: @18389
6770 /* 18389 */ GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(18437), // Rule ID 2184 //
6771 /* 18394 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
6772 /* 18397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6773 /* 18401 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6774 /* 18405 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
6775 /* 18416 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] }) => (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
6776 /* 18416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTH),
6777 /* 18419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6778 /* 18421 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
6779 /* 18423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6780 /* 18426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6781 /* 18429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6782 /* 18435 */ GIR_RootConstrainSelectedInstOperands,
6783 /* 18436 */ // GIR_Coverage, 2184,
6784 /* 18436 */ GIR_EraseRootFromParent_Done,
6785 /* 18437 */ // Label 401: @18437
6786 /* 18437 */ GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(18485), // Rule ID 2185 //
6787 /* 18442 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
6788 /* 18445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6789 /* 18449 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6790 /* 18453 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6791 /* 18464 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
6792 /* 18464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16),
6793 /* 18467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6794 /* 18469 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
6795 /* 18471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6796 /* 18474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6797 /* 18477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6798 /* 18483 */ GIR_RootConstrainSelectedInstOperands,
6799 /* 18484 */ // GIR_Coverage, 2185,
6800 /* 18484 */ GIR_EraseRootFromParent_Done,
6801 /* 18485 */ // Label 402: @18485
6802 /* 18485 */ GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(18533), // Rule ID 2422 //
6803 /* 18490 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6804 /* 18493 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6805 /* 18497 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6806 /* 18501 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
6807 /* 18512 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
6808 /* 18512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB),
6809 /* 18515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6810 /* 18517 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6811 /* 18519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6812 /* 18522 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6813 /* 18525 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6814 /* 18531 */ GIR_RootConstrainSelectedInstOperands,
6815 /* 18532 */ // GIR_Coverage, 2422,
6816 /* 18532 */ GIR_EraseRootFromParent_Done,
6817 /* 18533 */ // Label 403: @18533
6818 /* 18533 */ GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(18581), // Rule ID 2423 //
6819 /* 18538 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6820 /* 18541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6821 /* 18545 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6822 /* 18549 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
6823 /* 18560 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
6824 /* 18560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTH),
6825 /* 18563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6826 /* 18565 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6827 /* 18567 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6828 /* 18570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6829 /* 18573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6830 /* 18579 */ GIR_RootConstrainSelectedInstOperands,
6831 /* 18580 */ // GIR_Coverage, 2423,
6832 /* 18580 */ GIR_EraseRootFromParent_Done,
6833 /* 18581 */ // Label 404: @18581
6834 /* 18581 */ GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(18629), // Rule ID 2424 //
6835 /* 18586 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
6836 /* 18589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6837 /* 18593 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6838 /* 18597 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6839 /* 18608 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
6840 /* 18608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16),
6841 /* 18611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6842 /* 18613 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6843 /* 18615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6844 /* 18618 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6845 /* 18621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6846 /* 18627 */ GIR_RootConstrainSelectedInstOperands,
6847 /* 18628 */ // GIR_Coverage, 2424,
6848 /* 18628 */ GIR_EraseRootFromParent_Done,
6849 /* 18629 */ // Label 405: @18629
6850 /* 18629 */ GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(18706), // Rule ID 5954 //
6851 /* 18634 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
6852 /* 18637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6853 /* 18641 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6854 /* 18645 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6855 /* 18649 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6856 /* 18653 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6857 /* 18657 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6858 /* 18661 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6859 /* 18665 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6860 /* 18669 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6861 /* 18673 */ // MIs[2] Operand 1
6862 /* 18673 */ // No operand predicates
6863 /* 18673 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6864 /* 18677 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6865 /* 18679 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6866 /* 18679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6867 /* 18682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6868 /* 18684 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6869 /* 18686 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6870 /* 18689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6871 /* 18692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6872 /* 18698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6873 /* 18704 */ GIR_RootConstrainSelectedInstOperands,
6874 /* 18705 */ // GIR_Coverage, 5954,
6875 /* 18705 */ GIR_EraseRootFromParent_Done,
6876 /* 18706 */ // Label 406: @18706
6877 /* 18706 */ GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(18783), // Rule ID 5987 //
6878 /* 18711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6879 /* 18714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6880 /* 18718 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6881 /* 18722 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6882 /* 18726 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6883 /* 18730 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6884 /* 18734 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6885 /* 18738 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6886 /* 18742 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6887 /* 18746 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
6888 /* 18750 */ // MIs[2] Operand 1
6889 /* 18750 */ // No operand predicates
6890 /* 18750 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6891 /* 18754 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6892 /* 18756 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6893 /* 18756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
6894 /* 18759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6895 /* 18761 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6896 /* 18763 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6897 /* 18766 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6898 /* 18769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6899 /* 18775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6900 /* 18781 */ GIR_RootConstrainSelectedInstOperands,
6901 /* 18782 */ // GIR_Coverage, 5987,
6902 /* 18782 */ GIR_EraseRootFromParent_Done,
6903 /* 18783 */ // Label 407: @18783
6904 /* 18783 */ GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(18860), // Rule ID 5953 //
6905 /* 18788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
6906 /* 18791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6907 /* 18795 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6908 /* 18799 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6909 /* 18803 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6910 /* 18807 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6911 /* 18811 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6912 /* 18815 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6913 /* 18819 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6914 /* 18823 */ // MIs[2] Operand 1
6915 /* 18823 */ // No operand predicates
6916 /* 18823 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6917 /* 18827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6918 /* 18831 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6919 /* 18833 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6920 /* 18833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6921 /* 18836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6922 /* 18838 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6923 /* 18840 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6924 /* 18843 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6925 /* 18846 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6926 /* 18852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6927 /* 18858 */ GIR_RootConstrainSelectedInstOperands,
6928 /* 18859 */ // GIR_Coverage, 5953,
6929 /* 18859 */ GIR_EraseRootFromParent_Done,
6930 /* 18860 */ // Label 408: @18860
6931 /* 18860 */ GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(18937), // Rule ID 5986 //
6932 /* 18865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6933 /* 18868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6934 /* 18872 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6935 /* 18876 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6936 /* 18880 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6937 /* 18884 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6938 /* 18888 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6939 /* 18892 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6940 /* 18896 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
6941 /* 18900 */ // MIs[2] Operand 1
6942 /* 18900 */ // No operand predicates
6943 /* 18900 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6944 /* 18904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6945 /* 18908 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6946 /* 18910 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6947 /* 18910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
6948 /* 18913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6949 /* 18915 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6950 /* 18917 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6951 /* 18920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6952 /* 18923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6953 /* 18929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6954 /* 18935 */ GIR_RootConstrainSelectedInstOperands,
6955 /* 18936 */ // GIR_Coverage, 5986,
6956 /* 18936 */ GIR_EraseRootFromParent_Done,
6957 /* 18937 */ // Label 409: @18937
6958 /* 18937 */ GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(19014), // Rule ID 5952 //
6959 /* 18942 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
6960 /* 18945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6961 /* 18949 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6962 /* 18953 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6963 /* 18957 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6964 /* 18961 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6965 /* 18965 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6966 /* 18969 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6967 /* 18973 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6968 /* 18977 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6969 /* 18981 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6970 /* 18985 */ // MIs[2] Operand 1
6971 /* 18985 */ // No operand predicates
6972 /* 18985 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6973 /* 18987 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6974 /* 18987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6975 /* 18990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6976 /* 18992 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6977 /* 18994 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6978 /* 18997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6979 /* 19000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6980 /* 19006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6981 /* 19012 */ GIR_RootConstrainSelectedInstOperands,
6982 /* 19013 */ // GIR_Coverage, 5952,
6983 /* 19013 */ GIR_EraseRootFromParent_Done,
6984 /* 19014 */ // Label 410: @19014
6985 /* 19014 */ GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(19091), // Rule ID 5985 //
6986 /* 19019 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6987 /* 19022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6988 /* 19026 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6989 /* 19030 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6990 /* 19034 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6991 /* 19038 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6992 /* 19042 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6993 /* 19046 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6994 /* 19050 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6995 /* 19054 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6996 /* 19058 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
6997 /* 19062 */ // MIs[2] Operand 1
6998 /* 19062 */ // No operand predicates
6999 /* 19062 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
7000 /* 19064 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7001 /* 19064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
7002 /* 19067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7003 /* 19069 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7004 /* 19071 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7005 /* 19074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7006 /* 19077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7007 /* 19083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7008 /* 19089 */ GIR_RootConstrainSelectedInstOperands,
7009 /* 19090 */ // GIR_Coverage, 5985,
7010 /* 19090 */ GIR_EraseRootFromParent_Done,
7011 /* 19091 */ // Label 411: @19091
7012 /* 19091 */ GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(19168), // Rule ID 158 //
7013 /* 19096 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
7014 /* 19099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7015 /* 19103 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7016 /* 19107 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7017 /* 19111 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7018 /* 19115 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7019 /* 19119 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7020 /* 19123 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7021 /* 19127 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7022 /* 19131 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
7023 /* 19135 */ // MIs[2] Operand 1
7024 /* 19135 */ // No operand predicates
7025 /* 19135 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7026 /* 19139 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
7027 /* 19141 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] })) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7028 /* 19141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
7029 /* 19144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7030 /* 19146 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7031 /* 19148 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7032 /* 19151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7033 /* 19154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7034 /* 19160 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7035 /* 19166 */ GIR_RootConstrainSelectedInstOperands,
7036 /* 19167 */ // GIR_Coverage, 158,
7037 /* 19167 */ GIR_EraseRootFromParent_Done,
7038 /* 19168 */ // Label 412: @19168
7039 /* 19168 */ GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(19245), // Rule ID 489 //
7040 /* 19173 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7041 /* 19176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7042 /* 19180 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7043 /* 19184 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7044 /* 19188 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7045 /* 19192 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7046 /* 19196 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7047 /* 19200 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7048 /* 19204 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7049 /* 19208 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
7050 /* 19212 */ // MIs[2] Operand 1
7051 /* 19212 */ // No operand predicates
7052 /* 19212 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7053 /* 19216 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
7054 /* 19218 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7055 /* 19218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
7056 /* 19221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7057 /* 19223 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7058 /* 19225 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7059 /* 19228 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7060 /* 19231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7061 /* 19237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7062 /* 19243 */ GIR_RootConstrainSelectedInstOperands,
7063 /* 19244 */ // GIR_Coverage, 489,
7064 /* 19244 */ GIR_EraseRootFromParent_Done,
7065 /* 19245 */ // Label 413: @19245
7066 /* 19245 */ GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(19316), // Rule ID 5955 //
7067 /* 19250 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
7068 /* 19253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7069 /* 19257 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7070 /* 19261 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7071 /* 19265 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7072 /* 19269 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7073 /* 19273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7074 /* 19278 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7075 /* 19282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7076 /* 19286 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7077 /* 19288 */ // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
7078 /* 19288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr),
7079 /* 19291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7080 /* 19293 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
7081 /* 19295 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7082 /* 19299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7083 /* 19302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7084 /* 19308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7085 /* 19314 */ GIR_RootConstrainSelectedInstOperands,
7086 /* 19315 */ // GIR_Coverage, 5955,
7087 /* 19315 */ GIR_EraseRootFromParent_Done,
7088 /* 19316 */ // Label 414: @19316
7089 /* 19316 */ GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(19387), // Rule ID 5976 //
7090 /* 19321 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
7091 /* 19324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7092 /* 19328 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7093 /* 19332 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7094 /* 19336 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7095 /* 19340 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7096 /* 19344 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7097 /* 19349 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7098 /* 19353 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7099 /* 19357 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7100 /* 19359 */ // (and:{ *:[i32] } (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), tGPR:{ *:[i32] }:$Rn) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
7101 /* 19359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC),
7102 /* 19362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
7103 /* 19364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
7104 /* 19370 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
7105 /* 19372 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7106 /* 19376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7107 /* 19379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7108 /* 19385 */ GIR_RootConstrainSelectedInstOperands,
7109 /* 19386 */ // GIR_Coverage, 5976,
7110 /* 19386 */ GIR_EraseRootFromParent_Done,
7111 /* 19387 */ // Label 415: @19387
7112 /* 19387 */ GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(19458), // Rule ID 5988 //
7113 /* 19392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7114 /* 19395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7115 /* 19399 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7116 /* 19403 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7117 /* 19407 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7118 /* 19411 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7119 /* 19415 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7120 /* 19420 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7121 /* 19424 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7122 /* 19428 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7123 /* 19430 */ // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7124 /* 19430 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr),
7125 /* 19433 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7126 /* 19435 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
7127 /* 19437 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7128 /* 19441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7129 /* 19444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7130 /* 19450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7131 /* 19456 */ GIR_RootConstrainSelectedInstOperands,
7132 /* 19457 */ // GIR_Coverage, 5988,
7133 /* 19457 */ GIR_EraseRootFromParent_Done,
7134 /* 19458 */ // Label 416: @19458
7135 /* 19458 */ GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(19529), // Rule ID 159 //
7136 /* 19463 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
7137 /* 19466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7138 /* 19470 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7139 /* 19474 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7140 /* 19478 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7141 /* 19482 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7142 /* 19486 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7143 /* 19490 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7144 /* 19495 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7145 /* 19499 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7146 /* 19501 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
7147 /* 19501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr),
7148 /* 19504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7149 /* 19506 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7150 /* 19508 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7151 /* 19512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7152 /* 19515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7153 /* 19521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7154 /* 19527 */ GIR_RootConstrainSelectedInstOperands,
7155 /* 19528 */ // GIR_Coverage, 159,
7156 /* 19528 */ GIR_EraseRootFromParent_Done,
7157 /* 19529 */ // Label 417: @19529
7158 /* 19529 */ GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(19600), // Rule ID 312 //
7159 /* 19534 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
7160 /* 19537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7161 /* 19541 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7162 /* 19545 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7163 /* 19549 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7164 /* 19553 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7165 /* 19557 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7166 /* 19561 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7167 /* 19566 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7168 /* 19570 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7169 /* 19572 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
7170 /* 19572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC),
7171 /* 19575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
7172 /* 19577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
7173 /* 19583 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7174 /* 19585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7175 /* 19589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7176 /* 19592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7177 /* 19598 */ GIR_RootConstrainSelectedInstOperands,
7178 /* 19599 */ // GIR_Coverage, 312,
7179 /* 19599 */ GIR_EraseRootFromParent_Done,
7180 /* 19600 */ // Label 418: @19600
7181 /* 19600 */ GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(19671), // Rule ID 490 //
7182 /* 19605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7183 /* 19608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7184 /* 19612 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7185 /* 19616 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7186 /* 19620 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7187 /* 19624 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7188 /* 19628 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7189 /* 19632 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7190 /* 19637 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7191 /* 19641 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7192 /* 19643 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7193 /* 19643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr),
7194 /* 19646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7195 /* 19648 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7196 /* 19650 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7197 /* 19654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7198 /* 19657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7199 /* 19663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7200 /* 19669 */ GIR_RootConstrainSelectedInstOperands,
7201 /* 19670 */ // GIR_Coverage, 490,
7202 /* 19670 */ GIR_EraseRootFromParent_Done,
7203 /* 19671 */ // Label 419: @19671
7204 /* 19671 */ GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(19716), // Rule ID 344 //
7205 /* 19676 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
7206 /* 19679 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7207 /* 19683 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7208 /* 19687 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
7209 /* 19698 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
7210 /* 19698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTB),
7211 /* 19701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7212 /* 19703 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
7213 /* 19705 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7214 /* 19708 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7215 /* 19714 */ GIR_RootConstrainSelectedInstOperands,
7216 /* 19715 */ // GIR_Coverage, 344,
7217 /* 19715 */ GIR_EraseRootFromParent_Done,
7218 /* 19716 */ // Label 420: @19716
7219 /* 19716 */ GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(19761), // Rule ID 345 //
7220 /* 19721 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
7221 /* 19724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7222 /* 19728 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7223 /* 19732 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
7224 /* 19743 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
7225 /* 19743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTH),
7226 /* 19746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7227 /* 19748 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
7228 /* 19750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7229 /* 19753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7230 /* 19759 */ GIR_RootConstrainSelectedInstOperands,
7231 /* 19760 */ // GIR_Coverage, 345,
7232 /* 19760 */ GIR_EraseRootFromParent_Done,
7233 /* 19761 */ // Label 421: @19761
7234 /* 19761 */ GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(19820), // Rule ID 2080 //
7235 /* 19766 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
7236 /* 19769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7237 /* 19773 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7238 /* 19777 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7239 /* 19781 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7240 /* 19785 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not),
7241 /* 19789 */ // MIs[1] Operand 1
7242 /* 19789 */ // No operand predicates
7243 /* 19789 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7244 /* 19791 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>>:$imm))
7245 /* 19791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
7246 /* 19794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7247 /* 19796 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
7248 /* 19798 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm
7249 /* 19803 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7250 /* 19806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7251 /* 19812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7252 /* 19818 */ GIR_RootConstrainSelectedInstOperands,
7253 /* 19819 */ // GIR_Coverage, 2080,
7254 /* 19819 */ GIR_EraseRootFromParent_Done,
7255 /* 19820 */ // Label 422: @19820
7256 /* 19820 */ GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(19877), // Rule ID 146 //
7257 /* 19825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
7258 /* 19828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7259 /* 19832 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7260 /* 19836 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7261 /* 19840 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7262 /* 19844 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
7263 /* 19848 */ // MIs[1] Operand 1
7264 /* 19848 */ // No operand predicates
7265 /* 19848 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7266 /* 19850 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7267 /* 19850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDri),
7268 /* 19853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7269 /* 19855 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7270 /* 19857 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7271 /* 19860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7272 /* 19863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7273 /* 19869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7274 /* 19875 */ GIR_RootConstrainSelectedInstOperands,
7275 /* 19876 */ // GIR_Coverage, 146,
7276 /* 19876 */ GIR_EraseRootFromParent_Done,
7277 /* 19877 */ // Label 423: @19877
7278 /* 19877 */ GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(19934), // Rule ID 480 //
7279 /* 19882 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7280 /* 19885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7281 /* 19889 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7282 /* 19893 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7283 /* 19897 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7284 /* 19901 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
7285 /* 19905 */ // MIs[1] Operand 1
7286 /* 19905 */ // No operand predicates
7287 /* 19905 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7288 /* 19907 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7289 /* 19907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDri),
7290 /* 19910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7291 /* 19912 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7292 /* 19914 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7293 /* 19917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7294 /* 19920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7295 /* 19926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7296 /* 19932 */ GIR_RootConstrainSelectedInstOperands,
7297 /* 19933 */ // GIR_Coverage, 480,
7298 /* 19933 */ GIR_EraseRootFromParent_Done,
7299 /* 19934 */ // Label 424: @19934
7300 /* 19934 */ GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(19985), // Rule ID 162 //
7301 /* 19939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM),
7302 /* 19942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7303 /* 19946 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7304 /* 19950 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7305 /* 19954 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7306 /* 19958 */ // MIs[1] Operand 1
7307 /* 19958 */ // No operand predicates
7308 /* 19958 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm),
7309 /* 19962 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7310 /* 19964 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
7311 /* 19964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BFC),
7312 /* 19967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7313 /* 19969 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
7314 /* 19971 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7315 /* 19974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7316 /* 19977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7317 /* 19983 */ GIR_RootConstrainSelectedInstOperands,
7318 /* 19984 */ // GIR_Coverage, 162,
7319 /* 19984 */ GIR_EraseRootFromParent_Done,
7320 /* 19985 */ // Label 425: @19985
7321 /* 19985 */ GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(20036), // Rule ID 492 //
7322 /* 19990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7323 /* 19993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7324 /* 19997 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7325 /* 20001 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7326 /* 20005 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7327 /* 20009 */ // MIs[1] Operand 1
7328 /* 20009 */ // No operand predicates
7329 /* 20009 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm),
7330 /* 20013 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7331 /* 20015 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
7332 /* 20015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BFC),
7333 /* 20018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7334 /* 20020 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
7335 /* 20022 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7336 /* 20025 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7337 /* 20028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7338 /* 20034 */ GIR_RootConstrainSelectedInstOperands,
7339 /* 20035 */ // GIR_Coverage, 492,
7340 /* 20035 */ GIR_EraseRootFromParent_Done,
7341 /* 20036 */ // Label 426: @20036
7342 /* 20036 */ GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(20082), // Rule ID 147 //
7343 /* 20041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
7344 /* 20044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7345 /* 20048 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7346 /* 20052 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7347 /* 20056 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
7348 /* 20056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDrr),
7349 /* 20059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7350 /* 20061 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7351 /* 20063 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
7352 /* 20065 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7353 /* 20068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7354 /* 20074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7355 /* 20080 */ GIR_RootConstrainSelectedInstOperands,
7356 /* 20081 */ // GIR_Coverage, 147,
7357 /* 20081 */ GIR_EraseRootFromParent_Done,
7358 /* 20082 */ // Label 427: @20082
7359 /* 20082 */ GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(20128), // Rule ID 309 //
7360 /* 20087 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
7361 /* 20090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7362 /* 20094 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7363 /* 20098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7364 /* 20102 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tAND:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
7365 /* 20102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tAND),
7366 /* 20105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
7367 /* 20107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
7368 /* 20113 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7369 /* 20115 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
7370 /* 20117 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7371 /* 20120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7372 /* 20126 */ GIR_RootConstrainSelectedInstOperands,
7373 /* 20127 */ // GIR_Coverage, 309,
7374 /* 20127 */ GIR_EraseRootFromParent_Done,
7375 /* 20128 */ // Label 428: @20128
7376 /* 20128 */ GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(20174), // Rule ID 481 //
7377 /* 20133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7378 /* 20136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7379 /* 20140 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7380 /* 20144 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7381 /* 20148 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7382 /* 20148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7383 /* 20151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7384 /* 20153 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7385 /* 20155 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
7386 /* 20157 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7387 /* 20160 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7388 /* 20166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7389 /* 20172 */ GIR_RootConstrainSelectedInstOperands,
7390 /* 20173 */ // GIR_Coverage, 481,
7391 /* 20173 */ GIR_EraseRootFromParent_Done,
7392 /* 20174 */ // Label 429: @20174
7393 /* 20174 */ GIM_Reject,
7394 /* 20175 */ // Label 397: @20175
7395 /* 20175 */ GIM_Reject,
7396 /* 20176 */ // Label 384: @20176
7397 /* 20176 */ GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(20222), // Rule ID 2901 //
7398 /* 20181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7399 /* 20184 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
7400 /* 20187 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
7401 /* 20190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7402 /* 20194 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7403 /* 20198 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7404 /* 20202 */ // (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VANDd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
7405 /* 20202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7406 /* 20205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7407 /* 20207 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7408 /* 20209 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7409 /* 20211 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7410 /* 20214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7411 /* 20220 */ GIR_RootConstrainSelectedInstOperands,
7412 /* 20221 */ // GIR_Coverage, 2901,
7413 /* 20221 */ GIR_EraseRootFromParent_Done,
7414 /* 20222 */ // Label 430: @20222
7415 /* 20222 */ GIM_Reject,
7416 /* 20223 */ // Label 385: @20223
7417 /* 20223 */ GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(20340), // Rule ID 2012 //
7418 /* 20228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7419 /* 20231 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1,
7420 /* 20234 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1,
7421 /* 20237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7422 /* 20241 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7423 /* 20245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7424 /* 20249 */ // (and:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7425 /* 20249 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7426 /* 20252 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7427 /* 20256 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7428 /* 20261 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7429 /* 20265 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7430 /* 20270 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7431 /* 20273 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7432 /* 20277 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7433 /* 20282 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7434 /* 20286 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7435 /* 20291 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7436 /* 20294 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7437 /* 20298 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7438 /* 20303 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7439 /* 20306 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7440 /* 20309 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7441 /* 20312 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7442 /* 20318 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7443 /* 20324 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7444 /* 20326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7445 /* 20329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7446 /* 20331 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7447 /* 20334 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7448 /* 20339 */ // GIR_Coverage, 2012,
7449 /* 20339 */ GIR_EraseRootFromParent_Done,
7450 /* 20340 */ // Label 431: @20340
7451 /* 20340 */ GIM_Reject,
7452 /* 20341 */ // Label 386: @20341
7453 /* 20341 */ GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(20458), // Rule ID 2013 //
7454 /* 20346 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7455 /* 20349 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1,
7456 /* 20352 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1,
7457 /* 20355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7458 /* 20359 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7459 /* 20363 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7460 /* 20367 */ // (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7461 /* 20367 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7462 /* 20370 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7463 /* 20374 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7464 /* 20379 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7465 /* 20383 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7466 /* 20388 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7467 /* 20391 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7468 /* 20395 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7469 /* 20400 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7470 /* 20404 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7471 /* 20409 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7472 /* 20412 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7473 /* 20416 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7474 /* 20421 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7475 /* 20424 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7476 /* 20427 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7477 /* 20430 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7478 /* 20436 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7479 /* 20442 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7480 /* 20444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7481 /* 20447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7482 /* 20449 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7483 /* 20452 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7484 /* 20457 */ // GIR_Coverage, 2013,
7485 /* 20457 */ GIR_EraseRootFromParent_Done,
7486 /* 20458 */ // Label 432: @20458
7487 /* 20458 */ GIM_Reject,
7488 /* 20459 */ // Label 387: @20459
7489 /* 20459 */ GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(20576), // Rule ID 2014 //
7490 /* 20464 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7491 /* 20467 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1,
7492 /* 20470 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1,
7493 /* 20473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7494 /* 20477 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7495 /* 20481 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7496 /* 20485 */ // (and:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7497 /* 20485 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7498 /* 20488 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7499 /* 20492 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7500 /* 20497 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7501 /* 20501 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7502 /* 20506 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7503 /* 20509 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7504 /* 20513 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7505 /* 20518 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7506 /* 20522 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7507 /* 20527 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7508 /* 20530 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7509 /* 20534 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7510 /* 20539 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7511 /* 20542 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7512 /* 20545 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7513 /* 20548 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7514 /* 20554 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7515 /* 20560 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7516 /* 20562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7517 /* 20565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7518 /* 20567 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7519 /* 20570 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7520 /* 20575 */ // GIR_Coverage, 2014,
7521 /* 20575 */ GIR_EraseRootFromParent_Done,
7522 /* 20576 */ // Label 433: @20576
7523 /* 20576 */ GIM_Reject,
7524 /* 20577 */ // Label 388: @20577
7525 /* 20577 */ GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(20694), // Rule ID 2015 //
7526 /* 20582 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7527 /* 20585 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1,
7528 /* 20588 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1,
7529 /* 20591 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7530 /* 20595 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7531 /* 20599 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7532 /* 20603 */ // (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7533 /* 20603 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7534 /* 20606 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7535 /* 20610 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7536 /* 20615 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7537 /* 20619 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7538 /* 20624 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7539 /* 20627 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7540 /* 20631 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7541 /* 20636 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7542 /* 20640 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7543 /* 20645 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7544 /* 20648 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7545 /* 20652 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7546 /* 20657 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7547 /* 20660 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7548 /* 20663 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7549 /* 20666 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7550 /* 20672 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7551 /* 20678 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7552 /* 20680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7553 /* 20683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7554 /* 20685 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7555 /* 20688 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7556 /* 20693 */ // GIR_Coverage, 2015,
7557 /* 20693 */ GIR_EraseRootFromParent_Done,
7558 /* 20694 */ // Label 434: @20694
7559 /* 20694 */ GIM_Reject,
7560 /* 20695 */ // Label 389: @20695
7561 /* 20695 */ GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(20741), // Rule ID 2899 //
7562 /* 20700 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7563 /* 20703 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
7564 /* 20706 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
7565 /* 20709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7566 /* 20713 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7567 /* 20717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7568 /* 20721 */ // (and:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VANDd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
7569 /* 20721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7570 /* 20724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7571 /* 20726 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7572 /* 20728 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7573 /* 20730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7574 /* 20733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7575 /* 20739 */ GIR_RootConstrainSelectedInstOperands,
7576 /* 20740 */ // GIR_Coverage, 2899,
7577 /* 20740 */ GIR_EraseRootFromParent_Done,
7578 /* 20741 */ // Label 435: @20741
7579 /* 20741 */ GIM_Reject,
7580 /* 20742 */ // Label 390: @20742
7581 /* 20742 */ GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(20855),
7582 /* 20747 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
7583 /* 20750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
7584 /* 20753 */ GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(20793), // Rule ID 2902 //
7585 /* 20758 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7586 /* 20761 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7587 /* 20765 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7588 /* 20769 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7589 /* 20773 */ // (and:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VANDq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
7590 /* 20773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7591 /* 20776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7592 /* 20778 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7593 /* 20780 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7594 /* 20782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7595 /* 20785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7596 /* 20791 */ GIR_RootConstrainSelectedInstOperands,
7597 /* 20792 */ // GIR_Coverage, 2902,
7598 /* 20792 */ GIR_EraseRootFromParent_Done,
7599 /* 20793 */ // Label 437: @20793
7600 /* 20793 */ GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(20854), // Rule ID 3741 //
7601 /* 20798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7602 /* 20801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7603 /* 20805 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7604 /* 20809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7605 /* 20813 */ // (and:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VAND:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
7606 /* 20813 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7607 /* 20816 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7608 /* 20820 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7609 /* 20825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7610 /* 20828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7611 /* 20830 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7612 /* 20832 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7613 /* 20834 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7614 /* 20837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7615 /* 20843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7616 /* 20849 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7617 /* 20852 */ GIR_RootConstrainSelectedInstOperands,
7618 /* 20853 */ // GIR_Coverage, 3741,
7619 /* 20853 */ GIR_EraseRootFromParent_Done,
7620 /* 20854 */ // Label 438: @20854
7621 /* 20854 */ GIM_Reject,
7622 /* 20855 */ // Label 436: @20855
7623 /* 20855 */ GIM_Reject,
7624 /* 20856 */ // Label 391: @20856
7625 /* 20856 */ GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(20902), // Rule ID 2900 //
7626 /* 20861 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7627 /* 20864 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
7628 /* 20867 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
7629 /* 20870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7630 /* 20874 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7631 /* 20878 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7632 /* 20882 */ // (and:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VANDd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
7633 /* 20882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7634 /* 20885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7635 /* 20887 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7636 /* 20889 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7637 /* 20891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7638 /* 20894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7639 /* 20900 */ GIR_RootConstrainSelectedInstOperands,
7640 /* 20901 */ // GIR_Coverage, 2900,
7641 /* 20901 */ GIR_EraseRootFromParent_Done,
7642 /* 20902 */ // Label 439: @20902
7643 /* 20902 */ GIM_Reject,
7644 /* 20903 */ // Label 392: @20903
7645 /* 20903 */ GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(21016),
7646 /* 20908 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
7647 /* 20911 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7648 /* 20914 */ GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(20954), // Rule ID 2903 //
7649 /* 20919 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7650 /* 20922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7651 /* 20926 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7652 /* 20930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7653 /* 20934 */ // (and:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VANDq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
7654 /* 20934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7655 /* 20937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7656 /* 20939 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7657 /* 20941 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7658 /* 20943 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7659 /* 20946 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7660 /* 20952 */ GIR_RootConstrainSelectedInstOperands,
7661 /* 20953 */ // GIR_Coverage, 2903,
7662 /* 20953 */ GIR_EraseRootFromParent_Done,
7663 /* 20954 */ // Label 441: @20954
7664 /* 20954 */ GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(21015), // Rule ID 3745 //
7665 /* 20959 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7666 /* 20962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7667 /* 20966 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7668 /* 20970 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7669 /* 20974 */ // (and:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VAND:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
7670 /* 20974 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7671 /* 20977 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7672 /* 20981 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7673 /* 20986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7674 /* 20989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7675 /* 20991 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7676 /* 20993 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7677 /* 20995 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7678 /* 20998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7679 /* 21004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7680 /* 21010 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7681 /* 21013 */ GIR_RootConstrainSelectedInstOperands,
7682 /* 21014 */ // GIR_Coverage, 3745,
7683 /* 21014 */ GIR_EraseRootFromParent_Done,
7684 /* 21015 */ // Label 442: @21015
7685 /* 21015 */ GIM_Reject,
7686 /* 21016 */ // Label 440: @21016
7687 /* 21016 */ GIM_Reject,
7688 /* 21017 */ // Label 393: @21017
7689 /* 21017 */ GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(21063), // Rule ID 1295 //
7690 /* 21022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7691 /* 21025 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
7692 /* 21028 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
7693 /* 21031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7694 /* 21035 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7695 /* 21039 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7696 /* 21043 */ // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
7697 /* 21043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7698 /* 21046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7699 /* 21048 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
7700 /* 21050 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
7701 /* 21052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7702 /* 21055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7703 /* 21061 */ GIR_RootConstrainSelectedInstOperands,
7704 /* 21062 */ // GIR_Coverage, 1295,
7705 /* 21062 */ GIR_EraseRootFromParent_Done,
7706 /* 21063 */ // Label 443: @21063
7707 /* 21063 */ GIM_Reject,
7708 /* 21064 */ // Label 394: @21064
7709 /* 21064 */ GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(21177),
7710 /* 21069 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
7711 /* 21072 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7712 /* 21075 */ GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(21115), // Rule ID 1296 //
7713 /* 21080 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7714 /* 21083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7715 /* 21087 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7716 /* 21091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7717 /* 21095 */ // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
7718 /* 21095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7719 /* 21098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7720 /* 21100 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
7721 /* 21102 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
7722 /* 21104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7723 /* 21107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7724 /* 21113 */ GIR_RootConstrainSelectedInstOperands,
7725 /* 21114 */ // GIR_Coverage, 1296,
7726 /* 21114 */ GIR_EraseRootFromParent_Done,
7727 /* 21115 */ // Label 445: @21115
7728 /* 21115 */ GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(21176), // Rule ID 3749 //
7729 /* 21120 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7730 /* 21123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7731 /* 21127 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7732 /* 21131 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7733 /* 21135 */ // (and:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VAND:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
7734 /* 21135 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7735 /* 21138 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7736 /* 21142 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7737 /* 21147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7738 /* 21150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7739 /* 21152 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7740 /* 21154 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7741 /* 21156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7742 /* 21159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7743 /* 21165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7744 /* 21171 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7745 /* 21174 */ GIR_RootConstrainSelectedInstOperands,
7746 /* 21175 */ // GIR_Coverage, 3749,
7747 /* 21175 */ GIR_EraseRootFromParent_Done,
7748 /* 21176 */ // Label 446: @21176
7749 /* 21176 */ GIM_Reject,
7750 /* 21177 */ // Label 444: @21177
7751 /* 21177 */ GIM_Reject,
7752 /* 21178 */ // Label 395: @21178
7753 /* 21178 */ GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(21291),
7754 /* 21183 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
7755 /* 21186 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7756 /* 21189 */ GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(21229), // Rule ID 2904 //
7757 /* 21194 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7758 /* 21197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7759 /* 21201 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7760 /* 21205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7761 /* 21209 */ // (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VANDq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
7762 /* 21209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7763 /* 21212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7764 /* 21214 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7765 /* 21216 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7766 /* 21218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7767 /* 21221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7768 /* 21227 */ GIR_RootConstrainSelectedInstOperands,
7769 /* 21228 */ // GIR_Coverage, 2904,
7770 /* 21228 */ GIR_EraseRootFromParent_Done,
7771 /* 21229 */ // Label 448: @21229
7772 /* 21229 */ GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(21290), // Rule ID 3753 //
7773 /* 21234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7774 /* 21237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7775 /* 21241 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7776 /* 21245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7777 /* 21249 */ // (and:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VAND:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
7778 /* 21249 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7779 /* 21252 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7780 /* 21256 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7781 /* 21261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7782 /* 21264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7783 /* 21266 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7784 /* 21268 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7785 /* 21270 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7786 /* 21273 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7787 /* 21279 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7788 /* 21285 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7789 /* 21288 */ GIR_RootConstrainSelectedInstOperands,
7790 /* 21289 */ // GIR_Coverage, 3753,
7791 /* 21289 */ GIR_EraseRootFromParent_Done,
7792 /* 21290 */ // Label 449: @21290
7793 /* 21290 */ GIM_Reject,
7794 /* 21291 */ // Label 447: @21291
7795 /* 21291 */ GIM_Reject,
7796 /* 21292 */ // Label 396: @21292
7797 /* 21292 */ GIM_Reject,
7798 /* 21293 */ // Label 6: @21293
7799 /* 21293 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 463*/ GIMT_Encode4(27093),
7800 /* 21304 */ /*GILLT_s32*//*Label 450*/ GIMT_Encode4(21356),
7801 /* 21308 */ /*GILLT_s64*//*Label 451*/ GIMT_Encode4(25977),
7802 /* 21312 */ /*GILLT_v2s1*//*Label 452*/ GIMT_Encode4(26024),
7803 /* 21316 */ /*GILLT_v4s1*//*Label 453*/ GIMT_Encode4(26142),
7804 /* 21320 */ /*GILLT_v8s1*//*Label 454*/ GIMT_Encode4(26260),
7805 /* 21324 */ /*GILLT_v16s1*//*Label 455*/ GIMT_Encode4(26378),
7806 /* 21328 */ /*GILLT_v8s8*//*Label 456*/ GIMT_Encode4(26496),
7807 /* 21332 */ /*GILLT_v16s8*//*Label 457*/ GIMT_Encode4(26543),
7808 /* 21336 */ /*GILLT_v4s16*//*Label 458*/ GIMT_Encode4(26657),
7809 /* 21340 */ /*GILLT_v8s16*//*Label 459*/ GIMT_Encode4(26704),
7810 /* 21344 */ /*GILLT_v2s32*//*Label 460*/ GIMT_Encode4(26818),
7811 /* 21348 */ /*GILLT_v4s32*//*Label 461*/ GIMT_Encode4(26865),
7812 /* 21352 */ /*GILLT_v2s64*//*Label 462*/ GIMT_Encode4(26979),
7813 /* 21356 */ // Label 450: @21356
7814 /* 21356 */ GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(25976),
7815 /* 21361 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
7816 /* 21364 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7817 /* 21367 */ GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(21494), // Rule ID 6236 //
7818 /* 21372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7819 /* 21375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7820 /* 21379 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7821 /* 21383 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7822 /* 21387 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7823 /* 21391 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7824 /* 21395 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7825 /* 21399 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
7826 /* 21403 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7827 /* 21407 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7828 /* 21411 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7829 /* 21416 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
7830 /* 21420 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
7831 /* 21431 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7832 /* 21435 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
7833 /* 21439 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7834 /* 21443 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7835 /* 21447 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7836 /* 21451 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
7837 /* 21455 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7838 /* 21459 */ // MIs[4] Rm
7839 /* 21459 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7840 /* 21464 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
7841 /* 21468 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
7842 /* 21472 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7843 /* 21474 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
7844 /* 21474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH),
7845 /* 21477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7846 /* 21479 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7847 /* 21483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7848 /* 21486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7849 /* 21492 */ GIR_RootConstrainSelectedInstOperands,
7850 /* 21493 */ // GIR_Coverage, 6236,
7851 /* 21493 */ GIR_EraseRootFromParent_Done,
7852 /* 21494 */ // Label 465: @21494
7853 /* 21494 */ GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(21621), // Rule ID 6278 //
7854 /* 21499 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7855 /* 21502 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7856 /* 21506 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7857 /* 21510 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7858 /* 21514 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7859 /* 21518 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7860 /* 21522 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7861 /* 21526 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
7862 /* 21530 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7863 /* 21534 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7864 /* 21538 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7865 /* 21543 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
7866 /* 21547 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
7867 /* 21558 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7868 /* 21562 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
7869 /* 21566 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7870 /* 21570 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7871 /* 21574 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7872 /* 21578 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
7873 /* 21582 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7874 /* 21586 */ // MIs[4] Rm
7875 /* 21586 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7876 /* 21591 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
7877 /* 21595 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
7878 /* 21599 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7879 /* 21601 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
7880 /* 21601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH),
7881 /* 21604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7882 /* 21606 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7883 /* 21610 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7884 /* 21613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7885 /* 21619 */ GIR_RootConstrainSelectedInstOperands,
7886 /* 21620 */ // GIR_Coverage, 6278,
7887 /* 21620 */ GIR_EraseRootFromParent_Done,
7888 /* 21621 */ // Label 466: @21621
7889 /* 21621 */ GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(21748), // Rule ID 2100 //
7890 /* 21626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7891 /* 21629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7892 /* 21633 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7893 /* 21637 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
7894 /* 21641 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7895 /* 21645 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7896 /* 21649 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7897 /* 21653 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
7898 /* 21657 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7899 /* 21661 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7900 /* 21665 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7901 /* 21670 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
7902 /* 21674 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
7903 /* 21678 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7904 /* 21682 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
7905 /* 21686 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7906 /* 21690 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7907 /* 21694 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7908 /* 21698 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
7909 /* 21702 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7910 /* 21706 */ // MIs[4] Rm
7911 /* 21706 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7912 /* 21711 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
7913 /* 21715 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255),
7914 /* 21726 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7915 /* 21728 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
7916 /* 21728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH),
7917 /* 21731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7918 /* 21733 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7919 /* 21737 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7920 /* 21740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7921 /* 21746 */ GIR_RootConstrainSelectedInstOperands,
7922 /* 21747 */ // GIR_Coverage, 2100,
7923 /* 21747 */ GIR_EraseRootFromParent_Done,
7924 /* 21748 */ // Label 467: @21748
7925 /* 21748 */ GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(21875), // Rule ID 2382 //
7926 /* 21753 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7927 /* 21756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7928 /* 21760 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7929 /* 21764 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
7930 /* 21768 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7931 /* 21772 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7932 /* 21776 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7933 /* 21780 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
7934 /* 21784 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7935 /* 21788 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7936 /* 21792 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7937 /* 21797 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
7938 /* 21801 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
7939 /* 21805 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7940 /* 21809 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
7941 /* 21813 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7942 /* 21817 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7943 /* 21821 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7944 /* 21825 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
7945 /* 21829 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7946 /* 21833 */ // MIs[4] Rm
7947 /* 21833 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7948 /* 21838 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
7949 /* 21842 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255),
7950 /* 21853 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7951 /* 21855 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
7952 /* 21855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH),
7953 /* 21858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7954 /* 21860 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7955 /* 21864 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7956 /* 21867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7957 /* 21873 */ GIR_RootConstrainSelectedInstOperands,
7958 /* 21874 */ // GIR_Coverage, 2382,
7959 /* 21874 */ GIR_EraseRootFromParent_Done,
7960 /* 21875 */ // Label 468: @21875
7961 /* 21875 */ GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(22008), // Rule ID 5968 //
7962 /* 21880 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7963 /* 21883 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7964 /* 21887 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7965 /* 21891 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7966 /* 21895 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7967 /* 21899 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7968 /* 21903 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7969 /* 21907 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
7970 /* 21911 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7971 /* 21915 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7972 /* 21919 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7973 /* 21924 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7974 /* 21928 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7975 /* 21932 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
7976 /* 21936 */ // MIs[3] Operand 1
7977 /* 21936 */ // No operand predicates
7978 /* 21936 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7979 /* 21947 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7980 /* 21951 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
7981 /* 21955 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7982 /* 21959 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7983 /* 21963 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7984 /* 21968 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
7985 /* 21979 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7986 /* 21981 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7987 /* 21981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7988 /* 21984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7989 /* 21986 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
7990 /* 21990 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7991 /* 21994 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7992 /* 21997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7993 /* 22000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7994 /* 22006 */ GIR_RootConstrainSelectedInstOperands,
7995 /* 22007 */ // GIR_Coverage, 5968,
7996 /* 22007 */ GIR_EraseRootFromParent_Done,
7997 /* 22008 */ // Label 469: @22008
7998 /* 22008 */ GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(22141), // Rule ID 6005 //
7999 /* 22013 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8000 /* 22016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8001 /* 22020 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8002 /* 22024 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8003 /* 22028 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8004 /* 22032 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8005 /* 22036 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8006 /* 22040 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
8007 /* 22044 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8008 /* 22048 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8009 /* 22052 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8010 /* 22057 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8011 /* 22061 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8012 /* 22065 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
8013 /* 22069 */ // MIs[3] Operand 1
8014 /* 22069 */ // No operand predicates
8015 /* 22069 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8016 /* 22080 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
8017 /* 22084 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
8018 /* 22088 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
8019 /* 22092 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
8020 /* 22096 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8021 /* 22101 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
8022 /* 22112 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8023 /* 22114 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8024 /* 22114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8025 /* 22117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8026 /* 22119 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
8027 /* 22123 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
8028 /* 22127 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8029 /* 22130 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8030 /* 22133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8031 /* 22139 */ GIR_RootConstrainSelectedInstOperands,
8032 /* 22140 */ // GIR_Coverage, 6005,
8033 /* 22140 */ GIR_EraseRootFromParent_Done,
8034 /* 22141 */ // Label 470: @22141
8035 /* 22141 */ GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(22274), // Rule ID 6241 //
8036 /* 22146 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8037 /* 22149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8038 /* 22153 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8039 /* 22157 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8040 /* 22161 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8041 /* 22165 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8042 /* 22169 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8043 /* 22173 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
8044 /* 22177 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8045 /* 22181 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8046 /* 22185 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8047 /* 22190 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8048 /* 22194 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8049 /* 22198 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
8050 /* 22202 */ // MIs[3] Operand 1
8051 /* 22202 */ // No operand predicates
8052 /* 22202 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8053 /* 22213 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
8054 /* 22217 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
8055 /* 22221 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
8056 /* 22225 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
8057 /* 22229 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8058 /* 22234 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
8059 /* 22245 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8060 /* 22247 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
8061 /* 22247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8062 /* 22250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8063 /* 22252 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
8064 /* 22256 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8065 /* 22260 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8066 /* 22263 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8067 /* 22266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8068 /* 22272 */ GIR_RootConstrainSelectedInstOperands,
8069 /* 22273 */ // GIR_Coverage, 6241,
8070 /* 22273 */ GIR_EraseRootFromParent_Done,
8071 /* 22274 */ // Label 471: @22274
8072 /* 22274 */ GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(22407), // Rule ID 6283 //
8073 /* 22279 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8074 /* 22282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8075 /* 22286 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8076 /* 22290 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8077 /* 22294 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8078 /* 22298 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8079 /* 22302 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8080 /* 22306 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
8081 /* 22310 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8082 /* 22314 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8083 /* 22318 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8084 /* 22323 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8085 /* 22327 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8086 /* 22331 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
8087 /* 22335 */ // MIs[3] Operand 1
8088 /* 22335 */ // No operand predicates
8089 /* 22335 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8090 /* 22346 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
8091 /* 22350 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
8092 /* 22354 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
8093 /* 22358 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
8094 /* 22362 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8095 /* 22367 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
8096 /* 22378 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8097 /* 22380 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
8098 /* 22380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8099 /* 22383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8100 /* 22385 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
8101 /* 22389 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8102 /* 22393 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8103 /* 22396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8104 /* 22399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8105 /* 22405 */ GIR_RootConstrainSelectedInstOperands,
8106 /* 22406 */ // GIR_Coverage, 6283,
8107 /* 22406 */ GIR_EraseRootFromParent_Done,
8108 /* 22407 */ // Label 472: @22407
8109 /* 22407 */ GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(22540), // Rule ID 5967 //
8110 /* 22412 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8111 /* 22415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8112 /* 22419 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8113 /* 22423 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8114 /* 22427 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8115 /* 22431 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8116 /* 22435 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8117 /* 22439 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
8118 /* 22443 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8119 /* 22447 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8120 /* 22451 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8121 /* 22456 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8122 /* 22460 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8123 /* 22464 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
8124 /* 22468 */ // MIs[3] Operand 1
8125 /* 22468 */ // No operand predicates
8126 /* 22468 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8127 /* 22479 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
8128 /* 22483 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
8129 /* 22487 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
8130 /* 22491 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
8131 /* 22495 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8132 /* 22500 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535),
8133 /* 22511 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8134 /* 22513 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8135 /* 22513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8136 /* 22516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8137 /* 22518 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
8138 /* 22522 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
8139 /* 22526 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8140 /* 22529 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8141 /* 22532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8142 /* 22538 */ GIR_RootConstrainSelectedInstOperands,
8143 /* 22539 */ // GIR_Coverage, 5967,
8144 /* 22539 */ GIR_EraseRootFromParent_Done,
8145 /* 22540 */ // Label 473: @22540
8146 /* 22540 */ GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(22673), // Rule ID 6004 //
8147 /* 22545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8148 /* 22548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8149 /* 22552 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8150 /* 22556 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8151 /* 22560 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8152 /* 22564 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8153 /* 22568 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8154 /* 22572 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
8155 /* 22576 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8156 /* 22580 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8157 /* 22584 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8158 /* 22589 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8159 /* 22593 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8160 /* 22597 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
8161 /* 22601 */ // MIs[3] Operand 1
8162 /* 22601 */ // No operand predicates
8163 /* 22601 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8164 /* 22612 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
8165 /* 22616 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
8166 /* 22620 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
8167 /* 22624 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
8168 /* 22628 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8169 /* 22633 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535),
8170 /* 22644 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8171 /* 22646 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8172 /* 22646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8173 /* 22649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8174 /* 22651 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
8175 /* 22655 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
8176 /* 22659 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8177 /* 22662 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8178 /* 22665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8179 /* 22671 */ GIR_RootConstrainSelectedInstOperands,
8180 /* 22672 */ // GIR_Coverage, 6004,
8181 /* 22672 */ GIR_EraseRootFromParent_Done,
8182 /* 22673 */ // Label 474: @22673
8183 /* 22673 */ GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(22806), // Rule ID 202 //
8184 /* 22678 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8185 /* 22681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8186 /* 22685 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8187 /* 22689 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8188 /* 22693 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8189 /* 22697 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8190 /* 22701 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8191 /* 22706 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8192 /* 22717 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8193 /* 22721 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8194 /* 22725 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8195 /* 22729 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8196 /* 22733 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8197 /* 22737 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
8198 /* 22741 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8199 /* 22745 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8200 /* 22749 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8201 /* 22754 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8202 /* 22758 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8203 /* 22762 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
8204 /* 22766 */ // MIs[4] Operand 1
8205 /* 22766 */ // No operand predicates
8206 /* 22766 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8207 /* 22777 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8208 /* 22779 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8209 /* 22779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8210 /* 22782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8211 /* 22784 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8212 /* 22788 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8213 /* 22792 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8214 /* 22795 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8215 /* 22798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8216 /* 22804 */ GIR_RootConstrainSelectedInstOperands,
8217 /* 22805 */ // GIR_Coverage, 202,
8218 /* 22805 */ GIR_EraseRootFromParent_Done,
8219 /* 22806 */ // Label 475: @22806
8220 /* 22806 */ GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(22939), // Rule ID 539 //
8221 /* 22811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8222 /* 22814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8223 /* 22818 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8224 /* 22822 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8225 /* 22826 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8226 /* 22830 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8227 /* 22834 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8228 /* 22839 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8229 /* 22850 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8230 /* 22854 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8231 /* 22858 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8232 /* 22862 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8233 /* 22866 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8234 /* 22870 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
8235 /* 22874 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8236 /* 22878 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8237 /* 22882 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8238 /* 22887 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8239 /* 22891 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8240 /* 22895 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
8241 /* 22899 */ // MIs[4] Operand 1
8242 /* 22899 */ // No operand predicates
8243 /* 22899 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8244 /* 22910 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8245 /* 22912 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8246 /* 22912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8247 /* 22915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8248 /* 22917 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8249 /* 22921 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8250 /* 22925 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8251 /* 22928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8252 /* 22931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8253 /* 22937 */ GIR_RootConstrainSelectedInstOperands,
8254 /* 22938 */ // GIR_Coverage, 539,
8255 /* 22938 */ GIR_EraseRootFromParent_Done,
8256 /* 22939 */ // Label 476: @22939
8257 /* 22939 */ GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(23072), // Rule ID 2105 //
8258 /* 22944 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8259 /* 22947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8260 /* 22951 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8261 /* 22955 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8262 /* 22959 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8263 /* 22963 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8264 /* 22967 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8265 /* 22972 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8266 /* 22983 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8267 /* 22987 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8268 /* 22991 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8269 /* 22995 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8270 /* 22999 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8271 /* 23003 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
8272 /* 23007 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8273 /* 23011 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8274 /* 23015 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8275 /* 23020 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8276 /* 23024 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8277 /* 23028 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
8278 /* 23032 */ // MIs[4] Operand 1
8279 /* 23032 */ // No operand predicates
8280 /* 23032 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8281 /* 23043 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8282 /* 23045 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
8283 /* 23045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8284 /* 23048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8285 /* 23050 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8286 /* 23054 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
8287 /* 23058 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8288 /* 23061 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8289 /* 23064 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8290 /* 23070 */ GIR_RootConstrainSelectedInstOperands,
8291 /* 23071 */ // GIR_Coverage, 2105,
8292 /* 23071 */ GIR_EraseRootFromParent_Done,
8293 /* 23072 */ // Label 477: @23072
8294 /* 23072 */ GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(23205), // Rule ID 2387 //
8295 /* 23077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8296 /* 23080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8297 /* 23084 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8298 /* 23088 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8299 /* 23092 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8300 /* 23096 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8301 /* 23100 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8302 /* 23105 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8303 /* 23116 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8304 /* 23120 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8305 /* 23124 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8306 /* 23128 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8307 /* 23132 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8308 /* 23136 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
8309 /* 23140 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8310 /* 23144 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8311 /* 23148 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8312 /* 23153 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8313 /* 23157 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8314 /* 23161 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
8315 /* 23165 */ // MIs[4] Operand 1
8316 /* 23165 */ // No operand predicates
8317 /* 23165 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8318 /* 23176 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8319 /* 23178 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
8320 /* 23178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8321 /* 23181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8322 /* 23183 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8323 /* 23187 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
8324 /* 23191 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8325 /* 23194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8326 /* 23197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8327 /* 23203 */ GIR_RootConstrainSelectedInstOperands,
8328 /* 23204 */ // GIR_Coverage, 2387,
8329 /* 23204 */ GIR_EraseRootFromParent_Done,
8330 /* 23205 */ // Label 478: @23205
8331 /* 23205 */ GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(23338), // Rule ID 201 //
8332 /* 23210 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8333 /* 23213 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8334 /* 23217 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8335 /* 23221 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8336 /* 23225 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8337 /* 23229 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8338 /* 23233 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8339 /* 23238 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8340 /* 23249 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8341 /* 23253 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8342 /* 23257 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8343 /* 23261 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8344 /* 23265 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8345 /* 23269 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
8346 /* 23273 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8347 /* 23277 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8348 /* 23281 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8349 /* 23286 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8350 /* 23290 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8351 /* 23294 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
8352 /* 23298 */ // MIs[4] Operand 1
8353 /* 23298 */ // No operand predicates
8354 /* 23298 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8355 /* 23309 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8356 /* 23311 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8357 /* 23311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8358 /* 23314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8359 /* 23316 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8360 /* 23320 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8361 /* 23324 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8362 /* 23327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8363 /* 23330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8364 /* 23336 */ GIR_RootConstrainSelectedInstOperands,
8365 /* 23337 */ // GIR_Coverage, 201,
8366 /* 23337 */ GIR_EraseRootFromParent_Done,
8367 /* 23338 */ // Label 479: @23338
8368 /* 23338 */ GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(23471), // Rule ID 538 //
8369 /* 23343 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8370 /* 23346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8371 /* 23350 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8372 /* 23354 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8373 /* 23358 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8374 /* 23362 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8375 /* 23366 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8376 /* 23371 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8377 /* 23382 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8378 /* 23386 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8379 /* 23390 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8380 /* 23394 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8381 /* 23398 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8382 /* 23402 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
8383 /* 23406 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8384 /* 23410 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8385 /* 23414 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8386 /* 23419 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8387 /* 23423 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8388 /* 23427 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
8389 /* 23431 */ // MIs[4] Operand 1
8390 /* 23431 */ // No operand predicates
8391 /* 23431 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8392 /* 23442 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8393 /* 23444 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8394 /* 23444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8395 /* 23447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8396 /* 23449 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8397 /* 23453 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8398 /* 23457 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8399 /* 23460 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8400 /* 23463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8401 /* 23469 */ GIR_RootConstrainSelectedInstOperands,
8402 /* 23470 */ // GIR_Coverage, 538,
8403 /* 23470 */ GIR_EraseRootFromParent_Done,
8404 /* 23471 */ // Label 480: @23471
8405 /* 23471 */ GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(23576), // Rule ID 2101 //
8406 /* 23476 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8407 /* 23479 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8408 /* 23483 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8409 /* 23487 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8410 /* 23491 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8411 /* 23495 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8412 /* 23499 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8413 /* 23504 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8414 /* 23515 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8415 /* 23519 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8416 /* 23523 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8417 /* 23527 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8418 /* 23531 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8419 /* 23536 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8420 /* 23547 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8421 /* 23549 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
8422 /* 23549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8423 /* 23552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8424 /* 23554 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8425 /* 23558 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
8426 /* 23562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8427 /* 23565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8428 /* 23568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8429 /* 23574 */ GIR_RootConstrainSelectedInstOperands,
8430 /* 23575 */ // GIR_Coverage, 2101,
8431 /* 23575 */ GIR_EraseRootFromParent_Done,
8432 /* 23576 */ // Label 481: @23576
8433 /* 23576 */ GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(23681), // Rule ID 2383 //
8434 /* 23581 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8435 /* 23584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8436 /* 23588 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8437 /* 23592 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8438 /* 23596 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8439 /* 23600 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8440 /* 23604 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8441 /* 23609 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8442 /* 23620 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8443 /* 23624 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8444 /* 23628 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8445 /* 23632 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8446 /* 23636 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8447 /* 23641 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8448 /* 23652 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8449 /* 23654 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
8450 /* 23654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8451 /* 23657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8452 /* 23659 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8453 /* 23663 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8454 /* 23667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8455 /* 23670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8456 /* 23673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8457 /* 23679 */ GIR_RootConstrainSelectedInstOperands,
8458 /* 23680 */ // GIR_Coverage, 2383,
8459 /* 23680 */ GIR_EraseRootFromParent_Done,
8460 /* 23681 */ // Label 482: @23681
8461 /* 23681 */ GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(23786), // Rule ID 6237 //
8462 /* 23686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8463 /* 23689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8464 /* 23693 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8465 /* 23697 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8466 /* 23701 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8467 /* 23705 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8468 /* 23709 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8469 /* 23714 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8470 /* 23725 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8471 /* 23729 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8472 /* 23733 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8473 /* 23737 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8474 /* 23741 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8475 /* 23746 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8476 /* 23757 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8477 /* 23759 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
8478 /* 23759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8479 /* 23762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8480 /* 23764 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
8481 /* 23768 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
8482 /* 23772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8483 /* 23775 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8484 /* 23778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8485 /* 23784 */ GIR_RootConstrainSelectedInstOperands,
8486 /* 23785 */ // GIR_Coverage, 6237,
8487 /* 23785 */ GIR_EraseRootFromParent_Done,
8488 /* 23786 */ // Label 483: @23786
8489 /* 23786 */ GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(23891), // Rule ID 6279 //
8490 /* 23791 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8491 /* 23794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8492 /* 23798 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8493 /* 23802 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8494 /* 23806 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8495 /* 23810 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8496 /* 23814 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8497 /* 23819 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8498 /* 23830 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8499 /* 23834 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8500 /* 23838 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8501 /* 23842 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8502 /* 23846 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8503 /* 23851 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8504 /* 23862 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8505 /* 23864 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
8506 /* 23864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8507 /* 23867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8508 /* 23869 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
8509 /* 23873 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8510 /* 23877 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8511 /* 23880 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8512 /* 23883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8513 /* 23889 */ GIR_RootConstrainSelectedInstOperands,
8514 /* 23890 */ // GIR_Coverage, 6279,
8515 /* 23890 */ GIR_EraseRootFromParent_Done,
8516 /* 23891 */ // Label 484: @23891
8517 /* 23891 */ GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(23997), // Rule ID 2104 //
8518 /* 23896 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8519 /* 23899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8520 /* 23903 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8521 /* 23907 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8522 /* 23911 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8523 /* 23915 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8524 /* 23919 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8525 /* 23924 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8526 /* 23935 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8527 /* 23939 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
8528 /* 23943 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8529 /* 23947 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8530 /* 23951 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8531 /* 23956 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8532 /* 23960 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8533 /* 23964 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8534 /* 23968 */ // MIs[3] Operand 1
8535 /* 23968 */ // No operand predicates
8536 /* 23968 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8537 /* 23970 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8538 /* 23970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8539 /* 23973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8540 /* 23975 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8541 /* 23979 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8542 /* 23983 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8543 /* 23986 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8544 /* 23989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8545 /* 23995 */ GIR_RootConstrainSelectedInstOperands,
8546 /* 23996 */ // GIR_Coverage, 2104,
8547 /* 23996 */ GIR_EraseRootFromParent_Done,
8548 /* 23997 */ // Label 485: @23997
8549 /* 23997 */ GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(24103), // Rule ID 2386 //
8550 /* 24002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8551 /* 24005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8552 /* 24009 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8553 /* 24013 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8554 /* 24017 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8555 /* 24021 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8556 /* 24025 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8557 /* 24030 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8558 /* 24041 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8559 /* 24045 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
8560 /* 24049 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8561 /* 24053 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8562 /* 24057 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8563 /* 24062 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8564 /* 24066 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8565 /* 24070 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8566 /* 24074 */ // MIs[3] Operand 1
8567 /* 24074 */ // No operand predicates
8568 /* 24074 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8569 /* 24076 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8570 /* 24076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8571 /* 24079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8572 /* 24081 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8573 /* 24085 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8574 /* 24089 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8575 /* 24092 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8576 /* 24095 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8577 /* 24101 */ GIR_RootConstrainSelectedInstOperands,
8578 /* 24102 */ // GIR_Coverage, 2386,
8579 /* 24102 */ GIR_EraseRootFromParent_Done,
8580 /* 24103 */ // Label 486: @24103
8581 /* 24103 */ GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(24209), // Rule ID 2103 //
8582 /* 24108 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8583 /* 24111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8584 /* 24115 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8585 /* 24119 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8586 /* 24123 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8587 /* 24127 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8588 /* 24131 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8589 /* 24136 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8590 /* 24147 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8591 /* 24151 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
8592 /* 24155 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8593 /* 24159 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8594 /* 24163 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8595 /* 24168 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8596 /* 24172 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8597 /* 24176 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8598 /* 24180 */ // MIs[3] Operand 1
8599 /* 24180 */ // No operand predicates
8600 /* 24180 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8601 /* 24182 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8602 /* 24182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8603 /* 24185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8604 /* 24187 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8605 /* 24191 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8606 /* 24195 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8607 /* 24198 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8608 /* 24201 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8609 /* 24207 */ GIR_RootConstrainSelectedInstOperands,
8610 /* 24208 */ // GIR_Coverage, 2103,
8611 /* 24208 */ GIR_EraseRootFromParent_Done,
8612 /* 24209 */ // Label 487: @24209
8613 /* 24209 */ GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(24315), // Rule ID 2385 //
8614 /* 24214 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8615 /* 24217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8616 /* 24221 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8617 /* 24225 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8618 /* 24229 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8619 /* 24233 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8620 /* 24237 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8621 /* 24242 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8622 /* 24253 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8623 /* 24257 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
8624 /* 24261 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8625 /* 24265 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8626 /* 24269 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8627 /* 24274 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8628 /* 24278 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8629 /* 24282 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8630 /* 24286 */ // MIs[3] Operand 1
8631 /* 24286 */ // No operand predicates
8632 /* 24286 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8633 /* 24288 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8634 /* 24288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8635 /* 24291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8636 /* 24293 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8637 /* 24297 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8638 /* 24301 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8639 /* 24304 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8640 /* 24307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8641 /* 24313 */ GIR_RootConstrainSelectedInstOperands,
8642 /* 24314 */ // GIR_Coverage, 2385,
8643 /* 24314 */ GIR_EraseRootFromParent_Done,
8644 /* 24315 */ // Label 488: @24315
8645 /* 24315 */ GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(24421), // Rule ID 2102 //
8646 /* 24320 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8647 /* 24323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8648 /* 24327 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8649 /* 24331 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8650 /* 24335 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8651 /* 24339 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8652 /* 24343 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8653 /* 24348 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8654 /* 24359 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8655 /* 24363 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
8656 /* 24367 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8657 /* 24371 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8658 /* 24375 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8659 /* 24380 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8660 /* 24384 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8661 /* 24388 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8662 /* 24392 */ // MIs[3] Operand 1
8663 /* 24392 */ // No operand predicates
8664 /* 24392 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8665 /* 24394 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8666 /* 24394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8667 /* 24397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8668 /* 24399 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8669 /* 24403 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
8670 /* 24407 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8671 /* 24410 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8672 /* 24413 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8673 /* 24419 */ GIR_RootConstrainSelectedInstOperands,
8674 /* 24420 */ // GIR_Coverage, 2102,
8675 /* 24420 */ GIR_EraseRootFromParent_Done,
8676 /* 24421 */ // Label 489: @24421
8677 /* 24421 */ GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(24527), // Rule ID 2384 //
8678 /* 24426 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8679 /* 24429 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8680 /* 24433 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8681 /* 24437 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8682 /* 24441 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8683 /* 24445 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8684 /* 24449 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8685 /* 24454 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8686 /* 24465 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8687 /* 24469 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
8688 /* 24473 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8689 /* 24477 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8690 /* 24481 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8691 /* 24486 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8692 /* 24490 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8693 /* 24494 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8694 /* 24498 */ // MIs[3] Operand 1
8695 /* 24498 */ // No operand predicates
8696 /* 24498 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8697 /* 24500 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8698 /* 24500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8699 /* 24503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8700 /* 24505 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8701 /* 24509 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8702 /* 24513 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8703 /* 24516 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8704 /* 24519 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8705 /* 24525 */ GIR_RootConstrainSelectedInstOperands,
8706 /* 24526 */ // GIR_Coverage, 2384,
8707 /* 24526 */ GIR_EraseRootFromParent_Done,
8708 /* 24527 */ // Label 490: @24527
8709 /* 24527 */ GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(24633), // Rule ID 6240 //
8710 /* 24532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8711 /* 24535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8712 /* 24539 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8713 /* 24543 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
8714 /* 24547 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8715 /* 24551 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8716 /* 24555 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8717 /* 24560 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8718 /* 24564 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8719 /* 24568 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8720 /* 24572 */ // MIs[2] Operand 1
8721 /* 24572 */ // No operand predicates
8722 /* 24572 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8723 /* 24576 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8724 /* 24580 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8725 /* 24584 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8726 /* 24588 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8727 /* 24593 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8728 /* 24604 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8729 /* 24606 */ // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8730 /* 24606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8731 /* 24609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8732 /* 24611 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8733 /* 24615 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8734 /* 24619 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8735 /* 24622 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8736 /* 24625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8737 /* 24631 */ GIR_RootConstrainSelectedInstOperands,
8738 /* 24632 */ // GIR_Coverage, 6240,
8739 /* 24632 */ GIR_EraseRootFromParent_Done,
8740 /* 24633 */ // Label 491: @24633
8741 /* 24633 */ GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(24739), // Rule ID 6282 //
8742 /* 24638 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8743 /* 24641 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8744 /* 24645 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8745 /* 24649 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
8746 /* 24653 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8747 /* 24657 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8748 /* 24661 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8749 /* 24666 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8750 /* 24670 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8751 /* 24674 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8752 /* 24678 */ // MIs[2] Operand 1
8753 /* 24678 */ // No operand predicates
8754 /* 24678 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8755 /* 24682 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8756 /* 24686 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8757 /* 24690 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8758 /* 24694 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8759 /* 24699 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8760 /* 24710 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8761 /* 24712 */ // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8762 /* 24712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8763 /* 24715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8764 /* 24717 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8765 /* 24721 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8766 /* 24725 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8767 /* 24728 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8768 /* 24731 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8769 /* 24737 */ GIR_RootConstrainSelectedInstOperands,
8770 /* 24738 */ // GIR_Coverage, 6282,
8771 /* 24738 */ GIR_EraseRootFromParent_Done,
8772 /* 24739 */ // Label 492: @24739
8773 /* 24739 */ GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(24845), // Rule ID 6239 //
8774 /* 24744 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8775 /* 24747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8776 /* 24751 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8777 /* 24755 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
8778 /* 24759 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8779 /* 24763 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8780 /* 24767 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8781 /* 24772 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8782 /* 24776 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8783 /* 24780 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8784 /* 24784 */ // MIs[2] Operand 1
8785 /* 24784 */ // No operand predicates
8786 /* 24784 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8787 /* 24788 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8788 /* 24792 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8789 /* 24796 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8790 /* 24800 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8791 /* 24805 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8792 /* 24816 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8793 /* 24818 */ // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8794 /* 24818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8795 /* 24821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8796 /* 24823 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8797 /* 24827 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8798 /* 24831 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8799 /* 24834 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8800 /* 24837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8801 /* 24843 */ GIR_RootConstrainSelectedInstOperands,
8802 /* 24844 */ // GIR_Coverage, 6239,
8803 /* 24844 */ GIR_EraseRootFromParent_Done,
8804 /* 24845 */ // Label 493: @24845
8805 /* 24845 */ GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(24951), // Rule ID 6281 //
8806 /* 24850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8807 /* 24853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8808 /* 24857 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8809 /* 24861 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
8810 /* 24865 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8811 /* 24869 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8812 /* 24873 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8813 /* 24878 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8814 /* 24882 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8815 /* 24886 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8816 /* 24890 */ // MIs[2] Operand 1
8817 /* 24890 */ // No operand predicates
8818 /* 24890 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8819 /* 24894 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8820 /* 24898 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8821 /* 24902 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8822 /* 24906 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8823 /* 24911 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8824 /* 24922 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8825 /* 24924 */ // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8826 /* 24924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8827 /* 24927 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8828 /* 24929 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8829 /* 24933 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8830 /* 24937 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8831 /* 24940 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8832 /* 24943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8833 /* 24949 */ GIR_RootConstrainSelectedInstOperands,
8834 /* 24950 */ // GIR_Coverage, 6281,
8835 /* 24950 */ GIR_EraseRootFromParent_Done,
8836 /* 24951 */ // Label 494: @24951
8837 /* 24951 */ GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(25057), // Rule ID 6238 //
8838 /* 24956 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8839 /* 24959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8840 /* 24963 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8841 /* 24967 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
8842 /* 24971 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8843 /* 24975 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8844 /* 24979 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8845 /* 24984 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8846 /* 24988 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8847 /* 24992 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8848 /* 24996 */ // MIs[2] Operand 1
8849 /* 24996 */ // No operand predicates
8850 /* 24996 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8851 /* 25000 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8852 /* 25004 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8853 /* 25008 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8854 /* 25012 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8855 /* 25017 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535),
8856 /* 25028 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8857 /* 25030 */ // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8858 /* 25030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8859 /* 25033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8860 /* 25035 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
8861 /* 25039 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
8862 /* 25043 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8863 /* 25046 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8864 /* 25049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8865 /* 25055 */ GIR_RootConstrainSelectedInstOperands,
8866 /* 25056 */ // GIR_Coverage, 6238,
8867 /* 25056 */ GIR_EraseRootFromParent_Done,
8868 /* 25057 */ // Label 495: @25057
8869 /* 25057 */ GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(25163), // Rule ID 6280 //
8870 /* 25062 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8871 /* 25065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8872 /* 25069 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8873 /* 25073 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
8874 /* 25077 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8875 /* 25081 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8876 /* 25085 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8877 /* 25090 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8878 /* 25094 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8879 /* 25098 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8880 /* 25102 */ // MIs[2] Operand 1
8881 /* 25102 */ // No operand predicates
8882 /* 25102 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8883 /* 25106 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8884 /* 25110 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8885 /* 25114 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8886 /* 25118 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8887 /* 25123 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535),
8888 /* 25134 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8889 /* 25136 */ // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8890 /* 25136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8891 /* 25139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8892 /* 25141 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8893 /* 25145 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8894 /* 25149 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8895 /* 25152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8896 /* 25155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8897 /* 25161 */ GIR_RootConstrainSelectedInstOperands,
8898 /* 25162 */ // GIR_Coverage, 6280,
8899 /* 25162 */ GIR_EraseRootFromParent_Done,
8900 /* 25163 */ // Label 496: @25163
8901 /* 25163 */ GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(25240), // Rule ID 5992 //
8902 /* 25168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
8903 /* 25171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8904 /* 25175 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8905 /* 25179 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8906 /* 25183 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8907 /* 25187 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8908 /* 25191 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
8909 /* 25195 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8910 /* 25199 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8911 /* 25203 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8912 /* 25207 */ // MIs[2] Operand 1
8913 /* 25207 */ // No operand predicates
8914 /* 25207 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8915 /* 25211 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8916 /* 25213 */ // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8917 /* 25213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8918 /* 25216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8919 /* 25218 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
8920 /* 25220 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8921 /* 25223 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8922 /* 25226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8923 /* 25232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8924 /* 25238 */ GIR_RootConstrainSelectedInstOperands,
8925 /* 25239 */ // GIR_Coverage, 5992,
8926 /* 25239 */ GIR_EraseRootFromParent_Done,
8927 /* 25240 */ // Label 497: @25240
8928 /* 25240 */ GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(25317), // Rule ID 5991 //
8929 /* 25245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
8930 /* 25248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8931 /* 25252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8932 /* 25256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8933 /* 25260 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8934 /* 25264 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8935 /* 25268 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8936 /* 25272 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8937 /* 25276 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8938 /* 25280 */ // MIs[2] Operand 1
8939 /* 25280 */ // No operand predicates
8940 /* 25280 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
8941 /* 25284 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8942 /* 25288 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8943 /* 25290 */ // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8944 /* 25290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8945 /* 25293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8946 /* 25295 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
8947 /* 25297 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8948 /* 25300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8949 /* 25303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8950 /* 25309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8951 /* 25315 */ GIR_RootConstrainSelectedInstOperands,
8952 /* 25316 */ // GIR_Coverage, 5991,
8953 /* 25316 */ GIR_EraseRootFromParent_Done,
8954 /* 25317 */ // Label 498: @25317
8955 /* 25317 */ GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(25394), // Rule ID 5990 //
8956 /* 25322 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
8957 /* 25325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8958 /* 25329 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8959 /* 25333 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8960 /* 25337 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8961 /* 25341 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8962 /* 25345 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8963 /* 25349 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
8964 /* 25353 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8965 /* 25357 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8966 /* 25361 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8967 /* 25365 */ // MIs[2] Operand 1
8968 /* 25365 */ // No operand predicates
8969 /* 25365 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8970 /* 25367 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8971 /* 25367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8972 /* 25370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8973 /* 25372 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8974 /* 25374 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8975 /* 25377 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8976 /* 25380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8977 /* 25386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8978 /* 25392 */ GIR_RootConstrainSelectedInstOperands,
8979 /* 25393 */ // GIR_Coverage, 5990,
8980 /* 25393 */ GIR_EraseRootFromParent_Done,
8981 /* 25394 */ // Label 499: @25394
8982 /* 25394 */ GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(25471), // Rule ID 495 //
8983 /* 25399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
8984 /* 25402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8985 /* 25406 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8986 /* 25410 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8987 /* 25414 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8988 /* 25418 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8989 /* 25422 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8990 /* 25426 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8991 /* 25430 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8992 /* 25434 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8993 /* 25438 */ // MIs[2] Operand 1
8994 /* 25438 */ // No operand predicates
8995 /* 25438 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
8996 /* 25442 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8997 /* 25444 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8998 /* 25444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8999 /* 25447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9000 /* 25449 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9001 /* 25451 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
9002 /* 25454 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9003 /* 25457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9004 /* 25463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9005 /* 25469 */ GIR_RootConstrainSelectedInstOperands,
9006 /* 25470 */ // GIR_Coverage, 495,
9007 /* 25470 */ GIR_EraseRootFromParent_Done,
9008 /* 25471 */ // Label 500: @25471
9009 /* 25471 */ GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(25542), // Rule ID 5993 //
9010 /* 25476 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9011 /* 25479 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9012 /* 25483 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9013 /* 25487 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9014 /* 25491 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
9015 /* 25495 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
9016 /* 25499 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9017 /* 25504 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
9018 /* 25508 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9019 /* 25512 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9020 /* 25514 */ // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
9021 /* 25514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr),
9022 /* 25517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9023 /* 25519 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
9024 /* 25521 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
9025 /* 25525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9026 /* 25528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9027 /* 25534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9028 /* 25540 */ GIR_RootConstrainSelectedInstOperands,
9029 /* 25541 */ // GIR_Coverage, 5993,
9030 /* 25541 */ GIR_EraseRootFromParent_Done,
9031 /* 25542 */ // Label 501: @25542
9032 /* 25542 */ GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(25613), // Rule ID 496 //
9033 /* 25547 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9034 /* 25550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9035 /* 25554 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9036 /* 25558 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9037 /* 25562 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9038 /* 25566 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
9039 /* 25570 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
9040 /* 25574 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9041 /* 25579 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
9042 /* 25583 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9043 /* 25585 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
9044 /* 25585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr),
9045 /* 25588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9046 /* 25590 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9047 /* 25592 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
9048 /* 25596 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9049 /* 25599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9050 /* 25605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9051 /* 25611 */ GIR_RootConstrainSelectedInstOperands,
9052 /* 25612 */ // GIR_Coverage, 496,
9053 /* 25612 */ GIR_EraseRootFromParent_Done,
9054 /* 25613 */ // Label 502: @25613
9055 /* 25613 */ GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(25668), // Rule ID 2034 //
9056 /* 25618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM),
9057 /* 25621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
9058 /* 25625 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9059 /* 25629 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760),
9060 /* 25640 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
9061 /* 25640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVTi16),
9062 /* 25643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9063 /* 25645 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
9064 /* 25647 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535),
9065 /* 25657 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9066 /* 25660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9067 /* 25666 */ GIR_RootConstrainSelectedInstOperands,
9068 /* 25667 */ // GIR_Coverage, 2034,
9069 /* 25667 */ GIR_EraseRootFromParent_Done,
9070 /* 25668 */ // Label 503: @25668
9071 /* 25668 */ GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(25723), // Rule ID 2280 //
9072 /* 25673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9073 /* 25676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9074 /* 25680 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9075 /* 25684 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760),
9076 /* 25695 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
9077 /* 25695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVTi16),
9078 /* 25698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9079 /* 25700 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
9080 /* 25702 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535),
9081 /* 25712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9082 /* 25715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9083 /* 25721 */ GIR_RootConstrainSelectedInstOperands,
9084 /* 25722 */ // GIR_Coverage, 2280,
9085 /* 25722 */ GIR_EraseRootFromParent_Done,
9086 /* 25723 */ // Label 504: @25723
9087 /* 25723 */ GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(25780), // Rule ID 150 //
9088 /* 25728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
9089 /* 25731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9090 /* 25735 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9091 /* 25739 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9092 /* 25743 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9093 /* 25747 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
9094 /* 25751 */ // MIs[1] Operand 1
9095 /* 25751 */ // No operand predicates
9096 /* 25751 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9097 /* 25753 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
9098 /* 25753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRri),
9099 /* 25756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9100 /* 25758 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9101 /* 25760 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9102 /* 25763 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9103 /* 25766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9104 /* 25772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9105 /* 25778 */ GIR_RootConstrainSelectedInstOperands,
9106 /* 25779 */ // GIR_Coverage, 150,
9107 /* 25779 */ GIR_EraseRootFromParent_Done,
9108 /* 25780 */ // Label 505: @25780
9109 /* 25780 */ GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(25837), // Rule ID 483 //
9110 /* 25785 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9111 /* 25788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9112 /* 25792 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9113 /* 25796 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9114 /* 25800 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9115 /* 25804 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
9116 /* 25808 */ // MIs[1] Operand 1
9117 /* 25808 */ // No operand predicates
9118 /* 25808 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9119 /* 25810 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
9120 /* 25810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRri),
9121 /* 25813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9122 /* 25815 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9123 /* 25817 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9124 /* 25820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9125 /* 25823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9126 /* 25829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9127 /* 25835 */ GIR_RootConstrainSelectedInstOperands,
9128 /* 25836 */ // GIR_Coverage, 483,
9129 /* 25836 */ GIR_EraseRootFromParent_Done,
9130 /* 25837 */ // Label 506: @25837
9131 /* 25837 */ GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(25883), // Rule ID 151 //
9132 /* 25842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
9133 /* 25845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9134 /* 25849 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9135 /* 25853 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9136 /* 25857 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
9137 /* 25857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRrr),
9138 /* 25860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9139 /* 25862 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9140 /* 25864 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9141 /* 25866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9142 /* 25869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9143 /* 25875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9144 /* 25881 */ GIR_RootConstrainSelectedInstOperands,
9145 /* 25882 */ // GIR_Coverage, 151,
9146 /* 25882 */ GIR_EraseRootFromParent_Done,
9147 /* 25883 */ // Label 507: @25883
9148 /* 25883 */ GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(25929), // Rule ID 324 //
9149 /* 25888 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
9150 /* 25891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9151 /* 25895 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9152 /* 25899 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9153 /* 25903 */ // (or:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tORR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
9154 /* 25903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tORR),
9155 /* 25906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
9156 /* 25908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
9157 /* 25914 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9158 /* 25916 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9159 /* 25918 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9160 /* 25921 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9161 /* 25927 */ GIR_RootConstrainSelectedInstOperands,
9162 /* 25928 */ // GIR_Coverage, 324,
9163 /* 25928 */ GIR_EraseRootFromParent_Done,
9164 /* 25929 */ // Label 508: @25929
9165 /* 25929 */ GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(25975), // Rule ID 484 //
9166 /* 25934 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9167 /* 25937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9168 /* 25941 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9169 /* 25945 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9170 /* 25949 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
9171 /* 25949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
9172 /* 25952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9173 /* 25954 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9174 /* 25956 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9175 /* 25958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9176 /* 25961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9177 /* 25967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9178 /* 25973 */ GIR_RootConstrainSelectedInstOperands,
9179 /* 25974 */ // GIR_Coverage, 484,
9180 /* 25974 */ GIR_EraseRootFromParent_Done,
9181 /* 25975 */ // Label 509: @25975
9182 /* 25975 */ GIM_Reject,
9183 /* 25976 */ // Label 464: @25976
9184 /* 25976 */ GIM_Reject,
9185 /* 25977 */ // Label 451: @25977
9186 /* 25977 */ GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(26023), // Rule ID 2907 //
9187 /* 25982 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9188 /* 25985 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
9189 /* 25988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
9190 /* 25991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9191 /* 25995 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9192 /* 25999 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9193 /* 26003 */ // (or:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VORRd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
9194 /* 26003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
9195 /* 26006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9196 /* 26008 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9197 /* 26010 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9198 /* 26012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9199 /* 26015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9200 /* 26021 */ GIR_RootConstrainSelectedInstOperands,
9201 /* 26022 */ // GIR_Coverage, 2907,
9202 /* 26022 */ GIR_EraseRootFromParent_Done,
9203 /* 26023 */ // Label 510: @26023
9204 /* 26023 */ GIM_Reject,
9205 /* 26024 */ // Label 452: @26024
9206 /* 26024 */ GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(26141), // Rule ID 2020 //
9207 /* 26029 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9208 /* 26032 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1,
9209 /* 26035 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1,
9210 /* 26038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9211 /* 26042 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9212 /* 26046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9213 /* 26050 */ // (or:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9214 /* 26050 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9215 /* 26053 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9216 /* 26057 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9217 /* 26062 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9218 /* 26066 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9219 /* 26071 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9220 /* 26074 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9221 /* 26078 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9222 /* 26083 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9223 /* 26087 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9224 /* 26092 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9225 /* 26095 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
9226 /* 26099 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9227 /* 26104 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9228 /* 26107 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9229 /* 26110 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9230 /* 26113 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9231 /* 26119 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9232 /* 26125 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9233 /* 26127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9234 /* 26130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9235 /* 26132 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9236 /* 26135 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9237 /* 26140 */ // GIR_Coverage, 2020,
9238 /* 26140 */ GIR_EraseRootFromParent_Done,
9239 /* 26141 */ // Label 511: @26141
9240 /* 26141 */ GIM_Reject,
9241 /* 26142 */ // Label 453: @26142
9242 /* 26142 */ GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(26259), // Rule ID 2021 //
9243 /* 26147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9244 /* 26150 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1,
9245 /* 26153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1,
9246 /* 26156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9247 /* 26160 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9248 /* 26164 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9249 /* 26168 */ // (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9250 /* 26168 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9251 /* 26171 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9252 /* 26175 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9253 /* 26180 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9254 /* 26184 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9255 /* 26189 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9256 /* 26192 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9257 /* 26196 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9258 /* 26201 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9259 /* 26205 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9260 /* 26210 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9261 /* 26213 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
9262 /* 26217 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9263 /* 26222 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9264 /* 26225 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9265 /* 26228 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9266 /* 26231 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9267 /* 26237 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9268 /* 26243 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9269 /* 26245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9270 /* 26248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9271 /* 26250 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9272 /* 26253 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9273 /* 26258 */ // GIR_Coverage, 2021,
9274 /* 26258 */ GIR_EraseRootFromParent_Done,
9275 /* 26259 */ // Label 512: @26259
9276 /* 26259 */ GIM_Reject,
9277 /* 26260 */ // Label 454: @26260
9278 /* 26260 */ GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(26377), // Rule ID 2022 //
9279 /* 26265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9280 /* 26268 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1,
9281 /* 26271 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1,
9282 /* 26274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9283 /* 26278 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9284 /* 26282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9285 /* 26286 */ // (or:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9286 /* 26286 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9287 /* 26289 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9288 /* 26293 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9289 /* 26298 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9290 /* 26302 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9291 /* 26307 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9292 /* 26310 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9293 /* 26314 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9294 /* 26319 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9295 /* 26323 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9296 /* 26328 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9297 /* 26331 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
9298 /* 26335 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9299 /* 26340 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9300 /* 26343 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9301 /* 26346 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9302 /* 26349 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9303 /* 26355 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9304 /* 26361 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9305 /* 26363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9306 /* 26366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9307 /* 26368 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9308 /* 26371 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9309 /* 26376 */ // GIR_Coverage, 2022,
9310 /* 26376 */ GIR_EraseRootFromParent_Done,
9311 /* 26377 */ // Label 513: @26377
9312 /* 26377 */ GIM_Reject,
9313 /* 26378 */ // Label 455: @26378
9314 /* 26378 */ GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(26495), // Rule ID 2023 //
9315 /* 26383 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9316 /* 26386 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1,
9317 /* 26389 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1,
9318 /* 26392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9319 /* 26396 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9320 /* 26400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9321 /* 26404 */ // (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9322 /* 26404 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9323 /* 26407 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9324 /* 26411 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9325 /* 26416 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9326 /* 26420 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9327 /* 26425 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9328 /* 26428 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9329 /* 26432 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9330 /* 26437 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9331 /* 26441 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9332 /* 26446 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9333 /* 26449 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
9334 /* 26453 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9335 /* 26458 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9336 /* 26461 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9337 /* 26464 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9338 /* 26467 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9339 /* 26473 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9340 /* 26479 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9341 /* 26481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9342 /* 26484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9343 /* 26486 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9344 /* 26489 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9345 /* 26494 */ // GIR_Coverage, 2023,
9346 /* 26494 */ GIR_EraseRootFromParent_Done,
9347 /* 26495 */ // Label 514: @26495
9348 /* 26495 */ GIM_Reject,
9349 /* 26496 */ // Label 456: @26496
9350 /* 26496 */ GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(26542), // Rule ID 2905 //
9351 /* 26501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9352 /* 26504 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
9353 /* 26507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
9354 /* 26510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9355 /* 26514 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9356 /* 26518 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9357 /* 26522 */ // (or:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VORRd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
9358 /* 26522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
9359 /* 26525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9360 /* 26527 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9361 /* 26529 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9362 /* 26531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9363 /* 26534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9364 /* 26540 */ GIR_RootConstrainSelectedInstOperands,
9365 /* 26541 */ // GIR_Coverage, 2905,
9366 /* 26541 */ GIR_EraseRootFromParent_Done,
9367 /* 26542 */ // Label 515: @26542
9368 /* 26542 */ GIM_Reject,
9369 /* 26543 */ // Label 457: @26543
9370 /* 26543 */ GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(26656),
9371 /* 26548 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
9372 /* 26551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9373 /* 26554 */ GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(26594), // Rule ID 2908 //
9374 /* 26559 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9375 /* 26562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9376 /* 26566 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9377 /* 26570 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9378 /* 26574 */ // (or:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VORRq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
9379 /* 26574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9380 /* 26577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9381 /* 26579 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9382 /* 26581 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9383 /* 26583 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9384 /* 26586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9385 /* 26592 */ GIR_RootConstrainSelectedInstOperands,
9386 /* 26593 */ // GIR_Coverage, 2908,
9387 /* 26593 */ GIR_EraseRootFromParent_Done,
9388 /* 26594 */ // Label 517: @26594
9389 /* 26594 */ GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(26655), // Rule ID 3755 //
9390 /* 26599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9391 /* 26602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9392 /* 26606 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9393 /* 26610 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9394 /* 26614 */ // (or:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VORR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
9395 /* 26614 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9396 /* 26617 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9397 /* 26621 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9398 /* 26626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9399 /* 26629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9400 /* 26631 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9401 /* 26633 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9402 /* 26635 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9403 /* 26638 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9404 /* 26644 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9405 /* 26650 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9406 /* 26653 */ GIR_RootConstrainSelectedInstOperands,
9407 /* 26654 */ // GIR_Coverage, 3755,
9408 /* 26654 */ GIR_EraseRootFromParent_Done,
9409 /* 26655 */ // Label 518: @26655
9410 /* 26655 */ GIM_Reject,
9411 /* 26656 */ // Label 516: @26656
9412 /* 26656 */ GIM_Reject,
9413 /* 26657 */ // Label 458: @26657
9414 /* 26657 */ GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(26703), // Rule ID 2906 //
9415 /* 26662 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9416 /* 26665 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
9417 /* 26668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
9418 /* 26671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9419 /* 26675 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9420 /* 26679 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9421 /* 26683 */ // (or:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VORRd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
9422 /* 26683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
9423 /* 26686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9424 /* 26688 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9425 /* 26690 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9426 /* 26692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9427 /* 26695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9428 /* 26701 */ GIR_RootConstrainSelectedInstOperands,
9429 /* 26702 */ // GIR_Coverage, 2906,
9430 /* 26702 */ GIR_EraseRootFromParent_Done,
9431 /* 26703 */ // Label 519: @26703
9432 /* 26703 */ GIM_Reject,
9433 /* 26704 */ // Label 459: @26704
9434 /* 26704 */ GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(26817),
9435 /* 26709 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
9436 /* 26712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9437 /* 26715 */ GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(26755), // Rule ID 2909 //
9438 /* 26720 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9439 /* 26723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9440 /* 26727 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9441 /* 26731 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9442 /* 26735 */ // (or:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VORRq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
9443 /* 26735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9444 /* 26738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9445 /* 26740 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9446 /* 26742 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9447 /* 26744 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9448 /* 26747 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9449 /* 26753 */ GIR_RootConstrainSelectedInstOperands,
9450 /* 26754 */ // GIR_Coverage, 2909,
9451 /* 26754 */ GIR_EraseRootFromParent_Done,
9452 /* 26755 */ // Label 521: @26755
9453 /* 26755 */ GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(26816), // Rule ID 3759 //
9454 /* 26760 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9455 /* 26763 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9456 /* 26767 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9457 /* 26771 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9458 /* 26775 */ // (or:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VORR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
9459 /* 26775 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9460 /* 26778 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9461 /* 26782 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9462 /* 26787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9463 /* 26790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9464 /* 26792 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9465 /* 26794 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9466 /* 26796 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9467 /* 26799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9468 /* 26805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9469 /* 26811 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9470 /* 26814 */ GIR_RootConstrainSelectedInstOperands,
9471 /* 26815 */ // GIR_Coverage, 3759,
9472 /* 26815 */ GIR_EraseRootFromParent_Done,
9473 /* 26816 */ // Label 522: @26816
9474 /* 26816 */ GIM_Reject,
9475 /* 26817 */ // Label 520: @26817
9476 /* 26817 */ GIM_Reject,
9477 /* 26818 */ // Label 460: @26818
9478 /* 26818 */ GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(26864), // Rule ID 1299 //
9479 /* 26823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9480 /* 26826 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
9481 /* 26829 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
9482 /* 26832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9483 /* 26836 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9484 /* 26840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9485 /* 26844 */ // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
9486 /* 26844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
9487 /* 26847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9488 /* 26849 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9489 /* 26851 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9490 /* 26853 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9491 /* 26856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9492 /* 26862 */ GIR_RootConstrainSelectedInstOperands,
9493 /* 26863 */ // GIR_Coverage, 1299,
9494 /* 26863 */ GIR_EraseRootFromParent_Done,
9495 /* 26864 */ // Label 523: @26864
9496 /* 26864 */ GIM_Reject,
9497 /* 26865 */ // Label 461: @26865
9498 /* 26865 */ GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(26978),
9499 /* 26870 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
9500 /* 26873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9501 /* 26876 */ GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(26916), // Rule ID 1300 //
9502 /* 26881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9503 /* 26884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9504 /* 26888 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9505 /* 26892 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9506 /* 26896 */ // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
9507 /* 26896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9508 /* 26899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9509 /* 26901 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9510 /* 26903 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9511 /* 26905 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9512 /* 26908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9513 /* 26914 */ GIR_RootConstrainSelectedInstOperands,
9514 /* 26915 */ // GIR_Coverage, 1300,
9515 /* 26915 */ GIR_EraseRootFromParent_Done,
9516 /* 26916 */ // Label 525: @26916
9517 /* 26916 */ GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(26977), // Rule ID 3763 //
9518 /* 26921 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9519 /* 26924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9520 /* 26928 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9521 /* 26932 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9522 /* 26936 */ // (or:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VORR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
9523 /* 26936 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9524 /* 26939 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9525 /* 26943 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9526 /* 26948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9527 /* 26951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9528 /* 26953 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9529 /* 26955 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9530 /* 26957 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9531 /* 26960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9532 /* 26966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9533 /* 26972 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9534 /* 26975 */ GIR_RootConstrainSelectedInstOperands,
9535 /* 26976 */ // GIR_Coverage, 3763,
9536 /* 26976 */ GIR_EraseRootFromParent_Done,
9537 /* 26977 */ // Label 526: @26977
9538 /* 26977 */ GIM_Reject,
9539 /* 26978 */ // Label 524: @26978
9540 /* 26978 */ GIM_Reject,
9541 /* 26979 */ // Label 462: @26979
9542 /* 26979 */ GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(27092),
9543 /* 26984 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
9544 /* 26987 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9545 /* 26990 */ GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(27030), // Rule ID 2910 //
9546 /* 26995 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9547 /* 26998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9548 /* 27002 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9549 /* 27006 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9550 /* 27010 */ // (or:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VORRq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
9551 /* 27010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9552 /* 27013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9553 /* 27015 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9554 /* 27017 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9555 /* 27019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9556 /* 27022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9557 /* 27028 */ GIR_RootConstrainSelectedInstOperands,
9558 /* 27029 */ // GIR_Coverage, 2910,
9559 /* 27029 */ GIR_EraseRootFromParent_Done,
9560 /* 27030 */ // Label 528: @27030
9561 /* 27030 */ GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(27091), // Rule ID 3767 //
9562 /* 27035 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9563 /* 27038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9564 /* 27042 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9565 /* 27046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9566 /* 27050 */ // (or:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VORR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
9567 /* 27050 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9568 /* 27053 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9569 /* 27057 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9570 /* 27062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9571 /* 27065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9572 /* 27067 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9573 /* 27069 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9574 /* 27071 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9575 /* 27074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9576 /* 27080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9577 /* 27086 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9578 /* 27089 */ GIR_RootConstrainSelectedInstOperands,
9579 /* 27090 */ // GIR_Coverage, 3767,
9580 /* 27090 */ GIR_EraseRootFromParent_Done,
9581 /* 27091 */ // Label 529: @27091
9582 /* 27091 */ GIM_Reject,
9583 /* 27092 */ // Label 527: @27092
9584 /* 27092 */ GIM_Reject,
9585 /* 27093 */ // Label 463: @27093
9586 /* 27093 */ GIM_Reject,
9587 /* 27094 */ // Label 7: @27094
9588 /* 27094 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 543*/ GIMT_Encode4(28780),
9589 /* 27105 */ /*GILLT_s32*//*Label 530*/ GIMT_Encode4(27157),
9590 /* 27109 */ /*GILLT_s64*//*Label 531*/ GIMT_Encode4(27664),
9591 /* 27113 */ /*GILLT_v2s1*//*Label 532*/ GIMT_Encode4(27711),
9592 /* 27117 */ /*GILLT_v4s1*//*Label 533*/ GIMT_Encode4(27829),
9593 /* 27121 */ /*GILLT_v8s1*//*Label 534*/ GIMT_Encode4(27947),
9594 /* 27125 */ /*GILLT_v16s1*//*Label 535*/ GIMT_Encode4(28065),
9595 /* 27129 */ /*GILLT_v8s8*//*Label 536*/ GIMT_Encode4(28183),
9596 /* 27133 */ /*GILLT_v16s8*//*Label 537*/ GIMT_Encode4(28230),
9597 /* 27137 */ /*GILLT_v4s16*//*Label 538*/ GIMT_Encode4(28344),
9598 /* 27141 */ /*GILLT_v8s16*//*Label 539*/ GIMT_Encode4(28391),
9599 /* 27145 */ /*GILLT_v2s32*//*Label 540*/ GIMT_Encode4(28505),
9600 /* 27149 */ /*GILLT_v4s32*//*Label 541*/ GIMT_Encode4(28552),
9601 /* 27153 */ /*GILLT_v2s64*//*Label 542*/ GIMT_Encode4(28666),
9602 /* 27157 */ // Label 530: @27157
9603 /* 27157 */ GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(27663),
9604 /* 27162 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
9605 /* 27165 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9606 /* 27168 */ GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(27223), // Rule ID 5995 //
9607 /* 27173 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9608 /* 27176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9609 /* 27180 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 255,
9610 /* 27184 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9611 /* 27188 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9612 /* 27192 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
9613 /* 27196 */ // MIs[1] Operand 1
9614 /* 27196 */ // No operand predicates
9615 /* 27196 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9616 /* 27198 */ // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
9617 /* 27198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
9618 /* 27201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9619 /* 27203 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9620 /* 27206 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9621 /* 27209 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9622 /* 27215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9623 /* 27221 */ GIR_RootConstrainSelectedInstOperands,
9624 /* 27222 */ // GIR_Coverage, 5995,
9625 /* 27222 */ GIR_EraseRootFromParent_Done,
9626 /* 27223 */ // Label 545: @27223
9627 /* 27223 */ GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(27278), // Rule ID 498 //
9628 /* 27228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9629 /* 27231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9630 /* 27235 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9631 /* 27239 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9632 /* 27243 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
9633 /* 27247 */ // MIs[1] Operand 1
9634 /* 27247 */ // No operand predicates
9635 /* 27247 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9636 /* 27251 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9637 /* 27253 */ // (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
9638 /* 27253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
9639 /* 27256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9640 /* 27258 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9641 /* 27261 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9642 /* 27264 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9643 /* 27270 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9644 /* 27276 */ GIR_RootConstrainSelectedInstOperands,
9645 /* 27277 */ // GIR_Coverage, 498,
9646 /* 27277 */ GIR_EraseRootFromParent_Done,
9647 /* 27278 */ // Label 546: @27278
9648 /* 27278 */ GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(27322), // Rule ID 499 //
9649 /* 27283 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9650 /* 27286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9651 /* 27290 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9652 /* 27294 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9653 /* 27298 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
9654 /* 27298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNr),
9655 /* 27301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9656 /* 27303 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
9657 /* 27305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9658 /* 27308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9659 /* 27314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9660 /* 27320 */ GIR_RootConstrainSelectedInstOperands,
9661 /* 27321 */ // GIR_Coverage, 499,
9662 /* 27321 */ GIR_EraseRootFromParent_Done,
9663 /* 27322 */ // Label 547: @27322
9664 /* 27322 */ GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(27366), // Rule ID 164 //
9665 /* 27327 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
9666 /* 27330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9667 /* 27334 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9668 /* 27338 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9669 /* 27342 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
9670 /* 27342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNr),
9671 /* 27345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9672 /* 27347 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
9673 /* 27349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9674 /* 27352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9675 /* 27358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9676 /* 27364 */ GIR_RootConstrainSelectedInstOperands,
9677 /* 27365 */ // GIR_Coverage, 164,
9678 /* 27365 */ GIR_EraseRootFromParent_Done,
9679 /* 27366 */ // Label 548: @27366
9680 /* 27366 */ GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(27410), // Rule ID 323 //
9681 /* 27371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
9682 /* 27374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9683 /* 27378 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9684 /* 27382 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9685 /* 27386 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, -1:{ *:[i32] }) => (tMVN:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)
9686 /* 27386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMVN),
9687 /* 27389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9688 /* 27391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
9689 /* 27397 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9690 /* 27399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9691 /* 27402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9692 /* 27408 */ GIR_RootConstrainSelectedInstOperands,
9693 /* 27409 */ // GIR_Coverage, 323,
9694 /* 27409 */ GIR_EraseRootFromParent_Done,
9695 /* 27410 */ // Label 549: @27410
9696 /* 27410 */ GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(27467), // Rule ID 154 //
9697 /* 27415 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
9698 /* 27418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9699 /* 27422 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9700 /* 27426 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9701 /* 27430 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9702 /* 27434 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
9703 /* 27438 */ // MIs[1] Operand 1
9704 /* 27438 */ // No operand predicates
9705 /* 27438 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9706 /* 27440 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
9707 /* 27440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORri),
9708 /* 27443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9709 /* 27445 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9710 /* 27447 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9711 /* 27450 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9712 /* 27453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9713 /* 27459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9714 /* 27465 */ GIR_RootConstrainSelectedInstOperands,
9715 /* 27466 */ // GIR_Coverage, 154,
9716 /* 27466 */ GIR_EraseRootFromParent_Done,
9717 /* 27467 */ // Label 550: @27467
9718 /* 27467 */ GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(27524), // Rule ID 486 //
9719 /* 27472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9720 /* 27475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9721 /* 27479 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9722 /* 27483 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9723 /* 27487 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9724 /* 27491 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
9725 /* 27495 */ // MIs[1] Operand 1
9726 /* 27495 */ // No operand predicates
9727 /* 27495 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9728 /* 27497 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
9729 /* 27497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORri),
9730 /* 27500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9731 /* 27502 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9732 /* 27504 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9733 /* 27507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9734 /* 27510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9735 /* 27516 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9736 /* 27522 */ GIR_RootConstrainSelectedInstOperands,
9737 /* 27523 */ // GIR_Coverage, 486,
9738 /* 27523 */ GIR_EraseRootFromParent_Done,
9739 /* 27524 */ // Label 551: @27524
9740 /* 27524 */ GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(27570), // Rule ID 155 //
9741 /* 27529 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
9742 /* 27532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9743 /* 27536 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9744 /* 27540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9745 /* 27544 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
9746 /* 27544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORrr),
9747 /* 27547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9748 /* 27549 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9749 /* 27551 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9750 /* 27553 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9751 /* 27556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9752 /* 27562 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9753 /* 27568 */ GIR_RootConstrainSelectedInstOperands,
9754 /* 27569 */ // GIR_Coverage, 155,
9755 /* 27569 */ GIR_EraseRootFromParent_Done,
9756 /* 27570 */ // Label 552: @27570
9757 /* 27570 */ GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(27616), // Rule ID 316 //
9758 /* 27575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
9759 /* 27578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9760 /* 27582 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9761 /* 27586 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9762 /* 27590 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tEOR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
9763 /* 27590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tEOR),
9764 /* 27593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
9765 /* 27595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
9766 /* 27601 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9767 /* 27603 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9768 /* 27605 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9769 /* 27608 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9770 /* 27614 */ GIR_RootConstrainSelectedInstOperands,
9771 /* 27615 */ // GIR_Coverage, 316,
9772 /* 27615 */ GIR_EraseRootFromParent_Done,
9773 /* 27616 */ // Label 553: @27616
9774 /* 27616 */ GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(27662), // Rule ID 487 //
9775 /* 27621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9776 /* 27624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9777 /* 27628 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9778 /* 27632 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9779 /* 27636 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
9780 /* 27636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9781 /* 27639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9782 /* 27641 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9783 /* 27643 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9784 /* 27645 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9785 /* 27648 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9786 /* 27654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9787 /* 27660 */ GIR_RootConstrainSelectedInstOperands,
9788 /* 27661 */ // GIR_Coverage, 487,
9789 /* 27661 */ GIR_EraseRootFromParent_Done,
9790 /* 27662 */ // Label 554: @27662
9791 /* 27662 */ GIM_Reject,
9792 /* 27663 */ // Label 544: @27663
9793 /* 27663 */ GIM_Reject,
9794 /* 27664 */ // Label 531: @27664
9795 /* 27664 */ GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(27710), // Rule ID 2913 //
9796 /* 27669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9797 /* 27672 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
9798 /* 27675 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
9799 /* 27678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9800 /* 27682 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9801 /* 27686 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9802 /* 27690 */ // (xor:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VEORd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
9803 /* 27690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
9804 /* 27693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9805 /* 27695 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9806 /* 27697 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9807 /* 27699 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9808 /* 27702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9809 /* 27708 */ GIR_RootConstrainSelectedInstOperands,
9810 /* 27709 */ // GIR_Coverage, 2913,
9811 /* 27709 */ GIR_EraseRootFromParent_Done,
9812 /* 27710 */ // Label 555: @27710
9813 /* 27710 */ GIM_Reject,
9814 /* 27711 */ // Label 532: @27711
9815 /* 27711 */ GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(27828), // Rule ID 2016 //
9816 /* 27716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9817 /* 27719 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1,
9818 /* 27722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1,
9819 /* 27725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9820 /* 27729 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9821 /* 27733 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9822 /* 27737 */ // (xor:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9823 /* 27737 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9824 /* 27740 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9825 /* 27744 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9826 /* 27749 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9827 /* 27753 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9828 /* 27758 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9829 /* 27761 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9830 /* 27765 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9831 /* 27770 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9832 /* 27774 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9833 /* 27779 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9834 /* 27782 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9835 /* 27786 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9836 /* 27791 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9837 /* 27794 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9838 /* 27797 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9839 /* 27800 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9840 /* 27806 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9841 /* 27812 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9842 /* 27814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9843 /* 27817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9844 /* 27819 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9845 /* 27822 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9846 /* 27827 */ // GIR_Coverage, 2016,
9847 /* 27827 */ GIR_EraseRootFromParent_Done,
9848 /* 27828 */ // Label 556: @27828
9849 /* 27828 */ GIM_Reject,
9850 /* 27829 */ // Label 533: @27829
9851 /* 27829 */ GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(27946), // Rule ID 2017 //
9852 /* 27834 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9853 /* 27837 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1,
9854 /* 27840 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1,
9855 /* 27843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9856 /* 27847 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9857 /* 27851 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9858 /* 27855 */ // (xor:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9859 /* 27855 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9860 /* 27858 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9861 /* 27862 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9862 /* 27867 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9863 /* 27871 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9864 /* 27876 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9865 /* 27879 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9866 /* 27883 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9867 /* 27888 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9868 /* 27892 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9869 /* 27897 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9870 /* 27900 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9871 /* 27904 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9872 /* 27909 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9873 /* 27912 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9874 /* 27915 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9875 /* 27918 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9876 /* 27924 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9877 /* 27930 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9878 /* 27932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9879 /* 27935 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9880 /* 27937 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9881 /* 27940 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9882 /* 27945 */ // GIR_Coverage, 2017,
9883 /* 27945 */ GIR_EraseRootFromParent_Done,
9884 /* 27946 */ // Label 557: @27946
9885 /* 27946 */ GIM_Reject,
9886 /* 27947 */ // Label 534: @27947
9887 /* 27947 */ GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(28064), // Rule ID 2018 //
9888 /* 27952 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9889 /* 27955 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1,
9890 /* 27958 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1,
9891 /* 27961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9892 /* 27965 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9893 /* 27969 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9894 /* 27973 */ // (xor:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9895 /* 27973 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9896 /* 27976 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9897 /* 27980 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9898 /* 27985 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9899 /* 27989 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9900 /* 27994 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9901 /* 27997 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9902 /* 28001 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9903 /* 28006 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9904 /* 28010 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9905 /* 28015 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9906 /* 28018 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9907 /* 28022 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9908 /* 28027 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9909 /* 28030 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9910 /* 28033 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9911 /* 28036 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9912 /* 28042 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9913 /* 28048 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9914 /* 28050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9915 /* 28053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9916 /* 28055 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9917 /* 28058 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9918 /* 28063 */ // GIR_Coverage, 2018,
9919 /* 28063 */ GIR_EraseRootFromParent_Done,
9920 /* 28064 */ // Label 558: @28064
9921 /* 28064 */ GIM_Reject,
9922 /* 28065 */ // Label 535: @28065
9923 /* 28065 */ GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(28182), // Rule ID 2019 //
9924 /* 28070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9925 /* 28073 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1,
9926 /* 28076 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1,
9927 /* 28079 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9928 /* 28083 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9929 /* 28087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9930 /* 28091 */ // (xor:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9931 /* 28091 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9932 /* 28094 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9933 /* 28098 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9934 /* 28103 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9935 /* 28107 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9936 /* 28112 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9937 /* 28115 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9938 /* 28119 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9939 /* 28124 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9940 /* 28128 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9941 /* 28133 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9942 /* 28136 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9943 /* 28140 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9944 /* 28145 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9945 /* 28148 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9946 /* 28151 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9947 /* 28154 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9948 /* 28160 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9949 /* 28166 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9950 /* 28168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9951 /* 28171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9952 /* 28173 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9953 /* 28176 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9954 /* 28181 */ // GIR_Coverage, 2019,
9955 /* 28181 */ GIR_EraseRootFromParent_Done,
9956 /* 28182 */ // Label 559: @28182
9957 /* 28182 */ GIM_Reject,
9958 /* 28183 */ // Label 536: @28183
9959 /* 28183 */ GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(28229), // Rule ID 2911 //
9960 /* 28188 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9961 /* 28191 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
9962 /* 28194 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
9963 /* 28197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9964 /* 28201 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9965 /* 28205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9966 /* 28209 */ // (xor:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VEORd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
9967 /* 28209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
9968 /* 28212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9969 /* 28214 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9970 /* 28216 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9971 /* 28218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9972 /* 28221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9973 /* 28227 */ GIR_RootConstrainSelectedInstOperands,
9974 /* 28228 */ // GIR_Coverage, 2911,
9975 /* 28228 */ GIR_EraseRootFromParent_Done,
9976 /* 28229 */ // Label 560: @28229
9977 /* 28229 */ GIM_Reject,
9978 /* 28230 */ // Label 537: @28230
9979 /* 28230 */ GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(28343),
9980 /* 28235 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
9981 /* 28238 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9982 /* 28241 */ GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(28281), // Rule ID 2914 //
9983 /* 28246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9984 /* 28249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9985 /* 28253 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9986 /* 28257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9987 /* 28261 */ // (xor:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VEORq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
9988 /* 28261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
9989 /* 28264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9990 /* 28266 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9991 /* 28268 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9992 /* 28270 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9993 /* 28273 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9994 /* 28279 */ GIR_RootConstrainSelectedInstOperands,
9995 /* 28280 */ // GIR_Coverage, 2914,
9996 /* 28280 */ GIR_EraseRootFromParent_Done,
9997 /* 28281 */ // Label 562: @28281
9998 /* 28281 */ GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(28342), // Rule ID 3769 //
9999 /* 28286 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10000 /* 28289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10001 /* 28293 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10002 /* 28297 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10003 /* 28301 */ // (xor:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VEOR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10004 /* 28301 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10005 /* 28304 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10006 /* 28308 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10007 /* 28313 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
10008 /* 28316 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10009 /* 28318 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10010 /* 28320 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10011 /* 28322 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10012 /* 28325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10013 /* 28331 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10014 /* 28337 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10015 /* 28340 */ GIR_RootConstrainSelectedInstOperands,
10016 /* 28341 */ // GIR_Coverage, 3769,
10017 /* 28341 */ GIR_EraseRootFromParent_Done,
10018 /* 28342 */ // Label 563: @28342
10019 /* 28342 */ GIM_Reject,
10020 /* 28343 */ // Label 561: @28343
10021 /* 28343 */ GIM_Reject,
10022 /* 28344 */ // Label 538: @28344
10023 /* 28344 */ GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(28390), // Rule ID 2912 //
10024 /* 28349 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10025 /* 28352 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
10026 /* 28355 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
10027 /* 28358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10028 /* 28362 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10029 /* 28366 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10030 /* 28370 */ // (xor:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VEORd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
10031 /* 28370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
10032 /* 28373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10033 /* 28375 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
10034 /* 28377 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
10035 /* 28379 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10036 /* 28382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10037 /* 28388 */ GIR_RootConstrainSelectedInstOperands,
10038 /* 28389 */ // GIR_Coverage, 2912,
10039 /* 28389 */ GIR_EraseRootFromParent_Done,
10040 /* 28390 */ // Label 564: @28390
10041 /* 28390 */ GIM_Reject,
10042 /* 28391 */ // Label 539: @28391
10043 /* 28391 */ GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(28504),
10044 /* 28396 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10045 /* 28399 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10046 /* 28402 */ GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(28442), // Rule ID 2915 //
10047 /* 28407 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10048 /* 28410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10049 /* 28414 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10050 /* 28418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10051 /* 28422 */ // (xor:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VEORq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
10052 /* 28422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
10053 /* 28425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10054 /* 28427 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
10055 /* 28429 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
10056 /* 28431 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10057 /* 28434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10058 /* 28440 */ GIR_RootConstrainSelectedInstOperands,
10059 /* 28441 */ // GIR_Coverage, 2915,
10060 /* 28441 */ GIR_EraseRootFromParent_Done,
10061 /* 28442 */ // Label 566: @28442
10062 /* 28442 */ GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(28503), // Rule ID 3773 //
10063 /* 28447 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10064 /* 28450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10065 /* 28454 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10066 /* 28458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10067 /* 28462 */ // (xor:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VEOR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10068 /* 28462 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10069 /* 28465 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10070 /* 28469 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10071 /* 28474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
10072 /* 28477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10073 /* 28479 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10074 /* 28481 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10075 /* 28483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10076 /* 28486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10077 /* 28492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10078 /* 28498 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10079 /* 28501 */ GIR_RootConstrainSelectedInstOperands,
10080 /* 28502 */ // GIR_Coverage, 3773,
10081 /* 28502 */ GIR_EraseRootFromParent_Done,
10082 /* 28503 */ // Label 567: @28503
10083 /* 28503 */ GIM_Reject,
10084 /* 28504 */ // Label 565: @28504
10085 /* 28504 */ GIM_Reject,
10086 /* 28505 */ // Label 540: @28505
10087 /* 28505 */ GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(28551), // Rule ID 1297 //
10088 /* 28510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10089 /* 28513 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
10090 /* 28516 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
10091 /* 28519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10092 /* 28523 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10093 /* 28527 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10094 /* 28531 */ // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
10095 /* 28531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
10096 /* 28534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10097 /* 28536 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10098 /* 28538 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10099 /* 28540 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10100 /* 28543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10101 /* 28549 */ GIR_RootConstrainSelectedInstOperands,
10102 /* 28550 */ // GIR_Coverage, 1297,
10103 /* 28550 */ GIR_EraseRootFromParent_Done,
10104 /* 28551 */ // Label 568: @28551
10105 /* 28551 */ GIM_Reject,
10106 /* 28552 */ // Label 541: @28552
10107 /* 28552 */ GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(28665),
10108 /* 28557 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10109 /* 28560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10110 /* 28563 */ GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(28603), // Rule ID 1298 //
10111 /* 28568 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10112 /* 28571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10113 /* 28575 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10114 /* 28579 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10115 /* 28583 */ // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
10116 /* 28583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
10117 /* 28586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10118 /* 28588 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10119 /* 28590 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10120 /* 28592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10121 /* 28595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10122 /* 28601 */ GIR_RootConstrainSelectedInstOperands,
10123 /* 28602 */ // GIR_Coverage, 1298,
10124 /* 28602 */ GIR_EraseRootFromParent_Done,
10125 /* 28603 */ // Label 570: @28603
10126 /* 28603 */ GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(28664), // Rule ID 3777 //
10127 /* 28608 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10128 /* 28611 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10129 /* 28615 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10130 /* 28619 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10131 /* 28623 */ // (xor:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VEOR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10132 /* 28623 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10133 /* 28626 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10134 /* 28630 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10135 /* 28635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
10136 /* 28638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10137 /* 28640 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10138 /* 28642 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10139 /* 28644 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10140 /* 28647 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10141 /* 28653 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10142 /* 28659 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10143 /* 28662 */ GIR_RootConstrainSelectedInstOperands,
10144 /* 28663 */ // GIR_Coverage, 3777,
10145 /* 28663 */ GIR_EraseRootFromParent_Done,
10146 /* 28664 */ // Label 571: @28664
10147 /* 28664 */ GIM_Reject,
10148 /* 28665 */ // Label 569: @28665
10149 /* 28665 */ GIM_Reject,
10150 /* 28666 */ // Label 542: @28666
10151 /* 28666 */ GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(28779),
10152 /* 28671 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
10153 /* 28674 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
10154 /* 28677 */ GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(28717), // Rule ID 2916 //
10155 /* 28682 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10156 /* 28685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10157 /* 28689 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10158 /* 28693 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10159 /* 28697 */ // (xor:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VEORq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
10160 /* 28697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
10161 /* 28700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10162 /* 28702 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
10163 /* 28704 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
10164 /* 28706 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10165 /* 28709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10166 /* 28715 */ GIR_RootConstrainSelectedInstOperands,
10167 /* 28716 */ // GIR_Coverage, 2916,
10168 /* 28716 */ GIR_EraseRootFromParent_Done,
10169 /* 28717 */ // Label 573: @28717
10170 /* 28717 */ GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(28778), // Rule ID 3781 //
10171 /* 28722 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10172 /* 28725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10173 /* 28729 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10174 /* 28733 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10175 /* 28737 */ // (xor:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VEOR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
10176 /* 28737 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10177 /* 28740 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10178 /* 28744 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10179 /* 28749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
10180 /* 28752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10181 /* 28754 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10182 /* 28756 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10183 /* 28758 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10184 /* 28761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10185 /* 28767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10186 /* 28773 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10187 /* 28776 */ GIR_RootConstrainSelectedInstOperands,
10188 /* 28777 */ // GIR_Coverage, 3781,
10189 /* 28777 */ GIR_EraseRootFromParent_Done,
10190 /* 28778 */ // Label 574: @28778
10191 /* 28778 */ GIM_Reject,
10192 /* 28779 */ // Label 572: @28779
10193 /* 28779 */ GIM_Reject,
10194 /* 28780 */ // Label 543: @28780
10195 /* 28780 */ GIM_Reject,
10196 /* 28781 */ // Label 8: @28781
10197 /* 28781 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 581*/ GIMT_Encode4(29299),
10198 /* 28792 */ /*GILLT_v8s8*//*Label 575*/ GIMT_Encode4(28816),
10199 /* 28796 */ /*GILLT_v16s8*//*Label 576*/ GIMT_Encode4(28863),
10200 /* 28800 */ /*GILLT_v4s16*//*Label 577*/ GIMT_Encode4(28977),
10201 /* 28804 */ /*GILLT_v8s16*//*Label 578*/ GIMT_Encode4(29024),
10202 /* 28808 */ /*GILLT_v2s32*//*Label 579*/ GIMT_Encode4(29138),
10203 /* 28812 */ /*GILLT_v4s32*//*Label 580*/ GIMT_Encode4(29185),
10204 /* 28816 */ // Label 575: @28816
10205 /* 28816 */ GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(28862), // Rule ID 1323 //
10206 /* 28821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10207 /* 28824 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
10208 /* 28827 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
10209 /* 28830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10210 /* 28834 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10211 /* 28838 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10212 /* 28842 */ // (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
10213 /* 28842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i8),
10214 /* 28845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10215 /* 28847 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10216 /* 28849 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10217 /* 28851 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10218 /* 28854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10219 /* 28860 */ GIR_RootConstrainSelectedInstOperands,
10220 /* 28861 */ // GIR_Coverage, 1323,
10221 /* 28861 */ GIR_EraseRootFromParent_Done,
10222 /* 28862 */ // Label 582: @28862
10223 /* 28862 */ GIM_Reject,
10224 /* 28863 */ // Label 576: @28863
10225 /* 28863 */ GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(28976),
10226 /* 28868 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10227 /* 28871 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10228 /* 28874 */ GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(28914), // Rule ID 1324 //
10229 /* 28879 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10230 /* 28882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10231 /* 28886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10232 /* 28890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10233 /* 28894 */ // (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
10234 /* 28894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv16i8),
10235 /* 28897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10236 /* 28899 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10237 /* 28901 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10238 /* 28903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10239 /* 28906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10240 /* 28912 */ GIR_RootConstrainSelectedInstOperands,
10241 /* 28913 */ // GIR_Coverage, 1324,
10242 /* 28913 */ GIR_EraseRootFromParent_Done,
10243 /* 28914 */ // Label 584: @28914
10244 /* 28914 */ GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(28975), // Rule ID 3932 //
10245 /* 28919 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10246 /* 28922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10247 /* 28926 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10248 /* 28930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10249 /* 28934 */ // (abds:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10250 /* 28934 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10251 /* 28937 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10252 /* 28941 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10253 /* 28946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8),
10254 /* 28949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10255 /* 28951 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10256 /* 28953 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10257 /* 28955 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10258 /* 28958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10259 /* 28964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10260 /* 28970 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10261 /* 28973 */ GIR_RootConstrainSelectedInstOperands,
10262 /* 28974 */ // GIR_Coverage, 3932,
10263 /* 28974 */ GIR_EraseRootFromParent_Done,
10264 /* 28975 */ // Label 585: @28975
10265 /* 28975 */ GIM_Reject,
10266 /* 28976 */ // Label 583: @28976
10267 /* 28976 */ GIM_Reject,
10268 /* 28977 */ // Label 577: @28977
10269 /* 28977 */ GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(29023), // Rule ID 1319 //
10270 /* 28982 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10271 /* 28985 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
10272 /* 28988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
10273 /* 28991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10274 /* 28995 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10275 /* 28999 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10276 /* 29003 */ // (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
10277 /* 29003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i16),
10278 /* 29006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10279 /* 29008 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10280 /* 29010 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10281 /* 29012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10282 /* 29015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10283 /* 29021 */ GIR_RootConstrainSelectedInstOperands,
10284 /* 29022 */ // GIR_Coverage, 1319,
10285 /* 29022 */ GIR_EraseRootFromParent_Done,
10286 /* 29023 */ // Label 586: @29023
10287 /* 29023 */ GIM_Reject,
10288 /* 29024 */ // Label 578: @29024
10289 /* 29024 */ GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(29137),
10290 /* 29029 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10291 /* 29032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10292 /* 29035 */ GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(29075), // Rule ID 1321 //
10293 /* 29040 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10294 /* 29043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10295 /* 29047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10296 /* 29051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10297 /* 29055 */ // (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
10298 /* 29055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i16),
10299 /* 29058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10300 /* 29060 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10301 /* 29062 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10302 /* 29064 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10303 /* 29067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10304 /* 29073 */ GIR_RootConstrainSelectedInstOperands,
10305 /* 29074 */ // GIR_Coverage, 1321,
10306 /* 29074 */ GIR_EraseRootFromParent_Done,
10307 /* 29075 */ // Label 588: @29075
10308 /* 29075 */ GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(29136), // Rule ID 3935 //
10309 /* 29080 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10310 /* 29083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10311 /* 29087 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10312 /* 29091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10313 /* 29095 */ // (abds:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10314 /* 29095 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10315 /* 29098 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10316 /* 29102 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10317 /* 29107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16),
10318 /* 29110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10319 /* 29112 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10320 /* 29114 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10321 /* 29116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10322 /* 29119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10323 /* 29125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10324 /* 29131 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10325 /* 29134 */ GIR_RootConstrainSelectedInstOperands,
10326 /* 29135 */ // GIR_Coverage, 3935,
10327 /* 29135 */ GIR_EraseRootFromParent_Done,
10328 /* 29136 */ // Label 589: @29136
10329 /* 29136 */ GIM_Reject,
10330 /* 29137 */ // Label 587: @29137
10331 /* 29137 */ GIM_Reject,
10332 /* 29138 */ // Label 579: @29138
10333 /* 29138 */ GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(29184), // Rule ID 1320 //
10334 /* 29143 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10335 /* 29146 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
10336 /* 29149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
10337 /* 29152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10338 /* 29156 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10339 /* 29160 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10340 /* 29164 */ // (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
10341 /* 29164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv2i32),
10342 /* 29167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10343 /* 29169 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10344 /* 29171 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10345 /* 29173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10346 /* 29176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10347 /* 29182 */ GIR_RootConstrainSelectedInstOperands,
10348 /* 29183 */ // GIR_Coverage, 1320,
10349 /* 29183 */ GIR_EraseRootFromParent_Done,
10350 /* 29184 */ // Label 590: @29184
10351 /* 29184 */ GIM_Reject,
10352 /* 29185 */ // Label 580: @29185
10353 /* 29185 */ GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(29298),
10354 /* 29190 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10355 /* 29193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10356 /* 29196 */ GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(29236), // Rule ID 1322 //
10357 /* 29201 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10358 /* 29204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10359 /* 29208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10360 /* 29212 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10361 /* 29216 */ // (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
10362 /* 29216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i32),
10363 /* 29219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10364 /* 29221 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10365 /* 29223 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10366 /* 29225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10367 /* 29228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10368 /* 29234 */ GIR_RootConstrainSelectedInstOperands,
10369 /* 29235 */ // GIR_Coverage, 1322,
10370 /* 29235 */ GIR_EraseRootFromParent_Done,
10371 /* 29236 */ // Label 592: @29236
10372 /* 29236 */ GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(29297), // Rule ID 3939 //
10373 /* 29241 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10374 /* 29244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10375 /* 29248 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10376 /* 29252 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10377 /* 29256 */ // (abds:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10378 /* 29256 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10379 /* 29259 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10380 /* 29263 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10381 /* 29268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32),
10382 /* 29271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10383 /* 29273 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10384 /* 29275 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10385 /* 29277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10386 /* 29280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10387 /* 29286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10388 /* 29292 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10389 /* 29295 */ GIR_RootConstrainSelectedInstOperands,
10390 /* 29296 */ // GIR_Coverage, 3939,
10391 /* 29296 */ GIR_EraseRootFromParent_Done,
10392 /* 29297 */ // Label 593: @29297
10393 /* 29297 */ GIM_Reject,
10394 /* 29298 */ // Label 591: @29298
10395 /* 29298 */ GIM_Reject,
10396 /* 29299 */ // Label 581: @29299
10397 /* 29299 */ GIM_Reject,
10398 /* 29300 */ // Label 9: @29300
10399 /* 29300 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 600*/ GIMT_Encode4(29818),
10400 /* 29311 */ /*GILLT_v8s8*//*Label 594*/ GIMT_Encode4(29335),
10401 /* 29315 */ /*GILLT_v16s8*//*Label 595*/ GIMT_Encode4(29382),
10402 /* 29319 */ /*GILLT_v4s16*//*Label 596*/ GIMT_Encode4(29496),
10403 /* 29323 */ /*GILLT_v8s16*//*Label 597*/ GIMT_Encode4(29543),
10404 /* 29327 */ /*GILLT_v2s32*//*Label 598*/ GIMT_Encode4(29657),
10405 /* 29331 */ /*GILLT_v4s32*//*Label 599*/ GIMT_Encode4(29704),
10406 /* 29335 */ // Label 594: @29335
10407 /* 29335 */ GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(29381), // Rule ID 1329 //
10408 /* 29340 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10409 /* 29343 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
10410 /* 29346 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
10411 /* 29349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10412 /* 29353 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10413 /* 29357 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10414 /* 29361 */ // (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
10415 /* 29361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i8),
10416 /* 29364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10417 /* 29366 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10418 /* 29368 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10419 /* 29370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10420 /* 29373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10421 /* 29379 */ GIR_RootConstrainSelectedInstOperands,
10422 /* 29380 */ // GIR_Coverage, 1329,
10423 /* 29380 */ GIR_EraseRootFromParent_Done,
10424 /* 29381 */ // Label 601: @29381
10425 /* 29381 */ GIM_Reject,
10426 /* 29382 */ // Label 595: @29382
10427 /* 29382 */ GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(29495),
10428 /* 29387 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10429 /* 29390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10430 /* 29393 */ GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(29433), // Rule ID 1330 //
10431 /* 29398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10432 /* 29401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10433 /* 29405 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10434 /* 29409 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10435 /* 29413 */ // (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
10436 /* 29413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv16i8),
10437 /* 29416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10438 /* 29418 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10439 /* 29420 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10440 /* 29422 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10441 /* 29425 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10442 /* 29431 */ GIR_RootConstrainSelectedInstOperands,
10443 /* 29432 */ // GIR_Coverage, 1330,
10444 /* 29432 */ GIR_EraseRootFromParent_Done,
10445 /* 29433 */ // Label 603: @29433
10446 /* 29433 */ GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(29494), // Rule ID 3943 //
10447 /* 29438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10448 /* 29441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10449 /* 29445 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10450 /* 29449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10451 /* 29453 */ // (abdu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10452 /* 29453 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10453 /* 29456 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10454 /* 29460 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10455 /* 29465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8),
10456 /* 29468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10457 /* 29470 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10458 /* 29472 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10459 /* 29474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10460 /* 29477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10461 /* 29483 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10462 /* 29489 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10463 /* 29492 */ GIR_RootConstrainSelectedInstOperands,
10464 /* 29493 */ // GIR_Coverage, 3943,
10465 /* 29493 */ GIR_EraseRootFromParent_Done,
10466 /* 29494 */ // Label 604: @29494
10467 /* 29494 */ GIM_Reject,
10468 /* 29495 */ // Label 602: @29495
10469 /* 29495 */ GIM_Reject,
10470 /* 29496 */ // Label 596: @29496
10471 /* 29496 */ GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(29542), // Rule ID 1325 //
10472 /* 29501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10473 /* 29504 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
10474 /* 29507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
10475 /* 29510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10476 /* 29514 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10477 /* 29518 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10478 /* 29522 */ // (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
10479 /* 29522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i16),
10480 /* 29525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10481 /* 29527 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10482 /* 29529 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10483 /* 29531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10484 /* 29534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10485 /* 29540 */ GIR_RootConstrainSelectedInstOperands,
10486 /* 29541 */ // GIR_Coverage, 1325,
10487 /* 29541 */ GIR_EraseRootFromParent_Done,
10488 /* 29542 */ // Label 605: @29542
10489 /* 29542 */ GIM_Reject,
10490 /* 29543 */ // Label 597: @29543
10491 /* 29543 */ GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(29656),
10492 /* 29548 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10493 /* 29551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10494 /* 29554 */ GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(29594), // Rule ID 1327 //
10495 /* 29559 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10496 /* 29562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10497 /* 29566 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10498 /* 29570 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10499 /* 29574 */ // (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
10500 /* 29574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i16),
10501 /* 29577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10502 /* 29579 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10503 /* 29581 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10504 /* 29583 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10505 /* 29586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10506 /* 29592 */ GIR_RootConstrainSelectedInstOperands,
10507 /* 29593 */ // GIR_Coverage, 1327,
10508 /* 29593 */ GIR_EraseRootFromParent_Done,
10509 /* 29594 */ // Label 607: @29594
10510 /* 29594 */ GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(29655), // Rule ID 3947 //
10511 /* 29599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10512 /* 29602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10513 /* 29606 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10514 /* 29610 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10515 /* 29614 */ // (abdu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10516 /* 29614 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10517 /* 29617 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10518 /* 29621 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10519 /* 29626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16),
10520 /* 29629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10521 /* 29631 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10522 /* 29633 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10523 /* 29635 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10524 /* 29638 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10525 /* 29644 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10526 /* 29650 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10527 /* 29653 */ GIR_RootConstrainSelectedInstOperands,
10528 /* 29654 */ // GIR_Coverage, 3947,
10529 /* 29654 */ GIR_EraseRootFromParent_Done,
10530 /* 29655 */ // Label 608: @29655
10531 /* 29655 */ GIM_Reject,
10532 /* 29656 */ // Label 606: @29656
10533 /* 29656 */ GIM_Reject,
10534 /* 29657 */ // Label 598: @29657
10535 /* 29657 */ GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(29703), // Rule ID 1326 //
10536 /* 29662 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10537 /* 29665 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
10538 /* 29668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
10539 /* 29671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10540 /* 29675 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10541 /* 29679 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10542 /* 29683 */ // (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
10543 /* 29683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv2i32),
10544 /* 29686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10545 /* 29688 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10546 /* 29690 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10547 /* 29692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10548 /* 29695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10549 /* 29701 */ GIR_RootConstrainSelectedInstOperands,
10550 /* 29702 */ // GIR_Coverage, 1326,
10551 /* 29702 */ GIR_EraseRootFromParent_Done,
10552 /* 29703 */ // Label 609: @29703
10553 /* 29703 */ GIM_Reject,
10554 /* 29704 */ // Label 599: @29704
10555 /* 29704 */ GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(29817),
10556 /* 29709 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10557 /* 29712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10558 /* 29715 */ GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(29755), // Rule ID 1328 //
10559 /* 29720 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10560 /* 29723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10561 /* 29727 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10562 /* 29731 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10563 /* 29735 */ // (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
10564 /* 29735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i32),
10565 /* 29738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10566 /* 29740 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10567 /* 29742 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10568 /* 29744 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10569 /* 29747 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10570 /* 29753 */ GIR_RootConstrainSelectedInstOperands,
10571 /* 29754 */ // GIR_Coverage, 1328,
10572 /* 29754 */ GIR_EraseRootFromParent_Done,
10573 /* 29755 */ // Label 611: @29755
10574 /* 29755 */ GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(29816), // Rule ID 3951 //
10575 /* 29760 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10576 /* 29763 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10577 /* 29767 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10578 /* 29771 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10579 /* 29775 */ // (abdu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10580 /* 29775 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10581 /* 29778 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10582 /* 29782 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10583 /* 29787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32),
10584 /* 29790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10585 /* 29792 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10586 /* 29794 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10587 /* 29796 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10588 /* 29799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10589 /* 29805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10590 /* 29811 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10591 /* 29814 */ GIR_RootConstrainSelectedInstOperands,
10592 /* 29815 */ // GIR_Coverage, 3951,
10593 /* 29815 */ GIR_EraseRootFromParent_Done,
10594 /* 29816 */ // Label 612: @29816
10595 /* 29816 */ GIM_Reject,
10596 /* 29817 */ // Label 610: @29817
10597 /* 29817 */ GIM_Reject,
10598 /* 29818 */ // Label 600: @29818
10599 /* 29818 */ GIM_Reject,
10600 /* 29819 */ // Label 10: @29819
10601 /* 29819 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 616*/ GIMT_Encode4(30045),
10602 /* 29830 */ /*GILLT_v16s8*//*Label 613*/ GIMT_Encode4(29850), GIMT_Encode4(0),
10603 /* 29838 */ /*GILLT_v8s16*//*Label 614*/ GIMT_Encode4(29915), GIMT_Encode4(0),
10604 /* 29846 */ /*GILLT_v4s32*//*Label 615*/ GIMT_Encode4(29980),
10605 /* 29850 */ // Label 613: @29850
10606 /* 29850 */ GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(29914), // Rule ID 3991 //
10607 /* 29855 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10608 /* 29858 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10609 /* 29861 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10610 /* 29865 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10611 /* 29869 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10612 /* 29873 */ // (avgflooru:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10613 /* 29873 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10614 /* 29876 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10615 /* 29880 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10616 /* 29885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8),
10617 /* 29888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10618 /* 29890 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10619 /* 29892 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10620 /* 29894 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10621 /* 29897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10622 /* 29903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10623 /* 29909 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10624 /* 29912 */ GIR_RootConstrainSelectedInstOperands,
10625 /* 29913 */ // GIR_Coverage, 3991,
10626 /* 29913 */ GIR_EraseRootFromParent_Done,
10627 /* 29914 */ // Label 617: @29914
10628 /* 29914 */ GIM_Reject,
10629 /* 29915 */ // Label 614: @29915
10630 /* 29915 */ GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(29979), // Rule ID 3995 //
10631 /* 29920 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10632 /* 29923 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10633 /* 29926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10634 /* 29930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10635 /* 29934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10636 /* 29938 */ // (avgflooru:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10637 /* 29938 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10638 /* 29941 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10639 /* 29945 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10640 /* 29950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16),
10641 /* 29953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10642 /* 29955 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10643 /* 29957 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10644 /* 29959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10645 /* 29962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10646 /* 29968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10647 /* 29974 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10648 /* 29977 */ GIR_RootConstrainSelectedInstOperands,
10649 /* 29978 */ // GIR_Coverage, 3995,
10650 /* 29978 */ GIR_EraseRootFromParent_Done,
10651 /* 29979 */ // Label 618: @29979
10652 /* 29979 */ GIM_Reject,
10653 /* 29980 */ // Label 615: @29980
10654 /* 29980 */ GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(30044), // Rule ID 3999 //
10655 /* 29985 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10656 /* 29988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10657 /* 29991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10658 /* 29995 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10659 /* 29999 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10660 /* 30003 */ // (avgflooru:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10661 /* 30003 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10662 /* 30006 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10663 /* 30010 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10664 /* 30015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32),
10665 /* 30018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10666 /* 30020 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10667 /* 30022 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10668 /* 30024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10669 /* 30027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10670 /* 30033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10671 /* 30039 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10672 /* 30042 */ GIR_RootConstrainSelectedInstOperands,
10673 /* 30043 */ // GIR_Coverage, 3999,
10674 /* 30043 */ GIR_EraseRootFromParent_Done,
10675 /* 30044 */ // Label 619: @30044
10676 /* 30044 */ GIM_Reject,
10677 /* 30045 */ // Label 616: @30045
10678 /* 30045 */ GIM_Reject,
10679 /* 30046 */ // Label 11: @30046
10680 /* 30046 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 623*/ GIMT_Encode4(30272),
10681 /* 30057 */ /*GILLT_v16s8*//*Label 620*/ GIMT_Encode4(30077), GIMT_Encode4(0),
10682 /* 30065 */ /*GILLT_v8s16*//*Label 621*/ GIMT_Encode4(30142), GIMT_Encode4(0),
10683 /* 30073 */ /*GILLT_v4s32*//*Label 622*/ GIMT_Encode4(30207),
10684 /* 30077 */ // Label 620: @30077
10685 /* 30077 */ GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(30141), // Rule ID 3967 //
10686 /* 30082 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10687 /* 30085 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10688 /* 30088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10689 /* 30092 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10690 /* 30096 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10691 /* 30100 */ // (avgceilu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10692 /* 30100 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10693 /* 30103 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10694 /* 30107 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10695 /* 30112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8),
10696 /* 30115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10697 /* 30117 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10698 /* 30119 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10699 /* 30121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10700 /* 30124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10701 /* 30130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10702 /* 30136 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10703 /* 30139 */ GIR_RootConstrainSelectedInstOperands,
10704 /* 30140 */ // GIR_Coverage, 3967,
10705 /* 30140 */ GIR_EraseRootFromParent_Done,
10706 /* 30141 */ // Label 624: @30141
10707 /* 30141 */ GIM_Reject,
10708 /* 30142 */ // Label 621: @30142
10709 /* 30142 */ GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(30206), // Rule ID 3971 //
10710 /* 30147 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10711 /* 30150 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10712 /* 30153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10713 /* 30157 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10714 /* 30161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10715 /* 30165 */ // (avgceilu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10716 /* 30165 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10717 /* 30168 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10718 /* 30172 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10719 /* 30177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16),
10720 /* 30180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10721 /* 30182 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10722 /* 30184 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10723 /* 30186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10724 /* 30189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10725 /* 30195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10726 /* 30201 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10727 /* 30204 */ GIR_RootConstrainSelectedInstOperands,
10728 /* 30205 */ // GIR_Coverage, 3971,
10729 /* 30205 */ GIR_EraseRootFromParent_Done,
10730 /* 30206 */ // Label 625: @30206
10731 /* 30206 */ GIM_Reject,
10732 /* 30207 */ // Label 622: @30207
10733 /* 30207 */ GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(30271), // Rule ID 3975 //
10734 /* 30212 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10735 /* 30215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10736 /* 30218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10737 /* 30222 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10738 /* 30226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10739 /* 30230 */ // (avgceilu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10740 /* 30230 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10741 /* 30233 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10742 /* 30237 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10743 /* 30242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32),
10744 /* 30245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10745 /* 30247 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10746 /* 30249 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10747 /* 30251 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10748 /* 30254 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10749 /* 30260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10750 /* 30266 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10751 /* 30269 */ GIR_RootConstrainSelectedInstOperands,
10752 /* 30270 */ // GIR_Coverage, 3975,
10753 /* 30270 */ GIR_EraseRootFromParent_Done,
10754 /* 30271 */ // Label 626: @30271
10755 /* 30271 */ GIM_Reject,
10756 /* 30272 */ // Label 623: @30272
10757 /* 30272 */ GIM_Reject,
10758 /* 30273 */ // Label 12: @30273
10759 /* 30273 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 630*/ GIMT_Encode4(30499),
10760 /* 30284 */ /*GILLT_v16s8*//*Label 627*/ GIMT_Encode4(30304), GIMT_Encode4(0),
10761 /* 30292 */ /*GILLT_v8s16*//*Label 628*/ GIMT_Encode4(30369), GIMT_Encode4(0),
10762 /* 30300 */ /*GILLT_v4s32*//*Label 629*/ GIMT_Encode4(30434),
10763 /* 30304 */ // Label 627: @30304
10764 /* 30304 */ GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(30368), // Rule ID 3980 //
10765 /* 30309 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10766 /* 30312 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10767 /* 30315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10768 /* 30319 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10769 /* 30323 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10770 /* 30327 */ // (avgfloors:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10771 /* 30327 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10772 /* 30330 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10773 /* 30334 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10774 /* 30339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8),
10775 /* 30342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10776 /* 30344 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10777 /* 30346 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10778 /* 30348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10779 /* 30351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10780 /* 30357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10781 /* 30363 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10782 /* 30366 */ GIR_RootConstrainSelectedInstOperands,
10783 /* 30367 */ // GIR_Coverage, 3980,
10784 /* 30367 */ GIR_EraseRootFromParent_Done,
10785 /* 30368 */ // Label 631: @30368
10786 /* 30368 */ GIM_Reject,
10787 /* 30369 */ // Label 628: @30369
10788 /* 30369 */ GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(30433), // Rule ID 3983 //
10789 /* 30374 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10790 /* 30377 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10791 /* 30380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10792 /* 30384 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10793 /* 30388 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10794 /* 30392 */ // (avgfloors:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10795 /* 30392 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10796 /* 30395 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10797 /* 30399 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10798 /* 30404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16),
10799 /* 30407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10800 /* 30409 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10801 /* 30411 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10802 /* 30413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10803 /* 30416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10804 /* 30422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10805 /* 30428 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10806 /* 30431 */ GIR_RootConstrainSelectedInstOperands,
10807 /* 30432 */ // GIR_Coverage, 3983,
10808 /* 30432 */ GIR_EraseRootFromParent_Done,
10809 /* 30433 */ // Label 632: @30433
10810 /* 30433 */ GIM_Reject,
10811 /* 30434 */ // Label 629: @30434
10812 /* 30434 */ GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(30498), // Rule ID 3987 //
10813 /* 30439 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10814 /* 30442 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10815 /* 30445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10816 /* 30449 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10817 /* 30453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10818 /* 30457 */ // (avgfloors:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10819 /* 30457 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10820 /* 30460 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10821 /* 30464 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10822 /* 30469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32),
10823 /* 30472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10824 /* 30474 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10825 /* 30476 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10826 /* 30478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10827 /* 30481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10828 /* 30487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10829 /* 30493 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10830 /* 30496 */ GIR_RootConstrainSelectedInstOperands,
10831 /* 30497 */ // GIR_Coverage, 3987,
10832 /* 30497 */ GIR_EraseRootFromParent_Done,
10833 /* 30498 */ // Label 633: @30498
10834 /* 30498 */ GIM_Reject,
10835 /* 30499 */ // Label 630: @30499
10836 /* 30499 */ GIM_Reject,
10837 /* 30500 */ // Label 13: @30500
10838 /* 30500 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 637*/ GIMT_Encode4(30726),
10839 /* 30511 */ /*GILLT_v16s8*//*Label 634*/ GIMT_Encode4(30531), GIMT_Encode4(0),
10840 /* 30519 */ /*GILLT_v8s16*//*Label 635*/ GIMT_Encode4(30596), GIMT_Encode4(0),
10841 /* 30527 */ /*GILLT_v4s32*//*Label 636*/ GIMT_Encode4(30661),
10842 /* 30531 */ // Label 634: @30531
10843 /* 30531 */ GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(30595), // Rule ID 3956 //
10844 /* 30536 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10845 /* 30539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10846 /* 30542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10847 /* 30546 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10848 /* 30550 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10849 /* 30554 */ // (avgceils:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10850 /* 30554 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10851 /* 30557 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10852 /* 30561 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10853 /* 30566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8),
10854 /* 30569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10855 /* 30571 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10856 /* 30573 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10857 /* 30575 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10858 /* 30578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10859 /* 30584 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10860 /* 30590 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10861 /* 30593 */ GIR_RootConstrainSelectedInstOperands,
10862 /* 30594 */ // GIR_Coverage, 3956,
10863 /* 30594 */ GIR_EraseRootFromParent_Done,
10864 /* 30595 */ // Label 638: @30595
10865 /* 30595 */ GIM_Reject,
10866 /* 30596 */ // Label 635: @30596
10867 /* 30596 */ GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(30660), // Rule ID 3959 //
10868 /* 30601 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10869 /* 30604 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10870 /* 30607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10871 /* 30611 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10872 /* 30615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10873 /* 30619 */ // (avgceils:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10874 /* 30619 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10875 /* 30622 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10876 /* 30626 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10877 /* 30631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16),
10878 /* 30634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10879 /* 30636 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10880 /* 30638 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10881 /* 30640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10882 /* 30643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10883 /* 30649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10884 /* 30655 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10885 /* 30658 */ GIR_RootConstrainSelectedInstOperands,
10886 /* 30659 */ // GIR_Coverage, 3959,
10887 /* 30659 */ GIR_EraseRootFromParent_Done,
10888 /* 30660 */ // Label 639: @30660
10889 /* 30660 */ GIM_Reject,
10890 /* 30661 */ // Label 636: @30661
10891 /* 30661 */ GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(30725), // Rule ID 3963 //
10892 /* 30666 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10893 /* 30669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10894 /* 30672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10895 /* 30676 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10896 /* 30680 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10897 /* 30684 */ // (avgceils:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10898 /* 30684 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10899 /* 30687 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10900 /* 30691 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10901 /* 30696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32),
10902 /* 30699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10903 /* 30701 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10904 /* 30703 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10905 /* 30705 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10906 /* 30708 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10907 /* 30714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10908 /* 30720 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10909 /* 30723 */ GIR_RootConstrainSelectedInstOperands,
10910 /* 30724 */ // GIR_Coverage, 3963,
10911 /* 30724 */ GIR_EraseRootFromParent_Done,
10912 /* 30725 */ // Label 640: @30725
10913 /* 30725 */ GIM_Reject,
10914 /* 30726 */ // Label 637: @30726
10915 /* 30726 */ GIM_Reject,
10916 /* 30727 */ // Label 14: @30727
10917 /* 30727 */ GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(31093),
10918 /* 30732 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
10919 /* 30735 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 646*/ GIMT_Encode4(31092),
10920 /* 30746 */ /*GILLT_v16s8*//*Label 642*/ GIMT_Encode4(30770), GIMT_Encode4(0),
10921 /* 30754 */ /*GILLT_v8s16*//*Label 643*/ GIMT_Encode4(30828), GIMT_Encode4(0),
10922 /* 30762 */ /*GILLT_v4s32*//*Label 644*/ GIMT_Encode4(30931),
10923 /* 30766 */ /*GILLT_v2s64*//*Label 645*/ GIMT_Encode4(31034),
10924 /* 30770 */ // Label 642: @30770
10925 /* 30770 */ GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(30827), // Rule ID 3402 //
10926 /* 30775 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10927 /* 30778 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
10928 /* 30781 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
10929 /* 30784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10930 /* 30788 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10931 /* 30792 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10932 /* 30796 */ // (concat_vectors:{ *:[v16i8] } DPR:{ *:[v8i8] }:$Dn, DPR:{ *:[v8i8] }:$Dm) => (REG_SEQUENCE:{ *:[v16i8] } QPR:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dm, dsub_1:{ *:[i32] })
10933 /* 30796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
10934 /* 30799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10935 /* 30801 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
10936 /* 30803 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
10937 /* 30806 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10938 /* 30808 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
10939 /* 30811 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10940 /* 30816 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
10941 /* 30821 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
10942 /* 30826 */ // GIR_Coverage, 3402,
10943 /* 30826 */ GIR_EraseRootFromParent_Done,
10944 /* 30827 */ // Label 647: @30827
10945 /* 30827 */ GIM_Reject,
10946 /* 30828 */ // Label 643: @30828
10947 /* 30828 */ GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(30930),
10948 /* 30833 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
10949 /* 30836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
10950 /* 30839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10951 /* 30843 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10952 /* 30847 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10953 /* 30851 */ GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(30890), // Rule ID 3401 //
10954 /* 30856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10955 /* 30859 */ // (concat_vectors:{ *:[v8i16] } DPR:{ *:[v4i16] }:$Dn, DPR:{ *:[v4i16] }:$Dm) => (REG_SEQUENCE:{ *:[v8i16] } QPR:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dm, dsub_1:{ *:[i32] })
10956 /* 30859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
10957 /* 30862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10958 /* 30864 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
10959 /* 30866 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
10960 /* 30869 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10961 /* 30871 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
10962 /* 30874 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10963 /* 30879 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
10964 /* 30884 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
10965 /* 30889 */ // GIR_Coverage, 3401,
10966 /* 30889 */ GIR_EraseRootFromParent_Done,
10967 /* 30890 */ // Label 649: @30890
10968 /* 30890 */ GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(30929), // Rule ID 3404 //
10969 /* 30895 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10970 /* 30898 */ // (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm) => (REG_SEQUENCE:{ *:[v8f16] } QPR:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dm, dsub_1:{ *:[i32] })
10971 /* 30898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
10972 /* 30901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10973 /* 30903 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
10974 /* 30905 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
10975 /* 30908 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10976 /* 30910 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
10977 /* 30913 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10978 /* 30918 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
10979 /* 30923 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
10980 /* 30928 */ // GIR_Coverage, 3404,
10981 /* 30928 */ GIR_EraseRootFromParent_Done,
10982 /* 30929 */ // Label 650: @30929
10983 /* 30929 */ GIM_Reject,
10984 /* 30930 */ // Label 648: @30930
10985 /* 30930 */ GIM_Reject,
10986 /* 30931 */ // Label 644: @30931
10987 /* 30931 */ GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(31033),
10988 /* 30936 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
10989 /* 30939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
10990 /* 30942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10991 /* 30946 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10992 /* 30950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10993 /* 30954 */ GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(30993), // Rule ID 3400 //
10994 /* 30959 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10995 /* 30962 */ // (concat_vectors:{ *:[v4i32] } DPR:{ *:[v2i32] }:$Dn, DPR:{ *:[v2i32] }:$Dm) => (REG_SEQUENCE:{ *:[v4i32] } QPR:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dm, dsub_1:{ *:[i32] })
10996 /* 30962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
10997 /* 30965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10998 /* 30967 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
10999 /* 30969 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
11000 /* 30972 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
11001 /* 30974 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
11002 /* 30977 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11003 /* 30982 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
11004 /* 30987 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
11005 /* 30992 */ // GIR_Coverage, 3400,
11006 /* 30992 */ GIR_EraseRootFromParent_Done,
11007 /* 30993 */ // Label 652: @30993
11008 /* 30993 */ GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(31032), // Rule ID 3403 //
11009 /* 30998 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11010 /* 31001 */ // (concat_vectors:{ *:[v4f32] } DPR:{ *:[v2f32] }:$Dn, DPR:{ *:[v2f32] }:$Dm) => (REG_SEQUENCE:{ *:[v4f32] } QPR:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dm, dsub_1:{ *:[i32] })
11011 /* 31001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
11012 /* 31004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
11013 /* 31006 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
11014 /* 31008 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
11015 /* 31011 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
11016 /* 31013 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
11017 /* 31016 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11018 /* 31021 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
11019 /* 31026 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
11020 /* 31031 */ // GIR_Coverage, 3403,
11021 /* 31031 */ GIR_EraseRootFromParent_Done,
11022 /* 31032 */ // Label 653: @31032
11023 /* 31032 */ GIM_Reject,
11024 /* 31033 */ // Label 651: @31033
11025 /* 31033 */ GIM_Reject,
11026 /* 31034 */ // Label 645: @31034
11027 /* 31034 */ GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(31091), // Rule ID 3399 //
11028 /* 31039 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11029 /* 31042 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11030 /* 31045 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
11031 /* 31048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11032 /* 31052 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11033 /* 31056 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11034 /* 31060 */ // (concat_vectors:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm) => (REG_SEQUENCE:{ *:[v2i64] } QPR:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dm, dsub_1:{ *:[i32] })
11035 /* 31060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
11036 /* 31063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
11037 /* 31065 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
11038 /* 31067 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
11039 /* 31070 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
11040 /* 31072 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
11041 /* 31075 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11042 /* 31080 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
11043 /* 31085 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
11044 /* 31090 */ // GIR_Coverage, 3399,
11045 /* 31090 */ GIR_EraseRootFromParent_Done,
11046 /* 31091 */ // Label 654: @31091
11047 /* 31091 */ GIM_Reject,
11048 /* 31092 */ // Label 646: @31092
11049 /* 31092 */ GIM_Reject,
11050 /* 31093 */ // Label 641: @31093
11051 /* 31093 */ GIM_Reject,
11052 /* 31094 */ // Label 15: @31094
11053 /* 31094 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 664*/ GIMT_Encode4(40097),
11054 /* 31105 */ /*GILLT_s32*//*Label 655*/ GIMT_Encode4(31157),
11055 /* 31109 */ /*GILLT_s64*//*Label 656*/ GIMT_Encode4(31305), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
11056 /* 31129 */ /*GILLT_v8s8*//*Label 657*/ GIMT_Encode4(32060),
11057 /* 31133 */ /*GILLT_v16s8*//*Label 658*/ GIMT_Encode4(32475),
11058 /* 31137 */ /*GILLT_v4s16*//*Label 659*/ GIMT_Encode4(33430),
11059 /* 31141 */ /*GILLT_v8s16*//*Label 660*/ GIMT_Encode4(34185),
11060 /* 31145 */ /*GILLT_v2s32*//*Label 661*/ GIMT_Encode4(35904),
11061 /* 31149 */ /*GILLT_v4s32*//*Label 662*/ GIMT_Encode4(36659),
11062 /* 31153 */ /*GILLT_v2s64*//*Label 663*/ GIMT_Encode4(38378),
11063 /* 31157 */ // Label 655: @31157
11064 /* 31157 */ GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(31304),
11065 /* 31162 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
11066 /* 31165 */ GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(31199), // Rule ID 740 //
11067 /* 31170 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs),
11068 /* 31173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
11069 /* 31177 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
11070 /* 31181 */ // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn) => (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn)
11071 /* 31181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVRS),
11072 /* 31184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
11073 /* 31186 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
11074 /* 31188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11075 /* 31191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11076 /* 31197 */ GIR_RootConstrainSelectedInstOperands,
11077 /* 31198 */ // GIR_Coverage, 740,
11078 /* 31198 */ GIR_EraseRootFromParent_Done,
11079 /* 31199 */ // Label 666: @31199
11080 /* 31199 */ GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(31233), // Rule ID 741 //
11081 /* 31204 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs_UseVMOVSR),
11082 /* 31207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
11083 /* 31211 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
11084 /* 31215 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt) => (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt)
11085 /* 31215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVSR),
11086 /* 31218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sn]
11087 /* 31220 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt
11088 /* 31222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11089 /* 31225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11090 /* 31231 */ GIR_RootConstrainSelectedInstOperands,
11091 /* 31232 */ // GIR_Coverage, 741,
11092 /* 31232 */ GIR_EraseRootFromParent_Done,
11093 /* 31233 */ // Label 667: @31233
11094 /* 31233 */ GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(31303), // Rule ID 3093 //
11095 /* 31238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseVMOVSR_HasNEON),
11096 /* 31241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
11097 /* 31245 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
11098 /* 31249 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VMOVDRR:{ *:[f64] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$a), ssub_0:{ *:[i32] })
11099 /* 31249 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
11100 /* 31252 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VMOVDRR),
11101 /* 31256 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11102 /* 31261 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
11103 /* 31265 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
11104 /* 31269 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
11105 /* 31272 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11106 /* 31278 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
11107 /* 31280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11108 /* 31283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
11109 /* 31285 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
11110 /* 31292 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
11111 /* 31297 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
11112 /* 31302 */ // GIR_Coverage, 3093,
11113 /* 31302 */ GIR_EraseRootFromParent_Done,
11114 /* 31303 */ // Label 668: @31303
11115 /* 31303 */ GIM_Reject,
11116 /* 31304 */ // Label 665: @31304
11117 /* 31304 */ GIM_Reject,
11118 /* 31305 */ // Label 656: @31305
11119 /* 31305 */ GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(31337), // Rule ID 3095 //
11120 /* 31310 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11121 /* 31313 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11122 /* 31316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11123 /* 31320 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11124 /* 31324 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[f64] }:$src
11125 /* 31324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11126 /* 31327 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11127 /* 31329 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11128 /* 31331 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11129 /* 31336 */ // GIR_Coverage, 3095,
11130 /* 31336 */ GIR_EraseRootFromParent_Done,
11131 /* 31337 */ // Label 669: @31337
11132 /* 31337 */ GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(31369), // Rule ID 3096 //
11133 /* 31342 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11134 /* 31345 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11135 /* 31348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11136 /* 31352 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11137 /* 31356 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v1i64] }:$src
11138 /* 31356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11139 /* 31359 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11140 /* 31361 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11141 /* 31363 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11142 /* 31368 */ // GIR_Coverage, 3096,
11143 /* 31368 */ GIR_EraseRootFromParent_Done,
11144 /* 31369 */ // Label 670: @31369
11145 /* 31369 */ GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(31401), // Rule ID 3107 //
11146 /* 31374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11147 /* 31377 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11148 /* 31380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11149 /* 31384 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11150 /* 31388 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[f64] }:$src
11151 /* 31388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11152 /* 31391 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11153 /* 31393 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11154 /* 31395 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11155 /* 31400 */ // GIR_Coverage, 3107,
11156 /* 31400 */ GIR_EraseRootFromParent_Done,
11157 /* 31401 */ // Label 671: @31401
11158 /* 31401 */ GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(31433), // Rule ID 3108 //
11159 /* 31406 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11160 /* 31409 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11161 /* 31412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11162 /* 31416 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11163 /* 31420 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[f64] }:$src
11164 /* 31420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11165 /* 31423 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11166 /* 31425 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11167 /* 31427 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11168 /* 31432 */ // GIR_Coverage, 3108,
11169 /* 31432 */ GIR_EraseRootFromParent_Done,
11170 /* 31433 */ // Label 672: @31433
11171 /* 31433 */ GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(31465), // Rule ID 3109 //
11172 /* 31438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11173 /* 31441 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11174 /* 31444 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11175 /* 31448 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11176 /* 31452 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[f64] }:$src
11177 /* 31452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11178 /* 31455 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11179 /* 31457 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11180 /* 31459 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11181 /* 31464 */ // GIR_Coverage, 3109,
11182 /* 31464 */ GIR_EraseRootFromParent_Done,
11183 /* 31465 */ // Label 673: @31465
11184 /* 31465 */ GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(31497), // Rule ID 3110 //
11185 /* 31470 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11186 /* 31473 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11187 /* 31476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11188 /* 31480 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11189 /* 31484 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[f64] }:$src
11190 /* 31484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11191 /* 31487 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11192 /* 31489 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11193 /* 31491 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11194 /* 31496 */ // GIR_Coverage, 3110,
11195 /* 31496 */ GIR_EraseRootFromParent_Done,
11196 /* 31497 */ // Label 674: @31497
11197 /* 31497 */ GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(31529), // Rule ID 3111 //
11198 /* 31502 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11199 /* 31505 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
11200 /* 31508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11201 /* 31512 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11202 /* 31516 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[f64] }:$src
11203 /* 31516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11204 /* 31519 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11205 /* 31521 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11206 /* 31523 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11207 /* 31528 */ // GIR_Coverage, 3111,
11208 /* 31528 */ GIR_EraseRootFromParent_Done,
11209 /* 31529 */ // Label 675: @31529
11210 /* 31529 */ GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(31561), // Rule ID 3112 //
11211 /* 31534 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11212 /* 31537 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11213 /* 31540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11214 /* 31544 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11215 /* 31548 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v1i64] }:$src
11216 /* 31548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11217 /* 31551 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11218 /* 31553 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11219 /* 31555 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11220 /* 31560 */ // GIR_Coverage, 3112,
11221 /* 31560 */ GIR_EraseRootFromParent_Done,
11222 /* 31561 */ // Label 676: @31561
11223 /* 31561 */ GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(31593), // Rule ID 3113 //
11224 /* 31566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11225 /* 31569 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11226 /* 31572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11227 /* 31576 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11228 /* 31580 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v1i64] }:$src
11229 /* 31580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11230 /* 31583 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11231 /* 31585 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11232 /* 31587 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11233 /* 31592 */ // GIR_Coverage, 3113,
11234 /* 31592 */ GIR_EraseRootFromParent_Done,
11235 /* 31593 */ // Label 677: @31593
11236 /* 31593 */ GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(31625), // Rule ID 3114 //
11237 /* 31598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11238 /* 31601 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11239 /* 31604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11240 /* 31608 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11241 /* 31612 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v1i64] }:$src
11242 /* 31612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11243 /* 31615 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11244 /* 31617 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11245 /* 31619 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11246 /* 31624 */ // GIR_Coverage, 3114,
11247 /* 31624 */ GIR_EraseRootFromParent_Done,
11248 /* 31625 */ // Label 678: @31625
11249 /* 31625 */ GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(31657), // Rule ID 3115 //
11250 /* 31630 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11251 /* 31633 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11252 /* 31636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11253 /* 31640 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11254 /* 31644 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v1i64] }:$src
11255 /* 31644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11256 /* 31647 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11257 /* 31649 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11258 /* 31651 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11259 /* 31656 */ // GIR_Coverage, 3115,
11260 /* 31656 */ GIR_EraseRootFromParent_Done,
11261 /* 31657 */ // Label 679: @31657
11262 /* 31657 */ GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(31689), // Rule ID 3116 //
11263 /* 31662 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11264 /* 31665 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
11265 /* 31668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11266 /* 31672 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11267 /* 31676 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v1i64] }:$src
11268 /* 31676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11269 /* 31679 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11270 /* 31681 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11271 /* 31683 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11272 /* 31688 */ // GIR_Coverage, 3116,
11273 /* 31688 */ GIR_EraseRootFromParent_Done,
11274 /* 31689 */ // Label 680: @31689
11275 /* 31689 */ GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(31726), // Rule ID 3179 //
11276 /* 31694 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11277 /* 31697 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11278 /* 31700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11279 /* 31704 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11280 /* 31708 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src)
11281 /* 31708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11282 /* 31711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11283 /* 31713 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11284 /* 31715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11285 /* 31718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11286 /* 31724 */ GIR_RootConstrainSelectedInstOperands,
11287 /* 31725 */ // GIR_Coverage, 3179,
11288 /* 31725 */ GIR_EraseRootFromParent_Done,
11289 /* 31726 */ // Label 681: @31726
11290 /* 31726 */ GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(31763), // Rule ID 3180 //
11291 /* 31731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11292 /* 31734 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11293 /* 31737 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11294 /* 31741 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11295 /* 31745 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src)
11296 /* 31745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11297 /* 31748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11298 /* 31750 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11299 /* 31752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11300 /* 31755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11301 /* 31761 */ GIR_RootConstrainSelectedInstOperands,
11302 /* 31762 */ // GIR_Coverage, 3180,
11303 /* 31762 */ GIR_EraseRootFromParent_Done,
11304 /* 31763 */ // Label 682: @31763
11305 /* 31763 */ GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(31800), // Rule ID 3181 //
11306 /* 31768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11307 /* 31771 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11308 /* 31774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11309 /* 31778 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11310 /* 31782 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src)
11311 /* 31782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11312 /* 31785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11313 /* 31787 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11314 /* 31789 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11315 /* 31792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11316 /* 31798 */ GIR_RootConstrainSelectedInstOperands,
11317 /* 31799 */ // GIR_Coverage, 3181,
11318 /* 31799 */ GIR_EraseRootFromParent_Done,
11319 /* 31800 */ // Label 683: @31800
11320 /* 31800 */ GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(31837), // Rule ID 3182 //
11321 /* 31805 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11322 /* 31808 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11323 /* 31811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11324 /* 31815 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11325 /* 31819 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src)
11326 /* 31819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11327 /* 31822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11328 /* 31824 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11329 /* 31826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11330 /* 31829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11331 /* 31835 */ GIR_RootConstrainSelectedInstOperands,
11332 /* 31836 */ // GIR_Coverage, 3182,
11333 /* 31836 */ GIR_EraseRootFromParent_Done,
11334 /* 31837 */ // Label 684: @31837
11335 /* 31837 */ GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(31874), // Rule ID 3183 //
11336 /* 31842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11337 /* 31845 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
11338 /* 31848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11339 /* 31852 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11340 /* 31856 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src)
11341 /* 31856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
11342 /* 31859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11343 /* 31861 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11344 /* 31863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11345 /* 31866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11346 /* 31872 */ GIR_RootConstrainSelectedInstOperands,
11347 /* 31873 */ // GIR_Coverage, 3183,
11348 /* 31873 */ GIR_EraseRootFromParent_Done,
11349 /* 31874 */ // Label 685: @31874
11350 /* 31874 */ GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(31911), // Rule ID 3184 //
11351 /* 31879 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11352 /* 31882 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11353 /* 31885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11354 /* 31889 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11355 /* 31893 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)
11356 /* 31893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11357 /* 31896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11358 /* 31898 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11359 /* 31900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11360 /* 31903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11361 /* 31909 */ GIR_RootConstrainSelectedInstOperands,
11362 /* 31910 */ // GIR_Coverage, 3184,
11363 /* 31910 */ GIR_EraseRootFromParent_Done,
11364 /* 31911 */ // Label 686: @31911
11365 /* 31911 */ GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(31948), // Rule ID 3185 //
11366 /* 31916 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11367 /* 31919 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11368 /* 31922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11369 /* 31926 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11370 /* 31930 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)
11371 /* 31930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11372 /* 31933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11373 /* 31935 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11374 /* 31937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11375 /* 31940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11376 /* 31946 */ GIR_RootConstrainSelectedInstOperands,
11377 /* 31947 */ // GIR_Coverage, 3185,
11378 /* 31947 */ GIR_EraseRootFromParent_Done,
11379 /* 31948 */ // Label 687: @31948
11380 /* 31948 */ GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(31985), // Rule ID 3186 //
11381 /* 31953 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11382 /* 31956 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11383 /* 31959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11384 /* 31963 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11385 /* 31967 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src)
11386 /* 31967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11387 /* 31970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11388 /* 31972 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11389 /* 31974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11390 /* 31977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11391 /* 31983 */ GIR_RootConstrainSelectedInstOperands,
11392 /* 31984 */ // GIR_Coverage, 3186,
11393 /* 31984 */ GIR_EraseRootFromParent_Done,
11394 /* 31985 */ // Label 688: @31985
11395 /* 31985 */ GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(32022), // Rule ID 3187 //
11396 /* 31990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11397 /* 31993 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11398 /* 31996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11399 /* 32000 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11400 /* 32004 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)
11401 /* 32004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11402 /* 32007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11403 /* 32009 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11404 /* 32011 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11405 /* 32014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11406 /* 32020 */ GIR_RootConstrainSelectedInstOperands,
11407 /* 32021 */ // GIR_Coverage, 3187,
11408 /* 32021 */ GIR_EraseRootFromParent_Done,
11409 /* 32022 */ // Label 689: @32022
11410 /* 32022 */ GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(32059), // Rule ID 3188 //
11411 /* 32027 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11412 /* 32030 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
11413 /* 32033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11414 /* 32037 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11415 /* 32041 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)
11416 /* 32041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
11417 /* 32044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11418 /* 32046 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11419 /* 32048 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11420 /* 32051 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11421 /* 32057 */ GIR_RootConstrainSelectedInstOperands,
11422 /* 32058 */ // GIR_Coverage, 3188,
11423 /* 32058 */ GIR_EraseRootFromParent_Done,
11424 /* 32059 */ // Label 690: @32059
11425 /* 32059 */ GIM_Reject,
11426 /* 32060 */ // Label 657: @32060
11427 /* 32060 */ GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(32092), // Rule ID 3137 //
11428 /* 32065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11429 /* 32068 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11430 /* 32071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11431 /* 32075 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11432 /* 32079 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v8i8] }:$src
11433 /* 32079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11434 /* 32082 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11435 /* 32084 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11436 /* 32086 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11437 /* 32091 */ // GIR_Coverage, 3137,
11438 /* 32091 */ GIR_EraseRootFromParent_Done,
11439 /* 32092 */ // Label 691: @32092
11440 /* 32092 */ GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(32124), // Rule ID 3138 //
11441 /* 32097 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11442 /* 32100 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11443 /* 32103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11444 /* 32107 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11445 /* 32111 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v8i8] }:$src
11446 /* 32111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11447 /* 32114 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11448 /* 32116 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11449 /* 32118 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11450 /* 32123 */ // GIR_Coverage, 3138,
11451 /* 32123 */ GIR_EraseRootFromParent_Done,
11452 /* 32124 */ // Label 692: @32124
11453 /* 32124 */ GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(32156), // Rule ID 3139 //
11454 /* 32129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11455 /* 32132 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11456 /* 32135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11457 /* 32139 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11458 /* 32143 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v8i8] }:$src
11459 /* 32143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11460 /* 32146 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11461 /* 32148 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11462 /* 32150 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11463 /* 32155 */ // GIR_Coverage, 3139,
11464 /* 32155 */ GIR_EraseRootFromParent_Done,
11465 /* 32156 */ // Label 693: @32156
11466 /* 32156 */ GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(32188), // Rule ID 3140 //
11467 /* 32161 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11468 /* 32164 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11469 /* 32167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11470 /* 32171 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11471 /* 32175 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v8i8] }:$src
11472 /* 32175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11473 /* 32178 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11474 /* 32180 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11475 /* 32182 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11476 /* 32187 */ // GIR_Coverage, 3140,
11477 /* 32187 */ GIR_EraseRootFromParent_Done,
11478 /* 32188 */ // Label 694: @32188
11479 /* 32188 */ GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(32220), // Rule ID 3141 //
11480 /* 32193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11481 /* 32196 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11482 /* 32199 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11483 /* 32203 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11484 /* 32207 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v8i8] }:$src
11485 /* 32207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11486 /* 32210 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11487 /* 32212 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11488 /* 32214 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11489 /* 32219 */ // GIR_Coverage, 3141,
11490 /* 32219 */ GIR_EraseRootFromParent_Done,
11491 /* 32220 */ // Label 695: @32220
11492 /* 32220 */ GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(32252), // Rule ID 3142 //
11493 /* 32225 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11494 /* 32228 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11495 /* 32231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11496 /* 32235 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11497 /* 32239 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v8i8] }:$src
11498 /* 32239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11499 /* 32242 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11500 /* 32244 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11501 /* 32246 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11502 /* 32251 */ // GIR_Coverage, 3142,
11503 /* 32251 */ GIR_EraseRootFromParent_Done,
11504 /* 32252 */ // Label 696: @32252
11505 /* 32252 */ GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(32289), // Rule ID 3209 //
11506 /* 32257 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11507 /* 32260 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11508 /* 32263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11509 /* 32267 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11510 /* 32271 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src)
11511 /* 32271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
11512 /* 32274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11513 /* 32276 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11514 /* 32278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11515 /* 32281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11516 /* 32287 */ GIR_RootConstrainSelectedInstOperands,
11517 /* 32288 */ // GIR_Coverage, 3209,
11518 /* 32288 */ GIR_EraseRootFromParent_Done,
11519 /* 32289 */ // Label 697: @32289
11520 /* 32289 */ GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(32326), // Rule ID 3210 //
11521 /* 32294 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11522 /* 32297 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11523 /* 32300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11524 /* 32304 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11525 /* 32308 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)
11526 /* 32308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
11527 /* 32311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11528 /* 32313 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11529 /* 32315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11530 /* 32318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11531 /* 32324 */ GIR_RootConstrainSelectedInstOperands,
11532 /* 32325 */ // GIR_Coverage, 3210,
11533 /* 32325 */ GIR_EraseRootFromParent_Done,
11534 /* 32326 */ // Label 698: @32326
11535 /* 32326 */ GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(32363), // Rule ID 3211 //
11536 /* 32331 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11537 /* 32334 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11538 /* 32337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11539 /* 32341 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11540 /* 32345 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)
11541 /* 32345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
11542 /* 32348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11543 /* 32350 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11544 /* 32352 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11545 /* 32355 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11546 /* 32361 */ GIR_RootConstrainSelectedInstOperands,
11547 /* 32362 */ // GIR_Coverage, 3211,
11548 /* 32362 */ GIR_EraseRootFromParent_Done,
11549 /* 32363 */ // Label 699: @32363
11550 /* 32363 */ GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(32400), // Rule ID 3212 //
11551 /* 32368 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11552 /* 32371 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11553 /* 32374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11554 /* 32378 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11555 /* 32382 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)
11556 /* 32382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
11557 /* 32385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11558 /* 32387 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11559 /* 32389 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11560 /* 32392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11561 /* 32398 */ GIR_RootConstrainSelectedInstOperands,
11562 /* 32399 */ // GIR_Coverage, 3212,
11563 /* 32399 */ GIR_EraseRootFromParent_Done,
11564 /* 32400 */ // Label 700: @32400
11565 /* 32400 */ GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(32437), // Rule ID 3213 //
11566 /* 32405 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11567 /* 32408 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11568 /* 32411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11569 /* 32415 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11570 /* 32419 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src)
11571 /* 32419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
11572 /* 32422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11573 /* 32424 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11574 /* 32426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11575 /* 32429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11576 /* 32435 */ GIR_RootConstrainSelectedInstOperands,
11577 /* 32436 */ // GIR_Coverage, 3213,
11578 /* 32436 */ GIR_EraseRootFromParent_Done,
11579 /* 32437 */ // Label 701: @32437
11580 /* 32437 */ GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(32474), // Rule ID 3214 //
11581 /* 32442 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11582 /* 32445 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11583 /* 32448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11584 /* 32452 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11585 /* 32456 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)
11586 /* 32456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
11587 /* 32459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11588 /* 32461 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11589 /* 32463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11590 /* 32466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11591 /* 32472 */ GIR_RootConstrainSelectedInstOperands,
11592 /* 32473 */ // GIR_Coverage, 3214,
11593 /* 32473 */ GIR_EraseRootFromParent_Done,
11594 /* 32474 */ // Label 702: @32474
11595 /* 32474 */ GIM_Reject,
11596 /* 32475 */ // Label 658: @32475
11597 /* 32475 */ GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(32507), // Rule ID 3173 //
11598 /* 32480 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11599 /* 32483 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
11600 /* 32486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11601 /* 32490 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11602 /* 32494 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v16i8] }:$src
11603 /* 32494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11604 /* 32497 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11605 /* 32499 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11606 /* 32501 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11607 /* 32506 */ // GIR_Coverage, 3173,
11608 /* 32506 */ GIR_EraseRootFromParent_Done,
11609 /* 32507 */ // Label 703: @32507
11610 /* 32507 */ GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(32539), // Rule ID 3174 //
11611 /* 32512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11612 /* 32515 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
11613 /* 32518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11614 /* 32522 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11615 /* 32526 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v16i8] }:$src
11616 /* 32526 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11617 /* 32529 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11618 /* 32531 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11619 /* 32533 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11620 /* 32538 */ // GIR_Coverage, 3174,
11621 /* 32538 */ GIR_EraseRootFromParent_Done,
11622 /* 32539 */ // Label 704: @32539
11623 /* 32539 */ GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(32571), // Rule ID 3175 //
11624 /* 32544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11625 /* 32547 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11626 /* 32550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11627 /* 32554 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11628 /* 32558 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v16i8] }:$src
11629 /* 32558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11630 /* 32561 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11631 /* 32563 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11632 /* 32565 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11633 /* 32570 */ // GIR_Coverage, 3175,
11634 /* 32570 */ GIR_EraseRootFromParent_Done,
11635 /* 32571 */ // Label 705: @32571
11636 /* 32571 */ GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(32603), // Rule ID 3176 //
11637 /* 32576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11638 /* 32579 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11639 /* 32582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11640 /* 32586 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11641 /* 32590 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v16i8] }:$src
11642 /* 32590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11643 /* 32593 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11644 /* 32595 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11645 /* 32597 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11646 /* 32602 */ // GIR_Coverage, 3176,
11647 /* 32602 */ GIR_EraseRootFromParent_Done,
11648 /* 32603 */ // Label 706: @32603
11649 /* 32603 */ GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(32635), // Rule ID 3177 //
11650 /* 32608 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11651 /* 32611 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11652 /* 32614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11653 /* 32618 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11654 /* 32622 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v16i8] }:$src
11655 /* 32622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11656 /* 32625 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11657 /* 32627 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11658 /* 32629 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11659 /* 32634 */ // GIR_Coverage, 3177,
11660 /* 32634 */ GIR_EraseRootFromParent_Done,
11661 /* 32635 */ // Label 707: @32635
11662 /* 32635 */ GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(32667), // Rule ID 3178 //
11663 /* 32640 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11664 /* 32643 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11665 /* 32646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11666 /* 32650 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11667 /* 32654 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v16i8] }:$src
11668 /* 32654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11669 /* 32657 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11670 /* 32659 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11671 /* 32661 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11672 /* 32666 */ // GIR_Coverage, 3178,
11673 /* 32666 */ GIR_EraseRootFromParent_Done,
11674 /* 32667 */ // Label 708: @32667
11675 /* 32667 */ GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(32704), // Rule ID 3245 //
11676 /* 32672 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11677 /* 32675 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
11678 /* 32678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11679 /* 32682 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11680 /* 32686 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)
11681 /* 32686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
11682 /* 32689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11683 /* 32691 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11684 /* 32693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11685 /* 32696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11686 /* 32702 */ GIR_RootConstrainSelectedInstOperands,
11687 /* 32703 */ // GIR_Coverage, 3245,
11688 /* 32703 */ GIR_EraseRootFromParent_Done,
11689 /* 32704 */ // Label 709: @32704
11690 /* 32704 */ GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(32741), // Rule ID 3246 //
11691 /* 32709 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11692 /* 32712 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
11693 /* 32715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11694 /* 32719 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11695 /* 32723 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)
11696 /* 32723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
11697 /* 32726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11698 /* 32728 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11699 /* 32730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11700 /* 32733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11701 /* 32739 */ GIR_RootConstrainSelectedInstOperands,
11702 /* 32740 */ // GIR_Coverage, 3246,
11703 /* 32740 */ GIR_EraseRootFromParent_Done,
11704 /* 32741 */ // Label 710: @32741
11705 /* 32741 */ GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(32778), // Rule ID 3247 //
11706 /* 32746 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11707 /* 32749 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11708 /* 32752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11709 /* 32756 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11710 /* 32760 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)
11711 /* 32760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
11712 /* 32763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11713 /* 32765 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11714 /* 32767 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11715 /* 32770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11716 /* 32776 */ GIR_RootConstrainSelectedInstOperands,
11717 /* 32777 */ // GIR_Coverage, 3247,
11718 /* 32777 */ GIR_EraseRootFromParent_Done,
11719 /* 32778 */ // Label 711: @32778
11720 /* 32778 */ GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(32815), // Rule ID 3248 //
11721 /* 32783 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11722 /* 32786 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11723 /* 32789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11724 /* 32793 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11725 /* 32797 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)
11726 /* 32797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
11727 /* 32800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11728 /* 32802 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11729 /* 32804 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11730 /* 32807 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11731 /* 32813 */ GIR_RootConstrainSelectedInstOperands,
11732 /* 32814 */ // GIR_Coverage, 3248,
11733 /* 32814 */ GIR_EraseRootFromParent_Done,
11734 /* 32815 */ // Label 712: @32815
11735 /* 32815 */ GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(32852), // Rule ID 3249 //
11736 /* 32820 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11737 /* 32823 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11738 /* 32826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11739 /* 32830 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11740 /* 32834 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src)
11741 /* 32834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
11742 /* 32837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11743 /* 32839 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11744 /* 32841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11745 /* 32844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11746 /* 32850 */ GIR_RootConstrainSelectedInstOperands,
11747 /* 32851 */ // GIR_Coverage, 3249,
11748 /* 32851 */ GIR_EraseRootFromParent_Done,
11749 /* 32852 */ // Label 713: @32852
11750 /* 32852 */ GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(32889), // Rule ID 3250 //
11751 /* 32857 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11752 /* 32860 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11753 /* 32863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11754 /* 32867 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11755 /* 32871 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)
11756 /* 32871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
11757 /* 32874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11758 /* 32876 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11759 /* 32878 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11760 /* 32881 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11761 /* 32887 */ GIR_RootConstrainSelectedInstOperands,
11762 /* 32888 */ // GIR_Coverage, 3250,
11763 /* 32888 */ GIR_EraseRootFromParent_Done,
11764 /* 32889 */ // Label 714: @32889
11765 /* 32889 */ GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(32921), // Rule ID 5834 //
11766 /* 32894 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11767 /* 32897 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
11768 /* 32900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11769 /* 32904 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11770 /* 32908 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v16i8] }:$src
11771 /* 32908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11772 /* 32911 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11773 /* 32913 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11774 /* 32915 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11775 /* 32920 */ // GIR_Coverage, 5834,
11776 /* 32920 */ GIR_EraseRootFromParent_Done,
11777 /* 32921 */ // Label 715: @32921
11778 /* 32921 */ GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(32953), // Rule ID 5835 //
11779 /* 32926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11780 /* 32929 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
11781 /* 32932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11782 /* 32936 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11783 /* 32940 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v16i8] }:$src
11784 /* 32940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11785 /* 32943 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11786 /* 32945 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11787 /* 32947 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11788 /* 32952 */ // GIR_Coverage, 5835,
11789 /* 32952 */ GIR_EraseRootFromParent_Done,
11790 /* 32953 */ // Label 716: @32953
11791 /* 32953 */ GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(32985), // Rule ID 5836 //
11792 /* 32958 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11793 /* 32961 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11794 /* 32964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11795 /* 32968 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11796 /* 32972 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v16i8] }:$src
11797 /* 32972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11798 /* 32975 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11799 /* 32977 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11800 /* 32979 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11801 /* 32984 */ // GIR_Coverage, 5836,
11802 /* 32984 */ GIR_EraseRootFromParent_Done,
11803 /* 32985 */ // Label 717: @32985
11804 /* 32985 */ GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(33017), // Rule ID 5837 //
11805 /* 32990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11806 /* 32993 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11807 /* 32996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11808 /* 33000 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11809 /* 33004 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v16i8] }:$src
11810 /* 33004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11811 /* 33007 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11812 /* 33009 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11813 /* 33011 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11814 /* 33016 */ // GIR_Coverage, 5837,
11815 /* 33016 */ GIR_EraseRootFromParent_Done,
11816 /* 33017 */ // Label 718: @33017
11817 /* 33017 */ GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(33049), // Rule ID 5838 //
11818 /* 33022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11819 /* 33025 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11820 /* 33028 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11821 /* 33032 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11822 /* 33036 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v16i8] }:$src
11823 /* 33036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11824 /* 33039 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11825 /* 33041 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11826 /* 33043 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11827 /* 33048 */ // GIR_Coverage, 5838,
11828 /* 33048 */ GIR_EraseRootFromParent_Done,
11829 /* 33049 */ // Label 719: @33049
11830 /* 33049 */ GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(33081), // Rule ID 5839 //
11831 /* 33054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
11832 /* 33057 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11833 /* 33060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11834 /* 33064 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11835 /* 33068 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v16i8] }:$src
11836 /* 33068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11837 /* 33071 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11838 /* 33073 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11839 /* 33075 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11840 /* 33080 */ // GIR_Coverage, 5839,
11841 /* 33080 */ GIR_EraseRootFromParent_Done,
11842 /* 33081 */ // Label 720: @33081
11843 /* 33081 */ GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(33139), // Rule ID 5870 //
11844 /* 33086 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
11845 /* 33089 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
11846 /* 33092 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11847 /* 33096 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11848 /* 33100 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src)
11849 /* 33100 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11850 /* 33103 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11851 /* 33107 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11852 /* 33112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
11853 /* 33115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11854 /* 33117 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11855 /* 33119 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11856 /* 33122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11857 /* 33128 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11858 /* 33134 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11859 /* 33137 */ GIR_RootConstrainSelectedInstOperands,
11860 /* 33138 */ // GIR_Coverage, 5870,
11861 /* 33138 */ GIR_EraseRootFromParent_Done,
11862 /* 33139 */ // Label 721: @33139
11863 /* 33139 */ GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(33197), // Rule ID 5871 //
11864 /* 33144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
11865 /* 33147 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
11866 /* 33150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11867 /* 33154 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11868 /* 33158 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src)
11869 /* 33158 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11870 /* 33161 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11871 /* 33165 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11872 /* 33170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
11873 /* 33173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11874 /* 33175 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11875 /* 33177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11876 /* 33180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11877 /* 33186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11878 /* 33192 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11879 /* 33195 */ GIR_RootConstrainSelectedInstOperands,
11880 /* 33196 */ // GIR_Coverage, 5871,
11881 /* 33196 */ GIR_EraseRootFromParent_Done,
11882 /* 33197 */ // Label 722: @33197
11883 /* 33197 */ GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(33255), // Rule ID 5872 //
11884 /* 33202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
11885 /* 33205 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11886 /* 33208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11887 /* 33212 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11888 /* 33216 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src)
11889 /* 33216 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11890 /* 33219 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11891 /* 33223 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11892 /* 33228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
11893 /* 33231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11894 /* 33233 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11895 /* 33235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11896 /* 33238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11897 /* 33244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11898 /* 33250 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11899 /* 33253 */ GIR_RootConstrainSelectedInstOperands,
11900 /* 33254 */ // GIR_Coverage, 5872,
11901 /* 33254 */ GIR_EraseRootFromParent_Done,
11902 /* 33255 */ // Label 723: @33255
11903 /* 33255 */ GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(33313), // Rule ID 5873 //
11904 /* 33260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
11905 /* 33263 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11906 /* 33266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11907 /* 33270 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11908 /* 33274 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)
11909 /* 33274 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11910 /* 33277 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11911 /* 33281 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11912 /* 33286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
11913 /* 33289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11914 /* 33291 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11915 /* 33293 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11916 /* 33296 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11917 /* 33302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11918 /* 33308 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11919 /* 33311 */ GIR_RootConstrainSelectedInstOperands,
11920 /* 33312 */ // GIR_Coverage, 5873,
11921 /* 33312 */ GIR_EraseRootFromParent_Done,
11922 /* 33313 */ // Label 724: @33313
11923 /* 33313 */ GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(33371), // Rule ID 5874 //
11924 /* 33318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
11925 /* 33321 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11926 /* 33324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11927 /* 33328 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11928 /* 33332 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src)
11929 /* 33332 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11930 /* 33335 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11931 /* 33339 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11932 /* 33344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
11933 /* 33347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11934 /* 33349 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11935 /* 33351 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11936 /* 33354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11937 /* 33360 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11938 /* 33366 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11939 /* 33369 */ GIR_RootConstrainSelectedInstOperands,
11940 /* 33370 */ // GIR_Coverage, 5874,
11941 /* 33370 */ GIR_EraseRootFromParent_Done,
11942 /* 33371 */ // Label 725: @33371
11943 /* 33371 */ GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(33429), // Rule ID 5875 //
11944 /* 33376 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
11945 /* 33379 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11946 /* 33382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11947 /* 33386 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11948 /* 33390 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src)
11949 /* 33390 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11950 /* 33393 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11951 /* 33397 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11952 /* 33402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
11953 /* 33405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11954 /* 33407 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11955 /* 33409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11956 /* 33412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11957 /* 33418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11958 /* 33424 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11959 /* 33427 */ GIR_RootConstrainSelectedInstOperands,
11960 /* 33428 */ // GIR_Coverage, 5875,
11961 /* 33428 */ GIR_EraseRootFromParent_Done,
11962 /* 33429 */ // Label 726: @33429
11963 /* 33429 */ GIM_Reject,
11964 /* 33430 */ // Label 659: @33430
11965 /* 33430 */ GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(33462), // Rule ID 3099 //
11966 /* 33435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11967 /* 33438 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11968 /* 33441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11969 /* 33445 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11970 /* 33449 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v4i16] }:$src
11971 /* 33449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11972 /* 33452 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11973 /* 33454 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11974 /* 33456 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11975 /* 33461 */ // GIR_Coverage, 3099,
11976 /* 33461 */ GIR_EraseRootFromParent_Done,
11977 /* 33462 */ // Label 727: @33462
11978 /* 33462 */ GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(33494), // Rule ID 3100 //
11979 /* 33467 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11980 /* 33470 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11981 /* 33473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11982 /* 33477 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11983 /* 33481 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v4f16] }:$src
11984 /* 33481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11985 /* 33484 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11986 /* 33486 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11987 /* 33488 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11988 /* 33493 */ // GIR_Coverage, 3100,
11989 /* 33493 */ GIR_EraseRootFromParent_Done,
11990 /* 33494 */ // Label 728: @33494
11991 /* 33494 */ GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(33526), // Rule ID 3127 //
11992 /* 33499 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11993 /* 33502 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11994 /* 33505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11995 /* 33509 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11996 /* 33513 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4f16] }:$src
11997 /* 33513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11998 /* 33516 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11999 /* 33518 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12000 /* 33520 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12001 /* 33525 */ // GIR_Coverage, 3127,
12002 /* 33525 */ GIR_EraseRootFromParent_Done,
12003 /* 33526 */ // Label 729: @33526
12004 /* 33526 */ GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(33558), // Rule ID 3128 //
12005 /* 33531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12006 /* 33534 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12007 /* 33537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12008 /* 33541 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12009 /* 33545 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4f16] }:$src
12010 /* 33545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12011 /* 33548 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12012 /* 33550 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12013 /* 33552 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12014 /* 33557 */ // GIR_Coverage, 3128,
12015 /* 33557 */ GIR_EraseRootFromParent_Done,
12016 /* 33558 */ // Label 730: @33558
12017 /* 33558 */ GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(33590), // Rule ID 3129 //
12018 /* 33563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12019 /* 33566 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12020 /* 33569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12021 /* 33573 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12022 /* 33577 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4f16] }:$src
12023 /* 33577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12024 /* 33580 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12025 /* 33582 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12026 /* 33584 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12027 /* 33589 */ // GIR_Coverage, 3129,
12028 /* 33589 */ GIR_EraseRootFromParent_Done,
12029 /* 33590 */ // Label 731: @33590
12030 /* 33590 */ GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(33622), // Rule ID 3130 //
12031 /* 33595 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12032 /* 33598 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12033 /* 33601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12034 /* 33605 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12035 /* 33609 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4f16] }:$src
12036 /* 33609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12037 /* 33612 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12038 /* 33614 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12039 /* 33616 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12040 /* 33621 */ // GIR_Coverage, 3130,
12041 /* 33621 */ GIR_EraseRootFromParent_Done,
12042 /* 33622 */ // Label 732: @33622
12043 /* 33622 */ GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(33654), // Rule ID 3131 //
12044 /* 33627 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12045 /* 33630 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
12046 /* 33633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12047 /* 33637 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12048 /* 33641 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4f16] }:$src
12049 /* 33641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12050 /* 33644 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12051 /* 33646 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12052 /* 33648 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12053 /* 33653 */ // GIR_Coverage, 3131,
12054 /* 33653 */ GIR_EraseRootFromParent_Done,
12055 /* 33654 */ // Label 733: @33654
12056 /* 33654 */ GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(33686), // Rule ID 3132 //
12057 /* 33659 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12058 /* 33662 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12059 /* 33665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12060 /* 33669 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12061 /* 33673 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4i16] }:$src
12062 /* 33673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12063 /* 33676 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12064 /* 33678 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12065 /* 33680 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12066 /* 33685 */ // GIR_Coverage, 3132,
12067 /* 33685 */ GIR_EraseRootFromParent_Done,
12068 /* 33686 */ // Label 734: @33686
12069 /* 33686 */ GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(33718), // Rule ID 3133 //
12070 /* 33691 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12071 /* 33694 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12072 /* 33697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12073 /* 33701 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12074 /* 33705 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4i16] }:$src
12075 /* 33705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12076 /* 33708 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12077 /* 33710 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12078 /* 33712 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12079 /* 33717 */ // GIR_Coverage, 3133,
12080 /* 33717 */ GIR_EraseRootFromParent_Done,
12081 /* 33718 */ // Label 735: @33718
12082 /* 33718 */ GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(33750), // Rule ID 3134 //
12083 /* 33723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12084 /* 33726 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12085 /* 33729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12086 /* 33733 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12087 /* 33737 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4i16] }:$src
12088 /* 33737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12089 /* 33740 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12090 /* 33742 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12091 /* 33744 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12092 /* 33749 */ // GIR_Coverage, 3134,
12093 /* 33749 */ GIR_EraseRootFromParent_Done,
12094 /* 33750 */ // Label 736: @33750
12095 /* 33750 */ GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(33782), // Rule ID 3135 //
12096 /* 33755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12097 /* 33758 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12098 /* 33761 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12099 /* 33765 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12100 /* 33769 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4i16] }:$src
12101 /* 33769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12102 /* 33772 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12103 /* 33774 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12104 /* 33776 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12105 /* 33781 */ // GIR_Coverage, 3135,
12106 /* 33781 */ GIR_EraseRootFromParent_Done,
12107 /* 33782 */ // Label 737: @33782
12108 /* 33782 */ GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(33814), // Rule ID 3136 //
12109 /* 33787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12110 /* 33790 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
12111 /* 33793 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12112 /* 33797 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12113 /* 33801 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4i16] }:$src
12114 /* 33801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12115 /* 33804 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12116 /* 33806 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12117 /* 33808 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12118 /* 33813 */ // GIR_Coverage, 3136,
12119 /* 33813 */ GIR_EraseRootFromParent_Done,
12120 /* 33814 */ // Label 738: @33814
12121 /* 33814 */ GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(33851), // Rule ID 3199 //
12122 /* 33819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12123 /* 33822 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12124 /* 33825 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12125 /* 33829 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12126 /* 33833 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[f64] }:$src)
12127 /* 33833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
12128 /* 33836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12129 /* 33838 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12130 /* 33840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12131 /* 33843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12132 /* 33849 */ GIR_RootConstrainSelectedInstOperands,
12133 /* 33850 */ // GIR_Coverage, 3199,
12134 /* 33850 */ GIR_EraseRootFromParent_Done,
12135 /* 33851 */ // Label 739: @33851
12136 /* 33851 */ GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(33888), // Rule ID 3200 //
12137 /* 33856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12138 /* 33859 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12139 /* 33862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12140 /* 33866 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12141 /* 33870 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src)
12142 /* 33870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
12143 /* 33873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12144 /* 33875 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12145 /* 33877 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12146 /* 33880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12147 /* 33886 */ GIR_RootConstrainSelectedInstOperands,
12148 /* 33887 */ // GIR_Coverage, 3200,
12149 /* 33887 */ GIR_EraseRootFromParent_Done,
12150 /* 33888 */ // Label 740: @33888
12151 /* 33888 */ GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(33925), // Rule ID 3201 //
12152 /* 33893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12153 /* 33896 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12154 /* 33899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12155 /* 33903 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12156 /* 33907 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src)
12157 /* 33907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12158 /* 33910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12159 /* 33912 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12160 /* 33914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12161 /* 33917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12162 /* 33923 */ GIR_RootConstrainSelectedInstOperands,
12163 /* 33924 */ // GIR_Coverage, 3201,
12164 /* 33924 */ GIR_EraseRootFromParent_Done,
12165 /* 33925 */ // Label 741: @33925
12166 /* 33925 */ GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(33962), // Rule ID 3202 //
12167 /* 33930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12168 /* 33933 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12169 /* 33936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12170 /* 33940 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12171 /* 33944 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src)
12172 /* 33944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12173 /* 33947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12174 /* 33949 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12175 /* 33951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12176 /* 33954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12177 /* 33960 */ GIR_RootConstrainSelectedInstOperands,
12178 /* 33961 */ // GIR_Coverage, 3202,
12179 /* 33961 */ GIR_EraseRootFromParent_Done,
12180 /* 33962 */ // Label 742: @33962
12181 /* 33962 */ GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(33999), // Rule ID 3203 //
12182 /* 33967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12183 /* 33970 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
12184 /* 33973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12185 /* 33977 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12186 /* 33981 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src)
12187 /* 33981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
12188 /* 33984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12189 /* 33986 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12190 /* 33988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12191 /* 33991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12192 /* 33997 */ GIR_RootConstrainSelectedInstOperands,
12193 /* 33998 */ // GIR_Coverage, 3203,
12194 /* 33998 */ GIR_EraseRootFromParent_Done,
12195 /* 33999 */ // Label 743: @33999
12196 /* 33999 */ GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(34036), // Rule ID 3204 //
12197 /* 34004 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12198 /* 34007 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12199 /* 34010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12200 /* 34014 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12201 /* 34018 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src)
12202 /* 34018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
12203 /* 34021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12204 /* 34023 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12205 /* 34025 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12206 /* 34028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12207 /* 34034 */ GIR_RootConstrainSelectedInstOperands,
12208 /* 34035 */ // GIR_Coverage, 3204,
12209 /* 34035 */ GIR_EraseRootFromParent_Done,
12210 /* 34036 */ // Label 744: @34036
12211 /* 34036 */ GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(34073), // Rule ID 3205 //
12212 /* 34041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12213 /* 34044 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12214 /* 34047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12215 /* 34051 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12216 /* 34055 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)
12217 /* 34055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
12218 /* 34058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12219 /* 34060 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12220 /* 34062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12221 /* 34065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12222 /* 34071 */ GIR_RootConstrainSelectedInstOperands,
12223 /* 34072 */ // GIR_Coverage, 3205,
12224 /* 34072 */ GIR_EraseRootFromParent_Done,
12225 /* 34073 */ // Label 745: @34073
12226 /* 34073 */ GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(34110), // Rule ID 3206 //
12227 /* 34078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12228 /* 34081 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12229 /* 34084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12230 /* 34088 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12231 /* 34092 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)
12232 /* 34092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12233 /* 34095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12234 /* 34097 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12235 /* 34099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12236 /* 34102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12237 /* 34108 */ GIR_RootConstrainSelectedInstOperands,
12238 /* 34109 */ // GIR_Coverage, 3206,
12239 /* 34109 */ GIR_EraseRootFromParent_Done,
12240 /* 34110 */ // Label 746: @34110
12241 /* 34110 */ GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(34147), // Rule ID 3207 //
12242 /* 34115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12243 /* 34118 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12244 /* 34121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12245 /* 34125 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12246 /* 34129 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)
12247 /* 34129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12248 /* 34132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12249 /* 34134 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12250 /* 34136 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12251 /* 34139 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12252 /* 34145 */ GIR_RootConstrainSelectedInstOperands,
12253 /* 34146 */ // GIR_Coverage, 3207,
12254 /* 34146 */ GIR_EraseRootFromParent_Done,
12255 /* 34147 */ // Label 747: @34147
12256 /* 34147 */ GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(34184), // Rule ID 3208 //
12257 /* 34152 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12258 /* 34155 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
12259 /* 34158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12260 /* 34162 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12261 /* 34166 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)
12262 /* 34166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
12263 /* 34169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12264 /* 34171 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12265 /* 34173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12266 /* 34176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12267 /* 34182 */ GIR_RootConstrainSelectedInstOperands,
12268 /* 34183 */ // GIR_Coverage, 3208,
12269 /* 34183 */ GIR_EraseRootFromParent_Done,
12270 /* 34184 */ // Label 748: @34184
12271 /* 34184 */ GIM_Reject,
12272 /* 34185 */ // Label 660: @34185
12273 /* 34185 */ GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(34217), // Rule ID 3105 //
12274 /* 34190 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12275 /* 34193 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12276 /* 34196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12277 /* 34200 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12278 /* 34204 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v8i16] }:$src
12279 /* 34204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12280 /* 34207 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12281 /* 34209 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12282 /* 34211 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12283 /* 34216 */ // GIR_Coverage, 3105,
12284 /* 34216 */ GIR_EraseRootFromParent_Done,
12285 /* 34217 */ // Label 749: @34217
12286 /* 34217 */ GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(34249), // Rule ID 3106 //
12287 /* 34222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12288 /* 34225 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12289 /* 34228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12290 /* 34232 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12291 /* 34236 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v8f16] }:$src
12292 /* 34236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12293 /* 34239 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12294 /* 34241 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12295 /* 34243 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12296 /* 34248 */ // GIR_Coverage, 3106,
12297 /* 34248 */ GIR_EraseRootFromParent_Done,
12298 /* 34249 */ // Label 750: @34249
12299 /* 34249 */ GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(34281), // Rule ID 3163 //
12300 /* 34254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12301 /* 34257 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12302 /* 34260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12303 /* 34264 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12304 /* 34268 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8f16] }:$src
12305 /* 34268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12306 /* 34271 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12307 /* 34273 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12308 /* 34275 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12309 /* 34280 */ // GIR_Coverage, 3163,
12310 /* 34280 */ GIR_EraseRootFromParent_Done,
12311 /* 34281 */ // Label 751: @34281
12312 /* 34281 */ GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(34313), // Rule ID 3164 //
12313 /* 34286 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12314 /* 34289 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12315 /* 34292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12316 /* 34296 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12317 /* 34300 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8f16] }:$src
12318 /* 34300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12319 /* 34303 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12320 /* 34305 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12321 /* 34307 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12322 /* 34312 */ // GIR_Coverage, 3164,
12323 /* 34312 */ GIR_EraseRootFromParent_Done,
12324 /* 34313 */ // Label 752: @34313
12325 /* 34313 */ GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(34345), // Rule ID 3165 //
12326 /* 34318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12327 /* 34321 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12328 /* 34324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12329 /* 34328 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12330 /* 34332 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8f16] }:$src
12331 /* 34332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12332 /* 34335 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12333 /* 34337 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12334 /* 34339 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12335 /* 34344 */ // GIR_Coverage, 3165,
12336 /* 34344 */ GIR_EraseRootFromParent_Done,
12337 /* 34345 */ // Label 753: @34345
12338 /* 34345 */ GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(34377), // Rule ID 3166 //
12339 /* 34350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12340 /* 34353 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12341 /* 34356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12342 /* 34360 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12343 /* 34364 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8f16] }:$src
12344 /* 34364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12345 /* 34367 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12346 /* 34369 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12347 /* 34371 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12348 /* 34376 */ // GIR_Coverage, 3166,
12349 /* 34376 */ GIR_EraseRootFromParent_Done,
12350 /* 34377 */ // Label 754: @34377
12351 /* 34377 */ GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(34409), // Rule ID 3167 //
12352 /* 34382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12353 /* 34385 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12354 /* 34388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12355 /* 34392 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12356 /* 34396 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8f16] }:$src
12357 /* 34396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12358 /* 34399 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12359 /* 34401 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12360 /* 34403 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12361 /* 34408 */ // GIR_Coverage, 3167,
12362 /* 34408 */ GIR_EraseRootFromParent_Done,
12363 /* 34409 */ // Label 755: @34409
12364 /* 34409 */ GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(34441), // Rule ID 3168 //
12365 /* 34414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12366 /* 34417 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12367 /* 34420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12368 /* 34424 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12369 /* 34428 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8i16] }:$src
12370 /* 34428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12371 /* 34431 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12372 /* 34433 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12373 /* 34435 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12374 /* 34440 */ // GIR_Coverage, 3168,
12375 /* 34440 */ GIR_EraseRootFromParent_Done,
12376 /* 34441 */ // Label 756: @34441
12377 /* 34441 */ GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(34473), // Rule ID 3169 //
12378 /* 34446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12379 /* 34449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12380 /* 34452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12381 /* 34456 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12382 /* 34460 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8i16] }:$src
12383 /* 34460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12384 /* 34463 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12385 /* 34465 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12386 /* 34467 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12387 /* 34472 */ // GIR_Coverage, 3169,
12388 /* 34472 */ GIR_EraseRootFromParent_Done,
12389 /* 34473 */ // Label 757: @34473
12390 /* 34473 */ GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(34505), // Rule ID 3170 //
12391 /* 34478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12392 /* 34481 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12393 /* 34484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12394 /* 34488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12395 /* 34492 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8i16] }:$src
12396 /* 34492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12397 /* 34495 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12398 /* 34497 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12399 /* 34499 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12400 /* 34504 */ // GIR_Coverage, 3170,
12401 /* 34504 */ GIR_EraseRootFromParent_Done,
12402 /* 34505 */ // Label 758: @34505
12403 /* 34505 */ GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(34537), // Rule ID 3171 //
12404 /* 34510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12405 /* 34513 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12406 /* 34516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12407 /* 34520 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12408 /* 34524 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8i16] }:$src
12409 /* 34524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12410 /* 34527 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12411 /* 34529 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12412 /* 34531 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12413 /* 34536 */ // GIR_Coverage, 3171,
12414 /* 34536 */ GIR_EraseRootFromParent_Done,
12415 /* 34537 */ // Label 759: @34537
12416 /* 34537 */ GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(34569), // Rule ID 3172 //
12417 /* 34542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12418 /* 34545 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12419 /* 34548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12420 /* 34552 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12421 /* 34556 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8i16] }:$src
12422 /* 34556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12423 /* 34559 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12424 /* 34561 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12425 /* 34563 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12426 /* 34568 */ // GIR_Coverage, 3172,
12427 /* 34568 */ GIR_EraseRootFromParent_Done,
12428 /* 34569 */ // Label 760: @34569
12429 /* 34569 */ GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(34606), // Rule ID 3235 //
12430 /* 34574 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12431 /* 34577 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12432 /* 34580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12433 /* 34584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12434 /* 34588 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)
12435 /* 34588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12436 /* 34591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12437 /* 34593 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12438 /* 34595 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12439 /* 34598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12440 /* 34604 */ GIR_RootConstrainSelectedInstOperands,
12441 /* 34605 */ // GIR_Coverage, 3235,
12442 /* 34605 */ GIR_EraseRootFromParent_Done,
12443 /* 34606 */ // Label 761: @34606
12444 /* 34606 */ GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(34643), // Rule ID 3236 //
12445 /* 34611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12446 /* 34614 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12447 /* 34617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12448 /* 34621 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12449 /* 34625 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src)
12450 /* 34625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12451 /* 34628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12452 /* 34630 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12453 /* 34632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12454 /* 34635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12455 /* 34641 */ GIR_RootConstrainSelectedInstOperands,
12456 /* 34642 */ // GIR_Coverage, 3236,
12457 /* 34642 */ GIR_EraseRootFromParent_Done,
12458 /* 34643 */ // Label 762: @34643
12459 /* 34643 */ GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(34680), // Rule ID 3237 //
12460 /* 34648 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12461 /* 34651 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12462 /* 34654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12463 /* 34658 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12464 /* 34662 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src)
12465 /* 34662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12466 /* 34665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12467 /* 34667 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12468 /* 34669 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12469 /* 34672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12470 /* 34678 */ GIR_RootConstrainSelectedInstOperands,
12471 /* 34679 */ // GIR_Coverage, 3237,
12472 /* 34679 */ GIR_EraseRootFromParent_Done,
12473 /* 34680 */ // Label 763: @34680
12474 /* 34680 */ GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(34717), // Rule ID 3238 //
12475 /* 34685 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12476 /* 34688 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12477 /* 34691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12478 /* 34695 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12479 /* 34699 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src)
12480 /* 34699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12481 /* 34702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12482 /* 34704 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12483 /* 34706 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12484 /* 34709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12485 /* 34715 */ GIR_RootConstrainSelectedInstOperands,
12486 /* 34716 */ // GIR_Coverage, 3238,
12487 /* 34716 */ GIR_EraseRootFromParent_Done,
12488 /* 34717 */ // Label 764: @34717
12489 /* 34717 */ GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(34754), // Rule ID 3239 //
12490 /* 34722 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12491 /* 34725 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12492 /* 34728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12493 /* 34732 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12494 /* 34736 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src)
12495 /* 34736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
12496 /* 34739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12497 /* 34741 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12498 /* 34743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12499 /* 34746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12500 /* 34752 */ GIR_RootConstrainSelectedInstOperands,
12501 /* 34753 */ // GIR_Coverage, 3239,
12502 /* 34753 */ GIR_EraseRootFromParent_Done,
12503 /* 34754 */ // Label 765: @34754
12504 /* 34754 */ GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(34791), // Rule ID 3240 //
12505 /* 34759 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12506 /* 34762 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12507 /* 34765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12508 /* 34769 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12509 /* 34773 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)
12510 /* 34773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12511 /* 34776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12512 /* 34778 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12513 /* 34780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12514 /* 34783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12515 /* 34789 */ GIR_RootConstrainSelectedInstOperands,
12516 /* 34790 */ // GIR_Coverage, 3240,
12517 /* 34790 */ GIR_EraseRootFromParent_Done,
12518 /* 34791 */ // Label 766: @34791
12519 /* 34791 */ GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(34828), // Rule ID 3241 //
12520 /* 34796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12521 /* 34799 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12522 /* 34802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12523 /* 34806 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12524 /* 34810 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)
12525 /* 34810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12526 /* 34813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12527 /* 34815 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12528 /* 34817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12529 /* 34820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12530 /* 34826 */ GIR_RootConstrainSelectedInstOperands,
12531 /* 34827 */ // GIR_Coverage, 3241,
12532 /* 34827 */ GIR_EraseRootFromParent_Done,
12533 /* 34828 */ // Label 767: @34828
12534 /* 34828 */ GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(34865), // Rule ID 3242 //
12535 /* 34833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12536 /* 34836 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12537 /* 34839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12538 /* 34843 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12539 /* 34847 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)
12540 /* 34847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12541 /* 34850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12542 /* 34852 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12543 /* 34854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12544 /* 34857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12545 /* 34863 */ GIR_RootConstrainSelectedInstOperands,
12546 /* 34864 */ // GIR_Coverage, 3242,
12547 /* 34864 */ GIR_EraseRootFromParent_Done,
12548 /* 34865 */ // Label 768: @34865
12549 /* 34865 */ GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(34902), // Rule ID 3243 //
12550 /* 34870 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12551 /* 34873 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12552 /* 34876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12553 /* 34880 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12554 /* 34884 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)
12555 /* 34884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12556 /* 34887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12557 /* 34889 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12558 /* 34891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12559 /* 34894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12560 /* 34900 */ GIR_RootConstrainSelectedInstOperands,
12561 /* 34901 */ // GIR_Coverage, 3243,
12562 /* 34901 */ GIR_EraseRootFromParent_Done,
12563 /* 34902 */ // Label 769: @34902
12564 /* 34902 */ GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(34939), // Rule ID 3244 //
12565 /* 34907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12566 /* 34910 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12567 /* 34913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12568 /* 34917 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12569 /* 34921 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)
12570 /* 34921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
12571 /* 34924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12572 /* 34926 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12573 /* 34928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12574 /* 34931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12575 /* 34937 */ GIR_RootConstrainSelectedInstOperands,
12576 /* 34938 */ // GIR_Coverage, 3244,
12577 /* 34938 */ GIR_EraseRootFromParent_Done,
12578 /* 34939 */ // Label 770: @34939
12579 /* 34939 */ GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(34971), // Rule ID 5802 //
12580 /* 34944 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
12581 /* 34947 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12582 /* 34950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12583 /* 34954 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12584 /* 34958 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v8i16] }:$src
12585 /* 34958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12586 /* 34961 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12587 /* 34963 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12588 /* 34965 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12589 /* 34970 */ // GIR_Coverage, 5802,
12590 /* 34970 */ GIR_EraseRootFromParent_Done,
12591 /* 34971 */ // Label 771: @34971
12592 /* 34971 */ GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(35003), // Rule ID 5803 //
12593 /* 34976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
12594 /* 34979 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12595 /* 34982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12596 /* 34986 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12597 /* 34990 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v8f16] }:$src
12598 /* 34990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12599 /* 34993 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12600 /* 34995 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12601 /* 34997 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12602 /* 35002 */ // GIR_Coverage, 5803,
12603 /* 35002 */ GIR_EraseRootFromParent_Done,
12604 /* 35003 */ // Label 772: @35003
12605 /* 35003 */ GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(35035), // Rule ID 5824 //
12606 /* 35008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12607 /* 35011 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12608 /* 35014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12609 /* 35018 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12610 /* 35022 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8f16] }:$src
12611 /* 35022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12612 /* 35025 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12613 /* 35027 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12614 /* 35029 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12615 /* 35034 */ // GIR_Coverage, 5824,
12616 /* 35034 */ GIR_EraseRootFromParent_Done,
12617 /* 35035 */ // Label 773: @35035
12618 /* 35035 */ GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(35067), // Rule ID 5825 //
12619 /* 35040 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12620 /* 35043 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12621 /* 35046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12622 /* 35050 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12623 /* 35054 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8f16] }:$src
12624 /* 35054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12625 /* 35057 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12626 /* 35059 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12627 /* 35061 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12628 /* 35066 */ // GIR_Coverage, 5825,
12629 /* 35066 */ GIR_EraseRootFromParent_Done,
12630 /* 35067 */ // Label 774: @35067
12631 /* 35067 */ GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(35099), // Rule ID 5826 //
12632 /* 35072 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12633 /* 35075 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12634 /* 35078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12635 /* 35082 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12636 /* 35086 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8f16] }:$src
12637 /* 35086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12638 /* 35089 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12639 /* 35091 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12640 /* 35093 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12641 /* 35098 */ // GIR_Coverage, 5826,
12642 /* 35098 */ GIR_EraseRootFromParent_Done,
12643 /* 35099 */ // Label 775: @35099
12644 /* 35099 */ GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(35131), // Rule ID 5827 //
12645 /* 35104 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12646 /* 35107 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12647 /* 35110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12648 /* 35114 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12649 /* 35118 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8f16] }:$src
12650 /* 35118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12651 /* 35121 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12652 /* 35123 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12653 /* 35125 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12654 /* 35130 */ // GIR_Coverage, 5827,
12655 /* 35130 */ GIR_EraseRootFromParent_Done,
12656 /* 35131 */ // Label 776: @35131
12657 /* 35131 */ GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(35163), // Rule ID 5828 //
12658 /* 35136 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12659 /* 35139 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12660 /* 35142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12661 /* 35146 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12662 /* 35150 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8f16] }:$src
12663 /* 35150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12664 /* 35153 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12665 /* 35155 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12666 /* 35157 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12667 /* 35162 */ // GIR_Coverage, 5828,
12668 /* 35162 */ GIR_EraseRootFromParent_Done,
12669 /* 35163 */ // Label 777: @35163
12670 /* 35163 */ GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(35195), // Rule ID 5829 //
12671 /* 35168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12672 /* 35171 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12673 /* 35174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12674 /* 35178 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12675 /* 35182 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8i16] }:$src
12676 /* 35182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12677 /* 35185 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12678 /* 35187 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12679 /* 35189 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12680 /* 35194 */ // GIR_Coverage, 5829,
12681 /* 35194 */ GIR_EraseRootFromParent_Done,
12682 /* 35195 */ // Label 778: @35195
12683 /* 35195 */ GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(35227), // Rule ID 5830 //
12684 /* 35200 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12685 /* 35203 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12686 /* 35206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12687 /* 35210 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12688 /* 35214 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8i16] }:$src
12689 /* 35214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12690 /* 35217 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12691 /* 35219 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12692 /* 35221 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12693 /* 35226 */ // GIR_Coverage, 5830,
12694 /* 35226 */ GIR_EraseRootFromParent_Done,
12695 /* 35227 */ // Label 779: @35227
12696 /* 35227 */ GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(35259), // Rule ID 5831 //
12697 /* 35232 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12698 /* 35235 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12699 /* 35238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12700 /* 35242 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12701 /* 35246 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8i16] }:$src
12702 /* 35246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12703 /* 35249 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12704 /* 35251 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12705 /* 35253 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12706 /* 35258 */ // GIR_Coverage, 5831,
12707 /* 35258 */ GIR_EraseRootFromParent_Done,
12708 /* 35259 */ // Label 780: @35259
12709 /* 35259 */ GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(35291), // Rule ID 5832 //
12710 /* 35264 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12711 /* 35267 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12712 /* 35270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12713 /* 35274 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12714 /* 35278 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8i16] }:$src
12715 /* 35278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12716 /* 35281 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12717 /* 35283 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12718 /* 35285 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12719 /* 35290 */ // GIR_Coverage, 5832,
12720 /* 35290 */ GIR_EraseRootFromParent_Done,
12721 /* 35291 */ // Label 781: @35291
12722 /* 35291 */ GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(35323), // Rule ID 5833 //
12723 /* 35296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12724 /* 35299 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12725 /* 35302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12726 /* 35306 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12727 /* 35310 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8i16] }:$src
12728 /* 35310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12729 /* 35313 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12730 /* 35315 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12731 /* 35317 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12732 /* 35322 */ // GIR_Coverage, 5833,
12733 /* 35322 */ GIR_EraseRootFromParent_Done,
12734 /* 35323 */ // Label 782: @35323
12735 /* 35323 */ GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(35381), // Rule ID 5860 //
12736 /* 35328 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12737 /* 35331 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12738 /* 35334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12739 /* 35338 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12740 /* 35342 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src)
12741 /* 35342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12742 /* 35345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12743 /* 35349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12744 /* 35354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12745 /* 35357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12746 /* 35359 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12747 /* 35361 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12748 /* 35364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12749 /* 35370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12750 /* 35376 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12751 /* 35379 */ GIR_RootConstrainSelectedInstOperands,
12752 /* 35380 */ // GIR_Coverage, 5860,
12753 /* 35380 */ GIR_EraseRootFromParent_Done,
12754 /* 35381 */ // Label 783: @35381
12755 /* 35381 */ GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(35439), // Rule ID 5861 //
12756 /* 35386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12757 /* 35389 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12758 /* 35392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12759 /* 35396 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12760 /* 35400 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src)
12761 /* 35400 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12762 /* 35403 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12763 /* 35407 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12764 /* 35412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12765 /* 35415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12766 /* 35417 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12767 /* 35419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12768 /* 35422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12769 /* 35428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12770 /* 35434 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12771 /* 35437 */ GIR_RootConstrainSelectedInstOperands,
12772 /* 35438 */ // GIR_Coverage, 5861,
12773 /* 35438 */ GIR_EraseRootFromParent_Done,
12774 /* 35439 */ // Label 784: @35439
12775 /* 35439 */ GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(35497), // Rule ID 5862 //
12776 /* 35444 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12777 /* 35447 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12778 /* 35450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12779 /* 35454 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12780 /* 35458 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src)
12781 /* 35458 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12782 /* 35461 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12783 /* 35465 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12784 /* 35470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12785 /* 35473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12786 /* 35475 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12787 /* 35477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12788 /* 35480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12789 /* 35486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12790 /* 35492 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12791 /* 35495 */ GIR_RootConstrainSelectedInstOperands,
12792 /* 35496 */ // GIR_Coverage, 5862,
12793 /* 35496 */ GIR_EraseRootFromParent_Done,
12794 /* 35497 */ // Label 785: @35497
12795 /* 35497 */ GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(35555), // Rule ID 5863 //
12796 /* 35502 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12797 /* 35505 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12798 /* 35508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12799 /* 35512 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12800 /* 35516 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src)
12801 /* 35516 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12802 /* 35519 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12803 /* 35523 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12804 /* 35528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12805 /* 35531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12806 /* 35533 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12807 /* 35535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12808 /* 35538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12809 /* 35544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12810 /* 35550 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12811 /* 35553 */ GIR_RootConstrainSelectedInstOperands,
12812 /* 35554 */ // GIR_Coverage, 5863,
12813 /* 35554 */ GIR_EraseRootFromParent_Done,
12814 /* 35555 */ // Label 786: @35555
12815 /* 35555 */ GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(35613), // Rule ID 5864 //
12816 /* 35560 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12817 /* 35563 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12818 /* 35566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12819 /* 35570 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12820 /* 35574 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src)
12821 /* 35574 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12822 /* 35577 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12823 /* 35581 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12824 /* 35586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
12825 /* 35589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12826 /* 35591 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12827 /* 35593 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12828 /* 35596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12829 /* 35602 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12830 /* 35608 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12831 /* 35611 */ GIR_RootConstrainSelectedInstOperands,
12832 /* 35612 */ // GIR_Coverage, 5864,
12833 /* 35612 */ GIR_EraseRootFromParent_Done,
12834 /* 35613 */ // Label 787: @35613
12835 /* 35613 */ GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(35671), // Rule ID 5865 //
12836 /* 35618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12837 /* 35621 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12838 /* 35624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12839 /* 35628 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12840 /* 35632 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src)
12841 /* 35632 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12842 /* 35635 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12843 /* 35639 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12844 /* 35644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12845 /* 35647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12846 /* 35649 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12847 /* 35651 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12848 /* 35654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12849 /* 35660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12850 /* 35666 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12851 /* 35669 */ GIR_RootConstrainSelectedInstOperands,
12852 /* 35670 */ // GIR_Coverage, 5865,
12853 /* 35670 */ GIR_EraseRootFromParent_Done,
12854 /* 35671 */ // Label 788: @35671
12855 /* 35671 */ GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(35729), // Rule ID 5866 //
12856 /* 35676 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12857 /* 35679 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12858 /* 35682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12859 /* 35686 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12860 /* 35690 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src)
12861 /* 35690 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12862 /* 35693 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12863 /* 35697 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12864 /* 35702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12865 /* 35705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12866 /* 35707 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12867 /* 35709 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12868 /* 35712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12869 /* 35718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12870 /* 35724 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12871 /* 35727 */ GIR_RootConstrainSelectedInstOperands,
12872 /* 35728 */ // GIR_Coverage, 5866,
12873 /* 35728 */ GIR_EraseRootFromParent_Done,
12874 /* 35729 */ // Label 789: @35729
12875 /* 35729 */ GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(35787), // Rule ID 5867 //
12876 /* 35734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12877 /* 35737 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12878 /* 35740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12879 /* 35744 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12880 /* 35748 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src)
12881 /* 35748 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12882 /* 35751 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12883 /* 35755 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12884 /* 35760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12885 /* 35763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12886 /* 35765 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12887 /* 35767 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12888 /* 35770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12889 /* 35776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12890 /* 35782 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12891 /* 35785 */ GIR_RootConstrainSelectedInstOperands,
12892 /* 35786 */ // GIR_Coverage, 5867,
12893 /* 35786 */ GIR_EraseRootFromParent_Done,
12894 /* 35787 */ // Label 790: @35787
12895 /* 35787 */ GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(35845), // Rule ID 5868 //
12896 /* 35792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12897 /* 35795 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12898 /* 35798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12899 /* 35802 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12900 /* 35806 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src)
12901 /* 35806 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12902 /* 35809 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12903 /* 35813 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12904 /* 35818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12905 /* 35821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12906 /* 35823 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12907 /* 35825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12908 /* 35828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12909 /* 35834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12910 /* 35840 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12911 /* 35843 */ GIR_RootConstrainSelectedInstOperands,
12912 /* 35844 */ // GIR_Coverage, 5868,
12913 /* 35844 */ GIR_EraseRootFromParent_Done,
12914 /* 35845 */ // Label 791: @35845
12915 /* 35845 */ GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(35903), // Rule ID 5869 //
12916 /* 35850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12917 /* 35853 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12918 /* 35856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12919 /* 35860 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12920 /* 35864 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
12921 /* 35864 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12922 /* 35867 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12923 /* 35871 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12924 /* 35876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
12925 /* 35879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12926 /* 35881 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12927 /* 35883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12928 /* 35886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12929 /* 35892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12930 /* 35898 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12931 /* 35901 */ GIR_RootConstrainSelectedInstOperands,
12932 /* 35902 */ // GIR_Coverage, 5869,
12933 /* 35902 */ GIR_EraseRootFromParent_Done,
12934 /* 35903 */ // Label 792: @35903
12935 /* 35903 */ GIM_Reject,
12936 /* 35904 */ // Label 661: @35904
12937 /* 35904 */ GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(35936), // Rule ID 3097 //
12938 /* 35909 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12939 /* 35912 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12940 /* 35915 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12941 /* 35919 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12942 /* 35923 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v2f32] }:$src
12943 /* 35923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12944 /* 35926 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12945 /* 35928 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12946 /* 35930 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12947 /* 35935 */ // GIR_Coverage, 3097,
12948 /* 35935 */ GIR_EraseRootFromParent_Done,
12949 /* 35936 */ // Label 793: @35936
12950 /* 35936 */ GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(35968), // Rule ID 3098 //
12951 /* 35941 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12952 /* 35944 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12953 /* 35947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12954 /* 35951 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12955 /* 35955 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v2i32] }:$src
12956 /* 35955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12957 /* 35958 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12958 /* 35960 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12959 /* 35962 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12960 /* 35967 */ // GIR_Coverage, 3098,
12961 /* 35967 */ GIR_EraseRootFromParent_Done,
12962 /* 35968 */ // Label 794: @35968
12963 /* 35968 */ GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(36000), // Rule ID 3117 //
12964 /* 35973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12965 /* 35976 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12966 /* 35979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12967 /* 35983 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12968 /* 35987 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2f32] }:$src
12969 /* 35987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12970 /* 35990 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12971 /* 35992 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12972 /* 35994 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12973 /* 35999 */ // GIR_Coverage, 3117,
12974 /* 35999 */ GIR_EraseRootFromParent_Done,
12975 /* 36000 */ // Label 795: @36000
12976 /* 36000 */ GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(36032), // Rule ID 3118 //
12977 /* 36005 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12978 /* 36008 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12979 /* 36011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12980 /* 36015 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12981 /* 36019 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2f32] }:$src
12982 /* 36019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12983 /* 36022 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12984 /* 36024 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12985 /* 36026 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12986 /* 36031 */ // GIR_Coverage, 3118,
12987 /* 36031 */ GIR_EraseRootFromParent_Done,
12988 /* 36032 */ // Label 796: @36032
12989 /* 36032 */ GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(36064), // Rule ID 3119 //
12990 /* 36037 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12991 /* 36040 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
12992 /* 36043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12993 /* 36047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12994 /* 36051 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2f32] }:$src
12995 /* 36051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12996 /* 36054 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12997 /* 36056 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12998 /* 36058 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12999 /* 36063 */ // GIR_Coverage, 3119,
13000 /* 36063 */ GIR_EraseRootFromParent_Done,
13001 /* 36064 */ // Label 797: @36064
13002 /* 36064 */ GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(36096), // Rule ID 3120 //
13003 /* 36069 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13004 /* 36072 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13005 /* 36075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13006 /* 36079 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13007 /* 36083 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2f32] }:$src
13008 /* 36083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13009 /* 36086 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13010 /* 36088 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13011 /* 36090 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
13012 /* 36095 */ // GIR_Coverage, 3120,
13013 /* 36095 */ GIR_EraseRootFromParent_Done,
13014 /* 36096 */ // Label 798: @36096
13015 /* 36096 */ GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(36128), // Rule ID 3121 //
13016 /* 36101 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13017 /* 36104 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
13018 /* 36107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13019 /* 36111 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13020 /* 36115 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2f32] }:$src
13021 /* 36115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13022 /* 36118 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13023 /* 36120 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13024 /* 36122 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
13025 /* 36127 */ // GIR_Coverage, 3121,
13026 /* 36127 */ GIR_EraseRootFromParent_Done,
13027 /* 36128 */ // Label 799: @36128
13028 /* 36128 */ GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(36160), // Rule ID 3122 //
13029 /* 36133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13030 /* 36136 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13031 /* 36139 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13032 /* 36143 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13033 /* 36147 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2i32] }:$src
13034 /* 36147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13035 /* 36150 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13036 /* 36152 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13037 /* 36154 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
13038 /* 36159 */ // GIR_Coverage, 3122,
13039 /* 36159 */ GIR_EraseRootFromParent_Done,
13040 /* 36160 */ // Label 800: @36160
13041 /* 36160 */ GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(36192), // Rule ID 3123 //
13042 /* 36165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13043 /* 36168 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13044 /* 36171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13045 /* 36175 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13046 /* 36179 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2i32] }:$src
13047 /* 36179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13048 /* 36182 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13049 /* 36184 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13050 /* 36186 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
13051 /* 36191 */ // GIR_Coverage, 3123,
13052 /* 36191 */ GIR_EraseRootFromParent_Done,
13053 /* 36192 */ // Label 801: @36192
13054 /* 36192 */ GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(36224), // Rule ID 3124 //
13055 /* 36197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13056 /* 36200 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13057 /* 36203 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13058 /* 36207 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13059 /* 36211 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2i32] }:$src
13060 /* 36211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13061 /* 36214 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13062 /* 36216 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13063 /* 36218 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
13064 /* 36223 */ // GIR_Coverage, 3124,
13065 /* 36223 */ GIR_EraseRootFromParent_Done,
13066 /* 36224 */ // Label 802: @36224
13067 /* 36224 */ GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(36256), // Rule ID 3125 //
13068 /* 36229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13069 /* 36232 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13070 /* 36235 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13071 /* 36239 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13072 /* 36243 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2i32] }:$src
13073 /* 36243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13074 /* 36246 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13075 /* 36248 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13076 /* 36250 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
13077 /* 36255 */ // GIR_Coverage, 3125,
13078 /* 36255 */ GIR_EraseRootFromParent_Done,
13079 /* 36256 */ // Label 803: @36256
13080 /* 36256 */ GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(36288), // Rule ID 3126 //
13081 /* 36261 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13082 /* 36264 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
13083 /* 36267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13084 /* 36271 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13085 /* 36275 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2i32] }:$src
13086 /* 36275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13087 /* 36278 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13088 /* 36280 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13089 /* 36282 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
13090 /* 36287 */ // GIR_Coverage, 3126,
13091 /* 36287 */ GIR_EraseRootFromParent_Done,
13092 /* 36288 */ // Label 804: @36288
13093 /* 36288 */ GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(36325), // Rule ID 3189 //
13094 /* 36293 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13095 /* 36296 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13096 /* 36299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13097 /* 36303 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13098 /* 36307 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src)
13099 /* 36307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
13100 /* 36310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13101 /* 36312 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13102 /* 36314 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13103 /* 36317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13104 /* 36323 */ GIR_RootConstrainSelectedInstOperands,
13105 /* 36324 */ // GIR_Coverage, 3189,
13106 /* 36324 */ GIR_EraseRootFromParent_Done,
13107 /* 36325 */ // Label 805: @36325
13108 /* 36325 */ GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(36362), // Rule ID 3190 //
13109 /* 36330 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13110 /* 36333 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13111 /* 36336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13112 /* 36340 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13113 /* 36344 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)
13114 /* 36344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
13115 /* 36347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13116 /* 36349 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13117 /* 36351 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13118 /* 36354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13119 /* 36360 */ GIR_RootConstrainSelectedInstOperands,
13120 /* 36361 */ // GIR_Coverage, 3190,
13121 /* 36361 */ GIR_EraseRootFromParent_Done,
13122 /* 36362 */ // Label 806: @36362
13123 /* 36362 */ GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(36399), // Rule ID 3191 //
13124 /* 36367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13125 /* 36370 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13126 /* 36373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13127 /* 36377 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13128 /* 36381 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src)
13129 /* 36381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
13130 /* 36384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13131 /* 36386 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13132 /* 36388 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13133 /* 36391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13134 /* 36397 */ GIR_RootConstrainSelectedInstOperands,
13135 /* 36398 */ // GIR_Coverage, 3191,
13136 /* 36398 */ GIR_EraseRootFromParent_Done,
13137 /* 36399 */ // Label 807: @36399
13138 /* 36399 */ GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(36436), // Rule ID 3192 //
13139 /* 36404 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13140 /* 36407 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13141 /* 36410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13142 /* 36414 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13143 /* 36418 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)
13144 /* 36418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
13145 /* 36421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13146 /* 36423 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13147 /* 36425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13148 /* 36428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13149 /* 36434 */ GIR_RootConstrainSelectedInstOperands,
13150 /* 36435 */ // GIR_Coverage, 3192,
13151 /* 36435 */ GIR_EraseRootFromParent_Done,
13152 /* 36436 */ // Label 808: @36436
13153 /* 36436 */ GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(36473), // Rule ID 3193 //
13154 /* 36441 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13155 /* 36444 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
13156 /* 36447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13157 /* 36451 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13158 /* 36455 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)
13159 /* 36455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
13160 /* 36458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13161 /* 36460 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13162 /* 36462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13163 /* 36465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13164 /* 36471 */ GIR_RootConstrainSelectedInstOperands,
13165 /* 36472 */ // GIR_Coverage, 3193,
13166 /* 36472 */ GIR_EraseRootFromParent_Done,
13167 /* 36473 */ // Label 809: @36473
13168 /* 36473 */ GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(36510), // Rule ID 3194 //
13169 /* 36478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13170 /* 36481 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13171 /* 36484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13172 /* 36488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13173 /* 36492 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src)
13174 /* 36492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
13175 /* 36495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13176 /* 36497 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13177 /* 36499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13178 /* 36502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13179 /* 36508 */ GIR_RootConstrainSelectedInstOperands,
13180 /* 36509 */ // GIR_Coverage, 3194,
13181 /* 36509 */ GIR_EraseRootFromParent_Done,
13182 /* 36510 */ // Label 810: @36510
13183 /* 36510 */ GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(36547), // Rule ID 3195 //
13184 /* 36515 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13185 /* 36518 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13186 /* 36521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13187 /* 36525 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13188 /* 36529 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)
13189 /* 36529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
13190 /* 36532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13191 /* 36534 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13192 /* 36536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13193 /* 36539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13194 /* 36545 */ GIR_RootConstrainSelectedInstOperands,
13195 /* 36546 */ // GIR_Coverage, 3195,
13196 /* 36546 */ GIR_EraseRootFromParent_Done,
13197 /* 36547 */ // Label 811: @36547
13198 /* 36547 */ GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(36584), // Rule ID 3196 //
13199 /* 36552 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13200 /* 36555 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13201 /* 36558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13202 /* 36562 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13203 /* 36566 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src)
13204 /* 36566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
13205 /* 36569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13206 /* 36571 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13207 /* 36573 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13208 /* 36576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13209 /* 36582 */ GIR_RootConstrainSelectedInstOperands,
13210 /* 36583 */ // GIR_Coverage, 3196,
13211 /* 36583 */ GIR_EraseRootFromParent_Done,
13212 /* 36584 */ // Label 812: @36584
13213 /* 36584 */ GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(36621), // Rule ID 3197 //
13214 /* 36589 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13215 /* 36592 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13216 /* 36595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13217 /* 36599 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13218 /* 36603 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)
13219 /* 36603 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
13220 /* 36606 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13221 /* 36608 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13222 /* 36610 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13223 /* 36613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13224 /* 36619 */ GIR_RootConstrainSelectedInstOperands,
13225 /* 36620 */ // GIR_Coverage, 3197,
13226 /* 36620 */ GIR_EraseRootFromParent_Done,
13227 /* 36621 */ // Label 813: @36621
13228 /* 36621 */ GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(36658), // Rule ID 3198 //
13229 /* 36626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13230 /* 36629 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
13231 /* 36632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13232 /* 36636 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13233 /* 36640 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)
13234 /* 36640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
13235 /* 36643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13236 /* 36645 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13237 /* 36647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13238 /* 36650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13239 /* 36656 */ GIR_RootConstrainSelectedInstOperands,
13240 /* 36657 */ // GIR_Coverage, 3198,
13241 /* 36657 */ GIR_EraseRootFromParent_Done,
13242 /* 36658 */ // Label 814: @36658
13243 /* 36658 */ GIM_Reject,
13244 /* 36659 */ // Label 662: @36659
13245 /* 36659 */ GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(36691), // Rule ID 3103 //
13246 /* 36664 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13247 /* 36667 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13248 /* 36670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13249 /* 36674 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13250 /* 36678 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v4i32] }:$src
13251 /* 36678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13252 /* 36681 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13253 /* 36683 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13254 /* 36685 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13255 /* 36690 */ // GIR_Coverage, 3103,
13256 /* 36690 */ GIR_EraseRootFromParent_Done,
13257 /* 36691 */ // Label 815: @36691
13258 /* 36691 */ GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(36723), // Rule ID 3104 //
13259 /* 36696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13260 /* 36699 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13261 /* 36702 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13262 /* 36706 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13263 /* 36710 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v4f32] }:$src
13264 /* 36710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13265 /* 36713 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13266 /* 36715 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13267 /* 36717 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13268 /* 36722 */ // GIR_Coverage, 3104,
13269 /* 36722 */ GIR_EraseRootFromParent_Done,
13270 /* 36723 */ // Label 816: @36723
13271 /* 36723 */ GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(36755), // Rule ID 3153 //
13272 /* 36728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13273 /* 36731 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13274 /* 36734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13275 /* 36738 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13276 /* 36742 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4f32] }:$src
13277 /* 36742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13278 /* 36745 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13279 /* 36747 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13280 /* 36749 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13281 /* 36754 */ // GIR_Coverage, 3153,
13282 /* 36754 */ GIR_EraseRootFromParent_Done,
13283 /* 36755 */ // Label 817: @36755
13284 /* 36755 */ GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(36787), // Rule ID 3154 //
13285 /* 36760 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13286 /* 36763 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13287 /* 36766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13288 /* 36770 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13289 /* 36774 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4f32] }:$src
13290 /* 36774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13291 /* 36777 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13292 /* 36779 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13293 /* 36781 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13294 /* 36786 */ // GIR_Coverage, 3154,
13295 /* 36786 */ GIR_EraseRootFromParent_Done,
13296 /* 36787 */ // Label 818: @36787
13297 /* 36787 */ GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(36819), // Rule ID 3155 //
13298 /* 36792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13299 /* 36795 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13300 /* 36798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13301 /* 36802 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13302 /* 36806 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4f32] }:$src
13303 /* 36806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13304 /* 36809 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13305 /* 36811 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13306 /* 36813 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13307 /* 36818 */ // GIR_Coverage, 3155,
13308 /* 36818 */ GIR_EraseRootFromParent_Done,
13309 /* 36819 */ // Label 819: @36819
13310 /* 36819 */ GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(36851), // Rule ID 3156 //
13311 /* 36824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13312 /* 36827 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13313 /* 36830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13314 /* 36834 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13315 /* 36838 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4f32] }:$src
13316 /* 36838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13317 /* 36841 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13318 /* 36843 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13319 /* 36845 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13320 /* 36850 */ // GIR_Coverage, 3156,
13321 /* 36850 */ GIR_EraseRootFromParent_Done,
13322 /* 36851 */ // Label 820: @36851
13323 /* 36851 */ GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(36883), // Rule ID 3157 //
13324 /* 36856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13325 /* 36859 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13326 /* 36862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13327 /* 36866 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13328 /* 36870 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4f32] }:$src
13329 /* 36870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13330 /* 36873 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13331 /* 36875 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13332 /* 36877 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13333 /* 36882 */ // GIR_Coverage, 3157,
13334 /* 36882 */ GIR_EraseRootFromParent_Done,
13335 /* 36883 */ // Label 821: @36883
13336 /* 36883 */ GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(36915), // Rule ID 3158 //
13337 /* 36888 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13338 /* 36891 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13339 /* 36894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13340 /* 36898 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13341 /* 36902 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4i32] }:$src
13342 /* 36902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13343 /* 36905 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13344 /* 36907 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13345 /* 36909 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13346 /* 36914 */ // GIR_Coverage, 3158,
13347 /* 36914 */ GIR_EraseRootFromParent_Done,
13348 /* 36915 */ // Label 822: @36915
13349 /* 36915 */ GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(36947), // Rule ID 3159 //
13350 /* 36920 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13351 /* 36923 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13352 /* 36926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13353 /* 36930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13354 /* 36934 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4i32] }:$src
13355 /* 36934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13356 /* 36937 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13357 /* 36939 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13358 /* 36941 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13359 /* 36946 */ // GIR_Coverage, 3159,
13360 /* 36946 */ GIR_EraseRootFromParent_Done,
13361 /* 36947 */ // Label 823: @36947
13362 /* 36947 */ GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(36979), // Rule ID 3160 //
13363 /* 36952 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13364 /* 36955 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13365 /* 36958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13366 /* 36962 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13367 /* 36966 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4i32] }:$src
13368 /* 36966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13369 /* 36969 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13370 /* 36971 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13371 /* 36973 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13372 /* 36978 */ // GIR_Coverage, 3160,
13373 /* 36978 */ GIR_EraseRootFromParent_Done,
13374 /* 36979 */ // Label 824: @36979
13375 /* 36979 */ GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(37011), // Rule ID 3161 //
13376 /* 36984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13377 /* 36987 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13378 /* 36990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13379 /* 36994 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13380 /* 36998 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4i32] }:$src
13381 /* 36998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13382 /* 37001 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13383 /* 37003 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13384 /* 37005 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13385 /* 37010 */ // GIR_Coverage, 3161,
13386 /* 37010 */ GIR_EraseRootFromParent_Done,
13387 /* 37011 */ // Label 825: @37011
13388 /* 37011 */ GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(37043), // Rule ID 3162 //
13389 /* 37016 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13390 /* 37019 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13391 /* 37022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13392 /* 37026 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13393 /* 37030 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4i32] }:$src
13394 /* 37030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13395 /* 37033 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13396 /* 37035 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13397 /* 37037 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13398 /* 37042 */ // GIR_Coverage, 3162,
13399 /* 37042 */ GIR_EraseRootFromParent_Done,
13400 /* 37043 */ // Label 826: @37043
13401 /* 37043 */ GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(37080), // Rule ID 3225 //
13402 /* 37048 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13403 /* 37051 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13404 /* 37054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13405 /* 37058 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13406 /* 37062 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)
13407 /* 37062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
13408 /* 37065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13409 /* 37067 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13410 /* 37069 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13411 /* 37072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13412 /* 37078 */ GIR_RootConstrainSelectedInstOperands,
13413 /* 37079 */ // GIR_Coverage, 3225,
13414 /* 37079 */ GIR_EraseRootFromParent_Done,
13415 /* 37080 */ // Label 827: @37080
13416 /* 37080 */ GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(37117), // Rule ID 3226 //
13417 /* 37085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13418 /* 37088 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13419 /* 37091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13420 /* 37095 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13421 /* 37099 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)
13422 /* 37099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
13423 /* 37102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13424 /* 37104 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13425 /* 37106 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13426 /* 37109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13427 /* 37115 */ GIR_RootConstrainSelectedInstOperands,
13428 /* 37116 */ // GIR_Coverage, 3226,
13429 /* 37116 */ GIR_EraseRootFromParent_Done,
13430 /* 37117 */ // Label 828: @37117
13431 /* 37117 */ GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(37154), // Rule ID 3227 //
13432 /* 37122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13433 /* 37125 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13434 /* 37128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13435 /* 37132 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13436 /* 37136 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)
13437 /* 37136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
13438 /* 37139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13439 /* 37141 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13440 /* 37143 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13441 /* 37146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13442 /* 37152 */ GIR_RootConstrainSelectedInstOperands,
13443 /* 37153 */ // GIR_Coverage, 3227,
13444 /* 37153 */ GIR_EraseRootFromParent_Done,
13445 /* 37154 */ // Label 829: @37154
13446 /* 37154 */ GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(37191), // Rule ID 3228 //
13447 /* 37159 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13448 /* 37162 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13449 /* 37165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13450 /* 37169 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13451 /* 37173 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)
13452 /* 37173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
13453 /* 37176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13454 /* 37178 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13455 /* 37180 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13456 /* 37183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13457 /* 37189 */ GIR_RootConstrainSelectedInstOperands,
13458 /* 37190 */ // GIR_Coverage, 3228,
13459 /* 37190 */ GIR_EraseRootFromParent_Done,
13460 /* 37191 */ // Label 830: @37191
13461 /* 37191 */ GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(37228), // Rule ID 3229 //
13462 /* 37196 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13463 /* 37199 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13464 /* 37202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13465 /* 37206 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13466 /* 37210 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)
13467 /* 37210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
13468 /* 37213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13469 /* 37215 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13470 /* 37217 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13471 /* 37220 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13472 /* 37226 */ GIR_RootConstrainSelectedInstOperands,
13473 /* 37227 */ // GIR_Coverage, 3229,
13474 /* 37227 */ GIR_EraseRootFromParent_Done,
13475 /* 37228 */ // Label 831: @37228
13476 /* 37228 */ GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(37265), // Rule ID 3230 //
13477 /* 37233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13478 /* 37236 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13479 /* 37239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13480 /* 37243 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13481 /* 37247 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)
13482 /* 37247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
13483 /* 37250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13484 /* 37252 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13485 /* 37254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13486 /* 37257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13487 /* 37263 */ GIR_RootConstrainSelectedInstOperands,
13488 /* 37264 */ // GIR_Coverage, 3230,
13489 /* 37264 */ GIR_EraseRootFromParent_Done,
13490 /* 37265 */ // Label 832: @37265
13491 /* 37265 */ GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(37302), // Rule ID 3231 //
13492 /* 37270 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13493 /* 37273 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13494 /* 37276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13495 /* 37280 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13496 /* 37284 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)
13497 /* 37284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
13498 /* 37287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13499 /* 37289 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13500 /* 37291 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13501 /* 37294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13502 /* 37300 */ GIR_RootConstrainSelectedInstOperands,
13503 /* 37301 */ // GIR_Coverage, 3231,
13504 /* 37301 */ GIR_EraseRootFromParent_Done,
13505 /* 37302 */ // Label 833: @37302
13506 /* 37302 */ GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(37339), // Rule ID 3232 //
13507 /* 37307 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13508 /* 37310 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13509 /* 37313 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13510 /* 37317 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13511 /* 37321 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src)
13512 /* 37321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
13513 /* 37324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13514 /* 37326 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13515 /* 37328 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13516 /* 37331 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13517 /* 37337 */ GIR_RootConstrainSelectedInstOperands,
13518 /* 37338 */ // GIR_Coverage, 3232,
13519 /* 37338 */ GIR_EraseRootFromParent_Done,
13520 /* 37339 */ // Label 834: @37339
13521 /* 37339 */ GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(37376), // Rule ID 3233 //
13522 /* 37344 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13523 /* 37347 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13524 /* 37350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13525 /* 37354 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13526 /* 37358 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)
13527 /* 37358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
13528 /* 37361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13529 /* 37363 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13530 /* 37365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13531 /* 37368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13532 /* 37374 */ GIR_RootConstrainSelectedInstOperands,
13533 /* 37375 */ // GIR_Coverage, 3233,
13534 /* 37375 */ GIR_EraseRootFromParent_Done,
13535 /* 37376 */ // Label 835: @37376
13536 /* 37376 */ GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(37413), // Rule ID 3234 //
13537 /* 37381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13538 /* 37384 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13539 /* 37387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13540 /* 37391 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13541 /* 37395 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)
13542 /* 37395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
13543 /* 37398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13544 /* 37400 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13545 /* 37402 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13546 /* 37405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13547 /* 37411 */ GIR_RootConstrainSelectedInstOperands,
13548 /* 37412 */ // GIR_Coverage, 3234,
13549 /* 37412 */ GIR_EraseRootFromParent_Done,
13550 /* 37413 */ // Label 836: @37413
13551 /* 37413 */ GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(37445), // Rule ID 5800 //
13552 /* 37418 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
13553 /* 37421 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13554 /* 37424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13555 /* 37428 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13556 /* 37432 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v4i32] }:$src
13557 /* 37432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13558 /* 37435 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13559 /* 37437 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13560 /* 37439 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13561 /* 37444 */ // GIR_Coverage, 5800,
13562 /* 37444 */ GIR_EraseRootFromParent_Done,
13563 /* 37445 */ // Label 837: @37445
13564 /* 37445 */ GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(37477), // Rule ID 5801 //
13565 /* 37450 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
13566 /* 37453 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13567 /* 37456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13568 /* 37460 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13569 /* 37464 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v4f32] }:$src
13570 /* 37464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13571 /* 37467 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13572 /* 37469 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13573 /* 37471 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13574 /* 37476 */ // GIR_Coverage, 5801,
13575 /* 37476 */ GIR_EraseRootFromParent_Done,
13576 /* 37477 */ // Label 838: @37477
13577 /* 37477 */ GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(37509), // Rule ID 5814 //
13578 /* 37482 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13579 /* 37485 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13580 /* 37488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13581 /* 37492 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13582 /* 37496 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4f32] }:$src
13583 /* 37496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13584 /* 37499 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13585 /* 37501 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13586 /* 37503 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13587 /* 37508 */ // GIR_Coverage, 5814,
13588 /* 37508 */ GIR_EraseRootFromParent_Done,
13589 /* 37509 */ // Label 839: @37509
13590 /* 37509 */ GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(37541), // Rule ID 5815 //
13591 /* 37514 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13592 /* 37517 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13593 /* 37520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13594 /* 37524 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13595 /* 37528 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4f32] }:$src
13596 /* 37528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13597 /* 37531 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13598 /* 37533 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13599 /* 37535 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13600 /* 37540 */ // GIR_Coverage, 5815,
13601 /* 37540 */ GIR_EraseRootFromParent_Done,
13602 /* 37541 */ // Label 840: @37541
13603 /* 37541 */ GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(37573), // Rule ID 5816 //
13604 /* 37546 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13605 /* 37549 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13606 /* 37552 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13607 /* 37556 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13608 /* 37560 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4f32] }:$src
13609 /* 37560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13610 /* 37563 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13611 /* 37565 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13612 /* 37567 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13613 /* 37572 */ // GIR_Coverage, 5816,
13614 /* 37572 */ GIR_EraseRootFromParent_Done,
13615 /* 37573 */ // Label 841: @37573
13616 /* 37573 */ GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(37605), // Rule ID 5817 //
13617 /* 37578 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13618 /* 37581 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13619 /* 37584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13620 /* 37588 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13621 /* 37592 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4f32] }:$src
13622 /* 37592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13623 /* 37595 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13624 /* 37597 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13625 /* 37599 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13626 /* 37604 */ // GIR_Coverage, 5817,
13627 /* 37604 */ GIR_EraseRootFromParent_Done,
13628 /* 37605 */ // Label 842: @37605
13629 /* 37605 */ GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(37637), // Rule ID 5818 //
13630 /* 37610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13631 /* 37613 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13632 /* 37616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13633 /* 37620 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13634 /* 37624 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4f32] }:$src
13635 /* 37624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13636 /* 37627 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13637 /* 37629 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13638 /* 37631 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13639 /* 37636 */ // GIR_Coverage, 5818,
13640 /* 37636 */ GIR_EraseRootFromParent_Done,
13641 /* 37637 */ // Label 843: @37637
13642 /* 37637 */ GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(37669), // Rule ID 5819 //
13643 /* 37642 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13644 /* 37645 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13645 /* 37648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13646 /* 37652 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13647 /* 37656 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4i32] }:$src
13648 /* 37656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13649 /* 37659 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13650 /* 37661 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13651 /* 37663 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13652 /* 37668 */ // GIR_Coverage, 5819,
13653 /* 37668 */ GIR_EraseRootFromParent_Done,
13654 /* 37669 */ // Label 844: @37669
13655 /* 37669 */ GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(37701), // Rule ID 5820 //
13656 /* 37674 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13657 /* 37677 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13658 /* 37680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13659 /* 37684 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13660 /* 37688 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4i32] }:$src
13661 /* 37688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13662 /* 37691 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13663 /* 37693 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13664 /* 37695 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13665 /* 37700 */ // GIR_Coverage, 5820,
13666 /* 37700 */ GIR_EraseRootFromParent_Done,
13667 /* 37701 */ // Label 845: @37701
13668 /* 37701 */ GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(37733), // Rule ID 5821 //
13669 /* 37706 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13670 /* 37709 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13671 /* 37712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13672 /* 37716 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13673 /* 37720 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4i32] }:$src
13674 /* 37720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13675 /* 37723 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13676 /* 37725 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13677 /* 37727 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13678 /* 37732 */ // GIR_Coverage, 5821,
13679 /* 37732 */ GIR_EraseRootFromParent_Done,
13680 /* 37733 */ // Label 846: @37733
13681 /* 37733 */ GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(37765), // Rule ID 5822 //
13682 /* 37738 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13683 /* 37741 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13684 /* 37744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13685 /* 37748 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13686 /* 37752 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4i32] }:$src
13687 /* 37752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13688 /* 37755 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13689 /* 37757 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13690 /* 37759 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13691 /* 37764 */ // GIR_Coverage, 5822,
13692 /* 37764 */ GIR_EraseRootFromParent_Done,
13693 /* 37765 */ // Label 847: @37765
13694 /* 37765 */ GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(37797), // Rule ID 5823 //
13695 /* 37770 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13696 /* 37773 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13697 /* 37776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13698 /* 37780 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13699 /* 37784 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4i32] }:$src
13700 /* 37784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13701 /* 37787 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13702 /* 37789 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13703 /* 37791 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13704 /* 37796 */ // GIR_Coverage, 5823,
13705 /* 37796 */ GIR_EraseRootFromParent_Done,
13706 /* 37797 */ // Label 848: @37797
13707 /* 37797 */ GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(37855), // Rule ID 5850 //
13708 /* 37802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13709 /* 37805 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13710 /* 37808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13711 /* 37812 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13712 /* 37816 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src)
13713 /* 37816 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13714 /* 37819 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13715 /* 37823 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13716 /* 37828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13717 /* 37831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13718 /* 37833 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13719 /* 37835 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13720 /* 37838 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13721 /* 37844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13722 /* 37850 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13723 /* 37853 */ GIR_RootConstrainSelectedInstOperands,
13724 /* 37854 */ // GIR_Coverage, 5850,
13725 /* 37854 */ GIR_EraseRootFromParent_Done,
13726 /* 37855 */ // Label 849: @37855
13727 /* 37855 */ GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(37913), // Rule ID 5851 //
13728 /* 37860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13729 /* 37863 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13730 /* 37866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13731 /* 37870 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13732 /* 37874 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src)
13733 /* 37874 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13734 /* 37877 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13735 /* 37881 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13736 /* 37886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13737 /* 37889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13738 /* 37891 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13739 /* 37893 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13740 /* 37896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13741 /* 37902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13742 /* 37908 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13743 /* 37911 */ GIR_RootConstrainSelectedInstOperands,
13744 /* 37912 */ // GIR_Coverage, 5851,
13745 /* 37912 */ GIR_EraseRootFromParent_Done,
13746 /* 37913 */ // Label 850: @37913
13747 /* 37913 */ GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(37971), // Rule ID 5852 //
13748 /* 37918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13749 /* 37921 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13750 /* 37924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13751 /* 37928 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13752 /* 37932 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src)
13753 /* 37932 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13754 /* 37935 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13755 /* 37939 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13756 /* 37944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
13757 /* 37947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13758 /* 37949 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13759 /* 37951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13760 /* 37954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13761 /* 37960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13762 /* 37966 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13763 /* 37969 */ GIR_RootConstrainSelectedInstOperands,
13764 /* 37970 */ // GIR_Coverage, 5852,
13765 /* 37970 */ GIR_EraseRootFromParent_Done,
13766 /* 37971 */ // Label 851: @37971
13767 /* 37971 */ GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(38029), // Rule ID 5853 //
13768 /* 37976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13769 /* 37979 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13770 /* 37982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13771 /* 37986 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13772 /* 37990 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src)
13773 /* 37990 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13774 /* 37993 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13775 /* 37997 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13776 /* 38002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
13777 /* 38005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13778 /* 38007 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13779 /* 38009 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13780 /* 38012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13781 /* 38018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13782 /* 38024 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13783 /* 38027 */ GIR_RootConstrainSelectedInstOperands,
13784 /* 38028 */ // GIR_Coverage, 5853,
13785 /* 38028 */ GIR_EraseRootFromParent_Done,
13786 /* 38029 */ // Label 852: @38029
13787 /* 38029 */ GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(38087), // Rule ID 5854 //
13788 /* 38034 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13789 /* 38037 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13790 /* 38040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13791 /* 38044 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13792 /* 38048 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src)
13793 /* 38048 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13794 /* 38051 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13795 /* 38055 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13796 /* 38060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
13797 /* 38063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13798 /* 38065 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13799 /* 38067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13800 /* 38070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13801 /* 38076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13802 /* 38082 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13803 /* 38085 */ GIR_RootConstrainSelectedInstOperands,
13804 /* 38086 */ // GIR_Coverage, 5854,
13805 /* 38086 */ GIR_EraseRootFromParent_Done,
13806 /* 38087 */ // Label 853: @38087
13807 /* 38087 */ GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(38145), // Rule ID 5855 //
13808 /* 38092 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13809 /* 38095 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13810 /* 38098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13811 /* 38102 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13812 /* 38106 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src)
13813 /* 38106 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13814 /* 38109 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13815 /* 38113 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13816 /* 38118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13817 /* 38121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13818 /* 38123 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13819 /* 38125 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13820 /* 38128 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13821 /* 38134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13822 /* 38140 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13823 /* 38143 */ GIR_RootConstrainSelectedInstOperands,
13824 /* 38144 */ // GIR_Coverage, 5855,
13825 /* 38144 */ GIR_EraseRootFromParent_Done,
13826 /* 38145 */ // Label 854: @38145
13827 /* 38145 */ GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(38203), // Rule ID 5856 //
13828 /* 38150 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13829 /* 38153 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13830 /* 38156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13831 /* 38160 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13832 /* 38164 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src)
13833 /* 38164 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13834 /* 38167 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13835 /* 38171 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13836 /* 38176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13837 /* 38179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13838 /* 38181 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13839 /* 38183 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13840 /* 38186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13841 /* 38192 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13842 /* 38198 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13843 /* 38201 */ GIR_RootConstrainSelectedInstOperands,
13844 /* 38202 */ // GIR_Coverage, 5856,
13845 /* 38202 */ GIR_EraseRootFromParent_Done,
13846 /* 38203 */ // Label 855: @38203
13847 /* 38203 */ GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(38261), // Rule ID 5857 //
13848 /* 38208 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13849 /* 38211 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13850 /* 38214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13851 /* 38218 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13852 /* 38222 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src)
13853 /* 38222 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13854 /* 38225 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13855 /* 38229 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13856 /* 38234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
13857 /* 38237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13858 /* 38239 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13859 /* 38241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13860 /* 38244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13861 /* 38250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13862 /* 38256 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13863 /* 38259 */ GIR_RootConstrainSelectedInstOperands,
13864 /* 38260 */ // GIR_Coverage, 5857,
13865 /* 38260 */ GIR_EraseRootFromParent_Done,
13866 /* 38261 */ // Label 856: @38261
13867 /* 38261 */ GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(38319), // Rule ID 5858 //
13868 /* 38266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13869 /* 38269 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13870 /* 38272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13871 /* 38276 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13872 /* 38280 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
13873 /* 38280 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13874 /* 38283 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13875 /* 38287 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13876 /* 38292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
13877 /* 38295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13878 /* 38297 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13879 /* 38299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13880 /* 38302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13881 /* 38308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13882 /* 38314 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13883 /* 38317 */ GIR_RootConstrainSelectedInstOperands,
13884 /* 38318 */ // GIR_Coverage, 5858,
13885 /* 38318 */ GIR_EraseRootFromParent_Done,
13886 /* 38319 */ // Label 857: @38319
13887 /* 38319 */ GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(38377), // Rule ID 5859 //
13888 /* 38324 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13889 /* 38327 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13890 /* 38330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13891 /* 38334 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13892 /* 38338 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src)
13893 /* 38338 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13894 /* 38341 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13895 /* 38345 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13896 /* 38350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
13897 /* 38353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13898 /* 38355 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13899 /* 38357 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13900 /* 38360 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13901 /* 38366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13902 /* 38372 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13903 /* 38375 */ GIR_RootConstrainSelectedInstOperands,
13904 /* 38376 */ // GIR_Coverage, 5859,
13905 /* 38376 */ GIR_EraseRootFromParent_Done,
13906 /* 38377 */ // Label 858: @38377
13907 /* 38377 */ GIM_Reject,
13908 /* 38378 */ // Label 663: @38378
13909 /* 38378 */ GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(38410), // Rule ID 3101 //
13910 /* 38383 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13911 /* 38386 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13912 /* 38389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13913 /* 38393 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13914 /* 38397 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v2f64] }:$src
13915 /* 38397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13916 /* 38400 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13917 /* 38402 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13918 /* 38404 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13919 /* 38409 */ // GIR_Coverage, 3101,
13920 /* 38409 */ GIR_EraseRootFromParent_Done,
13921 /* 38410 */ // Label 859: @38410
13922 /* 38410 */ GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(38442), // Rule ID 3102 //
13923 /* 38415 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13924 /* 38418 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13925 /* 38421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13926 /* 38425 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13927 /* 38429 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v2i64] }:$src
13928 /* 38429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13929 /* 38432 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13930 /* 38434 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13931 /* 38436 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13932 /* 38441 */ // GIR_Coverage, 3102,
13933 /* 38441 */ GIR_EraseRootFromParent_Done,
13934 /* 38442 */ // Label 860: @38442
13935 /* 38442 */ GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(38474), // Rule ID 3143 //
13936 /* 38447 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13937 /* 38450 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13938 /* 38453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13939 /* 38457 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13940 /* 38461 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2f64] }:$src
13941 /* 38461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13942 /* 38464 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13943 /* 38466 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13944 /* 38468 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13945 /* 38473 */ // GIR_Coverage, 3143,
13946 /* 38473 */ GIR_EraseRootFromParent_Done,
13947 /* 38474 */ // Label 861: @38474
13948 /* 38474 */ GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(38506), // Rule ID 3144 //
13949 /* 38479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13950 /* 38482 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13951 /* 38485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13952 /* 38489 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13953 /* 38493 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2f64] }:$src
13954 /* 38493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13955 /* 38496 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13956 /* 38498 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13957 /* 38500 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13958 /* 38505 */ // GIR_Coverage, 3144,
13959 /* 38505 */ GIR_EraseRootFromParent_Done,
13960 /* 38506 */ // Label 862: @38506
13961 /* 38506 */ GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(38538), // Rule ID 3145 //
13962 /* 38511 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13963 /* 38514 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13964 /* 38517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13965 /* 38521 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13966 /* 38525 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2f64] }:$src
13967 /* 38525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13968 /* 38528 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13969 /* 38530 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13970 /* 38532 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13971 /* 38537 */ // GIR_Coverage, 3145,
13972 /* 38537 */ GIR_EraseRootFromParent_Done,
13973 /* 38538 */ // Label 863: @38538
13974 /* 38538 */ GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(38570), // Rule ID 3146 //
13975 /* 38543 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13976 /* 38546 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13977 /* 38549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13978 /* 38553 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13979 /* 38557 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2f64] }:$src
13980 /* 38557 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13981 /* 38560 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13982 /* 38562 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13983 /* 38564 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13984 /* 38569 */ // GIR_Coverage, 3146,
13985 /* 38569 */ GIR_EraseRootFromParent_Done,
13986 /* 38570 */ // Label 864: @38570
13987 /* 38570 */ GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(38602), // Rule ID 3147 //
13988 /* 38575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13989 /* 38578 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13990 /* 38581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13991 /* 38585 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13992 /* 38589 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2f64] }:$src
13993 /* 38589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13994 /* 38592 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13995 /* 38594 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13996 /* 38596 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13997 /* 38601 */ // GIR_Coverage, 3147,
13998 /* 38601 */ GIR_EraseRootFromParent_Done,
13999 /* 38602 */ // Label 865: @38602
14000 /* 38602 */ GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(38634), // Rule ID 3148 //
14001 /* 38607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
14002 /* 38610 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14003 /* 38613 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14004 /* 38617 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14005 /* 38621 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2i64] }:$src
14006 /* 38621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14007 /* 38624 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14008 /* 38626 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14009 /* 38628 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
14010 /* 38633 */ // GIR_Coverage, 3148,
14011 /* 38633 */ GIR_EraseRootFromParent_Done,
14012 /* 38634 */ // Label 866: @38634
14013 /* 38634 */ GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(38666), // Rule ID 3149 //
14014 /* 38639 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
14015 /* 38642 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14016 /* 38645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14017 /* 38649 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14018 /* 38653 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2i64] }:$src
14019 /* 38653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14020 /* 38656 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14021 /* 38658 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14022 /* 38660 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
14023 /* 38665 */ // GIR_Coverage, 3149,
14024 /* 38665 */ GIR_EraseRootFromParent_Done,
14025 /* 38666 */ // Label 867: @38666
14026 /* 38666 */ GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(38698), // Rule ID 3150 //
14027 /* 38671 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
14028 /* 38674 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14029 /* 38677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14030 /* 38681 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14031 /* 38685 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2i64] }:$src
14032 /* 38685 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14033 /* 38688 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14034 /* 38690 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14035 /* 38692 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
14036 /* 38697 */ // GIR_Coverage, 3150,
14037 /* 38697 */ GIR_EraseRootFromParent_Done,
14038 /* 38698 */ // Label 868: @38698
14039 /* 38698 */ GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(38730), // Rule ID 3151 //
14040 /* 38703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
14041 /* 38706 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14042 /* 38709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14043 /* 38713 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14044 /* 38717 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2i64] }:$src
14045 /* 38717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14046 /* 38720 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14047 /* 38722 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14048 /* 38724 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
14049 /* 38729 */ // GIR_Coverage, 3151,
14050 /* 38729 */ GIR_EraseRootFromParent_Done,
14051 /* 38730 */ // Label 869: @38730
14052 /* 38730 */ GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(38762), // Rule ID 3152 //
14053 /* 38735 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
14054 /* 38738 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
14055 /* 38741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14056 /* 38745 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14057 /* 38749 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2i64] }:$src
14058 /* 38749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14059 /* 38752 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14060 /* 38754 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14061 /* 38756 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
14062 /* 38761 */ // GIR_Coverage, 3152,
14063 /* 38761 */ GIR_EraseRootFromParent_Done,
14064 /* 38762 */ // Label 870: @38762
14065 /* 38762 */ GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(38799), // Rule ID 3215 //
14066 /* 38767 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14067 /* 38770 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14068 /* 38773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14069 /* 38777 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14070 /* 38781 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)
14071 /* 38781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
14072 /* 38784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14073 /* 38786 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14074 /* 38788 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14075 /* 38791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14076 /* 38797 */ GIR_RootConstrainSelectedInstOperands,
14077 /* 38798 */ // GIR_Coverage, 3215,
14078 /* 38798 */ GIR_EraseRootFromParent_Done,
14079 /* 38799 */ // Label 871: @38799
14080 /* 38799 */ GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(38836), // Rule ID 3216 //
14081 /* 38804 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14082 /* 38807 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14083 /* 38810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14084 /* 38814 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14085 /* 38818 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)
14086 /* 38818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
14087 /* 38821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14088 /* 38823 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14089 /* 38825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14090 /* 38828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14091 /* 38834 */ GIR_RootConstrainSelectedInstOperands,
14092 /* 38835 */ // GIR_Coverage, 3216,
14093 /* 38835 */ GIR_EraseRootFromParent_Done,
14094 /* 38836 */ // Label 872: @38836
14095 /* 38836 */ GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(38873), // Rule ID 3217 //
14096 /* 38841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14097 /* 38844 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14098 /* 38847 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14099 /* 38851 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14100 /* 38855 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)
14101 /* 38855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
14102 /* 38858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14103 /* 38860 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14104 /* 38862 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14105 /* 38865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14106 /* 38871 */ GIR_RootConstrainSelectedInstOperands,
14107 /* 38872 */ // GIR_Coverage, 3217,
14108 /* 38872 */ GIR_EraseRootFromParent_Done,
14109 /* 38873 */ // Label 873: @38873
14110 /* 38873 */ GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(38910), // Rule ID 3218 //
14111 /* 38878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14112 /* 38881 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14113 /* 38884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14114 /* 38888 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14115 /* 38892 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)
14116 /* 38892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
14117 /* 38895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14118 /* 38897 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14119 /* 38899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14120 /* 38902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14121 /* 38908 */ GIR_RootConstrainSelectedInstOperands,
14122 /* 38909 */ // GIR_Coverage, 3218,
14123 /* 38909 */ GIR_EraseRootFromParent_Done,
14124 /* 38910 */ // Label 874: @38910
14125 /* 38910 */ GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(38947), // Rule ID 3219 //
14126 /* 38915 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14127 /* 38918 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
14128 /* 38921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14129 /* 38925 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14130 /* 38929 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)
14131 /* 38929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
14132 /* 38932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14133 /* 38934 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14134 /* 38936 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14135 /* 38939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14136 /* 38945 */ GIR_RootConstrainSelectedInstOperands,
14137 /* 38946 */ // GIR_Coverage, 3219,
14138 /* 38946 */ GIR_EraseRootFromParent_Done,
14139 /* 38947 */ // Label 875: @38947
14140 /* 38947 */ GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(38984), // Rule ID 3220 //
14141 /* 38952 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14142 /* 38955 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14143 /* 38958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14144 /* 38962 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14145 /* 38966 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)
14146 /* 38966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
14147 /* 38969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14148 /* 38971 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14149 /* 38973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14150 /* 38976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14151 /* 38982 */ GIR_RootConstrainSelectedInstOperands,
14152 /* 38983 */ // GIR_Coverage, 3220,
14153 /* 38983 */ GIR_EraseRootFromParent_Done,
14154 /* 38984 */ // Label 876: @38984
14155 /* 38984 */ GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(39021), // Rule ID 3221 //
14156 /* 38989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14157 /* 38992 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14158 /* 38995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14159 /* 38999 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14160 /* 39003 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)
14161 /* 39003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
14162 /* 39006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14163 /* 39008 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14164 /* 39010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14165 /* 39013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14166 /* 39019 */ GIR_RootConstrainSelectedInstOperands,
14167 /* 39020 */ // GIR_Coverage, 3221,
14168 /* 39020 */ GIR_EraseRootFromParent_Done,
14169 /* 39021 */ // Label 877: @39021
14170 /* 39021 */ GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(39058), // Rule ID 3222 //
14171 /* 39026 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14172 /* 39029 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14173 /* 39032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14174 /* 39036 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14175 /* 39040 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src)
14176 /* 39040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
14177 /* 39043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14178 /* 39045 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14179 /* 39047 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14180 /* 39050 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14181 /* 39056 */ GIR_RootConstrainSelectedInstOperands,
14182 /* 39057 */ // GIR_Coverage, 3222,
14183 /* 39057 */ GIR_EraseRootFromParent_Done,
14184 /* 39058 */ // Label 878: @39058
14185 /* 39058 */ GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(39095), // Rule ID 3223 //
14186 /* 39063 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14187 /* 39066 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14188 /* 39069 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14189 /* 39073 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14190 /* 39077 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)
14191 /* 39077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
14192 /* 39080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14193 /* 39082 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14194 /* 39084 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14195 /* 39087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14196 /* 39093 */ GIR_RootConstrainSelectedInstOperands,
14197 /* 39094 */ // GIR_Coverage, 3223,
14198 /* 39094 */ GIR_EraseRootFromParent_Done,
14199 /* 39095 */ // Label 879: @39095
14200 /* 39095 */ GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(39132), // Rule ID 3224 //
14201 /* 39100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14202 /* 39103 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
14203 /* 39106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14204 /* 39110 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14205 /* 39114 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)
14206 /* 39114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
14207 /* 39117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14208 /* 39119 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14209 /* 39121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14210 /* 39124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14211 /* 39130 */ GIR_RootConstrainSelectedInstOperands,
14212 /* 39131 */ // GIR_Coverage, 3224,
14213 /* 39131 */ GIR_EraseRootFromParent_Done,
14214 /* 39132 */ // Label 880: @39132
14215 /* 39132 */ GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(39164), // Rule ID 5798 //
14216 /* 39137 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
14217 /* 39140 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14218 /* 39143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14219 /* 39147 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14220 /* 39151 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v2f64] }:$src
14221 /* 39151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14222 /* 39154 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14223 /* 39156 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14224 /* 39158 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14225 /* 39163 */ // GIR_Coverage, 5798,
14226 /* 39163 */ GIR_EraseRootFromParent_Done,
14227 /* 39164 */ // Label 881: @39164
14228 /* 39164 */ GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(39196), // Rule ID 5799 //
14229 /* 39169 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
14230 /* 39172 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14231 /* 39175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14232 /* 39179 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14233 /* 39183 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v2i64] }:$src
14234 /* 39183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14235 /* 39186 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14236 /* 39188 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14237 /* 39190 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14238 /* 39195 */ // GIR_Coverage, 5799,
14239 /* 39195 */ GIR_EraseRootFromParent_Done,
14240 /* 39196 */ // Label 882: @39196
14241 /* 39196 */ GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(39228), // Rule ID 5804 //
14242 /* 39201 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14243 /* 39204 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14244 /* 39207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14245 /* 39211 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14246 /* 39215 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2f64] }:$src
14247 /* 39215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14248 /* 39218 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14249 /* 39220 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14250 /* 39222 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14251 /* 39227 */ // GIR_Coverage, 5804,
14252 /* 39227 */ GIR_EraseRootFromParent_Done,
14253 /* 39228 */ // Label 883: @39228
14254 /* 39228 */ GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(39260), // Rule ID 5805 //
14255 /* 39233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14256 /* 39236 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14257 /* 39239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14258 /* 39243 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14259 /* 39247 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2f64] }:$src
14260 /* 39247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14261 /* 39250 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14262 /* 39252 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14263 /* 39254 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14264 /* 39259 */ // GIR_Coverage, 5805,
14265 /* 39259 */ GIR_EraseRootFromParent_Done,
14266 /* 39260 */ // Label 884: @39260
14267 /* 39260 */ GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(39292), // Rule ID 5806 //
14268 /* 39265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14269 /* 39268 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14270 /* 39271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14271 /* 39275 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14272 /* 39279 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2f64] }:$src
14273 /* 39279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14274 /* 39282 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14275 /* 39284 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14276 /* 39286 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14277 /* 39291 */ // GIR_Coverage, 5806,
14278 /* 39291 */ GIR_EraseRootFromParent_Done,
14279 /* 39292 */ // Label 885: @39292
14280 /* 39292 */ GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(39324), // Rule ID 5807 //
14281 /* 39297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14282 /* 39300 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14283 /* 39303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14284 /* 39307 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14285 /* 39311 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2f64] }:$src
14286 /* 39311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14287 /* 39314 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14288 /* 39316 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14289 /* 39318 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14290 /* 39323 */ // GIR_Coverage, 5807,
14291 /* 39323 */ GIR_EraseRootFromParent_Done,
14292 /* 39324 */ // Label 886: @39324
14293 /* 39324 */ GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(39356), // Rule ID 5808 //
14294 /* 39329 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14295 /* 39332 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
14296 /* 39335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14297 /* 39339 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14298 /* 39343 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2f64] }:$src
14299 /* 39343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14300 /* 39346 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14301 /* 39348 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14302 /* 39350 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14303 /* 39355 */ // GIR_Coverage, 5808,
14304 /* 39355 */ GIR_EraseRootFromParent_Done,
14305 /* 39356 */ // Label 887: @39356
14306 /* 39356 */ GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(39388), // Rule ID 5809 //
14307 /* 39361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14308 /* 39364 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14309 /* 39367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14310 /* 39371 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14311 /* 39375 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2i64] }:$src
14312 /* 39375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14313 /* 39378 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14314 /* 39380 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14315 /* 39382 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14316 /* 39387 */ // GIR_Coverage, 5809,
14317 /* 39387 */ GIR_EraseRootFromParent_Done,
14318 /* 39388 */ // Label 888: @39388
14319 /* 39388 */ GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(39420), // Rule ID 5810 //
14320 /* 39393 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14321 /* 39396 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14322 /* 39399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14323 /* 39403 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14324 /* 39407 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2i64] }:$src
14325 /* 39407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14326 /* 39410 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14327 /* 39412 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14328 /* 39414 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14329 /* 39419 */ // GIR_Coverage, 5810,
14330 /* 39419 */ GIR_EraseRootFromParent_Done,
14331 /* 39420 */ // Label 889: @39420
14332 /* 39420 */ GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(39452), // Rule ID 5811 //
14333 /* 39425 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14334 /* 39428 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14335 /* 39431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14336 /* 39435 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14337 /* 39439 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2i64] }:$src
14338 /* 39439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14339 /* 39442 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14340 /* 39444 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14341 /* 39446 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14342 /* 39451 */ // GIR_Coverage, 5811,
14343 /* 39451 */ GIR_EraseRootFromParent_Done,
14344 /* 39452 */ // Label 890: @39452
14345 /* 39452 */ GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(39484), // Rule ID 5812 //
14346 /* 39457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14347 /* 39460 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14348 /* 39463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14349 /* 39467 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14350 /* 39471 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2i64] }:$src
14351 /* 39471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14352 /* 39474 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14353 /* 39476 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14354 /* 39478 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14355 /* 39483 */ // GIR_Coverage, 5812,
14356 /* 39483 */ GIR_EraseRootFromParent_Done,
14357 /* 39484 */ // Label 891: @39484
14358 /* 39484 */ GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(39516), // Rule ID 5813 //
14359 /* 39489 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14360 /* 39492 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
14361 /* 39495 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14362 /* 39499 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14363 /* 39503 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2i64] }:$src
14364 /* 39503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14365 /* 39506 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14366 /* 39508 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14367 /* 39510 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14368 /* 39515 */ // GIR_Coverage, 5813,
14369 /* 39515 */ GIR_EraseRootFromParent_Done,
14370 /* 39516 */ // Label 892: @39516
14371 /* 39516 */ GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(39574), // Rule ID 5840 //
14372 /* 39521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14373 /* 39524 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14374 /* 39527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14375 /* 39531 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14376 /* 39535 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src)
14377 /* 39535 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14378 /* 39538 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14379 /* 39542 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14380 /* 39547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
14381 /* 39550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14382 /* 39552 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14383 /* 39554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14384 /* 39557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14385 /* 39563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14386 /* 39569 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14387 /* 39572 */ GIR_RootConstrainSelectedInstOperands,
14388 /* 39573 */ // GIR_Coverage, 5840,
14389 /* 39573 */ GIR_EraseRootFromParent_Done,
14390 /* 39574 */ // Label 893: @39574
14391 /* 39574 */ GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(39632), // Rule ID 5841 //
14392 /* 39579 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14393 /* 39582 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14394 /* 39585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14395 /* 39589 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14396 /* 39593 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src)
14397 /* 39593 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14398 /* 39596 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14399 /* 39600 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14400 /* 39605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
14401 /* 39608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14402 /* 39610 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14403 /* 39612 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14404 /* 39615 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14405 /* 39621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14406 /* 39627 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14407 /* 39630 */ GIR_RootConstrainSelectedInstOperands,
14408 /* 39631 */ // GIR_Coverage, 5841,
14409 /* 39631 */ GIR_EraseRootFromParent_Done,
14410 /* 39632 */ // Label 894: @39632
14411 /* 39632 */ GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(39690), // Rule ID 5842 //
14412 /* 39637 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14413 /* 39640 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14414 /* 39643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14415 /* 39647 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14416 /* 39651 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src)
14417 /* 39651 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14418 /* 39654 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14419 /* 39658 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14420 /* 39663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
14421 /* 39666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14422 /* 39668 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14423 /* 39670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14424 /* 39673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14425 /* 39679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14426 /* 39685 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14427 /* 39688 */ GIR_RootConstrainSelectedInstOperands,
14428 /* 39689 */ // GIR_Coverage, 5842,
14429 /* 39689 */ GIR_EraseRootFromParent_Done,
14430 /* 39690 */ // Label 895: @39690
14431 /* 39690 */ GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(39748), // Rule ID 5843 //
14432 /* 39695 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14433 /* 39698 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14434 /* 39701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14435 /* 39705 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14436 /* 39709 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src)
14437 /* 39709 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14438 /* 39712 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14439 /* 39716 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14440 /* 39721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
14441 /* 39724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14442 /* 39726 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14443 /* 39728 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14444 /* 39731 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14445 /* 39737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14446 /* 39743 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14447 /* 39746 */ GIR_RootConstrainSelectedInstOperands,
14448 /* 39747 */ // GIR_Coverage, 5843,
14449 /* 39747 */ GIR_EraseRootFromParent_Done,
14450 /* 39748 */ // Label 896: @39748
14451 /* 39748 */ GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(39806), // Rule ID 5844 //
14452 /* 39753 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14453 /* 39756 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
14454 /* 39759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14455 /* 39763 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14456 /* 39767 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src)
14457 /* 39767 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14458 /* 39770 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14459 /* 39774 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14460 /* 39779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
14461 /* 39782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14462 /* 39784 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14463 /* 39786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14464 /* 39789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14465 /* 39795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14466 /* 39801 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14467 /* 39804 */ GIR_RootConstrainSelectedInstOperands,
14468 /* 39805 */ // GIR_Coverage, 5844,
14469 /* 39805 */ GIR_EraseRootFromParent_Done,
14470 /* 39806 */ // Label 897: @39806
14471 /* 39806 */ GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(39864), // Rule ID 5845 //
14472 /* 39811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14473 /* 39814 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14474 /* 39817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14475 /* 39821 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14476 /* 39825 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src)
14477 /* 39825 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14478 /* 39828 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14479 /* 39832 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14480 /* 39837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
14481 /* 39840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14482 /* 39842 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14483 /* 39844 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14484 /* 39847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14485 /* 39853 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14486 /* 39859 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14487 /* 39862 */ GIR_RootConstrainSelectedInstOperands,
14488 /* 39863 */ // GIR_Coverage, 5845,
14489 /* 39863 */ GIR_EraseRootFromParent_Done,
14490 /* 39864 */ // Label 898: @39864
14491 /* 39864 */ GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(39922), // Rule ID 5846 //
14492 /* 39869 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14493 /* 39872 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14494 /* 39875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14495 /* 39879 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14496 /* 39883 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src)
14497 /* 39883 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14498 /* 39886 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14499 /* 39890 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14500 /* 39895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
14501 /* 39898 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14502 /* 39900 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14503 /* 39902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14504 /* 39905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14505 /* 39911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14506 /* 39917 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14507 /* 39920 */ GIR_RootConstrainSelectedInstOperands,
14508 /* 39921 */ // GIR_Coverage, 5846,
14509 /* 39921 */ GIR_EraseRootFromParent_Done,
14510 /* 39922 */ // Label 899: @39922
14511 /* 39922 */ GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(39980), // Rule ID 5847 //
14512 /* 39927 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14513 /* 39930 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14514 /* 39933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14515 /* 39937 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14516 /* 39941 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src)
14517 /* 39941 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14518 /* 39944 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14519 /* 39948 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14520 /* 39953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
14521 /* 39956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14522 /* 39958 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14523 /* 39960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14524 /* 39963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14525 /* 39969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14526 /* 39975 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14527 /* 39978 */ GIR_RootConstrainSelectedInstOperands,
14528 /* 39979 */ // GIR_Coverage, 5847,
14529 /* 39979 */ GIR_EraseRootFromParent_Done,
14530 /* 39980 */ // Label 900: @39980
14531 /* 39980 */ GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(40038), // Rule ID 5848 //
14532 /* 39985 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14533 /* 39988 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14534 /* 39991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14535 /* 39995 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14536 /* 39999 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src)
14537 /* 39999 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14538 /* 40002 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14539 /* 40006 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14540 /* 40011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
14541 /* 40014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14542 /* 40016 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14543 /* 40018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14544 /* 40021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14545 /* 40027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14546 /* 40033 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14547 /* 40036 */ GIR_RootConstrainSelectedInstOperands,
14548 /* 40037 */ // GIR_Coverage, 5848,
14549 /* 40037 */ GIR_EraseRootFromParent_Done,
14550 /* 40038 */ // Label 901: @40038
14551 /* 40038 */ GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(40096), // Rule ID 5849 //
14552 /* 40043 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14553 /* 40046 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
14554 /* 40049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14555 /* 40053 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14556 /* 40057 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src)
14557 /* 40057 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14558 /* 40060 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14559 /* 40064 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14560 /* 40069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
14561 /* 40072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14562 /* 40074 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14563 /* 40076 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14564 /* 40079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14565 /* 40085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14566 /* 40091 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14567 /* 40094 */ GIR_RootConstrainSelectedInstOperands,
14568 /* 40095 */ // GIR_Coverage, 5849,
14569 /* 40095 */ GIR_EraseRootFromParent_Done,
14570 /* 40096 */ // Label 902: @40096
14571 /* 40096 */ GIM_Reject,
14572 /* 40097 */ // Label 664: @40097
14573 /* 40097 */ GIM_Reject,
14574 /* 40098 */ // Label 16: @40098
14575 /* 40098 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 910*/ GIMT_Encode4(40505),
14576 /* 40109 */ /*GILLT_s16*//*Label 903*/ GIMT_Encode4(40161),
14577 /* 40113 */ /*GILLT_s32*//*Label 904*/ GIMT_Encode4(40199),
14578 /* 40117 */ /*GILLT_s64*//*Label 905*/ GIMT_Encode4(40237), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
14579 /* 40145 */ /*GILLT_v4s16*//*Label 906*/ GIMT_Encode4(40275),
14580 /* 40149 */ /*GILLT_v8s16*//*Label 907*/ GIMT_Encode4(40302),
14581 /* 40153 */ /*GILLT_v2s32*//*Label 908*/ GIMT_Encode4(40390),
14582 /* 40157 */ /*GILLT_v4s32*//*Label 909*/ GIMT_Encode4(40417),
14583 /* 40161 */ // Label 903: @40161
14584 /* 40161 */ GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(40198), // Rule ID 693 //
14585 /* 40166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
14586 /* 40169 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
14587 /* 40172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
14588 /* 40176 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
14589 /* 40180 */ // (ftrunc:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTZH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
14590 /* 40180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZH),
14591 /* 40183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
14592 /* 40185 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
14593 /* 40187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14594 /* 40190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14595 /* 40196 */ GIR_RootConstrainSelectedInstOperands,
14596 /* 40197 */ // GIR_Coverage, 693,
14597 /* 40197 */ GIR_EraseRootFromParent_Done,
14598 /* 40198 */ // Label 911: @40198
14599 /* 40198 */ GIM_Reject,
14600 /* 40199 */ // Label 904: @40199
14601 /* 40199 */ GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(40236), // Rule ID 695 //
14602 /* 40204 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
14603 /* 40207 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14604 /* 40210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14605 /* 40214 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14606 /* 40218 */ // (ftrunc:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTZS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14607 /* 40218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZS),
14608 /* 40221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
14609 /* 40223 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
14610 /* 40225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14611 /* 40228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14612 /* 40234 */ GIR_RootConstrainSelectedInstOperands,
14613 /* 40235 */ // GIR_Coverage, 695,
14614 /* 40235 */ GIR_EraseRootFromParent_Done,
14615 /* 40236 */ // Label 912: @40236
14616 /* 40236 */ GIM_Reject,
14617 /* 40237 */ // Label 905: @40237
14618 /* 40237 */ GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(40274), // Rule ID 697 //
14619 /* 40242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
14620 /* 40245 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
14621 /* 40248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14622 /* 40252 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14623 /* 40256 */ // (ftrunc:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTZD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
14624 /* 40256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZD),
14625 /* 40259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
14626 /* 40261 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
14627 /* 40263 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14628 /* 40266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14629 /* 40272 */ GIR_RootConstrainSelectedInstOperands,
14630 /* 40273 */ // GIR_Coverage, 697,
14631 /* 40273 */ GIR_EraseRootFromParent_Done,
14632 /* 40274 */ // Label 913: @40274
14633 /* 40274 */ GIM_Reject,
14634 /* 40275 */ // Label 906: @40275
14635 /* 40275 */ GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(40301), // Rule ID 1882 //
14636 /* 40280 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
14637 /* 40283 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
14638 /* 40286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14639 /* 40290 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14640 /* 40294 */ // (ftrunc:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTZNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
14641 /* 40294 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDh),
14642 /* 40299 */ GIR_RootConstrainSelectedInstOperands,
14643 /* 40300 */ // GIR_Coverage, 1882,
14644 /* 40300 */ GIR_Done,
14645 /* 40301 */ // Label 914: @40301
14646 /* 40301 */ GIM_Reject,
14647 /* 40302 */ // Label 907: @40302
14648 /* 40302 */ GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(40389),
14649 /* 40307 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14650 /* 40310 */ GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(40333), // Rule ID 1884 //
14651 /* 40315 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
14652 /* 40318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14653 /* 40322 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14654 /* 40326 */ // (ftrunc:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTZNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
14655 /* 40326 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQh),
14656 /* 40331 */ GIR_RootConstrainSelectedInstOperands,
14657 /* 40332 */ // GIR_Coverage, 1884,
14658 /* 40332 */ GIR_Done,
14659 /* 40333 */ // Label 916: @40333
14660 /* 40333 */ GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(40388), // Rule ID 4360 //
14661 /* 40338 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
14662 /* 40341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14663 /* 40345 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14664 /* 40349 */ // (ftrunc:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
14665 /* 40349 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14666 /* 40352 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14667 /* 40356 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14668 /* 40361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z),
14669 /* 40364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14670 /* 40366 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
14671 /* 40368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14672 /* 40371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14673 /* 40377 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14674 /* 40383 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14675 /* 40386 */ GIR_RootConstrainSelectedInstOperands,
14676 /* 40387 */ // GIR_Coverage, 4360,
14677 /* 40387 */ GIR_EraseRootFromParent_Done,
14678 /* 40388 */ // Label 917: @40388
14679 /* 40388 */ GIM_Reject,
14680 /* 40389 */ // Label 915: @40389
14681 /* 40389 */ GIM_Reject,
14682 /* 40390 */ // Label 908: @40390
14683 /* 40390 */ GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(40416), // Rule ID 1878 //
14684 /* 40395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
14685 /* 40398 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
14686 /* 40401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14687 /* 40405 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14688 /* 40409 */ // (ftrunc:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTZNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14689 /* 40409 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDf),
14690 /* 40414 */ GIR_RootConstrainSelectedInstOperands,
14691 /* 40415 */ // GIR_Coverage, 1878,
14692 /* 40415 */ GIR_Done,
14693 /* 40416 */ // Label 918: @40416
14694 /* 40416 */ GIM_Reject,
14695 /* 40417 */ // Label 909: @40417
14696 /* 40417 */ GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(40504),
14697 /* 40422 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14698 /* 40425 */ GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(40448), // Rule ID 1880 //
14699 /* 40430 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
14700 /* 40433 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14701 /* 40437 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14702 /* 40441 */ // (ftrunc:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTZNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14703 /* 40441 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQf),
14704 /* 40446 */ GIR_RootConstrainSelectedInstOperands,
14705 /* 40447 */ // GIR_Coverage, 1880,
14706 /* 40447 */ GIR_Done,
14707 /* 40448 */ // Label 920: @40448
14708 /* 40448 */ GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(40503), // Rule ID 4384 //
14709 /* 40453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
14710 /* 40456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14711 /* 40460 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14712 /* 40464 */ // (ftrunc:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
14713 /* 40464 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14714 /* 40467 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14715 /* 40471 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14716 /* 40476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z),
14717 /* 40479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14718 /* 40481 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
14719 /* 40483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14720 /* 40486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14721 /* 40492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14722 /* 40498 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14723 /* 40501 */ GIR_RootConstrainSelectedInstOperands,
14724 /* 40502 */ // GIR_Coverage, 4384,
14725 /* 40502 */ GIR_EraseRootFromParent_Done,
14726 /* 40503 */ // Label 921: @40503
14727 /* 40503 */ GIM_Reject,
14728 /* 40504 */ // Label 919: @40504
14729 /* 40504 */ GIM_Reject,
14730 /* 40505 */ // Label 910: @40505
14731 /* 40505 */ GIM_Reject,
14732 /* 40506 */ // Label 17: @40506
14733 /* 40506 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 929*/ GIMT_Encode4(40880),
14734 /* 40517 */ /*GILLT_s16*//*Label 922*/ GIMT_Encode4(40569),
14735 /* 40521 */ /*GILLT_s32*//*Label 923*/ GIMT_Encode4(40596),
14736 /* 40525 */ /*GILLT_s64*//*Label 924*/ GIMT_Encode4(40623), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
14737 /* 40553 */ /*GILLT_v4s16*//*Label 925*/ GIMT_Encode4(40650),
14738 /* 40557 */ /*GILLT_v8s16*//*Label 926*/ GIMT_Encode4(40677),
14739 /* 40561 */ /*GILLT_v2s32*//*Label 927*/ GIMT_Encode4(40765),
14740 /* 40565 */ /*GILLT_v4s32*//*Label 928*/ GIMT_Encode4(40792),
14741 /* 40569 */ // Label 922: @40569
14742 /* 40569 */ GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(40595), // Rule ID 711 //
14743 /* 40574 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
14744 /* 40577 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
14745 /* 40580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
14746 /* 40584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
14747 /* 40588 */ // (fround:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTAH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
14748 /* 40588 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAH),
14749 /* 40593 */ GIR_RootConstrainSelectedInstOperands,
14750 /* 40594 */ // GIR_Coverage, 711,
14751 /* 40594 */ GIR_Done,
14752 /* 40595 */ // Label 930: @40595
14753 /* 40595 */ GIM_Reject,
14754 /* 40596 */ // Label 923: @40596
14755 /* 40596 */ GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(40622), // Rule ID 713 //
14756 /* 40601 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
14757 /* 40604 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14758 /* 40607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14759 /* 40611 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14760 /* 40615 */ // (fround:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTAS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14761 /* 40615 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAS),
14762 /* 40620 */ GIR_RootConstrainSelectedInstOperands,
14763 /* 40621 */ // GIR_Coverage, 713,
14764 /* 40621 */ GIR_Done,
14765 /* 40622 */ // Label 931: @40622
14766 /* 40622 */ GIM_Reject,
14767 /* 40623 */ // Label 924: @40623
14768 /* 40623 */ GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(40649), // Rule ID 715 //
14769 /* 40628 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
14770 /* 40631 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
14771 /* 40634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14772 /* 40638 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14773 /* 40642 */ // (fround:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTAD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
14774 /* 40642 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAD),
14775 /* 40647 */ GIR_RootConstrainSelectedInstOperands,
14776 /* 40648 */ // GIR_Coverage, 715,
14777 /* 40648 */ GIR_Done,
14778 /* 40649 */ // Label 932: @40649
14779 /* 40649 */ GIM_Reject,
14780 /* 40650 */ // Label 925: @40650
14781 /* 40650 */ GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(40676), // Rule ID 1874 //
14782 /* 40655 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
14783 /* 40658 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
14784 /* 40661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14785 /* 40665 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14786 /* 40669 */ // (fround:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTANDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
14787 /* 40669 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDh),
14788 /* 40674 */ GIR_RootConstrainSelectedInstOperands,
14789 /* 40675 */ // GIR_Coverage, 1874,
14790 /* 40675 */ GIR_Done,
14791 /* 40676 */ // Label 933: @40676
14792 /* 40676 */ GIM_Reject,
14793 /* 40677 */ // Label 926: @40677
14794 /* 40677 */ GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(40764),
14795 /* 40682 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14796 /* 40685 */ GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(40708), // Rule ID 1876 //
14797 /* 40690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
14798 /* 40693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14799 /* 40697 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14800 /* 40701 */ // (fround:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTANQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
14801 /* 40701 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQh),
14802 /* 40706 */ GIR_RootConstrainSelectedInstOperands,
14803 /* 40707 */ // GIR_Coverage, 1876,
14804 /* 40707 */ GIR_Done,
14805 /* 40708 */ // Label 935: @40708
14806 /* 40708 */ GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(40763), // Rule ID 4356 //
14807 /* 40713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
14808 /* 40716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14809 /* 40720 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14810 /* 40724 */ // (fround:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
14811 /* 40724 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14812 /* 40727 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14813 /* 40731 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14814 /* 40736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A),
14815 /* 40739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14816 /* 40741 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
14817 /* 40743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14818 /* 40746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14819 /* 40752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14820 /* 40758 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14821 /* 40761 */ GIR_RootConstrainSelectedInstOperands,
14822 /* 40762 */ // GIR_Coverage, 4356,
14823 /* 40762 */ GIR_EraseRootFromParent_Done,
14824 /* 40763 */ // Label 936: @40763
14825 /* 40763 */ GIM_Reject,
14826 /* 40764 */ // Label 934: @40764
14827 /* 40764 */ GIM_Reject,
14828 /* 40765 */ // Label 927: @40765
14829 /* 40765 */ GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(40791), // Rule ID 1870 //
14830 /* 40770 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
14831 /* 40773 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
14832 /* 40776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14833 /* 40780 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14834 /* 40784 */ // (fround:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTANDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14835 /* 40784 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDf),
14836 /* 40789 */ GIR_RootConstrainSelectedInstOperands,
14837 /* 40790 */ // GIR_Coverage, 1870,
14838 /* 40790 */ GIR_Done,
14839 /* 40791 */ // Label 937: @40791
14840 /* 40791 */ GIM_Reject,
14841 /* 40792 */ // Label 928: @40792
14842 /* 40792 */ GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(40879),
14843 /* 40797 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14844 /* 40800 */ GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(40823), // Rule ID 1872 //
14845 /* 40805 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
14846 /* 40808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14847 /* 40812 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14848 /* 40816 */ // (fround:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTANQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14849 /* 40816 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQf),
14850 /* 40821 */ GIR_RootConstrainSelectedInstOperands,
14851 /* 40822 */ // GIR_Coverage, 1872,
14852 /* 40822 */ GIR_Done,
14853 /* 40823 */ // Label 939: @40823
14854 /* 40823 */ GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(40878), // Rule ID 4380 //
14855 /* 40828 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
14856 /* 40831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14857 /* 40835 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14858 /* 40839 */ // (fround:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
14859 /* 40839 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14860 /* 40842 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14861 /* 40846 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14862 /* 40851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A),
14863 /* 40854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14864 /* 40856 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
14865 /* 40858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14866 /* 40861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14867 /* 40867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14868 /* 40873 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14869 /* 40876 */ GIR_RootConstrainSelectedInstOperands,
14870 /* 40877 */ // GIR_Coverage, 4380,
14871 /* 40877 */ GIR_EraseRootFromParent_Done,
14872 /* 40878 */ // Label 940: @40878
14873 /* 40878 */ GIM_Reject,
14874 /* 40879 */ // Label 938: @40879
14875 /* 40879 */ GIM_Reject,
14876 /* 40880 */ // Label 929: @40880
14877 /* 40880 */ GIM_Reject,
14878 /* 40881 */ // Label 18: @40881
14879 /* 40881 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 948*/ GIMT_Encode4(41255),
14880 /* 40892 */ /*GILLT_s16*//*Label 941*/ GIMT_Encode4(40944),
14881 /* 40896 */ /*GILLT_s32*//*Label 942*/ GIMT_Encode4(40971),
14882 /* 40900 */ /*GILLT_s64*//*Label 943*/ GIMT_Encode4(40998), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
14883 /* 40928 */ /*GILLT_v4s16*//*Label 944*/ GIMT_Encode4(41025),
14884 /* 40932 */ /*GILLT_v8s16*//*Label 945*/ GIMT_Encode4(41052),
14885 /* 40936 */ /*GILLT_v2s32*//*Label 946*/ GIMT_Encode4(41140),
14886 /* 40940 */ /*GILLT_v4s32*//*Label 947*/ GIMT_Encode4(41167),
14887 /* 40944 */ // Label 941: @40944
14888 /* 40944 */ GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(40970), // Rule ID 717 //
14889 /* 40949 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
14890 /* 40952 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
14891 /* 40955 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
14892 /* 40959 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
14893 /* 40963 */ // (froundeven:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
14894 /* 40963 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNH),
14895 /* 40968 */ GIR_RootConstrainSelectedInstOperands,
14896 /* 40969 */ // GIR_Coverage, 717,
14897 /* 40969 */ GIR_Done,
14898 /* 40970 */ // Label 949: @40970
14899 /* 40970 */ GIM_Reject,
14900 /* 40971 */ // Label 942: @40971
14901 /* 40971 */ GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(40997), // Rule ID 719 //
14902 /* 40976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
14903 /* 40979 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14904 /* 40982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14905 /* 40986 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14906 /* 40990 */ // (froundeven:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14907 /* 40990 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNS),
14908 /* 40995 */ GIR_RootConstrainSelectedInstOperands,
14909 /* 40996 */ // GIR_Coverage, 719,
14910 /* 40996 */ GIR_Done,
14911 /* 40997 */ // Label 950: @40997
14912 /* 40997 */ GIM_Reject,
14913 /* 40998 */ // Label 943: @40998
14914 /* 40998 */ GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(41024), // Rule ID 721 //
14915 /* 41003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
14916 /* 41006 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
14917 /* 41009 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14918 /* 41013 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14919 /* 41017 */ // (froundeven:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
14920 /* 41017 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTND),
14921 /* 41022 */ GIR_RootConstrainSelectedInstOperands,
14922 /* 41023 */ // GIR_Coverage, 721,
14923 /* 41023 */ GIR_Done,
14924 /* 41024 */ // Label 951: @41024
14925 /* 41024 */ GIM_Reject,
14926 /* 41025 */ // Label 944: @41025
14927 /* 41025 */ GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(41051), // Rule ID 1858 //
14928 /* 41030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
14929 /* 41033 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
14930 /* 41036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14931 /* 41040 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14932 /* 41044 */ // (froundeven:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
14933 /* 41044 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDh),
14934 /* 41049 */ GIR_RootConstrainSelectedInstOperands,
14935 /* 41050 */ // GIR_Coverage, 1858,
14936 /* 41050 */ GIR_Done,
14937 /* 41051 */ // Label 952: @41051
14938 /* 41051 */ GIM_Reject,
14939 /* 41052 */ // Label 945: @41052
14940 /* 41052 */ GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(41139),
14941 /* 41057 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14942 /* 41060 */ GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(41083), // Rule ID 1860 //
14943 /* 41065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
14944 /* 41068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14945 /* 41072 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14946 /* 41076 */ // (froundeven:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
14947 /* 41076 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQh),
14948 /* 41081 */ GIR_RootConstrainSelectedInstOperands,
14949 /* 41082 */ // GIR_Coverage, 1860,
14950 /* 41082 */ GIR_Done,
14951 /* 41083 */ // Label 954: @41083
14952 /* 41083 */ GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(41138), // Rule ID 4348 //
14953 /* 41088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
14954 /* 41091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14955 /* 41095 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14956 /* 41099 */ // (froundeven:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
14957 /* 41099 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14958 /* 41102 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14959 /* 41106 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14960 /* 41111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N),
14961 /* 41114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14962 /* 41116 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
14963 /* 41118 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14964 /* 41121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14965 /* 41127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14966 /* 41133 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14967 /* 41136 */ GIR_RootConstrainSelectedInstOperands,
14968 /* 41137 */ // GIR_Coverage, 4348,
14969 /* 41137 */ GIR_EraseRootFromParent_Done,
14970 /* 41138 */ // Label 955: @41138
14971 /* 41138 */ GIM_Reject,
14972 /* 41139 */ // Label 953: @41139
14973 /* 41139 */ GIM_Reject,
14974 /* 41140 */ // Label 946: @41140
14975 /* 41140 */ GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(41166), // Rule ID 1854 //
14976 /* 41145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
14977 /* 41148 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
14978 /* 41151 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14979 /* 41155 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14980 /* 41159 */ // (froundeven:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTNNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14981 /* 41159 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDf),
14982 /* 41164 */ GIR_RootConstrainSelectedInstOperands,
14983 /* 41165 */ // GIR_Coverage, 1854,
14984 /* 41165 */ GIR_Done,
14985 /* 41166 */ // Label 956: @41166
14986 /* 41166 */ GIM_Reject,
14987 /* 41167 */ // Label 947: @41167
14988 /* 41167 */ GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(41254),
14989 /* 41172 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14990 /* 41175 */ GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(41198), // Rule ID 1856 //
14991 /* 41180 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
14992 /* 41183 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14993 /* 41187 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14994 /* 41191 */ // (froundeven:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTNNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14995 /* 41191 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQf),
14996 /* 41196 */ GIR_RootConstrainSelectedInstOperands,
14997 /* 41197 */ // GIR_Coverage, 1856,
14998 /* 41197 */ GIR_Done,
14999 /* 41198 */ // Label 958: @41198
15000 /* 41198 */ GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(41253), // Rule ID 4372 //
15001 /* 41203 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
15002 /* 41206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15003 /* 41210 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15004 /* 41214 */ // (froundeven:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
15005 /* 41214 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15006 /* 41217 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15007 /* 41221 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15008 /* 41226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N),
15009 /* 41229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15010 /* 41231 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
15011 /* 41233 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15012 /* 41236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15013 /* 41242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15014 /* 41248 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15015 /* 41251 */ GIR_RootConstrainSelectedInstOperands,
15016 /* 41252 */ // GIR_Coverage, 4372,
15017 /* 41252 */ GIR_EraseRootFromParent_Done,
15018 /* 41253 */ // Label 959: @41253
15019 /* 41253 */ GIM_Reject,
15020 /* 41254 */ // Label 957: @41254
15021 /* 41254 */ GIM_Reject,
15022 /* 41255 */ // Label 948: @41255
15023 /* 41255 */ GIM_Reject,
15024 /* 41256 */ // Label 19: @41256
15025 /* 41256 */ GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(41418),
15026 /* 41261 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15027 /* 41264 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
15028 /* 41267 */ GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(41342), // Rule ID 2239 //
15029 /* 41272 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
15030 /* 41275 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
15031 /* 41282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
15032 /* 41286 */ // MIs[0] Rn
15033 /* 41286 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
15034 /* 41290 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
15035 /* 41294 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (tLDRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
15036 /* 41294 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15037 /* 41297 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
15038 /* 41301 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15039 /* 41306 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
15040 /* 41312 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
15041 /* 41315 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
15042 /* 41318 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15043 /* 41324 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15044 /* 41326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSB),
15045 /* 41329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
15046 /* 41331 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
15047 /* 41333 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15048 /* 41336 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15049 /* 41340 */ GIR_RootConstrainSelectedInstOperands,
15050 /* 41341 */ // GIR_Coverage, 2239,
15051 /* 41341 */ GIR_EraseRootFromParent_Done,
15052 /* 41342 */ // Label 961: @41342
15053 /* 41342 */ GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(41417), // Rule ID 2240 //
15054 /* 41347 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
15055 /* 41350 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
15056 /* 41357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
15057 /* 41361 */ // MIs[0] Rn
15058 /* 41361 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
15059 /* 41365 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
15060 /* 41369 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (tLDRSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
15061 /* 41369 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15062 /* 41372 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
15063 /* 41376 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15064 /* 41381 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
15065 /* 41387 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
15066 /* 41390 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
15067 /* 41393 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15068 /* 41399 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15069 /* 41401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSH),
15070 /* 41404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
15071 /* 41406 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
15072 /* 41408 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15073 /* 41411 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15074 /* 41415 */ GIR_RootConstrainSelectedInstOperands,
15075 /* 41416 */ // GIR_Coverage, 2240,
15076 /* 41416 */ GIR_EraseRootFromParent_Done,
15077 /* 41417 */ // Label 962: @41417
15078 /* 41417 */ GIM_Reject,
15079 /* 41418 */ // Label 960: @41418
15080 /* 41418 */ GIM_Reject,
15081 /* 41419 */ // Label 20: @41419
15082 /* 41419 */ GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(41439), // Rule ID 5936 //
15083 /* 41424 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15084 /* 41427 */ // MIs[0] Operand 0
15085 /* 41427 */ GIM_CheckIsImm, /*MI*/0, /*Op*/0,
15086 /* 41430 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
15087 /* 41434 */ // (atomic_fence (timm:{ *:[i32] }), 0:{ *:[i32] }) => (MEMBARRIER)
15088 /* 41434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::MEMBARRIER),
15089 /* 41437 */ GIR_RootConstrainSelectedInstOperands,
15090 /* 41438 */ // GIR_Coverage, 5936,
15091 /* 41438 */ GIR_EraseRootFromParent_Done,
15092 /* 41439 */ // Label 963: @41439
15093 /* 41439 */ GIM_Reject,
15094 /* 41440 */ // Label 21: @41440
15095 /* 41440 */ GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(46494),
15096 /* 41445 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
15097 /* 41448 */ GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(41496), // Rule ID 2042 //
15098 /* 41453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
15099 /* 41456 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16),
15100 /* 41461 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15101 /* 41464 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15102 /* 41467 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
15103 /* 41471 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
15104 /* 41475 */ // (intrinsic_wo_chain:{ *:[i32] } 4201:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
15105 /* 41475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16),
15106 /* 41478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
15107 /* 41480 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src
15108 /* 41482 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15109 /* 41485 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15110 /* 41488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15111 /* 41494 */ GIR_RootConstrainSelectedInstOperands,
15112 /* 41495 */ // GIR_Coverage, 2042,
15113 /* 41495 */ GIR_EraseRootFromParent_Done,
15114 /* 41496 */ // Label 965: @41496
15115 /* 41496 */ GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(41544), // Rule ID 2296 //
15116 /* 41501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
15117 /* 41504 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16),
15118 /* 41509 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15119 /* 41512 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15120 /* 41515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
15121 /* 41519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
15122 /* 41523 */ // (intrinsic_wo_chain:{ *:[i32] } 4201:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
15123 /* 41523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16),
15124 /* 41526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
15125 /* 41528 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
15126 /* 41530 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15127 /* 41533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15128 /* 41536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15129 /* 41542 */ GIR_RootConstrainSelectedInstOperands,
15130 /* 41543 */ // GIR_Coverage, 2296,
15131 /* 41543 */ GIR_EraseRootFromParent_Done,
15132 /* 41544 */ // Label 966: @41544
15133 /* 41544 */ GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(41589), // Rule ID 744 //
15134 /* 41549 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
15135 /* 41552 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr),
15136 /* 41557 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15137 /* 41560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
15138 /* 41563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
15139 /* 41567 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15140 /* 41571 */ // (intrinsic_wo_chain:{ *:[f32] } 4202:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
15141 /* 41571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRD),
15142 /* 41574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
15143 /* 41576 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
15144 /* 41578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15145 /* 41581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15146 /* 41587 */ GIR_RootConstrainSelectedInstOperands,
15147 /* 41588 */ // GIR_Coverage, 744,
15148 /* 41588 */ GIR_EraseRootFromParent_Done,
15149 /* 41589 */ // Label 967: @41589
15150 /* 41589 */ GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(41634), // Rule ID 745 //
15151 /* 41594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
15152 /* 41597 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr),
15153 /* 41602 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15154 /* 41605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15155 /* 41608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
15156 /* 41612 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
15157 /* 41616 */ // (intrinsic_wo_chain:{ *:[f32] } 4202:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
15158 /* 41616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRS),
15159 /* 41619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
15160 /* 41621 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
15161 /* 41623 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15162 /* 41626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15163 /* 41632 */ GIR_RootConstrainSelectedInstOperands,
15164 /* 41633 */ // GIR_Coverage, 745,
15165 /* 41633 */ GIR_EraseRootFromParent_Done,
15166 /* 41634 */ // Label 968: @41634
15167 /* 41634 */ GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(41679), // Rule ID 746 //
15168 /* 41639 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
15169 /* 41642 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru),
15170 /* 41647 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15171 /* 41650 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
15172 /* 41653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
15173 /* 41657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15174 /* 41661 */ // (intrinsic_wo_chain:{ *:[f32] } 4203:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
15175 /* 41661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRD),
15176 /* 41664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
15177 /* 41666 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
15178 /* 41668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15179 /* 41671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15180 /* 41677 */ GIR_RootConstrainSelectedInstOperands,
15181 /* 41678 */ // GIR_Coverage, 746,
15182 /* 41678 */ GIR_EraseRootFromParent_Done,
15183 /* 41679 */ // Label 969: @41679
15184 /* 41679 */ GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(41724), // Rule ID 747 //
15185 /* 41684 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
15186 /* 41687 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru),
15187 /* 41692 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15188 /* 41695 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15189 /* 41698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
15190 /* 41702 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
15191 /* 41706 */ // (intrinsic_wo_chain:{ *:[f32] } 4203:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
15192 /* 41706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRS),
15193 /* 41709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
15194 /* 41711 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
15195 /* 41713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15196 /* 41716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15197 /* 41722 */ GIR_RootConstrainSelectedInstOperands,
15198 /* 41723 */ // GIR_Coverage, 747,
15199 /* 41723 */ GIR_EraseRootFromParent_Done,
15200 /* 41724 */ // Label 970: @41724
15201 /* 41724 */ GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(41769), // Rule ID 1404 //
15202 /* 41729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15203 /* 41732 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
15204 /* 41737 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15205 /* 41740 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
15206 /* 41743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15207 /* 41747 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15208 /* 41751 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4059:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
15209 /* 41751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i8),
15210 /* 41754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15211 /* 41756 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15212 /* 41758 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15213 /* 41761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15214 /* 41767 */ GIR_RootConstrainSelectedInstOperands,
15215 /* 41768 */ // GIR_Coverage, 1404,
15216 /* 41768 */ GIR_EraseRootFromParent_Done,
15217 /* 41769 */ // Label 971: @41769
15218 /* 41769 */ GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(41814), // Rule ID 1405 //
15219 /* 41774 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15220 /* 41777 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
15221 /* 41782 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15222 /* 41785 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15223 /* 41788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15224 /* 41792 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15225 /* 41796 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4059:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
15226 /* 41796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i16),
15227 /* 41799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15228 /* 41801 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15229 /* 41803 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15230 /* 41806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15231 /* 41812 */ GIR_RootConstrainSelectedInstOperands,
15232 /* 41813 */ // GIR_Coverage, 1405,
15233 /* 41813 */ GIR_EraseRootFromParent_Done,
15234 /* 41814 */ // Label 972: @41814
15235 /* 41814 */ GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(41859), // Rule ID 1406 //
15236 /* 41819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15237 /* 41822 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
15238 /* 41827 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
15239 /* 41830 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15240 /* 41833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15241 /* 41837 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15242 /* 41841 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4059:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
15243 /* 41841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv2i32),
15244 /* 41844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15245 /* 41846 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15246 /* 41848 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15247 /* 41851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15248 /* 41857 */ GIR_RootConstrainSelectedInstOperands,
15249 /* 41858 */ // GIR_Coverage, 1406,
15250 /* 41858 */ GIR_EraseRootFromParent_Done,
15251 /* 41859 */ // Label 973: @41859
15252 /* 41859 */ GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(41904), // Rule ID 1407 //
15253 /* 41864 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15254 /* 41867 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
15255 /* 41872 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15256 /* 41875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15257 /* 41878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15258 /* 41882 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15259 /* 41886 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4059:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
15260 /* 41886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv16i8),
15261 /* 41889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15262 /* 41891 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15263 /* 41893 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15264 /* 41896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15265 /* 41902 */ GIR_RootConstrainSelectedInstOperands,
15266 /* 41903 */ // GIR_Coverage, 1407,
15267 /* 41903 */ GIR_EraseRootFromParent_Done,
15268 /* 41904 */ // Label 974: @41904
15269 /* 41904 */ GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(41949), // Rule ID 1408 //
15270 /* 41909 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15271 /* 41912 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
15272 /* 41917 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15273 /* 41920 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15274 /* 41923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15275 /* 41927 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15276 /* 41931 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4059:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
15277 /* 41931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i16),
15278 /* 41934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15279 /* 41936 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15280 /* 41938 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15281 /* 41941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15282 /* 41947 */ GIR_RootConstrainSelectedInstOperands,
15283 /* 41948 */ // GIR_Coverage, 1408,
15284 /* 41948 */ GIR_EraseRootFromParent_Done,
15285 /* 41949 */ // Label 975: @41949
15286 /* 41949 */ GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(41994), // Rule ID 1409 //
15287 /* 41954 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15288 /* 41957 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
15289 /* 41962 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
15290 /* 41965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15291 /* 41968 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15292 /* 41972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15293 /* 41976 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4059:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
15294 /* 41976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i32),
15295 /* 41979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15296 /* 41981 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15297 /* 41983 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15298 /* 41986 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15299 /* 41992 */ GIR_RootConstrainSelectedInstOperands,
15300 /* 41993 */ // GIR_Coverage, 1409,
15301 /* 41993 */ GIR_EraseRootFromParent_Done,
15302 /* 41994 */ // Label 976: @41994
15303 /* 41994 */ GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(42039), // Rule ID 1410 //
15304 /* 41999 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15305 /* 42002 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
15306 /* 42007 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15307 /* 42010 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
15308 /* 42013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15309 /* 42017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15310 /* 42021 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4060:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
15311 /* 42021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i8),
15312 /* 42024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15313 /* 42026 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15314 /* 42028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15315 /* 42031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15316 /* 42037 */ GIR_RootConstrainSelectedInstOperands,
15317 /* 42038 */ // GIR_Coverage, 1410,
15318 /* 42038 */ GIR_EraseRootFromParent_Done,
15319 /* 42039 */ // Label 977: @42039
15320 /* 42039 */ GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(42084), // Rule ID 1411 //
15321 /* 42044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15322 /* 42047 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
15323 /* 42052 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15324 /* 42055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15325 /* 42058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15326 /* 42062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15327 /* 42066 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4060:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
15328 /* 42066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i16),
15329 /* 42069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15330 /* 42071 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15331 /* 42073 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15332 /* 42076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15333 /* 42082 */ GIR_RootConstrainSelectedInstOperands,
15334 /* 42083 */ // GIR_Coverage, 1411,
15335 /* 42083 */ GIR_EraseRootFromParent_Done,
15336 /* 42084 */ // Label 978: @42084
15337 /* 42084 */ GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(42129), // Rule ID 1412 //
15338 /* 42089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15339 /* 42092 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
15340 /* 42097 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
15341 /* 42100 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15342 /* 42103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15343 /* 42107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15344 /* 42111 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4060:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
15345 /* 42111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv2i32),
15346 /* 42114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15347 /* 42116 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15348 /* 42118 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15349 /* 42121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15350 /* 42127 */ GIR_RootConstrainSelectedInstOperands,
15351 /* 42128 */ // GIR_Coverage, 1412,
15352 /* 42128 */ GIR_EraseRootFromParent_Done,
15353 /* 42129 */ // Label 979: @42129
15354 /* 42129 */ GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(42174), // Rule ID 1413 //
15355 /* 42134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15356 /* 42137 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
15357 /* 42142 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15358 /* 42145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15359 /* 42148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15360 /* 42152 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15361 /* 42156 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4060:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
15362 /* 42156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv16i8),
15363 /* 42159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15364 /* 42161 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15365 /* 42163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15366 /* 42166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15367 /* 42172 */ GIR_RootConstrainSelectedInstOperands,
15368 /* 42173 */ // GIR_Coverage, 1413,
15369 /* 42173 */ GIR_EraseRootFromParent_Done,
15370 /* 42174 */ // Label 980: @42174
15371 /* 42174 */ GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(42219), // Rule ID 1414 //
15372 /* 42179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15373 /* 42182 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
15374 /* 42187 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15375 /* 42190 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15376 /* 42193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15377 /* 42197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15378 /* 42201 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4060:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
15379 /* 42201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i16),
15380 /* 42204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15381 /* 42206 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15382 /* 42208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15383 /* 42211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15384 /* 42217 */ GIR_RootConstrainSelectedInstOperands,
15385 /* 42218 */ // GIR_Coverage, 1414,
15386 /* 42218 */ GIR_EraseRootFromParent_Done,
15387 /* 42219 */ // Label 981: @42219
15388 /* 42219 */ GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(42264), // Rule ID 1415 //
15389 /* 42224 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15390 /* 42227 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
15391 /* 42232 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
15392 /* 42235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15393 /* 42238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15394 /* 42242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15395 /* 42246 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4060:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
15396 /* 42246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i32),
15397 /* 42249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15398 /* 42251 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15399 /* 42253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15400 /* 42256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15401 /* 42262 */ GIR_RootConstrainSelectedInstOperands,
15402 /* 42263 */ // GIR_Coverage, 1415,
15403 /* 42263 */ GIR_EraseRootFromParent_Done,
15404 /* 42264 */ // Label 982: @42264
15405 /* 42264 */ GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(42309), // Rule ID 1444 //
15406 /* 42269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15407 /* 42272 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
15408 /* 42277 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15409 /* 42280 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15410 /* 42283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15411 /* 42287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15412 /* 42291 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4087:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
15413 /* 42291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEd),
15414 /* 42294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15415 /* 42296 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15416 /* 42298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15417 /* 42301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15418 /* 42307 */ GIR_RootConstrainSelectedInstOperands,
15419 /* 42308 */ // GIR_Coverage, 1444,
15420 /* 42308 */ GIR_EraseRootFromParent_Done,
15421 /* 42309 */ // Label 983: @42309
15422 /* 42309 */ GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(42354), // Rule ID 1445 //
15423 /* 42314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15424 /* 42317 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
15425 /* 42322 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15426 /* 42325 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15427 /* 42328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15428 /* 42332 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15429 /* 42336 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4087:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
15430 /* 42336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEq),
15431 /* 42339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15432 /* 42341 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15433 /* 42343 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15434 /* 42346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15435 /* 42352 */ GIR_RootConstrainSelectedInstOperands,
15436 /* 42353 */ // GIR_Coverage, 1445,
15437 /* 42353 */ GIR_EraseRootFromParent_Done,
15438 /* 42354 */ // Label 984: @42354
15439 /* 42354 */ GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(42399), // Rule ID 1446 //
15440 /* 42359 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15441 /* 42362 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
15442 /* 42367 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15443 /* 42370 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15444 /* 42373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15445 /* 42377 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15446 /* 42381 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4087:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15447 /* 42381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfd),
15448 /* 42384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15449 /* 42386 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15450 /* 42388 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15451 /* 42391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15452 /* 42397 */ GIR_RootConstrainSelectedInstOperands,
15453 /* 42398 */ // GIR_Coverage, 1446,
15454 /* 42398 */ GIR_EraseRootFromParent_Done,
15455 /* 42399 */ // Label 985: @42399
15456 /* 42399 */ GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(42444), // Rule ID 1447 //
15457 /* 42404 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15458 /* 42407 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
15459 /* 42412 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15460 /* 42415 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15461 /* 42418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15462 /* 42422 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15463 /* 42426 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4087:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15464 /* 42426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfq),
15465 /* 42429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15466 /* 42431 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15467 /* 42433 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15468 /* 42436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15469 /* 42442 */ GIR_RootConstrainSelectedInstOperands,
15470 /* 42443 */ // GIR_Coverage, 1447,
15471 /* 42443 */ GIR_EraseRootFromParent_Done,
15472 /* 42444 */ // Label 986: @42444
15473 /* 42444 */ GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(42489), // Rule ID 1448 //
15474 /* 42449 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
15475 /* 42452 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
15476 /* 42457 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15477 /* 42460 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15478 /* 42463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15479 /* 42467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15480 /* 42471 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4087:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15481 /* 42471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhd),
15482 /* 42474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15483 /* 42476 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15484 /* 42478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15485 /* 42481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15486 /* 42487 */ GIR_RootConstrainSelectedInstOperands,
15487 /* 42488 */ // GIR_Coverage, 1448,
15488 /* 42488 */ GIR_EraseRootFromParent_Done,
15489 /* 42489 */ // Label 987: @42489
15490 /* 42489 */ GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(42534), // Rule ID 1449 //
15491 /* 42494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
15492 /* 42497 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
15493 /* 42502 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15494 /* 42505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15495 /* 42508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15496 /* 42512 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15497 /* 42516 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4087:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15498 /* 42516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhq),
15499 /* 42519 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15500 /* 42521 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15501 /* 42523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15502 /* 42526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15503 /* 42532 */ GIR_RootConstrainSelectedInstOperands,
15504 /* 42533 */ // GIR_Coverage, 1449,
15505 /* 42533 */ GIR_EraseRootFromParent_Done,
15506 /* 42534 */ // Label 988: @42534
15507 /* 42534 */ GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(42579), // Rule ID 1454 //
15508 /* 42539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15509 /* 42542 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
15510 /* 42547 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15511 /* 42550 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15512 /* 42553 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15513 /* 42557 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15514 /* 42561 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4094:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
15515 /* 42561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEd),
15516 /* 42564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15517 /* 42566 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15518 /* 42568 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15519 /* 42571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15520 /* 42577 */ GIR_RootConstrainSelectedInstOperands,
15521 /* 42578 */ // GIR_Coverage, 1454,
15522 /* 42578 */ GIR_EraseRootFromParent_Done,
15523 /* 42579 */ // Label 989: @42579
15524 /* 42579 */ GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(42624), // Rule ID 1455 //
15525 /* 42584 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15526 /* 42587 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
15527 /* 42592 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15528 /* 42595 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15529 /* 42598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15530 /* 42602 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15531 /* 42606 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4094:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
15532 /* 42606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEq),
15533 /* 42609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15534 /* 42611 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15535 /* 42613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15536 /* 42616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15537 /* 42622 */ GIR_RootConstrainSelectedInstOperands,
15538 /* 42623 */ // GIR_Coverage, 1455,
15539 /* 42623 */ GIR_EraseRootFromParent_Done,
15540 /* 42624 */ // Label 990: @42624
15541 /* 42624 */ GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(42669), // Rule ID 1456 //
15542 /* 42629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15543 /* 42632 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
15544 /* 42637 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15545 /* 42640 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15546 /* 42643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15547 /* 42647 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15548 /* 42651 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4094:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15549 /* 42651 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfd),
15550 /* 42654 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15551 /* 42656 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15552 /* 42658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15553 /* 42661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15554 /* 42667 */ GIR_RootConstrainSelectedInstOperands,
15555 /* 42668 */ // GIR_Coverage, 1456,
15556 /* 42668 */ GIR_EraseRootFromParent_Done,
15557 /* 42669 */ // Label 991: @42669
15558 /* 42669 */ GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(42714), // Rule ID 1457 //
15559 /* 42674 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15560 /* 42677 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
15561 /* 42682 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15562 /* 42685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15563 /* 42688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15564 /* 42692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15565 /* 42696 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4094:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15566 /* 42696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfq),
15567 /* 42699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15568 /* 42701 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15569 /* 42703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15570 /* 42706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15571 /* 42712 */ GIR_RootConstrainSelectedInstOperands,
15572 /* 42713 */ // GIR_Coverage, 1457,
15573 /* 42713 */ GIR_EraseRootFromParent_Done,
15574 /* 42714 */ // Label 992: @42714
15575 /* 42714 */ GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(42759), // Rule ID 1458 //
15576 /* 42719 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
15577 /* 42722 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
15578 /* 42727 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15579 /* 42730 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15580 /* 42733 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15581 /* 42737 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15582 /* 42741 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4094:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15583 /* 42741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhd),
15584 /* 42744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15585 /* 42746 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15586 /* 42748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15587 /* 42751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15588 /* 42757 */ GIR_RootConstrainSelectedInstOperands,
15589 /* 42758 */ // GIR_Coverage, 1458,
15590 /* 42758 */ GIR_EraseRootFromParent_Done,
15591 /* 42759 */ // Label 993: @42759
15592 /* 42759 */ GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(42804), // Rule ID 1459 //
15593 /* 42764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
15594 /* 42767 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
15595 /* 42772 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15596 /* 42775 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15597 /* 42778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15598 /* 42782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15599 /* 42786 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4094:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15600 /* 42786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhq),
15601 /* 42789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15602 /* 42791 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15603 /* 42793 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15604 /* 42796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15605 /* 42802 */ GIR_RootConstrainSelectedInstOperands,
15606 /* 42803 */ // GIR_Coverage, 1459,
15607 /* 42803 */ GIR_EraseRootFromParent_Done,
15608 /* 42804 */ // Label 994: @42804
15609 /* 42804 */ GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(42849), // Rule ID 1680 //
15610 /* 42809 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15611 /* 42812 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
15612 /* 42817 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
15613 /* 42820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
15614 /* 42823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15615 /* 42827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15616 /* 42831 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4065:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
15617 /* 42831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i8),
15618 /* 42834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15619 /* 42836 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15620 /* 42838 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15621 /* 42841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15622 /* 42847 */ GIR_RootConstrainSelectedInstOperands,
15623 /* 42848 */ // GIR_Coverage, 1680,
15624 /* 42848 */ GIR_EraseRootFromParent_Done,
15625 /* 42849 */ // Label 995: @42849
15626 /* 42849 */ GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(42894), // Rule ID 1681 //
15627 /* 42854 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15628 /* 42857 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
15629 /* 42862 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15630 /* 42865 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15631 /* 42868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15632 /* 42872 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15633 /* 42876 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4065:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
15634 /* 42876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i16),
15635 /* 42879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15636 /* 42881 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15637 /* 42883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15638 /* 42886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15639 /* 42892 */ GIR_RootConstrainSelectedInstOperands,
15640 /* 42893 */ // GIR_Coverage, 1681,
15641 /* 42893 */ GIR_EraseRootFromParent_Done,
15642 /* 42894 */ // Label 996: @42894
15643 /* 42894 */ GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(42939), // Rule ID 1682 //
15644 /* 42899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15645 /* 42902 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
15646 /* 42907 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15647 /* 42910 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15648 /* 42913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15649 /* 42917 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15650 /* 42921 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4065:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
15651 /* 42921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv2i32),
15652 /* 42924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15653 /* 42926 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15654 /* 42928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15655 /* 42931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15656 /* 42937 */ GIR_RootConstrainSelectedInstOperands,
15657 /* 42938 */ // GIR_Coverage, 1682,
15658 /* 42938 */ GIR_EraseRootFromParent_Done,
15659 /* 42939 */ // Label 997: @42939
15660 /* 42939 */ GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(42984), // Rule ID 1683 //
15661 /* 42944 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15662 /* 42947 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
15663 /* 42952 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
15664 /* 42955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15665 /* 42958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15666 /* 42962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15667 /* 42966 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4065:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
15668 /* 42966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv16i8),
15669 /* 42969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15670 /* 42971 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15671 /* 42973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15672 /* 42976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15673 /* 42982 */ GIR_RootConstrainSelectedInstOperands,
15674 /* 42983 */ // GIR_Coverage, 1683,
15675 /* 42983 */ GIR_EraseRootFromParent_Done,
15676 /* 42984 */ // Label 998: @42984
15677 /* 42984 */ GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(43029), // Rule ID 1684 //
15678 /* 42989 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15679 /* 42992 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
15680 /* 42997 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15681 /* 43000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15682 /* 43003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15683 /* 43007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15684 /* 43011 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4065:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
15685 /* 43011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i16),
15686 /* 43014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15687 /* 43016 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15688 /* 43018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15689 /* 43021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15690 /* 43027 */ GIR_RootConstrainSelectedInstOperands,
15691 /* 43028 */ // GIR_Coverage, 1684,
15692 /* 43028 */ GIR_EraseRootFromParent_Done,
15693 /* 43029 */ // Label 999: @43029
15694 /* 43029 */ GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(43074), // Rule ID 1685 //
15695 /* 43034 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15696 /* 43037 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
15697 /* 43042 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15698 /* 43045 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15699 /* 43048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15700 /* 43052 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15701 /* 43056 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4065:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
15702 /* 43056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i32),
15703 /* 43059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15704 /* 43061 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15705 /* 43063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15706 /* 43066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15707 /* 43072 */ GIR_RootConstrainSelectedInstOperands,
15708 /* 43073 */ // GIR_Coverage, 1685,
15709 /* 43073 */ GIR_EraseRootFromParent_Done,
15710 /* 43074 */ // Label 1000: @43074
15711 /* 43074 */ GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(43119), // Rule ID 1696 //
15712 /* 43079 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15713 /* 43082 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
15714 /* 43087 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
15715 /* 43090 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
15716 /* 43093 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15717 /* 43097 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15718 /* 43101 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4071:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQNEGv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
15719 /* 43101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i8),
15720 /* 43104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15721 /* 43106 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15722 /* 43108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15723 /* 43111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15724 /* 43117 */ GIR_RootConstrainSelectedInstOperands,
15725 /* 43118 */ // GIR_Coverage, 1696,
15726 /* 43118 */ GIR_EraseRootFromParent_Done,
15727 /* 43119 */ // Label 1001: @43119
15728 /* 43119 */ GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(43164), // Rule ID 1697 //
15729 /* 43124 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15730 /* 43127 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
15731 /* 43132 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15732 /* 43135 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15733 /* 43138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15734 /* 43142 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15735 /* 43146 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4071:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQNEGv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
15736 /* 43146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i16),
15737 /* 43149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15738 /* 43151 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15739 /* 43153 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15740 /* 43156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15741 /* 43162 */ GIR_RootConstrainSelectedInstOperands,
15742 /* 43163 */ // GIR_Coverage, 1697,
15743 /* 43163 */ GIR_EraseRootFromParent_Done,
15744 /* 43164 */ // Label 1002: @43164
15745 /* 43164 */ GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(43209), // Rule ID 1698 //
15746 /* 43169 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15747 /* 43172 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
15748 /* 43177 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15749 /* 43180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15750 /* 43183 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15751 /* 43187 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15752 /* 43191 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4071:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQNEGv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
15753 /* 43191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv2i32),
15754 /* 43194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15755 /* 43196 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15756 /* 43198 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15757 /* 43201 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15758 /* 43207 */ GIR_RootConstrainSelectedInstOperands,
15759 /* 43208 */ // GIR_Coverage, 1698,
15760 /* 43208 */ GIR_EraseRootFromParent_Done,
15761 /* 43209 */ // Label 1003: @43209
15762 /* 43209 */ GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(43254), // Rule ID 1699 //
15763 /* 43214 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15764 /* 43217 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
15765 /* 43222 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
15766 /* 43225 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15767 /* 43228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15768 /* 43232 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15769 /* 43236 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4071:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQNEGv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
15770 /* 43236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv16i8),
15771 /* 43239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15772 /* 43241 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15773 /* 43243 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15774 /* 43246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15775 /* 43252 */ GIR_RootConstrainSelectedInstOperands,
15776 /* 43253 */ // GIR_Coverage, 1699,
15777 /* 43253 */ GIR_EraseRootFromParent_Done,
15778 /* 43254 */ // Label 1004: @43254
15779 /* 43254 */ GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(43299), // Rule ID 1700 //
15780 /* 43259 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15781 /* 43262 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
15782 /* 43267 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15783 /* 43270 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15784 /* 43273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15785 /* 43277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15786 /* 43281 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4071:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQNEGv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
15787 /* 43281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i16),
15788 /* 43284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15789 /* 43286 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15790 /* 43288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15791 /* 43291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15792 /* 43297 */ GIR_RootConstrainSelectedInstOperands,
15793 /* 43298 */ // GIR_Coverage, 1700,
15794 /* 43298 */ GIR_EraseRootFromParent_Done,
15795 /* 43299 */ // Label 1005: @43299
15796 /* 43299 */ GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(43344), // Rule ID 1701 //
15797 /* 43304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15798 /* 43307 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
15799 /* 43312 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15800 /* 43315 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15801 /* 43318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15802 /* 43322 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15803 /* 43326 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4071:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQNEGv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
15804 /* 43326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i32),
15805 /* 43329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15806 /* 43331 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15807 /* 43333 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15808 /* 43336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15809 /* 43342 */ GIR_RootConstrainSelectedInstOperands,
15810 /* 43343 */ // GIR_Coverage, 1701,
15811 /* 43343 */ GIR_EraseRootFromParent_Done,
15812 /* 43344 */ // Label 1006: @43344
15813 /* 43344 */ GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(43389), // Rule ID 1751 //
15814 /* 43349 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15815 /* 43352 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns),
15816 /* 43357 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
15817 /* 43360 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15818 /* 43363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15819 /* 43367 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15820 /* 43371 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4068:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
15821 /* 43371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv8i8),
15822 /* 43374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15823 /* 43376 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15824 /* 43378 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15825 /* 43381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15826 /* 43387 */ GIR_RootConstrainSelectedInstOperands,
15827 /* 43388 */ // GIR_Coverage, 1751,
15828 /* 43388 */ GIR_EraseRootFromParent_Done,
15829 /* 43389 */ // Label 1007: @43389
15830 /* 43389 */ GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(43434), // Rule ID 1752 //
15831 /* 43394 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15832 /* 43397 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns),
15833 /* 43402 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15834 /* 43405 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15835 /* 43408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15836 /* 43412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15837 /* 43416 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4068:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
15838 /* 43416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv4i16),
15839 /* 43419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15840 /* 43421 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15841 /* 43423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15842 /* 43426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15843 /* 43432 */ GIR_RootConstrainSelectedInstOperands,
15844 /* 43433 */ // GIR_Coverage, 1752,
15845 /* 43433 */ GIR_EraseRootFromParent_Done,
15846 /* 43434 */ // Label 1008: @43434
15847 /* 43434 */ GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(43479), // Rule ID 1753 //
15848 /* 43439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15849 /* 43442 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns),
15850 /* 43447 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15851 /* 43450 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
15852 /* 43453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15853 /* 43457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15854 /* 43461 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4068:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
15855 /* 43461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv2i32),
15856 /* 43464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15857 /* 43466 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15858 /* 43468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15859 /* 43471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15860 /* 43477 */ GIR_RootConstrainSelectedInstOperands,
15861 /* 43478 */ // GIR_Coverage, 1753,
15862 /* 43478 */ GIR_EraseRootFromParent_Done,
15863 /* 43479 */ // Label 1009: @43479
15864 /* 43479 */ GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(43524), // Rule ID 1754 //
15865 /* 43484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15866 /* 43487 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu),
15867 /* 43492 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
15868 /* 43495 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15869 /* 43498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15870 /* 43502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15871 /* 43506 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4070:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
15872 /* 43506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv8i8),
15873 /* 43509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15874 /* 43511 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15875 /* 43513 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15876 /* 43516 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15877 /* 43522 */ GIR_RootConstrainSelectedInstOperands,
15878 /* 43523 */ // GIR_Coverage, 1754,
15879 /* 43523 */ GIR_EraseRootFromParent_Done,
15880 /* 43524 */ // Label 1010: @43524
15881 /* 43524 */ GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(43569), // Rule ID 1755 //
15882 /* 43529 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15883 /* 43532 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu),
15884 /* 43537 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15885 /* 43540 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15886 /* 43543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15887 /* 43547 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15888 /* 43551 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4070:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
15889 /* 43551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv4i16),
15890 /* 43554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15891 /* 43556 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15892 /* 43558 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15893 /* 43561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15894 /* 43567 */ GIR_RootConstrainSelectedInstOperands,
15895 /* 43568 */ // GIR_Coverage, 1755,
15896 /* 43568 */ GIR_EraseRootFromParent_Done,
15897 /* 43569 */ // Label 1011: @43569
15898 /* 43569 */ GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(43614), // Rule ID 1756 //
15899 /* 43574 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15900 /* 43577 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu),
15901 /* 43582 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15902 /* 43585 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
15903 /* 43588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15904 /* 43592 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15905 /* 43596 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4070:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
15906 /* 43596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv2i32),
15907 /* 43599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15908 /* 43601 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15909 /* 43603 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15910 /* 43606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15911 /* 43612 */ GIR_RootConstrainSelectedInstOperands,
15912 /* 43613 */ // GIR_Coverage, 1756,
15913 /* 43613 */ GIR_EraseRootFromParent_Done,
15914 /* 43614 */ // Label 1012: @43614
15915 /* 43614 */ GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(43659), // Rule ID 1757 //
15916 /* 43619 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15917 /* 43622 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu),
15918 /* 43627 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
15919 /* 43630 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15920 /* 43633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15921 /* 43637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15922 /* 43641 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4069:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
15923 /* 43641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv8i8),
15924 /* 43644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15925 /* 43646 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15926 /* 43648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15927 /* 43651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15928 /* 43657 */ GIR_RootConstrainSelectedInstOperands,
15929 /* 43658 */ // GIR_Coverage, 1757,
15930 /* 43658 */ GIR_EraseRootFromParent_Done,
15931 /* 43659 */ // Label 1013: @43659
15932 /* 43659 */ GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(43704), // Rule ID 1758 //
15933 /* 43664 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15934 /* 43667 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu),
15935 /* 43672 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15936 /* 43675 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15937 /* 43678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15938 /* 43682 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15939 /* 43686 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4069:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
15940 /* 43686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv4i16),
15941 /* 43689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15942 /* 43691 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15943 /* 43693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15944 /* 43696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15945 /* 43702 */ GIR_RootConstrainSelectedInstOperands,
15946 /* 43703 */ // GIR_Coverage, 1758,
15947 /* 43703 */ GIR_EraseRootFromParent_Done,
15948 /* 43704 */ // Label 1014: @43704
15949 /* 43704 */ GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(43749), // Rule ID 1759 //
15950 /* 43709 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15951 /* 43712 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu),
15952 /* 43717 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15953 /* 43720 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
15954 /* 43723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15955 /* 43727 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15956 /* 43731 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4069:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
15957 /* 43731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv2i32),
15958 /* 43734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15959 /* 43736 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15960 /* 43738 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15961 /* 43741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15962 /* 43747 */ GIR_RootConstrainSelectedInstOperands,
15963 /* 43748 */ // GIR_Coverage, 1759,
15964 /* 43748 */ GIR_EraseRootFromParent_Done,
15965 /* 43749 */ // Label 1015: @43749
15966 /* 43749 */ GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(43785), // Rule ID 1782 //
15967 /* 43754 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15968 /* 43757 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
15969 /* 43762 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15970 /* 43765 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15971 /* 43768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15972 /* 43772 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15973 /* 43776 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4013:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15974 /* 43776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDf),
15975 /* 43779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15976 /* 43781 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15977 /* 43783 */ GIR_RootConstrainSelectedInstOperands,
15978 /* 43784 */ // GIR_Coverage, 1782,
15979 /* 43784 */ GIR_EraseRootFromParent_Done,
15980 /* 43785 */ // Label 1016: @43785
15981 /* 43785 */ GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(43821), // Rule ID 1783 //
15982 /* 43790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15983 /* 43793 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
15984 /* 43798 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15985 /* 43801 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15986 /* 43804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15987 /* 43808 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15988 /* 43812 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4013:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15989 /* 43812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQf),
15990 /* 43815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15991 /* 43817 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15992 /* 43819 */ GIR_RootConstrainSelectedInstOperands,
15993 /* 43820 */ // GIR_Coverage, 1783,
15994 /* 43820 */ GIR_EraseRootFromParent_Done,
15995 /* 43821 */ // Label 1017: @43821
15996 /* 43821 */ GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(43857), // Rule ID 1784 //
15997 /* 43826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
15998 /* 43829 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
15999 /* 43834 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16000 /* 43837 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
16001 /* 43840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16002 /* 43844 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16003 /* 43848 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4014:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
16004 /* 43848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDf),
16005 /* 43851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16006 /* 43853 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16007 /* 43855 */ GIR_RootConstrainSelectedInstOperands,
16008 /* 43856 */ // GIR_Coverage, 1784,
16009 /* 43856 */ GIR_EraseRootFromParent_Done,
16010 /* 43857 */ // Label 1018: @43857
16011 /* 43857 */ GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(43893), // Rule ID 1785 //
16012 /* 43862 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16013 /* 43865 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
16014 /* 43870 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16015 /* 43873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16016 /* 43876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16017 /* 43880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16018 /* 43884 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4014:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
16019 /* 43884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQf),
16020 /* 43887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16021 /* 43889 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16022 /* 43891 */ GIR_RootConstrainSelectedInstOperands,
16023 /* 43892 */ // GIR_Coverage, 1785,
16024 /* 43892 */ GIR_EraseRootFromParent_Done,
16025 /* 43893 */ // Label 1019: @43893
16026 /* 43893 */ GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(43929), // Rule ID 1786 //
16027 /* 43898 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16028 /* 43901 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
16029 /* 43906 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16030 /* 43909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16031 /* 43912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16032 /* 43916 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16033 /* 43920 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4013:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16034 /* 43920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDh),
16035 /* 43923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16036 /* 43925 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16037 /* 43927 */ GIR_RootConstrainSelectedInstOperands,
16038 /* 43928 */ // GIR_Coverage, 1786,
16039 /* 43928 */ GIR_EraseRootFromParent_Done,
16040 /* 43929 */ // Label 1020: @43929
16041 /* 43929 */ GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(43965), // Rule ID 1787 //
16042 /* 43934 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16043 /* 43937 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
16044 /* 43942 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16045 /* 43945 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16046 /* 43948 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16047 /* 43952 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16048 /* 43956 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4013:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16049 /* 43956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQh),
16050 /* 43959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16051 /* 43961 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16052 /* 43963 */ GIR_RootConstrainSelectedInstOperands,
16053 /* 43964 */ // GIR_Coverage, 1787,
16054 /* 43964 */ GIR_EraseRootFromParent_Done,
16055 /* 43965 */ // Label 1021: @43965
16056 /* 43965 */ GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(44001), // Rule ID 1788 //
16057 /* 43970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16058 /* 43973 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
16059 /* 43978 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16060 /* 43981 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16061 /* 43984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16062 /* 43988 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16063 /* 43992 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4014:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16064 /* 43992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDh),
16065 /* 43995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16066 /* 43997 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16067 /* 43999 */ GIR_RootConstrainSelectedInstOperands,
16068 /* 44000 */ // GIR_Coverage, 1788,
16069 /* 44000 */ GIR_EraseRootFromParent_Done,
16070 /* 44001 */ // Label 1022: @44001
16071 /* 44001 */ GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(44037), // Rule ID 1789 //
16072 /* 44006 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16073 /* 44009 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
16074 /* 44014 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16075 /* 44017 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16076 /* 44020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16077 /* 44024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16078 /* 44028 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4014:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16079 /* 44028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQh),
16080 /* 44031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16081 /* 44033 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16082 /* 44035 */ GIR_RootConstrainSelectedInstOperands,
16083 /* 44036 */ // GIR_Coverage, 1789,
16084 /* 44036 */ GIR_EraseRootFromParent_Done,
16085 /* 44037 */ // Label 1023: @44037
16086 /* 44037 */ GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(44073), // Rule ID 1790 //
16087 /* 44042 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16088 /* 44045 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
16089 /* 44050 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16090 /* 44053 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
16091 /* 44056 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16092 /* 44060 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16093 /* 44064 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4025:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
16094 /* 44064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDf),
16095 /* 44067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16096 /* 44069 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16097 /* 44071 */ GIR_RootConstrainSelectedInstOperands,
16098 /* 44072 */ // GIR_Coverage, 1790,
16099 /* 44072 */ GIR_EraseRootFromParent_Done,
16100 /* 44073 */ // Label 1024: @44073
16101 /* 44073 */ GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(44109), // Rule ID 1791 //
16102 /* 44078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16103 /* 44081 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
16104 /* 44086 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16105 /* 44089 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16106 /* 44092 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16107 /* 44096 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16108 /* 44100 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4025:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
16109 /* 44100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQf),
16110 /* 44103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16111 /* 44105 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16112 /* 44107 */ GIR_RootConstrainSelectedInstOperands,
16113 /* 44108 */ // GIR_Coverage, 1791,
16114 /* 44108 */ GIR_EraseRootFromParent_Done,
16115 /* 44109 */ // Label 1025: @44109
16116 /* 44109 */ GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(44145), // Rule ID 1792 //
16117 /* 44114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16118 /* 44117 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
16119 /* 44122 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16120 /* 44125 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
16121 /* 44128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16122 /* 44132 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16123 /* 44136 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4026:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
16124 /* 44136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDf),
16125 /* 44139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16126 /* 44141 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16127 /* 44143 */ GIR_RootConstrainSelectedInstOperands,
16128 /* 44144 */ // GIR_Coverage, 1792,
16129 /* 44144 */ GIR_EraseRootFromParent_Done,
16130 /* 44145 */ // Label 1026: @44145
16131 /* 44145 */ GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(44181), // Rule ID 1793 //
16132 /* 44150 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16133 /* 44153 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
16134 /* 44158 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16135 /* 44161 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16136 /* 44164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16137 /* 44168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16138 /* 44172 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4026:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
16139 /* 44172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQf),
16140 /* 44175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16141 /* 44177 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16142 /* 44179 */ GIR_RootConstrainSelectedInstOperands,
16143 /* 44180 */ // GIR_Coverage, 1793,
16144 /* 44180 */ GIR_EraseRootFromParent_Done,
16145 /* 44181 */ // Label 1027: @44181
16146 /* 44181 */ GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(44217), // Rule ID 1794 //
16147 /* 44186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16148 /* 44189 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
16149 /* 44194 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16150 /* 44197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16151 /* 44200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16152 /* 44204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16153 /* 44208 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4025:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16154 /* 44208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDh),
16155 /* 44211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16156 /* 44213 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16157 /* 44215 */ GIR_RootConstrainSelectedInstOperands,
16158 /* 44216 */ // GIR_Coverage, 1794,
16159 /* 44216 */ GIR_EraseRootFromParent_Done,
16160 /* 44217 */ // Label 1028: @44217
16161 /* 44217 */ GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(44253), // Rule ID 1795 //
16162 /* 44222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16163 /* 44225 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
16164 /* 44230 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16165 /* 44233 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16166 /* 44236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16167 /* 44240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16168 /* 44244 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4025:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16169 /* 44244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQh),
16170 /* 44247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16171 /* 44249 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16172 /* 44251 */ GIR_RootConstrainSelectedInstOperands,
16173 /* 44252 */ // GIR_Coverage, 1795,
16174 /* 44252 */ GIR_EraseRootFromParent_Done,
16175 /* 44253 */ // Label 1029: @44253
16176 /* 44253 */ GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(44289), // Rule ID 1796 //
16177 /* 44258 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16178 /* 44261 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
16179 /* 44266 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16180 /* 44269 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16181 /* 44272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16182 /* 44276 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16183 /* 44280 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4026:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16184 /* 44280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDh),
16185 /* 44283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16186 /* 44285 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16187 /* 44287 */ GIR_RootConstrainSelectedInstOperands,
16188 /* 44288 */ // GIR_Coverage, 1796,
16189 /* 44288 */ GIR_EraseRootFromParent_Done,
16190 /* 44289 */ // Label 1030: @44289
16191 /* 44289 */ GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(44325), // Rule ID 1797 //
16192 /* 44294 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16193 /* 44297 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
16194 /* 44302 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16195 /* 44305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16196 /* 44308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16197 /* 44312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16198 /* 44316 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4026:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16199 /* 44316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQh),
16200 /* 44319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16201 /* 44321 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16202 /* 44323 */ GIR_RootConstrainSelectedInstOperands,
16203 /* 44324 */ // GIR_Coverage, 1797,
16204 /* 44324 */ GIR_EraseRootFromParent_Done,
16205 /* 44325 */ // Label 1031: @44325
16206 /* 44325 */ GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(44361), // Rule ID 1798 //
16207 /* 44330 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16208 /* 44333 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
16209 /* 44338 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16210 /* 44341 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
16211 /* 44344 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16212 /* 44348 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16213 /* 44352 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4027:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
16214 /* 44352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDf),
16215 /* 44355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16216 /* 44357 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16217 /* 44359 */ GIR_RootConstrainSelectedInstOperands,
16218 /* 44360 */ // GIR_Coverage, 1798,
16219 /* 44360 */ GIR_EraseRootFromParent_Done,
16220 /* 44361 */ // Label 1032: @44361
16221 /* 44361 */ GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(44397), // Rule ID 1799 //
16222 /* 44366 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16223 /* 44369 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
16224 /* 44374 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16225 /* 44377 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16226 /* 44380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16227 /* 44384 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16228 /* 44388 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4027:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
16229 /* 44388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQf),
16230 /* 44391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16231 /* 44393 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16232 /* 44395 */ GIR_RootConstrainSelectedInstOperands,
16233 /* 44396 */ // GIR_Coverage, 1799,
16234 /* 44396 */ GIR_EraseRootFromParent_Done,
16235 /* 44397 */ // Label 1033: @44397
16236 /* 44397 */ GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(44433), // Rule ID 1800 //
16237 /* 44402 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16238 /* 44405 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
16239 /* 44410 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16240 /* 44413 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
16241 /* 44416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16242 /* 44420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16243 /* 44424 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4028:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
16244 /* 44424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDf),
16245 /* 44427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16246 /* 44429 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16247 /* 44431 */ GIR_RootConstrainSelectedInstOperands,
16248 /* 44432 */ // GIR_Coverage, 1800,
16249 /* 44432 */ GIR_EraseRootFromParent_Done,
16250 /* 44433 */ // Label 1034: @44433
16251 /* 44433 */ GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(44469), // Rule ID 1801 //
16252 /* 44438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16253 /* 44441 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
16254 /* 44446 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16255 /* 44449 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16256 /* 44452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16257 /* 44456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16258 /* 44460 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4028:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
16259 /* 44460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQf),
16260 /* 44463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16261 /* 44465 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16262 /* 44467 */ GIR_RootConstrainSelectedInstOperands,
16263 /* 44468 */ // GIR_Coverage, 1801,
16264 /* 44468 */ GIR_EraseRootFromParent_Done,
16265 /* 44469 */ // Label 1035: @44469
16266 /* 44469 */ GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(44505), // Rule ID 1802 //
16267 /* 44474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16268 /* 44477 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
16269 /* 44482 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16270 /* 44485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16271 /* 44488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16272 /* 44492 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16273 /* 44496 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4027:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16274 /* 44496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDh),
16275 /* 44499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16276 /* 44501 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16277 /* 44503 */ GIR_RootConstrainSelectedInstOperands,
16278 /* 44504 */ // GIR_Coverage, 1802,
16279 /* 44504 */ GIR_EraseRootFromParent_Done,
16280 /* 44505 */ // Label 1036: @44505
16281 /* 44505 */ GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(44541), // Rule ID 1803 //
16282 /* 44510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16283 /* 44513 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
16284 /* 44518 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16285 /* 44521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16286 /* 44524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16287 /* 44528 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16288 /* 44532 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4027:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16289 /* 44532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQh),
16290 /* 44535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16291 /* 44537 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16292 /* 44539 */ GIR_RootConstrainSelectedInstOperands,
16293 /* 44540 */ // GIR_Coverage, 1803,
16294 /* 44540 */ GIR_EraseRootFromParent_Done,
16295 /* 44541 */ // Label 1037: @44541
16296 /* 44541 */ GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(44577), // Rule ID 1804 //
16297 /* 44546 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16298 /* 44549 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
16299 /* 44554 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16300 /* 44557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16301 /* 44560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16302 /* 44564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16303 /* 44568 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4028:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16304 /* 44568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDh),
16305 /* 44571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16306 /* 44573 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16307 /* 44575 */ GIR_RootConstrainSelectedInstOperands,
16308 /* 44576 */ // GIR_Coverage, 1804,
16309 /* 44576 */ GIR_EraseRootFromParent_Done,
16310 /* 44577 */ // Label 1038: @44577
16311 /* 44577 */ GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(44613), // Rule ID 1805 //
16312 /* 44582 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16313 /* 44585 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
16314 /* 44590 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16315 /* 44593 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16316 /* 44596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16317 /* 44600 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16318 /* 44604 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4028:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16319 /* 44604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQh),
16320 /* 44607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16321 /* 44609 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16322 /* 44611 */ GIR_RootConstrainSelectedInstOperands,
16323 /* 44612 */ // GIR_Coverage, 1805,
16324 /* 44612 */ GIR_EraseRootFromParent_Done,
16325 /* 44613 */ // Label 1039: @44613
16326 /* 44613 */ GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(44649), // Rule ID 1806 //
16327 /* 44618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16328 /* 44621 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
16329 /* 44626 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16330 /* 44629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
16331 /* 44632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16332 /* 44636 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16333 /* 44640 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4023:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
16334 /* 44640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDf),
16335 /* 44643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16336 /* 44645 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16337 /* 44647 */ GIR_RootConstrainSelectedInstOperands,
16338 /* 44648 */ // GIR_Coverage, 1806,
16339 /* 44648 */ GIR_EraseRootFromParent_Done,
16340 /* 44649 */ // Label 1040: @44649
16341 /* 44649 */ GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(44685), // Rule ID 1807 //
16342 /* 44654 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16343 /* 44657 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
16344 /* 44662 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16345 /* 44665 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16346 /* 44668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16347 /* 44672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16348 /* 44676 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4023:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
16349 /* 44676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQf),
16350 /* 44679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16351 /* 44681 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16352 /* 44683 */ GIR_RootConstrainSelectedInstOperands,
16353 /* 44684 */ // GIR_Coverage, 1807,
16354 /* 44684 */ GIR_EraseRootFromParent_Done,
16355 /* 44685 */ // Label 1041: @44685
16356 /* 44685 */ GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(44721), // Rule ID 1808 //
16357 /* 44690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16358 /* 44693 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
16359 /* 44698 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16360 /* 44701 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
16361 /* 44704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16362 /* 44708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16363 /* 44712 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4024:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
16364 /* 44712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDf),
16365 /* 44715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16366 /* 44717 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16367 /* 44719 */ GIR_RootConstrainSelectedInstOperands,
16368 /* 44720 */ // GIR_Coverage, 1808,
16369 /* 44720 */ GIR_EraseRootFromParent_Done,
16370 /* 44721 */ // Label 1042: @44721
16371 /* 44721 */ GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(44757), // Rule ID 1809 //
16372 /* 44726 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16373 /* 44729 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
16374 /* 44734 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16375 /* 44737 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16376 /* 44740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16377 /* 44744 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16378 /* 44748 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4024:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
16379 /* 44748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQf),
16380 /* 44751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16381 /* 44753 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16382 /* 44755 */ GIR_RootConstrainSelectedInstOperands,
16383 /* 44756 */ // GIR_Coverage, 1809,
16384 /* 44756 */ GIR_EraseRootFromParent_Done,
16385 /* 44757 */ // Label 1043: @44757
16386 /* 44757 */ GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(44793), // Rule ID 1810 //
16387 /* 44762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16388 /* 44765 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
16389 /* 44770 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16390 /* 44773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16391 /* 44776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16392 /* 44780 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16393 /* 44784 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4023:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16394 /* 44784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDh),
16395 /* 44787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16396 /* 44789 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16397 /* 44791 */ GIR_RootConstrainSelectedInstOperands,
16398 /* 44792 */ // GIR_Coverage, 1810,
16399 /* 44792 */ GIR_EraseRootFromParent_Done,
16400 /* 44793 */ // Label 1044: @44793
16401 /* 44793 */ GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(44829), // Rule ID 1811 //
16402 /* 44798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16403 /* 44801 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
16404 /* 44806 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16405 /* 44809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16406 /* 44812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16407 /* 44816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16408 /* 44820 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4023:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16409 /* 44820 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQh),
16410 /* 44823 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16411 /* 44825 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16412 /* 44827 */ GIR_RootConstrainSelectedInstOperands,
16413 /* 44828 */ // GIR_Coverage, 1811,
16414 /* 44828 */ GIR_EraseRootFromParent_Done,
16415 /* 44829 */ // Label 1045: @44829
16416 /* 44829 */ GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(44865), // Rule ID 1812 //
16417 /* 44834 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16418 /* 44837 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
16419 /* 44842 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16420 /* 44845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16421 /* 44848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16422 /* 44852 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16423 /* 44856 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4024:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16424 /* 44856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDh),
16425 /* 44859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16426 /* 44861 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16427 /* 44863 */ GIR_RootConstrainSelectedInstOperands,
16428 /* 44864 */ // GIR_Coverage, 1812,
16429 /* 44864 */ GIR_EraseRootFromParent_Done,
16430 /* 44865 */ // Label 1046: @44865
16431 /* 44865 */ GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(44901), // Rule ID 1813 //
16432 /* 44870 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16433 /* 44873 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
16434 /* 44878 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16435 /* 44881 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16436 /* 44884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16437 /* 44888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16438 /* 44892 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4024:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16439 /* 44892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQh),
16440 /* 44895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16441 /* 44897 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16442 /* 44899 */ GIR_RootConstrainSelectedInstOperands,
16443 /* 44900 */ // GIR_Coverage, 1813,
16444 /* 44900 */ GIR_EraseRootFromParent_Done,
16445 /* 44901 */ // Label 1047: @44901
16446 /* 44901 */ GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(44946), // Rule ID 1830 //
16447 /* 44906 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16_HasNEON),
16448 /* 44909 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2hf),
16449 /* 44914 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16450 /* 44917 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16451 /* 44920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16452 /* 44924 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16453 /* 44928 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4019:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTf2h:{ *:[v4i16] } QPR:{ *:[v4f32] }:$Vm)
16454 /* 44928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h),
16455 /* 44931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16456 /* 44933 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16457 /* 44935 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16458 /* 44938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16459 /* 44944 */ GIR_RootConstrainSelectedInstOperands,
16460 /* 44945 */ // GIR_Coverage, 1830,
16461 /* 44945 */ GIR_EraseRootFromParent_Done,
16462 /* 44946 */ // Label 1048: @44946
16463 /* 44946 */ GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(44991), // Rule ID 1831 //
16464 /* 44951 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16_HasNEON),
16465 /* 44954 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvthf2fp),
16466 /* 44959 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16467 /* 44962 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16468 /* 44965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16469 /* 44969 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16470 /* 44973 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4022:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4i16] }:$Vm)
16471 /* 44973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f),
16472 /* 44976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16473 /* 44978 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16474 /* 44980 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16475 /* 44983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16476 /* 44989 */ GIR_RootConstrainSelectedInstOperands,
16477 /* 44990 */ // GIR_Coverage, 1831,
16478 /* 44990 */ GIR_EraseRootFromParent_Done,
16479 /* 44991 */ // Label 1049: @44991
16480 /* 44991 */ GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(45027), // Rule ID 1903 //
16481 /* 44996 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8),
16482 /* 44999 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesimc),
16483 /* 45004 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
16484 /* 45007 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
16485 /* 45010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16486 /* 45014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16487 /* 45018 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3982:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESIMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
16488 /* 45018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESIMC),
16489 /* 45021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16490 /* 45023 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16491 /* 45025 */ GIR_RootConstrainSelectedInstOperands,
16492 /* 45026 */ // GIR_Coverage, 1903,
16493 /* 45026 */ GIR_EraseRootFromParent_Done,
16494 /* 45027 */ // Label 1050: @45027
16495 /* 45027 */ GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(45063), // Rule ID 1904 //
16496 /* 45032 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8),
16497 /* 45035 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesmc),
16498 /* 45040 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
16499 /* 45043 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
16500 /* 45046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16501 /* 45050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16502 /* 45054 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3983:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
16503 /* 45054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESMC),
16504 /* 45057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16505 /* 45059 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16506 /* 45061 */ GIR_RootConstrainSelectedInstOperands,
16507 /* 45062 */ // GIR_Coverage, 1904,
16508 /* 45062 */ GIR_EraseRootFromParent_Done,
16509 /* 45063 */ // Label 1051: @45063
16510 /* 45063 */ GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(45111), // Rule ID 2037 //
16511 /* 45068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
16512 /* 45071 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16),
16513 /* 45076 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16514 /* 45079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16515 /* 45082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16516 /* 45086 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
16517 /* 45090 */ // (intrinsic_wo_chain:{ *:[i32] } 4176:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (SXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
16518 /* 45090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB16),
16519 /* 45093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16520 /* 45095 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src
16521 /* 45097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16522 /* 45100 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16523 /* 45103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16524 /* 45109 */ GIR_RootConstrainSelectedInstOperands,
16525 /* 45110 */ // GIR_Coverage, 2037,
16526 /* 45110 */ GIR_EraseRootFromParent_Done,
16527 /* 45111 */ // Label 1052: @45111
16528 /* 45111 */ GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(45159), // Rule ID 2285 //
16529 /* 45116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
16530 /* 45119 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16),
16531 /* 45124 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16532 /* 45127 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16533 /* 45130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16534 /* 45134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16535 /* 45138 */ // (intrinsic_wo_chain:{ *:[i32] } 4176:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (t2SXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 0:{ *:[i32] })
16536 /* 45138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB16),
16537 /* 45141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16538 /* 45143 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16539 /* 45145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16540 /* 45148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16541 /* 45151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16542 /* 45157 */ GIR_RootConstrainSelectedInstOperands,
16543 /* 45158 */ // GIR_Coverage, 2285,
16544 /* 45158 */ GIR_EraseRootFromParent_Done,
16545 /* 45159 */ // Label 1053: @45159
16546 /* 45159 */ GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(45225), // Rule ID 4349 //
16547 /* 45164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16548 /* 45167 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn),
16549 /* 45172 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16550 /* 45175 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16551 /* 45178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16552 /* 45182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16553 /* 45186 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
16554 /* 45186 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16555 /* 45189 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16556 /* 45193 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16557 /* 45198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N),
16558 /* 45201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16559 /* 45203 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16560 /* 45205 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16561 /* 45208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16562 /* 45214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16563 /* 45220 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16564 /* 45223 */ GIR_RootConstrainSelectedInstOperands,
16565 /* 45224 */ // GIR_Coverage, 4349,
16566 /* 45224 */ GIR_EraseRootFromParent_Done,
16567 /* 45225 */ // Label 1054: @45225
16568 /* 45225 */ GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(45291), // Rule ID 4353 //
16569 /* 45230 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16570 /* 45233 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintx),
16571 /* 45238 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16572 /* 45241 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16573 /* 45244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16574 /* 45248 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16575 /* 45252 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3946:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
16576 /* 45252 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16577 /* 45255 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16578 /* 45259 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16579 /* 45264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X),
16580 /* 45267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16581 /* 45269 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16582 /* 45271 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16583 /* 45274 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16584 /* 45280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16585 /* 45286 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16586 /* 45289 */ GIR_RootConstrainSelectedInstOperands,
16587 /* 45290 */ // GIR_Coverage, 4353,
16588 /* 45290 */ GIR_EraseRootFromParent_Done,
16589 /* 45291 */ // Label 1055: @45291
16590 /* 45291 */ GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(45357), // Rule ID 4357 //
16591 /* 45296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16592 /* 45299 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrinta),
16593 /* 45304 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16594 /* 45307 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16595 /* 45310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16596 /* 45314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16597 /* 45318 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3938:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
16598 /* 45318 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16599 /* 45321 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16600 /* 45325 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16601 /* 45330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A),
16602 /* 45333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16603 /* 45335 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16604 /* 45337 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16605 /* 45340 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16606 /* 45346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16607 /* 45352 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16608 /* 45355 */ GIR_RootConstrainSelectedInstOperands,
16609 /* 45356 */ // GIR_Coverage, 4357,
16610 /* 45356 */ GIR_EraseRootFromParent_Done,
16611 /* 45357 */ // Label 1056: @45357
16612 /* 45357 */ GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(45423), // Rule ID 4361 //
16613 /* 45362 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16614 /* 45365 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintz),
16615 /* 45370 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16616 /* 45373 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16617 /* 45376 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16618 /* 45380 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16619 /* 45384 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3948:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
16620 /* 45384 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16621 /* 45387 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16622 /* 45391 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16623 /* 45396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z),
16624 /* 45399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16625 /* 45401 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16626 /* 45403 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16627 /* 45406 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16628 /* 45412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16629 /* 45418 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16630 /* 45421 */ GIR_RootConstrainSelectedInstOperands,
16631 /* 45422 */ // GIR_Coverage, 4361,
16632 /* 45422 */ GIR_EraseRootFromParent_Done,
16633 /* 45423 */ // Label 1057: @45423
16634 /* 45423 */ GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(45489), // Rule ID 4365 //
16635 /* 45428 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16636 /* 45431 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintm),
16637 /* 45436 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16638 /* 45439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16639 /* 45442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16640 /* 45446 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16641 /* 45450 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3940:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
16642 /* 45450 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16643 /* 45453 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16644 /* 45457 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16645 /* 45462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M),
16646 /* 45465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16647 /* 45467 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16648 /* 45469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16649 /* 45472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16650 /* 45478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16651 /* 45484 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16652 /* 45487 */ GIR_RootConstrainSelectedInstOperands,
16653 /* 45488 */ // GIR_Coverage, 4365,
16654 /* 45488 */ GIR_EraseRootFromParent_Done,
16655 /* 45489 */ // Label 1058: @45489
16656 /* 45489 */ GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(45555), // Rule ID 4369 //
16657 /* 45494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16658 /* 45497 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintp),
16659 /* 45502 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16660 /* 45505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16661 /* 45508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16662 /* 45512 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16663 /* 45516 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3944:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
16664 /* 45516 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16665 /* 45519 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16666 /* 45523 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16667 /* 45528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P),
16668 /* 45531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16669 /* 45533 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16670 /* 45535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16671 /* 45538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16672 /* 45544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16673 /* 45550 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16674 /* 45553 */ GIR_RootConstrainSelectedInstOperands,
16675 /* 45554 */ // GIR_Coverage, 4369,
16676 /* 45554 */ GIR_EraseRootFromParent_Done,
16677 /* 45555 */ // Label 1059: @45555
16678 /* 45555 */ GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(45621), // Rule ID 4373 //
16679 /* 45560 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16680 /* 45563 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn),
16681 /* 45568 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16682 /* 45571 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16683 /* 45574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16684 /* 45578 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16685 /* 45582 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3942:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
16686 /* 45582 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16687 /* 45585 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16688 /* 45589 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16689 /* 45594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N),
16690 /* 45597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16691 /* 45599 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16692 /* 45601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16693 /* 45604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16694 /* 45610 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16695 /* 45616 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16696 /* 45619 */ GIR_RootConstrainSelectedInstOperands,
16697 /* 45620 */ // GIR_Coverage, 4373,
16698 /* 45620 */ GIR_EraseRootFromParent_Done,
16699 /* 45621 */ // Label 1060: @45621
16700 /* 45621 */ GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(45687), // Rule ID 4377 //
16701 /* 45626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16702 /* 45629 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintx),
16703 /* 45634 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16704 /* 45637 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16705 /* 45640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16706 /* 45644 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16707 /* 45648 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3946:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
16708 /* 45648 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16709 /* 45651 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16710 /* 45655 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16711 /* 45660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X),
16712 /* 45663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16713 /* 45665 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16714 /* 45667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16715 /* 45670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16716 /* 45676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16717 /* 45682 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16718 /* 45685 */ GIR_RootConstrainSelectedInstOperands,
16719 /* 45686 */ // GIR_Coverage, 4377,
16720 /* 45686 */ GIR_EraseRootFromParent_Done,
16721 /* 45687 */ // Label 1061: @45687
16722 /* 45687 */ GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(45753), // Rule ID 4381 //
16723 /* 45692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16724 /* 45695 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrinta),
16725 /* 45700 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16726 /* 45703 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16727 /* 45706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16728 /* 45710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16729 /* 45714 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3938:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
16730 /* 45714 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16731 /* 45717 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16732 /* 45721 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16733 /* 45726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A),
16734 /* 45729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16735 /* 45731 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16736 /* 45733 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16737 /* 45736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16738 /* 45742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16739 /* 45748 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16740 /* 45751 */ GIR_RootConstrainSelectedInstOperands,
16741 /* 45752 */ // GIR_Coverage, 4381,
16742 /* 45752 */ GIR_EraseRootFromParent_Done,
16743 /* 45753 */ // Label 1062: @45753
16744 /* 45753 */ GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(45819), // Rule ID 4385 //
16745 /* 45758 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16746 /* 45761 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintz),
16747 /* 45766 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16748 /* 45769 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16749 /* 45772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16750 /* 45776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16751 /* 45780 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3948:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
16752 /* 45780 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16753 /* 45783 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16754 /* 45787 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16755 /* 45792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z),
16756 /* 45795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16757 /* 45797 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16758 /* 45799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16759 /* 45802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16760 /* 45808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16761 /* 45814 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16762 /* 45817 */ GIR_RootConstrainSelectedInstOperands,
16763 /* 45818 */ // GIR_Coverage, 4385,
16764 /* 45818 */ GIR_EraseRootFromParent_Done,
16765 /* 45819 */ // Label 1063: @45819
16766 /* 45819 */ GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(45885), // Rule ID 4389 //
16767 /* 45824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16768 /* 45827 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintm),
16769 /* 45832 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16770 /* 45835 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16771 /* 45838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16772 /* 45842 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16773 /* 45846 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3940:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
16774 /* 45846 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16775 /* 45849 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16776 /* 45853 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16777 /* 45858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M),
16778 /* 45861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16779 /* 45863 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16780 /* 45865 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16781 /* 45868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16782 /* 45874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16783 /* 45880 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16784 /* 45883 */ GIR_RootConstrainSelectedInstOperands,
16785 /* 45884 */ // GIR_Coverage, 4389,
16786 /* 45884 */ GIR_EraseRootFromParent_Done,
16787 /* 45885 */ // Label 1064: @45885
16788 /* 45885 */ GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(45951), // Rule ID 4393 //
16789 /* 45890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16790 /* 45893 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintp),
16791 /* 45898 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16792 /* 45901 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16793 /* 45904 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16794 /* 45908 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16795 /* 45912 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3944:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
16796 /* 45912 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16797 /* 45915 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16798 /* 45919 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16799 /* 45924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P),
16800 /* 45927 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16801 /* 45929 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16802 /* 45931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16803 /* 45934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16804 /* 45940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16805 /* 45946 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16806 /* 45949 */ GIR_RootConstrainSelectedInstOperands,
16807 /* 45950 */ // GIR_Coverage, 4393,
16808 /* 45950 */ GIR_EraseRootFromParent_Done,
16809 /* 45951 */ // Label 1065: @45951
16810 /* 45951 */ GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(46002), // Rule ID 5379 //
16811 /* 45956 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16812 /* 45959 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp8),
16813 /* 45964 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s1,
16814 /* 45967 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16815 /* 45970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16816 /* 45974 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16817 /* 45978 */ // (intrinsic_wo_chain:{ *:[v16i1] } 3861:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP8:{ *:[v16i1] } rGPR:{ *:[i32] }:$Rn)
16818 /* 45978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP8),
16819 /* 45981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
16820 /* 45983 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16821 /* 45985 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16822 /* 45988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16823 /* 45994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16824 /* 46000 */ GIR_RootConstrainSelectedInstOperands,
16825 /* 46001 */ // GIR_Coverage, 5379,
16826 /* 46001 */ GIR_EraseRootFromParent_Done,
16827 /* 46002 */ // Label 1066: @46002
16828 /* 46002 */ GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(46053), // Rule ID 5381 //
16829 /* 46007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16830 /* 46010 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp16),
16831 /* 46015 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
16832 /* 46018 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16833 /* 46021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16834 /* 46025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16835 /* 46029 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3858:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP16:{ *:[v8i1] } rGPR:{ *:[i32] }:$Rn)
16836 /* 46029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP16),
16837 /* 46032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
16838 /* 46034 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16839 /* 46036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16840 /* 46039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16841 /* 46045 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16842 /* 46051 */ GIR_RootConstrainSelectedInstOperands,
16843 /* 46052 */ // GIR_Coverage, 5381,
16844 /* 46052 */ GIR_EraseRootFromParent_Done,
16845 /* 46053 */ // Label 1067: @46053
16846 /* 46053 */ GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(46104), // Rule ID 5383 //
16847 /* 46058 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16848 /* 46061 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp32),
16849 /* 46066 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
16850 /* 46069 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16851 /* 46072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16852 /* 46076 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16853 /* 46080 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3859:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP32:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn)
16854 /* 46080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP32),
16855 /* 46083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
16856 /* 46085 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16857 /* 46087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16858 /* 46090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16859 /* 46096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16860 /* 46102 */ GIR_RootConstrainSelectedInstOperands,
16861 /* 46103 */ // GIR_Coverage, 5383,
16862 /* 46103 */ GIR_EraseRootFromParent_Done,
16863 /* 46104 */ // Label 1068: @46104
16864 /* 46104 */ GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(46155), // Rule ID 5385 //
16865 /* 46109 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16866 /* 46112 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp64),
16867 /* 46117 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s1,
16868 /* 46120 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16869 /* 46123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16870 /* 46127 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16871 /* 46131 */ // (intrinsic_wo_chain:{ *:[v2i1] } 3860:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP64:{ *:[v2i1] } rGPR:{ *:[i32] }:$Rn)
16872 /* 46131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP64),
16873 /* 46134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
16874 /* 46136 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16875 /* 46138 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16876 /* 46141 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16877 /* 46147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16878 /* 46153 */ GIR_RootConstrainSelectedInstOperands,
16879 /* 46154 */ // GIR_Coverage, 5385,
16880 /* 46154 */ GIR_EraseRootFromParent_Done,
16881 /* 46155 */ // Label 1069: @46155
16882 /* 46155 */ GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(46201), // Rule ID 599 //
16883 /* 46160 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb),
16884 /* 46163 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tt),
16885 /* 46168 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16886 /* 46171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16887 /* 46175 */ // MIs[0] Rn
16888 /* 46175 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16889 /* 46179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16890 /* 46183 */ // (intrinsic_wo_chain:{ *:[i32] } 3735:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16891 /* 46183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TT),
16892 /* 46186 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
16893 /* 46188 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16894 /* 46190 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16895 /* 46193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16896 /* 46199 */ GIR_RootConstrainSelectedInstOperands,
16897 /* 46200 */ // GIR_Coverage, 599,
16898 /* 46200 */ GIR_EraseRootFromParent_Done,
16899 /* 46201 */ // Label 1070: @46201
16900 /* 46201 */ GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(46247), // Rule ID 600 //
16901 /* 46206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb),
16902 /* 46209 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttt),
16903 /* 46214 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16904 /* 46217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16905 /* 46221 */ // MIs[0] Rn
16906 /* 46221 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16907 /* 46225 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16908 /* 46229 */ // (intrinsic_wo_chain:{ *:[i32] } 3738:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16909 /* 46229 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTT),
16910 /* 46232 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
16911 /* 46234 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16912 /* 46236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16913 /* 46239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16914 /* 46245 */ GIR_RootConstrainSelectedInstOperands,
16915 /* 46246 */ // GIR_Coverage, 600,
16916 /* 46246 */ GIR_EraseRootFromParent_Done,
16917 /* 46247 */ // Label 1071: @46247
16918 /* 46247 */ GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(46293), // Rule ID 601 //
16919 /* 46252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb),
16920 /* 46255 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tta),
16921 /* 46260 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16922 /* 46263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16923 /* 46267 */ // MIs[0] Rn
16924 /* 46267 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16925 /* 46271 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16926 /* 46275 */ // (intrinsic_wo_chain:{ *:[i32] } 3736:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16927 /* 46275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTA),
16928 /* 46278 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
16929 /* 46280 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16930 /* 46282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16931 /* 46285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16932 /* 46291 */ GIR_RootConstrainSelectedInstOperands,
16933 /* 46292 */ // GIR_Coverage, 601,
16934 /* 46292 */ GIR_EraseRootFromParent_Done,
16935 /* 46293 */ // Label 1072: @46293
16936 /* 46293 */ GIM_Try, /*On fail goto*//*Label 1073*/ GIMT_Encode4(46339), // Rule ID 602 //
16937 /* 46298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb),
16938 /* 46301 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttat),
16939 /* 46306 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16940 /* 46309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16941 /* 46313 */ // MIs[0] Rn
16942 /* 46313 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16943 /* 46317 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16944 /* 46321 */ // (intrinsic_wo_chain:{ *:[i32] } 3737:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTAT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16945 /* 46321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTAT),
16946 /* 46324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
16947 /* 46326 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16948 /* 46328 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16949 /* 46331 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16950 /* 46337 */ GIR_RootConstrainSelectedInstOperands,
16951 /* 46338 */ // GIR_Coverage, 602,
16952 /* 46338 */ GIR_EraseRootFromParent_Done,
16953 /* 46339 */ // Label 1073: @46339
16954 /* 46339 */ GIM_Try, /*On fail goto*//*Label 1074*/ GIMT_Encode4(46493), // Rule ID 3068 //
16955 /* 46344 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16956 /* 46347 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1h),
16957 /* 46352 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16958 /* 46355 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16959 /* 46358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
16960 /* 46362 */ // (intrinsic_wo_chain:{ *:[i32] } 3990:{ *:[iPTR] }, i32:{ *:[i32] }:$Rn) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[f32] } (SHA1H:{ *:[v16i8] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$Rn, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }), GPR:{ *:[i32] })
16961 /* 46362 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
16962 /* 46365 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16963 /* 46369 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16964 /* 46374 */ GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16965 /* 46378 */ GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
16966 /* 46383 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
16967 /* 46386 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16968 /* 46390 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16969 /* 46395 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
16970 /* 46397 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
16971 /* 46400 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
16972 /* 46404 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16973 /* 46409 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
16974 /* 46412 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
16975 /* 46415 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
16976 /* 46418 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
16977 /* 46423 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
16978 /* 46428 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
16979 /* 46433 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
16980 /* 46436 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::SHA1H),
16981 /* 46440 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16982 /* 46445 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
16983 /* 46448 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16984 /* 46450 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16985 /* 46453 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16986 /* 46457 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16987 /* 46462 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
16988 /* 46469 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
16989 /* 46474 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::MQPRRegClassID),
16990 /* 46479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16991 /* 46482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16992 /* 46484 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16993 /* 46487 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
16994 /* 46492 */ // GIR_Coverage, 3068,
16995 /* 46492 */ GIR_EraseRootFromParent_Done,
16996 /* 46493 */ // Label 1074: @46493
16997 /* 46493 */ GIM_Reject,
16998 /* 46494 */ // Label 964: @46494
16999 /* 46494 */ GIM_Try, /*On fail goto*//*Label 1075*/ GIMT_Encode4(69506),
17000 /* 46499 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
17001 /* 46502 */ GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(46559), // Rule ID 2303 //
17002 /* 46507 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
17003 /* 46510 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16),
17004 /* 46515 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17005 /* 46518 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17006 /* 46521 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17007 /* 46524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17008 /* 46528 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17009 /* 46532 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17010 /* 46536 */ // (intrinsic_wo_chain:{ *:[i32] } 4200:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
17011 /* 46536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB16),
17012 /* 46539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17013 /* 46541 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17014 /* 46543 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17015 /* 46545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17016 /* 46548 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17017 /* 46551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17018 /* 46557 */ GIR_RootConstrainSelectedInstOperands,
17019 /* 46558 */ // GIR_Coverage, 2303,
17020 /* 46558 */ GIR_EraseRootFromParent_Done,
17021 /* 46559 */ // Label 1076: @46559
17022 /* 46559 */ GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(46658), // Rule ID 2074 //
17023 /* 46564 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
17024 /* 46567 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
17025 /* 46572 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17026 /* 46575 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17027 /* 46578 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17028 /* 46581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17029 /* 46585 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17030 /* 46589 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
17031 /* 46593 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
17032 /* 46597 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17033 /* 46601 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17034 /* 46606 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17035 /* 46610 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17036 /* 46614 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17037 /* 46618 */ // MIs[2] Operand 1
17038 /* 46618 */ // No operand predicates
17039 /* 46618 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
17040 /* 46622 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17041 /* 46626 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17042 /* 46630 */ // MIs[3] Operand 1
17043 /* 46630 */ // No operand predicates
17044 /* 46630 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17045 /* 46632 */ // (intrinsic_wo_chain:{ *:[i32] } 4195:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft)
17046 /* 46632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT),
17047 /* 46635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17048 /* 46637 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos
17049 /* 46640 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
17050 /* 46644 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft
17051 /* 46647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17052 /* 46650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17053 /* 46656 */ GIR_RootConstrainSelectedInstOperands,
17054 /* 46657 */ // GIR_Coverage, 2074,
17055 /* 46657 */ GIR_EraseRootFromParent_Done,
17056 /* 46658 */ // Label 1077: @46658
17057 /* 46658 */ GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(46757), // Rule ID 2340 //
17058 /* 46663 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
17059 /* 46666 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
17060 /* 46671 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17061 /* 46674 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17062 /* 46677 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17063 /* 46680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17064 /* 46684 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17065 /* 46688 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
17066 /* 46692 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
17067 /* 46696 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17068 /* 46700 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17069 /* 46705 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17070 /* 46709 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17071 /* 46713 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17072 /* 46717 */ // MIs[2] Operand 1
17073 /* 46717 */ // No operand predicates
17074 /* 46717 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
17075 /* 46721 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17076 /* 46725 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17077 /* 46729 */ // MIs[3] Operand 1
17078 /* 46729 */ // No operand predicates
17079 /* 46729 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17080 /* 46731 */ // (intrinsic_wo_chain:{ *:[i32] } 4195:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft)
17081 /* 46731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT),
17082 /* 46734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17083 /* 46736 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos
17084 /* 46739 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
17085 /* 46743 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft
17086 /* 46746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17087 /* 46749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17088 /* 46755 */ GIR_RootConstrainSelectedInstOperands,
17089 /* 46756 */ // GIR_Coverage, 2340,
17090 /* 46756 */ GIR_EraseRootFromParent_Done,
17091 /* 46757 */ // Label 1078: @46757
17092 /* 46757 */ GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(46841), // Rule ID 5945 //
17093 /* 46762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17094 /* 46765 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17095 /* 46770 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17096 /* 46773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17097 /* 46776 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17098 /* 46779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17099 /* 46783 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17100 /* 46787 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
17101 /* 46791 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
17102 /* 46794 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17103 /* 46799 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17104 /* 46803 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17105 /* 46808 */ // MIs[1] Rn
17106 /* 46808 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
17107 /* 46813 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17108 /* 46817 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17109 /* 46819 */ // (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn), GPRnopc:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17110 /* 46819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
17111 /* 46822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17112 /* 46824 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17113 /* 46826 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
17114 /* 46830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17115 /* 46833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17116 /* 46839 */ GIR_RootConstrainSelectedInstOperands,
17117 /* 46840 */ // GIR_Coverage, 5945,
17118 /* 46840 */ GIR_EraseRootFromParent_Done,
17119 /* 46841 */ // Label 1079: @46841
17120 /* 46841 */ GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(46925), // Rule ID 6268 //
17121 /* 46846 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
17122 /* 46849 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17123 /* 46854 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17124 /* 46857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17125 /* 46860 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17126 /* 46863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17127 /* 46867 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17128 /* 46871 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
17129 /* 46875 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
17130 /* 46878 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17131 /* 46883 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17132 /* 46887 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17133 /* 46892 */ // MIs[1] Rn
17134 /* 46892 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
17135 /* 46897 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17136 /* 46901 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17137 /* 46903 */ // (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
17138 /* 46903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
17139 /* 46906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17140 /* 46908 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17141 /* 46910 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
17142 /* 46914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17143 /* 46917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17144 /* 46923 */ GIR_RootConstrainSelectedInstOperands,
17145 /* 46924 */ // GIR_Coverage, 6268,
17146 /* 46924 */ GIR_EraseRootFromParent_Done,
17147 /* 46925 */ // Label 1080: @46925
17148 /* 46925 */ GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(47009), // Rule ID 108 //
17149 /* 46930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17150 /* 46933 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17151 /* 46938 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17152 /* 46941 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17153 /* 46944 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17154 /* 46947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17155 /* 46951 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17156 /* 46955 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17157 /* 46959 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
17158 /* 46963 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
17159 /* 46966 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17160 /* 46971 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17161 /* 46975 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17162 /* 46980 */ // MIs[1] Rn
17163 /* 46980 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
17164 /* 46985 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17165 /* 46987 */ // (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17166 /* 46987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
17167 /* 46990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17168 /* 46992 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
17169 /* 46994 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
17170 /* 46998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17171 /* 47001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17172 /* 47007 */ GIR_RootConstrainSelectedInstOperands,
17173 /* 47008 */ // GIR_Coverage, 108,
17174 /* 47008 */ GIR_EraseRootFromParent_Done,
17175 /* 47009 */ // Label 1081: @47009
17176 /* 47009 */ GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(47093), // Rule ID 109 //
17177 /* 47014 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17178 /* 47017 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
17179 /* 47022 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17180 /* 47025 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17181 /* 47028 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17182 /* 47031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17183 /* 47035 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17184 /* 47039 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17185 /* 47043 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
17186 /* 47047 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
17187 /* 47050 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17188 /* 47055 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17189 /* 47059 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17190 /* 47064 */ // MIs[1] Rn
17191 /* 47064 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
17192 /* 47069 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17193 /* 47071 */ // (intrinsic_wo_chain:{ *:[i32] } 4123:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17194 /* 47071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB),
17195 /* 47074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17196 /* 47076 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
17197 /* 47078 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
17198 /* 47082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17199 /* 47085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17200 /* 47091 */ GIR_RootConstrainSelectedInstOperands,
17201 /* 47092 */ // GIR_Coverage, 109,
17202 /* 47092 */ GIR_EraseRootFromParent_Done,
17203 /* 47093 */ // Label 1082: @47093
17204 /* 47093 */ GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(47177), // Rule ID 2318 //
17205 /* 47098 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
17206 /* 47101 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17207 /* 47106 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17208 /* 47109 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17209 /* 47112 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17210 /* 47115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17211 /* 47119 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17212 /* 47123 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17213 /* 47127 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
17214 /* 47131 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
17215 /* 47134 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17216 /* 47139 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17217 /* 47143 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17218 /* 47148 */ // MIs[1] Rn
17219 /* 47148 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
17220 /* 47153 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17221 /* 47155 */ // (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
17222 /* 47155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
17223 /* 47158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17224 /* 47160 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
17225 /* 47162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
17226 /* 47166 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17227 /* 47169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17228 /* 47175 */ GIR_RootConstrainSelectedInstOperands,
17229 /* 47176 */ // GIR_Coverage, 2318,
17230 /* 47176 */ GIR_EraseRootFromParent_Done,
17231 /* 47177 */ // Label 1083: @47177
17232 /* 47177 */ GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(47261), // Rule ID 2319 //
17233 /* 47182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
17234 /* 47185 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
17235 /* 47190 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17236 /* 47193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17237 /* 47196 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17238 /* 47199 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17239 /* 47203 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17240 /* 47207 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17241 /* 47211 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
17242 /* 47215 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
17243 /* 47218 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17244 /* 47223 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17245 /* 47227 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17246 /* 47232 */ // MIs[1] Rn
17247 /* 47232 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
17248 /* 47237 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17249 /* 47239 */ // (intrinsic_wo_chain:{ *:[i32] } 4123:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
17250 /* 47239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB),
17251 /* 47242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17252 /* 47244 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
17253 /* 47246 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
17254 /* 47250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17255 /* 47253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17256 /* 47259 */ GIR_RootConstrainSelectedInstOperands,
17257 /* 47260 */ // GIR_Coverage, 2319,
17258 /* 47260 */ GIR_EraseRootFromParent_Done,
17259 /* 47261 */ // Label 1084: @47261
17260 /* 47261 */ GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(47353), // Rule ID 4558 //
17261 /* 47266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
17262 /* 47269 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm),
17263 /* 47274 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17264 /* 47277 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17265 /* 47280 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17266 /* 47283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17267 /* 47287 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17268 /* 47291 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
17269 /* 47295 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17270 /* 47299 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17271 /* 47304 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
17272 /* 47308 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
17273 /* 47312 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17274 /* 47316 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17275 /* 47321 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17276 /* 47323 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3898:{ *:[iPTR] }, (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
17277 /* 47323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32),
17278 /* 47326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17279 /* 47328 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
17280 /* 47332 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
17281 /* 47336 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17282 /* 47339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17283 /* 47345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17284 /* 47351 */ GIR_RootConstrainSelectedInstOperands,
17285 /* 47352 */ // GIR_Coverage, 4558,
17286 /* 47352 */ GIR_EraseRootFromParent_Done,
17287 /* 47353 */ // Label 1085: @47353
17288 /* 47353 */ GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(47445), // Rule ID 4561 //
17289 /* 47358 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
17290 /* 47361 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm),
17291 /* 47366 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17292 /* 47369 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17293 /* 47372 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17294 /* 47375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17295 /* 47379 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17296 /* 47383 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
17297 /* 47387 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17298 /* 47391 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17299 /* 47396 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
17300 /* 47400 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
17301 /* 47404 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
17302 /* 47408 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17303 /* 47413 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17304 /* 47415 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3898:{ *:[iPTR] }, (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
17305 /* 47415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16),
17306 /* 47418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17307 /* 47420 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
17308 /* 47424 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
17309 /* 47428 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17310 /* 47431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17311 /* 47437 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17312 /* 47443 */ GIR_RootConstrainSelectedInstOperands,
17313 /* 47444 */ // GIR_Coverage, 4561,
17314 /* 47444 */ GIR_EraseRootFromParent_Done,
17315 /* 47445 */ // Label 1086: @47445
17316 /* 47445 */ GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(47537), // Rule ID 4564 //
17317 /* 47450 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
17318 /* 47453 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm),
17319 /* 47458 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17320 /* 47461 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17321 /* 47464 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17322 /* 47467 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17323 /* 47471 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17324 /* 47475 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
17325 /* 47479 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17326 /* 47483 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17327 /* 47488 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
17328 /* 47492 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
17329 /* 47496 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17330 /* 47500 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17331 /* 47505 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17332 /* 47507 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3901:{ *:[iPTR] }, (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
17333 /* 47507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32),
17334 /* 47510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17335 /* 47512 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
17336 /* 47516 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
17337 /* 47520 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17338 /* 47523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17339 /* 47529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17340 /* 47535 */ GIR_RootConstrainSelectedInstOperands,
17341 /* 47536 */ // GIR_Coverage, 4564,
17342 /* 47536 */ GIR_EraseRootFromParent_Done,
17343 /* 47537 */ // Label 1087: @47537
17344 /* 47537 */ GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(47629), // Rule ID 4567 //
17345 /* 47542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
17346 /* 47545 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm),
17347 /* 47550 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17348 /* 47553 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17349 /* 47556 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17350 /* 47559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17351 /* 47563 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17352 /* 47567 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
17353 /* 47571 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17354 /* 47575 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17355 /* 47580 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
17356 /* 47584 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
17357 /* 47588 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
17358 /* 47592 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17359 /* 47597 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17360 /* 47599 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3901:{ *:[iPTR] }, (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
17361 /* 47599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16),
17362 /* 47602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17363 /* 47604 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
17364 /* 47608 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
17365 /* 47612 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17366 /* 47615 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17367 /* 47621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17368 /* 47627 */ GIR_RootConstrainSelectedInstOperands,
17369 /* 47628 */ // GIR_Coverage, 4567,
17370 /* 47628 */ GIR_EraseRootFromParent_Done,
17371 /* 47629 */ // Label 1088: @47629
17372 /* 47629 */ GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(47702), // Rule ID 4489 //
17373 /* 47634 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17374 /* 47637 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
17375 /* 47642 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17376 /* 47645 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17377 /* 47648 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17378 /* 47651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17379 /* 47655 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17380 /* 47659 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17381 /* 47663 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3871:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17382 /* 47663 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17383 /* 47666 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17384 /* 47670 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17385 /* 47675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16a),
17386 /* 47678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17387 /* 47680 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17388 /* 47682 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17389 /* 47685 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17390 /* 47691 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17391 /* 47697 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17392 /* 47700 */ GIR_RootConstrainSelectedInstOperands,
17393 /* 47701 */ // GIR_Coverage, 4489,
17394 /* 47701 */ GIR_EraseRootFromParent_Done,
17395 /* 47702 */ // Label 1089: @47702
17396 /* 47702 */ GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(47775), // Rule ID 4491 //
17397 /* 47707 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17398 /* 47710 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
17399 /* 47715 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17400 /* 47718 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17401 /* 47721 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17402 /* 47724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17403 /* 47728 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17404 /* 47732 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17405 /* 47736 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3875:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17406 /* 47736 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17407 /* 47739 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17408 /* 47743 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17409 /* 47748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16n),
17410 /* 47751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17411 /* 47753 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17412 /* 47755 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17413 /* 47758 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17414 /* 47764 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17415 /* 47770 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17416 /* 47773 */ GIR_RootConstrainSelectedInstOperands,
17417 /* 47774 */ // GIR_Coverage, 4491,
17418 /* 47774 */ GIR_EraseRootFromParent_Done,
17419 /* 47775 */ // Label 1090: @47775
17420 /* 47775 */ GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(47848), // Rule ID 4493 //
17421 /* 47780 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17422 /* 47783 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
17423 /* 47788 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17424 /* 47791 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17425 /* 47794 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17426 /* 47797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17427 /* 47801 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17428 /* 47805 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17429 /* 47809 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3877:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17430 /* 47809 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17431 /* 47812 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17432 /* 47816 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17433 /* 47821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16p),
17434 /* 47824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17435 /* 47826 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17436 /* 47828 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17437 /* 47831 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17438 /* 47837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17439 /* 47843 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17440 /* 47846 */ GIR_RootConstrainSelectedInstOperands,
17441 /* 47847 */ // GIR_Coverage, 4493,
17442 /* 47847 */ GIR_EraseRootFromParent_Done,
17443 /* 47848 */ // Label 1091: @47848
17444 /* 47848 */ GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(47921), // Rule ID 4495 //
17445 /* 47853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17446 /* 47856 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
17447 /* 47861 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17448 /* 47864 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17449 /* 47867 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17450 /* 47870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17451 /* 47874 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17452 /* 47878 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17453 /* 47882 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3873:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17454 /* 47882 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17455 /* 47885 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17456 /* 47889 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17457 /* 47894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16m),
17458 /* 47897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17459 /* 47899 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17460 /* 47901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17461 /* 47904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17462 /* 47910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17463 /* 47916 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17464 /* 47919 */ GIR_RootConstrainSelectedInstOperands,
17465 /* 47920 */ // GIR_Coverage, 4495,
17466 /* 47920 */ GIR_EraseRootFromParent_Done,
17467 /* 47921 */ // Label 1092: @47921
17468 /* 47921 */ GIM_Try, /*On fail goto*//*Label 1093*/ GIMT_Encode4(47994), // Rule ID 4497 //
17469 /* 47926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17470 /* 47929 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
17471 /* 47934 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17472 /* 47937 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17473 /* 47940 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17474 /* 47943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17475 /* 47947 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17476 /* 47951 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17477 /* 47955 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3871:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17478 /* 47955 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17479 /* 47958 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17480 /* 47962 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17481 /* 47967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16a),
17482 /* 47970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17483 /* 47972 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17484 /* 47974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17485 /* 47977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17486 /* 47983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17487 /* 47989 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17488 /* 47992 */ GIR_RootConstrainSelectedInstOperands,
17489 /* 47993 */ // GIR_Coverage, 4497,
17490 /* 47993 */ GIR_EraseRootFromParent_Done,
17491 /* 47994 */ // Label 1093: @47994
17492 /* 47994 */ GIM_Try, /*On fail goto*//*Label 1094*/ GIMT_Encode4(48067), // Rule ID 4499 //
17493 /* 47999 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17494 /* 48002 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
17495 /* 48007 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17496 /* 48010 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17497 /* 48013 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17498 /* 48016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17499 /* 48020 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17500 /* 48024 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17501 /* 48028 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3875:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17502 /* 48028 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17503 /* 48031 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17504 /* 48035 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17505 /* 48040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16n),
17506 /* 48043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17507 /* 48045 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17508 /* 48047 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17509 /* 48050 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17510 /* 48056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17511 /* 48062 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17512 /* 48065 */ GIR_RootConstrainSelectedInstOperands,
17513 /* 48066 */ // GIR_Coverage, 4499,
17514 /* 48066 */ GIR_EraseRootFromParent_Done,
17515 /* 48067 */ // Label 1094: @48067
17516 /* 48067 */ GIM_Try, /*On fail goto*//*Label 1095*/ GIMT_Encode4(48140), // Rule ID 4501 //
17517 /* 48072 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17518 /* 48075 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
17519 /* 48080 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17520 /* 48083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17521 /* 48086 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17522 /* 48089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17523 /* 48093 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17524 /* 48097 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17525 /* 48101 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3877:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17526 /* 48101 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17527 /* 48104 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17528 /* 48108 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17529 /* 48113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16p),
17530 /* 48116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17531 /* 48118 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17532 /* 48120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17533 /* 48123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17534 /* 48129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17535 /* 48135 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17536 /* 48138 */ GIR_RootConstrainSelectedInstOperands,
17537 /* 48139 */ // GIR_Coverage, 4501,
17538 /* 48139 */ GIR_EraseRootFromParent_Done,
17539 /* 48140 */ // Label 1095: @48140
17540 /* 48140 */ GIM_Try, /*On fail goto*//*Label 1096*/ GIMT_Encode4(48213), // Rule ID 4503 //
17541 /* 48145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17542 /* 48148 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
17543 /* 48153 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17544 /* 48156 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17545 /* 48159 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17546 /* 48162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17547 /* 48166 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17548 /* 48170 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17549 /* 48174 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3873:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17550 /* 48174 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17551 /* 48177 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17552 /* 48181 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17553 /* 48186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16m),
17554 /* 48189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17555 /* 48191 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17556 /* 48193 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17557 /* 48196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17558 /* 48202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17559 /* 48208 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17560 /* 48211 */ GIR_RootConstrainSelectedInstOperands,
17561 /* 48212 */ // GIR_Coverage, 4503,
17562 /* 48212 */ GIR_EraseRootFromParent_Done,
17563 /* 48213 */ // Label 1096: @48213
17564 /* 48213 */ GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(48286), // Rule ID 4505 //
17565 /* 48218 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17566 /* 48221 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
17567 /* 48226 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17568 /* 48229 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17569 /* 48232 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17570 /* 48235 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17571 /* 48239 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17572 /* 48243 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17573 /* 48247 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3871:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17574 /* 48247 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17575 /* 48250 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17576 /* 48254 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17577 /* 48259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32a),
17578 /* 48262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17579 /* 48264 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17580 /* 48266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17581 /* 48269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17582 /* 48275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17583 /* 48281 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17584 /* 48284 */ GIR_RootConstrainSelectedInstOperands,
17585 /* 48285 */ // GIR_Coverage, 4505,
17586 /* 48285 */ GIR_EraseRootFromParent_Done,
17587 /* 48286 */ // Label 1097: @48286
17588 /* 48286 */ GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(48359), // Rule ID 4507 //
17589 /* 48291 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17590 /* 48294 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
17591 /* 48299 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17592 /* 48302 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17593 /* 48305 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17594 /* 48308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17595 /* 48312 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17596 /* 48316 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17597 /* 48320 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3875:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17598 /* 48320 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17599 /* 48323 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17600 /* 48327 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17601 /* 48332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32n),
17602 /* 48335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17603 /* 48337 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17604 /* 48339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17605 /* 48342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17606 /* 48348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17607 /* 48354 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17608 /* 48357 */ GIR_RootConstrainSelectedInstOperands,
17609 /* 48358 */ // GIR_Coverage, 4507,
17610 /* 48358 */ GIR_EraseRootFromParent_Done,
17611 /* 48359 */ // Label 1098: @48359
17612 /* 48359 */ GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(48432), // Rule ID 4509 //
17613 /* 48364 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17614 /* 48367 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
17615 /* 48372 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17616 /* 48375 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17617 /* 48378 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17618 /* 48381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17619 /* 48385 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17620 /* 48389 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17621 /* 48393 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3877:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17622 /* 48393 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17623 /* 48396 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17624 /* 48400 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17625 /* 48405 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32p),
17626 /* 48408 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17627 /* 48410 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17628 /* 48412 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17629 /* 48415 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17630 /* 48421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17631 /* 48427 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17632 /* 48430 */ GIR_RootConstrainSelectedInstOperands,
17633 /* 48431 */ // GIR_Coverage, 4509,
17634 /* 48431 */ GIR_EraseRootFromParent_Done,
17635 /* 48432 */ // Label 1099: @48432
17636 /* 48432 */ GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(48505), // Rule ID 4511 //
17637 /* 48437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17638 /* 48440 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
17639 /* 48445 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17640 /* 48448 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17641 /* 48451 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17642 /* 48454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17643 /* 48458 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17644 /* 48462 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17645 /* 48466 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3873:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17646 /* 48466 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17647 /* 48469 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17648 /* 48473 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17649 /* 48478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32m),
17650 /* 48481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17651 /* 48483 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17652 /* 48485 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17653 /* 48488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17654 /* 48494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17655 /* 48500 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17656 /* 48503 */ GIR_RootConstrainSelectedInstOperands,
17657 /* 48504 */ // GIR_Coverage, 4511,
17658 /* 48504 */ GIR_EraseRootFromParent_Done,
17659 /* 48505 */ // Label 1100: @48505
17660 /* 48505 */ GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(48578), // Rule ID 4513 //
17661 /* 48510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17662 /* 48513 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
17663 /* 48518 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17664 /* 48521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17665 /* 48524 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17666 /* 48527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17667 /* 48531 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17668 /* 48535 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17669 /* 48539 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3871:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17670 /* 48539 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17671 /* 48542 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17672 /* 48546 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17673 /* 48551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32a),
17674 /* 48554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17675 /* 48556 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17676 /* 48558 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17677 /* 48561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17678 /* 48567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17679 /* 48573 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17680 /* 48576 */ GIR_RootConstrainSelectedInstOperands,
17681 /* 48577 */ // GIR_Coverage, 4513,
17682 /* 48577 */ GIR_EraseRootFromParent_Done,
17683 /* 48578 */ // Label 1101: @48578
17684 /* 48578 */ GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(48651), // Rule ID 4515 //
17685 /* 48583 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17686 /* 48586 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
17687 /* 48591 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17688 /* 48594 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17689 /* 48597 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17690 /* 48600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17691 /* 48604 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17692 /* 48608 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17693 /* 48612 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3875:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17694 /* 48612 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17695 /* 48615 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17696 /* 48619 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17697 /* 48624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32n),
17698 /* 48627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17699 /* 48629 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17700 /* 48631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17701 /* 48634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17702 /* 48640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17703 /* 48646 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17704 /* 48649 */ GIR_RootConstrainSelectedInstOperands,
17705 /* 48650 */ // GIR_Coverage, 4515,
17706 /* 48650 */ GIR_EraseRootFromParent_Done,
17707 /* 48651 */ // Label 1102: @48651
17708 /* 48651 */ GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(48724), // Rule ID 4517 //
17709 /* 48656 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17710 /* 48659 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
17711 /* 48664 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17712 /* 48667 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17713 /* 48670 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17714 /* 48673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17715 /* 48677 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17716 /* 48681 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17717 /* 48685 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3877:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17718 /* 48685 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17719 /* 48688 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17720 /* 48692 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17721 /* 48697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32p),
17722 /* 48700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17723 /* 48702 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17724 /* 48704 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17725 /* 48707 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17726 /* 48713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17727 /* 48719 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17728 /* 48722 */ GIR_RootConstrainSelectedInstOperands,
17729 /* 48723 */ // GIR_Coverage, 4517,
17730 /* 48723 */ GIR_EraseRootFromParent_Done,
17731 /* 48724 */ // Label 1103: @48724
17732 /* 48724 */ GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(48797), // Rule ID 4519 //
17733 /* 48729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17734 /* 48732 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
17735 /* 48737 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17736 /* 48740 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17737 /* 48743 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17738 /* 48746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17739 /* 48750 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17740 /* 48754 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17741 /* 48758 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3873:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17742 /* 48758 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17743 /* 48761 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17744 /* 48765 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17745 /* 48770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32m),
17746 /* 48773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17747 /* 48775 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17748 /* 48777 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17749 /* 48780 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17750 /* 48786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17751 /* 48792 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17752 /* 48795 */ GIR_RootConstrainSelectedInstOperands,
17753 /* 48796 */ // GIR_Coverage, 4519,
17754 /* 48796 */ GIR_EraseRootFromParent_Done,
17755 /* 48797 */ // Label 1104: @48797
17756 /* 48797 */ GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(48870), // Rule ID 4522 //
17757 /* 48802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17758 /* 48805 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp),
17759 /* 48810 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17760 /* 48813 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17761 /* 48816 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17762 /* 48819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17763 /* 48823 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17764 /* 48827 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17765 /* 48831 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3866:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$src, 0:{ *:[i32] }) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
17766 /* 48831 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17767 /* 48834 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17768 /* 48838 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17769 /* 48843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z),
17770 /* 48846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17771 /* 48848 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17772 /* 48850 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17773 /* 48853 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17774 /* 48859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17775 /* 48865 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17776 /* 48868 */ GIR_RootConstrainSelectedInstOperands,
17777 /* 48869 */ // GIR_Coverage, 4522,
17778 /* 48869 */ GIR_EraseRootFromParent_Done,
17779 /* 48870 */ // Label 1105: @48870
17780 /* 48870 */ GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(48943), // Rule ID 4525 //
17781 /* 48875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17782 /* 48878 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp),
17783 /* 48883 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17784 /* 48886 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17785 /* 48889 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17786 /* 48892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17787 /* 48896 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17788 /* 48900 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
17789 /* 48904 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3866:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$src, 1:{ *:[i32] }) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
17790 /* 48904 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17791 /* 48907 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17792 /* 48911 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17793 /* 48916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z),
17794 /* 48919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17795 /* 48921 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17796 /* 48923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17797 /* 48926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17798 /* 48932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17799 /* 48938 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17800 /* 48941 */ GIR_RootConstrainSelectedInstOperands,
17801 /* 48942 */ // GIR_Coverage, 4525,
17802 /* 48942 */ GIR_EraseRootFromParent_Done,
17803 /* 48943 */ // Label 1106: @48943
17804 /* 48943 */ GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(49016), // Rule ID 4528 //
17805 /* 48948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17806 /* 48951 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp),
17807 /* 48956 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17808 /* 48959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17809 /* 48962 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17810 /* 48965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17811 /* 48969 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17812 /* 48973 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17813 /* 48977 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3866:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$src, 0:{ *:[i32] }) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
17814 /* 48977 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17815 /* 48980 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17816 /* 48984 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17817 /* 48989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z),
17818 /* 48992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17819 /* 48994 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17820 /* 48996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17821 /* 48999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17822 /* 49005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17823 /* 49011 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17824 /* 49014 */ GIR_RootConstrainSelectedInstOperands,
17825 /* 49015 */ // GIR_Coverage, 4528,
17826 /* 49015 */ GIR_EraseRootFromParent_Done,
17827 /* 49016 */ // Label 1107: @49016
17828 /* 49016 */ GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(49089), // Rule ID 4531 //
17829 /* 49021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17830 /* 49024 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp),
17831 /* 49029 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17832 /* 49032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17833 /* 49035 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17834 /* 49038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17835 /* 49042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17836 /* 49046 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
17837 /* 49050 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3866:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$src, 1:{ *:[i32] }) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
17838 /* 49050 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17839 /* 49053 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17840 /* 49057 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17841 /* 49062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z),
17842 /* 49065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17843 /* 49067 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17844 /* 49069 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17845 /* 49072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17846 /* 49078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17847 /* 49084 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17848 /* 49087 */ GIR_RootConstrainSelectedInstOperands,
17849 /* 49088 */ // GIR_Coverage, 4531,
17850 /* 49088 */ GIR_EraseRootFromParent_Done,
17851 /* 49089 */ // Label 1108: @49089
17852 /* 49089 */ GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(49162), // Rule ID 4534 //
17853 /* 49094 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17854 /* 49097 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int),
17855 /* 49102 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17856 /* 49105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17857 /* 49108 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17858 /* 49111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17859 /* 49115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17860 /* 49119 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17861 /* 49123 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3864:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 0:{ *:[i32] }) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
17862 /* 49123 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17863 /* 49126 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17864 /* 49130 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17865 /* 49135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n),
17866 /* 49138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17867 /* 49140 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17868 /* 49142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17869 /* 49145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17870 /* 49151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17871 /* 49157 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17872 /* 49160 */ GIR_RootConstrainSelectedInstOperands,
17873 /* 49161 */ // GIR_Coverage, 4534,
17874 /* 49161 */ GIR_EraseRootFromParent_Done,
17875 /* 49162 */ // Label 1109: @49162
17876 /* 49162 */ GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(49235), // Rule ID 4537 //
17877 /* 49167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17878 /* 49170 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int),
17879 /* 49175 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17880 /* 49178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17881 /* 49181 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17882 /* 49184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17883 /* 49188 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17884 /* 49192 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
17885 /* 49196 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3864:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 1:{ *:[i32] }) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
17886 /* 49196 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17887 /* 49199 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17888 /* 49203 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17889 /* 49208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n),
17890 /* 49211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17891 /* 49213 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17892 /* 49215 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17893 /* 49218 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17894 /* 49224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17895 /* 49230 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17896 /* 49233 */ GIR_RootConstrainSelectedInstOperands,
17897 /* 49234 */ // GIR_Coverage, 4537,
17898 /* 49234 */ GIR_EraseRootFromParent_Done,
17899 /* 49235 */ // Label 1110: @49235
17900 /* 49235 */ GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(49308), // Rule ID 4540 //
17901 /* 49240 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17902 /* 49243 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int),
17903 /* 49248 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17904 /* 49251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17905 /* 49254 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17906 /* 49257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17907 /* 49261 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17908 /* 49265 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17909 /* 49269 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3864:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, 0:{ *:[i32] }) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
17910 /* 49269 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17911 /* 49272 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17912 /* 49276 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17913 /* 49281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n),
17914 /* 49284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17915 /* 49286 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17916 /* 49288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17917 /* 49291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17918 /* 49297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17919 /* 49303 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17920 /* 49306 */ GIR_RootConstrainSelectedInstOperands,
17921 /* 49307 */ // GIR_Coverage, 4540,
17922 /* 49307 */ GIR_EraseRootFromParent_Done,
17923 /* 49308 */ // Label 1111: @49308
17924 /* 49308 */ GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(49381), // Rule ID 4543 //
17925 /* 49313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17926 /* 49316 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int),
17927 /* 49321 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17928 /* 49324 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17929 /* 49327 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17930 /* 49330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17931 /* 49334 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17932 /* 49338 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
17933 /* 49342 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3864:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, 1:{ *:[i32] }) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
17934 /* 49342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17935 /* 49345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17936 /* 49349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17937 /* 49354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n),
17938 /* 49357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17939 /* 49359 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17940 /* 49361 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17941 /* 49364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17942 /* 49370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17943 /* 49376 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17944 /* 49379 */ GIR_RootConstrainSelectedInstOperands,
17945 /* 49380 */ // GIR_Coverage, 4543,
17946 /* 49380 */ GIR_EraseRootFromParent_Done,
17947 /* 49381 */ // Label 1112: @49381
17948 /* 49381 */ GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(49454), // Rule ID 5023 //
17949 /* 49386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17950 /* 49389 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen),
17951 /* 49394 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17952 /* 49397 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17953 /* 49400 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17954 /* 49403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17955 /* 49407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17956 /* 49411 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17957 /* 49415 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3869:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf32f16bh:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm)
17958 /* 49415 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17959 /* 49418 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17960 /* 49422 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17961 /* 49427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16bh),
17962 /* 49430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17963 /* 49432 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
17964 /* 49434 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17965 /* 49437 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17966 /* 49443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17967 /* 49449 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17968 /* 49452 */ GIR_RootConstrainSelectedInstOperands,
17969 /* 49453 */ // GIR_Coverage, 5023,
17970 /* 49453 */ GIR_EraseRootFromParent_Done,
17971 /* 49454 */ // Label 1113: @49454
17972 /* 49454 */ GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(49527), // Rule ID 5029 //
17973 /* 49459 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17974 /* 49462 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen),
17975 /* 49467 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17976 /* 49470 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17977 /* 49473 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17978 /* 49476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17979 /* 49480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17980 /* 49484 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
17981 /* 49488 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3869:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf32f16th:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm)
17982 /* 49488 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17983 /* 49491 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17984 /* 49495 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17985 /* 49500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16th),
17986 /* 49503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17987 /* 49505 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
17988 /* 49507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17989 /* 49510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17990 /* 49516 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17991 /* 49522 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17992 /* 49525 */ GIR_RootConstrainSelectedInstOperands,
17993 /* 49526 */ // GIR_Coverage, 5029,
17994 /* 49526 */ GIR_EraseRootFromParent_Done,
17995 /* 49527 */ // Label 1114: @49527
17996 /* 49527 */ GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(49595), // Rule ID 2067 //
17997 /* 49532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
17998 /* 49535 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
17999 /* 49540 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18000 /* 49543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18001 /* 49546 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18002 /* 49549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18003 /* 49553 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18004 /* 49557 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18005 /* 49561 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18006 /* 49565 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
18007 /* 49569 */ // MIs[1] Operand 1
18008 /* 49569 */ // No operand predicates
18009 /* 49569 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18010 /* 49571 */ // (intrinsic_wo_chain:{ *:[i32] } 4195:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, 0:{ *:[i32] })
18011 /* 49571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT),
18012 /* 49574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18013 /* 49576 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
18014 /* 49579 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
18015 /* 49581 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18016 /* 49584 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18017 /* 49587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18018 /* 49593 */ GIR_RootConstrainSelectedInstOperands,
18019 /* 49594 */ // GIR_Coverage, 2067,
18020 /* 49594 */ GIR_EraseRootFromParent_Done,
18021 /* 49595 */ // Label 1115: @49595
18022 /* 49595 */ GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(49660), // Rule ID 2071 //
18023 /* 49600 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
18024 /* 49603 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16),
18025 /* 49608 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18026 /* 49611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18027 /* 49614 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18028 /* 49617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18029 /* 49621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18030 /* 49625 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18031 /* 49629 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18032 /* 49633 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
18033 /* 49637 */ // MIs[1] Operand 1
18034 /* 49637 */ // No operand predicates
18035 /* 49637 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18036 /* 49639 */ // (intrinsic_wo_chain:{ *:[i32] } 4196:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPRnopc:{ *:[i32] }:$a)
18037 /* 49639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT16),
18038 /* 49642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18039 /* 49644 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
18040 /* 49647 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
18041 /* 49649 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18042 /* 49652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18043 /* 49658 */ GIR_RootConstrainSelectedInstOperands,
18044 /* 49659 */ // GIR_Coverage, 2071,
18045 /* 49659 */ GIR_EraseRootFromParent_Done,
18046 /* 49660 */ // Label 1116: @49660
18047 /* 49660 */ GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(49728), // Rule ID 2335 //
18048 /* 49665 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
18049 /* 49668 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
18050 /* 49673 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18051 /* 49676 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18052 /* 49679 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18053 /* 49682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18054 /* 49686 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
18055 /* 49690 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18056 /* 49694 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18057 /* 49698 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
18058 /* 49702 */ // MIs[1] Operand 1
18059 /* 49702 */ // No operand predicates
18060 /* 49702 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18061 /* 49704 */ // (intrinsic_wo_chain:{ *:[i32] } 4195:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPR:{ *:[i32] }:$a, 0:{ *:[i32] })
18062 /* 49704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT),
18063 /* 49707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18064 /* 49709 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
18065 /* 49712 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
18066 /* 49714 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18067 /* 49717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18068 /* 49720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18069 /* 49726 */ GIR_RootConstrainSelectedInstOperands,
18070 /* 49727 */ // GIR_Coverage, 2335,
18071 /* 49727 */ GIR_EraseRootFromParent_Done,
18072 /* 49728 */ // Label 1117: @49728
18073 /* 49728 */ GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(49793), // Rule ID 2337 //
18074 /* 49733 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
18075 /* 49736 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16),
18076 /* 49741 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18077 /* 49744 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18078 /* 49747 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18079 /* 49750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18080 /* 49754 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
18081 /* 49758 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18082 /* 49762 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18083 /* 49766 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
18084 /* 49770 */ // MIs[1] Operand 1
18085 /* 49770 */ // No operand predicates
18086 /* 49770 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18087 /* 49772 */ // (intrinsic_wo_chain:{ *:[i32] } 4196:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (t2USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPR:{ *:[i32] }:$a)
18088 /* 49772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT16),
18089 /* 49775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18090 /* 49777 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
18091 /* 49780 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
18092 /* 49782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18093 /* 49785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18094 /* 49791 */ GIR_RootConstrainSelectedInstOperands,
18095 /* 49792 */ // GIR_Coverage, 2337,
18096 /* 49792 */ GIR_EraseRootFromParent_Done,
18097 /* 49793 */ // Label 1118: @49793
18098 /* 49793 */ GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(49876), // Rule ID 4311 //
18099 /* 49798 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm),
18100 /* 49803 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
18101 /* 49806 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
18102 /* 49809 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18103 /* 49812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18104 /* 49816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18105 /* 49820 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18106 /* 49824 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18107 /* 49828 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
18108 /* 49832 */ // MIs[1] Operand 1
18109 /* 49832 */ // No operand predicates
18110 /* 49832 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18111 /* 49834 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3933:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) => (MVE_VQSHLU_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
18112 /* 49834 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18113 /* 49837 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18114 /* 49841 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18115 /* 49846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms8),
18116 /* 49849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
18117 /* 49851 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
18118 /* 49853 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
18119 /* 49856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18120 /* 49859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18121 /* 49865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18122 /* 49871 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18123 /* 49874 */ GIR_RootConstrainSelectedInstOperands,
18124 /* 49875 */ // GIR_Coverage, 4311,
18125 /* 49875 */ GIR_EraseRootFromParent_Done,
18126 /* 49876 */ // Label 1119: @49876
18127 /* 49876 */ GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(49959), // Rule ID 4313 //
18128 /* 49881 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm),
18129 /* 49886 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
18130 /* 49889 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18131 /* 49892 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18132 /* 49895 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18133 /* 49899 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18134 /* 49903 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18135 /* 49907 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18136 /* 49911 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
18137 /* 49915 */ // MIs[1] Operand 1
18138 /* 49915 */ // No operand predicates
18139 /* 49915 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18140 /* 49917 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3933:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (MVE_VQSHLU_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
18141 /* 49917 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18142 /* 49920 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18143 /* 49924 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18144 /* 49929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms16),
18145 /* 49932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
18146 /* 49934 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
18147 /* 49936 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
18148 /* 49939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18149 /* 49942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18150 /* 49948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18151 /* 49954 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18152 /* 49957 */ GIR_RootConstrainSelectedInstOperands,
18153 /* 49958 */ // GIR_Coverage, 4313,
18154 /* 49958 */ GIR_EraseRootFromParent_Done,
18155 /* 49959 */ // Label 1120: @49959
18156 /* 49959 */ GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(50042), // Rule ID 4315 //
18157 /* 49964 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm),
18158 /* 49969 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
18159 /* 49972 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
18160 /* 49975 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18161 /* 49978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18162 /* 49982 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18163 /* 49986 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18164 /* 49990 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18165 /* 49994 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
18166 /* 49998 */ // MIs[1] Operand 1
18167 /* 49998 */ // No operand predicates
18168 /* 49998 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18169 /* 50000 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3933:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) => (MVE_VQSHLU_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
18170 /* 50000 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18171 /* 50003 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18172 /* 50007 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18173 /* 50012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms32),
18174 /* 50015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
18175 /* 50017 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
18176 /* 50019 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
18177 /* 50022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18178 /* 50025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18179 /* 50031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18180 /* 50037 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18181 /* 50040 */ GIR_RootConstrainSelectedInstOperands,
18182 /* 50041 */ // GIR_Coverage, 4315,
18183 /* 50041 */ GIR_EraseRootFromParent_Done,
18184 /* 50042 */ // Label 1121: @50042
18185 /* 50042 */ GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(50103), // Rule ID 1814 //
18186 /* 50047 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18187 /* 50050 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
18188 /* 50055 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
18189 /* 50058 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
18190 /* 50061 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18191 /* 50064 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18192 /* 50068 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18193 /* 50072 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18194 /* 50076 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18195 /* 50080 */ // MIs[1] Operand 1
18196 /* 50080 */ // No operand predicates
18197 /* 50080 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18198 /* 50082 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4017:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18199 /* 50082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsd),
18200 /* 50085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18201 /* 50087 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18202 /* 50089 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18203 /* 50092 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18204 /* 50095 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18205 /* 50101 */ GIR_RootConstrainSelectedInstOperands,
18206 /* 50102 */ // GIR_Coverage, 1814,
18207 /* 50102 */ GIR_EraseRootFromParent_Done,
18208 /* 50103 */ // Label 1122: @50103
18209 /* 50103 */ GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(50164), // Rule ID 1815 //
18210 /* 50108 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18211 /* 50111 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
18212 /* 50116 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
18213 /* 50119 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
18214 /* 50122 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18215 /* 50125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18216 /* 50129 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18217 /* 50133 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18218 /* 50137 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18219 /* 50141 */ // MIs[1] Operand 1
18220 /* 50141 */ // No operand predicates
18221 /* 50141 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18222 /* 50143 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4018:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18223 /* 50143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xud),
18224 /* 50146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18225 /* 50148 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18226 /* 50150 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18227 /* 50153 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18228 /* 50156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18229 /* 50162 */ GIR_RootConstrainSelectedInstOperands,
18230 /* 50163 */ // GIR_Coverage, 1815,
18231 /* 50163 */ GIR_EraseRootFromParent_Done,
18232 /* 50164 */ // Label 1123: @50164
18233 /* 50164 */ GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(50225), // Rule ID 1816 //
18234 /* 50169 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18235 /* 50172 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
18236 /* 50177 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
18237 /* 50180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
18238 /* 50183 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18239 /* 50186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18240 /* 50190 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18241 /* 50194 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18242 /* 50198 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18243 /* 50202 */ // MIs[1] Operand 1
18244 /* 50202 */ // No operand predicates
18245 /* 50202 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18246 /* 50204 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4020:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18247 /* 50204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fd),
18248 /* 50207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18249 /* 50209 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18250 /* 50211 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18251 /* 50214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18252 /* 50217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18253 /* 50223 */ GIR_RootConstrainSelectedInstOperands,
18254 /* 50224 */ // GIR_Coverage, 1816,
18255 /* 50224 */ GIR_EraseRootFromParent_Done,
18256 /* 50225 */ // Label 1124: @50225
18257 /* 50225 */ GIM_Try, /*On fail goto*//*Label 1125*/ GIMT_Encode4(50286), // Rule ID 1817 //
18258 /* 50230 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18259 /* 50233 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
18260 /* 50238 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
18261 /* 50241 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
18262 /* 50244 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18263 /* 50247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18264 /* 50251 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18265 /* 50255 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18266 /* 50259 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18267 /* 50263 */ // MIs[1] Operand 1
18268 /* 50263 */ // No operand predicates
18269 /* 50263 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18270 /* 50265 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4021:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18271 /* 50265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fd),
18272 /* 50268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18273 /* 50270 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18274 /* 50272 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18275 /* 50275 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18276 /* 50278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18277 /* 50284 */ GIR_RootConstrainSelectedInstOperands,
18278 /* 50285 */ // GIR_Coverage, 1817,
18279 /* 50285 */ GIR_EraseRootFromParent_Done,
18280 /* 50286 */ // Label 1125: @50286
18281 /* 50286 */ GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(50347), // Rule ID 1818 //
18282 /* 50291 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18283 /* 50294 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
18284 /* 50299 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
18285 /* 50302 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
18286 /* 50305 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18287 /* 50308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18288 /* 50312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18289 /* 50316 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18290 /* 50320 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18291 /* 50324 */ // MIs[1] Operand 1
18292 /* 50324 */ // No operand predicates
18293 /* 50324 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18294 /* 50326 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4017:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18295 /* 50326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsd),
18296 /* 50329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18297 /* 50331 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18298 /* 50333 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18299 /* 50336 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18300 /* 50339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18301 /* 50345 */ GIR_RootConstrainSelectedInstOperands,
18302 /* 50346 */ // GIR_Coverage, 1818,
18303 /* 50346 */ GIR_EraseRootFromParent_Done,
18304 /* 50347 */ // Label 1126: @50347
18305 /* 50347 */ GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(50408), // Rule ID 1819 //
18306 /* 50352 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18307 /* 50355 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
18308 /* 50360 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
18309 /* 50363 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
18310 /* 50366 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18311 /* 50369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18312 /* 50373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18313 /* 50377 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18314 /* 50381 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18315 /* 50385 */ // MIs[1] Operand 1
18316 /* 50385 */ // No operand predicates
18317 /* 50385 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18318 /* 50387 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4018:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18319 /* 50387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xud),
18320 /* 50390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18321 /* 50392 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18322 /* 50394 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18323 /* 50397 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18324 /* 50400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18325 /* 50406 */ GIR_RootConstrainSelectedInstOperands,
18326 /* 50407 */ // GIR_Coverage, 1819,
18327 /* 50407 */ GIR_EraseRootFromParent_Done,
18328 /* 50408 */ // Label 1127: @50408
18329 /* 50408 */ GIM_Try, /*On fail goto*//*Label 1128*/ GIMT_Encode4(50469), // Rule ID 1820 //
18330 /* 50413 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18331 /* 50416 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
18332 /* 50421 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
18333 /* 50424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
18334 /* 50427 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18335 /* 50430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18336 /* 50434 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18337 /* 50438 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18338 /* 50442 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18339 /* 50446 */ // MIs[1] Operand 1
18340 /* 50446 */ // No operand predicates
18341 /* 50446 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18342 /* 50448 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4020:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18343 /* 50448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hd),
18344 /* 50451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18345 /* 50453 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18346 /* 50455 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18347 /* 50458 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18348 /* 50461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18349 /* 50467 */ GIR_RootConstrainSelectedInstOperands,
18350 /* 50468 */ // GIR_Coverage, 1820,
18351 /* 50468 */ GIR_EraseRootFromParent_Done,
18352 /* 50469 */ // Label 1128: @50469
18353 /* 50469 */ GIM_Try, /*On fail goto*//*Label 1129*/ GIMT_Encode4(50530), // Rule ID 1821 //
18354 /* 50474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18355 /* 50477 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
18356 /* 50482 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
18357 /* 50485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
18358 /* 50488 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18359 /* 50491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18360 /* 50495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18361 /* 50499 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18362 /* 50503 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18363 /* 50507 */ // MIs[1] Operand 1
18364 /* 50507 */ // No operand predicates
18365 /* 50507 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18366 /* 50509 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4021:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18367 /* 50509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hd),
18368 /* 50512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18369 /* 50514 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18370 /* 50516 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18371 /* 50519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18372 /* 50522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18373 /* 50528 */ GIR_RootConstrainSelectedInstOperands,
18374 /* 50529 */ // GIR_Coverage, 1821,
18375 /* 50529 */ GIR_EraseRootFromParent_Done,
18376 /* 50530 */ // Label 1129: @50530
18377 /* 50530 */ GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(50591), // Rule ID 1822 //
18378 /* 50535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18379 /* 50538 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
18380 /* 50543 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
18381 /* 50546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
18382 /* 50549 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18383 /* 50552 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18384 /* 50556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18385 /* 50560 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18386 /* 50564 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18387 /* 50568 */ // MIs[1] Operand 1
18388 /* 50568 */ // No operand predicates
18389 /* 50568 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18390 /* 50570 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4017:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18391 /* 50570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsq),
18392 /* 50573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18393 /* 50575 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18394 /* 50577 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18395 /* 50580 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18396 /* 50583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18397 /* 50589 */ GIR_RootConstrainSelectedInstOperands,
18398 /* 50590 */ // GIR_Coverage, 1822,
18399 /* 50590 */ GIR_EraseRootFromParent_Done,
18400 /* 50591 */ // Label 1130: @50591
18401 /* 50591 */ GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(50652), // Rule ID 1823 //
18402 /* 50596 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18403 /* 50599 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
18404 /* 50604 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
18405 /* 50607 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
18406 /* 50610 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18407 /* 50613 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18408 /* 50617 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18409 /* 50621 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18410 /* 50625 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18411 /* 50629 */ // MIs[1] Operand 1
18412 /* 50629 */ // No operand predicates
18413 /* 50629 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18414 /* 50631 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4018:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xuq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18415 /* 50631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xuq),
18416 /* 50634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18417 /* 50636 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18418 /* 50638 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18419 /* 50641 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18420 /* 50644 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18421 /* 50650 */ GIR_RootConstrainSelectedInstOperands,
18422 /* 50651 */ // GIR_Coverage, 1823,
18423 /* 50651 */ GIR_EraseRootFromParent_Done,
18424 /* 50652 */ // Label 1131: @50652
18425 /* 50652 */ GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(50713), // Rule ID 1824 //
18426 /* 50657 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18427 /* 50660 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
18428 /* 50665 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
18429 /* 50668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
18430 /* 50671 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18431 /* 50674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18432 /* 50678 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18433 /* 50682 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18434 /* 50686 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18435 /* 50690 */ // MIs[1] Operand 1
18436 /* 50690 */ // No operand predicates
18437 /* 50690 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18438 /* 50692 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4020:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18439 /* 50692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fq),
18440 /* 50695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18441 /* 50697 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18442 /* 50699 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18443 /* 50702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18444 /* 50705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18445 /* 50711 */ GIR_RootConstrainSelectedInstOperands,
18446 /* 50712 */ // GIR_Coverage, 1824,
18447 /* 50712 */ GIR_EraseRootFromParent_Done,
18448 /* 50713 */ // Label 1132: @50713
18449 /* 50713 */ GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(50774), // Rule ID 1825 //
18450 /* 50718 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18451 /* 50721 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
18452 /* 50726 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
18453 /* 50729 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
18454 /* 50732 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18455 /* 50735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18456 /* 50739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18457 /* 50743 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18458 /* 50747 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18459 /* 50751 */ // MIs[1] Operand 1
18460 /* 50751 */ // No operand predicates
18461 /* 50751 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18462 /* 50753 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4021:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18463 /* 50753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fq),
18464 /* 50756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18465 /* 50758 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18466 /* 50760 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18467 /* 50763 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18468 /* 50766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18469 /* 50772 */ GIR_RootConstrainSelectedInstOperands,
18470 /* 50773 */ // GIR_Coverage, 1825,
18471 /* 50773 */ GIR_EraseRootFromParent_Done,
18472 /* 50774 */ // Label 1133: @50774
18473 /* 50774 */ GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(50835), // Rule ID 1826 //
18474 /* 50779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18475 /* 50782 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
18476 /* 50787 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
18477 /* 50790 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18478 /* 50793 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18479 /* 50796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18480 /* 50800 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18481 /* 50804 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18482 /* 50808 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18483 /* 50812 */ // MIs[1] Operand 1
18484 /* 50812 */ // No operand predicates
18485 /* 50812 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18486 /* 50814 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4017:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18487 /* 50814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsq),
18488 /* 50817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18489 /* 50819 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18490 /* 50821 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18491 /* 50824 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18492 /* 50827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18493 /* 50833 */ GIR_RootConstrainSelectedInstOperands,
18494 /* 50834 */ // GIR_Coverage, 1826,
18495 /* 50834 */ GIR_EraseRootFromParent_Done,
18496 /* 50835 */ // Label 1134: @50835
18497 /* 50835 */ GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(50896), // Rule ID 1827 //
18498 /* 50840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18499 /* 50843 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
18500 /* 50848 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
18501 /* 50851 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18502 /* 50854 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18503 /* 50857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18504 /* 50861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18505 /* 50865 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18506 /* 50869 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18507 /* 50873 */ // MIs[1] Operand 1
18508 /* 50873 */ // No operand predicates
18509 /* 50873 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18510 /* 50875 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4018:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xuq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18511 /* 50875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xuq),
18512 /* 50878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18513 /* 50880 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18514 /* 50882 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18515 /* 50885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18516 /* 50888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18517 /* 50894 */ GIR_RootConstrainSelectedInstOperands,
18518 /* 50895 */ // GIR_Coverage, 1827,
18519 /* 50895 */ GIR_EraseRootFromParent_Done,
18520 /* 50896 */ // Label 1135: @50896
18521 /* 50896 */ GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(50957), // Rule ID 1828 //
18522 /* 50901 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18523 /* 50904 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
18524 /* 50909 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
18525 /* 50912 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18526 /* 50915 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18527 /* 50918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18528 /* 50922 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18529 /* 50926 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18530 /* 50930 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18531 /* 50934 */ // MIs[1] Operand 1
18532 /* 50934 */ // No operand predicates
18533 /* 50934 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18534 /* 50936 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4020:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18535 /* 50936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hq),
18536 /* 50939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18537 /* 50941 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18538 /* 50943 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18539 /* 50946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18540 /* 50949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18541 /* 50955 */ GIR_RootConstrainSelectedInstOperands,
18542 /* 50956 */ // GIR_Coverage, 1828,
18543 /* 50956 */ GIR_EraseRootFromParent_Done,
18544 /* 50957 */ // Label 1136: @50957
18545 /* 50957 */ GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(51018), // Rule ID 1829 //
18546 /* 50962 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18547 /* 50965 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
18548 /* 50970 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
18549 /* 50973 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18550 /* 50976 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18551 /* 50979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18552 /* 50983 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18553 /* 50987 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18554 /* 50991 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18555 /* 50995 */ // MIs[1] Operand 1
18556 /* 50995 */ // No operand predicates
18557 /* 50995 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18558 /* 50997 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4021:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18559 /* 50997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hq),
18560 /* 51000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18561 /* 51002 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18562 /* 51004 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18563 /* 51007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18564 /* 51010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18565 /* 51016 */ GIR_RootConstrainSelectedInstOperands,
18566 /* 51017 */ // GIR_Coverage, 1829,
18567 /* 51017 */ GIR_EraseRootFromParent_Done,
18568 /* 51018 */ // Label 1137: @51018
18569 /* 51018 */ GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(51079), // Rule ID 1911 //
18570 /* 51023 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
18571 /* 51026 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqshl),
18572 /* 51031 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18573 /* 51034 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18574 /* 51037 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18575 /* 51040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18576 /* 51044 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18577 /* 51048 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18578 /* 51052 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18579 /* 51056 */ // MIs[1] Operand 1
18580 /* 51056 */ // No operand predicates
18581 /* 51056 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18582 /* 51058 */ // (intrinsic_wo_chain:{ *:[i32] } 3832:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
18583 /* 51058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQSHL),
18584 /* 51061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
18585 /* 51063 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
18586 /* 51065 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
18587 /* 51068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18588 /* 51071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18589 /* 51077 */ GIR_RootConstrainSelectedInstOperands,
18590 /* 51078 */ // GIR_Coverage, 1911,
18591 /* 51078 */ GIR_EraseRootFromParent_Done,
18592 /* 51079 */ // Label 1138: @51079
18593 /* 51079 */ GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(51140), // Rule ID 1912 //
18594 /* 51084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
18595 /* 51087 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_srshr),
18596 /* 51092 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18597 /* 51095 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18598 /* 51098 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18599 /* 51101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18600 /* 51105 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18601 /* 51109 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18602 /* 51113 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18603 /* 51117 */ // MIs[1] Operand 1
18604 /* 51117 */ // No operand predicates
18605 /* 51117 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18606 /* 51119 */ // (intrinsic_wo_chain:{ *:[i32] } 3834:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
18607 /* 51119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SRSHR),
18608 /* 51122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
18609 /* 51124 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
18610 /* 51126 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
18611 /* 51129 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18612 /* 51132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18613 /* 51138 */ GIR_RootConstrainSelectedInstOperands,
18614 /* 51139 */ // GIR_Coverage, 1912,
18615 /* 51139 */ GIR_EraseRootFromParent_Done,
18616 /* 51140 */ // Label 1139: @51140
18617 /* 51140 */ GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(51201), // Rule ID 1913 //
18618 /* 51145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
18619 /* 51148 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqshl),
18620 /* 51153 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18621 /* 51156 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18622 /* 51159 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18623 /* 51162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18624 /* 51166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18625 /* 51170 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18626 /* 51174 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18627 /* 51178 */ // MIs[1] Operand 1
18628 /* 51178 */ // No operand predicates
18629 /* 51178 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18630 /* 51180 */ // (intrinsic_wo_chain:{ *:[i32] } 3839:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_UQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
18631 /* 51180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQSHL),
18632 /* 51183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
18633 /* 51185 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
18634 /* 51187 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
18635 /* 51190 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18636 /* 51193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18637 /* 51199 */ GIR_RootConstrainSelectedInstOperands,
18638 /* 51200 */ // GIR_Coverage, 1913,
18639 /* 51200 */ GIR_EraseRootFromParent_Done,
18640 /* 51201 */ // Label 1140: @51201
18641 /* 51201 */ GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(51262), // Rule ID 1914 //
18642 /* 51206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
18643 /* 51209 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_urshr),
18644 /* 51214 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18645 /* 51217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18646 /* 51220 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18647 /* 51223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18648 /* 51227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18649 /* 51231 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18650 /* 51235 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18651 /* 51239 */ // MIs[1] Operand 1
18652 /* 51239 */ // No operand predicates
18653 /* 51239 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18654 /* 51241 */ // (intrinsic_wo_chain:{ *:[i32] } 3841:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_URSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
18655 /* 51241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_URSHR),
18656 /* 51244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
18657 /* 51246 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
18658 /* 51248 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
18659 /* 51251 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18660 /* 51254 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18661 /* 51260 */ GIR_RootConstrainSelectedInstOperands,
18662 /* 51261 */ // GIR_Coverage, 1914,
18663 /* 51261 */ GIR_EraseRootFromParent_Done,
18664 /* 51262 */ // Label 1141: @51262
18665 /* 51262 */ GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(51316), // Rule ID 104 //
18666 /* 51267 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18667 /* 51270 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8),
18668 /* 51275 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18669 /* 51278 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18670 /* 51281 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18671 /* 51284 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18672 /* 51288 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18673 /* 51292 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18674 /* 51296 */ // (intrinsic_wo_chain:{ *:[i32] } 4120:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18675 /* 51296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD8),
18676 /* 51299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18677 /* 51301 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18678 /* 51303 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18679 /* 51305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18680 /* 51308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18681 /* 51314 */ GIR_RootConstrainSelectedInstOperands,
18682 /* 51315 */ // GIR_Coverage, 104,
18683 /* 51315 */ GIR_EraseRootFromParent_Done,
18684 /* 51316 */ // Label 1142: @51316
18685 /* 51316 */ GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(51370), // Rule ID 105 //
18686 /* 51321 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18687 /* 51324 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16),
18688 /* 51329 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18689 /* 51332 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18690 /* 51335 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18691 /* 51338 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18692 /* 51342 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18693 /* 51346 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18694 /* 51350 */ // (intrinsic_wo_chain:{ *:[i32] } 4119:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18695 /* 51350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD16),
18696 /* 51353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18697 /* 51355 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18698 /* 51357 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18699 /* 51359 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18700 /* 51362 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18701 /* 51368 */ GIR_RootConstrainSelectedInstOperands,
18702 /* 51369 */ // GIR_Coverage, 105,
18703 /* 51369 */ GIR_EraseRootFromParent_Done,
18704 /* 51370 */ // Label 1143: @51370
18705 /* 51370 */ GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(51424), // Rule ID 106 //
18706 /* 51375 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18707 /* 51378 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16),
18708 /* 51383 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18709 /* 51386 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18710 /* 51389 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18711 /* 51392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18712 /* 51396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18713 /* 51400 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18714 /* 51404 */ // (intrinsic_wo_chain:{ *:[i32] } 4124:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18715 /* 51404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB16),
18716 /* 51407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18717 /* 51409 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18718 /* 51411 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18719 /* 51413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18720 /* 51416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18721 /* 51422 */ GIR_RootConstrainSelectedInstOperands,
18722 /* 51423 */ // GIR_Coverage, 106,
18723 /* 51423 */ GIR_EraseRootFromParent_Done,
18724 /* 51424 */ // Label 1144: @51424
18725 /* 51424 */ GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(51478), // Rule ID 107 //
18726 /* 51429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18727 /* 51432 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8),
18728 /* 51437 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18729 /* 51440 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18730 /* 51443 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18731 /* 51446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18732 /* 51450 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18733 /* 51454 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18734 /* 51458 */ // (intrinsic_wo_chain:{ *:[i32] } 4125:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18735 /* 51458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB8),
18736 /* 51461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18737 /* 51463 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18738 /* 51465 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18739 /* 51467 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18740 /* 51470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18741 /* 51476 */ GIR_RootConstrainSelectedInstOperands,
18742 /* 51477 */ // GIR_Coverage, 107,
18743 /* 51477 */ GIR_EraseRootFromParent_Done,
18744 /* 51478 */ // Label 1145: @51478
18745 /* 51478 */ GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(51532), // Rule ID 110 //
18746 /* 51483 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18747 /* 51486 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
18748 /* 51491 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18749 /* 51494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18750 /* 51497 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18751 /* 51500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18752 /* 51504 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18753 /* 51508 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18754 /* 51512 */ // (intrinsic_wo_chain:{ *:[i32] } 4123:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
18755 /* 51512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB),
18756 /* 51515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18757 /* 51517 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
18758 /* 51519 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
18759 /* 51521 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18760 /* 51524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18761 /* 51530 */ GIR_RootConstrainSelectedInstOperands,
18762 /* 51531 */ // GIR_Coverage, 110,
18763 /* 51531 */ GIR_EraseRootFromParent_Done,
18764 /* 51532 */ // Label 1146: @51532
18765 /* 51532 */ GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(51586), // Rule ID 111 //
18766 /* 51537 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18767 /* 51540 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
18768 /* 51545 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18769 /* 51548 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18770 /* 51551 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18771 /* 51554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18772 /* 51558 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18773 /* 51562 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18774 /* 51566 */ // (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
18775 /* 51566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD),
18776 /* 51569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18777 /* 51571 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
18778 /* 51573 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
18779 /* 51575 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18780 /* 51578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18781 /* 51584 */ GIR_RootConstrainSelectedInstOperands,
18782 /* 51585 */ // GIR_Coverage, 111,
18783 /* 51585 */ GIR_EraseRootFromParent_Done,
18784 /* 51586 */ // Label 1147: @51586
18785 /* 51586 */ GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(51640), // Rule ID 112 //
18786 /* 51591 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18787 /* 51594 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16),
18788 /* 51599 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18789 /* 51602 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18790 /* 51605 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18791 /* 51608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18792 /* 51612 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18793 /* 51616 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18794 /* 51620 */ // (intrinsic_wo_chain:{ *:[i32] } 4187:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18795 /* 51620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD16),
18796 /* 51623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18797 /* 51625 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18798 /* 51627 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18799 /* 51629 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18800 /* 51632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18801 /* 51638 */ GIR_RootConstrainSelectedInstOperands,
18802 /* 51639 */ // GIR_Coverage, 112,
18803 /* 51639 */ GIR_EraseRootFromParent_Done,
18804 /* 51640 */ // Label 1148: @51640
18805 /* 51640 */ GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(51694), // Rule ID 113 //
18806 /* 51645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18807 /* 51648 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8),
18808 /* 51653 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18809 /* 51656 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18810 /* 51659 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18811 /* 51662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18812 /* 51666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18813 /* 51670 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18814 /* 51674 */ // (intrinsic_wo_chain:{ *:[i32] } 4188:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18815 /* 51674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD8),
18816 /* 51677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18817 /* 51679 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18818 /* 51681 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18819 /* 51683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18820 /* 51686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18821 /* 51692 */ GIR_RootConstrainSelectedInstOperands,
18822 /* 51693 */ // GIR_Coverage, 113,
18823 /* 51693 */ GIR_EraseRootFromParent_Done,
18824 /* 51694 */ // Label 1149: @51694
18825 /* 51694 */ GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(51748), // Rule ID 114 //
18826 /* 51699 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18827 /* 51702 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16),
18828 /* 51707 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18829 /* 51710 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18830 /* 51713 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18831 /* 51716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18832 /* 51720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18833 /* 51724 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18834 /* 51728 */ // (intrinsic_wo_chain:{ *:[i32] } 4191:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18835 /* 51728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB16),
18836 /* 51731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18837 /* 51733 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18838 /* 51735 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18839 /* 51737 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18840 /* 51740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18841 /* 51746 */ GIR_RootConstrainSelectedInstOperands,
18842 /* 51747 */ // GIR_Coverage, 114,
18843 /* 51747 */ GIR_EraseRootFromParent_Done,
18844 /* 51748 */ // Label 1150: @51748
18845 /* 51748 */ GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(51802), // Rule ID 115 //
18846 /* 51753 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18847 /* 51756 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8),
18848 /* 51761 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18849 /* 51764 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18850 /* 51767 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18851 /* 51770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18852 /* 51774 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18853 /* 51778 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18854 /* 51782 */ // (intrinsic_wo_chain:{ *:[i32] } 4192:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18855 /* 51782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB8),
18856 /* 51785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18857 /* 51787 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18858 /* 51789 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18859 /* 51791 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18860 /* 51794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18861 /* 51800 */ GIR_RootConstrainSelectedInstOperands,
18862 /* 51801 */ // GIR_Coverage, 115,
18863 /* 51801 */ GIR_EraseRootFromParent_Done,
18864 /* 51802 */ // Label 1151: @51802
18865 /* 51802 */ GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(51856), // Rule ID 116 //
18866 /* 51807 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18867 /* 51810 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx),
18868 /* 51815 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18869 /* 51818 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18870 /* 51821 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18871 /* 51824 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18872 /* 51828 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18873 /* 51832 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18874 /* 51836 */ // (intrinsic_wo_chain:{ *:[i32] } 4121:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18875 /* 51836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QASX),
18876 /* 51839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18877 /* 51841 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18878 /* 51843 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18879 /* 51845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18880 /* 51848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18881 /* 51854 */ GIR_RootConstrainSelectedInstOperands,
18882 /* 51855 */ // GIR_Coverage, 116,
18883 /* 51855 */ GIR_EraseRootFromParent_Done,
18884 /* 51856 */ // Label 1152: @51856
18885 /* 51856 */ GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(51910), // Rule ID 117 //
18886 /* 51861 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18887 /* 51864 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax),
18888 /* 51869 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18889 /* 51872 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18890 /* 51875 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18891 /* 51878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18892 /* 51882 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18893 /* 51886 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18894 /* 51890 */ // (intrinsic_wo_chain:{ *:[i32] } 4122:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18895 /* 51890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSAX),
18896 /* 51893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18897 /* 51895 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18898 /* 51897 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18899 /* 51899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18900 /* 51902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18901 /* 51908 */ GIR_RootConstrainSelectedInstOperands,
18902 /* 51909 */ // GIR_Coverage, 117,
18903 /* 51909 */ GIR_EraseRootFromParent_Done,
18904 /* 51910 */ // Label 1153: @51910
18905 /* 51910 */ GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(51964), // Rule ID 118 //
18906 /* 51915 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18907 /* 51918 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx),
18908 /* 51923 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18909 /* 51926 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18910 /* 51929 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18911 /* 51932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18912 /* 51936 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18913 /* 51940 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18914 /* 51944 */ // (intrinsic_wo_chain:{ *:[i32] } 4189:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18915 /* 51944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQASX),
18916 /* 51947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18917 /* 51949 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18918 /* 51951 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18919 /* 51953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18920 /* 51956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18921 /* 51962 */ GIR_RootConstrainSelectedInstOperands,
18922 /* 51963 */ // GIR_Coverage, 118,
18923 /* 51963 */ GIR_EraseRootFromParent_Done,
18924 /* 51964 */ // Label 1154: @51964
18925 /* 51964 */ GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(52018), // Rule ID 119 //
18926 /* 51969 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18927 /* 51972 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax),
18928 /* 51977 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18929 /* 51980 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18930 /* 51983 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18931 /* 51986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18932 /* 51990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18933 /* 51994 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18934 /* 51998 */ // (intrinsic_wo_chain:{ *:[i32] } 4190:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18935 /* 51998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSAX),
18936 /* 52001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18937 /* 52003 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18938 /* 52005 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18939 /* 52007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18940 /* 52010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18941 /* 52016 */ GIR_RootConstrainSelectedInstOperands,
18942 /* 52017 */ // GIR_Coverage, 119,
18943 /* 52017 */ GIR_EraseRootFromParent_Done,
18944 /* 52018 */ // Label 1155: @52018
18945 /* 52018 */ GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(52072), // Rule ID 132 //
18946 /* 52023 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18947 /* 52026 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx),
18948 /* 52031 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18949 /* 52034 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18950 /* 52037 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18951 /* 52040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18952 /* 52044 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18953 /* 52048 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18954 /* 52052 */ // (intrinsic_wo_chain:{ *:[i32] } 4133:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18955 /* 52052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHASX),
18956 /* 52055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18957 /* 52057 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18958 /* 52059 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18959 /* 52061 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18960 /* 52064 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18961 /* 52070 */ GIR_RootConstrainSelectedInstOperands,
18962 /* 52071 */ // GIR_Coverage, 132,
18963 /* 52071 */ GIR_EraseRootFromParent_Done,
18964 /* 52072 */ // Label 1156: @52072
18965 /* 52072 */ GIM_Try, /*On fail goto*//*Label 1157*/ GIMT_Encode4(52126), // Rule ID 133 //
18966 /* 52077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18967 /* 52080 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16),
18968 /* 52085 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18969 /* 52088 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18970 /* 52091 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18971 /* 52094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18972 /* 52098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18973 /* 52102 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18974 /* 52106 */ // (intrinsic_wo_chain:{ *:[i32] } 4131:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18975 /* 52106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD16),
18976 /* 52109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18977 /* 52111 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18978 /* 52113 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18979 /* 52115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18980 /* 52118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18981 /* 52124 */ GIR_RootConstrainSelectedInstOperands,
18982 /* 52125 */ // GIR_Coverage, 133,
18983 /* 52125 */ GIR_EraseRootFromParent_Done,
18984 /* 52126 */ // Label 1157: @52126
18985 /* 52126 */ GIM_Try, /*On fail goto*//*Label 1158*/ GIMT_Encode4(52180), // Rule ID 134 //
18986 /* 52131 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18987 /* 52134 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8),
18988 /* 52139 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18989 /* 52142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18990 /* 52145 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18991 /* 52148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18992 /* 52152 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18993 /* 52156 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18994 /* 52160 */ // (intrinsic_wo_chain:{ *:[i32] } 4132:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18995 /* 52160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD8),
18996 /* 52163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18997 /* 52165 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18998 /* 52167 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18999 /* 52169 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19000 /* 52172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19001 /* 52178 */ GIR_RootConstrainSelectedInstOperands,
19002 /* 52179 */ // GIR_Coverage, 134,
19003 /* 52179 */ GIR_EraseRootFromParent_Done,
19004 /* 52180 */ // Label 1158: @52180
19005 /* 52180 */ GIM_Try, /*On fail goto*//*Label 1159*/ GIMT_Encode4(52234), // Rule ID 135 //
19006 /* 52185 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19007 /* 52188 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax),
19008 /* 52193 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19009 /* 52196 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19010 /* 52199 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19011 /* 52202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19012 /* 52206 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19013 /* 52210 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19014 /* 52214 */ // (intrinsic_wo_chain:{ *:[i32] } 4134:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19015 /* 52214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSAX),
19016 /* 52217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19017 /* 52219 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19018 /* 52221 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19019 /* 52223 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19020 /* 52226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19021 /* 52232 */ GIR_RootConstrainSelectedInstOperands,
19022 /* 52233 */ // GIR_Coverage, 135,
19023 /* 52233 */ GIR_EraseRootFromParent_Done,
19024 /* 52234 */ // Label 1159: @52234
19025 /* 52234 */ GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(52288), // Rule ID 136 //
19026 /* 52239 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19027 /* 52242 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16),
19028 /* 52247 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19029 /* 52250 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19030 /* 52253 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19031 /* 52256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19032 /* 52260 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19033 /* 52264 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19034 /* 52268 */ // (intrinsic_wo_chain:{ *:[i32] } 4135:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19035 /* 52268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB16),
19036 /* 52271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19037 /* 52273 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19038 /* 52275 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19039 /* 52277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19040 /* 52280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19041 /* 52286 */ GIR_RootConstrainSelectedInstOperands,
19042 /* 52287 */ // GIR_Coverage, 136,
19043 /* 52287 */ GIR_EraseRootFromParent_Done,
19044 /* 52288 */ // Label 1160: @52288
19045 /* 52288 */ GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(52342), // Rule ID 137 //
19046 /* 52293 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19047 /* 52296 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8),
19048 /* 52301 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19049 /* 52304 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19050 /* 52307 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19051 /* 52310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19052 /* 52314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19053 /* 52318 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19054 /* 52322 */ // (intrinsic_wo_chain:{ *:[i32] } 4136:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19055 /* 52322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB8),
19056 /* 52325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19057 /* 52327 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19058 /* 52329 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19059 /* 52331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19060 /* 52334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19061 /* 52340 */ GIR_RootConstrainSelectedInstOperands,
19062 /* 52341 */ // GIR_Coverage, 137,
19063 /* 52341 */ GIR_EraseRootFromParent_Done,
19064 /* 52342 */ // Label 1161: @52342
19065 /* 52342 */ GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(52396), // Rule ID 138 //
19066 /* 52347 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19067 /* 52350 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx),
19068 /* 52355 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19069 /* 52358 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19070 /* 52361 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19071 /* 52364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19072 /* 52368 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19073 /* 52372 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19074 /* 52376 */ // (intrinsic_wo_chain:{ *:[i32] } 4182:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19075 /* 52376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHASX),
19076 /* 52379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19077 /* 52381 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19078 /* 52383 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19079 /* 52385 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19080 /* 52388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19081 /* 52394 */ GIR_RootConstrainSelectedInstOperands,
19082 /* 52395 */ // GIR_Coverage, 138,
19083 /* 52395 */ GIR_EraseRootFromParent_Done,
19084 /* 52396 */ // Label 1162: @52396
19085 /* 52396 */ GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(52450), // Rule ID 139 //
19086 /* 52401 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19087 /* 52404 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16),
19088 /* 52409 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19089 /* 52412 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19090 /* 52415 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19091 /* 52418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19092 /* 52422 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19093 /* 52426 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19094 /* 52430 */ // (intrinsic_wo_chain:{ *:[i32] } 4180:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19095 /* 52430 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD16),
19096 /* 52433 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19097 /* 52435 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19098 /* 52437 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19099 /* 52439 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19100 /* 52442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19101 /* 52448 */ GIR_RootConstrainSelectedInstOperands,
19102 /* 52449 */ // GIR_Coverage, 139,
19103 /* 52449 */ GIR_EraseRootFromParent_Done,
19104 /* 52450 */ // Label 1163: @52450
19105 /* 52450 */ GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(52504), // Rule ID 140 //
19106 /* 52455 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19107 /* 52458 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8),
19108 /* 52463 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19109 /* 52466 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19110 /* 52469 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19111 /* 52472 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19112 /* 52476 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19113 /* 52480 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19114 /* 52484 */ // (intrinsic_wo_chain:{ *:[i32] } 4181:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19115 /* 52484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD8),
19116 /* 52487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19117 /* 52489 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19118 /* 52491 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19119 /* 52493 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19120 /* 52496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19121 /* 52502 */ GIR_RootConstrainSelectedInstOperands,
19122 /* 52503 */ // GIR_Coverage, 140,
19123 /* 52503 */ GIR_EraseRootFromParent_Done,
19124 /* 52504 */ // Label 1164: @52504
19125 /* 52504 */ GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(52558), // Rule ID 141 //
19126 /* 52509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19127 /* 52512 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax),
19128 /* 52517 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19129 /* 52520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19130 /* 52523 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19131 /* 52526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19132 /* 52530 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19133 /* 52534 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19134 /* 52538 */ // (intrinsic_wo_chain:{ *:[i32] } 4183:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19135 /* 52538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSAX),
19136 /* 52541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19137 /* 52543 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19138 /* 52545 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19139 /* 52547 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19140 /* 52550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19141 /* 52556 */ GIR_RootConstrainSelectedInstOperands,
19142 /* 52557 */ // GIR_Coverage, 141,
19143 /* 52557 */ GIR_EraseRootFromParent_Done,
19144 /* 52558 */ // Label 1165: @52558
19145 /* 52558 */ GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(52612), // Rule ID 142 //
19146 /* 52563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19147 /* 52566 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16),
19148 /* 52571 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19149 /* 52574 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19150 /* 52577 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19151 /* 52580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19152 /* 52584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19153 /* 52588 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19154 /* 52592 */ // (intrinsic_wo_chain:{ *:[i32] } 4184:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19155 /* 52592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB16),
19156 /* 52595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19157 /* 52597 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19158 /* 52599 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19159 /* 52601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19160 /* 52604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19161 /* 52610 */ GIR_RootConstrainSelectedInstOperands,
19162 /* 52611 */ // GIR_Coverage, 142,
19163 /* 52611 */ GIR_EraseRootFromParent_Done,
19164 /* 52612 */ // Label 1166: @52612
19165 /* 52612 */ GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(52666), // Rule ID 143 //
19166 /* 52617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19167 /* 52620 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8),
19168 /* 52625 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19169 /* 52628 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19170 /* 52631 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19171 /* 52634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19172 /* 52638 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19173 /* 52642 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19174 /* 52646 */ // (intrinsic_wo_chain:{ *:[i32] } 4185:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19175 /* 52646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB8),
19176 /* 52649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19177 /* 52651 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19178 /* 52653 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19179 /* 52655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19180 /* 52658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19181 /* 52664 */ GIR_RootConstrainSelectedInstOperands,
19182 /* 52665 */ // GIR_Coverage, 143,
19183 /* 52665 */ GIR_EraseRootFromParent_Done,
19184 /* 52666 */ // Label 1167: @52666
19185 /* 52666 */ GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(52720), // Rule ID 144 //
19186 /* 52671 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
19187 /* 52674 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8),
19188 /* 52679 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19189 /* 52682 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19190 /* 52685 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19191 /* 52688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
19192 /* 52692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
19193 /* 52696 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
19194 /* 52700 */ // (intrinsic_wo_chain:{ *:[i32] } 4193:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (USAD8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
19195 /* 52700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAD8),
19196 /* 52703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19197 /* 52705 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19198 /* 52707 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19199 /* 52709 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19200 /* 52712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19201 /* 52718 */ GIR_RootConstrainSelectedInstOperands,
19202 /* 52719 */ // GIR_Coverage, 144,
19203 /* 52719 */ GIR_EraseRootFromParent_Done,
19204 /* 52720 */ // Label 1168: @52720
19205 /* 52720 */ GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(52765), // Rule ID 203 //
19206 /* 52725 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
19207 /* 52728 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b),
19208 /* 52733 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19209 /* 52736 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19210 /* 52739 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19211 /* 52742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19212 /* 52746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19213 /* 52750 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19214 /* 52754 */ // (intrinsic_wo_chain:{ *:[i32] } 3739:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32B:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19215 /* 52754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32B),
19216 /* 52757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19217 /* 52759 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19218 /* 52761 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19219 /* 52763 */ GIR_RootConstrainSelectedInstOperands,
19220 /* 52764 */ // GIR_Coverage, 203,
19221 /* 52764 */ GIR_EraseRootFromParent_Done,
19222 /* 52765 */ // Label 1169: @52765
19223 /* 52765 */ GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(52810), // Rule ID 204 //
19224 /* 52770 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
19225 /* 52773 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb),
19226 /* 52778 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19227 /* 52781 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19228 /* 52784 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19229 /* 52787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19230 /* 52791 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19231 /* 52795 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19232 /* 52799 */ // (intrinsic_wo_chain:{ *:[i32] } 3740:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19233 /* 52799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CB),
19234 /* 52802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19235 /* 52804 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19236 /* 52806 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19237 /* 52808 */ GIR_RootConstrainSelectedInstOperands,
19238 /* 52809 */ // GIR_Coverage, 204,
19239 /* 52809 */ GIR_EraseRootFromParent_Done,
19240 /* 52810 */ // Label 1170: @52810
19241 /* 52810 */ GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(52855), // Rule ID 205 //
19242 /* 52815 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
19243 /* 52818 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h),
19244 /* 52823 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19245 /* 52826 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19246 /* 52829 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19247 /* 52832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19248 /* 52836 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19249 /* 52840 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19250 /* 52844 */ // (intrinsic_wo_chain:{ *:[i32] } 3743:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32H:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19251 /* 52844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32H),
19252 /* 52847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19253 /* 52849 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19254 /* 52851 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19255 /* 52853 */ GIR_RootConstrainSelectedInstOperands,
19256 /* 52854 */ // GIR_Coverage, 205,
19257 /* 52854 */ GIR_EraseRootFromParent_Done,
19258 /* 52855 */ // Label 1171: @52855
19259 /* 52855 */ GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(52900), // Rule ID 206 //
19260 /* 52860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
19261 /* 52863 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch),
19262 /* 52868 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19263 /* 52871 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19264 /* 52874 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19265 /* 52877 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19266 /* 52881 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19267 /* 52885 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19268 /* 52889 */ // (intrinsic_wo_chain:{ *:[i32] } 3741:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CH:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19269 /* 52889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CH),
19270 /* 52892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19271 /* 52894 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19272 /* 52896 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19273 /* 52898 */ GIR_RootConstrainSelectedInstOperands,
19274 /* 52899 */ // GIR_Coverage, 206,
19275 /* 52899 */ GIR_EraseRootFromParent_Done,
19276 /* 52900 */ // Label 1172: @52900
19277 /* 52900 */ GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(52945), // Rule ID 207 //
19278 /* 52905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
19279 /* 52908 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w),
19280 /* 52913 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19281 /* 52916 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19282 /* 52919 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19283 /* 52922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19284 /* 52926 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19285 /* 52930 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19286 /* 52934 */ // (intrinsic_wo_chain:{ *:[i32] } 3744:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32W:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19287 /* 52934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32W),
19288 /* 52937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19289 /* 52939 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19290 /* 52941 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19291 /* 52943 */ GIR_RootConstrainSelectedInstOperands,
19292 /* 52944 */ // GIR_Coverage, 207,
19293 /* 52944 */ GIR_EraseRootFromParent_Done,
19294 /* 52945 */ // Label 1173: @52945
19295 /* 52945 */ GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(52990), // Rule ID 208 //
19296 /* 52950 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
19297 /* 52953 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw),
19298 /* 52958 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19299 /* 52961 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19300 /* 52964 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19301 /* 52967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19302 /* 52971 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19303 /* 52975 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19304 /* 52979 */ // (intrinsic_wo_chain:{ *:[i32] } 3742:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CW:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19305 /* 52979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CW),
19306 /* 52982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19307 /* 52984 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19308 /* 52986 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19309 /* 52988 */ GIR_RootConstrainSelectedInstOperands,
19310 /* 52989 */ // GIR_Coverage, 208,
19311 /* 52989 */ GIR_EraseRootFromParent_Done,
19312 /* 52990 */ // Label 1174: @52990
19313 /* 52990 */ GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(53044), // Rule ID 431 //
19314 /* 52995 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19315 /* 52998 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16),
19316 /* 53003 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19317 /* 53006 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19318 /* 53009 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19319 /* 53012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19320 /* 53016 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19321 /* 53020 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19322 /* 53024 */ // (intrinsic_wo_chain:{ *:[i32] } 4119:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19323 /* 53024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD16),
19324 /* 53027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19325 /* 53029 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19326 /* 53031 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19327 /* 53033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19328 /* 53036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19329 /* 53042 */ GIR_RootConstrainSelectedInstOperands,
19330 /* 53043 */ // GIR_Coverage, 431,
19331 /* 53043 */ GIR_EraseRootFromParent_Done,
19332 /* 53044 */ // Label 1175: @53044
19333 /* 53044 */ GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(53098), // Rule ID 432 //
19334 /* 53049 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19335 /* 53052 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8),
19336 /* 53057 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19337 /* 53060 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19338 /* 53063 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19339 /* 53066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19340 /* 53070 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19341 /* 53074 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19342 /* 53078 */ // (intrinsic_wo_chain:{ *:[i32] } 4120:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19343 /* 53078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD8),
19344 /* 53081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19345 /* 53083 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19346 /* 53085 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19347 /* 53087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19348 /* 53090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19349 /* 53096 */ GIR_RootConstrainSelectedInstOperands,
19350 /* 53097 */ // GIR_Coverage, 432,
19351 /* 53097 */ GIR_EraseRootFromParent_Done,
19352 /* 53098 */ // Label 1176: @53098
19353 /* 53098 */ GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(53152), // Rule ID 433 //
19354 /* 53103 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19355 /* 53106 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx),
19356 /* 53111 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19357 /* 53114 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19358 /* 53117 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19359 /* 53120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19360 /* 53124 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19361 /* 53128 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19362 /* 53132 */ // (intrinsic_wo_chain:{ *:[i32] } 4121:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19363 /* 53132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QASX),
19364 /* 53135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19365 /* 53137 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19366 /* 53139 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19367 /* 53141 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19368 /* 53144 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19369 /* 53150 */ GIR_RootConstrainSelectedInstOperands,
19370 /* 53151 */ // GIR_Coverage, 433,
19371 /* 53151 */ GIR_EraseRootFromParent_Done,
19372 /* 53152 */ // Label 1177: @53152
19373 /* 53152 */ GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(53206), // Rule ID 434 //
19374 /* 53157 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19375 /* 53160 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8),
19376 /* 53165 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19377 /* 53168 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19378 /* 53171 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19379 /* 53174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19380 /* 53178 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19381 /* 53182 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19382 /* 53186 */ // (intrinsic_wo_chain:{ *:[i32] } 4192:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19383 /* 53186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB8),
19384 /* 53189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19385 /* 53191 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19386 /* 53193 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19387 /* 53195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19388 /* 53198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19389 /* 53204 */ GIR_RootConstrainSelectedInstOperands,
19390 /* 53205 */ // GIR_Coverage, 434,
19391 /* 53205 */ GIR_EraseRootFromParent_Done,
19392 /* 53206 */ // Label 1178: @53206
19393 /* 53206 */ GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(53260), // Rule ID 435 //
19394 /* 53211 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19395 /* 53214 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax),
19396 /* 53219 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19397 /* 53222 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19398 /* 53225 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19399 /* 53228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19400 /* 53232 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19401 /* 53236 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19402 /* 53240 */ // (intrinsic_wo_chain:{ *:[i32] } 4122:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19403 /* 53240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSAX),
19404 /* 53243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19405 /* 53245 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19406 /* 53247 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19407 /* 53249 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19408 /* 53252 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19409 /* 53258 */ GIR_RootConstrainSelectedInstOperands,
19410 /* 53259 */ // GIR_Coverage, 435,
19411 /* 53259 */ GIR_EraseRootFromParent_Done,
19412 /* 53260 */ // Label 1179: @53260
19413 /* 53260 */ GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(53314), // Rule ID 436 //
19414 /* 53265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19415 /* 53268 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16),
19416 /* 53273 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19417 /* 53276 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19418 /* 53279 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19419 /* 53282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19420 /* 53286 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19421 /* 53290 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19422 /* 53294 */ // (intrinsic_wo_chain:{ *:[i32] } 4124:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19423 /* 53294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB16),
19424 /* 53297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19425 /* 53299 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19426 /* 53301 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19427 /* 53303 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19428 /* 53306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19429 /* 53312 */ GIR_RootConstrainSelectedInstOperands,
19430 /* 53313 */ // GIR_Coverage, 436,
19431 /* 53313 */ GIR_EraseRootFromParent_Done,
19432 /* 53314 */ // Label 1180: @53314
19433 /* 53314 */ GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(53368), // Rule ID 437 //
19434 /* 53319 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19435 /* 53322 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8),
19436 /* 53327 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19437 /* 53330 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19438 /* 53333 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19439 /* 53336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19440 /* 53340 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19441 /* 53344 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19442 /* 53348 */ // (intrinsic_wo_chain:{ *:[i32] } 4125:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19443 /* 53348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB8),
19444 /* 53351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19445 /* 53353 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19446 /* 53355 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19447 /* 53357 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19448 /* 53360 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19449 /* 53366 */ GIR_RootConstrainSelectedInstOperands,
19450 /* 53367 */ // GIR_Coverage, 437,
19451 /* 53367 */ GIR_EraseRootFromParent_Done,
19452 /* 53368 */ // Label 1181: @53368
19453 /* 53368 */ GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(53422), // Rule ID 438 //
19454 /* 53373 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19455 /* 53376 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16),
19456 /* 53381 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19457 /* 53384 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19458 /* 53387 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19459 /* 53390 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19460 /* 53394 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19461 /* 53398 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19462 /* 53402 */ // (intrinsic_wo_chain:{ *:[i32] } 4187:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19463 /* 53402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD16),
19464 /* 53405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19465 /* 53407 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19466 /* 53409 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19467 /* 53411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19468 /* 53414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19469 /* 53420 */ GIR_RootConstrainSelectedInstOperands,
19470 /* 53421 */ // GIR_Coverage, 438,
19471 /* 53421 */ GIR_EraseRootFromParent_Done,
19472 /* 53422 */ // Label 1182: @53422
19473 /* 53422 */ GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(53476), // Rule ID 439 //
19474 /* 53427 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19475 /* 53430 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8),
19476 /* 53435 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19477 /* 53438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19478 /* 53441 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19479 /* 53444 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19480 /* 53448 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19481 /* 53452 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19482 /* 53456 */ // (intrinsic_wo_chain:{ *:[i32] } 4188:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19483 /* 53456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD8),
19484 /* 53459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19485 /* 53461 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19486 /* 53463 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19487 /* 53465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19488 /* 53468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19489 /* 53474 */ GIR_RootConstrainSelectedInstOperands,
19490 /* 53475 */ // GIR_Coverage, 439,
19491 /* 53475 */ GIR_EraseRootFromParent_Done,
19492 /* 53476 */ // Label 1183: @53476
19493 /* 53476 */ GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(53530), // Rule ID 440 //
19494 /* 53481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19495 /* 53484 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx),
19496 /* 53489 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19497 /* 53492 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19498 /* 53495 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19499 /* 53498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19500 /* 53502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19501 /* 53506 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19502 /* 53510 */ // (intrinsic_wo_chain:{ *:[i32] } 4189:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19503 /* 53510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQASX),
19504 /* 53513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19505 /* 53515 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19506 /* 53517 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19507 /* 53519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19508 /* 53522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19509 /* 53528 */ GIR_RootConstrainSelectedInstOperands,
19510 /* 53529 */ // GIR_Coverage, 440,
19511 /* 53529 */ GIR_EraseRootFromParent_Done,
19512 /* 53530 */ // Label 1184: @53530
19513 /* 53530 */ GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(53584), // Rule ID 441 //
19514 /* 53535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19515 /* 53538 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax),
19516 /* 53543 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19517 /* 53546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19518 /* 53549 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19519 /* 53552 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19520 /* 53556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19521 /* 53560 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19522 /* 53564 */ // (intrinsic_wo_chain:{ *:[i32] } 4190:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19523 /* 53564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSAX),
19524 /* 53567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19525 /* 53569 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19526 /* 53571 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19527 /* 53573 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19528 /* 53576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19529 /* 53582 */ GIR_RootConstrainSelectedInstOperands,
19530 /* 53583 */ // GIR_Coverage, 441,
19531 /* 53583 */ GIR_EraseRootFromParent_Done,
19532 /* 53584 */ // Label 1185: @53584
19533 /* 53584 */ GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(53638), // Rule ID 442 //
19534 /* 53589 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19535 /* 53592 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16),
19536 /* 53597 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19537 /* 53600 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19538 /* 53603 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19539 /* 53606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19540 /* 53610 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19541 /* 53614 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19542 /* 53618 */ // (intrinsic_wo_chain:{ *:[i32] } 4191:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19543 /* 53618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB16),
19544 /* 53621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19545 /* 53623 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19546 /* 53625 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19547 /* 53627 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19548 /* 53630 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19549 /* 53636 */ GIR_RootConstrainSelectedInstOperands,
19550 /* 53637 */ // GIR_Coverage, 442,
19551 /* 53637 */ GIR_EraseRootFromParent_Done,
19552 /* 53638 */ // Label 1186: @53638
19553 /* 53638 */ GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(53692), // Rule ID 455 //
19554 /* 53643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19555 /* 53646 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx),
19556 /* 53651 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19557 /* 53654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19558 /* 53657 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19559 /* 53660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19560 /* 53664 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19561 /* 53668 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19562 /* 53672 */ // (intrinsic_wo_chain:{ *:[i32] } 4133:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19563 /* 53672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHASX),
19564 /* 53675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19565 /* 53677 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19566 /* 53679 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19567 /* 53681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19568 /* 53684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19569 /* 53690 */ GIR_RootConstrainSelectedInstOperands,
19570 /* 53691 */ // GIR_Coverage, 455,
19571 /* 53691 */ GIR_EraseRootFromParent_Done,
19572 /* 53692 */ // Label 1187: @53692
19573 /* 53692 */ GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(53746), // Rule ID 456 //
19574 /* 53697 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19575 /* 53700 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16),
19576 /* 53705 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19577 /* 53708 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19578 /* 53711 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19579 /* 53714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19580 /* 53718 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19581 /* 53722 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19582 /* 53726 */ // (intrinsic_wo_chain:{ *:[i32] } 4131:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19583 /* 53726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD16),
19584 /* 53729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19585 /* 53731 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19586 /* 53733 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19587 /* 53735 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19588 /* 53738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19589 /* 53744 */ GIR_RootConstrainSelectedInstOperands,
19590 /* 53745 */ // GIR_Coverage, 456,
19591 /* 53745 */ GIR_EraseRootFromParent_Done,
19592 /* 53746 */ // Label 1188: @53746
19593 /* 53746 */ GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(53800), // Rule ID 457 //
19594 /* 53751 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19595 /* 53754 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8),
19596 /* 53759 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19597 /* 53762 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19598 /* 53765 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19599 /* 53768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19600 /* 53772 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19601 /* 53776 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19602 /* 53780 */ // (intrinsic_wo_chain:{ *:[i32] } 4132:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19603 /* 53780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD8),
19604 /* 53783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19605 /* 53785 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19606 /* 53787 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19607 /* 53789 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19608 /* 53792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19609 /* 53798 */ GIR_RootConstrainSelectedInstOperands,
19610 /* 53799 */ // GIR_Coverage, 457,
19611 /* 53799 */ GIR_EraseRootFromParent_Done,
19612 /* 53800 */ // Label 1189: @53800
19613 /* 53800 */ GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(53854), // Rule ID 458 //
19614 /* 53805 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19615 /* 53808 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax),
19616 /* 53813 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19617 /* 53816 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19618 /* 53819 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19619 /* 53822 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19620 /* 53826 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19621 /* 53830 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19622 /* 53834 */ // (intrinsic_wo_chain:{ *:[i32] } 4134:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19623 /* 53834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSAX),
19624 /* 53837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19625 /* 53839 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19626 /* 53841 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19627 /* 53843 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19628 /* 53846 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19629 /* 53852 */ GIR_RootConstrainSelectedInstOperands,
19630 /* 53853 */ // GIR_Coverage, 458,
19631 /* 53853 */ GIR_EraseRootFromParent_Done,
19632 /* 53854 */ // Label 1190: @53854
19633 /* 53854 */ GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(53908), // Rule ID 459 //
19634 /* 53859 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19635 /* 53862 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16),
19636 /* 53867 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19637 /* 53870 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19638 /* 53873 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19639 /* 53876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19640 /* 53880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19641 /* 53884 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19642 /* 53888 */ // (intrinsic_wo_chain:{ *:[i32] } 4135:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19643 /* 53888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB16),
19644 /* 53891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19645 /* 53893 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19646 /* 53895 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19647 /* 53897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19648 /* 53900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19649 /* 53906 */ GIR_RootConstrainSelectedInstOperands,
19650 /* 53907 */ // GIR_Coverage, 459,
19651 /* 53907 */ GIR_EraseRootFromParent_Done,
19652 /* 53908 */ // Label 1191: @53908
19653 /* 53908 */ GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(53962), // Rule ID 460 //
19654 /* 53913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19655 /* 53916 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8),
19656 /* 53921 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19657 /* 53924 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19658 /* 53927 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19659 /* 53930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19660 /* 53934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19661 /* 53938 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19662 /* 53942 */ // (intrinsic_wo_chain:{ *:[i32] } 4136:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19663 /* 53942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB8),
19664 /* 53945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19665 /* 53947 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19666 /* 53949 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19667 /* 53951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19668 /* 53954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19669 /* 53960 */ GIR_RootConstrainSelectedInstOperands,
19670 /* 53961 */ // GIR_Coverage, 460,
19671 /* 53961 */ GIR_EraseRootFromParent_Done,
19672 /* 53962 */ // Label 1192: @53962
19673 /* 53962 */ GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(54016), // Rule ID 461 //
19674 /* 53967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19675 /* 53970 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx),
19676 /* 53975 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19677 /* 53978 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19678 /* 53981 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19679 /* 53984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19680 /* 53988 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19681 /* 53992 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19682 /* 53996 */ // (intrinsic_wo_chain:{ *:[i32] } 4182:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19683 /* 53996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHASX),
19684 /* 53999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19685 /* 54001 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19686 /* 54003 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19687 /* 54005 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19688 /* 54008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19689 /* 54014 */ GIR_RootConstrainSelectedInstOperands,
19690 /* 54015 */ // GIR_Coverage, 461,
19691 /* 54015 */ GIR_EraseRootFromParent_Done,
19692 /* 54016 */ // Label 1193: @54016
19693 /* 54016 */ GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(54070), // Rule ID 462 //
19694 /* 54021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19695 /* 54024 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16),
19696 /* 54029 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19697 /* 54032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19698 /* 54035 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19699 /* 54038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19700 /* 54042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19701 /* 54046 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19702 /* 54050 */ // (intrinsic_wo_chain:{ *:[i32] } 4180:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19703 /* 54050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD16),
19704 /* 54053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19705 /* 54055 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19706 /* 54057 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19707 /* 54059 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19708 /* 54062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19709 /* 54068 */ GIR_RootConstrainSelectedInstOperands,
19710 /* 54069 */ // GIR_Coverage, 462,
19711 /* 54069 */ GIR_EraseRootFromParent_Done,
19712 /* 54070 */ // Label 1194: @54070
19713 /* 54070 */ GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(54124), // Rule ID 463 //
19714 /* 54075 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19715 /* 54078 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8),
19716 /* 54083 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19717 /* 54086 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19718 /* 54089 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19719 /* 54092 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19720 /* 54096 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19721 /* 54100 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19722 /* 54104 */ // (intrinsic_wo_chain:{ *:[i32] } 4181:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19723 /* 54104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD8),
19724 /* 54107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19725 /* 54109 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19726 /* 54111 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19727 /* 54113 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19728 /* 54116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19729 /* 54122 */ GIR_RootConstrainSelectedInstOperands,
19730 /* 54123 */ // GIR_Coverage, 463,
19731 /* 54123 */ GIR_EraseRootFromParent_Done,
19732 /* 54124 */ // Label 1195: @54124
19733 /* 54124 */ GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(54178), // Rule ID 464 //
19734 /* 54129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19735 /* 54132 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax),
19736 /* 54137 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19737 /* 54140 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19738 /* 54143 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19739 /* 54146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19740 /* 54150 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19741 /* 54154 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19742 /* 54158 */ // (intrinsic_wo_chain:{ *:[i32] } 4183:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19743 /* 54158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSAX),
19744 /* 54161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19745 /* 54163 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19746 /* 54165 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19747 /* 54167 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19748 /* 54170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19749 /* 54176 */ GIR_RootConstrainSelectedInstOperands,
19750 /* 54177 */ // GIR_Coverage, 464,
19751 /* 54177 */ GIR_EraseRootFromParent_Done,
19752 /* 54178 */ // Label 1196: @54178
19753 /* 54178 */ GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(54232), // Rule ID 465 //
19754 /* 54183 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19755 /* 54186 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16),
19756 /* 54191 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19757 /* 54194 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19758 /* 54197 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19759 /* 54200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19760 /* 54204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19761 /* 54208 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19762 /* 54212 */ // (intrinsic_wo_chain:{ *:[i32] } 4184:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19763 /* 54212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB16),
19764 /* 54215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19765 /* 54217 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19766 /* 54219 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19767 /* 54221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19768 /* 54224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19769 /* 54230 */ GIR_RootConstrainSelectedInstOperands,
19770 /* 54231 */ // GIR_Coverage, 465,
19771 /* 54231 */ GIR_EraseRootFromParent_Done,
19772 /* 54232 */ // Label 1197: @54232
19773 /* 54232 */ GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(54286), // Rule ID 466 //
19774 /* 54237 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19775 /* 54240 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8),
19776 /* 54245 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19777 /* 54248 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19778 /* 54251 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19779 /* 54254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19780 /* 54258 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19781 /* 54262 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19782 /* 54266 */ // (intrinsic_wo_chain:{ *:[i32] } 4185:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19783 /* 54266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB8),
19784 /* 54269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19785 /* 54271 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19786 /* 54273 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19787 /* 54275 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19788 /* 54278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19789 /* 54284 */ GIR_RootConstrainSelectedInstOperands,
19790 /* 54285 */ // GIR_Coverage, 466,
19791 /* 54285 */ GIR_EraseRootFromParent_Done,
19792 /* 54286 */ // Label 1198: @54286
19793 /* 54286 */ GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(54340), // Rule ID 467 //
19794 /* 54291 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19795 /* 54294 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8),
19796 /* 54299 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19797 /* 54302 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19798 /* 54305 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19799 /* 54308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19800 /* 54312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19801 /* 54316 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19802 /* 54320 */ // (intrinsic_wo_chain:{ *:[i32] } 4193:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19803 /* 54320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAD8),
19804 /* 54323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19805 /* 54325 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19806 /* 54327 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19807 /* 54329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19808 /* 54332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19809 /* 54338 */ GIR_RootConstrainSelectedInstOperands,
19810 /* 54339 */ // GIR_Coverage, 467,
19811 /* 54339 */ GIR_EraseRootFromParent_Done,
19812 /* 54340 */ // Label 1199: @54340
19813 /* 54340 */ GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(54394), // Rule ID 523 //
19814 /* 54345 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19815 /* 54348 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad),
19816 /* 54353 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19817 /* 54356 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19818 /* 54359 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19819 /* 54362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19820 /* 54366 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19821 /* 54370 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19822 /* 54374 */ // (intrinsic_wo_chain:{ *:[i32] } 4151:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19823 /* 54374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUAD),
19824 /* 54377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19825 /* 54379 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19826 /* 54381 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19827 /* 54383 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19828 /* 54386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19829 /* 54392 */ GIR_RootConstrainSelectedInstOperands,
19830 /* 54393 */ // GIR_Coverage, 523,
19831 /* 54393 */ GIR_EraseRootFromParent_Done,
19832 /* 54394 */ // Label 1200: @54394
19833 /* 54394 */ GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(54448), // Rule ID 524 //
19834 /* 54399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19835 /* 54402 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx),
19836 /* 54407 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19837 /* 54410 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19838 /* 54413 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19839 /* 54416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19840 /* 54420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19841 /* 54424 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19842 /* 54428 */ // (intrinsic_wo_chain:{ *:[i32] } 4152:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19843 /* 54428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUADX),
19844 /* 54431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19845 /* 54433 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19846 /* 54435 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19847 /* 54437 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19848 /* 54440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19849 /* 54446 */ GIR_RootConstrainSelectedInstOperands,
19850 /* 54447 */ // GIR_Coverage, 524,
19851 /* 54447 */ GIR_EraseRootFromParent_Done,
19852 /* 54448 */ // Label 1201: @54448
19853 /* 54448 */ GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(54502), // Rule ID 525 //
19854 /* 54453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19855 /* 54456 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd),
19856 /* 54461 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19857 /* 54464 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19858 /* 54467 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19859 /* 54470 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19860 /* 54474 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19861 /* 54478 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19862 /* 54482 */ // (intrinsic_wo_chain:{ *:[i32] } 4159:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19863 /* 54482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSD),
19864 /* 54485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19865 /* 54487 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19866 /* 54489 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19867 /* 54491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19868 /* 54494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19869 /* 54500 */ GIR_RootConstrainSelectedInstOperands,
19870 /* 54501 */ // GIR_Coverage, 525,
19871 /* 54501 */ GIR_EraseRootFromParent_Done,
19872 /* 54502 */ // Label 1202: @54502
19873 /* 54502 */ GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(54556), // Rule ID 526 //
19874 /* 54507 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19875 /* 54510 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx),
19876 /* 54515 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19877 /* 54518 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19878 /* 54521 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19879 /* 54524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19880 /* 54528 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19881 /* 54532 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19882 /* 54536 */ // (intrinsic_wo_chain:{ *:[i32] } 4160:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19883 /* 54536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSDX),
19884 /* 54539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19885 /* 54541 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19886 /* 54543 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19887 /* 54545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19888 /* 54548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19889 /* 54554 */ GIR_RootConstrainSelectedInstOperands,
19890 /* 54555 */ // GIR_Coverage, 526,
19891 /* 54555 */ GIR_EraseRootFromParent_Done,
19892 /* 54556 */ // Label 1203: @54556
19893 /* 54556 */ GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(54601), // Rule ID 540 //
19894 /* 54561 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
19895 /* 54564 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b),
19896 /* 54569 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19897 /* 54572 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19898 /* 54575 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19899 /* 54578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19900 /* 54582 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19901 /* 54586 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19902 /* 54590 */ // (intrinsic_wo_chain:{ *:[i32] } 3739:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32B:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19903 /* 54590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32B),
19904 /* 54593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19905 /* 54595 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19906 /* 54597 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19907 /* 54599 */ GIR_RootConstrainSelectedInstOperands,
19908 /* 54600 */ // GIR_Coverage, 540,
19909 /* 54600 */ GIR_EraseRootFromParent_Done,
19910 /* 54601 */ // Label 1204: @54601
19911 /* 54601 */ GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(54646), // Rule ID 541 //
19912 /* 54606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
19913 /* 54609 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb),
19914 /* 54614 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19915 /* 54617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19916 /* 54620 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19917 /* 54623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19918 /* 54627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19919 /* 54631 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19920 /* 54635 */ // (intrinsic_wo_chain:{ *:[i32] } 3740:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19921 /* 54635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CB),
19922 /* 54638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19923 /* 54640 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19924 /* 54642 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19925 /* 54644 */ GIR_RootConstrainSelectedInstOperands,
19926 /* 54645 */ // GIR_Coverage, 541,
19927 /* 54645 */ GIR_EraseRootFromParent_Done,
19928 /* 54646 */ // Label 1205: @54646
19929 /* 54646 */ GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(54691), // Rule ID 542 //
19930 /* 54651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
19931 /* 54654 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h),
19932 /* 54659 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19933 /* 54662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19934 /* 54665 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19935 /* 54668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19936 /* 54672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19937 /* 54676 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19938 /* 54680 */ // (intrinsic_wo_chain:{ *:[i32] } 3743:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32H:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19939 /* 54680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32H),
19940 /* 54683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19941 /* 54685 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19942 /* 54687 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19943 /* 54689 */ GIR_RootConstrainSelectedInstOperands,
19944 /* 54690 */ // GIR_Coverage, 542,
19945 /* 54690 */ GIR_EraseRootFromParent_Done,
19946 /* 54691 */ // Label 1206: @54691
19947 /* 54691 */ GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(54736), // Rule ID 543 //
19948 /* 54696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
19949 /* 54699 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch),
19950 /* 54704 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19951 /* 54707 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19952 /* 54710 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19953 /* 54713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19954 /* 54717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19955 /* 54721 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19956 /* 54725 */ // (intrinsic_wo_chain:{ *:[i32] } 3741:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19957 /* 54725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CH),
19958 /* 54728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19959 /* 54730 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19960 /* 54732 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19961 /* 54734 */ GIR_RootConstrainSelectedInstOperands,
19962 /* 54735 */ // GIR_Coverage, 543,
19963 /* 54735 */ GIR_EraseRootFromParent_Done,
19964 /* 54736 */ // Label 1207: @54736
19965 /* 54736 */ GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(54781), // Rule ID 544 //
19966 /* 54741 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
19967 /* 54744 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w),
19968 /* 54749 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19969 /* 54752 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19970 /* 54755 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19971 /* 54758 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19972 /* 54762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19973 /* 54766 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19974 /* 54770 */ // (intrinsic_wo_chain:{ *:[i32] } 3744:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32W:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19975 /* 54770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32W),
19976 /* 54773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19977 /* 54775 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19978 /* 54777 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19979 /* 54779 */ GIR_RootConstrainSelectedInstOperands,
19980 /* 54780 */ // GIR_Coverage, 544,
19981 /* 54780 */ GIR_EraseRootFromParent_Done,
19982 /* 54781 */ // Label 1208: @54781
19983 /* 54781 */ GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(54826), // Rule ID 545 //
19984 /* 54786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
19985 /* 54789 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw),
19986 /* 54794 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19987 /* 54797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19988 /* 54800 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19989 /* 54803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19990 /* 54807 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19991 /* 54811 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19992 /* 54815 */ // (intrinsic_wo_chain:{ *:[i32] } 3742:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CW:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19993 /* 54815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CW),
19994 /* 54818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19995 /* 54820 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19996 /* 54822 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19997 /* 54824 */ GIR_RootConstrainSelectedInstOperands,
19998 /* 54825 */ // GIR_Coverage, 545,
19999 /* 54825 */ GIR_EraseRootFromParent_Done,
20000 /* 54826 */ // Label 1209: @54826
20001 /* 54826 */ GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(54880), // Rule ID 912 //
20002 /* 54831 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20003 /* 54834 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
20004 /* 54839 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20005 /* 54842 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20006 /* 54845 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20007 /* 54848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20008 /* 54852 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20009 /* 54856 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20010 /* 54860 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4029:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20011 /* 54860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i16),
20012 /* 54863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20013 /* 54865 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20014 /* 54867 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20015 /* 54869 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20016 /* 54872 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20017 /* 54878 */ GIR_RootConstrainSelectedInstOperands,
20018 /* 54879 */ // GIR_Coverage, 912,
20019 /* 54879 */ GIR_EraseRootFromParent_Done,
20020 /* 54880 */ // Label 1210: @54880
20021 /* 54880 */ GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(54934), // Rule ID 913 //
20022 /* 54885 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20023 /* 54888 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
20024 /* 54893 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20025 /* 54896 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20026 /* 54899 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20027 /* 54902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20028 /* 54906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20029 /* 54910 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20030 /* 54914 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4029:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20031 /* 54914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv2i32),
20032 /* 54917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20033 /* 54919 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20034 /* 54921 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20035 /* 54923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20036 /* 54926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20037 /* 54932 */ GIR_RootConstrainSelectedInstOperands,
20038 /* 54933 */ // GIR_Coverage, 913,
20039 /* 54933 */ GIR_EraseRootFromParent_Done,
20040 /* 54934 */ // Label 1211: @54934
20041 /* 54934 */ GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(54988), // Rule ID 914 //
20042 /* 54939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20043 /* 54942 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
20044 /* 54947 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20045 /* 54950 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20046 /* 54953 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20047 /* 54956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20048 /* 54960 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20049 /* 54964 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20050 /* 54968 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4029:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20051 /* 54968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i16),
20052 /* 54971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20053 /* 54973 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20054 /* 54975 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20055 /* 54977 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20056 /* 54980 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20057 /* 54986 */ GIR_RootConstrainSelectedInstOperands,
20058 /* 54987 */ // GIR_Coverage, 914,
20059 /* 54987 */ GIR_EraseRootFromParent_Done,
20060 /* 54988 */ // Label 1212: @54988
20061 /* 54988 */ GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(55042), // Rule ID 915 //
20062 /* 54993 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20063 /* 54996 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
20064 /* 55001 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20065 /* 55004 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20066 /* 55007 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20067 /* 55010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20068 /* 55014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20069 /* 55018 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20070 /* 55022 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4029:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20071 /* 55022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i32),
20072 /* 55025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20073 /* 55027 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20074 /* 55029 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20075 /* 55031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20076 /* 55034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20077 /* 55040 */ GIR_RootConstrainSelectedInstOperands,
20078 /* 55041 */ // GIR_Coverage, 915,
20079 /* 55041 */ GIR_EraseRootFromParent_Done,
20080 /* 55042 */ // Label 1213: @55042
20081 /* 55042 */ GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(55096), // Rule ID 916 //
20082 /* 55047 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20083 /* 55050 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
20084 /* 55055 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
20085 /* 55058 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20086 /* 55061 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20087 /* 55064 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20088 /* 55068 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20089 /* 55072 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20090 /* 55076 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4029:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20091 /* 55076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i8),
20092 /* 55079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20093 /* 55081 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20094 /* 55083 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20095 /* 55085 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20096 /* 55088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20097 /* 55094 */ GIR_RootConstrainSelectedInstOperands,
20098 /* 55095 */ // GIR_Coverage, 916,
20099 /* 55095 */ GIR_EraseRootFromParent_Done,
20100 /* 55096 */ // Label 1214: @55096
20101 /* 55096 */ GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(55150), // Rule ID 917 //
20102 /* 55101 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20103 /* 55104 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
20104 /* 55109 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20105 /* 55112 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20106 /* 55115 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20107 /* 55118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20108 /* 55122 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20109 /* 55126 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20110 /* 55130 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4029:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20111 /* 55130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv16i8),
20112 /* 55133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20113 /* 55135 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20114 /* 55137 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20115 /* 55139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20116 /* 55142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20117 /* 55148 */ GIR_RootConstrainSelectedInstOperands,
20118 /* 55149 */ // GIR_Coverage, 917,
20119 /* 55149 */ GIR_EraseRootFromParent_Done,
20120 /* 55150 */ // Label 1215: @55150
20121 /* 55150 */ GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(55204), // Rule ID 918 //
20122 /* 55155 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20123 /* 55158 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
20124 /* 55163 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20125 /* 55166 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20126 /* 55169 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20127 /* 55172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20128 /* 55176 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20129 /* 55180 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20130 /* 55184 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4030:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20131 /* 55184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i16),
20132 /* 55187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20133 /* 55189 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20134 /* 55191 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20135 /* 55193 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20136 /* 55196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20137 /* 55202 */ GIR_RootConstrainSelectedInstOperands,
20138 /* 55203 */ // GIR_Coverage, 918,
20139 /* 55203 */ GIR_EraseRootFromParent_Done,
20140 /* 55204 */ // Label 1216: @55204
20141 /* 55204 */ GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(55258), // Rule ID 919 //
20142 /* 55209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20143 /* 55212 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
20144 /* 55217 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20145 /* 55220 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20146 /* 55223 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20147 /* 55226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20148 /* 55230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20149 /* 55234 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20150 /* 55238 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4030:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20151 /* 55238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv2i32),
20152 /* 55241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20153 /* 55243 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20154 /* 55245 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20155 /* 55247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20156 /* 55250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20157 /* 55256 */ GIR_RootConstrainSelectedInstOperands,
20158 /* 55257 */ // GIR_Coverage, 919,
20159 /* 55257 */ GIR_EraseRootFromParent_Done,
20160 /* 55258 */ // Label 1217: @55258
20161 /* 55258 */ GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(55312), // Rule ID 920 //
20162 /* 55263 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20163 /* 55266 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
20164 /* 55271 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20165 /* 55274 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20166 /* 55277 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20167 /* 55280 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20168 /* 55284 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20169 /* 55288 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20170 /* 55292 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4030:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20171 /* 55292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i16),
20172 /* 55295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20173 /* 55297 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20174 /* 55299 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20175 /* 55301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20176 /* 55304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20177 /* 55310 */ GIR_RootConstrainSelectedInstOperands,
20178 /* 55311 */ // GIR_Coverage, 920,
20179 /* 55311 */ GIR_EraseRootFromParent_Done,
20180 /* 55312 */ // Label 1218: @55312
20181 /* 55312 */ GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(55366), // Rule ID 921 //
20182 /* 55317 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20183 /* 55320 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
20184 /* 55325 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20185 /* 55328 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20186 /* 55331 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20187 /* 55334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20188 /* 55338 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20189 /* 55342 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20190 /* 55346 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4030:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20191 /* 55346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i32),
20192 /* 55349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20193 /* 55351 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20194 /* 55353 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20195 /* 55355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20196 /* 55358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20197 /* 55364 */ GIR_RootConstrainSelectedInstOperands,
20198 /* 55365 */ // GIR_Coverage, 921,
20199 /* 55365 */ GIR_EraseRootFromParent_Done,
20200 /* 55366 */ // Label 1219: @55366
20201 /* 55366 */ GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(55420), // Rule ID 922 //
20202 /* 55371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20203 /* 55374 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
20204 /* 55379 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
20205 /* 55382 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20206 /* 55385 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20207 /* 55388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20208 /* 55392 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20209 /* 55396 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20210 /* 55400 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4030:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20211 /* 55400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i8),
20212 /* 55403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20213 /* 55405 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20214 /* 55407 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20215 /* 55409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20216 /* 55412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20217 /* 55418 */ GIR_RootConstrainSelectedInstOperands,
20218 /* 55419 */ // GIR_Coverage, 922,
20219 /* 55419 */ GIR_EraseRootFromParent_Done,
20220 /* 55420 */ // Label 1220: @55420
20221 /* 55420 */ GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(55474), // Rule ID 923 //
20222 /* 55425 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20223 /* 55428 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
20224 /* 55433 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20225 /* 55436 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20226 /* 55439 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20227 /* 55442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20228 /* 55446 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20229 /* 55450 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20230 /* 55454 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4030:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20231 /* 55454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv16i8),
20232 /* 55457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20233 /* 55459 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20234 /* 55461 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20235 /* 55463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20236 /* 55466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20237 /* 55472 */ GIR_RootConstrainSelectedInstOperands,
20238 /* 55473 */ // GIR_Coverage, 923,
20239 /* 55473 */ GIR_EraseRootFromParent_Done,
20240 /* 55474 */ // Label 1221: @55474
20241 /* 55474 */ GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(55528), // Rule ID 924 //
20242 /* 55479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20243 /* 55482 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
20244 /* 55487 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20245 /* 55490 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20246 /* 55493 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20247 /* 55496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20248 /* 55500 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20249 /* 55504 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20250 /* 55508 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4089:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20251 /* 55508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i16),
20252 /* 55511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20253 /* 55513 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20254 /* 55515 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20255 /* 55517 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20256 /* 55520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20257 /* 55526 */ GIR_RootConstrainSelectedInstOperands,
20258 /* 55527 */ // GIR_Coverage, 924,
20259 /* 55527 */ GIR_EraseRootFromParent_Done,
20260 /* 55528 */ // Label 1222: @55528
20261 /* 55528 */ GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(55582), // Rule ID 925 //
20262 /* 55533 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20263 /* 55536 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
20264 /* 55541 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20265 /* 55544 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20266 /* 55547 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20267 /* 55550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20268 /* 55554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20269 /* 55558 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20270 /* 55562 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4089:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20271 /* 55562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv2i32),
20272 /* 55565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20273 /* 55567 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20274 /* 55569 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20275 /* 55571 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20276 /* 55574 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20277 /* 55580 */ GIR_RootConstrainSelectedInstOperands,
20278 /* 55581 */ // GIR_Coverage, 925,
20279 /* 55581 */ GIR_EraseRootFromParent_Done,
20280 /* 55582 */ // Label 1223: @55582
20281 /* 55582 */ GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(55636), // Rule ID 926 //
20282 /* 55587 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20283 /* 55590 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
20284 /* 55595 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20285 /* 55598 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20286 /* 55601 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20287 /* 55604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20288 /* 55608 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20289 /* 55612 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20290 /* 55616 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4089:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20291 /* 55616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i16),
20292 /* 55619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20293 /* 55621 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20294 /* 55623 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20295 /* 55625 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20296 /* 55628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20297 /* 55634 */ GIR_RootConstrainSelectedInstOperands,
20298 /* 55635 */ // GIR_Coverage, 926,
20299 /* 55635 */ GIR_EraseRootFromParent_Done,
20300 /* 55636 */ // Label 1224: @55636
20301 /* 55636 */ GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(55690), // Rule ID 927 //
20302 /* 55641 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20303 /* 55644 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
20304 /* 55649 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20305 /* 55652 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20306 /* 55655 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20307 /* 55658 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20308 /* 55662 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20309 /* 55666 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20310 /* 55670 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4089:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20311 /* 55670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i32),
20312 /* 55673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20313 /* 55675 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20314 /* 55677 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20315 /* 55679 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20316 /* 55682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20317 /* 55688 */ GIR_RootConstrainSelectedInstOperands,
20318 /* 55689 */ // GIR_Coverage, 927,
20319 /* 55689 */ GIR_EraseRootFromParent_Done,
20320 /* 55690 */ // Label 1225: @55690
20321 /* 55690 */ GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(55744), // Rule ID 928 //
20322 /* 55695 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20323 /* 55698 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
20324 /* 55703 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
20325 /* 55706 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20326 /* 55709 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20327 /* 55712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20328 /* 55716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20329 /* 55720 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20330 /* 55724 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4089:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20331 /* 55724 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i8),
20332 /* 55727 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20333 /* 55729 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20334 /* 55731 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20335 /* 55733 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20336 /* 55736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20337 /* 55742 */ GIR_RootConstrainSelectedInstOperands,
20338 /* 55743 */ // GIR_Coverage, 928,
20339 /* 55743 */ GIR_EraseRootFromParent_Done,
20340 /* 55744 */ // Label 1226: @55744
20341 /* 55744 */ GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(55798), // Rule ID 929 //
20342 /* 55749 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20343 /* 55752 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
20344 /* 55757 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20345 /* 55760 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20346 /* 55763 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20347 /* 55766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20348 /* 55770 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20349 /* 55774 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20350 /* 55778 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4089:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20351 /* 55778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv16i8),
20352 /* 55781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20353 /* 55783 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20354 /* 55785 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20355 /* 55787 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20356 /* 55790 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20357 /* 55796 */ GIR_RootConstrainSelectedInstOperands,
20358 /* 55797 */ // GIR_Coverage, 929,
20359 /* 55797 */ GIR_EraseRootFromParent_Done,
20360 /* 55798 */ // Label 1227: @55798
20361 /* 55798 */ GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(55852), // Rule ID 930 //
20362 /* 55803 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20363 /* 55806 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
20364 /* 55811 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20365 /* 55814 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20366 /* 55817 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20367 /* 55820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20368 /* 55824 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20369 /* 55828 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20370 /* 55832 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4090:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20371 /* 55832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i16),
20372 /* 55835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20373 /* 55837 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20374 /* 55839 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20375 /* 55841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20376 /* 55844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20377 /* 55850 */ GIR_RootConstrainSelectedInstOperands,
20378 /* 55851 */ // GIR_Coverage, 930,
20379 /* 55851 */ GIR_EraseRootFromParent_Done,
20380 /* 55852 */ // Label 1228: @55852
20381 /* 55852 */ GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(55906), // Rule ID 931 //
20382 /* 55857 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20383 /* 55860 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
20384 /* 55865 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20385 /* 55868 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20386 /* 55871 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20387 /* 55874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20388 /* 55878 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20389 /* 55882 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20390 /* 55886 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4090:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20391 /* 55886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv2i32),
20392 /* 55889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20393 /* 55891 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20394 /* 55893 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20395 /* 55895 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20396 /* 55898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20397 /* 55904 */ GIR_RootConstrainSelectedInstOperands,
20398 /* 55905 */ // GIR_Coverage, 931,
20399 /* 55905 */ GIR_EraseRootFromParent_Done,
20400 /* 55906 */ // Label 1229: @55906
20401 /* 55906 */ GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(55960), // Rule ID 932 //
20402 /* 55911 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20403 /* 55914 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
20404 /* 55919 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20405 /* 55922 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20406 /* 55925 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20407 /* 55928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20408 /* 55932 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20409 /* 55936 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20410 /* 55940 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4090:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20411 /* 55940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i16),
20412 /* 55943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20413 /* 55945 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20414 /* 55947 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20415 /* 55949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20416 /* 55952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20417 /* 55958 */ GIR_RootConstrainSelectedInstOperands,
20418 /* 55959 */ // GIR_Coverage, 932,
20419 /* 55959 */ GIR_EraseRootFromParent_Done,
20420 /* 55960 */ // Label 1230: @55960
20421 /* 55960 */ GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(56014), // Rule ID 933 //
20422 /* 55965 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20423 /* 55968 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
20424 /* 55973 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20425 /* 55976 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20426 /* 55979 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20427 /* 55982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20428 /* 55986 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20429 /* 55990 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20430 /* 55994 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4090:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20431 /* 55994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i32),
20432 /* 55997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20433 /* 55999 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20434 /* 56001 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20435 /* 56003 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20436 /* 56006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20437 /* 56012 */ GIR_RootConstrainSelectedInstOperands,
20438 /* 56013 */ // GIR_Coverage, 933,
20439 /* 56013 */ GIR_EraseRootFromParent_Done,
20440 /* 56014 */ // Label 1231: @56014
20441 /* 56014 */ GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(56068), // Rule ID 934 //
20442 /* 56019 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20443 /* 56022 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
20444 /* 56027 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
20445 /* 56030 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20446 /* 56033 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20447 /* 56036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20448 /* 56040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20449 /* 56044 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20450 /* 56048 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4090:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20451 /* 56048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i8),
20452 /* 56051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20453 /* 56053 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20454 /* 56055 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20455 /* 56057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20456 /* 56060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20457 /* 56066 */ GIR_RootConstrainSelectedInstOperands,
20458 /* 56067 */ // GIR_Coverage, 934,
20459 /* 56067 */ GIR_EraseRootFromParent_Done,
20460 /* 56068 */ // Label 1232: @56068
20461 /* 56068 */ GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(56122), // Rule ID 935 //
20462 /* 56073 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20463 /* 56076 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
20464 /* 56081 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20465 /* 56084 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20466 /* 56087 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20467 /* 56090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20468 /* 56094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20469 /* 56098 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20470 /* 56102 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4090:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20471 /* 56102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv16i8),
20472 /* 56105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20473 /* 56107 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20474 /* 56109 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20475 /* 56111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20476 /* 56114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20477 /* 56120 */ GIR_RootConstrainSelectedInstOperands,
20478 /* 56121 */ // GIR_Coverage, 935,
20479 /* 56121 */ GIR_EraseRootFromParent_Done,
20480 /* 56122 */ // Label 1233: @56122
20481 /* 56122 */ GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(56176), // Rule ID 952 //
20482 /* 56127 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20483 /* 56130 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn),
20484 /* 56135 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
20485 /* 56138 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20486 /* 56141 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20487 /* 56144 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20488 /* 56148 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20489 /* 56152 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20490 /* 56156 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4086:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRADDHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20491 /* 56156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv8i8),
20492 /* 56159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20493 /* 56161 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20494 /* 56163 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20495 /* 56165 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20496 /* 56168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20497 /* 56174 */ GIR_RootConstrainSelectedInstOperands,
20498 /* 56175 */ // GIR_Coverage, 952,
20499 /* 56175 */ GIR_EraseRootFromParent_Done,
20500 /* 56176 */ // Label 1234: @56176
20501 /* 56176 */ GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(56230), // Rule ID 953 //
20502 /* 56181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20503 /* 56184 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn),
20504 /* 56189 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20505 /* 56192 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20506 /* 56195 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20507 /* 56198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20508 /* 56202 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20509 /* 56206 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20510 /* 56210 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4086:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRADDHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20511 /* 56210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv4i16),
20512 /* 56213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20513 /* 56215 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20514 /* 56217 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20515 /* 56219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20516 /* 56222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20517 /* 56228 */ GIR_RootConstrainSelectedInstOperands,
20518 /* 56229 */ // GIR_Coverage, 953,
20519 /* 56229 */ GIR_EraseRootFromParent_Done,
20520 /* 56230 */ // Label 1235: @56230
20521 /* 56230 */ GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(56284), // Rule ID 954 //
20522 /* 56235 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20523 /* 56238 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn),
20524 /* 56243 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20525 /* 56246 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20526 /* 56249 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
20527 /* 56252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20528 /* 56256 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20529 /* 56260 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20530 /* 56264 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4086:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRADDHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
20531 /* 56264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv2i32),
20532 /* 56267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20533 /* 56269 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20534 /* 56271 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20535 /* 56273 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20536 /* 56276 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20537 /* 56282 */ GIR_RootConstrainSelectedInstOperands,
20538 /* 56283 */ // GIR_Coverage, 954,
20539 /* 56283 */ GIR_EraseRootFromParent_Done,
20540 /* 56284 */ // Label 1236: @56284
20541 /* 56284 */ GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(56338), // Rule ID 961 //
20542 /* 56289 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20543 /* 56292 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp),
20544 /* 56297 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
20545 /* 56300 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20546 /* 56303 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20547 /* 56306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20548 /* 56310 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20549 /* 56314 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20550 /* 56318 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4055:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULpd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20551 /* 56318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpd),
20552 /* 56321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20553 /* 56323 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20554 /* 56325 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20555 /* 56327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20556 /* 56330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20557 /* 56336 */ GIR_RootConstrainSelectedInstOperands,
20558 /* 56337 */ // GIR_Coverage, 961,
20559 /* 56337 */ GIR_EraseRootFromParent_Done,
20560 /* 56338 */ // Label 1237: @56338
20561 /* 56338 */ GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(56392), // Rule ID 962 //
20562 /* 56343 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20563 /* 56346 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp),
20564 /* 56351 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20565 /* 56354 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20566 /* 56357 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20567 /* 56360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20568 /* 56364 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20569 /* 56368 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20570 /* 56372 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4055:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULpq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20571 /* 56372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpq),
20572 /* 56375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20573 /* 56377 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20574 /* 56379 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20575 /* 56381 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20576 /* 56384 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20577 /* 56390 */ GIR_RootConstrainSelectedInstOperands,
20578 /* 56391 */ // GIR_Coverage, 962,
20579 /* 56391 */ GIR_EraseRootFromParent_Done,
20580 /* 56392 */ // Label 1238: @56392
20581 /* 56392 */ GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(56446), // Rule ID 975 //
20582 /* 56397 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20583 /* 56400 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh),
20584 /* 56405 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20585 /* 56408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20586 /* 56411 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20587 /* 56414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20588 /* 56418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20589 /* 56422 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20590 /* 56426 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4066:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20591 /* 56426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i16),
20592 /* 56429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20593 /* 56431 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20594 /* 56433 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20595 /* 56435 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20596 /* 56438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20597 /* 56444 */ GIR_RootConstrainSelectedInstOperands,
20598 /* 56445 */ // GIR_Coverage, 975,
20599 /* 56445 */ GIR_EraseRootFromParent_Done,
20600 /* 56446 */ // Label 1239: @56446
20601 /* 56446 */ GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(56500), // Rule ID 976 //
20602 /* 56451 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20603 /* 56454 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh),
20604 /* 56459 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20605 /* 56462 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20606 /* 56465 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20607 /* 56468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20608 /* 56472 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20609 /* 56476 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20610 /* 56480 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4066:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20611 /* 56480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv2i32),
20612 /* 56483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20613 /* 56485 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20614 /* 56487 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20615 /* 56489 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20616 /* 56492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20617 /* 56498 */ GIR_RootConstrainSelectedInstOperands,
20618 /* 56499 */ // GIR_Coverage, 976,
20619 /* 56499 */ GIR_EraseRootFromParent_Done,
20620 /* 56500 */ // Label 1240: @56500
20621 /* 56500 */ GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(56554), // Rule ID 977 //
20622 /* 56505 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20623 /* 56508 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh),
20624 /* 56513 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20625 /* 56516 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20626 /* 56519 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20627 /* 56522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20628 /* 56526 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20629 /* 56530 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20630 /* 56534 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4066:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20631 /* 56534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv8i16),
20632 /* 56537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20633 /* 56539 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20634 /* 56541 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20635 /* 56543 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20636 /* 56546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20637 /* 56552 */ GIR_RootConstrainSelectedInstOperands,
20638 /* 56553 */ // GIR_Coverage, 977,
20639 /* 56553 */ GIR_EraseRootFromParent_Done,
20640 /* 56554 */ // Label 1241: @56554
20641 /* 56554 */ GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(56608), // Rule ID 978 //
20642 /* 56559 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20643 /* 56562 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh),
20644 /* 56567 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20645 /* 56570 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20646 /* 56573 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20647 /* 56576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20648 /* 56580 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20649 /* 56584 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20650 /* 56588 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4066:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20651 /* 56588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i32),
20652 /* 56591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20653 /* 56593 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20654 /* 56595 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20655 /* 56597 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20656 /* 56600 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20657 /* 56606 */ GIR_RootConstrainSelectedInstOperands,
20658 /* 56607 */ // GIR_Coverage, 978,
20659 /* 56607 */ GIR_EraseRootFromParent_Done,
20660 /* 56608 */ // Label 1242: @56608
20661 /* 56608 */ GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(56662), // Rule ID 983 //
20662 /* 56613 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20663 /* 56616 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh),
20664 /* 56621 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20665 /* 56624 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20666 /* 56627 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20667 /* 56630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20668 /* 56634 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20669 /* 56638 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20670 /* 56642 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4074:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20671 /* 56642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i16),
20672 /* 56645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20673 /* 56647 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20674 /* 56649 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20675 /* 56651 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20676 /* 56654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20677 /* 56660 */ GIR_RootConstrainSelectedInstOperands,
20678 /* 56661 */ // GIR_Coverage, 983,
20679 /* 56661 */ GIR_EraseRootFromParent_Done,
20680 /* 56662 */ // Label 1243: @56662
20681 /* 56662 */ GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(56716), // Rule ID 984 //
20682 /* 56667 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20683 /* 56670 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh),
20684 /* 56675 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20685 /* 56678 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20686 /* 56681 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20687 /* 56684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20688 /* 56688 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20689 /* 56692 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20690 /* 56696 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4074:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20691 /* 56696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv2i32),
20692 /* 56699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20693 /* 56701 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20694 /* 56703 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20695 /* 56705 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20696 /* 56708 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20697 /* 56714 */ GIR_RootConstrainSelectedInstOperands,
20698 /* 56715 */ // GIR_Coverage, 984,
20699 /* 56715 */ GIR_EraseRootFromParent_Done,
20700 /* 56716 */ // Label 1244: @56716
20701 /* 56716 */ GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(56770), // Rule ID 985 //
20702 /* 56721 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20703 /* 56724 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh),
20704 /* 56729 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20705 /* 56732 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20706 /* 56735 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20707 /* 56738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20708 /* 56742 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20709 /* 56746 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20710 /* 56750 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4074:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20711 /* 56750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv8i16),
20712 /* 56753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20713 /* 56755 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20714 /* 56757 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20715 /* 56759 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20716 /* 56762 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20717 /* 56768 */ GIR_RootConstrainSelectedInstOperands,
20718 /* 56769 */ // GIR_Coverage, 985,
20719 /* 56769 */ GIR_EraseRootFromParent_Done,
20720 /* 56770 */ // Label 1245: @56770
20721 /* 56770 */ GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(56824), // Rule ID 986 //
20722 /* 56775 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20723 /* 56778 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh),
20724 /* 56783 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20725 /* 56786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20726 /* 56789 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20727 /* 56792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20728 /* 56796 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20729 /* 56800 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20730 /* 56804 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4074:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20731 /* 56804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i32),
20732 /* 56807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20733 /* 56809 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20734 /* 56811 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20735 /* 56813 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20736 /* 56816 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20737 /* 56822 */ GIR_RootConstrainSelectedInstOperands,
20738 /* 56823 */ // GIR_Coverage, 986,
20739 /* 56823 */ GIR_EraseRootFromParent_Done,
20740 /* 56824 */ // Label 1246: @56824
20741 /* 56824 */ GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(56878), // Rule ID 997 //
20742 /* 56829 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20743 /* 56832 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp),
20744 /* 56837 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20745 /* 56840 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20746 /* 56843 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20747 /* 56846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20748 /* 56850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20749 /* 56854 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20750 /* 56858 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4052:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULLp8:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20751 /* 56858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp8),
20752 /* 56861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20753 /* 56863 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20754 /* 56865 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20755 /* 56867 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20756 /* 56870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20757 /* 56876 */ GIR_RootConstrainSelectedInstOperands,
20758 /* 56877 */ // GIR_Coverage, 997,
20759 /* 56877 */ GIR_EraseRootFromParent_Done,
20760 /* 56878 */ // Label 1247: @56878
20761 /* 56878 */ GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(56923), // Rule ID 998 //
20762 /* 56883 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8),
20763 /* 56886 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp),
20764 /* 56891 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20765 /* 56894 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20766 /* 56897 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
20767 /* 56900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20768 /* 56904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20769 /* 56908 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20770 /* 56912 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4052:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VMULLp64:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
20771 /* 56912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp64),
20772 /* 56915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20773 /* 56917 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20774 /* 56919 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20775 /* 56921 */ GIR_RootConstrainSelectedInstOperands,
20776 /* 56922 */ // GIR_Coverage, 998,
20777 /* 56922 */ GIR_EraseRootFromParent_Done,
20778 /* 56923 */ // Label 1248: @56923
20779 /* 56923 */ GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(56977), // Rule ID 1003 //
20780 /* 56928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20781 /* 56931 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
20782 /* 56936 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20783 /* 56939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20784 /* 56942 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20785 /* 56945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20786 /* 56949 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20787 /* 56953 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20788 /* 56957 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4067:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULLv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20789 /* 56957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv4i32),
20790 /* 56960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20791 /* 56962 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20792 /* 56964 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20793 /* 56966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20794 /* 56969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20795 /* 56975 */ GIR_RootConstrainSelectedInstOperands,
20796 /* 56976 */ // GIR_Coverage, 1003,
20797 /* 56976 */ GIR_EraseRootFromParent_Done,
20798 /* 56977 */ // Label 1249: @56977
20799 /* 56977 */ GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(57031), // Rule ID 1004 //
20800 /* 56982 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20801 /* 56985 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
20802 /* 56990 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20803 /* 56993 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20804 /* 56996 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20805 /* 56999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20806 /* 57003 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20807 /* 57007 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20808 /* 57011 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4067:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULLv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20809 /* 57011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv2i64),
20810 /* 57014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20811 /* 57016 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20812 /* 57018 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20813 /* 57020 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20814 /* 57023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20815 /* 57029 */ GIR_RootConstrainSelectedInstOperands,
20816 /* 57030 */ // GIR_Coverage, 1004,
20817 /* 57030 */ GIR_EraseRootFromParent_Done,
20818 /* 57031 */ // Label 1250: @57031
20819 /* 57031 */ GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(57085), // Rule ID 1158 //
20820 /* 57036 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20821 /* 57039 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
20822 /* 57044 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20823 /* 57047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20824 /* 57050 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20825 /* 57053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20826 /* 57057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20827 /* 57061 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20828 /* 57065 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4031:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20829 /* 57065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i16),
20830 /* 57068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20831 /* 57070 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20832 /* 57072 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20833 /* 57074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20834 /* 57077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20835 /* 57083 */ GIR_RootConstrainSelectedInstOperands,
20836 /* 57084 */ // GIR_Coverage, 1158,
20837 /* 57084 */ GIR_EraseRootFromParent_Done,
20838 /* 57085 */ // Label 1251: @57085
20839 /* 57085 */ GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(57139), // Rule ID 1159 //
20840 /* 57090 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20841 /* 57093 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
20842 /* 57098 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20843 /* 57101 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20844 /* 57104 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20845 /* 57107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20846 /* 57111 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20847 /* 57115 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20848 /* 57119 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4031:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20849 /* 57119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv2i32),
20850 /* 57122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20851 /* 57124 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20852 /* 57126 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20853 /* 57128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20854 /* 57131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20855 /* 57137 */ GIR_RootConstrainSelectedInstOperands,
20856 /* 57138 */ // GIR_Coverage, 1159,
20857 /* 57138 */ GIR_EraseRootFromParent_Done,
20858 /* 57139 */ // Label 1252: @57139
20859 /* 57139 */ GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(57193), // Rule ID 1160 //
20860 /* 57144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20861 /* 57147 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
20862 /* 57152 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20863 /* 57155 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20864 /* 57158 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20865 /* 57161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20866 /* 57165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20867 /* 57169 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20868 /* 57173 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4031:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20869 /* 57173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i16),
20870 /* 57176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20871 /* 57178 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20872 /* 57180 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20873 /* 57182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20874 /* 57185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20875 /* 57191 */ GIR_RootConstrainSelectedInstOperands,
20876 /* 57192 */ // GIR_Coverage, 1160,
20877 /* 57192 */ GIR_EraseRootFromParent_Done,
20878 /* 57193 */ // Label 1253: @57193
20879 /* 57193 */ GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(57247), // Rule ID 1161 //
20880 /* 57198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20881 /* 57201 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
20882 /* 57206 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20883 /* 57209 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20884 /* 57212 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20885 /* 57215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20886 /* 57219 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20887 /* 57223 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20888 /* 57227 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4031:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20889 /* 57227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i32),
20890 /* 57230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20891 /* 57232 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20892 /* 57234 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20893 /* 57236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20894 /* 57239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20895 /* 57245 */ GIR_RootConstrainSelectedInstOperands,
20896 /* 57246 */ // GIR_Coverage, 1161,
20897 /* 57246 */ GIR_EraseRootFromParent_Done,
20898 /* 57247 */ // Label 1254: @57247
20899 /* 57247 */ GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(57301), // Rule ID 1162 //
20900 /* 57252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20901 /* 57255 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
20902 /* 57260 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
20903 /* 57263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20904 /* 57266 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20905 /* 57269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20906 /* 57273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20907 /* 57277 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20908 /* 57281 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4031:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20909 /* 57281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i8),
20910 /* 57284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20911 /* 57286 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20912 /* 57288 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20913 /* 57290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20914 /* 57293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20915 /* 57299 */ GIR_RootConstrainSelectedInstOperands,
20916 /* 57300 */ // GIR_Coverage, 1162,
20917 /* 57300 */ GIR_EraseRootFromParent_Done,
20918 /* 57301 */ // Label 1255: @57301
20919 /* 57301 */ GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(57355), // Rule ID 1163 //
20920 /* 57306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20921 /* 57309 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
20922 /* 57314 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20923 /* 57317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20924 /* 57320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20925 /* 57323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20926 /* 57327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20927 /* 57331 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20928 /* 57335 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4031:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20929 /* 57335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv16i8),
20930 /* 57338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20931 /* 57340 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20932 /* 57342 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20933 /* 57344 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20934 /* 57347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20935 /* 57353 */ GIR_RootConstrainSelectedInstOperands,
20936 /* 57354 */ // GIR_Coverage, 1163,
20937 /* 57354 */ GIR_EraseRootFromParent_Done,
20938 /* 57355 */ // Label 1256: @57355
20939 /* 57355 */ GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(57409), // Rule ID 1164 //
20940 /* 57360 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20941 /* 57363 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
20942 /* 57368 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20943 /* 57371 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20944 /* 57374 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20945 /* 57377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20946 /* 57381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20947 /* 57385 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20948 /* 57389 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4032:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20949 /* 57389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i16),
20950 /* 57392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20951 /* 57394 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20952 /* 57396 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20953 /* 57398 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20954 /* 57401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20955 /* 57407 */ GIR_RootConstrainSelectedInstOperands,
20956 /* 57408 */ // GIR_Coverage, 1164,
20957 /* 57408 */ GIR_EraseRootFromParent_Done,
20958 /* 57409 */ // Label 1257: @57409
20959 /* 57409 */ GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(57463), // Rule ID 1165 //
20960 /* 57414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20961 /* 57417 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
20962 /* 57422 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20963 /* 57425 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20964 /* 57428 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20965 /* 57431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20966 /* 57435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20967 /* 57439 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20968 /* 57443 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4032:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20969 /* 57443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv2i32),
20970 /* 57446 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20971 /* 57448 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20972 /* 57450 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20973 /* 57452 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20974 /* 57455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20975 /* 57461 */ GIR_RootConstrainSelectedInstOperands,
20976 /* 57462 */ // GIR_Coverage, 1165,
20977 /* 57462 */ GIR_EraseRootFromParent_Done,
20978 /* 57463 */ // Label 1258: @57463
20979 /* 57463 */ GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(57517), // Rule ID 1166 //
20980 /* 57468 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20981 /* 57471 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
20982 /* 57476 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20983 /* 57479 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20984 /* 57482 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20985 /* 57485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20986 /* 57489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20987 /* 57493 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20988 /* 57497 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4032:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20989 /* 57497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i16),
20990 /* 57500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20991 /* 57502 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20992 /* 57504 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20993 /* 57506 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20994 /* 57509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20995 /* 57515 */ GIR_RootConstrainSelectedInstOperands,
20996 /* 57516 */ // GIR_Coverage, 1166,
20997 /* 57516 */ GIR_EraseRootFromParent_Done,
20998 /* 57517 */ // Label 1259: @57517
20999 /* 57517 */ GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(57571), // Rule ID 1167 //
21000 /* 57522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21001 /* 57525 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
21002 /* 57530 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21003 /* 57533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21004 /* 57536 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21005 /* 57539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21006 /* 57543 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21007 /* 57547 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21008 /* 57551 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4032:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
21009 /* 57551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i32),
21010 /* 57554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21011 /* 57556 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21012 /* 57558 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21013 /* 57560 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21014 /* 57563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21015 /* 57569 */ GIR_RootConstrainSelectedInstOperands,
21016 /* 57570 */ // GIR_Coverage, 1167,
21017 /* 57570 */ GIR_EraseRootFromParent_Done,
21018 /* 57571 */ // Label 1260: @57571
21019 /* 57571 */ GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(57625), // Rule ID 1168 //
21020 /* 57576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21021 /* 57579 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
21022 /* 57584 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
21023 /* 57587 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21024 /* 57590 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21025 /* 57593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21026 /* 57597 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21027 /* 57601 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21028 /* 57605 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4032:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21029 /* 57605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i8),
21030 /* 57608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21031 /* 57610 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21032 /* 57612 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21033 /* 57614 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21034 /* 57617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21035 /* 57623 */ GIR_RootConstrainSelectedInstOperands,
21036 /* 57624 */ // GIR_Coverage, 1168,
21037 /* 57624 */ GIR_EraseRootFromParent_Done,
21038 /* 57625 */ // Label 1261: @57625
21039 /* 57625 */ GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(57679), // Rule ID 1169 //
21040 /* 57630 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21041 /* 57633 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
21042 /* 57638 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
21043 /* 57641 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21044 /* 57644 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
21045 /* 57647 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21046 /* 57651 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21047 /* 57655 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21048 /* 57659 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4032:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
21049 /* 57659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv16i8),
21050 /* 57662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21051 /* 57664 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21052 /* 57666 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21053 /* 57668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21054 /* 57671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21055 /* 57677 */ GIR_RootConstrainSelectedInstOperands,
21056 /* 57678 */ // GIR_Coverage, 1169,
21057 /* 57678 */ GIR_EraseRootFromParent_Done,
21058 /* 57679 */ // Label 1262: @57679
21059 /* 57679 */ GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(57733), // Rule ID 1186 //
21060 /* 57684 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21061 /* 57687 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn),
21062 /* 57692 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
21063 /* 57695 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21064 /* 57698 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21065 /* 57701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21066 /* 57705 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21067 /* 57709 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21068 /* 57713 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4096:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRSUBHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
21069 /* 57713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv8i8),
21070 /* 57716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21071 /* 57718 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21072 /* 57720 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21073 /* 57722 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21074 /* 57725 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21075 /* 57731 */ GIR_RootConstrainSelectedInstOperands,
21076 /* 57732 */ // GIR_Coverage, 1186,
21077 /* 57732 */ GIR_EraseRootFromParent_Done,
21078 /* 57733 */ // Label 1263: @57733
21079 /* 57733 */ GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(57787), // Rule ID 1187 //
21080 /* 57738 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21081 /* 57741 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn),
21082 /* 57746 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21083 /* 57749 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21084 /* 57752 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21085 /* 57755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21086 /* 57759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21087 /* 57763 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21088 /* 57767 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4096:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRSUBHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
21089 /* 57767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv4i16),
21090 /* 57770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21091 /* 57772 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21092 /* 57774 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21093 /* 57776 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21094 /* 57779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21095 /* 57785 */ GIR_RootConstrainSelectedInstOperands,
21096 /* 57786 */ // GIR_Coverage, 1187,
21097 /* 57786 */ GIR_EraseRootFromParent_Done,
21098 /* 57787 */ // Label 1264: @57787
21099 /* 57787 */ GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(57841), // Rule ID 1188 //
21100 /* 57792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21101 /* 57795 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn),
21102 /* 57800 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21103 /* 57803 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21104 /* 57806 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21105 /* 57809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21106 /* 57813 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21107 /* 57817 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21108 /* 57821 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4096:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRSUBHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
21109 /* 57821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv2i32),
21110 /* 57824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21111 /* 57826 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21112 /* 57828 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21113 /* 57830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21114 /* 57833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21115 /* 57839 */ GIR_RootConstrainSelectedInstOperands,
21116 /* 57840 */ // GIR_Coverage, 1188,
21117 /* 57840 */ GIR_EraseRootFromParent_Done,
21118 /* 57841 */ // Label 1265: @57841
21119 /* 57841 */ GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(57895), // Rule ID 1281 //
21120 /* 57846 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21121 /* 57849 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge),
21122 /* 57854 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21123 /* 57857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21124 /* 57860 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21125 /* 57863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21126 /* 57867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21127 /* 57871 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21128 /* 57875 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4007:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGEfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21129 /* 57875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfd),
21130 /* 57878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21131 /* 57880 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21132 /* 57882 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21133 /* 57884 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21134 /* 57887 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21135 /* 57893 */ GIR_RootConstrainSelectedInstOperands,
21136 /* 57894 */ // GIR_Coverage, 1281,
21137 /* 57894 */ GIR_EraseRootFromParent_Done,
21138 /* 57895 */ // Label 1266: @57895
21139 /* 57895 */ GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(57949), // Rule ID 1282 //
21140 /* 57900 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21141 /* 57903 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge),
21142 /* 57908 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21143 /* 57911 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21144 /* 57914 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21145 /* 57917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21146 /* 57921 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21147 /* 57925 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21148 /* 57929 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4007:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGEfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21149 /* 57929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfq),
21150 /* 57932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21151 /* 57934 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21152 /* 57936 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21153 /* 57938 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21154 /* 57941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21155 /* 57947 */ GIR_RootConstrainSelectedInstOperands,
21156 /* 57948 */ // GIR_Coverage, 1282,
21157 /* 57948 */ GIR_EraseRootFromParent_Done,
21158 /* 57949 */ // Label 1267: @57949
21159 /* 57949 */ GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(58003), // Rule ID 1283 //
21160 /* 57954 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21161 /* 57957 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge),
21162 /* 57962 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21163 /* 57965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21164 /* 57968 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21165 /* 57971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21166 /* 57975 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21167 /* 57979 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21168 /* 57983 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4007:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGEhd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21169 /* 57983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhd),
21170 /* 57986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21171 /* 57988 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21172 /* 57990 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21173 /* 57992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21174 /* 57995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21175 /* 58001 */ GIR_RootConstrainSelectedInstOperands,
21176 /* 58002 */ // GIR_Coverage, 1283,
21177 /* 58002 */ GIR_EraseRootFromParent_Done,
21178 /* 58003 */ // Label 1268: @58003
21179 /* 58003 */ GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(58057), // Rule ID 1284 //
21180 /* 58008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21181 /* 58011 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge),
21182 /* 58016 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21183 /* 58019 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21184 /* 58022 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21185 /* 58025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21186 /* 58029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21187 /* 58033 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21188 /* 58037 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4007:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGEhq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21189 /* 58037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhq),
21190 /* 58040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21191 /* 58042 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21192 /* 58044 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21193 /* 58046 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21194 /* 58049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21195 /* 58055 */ GIR_RootConstrainSelectedInstOperands,
21196 /* 58056 */ // GIR_Coverage, 1284,
21197 /* 58056 */ GIR_EraseRootFromParent_Done,
21198 /* 58057 */ // Label 1269: @58057
21199 /* 58057 */ GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(58111), // Rule ID 1285 //
21200 /* 58062 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21201 /* 58065 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt),
21202 /* 58070 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21203 /* 58073 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21204 /* 58076 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21205 /* 58079 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21206 /* 58083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21207 /* 58087 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21208 /* 58091 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4008:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGTfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21209 /* 58091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfd),
21210 /* 58094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21211 /* 58096 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21212 /* 58098 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21213 /* 58100 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21214 /* 58103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21215 /* 58109 */ GIR_RootConstrainSelectedInstOperands,
21216 /* 58110 */ // GIR_Coverage, 1285,
21217 /* 58110 */ GIR_EraseRootFromParent_Done,
21218 /* 58111 */ // Label 1270: @58111
21219 /* 58111 */ GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(58165), // Rule ID 1286 //
21220 /* 58116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21221 /* 58119 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt),
21222 /* 58124 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21223 /* 58127 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21224 /* 58130 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21225 /* 58133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21226 /* 58137 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21227 /* 58141 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21228 /* 58145 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4008:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGTfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21229 /* 58145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfq),
21230 /* 58148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21231 /* 58150 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21232 /* 58152 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21233 /* 58154 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21234 /* 58157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21235 /* 58163 */ GIR_RootConstrainSelectedInstOperands,
21236 /* 58164 */ // GIR_Coverage, 1286,
21237 /* 58164 */ GIR_EraseRootFromParent_Done,
21238 /* 58165 */ // Label 1271: @58165
21239 /* 58165 */ GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(58219), // Rule ID 1287 //
21240 /* 58170 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21241 /* 58173 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt),
21242 /* 58178 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21243 /* 58181 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21244 /* 58184 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21245 /* 58187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21246 /* 58191 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21247 /* 58195 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21248 /* 58199 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4008:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGThd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21249 /* 58199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThd),
21250 /* 58202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21251 /* 58204 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21252 /* 58206 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21253 /* 58208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21254 /* 58211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21255 /* 58217 */ GIR_RootConstrainSelectedInstOperands,
21256 /* 58218 */ // GIR_Coverage, 1287,
21257 /* 58218 */ GIR_EraseRootFromParent_Done,
21258 /* 58219 */ // Label 1272: @58219
21259 /* 58219 */ GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(58273), // Rule ID 1288 //
21260 /* 58224 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21261 /* 58227 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt),
21262 /* 58232 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21263 /* 58235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21264 /* 58238 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21265 /* 58241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21266 /* 58245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21267 /* 58249 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21268 /* 58253 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4008:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGThq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21269 /* 58253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThq),
21270 /* 58256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21271 /* 58258 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21272 /* 58260 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21273 /* 58262 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21274 /* 58265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21275 /* 58271 */ GIR_RootConstrainSelectedInstOperands,
21276 /* 58272 */ // GIR_Coverage, 1288,
21277 /* 58272 */ GIR_EraseRootFromParent_Done,
21278 /* 58273 */ // Label 1273: @58273
21279 /* 58273 */ GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(58327), // Rule ID 1331 //
21280 /* 58278 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21281 /* 58281 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
21282 /* 58286 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21283 /* 58289 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21284 /* 58292 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21285 /* 58295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21286 /* 58299 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21287 /* 58303 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21288 /* 58307 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4004:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VABDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21289 /* 58307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfd),
21290 /* 58310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21291 /* 58312 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21292 /* 58314 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21293 /* 58316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21294 /* 58319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21295 /* 58325 */ GIR_RootConstrainSelectedInstOperands,
21296 /* 58326 */ // GIR_Coverage, 1331,
21297 /* 58326 */ GIR_EraseRootFromParent_Done,
21298 /* 58327 */ // Label 1274: @58327
21299 /* 58327 */ GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(58381), // Rule ID 1332 //
21300 /* 58332 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21301 /* 58335 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
21302 /* 58340 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21303 /* 58343 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21304 /* 58346 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21305 /* 58349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21306 /* 58353 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21307 /* 58357 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21308 /* 58361 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4004:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VABDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21309 /* 58361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfq),
21310 /* 58364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21311 /* 58366 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21312 /* 58368 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21313 /* 58370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21314 /* 58373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21315 /* 58379 */ GIR_RootConstrainSelectedInstOperands,
21316 /* 58380 */ // GIR_Coverage, 1332,
21317 /* 58380 */ GIR_EraseRootFromParent_Done,
21318 /* 58381 */ // Label 1275: @58381
21319 /* 58381 */ GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(58435), // Rule ID 1333 //
21320 /* 58386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21321 /* 58389 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
21322 /* 58394 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21323 /* 58397 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21324 /* 58400 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21325 /* 58403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21326 /* 58407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21327 /* 58411 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21328 /* 58415 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4004:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VABDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21329 /* 58415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhd),
21330 /* 58418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21331 /* 58420 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21332 /* 58422 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21333 /* 58424 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21334 /* 58427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21335 /* 58433 */ GIR_RootConstrainSelectedInstOperands,
21336 /* 58434 */ // GIR_Coverage, 1333,
21337 /* 58434 */ GIR_EraseRootFromParent_Done,
21338 /* 58435 */ // Label 1276: @58435
21339 /* 58435 */ GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(58489), // Rule ID 1334 //
21340 /* 58440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21341 /* 58443 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
21342 /* 58448 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21343 /* 58451 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21344 /* 58454 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21345 /* 58457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21346 /* 58461 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21347 /* 58465 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21348 /* 58469 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4004:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VABDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21349 /* 58469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhq),
21350 /* 58472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21351 /* 58474 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21352 /* 58476 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21353 /* 58478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21354 /* 58481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21355 /* 58487 */ GIR_RootConstrainSelectedInstOperands,
21356 /* 58488 */ // GIR_Coverage, 1334,
21357 /* 58488 */ GIR_EraseRootFromParent_Done,
21358 /* 58489 */ // Label 1277: @58489
21359 /* 58489 */ GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(58543), // Rule ID 1399 //
21360 /* 58494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21361 /* 58497 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
21362 /* 58502 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
21363 /* 58505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21364 /* 58508 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21365 /* 58511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21366 /* 58515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21367 /* 58519 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21368 /* 58523 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4058:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPADDi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21369 /* 58523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi8),
21370 /* 58526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21371 /* 58528 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21372 /* 58530 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21373 /* 58532 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21374 /* 58535 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21375 /* 58541 */ GIR_RootConstrainSelectedInstOperands,
21376 /* 58542 */ // GIR_Coverage, 1399,
21377 /* 58542 */ GIR_EraseRootFromParent_Done,
21378 /* 58543 */ // Label 1278: @58543
21379 /* 58543 */ GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(58597), // Rule ID 1400 //
21380 /* 58548 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21381 /* 58551 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
21382 /* 58556 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21383 /* 58559 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21384 /* 58562 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21385 /* 58565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21386 /* 58569 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21387 /* 58573 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21388 /* 58577 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4058:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPADDi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21389 /* 58577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi16),
21390 /* 58580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21391 /* 58582 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21392 /* 58584 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21393 /* 58586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21394 /* 58589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21395 /* 58595 */ GIR_RootConstrainSelectedInstOperands,
21396 /* 58596 */ // GIR_Coverage, 1400,
21397 /* 58596 */ GIR_EraseRootFromParent_Done,
21398 /* 58597 */ // Label 1279: @58597
21399 /* 58597 */ GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(58651), // Rule ID 1401 //
21400 /* 58602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21401 /* 58605 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
21402 /* 58610 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21403 /* 58613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21404 /* 58616 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21405 /* 58619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21406 /* 58623 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21407 /* 58627 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21408 /* 58631 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4058:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPADDi32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21409 /* 58631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi32),
21410 /* 58634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21411 /* 58636 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21412 /* 58638 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21413 /* 58640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21414 /* 58643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21415 /* 58649 */ GIR_RootConstrainSelectedInstOperands,
21416 /* 58650 */ // GIR_Coverage, 1401,
21417 /* 58650 */ GIR_EraseRootFromParent_Done,
21418 /* 58651 */ // Label 1280: @58651
21419 /* 58651 */ GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(58705), // Rule ID 1402 //
21420 /* 58656 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21421 /* 58659 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
21422 /* 58664 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21423 /* 58667 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21424 /* 58670 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21425 /* 58673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21426 /* 58677 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21427 /* 58681 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21428 /* 58685 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4058:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPADDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21429 /* 58685 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDf),
21430 /* 58688 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21431 /* 58690 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21432 /* 58692 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21433 /* 58694 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21434 /* 58697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21435 /* 58703 */ GIR_RootConstrainSelectedInstOperands,
21436 /* 58704 */ // GIR_Coverage, 1402,
21437 /* 58704 */ GIR_EraseRootFromParent_Done,
21438 /* 58705 */ // Label 1281: @58705
21439 /* 58705 */ GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(58759), // Rule ID 1403 //
21440 /* 58710 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21441 /* 58713 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
21442 /* 58718 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21443 /* 58721 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21444 /* 58724 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21445 /* 58727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21446 /* 58731 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21447 /* 58735 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21448 /* 58739 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4058:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPADDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21449 /* 58739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDh),
21450 /* 58742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21451 /* 58744 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21452 /* 58746 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21453 /* 58748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21454 /* 58751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21455 /* 58757 */ GIR_RootConstrainSelectedInstOperands,
21456 /* 58758 */ // GIR_Coverage, 1403,
21457 /* 58758 */ GIR_EraseRootFromParent_Done,
21458 /* 58759 */ // Label 1282: @58759
21459 /* 58759 */ GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(58813), // Rule ID 1416 //
21460 /* 58764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21461 /* 58767 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21462 /* 58772 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21463 /* 58775 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21464 /* 58778 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21465 /* 58781 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21466 /* 58785 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21467 /* 58789 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21468 /* 58793 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4056:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALsv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
21469 /* 58793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i8),
21470 /* 58796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21471 /* 58798 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21472 /* 58800 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21473 /* 58802 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21474 /* 58805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21475 /* 58811 */ GIR_RootConstrainSelectedInstOperands,
21476 /* 58812 */ // GIR_Coverage, 1416,
21477 /* 58812 */ GIR_EraseRootFromParent_Done,
21478 /* 58813 */ // Label 1283: @58813
21479 /* 58813 */ GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(58867), // Rule ID 1417 //
21480 /* 58818 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21481 /* 58821 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21482 /* 58826 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21483 /* 58829 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21484 /* 58832 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21485 /* 58835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21486 /* 58839 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21487 /* 58843 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21488 /* 58847 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4056:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALsv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
21489 /* 58847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i16),
21490 /* 58850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21491 /* 58852 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21492 /* 58854 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21493 /* 58856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21494 /* 58859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21495 /* 58865 */ GIR_RootConstrainSelectedInstOperands,
21496 /* 58866 */ // GIR_Coverage, 1417,
21497 /* 58866 */ GIR_EraseRootFromParent_Done,
21498 /* 58867 */ // Label 1284: @58867
21499 /* 58867 */ GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(58921), // Rule ID 1418 //
21500 /* 58872 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21501 /* 58875 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21502 /* 58880 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21503 /* 58883 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21504 /* 58886 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21505 /* 58889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21506 /* 58893 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21507 /* 58897 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21508 /* 58901 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4056:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALsv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
21509 /* 58901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv2i32),
21510 /* 58904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21511 /* 58906 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21512 /* 58908 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21513 /* 58910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21514 /* 58913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21515 /* 58919 */ GIR_RootConstrainSelectedInstOperands,
21516 /* 58920 */ // GIR_Coverage, 1418,
21517 /* 58920 */ GIR_EraseRootFromParent_Done,
21518 /* 58921 */ // Label 1285: @58921
21519 /* 58921 */ GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(58975), // Rule ID 1419 //
21520 /* 58926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21521 /* 58929 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21522 /* 58934 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21523 /* 58937 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21524 /* 58940 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
21525 /* 58943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21526 /* 58947 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21527 /* 58951 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21528 /* 58955 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4056:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALsv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
21529 /* 58955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv16i8),
21530 /* 58958 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21531 /* 58960 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21532 /* 58962 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21533 /* 58964 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21534 /* 58967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21535 /* 58973 */ GIR_RootConstrainSelectedInstOperands,
21536 /* 58974 */ // GIR_Coverage, 1419,
21537 /* 58974 */ GIR_EraseRootFromParent_Done,
21538 /* 58975 */ // Label 1286: @58975
21539 /* 58975 */ GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(59029), // Rule ID 1420 //
21540 /* 58980 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21541 /* 58983 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21542 /* 58988 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21543 /* 58991 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21544 /* 58994 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21545 /* 58997 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21546 /* 59001 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21547 /* 59005 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21548 /* 59009 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4056:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALsv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
21549 /* 59009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i16),
21550 /* 59012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21551 /* 59014 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21552 /* 59016 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21553 /* 59018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21554 /* 59021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21555 /* 59027 */ GIR_RootConstrainSelectedInstOperands,
21556 /* 59028 */ // GIR_Coverage, 1420,
21557 /* 59028 */ GIR_EraseRootFromParent_Done,
21558 /* 59029 */ // Label 1287: @59029
21559 /* 59029 */ GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(59083), // Rule ID 1421 //
21560 /* 59034 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21561 /* 59037 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21562 /* 59042 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
21563 /* 59045 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21564 /* 59048 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21565 /* 59051 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21566 /* 59055 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21567 /* 59059 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21568 /* 59063 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4056:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALsv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
21569 /* 59063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i32),
21570 /* 59066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21571 /* 59068 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21572 /* 59070 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21573 /* 59072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21574 /* 59075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21575 /* 59081 */ GIR_RootConstrainSelectedInstOperands,
21576 /* 59082 */ // GIR_Coverage, 1421,
21577 /* 59082 */ GIR_EraseRootFromParent_Done,
21578 /* 59083 */ // Label 1288: @59083
21579 /* 59083 */ GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(59137), // Rule ID 1422 //
21580 /* 59088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21581 /* 59091 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21582 /* 59096 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21583 /* 59099 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21584 /* 59102 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21585 /* 59105 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21586 /* 59109 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21587 /* 59113 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21588 /* 59117 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4057:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALuv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
21589 /* 59117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i8),
21590 /* 59120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21591 /* 59122 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21592 /* 59124 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21593 /* 59126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21594 /* 59129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21595 /* 59135 */ GIR_RootConstrainSelectedInstOperands,
21596 /* 59136 */ // GIR_Coverage, 1422,
21597 /* 59136 */ GIR_EraseRootFromParent_Done,
21598 /* 59137 */ // Label 1289: @59137
21599 /* 59137 */ GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(59191), // Rule ID 1423 //
21600 /* 59142 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21601 /* 59145 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21602 /* 59150 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21603 /* 59153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21604 /* 59156 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21605 /* 59159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21606 /* 59163 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21607 /* 59167 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21608 /* 59171 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4057:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALuv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
21609 /* 59171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i16),
21610 /* 59174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21611 /* 59176 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21612 /* 59178 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21613 /* 59180 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21614 /* 59183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21615 /* 59189 */ GIR_RootConstrainSelectedInstOperands,
21616 /* 59190 */ // GIR_Coverage, 1423,
21617 /* 59190 */ GIR_EraseRootFromParent_Done,
21618 /* 59191 */ // Label 1290: @59191
21619 /* 59191 */ GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(59245), // Rule ID 1424 //
21620 /* 59196 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21621 /* 59199 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21622 /* 59204 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21623 /* 59207 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21624 /* 59210 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21625 /* 59213 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21626 /* 59217 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21627 /* 59221 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21628 /* 59225 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4057:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALuv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
21629 /* 59225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv2i32),
21630 /* 59228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21631 /* 59230 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21632 /* 59232 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21633 /* 59234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21634 /* 59237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21635 /* 59243 */ GIR_RootConstrainSelectedInstOperands,
21636 /* 59244 */ // GIR_Coverage, 1424,
21637 /* 59244 */ GIR_EraseRootFromParent_Done,
21638 /* 59245 */ // Label 1291: @59245
21639 /* 59245 */ GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(59299), // Rule ID 1425 //
21640 /* 59250 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21641 /* 59253 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21642 /* 59258 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21643 /* 59261 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21644 /* 59264 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
21645 /* 59267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21646 /* 59271 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21647 /* 59275 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21648 /* 59279 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4057:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALuv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
21649 /* 59279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv16i8),
21650 /* 59282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21651 /* 59284 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21652 /* 59286 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21653 /* 59288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21654 /* 59291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21655 /* 59297 */ GIR_RootConstrainSelectedInstOperands,
21656 /* 59298 */ // GIR_Coverage, 1425,
21657 /* 59298 */ GIR_EraseRootFromParent_Done,
21658 /* 59299 */ // Label 1292: @59299
21659 /* 59299 */ GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(59353), // Rule ID 1426 //
21660 /* 59304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21661 /* 59307 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21662 /* 59312 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21663 /* 59315 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21664 /* 59318 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21665 /* 59321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21666 /* 59325 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21667 /* 59329 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21668 /* 59333 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4057:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALuv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
21669 /* 59333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i16),
21670 /* 59336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21671 /* 59338 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21672 /* 59340 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21673 /* 59342 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21674 /* 59345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21675 /* 59351 */ GIR_RootConstrainSelectedInstOperands,
21676 /* 59352 */ // GIR_Coverage, 1426,
21677 /* 59352 */ GIR_EraseRootFromParent_Done,
21678 /* 59353 */ // Label 1293: @59353
21679 /* 59353 */ GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(59407), // Rule ID 1427 //
21680 /* 59358 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21681 /* 59361 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21682 /* 59366 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
21683 /* 59369 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21684 /* 59372 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21685 /* 59375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21686 /* 59379 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21687 /* 59383 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21688 /* 59387 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4057:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALuv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
21689 /* 59387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i32),
21690 /* 59390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21691 /* 59392 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21692 /* 59394 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21693 /* 59396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21694 /* 59399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21695 /* 59405 */ GIR_RootConstrainSelectedInstOperands,
21696 /* 59406 */ // GIR_Coverage, 1427,
21697 /* 59406 */ GIR_EraseRootFromParent_Done,
21698 /* 59407 */ // Label 1294: @59407
21699 /* 59407 */ GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(59461), // Rule ID 1428 //
21700 /* 59412 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21701 /* 59415 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21702 /* 59420 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
21703 /* 59423 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21704 /* 59426 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21705 /* 59429 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21706 /* 59433 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21707 /* 59437 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21708 /* 59441 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4061:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21709 /* 59441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs8),
21710 /* 59444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21711 /* 59446 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21712 /* 59448 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21713 /* 59450 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21714 /* 59453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21715 /* 59459 */ GIR_RootConstrainSelectedInstOperands,
21716 /* 59460 */ // GIR_Coverage, 1428,
21717 /* 59460 */ GIR_EraseRootFromParent_Done,
21718 /* 59461 */ // Label 1295: @59461
21719 /* 59461 */ GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(59515), // Rule ID 1429 //
21720 /* 59466 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21721 /* 59469 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21722 /* 59474 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21723 /* 59477 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21724 /* 59480 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21725 /* 59483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21726 /* 59487 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21727 /* 59491 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21728 /* 59495 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4061:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21729 /* 59495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs16),
21730 /* 59498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21731 /* 59500 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21732 /* 59502 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21733 /* 59504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21734 /* 59507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21735 /* 59513 */ GIR_RootConstrainSelectedInstOperands,
21736 /* 59514 */ // GIR_Coverage, 1429,
21737 /* 59514 */ GIR_EraseRootFromParent_Done,
21738 /* 59515 */ // Label 1296: @59515
21739 /* 59515 */ GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(59569), // Rule ID 1430 //
21740 /* 59520 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21741 /* 59523 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21742 /* 59528 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21743 /* 59531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21744 /* 59534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21745 /* 59537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21746 /* 59541 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21747 /* 59545 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21748 /* 59549 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4061:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21749 /* 59549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs32),
21750 /* 59552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21751 /* 59554 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21752 /* 59556 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21753 /* 59558 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21754 /* 59561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21755 /* 59567 */ GIR_RootConstrainSelectedInstOperands,
21756 /* 59568 */ // GIR_Coverage, 1430,
21757 /* 59568 */ GIR_EraseRootFromParent_Done,
21758 /* 59569 */ // Label 1297: @59569
21759 /* 59569 */ GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(59623), // Rule ID 1431 //
21760 /* 59574 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21761 /* 59577 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu),
21762 /* 59582 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
21763 /* 59585 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21764 /* 59588 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21765 /* 59591 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21766 /* 59595 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21767 /* 59599 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21768 /* 59603 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4062:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21769 /* 59603 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu8),
21770 /* 59606 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21771 /* 59608 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21772 /* 59610 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21773 /* 59612 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21774 /* 59615 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21775 /* 59621 */ GIR_RootConstrainSelectedInstOperands,
21776 /* 59622 */ // GIR_Coverage, 1431,
21777 /* 59622 */ GIR_EraseRootFromParent_Done,
21778 /* 59623 */ // Label 1298: @59623
21779 /* 59623 */ GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(59677), // Rule ID 1432 //
21780 /* 59628 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21781 /* 59631 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu),
21782 /* 59636 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21783 /* 59639 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21784 /* 59642 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21785 /* 59645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21786 /* 59649 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21787 /* 59653 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21788 /* 59657 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4062:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21789 /* 59657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu16),
21790 /* 59660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21791 /* 59662 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21792 /* 59664 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21793 /* 59666 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21794 /* 59669 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21795 /* 59675 */ GIR_RootConstrainSelectedInstOperands,
21796 /* 59676 */ // GIR_Coverage, 1432,
21797 /* 59676 */ GIR_EraseRootFromParent_Done,
21798 /* 59677 */ // Label 1299: @59677
21799 /* 59677 */ GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(59731), // Rule ID 1433 //
21800 /* 59682 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21801 /* 59685 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu),
21802 /* 59690 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21803 /* 59693 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21804 /* 59696 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21805 /* 59699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21806 /* 59703 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21807 /* 59707 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21808 /* 59711 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4062:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21809 /* 59711 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu32),
21810 /* 59714 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21811 /* 59716 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21812 /* 59718 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21813 /* 59720 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21814 /* 59723 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21815 /* 59729 */ GIR_RootConstrainSelectedInstOperands,
21816 /* 59730 */ // GIR_Coverage, 1433,
21817 /* 59730 */ GIR_EraseRootFromParent_Done,
21818 /* 59731 */ // Label 1300: @59731
21819 /* 59731 */ GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(59785), // Rule ID 1434 //
21820 /* 59736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21821 /* 59739 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21822 /* 59744 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21823 /* 59747 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21824 /* 59750 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21825 /* 59753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21826 /* 59757 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21827 /* 59761 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21828 /* 59765 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4061:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMAXf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21829 /* 59765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXf),
21830 /* 59768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21831 /* 59770 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21832 /* 59772 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21833 /* 59774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21834 /* 59777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21835 /* 59783 */ GIR_RootConstrainSelectedInstOperands,
21836 /* 59784 */ // GIR_Coverage, 1434,
21837 /* 59784 */ GIR_EraseRootFromParent_Done,
21838 /* 59785 */ // Label 1301: @59785
21839 /* 59785 */ GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(59839), // Rule ID 1435 //
21840 /* 59790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21841 /* 59793 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21842 /* 59798 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21843 /* 59801 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21844 /* 59804 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21845 /* 59807 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21846 /* 59811 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21847 /* 59815 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21848 /* 59819 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4061:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMAXh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21849 /* 59819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXh),
21850 /* 59822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21851 /* 59824 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21852 /* 59826 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21853 /* 59828 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21854 /* 59831 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21855 /* 59837 */ GIR_RootConstrainSelectedInstOperands,
21856 /* 59838 */ // GIR_Coverage, 1435,
21857 /* 59838 */ GIR_EraseRootFromParent_Done,
21858 /* 59839 */ // Label 1302: @59839
21859 /* 59839 */ GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(59893), // Rule ID 1436 //
21860 /* 59844 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21861 /* 59847 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
21862 /* 59852 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
21863 /* 59855 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21864 /* 59858 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21865 /* 59861 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21866 /* 59865 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21867 /* 59869 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21868 /* 59873 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4063:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21869 /* 59873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs8),
21870 /* 59876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21871 /* 59878 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21872 /* 59880 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21873 /* 59882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21874 /* 59885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21875 /* 59891 */ GIR_RootConstrainSelectedInstOperands,
21876 /* 59892 */ // GIR_Coverage, 1436,
21877 /* 59892 */ GIR_EraseRootFromParent_Done,
21878 /* 59893 */ // Label 1303: @59893
21879 /* 59893 */ GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(59947), // Rule ID 1437 //
21880 /* 59898 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21881 /* 59901 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
21882 /* 59906 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21883 /* 59909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21884 /* 59912 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21885 /* 59915 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21886 /* 59919 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21887 /* 59923 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21888 /* 59927 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4063:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21889 /* 59927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs16),
21890 /* 59930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21891 /* 59932 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21892 /* 59934 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21893 /* 59936 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21894 /* 59939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21895 /* 59945 */ GIR_RootConstrainSelectedInstOperands,
21896 /* 59946 */ // GIR_Coverage, 1437,
21897 /* 59946 */ GIR_EraseRootFromParent_Done,
21898 /* 59947 */ // Label 1304: @59947
21899 /* 59947 */ GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(60001), // Rule ID 1438 //
21900 /* 59952 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21901 /* 59955 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
21902 /* 59960 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21903 /* 59963 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21904 /* 59966 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21905 /* 59969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21906 /* 59973 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21907 /* 59977 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21908 /* 59981 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4063:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21909 /* 59981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs32),
21910 /* 59984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21911 /* 59986 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21912 /* 59988 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21913 /* 59990 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21914 /* 59993 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21915 /* 59999 */ GIR_RootConstrainSelectedInstOperands,
21916 /* 60000 */ // GIR_Coverage, 1438,
21917 /* 60000 */ GIR_EraseRootFromParent_Done,
21918 /* 60001 */ // Label 1305: @60001
21919 /* 60001 */ GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(60055), // Rule ID 1439 //
21920 /* 60006 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21921 /* 60009 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu),
21922 /* 60014 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
21923 /* 60017 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21924 /* 60020 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21925 /* 60023 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21926 /* 60027 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21927 /* 60031 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21928 /* 60035 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4064:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21929 /* 60035 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu8),
21930 /* 60038 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21931 /* 60040 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21932 /* 60042 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21933 /* 60044 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21934 /* 60047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21935 /* 60053 */ GIR_RootConstrainSelectedInstOperands,
21936 /* 60054 */ // GIR_Coverage, 1439,
21937 /* 60054 */ GIR_EraseRootFromParent_Done,
21938 /* 60055 */ // Label 1306: @60055
21939 /* 60055 */ GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(60109), // Rule ID 1440 //
21940 /* 60060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21941 /* 60063 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu),
21942 /* 60068 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21943 /* 60071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21944 /* 60074 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21945 /* 60077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21946 /* 60081 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21947 /* 60085 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21948 /* 60089 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4064:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21949 /* 60089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu16),
21950 /* 60092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21951 /* 60094 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21952 /* 60096 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21953 /* 60098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21954 /* 60101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21955 /* 60107 */ GIR_RootConstrainSelectedInstOperands,
21956 /* 60108 */ // GIR_Coverage, 1440,
21957 /* 60108 */ GIR_EraseRootFromParent_Done,
21958 /* 60109 */ // Label 1307: @60109
21959 /* 60109 */ GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(60163), // Rule ID 1441 //
21960 /* 60114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21961 /* 60117 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu),
21962 /* 60122 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21963 /* 60125 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21964 /* 60128 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21965 /* 60131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21966 /* 60135 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21967 /* 60139 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21968 /* 60143 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4064:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21969 /* 60143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu32),
21970 /* 60146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21971 /* 60148 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21972 /* 60150 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21973 /* 60152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21974 /* 60155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21975 /* 60161 */ GIR_RootConstrainSelectedInstOperands,
21976 /* 60162 */ // GIR_Coverage, 1441,
21977 /* 60162 */ GIR_EraseRootFromParent_Done,
21978 /* 60163 */ // Label 1308: @60163
21979 /* 60163 */ GIM_Try, /*On fail goto*//*Label 1309*/ GIMT_Encode4(60217), // Rule ID 1442 //
21980 /* 60168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21981 /* 60171 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
21982 /* 60176 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21983 /* 60179 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21984 /* 60182 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21985 /* 60185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21986 /* 60189 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21987 /* 60193 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21988 /* 60197 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4063:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMINf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21989 /* 60197 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINf),
21990 /* 60200 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21991 /* 60202 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21992 /* 60204 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21993 /* 60206 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21994 /* 60209 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21995 /* 60215 */ GIR_RootConstrainSelectedInstOperands,
21996 /* 60216 */ // GIR_Coverage, 1442,
21997 /* 60216 */ GIR_EraseRootFromParent_Done,
21998 /* 60217 */ // Label 1309: @60217
21999 /* 60217 */ GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(60271), // Rule ID 1443 //
22000 /* 60222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
22001 /* 60225 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
22002 /* 60230 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22003 /* 60233 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22004 /* 60236 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22005 /* 60239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22006 /* 60243 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22007 /* 60247 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22008 /* 60251 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4063:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMINh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
22009 /* 60251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINh),
22010 /* 60254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22011 /* 60256 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22012 /* 60258 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22013 /* 60260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22014 /* 60263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22015 /* 60269 */ GIR_RootConstrainSelectedInstOperands,
22016 /* 60270 */ // GIR_Coverage, 1443,
22017 /* 60270 */ GIR_EraseRootFromParent_Done,
22018 /* 60271 */ // Label 1310: @60271
22019 /* 60271 */ GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(60325), // Rule ID 1450 //
22020 /* 60276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22021 /* 60279 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps),
22022 /* 60284 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22023 /* 60287 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22024 /* 60290 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22025 /* 60293 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22026 /* 60297 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22027 /* 60301 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22028 /* 60305 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4088:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRECPSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
22029 /* 60305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfd),
22030 /* 60308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22031 /* 60310 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22032 /* 60312 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22033 /* 60314 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22034 /* 60317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22035 /* 60323 */ GIR_RootConstrainSelectedInstOperands,
22036 /* 60324 */ // GIR_Coverage, 1450,
22037 /* 60324 */ GIR_EraseRootFromParent_Done,
22038 /* 60325 */ // Label 1311: @60325
22039 /* 60325 */ GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(60379), // Rule ID 1451 //
22040 /* 60330 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22041 /* 60333 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps),
22042 /* 60338 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22043 /* 60341 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22044 /* 60344 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22045 /* 60347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22046 /* 60351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22047 /* 60355 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22048 /* 60359 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4088:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRECPSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
22049 /* 60359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfq),
22050 /* 60362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22051 /* 60364 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22052 /* 60366 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22053 /* 60368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22054 /* 60371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22055 /* 60377 */ GIR_RootConstrainSelectedInstOperands,
22056 /* 60378 */ // GIR_Coverage, 1451,
22057 /* 60378 */ GIR_EraseRootFromParent_Done,
22058 /* 60379 */ // Label 1312: @60379
22059 /* 60379 */ GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(60433), // Rule ID 1452 //
22060 /* 60384 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
22061 /* 60387 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps),
22062 /* 60392 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22063 /* 60395 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22064 /* 60398 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22065 /* 60401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22066 /* 60405 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22067 /* 60409 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22068 /* 60413 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4088:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRECPShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
22069 /* 60413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShd),
22070 /* 60416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22071 /* 60418 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22072 /* 60420 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22073 /* 60422 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22074 /* 60425 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22075 /* 60431 */ GIR_RootConstrainSelectedInstOperands,
22076 /* 60432 */ // GIR_Coverage, 1452,
22077 /* 60432 */ GIR_EraseRootFromParent_Done,
22078 /* 60433 */ // Label 1313: @60433
22079 /* 60433 */ GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(60487), // Rule ID 1453 //
22080 /* 60438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
22081 /* 60441 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps),
22082 /* 60446 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22083 /* 60449 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22084 /* 60452 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22085 /* 60455 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22086 /* 60459 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22087 /* 60463 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22088 /* 60467 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4088:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRECPShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
22089 /* 60467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShq),
22090 /* 60470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22091 /* 60472 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22092 /* 60474 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22093 /* 60476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22094 /* 60479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22095 /* 60485 */ GIR_RootConstrainSelectedInstOperands,
22096 /* 60486 */ // GIR_Coverage, 1453,
22097 /* 60486 */ GIR_EraseRootFromParent_Done,
22098 /* 60487 */ // Label 1314: @60487
22099 /* 60487 */ GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(60541), // Rule ID 1460 //
22100 /* 60492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22101 /* 60495 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts),
22102 /* 60500 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22103 /* 60503 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22104 /* 60506 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22105 /* 60509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22106 /* 60513 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22107 /* 60517 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22108 /* 60521 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4095:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
22109 /* 60521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfd),
22110 /* 60524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22111 /* 60526 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22112 /* 60528 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22113 /* 60530 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22114 /* 60533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22115 /* 60539 */ GIR_RootConstrainSelectedInstOperands,
22116 /* 60540 */ // GIR_Coverage, 1460,
22117 /* 60540 */ GIR_EraseRootFromParent_Done,
22118 /* 60541 */ // Label 1315: @60541
22119 /* 60541 */ GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(60595), // Rule ID 1461 //
22120 /* 60546 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22121 /* 60549 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts),
22122 /* 60554 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22123 /* 60557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22124 /* 60560 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22125 /* 60563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22126 /* 60567 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22127 /* 60571 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22128 /* 60575 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4095:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
22129 /* 60575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfq),
22130 /* 60578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22131 /* 60580 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22132 /* 60582 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22133 /* 60584 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22134 /* 60587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22135 /* 60593 */ GIR_RootConstrainSelectedInstOperands,
22136 /* 60594 */ // GIR_Coverage, 1461,
22137 /* 60594 */ GIR_EraseRootFromParent_Done,
22138 /* 60595 */ // Label 1316: @60595
22139 /* 60595 */ GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(60649), // Rule ID 1462 //
22140 /* 60600 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
22141 /* 60603 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts),
22142 /* 60608 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22143 /* 60611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22144 /* 60614 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22145 /* 60617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22146 /* 60621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22147 /* 60625 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22148 /* 60629 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4095:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
22149 /* 60629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShd),
22150 /* 60632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22151 /* 60634 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22152 /* 60636 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22153 /* 60638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22154 /* 60641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22155 /* 60647 */ GIR_RootConstrainSelectedInstOperands,
22156 /* 60648 */ // GIR_Coverage, 1462,
22157 /* 60648 */ GIR_EraseRootFromParent_Done,
22158 /* 60649 */ // Label 1317: @60649
22159 /* 60649 */ GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(60703), // Rule ID 1463 //
22160 /* 60654 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
22161 /* 60657 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts),
22162 /* 60662 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22163 /* 60665 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22164 /* 60668 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22165 /* 60671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22166 /* 60675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22167 /* 60679 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22168 /* 60683 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4095:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
22169 /* 60683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShq),
22170 /* 60686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22171 /* 60688 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22172 /* 60690 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22173 /* 60692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22174 /* 60695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22175 /* 60701 */ GIR_RootConstrainSelectedInstOperands,
22176 /* 60702 */ // GIR_Coverage, 1463,
22177 /* 60702 */ GIR_EraseRootFromParent_Done,
22178 /* 60703 */ // Label 1318: @60703
22179 /* 60703 */ GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(60757), // Rule ID 1464 //
22180 /* 60708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22181 /* 60711 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22182 /* 60716 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22183 /* 60719 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22184 /* 60722 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22185 /* 60725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22186 /* 60729 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22187 /* 60733 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22188 /* 60737 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4098:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22189 /* 60737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i16),
22190 /* 60740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22191 /* 60742 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22192 /* 60744 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22193 /* 60746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22194 /* 60749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22195 /* 60755 */ GIR_RootConstrainSelectedInstOperands,
22196 /* 60756 */ // GIR_Coverage, 1464,
22197 /* 60756 */ GIR_EraseRootFromParent_Done,
22198 /* 60757 */ // Label 1319: @60757
22199 /* 60757 */ GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(60811), // Rule ID 1465 //
22200 /* 60762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22201 /* 60765 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22202 /* 60770 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22203 /* 60773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22204 /* 60776 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22205 /* 60779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22206 /* 60783 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22207 /* 60787 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22208 /* 60791 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4098:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22209 /* 60791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i32),
22210 /* 60794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22211 /* 60796 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22212 /* 60798 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22213 /* 60800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22214 /* 60803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22215 /* 60809 */ GIR_RootConstrainSelectedInstOperands,
22216 /* 60810 */ // GIR_Coverage, 1465,
22217 /* 60810 */ GIR_EraseRootFromParent_Done,
22218 /* 60811 */ // Label 1320: @60811
22219 /* 60811 */ GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(60865), // Rule ID 1466 //
22220 /* 60816 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22221 /* 60819 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22222 /* 60824 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22223 /* 60827 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22224 /* 60830 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22225 /* 60833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22226 /* 60837 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22227 /* 60841 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22228 /* 60845 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4098:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22229 /* 60845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i16),
22230 /* 60848 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22231 /* 60850 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22232 /* 60852 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22233 /* 60854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22234 /* 60857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22235 /* 60863 */ GIR_RootConstrainSelectedInstOperands,
22236 /* 60864 */ // GIR_Coverage, 1466,
22237 /* 60864 */ GIR_EraseRootFromParent_Done,
22238 /* 60865 */ // Label 1321: @60865
22239 /* 60865 */ GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(60919), // Rule ID 1467 //
22240 /* 60870 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22241 /* 60873 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22242 /* 60878 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22243 /* 60881 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22244 /* 60884 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22245 /* 60887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22246 /* 60891 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22247 /* 60895 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22248 /* 60899 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4098:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22249 /* 60899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i32),
22250 /* 60902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22251 /* 60904 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22252 /* 60906 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22253 /* 60908 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22254 /* 60911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22255 /* 60917 */ GIR_RootConstrainSelectedInstOperands,
22256 /* 60918 */ // GIR_Coverage, 1467,
22257 /* 60918 */ GIR_EraseRootFromParent_Done,
22258 /* 60919 */ // Label 1322: @60919
22259 /* 60919 */ GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(60973), // Rule ID 1468 //
22260 /* 60924 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22261 /* 60927 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22262 /* 60932 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
22263 /* 60935 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22264 /* 60938 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22265 /* 60941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22266 /* 60945 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22267 /* 60949 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22268 /* 60953 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4098:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22269 /* 60953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i8),
22270 /* 60956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22271 /* 60958 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22272 /* 60960 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22273 /* 60962 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22274 /* 60965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22275 /* 60971 */ GIR_RootConstrainSelectedInstOperands,
22276 /* 60972 */ // GIR_Coverage, 1468,
22277 /* 60972 */ GIR_EraseRootFromParent_Done,
22278 /* 60973 */ // Label 1323: @60973
22279 /* 60973 */ GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(61027), // Rule ID 1469 //
22280 /* 60978 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22281 /* 60981 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22282 /* 60986 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22283 /* 60989 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22284 /* 60992 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22285 /* 60995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22286 /* 60999 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22287 /* 61003 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22288 /* 61007 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4098:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22289 /* 61007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv16i8),
22290 /* 61010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22291 /* 61012 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22292 /* 61014 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22293 /* 61016 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22294 /* 61019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22295 /* 61025 */ GIR_RootConstrainSelectedInstOperands,
22296 /* 61026 */ // GIR_Coverage, 1469,
22297 /* 61026 */ GIR_EraseRootFromParent_Done,
22298 /* 61027 */ // Label 1324: @61027
22299 /* 61027 */ GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(61081), // Rule ID 1470 //
22300 /* 61032 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22301 /* 61035 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22302 /* 61040 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22303 /* 61043 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22304 /* 61046 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22305 /* 61049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22306 /* 61053 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22307 /* 61057 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22308 /* 61061 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4098:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22309 /* 61061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv1i64),
22310 /* 61064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22311 /* 61066 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22312 /* 61068 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22313 /* 61070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22314 /* 61073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22315 /* 61079 */ GIR_RootConstrainSelectedInstOperands,
22316 /* 61080 */ // GIR_Coverage, 1470,
22317 /* 61080 */ GIR_EraseRootFromParent_Done,
22318 /* 61081 */ // Label 1325: @61081
22319 /* 61081 */ GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(61135), // Rule ID 1471 //
22320 /* 61086 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22321 /* 61089 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22322 /* 61094 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
22323 /* 61097 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22324 /* 61100 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22325 /* 61103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22326 /* 61107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22327 /* 61111 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22328 /* 61115 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4098:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22329 /* 61115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i64),
22330 /* 61118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22331 /* 61120 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22332 /* 61122 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22333 /* 61124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22334 /* 61127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22335 /* 61133 */ GIR_RootConstrainSelectedInstOperands,
22336 /* 61134 */ // GIR_Coverage, 1471,
22337 /* 61134 */ GIR_EraseRootFromParent_Done,
22338 /* 61135 */ // Label 1326: @61135
22339 /* 61135 */ GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(61189), // Rule ID 1472 //
22340 /* 61140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22341 /* 61143 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22342 /* 61148 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22343 /* 61151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22344 /* 61154 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22345 /* 61157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22346 /* 61161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22347 /* 61165 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22348 /* 61169 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4099:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22349 /* 61169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i16),
22350 /* 61172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22351 /* 61174 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22352 /* 61176 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22353 /* 61178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22354 /* 61181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22355 /* 61187 */ GIR_RootConstrainSelectedInstOperands,
22356 /* 61188 */ // GIR_Coverage, 1472,
22357 /* 61188 */ GIR_EraseRootFromParent_Done,
22358 /* 61189 */ // Label 1327: @61189
22359 /* 61189 */ GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(61243), // Rule ID 1473 //
22360 /* 61194 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22361 /* 61197 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22362 /* 61202 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22363 /* 61205 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22364 /* 61208 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22365 /* 61211 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22366 /* 61215 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22367 /* 61219 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22368 /* 61223 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4099:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22369 /* 61223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i32),
22370 /* 61226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22371 /* 61228 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22372 /* 61230 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22373 /* 61232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22374 /* 61235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22375 /* 61241 */ GIR_RootConstrainSelectedInstOperands,
22376 /* 61242 */ // GIR_Coverage, 1473,
22377 /* 61242 */ GIR_EraseRootFromParent_Done,
22378 /* 61243 */ // Label 1328: @61243
22379 /* 61243 */ GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(61297), // Rule ID 1474 //
22380 /* 61248 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22381 /* 61251 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22382 /* 61256 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22383 /* 61259 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22384 /* 61262 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22385 /* 61265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22386 /* 61269 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22387 /* 61273 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22388 /* 61277 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4099:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22389 /* 61277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i16),
22390 /* 61280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22391 /* 61282 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22392 /* 61284 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22393 /* 61286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22394 /* 61289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22395 /* 61295 */ GIR_RootConstrainSelectedInstOperands,
22396 /* 61296 */ // GIR_Coverage, 1474,
22397 /* 61296 */ GIR_EraseRootFromParent_Done,
22398 /* 61297 */ // Label 1329: @61297
22399 /* 61297 */ GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(61351), // Rule ID 1475 //
22400 /* 61302 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22401 /* 61305 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22402 /* 61310 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22403 /* 61313 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22404 /* 61316 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22405 /* 61319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22406 /* 61323 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22407 /* 61327 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22408 /* 61331 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4099:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22409 /* 61331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i32),
22410 /* 61334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22411 /* 61336 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22412 /* 61338 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22413 /* 61340 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22414 /* 61343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22415 /* 61349 */ GIR_RootConstrainSelectedInstOperands,
22416 /* 61350 */ // GIR_Coverage, 1475,
22417 /* 61350 */ GIR_EraseRootFromParent_Done,
22418 /* 61351 */ // Label 1330: @61351
22419 /* 61351 */ GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(61405), // Rule ID 1476 //
22420 /* 61356 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22421 /* 61359 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22422 /* 61364 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
22423 /* 61367 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22424 /* 61370 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22425 /* 61373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22426 /* 61377 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22427 /* 61381 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22428 /* 61385 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4099:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22429 /* 61385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i8),
22430 /* 61388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22431 /* 61390 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22432 /* 61392 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22433 /* 61394 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22434 /* 61397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22435 /* 61403 */ GIR_RootConstrainSelectedInstOperands,
22436 /* 61404 */ // GIR_Coverage, 1476,
22437 /* 61404 */ GIR_EraseRootFromParent_Done,
22438 /* 61405 */ // Label 1331: @61405
22439 /* 61405 */ GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(61459), // Rule ID 1477 //
22440 /* 61410 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22441 /* 61413 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22442 /* 61418 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22443 /* 61421 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22444 /* 61424 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22445 /* 61427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22446 /* 61431 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22447 /* 61435 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22448 /* 61439 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4099:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22449 /* 61439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv16i8),
22450 /* 61442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22451 /* 61444 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22452 /* 61446 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22453 /* 61448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22454 /* 61451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22455 /* 61457 */ GIR_RootConstrainSelectedInstOperands,
22456 /* 61458 */ // GIR_Coverage, 1477,
22457 /* 61458 */ GIR_EraseRootFromParent_Done,
22458 /* 61459 */ // Label 1332: @61459
22459 /* 61459 */ GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(61513), // Rule ID 1478 //
22460 /* 61464 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22461 /* 61467 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22462 /* 61472 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22463 /* 61475 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22464 /* 61478 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22465 /* 61481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22466 /* 61485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22467 /* 61489 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22468 /* 61493 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4099:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22469 /* 61493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv1i64),
22470 /* 61496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22471 /* 61498 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22472 /* 61500 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22473 /* 61502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22474 /* 61505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22475 /* 61511 */ GIR_RootConstrainSelectedInstOperands,
22476 /* 61512 */ // GIR_Coverage, 1478,
22477 /* 61512 */ GIR_EraseRootFromParent_Done,
22478 /* 61513 */ // Label 1333: @61513
22479 /* 61513 */ GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(61567), // Rule ID 1479 //
22480 /* 61518 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22481 /* 61521 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22482 /* 61526 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
22483 /* 61529 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22484 /* 61532 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22485 /* 61535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22486 /* 61539 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22487 /* 61543 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22488 /* 61547 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4099:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22489 /* 61547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i64),
22490 /* 61550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22491 /* 61552 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22492 /* 61554 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22493 /* 61556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22494 /* 61559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22495 /* 61565 */ GIR_RootConstrainSelectedInstOperands,
22496 /* 61566 */ // GIR_Coverage, 1479,
22497 /* 61566 */ GIR_EraseRootFromParent_Done,
22498 /* 61567 */ // Label 1334: @61567
22499 /* 61567 */ GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(61621), // Rule ID 1513 //
22500 /* 61572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22501 /* 61575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22502 /* 61580 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22503 /* 61583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22504 /* 61586 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22505 /* 61589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22506 /* 61593 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22507 /* 61597 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22508 /* 61601 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4092:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22509 /* 61601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i16),
22510 /* 61604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22511 /* 61606 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22512 /* 61608 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22513 /* 61610 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22514 /* 61613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22515 /* 61619 */ GIR_RootConstrainSelectedInstOperands,
22516 /* 61620 */ // GIR_Coverage, 1513,
22517 /* 61620 */ GIR_EraseRootFromParent_Done,
22518 /* 61621 */ // Label 1335: @61621
22519 /* 61621 */ GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(61675), // Rule ID 1514 //
22520 /* 61626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22521 /* 61629 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22522 /* 61634 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22523 /* 61637 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22524 /* 61640 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22525 /* 61643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22526 /* 61647 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22527 /* 61651 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22528 /* 61655 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4092:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22529 /* 61655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i32),
22530 /* 61658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22531 /* 61660 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22532 /* 61662 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22533 /* 61664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22534 /* 61667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22535 /* 61673 */ GIR_RootConstrainSelectedInstOperands,
22536 /* 61674 */ // GIR_Coverage, 1514,
22537 /* 61674 */ GIR_EraseRootFromParent_Done,
22538 /* 61675 */ // Label 1336: @61675
22539 /* 61675 */ GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(61729), // Rule ID 1515 //
22540 /* 61680 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22541 /* 61683 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22542 /* 61688 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22543 /* 61691 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22544 /* 61694 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22545 /* 61697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22546 /* 61701 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22547 /* 61705 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22548 /* 61709 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4092:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22549 /* 61709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i16),
22550 /* 61712 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22551 /* 61714 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22552 /* 61716 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22553 /* 61718 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22554 /* 61721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22555 /* 61727 */ GIR_RootConstrainSelectedInstOperands,
22556 /* 61728 */ // GIR_Coverage, 1515,
22557 /* 61728 */ GIR_EraseRootFromParent_Done,
22558 /* 61729 */ // Label 1337: @61729
22559 /* 61729 */ GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(61783), // Rule ID 1516 //
22560 /* 61734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22561 /* 61737 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22562 /* 61742 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22563 /* 61745 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22564 /* 61748 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22565 /* 61751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22566 /* 61755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22567 /* 61759 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22568 /* 61763 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4092:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22569 /* 61763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i32),
22570 /* 61766 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22571 /* 61768 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22572 /* 61770 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22573 /* 61772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22574 /* 61775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22575 /* 61781 */ GIR_RootConstrainSelectedInstOperands,
22576 /* 61782 */ // GIR_Coverage, 1516,
22577 /* 61782 */ GIR_EraseRootFromParent_Done,
22578 /* 61783 */ // Label 1338: @61783
22579 /* 61783 */ GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(61837), // Rule ID 1517 //
22580 /* 61788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22581 /* 61791 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22582 /* 61796 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
22583 /* 61799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22584 /* 61802 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22585 /* 61805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22586 /* 61809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22587 /* 61813 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22588 /* 61817 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4092:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22589 /* 61817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i8),
22590 /* 61820 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22591 /* 61822 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22592 /* 61824 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22593 /* 61826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22594 /* 61829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22595 /* 61835 */ GIR_RootConstrainSelectedInstOperands,
22596 /* 61836 */ // GIR_Coverage, 1517,
22597 /* 61836 */ GIR_EraseRootFromParent_Done,
22598 /* 61837 */ // Label 1339: @61837
22599 /* 61837 */ GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(61891), // Rule ID 1518 //
22600 /* 61842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22601 /* 61845 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22602 /* 61850 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22603 /* 61853 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22604 /* 61856 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22605 /* 61859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22606 /* 61863 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22607 /* 61867 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22608 /* 61871 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4092:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22609 /* 61871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv16i8),
22610 /* 61874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22611 /* 61876 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22612 /* 61878 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22613 /* 61880 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22614 /* 61883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22615 /* 61889 */ GIR_RootConstrainSelectedInstOperands,
22616 /* 61890 */ // GIR_Coverage, 1518,
22617 /* 61890 */ GIR_EraseRootFromParent_Done,
22618 /* 61891 */ // Label 1340: @61891
22619 /* 61891 */ GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(61945), // Rule ID 1519 //
22620 /* 61896 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22621 /* 61899 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22622 /* 61904 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22623 /* 61907 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22624 /* 61910 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22625 /* 61913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22626 /* 61917 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22627 /* 61921 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22628 /* 61925 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4092:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22629 /* 61925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv1i64),
22630 /* 61928 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22631 /* 61930 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22632 /* 61932 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22633 /* 61934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22634 /* 61937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22635 /* 61943 */ GIR_RootConstrainSelectedInstOperands,
22636 /* 61944 */ // GIR_Coverage, 1519,
22637 /* 61944 */ GIR_EraseRootFromParent_Done,
22638 /* 61945 */ // Label 1341: @61945
22639 /* 61945 */ GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(61999), // Rule ID 1520 //
22640 /* 61950 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22641 /* 61953 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22642 /* 61958 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
22643 /* 61961 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22644 /* 61964 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22645 /* 61967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22646 /* 61971 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22647 /* 61975 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22648 /* 61979 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4092:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22649 /* 61979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i64),
22650 /* 61982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22651 /* 61984 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22652 /* 61986 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22653 /* 61988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22654 /* 61991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22655 /* 61997 */ GIR_RootConstrainSelectedInstOperands,
22656 /* 61998 */ // GIR_Coverage, 1520,
22657 /* 61998 */ GIR_EraseRootFromParent_Done,
22658 /* 61999 */ // Label 1342: @61999
22659 /* 61999 */ GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(62053), // Rule ID 1521 //
22660 /* 62004 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22661 /* 62007 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22662 /* 62012 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22663 /* 62015 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22664 /* 62018 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22665 /* 62021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22666 /* 62025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22667 /* 62029 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22668 /* 62033 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4093:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22669 /* 62033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i16),
22670 /* 62036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22671 /* 62038 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22672 /* 62040 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22673 /* 62042 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22674 /* 62045 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22675 /* 62051 */ GIR_RootConstrainSelectedInstOperands,
22676 /* 62052 */ // GIR_Coverage, 1521,
22677 /* 62052 */ GIR_EraseRootFromParent_Done,
22678 /* 62053 */ // Label 1343: @62053
22679 /* 62053 */ GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(62107), // Rule ID 1522 //
22680 /* 62058 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22681 /* 62061 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22682 /* 62066 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22683 /* 62069 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22684 /* 62072 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22685 /* 62075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22686 /* 62079 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22687 /* 62083 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22688 /* 62087 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4093:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22689 /* 62087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i32),
22690 /* 62090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22691 /* 62092 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22692 /* 62094 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22693 /* 62096 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22694 /* 62099 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22695 /* 62105 */ GIR_RootConstrainSelectedInstOperands,
22696 /* 62106 */ // GIR_Coverage, 1522,
22697 /* 62106 */ GIR_EraseRootFromParent_Done,
22698 /* 62107 */ // Label 1344: @62107
22699 /* 62107 */ GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(62161), // Rule ID 1523 //
22700 /* 62112 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22701 /* 62115 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22702 /* 62120 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22703 /* 62123 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22704 /* 62126 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22705 /* 62129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22706 /* 62133 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22707 /* 62137 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22708 /* 62141 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4093:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22709 /* 62141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i16),
22710 /* 62144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22711 /* 62146 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22712 /* 62148 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22713 /* 62150 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22714 /* 62153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22715 /* 62159 */ GIR_RootConstrainSelectedInstOperands,
22716 /* 62160 */ // GIR_Coverage, 1523,
22717 /* 62160 */ GIR_EraseRootFromParent_Done,
22718 /* 62161 */ // Label 1345: @62161
22719 /* 62161 */ GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(62215), // Rule ID 1524 //
22720 /* 62166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22721 /* 62169 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22722 /* 62174 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22723 /* 62177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22724 /* 62180 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22725 /* 62183 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22726 /* 62187 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22727 /* 62191 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22728 /* 62195 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4093:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22729 /* 62195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i32),
22730 /* 62198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22731 /* 62200 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22732 /* 62202 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22733 /* 62204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22734 /* 62207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22735 /* 62213 */ GIR_RootConstrainSelectedInstOperands,
22736 /* 62214 */ // GIR_Coverage, 1524,
22737 /* 62214 */ GIR_EraseRootFromParent_Done,
22738 /* 62215 */ // Label 1346: @62215
22739 /* 62215 */ GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(62269), // Rule ID 1525 //
22740 /* 62220 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22741 /* 62223 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22742 /* 62228 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
22743 /* 62231 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22744 /* 62234 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22745 /* 62237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22746 /* 62241 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22747 /* 62245 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22748 /* 62249 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4093:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22749 /* 62249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i8),
22750 /* 62252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22751 /* 62254 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22752 /* 62256 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22753 /* 62258 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22754 /* 62261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22755 /* 62267 */ GIR_RootConstrainSelectedInstOperands,
22756 /* 62268 */ // GIR_Coverage, 1525,
22757 /* 62268 */ GIR_EraseRootFromParent_Done,
22758 /* 62269 */ // Label 1347: @62269
22759 /* 62269 */ GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(62323), // Rule ID 1526 //
22760 /* 62274 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22761 /* 62277 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22762 /* 62282 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22763 /* 62285 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22764 /* 62288 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22765 /* 62291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22766 /* 62295 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22767 /* 62299 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22768 /* 62303 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4093:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22769 /* 62303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv16i8),
22770 /* 62306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22771 /* 62308 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22772 /* 62310 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22773 /* 62312 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22774 /* 62315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22775 /* 62321 */ GIR_RootConstrainSelectedInstOperands,
22776 /* 62322 */ // GIR_Coverage, 1526,
22777 /* 62322 */ GIR_EraseRootFromParent_Done,
22778 /* 62323 */ // Label 1348: @62323
22779 /* 62323 */ GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(62377), // Rule ID 1527 //
22780 /* 62328 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22781 /* 62331 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22782 /* 62336 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22783 /* 62339 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22784 /* 62342 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22785 /* 62345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22786 /* 62349 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22787 /* 62353 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22788 /* 62357 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4093:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22789 /* 62357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv1i64),
22790 /* 62360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22791 /* 62362 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22792 /* 62364 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22793 /* 62366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22794 /* 62369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22795 /* 62375 */ GIR_RootConstrainSelectedInstOperands,
22796 /* 62376 */ // GIR_Coverage, 1527,
22797 /* 62376 */ GIR_EraseRootFromParent_Done,
22798 /* 62377 */ // Label 1349: @62377
22799 /* 62377 */ GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(62431), // Rule ID 1528 //
22800 /* 62382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22801 /* 62385 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22802 /* 62390 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
22803 /* 62393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22804 /* 62396 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22805 /* 62399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22806 /* 62403 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22807 /* 62407 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22808 /* 62411 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4093:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22809 /* 62411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i64),
22810 /* 62414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22811 /* 62416 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22812 /* 62418 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22813 /* 62420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22814 /* 62423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22815 /* 62429 */ GIR_RootConstrainSelectedInstOperands,
22816 /* 62430 */ // GIR_Coverage, 1528,
22817 /* 62430 */ GIR_EraseRootFromParent_Done,
22818 /* 62431 */ // Label 1350: @62431
22819 /* 62431 */ GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(62485), // Rule ID 1548 //
22820 /* 62436 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22821 /* 62439 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22822 /* 62444 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22823 /* 62447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22824 /* 62450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22825 /* 62453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22826 /* 62457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22827 /* 62461 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22828 /* 62465 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4083:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22829 /* 62465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i16),
22830 /* 62468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22831 /* 62470 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22832 /* 62472 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22833 /* 62474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22834 /* 62477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22835 /* 62483 */ GIR_RootConstrainSelectedInstOperands,
22836 /* 62484 */ // GIR_Coverage, 1548,
22837 /* 62484 */ GIR_EraseRootFromParent_Done,
22838 /* 62485 */ // Label 1351: @62485
22839 /* 62485 */ GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(62539), // Rule ID 1549 //
22840 /* 62490 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22841 /* 62493 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22842 /* 62498 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22843 /* 62501 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22844 /* 62504 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22845 /* 62507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22846 /* 62511 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22847 /* 62515 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22848 /* 62519 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4083:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22849 /* 62519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i32),
22850 /* 62522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22851 /* 62524 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22852 /* 62526 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22853 /* 62528 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22854 /* 62531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22855 /* 62537 */ GIR_RootConstrainSelectedInstOperands,
22856 /* 62538 */ // GIR_Coverage, 1549,
22857 /* 62538 */ GIR_EraseRootFromParent_Done,
22858 /* 62539 */ // Label 1352: @62539
22859 /* 62539 */ GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(62593), // Rule ID 1550 //
22860 /* 62544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22861 /* 62547 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22862 /* 62552 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22863 /* 62555 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22864 /* 62558 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22865 /* 62561 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22866 /* 62565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22867 /* 62569 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22868 /* 62573 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4083:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22869 /* 62573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i16),
22870 /* 62576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22871 /* 62578 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22872 /* 62580 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22873 /* 62582 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22874 /* 62585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22875 /* 62591 */ GIR_RootConstrainSelectedInstOperands,
22876 /* 62592 */ // GIR_Coverage, 1550,
22877 /* 62592 */ GIR_EraseRootFromParent_Done,
22878 /* 62593 */ // Label 1353: @62593
22879 /* 62593 */ GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(62647), // Rule ID 1551 //
22880 /* 62598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22881 /* 62601 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22882 /* 62606 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22883 /* 62609 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22884 /* 62612 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22885 /* 62615 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22886 /* 62619 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22887 /* 62623 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22888 /* 62627 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4083:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22889 /* 62627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i32),
22890 /* 62630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22891 /* 62632 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22892 /* 62634 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22893 /* 62636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22894 /* 62639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22895 /* 62645 */ GIR_RootConstrainSelectedInstOperands,
22896 /* 62646 */ // GIR_Coverage, 1551,
22897 /* 62646 */ GIR_EraseRootFromParent_Done,
22898 /* 62647 */ // Label 1354: @62647
22899 /* 62647 */ GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(62701), // Rule ID 1552 //
22900 /* 62652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22901 /* 62655 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22902 /* 62660 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
22903 /* 62663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22904 /* 62666 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22905 /* 62669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22906 /* 62673 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22907 /* 62677 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22908 /* 62681 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4083:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22909 /* 62681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i8),
22910 /* 62684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22911 /* 62686 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22912 /* 62688 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22913 /* 62690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22914 /* 62693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22915 /* 62699 */ GIR_RootConstrainSelectedInstOperands,
22916 /* 62700 */ // GIR_Coverage, 1552,
22917 /* 62700 */ GIR_EraseRootFromParent_Done,
22918 /* 62701 */ // Label 1355: @62701
22919 /* 62701 */ GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(62755), // Rule ID 1553 //
22920 /* 62706 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22921 /* 62709 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22922 /* 62714 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22923 /* 62717 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22924 /* 62720 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22925 /* 62723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22926 /* 62727 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22927 /* 62731 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22928 /* 62735 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4083:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22929 /* 62735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv16i8),
22930 /* 62738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22931 /* 62740 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22932 /* 62742 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22933 /* 62744 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22934 /* 62747 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22935 /* 62753 */ GIR_RootConstrainSelectedInstOperands,
22936 /* 62754 */ // GIR_Coverage, 1553,
22937 /* 62754 */ GIR_EraseRootFromParent_Done,
22938 /* 62755 */ // Label 1356: @62755
22939 /* 62755 */ GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(62809), // Rule ID 1554 //
22940 /* 62760 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22941 /* 62763 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22942 /* 62768 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22943 /* 62771 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22944 /* 62774 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22945 /* 62777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22946 /* 62781 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22947 /* 62785 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22948 /* 62789 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4083:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22949 /* 62789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv1i64),
22950 /* 62792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22951 /* 62794 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22952 /* 62796 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22953 /* 62798 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22954 /* 62801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22955 /* 62807 */ GIR_RootConstrainSelectedInstOperands,
22956 /* 62808 */ // GIR_Coverage, 1554,
22957 /* 62808 */ GIR_EraseRootFromParent_Done,
22958 /* 62809 */ // Label 1357: @62809
22959 /* 62809 */ GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(62863), // Rule ID 1555 //
22960 /* 62814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22961 /* 62817 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22962 /* 62822 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
22963 /* 62825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22964 /* 62828 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22965 /* 62831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22966 /* 62835 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22967 /* 62839 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22968 /* 62843 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4083:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22969 /* 62843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i64),
22970 /* 62846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22971 /* 62848 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22972 /* 62850 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22973 /* 62852 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22974 /* 62855 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22975 /* 62861 */ GIR_RootConstrainSelectedInstOperands,
22976 /* 62862 */ // GIR_Coverage, 1555,
22977 /* 62862 */ GIR_EraseRootFromParent_Done,
22978 /* 62863 */ // Label 1358: @62863
22979 /* 62863 */ GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(62917), // Rule ID 1556 //
22980 /* 62868 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22981 /* 62871 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
22982 /* 62876 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22983 /* 62879 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22984 /* 62882 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22985 /* 62885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22986 /* 62889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22987 /* 62893 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22988 /* 62897 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4085:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22989 /* 62897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i16),
22990 /* 62900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22991 /* 62902 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22992 /* 62904 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22993 /* 62906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22994 /* 62909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22995 /* 62915 */ GIR_RootConstrainSelectedInstOperands,
22996 /* 62916 */ // GIR_Coverage, 1556,
22997 /* 62916 */ GIR_EraseRootFromParent_Done,
22998 /* 62917 */ // Label 1359: @62917
22999 /* 62917 */ GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(62971), // Rule ID 1557 //
23000 /* 62922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23001 /* 62925 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
23002 /* 62930 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
23003 /* 62933 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
23004 /* 62936 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
23005 /* 62939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23006 /* 62943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23007 /* 62947 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23008 /* 62951 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4085:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
23009 /* 62951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i32),
23010 /* 62954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23011 /* 62956 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23012 /* 62958 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23013 /* 62960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23014 /* 62963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23015 /* 62969 */ GIR_RootConstrainSelectedInstOperands,
23016 /* 62970 */ // GIR_Coverage, 1557,
23017 /* 62970 */ GIR_EraseRootFromParent_Done,
23018 /* 62971 */ // Label 1360: @62971
23019 /* 62971 */ GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(63025), // Rule ID 1558 //
23020 /* 62976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23021 /* 62979 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
23022 /* 62984 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23023 /* 62987 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23024 /* 62990 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23025 /* 62993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23026 /* 62997 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23027 /* 63001 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23028 /* 63005 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4085:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
23029 /* 63005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i16),
23030 /* 63008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23031 /* 63010 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23032 /* 63012 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23033 /* 63014 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23034 /* 63017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23035 /* 63023 */ GIR_RootConstrainSelectedInstOperands,
23036 /* 63024 */ // GIR_Coverage, 1558,
23037 /* 63024 */ GIR_EraseRootFromParent_Done,
23038 /* 63025 */ // Label 1361: @63025
23039 /* 63025 */ GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(63079), // Rule ID 1559 //
23040 /* 63030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23041 /* 63033 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
23042 /* 63038 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23043 /* 63041 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23044 /* 63044 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23045 /* 63047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23046 /* 63051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23047 /* 63055 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23048 /* 63059 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4085:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
23049 /* 63059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i32),
23050 /* 63062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23051 /* 63064 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23052 /* 63066 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23053 /* 63068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23054 /* 63071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23055 /* 63077 */ GIR_RootConstrainSelectedInstOperands,
23056 /* 63078 */ // GIR_Coverage, 1559,
23057 /* 63078 */ GIR_EraseRootFromParent_Done,
23058 /* 63079 */ // Label 1362: @63079
23059 /* 63079 */ GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(63133), // Rule ID 1560 //
23060 /* 63084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23061 /* 63087 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
23062 /* 63092 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
23063 /* 63095 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
23064 /* 63098 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
23065 /* 63101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23066 /* 63105 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23067 /* 63109 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23068 /* 63113 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4085:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
23069 /* 63113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i8),
23070 /* 63116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23071 /* 63118 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23072 /* 63120 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23073 /* 63122 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23074 /* 63125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23075 /* 63131 */ GIR_RootConstrainSelectedInstOperands,
23076 /* 63132 */ // GIR_Coverage, 1560,
23077 /* 63132 */ GIR_EraseRootFromParent_Done,
23078 /* 63133 */ // Label 1363: @63133
23079 /* 63133 */ GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(63187), // Rule ID 1561 //
23080 /* 63138 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23081 /* 63141 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
23082 /* 63146 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23083 /* 63149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23084 /* 63152 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23085 /* 63155 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23086 /* 63159 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23087 /* 63163 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23088 /* 63167 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4085:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
23089 /* 63167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv16i8),
23090 /* 63170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23091 /* 63172 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23092 /* 63174 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23093 /* 63176 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23094 /* 63179 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23095 /* 63185 */ GIR_RootConstrainSelectedInstOperands,
23096 /* 63186 */ // GIR_Coverage, 1561,
23097 /* 63186 */ GIR_EraseRootFromParent_Done,
23098 /* 63187 */ // Label 1364: @63187
23099 /* 63187 */ GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(63241), // Rule ID 1562 //
23100 /* 63192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23101 /* 63195 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
23102 /* 63200 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
23103 /* 63203 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23104 /* 63206 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23105 /* 63209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23106 /* 63213 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23107 /* 63217 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23108 /* 63221 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4085:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
23109 /* 63221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv1i64),
23110 /* 63224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23111 /* 63226 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23112 /* 63228 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23113 /* 63230 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23114 /* 63233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23115 /* 63239 */ GIR_RootConstrainSelectedInstOperands,
23116 /* 63240 */ // GIR_Coverage, 1562,
23117 /* 63240 */ GIR_EraseRootFromParent_Done,
23118 /* 63241 */ // Label 1365: @63241
23119 /* 63241 */ GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(63295), // Rule ID 1563 //
23120 /* 63246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23121 /* 63249 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
23122 /* 63254 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23123 /* 63257 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23124 /* 63260 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23125 /* 63263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23126 /* 63267 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23127 /* 63271 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23128 /* 63275 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4085:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
23129 /* 63275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i64),
23130 /* 63278 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23131 /* 63280 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23132 /* 63282 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23133 /* 63284 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23134 /* 63287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23135 /* 63293 */ GIR_RootConstrainSelectedInstOperands,
23136 /* 63294 */ // GIR_Coverage, 1563,
23137 /* 63294 */ GIR_EraseRootFromParent_Done,
23138 /* 63295 */ // Label 1366: @63295
23139 /* 63295 */ GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(63349), // Rule ID 1597 //
23140 /* 63300 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23141 /* 63303 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23142 /* 63308 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
23143 /* 63311 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
23144 /* 63314 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
23145 /* 63317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23146 /* 63321 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23147 /* 63325 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23148 /* 63329 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4078:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
23149 /* 63329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i16),
23150 /* 63332 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23151 /* 63334 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23152 /* 63336 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23153 /* 63338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23154 /* 63341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23155 /* 63347 */ GIR_RootConstrainSelectedInstOperands,
23156 /* 63348 */ // GIR_Coverage, 1597,
23157 /* 63348 */ GIR_EraseRootFromParent_Done,
23158 /* 63349 */ // Label 1367: @63349
23159 /* 63349 */ GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(63403), // Rule ID 1598 //
23160 /* 63354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23161 /* 63357 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23162 /* 63362 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
23163 /* 63365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
23164 /* 63368 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
23165 /* 63371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23166 /* 63375 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23167 /* 63379 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23168 /* 63383 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4078:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
23169 /* 63383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i32),
23170 /* 63386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23171 /* 63388 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23172 /* 63390 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23173 /* 63392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23174 /* 63395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23175 /* 63401 */ GIR_RootConstrainSelectedInstOperands,
23176 /* 63402 */ // GIR_Coverage, 1598,
23177 /* 63402 */ GIR_EraseRootFromParent_Done,
23178 /* 63403 */ // Label 1368: @63403
23179 /* 63403 */ GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(63457), // Rule ID 1599 //
23180 /* 63408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23181 /* 63411 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23182 /* 63416 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23183 /* 63419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23184 /* 63422 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23185 /* 63425 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23186 /* 63429 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23187 /* 63433 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23188 /* 63437 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4078:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
23189 /* 63437 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i16),
23190 /* 63440 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23191 /* 63442 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23192 /* 63444 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23193 /* 63446 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23194 /* 63449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23195 /* 63455 */ GIR_RootConstrainSelectedInstOperands,
23196 /* 63456 */ // GIR_Coverage, 1599,
23197 /* 63456 */ GIR_EraseRootFromParent_Done,
23198 /* 63457 */ // Label 1369: @63457
23199 /* 63457 */ GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(63511), // Rule ID 1600 //
23200 /* 63462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23201 /* 63465 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23202 /* 63470 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23203 /* 63473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23204 /* 63476 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23205 /* 63479 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23206 /* 63483 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23207 /* 63487 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23208 /* 63491 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4078:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
23209 /* 63491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i32),
23210 /* 63494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23211 /* 63496 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23212 /* 63498 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23213 /* 63500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23214 /* 63503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23215 /* 63509 */ GIR_RootConstrainSelectedInstOperands,
23216 /* 63510 */ // GIR_Coverage, 1600,
23217 /* 63510 */ GIR_EraseRootFromParent_Done,
23218 /* 63511 */ // Label 1370: @63511
23219 /* 63511 */ GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(63565), // Rule ID 1601 //
23220 /* 63516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23221 /* 63519 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23222 /* 63524 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
23223 /* 63527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
23224 /* 63530 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
23225 /* 63533 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23226 /* 63537 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23227 /* 63541 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23228 /* 63545 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4078:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
23229 /* 63545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i8),
23230 /* 63548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23231 /* 63550 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23232 /* 63552 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23233 /* 63554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23234 /* 63557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23235 /* 63563 */ GIR_RootConstrainSelectedInstOperands,
23236 /* 63564 */ // GIR_Coverage, 1601,
23237 /* 63564 */ GIR_EraseRootFromParent_Done,
23238 /* 63565 */ // Label 1371: @63565
23239 /* 63565 */ GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(63619), // Rule ID 1602 //
23240 /* 63570 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23241 /* 63573 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23242 /* 63578 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23243 /* 63581 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23244 /* 63584 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23245 /* 63587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23246 /* 63591 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23247 /* 63595 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23248 /* 63599 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4078:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
23249 /* 63599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv16i8),
23250 /* 63602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23251 /* 63604 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23252 /* 63606 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23253 /* 63608 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23254 /* 63611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23255 /* 63617 */ GIR_RootConstrainSelectedInstOperands,
23256 /* 63618 */ // GIR_Coverage, 1602,
23257 /* 63618 */ GIR_EraseRootFromParent_Done,
23258 /* 63619 */ // Label 1372: @63619
23259 /* 63619 */ GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(63673), // Rule ID 1603 //
23260 /* 63624 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23261 /* 63627 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23262 /* 63632 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
23263 /* 63635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23264 /* 63638 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23265 /* 63641 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23266 /* 63645 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23267 /* 63649 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23268 /* 63653 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4078:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
23269 /* 63653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv1i64),
23270 /* 63656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23271 /* 63658 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23272 /* 63660 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23273 /* 63662 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23274 /* 63665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23275 /* 63671 */ GIR_RootConstrainSelectedInstOperands,
23276 /* 63672 */ // GIR_Coverage, 1603,
23277 /* 63672 */ GIR_EraseRootFromParent_Done,
23278 /* 63673 */ // Label 1373: @63673
23279 /* 63673 */ GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(63727), // Rule ID 1604 //
23280 /* 63678 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23281 /* 63681 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23282 /* 63686 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23283 /* 63689 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23284 /* 63692 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23285 /* 63695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23286 /* 63699 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23287 /* 63703 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23288 /* 63707 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4078:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
23289 /* 63707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i64),
23290 /* 63710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23291 /* 63712 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23292 /* 63714 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23293 /* 63716 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23294 /* 63719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23295 /* 63725 */ GIR_RootConstrainSelectedInstOperands,
23296 /* 63726 */ // GIR_Coverage, 1604,
23297 /* 63726 */ GIR_EraseRootFromParent_Done,
23298 /* 63727 */ // Label 1374: @63727
23299 /* 63727 */ GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(63781), // Rule ID 1605 //
23300 /* 63732 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23301 /* 63735 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23302 /* 63740 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
23303 /* 63743 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
23304 /* 63746 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
23305 /* 63749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23306 /* 63753 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23307 /* 63757 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23308 /* 63761 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4079:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
23309 /* 63761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i16),
23310 /* 63764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23311 /* 63766 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23312 /* 63768 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23313 /* 63770 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23314 /* 63773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23315 /* 63779 */ GIR_RootConstrainSelectedInstOperands,
23316 /* 63780 */ // GIR_Coverage, 1605,
23317 /* 63780 */ GIR_EraseRootFromParent_Done,
23318 /* 63781 */ // Label 1375: @63781
23319 /* 63781 */ GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(63835), // Rule ID 1606 //
23320 /* 63786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23321 /* 63789 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23322 /* 63794 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
23323 /* 63797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
23324 /* 63800 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
23325 /* 63803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23326 /* 63807 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23327 /* 63811 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23328 /* 63815 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4079:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
23329 /* 63815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i32),
23330 /* 63818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23331 /* 63820 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23332 /* 63822 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23333 /* 63824 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23334 /* 63827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23335 /* 63833 */ GIR_RootConstrainSelectedInstOperands,
23336 /* 63834 */ // GIR_Coverage, 1606,
23337 /* 63834 */ GIR_EraseRootFromParent_Done,
23338 /* 63835 */ // Label 1376: @63835
23339 /* 63835 */ GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(63889), // Rule ID 1607 //
23340 /* 63840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23341 /* 63843 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23342 /* 63848 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23343 /* 63851 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23344 /* 63854 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23345 /* 63857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23346 /* 63861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23347 /* 63865 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23348 /* 63869 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4079:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
23349 /* 63869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i16),
23350 /* 63872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23351 /* 63874 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23352 /* 63876 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23353 /* 63878 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23354 /* 63881 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23355 /* 63887 */ GIR_RootConstrainSelectedInstOperands,
23356 /* 63888 */ // GIR_Coverage, 1607,
23357 /* 63888 */ GIR_EraseRootFromParent_Done,
23358 /* 63889 */ // Label 1377: @63889
23359 /* 63889 */ GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(63943), // Rule ID 1608 //
23360 /* 63894 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23361 /* 63897 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23362 /* 63902 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23363 /* 63905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23364 /* 63908 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23365 /* 63911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23366 /* 63915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23367 /* 63919 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23368 /* 63923 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4079:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
23369 /* 63923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i32),
23370 /* 63926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23371 /* 63928 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23372 /* 63930 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23373 /* 63932 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23374 /* 63935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23375 /* 63941 */ GIR_RootConstrainSelectedInstOperands,
23376 /* 63942 */ // GIR_Coverage, 1608,
23377 /* 63942 */ GIR_EraseRootFromParent_Done,
23378 /* 63943 */ // Label 1378: @63943
23379 /* 63943 */ GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(63997), // Rule ID 1609 //
23380 /* 63948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23381 /* 63951 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23382 /* 63956 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
23383 /* 63959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
23384 /* 63962 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
23385 /* 63965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23386 /* 63969 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23387 /* 63973 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23388 /* 63977 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4079:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
23389 /* 63977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i8),
23390 /* 63980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23391 /* 63982 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23392 /* 63984 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23393 /* 63986 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23394 /* 63989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23395 /* 63995 */ GIR_RootConstrainSelectedInstOperands,
23396 /* 63996 */ // GIR_Coverage, 1609,
23397 /* 63996 */ GIR_EraseRootFromParent_Done,
23398 /* 63997 */ // Label 1379: @63997
23399 /* 63997 */ GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(64051), // Rule ID 1610 //
23400 /* 64002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23401 /* 64005 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23402 /* 64010 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23403 /* 64013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23404 /* 64016 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23405 /* 64019 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23406 /* 64023 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23407 /* 64027 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23408 /* 64031 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4079:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
23409 /* 64031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv16i8),
23410 /* 64034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23411 /* 64036 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23412 /* 64038 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23413 /* 64040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23414 /* 64043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23415 /* 64049 */ GIR_RootConstrainSelectedInstOperands,
23416 /* 64050 */ // GIR_Coverage, 1610,
23417 /* 64050 */ GIR_EraseRootFromParent_Done,
23418 /* 64051 */ // Label 1380: @64051
23419 /* 64051 */ GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(64105), // Rule ID 1611 //
23420 /* 64056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23421 /* 64059 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23422 /* 64064 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
23423 /* 64067 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23424 /* 64070 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23425 /* 64073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23426 /* 64077 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23427 /* 64081 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23428 /* 64085 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4079:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
23429 /* 64085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv1i64),
23430 /* 64088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23431 /* 64090 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23432 /* 64092 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23433 /* 64094 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23434 /* 64097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23435 /* 64103 */ GIR_RootConstrainSelectedInstOperands,
23436 /* 64104 */ // GIR_Coverage, 1611,
23437 /* 64104 */ GIR_EraseRootFromParent_Done,
23438 /* 64105 */ // Label 1381: @64105
23439 /* 64105 */ GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(64159), // Rule ID 1612 //
23440 /* 64110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23441 /* 64113 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23442 /* 64118 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23443 /* 64121 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23444 /* 64124 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23445 /* 64127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23446 /* 64131 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23447 /* 64135 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23448 /* 64139 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4079:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
23449 /* 64139 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i64),
23450 /* 64142 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23451 /* 64144 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23452 /* 64146 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23453 /* 64148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23454 /* 64151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23455 /* 64157 */ GIR_RootConstrainSelectedInstOperands,
23456 /* 64158 */ // GIR_Coverage, 1612,
23457 /* 64158 */ GIR_EraseRootFromParent_Done,
23458 /* 64159 */ // Label 1382: @64159
23459 /* 64159 */ GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(64204), // Rule ID 1901 //
23460 /* 64164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8),
23461 /* 64167 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesd),
23462 /* 64172 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23463 /* 64175 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23464 /* 64178 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23465 /* 64181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23466 /* 64185 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23467 /* 64189 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23468 /* 64193 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3980:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESD:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
23469 /* 64193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESD),
23470 /* 64196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23471 /* 64198 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
23472 /* 64200 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
23473 /* 64202 */ GIR_RootConstrainSelectedInstOperands,
23474 /* 64203 */ // GIR_Coverage, 1901,
23475 /* 64203 */ GIR_EraseRootFromParent_Done,
23476 /* 64204 */ // Label 1383: @64204
23477 /* 64204 */ GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(64249), // Rule ID 1902 //
23478 /* 64209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8),
23479 /* 64212 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aese),
23480 /* 64217 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23481 /* 64220 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23482 /* 64223 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23483 /* 64226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23484 /* 64230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23485 /* 64234 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23486 /* 64238 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3981:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESE:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
23487 /* 64238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESE),
23488 /* 64241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23489 /* 64243 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
23490 /* 64245 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
23491 /* 64247 */ GIR_RootConstrainSelectedInstOperands,
23492 /* 64248 */ // GIR_Coverage, 1902,
23493 /* 64248 */ GIR_EraseRootFromParent_Done,
23494 /* 64249 */ // Label 1384: @64249
23495 /* 64249 */ GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(64294), // Rule ID 1905 //
23496 /* 64254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
23497 /* 64257 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su1),
23498 /* 64262 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23499 /* 64265 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23500 /* 64268 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23501 /* 64271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23502 /* 64275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23503 /* 64279 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23504 /* 64283 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3994:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
23505 /* 64283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU1),
23506 /* 64286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23507 /* 64288 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
23508 /* 64290 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
23509 /* 64292 */ GIR_RootConstrainSelectedInstOperands,
23510 /* 64293 */ // GIR_Coverage, 1905,
23511 /* 64293 */ GIR_EraseRootFromParent_Done,
23512 /* 64294 */ // Label 1385: @64294
23513 /* 64294 */ GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(64339), // Rule ID 1906 //
23514 /* 64299 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
23515 /* 64302 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su0),
23516 /* 64307 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23517 /* 64310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23518 /* 64313 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23519 /* 64316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23520 /* 64320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23521 /* 64324 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23522 /* 64328 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3997:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
23523 /* 64328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU0),
23524 /* 64331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23525 /* 64333 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
23526 /* 64335 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
23527 /* 64337 */ GIR_RootConstrainSelectedInstOperands,
23528 /* 64338 */ // GIR_Coverage, 1906,
23529 /* 64338 */ GIR_EraseRootFromParent_Done,
23530 /* 64339 */ // Label 1386: @64339
23531 /* 64339 */ GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(64393), // Rule ID 1915 //
23532 /* 64344 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
23533 /* 64347 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqrshr),
23534 /* 64352 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23535 /* 64355 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23536 /* 64358 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23537 /* 64361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23538 /* 64365 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23539 /* 64369 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23540 /* 64373 */ // (intrinsic_wo_chain:{ *:[i32] } 3830:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_SQRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
23541 /* 64373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQRSHR),
23542 /* 64376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23543 /* 64378 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
23544 /* 64380 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23545 /* 64382 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23546 /* 64385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23547 /* 64391 */ GIR_RootConstrainSelectedInstOperands,
23548 /* 64392 */ // GIR_Coverage, 1915,
23549 /* 64392 */ GIR_EraseRootFromParent_Done,
23550 /* 64393 */ // Label 1387: @64393
23551 /* 64393 */ GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(64447), // Rule ID 1916 //
23552 /* 64398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
23553 /* 64401 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqrshl),
23554 /* 64406 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23555 /* 64409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23556 /* 64412 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23557 /* 64415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23558 /* 64419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23559 /* 64423 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23560 /* 64427 */ // (intrinsic_wo_chain:{ *:[i32] } 3837:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_UQRSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
23561 /* 64427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQRSHL),
23562 /* 64430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23563 /* 64432 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
23564 /* 64434 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23565 /* 64436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23566 /* 64439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23567 /* 64445 */ GIR_RootConstrainSelectedInstOperands,
23568 /* 64446 */ // GIR_Coverage, 1916,
23569 /* 64446 */ GIR_EraseRootFromParent_Done,
23570 /* 64447 */ // Label 1388: @64447
23571 /* 64447 */ GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(64504), // Rule ID 2039 //
23572 /* 64452 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23573 /* 64455 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16),
23574 /* 64460 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23575 /* 64463 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23576 /* 64466 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23577 /* 64469 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23578 /* 64473 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23579 /* 64477 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23580 /* 64481 */ // (intrinsic_wo_chain:{ *:[i32] } 4175:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (SXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
23581 /* 64481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB16),
23582 /* 64484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23583 /* 64486 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS
23584 /* 64488 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS
23585 /* 64490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23586 /* 64493 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23587 /* 64496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23588 /* 64502 */ GIR_RootConstrainSelectedInstOperands,
23589 /* 64503 */ // GIR_Coverage, 2039,
23590 /* 64503 */ GIR_EraseRootFromParent_Done,
23591 /* 64504 */ // Label 1389: @64504
23592 /* 64504 */ GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(64561), // Rule ID 2046 //
23593 /* 64509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23594 /* 64512 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16),
23595 /* 64517 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23596 /* 64520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23597 /* 64523 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23598 /* 64526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23599 /* 64530 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23600 /* 64534 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23601 /* 64538 */ // (intrinsic_wo_chain:{ *:[i32] } 4200:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (UXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
23602 /* 64538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB16),
23603 /* 64541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23604 /* 64543 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS
23605 /* 64545 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS
23606 /* 64547 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23607 /* 64550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23608 /* 64553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23609 /* 64559 */ GIR_RootConstrainSelectedInstOperands,
23610 /* 64560 */ // GIR_Coverage, 2046,
23611 /* 64560 */ GIR_EraseRootFromParent_Done,
23612 /* 64561 */ // Label 1390: @64561
23613 /* 64561 */ GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(64615), // Rule ID 2093 //
23614 /* 64566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23615 /* 64569 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad),
23616 /* 64574 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23617 /* 64577 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23618 /* 64580 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23619 /* 64583 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23620 /* 64587 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23621 /* 64591 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23622 /* 64595 */ // (intrinsic_wo_chain:{ *:[i32] } 4151:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23623 /* 64595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUAD),
23624 /* 64598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23625 /* 64600 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23626 /* 64602 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23627 /* 64604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23628 /* 64607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23629 /* 64613 */ GIR_RootConstrainSelectedInstOperands,
23630 /* 64614 */ // GIR_Coverage, 2093,
23631 /* 64614 */ GIR_EraseRootFromParent_Done,
23632 /* 64615 */ // Label 1391: @64615
23633 /* 64615 */ GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(64669), // Rule ID 2094 //
23634 /* 64620 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23635 /* 64623 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx),
23636 /* 64628 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23637 /* 64631 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23638 /* 64634 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23639 /* 64637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23640 /* 64641 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23641 /* 64645 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23642 /* 64649 */ // (intrinsic_wo_chain:{ *:[i32] } 4152:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23643 /* 64649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUADX),
23644 /* 64652 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23645 /* 64654 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23646 /* 64656 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23647 /* 64658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23648 /* 64661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23649 /* 64667 */ GIR_RootConstrainSelectedInstOperands,
23650 /* 64668 */ // GIR_Coverage, 2094,
23651 /* 64668 */ GIR_EraseRootFromParent_Done,
23652 /* 64669 */ // Label 1392: @64669
23653 /* 64669 */ GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(64723), // Rule ID 2095 //
23654 /* 64674 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23655 /* 64677 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd),
23656 /* 64682 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23657 /* 64685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23658 /* 64688 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23659 /* 64691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23660 /* 64695 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23661 /* 64699 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23662 /* 64703 */ // (intrinsic_wo_chain:{ *:[i32] } 4159:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23663 /* 64703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSD),
23664 /* 64706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23665 /* 64708 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23666 /* 64710 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23667 /* 64712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23668 /* 64715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23669 /* 64721 */ GIR_RootConstrainSelectedInstOperands,
23670 /* 64722 */ // GIR_Coverage, 2095,
23671 /* 64722 */ GIR_EraseRootFromParent_Done,
23672 /* 64723 */ // Label 1393: @64723
23673 /* 64723 */ GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(64777), // Rule ID 2096 //
23674 /* 64728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23675 /* 64731 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx),
23676 /* 64736 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23677 /* 64739 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23678 /* 64742 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23679 /* 64745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23680 /* 64749 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23681 /* 64753 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23682 /* 64757 */ // (intrinsic_wo_chain:{ *:[i32] } 4160:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23683 /* 64757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSDX),
23684 /* 64760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23685 /* 64762 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23686 /* 64764 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23687 /* 64766 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23688 /* 64769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23689 /* 64775 */ GIR_RootConstrainSelectedInstOperands,
23690 /* 64776 */ // GIR_Coverage, 2096,
23691 /* 64776 */ GIR_EraseRootFromParent_Done,
23692 /* 64777 */ // Label 1394: @64777
23693 /* 64777 */ GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(64831), // Rule ID 2170 //
23694 /* 64782 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23695 /* 64785 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb),
23696 /* 64790 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23697 /* 64793 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23698 /* 64796 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23699 /* 64799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23700 /* 64803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23701 /* 64807 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23702 /* 64811 */ // (intrinsic_wo_chain:{ *:[i32] } 4153:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23703 /* 64811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB),
23704 /* 64814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23705 /* 64816 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23706 /* 64818 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23707 /* 64820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23708 /* 64823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23709 /* 64829 */ GIR_RootConstrainSelectedInstOperands,
23710 /* 64830 */ // GIR_Coverage, 2170,
23711 /* 64830 */ GIR_EraseRootFromParent_Done,
23712 /* 64831 */ // Label 1395: @64831
23713 /* 64831 */ GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(64885), // Rule ID 2171 //
23714 /* 64836 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23715 /* 64839 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt),
23716 /* 64844 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23717 /* 64847 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23718 /* 64850 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23719 /* 64853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23720 /* 64857 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23721 /* 64861 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23722 /* 64865 */ // (intrinsic_wo_chain:{ *:[i32] } 4154:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23723 /* 64865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT),
23724 /* 64868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23725 /* 64870 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23726 /* 64872 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23727 /* 64874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23728 /* 64877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23729 /* 64883 */ GIR_RootConstrainSelectedInstOperands,
23730 /* 64884 */ // GIR_Coverage, 2171,
23731 /* 64884 */ GIR_EraseRootFromParent_Done,
23732 /* 64885 */ // Label 1396: @64885
23733 /* 64885 */ GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(64939), // Rule ID 2172 //
23734 /* 64890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23735 /* 64893 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb),
23736 /* 64898 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23737 /* 64901 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23738 /* 64904 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23739 /* 64907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23740 /* 64911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23741 /* 64915 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23742 /* 64919 */ // (intrinsic_wo_chain:{ *:[i32] } 4155:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23743 /* 64919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB),
23744 /* 64922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23745 /* 64924 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23746 /* 64926 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23747 /* 64928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23748 /* 64931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23749 /* 64937 */ GIR_RootConstrainSelectedInstOperands,
23750 /* 64938 */ // GIR_Coverage, 2172,
23751 /* 64938 */ GIR_EraseRootFromParent_Done,
23752 /* 64939 */ // Label 1397: @64939
23753 /* 64939 */ GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(64993), // Rule ID 2173 //
23754 /* 64944 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23755 /* 64947 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt),
23756 /* 64952 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23757 /* 64955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23758 /* 64958 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23759 /* 64961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23760 /* 64965 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23761 /* 64969 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23762 /* 64973 */ // (intrinsic_wo_chain:{ *:[i32] } 4156:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23763 /* 64973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT),
23764 /* 64976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23765 /* 64978 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23766 /* 64980 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23767 /* 64982 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23768 /* 64985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23769 /* 64991 */ GIR_RootConstrainSelectedInstOperands,
23770 /* 64992 */ // GIR_Coverage, 2173,
23771 /* 64992 */ GIR_EraseRootFromParent_Done,
23772 /* 64993 */ // Label 1398: @64993
23773 /* 64993 */ GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(65047), // Rule ID 2174 //
23774 /* 64998 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23775 /* 65001 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb),
23776 /* 65006 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23777 /* 65009 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23778 /* 65012 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23779 /* 65015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23780 /* 65019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23781 /* 65023 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23782 /* 65027 */ // (intrinsic_wo_chain:{ *:[i32] } 4157:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23783 /* 65027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWB),
23784 /* 65030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23785 /* 65032 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23786 /* 65034 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23787 /* 65036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23788 /* 65039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23789 /* 65045 */ GIR_RootConstrainSelectedInstOperands,
23790 /* 65046 */ // GIR_Coverage, 2174,
23791 /* 65046 */ GIR_EraseRootFromParent_Done,
23792 /* 65047 */ // Label 1399: @65047
23793 /* 65047 */ GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(65101), // Rule ID 2175 //
23794 /* 65052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23795 /* 65055 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt),
23796 /* 65060 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23797 /* 65063 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23798 /* 65066 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23799 /* 65069 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23800 /* 65073 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23801 /* 65077 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23802 /* 65081 */ // (intrinsic_wo_chain:{ *:[i32] } 4158:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23803 /* 65081 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWT),
23804 /* 65084 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23805 /* 65086 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23806 /* 65088 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23807 /* 65090 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23808 /* 65093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23809 /* 65099 */ GIR_RootConstrainSelectedInstOperands,
23810 /* 65100 */ // GIR_Coverage, 2175,
23811 /* 65100 */ GIR_EraseRootFromParent_Done,
23812 /* 65101 */ // Label 1400: @65101
23813 /* 65101 */ GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(65158), // Rule ID 2286 //
23814 /* 65106 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23815 /* 65109 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16),
23816 /* 65114 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23817 /* 65117 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23818 /* 65120 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23819 /* 65123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23820 /* 65127 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23821 /* 65131 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23822 /* 65135 */ // (intrinsic_wo_chain:{ *:[i32] } 4175:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
23823 /* 65135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB16),
23824 /* 65138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23825 /* 65140 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23826 /* 65142 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23827 /* 65144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23828 /* 65147 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23829 /* 65150 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23830 /* 65156 */ GIR_RootConstrainSelectedInstOperands,
23831 /* 65157 */ // GIR_Coverage, 2286,
23832 /* 65157 */ GIR_EraseRootFromParent_Done,
23833 /* 65158 */ // Label 1401: @65158
23834 /* 65158 */ GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(65212), // Rule ID 2316 //
23835 /* 65163 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23836 /* 65166 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
23837 /* 65171 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23838 /* 65174 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23839 /* 65177 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23840 /* 65180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23841 /* 65184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23842 /* 65188 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23843 /* 65192 */ // (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
23844 /* 65192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD),
23845 /* 65195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23846 /* 65197 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
23847 /* 65199 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
23848 /* 65201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23849 /* 65204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23850 /* 65210 */ GIR_RootConstrainSelectedInstOperands,
23851 /* 65211 */ // GIR_Coverage, 2316,
23852 /* 65211 */ GIR_EraseRootFromParent_Done,
23853 /* 65212 */ // Label 1402: @65212
23854 /* 65212 */ GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(65266), // Rule ID 2317 //
23855 /* 65217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23856 /* 65220 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
23857 /* 65225 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23858 /* 65228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23859 /* 65231 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23860 /* 65234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23861 /* 65238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23862 /* 65242 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23863 /* 65246 */ // (intrinsic_wo_chain:{ *:[i32] } 4123:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
23864 /* 65246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB),
23865 /* 65249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23866 /* 65251 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
23867 /* 65253 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
23868 /* 65255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23869 /* 65258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23870 /* 65264 */ GIR_RootConstrainSelectedInstOperands,
23871 /* 65265 */ // GIR_Coverage, 2317,
23872 /* 65265 */ GIR_EraseRootFromParent_Done,
23873 /* 65266 */ // Label 1403: @65266
23874 /* 65266 */ GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(65320), // Rule ID 2357 //
23875 /* 65271 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23876 /* 65274 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb),
23877 /* 65279 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23878 /* 65282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23879 /* 65285 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23880 /* 65288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23881 /* 65292 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23882 /* 65296 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23883 /* 65300 */ // (intrinsic_wo_chain:{ *:[i32] } 4153:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23884 /* 65300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB),
23885 /* 65303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23886 /* 65305 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23887 /* 65307 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23888 /* 65309 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23889 /* 65312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23890 /* 65318 */ GIR_RootConstrainSelectedInstOperands,
23891 /* 65319 */ // GIR_Coverage, 2357,
23892 /* 65319 */ GIR_EraseRootFromParent_Done,
23893 /* 65320 */ // Label 1404: @65320
23894 /* 65320 */ GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(65374), // Rule ID 2358 //
23895 /* 65325 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23896 /* 65328 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt),
23897 /* 65333 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23898 /* 65336 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23899 /* 65339 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23900 /* 65342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23901 /* 65346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23902 /* 65350 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23903 /* 65354 */ // (intrinsic_wo_chain:{ *:[i32] } 4154:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23904 /* 65354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT),
23905 /* 65357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23906 /* 65359 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23907 /* 65361 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23908 /* 65363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23909 /* 65366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23910 /* 65372 */ GIR_RootConstrainSelectedInstOperands,
23911 /* 65373 */ // GIR_Coverage, 2358,
23912 /* 65373 */ GIR_EraseRootFromParent_Done,
23913 /* 65374 */ // Label 1405: @65374
23914 /* 65374 */ GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(65428), // Rule ID 2359 //
23915 /* 65379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23916 /* 65382 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb),
23917 /* 65387 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23918 /* 65390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23919 /* 65393 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23920 /* 65396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23921 /* 65400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23922 /* 65404 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23923 /* 65408 */ // (intrinsic_wo_chain:{ *:[i32] } 4155:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23924 /* 65408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB),
23925 /* 65411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23926 /* 65413 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23927 /* 65415 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23928 /* 65417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23929 /* 65420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23930 /* 65426 */ GIR_RootConstrainSelectedInstOperands,
23931 /* 65427 */ // GIR_Coverage, 2359,
23932 /* 65427 */ GIR_EraseRootFromParent_Done,
23933 /* 65428 */ // Label 1406: @65428
23934 /* 65428 */ GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(65482), // Rule ID 2360 //
23935 /* 65433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23936 /* 65436 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt),
23937 /* 65441 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23938 /* 65444 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23939 /* 65447 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23940 /* 65450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23941 /* 65454 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23942 /* 65458 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23943 /* 65462 */ // (intrinsic_wo_chain:{ *:[i32] } 4156:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23944 /* 65462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT),
23945 /* 65465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23946 /* 65467 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23947 /* 65469 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23948 /* 65471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23949 /* 65474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23950 /* 65480 */ GIR_RootConstrainSelectedInstOperands,
23951 /* 65481 */ // GIR_Coverage, 2360,
23952 /* 65481 */ GIR_EraseRootFromParent_Done,
23953 /* 65482 */ // Label 1407: @65482
23954 /* 65482 */ GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(65536), // Rule ID 2361 //
23955 /* 65487 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23956 /* 65490 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb),
23957 /* 65495 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23958 /* 65498 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23959 /* 65501 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23960 /* 65504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23961 /* 65508 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23962 /* 65512 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23963 /* 65516 */ // (intrinsic_wo_chain:{ *:[i32] } 4157:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23964 /* 65516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWB),
23965 /* 65519 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23966 /* 65521 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23967 /* 65523 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23968 /* 65525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23969 /* 65528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23970 /* 65534 */ GIR_RootConstrainSelectedInstOperands,
23971 /* 65535 */ // GIR_Coverage, 2361,
23972 /* 65535 */ GIR_EraseRootFromParent_Done,
23973 /* 65536 */ // Label 1408: @65536
23974 /* 65536 */ GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(65590), // Rule ID 2362 //
23975 /* 65541 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23976 /* 65544 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt),
23977 /* 65549 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23978 /* 65552 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23979 /* 65555 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23980 /* 65558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23981 /* 65562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23982 /* 65566 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23983 /* 65570 */ // (intrinsic_wo_chain:{ *:[i32] } 4158:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23984 /* 65570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWT),
23985 /* 65573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23986 /* 65575 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23987 /* 65577 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23988 /* 65579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23989 /* 65582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23990 /* 65588 */ GIR_RootConstrainSelectedInstOperands,
23991 /* 65589 */ // GIR_Coverage, 2362,
23992 /* 65589 */ GIR_EraseRootFromParent_Done,
23993 /* 65590 */ // Label 1409: @65590
23994 /* 65590 */ GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(65638), // Rule ID 2888 //
23995 /* 65595 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a),
23996 /* 65598 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
23997 /* 65603 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
23998 /* 65606 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
23999 /* 65609 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
24000 /* 65612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24001 /* 65616 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24002 /* 65620 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24003 /* 65624 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4011:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 0:{ *:[i32] })
24004 /* 65624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16),
24005 /* 65627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24006 /* 65629 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24007 /* 65631 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24008 /* 65633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24009 /* 65636 */ GIR_RootConstrainSelectedInstOperands,
24010 /* 65637 */ // GIR_Coverage, 2888,
24011 /* 65637 */ GIR_EraseRootFromParent_Done,
24012 /* 65638 */ // Label 1410: @65638
24013 /* 65638 */ GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(65686), // Rule ID 2889 //
24014 /* 65643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a),
24015 /* 65646 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
24016 /* 65651 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
24017 /* 65654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
24018 /* 65657 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
24019 /* 65660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24020 /* 65664 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24021 /* 65668 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24022 /* 65672 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4010:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 1:{ *:[i32] })
24023 /* 65672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16),
24024 /* 65675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24025 /* 65677 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24026 /* 65679 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24027 /* 65681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
24028 /* 65684 */ GIR_RootConstrainSelectedInstOperands,
24029 /* 65685 */ // GIR_Coverage, 2889,
24030 /* 65685 */ GIR_EraseRootFromParent_Done,
24031 /* 65686 */ // Label 1411: @65686
24032 /* 65686 */ GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(65734), // Rule ID 2890 //
24033 /* 65691 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a),
24034 /* 65694 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
24035 /* 65699 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24036 /* 65702 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24037 /* 65705 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24038 /* 65708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24039 /* 65712 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24040 /* 65716 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24041 /* 65720 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4011:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 0:{ *:[i32] })
24042 /* 65720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16),
24043 /* 65723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24044 /* 65725 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24045 /* 65727 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24046 /* 65729 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24047 /* 65732 */ GIR_RootConstrainSelectedInstOperands,
24048 /* 65733 */ // GIR_Coverage, 2890,
24049 /* 65733 */ GIR_EraseRootFromParent_Done,
24050 /* 65734 */ // Label 1412: @65734
24051 /* 65734 */ GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(65782), // Rule ID 2891 //
24052 /* 65739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a),
24053 /* 65742 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
24054 /* 65747 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24055 /* 65750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24056 /* 65753 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24057 /* 65756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24058 /* 65760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24059 /* 65764 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24060 /* 65768 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4010:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 1:{ *:[i32] })
24061 /* 65768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16),
24062 /* 65771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24063 /* 65773 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24064 /* 65775 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24065 /* 65777 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
24066 /* 65780 */ GIR_RootConstrainSelectedInstOperands,
24067 /* 65781 */ // GIR_Coverage, 2891,
24068 /* 65781 */ GIR_EraseRootFromParent_Done,
24069 /* 65782 */ // Label 1413: @65782
24070 /* 65782 */ GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(65830), // Rule ID 2892 //
24071 /* 65787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a),
24072 /* 65790 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
24073 /* 65795 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
24074 /* 65798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
24075 /* 65801 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
24076 /* 65804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24077 /* 65808 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24078 /* 65812 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24079 /* 65816 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4011:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 0:{ *:[i32] })
24080 /* 65816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32),
24081 /* 65819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24082 /* 65821 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24083 /* 65823 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24084 /* 65825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24085 /* 65828 */ GIR_RootConstrainSelectedInstOperands,
24086 /* 65829 */ // GIR_Coverage, 2892,
24087 /* 65829 */ GIR_EraseRootFromParent_Done,
24088 /* 65830 */ // Label 1414: @65830
24089 /* 65830 */ GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(65878), // Rule ID 2893 //
24090 /* 65835 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a),
24091 /* 65838 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
24092 /* 65843 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
24093 /* 65846 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
24094 /* 65849 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
24095 /* 65852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24096 /* 65856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24097 /* 65860 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24098 /* 65864 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4010:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 1:{ *:[i32] })
24099 /* 65864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32),
24100 /* 65867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24101 /* 65869 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24102 /* 65871 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24103 /* 65873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
24104 /* 65876 */ GIR_RootConstrainSelectedInstOperands,
24105 /* 65877 */ // GIR_Coverage, 2893,
24106 /* 65877 */ GIR_EraseRootFromParent_Done,
24107 /* 65878 */ // Label 1415: @65878
24108 /* 65878 */ GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(65926), // Rule ID 2894 //
24109 /* 65883 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a),
24110 /* 65886 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
24111 /* 65891 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24112 /* 65894 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24113 /* 65897 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24114 /* 65900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24115 /* 65904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24116 /* 65908 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24117 /* 65912 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4011:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 0:{ *:[i32] })
24118 /* 65912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32),
24119 /* 65915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24120 /* 65917 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24121 /* 65919 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24122 /* 65921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24123 /* 65924 */ GIR_RootConstrainSelectedInstOperands,
24124 /* 65925 */ // GIR_Coverage, 2894,
24125 /* 65925 */ GIR_EraseRootFromParent_Done,
24126 /* 65926 */ // Label 1416: @65926
24127 /* 65926 */ GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(65974), // Rule ID 2895 //
24128 /* 65931 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a),
24129 /* 65934 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
24130 /* 65939 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24131 /* 65942 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24132 /* 65945 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24133 /* 65948 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24134 /* 65952 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24135 /* 65956 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24136 /* 65960 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4010:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 1:{ *:[i32] })
24137 /* 65960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32),
24138 /* 65963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24139 /* 65965 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24140 /* 65967 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24141 /* 65969 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
24142 /* 65972 */ GIR_RootConstrainSelectedInstOperands,
24143 /* 65973 */ // GIR_Coverage, 2895,
24144 /* 65973 */ GIR_EraseRootFromParent_Done,
24145 /* 65974 */ // Label 1417: @65974
24146 /* 65974 */ GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(66049), // Rule ID 3406 //
24147 /* 65979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24148 /* 65982 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm),
24149 /* 65987 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24150 /* 65990 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24151 /* 65993 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24152 /* 65996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24153 /* 66000 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24154 /* 66004 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24155 /* 66008 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3898:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
24156 /* 66008 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24157 /* 66011 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24158 /* 66015 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24159 /* 66020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32),
24160 /* 66023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24161 /* 66025 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24162 /* 66027 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24163 /* 66029 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24164 /* 66032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24165 /* 66038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24166 /* 66044 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24167 /* 66047 */ GIR_RootConstrainSelectedInstOperands,
24168 /* 66048 */ // GIR_Coverage, 3406,
24169 /* 66048 */ GIR_EraseRootFromParent_Done,
24170 /* 66049 */ // Label 1418: @66049
24171 /* 66049 */ GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(66154), // Rule ID 3482 //
24172 /* 66054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24173 /* 66057 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv),
24174 /* 66062 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24175 /* 66065 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24176 /* 66068 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24177 /* 66071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24178 /* 66075 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24179 /* 66079 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24180 /* 66083 */ // (intrinsic_wo_chain:{ *:[f32] } 3806:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
24181 /* 66083 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24182 /* 66086 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24183 /* 66090 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24184 /* 66095 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24185 /* 66099 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24186 /* 66104 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24187 /* 66107 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf32),
24188 /* 66111 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24189 /* 66116 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24190 /* 66119 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24191 /* 66123 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24192 /* 66126 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24193 /* 66132 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24194 /* 66138 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24195 /* 66140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24196 /* 66143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24197 /* 66145 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24198 /* 66148 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
24199 /* 66153 */ // GIR_Coverage, 3482,
24200 /* 66153 */ GIR_EraseRootFromParent_Done,
24201 /* 66154 */ // Label 1419: @66154
24202 /* 66154 */ GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(66259), // Rule ID 3484 //
24203 /* 66159 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24204 /* 66162 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv),
24205 /* 66167 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
24206 /* 66170 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
24207 /* 66173 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24208 /* 66176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24209 /* 66180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24210 /* 66184 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24211 /* 66188 */ // (intrinsic_wo_chain:{ *:[f16] } 3806:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
24212 /* 66188 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24213 /* 66191 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24214 /* 66195 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24215 /* 66200 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24216 /* 66204 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24217 /* 66209 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24218 /* 66212 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf16),
24219 /* 66216 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24220 /* 66221 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24221 /* 66224 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24222 /* 66228 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24223 /* 66231 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24224 /* 66237 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24225 /* 66243 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24226 /* 66245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24227 /* 66248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24228 /* 66250 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24229 /* 66253 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
24230 /* 66258 */ // GIR_Coverage, 3484,
24231 /* 66258 */ GIR_EraseRootFromParent_Done,
24232 /* 66259 */ // Label 1420: @66259
24233 /* 66259 */ GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(66364), // Rule ID 3486 //
24234 /* 66264 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24235 /* 66267 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv),
24236 /* 66272 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24237 /* 66275 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24238 /* 66278 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24239 /* 66281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24240 /* 66285 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24241 /* 66289 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24242 /* 66293 */ // (intrinsic_wo_chain:{ *:[f32] } 3797:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
24243 /* 66293 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24244 /* 66296 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24245 /* 66300 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24246 /* 66305 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24247 /* 66309 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24248 /* 66314 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24249 /* 66317 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf32),
24250 /* 66321 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24251 /* 66326 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24252 /* 66329 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24253 /* 66333 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24254 /* 66336 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24255 /* 66342 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24256 /* 66348 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24257 /* 66350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24258 /* 66353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24259 /* 66355 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24260 /* 66358 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
24261 /* 66363 */ // GIR_Coverage, 3486,
24262 /* 66363 */ GIR_EraseRootFromParent_Done,
24263 /* 66364 */ // Label 1421: @66364
24264 /* 66364 */ GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(66469), // Rule ID 3488 //
24265 /* 66369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24266 /* 66372 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv),
24267 /* 66377 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
24268 /* 66380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
24269 /* 66383 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24270 /* 66386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24271 /* 66390 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24272 /* 66394 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24273 /* 66398 */ // (intrinsic_wo_chain:{ *:[f16] } 3797:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
24274 /* 66398 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24275 /* 66401 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24276 /* 66405 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24277 /* 66410 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24278 /* 66414 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24279 /* 66419 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24280 /* 66422 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf16),
24281 /* 66426 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24282 /* 66431 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24283 /* 66434 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24284 /* 66438 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24285 /* 66441 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24286 /* 66447 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24287 /* 66453 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24288 /* 66455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24289 /* 66458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24290 /* 66460 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24291 /* 66463 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
24292 /* 66468 */ // GIR_Coverage, 3488,
24293 /* 66468 */ GIR_EraseRootFromParent_Done,
24294 /* 66469 */ // Label 1422: @66469
24295 /* 66469 */ GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(66574), // Rule ID 3490 //
24296 /* 66474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24297 /* 66477 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav),
24298 /* 66482 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24299 /* 66485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24300 /* 66488 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24301 /* 66491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24302 /* 66495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24303 /* 66499 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24304 /* 66503 */ // (intrinsic_wo_chain:{ *:[f32] } 3804:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
24305 /* 66503 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24306 /* 66506 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24307 /* 66510 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24308 /* 66515 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24309 /* 66519 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24310 /* 66524 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24311 /* 66527 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf32),
24312 /* 66531 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24313 /* 66536 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24314 /* 66539 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24315 /* 66543 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24316 /* 66546 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24317 /* 66552 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24318 /* 66558 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24319 /* 66560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24320 /* 66563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24321 /* 66565 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24322 /* 66568 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
24323 /* 66573 */ // GIR_Coverage, 3490,
24324 /* 66573 */ GIR_EraseRootFromParent_Done,
24325 /* 66574 */ // Label 1423: @66574
24326 /* 66574 */ GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(66679), // Rule ID 3492 //
24327 /* 66579 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24328 /* 66582 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav),
24329 /* 66587 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
24330 /* 66590 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
24331 /* 66593 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24332 /* 66596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24333 /* 66600 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24334 /* 66604 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24335 /* 66608 */ // (intrinsic_wo_chain:{ *:[f16] } 3804:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
24336 /* 66608 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24337 /* 66611 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24338 /* 66615 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24339 /* 66620 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24340 /* 66624 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24341 /* 66629 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24342 /* 66632 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf16),
24343 /* 66636 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24344 /* 66641 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24345 /* 66644 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24346 /* 66648 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24347 /* 66651 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24348 /* 66657 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24349 /* 66663 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24350 /* 66665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24351 /* 66668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24352 /* 66670 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24353 /* 66673 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
24354 /* 66678 */ // GIR_Coverage, 3492,
24355 /* 66678 */ GIR_EraseRootFromParent_Done,
24356 /* 66679 */ // Label 1424: @66679
24357 /* 66679 */ GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(66784), // Rule ID 3494 //
24358 /* 66684 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24359 /* 66687 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav),
24360 /* 66692 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24361 /* 66695 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24362 /* 66698 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24363 /* 66701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24364 /* 66705 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24365 /* 66709 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24366 /* 66713 */ // (intrinsic_wo_chain:{ *:[f32] } 3795:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
24367 /* 66713 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24368 /* 66716 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24369 /* 66720 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24370 /* 66725 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24371 /* 66729 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24372 /* 66734 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24373 /* 66737 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf32),
24374 /* 66741 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24375 /* 66746 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24376 /* 66749 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24377 /* 66753 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24378 /* 66756 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24379 /* 66762 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24380 /* 66768 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24381 /* 66770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24382 /* 66773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24383 /* 66775 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24384 /* 66778 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
24385 /* 66783 */ // GIR_Coverage, 3494,
24386 /* 66783 */ GIR_EraseRootFromParent_Done,
24387 /* 66784 */ // Label 1425: @66784
24388 /* 66784 */ GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(66889), // Rule ID 3496 //
24389 /* 66789 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24390 /* 66792 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav),
24391 /* 66797 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
24392 /* 66800 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
24393 /* 66803 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24394 /* 66806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24395 /* 66810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24396 /* 66814 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24397 /* 66818 */ // (intrinsic_wo_chain:{ *:[f16] } 3795:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
24398 /* 66818 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24399 /* 66821 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24400 /* 66825 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24401 /* 66830 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24402 /* 66834 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24403 /* 66839 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24404 /* 66842 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf16),
24405 /* 66846 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24406 /* 66851 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24407 /* 66854 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24408 /* 66858 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24409 /* 66861 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24410 /* 66867 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24411 /* 66873 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24412 /* 66875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24413 /* 66878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24414 /* 66880 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24415 /* 66883 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
24416 /* 66888 */ // GIR_Coverage, 3496,
24417 /* 66888 */ GIR_EraseRootFromParent_Done,
24418 /* 66889 */ // Label 1426: @66889
24419 /* 66889 */ GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(66949), // Rule ID 3546 //
24420 /* 66894 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24421 /* 66897 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav),
24422 /* 66902 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24423 /* 66905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24424 /* 66908 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24425 /* 66911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24426 /* 66915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24427 /* 66919 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24428 /* 66923 */ // (intrinsic_wo_chain:{ *:[i32] } 3802:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMINAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
24429 /* 66923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs8),
24430 /* 66926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
24431 /* 66928 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
24432 /* 66930 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
24433 /* 66932 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24434 /* 66935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24435 /* 66941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24436 /* 66947 */ GIR_RootConstrainSelectedInstOperands,
24437 /* 66948 */ // GIR_Coverage, 3546,
24438 /* 66948 */ GIR_EraseRootFromParent_Done,
24439 /* 66949 */ // Label 1427: @66949
24440 /* 66949 */ GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(67009), // Rule ID 3548 //
24441 /* 66954 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24442 /* 66957 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav),
24443 /* 66962 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24444 /* 66965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24445 /* 66968 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24446 /* 66971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24447 /* 66975 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24448 /* 66979 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24449 /* 66983 */ // (intrinsic_wo_chain:{ *:[i32] } 3802:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMINAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
24450 /* 66983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs16),
24451 /* 66986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
24452 /* 66988 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
24453 /* 66990 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
24454 /* 66992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24455 /* 66995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24456 /* 67001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24457 /* 67007 */ GIR_RootConstrainSelectedInstOperands,
24458 /* 67008 */ // GIR_Coverage, 3548,
24459 /* 67008 */ GIR_EraseRootFromParent_Done,
24460 /* 67009 */ // Label 1428: @67009
24461 /* 67009 */ GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(67069), // Rule ID 3550 //
24462 /* 67014 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24463 /* 67017 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav),
24464 /* 67022 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24465 /* 67025 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24466 /* 67028 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24467 /* 67031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24468 /* 67035 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24469 /* 67039 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24470 /* 67043 */ // (intrinsic_wo_chain:{ *:[i32] } 3802:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMINAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
24471 /* 67043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs32),
24472 /* 67046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
24473 /* 67048 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
24474 /* 67050 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
24475 /* 67052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24476 /* 67055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24477 /* 67061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24478 /* 67067 */ GIR_RootConstrainSelectedInstOperands,
24479 /* 67068 */ // GIR_Coverage, 3550,
24480 /* 67068 */ GIR_EraseRootFromParent_Done,
24481 /* 67069 */ // Label 1429: @67069
24482 /* 67069 */ GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(67129), // Rule ID 3552 //
24483 /* 67074 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24484 /* 67077 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav),
24485 /* 67082 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24486 /* 67085 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24487 /* 67088 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24488 /* 67091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24489 /* 67095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24490 /* 67099 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24491 /* 67103 */ // (intrinsic_wo_chain:{ *:[i32] } 3793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMAXAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
24492 /* 67103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs8),
24493 /* 67106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
24494 /* 67108 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
24495 /* 67110 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
24496 /* 67112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24497 /* 67115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24498 /* 67121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24499 /* 67127 */ GIR_RootConstrainSelectedInstOperands,
24500 /* 67128 */ // GIR_Coverage, 3552,
24501 /* 67128 */ GIR_EraseRootFromParent_Done,
24502 /* 67129 */ // Label 1430: @67129
24503 /* 67129 */ GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(67189), // Rule ID 3554 //
24504 /* 67134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24505 /* 67137 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav),
24506 /* 67142 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24507 /* 67145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24508 /* 67148 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24509 /* 67151 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24510 /* 67155 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24511 /* 67159 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24512 /* 67163 */ // (intrinsic_wo_chain:{ *:[i32] } 3793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMAXAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
24513 /* 67163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs16),
24514 /* 67166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
24515 /* 67168 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
24516 /* 67170 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
24517 /* 67172 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24518 /* 67175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24519 /* 67181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24520 /* 67187 */ GIR_RootConstrainSelectedInstOperands,
24521 /* 67188 */ // GIR_Coverage, 3554,
24522 /* 67188 */ GIR_EraseRootFromParent_Done,
24523 /* 67189 */ // Label 1431: @67189
24524 /* 67189 */ GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(67249), // Rule ID 3556 //
24525 /* 67194 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24526 /* 67197 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav),
24527 /* 67202 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24528 /* 67205 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24529 /* 67208 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24530 /* 67211 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24531 /* 67215 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24532 /* 67219 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24533 /* 67223 */ // (intrinsic_wo_chain:{ *:[i32] } 3793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMAXAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
24534 /* 67223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs32),
24535 /* 67226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
24536 /* 67228 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
24537 /* 67230 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
24538 /* 67232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24539 /* 67235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24540 /* 67241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24541 /* 67247 */ GIR_RootConstrainSelectedInstOperands,
24542 /* 67248 */ // GIR_Coverage, 3556,
24543 /* 67248 */ GIR_EraseRootFromParent_Done,
24544 /* 67249 */ // Label 1432: @67249
24545 /* 67249 */ GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(67324), // Rule ID 3663 //
24546 /* 67254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24547 /* 67257 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm),
24548 /* 67262 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24549 /* 67265 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24550 /* 67268 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24551 /* 67271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24552 /* 67275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24553 /* 67279 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24554 /* 67283 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3898:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
24555 /* 67283 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24556 /* 67286 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24557 /* 67290 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24558 /* 67295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16),
24559 /* 67298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24560 /* 67300 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24561 /* 67302 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24562 /* 67304 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24563 /* 67307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24564 /* 67313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24565 /* 67319 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24566 /* 67322 */ GIR_RootConstrainSelectedInstOperands,
24567 /* 67323 */ // GIR_Coverage, 3663,
24568 /* 67323 */ GIR_EraseRootFromParent_Done,
24569 /* 67324 */ // Label 1433: @67324
24570 /* 67324 */ GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(67399), // Rule ID 3668 //
24571 /* 67329 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24572 /* 67332 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm),
24573 /* 67337 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24574 /* 67340 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24575 /* 67343 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24576 /* 67346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24577 /* 67350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24578 /* 67354 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24579 /* 67358 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3901:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
24580 /* 67358 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24581 /* 67361 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24582 /* 67365 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24583 /* 67370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32),
24584 /* 67373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24585 /* 67375 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24586 /* 67377 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24587 /* 67379 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24588 /* 67382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24589 /* 67388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24590 /* 67394 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24591 /* 67397 */ GIR_RootConstrainSelectedInstOperands,
24592 /* 67398 */ // GIR_Coverage, 3668,
24593 /* 67398 */ GIR_EraseRootFromParent_Done,
24594 /* 67399 */ // Label 1434: @67399
24595 /* 67399 */ GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(67474), // Rule ID 3673 //
24596 /* 67404 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24597 /* 67407 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm),
24598 /* 67412 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24599 /* 67415 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24600 /* 67418 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24601 /* 67421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24602 /* 67425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24603 /* 67429 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24604 /* 67433 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3901:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
24605 /* 67433 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24606 /* 67436 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24607 /* 67440 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24608 /* 67445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16),
24609 /* 67448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24610 /* 67450 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24611 /* 67452 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24612 /* 67454 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24613 /* 67457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24614 /* 67463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24615 /* 67469 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24616 /* 67472 */ GIR_RootConstrainSelectedInstOperands,
24617 /* 67473 */ // GIR_Coverage, 3673,
24618 /* 67473 */ GIR_EraseRootFromParent_Done,
24619 /* 67474 */ // Label 1435: @67474
24620 /* 67474 */ GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(67549), // Rule ID 3853 //
24621 /* 67479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24622 /* 67482 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh),
24623 /* 67487 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
24624 /* 67490 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24625 /* 67493 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24626 /* 67496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24627 /* 67500 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24628 /* 67504 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24629 /* 67508 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3921:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24630 /* 67508 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24631 /* 67511 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24632 /* 67515 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24633 /* 67520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi8),
24634 /* 67523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24635 /* 67525 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24636 /* 67527 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24637 /* 67529 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24638 /* 67532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24639 /* 67538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24640 /* 67544 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24641 /* 67547 */ GIR_RootConstrainSelectedInstOperands,
24642 /* 67548 */ // GIR_Coverage, 3853,
24643 /* 67548 */ GIR_EraseRootFromParent_Done,
24644 /* 67549 */ // Label 1436: @67549
24645 /* 67549 */ GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(67624), // Rule ID 3860 //
24646 /* 67554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24647 /* 67557 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh),
24648 /* 67562 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24649 /* 67565 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24650 /* 67568 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24651 /* 67571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24652 /* 67575 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24653 /* 67579 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24654 /* 67583 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3921:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24655 /* 67583 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24656 /* 67586 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24657 /* 67590 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24658 /* 67595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi16),
24659 /* 67598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24660 /* 67600 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24661 /* 67602 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24662 /* 67604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24663 /* 67607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24664 /* 67613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24665 /* 67619 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24666 /* 67622 */ GIR_RootConstrainSelectedInstOperands,
24667 /* 67623 */ // GIR_Coverage, 3860,
24668 /* 67623 */ GIR_EraseRootFromParent_Done,
24669 /* 67624 */ // Label 1437: @67624
24670 /* 67624 */ GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(67699), // Rule ID 3864 //
24671 /* 67629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24672 /* 67632 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh),
24673 /* 67637 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24674 /* 67640 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24675 /* 67643 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24676 /* 67646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24677 /* 67650 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24678 /* 67654 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24679 /* 67658 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3921:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24680 /* 67658 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24681 /* 67661 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24682 /* 67665 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24683 /* 67670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi32),
24684 /* 67673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24685 /* 67675 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24686 /* 67677 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24687 /* 67679 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24688 /* 67682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24689 /* 67688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24690 /* 67694 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24691 /* 67697 */ GIR_RootConstrainSelectedInstOperands,
24692 /* 67698 */ // GIR_Coverage, 3864,
24693 /* 67698 */ GIR_EraseRootFromParent_Done,
24694 /* 67699 */ // Label 1438: @67699
24695 /* 67699 */ GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(67774), // Rule ID 3866 //
24696 /* 67704 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24697 /* 67707 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh),
24698 /* 67712 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
24699 /* 67715 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24700 /* 67718 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24701 /* 67721 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24702 /* 67725 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24703 /* 67729 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24704 /* 67733 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3930:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQRDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24705 /* 67733 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24706 /* 67736 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24707 /* 67740 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24708 /* 67745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi8),
24709 /* 67748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24710 /* 67750 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24711 /* 67752 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24712 /* 67754 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24713 /* 67757 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24714 /* 67763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24715 /* 67769 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24716 /* 67772 */ GIR_RootConstrainSelectedInstOperands,
24717 /* 67773 */ // GIR_Coverage, 3866,
24718 /* 67773 */ GIR_EraseRootFromParent_Done,
24719 /* 67774 */ // Label 1439: @67774
24720 /* 67774 */ GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(67849), // Rule ID 3868 //
24721 /* 67779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24722 /* 67782 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh),
24723 /* 67787 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24724 /* 67790 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24725 /* 67793 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24726 /* 67796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24727 /* 67800 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24728 /* 67804 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24729 /* 67808 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3930:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQRDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24730 /* 67808 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24731 /* 67811 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24732 /* 67815 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24733 /* 67820 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi16),
24734 /* 67823 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24735 /* 67825 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24736 /* 67827 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24737 /* 67829 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24738 /* 67832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24739 /* 67838 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24740 /* 67844 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24741 /* 67847 */ GIR_RootConstrainSelectedInstOperands,
24742 /* 67848 */ // GIR_Coverage, 3868,
24743 /* 67848 */ GIR_EraseRootFromParent_Done,
24744 /* 67849 */ // Label 1440: @67849
24745 /* 67849 */ GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(67924), // Rule ID 3870 //
24746 /* 67854 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24747 /* 67857 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh),
24748 /* 67862 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24749 /* 67865 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24750 /* 67868 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24751 /* 67871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24752 /* 67875 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24753 /* 67879 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24754 /* 67883 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3930:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQRDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24755 /* 67883 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24756 /* 67886 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24757 /* 67890 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24758 /* 67895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi32),
24759 /* 67898 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24760 /* 67900 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24761 /* 67902 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24762 /* 67904 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24763 /* 67907 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24764 /* 67913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24765 /* 67919 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24766 /* 67922 */ GIR_RootConstrainSelectedInstOperands,
24767 /* 67923 */ // GIR_Coverage, 3870,
24768 /* 67923 */ GIR_EraseRootFromParent_Done,
24769 /* 67924 */ // Label 1441: @67924
24770 /* 67924 */ GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(67999), // Rule ID 4396 //
24771 /* 67929 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24772 /* 67932 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmul),
24773 /* 67937 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24774 /* 67940 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24775 /* 67943 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24776 /* 67946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24777 /* 67950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24778 /* 67954 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24779 /* 67958 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3911:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
24780 /* 67958 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24781 /* 67961 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24782 /* 67965 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24783 /* 67970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32),
24784 /* 67973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24785 /* 67975 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24786 /* 67977 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24787 /* 67979 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24788 /* 67982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24789 /* 67988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24790 /* 67994 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24791 /* 67997 */ GIR_RootConstrainSelectedInstOperands,
24792 /* 67998 */ // GIR_Coverage, 4396,
24793 /* 67998 */ GIR_EraseRootFromParent_Done,
24794 /* 67999 */ // Label 1442: @67999
24795 /* 67999 */ GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(68074), // Rule ID 4403 //
24796 /* 68004 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24797 /* 68007 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmul),
24798 /* 68012 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24799 /* 68015 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24800 /* 68018 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24801 /* 68021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24802 /* 68025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24803 /* 68029 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24804 /* 68033 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3911:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
24805 /* 68033 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24806 /* 68036 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24807 /* 68040 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24808 /* 68045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16),
24809 /* 68048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24810 /* 68050 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24811 /* 68052 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24812 /* 68054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24813 /* 68057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24814 /* 68063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24815 /* 68069 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24816 /* 68072 */ GIR_RootConstrainSelectedInstOperands,
24817 /* 68073 */ // GIR_Coverage, 4403,
24818 /* 68073 */ GIR_EraseRootFromParent_Done,
24819 /* 68074 */ // Label 1443: @68074
24820 /* 68074 */ GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(68149), // Rule ID 4436 //
24821 /* 68079 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24822 /* 68082 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vadd),
24823 /* 68087 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24824 /* 68090 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24825 /* 68093 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24826 /* 68096 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24827 /* 68100 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24828 /* 68104 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24829 /* 68108 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3848:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
24830 /* 68108 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24831 /* 68111 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24832 /* 68115 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24833 /* 68120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32),
24834 /* 68123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24835 /* 68125 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24836 /* 68127 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24837 /* 68129 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24838 /* 68132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24839 /* 68138 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24840 /* 68144 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24841 /* 68147 */ GIR_RootConstrainSelectedInstOperands,
24842 /* 68148 */ // GIR_Coverage, 4436,
24843 /* 68148 */ GIR_EraseRootFromParent_Done,
24844 /* 68149 */ // Label 1444: @68149
24845 /* 68149 */ GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(68224), // Rule ID 4443 //
24846 /* 68154 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24847 /* 68157 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vadd),
24848 /* 68162 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24849 /* 68165 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24850 /* 68168 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24851 /* 68171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24852 /* 68175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24853 /* 68179 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24854 /* 68183 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3848:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
24855 /* 68183 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24856 /* 68186 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24857 /* 68190 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24858 /* 68195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16),
24859 /* 68198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24860 /* 68200 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24861 /* 68202 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24862 /* 68204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24863 /* 68207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24864 /* 68213 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24865 /* 68219 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24866 /* 68222 */ GIR_RootConstrainSelectedInstOperands,
24867 /* 68223 */ // GIR_Coverage, 4443,
24868 /* 68223 */ GIR_EraseRootFromParent_Done,
24869 /* 68224 */ // Label 1445: @68224
24870 /* 68224 */ GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(68299), // Rule ID 4450 //
24871 /* 68229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24872 /* 68232 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsub),
24873 /* 68237 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24874 /* 68240 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24875 /* 68243 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24876 /* 68246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24877 /* 68250 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24878 /* 68254 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24879 /* 68258 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3979:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
24880 /* 68258 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24881 /* 68261 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24882 /* 68265 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24883 /* 68270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32),
24884 /* 68273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24885 /* 68275 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24886 /* 68277 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24887 /* 68279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24888 /* 68282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24889 /* 68288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24890 /* 68294 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24891 /* 68297 */ GIR_RootConstrainSelectedInstOperands,
24892 /* 68298 */ // GIR_Coverage, 4450,
24893 /* 68298 */ GIR_EraseRootFromParent_Done,
24894 /* 68299 */ // Label 1446: @68299
24895 /* 68299 */ GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(68374), // Rule ID 4457 //
24896 /* 68304 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24897 /* 68307 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsub),
24898 /* 68312 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24899 /* 68315 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24900 /* 68318 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24901 /* 68321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24902 /* 68325 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24903 /* 68329 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24904 /* 68333 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3979:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
24905 /* 68333 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24906 /* 68336 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24907 /* 68340 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24908 /* 68345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16),
24909 /* 68348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24910 /* 68350 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24911 /* 68352 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24912 /* 68354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24913 /* 68357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24914 /* 68363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24915 /* 68369 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24916 /* 68372 */ GIR_RootConstrainSelectedInstOperands,
24917 /* 68373 */ // GIR_Coverage, 4457,
24918 /* 68373 */ GIR_EraseRootFromParent_Done,
24919 /* 68374 */ // Label 1447: @68374
24920 /* 68374 */ GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(68437), // Rule ID 4581 //
24921 /* 68379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24922 /* 68382 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_eq),
24923 /* 68387 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
24924 /* 68390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24925 /* 68393 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24926 /* 68396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24927 /* 68400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24928 /* 68404 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24929 /* 68408 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3780:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 0:{ *:[i32] })
24930 /* 68408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
24931 /* 68411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24932 /* 68413 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24933 /* 68415 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24934 /* 68417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24935 /* 68420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24936 /* 68423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24937 /* 68429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24938 /* 68435 */ GIR_RootConstrainSelectedInstOperands,
24939 /* 68436 */ // GIR_Coverage, 4581,
24940 /* 68436 */ GIR_EraseRootFromParent_Done,
24941 /* 68437 */ // Label 1448: @68437
24942 /* 68437 */ GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(68500), // Rule ID 4583 //
24943 /* 68442 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24944 /* 68445 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_eq),
24945 /* 68450 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
24946 /* 68453 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24947 /* 68456 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24948 /* 68459 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24949 /* 68463 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24950 /* 68467 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24951 /* 68471 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3780:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 0:{ *:[i32] })
24952 /* 68471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
24953 /* 68474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24954 /* 68476 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24955 /* 68478 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24956 /* 68480 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24957 /* 68483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24958 /* 68486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24959 /* 68492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24960 /* 68498 */ GIR_RootConstrainSelectedInstOperands,
24961 /* 68499 */ // GIR_Coverage, 4583,
24962 /* 68499 */ GIR_EraseRootFromParent_Done,
24963 /* 68500 */ // Label 1449: @68500
24964 /* 68500 */ GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(68563), // Rule ID 4670 //
24965 /* 68505 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24966 /* 68508 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ne),
24967 /* 68513 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
24968 /* 68516 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24969 /* 68519 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24970 /* 68522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24971 /* 68526 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24972 /* 68530 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24973 /* 68534 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3785:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 1:{ *:[i32] })
24974 /* 68534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
24975 /* 68537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24976 /* 68539 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24977 /* 68541 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24978 /* 68543 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
24979 /* 68546 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24980 /* 68549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24981 /* 68555 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24982 /* 68561 */ GIR_RootConstrainSelectedInstOperands,
24983 /* 68562 */ // GIR_Coverage, 4670,
24984 /* 68562 */ GIR_EraseRootFromParent_Done,
24985 /* 68563 */ // Label 1450: @68563
24986 /* 68563 */ GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(68626), // Rule ID 4672 //
24987 /* 68568 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24988 /* 68571 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ne),
24989 /* 68576 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
24990 /* 68579 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24991 /* 68582 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24992 /* 68585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24993 /* 68589 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24994 /* 68593 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24995 /* 68597 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3785:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 1:{ *:[i32] })
24996 /* 68597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
24997 /* 68600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24998 /* 68602 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24999 /* 68604 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25000 /* 68606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
25001 /* 68609 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25002 /* 68612 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25003 /* 68618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25004 /* 68624 */ GIR_RootConstrainSelectedInstOperands,
25005 /* 68625 */ // GIR_Coverage, 4672,
25006 /* 68625 */ GIR_EraseRootFromParent_Done,
25007 /* 68626 */ // Label 1451: @68626
25008 /* 68626 */ GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(68689), // Rule ID 4686 //
25009 /* 68631 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25010 /* 68634 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ge),
25011 /* 68639 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
25012 /* 68642 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25013 /* 68645 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25014 /* 68648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25015 /* 68652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25016 /* 68656 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25017 /* 68660 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3781:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 10:{ *:[i32] })
25018 /* 68660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
25019 /* 68663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25020 /* 68665 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25021 /* 68667 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25022 /* 68669 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/10,
25023 /* 68672 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25024 /* 68675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25025 /* 68681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25026 /* 68687 */ GIR_RootConstrainSelectedInstOperands,
25027 /* 68688 */ // GIR_Coverage, 4686,
25028 /* 68688 */ GIR_EraseRootFromParent_Done,
25029 /* 68689 */ // Label 1452: @68689
25030 /* 68689 */ GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(68752), // Rule ID 4688 //
25031 /* 68694 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25032 /* 68697 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ge),
25033 /* 68702 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
25034 /* 68705 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25035 /* 68708 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25036 /* 68711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25037 /* 68715 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25038 /* 68719 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25039 /* 68723 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3781:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 10:{ *:[i32] })
25040 /* 68723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
25041 /* 68726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25042 /* 68728 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25043 /* 68730 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25044 /* 68732 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/10,
25045 /* 68735 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25046 /* 68738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25047 /* 68744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25048 /* 68750 */ GIR_RootConstrainSelectedInstOperands,
25049 /* 68751 */ // GIR_Coverage, 4688,
25050 /* 68751 */ GIR_EraseRootFromParent_Done,
25051 /* 68752 */ // Label 1453: @68752
25052 /* 68752 */ GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(68815), // Rule ID 4702 //
25053 /* 68757 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25054 /* 68760 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_lt),
25055 /* 68765 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
25056 /* 68768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25057 /* 68771 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25058 /* 68774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25059 /* 68778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25060 /* 68782 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25061 /* 68786 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3784:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 11:{ *:[i32] })
25062 /* 68786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
25063 /* 68789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25064 /* 68791 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25065 /* 68793 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25066 /* 68795 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/11,
25067 /* 68798 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25068 /* 68801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25069 /* 68807 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25070 /* 68813 */ GIR_RootConstrainSelectedInstOperands,
25071 /* 68814 */ // GIR_Coverage, 4702,
25072 /* 68814 */ GIR_EraseRootFromParent_Done,
25073 /* 68815 */ // Label 1454: @68815
25074 /* 68815 */ GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(68878), // Rule ID 4704 //
25075 /* 68820 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25076 /* 68823 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_lt),
25077 /* 68828 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
25078 /* 68831 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25079 /* 68834 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25080 /* 68837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25081 /* 68841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25082 /* 68845 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25083 /* 68849 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3784:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 11:{ *:[i32] })
25084 /* 68849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
25085 /* 68852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25086 /* 68854 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25087 /* 68856 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25088 /* 68858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/11,
25089 /* 68861 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25090 /* 68864 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25091 /* 68870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25092 /* 68876 */ GIR_RootConstrainSelectedInstOperands,
25093 /* 68877 */ // GIR_Coverage, 4704,
25094 /* 68877 */ GIR_EraseRootFromParent_Done,
25095 /* 68878 */ // Label 1455: @68878
25096 /* 68878 */ GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(68941), // Rule ID 4718 //
25097 /* 68883 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25098 /* 68886 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_gt),
25099 /* 68891 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
25100 /* 68894 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25101 /* 68897 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25102 /* 68900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25103 /* 68904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25104 /* 68908 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25105 /* 68912 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3782:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 12:{ *:[i32] })
25106 /* 68912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
25107 /* 68915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25108 /* 68917 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25109 /* 68919 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25110 /* 68921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/12,
25111 /* 68924 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25112 /* 68927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25113 /* 68933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25114 /* 68939 */ GIR_RootConstrainSelectedInstOperands,
25115 /* 68940 */ // GIR_Coverage, 4718,
25116 /* 68940 */ GIR_EraseRootFromParent_Done,
25117 /* 68941 */ // Label 1456: @68941
25118 /* 68941 */ GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(69004), // Rule ID 4720 //
25119 /* 68946 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25120 /* 68949 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_gt),
25121 /* 68954 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
25122 /* 68957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25123 /* 68960 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25124 /* 68963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25125 /* 68967 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25126 /* 68971 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25127 /* 68975 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3782:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 12:{ *:[i32] })
25128 /* 68975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
25129 /* 68978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25130 /* 68980 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25131 /* 68982 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25132 /* 68984 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/12,
25133 /* 68987 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25134 /* 68990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25135 /* 68996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25136 /* 69002 */ GIR_RootConstrainSelectedInstOperands,
25137 /* 69003 */ // GIR_Coverage, 4720,
25138 /* 69003 */ GIR_EraseRootFromParent_Done,
25139 /* 69004 */ // Label 1457: @69004
25140 /* 69004 */ GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(69067), // Rule ID 4734 //
25141 /* 69009 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25142 /* 69012 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_le),
25143 /* 69017 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
25144 /* 69020 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25145 /* 69023 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25146 /* 69026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25147 /* 69030 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25148 /* 69034 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25149 /* 69038 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3783:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 13:{ *:[i32] })
25150 /* 69038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
25151 /* 69041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25152 /* 69043 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25153 /* 69045 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25154 /* 69047 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/13,
25155 /* 69050 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25156 /* 69053 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25157 /* 69059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25158 /* 69065 */ GIR_RootConstrainSelectedInstOperands,
25159 /* 69066 */ // GIR_Coverage, 4734,
25160 /* 69066 */ GIR_EraseRootFromParent_Done,
25161 /* 69067 */ // Label 1458: @69067
25162 /* 69067 */ GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(69130), // Rule ID 4736 //
25163 /* 69072 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25164 /* 69075 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_le),
25165 /* 69080 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
25166 /* 69083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25167 /* 69086 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25168 /* 69089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25169 /* 69093 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25170 /* 69097 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25171 /* 69101 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3783:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 13:{ *:[i32] })
25172 /* 69101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
25173 /* 69104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25174 /* 69106 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25175 /* 69108 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25176 /* 69110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/13,
25177 /* 69113 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25178 /* 69116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25179 /* 69122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25180 /* 69128 */ GIR_RootConstrainSelectedInstOperands,
25181 /* 69129 */ // GIR_Coverage, 4736,
25182 /* 69129 */ GIR_EraseRootFromParent_Done,
25183 /* 69130 */ // Label 1459: @69130
25184 /* 69130 */ GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(69205), // Rule ID 5258 //
25185 /* 69135 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25186 /* 69138 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
25187 /* 69143 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25188 /* 69146 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25189 /* 69149 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25190 /* 69152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25191 /* 69156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25192 /* 69160 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25193 /* 69164 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3849:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm)
25194 /* 69164 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25195 /* 69167 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25196 /* 69171 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25197 /* 69176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8),
25198 /* 69179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25199 /* 69181 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
25200 /* 69183 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
25201 /* 69185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25202 /* 69188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25203 /* 69194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25204 /* 69200 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25205 /* 69203 */ GIR_RootConstrainSelectedInstOperands,
25206 /* 69204 */ // GIR_Coverage, 5258,
25207 /* 69204 */ GIR_EraseRootFromParent_Done,
25208 /* 69205 */ // Label 1460: @69205
25209 /* 69205 */ GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(69280), // Rule ID 5263 //
25210 /* 69210 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25211 /* 69213 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
25212 /* 69218 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25213 /* 69221 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25214 /* 69224 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25215 /* 69227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25216 /* 69231 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25217 /* 69235 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25218 /* 69239 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3849:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm)
25219 /* 69239 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25220 /* 69242 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25221 /* 69246 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25222 /* 69251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16),
25223 /* 69254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25224 /* 69256 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
25225 /* 69258 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
25226 /* 69260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25227 /* 69263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25228 /* 69269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25229 /* 69275 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25230 /* 69278 */ GIR_RootConstrainSelectedInstOperands,
25231 /* 69279 */ // GIR_Coverage, 5263,
25232 /* 69279 */ GIR_EraseRootFromParent_Done,
25233 /* 69280 */ // Label 1461: @69280
25234 /* 69280 */ GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(69355), // Rule ID 5265 //
25235 /* 69285 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25236 /* 69288 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
25237 /* 69293 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25238 /* 69296 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25239 /* 69299 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25240 /* 69302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25241 /* 69306 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25242 /* 69310 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25243 /* 69314 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3849:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm)
25244 /* 69314 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25245 /* 69317 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25246 /* 69321 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25247 /* 69326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32),
25248 /* 69329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25249 /* 69331 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
25250 /* 69333 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
25251 /* 69335 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25252 /* 69338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25253 /* 69344 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25254 /* 69350 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25255 /* 69353 */ GIR_RootConstrainSelectedInstOperands,
25256 /* 69354 */ // GIR_Coverage, 5265,
25257 /* 69354 */ GIR_EraseRootFromParent_Done,
25258 /* 69355 */ // Label 1462: @69355
25259 /* 69355 */ GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(69430), // Rule ID 5267 //
25260 /* 69360 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25261 /* 69363 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
25262 /* 69368 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25263 /* 69371 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25264 /* 69374 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25265 /* 69377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25266 /* 69381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25267 /* 69385 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25268 /* 69389 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3849:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm)
25269 /* 69389 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25270 /* 69392 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25271 /* 69396 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25272 /* 69401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16),
25273 /* 69404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25274 /* 69406 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
25275 /* 69408 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
25276 /* 69410 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25277 /* 69413 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25278 /* 69419 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25279 /* 69425 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25280 /* 69428 */ GIR_RootConstrainSelectedInstOperands,
25281 /* 69429 */ // GIR_Coverage, 5267,
25282 /* 69429 */ GIR_EraseRootFromParent_Done,
25283 /* 69430 */ // Label 1463: @69430
25284 /* 69430 */ GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(69505), // Rule ID 5269 //
25285 /* 69435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25286 /* 69438 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
25287 /* 69443 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25288 /* 69446 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25289 /* 69449 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25290 /* 69452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25291 /* 69456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25292 /* 69460 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25293 /* 69464 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3849:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm)
25294 /* 69464 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25295 /* 69467 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25296 /* 69471 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25297 /* 69476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32),
25298 /* 69479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25299 /* 69481 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
25300 /* 69483 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
25301 /* 69485 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25302 /* 69488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25303 /* 69494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25304 /* 69500 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25305 /* 69503 */ GIR_RootConstrainSelectedInstOperands,
25306 /* 69504 */ // GIR_Coverage, 5269,
25307 /* 69504 */ GIR_EraseRootFromParent_Done,
25308 /* 69505 */ // Label 1464: @69505
25309 /* 69505 */ GIM_Reject,
25310 /* 69506 */ // Label 1075: @69506
25311 /* 69506 */ GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(80506),
25312 /* 69511 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
25313 /* 69514 */ GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(69604), // Rule ID 4299 //
25314 /* 69519 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
25315 /* 69524 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25316 /* 69527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25317 /* 69530 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25318 /* 69533 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25319 /* 69536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25320 /* 69540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25321 /* 69544 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25322 /* 69548 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25323 /* 69552 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
25324 /* 69556 */ // MIs[1] Operand 1
25325 /* 69556 */ // No operand predicates
25326 /* 69556 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25327 /* 69560 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25328 /* 69562 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3931:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
25329 /* 69562 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25330 /* 69565 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25331 /* 69569 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25332 /* 69574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms8),
25333 /* 69577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25334 /* 69579 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25335 /* 69581 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25336 /* 69584 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25337 /* 69587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25338 /* 69593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25339 /* 69599 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25340 /* 69602 */ GIR_RootConstrainSelectedInstOperands,
25341 /* 69603 */ // GIR_Coverage, 4299,
25342 /* 69603 */ GIR_EraseRootFromParent_Done,
25343 /* 69604 */ // Label 1466: @69604
25344 /* 69604 */ GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(69694), // Rule ID 4301 //
25345 /* 69609 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
25346 /* 69614 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25347 /* 69617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25348 /* 69620 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25349 /* 69623 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25350 /* 69626 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25351 /* 69630 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25352 /* 69634 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25353 /* 69638 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25354 /* 69642 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
25355 /* 69646 */ // MIs[1] Operand 1
25356 /* 69646 */ // No operand predicates
25357 /* 69646 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25358 /* 69650 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25359 /* 69652 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3931:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
25360 /* 69652 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25361 /* 69655 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25362 /* 69659 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25363 /* 69664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu8),
25364 /* 69667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25365 /* 69669 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25366 /* 69671 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25367 /* 69674 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25368 /* 69677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25369 /* 69683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25370 /* 69689 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25371 /* 69692 */ GIR_RootConstrainSelectedInstOperands,
25372 /* 69693 */ // GIR_Coverage, 4301,
25373 /* 69693 */ GIR_EraseRootFromParent_Done,
25374 /* 69694 */ // Label 1467: @69694
25375 /* 69694 */ GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(69784), // Rule ID 4303 //
25376 /* 69699 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
25377 /* 69704 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25378 /* 69707 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25379 /* 69710 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25380 /* 69713 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25381 /* 69716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25382 /* 69720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25383 /* 69724 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25384 /* 69728 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25385 /* 69732 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
25386 /* 69736 */ // MIs[1] Operand 1
25387 /* 69736 */ // No operand predicates
25388 /* 69736 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25389 /* 69740 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25390 /* 69742 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3931:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
25391 /* 69742 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25392 /* 69745 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25393 /* 69749 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25394 /* 69754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms16),
25395 /* 69757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25396 /* 69759 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25397 /* 69761 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25398 /* 69764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25399 /* 69767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25400 /* 69773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25401 /* 69779 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25402 /* 69782 */ GIR_RootConstrainSelectedInstOperands,
25403 /* 69783 */ // GIR_Coverage, 4303,
25404 /* 69783 */ GIR_EraseRootFromParent_Done,
25405 /* 69784 */ // Label 1468: @69784
25406 /* 69784 */ GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(69874), // Rule ID 4305 //
25407 /* 69789 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
25408 /* 69794 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25409 /* 69797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25410 /* 69800 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25411 /* 69803 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25412 /* 69806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25413 /* 69810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25414 /* 69814 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25415 /* 69818 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25416 /* 69822 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
25417 /* 69826 */ // MIs[1] Operand 1
25418 /* 69826 */ // No operand predicates
25419 /* 69826 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25420 /* 69830 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25421 /* 69832 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3931:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
25422 /* 69832 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25423 /* 69835 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25424 /* 69839 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25425 /* 69844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu16),
25426 /* 69847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25427 /* 69849 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25428 /* 69851 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25429 /* 69854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25430 /* 69857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25431 /* 69863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25432 /* 69869 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25433 /* 69872 */ GIR_RootConstrainSelectedInstOperands,
25434 /* 69873 */ // GIR_Coverage, 4305,
25435 /* 69873 */ GIR_EraseRootFromParent_Done,
25436 /* 69874 */ // Label 1469: @69874
25437 /* 69874 */ GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(69964), // Rule ID 4307 //
25438 /* 69879 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
25439 /* 69884 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25440 /* 69887 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25441 /* 69890 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25442 /* 69893 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25443 /* 69896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25444 /* 69900 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25445 /* 69904 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25446 /* 69908 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25447 /* 69912 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
25448 /* 69916 */ // MIs[1] Operand 1
25449 /* 69916 */ // No operand predicates
25450 /* 69916 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25451 /* 69920 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25452 /* 69922 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3931:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
25453 /* 69922 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25454 /* 69925 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25455 /* 69929 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25456 /* 69934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms32),
25457 /* 69937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25458 /* 69939 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25459 /* 69941 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25460 /* 69944 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25461 /* 69947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25462 /* 69953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25463 /* 69959 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25464 /* 69962 */ GIR_RootConstrainSelectedInstOperands,
25465 /* 69963 */ // GIR_Coverage, 4307,
25466 /* 69963 */ GIR_EraseRootFromParent_Done,
25467 /* 69964 */ // Label 1470: @69964
25468 /* 69964 */ GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(70054), // Rule ID 4309 //
25469 /* 69969 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
25470 /* 69974 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25471 /* 69977 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25472 /* 69980 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25473 /* 69983 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25474 /* 69986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25475 /* 69990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25476 /* 69994 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25477 /* 69998 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25478 /* 70002 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
25479 /* 70006 */ // MIs[1] Operand 1
25480 /* 70006 */ // No operand predicates
25481 /* 70006 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25482 /* 70010 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25483 /* 70012 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3931:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
25484 /* 70012 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25485 /* 70015 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25486 /* 70019 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25487 /* 70024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu32),
25488 /* 70027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25489 /* 70029 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25490 /* 70031 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25491 /* 70034 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25492 /* 70037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25493 /* 70043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25494 /* 70049 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25495 /* 70052 */ GIR_RootConstrainSelectedInstOperands,
25496 /* 70053 */ // GIR_Coverage, 4309,
25497 /* 70053 */ GIR_EraseRootFromParent_Done,
25498 /* 70054 */ // Label 1471: @70054
25499 /* 70054 */ GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(70144), // Rule ID 4317 //
25500 /* 70059 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
25501 /* 70064 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25502 /* 70067 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25503 /* 70070 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25504 /* 70073 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25505 /* 70076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25506 /* 70080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25507 /* 70084 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25508 /* 70088 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25509 /* 70092 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
25510 /* 70096 */ // MIs[1] Operand 1
25511 /* 70096 */ // No operand predicates
25512 /* 70096 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25513 /* 70100 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25514 /* 70102 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
25515 /* 70102 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25516 /* 70105 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25517 /* 70109 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25518 /* 70114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms8),
25519 /* 70117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25520 /* 70119 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25521 /* 70121 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25522 /* 70124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25523 /* 70127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25524 /* 70133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25525 /* 70139 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25526 /* 70142 */ GIR_RootConstrainSelectedInstOperands,
25527 /* 70143 */ // GIR_Coverage, 4317,
25528 /* 70143 */ GIR_EraseRootFromParent_Done,
25529 /* 70144 */ // Label 1472: @70144
25530 /* 70144 */ GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(70234), // Rule ID 4319 //
25531 /* 70149 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
25532 /* 70154 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25533 /* 70157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25534 /* 70160 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25535 /* 70163 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25536 /* 70166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25537 /* 70170 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25538 /* 70174 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25539 /* 70178 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25540 /* 70182 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
25541 /* 70186 */ // MIs[1] Operand 1
25542 /* 70186 */ // No operand predicates
25543 /* 70186 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25544 /* 70190 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25545 /* 70192 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3953:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
25546 /* 70192 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25547 /* 70195 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25548 /* 70199 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25549 /* 70204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu8),
25550 /* 70207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25551 /* 70209 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25552 /* 70211 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25553 /* 70214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25554 /* 70217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25555 /* 70223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25556 /* 70229 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25557 /* 70232 */ GIR_RootConstrainSelectedInstOperands,
25558 /* 70233 */ // GIR_Coverage, 4319,
25559 /* 70233 */ GIR_EraseRootFromParent_Done,
25560 /* 70234 */ // Label 1473: @70234
25561 /* 70234 */ GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(70324), // Rule ID 4321 //
25562 /* 70239 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
25563 /* 70244 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25564 /* 70247 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25565 /* 70250 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25566 /* 70253 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25567 /* 70256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25568 /* 70260 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25569 /* 70264 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25570 /* 70268 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25571 /* 70272 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
25572 /* 70276 */ // MIs[1] Operand 1
25573 /* 70276 */ // No operand predicates
25574 /* 70276 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25575 /* 70280 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25576 /* 70282 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
25577 /* 70282 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25578 /* 70285 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25579 /* 70289 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25580 /* 70294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms16),
25581 /* 70297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25582 /* 70299 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25583 /* 70301 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25584 /* 70304 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25585 /* 70307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25586 /* 70313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25587 /* 70319 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25588 /* 70322 */ GIR_RootConstrainSelectedInstOperands,
25589 /* 70323 */ // GIR_Coverage, 4321,
25590 /* 70323 */ GIR_EraseRootFromParent_Done,
25591 /* 70324 */ // Label 1474: @70324
25592 /* 70324 */ GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(70414), // Rule ID 4323 //
25593 /* 70329 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
25594 /* 70334 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25595 /* 70337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25596 /* 70340 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25597 /* 70343 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25598 /* 70346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25599 /* 70350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25600 /* 70354 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25601 /* 70358 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25602 /* 70362 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
25603 /* 70366 */ // MIs[1] Operand 1
25604 /* 70366 */ // No operand predicates
25605 /* 70366 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25606 /* 70370 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25607 /* 70372 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
25608 /* 70372 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25609 /* 70375 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25610 /* 70379 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25611 /* 70384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu16),
25612 /* 70387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25613 /* 70389 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25614 /* 70391 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25615 /* 70394 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25616 /* 70397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25617 /* 70403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25618 /* 70409 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25619 /* 70412 */ GIR_RootConstrainSelectedInstOperands,
25620 /* 70413 */ // GIR_Coverage, 4323,
25621 /* 70413 */ GIR_EraseRootFromParent_Done,
25622 /* 70414 */ // Label 1475: @70414
25623 /* 70414 */ GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(70504), // Rule ID 4325 //
25624 /* 70419 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
25625 /* 70424 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25626 /* 70427 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25627 /* 70430 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25628 /* 70433 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25629 /* 70436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25630 /* 70440 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25631 /* 70444 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25632 /* 70448 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25633 /* 70452 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32),
25634 /* 70456 */ // MIs[1] Operand 1
25635 /* 70456 */ // No operand predicates
25636 /* 70456 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25637 /* 70460 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25638 /* 70462 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
25639 /* 70462 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25640 /* 70465 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25641 /* 70469 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25642 /* 70474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms32),
25643 /* 70477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25644 /* 70479 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25645 /* 70481 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25646 /* 70484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25647 /* 70487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25648 /* 70493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25649 /* 70499 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25650 /* 70502 */ GIR_RootConstrainSelectedInstOperands,
25651 /* 70503 */ // GIR_Coverage, 4325,
25652 /* 70503 */ GIR_EraseRootFromParent_Done,
25653 /* 70504 */ // Label 1476: @70504
25654 /* 70504 */ GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(70594), // Rule ID 4327 //
25655 /* 70509 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
25656 /* 70514 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25657 /* 70517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25658 /* 70520 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25659 /* 70523 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25660 /* 70526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25661 /* 70530 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25662 /* 70534 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25663 /* 70538 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25664 /* 70542 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32),
25665 /* 70546 */ // MIs[1] Operand 1
25666 /* 70546 */ // No operand predicates
25667 /* 70546 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25668 /* 70550 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25669 /* 70552 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
25670 /* 70552 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25671 /* 70555 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25672 /* 70559 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25673 /* 70564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu32),
25674 /* 70567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25675 /* 70569 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25676 /* 70571 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25677 /* 70574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25678 /* 70577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25679 /* 70583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25680 /* 70589 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25681 /* 70592 */ GIR_RootConstrainSelectedInstOperands,
25682 /* 70593 */ // GIR_Coverage, 4327,
25683 /* 70593 */ GIR_EraseRootFromParent_Done,
25684 /* 70594 */ // Label 1477: @70594
25685 /* 70594 */ GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(70683), // Rule ID 4473 //
25686 /* 70599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25687 /* 70602 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25688 /* 70607 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25689 /* 70610 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25690 /* 70613 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25691 /* 70616 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25692 /* 70619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25693 /* 70623 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
25694 /* 70627 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25695 /* 70631 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25696 /* 70635 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25697 /* 70639 */ // MIs[1] Operand 1
25698 /* 70639 */ // No operand predicates
25699 /* 70639 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25700 /* 70641 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3862:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16s16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)
25701 /* 70641 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25702 /* 70644 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25703 /* 70648 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25704 /* 70653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16_fix),
25705 /* 70656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25706 /* 70658 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25707 /* 70660 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25708 /* 70663 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25709 /* 70666 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25710 /* 70672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25711 /* 70678 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25712 /* 70681 */ GIR_RootConstrainSelectedInstOperands,
25713 /* 70682 */ // GIR_Coverage, 4473,
25714 /* 70682 */ GIR_EraseRootFromParent_Done,
25715 /* 70683 */ // Label 1478: @70683
25716 /* 70683 */ GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(70772), // Rule ID 4475 //
25717 /* 70688 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25718 /* 70691 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25719 /* 70696 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25720 /* 70699 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25721 /* 70702 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25722 /* 70705 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25723 /* 70708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25724 /* 70712 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
25725 /* 70716 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25726 /* 70720 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25727 /* 70724 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25728 /* 70728 */ // MIs[1] Operand 1
25729 /* 70728 */ // No operand predicates
25730 /* 70728 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25731 /* 70730 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3862:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)
25732 /* 70730 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25733 /* 70733 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25734 /* 70737 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25735 /* 70742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16_fix),
25736 /* 70745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25737 /* 70747 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25738 /* 70749 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25739 /* 70752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25740 /* 70755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25741 /* 70761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25742 /* 70767 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25743 /* 70770 */ GIR_RootConstrainSelectedInstOperands,
25744 /* 70771 */ // GIR_Coverage, 4475,
25745 /* 70771 */ GIR_EraseRootFromParent_Done,
25746 /* 70772 */ // Label 1479: @70772
25747 /* 70772 */ GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(70861), // Rule ID 4477 //
25748 /* 70777 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25749 /* 70780 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25750 /* 70785 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25751 /* 70788 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25752 /* 70791 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25753 /* 70794 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25754 /* 70797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25755 /* 70801 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
25756 /* 70805 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25757 /* 70809 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25758 /* 70813 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25759 /* 70817 */ // MIs[1] Operand 1
25760 /* 70817 */ // No operand predicates
25761 /* 70817 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25762 /* 70819 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3862:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16u16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)
25763 /* 70819 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25764 /* 70822 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25765 /* 70826 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25766 /* 70831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16_fix),
25767 /* 70834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25768 /* 70836 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25769 /* 70838 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25770 /* 70841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25771 /* 70844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25772 /* 70850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25773 /* 70856 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25774 /* 70859 */ GIR_RootConstrainSelectedInstOperands,
25775 /* 70860 */ // GIR_Coverage, 4477,
25776 /* 70860 */ GIR_EraseRootFromParent_Done,
25777 /* 70861 */ // Label 1480: @70861
25778 /* 70861 */ GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(70950), // Rule ID 4479 //
25779 /* 70866 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25780 /* 70869 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25781 /* 70874 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25782 /* 70877 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25783 /* 70880 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25784 /* 70883 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25785 /* 70886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25786 /* 70890 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
25787 /* 70894 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25788 /* 70898 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25789 /* 70902 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25790 /* 70906 */ // MIs[1] Operand 1
25791 /* 70906 */ // No operand predicates
25792 /* 70906 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25793 /* 70908 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3862:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)
25794 /* 70908 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25795 /* 70911 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25796 /* 70915 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25797 /* 70920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16_fix),
25798 /* 70923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25799 /* 70925 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25800 /* 70927 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25801 /* 70930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25802 /* 70933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25803 /* 70939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25804 /* 70945 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25805 /* 70948 */ GIR_RootConstrainSelectedInstOperands,
25806 /* 70949 */ // GIR_Coverage, 4479,
25807 /* 70949 */ GIR_EraseRootFromParent_Done,
25808 /* 70950 */ // Label 1481: @70950
25809 /* 70950 */ GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(71039), // Rule ID 4481 //
25810 /* 70955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25811 /* 70958 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25812 /* 70963 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25813 /* 70966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25814 /* 70969 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25815 /* 70972 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25816 /* 70975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25817 /* 70979 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
25818 /* 70983 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25819 /* 70987 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25820 /* 70991 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25821 /* 70995 */ // MIs[1] Operand 1
25822 /* 70995 */ // No operand predicates
25823 /* 70995 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25824 /* 70997 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3862:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32s32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)
25825 /* 70997 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25826 /* 71000 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25827 /* 71004 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25828 /* 71009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32_fix),
25829 /* 71012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25830 /* 71014 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25831 /* 71016 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25832 /* 71019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25833 /* 71022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25834 /* 71028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25835 /* 71034 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25836 /* 71037 */ GIR_RootConstrainSelectedInstOperands,
25837 /* 71038 */ // GIR_Coverage, 4481,
25838 /* 71038 */ GIR_EraseRootFromParent_Done,
25839 /* 71039 */ // Label 1482: @71039
25840 /* 71039 */ GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(71128), // Rule ID 4483 //
25841 /* 71044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25842 /* 71047 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25843 /* 71052 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25844 /* 71055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25845 /* 71058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25846 /* 71061 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25847 /* 71064 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25848 /* 71068 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
25849 /* 71072 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25850 /* 71076 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25851 /* 71080 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25852 /* 71084 */ // MIs[1] Operand 1
25853 /* 71084 */ // No operand predicates
25854 /* 71084 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25855 /* 71086 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3862:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)
25856 /* 71086 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25857 /* 71089 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25858 /* 71093 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25859 /* 71098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32_fix),
25860 /* 71101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25861 /* 71103 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25862 /* 71105 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25863 /* 71108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25864 /* 71111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25865 /* 71117 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25866 /* 71123 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25867 /* 71126 */ GIR_RootConstrainSelectedInstOperands,
25868 /* 71127 */ // GIR_Coverage, 4483,
25869 /* 71127 */ GIR_EraseRootFromParent_Done,
25870 /* 71128 */ // Label 1483: @71128
25871 /* 71128 */ GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(71217), // Rule ID 4485 //
25872 /* 71133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25873 /* 71136 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25874 /* 71141 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25875 /* 71144 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25876 /* 71147 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25877 /* 71150 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25878 /* 71153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25879 /* 71157 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
25880 /* 71161 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25881 /* 71165 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25882 /* 71169 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25883 /* 71173 */ // MIs[1] Operand 1
25884 /* 71173 */ // No operand predicates
25885 /* 71173 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25886 /* 71175 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3862:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32u32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)
25887 /* 71175 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25888 /* 71178 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25889 /* 71182 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25890 /* 71187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32_fix),
25891 /* 71190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25892 /* 71192 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25893 /* 71194 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25894 /* 71197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25895 /* 71200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25896 /* 71206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25897 /* 71212 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25898 /* 71215 */ GIR_RootConstrainSelectedInstOperands,
25899 /* 71216 */ // GIR_Coverage, 4485,
25900 /* 71216 */ GIR_EraseRootFromParent_Done,
25901 /* 71217 */ // Label 1484: @71217
25902 /* 71217 */ GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(71306), // Rule ID 4487 //
25903 /* 71222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25904 /* 71225 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25905 /* 71230 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25906 /* 71233 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25907 /* 71236 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25908 /* 71239 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25909 /* 71242 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25910 /* 71246 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
25911 /* 71250 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25912 /* 71254 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25913 /* 71258 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25914 /* 71262 */ // MIs[1] Operand 1
25915 /* 71262 */ // No operand predicates
25916 /* 71262 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25917 /* 71264 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3862:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)
25918 /* 71264 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25919 /* 71267 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25920 /* 71271 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25921 /* 71276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32_fix),
25922 /* 71279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25923 /* 71281 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25924 /* 71283 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25925 /* 71286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25926 /* 71289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25927 /* 71295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25928 /* 71301 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25929 /* 71304 */ GIR_RootConstrainSelectedInstOperands,
25930 /* 71305 */ // GIR_Coverage, 4487,
25931 /* 71305 */ GIR_EraseRootFromParent_Done,
25932 /* 71306 */ // Label 1485: @71306
25933 /* 71306 */ GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(71373), // Rule ID 3498 //
25934 /* 71311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25935 /* 71314 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
25936 /* 71319 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
25937 /* 71322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25938 /* 71325 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25939 /* 71328 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25940 /* 71331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25941 /* 71335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25942 /* 71339 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25943 /* 71343 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25944 /* 71347 */ // (intrinsic_wo_chain:{ *:[i32] } 3808:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25945 /* 71347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8),
25946 /* 71350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25947 /* 71352 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25948 /* 71354 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25949 /* 71356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25950 /* 71359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25951 /* 71365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25952 /* 71371 */ GIR_RootConstrainSelectedInstOperands,
25953 /* 71372 */ // GIR_Coverage, 3498,
25954 /* 71372 */ GIR_EraseRootFromParent_Done,
25955 /* 71373 */ // Label 1486: @71373
25956 /* 71373 */ GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(71440), // Rule ID 3500 //
25957 /* 71378 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25958 /* 71381 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
25959 /* 71386 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
25960 /* 71389 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25961 /* 71392 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25962 /* 71395 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25963 /* 71398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25964 /* 71402 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25965 /* 71406 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25966 /* 71410 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25967 /* 71414 */ // (intrinsic_wo_chain:{ *:[i32] } 3808:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25968 /* 71414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16),
25969 /* 71417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25970 /* 71419 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25971 /* 71421 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25972 /* 71423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25973 /* 71426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25974 /* 71432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25975 /* 71438 */ GIR_RootConstrainSelectedInstOperands,
25976 /* 71439 */ // GIR_Coverage, 3500,
25977 /* 71439 */ GIR_EraseRootFromParent_Done,
25978 /* 71440 */ // Label 1487: @71440
25979 /* 71440 */ GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(71507), // Rule ID 3502 //
25980 /* 71445 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25981 /* 71448 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
25982 /* 71453 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
25983 /* 71456 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25984 /* 71459 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25985 /* 71462 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25986 /* 71465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25987 /* 71469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25988 /* 71473 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25989 /* 71477 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25990 /* 71481 */ // (intrinsic_wo_chain:{ *:[i32] } 3808:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25991 /* 71481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32),
25992 /* 71484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25993 /* 71486 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25994 /* 71488 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25995 /* 71490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25996 /* 71493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25997 /* 71499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25998 /* 71505 */ GIR_RootConstrainSelectedInstOperands,
25999 /* 71506 */ // GIR_Coverage, 3502,
26000 /* 71506 */ GIR_EraseRootFromParent_Done,
26001 /* 71507 */ // Label 1488: @71507
26002 /* 71507 */ GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(71574), // Rule ID 3504 //
26003 /* 71512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26004 /* 71515 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
26005 /* 71520 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26006 /* 71523 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26007 /* 71526 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26008 /* 71529 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26009 /* 71532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26010 /* 71536 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26011 /* 71540 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26012 /* 71544 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26013 /* 71548 */ // (intrinsic_wo_chain:{ *:[i32] } 3808:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
26014 /* 71548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8),
26015 /* 71551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26016 /* 71553 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26017 /* 71555 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26018 /* 71557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26019 /* 71560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26020 /* 71566 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26021 /* 71572 */ GIR_RootConstrainSelectedInstOperands,
26022 /* 71573 */ // GIR_Coverage, 3504,
26023 /* 71573 */ GIR_EraseRootFromParent_Done,
26024 /* 71574 */ // Label 1489: @71574
26025 /* 71574 */ GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(71641), // Rule ID 3506 //
26026 /* 71579 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26027 /* 71582 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
26028 /* 71587 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26029 /* 71590 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26030 /* 71593 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26031 /* 71596 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26032 /* 71599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26033 /* 71603 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26034 /* 71607 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26035 /* 71611 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26036 /* 71615 */ // (intrinsic_wo_chain:{ *:[i32] } 3808:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
26037 /* 71615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16),
26038 /* 71618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26039 /* 71620 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26040 /* 71622 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26041 /* 71624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26042 /* 71627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26043 /* 71633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26044 /* 71639 */ GIR_RootConstrainSelectedInstOperands,
26045 /* 71640 */ // GIR_Coverage, 3506,
26046 /* 71640 */ GIR_EraseRootFromParent_Done,
26047 /* 71641 */ // Label 1490: @71641
26048 /* 71641 */ GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(71708), // Rule ID 3508 //
26049 /* 71646 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26050 /* 71649 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
26051 /* 71654 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26052 /* 71657 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26053 /* 71660 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26054 /* 71663 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26055 /* 71666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26056 /* 71670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26057 /* 71674 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26058 /* 71678 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26059 /* 71682 */ // (intrinsic_wo_chain:{ *:[i32] } 3808:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
26060 /* 71682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32),
26061 /* 71685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26062 /* 71687 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26063 /* 71689 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26064 /* 71691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26065 /* 71694 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26066 /* 71700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26067 /* 71706 */ GIR_RootConstrainSelectedInstOperands,
26068 /* 71707 */ // GIR_Coverage, 3508,
26069 /* 71707 */ GIR_EraseRootFromParent_Done,
26070 /* 71708 */ // Label 1491: @71708
26071 /* 71708 */ GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(71775), // Rule ID 3510 //
26072 /* 71713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26073 /* 71716 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
26074 /* 71721 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26075 /* 71724 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26076 /* 71727 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26077 /* 71730 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26078 /* 71733 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26079 /* 71737 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26080 /* 71741 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26081 /* 71745 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26082 /* 71749 */ // (intrinsic_wo_chain:{ *:[i32] } 3799:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
26083 /* 71749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8),
26084 /* 71752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26085 /* 71754 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26086 /* 71756 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26087 /* 71758 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26088 /* 71761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26089 /* 71767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26090 /* 71773 */ GIR_RootConstrainSelectedInstOperands,
26091 /* 71774 */ // GIR_Coverage, 3510,
26092 /* 71774 */ GIR_EraseRootFromParent_Done,
26093 /* 71775 */ // Label 1492: @71775
26094 /* 71775 */ GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(71842), // Rule ID 3512 //
26095 /* 71780 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26096 /* 71783 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
26097 /* 71788 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26098 /* 71791 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26099 /* 71794 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26100 /* 71797 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26101 /* 71800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26102 /* 71804 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26103 /* 71808 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26104 /* 71812 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26105 /* 71816 */ // (intrinsic_wo_chain:{ *:[i32] } 3799:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
26106 /* 71816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16),
26107 /* 71819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26108 /* 71821 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26109 /* 71823 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26110 /* 71825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26111 /* 71828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26112 /* 71834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26113 /* 71840 */ GIR_RootConstrainSelectedInstOperands,
26114 /* 71841 */ // GIR_Coverage, 3512,
26115 /* 71841 */ GIR_EraseRootFromParent_Done,
26116 /* 71842 */ // Label 1493: @71842
26117 /* 71842 */ GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(71909), // Rule ID 3514 //
26118 /* 71847 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26119 /* 71850 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
26120 /* 71855 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26121 /* 71858 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26122 /* 71861 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26123 /* 71864 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26124 /* 71867 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26125 /* 71871 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26126 /* 71875 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26127 /* 71879 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26128 /* 71883 */ // (intrinsic_wo_chain:{ *:[i32] } 3799:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
26129 /* 71883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32),
26130 /* 71886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26131 /* 71888 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26132 /* 71890 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26133 /* 71892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26134 /* 71895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26135 /* 71901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26136 /* 71907 */ GIR_RootConstrainSelectedInstOperands,
26137 /* 71908 */ // GIR_Coverage, 3514,
26138 /* 71908 */ GIR_EraseRootFromParent_Done,
26139 /* 71909 */ // Label 1494: @71909
26140 /* 71909 */ GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(71976), // Rule ID 3516 //
26141 /* 71914 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26142 /* 71917 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
26143 /* 71922 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26144 /* 71925 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26145 /* 71928 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26146 /* 71931 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26147 /* 71934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26148 /* 71938 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26149 /* 71942 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26150 /* 71946 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26151 /* 71950 */ // (intrinsic_wo_chain:{ *:[i32] } 3799:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
26152 /* 71950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8),
26153 /* 71953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26154 /* 71955 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26155 /* 71957 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26156 /* 71959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26157 /* 71962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26158 /* 71968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26159 /* 71974 */ GIR_RootConstrainSelectedInstOperands,
26160 /* 71975 */ // GIR_Coverage, 3516,
26161 /* 71975 */ GIR_EraseRootFromParent_Done,
26162 /* 71976 */ // Label 1495: @71976
26163 /* 71976 */ GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(72043), // Rule ID 3518 //
26164 /* 71981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26165 /* 71984 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
26166 /* 71989 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26167 /* 71992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26168 /* 71995 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26169 /* 71998 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26170 /* 72001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26171 /* 72005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26172 /* 72009 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26173 /* 72013 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26174 /* 72017 */ // (intrinsic_wo_chain:{ *:[i32] } 3799:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
26175 /* 72017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16),
26176 /* 72020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26177 /* 72022 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26178 /* 72024 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26179 /* 72026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26180 /* 72029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26181 /* 72035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26182 /* 72041 */ GIR_RootConstrainSelectedInstOperands,
26183 /* 72042 */ // GIR_Coverage, 3518,
26184 /* 72042 */ GIR_EraseRootFromParent_Done,
26185 /* 72043 */ // Label 1496: @72043
26186 /* 72043 */ GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(72110), // Rule ID 3520 //
26187 /* 72048 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26188 /* 72051 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
26189 /* 72056 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26190 /* 72059 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26191 /* 72062 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26192 /* 72065 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26193 /* 72068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26194 /* 72072 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26195 /* 72076 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26196 /* 72080 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26197 /* 72084 */ // (intrinsic_wo_chain:{ *:[i32] } 3799:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
26198 /* 72084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32),
26199 /* 72087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26200 /* 72089 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26201 /* 72091 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26202 /* 72093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26203 /* 72096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26204 /* 72102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26205 /* 72108 */ GIR_RootConstrainSelectedInstOperands,
26206 /* 72109 */ // GIR_Coverage, 3520,
26207 /* 72109 */ GIR_EraseRootFromParent_Done,
26208 /* 72110 */ // Label 1497: @72110
26209 /* 72110 */ GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(72192), // Rule ID 3931 //
26210 /* 72115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26211 /* 72118 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26212 /* 72123 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26213 /* 72126 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26214 /* 72129 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26215 /* 72132 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26216 /* 72135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26217 /* 72139 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26218 /* 72143 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26219 /* 72147 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26220 /* 72151 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3845:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26221 /* 72151 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26222 /* 72154 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26223 /* 72158 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26224 /* 72163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8),
26225 /* 72166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26226 /* 72168 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26227 /* 72170 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26228 /* 72172 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26229 /* 72175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26230 /* 72181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26231 /* 72187 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26232 /* 72190 */ GIR_RootConstrainSelectedInstOperands,
26233 /* 72191 */ // GIR_Coverage, 3931,
26234 /* 72191 */ GIR_EraseRootFromParent_Done,
26235 /* 72192 */ // Label 1498: @72192
26236 /* 72192 */ GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(72274), // Rule ID 3938 //
26237 /* 72197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26238 /* 72200 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26239 /* 72205 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26240 /* 72208 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26241 /* 72211 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26242 /* 72214 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26243 /* 72217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26244 /* 72221 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26245 /* 72225 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26246 /* 72229 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26247 /* 72233 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3845:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26248 /* 72233 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26249 /* 72236 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26250 /* 72240 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26251 /* 72245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16),
26252 /* 72248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26253 /* 72250 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26254 /* 72252 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26255 /* 72254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26256 /* 72257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26257 /* 72263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26258 /* 72269 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26259 /* 72272 */ GIR_RootConstrainSelectedInstOperands,
26260 /* 72273 */ // GIR_Coverage, 3938,
26261 /* 72273 */ GIR_EraseRootFromParent_Done,
26262 /* 72274 */ // Label 1499: @72274
26263 /* 72274 */ GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(72356), // Rule ID 3942 //
26264 /* 72279 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26265 /* 72282 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26266 /* 72287 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26267 /* 72290 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26268 /* 72293 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26269 /* 72296 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26270 /* 72299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26271 /* 72303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26272 /* 72307 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26273 /* 72311 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26274 /* 72315 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3845:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26275 /* 72315 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26276 /* 72318 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26277 /* 72322 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26278 /* 72327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32),
26279 /* 72330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26280 /* 72332 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26281 /* 72334 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26282 /* 72336 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26283 /* 72339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26284 /* 72345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26285 /* 72351 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26286 /* 72354 */ GIR_RootConstrainSelectedInstOperands,
26287 /* 72355 */ // GIR_Coverage, 3942,
26288 /* 72355 */ GIR_EraseRootFromParent_Done,
26289 /* 72356 */ // Label 1500: @72356
26290 /* 72356 */ GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(72438), // Rule ID 3946 //
26291 /* 72361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26292 /* 72364 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26293 /* 72369 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26294 /* 72372 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26295 /* 72375 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26296 /* 72378 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26297 /* 72381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26298 /* 72385 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26299 /* 72389 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26300 /* 72393 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26301 /* 72397 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3845:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26302 /* 72397 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26303 /* 72400 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26304 /* 72404 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26305 /* 72409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8),
26306 /* 72412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26307 /* 72414 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26308 /* 72416 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26309 /* 72418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26310 /* 72421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26311 /* 72427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26312 /* 72433 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26313 /* 72436 */ GIR_RootConstrainSelectedInstOperands,
26314 /* 72437 */ // GIR_Coverage, 3946,
26315 /* 72437 */ GIR_EraseRootFromParent_Done,
26316 /* 72438 */ // Label 1501: @72438
26317 /* 72438 */ GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(72520), // Rule ID 3950 //
26318 /* 72443 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26319 /* 72446 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26320 /* 72451 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26321 /* 72454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26322 /* 72457 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26323 /* 72460 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26324 /* 72463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26325 /* 72467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26326 /* 72471 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26327 /* 72475 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26328 /* 72479 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3845:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26329 /* 72479 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26330 /* 72482 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26331 /* 72486 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26332 /* 72491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16),
26333 /* 72494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26334 /* 72496 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26335 /* 72498 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26336 /* 72500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26337 /* 72503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26338 /* 72509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26339 /* 72515 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26340 /* 72518 */ GIR_RootConstrainSelectedInstOperands,
26341 /* 72519 */ // GIR_Coverage, 3950,
26342 /* 72519 */ GIR_EraseRootFromParent_Done,
26343 /* 72520 */ // Label 1502: @72520
26344 /* 72520 */ GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(72602), // Rule ID 3954 //
26345 /* 72525 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26346 /* 72528 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26347 /* 72533 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26348 /* 72536 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26349 /* 72539 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26350 /* 72542 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26351 /* 72545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26352 /* 72549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26353 /* 72553 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26354 /* 72557 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26355 /* 72561 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3845:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26356 /* 72561 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26357 /* 72564 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26358 /* 72568 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26359 /* 72573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32),
26360 /* 72576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26361 /* 72578 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26362 /* 72580 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26363 /* 72582 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26364 /* 72585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26365 /* 72591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26366 /* 72597 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26367 /* 72600 */ GIR_RootConstrainSelectedInstOperands,
26368 /* 72601 */ // GIR_Coverage, 3954,
26369 /* 72601 */ GIR_EraseRootFromParent_Done,
26370 /* 72602 */ // Label 1503: @72602
26371 /* 72602 */ GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(72684), // Rule ID 3955 //
26372 /* 72607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26373 /* 72610 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
26374 /* 72615 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26375 /* 72618 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26376 /* 72621 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26377 /* 72624 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26378 /* 72627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26379 /* 72631 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26380 /* 72635 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26381 /* 72639 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26382 /* 72643 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3937:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26383 /* 72643 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26384 /* 72646 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26385 /* 72650 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26386 /* 72655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8),
26387 /* 72658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26388 /* 72660 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26389 /* 72662 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26390 /* 72664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26391 /* 72667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26392 /* 72673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26393 /* 72679 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26394 /* 72682 */ GIR_RootConstrainSelectedInstOperands,
26395 /* 72683 */ // GIR_Coverage, 3955,
26396 /* 72683 */ GIR_EraseRootFromParent_Done,
26397 /* 72684 */ // Label 1504: @72684
26398 /* 72684 */ GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(72766), // Rule ID 3962 //
26399 /* 72689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26400 /* 72692 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
26401 /* 72697 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26402 /* 72700 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26403 /* 72703 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26404 /* 72706 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26405 /* 72709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26406 /* 72713 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26407 /* 72717 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26408 /* 72721 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26409 /* 72725 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3937:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26410 /* 72725 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26411 /* 72728 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26412 /* 72732 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26413 /* 72737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16),
26414 /* 72740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26415 /* 72742 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26416 /* 72744 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26417 /* 72746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26418 /* 72749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26419 /* 72755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26420 /* 72761 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26421 /* 72764 */ GIR_RootConstrainSelectedInstOperands,
26422 /* 72765 */ // GIR_Coverage, 3962,
26423 /* 72765 */ GIR_EraseRootFromParent_Done,
26424 /* 72766 */ // Label 1505: @72766
26425 /* 72766 */ GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(72848), // Rule ID 3966 //
26426 /* 72771 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26427 /* 72774 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
26428 /* 72779 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26429 /* 72782 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26430 /* 72785 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26431 /* 72788 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26432 /* 72791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26433 /* 72795 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26434 /* 72799 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26435 /* 72803 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26436 /* 72807 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3937:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26437 /* 72807 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26438 /* 72810 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26439 /* 72814 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26440 /* 72819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32),
26441 /* 72822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26442 /* 72824 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26443 /* 72826 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26444 /* 72828 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26445 /* 72831 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26446 /* 72837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26447 /* 72843 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26448 /* 72846 */ GIR_RootConstrainSelectedInstOperands,
26449 /* 72847 */ // GIR_Coverage, 3966,
26450 /* 72847 */ GIR_EraseRootFromParent_Done,
26451 /* 72848 */ // Label 1506: @72848
26452 /* 72848 */ GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(72930), // Rule ID 3970 //
26453 /* 72853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26454 /* 72856 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
26455 /* 72861 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26456 /* 72864 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26457 /* 72867 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26458 /* 72870 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26459 /* 72873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26460 /* 72877 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26461 /* 72881 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26462 /* 72885 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26463 /* 72889 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3937:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26464 /* 72889 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26465 /* 72892 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26466 /* 72896 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26467 /* 72901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8),
26468 /* 72904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26469 /* 72906 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26470 /* 72908 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26471 /* 72910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26472 /* 72913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26473 /* 72919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26474 /* 72925 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26475 /* 72928 */ GIR_RootConstrainSelectedInstOperands,
26476 /* 72929 */ // GIR_Coverage, 3970,
26477 /* 72929 */ GIR_EraseRootFromParent_Done,
26478 /* 72930 */ // Label 1507: @72930
26479 /* 72930 */ GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(73012), // Rule ID 3974 //
26480 /* 72935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26481 /* 72938 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
26482 /* 72943 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26483 /* 72946 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26484 /* 72949 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26485 /* 72952 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26486 /* 72955 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26487 /* 72959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26488 /* 72963 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26489 /* 72967 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26490 /* 72971 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3937:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26491 /* 72971 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26492 /* 72974 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26493 /* 72978 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26494 /* 72983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16),
26495 /* 72986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26496 /* 72988 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26497 /* 72990 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26498 /* 72992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26499 /* 72995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26500 /* 73001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26501 /* 73007 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26502 /* 73010 */ GIR_RootConstrainSelectedInstOperands,
26503 /* 73011 */ // GIR_Coverage, 3974,
26504 /* 73011 */ GIR_EraseRootFromParent_Done,
26505 /* 73012 */ // Label 1508: @73012
26506 /* 73012 */ GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(73094), // Rule ID 3978 //
26507 /* 73017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26508 /* 73020 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
26509 /* 73025 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26510 /* 73028 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26511 /* 73031 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26512 /* 73034 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26513 /* 73037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26514 /* 73041 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26515 /* 73045 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26516 /* 73049 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26517 /* 73053 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3937:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26518 /* 73053 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26519 /* 73056 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26520 /* 73060 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26521 /* 73065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32),
26522 /* 73068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26523 /* 73070 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26524 /* 73072 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26525 /* 73074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26526 /* 73077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26527 /* 73083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26528 /* 73089 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26529 /* 73092 */ GIR_RootConstrainSelectedInstOperands,
26530 /* 73093 */ // GIR_Coverage, 3978,
26531 /* 73093 */ GIR_EraseRootFromParent_Done,
26532 /* 73094 */ // Label 1509: @73094
26533 /* 73094 */ GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(73176), // Rule ID 3979 //
26534 /* 73099 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26535 /* 73102 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
26536 /* 73107 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26537 /* 73110 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26538 /* 73113 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26539 /* 73116 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26540 /* 73119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26541 /* 73123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26542 /* 73127 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26543 /* 73131 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26544 /* 73135 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3883:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26545 /* 73135 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26546 /* 73138 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26547 /* 73142 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26548 /* 73147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8),
26549 /* 73150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26550 /* 73152 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26551 /* 73154 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26552 /* 73156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26553 /* 73159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26554 /* 73165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26555 /* 73171 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26556 /* 73174 */ GIR_RootConstrainSelectedInstOperands,
26557 /* 73175 */ // GIR_Coverage, 3979,
26558 /* 73175 */ GIR_EraseRootFromParent_Done,
26559 /* 73176 */ // Label 1510: @73176
26560 /* 73176 */ GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(73258), // Rule ID 3986 //
26561 /* 73181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26562 /* 73184 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
26563 /* 73189 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26564 /* 73192 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26565 /* 73195 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26566 /* 73198 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26567 /* 73201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26568 /* 73205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26569 /* 73209 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26570 /* 73213 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26571 /* 73217 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3883:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26572 /* 73217 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26573 /* 73220 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26574 /* 73224 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26575 /* 73229 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16),
26576 /* 73232 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26577 /* 73234 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26578 /* 73236 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26579 /* 73238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26580 /* 73241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26581 /* 73247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26582 /* 73253 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26583 /* 73256 */ GIR_RootConstrainSelectedInstOperands,
26584 /* 73257 */ // GIR_Coverage, 3986,
26585 /* 73257 */ GIR_EraseRootFromParent_Done,
26586 /* 73258 */ // Label 1511: @73258
26587 /* 73258 */ GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(73340), // Rule ID 3990 //
26588 /* 73263 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26589 /* 73266 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
26590 /* 73271 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26591 /* 73274 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26592 /* 73277 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26593 /* 73280 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26594 /* 73283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26595 /* 73287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26596 /* 73291 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26597 /* 73295 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26598 /* 73299 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3883:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26599 /* 73299 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26600 /* 73302 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26601 /* 73306 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26602 /* 73311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32),
26603 /* 73314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26604 /* 73316 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26605 /* 73318 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26606 /* 73320 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26607 /* 73323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26608 /* 73329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26609 /* 73335 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26610 /* 73338 */ GIR_RootConstrainSelectedInstOperands,
26611 /* 73339 */ // GIR_Coverage, 3990,
26612 /* 73339 */ GIR_EraseRootFromParent_Done,
26613 /* 73340 */ // Label 1512: @73340
26614 /* 73340 */ GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(73422), // Rule ID 3994 //
26615 /* 73345 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26616 /* 73348 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
26617 /* 73353 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26618 /* 73356 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26619 /* 73359 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26620 /* 73362 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26621 /* 73365 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26622 /* 73369 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26623 /* 73373 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26624 /* 73377 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26625 /* 73381 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3883:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26626 /* 73381 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26627 /* 73384 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26628 /* 73388 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26629 /* 73393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8),
26630 /* 73396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26631 /* 73398 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26632 /* 73400 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26633 /* 73402 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26634 /* 73405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26635 /* 73411 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26636 /* 73417 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26637 /* 73420 */ GIR_RootConstrainSelectedInstOperands,
26638 /* 73421 */ // GIR_Coverage, 3994,
26639 /* 73421 */ GIR_EraseRootFromParent_Done,
26640 /* 73422 */ // Label 1513: @73422
26641 /* 73422 */ GIM_Try, /*On fail goto*//*Label 1514*/ GIMT_Encode4(73504), // Rule ID 3998 //
26642 /* 73427 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26643 /* 73430 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
26644 /* 73435 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26645 /* 73438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26646 /* 73441 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26647 /* 73444 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26648 /* 73447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26649 /* 73451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26650 /* 73455 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26651 /* 73459 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26652 /* 73463 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3883:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26653 /* 73463 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26654 /* 73466 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26655 /* 73470 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26656 /* 73475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16),
26657 /* 73478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26658 /* 73480 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26659 /* 73482 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26660 /* 73484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26661 /* 73487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26662 /* 73493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26663 /* 73499 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26664 /* 73502 */ GIR_RootConstrainSelectedInstOperands,
26665 /* 73503 */ // GIR_Coverage, 3998,
26666 /* 73503 */ GIR_EraseRootFromParent_Done,
26667 /* 73504 */ // Label 1514: @73504
26668 /* 73504 */ GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(73586), // Rule ID 4002 //
26669 /* 73509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26670 /* 73512 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
26671 /* 73517 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26672 /* 73520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26673 /* 73523 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26674 /* 73526 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26675 /* 73529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26676 /* 73533 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26677 /* 73537 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26678 /* 73541 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26679 /* 73545 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3883:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26680 /* 73545 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26681 /* 73548 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26682 /* 73552 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26683 /* 73557 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32),
26684 /* 73560 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26685 /* 73562 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26686 /* 73564 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26687 /* 73566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26688 /* 73569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26689 /* 73575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26690 /* 73581 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26691 /* 73584 */ GIR_RootConstrainSelectedInstOperands,
26692 /* 73585 */ // GIR_Coverage, 4002,
26693 /* 73585 */ GIR_EraseRootFromParent_Done,
26694 /* 73586 */ // Label 1515: @73586
26695 /* 73586 */ GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(73668), // Rule ID 4003 //
26696 /* 73591 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26697 /* 73594 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
26698 /* 73599 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26699 /* 73602 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26700 /* 73605 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26701 /* 73608 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26702 /* 73611 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26703 /* 73615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26704 /* 73619 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26705 /* 73623 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26706 /* 73627 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3884:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26707 /* 73627 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26708 /* 73630 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26709 /* 73634 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26710 /* 73639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs8),
26711 /* 73642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26712 /* 73644 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26713 /* 73646 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26714 /* 73648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26715 /* 73651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26716 /* 73657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26717 /* 73663 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26718 /* 73666 */ GIR_RootConstrainSelectedInstOperands,
26719 /* 73667 */ // GIR_Coverage, 4003,
26720 /* 73667 */ GIR_EraseRootFromParent_Done,
26721 /* 73668 */ // Label 1516: @73668
26722 /* 73668 */ GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(73750), // Rule ID 4006 //
26723 /* 73673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26724 /* 73676 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
26725 /* 73681 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26726 /* 73684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26727 /* 73687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26728 /* 73690 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26729 /* 73693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26730 /* 73697 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26731 /* 73701 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26732 /* 73705 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26733 /* 73709 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3884:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26734 /* 73709 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26735 /* 73712 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26736 /* 73716 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26737 /* 73721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs16),
26738 /* 73724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26739 /* 73726 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26740 /* 73728 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26741 /* 73730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26742 /* 73733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26743 /* 73739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26744 /* 73745 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26745 /* 73748 */ GIR_RootConstrainSelectedInstOperands,
26746 /* 73749 */ // GIR_Coverage, 4006,
26747 /* 73749 */ GIR_EraseRootFromParent_Done,
26748 /* 73750 */ // Label 1517: @73750
26749 /* 73750 */ GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(73832), // Rule ID 4009 //
26750 /* 73755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26751 /* 73758 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
26752 /* 73763 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26753 /* 73766 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26754 /* 73769 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26755 /* 73772 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26756 /* 73775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26757 /* 73779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26758 /* 73783 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26759 /* 73787 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26760 /* 73791 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3884:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26761 /* 73791 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26762 /* 73794 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26763 /* 73798 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26764 /* 73803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs32),
26765 /* 73806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26766 /* 73808 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26767 /* 73810 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26768 /* 73812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26769 /* 73815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26770 /* 73821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26771 /* 73827 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26772 /* 73830 */ GIR_RootConstrainSelectedInstOperands,
26773 /* 73831 */ // GIR_Coverage, 4009,
26774 /* 73831 */ GIR_EraseRootFromParent_Done,
26775 /* 73832 */ // Label 1518: @73832
26776 /* 73832 */ GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(73914), // Rule ID 4012 //
26777 /* 73837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26778 /* 73840 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
26779 /* 73845 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26780 /* 73848 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26781 /* 73851 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26782 /* 73854 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26783 /* 73857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26784 /* 73861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26785 /* 73865 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26786 /* 73869 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26787 /* 73873 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3884:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26788 /* 73873 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26789 /* 73876 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26790 /* 73880 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26791 /* 73885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu8),
26792 /* 73888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26793 /* 73890 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26794 /* 73892 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26795 /* 73894 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26796 /* 73897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26797 /* 73903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26798 /* 73909 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26799 /* 73912 */ GIR_RootConstrainSelectedInstOperands,
26800 /* 73913 */ // GIR_Coverage, 4012,
26801 /* 73913 */ GIR_EraseRootFromParent_Done,
26802 /* 73914 */ // Label 1519: @73914
26803 /* 73914 */ GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(73996), // Rule ID 4015 //
26804 /* 73919 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26805 /* 73922 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
26806 /* 73927 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26807 /* 73930 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26808 /* 73933 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26809 /* 73936 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26810 /* 73939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26811 /* 73943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26812 /* 73947 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26813 /* 73951 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26814 /* 73955 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3884:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26815 /* 73955 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26816 /* 73958 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26817 /* 73962 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26818 /* 73967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu16),
26819 /* 73970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26820 /* 73972 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26821 /* 73974 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26822 /* 73976 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26823 /* 73979 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26824 /* 73985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26825 /* 73991 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26826 /* 73994 */ GIR_RootConstrainSelectedInstOperands,
26827 /* 73995 */ // GIR_Coverage, 4015,
26828 /* 73995 */ GIR_EraseRootFromParent_Done,
26829 /* 73996 */ // Label 1520: @73996
26830 /* 73996 */ GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(74078), // Rule ID 4018 //
26831 /* 74001 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26832 /* 74004 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
26833 /* 74009 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26834 /* 74012 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26835 /* 74015 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26836 /* 74018 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26837 /* 74021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26838 /* 74025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26839 /* 74029 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26840 /* 74033 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26841 /* 74037 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3884:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26842 /* 74037 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26843 /* 74040 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26844 /* 74044 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26845 /* 74049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu32),
26846 /* 74052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26847 /* 74054 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26848 /* 74056 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26849 /* 74058 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26850 /* 74061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26851 /* 74067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26852 /* 74073 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26853 /* 74076 */ GIR_RootConstrainSelectedInstOperands,
26854 /* 74077 */ // GIR_Coverage, 4018,
26855 /* 74077 */ GIR_EraseRootFromParent_Done,
26856 /* 74078 */ // Label 1521: @74078
26857 /* 74078 */ GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(74160), // Rule ID 4467 //
26858 /* 74083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
26859 /* 74086 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26860 /* 74091 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26861 /* 74094 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26862 /* 74097 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26863 /* 74100 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26864 /* 74103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26865 /* 74107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26866 /* 74111 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26867 /* 74115 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26868 /* 74119 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3845:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
26869 /* 74119 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26870 /* 74122 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26871 /* 74126 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26872 /* 74131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32),
26873 /* 74134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26874 /* 74136 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26875 /* 74138 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26876 /* 74140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26877 /* 74143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26878 /* 74149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26879 /* 74155 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26880 /* 74158 */ GIR_RootConstrainSelectedInstOperands,
26881 /* 74159 */ // GIR_Coverage, 4467,
26882 /* 74159 */ GIR_EraseRootFromParent_Done,
26883 /* 74160 */ // Label 1522: @74160
26884 /* 74160 */ GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(74242), // Rule ID 4469 //
26885 /* 74165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
26886 /* 74168 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26887 /* 74173 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26888 /* 74176 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26889 /* 74179 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26890 /* 74182 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26891 /* 74185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26892 /* 74189 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26893 /* 74193 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26894 /* 74197 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26895 /* 74201 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3845:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
26896 /* 74201 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26897 /* 74204 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26898 /* 74208 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26899 /* 74213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16),
26900 /* 74216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26901 /* 74218 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26902 /* 74220 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26903 /* 74222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26904 /* 74225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26905 /* 74231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26906 /* 74237 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26907 /* 74240 */ GIR_RootConstrainSelectedInstOperands,
26908 /* 74241 */ // GIR_Coverage, 4469,
26909 /* 74241 */ GIR_EraseRootFromParent_Done,
26910 /* 74242 */ // Label 1523: @74242
26911 /* 74242 */ GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(74324), // Rule ID 4902 //
26912 /* 74247 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26913 /* 74250 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly),
26914 /* 74255 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26915 /* 74258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26916 /* 74261 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26917 /* 74264 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26918 /* 74267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26919 /* 74271 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26920 /* 74275 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26921 /* 74279 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26922 /* 74283 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3914:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26923 /* 74283 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26924 /* 74286 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26925 /* 74290 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26926 /* 74295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp8),
26927 /* 74298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26928 /* 74300 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26929 /* 74302 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26930 /* 74304 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26931 /* 74307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26932 /* 74313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26933 /* 74319 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26934 /* 74322 */ GIR_RootConstrainSelectedInstOperands,
26935 /* 74323 */ // GIR_Coverage, 4902,
26936 /* 74323 */ GIR_EraseRootFromParent_Done,
26937 /* 74324 */ // Label 1524: @74324
26938 /* 74324 */ GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(74406), // Rule ID 4904 //
26939 /* 74329 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26940 /* 74332 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly),
26941 /* 74337 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26942 /* 74340 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26943 /* 74343 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26944 /* 74346 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26945 /* 74349 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26946 /* 74353 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26947 /* 74357 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26948 /* 74361 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26949 /* 74365 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3914:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26950 /* 74365 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26951 /* 74368 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26952 /* 74372 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26953 /* 74377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp8),
26954 /* 74380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26955 /* 74382 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26956 /* 74384 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26957 /* 74386 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26958 /* 74389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26959 /* 74395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26960 /* 74401 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26961 /* 74404 */ GIR_RootConstrainSelectedInstOperands,
26962 /* 74405 */ // GIR_Coverage, 4904,
26963 /* 74405 */ GIR_EraseRootFromParent_Done,
26964 /* 74406 */ // Label 1525: @74406
26965 /* 74406 */ GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(74488), // Rule ID 4906 //
26966 /* 74411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26967 /* 74414 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly),
26968 /* 74419 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26969 /* 74422 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26970 /* 74425 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26971 /* 74428 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26972 /* 74431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26973 /* 74435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26974 /* 74439 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26975 /* 74443 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26976 /* 74447 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3914:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26977 /* 74447 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26978 /* 74450 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26979 /* 74454 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26980 /* 74459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp16),
26981 /* 74462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26982 /* 74464 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26983 /* 74466 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26984 /* 74468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26985 /* 74471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26986 /* 74477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26987 /* 74483 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26988 /* 74486 */ GIR_RootConstrainSelectedInstOperands,
26989 /* 74487 */ // GIR_Coverage, 4906,
26990 /* 74487 */ GIR_EraseRootFromParent_Done,
26991 /* 74488 */ // Label 1526: @74488
26992 /* 74488 */ GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(74570), // Rule ID 4908 //
26993 /* 74493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26994 /* 74496 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly),
26995 /* 74501 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26996 /* 74504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26997 /* 74507 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26998 /* 74510 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26999 /* 74513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27000 /* 74517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27001 /* 74521 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27002 /* 74525 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27003 /* 74529 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3914:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
27004 /* 74529 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27005 /* 74532 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27006 /* 74536 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27007 /* 74541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp16),
27008 /* 74544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27009 /* 74546 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27010 /* 74548 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27011 /* 74550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27012 /* 74553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27013 /* 74559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27014 /* 74565 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27015 /* 74568 */ GIR_RootConstrainSelectedInstOperands,
27016 /* 74569 */ // GIR_Coverage, 4908,
27017 /* 74569 */ GIR_EraseRootFromParent_Done,
27018 /* 74570 */ // Label 1527: @74570
27019 /* 74570 */ GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(74652), // Rule ID 4935 //
27020 /* 74575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27021 /* 74578 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
27022 /* 74583 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
27023 /* 74586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27024 /* 74589 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27025 /* 74592 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27026 /* 74595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27027 /* 74599 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27028 /* 74603 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27029 /* 74607 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27030 /* 74611 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3912:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
27031 /* 74611 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27032 /* 74614 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27033 /* 74618 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27034 /* 74623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8),
27035 /* 74626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27036 /* 74628 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27037 /* 74630 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27038 /* 74632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27039 /* 74635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27040 /* 74641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27041 /* 74647 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27042 /* 74650 */ GIR_RootConstrainSelectedInstOperands,
27043 /* 74651 */ // GIR_Coverage, 4935,
27044 /* 74651 */ GIR_EraseRootFromParent_Done,
27045 /* 74652 */ // Label 1528: @74652
27046 /* 74652 */ GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(74734), // Rule ID 4942 //
27047 /* 74657 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27048 /* 74660 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
27049 /* 74665 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27050 /* 74668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27051 /* 74671 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27052 /* 74674 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27053 /* 74677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27054 /* 74681 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27055 /* 74685 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27056 /* 74689 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27057 /* 74693 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3912:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
27058 /* 74693 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27059 /* 74696 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27060 /* 74700 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27061 /* 74705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16),
27062 /* 74708 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27063 /* 74710 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27064 /* 74712 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27065 /* 74714 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27066 /* 74717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27067 /* 74723 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27068 /* 74729 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27069 /* 74732 */ GIR_RootConstrainSelectedInstOperands,
27070 /* 74733 */ // GIR_Coverage, 4942,
27071 /* 74733 */ GIR_EraseRootFromParent_Done,
27072 /* 74734 */ // Label 1529: @74734
27073 /* 74734 */ GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(74816), // Rule ID 4946 //
27074 /* 74739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27075 /* 74742 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
27076 /* 74747 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27077 /* 74750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27078 /* 74753 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27079 /* 74756 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27080 /* 74759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27081 /* 74763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27082 /* 74767 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27083 /* 74771 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27084 /* 74775 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3912:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
27085 /* 74775 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27086 /* 74778 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27087 /* 74782 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27088 /* 74787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32),
27089 /* 74790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27090 /* 74792 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27091 /* 74794 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27092 /* 74796 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27093 /* 74799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27094 /* 74805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27095 /* 74811 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27096 /* 74814 */ GIR_RootConstrainSelectedInstOperands,
27097 /* 74815 */ // GIR_Coverage, 4946,
27098 /* 74815 */ GIR_EraseRootFromParent_Done,
27099 /* 74816 */ // Label 1530: @74816
27100 /* 74816 */ GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(74898), // Rule ID 4950 //
27101 /* 74821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27102 /* 74824 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
27103 /* 74829 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
27104 /* 74832 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27105 /* 74835 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27106 /* 74838 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27107 /* 74841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27108 /* 74845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27109 /* 74849 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27110 /* 74853 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27111 /* 74857 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3912:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
27112 /* 74857 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27113 /* 74860 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27114 /* 74864 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27115 /* 74869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8),
27116 /* 74872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27117 /* 74874 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27118 /* 74876 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27119 /* 74878 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27120 /* 74881 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27121 /* 74887 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27122 /* 74893 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27123 /* 74896 */ GIR_RootConstrainSelectedInstOperands,
27124 /* 74897 */ // GIR_Coverage, 4950,
27125 /* 74897 */ GIR_EraseRootFromParent_Done,
27126 /* 74898 */ // Label 1531: @74898
27127 /* 74898 */ GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(74980), // Rule ID 4954 //
27128 /* 74903 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27129 /* 74906 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
27130 /* 74911 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27131 /* 74914 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27132 /* 74917 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27133 /* 74920 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27134 /* 74923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27135 /* 74927 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27136 /* 74931 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27137 /* 74935 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27138 /* 74939 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3912:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
27139 /* 74939 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27140 /* 74942 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27141 /* 74946 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27142 /* 74951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16),
27143 /* 74954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27144 /* 74956 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27145 /* 74958 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27146 /* 74960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27147 /* 74963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27148 /* 74969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27149 /* 74975 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27150 /* 74978 */ GIR_RootConstrainSelectedInstOperands,
27151 /* 74979 */ // GIR_Coverage, 4954,
27152 /* 74979 */ GIR_EraseRootFromParent_Done,
27153 /* 74980 */ // Label 1532: @74980
27154 /* 74980 */ GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(75062), // Rule ID 4958 //
27155 /* 74985 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27156 /* 74988 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
27157 /* 74993 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27158 /* 74996 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27159 /* 74999 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27160 /* 75002 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27161 /* 75005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27162 /* 75009 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27163 /* 75013 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27164 /* 75017 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27165 /* 75021 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3912:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
27166 /* 75021 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27167 /* 75024 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27168 /* 75028 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27169 /* 75033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32),
27170 /* 75036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27171 /* 75038 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27172 /* 75040 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27173 /* 75042 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27174 /* 75045 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27175 /* 75051 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27176 /* 75057 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27177 /* 75060 */ GIR_RootConstrainSelectedInstOperands,
27178 /* 75061 */ // GIR_Coverage, 4958,
27179 /* 75061 */ GIR_EraseRootFromParent_Done,
27180 /* 75062 */ // Label 1533: @75062
27181 /* 75062 */ GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(75144), // Rule ID 4959 //
27182 /* 75067 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27183 /* 75070 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
27184 /* 75075 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
27185 /* 75078 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27186 /* 75081 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27187 /* 75084 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27188 /* 75087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27189 /* 75091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27190 /* 75095 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27191 /* 75099 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27192 /* 75103 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3952:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
27193 /* 75103 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27194 /* 75106 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27195 /* 75110 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27196 /* 75115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs8),
27197 /* 75118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27198 /* 75120 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27199 /* 75122 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27200 /* 75124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27201 /* 75127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27202 /* 75133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27203 /* 75139 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27204 /* 75142 */ GIR_RootConstrainSelectedInstOperands,
27205 /* 75143 */ // GIR_Coverage, 4959,
27206 /* 75143 */ GIR_EraseRootFromParent_Done,
27207 /* 75144 */ // Label 1534: @75144
27208 /* 75144 */ GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(75226), // Rule ID 4961 //
27209 /* 75149 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27210 /* 75152 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
27211 /* 75157 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27212 /* 75160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27213 /* 75163 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27214 /* 75166 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27215 /* 75169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27216 /* 75173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27217 /* 75177 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27218 /* 75181 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27219 /* 75185 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3952:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
27220 /* 75185 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27221 /* 75188 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27222 /* 75192 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27223 /* 75197 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs16),
27224 /* 75200 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27225 /* 75202 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27226 /* 75204 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27227 /* 75206 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27228 /* 75209 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27229 /* 75215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27230 /* 75221 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27231 /* 75224 */ GIR_RootConstrainSelectedInstOperands,
27232 /* 75225 */ // GIR_Coverage, 4961,
27233 /* 75225 */ GIR_EraseRootFromParent_Done,
27234 /* 75226 */ // Label 1535: @75226
27235 /* 75226 */ GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(75308), // Rule ID 4963 //
27236 /* 75231 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27237 /* 75234 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
27238 /* 75239 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27239 /* 75242 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27240 /* 75245 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27241 /* 75248 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27242 /* 75251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27243 /* 75255 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27244 /* 75259 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27245 /* 75263 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27246 /* 75267 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3952:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
27247 /* 75267 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27248 /* 75270 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27249 /* 75274 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27250 /* 75279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs32),
27251 /* 75282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27252 /* 75284 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27253 /* 75286 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27254 /* 75288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27255 /* 75291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27256 /* 75297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27257 /* 75303 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27258 /* 75306 */ GIR_RootConstrainSelectedInstOperands,
27259 /* 75307 */ // GIR_Coverage, 4963,
27260 /* 75307 */ GIR_EraseRootFromParent_Done,
27261 /* 75308 */ // Label 1536: @75308
27262 /* 75308 */ GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(75390), // Rule ID 4965 //
27263 /* 75313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27264 /* 75316 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
27265 /* 75321 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
27266 /* 75324 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27267 /* 75327 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27268 /* 75330 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27269 /* 75333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27270 /* 75337 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27271 /* 75341 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27272 /* 75345 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27273 /* 75349 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3952:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
27274 /* 75349 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27275 /* 75352 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27276 /* 75356 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27277 /* 75361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu8),
27278 /* 75364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27279 /* 75366 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27280 /* 75368 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27281 /* 75370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27282 /* 75373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27283 /* 75379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27284 /* 75385 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27285 /* 75388 */ GIR_RootConstrainSelectedInstOperands,
27286 /* 75389 */ // GIR_Coverage, 4965,
27287 /* 75389 */ GIR_EraseRootFromParent_Done,
27288 /* 75390 */ // Label 1537: @75390
27289 /* 75390 */ GIM_Try, /*On fail goto*//*Label 1538*/ GIMT_Encode4(75472), // Rule ID 4967 //
27290 /* 75395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27291 /* 75398 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
27292 /* 75403 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27293 /* 75406 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27294 /* 75409 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27295 /* 75412 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27296 /* 75415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27297 /* 75419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27298 /* 75423 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27299 /* 75427 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27300 /* 75431 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3952:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
27301 /* 75431 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27302 /* 75434 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27303 /* 75438 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27304 /* 75443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu16),
27305 /* 75446 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27306 /* 75448 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27307 /* 75450 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27308 /* 75452 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27309 /* 75455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27310 /* 75461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27311 /* 75467 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27312 /* 75470 */ GIR_RootConstrainSelectedInstOperands,
27313 /* 75471 */ // GIR_Coverage, 4967,
27314 /* 75471 */ GIR_EraseRootFromParent_Done,
27315 /* 75472 */ // Label 1538: @75472
27316 /* 75472 */ GIM_Try, /*On fail goto*//*Label 1539*/ GIMT_Encode4(75554), // Rule ID 4969 //
27317 /* 75477 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27318 /* 75480 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
27319 /* 75485 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27320 /* 75488 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27321 /* 75491 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27322 /* 75494 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27323 /* 75497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27324 /* 75501 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27325 /* 75505 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27326 /* 75509 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27327 /* 75513 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3952:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
27328 /* 75513 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27329 /* 75516 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27330 /* 75520 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27331 /* 75525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu32),
27332 /* 75528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27333 /* 75530 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27334 /* 75532 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27335 /* 75534 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27336 /* 75537 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27337 /* 75543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27338 /* 75549 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27339 /* 75552 */ GIR_RootConstrainSelectedInstOperands,
27340 /* 75553 */ // GIR_Coverage, 4969,
27341 /* 75553 */ GIR_EraseRootFromParent_Done,
27342 /* 75554 */ // Label 1539: @75554
27343 /* 75554 */ GIM_Try, /*On fail goto*//*Label 1540*/ GIMT_Encode4(75621), // Rule ID 5020 //
27344 /* 75559 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27345 /* 75562 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow),
27346 /* 75567 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27347 /* 75570 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27348 /* 75573 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27349 /* 75576 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27350 /* 75579 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27351 /* 75583 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27352 /* 75587 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27353 /* 75591 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27354 /* 75595 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3867:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf16f32bh:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
27355 /* 75595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32bh),
27356 /* 75598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27357 /* 75600 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
27358 /* 75602 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
27359 /* 75604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27360 /* 75607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27361 /* 75613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27362 /* 75619 */ GIR_RootConstrainSelectedInstOperands,
27363 /* 75620 */ // GIR_Coverage, 5020,
27364 /* 75620 */ GIR_EraseRootFromParent_Done,
27365 /* 75621 */ // Label 1540: @75621
27366 /* 75621 */ GIM_Try, /*On fail goto*//*Label 1541*/ GIMT_Encode4(75688), // Rule ID 5026 //
27367 /* 75626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27368 /* 75629 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow),
27369 /* 75634 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27370 /* 75637 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27371 /* 75640 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27372 /* 75643 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27373 /* 75646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27374 /* 75650 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27375 /* 75654 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27376 /* 75658 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27377 /* 75662 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3867:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf16f32th:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
27378 /* 75662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32th),
27379 /* 75665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27380 /* 75667 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
27381 /* 75669 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
27382 /* 75671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27383 /* 75674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27384 /* 75680 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27385 /* 75686 */ GIR_RootConstrainSelectedInstOperands,
27386 /* 75687 */ // GIR_Coverage, 5026,
27387 /* 75687 */ GIR_EraseRootFromParent_Done,
27388 /* 75688 */ // Label 1541: @75688
27389 /* 75688 */ GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(75770), // Rule ID 5044 //
27390 /* 75693 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27391 /* 75696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull),
27392 /* 75701 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27393 /* 75704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27394 /* 75707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27395 /* 75710 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27396 /* 75713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27397 /* 75717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27398 /* 75721 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27399 /* 75725 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27400 /* 75729 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3922:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
27401 /* 75729 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27402 /* 75732 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27403 /* 75736 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27404 /* 75741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16bh),
27405 /* 75744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27406 /* 75746 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27407 /* 75748 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27408 /* 75750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27409 /* 75753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27410 /* 75759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27411 /* 75765 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27412 /* 75768 */ GIR_RootConstrainSelectedInstOperands,
27413 /* 75769 */ // GIR_Coverage, 5044,
27414 /* 75769 */ GIR_EraseRootFromParent_Done,
27415 /* 75770 */ // Label 1542: @75770
27416 /* 75770 */ GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(75852), // Rule ID 5046 //
27417 /* 75775 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27418 /* 75778 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull),
27419 /* 75783 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27420 /* 75786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27421 /* 75789 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27422 /* 75792 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27423 /* 75795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27424 /* 75799 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27425 /* 75803 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27426 /* 75807 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27427 /* 75811 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3922:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
27428 /* 75811 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27429 /* 75814 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27430 /* 75818 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27431 /* 75823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16th),
27432 /* 75826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27433 /* 75828 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27434 /* 75830 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27435 /* 75832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27436 /* 75835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27437 /* 75841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27438 /* 75847 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27439 /* 75850 */ GIR_RootConstrainSelectedInstOperands,
27440 /* 75851 */ // GIR_Coverage, 5046,
27441 /* 75851 */ GIR_EraseRootFromParent_Done,
27442 /* 75852 */ // Label 1543: @75852
27443 /* 75852 */ GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(75934), // Rule ID 5048 //
27444 /* 75857 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27445 /* 75860 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull),
27446 /* 75865 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
27447 /* 75868 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27448 /* 75871 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27449 /* 75874 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27450 /* 75877 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27451 /* 75881 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27452 /* 75885 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27453 /* 75889 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27454 /* 75893 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3922:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs32bh:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
27455 /* 75893 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27456 /* 75896 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27457 /* 75900 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27458 /* 75905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32bh),
27459 /* 75908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27460 /* 75910 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27461 /* 75912 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27462 /* 75914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27463 /* 75917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27464 /* 75923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27465 /* 75929 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27466 /* 75932 */ GIR_RootConstrainSelectedInstOperands,
27467 /* 75933 */ // GIR_Coverage, 5048,
27468 /* 75933 */ GIR_EraseRootFromParent_Done,
27469 /* 75934 */ // Label 1544: @75934
27470 /* 75934 */ GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(76016), // Rule ID 5050 //
27471 /* 75939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27472 /* 75942 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull),
27473 /* 75947 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
27474 /* 75950 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27475 /* 75953 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27476 /* 75956 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27477 /* 75959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27478 /* 75963 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27479 /* 75967 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27480 /* 75971 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27481 /* 75975 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3922:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs32th:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
27482 /* 75975 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27483 /* 75978 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27484 /* 75982 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27485 /* 75987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32th),
27486 /* 75990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27487 /* 75992 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27488 /* 75994 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27489 /* 75996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27490 /* 75999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27491 /* 76005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27492 /* 76011 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27493 /* 76014 */ GIR_RootConstrainSelectedInstOperands,
27494 /* 76015 */ // GIR_Coverage, 5050,
27495 /* 76015 */ GIR_EraseRootFromParent_Done,
27496 /* 76016 */ // Label 1545: @76016
27497 /* 76016 */ GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(76102), // Rule ID 4416 //
27498 /* 76021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27499 /* 76024 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
27500 /* 76029 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27501 /* 76032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27502 /* 76035 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27503 /* 76038 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27504 /* 76041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27505 /* 76045 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27506 /* 76049 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
27507 /* 76053 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
27508 /* 76057 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27509 /* 76062 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27510 /* 76066 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27511 /* 76070 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27512 /* 76072 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3787:{ *:[iPTR] }, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
27513 /* 76072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
27514 /* 76075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27515 /* 76077 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
27516 /* 76079 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
27517 /* 76083 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
27518 /* 76085 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27519 /* 76088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27520 /* 76094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27521 /* 76100 */ GIR_RootConstrainSelectedInstOperands,
27522 /* 76101 */ // GIR_Coverage, 4416,
27523 /* 76101 */ GIR_EraseRootFromParent_Done,
27524 /* 76102 */ // Label 1546: @76102
27525 /* 76102 */ GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(76188), // Rule ID 4430 //
27526 /* 76107 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27527 /* 76110 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
27528 /* 76115 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27529 /* 76118 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27530 /* 76121 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27531 /* 76124 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
27532 /* 76127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27533 /* 76131 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27534 /* 76135 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
27535 /* 76139 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
27536 /* 76143 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27537 /* 76148 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27538 /* 76152 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27539 /* 76156 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27540 /* 76158 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3787:{ *:[iPTR] }, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
27541 /* 76158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
27542 /* 76161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27543 /* 76163 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
27544 /* 76165 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
27545 /* 76169 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
27546 /* 76171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27547 /* 76174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27548 /* 76180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27549 /* 76186 */ GIR_RootConstrainSelectedInstOperands,
27550 /* 76187 */ // GIR_Coverage, 4430,
27551 /* 76187 */ GIR_EraseRootFromParent_Done,
27552 /* 76188 */ // Label 1547: @76188
27553 /* 76188 */ GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(76279), // Rule ID 4874 //
27554 /* 76193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27555 /* 76196 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq),
27556 /* 76201 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27557 /* 76204 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27558 /* 76207 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27559 /* 76210 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
27560 /* 76213 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27561 /* 76217 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27562 /* 76221 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27563 /* 76225 */ // MIs[1] Operand 1
27564 /* 76225 */ // No operand predicates
27565 /* 76225 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27566 /* 76229 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27567 /* 76233 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27568 /* 76235 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3856:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
27569 /* 76235 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27570 /* 76238 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27571 /* 76242 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27572 /* 76247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf16),
27573 /* 76250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27574 /* 76252 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27575 /* 76254 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm
27576 /* 76256 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
27577 /* 76259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27578 /* 76262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27579 /* 76268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27580 /* 76274 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27581 /* 76277 */ GIR_RootConstrainSelectedInstOperands,
27582 /* 76278 */ // GIR_Coverage, 4874,
27583 /* 76278 */ GIR_EraseRootFromParent_Done,
27584 /* 76279 */ // Label 1548: @76279
27585 /* 76279 */ GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(76370), // Rule ID 4876 //
27586 /* 76284 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27587 /* 76287 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq),
27588 /* 76292 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27589 /* 76295 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27590 /* 76298 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27591 /* 76301 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27592 /* 76304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27593 /* 76308 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27594 /* 76312 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27595 /* 76316 */ // MIs[1] Operand 1
27596 /* 76316 */ // No operand predicates
27597 /* 76316 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27598 /* 76320 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27599 /* 76324 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27600 /* 76326 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3856:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
27601 /* 76326 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27602 /* 76329 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27603 /* 76333 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27604 /* 76338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf32),
27605 /* 76341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27606 /* 76343 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27607 /* 76345 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm
27608 /* 76347 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
27609 /* 76350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27610 /* 76353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27611 /* 76359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27612 /* 76365 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27613 /* 76368 */ GIR_RootConstrainSelectedInstOperands,
27614 /* 76369 */ // GIR_Coverage, 4876,
27615 /* 76369 */ GIR_EraseRootFromParent_Done,
27616 /* 76370 */ // Label 1549: @76370
27617 /* 76370 */ GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(76456), // Rule ID 4417 //
27618 /* 76375 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27619 /* 76378 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
27620 /* 76383 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27621 /* 76386 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27622 /* 76389 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27623 /* 76392 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27624 /* 76395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27625 /* 76399 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27626 /* 76403 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
27627 /* 76407 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
27628 /* 76411 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
27629 /* 76415 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27630 /* 76420 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27631 /* 76424 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27632 /* 76426 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3787:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$m1, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m2), MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
27633 /* 76426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
27634 /* 76429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27635 /* 76431 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
27636 /* 76433 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
27637 /* 76435 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m2
27638 /* 76439 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27639 /* 76442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27640 /* 76448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27641 /* 76454 */ GIR_RootConstrainSelectedInstOperands,
27642 /* 76455 */ // GIR_Coverage, 4417,
27643 /* 76455 */ GIR_EraseRootFromParent_Done,
27644 /* 76456 */ // Label 1550: @76456
27645 /* 76456 */ GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(76542), // Rule ID 4431 //
27646 /* 76461 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27647 /* 76464 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
27648 /* 76469 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27649 /* 76472 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27650 /* 76475 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27651 /* 76478 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
27652 /* 76481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27653 /* 76485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27654 /* 76489 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
27655 /* 76493 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
27656 /* 76497 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
27657 /* 76501 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27658 /* 76506 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27659 /* 76510 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27660 /* 76512 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3787:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$m1, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m2), MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
27661 /* 76512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
27662 /* 76515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27663 /* 76517 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
27664 /* 76519 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
27665 /* 76521 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m2
27666 /* 76525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27667 /* 76528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27668 /* 76534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27669 /* 76540 */ GIR_RootConstrainSelectedInstOperands,
27670 /* 76541 */ // GIR_Coverage, 4431,
27671 /* 76541 */ GIR_EraseRootFromParent_Done,
27672 /* 76542 */ // Label 1551: @76542
27673 /* 76542 */ GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(76605), // Rule ID 145 //
27674 /* 76547 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
27675 /* 76550 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8),
27676 /* 76555 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27677 /* 76558 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27678 /* 76561 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27679 /* 76564 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27680 /* 76567 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27681 /* 76571 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27682 /* 76575 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27683 /* 76579 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27684 /* 76583 */ // (intrinsic_wo_chain:{ *:[i32] } 4194:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (USADA8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
27685 /* 76583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USADA8),
27686 /* 76586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27687 /* 76588 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
27688 /* 76590 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
27689 /* 76592 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
27690 /* 76594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27691 /* 76597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27692 /* 76603 */ GIR_RootConstrainSelectedInstOperands,
27693 /* 76604 */ // GIR_Coverage, 145,
27694 /* 76604 */ GIR_EraseRootFromParent_Done,
27695 /* 76605 */ // Label 1552: @76605
27696 /* 76605 */ GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(76668), // Rule ID 468 //
27697 /* 76610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
27698 /* 76613 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8),
27699 /* 76618 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27700 /* 76621 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27701 /* 76624 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27702 /* 76627 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27703 /* 76630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27704 /* 76634 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27705 /* 76638 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27706 /* 76642 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27707 /* 76646 */ // (intrinsic_wo_chain:{ *:[i32] } 4194:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2USADA8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
27708 /* 76646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USADA8),
27709 /* 76649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27710 /* 76651 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
27711 /* 76653 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
27712 /* 76655 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
27713 /* 76657 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27714 /* 76660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27715 /* 76666 */ GIR_RootConstrainSelectedInstOperands,
27716 /* 76667 */ // GIR_Coverage, 468,
27717 /* 76667 */ GIR_EraseRootFromParent_Done,
27718 /* 76668 */ // Label 1553: @76668
27719 /* 76668 */ GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(76731), // Rule ID 527 //
27720 /* 76673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
27721 /* 76676 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad),
27722 /* 76681 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27723 /* 76684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27724 /* 76687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27725 /* 76690 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27726 /* 76693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27727 /* 76697 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27728 /* 76701 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27729 /* 76705 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27730 /* 76709 */ // (intrinsic_wo_chain:{ *:[i32] } 4139:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
27731 /* 76709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAD),
27732 /* 76712 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27733 /* 76714 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
27734 /* 76716 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
27735 /* 76718 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
27736 /* 76720 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27737 /* 76723 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27738 /* 76729 */ GIR_RootConstrainSelectedInstOperands,
27739 /* 76730 */ // GIR_Coverage, 527,
27740 /* 76730 */ GIR_EraseRootFromParent_Done,
27741 /* 76731 */ // Label 1554: @76731
27742 /* 76731 */ GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(76794), // Rule ID 528 //
27743 /* 76736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
27744 /* 76739 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx),
27745 /* 76744 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27746 /* 76747 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27747 /* 76750 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27748 /* 76753 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27749 /* 76756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27750 /* 76760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27751 /* 76764 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27752 /* 76768 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27753 /* 76772 */ // (intrinsic_wo_chain:{ *:[i32] } 4140:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
27754 /* 76772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLADX),
27755 /* 76775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27756 /* 76777 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
27757 /* 76779 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
27758 /* 76781 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
27759 /* 76783 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27760 /* 76786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27761 /* 76792 */ GIR_RootConstrainSelectedInstOperands,
27762 /* 76793 */ // GIR_Coverage, 528,
27763 /* 76793 */ GIR_EraseRootFromParent_Done,
27764 /* 76794 */ // Label 1555: @76794
27765 /* 76794 */ GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(76857), // Rule ID 529 //
27766 /* 76799 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
27767 /* 76802 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd),
27768 /* 76807 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27769 /* 76810 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27770 /* 76813 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27771 /* 76816 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27772 /* 76819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27773 /* 76823 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27774 /* 76827 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27775 /* 76831 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27776 /* 76835 */ // (intrinsic_wo_chain:{ *:[i32] } 4147:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
27777 /* 76835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSD),
27778 /* 76838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27779 /* 76840 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
27780 /* 76842 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
27781 /* 76844 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
27782 /* 76846 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27783 /* 76849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27784 /* 76855 */ GIR_RootConstrainSelectedInstOperands,
27785 /* 76856 */ // GIR_Coverage, 529,
27786 /* 76856 */ GIR_EraseRootFromParent_Done,
27787 /* 76857 */ // Label 1556: @76857
27788 /* 76857 */ GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(76920), // Rule ID 530 //
27789 /* 76862 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
27790 /* 76865 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx),
27791 /* 76870 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27792 /* 76873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27793 /* 76876 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27794 /* 76879 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27795 /* 76882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27796 /* 76886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27797 /* 76890 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27798 /* 76894 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27799 /* 76898 */ // (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
27800 /* 76898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSDX),
27801 /* 76901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27802 /* 76903 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
27803 /* 76905 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
27804 /* 76907 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
27805 /* 76909 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27806 /* 76912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27807 /* 76918 */ GIR_RootConstrainSelectedInstOperands,
27808 /* 76919 */ // GIR_Coverage, 530,
27809 /* 76919 */ GIR_EraseRootFromParent_Done,
27810 /* 76920 */ // Label 1557: @76920
27811 /* 76920 */ GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(76974), // Rule ID 1113 //
27812 /* 76925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
27813 /* 76928 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot),
27814 /* 76933 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
27815 /* 76936 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
27816 /* 76939 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
27817 /* 76942 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
27818 /* 76945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27819 /* 76949 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27820 /* 76953 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27821 /* 76957 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27822 /* 76961 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4000:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27823 /* 76961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTD),
27824 /* 76964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27825 /* 76966 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27826 /* 76968 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27827 /* 76970 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27828 /* 76972 */ GIR_RootConstrainSelectedInstOperands,
27829 /* 76973 */ // GIR_Coverage, 1113,
27830 /* 76973 */ GIR_EraseRootFromParent_Done,
27831 /* 76974 */ // Label 1558: @76974
27832 /* 76974 */ GIM_Try, /*On fail goto*//*Label 1559*/ GIMT_Encode4(77028), // Rule ID 1114 //
27833 /* 76979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
27834 /* 76982 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot),
27835 /* 76987 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
27836 /* 76990 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
27837 /* 76993 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
27838 /* 76996 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
27839 /* 76999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27840 /* 77003 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27841 /* 77007 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27842 /* 77011 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27843 /* 77015 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3988:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27844 /* 77015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTD),
27845 /* 77018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27846 /* 77020 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27847 /* 77022 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27848 /* 77024 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27849 /* 77026 */ GIR_RootConstrainSelectedInstOperands,
27850 /* 77027 */ // GIR_Coverage, 1114,
27851 /* 77027 */ GIR_EraseRootFromParent_Done,
27852 /* 77028 */ // Label 1559: @77028
27853 /* 77028 */ GIM_Try, /*On fail goto*//*Label 1560*/ GIMT_Encode4(77082), // Rule ID 1115 //
27854 /* 77033 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
27855 /* 77036 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot),
27856 /* 77041 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27857 /* 77044 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27858 /* 77047 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27859 /* 77050 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27860 /* 77053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27861 /* 77057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27862 /* 77061 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27863 /* 77065 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27864 /* 77069 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4000:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27865 /* 77069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTQ),
27866 /* 77072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27867 /* 77074 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27868 /* 77076 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27869 /* 77078 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27870 /* 77080 */ GIR_RootConstrainSelectedInstOperands,
27871 /* 77081 */ // GIR_Coverage, 1115,
27872 /* 77081 */ GIR_EraseRootFromParent_Done,
27873 /* 77082 */ // Label 1560: @77082
27874 /* 77082 */ GIM_Try, /*On fail goto*//*Label 1561*/ GIMT_Encode4(77136), // Rule ID 1116 //
27875 /* 77087 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
27876 /* 77090 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot),
27877 /* 77095 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27878 /* 77098 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27879 /* 77101 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27880 /* 77104 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27881 /* 77107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27882 /* 77111 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27883 /* 77115 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27884 /* 77119 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27885 /* 77123 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3988:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27886 /* 77123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTQ),
27887 /* 77126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27888 /* 77128 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27889 /* 77130 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27890 /* 77132 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27891 /* 77134 */ GIR_RootConstrainSelectedInstOperands,
27892 /* 77135 */ // GIR_Coverage, 1116,
27893 /* 77135 */ GIR_EraseRootFromParent_Done,
27894 /* 77136 */ // Label 1561: @77136
27895 /* 77136 */ GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(77190), // Rule ID 1117 //
27896 /* 77141 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
27897 /* 77144 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_smmla),
27898 /* 77149 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27899 /* 77152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27900 /* 77155 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27901 /* 77158 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27902 /* 77161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27903 /* 77165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27904 /* 77169 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27905 /* 77173 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27906 /* 77177 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3999:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27907 /* 77177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSMMLA),
27908 /* 77180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27909 /* 77182 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27910 /* 77184 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27911 /* 77186 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27912 /* 77188 */ GIR_RootConstrainSelectedInstOperands,
27913 /* 77189 */ // GIR_Coverage, 1117,
27914 /* 77189 */ GIR_EraseRootFromParent_Done,
27915 /* 77190 */ // Label 1562: @77190
27916 /* 77190 */ GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(77244), // Rule ID 1118 //
27917 /* 77195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
27918 /* 77198 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_ummla),
27919 /* 77203 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27920 /* 77206 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27921 /* 77209 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27922 /* 77212 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27923 /* 77215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27924 /* 77219 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27925 /* 77223 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27926 /* 77227 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27927 /* 77231 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4001:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27928 /* 77231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUMMLA),
27929 /* 77234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27930 /* 77236 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27931 /* 77238 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27932 /* 77240 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27933 /* 77242 */ GIR_RootConstrainSelectedInstOperands,
27934 /* 77243 */ // GIR_Coverage, 1118,
27935 /* 77243 */ GIR_EraseRootFromParent_Done,
27936 /* 77244 */ // Label 1563: @77244
27937 /* 77244 */ GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(77298), // Rule ID 1119 //
27938 /* 77249 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
27939 /* 77252 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usmmla),
27940 /* 77257 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27941 /* 77260 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27942 /* 77263 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27943 /* 77266 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27944 /* 77269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27945 /* 77273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27946 /* 77277 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27947 /* 77281 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27948 /* 77285 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4003:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27949 /* 77285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSMMLA),
27950 /* 77288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27951 /* 77290 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27952 /* 77292 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27953 /* 77294 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27954 /* 77296 */ GIR_RootConstrainSelectedInstOperands,
27955 /* 77297 */ // GIR_Coverage, 1119,
27956 /* 77297 */ GIR_EraseRootFromParent_Done,
27957 /* 77298 */ // Label 1564: @77298
27958 /* 77298 */ GIM_Try, /*On fail goto*//*Label 1565*/ GIMT_Encode4(77352), // Rule ID 1120 //
27959 /* 77303 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
27960 /* 77306 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot),
27961 /* 77311 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
27962 /* 77314 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
27963 /* 77317 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
27964 /* 77320 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
27965 /* 77323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27966 /* 77327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27967 /* 77331 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27968 /* 77335 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27969 /* 77339 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4002:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27970 /* 77339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTD),
27971 /* 77342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27972 /* 77344 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27973 /* 77346 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27974 /* 77348 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27975 /* 77350 */ GIR_RootConstrainSelectedInstOperands,
27976 /* 77351 */ // GIR_Coverage, 1120,
27977 /* 77351 */ GIR_EraseRootFromParent_Done,
27978 /* 77352 */ // Label 1565: @77352
27979 /* 77352 */ GIM_Try, /*On fail goto*//*Label 1566*/ GIMT_Encode4(77406), // Rule ID 1121 //
27980 /* 77357 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
27981 /* 77360 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot),
27982 /* 77365 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27983 /* 77368 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27984 /* 77371 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27985 /* 77374 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27986 /* 77377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27987 /* 77381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27988 /* 77385 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27989 /* 77389 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27990 /* 77393 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4002:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27991 /* 77393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTQ),
27992 /* 77396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27993 /* 77398 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27994 /* 77400 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27995 /* 77402 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27996 /* 77404 */ GIR_RootConstrainSelectedInstOperands,
27997 /* 77405 */ // GIR_Coverage, 1121,
27998 /* 77405 */ GIR_EraseRootFromParent_Done,
27999 /* 77406 */ // Label 1566: @77406
28000 /* 77406 */ GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(77469), // Rule ID 1852 //
28001 /* 77411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28002 /* 77414 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx1),
28003 /* 77419 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
28004 /* 77422 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
28005 /* 77425 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
28006 /* 77428 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
28007 /* 77431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28008 /* 77435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28009 /* 77439 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28010 /* 77443 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28011 /* 77447 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4114:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VTBX1:{ *:[v8i8] } DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
28012 /* 77447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX1),
28013 /* 77450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28014 /* 77452 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
28015 /* 77454 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28016 /* 77456 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28017 /* 77458 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28018 /* 77461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28019 /* 77467 */ GIR_RootConstrainSelectedInstOperands,
28020 /* 77468 */ // GIR_Coverage, 1852,
28021 /* 77468 */ GIR_EraseRootFromParent_Done,
28022 /* 77469 */ // Label 1567: @77469
28023 /* 77469 */ GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(77523), // Rule ID 1907 //
28024 /* 77474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
28025 /* 77477 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su0),
28026 /* 77482 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28027 /* 77485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28028 /* 77488 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28029 /* 77491 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28030 /* 77494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28031 /* 77498 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28032 /* 77502 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28033 /* 77506 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28034 /* 77510 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3993:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28035 /* 77510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU0),
28036 /* 77513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28037 /* 77515 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28038 /* 77517 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28039 /* 77519 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28040 /* 77521 */ GIR_RootConstrainSelectedInstOperands,
28041 /* 77522 */ // GIR_Coverage, 1907,
28042 /* 77522 */ GIR_EraseRootFromParent_Done,
28043 /* 77523 */ // Label 1568: @77523
28044 /* 77523 */ GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(77577), // Rule ID 1908 //
28045 /* 77528 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
28046 /* 77531 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h),
28047 /* 77536 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28048 /* 77539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28049 /* 77542 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28050 /* 77545 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28051 /* 77548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28052 /* 77552 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28053 /* 77556 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28054 /* 77560 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28055 /* 77564 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3995:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28056 /* 77564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H),
28057 /* 77567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28058 /* 77569 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28059 /* 77571 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28060 /* 77573 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28061 /* 77575 */ GIR_RootConstrainSelectedInstOperands,
28062 /* 77576 */ // GIR_Coverage, 1908,
28063 /* 77576 */ GIR_EraseRootFromParent_Done,
28064 /* 77577 */ // Label 1569: @77577
28065 /* 77577 */ GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(77631), // Rule ID 1909 //
28066 /* 77582 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
28067 /* 77585 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h2),
28068 /* 77590 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28069 /* 77593 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28070 /* 77596 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28071 /* 77599 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28072 /* 77602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28073 /* 77606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28074 /* 77610 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28075 /* 77614 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28076 /* 77618 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3996:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H2:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28077 /* 77618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H2),
28078 /* 77621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28079 /* 77623 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28080 /* 77625 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28081 /* 77627 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28082 /* 77629 */ GIR_RootConstrainSelectedInstOperands,
28083 /* 77630 */ // GIR_Coverage, 1909,
28084 /* 77630 */ GIR_EraseRootFromParent_Done,
28085 /* 77631 */ // Label 1570: @77631
28086 /* 77631 */ GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(77685), // Rule ID 1910 //
28087 /* 77636 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
28088 /* 77639 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su1),
28089 /* 77644 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28090 /* 77647 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28091 /* 77650 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28092 /* 77653 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28093 /* 77656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28094 /* 77660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28095 /* 77664 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28096 /* 77668 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28097 /* 77672 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3998:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28098 /* 77672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU1),
28099 /* 77675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28100 /* 77677 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28101 /* 77679 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28102 /* 77681 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28103 /* 77683 */ GIR_RootConstrainSelectedInstOperands,
28104 /* 77684 */ // GIR_Coverage, 1910,
28105 /* 77684 */ GIR_EraseRootFromParent_Done,
28106 /* 77685 */ // Label 1571: @77685
28107 /* 77685 */ GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(77748), // Rule ID 2085 //
28108 /* 77690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
28109 /* 77693 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad),
28110 /* 77698 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28111 /* 77701 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28112 /* 77704 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28113 /* 77707 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28114 /* 77710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28115 /* 77714 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28116 /* 77718 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28117 /* 77722 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28118 /* 77726 */ // (intrinsic_wo_chain:{ *:[i32] } 4139:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
28119 /* 77726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAD),
28120 /* 77729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28121 /* 77731 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
28122 /* 77733 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
28123 /* 77735 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
28124 /* 77737 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28125 /* 77740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28126 /* 77746 */ GIR_RootConstrainSelectedInstOperands,
28127 /* 77747 */ // GIR_Coverage, 2085,
28128 /* 77747 */ GIR_EraseRootFromParent_Done,
28129 /* 77748 */ // Label 1572: @77748
28130 /* 77748 */ GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(77811), // Rule ID 2086 //
28131 /* 77753 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
28132 /* 77756 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx),
28133 /* 77761 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28134 /* 77764 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28135 /* 77767 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28136 /* 77770 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28137 /* 77773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28138 /* 77777 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28139 /* 77781 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28140 /* 77785 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28141 /* 77789 */ // (intrinsic_wo_chain:{ *:[i32] } 4140:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
28142 /* 77789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLADX),
28143 /* 77792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28144 /* 77794 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
28145 /* 77796 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
28146 /* 77798 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
28147 /* 77800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28148 /* 77803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28149 /* 77809 */ GIR_RootConstrainSelectedInstOperands,
28150 /* 77810 */ // GIR_Coverage, 2086,
28151 /* 77810 */ GIR_EraseRootFromParent_Done,
28152 /* 77811 */ // Label 1573: @77811
28153 /* 77811 */ GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(77874), // Rule ID 2087 //
28154 /* 77816 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
28155 /* 77819 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd),
28156 /* 77824 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28157 /* 77827 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28158 /* 77830 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28159 /* 77833 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28160 /* 77836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28161 /* 77840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28162 /* 77844 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28163 /* 77848 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28164 /* 77852 */ // (intrinsic_wo_chain:{ *:[i32] } 4147:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
28165 /* 77852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSD),
28166 /* 77855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28167 /* 77857 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
28168 /* 77859 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
28169 /* 77861 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
28170 /* 77863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28171 /* 77866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28172 /* 77872 */ GIR_RootConstrainSelectedInstOperands,
28173 /* 77873 */ // GIR_Coverage, 2087,
28174 /* 77873 */ GIR_EraseRootFromParent_Done,
28175 /* 77874 */ // Label 1574: @77874
28176 /* 77874 */ GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(77937), // Rule ID 2088 //
28177 /* 77879 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
28178 /* 77882 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx),
28179 /* 77887 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28180 /* 77890 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28181 /* 77893 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28182 /* 77896 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28183 /* 77899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28184 /* 77903 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28185 /* 77907 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28186 /* 77911 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28187 /* 77915 */ // (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
28188 /* 77915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSDX),
28189 /* 77918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28190 /* 77920 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
28191 /* 77922 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
28192 /* 77924 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
28193 /* 77926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28194 /* 77929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28195 /* 77935 */ GIR_RootConstrainSelectedInstOperands,
28196 /* 77936 */ // GIR_Coverage, 2088,
28197 /* 77936 */ GIR_EraseRootFromParent_Done,
28198 /* 77937 */ // Label 1575: @77937
28199 /* 77937 */ GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(78000), // Rule ID 2176 //
28200 /* 77942 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
28201 /* 77945 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb),
28202 /* 77950 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28203 /* 77953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28204 /* 77956 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28205 /* 77959 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28206 /* 77962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28207 /* 77966 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28208 /* 77970 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28209 /* 77974 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28210 /* 77978 */ // (intrinsic_wo_chain:{ *:[i32] } 4137:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28211 /* 77978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB),
28212 /* 77981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28213 /* 77983 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28214 /* 77985 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28215 /* 77987 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28216 /* 77989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28217 /* 77992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28218 /* 77998 */ GIR_RootConstrainSelectedInstOperands,
28219 /* 77999 */ // GIR_Coverage, 2176,
28220 /* 77999 */ GIR_EraseRootFromParent_Done,
28221 /* 78000 */ // Label 1576: @78000
28222 /* 78000 */ GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(78063), // Rule ID 2177 //
28223 /* 78005 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
28224 /* 78008 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt),
28225 /* 78013 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28226 /* 78016 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28227 /* 78019 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28228 /* 78022 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28229 /* 78025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28230 /* 78029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28231 /* 78033 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28232 /* 78037 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28233 /* 78041 */ // (intrinsic_wo_chain:{ *:[i32] } 4138:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28234 /* 78041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
28235 /* 78044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28236 /* 78046 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28237 /* 78048 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28238 /* 78050 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28239 /* 78052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28240 /* 78055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28241 /* 78061 */ GIR_RootConstrainSelectedInstOperands,
28242 /* 78062 */ // GIR_Coverage, 2177,
28243 /* 78062 */ GIR_EraseRootFromParent_Done,
28244 /* 78063 */ // Label 1577: @78063
28245 /* 78063 */ GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(78126), // Rule ID 2178 //
28246 /* 78068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
28247 /* 78071 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb),
28248 /* 78076 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28249 /* 78079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28250 /* 78082 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28251 /* 78085 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28252 /* 78088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28253 /* 78092 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28254 /* 78096 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28255 /* 78100 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28256 /* 78104 */ // (intrinsic_wo_chain:{ *:[i32] } 4143:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28257 /* 78104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB),
28258 /* 78107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28259 /* 78109 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28260 /* 78111 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28261 /* 78113 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28262 /* 78115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28263 /* 78118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28264 /* 78124 */ GIR_RootConstrainSelectedInstOperands,
28265 /* 78125 */ // GIR_Coverage, 2178,
28266 /* 78125 */ GIR_EraseRootFromParent_Done,
28267 /* 78126 */ // Label 1578: @78126
28268 /* 78126 */ GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(78189), // Rule ID 2179 //
28269 /* 78131 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
28270 /* 78134 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt),
28271 /* 78139 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28272 /* 78142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28273 /* 78145 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28274 /* 78148 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28275 /* 78151 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28276 /* 78155 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28277 /* 78159 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28278 /* 78163 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28279 /* 78167 */ // (intrinsic_wo_chain:{ *:[i32] } 4144:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28280 /* 78167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT),
28281 /* 78170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28282 /* 78172 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28283 /* 78174 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28284 /* 78176 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28285 /* 78178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28286 /* 78181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28287 /* 78187 */ GIR_RootConstrainSelectedInstOperands,
28288 /* 78188 */ // GIR_Coverage, 2179,
28289 /* 78188 */ GIR_EraseRootFromParent_Done,
28290 /* 78189 */ // Label 1579: @78189
28291 /* 78189 */ GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(78252), // Rule ID 2180 //
28292 /* 78194 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
28293 /* 78197 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb),
28294 /* 78202 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28295 /* 78205 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28296 /* 78208 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28297 /* 78211 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28298 /* 78214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28299 /* 78218 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28300 /* 78222 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28301 /* 78226 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28302 /* 78230 */ // (intrinsic_wo_chain:{ *:[i32] } 4145:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28303 /* 78230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWB),
28304 /* 78233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28305 /* 78235 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28306 /* 78237 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28307 /* 78239 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28308 /* 78241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28309 /* 78244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28310 /* 78250 */ GIR_RootConstrainSelectedInstOperands,
28311 /* 78251 */ // GIR_Coverage, 2180,
28312 /* 78251 */ GIR_EraseRootFromParent_Done,
28313 /* 78252 */ // Label 1580: @78252
28314 /* 78252 */ GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(78315), // Rule ID 2181 //
28315 /* 78257 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
28316 /* 78260 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt),
28317 /* 78265 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28318 /* 78268 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28319 /* 78271 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28320 /* 78274 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28321 /* 78277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28322 /* 78281 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28323 /* 78285 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28324 /* 78289 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28325 /* 78293 */ // (intrinsic_wo_chain:{ *:[i32] } 4146:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28326 /* 78293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWT),
28327 /* 78296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28328 /* 78298 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28329 /* 78300 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28330 /* 78302 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28331 /* 78304 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28332 /* 78307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28333 /* 78313 */ GIR_RootConstrainSelectedInstOperands,
28334 /* 78314 */ // GIR_Coverage, 2181,
28335 /* 78314 */ GIR_EraseRootFromParent_Done,
28336 /* 78315 */ // Label 1581: @78315
28337 /* 78315 */ GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(78378), // Rule ID 2367 //
28338 /* 78320 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28339 /* 78323 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb),
28340 /* 78328 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28341 /* 78331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28342 /* 78334 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28343 /* 78337 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28344 /* 78340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28345 /* 78344 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28346 /* 78348 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28347 /* 78352 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28348 /* 78356 */ // (intrinsic_wo_chain:{ *:[i32] } 4137:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28349 /* 78356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB),
28350 /* 78359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28351 /* 78361 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28352 /* 78363 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28353 /* 78365 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28354 /* 78367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28355 /* 78370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28356 /* 78376 */ GIR_RootConstrainSelectedInstOperands,
28357 /* 78377 */ // GIR_Coverage, 2367,
28358 /* 78377 */ GIR_EraseRootFromParent_Done,
28359 /* 78378 */ // Label 1582: @78378
28360 /* 78378 */ GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(78441), // Rule ID 2368 //
28361 /* 78383 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28362 /* 78386 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt),
28363 /* 78391 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28364 /* 78394 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28365 /* 78397 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28366 /* 78400 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28367 /* 78403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28368 /* 78407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28369 /* 78411 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28370 /* 78415 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28371 /* 78419 */ // (intrinsic_wo_chain:{ *:[i32] } 4138:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28372 /* 78419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
28373 /* 78422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28374 /* 78424 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28375 /* 78426 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28376 /* 78428 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28377 /* 78430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28378 /* 78433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28379 /* 78439 */ GIR_RootConstrainSelectedInstOperands,
28380 /* 78440 */ // GIR_Coverage, 2368,
28381 /* 78440 */ GIR_EraseRootFromParent_Done,
28382 /* 78441 */ // Label 1583: @78441
28383 /* 78441 */ GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(78504), // Rule ID 2369 //
28384 /* 78446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28385 /* 78449 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb),
28386 /* 78454 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28387 /* 78457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28388 /* 78460 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28389 /* 78463 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28390 /* 78466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28391 /* 78470 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28392 /* 78474 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28393 /* 78478 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28394 /* 78482 */ // (intrinsic_wo_chain:{ *:[i32] } 4143:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28395 /* 78482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB),
28396 /* 78485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28397 /* 78487 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28398 /* 78489 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28399 /* 78491 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28400 /* 78493 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28401 /* 78496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28402 /* 78502 */ GIR_RootConstrainSelectedInstOperands,
28403 /* 78503 */ // GIR_Coverage, 2369,
28404 /* 78503 */ GIR_EraseRootFromParent_Done,
28405 /* 78504 */ // Label 1584: @78504
28406 /* 78504 */ GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(78567), // Rule ID 2370 //
28407 /* 78509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28408 /* 78512 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt),
28409 /* 78517 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28410 /* 78520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28411 /* 78523 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28412 /* 78526 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28413 /* 78529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28414 /* 78533 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28415 /* 78537 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28416 /* 78541 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28417 /* 78545 */ // (intrinsic_wo_chain:{ *:[i32] } 4144:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28418 /* 78545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT),
28419 /* 78548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28420 /* 78550 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28421 /* 78552 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28422 /* 78554 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28423 /* 78556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28424 /* 78559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28425 /* 78565 */ GIR_RootConstrainSelectedInstOperands,
28426 /* 78566 */ // GIR_Coverage, 2370,
28427 /* 78566 */ GIR_EraseRootFromParent_Done,
28428 /* 78567 */ // Label 1585: @78567
28429 /* 78567 */ GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(78630), // Rule ID 2371 //
28430 /* 78572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28431 /* 78575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb),
28432 /* 78580 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28433 /* 78583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28434 /* 78586 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28435 /* 78589 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28436 /* 78592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28437 /* 78596 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28438 /* 78600 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28439 /* 78604 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28440 /* 78608 */ // (intrinsic_wo_chain:{ *:[i32] } 4145:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28441 /* 78608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWB),
28442 /* 78611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28443 /* 78613 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28444 /* 78615 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28445 /* 78617 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28446 /* 78619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28447 /* 78622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28448 /* 78628 */ GIR_RootConstrainSelectedInstOperands,
28449 /* 78629 */ // GIR_Coverage, 2371,
28450 /* 78629 */ GIR_EraseRootFromParent_Done,
28451 /* 78630 */ // Label 1586: @78630
28452 /* 78630 */ GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(78693), // Rule ID 2372 //
28453 /* 78635 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28454 /* 78638 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt),
28455 /* 78643 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28456 /* 78646 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28457 /* 78649 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28458 /* 78652 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28459 /* 78655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28460 /* 78659 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28461 /* 78663 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28462 /* 78667 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28463 /* 78671 */ // (intrinsic_wo_chain:{ *:[i32] } 4146:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28464 /* 78671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWT),
28465 /* 78674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28466 /* 78676 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28467 /* 78678 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28468 /* 78680 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28469 /* 78682 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28470 /* 78685 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28471 /* 78691 */ GIR_RootConstrainSelectedInstOperands,
28472 /* 78692 */ // GIR_Coverage, 2372,
28473 /* 78692 */ GIR_EraseRootFromParent_Done,
28474 /* 78693 */ // Label 1587: @78693
28475 /* 78693 */ GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(78756), // Rule ID 2842 //
28476 /* 78698 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28477 /* 78701 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah),
28478 /* 78706 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
28479 /* 78709 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
28480 /* 78712 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
28481 /* 78715 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
28482 /* 78718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28483 /* 78722 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28484 /* 78726 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28485 /* 78730 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28486 /* 78734 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4072:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLAHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
28487 /* 78734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i16),
28488 /* 78737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28489 /* 78739 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28490 /* 78741 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28491 /* 78743 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28492 /* 78745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28493 /* 78748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28494 /* 78754 */ GIR_RootConstrainSelectedInstOperands,
28495 /* 78755 */ // GIR_Coverage, 2842,
28496 /* 78755 */ GIR_EraseRootFromParent_Done,
28497 /* 78756 */ // Label 1588: @78756
28498 /* 78756 */ GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(78819), // Rule ID 2843 //
28499 /* 78761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28500 /* 78764 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah),
28501 /* 78769 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
28502 /* 78772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
28503 /* 78775 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
28504 /* 78778 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
28505 /* 78781 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28506 /* 78785 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28507 /* 78789 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28508 /* 78793 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28509 /* 78797 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4072:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLAHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
28510 /* 78797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv2i32),
28511 /* 78800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28512 /* 78802 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28513 /* 78804 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28514 /* 78806 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28515 /* 78808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28516 /* 78811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28517 /* 78817 */ GIR_RootConstrainSelectedInstOperands,
28518 /* 78818 */ // GIR_Coverage, 2843,
28519 /* 78818 */ GIR_EraseRootFromParent_Done,
28520 /* 78819 */ // Label 1589: @78819
28521 /* 78819 */ GIM_Try, /*On fail goto*//*Label 1590*/ GIMT_Encode4(78882), // Rule ID 2844 //
28522 /* 78824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28523 /* 78827 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah),
28524 /* 78832 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
28525 /* 78835 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28526 /* 78838 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28527 /* 78841 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
28528 /* 78844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28529 /* 78848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28530 /* 78852 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28531 /* 78856 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28532 /* 78860 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4072:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLAHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
28533 /* 78860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv8i16),
28534 /* 78863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28535 /* 78865 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28536 /* 78867 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28537 /* 78869 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28538 /* 78871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28539 /* 78874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28540 /* 78880 */ GIR_RootConstrainSelectedInstOperands,
28541 /* 78881 */ // GIR_Coverage, 2844,
28542 /* 78881 */ GIR_EraseRootFromParent_Done,
28543 /* 78882 */ // Label 1590: @78882
28544 /* 78882 */ GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(78945), // Rule ID 2845 //
28545 /* 78887 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28546 /* 78890 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah),
28547 /* 78895 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28548 /* 78898 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28549 /* 78901 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28550 /* 78904 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28551 /* 78907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28552 /* 78911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28553 /* 78915 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28554 /* 78919 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28555 /* 78923 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4072:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLAHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28556 /* 78923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i32),
28557 /* 78926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28558 /* 78928 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28559 /* 78930 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28560 /* 78932 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28561 /* 78934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28562 /* 78937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28563 /* 78943 */ GIR_RootConstrainSelectedInstOperands,
28564 /* 78944 */ // GIR_Coverage, 2845,
28565 /* 78944 */ GIR_EraseRootFromParent_Done,
28566 /* 78945 */ // Label 1591: @78945
28567 /* 78945 */ GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(79008), // Rule ID 2850 //
28568 /* 78950 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28569 /* 78953 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh),
28570 /* 78958 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
28571 /* 78961 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
28572 /* 78964 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
28573 /* 78967 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
28574 /* 78970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28575 /* 78974 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28576 /* 78978 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28577 /* 78982 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28578 /* 78986 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4073:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLSHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
28579 /* 78986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i16),
28580 /* 78989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28581 /* 78991 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28582 /* 78993 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28583 /* 78995 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28584 /* 78997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28585 /* 79000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28586 /* 79006 */ GIR_RootConstrainSelectedInstOperands,
28587 /* 79007 */ // GIR_Coverage, 2850,
28588 /* 79007 */ GIR_EraseRootFromParent_Done,
28589 /* 79008 */ // Label 1592: @79008
28590 /* 79008 */ GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(79071), // Rule ID 2851 //
28591 /* 79013 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28592 /* 79016 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh),
28593 /* 79021 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
28594 /* 79024 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
28595 /* 79027 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
28596 /* 79030 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
28597 /* 79033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28598 /* 79037 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28599 /* 79041 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28600 /* 79045 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28601 /* 79049 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4073:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLSHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
28602 /* 79049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv2i32),
28603 /* 79052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28604 /* 79054 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28605 /* 79056 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28606 /* 79058 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28607 /* 79060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28608 /* 79063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28609 /* 79069 */ GIR_RootConstrainSelectedInstOperands,
28610 /* 79070 */ // GIR_Coverage, 2851,
28611 /* 79070 */ GIR_EraseRootFromParent_Done,
28612 /* 79071 */ // Label 1593: @79071
28613 /* 79071 */ GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(79134), // Rule ID 2852 //
28614 /* 79076 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28615 /* 79079 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh),
28616 /* 79084 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
28617 /* 79087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28618 /* 79090 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28619 /* 79093 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
28620 /* 79096 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28621 /* 79100 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28622 /* 79104 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28623 /* 79108 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28624 /* 79112 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4073:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLSHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
28625 /* 79112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv8i16),
28626 /* 79115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28627 /* 79117 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28628 /* 79119 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28629 /* 79121 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28630 /* 79123 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28631 /* 79126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28632 /* 79132 */ GIR_RootConstrainSelectedInstOperands,
28633 /* 79133 */ // GIR_Coverage, 2852,
28634 /* 79133 */ GIR_EraseRootFromParent_Done,
28635 /* 79134 */ // Label 1594: @79134
28636 /* 79134 */ GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(79197), // Rule ID 2853 //
28637 /* 79139 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28638 /* 79142 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh),
28639 /* 79147 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28640 /* 79150 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28641 /* 79153 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28642 /* 79156 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28643 /* 79159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28644 /* 79163 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28645 /* 79167 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28646 /* 79171 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28647 /* 79175 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4073:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLSHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28648 /* 79175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i32),
28649 /* 79178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28650 /* 79180 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28651 /* 79182 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28652 /* 79184 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28653 /* 79186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28654 /* 79189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28655 /* 79195 */ GIR_RootConstrainSelectedInstOperands,
28656 /* 79196 */ // GIR_Coverage, 2853,
28657 /* 79196 */ GIR_EraseRootFromParent_Done,
28658 /* 79197 */ // Label 1595: @79197
28659 /* 79197 */ GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(79266), // Rule ID 4422 //
28660 /* 79202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
28661 /* 79205 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
28662 /* 79210 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28663 /* 79213 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28664 /* 79216 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28665 /* 79219 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28666 /* 79222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28667 /* 79226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28668 /* 79230 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28669 /* 79234 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28670 /* 79238 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3787:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
28671 /* 79238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32),
28672 /* 79241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28673 /* 79243 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
28674 /* 79245 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
28675 /* 79247 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
28676 /* 79249 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28677 /* 79252 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28678 /* 79258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28679 /* 79264 */ GIR_RootConstrainSelectedInstOperands,
28680 /* 79265 */ // GIR_Coverage, 4422,
28681 /* 79265 */ GIR_EraseRootFromParent_Done,
28682 /* 79266 */ // Label 1596: @79266
28683 /* 79266 */ GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(79335), // Rule ID 4426 //
28684 /* 79271 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
28685 /* 79274 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
28686 /* 79279 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
28687 /* 79282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28688 /* 79285 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28689 /* 79288 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
28690 /* 79291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28691 /* 79295 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28692 /* 79299 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28693 /* 79303 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28694 /* 79307 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3787:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
28695 /* 79307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16),
28696 /* 79310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28697 /* 79312 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
28698 /* 79314 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
28699 /* 79316 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
28700 /* 79318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28701 /* 79321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28702 /* 79327 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28703 /* 79333 */ GIR_RootConstrainSelectedInstOperands,
28704 /* 79334 */ // GIR_Coverage, 4426,
28705 /* 79334 */ GIR_EraseRootFromParent_Done,
28706 /* 79335 */ // Label 1597: @79335
28707 /* 79335 */ GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(79404), // Rule ID 5355 //
28708 /* 79340 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28709 /* 79343 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah),
28710 /* 79348 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
28711 /* 79351 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28712 /* 79354 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28713 /* 79357 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28714 /* 79360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28715 /* 79364 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28716 /* 79368 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28717 /* 79372 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28718 /* 79376 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3917:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28719 /* 79376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs8),
28720 /* 79379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28721 /* 79381 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28722 /* 79383 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28723 /* 79385 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28724 /* 79387 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28725 /* 79390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28726 /* 79396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28727 /* 79402 */ GIR_RootConstrainSelectedInstOperands,
28728 /* 79403 */ // GIR_Coverage, 5355,
28729 /* 79403 */ GIR_EraseRootFromParent_Done,
28730 /* 79404 */ // Label 1598: @79404
28731 /* 79404 */ GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(79473), // Rule ID 5357 //
28732 /* 79409 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28733 /* 79412 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah),
28734 /* 79417 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
28735 /* 79420 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28736 /* 79423 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28737 /* 79426 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28738 /* 79429 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28739 /* 79433 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28740 /* 79437 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28741 /* 79441 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28742 /* 79445 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3917:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28743 /* 79445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs16),
28744 /* 79448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28745 /* 79450 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28746 /* 79452 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28747 /* 79454 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28748 /* 79456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28749 /* 79459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28750 /* 79465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28751 /* 79471 */ GIR_RootConstrainSelectedInstOperands,
28752 /* 79472 */ // GIR_Coverage, 5357,
28753 /* 79472 */ GIR_EraseRootFromParent_Done,
28754 /* 79473 */ // Label 1599: @79473
28755 /* 79473 */ GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(79542), // Rule ID 5359 //
28756 /* 79478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28757 /* 79481 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah),
28758 /* 79486 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28759 /* 79489 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28760 /* 79492 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28761 /* 79495 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28762 /* 79498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28763 /* 79502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28764 /* 79506 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28765 /* 79510 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28766 /* 79514 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3917:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28767 /* 79514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs32),
28768 /* 79517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28769 /* 79519 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28770 /* 79521 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28771 /* 79523 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28772 /* 79525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28773 /* 79528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28774 /* 79534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28775 /* 79540 */ GIR_RootConstrainSelectedInstOperands,
28776 /* 79541 */ // GIR_Coverage, 5359,
28777 /* 79541 */ GIR_EraseRootFromParent_Done,
28778 /* 79542 */ // Label 1600: @79542
28779 /* 79542 */ GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(79611), // Rule ID 5361 //
28780 /* 79547 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28781 /* 79550 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah),
28782 /* 79555 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
28783 /* 79558 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28784 /* 79561 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28785 /* 79564 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28786 /* 79567 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28787 /* 79571 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28788 /* 79575 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28789 /* 79579 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28790 /* 79583 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3926:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28791 /* 79583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs8),
28792 /* 79586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28793 /* 79588 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28794 /* 79590 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28795 /* 79592 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28796 /* 79594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28797 /* 79597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28798 /* 79603 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28799 /* 79609 */ GIR_RootConstrainSelectedInstOperands,
28800 /* 79610 */ // GIR_Coverage, 5361,
28801 /* 79610 */ GIR_EraseRootFromParent_Done,
28802 /* 79611 */ // Label 1601: @79611
28803 /* 79611 */ GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(79680), // Rule ID 5363 //
28804 /* 79616 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28805 /* 79619 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah),
28806 /* 79624 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
28807 /* 79627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28808 /* 79630 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28809 /* 79633 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28810 /* 79636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28811 /* 79640 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28812 /* 79644 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28813 /* 79648 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28814 /* 79652 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3926:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28815 /* 79652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs16),
28816 /* 79655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28817 /* 79657 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28818 /* 79659 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28819 /* 79661 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28820 /* 79663 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28821 /* 79666 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28822 /* 79672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28823 /* 79678 */ GIR_RootConstrainSelectedInstOperands,
28824 /* 79679 */ // GIR_Coverage, 5363,
28825 /* 79679 */ GIR_EraseRootFromParent_Done,
28826 /* 79680 */ // Label 1602: @79680
28827 /* 79680 */ GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(79749), // Rule ID 5365 //
28828 /* 79685 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28829 /* 79688 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah),
28830 /* 79693 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28831 /* 79696 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28832 /* 79699 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28833 /* 79702 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28834 /* 79705 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28835 /* 79709 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28836 /* 79713 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28837 /* 79717 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28838 /* 79721 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3926:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28839 /* 79721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs32),
28840 /* 79724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28841 /* 79726 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28842 /* 79728 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28843 /* 79730 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28844 /* 79732 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28845 /* 79735 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28846 /* 79741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28847 /* 79747 */ GIR_RootConstrainSelectedInstOperands,
28848 /* 79748 */ // GIR_Coverage, 5365,
28849 /* 79748 */ GIR_EraseRootFromParent_Done,
28850 /* 79749 */ // Label 1603: @79749
28851 /* 79749 */ GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(79818), // Rule ID 5367 //
28852 /* 79754 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28853 /* 79757 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash),
28854 /* 79762 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
28855 /* 79765 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28856 /* 79768 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28857 /* 79771 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28858 /* 79774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28859 /* 79778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28860 /* 79782 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28861 /* 79786 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28862 /* 79790 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3919:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28863 /* 79790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs8),
28864 /* 79793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28865 /* 79795 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28866 /* 79797 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28867 /* 79799 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28868 /* 79801 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28869 /* 79804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28870 /* 79810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28871 /* 79816 */ GIR_RootConstrainSelectedInstOperands,
28872 /* 79817 */ // GIR_Coverage, 5367,
28873 /* 79817 */ GIR_EraseRootFromParent_Done,
28874 /* 79818 */ // Label 1604: @79818
28875 /* 79818 */ GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(79887), // Rule ID 5369 //
28876 /* 79823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28877 /* 79826 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash),
28878 /* 79831 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
28879 /* 79834 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28880 /* 79837 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28881 /* 79840 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28882 /* 79843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28883 /* 79847 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28884 /* 79851 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28885 /* 79855 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28886 /* 79859 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3919:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28887 /* 79859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs16),
28888 /* 79862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28889 /* 79864 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28890 /* 79866 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28891 /* 79868 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28892 /* 79870 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28893 /* 79873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28894 /* 79879 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28895 /* 79885 */ GIR_RootConstrainSelectedInstOperands,
28896 /* 79886 */ // GIR_Coverage, 5369,
28897 /* 79886 */ GIR_EraseRootFromParent_Done,
28898 /* 79887 */ // Label 1605: @79887
28899 /* 79887 */ GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(79956), // Rule ID 5371 //
28900 /* 79892 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28901 /* 79895 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash),
28902 /* 79900 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28903 /* 79903 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28904 /* 79906 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28905 /* 79909 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28906 /* 79912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28907 /* 79916 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28908 /* 79920 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28909 /* 79924 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28910 /* 79928 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3919:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28911 /* 79928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs32),
28912 /* 79931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28913 /* 79933 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28914 /* 79935 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28915 /* 79937 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28916 /* 79939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28917 /* 79942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28918 /* 79948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28919 /* 79954 */ GIR_RootConstrainSelectedInstOperands,
28920 /* 79955 */ // GIR_Coverage, 5371,
28921 /* 79955 */ GIR_EraseRootFromParent_Done,
28922 /* 79956 */ // Label 1606: @79956
28923 /* 79956 */ GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(80025), // Rule ID 5373 //
28924 /* 79961 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28925 /* 79964 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash),
28926 /* 79969 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
28927 /* 79972 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28928 /* 79975 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28929 /* 79978 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28930 /* 79981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28931 /* 79985 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28932 /* 79989 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28933 /* 79993 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28934 /* 79997 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3928:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28935 /* 79997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs8),
28936 /* 80000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28937 /* 80002 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28938 /* 80004 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28939 /* 80006 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28940 /* 80008 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28941 /* 80011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28942 /* 80017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28943 /* 80023 */ GIR_RootConstrainSelectedInstOperands,
28944 /* 80024 */ // GIR_Coverage, 5373,
28945 /* 80024 */ GIR_EraseRootFromParent_Done,
28946 /* 80025 */ // Label 1607: @80025
28947 /* 80025 */ GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(80094), // Rule ID 5375 //
28948 /* 80030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28949 /* 80033 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash),
28950 /* 80038 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
28951 /* 80041 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28952 /* 80044 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28953 /* 80047 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28954 /* 80050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28955 /* 80054 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28956 /* 80058 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28957 /* 80062 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28958 /* 80066 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3928:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28959 /* 80066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs16),
28960 /* 80069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28961 /* 80071 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28962 /* 80073 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28963 /* 80075 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28964 /* 80077 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28965 /* 80080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28966 /* 80086 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28967 /* 80092 */ GIR_RootConstrainSelectedInstOperands,
28968 /* 80093 */ // GIR_Coverage, 5375,
28969 /* 80093 */ GIR_EraseRootFromParent_Done,
28970 /* 80094 */ // Label 1608: @80094
28971 /* 80094 */ GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(80163), // Rule ID 5377 //
28972 /* 80099 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
28973 /* 80102 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash),
28974 /* 80107 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28975 /* 80110 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28976 /* 80113 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28977 /* 80116 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28978 /* 80119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28979 /* 80123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28980 /* 80127 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28981 /* 80131 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28982 /* 80135 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3928:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28983 /* 80135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs32),
28984 /* 80138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28985 /* 80140 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28986 /* 80142 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28987 /* 80144 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28988 /* 80146 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28989 /* 80149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28990 /* 80155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28991 /* 80161 */ GIR_RootConstrainSelectedInstOperands,
28992 /* 80162 */ // GIR_Coverage, 5377,
28993 /* 80162 */ GIR_EraseRootFromParent_Done,
28994 /* 80163 */ // Label 1609: @80163
28995 /* 80163 */ GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(80277), // Rule ID 3069 //
28996 /* 80168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28997 /* 80171 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1c),
28998 /* 80176 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28999 /* 80179 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29000 /* 80182 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29001 /* 80185 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
29002 /* 80188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
29003 /* 80192 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3989:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1C:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
29004 /* 80192 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
29005 /* 80195 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29006 /* 80199 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29007 /* 80204 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
29008 /* 80208 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
29009 /* 80213 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
29010 /* 80216 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29011 /* 80220 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29012 /* 80225 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
29013 /* 80227 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
29014 /* 80230 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
29015 /* 80234 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29016 /* 80239 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
29017 /* 80242 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
29018 /* 80245 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17,
29019 /* 80248 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
29020 /* 80253 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
29021 /* 80258 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
29022 /* 80263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1C),
29023 /* 80266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
29024 /* 80268 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd
29025 /* 80270 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29026 /* 80273 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk
29027 /* 80275 */ GIR_RootConstrainSelectedInstOperands,
29028 /* 80276 */ // GIR_Coverage, 3069,
29029 /* 80276 */ GIR_EraseRootFromParent_Done,
29030 /* 80277 */ // Label 1610: @80277
29031 /* 80277 */ GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(80391), // Rule ID 3070 //
29032 /* 80282 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
29033 /* 80285 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1m),
29034 /* 80290 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29035 /* 80293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29036 /* 80296 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29037 /* 80299 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
29038 /* 80302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
29039 /* 80306 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3991:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1M:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
29040 /* 80306 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
29041 /* 80309 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29042 /* 80313 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29043 /* 80318 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
29044 /* 80322 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
29045 /* 80327 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
29046 /* 80330 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29047 /* 80334 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29048 /* 80339 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
29049 /* 80341 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
29050 /* 80344 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
29051 /* 80348 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29052 /* 80353 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
29053 /* 80356 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
29054 /* 80359 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17,
29055 /* 80362 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
29056 /* 80367 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
29057 /* 80372 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
29058 /* 80377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1M),
29059 /* 80380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
29060 /* 80382 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd
29061 /* 80384 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29062 /* 80387 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk
29063 /* 80389 */ GIR_RootConstrainSelectedInstOperands,
29064 /* 80390 */ // GIR_Coverage, 3070,
29065 /* 80390 */ GIR_EraseRootFromParent_Done,
29066 /* 80391 */ // Label 1611: @80391
29067 /* 80391 */ GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(80505), // Rule ID 3071 //
29068 /* 80396 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
29069 /* 80399 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1p),
29070 /* 80404 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29071 /* 80407 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29072 /* 80410 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29073 /* 80413 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
29074 /* 80416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
29075 /* 80420 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3992:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1P:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
29076 /* 80420 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
29077 /* 80423 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29078 /* 80427 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29079 /* 80432 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
29080 /* 80436 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
29081 /* 80441 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
29082 /* 80444 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29083 /* 80448 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29084 /* 80453 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
29085 /* 80455 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
29086 /* 80458 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
29087 /* 80462 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29088 /* 80467 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
29089 /* 80470 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
29090 /* 80473 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17,
29091 /* 80476 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
29092 /* 80481 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
29093 /* 80486 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
29094 /* 80491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1P),
29095 /* 80494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
29096 /* 80496 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd
29097 /* 80498 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29098 /* 80501 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk
29099 /* 80503 */ GIR_RootConstrainSelectedInstOperands,
29100 /* 80504 */ // GIR_Coverage, 3071,
29101 /* 80504 */ GIR_EraseRootFromParent_Done,
29102 /* 80505 */ // Label 1612: @80505
29103 /* 80505 */ GIM_Reject,
29104 /* 80506 */ // Label 1465: @80506
29105 /* 80506 */ GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(83892),
29106 /* 80511 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
29107 /* 80514 */ GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(80598), // Rule ID 4110 //
29108 /* 80519 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29109 /* 80524 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29110 /* 80527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29111 /* 80530 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29112 /* 80533 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29113 /* 80536 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29114 /* 80539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29115 /* 80543 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29116 /* 80547 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
29117 /* 80551 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29118 /* 80555 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29119 /* 80559 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3963:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
29120 /* 80559 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29121 /* 80562 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29122 /* 80566 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29123 /* 80571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8bh),
29124 /* 80574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29125 /* 80576 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29126 /* 80578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29127 /* 80581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29128 /* 80587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29129 /* 80593 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29130 /* 80596 */ GIR_RootConstrainSelectedInstOperands,
29131 /* 80597 */ // GIR_Coverage, 4110,
29132 /* 80597 */ GIR_EraseRootFromParent_Done,
29133 /* 80598 */ // Label 1614: @80598
29134 /* 80598 */ GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(80682), // Rule ID 4114 //
29135 /* 80603 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29136 /* 80608 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29137 /* 80611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29138 /* 80614 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29139 /* 80617 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29140 /* 80620 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29141 /* 80623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29142 /* 80627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29143 /* 80631 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
29144 /* 80635 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29145 /* 80639 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29146 /* 80643 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3963:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
29147 /* 80643 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29148 /* 80646 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29149 /* 80650 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29150 /* 80655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8th),
29151 /* 80658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29152 /* 80660 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29153 /* 80662 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29154 /* 80665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29155 /* 80671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29156 /* 80677 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29157 /* 80680 */ GIR_RootConstrainSelectedInstOperands,
29158 /* 80681 */ // GIR_Coverage, 4114,
29159 /* 80681 */ GIR_EraseRootFromParent_Done,
29160 /* 80682 */ // Label 1615: @80682
29161 /* 80682 */ GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(80766), // Rule ID 4118 //
29162 /* 80687 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29163 /* 80692 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29164 /* 80695 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29165 /* 80698 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29166 /* 80701 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29167 /* 80704 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29168 /* 80707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29169 /* 80711 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29170 /* 80715 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
29171 /* 80719 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29172 /* 80723 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29173 /* 80727 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3963:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
29174 /* 80727 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29175 /* 80730 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29176 /* 80734 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29177 /* 80739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16bh),
29178 /* 80742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29179 /* 80744 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29180 /* 80746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29181 /* 80749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29182 /* 80755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29183 /* 80761 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29184 /* 80764 */ GIR_RootConstrainSelectedInstOperands,
29185 /* 80765 */ // GIR_Coverage, 4118,
29186 /* 80765 */ GIR_EraseRootFromParent_Done,
29187 /* 80766 */ // Label 1616: @80766
29188 /* 80766 */ GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(80850), // Rule ID 4122 //
29189 /* 80771 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29190 /* 80776 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29191 /* 80779 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29192 /* 80782 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29193 /* 80785 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29194 /* 80788 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29195 /* 80791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29196 /* 80795 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29197 /* 80799 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
29198 /* 80803 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29199 /* 80807 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29200 /* 80811 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3963:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
29201 /* 80811 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29202 /* 80814 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29203 /* 80818 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29204 /* 80823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16th),
29205 /* 80826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29206 /* 80828 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29207 /* 80830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29208 /* 80833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29209 /* 80839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29210 /* 80845 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29211 /* 80848 */ GIR_RootConstrainSelectedInstOperands,
29212 /* 80849 */ // GIR_Coverage, 4122,
29213 /* 80849 */ GIR_EraseRootFromParent_Done,
29214 /* 80850 */ // Label 1617: @80850
29215 /* 80850 */ GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(80934), // Rule ID 4126 //
29216 /* 80855 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29217 /* 80860 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29218 /* 80863 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29219 /* 80866 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29220 /* 80869 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29221 /* 80872 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29222 /* 80875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29223 /* 80879 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29224 /* 80883 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
29225 /* 80887 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29226 /* 80891 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29227 /* 80895 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3963:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
29228 /* 80895 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29229 /* 80898 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29230 /* 80902 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29231 /* 80907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8bh),
29232 /* 80910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29233 /* 80912 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29234 /* 80914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29235 /* 80917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29236 /* 80923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29237 /* 80929 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29238 /* 80932 */ GIR_RootConstrainSelectedInstOperands,
29239 /* 80933 */ // GIR_Coverage, 4126,
29240 /* 80933 */ GIR_EraseRootFromParent_Done,
29241 /* 80934 */ // Label 1618: @80934
29242 /* 80934 */ GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(81018), // Rule ID 4130 //
29243 /* 80939 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29244 /* 80944 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29245 /* 80947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29246 /* 80950 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29247 /* 80953 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29248 /* 80956 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29249 /* 80959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29250 /* 80963 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29251 /* 80967 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
29252 /* 80971 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29253 /* 80975 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29254 /* 80979 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3963:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
29255 /* 80979 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29256 /* 80982 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29257 /* 80986 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29258 /* 80991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8th),
29259 /* 80994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29260 /* 80996 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29261 /* 80998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29262 /* 81001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29263 /* 81007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29264 /* 81013 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29265 /* 81016 */ GIR_RootConstrainSelectedInstOperands,
29266 /* 81017 */ // GIR_Coverage, 4130,
29267 /* 81017 */ GIR_EraseRootFromParent_Done,
29268 /* 81018 */ // Label 1619: @81018
29269 /* 81018 */ GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(81102), // Rule ID 4134 //
29270 /* 81023 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29271 /* 81028 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29272 /* 81031 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29273 /* 81034 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29274 /* 81037 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29275 /* 81040 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29276 /* 81043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29277 /* 81047 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29278 /* 81051 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
29279 /* 81055 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29280 /* 81059 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29281 /* 81063 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3963:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
29282 /* 81063 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29283 /* 81066 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29284 /* 81070 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29285 /* 81075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16bh),
29286 /* 81078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29287 /* 81080 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29288 /* 81082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29289 /* 81085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29290 /* 81091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29291 /* 81097 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29292 /* 81100 */ GIR_RootConstrainSelectedInstOperands,
29293 /* 81101 */ // GIR_Coverage, 4134,
29294 /* 81101 */ GIR_EraseRootFromParent_Done,
29295 /* 81102 */ // Label 1620: @81102
29296 /* 81102 */ GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(81186), // Rule ID 4138 //
29297 /* 81107 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29298 /* 81112 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29299 /* 81115 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29300 /* 81118 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29301 /* 81121 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29302 /* 81124 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29303 /* 81127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29304 /* 81131 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29305 /* 81135 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
29306 /* 81139 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29307 /* 81143 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29308 /* 81147 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3963:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
29309 /* 81147 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29310 /* 81150 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29311 /* 81154 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29312 /* 81159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16th),
29313 /* 81162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29314 /* 81164 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29315 /* 81166 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29316 /* 81169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29317 /* 81175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29318 /* 81181 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29319 /* 81184 */ GIR_RootConstrainSelectedInstOperands,
29320 /* 81185 */ // GIR_Coverage, 4138,
29321 /* 81185 */ GIR_EraseRootFromParent_Done,
29322 /* 81186 */ // Label 1621: @81186
29323 /* 81186 */ GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(81275), // Rule ID 4878 //
29324 /* 81191 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29325 /* 81194 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29326 /* 81199 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29327 /* 81202 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29328 /* 81205 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29329 /* 81208 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29330 /* 81211 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29331 /* 81214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29332 /* 81218 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29333 /* 81222 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29334 /* 81226 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29335 /* 81230 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29336 /* 81234 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3913:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
29337 /* 81234 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29338 /* 81237 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29339 /* 81241 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29340 /* 81246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8),
29341 /* 81249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29342 /* 81251 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29343 /* 81253 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29344 /* 81255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29345 /* 81258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29346 /* 81264 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29347 /* 81270 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29348 /* 81273 */ GIR_RootConstrainSelectedInstOperands,
29349 /* 81274 */ // GIR_Coverage, 4878,
29350 /* 81274 */ GIR_EraseRootFromParent_Done,
29351 /* 81275 */ // Label 1622: @81275
29352 /* 81275 */ GIM_Try, /*On fail goto*//*Label 1623*/ GIMT_Encode4(81364), // Rule ID 4880 //
29353 /* 81280 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29354 /* 81283 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29355 /* 81288 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29356 /* 81291 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29357 /* 81294 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29358 /* 81297 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29359 /* 81300 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29360 /* 81303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29361 /* 81307 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29362 /* 81311 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29363 /* 81315 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29364 /* 81319 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29365 /* 81323 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3913:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
29366 /* 81323 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29367 /* 81326 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29368 /* 81330 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29369 /* 81335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs8),
29370 /* 81338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29371 /* 81340 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29372 /* 81342 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29373 /* 81344 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29374 /* 81347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29375 /* 81353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29376 /* 81359 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29377 /* 81362 */ GIR_RootConstrainSelectedInstOperands,
29378 /* 81363 */ // GIR_Coverage, 4880,
29379 /* 81363 */ GIR_EraseRootFromParent_Done,
29380 /* 81364 */ // Label 1623: @81364
29381 /* 81364 */ GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(81453), // Rule ID 4882 //
29382 /* 81369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29383 /* 81372 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29384 /* 81377 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29385 /* 81380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29386 /* 81383 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29387 /* 81386 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29388 /* 81389 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29389 /* 81392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29390 /* 81396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29391 /* 81400 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29392 /* 81404 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29393 /* 81408 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29394 /* 81412 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3913:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29395 /* 81412 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29396 /* 81415 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29397 /* 81419 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29398 /* 81424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16),
29399 /* 81427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29400 /* 81429 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29401 /* 81431 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29402 /* 81433 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29403 /* 81436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29404 /* 81442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29405 /* 81448 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29406 /* 81451 */ GIR_RootConstrainSelectedInstOperands,
29407 /* 81452 */ // GIR_Coverage, 4882,
29408 /* 81452 */ GIR_EraseRootFromParent_Done,
29409 /* 81453 */ // Label 1624: @81453
29410 /* 81453 */ GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(81542), // Rule ID 4884 //
29411 /* 81458 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29412 /* 81461 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29413 /* 81466 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29414 /* 81469 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29415 /* 81472 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29416 /* 81475 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29417 /* 81478 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29418 /* 81481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29419 /* 81485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29420 /* 81489 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29421 /* 81493 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29422 /* 81497 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29423 /* 81501 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3913:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29424 /* 81501 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29425 /* 81504 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29426 /* 81508 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29427 /* 81513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs16),
29428 /* 81516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29429 /* 81518 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29430 /* 81520 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29431 /* 81522 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29432 /* 81525 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29433 /* 81531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29434 /* 81537 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29435 /* 81540 */ GIR_RootConstrainSelectedInstOperands,
29436 /* 81541 */ // GIR_Coverage, 4884,
29437 /* 81541 */ GIR_EraseRootFromParent_Done,
29438 /* 81542 */ // Label 1625: @81542
29439 /* 81542 */ GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(81631), // Rule ID 4886 //
29440 /* 81547 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29441 /* 81550 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29442 /* 81555 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
29443 /* 81558 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29444 /* 81561 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29445 /* 81564 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29446 /* 81567 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29447 /* 81570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29448 /* 81574 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29449 /* 81578 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29450 /* 81582 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29451 /* 81586 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29452 /* 81590 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3913:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29453 /* 81590 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29454 /* 81593 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29455 /* 81597 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29456 /* 81602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs32),
29457 /* 81605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29458 /* 81607 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29459 /* 81609 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29460 /* 81611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29461 /* 81614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29462 /* 81620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29463 /* 81626 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29464 /* 81629 */ GIR_RootConstrainSelectedInstOperands,
29465 /* 81630 */ // GIR_Coverage, 4886,
29466 /* 81630 */ GIR_EraseRootFromParent_Done,
29467 /* 81631 */ // Label 1626: @81631
29468 /* 81631 */ GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(81720), // Rule ID 4888 //
29469 /* 81636 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29470 /* 81639 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29471 /* 81644 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
29472 /* 81647 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29473 /* 81650 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29474 /* 81653 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29475 /* 81656 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29476 /* 81659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29477 /* 81663 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29478 /* 81667 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29479 /* 81671 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29480 /* 81675 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29481 /* 81679 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3913:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29482 /* 81679 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29483 /* 81682 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29484 /* 81686 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29485 /* 81691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs32),
29486 /* 81694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29487 /* 81696 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29488 /* 81698 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29489 /* 81700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29490 /* 81703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29491 /* 81709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29492 /* 81715 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29493 /* 81718 */ GIR_RootConstrainSelectedInstOperands,
29494 /* 81719 */ // GIR_Coverage, 4888,
29495 /* 81719 */ GIR_EraseRootFromParent_Done,
29496 /* 81720 */ // Label 1627: @81720
29497 /* 81720 */ GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(81809), // Rule ID 4890 //
29498 /* 81725 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29499 /* 81728 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29500 /* 81733 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29501 /* 81736 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29502 /* 81739 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29503 /* 81742 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29504 /* 81745 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29505 /* 81748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29506 /* 81752 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29507 /* 81756 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29508 /* 81760 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29509 /* 81764 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29510 /* 81768 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3913:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
29511 /* 81768 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29512 /* 81771 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29513 /* 81775 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29514 /* 81780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu8),
29515 /* 81783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29516 /* 81785 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29517 /* 81787 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29518 /* 81789 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29519 /* 81792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29520 /* 81798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29521 /* 81804 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29522 /* 81807 */ GIR_RootConstrainSelectedInstOperands,
29523 /* 81808 */ // GIR_Coverage, 4890,
29524 /* 81808 */ GIR_EraseRootFromParent_Done,
29525 /* 81809 */ // Label 1628: @81809
29526 /* 81809 */ GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(81898), // Rule ID 4892 //
29527 /* 81814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29528 /* 81817 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29529 /* 81822 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29530 /* 81825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29531 /* 81828 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29532 /* 81831 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29533 /* 81834 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29534 /* 81837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29535 /* 81841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29536 /* 81845 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29537 /* 81849 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29538 /* 81853 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29539 /* 81857 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3913:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
29540 /* 81857 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29541 /* 81860 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29542 /* 81864 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29543 /* 81869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu8),
29544 /* 81872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29545 /* 81874 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29546 /* 81876 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29547 /* 81878 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29548 /* 81881 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29549 /* 81887 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29550 /* 81893 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29551 /* 81896 */ GIR_RootConstrainSelectedInstOperands,
29552 /* 81897 */ // GIR_Coverage, 4892,
29553 /* 81897 */ GIR_EraseRootFromParent_Done,
29554 /* 81898 */ // Label 1629: @81898
29555 /* 81898 */ GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(81987), // Rule ID 4894 //
29556 /* 81903 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29557 /* 81906 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29558 /* 81911 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29559 /* 81914 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29560 /* 81917 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29561 /* 81920 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29562 /* 81923 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29563 /* 81926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29564 /* 81930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29565 /* 81934 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29566 /* 81938 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29567 /* 81942 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29568 /* 81946 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3913:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29569 /* 81946 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29570 /* 81949 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29571 /* 81953 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29572 /* 81958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu16),
29573 /* 81961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29574 /* 81963 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29575 /* 81965 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29576 /* 81967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29577 /* 81970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29578 /* 81976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29579 /* 81982 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29580 /* 81985 */ GIR_RootConstrainSelectedInstOperands,
29581 /* 81986 */ // GIR_Coverage, 4894,
29582 /* 81986 */ GIR_EraseRootFromParent_Done,
29583 /* 81987 */ // Label 1630: @81987
29584 /* 81987 */ GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(82076), // Rule ID 4896 //
29585 /* 81992 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29586 /* 81995 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29587 /* 82000 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29588 /* 82003 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29589 /* 82006 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29590 /* 82009 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29591 /* 82012 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29592 /* 82015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29593 /* 82019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29594 /* 82023 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29595 /* 82027 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29596 /* 82031 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29597 /* 82035 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3913:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29598 /* 82035 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29599 /* 82038 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29600 /* 82042 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29601 /* 82047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu16),
29602 /* 82050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29603 /* 82052 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29604 /* 82054 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29605 /* 82056 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29606 /* 82059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29607 /* 82065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29608 /* 82071 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29609 /* 82074 */ GIR_RootConstrainSelectedInstOperands,
29610 /* 82075 */ // GIR_Coverage, 4896,
29611 /* 82075 */ GIR_EraseRootFromParent_Done,
29612 /* 82076 */ // Label 1631: @82076
29613 /* 82076 */ GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(82165), // Rule ID 4898 //
29614 /* 82081 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29615 /* 82084 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29616 /* 82089 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
29617 /* 82092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29618 /* 82095 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29619 /* 82098 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29620 /* 82101 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29621 /* 82104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29622 /* 82108 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29623 /* 82112 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29624 /* 82116 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29625 /* 82120 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29626 /* 82124 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3913:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29627 /* 82124 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29628 /* 82127 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29629 /* 82131 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29630 /* 82136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu32),
29631 /* 82139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29632 /* 82141 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29633 /* 82143 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29634 /* 82145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29635 /* 82148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29636 /* 82154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29637 /* 82160 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29638 /* 82163 */ GIR_RootConstrainSelectedInstOperands,
29639 /* 82164 */ // GIR_Coverage, 4898,
29640 /* 82164 */ GIR_EraseRootFromParent_Done,
29641 /* 82165 */ // Label 1632: @82165
29642 /* 82165 */ GIM_Try, /*On fail goto*//*Label 1633*/ GIMT_Encode4(82254), // Rule ID 4900 //
29643 /* 82170 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29644 /* 82173 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29645 /* 82178 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
29646 /* 82181 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29647 /* 82184 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29648 /* 82187 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29649 /* 82190 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29650 /* 82193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29651 /* 82197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29652 /* 82201 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29653 /* 82205 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29654 /* 82209 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29655 /* 82213 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3913:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29656 /* 82213 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29657 /* 82216 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29658 /* 82220 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29659 /* 82225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu32),
29660 /* 82228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29661 /* 82230 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29662 /* 82232 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29663 /* 82234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29664 /* 82237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29665 /* 82243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29666 /* 82249 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29667 /* 82252 */ GIR_RootConstrainSelectedInstOperands,
29668 /* 82253 */ // GIR_Coverage, 4900,
29669 /* 82253 */ GIR_EraseRootFromParent_Done,
29670 /* 82254 */ // Label 1633: @82254
29671 /* 82254 */ GIM_Try, /*On fail goto*//*Label 1634*/ GIMT_Encode4(82352), // Rule ID 4463 //
29672 /* 82259 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
29673 /* 82262 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29674 /* 82267 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29675 /* 82270 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29676 /* 82273 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29677 /* 82276 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
29678 /* 82279 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
29679 /* 82282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29680 /* 82286 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29681 /* 82290 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29682 /* 82294 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29683 /* 82298 */ // MIs[1] Operand 1
29684 /* 82298 */ // No operand predicates
29685 /* 82298 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29686 /* 82302 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29687 /* 82306 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
29688 /* 82308 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3851:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
29689 /* 82308 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29690 /* 82311 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29691 /* 82315 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29692 /* 82320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf16),
29693 /* 82323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29694 /* 82325 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29695 /* 82327 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29696 /* 82329 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29697 /* 82332 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29698 /* 82335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29699 /* 82341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29700 /* 82347 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29701 /* 82350 */ GIR_RootConstrainSelectedInstOperands,
29702 /* 82351 */ // GIR_Coverage, 4463,
29703 /* 82351 */ GIR_EraseRootFromParent_Done,
29704 /* 82352 */ // Label 1634: @82352
29705 /* 82352 */ GIM_Try, /*On fail goto*//*Label 1635*/ GIMT_Encode4(82450), // Rule ID 4465 //
29706 /* 82357 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
29707 /* 82360 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29708 /* 82365 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29709 /* 82368 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29710 /* 82371 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29711 /* 82374 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
29712 /* 82377 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
29713 /* 82380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29714 /* 82384 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29715 /* 82388 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29716 /* 82392 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29717 /* 82396 */ // MIs[1] Operand 1
29718 /* 82396 */ // No operand predicates
29719 /* 82396 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29720 /* 82400 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29721 /* 82404 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
29722 /* 82406 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3851:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
29723 /* 82406 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29724 /* 82409 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29725 /* 82413 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29726 /* 82418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf32),
29727 /* 82421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29728 /* 82423 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29729 /* 82425 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29730 /* 82427 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29731 /* 82430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29732 /* 82433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29733 /* 82439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29734 /* 82445 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29735 /* 82448 */ GIR_RootConstrainSelectedInstOperands,
29736 /* 82449 */ // GIR_Coverage, 4465,
29737 /* 82449 */ GIR_EraseRootFromParent_Done,
29738 /* 82450 */ // Label 1635: @82450
29739 /* 82450 */ GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(82548), // Rule ID 5032 //
29740 /* 82455 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29741 /* 82458 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29742 /* 82463 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
29743 /* 82466 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29744 /* 82469 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29745 /* 82472 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29746 /* 82475 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8,
29747 /* 82478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29748 /* 82482 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29749 /* 82486 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29750 /* 82490 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29751 /* 82494 */ // MIs[1] Operand 1
29752 /* 82494 */ // No operand predicates
29753 /* 82494 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29754 /* 82498 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29755 /* 82502 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
29756 /* 82504 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3851:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VCADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
29757 /* 82504 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29758 /* 82507 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29759 /* 82511 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29760 /* 82516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi8),
29761 /* 82519 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29762 /* 82521 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29763 /* 82523 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29764 /* 82525 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29765 /* 82528 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29766 /* 82531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29767 /* 82537 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29768 /* 82543 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29769 /* 82546 */ GIR_RootConstrainSelectedInstOperands,
29770 /* 82547 */ // GIR_Coverage, 5032,
29771 /* 82547 */ GIR_EraseRootFromParent_Done,
29772 /* 82548 */ // Label 1636: @82548
29773 /* 82548 */ GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(82646), // Rule ID 5034 //
29774 /* 82553 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29775 /* 82556 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29776 /* 82561 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29777 /* 82564 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29778 /* 82567 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29779 /* 82570 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
29780 /* 82573 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
29781 /* 82576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29782 /* 82580 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29783 /* 82584 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29784 /* 82588 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29785 /* 82592 */ // MIs[1] Operand 1
29786 /* 82592 */ // No operand predicates
29787 /* 82592 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29788 /* 82596 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29789 /* 82600 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
29790 /* 82602 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3851:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VCADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
29791 /* 82602 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29792 /* 82605 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29793 /* 82609 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29794 /* 82614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi16),
29795 /* 82617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29796 /* 82619 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29797 /* 82621 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29798 /* 82623 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29799 /* 82626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29800 /* 82629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29801 /* 82635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29802 /* 82641 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29803 /* 82644 */ GIR_RootConstrainSelectedInstOperands,
29804 /* 82645 */ // GIR_Coverage, 5034,
29805 /* 82645 */ GIR_EraseRootFromParent_Done,
29806 /* 82646 */ // Label 1637: @82646
29807 /* 82646 */ GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(82744), // Rule ID 5036 //
29808 /* 82651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29809 /* 82654 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29810 /* 82659 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29811 /* 82662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29812 /* 82665 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29813 /* 82668 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
29814 /* 82671 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
29815 /* 82674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29816 /* 82678 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29817 /* 82682 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29818 /* 82686 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29819 /* 82690 */ // MIs[1] Operand 1
29820 /* 82690 */ // No operand predicates
29821 /* 82690 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29822 /* 82694 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29823 /* 82698 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
29824 /* 82700 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3851:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VCADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
29825 /* 82700 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29826 /* 82703 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29827 /* 82707 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29828 /* 82712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi32),
29829 /* 82715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29830 /* 82717 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29831 /* 82719 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29832 /* 82721 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29833 /* 82724 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29834 /* 82727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29835 /* 82733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29836 /* 82739 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29837 /* 82742 */ GIR_RootConstrainSelectedInstOperands,
29838 /* 82743 */ // GIR_Coverage, 5036,
29839 /* 82743 */ GIR_EraseRootFromParent_Done,
29840 /* 82744 */ // Label 1638: @82744
29841 /* 82744 */ GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(82842), // Rule ID 5038 //
29842 /* 82749 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29843 /* 82752 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29844 /* 82757 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
29845 /* 82760 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29846 /* 82763 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29847 /* 82766 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29848 /* 82769 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8,
29849 /* 82772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29850 /* 82776 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29851 /* 82780 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29852 /* 82784 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29853 /* 82788 */ // MIs[1] Operand 1
29854 /* 82788 */ // No operand predicates
29855 /* 82788 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29856 /* 82792 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29857 /* 82796 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
29858 /* 82798 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3851:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VHCADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
29859 /* 82798 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29860 /* 82801 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29861 /* 82805 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29862 /* 82810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs8),
29863 /* 82813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29864 /* 82815 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29865 /* 82817 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29866 /* 82819 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29867 /* 82822 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29868 /* 82825 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29869 /* 82831 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29870 /* 82837 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29871 /* 82840 */ GIR_RootConstrainSelectedInstOperands,
29872 /* 82841 */ // GIR_Coverage, 5038,
29873 /* 82841 */ GIR_EraseRootFromParent_Done,
29874 /* 82842 */ // Label 1639: @82842
29875 /* 82842 */ GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(82940), // Rule ID 5040 //
29876 /* 82847 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29877 /* 82850 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29878 /* 82855 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29879 /* 82858 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29880 /* 82861 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29881 /* 82864 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
29882 /* 82867 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
29883 /* 82870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29884 /* 82874 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29885 /* 82878 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29886 /* 82882 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29887 /* 82886 */ // MIs[1] Operand 1
29888 /* 82886 */ // No operand predicates
29889 /* 82886 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29890 /* 82890 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29891 /* 82894 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
29892 /* 82896 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3851:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VHCADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
29893 /* 82896 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29894 /* 82899 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29895 /* 82903 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29896 /* 82908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs16),
29897 /* 82911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29898 /* 82913 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29899 /* 82915 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29900 /* 82917 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29901 /* 82920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29902 /* 82923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29903 /* 82929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29904 /* 82935 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29905 /* 82938 */ GIR_RootConstrainSelectedInstOperands,
29906 /* 82939 */ // GIR_Coverage, 5040,
29907 /* 82939 */ GIR_EraseRootFromParent_Done,
29908 /* 82940 */ // Label 1640: @82940
29909 /* 82940 */ GIM_Try, /*On fail goto*//*Label 1641*/ GIMT_Encode4(83038), // Rule ID 5042 //
29910 /* 82945 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29911 /* 82948 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29912 /* 82953 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29913 /* 82956 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29914 /* 82959 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29915 /* 82962 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
29916 /* 82965 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
29917 /* 82968 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29918 /* 82972 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29919 /* 82976 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29920 /* 82980 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29921 /* 82984 */ // MIs[1] Operand 1
29922 /* 82984 */ // No operand predicates
29923 /* 82984 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29924 /* 82988 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29925 /* 82992 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
29926 /* 82994 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3851:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VHCADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
29927 /* 82994 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29928 /* 82997 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29929 /* 83001 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29930 /* 83006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs32),
29931 /* 83009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29932 /* 83011 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29933 /* 83013 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29934 /* 83015 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29935 /* 83018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29936 /* 83021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29937 /* 83027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29938 /* 83033 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29939 /* 83036 */ GIR_RootConstrainSelectedInstOperands,
29940 /* 83037 */ // GIR_Coverage, 5042,
29941 /* 83037 */ GIR_EraseRootFromParent_Done,
29942 /* 83038 */ // Label 1641: @83038
29943 /* 83038 */ GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(83114), // Rule ID 3414 //
29944 /* 83043 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29945 /* 83046 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
29946 /* 83051 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
29947 /* 83054 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29948 /* 83057 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29949 /* 83060 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
29950 /* 83063 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8,
29951 /* 83066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29952 /* 83070 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29953 /* 83074 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29954 /* 83078 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29955 /* 83082 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29956 /* 83086 */ // (intrinsic_wo_chain:{ *:[i32] } 3843:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
29957 /* 83086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs8),
29958 /* 83089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
29959 /* 83091 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
29960 /* 83093 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29961 /* 83095 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29962 /* 83097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29963 /* 83100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29964 /* 83106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29965 /* 83112 */ GIR_RootConstrainSelectedInstOperands,
29966 /* 83113 */ // GIR_Coverage, 3414,
29967 /* 83113 */ GIR_EraseRootFromParent_Done,
29968 /* 83114 */ // Label 1642: @83114
29969 /* 83114 */ GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(83190), // Rule ID 3416 //
29970 /* 83119 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29971 /* 83122 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
29972 /* 83127 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
29973 /* 83130 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29974 /* 83133 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29975 /* 83136 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
29976 /* 83139 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
29977 /* 83142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29978 /* 83146 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29979 /* 83150 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29980 /* 83154 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29981 /* 83158 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29982 /* 83162 */ // (intrinsic_wo_chain:{ *:[i32] } 3843:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
29983 /* 83162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs16),
29984 /* 83165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
29985 /* 83167 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
29986 /* 83169 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29987 /* 83171 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29988 /* 83173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29989 /* 83176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29990 /* 83182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29991 /* 83188 */ GIR_RootConstrainSelectedInstOperands,
29992 /* 83189 */ // GIR_Coverage, 3416,
29993 /* 83189 */ GIR_EraseRootFromParent_Done,
29994 /* 83190 */ // Label 1643: @83190
29995 /* 83190 */ GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(83266), // Rule ID 3418 //
29996 /* 83195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29997 /* 83198 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
29998 /* 83203 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
29999 /* 83206 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30000 /* 83209 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30001 /* 83212 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
30002 /* 83215 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
30003 /* 83218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30004 /* 83222 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30005 /* 83226 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30006 /* 83230 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30007 /* 83234 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30008 /* 83238 */ // (intrinsic_wo_chain:{ *:[i32] } 3843:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
30009 /* 83238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs32),
30010 /* 83241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
30011 /* 83243 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
30012 /* 83245 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30013 /* 83247 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30014 /* 83249 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30015 /* 83252 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30016 /* 83258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30017 /* 83264 */ GIR_RootConstrainSelectedInstOperands,
30018 /* 83265 */ // GIR_Coverage, 3418,
30019 /* 83265 */ GIR_EraseRootFromParent_Done,
30020 /* 83266 */ // Label 1644: @83266
30021 /* 83266 */ GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(83342), // Rule ID 3420 //
30022 /* 83271 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
30023 /* 83274 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
30024 /* 83279 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
30025 /* 83282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30026 /* 83285 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30027 /* 83288 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30028 /* 83291 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8,
30029 /* 83294 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30030 /* 83298 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30031 /* 83302 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30032 /* 83306 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30033 /* 83310 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30034 /* 83314 */ // (intrinsic_wo_chain:{ *:[i32] } 3843:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVu8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30035 /* 83314 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu8),
30036 /* 83317 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
30037 /* 83319 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
30038 /* 83321 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30039 /* 83323 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30040 /* 83325 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30041 /* 83328 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30042 /* 83334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30043 /* 83340 */ GIR_RootConstrainSelectedInstOperands,
30044 /* 83341 */ // GIR_Coverage, 3420,
30045 /* 83341 */ GIR_EraseRootFromParent_Done,
30046 /* 83342 */ // Label 1645: @83342
30047 /* 83342 */ GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(83418), // Rule ID 3422 //
30048 /* 83347 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
30049 /* 83350 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
30050 /* 83355 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
30051 /* 83358 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30052 /* 83361 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30053 /* 83364 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
30054 /* 83367 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
30055 /* 83370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30056 /* 83374 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30057 /* 83378 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30058 /* 83382 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30059 /* 83386 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30060 /* 83390 */ // (intrinsic_wo_chain:{ *:[i32] } 3843:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVu16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30061 /* 83390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu16),
30062 /* 83393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
30063 /* 83395 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
30064 /* 83397 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30065 /* 83399 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30066 /* 83401 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30067 /* 83404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30068 /* 83410 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30069 /* 83416 */ GIR_RootConstrainSelectedInstOperands,
30070 /* 83417 */ // GIR_Coverage, 3422,
30071 /* 83417 */ GIR_EraseRootFromParent_Done,
30072 /* 83418 */ // Label 1646: @83418
30073 /* 83418 */ GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(83494), // Rule ID 3424 //
30074 /* 83423 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
30075 /* 83426 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
30076 /* 83431 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
30077 /* 83434 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30078 /* 83437 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30079 /* 83440 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
30080 /* 83443 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
30081 /* 83446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30082 /* 83450 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30083 /* 83454 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30084 /* 83458 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30085 /* 83462 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30086 /* 83466 */ // (intrinsic_wo_chain:{ *:[i32] } 3843:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVu32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
30087 /* 83466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu32),
30088 /* 83469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
30089 /* 83471 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
30090 /* 83473 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30091 /* 83475 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30092 /* 83477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30093 /* 83480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30094 /* 83486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30095 /* 83492 */ GIR_RootConstrainSelectedInstOperands,
30096 /* 83493 */ // GIR_Coverage, 3424,
30097 /* 83493 */ GIR_EraseRootFromParent_Done,
30098 /* 83494 */ // Label 1647: @83494
30099 /* 83494 */ GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(83579), // Rule ID 4409 //
30100 /* 83499 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
30101 /* 83502 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq),
30102 /* 83507 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30103 /* 83510 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30104 /* 83513 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
30105 /* 83516 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
30106 /* 83519 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
30107 /* 83522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30108 /* 83526 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
30109 /* 83530 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30110 /* 83534 */ // MIs[1] Operand 1
30111 /* 83534 */ // No operand predicates
30112 /* 83534 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30113 /* 83538 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30114 /* 83542 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30115 /* 83546 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
30116 /* 83548 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3854:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
30117 /* 83548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf16),
30118 /* 83551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30119 /* 83553 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src
30120 /* 83555 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30121 /* 83557 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30122 /* 83559 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
30123 /* 83562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30124 /* 83565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30125 /* 83571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30126 /* 83577 */ GIR_RootConstrainSelectedInstOperands,
30127 /* 83578 */ // GIR_Coverage, 4409,
30128 /* 83578 */ GIR_EraseRootFromParent_Done,
30129 /* 83579 */ // Label 1648: @83579
30130 /* 83579 */ GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(83664), // Rule ID 4412 //
30131 /* 83584 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
30132 /* 83587 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq),
30133 /* 83592 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30134 /* 83595 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30135 /* 83598 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30136 /* 83601 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
30137 /* 83604 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
30138 /* 83607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30139 /* 83611 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
30140 /* 83615 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30141 /* 83619 */ // MIs[1] Operand 1
30142 /* 83619 */ // No operand predicates
30143 /* 83619 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30144 /* 83623 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30145 /* 83627 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30146 /* 83631 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
30147 /* 83633 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3854:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
30148 /* 83633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf32),
30149 /* 83636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30150 /* 83638 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src
30151 /* 83640 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30152 /* 83642 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30153 /* 83644 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
30154 /* 83647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30155 /* 83650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30156 /* 83656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30157 /* 83662 */ GIR_RootConstrainSelectedInstOperands,
30158 /* 83663 */ // GIR_Coverage, 4412,
30159 /* 83663 */ GIR_EraseRootFromParent_Done,
30160 /* 83664 */ // Label 1649: @83664
30161 /* 83664 */ GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(83760), // Rule ID 3063 //
30162 /* 83669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
30163 /* 83672 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx2),
30164 /* 83677 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
30165 /* 83680 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
30166 /* 83683 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
30167 /* 83686 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
30168 /* 83689 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
30169 /* 83692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
30170 /* 83696 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4115:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vm) => (VTBX2:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v16i8] } DPair:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
30171 /* 83696 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
30172 /* 83699 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
30173 /* 83703 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30174 /* 83708 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
30175 /* 83712 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
30176 /* 83715 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
30177 /* 83719 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
30178 /* 83722 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
30179 /* 83727 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
30180 /* 83732 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
30181 /* 83737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX2),
30182 /* 83740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
30183 /* 83742 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
30184 /* 83744 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30185 /* 83747 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm
30186 /* 83749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
30187 /* 83752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30188 /* 83758 */ GIR_RootConstrainSelectedInstOperands,
30189 /* 83759 */ // GIR_Coverage, 3063,
30190 /* 83759 */ GIR_EraseRootFromParent_Done,
30191 /* 83760 */ // Label 1650: @83760
30192 /* 83760 */ GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(83891), // Rule ID 3064 //
30193 /* 83765 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
30194 /* 83768 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl3),
30195 /* 83773 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
30196 /* 83776 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
30197 /* 83779 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
30198 /* 83782 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
30199 /* 83785 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
30200 /* 83788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
30201 /* 83792 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4112:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBL3Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
30202 /* 83792 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
30203 /* 83795 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30204 /* 83799 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30205 /* 83804 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
30206 /* 83806 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
30207 /* 83809 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
30208 /* 83813 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30209 /* 83818 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
30210 /* 83822 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
30211 /* 83825 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
30212 /* 83829 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
30213 /* 83832 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
30214 /* 83836 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
30215 /* 83839 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
30216 /* 83842 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
30217 /* 83845 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
30218 /* 83850 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
30219 /* 83855 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
30220 /* 83860 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
30221 /* 83865 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
30222 /* 83870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL3Pseudo),
30223 /* 83873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
30224 /* 83875 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30225 /* 83878 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm
30226 /* 83880 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
30227 /* 83883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30228 /* 83889 */ GIR_RootConstrainSelectedInstOperands,
30229 /* 83890 */ // GIR_Coverage, 3064,
30230 /* 83890 */ GIR_EraseRootFromParent_Done,
30231 /* 83891 */ // Label 1651: @83891
30232 /* 83891 */ GIM_Reject,
30233 /* 83892 */ // Label 1613: @83892
30234 /* 83892 */ GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(89198),
30235 /* 83897 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
30236 /* 83900 */ GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(83993), // Rule ID 4221 //
30237 /* 83905 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30238 /* 83910 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30239 /* 83913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30240 /* 83916 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30241 /* 83919 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30242 /* 83922 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30243 /* 83925 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30244 /* 83928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30245 /* 83932 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30246 /* 83936 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30247 /* 83940 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30248 /* 83944 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30249 /* 83948 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30250 /* 83952 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30251 /* 83952 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30252 /* 83955 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30253 /* 83959 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30254 /* 83964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs8),
30255 /* 83967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30256 /* 83969 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30257 /* 83971 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30258 /* 83973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30259 /* 83976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30260 /* 83982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30261 /* 83988 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30262 /* 83991 */ GIR_RootConstrainSelectedInstOperands,
30263 /* 83992 */ // GIR_Coverage, 4221,
30264 /* 83992 */ GIR_EraseRootFromParent_Done,
30265 /* 83993 */ // Label 1653: @83993
30266 /* 83993 */ GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(84086), // Rule ID 4223 //
30267 /* 83998 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30268 /* 84003 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30269 /* 84006 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30270 /* 84009 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
30271 /* 84012 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30272 /* 84015 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30273 /* 84018 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30274 /* 84021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30275 /* 84025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30276 /* 84029 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30277 /* 84033 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30278 /* 84037 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30279 /* 84041 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30280 /* 84045 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30281 /* 84045 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30282 /* 84048 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30283 /* 84052 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30284 /* 84057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs16),
30285 /* 84060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30286 /* 84062 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30287 /* 84064 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30288 /* 84066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30289 /* 84069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30290 /* 84075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30291 /* 84081 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30292 /* 84084 */ GIR_RootConstrainSelectedInstOperands,
30293 /* 84085 */ // GIR_Coverage, 4223,
30294 /* 84085 */ GIR_EraseRootFromParent_Done,
30295 /* 84086 */ // Label 1654: @84086
30296 /* 84086 */ GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(84179), // Rule ID 4225 //
30297 /* 84091 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30298 /* 84096 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30299 /* 84099 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
30300 /* 84102 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30301 /* 84105 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30302 /* 84108 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30303 /* 84111 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30304 /* 84114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30305 /* 84118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30306 /* 84122 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30307 /* 84126 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30308 /* 84130 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30309 /* 84134 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30310 /* 84138 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3959:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30311 /* 84138 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30312 /* 84141 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30313 /* 84145 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30314 /* 84150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs32),
30315 /* 84153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30316 /* 84155 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30317 /* 84157 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30318 /* 84159 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30319 /* 84162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30320 /* 84168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30321 /* 84174 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30322 /* 84177 */ GIR_RootConstrainSelectedInstOperands,
30323 /* 84178 */ // GIR_Coverage, 4225,
30324 /* 84178 */ GIR_EraseRootFromParent_Done,
30325 /* 84179 */ // Label 1655: @84179
30326 /* 84179 */ GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(84272), // Rule ID 4227 //
30327 /* 84184 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30328 /* 84189 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30329 /* 84192 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30330 /* 84195 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30331 /* 84198 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30332 /* 84201 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30333 /* 84204 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30334 /* 84207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30335 /* 84211 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30336 /* 84215 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30337 /* 84219 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30338 /* 84223 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30339 /* 84227 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30340 /* 84231 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30341 /* 84231 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30342 /* 84234 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30343 /* 84238 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30344 /* 84243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu8),
30345 /* 84246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30346 /* 84248 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30347 /* 84250 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30348 /* 84252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30349 /* 84255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30350 /* 84261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30351 /* 84267 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30352 /* 84270 */ GIR_RootConstrainSelectedInstOperands,
30353 /* 84271 */ // GIR_Coverage, 4227,
30354 /* 84271 */ GIR_EraseRootFromParent_Done,
30355 /* 84272 */ // Label 1656: @84272
30356 /* 84272 */ GIM_Try, /*On fail goto*//*Label 1657*/ GIMT_Encode4(84365), // Rule ID 4229 //
30357 /* 84277 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30358 /* 84282 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30359 /* 84285 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30360 /* 84288 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
30361 /* 84291 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30362 /* 84294 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30363 /* 84297 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30364 /* 84300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30365 /* 84304 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30366 /* 84308 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30367 /* 84312 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30368 /* 84316 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30369 /* 84320 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30370 /* 84324 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30371 /* 84324 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30372 /* 84327 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30373 /* 84331 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30374 /* 84336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu16),
30375 /* 84339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30376 /* 84341 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30377 /* 84343 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30378 /* 84345 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30379 /* 84348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30380 /* 84354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30381 /* 84360 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30382 /* 84363 */ GIR_RootConstrainSelectedInstOperands,
30383 /* 84364 */ // GIR_Coverage, 4229,
30384 /* 84364 */ GIR_EraseRootFromParent_Done,
30385 /* 84365 */ // Label 1657: @84365
30386 /* 84365 */ GIM_Try, /*On fail goto*//*Label 1658*/ GIMT_Encode4(84458), // Rule ID 4231 //
30387 /* 84370 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30388 /* 84375 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30389 /* 84378 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
30390 /* 84381 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30391 /* 84384 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30392 /* 84387 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30393 /* 84390 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30394 /* 84393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30395 /* 84397 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30396 /* 84401 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30397 /* 84405 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30398 /* 84409 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30399 /* 84413 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30400 /* 84417 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3959:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30401 /* 84417 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30402 /* 84420 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30403 /* 84424 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30404 /* 84429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu32),
30405 /* 84432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30406 /* 84434 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30407 /* 84436 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30408 /* 84438 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30409 /* 84441 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30410 /* 84447 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30411 /* 84453 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30412 /* 84456 */ GIR_RootConstrainSelectedInstOperands,
30413 /* 84457 */ // GIR_Coverage, 4231,
30414 /* 84457 */ GIR_EraseRootFromParent_Done,
30415 /* 84458 */ // Label 1658: @84458
30416 /* 84458 */ GIM_Try, /*On fail goto*//*Label 1659*/ GIMT_Encode4(84551), // Rule ID 4233 //
30417 /* 84463 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30418 /* 84468 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30419 /* 84471 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30420 /* 84474 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30421 /* 84477 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30422 /* 84480 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30423 /* 84483 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30424 /* 84486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30425 /* 84490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30426 /* 84494 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30427 /* 84498 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30428 /* 84502 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30429 /* 84506 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30430 /* 84510 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30431 /* 84510 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30432 /* 84513 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30433 /* 84517 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30434 /* 84522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs8),
30435 /* 84525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30436 /* 84527 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30437 /* 84529 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30438 /* 84531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30439 /* 84534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30440 /* 84540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30441 /* 84546 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30442 /* 84549 */ GIR_RootConstrainSelectedInstOperands,
30443 /* 84550 */ // GIR_Coverage, 4233,
30444 /* 84550 */ GIR_EraseRootFromParent_Done,
30445 /* 84551 */ // Label 1659: @84551
30446 /* 84551 */ GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(84644), // Rule ID 4235 //
30447 /* 84556 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30448 /* 84561 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30449 /* 84564 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30450 /* 84567 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
30451 /* 84570 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30452 /* 84573 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30453 /* 84576 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30454 /* 84579 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30455 /* 84583 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30456 /* 84587 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30457 /* 84591 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30458 /* 84595 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30459 /* 84599 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30460 /* 84603 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30461 /* 84603 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30462 /* 84606 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30463 /* 84610 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30464 /* 84615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs16),
30465 /* 84618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30466 /* 84620 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30467 /* 84622 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30468 /* 84624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30469 /* 84627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30470 /* 84633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30471 /* 84639 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30472 /* 84642 */ GIR_RootConstrainSelectedInstOperands,
30473 /* 84643 */ // GIR_Coverage, 4235,
30474 /* 84643 */ GIR_EraseRootFromParent_Done,
30475 /* 84644 */ // Label 1660: @84644
30476 /* 84644 */ GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(84737), // Rule ID 4237 //
30477 /* 84649 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30478 /* 84654 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30479 /* 84657 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
30480 /* 84660 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30481 /* 84663 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30482 /* 84666 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30483 /* 84669 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30484 /* 84672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30485 /* 84676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30486 /* 84680 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30487 /* 84684 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30488 /* 84688 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30489 /* 84692 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30490 /* 84696 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3959:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30491 /* 84696 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30492 /* 84699 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30493 /* 84703 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30494 /* 84708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs32),
30495 /* 84711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30496 /* 84713 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30497 /* 84715 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30498 /* 84717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30499 /* 84720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30500 /* 84726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30501 /* 84732 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30502 /* 84735 */ GIR_RootConstrainSelectedInstOperands,
30503 /* 84736 */ // GIR_Coverage, 4237,
30504 /* 84736 */ GIR_EraseRootFromParent_Done,
30505 /* 84737 */ // Label 1661: @84737
30506 /* 84737 */ GIM_Try, /*On fail goto*//*Label 1662*/ GIMT_Encode4(84830), // Rule ID 4239 //
30507 /* 84742 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30508 /* 84747 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30509 /* 84750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30510 /* 84753 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30511 /* 84756 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30512 /* 84759 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30513 /* 84762 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30514 /* 84765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30515 /* 84769 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30516 /* 84773 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30517 /* 84777 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30518 /* 84781 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30519 /* 84785 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30520 /* 84789 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30521 /* 84789 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30522 /* 84792 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30523 /* 84796 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30524 /* 84801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu8),
30525 /* 84804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30526 /* 84806 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30527 /* 84808 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30528 /* 84810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30529 /* 84813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30530 /* 84819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30531 /* 84825 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30532 /* 84828 */ GIR_RootConstrainSelectedInstOperands,
30533 /* 84829 */ // GIR_Coverage, 4239,
30534 /* 84829 */ GIR_EraseRootFromParent_Done,
30535 /* 84830 */ // Label 1662: @84830
30536 /* 84830 */ GIM_Try, /*On fail goto*//*Label 1663*/ GIMT_Encode4(84923), // Rule ID 4241 //
30537 /* 84835 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30538 /* 84840 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30539 /* 84843 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30540 /* 84846 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
30541 /* 84849 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30542 /* 84852 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30543 /* 84855 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30544 /* 84858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30545 /* 84862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30546 /* 84866 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30547 /* 84870 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30548 /* 84874 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30549 /* 84878 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30550 /* 84882 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30551 /* 84882 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30552 /* 84885 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30553 /* 84889 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30554 /* 84894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu16),
30555 /* 84897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30556 /* 84899 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30557 /* 84901 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30558 /* 84903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30559 /* 84906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30560 /* 84912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30561 /* 84918 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30562 /* 84921 */ GIR_RootConstrainSelectedInstOperands,
30563 /* 84922 */ // GIR_Coverage, 4241,
30564 /* 84922 */ GIR_EraseRootFromParent_Done,
30565 /* 84923 */ // Label 1663: @84923
30566 /* 84923 */ GIM_Try, /*On fail goto*//*Label 1664*/ GIMT_Encode4(85016), // Rule ID 4243 //
30567 /* 84928 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30568 /* 84933 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30569 /* 84936 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
30570 /* 84939 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30571 /* 84942 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30572 /* 84945 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30573 /* 84948 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30574 /* 84951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30575 /* 84955 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30576 /* 84959 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30577 /* 84963 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30578 /* 84967 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30579 /* 84971 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30580 /* 84975 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3959:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30581 /* 84975 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30582 /* 84978 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30583 /* 84982 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30584 /* 84987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu32),
30585 /* 84990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30586 /* 84992 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30587 /* 84994 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30588 /* 84996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30589 /* 84999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30590 /* 85005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30591 /* 85011 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30592 /* 85014 */ GIR_RootConstrainSelectedInstOperands,
30593 /* 85015 */ // GIR_Coverage, 4243,
30594 /* 85015 */ GIR_EraseRootFromParent_Done,
30595 /* 85016 */ // Label 1664: @85016
30596 /* 85016 */ GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(85109), // Rule ID 4245 //
30597 /* 85021 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30598 /* 85026 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30599 /* 85029 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30600 /* 85032 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30601 /* 85035 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30602 /* 85038 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30603 /* 85041 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30604 /* 85044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30605 /* 85048 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30606 /* 85052 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30607 /* 85056 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30608 /* 85060 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30609 /* 85064 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30610 /* 85068 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30611 /* 85068 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30612 /* 85071 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30613 /* 85075 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30614 /* 85080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs8),
30615 /* 85083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30616 /* 85085 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30617 /* 85087 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30618 /* 85089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30619 /* 85092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30620 /* 85098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30621 /* 85104 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30622 /* 85107 */ GIR_RootConstrainSelectedInstOperands,
30623 /* 85108 */ // GIR_Coverage, 4245,
30624 /* 85108 */ GIR_EraseRootFromParent_Done,
30625 /* 85109 */ // Label 1665: @85109
30626 /* 85109 */ GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(85202), // Rule ID 4247 //
30627 /* 85114 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30628 /* 85119 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30629 /* 85122 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30630 /* 85125 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
30631 /* 85128 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30632 /* 85131 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30633 /* 85134 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30634 /* 85137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30635 /* 85141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30636 /* 85145 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30637 /* 85149 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30638 /* 85153 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30639 /* 85157 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30640 /* 85161 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30641 /* 85161 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30642 /* 85164 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30643 /* 85168 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30644 /* 85173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs16),
30645 /* 85176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30646 /* 85178 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30647 /* 85180 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30648 /* 85182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30649 /* 85185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30650 /* 85191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30651 /* 85197 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30652 /* 85200 */ GIR_RootConstrainSelectedInstOperands,
30653 /* 85201 */ // GIR_Coverage, 4247,
30654 /* 85201 */ GIR_EraseRootFromParent_Done,
30655 /* 85202 */ // Label 1666: @85202
30656 /* 85202 */ GIM_Try, /*On fail goto*//*Label 1667*/ GIMT_Encode4(85295), // Rule ID 4249 //
30657 /* 85207 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30658 /* 85212 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30659 /* 85215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
30660 /* 85218 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30661 /* 85221 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30662 /* 85224 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30663 /* 85227 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30664 /* 85230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30665 /* 85234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30666 /* 85238 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30667 /* 85242 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30668 /* 85246 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30669 /* 85250 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30670 /* 85254 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3959:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30671 /* 85254 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30672 /* 85257 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30673 /* 85261 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30674 /* 85266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs32),
30675 /* 85269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30676 /* 85271 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30677 /* 85273 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30678 /* 85275 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30679 /* 85278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30680 /* 85284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30681 /* 85290 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30682 /* 85293 */ GIR_RootConstrainSelectedInstOperands,
30683 /* 85294 */ // GIR_Coverage, 4249,
30684 /* 85294 */ GIR_EraseRootFromParent_Done,
30685 /* 85295 */ // Label 1667: @85295
30686 /* 85295 */ GIM_Try, /*On fail goto*//*Label 1668*/ GIMT_Encode4(85388), // Rule ID 4251 //
30687 /* 85300 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30688 /* 85305 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30689 /* 85308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30690 /* 85311 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30691 /* 85314 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30692 /* 85317 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30693 /* 85320 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30694 /* 85323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30695 /* 85327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30696 /* 85331 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30697 /* 85335 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30698 /* 85339 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30699 /* 85343 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30700 /* 85347 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30701 /* 85347 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30702 /* 85350 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30703 /* 85354 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30704 /* 85359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu8),
30705 /* 85362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30706 /* 85364 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30707 /* 85366 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30708 /* 85368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30709 /* 85371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30710 /* 85377 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30711 /* 85383 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30712 /* 85386 */ GIR_RootConstrainSelectedInstOperands,
30713 /* 85387 */ // GIR_Coverage, 4251,
30714 /* 85387 */ GIR_EraseRootFromParent_Done,
30715 /* 85388 */ // Label 1668: @85388
30716 /* 85388 */ GIM_Try, /*On fail goto*//*Label 1669*/ GIMT_Encode4(85481), // Rule ID 4253 //
30717 /* 85393 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30718 /* 85398 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30719 /* 85401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30720 /* 85404 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
30721 /* 85407 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30722 /* 85410 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30723 /* 85413 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30724 /* 85416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30725 /* 85420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30726 /* 85424 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30727 /* 85428 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30728 /* 85432 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30729 /* 85436 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30730 /* 85440 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30731 /* 85440 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30732 /* 85443 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30733 /* 85447 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30734 /* 85452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu16),
30735 /* 85455 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30736 /* 85457 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30737 /* 85459 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30738 /* 85461 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30739 /* 85464 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30740 /* 85470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30741 /* 85476 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30742 /* 85479 */ GIR_RootConstrainSelectedInstOperands,
30743 /* 85480 */ // GIR_Coverage, 4253,
30744 /* 85480 */ GIR_EraseRootFromParent_Done,
30745 /* 85481 */ // Label 1669: @85481
30746 /* 85481 */ GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(85574), // Rule ID 4255 //
30747 /* 85486 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30748 /* 85491 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30749 /* 85494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
30750 /* 85497 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30751 /* 85500 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30752 /* 85503 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30753 /* 85506 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30754 /* 85509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30755 /* 85513 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30756 /* 85517 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30757 /* 85521 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30758 /* 85525 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30759 /* 85529 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30760 /* 85533 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3959:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30761 /* 85533 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30762 /* 85536 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30763 /* 85540 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30764 /* 85545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu32),
30765 /* 85548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30766 /* 85550 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30767 /* 85552 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30768 /* 85554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30769 /* 85557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30770 /* 85563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30771 /* 85569 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30772 /* 85572 */ GIR_RootConstrainSelectedInstOperands,
30773 /* 85573 */ // GIR_Coverage, 4255,
30774 /* 85573 */ GIR_EraseRootFromParent_Done,
30775 /* 85574 */ // Label 1670: @85574
30776 /* 85574 */ GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(85667), // Rule ID 4257 //
30777 /* 85579 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30778 /* 85584 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30779 /* 85587 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30780 /* 85590 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30781 /* 85593 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30782 /* 85596 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30783 /* 85599 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30784 /* 85602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30785 /* 85606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30786 /* 85610 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30787 /* 85614 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30788 /* 85618 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30789 /* 85622 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30790 /* 85626 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30791 /* 85626 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30792 /* 85629 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30793 /* 85633 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30794 /* 85638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs8),
30795 /* 85641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30796 /* 85643 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30797 /* 85645 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30798 /* 85647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30799 /* 85650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30800 /* 85656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30801 /* 85662 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30802 /* 85665 */ GIR_RootConstrainSelectedInstOperands,
30803 /* 85666 */ // GIR_Coverage, 4257,
30804 /* 85666 */ GIR_EraseRootFromParent_Done,
30805 /* 85667 */ // Label 1671: @85667
30806 /* 85667 */ GIM_Try, /*On fail goto*//*Label 1672*/ GIMT_Encode4(85760), // Rule ID 4259 //
30807 /* 85672 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30808 /* 85677 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30809 /* 85680 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30810 /* 85683 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
30811 /* 85686 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30812 /* 85689 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30813 /* 85692 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30814 /* 85695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30815 /* 85699 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30816 /* 85703 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30817 /* 85707 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30818 /* 85711 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30819 /* 85715 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30820 /* 85719 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30821 /* 85719 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30822 /* 85722 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30823 /* 85726 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30824 /* 85731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs16),
30825 /* 85734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30826 /* 85736 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30827 /* 85738 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30828 /* 85740 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30829 /* 85743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30830 /* 85749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30831 /* 85755 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30832 /* 85758 */ GIR_RootConstrainSelectedInstOperands,
30833 /* 85759 */ // GIR_Coverage, 4259,
30834 /* 85759 */ GIR_EraseRootFromParent_Done,
30835 /* 85760 */ // Label 1672: @85760
30836 /* 85760 */ GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(85853), // Rule ID 4261 //
30837 /* 85765 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30838 /* 85770 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30839 /* 85773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
30840 /* 85776 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30841 /* 85779 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30842 /* 85782 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30843 /* 85785 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30844 /* 85788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30845 /* 85792 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30846 /* 85796 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30847 /* 85800 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30848 /* 85804 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30849 /* 85808 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30850 /* 85812 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3959:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30851 /* 85812 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30852 /* 85815 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30853 /* 85819 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30854 /* 85824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs32),
30855 /* 85827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30856 /* 85829 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30857 /* 85831 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30858 /* 85833 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30859 /* 85836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30860 /* 85842 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30861 /* 85848 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30862 /* 85851 */ GIR_RootConstrainSelectedInstOperands,
30863 /* 85852 */ // GIR_Coverage, 4261,
30864 /* 85852 */ GIR_EraseRootFromParent_Done,
30865 /* 85853 */ // Label 1673: @85853
30866 /* 85853 */ GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(85946), // Rule ID 4263 //
30867 /* 85858 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30868 /* 85863 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30869 /* 85866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30870 /* 85869 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30871 /* 85872 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30872 /* 85875 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30873 /* 85878 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30874 /* 85881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30875 /* 85885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30876 /* 85889 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30877 /* 85893 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30878 /* 85897 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30879 /* 85901 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30880 /* 85905 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3959:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30881 /* 85905 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30882 /* 85908 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30883 /* 85912 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30884 /* 85917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu8),
30885 /* 85920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30886 /* 85922 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30887 /* 85924 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30888 /* 85926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30889 /* 85929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30890 /* 85935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30891 /* 85941 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30892 /* 85944 */ GIR_RootConstrainSelectedInstOperands,
30893 /* 85945 */ // GIR_Coverage, 4263,
30894 /* 85945 */ GIR_EraseRootFromParent_Done,
30895 /* 85946 */ // Label 1674: @85946
30896 /* 85946 */ GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(86039), // Rule ID 4265 //
30897 /* 85951 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30898 /* 85956 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30899 /* 85959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30900 /* 85962 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
30901 /* 85965 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30902 /* 85968 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30903 /* 85971 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30904 /* 85974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30905 /* 85978 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30906 /* 85982 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30907 /* 85986 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30908 /* 85990 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30909 /* 85994 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30910 /* 85998 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3959:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30911 /* 85998 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30912 /* 86001 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30913 /* 86005 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30914 /* 86010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu16),
30915 /* 86013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30916 /* 86015 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30917 /* 86017 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30918 /* 86019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30919 /* 86022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30920 /* 86028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30921 /* 86034 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30922 /* 86037 */ GIR_RootConstrainSelectedInstOperands,
30923 /* 86038 */ // GIR_Coverage, 4265,
30924 /* 86038 */ GIR_EraseRootFromParent_Done,
30925 /* 86039 */ // Label 1675: @86039
30926 /* 86039 */ GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(86132), // Rule ID 4267 //
30927 /* 86044 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30928 /* 86049 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30929 /* 86052 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
30930 /* 86055 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30931 /* 86058 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30932 /* 86061 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30933 /* 86064 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30934 /* 86067 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30935 /* 86071 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30936 /* 86075 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30937 /* 86079 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30938 /* 86083 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30939 /* 86087 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30940 /* 86091 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3959:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30941 /* 86091 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30942 /* 86094 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30943 /* 86098 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30944 /* 86103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu32),
30945 /* 86106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30946 /* 86108 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30947 /* 86110 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30948 /* 86112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30949 /* 86115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30950 /* 86121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30951 /* 86127 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30952 /* 86130 */ GIR_RootConstrainSelectedInstOperands,
30953 /* 86131 */ // GIR_Coverage, 4267,
30954 /* 86131 */ GIR_EraseRootFromParent_Done,
30955 /* 86132 */ // Label 1676: @86132
30956 /* 86132 */ GIM_Try, /*On fail goto*//*Label 1677*/ GIMT_Encode4(86210), // Rule ID 4980 //
30957 /* 86137 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
30958 /* 86142 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30959 /* 86145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30960 /* 86148 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30961 /* 86151 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30962 /* 86154 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30963 /* 86157 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30964 /* 86160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30965 /* 86164 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30966 /* 86168 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30967 /* 86172 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30968 /* 86176 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30969 /* 86180 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30970 /* 86184 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3924:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30971 /* 86184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32bh),
30972 /* 86187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30973 /* 86189 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
30974 /* 86191 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
30975 /* 86193 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30976 /* 86196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30977 /* 86202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30978 /* 86208 */ GIR_RootConstrainSelectedInstOperands,
30979 /* 86209 */ // GIR_Coverage, 4980,
30980 /* 86209 */ GIR_EraseRootFromParent_Done,
30981 /* 86210 */ // Label 1677: @86210
30982 /* 86210 */ GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(86288), // Rule ID 4982 //
30983 /* 86215 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
30984 /* 86220 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30985 /* 86223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30986 /* 86226 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30987 /* 86229 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30988 /* 86232 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30989 /* 86235 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30990 /* 86238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30991 /* 86242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30992 /* 86246 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30993 /* 86250 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30994 /* 86254 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30995 /* 86258 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30996 /* 86262 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3924:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30997 /* 86262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32th),
30998 /* 86265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30999 /* 86267 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31000 /* 86269 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31001 /* 86271 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31002 /* 86274 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31003 /* 86280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31004 /* 86286 */ GIR_RootConstrainSelectedInstOperands,
31005 /* 86287 */ // GIR_Coverage, 4982,
31006 /* 86287 */ GIR_EraseRootFromParent_Done,
31007 /* 86288 */ // Label 1678: @86288
31008 /* 86288 */ GIM_Try, /*On fail goto*//*Label 1679*/ GIMT_Encode4(86366), // Rule ID 4984 //
31009 /* 86293 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31010 /* 86298 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31011 /* 86301 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31012 /* 86304 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31013 /* 86307 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31014 /* 86310 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31015 /* 86313 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31016 /* 86316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31017 /* 86320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31018 /* 86324 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31019 /* 86328 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31020 /* 86332 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31021 /* 86336 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31022 /* 86340 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3924:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
31023 /* 86340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16bh),
31024 /* 86343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31025 /* 86345 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31026 /* 86347 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31027 /* 86349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31028 /* 86352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31029 /* 86358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31030 /* 86364 */ GIR_RootConstrainSelectedInstOperands,
31031 /* 86365 */ // GIR_Coverage, 4984,
31032 /* 86365 */ GIR_EraseRootFromParent_Done,
31033 /* 86366 */ // Label 1679: @86366
31034 /* 86366 */ GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(86444), // Rule ID 4986 //
31035 /* 86371 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31036 /* 86376 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31037 /* 86379 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31038 /* 86382 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31039 /* 86385 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31040 /* 86388 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31041 /* 86391 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31042 /* 86394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31043 /* 86398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31044 /* 86402 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31045 /* 86406 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31046 /* 86410 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31047 /* 86414 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31048 /* 86418 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3924:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
31049 /* 86418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16th),
31050 /* 86421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31051 /* 86423 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31052 /* 86425 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31053 /* 86427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31054 /* 86430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31055 /* 86436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31056 /* 86442 */ GIR_RootConstrainSelectedInstOperands,
31057 /* 86443 */ // GIR_Coverage, 4986,
31058 /* 86443 */ GIR_EraseRootFromParent_Done,
31059 /* 86444 */ // Label 1680: @86444
31060 /* 86444 */ GIM_Try, /*On fail goto*//*Label 1681*/ GIMT_Encode4(86522), // Rule ID 4988 //
31061 /* 86449 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31062 /* 86454 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31063 /* 86457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31064 /* 86460 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
31065 /* 86463 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31066 /* 86466 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31067 /* 86469 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31068 /* 86472 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31069 /* 86476 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31070 /* 86480 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31071 /* 86484 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31072 /* 86488 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31073 /* 86492 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31074 /* 86496 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3924:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
31075 /* 86496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32bh),
31076 /* 86499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31077 /* 86501 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31078 /* 86503 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31079 /* 86505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31080 /* 86508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31081 /* 86514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31082 /* 86520 */ GIR_RootConstrainSelectedInstOperands,
31083 /* 86521 */ // GIR_Coverage, 4988,
31084 /* 86521 */ GIR_EraseRootFromParent_Done,
31085 /* 86522 */ // Label 1681: @86522
31086 /* 86522 */ GIM_Try, /*On fail goto*//*Label 1682*/ GIMT_Encode4(86600), // Rule ID 4990 //
31087 /* 86527 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31088 /* 86532 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31089 /* 86535 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31090 /* 86538 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
31091 /* 86541 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31092 /* 86544 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31093 /* 86547 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31094 /* 86550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31095 /* 86554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31096 /* 86558 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31097 /* 86562 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31098 /* 86566 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31099 /* 86570 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31100 /* 86574 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3924:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
31101 /* 86574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32th),
31102 /* 86577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31103 /* 86579 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31104 /* 86581 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31105 /* 86583 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31106 /* 86586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31107 /* 86592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31108 /* 86598 */ GIR_RootConstrainSelectedInstOperands,
31109 /* 86599 */ // GIR_Coverage, 4990,
31110 /* 86599 */ GIR_EraseRootFromParent_Done,
31111 /* 86600 */ // Label 1682: @86600
31112 /* 86600 */ GIM_Try, /*On fail goto*//*Label 1683*/ GIMT_Encode4(86678), // Rule ID 4992 //
31113 /* 86605 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31114 /* 86610 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31115 /* 86613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31116 /* 86616 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31117 /* 86619 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31118 /* 86622 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31119 /* 86625 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31120 /* 86628 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31121 /* 86632 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31122 /* 86636 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31123 /* 86640 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31124 /* 86644 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31125 /* 86648 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31126 /* 86652 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3924:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
31127 /* 86652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16bh),
31128 /* 86655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31129 /* 86657 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31130 /* 86659 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31131 /* 86661 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31132 /* 86664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31133 /* 86670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31134 /* 86676 */ GIR_RootConstrainSelectedInstOperands,
31135 /* 86677 */ // GIR_Coverage, 4992,
31136 /* 86677 */ GIR_EraseRootFromParent_Done,
31137 /* 86678 */ // Label 1683: @86678
31138 /* 86678 */ GIM_Try, /*On fail goto*//*Label 1684*/ GIMT_Encode4(86756), // Rule ID 4994 //
31139 /* 86683 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31140 /* 86688 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31141 /* 86691 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31142 /* 86694 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31143 /* 86697 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31144 /* 86700 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31145 /* 86703 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31146 /* 86706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31147 /* 86710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31148 /* 86714 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31149 /* 86718 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31150 /* 86722 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31151 /* 86726 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31152 /* 86730 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3924:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
31153 /* 86730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16th),
31154 /* 86733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31155 /* 86735 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31156 /* 86737 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31157 /* 86739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31158 /* 86742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31159 /* 86748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31160 /* 86754 */ GIR_RootConstrainSelectedInstOperands,
31161 /* 86755 */ // GIR_Coverage, 4994,
31162 /* 86755 */ GIR_EraseRootFromParent_Done,
31163 /* 86756 */ // Label 1684: @86756
31164 /* 86756 */ GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(86834), // Rule ID 4996 //
31165 /* 86761 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31166 /* 86766 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31167 /* 86769 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31168 /* 86772 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
31169 /* 86775 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31170 /* 86778 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31171 /* 86781 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31172 /* 86784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31173 /* 86788 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31174 /* 86792 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31175 /* 86796 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31176 /* 86800 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31177 /* 86804 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31178 /* 86808 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3924:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
31179 /* 86808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32bh),
31180 /* 86811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31181 /* 86813 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31182 /* 86815 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31183 /* 86817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31184 /* 86820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31185 /* 86826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31186 /* 86832 */ GIR_RootConstrainSelectedInstOperands,
31187 /* 86833 */ // GIR_Coverage, 4996,
31188 /* 86833 */ GIR_EraseRootFromParent_Done,
31189 /* 86834 */ // Label 1685: @86834
31190 /* 86834 */ GIM_Try, /*On fail goto*//*Label 1686*/ GIMT_Encode4(86912), // Rule ID 4998 //
31191 /* 86839 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31192 /* 86844 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31193 /* 86847 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31194 /* 86850 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
31195 /* 86853 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31196 /* 86856 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31197 /* 86859 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31198 /* 86862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31199 /* 86866 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31200 /* 86870 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31201 /* 86874 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31202 /* 86878 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31203 /* 86882 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31204 /* 86886 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3924:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
31205 /* 86886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32th),
31206 /* 86889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31207 /* 86891 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31208 /* 86893 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31209 /* 86895 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31210 /* 86898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31211 /* 86904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31212 /* 86910 */ GIR_RootConstrainSelectedInstOperands,
31213 /* 86911 */ // GIR_Coverage, 4998,
31214 /* 86911 */ GIR_EraseRootFromParent_Done,
31215 /* 86912 */ // Label 1686: @86912
31216 /* 86912 */ GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(86990), // Rule ID 5000 //
31217 /* 86917 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31218 /* 86922 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31219 /* 86925 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31220 /* 86928 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31221 /* 86931 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31222 /* 86934 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31223 /* 86937 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31224 /* 86940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31225 /* 86944 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31226 /* 86948 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31227 /* 86952 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31228 /* 86956 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31229 /* 86960 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31230 /* 86964 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3924:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
31231 /* 86964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16bh),
31232 /* 86967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31233 /* 86969 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31234 /* 86971 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31235 /* 86973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31236 /* 86976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31237 /* 86982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31238 /* 86988 */ GIR_RootConstrainSelectedInstOperands,
31239 /* 86989 */ // GIR_Coverage, 5000,
31240 /* 86989 */ GIR_EraseRootFromParent_Done,
31241 /* 86990 */ // Label 1687: @86990
31242 /* 86990 */ GIM_Try, /*On fail goto*//*Label 1688*/ GIMT_Encode4(87068), // Rule ID 5002 //
31243 /* 86995 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31244 /* 87000 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31245 /* 87003 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31246 /* 87006 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31247 /* 87009 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31248 /* 87012 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31249 /* 87015 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31250 /* 87018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31251 /* 87022 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31252 /* 87026 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31253 /* 87030 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31254 /* 87034 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31255 /* 87038 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31256 /* 87042 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3924:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
31257 /* 87042 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16th),
31258 /* 87045 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31259 /* 87047 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31260 /* 87049 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31261 /* 87051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31262 /* 87054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31263 /* 87060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31264 /* 87066 */ GIR_RootConstrainSelectedInstOperands,
31265 /* 87067 */ // GIR_Coverage, 5002,
31266 /* 87067 */ GIR_EraseRootFromParent_Done,
31267 /* 87068 */ // Label 1688: @87068
31268 /* 87068 */ GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(87146), // Rule ID 5204 //
31269 /* 87073 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31270 /* 87078 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31271 /* 87081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31272 /* 87084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31273 /* 87087 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31274 /* 87090 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31275 /* 87093 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31276 /* 87096 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31277 /* 87100 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31278 /* 87104 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31279 /* 87108 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31280 /* 87112 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31281 /* 87116 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31282 /* 87120 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3957:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31283 /* 87120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs8),
31284 /* 87123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31285 /* 87125 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31286 /* 87127 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31287 /* 87129 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31288 /* 87132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31289 /* 87138 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31290 /* 87144 */ GIR_RootConstrainSelectedInstOperands,
31291 /* 87145 */ // GIR_Coverage, 5204,
31292 /* 87145 */ GIR_EraseRootFromParent_Done,
31293 /* 87146 */ // Label 1689: @87146
31294 /* 87146 */ GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(87224), // Rule ID 5206 //
31295 /* 87151 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31296 /* 87156 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31297 /* 87159 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31298 /* 87162 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31299 /* 87165 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31300 /* 87168 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31301 /* 87171 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31302 /* 87174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31303 /* 87178 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31304 /* 87182 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31305 /* 87186 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31306 /* 87190 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31307 /* 87194 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31308 /* 87198 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3957:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31309 /* 87198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs16),
31310 /* 87201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31311 /* 87203 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31312 /* 87205 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31313 /* 87207 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31314 /* 87210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31315 /* 87216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31316 /* 87222 */ GIR_RootConstrainSelectedInstOperands,
31317 /* 87223 */ // GIR_Coverage, 5206,
31318 /* 87223 */ GIR_EraseRootFromParent_Done,
31319 /* 87224 */ // Label 1690: @87224
31320 /* 87224 */ GIM_Try, /*On fail goto*//*Label 1691*/ GIMT_Encode4(87302), // Rule ID 5208 //
31321 /* 87229 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31322 /* 87234 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31323 /* 87237 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31324 /* 87240 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31325 /* 87243 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31326 /* 87246 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31327 /* 87249 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31328 /* 87252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31329 /* 87256 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31330 /* 87260 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31331 /* 87264 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31332 /* 87268 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31333 /* 87272 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31334 /* 87276 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3957:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31335 /* 87276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs32),
31336 /* 87279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31337 /* 87281 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31338 /* 87283 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31339 /* 87285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31340 /* 87288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31341 /* 87294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31342 /* 87300 */ GIR_RootConstrainSelectedInstOperands,
31343 /* 87301 */ // GIR_Coverage, 5208,
31344 /* 87301 */ GIR_EraseRootFromParent_Done,
31345 /* 87302 */ // Label 1691: @87302
31346 /* 87302 */ GIM_Try, /*On fail goto*//*Label 1692*/ GIMT_Encode4(87380), // Rule ID 5210 //
31347 /* 87307 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31348 /* 87312 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31349 /* 87315 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31350 /* 87318 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31351 /* 87321 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31352 /* 87324 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31353 /* 87327 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31354 /* 87330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31355 /* 87334 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31356 /* 87338 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31357 /* 87342 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31358 /* 87346 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31359 /* 87350 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31360 /* 87354 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3957:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31361 /* 87354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru8),
31362 /* 87357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31363 /* 87359 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31364 /* 87361 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31365 /* 87363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31366 /* 87366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31367 /* 87372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31368 /* 87378 */ GIR_RootConstrainSelectedInstOperands,
31369 /* 87379 */ // GIR_Coverage, 5210,
31370 /* 87379 */ GIR_EraseRootFromParent_Done,
31371 /* 87380 */ // Label 1692: @87380
31372 /* 87380 */ GIM_Try, /*On fail goto*//*Label 1693*/ GIMT_Encode4(87458), // Rule ID 5212 //
31373 /* 87385 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31374 /* 87390 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31375 /* 87393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31376 /* 87396 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31377 /* 87399 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31378 /* 87402 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31379 /* 87405 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31380 /* 87408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31381 /* 87412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31382 /* 87416 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31383 /* 87420 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31384 /* 87424 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31385 /* 87428 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31386 /* 87432 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3957:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31387 /* 87432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru16),
31388 /* 87435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31389 /* 87437 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31390 /* 87439 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31391 /* 87441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31392 /* 87444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31393 /* 87450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31394 /* 87456 */ GIR_RootConstrainSelectedInstOperands,
31395 /* 87457 */ // GIR_Coverage, 5212,
31396 /* 87457 */ GIR_EraseRootFromParent_Done,
31397 /* 87458 */ // Label 1693: @87458
31398 /* 87458 */ GIM_Try, /*On fail goto*//*Label 1694*/ GIMT_Encode4(87536), // Rule ID 5214 //
31399 /* 87463 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31400 /* 87468 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31401 /* 87471 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31402 /* 87474 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31403 /* 87477 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31404 /* 87480 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31405 /* 87483 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31406 /* 87486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31407 /* 87490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31408 /* 87494 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31409 /* 87498 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31410 /* 87502 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31411 /* 87506 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31412 /* 87510 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3957:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31413 /* 87510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru32),
31414 /* 87513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31415 /* 87515 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31416 /* 87517 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31417 /* 87519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31418 /* 87522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31419 /* 87528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31420 /* 87534 */ GIR_RootConstrainSelectedInstOperands,
31421 /* 87535 */ // GIR_Coverage, 5214,
31422 /* 87535 */ GIR_EraseRootFromParent_Done,
31423 /* 87536 */ // Label 1694: @87536
31424 /* 87536 */ GIM_Try, /*On fail goto*//*Label 1695*/ GIMT_Encode4(87614), // Rule ID 5216 //
31425 /* 87541 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31426 /* 87546 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31427 /* 87549 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31428 /* 87552 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31429 /* 87555 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31430 /* 87558 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31431 /* 87561 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31432 /* 87564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31433 /* 87568 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31434 /* 87572 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31435 /* 87576 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31436 /* 87580 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31437 /* 87584 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31438 /* 87588 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3957:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31439 /* 87588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs8),
31440 /* 87591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31441 /* 87593 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31442 /* 87595 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31443 /* 87597 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31444 /* 87600 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31445 /* 87606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31446 /* 87612 */ GIR_RootConstrainSelectedInstOperands,
31447 /* 87613 */ // GIR_Coverage, 5216,
31448 /* 87613 */ GIR_EraseRootFromParent_Done,
31449 /* 87614 */ // Label 1695: @87614
31450 /* 87614 */ GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(87692), // Rule ID 5218 //
31451 /* 87619 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31452 /* 87624 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31453 /* 87627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31454 /* 87630 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31455 /* 87633 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31456 /* 87636 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31457 /* 87639 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31458 /* 87642 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31459 /* 87646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31460 /* 87650 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31461 /* 87654 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31462 /* 87658 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31463 /* 87662 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31464 /* 87666 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3957:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31465 /* 87666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs16),
31466 /* 87669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31467 /* 87671 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31468 /* 87673 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31469 /* 87675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31470 /* 87678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31471 /* 87684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31472 /* 87690 */ GIR_RootConstrainSelectedInstOperands,
31473 /* 87691 */ // GIR_Coverage, 5218,
31474 /* 87691 */ GIR_EraseRootFromParent_Done,
31475 /* 87692 */ // Label 1696: @87692
31476 /* 87692 */ GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(87770), // Rule ID 5220 //
31477 /* 87697 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31478 /* 87702 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31479 /* 87705 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31480 /* 87708 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31481 /* 87711 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31482 /* 87714 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31483 /* 87717 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31484 /* 87720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31485 /* 87724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31486 /* 87728 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31487 /* 87732 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31488 /* 87736 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31489 /* 87740 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31490 /* 87744 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3957:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31491 /* 87744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs32),
31492 /* 87747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31493 /* 87749 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31494 /* 87751 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31495 /* 87753 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31496 /* 87756 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31497 /* 87762 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31498 /* 87768 */ GIR_RootConstrainSelectedInstOperands,
31499 /* 87769 */ // GIR_Coverage, 5220,
31500 /* 87769 */ GIR_EraseRootFromParent_Done,
31501 /* 87770 */ // Label 1697: @87770
31502 /* 87770 */ GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(87848), // Rule ID 5222 //
31503 /* 87775 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31504 /* 87780 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31505 /* 87783 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31506 /* 87786 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31507 /* 87789 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31508 /* 87792 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31509 /* 87795 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31510 /* 87798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31511 /* 87802 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31512 /* 87806 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31513 /* 87810 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31514 /* 87814 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31515 /* 87818 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31516 /* 87822 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3957:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31517 /* 87822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru8),
31518 /* 87825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31519 /* 87827 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31520 /* 87829 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31521 /* 87831 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31522 /* 87834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31523 /* 87840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31524 /* 87846 */ GIR_RootConstrainSelectedInstOperands,
31525 /* 87847 */ // GIR_Coverage, 5222,
31526 /* 87847 */ GIR_EraseRootFromParent_Done,
31527 /* 87848 */ // Label 1698: @87848
31528 /* 87848 */ GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(87926), // Rule ID 5224 //
31529 /* 87853 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31530 /* 87858 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31531 /* 87861 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31532 /* 87864 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31533 /* 87867 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31534 /* 87870 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31535 /* 87873 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31536 /* 87876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31537 /* 87880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31538 /* 87884 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31539 /* 87888 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31540 /* 87892 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31541 /* 87896 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31542 /* 87900 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3957:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31543 /* 87900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru16),
31544 /* 87903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31545 /* 87905 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31546 /* 87907 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31547 /* 87909 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31548 /* 87912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31549 /* 87918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31550 /* 87924 */ GIR_RootConstrainSelectedInstOperands,
31551 /* 87925 */ // GIR_Coverage, 5224,
31552 /* 87925 */ GIR_EraseRootFromParent_Done,
31553 /* 87926 */ // Label 1699: @87926
31554 /* 87926 */ GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(88004), // Rule ID 5226 //
31555 /* 87931 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31556 /* 87936 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31557 /* 87939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31558 /* 87942 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31559 /* 87945 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31560 /* 87948 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31561 /* 87951 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31562 /* 87954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31563 /* 87958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31564 /* 87962 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31565 /* 87966 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31566 /* 87970 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31567 /* 87974 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31568 /* 87978 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3957:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31569 /* 87978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru32),
31570 /* 87981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31571 /* 87983 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31572 /* 87985 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31573 /* 87987 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31574 /* 87990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31575 /* 87996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31576 /* 88002 */ GIR_RootConstrainSelectedInstOperands,
31577 /* 88003 */ // GIR_Coverage, 5226,
31578 /* 88003 */ GIR_EraseRootFromParent_Done,
31579 /* 88004 */ // Label 1700: @88004
31580 /* 88004 */ GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(88082), // Rule ID 5228 //
31581 /* 88009 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31582 /* 88014 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31583 /* 88017 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31584 /* 88020 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31585 /* 88023 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31586 /* 88026 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31587 /* 88029 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31588 /* 88032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31589 /* 88036 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31590 /* 88040 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31591 /* 88044 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31592 /* 88048 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31593 /* 88052 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31594 /* 88056 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3957:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31595 /* 88056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs8),
31596 /* 88059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31597 /* 88061 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31598 /* 88063 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31599 /* 88065 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31600 /* 88068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31601 /* 88074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31602 /* 88080 */ GIR_RootConstrainSelectedInstOperands,
31603 /* 88081 */ // GIR_Coverage, 5228,
31604 /* 88081 */ GIR_EraseRootFromParent_Done,
31605 /* 88082 */ // Label 1701: @88082
31606 /* 88082 */ GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(88160), // Rule ID 5230 //
31607 /* 88087 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31608 /* 88092 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31609 /* 88095 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31610 /* 88098 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31611 /* 88101 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31612 /* 88104 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31613 /* 88107 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31614 /* 88110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31615 /* 88114 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31616 /* 88118 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31617 /* 88122 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31618 /* 88126 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31619 /* 88130 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31620 /* 88134 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3957:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31621 /* 88134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs16),
31622 /* 88137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31623 /* 88139 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31624 /* 88141 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31625 /* 88143 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31626 /* 88146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31627 /* 88152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31628 /* 88158 */ GIR_RootConstrainSelectedInstOperands,
31629 /* 88159 */ // GIR_Coverage, 5230,
31630 /* 88159 */ GIR_EraseRootFromParent_Done,
31631 /* 88160 */ // Label 1702: @88160
31632 /* 88160 */ GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(88238), // Rule ID 5232 //
31633 /* 88165 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31634 /* 88170 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31635 /* 88173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31636 /* 88176 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31637 /* 88179 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31638 /* 88182 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31639 /* 88185 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31640 /* 88188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31641 /* 88192 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31642 /* 88196 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31643 /* 88200 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31644 /* 88204 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31645 /* 88208 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31646 /* 88212 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3957:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31647 /* 88212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs32),
31648 /* 88215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31649 /* 88217 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31650 /* 88219 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31651 /* 88221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31652 /* 88224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31653 /* 88230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31654 /* 88236 */ GIR_RootConstrainSelectedInstOperands,
31655 /* 88237 */ // GIR_Coverage, 5232,
31656 /* 88237 */ GIR_EraseRootFromParent_Done,
31657 /* 88238 */ // Label 1703: @88238
31658 /* 88238 */ GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(88316), // Rule ID 5234 //
31659 /* 88243 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31660 /* 88248 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31661 /* 88251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31662 /* 88254 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31663 /* 88257 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31664 /* 88260 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31665 /* 88263 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31666 /* 88266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31667 /* 88270 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31668 /* 88274 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31669 /* 88278 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31670 /* 88282 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31671 /* 88286 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31672 /* 88290 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3957:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31673 /* 88290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru8),
31674 /* 88293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31675 /* 88295 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31676 /* 88297 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31677 /* 88299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31678 /* 88302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31679 /* 88308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31680 /* 88314 */ GIR_RootConstrainSelectedInstOperands,
31681 /* 88315 */ // GIR_Coverage, 5234,
31682 /* 88315 */ GIR_EraseRootFromParent_Done,
31683 /* 88316 */ // Label 1704: @88316
31684 /* 88316 */ GIM_Try, /*On fail goto*//*Label 1705*/ GIMT_Encode4(88394), // Rule ID 5236 //
31685 /* 88321 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31686 /* 88326 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31687 /* 88329 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31688 /* 88332 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31689 /* 88335 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31690 /* 88338 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31691 /* 88341 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31692 /* 88344 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31693 /* 88348 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31694 /* 88352 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31695 /* 88356 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31696 /* 88360 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31697 /* 88364 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31698 /* 88368 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3957:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31699 /* 88368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru16),
31700 /* 88371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31701 /* 88373 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31702 /* 88375 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31703 /* 88377 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31704 /* 88380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31705 /* 88386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31706 /* 88392 */ GIR_RootConstrainSelectedInstOperands,
31707 /* 88393 */ // GIR_Coverage, 5236,
31708 /* 88393 */ GIR_EraseRootFromParent_Done,
31709 /* 88394 */ // Label 1705: @88394
31710 /* 88394 */ GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(88472), // Rule ID 5238 //
31711 /* 88399 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31712 /* 88404 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31713 /* 88407 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31714 /* 88410 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31715 /* 88413 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31716 /* 88416 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31717 /* 88419 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31718 /* 88422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31719 /* 88426 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31720 /* 88430 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31721 /* 88434 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31722 /* 88438 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31723 /* 88442 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31724 /* 88446 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3957:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31725 /* 88446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru32),
31726 /* 88449 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31727 /* 88451 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31728 /* 88453 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31729 /* 88455 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31730 /* 88458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31731 /* 88464 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31732 /* 88470 */ GIR_RootConstrainSelectedInstOperands,
31733 /* 88471 */ // GIR_Coverage, 5238,
31734 /* 88471 */ GIR_EraseRootFromParent_Done,
31735 /* 88472 */ // Label 1706: @88472
31736 /* 88472 */ GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(88550), // Rule ID 5240 //
31737 /* 88477 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31738 /* 88482 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31739 /* 88485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31740 /* 88488 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31741 /* 88491 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31742 /* 88494 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31743 /* 88497 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31744 /* 88500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31745 /* 88504 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31746 /* 88508 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31747 /* 88512 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31748 /* 88516 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31749 /* 88520 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31750 /* 88524 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3957:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31751 /* 88524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs8),
31752 /* 88527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31753 /* 88529 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31754 /* 88531 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31755 /* 88533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31756 /* 88536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31757 /* 88542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31758 /* 88548 */ GIR_RootConstrainSelectedInstOperands,
31759 /* 88549 */ // GIR_Coverage, 5240,
31760 /* 88549 */ GIR_EraseRootFromParent_Done,
31761 /* 88550 */ // Label 1707: @88550
31762 /* 88550 */ GIM_Try, /*On fail goto*//*Label 1708*/ GIMT_Encode4(88628), // Rule ID 5242 //
31763 /* 88555 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31764 /* 88560 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31765 /* 88563 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31766 /* 88566 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31767 /* 88569 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31768 /* 88572 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31769 /* 88575 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31770 /* 88578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31771 /* 88582 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31772 /* 88586 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31773 /* 88590 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31774 /* 88594 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31775 /* 88598 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31776 /* 88602 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3957:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31777 /* 88602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs16),
31778 /* 88605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31779 /* 88607 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31780 /* 88609 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31781 /* 88611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31782 /* 88614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31783 /* 88620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31784 /* 88626 */ GIR_RootConstrainSelectedInstOperands,
31785 /* 88627 */ // GIR_Coverage, 5242,
31786 /* 88627 */ GIR_EraseRootFromParent_Done,
31787 /* 88628 */ // Label 1708: @88628
31788 /* 88628 */ GIM_Try, /*On fail goto*//*Label 1709*/ GIMT_Encode4(88706), // Rule ID 5244 //
31789 /* 88633 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31790 /* 88638 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31791 /* 88641 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31792 /* 88644 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31793 /* 88647 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31794 /* 88650 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31795 /* 88653 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31796 /* 88656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31797 /* 88660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31798 /* 88664 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31799 /* 88668 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31800 /* 88672 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31801 /* 88676 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31802 /* 88680 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3957:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31803 /* 88680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs32),
31804 /* 88683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31805 /* 88685 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31806 /* 88687 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31807 /* 88689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31808 /* 88692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31809 /* 88698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31810 /* 88704 */ GIR_RootConstrainSelectedInstOperands,
31811 /* 88705 */ // GIR_Coverage, 5244,
31812 /* 88705 */ GIR_EraseRootFromParent_Done,
31813 /* 88706 */ // Label 1709: @88706
31814 /* 88706 */ GIM_Try, /*On fail goto*//*Label 1710*/ GIMT_Encode4(88784), // Rule ID 5246 //
31815 /* 88711 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31816 /* 88716 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31817 /* 88719 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31818 /* 88722 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31819 /* 88725 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31820 /* 88728 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31821 /* 88731 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31822 /* 88734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31823 /* 88738 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31824 /* 88742 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31825 /* 88746 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31826 /* 88750 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31827 /* 88754 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31828 /* 88758 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3957:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31829 /* 88758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru8),
31830 /* 88761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31831 /* 88763 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31832 /* 88765 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31833 /* 88767 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31834 /* 88770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31835 /* 88776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31836 /* 88782 */ GIR_RootConstrainSelectedInstOperands,
31837 /* 88783 */ // GIR_Coverage, 5246,
31838 /* 88783 */ GIR_EraseRootFromParent_Done,
31839 /* 88784 */ // Label 1710: @88784
31840 /* 88784 */ GIM_Try, /*On fail goto*//*Label 1711*/ GIMT_Encode4(88862), // Rule ID 5248 //
31841 /* 88789 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31842 /* 88794 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31843 /* 88797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31844 /* 88800 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31845 /* 88803 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31846 /* 88806 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31847 /* 88809 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31848 /* 88812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31849 /* 88816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31850 /* 88820 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31851 /* 88824 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31852 /* 88828 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31853 /* 88832 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31854 /* 88836 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3957:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31855 /* 88836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru16),
31856 /* 88839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31857 /* 88841 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31858 /* 88843 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31859 /* 88845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31860 /* 88848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31861 /* 88854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31862 /* 88860 */ GIR_RootConstrainSelectedInstOperands,
31863 /* 88861 */ // GIR_Coverage, 5248,
31864 /* 88861 */ GIR_EraseRootFromParent_Done,
31865 /* 88862 */ // Label 1711: @88862
31866 /* 88862 */ GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(88940), // Rule ID 5250 //
31867 /* 88867 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31868 /* 88872 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31869 /* 88875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31870 /* 88878 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31871 /* 88881 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31872 /* 88884 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31873 /* 88887 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31874 /* 88890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31875 /* 88894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31876 /* 88898 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31877 /* 88902 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31878 /* 88906 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31879 /* 88910 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31880 /* 88914 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3957:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31881 /* 88914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru32),
31882 /* 88917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31883 /* 88919 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31884 /* 88921 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31885 /* 88923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31886 /* 88926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31887 /* 88932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31888 /* 88938 */ GIR_RootConstrainSelectedInstOperands,
31889 /* 88939 */ // GIR_Coverage, 5250,
31890 /* 88939 */ GIR_EraseRootFromParent_Done,
31891 /* 88940 */ // Label 1712: @88940
31892 /* 88940 */ GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(89076), // Rule ID 3065 //
31893 /* 88945 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
31894 /* 88948 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx3),
31895 /* 88953 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
31896 /* 88956 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
31897 /* 88959 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
31898 /* 88962 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
31899 /* 88965 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
31900 /* 88968 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8,
31901 /* 88971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
31902 /* 88975 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4116:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBX3Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
31903 /* 88975 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
31904 /* 88978 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
31905 /* 88982 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
31906 /* 88987 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
31907 /* 88989 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
31908 /* 88992 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
31909 /* 88996 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
31910 /* 89001 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
31911 /* 89005 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
31912 /* 89008 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
31913 /* 89012 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
31914 /* 89015 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
31915 /* 89019 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
31916 /* 89022 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
31917 /* 89025 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
31918 /* 89028 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
31919 /* 89033 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
31920 /* 89038 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
31921 /* 89043 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
31922 /* 89048 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
31923 /* 89053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX3Pseudo),
31924 /* 89056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31925 /* 89058 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
31926 /* 89060 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31927 /* 89063 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm
31928 /* 89065 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
31929 /* 89068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31930 /* 89074 */ GIR_RootConstrainSelectedInstOperands,
31931 /* 89075 */ // GIR_Coverage, 3065,
31932 /* 89075 */ GIR_EraseRootFromParent_Done,
31933 /* 89076 */ // Label 1713: @89076
31934 /* 89076 */ GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(89197), // Rule ID 3066 //
31935 /* 89081 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
31936 /* 89084 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl4),
31937 /* 89089 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
31938 /* 89092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
31939 /* 89095 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
31940 /* 89098 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
31941 /* 89101 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
31942 /* 89104 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8,
31943 /* 89107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
31944 /* 89111 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4113:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBL4Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
31945 /* 89111 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
31946 /* 89114 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
31947 /* 89118 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
31948 /* 89123 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
31949 /* 89127 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
31950 /* 89130 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
31951 /* 89134 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
31952 /* 89137 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
31953 /* 89141 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
31954 /* 89144 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn3
31955 /* 89148 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
31956 /* 89151 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
31957 /* 89156 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
31958 /* 89161 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
31959 /* 89166 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
31960 /* 89171 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
31961 /* 89176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL4Pseudo),
31962 /* 89179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31963 /* 89181 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31964 /* 89184 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm
31965 /* 89186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
31966 /* 89189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31967 /* 89195 */ GIR_RootConstrainSelectedInstOperands,
31968 /* 89196 */ // GIR_Coverage, 3066,
31969 /* 89196 */ GIR_EraseRootFromParent_Done,
31970 /* 89197 */ // Label 1714: @89197
31971 /* 89197 */ GIM_Reject,
31972 /* 89198 */ // Label 1652: @89198
31973 /* 89198 */ GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(94091),
31974 /* 89203 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/8,
31975 /* 89206 */ GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(89294), // Rule ID 3558 //
31976 /* 89211 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
31977 /* 89214 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
31978 /* 89219 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
31979 /* 89222 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
31980 /* 89225 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31981 /* 89228 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31982 /* 89231 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31983 /* 89234 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
31984 /* 89237 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
31985 /* 89240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31986 /* 89244 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31987 /* 89248 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31988 /* 89252 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31989 /* 89256 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31990 /* 89260 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31991 /* 89264 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31992 /* 89268 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
31993 /* 89268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs8),
31994 /* 89271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31995 /* 89273 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31996 /* 89275 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31997 /* 89277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31998 /* 89280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31999 /* 89286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32000 /* 89292 */ GIR_RootConstrainSelectedInstOperands,
32001 /* 89293 */ // GIR_Coverage, 3558,
32002 /* 89293 */ GIR_EraseRootFromParent_Done,
32003 /* 89294 */ // Label 1716: @89294
32004 /* 89294 */ GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(89382), // Rule ID 3562 //
32005 /* 89299 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32006 /* 89302 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32007 /* 89307 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32008 /* 89310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32009 /* 89313 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32010 /* 89316 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32011 /* 89319 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32012 /* 89322 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32013 /* 89325 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32014 /* 89328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32015 /* 89332 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32016 /* 89336 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32017 /* 89340 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32018 /* 89344 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32019 /* 89348 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32020 /* 89352 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32021 /* 89356 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32022 /* 89356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs8),
32023 /* 89359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32024 /* 89361 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32025 /* 89363 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32026 /* 89365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32027 /* 89368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32028 /* 89374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32029 /* 89380 */ GIR_RootConstrainSelectedInstOperands,
32030 /* 89381 */ // GIR_Coverage, 3562,
32031 /* 89381 */ GIR_EraseRootFromParent_Done,
32032 /* 89382 */ // Label 1717: @89382
32033 /* 89382 */ GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(89470), // Rule ID 3566 //
32034 /* 89387 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32035 /* 89390 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32036 /* 89395 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32037 /* 89398 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32038 /* 89401 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32039 /* 89404 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32040 /* 89407 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32041 /* 89410 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32042 /* 89413 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32043 /* 89416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32044 /* 89420 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
32045 /* 89424 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32046 /* 89428 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32047 /* 89432 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32048 /* 89436 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32049 /* 89440 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32050 /* 89444 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVu8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32051 /* 89444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8),
32052 /* 89447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32053 /* 89449 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32054 /* 89451 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32055 /* 89453 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32056 /* 89456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32057 /* 89462 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32058 /* 89468 */ GIR_RootConstrainSelectedInstOperands,
32059 /* 89469 */ // GIR_Coverage, 3566,
32060 /* 89469 */ GIR_EraseRootFromParent_Done,
32061 /* 89470 */ // Label 1718: @89470
32062 /* 89470 */ GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(89558), // Rule ID 3570 //
32063 /* 89475 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32064 /* 89478 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32065 /* 89483 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32066 /* 89486 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32067 /* 89489 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32068 /* 89492 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32069 /* 89495 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32070 /* 89498 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32071 /* 89501 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32072 /* 89504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32073 /* 89508 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32074 /* 89512 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32075 /* 89516 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32076 /* 89520 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32077 /* 89524 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32078 /* 89528 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32079 /* 89532 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32080 /* 89532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs16),
32081 /* 89535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32082 /* 89537 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32083 /* 89539 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32084 /* 89541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32085 /* 89544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32086 /* 89550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32087 /* 89556 */ GIR_RootConstrainSelectedInstOperands,
32088 /* 89557 */ // GIR_Coverage, 3570,
32089 /* 89557 */ GIR_EraseRootFromParent_Done,
32090 /* 89558 */ // Label 1719: @89558
32091 /* 89558 */ GIM_Try, /*On fail goto*//*Label 1720*/ GIMT_Encode4(89646), // Rule ID 3574 //
32092 /* 89563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32093 /* 89566 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32094 /* 89571 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32095 /* 89574 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32096 /* 89577 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32097 /* 89580 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32098 /* 89583 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32099 /* 89586 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32100 /* 89589 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32101 /* 89592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32102 /* 89596 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32103 /* 89600 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32104 /* 89604 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32105 /* 89608 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32106 /* 89612 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32107 /* 89616 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32108 /* 89620 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32109 /* 89620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs16),
32110 /* 89623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32111 /* 89625 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32112 /* 89627 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32113 /* 89629 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32114 /* 89632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32115 /* 89638 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32116 /* 89644 */ GIR_RootConstrainSelectedInstOperands,
32117 /* 89645 */ // GIR_Coverage, 3574,
32118 /* 89645 */ GIR_EraseRootFromParent_Done,
32119 /* 89646 */ // Label 1720: @89646
32120 /* 89646 */ GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(89734), // Rule ID 3578 //
32121 /* 89651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32122 /* 89654 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32123 /* 89659 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32124 /* 89662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32125 /* 89665 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32126 /* 89668 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32127 /* 89671 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32128 /* 89674 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32129 /* 89677 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32130 /* 89680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32131 /* 89684 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
32132 /* 89688 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32133 /* 89692 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32134 /* 89696 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32135 /* 89700 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32136 /* 89704 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32137 /* 89708 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVu16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32138 /* 89708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16),
32139 /* 89711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32140 /* 89713 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32141 /* 89715 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32142 /* 89717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32143 /* 89720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32144 /* 89726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32145 /* 89732 */ GIR_RootConstrainSelectedInstOperands,
32146 /* 89733 */ // GIR_Coverage, 3578,
32147 /* 89733 */ GIR_EraseRootFromParent_Done,
32148 /* 89734 */ // Label 1721: @89734
32149 /* 89734 */ GIM_Try, /*On fail goto*//*Label 1722*/ GIMT_Encode4(89822), // Rule ID 3582 //
32150 /* 89739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32151 /* 89742 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32152 /* 89747 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32153 /* 89750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32154 /* 89753 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32155 /* 89756 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32156 /* 89759 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32157 /* 89762 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32158 /* 89765 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32159 /* 89768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32160 /* 89772 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32161 /* 89776 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32162 /* 89780 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32163 /* 89784 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32164 /* 89788 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32165 /* 89792 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32166 /* 89796 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32167 /* 89796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs32),
32168 /* 89799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32169 /* 89801 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32170 /* 89803 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32171 /* 89805 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32172 /* 89808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32173 /* 89814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32174 /* 89820 */ GIR_RootConstrainSelectedInstOperands,
32175 /* 89821 */ // GIR_Coverage, 3582,
32176 /* 89821 */ GIR_EraseRootFromParent_Done,
32177 /* 89822 */ // Label 1722: @89822
32178 /* 89822 */ GIM_Try, /*On fail goto*//*Label 1723*/ GIMT_Encode4(89910), // Rule ID 3586 //
32179 /* 89827 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32180 /* 89830 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32181 /* 89835 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32182 /* 89838 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32183 /* 89841 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32184 /* 89844 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32185 /* 89847 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32186 /* 89850 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32187 /* 89853 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32188 /* 89856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32189 /* 89860 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32190 /* 89864 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32191 /* 89868 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32192 /* 89872 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32193 /* 89876 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32194 /* 89880 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32195 /* 89884 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32196 /* 89884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs32),
32197 /* 89887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32198 /* 89889 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32199 /* 89891 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32200 /* 89893 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32201 /* 89896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32202 /* 89902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32203 /* 89908 */ GIR_RootConstrainSelectedInstOperands,
32204 /* 89909 */ // GIR_Coverage, 3586,
32205 /* 89909 */ GIR_EraseRootFromParent_Done,
32206 /* 89910 */ // Label 1723: @89910
32207 /* 89910 */ GIM_Try, /*On fail goto*//*Label 1724*/ GIMT_Encode4(89998), // Rule ID 3590 //
32208 /* 89915 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32209 /* 89918 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32210 /* 89923 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32211 /* 89926 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32212 /* 89929 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32213 /* 89932 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32214 /* 89935 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32215 /* 89938 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32216 /* 89941 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32217 /* 89944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32218 /* 89948 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
32219 /* 89952 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32220 /* 89956 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32221 /* 89960 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32222 /* 89964 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32223 /* 89968 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32224 /* 89972 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVu32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32225 /* 89972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32),
32226 /* 89975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32227 /* 89977 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32228 /* 89979 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32229 /* 89981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32230 /* 89984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32231 /* 89990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32232 /* 89996 */ GIR_RootConstrainSelectedInstOperands,
32233 /* 89997 */ // GIR_Coverage, 3590,
32234 /* 89997 */ GIR_EraseRootFromParent_Done,
32235 /* 89998 */ // Label 1724: @89998
32236 /* 89998 */ GIM_Try, /*On fail goto*//*Label 1725*/ GIMT_Encode4(90086), // Rule ID 3594 //
32237 /* 90003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32238 /* 90006 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32239 /* 90011 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32240 /* 90014 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32241 /* 90017 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32242 /* 90020 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32243 /* 90023 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32244 /* 90026 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32245 /* 90029 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32246 /* 90032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32247 /* 90036 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32248 /* 90040 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32249 /* 90044 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32250 /* 90048 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32251 /* 90052 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32252 /* 90056 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32253 /* 90060 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32254 /* 90060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs8),
32255 /* 90063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32256 /* 90065 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32257 /* 90067 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32258 /* 90069 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32259 /* 90072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32260 /* 90078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32261 /* 90084 */ GIR_RootConstrainSelectedInstOperands,
32262 /* 90085 */ // GIR_Coverage, 3594,
32263 /* 90085 */ GIR_EraseRootFromParent_Done,
32264 /* 90086 */ // Label 1725: @90086
32265 /* 90086 */ GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(90174), // Rule ID 3598 //
32266 /* 90091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32267 /* 90094 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32268 /* 90099 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32269 /* 90102 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32270 /* 90105 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32271 /* 90108 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32272 /* 90111 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32273 /* 90114 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32274 /* 90117 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32275 /* 90120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32276 /* 90124 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32277 /* 90128 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32278 /* 90132 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32279 /* 90136 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32280 /* 90140 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32281 /* 90144 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32282 /* 90148 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32283 /* 90148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs8),
32284 /* 90151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32285 /* 90153 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32286 /* 90155 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32287 /* 90157 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32288 /* 90160 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32289 /* 90166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32290 /* 90172 */ GIR_RootConstrainSelectedInstOperands,
32291 /* 90173 */ // GIR_Coverage, 3598,
32292 /* 90173 */ GIR_EraseRootFromParent_Done,
32293 /* 90174 */ // Label 1726: @90174
32294 /* 90174 */ GIM_Try, /*On fail goto*//*Label 1727*/ GIMT_Encode4(90262), // Rule ID 3602 //
32295 /* 90179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32296 /* 90182 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32297 /* 90187 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32298 /* 90190 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32299 /* 90193 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32300 /* 90196 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32301 /* 90199 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32302 /* 90202 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32303 /* 90205 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32304 /* 90208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32305 /* 90212 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32306 /* 90216 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32307 /* 90220 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32308 /* 90224 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32309 /* 90228 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32310 /* 90232 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32311 /* 90236 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32312 /* 90236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs16),
32313 /* 90239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32314 /* 90241 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32315 /* 90243 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32316 /* 90245 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32317 /* 90248 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32318 /* 90254 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32319 /* 90260 */ GIR_RootConstrainSelectedInstOperands,
32320 /* 90261 */ // GIR_Coverage, 3602,
32321 /* 90261 */ GIR_EraseRootFromParent_Done,
32322 /* 90262 */ // Label 1727: @90262
32323 /* 90262 */ GIM_Try, /*On fail goto*//*Label 1728*/ GIMT_Encode4(90350), // Rule ID 3606 //
32324 /* 90267 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32325 /* 90270 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32326 /* 90275 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32327 /* 90278 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32328 /* 90281 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32329 /* 90284 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32330 /* 90287 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32331 /* 90290 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32332 /* 90293 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32333 /* 90296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32334 /* 90300 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32335 /* 90304 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32336 /* 90308 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32337 /* 90312 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32338 /* 90316 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32339 /* 90320 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32340 /* 90324 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32341 /* 90324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs16),
32342 /* 90327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32343 /* 90329 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32344 /* 90331 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32345 /* 90333 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32346 /* 90336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32347 /* 90342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32348 /* 90348 */ GIR_RootConstrainSelectedInstOperands,
32349 /* 90349 */ // GIR_Coverage, 3606,
32350 /* 90349 */ GIR_EraseRootFromParent_Done,
32351 /* 90350 */ // Label 1728: @90350
32352 /* 90350 */ GIM_Try, /*On fail goto*//*Label 1729*/ GIMT_Encode4(90438), // Rule ID 3610 //
32353 /* 90355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32354 /* 90358 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32355 /* 90363 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32356 /* 90366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32357 /* 90369 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32358 /* 90372 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32359 /* 90375 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32360 /* 90378 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32361 /* 90381 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32362 /* 90384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32363 /* 90388 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32364 /* 90392 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32365 /* 90396 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32366 /* 90400 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32367 /* 90404 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32368 /* 90408 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32369 /* 90412 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32370 /* 90412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs32),
32371 /* 90415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32372 /* 90417 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32373 /* 90419 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32374 /* 90421 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32375 /* 90424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32376 /* 90430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32377 /* 90436 */ GIR_RootConstrainSelectedInstOperands,
32378 /* 90437 */ // GIR_Coverage, 3610,
32379 /* 90437 */ GIR_EraseRootFromParent_Done,
32380 /* 90438 */ // Label 1729: @90438
32381 /* 90438 */ GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(90526), // Rule ID 3614 //
32382 /* 90443 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32383 /* 90446 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32384 /* 90451 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32385 /* 90454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32386 /* 90457 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32387 /* 90460 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32388 /* 90463 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32389 /* 90466 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32390 /* 90469 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32391 /* 90472 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32392 /* 90476 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32393 /* 90480 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32394 /* 90484 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32395 /* 90488 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32396 /* 90492 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32397 /* 90496 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32398 /* 90500 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32399 /* 90500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs32),
32400 /* 90503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32401 /* 90505 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32402 /* 90507 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32403 /* 90509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32404 /* 90512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32405 /* 90518 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32406 /* 90524 */ GIR_RootConstrainSelectedInstOperands,
32407 /* 90525 */ // GIR_Coverage, 3614,
32408 /* 90525 */ GIR_EraseRootFromParent_Done,
32409 /* 90526 */ // Label 1730: @90526
32410 /* 90526 */ GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(90616), // Rule ID 3560 //
32411 /* 90531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32412 /* 90534 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32413 /* 90539 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32414 /* 90542 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32415 /* 90545 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32416 /* 90548 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32417 /* 90551 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32418 /* 90554 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32419 /* 90557 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32420 /* 90560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32421 /* 90564 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32422 /* 90568 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32423 /* 90572 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32424 /* 90576 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32425 /* 90580 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32426 /* 90584 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32427 /* 90588 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32428 /* 90588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas8),
32429 /* 90591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32430 /* 90593 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32431 /* 90595 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32432 /* 90597 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32433 /* 90599 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32434 /* 90602 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32435 /* 90608 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32436 /* 90614 */ GIR_RootConstrainSelectedInstOperands,
32437 /* 90615 */ // GIR_Coverage, 3560,
32438 /* 90615 */ GIR_EraseRootFromParent_Done,
32439 /* 90616 */ // Label 1731: @90616
32440 /* 90616 */ GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(90706), // Rule ID 3564 //
32441 /* 90621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32442 /* 90624 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32443 /* 90629 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32444 /* 90632 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32445 /* 90635 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32446 /* 90638 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32447 /* 90641 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32448 /* 90644 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32449 /* 90647 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32450 /* 90650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32451 /* 90654 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32452 /* 90658 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32453 /* 90662 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32454 /* 90666 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32455 /* 90670 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32456 /* 90674 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32457 /* 90678 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32458 /* 90678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs8),
32459 /* 90681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32460 /* 90683 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32461 /* 90685 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32462 /* 90687 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32463 /* 90689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32464 /* 90692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32465 /* 90698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32466 /* 90704 */ GIR_RootConstrainSelectedInstOperands,
32467 /* 90705 */ // GIR_Coverage, 3564,
32468 /* 90705 */ GIR_EraseRootFromParent_Done,
32469 /* 90706 */ // Label 1732: @90706
32470 /* 90706 */ GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(90796), // Rule ID 3568 //
32471 /* 90711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32472 /* 90714 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32473 /* 90719 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32474 /* 90722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32475 /* 90725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32476 /* 90728 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32477 /* 90731 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32478 /* 90734 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32479 /* 90737 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32480 /* 90740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32481 /* 90744 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
32482 /* 90748 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32483 /* 90752 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32484 /* 90756 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32485 /* 90760 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32486 /* 90764 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32487 /* 90768 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVau8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32488 /* 90768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8),
32489 /* 90771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32490 /* 90773 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32491 /* 90775 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32492 /* 90777 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32493 /* 90779 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32494 /* 90782 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32495 /* 90788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32496 /* 90794 */ GIR_RootConstrainSelectedInstOperands,
32497 /* 90795 */ // GIR_Coverage, 3568,
32498 /* 90795 */ GIR_EraseRootFromParent_Done,
32499 /* 90796 */ // Label 1733: @90796
32500 /* 90796 */ GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(90886), // Rule ID 3572 //
32501 /* 90801 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32502 /* 90804 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32503 /* 90809 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32504 /* 90812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32505 /* 90815 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32506 /* 90818 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32507 /* 90821 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32508 /* 90824 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32509 /* 90827 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32510 /* 90830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32511 /* 90834 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32512 /* 90838 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32513 /* 90842 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32514 /* 90846 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32515 /* 90850 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32516 /* 90854 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32517 /* 90858 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32518 /* 90858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas16),
32519 /* 90861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32520 /* 90863 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32521 /* 90865 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32522 /* 90867 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32523 /* 90869 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32524 /* 90872 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32525 /* 90878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32526 /* 90884 */ GIR_RootConstrainSelectedInstOperands,
32527 /* 90885 */ // GIR_Coverage, 3572,
32528 /* 90885 */ GIR_EraseRootFromParent_Done,
32529 /* 90886 */ // Label 1734: @90886
32530 /* 90886 */ GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(90976), // Rule ID 3576 //
32531 /* 90891 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32532 /* 90894 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32533 /* 90899 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32534 /* 90902 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32535 /* 90905 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32536 /* 90908 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32537 /* 90911 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32538 /* 90914 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32539 /* 90917 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32540 /* 90920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32541 /* 90924 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32542 /* 90928 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32543 /* 90932 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32544 /* 90936 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32545 /* 90940 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32546 /* 90944 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32547 /* 90948 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32548 /* 90948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs16),
32549 /* 90951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32550 /* 90953 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32551 /* 90955 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32552 /* 90957 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32553 /* 90959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32554 /* 90962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32555 /* 90968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32556 /* 90974 */ GIR_RootConstrainSelectedInstOperands,
32557 /* 90975 */ // GIR_Coverage, 3576,
32558 /* 90975 */ GIR_EraseRootFromParent_Done,
32559 /* 90976 */ // Label 1735: @90976
32560 /* 90976 */ GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(91066), // Rule ID 3580 //
32561 /* 90981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32562 /* 90984 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32563 /* 90989 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32564 /* 90992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32565 /* 90995 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32566 /* 90998 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32567 /* 91001 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32568 /* 91004 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32569 /* 91007 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32570 /* 91010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32571 /* 91014 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
32572 /* 91018 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32573 /* 91022 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32574 /* 91026 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32575 /* 91030 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32576 /* 91034 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32577 /* 91038 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVau16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32578 /* 91038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16),
32579 /* 91041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32580 /* 91043 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32581 /* 91045 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32582 /* 91047 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32583 /* 91049 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32584 /* 91052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32585 /* 91058 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32586 /* 91064 */ GIR_RootConstrainSelectedInstOperands,
32587 /* 91065 */ // GIR_Coverage, 3580,
32588 /* 91065 */ GIR_EraseRootFromParent_Done,
32589 /* 91066 */ // Label 1736: @91066
32590 /* 91066 */ GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(91156), // Rule ID 3584 //
32591 /* 91071 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32592 /* 91074 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32593 /* 91079 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32594 /* 91082 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32595 /* 91085 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32596 /* 91088 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32597 /* 91091 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32598 /* 91094 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32599 /* 91097 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32600 /* 91100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32601 /* 91104 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32602 /* 91108 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32603 /* 91112 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32604 /* 91116 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32605 /* 91120 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32606 /* 91124 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32607 /* 91128 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32608 /* 91128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas32),
32609 /* 91131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32610 /* 91133 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32611 /* 91135 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32612 /* 91137 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32613 /* 91139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32614 /* 91142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32615 /* 91148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32616 /* 91154 */ GIR_RootConstrainSelectedInstOperands,
32617 /* 91155 */ // GIR_Coverage, 3584,
32618 /* 91155 */ GIR_EraseRootFromParent_Done,
32619 /* 91156 */ // Label 1737: @91156
32620 /* 91156 */ GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(91246), // Rule ID 3588 //
32621 /* 91161 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32622 /* 91164 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32623 /* 91169 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32624 /* 91172 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32625 /* 91175 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32626 /* 91178 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32627 /* 91181 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32628 /* 91184 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32629 /* 91187 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32630 /* 91190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32631 /* 91194 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32632 /* 91198 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32633 /* 91202 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32634 /* 91206 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32635 /* 91210 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32636 /* 91214 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32637 /* 91218 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32638 /* 91218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs32),
32639 /* 91221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32640 /* 91223 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32641 /* 91225 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32642 /* 91227 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32643 /* 91229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32644 /* 91232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32645 /* 91238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32646 /* 91244 */ GIR_RootConstrainSelectedInstOperands,
32647 /* 91245 */ // GIR_Coverage, 3588,
32648 /* 91245 */ GIR_EraseRootFromParent_Done,
32649 /* 91246 */ // Label 1738: @91246
32650 /* 91246 */ GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(91336), // Rule ID 3592 //
32651 /* 91251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32652 /* 91254 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32653 /* 91259 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32654 /* 91262 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32655 /* 91265 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32656 /* 91268 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32657 /* 91271 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32658 /* 91274 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32659 /* 91277 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32660 /* 91280 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32661 /* 91284 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
32662 /* 91288 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32663 /* 91292 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32664 /* 91296 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32665 /* 91300 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32666 /* 91304 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32667 /* 91308 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVau32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32668 /* 91308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32),
32669 /* 91311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32670 /* 91313 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32671 /* 91315 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32672 /* 91317 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32673 /* 91319 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32674 /* 91322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32675 /* 91328 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32676 /* 91334 */ GIR_RootConstrainSelectedInstOperands,
32677 /* 91335 */ // GIR_Coverage, 3592,
32678 /* 91335 */ GIR_EraseRootFromParent_Done,
32679 /* 91336 */ // Label 1739: @91336
32680 /* 91336 */ GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(91426), // Rule ID 3596 //
32681 /* 91341 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32682 /* 91344 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32683 /* 91349 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32684 /* 91352 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32685 /* 91355 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32686 /* 91358 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32687 /* 91361 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32688 /* 91364 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32689 /* 91367 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32690 /* 91370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32691 /* 91374 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32692 /* 91378 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32693 /* 91382 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32694 /* 91386 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32695 /* 91390 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32696 /* 91394 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32697 /* 91398 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32698 /* 91398 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas8),
32699 /* 91401 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32700 /* 91403 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32701 /* 91405 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32702 /* 91407 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32703 /* 91409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32704 /* 91412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32705 /* 91418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32706 /* 91424 */ GIR_RootConstrainSelectedInstOperands,
32707 /* 91425 */ // GIR_Coverage, 3596,
32708 /* 91425 */ GIR_EraseRootFromParent_Done,
32709 /* 91426 */ // Label 1740: @91426
32710 /* 91426 */ GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(91516), // Rule ID 3600 //
32711 /* 91431 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32712 /* 91434 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32713 /* 91439 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32714 /* 91442 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32715 /* 91445 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32716 /* 91448 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32717 /* 91451 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32718 /* 91454 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32719 /* 91457 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32720 /* 91460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32721 /* 91464 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32722 /* 91468 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32723 /* 91472 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32724 /* 91476 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32725 /* 91480 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32726 /* 91484 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32727 /* 91488 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32728 /* 91488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs8),
32729 /* 91491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32730 /* 91493 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32731 /* 91495 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32732 /* 91497 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32733 /* 91499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32734 /* 91502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32735 /* 91508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32736 /* 91514 */ GIR_RootConstrainSelectedInstOperands,
32737 /* 91515 */ // GIR_Coverage, 3600,
32738 /* 91515 */ GIR_EraseRootFromParent_Done,
32739 /* 91516 */ // Label 1741: @91516
32740 /* 91516 */ GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(91606), // Rule ID 3604 //
32741 /* 91521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32742 /* 91524 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32743 /* 91529 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32744 /* 91532 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32745 /* 91535 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32746 /* 91538 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32747 /* 91541 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32748 /* 91544 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32749 /* 91547 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32750 /* 91550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32751 /* 91554 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32752 /* 91558 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32753 /* 91562 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32754 /* 91566 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32755 /* 91570 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32756 /* 91574 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32757 /* 91578 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32758 /* 91578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas16),
32759 /* 91581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32760 /* 91583 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32761 /* 91585 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32762 /* 91587 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32763 /* 91589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32764 /* 91592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32765 /* 91598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32766 /* 91604 */ GIR_RootConstrainSelectedInstOperands,
32767 /* 91605 */ // GIR_Coverage, 3604,
32768 /* 91605 */ GIR_EraseRootFromParent_Done,
32769 /* 91606 */ // Label 1742: @91606
32770 /* 91606 */ GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(91696), // Rule ID 3608 //
32771 /* 91611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32772 /* 91614 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32773 /* 91619 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32774 /* 91622 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32775 /* 91625 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32776 /* 91628 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32777 /* 91631 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32778 /* 91634 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32779 /* 91637 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32780 /* 91640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32781 /* 91644 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32782 /* 91648 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32783 /* 91652 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32784 /* 91656 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32785 /* 91660 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32786 /* 91664 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32787 /* 91668 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32788 /* 91668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs16),
32789 /* 91671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32790 /* 91673 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32791 /* 91675 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32792 /* 91677 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32793 /* 91679 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32794 /* 91682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32795 /* 91688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32796 /* 91694 */ GIR_RootConstrainSelectedInstOperands,
32797 /* 91695 */ // GIR_Coverage, 3608,
32798 /* 91695 */ GIR_EraseRootFromParent_Done,
32799 /* 91696 */ // Label 1743: @91696
32800 /* 91696 */ GIM_Try, /*On fail goto*//*Label 1744*/ GIMT_Encode4(91786), // Rule ID 3612 //
32801 /* 91701 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32802 /* 91704 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32803 /* 91709 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32804 /* 91712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32805 /* 91715 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32806 /* 91718 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32807 /* 91721 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32808 /* 91724 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32809 /* 91727 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32810 /* 91730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32811 /* 91734 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32812 /* 91738 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32813 /* 91742 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32814 /* 91746 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32815 /* 91750 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32816 /* 91754 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32817 /* 91758 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32818 /* 91758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas32),
32819 /* 91761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32820 /* 91763 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32821 /* 91765 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32822 /* 91767 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32823 /* 91769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32824 /* 91772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32825 /* 91778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32826 /* 91784 */ GIR_RootConstrainSelectedInstOperands,
32827 /* 91785 */ // GIR_Coverage, 3612,
32828 /* 91785 */ GIR_EraseRootFromParent_Done,
32829 /* 91786 */ // Label 1744: @91786
32830 /* 91786 */ GIM_Try, /*On fail goto*//*Label 1745*/ GIMT_Encode4(91876), // Rule ID 3616 //
32831 /* 91791 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32832 /* 91794 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32833 /* 91799 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32834 /* 91802 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32835 /* 91805 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32836 /* 91808 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32837 /* 91811 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32838 /* 91814 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32839 /* 91817 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32840 /* 91820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32841 /* 91824 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32842 /* 91828 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32843 /* 91832 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32844 /* 91836 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32845 /* 91840 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32846 /* 91844 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32847 /* 91848 */ // (intrinsic_wo_chain:{ *:[i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32848 /* 91848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs32),
32849 /* 91851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32850 /* 91853 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32851 /* 91855 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32852 /* 91857 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32853 /* 91859 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32854 /* 91862 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32855 /* 91868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32856 /* 91874 */ GIR_RootConstrainSelectedInstOperands,
32857 /* 91875 */ // GIR_Coverage, 3616,
32858 /* 91875 */ GIR_EraseRootFromParent_Done,
32859 /* 91876 */ // Label 1745: @91876
32860 /* 91876 */ GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(91963), // Rule ID 4826 //
32861 /* 91881 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32862 /* 91886 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
32863 /* 91889 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
32864 /* 91892 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
32865 /* 91895 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
32866 /* 91898 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32867 /* 91901 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
32868 /* 91904 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
32869 /* 91907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32870 /* 91911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32871 /* 91915 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32872 /* 91919 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32873 /* 91923 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32874 /* 91927 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32875 /* 91931 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32876 /* 91935 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3915:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
32877 /* 91935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs8),
32878 /* 91938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32879 /* 91940 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
32880 /* 91942 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
32881 /* 91944 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
32882 /* 91946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32883 /* 91949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32884 /* 91955 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32885 /* 91961 */ GIR_RootConstrainSelectedInstOperands,
32886 /* 91962 */ // GIR_Coverage, 4826,
32887 /* 91962 */ GIR_EraseRootFromParent_Done,
32888 /* 91963 */ // Label 1746: @91963
32889 /* 91963 */ GIM_Try, /*On fail goto*//*Label 1747*/ GIMT_Encode4(92050), // Rule ID 4828 //
32890 /* 91968 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32891 /* 91973 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
32892 /* 91976 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
32893 /* 91979 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
32894 /* 91982 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
32895 /* 91985 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32896 /* 91988 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
32897 /* 91991 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
32898 /* 91994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32899 /* 91998 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32900 /* 92002 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32901 /* 92006 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32902 /* 92010 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32903 /* 92014 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32904 /* 92018 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32905 /* 92022 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3915:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
32906 /* 92022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs16),
32907 /* 92025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32908 /* 92027 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
32909 /* 92029 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
32910 /* 92031 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
32911 /* 92033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32912 /* 92036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32913 /* 92042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32914 /* 92048 */ GIR_RootConstrainSelectedInstOperands,
32915 /* 92049 */ // GIR_Coverage, 4828,
32916 /* 92049 */ GIR_EraseRootFromParent_Done,
32917 /* 92050 */ // Label 1747: @92050
32918 /* 92050 */ GIM_Try, /*On fail goto*//*Label 1748*/ GIMT_Encode4(92137), // Rule ID 4830 //
32919 /* 92055 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32920 /* 92060 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
32921 /* 92063 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
32922 /* 92066 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
32923 /* 92069 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
32924 /* 92072 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32925 /* 92075 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
32926 /* 92078 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
32927 /* 92081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32928 /* 92085 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32929 /* 92089 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32930 /* 92093 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32931 /* 92097 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32932 /* 92101 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32933 /* 92105 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32934 /* 92109 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3915:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
32935 /* 92109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs32),
32936 /* 92112 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32937 /* 92114 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
32938 /* 92116 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
32939 /* 92118 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
32940 /* 92120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32941 /* 92123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32942 /* 92129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32943 /* 92135 */ GIR_RootConstrainSelectedInstOperands,
32944 /* 92136 */ // GIR_Coverage, 4830,
32945 /* 92136 */ GIR_EraseRootFromParent_Done,
32946 /* 92137 */ // Label 1748: @92137
32947 /* 92137 */ GIM_Try, /*On fail goto*//*Label 1749*/ GIMT_Encode4(92224), // Rule ID 4832 //
32948 /* 92142 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32949 /* 92147 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
32950 /* 92150 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
32951 /* 92153 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
32952 /* 92156 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
32953 /* 92159 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32954 /* 92162 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
32955 /* 92165 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
32956 /* 92168 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32957 /* 92172 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32958 /* 92176 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32959 /* 92180 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32960 /* 92184 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32961 /* 92188 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32962 /* 92192 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32963 /* 92196 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3915:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
32964 /* 92196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs8),
32965 /* 92199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32966 /* 92201 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
32967 /* 92203 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
32968 /* 92205 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
32969 /* 92207 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32970 /* 92210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32971 /* 92216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32972 /* 92222 */ GIR_RootConstrainSelectedInstOperands,
32973 /* 92223 */ // GIR_Coverage, 4832,
32974 /* 92223 */ GIR_EraseRootFromParent_Done,
32975 /* 92224 */ // Label 1749: @92224
32976 /* 92224 */ GIM_Try, /*On fail goto*//*Label 1750*/ GIMT_Encode4(92311), // Rule ID 4834 //
32977 /* 92229 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
32978 /* 92234 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
32979 /* 92237 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
32980 /* 92240 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
32981 /* 92243 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
32982 /* 92246 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32983 /* 92249 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
32984 /* 92252 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
32985 /* 92255 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32986 /* 92259 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32987 /* 92263 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32988 /* 92267 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32989 /* 92271 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32990 /* 92275 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32991 /* 92279 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32992 /* 92283 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3915:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
32993 /* 92283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs16),
32994 /* 92286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32995 /* 92288 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
32996 /* 92290 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
32997 /* 92292 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
32998 /* 92294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32999 /* 92297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33000 /* 92303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33001 /* 92309 */ GIR_RootConstrainSelectedInstOperands,
33002 /* 92310 */ // GIR_Coverage, 4834,
33003 /* 92310 */ GIR_EraseRootFromParent_Done,
33004 /* 92311 */ // Label 1750: @92311
33005 /* 92311 */ GIM_Try, /*On fail goto*//*Label 1751*/ GIMT_Encode4(92398), // Rule ID 4836 //
33006 /* 92316 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33007 /* 92321 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
33008 /* 92324 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33009 /* 92327 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33010 /* 92330 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33011 /* 92333 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33012 /* 92336 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33013 /* 92339 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33014 /* 92342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33015 /* 92346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33016 /* 92350 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33017 /* 92354 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33018 /* 92358 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33019 /* 92362 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33020 /* 92366 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33021 /* 92370 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3915:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33022 /* 92370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs32),
33023 /* 92373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33024 /* 92375 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33025 /* 92377 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33026 /* 92379 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33027 /* 92381 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33028 /* 92384 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33029 /* 92390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33030 /* 92396 */ GIR_RootConstrainSelectedInstOperands,
33031 /* 92397 */ // GIR_Coverage, 4836,
33032 /* 92397 */ GIR_EraseRootFromParent_Done,
33033 /* 92398 */ // Label 1751: @92398
33034 /* 92398 */ GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(92485), // Rule ID 4838 //
33035 /* 92403 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33036 /* 92408 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33037 /* 92411 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33038 /* 92414 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33039 /* 92417 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
33040 /* 92420 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33041 /* 92423 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33042 /* 92426 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33043 /* 92429 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33044 /* 92433 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33045 /* 92437 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33046 /* 92441 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33047 /* 92445 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33048 /* 92449 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33049 /* 92453 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33050 /* 92457 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3915:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33051 /* 92457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs8),
33052 /* 92460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33053 /* 92462 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33054 /* 92464 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33055 /* 92466 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33056 /* 92468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33057 /* 92471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33058 /* 92477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33059 /* 92483 */ GIR_RootConstrainSelectedInstOperands,
33060 /* 92484 */ // GIR_Coverage, 4838,
33061 /* 92484 */ GIR_EraseRootFromParent_Done,
33062 /* 92485 */ // Label 1752: @92485
33063 /* 92485 */ GIM_Try, /*On fail goto*//*Label 1753*/ GIMT_Encode4(92572), // Rule ID 4840 //
33064 /* 92490 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33065 /* 92495 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33066 /* 92498 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33067 /* 92501 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33068 /* 92504 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
33069 /* 92507 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33070 /* 92510 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33071 /* 92513 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33072 /* 92516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33073 /* 92520 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33074 /* 92524 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33075 /* 92528 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33076 /* 92532 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33077 /* 92536 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33078 /* 92540 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33079 /* 92544 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3915:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33080 /* 92544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs16),
33081 /* 92547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33082 /* 92549 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33083 /* 92551 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33084 /* 92553 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33085 /* 92555 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33086 /* 92558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33087 /* 92564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33088 /* 92570 */ GIR_RootConstrainSelectedInstOperands,
33089 /* 92571 */ // GIR_Coverage, 4840,
33090 /* 92571 */ GIR_EraseRootFromParent_Done,
33091 /* 92572 */ // Label 1753: @92572
33092 /* 92572 */ GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(92659), // Rule ID 4842 //
33093 /* 92577 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33094 /* 92582 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
33095 /* 92585 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33096 /* 92588 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33097 /* 92591 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33098 /* 92594 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33099 /* 92597 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33100 /* 92600 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33101 /* 92603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33102 /* 92607 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33103 /* 92611 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33104 /* 92615 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33105 /* 92619 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33106 /* 92623 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33107 /* 92627 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33108 /* 92631 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3915:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33109 /* 92631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs32),
33110 /* 92634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33111 /* 92636 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33112 /* 92638 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33113 /* 92640 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33114 /* 92642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33115 /* 92645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33116 /* 92651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33117 /* 92657 */ GIR_RootConstrainSelectedInstOperands,
33118 /* 92658 */ // GIR_Coverage, 4842,
33119 /* 92658 */ GIR_EraseRootFromParent_Done,
33120 /* 92659 */ // Label 1754: @92659
33121 /* 92659 */ GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(92746), // Rule ID 4844 //
33122 /* 92664 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33123 /* 92669 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33124 /* 92672 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33125 /* 92675 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33126 /* 92678 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
33127 /* 92681 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33128 /* 92684 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33129 /* 92687 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33130 /* 92690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33131 /* 92694 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33132 /* 92698 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33133 /* 92702 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33134 /* 92706 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33135 /* 92710 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33136 /* 92714 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33137 /* 92718 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3915:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33138 /* 92718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs8),
33139 /* 92721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33140 /* 92723 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33141 /* 92725 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33142 /* 92727 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33143 /* 92729 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33144 /* 92732 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33145 /* 92738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33146 /* 92744 */ GIR_RootConstrainSelectedInstOperands,
33147 /* 92745 */ // GIR_Coverage, 4844,
33148 /* 92745 */ GIR_EraseRootFromParent_Done,
33149 /* 92746 */ // Label 1755: @92746
33150 /* 92746 */ GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(92833), // Rule ID 4846 //
33151 /* 92751 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33152 /* 92756 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33153 /* 92759 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33154 /* 92762 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33155 /* 92765 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
33156 /* 92768 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33157 /* 92771 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33158 /* 92774 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33159 /* 92777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33160 /* 92781 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33161 /* 92785 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33162 /* 92789 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33163 /* 92793 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33164 /* 92797 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33165 /* 92801 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33166 /* 92805 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3915:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33167 /* 92805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs16),
33168 /* 92808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33169 /* 92810 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33170 /* 92812 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33171 /* 92814 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33172 /* 92816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33173 /* 92819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33174 /* 92825 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33175 /* 92831 */ GIR_RootConstrainSelectedInstOperands,
33176 /* 92832 */ // GIR_Coverage, 4846,
33177 /* 92832 */ GIR_EraseRootFromParent_Done,
33178 /* 92833 */ // Label 1756: @92833
33179 /* 92833 */ GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(92920), // Rule ID 4848 //
33180 /* 92838 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33181 /* 92843 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
33182 /* 92846 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33183 /* 92849 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33184 /* 92852 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33185 /* 92855 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33186 /* 92858 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33187 /* 92861 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33188 /* 92864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33189 /* 92868 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33190 /* 92872 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33191 /* 92876 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33192 /* 92880 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33193 /* 92884 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33194 /* 92888 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33195 /* 92892 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3915:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33196 /* 92892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs32),
33197 /* 92895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33198 /* 92897 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33199 /* 92899 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33200 /* 92901 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33201 /* 92903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33202 /* 92906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33203 /* 92912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33204 /* 92918 */ GIR_RootConstrainSelectedInstOperands,
33205 /* 92919 */ // GIR_Coverage, 4848,
33206 /* 92919 */ GIR_EraseRootFromParent_Done,
33207 /* 92920 */ // Label 1757: @92920
33208 /* 92920 */ GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(93007), // Rule ID 4850 //
33209 /* 92925 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33210 /* 92930 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33211 /* 92933 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33212 /* 92936 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33213 /* 92939 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
33214 /* 92942 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33215 /* 92945 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33216 /* 92948 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33217 /* 92951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33218 /* 92955 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33219 /* 92959 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33220 /* 92963 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33221 /* 92967 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33222 /* 92971 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33223 /* 92975 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33224 /* 92979 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3915:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33225 /* 92979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs8),
33226 /* 92982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33227 /* 92984 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33228 /* 92986 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33229 /* 92988 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33230 /* 92990 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33231 /* 92993 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33232 /* 92999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33233 /* 93005 */ GIR_RootConstrainSelectedInstOperands,
33234 /* 93006 */ // GIR_Coverage, 4850,
33235 /* 93006 */ GIR_EraseRootFromParent_Done,
33236 /* 93007 */ // Label 1758: @93007
33237 /* 93007 */ GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(93094), // Rule ID 4852 //
33238 /* 93012 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33239 /* 93017 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33240 /* 93020 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33241 /* 93023 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33242 /* 93026 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
33243 /* 93029 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33244 /* 93032 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33245 /* 93035 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33246 /* 93038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33247 /* 93042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33248 /* 93046 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33249 /* 93050 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33250 /* 93054 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33251 /* 93058 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33252 /* 93062 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33253 /* 93066 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3915:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33254 /* 93066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs16),
33255 /* 93069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33256 /* 93071 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33257 /* 93073 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33258 /* 93075 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33259 /* 93077 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33260 /* 93080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33261 /* 93086 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33262 /* 93092 */ GIR_RootConstrainSelectedInstOperands,
33263 /* 93093 */ // GIR_Coverage, 4852,
33264 /* 93093 */ GIR_EraseRootFromParent_Done,
33265 /* 93094 */ // Label 1759: @93094
33266 /* 93094 */ GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(93181), // Rule ID 4854 //
33267 /* 93099 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33268 /* 93104 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
33269 /* 93107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33270 /* 93110 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33271 /* 93113 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33272 /* 93116 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33273 /* 93119 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33274 /* 93122 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33275 /* 93125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33276 /* 93129 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33277 /* 93133 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33278 /* 93137 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33279 /* 93141 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33280 /* 93145 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33281 /* 93149 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33282 /* 93153 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3915:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33283 /* 93153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs32),
33284 /* 93156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33285 /* 93158 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33286 /* 93160 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33287 /* 93162 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33288 /* 93164 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33289 /* 93167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33290 /* 93173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33291 /* 93179 */ GIR_RootConstrainSelectedInstOperands,
33292 /* 93180 */ // GIR_Coverage, 4854,
33293 /* 93180 */ GIR_EraseRootFromParent_Done,
33294 /* 93181 */ // Label 1760: @93181
33295 /* 93181 */ GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(93268), // Rule ID 4856 //
33296 /* 93186 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33297 /* 93191 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33298 /* 93194 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33299 /* 93197 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33300 /* 93200 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
33301 /* 93203 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33302 /* 93206 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33303 /* 93209 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33304 /* 93212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33305 /* 93216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33306 /* 93220 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33307 /* 93224 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33308 /* 93228 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33309 /* 93232 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33310 /* 93236 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33311 /* 93240 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3915:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33312 /* 93240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs8),
33313 /* 93243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33314 /* 93245 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33315 /* 93247 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33316 /* 93249 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33317 /* 93251 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33318 /* 93254 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33319 /* 93260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33320 /* 93266 */ GIR_RootConstrainSelectedInstOperands,
33321 /* 93267 */ // GIR_Coverage, 4856,
33322 /* 93267 */ GIR_EraseRootFromParent_Done,
33323 /* 93268 */ // Label 1761: @93268
33324 /* 93268 */ GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(93355), // Rule ID 4858 //
33325 /* 93273 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33326 /* 93278 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33327 /* 93281 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33328 /* 93284 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33329 /* 93287 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
33330 /* 93290 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33331 /* 93293 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33332 /* 93296 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33333 /* 93299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33334 /* 93303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33335 /* 93307 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33336 /* 93311 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33337 /* 93315 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33338 /* 93319 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33339 /* 93323 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33340 /* 93327 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3915:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33341 /* 93327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs16),
33342 /* 93330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33343 /* 93332 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33344 /* 93334 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33345 /* 93336 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33346 /* 93338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33347 /* 93341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33348 /* 93347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33349 /* 93353 */ GIR_RootConstrainSelectedInstOperands,
33350 /* 93354 */ // GIR_Coverage, 4858,
33351 /* 93354 */ GIR_EraseRootFromParent_Done,
33352 /* 93355 */ // Label 1762: @93355
33353 /* 93355 */ GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(93442), // Rule ID 4860 //
33354 /* 93360 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33355 /* 93365 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
33356 /* 93368 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33357 /* 93371 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33358 /* 93374 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33359 /* 93377 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33360 /* 93380 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33361 /* 93383 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33362 /* 93386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33363 /* 93390 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33364 /* 93394 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33365 /* 93398 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33366 /* 93402 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33367 /* 93406 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33368 /* 93410 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33369 /* 93414 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3915:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33370 /* 93414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs32),
33371 /* 93417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33372 /* 93419 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33373 /* 93421 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33374 /* 93423 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33375 /* 93425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33376 /* 93428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33377 /* 93434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33378 /* 93440 */ GIR_RootConstrainSelectedInstOperands,
33379 /* 93441 */ // GIR_Coverage, 4860,
33380 /* 93441 */ GIR_EraseRootFromParent_Done,
33381 /* 93442 */ // Label 1763: @93442
33382 /* 93442 */ GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(93529), // Rule ID 4862 //
33383 /* 93447 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33384 /* 93452 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33385 /* 93455 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33386 /* 93458 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33387 /* 93461 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
33388 /* 93464 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33389 /* 93467 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33390 /* 93470 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33391 /* 93473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33392 /* 93477 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33393 /* 93481 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33394 /* 93485 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33395 /* 93489 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33396 /* 93493 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33397 /* 93497 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33398 /* 93501 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3915:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33399 /* 93501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs8),
33400 /* 93504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33401 /* 93506 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33402 /* 93508 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33403 /* 93510 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33404 /* 93512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33405 /* 93515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33406 /* 93521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33407 /* 93527 */ GIR_RootConstrainSelectedInstOperands,
33408 /* 93528 */ // GIR_Coverage, 4862,
33409 /* 93528 */ GIR_EraseRootFromParent_Done,
33410 /* 93529 */ // Label 1764: @93529
33411 /* 93529 */ GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(93616), // Rule ID 4864 //
33412 /* 93534 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33413 /* 93539 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33414 /* 93542 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33415 /* 93545 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33416 /* 93548 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
33417 /* 93551 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33418 /* 93554 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33419 /* 93557 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33420 /* 93560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33421 /* 93564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33422 /* 93568 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33423 /* 93572 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33424 /* 93576 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33425 /* 93580 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33426 /* 93584 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33427 /* 93588 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3915:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33428 /* 93588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs16),
33429 /* 93591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33430 /* 93593 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33431 /* 93595 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33432 /* 93597 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33433 /* 93599 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33434 /* 93602 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33435 /* 93608 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33436 /* 93614 */ GIR_RootConstrainSelectedInstOperands,
33437 /* 93615 */ // GIR_Coverage, 4864,
33438 /* 93615 */ GIR_EraseRootFromParent_Done,
33439 /* 93616 */ // Label 1765: @93616
33440 /* 93616 */ GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(93703), // Rule ID 4866 //
33441 /* 93621 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33442 /* 93626 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
33443 /* 93629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33444 /* 93632 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33445 /* 93635 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33446 /* 93638 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33447 /* 93641 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33448 /* 93644 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33449 /* 93647 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33450 /* 93651 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33451 /* 93655 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33452 /* 93659 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33453 /* 93663 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33454 /* 93667 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33455 /* 93671 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33456 /* 93675 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3915:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33457 /* 93675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs32),
33458 /* 93678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33459 /* 93680 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33460 /* 93682 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33461 /* 93684 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33462 /* 93686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33463 /* 93689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33464 /* 93695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33465 /* 93701 */ GIR_RootConstrainSelectedInstOperands,
33466 /* 93702 */ // GIR_Coverage, 4866,
33467 /* 93702 */ GIR_EraseRootFromParent_Done,
33468 /* 93703 */ // Label 1766: @93703
33469 /* 93703 */ GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(93790), // Rule ID 4868 //
33470 /* 93708 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33471 /* 93713 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33472 /* 93716 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33473 /* 93719 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33474 /* 93722 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
33475 /* 93725 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33476 /* 93728 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33477 /* 93731 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33478 /* 93734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33479 /* 93738 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33480 /* 93742 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33481 /* 93746 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33482 /* 93750 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33483 /* 93754 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33484 /* 93758 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33485 /* 93762 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3915:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33486 /* 93762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs8),
33487 /* 93765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33488 /* 93767 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33489 /* 93769 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33490 /* 93771 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33491 /* 93773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33492 /* 93776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33493 /* 93782 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33494 /* 93788 */ GIR_RootConstrainSelectedInstOperands,
33495 /* 93789 */ // GIR_Coverage, 4868,
33496 /* 93789 */ GIR_EraseRootFromParent_Done,
33497 /* 93790 */ // Label 1767: @93790
33498 /* 93790 */ GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(93877), // Rule ID 4870 //
33499 /* 93795 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33500 /* 93800 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33501 /* 93803 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33502 /* 93806 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33503 /* 93809 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
33504 /* 93812 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33505 /* 93815 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33506 /* 93818 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33507 /* 93821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33508 /* 93825 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33509 /* 93829 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33510 /* 93833 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33511 /* 93837 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33512 /* 93841 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33513 /* 93845 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33514 /* 93849 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3915:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33515 /* 93849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs16),
33516 /* 93852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33517 /* 93854 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33518 /* 93856 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33519 /* 93858 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33520 /* 93860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33521 /* 93863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33522 /* 93869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33523 /* 93875 */ GIR_RootConstrainSelectedInstOperands,
33524 /* 93876 */ // GIR_Coverage, 4870,
33525 /* 93876 */ GIR_EraseRootFromParent_Done,
33526 /* 93877 */ // Label 1768: @93877
33527 /* 93877 */ GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(93964), // Rule ID 4872 //
33528 /* 93882 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33529 /* 93887 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
33530 /* 93890 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33531 /* 93893 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33532 /* 93896 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33533 /* 93899 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33534 /* 93902 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33535 /* 93905 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33536 /* 93908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33537 /* 93912 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33538 /* 93916 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33539 /* 93920 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33540 /* 93924 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33541 /* 93928 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33542 /* 93932 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33543 /* 93936 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3915:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33544 /* 93936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs32),
33545 /* 93939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33546 /* 93941 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33547 /* 93943 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33548 /* 93945 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33549 /* 93947 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33550 /* 93950 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33551 /* 93956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33552 /* 93962 */ GIR_RootConstrainSelectedInstOperands,
33553 /* 93963 */ // GIR_Coverage, 4872,
33554 /* 93963 */ GIR_EraseRootFromParent_Done,
33555 /* 93964 */ // Label 1769: @93964
33556 /* 93964 */ GIM_Try, /*On fail goto*//*Label 1770*/ GIMT_Encode4(94090), // Rule ID 3067 //
33557 /* 93969 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
33558 /* 93972 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx4),
33559 /* 93977 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
33560 /* 93980 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
33561 /* 93983 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
33562 /* 93986 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
33563 /* 93989 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
33564 /* 93992 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8,
33565 /* 93995 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s8,
33566 /* 93998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
33567 /* 94002 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4117:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBX4Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
33568 /* 94002 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
33569 /* 94005 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
33570 /* 94009 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
33571 /* 94014 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
33572 /* 94018 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
33573 /* 94021 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
33574 /* 94025 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
33575 /* 94028 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
33576 /* 94032 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
33577 /* 94035 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // Vn3
33578 /* 94039 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
33579 /* 94042 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
33580 /* 94047 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
33581 /* 94052 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
33582 /* 94057 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
33583 /* 94062 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
33584 /* 94067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX4Pseudo),
33585 /* 94070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
33586 /* 94072 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
33587 /* 94074 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33588 /* 94077 */ GIR_RootToRootCopy, /*OpIdx*/7, // Vm
33589 /* 94079 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33590 /* 94082 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33591 /* 94088 */ GIR_RootConstrainSelectedInstOperands,
33592 /* 94089 */ // GIR_Coverage, 3067,
33593 /* 94089 */ GIR_EraseRootFromParent_Done,
33594 /* 94090 */ // Label 1770: @94090
33595 /* 94090 */ GIM_Reject,
33596 /* 94091 */ // Label 1715: @94091
33597 /* 94091 */ GIM_Try, /*On fail goto*//*Label 1771*/ GIMT_Encode4(98385),
33598 /* 94096 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/10,
33599 /* 94099 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshrn),
33600 /* 94104 */ GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(94211), // Rule ID 4141 //
33601 /* 94109 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33602 /* 94112 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33603 /* 94115 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33604 /* 94118 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33605 /* 94121 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33606 /* 94124 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33607 /* 94127 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33608 /* 94130 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
33609 /* 94133 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
33610 /* 94136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33611 /* 94140 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33612 /* 94144 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33613 /* 94148 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33614 /* 94152 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33615 /* 94156 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33616 /* 94160 */ // MIs[1] Operand 1
33617 /* 94160 */ // No operand predicates
33618 /* 94160 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33619 /* 94164 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33620 /* 94168 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33621 /* 94172 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33622 /* 94176 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
33623 /* 94180 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33624 /* 94182 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33625 /* 94182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh),
33626 /* 94185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33627 /* 94187 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
33628 /* 94189 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
33629 /* 94191 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33630 /* 94194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33631 /* 94197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33632 /* 94203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33633 /* 94209 */ GIR_RootConstrainSelectedInstOperands,
33634 /* 94210 */ // GIR_Coverage, 4141,
33635 /* 94210 */ GIR_EraseRootFromParent_Done,
33636 /* 94211 */ // Label 1772: @94211
33637 /* 94211 */ GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(94318), // Rule ID 4143 //
33638 /* 94216 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33639 /* 94219 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33640 /* 94222 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33641 /* 94225 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33642 /* 94228 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33643 /* 94231 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33644 /* 94234 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33645 /* 94237 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
33646 /* 94240 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
33647 /* 94243 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33648 /* 94247 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33649 /* 94251 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33650 /* 94255 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33651 /* 94259 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33652 /* 94263 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33653 /* 94267 */ // MIs[1] Operand 1
33654 /* 94267 */ // No operand predicates
33655 /* 94267 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33656 /* 94271 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33657 /* 94275 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33658 /* 94279 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33659 /* 94283 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
33660 /* 94287 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33661 /* 94289 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33662 /* 94289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th),
33663 /* 94292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33664 /* 94294 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
33665 /* 94296 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
33666 /* 94298 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33667 /* 94301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33668 /* 94304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33669 /* 94310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33670 /* 94316 */ GIR_RootConstrainSelectedInstOperands,
33671 /* 94317 */ // GIR_Coverage, 4143,
33672 /* 94317 */ GIR_EraseRootFromParent_Done,
33673 /* 94318 */ // Label 1773: @94318
33674 /* 94318 */ GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(94425), // Rule ID 4145 //
33675 /* 94323 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33676 /* 94326 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33677 /* 94329 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33678 /* 94332 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33679 /* 94335 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33680 /* 94338 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33681 /* 94341 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33682 /* 94344 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
33683 /* 94347 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
33684 /* 94350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33685 /* 94354 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33686 /* 94358 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33687 /* 94362 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33688 /* 94366 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33689 /* 94370 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
33690 /* 94374 */ // MIs[1] Operand 1
33691 /* 94374 */ // No operand predicates
33692 /* 94374 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33693 /* 94378 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33694 /* 94382 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33695 /* 94386 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33696 /* 94390 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
33697 /* 94394 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33698 /* 94396 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33699 /* 94396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh),
33700 /* 94399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33701 /* 94401 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
33702 /* 94403 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
33703 /* 94405 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33704 /* 94408 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33705 /* 94411 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33706 /* 94417 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33707 /* 94423 */ GIR_RootConstrainSelectedInstOperands,
33708 /* 94424 */ // GIR_Coverage, 4145,
33709 /* 94424 */ GIR_EraseRootFromParent_Done,
33710 /* 94425 */ // Label 1774: @94425
33711 /* 94425 */ GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(94532), // Rule ID 4147 //
33712 /* 94430 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33713 /* 94433 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33714 /* 94436 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33715 /* 94439 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33716 /* 94442 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33717 /* 94445 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33718 /* 94448 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33719 /* 94451 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
33720 /* 94454 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
33721 /* 94457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33722 /* 94461 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33723 /* 94465 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33724 /* 94469 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33725 /* 94473 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33726 /* 94477 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
33727 /* 94481 */ // MIs[1] Operand 1
33728 /* 94481 */ // No operand predicates
33729 /* 94481 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33730 /* 94485 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33731 /* 94489 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33732 /* 94493 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33733 /* 94497 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
33734 /* 94501 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33735 /* 94503 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33736 /* 94503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th),
33737 /* 94506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33738 /* 94508 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
33739 /* 94510 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
33740 /* 94512 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33741 /* 94515 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33742 /* 94518 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33743 /* 94524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33744 /* 94530 */ GIR_RootConstrainSelectedInstOperands,
33745 /* 94531 */ // GIR_Coverage, 4147,
33746 /* 94531 */ GIR_EraseRootFromParent_Done,
33747 /* 94532 */ // Label 1775: @94532
33748 /* 94532 */ GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(94639), // Rule ID 4149 //
33749 /* 94537 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33750 /* 94540 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33751 /* 94543 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33752 /* 94546 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33753 /* 94549 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33754 /* 94552 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33755 /* 94555 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33756 /* 94558 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
33757 /* 94561 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
33758 /* 94564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33759 /* 94568 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33760 /* 94572 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33761 /* 94576 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33762 /* 94580 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33763 /* 94584 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33764 /* 94588 */ // MIs[1] Operand 1
33765 /* 94588 */ // No operand predicates
33766 /* 94588 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33767 /* 94592 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33768 /* 94596 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33769 /* 94600 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
33770 /* 94604 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
33771 /* 94608 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33772 /* 94610 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33773 /* 94610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh),
33774 /* 94613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33775 /* 94615 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
33776 /* 94617 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
33777 /* 94619 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33778 /* 94622 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33779 /* 94625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33780 /* 94631 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33781 /* 94637 */ GIR_RootConstrainSelectedInstOperands,
33782 /* 94638 */ // GIR_Coverage, 4149,
33783 /* 94638 */ GIR_EraseRootFromParent_Done,
33784 /* 94639 */ // Label 1776: @94639
33785 /* 94639 */ GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(94746), // Rule ID 4151 //
33786 /* 94644 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33787 /* 94647 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33788 /* 94650 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33789 /* 94653 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33790 /* 94656 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33791 /* 94659 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33792 /* 94662 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33793 /* 94665 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
33794 /* 94668 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
33795 /* 94671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33796 /* 94675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33797 /* 94679 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33798 /* 94683 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33799 /* 94687 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33800 /* 94691 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33801 /* 94695 */ // MIs[1] Operand 1
33802 /* 94695 */ // No operand predicates
33803 /* 94695 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33804 /* 94699 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33805 /* 94703 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33806 /* 94707 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
33807 /* 94711 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
33808 /* 94715 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33809 /* 94717 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33810 /* 94717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th),
33811 /* 94720 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33812 /* 94722 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
33813 /* 94724 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
33814 /* 94726 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33815 /* 94729 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33816 /* 94732 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33817 /* 94738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33818 /* 94744 */ GIR_RootConstrainSelectedInstOperands,
33819 /* 94745 */ // GIR_Coverage, 4151,
33820 /* 94745 */ GIR_EraseRootFromParent_Done,
33821 /* 94746 */ // Label 1777: @94746
33822 /* 94746 */ GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(94853), // Rule ID 4153 //
33823 /* 94751 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33824 /* 94754 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33825 /* 94757 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33826 /* 94760 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33827 /* 94763 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33828 /* 94766 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33829 /* 94769 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33830 /* 94772 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
33831 /* 94775 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
33832 /* 94778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33833 /* 94782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33834 /* 94786 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33835 /* 94790 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33836 /* 94794 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33837 /* 94798 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
33838 /* 94802 */ // MIs[1] Operand 1
33839 /* 94802 */ // No operand predicates
33840 /* 94802 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33841 /* 94806 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33842 /* 94810 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33843 /* 94814 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
33844 /* 94818 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
33845 /* 94822 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33846 /* 94824 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33847 /* 94824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh),
33848 /* 94827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33849 /* 94829 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
33850 /* 94831 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
33851 /* 94833 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33852 /* 94836 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33853 /* 94839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33854 /* 94845 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33855 /* 94851 */ GIR_RootConstrainSelectedInstOperands,
33856 /* 94852 */ // GIR_Coverage, 4153,
33857 /* 94852 */ GIR_EraseRootFromParent_Done,
33858 /* 94853 */ // Label 1778: @94853
33859 /* 94853 */ GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(94960), // Rule ID 4155 //
33860 /* 94858 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33861 /* 94861 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33862 /* 94864 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33863 /* 94867 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33864 /* 94870 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33865 /* 94873 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33866 /* 94876 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33867 /* 94879 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
33868 /* 94882 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
33869 /* 94885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33870 /* 94889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33871 /* 94893 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33872 /* 94897 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33873 /* 94901 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33874 /* 94905 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
33875 /* 94909 */ // MIs[1] Operand 1
33876 /* 94909 */ // No operand predicates
33877 /* 94909 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33878 /* 94913 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33879 /* 94917 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33880 /* 94921 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
33881 /* 94925 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
33882 /* 94929 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33883 /* 94931 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33884 /* 94931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th),
33885 /* 94934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33886 /* 94936 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
33887 /* 94938 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
33888 /* 94940 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33889 /* 94943 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33890 /* 94946 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33891 /* 94952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33892 /* 94958 */ GIR_RootConstrainSelectedInstOperands,
33893 /* 94959 */ // GIR_Coverage, 4155,
33894 /* 94959 */ GIR_EraseRootFromParent_Done,
33895 /* 94960 */ // Label 1779: @94960
33896 /* 94960 */ GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(95067), // Rule ID 4157 //
33897 /* 94965 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33898 /* 94968 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33899 /* 94971 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33900 /* 94974 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33901 /* 94977 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33902 /* 94980 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33903 /* 94983 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33904 /* 94986 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
33905 /* 94989 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
33906 /* 94992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33907 /* 94996 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33908 /* 95000 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33909 /* 95004 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33910 /* 95008 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33911 /* 95012 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33912 /* 95016 */ // MIs[1] Operand 1
33913 /* 95016 */ // No operand predicates
33914 /* 95016 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33915 /* 95020 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33916 /* 95024 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33917 /* 95028 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33918 /* 95032 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
33919 /* 95036 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33920 /* 95038 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33921 /* 95038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh),
33922 /* 95041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33923 /* 95043 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
33924 /* 95045 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
33925 /* 95047 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33926 /* 95050 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33927 /* 95053 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33928 /* 95059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33929 /* 95065 */ GIR_RootConstrainSelectedInstOperands,
33930 /* 95066 */ // GIR_Coverage, 4157,
33931 /* 95066 */ GIR_EraseRootFromParent_Done,
33932 /* 95067 */ // Label 1780: @95067
33933 /* 95067 */ GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(95174), // Rule ID 4159 //
33934 /* 95072 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33935 /* 95075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33936 /* 95078 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33937 /* 95081 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33938 /* 95084 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33939 /* 95087 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33940 /* 95090 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33941 /* 95093 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
33942 /* 95096 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
33943 /* 95099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33944 /* 95103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33945 /* 95107 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33946 /* 95111 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33947 /* 95115 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33948 /* 95119 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33949 /* 95123 */ // MIs[1] Operand 1
33950 /* 95123 */ // No operand predicates
33951 /* 95123 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33952 /* 95127 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33953 /* 95131 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33954 /* 95135 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33955 /* 95139 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
33956 /* 95143 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33957 /* 95145 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33958 /* 95145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th),
33959 /* 95148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33960 /* 95150 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
33961 /* 95152 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
33962 /* 95154 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33963 /* 95157 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33964 /* 95160 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33965 /* 95166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33966 /* 95172 */ GIR_RootConstrainSelectedInstOperands,
33967 /* 95173 */ // GIR_Coverage, 4159,
33968 /* 95173 */ GIR_EraseRootFromParent_Done,
33969 /* 95174 */ // Label 1781: @95174
33970 /* 95174 */ GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(95281), // Rule ID 4161 //
33971 /* 95179 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33972 /* 95182 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33973 /* 95185 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33974 /* 95188 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33975 /* 95191 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33976 /* 95194 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33977 /* 95197 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33978 /* 95200 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
33979 /* 95203 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
33980 /* 95206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33981 /* 95210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33982 /* 95214 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33983 /* 95218 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33984 /* 95222 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33985 /* 95226 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
33986 /* 95230 */ // MIs[1] Operand 1
33987 /* 95230 */ // No operand predicates
33988 /* 95230 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33989 /* 95234 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33990 /* 95238 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33991 /* 95242 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33992 /* 95246 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
33993 /* 95250 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33994 /* 95252 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
33995 /* 95252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh),
33996 /* 95255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33997 /* 95257 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
33998 /* 95259 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
33999 /* 95261 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34000 /* 95264 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34001 /* 95267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34002 /* 95273 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34003 /* 95279 */ GIR_RootConstrainSelectedInstOperands,
34004 /* 95280 */ // GIR_Coverage, 4161,
34005 /* 95280 */ GIR_EraseRootFromParent_Done,
34006 /* 95281 */ // Label 1782: @95281
34007 /* 95281 */ GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(95388), // Rule ID 4163 //
34008 /* 95286 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34009 /* 95289 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34010 /* 95292 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34011 /* 95295 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34012 /* 95298 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34013 /* 95301 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34014 /* 95304 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34015 /* 95307 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34016 /* 95310 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34017 /* 95313 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34018 /* 95317 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34019 /* 95321 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34020 /* 95325 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34021 /* 95329 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34022 /* 95333 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34023 /* 95337 */ // MIs[1] Operand 1
34024 /* 95337 */ // No operand predicates
34025 /* 95337 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34026 /* 95341 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34027 /* 95345 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34028 /* 95349 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34029 /* 95353 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34030 /* 95357 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34031 /* 95359 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34032 /* 95359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th),
34033 /* 95362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34034 /* 95364 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34035 /* 95366 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34036 /* 95368 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34037 /* 95371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34038 /* 95374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34039 /* 95380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34040 /* 95386 */ GIR_RootConstrainSelectedInstOperands,
34041 /* 95387 */ // GIR_Coverage, 4163,
34042 /* 95387 */ GIR_EraseRootFromParent_Done,
34043 /* 95388 */ // Label 1783: @95388
34044 /* 95388 */ GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(95495), // Rule ID 4165 //
34045 /* 95393 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34046 /* 95396 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34047 /* 95399 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34048 /* 95402 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34049 /* 95405 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34050 /* 95408 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34051 /* 95411 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34052 /* 95414 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34053 /* 95417 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34054 /* 95420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34055 /* 95424 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34056 /* 95428 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34057 /* 95432 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34058 /* 95436 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34059 /* 95440 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34060 /* 95444 */ // MIs[1] Operand 1
34061 /* 95444 */ // No operand predicates
34062 /* 95444 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34063 /* 95448 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34064 /* 95452 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34065 /* 95456 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34066 /* 95460 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34067 /* 95464 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34068 /* 95466 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34069 /* 95466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh),
34070 /* 95469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34071 /* 95471 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34072 /* 95473 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34073 /* 95475 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34074 /* 95478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34075 /* 95481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34076 /* 95487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34077 /* 95493 */ GIR_RootConstrainSelectedInstOperands,
34078 /* 95494 */ // GIR_Coverage, 4165,
34079 /* 95494 */ GIR_EraseRootFromParent_Done,
34080 /* 95495 */ // Label 1784: @95495
34081 /* 95495 */ GIM_Try, /*On fail goto*//*Label 1785*/ GIMT_Encode4(95602), // Rule ID 4167 //
34082 /* 95500 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34083 /* 95503 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34084 /* 95506 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34085 /* 95509 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34086 /* 95512 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34087 /* 95515 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34088 /* 95518 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34089 /* 95521 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34090 /* 95524 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34091 /* 95527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34092 /* 95531 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34093 /* 95535 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34094 /* 95539 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34095 /* 95543 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34096 /* 95547 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34097 /* 95551 */ // MIs[1] Operand 1
34098 /* 95551 */ // No operand predicates
34099 /* 95551 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34100 /* 95555 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34101 /* 95559 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34102 /* 95563 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34103 /* 95567 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34104 /* 95571 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34105 /* 95573 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34106 /* 95573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th),
34107 /* 95576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34108 /* 95578 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34109 /* 95580 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34110 /* 95582 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34111 /* 95585 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34112 /* 95588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34113 /* 95594 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34114 /* 95600 */ GIR_RootConstrainSelectedInstOperands,
34115 /* 95601 */ // GIR_Coverage, 4167,
34116 /* 95601 */ GIR_EraseRootFromParent_Done,
34117 /* 95602 */ // Label 1785: @95602
34118 /* 95602 */ GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(95709), // Rule ID 4169 //
34119 /* 95607 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34120 /* 95610 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34121 /* 95613 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34122 /* 95616 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34123 /* 95619 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34124 /* 95622 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34125 /* 95625 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34126 /* 95628 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34127 /* 95631 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34128 /* 95634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34129 /* 95638 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34130 /* 95642 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34131 /* 95646 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34132 /* 95650 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34133 /* 95654 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34134 /* 95658 */ // MIs[1] Operand 1
34135 /* 95658 */ // No operand predicates
34136 /* 95658 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34137 /* 95662 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34138 /* 95666 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34139 /* 95670 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34140 /* 95674 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34141 /* 95678 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34142 /* 95680 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34143 /* 95680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh),
34144 /* 95683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34145 /* 95685 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34146 /* 95687 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34147 /* 95689 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34148 /* 95692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34149 /* 95695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34150 /* 95701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34151 /* 95707 */ GIR_RootConstrainSelectedInstOperands,
34152 /* 95708 */ // GIR_Coverage, 4169,
34153 /* 95708 */ GIR_EraseRootFromParent_Done,
34154 /* 95709 */ // Label 1786: @95709
34155 /* 95709 */ GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(95816), // Rule ID 4171 //
34156 /* 95714 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34157 /* 95717 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34158 /* 95720 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34159 /* 95723 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34160 /* 95726 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34161 /* 95729 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34162 /* 95732 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34163 /* 95735 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34164 /* 95738 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34165 /* 95741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34166 /* 95745 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34167 /* 95749 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34168 /* 95753 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34169 /* 95757 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34170 /* 95761 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34171 /* 95765 */ // MIs[1] Operand 1
34172 /* 95765 */ // No operand predicates
34173 /* 95765 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34174 /* 95769 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34175 /* 95773 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34176 /* 95777 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34177 /* 95781 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34178 /* 95785 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34179 /* 95787 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34180 /* 95787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th),
34181 /* 95790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34182 /* 95792 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34183 /* 95794 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34184 /* 95796 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34185 /* 95799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34186 /* 95802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34187 /* 95808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34188 /* 95814 */ GIR_RootConstrainSelectedInstOperands,
34189 /* 95815 */ // GIR_Coverage, 4171,
34190 /* 95815 */ GIR_EraseRootFromParent_Done,
34191 /* 95816 */ // Label 1787: @95816
34192 /* 95816 */ GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(95923), // Rule ID 4173 //
34193 /* 95821 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34194 /* 95824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34195 /* 95827 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34196 /* 95830 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34197 /* 95833 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34198 /* 95836 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34199 /* 95839 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34200 /* 95842 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34201 /* 95845 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34202 /* 95848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34203 /* 95852 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34204 /* 95856 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34205 /* 95860 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34206 /* 95864 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34207 /* 95868 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34208 /* 95872 */ // MIs[1] Operand 1
34209 /* 95872 */ // No operand predicates
34210 /* 95872 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34211 /* 95876 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34212 /* 95880 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34213 /* 95884 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34214 /* 95888 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34215 /* 95892 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34216 /* 95894 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34217 /* 95894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs16),
34218 /* 95897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34219 /* 95899 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34220 /* 95901 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34221 /* 95903 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34222 /* 95906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34223 /* 95909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34224 /* 95915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34225 /* 95921 */ GIR_RootConstrainSelectedInstOperands,
34226 /* 95922 */ // GIR_Coverage, 4173,
34227 /* 95922 */ GIR_EraseRootFromParent_Done,
34228 /* 95923 */ // Label 1788: @95923
34229 /* 95923 */ GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(96030), // Rule ID 4175 //
34230 /* 95928 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34231 /* 95931 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34232 /* 95934 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34233 /* 95937 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34234 /* 95940 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34235 /* 95943 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34236 /* 95946 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34237 /* 95949 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34238 /* 95952 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34239 /* 95955 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34240 /* 95959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34241 /* 95963 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34242 /* 95967 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34243 /* 95971 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34244 /* 95975 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34245 /* 95979 */ // MIs[1] Operand 1
34246 /* 95979 */ // No operand predicates
34247 /* 95979 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34248 /* 95983 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34249 /* 95987 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34250 /* 95991 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34251 /* 95995 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34252 /* 95999 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34253 /* 96001 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34254 /* 96001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths16),
34255 /* 96004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34256 /* 96006 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34257 /* 96008 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34258 /* 96010 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34259 /* 96013 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34260 /* 96016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34261 /* 96022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34262 /* 96028 */ GIR_RootConstrainSelectedInstOperands,
34263 /* 96029 */ // GIR_Coverage, 4175,
34264 /* 96029 */ GIR_EraseRootFromParent_Done,
34265 /* 96030 */ // Label 1789: @96030
34266 /* 96030 */ GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(96137), // Rule ID 4177 //
34267 /* 96035 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34268 /* 96038 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34269 /* 96041 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34270 /* 96044 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34271 /* 96047 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34272 /* 96050 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34273 /* 96053 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34274 /* 96056 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34275 /* 96059 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34276 /* 96062 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34277 /* 96066 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34278 /* 96070 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34279 /* 96074 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34280 /* 96078 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34281 /* 96082 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34282 /* 96086 */ // MIs[1] Operand 1
34283 /* 96086 */ // No operand predicates
34284 /* 96086 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34285 /* 96090 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34286 /* 96094 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34287 /* 96098 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34288 /* 96102 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34289 /* 96106 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34290 /* 96108 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34291 /* 96108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs32),
34292 /* 96111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34293 /* 96113 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34294 /* 96115 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34295 /* 96117 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34296 /* 96120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34297 /* 96123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34298 /* 96129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34299 /* 96135 */ GIR_RootConstrainSelectedInstOperands,
34300 /* 96136 */ // GIR_Coverage, 4177,
34301 /* 96136 */ GIR_EraseRootFromParent_Done,
34302 /* 96137 */ // Label 1790: @96137
34303 /* 96137 */ GIM_Try, /*On fail goto*//*Label 1791*/ GIMT_Encode4(96244), // Rule ID 4179 //
34304 /* 96142 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34305 /* 96145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34306 /* 96148 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34307 /* 96151 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34308 /* 96154 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34309 /* 96157 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34310 /* 96160 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34311 /* 96163 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34312 /* 96166 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34313 /* 96169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34314 /* 96173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34315 /* 96177 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34316 /* 96181 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34317 /* 96185 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34318 /* 96189 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34319 /* 96193 */ // MIs[1] Operand 1
34320 /* 96193 */ // No operand predicates
34321 /* 96193 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34322 /* 96197 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34323 /* 96201 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34324 /* 96205 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34325 /* 96209 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34326 /* 96213 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34327 /* 96215 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34328 /* 96215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths32),
34329 /* 96218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34330 /* 96220 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34331 /* 96222 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34332 /* 96224 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34333 /* 96227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34334 /* 96230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34335 /* 96236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34336 /* 96242 */ GIR_RootConstrainSelectedInstOperands,
34337 /* 96243 */ // GIR_Coverage, 4179,
34338 /* 96243 */ GIR_EraseRootFromParent_Done,
34339 /* 96244 */ // Label 1791: @96244
34340 /* 96244 */ GIM_Try, /*On fail goto*//*Label 1792*/ GIMT_Encode4(96351), // Rule ID 4181 //
34341 /* 96249 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34342 /* 96252 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34343 /* 96255 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34344 /* 96258 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34345 /* 96261 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34346 /* 96264 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34347 /* 96267 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34348 /* 96270 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34349 /* 96273 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34350 /* 96276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34351 /* 96280 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34352 /* 96284 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34353 /* 96288 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34354 /* 96292 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34355 /* 96296 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34356 /* 96300 */ // MIs[1] Operand 1
34357 /* 96300 */ // No operand predicates
34358 /* 96300 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34359 /* 96304 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34360 /* 96308 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34361 /* 96312 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34362 /* 96316 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34363 /* 96320 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34364 /* 96322 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34365 /* 96322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu16),
34366 /* 96325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34367 /* 96327 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34368 /* 96329 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34369 /* 96331 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34370 /* 96334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34371 /* 96337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34372 /* 96343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34373 /* 96349 */ GIR_RootConstrainSelectedInstOperands,
34374 /* 96350 */ // GIR_Coverage, 4181,
34375 /* 96350 */ GIR_EraseRootFromParent_Done,
34376 /* 96351 */ // Label 1792: @96351
34377 /* 96351 */ GIM_Try, /*On fail goto*//*Label 1793*/ GIMT_Encode4(96458), // Rule ID 4183 //
34378 /* 96356 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34379 /* 96359 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34380 /* 96362 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34381 /* 96365 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34382 /* 96368 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34383 /* 96371 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34384 /* 96374 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34385 /* 96377 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34386 /* 96380 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34387 /* 96383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34388 /* 96387 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34389 /* 96391 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34390 /* 96395 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34391 /* 96399 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34392 /* 96403 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34393 /* 96407 */ // MIs[1] Operand 1
34394 /* 96407 */ // No operand predicates
34395 /* 96407 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34396 /* 96411 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34397 /* 96415 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34398 /* 96419 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34399 /* 96423 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34400 /* 96427 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34401 /* 96429 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34402 /* 96429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu16),
34403 /* 96432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34404 /* 96434 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34405 /* 96436 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34406 /* 96438 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34407 /* 96441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34408 /* 96444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34409 /* 96450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34410 /* 96456 */ GIR_RootConstrainSelectedInstOperands,
34411 /* 96457 */ // GIR_Coverage, 4183,
34412 /* 96457 */ GIR_EraseRootFromParent_Done,
34413 /* 96458 */ // Label 1793: @96458
34414 /* 96458 */ GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(96565), // Rule ID 4185 //
34415 /* 96463 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34416 /* 96466 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34417 /* 96469 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34418 /* 96472 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34419 /* 96475 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34420 /* 96478 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34421 /* 96481 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34422 /* 96484 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34423 /* 96487 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34424 /* 96490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34425 /* 96494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34426 /* 96498 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34427 /* 96502 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34428 /* 96506 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34429 /* 96510 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34430 /* 96514 */ // MIs[1] Operand 1
34431 /* 96514 */ // No operand predicates
34432 /* 96514 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34433 /* 96518 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34434 /* 96522 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34435 /* 96526 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34436 /* 96530 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34437 /* 96534 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34438 /* 96536 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34439 /* 96536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu32),
34440 /* 96539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34441 /* 96541 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34442 /* 96543 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34443 /* 96545 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34444 /* 96548 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34445 /* 96551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34446 /* 96557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34447 /* 96563 */ GIR_RootConstrainSelectedInstOperands,
34448 /* 96564 */ // GIR_Coverage, 4185,
34449 /* 96564 */ GIR_EraseRootFromParent_Done,
34450 /* 96565 */ // Label 1794: @96565
34451 /* 96565 */ GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(96672), // Rule ID 4187 //
34452 /* 96570 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34453 /* 96573 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34454 /* 96576 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34455 /* 96579 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34456 /* 96582 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34457 /* 96585 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34458 /* 96588 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34459 /* 96591 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34460 /* 96594 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34461 /* 96597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34462 /* 96601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34463 /* 96605 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34464 /* 96609 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34465 /* 96613 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34466 /* 96617 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34467 /* 96621 */ // MIs[1] Operand 1
34468 /* 96621 */ // No operand predicates
34469 /* 96621 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34470 /* 96625 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34471 /* 96629 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34472 /* 96633 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34473 /* 96637 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34474 /* 96641 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34475 /* 96643 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34476 /* 96643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu32),
34477 /* 96646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34478 /* 96648 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34479 /* 96650 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34480 /* 96652 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34481 /* 96655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34482 /* 96658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34483 /* 96664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34484 /* 96670 */ GIR_RootConstrainSelectedInstOperands,
34485 /* 96671 */ // GIR_Coverage, 4187,
34486 /* 96671 */ GIR_EraseRootFromParent_Done,
34487 /* 96672 */ // Label 1795: @96672
34488 /* 96672 */ GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(96779), // Rule ID 4189 //
34489 /* 96677 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34490 /* 96680 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34491 /* 96683 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34492 /* 96686 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34493 /* 96689 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34494 /* 96692 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34495 /* 96695 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34496 /* 96698 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34497 /* 96701 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34498 /* 96704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34499 /* 96708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34500 /* 96712 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34501 /* 96716 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34502 /* 96720 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34503 /* 96724 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34504 /* 96728 */ // MIs[1] Operand 1
34505 /* 96728 */ // No operand predicates
34506 /* 96728 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34507 /* 96732 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34508 /* 96736 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34509 /* 96740 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34510 /* 96744 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34511 /* 96748 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34512 /* 96750 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34513 /* 96750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs16),
34514 /* 96753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34515 /* 96755 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34516 /* 96757 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34517 /* 96759 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34518 /* 96762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34519 /* 96765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34520 /* 96771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34521 /* 96777 */ GIR_RootConstrainSelectedInstOperands,
34522 /* 96778 */ // GIR_Coverage, 4189,
34523 /* 96778 */ GIR_EraseRootFromParent_Done,
34524 /* 96779 */ // Label 1796: @96779
34525 /* 96779 */ GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(96886), // Rule ID 4191 //
34526 /* 96784 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34527 /* 96787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34528 /* 96790 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34529 /* 96793 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34530 /* 96796 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34531 /* 96799 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34532 /* 96802 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34533 /* 96805 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34534 /* 96808 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34535 /* 96811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34536 /* 96815 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34537 /* 96819 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34538 /* 96823 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34539 /* 96827 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34540 /* 96831 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34541 /* 96835 */ // MIs[1] Operand 1
34542 /* 96835 */ // No operand predicates
34543 /* 96835 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34544 /* 96839 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34545 /* 96843 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34546 /* 96847 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34547 /* 96851 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34548 /* 96855 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34549 /* 96857 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34550 /* 96857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths16),
34551 /* 96860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34552 /* 96862 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34553 /* 96864 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34554 /* 96866 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34555 /* 96869 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34556 /* 96872 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34557 /* 96878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34558 /* 96884 */ GIR_RootConstrainSelectedInstOperands,
34559 /* 96885 */ // GIR_Coverage, 4191,
34560 /* 96885 */ GIR_EraseRootFromParent_Done,
34561 /* 96886 */ // Label 1797: @96886
34562 /* 96886 */ GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(96993), // Rule ID 4193 //
34563 /* 96891 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34564 /* 96894 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34565 /* 96897 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34566 /* 96900 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34567 /* 96903 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34568 /* 96906 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34569 /* 96909 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34570 /* 96912 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34571 /* 96915 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34572 /* 96918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34573 /* 96922 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34574 /* 96926 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34575 /* 96930 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34576 /* 96934 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34577 /* 96938 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34578 /* 96942 */ // MIs[1] Operand 1
34579 /* 96942 */ // No operand predicates
34580 /* 96942 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34581 /* 96946 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34582 /* 96950 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34583 /* 96954 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34584 /* 96958 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34585 /* 96962 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34586 /* 96964 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34587 /* 96964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs32),
34588 /* 96967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34589 /* 96969 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34590 /* 96971 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34591 /* 96973 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34592 /* 96976 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34593 /* 96979 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34594 /* 96985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34595 /* 96991 */ GIR_RootConstrainSelectedInstOperands,
34596 /* 96992 */ // GIR_Coverage, 4193,
34597 /* 96992 */ GIR_EraseRootFromParent_Done,
34598 /* 96993 */ // Label 1798: @96993
34599 /* 96993 */ GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(97100), // Rule ID 4195 //
34600 /* 96998 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34601 /* 97001 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34602 /* 97004 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34603 /* 97007 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34604 /* 97010 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34605 /* 97013 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34606 /* 97016 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34607 /* 97019 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34608 /* 97022 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34609 /* 97025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34610 /* 97029 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34611 /* 97033 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34612 /* 97037 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34613 /* 97041 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34614 /* 97045 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34615 /* 97049 */ // MIs[1] Operand 1
34616 /* 97049 */ // No operand predicates
34617 /* 97049 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34618 /* 97053 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34619 /* 97057 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34620 /* 97061 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34621 /* 97065 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34622 /* 97069 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34623 /* 97071 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34624 /* 97071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths32),
34625 /* 97074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34626 /* 97076 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34627 /* 97078 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34628 /* 97080 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34629 /* 97083 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34630 /* 97086 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34631 /* 97092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34632 /* 97098 */ GIR_RootConstrainSelectedInstOperands,
34633 /* 97099 */ // GIR_Coverage, 4195,
34634 /* 97099 */ GIR_EraseRootFromParent_Done,
34635 /* 97100 */ // Label 1799: @97100
34636 /* 97100 */ GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(97207), // Rule ID 4197 //
34637 /* 97105 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34638 /* 97108 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34639 /* 97111 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34640 /* 97114 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34641 /* 97117 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34642 /* 97120 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34643 /* 97123 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34644 /* 97126 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34645 /* 97129 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34646 /* 97132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34647 /* 97136 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34648 /* 97140 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34649 /* 97144 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34650 /* 97148 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34651 /* 97152 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34652 /* 97156 */ // MIs[1] Operand 1
34653 /* 97156 */ // No operand predicates
34654 /* 97156 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34655 /* 97160 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34656 /* 97164 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34657 /* 97168 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34658 /* 97172 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34659 /* 97176 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34660 /* 97178 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34661 /* 97178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu16),
34662 /* 97181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34663 /* 97183 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34664 /* 97185 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34665 /* 97187 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34666 /* 97190 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34667 /* 97193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34668 /* 97199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34669 /* 97205 */ GIR_RootConstrainSelectedInstOperands,
34670 /* 97206 */ // GIR_Coverage, 4197,
34671 /* 97206 */ GIR_EraseRootFromParent_Done,
34672 /* 97207 */ // Label 1800: @97207
34673 /* 97207 */ GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(97314), // Rule ID 4199 //
34674 /* 97212 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34675 /* 97215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34676 /* 97218 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34677 /* 97221 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34678 /* 97224 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34679 /* 97227 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34680 /* 97230 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34681 /* 97233 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34682 /* 97236 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34683 /* 97239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34684 /* 97243 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34685 /* 97247 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34686 /* 97251 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34687 /* 97255 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34688 /* 97259 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34689 /* 97263 */ // MIs[1] Operand 1
34690 /* 97263 */ // No operand predicates
34691 /* 97263 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34692 /* 97267 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34693 /* 97271 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34694 /* 97275 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34695 /* 97279 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34696 /* 97283 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34697 /* 97285 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34698 /* 97285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu16),
34699 /* 97288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34700 /* 97290 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34701 /* 97292 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34702 /* 97294 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34703 /* 97297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34704 /* 97300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34705 /* 97306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34706 /* 97312 */ GIR_RootConstrainSelectedInstOperands,
34707 /* 97313 */ // GIR_Coverage, 4199,
34708 /* 97313 */ GIR_EraseRootFromParent_Done,
34709 /* 97314 */ // Label 1801: @97314
34710 /* 97314 */ GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(97421), // Rule ID 4201 //
34711 /* 97319 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34712 /* 97322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34713 /* 97325 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34714 /* 97328 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34715 /* 97331 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34716 /* 97334 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34717 /* 97337 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34718 /* 97340 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34719 /* 97343 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34720 /* 97346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34721 /* 97350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34722 /* 97354 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34723 /* 97358 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34724 /* 97362 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34725 /* 97366 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34726 /* 97370 */ // MIs[1] Operand 1
34727 /* 97370 */ // No operand predicates
34728 /* 97370 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34729 /* 97374 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34730 /* 97378 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34731 /* 97382 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34732 /* 97386 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34733 /* 97390 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34734 /* 97392 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34735 /* 97392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu32),
34736 /* 97395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34737 /* 97397 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34738 /* 97399 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34739 /* 97401 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34740 /* 97404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34741 /* 97407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34742 /* 97413 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34743 /* 97419 */ GIR_RootConstrainSelectedInstOperands,
34744 /* 97420 */ // GIR_Coverage, 4201,
34745 /* 97420 */ GIR_EraseRootFromParent_Done,
34746 /* 97421 */ // Label 1802: @97421
34747 /* 97421 */ GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(97528), // Rule ID 4203 //
34748 /* 97426 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34749 /* 97429 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34750 /* 97432 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34751 /* 97435 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34752 /* 97438 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34753 /* 97441 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34754 /* 97444 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34755 /* 97447 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34756 /* 97450 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34757 /* 97453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34758 /* 97457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34759 /* 97461 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34760 /* 97465 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34761 /* 97469 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34762 /* 97473 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34763 /* 97477 */ // MIs[1] Operand 1
34764 /* 97477 */ // No operand predicates
34765 /* 97477 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34766 /* 97481 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34767 /* 97485 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34768 /* 97489 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34769 /* 97493 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34770 /* 97497 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34771 /* 97499 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34772 /* 97499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu32),
34773 /* 97502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34774 /* 97504 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34775 /* 97506 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34776 /* 97508 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34777 /* 97511 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34778 /* 97514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34779 /* 97520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34780 /* 97526 */ GIR_RootConstrainSelectedInstOperands,
34781 /* 97527 */ // GIR_Coverage, 4203,
34782 /* 97527 */ GIR_EraseRootFromParent_Done,
34783 /* 97528 */ // Label 1803: @97528
34784 /* 97528 */ GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(97635), // Rule ID 4205 //
34785 /* 97533 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34786 /* 97536 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34787 /* 97539 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34788 /* 97542 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34789 /* 97545 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34790 /* 97548 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34791 /* 97551 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34792 /* 97554 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34793 /* 97557 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34794 /* 97560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34795 /* 97564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34796 /* 97568 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34797 /* 97572 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34798 /* 97576 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34799 /* 97580 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34800 /* 97584 */ // MIs[1] Operand 1
34801 /* 97584 */ // No operand predicates
34802 /* 97584 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34803 /* 97588 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34804 /* 97592 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34805 /* 97596 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34806 /* 97600 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34807 /* 97604 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34808 /* 97606 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34809 /* 97606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16bh),
34810 /* 97609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34811 /* 97611 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34812 /* 97613 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34813 /* 97615 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34814 /* 97618 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34815 /* 97621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34816 /* 97627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34817 /* 97633 */ GIR_RootConstrainSelectedInstOperands,
34818 /* 97634 */ // GIR_Coverage, 4205,
34819 /* 97634 */ GIR_EraseRootFromParent_Done,
34820 /* 97635 */ // Label 1804: @97635
34821 /* 97635 */ GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(97742), // Rule ID 4207 //
34822 /* 97640 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34823 /* 97643 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34824 /* 97646 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34825 /* 97649 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34826 /* 97652 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34827 /* 97655 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34828 /* 97658 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34829 /* 97661 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34830 /* 97664 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34831 /* 97667 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34832 /* 97671 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34833 /* 97675 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34834 /* 97679 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34835 /* 97683 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34836 /* 97687 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34837 /* 97691 */ // MIs[1] Operand 1
34838 /* 97691 */ // No operand predicates
34839 /* 97691 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34840 /* 97695 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34841 /* 97699 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34842 /* 97703 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34843 /* 97707 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34844 /* 97711 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34845 /* 97713 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34846 /* 97713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16th),
34847 /* 97716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34848 /* 97718 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34849 /* 97720 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34850 /* 97722 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34851 /* 97725 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34852 /* 97728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34853 /* 97734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34854 /* 97740 */ GIR_RootConstrainSelectedInstOperands,
34855 /* 97741 */ // GIR_Coverage, 4207,
34856 /* 97741 */ GIR_EraseRootFromParent_Done,
34857 /* 97742 */ // Label 1805: @97742
34858 /* 97742 */ GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(97849), // Rule ID 4209 //
34859 /* 97747 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34860 /* 97750 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34861 /* 97753 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34862 /* 97756 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34863 /* 97759 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34864 /* 97762 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34865 /* 97765 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34866 /* 97768 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34867 /* 97771 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34868 /* 97774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34869 /* 97778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34870 /* 97782 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34871 /* 97786 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34872 /* 97790 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34873 /* 97794 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34874 /* 97798 */ // MIs[1] Operand 1
34875 /* 97798 */ // No operand predicates
34876 /* 97798 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34877 /* 97802 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34878 /* 97806 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34879 /* 97810 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34880 /* 97814 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34881 /* 97818 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34882 /* 97820 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34883 /* 97820 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32bh),
34884 /* 97823 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34885 /* 97825 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34886 /* 97827 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34887 /* 97829 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34888 /* 97832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34889 /* 97835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34890 /* 97841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34891 /* 97847 */ GIR_RootConstrainSelectedInstOperands,
34892 /* 97848 */ // GIR_Coverage, 4209,
34893 /* 97848 */ GIR_EraseRootFromParent_Done,
34894 /* 97849 */ // Label 1806: @97849
34895 /* 97849 */ GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(97956), // Rule ID 4211 //
34896 /* 97854 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34897 /* 97857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34898 /* 97860 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34899 /* 97863 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34900 /* 97866 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34901 /* 97869 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34902 /* 97872 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34903 /* 97875 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34904 /* 97878 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34905 /* 97881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34906 /* 97885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34907 /* 97889 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34908 /* 97893 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34909 /* 97897 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34910 /* 97901 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34911 /* 97905 */ // MIs[1] Operand 1
34912 /* 97905 */ // No operand predicates
34913 /* 97905 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34914 /* 97909 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34915 /* 97913 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34916 /* 97917 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34917 /* 97921 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34918 /* 97925 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34919 /* 97927 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34920 /* 97927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32th),
34921 /* 97930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34922 /* 97932 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34923 /* 97934 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34924 /* 97936 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34925 /* 97939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34926 /* 97942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34927 /* 97948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34928 /* 97954 */ GIR_RootConstrainSelectedInstOperands,
34929 /* 97955 */ // GIR_Coverage, 4211,
34930 /* 97955 */ GIR_EraseRootFromParent_Done,
34931 /* 97956 */ // Label 1807: @97956
34932 /* 97956 */ GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(98063), // Rule ID 4213 //
34933 /* 97961 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34934 /* 97964 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34935 /* 97967 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34936 /* 97970 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34937 /* 97973 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34938 /* 97976 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34939 /* 97979 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34940 /* 97982 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34941 /* 97985 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34942 /* 97988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34943 /* 97992 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34944 /* 97996 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34945 /* 98000 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34946 /* 98004 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34947 /* 98008 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34948 /* 98012 */ // MIs[1] Operand 1
34949 /* 98012 */ // No operand predicates
34950 /* 98012 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34951 /* 98016 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34952 /* 98020 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34953 /* 98024 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34954 /* 98028 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34955 /* 98032 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34956 /* 98034 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34957 /* 98034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16bh),
34958 /* 98037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34959 /* 98039 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34960 /* 98041 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34961 /* 98043 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34962 /* 98046 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34963 /* 98049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34964 /* 98055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34965 /* 98061 */ GIR_RootConstrainSelectedInstOperands,
34966 /* 98062 */ // GIR_Coverage, 4213,
34967 /* 98062 */ GIR_EraseRootFromParent_Done,
34968 /* 98063 */ // Label 1808: @98063
34969 /* 98063 */ GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(98170), // Rule ID 4215 //
34970 /* 98068 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34971 /* 98071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34972 /* 98074 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34973 /* 98077 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34974 /* 98080 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34975 /* 98083 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34976 /* 98086 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34977 /* 98089 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34978 /* 98092 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34979 /* 98095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34980 /* 98099 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34981 /* 98103 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34982 /* 98107 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34983 /* 98111 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34984 /* 98115 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34985 /* 98119 */ // MIs[1] Operand 1
34986 /* 98119 */ // No operand predicates
34987 /* 98119 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34988 /* 98123 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34989 /* 98127 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34990 /* 98131 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34991 /* 98135 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34992 /* 98139 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34993 /* 98141 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34994 /* 98141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16th),
34995 /* 98144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34996 /* 98146 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34997 /* 98148 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34998 /* 98150 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34999 /* 98153 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35000 /* 98156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35001 /* 98162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35002 /* 98168 */ GIR_RootConstrainSelectedInstOperands,
35003 /* 98169 */ // GIR_Coverage, 4215,
35004 /* 98169 */ GIR_EraseRootFromParent_Done,
35005 /* 98170 */ // Label 1809: @98170
35006 /* 98170 */ GIM_Try, /*On fail goto*//*Label 1810*/ GIMT_Encode4(98277), // Rule ID 4217 //
35007 /* 98175 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
35008 /* 98178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
35009 /* 98181 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
35010 /* 98184 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
35011 /* 98187 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
35012 /* 98190 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
35013 /* 98193 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
35014 /* 98196 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
35015 /* 98199 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
35016 /* 98202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35017 /* 98206 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35018 /* 98210 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35019 /* 98214 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
35020 /* 98218 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35021 /* 98222 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
35022 /* 98226 */ // MIs[1] Operand 1
35023 /* 98226 */ // No operand predicates
35024 /* 98226 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
35025 /* 98230 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
35026 /* 98234 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
35027 /* 98238 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
35028 /* 98242 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
35029 /* 98246 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35030 /* 98248 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
35031 /* 98248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32bh),
35032 /* 98251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35033 /* 98253 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
35034 /* 98255 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
35035 /* 98257 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35036 /* 98260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35037 /* 98263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35038 /* 98269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35039 /* 98275 */ GIR_RootConstrainSelectedInstOperands,
35040 /* 98276 */ // GIR_Coverage, 4217,
35041 /* 98276 */ GIR_EraseRootFromParent_Done,
35042 /* 98277 */ // Label 1810: @98277
35043 /* 98277 */ GIM_Try, /*On fail goto*//*Label 1811*/ GIMT_Encode4(98384), // Rule ID 4219 //
35044 /* 98282 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
35045 /* 98285 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
35046 /* 98288 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
35047 /* 98291 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
35048 /* 98294 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
35049 /* 98297 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
35050 /* 98300 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
35051 /* 98303 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
35052 /* 98306 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
35053 /* 98309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35054 /* 98313 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35055 /* 98317 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35056 /* 98321 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
35057 /* 98325 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35058 /* 98329 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
35059 /* 98333 */ // MIs[1] Operand 1
35060 /* 98333 */ // No operand predicates
35061 /* 98333 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
35062 /* 98337 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
35063 /* 98341 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
35064 /* 98345 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
35065 /* 98349 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
35066 /* 98353 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35067 /* 98355 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3965:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
35068 /* 98355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32th),
35069 /* 98358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35070 /* 98360 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
35071 /* 98362 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
35072 /* 98364 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35073 /* 98367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35074 /* 98370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35075 /* 98376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35076 /* 98382 */ GIR_RootConstrainSelectedInstOperands,
35077 /* 98383 */ // GIR_Coverage, 4219,
35078 /* 98383 */ GIR_EraseRootFromParent_Done,
35079 /* 98384 */ // Label 1811: @98384
35080 /* 98384 */ GIM_Reject,
35081 /* 98385 */ // Label 1771: @98385
35082 /* 98385 */ GIM_Reject,
35083 /* 98386 */ // Label 22: @98386
35084 /* 98386 */ GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(98443),
35085 /* 98391 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
35086 /* 98394 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_clrex),
35087 /* 98399 */ GIM_Try, /*On fail goto*//*Label 1813*/ GIMT_Encode4(98416), // Rule ID 244 //
35088 /* 98404 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6K_IsARM),
35089 /* 98407 */ // (intrinsic_void 3732:{ *:[iPTR] }) => (CLREX)
35090 /* 98407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLREX),
35091 /* 98410 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35092 /* 98414 */ GIR_RootConstrainSelectedInstOperands,
35093 /* 98415 */ // GIR_Coverage, 244,
35094 /* 98415 */ GIR_EraseRootFromParent_Done,
35095 /* 98416 */ // Label 1813: @98416
35096 /* 98416 */ GIM_Try, /*On fail goto*//*Label 1814*/ GIMT_Encode4(98442), // Rule ID 573 //
35097 /* 98421 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV7Clrex_IsThumb),
35098 /* 98424 */ // (intrinsic_void 3732:{ *:[iPTR] }) => (t2CLREX)
35099 /* 98424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLREX),
35100 /* 98427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35101 /* 98430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35102 /* 98436 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35103 /* 98440 */ GIR_RootConstrainSelectedInstOperands,
35104 /* 98441 */ // GIR_Coverage, 573,
35105 /* 98441 */ GIR_EraseRootFromParent_Done,
35106 /* 98442 */ // Label 1814: @98442
35107 /* 98442 */ GIM_Reject,
35108 /* 98443 */ // Label 1812: @98443
35109 /* 98443 */ GIM_Try, /*On fail goto*//*Label 1815*/ GIMT_Encode4(99245),
35110 /* 98448 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
35111 /* 98451 */ GIM_Try, /*On fail goto*//*Label 1816*/ GIMT_Encode4(98487), // Rule ID 343 //
35112 /* 98456 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsWindows),
35113 /* 98459 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
35114 /* 98464 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35115 /* 98467 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/1, GIMT_Encode8(249),
35116 /* 98478 */ // (intrinsic_void 4186:{ *:[iPTR] }, 249:{ *:[i32] }) => (t__brkdiv0)
35117 /* 98478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t__brkdiv0),
35118 /* 98481 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35119 /* 98485 */ GIR_RootConstrainSelectedInstOperands,
35120 /* 98486 */ // GIR_Coverage, 343,
35121 /* 98486 */ GIR_EraseRootFromParent_Done,
35122 /* 98487 */ // Label 1816: @98487
35123 /* 98487 */ GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(98539), // Rule ID 2 //
35124 /* 98492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
35125 /* 98495 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint),
35126 /* 98500 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35127 /* 98503 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35128 /* 98507 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35129 /* 98511 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239),
35130 /* 98515 */ // MIs[1] Operand 1
35131 /* 98515 */ // No operand predicates
35132 /* 98515 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35133 /* 98517 */ // (intrinsic_void 3750:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (HINT (imm:{ *:[i32] }):$imm)
35134 /* 98517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::HINT),
35135 /* 98520 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35136 /* 98523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35137 /* 98526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35138 /* 98532 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35139 /* 98537 */ GIR_RootConstrainSelectedInstOperands,
35140 /* 98538 */ // GIR_Coverage, 2,
35141 /* 98538 */ GIR_EraseRootFromParent_Done,
35142 /* 98539 */ // Label 1817: @98539
35143 /* 98539 */ GIM_Try, /*On fail goto*//*Label 1818*/ GIMT_Encode4(98591), // Rule ID 10 //
35144 /* 98544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV7_IsARM),
35145 /* 98547 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg),
35146 /* 98552 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35147 /* 98555 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35148 /* 98559 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35149 /* 98563 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35150 /* 98567 */ // MIs[1] Operand 1
35151 /* 98567 */ // No operand predicates
35152 /* 98567 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35153 /* 98569 */ // (intrinsic_void 3745:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DBG (imm:{ *:[i32] }):$opt)
35154 /* 98569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DBG),
35155 /* 98572 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35156 /* 98575 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35157 /* 98578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35158 /* 98584 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35159 /* 98589 */ GIR_RootConstrainSelectedInstOperands,
35160 /* 98590 */ // GIR_Coverage, 10,
35161 /* 98590 */ GIR_EraseRootFromParent_Done,
35162 /* 98591 */ // Label 1818: @98591
35163 /* 98591 */ GIM_Try, /*On fail goto*//*Label 1819*/ GIMT_Encode4(98634), // Rule ID 11 //
35164 /* 98596 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35165 /* 98599 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
35166 /* 98604 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35167 /* 98607 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35168 /* 98611 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35169 /* 98615 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
35170 /* 98619 */ // MIs[1] Operand 1
35171 /* 98619 */ // No operand predicates
35172 /* 98619 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35173 /* 98621 */ // (intrinsic_void 4186:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (UDF (imm:{ *:[i32] }):$imm16)
35174 /* 98621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF),
35175 /* 98624 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
35176 /* 98627 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35177 /* 98632 */ GIR_RootConstrainSelectedInstOperands,
35178 /* 98633 */ // GIR_Coverage, 11,
35179 /* 98633 */ GIR_EraseRootFromParent_Done,
35180 /* 98634 */ // Label 1819: @98634
35181 /* 98634 */ GIM_Try, /*On fail goto*//*Label 1820*/ GIMT_Encode4(98677), // Rule ID 227 //
35182 /* 98639 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM),
35183 /* 98642 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb),
35184 /* 98647 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35185 /* 98650 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35186 /* 98654 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35187 /* 98658 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35188 /* 98662 */ // MIs[1] Operand 1
35189 /* 98662 */ // No operand predicates
35190 /* 98662 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35191 /* 98664 */ // (intrinsic_void 3746:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DMB (imm:{ *:[i32] }):$opt)
35192 /* 98664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DMB),
35193 /* 98667 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35194 /* 98670 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35195 /* 98675 */ GIR_RootConstrainSelectedInstOperands,
35196 /* 98676 */ // GIR_Coverage, 227,
35197 /* 98676 */ GIR_EraseRootFromParent_Done,
35198 /* 98677 */ // Label 1820: @98677
35199 /* 98677 */ GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(98720), // Rule ID 228 //
35200 /* 98682 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM),
35201 /* 98685 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb),
35202 /* 98690 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35203 /* 98693 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35204 /* 98697 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35205 /* 98701 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35206 /* 98705 */ // MIs[1] Operand 1
35207 /* 98705 */ // No operand predicates
35208 /* 98705 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35209 /* 98707 */ // (intrinsic_void 3747:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DSB (imm:{ *:[i32] }):$opt)
35210 /* 98707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DSB),
35211 /* 98710 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35212 /* 98713 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35213 /* 98718 */ GIR_RootConstrainSelectedInstOperands,
35214 /* 98719 */ // GIR_Coverage, 228,
35215 /* 98719 */ GIR_EraseRootFromParent_Done,
35216 /* 98720 */ // Label 1821: @98720
35217 /* 98720 */ GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(98763), // Rule ID 229 //
35218 /* 98725 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM),
35219 /* 98728 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb),
35220 /* 98733 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35221 /* 98736 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35222 /* 98740 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35223 /* 98744 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35224 /* 98748 */ // MIs[1] Operand 1
35225 /* 98748 */ // No operand predicates
35226 /* 98748 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35227 /* 98750 */ // (intrinsic_void 3751:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (ISB (imm:{ *:[i32] }):$opt)
35228 /* 98750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ISB),
35229 /* 98753 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35230 /* 98756 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35231 /* 98761 */ GIR_RootConstrainSelectedInstOperands,
35232 /* 98762 */ // GIR_Coverage, 229,
35233 /* 98762 */ GIR_EraseRootFromParent_Done,
35234 /* 98763 */ // Label 1822: @98763
35235 /* 98763 */ GIM_Try, /*On fail goto*//*Label 1823*/ GIMT_Encode4(98815), // Rule ID 275 //
35236 /* 98768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6M_IsThumb),
35237 /* 98771 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint),
35238 /* 98776 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35239 /* 98779 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35240 /* 98783 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35241 /* 98787 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35242 /* 98791 */ // MIs[1] Operand 1
35243 /* 98791 */ // No operand predicates
35244 /* 98791 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35245 /* 98793 */ // (intrinsic_void 3750:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (tHINT (imm:{ *:[i32] }):$imm)
35246 /* 98793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tHINT),
35247 /* 98796 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35248 /* 98799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35249 /* 98802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35250 /* 98808 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35251 /* 98813 */ GIR_RootConstrainSelectedInstOperands,
35252 /* 98814 */ // GIR_Coverage, 275,
35253 /* 98814 */ GIR_EraseRootFromParent_Done,
35254 /* 98815 */ // Label 1823: @98815
35255 /* 98815 */ GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(98858), // Rule ID 342 //
35256 /* 98820 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb),
35257 /* 98823 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
35258 /* 98828 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35259 /* 98831 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35260 /* 98835 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35261 /* 98839 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255),
35262 /* 98843 */ // MIs[1] Operand 1
35263 /* 98843 */ // No operand predicates
35264 /* 98843 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35265 /* 98845 */ // (intrinsic_void 4186:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$imm8) => (tUDF (imm:{ *:[i32] }):$imm8)
35266 /* 98845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF),
35267 /* 98848 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8
35268 /* 98851 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35269 /* 98856 */ GIR_RootConstrainSelectedInstOperands,
35270 /* 98857 */ // GIR_Coverage, 342,
35271 /* 98857 */ GIR_EraseRootFromParent_Done,
35272 /* 98858 */ // Label 1824: @98858
35273 /* 98858 */ GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(98901), // Rule ID 493 //
35274 /* 98863 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
35275 /* 98866 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
35276 /* 98871 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35277 /* 98874 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35278 /* 98878 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35279 /* 98882 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
35280 /* 98886 */ // MIs[1] Operand 1
35281 /* 98886 */ // No operand predicates
35282 /* 98886 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35283 /* 98888 */ // (intrinsic_void 4186:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (t2UDF (imm:{ *:[i32] }):$imm16)
35284 /* 98888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDF),
35285 /* 98891 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
35286 /* 98894 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35287 /* 98899 */ GIR_RootConstrainSelectedInstOperands,
35288 /* 98900 */ // GIR_Coverage, 493,
35289 /* 98900 */ GIR_EraseRootFromParent_Done,
35290 /* 98901 */ // Label 1825: @98901
35291 /* 98901 */ GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(98953), // Rule ID 558 //
35292 /* 98906 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb),
35293 /* 98909 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb),
35294 /* 98914 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35295 /* 98917 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35296 /* 98921 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35297 /* 98925 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35298 /* 98929 */ // MIs[1] Operand 1
35299 /* 98929 */ // No operand predicates
35300 /* 98929 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35301 /* 98931 */ // (intrinsic_void 3746:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DMB (imm:{ *:[i32] }):$opt)
35302 /* 98931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DMB),
35303 /* 98934 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35304 /* 98937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35305 /* 98940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35306 /* 98946 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35307 /* 98951 */ GIR_RootConstrainSelectedInstOperands,
35308 /* 98952 */ // GIR_Coverage, 558,
35309 /* 98952 */ GIR_EraseRootFromParent_Done,
35310 /* 98953 */ // Label 1826: @98953
35311 /* 98953 */ GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(99005), // Rule ID 559 //
35312 /* 98958 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb),
35313 /* 98961 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb),
35314 /* 98966 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35315 /* 98969 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35316 /* 98973 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35317 /* 98977 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35318 /* 98981 */ // MIs[1] Operand 1
35319 /* 98981 */ // No operand predicates
35320 /* 98981 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35321 /* 98983 */ // (intrinsic_void 3747:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DSB (imm:{ *:[i32] }):$opt)
35322 /* 98983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DSB),
35323 /* 98986 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35324 /* 98989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35325 /* 98992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35326 /* 98998 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35327 /* 99003 */ GIR_RootConstrainSelectedInstOperands,
35328 /* 99004 */ // GIR_Coverage, 559,
35329 /* 99004 */ GIR_EraseRootFromParent_Done,
35330 /* 99005 */ // Label 1827: @99005
35331 /* 99005 */ GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(99057), // Rule ID 560 //
35332 /* 99010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb),
35333 /* 99013 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb),
35334 /* 99018 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35335 /* 99021 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35336 /* 99025 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35337 /* 99029 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35338 /* 99033 */ // MIs[1] Operand 1
35339 /* 99033 */ // No operand predicates
35340 /* 99033 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35341 /* 99035 */ // (intrinsic_void 3751:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2ISB (imm:{ *:[i32] }):$opt)
35342 /* 99035 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ISB),
35343 /* 99038 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35344 /* 99041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35345 /* 99044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35346 /* 99050 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35347 /* 99055 */ GIR_RootConstrainSelectedInstOperands,
35348 /* 99056 */ // GIR_Coverage, 560,
35349 /* 99056 */ GIR_EraseRootFromParent_Done,
35350 /* 99057 */ // Label 1828: @99057
35351 /* 99057 */ GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(99109), // Rule ID 578 //
35352 /* 99062 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
35353 /* 99065 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint),
35354 /* 99070 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35355 /* 99073 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35356 /* 99077 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35357 /* 99081 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239),
35358 /* 99085 */ // MIs[1] Operand 1
35359 /* 99085 */ // No operand predicates
35360 /* 99085 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35361 /* 99087 */ // (intrinsic_void 3750:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (t2HINT (imm:{ *:[i32] }):$imm)
35362 /* 99087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2HINT),
35363 /* 99090 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35364 /* 99093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35365 /* 99096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35366 /* 99102 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35367 /* 99107 */ GIR_RootConstrainSelectedInstOperands,
35368 /* 99108 */ // GIR_Coverage, 578,
35369 /* 99108 */ GIR_EraseRootFromParent_Done,
35370 /* 99109 */ // Label 1829: @99109
35371 /* 99109 */ GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(99161), // Rule ID 579 //
35372 /* 99114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
35373 /* 99117 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg),
35374 /* 99122 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35375 /* 99125 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35376 /* 99129 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35377 /* 99133 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35378 /* 99137 */ // MIs[1] Operand 1
35379 /* 99137 */ // No operand predicates
35380 /* 99137 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35381 /* 99139 */ // (intrinsic_void 3745:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DBG (imm:{ *:[i32] }):$opt)
35382 /* 99139 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DBG),
35383 /* 99142 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35384 /* 99145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35385 /* 99148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35386 /* 99154 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35387 /* 99159 */ GIR_RootConstrainSelectedInstOperands,
35388 /* 99160 */ // GIR_Coverage, 579,
35389 /* 99160 */ GIR_EraseRootFromParent_Done,
35390 /* 99161 */ // Label 1830: @99161
35391 /* 99161 */ GIM_Try, /*On fail goto*//*Label 1831*/ GIMT_Encode4(99201), // Rule ID 845 //
35392 /* 99166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs),
35393 /* 99169 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_get_fpscr),
35394 /* 99174 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35395 /* 99177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35396 /* 99181 */ // (intrinsic_w_chain:{ *:[i32] } 3748:{ *:[iPTR] }) => (VMRS:{ *:[i32] })
35397 /* 99181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS),
35398 /* 99184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
35399 /* 99186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35400 /* 99189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35401 /* 99195 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35402 /* 99199 */ GIR_RootConstrainSelectedInstOperands,
35403 /* 99200 */ // GIR_Coverage, 845,
35404 /* 99200 */ GIR_EraseRootFromParent_Done,
35405 /* 99201 */ // Label 1831: @99201
35406 /* 99201 */ GIM_Try, /*On fail goto*//*Label 1832*/ GIMT_Encode4(99244), // Rule ID 846 //
35407 /* 99206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs),
35408 /* 99209 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_set_fpscr),
35409 /* 99214 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35410 /* 99217 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35411 /* 99221 */ // (intrinsic_void 4130:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt)
35412 /* 99221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
35413 /* 99224 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt
35414 /* 99226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35415 /* 99229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35416 /* 99235 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
35417 /* 99238 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35418 /* 99242 */ GIR_RootConstrainSelectedInstOperands,
35419 /* 99243 */ // GIR_Coverage, 846,
35420 /* 99243 */ GIR_EraseRootFromParent_Done,
35421 /* 99244 */ // Label 1832: @99244
35422 /* 99244 */ GIM_Reject,
35423 /* 99245 */ // Label 1815: @99245
35424 /* 99245 */ GIM_Try, /*On fail goto*//*Label 1833*/ GIMT_Encode4(99288), // Rule ID 603 //
35425 /* 99250 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLOB_HasV8_1MMainline_IsThumb2),
35426 /* 99253 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
35427 /* 99256 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::start_loop_iterations),
35428 /* 99261 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35429 /* 99264 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35430 /* 99267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRlrRegClassID),
35431 /* 99271 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35432 /* 99275 */ // (intrinsic_w_chain:{ *:[i32] } 362:{ *:[iPTR] }, rGPR:{ *:[i32] }:$tc) => (t2DoLoopStart:{ *:[i32] } rGPR:{ *:[i32] }:$tc)
35433 /* 99275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DoLoopStart),
35434 /* 99278 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[X]
35435 /* 99280 */ GIR_RootToRootCopy, /*OpIdx*/2, // tc
35436 /* 99282 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35437 /* 99286 */ GIR_RootConstrainSelectedInstOperands,
35438 /* 99287 */ // GIR_Coverage, 603,
35439 /* 99287 */ GIR_EraseRootFromParent_Done,
35440 /* 99288 */ // Label 1833: @99288
35441 /* 99288 */ GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(101279),
35442 /* 99293 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
35443 /* 99296 */ GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(99350), // Rule ID 5566 //
35444 /* 99301 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base),
35445 /* 99306 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
35446 /* 99309 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
35447 /* 99312 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35448 /* 99315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35449 /* 99319 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35450 /* 99323 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35451 /* 99327 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35452 /* 99331 */ // MIs[1] Operand 1
35453 /* 99331 */ // No operand predicates
35454 /* 99331 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35455 /* 99333 */ // (intrinsic_w_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35456 /* 99333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi),
35457 /* 99336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35458 /* 99338 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
35459 /* 99340 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35460 /* 99343 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35461 /* 99348 */ GIR_RootConstrainSelectedInstOperands,
35462 /* 99349 */ // GIR_Coverage, 5566,
35463 /* 99349 */ GIR_EraseRootFromParent_Done,
35464 /* 99350 */ // Label 1835: @99350
35465 /* 99350 */ GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(99404), // Rule ID 5572 //
35466 /* 99355 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base),
35467 /* 99360 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
35468 /* 99363 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
35469 /* 99366 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35470 /* 99369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35471 /* 99373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35472 /* 99377 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35473 /* 99381 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35474 /* 99385 */ // MIs[1] Operand 1
35475 /* 99385 */ // No operand predicates
35476 /* 99385 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35477 /* 99387 */ // (intrinsic_w_chain:{ *:[v4f32] } 3891:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35478 /* 99387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi),
35479 /* 99390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35480 /* 99392 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
35481 /* 99394 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35482 /* 99397 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35483 /* 99402 */ GIR_RootConstrainSelectedInstOperands,
35484 /* 99403 */ // GIR_Coverage, 5572,
35485 /* 99403 */ GIR_EraseRootFromParent_Done,
35486 /* 99404 */ // Label 1836: @99404
35487 /* 99404 */ GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(99458), // Rule ID 5574 //
35488 /* 99409 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base),
35489 /* 99414 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
35490 /* 99417 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
35491 /* 99420 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35492 /* 99423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35493 /* 99427 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35494 /* 99431 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35495 /* 99435 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35496 /* 99439 */ // MIs[1] Operand 1
35497 /* 99439 */ // No operand predicates
35498 /* 99439 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35499 /* 99441 */ // (intrinsic_w_chain:{ *:[v2i64] } 3891:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35500 /* 99441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi),
35501 /* 99444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35502 /* 99446 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
35503 /* 99448 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35504 /* 99451 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35505 /* 99456 */ GIR_RootConstrainSelectedInstOperands,
35506 /* 99457 */ // GIR_Coverage, 5574,
35507 /* 99457 */ GIR_EraseRootFromParent_Done,
35508 /* 99458 */ // Label 1837: @99458
35509 /* 99458 */ GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(99512), // Rule ID 5576 //
35510 /* 99463 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base),
35511 /* 99468 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
35512 /* 99471 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
35513 /* 99474 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35514 /* 99477 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35515 /* 99481 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35516 /* 99485 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35517 /* 99489 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35518 /* 99493 */ // MIs[1] Operand 1
35519 /* 99493 */ // No operand predicates
35520 /* 99493 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35521 /* 99495 */ // (intrinsic_w_chain:{ *:[v2f64] } 3891:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35522 /* 99495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi),
35523 /* 99498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35524 /* 99500 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
35525 /* 99502 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35526 /* 99505 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35527 /* 99510 */ GIR_RootConstrainSelectedInstOperands,
35528 /* 99511 */ // GIR_Coverage, 5576,
35529 /* 99511 */ GIR_EraseRootFromParent_Done,
35530 /* 99512 */ // Label 1838: @99512
35531 /* 99512 */ GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(99554), // Rule ID 1927 //
35532 /* 99517 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_space),
35533 /* 99522 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35534 /* 99525 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35535 /* 99528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35536 /* 99532 */ // MIs[0] size
35537 /* 99532 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35538 /* 99535 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35539 /* 99539 */ // (intrinsic_w_chain:{ *:[i32] } 4161:{ *:[iPTR] }, (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) => (SPACE:{ *:[i32] } (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn)
35540 /* 99539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SPACE),
35541 /* 99542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35542 /* 99544 */ GIR_RootToRootCopy, /*OpIdx*/2, // size
35543 /* 99546 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
35544 /* 99548 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35545 /* 99552 */ GIR_RootConstrainSelectedInstOperands,
35546 /* 99553 */ // GIR_Coverage, 1927,
35547 /* 99553 */ GIR_EraseRootFromParent_Done,
35548 /* 99554 */ // Label 1839: @99554
35549 /* 99554 */ GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(99608), // Rule ID 5568 //
35550 /* 99559 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base),
35551 /* 99564 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
35552 /* 99567 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35553 /* 99570 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
35554 /* 99573 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35555 /* 99577 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35556 /* 99581 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35557 /* 99585 */ // MIs[1] Operand 1
35558 /* 99585 */ // No operand predicates
35559 /* 99585 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35560 /* 99589 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35561 /* 99591 */ // (intrinsic_void 3973:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35562 /* 99591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi),
35563 /* 99594 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
35564 /* 99596 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
35565 /* 99598 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35566 /* 99601 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35567 /* 99606 */ GIR_RootConstrainSelectedInstOperands,
35568 /* 99607 */ // GIR_Coverage, 5568,
35569 /* 99607 */ GIR_EraseRootFromParent_Done,
35570 /* 99608 */ // Label 1840: @99608
35571 /* 99608 */ GIM_Try, /*On fail goto*//*Label 1841*/ GIMT_Encode4(99662), // Rule ID 5578 //
35572 /* 99613 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base),
35573 /* 99618 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
35574 /* 99621 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35575 /* 99624 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
35576 /* 99627 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35577 /* 99631 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35578 /* 99635 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35579 /* 99639 */ // MIs[1] Operand 1
35580 /* 99639 */ // No operand predicates
35581 /* 99639 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35582 /* 99643 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35583 /* 99645 */ // (intrinsic_void 3973:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35584 /* 99645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi),
35585 /* 99648 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
35586 /* 99650 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
35587 /* 99652 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35588 /* 99655 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35589 /* 99660 */ GIR_RootConstrainSelectedInstOperands,
35590 /* 99661 */ // GIR_Coverage, 5578,
35591 /* 99661 */ GIR_EraseRootFromParent_Done,
35592 /* 99662 */ // Label 1841: @99662
35593 /* 99662 */ GIM_Try, /*On fail goto*//*Label 1842*/ GIMT_Encode4(99716), // Rule ID 5582 //
35594 /* 99667 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base),
35595 /* 99672 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
35596 /* 99675 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35597 /* 99678 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
35598 /* 99681 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35599 /* 99685 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35600 /* 99689 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35601 /* 99693 */ // MIs[1] Operand 1
35602 /* 99693 */ // No operand predicates
35603 /* 99693 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35604 /* 99697 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35605 /* 99699 */ // (intrinsic_void 3973:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35606 /* 99699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi),
35607 /* 99702 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
35608 /* 99704 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
35609 /* 99706 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35610 /* 99709 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35611 /* 99714 */ GIR_RootConstrainSelectedInstOperands,
35612 /* 99715 */ // GIR_Coverage, 5582,
35613 /* 99715 */ GIR_EraseRootFromParent_Done,
35614 /* 99716 */ // Label 1842: @99716
35615 /* 99716 */ GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(99770), // Rule ID 5586 //
35616 /* 99721 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base),
35617 /* 99726 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
35618 /* 99729 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35619 /* 99732 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
35620 /* 99735 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35621 /* 99739 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35622 /* 99743 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35623 /* 99747 */ // MIs[1] Operand 1
35624 /* 99747 */ // No operand predicates
35625 /* 99747 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35626 /* 99751 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35627 /* 99753 */ // (intrinsic_void 3973:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35628 /* 99753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi),
35629 /* 99756 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
35630 /* 99758 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
35631 /* 99760 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35632 /* 99763 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35633 /* 99768 */ GIR_RootConstrainSelectedInstOperands,
35634 /* 99769 */ // GIR_Coverage, 5586,
35635 /* 99769 */ GIR_EraseRootFromParent_Done,
35636 /* 99770 */ // Label 1843: @99770
35637 /* 99770 */ GIM_Try, /*On fail goto*//*Label 1844*/ GIMT_Encode4(99828), // Rule ID 3 //
35638 /* 99775 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
35639 /* 99778 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel),
35640 /* 99783 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35641 /* 99786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35642 /* 99789 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35643 /* 99792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35644 /* 99796 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35645 /* 99800 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35646 /* 99804 */ // (intrinsic_w_chain:{ *:[i32] } 4129:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
35647 /* 99804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SEL),
35648 /* 99807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35649 /* 99809 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35650 /* 99811 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35651 /* 99813 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35652 /* 99816 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35653 /* 99822 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35654 /* 99826 */ GIR_RootConstrainSelectedInstOperands,
35655 /* 99827 */ // GIR_Coverage, 3,
35656 /* 99827 */ GIR_EraseRootFromParent_Done,
35657 /* 99828 */ // Label 1844: @99828
35658 /* 99828 */ GIM_Try, /*On fail goto*//*Label 1845*/ GIMT_Encode4(99886), // Rule ID 120 //
35659 /* 99833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35660 /* 99836 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx),
35661 /* 99841 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35662 /* 99844 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35663 /* 99847 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35664 /* 99850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35665 /* 99854 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35666 /* 99858 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35667 /* 99862 */ // (intrinsic_w_chain:{ *:[i32] } 4128:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35668 /* 99862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SASX),
35669 /* 99865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35670 /* 99867 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35671 /* 99869 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35672 /* 99871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35673 /* 99874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35674 /* 99880 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35675 /* 99884 */ GIR_RootConstrainSelectedInstOperands,
35676 /* 99885 */ // GIR_Coverage, 120,
35677 /* 99885 */ GIR_EraseRootFromParent_Done,
35678 /* 99886 */ // Label 1845: @99886
35679 /* 99886 */ GIM_Try, /*On fail goto*//*Label 1846*/ GIMT_Encode4(99944), // Rule ID 121 //
35680 /* 99891 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35681 /* 99894 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16),
35682 /* 99899 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35683 /* 99902 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35684 /* 99905 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35685 /* 99908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35686 /* 99912 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35687 /* 99916 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35688 /* 99920 */ // (intrinsic_w_chain:{ *:[i32] } 4126:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35689 /* 99920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD16),
35690 /* 99923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35691 /* 99925 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35692 /* 99927 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35693 /* 99929 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35694 /* 99932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35695 /* 99938 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35696 /* 99942 */ GIR_RootConstrainSelectedInstOperands,
35697 /* 99943 */ // GIR_Coverage, 121,
35698 /* 99943 */ GIR_EraseRootFromParent_Done,
35699 /* 99944 */ // Label 1846: @99944
35700 /* 99944 */ GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(100002), // Rule ID 122 //
35701 /* 99949 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35702 /* 99952 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8),
35703 /* 99957 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35704 /* 99960 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35705 /* 99963 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35706 /* 99966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35707 /* 99970 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35708 /* 99974 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35709 /* 99978 */ // (intrinsic_w_chain:{ *:[i32] } 4127:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35710 /* 99978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD8),
35711 /* 99981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35712 /* 99983 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35713 /* 99985 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35714 /* 99987 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35715 /* 99990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35716 /* 99996 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35717 /* 100000 */ GIR_RootConstrainSelectedInstOperands,
35718 /* 100001 */ // GIR_Coverage, 122,
35719 /* 100001 */ GIR_EraseRootFromParent_Done,
35720 /* 100002 */ // Label 1847: @100002
35721 /* 100002 */ GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(100060), // Rule ID 123 //
35722 /* 100007 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35723 /* 100010 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax),
35724 /* 100015 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35725 /* 100018 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35726 /* 100021 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35727 /* 100024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35728 /* 100028 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35729 /* 100032 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35730 /* 100036 */ // (intrinsic_w_chain:{ *:[i32] } 4164:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35731 /* 100036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSAX),
35732 /* 100039 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35733 /* 100041 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35734 /* 100043 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35735 /* 100045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35736 /* 100048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35737 /* 100054 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35738 /* 100058 */ GIR_RootConstrainSelectedInstOperands,
35739 /* 100059 */ // GIR_Coverage, 123,
35740 /* 100059 */ GIR_EraseRootFromParent_Done,
35741 /* 100060 */ // Label 1848: @100060
35742 /* 100060 */ GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(100118), // Rule ID 124 //
35743 /* 100065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35744 /* 100068 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16),
35745 /* 100073 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35746 /* 100076 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35747 /* 100079 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35748 /* 100082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35749 /* 100086 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35750 /* 100090 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35751 /* 100094 */ // (intrinsic_w_chain:{ *:[i32] } 4165:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35752 /* 100094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB16),
35753 /* 100097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35754 /* 100099 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35755 /* 100101 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35756 /* 100103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35757 /* 100106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35758 /* 100112 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35759 /* 100116 */ GIR_RootConstrainSelectedInstOperands,
35760 /* 100117 */ // GIR_Coverage, 124,
35761 /* 100117 */ GIR_EraseRootFromParent_Done,
35762 /* 100118 */ // Label 1849: @100118
35763 /* 100118 */ GIM_Try, /*On fail goto*//*Label 1850*/ GIMT_Encode4(100176), // Rule ID 125 //
35764 /* 100123 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35765 /* 100126 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8),
35766 /* 100131 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35767 /* 100134 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35768 /* 100137 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35769 /* 100140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35770 /* 100144 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35771 /* 100148 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35772 /* 100152 */ // (intrinsic_w_chain:{ *:[i32] } 4166:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35773 /* 100152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB8),
35774 /* 100155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35775 /* 100157 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35776 /* 100159 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35777 /* 100161 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35778 /* 100164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35779 /* 100170 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35780 /* 100174 */ GIR_RootConstrainSelectedInstOperands,
35781 /* 100175 */ // GIR_Coverage, 125,
35782 /* 100175 */ GIR_EraseRootFromParent_Done,
35783 /* 100176 */ // Label 1850: @100176
35784 /* 100176 */ GIM_Try, /*On fail goto*//*Label 1851*/ GIMT_Encode4(100234), // Rule ID 126 //
35785 /* 100181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35786 /* 100184 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx),
35787 /* 100189 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35788 /* 100192 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35789 /* 100195 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35790 /* 100198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35791 /* 100202 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35792 /* 100206 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35793 /* 100210 */ // (intrinsic_w_chain:{ *:[i32] } 4179:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35794 /* 100210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UASX),
35795 /* 100213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35796 /* 100215 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35797 /* 100217 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35798 /* 100219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35799 /* 100222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35800 /* 100228 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35801 /* 100232 */ GIR_RootConstrainSelectedInstOperands,
35802 /* 100233 */ // GIR_Coverage, 126,
35803 /* 100233 */ GIR_EraseRootFromParent_Done,
35804 /* 100234 */ // Label 1851: @100234
35805 /* 100234 */ GIM_Try, /*On fail goto*//*Label 1852*/ GIMT_Encode4(100292), // Rule ID 127 //
35806 /* 100239 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35807 /* 100242 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16),
35808 /* 100247 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35809 /* 100250 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35810 /* 100253 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35811 /* 100256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35812 /* 100260 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35813 /* 100264 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35814 /* 100268 */ // (intrinsic_w_chain:{ *:[i32] } 4177:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35815 /* 100268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD16),
35816 /* 100271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35817 /* 100273 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35818 /* 100275 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35819 /* 100277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35820 /* 100280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35821 /* 100286 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35822 /* 100290 */ GIR_RootConstrainSelectedInstOperands,
35823 /* 100291 */ // GIR_Coverage, 127,
35824 /* 100291 */ GIR_EraseRootFromParent_Done,
35825 /* 100292 */ // Label 1852: @100292
35826 /* 100292 */ GIM_Try, /*On fail goto*//*Label 1853*/ GIMT_Encode4(100350), // Rule ID 128 //
35827 /* 100297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35828 /* 100300 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8),
35829 /* 100305 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35830 /* 100308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35831 /* 100311 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35832 /* 100314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35833 /* 100318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35834 /* 100322 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35835 /* 100326 */ // (intrinsic_w_chain:{ *:[i32] } 4178:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35836 /* 100326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD8),
35837 /* 100329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35838 /* 100331 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35839 /* 100333 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35840 /* 100335 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35841 /* 100338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35842 /* 100344 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35843 /* 100348 */ GIR_RootConstrainSelectedInstOperands,
35844 /* 100349 */ // GIR_Coverage, 128,
35845 /* 100349 */ GIR_EraseRootFromParent_Done,
35846 /* 100350 */ // Label 1853: @100350
35847 /* 100350 */ GIM_Try, /*On fail goto*//*Label 1854*/ GIMT_Encode4(100408), // Rule ID 129 //
35848 /* 100355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35849 /* 100358 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax),
35850 /* 100363 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35851 /* 100366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35852 /* 100369 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35853 /* 100372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35854 /* 100376 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35855 /* 100380 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35856 /* 100384 */ // (intrinsic_w_chain:{ *:[i32] } 4197:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35857 /* 100384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAX),
35858 /* 100387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35859 /* 100389 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35860 /* 100391 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35861 /* 100393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35862 /* 100396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35863 /* 100402 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35864 /* 100406 */ GIR_RootConstrainSelectedInstOperands,
35865 /* 100407 */ // GIR_Coverage, 129,
35866 /* 100407 */ GIR_EraseRootFromParent_Done,
35867 /* 100408 */ // Label 1854: @100408
35868 /* 100408 */ GIM_Try, /*On fail goto*//*Label 1855*/ GIMT_Encode4(100466), // Rule ID 130 //
35869 /* 100413 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35870 /* 100416 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16),
35871 /* 100421 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35872 /* 100424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35873 /* 100427 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35874 /* 100430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35875 /* 100434 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35876 /* 100438 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35877 /* 100442 */ // (intrinsic_w_chain:{ *:[i32] } 4198:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35878 /* 100442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB16),
35879 /* 100445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35880 /* 100447 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35881 /* 100449 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35882 /* 100451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35883 /* 100454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35884 /* 100460 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35885 /* 100464 */ GIR_RootConstrainSelectedInstOperands,
35886 /* 100465 */ // GIR_Coverage, 130,
35887 /* 100465 */ GIR_EraseRootFromParent_Done,
35888 /* 100466 */ // Label 1855: @100466
35889 /* 100466 */ GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(100524), // Rule ID 131 //
35890 /* 100471 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35891 /* 100474 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8),
35892 /* 100479 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35893 /* 100482 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35894 /* 100485 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35895 /* 100488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35896 /* 100492 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35897 /* 100496 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35898 /* 100500 */ // (intrinsic_w_chain:{ *:[i32] } 4199:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35899 /* 100500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB8),
35900 /* 100503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35901 /* 100505 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35902 /* 100507 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35903 /* 100509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35904 /* 100512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35905 /* 100518 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35906 /* 100522 */ GIR_RootConstrainSelectedInstOperands,
35907 /* 100523 */ // GIR_Coverage, 131,
35908 /* 100523 */ GIR_EraseRootFromParent_Done,
35909 /* 100524 */ // Label 1856: @100524
35910 /* 100524 */ GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(100582), // Rule ID 430 //
35911 /* 100529 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
35912 /* 100532 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel),
35913 /* 100537 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35914 /* 100540 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35915 /* 100543 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35916 /* 100546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35917 /* 100550 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35918 /* 100554 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35919 /* 100558 */ // (intrinsic_w_chain:{ *:[i32] } 4129:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (t2SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
35920 /* 100558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SEL),
35921 /* 100561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35922 /* 100563 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35923 /* 100565 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35924 /* 100567 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35925 /* 100570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35926 /* 100576 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35927 /* 100580 */ GIR_RootConstrainSelectedInstOperands,
35928 /* 100581 */ // GIR_Coverage, 430,
35929 /* 100581 */ GIR_EraseRootFromParent_Done,
35930 /* 100582 */ // Label 1857: @100582
35931 /* 100582 */ GIM_Try, /*On fail goto*//*Label 1858*/ GIMT_Encode4(100640), // Rule ID 443 //
35932 /* 100587 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
35933 /* 100590 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx),
35934 /* 100595 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35935 /* 100598 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35936 /* 100601 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35937 /* 100604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35938 /* 100608 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35939 /* 100612 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35940 /* 100616 */ // (intrinsic_w_chain:{ *:[i32] } 4128:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35941 /* 100616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SASX),
35942 /* 100619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35943 /* 100621 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35944 /* 100623 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35945 /* 100625 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35946 /* 100628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35947 /* 100634 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35948 /* 100638 */ GIR_RootConstrainSelectedInstOperands,
35949 /* 100639 */ // GIR_Coverage, 443,
35950 /* 100639 */ GIR_EraseRootFromParent_Done,
35951 /* 100640 */ // Label 1858: @100640
35952 /* 100640 */ GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(100698), // Rule ID 444 //
35953 /* 100645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
35954 /* 100648 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16),
35955 /* 100653 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35956 /* 100656 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35957 /* 100659 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35958 /* 100662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35959 /* 100666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35960 /* 100670 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35961 /* 100674 */ // (intrinsic_w_chain:{ *:[i32] } 4126:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35962 /* 100674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD16),
35963 /* 100677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35964 /* 100679 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35965 /* 100681 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35966 /* 100683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35967 /* 100686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35968 /* 100692 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35969 /* 100696 */ GIR_RootConstrainSelectedInstOperands,
35970 /* 100697 */ // GIR_Coverage, 444,
35971 /* 100697 */ GIR_EraseRootFromParent_Done,
35972 /* 100698 */ // Label 1859: @100698
35973 /* 100698 */ GIM_Try, /*On fail goto*//*Label 1860*/ GIMT_Encode4(100756), // Rule ID 445 //
35974 /* 100703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
35975 /* 100706 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8),
35976 /* 100711 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35977 /* 100714 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35978 /* 100717 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35979 /* 100720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35980 /* 100724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35981 /* 100728 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35982 /* 100732 */ // (intrinsic_w_chain:{ *:[i32] } 4127:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35983 /* 100732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD8),
35984 /* 100735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35985 /* 100737 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35986 /* 100739 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35987 /* 100741 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35988 /* 100744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35989 /* 100750 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35990 /* 100754 */ GIR_RootConstrainSelectedInstOperands,
35991 /* 100755 */ // GIR_Coverage, 445,
35992 /* 100755 */ GIR_EraseRootFromParent_Done,
35993 /* 100756 */ // Label 1860: @100756
35994 /* 100756 */ GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(100814), // Rule ID 446 //
35995 /* 100761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
35996 /* 100764 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax),
35997 /* 100769 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35998 /* 100772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35999 /* 100775 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36000 /* 100778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36001 /* 100782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36002 /* 100786 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36003 /* 100790 */ // (intrinsic_w_chain:{ *:[i32] } 4164:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36004 /* 100790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSAX),
36005 /* 100793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36006 /* 100795 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36007 /* 100797 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36008 /* 100799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36009 /* 100802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36010 /* 100808 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36011 /* 100812 */ GIR_RootConstrainSelectedInstOperands,
36012 /* 100813 */ // GIR_Coverage, 446,
36013 /* 100813 */ GIR_EraseRootFromParent_Done,
36014 /* 100814 */ // Label 1861: @100814
36015 /* 100814 */ GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(100872), // Rule ID 447 //
36016 /* 100819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36017 /* 100822 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16),
36018 /* 100827 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36019 /* 100830 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36020 /* 100833 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36021 /* 100836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36022 /* 100840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36023 /* 100844 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36024 /* 100848 */ // (intrinsic_w_chain:{ *:[i32] } 4165:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36025 /* 100848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB16),
36026 /* 100851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36027 /* 100853 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36028 /* 100855 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36029 /* 100857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36030 /* 100860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36031 /* 100866 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36032 /* 100870 */ GIR_RootConstrainSelectedInstOperands,
36033 /* 100871 */ // GIR_Coverage, 447,
36034 /* 100871 */ GIR_EraseRootFromParent_Done,
36035 /* 100872 */ // Label 1862: @100872
36036 /* 100872 */ GIM_Try, /*On fail goto*//*Label 1863*/ GIMT_Encode4(100930), // Rule ID 448 //
36037 /* 100877 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36038 /* 100880 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8),
36039 /* 100885 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36040 /* 100888 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36041 /* 100891 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36042 /* 100894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36043 /* 100898 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36044 /* 100902 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36045 /* 100906 */ // (intrinsic_w_chain:{ *:[i32] } 4166:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36046 /* 100906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB8),
36047 /* 100909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36048 /* 100911 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36049 /* 100913 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36050 /* 100915 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36051 /* 100918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36052 /* 100924 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36053 /* 100928 */ GIR_RootConstrainSelectedInstOperands,
36054 /* 100929 */ // GIR_Coverage, 448,
36055 /* 100929 */ GIR_EraseRootFromParent_Done,
36056 /* 100930 */ // Label 1863: @100930
36057 /* 100930 */ GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(100988), // Rule ID 449 //
36058 /* 100935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36059 /* 100938 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx),
36060 /* 100943 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36061 /* 100946 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36062 /* 100949 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36063 /* 100952 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36064 /* 100956 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36065 /* 100960 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36066 /* 100964 */ // (intrinsic_w_chain:{ *:[i32] } 4179:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36067 /* 100964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UASX),
36068 /* 100967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36069 /* 100969 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36070 /* 100971 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36071 /* 100973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36072 /* 100976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36073 /* 100982 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36074 /* 100986 */ GIR_RootConstrainSelectedInstOperands,
36075 /* 100987 */ // GIR_Coverage, 449,
36076 /* 100987 */ GIR_EraseRootFromParent_Done,
36077 /* 100988 */ // Label 1864: @100988
36078 /* 100988 */ GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(101046), // Rule ID 450 //
36079 /* 100993 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36080 /* 100996 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16),
36081 /* 101001 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36082 /* 101004 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36083 /* 101007 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36084 /* 101010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36085 /* 101014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36086 /* 101018 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36087 /* 101022 */ // (intrinsic_w_chain:{ *:[i32] } 4177:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36088 /* 101022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD16),
36089 /* 101025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36090 /* 101027 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36091 /* 101029 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36092 /* 101031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36093 /* 101034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36094 /* 101040 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36095 /* 101044 */ GIR_RootConstrainSelectedInstOperands,
36096 /* 101045 */ // GIR_Coverage, 450,
36097 /* 101045 */ GIR_EraseRootFromParent_Done,
36098 /* 101046 */ // Label 1865: @101046
36099 /* 101046 */ GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(101104), // Rule ID 451 //
36100 /* 101051 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36101 /* 101054 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8),
36102 /* 101059 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36103 /* 101062 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36104 /* 101065 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36105 /* 101068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36106 /* 101072 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36107 /* 101076 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36108 /* 101080 */ // (intrinsic_w_chain:{ *:[i32] } 4178:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36109 /* 101080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD8),
36110 /* 101083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36111 /* 101085 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36112 /* 101087 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36113 /* 101089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36114 /* 101092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36115 /* 101098 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36116 /* 101102 */ GIR_RootConstrainSelectedInstOperands,
36117 /* 101103 */ // GIR_Coverage, 451,
36118 /* 101103 */ GIR_EraseRootFromParent_Done,
36119 /* 101104 */ // Label 1866: @101104
36120 /* 101104 */ GIM_Try, /*On fail goto*//*Label 1867*/ GIMT_Encode4(101162), // Rule ID 452 //
36121 /* 101109 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36122 /* 101112 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax),
36123 /* 101117 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36124 /* 101120 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36125 /* 101123 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36126 /* 101126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36127 /* 101130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36128 /* 101134 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36129 /* 101138 */ // (intrinsic_w_chain:{ *:[i32] } 4197:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36130 /* 101138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAX),
36131 /* 101141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36132 /* 101143 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36133 /* 101145 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36134 /* 101147 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36135 /* 101150 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36136 /* 101156 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36137 /* 101160 */ GIR_RootConstrainSelectedInstOperands,
36138 /* 101161 */ // GIR_Coverage, 452,
36139 /* 101161 */ GIR_EraseRootFromParent_Done,
36140 /* 101162 */ // Label 1867: @101162
36141 /* 101162 */ GIM_Try, /*On fail goto*//*Label 1868*/ GIMT_Encode4(101220), // Rule ID 453 //
36142 /* 101167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36143 /* 101170 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16),
36144 /* 101175 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36145 /* 101178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36146 /* 101181 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36147 /* 101184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36148 /* 101188 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36149 /* 101192 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36150 /* 101196 */ // (intrinsic_w_chain:{ *:[i32] } 4198:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36151 /* 101196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB16),
36152 /* 101199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36153 /* 101201 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36154 /* 101203 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36155 /* 101205 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36156 /* 101208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36157 /* 101214 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36158 /* 101218 */ GIR_RootConstrainSelectedInstOperands,
36159 /* 101219 */ // GIR_Coverage, 453,
36160 /* 101219 */ GIR_EraseRootFromParent_Done,
36161 /* 101220 */ // Label 1868: @101220
36162 /* 101220 */ GIM_Try, /*On fail goto*//*Label 1869*/ GIMT_Encode4(101278), // Rule ID 454 //
36163 /* 101225 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36164 /* 101228 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8),
36165 /* 101233 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36166 /* 101236 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36167 /* 101239 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36168 /* 101242 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36169 /* 101246 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36170 /* 101250 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36171 /* 101254 */ // (intrinsic_w_chain:{ *:[i32] } 4199:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36172 /* 101254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB8),
36173 /* 101257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36174 /* 101259 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36175 /* 101261 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36176 /* 101263 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36177 /* 101266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36178 /* 101272 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36179 /* 101276 */ GIR_RootConstrainSelectedInstOperands,
36180 /* 101277 */ // GIR_Coverage, 454,
36181 /* 101277 */ GIR_EraseRootFromParent_Done,
36182 /* 101278 */ // Label 1869: @101278
36183 /* 101278 */ GIM_Reject,
36184 /* 101279 */ // Label 1834: @101279
36185 /* 101279 */ GIM_Try, /*On fail goto*//*Label 1870*/ GIMT_Encode4(101525),
36186 /* 101284 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
36187 /* 101287 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base_wb),
36188 /* 101292 */ GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(101350), // Rule ID 5570 //
36189 /* 101297 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
36190 /* 101300 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36191 /* 101303 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36192 /* 101306 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
36193 /* 101309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36194 /* 101313 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36195 /* 101317 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36196 /* 101321 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36197 /* 101325 */ // MIs[1] Operand 1
36198 /* 101325 */ // No operand predicates
36199 /* 101325 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36200 /* 101329 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36201 /* 101331 */ // (intrinsic_w_chain:{ *:[v4i32] } 3975:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
36202 /* 101331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre),
36203 /* 101334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
36204 /* 101336 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
36205 /* 101338 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
36206 /* 101340 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36207 /* 101343 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
36208 /* 101348 */ GIR_RootConstrainSelectedInstOperands,
36209 /* 101349 */ // GIR_Coverage, 5570,
36210 /* 101349 */ GIR_EraseRootFromParent_Done,
36211 /* 101350 */ // Label 1871: @101350
36212 /* 101350 */ GIM_Try, /*On fail goto*//*Label 1872*/ GIMT_Encode4(101408), // Rule ID 5580 //
36213 /* 101355 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
36214 /* 101358 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36215 /* 101361 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36216 /* 101364 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
36217 /* 101367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36218 /* 101371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36219 /* 101375 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36220 /* 101379 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36221 /* 101383 */ // MIs[1] Operand 1
36222 /* 101383 */ // No operand predicates
36223 /* 101383 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36224 /* 101387 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36225 /* 101389 */ // (intrinsic_w_chain:{ *:[v4i32] } 3975:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
36226 /* 101389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre),
36227 /* 101392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
36228 /* 101394 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
36229 /* 101396 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
36230 /* 101398 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36231 /* 101401 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
36232 /* 101406 */ GIR_RootConstrainSelectedInstOperands,
36233 /* 101407 */ // GIR_Coverage, 5580,
36234 /* 101407 */ GIR_EraseRootFromParent_Done,
36235 /* 101408 */ // Label 1872: @101408
36236 /* 101408 */ GIM_Try, /*On fail goto*//*Label 1873*/ GIMT_Encode4(101466), // Rule ID 5584 //
36237 /* 101413 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
36238 /* 101416 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
36239 /* 101419 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36240 /* 101422 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
36241 /* 101425 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36242 /* 101429 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36243 /* 101433 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36244 /* 101437 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36245 /* 101441 */ // MIs[1] Operand 1
36246 /* 101441 */ // No operand predicates
36247 /* 101441 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36248 /* 101445 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36249 /* 101447 */ // (intrinsic_w_chain:{ *:[v2i64] } 3975:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
36250 /* 101447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre),
36251 /* 101450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
36252 /* 101452 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
36253 /* 101454 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
36254 /* 101456 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36255 /* 101459 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
36256 /* 101464 */ GIR_RootConstrainSelectedInstOperands,
36257 /* 101465 */ // GIR_Coverage, 5584,
36258 /* 101465 */ GIR_EraseRootFromParent_Done,
36259 /* 101466 */ // Label 1873: @101466
36260 /* 101466 */ GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(101524), // Rule ID 5588 //
36261 /* 101471 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
36262 /* 101474 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
36263 /* 101477 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36264 /* 101480 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
36265 /* 101483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36266 /* 101487 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36267 /* 101491 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36268 /* 101495 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36269 /* 101499 */ // MIs[1] Operand 1
36270 /* 101499 */ // No operand predicates
36271 /* 101499 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36272 /* 101503 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36273 /* 101505 */ // (intrinsic_w_chain:{ *:[v2i64] } 3975:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
36274 /* 101505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre),
36275 /* 101508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
36276 /* 101510 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
36277 /* 101512 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
36278 /* 101514 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36279 /* 101517 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
36280 /* 101522 */ GIR_RootConstrainSelectedInstOperands,
36281 /* 101523 */ // GIR_Coverage, 5588,
36282 /* 101523 */ GIR_EraseRootFromParent_Done,
36283 /* 101524 */ // Label 1874: @101524
36284 /* 101524 */ GIM_Reject,
36285 /* 101525 */ // Label 1870: @101525
36286 /* 101525 */ GIM_Try, /*On fail goto*//*Label 1875*/ GIMT_Encode4(102696),
36287 /* 101530 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
36288 /* 101533 */ GIM_Try, /*On fail goto*//*Label 1876*/ GIMT_Encode4(101594), // Rule ID 5458 //
36289 /* 101538 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36290 /* 101543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36291 /* 101546 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
36292 /* 101549 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36293 /* 101552 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36294 /* 101555 */ // MIs[0] base
36295 /* 101555 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36296 /* 101559 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36297 /* 101563 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36298 /* 101567 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36299 /* 101571 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36300 /* 101575 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36301 /* 101579 */ // (intrinsic_void 3977:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36302 /* 101579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u),
36303 /* 101582 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36304 /* 101584 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36305 /* 101586 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36306 /* 101588 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36307 /* 101592 */ GIR_RootConstrainSelectedInstOperands,
36308 /* 101593 */ // GIR_Coverage, 5458,
36309 /* 101593 */ GIR_EraseRootFromParent_Done,
36310 /* 101594 */ // Label 1876: @101594
36311 /* 101594 */ GIM_Try, /*On fail goto*//*Label 1877*/ GIMT_Encode4(101655), // Rule ID 5459 //
36312 /* 101599 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36313 /* 101604 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36314 /* 101607 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
36315 /* 101610 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36316 /* 101613 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36317 /* 101616 */ // MIs[0] base
36318 /* 101616 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36319 /* 101620 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36320 /* 101624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36321 /* 101628 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36322 /* 101632 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36323 /* 101636 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
36324 /* 101640 */ // (intrinsic_void 3977:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36325 /* 101640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq),
36326 /* 101643 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36327 /* 101645 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36328 /* 101647 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36329 /* 101649 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36330 /* 101653 */ GIR_RootConstrainSelectedInstOperands,
36331 /* 101654 */ // GIR_Coverage, 5459,
36332 /* 101654 */ GIR_EraseRootFromParent_Done,
36333 /* 101655 */ // Label 1877: @101655
36334 /* 101655 */ GIM_Try, /*On fail goto*//*Label 1878*/ GIMT_Encode4(101716), // Rule ID 5462 //
36335 /* 101660 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36336 /* 101665 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
36337 /* 101668 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
36338 /* 101671 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36339 /* 101674 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36340 /* 101677 */ // MIs[0] base
36341 /* 101677 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36342 /* 101681 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36343 /* 101685 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36344 /* 101689 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36345 /* 101693 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36346 /* 101697 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36347 /* 101701 */ // (intrinsic_void 3977:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, MQPR:{ *:[v16i8] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB8_rq MQPR:{ *:[v16i8] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
36348 /* 101701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB8_rq),
36349 /* 101704 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36350 /* 101706 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36351 /* 101708 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36352 /* 101710 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36353 /* 101714 */ GIR_RootConstrainSelectedInstOperands,
36354 /* 101715 */ // GIR_Coverage, 5462,
36355 /* 101715 */ GIR_EraseRootFromParent_Done,
36356 /* 101716 */ // Label 1878: @101716
36357 /* 101716 */ GIM_Try, /*On fail goto*//*Label 1879*/ GIMT_Encode4(101777), // Rule ID 5542 //
36358 /* 101721 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36359 /* 101726 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36360 /* 101729 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
36361 /* 101732 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36362 /* 101735 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36363 /* 101738 */ // MIs[0] base
36364 /* 101738 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36365 /* 101742 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36366 /* 101746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36367 /* 101750 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36368 /* 101754 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36369 /* 101758 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36370 /* 101762 */ // (intrinsic_void 3977:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36371 /* 101762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB16_rq),
36372 /* 101765 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36373 /* 101767 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36374 /* 101769 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36375 /* 101771 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36376 /* 101775 */ GIR_RootConstrainSelectedInstOperands,
36377 /* 101776 */ // GIR_Coverage, 5542,
36378 /* 101776 */ GIR_EraseRootFromParent_Done,
36379 /* 101777 */ // Label 1879: @101777
36380 /* 101777 */ GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(101838), // Rule ID 5544 //
36381 /* 101782 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36382 /* 101787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36383 /* 101790 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
36384 /* 101793 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36385 /* 101796 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36386 /* 101799 */ // MIs[0] base
36387 /* 101799 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36388 /* 101803 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36389 /* 101807 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36390 /* 101811 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36391 /* 101815 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36392 /* 101819 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36393 /* 101823 */ // (intrinsic_void 3977:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36394 /* 101823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB32_rq),
36395 /* 101826 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36396 /* 101828 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36397 /* 101830 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36398 /* 101832 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36399 /* 101836 */ GIR_RootConstrainSelectedInstOperands,
36400 /* 101837 */ // GIR_Coverage, 5544,
36401 /* 101837 */ GIR_EraseRootFromParent_Done,
36402 /* 101838 */ // Label 1880: @101838
36403 /* 101838 */ GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(101899), // Rule ID 5546 //
36404 /* 101843 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36405 /* 101848 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36406 /* 101851 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
36407 /* 101854 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36408 /* 101857 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36409 /* 101860 */ // MIs[0] base
36410 /* 101860 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36411 /* 101864 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36412 /* 101868 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36413 /* 101872 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36414 /* 101876 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36415 /* 101880 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36416 /* 101884 */ // (intrinsic_void 3977:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36417 /* 101884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u),
36418 /* 101887 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36419 /* 101889 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36420 /* 101891 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36421 /* 101893 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36422 /* 101897 */ GIR_RootConstrainSelectedInstOperands,
36423 /* 101898 */ // GIR_Coverage, 5546,
36424 /* 101898 */ GIR_EraseRootFromParent_Done,
36425 /* 101899 */ // Label 1881: @101899
36426 /* 101899 */ GIM_Try, /*On fail goto*//*Label 1882*/ GIMT_Encode4(101960), // Rule ID 5547 //
36427 /* 101904 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36428 /* 101909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36429 /* 101912 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
36430 /* 101915 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36431 /* 101918 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36432 /* 101921 */ // MIs[0] base
36433 /* 101921 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36434 /* 101925 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36435 /* 101929 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36436 /* 101933 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36437 /* 101937 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36438 /* 101941 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
36439 /* 101945 */ // (intrinsic_void 3977:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36440 /* 101945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq),
36441 /* 101948 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36442 /* 101950 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36443 /* 101952 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36444 /* 101954 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36445 /* 101958 */ GIR_RootConstrainSelectedInstOperands,
36446 /* 101959 */ // GIR_Coverage, 5547,
36447 /* 101959 */ GIR_EraseRootFromParent_Done,
36448 /* 101960 */ // Label 1882: @101960
36449 /* 101960 */ GIM_Try, /*On fail goto*//*Label 1883*/ GIMT_Encode4(102021), // Rule ID 5550 //
36450 /* 101965 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36451 /* 101970 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36452 /* 101973 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
36453 /* 101976 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36454 /* 101979 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36455 /* 101982 */ // MIs[0] base
36456 /* 101982 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36457 /* 101986 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36458 /* 101990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36459 /* 101994 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36460 /* 101998 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36461 /* 102002 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36462 /* 102006 */ // (intrinsic_void 3977:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36463 /* 102006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq_u),
36464 /* 102009 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36465 /* 102011 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36466 /* 102013 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36467 /* 102015 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36468 /* 102019 */ GIR_RootConstrainSelectedInstOperands,
36469 /* 102020 */ // GIR_Coverage, 5550,
36470 /* 102020 */ GIR_EraseRootFromParent_Done,
36471 /* 102021 */ // Label 1883: @102021
36472 /* 102021 */ GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(102082), // Rule ID 5551 //
36473 /* 102026 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36474 /* 102031 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36475 /* 102034 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
36476 /* 102037 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36477 /* 102040 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36478 /* 102043 */ // MIs[0] base
36479 /* 102043 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36480 /* 102047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36481 /* 102051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36482 /* 102055 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36483 /* 102059 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36484 /* 102063 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
36485 /* 102067 */ // (intrinsic_void 3977:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36486 /* 102067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq),
36487 /* 102070 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36488 /* 102072 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36489 /* 102074 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36490 /* 102076 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36491 /* 102080 */ GIR_RootConstrainSelectedInstOperands,
36492 /* 102081 */ // GIR_Coverage, 5551,
36493 /* 102081 */ GIR_EraseRootFromParent_Done,
36494 /* 102082 */ // Label 1884: @102082
36495 /* 102082 */ GIM_Try, /*On fail goto*//*Label 1885*/ GIMT_Encode4(102143), // Rule ID 5554 //
36496 /* 102087 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36497 /* 102092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36498 /* 102095 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
36499 /* 102098 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36500 /* 102101 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36501 /* 102104 */ // MIs[0] base
36502 /* 102104 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36503 /* 102108 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36504 /* 102112 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36505 /* 102116 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36506 /* 102120 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
36507 /* 102124 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36508 /* 102128 */ // (intrinsic_void 3977:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36509 /* 102128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u),
36510 /* 102131 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36511 /* 102133 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36512 /* 102135 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36513 /* 102137 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36514 /* 102141 */ GIR_RootConstrainSelectedInstOperands,
36515 /* 102142 */ // GIR_Coverage, 5554,
36516 /* 102142 */ GIR_EraseRootFromParent_Done,
36517 /* 102143 */ // Label 1885: @102143
36518 /* 102143 */ GIM_Try, /*On fail goto*//*Label 1886*/ GIMT_Encode4(102204), // Rule ID 5555 //
36519 /* 102148 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36520 /* 102153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36521 /* 102156 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
36522 /* 102159 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36523 /* 102162 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36524 /* 102165 */ // MIs[0] base
36525 /* 102165 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36526 /* 102169 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36527 /* 102173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36528 /* 102177 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36529 /* 102181 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
36530 /* 102185 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
36531 /* 102189 */ // (intrinsic_void 3977:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36532 /* 102189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq),
36533 /* 102192 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36534 /* 102194 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36535 /* 102196 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36536 /* 102198 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36537 /* 102202 */ GIR_RootConstrainSelectedInstOperands,
36538 /* 102203 */ // GIR_Coverage, 5555,
36539 /* 102203 */ GIR_EraseRootFromParent_Done,
36540 /* 102204 */ // Label 1886: @102204
36541 /* 102204 */ GIM_Try, /*On fail goto*//*Label 1887*/ GIMT_Encode4(102265), // Rule ID 5558 //
36542 /* 102209 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36543 /* 102214 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36544 /* 102217 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
36545 /* 102220 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36546 /* 102223 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36547 /* 102226 */ // MIs[0] base
36548 /* 102226 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36549 /* 102230 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36550 /* 102234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36551 /* 102238 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36552 /* 102242 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
36553 /* 102246 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36554 /* 102250 */ // (intrinsic_void 3977:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36555 /* 102250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u),
36556 /* 102253 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36557 /* 102255 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36558 /* 102257 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36559 /* 102259 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36560 /* 102263 */ GIR_RootConstrainSelectedInstOperands,
36561 /* 102264 */ // GIR_Coverage, 5558,
36562 /* 102264 */ GIR_EraseRootFromParent_Done,
36563 /* 102265 */ // Label 1887: @102265
36564 /* 102265 */ GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(102326), // Rule ID 5559 //
36565 /* 102270 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36566 /* 102275 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36567 /* 102278 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
36568 /* 102281 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36569 /* 102284 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36570 /* 102287 */ // MIs[0] base
36571 /* 102287 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36572 /* 102291 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36573 /* 102295 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36574 /* 102299 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36575 /* 102303 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
36576 /* 102307 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
36577 /* 102311 */ // (intrinsic_void 3977:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36578 /* 102311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq),
36579 /* 102314 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36580 /* 102316 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36581 /* 102318 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36582 /* 102320 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36583 /* 102324 */ GIR_RootConstrainSelectedInstOperands,
36584 /* 102325 */ // GIR_Coverage, 5559,
36585 /* 102325 */ GIR_EraseRootFromParent_Done,
36586 /* 102326 */ // Label 1888: @102326
36587 /* 102326 */ GIM_Try, /*On fail goto*//*Label 1889*/ GIMT_Encode4(102387), // Rule ID 5562 //
36588 /* 102331 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36589 /* 102336 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
36590 /* 102339 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
36591 /* 102342 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36592 /* 102345 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36593 /* 102348 */ // MIs[0] base
36594 /* 102348 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36595 /* 102352 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36596 /* 102356 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36597 /* 102360 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36598 /* 102364 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
36599 /* 102368 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36600 /* 102372 */ // (intrinsic_void 3977:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRD64_rq_u MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36601 /* 102372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq_u),
36602 /* 102375 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36603 /* 102377 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36604 /* 102379 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36605 /* 102381 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36606 /* 102385 */ GIR_RootConstrainSelectedInstOperands,
36607 /* 102386 */ // GIR_Coverage, 5562,
36608 /* 102386 */ GIR_EraseRootFromParent_Done,
36609 /* 102387 */ // Label 1889: @102387
36610 /* 102387 */ GIM_Try, /*On fail goto*//*Label 1890*/ GIMT_Encode4(102448), // Rule ID 5563 //
36611 /* 102392 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36612 /* 102397 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
36613 /* 102400 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
36614 /* 102403 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36615 /* 102406 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36616 /* 102409 */ // MIs[0] base
36617 /* 102409 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36618 /* 102413 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36619 /* 102417 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36620 /* 102421 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36621 /* 102425 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
36622 /* 102429 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
36623 /* 102433 */ // (intrinsic_void 3977:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 3:{ *:[i32] }) => (MVE_VSTRD64_rq MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36624 /* 102433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq),
36625 /* 102436 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36626 /* 102438 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36627 /* 102440 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36628 /* 102442 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36629 /* 102446 */ GIR_RootConstrainSelectedInstOperands,
36630 /* 102447 */ // GIR_Coverage, 5563,
36631 /* 102447 */ GIR_EraseRootFromParent_Done,
36632 /* 102448 */ // Label 1890: @102448
36633 /* 102448 */ GIM_Try, /*On fail goto*//*Label 1891*/ GIMT_Encode4(102512), // Rule ID 257 //
36634 /* 102453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
36635 /* 102456 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr),
36636 /* 102461 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36637 /* 102464 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36638 /* 102467 */ // MIs[0] cop
36639 /* 102467 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36640 /* 102470 */ // MIs[0] opc1
36641 /* 102470 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36642 /* 102473 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36643 /* 102477 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36644 /* 102481 */ // MIs[0] CRm
36645 /* 102481 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36646 /* 102484 */ // (intrinsic_void 3762:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
36647 /* 102484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR),
36648 /* 102487 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
36649 /* 102489 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
36650 /* 102491 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
36651 /* 102493 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
36652 /* 102495 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
36653 /* 102497 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36654 /* 102500 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36655 /* 102506 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36656 /* 102510 */ GIR_RootConstrainSelectedInstOperands,
36657 /* 102511 */ // GIR_Coverage, 257,
36658 /* 102511 */ GIR_EraseRootFromParent_Done,
36659 /* 102512 */ // Label 1891: @102512
36660 /* 102512 */ GIM_Try, /*On fail goto*//*Label 1892*/ GIMT_Encode4(102567), // Rule ID 258 //
36661 /* 102517 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8),
36662 /* 102520 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2),
36663 /* 102525 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36664 /* 102528 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36665 /* 102531 */ // MIs[0] cop
36666 /* 102531 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36667 /* 102534 */ // MIs[0] opc1
36668 /* 102534 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36669 /* 102537 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36670 /* 102541 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36671 /* 102545 */ // MIs[0] CRm
36672 /* 102545 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36673 /* 102548 */ // (intrinsic_void 3763:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
36674 /* 102548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR2),
36675 /* 102551 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
36676 /* 102553 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
36677 /* 102555 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
36678 /* 102557 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
36679 /* 102559 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
36680 /* 102561 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36681 /* 102565 */ GIR_RootConstrainSelectedInstOperands,
36682 /* 102566 */ // GIR_Coverage, 258,
36683 /* 102566 */ GIR_EraseRootFromParent_Done,
36684 /* 102567 */ // Label 1892: @102567
36685 /* 102567 */ GIM_Try, /*On fail goto*//*Label 1893*/ GIMT_Encode4(102631), // Rule ID 595 //
36686 /* 102572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
36687 /* 102575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr),
36688 /* 102580 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36689 /* 102583 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36690 /* 102586 */ // MIs[0] cop
36691 /* 102586 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36692 /* 102589 */ // MIs[0] opc1
36693 /* 102589 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36694 /* 102592 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36695 /* 102596 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36696 /* 102600 */ // MIs[0] CRm
36697 /* 102600 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36698 /* 102603 */ // (intrinsic_void 3762:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
36699 /* 102603 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR),
36700 /* 102606 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
36701 /* 102608 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
36702 /* 102610 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
36703 /* 102612 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
36704 /* 102614 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
36705 /* 102616 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36706 /* 102619 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36707 /* 102625 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36708 /* 102629 */ GIR_RootConstrainSelectedInstOperands,
36709 /* 102630 */ // GIR_Coverage, 595,
36710 /* 102630 */ GIR_EraseRootFromParent_Done,
36711 /* 102631 */ // Label 1893: @102631
36712 /* 102631 */ GIM_Try, /*On fail goto*//*Label 1894*/ GIMT_Encode4(102695), // Rule ID 596 //
36713 /* 102636 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8),
36714 /* 102639 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2),
36715 /* 102644 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36716 /* 102647 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36717 /* 102650 */ // MIs[0] cop
36718 /* 102650 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36719 /* 102653 */ // MIs[0] opc1
36720 /* 102653 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36721 /* 102656 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36722 /* 102660 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36723 /* 102664 */ // MIs[0] CRm
36724 /* 102664 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36725 /* 102667 */ // (intrinsic_void 3763:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
36726 /* 102667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR2),
36727 /* 102670 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
36728 /* 102672 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
36729 /* 102674 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
36730 /* 102676 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
36731 /* 102678 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
36732 /* 102680 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36733 /* 102683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36734 /* 102689 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36735 /* 102693 */ GIR_RootConstrainSelectedInstOperands,
36736 /* 102694 */ // GIR_Coverage, 596,
36737 /* 102694 */ GIR_EraseRootFromParent_Done,
36738 /* 102695 */ // Label 1894: @102695
36739 /* 102695 */ GIM_Reject,
36740 /* 102696 */ // Label 1875: @102696
36741 /* 102696 */ GIM_Try, /*On fail goto*//*Label 1895*/ GIMT_Encode4(106047),
36742 /* 102701 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
36743 /* 102704 */ GIM_Try, /*On fail goto*//*Label 1896*/ GIMT_Encode4(102765), // Rule ID 245 //
36744 /* 102709 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8),
36745 /* 102712 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp),
36746 /* 102717 */ // MIs[0] cop
36747 /* 102717 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36748 /* 102720 */ // MIs[0] opc1
36749 /* 102720 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36750 /* 102723 */ // MIs[0] CRd
36751 /* 102723 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
36752 /* 102726 */ // MIs[0] CRn
36753 /* 102726 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36754 /* 102729 */ // MIs[0] CRm
36755 /* 102729 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36756 /* 102732 */ // MIs[0] opc2
36757 /* 102732 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36758 /* 102735 */ // (intrinsic_void 3730:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36759 /* 102735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP),
36760 /* 102738 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
36761 /* 102740 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
36762 /* 102742 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
36763 /* 102744 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
36764 /* 102746 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
36765 /* 102748 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
36766 /* 102750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36767 /* 102753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36768 /* 102759 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36769 /* 102763 */ GIR_RootConstrainSelectedInstOperands,
36770 /* 102764 */ // GIR_Coverage, 245,
36771 /* 102764 */ GIR_EraseRootFromParent_Done,
36772 /* 102765 */ // Label 1896: @102765
36773 /* 102765 */ GIM_Try, /*On fail goto*//*Label 1897*/ GIMT_Encode4(102817), // Rule ID 246 //
36774 /* 102770 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8),
36775 /* 102773 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2),
36776 /* 102778 */ // MIs[0] cop
36777 /* 102778 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36778 /* 102781 */ // MIs[0] opc1
36779 /* 102781 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36780 /* 102784 */ // MIs[0] CRd
36781 /* 102784 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
36782 /* 102787 */ // MIs[0] CRn
36783 /* 102787 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36784 /* 102790 */ // MIs[0] CRm
36785 /* 102790 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36786 /* 102793 */ // MIs[0] opc2
36787 /* 102793 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36788 /* 102796 */ // (intrinsic_void 3731:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36789 /* 102796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP2),
36790 /* 102799 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
36791 /* 102801 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
36792 /* 102803 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
36793 /* 102805 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
36794 /* 102807 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
36795 /* 102809 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
36796 /* 102811 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36797 /* 102815 */ GIR_RootConstrainSelectedInstOperands,
36798 /* 102816 */ // GIR_Coverage, 246,
36799 /* 102816 */ GIR_EraseRootFromParent_Done,
36800 /* 102817 */ // Label 1897: @102817
36801 /* 102817 */ GIM_Try, /*On fail goto*//*Label 1898*/ GIMT_Encode4(102878), // Rule ID 597 //
36802 /* 102822 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8),
36803 /* 102825 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp),
36804 /* 102830 */ // MIs[0] cop
36805 /* 102830 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36806 /* 102833 */ // MIs[0] opc1
36807 /* 102833 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36808 /* 102836 */ // MIs[0] CRd
36809 /* 102836 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
36810 /* 102839 */ // MIs[0] CRn
36811 /* 102839 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36812 /* 102842 */ // MIs[0] CRm
36813 /* 102842 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36814 /* 102845 */ // MIs[0] opc2
36815 /* 102845 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36816 /* 102848 */ // (intrinsic_void 3730:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36817 /* 102848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP),
36818 /* 102851 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
36819 /* 102853 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
36820 /* 102855 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
36821 /* 102857 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
36822 /* 102859 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
36823 /* 102861 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
36824 /* 102863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36825 /* 102866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36826 /* 102872 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36827 /* 102876 */ GIR_RootConstrainSelectedInstOperands,
36828 /* 102877 */ // GIR_Coverage, 597,
36829 /* 102877 */ GIR_EraseRootFromParent_Done,
36830 /* 102878 */ // Label 1898: @102878
36831 /* 102878 */ GIM_Try, /*On fail goto*//*Label 1899*/ GIMT_Encode4(102939), // Rule ID 598 //
36832 /* 102883 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8),
36833 /* 102886 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2),
36834 /* 102891 */ // MIs[0] cop
36835 /* 102891 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36836 /* 102894 */ // MIs[0] opc1
36837 /* 102894 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36838 /* 102897 */ // MIs[0] CRd
36839 /* 102897 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
36840 /* 102900 */ // MIs[0] CRn
36841 /* 102900 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
36842 /* 102903 */ // MIs[0] CRm
36843 /* 102903 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36844 /* 102906 */ // MIs[0] opc2
36845 /* 102906 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
36846 /* 102909 */ // (intrinsic_void 3731:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
36847 /* 102909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP2),
36848 /* 102912 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
36849 /* 102914 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
36850 /* 102916 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
36851 /* 102918 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
36852 /* 102920 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
36853 /* 102922 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
36854 /* 102924 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36855 /* 102927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36856 /* 102933 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36857 /* 102937 */ GIR_RootConstrainSelectedInstOperands,
36858 /* 102938 */ // GIR_Coverage, 598,
36859 /* 102938 */ GIR_EraseRootFromParent_Done,
36860 /* 102939 */ // Label 1899: @102939
36861 /* 102939 */ GIM_Try, /*On fail goto*//*Label 1900*/ GIMT_Encode4(103007), // Rule ID 5452 //
36862 /* 102944 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
36863 /* 102949 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
36864 /* 102952 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
36865 /* 102955 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36866 /* 102958 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36867 /* 102961 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
36868 /* 102964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36869 /* 102968 */ // MIs[0] base
36870 /* 102968 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36871 /* 102972 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36872 /* 102976 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36873 /* 102980 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36874 /* 102984 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36875 /* 102988 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
36876 /* 102992 */ // (intrinsic_w_chain:{ *:[v8i16] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36877 /* 102992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
36878 /* 102995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36879 /* 102997 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
36880 /* 102999 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
36881 /* 103001 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36882 /* 103005 */ GIR_RootConstrainSelectedInstOperands,
36883 /* 103006 */ // GIR_Coverage, 5452,
36884 /* 103006 */ GIR_EraseRootFromParent_Done,
36885 /* 103007 */ // Label 1900: @103007
36886 /* 103007 */ GIM_Try, /*On fail goto*//*Label 1901*/ GIMT_Encode4(103075), // Rule ID 5453 //
36887 /* 103012 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
36888 /* 103017 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
36889 /* 103020 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
36890 /* 103023 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36891 /* 103026 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36892 /* 103029 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
36893 /* 103032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36894 /* 103036 */ // MIs[0] base
36895 /* 103036 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36896 /* 103040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36897 /* 103044 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36898 /* 103048 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36899 /* 103052 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
36900 /* 103056 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
36901 /* 103060 */ // (intrinsic_w_chain:{ *:[v8i16] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36902 /* 103060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
36903 /* 103063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36904 /* 103065 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
36905 /* 103067 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
36906 /* 103069 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36907 /* 103073 */ GIR_RootConstrainSelectedInstOperands,
36908 /* 103074 */ // GIR_Coverage, 5453,
36909 /* 103074 */ GIR_EraseRootFromParent_Done,
36910 /* 103075 */ // Label 1901: @103075
36911 /* 103075 */ GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(103143), // Rule ID 5456 //
36912 /* 103080 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
36913 /* 103085 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
36914 /* 103088 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
36915 /* 103091 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36916 /* 103094 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36917 /* 103097 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
36918 /* 103100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36919 /* 103104 */ // MIs[0] base
36920 /* 103104 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36921 /* 103108 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36922 /* 103112 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36923 /* 103116 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36924 /* 103120 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36925 /* 103124 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
36926 /* 103128 */ // (intrinsic_w_chain:{ *:[v16i8] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
36927 /* 103128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq),
36928 /* 103131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36929 /* 103133 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
36930 /* 103135 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
36931 /* 103137 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36932 /* 103141 */ GIR_RootConstrainSelectedInstOperands,
36933 /* 103142 */ // GIR_Coverage, 5456,
36934 /* 103142 */ GIR_EraseRootFromParent_Done,
36935 /* 103143 */ // Label 1902: @103143
36936 /* 103143 */ GIM_Try, /*On fail goto*//*Label 1903*/ GIMT_Encode4(103211), // Rule ID 5464 //
36937 /* 103148 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
36938 /* 103153 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
36939 /* 103156 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
36940 /* 103159 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36941 /* 103162 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36942 /* 103165 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
36943 /* 103168 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36944 /* 103172 */ // MIs[0] base
36945 /* 103172 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36946 /* 103176 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36947 /* 103180 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36948 /* 103184 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36949 /* 103188 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36950 /* 103192 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
36951 /* 103196 */ // (intrinsic_w_chain:{ *:[v16i8] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
36952 /* 103196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq),
36953 /* 103199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36954 /* 103201 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
36955 /* 103203 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
36956 /* 103205 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36957 /* 103209 */ GIR_RootConstrainSelectedInstOperands,
36958 /* 103210 */ // GIR_Coverage, 5464,
36959 /* 103210 */ GIR_EraseRootFromParent_Done,
36960 /* 103211 */ // Label 1903: @103211
36961 /* 103211 */ GIM_Try, /*On fail goto*//*Label 1904*/ GIMT_Encode4(103279), // Rule ID 5466 //
36962 /* 103216 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
36963 /* 103221 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
36964 /* 103224 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
36965 /* 103227 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36966 /* 103230 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36967 /* 103233 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
36968 /* 103236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36969 /* 103240 */ // MIs[0] base
36970 /* 103240 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36971 /* 103244 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36972 /* 103248 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36973 /* 103252 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36974 /* 103256 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36975 /* 103260 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
36976 /* 103264 */ // (intrinsic_w_chain:{ *:[v8i16] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36977 /* 103264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU16_rq),
36978 /* 103267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36979 /* 103269 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
36980 /* 103271 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
36981 /* 103273 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36982 /* 103277 */ GIR_RootConstrainSelectedInstOperands,
36983 /* 103278 */ // GIR_Coverage, 5466,
36984 /* 103278 */ GIR_EraseRootFromParent_Done,
36985 /* 103279 */ // Label 1904: @103279
36986 /* 103279 */ GIM_Try, /*On fail goto*//*Label 1905*/ GIMT_Encode4(103347), // Rule ID 5468 //
36987 /* 103284 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
36988 /* 103289 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
36989 /* 103292 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
36990 /* 103295 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36991 /* 103298 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36992 /* 103301 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
36993 /* 103304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36994 /* 103308 */ // MIs[0] base
36995 /* 103308 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
36996 /* 103312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36997 /* 103316 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36998 /* 103320 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36999 /* 103324 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37000 /* 103328 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37001 /* 103332 */ // (intrinsic_w_chain:{ *:[v8i16] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37002 /* 103332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS16_rq),
37003 /* 103335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37004 /* 103337 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37005 /* 103339 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37006 /* 103341 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37007 /* 103345 */ GIR_RootConstrainSelectedInstOperands,
37008 /* 103346 */ // GIR_Coverage, 5468,
37009 /* 103346 */ GIR_EraseRootFromParent_Done,
37010 /* 103347 */ // Label 1905: @103347
37011 /* 103347 */ GIM_Try, /*On fail goto*//*Label 1906*/ GIMT_Encode4(103415), // Rule ID 5470 //
37012 /* 103352 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37013 /* 103357 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37014 /* 103360 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37015 /* 103363 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37016 /* 103366 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37017 /* 103369 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37018 /* 103372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37019 /* 103376 */ // MIs[0] base
37020 /* 103376 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37021 /* 103380 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37022 /* 103384 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37023 /* 103388 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
37024 /* 103392 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37025 /* 103396 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37026 /* 103400 */ // (intrinsic_w_chain:{ *:[v4i32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37027 /* 103400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU32_rq),
37028 /* 103403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37029 /* 103405 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37030 /* 103407 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37031 /* 103409 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37032 /* 103413 */ GIR_RootConstrainSelectedInstOperands,
37033 /* 103414 */ // GIR_Coverage, 5470,
37034 /* 103414 */ GIR_EraseRootFromParent_Done,
37035 /* 103415 */ // Label 1906: @103415
37036 /* 103415 */ GIM_Try, /*On fail goto*//*Label 1907*/ GIMT_Encode4(103483), // Rule ID 5472 //
37037 /* 103420 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37038 /* 103425 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37039 /* 103428 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37040 /* 103431 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37041 /* 103434 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37042 /* 103437 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37043 /* 103440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37044 /* 103444 */ // MIs[0] base
37045 /* 103444 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37046 /* 103448 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37047 /* 103452 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37048 /* 103456 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
37049 /* 103460 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37050 /* 103464 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37051 /* 103468 */ // (intrinsic_w_chain:{ *:[v4i32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37052 /* 103468 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS32_rq),
37053 /* 103471 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37054 /* 103473 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37055 /* 103475 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37056 /* 103477 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37057 /* 103481 */ GIR_RootConstrainSelectedInstOperands,
37058 /* 103482 */ // GIR_Coverage, 5472,
37059 /* 103482 */ GIR_EraseRootFromParent_Done,
37060 /* 103483 */ // Label 1907: @103483
37061 /* 103483 */ GIM_Try, /*On fail goto*//*Label 1908*/ GIMT_Encode4(103551), // Rule ID 5474 //
37062 /* 103488 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37063 /* 103493 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37064 /* 103496 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37065 /* 103499 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37066 /* 103502 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37067 /* 103505 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37068 /* 103508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37069 /* 103512 */ // MIs[0] base
37070 /* 103512 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37071 /* 103516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37072 /* 103520 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37073 /* 103524 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37074 /* 103528 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37075 /* 103532 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37076 /* 103536 */ // (intrinsic_w_chain:{ *:[v8i16] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37077 /* 103536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
37078 /* 103539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37079 /* 103541 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37080 /* 103543 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37081 /* 103545 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37082 /* 103549 */ GIR_RootConstrainSelectedInstOperands,
37083 /* 103550 */ // GIR_Coverage, 5474,
37084 /* 103550 */ GIR_EraseRootFromParent_Done,
37085 /* 103551 */ // Label 1908: @103551
37086 /* 103551 */ GIM_Try, /*On fail goto*//*Label 1909*/ GIMT_Encode4(103619), // Rule ID 5475 //
37087 /* 103556 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37088 /* 103561 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37089 /* 103564 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37090 /* 103567 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37091 /* 103570 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37092 /* 103573 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37093 /* 103576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37094 /* 103580 */ // MIs[0] base
37095 /* 103580 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37096 /* 103584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37097 /* 103588 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37098 /* 103592 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37099 /* 103596 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37100 /* 103600 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37101 /* 103604 */ // (intrinsic_w_chain:{ *:[v8i16] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37102 /* 103604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37103 /* 103607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37104 /* 103609 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37105 /* 103611 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37106 /* 103613 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37107 /* 103617 */ GIR_RootConstrainSelectedInstOperands,
37108 /* 103618 */ // GIR_Coverage, 5475,
37109 /* 103618 */ GIR_EraseRootFromParent_Done,
37110 /* 103619 */ // Label 1909: @103619
37111 /* 103619 */ GIM_Try, /*On fail goto*//*Label 1910*/ GIMT_Encode4(103687), // Rule ID 5478 //
37112 /* 103624 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37113 /* 103629 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37114 /* 103632 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37115 /* 103635 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37116 /* 103638 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37117 /* 103641 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37118 /* 103644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37119 /* 103648 */ // MIs[0] base
37120 /* 103648 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37121 /* 103652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37122 /* 103656 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37123 /* 103660 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37124 /* 103664 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37125 /* 103668 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37126 /* 103672 */ // (intrinsic_w_chain:{ *:[v8i16] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37127 /* 103672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
37128 /* 103675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37129 /* 103677 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37130 /* 103679 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37131 /* 103681 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37132 /* 103685 */ GIR_RootConstrainSelectedInstOperands,
37133 /* 103686 */ // GIR_Coverage, 5478,
37134 /* 103686 */ GIR_EraseRootFromParent_Done,
37135 /* 103687 */ // Label 1910: @103687
37136 /* 103687 */ GIM_Try, /*On fail goto*//*Label 1911*/ GIMT_Encode4(103755), // Rule ID 5479 //
37137 /* 103692 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37138 /* 103697 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37139 /* 103700 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37140 /* 103703 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37141 /* 103706 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37142 /* 103709 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37143 /* 103712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37144 /* 103716 */ // MIs[0] base
37145 /* 103716 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37146 /* 103720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37147 /* 103724 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37148 /* 103728 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37149 /* 103732 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37150 /* 103736 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37151 /* 103740 */ // (intrinsic_w_chain:{ *:[v8i16] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37152 /* 103740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37153 /* 103743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37154 /* 103745 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37155 /* 103747 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37156 /* 103749 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37157 /* 103753 */ GIR_RootConstrainSelectedInstOperands,
37158 /* 103754 */ // GIR_Coverage, 5479,
37159 /* 103754 */ GIR_EraseRootFromParent_Done,
37160 /* 103755 */ // Label 1911: @103755
37161 /* 103755 */ GIM_Try, /*On fail goto*//*Label 1912*/ GIMT_Encode4(103823), // Rule ID 5482 //
37162 /* 103760 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37163 /* 103765 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37164 /* 103768 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37165 /* 103771 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37166 /* 103774 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37167 /* 103777 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37168 /* 103780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37169 /* 103784 */ // MIs[0] base
37170 /* 103784 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37171 /* 103788 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37172 /* 103792 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37173 /* 103796 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37174 /* 103800 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37175 /* 103804 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37176 /* 103808 */ // (intrinsic_w_chain:{ *:[v8i16] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37177 /* 103808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
37178 /* 103811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37179 /* 103813 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37180 /* 103815 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37181 /* 103817 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37182 /* 103821 */ GIR_RootConstrainSelectedInstOperands,
37183 /* 103822 */ // GIR_Coverage, 5482,
37184 /* 103822 */ GIR_EraseRootFromParent_Done,
37185 /* 103823 */ // Label 1912: @103823
37186 /* 103823 */ GIM_Try, /*On fail goto*//*Label 1913*/ GIMT_Encode4(103891), // Rule ID 5483 //
37187 /* 103828 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37188 /* 103833 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37189 /* 103836 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37190 /* 103839 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37191 /* 103842 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37192 /* 103845 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37193 /* 103848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37194 /* 103852 */ // MIs[0] base
37195 /* 103852 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37196 /* 103856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37197 /* 103860 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37198 /* 103864 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37199 /* 103868 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37200 /* 103872 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37201 /* 103876 */ // (intrinsic_w_chain:{ *:[v8i16] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37202 /* 103876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37203 /* 103879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37204 /* 103881 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37205 /* 103883 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37206 /* 103885 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37207 /* 103889 */ GIR_RootConstrainSelectedInstOperands,
37208 /* 103890 */ // GIR_Coverage, 5483,
37209 /* 103890 */ GIR_EraseRootFromParent_Done,
37210 /* 103891 */ // Label 1913: @103891
37211 /* 103891 */ GIM_Try, /*On fail goto*//*Label 1914*/ GIMT_Encode4(103959), // Rule ID 5486 //
37212 /* 103896 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37213 /* 103901 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37214 /* 103904 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37215 /* 103907 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37216 /* 103910 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37217 /* 103913 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37218 /* 103916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37219 /* 103920 */ // MIs[0] base
37220 /* 103920 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37221 /* 103924 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37222 /* 103928 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37223 /* 103932 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37224 /* 103936 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37225 /* 103940 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37226 /* 103944 */ // (intrinsic_w_chain:{ *:[v8f16] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37227 /* 103944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
37228 /* 103947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37229 /* 103949 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37230 /* 103951 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37231 /* 103953 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37232 /* 103957 */ GIR_RootConstrainSelectedInstOperands,
37233 /* 103958 */ // GIR_Coverage, 5486,
37234 /* 103958 */ GIR_EraseRootFromParent_Done,
37235 /* 103959 */ // Label 1914: @103959
37236 /* 103959 */ GIM_Try, /*On fail goto*//*Label 1915*/ GIMT_Encode4(104027), // Rule ID 5487 //
37237 /* 103964 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37238 /* 103969 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37239 /* 103972 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37240 /* 103975 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37241 /* 103978 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37242 /* 103981 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37243 /* 103984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37244 /* 103988 */ // MIs[0] base
37245 /* 103988 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37246 /* 103992 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37247 /* 103996 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37248 /* 104000 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37249 /* 104004 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37250 /* 104008 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37251 /* 104012 */ // (intrinsic_w_chain:{ *:[v8f16] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37252 /* 104012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37253 /* 104015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37254 /* 104017 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37255 /* 104019 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37256 /* 104021 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37257 /* 104025 */ GIR_RootConstrainSelectedInstOperands,
37258 /* 104026 */ // GIR_Coverage, 5487,
37259 /* 104026 */ GIR_EraseRootFromParent_Done,
37260 /* 104027 */ // Label 1915: @104027
37261 /* 104027 */ GIM_Try, /*On fail goto*//*Label 1916*/ GIMT_Encode4(104095), // Rule ID 5490 //
37262 /* 104032 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37263 /* 104037 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37264 /* 104040 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37265 /* 104043 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37266 /* 104046 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37267 /* 104049 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37268 /* 104052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37269 /* 104056 */ // MIs[0] base
37270 /* 104056 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37271 /* 104060 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37272 /* 104064 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37273 /* 104068 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37274 /* 104072 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37275 /* 104076 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37276 /* 104080 */ // (intrinsic_w_chain:{ *:[v8f16] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37277 /* 104080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
37278 /* 104083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37279 /* 104085 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37280 /* 104087 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37281 /* 104089 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37282 /* 104093 */ GIR_RootConstrainSelectedInstOperands,
37283 /* 104094 */ // GIR_Coverage, 5490,
37284 /* 104094 */ GIR_EraseRootFromParent_Done,
37285 /* 104095 */ // Label 1916: @104095
37286 /* 104095 */ GIM_Try, /*On fail goto*//*Label 1917*/ GIMT_Encode4(104163), // Rule ID 5491 //
37287 /* 104100 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37288 /* 104105 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37289 /* 104108 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37290 /* 104111 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37291 /* 104114 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37292 /* 104117 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37293 /* 104120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37294 /* 104124 */ // MIs[0] base
37295 /* 104124 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37296 /* 104128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37297 /* 104132 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37298 /* 104136 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37299 /* 104140 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37300 /* 104144 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37301 /* 104148 */ // (intrinsic_w_chain:{ *:[v8f16] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37302 /* 104148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37303 /* 104151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37304 /* 104153 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37305 /* 104155 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37306 /* 104157 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37307 /* 104161 */ GIR_RootConstrainSelectedInstOperands,
37308 /* 104162 */ // GIR_Coverage, 5491,
37309 /* 104162 */ GIR_EraseRootFromParent_Done,
37310 /* 104163 */ // Label 1917: @104163
37311 /* 104163 */ GIM_Try, /*On fail goto*//*Label 1918*/ GIMT_Encode4(104231), // Rule ID 5494 //
37312 /* 104168 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37313 /* 104173 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37314 /* 104176 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37315 /* 104179 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37316 /* 104182 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37317 /* 104185 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37318 /* 104188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37319 /* 104192 */ // MIs[0] base
37320 /* 104192 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37321 /* 104196 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37322 /* 104200 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37323 /* 104204 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37324 /* 104208 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37325 /* 104212 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37326 /* 104216 */ // (intrinsic_w_chain:{ *:[v4i32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37327 /* 104216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq_u),
37328 /* 104219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37329 /* 104221 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37330 /* 104223 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37331 /* 104225 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37332 /* 104229 */ GIR_RootConstrainSelectedInstOperands,
37333 /* 104230 */ // GIR_Coverage, 5494,
37334 /* 104230 */ GIR_EraseRootFromParent_Done,
37335 /* 104231 */ // Label 1918: @104231
37336 /* 104231 */ GIM_Try, /*On fail goto*//*Label 1919*/ GIMT_Encode4(104299), // Rule ID 5495 //
37337 /* 104236 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37338 /* 104241 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37339 /* 104244 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37340 /* 104247 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37341 /* 104250 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37342 /* 104253 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37343 /* 104256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37344 /* 104260 */ // MIs[0] base
37345 /* 104260 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37346 /* 104264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37347 /* 104268 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37348 /* 104272 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37349 /* 104276 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37350 /* 104280 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37351 /* 104284 */ // (intrinsic_w_chain:{ *:[v4i32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37352 /* 104284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq),
37353 /* 104287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37354 /* 104289 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37355 /* 104291 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37356 /* 104293 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37357 /* 104297 */ GIR_RootConstrainSelectedInstOperands,
37358 /* 104298 */ // GIR_Coverage, 5495,
37359 /* 104298 */ GIR_EraseRootFromParent_Done,
37360 /* 104299 */ // Label 1919: @104299
37361 /* 104299 */ GIM_Try, /*On fail goto*//*Label 1920*/ GIMT_Encode4(104367), // Rule ID 5498 //
37362 /* 104304 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37363 /* 104309 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37364 /* 104312 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37365 /* 104315 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37366 /* 104318 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37367 /* 104321 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37368 /* 104324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37369 /* 104328 */ // MIs[0] base
37370 /* 104328 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37371 /* 104332 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37372 /* 104336 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37373 /* 104340 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37374 /* 104344 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37375 /* 104348 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37376 /* 104352 */ // (intrinsic_w_chain:{ *:[v4i32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37377 /* 104352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq_u),
37378 /* 104355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37379 /* 104357 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37380 /* 104359 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37381 /* 104361 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37382 /* 104365 */ GIR_RootConstrainSelectedInstOperands,
37383 /* 104366 */ // GIR_Coverage, 5498,
37384 /* 104366 */ GIR_EraseRootFromParent_Done,
37385 /* 104367 */ // Label 1920: @104367
37386 /* 104367 */ GIM_Try, /*On fail goto*//*Label 1921*/ GIMT_Encode4(104435), // Rule ID 5499 //
37387 /* 104372 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37388 /* 104377 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37389 /* 104380 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37390 /* 104383 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37391 /* 104386 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37392 /* 104389 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37393 /* 104392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37394 /* 104396 */ // MIs[0] base
37395 /* 104396 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37396 /* 104400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37397 /* 104404 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37398 /* 104408 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37399 /* 104412 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37400 /* 104416 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37401 /* 104420 */ // (intrinsic_w_chain:{ *:[v4i32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37402 /* 104420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq),
37403 /* 104423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37404 /* 104425 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37405 /* 104427 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37406 /* 104429 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37407 /* 104433 */ GIR_RootConstrainSelectedInstOperands,
37408 /* 104434 */ // GIR_Coverage, 5499,
37409 /* 104434 */ GIR_EraseRootFromParent_Done,
37410 /* 104435 */ // Label 1921: @104435
37411 /* 104435 */ GIM_Try, /*On fail goto*//*Label 1922*/ GIMT_Encode4(104503), // Rule ID 5502 //
37412 /* 104440 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37413 /* 104445 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37414 /* 104448 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37415 /* 104451 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37416 /* 104454 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37417 /* 104457 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37418 /* 104460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37419 /* 104464 */ // MIs[0] base
37420 /* 104464 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37421 /* 104468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37422 /* 104472 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37423 /* 104476 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37424 /* 104480 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37425 /* 104484 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37426 /* 104488 */ // (intrinsic_w_chain:{ *:[v4i32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37427 /* 104488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37428 /* 104491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37429 /* 104493 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37430 /* 104495 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37431 /* 104497 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37432 /* 104501 */ GIR_RootConstrainSelectedInstOperands,
37433 /* 104502 */ // GIR_Coverage, 5502,
37434 /* 104502 */ GIR_EraseRootFromParent_Done,
37435 /* 104503 */ // Label 1922: @104503
37436 /* 104503 */ GIM_Try, /*On fail goto*//*Label 1923*/ GIMT_Encode4(104571), // Rule ID 5503 //
37437 /* 104508 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37438 /* 104513 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37439 /* 104516 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37440 /* 104519 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37441 /* 104522 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37442 /* 104525 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37443 /* 104528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37444 /* 104532 */ // MIs[0] base
37445 /* 104532 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37446 /* 104536 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37447 /* 104540 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37448 /* 104544 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37449 /* 104548 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37450 /* 104552 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37451 /* 104556 */ // (intrinsic_w_chain:{ *:[v4i32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37452 /* 104556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37453 /* 104559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37454 /* 104561 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37455 /* 104563 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37456 /* 104565 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37457 /* 104569 */ GIR_RootConstrainSelectedInstOperands,
37458 /* 104570 */ // GIR_Coverage, 5503,
37459 /* 104570 */ GIR_EraseRootFromParent_Done,
37460 /* 104571 */ // Label 1923: @104571
37461 /* 104571 */ GIM_Try, /*On fail goto*//*Label 1924*/ GIMT_Encode4(104639), // Rule ID 5506 //
37462 /* 104576 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37463 /* 104581 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37464 /* 104584 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37465 /* 104587 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37466 /* 104590 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37467 /* 104593 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37468 /* 104596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37469 /* 104600 */ // MIs[0] base
37470 /* 104600 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37471 /* 104604 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37472 /* 104608 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37473 /* 104612 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37474 /* 104616 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37475 /* 104620 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37476 /* 104624 */ // (intrinsic_w_chain:{ *:[v4i32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37477 /* 104624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37478 /* 104627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37479 /* 104629 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37480 /* 104631 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37481 /* 104633 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37482 /* 104637 */ GIR_RootConstrainSelectedInstOperands,
37483 /* 104638 */ // GIR_Coverage, 5506,
37484 /* 104638 */ GIR_EraseRootFromParent_Done,
37485 /* 104639 */ // Label 1924: @104639
37486 /* 104639 */ GIM_Try, /*On fail goto*//*Label 1925*/ GIMT_Encode4(104707), // Rule ID 5507 //
37487 /* 104644 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37488 /* 104649 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37489 /* 104652 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37490 /* 104655 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37491 /* 104658 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37492 /* 104661 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37493 /* 104664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37494 /* 104668 */ // MIs[0] base
37495 /* 104668 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37496 /* 104672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37497 /* 104676 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37498 /* 104680 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37499 /* 104684 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37500 /* 104688 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37501 /* 104692 */ // (intrinsic_w_chain:{ *:[v4i32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37502 /* 104692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37503 /* 104695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37504 /* 104697 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37505 /* 104699 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37506 /* 104701 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37507 /* 104705 */ GIR_RootConstrainSelectedInstOperands,
37508 /* 104706 */ // GIR_Coverage, 5507,
37509 /* 104706 */ GIR_EraseRootFromParent_Done,
37510 /* 104707 */ // Label 1925: @104707
37511 /* 104707 */ GIM_Try, /*On fail goto*//*Label 1926*/ GIMT_Encode4(104775), // Rule ID 5510 //
37512 /* 104712 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37513 /* 104717 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37514 /* 104720 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37515 /* 104723 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37516 /* 104726 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37517 /* 104729 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37518 /* 104732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37519 /* 104736 */ // MIs[0] base
37520 /* 104736 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37521 /* 104740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37522 /* 104744 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37523 /* 104748 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37524 /* 104752 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37525 /* 104756 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37526 /* 104760 */ // (intrinsic_w_chain:{ *:[v4i32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37527 /* 104760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37528 /* 104763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37529 /* 104765 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37530 /* 104767 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37531 /* 104769 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37532 /* 104773 */ GIR_RootConstrainSelectedInstOperands,
37533 /* 104774 */ // GIR_Coverage, 5510,
37534 /* 104774 */ GIR_EraseRootFromParent_Done,
37535 /* 104775 */ // Label 1926: @104775
37536 /* 104775 */ GIM_Try, /*On fail goto*//*Label 1927*/ GIMT_Encode4(104843), // Rule ID 5511 //
37537 /* 104780 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37538 /* 104785 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37539 /* 104788 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37540 /* 104791 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37541 /* 104794 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37542 /* 104797 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37543 /* 104800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37544 /* 104804 */ // MIs[0] base
37545 /* 104804 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37546 /* 104808 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37547 /* 104812 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37548 /* 104816 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37549 /* 104820 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37550 /* 104824 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37551 /* 104828 */ // (intrinsic_w_chain:{ *:[v4i32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37552 /* 104828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37553 /* 104831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37554 /* 104833 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37555 /* 104835 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37556 /* 104837 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37557 /* 104841 */ GIR_RootConstrainSelectedInstOperands,
37558 /* 104842 */ // GIR_Coverage, 5511,
37559 /* 104842 */ GIR_EraseRootFromParent_Done,
37560 /* 104843 */ // Label 1927: @104843
37561 /* 104843 */ GIM_Try, /*On fail goto*//*Label 1928*/ GIMT_Encode4(104911), // Rule ID 5514 //
37562 /* 104848 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37563 /* 104853 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37564 /* 104856 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37565 /* 104859 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37566 /* 104862 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37567 /* 104865 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37568 /* 104868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37569 /* 104872 */ // MIs[0] base
37570 /* 104872 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37571 /* 104876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37572 /* 104880 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37573 /* 104884 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37574 /* 104888 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37575 /* 104892 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37576 /* 104896 */ // (intrinsic_w_chain:{ *:[v4i32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37577 /* 104896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37578 /* 104899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37579 /* 104901 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37580 /* 104903 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37581 /* 104905 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37582 /* 104909 */ GIR_RootConstrainSelectedInstOperands,
37583 /* 104910 */ // GIR_Coverage, 5514,
37584 /* 104910 */ GIR_EraseRootFromParent_Done,
37585 /* 104911 */ // Label 1928: @104911
37586 /* 104911 */ GIM_Try, /*On fail goto*//*Label 1929*/ GIMT_Encode4(104979), // Rule ID 5515 //
37587 /* 104916 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37588 /* 104921 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37589 /* 104924 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37590 /* 104927 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37591 /* 104930 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37592 /* 104933 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37593 /* 104936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37594 /* 104940 */ // MIs[0] base
37595 /* 104940 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37596 /* 104944 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37597 /* 104948 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37598 /* 104952 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37599 /* 104956 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37600 /* 104960 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37601 /* 104964 */ // (intrinsic_w_chain:{ *:[v4i32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37602 /* 104964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37603 /* 104967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37604 /* 104969 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37605 /* 104971 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37606 /* 104973 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37607 /* 104977 */ GIR_RootConstrainSelectedInstOperands,
37608 /* 104978 */ // GIR_Coverage, 5515,
37609 /* 104978 */ GIR_EraseRootFromParent_Done,
37610 /* 104979 */ // Label 1929: @104979
37611 /* 104979 */ GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(105047), // Rule ID 5518 //
37612 /* 104984 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37613 /* 104989 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37614 /* 104992 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37615 /* 104995 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37616 /* 104998 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37617 /* 105001 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37618 /* 105004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37619 /* 105008 */ // MIs[0] base
37620 /* 105008 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37621 /* 105012 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37622 /* 105016 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37623 /* 105020 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37624 /* 105024 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37625 /* 105028 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37626 /* 105032 */ // (intrinsic_w_chain:{ *:[v4f32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37627 /* 105032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37628 /* 105035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37629 /* 105037 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37630 /* 105039 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37631 /* 105041 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37632 /* 105045 */ GIR_RootConstrainSelectedInstOperands,
37633 /* 105046 */ // GIR_Coverage, 5518,
37634 /* 105046 */ GIR_EraseRootFromParent_Done,
37635 /* 105047 */ // Label 1930: @105047
37636 /* 105047 */ GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(105115), // Rule ID 5519 //
37637 /* 105052 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37638 /* 105057 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37639 /* 105060 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37640 /* 105063 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37641 /* 105066 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37642 /* 105069 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37643 /* 105072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37644 /* 105076 */ // MIs[0] base
37645 /* 105076 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37646 /* 105080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37647 /* 105084 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37648 /* 105088 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37649 /* 105092 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37650 /* 105096 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37651 /* 105100 */ // (intrinsic_w_chain:{ *:[v4f32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37652 /* 105100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37653 /* 105103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37654 /* 105105 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37655 /* 105107 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37656 /* 105109 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37657 /* 105113 */ GIR_RootConstrainSelectedInstOperands,
37658 /* 105114 */ // GIR_Coverage, 5519,
37659 /* 105114 */ GIR_EraseRootFromParent_Done,
37660 /* 105115 */ // Label 1931: @105115
37661 /* 105115 */ GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(105183), // Rule ID 5522 //
37662 /* 105120 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37663 /* 105125 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37664 /* 105128 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37665 /* 105131 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37666 /* 105134 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37667 /* 105137 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37668 /* 105140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37669 /* 105144 */ // MIs[0] base
37670 /* 105144 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37671 /* 105148 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37672 /* 105152 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37673 /* 105156 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37674 /* 105160 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37675 /* 105164 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37676 /* 105168 */ // (intrinsic_w_chain:{ *:[v4f32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37677 /* 105168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37678 /* 105171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37679 /* 105173 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37680 /* 105175 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37681 /* 105177 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37682 /* 105181 */ GIR_RootConstrainSelectedInstOperands,
37683 /* 105182 */ // GIR_Coverage, 5522,
37684 /* 105182 */ GIR_EraseRootFromParent_Done,
37685 /* 105183 */ // Label 1932: @105183
37686 /* 105183 */ GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(105251), // Rule ID 5523 //
37687 /* 105188 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37688 /* 105193 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37689 /* 105196 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37690 /* 105199 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37691 /* 105202 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37692 /* 105205 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37693 /* 105208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37694 /* 105212 */ // MIs[0] base
37695 /* 105212 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37696 /* 105216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37697 /* 105220 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37698 /* 105224 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37699 /* 105228 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37700 /* 105232 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37701 /* 105236 */ // (intrinsic_w_chain:{ *:[v4f32] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37702 /* 105236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37703 /* 105239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37704 /* 105241 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37705 /* 105243 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37706 /* 105245 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37707 /* 105249 */ GIR_RootConstrainSelectedInstOperands,
37708 /* 105250 */ // GIR_Coverage, 5523,
37709 /* 105250 */ GIR_EraseRootFromParent_Done,
37710 /* 105251 */ // Label 1933: @105251
37711 /* 105251 */ GIM_Try, /*On fail goto*//*Label 1934*/ GIMT_Encode4(105319), // Rule ID 5526 //
37712 /* 105256 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37713 /* 105261 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
37714 /* 105264 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
37715 /* 105267 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37716 /* 105270 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37717 /* 105273 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37718 /* 105276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37719 /* 105280 */ // MIs[0] base
37720 /* 105280 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37721 /* 105284 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37722 /* 105288 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37723 /* 105292 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37724 /* 105296 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37725 /* 105300 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37726 /* 105304 */ // (intrinsic_w_chain:{ *:[v2i64] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37727 /* 105304 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
37728 /* 105307 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37729 /* 105309 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37730 /* 105311 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37731 /* 105313 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37732 /* 105317 */ GIR_RootConstrainSelectedInstOperands,
37733 /* 105318 */ // GIR_Coverage, 5526,
37734 /* 105318 */ GIR_EraseRootFromParent_Done,
37735 /* 105319 */ // Label 1934: @105319
37736 /* 105319 */ GIM_Try, /*On fail goto*//*Label 1935*/ GIMT_Encode4(105387), // Rule ID 5527 //
37737 /* 105324 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37738 /* 105329 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
37739 /* 105332 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
37740 /* 105335 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37741 /* 105338 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37742 /* 105341 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37743 /* 105344 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37744 /* 105348 */ // MIs[0] base
37745 /* 105348 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37746 /* 105352 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37747 /* 105356 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37748 /* 105360 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37749 /* 105364 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
37750 /* 105368 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37751 /* 105372 */ // (intrinsic_w_chain:{ *:[v2i64] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37752 /* 105372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
37753 /* 105375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37754 /* 105377 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37755 /* 105379 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37756 /* 105381 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37757 /* 105385 */ GIR_RootConstrainSelectedInstOperands,
37758 /* 105386 */ // GIR_Coverage, 5527,
37759 /* 105386 */ GIR_EraseRootFromParent_Done,
37760 /* 105387 */ // Label 1935: @105387
37761 /* 105387 */ GIM_Try, /*On fail goto*//*Label 1936*/ GIMT_Encode4(105455), // Rule ID 5530 //
37762 /* 105392 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37763 /* 105397 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
37764 /* 105400 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
37765 /* 105403 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37766 /* 105406 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37767 /* 105409 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37768 /* 105412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37769 /* 105416 */ // MIs[0] base
37770 /* 105416 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37771 /* 105420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37772 /* 105424 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37773 /* 105428 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37774 /* 105432 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37775 /* 105436 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37776 /* 105440 */ // (intrinsic_w_chain:{ *:[v2i64] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37777 /* 105440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
37778 /* 105443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37779 /* 105445 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37780 /* 105447 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37781 /* 105449 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37782 /* 105453 */ GIR_RootConstrainSelectedInstOperands,
37783 /* 105454 */ // GIR_Coverage, 5530,
37784 /* 105454 */ GIR_EraseRootFromParent_Done,
37785 /* 105455 */ // Label 1936: @105455
37786 /* 105455 */ GIM_Try, /*On fail goto*//*Label 1937*/ GIMT_Encode4(105523), // Rule ID 5531 //
37787 /* 105460 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37788 /* 105465 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
37789 /* 105468 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
37790 /* 105471 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37791 /* 105474 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37792 /* 105477 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37793 /* 105480 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37794 /* 105484 */ // MIs[0] base
37795 /* 105484 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37796 /* 105488 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37797 /* 105492 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37798 /* 105496 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37799 /* 105500 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
37800 /* 105504 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37801 /* 105508 */ // (intrinsic_w_chain:{ *:[v2i64] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37802 /* 105508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
37803 /* 105511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37804 /* 105513 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37805 /* 105515 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37806 /* 105517 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37807 /* 105521 */ GIR_RootConstrainSelectedInstOperands,
37808 /* 105522 */ // GIR_Coverage, 5531,
37809 /* 105522 */ GIR_EraseRootFromParent_Done,
37810 /* 105523 */ // Label 1937: @105523
37811 /* 105523 */ GIM_Try, /*On fail goto*//*Label 1938*/ GIMT_Encode4(105591), // Rule ID 5534 //
37812 /* 105528 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37813 /* 105533 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
37814 /* 105536 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
37815 /* 105539 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37816 /* 105542 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37817 /* 105545 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37818 /* 105548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37819 /* 105552 */ // MIs[0] base
37820 /* 105552 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37821 /* 105556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37822 /* 105560 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37823 /* 105564 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37824 /* 105568 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37825 /* 105572 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37826 /* 105576 */ // (intrinsic_w_chain:{ *:[v2i64] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37827 /* 105576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
37828 /* 105579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37829 /* 105581 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37830 /* 105583 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37831 /* 105585 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37832 /* 105589 */ GIR_RootConstrainSelectedInstOperands,
37833 /* 105590 */ // GIR_Coverage, 5534,
37834 /* 105590 */ GIR_EraseRootFromParent_Done,
37835 /* 105591 */ // Label 1938: @105591
37836 /* 105591 */ GIM_Try, /*On fail goto*//*Label 1939*/ GIMT_Encode4(105659), // Rule ID 5535 //
37837 /* 105596 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37838 /* 105601 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
37839 /* 105604 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
37840 /* 105607 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37841 /* 105610 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37842 /* 105613 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37843 /* 105616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37844 /* 105620 */ // MIs[0] base
37845 /* 105620 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37846 /* 105624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37847 /* 105628 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37848 /* 105632 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37849 /* 105636 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
37850 /* 105640 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37851 /* 105644 */ // (intrinsic_w_chain:{ *:[v2i64] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37852 /* 105644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
37853 /* 105647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37854 /* 105649 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37855 /* 105651 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37856 /* 105653 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37857 /* 105657 */ GIR_RootConstrainSelectedInstOperands,
37858 /* 105658 */ // GIR_Coverage, 5535,
37859 /* 105658 */ GIR_EraseRootFromParent_Done,
37860 /* 105659 */ // Label 1939: @105659
37861 /* 105659 */ GIM_Try, /*On fail goto*//*Label 1940*/ GIMT_Encode4(105727), // Rule ID 5538 //
37862 /* 105664 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37863 /* 105669 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
37864 /* 105672 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
37865 /* 105675 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37866 /* 105678 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37867 /* 105681 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37868 /* 105684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37869 /* 105688 */ // MIs[0] base
37870 /* 105688 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37871 /* 105692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37872 /* 105696 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37873 /* 105700 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37874 /* 105704 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37875 /* 105708 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37876 /* 105712 */ // (intrinsic_w_chain:{ *:[v2i64] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37877 /* 105712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
37878 /* 105715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37879 /* 105717 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37880 /* 105719 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37881 /* 105721 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37882 /* 105725 */ GIR_RootConstrainSelectedInstOperands,
37883 /* 105726 */ // GIR_Coverage, 5538,
37884 /* 105726 */ GIR_EraseRootFromParent_Done,
37885 /* 105727 */ // Label 1940: @105727
37886 /* 105727 */ GIM_Try, /*On fail goto*//*Label 1941*/ GIMT_Encode4(105795), // Rule ID 5539 //
37887 /* 105732 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37888 /* 105737 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
37889 /* 105740 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
37890 /* 105743 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37891 /* 105746 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37892 /* 105749 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37893 /* 105752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37894 /* 105756 */ // MIs[0] base
37895 /* 105756 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37896 /* 105760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37897 /* 105764 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37898 /* 105768 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
37899 /* 105772 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
37900 /* 105776 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37901 /* 105780 */ // (intrinsic_w_chain:{ *:[v2i64] } 3895:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
37902 /* 105780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
37903 /* 105783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37904 /* 105785 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37905 /* 105787 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37906 /* 105789 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37907 /* 105793 */ GIR_RootConstrainSelectedInstOperands,
37908 /* 105794 */ // GIR_Coverage, 5539,
37909 /* 105794 */ GIR_EraseRootFromParent_Done,
37910 /* 105795 */ // Label 1941: @105795
37911 /* 105795 */ GIM_Try, /*On fail goto*//*Label 1942*/ GIMT_Encode4(105860), // Rule ID 255 //
37912 /* 105800 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
37913 /* 105803 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr),
37914 /* 105808 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
37915 /* 105811 */ // MIs[0] cop
37916 /* 105811 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37917 /* 105814 */ // MIs[0] opc1
37918 /* 105814 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37919 /* 105817 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37920 /* 105821 */ // MIs[0] CRn
37921 /* 105821 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
37922 /* 105824 */ // MIs[0] CRm
37923 /* 105824 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37924 /* 105827 */ // MIs[0] opc2
37925 /* 105827 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
37926 /* 105830 */ // (intrinsic_void 3760:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
37927 /* 105830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR),
37928 /* 105833 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
37929 /* 105835 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
37930 /* 105837 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
37931 /* 105839 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
37932 /* 105841 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
37933 /* 105843 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
37934 /* 105845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37935 /* 105848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37936 /* 105854 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37937 /* 105858 */ GIR_RootConstrainSelectedInstOperands,
37938 /* 105859 */ // GIR_Coverage, 255,
37939 /* 105859 */ GIR_EraseRootFromParent_Done,
37940 /* 105860 */ // Label 1942: @105860
37941 /* 105860 */ GIM_Try, /*On fail goto*//*Label 1943*/ GIMT_Encode4(105916), // Rule ID 256 //
37942 /* 105865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8),
37943 /* 105868 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2),
37944 /* 105873 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
37945 /* 105876 */ // MIs[0] cop
37946 /* 105876 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37947 /* 105879 */ // MIs[0] opc1
37948 /* 105879 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37949 /* 105882 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37950 /* 105886 */ // MIs[0] CRn
37951 /* 105886 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
37952 /* 105889 */ // MIs[0] CRm
37953 /* 105889 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37954 /* 105892 */ // MIs[0] opc2
37955 /* 105892 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
37956 /* 105895 */ // (intrinsic_void 3761:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
37957 /* 105895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR2),
37958 /* 105898 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
37959 /* 105900 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
37960 /* 105902 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
37961 /* 105904 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
37962 /* 105906 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
37963 /* 105908 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
37964 /* 105910 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37965 /* 105914 */ GIR_RootConstrainSelectedInstOperands,
37966 /* 105915 */ // GIR_Coverage, 256,
37967 /* 105915 */ GIR_EraseRootFromParent_Done,
37968 /* 105916 */ // Label 1943: @105916
37969 /* 105916 */ GIM_Try, /*On fail goto*//*Label 1944*/ GIMT_Encode4(105981), // Rule ID 593 //
37970 /* 105921 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
37971 /* 105924 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr),
37972 /* 105929 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
37973 /* 105932 */ // MIs[0] cop
37974 /* 105932 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37975 /* 105935 */ // MIs[0] opc1
37976 /* 105935 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37977 /* 105938 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37978 /* 105942 */ // MIs[0] CRn
37979 /* 105942 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
37980 /* 105945 */ // MIs[0] CRm
37981 /* 105945 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37982 /* 105948 */ // MIs[0] opc2
37983 /* 105948 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
37984 /* 105951 */ // (intrinsic_void 3760:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
37985 /* 105951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR),
37986 /* 105954 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
37987 /* 105956 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
37988 /* 105958 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
37989 /* 105960 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
37990 /* 105962 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
37991 /* 105964 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
37992 /* 105966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37993 /* 105969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37994 /* 105975 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37995 /* 105979 */ GIR_RootConstrainSelectedInstOperands,
37996 /* 105980 */ // GIR_Coverage, 593,
37997 /* 105980 */ GIR_EraseRootFromParent_Done,
37998 /* 105981 */ // Label 1944: @105981
37999 /* 105981 */ GIM_Try, /*On fail goto*//*Label 1945*/ GIMT_Encode4(106046), // Rule ID 594 //
38000 /* 105986 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8),
38001 /* 105989 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2),
38002 /* 105994 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
38003 /* 105997 */ // MIs[0] cop
38004 /* 105997 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
38005 /* 106000 */ // MIs[0] opc1
38006 /* 106000 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
38007 /* 106003 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38008 /* 106007 */ // MIs[0] CRn
38009 /* 106007 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
38010 /* 106010 */ // MIs[0] CRm
38011 /* 106010 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
38012 /* 106013 */ // MIs[0] opc2
38013 /* 106013 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
38014 /* 106016 */ // (intrinsic_void 3761:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
38015 /* 106016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR2),
38016 /* 106019 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
38017 /* 106021 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
38018 /* 106023 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
38019 /* 106025 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
38020 /* 106027 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
38021 /* 106029 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
38022 /* 106031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38023 /* 106034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38024 /* 106040 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38025 /* 106044 */ GIR_RootConstrainSelectedInstOperands,
38026 /* 106045 */ // GIR_Coverage, 594,
38027 /* 106045 */ GIR_EraseRootFromParent_Done,
38028 /* 106046 */ // Label 1945: @106046
38029 /* 106046 */ GIM_Reject,
38030 /* 106047 */ // Label 1895: @106047
38031 /* 106047 */ GIM_Reject,
38032 /* 106048 */ // Label 23: @106048
38033 /* 106048 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 1949*/ GIMT_Encode4(106189),
38034 /* 106059 */ /*GILLT_v8s16*//*Label 1946*/ GIMT_Encode4(106075), GIMT_Encode4(0),
38035 /* 106067 */ /*GILLT_v4s32*//*Label 1947*/ GIMT_Encode4(106113),
38036 /* 106071 */ /*GILLT_v2s64*//*Label 1948*/ GIMT_Encode4(106151),
38037 /* 106075 */ // Label 1946: @106075
38038 /* 106075 */ GIM_Try, /*On fail goto*//*Label 1950*/ GIMT_Encode4(106112), // Rule ID 3041 //
38039 /* 106080 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38040 /* 106083 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
38041 /* 106086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38042 /* 106090 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38043 /* 106094 */ // (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
38044 /* 106094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16),
38045 /* 106097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38046 /* 106099 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38047 /* 106101 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38048 /* 106104 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38049 /* 106110 */ GIR_RootConstrainSelectedInstOperands,
38050 /* 106111 */ // GIR_Coverage, 3041,
38051 /* 106111 */ GIR_EraseRootFromParent_Done,
38052 /* 106112 */ // Label 1950: @106112
38053 /* 106112 */ GIM_Reject,
38054 /* 106113 */ // Label 1947: @106113
38055 /* 106113 */ GIM_Try, /*On fail goto*//*Label 1951*/ GIMT_Encode4(106150), // Rule ID 3042 //
38056 /* 106118 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38057 /* 106121 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
38058 /* 106124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38059 /* 106128 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38060 /* 106132 */ // (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
38061 /* 106132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32),
38062 /* 106135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38063 /* 106137 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38064 /* 106139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38065 /* 106142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38066 /* 106148 */ GIR_RootConstrainSelectedInstOperands,
38067 /* 106149 */ // GIR_Coverage, 3042,
38068 /* 106149 */ GIR_EraseRootFromParent_Done,
38069 /* 106150 */ // Label 1951: @106150
38070 /* 106150 */ GIM_Reject,
38071 /* 106151 */ // Label 1948: @106151
38072 /* 106151 */ GIM_Try, /*On fail goto*//*Label 1952*/ GIMT_Encode4(106188), // Rule ID 3043 //
38073 /* 106156 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38074 /* 106159 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
38075 /* 106162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38076 /* 106166 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38077 /* 106170 */ // (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
38078 /* 106170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64),
38079 /* 106173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38080 /* 106175 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38081 /* 106177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38082 /* 106180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38083 /* 106186 */ GIR_RootConstrainSelectedInstOperands,
38084 /* 106187 */ // GIR_Coverage, 3043,
38085 /* 106187 */ GIR_EraseRootFromParent_Done,
38086 /* 106188 */ // Label 1952: @106188
38087 /* 106188 */ GIM_Reject,
38088 /* 106189 */ // Label 1949: @106189
38089 /* 106189 */ GIM_Reject,
38090 /* 106190 */ // Label 24: @106190
38091 /* 106190 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1956*/ GIMT_Encode4(106335),
38092 /* 106201 */ /*GILLT_v8s8*//*Label 1953*/ GIMT_Encode4(106221), GIMT_Encode4(0),
38093 /* 106209 */ /*GILLT_v4s16*//*Label 1954*/ GIMT_Encode4(106259), GIMT_Encode4(0),
38094 /* 106217 */ /*GILLT_v2s32*//*Label 1955*/ GIMT_Encode4(106297),
38095 /* 106221 */ // Label 1953: @106221
38096 /* 106221 */ GIM_Try, /*On fail goto*//*Label 1957*/ GIMT_Encode4(106258), // Rule ID 1748 //
38097 /* 106226 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38098 /* 106229 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
38099 /* 106232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38100 /* 106236 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38101 /* 106240 */ // (trunc:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) => (VMOVNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
38102 /* 106240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv8i8),
38103 /* 106243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38104 /* 106245 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38105 /* 106247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38106 /* 106250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38107 /* 106256 */ GIR_RootConstrainSelectedInstOperands,
38108 /* 106257 */ // GIR_Coverage, 1748,
38109 /* 106257 */ GIR_EraseRootFromParent_Done,
38110 /* 106258 */ // Label 1957: @106258
38111 /* 106258 */ GIM_Reject,
38112 /* 106259 */ // Label 1954: @106259
38113 /* 106259 */ GIM_Try, /*On fail goto*//*Label 1958*/ GIMT_Encode4(106296), // Rule ID 1749 //
38114 /* 106264 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38115 /* 106267 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
38116 /* 106270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38117 /* 106274 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38118 /* 106278 */ // (trunc:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) => (VMOVNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
38119 /* 106278 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv4i16),
38120 /* 106281 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38121 /* 106283 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38122 /* 106285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38123 /* 106288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38124 /* 106294 */ GIR_RootConstrainSelectedInstOperands,
38125 /* 106295 */ // GIR_Coverage, 1749,
38126 /* 106295 */ GIR_EraseRootFromParent_Done,
38127 /* 106296 */ // Label 1958: @106296
38128 /* 106296 */ GIM_Reject,
38129 /* 106297 */ // Label 1955: @106297
38130 /* 106297 */ GIM_Try, /*On fail goto*//*Label 1959*/ GIMT_Encode4(106334), // Rule ID 1750 //
38131 /* 106302 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38132 /* 106305 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
38133 /* 106308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38134 /* 106312 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38135 /* 106316 */ // (trunc:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) => (VMOVNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
38136 /* 106316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv2i32),
38137 /* 106319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38138 /* 106321 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38139 /* 106323 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38140 /* 106326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38141 /* 106332 */ GIR_RootConstrainSelectedInstOperands,
38142 /* 106333 */ // GIR_Coverage, 1750,
38143 /* 106333 */ GIR_EraseRootFromParent_Done,
38144 /* 106334 */ // Label 1959: @106334
38145 /* 106334 */ GIM_Reject,
38146 /* 106335 */ // Label 1956: @106335
38147 /* 106335 */ GIM_Reject,
38148 /* 106336 */ // Label 25: @106336
38149 /* 106336 */ GIM_Try, /*On fail goto*//*Label 1960*/ GIMT_Encode4(106656),
38150 /* 106341 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
38151 /* 106344 */ GIM_Try, /*On fail goto*//*Label 1961*/ GIMT_Encode4(106385), // Rule ID 403 //
38152 /* 106349 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38153 /* 106352 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
38154 /* 106356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38155 /* 106360 */ // MIs[0] Operand 1
38156 /* 106360 */ // No operand predicates
38157 /* 106360 */ // (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm => (t2MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38158 /* 106360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
38159 /* 106363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38160 /* 106365 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38161 /* 106368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38162 /* 106371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38163 /* 106377 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38164 /* 106383 */ GIR_RootConstrainSelectedInstOperands,
38165 /* 106384 */ // GIR_Coverage, 403,
38166 /* 106384 */ GIR_EraseRootFromParent_Done,
38167 /* 106385 */ // Label 1961: @106385
38168 /* 106385 */ GIM_Try, /*On fail goto*//*Label 1962*/ GIMT_Encode4(106426), // Rule ID 56 //
38169 /* 106390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
38170 /* 106393 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
38171 /* 106397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38172 /* 106401 */ // MIs[0] Operand 1
38173 /* 106401 */ // No operand predicates
38174 /* 106401 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm => (MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38175 /* 106401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi),
38176 /* 106404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38177 /* 106406 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38178 /* 106409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38179 /* 106412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38180 /* 106418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38181 /* 106424 */ GIR_RootConstrainSelectedInstOperands,
38182 /* 106425 */ // GIR_Coverage, 56,
38183 /* 106425 */ GIR_EraseRootFromParent_Done,
38184 /* 106426 */ // Label 1962: @106426
38185 /* 106426 */ GIM_Try, /*On fail goto*//*Label 1963*/ GIMT_Encode4(106461), // Rule ID 57 //
38186 /* 106431 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM),
38187 /* 106434 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
38188 /* 106438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38189 /* 106442 */ // MIs[0] Operand 1
38190 /* 106442 */ // No operand predicates
38191 /* 106442 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38192 /* 106442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi16),
38193 /* 106445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38194 /* 106447 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38195 /* 106450 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38196 /* 106453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38197 /* 106459 */ GIR_RootConstrainSelectedInstOperands,
38198 /* 106460 */ // GIR_Coverage, 57,
38199 /* 106460 */ GIR_EraseRootFromParent_Done,
38200 /* 106461 */ // Label 1963: @106461
38201 /* 106461 */ GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(106504), // Rule ID 167 //
38202 /* 106466 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
38203 /* 106469 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not),
38204 /* 106473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38205 /* 106477 */ // MIs[0] Operand 1
38206 /* 106477 */ // No operand predicates
38207 /* 106477 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm => (MVNi:{ *:[i32] } (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm))
38208 /* 106477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNi),
38209 /* 106480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38210 /* 106482 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm
38211 /* 106487 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38212 /* 106490 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38213 /* 106496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38214 /* 106502 */ GIR_RootConstrainSelectedInstOperands,
38215 /* 106503 */ // GIR_Coverage, 167,
38216 /* 106503 */ GIR_EraseRootFromParent_Done,
38217 /* 106504 */ // Label 1964: @106504
38218 /* 106504 */ GIM_Try, /*On fail goto*//*Label 1965*/ GIMT_Encode4(106530), // Rule ID 267 //
38219 /* 106509 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
38220 /* 106512 */ GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_arm_i32imm),
38221 /* 106516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38222 /* 106520 */ // MIs[0] Operand 1
38223 /* 106520 */ // No operand predicates
38224 /* 106520 */ // (imm:{ *:[i32] })<<P:Predicate_arm_i32imm>>:$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
38225 /* 106520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi32imm),
38226 /* 106523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38227 /* 106525 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
38228 /* 106528 */ GIR_RootConstrainSelectedInstOperands,
38229 /* 106529 */ // GIR_Coverage, 267,
38230 /* 106529 */ GIR_EraseRootFromParent_Done,
38231 /* 106530 */ // Label 1965: @106530
38232 /* 106530 */ GIM_Try, /*On fail goto*//*Label 1966*/ GIMT_Encode4(106571), // Rule ID 321 //
38233 /* 106535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
38234 /* 106538 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr),
38235 /* 106542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38236 /* 106546 */ // MIs[0] Operand 1
38237 /* 106546 */ // No operand predicates
38238 /* 106546 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8 => (tMOVi8:{ *:[i32] } (imm:{ *:[i32] }):$imm8)
38239 /* 106546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
38240 /* 106549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38241 /* 106551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
38242 /* 106557 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm8
38243 /* 106560 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38244 /* 106563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38245 /* 106569 */ GIR_RootConstrainSelectedInstOperands,
38246 /* 106570 */ // GIR_Coverage, 321,
38247 /* 106570 */ GIR_EraseRootFromParent_Done,
38248 /* 106571 */ // Label 1966: @106571
38249 /* 106571 */ GIM_Try, /*On fail goto*//*Label 1967*/ GIMT_Encode4(106606), // Rule ID 404 //
38250 /* 106576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb),
38251 /* 106579 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
38252 /* 106583 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38253 /* 106587 */ // MIs[0] Operand 1
38254 /* 106587 */ // No operand predicates
38255 /* 106587 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (t2MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38256 /* 106587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16),
38257 /* 106590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38258 /* 106592 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38259 /* 106595 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38260 /* 106598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38261 /* 106604 */ GIR_RootConstrainSelectedInstOperands,
38262 /* 106605 */ // GIR_Coverage, 404,
38263 /* 106605 */ GIR_EraseRootFromParent_Done,
38264 /* 106606 */ // Label 1967: @106606
38265 /* 106606 */ GIM_Try, /*On fail goto*//*Label 1968*/ GIMT_Encode4(106655),
38266 /* 106611 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38267 /* 106615 */ GIM_Try, /*On fail goto*//*Label 1969*/ GIMT_Encode4(106636), // Rule ID 352 //
38268 /* 106620 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only),
38269 /* 106623 */ // MIs[0] Operand 1
38270 /* 106623 */ // No operand predicates
38271 /* 106623 */ // (imm:{ *:[i32] }):$src => (tMOVi32imm:{ *:[i32] }:{ *:[i32] } (imm:{ *:[i32] }):$src)
38272 /* 106623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi32imm),
38273 /* 106626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38274 /* 106628 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
38275 /* 106631 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::CPSR*/0,
38276 /* 106634 */ GIR_RootConstrainSelectedInstOperands,
38277 /* 106635 */ // GIR_Coverage, 352,
38278 /* 106635 */ GIR_EraseRootFromParent_Done,
38279 /* 106636 */ // Label 1969: @106636
38280 /* 106636 */ GIM_Try, /*On fail goto*//*Label 1970*/ GIMT_Encode4(106654), // Rule ID 581 //
38281 /* 106641 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_UseMovt),
38282 /* 106644 */ // MIs[0] Operand 1
38283 /* 106644 */ // No operand predicates
38284 /* 106644 */ // (imm:{ *:[i32] }):$src => (t2MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
38285 /* 106644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm),
38286 /* 106647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38287 /* 106649 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
38288 /* 106652 */ GIR_RootConstrainSelectedInstOperands,
38289 /* 106653 */ // GIR_Coverage, 581,
38290 /* 106653 */ GIR_EraseRootFromParent_Done,
38291 /* 106654 */ // Label 1970: @106654
38292 /* 106654 */ GIM_Reject,
38293 /* 106655 */ // Label 1968: @106655
38294 /* 106655 */ GIM_Reject,
38295 /* 106656 */ // Label 1960: @106656
38296 /* 106656 */ GIM_Reject,
38297 /* 106657 */ // Label 26: @106657
38298 /* 106657 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1973*/ GIMT_Encode4(106752),
38299 /* 106668 */ /*GILLT_s32*//*Label 1971*/ GIMT_Encode4(106676),
38300 /* 106672 */ /*GILLT_s64*//*Label 1972*/ GIMT_Encode4(106714),
38301 /* 106676 */ // Label 1971: @106676
38302 /* 106676 */ GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(106713), // Rule ID 848 //
38303 /* 106681 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP3),
38304 /* 106684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38305 /* 106688 */ // MIs[0] Operand 1
38306 /* 106688 */ // No operand predicates
38307 /* 106688 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f32imm),
38308 /* 106692 */ // (fpimm:{ *:[f32] })<<P:Predicate_vfp_f32imm>><<X:vfp_f32imm_xform>>:$imm => (FCONSTS:{ *:[f32] } (vfp_f32imm_xform:{ *:[f32] } (fpimm:{ *:[f32] }):$imm))
38309 /* 106692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTS),
38310 /* 106695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
38311 /* 106697 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF32Imm), // imm
38312 /* 106702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38313 /* 106705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38314 /* 106711 */ GIR_RootConstrainSelectedInstOperands,
38315 /* 106712 */ // GIR_Coverage, 848,
38316 /* 106712 */ GIR_EraseRootFromParent_Done,
38317 /* 106713 */ // Label 1974: @106713
38318 /* 106713 */ GIM_Reject,
38319 /* 106714 */ // Label 1972: @106714
38320 /* 106714 */ GIM_Try, /*On fail goto*//*Label 1975*/ GIMT_Encode4(106751), // Rule ID 847 //
38321 /* 106719 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP3),
38322 /* 106722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38323 /* 106726 */ // MIs[0] Operand 1
38324 /* 106726 */ // No operand predicates
38325 /* 106726 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f64imm),
38326 /* 106730 */ // (fpimm:{ *:[f64] })<<P:Predicate_vfp_f64imm>><<X:vfp_f64imm_xform>>:$imm => (FCONSTD:{ *:[f64] } (vfp_f64imm_xform:{ *:[f64] } (fpimm:{ *:[f64] }):$imm))
38327 /* 106730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTD),
38328 /* 106733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
38329 /* 106735 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF64Imm), // imm
38330 /* 106740 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38331 /* 106743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38332 /* 106749 */ GIR_RootConstrainSelectedInstOperands,
38333 /* 106750 */ // GIR_Coverage, 847,
38334 /* 106750 */ GIR_EraseRootFromParent_Done,
38335 /* 106751 */ // Label 1975: @106751
38336 /* 106751 */ GIM_Reject,
38337 /* 106752 */ // Label 1973: @106752
38338 /* 106752 */ GIM_Reject,
38339 /* 106753 */ // Label 27: @106753
38340 /* 106753 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 1979*/ GIMT_Encode4(106894),
38341 /* 106764 */ /*GILLT_v8s16*//*Label 1976*/ GIMT_Encode4(106780), GIMT_Encode4(0),
38342 /* 106772 */ /*GILLT_v4s32*//*Label 1977*/ GIMT_Encode4(106818),
38343 /* 106776 */ /*GILLT_v2s64*//*Label 1978*/ GIMT_Encode4(106856),
38344 /* 106780 */ // Label 1976: @106780
38345 /* 106780 */ GIM_Try, /*On fail goto*//*Label 1980*/ GIMT_Encode4(106817), // Rule ID 1760 //
38346 /* 106785 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38347 /* 106788 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
38348 /* 106791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38349 /* 106795 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38350 /* 106799 */ // (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
38351 /* 106799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv8i16),
38352 /* 106802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38353 /* 106804 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38354 /* 106806 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38355 /* 106809 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38356 /* 106815 */ GIR_RootConstrainSelectedInstOperands,
38357 /* 106816 */ // GIR_Coverage, 1760,
38358 /* 106816 */ GIR_EraseRootFromParent_Done,
38359 /* 106817 */ // Label 1980: @106817
38360 /* 106817 */ GIM_Reject,
38361 /* 106818 */ // Label 1977: @106818
38362 /* 106818 */ GIM_Try, /*On fail goto*//*Label 1981*/ GIMT_Encode4(106855), // Rule ID 1761 //
38363 /* 106823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38364 /* 106826 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
38365 /* 106829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38366 /* 106833 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38367 /* 106837 */ // (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
38368 /* 106837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv4i32),
38369 /* 106840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38370 /* 106842 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38371 /* 106844 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38372 /* 106847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38373 /* 106853 */ GIR_RootConstrainSelectedInstOperands,
38374 /* 106854 */ // GIR_Coverage, 1761,
38375 /* 106854 */ GIR_EraseRootFromParent_Done,
38376 /* 106855 */ // Label 1981: @106855
38377 /* 106855 */ GIM_Reject,
38378 /* 106856 */ // Label 1978: @106856
38379 /* 106856 */ GIM_Try, /*On fail goto*//*Label 1982*/ GIMT_Encode4(106893), // Rule ID 1762 //
38380 /* 106861 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38381 /* 106864 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
38382 /* 106867 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38383 /* 106871 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38384 /* 106875 */ // (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
38385 /* 106875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv2i64),
38386 /* 106878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38387 /* 106880 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38388 /* 106882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38389 /* 106885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38390 /* 106891 */ GIR_RootConstrainSelectedInstOperands,
38391 /* 106892 */ // GIR_Coverage, 1762,
38392 /* 106892 */ GIR_EraseRootFromParent_Done,
38393 /* 106893 */ // Label 1982: @106893
38394 /* 106893 */ GIM_Reject,
38395 /* 106894 */ // Label 1979: @106894
38396 /* 106894 */ GIM_Reject,
38397 /* 106895 */ // Label 28: @106895
38398 /* 106895 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 1986*/ GIMT_Encode4(107499),
38399 /* 106906 */ /*GILLT_s32*//*Label 1983*/ GIMT_Encode4(106954), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38400 /* 106942 */ /*GILLT_v8s16*//*Label 1984*/ GIMT_Encode4(107246), GIMT_Encode4(0),
38401 /* 106950 */ /*GILLT_v4s32*//*Label 1985*/ GIMT_Encode4(107316),
38402 /* 106954 */ // Label 1983: @106954
38403 /* 106954 */ GIM_Try, /*On fail goto*//*Label 1987*/ GIMT_Encode4(107245),
38404 /* 106959 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
38405 /* 106962 */ GIM_Try, /*On fail goto*//*Label 1988*/ GIMT_Encode4(107007), // Rule ID 339 //
38406 /* 106967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
38407 /* 106970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38408 /* 106974 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38409 /* 106978 */ // MIs[0] Operand 2
38410 /* 106978 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
38411 /* 106989 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }) => (tSXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
38412 /* 106989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTB),
38413 /* 106992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38414 /* 106994 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
38415 /* 106996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38416 /* 106999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38417 /* 107005 */ GIR_RootConstrainSelectedInstOperands,
38418 /* 107006 */ // GIR_Coverage, 339,
38419 /* 107006 */ GIR_EraseRootFromParent_Done,
38420 /* 107007 */ // Label 1988: @107007
38421 /* 107007 */ GIM_Try, /*On fail goto*//*Label 1989*/ GIMT_Encode4(107052), // Rule ID 340 //
38422 /* 107012 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
38423 /* 107015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38424 /* 107019 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38425 /* 107023 */ // MIs[0] Operand 2
38426 /* 107023 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
38427 /* 107034 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }) => (tSXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
38428 /* 107034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTH),
38429 /* 107037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38430 /* 107039 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
38431 /* 107041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38432 /* 107044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38433 /* 107050 */ GIR_RootConstrainSelectedInstOperands,
38434 /* 107051 */ // GIR_Coverage, 340,
38435 /* 107051 */ GIR_EraseRootFromParent_Done,
38436 /* 107052 */ // Label 1989: @107052
38437 /* 107052 */ GIM_Try, /*On fail goto*//*Label 1990*/ GIMT_Encode4(107100), // Rule ID 2188 //
38438 /* 107057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
38439 /* 107060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
38440 /* 107064 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38441 /* 107068 */ // MIs[0] Operand 2
38442 /* 107068 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
38443 /* 107079 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (SXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
38444 /* 107079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB),
38445 /* 107082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38446 /* 107084 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
38447 /* 107086 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38448 /* 107089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38449 /* 107092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38450 /* 107098 */ GIR_RootConstrainSelectedInstOperands,
38451 /* 107099 */ // GIR_Coverage, 2188,
38452 /* 107099 */ GIR_EraseRootFromParent_Done,
38453 /* 107100 */ // Label 1990: @107100
38454 /* 107100 */ GIM_Try, /*On fail goto*//*Label 1991*/ GIMT_Encode4(107148), // Rule ID 2189 //
38455 /* 107105 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
38456 /* 107108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
38457 /* 107112 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38458 /* 107116 */ // MIs[0] Operand 2
38459 /* 107116 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
38460 /* 107127 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (SXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
38461 /* 107127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTH),
38462 /* 107130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38463 /* 107132 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
38464 /* 107134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38465 /* 107137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38466 /* 107140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38467 /* 107146 */ GIR_RootConstrainSelectedInstOperands,
38468 /* 107147 */ // GIR_Coverage, 2189,
38469 /* 107147 */ GIR_EraseRootFromParent_Done,
38470 /* 107148 */ // Label 1991: @107148
38471 /* 107148 */ GIM_Try, /*On fail goto*//*Label 1992*/ GIMT_Encode4(107196), // Rule ID 2427 //
38472 /* 107153 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38473 /* 107156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38474 /* 107160 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38475 /* 107164 */ // MIs[0] Operand 2
38476 /* 107164 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
38477 /* 107175 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (t2SXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
38478 /* 107175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB),
38479 /* 107178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38480 /* 107180 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
38481 /* 107182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38482 /* 107185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38483 /* 107188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38484 /* 107194 */ GIR_RootConstrainSelectedInstOperands,
38485 /* 107195 */ // GIR_Coverage, 2427,
38486 /* 107195 */ GIR_EraseRootFromParent_Done,
38487 /* 107196 */ // Label 1992: @107196
38488 /* 107196 */ GIM_Try, /*On fail goto*//*Label 1993*/ GIMT_Encode4(107244), // Rule ID 2428 //
38489 /* 107201 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38490 /* 107204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38491 /* 107208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38492 /* 107212 */ // MIs[0] Operand 2
38493 /* 107212 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
38494 /* 107223 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (t2SXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
38495 /* 107223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTH),
38496 /* 107226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38497 /* 107228 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
38498 /* 107230 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38499 /* 107233 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38500 /* 107236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38501 /* 107242 */ GIR_RootConstrainSelectedInstOperands,
38502 /* 107243 */ // GIR_Coverage, 2428,
38503 /* 107243 */ GIR_EraseRootFromParent_Done,
38504 /* 107244 */ // Label 1993: @107244
38505 /* 107244 */ GIM_Reject,
38506 /* 107245 */ // Label 1987: @107245
38507 /* 107245 */ GIM_Reject,
38508 /* 107246 */ // Label 1984: @107246
38509 /* 107246 */ GIM_Try, /*On fail goto*//*Label 1994*/ GIMT_Encode4(107315), // Rule ID 4097 //
38510 /* 107251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
38511 /* 107254 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
38512 /* 107257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38513 /* 107261 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38514 /* 107265 */ // MIs[0] Operand 2
38515 /* 107265 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
38516 /* 107276 */ // (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, v8i8:{ *:[Other] }) => (MVE_VMOVLs8bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src)
38517 /* 107276 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38518 /* 107279 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38519 /* 107283 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38520 /* 107288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh),
38521 /* 107291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38522 /* 107293 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
38523 /* 107295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38524 /* 107298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38525 /* 107304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38526 /* 107310 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38527 /* 107313 */ GIR_RootConstrainSelectedInstOperands,
38528 /* 107314 */ // GIR_Coverage, 4097,
38529 /* 107314 */ GIR_EraseRootFromParent_Done,
38530 /* 107315 */ // Label 1994: @107315
38531 /* 107315 */ GIM_Reject,
38532 /* 107316 */ // Label 1985: @107316
38533 /* 107316 */ GIM_Try, /*On fail goto*//*Label 1995*/ GIMT_Encode4(107498),
38534 /* 107321 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
38535 /* 107324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38536 /* 107328 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38537 /* 107332 */ GIM_Try, /*On fail goto*//*Label 1996*/ GIMT_Encode4(107390), // Rule ID 4096 //
38538 /* 107337 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
38539 /* 107340 */ // MIs[0] Operand 2
38540 /* 107340 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
38541 /* 107351 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i16:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src)
38542 /* 107351 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38543 /* 107354 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38544 /* 107358 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38545 /* 107363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh),
38546 /* 107366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38547 /* 107368 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
38548 /* 107370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38549 /* 107373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38550 /* 107379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38551 /* 107385 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38552 /* 107388 */ GIR_RootConstrainSelectedInstOperands,
38553 /* 107389 */ // GIR_Coverage, 4096,
38554 /* 107389 */ GIR_EraseRootFromParent_Done,
38555 /* 107390 */ // Label 1996: @107390
38556 /* 107390 */ GIM_Try, /*On fail goto*//*Label 1997*/ GIMT_Encode4(107497), // Rule ID 4098 //
38557 /* 107395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
38558 /* 107398 */ // MIs[0] Operand 2
38559 /* 107398 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
38560 /* 107409 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i8:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } (MVE_VMOVLs8bh:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src))
38561 /* 107409 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
38562 /* 107412 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38563 /* 107416 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38564 /* 107421 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
38565 /* 107424 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38566 /* 107428 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38567 /* 107433 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
38568 /* 107436 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh),
38569 /* 107440 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38570 /* 107445 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
38571 /* 107449 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
38572 /* 107452 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38573 /* 107458 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38574 /* 107464 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
38575 /* 107467 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38576 /* 107469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh),
38577 /* 107472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38578 /* 107474 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38579 /* 107477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38580 /* 107480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38581 /* 107486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38582 /* 107492 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38583 /* 107495 */ GIR_RootConstrainSelectedInstOperands,
38584 /* 107496 */ // GIR_Coverage, 4098,
38585 /* 107496 */ GIR_EraseRootFromParent_Done,
38586 /* 107497 */ // Label 1997: @107497
38587 /* 107497 */ GIM_Reject,
38588 /* 107498 */ // Label 1995: @107498
38589 /* 107498 */ GIM_Reject,
38590 /* 107499 */ // Label 1986: @107499
38591 /* 107499 */ GIM_Reject,
38592 /* 107500 */ // Label 29: @107500
38593 /* 107500 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 2001*/ GIMT_Encode4(108199),
38594 /* 107511 */ /*GILLT_v8s16*//*Label 1998*/ GIMT_Encode4(107527), GIMT_Encode4(0),
38595 /* 107519 */ /*GILLT_v4s32*//*Label 1999*/ GIMT_Encode4(107751),
38596 /* 107523 */ /*GILLT_v2s64*//*Label 2000*/ GIMT_Encode4(107975),
38597 /* 107527 */ // Label 1998: @107527
38598 /* 107527 */ GIM_Try, /*On fail goto*//*Label 2002*/ GIMT_Encode4(107750),
38599 /* 107532 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
38600 /* 107535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38601 /* 107539 */ GIM_Try, /*On fail goto*//*Label 2003*/ GIMT_Encode4(107599), // Rule ID 1335 //
38602 /* 107544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38603 /* 107547 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38604 /* 107551 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
38605 /* 107555 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
38606 /* 107559 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
38607 /* 107563 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38608 /* 107568 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38609 /* 107573 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38610 /* 107575 */ // (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
38611 /* 107575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv8i16),
38612 /* 107578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38613 /* 107580 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38614 /* 107584 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38615 /* 107588 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38616 /* 107591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38617 /* 107597 */ GIR_RootConstrainSelectedInstOperands,
38618 /* 107598 */ // GIR_Coverage, 1335,
38619 /* 107598 */ GIR_EraseRootFromParent_Done,
38620 /* 107599 */ // Label 2003: @107599
38621 /* 107599 */ GIM_Try, /*On fail goto*//*Label 2004*/ GIMT_Encode4(107659), // Rule ID 1338 //
38622 /* 107604 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38623 /* 107607 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38624 /* 107611 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
38625 /* 107615 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
38626 /* 107619 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
38627 /* 107623 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38628 /* 107628 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38629 /* 107633 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38630 /* 107635 */ // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
38631 /* 107635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16),
38632 /* 107638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38633 /* 107640 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38634 /* 107644 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38635 /* 107648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38636 /* 107651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38637 /* 107657 */ GIR_RootConstrainSelectedInstOperands,
38638 /* 107658 */ // GIR_Coverage, 1338,
38639 /* 107658 */ GIR_EraseRootFromParent_Done,
38640 /* 107659 */ // Label 2004: @107659
38641 /* 107659 */ GIM_Try, /*On fail goto*//*Label 2005*/ GIMT_Encode4(107719), // Rule ID 2953 //
38642 /* 107664 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38643 /* 107667 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38644 /* 107671 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
38645 /* 107675 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
38646 /* 107679 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
38647 /* 107683 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38648 /* 107688 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38649 /* 107693 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38650 /* 107695 */ // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB)
38651 /* 107695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16),
38652 /* 107698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38653 /* 107700 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA
38654 /* 107704 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB
38655 /* 107708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38656 /* 107711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38657 /* 107717 */ GIR_RootConstrainSelectedInstOperands,
38658 /* 107718 */ // GIR_Coverage, 2953,
38659 /* 107718 */ GIR_EraseRootFromParent_Done,
38660 /* 107719 */ // Label 2005: @107719
38661 /* 107719 */ GIM_Try, /*On fail goto*//*Label 2006*/ GIMT_Encode4(107749), // Rule ID 1763 //
38662 /* 107724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38663 /* 107727 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38664 /* 107731 */ // (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
38665 /* 107731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16),
38666 /* 107734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38667 /* 107736 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38668 /* 107738 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38669 /* 107741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38670 /* 107747 */ GIR_RootConstrainSelectedInstOperands,
38671 /* 107748 */ // GIR_Coverage, 1763,
38672 /* 107748 */ GIR_EraseRootFromParent_Done,
38673 /* 107749 */ // Label 2006: @107749
38674 /* 107749 */ GIM_Reject,
38675 /* 107750 */ // Label 2002: @107750
38676 /* 107750 */ GIM_Reject,
38677 /* 107751 */ // Label 1999: @107751
38678 /* 107751 */ GIM_Try, /*On fail goto*//*Label 2007*/ GIMT_Encode4(107974),
38679 /* 107756 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
38680 /* 107759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38681 /* 107763 */ GIM_Try, /*On fail goto*//*Label 2008*/ GIMT_Encode4(107823), // Rule ID 1336 //
38682 /* 107768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38683 /* 107771 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38684 /* 107775 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
38685 /* 107779 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
38686 /* 107783 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38687 /* 107787 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38688 /* 107792 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38689 /* 107797 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38690 /* 107799 */ // (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
38691 /* 107799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv4i32),
38692 /* 107802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38693 /* 107804 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38694 /* 107808 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38695 /* 107812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38696 /* 107815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38697 /* 107821 */ GIR_RootConstrainSelectedInstOperands,
38698 /* 107822 */ // GIR_Coverage, 1336,
38699 /* 107822 */ GIR_EraseRootFromParent_Done,
38700 /* 107823 */ // Label 2008: @107823
38701 /* 107823 */ GIM_Try, /*On fail goto*//*Label 2009*/ GIMT_Encode4(107883), // Rule ID 1339 //
38702 /* 107828 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38703 /* 107831 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38704 /* 107835 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
38705 /* 107839 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
38706 /* 107843 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38707 /* 107847 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38708 /* 107852 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38709 /* 107857 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38710 /* 107859 */ // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
38711 /* 107859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32),
38712 /* 107862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38713 /* 107864 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38714 /* 107868 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38715 /* 107872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38716 /* 107875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38717 /* 107881 */ GIR_RootConstrainSelectedInstOperands,
38718 /* 107882 */ // GIR_Coverage, 1339,
38719 /* 107882 */ GIR_EraseRootFromParent_Done,
38720 /* 107883 */ // Label 2009: @107883
38721 /* 107883 */ GIM_Try, /*On fail goto*//*Label 2010*/ GIMT_Encode4(107943), // Rule ID 2954 //
38722 /* 107888 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38723 /* 107891 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38724 /* 107895 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
38725 /* 107899 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
38726 /* 107903 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38727 /* 107907 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38728 /* 107912 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38729 /* 107917 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38730 /* 107919 */ // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB)
38731 /* 107919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32),
38732 /* 107922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38733 /* 107924 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA
38734 /* 107928 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB
38735 /* 107932 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38736 /* 107935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38737 /* 107941 */ GIR_RootConstrainSelectedInstOperands,
38738 /* 107942 */ // GIR_Coverage, 2954,
38739 /* 107942 */ GIR_EraseRootFromParent_Done,
38740 /* 107943 */ // Label 2010: @107943
38741 /* 107943 */ GIM_Try, /*On fail goto*//*Label 2011*/ GIMT_Encode4(107973), // Rule ID 1764 //
38742 /* 107948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38743 /* 107951 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38744 /* 107955 */ // (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
38745 /* 107955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32),
38746 /* 107958 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38747 /* 107960 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38748 /* 107962 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38749 /* 107965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38750 /* 107971 */ GIR_RootConstrainSelectedInstOperands,
38751 /* 107972 */ // GIR_Coverage, 1764,
38752 /* 107972 */ GIR_EraseRootFromParent_Done,
38753 /* 107973 */ // Label 2011: @107973
38754 /* 107973 */ GIM_Reject,
38755 /* 107974 */ // Label 2007: @107974
38756 /* 107974 */ GIM_Reject,
38757 /* 107975 */ // Label 2000: @107975
38758 /* 107975 */ GIM_Try, /*On fail goto*//*Label 2012*/ GIMT_Encode4(108198),
38759 /* 107980 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
38760 /* 107983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38761 /* 107987 */ GIM_Try, /*On fail goto*//*Label 2013*/ GIMT_Encode4(108047), // Rule ID 1337 //
38762 /* 107992 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38763 /* 107995 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38764 /* 107999 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
38765 /* 108003 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
38766 /* 108007 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38767 /* 108011 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38768 /* 108016 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38769 /* 108021 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38770 /* 108023 */ // (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38771 /* 108023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv2i64),
38772 /* 108026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38773 /* 108028 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38774 /* 108032 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38775 /* 108036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38776 /* 108039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38777 /* 108045 */ GIR_RootConstrainSelectedInstOperands,
38778 /* 108046 */ // GIR_Coverage, 1337,
38779 /* 108046 */ GIR_EraseRootFromParent_Done,
38780 /* 108047 */ // Label 2013: @108047
38781 /* 108047 */ GIM_Try, /*On fail goto*//*Label 2014*/ GIMT_Encode4(108107), // Rule ID 1340 //
38782 /* 108052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38783 /* 108055 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38784 /* 108059 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
38785 /* 108063 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
38786 /* 108067 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38787 /* 108071 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38788 /* 108076 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38789 /* 108081 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38790 /* 108083 */ // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38791 /* 108083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv2i64),
38792 /* 108086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38793 /* 108088 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38794 /* 108092 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38795 /* 108096 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38796 /* 108099 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38797 /* 108105 */ GIR_RootConstrainSelectedInstOperands,
38798 /* 108106 */ // GIR_Coverage, 1340,
38799 /* 108106 */ GIR_EraseRootFromParent_Done,
38800 /* 108107 */ // Label 2014: @108107
38801 /* 108107 */ GIM_Try, /*On fail goto*//*Label 2015*/ GIMT_Encode4(108167), // Rule ID 2955 //
38802 /* 108112 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38803 /* 108115 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38804 /* 108119 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
38805 /* 108123 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
38806 /* 108127 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38807 /* 108131 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38808 /* 108136 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38809 /* 108141 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38810 /* 108143 */ // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$opA, DPR:{ *:[v2i32] }:$opB)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$opA, DPR:{ *:[v2i32] }:$opB)
38811 /* 108143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv2i64),
38812 /* 108146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38813 /* 108148 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA
38814 /* 108152 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB
38815 /* 108156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38816 /* 108159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38817 /* 108165 */ GIR_RootConstrainSelectedInstOperands,
38818 /* 108166 */ // GIR_Coverage, 2955,
38819 /* 108166 */ GIR_EraseRootFromParent_Done,
38820 /* 108167 */ // Label 2015: @108167
38821 /* 108167 */ GIM_Try, /*On fail goto*//*Label 2016*/ GIMT_Encode4(108197), // Rule ID 1765 //
38822 /* 108172 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38823 /* 108175 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38824 /* 108179 */ // (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
38825 /* 108179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64),
38826 /* 108182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38827 /* 108184 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38828 /* 108186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38829 /* 108189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38830 /* 108195 */ GIR_RootConstrainSelectedInstOperands,
38831 /* 108196 */ // GIR_Coverage, 1765,
38832 /* 108196 */ GIR_EraseRootFromParent_Done,
38833 /* 108197 */ // Label 2016: @108197
38834 /* 108197 */ GIM_Reject,
38835 /* 108198 */ // Label 2012: @108198
38836 /* 108198 */ GIM_Reject,
38837 /* 108199 */ // Label 2001: @108199
38838 /* 108199 */ GIM_Reject,
38839 /* 108200 */ // Label 30: @108200
38840 /* 108200 */ GIM_Try, /*On fail goto*//*Label 2017*/ GIMT_Encode4(108415),
38841 /* 108205 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
38842 /* 108208 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
38843 /* 108211 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
38844 /* 108214 */ GIM_Try, /*On fail goto*//*Label 2018*/ GIMT_Encode4(108271), // Rule ID 469 //
38845 /* 108219 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38846 /* 108222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38847 /* 108226 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38848 /* 108230 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38849 /* 108234 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
38850 /* 108238 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31),
38851 /* 108242 */ // MIs[1] Operand 1
38852 /* 108242 */ // No operand predicates
38853 /* 108242 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38854 /* 108244 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2LSLri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm)
38855 /* 108244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLri),
38856 /* 108247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38857 /* 108249 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
38858 /* 108251 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
38859 /* 108254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38860 /* 108257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38861 /* 108263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38862 /* 108269 */ GIR_RootConstrainSelectedInstOperands,
38863 /* 108270 */ // GIR_Coverage, 469,
38864 /* 108270 */ GIR_EraseRootFromParent_Done,
38865 /* 108271 */ // Label 2018: @108271
38866 /* 108271 */ GIM_Try, /*On fail goto*//*Label 2019*/ GIMT_Encode4(108368),
38867 /* 108276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38868 /* 108280 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38869 /* 108284 */ GIM_Try, /*On fail goto*//*Label 2020*/ GIMT_Encode4(108329), // Rule ID 317 //
38870 /* 108289 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
38871 /* 108292 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38872 /* 108296 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
38873 /* 108300 */ // MIs[1] Operand 1
38874 /* 108300 */ // No operand predicates
38875 /* 108300 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38876 /* 108302 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5) => (tLSLri:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5)
38877 /* 108302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLri),
38878 /* 108305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38879 /* 108307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
38880 /* 108313 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
38881 /* 108315 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm5
38882 /* 108318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38883 /* 108321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38884 /* 108327 */ GIR_RootConstrainSelectedInstOperands,
38885 /* 108328 */ // GIR_Coverage, 317,
38886 /* 108328 */ GIR_EraseRootFromParent_Done,
38887 /* 108329 */ // Label 2020: @108329
38888 /* 108329 */ GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(108367), // Rule ID 318 //
38889 /* 108334 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
38890 /* 108337 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38891 /* 108341 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSLrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
38892 /* 108341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLrr),
38893 /* 108344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
38894 /* 108346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
38895 /* 108352 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38896 /* 108354 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38897 /* 108356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38898 /* 108359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38899 /* 108365 */ GIR_RootConstrainSelectedInstOperands,
38900 /* 108366 */ // GIR_Coverage, 318,
38901 /* 108366 */ GIR_EraseRootFromParent_Done,
38902 /* 108367 */ // Label 2021: @108367
38903 /* 108367 */ GIM_Reject,
38904 /* 108368 */ // Label 2019: @108368
38905 /* 108368 */ GIM_Try, /*On fail goto*//*Label 2022*/ GIMT_Encode4(108414), // Rule ID 470 //
38906 /* 108373 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38907 /* 108376 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38908 /* 108380 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38909 /* 108384 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38910 /* 108388 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSLrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
38911 /* 108388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLrr),
38912 /* 108391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38913 /* 108393 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38914 /* 108395 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38915 /* 108397 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38916 /* 108400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38917 /* 108406 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38918 /* 108412 */ GIR_RootConstrainSelectedInstOperands,
38919 /* 108413 */ // GIR_Coverage, 470,
38920 /* 108413 */ GIR_EraseRootFromParent_Done,
38921 /* 108414 */ // Label 2022: @108414
38922 /* 108414 */ GIM_Reject,
38923 /* 108415 */ // Label 2017: @108415
38924 /* 108415 */ GIM_Reject,
38925 /* 108416 */ // Label 31: @108416
38926 /* 108416 */ GIM_Try, /*On fail goto*//*Label 2023*/ GIMT_Encode4(108523),
38927 /* 108421 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
38928 /* 108424 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
38929 /* 108427 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
38930 /* 108430 */ GIM_Try, /*On fail goto*//*Label 2024*/ GIMT_Encode4(108476), // Rule ID 320 //
38931 /* 108435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
38932 /* 108438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38933 /* 108442 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38934 /* 108446 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38935 /* 108450 */ // (srl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
38936 /* 108450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSRrr),
38937 /* 108453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
38938 /* 108455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
38939 /* 108461 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38940 /* 108463 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38941 /* 108465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38942 /* 108468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38943 /* 108474 */ GIR_RootConstrainSelectedInstOperands,
38944 /* 108475 */ // GIR_Coverage, 320,
38945 /* 108475 */ GIR_EraseRootFromParent_Done,
38946 /* 108476 */ // Label 2024: @108476
38947 /* 108476 */ GIM_Try, /*On fail goto*//*Label 2025*/ GIMT_Encode4(108522), // Rule ID 472 //
38948 /* 108481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38949 /* 108484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38950 /* 108488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38951 /* 108492 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38952 /* 108496 */ // (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
38953 /* 108496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSRrr),
38954 /* 108499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38955 /* 108501 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
38956 /* 108503 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
38957 /* 108505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38958 /* 108508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38959 /* 108514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38960 /* 108520 */ GIR_RootConstrainSelectedInstOperands,
38961 /* 108521 */ // GIR_Coverage, 472,
38962 /* 108521 */ GIR_EraseRootFromParent_Done,
38963 /* 108522 */ // Label 2025: @108522
38964 /* 108522 */ GIM_Reject,
38965 /* 108523 */ // Label 2023: @108523
38966 /* 108523 */ GIM_Reject,
38967 /* 108524 */ // Label 32: @108524
38968 /* 108524 */ GIM_Try, /*On fail goto*//*Label 2026*/ GIMT_Encode4(108796),
38969 /* 108529 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
38970 /* 108532 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
38971 /* 108535 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
38972 /* 108538 */ GIM_Try, /*On fail goto*//*Label 2027*/ GIMT_Encode4(108593), // Rule ID 200 //
38973 /* 108543 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
38974 /* 108546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38975 /* 108550 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38976 /* 108554 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
38977 /* 108558 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38978 /* 108562 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38979 /* 108567 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
38980 /* 108571 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38981 /* 108573 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
38982 /* 108573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH),
38983 /* 108576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38984 /* 108578 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
38985 /* 108582 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38986 /* 108585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38987 /* 108591 */ GIR_RootConstrainSelectedInstOperands,
38988 /* 108592 */ // GIR_Coverage, 200,
38989 /* 108592 */ GIR_EraseRootFromParent_Done,
38990 /* 108593 */ // Label 2027: @108593
38991 /* 108593 */ GIM_Try, /*On fail goto*//*Label 2028*/ GIMT_Encode4(108648), // Rule ID 327 //
38992 /* 108598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
38993 /* 108601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38994 /* 108605 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38995 /* 108609 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
38996 /* 108613 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38997 /* 108617 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38998 /* 108622 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
38999 /* 108626 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39000 /* 108628 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREVSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
39001 /* 108628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREVSH),
39002 /* 108631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39003 /* 108633 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
39004 /* 108637 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39005 /* 108640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39006 /* 108646 */ GIR_RootConstrainSelectedInstOperands,
39007 /* 108647 */ // GIR_Coverage, 327,
39008 /* 108647 */ GIR_EraseRootFromParent_Done,
39009 /* 108648 */ // Label 2028: @108648
39010 /* 108648 */ GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(108703), // Rule ID 537 //
39011 /* 108653 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
39012 /* 108656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39013 /* 108660 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39014 /* 108664 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
39015 /* 108668 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39016 /* 108672 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39017 /* 108677 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
39018 /* 108681 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39019 /* 108683 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
39020 /* 108683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH),
39021 /* 108686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39022 /* 108688 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
39023 /* 108692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39024 /* 108695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39025 /* 108701 */ GIR_RootConstrainSelectedInstOperands,
39026 /* 108702 */ // GIR_Coverage, 537,
39027 /* 108702 */ GIR_EraseRootFromParent_Done,
39028 /* 108703 */ // Label 2029: @108703
39029 /* 108703 */ GIM_Try, /*On fail goto*//*Label 2030*/ GIMT_Encode4(108749), // Rule ID 311 //
39030 /* 108708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
39031 /* 108711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39032 /* 108715 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39033 /* 108719 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39034 /* 108723 */ // (sra:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tASRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
39035 /* 108723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tASRrr),
39036 /* 108726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
39037 /* 108728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
39038 /* 108734 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39039 /* 108736 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39040 /* 108738 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39041 /* 108741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39042 /* 108747 */ GIR_RootConstrainSelectedInstOperands,
39043 /* 108748 */ // GIR_Coverage, 311,
39044 /* 108748 */ GIR_EraseRootFromParent_Done,
39045 /* 108749 */ // Label 2030: @108749
39046 /* 108749 */ GIM_Try, /*On fail goto*//*Label 2031*/ GIMT_Encode4(108795), // Rule ID 474 //
39047 /* 108754 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
39048 /* 108757 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39049 /* 108761 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39050 /* 108765 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39051 /* 108769 */ // (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ASRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
39052 /* 108769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ASRrr),
39053 /* 108772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39054 /* 108774 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39055 /* 108776 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39056 /* 108778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39057 /* 108781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39058 /* 108787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39059 /* 108793 */ GIR_RootConstrainSelectedInstOperands,
39060 /* 108794 */ // GIR_Coverage, 474,
39061 /* 108794 */ GIR_EraseRootFromParent_Done,
39062 /* 108795 */ // Label 2031: @108795
39063 /* 108795 */ GIM_Reject,
39064 /* 108796 */ // Label 2026: @108796
39065 /* 108796 */ GIM_Reject,
39066 /* 108797 */ // Label 33: @108797
39067 /* 108797 */ GIM_Try, /*On fail goto*//*Label 2032*/ GIMT_Encode4(109128),
39068 /* 108802 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
39069 /* 108805 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
39070 /* 108808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
39071 /* 108811 */ GIM_Try, /*On fail goto*//*Label 2033*/ GIMT_Encode4(108866), // Rule ID 199 //
39072 /* 108816 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
39073 /* 108819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39074 /* 108823 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39075 /* 108827 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
39076 /* 108831 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39077 /* 108835 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39078 /* 108840 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
39079 /* 108844 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39080 /* 108846 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REV16:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
39081 /* 108846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV16),
39082 /* 108849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39083 /* 108851 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
39084 /* 108855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39085 /* 108858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39086 /* 108864 */ GIR_RootConstrainSelectedInstOperands,
39087 /* 108865 */ // GIR_Coverage, 199,
39088 /* 108865 */ GIR_EraseRootFromParent_Done,
39089 /* 108866 */ // Label 2033: @108866
39090 /* 108866 */ GIM_Try, /*On fail goto*//*Label 2034*/ GIMT_Encode4(108921), // Rule ID 326 //
39091 /* 108871 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
39092 /* 108874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39093 /* 108878 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39094 /* 108882 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
39095 /* 108886 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39096 /* 108890 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39097 /* 108895 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
39098 /* 108899 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39099 /* 108901 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREV16:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
39100 /* 108901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV16),
39101 /* 108904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39102 /* 108906 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
39103 /* 108910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39104 /* 108913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39105 /* 108919 */ GIR_RootConstrainSelectedInstOperands,
39106 /* 108920 */ // GIR_Coverage, 326,
39107 /* 108920 */ GIR_EraseRootFromParent_Done,
39108 /* 108921 */ // Label 2034: @108921
39109 /* 108921 */ GIM_Try, /*On fail goto*//*Label 2035*/ GIMT_Encode4(109035),
39110 /* 108926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39111 /* 108930 */ GIM_Try, /*On fail goto*//*Label 2036*/ GIMT_Encode4(108981), // Rule ID 536 //
39112 /* 108935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
39113 /* 108938 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39114 /* 108942 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
39115 /* 108946 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39116 /* 108950 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39117 /* 108955 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
39118 /* 108959 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39119 /* 108961 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REV16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
39120 /* 108961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV16),
39121 /* 108964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39122 /* 108966 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
39123 /* 108970 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39124 /* 108973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39125 /* 108979 */ GIR_RootConstrainSelectedInstOperands,
39126 /* 108980 */ // GIR_Coverage, 536,
39127 /* 108980 */ GIR_EraseRootFromParent_Done,
39128 /* 108981 */ // Label 2036: @108981
39129 /* 108981 */ GIM_Try, /*On fail goto*//*Label 2037*/ GIMT_Encode4(109034), // Rule ID 475 //
39130 /* 108986 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
39131 /* 108989 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39132 /* 108993 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39133 /* 108997 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39134 /* 109001 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31),
39135 /* 109005 */ // MIs[1] Operand 1
39136 /* 109005 */ // No operand predicates
39137 /* 109005 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39138 /* 109007 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2RORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm)
39139 /* 109007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORri),
39140 /* 109010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39141 /* 109012 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
39142 /* 109014 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
39143 /* 109017 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39144 /* 109020 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39145 /* 109026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39146 /* 109032 */ GIR_RootConstrainSelectedInstOperands,
39147 /* 109033 */ // GIR_Coverage, 475,
39148 /* 109033 */ GIR_EraseRootFromParent_Done,
39149 /* 109034 */ // Label 2037: @109034
39150 /* 109034 */ GIM_Reject,
39151 /* 109035 */ // Label 2035: @109035
39152 /* 109035 */ GIM_Try, /*On fail goto*//*Label 2038*/ GIMT_Encode4(109081), // Rule ID 328 //
39153 /* 109040 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
39154 /* 109043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39155 /* 109047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39156 /* 109051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39157 /* 109055 */ // (rotr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tROR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
39158 /* 109055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tROR),
39159 /* 109058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
39160 /* 109060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
39161 /* 109066 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39162 /* 109068 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39163 /* 109070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39164 /* 109073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39165 /* 109079 */ GIR_RootConstrainSelectedInstOperands,
39166 /* 109080 */ // GIR_Coverage, 328,
39167 /* 109080 */ GIR_EraseRootFromParent_Done,
39168 /* 109081 */ // Label 2038: @109081
39169 /* 109081 */ GIM_Try, /*On fail goto*//*Label 2039*/ GIMT_Encode4(109127), // Rule ID 476 //
39170 /* 109086 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
39171 /* 109089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39172 /* 109093 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39173 /* 109097 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39174 /* 109101 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2RORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
39175 /* 109101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORrr),
39176 /* 109104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39177 /* 109106 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39178 /* 109108 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39179 /* 109110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39180 /* 109113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39181 /* 109119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39182 /* 109125 */ GIR_RootConstrainSelectedInstOperands,
39183 /* 109126 */ // GIR_Coverage, 476,
39184 /* 109126 */ GIR_EraseRootFromParent_Done,
39185 /* 109127 */ // Label 2039: @109127
39186 /* 109127 */ GIM_Reject,
39187 /* 109128 */ // Label 2032: @109128
39188 /* 109128 */ GIM_Reject,
39189 /* 109129 */ // Label 34: @109129
39190 /* 109129 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2043*/ GIMT_Encode4(109364),
39191 /* 109140 */ /*GILLT_v16s8*//*Label 2040*/ GIMT_Encode4(109160), GIMT_Encode4(0),
39192 /* 109148 */ /*GILLT_v8s16*//*Label 2041*/ GIMT_Encode4(109228), GIMT_Encode4(0),
39193 /* 109156 */ /*GILLT_v4s32*//*Label 2042*/ GIMT_Encode4(109296),
39194 /* 109160 */ // Label 2040: @109160
39195 /* 109160 */ GIM_Try, /*On fail goto*//*Label 2044*/ GIMT_Encode4(109227), // Rule ID 4947 //
39196 /* 109165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39197 /* 109168 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
39198 /* 109171 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
39199 /* 109174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39200 /* 109178 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39201 /* 109182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39202 /* 109186 */ // (mulhu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
39203 /* 109186 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39204 /* 109189 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39205 /* 109193 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39206 /* 109198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8),
39207 /* 109201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39208 /* 109203 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39209 /* 109205 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39210 /* 109207 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39211 /* 109210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39212 /* 109216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39213 /* 109222 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39214 /* 109225 */ GIR_RootConstrainSelectedInstOperands,
39215 /* 109226 */ // GIR_Coverage, 4947,
39216 /* 109226 */ GIR_EraseRootFromParent_Done,
39217 /* 109227 */ // Label 2044: @109227
39218 /* 109227 */ GIM_Reject,
39219 /* 109228 */ // Label 2041: @109228
39220 /* 109228 */ GIM_Try, /*On fail goto*//*Label 2045*/ GIMT_Encode4(109295), // Rule ID 4951 //
39221 /* 109233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39222 /* 109236 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
39223 /* 109239 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
39224 /* 109242 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39225 /* 109246 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39226 /* 109250 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39227 /* 109254 */ // (mulhu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
39228 /* 109254 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39229 /* 109257 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39230 /* 109261 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39231 /* 109266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16),
39232 /* 109269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39233 /* 109271 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39234 /* 109273 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39235 /* 109275 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39236 /* 109278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39237 /* 109284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39238 /* 109290 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39239 /* 109293 */ GIR_RootConstrainSelectedInstOperands,
39240 /* 109294 */ // GIR_Coverage, 4951,
39241 /* 109294 */ GIR_EraseRootFromParent_Done,
39242 /* 109295 */ // Label 2045: @109295
39243 /* 109295 */ GIM_Reject,
39244 /* 109296 */ // Label 2042: @109296
39245 /* 109296 */ GIM_Try, /*On fail goto*//*Label 2046*/ GIMT_Encode4(109363), // Rule ID 4955 //
39246 /* 109301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39247 /* 109304 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
39248 /* 109307 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
39249 /* 109310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39250 /* 109314 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39251 /* 109318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39252 /* 109322 */ // (mulhu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
39253 /* 109322 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39254 /* 109325 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39255 /* 109329 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39256 /* 109334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32),
39257 /* 109337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39258 /* 109339 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39259 /* 109341 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39260 /* 109343 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39261 /* 109346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39262 /* 109352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39263 /* 109358 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39264 /* 109361 */ GIR_RootConstrainSelectedInstOperands,
39265 /* 109362 */ // GIR_Coverage, 4955,
39266 /* 109362 */ GIR_EraseRootFromParent_Done,
39267 /* 109363 */ // Label 2046: @109363
39268 /* 109363 */ GIM_Reject,
39269 /* 109364 */ // Label 2043: @109364
39270 /* 109364 */ GIM_Reject,
39271 /* 109365 */ // Label 35: @109365
39272 /* 109365 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2051*/ GIMT_Encode4(109721),
39273 /* 109376 */ /*GILLT_s32*//*Label 2047*/ GIMT_Encode4(109424), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
39274 /* 109404 */ /*GILLT_v16s8*//*Label 2048*/ GIMT_Encode4(109517), GIMT_Encode4(0),
39275 /* 109412 */ /*GILLT_v8s16*//*Label 2049*/ GIMT_Encode4(109585), GIMT_Encode4(0),
39276 /* 109420 */ /*GILLT_v4s32*//*Label 2050*/ GIMT_Encode4(109653),
39277 /* 109424 */ // Label 2047: @109424
39278 /* 109424 */ GIM_Try, /*On fail goto*//*Label 2052*/ GIMT_Encode4(109516),
39279 /* 109429 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
39280 /* 109432 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
39281 /* 109435 */ GIM_Try, /*On fail goto*//*Label 2053*/ GIMT_Encode4(109475), // Rule ID 177 //
39282 /* 109440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
39283 /* 109443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39284 /* 109447 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39285 /* 109451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39286 /* 109455 */ // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SMMUL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
39287 /* 109455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMUL),
39288 /* 109458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39289 /* 109460 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39290 /* 109462 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39291 /* 109464 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39292 /* 109467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39293 /* 109473 */ GIR_RootConstrainSelectedInstOperands,
39294 /* 109474 */ // GIR_Coverage, 177,
39295 /* 109474 */ GIR_EraseRootFromParent_Done,
39296 /* 109475 */ // Label 2053: @109475
39297 /* 109475 */ GIM_Try, /*On fail goto*//*Label 2054*/ GIMT_Encode4(109515), // Rule ID 506 //
39298 /* 109480 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
39299 /* 109483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39300 /* 109487 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39301 /* 109491 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39302 /* 109495 */ // (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMMUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
39303 /* 109495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMUL),
39304 /* 109498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39305 /* 109500 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39306 /* 109502 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39307 /* 109504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39308 /* 109507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39309 /* 109513 */ GIR_RootConstrainSelectedInstOperands,
39310 /* 109514 */ // GIR_Coverage, 506,
39311 /* 109514 */ GIR_EraseRootFromParent_Done,
39312 /* 109515 */ // Label 2054: @109515
39313 /* 109515 */ GIM_Reject,
39314 /* 109516 */ // Label 2052: @109516
39315 /* 109516 */ GIM_Reject,
39316 /* 109517 */ // Label 2048: @109517
39317 /* 109517 */ GIM_Try, /*On fail goto*//*Label 2055*/ GIMT_Encode4(109584), // Rule ID 4936 //
39318 /* 109522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39319 /* 109525 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
39320 /* 109528 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
39321 /* 109531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39322 /* 109535 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39323 /* 109539 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39324 /* 109543 */ // (mulhs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
39325 /* 109543 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39326 /* 109546 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39327 /* 109550 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39328 /* 109555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8),
39329 /* 109558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39330 /* 109560 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39331 /* 109562 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39332 /* 109564 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39333 /* 109567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39334 /* 109573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39335 /* 109579 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39336 /* 109582 */ GIR_RootConstrainSelectedInstOperands,
39337 /* 109583 */ // GIR_Coverage, 4936,
39338 /* 109583 */ GIR_EraseRootFromParent_Done,
39339 /* 109584 */ // Label 2055: @109584
39340 /* 109584 */ GIM_Reject,
39341 /* 109585 */ // Label 2049: @109585
39342 /* 109585 */ GIM_Try, /*On fail goto*//*Label 2056*/ GIMT_Encode4(109652), // Rule ID 4939 //
39343 /* 109590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39344 /* 109593 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
39345 /* 109596 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
39346 /* 109599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39347 /* 109603 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39348 /* 109607 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39349 /* 109611 */ // (mulhs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
39350 /* 109611 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39351 /* 109614 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39352 /* 109618 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39353 /* 109623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16),
39354 /* 109626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39355 /* 109628 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39356 /* 109630 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39357 /* 109632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39358 /* 109635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39359 /* 109641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39360 /* 109647 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39361 /* 109650 */ GIR_RootConstrainSelectedInstOperands,
39362 /* 109651 */ // GIR_Coverage, 4939,
39363 /* 109651 */ GIR_EraseRootFromParent_Done,
39364 /* 109652 */ // Label 2056: @109652
39365 /* 109652 */ GIM_Reject,
39366 /* 109653 */ // Label 2050: @109653
39367 /* 109653 */ GIM_Try, /*On fail goto*//*Label 2057*/ GIMT_Encode4(109720), // Rule ID 4943 //
39368 /* 109658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39369 /* 109661 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
39370 /* 109664 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
39371 /* 109667 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39372 /* 109671 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39373 /* 109675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39374 /* 109679 */ // (mulhs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
39375 /* 109679 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39376 /* 109682 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39377 /* 109686 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39378 /* 109691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32),
39379 /* 109694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39380 /* 109696 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39381 /* 109698 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39382 /* 109700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39383 /* 109703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39384 /* 109709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39385 /* 109715 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39386 /* 109718 */ GIR_RootConstrainSelectedInstOperands,
39387 /* 109719 */ // GIR_Coverage, 4943,
39388 /* 109719 */ GIR_EraseRootFromParent_Done,
39389 /* 109720 */ // Label 2057: @109720
39390 /* 109720 */ GIM_Reject,
39391 /* 109721 */ // Label 2051: @109721
39392 /* 109721 */ GIM_Reject,
39393 /* 109722 */ // Label 36: @109722
39394 /* 109722 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 2066*/ GIMT_Encode4(110358),
39395 /* 109733 */ /*GILLT_s64*//*Label 2058*/ GIMT_Encode4(109781), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
39396 /* 109753 */ /*GILLT_v8s8*//*Label 2059*/ GIMT_Encode4(109828),
39397 /* 109757 */ /*GILLT_v16s8*//*Label 2060*/ GIMT_Encode4(109875),
39398 /* 109761 */ /*GILLT_v4s16*//*Label 2061*/ GIMT_Encode4(109989),
39399 /* 109765 */ /*GILLT_v8s16*//*Label 2062*/ GIMT_Encode4(110036),
39400 /* 109769 */ /*GILLT_v2s32*//*Label 2063*/ GIMT_Encode4(110150),
39401 /* 109773 */ /*GILLT_v4s32*//*Label 2064*/ GIMT_Encode4(110197),
39402 /* 109777 */ /*GILLT_v2s64*//*Label 2065*/ GIMT_Encode4(110311),
39403 /* 109781 */ // Label 2058: @109781
39404 /* 109781 */ GIM_Try, /*On fail goto*//*Label 2067*/ GIMT_Encode4(109827), // Rule ID 950 //
39405 /* 109786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39406 /* 109789 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
39407 /* 109792 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
39408 /* 109795 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39409 /* 109799 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39410 /* 109803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39411 /* 109807 */ // (uaddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
39412 /* 109807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv1i64),
39413 /* 109810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39414 /* 109812 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39415 /* 109814 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39416 /* 109816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39417 /* 109819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39418 /* 109825 */ GIR_RootConstrainSelectedInstOperands,
39419 /* 109826 */ // GIR_Coverage, 950,
39420 /* 109826 */ GIR_EraseRootFromParent_Done,
39421 /* 109827 */ // Label 2067: @109827
39422 /* 109827 */ GIM_Reject,
39423 /* 109828 */ // Label 2059: @109828
39424 /* 109828 */ GIM_Try, /*On fail goto*//*Label 2068*/ GIMT_Encode4(109874), // Rule ID 948 //
39425 /* 109833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39426 /* 109836 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
39427 /* 109839 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
39428 /* 109842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39429 /* 109846 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39430 /* 109850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39431 /* 109854 */ // (uaddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
39432 /* 109854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i8),
39433 /* 109857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39434 /* 109859 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39435 /* 109861 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39436 /* 109863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39437 /* 109866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39438 /* 109872 */ GIR_RootConstrainSelectedInstOperands,
39439 /* 109873 */ // GIR_Coverage, 948,
39440 /* 109873 */ GIR_EraseRootFromParent_Done,
39441 /* 109874 */ // Label 2068: @109874
39442 /* 109874 */ GIM_Reject,
39443 /* 109875 */ // Label 2060: @109875
39444 /* 109875 */ GIM_Try, /*On fail goto*//*Label 2069*/ GIMT_Encode4(109988),
39445 /* 109880 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
39446 /* 109883 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
39447 /* 109886 */ GIM_Try, /*On fail goto*//*Label 2070*/ GIMT_Encode4(109926), // Rule ID 949 //
39448 /* 109891 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39449 /* 109894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39450 /* 109898 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39451 /* 109902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39452 /* 109906 */ // (uaddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
39453 /* 109906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv16i8),
39454 /* 109909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39455 /* 109911 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39456 /* 109913 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39457 /* 109915 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39458 /* 109918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39459 /* 109924 */ GIR_RootConstrainSelectedInstOperands,
39460 /* 109925 */ // GIR_Coverage, 949,
39461 /* 109925 */ GIR_EraseRootFromParent_Done,
39462 /* 109926 */ // Label 2070: @109926
39463 /* 109926 */ GIM_Try, /*On fail goto*//*Label 2071*/ GIMT_Encode4(109987), // Rule ID 3904 //
39464 /* 109931 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39465 /* 109934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39466 /* 109938 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39467 /* 109942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39468 /* 109946 */ // (uaddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
39469 /* 109946 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39470 /* 109949 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39471 /* 109953 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39472 /* 109958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu8),
39473 /* 109961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39474 /* 109963 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39475 /* 109965 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39476 /* 109967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39477 /* 109970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39478 /* 109976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39479 /* 109982 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39480 /* 109985 */ GIR_RootConstrainSelectedInstOperands,
39481 /* 109986 */ // GIR_Coverage, 3904,
39482 /* 109986 */ GIR_EraseRootFromParent_Done,
39483 /* 109987 */ // Label 2071: @109987
39484 /* 109987 */ GIM_Reject,
39485 /* 109988 */ // Label 2069: @109988
39486 /* 109988 */ GIM_Reject,
39487 /* 109989 */ // Label 2061: @109989
39488 /* 109989 */ GIM_Try, /*On fail goto*//*Label 2072*/ GIMT_Encode4(110035), // Rule ID 944 //
39489 /* 109994 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39490 /* 109997 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
39491 /* 110000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
39492 /* 110003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39493 /* 110007 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39494 /* 110011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39495 /* 110015 */ // (uaddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39496 /* 110015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i16),
39497 /* 110018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39498 /* 110020 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39499 /* 110022 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39500 /* 110024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39501 /* 110027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39502 /* 110033 */ GIR_RootConstrainSelectedInstOperands,
39503 /* 110034 */ // GIR_Coverage, 944,
39504 /* 110034 */ GIR_EraseRootFromParent_Done,
39505 /* 110035 */ // Label 2072: @110035
39506 /* 110035 */ GIM_Reject,
39507 /* 110036 */ // Label 2062: @110036
39508 /* 110036 */ GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(110149),
39509 /* 110041 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
39510 /* 110044 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
39511 /* 110047 */ GIM_Try, /*On fail goto*//*Label 2074*/ GIMT_Encode4(110087), // Rule ID 946 //
39512 /* 110052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39513 /* 110055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39514 /* 110059 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39515 /* 110063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39516 /* 110067 */ // (uaddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
39517 /* 110067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i16),
39518 /* 110070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39519 /* 110072 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39520 /* 110074 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39521 /* 110076 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39522 /* 110079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39523 /* 110085 */ GIR_RootConstrainSelectedInstOperands,
39524 /* 110086 */ // GIR_Coverage, 946,
39525 /* 110086 */ GIR_EraseRootFromParent_Done,
39526 /* 110087 */ // Label 2074: @110087
39527 /* 110087 */ GIM_Try, /*On fail goto*//*Label 2075*/ GIMT_Encode4(110148), // Rule ID 3907 //
39528 /* 110092 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39529 /* 110095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39530 /* 110099 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39531 /* 110103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39532 /* 110107 */ // (uaddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
39533 /* 110107 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39534 /* 110110 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39535 /* 110114 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39536 /* 110119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu16),
39537 /* 110122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39538 /* 110124 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39539 /* 110126 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39540 /* 110128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39541 /* 110131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39542 /* 110137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39543 /* 110143 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39544 /* 110146 */ GIR_RootConstrainSelectedInstOperands,
39545 /* 110147 */ // GIR_Coverage, 3907,
39546 /* 110147 */ GIR_EraseRootFromParent_Done,
39547 /* 110148 */ // Label 2075: @110148
39548 /* 110148 */ GIM_Reject,
39549 /* 110149 */ // Label 2073: @110149
39550 /* 110149 */ GIM_Reject,
39551 /* 110150 */ // Label 2063: @110150
39552 /* 110150 */ GIM_Try, /*On fail goto*//*Label 2076*/ GIMT_Encode4(110196), // Rule ID 945 //
39553 /* 110155 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39554 /* 110158 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
39555 /* 110161 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
39556 /* 110164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39557 /* 110168 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39558 /* 110172 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39559 /* 110176 */ // (uaddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
39560 /* 110176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i32),
39561 /* 110179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39562 /* 110181 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39563 /* 110183 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39564 /* 110185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39565 /* 110188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39566 /* 110194 */ GIR_RootConstrainSelectedInstOperands,
39567 /* 110195 */ // GIR_Coverage, 945,
39568 /* 110195 */ GIR_EraseRootFromParent_Done,
39569 /* 110196 */ // Label 2076: @110196
39570 /* 110196 */ GIM_Reject,
39571 /* 110197 */ // Label 2064: @110197
39572 /* 110197 */ GIM_Try, /*On fail goto*//*Label 2077*/ GIMT_Encode4(110310),
39573 /* 110202 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
39574 /* 110205 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
39575 /* 110208 */ GIM_Try, /*On fail goto*//*Label 2078*/ GIMT_Encode4(110248), // Rule ID 947 //
39576 /* 110213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39577 /* 110216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39578 /* 110220 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39579 /* 110224 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39580 /* 110228 */ // (uaddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
39581 /* 110228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i32),
39582 /* 110231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39583 /* 110233 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39584 /* 110235 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39585 /* 110237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39586 /* 110240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39587 /* 110246 */ GIR_RootConstrainSelectedInstOperands,
39588 /* 110247 */ // GIR_Coverage, 947,
39589 /* 110247 */ GIR_EraseRootFromParent_Done,
39590 /* 110248 */ // Label 2078: @110248
39591 /* 110248 */ GIM_Try, /*On fail goto*//*Label 2079*/ GIMT_Encode4(110309), // Rule ID 3910 //
39592 /* 110253 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39593 /* 110256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39594 /* 110260 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39595 /* 110264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39596 /* 110268 */ // (uaddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
39597 /* 110268 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39598 /* 110271 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39599 /* 110275 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39600 /* 110280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu32),
39601 /* 110283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39602 /* 110285 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39603 /* 110287 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39604 /* 110289 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39605 /* 110292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39606 /* 110298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39607 /* 110304 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39608 /* 110307 */ GIR_RootConstrainSelectedInstOperands,
39609 /* 110308 */ // GIR_Coverage, 3910,
39610 /* 110308 */ GIR_EraseRootFromParent_Done,
39611 /* 110309 */ // Label 2079: @110309
39612 /* 110309 */ GIM_Reject,
39613 /* 110310 */ // Label 2077: @110310
39614 /* 110310 */ GIM_Reject,
39615 /* 110311 */ // Label 2065: @110311
39616 /* 110311 */ GIM_Try, /*On fail goto*//*Label 2080*/ GIMT_Encode4(110357), // Rule ID 951 //
39617 /* 110316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39618 /* 110319 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
39619 /* 110322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
39620 /* 110325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39621 /* 110329 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39622 /* 110333 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39623 /* 110337 */ // (uaddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
39624 /* 110337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i64),
39625 /* 110340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39626 /* 110342 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39627 /* 110344 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39628 /* 110346 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39629 /* 110349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39630 /* 110355 */ GIR_RootConstrainSelectedInstOperands,
39631 /* 110356 */ // GIR_Coverage, 951,
39632 /* 110356 */ GIR_EraseRootFromParent_Done,
39633 /* 110357 */ // Label 2080: @110357
39634 /* 110357 */ GIM_Reject,
39635 /* 110358 */ // Label 2066: @110358
39636 /* 110358 */ GIM_Reject,
39637 /* 110359 */ // Label 37: @110359
39638 /* 110359 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 2090*/ GIMT_Encode4(111650),
39639 /* 110370 */ /*GILLT_s32*//*Label 2081*/ GIMT_Encode4(110422),
39640 /* 110374 */ /*GILLT_s64*//*Label 2082*/ GIMT_Encode4(110763), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
39641 /* 110394 */ /*GILLT_v8s8*//*Label 2083*/ GIMT_Encode4(110810),
39642 /* 110398 */ /*GILLT_v16s8*//*Label 2084*/ GIMT_Encode4(110857),
39643 /* 110402 */ /*GILLT_v4s16*//*Label 2085*/ GIMT_Encode4(110971),
39644 /* 110406 */ /*GILLT_v8s16*//*Label 2086*/ GIMT_Encode4(111018),
39645 /* 110410 */ /*GILLT_v2s32*//*Label 2087*/ GIMT_Encode4(111132),
39646 /* 110414 */ /*GILLT_v4s32*//*Label 2088*/ GIMT_Encode4(111179),
39647 /* 110418 */ /*GILLT_v2s64*//*Label 2089*/ GIMT_Encode4(111449),
39648 /* 110422 */ // Label 2081: @110422
39649 /* 110422 */ GIM_Try, /*On fail goto*//*Label 2091*/ GIMT_Encode4(110762),
39650 /* 110427 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
39651 /* 110430 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
39652 /* 110433 */ GIM_Try, /*On fail goto*//*Label 2092*/ GIMT_Encode4(110495), // Rule ID 6235 //
39653 /* 110438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
39654 /* 110441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
39655 /* 110445 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39656 /* 110449 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
39657 /* 110453 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39658 /* 110457 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39659 /* 110462 */ // MIs[1] Rn
39660 /* 110462 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
39661 /* 110467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39662 /* 110471 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39663 /* 110473 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39664 /* 110473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
39665 /* 110476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39666 /* 110478 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39667 /* 110480 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
39668 /* 110484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39669 /* 110487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39670 /* 110493 */ GIR_RootConstrainSelectedInstOperands,
39671 /* 110494 */ // GIR_Coverage, 6235,
39672 /* 110494 */ GIR_EraseRootFromParent_Done,
39673 /* 110495 */ // Label 2092: @110495
39674 /* 110495 */ GIM_Try, /*On fail goto*//*Label 2093*/ GIMT_Encode4(110557), // Rule ID 6269 //
39675 /* 110500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
39676 /* 110503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39677 /* 110507 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39678 /* 110511 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
39679 /* 110515 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39680 /* 110519 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39681 /* 110524 */ // MIs[1] Rn
39682 /* 110524 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
39683 /* 110529 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39684 /* 110533 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39685 /* 110535 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39686 /* 110535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
39687 /* 110538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39688 /* 110540 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39689 /* 110542 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
39690 /* 110546 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39691 /* 110549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39692 /* 110555 */ GIR_RootConstrainSelectedInstOperands,
39693 /* 110556 */ // GIR_Coverage, 6269,
39694 /* 110556 */ GIR_EraseRootFromParent_Done,
39695 /* 110557 */ // Label 2093: @110557
39696 /* 110557 */ GIM_Try, /*On fail goto*//*Label 2094*/ GIMT_Encode4(110619), // Rule ID 2056 //
39697 /* 110562 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
39698 /* 110565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
39699 /* 110569 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39700 /* 110573 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39701 /* 110577 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
39702 /* 110581 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39703 /* 110585 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39704 /* 110590 */ // MIs[1] Rn
39705 /* 110590 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
39706 /* 110595 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39707 /* 110597 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39708 /* 110597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
39709 /* 110600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39710 /* 110602 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
39711 /* 110604 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
39712 /* 110608 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39713 /* 110611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39714 /* 110617 */ GIR_RootConstrainSelectedInstOperands,
39715 /* 110618 */ // GIR_Coverage, 2056,
39716 /* 110618 */ GIR_EraseRootFromParent_Done,
39717 /* 110619 */ // Label 2094: @110619
39718 /* 110619 */ GIM_Try, /*On fail goto*//*Label 2095*/ GIMT_Encode4(110681), // Rule ID 2322 //
39719 /* 110624 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
39720 /* 110627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39721 /* 110631 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39722 /* 110635 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39723 /* 110639 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
39724 /* 110643 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39725 /* 110647 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39726 /* 110652 */ // MIs[1] Rn
39727 /* 110652 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
39728 /* 110657 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39729 /* 110659 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39730 /* 110659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
39731 /* 110662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39732 /* 110664 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
39733 /* 110666 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
39734 /* 110670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39735 /* 110673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39736 /* 110679 */ GIR_RootConstrainSelectedInstOperands,
39737 /* 110680 */ // GIR_Coverage, 2322,
39738 /* 110680 */ GIR_EraseRootFromParent_Done,
39739 /* 110681 */ // Label 2095: @110681
39740 /* 110681 */ GIM_Try, /*On fail goto*//*Label 2096*/ GIMT_Encode4(110721), // Rule ID 2054 //
39741 /* 110686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
39742 /* 110689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
39743 /* 110693 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39744 /* 110697 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39745 /* 110701 */ // (saddsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QADD:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
39746 /* 110701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD),
39747 /* 110704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39748 /* 110706 */ GIR_RootToRootCopy, /*OpIdx*/1, // a
39749 /* 110708 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
39750 /* 110710 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39751 /* 110713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39752 /* 110719 */ GIR_RootConstrainSelectedInstOperands,
39753 /* 110720 */ // GIR_Coverage, 2054,
39754 /* 110720 */ GIR_EraseRootFromParent_Done,
39755 /* 110721 */ // Label 2096: @110721
39756 /* 110721 */ GIM_Try, /*On fail goto*//*Label 2097*/ GIMT_Encode4(110761), // Rule ID 2320 //
39757 /* 110726 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
39758 /* 110729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39759 /* 110733 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39760 /* 110737 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39761 /* 110741 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39762 /* 110741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD),
39763 /* 110744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39764 /* 110746 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
39765 /* 110748 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
39766 /* 110750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39767 /* 110753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39768 /* 110759 */ GIR_RootConstrainSelectedInstOperands,
39769 /* 110760 */ // GIR_Coverage, 2320,
39770 /* 110760 */ GIR_EraseRootFromParent_Done,
39771 /* 110761 */ // Label 2097: @110761
39772 /* 110761 */ GIM_Reject,
39773 /* 110762 */ // Label 2091: @110762
39774 /* 110762 */ GIM_Reject,
39775 /* 110763 */ // Label 2082: @110763
39776 /* 110763 */ GIM_Try, /*On fail goto*//*Label 2098*/ GIMT_Encode4(110809), // Rule ID 942 //
39777 /* 110768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39778 /* 110771 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
39779 /* 110774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
39780 /* 110777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39781 /* 110781 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39782 /* 110785 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39783 /* 110789 */ // (saddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
39784 /* 110789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv1i64),
39785 /* 110792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39786 /* 110794 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39787 /* 110796 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39788 /* 110798 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39789 /* 110801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39790 /* 110807 */ GIR_RootConstrainSelectedInstOperands,
39791 /* 110808 */ // GIR_Coverage, 942,
39792 /* 110808 */ GIR_EraseRootFromParent_Done,
39793 /* 110809 */ // Label 2098: @110809
39794 /* 110809 */ GIM_Reject,
39795 /* 110810 */ // Label 2083: @110810
39796 /* 110810 */ GIM_Try, /*On fail goto*//*Label 2099*/ GIMT_Encode4(110856), // Rule ID 940 //
39797 /* 110815 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39798 /* 110818 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
39799 /* 110821 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
39800 /* 110824 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39801 /* 110828 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39802 /* 110832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39803 /* 110836 */ // (saddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
39804 /* 110836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i8),
39805 /* 110839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39806 /* 110841 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39807 /* 110843 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39808 /* 110845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39809 /* 110848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39810 /* 110854 */ GIR_RootConstrainSelectedInstOperands,
39811 /* 110855 */ // GIR_Coverage, 940,
39812 /* 110855 */ GIR_EraseRootFromParent_Done,
39813 /* 110856 */ // Label 2099: @110856
39814 /* 110856 */ GIM_Reject,
39815 /* 110857 */ // Label 2084: @110857
39816 /* 110857 */ GIM_Try, /*On fail goto*//*Label 2100*/ GIMT_Encode4(110970),
39817 /* 110862 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
39818 /* 110865 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
39819 /* 110868 */ GIM_Try, /*On fail goto*//*Label 2101*/ GIMT_Encode4(110908), // Rule ID 941 //
39820 /* 110873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39821 /* 110876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39822 /* 110880 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39823 /* 110884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39824 /* 110888 */ // (saddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
39825 /* 110888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv16i8),
39826 /* 110891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39827 /* 110893 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39828 /* 110895 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39829 /* 110897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39830 /* 110900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39831 /* 110906 */ GIR_RootConstrainSelectedInstOperands,
39832 /* 110907 */ // GIR_Coverage, 941,
39833 /* 110907 */ GIR_EraseRootFromParent_Done,
39834 /* 110908 */ // Label 2101: @110908
39835 /* 110908 */ GIM_Try, /*On fail goto*//*Label 2102*/ GIMT_Encode4(110969), // Rule ID 3895 //
39836 /* 110913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39837 /* 110916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39838 /* 110920 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39839 /* 110924 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39840 /* 110928 */ // (saddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
39841 /* 110928 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39842 /* 110931 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39843 /* 110935 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39844 /* 110940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs8),
39845 /* 110943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39846 /* 110945 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39847 /* 110947 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39848 /* 110949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39849 /* 110952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39850 /* 110958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39851 /* 110964 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39852 /* 110967 */ GIR_RootConstrainSelectedInstOperands,
39853 /* 110968 */ // GIR_Coverage, 3895,
39854 /* 110968 */ GIR_EraseRootFromParent_Done,
39855 /* 110969 */ // Label 2102: @110969
39856 /* 110969 */ GIM_Reject,
39857 /* 110970 */ // Label 2100: @110970
39858 /* 110970 */ GIM_Reject,
39859 /* 110971 */ // Label 2085: @110971
39860 /* 110971 */ GIM_Try, /*On fail goto*//*Label 2103*/ GIMT_Encode4(111017), // Rule ID 936 //
39861 /* 110976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39862 /* 110979 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
39863 /* 110982 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
39864 /* 110985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39865 /* 110989 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39866 /* 110993 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39867 /* 110997 */ // (saddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39868 /* 110997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i16),
39869 /* 111000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39870 /* 111002 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39871 /* 111004 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39872 /* 111006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39873 /* 111009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39874 /* 111015 */ GIR_RootConstrainSelectedInstOperands,
39875 /* 111016 */ // GIR_Coverage, 936,
39876 /* 111016 */ GIR_EraseRootFromParent_Done,
39877 /* 111017 */ // Label 2103: @111017
39878 /* 111017 */ GIM_Reject,
39879 /* 111018 */ // Label 2086: @111018
39880 /* 111018 */ GIM_Try, /*On fail goto*//*Label 2104*/ GIMT_Encode4(111131),
39881 /* 111023 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
39882 /* 111026 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
39883 /* 111029 */ GIM_Try, /*On fail goto*//*Label 2105*/ GIMT_Encode4(111069), // Rule ID 938 //
39884 /* 111034 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39885 /* 111037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39886 /* 111041 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39887 /* 111045 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39888 /* 111049 */ // (saddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
39889 /* 111049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i16),
39890 /* 111052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39891 /* 111054 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39892 /* 111056 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39893 /* 111058 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39894 /* 111061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39895 /* 111067 */ GIR_RootConstrainSelectedInstOperands,
39896 /* 111068 */ // GIR_Coverage, 938,
39897 /* 111068 */ GIR_EraseRootFromParent_Done,
39898 /* 111069 */ // Label 2105: @111069
39899 /* 111069 */ GIM_Try, /*On fail goto*//*Label 2106*/ GIMT_Encode4(111130), // Rule ID 3898 //
39900 /* 111074 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39901 /* 111077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39902 /* 111081 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39903 /* 111085 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39904 /* 111089 */ // (saddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
39905 /* 111089 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39906 /* 111092 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39907 /* 111096 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39908 /* 111101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs16),
39909 /* 111104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39910 /* 111106 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39911 /* 111108 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39912 /* 111110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39913 /* 111113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39914 /* 111119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39915 /* 111125 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39916 /* 111128 */ GIR_RootConstrainSelectedInstOperands,
39917 /* 111129 */ // GIR_Coverage, 3898,
39918 /* 111129 */ GIR_EraseRootFromParent_Done,
39919 /* 111130 */ // Label 2106: @111130
39920 /* 111130 */ GIM_Reject,
39921 /* 111131 */ // Label 2104: @111131
39922 /* 111131 */ GIM_Reject,
39923 /* 111132 */ // Label 2087: @111132
39924 /* 111132 */ GIM_Try, /*On fail goto*//*Label 2107*/ GIMT_Encode4(111178), // Rule ID 937 //
39925 /* 111137 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39926 /* 111140 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
39927 /* 111143 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
39928 /* 111146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39929 /* 111150 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39930 /* 111154 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39931 /* 111158 */ // (saddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
39932 /* 111158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i32),
39933 /* 111161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39934 /* 111163 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39935 /* 111165 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39936 /* 111167 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39937 /* 111170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39938 /* 111176 */ GIR_RootConstrainSelectedInstOperands,
39939 /* 111177 */ // GIR_Coverage, 937,
39940 /* 111177 */ GIR_EraseRootFromParent_Done,
39941 /* 111178 */ // Label 2107: @111178
39942 /* 111178 */ GIM_Reject,
39943 /* 111179 */ // Label 2088: @111179
39944 /* 111179 */ GIM_Try, /*On fail goto*//*Label 2108*/ GIMT_Encode4(111448),
39945 /* 111184 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
39946 /* 111187 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
39947 /* 111190 */ GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(111268), // Rule ID 6349 //
39948 /* 111195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39949 /* 111198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39950 /* 111202 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39951 /* 111206 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
39952 /* 111210 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
39953 /* 111213 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
39954 /* 111218 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
39955 /* 111222 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
39956 /* 111226 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39957 /* 111231 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39958 /* 111236 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39959 /* 111240 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39960 /* 111242 */ // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 4067:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39961 /* 111242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32),
39962 /* 111245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39963 /* 111247 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
39964 /* 111249 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
39965 /* 111253 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
39966 /* 111257 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39967 /* 111260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39968 /* 111266 */ GIR_RootConstrainSelectedInstOperands,
39969 /* 111267 */ // GIR_Coverage, 6349,
39970 /* 111267 */ GIR_EraseRootFromParent_Done,
39971 /* 111268 */ // Label 2109: @111268
39972 /* 111268 */ GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(111346), // Rule ID 2858 //
39973 /* 111273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39974 /* 111276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39975 /* 111280 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39976 /* 111284 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39977 /* 111288 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
39978 /* 111292 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
39979 /* 111295 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
39980 /* 111300 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
39981 /* 111304 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
39982 /* 111308 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39983 /* 111313 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39984 /* 111318 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39985 /* 111320 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 4067:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39986 /* 111320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32),
39987 /* 111323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39988 /* 111325 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
39989 /* 111327 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
39990 /* 111331 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
39991 /* 111335 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39992 /* 111338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39993 /* 111344 */ GIR_RootConstrainSelectedInstOperands,
39994 /* 111345 */ // GIR_Coverage, 2858,
39995 /* 111345 */ GIR_EraseRootFromParent_Done,
39996 /* 111346 */ // Label 2110: @111346
39997 /* 111346 */ GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(111386), // Rule ID 939 //
39998 /* 111351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39999 /* 111354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40000 /* 111358 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40001 /* 111362 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40002 /* 111366 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
40003 /* 111366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i32),
40004 /* 111369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40005 /* 111371 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40006 /* 111373 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40007 /* 111375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40008 /* 111378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40009 /* 111384 */ GIR_RootConstrainSelectedInstOperands,
40010 /* 111385 */ // GIR_Coverage, 939,
40011 /* 111385 */ GIR_EraseRootFromParent_Done,
40012 /* 111386 */ // Label 2111: @111386
40013 /* 111386 */ GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(111447), // Rule ID 3901 //
40014 /* 111391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40015 /* 111394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40016 /* 111398 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40017 /* 111402 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40018 /* 111406 */ // (saddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
40019 /* 111406 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40020 /* 111409 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40021 /* 111413 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40022 /* 111418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs32),
40023 /* 111421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40024 /* 111423 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
40025 /* 111425 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
40026 /* 111427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40027 /* 111430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40028 /* 111436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40029 /* 111442 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40030 /* 111445 */ GIR_RootConstrainSelectedInstOperands,
40031 /* 111446 */ // GIR_Coverage, 3901,
40032 /* 111446 */ GIR_EraseRootFromParent_Done,
40033 /* 111447 */ // Label 2112: @111447
40034 /* 111447 */ GIM_Reject,
40035 /* 111448 */ // Label 2108: @111448
40036 /* 111448 */ GIM_Reject,
40037 /* 111449 */ // Label 2089: @111449
40038 /* 111449 */ GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(111649),
40039 /* 111454 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
40040 /* 111457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
40041 /* 111460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40042 /* 111464 */ GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(111538), // Rule ID 6350 //
40043 /* 111469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40044 /* 111472 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40045 /* 111476 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
40046 /* 111480 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
40047 /* 111483 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
40048 /* 111488 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
40049 /* 111492 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
40050 /* 111496 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40051 /* 111501 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40052 /* 111506 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40053 /* 111510 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40054 /* 111512 */ // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 4067:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$src1) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
40055 /* 111512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64),
40056 /* 111515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40057 /* 111517 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
40058 /* 111519 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
40059 /* 111523 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
40060 /* 111527 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40061 /* 111530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40062 /* 111536 */ GIR_RootConstrainSelectedInstOperands,
40063 /* 111537 */ // GIR_Coverage, 6350,
40064 /* 111537 */ GIR_EraseRootFromParent_Done,
40065 /* 111538 */ // Label 2114: @111538
40066 /* 111538 */ GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(111612), // Rule ID 2859 //
40067 /* 111543 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40068 /* 111546 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40069 /* 111550 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40070 /* 111554 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
40071 /* 111558 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
40072 /* 111561 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
40073 /* 111566 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
40074 /* 111570 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
40075 /* 111574 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40076 /* 111579 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40077 /* 111584 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40078 /* 111586 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 4067:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
40079 /* 111586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64),
40080 /* 111589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40081 /* 111591 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
40082 /* 111593 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
40083 /* 111597 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
40084 /* 111601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40085 /* 111604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40086 /* 111610 */ GIR_RootConstrainSelectedInstOperands,
40087 /* 111611 */ // GIR_Coverage, 2859,
40088 /* 111611 */ GIR_EraseRootFromParent_Done,
40089 /* 111612 */ // Label 2115: @111612
40090 /* 111612 */ GIM_Try, /*On fail goto*//*Label 2116*/ GIMT_Encode4(111648), // Rule ID 943 //
40091 /* 111617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40092 /* 111620 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40093 /* 111624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40094 /* 111628 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
40095 /* 111628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i64),
40096 /* 111631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40097 /* 111633 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40098 /* 111635 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40099 /* 111637 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40100 /* 111640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40101 /* 111646 */ GIR_RootConstrainSelectedInstOperands,
40102 /* 111647 */ // GIR_Coverage, 943,
40103 /* 111647 */ GIR_EraseRootFromParent_Done,
40104 /* 111648 */ // Label 2116: @111648
40105 /* 111648 */ GIM_Reject,
40106 /* 111649 */ // Label 2113: @111649
40107 /* 111649 */ GIM_Reject,
40108 /* 111650 */ // Label 2090: @111650
40109 /* 111650 */ GIM_Reject,
40110 /* 111651 */ // Label 38: @111651
40111 /* 111651 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 2125*/ GIMT_Encode4(112287),
40112 /* 111662 */ /*GILLT_s64*//*Label 2117*/ GIMT_Encode4(111710), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
40113 /* 111682 */ /*GILLT_v8s8*//*Label 2118*/ GIMT_Encode4(111757),
40114 /* 111686 */ /*GILLT_v16s8*//*Label 2119*/ GIMT_Encode4(111804),
40115 /* 111690 */ /*GILLT_v4s16*//*Label 2120*/ GIMT_Encode4(111918),
40116 /* 111694 */ /*GILLT_v8s16*//*Label 2121*/ GIMT_Encode4(111965),
40117 /* 111698 */ /*GILLT_v2s32*//*Label 2122*/ GIMT_Encode4(112079),
40118 /* 111702 */ /*GILLT_v4s32*//*Label 2123*/ GIMT_Encode4(112126),
40119 /* 111706 */ /*GILLT_v2s64*//*Label 2124*/ GIMT_Encode4(112240),
40120 /* 111710 */ // Label 2117: @111710
40121 /* 111710 */ GIM_Try, /*On fail goto*//*Label 2126*/ GIMT_Encode4(111756), // Rule ID 1184 //
40122 /* 111715 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40123 /* 111718 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
40124 /* 111721 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
40125 /* 111724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40126 /* 111728 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40127 /* 111732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40128 /* 111736 */ // (usubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
40129 /* 111736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv1i64),
40130 /* 111739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40131 /* 111741 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40132 /* 111743 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40133 /* 111745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40134 /* 111748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40135 /* 111754 */ GIR_RootConstrainSelectedInstOperands,
40136 /* 111755 */ // GIR_Coverage, 1184,
40137 /* 111755 */ GIR_EraseRootFromParent_Done,
40138 /* 111756 */ // Label 2126: @111756
40139 /* 111756 */ GIM_Reject,
40140 /* 111757 */ // Label 2118: @111757
40141 /* 111757 */ GIM_Try, /*On fail goto*//*Label 2127*/ GIMT_Encode4(111803), // Rule ID 1182 //
40142 /* 111762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40143 /* 111765 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
40144 /* 111768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
40145 /* 111771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40146 /* 111775 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40147 /* 111779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40148 /* 111783 */ // (usubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
40149 /* 111783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i8),
40150 /* 111786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40151 /* 111788 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40152 /* 111790 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40153 /* 111792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40154 /* 111795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40155 /* 111801 */ GIR_RootConstrainSelectedInstOperands,
40156 /* 111802 */ // GIR_Coverage, 1182,
40157 /* 111802 */ GIR_EraseRootFromParent_Done,
40158 /* 111803 */ // Label 2127: @111803
40159 /* 111803 */ GIM_Reject,
40160 /* 111804 */ // Label 2119: @111804
40161 /* 111804 */ GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(111917),
40162 /* 111809 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
40163 /* 111812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
40164 /* 111815 */ GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(111855), // Rule ID 1183 //
40165 /* 111820 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40166 /* 111823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40167 /* 111827 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40168 /* 111831 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40169 /* 111835 */ // (usubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
40170 /* 111835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv16i8),
40171 /* 111838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40172 /* 111840 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40173 /* 111842 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40174 /* 111844 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40175 /* 111847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40176 /* 111853 */ GIR_RootConstrainSelectedInstOperands,
40177 /* 111854 */ // GIR_Coverage, 1183,
40178 /* 111854 */ GIR_EraseRootFromParent_Done,
40179 /* 111855 */ // Label 2129: @111855
40180 /* 111855 */ GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(111916), // Rule ID 3922 //
40181 /* 111860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40182 /* 111863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40183 /* 111867 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40184 /* 111871 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40185 /* 111875 */ // (usubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
40186 /* 111875 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40187 /* 111878 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40188 /* 111882 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40189 /* 111887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu8),
40190 /* 111890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40191 /* 111892 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
40192 /* 111894 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
40193 /* 111896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40194 /* 111899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40195 /* 111905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40196 /* 111911 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40197 /* 111914 */ GIR_RootConstrainSelectedInstOperands,
40198 /* 111915 */ // GIR_Coverage, 3922,
40199 /* 111915 */ GIR_EraseRootFromParent_Done,
40200 /* 111916 */ // Label 2130: @111916
40201 /* 111916 */ GIM_Reject,
40202 /* 111917 */ // Label 2128: @111917
40203 /* 111917 */ GIM_Reject,
40204 /* 111918 */ // Label 2120: @111918
40205 /* 111918 */ GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(111964), // Rule ID 1178 //
40206 /* 111923 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40207 /* 111926 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
40208 /* 111929 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
40209 /* 111932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40210 /* 111936 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40211 /* 111940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40212 /* 111944 */ // (usubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
40213 /* 111944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i16),
40214 /* 111947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40215 /* 111949 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40216 /* 111951 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40217 /* 111953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40218 /* 111956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40219 /* 111962 */ GIR_RootConstrainSelectedInstOperands,
40220 /* 111963 */ // GIR_Coverage, 1178,
40221 /* 111963 */ GIR_EraseRootFromParent_Done,
40222 /* 111964 */ // Label 2131: @111964
40223 /* 111964 */ GIM_Reject,
40224 /* 111965 */ // Label 2121: @111965
40225 /* 111965 */ GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(112078),
40226 /* 111970 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
40227 /* 111973 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
40228 /* 111976 */ GIM_Try, /*On fail goto*//*Label 2133*/ GIMT_Encode4(112016), // Rule ID 1180 //
40229 /* 111981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40230 /* 111984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40231 /* 111988 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40232 /* 111992 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40233 /* 111996 */ // (usubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
40234 /* 111996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i16),
40235 /* 111999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40236 /* 112001 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40237 /* 112003 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40238 /* 112005 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40239 /* 112008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40240 /* 112014 */ GIR_RootConstrainSelectedInstOperands,
40241 /* 112015 */ // GIR_Coverage, 1180,
40242 /* 112015 */ GIR_EraseRootFromParent_Done,
40243 /* 112016 */ // Label 2133: @112016
40244 /* 112016 */ GIM_Try, /*On fail goto*//*Label 2134*/ GIMT_Encode4(112077), // Rule ID 3925 //
40245 /* 112021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40246 /* 112024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40247 /* 112028 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40248 /* 112032 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40249 /* 112036 */ // (usubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
40250 /* 112036 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40251 /* 112039 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40252 /* 112043 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40253 /* 112048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu16),
40254 /* 112051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40255 /* 112053 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
40256 /* 112055 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
40257 /* 112057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40258 /* 112060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40259 /* 112066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40260 /* 112072 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40261 /* 112075 */ GIR_RootConstrainSelectedInstOperands,
40262 /* 112076 */ // GIR_Coverage, 3925,
40263 /* 112076 */ GIR_EraseRootFromParent_Done,
40264 /* 112077 */ // Label 2134: @112077
40265 /* 112077 */ GIM_Reject,
40266 /* 112078 */ // Label 2132: @112078
40267 /* 112078 */ GIM_Reject,
40268 /* 112079 */ // Label 2122: @112079
40269 /* 112079 */ GIM_Try, /*On fail goto*//*Label 2135*/ GIMT_Encode4(112125), // Rule ID 1179 //
40270 /* 112084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40271 /* 112087 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
40272 /* 112090 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
40273 /* 112093 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40274 /* 112097 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40275 /* 112101 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40276 /* 112105 */ // (usubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
40277 /* 112105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i32),
40278 /* 112108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40279 /* 112110 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40280 /* 112112 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40281 /* 112114 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40282 /* 112117 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40283 /* 112123 */ GIR_RootConstrainSelectedInstOperands,
40284 /* 112124 */ // GIR_Coverage, 1179,
40285 /* 112124 */ GIR_EraseRootFromParent_Done,
40286 /* 112125 */ // Label 2135: @112125
40287 /* 112125 */ GIM_Reject,
40288 /* 112126 */ // Label 2123: @112126
40289 /* 112126 */ GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(112239),
40290 /* 112131 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
40291 /* 112134 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
40292 /* 112137 */ GIM_Try, /*On fail goto*//*Label 2137*/ GIMT_Encode4(112177), // Rule ID 1181 //
40293 /* 112142 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40294 /* 112145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40295 /* 112149 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40296 /* 112153 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40297 /* 112157 */ // (usubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
40298 /* 112157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i32),
40299 /* 112160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40300 /* 112162 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40301 /* 112164 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40302 /* 112166 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40303 /* 112169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40304 /* 112175 */ GIR_RootConstrainSelectedInstOperands,
40305 /* 112176 */ // GIR_Coverage, 1181,
40306 /* 112176 */ GIR_EraseRootFromParent_Done,
40307 /* 112177 */ // Label 2137: @112177
40308 /* 112177 */ GIM_Try, /*On fail goto*//*Label 2138*/ GIMT_Encode4(112238), // Rule ID 3928 //
40309 /* 112182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40310 /* 112185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40311 /* 112189 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40312 /* 112193 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40313 /* 112197 */ // (usubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
40314 /* 112197 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40315 /* 112200 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40316 /* 112204 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40317 /* 112209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu32),
40318 /* 112212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40319 /* 112214 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
40320 /* 112216 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
40321 /* 112218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40322 /* 112221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40323 /* 112227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40324 /* 112233 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40325 /* 112236 */ GIR_RootConstrainSelectedInstOperands,
40326 /* 112237 */ // GIR_Coverage, 3928,
40327 /* 112237 */ GIR_EraseRootFromParent_Done,
40328 /* 112238 */ // Label 2138: @112238
40329 /* 112238 */ GIM_Reject,
40330 /* 112239 */ // Label 2136: @112239
40331 /* 112239 */ GIM_Reject,
40332 /* 112240 */ // Label 2124: @112240
40333 /* 112240 */ GIM_Try, /*On fail goto*//*Label 2139*/ GIMT_Encode4(112286), // Rule ID 1185 //
40334 /* 112245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40335 /* 112248 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
40336 /* 112251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
40337 /* 112254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40338 /* 112258 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40339 /* 112262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40340 /* 112266 */ // (usubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
40341 /* 112266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i64),
40342 /* 112269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40343 /* 112271 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40344 /* 112273 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40345 /* 112275 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40346 /* 112278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40347 /* 112284 */ GIR_RootConstrainSelectedInstOperands,
40348 /* 112285 */ // GIR_Coverage, 1185,
40349 /* 112285 */ GIR_EraseRootFromParent_Done,
40350 /* 112286 */ // Label 2139: @112286
40351 /* 112286 */ GIM_Reject,
40352 /* 112287 */ // Label 2125: @112287
40353 /* 112287 */ GIM_Reject,
40354 /* 112288 */ // Label 39: @112288
40355 /* 112288 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 2149*/ GIMT_Encode4(113299),
40356 /* 112299 */ /*GILLT_s32*//*Label 2140*/ GIMT_Encode4(112351),
40357 /* 112303 */ /*GILLT_s64*//*Label 2141*/ GIMT_Encode4(112568), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
40358 /* 112323 */ /*GILLT_v8s8*//*Label 2142*/ GIMT_Encode4(112615),
40359 /* 112327 */ /*GILLT_v16s8*//*Label 2143*/ GIMT_Encode4(112662),
40360 /* 112331 */ /*GILLT_v4s16*//*Label 2144*/ GIMT_Encode4(112776),
40361 /* 112335 */ /*GILLT_v8s16*//*Label 2145*/ GIMT_Encode4(112823),
40362 /* 112339 */ /*GILLT_v2s32*//*Label 2146*/ GIMT_Encode4(112937),
40363 /* 112343 */ /*GILLT_v4s32*//*Label 2147*/ GIMT_Encode4(112984),
40364 /* 112347 */ /*GILLT_v2s64*//*Label 2148*/ GIMT_Encode4(113176),
40365 /* 112351 */ // Label 2140: @112351
40366 /* 112351 */ GIM_Try, /*On fail goto*//*Label 2150*/ GIMT_Encode4(112567),
40367 /* 112356 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
40368 /* 112359 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
40369 /* 112362 */ GIM_Try, /*On fail goto*//*Label 2151*/ GIMT_Encode4(112424), // Rule ID 2057 //
40370 /* 112367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
40371 /* 112370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
40372 /* 112374 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40373 /* 112378 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40374 /* 112382 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
40375 /* 112386 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40376 /* 112390 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40377 /* 112395 */ // MIs[1] Rn
40378 /* 112395 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
40379 /* 112400 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40380 /* 112402 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
40381 /* 112402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB),
40382 /* 112405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
40383 /* 112407 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
40384 /* 112409 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
40385 /* 112413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40386 /* 112416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40387 /* 112422 */ GIR_RootConstrainSelectedInstOperands,
40388 /* 112423 */ // GIR_Coverage, 2057,
40389 /* 112423 */ GIR_EraseRootFromParent_Done,
40390 /* 112424 */ // Label 2151: @112424
40391 /* 112424 */ GIM_Try, /*On fail goto*//*Label 2152*/ GIMT_Encode4(112486), // Rule ID 2323 //
40392 /* 112429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
40393 /* 112432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40394 /* 112436 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40395 /* 112440 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40396 /* 112444 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
40397 /* 112448 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40398 /* 112452 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40399 /* 112457 */ // MIs[1] Rn
40400 /* 112457 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
40401 /* 112462 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40402 /* 112464 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
40403 /* 112464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB),
40404 /* 112467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
40405 /* 112469 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
40406 /* 112471 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
40407 /* 112475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40408 /* 112478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40409 /* 112484 */ GIR_RootConstrainSelectedInstOperands,
40410 /* 112485 */ // GIR_Coverage, 2323,
40411 /* 112485 */ GIR_EraseRootFromParent_Done,
40412 /* 112486 */ // Label 2152: @112486
40413 /* 112486 */ GIM_Try, /*On fail goto*//*Label 2153*/ GIMT_Encode4(112526), // Rule ID 2055 //
40414 /* 112491 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
40415 /* 112494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
40416 /* 112498 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
40417 /* 112502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
40418 /* 112506 */ // (ssubsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QSUB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
40419 /* 112506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB),
40420 /* 112509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
40421 /* 112511 */ GIR_RootToRootCopy, /*OpIdx*/1, // a
40422 /* 112513 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
40423 /* 112515 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40424 /* 112518 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40425 /* 112524 */ GIR_RootConstrainSelectedInstOperands,
40426 /* 112525 */ // GIR_Coverage, 2055,
40427 /* 112525 */ GIR_EraseRootFromParent_Done,
40428 /* 112526 */ // Label 2153: @112526
40429 /* 112526 */ GIM_Try, /*On fail goto*//*Label 2154*/ GIMT_Encode4(112566), // Rule ID 2321 //
40430 /* 112531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
40431 /* 112534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40432 /* 112538 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40433 /* 112542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40434 /* 112546 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
40435 /* 112546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB),
40436 /* 112549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
40437 /* 112551 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
40438 /* 112553 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
40439 /* 112555 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40440 /* 112558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40441 /* 112564 */ GIR_RootConstrainSelectedInstOperands,
40442 /* 112565 */ // GIR_Coverage, 2321,
40443 /* 112565 */ GIR_EraseRootFromParent_Done,
40444 /* 112566 */ // Label 2154: @112566
40445 /* 112566 */ GIM_Reject,
40446 /* 112567 */ // Label 2150: @112567
40447 /* 112567 */ GIM_Reject,
40448 /* 112568 */ // Label 2141: @112568
40449 /* 112568 */ GIM_Try, /*On fail goto*//*Label 2155*/ GIMT_Encode4(112614), // Rule ID 1176 //
40450 /* 112573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40451 /* 112576 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
40452 /* 112579 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
40453 /* 112582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40454 /* 112586 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40455 /* 112590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40456 /* 112594 */ // (ssubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
40457 /* 112594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv1i64),
40458 /* 112597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40459 /* 112599 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40460 /* 112601 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40461 /* 112603 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40462 /* 112606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40463 /* 112612 */ GIR_RootConstrainSelectedInstOperands,
40464 /* 112613 */ // GIR_Coverage, 1176,
40465 /* 112613 */ GIR_EraseRootFromParent_Done,
40466 /* 112614 */ // Label 2155: @112614
40467 /* 112614 */ GIM_Reject,
40468 /* 112615 */ // Label 2142: @112615
40469 /* 112615 */ GIM_Try, /*On fail goto*//*Label 2156*/ GIMT_Encode4(112661), // Rule ID 1174 //
40470 /* 112620 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40471 /* 112623 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
40472 /* 112626 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
40473 /* 112629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40474 /* 112633 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40475 /* 112637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40476 /* 112641 */ // (ssubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
40477 /* 112641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i8),
40478 /* 112644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40479 /* 112646 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40480 /* 112648 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40481 /* 112650 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40482 /* 112653 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40483 /* 112659 */ GIR_RootConstrainSelectedInstOperands,
40484 /* 112660 */ // GIR_Coverage, 1174,
40485 /* 112660 */ GIR_EraseRootFromParent_Done,
40486 /* 112661 */ // Label 2156: @112661
40487 /* 112661 */ GIM_Reject,
40488 /* 112662 */ // Label 2143: @112662
40489 /* 112662 */ GIM_Try, /*On fail goto*//*Label 2157*/ GIMT_Encode4(112775),
40490 /* 112667 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
40491 /* 112670 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
40492 /* 112673 */ GIM_Try, /*On fail goto*//*Label 2158*/ GIMT_Encode4(112713), // Rule ID 1175 //
40493 /* 112678 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40494 /* 112681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40495 /* 112685 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40496 /* 112689 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40497 /* 112693 */ // (ssubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
40498 /* 112693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv16i8),
40499 /* 112696 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40500 /* 112698 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40501 /* 112700 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40502 /* 112702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40503 /* 112705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40504 /* 112711 */ GIR_RootConstrainSelectedInstOperands,
40505 /* 112712 */ // GIR_Coverage, 1175,
40506 /* 112712 */ GIR_EraseRootFromParent_Done,
40507 /* 112713 */ // Label 2158: @112713
40508 /* 112713 */ GIM_Try, /*On fail goto*//*Label 2159*/ GIMT_Encode4(112774), // Rule ID 3913 //
40509 /* 112718 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40510 /* 112721 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40511 /* 112725 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40512 /* 112729 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40513 /* 112733 */ // (ssubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
40514 /* 112733 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40515 /* 112736 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40516 /* 112740 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40517 /* 112745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs8),
40518 /* 112748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40519 /* 112750 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
40520 /* 112752 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
40521 /* 112754 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40522 /* 112757 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40523 /* 112763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40524 /* 112769 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40525 /* 112772 */ GIR_RootConstrainSelectedInstOperands,
40526 /* 112773 */ // GIR_Coverage, 3913,
40527 /* 112773 */ GIR_EraseRootFromParent_Done,
40528 /* 112774 */ // Label 2159: @112774
40529 /* 112774 */ GIM_Reject,
40530 /* 112775 */ // Label 2157: @112775
40531 /* 112775 */ GIM_Reject,
40532 /* 112776 */ // Label 2144: @112776
40533 /* 112776 */ GIM_Try, /*On fail goto*//*Label 2160*/ GIMT_Encode4(112822), // Rule ID 1170 //
40534 /* 112781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40535 /* 112784 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
40536 /* 112787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
40537 /* 112790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40538 /* 112794 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40539 /* 112798 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40540 /* 112802 */ // (ssubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
40541 /* 112802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i16),
40542 /* 112805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40543 /* 112807 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40544 /* 112809 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40545 /* 112811 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40546 /* 112814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40547 /* 112820 */ GIR_RootConstrainSelectedInstOperands,
40548 /* 112821 */ // GIR_Coverage, 1170,
40549 /* 112821 */ GIR_EraseRootFromParent_Done,
40550 /* 112822 */ // Label 2160: @112822
40551 /* 112822 */ GIM_Reject,
40552 /* 112823 */ // Label 2145: @112823
40553 /* 112823 */ GIM_Try, /*On fail goto*//*Label 2161*/ GIMT_Encode4(112936),
40554 /* 112828 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
40555 /* 112831 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
40556 /* 112834 */ GIM_Try, /*On fail goto*//*Label 2162*/ GIMT_Encode4(112874), // Rule ID 1172 //
40557 /* 112839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40558 /* 112842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40559 /* 112846 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40560 /* 112850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40561 /* 112854 */ // (ssubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
40562 /* 112854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i16),
40563 /* 112857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40564 /* 112859 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40565 /* 112861 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40566 /* 112863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40567 /* 112866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40568 /* 112872 */ GIR_RootConstrainSelectedInstOperands,
40569 /* 112873 */ // GIR_Coverage, 1172,
40570 /* 112873 */ GIR_EraseRootFromParent_Done,
40571 /* 112874 */ // Label 2162: @112874
40572 /* 112874 */ GIM_Try, /*On fail goto*//*Label 2163*/ GIMT_Encode4(112935), // Rule ID 3916 //
40573 /* 112879 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40574 /* 112882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40575 /* 112886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40576 /* 112890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40577 /* 112894 */ // (ssubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
40578 /* 112894 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40579 /* 112897 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40580 /* 112901 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40581 /* 112906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs16),
40582 /* 112909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40583 /* 112911 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
40584 /* 112913 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
40585 /* 112915 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40586 /* 112918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40587 /* 112924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40588 /* 112930 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40589 /* 112933 */ GIR_RootConstrainSelectedInstOperands,
40590 /* 112934 */ // GIR_Coverage, 3916,
40591 /* 112934 */ GIR_EraseRootFromParent_Done,
40592 /* 112935 */ // Label 2163: @112935
40593 /* 112935 */ GIM_Reject,
40594 /* 112936 */ // Label 2161: @112936
40595 /* 112936 */ GIM_Reject,
40596 /* 112937 */ // Label 2146: @112937
40597 /* 112937 */ GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(112983), // Rule ID 1171 //
40598 /* 112942 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40599 /* 112945 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
40600 /* 112948 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
40601 /* 112951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40602 /* 112955 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40603 /* 112959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40604 /* 112963 */ // (ssubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
40605 /* 112963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i32),
40606 /* 112966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40607 /* 112968 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40608 /* 112970 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40609 /* 112972 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40610 /* 112975 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40611 /* 112981 */ GIR_RootConstrainSelectedInstOperands,
40612 /* 112982 */ // GIR_Coverage, 1171,
40613 /* 112982 */ GIR_EraseRootFromParent_Done,
40614 /* 112983 */ // Label 2164: @112983
40615 /* 112983 */ GIM_Reject,
40616 /* 112984 */ // Label 2147: @112984
40617 /* 112984 */ GIM_Try, /*On fail goto*//*Label 2165*/ GIMT_Encode4(113175),
40618 /* 112989 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
40619 /* 112992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
40620 /* 112995 */ GIM_Try, /*On fail goto*//*Label 2166*/ GIMT_Encode4(113073), // Rule ID 2868 //
40621 /* 113000 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40622 /* 113003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40623 /* 113007 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40624 /* 113011 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40625 /* 113015 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
40626 /* 113019 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
40627 /* 113022 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
40628 /* 113027 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
40629 /* 113031 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
40630 /* 113035 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40631 /* 113040 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40632 /* 113045 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40633 /* 113047 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 4067:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLSLv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
40634 /* 113047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv4i32),
40635 /* 113050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40636 /* 113052 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
40637 /* 113054 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
40638 /* 113058 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
40639 /* 113062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40640 /* 113065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40641 /* 113071 */ GIR_RootConstrainSelectedInstOperands,
40642 /* 113072 */ // GIR_Coverage, 2868,
40643 /* 113072 */ GIR_EraseRootFromParent_Done,
40644 /* 113073 */ // Label 2166: @113073
40645 /* 113073 */ GIM_Try, /*On fail goto*//*Label 2167*/ GIMT_Encode4(113113), // Rule ID 1173 //
40646 /* 113078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40647 /* 113081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40648 /* 113085 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40649 /* 113089 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40650 /* 113093 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
40651 /* 113093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i32),
40652 /* 113096 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40653 /* 113098 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40654 /* 113100 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40655 /* 113102 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40656 /* 113105 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40657 /* 113111 */ GIR_RootConstrainSelectedInstOperands,
40658 /* 113112 */ // GIR_Coverage, 1173,
40659 /* 113112 */ GIR_EraseRootFromParent_Done,
40660 /* 113113 */ // Label 2167: @113113
40661 /* 113113 */ GIM_Try, /*On fail goto*//*Label 2168*/ GIMT_Encode4(113174), // Rule ID 3919 //
40662 /* 113118 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40663 /* 113121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40664 /* 113125 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40665 /* 113129 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40666 /* 113133 */ // (ssubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
40667 /* 113133 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40668 /* 113136 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40669 /* 113140 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40670 /* 113145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs32),
40671 /* 113148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40672 /* 113150 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
40673 /* 113152 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
40674 /* 113154 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40675 /* 113157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40676 /* 113163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40677 /* 113169 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40678 /* 113172 */ GIR_RootConstrainSelectedInstOperands,
40679 /* 113173 */ // GIR_Coverage, 3919,
40680 /* 113173 */ GIR_EraseRootFromParent_Done,
40681 /* 113174 */ // Label 2168: @113174
40682 /* 113174 */ GIM_Reject,
40683 /* 113175 */ // Label 2165: @113175
40684 /* 113175 */ GIM_Reject,
40685 /* 113176 */ // Label 2148: @113176
40686 /* 113176 */ GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(113298),
40687 /* 113181 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
40688 /* 113184 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
40689 /* 113187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40690 /* 113191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40691 /* 113195 */ GIM_Try, /*On fail goto*//*Label 2170*/ GIMT_Encode4(113265), // Rule ID 2869 //
40692 /* 113200 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40693 /* 113203 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40694 /* 113207 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
40695 /* 113211 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
40696 /* 113214 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
40697 /* 113219 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
40698 /* 113223 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
40699 /* 113227 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40700 /* 113232 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40701 /* 113237 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40702 /* 113239 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 4067:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLSLv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
40703 /* 113239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv2i64),
40704 /* 113242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40705 /* 113244 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
40706 /* 113246 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
40707 /* 113250 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
40708 /* 113254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40709 /* 113257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40710 /* 113263 */ GIR_RootConstrainSelectedInstOperands,
40711 /* 113264 */ // GIR_Coverage, 2869,
40712 /* 113264 */ GIR_EraseRootFromParent_Done,
40713 /* 113265 */ // Label 2170: @113265
40714 /* 113265 */ GIM_Try, /*On fail goto*//*Label 2171*/ GIMT_Encode4(113297), // Rule ID 1177 //
40715 /* 113270 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40716 /* 113273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40717 /* 113277 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
40718 /* 113277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i64),
40719 /* 113280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40720 /* 113282 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40721 /* 113284 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40722 /* 113286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40723 /* 113289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40724 /* 113295 */ GIR_RootConstrainSelectedInstOperands,
40725 /* 113296 */ // GIR_Coverage, 1177,
40726 /* 113296 */ GIR_EraseRootFromParent_Done,
40727 /* 113297 */ // Label 2171: @113297
40728 /* 113297 */ GIM_Reject,
40729 /* 113298 */ // Label 2169: @113298
40730 /* 113298 */ GIM_Reject,
40731 /* 113299 */ // Label 2149: @113299
40732 /* 113299 */ GIM_Reject,
40733 /* 113300 */ // Label 40: @113300
40734 /* 113300 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2179*/ GIMT_Encode4(115652),
40735 /* 113311 */ /*GILLT_s16*//*Label 2172*/ GIMT_Encode4(113363),
40736 /* 113315 */ /*GILLT_s32*//*Label 2173*/ GIMT_Encode4(113410),
40737 /* 113319 */ /*GILLT_s64*//*Label 2174*/ GIMT_Encode4(115005), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
40738 /* 113347 */ /*GILLT_v4s16*//*Label 2175*/ GIMT_Encode4(115052),
40739 /* 113351 */ /*GILLT_v8s16*//*Label 2176*/ GIMT_Encode4(115237),
40740 /* 113355 */ /*GILLT_v2s32*//*Label 2177*/ GIMT_Encode4(115491),
40741 /* 113359 */ /*GILLT_v4s32*//*Label 2178*/ GIMT_Encode4(115538),
40742 /* 113363 */ // Label 2172: @113363
40743 /* 113363 */ GIM_Try, /*On fail goto*//*Label 2180*/ GIMT_Encode4(113409), // Rule ID 621 //
40744 /* 113368 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
40745 /* 113371 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
40746 /* 113374 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
40747 /* 113377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40748 /* 113381 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40749 /* 113385 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40750 /* 113389 */ // (fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40751 /* 113389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH),
40752 /* 113392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40753 /* 113394 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
40754 /* 113396 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
40755 /* 113398 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40756 /* 113401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40757 /* 113407 */ GIR_RootConstrainSelectedInstOperands,
40758 /* 113408 */ // GIR_Coverage, 621,
40759 /* 113408 */ GIR_EraseRootFromParent_Done,
40760 /* 113409 */ // Label 2180: @113409
40761 /* 113409 */ GIM_Reject,
40762 /* 113410 */ // Label 2173: @113410
40763 /* 113410 */ GIM_Try, /*On fail goto*//*Label 2181*/ GIMT_Encode4(115004),
40764 /* 113415 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
40765 /* 113418 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
40766 /* 113421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40767 /* 113425 */ GIM_Try, /*On fail goto*//*Label 2182*/ GIMT_Encode4(113753), // Rule ID 6529 //
40768 /* 113430 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP),
40769 /* 113433 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40770 /* 113437 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
40771 /* 113441 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40772 /* 113445 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40773 /* 113449 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40774 /* 113454 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40775 /* 113459 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40776 /* 113463 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40777 /* 113465 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40778 /* 113465 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
40779 /* 113468 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40780 /* 113472 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40781 /* 113477 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
40782 /* 113479 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
40783 /* 113482 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40784 /* 113486 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40785 /* 113491 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
40786 /* 113494 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40787 /* 113499 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
40788 /* 113502 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40789 /* 113506 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40790 /* 113511 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
40791 /* 113514 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
40792 /* 113518 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
40793 /* 113521 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40794 /* 113526 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40795 /* 113531 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40796 /* 113536 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40797 /* 113539 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40798 /* 113543 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40799 /* 113548 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40800 /* 113550 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40801 /* 113553 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40802 /* 113557 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40803 /* 113562 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
40804 /* 113565 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40805 /* 113570 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40806 /* 113573 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40807 /* 113577 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40808 /* 113582 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
40809 /* 113585 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
40810 /* 113589 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
40811 /* 113592 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40812 /* 113597 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40813 /* 113602 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40814 /* 113607 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40815 /* 113610 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40816 /* 113614 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40817 /* 113619 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40818 /* 113621 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40819 /* 113624 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40820 /* 113628 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40821 /* 113633 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
40822 /* 113636 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40823 /* 113641 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40824 /* 113644 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40825 /* 113648 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40826 /* 113653 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
40827 /* 113656 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc
40828 /* 113660 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
40829 /* 113663 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40830 /* 113668 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40831 /* 113673 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40832 /* 113678 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40833 /* 113681 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd),
40834 /* 113685 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40835 /* 113690 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
40836 /* 113693 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
40837 /* 113696 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
40838 /* 113699 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
40839 /* 113702 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40840 /* 113708 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40841 /* 113710 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40842 /* 113713 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40843 /* 113717 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40844 /* 113722 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
40845 /* 113725 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40846 /* 113730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40847 /* 113733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40848 /* 113735 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
40849 /* 113742 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
40850 /* 113747 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40851 /* 113752 */ // GIR_Coverage, 6529,
40852 /* 113752 */ GIR_EraseRootFromParent_Done,
40853 /* 113753 */ // Label 2182: @113753
40854 /* 113753 */ GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(114081), // Rule ID 6530 //
40855 /* 113758 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP),
40856 /* 113761 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40857 /* 113765 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
40858 /* 113769 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40859 /* 113773 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40860 /* 113777 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40861 /* 113782 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40862 /* 113787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40863 /* 113791 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40864 /* 113793 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40865 /* 113793 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
40866 /* 113796 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40867 /* 113800 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40868 /* 113805 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
40869 /* 113807 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
40870 /* 113810 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40871 /* 113814 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40872 /* 113819 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
40873 /* 113822 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40874 /* 113827 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
40875 /* 113830 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40876 /* 113834 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40877 /* 113839 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
40878 /* 113842 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
40879 /* 113846 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
40880 /* 113849 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40881 /* 113854 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40882 /* 113859 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40883 /* 113864 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40884 /* 113867 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40885 /* 113871 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40886 /* 113876 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40887 /* 113878 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40888 /* 113881 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40889 /* 113885 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40890 /* 113890 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
40891 /* 113893 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40892 /* 113898 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40893 /* 113901 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40894 /* 113905 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40895 /* 113910 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
40896 /* 113913 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
40897 /* 113917 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
40898 /* 113920 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40899 /* 113925 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40900 /* 113930 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40901 /* 113935 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40902 /* 113938 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40903 /* 113942 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40904 /* 113947 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40905 /* 113949 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40906 /* 113952 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40907 /* 113956 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40908 /* 113961 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
40909 /* 113964 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40910 /* 113969 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40911 /* 113972 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40912 /* 113976 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40913 /* 113981 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
40914 /* 113984 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc
40915 /* 113988 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
40916 /* 113991 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40917 /* 113996 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40918 /* 114001 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40919 /* 114006 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40920 /* 114009 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd),
40921 /* 114013 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40922 /* 114018 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
40923 /* 114021 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
40924 /* 114024 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
40925 /* 114027 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
40926 /* 114030 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40927 /* 114036 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40928 /* 114038 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40929 /* 114041 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40930 /* 114045 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40931 /* 114050 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
40932 /* 114053 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40933 /* 114058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40934 /* 114061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40935 /* 114063 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
40936 /* 114070 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
40937 /* 114075 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40938 /* 114080 */ // GIR_Coverage, 6530,
40939 /* 114080 */ GIR_EraseRootFromParent_Done,
40940 /* 114081 */ // Label 2183: @114081
40941 /* 114081 */ GIM_Try, /*On fail goto*//*Label 2184*/ GIMT_Encode4(114409), // Rule ID 3075 //
40942 /* 114086 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP),
40943 /* 114089 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40944 /* 114093 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40945 /* 114097 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
40946 /* 114101 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40947 /* 114105 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40948 /* 114109 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40949 /* 114114 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40950 /* 114119 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40951 /* 114121 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40952 /* 114121 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
40953 /* 114124 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40954 /* 114128 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40955 /* 114133 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
40956 /* 114135 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
40957 /* 114138 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40958 /* 114142 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40959 /* 114147 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
40960 /* 114150 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40961 /* 114155 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
40962 /* 114158 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40963 /* 114162 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40964 /* 114167 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
40965 /* 114170 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
40966 /* 114174 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
40967 /* 114177 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40968 /* 114182 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40969 /* 114187 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40970 /* 114192 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
40971 /* 114195 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40972 /* 114199 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40973 /* 114204 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
40974 /* 114206 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
40975 /* 114209 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40976 /* 114213 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40977 /* 114218 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
40978 /* 114221 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40979 /* 114226 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
40980 /* 114229 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40981 /* 114233 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40982 /* 114238 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
40983 /* 114241 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
40984 /* 114245 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
40985 /* 114248 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40986 /* 114253 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40987 /* 114258 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40988 /* 114263 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40989 /* 114266 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40990 /* 114270 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40991 /* 114275 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40992 /* 114277 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40993 /* 114280 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40994 /* 114284 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40995 /* 114289 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
40996 /* 114292 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40997 /* 114297 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40998 /* 114300 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40999 /* 114304 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41000 /* 114309 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41001 /* 114312 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
41002 /* 114316 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41003 /* 114319 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41004 /* 114324 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41005 /* 114329 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41006 /* 114334 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41007 /* 114337 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd),
41008 /* 114341 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41009 /* 114346 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41010 /* 114349 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41011 /* 114352 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
41012 /* 114355 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41013 /* 114358 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41014 /* 114364 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41015 /* 114366 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41016 /* 114369 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41017 /* 114373 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41018 /* 114378 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41019 /* 114381 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41020 /* 114386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41021 /* 114389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41022 /* 114391 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41023 /* 114398 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41024 /* 114403 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41025 /* 114408 */ // GIR_Coverage, 3075,
41026 /* 114408 */ GIR_EraseRootFromParent_Done,
41027 /* 114409 */ // Label 2184: @114409
41028 /* 114409 */ GIM_Try, /*On fail goto*//*Label 2185*/ GIMT_Encode4(114737), // Rule ID 3077 //
41029 /* 114414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP),
41030 /* 114417 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41031 /* 114421 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41032 /* 114425 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41033 /* 114429 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41034 /* 114433 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41035 /* 114437 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41036 /* 114442 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41037 /* 114447 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41038 /* 114449 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41039 /* 114449 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
41040 /* 114452 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41041 /* 114456 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41042 /* 114461 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
41043 /* 114463 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
41044 /* 114466 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41045 /* 114470 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41046 /* 114475 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
41047 /* 114478 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41048 /* 114483 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
41049 /* 114486 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41050 /* 114490 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41051 /* 114495 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
41052 /* 114498 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
41053 /* 114502 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
41054 /* 114505 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41055 /* 114510 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41056 /* 114515 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41057 /* 114520 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41058 /* 114523 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41059 /* 114527 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41060 /* 114532 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41061 /* 114534 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41062 /* 114537 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41063 /* 114541 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41064 /* 114546 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41065 /* 114549 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41066 /* 114554 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41067 /* 114557 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41068 /* 114561 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41069 /* 114566 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41070 /* 114569 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
41071 /* 114573 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41072 /* 114576 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41073 /* 114581 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41074 /* 114586 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41075 /* 114591 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41076 /* 114594 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41077 /* 114598 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41078 /* 114603 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41079 /* 114605 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41080 /* 114608 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41081 /* 114612 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41082 /* 114617 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41083 /* 114620 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41084 /* 114625 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41085 /* 114628 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41086 /* 114632 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41087 /* 114637 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41088 /* 114640 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
41089 /* 114644 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41090 /* 114647 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41091 /* 114652 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41092 /* 114657 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41093 /* 114662 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41094 /* 114665 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd),
41095 /* 114669 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41096 /* 114674 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41097 /* 114677 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41098 /* 114680 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
41099 /* 114683 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41100 /* 114686 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41101 /* 114692 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41102 /* 114694 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41103 /* 114697 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41104 /* 114701 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41105 /* 114706 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41106 /* 114709 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41107 /* 114714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41108 /* 114717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41109 /* 114719 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41110 /* 114726 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41111 /* 114731 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41112 /* 114736 */ // GIR_Coverage, 3077,
41113 /* 114736 */ GIR_EraseRootFromParent_Done,
41114 /* 114737 */ // Label 2185: @114737
41115 /* 114737 */ GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(114773), // Rule ID 619 //
41116 /* 114742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
41117 /* 114745 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41118 /* 114749 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41119 /* 114753 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41120 /* 114753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS),
41121 /* 114756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
41122 /* 114758 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
41123 /* 114760 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
41124 /* 114762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41125 /* 114765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41126 /* 114771 */ GIR_RootConstrainSelectedInstOperands,
41127 /* 114772 */ // GIR_Coverage, 619,
41128 /* 114772 */ GIR_EraseRootFromParent_Done,
41129 /* 114773 */ // Label 2186: @114773
41130 /* 114773 */ GIM_Try, /*On fail goto*//*Label 2187*/ GIMT_Encode4(115003), // Rule ID 3072 //
41131 /* 114778 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
41132 /* 114781 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41133 /* 114785 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41134 /* 114789 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VADDfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41135 /* 114789 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41136 /* 114792 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41137 /* 114796 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41138 /* 114801 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41139 /* 114803 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41140 /* 114806 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41141 /* 114810 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41142 /* 114815 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41143 /* 114818 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41144 /* 114823 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41145 /* 114826 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41146 /* 114830 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41147 /* 114835 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41148 /* 114838 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
41149 /* 114842 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41150 /* 114845 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41151 /* 114850 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41152 /* 114855 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41153 /* 114860 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41154 /* 114863 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41155 /* 114867 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41156 /* 114872 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41157 /* 114874 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41158 /* 114877 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41159 /* 114881 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41160 /* 114886 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41161 /* 114889 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41162 /* 114894 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41163 /* 114897 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41164 /* 114901 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41165 /* 114906 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41166 /* 114909 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
41167 /* 114913 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41168 /* 114916 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41169 /* 114921 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41170 /* 114926 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41171 /* 114931 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41172 /* 114934 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VADDfd),
41173 /* 114938 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41174 /* 114943 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41175 /* 114946 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41176 /* 114949 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41177 /* 114952 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41178 /* 114958 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41179 /* 114960 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41180 /* 114963 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41181 /* 114967 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41182 /* 114972 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41183 /* 114975 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41184 /* 114980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41185 /* 114983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41186 /* 114985 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41187 /* 114992 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41188 /* 114997 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41189 /* 115002 */ // GIR_Coverage, 3072,
41190 /* 115002 */ GIR_EraseRootFromParent_Done,
41191 /* 115003 */ // Label 2187: @115003
41192 /* 115003 */ GIM_Reject,
41193 /* 115004 */ // Label 2181: @115004
41194 /* 115004 */ GIM_Reject,
41195 /* 115005 */ // Label 2174: @115005
41196 /* 115005 */ GIM_Try, /*On fail goto*//*Label 2188*/ GIMT_Encode4(115051), // Rule ID 617 //
41197 /* 115010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
41198 /* 115013 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
41199 /* 115016 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41200 /* 115019 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41201 /* 115023 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41202 /* 115027 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41203 /* 115031 */ // (fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41204 /* 115031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD),
41205 /* 115034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
41206 /* 115036 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
41207 /* 115038 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
41208 /* 115040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41209 /* 115043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41210 /* 115049 */ GIR_RootConstrainSelectedInstOperands,
41211 /* 115050 */ // GIR_Coverage, 617,
41212 /* 115050 */ GIR_EraseRootFromParent_Done,
41213 /* 115051 */ // Label 2188: @115051
41214 /* 115051 */ GIM_Reject,
41215 /* 115052 */ // Label 2175: @115052
41216 /* 115052 */ GIM_Try, /*On fail goto*//*Label 2189*/ GIMT_Encode4(115236),
41217 /* 115057 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
41218 /* 115060 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
41219 /* 115063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41220 /* 115067 */ GIM_Try, /*On fail goto*//*Label 2190*/ GIMT_Encode4(115133), // Rule ID 6165 //
41221 /* 115072 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
41222 /* 115075 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41223 /* 115079 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41224 /* 115083 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
41225 /* 115087 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
41226 /* 115091 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41227 /* 115096 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41228 /* 115101 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41229 /* 115105 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41230 /* 115107 */ // (fadd:{ *:[v4f16] } (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm), DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41231 /* 115107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd),
41232 /* 115110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41233 /* 115112 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
41234 /* 115114 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41235 /* 115118 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41236 /* 115122 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41237 /* 115125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41238 /* 115131 */ GIR_RootConstrainSelectedInstOperands,
41239 /* 115132 */ // GIR_Coverage, 6165,
41240 /* 115132 */ GIR_EraseRootFromParent_Done,
41241 /* 115133 */ // Label 2190: @115133
41242 /* 115133 */ GIM_Try, /*On fail goto*//*Label 2191*/ GIMT_Encode4(115199), // Rule ID 1101 //
41243 /* 115138 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
41244 /* 115141 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41245 /* 115145 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41246 /* 115149 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41247 /* 115153 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
41248 /* 115157 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
41249 /* 115161 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41250 /* 115166 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41251 /* 115171 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41252 /* 115173 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41253 /* 115173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd),
41254 /* 115176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41255 /* 115178 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
41256 /* 115180 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41257 /* 115184 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41258 /* 115188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41259 /* 115191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41260 /* 115197 */ GIR_RootConstrainSelectedInstOperands,
41261 /* 115198 */ // GIR_Coverage, 1101,
41262 /* 115198 */ GIR_EraseRootFromParent_Done,
41263 /* 115199 */ // Label 2191: @115199
41264 /* 115199 */ GIM_Try, /*On fail goto*//*Label 2192*/ GIMT_Encode4(115235), // Rule ID 886 //
41265 /* 115204 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
41266 /* 115207 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41267 /* 115211 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41268 /* 115215 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VADDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41269 /* 115215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhd),
41270 /* 115218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41271 /* 115220 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
41272 /* 115222 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
41273 /* 115224 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41274 /* 115227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41275 /* 115233 */ GIR_RootConstrainSelectedInstOperands,
41276 /* 115234 */ // GIR_Coverage, 886,
41277 /* 115234 */ GIR_EraseRootFromParent_Done,
41278 /* 115235 */ // Label 2192: @115235
41279 /* 115235 */ GIM_Reject,
41280 /* 115236 */ // Label 2189: @115236
41281 /* 115236 */ GIM_Reject,
41282 /* 115237 */ // Label 2176: @115237
41283 /* 115237 */ GIM_Try, /*On fail goto*//*Label 2193*/ GIMT_Encode4(115490),
41284 /* 115242 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
41285 /* 115245 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
41286 /* 115248 */ GIM_Try, /*On fail goto*//*Label 2194*/ GIMT_Encode4(115318), // Rule ID 6166 //
41287 /* 115253 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
41288 /* 115256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41289 /* 115260 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41290 /* 115264 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41291 /* 115268 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
41292 /* 115272 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
41293 /* 115276 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41294 /* 115281 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41295 /* 115286 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41296 /* 115290 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41297 /* 115292 */ // (fadd:{ *:[v8f16] } (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm), QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41298 /* 115292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq),
41299 /* 115295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41300 /* 115297 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
41301 /* 115299 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41302 /* 115303 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41303 /* 115307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41304 /* 115310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41305 /* 115316 */ GIR_RootConstrainSelectedInstOperands,
41306 /* 115317 */ // GIR_Coverage, 6166,
41307 /* 115317 */ GIR_EraseRootFromParent_Done,
41308 /* 115318 */ // Label 2194: @115318
41309 /* 115318 */ GIM_Try, /*On fail goto*//*Label 2195*/ GIMT_Encode4(115388), // Rule ID 1102 //
41310 /* 115323 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
41311 /* 115326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41312 /* 115330 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41313 /* 115334 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41314 /* 115338 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41315 /* 115342 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
41316 /* 115346 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
41317 /* 115350 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41318 /* 115355 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41319 /* 115360 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41320 /* 115362 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41321 /* 115362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq),
41322 /* 115365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41323 /* 115367 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
41324 /* 115369 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41325 /* 115373 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41326 /* 115377 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41327 /* 115380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41328 /* 115386 */ GIR_RootConstrainSelectedInstOperands,
41329 /* 115387 */ // GIR_Coverage, 1102,
41330 /* 115387 */ GIR_EraseRootFromParent_Done,
41331 /* 115388 */ // Label 2195: @115388
41332 /* 115388 */ GIM_Try, /*On fail goto*//*Label 2196*/ GIMT_Encode4(115428), // Rule ID 887 //
41333 /* 115393 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
41334 /* 115396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41335 /* 115400 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41336 /* 115404 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41337 /* 115408 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VADDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41338 /* 115408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhq),
41339 /* 115411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41340 /* 115413 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
41341 /* 115415 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
41342 /* 115417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41343 /* 115420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41344 /* 115426 */ GIR_RootConstrainSelectedInstOperands,
41345 /* 115427 */ // GIR_Coverage, 887,
41346 /* 115427 */ GIR_EraseRootFromParent_Done,
41347 /* 115428 */ // Label 2196: @115428
41348 /* 115428 */ GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(115489), // Rule ID 4442 //
41349 /* 115433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
41350 /* 115436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41351 /* 115440 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41352 /* 115444 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41353 /* 115448 */ // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
41354 /* 115448 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41355 /* 115451 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41356 /* 115455 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41357 /* 115460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16),
41358 /* 115463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
41359 /* 115465 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
41360 /* 115467 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
41361 /* 115469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41362 /* 115472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41363 /* 115478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41364 /* 115484 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41365 /* 115487 */ GIR_RootConstrainSelectedInstOperands,
41366 /* 115488 */ // GIR_Coverage, 4442,
41367 /* 115488 */ GIR_EraseRootFromParent_Done,
41368 /* 115489 */ // Label 2197: @115489
41369 /* 115489 */ GIM_Reject,
41370 /* 115490 */ // Label 2193: @115490
41371 /* 115490 */ GIM_Reject,
41372 /* 115491 */ // Label 2177: @115491
41373 /* 115491 */ GIM_Try, /*On fail goto*//*Label 2198*/ GIMT_Encode4(115537), // Rule ID 884 //
41374 /* 115496 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
41375 /* 115499 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
41376 /* 115502 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
41377 /* 115505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41378 /* 115509 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41379 /* 115513 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41380 /* 115517 */ // (fadd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VADDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
41381 /* 115517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfd),
41382 /* 115520 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41383 /* 115522 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
41384 /* 115524 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
41385 /* 115526 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41386 /* 115529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41387 /* 115535 */ GIR_RootConstrainSelectedInstOperands,
41388 /* 115536 */ // GIR_Coverage, 884,
41389 /* 115536 */ GIR_EraseRootFromParent_Done,
41390 /* 115537 */ // Label 2198: @115537
41391 /* 115537 */ GIM_Reject,
41392 /* 115538 */ // Label 2178: @115538
41393 /* 115538 */ GIM_Try, /*On fail goto*//*Label 2199*/ GIMT_Encode4(115651),
41394 /* 115543 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
41395 /* 115546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
41396 /* 115549 */ GIM_Try, /*On fail goto*//*Label 2200*/ GIMT_Encode4(115589), // Rule ID 885 //
41397 /* 115554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
41398 /* 115557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41399 /* 115561 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41400 /* 115565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41401 /* 115569 */ // (fadd:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VADDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
41402 /* 115569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfq),
41403 /* 115572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41404 /* 115574 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
41405 /* 115576 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
41406 /* 115578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41407 /* 115581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41408 /* 115587 */ GIR_RootConstrainSelectedInstOperands,
41409 /* 115588 */ // GIR_Coverage, 885,
41410 /* 115588 */ GIR_EraseRootFromParent_Done,
41411 /* 115589 */ // Label 2200: @115589
41412 /* 115589 */ GIM_Try, /*On fail goto*//*Label 2201*/ GIMT_Encode4(115650), // Rule ID 4435 //
41413 /* 115594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
41414 /* 115597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41415 /* 115601 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41416 /* 115605 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41417 /* 115609 */ // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
41418 /* 115609 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41419 /* 115612 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41420 /* 115616 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41421 /* 115621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32),
41422 /* 115624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
41423 /* 115626 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
41424 /* 115628 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
41425 /* 115630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41426 /* 115633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41427 /* 115639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41428 /* 115645 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41429 /* 115648 */ GIR_RootConstrainSelectedInstOperands,
41430 /* 115649 */ // GIR_Coverage, 4435,
41431 /* 115649 */ GIR_EraseRootFromParent_Done,
41432 /* 115650 */ // Label 2201: @115650
41433 /* 115650 */ GIM_Reject,
41434 /* 115651 */ // Label 2199: @115651
41435 /* 115651 */ GIM_Reject,
41436 /* 115652 */ // Label 2179: @115652
41437 /* 115652 */ GIM_Reject,
41438 /* 115653 */ // Label 41: @115653
41439 /* 115653 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2209*/ GIMT_Encode4(117329),
41440 /* 115664 */ /*GILLT_s16*//*Label 2202*/ GIMT_Encode4(115716),
41441 /* 115668 */ /*GILLT_s32*//*Label 2203*/ GIMT_Encode4(115763),
41442 /* 115672 */ /*GILLT_s64*//*Label 2204*/ GIMT_Encode4(116690), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
41443 /* 115700 */ /*GILLT_v4s16*//*Label 2205*/ GIMT_Encode4(116737),
41444 /* 115704 */ /*GILLT_v8s16*//*Label 2206*/ GIMT_Encode4(116914),
41445 /* 115708 */ /*GILLT_v2s32*//*Label 2207*/ GIMT_Encode4(117168),
41446 /* 115712 */ /*GILLT_v4s32*//*Label 2208*/ GIMT_Encode4(117215),
41447 /* 115716 */ // Label 2202: @115716
41448 /* 115716 */ GIM_Try, /*On fail goto*//*Label 2210*/ GIMT_Encode4(115762), // Rule ID 627 //
41449 /* 115721 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41450 /* 115724 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
41451 /* 115727 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41452 /* 115730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41453 /* 115734 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41454 /* 115738 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41455 /* 115742 */ // (fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41456 /* 115742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH),
41457 /* 115745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
41458 /* 115747 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
41459 /* 115749 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
41460 /* 115751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41461 /* 115754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41462 /* 115760 */ GIR_RootConstrainSelectedInstOperands,
41463 /* 115761 */ // GIR_Coverage, 627,
41464 /* 115761 */ GIR_EraseRootFromParent_Done,
41465 /* 115762 */ // Label 2210: @115762
41466 /* 115762 */ GIM_Reject,
41467 /* 115763 */ // Label 2203: @115763
41468 /* 115763 */ GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(116689),
41469 /* 115768 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
41470 /* 115771 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41471 /* 115774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41472 /* 115778 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41473 /* 115782 */ GIM_Try, /*On fail goto*//*Label 2212*/ GIMT_Encode4(116106), // Rule ID 3076 //
41474 /* 115787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP),
41475 /* 115790 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41476 /* 115794 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41477 /* 115798 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41478 /* 115802 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41479 /* 115806 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41480 /* 115811 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41481 /* 115816 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41482 /* 115818 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41483 /* 115818 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
41484 /* 115821 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41485 /* 115825 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41486 /* 115830 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
41487 /* 115832 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
41488 /* 115835 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41489 /* 115839 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41490 /* 115844 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
41491 /* 115847 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41492 /* 115852 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
41493 /* 115855 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41494 /* 115859 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41495 /* 115864 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
41496 /* 115867 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
41497 /* 115871 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
41498 /* 115874 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41499 /* 115879 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41500 /* 115884 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41501 /* 115889 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41502 /* 115892 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41503 /* 115896 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41504 /* 115901 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41505 /* 115903 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41506 /* 115906 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41507 /* 115910 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41508 /* 115915 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41509 /* 115918 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41510 /* 115923 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41511 /* 115926 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41512 /* 115930 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41513 /* 115935 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41514 /* 115938 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
41515 /* 115942 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41516 /* 115945 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41517 /* 115950 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41518 /* 115955 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41519 /* 115960 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41520 /* 115963 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41521 /* 115967 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41522 /* 115972 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41523 /* 115974 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41524 /* 115977 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41525 /* 115981 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41526 /* 115986 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41527 /* 115989 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41528 /* 115994 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41529 /* 115997 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41530 /* 116001 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41531 /* 116006 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41532 /* 116009 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
41533 /* 116013 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41534 /* 116016 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41535 /* 116021 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41536 /* 116026 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41537 /* 116031 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41538 /* 116034 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLSfd),
41539 /* 116038 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41540 /* 116043 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41541 /* 116046 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41542 /* 116049 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
41543 /* 116052 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41544 /* 116055 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41545 /* 116061 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41546 /* 116063 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41547 /* 116066 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41548 /* 116070 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41549 /* 116075 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41550 /* 116078 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41551 /* 116083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41552 /* 116086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41553 /* 116088 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41554 /* 116095 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41555 /* 116100 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41556 /* 116105 */ // GIR_Coverage, 3076,
41557 /* 116105 */ GIR_EraseRootFromParent_Done,
41558 /* 116106 */ // Label 2212: @116106
41559 /* 116106 */ GIM_Try, /*On fail goto*//*Label 2213*/ GIMT_Encode4(116430), // Rule ID 3078 //
41560 /* 116111 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP),
41561 /* 116114 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41562 /* 116118 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41563 /* 116122 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41564 /* 116126 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41565 /* 116130 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41566 /* 116135 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41567 /* 116140 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41568 /* 116142 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41569 /* 116142 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
41570 /* 116145 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41571 /* 116149 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41572 /* 116154 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
41573 /* 116156 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
41574 /* 116159 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41575 /* 116163 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41576 /* 116168 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
41577 /* 116171 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41578 /* 116176 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
41579 /* 116179 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41580 /* 116183 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41581 /* 116188 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
41582 /* 116191 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
41583 /* 116195 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
41584 /* 116198 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41585 /* 116203 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41586 /* 116208 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41587 /* 116213 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41588 /* 116216 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41589 /* 116220 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41590 /* 116225 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41591 /* 116227 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41592 /* 116230 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41593 /* 116234 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41594 /* 116239 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41595 /* 116242 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41596 /* 116247 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41597 /* 116250 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41598 /* 116254 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41599 /* 116259 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41600 /* 116262 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
41601 /* 116266 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41602 /* 116269 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41603 /* 116274 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41604 /* 116279 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41605 /* 116284 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41606 /* 116287 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41607 /* 116291 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41608 /* 116296 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41609 /* 116298 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41610 /* 116301 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41611 /* 116305 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41612 /* 116310 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41613 /* 116313 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41614 /* 116318 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41615 /* 116321 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41616 /* 116325 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41617 /* 116330 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41618 /* 116333 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
41619 /* 116337 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41620 /* 116340 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41621 /* 116345 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41622 /* 116350 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41623 /* 116355 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41624 /* 116358 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMSfd),
41625 /* 116362 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41626 /* 116367 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41627 /* 116370 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41628 /* 116373 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
41629 /* 116376 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41630 /* 116379 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41631 /* 116385 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41632 /* 116387 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41633 /* 116390 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41634 /* 116394 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41635 /* 116399 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41636 /* 116402 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41637 /* 116407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41638 /* 116410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41639 /* 116412 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41640 /* 116419 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41641 /* 116424 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41642 /* 116429 */ // GIR_Coverage, 3078,
41643 /* 116429 */ GIR_EraseRootFromParent_Done,
41644 /* 116430 */ // Label 2213: @116430
41645 /* 116430 */ GIM_Try, /*On fail goto*//*Label 2214*/ GIMT_Encode4(116462), // Rule ID 625 //
41646 /* 116435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
41647 /* 116438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41648 /* 116442 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41649 /* 116442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS),
41650 /* 116445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
41651 /* 116447 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
41652 /* 116449 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
41653 /* 116451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41654 /* 116454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41655 /* 116460 */ GIR_RootConstrainSelectedInstOperands,
41656 /* 116461 */ // GIR_Coverage, 625,
41657 /* 116461 */ GIR_EraseRootFromParent_Done,
41658 /* 116462 */ // Label 2214: @116462
41659 /* 116462 */ GIM_Try, /*On fail goto*//*Label 2215*/ GIMT_Encode4(116688), // Rule ID 3073 //
41660 /* 116467 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
41661 /* 116470 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41662 /* 116474 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VSUBfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41663 /* 116474 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41664 /* 116477 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41665 /* 116481 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41666 /* 116486 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41667 /* 116488 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41668 /* 116491 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41669 /* 116495 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41670 /* 116500 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41671 /* 116503 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41672 /* 116508 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41673 /* 116511 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41674 /* 116515 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41675 /* 116520 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41676 /* 116523 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
41677 /* 116527 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41678 /* 116530 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41679 /* 116535 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41680 /* 116540 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41681 /* 116545 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41682 /* 116548 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41683 /* 116552 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41684 /* 116557 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41685 /* 116559 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41686 /* 116562 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41687 /* 116566 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41688 /* 116571 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41689 /* 116574 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41690 /* 116579 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41691 /* 116582 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41692 /* 116586 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41693 /* 116591 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41694 /* 116594 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
41695 /* 116598 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41696 /* 116601 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41697 /* 116606 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41698 /* 116611 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41699 /* 116616 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41700 /* 116619 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VSUBfd),
41701 /* 116623 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41702 /* 116628 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41703 /* 116631 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41704 /* 116634 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41705 /* 116637 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41706 /* 116643 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41707 /* 116645 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41708 /* 116648 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41709 /* 116652 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41710 /* 116657 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41711 /* 116660 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41712 /* 116665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41713 /* 116668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41714 /* 116670 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41715 /* 116677 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41716 /* 116682 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41717 /* 116687 */ // GIR_Coverage, 3073,
41718 /* 116687 */ GIR_EraseRootFromParent_Done,
41719 /* 116688 */ // Label 2215: @116688
41720 /* 116688 */ GIM_Reject,
41721 /* 116689 */ // Label 2211: @116689
41722 /* 116689 */ GIM_Reject,
41723 /* 116690 */ // Label 2204: @116690
41724 /* 116690 */ GIM_Try, /*On fail goto*//*Label 2216*/ GIMT_Encode4(116736), // Rule ID 623 //
41725 /* 116695 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
41726 /* 116698 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
41727 /* 116701 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41728 /* 116704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41729 /* 116708 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41730 /* 116712 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41731 /* 116716 */ // (fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41732 /* 116716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD),
41733 /* 116719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
41734 /* 116721 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
41735 /* 116723 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
41736 /* 116725 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41737 /* 116728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41738 /* 116734 */ GIR_RootConstrainSelectedInstOperands,
41739 /* 116735 */ // GIR_Coverage, 623,
41740 /* 116735 */ GIR_EraseRootFromParent_Done,
41741 /* 116736 */ // Label 2216: @116736
41742 /* 116736 */ GIM_Reject,
41743 /* 116737 */ // Label 2205: @116737
41744 /* 116737 */ GIM_Try, /*On fail goto*//*Label 2217*/ GIMT_Encode4(116913),
41745 /* 116742 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
41746 /* 116745 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
41747 /* 116748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41748 /* 116752 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41749 /* 116756 */ GIM_Try, /*On fail goto*//*Label 2218*/ GIMT_Encode4(116818), // Rule ID 1067 //
41750 /* 116761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx),
41751 /* 116764 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41752 /* 116768 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41753 /* 116772 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
41754 /* 116776 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
41755 /* 116780 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41756 /* 116785 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41757 /* 116790 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41758 /* 116792 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VMLShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41759 /* 116792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShd),
41760 /* 116795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41761 /* 116797 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
41762 /* 116799 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41763 /* 116803 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41764 /* 116807 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41765 /* 116810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41766 /* 116816 */ GIR_RootConstrainSelectedInstOperands,
41767 /* 116817 */ // GIR_Coverage, 1067,
41768 /* 116817 */ GIR_EraseRootFromParent_Done,
41769 /* 116818 */ // Label 2218: @116818
41770 /* 116818 */ GIM_Try, /*On fail goto*//*Label 2219*/ GIMT_Encode4(116880), // Rule ID 1111 //
41771 /* 116823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
41772 /* 116826 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41773 /* 116830 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41774 /* 116834 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
41775 /* 116838 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
41776 /* 116842 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41777 /* 116847 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41778 /* 116852 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41779 /* 116854 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41780 /* 116854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShd),
41781 /* 116857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41782 /* 116859 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
41783 /* 116861 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41784 /* 116865 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41785 /* 116869 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41786 /* 116872 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41787 /* 116878 */ GIR_RootConstrainSelectedInstOperands,
41788 /* 116879 */ // GIR_Coverage, 1111,
41789 /* 116879 */ GIR_EraseRootFromParent_Done,
41790 /* 116880 */ // Label 2219: @116880
41791 /* 116880 */ GIM_Try, /*On fail goto*//*Label 2220*/ GIMT_Encode4(116912), // Rule ID 1132 //
41792 /* 116885 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
41793 /* 116888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41794 /* 116892 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VSUBhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41795 /* 116892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhd),
41796 /* 116895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41797 /* 116897 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
41798 /* 116899 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
41799 /* 116901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41800 /* 116904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41801 /* 116910 */ GIR_RootConstrainSelectedInstOperands,
41802 /* 116911 */ // GIR_Coverage, 1132,
41803 /* 116911 */ GIR_EraseRootFromParent_Done,
41804 /* 116912 */ // Label 2220: @116912
41805 /* 116912 */ GIM_Reject,
41806 /* 116913 */ // Label 2217: @116913
41807 /* 116913 */ GIM_Reject,
41808 /* 116914 */ // Label 2206: @116914
41809 /* 116914 */ GIM_Try, /*On fail goto*//*Label 2221*/ GIMT_Encode4(117167),
41810 /* 116919 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
41811 /* 116922 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
41812 /* 116925 */ GIM_Try, /*On fail goto*//*Label 2222*/ GIMT_Encode4(116995), // Rule ID 1068 //
41813 /* 116930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx),
41814 /* 116933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41815 /* 116937 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41816 /* 116941 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41817 /* 116945 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41818 /* 116949 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
41819 /* 116953 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
41820 /* 116957 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41821 /* 116962 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41822 /* 116967 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41823 /* 116969 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VMLShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41824 /* 116969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShq),
41825 /* 116972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41826 /* 116974 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
41827 /* 116976 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41828 /* 116980 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41829 /* 116984 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41830 /* 116987 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41831 /* 116993 */ GIR_RootConstrainSelectedInstOperands,
41832 /* 116994 */ // GIR_Coverage, 1068,
41833 /* 116994 */ GIR_EraseRootFromParent_Done,
41834 /* 116995 */ // Label 2222: @116995
41835 /* 116995 */ GIM_Try, /*On fail goto*//*Label 2223*/ GIMT_Encode4(117065), // Rule ID 1112 //
41836 /* 117000 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
41837 /* 117003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41838 /* 117007 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41839 /* 117011 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41840 /* 117015 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41841 /* 117019 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
41842 /* 117023 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
41843 /* 117027 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41844 /* 117032 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41845 /* 117037 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41846 /* 117039 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41847 /* 117039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShq),
41848 /* 117042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41849 /* 117044 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
41850 /* 117046 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41851 /* 117050 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41852 /* 117054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41853 /* 117057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41854 /* 117063 */ GIR_RootConstrainSelectedInstOperands,
41855 /* 117064 */ // GIR_Coverage, 1112,
41856 /* 117064 */ GIR_EraseRootFromParent_Done,
41857 /* 117065 */ // Label 2223: @117065
41858 /* 117065 */ GIM_Try, /*On fail goto*//*Label 2224*/ GIMT_Encode4(117105), // Rule ID 1133 //
41859 /* 117070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
41860 /* 117073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41861 /* 117077 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41862 /* 117081 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41863 /* 117085 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VSUBhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41864 /* 117085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhq),
41865 /* 117088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41866 /* 117090 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
41867 /* 117092 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
41868 /* 117094 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41869 /* 117097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41870 /* 117103 */ GIR_RootConstrainSelectedInstOperands,
41871 /* 117104 */ // GIR_Coverage, 1133,
41872 /* 117104 */ GIR_EraseRootFromParent_Done,
41873 /* 117105 */ // Label 2224: @117105
41874 /* 117105 */ GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(117166), // Rule ID 4456 //
41875 /* 117110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
41876 /* 117113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41877 /* 117117 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41878 /* 117121 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41879 /* 117125 */ // (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
41880 /* 117125 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41881 /* 117128 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41882 /* 117132 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41883 /* 117137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16),
41884 /* 117140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
41885 /* 117142 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
41886 /* 117144 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
41887 /* 117146 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41888 /* 117149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41889 /* 117155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41890 /* 117161 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41891 /* 117164 */ GIR_RootConstrainSelectedInstOperands,
41892 /* 117165 */ // GIR_Coverage, 4456,
41893 /* 117165 */ GIR_EraseRootFromParent_Done,
41894 /* 117166 */ // Label 2225: @117166
41895 /* 117166 */ GIM_Reject,
41896 /* 117167 */ // Label 2221: @117167
41897 /* 117167 */ GIM_Reject,
41898 /* 117168 */ // Label 2207: @117168
41899 /* 117168 */ GIM_Try, /*On fail goto*//*Label 2226*/ GIMT_Encode4(117214), // Rule ID 1130 //
41900 /* 117173 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
41901 /* 117176 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
41902 /* 117179 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
41903 /* 117182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41904 /* 117186 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41905 /* 117190 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41906 /* 117194 */ // (fsub:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VSUBfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
41907 /* 117194 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfd),
41908 /* 117197 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41909 /* 117199 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
41910 /* 117201 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
41911 /* 117203 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41912 /* 117206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41913 /* 117212 */ GIR_RootConstrainSelectedInstOperands,
41914 /* 117213 */ // GIR_Coverage, 1130,
41915 /* 117213 */ GIR_EraseRootFromParent_Done,
41916 /* 117214 */ // Label 2226: @117214
41917 /* 117214 */ GIM_Reject,
41918 /* 117215 */ // Label 2208: @117215
41919 /* 117215 */ GIM_Try, /*On fail goto*//*Label 2227*/ GIMT_Encode4(117328),
41920 /* 117220 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
41921 /* 117223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
41922 /* 117226 */ GIM_Try, /*On fail goto*//*Label 2228*/ GIMT_Encode4(117266), // Rule ID 1131 //
41923 /* 117231 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
41924 /* 117234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41925 /* 117238 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41926 /* 117242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41927 /* 117246 */ // (fsub:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VSUBfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
41928 /* 117246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfq),
41929 /* 117249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41930 /* 117251 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
41931 /* 117253 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
41932 /* 117255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41933 /* 117258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41934 /* 117264 */ GIR_RootConstrainSelectedInstOperands,
41935 /* 117265 */ // GIR_Coverage, 1131,
41936 /* 117265 */ GIR_EraseRootFromParent_Done,
41937 /* 117266 */ // Label 2228: @117266
41938 /* 117266 */ GIM_Try, /*On fail goto*//*Label 2229*/ GIMT_Encode4(117327), // Rule ID 4449 //
41939 /* 117271 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
41940 /* 117274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41941 /* 117278 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41942 /* 117282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41943 /* 117286 */ // (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
41944 /* 117286 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41945 /* 117289 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41946 /* 117293 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41947 /* 117298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32),
41948 /* 117301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
41949 /* 117303 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
41950 /* 117305 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
41951 /* 117307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41952 /* 117310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41953 /* 117316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41954 /* 117322 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41955 /* 117325 */ GIR_RootConstrainSelectedInstOperands,
41956 /* 117326 */ // GIR_Coverage, 4449,
41957 /* 117326 */ GIR_EraseRootFromParent_Done,
41958 /* 117327 */ // Label 2229: @117327
41959 /* 117327 */ GIM_Reject,
41960 /* 117328 */ // Label 2227: @117328
41961 /* 117328 */ GIM_Reject,
41962 /* 117329 */ // Label 2209: @117329
41963 /* 117329 */ GIM_Reject,
41964 /* 117330 */ // Label 42: @117330
41965 /* 117330 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2237*/ GIMT_Encode4(118310),
41966 /* 117341 */ /*GILLT_s16*//*Label 2230*/ GIMT_Encode4(117393),
41967 /* 117345 */ /*GILLT_s32*//*Label 2231*/ GIMT_Encode4(117440),
41968 /* 117349 */ /*GILLT_s64*//*Label 2232*/ GIMT_Encode4(117829), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
41969 /* 117377 */ /*GILLT_v4s16*//*Label 2233*/ GIMT_Encode4(117988),
41970 /* 117381 */ /*GILLT_v8s16*//*Label 2234*/ GIMT_Encode4(118035),
41971 /* 117385 */ /*GILLT_v2s32*//*Label 2235*/ GIMT_Encode4(118149),
41972 /* 117389 */ /*GILLT_v4s32*//*Label 2236*/ GIMT_Encode4(118196),
41973 /* 117393 */ // Label 2230: @117393
41974 /* 117393 */ GIM_Try, /*On fail goto*//*Label 2238*/ GIMT_Encode4(117439), // Rule ID 639 //
41975 /* 117398 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41976 /* 117401 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
41977 /* 117404 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41978 /* 117407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41979 /* 117411 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41980 /* 117415 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41981 /* 117419 */ // (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41982 /* 117419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH),
41983 /* 117422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
41984 /* 117424 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
41985 /* 117426 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
41986 /* 117428 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41987 /* 117431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41988 /* 117437 */ GIR_RootConstrainSelectedInstOperands,
41989 /* 117438 */ // GIR_Coverage, 639,
41990 /* 117438 */ GIR_EraseRootFromParent_Done,
41991 /* 117439 */ // Label 2238: @117439
41992 /* 117439 */ GIM_Reject,
41993 /* 117440 */ // Label 2231: @117440
41994 /* 117440 */ GIM_Try, /*On fail goto*//*Label 2239*/ GIMT_Encode4(117828),
41995 /* 117445 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
41996 /* 117448 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41997 /* 117451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41998 /* 117455 */ GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(117508), // Rule ID 2488 //
41999 /* 117460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NoHonorSignDependentRounding),
42000 /* 117463 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42001 /* 117467 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42002 /* 117471 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42003 /* 117475 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42004 /* 117480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42005 /* 117484 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42006 /* 117486 */ // (fmul:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
42007 /* 117486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
42008 /* 117489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42009 /* 117491 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
42010 /* 117495 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
42011 /* 117497 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42012 /* 117500 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42013 /* 117506 */ GIR_RootConstrainSelectedInstOperands,
42014 /* 117507 */ // GIR_Coverage, 2488,
42015 /* 117507 */ GIR_EraseRootFromParent_Done,
42016 /* 117508 */ // Label 2240: @117508
42017 /* 117508 */ GIM_Try, /*On fail goto*//*Label 2241*/ GIMT_Encode4(117561), // Rule ID 6292 //
42018 /* 117513 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NoHonorSignDependentRounding),
42019 /* 117516 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42020 /* 117520 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42021 /* 117524 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42022 /* 117528 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42023 /* 117532 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42024 /* 117537 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42025 /* 117539 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
42026 /* 117539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
42027 /* 117542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42028 /* 117544 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
42029 /* 117548 */ GIR_RootToRootCopy, /*OpIdx*/1, // b
42030 /* 117550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42031 /* 117553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42032 /* 117559 */ GIR_RootConstrainSelectedInstOperands,
42033 /* 117560 */ // GIR_Coverage, 6292,
42034 /* 117560 */ GIR_EraseRootFromParent_Done,
42035 /* 117561 */ // Label 2241: @117561
42036 /* 117561 */ GIM_Try, /*On fail goto*//*Label 2242*/ GIMT_Encode4(117597), // Rule ID 637 //
42037 /* 117566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
42038 /* 117569 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42039 /* 117573 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42040 /* 117577 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42041 /* 117577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS),
42042 /* 117580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42043 /* 117582 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
42044 /* 117584 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42045 /* 117586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42046 /* 117589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42047 /* 117595 */ GIR_RootConstrainSelectedInstOperands,
42048 /* 117596 */ // GIR_Coverage, 637,
42049 /* 117596 */ GIR_EraseRootFromParent_Done,
42050 /* 117597 */ // Label 2242: @117597
42051 /* 117597 */ GIM_Try, /*On fail goto*//*Label 2243*/ GIMT_Encode4(117827), // Rule ID 3074 //
42052 /* 117602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
42053 /* 117605 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42054 /* 117609 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42055 /* 117613 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMULfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
42056 /* 117613 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
42057 /* 117616 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42058 /* 117620 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42059 /* 117625 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
42060 /* 117627 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
42061 /* 117630 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42062 /* 117634 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42063 /* 117639 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
42064 /* 117642 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42065 /* 117647 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
42066 /* 117650 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
42067 /* 117654 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42068 /* 117659 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
42069 /* 117662 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
42070 /* 117666 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
42071 /* 117669 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42072 /* 117674 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42073 /* 117679 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
42074 /* 117684 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
42075 /* 117687 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42076 /* 117691 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42077 /* 117696 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
42078 /* 117698 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
42079 /* 117701 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42080 /* 117705 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42081 /* 117710 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
42082 /* 117713 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42083 /* 117718 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
42084 /* 117721 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
42085 /* 117725 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42086 /* 117730 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
42087 /* 117733 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
42088 /* 117737 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
42089 /* 117740 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42090 /* 117745 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42091 /* 117750 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
42092 /* 117755 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
42093 /* 117758 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMULfd),
42094 /* 117762 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42095 /* 117767 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
42096 /* 117770 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
42097 /* 117773 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
42098 /* 117776 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42099 /* 117782 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42100 /* 117784 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
42101 /* 117787 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42102 /* 117791 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42103 /* 117796 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
42104 /* 117799 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42105 /* 117804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42106 /* 117807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42107 /* 117809 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
42108 /* 117816 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42109 /* 117821 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42110 /* 117826 */ // GIR_Coverage, 3074,
42111 /* 117826 */ GIR_EraseRootFromParent_Done,
42112 /* 117827 */ // Label 2243: @117827
42113 /* 117827 */ GIM_Reject,
42114 /* 117828 */ // Label 2239: @117828
42115 /* 117828 */ GIM_Reject,
42116 /* 117829 */ // Label 2232: @117829
42117 /* 117829 */ GIM_Try, /*On fail goto*//*Label 2244*/ GIMT_Encode4(117987),
42118 /* 117834 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
42119 /* 117837 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
42120 /* 117840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42121 /* 117844 */ GIM_Try, /*On fail goto*//*Label 2245*/ GIMT_Encode4(117897), // Rule ID 2487 //
42122 /* 117849 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding),
42123 /* 117852 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42124 /* 117856 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42125 /* 117860 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42126 /* 117864 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42127 /* 117869 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42128 /* 117873 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42129 /* 117875 */ // (fmul:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a), DPR:{ *:[f64] }:$b) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
42130 /* 117875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
42131 /* 117878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42132 /* 117880 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
42133 /* 117884 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
42134 /* 117886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42135 /* 117889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42136 /* 117895 */ GIR_RootConstrainSelectedInstOperands,
42137 /* 117896 */ // GIR_Coverage, 2487,
42138 /* 117896 */ GIR_EraseRootFromParent_Done,
42139 /* 117897 */ // Label 2245: @117897
42140 /* 117897 */ GIM_Try, /*On fail goto*//*Label 2246*/ GIMT_Encode4(117950), // Rule ID 6291 //
42141 /* 117902 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding),
42142 /* 117905 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42143 /* 117909 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42144 /* 117913 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42145 /* 117917 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42146 /* 117921 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42147 /* 117926 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42148 /* 117928 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$b, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
42149 /* 117928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
42150 /* 117931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42151 /* 117933 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
42152 /* 117937 */ GIR_RootToRootCopy, /*OpIdx*/1, // b
42153 /* 117939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42154 /* 117942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42155 /* 117948 */ GIR_RootConstrainSelectedInstOperands,
42156 /* 117949 */ // GIR_Coverage, 6291,
42157 /* 117949 */ GIR_EraseRootFromParent_Done,
42158 /* 117950 */ // Label 2246: @117950
42159 /* 117950 */ GIM_Try, /*On fail goto*//*Label 2247*/ GIMT_Encode4(117986), // Rule ID 635 //
42160 /* 117955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
42161 /* 117958 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42162 /* 117962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42163 /* 117966 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42164 /* 117966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD),
42165 /* 117969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42166 /* 117971 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
42167 /* 117973 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
42168 /* 117975 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42169 /* 117978 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42170 /* 117984 */ GIR_RootConstrainSelectedInstOperands,
42171 /* 117985 */ // GIR_Coverage, 635,
42172 /* 117985 */ GIR_EraseRootFromParent_Done,
42173 /* 117986 */ // Label 2247: @117986
42174 /* 117986 */ GIM_Reject,
42175 /* 117987 */ // Label 2244: @117987
42176 /* 117987 */ GIM_Reject,
42177 /* 117988 */ // Label 2233: @117988
42178 /* 117988 */ GIM_Try, /*On fail goto*//*Label 2248*/ GIMT_Encode4(118034), // Rule ID 965 //
42179 /* 117993 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42180 /* 117996 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
42181 /* 117999 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
42182 /* 118002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42183 /* 118006 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42184 /* 118010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42185 /* 118014 */ // (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMULhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
42186 /* 118014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhd),
42187 /* 118017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42188 /* 118019 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
42189 /* 118021 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42190 /* 118023 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42191 /* 118026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42192 /* 118032 */ GIR_RootConstrainSelectedInstOperands,
42193 /* 118033 */ // GIR_Coverage, 965,
42194 /* 118033 */ GIR_EraseRootFromParent_Done,
42195 /* 118034 */ // Label 2248: @118034
42196 /* 118034 */ GIM_Reject,
42197 /* 118035 */ // Label 2234: @118035
42198 /* 118035 */ GIM_Try, /*On fail goto*//*Label 2249*/ GIMT_Encode4(118148),
42199 /* 118040 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42200 /* 118043 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
42201 /* 118046 */ GIM_Try, /*On fail goto*//*Label 2250*/ GIMT_Encode4(118086), // Rule ID 966 //
42202 /* 118051 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42203 /* 118054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42204 /* 118058 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42205 /* 118062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42206 /* 118066 */ // (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMULhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
42207 /* 118066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhq),
42208 /* 118069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42209 /* 118071 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
42210 /* 118073 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42211 /* 118075 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42212 /* 118078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42213 /* 118084 */ GIR_RootConstrainSelectedInstOperands,
42214 /* 118085 */ // GIR_Coverage, 966,
42215 /* 118085 */ GIR_EraseRootFromParent_Done,
42216 /* 118086 */ // Label 2250: @118086
42217 /* 118086 */ GIM_Try, /*On fail goto*//*Label 2251*/ GIMT_Encode4(118147), // Rule ID 4402 //
42218 /* 118091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
42219 /* 118094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42220 /* 118098 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42221 /* 118102 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42222 /* 118106 */ // (fmul:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
42223 /* 118106 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42224 /* 118109 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42225 /* 118113 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42226 /* 118118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16),
42227 /* 118121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42228 /* 118123 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
42229 /* 118125 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
42230 /* 118127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42231 /* 118130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42232 /* 118136 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42233 /* 118142 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42234 /* 118145 */ GIR_RootConstrainSelectedInstOperands,
42235 /* 118146 */ // GIR_Coverage, 4402,
42236 /* 118146 */ GIR_EraseRootFromParent_Done,
42237 /* 118147 */ // Label 2251: @118147
42238 /* 118147 */ GIM_Reject,
42239 /* 118148 */ // Label 2249: @118148
42240 /* 118148 */ GIM_Reject,
42241 /* 118149 */ // Label 2235: @118149
42242 /* 118149 */ GIM_Try, /*On fail goto*//*Label 2252*/ GIMT_Encode4(118195), // Rule ID 963 //
42243 /* 118154 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42244 /* 118157 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
42245 /* 118160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42246 /* 118163 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42247 /* 118167 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42248 /* 118171 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42249 /* 118175 */ // (fmul:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMULfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
42250 /* 118175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfd),
42251 /* 118178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42252 /* 118180 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
42253 /* 118182 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42254 /* 118184 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42255 /* 118187 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42256 /* 118193 */ GIR_RootConstrainSelectedInstOperands,
42257 /* 118194 */ // GIR_Coverage, 963,
42258 /* 118194 */ GIR_EraseRootFromParent_Done,
42259 /* 118195 */ // Label 2252: @118195
42260 /* 118195 */ GIM_Reject,
42261 /* 118196 */ // Label 2236: @118196
42262 /* 118196 */ GIM_Try, /*On fail goto*//*Label 2253*/ GIMT_Encode4(118309),
42263 /* 118201 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42264 /* 118204 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42265 /* 118207 */ GIM_Try, /*On fail goto*//*Label 2254*/ GIMT_Encode4(118247), // Rule ID 964 //
42266 /* 118212 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42267 /* 118215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42268 /* 118219 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42269 /* 118223 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42270 /* 118227 */ // (fmul:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMULfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
42271 /* 118227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfq),
42272 /* 118230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42273 /* 118232 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
42274 /* 118234 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42275 /* 118236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42276 /* 118239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42277 /* 118245 */ GIR_RootConstrainSelectedInstOperands,
42278 /* 118246 */ // GIR_Coverage, 964,
42279 /* 118246 */ GIR_EraseRootFromParent_Done,
42280 /* 118247 */ // Label 2254: @118247
42281 /* 118247 */ GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(118308), // Rule ID 4395 //
42282 /* 118252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
42283 /* 118255 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42284 /* 118259 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42285 /* 118263 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42286 /* 118267 */ // (fmul:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
42287 /* 118267 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42288 /* 118270 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42289 /* 118274 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42290 /* 118279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32),
42291 /* 118282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42292 /* 118284 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
42293 /* 118286 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
42294 /* 118288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42295 /* 118291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42296 /* 118297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42297 /* 118303 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42298 /* 118306 */ GIR_RootConstrainSelectedInstOperands,
42299 /* 118307 */ // GIR_Coverage, 4395,
42300 /* 118307 */ GIR_EraseRootFromParent_Done,
42301 /* 118308 */ // Label 2255: @118308
42302 /* 118308 */ GIM_Reject,
42303 /* 118309 */ // Label 2253: @118309
42304 /* 118309 */ GIM_Reject,
42305 /* 118310 */ // Label 2237: @118310
42306 /* 118310 */ GIM_Reject,
42307 /* 118311 */ // Label 43: @118311
42308 /* 118311 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2263*/ GIMT_Encode4(120401),
42309 /* 118322 */ /*GILLT_s16*//*Label 2256*/ GIMT_Encode4(118374),
42310 /* 118326 */ /*GILLT_s32*//*Label 2257*/ GIMT_Encode4(118761),
42311 /* 118330 */ /*GILLT_s64*//*Label 2258*/ GIMT_Encode4(119148), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
42312 /* 118358 */ /*GILLT_v4s16*//*Label 2259*/ GIMT_Encode4(119535),
42313 /* 118362 */ /*GILLT_v8s16*//*Label 2260*/ GIMT_Encode4(119591),
42314 /* 118366 */ /*GILLT_v2s32*//*Label 2261*/ GIMT_Encode4(119843),
42315 /* 118370 */ /*GILLT_v4s32*//*Label 2262*/ GIMT_Encode4(120023),
42316 /* 118374 */ // Label 2256: @118374
42317 /* 118374 */ GIM_Try, /*On fail goto*//*Label 2264*/ GIMT_Encode4(118760),
42318 /* 118379 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
42319 /* 118382 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
42320 /* 118385 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
42321 /* 118388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42322 /* 118392 */ GIM_Try, /*On fail goto*//*Label 2265*/ GIMT_Encode4(118466), // Rule ID 2761 //
42323 /* 118397 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42324 /* 118400 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42325 /* 118404 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42326 /* 118408 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42327 /* 118412 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42328 /* 118417 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42329 /* 118421 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42330 /* 118425 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42331 /* 118429 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
42332 /* 118433 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42333 /* 118438 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
42334 /* 118440 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42335 /* 118440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
42336 /* 118443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42337 /* 118445 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42338 /* 118449 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42339 /* 118453 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42340 /* 118455 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42341 /* 118458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42342 /* 118464 */ GIR_RootConstrainSelectedInstOperands,
42343 /* 118465 */ // GIR_Coverage, 2761,
42344 /* 118465 */ GIR_EraseRootFromParent_Done,
42345 /* 118466 */ // Label 2265: @118466
42346 /* 118466 */ GIM_Try, /*On fail goto*//*Label 2266*/ GIMT_Encode4(118540), // Rule ID 6312 //
42347 /* 118471 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42348 /* 118474 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42349 /* 118478 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42350 /* 118482 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42351 /* 118486 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42352 /* 118490 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42353 /* 118495 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42354 /* 118499 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42355 /* 118503 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
42356 /* 118507 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42357 /* 118512 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
42358 /* 118514 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42359 /* 118514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
42360 /* 118517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42361 /* 118519 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42362 /* 118523 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42363 /* 118527 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
42364 /* 118529 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42365 /* 118532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42366 /* 118538 */ GIR_RootConstrainSelectedInstOperands,
42367 /* 118539 */ // GIR_Coverage, 6312,
42368 /* 118539 */ GIR_EraseRootFromParent_Done,
42369 /* 118540 */ // Label 2266: @118540
42370 /* 118540 */ GIM_Try, /*On fail goto*//*Label 2267*/ GIMT_Encode4(118599), // Rule ID 2741 //
42371 /* 118545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42372 /* 118548 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42373 /* 118552 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42374 /* 118556 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42375 /* 118560 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42376 /* 118565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42377 /* 118569 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42378 /* 118573 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42379 /* 118575 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42380 /* 118575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
42381 /* 118578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42382 /* 118580 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
42383 /* 118582 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42384 /* 118586 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42385 /* 118588 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42386 /* 118591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42387 /* 118597 */ GIR_RootConstrainSelectedInstOperands,
42388 /* 118598 */ // GIR_Coverage, 2741,
42389 /* 118598 */ GIR_EraseRootFromParent_Done,
42390 /* 118599 */ // Label 2267: @118599
42391 /* 118599 */ GIM_Try, /*On fail goto*//*Label 2268*/ GIMT_Encode4(118658), // Rule ID 6306 //
42392 /* 118604 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42393 /* 118607 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42394 /* 118611 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42395 /* 118615 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42396 /* 118619 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42397 /* 118623 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42398 /* 118628 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42399 /* 118632 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42400 /* 118634 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42401 /* 118634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
42402 /* 118637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42403 /* 118639 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
42404 /* 118641 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42405 /* 118645 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
42406 /* 118647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42407 /* 118650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42408 /* 118656 */ GIR_RootConstrainSelectedInstOperands,
42409 /* 118657 */ // GIR_Coverage, 6306,
42410 /* 118657 */ GIR_EraseRootFromParent_Done,
42411 /* 118658 */ // Label 2268: @118658
42412 /* 118658 */ GIM_Try, /*On fail goto*//*Label 2269*/ GIMT_Encode4(118717), // Rule ID 2775 //
42413 /* 118663 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42414 /* 118666 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42415 /* 118670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42416 /* 118674 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
42417 /* 118678 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42418 /* 118682 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42419 /* 118686 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42420 /* 118691 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42421 /* 118693 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42422 /* 118693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
42423 /* 118696 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42424 /* 118698 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
42425 /* 118702 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
42426 /* 118704 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42427 /* 118706 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42428 /* 118709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42429 /* 118715 */ GIR_RootConstrainSelectedInstOperands,
42430 /* 118716 */ // GIR_Coverage, 2775,
42431 /* 118716 */ GIR_EraseRootFromParent_Done,
42432 /* 118717 */ // Label 2269: @118717
42433 /* 118717 */ GIM_Try, /*On fail goto*//*Label 2270*/ GIMT_Encode4(118759), // Rule ID 2723 //
42434 /* 118722 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42435 /* 118725 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42436 /* 118729 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42437 /* 118733 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42438 /* 118737 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42439 /* 118737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH),
42440 /* 118740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42441 /* 118742 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
42442 /* 118744 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
42443 /* 118746 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42444 /* 118748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42445 /* 118751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42446 /* 118757 */ GIR_RootConstrainSelectedInstOperands,
42447 /* 118758 */ // GIR_Coverage, 2723,
42448 /* 118758 */ GIR_EraseRootFromParent_Done,
42449 /* 118759 */ // Label 2270: @118759
42450 /* 118759 */ GIM_Reject,
42451 /* 118760 */ // Label 2264: @118760
42452 /* 118760 */ GIM_Reject,
42453 /* 118761 */ // Label 2257: @118761
42454 /* 118761 */ GIM_Try, /*On fail goto*//*Label 2271*/ GIMT_Encode4(119147),
42455 /* 118766 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
42456 /* 118769 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
42457 /* 118772 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
42458 /* 118775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42459 /* 118779 */ GIM_Try, /*On fail goto*//*Label 2272*/ GIMT_Encode4(118853), // Rule ID 2759 //
42460 /* 118784 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42461 /* 118787 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42462 /* 118791 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42463 /* 118795 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42464 /* 118799 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42465 /* 118804 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42466 /* 118808 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42467 /* 118812 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42468 /* 118816 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
42469 /* 118820 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42470 /* 118825 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
42471 /* 118827 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42472 /* 118827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
42473 /* 118830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42474 /* 118832 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42475 /* 118836 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42476 /* 118840 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42477 /* 118842 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42478 /* 118845 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42479 /* 118851 */ GIR_RootConstrainSelectedInstOperands,
42480 /* 118852 */ // GIR_Coverage, 2759,
42481 /* 118852 */ GIR_EraseRootFromParent_Done,
42482 /* 118853 */ // Label 2272: @118853
42483 /* 118853 */ GIM_Try, /*On fail goto*//*Label 2273*/ GIMT_Encode4(118927), // Rule ID 6310 //
42484 /* 118858 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42485 /* 118861 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42486 /* 118865 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42487 /* 118869 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42488 /* 118873 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42489 /* 118877 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42490 /* 118882 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42491 /* 118886 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42492 /* 118890 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
42493 /* 118894 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42494 /* 118899 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
42495 /* 118901 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42496 /* 118901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
42497 /* 118904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42498 /* 118906 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42499 /* 118910 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42500 /* 118914 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
42501 /* 118916 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42502 /* 118919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42503 /* 118925 */ GIR_RootConstrainSelectedInstOperands,
42504 /* 118926 */ // GIR_Coverage, 6310,
42505 /* 118926 */ GIR_EraseRootFromParent_Done,
42506 /* 118927 */ // Label 2273: @118927
42507 /* 118927 */ GIM_Try, /*On fail goto*//*Label 2274*/ GIMT_Encode4(118986), // Rule ID 2739 //
42508 /* 118932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42509 /* 118935 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42510 /* 118939 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42511 /* 118943 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42512 /* 118947 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42513 /* 118952 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42514 /* 118956 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42515 /* 118960 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42516 /* 118962 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42517 /* 118962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
42518 /* 118965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42519 /* 118967 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
42520 /* 118969 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42521 /* 118973 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42522 /* 118975 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42523 /* 118978 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42524 /* 118984 */ GIR_RootConstrainSelectedInstOperands,
42525 /* 118985 */ // GIR_Coverage, 2739,
42526 /* 118985 */ GIR_EraseRootFromParent_Done,
42527 /* 118986 */ // Label 2274: @118986
42528 /* 118986 */ GIM_Try, /*On fail goto*//*Label 2275*/ GIMT_Encode4(119045), // Rule ID 6304 //
42529 /* 118991 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42530 /* 118994 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42531 /* 118998 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42532 /* 119002 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42533 /* 119006 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42534 /* 119010 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42535 /* 119015 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42536 /* 119019 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42537 /* 119021 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42538 /* 119021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
42539 /* 119024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42540 /* 119026 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
42541 /* 119028 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42542 /* 119032 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
42543 /* 119034 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42544 /* 119037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42545 /* 119043 */ GIR_RootConstrainSelectedInstOperands,
42546 /* 119044 */ // GIR_Coverage, 6304,
42547 /* 119044 */ GIR_EraseRootFromParent_Done,
42548 /* 119045 */ // Label 2275: @119045
42549 /* 119045 */ GIM_Try, /*On fail goto*//*Label 2276*/ GIMT_Encode4(119104), // Rule ID 2773 //
42550 /* 119050 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42551 /* 119053 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42552 /* 119057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42553 /* 119061 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
42554 /* 119065 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42555 /* 119069 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42556 /* 119073 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42557 /* 119078 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42558 /* 119080 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42559 /* 119080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
42560 /* 119083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42561 /* 119085 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
42562 /* 119089 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
42563 /* 119091 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42564 /* 119093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42565 /* 119096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42566 /* 119102 */ GIR_RootConstrainSelectedInstOperands,
42567 /* 119103 */ // GIR_Coverage, 2773,
42568 /* 119103 */ GIR_EraseRootFromParent_Done,
42569 /* 119104 */ // Label 2276: @119104
42570 /* 119104 */ GIM_Try, /*On fail goto*//*Label 2277*/ GIMT_Encode4(119146), // Rule ID 2721 //
42571 /* 119109 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42572 /* 119112 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42573 /* 119116 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42574 /* 119120 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42575 /* 119124 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42576 /* 119124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS),
42577 /* 119127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42578 /* 119129 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
42579 /* 119131 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
42580 /* 119133 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42581 /* 119135 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42582 /* 119138 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42583 /* 119144 */ GIR_RootConstrainSelectedInstOperands,
42584 /* 119145 */ // GIR_Coverage, 2721,
42585 /* 119145 */ GIR_EraseRootFromParent_Done,
42586 /* 119146 */ // Label 2277: @119146
42587 /* 119146 */ GIM_Reject,
42588 /* 119147 */ // Label 2271: @119147
42589 /* 119147 */ GIM_Reject,
42590 /* 119148 */ // Label 2258: @119148
42591 /* 119148 */ GIM_Try, /*On fail goto*//*Label 2278*/ GIMT_Encode4(119534),
42592 /* 119153 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
42593 /* 119156 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
42594 /* 119159 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
42595 /* 119162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42596 /* 119166 */ GIM_Try, /*On fail goto*//*Label 2279*/ GIMT_Encode4(119240), // Rule ID 2757 //
42597 /* 119171 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42598 /* 119174 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42599 /* 119178 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42600 /* 119182 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42601 /* 119186 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42602 /* 119191 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42603 /* 119195 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42604 /* 119199 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42605 /* 119203 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
42606 /* 119207 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42607 /* 119212 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
42608 /* 119214 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42609 /* 119214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
42610 /* 119217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42611 /* 119219 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
42612 /* 119223 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42613 /* 119227 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
42614 /* 119229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42615 /* 119232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42616 /* 119238 */ GIR_RootConstrainSelectedInstOperands,
42617 /* 119239 */ // GIR_Coverage, 2757,
42618 /* 119239 */ GIR_EraseRootFromParent_Done,
42619 /* 119240 */ // Label 2279: @119240
42620 /* 119240 */ GIM_Try, /*On fail goto*//*Label 2280*/ GIMT_Encode4(119314), // Rule ID 6308 //
42621 /* 119245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42622 /* 119248 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42623 /* 119252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42624 /* 119256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42625 /* 119260 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42626 /* 119264 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42627 /* 119269 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42628 /* 119273 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42629 /* 119277 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
42630 /* 119281 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42631 /* 119286 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
42632 /* 119288 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42633 /* 119288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
42634 /* 119291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42635 /* 119293 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
42636 /* 119297 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42637 /* 119301 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
42638 /* 119303 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42639 /* 119306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42640 /* 119312 */ GIR_RootConstrainSelectedInstOperands,
42641 /* 119313 */ // GIR_Coverage, 6308,
42642 /* 119313 */ GIR_EraseRootFromParent_Done,
42643 /* 119314 */ // Label 2280: @119314
42644 /* 119314 */ GIM_Try, /*On fail goto*//*Label 2281*/ GIMT_Encode4(119373), // Rule ID 2737 //
42645 /* 119319 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42646 /* 119322 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42647 /* 119326 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42648 /* 119330 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42649 /* 119334 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42650 /* 119339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42651 /* 119343 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42652 /* 119347 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42653 /* 119349 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42654 /* 119349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
42655 /* 119352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42656 /* 119354 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
42657 /* 119356 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42658 /* 119360 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
42659 /* 119362 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42660 /* 119365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42661 /* 119371 */ GIR_RootConstrainSelectedInstOperands,
42662 /* 119372 */ // GIR_Coverage, 2737,
42663 /* 119372 */ GIR_EraseRootFromParent_Done,
42664 /* 119373 */ // Label 2281: @119373
42665 /* 119373 */ GIM_Try, /*On fail goto*//*Label 2282*/ GIMT_Encode4(119432), // Rule ID 6302 //
42666 /* 119378 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42667 /* 119381 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42668 /* 119385 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42669 /* 119389 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42670 /* 119393 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42671 /* 119397 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42672 /* 119402 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42673 /* 119406 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42674 /* 119408 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42675 /* 119408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
42676 /* 119411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42677 /* 119413 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
42678 /* 119415 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42679 /* 119419 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
42680 /* 119421 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42681 /* 119424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42682 /* 119430 */ GIR_RootConstrainSelectedInstOperands,
42683 /* 119431 */ // GIR_Coverage, 6302,
42684 /* 119431 */ GIR_EraseRootFromParent_Done,
42685 /* 119432 */ // Label 2282: @119432
42686 /* 119432 */ GIM_Try, /*On fail goto*//*Label 2283*/ GIMT_Encode4(119491), // Rule ID 2771 //
42687 /* 119437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42688 /* 119440 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42689 /* 119444 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42690 /* 119448 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
42691 /* 119452 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42692 /* 119456 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42693 /* 119460 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42694 /* 119465 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42695 /* 119467 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42696 /* 119467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
42697 /* 119470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42698 /* 119472 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin
42699 /* 119476 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
42700 /* 119478 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
42701 /* 119480 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42702 /* 119483 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42703 /* 119489 */ GIR_RootConstrainSelectedInstOperands,
42704 /* 119490 */ // GIR_Coverage, 2771,
42705 /* 119490 */ GIR_EraseRootFromParent_Done,
42706 /* 119491 */ // Label 2283: @119491
42707 /* 119491 */ GIM_Try, /*On fail goto*//*Label 2284*/ GIMT_Encode4(119533), // Rule ID 2719 //
42708 /* 119496 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42709 /* 119499 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42710 /* 119503 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42711 /* 119507 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42712 /* 119511 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42713 /* 119511 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD),
42714 /* 119514 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42715 /* 119516 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
42716 /* 119518 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
42717 /* 119520 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
42718 /* 119522 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42719 /* 119525 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42720 /* 119531 */ GIR_RootConstrainSelectedInstOperands,
42721 /* 119532 */ // GIR_Coverage, 2719,
42722 /* 119532 */ GIR_EraseRootFromParent_Done,
42723 /* 119533 */ // Label 2284: @119533
42724 /* 119533 */ GIM_Reject,
42725 /* 119534 */ // Label 2278: @119534
42726 /* 119534 */ GIM_Reject,
42727 /* 119535 */ // Label 2259: @119535
42728 /* 119535 */ GIM_Try, /*On fail goto*//*Label 2285*/ GIMT_Encode4(119590), // Rule ID 2872 //
42729 /* 119540 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42730 /* 119543 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
42731 /* 119546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
42732 /* 119549 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
42733 /* 119552 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42734 /* 119556 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42735 /* 119560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42736 /* 119564 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42737 /* 119568 */ // (fma:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm, DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
42738 /* 119568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd),
42739 /* 119571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42740 /* 119573 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
42741 /* 119575 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
42742 /* 119577 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42743 /* 119579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42744 /* 119582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42745 /* 119588 */ GIR_RootConstrainSelectedInstOperands,
42746 /* 119589 */ // GIR_Coverage, 2872,
42747 /* 119589 */ GIR_EraseRootFromParent_Done,
42748 /* 119590 */ // Label 2285: @119590
42749 /* 119590 */ GIM_Reject,
42750 /* 119591 */ // Label 2260: @119591
42751 /* 119591 */ GIM_Try, /*On fail goto*//*Label 2286*/ GIMT_Encode4(119842),
42752 /* 119596 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42753 /* 119599 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
42754 /* 119602 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
42755 /* 119605 */ GIM_Try, /*On fail goto*//*Label 2287*/ GIMT_Encode4(119674), // Rule ID 4429 //
42756 /* 119610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
42757 /* 119613 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42758 /* 119617 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42759 /* 119621 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42760 /* 119625 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
42761 /* 119629 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42762 /* 119634 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42763 /* 119638 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42764 /* 119642 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42765 /* 119644 */ // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
42766 /* 119644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
42767 /* 119647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42768 /* 119649 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
42769 /* 119651 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
42770 /* 119655 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
42771 /* 119657 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42772 /* 119660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42773 /* 119666 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42774 /* 119672 */ GIR_RootConstrainSelectedInstOperands,
42775 /* 119673 */ // GIR_Coverage, 4429,
42776 /* 119673 */ GIR_EraseRootFromParent_Done,
42777 /* 119674 */ // Label 2287: @119674
42778 /* 119674 */ GIM_Try, /*On fail goto*//*Label 2288*/ GIMT_Encode4(119743), // Rule ID 6648 //
42779 /* 119679 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
42780 /* 119682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42781 /* 119686 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42782 /* 119690 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42783 /* 119694 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42784 /* 119698 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
42785 /* 119702 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42786 /* 119707 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42787 /* 119711 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42788 /* 119713 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m2, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
42789 /* 119713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
42790 /* 119716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42791 /* 119718 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
42792 /* 119720 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
42793 /* 119724 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2
42794 /* 119726 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42795 /* 119729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42796 /* 119735 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42797 /* 119741 */ GIR_RootConstrainSelectedInstOperands,
42798 /* 119742 */ // GIR_Coverage, 6648,
42799 /* 119742 */ GIR_EraseRootFromParent_Done,
42800 /* 119743 */ // Label 2288: @119743
42801 /* 119743 */ GIM_Try, /*On fail goto*//*Label 2289*/ GIMT_Encode4(119789), // Rule ID 2873 //
42802 /* 119748 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42803 /* 119751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42804 /* 119755 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42805 /* 119759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42806 /* 119763 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42807 /* 119767 */ // (fma:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm, QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
42808 /* 119767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq),
42809 /* 119770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42810 /* 119772 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
42811 /* 119774 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
42812 /* 119776 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42813 /* 119778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42814 /* 119781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42815 /* 119787 */ GIR_RootConstrainSelectedInstOperands,
42816 /* 119788 */ // GIR_Coverage, 2873,
42817 /* 119788 */ GIR_EraseRootFromParent_Done,
42818 /* 119789 */ // Label 2289: @119789
42819 /* 119789 */ GIM_Try, /*On fail goto*//*Label 2290*/ GIMT_Encode4(119841), // Rule ID 4425 //
42820 /* 119794 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
42821 /* 119797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42822 /* 119801 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42823 /* 119805 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42824 /* 119809 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42825 /* 119813 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
42826 /* 119813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16),
42827 /* 119816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42828 /* 119818 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
42829 /* 119820 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1
42830 /* 119822 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
42831 /* 119824 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42832 /* 119827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42833 /* 119833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42834 /* 119839 */ GIR_RootConstrainSelectedInstOperands,
42835 /* 119840 */ // GIR_Coverage, 4425,
42836 /* 119840 */ GIR_EraseRootFromParent_Done,
42837 /* 119841 */ // Label 2290: @119841
42838 /* 119841 */ GIM_Reject,
42839 /* 119842 */ // Label 2286: @119842
42840 /* 119842 */ GIM_Reject,
42841 /* 119843 */ // Label 2261: @119843
42842 /* 119843 */ GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(120022),
42843 /* 119848 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
42844 /* 119851 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42845 /* 119854 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
42846 /* 119857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42847 /* 119861 */ GIM_Try, /*On fail goto*//*Label 2292*/ GIMT_Encode4(119920), // Rule ID 2876 //
42848 /* 119866 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
42849 /* 119869 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42850 /* 119873 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42851 /* 119877 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
42852 /* 119881 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42853 /* 119886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42854 /* 119890 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42855 /* 119894 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42856 /* 119896 */ // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
42857 /* 119896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd),
42858 /* 119899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42859 /* 119901 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
42860 /* 119903 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42861 /* 119907 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42862 /* 119909 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42863 /* 119912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42864 /* 119918 */ GIR_RootConstrainSelectedInstOperands,
42865 /* 119919 */ // GIR_Coverage, 2876,
42866 /* 119919 */ GIR_EraseRootFromParent_Done,
42867 /* 119920 */ // Label 2292: @119920
42868 /* 119920 */ GIM_Try, /*On fail goto*//*Label 2293*/ GIMT_Encode4(119979), // Rule ID 6365 //
42869 /* 119925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
42870 /* 119928 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42871 /* 119932 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42872 /* 119936 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42873 /* 119940 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
42874 /* 119944 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42875 /* 119949 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42876 /* 119953 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42877 /* 119955 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm, (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
42878 /* 119955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd),
42879 /* 119958 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42880 /* 119960 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
42881 /* 119962 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42882 /* 119966 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42883 /* 119968 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42884 /* 119971 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42885 /* 119977 */ GIR_RootConstrainSelectedInstOperands,
42886 /* 119978 */ // GIR_Coverage, 6365,
42887 /* 119978 */ GIR_EraseRootFromParent_Done,
42888 /* 119979 */ // Label 2293: @119979
42889 /* 119979 */ GIM_Try, /*On fail goto*//*Label 2294*/ GIMT_Encode4(120021), // Rule ID 2874 //
42890 /* 119984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
42891 /* 119987 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42892 /* 119991 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42893 /* 119995 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42894 /* 119999 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMAfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
42895 /* 119999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfd),
42896 /* 120002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42897 /* 120004 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
42898 /* 120006 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
42899 /* 120008 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42900 /* 120010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42901 /* 120013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42902 /* 120019 */ GIR_RootConstrainSelectedInstOperands,
42903 /* 120020 */ // GIR_Coverage, 2874,
42904 /* 120020 */ GIR_EraseRootFromParent_Done,
42905 /* 120021 */ // Label 2294: @120021
42906 /* 120021 */ GIM_Reject,
42907 /* 120022 */ // Label 2291: @120022
42908 /* 120022 */ GIM_Reject,
42909 /* 120023 */ // Label 2262: @120023
42910 /* 120023 */ GIM_Try, /*On fail goto*//*Label 2295*/ GIMT_Encode4(120400),
42911 /* 120028 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42912 /* 120031 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42913 /* 120034 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
42914 /* 120037 */ GIM_Try, /*On fail goto*//*Label 2296*/ GIMT_Encode4(120100), // Rule ID 2877 //
42915 /* 120042 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
42916 /* 120045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42917 /* 120049 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42918 /* 120053 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42919 /* 120057 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
42920 /* 120061 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42921 /* 120066 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42922 /* 120070 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42923 /* 120074 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42924 /* 120076 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
42925 /* 120076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq),
42926 /* 120079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42927 /* 120081 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
42928 /* 120083 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42929 /* 120087 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42930 /* 120089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42931 /* 120092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42932 /* 120098 */ GIR_RootConstrainSelectedInstOperands,
42933 /* 120099 */ // GIR_Coverage, 2877,
42934 /* 120099 */ GIR_EraseRootFromParent_Done,
42935 /* 120100 */ // Label 2296: @120100
42936 /* 120100 */ GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(120169), // Rule ID 4415 //
42937 /* 120105 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
42938 /* 120108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42939 /* 120112 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42940 /* 120116 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42941 /* 120120 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
42942 /* 120124 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42943 /* 120129 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42944 /* 120133 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42945 /* 120137 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42946 /* 120139 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
42947 /* 120139 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
42948 /* 120142 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42949 /* 120144 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
42950 /* 120146 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
42951 /* 120150 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
42952 /* 120152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42953 /* 120155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42954 /* 120161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42955 /* 120167 */ GIR_RootConstrainSelectedInstOperands,
42956 /* 120168 */ // GIR_Coverage, 4415,
42957 /* 120168 */ GIR_EraseRootFromParent_Done,
42958 /* 120169 */ // Label 2297: @120169
42959 /* 120169 */ GIM_Try, /*On fail goto*//*Label 2298*/ GIMT_Encode4(120232), // Rule ID 6366 //
42960 /* 120174 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
42961 /* 120177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42962 /* 120181 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42963 /* 120185 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42964 /* 120189 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42965 /* 120193 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
42966 /* 120197 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42967 /* 120202 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42968 /* 120206 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42969 /* 120208 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm, (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
42970 /* 120208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq),
42971 /* 120211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42972 /* 120213 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
42973 /* 120215 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42974 /* 120219 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42975 /* 120221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42976 /* 120224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42977 /* 120230 */ GIR_RootConstrainSelectedInstOperands,
42978 /* 120231 */ // GIR_Coverage, 6366,
42979 /* 120231 */ GIR_EraseRootFromParent_Done,
42980 /* 120232 */ // Label 2298: @120232
42981 /* 120232 */ GIM_Try, /*On fail goto*//*Label 2299*/ GIMT_Encode4(120301), // Rule ID 6646 //
42982 /* 120237 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
42983 /* 120240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42984 /* 120244 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42985 /* 120248 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42986 /* 120252 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42987 /* 120256 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
42988 /* 120260 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42989 /* 120265 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42990 /* 120269 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42991 /* 120271 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m2, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
42992 /* 120271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
42993 /* 120274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42994 /* 120276 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
42995 /* 120278 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
42996 /* 120282 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2
42997 /* 120284 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42998 /* 120287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42999 /* 120293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43000 /* 120299 */ GIR_RootConstrainSelectedInstOperands,
43001 /* 120300 */ // GIR_Coverage, 6646,
43002 /* 120300 */ GIR_EraseRootFromParent_Done,
43003 /* 120301 */ // Label 2299: @120301
43004 /* 120301 */ GIM_Try, /*On fail goto*//*Label 2300*/ GIMT_Encode4(120347), // Rule ID 2875 //
43005 /* 120306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
43006 /* 120309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43007 /* 120313 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43008 /* 120317 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43009 /* 120321 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43010 /* 120325 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMAfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
43011 /* 120325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfq),
43012 /* 120328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43013 /* 120330 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
43014 /* 120332 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43015 /* 120334 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43016 /* 120336 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43017 /* 120339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43018 /* 120345 */ GIR_RootConstrainSelectedInstOperands,
43019 /* 120346 */ // GIR_Coverage, 2875,
43020 /* 120346 */ GIR_EraseRootFromParent_Done,
43021 /* 120347 */ // Label 2300: @120347
43022 /* 120347 */ GIM_Try, /*On fail goto*//*Label 2301*/ GIMT_Encode4(120399), // Rule ID 4421 //
43023 /* 120352 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
43024 /* 120355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43025 /* 120359 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43026 /* 120363 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43027 /* 120367 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43028 /* 120371 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
43029 /* 120371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32),
43030 /* 120374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43031 /* 120376 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
43032 /* 120378 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1
43033 /* 120380 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
43034 /* 120382 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43035 /* 120385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43036 /* 120391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43037 /* 120397 */ GIR_RootConstrainSelectedInstOperands,
43038 /* 120398 */ // GIR_Coverage, 4421,
43039 /* 120398 */ GIR_EraseRootFromParent_Done,
43040 /* 120399 */ // Label 2301: @120399
43041 /* 120399 */ GIM_Reject,
43042 /* 120400 */ // Label 2295: @120400
43043 /* 120400 */ GIM_Reject,
43044 /* 120401 */ // Label 2263: @120401
43045 /* 120401 */ GIM_Reject,
43046 /* 120402 */ // Label 44: @120402
43047 /* 120402 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2305*/ GIMT_Encode4(120566),
43048 /* 120413 */ /*GILLT_s16*//*Label 2302*/ GIMT_Encode4(120425),
43049 /* 120417 */ /*GILLT_s32*//*Label 2303*/ GIMT_Encode4(120472),
43050 /* 120421 */ /*GILLT_s64*//*Label 2304*/ GIMT_Encode4(120519),
43051 /* 120425 */ // Label 2302: @120425
43052 /* 120425 */ GIM_Try, /*On fail goto*//*Label 2306*/ GIMT_Encode4(120471), // Rule ID 633 //
43053 /* 120430 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43054 /* 120433 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
43055 /* 120436 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
43056 /* 120439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43057 /* 120443 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43058 /* 120447 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43059 /* 120451 */ // (fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43060 /* 120451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH),
43061 /* 120454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43062 /* 120456 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
43063 /* 120458 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
43064 /* 120460 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43065 /* 120463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43066 /* 120469 */ GIR_RootConstrainSelectedInstOperands,
43067 /* 120470 */ // GIR_Coverage, 633,
43068 /* 120470 */ GIR_EraseRootFromParent_Done,
43069 /* 120471 */ // Label 2306: @120471
43070 /* 120471 */ GIM_Reject,
43071 /* 120472 */ // Label 2303: @120472
43072 /* 120472 */ GIM_Try, /*On fail goto*//*Label 2307*/ GIMT_Encode4(120518), // Rule ID 631 //
43073 /* 120477 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2),
43074 /* 120480 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
43075 /* 120483 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
43076 /* 120486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43077 /* 120490 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43078 /* 120494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43079 /* 120498 */ // (fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43080 /* 120498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS),
43081 /* 120501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43082 /* 120503 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
43083 /* 120505 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
43084 /* 120507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43085 /* 120510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43086 /* 120516 */ GIR_RootConstrainSelectedInstOperands,
43087 /* 120517 */ // GIR_Coverage, 631,
43088 /* 120517 */ GIR_EraseRootFromParent_Done,
43089 /* 120518 */ // Label 2307: @120518
43090 /* 120518 */ GIM_Reject,
43091 /* 120519 */ // Label 2304: @120519
43092 /* 120519 */ GIM_Try, /*On fail goto*//*Label 2308*/ GIMT_Encode4(120565), // Rule ID 629 //
43093 /* 120524 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
43094 /* 120527 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
43095 /* 120530 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
43096 /* 120533 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43097 /* 120537 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43098 /* 120541 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43099 /* 120545 */ // (fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43100 /* 120545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD),
43101 /* 120548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43102 /* 120550 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
43103 /* 120552 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
43104 /* 120554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43105 /* 120557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43106 /* 120563 */ GIR_RootConstrainSelectedInstOperands,
43107 /* 120564 */ // GIR_Coverage, 629,
43108 /* 120564 */ GIR_EraseRootFromParent_Done,
43109 /* 120565 */ // Label 2308: @120565
43110 /* 120565 */ GIM_Reject,
43111 /* 120566 */ // Label 2305: @120566
43112 /* 120566 */ GIM_Reject,
43113 /* 120567 */ // Label 45: @120567
43114 /* 120567 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2316*/ GIMT_Encode4(123006),
43115 /* 120578 */ /*GILLT_s16*//*Label 2309*/ GIMT_Encode4(120630),
43116 /* 120582 */ /*GILLT_s32*//*Label 2310*/ GIMT_Encode4(121280),
43117 /* 120586 */ /*GILLT_s64*//*Label 2311*/ GIMT_Encode4(122082), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
43118 /* 120614 */ /*GILLT_v4s16*//*Label 2312*/ GIMT_Encode4(122732),
43119 /* 120618 */ /*GILLT_v8s16*//*Label 2313*/ GIMT_Encode4(122770),
43120 /* 120622 */ /*GILLT_v2s32*//*Label 2314*/ GIMT_Encode4(122869),
43121 /* 120626 */ /*GILLT_v4s32*//*Label 2315*/ GIMT_Encode4(122907),
43122 /* 120630 */ // Label 2309: @120630
43123 /* 120630 */ GIM_Try, /*On fail goto*//*Label 2317*/ GIMT_Encode4(121279),
43124 /* 120635 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
43125 /* 120638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43126 /* 120642 */ GIM_Try, /*On fail goto*//*Label 2318*/ GIMT_Encode4(120727), // Rule ID 2781 //
43127 /* 120647 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43128 /* 120650 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43129 /* 120654 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43130 /* 120658 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43131 /* 120662 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43132 /* 120666 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
43133 /* 120670 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
43134 /* 120674 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43135 /* 120678 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
43136 /* 120682 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43137 /* 120687 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43138 /* 120692 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43139 /* 120697 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43140 /* 120699 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43141 /* 120699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
43142 /* 120702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43143 /* 120704 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43144 /* 120708 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43145 /* 120712 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43146 /* 120716 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43147 /* 120719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43148 /* 120725 */ GIR_RootConstrainSelectedInstOperands,
43149 /* 120726 */ // GIR_Coverage, 2781,
43150 /* 120726 */ GIR_EraseRootFromParent_Done,
43151 /* 120727 */ // Label 2318: @120727
43152 /* 120727 */ GIM_Try, /*On fail goto*//*Label 2319*/ GIMT_Encode4(120812), // Rule ID 6318 //
43153 /* 120732 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43154 /* 120735 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43155 /* 120739 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43156 /* 120743 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43157 /* 120747 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43158 /* 120751 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
43159 /* 120755 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43160 /* 120760 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
43161 /* 120764 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43162 /* 120768 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
43163 /* 120772 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43164 /* 120777 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43165 /* 120782 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43166 /* 120784 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43167 /* 120784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
43168 /* 120787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43169 /* 120789 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43170 /* 120793 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43171 /* 120797 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
43172 /* 120801 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43173 /* 120804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43174 /* 120810 */ GIR_RootConstrainSelectedInstOperands,
43175 /* 120811 */ // GIR_Coverage, 6318,
43176 /* 120811 */ GIR_EraseRootFromParent_Done,
43177 /* 120812 */ // Label 2319: @120812
43178 /* 120812 */ GIM_Try, /*On fail goto*//*Label 2320*/ GIMT_Encode4(120897), // Rule ID 2780 //
43179 /* 120817 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43180 /* 120820 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43181 /* 120824 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43182 /* 120828 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43183 /* 120832 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43184 /* 120836 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
43185 /* 120840 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
43186 /* 120844 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43187 /* 120848 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
43188 /* 120852 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43189 /* 120857 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43190 /* 120862 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43191 /* 120867 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43192 /* 120869 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43193 /* 120869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
43194 /* 120872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43195 /* 120874 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43196 /* 120878 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43197 /* 120882 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43198 /* 120886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43199 /* 120889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43200 /* 120895 */ GIR_RootConstrainSelectedInstOperands,
43201 /* 120896 */ // GIR_Coverage, 2780,
43202 /* 120896 */ GIR_EraseRootFromParent_Done,
43203 /* 120897 */ // Label 2320: @120897
43204 /* 120897 */ GIM_Try, /*On fail goto*//*Label 2321*/ GIMT_Encode4(120982), // Rule ID 6317 //
43205 /* 120902 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43206 /* 120905 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43207 /* 120909 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43208 /* 120913 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43209 /* 120917 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43210 /* 120921 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
43211 /* 120925 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43212 /* 120930 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
43213 /* 120934 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43214 /* 120938 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
43215 /* 120942 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43216 /* 120947 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43217 /* 120952 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43218 /* 120954 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43219 /* 120954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
43220 /* 120957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43221 /* 120959 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43222 /* 120963 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43223 /* 120967 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
43224 /* 120971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43225 /* 120974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43226 /* 120980 */ GIR_RootConstrainSelectedInstOperands,
43227 /* 120981 */ // GIR_Coverage, 6317,
43228 /* 120981 */ GIR_EraseRootFromParent_Done,
43229 /* 120982 */ // Label 2321: @120982
43230 /* 120982 */ GIM_Try, /*On fail goto*//*Label 2322*/ GIMT_Encode4(121055), // Rule ID 2755 //
43231 /* 120987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43232 /* 120990 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43233 /* 120994 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43234 /* 120998 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43235 /* 121002 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43236 /* 121006 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
43237 /* 121010 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43238 /* 121015 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43239 /* 121020 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43240 /* 121025 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43241 /* 121027 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43242 /* 121027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
43243 /* 121030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43244 /* 121032 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43245 /* 121036 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43246 /* 121040 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43247 /* 121044 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43248 /* 121047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43249 /* 121053 */ GIR_RootConstrainSelectedInstOperands,
43250 /* 121054 */ // GIR_Coverage, 2755,
43251 /* 121054 */ GIR_EraseRootFromParent_Done,
43252 /* 121055 */ // Label 2322: @121055
43253 /* 121055 */ GIM_Try, /*On fail goto*//*Label 2323*/ GIMT_Encode4(121128), // Rule ID 2754 //
43254 /* 121060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43255 /* 121063 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43256 /* 121067 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43257 /* 121071 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43258 /* 121075 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43259 /* 121079 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
43260 /* 121083 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43261 /* 121088 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43262 /* 121093 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43263 /* 121098 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43264 /* 121100 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43265 /* 121100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
43266 /* 121103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43267 /* 121105 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43268 /* 121109 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43269 /* 121113 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43270 /* 121117 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43271 /* 121120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43272 /* 121126 */ GIR_RootConstrainSelectedInstOperands,
43273 /* 121127 */ // GIR_Coverage, 2754,
43274 /* 121127 */ GIR_EraseRootFromParent_Done,
43275 /* 121128 */ // Label 2323: @121128
43276 /* 121128 */ GIM_Try, /*On fail goto*//*Label 2324*/ GIMT_Encode4(121188), // Rule ID 645 //
43277 /* 121133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43278 /* 121136 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43279 /* 121140 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
43280 /* 121144 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43281 /* 121148 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43282 /* 121152 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43283 /* 121157 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43284 /* 121162 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43285 /* 121164 */ // (fneg:{ *:[f16] } (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43286 /* 121164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH),
43287 /* 121167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43288 /* 121169 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43289 /* 121173 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43290 /* 121177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43291 /* 121180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43292 /* 121186 */ GIR_RootConstrainSelectedInstOperands,
43293 /* 121187 */ // GIR_Coverage, 645,
43294 /* 121187 */ GIR_EraseRootFromParent_Done,
43295 /* 121188 */ // Label 2324: @121188
43296 /* 121188 */ GIM_Try, /*On fail goto*//*Label 2325*/ GIMT_Encode4(121248), // Rule ID 644 //
43297 /* 121193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43298 /* 121196 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43299 /* 121200 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
43300 /* 121204 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43301 /* 121208 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43302 /* 121212 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43303 /* 121217 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43304 /* 121222 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43305 /* 121224 */ // (fneg:{ *:[f16] } (strict_fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43306 /* 121224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH),
43307 /* 121227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43308 /* 121229 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43309 /* 121233 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43310 /* 121237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43311 /* 121240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43312 /* 121246 */ GIR_RootConstrainSelectedInstOperands,
43313 /* 121247 */ // GIR_Coverage, 644,
43314 /* 121247 */ GIR_EraseRootFromParent_Done,
43315 /* 121248 */ // Label 2325: @121248
43316 /* 121248 */ GIM_Try, /*On fail goto*//*Label 2326*/ GIMT_Encode4(121278), // Rule ID 691 //
43317 /* 121253 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43318 /* 121256 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43319 /* 121260 */ // (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VNEGH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
43320 /* 121260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGH),
43321 /* 121263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43322 /* 121265 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
43323 /* 121267 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43324 /* 121270 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43325 /* 121276 */ GIR_RootConstrainSelectedInstOperands,
43326 /* 121277 */ // GIR_Coverage, 691,
43327 /* 121277 */ GIR_EraseRootFromParent_Done,
43328 /* 121278 */ // Label 2326: @121278
43329 /* 121278 */ GIM_Reject,
43330 /* 121279 */ // Label 2317: @121279
43331 /* 121279 */ GIM_Reject,
43332 /* 121280 */ // Label 2310: @121280
43333 /* 121280 */ GIM_Try, /*On fail goto*//*Label 2327*/ GIMT_Encode4(122081),
43334 /* 121285 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
43335 /* 121288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43336 /* 121292 */ GIM_Try, /*On fail goto*//*Label 2328*/ GIMT_Encode4(121377), // Rule ID 2779 //
43337 /* 121297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
43338 /* 121300 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43339 /* 121304 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43340 /* 121308 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43341 /* 121312 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43342 /* 121316 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43343 /* 121320 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
43344 /* 121324 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43345 /* 121328 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
43346 /* 121332 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43347 /* 121337 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43348 /* 121342 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43349 /* 121347 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43350 /* 121349 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43351 /* 121349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
43352 /* 121352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43353 /* 121354 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43354 /* 121358 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43355 /* 121362 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43356 /* 121366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43357 /* 121369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43358 /* 121375 */ GIR_RootConstrainSelectedInstOperands,
43359 /* 121376 */ // GIR_Coverage, 2779,
43360 /* 121376 */ GIR_EraseRootFromParent_Done,
43361 /* 121377 */ // Label 2328: @121377
43362 /* 121377 */ GIM_Try, /*On fail goto*//*Label 2329*/ GIMT_Encode4(121462), // Rule ID 6316 //
43363 /* 121382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
43364 /* 121385 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43365 /* 121389 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43366 /* 121393 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43367 /* 121397 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43368 /* 121401 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43369 /* 121405 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43370 /* 121410 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
43371 /* 121414 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43372 /* 121418 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
43373 /* 121422 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43374 /* 121427 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43375 /* 121432 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43376 /* 121434 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43377 /* 121434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
43378 /* 121437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43379 /* 121439 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43380 /* 121443 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43381 /* 121447 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
43382 /* 121451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43383 /* 121454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43384 /* 121460 */ GIR_RootConstrainSelectedInstOperands,
43385 /* 121461 */ // GIR_Coverage, 6316,
43386 /* 121461 */ GIR_EraseRootFromParent_Done,
43387 /* 121462 */ // Label 2329: @121462
43388 /* 121462 */ GIM_Try, /*On fail goto*//*Label 2330*/ GIMT_Encode4(121547), // Rule ID 2778 //
43389 /* 121467 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
43390 /* 121470 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43391 /* 121474 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43392 /* 121478 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43393 /* 121482 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43394 /* 121486 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43395 /* 121490 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
43396 /* 121494 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43397 /* 121498 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
43398 /* 121502 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43399 /* 121507 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43400 /* 121512 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43401 /* 121517 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43402 /* 121519 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43403 /* 121519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
43404 /* 121522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43405 /* 121524 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43406 /* 121528 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43407 /* 121532 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43408 /* 121536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43409 /* 121539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43410 /* 121545 */ GIR_RootConstrainSelectedInstOperands,
43411 /* 121546 */ // GIR_Coverage, 2778,
43412 /* 121546 */ GIR_EraseRootFromParent_Done,
43413 /* 121547 */ // Label 2330: @121547
43414 /* 121547 */ GIM_Try, /*On fail goto*//*Label 2331*/ GIMT_Encode4(121632), // Rule ID 6315 //
43415 /* 121552 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
43416 /* 121555 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43417 /* 121559 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43418 /* 121563 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43419 /* 121567 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43420 /* 121571 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43421 /* 121575 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43422 /* 121580 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
43423 /* 121584 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43424 /* 121588 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
43425 /* 121592 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43426 /* 121597 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43427 /* 121602 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43428 /* 121604 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43429 /* 121604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
43430 /* 121607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43431 /* 121609 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43432 /* 121613 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43433 /* 121617 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
43434 /* 121621 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43435 /* 121624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43436 /* 121630 */ GIR_RootConstrainSelectedInstOperands,
43437 /* 121631 */ // GIR_Coverage, 6315,
43438 /* 121631 */ GIR_EraseRootFromParent_Done,
43439 /* 121632 */ // Label 2331: @121632
43440 /* 121632 */ GIM_Try, /*On fail goto*//*Label 2332*/ GIMT_Encode4(121705), // Rule ID 2753 //
43441 /* 121637 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
43442 /* 121640 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43443 /* 121644 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43444 /* 121648 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43445 /* 121652 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43446 /* 121656 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43447 /* 121660 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43448 /* 121665 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43449 /* 121670 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43450 /* 121675 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43451 /* 121677 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43452 /* 121677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
43453 /* 121680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43454 /* 121682 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43455 /* 121686 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43456 /* 121690 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43457 /* 121694 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43458 /* 121697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43459 /* 121703 */ GIR_RootConstrainSelectedInstOperands,
43460 /* 121704 */ // GIR_Coverage, 2753,
43461 /* 121704 */ GIR_EraseRootFromParent_Done,
43462 /* 121705 */ // Label 2332: @121705
43463 /* 121705 */ GIM_Try, /*On fail goto*//*Label 2333*/ GIMT_Encode4(121778), // Rule ID 2752 //
43464 /* 121710 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
43465 /* 121713 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43466 /* 121717 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43467 /* 121721 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43468 /* 121725 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43469 /* 121729 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43470 /* 121733 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43471 /* 121738 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43472 /* 121743 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43473 /* 121748 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43474 /* 121750 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43475 /* 121750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
43476 /* 121753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43477 /* 121755 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43478 /* 121759 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43479 /* 121763 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43480 /* 121767 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43481 /* 121770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43482 /* 121776 */ GIR_RootConstrainSelectedInstOperands,
43483 /* 121777 */ // GIR_Coverage, 2752,
43484 /* 121777 */ GIR_EraseRootFromParent_Done,
43485 /* 121778 */ // Label 2333: @121778
43486 /* 121778 */ GIM_Try, /*On fail goto*//*Label 2334*/ GIMT_Encode4(121838), // Rule ID 643 //
43487 /* 121783 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2),
43488 /* 121786 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43489 /* 121790 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
43490 /* 121794 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43491 /* 121798 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43492 /* 121802 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43493 /* 121807 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43494 /* 121812 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43495 /* 121814 */ // (fneg:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43496 /* 121814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
43497 /* 121817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43498 /* 121819 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43499 /* 121823 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43500 /* 121827 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43501 /* 121830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43502 /* 121836 */ GIR_RootConstrainSelectedInstOperands,
43503 /* 121837 */ // GIR_Coverage, 643,
43504 /* 121837 */ GIR_EraseRootFromParent_Done,
43505 /* 121838 */ // Label 2334: @121838
43506 /* 121838 */ GIM_Try, /*On fail goto*//*Label 2335*/ GIMT_Encode4(121898), // Rule ID 642 //
43507 /* 121843 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2),
43508 /* 121846 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43509 /* 121850 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
43510 /* 121854 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43511 /* 121858 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43512 /* 121862 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43513 /* 121867 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43514 /* 121872 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43515 /* 121874 */ // (fneg:{ *:[f32] } (strict_fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43516 /* 121874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
43517 /* 121877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43518 /* 121879 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43519 /* 121883 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43520 /* 121887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43521 /* 121890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43522 /* 121896 */ GIR_RootConstrainSelectedInstOperands,
43523 /* 121897 */ // GIR_Coverage, 642,
43524 /* 121897 */ GIR_EraseRootFromParent_Done,
43525 /* 121898 */ // Label 2335: @121898
43526 /* 121898 */ GIM_Try, /*On fail goto*//*Label 2336*/ GIMT_Encode4(121928), // Rule ID 690 //
43527 /* 121903 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
43528 /* 121906 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43529 /* 121910 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VNEGS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
43530 /* 121910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGS),
43531 /* 121913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43532 /* 121915 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
43533 /* 121917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43534 /* 121920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43535 /* 121926 */ GIR_RootConstrainSelectedInstOperands,
43536 /* 121927 */ // GIR_Coverage, 690,
43537 /* 121927 */ GIR_EraseRootFromParent_Done,
43538 /* 121928 */ // Label 2336: @121928
43539 /* 121928 */ GIM_Try, /*On fail goto*//*Label 2337*/ GIMT_Encode4(122080), // Rule ID 3080 //
43540 /* 121933 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
43541 /* 121936 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43542 /* 121940 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VNEGfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
43543 /* 121940 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
43544 /* 121943 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43545 /* 121947 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43546 /* 121952 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
43547 /* 121954 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
43548 /* 121957 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43549 /* 121961 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43550 /* 121966 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
43551 /* 121969 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43552 /* 121974 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
43553 /* 121977 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43554 /* 121981 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43555 /* 121986 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
43556 /* 121989 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
43557 /* 121993 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
43558 /* 121996 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43559 /* 122001 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43560 /* 122006 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
43561 /* 122011 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
43562 /* 122014 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VNEGfd),
43563 /* 122018 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43564 /* 122023 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
43565 /* 122026 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
43566 /* 122029 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43567 /* 122035 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43568 /* 122037 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
43569 /* 122040 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43570 /* 122044 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43571 /* 122049 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
43572 /* 122052 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43573 /* 122057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43574 /* 122060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43575 /* 122062 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
43576 /* 122069 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
43577 /* 122074 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43578 /* 122079 */ // GIR_Coverage, 3080,
43579 /* 122079 */ GIR_EraseRootFromParent_Done,
43580 /* 122080 */ // Label 2337: @122080
43581 /* 122080 */ GIM_Reject,
43582 /* 122081 */ // Label 2327: @122081
43583 /* 122081 */ GIM_Reject,
43584 /* 122082 */ // Label 2311: @122082
43585 /* 122082 */ GIM_Try, /*On fail goto*//*Label 2338*/ GIMT_Encode4(122731),
43586 /* 122087 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
43587 /* 122090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43588 /* 122094 */ GIM_Try, /*On fail goto*//*Label 2339*/ GIMT_Encode4(122179), // Rule ID 2777 //
43589 /* 122099 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
43590 /* 122102 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43591 /* 122106 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43592 /* 122110 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43593 /* 122114 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43594 /* 122118 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43595 /* 122122 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
43596 /* 122126 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43597 /* 122130 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
43598 /* 122134 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43599 /* 122139 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43600 /* 122144 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43601 /* 122149 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43602 /* 122151 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43603 /* 122151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
43604 /* 122154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43605 /* 122156 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43606 /* 122160 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
43607 /* 122164 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
43608 /* 122168 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43609 /* 122171 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43610 /* 122177 */ GIR_RootConstrainSelectedInstOperands,
43611 /* 122178 */ // GIR_Coverage, 2777,
43612 /* 122178 */ GIR_EraseRootFromParent_Done,
43613 /* 122179 */ // Label 2339: @122179
43614 /* 122179 */ GIM_Try, /*On fail goto*//*Label 2340*/ GIMT_Encode4(122264), // Rule ID 6314 //
43615 /* 122184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
43616 /* 122187 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43617 /* 122191 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43618 /* 122195 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43619 /* 122199 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43620 /* 122203 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43621 /* 122207 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43622 /* 122212 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
43623 /* 122216 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43624 /* 122220 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
43625 /* 122224 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43626 /* 122229 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43627 /* 122234 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43628 /* 122236 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43629 /* 122236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
43630 /* 122239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43631 /* 122241 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43632 /* 122245 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
43633 /* 122249 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm
43634 /* 122253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43635 /* 122256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43636 /* 122262 */ GIR_RootConstrainSelectedInstOperands,
43637 /* 122263 */ // GIR_Coverage, 6314,
43638 /* 122263 */ GIR_EraseRootFromParent_Done,
43639 /* 122264 */ // Label 2340: @122264
43640 /* 122264 */ GIM_Try, /*On fail goto*//*Label 2341*/ GIMT_Encode4(122349), // Rule ID 2776 //
43641 /* 122269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
43642 /* 122272 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43643 /* 122276 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43644 /* 122280 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43645 /* 122284 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43646 /* 122288 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43647 /* 122292 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
43648 /* 122296 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43649 /* 122300 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
43650 /* 122304 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43651 /* 122309 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43652 /* 122314 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43653 /* 122319 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43654 /* 122321 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43655 /* 122321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
43656 /* 122324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43657 /* 122326 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43658 /* 122330 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
43659 /* 122334 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
43660 /* 122338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43661 /* 122341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43662 /* 122347 */ GIR_RootConstrainSelectedInstOperands,
43663 /* 122348 */ // GIR_Coverage, 2776,
43664 /* 122348 */ GIR_EraseRootFromParent_Done,
43665 /* 122349 */ // Label 2341: @122349
43666 /* 122349 */ GIM_Try, /*On fail goto*//*Label 2342*/ GIMT_Encode4(122434), // Rule ID 6313 //
43667 /* 122354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
43668 /* 122357 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43669 /* 122361 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43670 /* 122365 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43671 /* 122369 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43672 /* 122373 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43673 /* 122377 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43674 /* 122382 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
43675 /* 122386 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43676 /* 122390 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
43677 /* 122394 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43678 /* 122399 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43679 /* 122404 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43680 /* 122406 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43681 /* 122406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
43682 /* 122409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43683 /* 122411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43684 /* 122415 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
43685 /* 122419 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm
43686 /* 122423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43687 /* 122426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43688 /* 122432 */ GIR_RootConstrainSelectedInstOperands,
43689 /* 122433 */ // GIR_Coverage, 6313,
43690 /* 122433 */ GIR_EraseRootFromParent_Done,
43691 /* 122434 */ // Label 2342: @122434
43692 /* 122434 */ GIM_Try, /*On fail goto*//*Label 2343*/ GIMT_Encode4(122507), // Rule ID 2751 //
43693 /* 122439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
43694 /* 122442 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43695 /* 122446 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43696 /* 122450 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43697 /* 122454 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43698 /* 122458 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43699 /* 122462 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43700 /* 122467 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43701 /* 122472 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43702 /* 122477 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43703 /* 122479 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43704 /* 122479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
43705 /* 122482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43706 /* 122484 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43707 /* 122488 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
43708 /* 122492 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
43709 /* 122496 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43710 /* 122499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43711 /* 122505 */ GIR_RootConstrainSelectedInstOperands,
43712 /* 122506 */ // GIR_Coverage, 2751,
43713 /* 122506 */ GIR_EraseRootFromParent_Done,
43714 /* 122507 */ // Label 2343: @122507
43715 /* 122507 */ GIM_Try, /*On fail goto*//*Label 2344*/ GIMT_Encode4(122580), // Rule ID 2750 //
43716 /* 122512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
43717 /* 122515 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43718 /* 122519 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43719 /* 122523 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43720 /* 122527 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43721 /* 122531 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43722 /* 122535 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43723 /* 122540 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43724 /* 122545 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43725 /* 122550 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43726 /* 122552 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43727 /* 122552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
43728 /* 122555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43729 /* 122557 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43730 /* 122561 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
43731 /* 122565 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
43732 /* 122569 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43733 /* 122572 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43734 /* 122578 */ GIR_RootConstrainSelectedInstOperands,
43735 /* 122579 */ // GIR_Coverage, 2750,
43736 /* 122579 */ GIR_EraseRootFromParent_Done,
43737 /* 122580 */ // Label 2344: @122580
43738 /* 122580 */ GIM_Try, /*On fail goto*//*Label 2345*/ GIMT_Encode4(122640), // Rule ID 641 //
43739 /* 122585 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
43740 /* 122588 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43741 /* 122592 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
43742 /* 122596 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43743 /* 122600 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43744 /* 122604 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43745 /* 122609 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43746 /* 122614 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43747 /* 122616 */ // (fneg:{ *:[f64] } (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43748 /* 122616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
43749 /* 122619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43750 /* 122621 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
43751 /* 122625 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
43752 /* 122629 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43753 /* 122632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43754 /* 122638 */ GIR_RootConstrainSelectedInstOperands,
43755 /* 122639 */ // GIR_Coverage, 641,
43756 /* 122639 */ GIR_EraseRootFromParent_Done,
43757 /* 122640 */ // Label 2345: @122640
43758 /* 122640 */ GIM_Try, /*On fail goto*//*Label 2346*/ GIMT_Encode4(122700), // Rule ID 640 //
43759 /* 122645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
43760 /* 122648 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43761 /* 122652 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
43762 /* 122656 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43763 /* 122660 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43764 /* 122664 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43765 /* 122669 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43766 /* 122674 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43767 /* 122676 */ // (fneg:{ *:[f64] } (strict_fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43768 /* 122676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
43769 /* 122679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43770 /* 122681 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
43771 /* 122685 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
43772 /* 122689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43773 /* 122692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43774 /* 122698 */ GIR_RootConstrainSelectedInstOperands,
43775 /* 122699 */ // GIR_Coverage, 640,
43776 /* 122699 */ GIR_EraseRootFromParent_Done,
43777 /* 122700 */ // Label 2346: @122700
43778 /* 122700 */ GIM_Try, /*On fail goto*//*Label 2347*/ GIMT_Encode4(122730), // Rule ID 689 //
43779 /* 122705 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
43780 /* 122708 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43781 /* 122712 */ // (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VNEGD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
43782 /* 122712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGD),
43783 /* 122715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43784 /* 122717 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
43785 /* 122719 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43786 /* 122722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43787 /* 122728 */ GIR_RootConstrainSelectedInstOperands,
43788 /* 122729 */ // GIR_Coverage, 689,
43789 /* 122729 */ GIR_EraseRootFromParent_Done,
43790 /* 122730 */ // Label 2347: @122730
43791 /* 122730 */ GIM_Reject,
43792 /* 122731 */ // Label 2338: @122731
43793 /* 122731 */ GIM_Reject,
43794 /* 122732 */ // Label 2312: @122732
43795 /* 122732 */ GIM_Try, /*On fail goto*//*Label 2348*/ GIMT_Encode4(122769), // Rule ID 1694 //
43796 /* 122737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43797 /* 122740 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
43798 /* 122743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43799 /* 122747 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43800 /* 122751 */ // (fneg:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VNEGhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
43801 /* 122751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhd),
43802 /* 122754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43803 /* 122756 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
43804 /* 122758 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43805 /* 122761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43806 /* 122767 */ GIR_RootConstrainSelectedInstOperands,
43807 /* 122768 */ // GIR_Coverage, 1694,
43808 /* 122768 */ GIR_EraseRootFromParent_Done,
43809 /* 122769 */ // Label 2348: @122769
43810 /* 122769 */ GIM_Reject,
43811 /* 122770 */ // Label 2313: @122770
43812 /* 122770 */ GIM_Try, /*On fail goto*//*Label 2349*/ GIMT_Encode4(122868),
43813 /* 122775 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
43814 /* 122778 */ GIM_Try, /*On fail goto*//*Label 2350*/ GIMT_Encode4(122812), // Rule ID 1695 //
43815 /* 122783 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43816 /* 122786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43817 /* 122790 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43818 /* 122794 */ // (fneg:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VNEGhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
43819 /* 122794 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhq),
43820 /* 122797 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43821 /* 122799 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
43822 /* 122801 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43823 /* 122804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43824 /* 122810 */ GIR_RootConstrainSelectedInstOperands,
43825 /* 122811 */ // GIR_Coverage, 1695,
43826 /* 122811 */ GIR_EraseRootFromParent_Done,
43827 /* 122812 */ // Label 2350: @122812
43828 /* 122812 */ GIM_Try, /*On fail goto*//*Label 2351*/ GIMT_Encode4(122867), // Rule ID 4553 //
43829 /* 122817 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
43830 /* 122820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43831 /* 122824 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43832 /* 122828 */ // (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VNEGf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v)
43833 /* 122828 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43834 /* 122831 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43835 /* 122835 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43836 /* 122840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf16),
43837 /* 122843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43838 /* 122845 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
43839 /* 122847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43840 /* 122850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43841 /* 122856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43842 /* 122862 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43843 /* 122865 */ GIR_RootConstrainSelectedInstOperands,
43844 /* 122866 */ // GIR_Coverage, 4553,
43845 /* 122866 */ GIR_EraseRootFromParent_Done,
43846 /* 122867 */ // Label 2351: @122867
43847 /* 122867 */ GIM_Reject,
43848 /* 122868 */ // Label 2349: @122868
43849 /* 122868 */ GIM_Reject,
43850 /* 122869 */ // Label 2314: @122869
43851 /* 122869 */ GIM_Try, /*On fail goto*//*Label 2352*/ GIMT_Encode4(122906), // Rule ID 1692 //
43852 /* 122874 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43853 /* 122877 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
43854 /* 122880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43855 /* 122884 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43856 /* 122888 */ // (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VNEGfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
43857 /* 122888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGfd),
43858 /* 122891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43859 /* 122893 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
43860 /* 122895 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43861 /* 122898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43862 /* 122904 */ GIR_RootConstrainSelectedInstOperands,
43863 /* 122905 */ // GIR_Coverage, 1692,
43864 /* 122905 */ GIR_EraseRootFromParent_Done,
43865 /* 122906 */ // Label 2352: @122906
43866 /* 122906 */ GIM_Reject,
43867 /* 122907 */ // Label 2315: @122907
43868 /* 122907 */ GIM_Try, /*On fail goto*//*Label 2353*/ GIMT_Encode4(123005),
43869 /* 122912 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
43870 /* 122915 */ GIM_Try, /*On fail goto*//*Label 2354*/ GIMT_Encode4(122949), // Rule ID 1693 //
43871 /* 122920 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
43872 /* 122923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43873 /* 122927 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43874 /* 122931 */ // (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VNEGf32q:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
43875 /* 122931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGf32q),
43876 /* 122934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43877 /* 122936 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
43878 /* 122938 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43879 /* 122941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43880 /* 122947 */ GIR_RootConstrainSelectedInstOperands,
43881 /* 122948 */ // GIR_Coverage, 1693,
43882 /* 122948 */ GIR_EraseRootFromParent_Done,
43883 /* 122949 */ // Label 2354: @122949
43884 /* 122949 */ GIM_Try, /*On fail goto*//*Label 2355*/ GIMT_Encode4(123004), // Rule ID 4555 //
43885 /* 122954 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
43886 /* 122957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43887 /* 122961 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43888 /* 122965 */ // (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VNEGf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v)
43889 /* 122965 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43890 /* 122968 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43891 /* 122972 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43892 /* 122977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf32),
43893 /* 122980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43894 /* 122982 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
43895 /* 122984 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43896 /* 122987 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43897 /* 122993 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43898 /* 122999 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43899 /* 123002 */ GIR_RootConstrainSelectedInstOperands,
43900 /* 123003 */ // GIR_Coverage, 4555,
43901 /* 123003 */ GIR_EraseRootFromParent_Done,
43902 /* 123004 */ // Label 2355: @123004
43903 /* 123004 */ GIM_Reject,
43904 /* 123005 */ // Label 2353: @123005
43905 /* 123005 */ GIM_Reject,
43906 /* 123006 */ // Label 2316: @123006
43907 /* 123006 */ GIM_Reject,
43908 /* 123007 */ // Label 46: @123007
43909 /* 123007 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2359*/ GIMT_Encode4(123258),
43910 /* 123018 */ /*GILLT_s32*//*Label 2356*/ GIMT_Encode4(123066),
43911 /* 123022 */ /*GILLT_s64*//*Label 2357*/ GIMT_Encode4(123126), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
43912 /* 123062 */ /*GILLT_v4s32*//*Label 2358*/ GIMT_Encode4(123223),
43913 /* 123066 */ // Label 2356: @123066
43914 /* 123066 */ GIM_Try, /*On fail goto*//*Label 2360*/ GIMT_Encode4(123125), // Rule ID 2490 //
43915 /* 123071 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16),
43916 /* 123074 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
43917 /* 123077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43918 /* 123081 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43919 /* 123085 */ // (fpextend:{ *:[f32] } HPR:{ *:[f16] }:$Sm) => (VCVTBHS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
43920 /* 123085 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43921 /* 123088 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43922 /* 123092 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43923 /* 123097 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
43924 /* 123101 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
43925 /* 123106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHS),
43926 /* 123109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43927 /* 123111 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43928 /* 123114 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43929 /* 123117 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43930 /* 123123 */ GIR_RootConstrainSelectedInstOperands,
43931 /* 123124 */ // GIR_Coverage, 2490,
43932 /* 123124 */ GIR_EraseRootFromParent_Done,
43933 /* 123125 */ // Label 2360: @123125
43934 /* 123125 */ GIM_Reject,
43935 /* 123126 */ // Label 2357: @123126
43936 /* 123126 */ GIM_Try, /*On fail goto*//*Label 2361*/ GIMT_Encode4(123163), // Rule ID 686 //
43937 /* 123131 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
43938 /* 123134 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
43939 /* 123137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43940 /* 123141 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43941 /* 123145 */ // (fpextend:{ *:[f64] } SPR:{ *:[f32] }:$Sm) => (VCVTDS:{ *:[f64] } SPR:{ *:[f32] }:$Sm)
43942 /* 123145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTDS),
43943 /* 123148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43944 /* 123150 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
43945 /* 123152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43946 /* 123155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43947 /* 123161 */ GIR_RootConstrainSelectedInstOperands,
43948 /* 123162 */ // GIR_Coverage, 686,
43949 /* 123162 */ GIR_EraseRootFromParent_Done,
43950 /* 123163 */ // Label 2361: @123163
43951 /* 123163 */ GIM_Try, /*On fail goto*//*Label 2362*/ GIMT_Encode4(123222), // Rule ID 2510 //
43952 /* 123168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
43953 /* 123171 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
43954 /* 123174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43955 /* 123178 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43956 /* 123182 */ // (fpextend:{ *:[f64] } HPR:{ *:[f16] }:$Sm) => (VCVTBHD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
43957 /* 123182 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43958 /* 123185 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43959 /* 123189 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43960 /* 123194 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
43961 /* 123198 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
43962 /* 123203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHD),
43963 /* 123206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43964 /* 123208 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43965 /* 123211 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43966 /* 123214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43967 /* 123220 */ GIR_RootConstrainSelectedInstOperands,
43968 /* 123221 */ // GIR_Coverage, 2510,
43969 /* 123221 */ GIR_EraseRootFromParent_Done,
43970 /* 123222 */ // Label 2362: @123222
43971 /* 123222 */ GIM_Reject,
43972 /* 123223 */ // Label 2358: @123223
43973 /* 123223 */ GIM_Try, /*On fail goto*//*Label 2363*/ GIMT_Encode4(123257), // Rule ID 3045 //
43974 /* 123228 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
43975 /* 123231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43976 /* 123235 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43977 /* 123239 */ // (fpextend:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src)
43978 /* 123239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f),
43979 /* 123242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43980 /* 123244 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
43981 /* 123246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43982 /* 123249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43983 /* 123255 */ GIR_RootConstrainSelectedInstOperands,
43984 /* 123256 */ // GIR_Coverage, 3045,
43985 /* 123256 */ GIR_EraseRootFromParent_Done,
43986 /* 123257 */ // Label 2363: @123257
43987 /* 123257 */ GIM_Reject,
43988 /* 123258 */ // Label 2359: @123258
43989 /* 123258 */ GIM_Reject,
43990 /* 123259 */ // Label 47: @123259
43991 /* 123259 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(10), /*)*//*default:*//*Label 2367*/ GIMT_Encode4(123538),
43992 /* 123270 */ /*GILLT_s16*//*Label 2364*/ GIMT_Encode4(123310),
43993 /* 123274 */ /*GILLT_s32*//*Label 2365*/ GIMT_Encode4(123465), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
43994 /* 123306 */ /*GILLT_v4s16*//*Label 2366*/ GIMT_Encode4(123503),
43995 /* 123310 */ // Label 2364: @123310
43996 /* 123310 */ GIM_Try, /*On fail goto*//*Label 2368*/ GIMT_Encode4(123387), // Rule ID 2494 //
43997 /* 123315 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16),
43998 /* 123318 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
43999 /* 123321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44000 /* 123325 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44001 /* 123329 */ // (fpround:{ *:[f16] } SPR:{ *:[f32] }:$Sm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBSH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), SPR:{ *:[f32] }:$Sm), HPR:{ *:[i32] })
44002 /* 123329 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44003 /* 123332 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44004 /* 123336 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44005 /* 123341 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44006 /* 123343 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44007 /* 123346 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBSH),
44008 /* 123350 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44009 /* 123355 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44010 /* 123358 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
44011 /* 123362 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44012 /* 123365 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44013 /* 123371 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44014 /* 123373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44015 /* 123376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44016 /* 123378 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44017 /* 123381 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
44018 /* 123386 */ // GIR_Coverage, 2494,
44019 /* 123386 */ GIR_EraseRootFromParent_Done,
44020 /* 123387 */ // Label 2368: @123387
44021 /* 123387 */ GIM_Try, /*On fail goto*//*Label 2369*/ GIMT_Encode4(123464), // Rule ID 2514 //
44022 /* 123392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44023 /* 123395 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44024 /* 123398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44025 /* 123402 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44026 /* 123406 */ // (fpround:{ *:[f16] } DPR:{ *:[f64] }:$Dm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBDH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), DPR:{ *:[f64] }:$Dm), HPR:{ *:[i32] })
44027 /* 123406 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44028 /* 123409 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44029 /* 123413 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44030 /* 123418 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44031 /* 123420 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44032 /* 123423 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBDH),
44033 /* 123427 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44034 /* 123432 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44035 /* 123435 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dm
44036 /* 123439 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44037 /* 123442 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44038 /* 123448 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44039 /* 123450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44040 /* 123453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44041 /* 123455 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44042 /* 123458 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
44043 /* 123463 */ // GIR_Coverage, 2514,
44044 /* 123463 */ GIR_EraseRootFromParent_Done,
44045 /* 123464 */ // Label 2369: @123464
44046 /* 123464 */ GIM_Reject,
44047 /* 123465 */ // Label 2365: @123465
44048 /* 123465 */ GIM_Try, /*On fail goto*//*Label 2370*/ GIMT_Encode4(123502), // Rule ID 688 //
44049 /* 123470 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
44050 /* 123473 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44051 /* 123476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44052 /* 123480 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44053 /* 123484 */ // (fpround:{ *:[f32] } DPR:{ *:[f64] }:$Dm) => (VCVTSD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
44054 /* 123484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTSD),
44055 /* 123487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
44056 /* 123489 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
44057 /* 123491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44058 /* 123494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44059 /* 123500 */ GIR_RootConstrainSelectedInstOperands,
44060 /* 123501 */ // GIR_Coverage, 688,
44061 /* 123501 */ GIR_EraseRootFromParent_Done,
44062 /* 123502 */ // Label 2370: @123502
44063 /* 123502 */ GIM_Reject,
44064 /* 123503 */ // Label 2366: @123503
44065 /* 123503 */ GIM_Try, /*On fail goto*//*Label 2371*/ GIMT_Encode4(123537), // Rule ID 3044 //
44066 /* 123508 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44067 /* 123511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44068 /* 123515 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44069 /* 123519 */ // (fpround:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src) => (VCVTf2h:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src)
44070 /* 123519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h),
44071 /* 123522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44072 /* 123524 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
44073 /* 123526 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44074 /* 123529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44075 /* 123535 */ GIR_RootConstrainSelectedInstOperands,
44076 /* 123536 */ // GIR_Coverage, 3044,
44077 /* 123536 */ GIR_EraseRootFromParent_Done,
44078 /* 123537 */ // Label 2371: @123537
44079 /* 123537 */ GIM_Reject,
44080 /* 123538 */ // Label 2367: @123538
44081 /* 123538 */ GIM_Reject,
44082 /* 123539 */ // Label 48: @123539
44083 /* 123539 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2379*/ GIMT_Encode4(124872),
44084 /* 123550 */ /*GILLT_s32*//*Label 2372*/ GIMT_Encode4(123598), GIMT_Encode4(0), GIMT_Encode4(0),
44085 /* 123562 */ /*GILLT_v4s1*//*Label 2373*/ GIMT_Encode4(124492),
44086 /* 123566 */ /*GILLT_v8s1*//*Label 2374*/ GIMT_Encode4(124545), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
44087 /* 123582 */ /*GILLT_v4s16*//*Label 2375*/ GIMT_Encode4(124598),
44088 /* 123586 */ /*GILLT_v8s16*//*Label 2376*/ GIMT_Encode4(124636),
44089 /* 123590 */ /*GILLT_v2s32*//*Label 2377*/ GIMT_Encode4(124735),
44090 /* 123594 */ /*GILLT_v4s32*//*Label 2378*/ GIMT_Encode4(124773),
44091 /* 123598 */ // Label 2372: @123598
44092 /* 123598 */ GIM_Try, /*On fail goto*//*Label 2380*/ GIMT_Encode4(123664), // Rule ID 2544 //
44093 /* 123603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44094 /* 123606 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44095 /* 123609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44096 /* 123613 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44097 /* 123617 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
44098 /* 123621 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44099 /* 123625 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44100 /* 123630 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44101 /* 123632 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44102 /* 123632 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44103 /* 123635 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSH),
44104 /* 123639 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44105 /* 123644 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44106 /* 123648 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44107 /* 123650 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44108 /* 123653 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44109 /* 123655 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44110 /* 123658 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44111 /* 123663 */ // GIR_Coverage, 2544,
44112 /* 123663 */ GIR_EraseRootFromParent_Done,
44113 /* 123664 */ // Label 2380: @123664
44114 /* 123664 */ GIM_Try, /*On fail goto*//*Label 2381*/ GIMT_Encode4(123730), // Rule ID 2552 //
44115 /* 123669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
44116 /* 123672 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44117 /* 123675 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44118 /* 123679 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44119 /* 123683 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
44120 /* 123687 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44121 /* 123691 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44122 /* 123696 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44123 /* 123698 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44124 /* 123698 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44125 /* 123701 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSS),
44126 /* 123705 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44127 /* 123710 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44128 /* 123714 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44129 /* 123716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44130 /* 123719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44131 /* 123721 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44132 /* 123724 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44133 /* 123729 */ // GIR_Coverage, 2552,
44134 /* 123729 */ GIR_EraseRootFromParent_Done,
44135 /* 123730 */ // Label 2381: @123730
44136 /* 123730 */ GIM_Try, /*On fail goto*//*Label 2382*/ GIMT_Encode4(123796), // Rule ID 2560 //
44137 /* 123735 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44138 /* 123738 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44139 /* 123741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44140 /* 123745 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44141 /* 123749 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
44142 /* 123753 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44143 /* 123757 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44144 /* 123762 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44145 /* 123764 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44146 /* 123764 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44147 /* 123767 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSD),
44148 /* 123771 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44149 /* 123776 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44150 /* 123780 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44151 /* 123782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44152 /* 123785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44153 /* 123787 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44154 /* 123790 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44155 /* 123795 */ // GIR_Coverage, 2560,
44156 /* 123795 */ GIR_EraseRootFromParent_Done,
44157 /* 123796 */ // Label 2382: @123796
44158 /* 123796 */ GIM_Try, /*On fail goto*//*Label 2383*/ GIMT_Encode4(123862), // Rule ID 2568 //
44159 /* 123801 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44160 /* 123804 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44161 /* 123807 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44162 /* 123811 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44163 /* 123815 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
44164 /* 123819 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44165 /* 123823 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44166 /* 123828 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44167 /* 123830 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44168 /* 123830 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44169 /* 123833 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSH),
44170 /* 123837 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44171 /* 123842 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44172 /* 123846 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44173 /* 123848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44174 /* 123851 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44175 /* 123853 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44176 /* 123856 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44177 /* 123861 */ // GIR_Coverage, 2568,
44178 /* 123861 */ GIR_EraseRootFromParent_Done,
44179 /* 123862 */ // Label 2383: @123862
44180 /* 123862 */ GIM_Try, /*On fail goto*//*Label 2384*/ GIMT_Encode4(123928), // Rule ID 2576 //
44181 /* 123867 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
44182 /* 123870 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44183 /* 123873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44184 /* 123877 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44185 /* 123881 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
44186 /* 123885 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44187 /* 123889 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44188 /* 123894 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44189 /* 123896 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44190 /* 123896 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44191 /* 123899 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSS),
44192 /* 123903 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44193 /* 123908 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44194 /* 123912 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44195 /* 123914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44196 /* 123917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44197 /* 123919 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44198 /* 123922 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44199 /* 123927 */ // GIR_Coverage, 2576,
44200 /* 123927 */ GIR_EraseRootFromParent_Done,
44201 /* 123928 */ // Label 2384: @123928
44202 /* 123928 */ GIM_Try, /*On fail goto*//*Label 2385*/ GIMT_Encode4(123994), // Rule ID 2584 //
44203 /* 123933 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44204 /* 123936 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44205 /* 123939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44206 /* 123943 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44207 /* 123947 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
44208 /* 123951 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44209 /* 123955 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44210 /* 123960 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44211 /* 123962 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44212 /* 123962 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44213 /* 123965 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSD),
44214 /* 123969 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44215 /* 123974 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44216 /* 123978 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44217 /* 123980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44218 /* 123983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44219 /* 123985 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44220 /* 123988 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44221 /* 123993 */ // GIR_Coverage, 2584,
44222 /* 123993 */ GIR_EraseRootFromParent_Done,
44223 /* 123994 */ // Label 2385: @123994
44224 /* 123994 */ GIM_Try, /*On fail goto*//*Label 2386*/ GIMT_Encode4(124060), // Rule ID 2520 //
44225 /* 123999 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44226 /* 124002 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44227 /* 124005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44228 /* 124009 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44229 /* 124013 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
44230 /* 124017 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44231 /* 124021 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44232 /* 124026 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44233 /* 124028 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44234 /* 124028 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44235 /* 124031 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASH),
44236 /* 124035 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44237 /* 124040 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44238 /* 124044 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44239 /* 124046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44240 /* 124049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44241 /* 124051 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44242 /* 124054 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44243 /* 124059 */ // GIR_Coverage, 2520,
44244 /* 124059 */ GIR_EraseRootFromParent_Done,
44245 /* 124060 */ // Label 2386: @124060
44246 /* 124060 */ GIM_Try, /*On fail goto*//*Label 2387*/ GIMT_Encode4(124126), // Rule ID 2528 //
44247 /* 124065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
44248 /* 124068 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44249 /* 124071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44250 /* 124075 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44251 /* 124079 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
44252 /* 124083 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44253 /* 124087 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44254 /* 124092 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44255 /* 124094 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44256 /* 124094 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44257 /* 124097 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASS),
44258 /* 124101 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44259 /* 124106 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44260 /* 124110 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44261 /* 124112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44262 /* 124115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44263 /* 124117 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44264 /* 124120 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44265 /* 124125 */ // GIR_Coverage, 2528,
44266 /* 124125 */ GIR_EraseRootFromParent_Done,
44267 /* 124126 */ // Label 2387: @124126
44268 /* 124126 */ GIM_Try, /*On fail goto*//*Label 2388*/ GIMT_Encode4(124192), // Rule ID 2536 //
44269 /* 124131 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44270 /* 124134 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44271 /* 124137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44272 /* 124141 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44273 /* 124145 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
44274 /* 124149 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44275 /* 124153 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44276 /* 124158 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44277 /* 124160 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44278 /* 124160 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44279 /* 124163 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASD),
44280 /* 124167 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44281 /* 124172 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44282 /* 124176 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44283 /* 124178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44284 /* 124181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44285 /* 124183 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44286 /* 124186 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44287 /* 124191 */ // GIR_Coverage, 2536,
44288 /* 124191 */ GIR_EraseRootFromParent_Done,
44289 /* 124192 */ // Label 2388: @124192
44290 /* 124192 */ GIM_Try, /*On fail goto*//*Label 2389*/ GIMT_Encode4(124252), // Rule ID 2617 //
44291 /* 124197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
44292 /* 124200 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44293 /* 124203 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44294 /* 124207 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44295 /* 124211 */ // (fp_to_sint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44296 /* 124211 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44297 /* 124214 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZD),
44298 /* 124218 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44299 /* 124223 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44300 /* 124227 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44301 /* 124230 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44302 /* 124236 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44303 /* 124238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44304 /* 124241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44305 /* 124243 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44306 /* 124246 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44307 /* 124251 */ // GIR_Coverage, 2617,
44308 /* 124251 */ GIR_EraseRootFromParent_Done,
44309 /* 124252 */ // Label 2389: @124252
44310 /* 124252 */ GIM_Try, /*On fail goto*//*Label 2390*/ GIMT_Encode4(124312), // Rule ID 2623 //
44311 /* 124257 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
44312 /* 124260 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44313 /* 124263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44314 /* 124267 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44315 /* 124271 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44316 /* 124271 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44317 /* 124274 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZS),
44318 /* 124278 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44319 /* 124283 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44320 /* 124287 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44321 /* 124290 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44322 /* 124296 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44323 /* 124298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44324 /* 124301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44325 /* 124303 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44326 /* 124306 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44327 /* 124311 */ // GIR_Coverage, 2623,
44328 /* 124311 */ GIR_EraseRootFromParent_Done,
44329 /* 124312 */ // Label 2390: @124312
44330 /* 124312 */ GIM_Try, /*On fail goto*//*Label 2391*/ GIMT_Encode4(124372), // Rule ID 2629 //
44331 /* 124317 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
44332 /* 124320 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44333 /* 124323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44334 /* 124327 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44335 /* 124331 */ // (fp_to_sint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44336 /* 124331 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44337 /* 124334 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZH),
44338 /* 124338 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44339 /* 124343 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44340 /* 124347 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44341 /* 124350 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44342 /* 124356 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44343 /* 124358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44344 /* 124361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44345 /* 124363 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44346 /* 124366 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44347 /* 124371 */ // GIR_Coverage, 2629,
44348 /* 124371 */ GIR_EraseRootFromParent_Done,
44349 /* 124372 */ // Label 2391: @124372
44350 /* 124372 */ GIM_Try, /*On fail goto*//*Label 2392*/ GIMT_Encode4(124491), // Rule ID 3085 //
44351 /* 124377 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
44352 /* 124380 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44353 /* 124383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44354 /* 124387 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44355 /* 124391 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2sd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
44356 /* 124391 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
44357 /* 124394 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44358 /* 124398 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44359 /* 124403 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44360 /* 124405 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
44361 /* 124408 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
44362 /* 124412 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44363 /* 124417 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
44364 /* 124420 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
44365 /* 124424 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
44366 /* 124427 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44367 /* 124432 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44368 /* 124437 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
44369 /* 124442 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
44370 /* 124445 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd),
44371 /* 124449 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44372 /* 124454 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44373 /* 124457 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44374 /* 124460 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44375 /* 124466 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44376 /* 124468 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44377 /* 124471 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44378 /* 124473 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
44379 /* 124480 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
44380 /* 124485 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44381 /* 124490 */ // GIR_Coverage, 3085,
44382 /* 124490 */ GIR_EraseRootFromParent_Done,
44383 /* 124491 */ // Label 2392: @124491
44384 /* 124491 */ GIM_Reject,
44385 /* 124492 */ // Label 2373: @124492
44386 /* 124492 */ GIM_Try, /*On fail goto*//*Label 2393*/ GIMT_Encode4(124544), // Rule ID 5620 //
44387 /* 124497 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44388 /* 124500 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44389 /* 124503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
44390 /* 124507 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44391 /* 124511 */ // (fp_to_sint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
44392 /* 124511 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r),
44393 /* 124514 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
44394 /* 124516 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
44395 /* 124518 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44396 /* 124524 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44397 /* 124527 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44398 /* 124530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44399 /* 124536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44400 /* 124542 */ GIR_RootConstrainSelectedInstOperands,
44401 /* 124543 */ // GIR_Coverage, 5620,
44402 /* 124543 */ GIR_EraseRootFromParent_Done,
44403 /* 124544 */ // Label 2393: @124544
44404 /* 124544 */ GIM_Reject,
44405 /* 124545 */ // Label 2374: @124545
44406 /* 124545 */ GIM_Try, /*On fail goto*//*Label 2394*/ GIMT_Encode4(124597), // Rule ID 5621 //
44407 /* 124550 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44408 /* 124553 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
44409 /* 124556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
44410 /* 124560 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44411 /* 124564 */ // (fp_to_sint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
44412 /* 124564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r),
44413 /* 124567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
44414 /* 124569 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
44415 /* 124571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44416 /* 124577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44417 /* 124580 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44418 /* 124583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44419 /* 124589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44420 /* 124595 */ GIR_RootConstrainSelectedInstOperands,
44421 /* 124596 */ // GIR_Coverage, 5621,
44422 /* 124596 */ GIR_EraseRootFromParent_Done,
44423 /* 124597 */ // Label 2394: @124597
44424 /* 124597 */ GIM_Reject,
44425 /* 124598 */ // Label 2375: @124598
44426 /* 124598 */ GIM_Try, /*On fail goto*//*Label 2395*/ GIMT_Encode4(124635), // Rule ID 1774 //
44427 /* 124603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44428 /* 124606 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
44429 /* 124609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44430 /* 124613 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44431 /* 124617 */ // (fp_to_sint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2sd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
44432 /* 124617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sd),
44433 /* 124620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44434 /* 124622 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44435 /* 124624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44436 /* 124627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44437 /* 124633 */ GIR_RootConstrainSelectedInstOperands,
44438 /* 124634 */ // GIR_Coverage, 1774,
44439 /* 124634 */ GIR_EraseRootFromParent_Done,
44440 /* 124635 */ // Label 2395: @124635
44441 /* 124635 */ GIM_Reject,
44442 /* 124636 */ // Label 2376: @124636
44443 /* 124636 */ GIM_Try, /*On fail goto*//*Label 2396*/ GIMT_Encode4(124734),
44444 /* 124641 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
44445 /* 124644 */ GIM_Try, /*On fail goto*//*Label 2397*/ GIMT_Encode4(124678), // Rule ID 1778 //
44446 /* 124649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44447 /* 124652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44448 /* 124656 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44449 /* 124660 */ // (fp_to_sint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2sq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
44450 /* 124660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sq),
44451 /* 124663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44452 /* 124665 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44453 /* 124667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44454 /* 124670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44455 /* 124676 */ GIR_RootConstrainSelectedInstOperands,
44456 /* 124677 */ // GIR_Coverage, 1778,
44457 /* 124677 */ GIR_EraseRootFromParent_Done,
44458 /* 124678 */ // Label 2397: @124678
44459 /* 124678 */ GIM_Try, /*On fail goto*//*Label 2398*/ GIMT_Encode4(124733), // Rule ID 4521 //
44460 /* 124683 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44461 /* 124686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44462 /* 124690 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44463 /* 124694 */ // (fp_to_sint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
44464 /* 124694 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44465 /* 124697 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44466 /* 124701 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44467 /* 124706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z),
44468 /* 124709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44469 /* 124711 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
44470 /* 124713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44471 /* 124716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44472 /* 124722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44473 /* 124728 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44474 /* 124731 */ GIR_RootConstrainSelectedInstOperands,
44475 /* 124732 */ // GIR_Coverage, 4521,
44476 /* 124732 */ GIR_EraseRootFromParent_Done,
44477 /* 124733 */ // Label 2398: @124733
44478 /* 124733 */ GIM_Reject,
44479 /* 124734 */ // Label 2396: @124734
44480 /* 124734 */ GIM_Reject,
44481 /* 124735 */ // Label 2377: @124735
44482 /* 124735 */ GIM_Try, /*On fail goto*//*Label 2399*/ GIMT_Encode4(124772), // Rule ID 1766 //
44483 /* 124740 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44484 /* 124743 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
44485 /* 124746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44486 /* 124750 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44487 /* 124754 */ // (fp_to_sint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2sd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
44488 /* 124754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd),
44489 /* 124757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44490 /* 124759 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44491 /* 124761 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44492 /* 124764 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44493 /* 124770 */ GIR_RootConstrainSelectedInstOperands,
44494 /* 124771 */ // GIR_Coverage, 1766,
44495 /* 124771 */ GIR_EraseRootFromParent_Done,
44496 /* 124772 */ // Label 2399: @124772
44497 /* 124772 */ GIM_Reject,
44498 /* 124773 */ // Label 2378: @124773
44499 /* 124773 */ GIM_Try, /*On fail goto*//*Label 2400*/ GIMT_Encode4(124871),
44500 /* 124778 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44501 /* 124781 */ GIM_Try, /*On fail goto*//*Label 2401*/ GIMT_Encode4(124815), // Rule ID 1770 //
44502 /* 124786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44503 /* 124789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44504 /* 124793 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44505 /* 124797 */ // (fp_to_sint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2sq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
44506 /* 124797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sq),
44507 /* 124800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44508 /* 124802 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44509 /* 124804 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44510 /* 124807 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44511 /* 124813 */ GIR_RootConstrainSelectedInstOperands,
44512 /* 124814 */ // GIR_Coverage, 1770,
44513 /* 124814 */ GIR_EraseRootFromParent_Done,
44514 /* 124815 */ // Label 2401: @124815
44515 /* 124815 */ GIM_Try, /*On fail goto*//*Label 2402*/ GIMT_Encode4(124870), // Rule ID 4527 //
44516 /* 124820 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44517 /* 124823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44518 /* 124827 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44519 /* 124831 */ // (fp_to_sint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
44520 /* 124831 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44521 /* 124834 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44522 /* 124838 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44523 /* 124843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z),
44524 /* 124846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44525 /* 124848 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
44526 /* 124850 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44527 /* 124853 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44528 /* 124859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44529 /* 124865 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44530 /* 124868 */ GIR_RootConstrainSelectedInstOperands,
44531 /* 124869 */ // GIR_Coverage, 4527,
44532 /* 124869 */ GIR_EraseRootFromParent_Done,
44533 /* 124870 */ // Label 2402: @124870
44534 /* 124870 */ GIM_Reject,
44535 /* 124871 */ // Label 2400: @124871
44536 /* 124871 */ GIM_Reject,
44537 /* 124872 */ // Label 2379: @124872
44538 /* 124872 */ GIM_Reject,
44539 /* 124873 */ // Label 49: @124873
44540 /* 124873 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2410*/ GIMT_Encode4(126206),
44541 /* 124884 */ /*GILLT_s32*//*Label 2403*/ GIMT_Encode4(124932), GIMT_Encode4(0), GIMT_Encode4(0),
44542 /* 124896 */ /*GILLT_v4s1*//*Label 2404*/ GIMT_Encode4(125826),
44543 /* 124900 */ /*GILLT_v8s1*//*Label 2405*/ GIMT_Encode4(125879), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
44544 /* 124916 */ /*GILLT_v4s16*//*Label 2406*/ GIMT_Encode4(125932),
44545 /* 124920 */ /*GILLT_v8s16*//*Label 2407*/ GIMT_Encode4(125970),
44546 /* 124924 */ /*GILLT_v2s32*//*Label 2408*/ GIMT_Encode4(126069),
44547 /* 124928 */ /*GILLT_v4s32*//*Label 2409*/ GIMT_Encode4(126107),
44548 /* 124932 */ // Label 2403: @124932
44549 /* 124932 */ GIM_Try, /*On fail goto*//*Label 2411*/ GIMT_Encode4(124998), // Rule ID 2548 //
44550 /* 124937 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44551 /* 124940 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44552 /* 124943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44553 /* 124947 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44554 /* 124951 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
44555 /* 124955 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44556 /* 124959 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44557 /* 124964 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44558 /* 124966 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44559 /* 124966 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44560 /* 124969 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUH),
44561 /* 124973 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44562 /* 124978 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44563 /* 124982 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44564 /* 124984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44565 /* 124987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44566 /* 124989 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44567 /* 124992 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44568 /* 124997 */ // GIR_Coverage, 2548,
44569 /* 124997 */ GIR_EraseRootFromParent_Done,
44570 /* 124998 */ // Label 2411: @124998
44571 /* 124998 */ GIM_Try, /*On fail goto*//*Label 2412*/ GIMT_Encode4(125064), // Rule ID 2556 //
44572 /* 125003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
44573 /* 125006 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44574 /* 125009 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44575 /* 125013 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44576 /* 125017 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
44577 /* 125021 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44578 /* 125025 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44579 /* 125030 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44580 /* 125032 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44581 /* 125032 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44582 /* 125035 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUS),
44583 /* 125039 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44584 /* 125044 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44585 /* 125048 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44586 /* 125050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44587 /* 125053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44588 /* 125055 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44589 /* 125058 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44590 /* 125063 */ // GIR_Coverage, 2556,
44591 /* 125063 */ GIR_EraseRootFromParent_Done,
44592 /* 125064 */ // Label 2412: @125064
44593 /* 125064 */ GIM_Try, /*On fail goto*//*Label 2413*/ GIMT_Encode4(125130), // Rule ID 2564 //
44594 /* 125069 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44595 /* 125072 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44596 /* 125075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44597 /* 125079 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44598 /* 125083 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
44599 /* 125087 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44600 /* 125091 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44601 /* 125096 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44602 /* 125098 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44603 /* 125098 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44604 /* 125101 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUD),
44605 /* 125105 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44606 /* 125110 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44607 /* 125114 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44608 /* 125116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44609 /* 125119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44610 /* 125121 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44611 /* 125124 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44612 /* 125129 */ // GIR_Coverage, 2564,
44613 /* 125129 */ GIR_EraseRootFromParent_Done,
44614 /* 125130 */ // Label 2413: @125130
44615 /* 125130 */ GIM_Try, /*On fail goto*//*Label 2414*/ GIMT_Encode4(125196), // Rule ID 2572 //
44616 /* 125135 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44617 /* 125138 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44618 /* 125141 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44619 /* 125145 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44620 /* 125149 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
44621 /* 125153 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44622 /* 125157 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44623 /* 125162 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44624 /* 125164 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44625 /* 125164 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44626 /* 125167 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUH),
44627 /* 125171 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44628 /* 125176 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44629 /* 125180 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44630 /* 125182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44631 /* 125185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44632 /* 125187 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44633 /* 125190 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44634 /* 125195 */ // GIR_Coverage, 2572,
44635 /* 125195 */ GIR_EraseRootFromParent_Done,
44636 /* 125196 */ // Label 2414: @125196
44637 /* 125196 */ GIM_Try, /*On fail goto*//*Label 2415*/ GIMT_Encode4(125262), // Rule ID 2580 //
44638 /* 125201 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
44639 /* 125204 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44640 /* 125207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44641 /* 125211 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44642 /* 125215 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
44643 /* 125219 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44644 /* 125223 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44645 /* 125228 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44646 /* 125230 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44647 /* 125230 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44648 /* 125233 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUS),
44649 /* 125237 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44650 /* 125242 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44651 /* 125246 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44652 /* 125248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44653 /* 125251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44654 /* 125253 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44655 /* 125256 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44656 /* 125261 */ // GIR_Coverage, 2580,
44657 /* 125261 */ GIR_EraseRootFromParent_Done,
44658 /* 125262 */ // Label 2415: @125262
44659 /* 125262 */ GIM_Try, /*On fail goto*//*Label 2416*/ GIMT_Encode4(125328), // Rule ID 2588 //
44660 /* 125267 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44661 /* 125270 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44662 /* 125273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44663 /* 125277 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44664 /* 125281 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
44665 /* 125285 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44666 /* 125289 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44667 /* 125294 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44668 /* 125296 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44669 /* 125296 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44670 /* 125299 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUD),
44671 /* 125303 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44672 /* 125308 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44673 /* 125312 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44674 /* 125314 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44675 /* 125317 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44676 /* 125319 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44677 /* 125322 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44678 /* 125327 */ // GIR_Coverage, 2588,
44679 /* 125327 */ GIR_EraseRootFromParent_Done,
44680 /* 125328 */ // Label 2416: @125328
44681 /* 125328 */ GIM_Try, /*On fail goto*//*Label 2417*/ GIMT_Encode4(125394), // Rule ID 2524 //
44682 /* 125333 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44683 /* 125336 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44684 /* 125339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44685 /* 125343 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44686 /* 125347 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
44687 /* 125351 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44688 /* 125355 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44689 /* 125360 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44690 /* 125362 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44691 /* 125362 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44692 /* 125365 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUH),
44693 /* 125369 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44694 /* 125374 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44695 /* 125378 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44696 /* 125380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44697 /* 125383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44698 /* 125385 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44699 /* 125388 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44700 /* 125393 */ // GIR_Coverage, 2524,
44701 /* 125393 */ GIR_EraseRootFromParent_Done,
44702 /* 125394 */ // Label 2417: @125394
44703 /* 125394 */ GIM_Try, /*On fail goto*//*Label 2418*/ GIMT_Encode4(125460), // Rule ID 2532 //
44704 /* 125399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
44705 /* 125402 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44706 /* 125405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44707 /* 125409 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44708 /* 125413 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
44709 /* 125417 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44710 /* 125421 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44711 /* 125426 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44712 /* 125428 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44713 /* 125428 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44714 /* 125431 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUS),
44715 /* 125435 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44716 /* 125440 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44717 /* 125444 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44718 /* 125446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44719 /* 125449 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44720 /* 125451 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44721 /* 125454 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44722 /* 125459 */ // GIR_Coverage, 2532,
44723 /* 125459 */ GIR_EraseRootFromParent_Done,
44724 /* 125460 */ // Label 2418: @125460
44725 /* 125460 */ GIM_Try, /*On fail goto*//*Label 2419*/ GIMT_Encode4(125526), // Rule ID 2540 //
44726 /* 125465 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44727 /* 125468 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44728 /* 125471 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44729 /* 125475 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44730 /* 125479 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
44731 /* 125483 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44732 /* 125487 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44733 /* 125492 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44734 /* 125494 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44735 /* 125494 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44736 /* 125497 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUD),
44737 /* 125501 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44738 /* 125506 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44739 /* 125510 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44740 /* 125512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44741 /* 125515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44742 /* 125517 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44743 /* 125520 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44744 /* 125525 */ // GIR_Coverage, 2540,
44745 /* 125525 */ GIR_EraseRootFromParent_Done,
44746 /* 125526 */ // Label 2419: @125526
44747 /* 125526 */ GIM_Try, /*On fail goto*//*Label 2420*/ GIMT_Encode4(125586), // Rule ID 2632 //
44748 /* 125531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
44749 /* 125534 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44750 /* 125537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44751 /* 125541 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44752 /* 125545 */ // (fp_to_uint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44753 /* 125545 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44754 /* 125548 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZD),
44755 /* 125552 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44756 /* 125557 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44757 /* 125561 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44758 /* 125564 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44759 /* 125570 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44760 /* 125572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44761 /* 125575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44762 /* 125577 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44763 /* 125580 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44764 /* 125585 */ // GIR_Coverage, 2632,
44765 /* 125585 */ GIR_EraseRootFromParent_Done,
44766 /* 125586 */ // Label 2420: @125586
44767 /* 125586 */ GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(125646), // Rule ID 2638 //
44768 /* 125591 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
44769 /* 125594 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44770 /* 125597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44771 /* 125601 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44772 /* 125605 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44773 /* 125605 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44774 /* 125608 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZS),
44775 /* 125612 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44776 /* 125617 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44777 /* 125621 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44778 /* 125624 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44779 /* 125630 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44780 /* 125632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44781 /* 125635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44782 /* 125637 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44783 /* 125640 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44784 /* 125645 */ // GIR_Coverage, 2638,
44785 /* 125645 */ GIR_EraseRootFromParent_Done,
44786 /* 125646 */ // Label 2421: @125646
44787 /* 125646 */ GIM_Try, /*On fail goto*//*Label 2422*/ GIMT_Encode4(125706), // Rule ID 2644 //
44788 /* 125651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
44789 /* 125654 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44790 /* 125657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44791 /* 125661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44792 /* 125665 */ // (fp_to_uint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44793 /* 125665 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44794 /* 125668 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZH),
44795 /* 125672 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44796 /* 125677 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44797 /* 125681 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44798 /* 125684 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44799 /* 125690 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44800 /* 125692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44801 /* 125695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44802 /* 125697 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44803 /* 125700 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44804 /* 125705 */ // GIR_Coverage, 2644,
44805 /* 125705 */ GIR_EraseRootFromParent_Done,
44806 /* 125706 */ // Label 2422: @125706
44807 /* 125706 */ GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(125825), // Rule ID 3086 //
44808 /* 125711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
44809 /* 125714 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44810 /* 125717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44811 /* 125721 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44812 /* 125725 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2ud:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
44813 /* 125725 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
44814 /* 125728 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44815 /* 125732 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44816 /* 125737 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44817 /* 125739 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
44818 /* 125742 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
44819 /* 125746 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44820 /* 125751 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
44821 /* 125754 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
44822 /* 125758 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
44823 /* 125761 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44824 /* 125766 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44825 /* 125771 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
44826 /* 125776 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
44827 /* 125779 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud),
44828 /* 125783 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44829 /* 125788 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44830 /* 125791 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44831 /* 125794 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44832 /* 125800 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44833 /* 125802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44834 /* 125805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44835 /* 125807 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
44836 /* 125814 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
44837 /* 125819 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44838 /* 125824 */ // GIR_Coverage, 3086,
44839 /* 125824 */ GIR_EraseRootFromParent_Done,
44840 /* 125825 */ // Label 2423: @125825
44841 /* 125825 */ GIM_Reject,
44842 /* 125826 */ // Label 2404: @125826
44843 /* 125826 */ GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(125878), // Rule ID 5618 //
44844 /* 125831 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44845 /* 125834 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44846 /* 125837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
44847 /* 125841 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44848 /* 125845 */ // (fp_to_uint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
44849 /* 125845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r),
44850 /* 125848 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
44851 /* 125850 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
44852 /* 125852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44853 /* 125858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44854 /* 125861 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44855 /* 125864 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44856 /* 125870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44857 /* 125876 */ GIR_RootConstrainSelectedInstOperands,
44858 /* 125877 */ // GIR_Coverage, 5618,
44859 /* 125877 */ GIR_EraseRootFromParent_Done,
44860 /* 125878 */ // Label 2424: @125878
44861 /* 125878 */ GIM_Reject,
44862 /* 125879 */ // Label 2405: @125879
44863 /* 125879 */ GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(125931), // Rule ID 5619 //
44864 /* 125884 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44865 /* 125887 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
44866 /* 125890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
44867 /* 125894 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44868 /* 125898 */ // (fp_to_uint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
44869 /* 125898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r),
44870 /* 125901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
44871 /* 125903 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
44872 /* 125905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44873 /* 125911 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44874 /* 125914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44875 /* 125917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44876 /* 125923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44877 /* 125929 */ GIR_RootConstrainSelectedInstOperands,
44878 /* 125930 */ // GIR_Coverage, 5619,
44879 /* 125930 */ GIR_EraseRootFromParent_Done,
44880 /* 125931 */ // Label 2425: @125931
44881 /* 125931 */ GIM_Reject,
44882 /* 125932 */ // Label 2406: @125932
44883 /* 125932 */ GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(125969), // Rule ID 1775 //
44884 /* 125937 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44885 /* 125940 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
44886 /* 125943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44887 /* 125947 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44888 /* 125951 */ // (fp_to_uint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2ud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
44889 /* 125951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2ud),
44890 /* 125954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44891 /* 125956 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44892 /* 125958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44893 /* 125961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44894 /* 125967 */ GIR_RootConstrainSelectedInstOperands,
44895 /* 125968 */ // GIR_Coverage, 1775,
44896 /* 125968 */ GIR_EraseRootFromParent_Done,
44897 /* 125969 */ // Label 2426: @125969
44898 /* 125969 */ GIM_Reject,
44899 /* 125970 */ // Label 2407: @125970
44900 /* 125970 */ GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(126068),
44901 /* 125975 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
44902 /* 125978 */ GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(126012), // Rule ID 1779 //
44903 /* 125983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44904 /* 125986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44905 /* 125990 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44906 /* 125994 */ // (fp_to_uint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2uq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
44907 /* 125994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2uq),
44908 /* 125997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44909 /* 125999 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44910 /* 126001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44911 /* 126004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44912 /* 126010 */ GIR_RootConstrainSelectedInstOperands,
44913 /* 126011 */ // GIR_Coverage, 1779,
44914 /* 126011 */ GIR_EraseRootFromParent_Done,
44915 /* 126012 */ // Label 2428: @126012
44916 /* 126012 */ GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(126067), // Rule ID 4524 //
44917 /* 126017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44918 /* 126020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44919 /* 126024 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44920 /* 126028 */ // (fp_to_uint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
44921 /* 126028 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44922 /* 126031 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44923 /* 126035 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44924 /* 126040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z),
44925 /* 126043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44926 /* 126045 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
44927 /* 126047 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44928 /* 126050 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44929 /* 126056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44930 /* 126062 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44931 /* 126065 */ GIR_RootConstrainSelectedInstOperands,
44932 /* 126066 */ // GIR_Coverage, 4524,
44933 /* 126066 */ GIR_EraseRootFromParent_Done,
44934 /* 126067 */ // Label 2429: @126067
44935 /* 126067 */ GIM_Reject,
44936 /* 126068 */ // Label 2427: @126068
44937 /* 126068 */ GIM_Reject,
44938 /* 126069 */ // Label 2408: @126069
44939 /* 126069 */ GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(126106), // Rule ID 1767 //
44940 /* 126074 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44941 /* 126077 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
44942 /* 126080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44943 /* 126084 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44944 /* 126088 */ // (fp_to_uint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2ud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
44945 /* 126088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud),
44946 /* 126091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44947 /* 126093 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44948 /* 126095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44949 /* 126098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44950 /* 126104 */ GIR_RootConstrainSelectedInstOperands,
44951 /* 126105 */ // GIR_Coverage, 1767,
44952 /* 126105 */ GIR_EraseRootFromParent_Done,
44953 /* 126106 */ // Label 2430: @126106
44954 /* 126106 */ GIM_Reject,
44955 /* 126107 */ // Label 2409: @126107
44956 /* 126107 */ GIM_Try, /*On fail goto*//*Label 2431*/ GIMT_Encode4(126205),
44957 /* 126112 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44958 /* 126115 */ GIM_Try, /*On fail goto*//*Label 2432*/ GIMT_Encode4(126149), // Rule ID 1771 //
44959 /* 126120 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44960 /* 126123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44961 /* 126127 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44962 /* 126131 */ // (fp_to_uint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2uq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
44963 /* 126131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2uq),
44964 /* 126134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44965 /* 126136 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44966 /* 126138 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44967 /* 126141 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44968 /* 126147 */ GIR_RootConstrainSelectedInstOperands,
44969 /* 126148 */ // GIR_Coverage, 1771,
44970 /* 126148 */ GIR_EraseRootFromParent_Done,
44971 /* 126149 */ // Label 2432: @126149
44972 /* 126149 */ GIM_Try, /*On fail goto*//*Label 2433*/ GIMT_Encode4(126204), // Rule ID 4530 //
44973 /* 126154 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44974 /* 126157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44975 /* 126161 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44976 /* 126165 */ // (fp_to_uint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
44977 /* 126165 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44978 /* 126168 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44979 /* 126172 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44980 /* 126177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z),
44981 /* 126180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44982 /* 126182 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
44983 /* 126184 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44984 /* 126187 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44985 /* 126193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44986 /* 126199 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44987 /* 126202 */ GIR_RootConstrainSelectedInstOperands,
44988 /* 126203 */ // GIR_Coverage, 4530,
44989 /* 126203 */ GIR_EraseRootFromParent_Done,
44990 /* 126204 */ // Label 2433: @126204
44991 /* 126204 */ GIM_Reject,
44992 /* 126205 */ // Label 2431: @126205
44993 /* 126205 */ GIM_Reject,
44994 /* 126206 */ // Label 2410: @126206
44995 /* 126206 */ GIM_Reject,
44996 /* 126207 */ // Label 50: @126207
44997 /* 126207 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2441*/ GIMT_Encode4(126858),
44998 /* 126218 */ /*GILLT_s16*//*Label 2434*/ GIMT_Encode4(126270),
44999 /* 126222 */ /*GILLT_s32*//*Label 2435*/ GIMT_Encode4(126330),
45000 /* 126226 */ /*GILLT_s64*//*Label 2436*/ GIMT_Encode4(126524), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45001 /* 126254 */ /*GILLT_v4s16*//*Label 2437*/ GIMT_Encode4(126584),
45002 /* 126258 */ /*GILLT_v8s16*//*Label 2438*/ GIMT_Encode4(126622),
45003 /* 126262 */ /*GILLT_v2s32*//*Label 2439*/ GIMT_Encode4(126721),
45004 /* 126266 */ /*GILLT_v4s32*//*Label 2440*/ GIMT_Encode4(126759),
45005 /* 126270 */ // Label 2434: @126270
45006 /* 126270 */ GIM_Try, /*On fail goto*//*Label 2442*/ GIMT_Encode4(126329), // Rule ID 2605 //
45007 /* 126275 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
45008 /* 126278 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45009 /* 126281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45010 /* 126285 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45011 /* 126289 */ // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VSITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
45012 /* 126289 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45013 /* 126292 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45014 /* 126296 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45015 /* 126301 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
45016 /* 126305 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45017 /* 126310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOH),
45018 /* 126313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
45019 /* 126315 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45020 /* 126318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45021 /* 126321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45022 /* 126327 */ GIR_RootConstrainSelectedInstOperands,
45023 /* 126328 */ // GIR_Coverage, 2605,
45024 /* 126328 */ GIR_EraseRootFromParent_Done,
45025 /* 126329 */ // Label 2442: @126329
45026 /* 126329 */ GIM_Reject,
45027 /* 126330 */ // Label 2435: @126330
45028 /* 126330 */ GIM_Try, /*On fail goto*//*Label 2443*/ GIMT_Encode4(126523),
45029 /* 126335 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45030 /* 126338 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45031 /* 126342 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45032 /* 126346 */ GIM_Try, /*On fail goto*//*Label 2444*/ GIMT_Encode4(126394), // Rule ID 2601 //
45033 /* 126351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
45034 /* 126354 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VSITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
45035 /* 126354 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45036 /* 126357 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45037 /* 126361 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45038 /* 126366 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
45039 /* 126370 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45040 /* 126375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOS),
45041 /* 126378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
45042 /* 126380 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45043 /* 126383 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45044 /* 126386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45045 /* 126392 */ GIR_RootConstrainSelectedInstOperands,
45046 /* 126393 */ // GIR_Coverage, 2601,
45047 /* 126393 */ GIR_EraseRootFromParent_Done,
45048 /* 126394 */ // Label 2444: @126394
45049 /* 126394 */ GIM_Try, /*On fail goto*//*Label 2445*/ GIMT_Encode4(126522), // Rule ID 3087 //
45050 /* 126399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
45051 /* 126402 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTs2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
45052 /* 126402 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
45053 /* 126405 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45054 /* 126409 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45055 /* 126414 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a
45056 /* 126418 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45057 /* 126423 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
45058 /* 126426 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45059 /* 126430 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45060 /* 126435 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45061 /* 126437 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
45062 /* 126440 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45063 /* 126444 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45064 /* 126449 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
45065 /* 126452 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
45066 /* 126455 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
45067 /* 126458 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45068 /* 126463 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45069 /* 126468 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
45070 /* 126473 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
45071 /* 126476 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd),
45072 /* 126480 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45073 /* 126485 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45074 /* 126488 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
45075 /* 126491 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45076 /* 126497 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45077 /* 126499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45078 /* 126502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45079 /* 126504 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
45080 /* 126511 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45081 /* 126516 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45082 /* 126521 */ // GIR_Coverage, 3087,
45083 /* 126521 */ GIR_EraseRootFromParent_Done,
45084 /* 126522 */ // Label 2445: @126522
45085 /* 126522 */ GIM_Reject,
45086 /* 126523 */ // Label 2443: @126523
45087 /* 126523 */ GIM_Reject,
45088 /* 126524 */ // Label 2436: @126524
45089 /* 126524 */ GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(126583), // Rule ID 2597 //
45090 /* 126529 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
45091 /* 126532 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45092 /* 126535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45093 /* 126539 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45094 /* 126543 */ // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VSITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
45095 /* 126543 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45096 /* 126546 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45097 /* 126550 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45098 /* 126555 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
45099 /* 126559 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45100 /* 126564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOD),
45101 /* 126567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
45102 /* 126569 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45103 /* 126572 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45104 /* 126575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45105 /* 126581 */ GIR_RootConstrainSelectedInstOperands,
45106 /* 126582 */ // GIR_Coverage, 2597,
45107 /* 126582 */ GIR_EraseRootFromParent_Done,
45108 /* 126583 */ // Label 2446: @126583
45109 /* 126583 */ GIM_Reject,
45110 /* 126584 */ // Label 2437: @126584
45111 /* 126584 */ GIM_Try, /*On fail goto*//*Label 2447*/ GIMT_Encode4(126621), // Rule ID 1776 //
45112 /* 126589 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45113 /* 126592 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45114 /* 126595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45115 /* 126599 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45116 /* 126603 */ // (sint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
45117 /* 126603 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hd),
45118 /* 126606 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45119 /* 126608 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45120 /* 126610 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45121 /* 126613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45122 /* 126619 */ GIR_RootConstrainSelectedInstOperands,
45123 /* 126620 */ // GIR_Coverage, 1776,
45124 /* 126620 */ GIR_EraseRootFromParent_Done,
45125 /* 126621 */ // Label 2447: @126621
45126 /* 126621 */ GIM_Reject,
45127 /* 126622 */ // Label 2438: @126622
45128 /* 126622 */ GIM_Try, /*On fail goto*//*Label 2448*/ GIMT_Encode4(126720),
45129 /* 126627 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45130 /* 126630 */ GIM_Try, /*On fail goto*//*Label 2449*/ GIMT_Encode4(126664), // Rule ID 1780 //
45131 /* 126635 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45132 /* 126638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45133 /* 126642 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45134 /* 126646 */ // (sint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
45135 /* 126646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hq),
45136 /* 126649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45137 /* 126651 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45138 /* 126653 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45139 /* 126656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45140 /* 126662 */ GIR_RootConstrainSelectedInstOperands,
45141 /* 126663 */ // GIR_Coverage, 1780,
45142 /* 126663 */ GIR_EraseRootFromParent_Done,
45143 /* 126664 */ // Label 2449: @126664
45144 /* 126664 */ GIM_Try, /*On fail goto*//*Label 2450*/ GIMT_Encode4(126719), // Rule ID 4533 //
45145 /* 126669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45146 /* 126672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45147 /* 126676 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45148 /* 126680 */ // (sint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
45149 /* 126680 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45150 /* 126683 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45151 /* 126687 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45152 /* 126692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n),
45153 /* 126695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45154 /* 126697 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
45155 /* 126699 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45156 /* 126702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45157 /* 126708 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45158 /* 126714 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45159 /* 126717 */ GIR_RootConstrainSelectedInstOperands,
45160 /* 126718 */ // GIR_Coverage, 4533,
45161 /* 126718 */ GIR_EraseRootFromParent_Done,
45162 /* 126719 */ // Label 2450: @126719
45163 /* 126719 */ GIM_Reject,
45164 /* 126720 */ // Label 2448: @126720
45165 /* 126720 */ GIM_Reject,
45166 /* 126721 */ // Label 2439: @126721
45167 /* 126721 */ GIM_Try, /*On fail goto*//*Label 2451*/ GIMT_Encode4(126758), // Rule ID 1768 //
45168 /* 126726 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45169 /* 126729 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45170 /* 126732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45171 /* 126736 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45172 /* 126740 */ // (sint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
45173 /* 126740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd),
45174 /* 126743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45175 /* 126745 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45176 /* 126747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45177 /* 126750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45178 /* 126756 */ GIR_RootConstrainSelectedInstOperands,
45179 /* 126757 */ // GIR_Coverage, 1768,
45180 /* 126757 */ GIR_EraseRootFromParent_Done,
45181 /* 126758 */ // Label 2451: @126758
45182 /* 126758 */ GIM_Reject,
45183 /* 126759 */ // Label 2440: @126759
45184 /* 126759 */ GIM_Try, /*On fail goto*//*Label 2452*/ GIMT_Encode4(126857),
45185 /* 126764 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45186 /* 126767 */ GIM_Try, /*On fail goto*//*Label 2453*/ GIMT_Encode4(126801), // Rule ID 1772 //
45187 /* 126772 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45188 /* 126775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45189 /* 126779 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45190 /* 126783 */ // (sint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
45191 /* 126783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fq),
45192 /* 126786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45193 /* 126788 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45194 /* 126790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45195 /* 126793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45196 /* 126799 */ GIR_RootConstrainSelectedInstOperands,
45197 /* 126800 */ // GIR_Coverage, 1772,
45198 /* 126800 */ GIR_EraseRootFromParent_Done,
45199 /* 126801 */ // Label 2453: @126801
45200 /* 126801 */ GIM_Try, /*On fail goto*//*Label 2454*/ GIMT_Encode4(126856), // Rule ID 4539 //
45201 /* 126806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45202 /* 126809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45203 /* 126813 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45204 /* 126817 */ // (sint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
45205 /* 126817 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45206 /* 126820 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45207 /* 126824 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45208 /* 126829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n),
45209 /* 126832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45210 /* 126834 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
45211 /* 126836 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45212 /* 126839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45213 /* 126845 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45214 /* 126851 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45215 /* 126854 */ GIR_RootConstrainSelectedInstOperands,
45216 /* 126855 */ // GIR_Coverage, 4539,
45217 /* 126855 */ GIR_EraseRootFromParent_Done,
45218 /* 126856 */ // Label 2454: @126856
45219 /* 126856 */ GIM_Reject,
45220 /* 126857 */ // Label 2452: @126857
45221 /* 126857 */ GIM_Reject,
45222 /* 126858 */ // Label 2441: @126858
45223 /* 126858 */ GIM_Reject,
45224 /* 126859 */ // Label 51: @126859
45225 /* 126859 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2462*/ GIMT_Encode4(127510),
45226 /* 126870 */ /*GILLT_s16*//*Label 2455*/ GIMT_Encode4(126922),
45227 /* 126874 */ /*GILLT_s32*//*Label 2456*/ GIMT_Encode4(126982),
45228 /* 126878 */ /*GILLT_s64*//*Label 2457*/ GIMT_Encode4(127176), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45229 /* 126906 */ /*GILLT_v4s16*//*Label 2458*/ GIMT_Encode4(127236),
45230 /* 126910 */ /*GILLT_v8s16*//*Label 2459*/ GIMT_Encode4(127274),
45231 /* 126914 */ /*GILLT_v2s32*//*Label 2460*/ GIMT_Encode4(127373),
45232 /* 126918 */ /*GILLT_v4s32*//*Label 2461*/ GIMT_Encode4(127411),
45233 /* 126922 */ // Label 2455: @126922
45234 /* 126922 */ GIM_Try, /*On fail goto*//*Label 2463*/ GIMT_Encode4(126981), // Rule ID 2615 //
45235 /* 126927 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
45236 /* 126930 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45237 /* 126933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45238 /* 126937 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45239 /* 126941 */ // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VUITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
45240 /* 126941 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45241 /* 126944 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45242 /* 126948 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45243 /* 126953 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
45244 /* 126957 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45245 /* 126962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOH),
45246 /* 126965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
45247 /* 126967 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45248 /* 126970 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45249 /* 126973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45250 /* 126979 */ GIR_RootConstrainSelectedInstOperands,
45251 /* 126980 */ // GIR_Coverage, 2615,
45252 /* 126980 */ GIR_EraseRootFromParent_Done,
45253 /* 126981 */ // Label 2463: @126981
45254 /* 126981 */ GIM_Reject,
45255 /* 126982 */ // Label 2456: @126982
45256 /* 126982 */ GIM_Try, /*On fail goto*//*Label 2464*/ GIMT_Encode4(127175),
45257 /* 126987 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45258 /* 126990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45259 /* 126994 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45260 /* 126998 */ GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(127046), // Rule ID 2611 //
45261 /* 127003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
45262 /* 127006 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VUITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
45263 /* 127006 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45264 /* 127009 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45265 /* 127013 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45266 /* 127018 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
45267 /* 127022 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45268 /* 127027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOS),
45269 /* 127030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
45270 /* 127032 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45271 /* 127035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45272 /* 127038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45273 /* 127044 */ GIR_RootConstrainSelectedInstOperands,
45274 /* 127045 */ // GIR_Coverage, 2611,
45275 /* 127045 */ GIR_EraseRootFromParent_Done,
45276 /* 127046 */ // Label 2465: @127046
45277 /* 127046 */ GIM_Try, /*On fail goto*//*Label 2466*/ GIMT_Encode4(127174), // Rule ID 3088 //
45278 /* 127051 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
45279 /* 127054 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTu2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
45280 /* 127054 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
45281 /* 127057 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45282 /* 127061 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45283 /* 127066 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a
45284 /* 127070 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45285 /* 127075 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
45286 /* 127078 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45287 /* 127082 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45288 /* 127087 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45289 /* 127089 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
45290 /* 127092 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45291 /* 127096 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45292 /* 127101 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
45293 /* 127104 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
45294 /* 127107 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
45295 /* 127110 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45296 /* 127115 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45297 /* 127120 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
45298 /* 127125 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
45299 /* 127128 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd),
45300 /* 127132 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45301 /* 127137 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45302 /* 127140 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
45303 /* 127143 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45304 /* 127149 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45305 /* 127151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45306 /* 127154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45307 /* 127156 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
45308 /* 127163 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45309 /* 127168 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45310 /* 127173 */ // GIR_Coverage, 3088,
45311 /* 127173 */ GIR_EraseRootFromParent_Done,
45312 /* 127174 */ // Label 2466: @127174
45313 /* 127174 */ GIM_Reject,
45314 /* 127175 */ // Label 2464: @127175
45315 /* 127175 */ GIM_Reject,
45316 /* 127176 */ // Label 2457: @127176
45317 /* 127176 */ GIM_Try, /*On fail goto*//*Label 2467*/ GIMT_Encode4(127235), // Rule ID 2607 //
45318 /* 127181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
45319 /* 127184 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45320 /* 127187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45321 /* 127191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45322 /* 127195 */ // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VUITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
45323 /* 127195 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45324 /* 127198 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45325 /* 127202 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45326 /* 127207 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
45327 /* 127211 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45328 /* 127216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOD),
45329 /* 127219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
45330 /* 127221 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45331 /* 127224 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45332 /* 127227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45333 /* 127233 */ GIR_RootConstrainSelectedInstOperands,
45334 /* 127234 */ // GIR_Coverage, 2607,
45335 /* 127234 */ GIR_EraseRootFromParent_Done,
45336 /* 127235 */ // Label 2467: @127235
45337 /* 127235 */ GIM_Reject,
45338 /* 127236 */ // Label 2458: @127236
45339 /* 127236 */ GIM_Try, /*On fail goto*//*Label 2468*/ GIMT_Encode4(127273), // Rule ID 1777 //
45340 /* 127241 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45341 /* 127244 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45342 /* 127247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45343 /* 127251 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45344 /* 127255 */ // (uint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
45345 /* 127255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hd),
45346 /* 127258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45347 /* 127260 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45348 /* 127262 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45349 /* 127265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45350 /* 127271 */ GIR_RootConstrainSelectedInstOperands,
45351 /* 127272 */ // GIR_Coverage, 1777,
45352 /* 127272 */ GIR_EraseRootFromParent_Done,
45353 /* 127273 */ // Label 2468: @127273
45354 /* 127273 */ GIM_Reject,
45355 /* 127274 */ // Label 2459: @127274
45356 /* 127274 */ GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(127372),
45357 /* 127279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45358 /* 127282 */ GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(127316), // Rule ID 1781 //
45359 /* 127287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45360 /* 127290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45361 /* 127294 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45362 /* 127298 */ // (uint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
45363 /* 127298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hq),
45364 /* 127301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45365 /* 127303 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45366 /* 127305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45367 /* 127308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45368 /* 127314 */ GIR_RootConstrainSelectedInstOperands,
45369 /* 127315 */ // GIR_Coverage, 1781,
45370 /* 127315 */ GIR_EraseRootFromParent_Done,
45371 /* 127316 */ // Label 2470: @127316
45372 /* 127316 */ GIM_Try, /*On fail goto*//*Label 2471*/ GIMT_Encode4(127371), // Rule ID 4536 //
45373 /* 127321 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45374 /* 127324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45375 /* 127328 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45376 /* 127332 */ // (uint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
45377 /* 127332 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45378 /* 127335 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45379 /* 127339 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45380 /* 127344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n),
45381 /* 127347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45382 /* 127349 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
45383 /* 127351 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45384 /* 127354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45385 /* 127360 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45386 /* 127366 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45387 /* 127369 */ GIR_RootConstrainSelectedInstOperands,
45388 /* 127370 */ // GIR_Coverage, 4536,
45389 /* 127370 */ GIR_EraseRootFromParent_Done,
45390 /* 127371 */ // Label 2471: @127371
45391 /* 127371 */ GIM_Reject,
45392 /* 127372 */ // Label 2469: @127372
45393 /* 127372 */ GIM_Reject,
45394 /* 127373 */ // Label 2460: @127373
45395 /* 127373 */ GIM_Try, /*On fail goto*//*Label 2472*/ GIMT_Encode4(127410), // Rule ID 1769 //
45396 /* 127378 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45397 /* 127381 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45398 /* 127384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45399 /* 127388 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45400 /* 127392 */ // (uint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
45401 /* 127392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd),
45402 /* 127395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45403 /* 127397 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45404 /* 127399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45405 /* 127402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45406 /* 127408 */ GIR_RootConstrainSelectedInstOperands,
45407 /* 127409 */ // GIR_Coverage, 1769,
45408 /* 127409 */ GIR_EraseRootFromParent_Done,
45409 /* 127410 */ // Label 2472: @127410
45410 /* 127410 */ GIM_Reject,
45411 /* 127411 */ // Label 2461: @127411
45412 /* 127411 */ GIM_Try, /*On fail goto*//*Label 2473*/ GIMT_Encode4(127509),
45413 /* 127416 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45414 /* 127419 */ GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(127453), // Rule ID 1773 //
45415 /* 127424 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45416 /* 127427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45417 /* 127431 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45418 /* 127435 */ // (uint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
45419 /* 127435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fq),
45420 /* 127438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45421 /* 127440 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45422 /* 127442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45423 /* 127445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45424 /* 127451 */ GIR_RootConstrainSelectedInstOperands,
45425 /* 127452 */ // GIR_Coverage, 1773,
45426 /* 127452 */ GIR_EraseRootFromParent_Done,
45427 /* 127453 */ // Label 2474: @127453
45428 /* 127453 */ GIM_Try, /*On fail goto*//*Label 2475*/ GIMT_Encode4(127508), // Rule ID 4542 //
45429 /* 127458 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45430 /* 127461 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45431 /* 127465 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45432 /* 127469 */ // (uint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
45433 /* 127469 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45434 /* 127472 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45435 /* 127476 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45436 /* 127481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n),
45437 /* 127484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45438 /* 127486 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
45439 /* 127488 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45440 /* 127491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45441 /* 127497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45442 /* 127503 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45443 /* 127506 */ GIR_RootConstrainSelectedInstOperands,
45444 /* 127507 */ // GIR_Coverage, 4542,
45445 /* 127507 */ GIR_EraseRootFromParent_Done,
45446 /* 127508 */ // Label 2475: @127508
45447 /* 127508 */ GIM_Reject,
45448 /* 127509 */ // Label 2473: @127509
45449 /* 127509 */ GIM_Reject,
45450 /* 127510 */ // Label 2462: @127510
45451 /* 127510 */ GIM_Reject,
45452 /* 127511 */ // Label 52: @127511
45453 /* 127511 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2483*/ GIMT_Encode4(128286),
45454 /* 127522 */ /*GILLT_s16*//*Label 2476*/ GIMT_Encode4(127574),
45455 /* 127526 */ /*GILLT_s32*//*Label 2477*/ GIMT_Encode4(127612),
45456 /* 127530 */ /*GILLT_s64*//*Label 2478*/ GIMT_Encode4(127804), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45457 /* 127558 */ /*GILLT_v4s16*//*Label 2479*/ GIMT_Encode4(127842),
45458 /* 127562 */ /*GILLT_v8s16*//*Label 2480*/ GIMT_Encode4(127880),
45459 /* 127566 */ /*GILLT_v2s32*//*Label 2481*/ GIMT_Encode4(128064),
45460 /* 127570 */ /*GILLT_v4s32*//*Label 2482*/ GIMT_Encode4(128102),
45461 /* 127574 */ // Label 2476: @127574
45462 /* 127574 */ GIM_Try, /*On fail goto*//*Label 2484*/ GIMT_Encode4(127611), // Rule ID 678 //
45463 /* 127579 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
45464 /* 127582 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
45465 /* 127585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45466 /* 127589 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45467 /* 127593 */ // (fabs:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VABSH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
45468 /* 127593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSH),
45469 /* 127596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
45470 /* 127598 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
45471 /* 127600 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45472 /* 127603 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45473 /* 127609 */ GIR_RootConstrainSelectedInstOperands,
45474 /* 127610 */ // GIR_Coverage, 678,
45475 /* 127610 */ GIR_EraseRootFromParent_Done,
45476 /* 127611 */ // Label 2484: @127611
45477 /* 127611 */ GIM_Reject,
45478 /* 127612 */ // Label 2477: @127612
45479 /* 127612 */ GIM_Try, /*On fail goto*//*Label 2485*/ GIMT_Encode4(127803),
45480 /* 127617 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45481 /* 127620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45482 /* 127624 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45483 /* 127628 */ GIM_Try, /*On fail goto*//*Label 2486*/ GIMT_Encode4(127654), // Rule ID 677 //
45484 /* 127633 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
45485 /* 127636 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VABSS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
45486 /* 127636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSS),
45487 /* 127639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
45488 /* 127641 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
45489 /* 127643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45490 /* 127646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45491 /* 127652 */ GIR_RootConstrainSelectedInstOperands,
45492 /* 127653 */ // GIR_Coverage, 677,
45493 /* 127653 */ GIR_EraseRootFromParent_Done,
45494 /* 127654 */ // Label 2486: @127654
45495 /* 127654 */ GIM_Try, /*On fail goto*//*Label 2487*/ GIMT_Encode4(127802), // Rule ID 3079 //
45496 /* 127659 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
45497 /* 127662 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VABSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
45498 /* 127662 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
45499 /* 127665 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45500 /* 127669 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45501 /* 127674 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
45502 /* 127676 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
45503 /* 127679 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45504 /* 127683 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45505 /* 127688 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
45506 /* 127691 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45507 /* 127696 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
45508 /* 127699 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45509 /* 127703 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45510 /* 127708 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
45511 /* 127711 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
45512 /* 127715 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
45513 /* 127718 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45514 /* 127723 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45515 /* 127728 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
45516 /* 127733 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
45517 /* 127736 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VABSfd),
45518 /* 127740 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45519 /* 127745 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
45520 /* 127748 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
45521 /* 127751 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45522 /* 127757 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45523 /* 127759 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
45524 /* 127762 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45525 /* 127766 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45526 /* 127771 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45527 /* 127774 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45528 /* 127779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45529 /* 127782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45530 /* 127784 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
45531 /* 127791 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45532 /* 127796 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45533 /* 127801 */ // GIR_Coverage, 3079,
45534 /* 127801 */ GIR_EraseRootFromParent_Done,
45535 /* 127802 */ // Label 2487: @127802
45536 /* 127802 */ GIM_Reject,
45537 /* 127803 */ // Label 2485: @127803
45538 /* 127803 */ GIM_Reject,
45539 /* 127804 */ // Label 2478: @127804
45540 /* 127804 */ GIM_Try, /*On fail goto*//*Label 2488*/ GIMT_Encode4(127841), // Rule ID 676 //
45541 /* 127809 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
45542 /* 127812 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
45543 /* 127815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45544 /* 127819 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45545 /* 127823 */ // (fabs:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VABSD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
45546 /* 127823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSD),
45547 /* 127826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
45548 /* 127828 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
45549 /* 127830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45550 /* 127833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45551 /* 127839 */ GIR_RootConstrainSelectedInstOperands,
45552 /* 127840 */ // GIR_Coverage, 676,
45553 /* 127840 */ GIR_EraseRootFromParent_Done,
45554 /* 127841 */ // Label 2488: @127841
45555 /* 127841 */ GIM_Reject,
45556 /* 127842 */ // Label 2479: @127842
45557 /* 127842 */ GIM_Try, /*On fail goto*//*Label 2489*/ GIMT_Encode4(127879), // Rule ID 1678 //
45558 /* 127847 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45559 /* 127850 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45560 /* 127853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45561 /* 127857 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45562 /* 127861 */ // (fabs:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VABShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
45563 /* 127861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShd),
45564 /* 127864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45565 /* 127866 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45566 /* 127868 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45567 /* 127871 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45568 /* 127877 */ GIR_RootConstrainSelectedInstOperands,
45569 /* 127878 */ // GIR_Coverage, 1678,
45570 /* 127878 */ GIR_EraseRootFromParent_Done,
45571 /* 127879 */ // Label 2489: @127879
45572 /* 127879 */ GIM_Reject,
45573 /* 127880 */ // Label 2480: @127880
45574 /* 127880 */ GIM_Try, /*On fail goto*//*Label 2490*/ GIMT_Encode4(128063),
45575 /* 127885 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45576 /* 127888 */ GIM_Try, /*On fail goto*//*Label 2491*/ GIMT_Encode4(127973), // Rule ID 4471 //
45577 /* 127893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45578 /* 127896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45579 /* 127900 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45580 /* 127904 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
45581 /* 127908 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
45582 /* 127912 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
45583 /* 127916 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45584 /* 127921 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45585 /* 127926 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45586 /* 127928 */ // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
45587 /* 127928 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45588 /* 127931 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45589 /* 127935 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45590 /* 127940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16),
45591 /* 127943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45592 /* 127945 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45593 /* 127949 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn
45594 /* 127953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45595 /* 127956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45596 /* 127962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45597 /* 127968 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45598 /* 127971 */ GIR_RootConstrainSelectedInstOperands,
45599 /* 127972 */ // GIR_Coverage, 4471,
45600 /* 127972 */ GIR_EraseRootFromParent_Done,
45601 /* 127973 */ // Label 2491: @127973
45602 /* 127973 */ GIM_Try, /*On fail goto*//*Label 2492*/ GIMT_Encode4(128007), // Rule ID 1679 //
45603 /* 127978 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45604 /* 127981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45605 /* 127985 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45606 /* 127989 */ // (fabs:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VABShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
45607 /* 127989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShq),
45608 /* 127992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45609 /* 127994 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45610 /* 127996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45611 /* 127999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45612 /* 128005 */ GIR_RootConstrainSelectedInstOperands,
45613 /* 128006 */ // GIR_Coverage, 1679,
45614 /* 128006 */ GIR_EraseRootFromParent_Done,
45615 /* 128007 */ // Label 2492: @128007
45616 /* 128007 */ GIM_Try, /*On fail goto*//*Label 2493*/ GIMT_Encode4(128062), // Rule ID 4549 //
45617 /* 128012 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
45618 /* 128015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45619 /* 128019 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45620 /* 128023 */ // (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VABSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v)
45621 /* 128023 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45622 /* 128026 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45623 /* 128030 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45624 /* 128035 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf16),
45625 /* 128038 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45626 /* 128040 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
45627 /* 128042 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45628 /* 128045 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45629 /* 128051 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45630 /* 128057 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45631 /* 128060 */ GIR_RootConstrainSelectedInstOperands,
45632 /* 128061 */ // GIR_Coverage, 4549,
45633 /* 128061 */ GIR_EraseRootFromParent_Done,
45634 /* 128062 */ // Label 2493: @128062
45635 /* 128062 */ GIM_Reject,
45636 /* 128063 */ // Label 2490: @128063
45637 /* 128063 */ GIM_Reject,
45638 /* 128064 */ // Label 2481: @128064
45639 /* 128064 */ GIM_Try, /*On fail goto*//*Label 2494*/ GIMT_Encode4(128101), // Rule ID 1676 //
45640 /* 128069 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45641 /* 128072 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45642 /* 128075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45643 /* 128079 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45644 /* 128083 */ // (fabs:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VABSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
45645 /* 128083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfd),
45646 /* 128086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45647 /* 128088 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45648 /* 128090 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45649 /* 128093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45650 /* 128099 */ GIR_RootConstrainSelectedInstOperands,
45651 /* 128100 */ // GIR_Coverage, 1676,
45652 /* 128100 */ GIR_EraseRootFromParent_Done,
45653 /* 128101 */ // Label 2494: @128101
45654 /* 128101 */ GIM_Reject,
45655 /* 128102 */ // Label 2482: @128102
45656 /* 128102 */ GIM_Try, /*On fail goto*//*Label 2495*/ GIMT_Encode4(128285),
45657 /* 128107 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45658 /* 128110 */ GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(128195), // Rule ID 4472 //
45659 /* 128115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45660 /* 128118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45661 /* 128122 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45662 /* 128126 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
45663 /* 128130 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
45664 /* 128134 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
45665 /* 128138 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45666 /* 128143 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45667 /* 128148 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45668 /* 128150 */ // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
45669 /* 128150 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45670 /* 128153 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45671 /* 128157 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45672 /* 128162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32),
45673 /* 128165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45674 /* 128167 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45675 /* 128171 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn
45676 /* 128175 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45677 /* 128178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45678 /* 128184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45679 /* 128190 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45680 /* 128193 */ GIR_RootConstrainSelectedInstOperands,
45681 /* 128194 */ // GIR_Coverage, 4472,
45682 /* 128194 */ GIR_EraseRootFromParent_Done,
45683 /* 128195 */ // Label 2496: @128195
45684 /* 128195 */ GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(128229), // Rule ID 1677 //
45685 /* 128200 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45686 /* 128203 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45687 /* 128207 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45688 /* 128211 */ // (fabs:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VABSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
45689 /* 128211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfq),
45690 /* 128214 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45691 /* 128216 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45692 /* 128218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45693 /* 128221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45694 /* 128227 */ GIR_RootConstrainSelectedInstOperands,
45695 /* 128228 */ // GIR_Coverage, 1677,
45696 /* 128228 */ GIR_EraseRootFromParent_Done,
45697 /* 128229 */ // Label 2497: @128229
45698 /* 128229 */ GIM_Try, /*On fail goto*//*Label 2498*/ GIMT_Encode4(128284), // Rule ID 4551 //
45699 /* 128234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
45700 /* 128237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45701 /* 128241 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45702 /* 128245 */ // (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VABSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v)
45703 /* 128245 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45704 /* 128248 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45705 /* 128252 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45706 /* 128257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf32),
45707 /* 128260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45708 /* 128262 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
45709 /* 128264 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45710 /* 128267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45711 /* 128273 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45712 /* 128279 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45713 /* 128282 */ GIR_RootConstrainSelectedInstOperands,
45714 /* 128283 */ // GIR_Coverage, 4551,
45715 /* 128283 */ GIR_EraseRootFromParent_Done,
45716 /* 128284 */ // Label 2498: @128284
45717 /* 128284 */ GIM_Reject,
45718 /* 128285 */ // Label 2495: @128285
45719 /* 128285 */ GIM_Reject,
45720 /* 128286 */ // Label 2483: @128286
45721 /* 128286 */ GIM_Reject,
45722 /* 128287 */ // Label 53: @128287
45723 /* 128287 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2506*/ GIMT_Encode4(128878),
45724 /* 128298 */ /*GILLT_s16*//*Label 2499*/ GIMT_Encode4(128350),
45725 /* 128302 */ /*GILLT_s32*//*Label 2500*/ GIMT_Encode4(128384),
45726 /* 128306 */ /*GILLT_s64*//*Label 2501*/ GIMT_Encode4(128418), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45727 /* 128334 */ /*GILLT_v4s16*//*Label 2502*/ GIMT_Encode4(128452),
45728 /* 128338 */ /*GILLT_v8s16*//*Label 2503*/ GIMT_Encode4(128486),
45729 /* 128342 */ /*GILLT_v2s32*//*Label 2504*/ GIMT_Encode4(128665),
45730 /* 128346 */ /*GILLT_v4s32*//*Label 2505*/ GIMT_Encode4(128699),
45731 /* 128350 */ // Label 2499: @128350
45732 /* 128350 */ GIM_Try, /*On fail goto*//*Label 2507*/ GIMT_Encode4(128383), // Rule ID 665 //
45733 /* 128355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
45734 /* 128358 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
45735 /* 128361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
45736 /* 128364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45737 /* 128368 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45738 /* 128372 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45739 /* 128376 */ // (fminnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMINNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
45740 /* 128376 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMH),
45741 /* 128381 */ GIR_RootConstrainSelectedInstOperands,
45742 /* 128382 */ // GIR_Coverage, 665,
45743 /* 128382 */ GIR_Done,
45744 /* 128383 */ // Label 2507: @128383
45745 /* 128383 */ GIM_Reject,
45746 /* 128384 */ // Label 2500: @128384
45747 /* 128384 */ GIM_Try, /*On fail goto*//*Label 2508*/ GIMT_Encode4(128417), // Rule ID 667 //
45748 /* 128389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
45749 /* 128392 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45750 /* 128395 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
45751 /* 128398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45752 /* 128402 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45753 /* 128406 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45754 /* 128410 */ // (fminnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMINNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
45755 /* 128410 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMS),
45756 /* 128415 */ GIR_RootConstrainSelectedInstOperands,
45757 /* 128416 */ // GIR_Coverage, 667,
45758 /* 128416 */ GIR_Done,
45759 /* 128417 */ // Label 2508: @128417
45760 /* 128417 */ GIM_Reject,
45761 /* 128418 */ // Label 2501: @128418
45762 /* 128418 */ GIM_Try, /*On fail goto*//*Label 2509*/ GIMT_Encode4(128451), // Rule ID 669 //
45763 /* 128423 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
45764 /* 128426 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
45765 /* 128429 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
45766 /* 128432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45767 /* 128436 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45768 /* 128440 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45769 /* 128444 */ // (fminnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMINNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
45770 /* 128444 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMD),
45771 /* 128449 */ GIR_RootConstrainSelectedInstOperands,
45772 /* 128450 */ // GIR_Coverage, 669,
45773 /* 128450 */ GIR_Done,
45774 /* 128451 */ // Label 2509: @128451
45775 /* 128451 */ GIM_Reject,
45776 /* 128452 */ // Label 2502: @128452
45777 /* 128452 */ GIM_Try, /*On fail goto*//*Label 2510*/ GIMT_Encode4(128485), // Rule ID 1397 //
45778 /* 128457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON),
45779 /* 128460 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45780 /* 128463 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
45781 /* 128466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45782 /* 128470 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45783 /* 128474 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45784 /* 128478 */ // (fminnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMINNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
45785 /* 128478 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDh),
45786 /* 128483 */ GIR_RootConstrainSelectedInstOperands,
45787 /* 128484 */ // GIR_Coverage, 1397,
45788 /* 128484 */ GIR_Done,
45789 /* 128485 */ // Label 2510: @128485
45790 /* 128485 */ GIM_Reject,
45791 /* 128486 */ // Label 2503: @128486
45792 /* 128486 */ GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(128664),
45793 /* 128491 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45794 /* 128494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
45795 /* 128497 */ GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(128575), // Rule ID 4566 //
45796 /* 128502 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
45797 /* 128505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45798 /* 128509 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45799 /* 128513 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
45800 /* 128517 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
45801 /* 128521 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45802 /* 128526 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
45803 /* 128530 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
45804 /* 128534 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
45805 /* 128538 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45806 /* 128543 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
45807 /* 128545 */ // (fminnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
45808 /* 128545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16),
45809 /* 128548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45810 /* 128550 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
45811 /* 128554 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
45812 /* 128558 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45813 /* 128561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45814 /* 128567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45815 /* 128573 */ GIR_RootConstrainSelectedInstOperands,
45816 /* 128574 */ // GIR_Coverage, 4566,
45817 /* 128574 */ GIR_EraseRootFromParent_Done,
45818 /* 128575 */ // Label 2512: @128575
45819 /* 128575 */ GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(128602), // Rule ID 1398 //
45820 /* 128580 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON),
45821 /* 128583 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45822 /* 128587 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45823 /* 128591 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45824 /* 128595 */ // (fminnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMINNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
45825 /* 128595 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQh),
45826 /* 128600 */ GIR_RootConstrainSelectedInstOperands,
45827 /* 128601 */ // GIR_Coverage, 1398,
45828 /* 128601 */ GIR_Done,
45829 /* 128602 */ // Label 2513: @128602
45830 /* 128602 */ GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(128663), // Rule ID 3672 //
45831 /* 128607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45832 /* 128610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45833 /* 128614 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45834 /* 128618 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45835 /* 128622 */ // (fminnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
45836 /* 128622 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45837 /* 128625 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45838 /* 128629 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45839 /* 128634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16),
45840 /* 128637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45841 /* 128639 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
45842 /* 128641 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
45843 /* 128643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45844 /* 128646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45845 /* 128652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45846 /* 128658 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45847 /* 128661 */ GIR_RootConstrainSelectedInstOperands,
45848 /* 128662 */ // GIR_Coverage, 3672,
45849 /* 128662 */ GIR_EraseRootFromParent_Done,
45850 /* 128663 */ // Label 2514: @128663
45851 /* 128663 */ GIM_Reject,
45852 /* 128664 */ // Label 2511: @128664
45853 /* 128664 */ GIM_Reject,
45854 /* 128665 */ // Label 2504: @128665
45855 /* 128665 */ GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(128698), // Rule ID 1395 //
45856 /* 128670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON),
45857 /* 128673 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45858 /* 128676 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
45859 /* 128679 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45860 /* 128683 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45861 /* 128687 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45862 /* 128691 */ // (fminnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMINNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
45863 /* 128691 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDf),
45864 /* 128696 */ GIR_RootConstrainSelectedInstOperands,
45865 /* 128697 */ // GIR_Coverage, 1395,
45866 /* 128697 */ GIR_Done,
45867 /* 128698 */ // Label 2515: @128698
45868 /* 128698 */ GIM_Reject,
45869 /* 128699 */ // Label 2505: @128699
45870 /* 128699 */ GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(128877),
45871 /* 128704 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45872 /* 128707 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
45873 /* 128710 */ GIM_Try, /*On fail goto*//*Label 2517*/ GIMT_Encode4(128788), // Rule ID 4563 //
45874 /* 128715 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
45875 /* 128718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45876 /* 128722 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45877 /* 128726 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
45878 /* 128730 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
45879 /* 128734 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45880 /* 128739 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
45881 /* 128743 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
45882 /* 128747 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
45883 /* 128751 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45884 /* 128756 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
45885 /* 128758 */ // (fminnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
45886 /* 128758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32),
45887 /* 128761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45888 /* 128763 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
45889 /* 128767 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
45890 /* 128771 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45891 /* 128774 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45892 /* 128780 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45893 /* 128786 */ GIR_RootConstrainSelectedInstOperands,
45894 /* 128787 */ // GIR_Coverage, 4563,
45895 /* 128787 */ GIR_EraseRootFromParent_Done,
45896 /* 128788 */ // Label 2517: @128788
45897 /* 128788 */ GIM_Try, /*On fail goto*//*Label 2518*/ GIMT_Encode4(128815), // Rule ID 1396 //
45898 /* 128793 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON),
45899 /* 128796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45900 /* 128800 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45901 /* 128804 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45902 /* 128808 */ // (fminnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMINNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
45903 /* 128808 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQf),
45904 /* 128813 */ GIR_RootConstrainSelectedInstOperands,
45905 /* 128814 */ // GIR_Coverage, 1396,
45906 /* 128814 */ GIR_Done,
45907 /* 128815 */ // Label 2518: @128815
45908 /* 128815 */ GIM_Try, /*On fail goto*//*Label 2519*/ GIMT_Encode4(128876), // Rule ID 3667 //
45909 /* 128820 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45910 /* 128823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45911 /* 128827 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45912 /* 128831 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45913 /* 128835 */ // (fminnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
45914 /* 128835 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45915 /* 128838 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45916 /* 128842 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45917 /* 128847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32),
45918 /* 128850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45919 /* 128852 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
45920 /* 128854 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
45921 /* 128856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45922 /* 128859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45923 /* 128865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45924 /* 128871 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45925 /* 128874 */ GIR_RootConstrainSelectedInstOperands,
45926 /* 128875 */ // GIR_Coverage, 3667,
45927 /* 128875 */ GIR_EraseRootFromParent_Done,
45928 /* 128876 */ // Label 2519: @128876
45929 /* 128876 */ GIM_Reject,
45930 /* 128877 */ // Label 2516: @128877
45931 /* 128877 */ GIM_Reject,
45932 /* 128878 */ // Label 2506: @128878
45933 /* 128878 */ GIM_Reject,
45934 /* 128879 */ // Label 54: @128879
45935 /* 128879 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2527*/ GIMT_Encode4(129470),
45936 /* 128890 */ /*GILLT_s16*//*Label 2520*/ GIMT_Encode4(128942),
45937 /* 128894 */ /*GILLT_s32*//*Label 2521*/ GIMT_Encode4(128976),
45938 /* 128898 */ /*GILLT_s64*//*Label 2522*/ GIMT_Encode4(129010), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45939 /* 128926 */ /*GILLT_v4s16*//*Label 2523*/ GIMT_Encode4(129044),
45940 /* 128930 */ /*GILLT_v8s16*//*Label 2524*/ GIMT_Encode4(129078),
45941 /* 128934 */ /*GILLT_v2s32*//*Label 2525*/ GIMT_Encode4(129257),
45942 /* 128938 */ /*GILLT_v4s32*//*Label 2526*/ GIMT_Encode4(129291),
45943 /* 128942 */ // Label 2520: @128942
45944 /* 128942 */ GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(128975), // Rule ID 659 //
45945 /* 128947 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
45946 /* 128950 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
45947 /* 128953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
45948 /* 128956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45949 /* 128960 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45950 /* 128964 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45951 /* 128968 */ // (fmaxnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMAXNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
45952 /* 128968 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMH),
45953 /* 128973 */ GIR_RootConstrainSelectedInstOperands,
45954 /* 128974 */ // GIR_Coverage, 659,
45955 /* 128974 */ GIR_Done,
45956 /* 128975 */ // Label 2528: @128975
45957 /* 128975 */ GIM_Reject,
45958 /* 128976 */ // Label 2521: @128976
45959 /* 128976 */ GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(129009), // Rule ID 661 //
45960 /* 128981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
45961 /* 128984 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45962 /* 128987 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
45963 /* 128990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45964 /* 128994 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45965 /* 128998 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45966 /* 129002 */ // (fmaxnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMAXNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
45967 /* 129002 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMS),
45968 /* 129007 */ GIR_RootConstrainSelectedInstOperands,
45969 /* 129008 */ // GIR_Coverage, 661,
45970 /* 129008 */ GIR_Done,
45971 /* 129009 */ // Label 2529: @129009
45972 /* 129009 */ GIM_Reject,
45973 /* 129010 */ // Label 2522: @129010
45974 /* 129010 */ GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(129043), // Rule ID 663 //
45975 /* 129015 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
45976 /* 129018 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
45977 /* 129021 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
45978 /* 129024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45979 /* 129028 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45980 /* 129032 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45981 /* 129036 */ // (fmaxnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMAXNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
45982 /* 129036 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMD),
45983 /* 129041 */ GIR_RootConstrainSelectedInstOperands,
45984 /* 129042 */ // GIR_Coverage, 663,
45985 /* 129042 */ GIR_Done,
45986 /* 129043 */ // Label 2530: @129043
45987 /* 129043 */ GIM_Reject,
45988 /* 129044 */ // Label 2523: @129044
45989 /* 129044 */ GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(129077), // Rule ID 1377 //
45990 /* 129049 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON),
45991 /* 129052 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45992 /* 129055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
45993 /* 129058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45994 /* 129062 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45995 /* 129066 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45996 /* 129070 */ // (fmaxnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMAXNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
45997 /* 129070 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDh),
45998 /* 129075 */ GIR_RootConstrainSelectedInstOperands,
45999 /* 129076 */ // GIR_Coverage, 1377,
46000 /* 129076 */ GIR_Done,
46001 /* 129077 */ // Label 2531: @129077
46002 /* 129077 */ GIM_Reject,
46003 /* 129078 */ // Label 2524: @129078
46004 /* 129078 */ GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(129256),
46005 /* 129083 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
46006 /* 129086 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
46007 /* 129089 */ GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(129167), // Rule ID 4560 //
46008 /* 129094 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46009 /* 129097 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46010 /* 129101 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46011 /* 129105 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
46012 /* 129109 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
46013 /* 129113 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46014 /* 129118 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
46015 /* 129122 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
46016 /* 129126 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
46017 /* 129130 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46018 /* 129135 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46019 /* 129137 */ // (fmaxnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
46020 /* 129137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16),
46021 /* 129140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46022 /* 129142 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
46023 /* 129146 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
46024 /* 129150 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46025 /* 129153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46026 /* 129159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46027 /* 129165 */ GIR_RootConstrainSelectedInstOperands,
46028 /* 129166 */ // GIR_Coverage, 4560,
46029 /* 129166 */ GIR_EraseRootFromParent_Done,
46030 /* 129167 */ // Label 2533: @129167
46031 /* 129167 */ GIM_Try, /*On fail goto*//*Label 2534*/ GIMT_Encode4(129194), // Rule ID 1378 //
46032 /* 129172 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON),
46033 /* 129175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46034 /* 129179 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46035 /* 129183 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46036 /* 129187 */ // (fmaxnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMAXNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
46037 /* 129187 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQh),
46038 /* 129192 */ GIR_RootConstrainSelectedInstOperands,
46039 /* 129193 */ // GIR_Coverage, 1378,
46040 /* 129193 */ GIR_Done,
46041 /* 129194 */ // Label 2534: @129194
46042 /* 129194 */ GIM_Try, /*On fail goto*//*Label 2535*/ GIMT_Encode4(129255), // Rule ID 3662 //
46043 /* 129199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
46044 /* 129202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46045 /* 129206 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46046 /* 129210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46047 /* 129214 */ // (fmaxnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
46048 /* 129214 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46049 /* 129217 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46050 /* 129221 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46051 /* 129226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16),
46052 /* 129229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46053 /* 129231 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
46054 /* 129233 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
46055 /* 129235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46056 /* 129238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46057 /* 129244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46058 /* 129250 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46059 /* 129253 */ GIR_RootConstrainSelectedInstOperands,
46060 /* 129254 */ // GIR_Coverage, 3662,
46061 /* 129254 */ GIR_EraseRootFromParent_Done,
46062 /* 129255 */ // Label 2535: @129255
46063 /* 129255 */ GIM_Reject,
46064 /* 129256 */ // Label 2532: @129256
46065 /* 129256 */ GIM_Reject,
46066 /* 129257 */ // Label 2525: @129257
46067 /* 129257 */ GIM_Try, /*On fail goto*//*Label 2536*/ GIMT_Encode4(129290), // Rule ID 1375 //
46068 /* 129262 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON),
46069 /* 129265 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
46070 /* 129268 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
46071 /* 129271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46072 /* 129275 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46073 /* 129279 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46074 /* 129283 */ // (fmaxnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMAXNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
46075 /* 129283 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDf),
46076 /* 129288 */ GIR_RootConstrainSelectedInstOperands,
46077 /* 129289 */ // GIR_Coverage, 1375,
46078 /* 129289 */ GIR_Done,
46079 /* 129290 */ // Label 2536: @129290
46080 /* 129290 */ GIM_Reject,
46081 /* 129291 */ // Label 2526: @129291
46082 /* 129291 */ GIM_Try, /*On fail goto*//*Label 2537*/ GIMT_Encode4(129469),
46083 /* 129296 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
46084 /* 129299 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
46085 /* 129302 */ GIM_Try, /*On fail goto*//*Label 2538*/ GIMT_Encode4(129380), // Rule ID 4557 //
46086 /* 129307 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46087 /* 129310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46088 /* 129314 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46089 /* 129318 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
46090 /* 129322 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
46091 /* 129326 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46092 /* 129331 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
46093 /* 129335 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
46094 /* 129339 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
46095 /* 129343 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46096 /* 129348 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46097 /* 129350 */ // (fmaxnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
46098 /* 129350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32),
46099 /* 129353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46100 /* 129355 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
46101 /* 129359 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
46102 /* 129363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46103 /* 129366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46104 /* 129372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46105 /* 129378 */ GIR_RootConstrainSelectedInstOperands,
46106 /* 129379 */ // GIR_Coverage, 4557,
46107 /* 129379 */ GIR_EraseRootFromParent_Done,
46108 /* 129380 */ // Label 2538: @129380
46109 /* 129380 */ GIM_Try, /*On fail goto*//*Label 2539*/ GIMT_Encode4(129407), // Rule ID 1376 //
46110 /* 129385 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON),
46111 /* 129388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46112 /* 129392 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46113 /* 129396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46114 /* 129400 */ // (fmaxnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMAXNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
46115 /* 129400 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQf),
46116 /* 129405 */ GIR_RootConstrainSelectedInstOperands,
46117 /* 129406 */ // GIR_Coverage, 1376,
46118 /* 129406 */ GIR_Done,
46119 /* 129407 */ // Label 2539: @129407
46120 /* 129407 */ GIM_Try, /*On fail goto*//*Label 2540*/ GIMT_Encode4(129468), // Rule ID 3405 //
46121 /* 129412 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
46122 /* 129415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46123 /* 129419 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46124 /* 129423 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46125 /* 129427 */ // (fmaxnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
46126 /* 129427 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46127 /* 129430 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46128 /* 129434 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46129 /* 129439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32),
46130 /* 129442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46131 /* 129444 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
46132 /* 129446 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
46133 /* 129448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46134 /* 129451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46135 /* 129457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46136 /* 129463 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46137 /* 129466 */ GIR_RootConstrainSelectedInstOperands,
46138 /* 129467 */ // GIR_Coverage, 3405,
46139 /* 129467 */ GIR_EraseRootFromParent_Done,
46140 /* 129468 */ // Label 2540: @129468
46141 /* 129468 */ GIM_Reject,
46142 /* 129469 */ // Label 2537: @129469
46143 /* 129469 */ GIM_Reject,
46144 /* 129470 */ // Label 2527: @129470
46145 /* 129470 */ GIM_Reject,
46146 /* 129471 */ // Label 55: @129471
46147 /* 129471 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2547*/ GIMT_Encode4(130204),
46148 /* 129482 */ /*GILLT_s16*//*Label 2541*/ GIMT_Encode4(129534),
46149 /* 129486 */ /*GILLT_s32*//*Label 2542*/ GIMT_Encode4(129775), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
46150 /* 129518 */ /*GILLT_v4s16*//*Label 2543*/ GIMT_Encode4(130016),
46151 /* 129522 */ /*GILLT_v8s16*//*Label 2544*/ GIMT_Encode4(130063),
46152 /* 129526 */ /*GILLT_v2s32*//*Label 2545*/ GIMT_Encode4(130110),
46153 /* 129530 */ /*GILLT_v4s32*//*Label 2546*/ GIMT_Encode4(130157),
46154 /* 129534 */ // Label 2541: @129534
46155 /* 129534 */ GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(129774), // Rule ID 3082 //
46156 /* 129539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
46157 /* 129542 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46158 /* 129545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46159 /* 129548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46160 /* 129552 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46161 /* 129556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46162 /* 129560 */ // (fminimum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMINhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
46163 /* 129560 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
46164 /* 129563 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46165 /* 129567 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46166 /* 129572 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
46167 /* 129574 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
46168 /* 129577 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46169 /* 129581 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46170 /* 129586 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
46171 /* 129589 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46172 /* 129594 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
46173 /* 129597 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46174 /* 129601 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46175 /* 129606 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
46176 /* 129609 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
46177 /* 129613 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
46178 /* 129616 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46179 /* 129621 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46180 /* 129626 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
46181 /* 129631 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
46182 /* 129634 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46183 /* 129638 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46184 /* 129643 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
46185 /* 129645 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
46186 /* 129648 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46187 /* 129652 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46188 /* 129657 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
46189 /* 129660 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46190 /* 129665 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
46191 /* 129668 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46192 /* 129672 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46193 /* 129677 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
46194 /* 129680 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
46195 /* 129684 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
46196 /* 129687 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46197 /* 129692 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46198 /* 129697 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
46199 /* 129702 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
46200 /* 129705 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINhd),
46201 /* 129709 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46202 /* 129714 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
46203 /* 129717 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
46204 /* 129720 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
46205 /* 129723 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46206 /* 129729 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46207 /* 129731 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
46208 /* 129734 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46209 /* 129738 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46210 /* 129743 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
46211 /* 129746 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46212 /* 129751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46213 /* 129754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46214 /* 129756 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
46215 /* 129763 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
46216 /* 129768 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46217 /* 129773 */ // GIR_Coverage, 3082,
46218 /* 129773 */ GIR_EraseRootFromParent_Done,
46219 /* 129774 */ // Label 2548: @129774
46220 /* 129774 */ GIM_Reject,
46221 /* 129775 */ // Label 2542: @129775
46222 /* 129775 */ GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(130015), // Rule ID 3084 //
46223 /* 129780 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46224 /* 129783 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46225 /* 129786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46226 /* 129789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46227 /* 129793 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46228 /* 129797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46229 /* 129801 */ // (fminimum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMINfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
46230 /* 129801 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
46231 /* 129804 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46232 /* 129808 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46233 /* 129813 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
46234 /* 129815 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
46235 /* 129818 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46236 /* 129822 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46237 /* 129827 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
46238 /* 129830 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46239 /* 129835 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
46240 /* 129838 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46241 /* 129842 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46242 /* 129847 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
46243 /* 129850 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
46244 /* 129854 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
46245 /* 129857 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46246 /* 129862 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46247 /* 129867 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
46248 /* 129872 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
46249 /* 129875 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46250 /* 129879 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46251 /* 129884 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
46252 /* 129886 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
46253 /* 129889 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46254 /* 129893 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46255 /* 129898 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
46256 /* 129901 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46257 /* 129906 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
46258 /* 129909 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46259 /* 129913 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46260 /* 129918 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
46261 /* 129921 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
46262 /* 129925 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
46263 /* 129928 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46264 /* 129933 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46265 /* 129938 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
46266 /* 129943 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
46267 /* 129946 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINfd),
46268 /* 129950 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46269 /* 129955 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
46270 /* 129958 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
46271 /* 129961 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
46272 /* 129964 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46273 /* 129970 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46274 /* 129972 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
46275 /* 129975 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46276 /* 129979 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46277 /* 129984 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
46278 /* 129987 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46279 /* 129992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46280 /* 129995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46281 /* 129997 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
46282 /* 130004 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
46283 /* 130009 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46284 /* 130014 */ // GIR_Coverage, 3084,
46285 /* 130014 */ GIR_EraseRootFromParent_Done,
46286 /* 130015 */ // Label 2549: @130015
46287 /* 130015 */ GIM_Reject,
46288 /* 130016 */ // Label 2543: @130016
46289 /* 130016 */ GIM_Try, /*On fail goto*//*Label 2550*/ GIMT_Encode4(130062), // Rule ID 1393 //
46290 /* 130021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
46291 /* 130024 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
46292 /* 130027 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
46293 /* 130030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46294 /* 130034 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46295 /* 130038 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46296 /* 130042 */ // (fminimum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMINhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
46297 /* 130042 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhd),
46298 /* 130045 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46299 /* 130047 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46300 /* 130049 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46301 /* 130051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46302 /* 130054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46303 /* 130060 */ GIR_RootConstrainSelectedInstOperands,
46304 /* 130061 */ // GIR_Coverage, 1393,
46305 /* 130061 */ GIR_EraseRootFromParent_Done,
46306 /* 130062 */ // Label 2550: @130062
46307 /* 130062 */ GIM_Reject,
46308 /* 130063 */ // Label 2544: @130063
46309 /* 130063 */ GIM_Try, /*On fail goto*//*Label 2551*/ GIMT_Encode4(130109), // Rule ID 1394 //
46310 /* 130068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
46311 /* 130071 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
46312 /* 130074 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
46313 /* 130077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46314 /* 130081 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46315 /* 130085 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46316 /* 130089 */ // (fminimum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMINhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
46317 /* 130089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhq),
46318 /* 130092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46319 /* 130094 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46320 /* 130096 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46321 /* 130098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46322 /* 130101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46323 /* 130107 */ GIR_RootConstrainSelectedInstOperands,
46324 /* 130108 */ // GIR_Coverage, 1394,
46325 /* 130108 */ GIR_EraseRootFromParent_Done,
46326 /* 130109 */ // Label 2551: @130109
46327 /* 130109 */ GIM_Reject,
46328 /* 130110 */ // Label 2545: @130110
46329 /* 130110 */ GIM_Try, /*On fail goto*//*Label 2552*/ GIMT_Encode4(130156), // Rule ID 1391 //
46330 /* 130115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46331 /* 130118 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
46332 /* 130121 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
46333 /* 130124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46334 /* 130128 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46335 /* 130132 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46336 /* 130136 */ // (fminimum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMINfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
46337 /* 130136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfd),
46338 /* 130139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46339 /* 130141 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46340 /* 130143 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46341 /* 130145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46342 /* 130148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46343 /* 130154 */ GIR_RootConstrainSelectedInstOperands,
46344 /* 130155 */ // GIR_Coverage, 1391,
46345 /* 130155 */ GIR_EraseRootFromParent_Done,
46346 /* 130156 */ // Label 2552: @130156
46347 /* 130156 */ GIM_Reject,
46348 /* 130157 */ // Label 2546: @130157
46349 /* 130157 */ GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(130203), // Rule ID 1392 //
46350 /* 130162 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46351 /* 130165 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
46352 /* 130168 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
46353 /* 130171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46354 /* 130175 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46355 /* 130179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46356 /* 130183 */ // (fminimum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMINfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
46357 /* 130183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfq),
46358 /* 130186 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46359 /* 130188 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46360 /* 130190 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46361 /* 130192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46362 /* 130195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46363 /* 130201 */ GIR_RootConstrainSelectedInstOperands,
46364 /* 130202 */ // GIR_Coverage, 1392,
46365 /* 130202 */ GIR_EraseRootFromParent_Done,
46366 /* 130203 */ // Label 2553: @130203
46367 /* 130203 */ GIM_Reject,
46368 /* 130204 */ // Label 2547: @130204
46369 /* 130204 */ GIM_Reject,
46370 /* 130205 */ // Label 56: @130205
46371 /* 130205 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2560*/ GIMT_Encode4(130938),
46372 /* 130216 */ /*GILLT_s16*//*Label 2554*/ GIMT_Encode4(130268),
46373 /* 130220 */ /*GILLT_s32*//*Label 2555*/ GIMT_Encode4(130509), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
46374 /* 130252 */ /*GILLT_v4s16*//*Label 2556*/ GIMT_Encode4(130750),
46375 /* 130256 */ /*GILLT_v8s16*//*Label 2557*/ GIMT_Encode4(130797),
46376 /* 130260 */ /*GILLT_v2s32*//*Label 2558*/ GIMT_Encode4(130844),
46377 /* 130264 */ /*GILLT_v4s32*//*Label 2559*/ GIMT_Encode4(130891),
46378 /* 130268 */ // Label 2554: @130268
46379 /* 130268 */ GIM_Try, /*On fail goto*//*Label 2561*/ GIMT_Encode4(130508), // Rule ID 3081 //
46380 /* 130273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
46381 /* 130276 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46382 /* 130279 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46383 /* 130282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46384 /* 130286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46385 /* 130290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46386 /* 130294 */ // (fmaximum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMAXhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
46387 /* 130294 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
46388 /* 130297 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46389 /* 130301 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46390 /* 130306 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
46391 /* 130308 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
46392 /* 130311 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46393 /* 130315 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46394 /* 130320 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
46395 /* 130323 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46396 /* 130328 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
46397 /* 130331 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46398 /* 130335 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46399 /* 130340 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
46400 /* 130343 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
46401 /* 130347 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
46402 /* 130350 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46403 /* 130355 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46404 /* 130360 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
46405 /* 130365 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
46406 /* 130368 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46407 /* 130372 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46408 /* 130377 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
46409 /* 130379 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
46410 /* 130382 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46411 /* 130386 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46412 /* 130391 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
46413 /* 130394 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46414 /* 130399 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
46415 /* 130402 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46416 /* 130406 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46417 /* 130411 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
46418 /* 130414 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
46419 /* 130418 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
46420 /* 130421 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46421 /* 130426 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46422 /* 130431 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
46423 /* 130436 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
46424 /* 130439 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXhd),
46425 /* 130443 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46426 /* 130448 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
46427 /* 130451 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
46428 /* 130454 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
46429 /* 130457 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46430 /* 130463 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46431 /* 130465 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
46432 /* 130468 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46433 /* 130472 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46434 /* 130477 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
46435 /* 130480 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46436 /* 130485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46437 /* 130488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46438 /* 130490 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
46439 /* 130497 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
46440 /* 130502 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46441 /* 130507 */ // GIR_Coverage, 3081,
46442 /* 130507 */ GIR_EraseRootFromParent_Done,
46443 /* 130508 */ // Label 2561: @130508
46444 /* 130508 */ GIM_Reject,
46445 /* 130509 */ // Label 2555: @130509
46446 /* 130509 */ GIM_Try, /*On fail goto*//*Label 2562*/ GIMT_Encode4(130749), // Rule ID 3083 //
46447 /* 130514 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46448 /* 130517 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46449 /* 130520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46450 /* 130523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46451 /* 130527 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46452 /* 130531 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46453 /* 130535 */ // (fmaximum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMAXfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
46454 /* 130535 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
46455 /* 130538 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46456 /* 130542 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46457 /* 130547 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
46458 /* 130549 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
46459 /* 130552 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46460 /* 130556 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46461 /* 130561 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
46462 /* 130564 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46463 /* 130569 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
46464 /* 130572 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46465 /* 130576 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46466 /* 130581 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
46467 /* 130584 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
46468 /* 130588 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
46469 /* 130591 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46470 /* 130596 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46471 /* 130601 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
46472 /* 130606 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
46473 /* 130609 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46474 /* 130613 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46475 /* 130618 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
46476 /* 130620 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
46477 /* 130623 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46478 /* 130627 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46479 /* 130632 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
46480 /* 130635 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46481 /* 130640 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
46482 /* 130643 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46483 /* 130647 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46484 /* 130652 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
46485 /* 130655 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
46486 /* 130659 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
46487 /* 130662 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46488 /* 130667 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46489 /* 130672 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
46490 /* 130677 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
46491 /* 130680 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXfd),
46492 /* 130684 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46493 /* 130689 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
46494 /* 130692 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
46495 /* 130695 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
46496 /* 130698 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46497 /* 130704 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46498 /* 130706 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
46499 /* 130709 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46500 /* 130713 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46501 /* 130718 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
46502 /* 130721 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46503 /* 130726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46504 /* 130729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46505 /* 130731 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
46506 /* 130738 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
46507 /* 130743 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46508 /* 130748 */ // GIR_Coverage, 3083,
46509 /* 130748 */ GIR_EraseRootFromParent_Done,
46510 /* 130749 */ // Label 2562: @130749
46511 /* 130749 */ GIM_Reject,
46512 /* 130750 */ // Label 2556: @130750
46513 /* 130750 */ GIM_Try, /*On fail goto*//*Label 2563*/ GIMT_Encode4(130796), // Rule ID 1373 //
46514 /* 130755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
46515 /* 130758 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
46516 /* 130761 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
46517 /* 130764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46518 /* 130768 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46519 /* 130772 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46520 /* 130776 */ // (fmaximum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMAXhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
46521 /* 130776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhd),
46522 /* 130779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46523 /* 130781 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46524 /* 130783 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46525 /* 130785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46526 /* 130788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46527 /* 130794 */ GIR_RootConstrainSelectedInstOperands,
46528 /* 130795 */ // GIR_Coverage, 1373,
46529 /* 130795 */ GIR_EraseRootFromParent_Done,
46530 /* 130796 */ // Label 2563: @130796
46531 /* 130796 */ GIM_Reject,
46532 /* 130797 */ // Label 2557: @130797
46533 /* 130797 */ GIM_Try, /*On fail goto*//*Label 2564*/ GIMT_Encode4(130843), // Rule ID 1374 //
46534 /* 130802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
46535 /* 130805 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
46536 /* 130808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
46537 /* 130811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46538 /* 130815 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46539 /* 130819 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46540 /* 130823 */ // (fmaximum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMAXhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
46541 /* 130823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhq),
46542 /* 130826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46543 /* 130828 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46544 /* 130830 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46545 /* 130832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46546 /* 130835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46547 /* 130841 */ GIR_RootConstrainSelectedInstOperands,
46548 /* 130842 */ // GIR_Coverage, 1374,
46549 /* 130842 */ GIR_EraseRootFromParent_Done,
46550 /* 130843 */ // Label 2564: @130843
46551 /* 130843 */ GIM_Reject,
46552 /* 130844 */ // Label 2558: @130844
46553 /* 130844 */ GIM_Try, /*On fail goto*//*Label 2565*/ GIMT_Encode4(130890), // Rule ID 1371 //
46554 /* 130849 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46555 /* 130852 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
46556 /* 130855 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
46557 /* 130858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46558 /* 130862 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46559 /* 130866 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46560 /* 130870 */ // (fmaximum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMAXfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
46561 /* 130870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfd),
46562 /* 130873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46563 /* 130875 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46564 /* 130877 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46565 /* 130879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46566 /* 130882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46567 /* 130888 */ GIR_RootConstrainSelectedInstOperands,
46568 /* 130889 */ // GIR_Coverage, 1371,
46569 /* 130889 */ GIR_EraseRootFromParent_Done,
46570 /* 130890 */ // Label 2565: @130890
46571 /* 130890 */ GIM_Reject,
46572 /* 130891 */ // Label 2559: @130891
46573 /* 130891 */ GIM_Try, /*On fail goto*//*Label 2566*/ GIMT_Encode4(130937), // Rule ID 1372 //
46574 /* 130896 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46575 /* 130899 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
46576 /* 130902 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
46577 /* 130905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46578 /* 130909 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46579 /* 130913 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46580 /* 130917 */ // (fmaximum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMAXfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
46581 /* 130917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfq),
46582 /* 130920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46583 /* 130922 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46584 /* 130924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46585 /* 130926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46586 /* 130929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46587 /* 130935 */ GIR_RootConstrainSelectedInstOperands,
46588 /* 130936 */ // GIR_Coverage, 1372,
46589 /* 130936 */ GIR_EraseRootFromParent_Done,
46590 /* 130937 */ // Label 2566: @130937
46591 /* 130937 */ GIM_Reject,
46592 /* 130938 */ // Label 2560: @130938
46593 /* 130938 */ GIM_Reject,
46594 /* 130939 */ // Label 57: @130939
46595 /* 130939 */ GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(130971), // Rule ID 2786 //
46596 /* 130944 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46597 /* 130947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
46598 /* 130951 */ // (get_fpenv:{ *:[i32] }) => (VMRS:{ *:[i32] })
46599 /* 130951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS),
46600 /* 130954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
46601 /* 130956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46602 /* 130959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46603 /* 130965 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
46604 /* 130969 */ GIR_RootConstrainSelectedInstOperands,
46605 /* 130970 */ // GIR_Coverage, 2786,
46606 /* 130970 */ GIR_EraseRootFromParent_Done,
46607 /* 130971 */ // Label 2567: @130971
46608 /* 130971 */ GIM_Reject,
46609 /* 130972 */ // Label 58: @130972
46610 /* 130972 */ GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(131007), // Rule ID 2787 //
46611 /* 130977 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46612 /* 130980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
46613 /* 130984 */ // (set_fpenv GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt)
46614 /* 130984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
46615 /* 130987 */ GIR_RootToRootCopy, /*OpIdx*/0, // Rt
46616 /* 130989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46617 /* 130992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46618 /* 130998 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
46619 /* 131001 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
46620 /* 131005 */ GIR_RootConstrainSelectedInstOperands,
46621 /* 131006 */ // GIR_Coverage, 2787,
46622 /* 131006 */ GIR_EraseRootFromParent_Done,
46623 /* 131007 */ // Label 2568: @131007
46624 /* 131007 */ GIM_Reject,
46625 /* 131008 */ // Label 59: @131008
46626 /* 131008 */ GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(131072), // Rule ID 2788 //
46627 /* 131013 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
46628 /* 131016 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (MOVi:{ *:[i32] } 0:{ *:[i32] }))
46629 /* 131016 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
46630 /* 131019 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MOVi),
46631 /* 131023 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46632 /* 131028 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
46633 /* 131031 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
46634 /* 131034 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46635 /* 131040 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46636 /* 131046 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
46637 /* 131048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
46638 /* 131051 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46639 /* 131054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46640 /* 131057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46641 /* 131063 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
46642 /* 131066 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
46643 /* 131070 */ GIR_RootConstrainSelectedInstOperands,
46644 /* 131071 */ // GIR_Coverage, 2788,
46645 /* 131071 */ GIR_EraseRootFromParent_Done,
46646 /* 131072 */ // Label 2569: @131072
46647 /* 131072 */ GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(131136), // Rule ID 2789 //
46648 /* 131077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb),
46649 /* 131080 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
46650 /* 131080 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
46651 /* 131083 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
46652 /* 131087 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46653 /* 131092 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
46654 /* 131098 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
46655 /* 131101 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
46656 /* 131104 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46657 /* 131110 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
46658 /* 131112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
46659 /* 131115 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46660 /* 131118 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46661 /* 131121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46662 /* 131127 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
46663 /* 131130 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
46664 /* 131134 */ GIR_RootConstrainSelectedInstOperands,
46665 /* 131135 */ // GIR_Coverage, 2789,
46666 /* 131135 */ GIR_EraseRootFromParent_Done,
46667 /* 131136 */ // Label 2570: @131136
46668 /* 131136 */ GIM_Reject,
46669 /* 131137 */ // Label 60: @131137
46670 /* 131137 */ GIM_Try, /*On fail goto*//*Label 2571*/ GIMT_Encode4(131169), // Rule ID 2790 //
46671 /* 131142 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46672 /* 131145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
46673 /* 131149 */ // (get_fpmode:{ *:[i32] }) => (VMRS:{ *:[i32] })
46674 /* 131149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS),
46675 /* 131152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
46676 /* 131154 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46677 /* 131157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46678 /* 131163 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
46679 /* 131167 */ GIR_RootConstrainSelectedInstOperands,
46680 /* 131168 */ // GIR_Coverage, 2790,
46681 /* 131168 */ GIR_EraseRootFromParent_Done,
46682 /* 131169 */ // Label 2571: @131169
46683 /* 131169 */ GIM_Reject,
46684 /* 131170 */ // Label 61: @131170
46685 /* 131170 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 2578*/ GIMT_Encode4(131688),
46686 /* 131181 */ /*GILLT_v8s8*//*Label 2572*/ GIMT_Encode4(131205),
46687 /* 131185 */ /*GILLT_v16s8*//*Label 2573*/ GIMT_Encode4(131252),
46688 /* 131189 */ /*GILLT_v4s16*//*Label 2574*/ GIMT_Encode4(131366),
46689 /* 131193 */ /*GILLT_v8s16*//*Label 2575*/ GIMT_Encode4(131413),
46690 /* 131197 */ /*GILLT_v2s32*//*Label 2576*/ GIMT_Encode4(131527),
46691 /* 131201 */ /*GILLT_v4s32*//*Label 2577*/ GIMT_Encode4(131574),
46692 /* 131205 */ // Label 2572: @131205
46693 /* 131205 */ GIM_Try, /*On fail goto*//*Label 2579*/ GIMT_Encode4(131251), // Rule ID 1383 //
46694 /* 131210 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46695 /* 131213 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
46696 /* 131216 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
46697 /* 131219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46698 /* 131223 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46699 /* 131227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46700 /* 131231 */ // (smin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
46701 /* 131231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i8),
46702 /* 131234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46703 /* 131236 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46704 /* 131238 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46705 /* 131240 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46706 /* 131243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46707 /* 131249 */ GIR_RootConstrainSelectedInstOperands,
46708 /* 131250 */ // GIR_Coverage, 1383,
46709 /* 131250 */ GIR_EraseRootFromParent_Done,
46710 /* 131251 */ // Label 2579: @131251
46711 /* 131251 */ GIM_Reject,
46712 /* 131252 */ // Label 2573: @131252
46713 /* 131252 */ GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(131365),
46714 /* 131257 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
46715 /* 131260 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
46716 /* 131263 */ GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(131303), // Rule ID 1384 //
46717 /* 131268 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46718 /* 131271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46719 /* 131275 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46720 /* 131279 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46721 /* 131283 */ // (smin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
46722 /* 131283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv16i8),
46723 /* 131286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46724 /* 131288 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46725 /* 131290 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46726 /* 131292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46727 /* 131295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46728 /* 131301 */ GIR_RootConstrainSelectedInstOperands,
46729 /* 131302 */ // GIR_Coverage, 1384,
46730 /* 131302 */ GIR_EraseRootFromParent_Done,
46731 /* 131303 */ // Label 2581: @131303
46732 /* 131303 */ GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(131364), // Rule ID 3677 //
46733 /* 131308 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46734 /* 131311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46735 /* 131315 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46736 /* 131319 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46737 /* 131323 */ // (smin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
46738 /* 131323 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46739 /* 131326 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46740 /* 131330 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46741 /* 131335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs8),
46742 /* 131338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46743 /* 131340 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
46744 /* 131342 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
46745 /* 131344 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46746 /* 131347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46747 /* 131353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46748 /* 131359 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46749 /* 131362 */ GIR_RootConstrainSelectedInstOperands,
46750 /* 131363 */ // GIR_Coverage, 3677,
46751 /* 131363 */ GIR_EraseRootFromParent_Done,
46752 /* 131364 */ // Label 2582: @131364
46753 /* 131364 */ GIM_Reject,
46754 /* 131365 */ // Label 2580: @131365
46755 /* 131365 */ GIM_Reject,
46756 /* 131366 */ // Label 2574: @131366
46757 /* 131366 */ GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(131412), // Rule ID 1379 //
46758 /* 131371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46759 /* 131374 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
46760 /* 131377 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
46761 /* 131380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46762 /* 131384 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46763 /* 131388 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46764 /* 131392 */ // (smin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
46765 /* 131392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i16),
46766 /* 131395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46767 /* 131397 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46768 /* 131399 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46769 /* 131401 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46770 /* 131404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46771 /* 131410 */ GIR_RootConstrainSelectedInstOperands,
46772 /* 131411 */ // GIR_Coverage, 1379,
46773 /* 131411 */ GIR_EraseRootFromParent_Done,
46774 /* 131412 */ // Label 2583: @131412
46775 /* 131412 */ GIM_Reject,
46776 /* 131413 */ // Label 2575: @131413
46777 /* 131413 */ GIM_Try, /*On fail goto*//*Label 2584*/ GIMT_Encode4(131526),
46778 /* 131418 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
46779 /* 131421 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
46780 /* 131424 */ GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(131464), // Rule ID 1381 //
46781 /* 131429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46782 /* 131432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46783 /* 131436 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46784 /* 131440 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46785 /* 131444 */ // (smin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
46786 /* 131444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i16),
46787 /* 131447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46788 /* 131449 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46789 /* 131451 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46790 /* 131453 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46791 /* 131456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46792 /* 131462 */ GIR_RootConstrainSelectedInstOperands,
46793 /* 131463 */ // GIR_Coverage, 1381,
46794 /* 131463 */ GIR_EraseRootFromParent_Done,
46795 /* 131464 */ // Label 2585: @131464
46796 /* 131464 */ GIM_Try, /*On fail goto*//*Label 2586*/ GIMT_Encode4(131525), // Rule ID 3680 //
46797 /* 131469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46798 /* 131472 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46799 /* 131476 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46800 /* 131480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46801 /* 131484 */ // (smin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
46802 /* 131484 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46803 /* 131487 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46804 /* 131491 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46805 /* 131496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs16),
46806 /* 131499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46807 /* 131501 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
46808 /* 131503 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
46809 /* 131505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46810 /* 131508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46811 /* 131514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46812 /* 131520 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46813 /* 131523 */ GIR_RootConstrainSelectedInstOperands,
46814 /* 131524 */ // GIR_Coverage, 3680,
46815 /* 131524 */ GIR_EraseRootFromParent_Done,
46816 /* 131525 */ // Label 2586: @131525
46817 /* 131525 */ GIM_Reject,
46818 /* 131526 */ // Label 2584: @131526
46819 /* 131526 */ GIM_Reject,
46820 /* 131527 */ // Label 2576: @131527
46821 /* 131527 */ GIM_Try, /*On fail goto*//*Label 2587*/ GIMT_Encode4(131573), // Rule ID 1380 //
46822 /* 131532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46823 /* 131535 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
46824 /* 131538 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
46825 /* 131541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46826 /* 131545 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46827 /* 131549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46828 /* 131553 */ // (smin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
46829 /* 131553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv2i32),
46830 /* 131556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46831 /* 131558 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46832 /* 131560 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46833 /* 131562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46834 /* 131565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46835 /* 131571 */ GIR_RootConstrainSelectedInstOperands,
46836 /* 131572 */ // GIR_Coverage, 1380,
46837 /* 131572 */ GIR_EraseRootFromParent_Done,
46838 /* 131573 */ // Label 2587: @131573
46839 /* 131573 */ GIM_Reject,
46840 /* 131574 */ // Label 2577: @131574
46841 /* 131574 */ GIM_Try, /*On fail goto*//*Label 2588*/ GIMT_Encode4(131687),
46842 /* 131579 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
46843 /* 131582 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
46844 /* 131585 */ GIM_Try, /*On fail goto*//*Label 2589*/ GIMT_Encode4(131625), // Rule ID 1382 //
46845 /* 131590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46846 /* 131593 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46847 /* 131597 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46848 /* 131601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46849 /* 131605 */ // (smin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
46850 /* 131605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i32),
46851 /* 131608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46852 /* 131610 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46853 /* 131612 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46854 /* 131614 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46855 /* 131617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46856 /* 131623 */ GIR_RootConstrainSelectedInstOperands,
46857 /* 131624 */ // GIR_Coverage, 1382,
46858 /* 131624 */ GIR_EraseRootFromParent_Done,
46859 /* 131625 */ // Label 2589: @131625
46860 /* 131625 */ GIM_Try, /*On fail goto*//*Label 2590*/ GIMT_Encode4(131686), // Rule ID 3683 //
46861 /* 131630 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46862 /* 131633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46863 /* 131637 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46864 /* 131641 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46865 /* 131645 */ // (smin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
46866 /* 131645 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46867 /* 131648 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46868 /* 131652 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46869 /* 131657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs32),
46870 /* 131660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46871 /* 131662 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
46872 /* 131664 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
46873 /* 131666 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46874 /* 131669 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46875 /* 131675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46876 /* 131681 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46877 /* 131684 */ GIR_RootConstrainSelectedInstOperands,
46878 /* 131685 */ // GIR_Coverage, 3683,
46879 /* 131685 */ GIR_EraseRootFromParent_Done,
46880 /* 131686 */ // Label 2590: @131686
46881 /* 131686 */ GIM_Reject,
46882 /* 131687 */ // Label 2588: @131687
46883 /* 131687 */ GIM_Reject,
46884 /* 131688 */ // Label 2578: @131688
46885 /* 131688 */ GIM_Reject,
46886 /* 131689 */ // Label 62: @131689
46887 /* 131689 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 2597*/ GIMT_Encode4(132207),
46888 /* 131700 */ /*GILLT_v8s8*//*Label 2591*/ GIMT_Encode4(131724),
46889 /* 131704 */ /*GILLT_v16s8*//*Label 2592*/ GIMT_Encode4(131771),
46890 /* 131708 */ /*GILLT_v4s16*//*Label 2593*/ GIMT_Encode4(131885),
46891 /* 131712 */ /*GILLT_v8s16*//*Label 2594*/ GIMT_Encode4(131932),
46892 /* 131716 */ /*GILLT_v2s32*//*Label 2595*/ GIMT_Encode4(132046),
46893 /* 131720 */ /*GILLT_v4s32*//*Label 2596*/ GIMT_Encode4(132093),
46894 /* 131724 */ // Label 2591: @131724
46895 /* 131724 */ GIM_Try, /*On fail goto*//*Label 2598*/ GIMT_Encode4(131770), // Rule ID 1363 //
46896 /* 131729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46897 /* 131732 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
46898 /* 131735 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
46899 /* 131738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46900 /* 131742 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46901 /* 131746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46902 /* 131750 */ // (smax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
46903 /* 131750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i8),
46904 /* 131753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46905 /* 131755 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46906 /* 131757 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46907 /* 131759 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46908 /* 131762 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46909 /* 131768 */ GIR_RootConstrainSelectedInstOperands,
46910 /* 131769 */ // GIR_Coverage, 1363,
46911 /* 131769 */ GIR_EraseRootFromParent_Done,
46912 /* 131770 */ // Label 2598: @131770
46913 /* 131770 */ GIM_Reject,
46914 /* 131771 */ // Label 2592: @131771
46915 /* 131771 */ GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(131884),
46916 /* 131776 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
46917 /* 131779 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
46918 /* 131782 */ GIM_Try, /*On fail goto*//*Label 2600*/ GIMT_Encode4(131822), // Rule ID 1364 //
46919 /* 131787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46920 /* 131790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46921 /* 131794 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46922 /* 131798 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46923 /* 131802 */ // (smax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
46924 /* 131802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv16i8),
46925 /* 131805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46926 /* 131807 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46927 /* 131809 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46928 /* 131811 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46929 /* 131814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46930 /* 131820 */ GIR_RootConstrainSelectedInstOperands,
46931 /* 131821 */ // GIR_Coverage, 1364,
46932 /* 131821 */ GIR_EraseRootFromParent_Done,
46933 /* 131822 */ // Label 2600: @131822
46934 /* 131822 */ GIM_Try, /*On fail goto*//*Label 2601*/ GIMT_Encode4(131883), // Rule ID 3695 //
46935 /* 131827 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46936 /* 131830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46937 /* 131834 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46938 /* 131838 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46939 /* 131842 */ // (smax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
46940 /* 131842 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46941 /* 131845 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46942 /* 131849 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46943 /* 131854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs8),
46944 /* 131857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46945 /* 131859 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
46946 /* 131861 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
46947 /* 131863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46948 /* 131866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46949 /* 131872 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46950 /* 131878 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46951 /* 131881 */ GIR_RootConstrainSelectedInstOperands,
46952 /* 131882 */ // GIR_Coverage, 3695,
46953 /* 131882 */ GIR_EraseRootFromParent_Done,
46954 /* 131883 */ // Label 2601: @131883
46955 /* 131883 */ GIM_Reject,
46956 /* 131884 */ // Label 2599: @131884
46957 /* 131884 */ GIM_Reject,
46958 /* 131885 */ // Label 2593: @131885
46959 /* 131885 */ GIM_Try, /*On fail goto*//*Label 2602*/ GIMT_Encode4(131931), // Rule ID 1359 //
46960 /* 131890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46961 /* 131893 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
46962 /* 131896 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
46963 /* 131899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46964 /* 131903 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46965 /* 131907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46966 /* 131911 */ // (smax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
46967 /* 131911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i16),
46968 /* 131914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46969 /* 131916 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46970 /* 131918 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46971 /* 131920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46972 /* 131923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46973 /* 131929 */ GIR_RootConstrainSelectedInstOperands,
46974 /* 131930 */ // GIR_Coverage, 1359,
46975 /* 131930 */ GIR_EraseRootFromParent_Done,
46976 /* 131931 */ // Label 2602: @131931
46977 /* 131931 */ GIM_Reject,
46978 /* 131932 */ // Label 2594: @131932
46979 /* 131932 */ GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(132045),
46980 /* 131937 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
46981 /* 131940 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
46982 /* 131943 */ GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(131983), // Rule ID 1361 //
46983 /* 131948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46984 /* 131951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46985 /* 131955 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46986 /* 131959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46987 /* 131963 */ // (smax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
46988 /* 131963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i16),
46989 /* 131966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46990 /* 131968 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46991 /* 131970 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46992 /* 131972 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46993 /* 131975 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46994 /* 131981 */ GIR_RootConstrainSelectedInstOperands,
46995 /* 131982 */ // GIR_Coverage, 1361,
46996 /* 131982 */ GIR_EraseRootFromParent_Done,
46997 /* 131983 */ // Label 2604: @131983
46998 /* 131983 */ GIM_Try, /*On fail goto*//*Label 2605*/ GIMT_Encode4(132044), // Rule ID 3698 //
46999 /* 131988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47000 /* 131991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47001 /* 131995 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47002 /* 131999 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47003 /* 132003 */ // (smax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
47004 /* 132003 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47005 /* 132006 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47006 /* 132010 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47007 /* 132015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs16),
47008 /* 132018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47009 /* 132020 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47010 /* 132022 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47011 /* 132024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47012 /* 132027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47013 /* 132033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47014 /* 132039 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47015 /* 132042 */ GIR_RootConstrainSelectedInstOperands,
47016 /* 132043 */ // GIR_Coverage, 3698,
47017 /* 132043 */ GIR_EraseRootFromParent_Done,
47018 /* 132044 */ // Label 2605: @132044
47019 /* 132044 */ GIM_Reject,
47020 /* 132045 */ // Label 2603: @132045
47021 /* 132045 */ GIM_Reject,
47022 /* 132046 */ // Label 2595: @132046
47023 /* 132046 */ GIM_Try, /*On fail goto*//*Label 2606*/ GIMT_Encode4(132092), // Rule ID 1360 //
47024 /* 132051 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47025 /* 132054 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
47026 /* 132057 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
47027 /* 132060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47028 /* 132064 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47029 /* 132068 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47030 /* 132072 */ // (smax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
47031 /* 132072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv2i32),
47032 /* 132075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47033 /* 132077 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47034 /* 132079 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47035 /* 132081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47036 /* 132084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47037 /* 132090 */ GIR_RootConstrainSelectedInstOperands,
47038 /* 132091 */ // GIR_Coverage, 1360,
47039 /* 132091 */ GIR_EraseRootFromParent_Done,
47040 /* 132092 */ // Label 2606: @132092
47041 /* 132092 */ GIM_Reject,
47042 /* 132093 */ // Label 2596: @132093
47043 /* 132093 */ GIM_Try, /*On fail goto*//*Label 2607*/ GIMT_Encode4(132206),
47044 /* 132098 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
47045 /* 132101 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
47046 /* 132104 */ GIM_Try, /*On fail goto*//*Label 2608*/ GIMT_Encode4(132144), // Rule ID 1362 //
47047 /* 132109 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47048 /* 132112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47049 /* 132116 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47050 /* 132120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47051 /* 132124 */ // (smax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
47052 /* 132124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i32),
47053 /* 132127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47054 /* 132129 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47055 /* 132131 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47056 /* 132133 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47057 /* 132136 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47058 /* 132142 */ GIR_RootConstrainSelectedInstOperands,
47059 /* 132143 */ // GIR_Coverage, 1362,
47060 /* 132143 */ GIR_EraseRootFromParent_Done,
47061 /* 132144 */ // Label 2608: @132144
47062 /* 132144 */ GIM_Try, /*On fail goto*//*Label 2609*/ GIMT_Encode4(132205), // Rule ID 3701 //
47063 /* 132149 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47064 /* 132152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47065 /* 132156 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47066 /* 132160 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47067 /* 132164 */ // (smax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
47068 /* 132164 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47069 /* 132167 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47070 /* 132171 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47071 /* 132176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs32),
47072 /* 132179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47073 /* 132181 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47074 /* 132183 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47075 /* 132185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47076 /* 132188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47077 /* 132194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47078 /* 132200 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47079 /* 132203 */ GIR_RootConstrainSelectedInstOperands,
47080 /* 132204 */ // GIR_Coverage, 3701,
47081 /* 132204 */ GIR_EraseRootFromParent_Done,
47082 /* 132205 */ // Label 2609: @132205
47083 /* 132205 */ GIM_Reject,
47084 /* 132206 */ // Label 2607: @132206
47085 /* 132206 */ GIM_Reject,
47086 /* 132207 */ // Label 2597: @132207
47087 /* 132207 */ GIM_Reject,
47088 /* 132208 */ // Label 63: @132208
47089 /* 132208 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 2616*/ GIMT_Encode4(133104),
47090 /* 132219 */ /*GILLT_v8s8*//*Label 2610*/ GIMT_Encode4(132243),
47091 /* 132223 */ /*GILLT_v16s8*//*Label 2611*/ GIMT_Encode4(132290),
47092 /* 132227 */ /*GILLT_v4s16*//*Label 2612*/ GIMT_Encode4(132530),
47093 /* 132231 */ /*GILLT_v8s16*//*Label 2613*/ GIMT_Encode4(132577),
47094 /* 132235 */ /*GILLT_v2s32*//*Label 2614*/ GIMT_Encode4(132817),
47095 /* 132239 */ /*GILLT_v4s32*//*Label 2615*/ GIMT_Encode4(132864),
47096 /* 132243 */ // Label 2610: @132243
47097 /* 132243 */ GIM_Try, /*On fail goto*//*Label 2617*/ GIMT_Encode4(132289), // Rule ID 1389 //
47098 /* 132248 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47099 /* 132251 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
47100 /* 132254 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
47101 /* 132257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47102 /* 132261 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47103 /* 132265 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47104 /* 132269 */ // (umin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
47105 /* 132269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i8),
47106 /* 132272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47107 /* 132274 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47108 /* 132276 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47109 /* 132278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47110 /* 132281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47111 /* 132287 */ GIR_RootConstrainSelectedInstOperands,
47112 /* 132288 */ // GIR_Coverage, 1389,
47113 /* 132288 */ GIR_EraseRootFromParent_Done,
47114 /* 132289 */ // Label 2617: @132289
47115 /* 132289 */ GIM_Reject,
47116 /* 132290 */ // Label 2611: @132290
47117 /* 132290 */ GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(132529),
47118 /* 132295 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
47119 /* 132298 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
47120 /* 132301 */ GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(132364), // Rule ID 6633 //
47121 /* 132306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47122 /* 132309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47123 /* 132313 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47124 /* 132317 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47125 /* 132321 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
47126 /* 132325 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47127 /* 132330 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47128 /* 132334 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47129 /* 132336 */ // (umin:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
47130 /* 132336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8),
47131 /* 132339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47132 /* 132341 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
47133 /* 132343 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47134 /* 132347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47135 /* 132350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47136 /* 132356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47137 /* 132362 */ GIR_RootConstrainSelectedInstOperands,
47138 /* 132363 */ // GIR_Coverage, 6633,
47139 /* 132363 */ GIR_EraseRootFromParent_Done,
47140 /* 132364 */ // Label 2619: @132364
47141 /* 132364 */ GIM_Try, /*On fail goto*//*Label 2620*/ GIMT_Encode4(132427), // Rule ID 4076 //
47142 /* 132369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47143 /* 132372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47144 /* 132376 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47145 /* 132380 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47146 /* 132384 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47147 /* 132388 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
47148 /* 132392 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47149 /* 132397 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47150 /* 132399 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
47151 /* 132399 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8),
47152 /* 132402 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47153 /* 132404 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
47154 /* 132406 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47155 /* 132410 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47156 /* 132413 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47157 /* 132419 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47158 /* 132425 */ GIR_RootConstrainSelectedInstOperands,
47159 /* 132426 */ // GIR_Coverage, 4076,
47160 /* 132426 */ GIR_EraseRootFromParent_Done,
47161 /* 132427 */ // Label 2620: @132427
47162 /* 132427 */ GIM_Try, /*On fail goto*//*Label 2621*/ GIMT_Encode4(132467), // Rule ID 1390 //
47163 /* 132432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47164 /* 132435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47165 /* 132439 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47166 /* 132443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47167 /* 132447 */ // (umin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
47168 /* 132447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv16i8),
47169 /* 132450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47170 /* 132452 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47171 /* 132454 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47172 /* 132456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47173 /* 132459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47174 /* 132465 */ GIR_RootConstrainSelectedInstOperands,
47175 /* 132466 */ // GIR_Coverage, 1390,
47176 /* 132466 */ GIR_EraseRootFromParent_Done,
47177 /* 132467 */ // Label 2621: @132467
47178 /* 132467 */ GIM_Try, /*On fail goto*//*Label 2622*/ GIMT_Encode4(132528), // Rule ID 3686 //
47179 /* 132472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47180 /* 132475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47181 /* 132479 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47182 /* 132483 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47183 /* 132487 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
47184 /* 132487 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47185 /* 132490 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47186 /* 132494 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47187 /* 132499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu8),
47188 /* 132502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47189 /* 132504 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47190 /* 132506 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47191 /* 132508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47192 /* 132511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47193 /* 132517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47194 /* 132523 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47195 /* 132526 */ GIR_RootConstrainSelectedInstOperands,
47196 /* 132527 */ // GIR_Coverage, 3686,
47197 /* 132527 */ GIR_EraseRootFromParent_Done,
47198 /* 132528 */ // Label 2622: @132528
47199 /* 132528 */ GIM_Reject,
47200 /* 132529 */ // Label 2618: @132529
47201 /* 132529 */ GIM_Reject,
47202 /* 132530 */ // Label 2612: @132530
47203 /* 132530 */ GIM_Try, /*On fail goto*//*Label 2623*/ GIMT_Encode4(132576), // Rule ID 1385 //
47204 /* 132535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47205 /* 132538 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
47206 /* 132541 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
47207 /* 132544 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47208 /* 132548 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47209 /* 132552 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47210 /* 132556 */ // (umin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
47211 /* 132556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i16),
47212 /* 132559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47213 /* 132561 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47214 /* 132563 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47215 /* 132565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47216 /* 132568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47217 /* 132574 */ GIR_RootConstrainSelectedInstOperands,
47218 /* 132575 */ // GIR_Coverage, 1385,
47219 /* 132575 */ GIR_EraseRootFromParent_Done,
47220 /* 132576 */ // Label 2623: @132576
47221 /* 132576 */ GIM_Reject,
47222 /* 132577 */ // Label 2613: @132577
47223 /* 132577 */ GIM_Try, /*On fail goto*//*Label 2624*/ GIMT_Encode4(132816),
47224 /* 132582 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
47225 /* 132585 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
47226 /* 132588 */ GIM_Try, /*On fail goto*//*Label 2625*/ GIMT_Encode4(132651), // Rule ID 6634 //
47227 /* 132593 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47228 /* 132596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47229 /* 132600 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47230 /* 132604 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47231 /* 132608 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47232 /* 132612 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47233 /* 132617 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47234 /* 132621 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47235 /* 132623 */ // (umin:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
47236 /* 132623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16),
47237 /* 132626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47238 /* 132628 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
47239 /* 132630 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47240 /* 132634 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47241 /* 132637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47242 /* 132643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47243 /* 132649 */ GIR_RootConstrainSelectedInstOperands,
47244 /* 132650 */ // GIR_Coverage, 6634,
47245 /* 132650 */ GIR_EraseRootFromParent_Done,
47246 /* 132651 */ // Label 2625: @132651
47247 /* 132651 */ GIM_Try, /*On fail goto*//*Label 2626*/ GIMT_Encode4(132714), // Rule ID 4078 //
47248 /* 132656 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47249 /* 132659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47250 /* 132663 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47251 /* 132667 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47252 /* 132671 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47253 /* 132675 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47254 /* 132679 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47255 /* 132684 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47256 /* 132686 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
47257 /* 132686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16),
47258 /* 132689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47259 /* 132691 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
47260 /* 132693 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47261 /* 132697 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47262 /* 132700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47263 /* 132706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47264 /* 132712 */ GIR_RootConstrainSelectedInstOperands,
47265 /* 132713 */ // GIR_Coverage, 4078,
47266 /* 132713 */ GIR_EraseRootFromParent_Done,
47267 /* 132714 */ // Label 2626: @132714
47268 /* 132714 */ GIM_Try, /*On fail goto*//*Label 2627*/ GIMT_Encode4(132754), // Rule ID 1387 //
47269 /* 132719 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47270 /* 132722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47271 /* 132726 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47272 /* 132730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47273 /* 132734 */ // (umin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
47274 /* 132734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i16),
47275 /* 132737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47276 /* 132739 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47277 /* 132741 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47278 /* 132743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47279 /* 132746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47280 /* 132752 */ GIR_RootConstrainSelectedInstOperands,
47281 /* 132753 */ // GIR_Coverage, 1387,
47282 /* 132753 */ GIR_EraseRootFromParent_Done,
47283 /* 132754 */ // Label 2627: @132754
47284 /* 132754 */ GIM_Try, /*On fail goto*//*Label 2628*/ GIMT_Encode4(132815), // Rule ID 3689 //
47285 /* 132759 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47286 /* 132762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47287 /* 132766 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47288 /* 132770 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47289 /* 132774 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
47290 /* 132774 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47291 /* 132777 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47292 /* 132781 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47293 /* 132786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu16),
47294 /* 132789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47295 /* 132791 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47296 /* 132793 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47297 /* 132795 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47298 /* 132798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47299 /* 132804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47300 /* 132810 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47301 /* 132813 */ GIR_RootConstrainSelectedInstOperands,
47302 /* 132814 */ // GIR_Coverage, 3689,
47303 /* 132814 */ GIR_EraseRootFromParent_Done,
47304 /* 132815 */ // Label 2628: @132815
47305 /* 132815 */ GIM_Reject,
47306 /* 132816 */ // Label 2624: @132816
47307 /* 132816 */ GIM_Reject,
47308 /* 132817 */ // Label 2614: @132817
47309 /* 132817 */ GIM_Try, /*On fail goto*//*Label 2629*/ GIMT_Encode4(132863), // Rule ID 1386 //
47310 /* 132822 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47311 /* 132825 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
47312 /* 132828 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
47313 /* 132831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47314 /* 132835 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47315 /* 132839 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47316 /* 132843 */ // (umin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
47317 /* 132843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv2i32),
47318 /* 132846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47319 /* 132848 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47320 /* 132850 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47321 /* 132852 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47322 /* 132855 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47323 /* 132861 */ GIR_RootConstrainSelectedInstOperands,
47324 /* 132862 */ // GIR_Coverage, 1386,
47325 /* 132862 */ GIR_EraseRootFromParent_Done,
47326 /* 132863 */ // Label 2629: @132863
47327 /* 132863 */ GIM_Reject,
47328 /* 132864 */ // Label 2615: @132864
47329 /* 132864 */ GIM_Try, /*On fail goto*//*Label 2630*/ GIMT_Encode4(133103),
47330 /* 132869 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
47331 /* 132872 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
47332 /* 132875 */ GIM_Try, /*On fail goto*//*Label 2631*/ GIMT_Encode4(132938), // Rule ID 6635 //
47333 /* 132880 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47334 /* 132883 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47335 /* 132887 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47336 /* 132891 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47337 /* 132895 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47338 /* 132899 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47339 /* 132904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47340 /* 132908 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47341 /* 132910 */ // (umin:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
47342 /* 132910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32),
47343 /* 132913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47344 /* 132915 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
47345 /* 132917 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47346 /* 132921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47347 /* 132924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47348 /* 132930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47349 /* 132936 */ GIR_RootConstrainSelectedInstOperands,
47350 /* 132937 */ // GIR_Coverage, 6635,
47351 /* 132937 */ GIR_EraseRootFromParent_Done,
47352 /* 132938 */ // Label 2631: @132938
47353 /* 132938 */ GIM_Try, /*On fail goto*//*Label 2632*/ GIMT_Encode4(133001), // Rule ID 4080 //
47354 /* 132943 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47355 /* 132946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47356 /* 132950 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47357 /* 132954 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47358 /* 132958 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47359 /* 132962 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47360 /* 132966 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47361 /* 132971 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47362 /* 132973 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
47363 /* 132973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32),
47364 /* 132976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47365 /* 132978 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
47366 /* 132980 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47367 /* 132984 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47368 /* 132987 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47369 /* 132993 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47370 /* 132999 */ GIR_RootConstrainSelectedInstOperands,
47371 /* 133000 */ // GIR_Coverage, 4080,
47372 /* 133000 */ GIR_EraseRootFromParent_Done,
47373 /* 133001 */ // Label 2632: @133001
47374 /* 133001 */ GIM_Try, /*On fail goto*//*Label 2633*/ GIMT_Encode4(133041), // Rule ID 1388 //
47375 /* 133006 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47376 /* 133009 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47377 /* 133013 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47378 /* 133017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47379 /* 133021 */ // (umin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
47380 /* 133021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i32),
47381 /* 133024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47382 /* 133026 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47383 /* 133028 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47384 /* 133030 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47385 /* 133033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47386 /* 133039 */ GIR_RootConstrainSelectedInstOperands,
47387 /* 133040 */ // GIR_Coverage, 1388,
47388 /* 133040 */ GIR_EraseRootFromParent_Done,
47389 /* 133041 */ // Label 2633: @133041
47390 /* 133041 */ GIM_Try, /*On fail goto*//*Label 2634*/ GIMT_Encode4(133102), // Rule ID 3692 //
47391 /* 133046 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47392 /* 133049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47393 /* 133053 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47394 /* 133057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47395 /* 133061 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
47396 /* 133061 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47397 /* 133064 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47398 /* 133068 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47399 /* 133073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu32),
47400 /* 133076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47401 /* 133078 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47402 /* 133080 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47403 /* 133082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47404 /* 133085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47405 /* 133091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47406 /* 133097 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47407 /* 133100 */ GIR_RootConstrainSelectedInstOperands,
47408 /* 133101 */ // GIR_Coverage, 3692,
47409 /* 133101 */ GIR_EraseRootFromParent_Done,
47410 /* 133102 */ // Label 2634: @133102
47411 /* 133102 */ GIM_Reject,
47412 /* 133103 */ // Label 2630: @133103
47413 /* 133103 */ GIM_Reject,
47414 /* 133104 */ // Label 2616: @133104
47415 /* 133104 */ GIM_Reject,
47416 /* 133105 */ // Label 64: @133105
47417 /* 133105 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 2641*/ GIMT_Encode4(134001),
47418 /* 133116 */ /*GILLT_v8s8*//*Label 2635*/ GIMT_Encode4(133140),
47419 /* 133120 */ /*GILLT_v16s8*//*Label 2636*/ GIMT_Encode4(133187),
47420 /* 133124 */ /*GILLT_v4s16*//*Label 2637*/ GIMT_Encode4(133427),
47421 /* 133128 */ /*GILLT_v8s16*//*Label 2638*/ GIMT_Encode4(133474),
47422 /* 133132 */ /*GILLT_v2s32*//*Label 2639*/ GIMT_Encode4(133714),
47423 /* 133136 */ /*GILLT_v4s32*//*Label 2640*/ GIMT_Encode4(133761),
47424 /* 133140 */ // Label 2635: @133140
47425 /* 133140 */ GIM_Try, /*On fail goto*//*Label 2642*/ GIMT_Encode4(133186), // Rule ID 1369 //
47426 /* 133145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47427 /* 133148 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
47428 /* 133151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
47429 /* 133154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47430 /* 133158 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47431 /* 133162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47432 /* 133166 */ // (umax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
47433 /* 133166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i8),
47434 /* 133169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47435 /* 133171 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47436 /* 133173 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47437 /* 133175 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47438 /* 133178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47439 /* 133184 */ GIR_RootConstrainSelectedInstOperands,
47440 /* 133185 */ // GIR_Coverage, 1369,
47441 /* 133185 */ GIR_EraseRootFromParent_Done,
47442 /* 133186 */ // Label 2642: @133186
47443 /* 133186 */ GIM_Reject,
47444 /* 133187 */ // Label 2636: @133187
47445 /* 133187 */ GIM_Try, /*On fail goto*//*Label 2643*/ GIMT_Encode4(133426),
47446 /* 133192 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
47447 /* 133195 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
47448 /* 133198 */ GIM_Try, /*On fail goto*//*Label 2644*/ GIMT_Encode4(133261), // Rule ID 6636 //
47449 /* 133203 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47450 /* 133206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47451 /* 133210 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47452 /* 133214 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47453 /* 133218 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
47454 /* 133222 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47455 /* 133227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47456 /* 133231 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47457 /* 133233 */ // (umax:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
47458 /* 133233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8),
47459 /* 133236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47460 /* 133238 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
47461 /* 133240 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47462 /* 133244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47463 /* 133247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47464 /* 133253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47465 /* 133259 */ GIR_RootConstrainSelectedInstOperands,
47466 /* 133260 */ // GIR_Coverage, 6636,
47467 /* 133260 */ GIR_EraseRootFromParent_Done,
47468 /* 133261 */ // Label 2644: @133261
47469 /* 133261 */ GIM_Try, /*On fail goto*//*Label 2645*/ GIMT_Encode4(133324), // Rule ID 4082 //
47470 /* 133266 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47471 /* 133269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47472 /* 133273 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47473 /* 133277 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47474 /* 133281 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47475 /* 133285 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
47476 /* 133289 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47477 /* 133294 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47478 /* 133296 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
47479 /* 133296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8),
47480 /* 133299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47481 /* 133301 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
47482 /* 133303 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47483 /* 133307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47484 /* 133310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47485 /* 133316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47486 /* 133322 */ GIR_RootConstrainSelectedInstOperands,
47487 /* 133323 */ // GIR_Coverage, 4082,
47488 /* 133323 */ GIR_EraseRootFromParent_Done,
47489 /* 133324 */ // Label 2645: @133324
47490 /* 133324 */ GIM_Try, /*On fail goto*//*Label 2646*/ GIMT_Encode4(133364), // Rule ID 1370 //
47491 /* 133329 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47492 /* 133332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47493 /* 133336 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47494 /* 133340 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47495 /* 133344 */ // (umax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
47496 /* 133344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv16i8),
47497 /* 133347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47498 /* 133349 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47499 /* 133351 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47500 /* 133353 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47501 /* 133356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47502 /* 133362 */ GIR_RootConstrainSelectedInstOperands,
47503 /* 133363 */ // GIR_Coverage, 1370,
47504 /* 133363 */ GIR_EraseRootFromParent_Done,
47505 /* 133364 */ // Label 2646: @133364
47506 /* 133364 */ GIM_Try, /*On fail goto*//*Label 2647*/ GIMT_Encode4(133425), // Rule ID 3704 //
47507 /* 133369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47508 /* 133372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47509 /* 133376 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47510 /* 133380 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47511 /* 133384 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
47512 /* 133384 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47513 /* 133387 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47514 /* 133391 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47515 /* 133396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu8),
47516 /* 133399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47517 /* 133401 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47518 /* 133403 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47519 /* 133405 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47520 /* 133408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47521 /* 133414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47522 /* 133420 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47523 /* 133423 */ GIR_RootConstrainSelectedInstOperands,
47524 /* 133424 */ // GIR_Coverage, 3704,
47525 /* 133424 */ GIR_EraseRootFromParent_Done,
47526 /* 133425 */ // Label 2647: @133425
47527 /* 133425 */ GIM_Reject,
47528 /* 133426 */ // Label 2643: @133426
47529 /* 133426 */ GIM_Reject,
47530 /* 133427 */ // Label 2637: @133427
47531 /* 133427 */ GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(133473), // Rule ID 1365 //
47532 /* 133432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47533 /* 133435 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
47534 /* 133438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
47535 /* 133441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47536 /* 133445 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47537 /* 133449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47538 /* 133453 */ // (umax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
47539 /* 133453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i16),
47540 /* 133456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47541 /* 133458 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47542 /* 133460 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47543 /* 133462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47544 /* 133465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47545 /* 133471 */ GIR_RootConstrainSelectedInstOperands,
47546 /* 133472 */ // GIR_Coverage, 1365,
47547 /* 133472 */ GIR_EraseRootFromParent_Done,
47548 /* 133473 */ // Label 2648: @133473
47549 /* 133473 */ GIM_Reject,
47550 /* 133474 */ // Label 2638: @133474
47551 /* 133474 */ GIM_Try, /*On fail goto*//*Label 2649*/ GIMT_Encode4(133713),
47552 /* 133479 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
47553 /* 133482 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
47554 /* 133485 */ GIM_Try, /*On fail goto*//*Label 2650*/ GIMT_Encode4(133548), // Rule ID 6637 //
47555 /* 133490 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47556 /* 133493 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47557 /* 133497 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47558 /* 133501 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47559 /* 133505 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47560 /* 133509 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47561 /* 133514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47562 /* 133518 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47563 /* 133520 */ // (umax:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
47564 /* 133520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16),
47565 /* 133523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47566 /* 133525 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
47567 /* 133527 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47568 /* 133531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47569 /* 133534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47570 /* 133540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47571 /* 133546 */ GIR_RootConstrainSelectedInstOperands,
47572 /* 133547 */ // GIR_Coverage, 6637,
47573 /* 133547 */ GIR_EraseRootFromParent_Done,
47574 /* 133548 */ // Label 2650: @133548
47575 /* 133548 */ GIM_Try, /*On fail goto*//*Label 2651*/ GIMT_Encode4(133611), // Rule ID 4084 //
47576 /* 133553 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47577 /* 133556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47578 /* 133560 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47579 /* 133564 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47580 /* 133568 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47581 /* 133572 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47582 /* 133576 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47583 /* 133581 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47584 /* 133583 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
47585 /* 133583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16),
47586 /* 133586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47587 /* 133588 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
47588 /* 133590 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47589 /* 133594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47590 /* 133597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47591 /* 133603 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47592 /* 133609 */ GIR_RootConstrainSelectedInstOperands,
47593 /* 133610 */ // GIR_Coverage, 4084,
47594 /* 133610 */ GIR_EraseRootFromParent_Done,
47595 /* 133611 */ // Label 2651: @133611
47596 /* 133611 */ GIM_Try, /*On fail goto*//*Label 2652*/ GIMT_Encode4(133651), // Rule ID 1367 //
47597 /* 133616 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47598 /* 133619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47599 /* 133623 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47600 /* 133627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47601 /* 133631 */ // (umax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
47602 /* 133631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i16),
47603 /* 133634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47604 /* 133636 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47605 /* 133638 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47606 /* 133640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47607 /* 133643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47608 /* 133649 */ GIR_RootConstrainSelectedInstOperands,
47609 /* 133650 */ // GIR_Coverage, 1367,
47610 /* 133650 */ GIR_EraseRootFromParent_Done,
47611 /* 133651 */ // Label 2652: @133651
47612 /* 133651 */ GIM_Try, /*On fail goto*//*Label 2653*/ GIMT_Encode4(133712), // Rule ID 3707 //
47613 /* 133656 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47614 /* 133659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47615 /* 133663 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47616 /* 133667 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47617 /* 133671 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
47618 /* 133671 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47619 /* 133674 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47620 /* 133678 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47621 /* 133683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu16),
47622 /* 133686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47623 /* 133688 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47624 /* 133690 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47625 /* 133692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47626 /* 133695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47627 /* 133701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47628 /* 133707 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47629 /* 133710 */ GIR_RootConstrainSelectedInstOperands,
47630 /* 133711 */ // GIR_Coverage, 3707,
47631 /* 133711 */ GIR_EraseRootFromParent_Done,
47632 /* 133712 */ // Label 2653: @133712
47633 /* 133712 */ GIM_Reject,
47634 /* 133713 */ // Label 2649: @133713
47635 /* 133713 */ GIM_Reject,
47636 /* 133714 */ // Label 2639: @133714
47637 /* 133714 */ GIM_Try, /*On fail goto*//*Label 2654*/ GIMT_Encode4(133760), // Rule ID 1366 //
47638 /* 133719 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47639 /* 133722 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
47640 /* 133725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
47641 /* 133728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47642 /* 133732 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47643 /* 133736 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47644 /* 133740 */ // (umax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
47645 /* 133740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv2i32),
47646 /* 133743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47647 /* 133745 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47648 /* 133747 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47649 /* 133749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47650 /* 133752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47651 /* 133758 */ GIR_RootConstrainSelectedInstOperands,
47652 /* 133759 */ // GIR_Coverage, 1366,
47653 /* 133759 */ GIR_EraseRootFromParent_Done,
47654 /* 133760 */ // Label 2654: @133760
47655 /* 133760 */ GIM_Reject,
47656 /* 133761 */ // Label 2640: @133761
47657 /* 133761 */ GIM_Try, /*On fail goto*//*Label 2655*/ GIMT_Encode4(134000),
47658 /* 133766 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
47659 /* 133769 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
47660 /* 133772 */ GIM_Try, /*On fail goto*//*Label 2656*/ GIMT_Encode4(133835), // Rule ID 6638 //
47661 /* 133777 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47662 /* 133780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47663 /* 133784 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47664 /* 133788 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47665 /* 133792 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47666 /* 133796 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47667 /* 133801 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47668 /* 133805 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47669 /* 133807 */ // (umax:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
47670 /* 133807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32),
47671 /* 133810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47672 /* 133812 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
47673 /* 133814 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47674 /* 133818 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47675 /* 133821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47676 /* 133827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47677 /* 133833 */ GIR_RootConstrainSelectedInstOperands,
47678 /* 133834 */ // GIR_Coverage, 6638,
47679 /* 133834 */ GIR_EraseRootFromParent_Done,
47680 /* 133835 */ // Label 2656: @133835
47681 /* 133835 */ GIM_Try, /*On fail goto*//*Label 2657*/ GIMT_Encode4(133898), // Rule ID 4086 //
47682 /* 133840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47683 /* 133843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47684 /* 133847 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47685 /* 133851 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47686 /* 133855 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47687 /* 133859 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47688 /* 133863 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47689 /* 133868 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47690 /* 133870 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
47691 /* 133870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32),
47692 /* 133873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47693 /* 133875 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
47694 /* 133877 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47695 /* 133881 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47696 /* 133884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47697 /* 133890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47698 /* 133896 */ GIR_RootConstrainSelectedInstOperands,
47699 /* 133897 */ // GIR_Coverage, 4086,
47700 /* 133897 */ GIR_EraseRootFromParent_Done,
47701 /* 133898 */ // Label 2657: @133898
47702 /* 133898 */ GIM_Try, /*On fail goto*//*Label 2658*/ GIMT_Encode4(133938), // Rule ID 1368 //
47703 /* 133903 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47704 /* 133906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47705 /* 133910 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47706 /* 133914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47707 /* 133918 */ // (umax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
47708 /* 133918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i32),
47709 /* 133921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47710 /* 133923 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47711 /* 133925 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47712 /* 133927 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47713 /* 133930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47714 /* 133936 */ GIR_RootConstrainSelectedInstOperands,
47715 /* 133937 */ // GIR_Coverage, 1368,
47716 /* 133937 */ GIR_EraseRootFromParent_Done,
47717 /* 133938 */ // Label 2658: @133938
47718 /* 133938 */ GIM_Try, /*On fail goto*//*Label 2659*/ GIMT_Encode4(133999), // Rule ID 3710 //
47719 /* 133943 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47720 /* 133946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47721 /* 133950 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47722 /* 133954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47723 /* 133958 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
47724 /* 133958 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47725 /* 133961 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47726 /* 133965 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47727 /* 133970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu32),
47728 /* 133973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47729 /* 133975 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47730 /* 133977 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47731 /* 133979 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47732 /* 133982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47733 /* 133988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47734 /* 133994 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47735 /* 133997 */ GIR_RootConstrainSelectedInstOperands,
47736 /* 133998 */ // GIR_Coverage, 3710,
47737 /* 133998 */ GIR_EraseRootFromParent_Done,
47738 /* 133999 */ // Label 2659: @133999
47739 /* 133999 */ GIM_Reject,
47740 /* 134000 */ // Label 2655: @134000
47741 /* 134000 */ GIM_Reject,
47742 /* 134001 */ // Label 2641: @134001
47743 /* 134001 */ GIM_Reject,
47744 /* 134002 */ // Label 65: @134002
47745 /* 134002 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 2666*/ GIMT_Encode4(134448),
47746 /* 134013 */ /*GILLT_v8s8*//*Label 2660*/ GIMT_Encode4(134037),
47747 /* 134017 */ /*GILLT_v16s8*//*Label 2661*/ GIMT_Encode4(134075),
47748 /* 134021 */ /*GILLT_v4s16*//*Label 2662*/ GIMT_Encode4(134174),
47749 /* 134025 */ /*GILLT_v8s16*//*Label 2663*/ GIMT_Encode4(134212),
47750 /* 134029 */ /*GILLT_v2s32*//*Label 2664*/ GIMT_Encode4(134311),
47751 /* 134033 */ /*GILLT_v4s32*//*Label 2665*/ GIMT_Encode4(134349),
47752 /* 134037 */ // Label 2660: @134037
47753 /* 134037 */ GIM_Try, /*On fail goto*//*Label 2667*/ GIMT_Encode4(134074), // Rule ID 1670 //
47754 /* 134042 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47755 /* 134045 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
47756 /* 134048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47757 /* 134052 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47758 /* 134056 */ // (abs:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
47759 /* 134056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i8),
47760 /* 134059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47761 /* 134061 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
47762 /* 134063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47763 /* 134066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47764 /* 134072 */ GIR_RootConstrainSelectedInstOperands,
47765 /* 134073 */ // GIR_Coverage, 1670,
47766 /* 134073 */ GIR_EraseRootFromParent_Done,
47767 /* 134074 */ // Label 2667: @134074
47768 /* 134074 */ GIM_Reject,
47769 /* 134075 */ // Label 2661: @134075
47770 /* 134075 */ GIM_Try, /*On fail goto*//*Label 2668*/ GIMT_Encode4(134173),
47771 /* 134080 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
47772 /* 134083 */ GIM_Try, /*On fail goto*//*Label 2669*/ GIMT_Encode4(134117), // Rule ID 1673 //
47773 /* 134088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47774 /* 134091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47775 /* 134095 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47776 /* 134099 */ // (abs:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
47777 /* 134099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv16i8),
47778 /* 134102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47779 /* 134104 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
47780 /* 134106 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47781 /* 134109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47782 /* 134115 */ GIR_RootConstrainSelectedInstOperands,
47783 /* 134116 */ // GIR_Coverage, 1673,
47784 /* 134116 */ GIR_EraseRootFromParent_Done,
47785 /* 134117 */ // Label 2669: @134117
47786 /* 134117 */ GIM_Try, /*On fail goto*//*Label 2670*/ GIMT_Encode4(134172), // Rule ID 4043 //
47787 /* 134122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47788 /* 134125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47789 /* 134129 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47790 /* 134133 */ // (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v) => (MVE_VABSs8:{ *:[v16i8] } ?:{ *:[v16i8] }:$v)
47791 /* 134133 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47792 /* 134136 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47793 /* 134140 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47794 /* 134145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs8),
47795 /* 134148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47796 /* 134150 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
47797 /* 134152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47798 /* 134155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47799 /* 134161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47800 /* 134167 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47801 /* 134170 */ GIR_RootConstrainSelectedInstOperands,
47802 /* 134171 */ // GIR_Coverage, 4043,
47803 /* 134171 */ GIR_EraseRootFromParent_Done,
47804 /* 134172 */ // Label 2670: @134172
47805 /* 134172 */ GIM_Reject,
47806 /* 134173 */ // Label 2668: @134173
47807 /* 134173 */ GIM_Reject,
47808 /* 134174 */ // Label 2662: @134174
47809 /* 134174 */ GIM_Try, /*On fail goto*//*Label 2671*/ GIMT_Encode4(134211), // Rule ID 1671 //
47810 /* 134179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47811 /* 134182 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
47812 /* 134185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47813 /* 134189 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47814 /* 134193 */ // (abs:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
47815 /* 134193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i16),
47816 /* 134196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47817 /* 134198 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
47818 /* 134200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47819 /* 134203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47820 /* 134209 */ GIR_RootConstrainSelectedInstOperands,
47821 /* 134210 */ // GIR_Coverage, 1671,
47822 /* 134210 */ GIR_EraseRootFromParent_Done,
47823 /* 134211 */ // Label 2671: @134211
47824 /* 134211 */ GIM_Reject,
47825 /* 134212 */ // Label 2663: @134212
47826 /* 134212 */ GIM_Try, /*On fail goto*//*Label 2672*/ GIMT_Encode4(134310),
47827 /* 134217 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
47828 /* 134220 */ GIM_Try, /*On fail goto*//*Label 2673*/ GIMT_Encode4(134254), // Rule ID 1674 //
47829 /* 134225 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47830 /* 134228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47831 /* 134232 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47832 /* 134236 */ // (abs:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
47833 /* 134236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i16),
47834 /* 134239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47835 /* 134241 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
47836 /* 134243 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47837 /* 134246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47838 /* 134252 */ GIR_RootConstrainSelectedInstOperands,
47839 /* 134253 */ // GIR_Coverage, 1674,
47840 /* 134253 */ GIR_EraseRootFromParent_Done,
47841 /* 134254 */ // Label 2673: @134254
47842 /* 134254 */ GIM_Try, /*On fail goto*//*Label 2674*/ GIMT_Encode4(134309), // Rule ID 4049 //
47843 /* 134259 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47844 /* 134262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47845 /* 134266 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47846 /* 134270 */ // (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v) => (MVE_VABSs16:{ *:[v8i16] } ?:{ *:[v8i16] }:$v)
47847 /* 134270 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47848 /* 134273 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47849 /* 134277 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47850 /* 134282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs16),
47851 /* 134285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47852 /* 134287 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
47853 /* 134289 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47854 /* 134292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47855 /* 134298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47856 /* 134304 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47857 /* 134307 */ GIR_RootConstrainSelectedInstOperands,
47858 /* 134308 */ // GIR_Coverage, 4049,
47859 /* 134308 */ GIR_EraseRootFromParent_Done,
47860 /* 134309 */ // Label 2674: @134309
47861 /* 134309 */ GIM_Reject,
47862 /* 134310 */ // Label 2672: @134310
47863 /* 134310 */ GIM_Reject,
47864 /* 134311 */ // Label 2664: @134311
47865 /* 134311 */ GIM_Try, /*On fail goto*//*Label 2675*/ GIMT_Encode4(134348), // Rule ID 1672 //
47866 /* 134316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47867 /* 134319 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
47868 /* 134322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47869 /* 134326 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47870 /* 134330 */ // (abs:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
47871 /* 134330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv2i32),
47872 /* 134333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47873 /* 134335 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
47874 /* 134337 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47875 /* 134340 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47876 /* 134346 */ GIR_RootConstrainSelectedInstOperands,
47877 /* 134347 */ // GIR_Coverage, 1672,
47878 /* 134347 */ GIR_EraseRootFromParent_Done,
47879 /* 134348 */ // Label 2675: @134348
47880 /* 134348 */ GIM_Reject,
47881 /* 134349 */ // Label 2665: @134349
47882 /* 134349 */ GIM_Try, /*On fail goto*//*Label 2676*/ GIMT_Encode4(134447),
47883 /* 134354 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
47884 /* 134357 */ GIM_Try, /*On fail goto*//*Label 2677*/ GIMT_Encode4(134391), // Rule ID 1675 //
47885 /* 134362 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47886 /* 134365 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47887 /* 134369 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47888 /* 134373 */ // (abs:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
47889 /* 134373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i32),
47890 /* 134376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47891 /* 134378 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
47892 /* 134380 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47893 /* 134383 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47894 /* 134389 */ GIR_RootConstrainSelectedInstOperands,
47895 /* 134390 */ // GIR_Coverage, 1675,
47896 /* 134390 */ GIR_EraseRootFromParent_Done,
47897 /* 134391 */ // Label 2677: @134391
47898 /* 134391 */ GIM_Try, /*On fail goto*//*Label 2678*/ GIMT_Encode4(134446), // Rule ID 4055 //
47899 /* 134396 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47900 /* 134399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47901 /* 134403 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47902 /* 134407 */ // (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v) => (MVE_VABSs32:{ *:[v4i32] } ?:{ *:[v4i32] }:$v)
47903 /* 134407 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47904 /* 134410 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47905 /* 134414 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47906 /* 134419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs32),
47907 /* 134422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47908 /* 134424 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
47909 /* 134426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47910 /* 134429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47911 /* 134435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47912 /* 134441 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47913 /* 134444 */ GIR_RootConstrainSelectedInstOperands,
47914 /* 134445 */ // GIR_Coverage, 4055,
47915 /* 134445 */ GIR_EraseRootFromParent_Done,
47916 /* 134446 */ // Label 2678: @134446
47917 /* 134446 */ GIM_Reject,
47918 /* 134447 */ // Label 2676: @134447
47919 /* 134447 */ GIM_Reject,
47920 /* 134448 */ // Label 2666: @134448
47921 /* 134448 */ GIM_Reject,
47922 /* 134449 */ // Label 66: @134449
47923 /* 134449 */ GIM_Try, /*On fail goto*//*Label 2679*/ GIMT_Encode4(134521),
47924 /* 134454 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
47925 /* 134457 */ GIM_Try, /*On fail goto*//*Label 2680*/ GIMT_Encode4(134472), // Rule ID 31 //
47926 /* 134462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
47927 /* 134465 */ // (br (bb:{ *:[Other] }):$target) => (B (bb:{ *:[Other] }):$target)
47928 /* 134465 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::B),
47929 /* 134470 */ GIR_RootConstrainSelectedInstOperands,
47930 /* 134471 */ // GIR_Coverage, 31,
47931 /* 134471 */ GIR_Done,
47932 /* 134472 */ // Label 2680: @134472
47933 /* 134472 */ GIM_Try, /*On fail goto*//*Label 2681*/ GIMT_Encode4(134496), // Rule ID 282 //
47934 /* 134477 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
47935 /* 134480 */ // (br (bb:{ *:[Other] }):$target) => (tB (bb:{ *:[Other] }):$target)
47936 /* 134480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tB),
47937 /* 134483 */ GIR_RootToRootCopy, /*OpIdx*/0, // target
47938 /* 134485 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47939 /* 134488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47940 /* 134494 */ GIR_RootConstrainSelectedInstOperands,
47941 /* 134495 */ // GIR_Coverage, 282,
47942 /* 134495 */ GIR_EraseRootFromParent_Done,
47943 /* 134496 */ // Label 2681: @134496
47944 /* 134496 */ GIM_Try, /*On fail goto*//*Label 2682*/ GIMT_Encode4(134520), // Rule ID 576 //
47945 /* 134501 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb),
47946 /* 134504 */ // (br (bb:{ *:[Other] }):$target) => (t2B (bb:{ *:[Other] }):$target)
47947 /* 134504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2B),
47948 /* 134507 */ GIR_RootToRootCopy, /*OpIdx*/0, // target
47949 /* 134509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47950 /* 134512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47951 /* 134518 */ GIR_RootConstrainSelectedInstOperands,
47952 /* 134519 */ // GIR_Coverage, 576,
47953 /* 134519 */ GIR_EraseRootFromParent_Done,
47954 /* 134520 */ // Label 2682: @134520
47955 /* 134520 */ GIM_Reject,
47956 /* 134521 */ // Label 2679: @134521
47957 /* 134521 */ GIM_Reject,
47958 /* 134522 */ // Label 67: @134522
47959 /* 134522 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(11), /*)*//*default:*//*Label 2687*/ GIMT_Encode4(134801),
47960 /* 134533 */ /*GILLT_v8s8*//*Label 2683*/ GIMT_Encode4(134549),
47961 /* 134537 */ /*GILLT_v16s8*//*Label 2684*/ GIMT_Encode4(134612),
47962 /* 134541 */ /*GILLT_v4s16*//*Label 2685*/ GIMT_Encode4(134675),
47963 /* 134545 */ /*GILLT_v8s16*//*Label 2686*/ GIMT_Encode4(134738),
47964 /* 134549 */ // Label 2683: @134549
47965 /* 134549 */ GIM_Try, /*On fail goto*//*Label 2688*/ GIMT_Encode4(134611), // Rule ID 1733 //
47966 /* 134554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47967 /* 134557 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
47968 /* 134560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
47969 /* 134563 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
47970 /* 134566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47971 /* 134570 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47972 /* 134574 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
47973 /* 134578 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
47974 /* 134582 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
47975 /* 134586 */ // MIs[1] Operand 1
47976 /* 134586 */ // No operand predicates
47977 /* 134586 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47978 /* 134588 */ // (vector_insert:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane)
47979 /* 134588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi8),
47980 /* 134591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V]
47981 /* 134593 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
47982 /* 134595 */ GIR_RootToRootCopy, /*OpIdx*/2, // R
47983 /* 134597 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
47984 /* 134600 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47985 /* 134603 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47986 /* 134609 */ GIR_RootConstrainSelectedInstOperands,
47987 /* 134610 */ // GIR_Coverage, 1733,
47988 /* 134610 */ GIR_EraseRootFromParent_Done,
47989 /* 134611 */ // Label 2688: @134611
47990 /* 134611 */ GIM_Reject,
47991 /* 134612 */ // Label 2684: @134612
47992 /* 134612 */ GIM_Try, /*On fail goto*//*Label 2689*/ GIMT_Encode4(134674), // Rule ID 3818 //
47993 /* 134617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47994 /* 134620 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
47995 /* 134623 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
47996 /* 134626 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
47997 /* 134629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47998 /* 134633 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47999 /* 134637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48000 /* 134641 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48001 /* 134645 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48002 /* 134649 */ // MIs[1] Operand 1
48003 /* 134649 */ // No operand predicates
48004 /* 134649 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48005 /* 134651 */ // (vector_insert:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane)
48006 /* 134651 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_8),
48007 /* 134654 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48008 /* 134656 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
48009 /* 134658 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2
48010 /* 134660 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
48011 /* 134663 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48012 /* 134666 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48013 /* 134672 */ GIR_RootConstrainSelectedInstOperands,
48014 /* 134673 */ // GIR_Coverage, 3818,
48015 /* 134673 */ GIR_EraseRootFromParent_Done,
48016 /* 134674 */ // Label 2689: @134674
48017 /* 134674 */ GIM_Reject,
48018 /* 134675 */ // Label 2685: @134675
48019 /* 134675 */ GIM_Try, /*On fail goto*//*Label 2690*/ GIMT_Encode4(134737), // Rule ID 1734 //
48020 /* 134680 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48021 /* 134683 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
48022 /* 134686 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
48023 /* 134689 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48024 /* 134692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48025 /* 134696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48026 /* 134700 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48027 /* 134704 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48028 /* 134708 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48029 /* 134712 */ // MIs[1] Operand 1
48030 /* 134712 */ // No operand predicates
48031 /* 134712 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48032 /* 134714 */ // (vector_insert:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane)
48033 /* 134714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi16),
48034 /* 134717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V]
48035 /* 134719 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
48036 /* 134721 */ GIR_RootToRootCopy, /*OpIdx*/2, // R
48037 /* 134723 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
48038 /* 134726 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48039 /* 134729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48040 /* 134735 */ GIR_RootConstrainSelectedInstOperands,
48041 /* 134736 */ // GIR_Coverage, 1734,
48042 /* 134736 */ GIR_EraseRootFromParent_Done,
48043 /* 134737 */ // Label 2690: @134737
48044 /* 134737 */ GIM_Reject,
48045 /* 134738 */ // Label 2686: @134738
48046 /* 134738 */ GIM_Try, /*On fail goto*//*Label 2691*/ GIMT_Encode4(134800), // Rule ID 3819 //
48047 /* 134743 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48048 /* 134746 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
48049 /* 134749 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
48050 /* 134752 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48051 /* 134755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48052 /* 134759 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48053 /* 134763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48054 /* 134767 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48055 /* 134771 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48056 /* 134775 */ // MIs[1] Operand 1
48057 /* 134775 */ // No operand predicates
48058 /* 134775 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48059 /* 134777 */ // (vector_insert:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane)
48060 /* 134777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_16),
48061 /* 134780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48062 /* 134782 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
48063 /* 134784 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2
48064 /* 134786 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
48065 /* 134789 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48066 /* 134792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48067 /* 134798 */ GIR_RootConstrainSelectedInstOperands,
48068 /* 134799 */ // GIR_Coverage, 3819,
48069 /* 134799 */ GIR_EraseRootFromParent_Done,
48070 /* 134800 */ // Label 2691: @134800
48071 /* 134800 */ GIM_Reject,
48072 /* 134801 */ // Label 2687: @134801
48073 /* 134801 */ GIM_Reject,
48074 /* 134802 */ // Label 68: @134802
48075 /* 134802 */ GIM_Try, /*On fail goto*//*Label 2692*/ GIMT_Encode4(134858), // Rule ID 1732 //
48076 /* 134807 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs_HasFastVGETLNi32),
48077 /* 134810 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
48078 /* 134813 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
48079 /* 134816 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
48080 /* 134819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48081 /* 134823 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48082 /* 134827 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
48083 /* 134831 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48084 /* 134835 */ // MIs[1] Operand 1
48085 /* 134835 */ // No operand predicates
48086 /* 134835 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48087 /* 134837 */ // (extractelt:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane) => (VGETLNi32:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane)
48088 /* 134837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VGETLNi32),
48089 /* 134840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[R]
48090 /* 134842 */ GIR_RootToRootCopy, /*OpIdx*/1, // V
48091 /* 134844 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
48092 /* 134847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48093 /* 134850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48094 /* 134856 */ GIR_RootConstrainSelectedInstOperands,
48095 /* 134857 */ // GIR_Coverage, 1732,
48096 /* 134857 */ GIR_EraseRootFromParent_Done,
48097 /* 134858 */ // Label 2692: @134858
48098 /* 134858 */ GIM_Reject,
48099 /* 134859 */ // Label 69: @134859
48100 /* 134859 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2700*/ GIMT_Encode4(135407),
48101 /* 134870 */ /*GILLT_s32*//*Label 2693*/ GIMT_Encode4(134918), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48102 /* 134894 */ /*GILLT_v8s8*//*Label 2694*/ GIMT_Encode4(134996),
48103 /* 134898 */ /*GILLT_v16s8*//*Label 2695*/ GIMT_Encode4(135034),
48104 /* 134902 */ /*GILLT_v4s16*//*Label 2696*/ GIMT_Encode4(135133),
48105 /* 134906 */ /*GILLT_v8s16*//*Label 2697*/ GIMT_Encode4(135171),
48106 /* 134910 */ /*GILLT_v2s32*//*Label 2698*/ GIMT_Encode4(135270),
48107 /* 134914 */ /*GILLT_v4s32*//*Label 2699*/ GIMT_Encode4(135308),
48108 /* 134918 */ // Label 2693: @134918
48109 /* 134918 */ GIM_Try, /*On fail goto*//*Label 2701*/ GIMT_Encode4(134995),
48110 /* 134923 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
48111 /* 134926 */ GIM_Try, /*On fail goto*//*Label 2702*/ GIMT_Encode4(134960), // Rule ID 196 //
48112 /* 134931 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsARM),
48113 /* 134934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48114 /* 134938 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48115 /* 134942 */ // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
48116 /* 134942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLZ),
48117 /* 134945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48118 /* 134947 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
48119 /* 134949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48120 /* 134952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48121 /* 134958 */ GIR_RootConstrainSelectedInstOperands,
48122 /* 134959 */ // GIR_Coverage, 196,
48123 /* 134959 */ GIR_EraseRootFromParent_Done,
48124 /* 134960 */ // Label 2702: @134960
48125 /* 134960 */ GIM_Try, /*On fail goto*//*Label 2703*/ GIMT_Encode4(134994), // Rule ID 533 //
48126 /* 134965 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
48127 /* 134968 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48128 /* 134972 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48129 /* 134976 */ // (ctlz:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2CLZ:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
48130 /* 134976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLZ),
48131 /* 134979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48132 /* 134981 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
48133 /* 134983 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48134 /* 134986 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48135 /* 134992 */ GIR_RootConstrainSelectedInstOperands,
48136 /* 134993 */ // GIR_Coverage, 533,
48137 /* 134993 */ GIR_EraseRootFromParent_Done,
48138 /* 134994 */ // Label 2703: @134994
48139 /* 134994 */ GIM_Reject,
48140 /* 134995 */ // Label 2701: @134995
48141 /* 134995 */ GIM_Reject,
48142 /* 134996 */ // Label 2694: @134996
48143 /* 134996 */ GIM_Try, /*On fail goto*//*Label 2704*/ GIMT_Encode4(135033), // Rule ID 1708 //
48144 /* 135001 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48145 /* 135004 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
48146 /* 135007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48147 /* 135011 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48148 /* 135015 */ // (ctlz:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLZv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
48149 /* 135015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i8),
48150 /* 135018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48151 /* 135020 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48152 /* 135022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48153 /* 135025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48154 /* 135031 */ GIR_RootConstrainSelectedInstOperands,
48155 /* 135032 */ // GIR_Coverage, 1708,
48156 /* 135032 */ GIR_EraseRootFromParent_Done,
48157 /* 135033 */ // Label 2704: @135033
48158 /* 135033 */ GIM_Reject,
48159 /* 135034 */ // Label 2695: @135034
48160 /* 135034 */ GIM_Try, /*On fail goto*//*Label 2705*/ GIMT_Encode4(135132),
48161 /* 135039 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
48162 /* 135042 */ GIM_Try, /*On fail goto*//*Label 2706*/ GIMT_Encode4(135076), // Rule ID 1711 //
48163 /* 135047 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48164 /* 135050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48165 /* 135054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48166 /* 135058 */ // (ctlz:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLZv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
48167 /* 135058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv16i8),
48168 /* 135061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48169 /* 135063 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48170 /* 135065 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48171 /* 135068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48172 /* 135074 */ GIR_RootConstrainSelectedInstOperands,
48173 /* 135075 */ // GIR_Coverage, 1711,
48174 /* 135075 */ GIR_EraseRootFromParent_Done,
48175 /* 135076 */ // Label 2706: @135076
48176 /* 135076 */ GIM_Try, /*On fail goto*//*Label 2707*/ GIMT_Encode4(135131), // Rule ID 4037 //
48177 /* 135081 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48178 /* 135084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48179 /* 135088 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48180 /* 135092 */ // (ctlz:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLZs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)
48181 /* 135092 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48182 /* 135095 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48183 /* 135099 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48184 /* 135104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs8),
48185 /* 135107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48186 /* 135109 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
48187 /* 135111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48188 /* 135114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48189 /* 135120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48190 /* 135126 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48191 /* 135129 */ GIR_RootConstrainSelectedInstOperands,
48192 /* 135130 */ // GIR_Coverage, 4037,
48193 /* 135130 */ GIR_EraseRootFromParent_Done,
48194 /* 135131 */ // Label 2707: @135131
48195 /* 135131 */ GIM_Reject,
48196 /* 135132 */ // Label 2705: @135132
48197 /* 135132 */ GIM_Reject,
48198 /* 135133 */ // Label 2696: @135133
48199 /* 135133 */ GIM_Try, /*On fail goto*//*Label 2708*/ GIMT_Encode4(135170), // Rule ID 1709 //
48200 /* 135138 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48201 /* 135141 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
48202 /* 135144 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48203 /* 135148 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48204 /* 135152 */ // (ctlz:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLZv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
48205 /* 135152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i16),
48206 /* 135155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48207 /* 135157 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48208 /* 135159 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48209 /* 135162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48210 /* 135168 */ GIR_RootConstrainSelectedInstOperands,
48211 /* 135169 */ // GIR_Coverage, 1709,
48212 /* 135169 */ GIR_EraseRootFromParent_Done,
48213 /* 135170 */ // Label 2708: @135170
48214 /* 135170 */ GIM_Reject,
48215 /* 135171 */ // Label 2697: @135171
48216 /* 135171 */ GIM_Try, /*On fail goto*//*Label 2709*/ GIMT_Encode4(135269),
48217 /* 135176 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
48218 /* 135179 */ GIM_Try, /*On fail goto*//*Label 2710*/ GIMT_Encode4(135213), // Rule ID 1712 //
48219 /* 135184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48220 /* 135187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48221 /* 135191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48222 /* 135195 */ // (ctlz:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLZv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
48223 /* 135195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i16),
48224 /* 135198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48225 /* 135200 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48226 /* 135202 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48227 /* 135205 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48228 /* 135211 */ GIR_RootConstrainSelectedInstOperands,
48229 /* 135212 */ // GIR_Coverage, 1712,
48230 /* 135212 */ GIR_EraseRootFromParent_Done,
48231 /* 135213 */ // Label 2710: @135213
48232 /* 135213 */ GIM_Try, /*On fail goto*//*Label 2711*/ GIMT_Encode4(135268), // Rule ID 4039 //
48233 /* 135218 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48234 /* 135221 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48235 /* 135225 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48236 /* 135229 */ // (ctlz:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLZs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)
48237 /* 135229 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48238 /* 135232 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48239 /* 135236 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48240 /* 135241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs16),
48241 /* 135244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48242 /* 135246 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
48243 /* 135248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48244 /* 135251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48245 /* 135257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48246 /* 135263 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48247 /* 135266 */ GIR_RootConstrainSelectedInstOperands,
48248 /* 135267 */ // GIR_Coverage, 4039,
48249 /* 135267 */ GIR_EraseRootFromParent_Done,
48250 /* 135268 */ // Label 2711: @135268
48251 /* 135268 */ GIM_Reject,
48252 /* 135269 */ // Label 2709: @135269
48253 /* 135269 */ GIM_Reject,
48254 /* 135270 */ // Label 2698: @135270
48255 /* 135270 */ GIM_Try, /*On fail goto*//*Label 2712*/ GIMT_Encode4(135307), // Rule ID 1710 //
48256 /* 135275 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48257 /* 135278 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
48258 /* 135281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48259 /* 135285 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48260 /* 135289 */ // (ctlz:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLZv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
48261 /* 135289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv2i32),
48262 /* 135292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48263 /* 135294 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48264 /* 135296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48265 /* 135299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48266 /* 135305 */ GIR_RootConstrainSelectedInstOperands,
48267 /* 135306 */ // GIR_Coverage, 1710,
48268 /* 135306 */ GIR_EraseRootFromParent_Done,
48269 /* 135307 */ // Label 2712: @135307
48270 /* 135307 */ GIM_Reject,
48271 /* 135308 */ // Label 2699: @135308
48272 /* 135308 */ GIM_Try, /*On fail goto*//*Label 2713*/ GIMT_Encode4(135406),
48273 /* 135313 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
48274 /* 135316 */ GIM_Try, /*On fail goto*//*Label 2714*/ GIMT_Encode4(135350), // Rule ID 1713 //
48275 /* 135321 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48276 /* 135324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48277 /* 135328 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48278 /* 135332 */ // (ctlz:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLZv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
48279 /* 135332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i32),
48280 /* 135335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48281 /* 135337 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48282 /* 135339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48283 /* 135342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48284 /* 135348 */ GIR_RootConstrainSelectedInstOperands,
48285 /* 135349 */ // GIR_Coverage, 1713,
48286 /* 135349 */ GIR_EraseRootFromParent_Done,
48287 /* 135350 */ // Label 2714: @135350
48288 /* 135350 */ GIM_Try, /*On fail goto*//*Label 2715*/ GIMT_Encode4(135405), // Rule ID 4041 //
48289 /* 135355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48290 /* 135358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48291 /* 135362 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48292 /* 135366 */ // (ctlz:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLZs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)
48293 /* 135366 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48294 /* 135369 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48295 /* 135373 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48296 /* 135378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs32),
48297 /* 135381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48298 /* 135383 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
48299 /* 135385 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48300 /* 135388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48301 /* 135394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48302 /* 135400 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48303 /* 135403 */ GIR_RootConstrainSelectedInstOperands,
48304 /* 135404 */ // GIR_Coverage, 4041,
48305 /* 135404 */ GIR_EraseRootFromParent_Done,
48306 /* 135405 */ // Label 2715: @135405
48307 /* 135405 */ GIM_Reject,
48308 /* 135406 */ // Label 2713: @135406
48309 /* 135406 */ GIM_Reject,
48310 /* 135407 */ // Label 2700: @135407
48311 /* 135407 */ GIM_Reject,
48312 /* 135408 */ // Label 70: @135408
48313 /* 135408 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 2722*/ GIMT_Encode4(135854),
48314 /* 135419 */ /*GILLT_v8s8*//*Label 2716*/ GIMT_Encode4(135443),
48315 /* 135423 */ /*GILLT_v16s8*//*Label 2717*/ GIMT_Encode4(135481),
48316 /* 135427 */ /*GILLT_v4s16*//*Label 2718*/ GIMT_Encode4(135580),
48317 /* 135431 */ /*GILLT_v8s16*//*Label 2719*/ GIMT_Encode4(135618),
48318 /* 135435 */ /*GILLT_v2s32*//*Label 2720*/ GIMT_Encode4(135717),
48319 /* 135439 */ /*GILLT_v4s32*//*Label 2721*/ GIMT_Encode4(135755),
48320 /* 135443 */ // Label 2716: @135443
48321 /* 135443 */ GIM_Try, /*On fail goto*//*Label 2723*/ GIMT_Encode4(135480), // Rule ID 1702 //
48322 /* 135448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48323 /* 135451 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
48324 /* 135454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48325 /* 135458 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48326 /* 135462 */ // (ctls:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
48327 /* 135462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i8),
48328 /* 135465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48329 /* 135467 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48330 /* 135469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48331 /* 135472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48332 /* 135478 */ GIR_RootConstrainSelectedInstOperands,
48333 /* 135479 */ // GIR_Coverage, 1702,
48334 /* 135479 */ GIR_EraseRootFromParent_Done,
48335 /* 135480 */ // Label 2723: @135480
48336 /* 135480 */ GIM_Reject,
48337 /* 135481 */ // Label 2717: @135481
48338 /* 135481 */ GIM_Try, /*On fail goto*//*Label 2724*/ GIMT_Encode4(135579),
48339 /* 135486 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
48340 /* 135489 */ GIM_Try, /*On fail goto*//*Label 2725*/ GIMT_Encode4(135523), // Rule ID 1705 //
48341 /* 135494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48342 /* 135497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48343 /* 135501 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48344 /* 135505 */ // (ctls:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
48345 /* 135505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv16i8),
48346 /* 135508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48347 /* 135510 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48348 /* 135512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48349 /* 135515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48350 /* 135521 */ GIR_RootConstrainSelectedInstOperands,
48351 /* 135522 */ // GIR_Coverage, 1705,
48352 /* 135522 */ GIR_EraseRootFromParent_Done,
48353 /* 135523 */ // Label 2725: @135523
48354 /* 135523 */ GIM_Try, /*On fail goto*//*Label 2726*/ GIMT_Encode4(135578), // Rule ID 4031 //
48355 /* 135528 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48356 /* 135531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48357 /* 135535 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48358 /* 135539 */ // (ctls:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLSs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)
48359 /* 135539 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48360 /* 135542 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48361 /* 135546 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48362 /* 135551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs8),
48363 /* 135554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48364 /* 135556 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
48365 /* 135558 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48366 /* 135561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48367 /* 135567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48368 /* 135573 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48369 /* 135576 */ GIR_RootConstrainSelectedInstOperands,
48370 /* 135577 */ // GIR_Coverage, 4031,
48371 /* 135577 */ GIR_EraseRootFromParent_Done,
48372 /* 135578 */ // Label 2726: @135578
48373 /* 135578 */ GIM_Reject,
48374 /* 135579 */ // Label 2724: @135579
48375 /* 135579 */ GIM_Reject,
48376 /* 135580 */ // Label 2718: @135580
48377 /* 135580 */ GIM_Try, /*On fail goto*//*Label 2727*/ GIMT_Encode4(135617), // Rule ID 1703 //
48378 /* 135585 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48379 /* 135588 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
48380 /* 135591 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48381 /* 135595 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48382 /* 135599 */ // (ctls:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
48383 /* 135599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i16),
48384 /* 135602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48385 /* 135604 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48386 /* 135606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48387 /* 135609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48388 /* 135615 */ GIR_RootConstrainSelectedInstOperands,
48389 /* 135616 */ // GIR_Coverage, 1703,
48390 /* 135616 */ GIR_EraseRootFromParent_Done,
48391 /* 135617 */ // Label 2727: @135617
48392 /* 135617 */ GIM_Reject,
48393 /* 135618 */ // Label 2719: @135618
48394 /* 135618 */ GIM_Try, /*On fail goto*//*Label 2728*/ GIMT_Encode4(135716),
48395 /* 135623 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
48396 /* 135626 */ GIM_Try, /*On fail goto*//*Label 2729*/ GIMT_Encode4(135660), // Rule ID 1706 //
48397 /* 135631 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48398 /* 135634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48399 /* 135638 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48400 /* 135642 */ // (ctls:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
48401 /* 135642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i16),
48402 /* 135645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48403 /* 135647 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48404 /* 135649 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48405 /* 135652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48406 /* 135658 */ GIR_RootConstrainSelectedInstOperands,
48407 /* 135659 */ // GIR_Coverage, 1706,
48408 /* 135659 */ GIR_EraseRootFromParent_Done,
48409 /* 135660 */ // Label 2729: @135660
48410 /* 135660 */ GIM_Try, /*On fail goto*//*Label 2730*/ GIMT_Encode4(135715), // Rule ID 4033 //
48411 /* 135665 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48412 /* 135668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48413 /* 135672 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48414 /* 135676 */ // (ctls:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLSs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)
48415 /* 135676 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48416 /* 135679 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48417 /* 135683 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48418 /* 135688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs16),
48419 /* 135691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48420 /* 135693 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
48421 /* 135695 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48422 /* 135698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48423 /* 135704 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48424 /* 135710 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48425 /* 135713 */ GIR_RootConstrainSelectedInstOperands,
48426 /* 135714 */ // GIR_Coverage, 4033,
48427 /* 135714 */ GIR_EraseRootFromParent_Done,
48428 /* 135715 */ // Label 2730: @135715
48429 /* 135715 */ GIM_Reject,
48430 /* 135716 */ // Label 2728: @135716
48431 /* 135716 */ GIM_Reject,
48432 /* 135717 */ // Label 2720: @135717
48433 /* 135717 */ GIM_Try, /*On fail goto*//*Label 2731*/ GIMT_Encode4(135754), // Rule ID 1704 //
48434 /* 135722 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48435 /* 135725 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
48436 /* 135728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48437 /* 135732 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48438 /* 135736 */ // (ctls:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
48439 /* 135736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv2i32),
48440 /* 135739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48441 /* 135741 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48442 /* 135743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48443 /* 135746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48444 /* 135752 */ GIR_RootConstrainSelectedInstOperands,
48445 /* 135753 */ // GIR_Coverage, 1704,
48446 /* 135753 */ GIR_EraseRootFromParent_Done,
48447 /* 135754 */ // Label 2731: @135754
48448 /* 135754 */ GIM_Reject,
48449 /* 135755 */ // Label 2721: @135755
48450 /* 135755 */ GIM_Try, /*On fail goto*//*Label 2732*/ GIMT_Encode4(135853),
48451 /* 135760 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
48452 /* 135763 */ GIM_Try, /*On fail goto*//*Label 2733*/ GIMT_Encode4(135797), // Rule ID 1707 //
48453 /* 135768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48454 /* 135771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48455 /* 135775 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48456 /* 135779 */ // (ctls:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
48457 /* 135779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i32),
48458 /* 135782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48459 /* 135784 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48460 /* 135786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48461 /* 135789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48462 /* 135795 */ GIR_RootConstrainSelectedInstOperands,
48463 /* 135796 */ // GIR_Coverage, 1707,
48464 /* 135796 */ GIR_EraseRootFromParent_Done,
48465 /* 135797 */ // Label 2733: @135797
48466 /* 135797 */ GIM_Try, /*On fail goto*//*Label 2734*/ GIMT_Encode4(135852), // Rule ID 4035 //
48467 /* 135802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48468 /* 135805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48469 /* 135809 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48470 /* 135813 */ // (ctls:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLSs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)
48471 /* 135813 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48472 /* 135816 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48473 /* 135820 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48474 /* 135825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs32),
48475 /* 135828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48476 /* 135830 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
48477 /* 135832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48478 /* 135835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48479 /* 135841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48480 /* 135847 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48481 /* 135850 */ GIR_RootConstrainSelectedInstOperands,
48482 /* 135851 */ // GIR_Coverage, 4035,
48483 /* 135851 */ GIR_EraseRootFromParent_Done,
48484 /* 135852 */ // Label 2734: @135852
48485 /* 135852 */ GIM_Reject,
48486 /* 135853 */ // Label 2732: @135853
48487 /* 135853 */ GIM_Reject,
48488 /* 135854 */ // Label 2722: @135854
48489 /* 135854 */ GIM_Reject,
48490 /* 135855 */ // Label 71: @135855
48491 /* 135855 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 2737*/ GIMT_Encode4(135950),
48492 /* 135866 */ /*GILLT_v8s8*//*Label 2735*/ GIMT_Encode4(135874),
48493 /* 135870 */ /*GILLT_v16s8*//*Label 2736*/ GIMT_Encode4(135912),
48494 /* 135874 */ // Label 2735: @135874
48495 /* 135874 */ GIM_Try, /*On fail goto*//*Label 2738*/ GIMT_Encode4(135911), // Rule ID 1714 //
48496 /* 135879 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48497 /* 135882 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
48498 /* 135885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48499 /* 135889 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48500 /* 135893 */ // (ctpop:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCNTd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
48501 /* 135893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTd),
48502 /* 135896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48503 /* 135898 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48504 /* 135900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48505 /* 135903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48506 /* 135909 */ GIR_RootConstrainSelectedInstOperands,
48507 /* 135910 */ // GIR_Coverage, 1714,
48508 /* 135910 */ GIR_EraseRootFromParent_Done,
48509 /* 135911 */ // Label 2738: @135911
48510 /* 135911 */ GIM_Reject,
48511 /* 135912 */ // Label 2736: @135912
48512 /* 135912 */ GIM_Try, /*On fail goto*//*Label 2739*/ GIMT_Encode4(135949), // Rule ID 1715 //
48513 /* 135917 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48514 /* 135920 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
48515 /* 135923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48516 /* 135927 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48517 /* 135931 */ // (ctpop:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCNTq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
48518 /* 135931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTq),
48519 /* 135934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48520 /* 135936 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48521 /* 135938 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48522 /* 135941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48523 /* 135947 */ GIR_RootConstrainSelectedInstOperands,
48524 /* 135948 */ // GIR_Coverage, 1715,
48525 /* 135948 */ GIR_EraseRootFromParent_Done,
48526 /* 135949 */ // Label 2739: @135949
48527 /* 135949 */ GIM_Reject,
48528 /* 135950 */ // Label 2737: @135950
48529 /* 135950 */ GIM_Reject,
48530 /* 135951 */ // Label 72: @135951
48531 /* 135951 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2743*/ GIMT_Encode4(136240),
48532 /* 135962 */ /*GILLT_s32*//*Label 2740*/ GIMT_Encode4(136010), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48533 /* 135998 */ /*GILLT_v8s16*//*Label 2741*/ GIMT_Encode4(136122), GIMT_Encode4(0),
48534 /* 136006 */ /*GILLT_v4s32*//*Label 2742*/ GIMT_Encode4(136181),
48535 /* 136010 */ // Label 2740: @136010
48536 /* 136010 */ GIM_Try, /*On fail goto*//*Label 2744*/ GIMT_Encode4(136121),
48537 /* 136015 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
48538 /* 136018 */ GIM_Try, /*On fail goto*//*Label 2745*/ GIMT_Encode4(136052), // Rule ID 198 //
48539 /* 136023 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
48540 /* 136026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48541 /* 136030 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48542 /* 136034 */ // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (REV:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
48543 /* 136034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV),
48544 /* 136037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48545 /* 136039 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
48546 /* 136041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48547 /* 136044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48548 /* 136050 */ GIR_RootConstrainSelectedInstOperands,
48549 /* 136051 */ // GIR_Coverage, 198,
48550 /* 136051 */ GIR_EraseRootFromParent_Done,
48551 /* 136052 */ // Label 2745: @136052
48552 /* 136052 */ GIM_Try, /*On fail goto*//*Label 2746*/ GIMT_Encode4(136086), // Rule ID 325 //
48553 /* 136057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
48554 /* 136060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
48555 /* 136064 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
48556 /* 136068 */ // (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) => (tREV:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
48557 /* 136068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV),
48558 /* 136071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48559 /* 136073 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
48560 /* 136075 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48561 /* 136078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48562 /* 136084 */ GIR_RootConstrainSelectedInstOperands,
48563 /* 136085 */ // GIR_Coverage, 325,
48564 /* 136085 */ GIR_EraseRootFromParent_Done,
48565 /* 136086 */ // Label 2746: @136086
48566 /* 136086 */ GIM_Try, /*On fail goto*//*Label 2747*/ GIMT_Encode4(136120), // Rule ID 535 //
48567 /* 136091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
48568 /* 136094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48569 /* 136098 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48570 /* 136102 */ // (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2REV:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
48571 /* 136102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV),
48572 /* 136105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48573 /* 136107 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
48574 /* 136109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48575 /* 136112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48576 /* 136118 */ GIR_RootConstrainSelectedInstOperands,
48577 /* 136119 */ // GIR_Coverage, 535,
48578 /* 136119 */ GIR_EraseRootFromParent_Done,
48579 /* 136120 */ // Label 2747: @136120
48580 /* 136120 */ GIM_Reject,
48581 /* 136121 */ // Label 2744: @136121
48582 /* 136121 */ GIM_Reject,
48583 /* 136122 */ // Label 2741: @136122
48584 /* 136122 */ GIM_Try, /*On fail goto*//*Label 2748*/ GIMT_Encode4(136180), // Rule ID 3713 //
48585 /* 136127 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48586 /* 136130 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
48587 /* 136133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48588 /* 136137 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48589 /* 136141 */ // (bswap:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src)
48590 /* 136141 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48591 /* 136144 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48592 /* 136148 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48593 /* 136153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
48594 /* 136156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48595 /* 136158 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
48596 /* 136160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48597 /* 136163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48598 /* 136169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48599 /* 136175 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48600 /* 136178 */ GIR_RootConstrainSelectedInstOperands,
48601 /* 136179 */ // GIR_Coverage, 3713,
48602 /* 136179 */ GIR_EraseRootFromParent_Done,
48603 /* 136180 */ // Label 2748: @136180
48604 /* 136180 */ GIM_Reject,
48605 /* 136181 */ // Label 2742: @136181
48606 /* 136181 */ GIM_Try, /*On fail goto*//*Label 2749*/ GIMT_Encode4(136239), // Rule ID 3714 //
48607 /* 136186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48608 /* 136189 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
48609 /* 136192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48610 /* 136196 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48611 /* 136200 */ // (bswap:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src)
48612 /* 136200 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48613 /* 136203 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48614 /* 136207 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48615 /* 136212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
48616 /* 136215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48617 /* 136217 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
48618 /* 136219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48619 /* 136222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48620 /* 136228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48621 /* 136234 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48622 /* 136237 */ GIR_RootConstrainSelectedInstOperands,
48623 /* 136238 */ // GIR_Coverage, 3714,
48624 /* 136238 */ GIR_EraseRootFromParent_Done,
48625 /* 136239 */ // Label 2749: @136239
48626 /* 136239 */ GIM_Reject,
48627 /* 136240 */ // Label 2743: @136240
48628 /* 136240 */ GIM_Reject,
48629 /* 136241 */ // Label 73: @136241
48630 /* 136241 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2754*/ GIMT_Encode4(136660),
48631 /* 136252 */ /*GILLT_s32*//*Label 2750*/ GIMT_Encode4(136300), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48632 /* 136280 */ /*GILLT_v16s8*//*Label 2751*/ GIMT_Encode4(136378), GIMT_Encode4(0),
48633 /* 136288 */ /*GILLT_v8s16*//*Label 2752*/ GIMT_Encode4(136472), GIMT_Encode4(0),
48634 /* 136296 */ /*GILLT_v4s32*//*Label 2753*/ GIMT_Encode4(136566),
48635 /* 136300 */ // Label 2750: @136300
48636 /* 136300 */ GIM_Try, /*On fail goto*//*Label 2755*/ GIMT_Encode4(136377),
48637 /* 136305 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
48638 /* 136308 */ GIM_Try, /*On fail goto*//*Label 2756*/ GIMT_Encode4(136342), // Rule ID 197 //
48639 /* 136313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM),
48640 /* 136316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48641 /* 136320 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48642 /* 136324 */ // (bitreverse:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (RBIT:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
48643 /* 136324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RBIT),
48644 /* 136327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48645 /* 136329 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
48646 /* 136331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48647 /* 136334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48648 /* 136340 */ GIR_RootConstrainSelectedInstOperands,
48649 /* 136341 */ // GIR_Coverage, 197,
48650 /* 136341 */ GIR_EraseRootFromParent_Done,
48651 /* 136342 */ // Label 2756: @136342
48652 /* 136342 */ GIM_Try, /*On fail goto*//*Label 2757*/ GIMT_Encode4(136376), // Rule ID 534 //
48653 /* 136347 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
48654 /* 136350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48655 /* 136354 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48656 /* 136358 */ // (bitreverse:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2RBIT:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
48657 /* 136358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RBIT),
48658 /* 136361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48659 /* 136363 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
48660 /* 136365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48661 /* 136368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48662 /* 136374 */ GIR_RootConstrainSelectedInstOperands,
48663 /* 136375 */ // GIR_Coverage, 534,
48664 /* 136375 */ GIR_EraseRootFromParent_Done,
48665 /* 136376 */ // Label 2757: @136376
48666 /* 136376 */ GIM_Reject,
48667 /* 136377 */ // Label 2755: @136377
48668 /* 136377 */ GIM_Reject,
48669 /* 136378 */ // Label 2751: @136378
48670 /* 136378 */ GIM_Try, /*On fail goto*//*Label 2758*/ GIMT_Encode4(136471), // Rule ID 5260 //
48671 /* 136383 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48672 /* 136386 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
48673 /* 136389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48674 /* 136393 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48675 /* 136397 */ // (bitreverse:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1, (t2MOVi:{ *:[i32] } 8:{ *:[i32] }))
48676 /* 136397 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
48677 /* 136400 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48678 /* 136404 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48679 /* 136409 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48680 /* 136412 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
48681 /* 136416 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48682 /* 136421 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
48683 /* 136424 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48684 /* 136427 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48685 /* 136433 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48686 /* 136439 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48687 /* 136441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8),
48688 /* 136444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48689 /* 136446 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1
48690 /* 136448 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48691 /* 136451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48692 /* 136454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48693 /* 136460 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48694 /* 136466 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
48695 /* 136469 */ GIR_RootConstrainSelectedInstOperands,
48696 /* 136470 */ // GIR_Coverage, 5260,
48697 /* 136470 */ GIR_EraseRootFromParent_Done,
48698 /* 136471 */ // Label 2758: @136471
48699 /* 136471 */ GIM_Reject,
48700 /* 136472 */ // Label 2752: @136472
48701 /* 136472 */ GIM_Try, /*On fail goto*//*Label 2759*/ GIMT_Encode4(136565), // Rule ID 5262 //
48702 /* 136477 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48703 /* 136480 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
48704 /* 136483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48705 /* 136487 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48706 /* 136491 */ // (bitreverse:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1, (t2MOVi:{ *:[i32] } 16:{ *:[i32] }))
48707 /* 136491 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
48708 /* 136494 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48709 /* 136498 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48710 /* 136503 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48711 /* 136506 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
48712 /* 136510 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48713 /* 136515 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/16,
48714 /* 136518 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48715 /* 136521 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48716 /* 136527 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48717 /* 136533 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48718 /* 136535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16),
48719 /* 136538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48720 /* 136540 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1
48721 /* 136542 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48722 /* 136545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48723 /* 136548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48724 /* 136554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48725 /* 136560 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
48726 /* 136563 */ GIR_RootConstrainSelectedInstOperands,
48727 /* 136564 */ // GIR_Coverage, 5262,
48728 /* 136564 */ GIR_EraseRootFromParent_Done,
48729 /* 136565 */ // Label 2759: @136565
48730 /* 136565 */ GIM_Reject,
48731 /* 136566 */ // Label 2753: @136566
48732 /* 136566 */ GIM_Try, /*On fail goto*//*Label 2760*/ GIMT_Encode4(136659), // Rule ID 5261 //
48733 /* 136571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48734 /* 136574 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
48735 /* 136577 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48736 /* 136581 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48737 /* 136585 */ // (bitreverse:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1, (t2MOVi:{ *:[i32] } 32:{ *:[i32] }))
48738 /* 136585 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
48739 /* 136588 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48740 /* 136592 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48741 /* 136597 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48742 /* 136600 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
48743 /* 136604 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48744 /* 136609 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/32,
48745 /* 136612 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48746 /* 136615 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48747 /* 136621 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48748 /* 136627 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48749 /* 136629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32),
48750 /* 136632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48751 /* 136634 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1
48752 /* 136636 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48753 /* 136639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48754 /* 136642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48755 /* 136648 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48756 /* 136654 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
48757 /* 136657 */ GIR_RootConstrainSelectedInstOperands,
48758 /* 136658 */ // GIR_Coverage, 5261,
48759 /* 136658 */ GIR_EraseRootFromParent_Done,
48760 /* 136659 */ // Label 2760: @136659
48761 /* 136659 */ GIM_Reject,
48762 /* 136660 */ // Label 2754: @136660
48763 /* 136660 */ GIM_Reject,
48764 /* 136661 */ // Label 74: @136661
48765 /* 136661 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2768*/ GIMT_Encode4(137035),
48766 /* 136672 */ /*GILLT_s16*//*Label 2761*/ GIMT_Encode4(136724),
48767 /* 136676 */ /*GILLT_s32*//*Label 2762*/ GIMT_Encode4(136751),
48768 /* 136680 */ /*GILLT_s64*//*Label 2763*/ GIMT_Encode4(136778), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48769 /* 136708 */ /*GILLT_v4s16*//*Label 2764*/ GIMT_Encode4(136805),
48770 /* 136712 */ /*GILLT_v8s16*//*Label 2765*/ GIMT_Encode4(136832),
48771 /* 136716 */ /*GILLT_v2s32*//*Label 2766*/ GIMT_Encode4(136920),
48772 /* 136720 */ /*GILLT_v4s32*//*Label 2767*/ GIMT_Encode4(136947),
48773 /* 136724 */ // Label 2761: @136724
48774 /* 136724 */ GIM_Try, /*On fail goto*//*Label 2769*/ GIMT_Encode4(136750), // Rule ID 723 //
48775 /* 136729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
48776 /* 136732 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
48777 /* 136735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48778 /* 136739 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48779 /* 136743 */ // (fceil:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTPH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
48780 /* 136743 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPH),
48781 /* 136748 */ GIR_RootConstrainSelectedInstOperands,
48782 /* 136749 */ // GIR_Coverage, 723,
48783 /* 136749 */ GIR_Done,
48784 /* 136750 */ // Label 2769: @136750
48785 /* 136750 */ GIM_Reject,
48786 /* 136751 */ // Label 2762: @136751
48787 /* 136751 */ GIM_Try, /*On fail goto*//*Label 2770*/ GIMT_Encode4(136777), // Rule ID 725 //
48788 /* 136756 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
48789 /* 136759 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
48790 /* 136762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48791 /* 136766 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48792 /* 136770 */ // (fceil:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTPS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
48793 /* 136770 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPS),
48794 /* 136775 */ GIR_RootConstrainSelectedInstOperands,
48795 /* 136776 */ // GIR_Coverage, 725,
48796 /* 136776 */ GIR_Done,
48797 /* 136777 */ // Label 2770: @136777
48798 /* 136777 */ GIM_Reject,
48799 /* 136778 */ // Label 2763: @136778
48800 /* 136778 */ GIM_Try, /*On fail goto*//*Label 2771*/ GIMT_Encode4(136804), // Rule ID 727 //
48801 /* 136783 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
48802 /* 136786 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
48803 /* 136789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48804 /* 136793 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48805 /* 136797 */ // (fceil:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTPD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
48806 /* 136797 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPD),
48807 /* 136802 */ GIR_RootConstrainSelectedInstOperands,
48808 /* 136803 */ // GIR_Coverage, 727,
48809 /* 136803 */ GIR_Done,
48810 /* 136804 */ // Label 2771: @136804
48811 /* 136804 */ GIM_Reject,
48812 /* 136805 */ // Label 2764: @136805
48813 /* 136805 */ GIM_Try, /*On fail goto*//*Label 2772*/ GIMT_Encode4(136831), // Rule ID 1898 //
48814 /* 136810 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
48815 /* 136813 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
48816 /* 136816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48817 /* 136820 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48818 /* 136824 */ // (fceil:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTPNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
48819 /* 136824 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDh),
48820 /* 136829 */ GIR_RootConstrainSelectedInstOperands,
48821 /* 136830 */ // GIR_Coverage, 1898,
48822 /* 136830 */ GIR_Done,
48823 /* 136831 */ // Label 2772: @136831
48824 /* 136831 */ GIM_Reject,
48825 /* 136832 */ // Label 2765: @136832
48826 /* 136832 */ GIM_Try, /*On fail goto*//*Label 2773*/ GIMT_Encode4(136919),
48827 /* 136837 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
48828 /* 136840 */ GIM_Try, /*On fail goto*//*Label 2774*/ GIMT_Encode4(136863), // Rule ID 1900 //
48829 /* 136845 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
48830 /* 136848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48831 /* 136852 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48832 /* 136856 */ // (fceil:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTPNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
48833 /* 136856 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQh),
48834 /* 136861 */ GIR_RootConstrainSelectedInstOperands,
48835 /* 136862 */ // GIR_Coverage, 1900,
48836 /* 136862 */ GIR_Done,
48837 /* 136863 */ // Label 2774: @136863
48838 /* 136863 */ GIM_Try, /*On fail goto*//*Label 2775*/ GIMT_Encode4(136918), // Rule ID 4368 //
48839 /* 136868 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
48840 /* 136871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48841 /* 136875 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48842 /* 136879 */ // (fceil:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
48843 /* 136879 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48844 /* 136882 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48845 /* 136886 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48846 /* 136891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P),
48847 /* 136894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48848 /* 136896 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
48849 /* 136898 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48850 /* 136901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48851 /* 136907 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48852 /* 136913 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48853 /* 136916 */ GIR_RootConstrainSelectedInstOperands,
48854 /* 136917 */ // GIR_Coverage, 4368,
48855 /* 136917 */ GIR_EraseRootFromParent_Done,
48856 /* 136918 */ // Label 2775: @136918
48857 /* 136918 */ GIM_Reject,
48858 /* 136919 */ // Label 2773: @136919
48859 /* 136919 */ GIM_Reject,
48860 /* 136920 */ // Label 2766: @136920
48861 /* 136920 */ GIM_Try, /*On fail goto*//*Label 2776*/ GIMT_Encode4(136946), // Rule ID 1894 //
48862 /* 136925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
48863 /* 136928 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
48864 /* 136931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48865 /* 136935 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48866 /* 136939 */ // (fceil:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTPNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
48867 /* 136939 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDf),
48868 /* 136944 */ GIR_RootConstrainSelectedInstOperands,
48869 /* 136945 */ // GIR_Coverage, 1894,
48870 /* 136945 */ GIR_Done,
48871 /* 136946 */ // Label 2776: @136946
48872 /* 136946 */ GIM_Reject,
48873 /* 136947 */ // Label 2767: @136947
48874 /* 136947 */ GIM_Try, /*On fail goto*//*Label 2777*/ GIMT_Encode4(137034),
48875 /* 136952 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
48876 /* 136955 */ GIM_Try, /*On fail goto*//*Label 2778*/ GIMT_Encode4(136978), // Rule ID 1896 //
48877 /* 136960 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
48878 /* 136963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48879 /* 136967 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48880 /* 136971 */ // (fceil:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTPNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
48881 /* 136971 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQf),
48882 /* 136976 */ GIR_RootConstrainSelectedInstOperands,
48883 /* 136977 */ // GIR_Coverage, 1896,
48884 /* 136977 */ GIR_Done,
48885 /* 136978 */ // Label 2778: @136978
48886 /* 136978 */ GIM_Try, /*On fail goto*//*Label 2779*/ GIMT_Encode4(137033), // Rule ID 4392 //
48887 /* 136983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
48888 /* 136986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48889 /* 136990 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48890 /* 136994 */ // (fceil:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
48891 /* 136994 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48892 /* 136997 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48893 /* 137001 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48894 /* 137006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P),
48895 /* 137009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48896 /* 137011 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
48897 /* 137013 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48898 /* 137016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48899 /* 137022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48900 /* 137028 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48901 /* 137031 */ GIR_RootConstrainSelectedInstOperands,
48902 /* 137032 */ // GIR_Coverage, 4392,
48903 /* 137032 */ GIR_EraseRootFromParent_Done,
48904 /* 137033 */ // Label 2779: @137033
48905 /* 137033 */ GIM_Reject,
48906 /* 137034 */ // Label 2777: @137034
48907 /* 137034 */ GIM_Reject,
48908 /* 137035 */ // Label 2768: @137035
48909 /* 137035 */ GIM_Reject,
48910 /* 137036 */ // Label 75: @137036
48911 /* 137036 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2783*/ GIMT_Encode4(137173),
48912 /* 137047 */ /*GILLT_s16*//*Label 2780*/ GIMT_Encode4(137059),
48913 /* 137051 */ /*GILLT_s32*//*Label 2781*/ GIMT_Encode4(137097),
48914 /* 137055 */ /*GILLT_s64*//*Label 2782*/ GIMT_Encode4(137135),
48915 /* 137059 */ // Label 2780: @137059
48916 /* 137059 */ GIM_Try, /*On fail goto*//*Label 2784*/ GIMT_Encode4(137096), // Rule ID 739 //
48917 /* 137064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
48918 /* 137067 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
48919 /* 137070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48920 /* 137074 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48921 /* 137078 */ // (fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
48922 /* 137078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH),
48923 /* 137081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
48924 /* 137083 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
48925 /* 137085 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48926 /* 137088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48927 /* 137094 */ GIR_RootConstrainSelectedInstOperands,
48928 /* 137095 */ // GIR_Coverage, 739,
48929 /* 137095 */ GIR_EraseRootFromParent_Done,
48930 /* 137096 */ // Label 2784: @137096
48931 /* 137096 */ GIM_Reject,
48932 /* 137097 */ // Label 2781: @137097
48933 /* 137097 */ GIM_Try, /*On fail goto*//*Label 2785*/ GIMT_Encode4(137134), // Rule ID 737 //
48934 /* 137102 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2),
48935 /* 137105 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
48936 /* 137108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48937 /* 137112 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48938 /* 137116 */ // (fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
48939 /* 137116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS),
48940 /* 137119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
48941 /* 137121 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
48942 /* 137123 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48943 /* 137126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48944 /* 137132 */ GIR_RootConstrainSelectedInstOperands,
48945 /* 137133 */ // GIR_Coverage, 737,
48946 /* 137133 */ GIR_EraseRootFromParent_Done,
48947 /* 137134 */ // Label 2785: @137134
48948 /* 137134 */ GIM_Reject,
48949 /* 137135 */ // Label 2782: @137135
48950 /* 137135 */ GIM_Try, /*On fail goto*//*Label 2786*/ GIMT_Encode4(137172), // Rule ID 735 //
48951 /* 137140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
48952 /* 137143 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
48953 /* 137146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48954 /* 137150 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48955 /* 137154 */ // (fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
48956 /* 137154 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD),
48957 /* 137157 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
48958 /* 137159 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
48959 /* 137161 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48960 /* 137164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48961 /* 137170 */ GIR_RootConstrainSelectedInstOperands,
48962 /* 137171 */ // GIR_Coverage, 735,
48963 /* 137171 */ GIR_EraseRootFromParent_Done,
48964 /* 137172 */ // Label 2786: @137172
48965 /* 137172 */ GIM_Reject,
48966 /* 137173 */ // Label 2783: @137173
48967 /* 137173 */ GIM_Reject,
48968 /* 137174 */ // Label 76: @137174
48969 /* 137174 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2794*/ GIMT_Encode4(137548),
48970 /* 137185 */ /*GILLT_s16*//*Label 2787*/ GIMT_Encode4(137237),
48971 /* 137189 */ /*GILLT_s32*//*Label 2788*/ GIMT_Encode4(137264),
48972 /* 137193 */ /*GILLT_s64*//*Label 2789*/ GIMT_Encode4(137291), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48973 /* 137221 */ /*GILLT_v4s16*//*Label 2790*/ GIMT_Encode4(137318),
48974 /* 137225 */ /*GILLT_v8s16*//*Label 2791*/ GIMT_Encode4(137345),
48975 /* 137229 */ /*GILLT_v2s32*//*Label 2792*/ GIMT_Encode4(137433),
48976 /* 137233 */ /*GILLT_v4s32*//*Label 2793*/ GIMT_Encode4(137460),
48977 /* 137237 */ // Label 2787: @137237
48978 /* 137237 */ GIM_Try, /*On fail goto*//*Label 2795*/ GIMT_Encode4(137263), // Rule ID 729 //
48979 /* 137242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
48980 /* 137245 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
48981 /* 137248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48982 /* 137252 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48983 /* 137256 */ // (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTMH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
48984 /* 137256 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMH),
48985 /* 137261 */ GIR_RootConstrainSelectedInstOperands,
48986 /* 137262 */ // GIR_Coverage, 729,
48987 /* 137262 */ GIR_Done,
48988 /* 137263 */ // Label 2795: @137263
48989 /* 137263 */ GIM_Reject,
48990 /* 137264 */ // Label 2788: @137264
48991 /* 137264 */ GIM_Try, /*On fail goto*//*Label 2796*/ GIMT_Encode4(137290), // Rule ID 731 //
48992 /* 137269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
48993 /* 137272 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
48994 /* 137275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48995 /* 137279 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48996 /* 137283 */ // (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTMS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
48997 /* 137283 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMS),
48998 /* 137288 */ GIR_RootConstrainSelectedInstOperands,
48999 /* 137289 */ // GIR_Coverage, 731,
49000 /* 137289 */ GIR_Done,
49001 /* 137290 */ // Label 2796: @137290
49002 /* 137290 */ GIM_Reject,
49003 /* 137291 */ // Label 2789: @137291
49004 /* 137291 */ GIM_Try, /*On fail goto*//*Label 2797*/ GIMT_Encode4(137317), // Rule ID 733 //
49005 /* 137296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
49006 /* 137299 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49007 /* 137302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49008 /* 137306 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49009 /* 137310 */ // (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTMD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
49010 /* 137310 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMD),
49011 /* 137315 */ GIR_RootConstrainSelectedInstOperands,
49012 /* 137316 */ // GIR_Coverage, 733,
49013 /* 137316 */ GIR_Done,
49014 /* 137317 */ // Label 2797: @137317
49015 /* 137317 */ GIM_Reject,
49016 /* 137318 */ // Label 2790: @137318
49017 /* 137318 */ GIM_Try, /*On fail goto*//*Label 2798*/ GIMT_Encode4(137344), // Rule ID 1890 //
49018 /* 137323 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
49019 /* 137326 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
49020 /* 137329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49021 /* 137333 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49022 /* 137337 */ // (ffloor:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
49023 /* 137337 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDh),
49024 /* 137342 */ GIR_RootConstrainSelectedInstOperands,
49025 /* 137343 */ // GIR_Coverage, 1890,
49026 /* 137343 */ GIR_Done,
49027 /* 137344 */ // Label 2798: @137344
49028 /* 137344 */ GIM_Reject,
49029 /* 137345 */ // Label 2791: @137345
49030 /* 137345 */ GIM_Try, /*On fail goto*//*Label 2799*/ GIMT_Encode4(137432),
49031 /* 137350 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
49032 /* 137353 */ GIM_Try, /*On fail goto*//*Label 2800*/ GIMT_Encode4(137376), // Rule ID 1892 //
49033 /* 137358 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
49034 /* 137361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49035 /* 137365 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49036 /* 137369 */ // (ffloor:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
49037 /* 137369 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQh),
49038 /* 137374 */ GIR_RootConstrainSelectedInstOperands,
49039 /* 137375 */ // GIR_Coverage, 1892,
49040 /* 137375 */ GIR_Done,
49041 /* 137376 */ // Label 2800: @137376
49042 /* 137376 */ GIM_Try, /*On fail goto*//*Label 2801*/ GIMT_Encode4(137431), // Rule ID 4364 //
49043 /* 137381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
49044 /* 137384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49045 /* 137388 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49046 /* 137392 */ // (ffloor:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
49047 /* 137392 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
49048 /* 137395 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
49049 /* 137399 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
49050 /* 137404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M),
49051 /* 137407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
49052 /* 137409 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
49053 /* 137411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
49054 /* 137414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49055 /* 137420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49056 /* 137426 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49057 /* 137429 */ GIR_RootConstrainSelectedInstOperands,
49058 /* 137430 */ // GIR_Coverage, 4364,
49059 /* 137430 */ GIR_EraseRootFromParent_Done,
49060 /* 137431 */ // Label 2801: @137431
49061 /* 137431 */ GIM_Reject,
49062 /* 137432 */ // Label 2799: @137432
49063 /* 137432 */ GIM_Reject,
49064 /* 137433 */ // Label 2792: @137433
49065 /* 137433 */ GIM_Try, /*On fail goto*//*Label 2802*/ GIMT_Encode4(137459), // Rule ID 1886 //
49066 /* 137438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
49067 /* 137441 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
49068 /* 137444 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49069 /* 137448 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49070 /* 137452 */ // (ffloor:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
49071 /* 137452 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDf),
49072 /* 137457 */ GIR_RootConstrainSelectedInstOperands,
49073 /* 137458 */ // GIR_Coverage, 1886,
49074 /* 137458 */ GIR_Done,
49075 /* 137459 */ // Label 2802: @137459
49076 /* 137459 */ GIM_Reject,
49077 /* 137460 */ // Label 2793: @137460
49078 /* 137460 */ GIM_Try, /*On fail goto*//*Label 2803*/ GIMT_Encode4(137547),
49079 /* 137465 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
49080 /* 137468 */ GIM_Try, /*On fail goto*//*Label 2804*/ GIMT_Encode4(137491), // Rule ID 1888 //
49081 /* 137473 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
49082 /* 137476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49083 /* 137480 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49084 /* 137484 */ // (ffloor:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
49085 /* 137484 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQf),
49086 /* 137489 */ GIR_RootConstrainSelectedInstOperands,
49087 /* 137490 */ // GIR_Coverage, 1888,
49088 /* 137490 */ GIR_Done,
49089 /* 137491 */ // Label 2804: @137491
49090 /* 137491 */ GIM_Try, /*On fail goto*//*Label 2805*/ GIMT_Encode4(137546), // Rule ID 4388 //
49091 /* 137496 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
49092 /* 137499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49093 /* 137503 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49094 /* 137507 */ // (ffloor:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
49095 /* 137507 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
49096 /* 137510 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
49097 /* 137514 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
49098 /* 137519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M),
49099 /* 137522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
49100 /* 137524 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
49101 /* 137526 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
49102 /* 137529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49103 /* 137535 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49104 /* 137541 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49105 /* 137544 */ GIR_RootConstrainSelectedInstOperands,
49106 /* 137545 */ // GIR_Coverage, 4388,
49107 /* 137545 */ GIR_EraseRootFromParent_Done,
49108 /* 137546 */ // Label 2805: @137546
49109 /* 137546 */ GIM_Reject,
49110 /* 137547 */ // Label 2803: @137547
49111 /* 137547 */ GIM_Reject,
49112 /* 137548 */ // Label 2794: @137548
49113 /* 137548 */ GIM_Reject,
49114 /* 137549 */ // Label 77: @137549
49115 /* 137549 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2813*/ GIMT_Encode4(137956),
49116 /* 137560 */ /*GILLT_s16*//*Label 2806*/ GIMT_Encode4(137612),
49117 /* 137564 */ /*GILLT_s32*//*Label 2807*/ GIMT_Encode4(137650),
49118 /* 137568 */ /*GILLT_s64*//*Label 2808*/ GIMT_Encode4(137688), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
49119 /* 137596 */ /*GILLT_v4s16*//*Label 2809*/ GIMT_Encode4(137726),
49120 /* 137600 */ /*GILLT_v8s16*//*Label 2810*/ GIMT_Encode4(137753),
49121 /* 137604 */ /*GILLT_v2s32*//*Label 2811*/ GIMT_Encode4(137841),
49122 /* 137608 */ /*GILLT_v4s32*//*Label 2812*/ GIMT_Encode4(137868),
49123 /* 137612 */ // Label 2806: @137612
49124 /* 137612 */ GIM_Try, /*On fail goto*//*Label 2814*/ GIMT_Encode4(137649), // Rule ID 705 //
49125 /* 137617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49126 /* 137620 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49127 /* 137623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49128 /* 137627 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49129 /* 137631 */ // (frint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTXH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
49130 /* 137631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXH),
49131 /* 137634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49132 /* 137636 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49133 /* 137638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49134 /* 137641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49135 /* 137647 */ GIR_RootConstrainSelectedInstOperands,
49136 /* 137648 */ // GIR_Coverage, 705,
49137 /* 137648 */ GIR_EraseRootFromParent_Done,
49138 /* 137649 */ // Label 2814: @137649
49139 /* 137649 */ GIM_Reject,
49140 /* 137650 */ // Label 2807: @137650
49141 /* 137650 */ GIM_Try, /*On fail goto*//*Label 2815*/ GIMT_Encode4(137687), // Rule ID 707 //
49142 /* 137655 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
49143 /* 137658 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49144 /* 137661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49145 /* 137665 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49146 /* 137669 */ // (frint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTXS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
49147 /* 137669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXS),
49148 /* 137672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49149 /* 137674 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49150 /* 137676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49151 /* 137679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49152 /* 137685 */ GIR_RootConstrainSelectedInstOperands,
49153 /* 137686 */ // GIR_Coverage, 707,
49154 /* 137686 */ GIR_EraseRootFromParent_Done,
49155 /* 137687 */ // Label 2815: @137687
49156 /* 137687 */ GIM_Reject,
49157 /* 137688 */ // Label 2808: @137688
49158 /* 137688 */ GIM_Try, /*On fail goto*//*Label 2816*/ GIMT_Encode4(137725), // Rule ID 709 //
49159 /* 137693 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
49160 /* 137696 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49161 /* 137699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49162 /* 137703 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49163 /* 137707 */ // (frint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTXD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
49164 /* 137707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXD),
49165 /* 137710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49166 /* 137712 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
49167 /* 137714 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49168 /* 137717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49169 /* 137723 */ GIR_RootConstrainSelectedInstOperands,
49170 /* 137724 */ // GIR_Coverage, 709,
49171 /* 137724 */ GIR_EraseRootFromParent_Done,
49172 /* 137725 */ // Label 2816: @137725
49173 /* 137725 */ GIM_Reject,
49174 /* 137726 */ // Label 2809: @137726
49175 /* 137726 */ GIM_Try, /*On fail goto*//*Label 2817*/ GIMT_Encode4(137752), // Rule ID 1866 //
49176 /* 137731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
49177 /* 137734 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
49178 /* 137737 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49179 /* 137741 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49180 /* 137745 */ // (frint:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTXNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
49181 /* 137745 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDh),
49182 /* 137750 */ GIR_RootConstrainSelectedInstOperands,
49183 /* 137751 */ // GIR_Coverage, 1866,
49184 /* 137751 */ GIR_Done,
49185 /* 137752 */ // Label 2817: @137752
49186 /* 137752 */ GIM_Reject,
49187 /* 137753 */ // Label 2810: @137753
49188 /* 137753 */ GIM_Try, /*On fail goto*//*Label 2818*/ GIMT_Encode4(137840),
49189 /* 137758 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
49190 /* 137761 */ GIM_Try, /*On fail goto*//*Label 2819*/ GIMT_Encode4(137784), // Rule ID 1868 //
49191 /* 137766 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
49192 /* 137769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49193 /* 137773 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49194 /* 137777 */ // (frint:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTXNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
49195 /* 137777 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQh),
49196 /* 137782 */ GIR_RootConstrainSelectedInstOperands,
49197 /* 137783 */ // GIR_Coverage, 1868,
49198 /* 137783 */ GIR_Done,
49199 /* 137784 */ // Label 2819: @137784
49200 /* 137784 */ GIM_Try, /*On fail goto*//*Label 2820*/ GIMT_Encode4(137839), // Rule ID 4352 //
49201 /* 137789 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
49202 /* 137792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49203 /* 137796 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49204 /* 137800 */ // (frint:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
49205 /* 137800 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
49206 /* 137803 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
49207 /* 137807 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
49208 /* 137812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X),
49209 /* 137815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
49210 /* 137817 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
49211 /* 137819 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
49212 /* 137822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49213 /* 137828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49214 /* 137834 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49215 /* 137837 */ GIR_RootConstrainSelectedInstOperands,
49216 /* 137838 */ // GIR_Coverage, 4352,
49217 /* 137838 */ GIR_EraseRootFromParent_Done,
49218 /* 137839 */ // Label 2820: @137839
49219 /* 137839 */ GIM_Reject,
49220 /* 137840 */ // Label 2818: @137840
49221 /* 137840 */ GIM_Reject,
49222 /* 137841 */ // Label 2811: @137841
49223 /* 137841 */ GIM_Try, /*On fail goto*//*Label 2821*/ GIMT_Encode4(137867), // Rule ID 1862 //
49224 /* 137846 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
49225 /* 137849 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
49226 /* 137852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49227 /* 137856 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49228 /* 137860 */ // (frint:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTXNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
49229 /* 137860 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDf),
49230 /* 137865 */ GIR_RootConstrainSelectedInstOperands,
49231 /* 137866 */ // GIR_Coverage, 1862,
49232 /* 137866 */ GIR_Done,
49233 /* 137867 */ // Label 2821: @137867
49234 /* 137867 */ GIM_Reject,
49235 /* 137868 */ // Label 2812: @137868
49236 /* 137868 */ GIM_Try, /*On fail goto*//*Label 2822*/ GIMT_Encode4(137955),
49237 /* 137873 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
49238 /* 137876 */ GIM_Try, /*On fail goto*//*Label 2823*/ GIMT_Encode4(137899), // Rule ID 1864 //
49239 /* 137881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
49240 /* 137884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49241 /* 137888 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49242 /* 137892 */ // (frint:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTXNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
49243 /* 137892 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQf),
49244 /* 137897 */ GIR_RootConstrainSelectedInstOperands,
49245 /* 137898 */ // GIR_Coverage, 1864,
49246 /* 137898 */ GIR_Done,
49247 /* 137899 */ // Label 2823: @137899
49248 /* 137899 */ GIM_Try, /*On fail goto*//*Label 2824*/ GIMT_Encode4(137954), // Rule ID 4376 //
49249 /* 137904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
49250 /* 137907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49251 /* 137911 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49252 /* 137915 */ // (frint:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
49253 /* 137915 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
49254 /* 137918 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
49255 /* 137922 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
49256 /* 137927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X),
49257 /* 137930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
49258 /* 137932 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
49259 /* 137934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
49260 /* 137937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49261 /* 137943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49262 /* 137949 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49263 /* 137952 */ GIR_RootConstrainSelectedInstOperands,
49264 /* 137953 */ // GIR_Coverage, 4376,
49265 /* 137953 */ GIR_EraseRootFromParent_Done,
49266 /* 137954 */ // Label 2824: @137954
49267 /* 137954 */ GIM_Reject,
49268 /* 137955 */ // Label 2822: @137955
49269 /* 137955 */ GIM_Reject,
49270 /* 137956 */ // Label 2813: @137956
49271 /* 137956 */ GIM_Reject,
49272 /* 137957 */ // Label 78: @137957
49273 /* 137957 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2828*/ GIMT_Encode4(138094),
49274 /* 137968 */ /*GILLT_s16*//*Label 2825*/ GIMT_Encode4(137980),
49275 /* 137972 */ /*GILLT_s32*//*Label 2826*/ GIMT_Encode4(138018),
49276 /* 137976 */ /*GILLT_s64*//*Label 2827*/ GIMT_Encode4(138056),
49277 /* 137980 */ // Label 2825: @137980
49278 /* 137980 */ GIM_Try, /*On fail goto*//*Label 2829*/ GIMT_Encode4(138017), // Rule ID 699 //
49279 /* 137985 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49280 /* 137988 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49281 /* 137991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49282 /* 137995 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49283 /* 137999 */ // (fnearbyint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTRH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
49284 /* 137999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRH),
49285 /* 138002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49286 /* 138004 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49287 /* 138006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49288 /* 138009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49289 /* 138015 */ GIR_RootConstrainSelectedInstOperands,
49290 /* 138016 */ // GIR_Coverage, 699,
49291 /* 138016 */ GIR_EraseRootFromParent_Done,
49292 /* 138017 */ // Label 2829: @138017
49293 /* 138017 */ GIM_Reject,
49294 /* 138018 */ // Label 2826: @138018
49295 /* 138018 */ GIM_Try, /*On fail goto*//*Label 2830*/ GIMT_Encode4(138055), // Rule ID 701 //
49296 /* 138023 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
49297 /* 138026 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49298 /* 138029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49299 /* 138033 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49300 /* 138037 */ // (fnearbyint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
49301 /* 138037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRS),
49302 /* 138040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49303 /* 138042 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49304 /* 138044 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49305 /* 138047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49306 /* 138053 */ GIR_RootConstrainSelectedInstOperands,
49307 /* 138054 */ // GIR_Coverage, 701,
49308 /* 138054 */ GIR_EraseRootFromParent_Done,
49309 /* 138055 */ // Label 2830: @138055
49310 /* 138055 */ GIM_Reject,
49311 /* 138056 */ // Label 2827: @138056
49312 /* 138056 */ GIM_Try, /*On fail goto*//*Label 2831*/ GIMT_Encode4(138093), // Rule ID 703 //
49313 /* 138061 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
49314 /* 138064 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49315 /* 138067 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49316 /* 138071 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49317 /* 138075 */ // (fnearbyint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTRD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
49318 /* 138075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRD),
49319 /* 138078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49320 /* 138080 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
49321 /* 138082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49322 /* 138085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49323 /* 138091 */ GIR_RootConstrainSelectedInstOperands,
49324 /* 138092 */ // GIR_Coverage, 703,
49325 /* 138092 */ GIR_EraseRootFromParent_Done,
49326 /* 138093 */ // Label 2831: @138093
49327 /* 138093 */ GIM_Reject,
49328 /* 138094 */ // Label 2828: @138094
49329 /* 138094 */ GIM_Reject,
49330 /* 138095 */ // Label 79: @138095
49331 /* 138095 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2835*/ GIMT_Encode4(138259),
49332 /* 138106 */ /*GILLT_s16*//*Label 2832*/ GIMT_Encode4(138118),
49333 /* 138110 */ /*GILLT_s32*//*Label 2833*/ GIMT_Encode4(138165),
49334 /* 138114 */ /*GILLT_s64*//*Label 2834*/ GIMT_Encode4(138212),
49335 /* 138118 */ // Label 2832: @138118
49336 /* 138118 */ GIM_Try, /*On fail goto*//*Label 2836*/ GIMT_Encode4(138164), // Rule ID 620 //
49337 /* 138123 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49338 /* 138126 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49339 /* 138129 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
49340 /* 138132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49341 /* 138136 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49342 /* 138140 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49343 /* 138144 */ // (strict_fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49344 /* 138144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH),
49345 /* 138147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49346 /* 138149 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49347 /* 138151 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49348 /* 138153 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49349 /* 138156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49350 /* 138162 */ GIR_RootConstrainSelectedInstOperands,
49351 /* 138163 */ // GIR_Coverage, 620,
49352 /* 138163 */ GIR_EraseRootFromParent_Done,
49353 /* 138164 */ // Label 2836: @138164
49354 /* 138164 */ GIM_Reject,
49355 /* 138165 */ // Label 2833: @138165
49356 /* 138165 */ GIM_Try, /*On fail goto*//*Label 2837*/ GIMT_Encode4(138211), // Rule ID 618 //
49357 /* 138170 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
49358 /* 138173 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49359 /* 138176 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49360 /* 138179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49361 /* 138183 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49362 /* 138187 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49363 /* 138191 */ // (strict_fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49364 /* 138191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS),
49365 /* 138194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49366 /* 138196 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49367 /* 138198 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49368 /* 138200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49369 /* 138203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49370 /* 138209 */ GIR_RootConstrainSelectedInstOperands,
49371 /* 138210 */ // GIR_Coverage, 618,
49372 /* 138210 */ GIR_EraseRootFromParent_Done,
49373 /* 138211 */ // Label 2837: @138211
49374 /* 138211 */ GIM_Reject,
49375 /* 138212 */ // Label 2834: @138212
49376 /* 138212 */ GIM_Try, /*On fail goto*//*Label 2838*/ GIMT_Encode4(138258), // Rule ID 616 //
49377 /* 138217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
49378 /* 138220 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49379 /* 138223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49380 /* 138226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49381 /* 138230 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49382 /* 138234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49383 /* 138238 */ // (strict_fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
49384 /* 138238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD),
49385 /* 138241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49386 /* 138243 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
49387 /* 138245 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
49388 /* 138247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49389 /* 138250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49390 /* 138256 */ GIR_RootConstrainSelectedInstOperands,
49391 /* 138257 */ // GIR_Coverage, 616,
49392 /* 138257 */ GIR_EraseRootFromParent_Done,
49393 /* 138258 */ // Label 2838: @138258
49394 /* 138258 */ GIM_Reject,
49395 /* 138259 */ // Label 2835: @138259
49396 /* 138259 */ GIM_Reject,
49397 /* 138260 */ // Label 80: @138260
49398 /* 138260 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2842*/ GIMT_Encode4(138424),
49399 /* 138271 */ /*GILLT_s16*//*Label 2839*/ GIMT_Encode4(138283),
49400 /* 138275 */ /*GILLT_s32*//*Label 2840*/ GIMT_Encode4(138330),
49401 /* 138279 */ /*GILLT_s64*//*Label 2841*/ GIMT_Encode4(138377),
49402 /* 138283 */ // Label 2839: @138283
49403 /* 138283 */ GIM_Try, /*On fail goto*//*Label 2843*/ GIMT_Encode4(138329), // Rule ID 626 //
49404 /* 138288 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49405 /* 138291 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49406 /* 138294 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
49407 /* 138297 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49408 /* 138301 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49409 /* 138305 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49410 /* 138309 */ // (strict_fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49411 /* 138309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH),
49412 /* 138312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49413 /* 138314 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49414 /* 138316 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49415 /* 138318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49416 /* 138321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49417 /* 138327 */ GIR_RootConstrainSelectedInstOperands,
49418 /* 138328 */ // GIR_Coverage, 626,
49419 /* 138328 */ GIR_EraseRootFromParent_Done,
49420 /* 138329 */ // Label 2843: @138329
49421 /* 138329 */ GIM_Reject,
49422 /* 138330 */ // Label 2840: @138330
49423 /* 138330 */ GIM_Try, /*On fail goto*//*Label 2844*/ GIMT_Encode4(138376), // Rule ID 624 //
49424 /* 138335 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
49425 /* 138338 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49426 /* 138341 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49427 /* 138344 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49428 /* 138348 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49429 /* 138352 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49430 /* 138356 */ // (strict_fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49431 /* 138356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS),
49432 /* 138359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49433 /* 138361 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49434 /* 138363 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49435 /* 138365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49436 /* 138368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49437 /* 138374 */ GIR_RootConstrainSelectedInstOperands,
49438 /* 138375 */ // GIR_Coverage, 624,
49439 /* 138375 */ GIR_EraseRootFromParent_Done,
49440 /* 138376 */ // Label 2844: @138376
49441 /* 138376 */ GIM_Reject,
49442 /* 138377 */ // Label 2841: @138377
49443 /* 138377 */ GIM_Try, /*On fail goto*//*Label 2845*/ GIMT_Encode4(138423), // Rule ID 622 //
49444 /* 138382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
49445 /* 138385 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49446 /* 138388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49447 /* 138391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49448 /* 138395 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49449 /* 138399 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49450 /* 138403 */ // (strict_fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
49451 /* 138403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD),
49452 /* 138406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49453 /* 138408 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
49454 /* 138410 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
49455 /* 138412 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49456 /* 138415 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49457 /* 138421 */ GIR_RootConstrainSelectedInstOperands,
49458 /* 138422 */ // GIR_Coverage, 622,
49459 /* 138422 */ GIR_EraseRootFromParent_Done,
49460 /* 138423 */ // Label 2845: @138423
49461 /* 138423 */ GIM_Reject,
49462 /* 138424 */ // Label 2842: @138424
49463 /* 138424 */ GIM_Reject,
49464 /* 138425 */ // Label 81: @138425
49465 /* 138425 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2849*/ GIMT_Encode4(138589),
49466 /* 138436 */ /*GILLT_s16*//*Label 2846*/ GIMT_Encode4(138448),
49467 /* 138440 */ /*GILLT_s32*//*Label 2847*/ GIMT_Encode4(138495),
49468 /* 138444 */ /*GILLT_s64*//*Label 2848*/ GIMT_Encode4(138542),
49469 /* 138448 */ // Label 2846: @138448
49470 /* 138448 */ GIM_Try, /*On fail goto*//*Label 2850*/ GIMT_Encode4(138494), // Rule ID 638 //
49471 /* 138453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49472 /* 138456 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49473 /* 138459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
49474 /* 138462 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49475 /* 138466 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49476 /* 138470 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49477 /* 138474 */ // (strict_fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49478 /* 138474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH),
49479 /* 138477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49480 /* 138479 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49481 /* 138481 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49482 /* 138483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49483 /* 138486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49484 /* 138492 */ GIR_RootConstrainSelectedInstOperands,
49485 /* 138493 */ // GIR_Coverage, 638,
49486 /* 138493 */ GIR_EraseRootFromParent_Done,
49487 /* 138494 */ // Label 2850: @138494
49488 /* 138494 */ GIM_Reject,
49489 /* 138495 */ // Label 2847: @138495
49490 /* 138495 */ GIM_Try, /*On fail goto*//*Label 2851*/ GIMT_Encode4(138541), // Rule ID 636 //
49491 /* 138500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
49492 /* 138503 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49493 /* 138506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49494 /* 138509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49495 /* 138513 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49496 /* 138517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49497 /* 138521 */ // (strict_fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49498 /* 138521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS),
49499 /* 138524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49500 /* 138526 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49501 /* 138528 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49502 /* 138530 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49503 /* 138533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49504 /* 138539 */ GIR_RootConstrainSelectedInstOperands,
49505 /* 138540 */ // GIR_Coverage, 636,
49506 /* 138540 */ GIR_EraseRootFromParent_Done,
49507 /* 138541 */ // Label 2851: @138541
49508 /* 138541 */ GIM_Reject,
49509 /* 138542 */ // Label 2848: @138542
49510 /* 138542 */ GIM_Try, /*On fail goto*//*Label 2852*/ GIMT_Encode4(138588), // Rule ID 634 //
49511 /* 138547 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
49512 /* 138550 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49513 /* 138553 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49514 /* 138556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49515 /* 138560 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49516 /* 138564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49517 /* 138568 */ // (strict_fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
49518 /* 138568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD),
49519 /* 138571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49520 /* 138573 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
49521 /* 138575 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
49522 /* 138577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49523 /* 138580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49524 /* 138586 */ GIR_RootConstrainSelectedInstOperands,
49525 /* 138587 */ // GIR_Coverage, 634,
49526 /* 138587 */ GIR_EraseRootFromParent_Done,
49527 /* 138588 */ // Label 2852: @138588
49528 /* 138588 */ GIM_Reject,
49529 /* 138589 */ // Label 2849: @138589
49530 /* 138589 */ GIM_Reject,
49531 /* 138590 */ // Label 82: @138590
49532 /* 138590 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2856*/ GIMT_Encode4(138754),
49533 /* 138601 */ /*GILLT_s16*//*Label 2853*/ GIMT_Encode4(138613),
49534 /* 138605 */ /*GILLT_s32*//*Label 2854*/ GIMT_Encode4(138660),
49535 /* 138609 */ /*GILLT_s64*//*Label 2855*/ GIMT_Encode4(138707),
49536 /* 138613 */ // Label 2853: @138613
49537 /* 138613 */ GIM_Try, /*On fail goto*//*Label 2857*/ GIMT_Encode4(138659), // Rule ID 632 //
49538 /* 138618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49539 /* 138621 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49540 /* 138624 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
49541 /* 138627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49542 /* 138631 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49543 /* 138635 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49544 /* 138639 */ // (strict_fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49545 /* 138639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH),
49546 /* 138642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49547 /* 138644 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49548 /* 138646 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49549 /* 138648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49550 /* 138651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49551 /* 138657 */ GIR_RootConstrainSelectedInstOperands,
49552 /* 138658 */ // GIR_Coverage, 632,
49553 /* 138658 */ GIR_EraseRootFromParent_Done,
49554 /* 138659 */ // Label 2857: @138659
49555 /* 138659 */ GIM_Reject,
49556 /* 138660 */ // Label 2854: @138660
49557 /* 138660 */ GIM_Try, /*On fail goto*//*Label 2858*/ GIMT_Encode4(138706), // Rule ID 630 //
49558 /* 138665 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2),
49559 /* 138668 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49560 /* 138671 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49561 /* 138674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49562 /* 138678 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49563 /* 138682 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49564 /* 138686 */ // (strict_fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49565 /* 138686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS),
49566 /* 138689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49567 /* 138691 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49568 /* 138693 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49569 /* 138695 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49570 /* 138698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49571 /* 138704 */ GIR_RootConstrainSelectedInstOperands,
49572 /* 138705 */ // GIR_Coverage, 630,
49573 /* 138705 */ GIR_EraseRootFromParent_Done,
49574 /* 138706 */ // Label 2858: @138706
49575 /* 138706 */ GIM_Reject,
49576 /* 138707 */ // Label 2855: @138707
49577 /* 138707 */ GIM_Try, /*On fail goto*//*Label 2859*/ GIMT_Encode4(138753), // Rule ID 628 //
49578 /* 138712 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
49579 /* 138715 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49580 /* 138718 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49581 /* 138721 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49582 /* 138725 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49583 /* 138729 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49584 /* 138733 */ // (strict_fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
49585 /* 138733 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD),
49586 /* 138736 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49587 /* 138738 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
49588 /* 138740 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
49589 /* 138742 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49590 /* 138745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49591 /* 138751 */ GIR_RootConstrainSelectedInstOperands,
49592 /* 138752 */ // GIR_Coverage, 628,
49593 /* 138752 */ GIR_EraseRootFromParent_Done,
49594 /* 138753 */ // Label 2859: @138753
49595 /* 138753 */ GIM_Reject,
49596 /* 138754 */ // Label 2856: @138754
49597 /* 138754 */ GIM_Reject,
49598 /* 138755 */ // Label 83: @138755
49599 /* 138755 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2863*/ GIMT_Encode4(139939),
49600 /* 138766 */ /*GILLT_s16*//*Label 2860*/ GIMT_Encode4(138778),
49601 /* 138770 */ /*GILLT_s32*//*Label 2861*/ GIMT_Encode4(139165),
49602 /* 138774 */ /*GILLT_s64*//*Label 2862*/ GIMT_Encode4(139552),
49603 /* 138778 */ // Label 2860: @138778
49604 /* 138778 */ GIM_Try, /*On fail goto*//*Label 2864*/ GIMT_Encode4(139164),
49605 /* 138783 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49606 /* 138786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
49607 /* 138789 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
49608 /* 138792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49609 /* 138796 */ GIM_Try, /*On fail goto*//*Label 2865*/ GIMT_Encode4(138870), // Rule ID 2760 //
49610 /* 138801 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49611 /* 138804 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49612 /* 138808 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49613 /* 138812 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
49614 /* 138816 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49615 /* 138821 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49616 /* 138825 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
49617 /* 138829 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
49618 /* 138833 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
49619 /* 138837 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49620 /* 138842 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
49621 /* 138844 */ // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49622 /* 138844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
49623 /* 138847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49624 /* 138849 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
49625 /* 138853 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49626 /* 138857 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49627 /* 138859 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49628 /* 138862 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49629 /* 138868 */ GIR_RootConstrainSelectedInstOperands,
49630 /* 138869 */ // GIR_Coverage, 2760,
49631 /* 138869 */ GIR_EraseRootFromParent_Done,
49632 /* 138870 */ // Label 2865: @138870
49633 /* 138870 */ GIM_Try, /*On fail goto*//*Label 2866*/ GIMT_Encode4(138944), // Rule ID 6311 //
49634 /* 138875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49635 /* 138878 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49636 /* 138882 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
49637 /* 138886 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49638 /* 138890 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
49639 /* 138894 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49640 /* 138899 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
49641 /* 138903 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
49642 /* 138907 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
49643 /* 138911 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49644 /* 138916 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
49645 /* 138918 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49646 /* 138918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
49647 /* 138921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49648 /* 138923 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
49649 /* 138927 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49650 /* 138931 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49651 /* 138933 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49652 /* 138936 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49653 /* 138942 */ GIR_RootConstrainSelectedInstOperands,
49654 /* 138943 */ // GIR_Coverage, 6311,
49655 /* 138943 */ GIR_EraseRootFromParent_Done,
49656 /* 138944 */ // Label 2866: @138944
49657 /* 138944 */ GIM_Try, /*On fail goto*//*Label 2867*/ GIMT_Encode4(139003), // Rule ID 2740 //
49658 /* 138949 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49659 /* 138952 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49660 /* 138956 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49661 /* 138960 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
49662 /* 138964 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49663 /* 138969 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49664 /* 138973 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49665 /* 138977 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49666 /* 138979 */ // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49667 /* 138979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
49668 /* 138982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49669 /* 138984 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
49670 /* 138986 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49671 /* 138990 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49672 /* 138992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49673 /* 138995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49674 /* 139001 */ GIR_RootConstrainSelectedInstOperands,
49675 /* 139002 */ // GIR_Coverage, 2740,
49676 /* 139002 */ GIR_EraseRootFromParent_Done,
49677 /* 139003 */ // Label 2867: @139003
49678 /* 139003 */ GIM_Try, /*On fail goto*//*Label 2868*/ GIMT_Encode4(139062), // Rule ID 6305 //
49679 /* 139008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49680 /* 139011 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49681 /* 139015 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
49682 /* 139019 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49683 /* 139023 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
49684 /* 139027 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49685 /* 139032 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49686 /* 139036 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49687 /* 139038 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49688 /* 139038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
49689 /* 139041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49690 /* 139043 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
49691 /* 139045 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49692 /* 139049 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49693 /* 139051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49694 /* 139054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49695 /* 139060 */ GIR_RootConstrainSelectedInstOperands,
49696 /* 139061 */ // GIR_Coverage, 6305,
49697 /* 139061 */ GIR_EraseRootFromParent_Done,
49698 /* 139062 */ // Label 2868: @139062
49699 /* 139062 */ GIM_Try, /*On fail goto*//*Label 2869*/ GIMT_Encode4(139121), // Rule ID 2774 //
49700 /* 139067 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49701 /* 139070 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49702 /* 139074 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49703 /* 139078 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49704 /* 139082 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49705 /* 139086 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
49706 /* 139090 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49707 /* 139095 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49708 /* 139097 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49709 /* 139097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
49710 /* 139100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49711 /* 139102 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
49712 /* 139106 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49713 /* 139108 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49714 /* 139110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49715 /* 139113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49716 /* 139119 */ GIR_RootConstrainSelectedInstOperands,
49717 /* 139120 */ // GIR_Coverage, 2774,
49718 /* 139120 */ GIR_EraseRootFromParent_Done,
49719 /* 139121 */ // Label 2869: @139121
49720 /* 139121 */ GIM_Try, /*On fail goto*//*Label 2870*/ GIMT_Encode4(139163), // Rule ID 2722 //
49721 /* 139126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49722 /* 139129 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49723 /* 139133 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49724 /* 139137 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49725 /* 139141 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49726 /* 139141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH),
49727 /* 139144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49728 /* 139146 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
49729 /* 139148 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49730 /* 139150 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49731 /* 139152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49732 /* 139155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49733 /* 139161 */ GIR_RootConstrainSelectedInstOperands,
49734 /* 139162 */ // GIR_Coverage, 2722,
49735 /* 139162 */ GIR_EraseRootFromParent_Done,
49736 /* 139163 */ // Label 2870: @139163
49737 /* 139163 */ GIM_Reject,
49738 /* 139164 */ // Label 2864: @139164
49739 /* 139164 */ GIM_Reject,
49740 /* 139165 */ // Label 2861: @139165
49741 /* 139165 */ GIM_Try, /*On fail goto*//*Label 2871*/ GIMT_Encode4(139551),
49742 /* 139170 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49743 /* 139173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49744 /* 139176 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49745 /* 139179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49746 /* 139183 */ GIM_Try, /*On fail goto*//*Label 2872*/ GIMT_Encode4(139257), // Rule ID 2758 //
49747 /* 139188 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
49748 /* 139191 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49749 /* 139195 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49750 /* 139199 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
49751 /* 139203 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49752 /* 139208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49753 /* 139212 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
49754 /* 139216 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
49755 /* 139220 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
49756 /* 139224 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49757 /* 139229 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
49758 /* 139231 */ // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49759 /* 139231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
49760 /* 139234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49761 /* 139236 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
49762 /* 139240 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49763 /* 139244 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49764 /* 139246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49765 /* 139249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49766 /* 139255 */ GIR_RootConstrainSelectedInstOperands,
49767 /* 139256 */ // GIR_Coverage, 2758,
49768 /* 139256 */ GIR_EraseRootFromParent_Done,
49769 /* 139257 */ // Label 2872: @139257
49770 /* 139257 */ GIM_Try, /*On fail goto*//*Label 2873*/ GIMT_Encode4(139331), // Rule ID 6309 //
49771 /* 139262 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
49772 /* 139265 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49773 /* 139269 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
49774 /* 139273 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49775 /* 139277 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
49776 /* 139281 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49777 /* 139286 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
49778 /* 139290 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
49779 /* 139294 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
49780 /* 139298 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49781 /* 139303 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
49782 /* 139305 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49783 /* 139305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
49784 /* 139308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49785 /* 139310 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
49786 /* 139314 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49787 /* 139318 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49788 /* 139320 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49789 /* 139323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49790 /* 139329 */ GIR_RootConstrainSelectedInstOperands,
49791 /* 139330 */ // GIR_Coverage, 6309,
49792 /* 139330 */ GIR_EraseRootFromParent_Done,
49793 /* 139331 */ // Label 2873: @139331
49794 /* 139331 */ GIM_Try, /*On fail goto*//*Label 2874*/ GIMT_Encode4(139390), // Rule ID 2738 //
49795 /* 139336 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
49796 /* 139339 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49797 /* 139343 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49798 /* 139347 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
49799 /* 139351 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49800 /* 139356 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49801 /* 139360 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49802 /* 139364 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49803 /* 139366 */ // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49804 /* 139366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
49805 /* 139369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49806 /* 139371 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
49807 /* 139373 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49808 /* 139377 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49809 /* 139379 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49810 /* 139382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49811 /* 139388 */ GIR_RootConstrainSelectedInstOperands,
49812 /* 139389 */ // GIR_Coverage, 2738,
49813 /* 139389 */ GIR_EraseRootFromParent_Done,
49814 /* 139390 */ // Label 2874: @139390
49815 /* 139390 */ GIM_Try, /*On fail goto*//*Label 2875*/ GIMT_Encode4(139449), // Rule ID 6303 //
49816 /* 139395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
49817 /* 139398 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49818 /* 139402 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
49819 /* 139406 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49820 /* 139410 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
49821 /* 139414 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49822 /* 139419 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49823 /* 139423 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49824 /* 139425 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49825 /* 139425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
49826 /* 139428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49827 /* 139430 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
49828 /* 139432 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49829 /* 139436 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49830 /* 139438 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49831 /* 139441 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49832 /* 139447 */ GIR_RootConstrainSelectedInstOperands,
49833 /* 139448 */ // GIR_Coverage, 6303,
49834 /* 139448 */ GIR_EraseRootFromParent_Done,
49835 /* 139449 */ // Label 2875: @139449
49836 /* 139449 */ GIM_Try, /*On fail goto*//*Label 2876*/ GIMT_Encode4(139508), // Rule ID 2772 //
49837 /* 139454 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
49838 /* 139457 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49839 /* 139461 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49840 /* 139465 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49841 /* 139469 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49842 /* 139473 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
49843 /* 139477 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49844 /* 139482 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49845 /* 139484 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49846 /* 139484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
49847 /* 139487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49848 /* 139489 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
49849 /* 139493 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49850 /* 139495 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49851 /* 139497 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49852 /* 139500 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49853 /* 139506 */ GIR_RootConstrainSelectedInstOperands,
49854 /* 139507 */ // GIR_Coverage, 2772,
49855 /* 139507 */ GIR_EraseRootFromParent_Done,
49856 /* 139508 */ // Label 2876: @139508
49857 /* 139508 */ GIM_Try, /*On fail goto*//*Label 2877*/ GIMT_Encode4(139550), // Rule ID 2720 //
49858 /* 139513 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
49859 /* 139516 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49860 /* 139520 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49861 /* 139524 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49862 /* 139528 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49863 /* 139528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS),
49864 /* 139531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49865 /* 139533 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
49866 /* 139535 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49867 /* 139537 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49868 /* 139539 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49869 /* 139542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49870 /* 139548 */ GIR_RootConstrainSelectedInstOperands,
49871 /* 139549 */ // GIR_Coverage, 2720,
49872 /* 139549 */ GIR_EraseRootFromParent_Done,
49873 /* 139550 */ // Label 2877: @139550
49874 /* 139550 */ GIM_Reject,
49875 /* 139551 */ // Label 2871: @139551
49876 /* 139551 */ GIM_Reject,
49877 /* 139552 */ // Label 2862: @139552
49878 /* 139552 */ GIM_Try, /*On fail goto*//*Label 2878*/ GIMT_Encode4(139938),
49879 /* 139557 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49880 /* 139560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49881 /* 139563 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
49882 /* 139566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49883 /* 139570 */ GIM_Try, /*On fail goto*//*Label 2879*/ GIMT_Encode4(139644), // Rule ID 2756 //
49884 /* 139575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
49885 /* 139578 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49886 /* 139582 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49887 /* 139586 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
49888 /* 139590 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49889 /* 139595 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49890 /* 139599 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
49891 /* 139603 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
49892 /* 139607 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
49893 /* 139611 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49894 /* 139616 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
49895 /* 139618 */ // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
49896 /* 139618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
49897 /* 139621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49898 /* 139623 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
49899 /* 139627 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
49900 /* 139631 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
49901 /* 139633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49902 /* 139636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49903 /* 139642 */ GIR_RootConstrainSelectedInstOperands,
49904 /* 139643 */ // GIR_Coverage, 2756,
49905 /* 139643 */ GIR_EraseRootFromParent_Done,
49906 /* 139644 */ // Label 2879: @139644
49907 /* 139644 */ GIM_Try, /*On fail goto*//*Label 2880*/ GIMT_Encode4(139718), // Rule ID 6307 //
49908 /* 139649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
49909 /* 139652 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49910 /* 139656 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
49911 /* 139660 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49912 /* 139664 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
49913 /* 139668 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49914 /* 139673 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
49915 /* 139677 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
49916 /* 139681 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
49917 /* 139685 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49918 /* 139690 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
49919 /* 139692 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
49920 /* 139692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
49921 /* 139695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49922 /* 139697 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
49923 /* 139701 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
49924 /* 139705 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
49925 /* 139707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49926 /* 139710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49927 /* 139716 */ GIR_RootConstrainSelectedInstOperands,
49928 /* 139717 */ // GIR_Coverage, 6307,
49929 /* 139717 */ GIR_EraseRootFromParent_Done,
49930 /* 139718 */ // Label 2880: @139718
49931 /* 139718 */ GIM_Try, /*On fail goto*//*Label 2881*/ GIMT_Encode4(139777), // Rule ID 2736 //
49932 /* 139723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
49933 /* 139726 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49934 /* 139730 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49935 /* 139734 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
49936 /* 139738 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49937 /* 139743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49938 /* 139747 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49939 /* 139751 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49940 /* 139753 */ // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
49941 /* 139753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
49942 /* 139756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49943 /* 139758 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
49944 /* 139760 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
49945 /* 139764 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
49946 /* 139766 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49947 /* 139769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49948 /* 139775 */ GIR_RootConstrainSelectedInstOperands,
49949 /* 139776 */ // GIR_Coverage, 2736,
49950 /* 139776 */ GIR_EraseRootFromParent_Done,
49951 /* 139777 */ // Label 2881: @139777
49952 /* 139777 */ GIM_Try, /*On fail goto*//*Label 2882*/ GIMT_Encode4(139836), // Rule ID 6301 //
49953 /* 139782 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
49954 /* 139785 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49955 /* 139789 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
49956 /* 139793 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49957 /* 139797 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
49958 /* 139801 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49959 /* 139806 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49960 /* 139810 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49961 /* 139812 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
49962 /* 139812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
49963 /* 139815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49964 /* 139817 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
49965 /* 139819 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
49966 /* 139823 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
49967 /* 139825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49968 /* 139828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49969 /* 139834 */ GIR_RootConstrainSelectedInstOperands,
49970 /* 139835 */ // GIR_Coverage, 6301,
49971 /* 139835 */ GIR_EraseRootFromParent_Done,
49972 /* 139836 */ // Label 2882: @139836
49973 /* 139836 */ GIM_Try, /*On fail goto*//*Label 2883*/ GIMT_Encode4(139895), // Rule ID 2770 //
49974 /* 139841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
49975 /* 139844 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49976 /* 139848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49977 /* 139852 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49978 /* 139856 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49979 /* 139860 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
49980 /* 139864 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49981 /* 139869 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49982 /* 139871 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
49983 /* 139871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
49984 /* 139874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49985 /* 139876 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin
49986 /* 139880 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
49987 /* 139882 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
49988 /* 139884 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49989 /* 139887 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49990 /* 139893 */ GIR_RootConstrainSelectedInstOperands,
49991 /* 139894 */ // GIR_Coverage, 2770,
49992 /* 139894 */ GIR_EraseRootFromParent_Done,
49993 /* 139895 */ // Label 2883: @139895
49994 /* 139895 */ GIM_Try, /*On fail goto*//*Label 2884*/ GIMT_Encode4(139937), // Rule ID 2718 //
49995 /* 139900 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
49996 /* 139903 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49997 /* 139907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49998 /* 139911 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49999 /* 139915 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
50000 /* 139915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD),
50001 /* 139918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
50002 /* 139920 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
50003 /* 139922 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
50004 /* 139924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
50005 /* 139926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
50006 /* 139929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50007 /* 139935 */ GIR_RootConstrainSelectedInstOperands,
50008 /* 139936 */ // GIR_Coverage, 2718,
50009 /* 139936 */ GIR_EraseRootFromParent_Done,
50010 /* 139937 */ // Label 2884: @139937
50011 /* 139937 */ GIM_Reject,
50012 /* 139938 */ // Label 2878: @139938
50013 /* 139938 */ GIM_Reject,
50014 /* 139939 */ // Label 2863: @139939
50015 /* 139939 */ GIM_Reject,
50016 /* 139940 */ // Label 84: @139940
50017 /* 139940 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2888*/ GIMT_Encode4(140077),
50018 /* 139951 */ /*GILLT_s16*//*Label 2885*/ GIMT_Encode4(139963),
50019 /* 139955 */ /*GILLT_s32*//*Label 2886*/ GIMT_Encode4(140001),
50020 /* 139959 */ /*GILLT_s64*//*Label 2887*/ GIMT_Encode4(140039),
50021 /* 139963 */ // Label 2885: @139963
50022 /* 139963 */ GIM_Try, /*On fail goto*//*Label 2889*/ GIMT_Encode4(140000), // Rule ID 738 //
50023 /* 139968 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
50024 /* 139971 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
50025 /* 139974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
50026 /* 139978 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
50027 /* 139982 */ // (strict_fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
50028 /* 139982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH),
50029 /* 139985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
50030 /* 139987 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
50031 /* 139989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
50032 /* 139992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50033 /* 139998 */ GIR_RootConstrainSelectedInstOperands,
50034 /* 139999 */ // GIR_Coverage, 738,
50035 /* 139999 */ GIR_EraseRootFromParent_Done,
50036 /* 140000 */ // Label 2889: @140000
50037 /* 140000 */ GIM_Reject,
50038 /* 140001 */ // Label 2886: @140001
50039 /* 140001 */ GIM_Try, /*On fail goto*//*Label 2890*/ GIMT_Encode4(140038), // Rule ID 736 //
50040 /* 140006 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2),
50041 /* 140009 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
50042 /* 140012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
50043 /* 140016 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
50044 /* 140020 */ // (strict_fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
50045 /* 140020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS),
50046 /* 140023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
50047 /* 140025 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
50048 /* 140027 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
50049 /* 140030 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50050 /* 140036 */ GIR_RootConstrainSelectedInstOperands,
50051 /* 140037 */ // GIR_Coverage, 736,
50052 /* 140037 */ GIR_EraseRootFromParent_Done,
50053 /* 140038 */ // Label 2890: @140038
50054 /* 140038 */ GIM_Reject,
50055 /* 140039 */ // Label 2887: @140039
50056 /* 140039 */ GIM_Try, /*On fail goto*//*Label 2891*/ GIMT_Encode4(140076), // Rule ID 734 //
50057 /* 140044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
50058 /* 140047 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
50059 /* 140050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50060 /* 140054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50061 /* 140058 */ // (strict_fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
50062 /* 140058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD),
50063 /* 140061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
50064 /* 140063 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
50065 /* 140065 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
50066 /* 140068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50067 /* 140074 */ GIR_RootConstrainSelectedInstOperands,
50068 /* 140075 */ // GIR_Coverage, 734,
50069 /* 140075 */ GIR_EraseRootFromParent_Done,
50070 /* 140076 */ // Label 2891: @140076
50071 /* 140076 */ GIM_Reject,
50072 /* 140077 */ // Label 2888: @140077
50073 /* 140077 */ GIM_Reject,
50074 /* 140078 */ // Label 85: @140078
50075 /* 140078 */ GIM_Try, /*On fail goto*//*Label 2892*/ GIMT_Encode4(140093), // Rule ID 12 //
50076 /* 140083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
50077 /* 140086 */ // (trap) => (TRAP)
50078 /* 140086 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::TRAP),
50079 /* 140091 */ GIR_RootConstrainSelectedInstOperands,
50080 /* 140092 */ // GIR_Coverage, 12,
50081 /* 140092 */ GIR_Done,
50082 /* 140093 */ // Label 2892: @140093
50083 /* 140093 */ GIM_Try, /*On fail goto*//*Label 2893*/ GIMT_Encode4(140108), // Rule ID 284 //
50084 /* 140098 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb),
50085 /* 140101 */ // (trap) => (tTRAP)
50086 /* 140101 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tTRAP),
50087 /* 140106 */ GIR_RootConstrainSelectedInstOperands,
50088 /* 140107 */ // GIR_Coverage, 284,
50089 /* 140107 */ GIR_Done,
50090 /* 140108 */ // Label 2893: @140108
50091 /* 140108 */ GIM_Reject,
50092 /* 140109 */ // Label 86: @140109
50093 /* 140109 */ GIM_Try, /*On fail goto*//*Label 2894*/ GIMT_Encode4(140125), // Rule ID 2024 //
50094 /* 140114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsARM),
50095 /* 140117 */ // (debugtrap) => (BKPT 0:{ *:[i32] })
50096 /* 140117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BKPT),
50097 /* 140120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50098 /* 140123 */ GIR_RootConstrainSelectedInstOperands,
50099 /* 140124 */ // GIR_Coverage, 2024,
50100 /* 140124 */ GIR_EraseRootFromParent_Done,
50101 /* 140125 */ // Label 2894: @140125
50102 /* 140125 */ GIM_Try, /*On fail goto*//*Label 2895*/ GIMT_Encode4(140152), // Rule ID 2025 //
50103 /* 140130 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV5T),
50104 /* 140133 */ // (debugtrap) => (UDF 254:{ *:[i32] })
50105 /* 140133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF),
50106 /* 140136 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254),
50107 /* 140146 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
50108 /* 140150 */ GIR_RootConstrainSelectedInstOperands,
50109 /* 140151 */ // GIR_Coverage, 2025,
50110 /* 140151 */ GIR_EraseRootFromParent_Done,
50111 /* 140152 */ // Label 2895: @140152
50112 /* 140152 */ GIM_Try, /*On fail goto*//*Label 2896*/ GIMT_Encode4(140168), // Rule ID 2210 //
50113 /* 140157 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsThumb),
50114 /* 140160 */ // (debugtrap) => (tBKPT 0:{ *:[i32] })
50115 /* 140160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBKPT),
50116 /* 140163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50117 /* 140166 */ GIR_RootConstrainSelectedInstOperands,
50118 /* 140167 */ // GIR_Coverage, 2210,
50119 /* 140167 */ GIR_EraseRootFromParent_Done,
50120 /* 140168 */ // Label 2896: @140168
50121 /* 140168 */ GIM_Try, /*On fail goto*//*Label 2897*/ GIMT_Encode4(140195), // Rule ID 2211 //
50122 /* 140173 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_NoV5T),
50123 /* 140176 */ // (debugtrap) => (tUDF 254:{ *:[i32] })
50124 /* 140176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF),
50125 /* 140179 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254),
50126 /* 140189 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
50127 /* 140193 */ GIR_RootConstrainSelectedInstOperands,
50128 /* 140194 */ // GIR_Coverage, 2211,
50129 /* 140194 */ GIR_EraseRootFromParent_Done,
50130 /* 140195 */ // Label 2897: @140195
50131 /* 140195 */ GIM_Reject,
50132 /* 140196 */ // Label 87: @140196
50133 /* 140196 */ GIM_Try, /*On fail goto*//*Label 2898*/ GIMT_Encode4(140596),
50134 /* 140201 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
50135 /* 140204 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2902*/ GIMT_Encode4(140490),
50136 /* 140215 */ /*GILLT_v16s8*//*Label 2899*/ GIMT_Encode4(140235), GIMT_Encode4(0),
50137 /* 140223 */ /*GILLT_v8s16*//*Label 2900*/ GIMT_Encode4(140348), GIMT_Encode4(0),
50138 /* 140231 */ /*GILLT_v4s32*//*Label 2901*/ GIMT_Encode4(140419),
50139 /* 140235 */ // Label 2899: @140235
50140 /* 140235 */ GIM_Try, /*On fail goto*//*Label 2903*/ GIMT_Encode4(140347),
50141 /* 140240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
50142 /* 140244 */ GIM_Try, /*On fail goto*//*Label 2904*/ GIMT_Encode4(140310), // Rule ID 3622 //
50143 /* 140249 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50144 /* 140252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50145 /* 140256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
50146 /* 140260 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
50147 /* 140264 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
50148 /* 140268 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50149 /* 140273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50150 /* 140278 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50151 /* 140280 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)) => (MVE_VMLADAVu8:{ *:[i32] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
50152 /* 140280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8),
50153 /* 140283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50154 /* 140285 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
50155 /* 140289 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
50156 /* 140293 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50157 /* 140296 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50158 /* 140302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50159 /* 140308 */ GIR_RootConstrainSelectedInstOperands,
50160 /* 140309 */ // GIR_Coverage, 3622,
50161 /* 140309 */ GIR_EraseRootFromParent_Done,
50162 /* 140310 */ // Label 2904: @140310
50163 /* 140310 */ GIM_Try, /*On fail goto*//*Label 2905*/ GIMT_Encode4(140346), // Rule ID 3426 //
50164 /* 140315 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50165 /* 140318 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50166 /* 140322 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec) => (MVE_VADDVu8no_acc:{ *:[i32] } ?:{ *:[v16i8] }:$vec)
50167 /* 140322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8no_acc),
50168 /* 140325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
50169 /* 140327 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec
50170 /* 140329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50171 /* 140332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50172 /* 140338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50173 /* 140344 */ GIR_RootConstrainSelectedInstOperands,
50174 /* 140345 */ // GIR_Coverage, 3426,
50175 /* 140345 */ GIR_EraseRootFromParent_Done,
50176 /* 140346 */ // Label 2905: @140346
50177 /* 140346 */ GIM_Reject,
50178 /* 140347 */ // Label 2903: @140347
50179 /* 140347 */ GIM_Reject,
50180 /* 140348 */ // Label 2900: @140348
50181 /* 140348 */ GIM_Try, /*On fail goto*//*Label 2906*/ GIMT_Encode4(140418), // Rule ID 3619 //
50182 /* 140353 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50183 /* 140356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
50184 /* 140360 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50185 /* 140364 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
50186 /* 140368 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
50187 /* 140372 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
50188 /* 140376 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50189 /* 140381 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50190 /* 140386 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50191 /* 140388 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)) => (MVE_VMLADAVu16:{ *:[i32] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
50192 /* 140388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16),
50193 /* 140391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50194 /* 140393 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
50195 /* 140397 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
50196 /* 140401 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50197 /* 140404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50198 /* 140410 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50199 /* 140416 */ GIR_RootConstrainSelectedInstOperands,
50200 /* 140417 */ // GIR_Coverage, 3619,
50201 /* 140417 */ GIR_EraseRootFromParent_Done,
50202 /* 140418 */ // Label 2906: @140418
50203 /* 140418 */ GIM_Reject,
50204 /* 140419 */ // Label 2901: @140419
50205 /* 140419 */ GIM_Try, /*On fail goto*//*Label 2907*/ GIMT_Encode4(140489), // Rule ID 3618 //
50206 /* 140424 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50207 /* 140427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
50208 /* 140431 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50209 /* 140435 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
50210 /* 140439 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
50211 /* 140443 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
50212 /* 140447 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50213 /* 140452 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50214 /* 140457 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50215 /* 140459 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)) => (MVE_VMLADAVu32:{ *:[i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
50216 /* 140459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32),
50217 /* 140462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50218 /* 140464 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
50219 /* 140468 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
50220 /* 140472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50221 /* 140475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50222 /* 140481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50223 /* 140487 */ GIR_RootConstrainSelectedInstOperands,
50224 /* 140488 */ // GIR_Coverage, 3618,
50225 /* 140488 */ GIR_EraseRootFromParent_Done,
50226 /* 140489 */ // Label 2907: @140489
50227 /* 140489 */ GIM_Reject,
50228 /* 140490 */ // Label 2902: @140490
50229 /* 140490 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2910*/ GIMT_Encode4(140595),
50230 /* 140501 */ /*GILLT_v8s16*//*Label 2908*/ GIMT_Encode4(140513), GIMT_Encode4(0),
50231 /* 140509 */ /*GILLT_v4s32*//*Label 2909*/ GIMT_Encode4(140554),
50232 /* 140513 */ // Label 2908: @140513
50233 /* 140513 */ GIM_Try, /*On fail goto*//*Label 2911*/ GIMT_Encode4(140553), // Rule ID 3454 //
50234 /* 140518 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50235 /* 140521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
50236 /* 140525 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50237 /* 140529 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec) => (MVE_VADDVu16no_acc:{ *:[i32] } ?:{ *:[v8i16] }:$vec)
50238 /* 140529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16no_acc),
50239 /* 140532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
50240 /* 140534 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec
50241 /* 140536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50242 /* 140539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50243 /* 140545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50244 /* 140551 */ GIR_RootConstrainSelectedInstOperands,
50245 /* 140552 */ // GIR_Coverage, 3454,
50246 /* 140552 */ GIR_EraseRootFromParent_Done,
50247 /* 140553 */ // Label 2911: @140553
50248 /* 140553 */ GIM_Reject,
50249 /* 140554 */ // Label 2909: @140554
50250 /* 140554 */ GIM_Try, /*On fail goto*//*Label 2912*/ GIMT_Encode4(140594), // Rule ID 3464 //
50251 /* 140559 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50252 /* 140562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
50253 /* 140566 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50254 /* 140570 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec) => (MVE_VADDVu32no_acc:{ *:[i32] } ?:{ *:[v4i32] }:$vec)
50255 /* 140570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32no_acc),
50256 /* 140573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
50257 /* 140575 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec
50258 /* 140577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50259 /* 140580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50260 /* 140586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50261 /* 140592 */ GIR_RootConstrainSelectedInstOperands,
50262 /* 140593 */ // GIR_Coverage, 3464,
50263 /* 140593 */ GIR_EraseRootFromParent_Done,
50264 /* 140594 */ // Label 2912: @140594
50265 /* 140594 */ GIM_Reject,
50266 /* 140595 */ // Label 2910: @140595
50267 /* 140595 */ GIM_Reject,
50268 /* 140596 */ // Label 2898: @140596
50269 /* 140596 */ GIM_Reject,
50270 /* 140597 */ // Label 88: @140597
50271 /* 140597 */ GIM_Try, /*On fail goto*//*Label 2913*/ GIMT_Encode4(140864),
50272 /* 140602 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
50273 /* 140605 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2917*/ GIMT_Encode4(140863),
50274 /* 140616 */ /*GILLT_v16s8*//*Label 2914*/ GIMT_Encode4(140636), GIMT_Encode4(0),
50275 /* 140624 */ /*GILLT_v8s16*//*Label 2915*/ GIMT_Encode4(140712), GIMT_Encode4(0),
50276 /* 140632 */ /*GILLT_v4s32*//*Label 2916*/ GIMT_Encode4(140780),
50277 /* 140636 */ // Label 2914: @140636
50278 /* 140636 */ GIM_Try, /*On fail goto*//*Label 2918*/ GIMT_Encode4(140711), // Rule ID 3522 //
50279 /* 140641 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50280 /* 140644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50281 /* 140648 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50282 /* 140652 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVs8:{ *:[i32] } (t2MVNi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
50283 /* 140652 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50284 /* 140655 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
50285 /* 140659 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50286 /* 140664 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127,
50287 /* 140667 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50288 /* 140670 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50289 /* 140676 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50290 /* 140682 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50291 /* 140684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8),
50292 /* 140687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50293 /* 140689 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50294 /* 140692 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50295 /* 140694 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50296 /* 140697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50297 /* 140703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50298 /* 140709 */ GIR_RootConstrainSelectedInstOperands,
50299 /* 140710 */ // GIR_Coverage, 3522,
50300 /* 140710 */ GIR_EraseRootFromParent_Done,
50301 /* 140711 */ // Label 2918: @140711
50302 /* 140711 */ GIM_Reject,
50303 /* 140712 */ // Label 2915: @140712
50304 /* 140712 */ GIM_Try, /*On fail goto*//*Label 2919*/ GIMT_Encode4(140779), // Rule ID 3523 //
50305 /* 140717 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50306 /* 140720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50307 /* 140724 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50308 /* 140728 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVs16:{ *:[i32] } (t2MOVi32imm:{ *:[i32] } -32768:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
50309 /* 140728 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50310 /* 140731 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm),
50311 /* 140735 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50312 /* 140740 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744073709518848u),
50313 /* 140750 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50314 /* 140752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16),
50315 /* 140755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50316 /* 140757 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50317 /* 140760 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50318 /* 140762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50319 /* 140765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50320 /* 140771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50321 /* 140777 */ GIR_RootConstrainSelectedInstOperands,
50322 /* 140778 */ // GIR_Coverage, 3523,
50323 /* 140778 */ GIR_EraseRootFromParent_Done,
50324 /* 140779 */ // Label 2919: @140779
50325 /* 140779 */ GIM_Reject,
50326 /* 140780 */ // Label 2916: @140780
50327 /* 140780 */ GIM_Try, /*On fail goto*//*Label 2920*/ GIMT_Encode4(140862), // Rule ID 3524 //
50328 /* 140785 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50329 /* 140788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50330 /* 140792 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50331 /* 140796 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVs32:{ *:[i32] } (t2MOVi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
50332 /* 140796 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50333 /* 140799 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
50334 /* 140803 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50335 /* 140808 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744071562067968u),
50336 /* 140818 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50337 /* 140821 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50338 /* 140827 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50339 /* 140833 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50340 /* 140835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32),
50341 /* 140838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50342 /* 140840 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50343 /* 140843 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50344 /* 140845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50345 /* 140848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50346 /* 140854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50347 /* 140860 */ GIR_RootConstrainSelectedInstOperands,
50348 /* 140861 */ // GIR_Coverage, 3524,
50349 /* 140861 */ GIR_EraseRootFromParent_Done,
50350 /* 140862 */ // Label 2920: @140862
50351 /* 140862 */ GIM_Reject,
50352 /* 140863 */ // Label 2917: @140863
50353 /* 140863 */ GIM_Reject,
50354 /* 140864 */ // Label 2913: @140864
50355 /* 140864 */ GIM_Reject,
50356 /* 140865 */ // Label 89: @140865
50357 /* 140865 */ GIM_Try, /*On fail goto*//*Label 2921*/ GIMT_Encode4(141141),
50358 /* 140870 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
50359 /* 140873 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2925*/ GIMT_Encode4(141140),
50360 /* 140884 */ /*GILLT_v16s8*//*Label 2922*/ GIMT_Encode4(140904), GIMT_Encode4(0),
50361 /* 140892 */ /*GILLT_v8s16*//*Label 2923*/ GIMT_Encode4(140980), GIMT_Encode4(0),
50362 /* 140900 */ /*GILLT_v4s32*//*Label 2924*/ GIMT_Encode4(141057),
50363 /* 140904 */ // Label 2922: @140904
50364 /* 140904 */ GIM_Try, /*On fail goto*//*Label 2926*/ GIMT_Encode4(140979), // Rule ID 3528 //
50365 /* 140909 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50366 /* 140912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50367 /* 140916 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50368 /* 140920 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVs8:{ *:[i32] } (t2MOVi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
50369 /* 140920 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50370 /* 140923 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
50371 /* 140927 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50372 /* 140932 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127,
50373 /* 140935 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50374 /* 140938 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50375 /* 140944 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50376 /* 140950 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50377 /* 140952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8),
50378 /* 140955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50379 /* 140957 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50380 /* 140960 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50381 /* 140962 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50382 /* 140965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50383 /* 140971 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50384 /* 140977 */ GIR_RootConstrainSelectedInstOperands,
50385 /* 140978 */ // GIR_Coverage, 3528,
50386 /* 140978 */ GIR_EraseRootFromParent_Done,
50387 /* 140979 */ // Label 2926: @140979
50388 /* 140979 */ GIM_Reject,
50389 /* 140980 */ // Label 2923: @140980
50390 /* 140980 */ GIM_Try, /*On fail goto*//*Label 2927*/ GIMT_Encode4(141056), // Rule ID 3529 //
50391 /* 140985 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50392 /* 140988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50393 /* 140992 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50394 /* 140996 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVs16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 32767:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
50395 /* 140996 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50396 /* 140999 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16),
50397 /* 141003 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50398 /* 141008 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767),
50399 /* 141018 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50400 /* 141021 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50401 /* 141027 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50402 /* 141029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16),
50403 /* 141032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50404 /* 141034 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50405 /* 141037 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50406 /* 141039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50407 /* 141042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50408 /* 141048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50409 /* 141054 */ GIR_RootConstrainSelectedInstOperands,
50410 /* 141055 */ // GIR_Coverage, 3529,
50411 /* 141055 */ GIR_EraseRootFromParent_Done,
50412 /* 141056 */ // Label 2927: @141056
50413 /* 141056 */ GIM_Reject,
50414 /* 141057 */ // Label 2924: @141057
50415 /* 141057 */ GIM_Try, /*On fail goto*//*Label 2928*/ GIMT_Encode4(141139), // Rule ID 3530 //
50416 /* 141062 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50417 /* 141065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50418 /* 141069 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50419 /* 141073 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVs32:{ *:[i32] } (t2MVNi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
50420 /* 141073 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50421 /* 141076 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
50422 /* 141080 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50423 /* 141085 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744071562067968u),
50424 /* 141095 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50425 /* 141098 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50426 /* 141104 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50427 /* 141110 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50428 /* 141112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32),
50429 /* 141115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50430 /* 141117 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50431 /* 141120 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50432 /* 141122 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50433 /* 141125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50434 /* 141131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50435 /* 141137 */ GIR_RootConstrainSelectedInstOperands,
50436 /* 141138 */ // GIR_Coverage, 3530,
50437 /* 141138 */ GIR_EraseRootFromParent_Done,
50438 /* 141139 */ // Label 2928: @141139
50439 /* 141139 */ GIM_Reject,
50440 /* 141140 */ // Label 2925: @141140
50441 /* 141140 */ GIM_Reject,
50442 /* 141141 */ // Label 2921: @141141
50443 /* 141141 */ GIM_Reject,
50444 /* 141142 */ // Label 90: @141142
50445 /* 141142 */ GIM_Try, /*On fail goto*//*Label 2929*/ GIMT_Encode4(141410),
50446 /* 141147 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
50447 /* 141150 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2933*/ GIMT_Encode4(141409),
50448 /* 141161 */ /*GILLT_v16s8*//*Label 2930*/ GIMT_Encode4(141181), GIMT_Encode4(0),
50449 /* 141169 */ /*GILLT_v8s16*//*Label 2931*/ GIMT_Encode4(141257), GIMT_Encode4(0),
50450 /* 141177 */ /*GILLT_v4s32*//*Label 2932*/ GIMT_Encode4(141333),
50451 /* 141181 */ // Label 2930: @141181
50452 /* 141181 */ GIM_Try, /*On fail goto*//*Label 2934*/ GIMT_Encode4(141256), // Rule ID 3525 //
50453 /* 141186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50454 /* 141189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50455 /* 141193 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50456 /* 141197 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
50457 /* 141197 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50458 /* 141200 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
50459 /* 141204 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50460 /* 141209 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
50461 /* 141212 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50462 /* 141215 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50463 /* 141221 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50464 /* 141227 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50465 /* 141229 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8),
50466 /* 141232 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50467 /* 141234 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50468 /* 141237 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50469 /* 141239 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50470 /* 141242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50471 /* 141248 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50472 /* 141254 */ GIR_RootConstrainSelectedInstOperands,
50473 /* 141255 */ // GIR_Coverage, 3525,
50474 /* 141255 */ GIR_EraseRootFromParent_Done,
50475 /* 141256 */ // Label 2934: @141256
50476 /* 141256 */ GIM_Reject,
50477 /* 141257 */ // Label 2931: @141257
50478 /* 141257 */ GIM_Try, /*On fail goto*//*Label 2935*/ GIMT_Encode4(141332), // Rule ID 3526 //
50479 /* 141262 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50480 /* 141265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50481 /* 141269 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50482 /* 141273 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVu16:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
50483 /* 141273 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50484 /* 141276 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
50485 /* 141280 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50486 /* 141285 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
50487 /* 141288 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50488 /* 141291 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50489 /* 141297 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50490 /* 141303 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50491 /* 141305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16),
50492 /* 141308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50493 /* 141310 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50494 /* 141313 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50495 /* 141315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50496 /* 141318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50497 /* 141324 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50498 /* 141330 */ GIR_RootConstrainSelectedInstOperands,
50499 /* 141331 */ // GIR_Coverage, 3526,
50500 /* 141331 */ GIR_EraseRootFromParent_Done,
50501 /* 141332 */ // Label 2935: @141332
50502 /* 141332 */ GIM_Reject,
50503 /* 141333 */ // Label 2932: @141333
50504 /* 141333 */ GIM_Try, /*On fail goto*//*Label 2936*/ GIMT_Encode4(141408), // Rule ID 3527 //
50505 /* 141338 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50506 /* 141341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50507 /* 141345 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50508 /* 141349 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
50509 /* 141349 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50510 /* 141352 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
50511 /* 141356 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50512 /* 141361 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
50513 /* 141364 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50514 /* 141367 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50515 /* 141373 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50516 /* 141379 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50517 /* 141381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32),
50518 /* 141384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50519 /* 141386 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50520 /* 141389 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50521 /* 141391 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50522 /* 141394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50523 /* 141400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50524 /* 141406 */ GIR_RootConstrainSelectedInstOperands,
50525 /* 141407 */ // GIR_Coverage, 3527,
50526 /* 141407 */ GIR_EraseRootFromParent_Done,
50527 /* 141408 */ // Label 2936: @141408
50528 /* 141408 */ GIM_Reject,
50529 /* 141409 */ // Label 2933: @141409
50530 /* 141409 */ GIM_Reject,
50531 /* 141410 */ // Label 2929: @141410
50532 /* 141410 */ GIM_Reject,
50533 /* 141411 */ // Label 91: @141411
50534 /* 141411 */ GIM_Try, /*On fail goto*//*Label 2937*/ GIMT_Encode4(141694),
50535 /* 141416 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
50536 /* 141419 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2941*/ GIMT_Encode4(141693),
50537 /* 141430 */ /*GILLT_v16s8*//*Label 2938*/ GIMT_Encode4(141450), GIMT_Encode4(0),
50538 /* 141438 */ /*GILLT_v8s16*//*Label 2939*/ GIMT_Encode4(141533), GIMT_Encode4(0),
50539 /* 141446 */ /*GILLT_v4s32*//*Label 2940*/ GIMT_Encode4(141610),
50540 /* 141450 */ // Label 2938: @141450
50541 /* 141450 */ GIM_Try, /*On fail goto*//*Label 2942*/ GIMT_Encode4(141532), // Rule ID 3531 //
50542 /* 141455 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50543 /* 141458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50544 /* 141462 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50545 /* 141466 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 255:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
50546 /* 141466 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50547 /* 141469 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
50548 /* 141473 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50549 /* 141478 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(255),
50550 /* 141488 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50551 /* 141491 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50552 /* 141497 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50553 /* 141503 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50554 /* 141505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8),
50555 /* 141508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50556 /* 141510 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50557 /* 141513 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50558 /* 141515 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50559 /* 141518 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50560 /* 141524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50561 /* 141530 */ GIR_RootConstrainSelectedInstOperands,
50562 /* 141531 */ // GIR_Coverage, 3531,
50563 /* 141531 */ GIR_EraseRootFromParent_Done,
50564 /* 141532 */ // Label 2942: @141532
50565 /* 141532 */ GIM_Reject,
50566 /* 141533 */ // Label 2939: @141533
50567 /* 141533 */ GIM_Try, /*On fail goto*//*Label 2943*/ GIMT_Encode4(141609), // Rule ID 3532 //
50568 /* 141538 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50569 /* 141541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50570 /* 141545 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50571 /* 141549 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVu16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 65535:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
50572 /* 141549 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50573 /* 141552 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16),
50574 /* 141556 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50575 /* 141561 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
50576 /* 141571 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50577 /* 141574 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50578 /* 141580 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50579 /* 141582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16),
50580 /* 141585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50581 /* 141587 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50582 /* 141590 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50583 /* 141592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50584 /* 141595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50585 /* 141601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50586 /* 141607 */ GIR_RootConstrainSelectedInstOperands,
50587 /* 141608 */ // GIR_Coverage, 3532,
50588 /* 141608 */ GIR_EraseRootFromParent_Done,
50589 /* 141609 */ // Label 2943: @141609
50590 /* 141609 */ GIM_Reject,
50591 /* 141610 */ // Label 2940: @141610
50592 /* 141610 */ GIM_Try, /*On fail goto*//*Label 2944*/ GIMT_Encode4(141692), // Rule ID 3533 //
50593 /* 141615 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50594 /* 141618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50595 /* 141622 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50596 /* 141626 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 4294967295:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
50597 /* 141626 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50598 /* 141629 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
50599 /* 141633 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50600 /* 141638 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(4294967295),
50601 /* 141648 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50602 /* 141651 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50603 /* 141657 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50604 /* 141663 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50605 /* 141665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32),
50606 /* 141668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50607 /* 141670 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50608 /* 141673 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50609 /* 141675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50610 /* 141678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50611 /* 141684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50612 /* 141690 */ GIR_RootConstrainSelectedInstOperands,
50613 /* 141691 */ // GIR_Coverage, 3533,
50614 /* 141691 */ GIR_EraseRootFromParent_Done,
50615 /* 141692 */ // Label 2944: @141692
50616 /* 141692 */ GIM_Reject,
50617 /* 141693 */ // Label 2941: @141693
50618 /* 141693 */ GIM_Reject,
50619 /* 141694 */ // Label 2937: @141694
50620 /* 141694 */ GIM_Reject,
50621 /* 141695 */ // Label 92: @141695
50622 /* 141695 */ GIM_Reject,
50623 /* 141696 */ }; // Size: 141696 bytes
50624 return MatchTable0;
50625}
50626#undef GIMT_Encode2
50627#undef GIMT_Encode4
50628#undef GIMT_Encode8
50629
50630
50631#endif // GET_GLOBALISEL_IMPL
50632
50633#ifdef GET_GLOBALISEL_PREDICATES_DECL
50634
50635PredicateBitset AvailableModuleFeatures;
50636mutable PredicateBitset AvailableFunctionFeatures;
50637PredicateBitset getAvailableFeatures() const {
50638 return AvailableModuleFeatures | AvailableFunctionFeatures;
50639}
50640PredicateBitset
50641computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const;
50642PredicateBitset
50643computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget,
50644 const MachineFunction *MF) const;
50645void setupGeneratedPerFunctionState(MachineFunction &MF) override;
50646
50647#endif // GET_GLOBALISEL_PREDICATES_DECL
50648
50649#ifdef GET_GLOBALISEL_PREDICATES_INIT
50650
50651AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
50652AvailableFunctionFeatures()
50653
50654#endif // GET_GLOBALISEL_PREDICATES_INIT
50655
50656