| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Global Instruction Selector for the ARM target *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 10 | |
| 11 | const unsigned MAX_SUBTARGET_PREDICATES = 83; |
| 12 | using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>; |
| 13 | |
| 14 | #endif // GET_GLOBALISEL_PREDICATE_BITSET |
| 15 | |
| 16 | #ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 17 | |
| 18 | mutable MatcherState State; |
| 19 | typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; |
| 20 | typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; |
| 21 | const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo; |
| 22 | static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; |
| 23 | static ARMInstructionSelector::CustomRendererFn CustomRenderers[]; |
| 24 | bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; |
| 25 | bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; |
| 26 | bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; |
| 27 | const uint8_t *getMatchTable() const override; |
| 28 | bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override; |
| 29 | bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override; |
| 30 | bool testSimplePredicate(unsigned PredicateID) const override; |
| 31 | bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override; |
| 32 | |
| 33 | #endif // GET_GLOBALISEL_TEMPORARIES_DECL |
| 34 | |
| 35 | #ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 36 | |
| 37 | , State(0), |
| 38 | ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) |
| 39 | |
| 40 | #endif // GET_GLOBALISEL_TEMPORARIES_INIT |
| 41 | |
| 42 | #ifdef GET_GLOBALISEL_IMPL |
| 43 | |
| 44 | // LLT Objects. |
| 45 | enum { |
| 46 | GILLT_s16, |
| 47 | GILLT_s32, |
| 48 | GILLT_s64, |
| 49 | GILLT_v2s1, |
| 50 | GILLT_v4s1, |
| 51 | GILLT_v8s1, |
| 52 | GILLT_v16s1, |
| 53 | GILLT_v8s8, |
| 54 | GILLT_v16s8, |
| 55 | GILLT_v4s16, |
| 56 | GILLT_v8s16, |
| 57 | GILLT_v2s32, |
| 58 | GILLT_v4s32, |
| 59 | GILLT_v2s64, |
| 60 | GILLT_v4s64, |
| 61 | GILLT_v8s64, |
| 62 | }; |
| 63 | const static size_t NumTypeObjects = 16; |
| 64 | const static LLT TypeObjects[] = { |
| 65 | LLT::scalar(16), |
| 66 | LLT::scalar(32), |
| 67 | LLT::scalar(64), |
| 68 | LLT::vector(ElementCount::getFixed(2), LLT::scalar(1)), |
| 69 | LLT::vector(ElementCount::getFixed(4), LLT::scalar(1)), |
| 70 | LLT::vector(ElementCount::getFixed(8), LLT::scalar(1)), |
| 71 | LLT::vector(ElementCount::getFixed(16), LLT::scalar(1)), |
| 72 | LLT::vector(ElementCount::getFixed(8), LLT::scalar(8)), |
| 73 | LLT::vector(ElementCount::getFixed(16), LLT::scalar(8)), |
| 74 | LLT::vector(ElementCount::getFixed(4), LLT::scalar(16)), |
| 75 | LLT::vector(ElementCount::getFixed(8), LLT::scalar(16)), |
| 76 | LLT::vector(ElementCount::getFixed(2), LLT::scalar(32)), |
| 77 | LLT::vector(ElementCount::getFixed(4), LLT::scalar(32)), |
| 78 | LLT::vector(ElementCount::getFixed(2), LLT::scalar(64)), |
| 79 | LLT::vector(ElementCount::getFixed(4), LLT::scalar(64)), |
| 80 | LLT::vector(ElementCount::getFixed(8), LLT::scalar(64)), |
| 81 | }; |
| 82 | |
| 83 | // Bits for subtarget features that participate in instruction matching. |
| 84 | enum SubtargetFeatureBits : uint8_t { |
| 85 | Feature_NoHonorSignDependentRoundingBit = 73, |
| 86 | Feature_HasV4TBit = 4, |
| 87 | Feature_NoV4TBit = 5, |
| 88 | Feature_HasV5TBit = 11, |
| 89 | Feature_NoV5TBit = 63, |
| 90 | Feature_HasV5TEBit = 9, |
| 91 | Feature_HasV6Bit = 0, |
| 92 | Feature_NoV6Bit = 7, |
| 93 | Feature_HasV6MBit = 26, |
| 94 | Feature_HasV8MBaselineBit = 33, |
| 95 | Feature_HasV8_1MMainlineBit = 39, |
| 96 | Feature_HasMVEIntBit = 61, |
| 97 | Feature_HasMVEFloatBit = 62, |
| 98 | Feature_HasCDEBit = 82, |
| 99 | Feature_HasFPRegsBit = 40, |
| 100 | Feature_HasFPRegs16Bit = 41, |
| 101 | Feature_HasFPRegs64Bit = 74, |
| 102 | Feature_HasV6T2Bit = 6, |
| 103 | Feature_HasV6KBit = 16, |
| 104 | Feature_HasV7Bit = 3, |
| 105 | Feature_HasV8Bit = 53, |
| 106 | Feature_PreV8Bit = 17, |
| 107 | Feature_HasV8_1aBit = 76, |
| 108 | Feature_HasV8_3aBit = 77, |
| 109 | Feature_NoVFPBit = 20, |
| 110 | Feature_HasVFP2Bit = 19, |
| 111 | Feature_HasVFP3Bit = 50, |
| 112 | Feature_HasVFP4Bit = 48, |
| 113 | Feature_HasDPVFPBit = 42, |
| 114 | Feature_HasFPARMv8Bit = 45, |
| 115 | Feature_HasNEONBit = 51, |
| 116 | Feature_HasSHA2Bit = 60, |
| 117 | Feature_HasAESBit = 52, |
| 118 | Feature_HasDotProdBit = 54, |
| 119 | Feature_HasCRCBit = 12, |
| 120 | Feature_HasLOBBit = 38, |
| 121 | Feature_HasFP16Bit = 59, |
| 122 | Feature_HasFullFP16Bit = 44, |
| 123 | Feature_HasMatMulInt8Bit = 55, |
| 124 | Feature_HasDivideInThumbBit = 35, |
| 125 | Feature_HasDivideInARMBit = 10, |
| 126 | Feature_HasDSPBit = 34, |
| 127 | Feature_HasDBBit = 13, |
| 128 | Feature_HasV7ClrexBit = 15, |
| 129 | Feature_HasAcquireReleaseBit = 14, |
| 130 | Feature_HasMPBit = 2, |
| 131 | Feature_Has8MSecExtBit = 27, |
| 132 | Feature_HasZCZBit = 56, |
| 133 | Feature_UseNEONForFPBit = 80, |
| 134 | Feature_DontUseNEONForFPBit = 43, |
| 135 | Feature_IsThumbBit = 24, |
| 136 | Feature_IsThumb1OnlyBit = 25, |
| 137 | Feature_IsThumb2Bit = 32, |
| 138 | Feature_IsNotMClassBit = 36, |
| 139 | Feature_IsARMBit = 1, |
| 140 | Feature_IsWindowsBit = 28, |
| 141 | Feature_IsNotWindowsBit = 29, |
| 142 | Feature_IsReadTPTPIDRURWBit = 66, |
| 143 | Feature_IsReadTPTPIDRUROBit = 67, |
| 144 | Feature_IsReadTPTPIDRPRWBit = 68, |
| 145 | Feature_IsReadTPSoftBit = 18, |
| 146 | Feature_UseMovtBit = 37, |
| 147 | Feature_DontUseMovtBit = 21, |
| 148 | Feature_UseMovtInPicBit = 22, |
| 149 | Feature_DontUseMovtInPicBit = 23, |
| 150 | Feature_UseFPVMLxBit = 47, |
| 151 | Feature_SLSBLRMitigationBit = 65, |
| 152 | Feature_NoSLSBLRMitigationBit = 64, |
| 153 | Feature_UseMulOpsBit = 8, |
| 154 | Feature_UseFusedMACBit = 49, |
| 155 | Feature_HasFastVGETLNi32Bit = 57, |
| 156 | Feature_HasSlowVGETLNi32Bit = 78, |
| 157 | Feature_HasFastVDUP32Bit = 58, |
| 158 | Feature_HasSlowVDUP32Bit = 79, |
| 159 | Feature_UseVMOVSRBit = 46, |
| 160 | Feature_DontUseVMOVSRBit = 81, |
| 161 | Feature_IsLEBit = 72, |
| 162 | Feature_IsBEBit = 75, |
| 163 | Feature_GenExecuteOnlyBit = 31, |
| 164 | Feature_DontGenExecuteOnlyBit = 30, |
| 165 | Feature_GenT1ExecuteOnlyBit = 71, |
| 166 | Feature_SignRetAddrBit = 70, |
| 167 | Feature_NoSignRetAddrBit = 69, |
| 168 | }; |
| 169 | |
| 170 | PredicateBitset ARMInstructionSelector:: |
| 171 | computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const { |
| 172 | PredicateBitset Features{}; |
| 173 | if (!TM.Options.HonorSignDependentRoundingFPMath()) |
| 174 | Features.set(Feature_NoHonorSignDependentRoundingBit); |
| 175 | if (Subtarget->hasV4TOps()) |
| 176 | Features.set(Feature_HasV4TBit); |
| 177 | if (!Subtarget->hasV4TOps()) |
| 178 | Features.set(Feature_NoV4TBit); |
| 179 | if (Subtarget->hasV5TOps()) |
| 180 | Features.set(Feature_HasV5TBit); |
| 181 | if (!Subtarget->hasV5TOps()) |
| 182 | Features.set(Feature_NoV5TBit); |
| 183 | if (Subtarget->hasV5TEOps()) |
| 184 | Features.set(Feature_HasV5TEBit); |
| 185 | if (Subtarget->hasV6Ops()) |
| 186 | Features.set(Feature_HasV6Bit); |
| 187 | if (!Subtarget->hasV6Ops()) |
| 188 | Features.set(Feature_NoV6Bit); |
| 189 | if (Subtarget->hasV6MOps()) |
| 190 | Features.set(Feature_HasV6MBit); |
| 191 | if (Subtarget->hasV8MBaselineOps()) |
| 192 | Features.set(Feature_HasV8MBaselineBit); |
| 193 | if (Subtarget->hasV8_1MMainlineOps()) |
| 194 | Features.set(Feature_HasV8_1MMainlineBit); |
| 195 | if (Subtarget->hasMVEIntegerOps()) |
| 196 | Features.set(Feature_HasMVEIntBit); |
| 197 | if (Subtarget->hasMVEFloatOps()) |
| 198 | Features.set(Feature_HasMVEFloatBit); |
| 199 | if (Subtarget->hasCDEOps()) |
| 200 | Features.set(Feature_HasCDEBit); |
| 201 | if (Subtarget->hasFPRegs()) |
| 202 | Features.set(Feature_HasFPRegsBit); |
| 203 | if (Subtarget->hasFPRegs16()) |
| 204 | Features.set(Feature_HasFPRegs16Bit); |
| 205 | if (Subtarget->hasFPRegs64()) |
| 206 | Features.set(Feature_HasFPRegs64Bit); |
| 207 | if (Subtarget->hasV6T2Ops()) |
| 208 | Features.set(Feature_HasV6T2Bit); |
| 209 | if (Subtarget->hasV6KOps()) |
| 210 | Features.set(Feature_HasV6KBit); |
| 211 | if (Subtarget->hasV7Ops()) |
| 212 | Features.set(Feature_HasV7Bit); |
| 213 | if (Subtarget->hasV8Ops()) |
| 214 | Features.set(Feature_HasV8Bit); |
| 215 | if (!Subtarget->hasV8Ops()) |
| 216 | Features.set(Feature_PreV8Bit); |
| 217 | if (Subtarget->hasV8_1aOps()) |
| 218 | Features.set(Feature_HasV8_1aBit); |
| 219 | if (Subtarget->hasV8_3aOps()) |
| 220 | Features.set(Feature_HasV8_3aBit); |
| 221 | if (!Subtarget->hasVFP2Base()) |
| 222 | Features.set(Feature_NoVFPBit); |
| 223 | if (Subtarget->hasVFP2Base()) |
| 224 | Features.set(Feature_HasVFP2Bit); |
| 225 | if (Subtarget->hasVFP3Base()) |
| 226 | Features.set(Feature_HasVFP3Bit); |
| 227 | if (Subtarget->hasVFP4Base()) |
| 228 | Features.set(Feature_HasVFP4Bit); |
| 229 | if (Subtarget->hasFP64()) |
| 230 | Features.set(Feature_HasDPVFPBit); |
| 231 | if (Subtarget->hasFPARMv8Base()) |
| 232 | Features.set(Feature_HasFPARMv8Bit); |
| 233 | if (Subtarget->hasNEON()) |
| 234 | Features.set(Feature_HasNEONBit); |
| 235 | if (Subtarget->hasSHA2()) |
| 236 | Features.set(Feature_HasSHA2Bit); |
| 237 | if (Subtarget->hasAES()) |
| 238 | Features.set(Feature_HasAESBit); |
| 239 | if (Subtarget->hasDotProd()) |
| 240 | Features.set(Feature_HasDotProdBit); |
| 241 | if (Subtarget->hasCRC()) |
| 242 | Features.set(Feature_HasCRCBit); |
| 243 | if (Subtarget->hasLOB()) |
| 244 | Features.set(Feature_HasLOBBit); |
| 245 | if (Subtarget->hasFP16()) |
| 246 | Features.set(Feature_HasFP16Bit); |
| 247 | if (Subtarget->hasFullFP16()) |
| 248 | Features.set(Feature_HasFullFP16Bit); |
| 249 | if (Subtarget->hasMatMulInt8()) |
| 250 | Features.set(Feature_HasMatMulInt8Bit); |
| 251 | if (Subtarget->hasDivideInThumbMode()) |
| 252 | Features.set(Feature_HasDivideInThumbBit); |
| 253 | if (Subtarget->hasDivideInARMMode()) |
| 254 | Features.set(Feature_HasDivideInARMBit); |
| 255 | if (Subtarget->hasDSP()) |
| 256 | Features.set(Feature_HasDSPBit); |
| 257 | if (Subtarget->hasDataBarrier()) |
| 258 | Features.set(Feature_HasDBBit); |
| 259 | if (Subtarget->hasV7Clrex()) |
| 260 | Features.set(Feature_HasV7ClrexBit); |
| 261 | if (Subtarget->hasAcquireRelease()) |
| 262 | Features.set(Feature_HasAcquireReleaseBit); |
| 263 | if (Subtarget->hasMPExtension()) |
| 264 | Features.set(Feature_HasMPBit); |
| 265 | if (Subtarget->has8MSecExt()) |
| 266 | Features.set(Feature_Has8MSecExtBit); |
| 267 | if (Subtarget->hasZeroCycleZeroing()) |
| 268 | Features.set(Feature_HasZCZBit); |
| 269 | if (Subtarget->useNEONForSinglePrecisionFP()) |
| 270 | Features.set(Feature_UseNEONForFPBit); |
| 271 | if (!Subtarget->useNEONForSinglePrecisionFP()) |
| 272 | Features.set(Feature_DontUseNEONForFPBit); |
| 273 | if (Subtarget->isThumb()) |
| 274 | Features.set(Feature_IsThumbBit); |
| 275 | if (Subtarget->isThumb1Only()) |
| 276 | Features.set(Feature_IsThumb1OnlyBit); |
| 277 | if (Subtarget->isThumb2()) |
| 278 | Features.set(Feature_IsThumb2Bit); |
| 279 | if (!Subtarget->isMClass()) |
| 280 | Features.set(Feature_IsNotMClassBit); |
| 281 | if (!Subtarget->isThumb()) |
| 282 | Features.set(Feature_IsARMBit); |
| 283 | if (Subtarget->isTargetWindows()) |
| 284 | Features.set(Feature_IsWindowsBit); |
| 285 | if (!Subtarget->isTargetWindows()) |
| 286 | Features.set(Feature_IsNotWindowsBit); |
| 287 | if (Subtarget->isReadTPTPIDRURW()) |
| 288 | Features.set(Feature_IsReadTPTPIDRURWBit); |
| 289 | if (Subtarget->isReadTPTPIDRURO()) |
| 290 | Features.set(Feature_IsReadTPTPIDRUROBit); |
| 291 | if (Subtarget->isReadTPTPIDRPRW()) |
| 292 | Features.set(Feature_IsReadTPTPIDRPRWBit); |
| 293 | if (Subtarget->isReadTPSoft()) |
| 294 | Features.set(Feature_IsReadTPSoftBit); |
| 295 | if (Subtarget->useMulOps()) |
| 296 | Features.set(Feature_UseMulOpsBit); |
| 297 | if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast && Subtarget->useFPVFMx()) |
| 298 | Features.set(Feature_UseFusedMACBit); |
| 299 | if (!Subtarget->hasSlowVGETLNi32()) |
| 300 | Features.set(Feature_HasFastVGETLNi32Bit); |
| 301 | if (Subtarget->hasSlowVGETLNi32()) |
| 302 | Features.set(Feature_HasSlowVGETLNi32Bit); |
| 303 | if (!Subtarget->hasSlowVDUP32()) |
| 304 | Features.set(Feature_HasFastVDUP32Bit); |
| 305 | if (Subtarget->hasSlowVDUP32()) |
| 306 | Features.set(Feature_HasSlowVDUP32Bit); |
| 307 | if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP()) |
| 308 | Features.set(Feature_UseVMOVSRBit); |
| 309 | if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP()) |
| 310 | Features.set(Feature_DontUseVMOVSRBit); |
| 311 | if (Subtarget->genExecuteOnly()) |
| 312 | Features.set(Feature_GenExecuteOnlyBit); |
| 313 | if (!Subtarget->genExecuteOnly()) |
| 314 | Features.set(Feature_DontGenExecuteOnlyBit); |
| 315 | if (Subtarget->genExecuteOnly() && Subtarget->isThumb1Only() && !Subtarget->hasV8MBaselineOps()) |
| 316 | Features.set(Feature_GenT1ExecuteOnlyBit); |
| 317 | return Features; |
| 318 | } |
| 319 | |
| 320 | void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { |
| 321 | AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget *)&MF.getSubtarget(), &MF); |
| 322 | } |
| 323 | PredicateBitset ARMInstructionSelector:: |
| 324 | computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const { |
| 325 | PredicateBitset Features{}; |
| 326 | if (Subtarget->useMovt()) |
| 327 | Features.set(Feature_UseMovtBit); |
| 328 | if (!Subtarget->useMovt()) |
| 329 | Features.set(Feature_DontUseMovtBit); |
| 330 | if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt()) |
| 331 | Features.set(Feature_UseMovtInPicBit); |
| 332 | if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt()) |
| 333 | Features.set(Feature_DontUseMovtInPicBit); |
| 334 | if (((Subtarget->useFPVMLx() && TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||Subtarget->hasMinSize())) |
| 335 | Features.set(Feature_UseFPVMLxBit); |
| 336 | if ( MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() ) |
| 337 | Features.set(Feature_SLSBLRMitigationBit); |
| 338 | if ( !MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() ) |
| 339 | Features.set(Feature_NoSLSBLRMitigationBit); |
| 340 | if (MF->getDataLayout().isLittleEndian()) |
| 341 | Features.set(Feature_IsLEBit); |
| 342 | if (MF->getDataLayout().isBigEndian()) |
| 343 | Features.set(Feature_IsBEBit); |
| 344 | if ( MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) ) |
| 345 | Features.set(Feature_SignRetAddrBit); |
| 346 | if ( !MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) ) |
| 347 | Features.set(Feature_NoSignRetAddrBit); |
| 348 | return Features; |
| 349 | } |
| 350 | |
| 351 | // Feature bitsets. |
| 352 | enum { |
| 353 | GIFBS_Invalid, |
| 354 | GIFBS_HasDotProd, |
| 355 | GIFBS_HasFP16, |
| 356 | GIFBS_HasFPARMv8, |
| 357 | GIFBS_HasFPRegs, |
| 358 | GIFBS_HasFullFP16, |
| 359 | GIFBS_HasMVEFloat, |
| 360 | GIFBS_HasMVEInt, |
| 361 | GIFBS_HasMatMulInt8, |
| 362 | GIFBS_HasNEON, |
| 363 | GIFBS_HasVFP2, |
| 364 | GIFBS_HasVFP3, |
| 365 | GIFBS_HasVFP4, |
| 366 | GIFBS_IsARM, |
| 367 | GIFBS_IsThumb, |
| 368 | GIFBS_IsThumb2, |
| 369 | GIFBS_NoHonorSignDependentRounding, |
| 370 | GIFBS_DontUseNEONForFP_HasVFP2, |
| 371 | GIFBS_DontUseVMOVSR_HasNEON, |
| 372 | GIFBS_Has8MSecExt_IsThumb, |
| 373 | GIFBS_HasAES_HasV8, |
| 374 | GIFBS_HasCRC_IsARM, |
| 375 | GIFBS_HasCRC_IsThumb2, |
| 376 | GIFBS_HasDB_IsARM, |
| 377 | GIFBS_HasDB_IsThumb, |
| 378 | GIFBS_HasDPVFP_HasFPARMv8, |
| 379 | GIFBS_HasDPVFP_HasVFP2, |
| 380 | GIFBS_HasDPVFP_HasVFP3, |
| 381 | GIFBS_HasDPVFP_HasVFP4, |
| 382 | GIFBS_HasDPVFP_NoHonorSignDependentRounding, |
| 383 | GIFBS_HasDSP_IsThumb2, |
| 384 | GIFBS_HasDivideInARM_IsARM, |
| 385 | GIFBS_HasFP16_HasNEON, |
| 386 | GIFBS_HasFPARMv8_HasNEON, |
| 387 | GIFBS_HasFPRegs_HasFastVGETLNi32, |
| 388 | GIFBS_HasFPRegs_UseVMOVSR, |
| 389 | GIFBS_HasFullFP16_HasNEON, |
| 390 | GIFBS_HasMVEInt_HasV8_1MMainline, |
| 391 | GIFBS_HasMVEInt_IsBE, |
| 392 | GIFBS_HasMVEInt_IsLE, |
| 393 | GIFBS_HasNEON_HasV8, |
| 394 | GIFBS_HasNEON_HasV8_1a, |
| 395 | GIFBS_HasNEON_HasV8_3a, |
| 396 | GIFBS_HasNEON_HasVFP4, |
| 397 | GIFBS_HasNEON_IsBE, |
| 398 | GIFBS_HasNEON_IsLE, |
| 399 | GIFBS_HasNEON_UseNEONForFP, |
| 400 | GIFBS_HasSHA2_HasV8, |
| 401 | GIFBS_HasV5T_IsARM, |
| 402 | GIFBS_HasV5T_IsThumb, |
| 403 | GIFBS_HasV5TE_IsARM, |
| 404 | GIFBS_HasV6_IsARM, |
| 405 | GIFBS_HasV6K_IsARM, |
| 406 | GIFBS_HasV6M_IsThumb, |
| 407 | GIFBS_HasV6T2_IsARM, |
| 408 | GIFBS_HasV7_IsARM, |
| 409 | GIFBS_HasV7Clrex_IsThumb, |
| 410 | GIFBS_HasV8MBaseline_IsThumb, |
| 411 | GIFBS_IsARM_NoV5T, |
| 412 | GIFBS_IsARM_NoV6, |
| 413 | GIFBS_IsARM_PreV8, |
| 414 | GIFBS_IsThumb_IsThumb1Only, |
| 415 | GIFBS_IsThumb_IsWindows, |
| 416 | GIFBS_IsThumb_NoV5T, |
| 417 | GIFBS_IsThumb_UseMovt, |
| 418 | GIFBS_IsThumb2_PreV8, |
| 419 | GIFBS_IsThumb2_UseMulOps, |
| 420 | GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only, |
| 421 | GIFBS_HasDSP_IsThumb2_UseMulOps, |
| 422 | GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb, |
| 423 | GIFBS_HasFPARMv8_HasFullFP16_HasNEON, |
| 424 | GIFBS_HasFullFP16_HasNEON_HasV8, |
| 425 | GIFBS_HasFullFP16_HasNEON_HasV8_3a, |
| 426 | GIFBS_HasFullFP16_HasNEON_UseFPVMLx, |
| 427 | GIFBS_HasFullFP16_HasNEON_UseFusedMAC, |
| 428 | GIFBS_HasLOB_HasV8_1MMainline_IsThumb2, |
| 429 | GIFBS_HasNEON_UseFPVMLx_UseNEONForFP, |
| 430 | GIFBS_HasV5TE_IsARM_UseMulOps, |
| 431 | GIFBS_HasV6_IsARM_UseMulOps, |
| 432 | GIFBS_HasV6_IsThumb_IsThumb1Only, |
| 433 | GIFBS_HasV6T2_IsARM_UseMulOps, |
| 434 | GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP, |
| 435 | GIFBS_IsARM_NoV6_UseMulOps, |
| 436 | }; |
| 437 | constexpr static PredicateBitset FeatureBitsets[] { |
| 438 | {}, // GIFBS_Invalid |
| 439 | {Feature_HasDotProdBit, }, |
| 440 | {Feature_HasFP16Bit, }, |
| 441 | {Feature_HasFPARMv8Bit, }, |
| 442 | {Feature_HasFPRegsBit, }, |
| 443 | {Feature_HasFullFP16Bit, }, |
| 444 | {Feature_HasMVEFloatBit, }, |
| 445 | {Feature_HasMVEIntBit, }, |
| 446 | {Feature_HasMatMulInt8Bit, }, |
| 447 | {Feature_HasNEONBit, }, |
| 448 | {Feature_HasVFP2Bit, }, |
| 449 | {Feature_HasVFP3Bit, }, |
| 450 | {Feature_HasVFP4Bit, }, |
| 451 | {Feature_IsARMBit, }, |
| 452 | {Feature_IsThumbBit, }, |
| 453 | {Feature_IsThumb2Bit, }, |
| 454 | {Feature_NoHonorSignDependentRoundingBit, }, |
| 455 | {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, }, |
| 456 | {Feature_DontUseVMOVSRBit, Feature_HasNEONBit, }, |
| 457 | {Feature_Has8MSecExtBit, Feature_IsThumbBit, }, |
| 458 | {Feature_HasAESBit, Feature_HasV8Bit, }, |
| 459 | {Feature_HasCRCBit, Feature_IsARMBit, }, |
| 460 | {Feature_HasCRCBit, Feature_IsThumb2Bit, }, |
| 461 | {Feature_HasDBBit, Feature_IsARMBit, }, |
| 462 | {Feature_HasDBBit, Feature_IsThumbBit, }, |
| 463 | {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, }, |
| 464 | {Feature_HasDPVFPBit, Feature_HasVFP2Bit, }, |
| 465 | {Feature_HasDPVFPBit, Feature_HasVFP3Bit, }, |
| 466 | {Feature_HasDPVFPBit, Feature_HasVFP4Bit, }, |
| 467 | {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, }, |
| 468 | {Feature_HasDSPBit, Feature_IsThumb2Bit, }, |
| 469 | {Feature_HasDivideInARMBit, Feature_IsARMBit, }, |
| 470 | {Feature_HasFP16Bit, Feature_HasNEONBit, }, |
| 471 | {Feature_HasFPARMv8Bit, Feature_HasNEONBit, }, |
| 472 | {Feature_HasFPRegsBit, Feature_HasFastVGETLNi32Bit, }, |
| 473 | {Feature_HasFPRegsBit, Feature_UseVMOVSRBit, }, |
| 474 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, }, |
| 475 | {Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, }, |
| 476 | {Feature_HasMVEIntBit, Feature_IsBEBit, }, |
| 477 | {Feature_HasMVEIntBit, Feature_IsLEBit, }, |
| 478 | {Feature_HasNEONBit, Feature_HasV8Bit, }, |
| 479 | {Feature_HasNEONBit, Feature_HasV8_1aBit, }, |
| 480 | {Feature_HasNEONBit, Feature_HasV8_3aBit, }, |
| 481 | {Feature_HasNEONBit, Feature_HasVFP4Bit, }, |
| 482 | {Feature_HasNEONBit, Feature_IsBEBit, }, |
| 483 | {Feature_HasNEONBit, Feature_IsLEBit, }, |
| 484 | {Feature_HasNEONBit, Feature_UseNEONForFPBit, }, |
| 485 | {Feature_HasSHA2Bit, Feature_HasV8Bit, }, |
| 486 | {Feature_HasV5TBit, Feature_IsARMBit, }, |
| 487 | {Feature_HasV5TBit, Feature_IsThumbBit, }, |
| 488 | {Feature_HasV5TEBit, Feature_IsARMBit, }, |
| 489 | {Feature_HasV6Bit, Feature_IsARMBit, }, |
| 490 | {Feature_HasV6KBit, Feature_IsARMBit, }, |
| 491 | {Feature_HasV6MBit, Feature_IsThumbBit, }, |
| 492 | {Feature_HasV6T2Bit, Feature_IsARMBit, }, |
| 493 | {Feature_HasV7Bit, Feature_IsARMBit, }, |
| 494 | {Feature_HasV7ClrexBit, Feature_IsThumbBit, }, |
| 495 | {Feature_HasV8MBaselineBit, Feature_IsThumbBit, }, |
| 496 | {Feature_IsARMBit, Feature_NoV5TBit, }, |
| 497 | {Feature_IsARMBit, Feature_NoV6Bit, }, |
| 498 | {Feature_IsARMBit, Feature_PreV8Bit, }, |
| 499 | {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, }, |
| 500 | {Feature_IsThumbBit, Feature_IsWindowsBit, }, |
| 501 | {Feature_IsThumbBit, Feature_NoV5TBit, }, |
| 502 | {Feature_IsThumbBit, Feature_UseMovtBit, }, |
| 503 | {Feature_IsThumb2Bit, Feature_PreV8Bit, }, |
| 504 | {Feature_IsThumb2Bit, Feature_UseMulOpsBit, }, |
| 505 | {Feature_DontUseMovtBit, Feature_GenExecuteOnlyBit, Feature_IsThumb1OnlyBit, }, |
| 506 | {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, }, |
| 507 | {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, }, |
| 508 | {Feature_HasFPARMv8Bit, Feature_HasFullFP16Bit, Feature_HasNEONBit, }, |
| 509 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, }, |
| 510 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, }, |
| 511 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, }, |
| 512 | {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, }, |
| 513 | {Feature_HasLOBBit, Feature_HasV8_1MMainlineBit, Feature_IsThumb2Bit, }, |
| 514 | {Feature_HasNEONBit, Feature_UseFPVMLxBit, Feature_UseNEONForFPBit, }, |
| 515 | {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, }, |
| 516 | {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, }, |
| 517 | {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, }, |
| 518 | {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, }, |
| 519 | {Feature_HasVFP4Bit, Feature_UseFusedMACBit, Feature_UseNEONForFPBit, }, |
| 520 | {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, }, |
| 521 | }; |
| 522 | |
| 523 | // ComplexPattern predicates. |
| 524 | enum { |
| 525 | GICP_Invalid, |
| 526 | }; |
| 527 | // See constructor for table contents |
| 528 | |
| 529 | ARMInstructionSelector::ComplexMatcherMemFn |
| 530 | ARMInstructionSelector::ComplexPredicateFns[] = { |
| 531 | nullptr, // GICP_Invalid |
| 532 | }; |
| 533 | |
| 534 | // PatFrag predicates. |
| 535 | enum { |
| 536 | GICXXPred_MI_Predicate_bf_inv_mask_imm = GICXXPred_Invalid + 1, |
| 537 | GICXXPred_MI_Predicate_ffloor_nnan, |
| 538 | GICXXPred_MI_Predicate_or_disjoint, |
| 539 | GICXXPred_MI_Predicate_vfp_f32imm, |
| 540 | GICXXPred_MI_Predicate_vfp_f64imm, |
| 541 | }; |
| 542 | bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const { |
| 543 | const MachineFunction &MF = *MI.getParent()->getParent(); |
| 544 | const MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 545 | const auto &Operands = State.RecordedOperands; |
| 546 | (void)Operands; |
| 547 | (void)MRI; |
| 548 | switch (PredicateID) { |
| 549 | case GICXXPred_MI_Predicate_bf_inv_mask_imm: { |
| 550 | |
| 551 | // There's better methods of implementing this check. IntImmLeaf<> would be |
| 552 | // equivalent and have less boilerplate but we need a test for C++ |
| 553 | // predicates and this one causes new rules to be imported into GlobalISel |
| 554 | // without requiring additional features first. |
| 555 | const auto &MO = MI.getOperand(1); |
| 556 | if (!MO.isCImm()) |
| 557 | return false; |
| 558 | return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue()); |
| 559 | |
| 560 | llvm_unreachable("bf_inv_mask_imm should have returned"); |
| 561 | } |
| 562 | case GICXXPred_MI_Predicate_ffloor_nnan: { |
| 563 | |
| 564 | return MI.getFlag(MachineInstr::FmNoNans); |
| 565 | |
| 566 | } |
| 567 | case GICXXPred_MI_Predicate_or_disjoint: { |
| 568 | |
| 569 | return MI.getFlag(MachineInstr::Disjoint); |
| 570 | |
| 571 | } |
| 572 | case GICXXPred_MI_Predicate_vfp_f32imm: { |
| 573 | |
| 574 | const auto &MO = MI.getOperand(1); |
| 575 | if (!MO.isFPImm()) |
| 576 | return false; |
| 577 | return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1; |
| 578 | |
| 579 | llvm_unreachable("vfp_f32imm should have returned"); |
| 580 | } |
| 581 | case GICXXPred_MI_Predicate_vfp_f64imm: { |
| 582 | |
| 583 | const auto &MO = MI.getOperand(1); |
| 584 | if (!MO.isFPImm()) |
| 585 | return false; |
| 586 | return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1; |
| 587 | |
| 588 | llvm_unreachable("vfp_f64imm should have returned"); |
| 589 | } |
| 590 | } |
| 591 | llvm_unreachable("Unknown predicate"); |
| 592 | return false; |
| 593 | } |
| 594 | // PatFrag predicates. |
| 595 | bool ARMInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const { |
| 596 | const auto &Operands = State.RecordedOperands; |
| 597 | Register Reg = MO.getReg(); |
| 598 | (void)Operands; |
| 599 | (void)Reg; |
| 600 | llvm_unreachable("Unknown predicate"); |
| 601 | return false; |
| 602 | } |
| 603 | // PatFrag predicates. |
| 604 | enum { |
| 605 | GICXXPred_I64_Predicate_VectorIndex8 = GICXXPred_Invalid + 1, |
| 606 | GICXXPred_I64_Predicate_VectorIndex16, |
| 607 | GICXXPred_I64_Predicate_VectorIndex32, |
| 608 | GICXXPred_I64_Predicate_VectorIndex32_Hi, |
| 609 | GICXXPred_I64_Predicate_VectorIndex64, |
| 610 | GICXXPred_I64_Predicate_asr_imm, |
| 611 | GICXXPred_I64_Predicate_imm0_7, |
| 612 | GICXXPred_I64_Predicate_imm0_15, |
| 613 | GICXXPred_I64_Predicate_imm0_31, |
| 614 | GICXXPred_I64_Predicate_imm0_32, |
| 615 | GICXXPred_I64_Predicate_imm0_63, |
| 616 | GICXXPred_I64_Predicate_imm0_239, |
| 617 | GICXXPred_I64_Predicate_imm0_255, |
| 618 | GICXXPred_I64_Predicate_imm0_255_expr, |
| 619 | GICXXPred_I64_Predicate_imm0_4095, |
| 620 | GICXXPred_I64_Predicate_imm0_65535, |
| 621 | GICXXPred_I64_Predicate_imm0_65535_expr, |
| 622 | GICXXPred_I64_Predicate_imm0_65535_neg, |
| 623 | GICXXPred_I64_Predicate_imm1_7, |
| 624 | GICXXPred_I64_Predicate_imm1_15, |
| 625 | GICXXPred_I64_Predicate_imm1_16, |
| 626 | GICXXPred_I64_Predicate_imm1_31, |
| 627 | GICXXPred_I64_Predicate_imm8, |
| 628 | GICXXPred_I64_Predicate_imm8_255, |
| 629 | GICXXPred_I64_Predicate_imm8_or_16, |
| 630 | GICXXPred_I64_Predicate_imm16, |
| 631 | GICXXPred_I64_Predicate_imm16_31, |
| 632 | GICXXPred_I64_Predicate_imm24b, |
| 633 | GICXXPred_I64_Predicate_imm32, |
| 634 | GICXXPred_I64_Predicate_imm256_510, |
| 635 | GICXXPred_I64_Predicate_imm_3b, |
| 636 | GICXXPred_I64_Predicate_imm_4b, |
| 637 | GICXXPred_I64_Predicate_imm_6b, |
| 638 | GICXXPred_I64_Predicate_imm_7b, |
| 639 | GICXXPred_I64_Predicate_imm_9b, |
| 640 | GICXXPred_I64_Predicate_imm_11b, |
| 641 | GICXXPred_I64_Predicate_imm_12b, |
| 642 | GICXXPred_I64_Predicate_imm_13b, |
| 643 | GICXXPred_I64_Predicate_imm_even, |
| 644 | GICXXPred_I64_Predicate_imm_odd, |
| 645 | GICXXPred_I64_Predicate_imm_sr, |
| 646 | GICXXPred_I64_Predicate_long_shift, |
| 647 | GICXXPred_I64_Predicate_mod_imm, |
| 648 | GICXXPred_I64_Predicate_mod_imm_not, |
| 649 | GICXXPred_I64_Predicate_pkh_asr_amt, |
| 650 | GICXXPred_I64_Predicate_pkh_lsl_amt, |
| 651 | GICXXPred_I64_Predicate_shr_imm8, |
| 652 | GICXXPred_I64_Predicate_shr_imm16, |
| 653 | GICXXPred_I64_Predicate_shr_imm32, |
| 654 | GICXXPred_I64_Predicate_shr_imm64, |
| 655 | GICXXPred_I64_Predicate_t2_so_imm, |
| 656 | GICXXPred_I64_Predicate_t2_so_imm_neg, |
| 657 | }; |
| 658 | bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { |
| 659 | switch (PredicateID) { |
| 660 | case GICXXPred_I64_Predicate_VectorIndex8: { |
| 661 | |
| 662 | return ((uint64_t)Imm) < 8; |
| 663 | |
| 664 | } |
| 665 | case GICXXPred_I64_Predicate_VectorIndex16: { |
| 666 | |
| 667 | return ((uint64_t)Imm) < 4; |
| 668 | |
| 669 | } |
| 670 | case GICXXPred_I64_Predicate_VectorIndex32: { |
| 671 | |
| 672 | return ((uint64_t)Imm) < 2; |
| 673 | |
| 674 | } |
| 675 | case GICXXPred_I64_Predicate_VectorIndex32_Hi: { |
| 676 | |
| 677 | return ((uint64_t)Imm) >= 2 && ((uint64_t)Imm) < 4; |
| 678 | |
| 679 | } |
| 680 | case GICXXPred_I64_Predicate_VectorIndex64: { |
| 681 | |
| 682 | return ((uint64_t)Imm) < 1; |
| 683 | |
| 684 | } |
| 685 | case GICXXPred_I64_Predicate_asr_imm: { |
| 686 | return Imm > 0 && Imm <= 32; |
| 687 | } |
| 688 | case GICXXPred_I64_Predicate_imm0_7: { |
| 689 | |
| 690 | return Imm >= 0 && Imm < 8; |
| 691 | |
| 692 | } |
| 693 | case GICXXPred_I64_Predicate_imm0_15: { |
| 694 | |
| 695 | return Imm >= 0 && Imm < 16; |
| 696 | |
| 697 | } |
| 698 | case GICXXPred_I64_Predicate_imm0_31: { |
| 699 | |
| 700 | return Imm >= 0 && Imm < 32; |
| 701 | |
| 702 | } |
| 703 | case GICXXPred_I64_Predicate_imm0_32: { |
| 704 | |
| 705 | return Imm >= 0 && Imm < 33; |
| 706 | |
| 707 | } |
| 708 | case GICXXPred_I64_Predicate_imm0_63: { |
| 709 | |
| 710 | return Imm >= 0 && Imm < 64; |
| 711 | |
| 712 | } |
| 713 | case GICXXPred_I64_Predicate_imm0_239: { |
| 714 | return Imm >= 0 && Imm < 240; |
| 715 | } |
| 716 | case GICXXPred_I64_Predicate_imm0_255: { |
| 717 | return Imm >= 0 && Imm < 256; |
| 718 | } |
| 719 | case GICXXPred_I64_Predicate_imm0_255_expr: { |
| 720 | return Imm >= 0 && Imm < 256; |
| 721 | } |
| 722 | case GICXXPred_I64_Predicate_imm0_4095: { |
| 723 | |
| 724 | return Imm >= 0 && Imm < 4096; |
| 725 | |
| 726 | } |
| 727 | case GICXXPred_I64_Predicate_imm0_65535: { |
| 728 | |
| 729 | return Imm >= 0 && Imm < 65536; |
| 730 | |
| 731 | } |
| 732 | case GICXXPred_I64_Predicate_imm0_65535_expr: { |
| 733 | |
| 734 | return Imm >= 0 && Imm < 65536; |
| 735 | |
| 736 | } |
| 737 | case GICXXPred_I64_Predicate_imm0_65535_neg: { |
| 738 | |
| 739 | return -Imm >= 0 && -Imm < 65536; |
| 740 | |
| 741 | } |
| 742 | case GICXXPred_I64_Predicate_imm1_7: { |
| 743 | return Imm > 0 && Imm < 8; |
| 744 | } |
| 745 | case GICXXPred_I64_Predicate_imm1_15: { |
| 746 | return Imm > 0 && Imm < 16; |
| 747 | } |
| 748 | case GICXXPred_I64_Predicate_imm1_16: { |
| 749 | |
| 750 | return Imm > 0 && Imm <= 16; |
| 751 | |
| 752 | } |
| 753 | case GICXXPred_I64_Predicate_imm1_31: { |
| 754 | return Imm > 0 && Imm < 32; |
| 755 | } |
| 756 | case GICXXPred_I64_Predicate_imm8: { |
| 757 | return Imm == 8; |
| 758 | } |
| 759 | case GICXXPred_I64_Predicate_imm8_255: { |
| 760 | |
| 761 | return Imm >= 8 && Imm < 256; |
| 762 | |
| 763 | } |
| 764 | case GICXXPred_I64_Predicate_imm8_or_16: { |
| 765 | return Imm == 8 || Imm == 16; |
| 766 | } |
| 767 | case GICXXPred_I64_Predicate_imm16: { |
| 768 | return Imm == 16; |
| 769 | } |
| 770 | case GICXXPred_I64_Predicate_imm16_31: { |
| 771 | |
| 772 | return (int32_t)Imm >= 16 && (int32_t)Imm < 32; |
| 773 | |
| 774 | } |
| 775 | case GICXXPred_I64_Predicate_imm24b: { |
| 776 | |
| 777 | return Imm >= 0 && Imm <= 0xffffff; |
| 778 | |
| 779 | } |
| 780 | case GICXXPred_I64_Predicate_imm32: { |
| 781 | return Imm == 32; |
| 782 | } |
| 783 | case GICXXPred_I64_Predicate_imm256_510: { |
| 784 | |
| 785 | return Imm >= 256 && Imm < 511; |
| 786 | |
| 787 | } |
| 788 | case GICXXPred_I64_Predicate_imm_3b: { |
| 789 | { return Imm >= 0 && Imm < (1 << 3); } |
| 790 | llvm_unreachable("imm_3b should have returned"); |
| 791 | } |
| 792 | case GICXXPred_I64_Predicate_imm_4b: { |
| 793 | { return Imm >= 0 && Imm < (1 << 4); } |
| 794 | llvm_unreachable("imm_4b should have returned"); |
| 795 | } |
| 796 | case GICXXPred_I64_Predicate_imm_6b: { |
| 797 | { return Imm >= 0 && Imm < (1 << 6); } |
| 798 | llvm_unreachable("imm_6b should have returned"); |
| 799 | } |
| 800 | case GICXXPred_I64_Predicate_imm_7b: { |
| 801 | { return Imm >= 0 && Imm < (1 << 7); } |
| 802 | llvm_unreachable("imm_7b should have returned"); |
| 803 | } |
| 804 | case GICXXPred_I64_Predicate_imm_9b: { |
| 805 | { return Imm >= 0 && Imm < (1 << 9); } |
| 806 | llvm_unreachable("imm_9b should have returned"); |
| 807 | } |
| 808 | case GICXXPred_I64_Predicate_imm_11b: { |
| 809 | { return Imm >= 0 && Imm < (1 << 11); } |
| 810 | llvm_unreachable("imm_11b should have returned"); |
| 811 | } |
| 812 | case GICXXPred_I64_Predicate_imm_12b: { |
| 813 | { return Imm >= 0 && Imm < (1 << 12); } |
| 814 | llvm_unreachable("imm_12b should have returned"); |
| 815 | } |
| 816 | case GICXXPred_I64_Predicate_imm_13b: { |
| 817 | { return Imm >= 0 && Imm < (1 << 13); } |
| 818 | llvm_unreachable("imm_13b should have returned"); |
| 819 | } |
| 820 | case GICXXPred_I64_Predicate_imm_even: { |
| 821 | return (Imm & 1) == 0; |
| 822 | } |
| 823 | case GICXXPred_I64_Predicate_imm_odd: { |
| 824 | return (Imm & 1) == 1; |
| 825 | } |
| 826 | case GICXXPred_I64_Predicate_imm_sr: { |
| 827 | |
| 828 | return Imm > 0 && Imm <= 32; |
| 829 | |
| 830 | } |
| 831 | case GICXXPred_I64_Predicate_long_shift: { |
| 832 | return Imm > 0 && Imm <= 32; |
| 833 | } |
| 834 | case GICXXPred_I64_Predicate_mod_imm: { |
| 835 | |
| 836 | return ARM_AM::getSOImmVal(Imm) != -1; |
| 837 | |
| 838 | } |
| 839 | case GICXXPred_I64_Predicate_mod_imm_not: { |
| 840 | |
| 841 | return ARM_AM::getSOImmVal(~(uint32_t)Imm) != -1; |
| 842 | |
| 843 | } |
| 844 | case GICXXPred_I64_Predicate_pkh_asr_amt: { |
| 845 | return Imm > 0 && Imm <= 32; |
| 846 | } |
| 847 | case GICXXPred_I64_Predicate_pkh_lsl_amt: { |
| 848 | return Imm >= 0 && Imm < 32; |
| 849 | } |
| 850 | case GICXXPred_I64_Predicate_shr_imm8: { |
| 851 | return Imm > 0 && Imm <= 8; |
| 852 | } |
| 853 | case GICXXPred_I64_Predicate_shr_imm16: { |
| 854 | return Imm > 0 && Imm <= 16; |
| 855 | } |
| 856 | case GICXXPred_I64_Predicate_shr_imm32: { |
| 857 | return Imm > 0 && Imm <= 32; |
| 858 | } |
| 859 | case GICXXPred_I64_Predicate_shr_imm64: { |
| 860 | return Imm > 0 && Imm <= 64; |
| 861 | } |
| 862 | case GICXXPred_I64_Predicate_t2_so_imm: { |
| 863 | |
| 864 | return ARM_AM::getT2SOImmVal(Imm) != -1; |
| 865 | |
| 866 | } |
| 867 | case GICXXPred_I64_Predicate_t2_so_imm_neg: { |
| 868 | |
| 869 | return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1; |
| 870 | |
| 871 | } |
| 872 | } |
| 873 | llvm_unreachable("Unknown predicate"); |
| 874 | return false; |
| 875 | } |
| 876 | // PatFrag predicates. |
| 877 | bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { |
| 878 | llvm_unreachable("Unknown predicate"); |
| 879 | return false; |
| 880 | } |
| 881 | // PatFrag predicates. |
| 882 | enum { |
| 883 | GICXXPred_APInt_Predicate_arm_i32imm = GICXXPred_Invalid + 1, |
| 884 | }; |
| 885 | bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { |
| 886 | switch (PredicateID) { |
| 887 | case GICXXPred_APInt_Predicate_arm_i32imm: { |
| 888 | |
| 889 | if (Subtarget->useMovt()) |
| 890 | return true; |
| 891 | if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue())) |
| 892 | return true; |
| 893 | return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue()); |
| 894 | |
| 895 | llvm_unreachable("arm_i32imm should have returned"); |
| 896 | } |
| 897 | } |
| 898 | llvm_unreachable("Unknown predicate"); |
| 899 | return false; |
| 900 | } |
| 901 | bool ARMInstructionSelector::testSimplePredicate(unsigned) const { |
| 902 | llvm_unreachable("ARMInstructionSelector does not support simple predicates!"); |
| 903 | return false; |
| 904 | } |
| 905 | // Custom renderers. |
| 906 | enum { |
| 907 | GICR_Invalid, |
| 908 | GICR_renderInvertedImm, |
| 909 | GICR_renderVFPF32Imm, |
| 910 | GICR_renderVFPF64Imm, |
| 911 | }; |
| 912 | ARMInstructionSelector::CustomRendererFn |
| 913 | ARMInstructionSelector::CustomRenderers[] = { |
| 914 | nullptr, // GICR_Invalid |
| 915 | &ARMInstructionSelector::renderInvertedImm, |
| 916 | &ARMInstructionSelector::renderVFPF32Imm, |
| 917 | &ARMInstructionSelector::renderVFPF64Imm, |
| 918 | }; |
| 919 | |
| 920 | bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { |
| 921 | const PredicateBitset AvailableFeatures = getAvailableFeatures(); |
| 922 | MachineIRBuilder B(I); |
| 923 | State.MIs.clear(); |
| 924 | State.MIs.push_back(&I); |
| 925 | |
| 926 | if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) { |
| 927 | return true; |
| 928 | } |
| 929 | |
| 930 | return false; |
| 931 | } |
| 932 | |
| 933 | bool ARMInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const { |
| 934 | llvm_unreachable("ARMInstructionSelector does not support custom C++ actions!"); |
| 935 | } |
| 936 | #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ |
| 937 | #define GIMT_Encode2(Val) uint8_t(Val), uint8_t((Val) >> 8) |
| 938 | #define GIMT_Encode4(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24) |
| 939 | #define GIMT_Encode8(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24), uint8_t(uint64_t(Val) >> 32), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 56) |
| 940 | #else |
| 941 | #define GIMT_Encode2(Val) uint8_t((Val) >> 8), uint8_t(Val) |
| 942 | #define GIMT_Encode4(Val) uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val) |
| 943 | #define GIMT_Encode8(Val) uint8_t(uint64_t(Val) >> 56), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 32), uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val) |
| 944 | #endif |
| 945 | const uint8_t *ARMInstructionSelector::getMatchTable() const { |
| 946 | constexpr static uint8_t MatchTable0[] = { |
| 947 | /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(55), GIMT_Encode2(329), /*)*//*default:*//*Label 94*/ GIMT_Encode4(131919), |
| 948 | /* 10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(1106), |
| 949 | /* 14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(12534), |
| 950 | /* 18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(15632), |
| 951 | /* 22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(17295), |
| 952 | /* 26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(17389), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 953 | /* 46 */ /*TargetOpcode::G_AND*//*Label 5*/ GIMT_Encode4(17483), |
| 954 | /* 50 */ /*TargetOpcode::G_OR*//*Label 6*/ GIMT_Encode4(20583), |
| 955 | /* 54 */ /*TargetOpcode::G_XOR*//*Label 7*/ GIMT_Encode4(26309), |
| 956 | /* 58 */ /*TargetOpcode::G_ABDS*//*Label 8*/ GIMT_Encode4(27968), |
| 957 | /* 62 */ /*TargetOpcode::G_ABDU*//*Label 9*/ GIMT_Encode4(28478), |
| 958 | /* 66 */ /*TargetOpcode::G_UAVGFLOOR*//*Label 10*/ GIMT_Encode4(28988), |
| 959 | /* 70 */ /*TargetOpcode::G_UAVGCEIL*//*Label 11*/ GIMT_Encode4(29215), |
| 960 | /* 74 */ /*TargetOpcode::G_SAVGFLOOR*//*Label 12*/ GIMT_Encode4(29442), |
| 961 | /* 78 */ /*TargetOpcode::G_SAVGCEIL*//*Label 13*/ GIMT_Encode4(29669), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 962 | /* 130 */ /*TargetOpcode::G_CONCAT_VECTORS*//*Label 14*/ GIMT_Encode4(29896), GIMT_Encode4(0), GIMT_Encode4(0), |
| 963 | /* 142 */ /*TargetOpcode::G_BITCAST*//*Label 15*/ GIMT_Encode4(30563), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 964 | /* 158 */ /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 16*/ GIMT_Encode4(37750), |
| 965 | /* 162 */ /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 17*/ GIMT_Encode4(38149), GIMT_Encode4(0), GIMT_Encode4(0), |
| 966 | /* 174 */ /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 18*/ GIMT_Encode4(38515), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 967 | /* 190 */ /*TargetOpcode::G_SEXTLOAD*//*Label 19*/ GIMT_Encode4(38881), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 968 | /* 326 */ /*TargetOpcode::G_FENCE*//*Label 20*/ GIMT_Encode4(39042), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 969 | /* 346 */ /*TargetOpcode::G_INTRINSIC*//*Label 21*/ GIMT_Encode4(39063), |
| 970 | /* 350 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 22*/ GIMT_Encode4(90359), GIMT_Encode4(0), GIMT_Encode4(0), |
| 971 | /* 362 */ /*TargetOpcode::G_ANYEXT*//*Label 23*/ GIMT_Encode4(96139), |
| 972 | /* 366 */ /*TargetOpcode::G_TRUNC*//*Label 24*/ GIMT_Encode4(96278), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 973 | /* 382 */ /*TargetOpcode::G_CONSTANT*//*Label 25*/ GIMT_Encode4(96421), |
| 974 | /* 386 */ /*TargetOpcode::G_FCONSTANT*//*Label 26*/ GIMT_Encode4(96733), GIMT_Encode4(0), GIMT_Encode4(0), |
| 975 | /* 398 */ /*TargetOpcode::G_SEXT*//*Label 27*/ GIMT_Encode4(96827), |
| 976 | /* 402 */ /*TargetOpcode::G_SEXT_INREG*//*Label 28*/ GIMT_Encode4(96966), |
| 977 | /* 406 */ /*TargetOpcode::G_ZEXT*//*Label 29*/ GIMT_Encode4(97556), |
| 978 | /* 410 */ /*TargetOpcode::G_SHL*//*Label 30*/ GIMT_Encode4(98244), |
| 979 | /* 414 */ /*TargetOpcode::G_LSHR*//*Label 31*/ GIMT_Encode4(98456), |
| 980 | /* 418 */ /*TargetOpcode::G_ASHR*//*Label 32*/ GIMT_Encode4(98562), GIMT_Encode4(0), GIMT_Encode4(0), |
| 981 | /* 430 */ /*TargetOpcode::G_ROTR*//*Label 33*/ GIMT_Encode4(98830), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 982 | /* 498 */ /*TargetOpcode::G_UMULH*//*Label 34*/ GIMT_Encode4(99156), |
| 983 | /* 502 */ /*TargetOpcode::G_SMULH*//*Label 35*/ GIMT_Encode4(99389), |
| 984 | /* 506 */ /*TargetOpcode::G_UADDSAT*//*Label 36*/ GIMT_Encode4(99741), |
| 985 | /* 510 */ /*TargetOpcode::G_SADDSAT*//*Label 37*/ GIMT_Encode4(100367), |
| 986 | /* 514 */ /*TargetOpcode::G_USUBSAT*//*Label 38*/ GIMT_Encode4(101640), |
| 987 | /* 518 */ /*TargetOpcode::G_SSUBSAT*//*Label 39*/ GIMT_Encode4(102266), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 988 | /* 562 */ /*TargetOpcode::G_FADD*//*Label 40*/ GIMT_Encode4(103259), |
| 989 | /* 566 */ /*TargetOpcode::G_FSUB*//*Label 41*/ GIMT_Encode4(105594), |
| 990 | /* 570 */ /*TargetOpcode::G_FMUL*//*Label 42*/ GIMT_Encode4(107247), |
| 991 | /* 574 */ /*TargetOpcode::G_FMA*//*Label 43*/ GIMT_Encode4(108216), GIMT_Encode4(0), |
| 992 | /* 582 */ /*TargetOpcode::G_FDIV*//*Label 44*/ GIMT_Encode4(110279), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 993 | /* 634 */ /*TargetOpcode::G_FNEG*//*Label 45*/ GIMT_Encode4(110441), |
| 994 | /* 638 */ /*TargetOpcode::G_FPEXT*//*Label 46*/ GIMT_Encode4(112849), |
| 995 | /* 642 */ /*TargetOpcode::G_FPTRUNC*//*Label 47*/ GIMT_Encode4(113113), |
| 996 | /* 646 */ /*TargetOpcode::G_FPTOSI*//*Label 48*/ GIMT_Encode4(113405), |
| 997 | /* 650 */ /*TargetOpcode::G_FPTOUI*//*Label 49*/ GIMT_Encode4(114687), |
| 998 | /* 654 */ /*TargetOpcode::G_SITOFP*//*Label 50*/ GIMT_Encode4(115969), |
| 999 | /* 658 */ /*TargetOpcode::G_UITOFP*//*Label 51*/ GIMT_Encode4(116611), |
| 1000 | /* 662 */ /*TargetOpcode::G_FPTOSI_SAT*//*Label 52*/ GIMT_Encode4(117253), |
| 1001 | /* 666 */ /*TargetOpcode::G_FPTOUI_SAT*//*Label 53*/ GIMT_Encode4(117616), |
| 1002 | /* 670 */ /*TargetOpcode::G_FABS*//*Label 54*/ GIMT_Encode4(117979), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1003 | /* 686 */ /*TargetOpcode::G_FMINNUM*//*Label 55*/ GIMT_Encode4(118743), |
| 1004 | /* 690 */ /*TargetOpcode::G_FMAXNUM*//*Label 56*/ GIMT_Encode4(119324), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1005 | /* 702 */ /*TargetOpcode::G_FMINIMUM*//*Label 57*/ GIMT_Encode4(119905), |
| 1006 | /* 706 */ /*TargetOpcode::G_FMAXIMUM*//*Label 58*/ GIMT_Encode4(120633), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1007 | /* 718 */ /*TargetOpcode::G_GET_FPENV*//*Label 59*/ GIMT_Encode4(121361), |
| 1008 | /* 722 */ /*TargetOpcode::G_SET_FPENV*//*Label 60*/ GIMT_Encode4(121394), |
| 1009 | /* 726 */ /*TargetOpcode::G_RESET_FPENV*//*Label 61*/ GIMT_Encode4(121430), |
| 1010 | /* 730 */ /*TargetOpcode::G_GET_FPMODE*//*Label 62*/ GIMT_Encode4(121557), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1011 | /* 758 */ /*TargetOpcode::G_SMIN*//*Label 63*/ GIMT_Encode4(121590), |
| 1012 | /* 762 */ /*TargetOpcode::G_SMAX*//*Label 64*/ GIMT_Encode4(122100), |
| 1013 | /* 766 */ /*TargetOpcode::G_UMIN*//*Label 65*/ GIMT_Encode4(122610), |
| 1014 | /* 770 */ /*TargetOpcode::G_UMAX*//*Label 66*/ GIMT_Encode4(123498), |
| 1015 | /* 774 */ /*TargetOpcode::G_ABS*//*Label 67*/ GIMT_Encode4(124386), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1016 | /* 786 */ /*TargetOpcode::G_BR*//*Label 68*/ GIMT_Encode4(124824), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1017 | /* 806 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 69*/ GIMT_Encode4(124894), |
| 1018 | /* 810 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 70*/ GIMT_Encode4(125170), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1019 | /* 838 */ /*TargetOpcode::G_CTLZ*//*Label 71*/ GIMT_Encode4(125226), GIMT_Encode4(0), |
| 1020 | /* 846 */ /*TargetOpcode::G_CTLS*//*Label 72*/ GIMT_Encode4(125764), |
| 1021 | /* 850 */ /*TargetOpcode::G_CTPOP*//*Label 73*/ GIMT_Encode4(126202), |
| 1022 | /* 854 */ /*TargetOpcode::G_BSWAP*//*Label 74*/ GIMT_Encode4(126296), |
| 1023 | /* 858 */ /*TargetOpcode::G_BITREVERSE*//*Label 75*/ GIMT_Encode4(126581), GIMT_Encode4(0), |
| 1024 | /* 866 */ /*TargetOpcode::G_FCEIL*//*Label 76*/ GIMT_Encode4(126996), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1025 | /* 914 */ /*TargetOpcode::G_FSQRT*//*Label 77*/ GIMT_Encode4(127362), |
| 1026 | /* 918 */ /*TargetOpcode::G_FFLOOR*//*Label 78*/ GIMT_Encode4(127497), |
| 1027 | /* 922 */ /*TargetOpcode::G_FRINT*//*Label 79*/ GIMT_Encode4(127863), |
| 1028 | /* 926 */ /*TargetOpcode::G_FNEARBYINT*//*Label 80*/ GIMT_Encode4(128262), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1029 | /* 954 */ /*TargetOpcode::G_STRICT_FADD*//*Label 81*/ GIMT_Encode4(128397), |
| 1030 | /* 958 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 82*/ GIMT_Encode4(128559), |
| 1031 | /* 962 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 83*/ GIMT_Encode4(128721), |
| 1032 | /* 966 */ /*TargetOpcode::G_STRICT_FDIV*//*Label 84*/ GIMT_Encode4(128883), GIMT_Encode4(0), |
| 1033 | /* 974 */ /*TargetOpcode::G_STRICT_FMA*//*Label 85*/ GIMT_Encode4(129045), |
| 1034 | /* 978 */ /*TargetOpcode::G_STRICT_FSQRT*//*Label 86*/ GIMT_Encode4(130212), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1035 | /* 1026 */ /*TargetOpcode::G_TRAP*//*Label 87*/ GIMT_Encode4(130347), |
| 1036 | /* 1030 */ /*TargetOpcode::G_DEBUGTRAP*//*Label 88*/ GIMT_Encode4(130376), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1037 | /* 1070 */ /*TargetOpcode::G_VECREDUCE_ADD*//*Label 89*/ GIMT_Encode4(130459), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1038 | /* 1090 */ /*TargetOpcode::G_VECREDUCE_SMAX*//*Label 90*/ GIMT_Encode4(130833), |
| 1039 | /* 1094 */ /*TargetOpcode::G_VECREDUCE_SMIN*//*Label 91*/ GIMT_Encode4(131098), |
| 1040 | /* 1098 */ /*TargetOpcode::G_VECREDUCE_UMAX*//*Label 92*/ GIMT_Encode4(131372), |
| 1041 | /* 1102 */ /*TargetOpcode::G_VECREDUCE_UMIN*//*Label 93*/ GIMT_Encode4(131638), |
| 1042 | /* 1106 */ // Label 0: @1106 |
| 1043 | /* 1106 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 104*/ GIMT_Encode4(12533), |
| 1044 | /* 1117 */ /*GILLT_s32*//*Label 95*/ GIMT_Encode4(1169), |
| 1045 | /* 1121 */ /*GILLT_s64*//*Label 96*/ GIMT_Encode4(6812), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 1046 | /* 1141 */ /*GILLT_v8s8*//*Label 97*/ GIMT_Encode4(6858), |
| 1047 | /* 1145 */ /*GILLT_v16s8*//*Label 98*/ GIMT_Encode4(7292), |
| 1048 | /* 1149 */ /*GILLT_v4s16*//*Label 99*/ GIMT_Encode4(7792), |
| 1049 | /* 1153 */ /*GILLT_v8s16*//*Label 100*/ GIMT_Encode4(8226), |
| 1050 | /* 1157 */ /*GILLT_v2s32*//*Label 101*/ GIMT_Encode4(9661), |
| 1051 | /* 1161 */ /*GILLT_v4s32*//*Label 102*/ GIMT_Encode4(10095), |
| 1052 | /* 1165 */ /*GILLT_v2s64*//*Label 103*/ GIMT_Encode4(11530), |
| 1053 | /* 1169 */ // Label 95: @1169 |
| 1054 | /* 1169 */ GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(6811), |
| 1055 | /* 1174 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 1056 | /* 1177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 1057 | /* 1180 */ GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(1326), |
| 1058 | /* 1185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1059 | /* 1189 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1060 | /* 1193 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 107*/ GIMT_Encode4(1259), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6264 // |
| 1061 | /* 1200 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1062 | /* 1204 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1063 | /* 1208 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1064 | /* 1212 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1065 | /* 1216 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1066 | /* 1221 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1067 | /* 1232 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1068 | /* 1234 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1069 | /* 1234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB), |
| 1070 | /* 1237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1071 | /* 1239 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1072 | /* 1241 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1073 | /* 1245 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1074 | /* 1248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1075 | /* 1251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1076 | /* 1257 */ GIR_RootConstrainSelectedInstOperands, |
| 1077 | /* 1258 */ // GIR_Coverage, 6264, |
| 1078 | /* 1258 */ GIR_EraseRootFromParent_Done, |
| 1079 | /* 1259 */ // Label 107: @1259 |
| 1080 | /* 1259 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 108*/ GIMT_Encode4(1325), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6265 // |
| 1081 | /* 1266 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1082 | /* 1270 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1083 | /* 1274 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1084 | /* 1278 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1085 | /* 1282 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1086 | /* 1287 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1087 | /* 1298 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1088 | /* 1300 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1089 | /* 1300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH), |
| 1090 | /* 1303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1091 | /* 1305 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1092 | /* 1307 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1093 | /* 1311 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1094 | /* 1314 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1095 | /* 1317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1096 | /* 1323 */ GIR_RootConstrainSelectedInstOperands, |
| 1097 | /* 1324 */ // GIR_Coverage, 6265, |
| 1098 | /* 1324 */ GIR_EraseRootFromParent_Done, |
| 1099 | /* 1325 */ // Label 108: @1325 |
| 1100 | /* 1325 */ GIM_Reject, |
| 1101 | /* 1326 */ // Label 106: @1326 |
| 1102 | /* 1326 */ GIM_Try, /*On fail goto*//*Label 109*/ GIMT_Encode4(1472), |
| 1103 | /* 1331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1104 | /* 1335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1105 | /* 1339 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 110*/ GIMT_Encode4(1405), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6302 // |
| 1106 | /* 1346 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1107 | /* 1350 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1108 | /* 1354 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1109 | /* 1358 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1110 | /* 1362 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1111 | /* 1367 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1112 | /* 1378 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1113 | /* 1380 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1114 | /* 1380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB), |
| 1115 | /* 1383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1116 | /* 1385 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1117 | /* 1387 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1118 | /* 1391 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1119 | /* 1394 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1120 | /* 1397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1121 | /* 1403 */ GIR_RootConstrainSelectedInstOperands, |
| 1122 | /* 1404 */ // GIR_Coverage, 6302, |
| 1123 | /* 1404 */ GIR_EraseRootFromParent_Done, |
| 1124 | /* 1405 */ // Label 110: @1405 |
| 1125 | /* 1405 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 111*/ GIMT_Encode4(1471), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6303 // |
| 1126 | /* 1412 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1127 | /* 1416 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1128 | /* 1420 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1129 | /* 1424 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1130 | /* 1428 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1131 | /* 1433 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1132 | /* 1444 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1133 | /* 1446 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1134 | /* 1446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH), |
| 1135 | /* 1449 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1136 | /* 1451 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1137 | /* 1453 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1138 | /* 1457 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1139 | /* 1460 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1140 | /* 1463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1141 | /* 1469 */ GIR_RootConstrainSelectedInstOperands, |
| 1142 | /* 1470 */ // GIR_Coverage, 6303, |
| 1143 | /* 1470 */ GIR_EraseRootFromParent_Done, |
| 1144 | /* 1471 */ // Label 111: @1471 |
| 1145 | /* 1471 */ GIM_Reject, |
| 1146 | /* 1472 */ // Label 109: @1472 |
| 1147 | /* 1472 */ GIM_Try, /*On fail goto*//*Label 112*/ GIMT_Encode4(1618), |
| 1148 | /* 1477 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1149 | /* 1481 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1150 | /* 1485 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 113*/ GIMT_Encode4(1551), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2193 // |
| 1151 | /* 1492 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1152 | /* 1496 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1153 | /* 1500 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1154 | /* 1504 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1155 | /* 1508 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1156 | /* 1513 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1157 | /* 1524 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1158 | /* 1526 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1159 | /* 1526 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB), |
| 1160 | /* 1529 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1161 | /* 1531 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1162 | /* 1533 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1163 | /* 1537 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1164 | /* 1540 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1165 | /* 1543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1166 | /* 1549 */ GIR_RootConstrainSelectedInstOperands, |
| 1167 | /* 1550 */ // GIR_Coverage, 2193, |
| 1168 | /* 1550 */ GIR_EraseRootFromParent_Done, |
| 1169 | /* 1551 */ // Label 113: @1551 |
| 1170 | /* 1551 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 114*/ GIMT_Encode4(1617), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2194 // |
| 1171 | /* 1558 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1172 | /* 1562 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1173 | /* 1566 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1174 | /* 1570 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1175 | /* 1574 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1176 | /* 1579 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1177 | /* 1590 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1178 | /* 1592 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1179 | /* 1592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH), |
| 1180 | /* 1595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1181 | /* 1597 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1182 | /* 1599 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1183 | /* 1603 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1184 | /* 1606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1185 | /* 1609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1186 | /* 1615 */ GIR_RootConstrainSelectedInstOperands, |
| 1187 | /* 1616 */ // GIR_Coverage, 2194, |
| 1188 | /* 1616 */ GIR_EraseRootFromParent_Done, |
| 1189 | /* 1617 */ // Label 114: @1617 |
| 1190 | /* 1617 */ GIM_Reject, |
| 1191 | /* 1618 */ // Label 112: @1618 |
| 1192 | /* 1618 */ GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(2266), |
| 1193 | /* 1623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1194 | /* 1627 */ GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(1769), |
| 1195 | /* 1632 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1196 | /* 1636 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 117*/ GIMT_Encode4(1702), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2436 // |
| 1197 | /* 1643 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1198 | /* 1647 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1199 | /* 1651 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1200 | /* 1655 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1201 | /* 1659 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1202 | /* 1664 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 1203 | /* 1675 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1204 | /* 1677 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1205 | /* 1677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB), |
| 1206 | /* 1680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1207 | /* 1682 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1208 | /* 1684 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1209 | /* 1688 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1210 | /* 1691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1211 | /* 1694 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1212 | /* 1700 */ GIR_RootConstrainSelectedInstOperands, |
| 1213 | /* 1701 */ // GIR_Coverage, 2436, |
| 1214 | /* 1701 */ GIR_EraseRootFromParent_Done, |
| 1215 | /* 1702 */ // Label 117: @1702 |
| 1216 | /* 1702 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 118*/ GIMT_Encode4(1768), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2437 // |
| 1217 | /* 1709 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1218 | /* 1713 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 1219 | /* 1717 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1220 | /* 1721 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1221 | /* 1725 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1222 | /* 1730 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 1223 | /* 1741 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 1224 | /* 1743 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 1225 | /* 1743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH), |
| 1226 | /* 1746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1227 | /* 1748 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1228 | /* 1750 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 1229 | /* 1754 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1230 | /* 1757 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1231 | /* 1760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1232 | /* 1766 */ GIR_RootConstrainSelectedInstOperands, |
| 1233 | /* 1767 */ // GIR_Coverage, 2437, |
| 1234 | /* 1767 */ GIR_EraseRootFromParent_Done, |
| 1235 | /* 1768 */ // Label 118: @1768 |
| 1236 | /* 1768 */ GIM_Reject, |
| 1237 | /* 1769 */ // Label 116: @1769 |
| 1238 | /* 1769 */ GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(2017), |
| 1239 | /* 1774 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1240 | /* 1778 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 120*/ GIMT_Encode4(1897), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6276 // |
| 1241 | /* 1785 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1242 | /* 1789 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1243 | /* 1793 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1244 | /* 1797 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1245 | /* 1801 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1246 | /* 1805 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1247 | /* 1809 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1248 | /* 1813 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1249 | /* 1817 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1250 | /* 1821 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1251 | /* 1825 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1252 | /* 1829 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1253 | /* 1834 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24, |
| 1254 | /* 1838 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1255 | /* 1842 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1256 | /* 1846 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1257 | /* 1850 */ // MIs[4] Rm |
| 1258 | /* 1850 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1259 | /* 1855 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 1260 | /* 1859 */ // MIs[1] Operand 2 |
| 1261 | /* 1859 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1262 | /* 1870 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1263 | /* 1872 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1264 | /* 1872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1265 | /* 1875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1266 | /* 1877 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1267 | /* 1879 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1268 | /* 1883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1269 | /* 1886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1270 | /* 1889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1271 | /* 1895 */ GIR_RootConstrainSelectedInstOperands, |
| 1272 | /* 1896 */ // GIR_Coverage, 6276, |
| 1273 | /* 1896 */ GIR_EraseRootFromParent_Done, |
| 1274 | /* 1897 */ // Label 120: @1897 |
| 1275 | /* 1897 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 121*/ GIMT_Encode4(2016), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6277 // |
| 1276 | /* 1904 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1277 | /* 1908 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1278 | /* 1912 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1279 | /* 1916 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1280 | /* 1920 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1281 | /* 1924 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1282 | /* 1928 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1283 | /* 1932 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1284 | /* 1936 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1285 | /* 1940 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1286 | /* 1944 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1287 | /* 1948 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1288 | /* 1953 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8, |
| 1289 | /* 1957 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1290 | /* 1961 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1291 | /* 1965 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1292 | /* 1969 */ // MIs[4] Rm |
| 1293 | /* 1969 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1294 | /* 1974 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 1295 | /* 1978 */ // MIs[1] Operand 2 |
| 1296 | /* 1978 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1297 | /* 1989 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1298 | /* 1991 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1299 | /* 1991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1300 | /* 1994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1301 | /* 1996 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1302 | /* 1998 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1303 | /* 2002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1304 | /* 2005 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1305 | /* 2008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1306 | /* 2014 */ GIR_RootConstrainSelectedInstOperands, |
| 1307 | /* 2015 */ // GIR_Coverage, 6277, |
| 1308 | /* 2015 */ GIR_EraseRootFromParent_Done, |
| 1309 | /* 2016 */ // Label 121: @2016 |
| 1310 | /* 2016 */ GIM_Reject, |
| 1311 | /* 2017 */ // Label 119: @2017 |
| 1312 | /* 2017 */ GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(2265), |
| 1313 | /* 2022 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1314 | /* 2026 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 123*/ GIMT_Encode4(2145), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2300 // |
| 1315 | /* 2033 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1316 | /* 2037 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1317 | /* 2041 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1318 | /* 2045 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1319 | /* 2049 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1320 | /* 2053 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1321 | /* 2057 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1322 | /* 2061 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1323 | /* 2065 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1324 | /* 2069 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1325 | /* 2073 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1326 | /* 2077 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1327 | /* 2082 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24, |
| 1328 | /* 2086 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1329 | /* 2090 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1330 | /* 2094 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1331 | /* 2098 */ // MIs[4] Rm |
| 1332 | /* 2098 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1333 | /* 2103 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 1334 | /* 2107 */ // MIs[1] Operand 2 |
| 1335 | /* 2107 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1336 | /* 2118 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1337 | /* 2120 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1338 | /* 2120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1339 | /* 2123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1340 | /* 2125 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1341 | /* 2127 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1342 | /* 2131 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1343 | /* 2134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1344 | /* 2137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1345 | /* 2143 */ GIR_RootConstrainSelectedInstOperands, |
| 1346 | /* 2144 */ // GIR_Coverage, 2300, |
| 1347 | /* 2144 */ GIR_EraseRootFromParent_Done, |
| 1348 | /* 2145 */ // Label 123: @2145 |
| 1349 | /* 2145 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 124*/ GIMT_Encode4(2264), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6275 // |
| 1350 | /* 2152 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1351 | /* 2156 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1352 | /* 2160 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1353 | /* 2164 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1354 | /* 2168 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 1355 | /* 2172 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1356 | /* 2176 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1357 | /* 2180 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 1358 | /* 2184 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 1359 | /* 2188 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1360 | /* 2192 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1361 | /* 2196 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1362 | /* 2201 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8, |
| 1363 | /* 2205 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4] |
| 1364 | /* 2209 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 1365 | /* 2213 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 1366 | /* 2217 */ // MIs[4] Rm |
| 1367 | /* 2217 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1, |
| 1368 | /* 2222 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 1369 | /* 2226 */ // MIs[1] Operand 2 |
| 1370 | /* 2226 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1371 | /* 2237 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 1372 | /* 2239 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1373 | /* 2239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1374 | /* 2242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1375 | /* 2244 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1376 | /* 2246 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1377 | /* 2250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1378 | /* 2253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1379 | /* 2256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1380 | /* 2262 */ GIR_RootConstrainSelectedInstOperands, |
| 1381 | /* 2263 */ // GIR_Coverage, 6275, |
| 1382 | /* 2263 */ GIR_EraseRootFromParent_Done, |
| 1383 | /* 2264 */ // Label 124: @2264 |
| 1384 | /* 2264 */ GIM_Reject, |
| 1385 | /* 2265 */ // Label 122: @2265 |
| 1386 | /* 2265 */ GIM_Reject, |
| 1387 | /* 2266 */ // Label 115: @2266 |
| 1388 | /* 2266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 125*/ GIMT_Encode4(2375), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5975 // |
| 1389 | /* 2273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1390 | /* 2277 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1391 | /* 2281 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1392 | /* 2285 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1393 | /* 2289 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1394 | /* 2293 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1395 | /* 2297 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1396 | /* 2301 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1397 | /* 2305 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1398 | /* 2309 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1399 | /* 2314 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1400 | /* 2318 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1401 | /* 2322 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1402 | /* 2326 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1403 | /* 2330 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1404 | /* 2334 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1405 | /* 2339 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1406 | /* 2343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1407 | /* 2347 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1408 | /* 2349 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1409 | /* 2349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), |
| 1410 | /* 2352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1411 | /* 2354 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1412 | /* 2358 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1413 | /* 2362 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1414 | /* 2364 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1415 | /* 2367 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1416 | /* 2373 */ GIR_RootConstrainSelectedInstOperands, |
| 1417 | /* 2374 */ // GIR_Coverage, 5975, |
| 1418 | /* 2374 */ GIR_EraseRootFromParent_Done, |
| 1419 | /* 2375 */ // Label 125: @2375 |
| 1420 | /* 2375 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 126*/ GIMT_Encode4(2484), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6010 // |
| 1421 | /* 2382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1422 | /* 2386 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1423 | /* 2390 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1424 | /* 2394 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1425 | /* 2398 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1426 | /* 2402 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1427 | /* 2406 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1428 | /* 2410 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1429 | /* 2414 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1430 | /* 2418 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1431 | /* 2423 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1432 | /* 2427 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1433 | /* 2431 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1434 | /* 2435 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1435 | /* 2439 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1436 | /* 2443 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1437 | /* 2448 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1438 | /* 2452 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1439 | /* 2456 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1440 | /* 2458 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1441 | /* 2458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), |
| 1442 | /* 2461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1443 | /* 2463 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1444 | /* 2467 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1445 | /* 2471 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1446 | /* 2473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1447 | /* 2476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1448 | /* 2482 */ GIR_RootConstrainSelectedInstOperands, |
| 1449 | /* 2483 */ // GIR_Coverage, 6010, |
| 1450 | /* 2483 */ GIR_EraseRootFromParent_Done, |
| 1451 | /* 2484 */ // Label 126: @2484 |
| 1452 | /* 2484 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 127*/ GIMT_Encode4(2593), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 191 // |
| 1453 | /* 2491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1454 | /* 2495 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1455 | /* 2499 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1456 | /* 2503 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1457 | /* 2507 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1458 | /* 2511 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1459 | /* 2515 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1460 | /* 2519 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1461 | /* 2523 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1462 | /* 2527 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1463 | /* 2531 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1464 | /* 2536 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1465 | /* 2540 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1466 | /* 2544 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1467 | /* 2548 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1468 | /* 2552 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1469 | /* 2556 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1470 | /* 2561 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1471 | /* 2565 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1472 | /* 2567 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1473 | /* 2567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), |
| 1474 | /* 2570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1475 | /* 2572 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1476 | /* 2576 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1477 | /* 2580 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1478 | /* 2582 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1479 | /* 2585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1480 | /* 2591 */ GIR_RootConstrainSelectedInstOperands, |
| 1481 | /* 2592 */ // GIR_Coverage, 191, |
| 1482 | /* 2592 */ GIR_EraseRootFromParent_Done, |
| 1483 | /* 2593 */ // Label 127: @2593 |
| 1484 | /* 2593 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 128*/ GIMT_Encode4(2702), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 520 // |
| 1485 | /* 2600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1486 | /* 2604 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1487 | /* 2608 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1488 | /* 2612 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1489 | /* 2616 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1490 | /* 2620 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1491 | /* 2624 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1492 | /* 2628 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1493 | /* 2632 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1494 | /* 2636 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1495 | /* 2640 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1496 | /* 2645 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1497 | /* 2649 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1498 | /* 2653 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1499 | /* 2657 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1500 | /* 2661 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1501 | /* 2665 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1502 | /* 2670 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1503 | /* 2674 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1504 | /* 2676 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1505 | /* 2676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), |
| 1506 | /* 2679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1507 | /* 2681 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1508 | /* 2685 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1509 | /* 2689 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1510 | /* 2691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1511 | /* 2694 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1512 | /* 2700 */ GIR_RootConstrainSelectedInstOperands, |
| 1513 | /* 2701 */ // GIR_Coverage, 520, |
| 1514 | /* 2701 */ GIR_EraseRootFromParent_Done, |
| 1515 | /* 2702 */ // Label 128: @2702 |
| 1516 | /* 2702 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 129*/ GIMT_Encode4(2814), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5974 // |
| 1517 | /* 2709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1518 | /* 2713 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1519 | /* 2717 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1520 | /* 2721 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1521 | /* 2725 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1522 | /* 2729 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1523 | /* 2733 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1524 | /* 2737 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1525 | /* 2741 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1526 | /* 2745 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1527 | /* 2750 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1528 | /* 2754 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1529 | /* 2758 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1530 | /* 2762 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1531 | /* 2766 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1532 | /* 2771 */ // MIs[3] Operand 2 |
| 1533 | /* 2771 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1534 | /* 2782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1535 | /* 2786 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1536 | /* 2788 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1537 | /* 2788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 1538 | /* 2791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1539 | /* 2793 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 1540 | /* 2797 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1541 | /* 2801 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1542 | /* 2803 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1543 | /* 2806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1544 | /* 2812 */ GIR_RootConstrainSelectedInstOperands, |
| 1545 | /* 2813 */ // GIR_Coverage, 5974, |
| 1546 | /* 2813 */ GIR_EraseRootFromParent_Done, |
| 1547 | /* 2814 */ // Label 129: @2814 |
| 1548 | /* 2814 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 130*/ GIMT_Encode4(2926), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6009 // |
| 1549 | /* 2821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1550 | /* 2825 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1551 | /* 2829 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1552 | /* 2833 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1553 | /* 2837 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1554 | /* 2841 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1555 | /* 2845 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1556 | /* 2849 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1557 | /* 2853 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1558 | /* 2857 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1559 | /* 2862 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1560 | /* 2866 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1561 | /* 2870 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1562 | /* 2874 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1563 | /* 2878 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1564 | /* 2883 */ // MIs[3] Operand 2 |
| 1565 | /* 2883 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1566 | /* 2894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1567 | /* 2898 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1568 | /* 2900 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1569 | /* 2900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 1570 | /* 2903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1571 | /* 2905 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 1572 | /* 2909 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1573 | /* 2913 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1574 | /* 2915 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1575 | /* 2918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1576 | /* 2924 */ GIR_RootConstrainSelectedInstOperands, |
| 1577 | /* 2925 */ // GIR_Coverage, 6009, |
| 1578 | /* 2925 */ GIR_EraseRootFromParent_Done, |
| 1579 | /* 2926 */ // Label 130: @2926 |
| 1580 | /* 2926 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 131*/ GIMT_Encode4(3038), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5973 // |
| 1581 | /* 2933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1582 | /* 2937 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1583 | /* 2941 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1584 | /* 2945 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1585 | /* 2949 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1586 | /* 2953 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1587 | /* 2957 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1588 | /* 2961 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1589 | /* 2965 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1590 | /* 2970 */ // MIs[2] Operand 2 |
| 1591 | /* 2970 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1592 | /* 2981 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1593 | /* 2985 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1594 | /* 2989 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1595 | /* 2993 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1596 | /* 2997 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1597 | /* 3002 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1598 | /* 3006 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1599 | /* 3010 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1600 | /* 3012 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1601 | /* 3012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 1602 | /* 3015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1603 | /* 3017 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1604 | /* 3021 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1605 | /* 3025 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1606 | /* 3027 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1607 | /* 3030 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1608 | /* 3036 */ GIR_RootConstrainSelectedInstOperands, |
| 1609 | /* 3037 */ // GIR_Coverage, 5973, |
| 1610 | /* 3037 */ GIR_EraseRootFromParent_Done, |
| 1611 | /* 3038 */ // Label 131: @3038 |
| 1612 | /* 3038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 132*/ GIMT_Encode4(3150), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6008 // |
| 1613 | /* 3045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1614 | /* 3049 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1615 | /* 3053 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1616 | /* 3057 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1617 | /* 3061 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1618 | /* 3065 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1619 | /* 3069 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1620 | /* 3073 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1621 | /* 3077 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1622 | /* 3082 */ // MIs[2] Operand 2 |
| 1623 | /* 3082 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1624 | /* 3093 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1625 | /* 3097 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1626 | /* 3101 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1627 | /* 3105 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1628 | /* 3109 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1629 | /* 3114 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1630 | /* 3118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1631 | /* 3122 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1632 | /* 3124 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1633 | /* 3124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 1634 | /* 3127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1635 | /* 3129 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1636 | /* 3133 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1637 | /* 3137 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1638 | /* 3139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1639 | /* 3142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1640 | /* 3148 */ GIR_RootConstrainSelectedInstOperands, |
| 1641 | /* 3149 */ // GIR_Coverage, 6008, |
| 1642 | /* 3149 */ GIR_EraseRootFromParent_Done, |
| 1643 | /* 3150 */ // Label 132: @3150 |
| 1644 | /* 3150 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 133*/ GIMT_Encode4(3262), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 190 // |
| 1645 | /* 3157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1646 | /* 3161 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1647 | /* 3165 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1648 | /* 3169 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1649 | /* 3173 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1650 | /* 3177 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1651 | /* 3181 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1652 | /* 3185 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1653 | /* 3189 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1654 | /* 3193 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1655 | /* 3197 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1656 | /* 3202 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1657 | /* 3206 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1658 | /* 3210 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1659 | /* 3214 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1660 | /* 3218 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1661 | /* 3223 */ // MIs[3] Operand 2 |
| 1662 | /* 3223 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1663 | /* 3234 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1664 | /* 3236 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLATB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1665 | /* 3236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB), |
| 1666 | /* 3239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1667 | /* 3241 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1668 | /* 3245 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1669 | /* 3249 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1670 | /* 3251 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1671 | /* 3254 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1672 | /* 3260 */ GIR_RootConstrainSelectedInstOperands, |
| 1673 | /* 3261 */ // GIR_Coverage, 190, |
| 1674 | /* 3261 */ GIR_EraseRootFromParent_Done, |
| 1675 | /* 3262 */ // Label 133: @3262 |
| 1676 | /* 3262 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 134*/ GIMT_Encode4(3374), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 519 // |
| 1677 | /* 3269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1678 | /* 3273 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1679 | /* 3277 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1680 | /* 3281 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1681 | /* 3285 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1682 | /* 3289 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1683 | /* 3293 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1684 | /* 3297 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1685 | /* 3301 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1686 | /* 3305 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1687 | /* 3309 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1688 | /* 3314 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 1689 | /* 3318 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1690 | /* 3322 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1691 | /* 3326 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1692 | /* 3330 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1693 | /* 3335 */ // MIs[3] Operand 2 |
| 1694 | /* 3335 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1695 | /* 3346 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1696 | /* 3348 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLATB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1697 | /* 3348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB), |
| 1698 | /* 3351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1699 | /* 3353 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1700 | /* 3357 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1701 | /* 3361 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1702 | /* 3363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1703 | /* 3366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1704 | /* 3372 */ GIR_RootConstrainSelectedInstOperands, |
| 1705 | /* 3373 */ // GIR_Coverage, 519, |
| 1706 | /* 3373 */ GIR_EraseRootFromParent_Done, |
| 1707 | /* 3374 */ // Label 134: @3374 |
| 1708 | /* 3374 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 135*/ GIMT_Encode4(3486), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 189 // |
| 1709 | /* 3381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1710 | /* 3385 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1711 | /* 3389 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1712 | /* 3393 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1713 | /* 3397 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1714 | /* 3401 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1715 | /* 3405 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1716 | /* 3409 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1717 | /* 3413 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1718 | /* 3417 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1719 | /* 3422 */ // MIs[2] Operand 2 |
| 1720 | /* 3422 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1721 | /* 3433 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1722 | /* 3437 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1723 | /* 3441 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1724 | /* 3445 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1725 | /* 3449 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1726 | /* 3454 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1727 | /* 3458 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1728 | /* 3460 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1729 | /* 3460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 1730 | /* 3463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1731 | /* 3465 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1732 | /* 3469 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1733 | /* 3473 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1734 | /* 3475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1735 | /* 3478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1736 | /* 3484 */ GIR_RootConstrainSelectedInstOperands, |
| 1737 | /* 3485 */ // GIR_Coverage, 189, |
| 1738 | /* 3485 */ GIR_EraseRootFromParent_Done, |
| 1739 | /* 3486 */ // Label 135: @3486 |
| 1740 | /* 3486 */ GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(3776), |
| 1741 | /* 3491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1742 | /* 3495 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 137*/ GIMT_Encode4(3603), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 518 // |
| 1743 | /* 3502 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1744 | /* 3506 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1745 | /* 3510 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1746 | /* 3514 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1747 | /* 3518 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1748 | /* 3522 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1749 | /* 3526 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1750 | /* 3530 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1751 | /* 3534 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1752 | /* 3539 */ // MIs[2] Operand 2 |
| 1753 | /* 3539 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1754 | /* 3550 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1755 | /* 3554 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 1756 | /* 3558 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1757 | /* 3562 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 1758 | /* 3566 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1759 | /* 3571 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 1760 | /* 3575 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1761 | /* 3577 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1762 | /* 3577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 1763 | /* 3580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1764 | /* 3582 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1765 | /* 3586 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1766 | /* 3590 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1767 | /* 3592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1768 | /* 3595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1769 | /* 3601 */ GIR_RootConstrainSelectedInstOperands, |
| 1770 | /* 3602 */ // GIR_Coverage, 518, |
| 1771 | /* 3602 */ GIR_EraseRootFromParent_Done, |
| 1772 | /* 3603 */ // Label 137: @3603 |
| 1773 | /* 3603 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 138*/ GIMT_Encode4(3689), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6274 // |
| 1774 | /* 3610 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1775 | /* 3614 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1776 | /* 3618 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1777 | /* 3622 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1778 | /* 3626 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR), |
| 1779 | /* 3630 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1780 | /* 3634 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1781 | /* 3638 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1782 | /* 3643 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 1783 | /* 3647 */ // MIs[1] Operand 2 |
| 1784 | /* 3647 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1785 | /* 3658 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1786 | /* 3662 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1787 | /* 3664 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1788 | /* 3664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1789 | /* 3667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1790 | /* 3669 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 1791 | /* 3671 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1792 | /* 3675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1793 | /* 3678 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1794 | /* 3681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1795 | /* 3687 */ GIR_RootConstrainSelectedInstOperands, |
| 1796 | /* 3688 */ // GIR_Coverage, 6274, |
| 1797 | /* 3688 */ GIR_EraseRootFromParent_Done, |
| 1798 | /* 3689 */ // Label 138: @3689 |
| 1799 | /* 3689 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 139*/ GIMT_Encode4(3775), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2299 // |
| 1800 | /* 3696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1801 | /* 3700 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1802 | /* 3704 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1803 | /* 3708 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1804 | /* 3712 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1805 | /* 3716 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR), |
| 1806 | /* 3720 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1807 | /* 3724 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 1808 | /* 3728 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1809 | /* 3733 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 1810 | /* 3737 */ // MIs[1] Operand 2 |
| 1811 | /* 3737 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 1812 | /* 3748 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1813 | /* 3750 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] }) |
| 1814 | /* 3750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 1815 | /* 3753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1816 | /* 3755 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 1817 | /* 3757 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 1818 | /* 3761 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 1819 | /* 3764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1820 | /* 3767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1821 | /* 3773 */ GIR_RootConstrainSelectedInstOperands, |
| 1822 | /* 3774 */ // GIR_Coverage, 2299, |
| 1823 | /* 3774 */ GIR_EraseRootFromParent_Done, |
| 1824 | /* 3775 */ // Label 139: @3775 |
| 1825 | /* 3775 */ GIM_Reject, |
| 1826 | /* 3776 */ // Label 136: @3776 |
| 1827 | /* 3776 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 140*/ GIMT_Encode4(3891), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5972 // |
| 1828 | /* 3783 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1829 | /* 3787 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1830 | /* 3791 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1831 | /* 3795 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1832 | /* 3799 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1833 | /* 3803 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1834 | /* 3807 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1835 | /* 3811 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1836 | /* 3815 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1837 | /* 3820 */ // MIs[2] Operand 2 |
| 1838 | /* 3820 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1839 | /* 3831 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1840 | /* 3835 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1841 | /* 3839 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1842 | /* 3843 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1843 | /* 3848 */ // MIs[3] Operand 2 |
| 1844 | /* 3848 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1845 | /* 3859 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1846 | /* 3863 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1847 | /* 3865 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1848 | /* 3865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB), |
| 1849 | /* 3868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1850 | /* 3870 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1851 | /* 3874 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1852 | /* 3878 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1853 | /* 3880 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1854 | /* 3883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1855 | /* 3889 */ GIR_RootConstrainSelectedInstOperands, |
| 1856 | /* 3890 */ // GIR_Coverage, 5972, |
| 1857 | /* 3890 */ GIR_EraseRootFromParent_Done, |
| 1858 | /* 3891 */ // Label 140: @3891 |
| 1859 | /* 3891 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 141*/ GIMT_Encode4(4006), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6007 // |
| 1860 | /* 3898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1861 | /* 3902 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1862 | /* 3906 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1863 | /* 3910 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1864 | /* 3914 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1865 | /* 3918 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1866 | /* 3922 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1867 | /* 3926 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1868 | /* 3930 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1869 | /* 3935 */ // MIs[2] Operand 2 |
| 1870 | /* 3935 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1871 | /* 3946 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1872 | /* 3950 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1873 | /* 3954 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1874 | /* 3958 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1875 | /* 3963 */ // MIs[3] Operand 2 |
| 1876 | /* 3963 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1877 | /* 3974 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1878 | /* 3978 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1879 | /* 3980 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1880 | /* 3980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB), |
| 1881 | /* 3983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1882 | /* 3985 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1883 | /* 3989 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1884 | /* 3993 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 1885 | /* 3995 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1886 | /* 3998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1887 | /* 4004 */ GIR_RootConstrainSelectedInstOperands, |
| 1888 | /* 4005 */ // GIR_Coverage, 6007, |
| 1889 | /* 4005 */ GIR_EraseRootFromParent_Done, |
| 1890 | /* 4006 */ // Label 141: @4006 |
| 1891 | /* 4006 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 142*/ GIMT_Encode4(4121), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 188 // |
| 1892 | /* 4013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1893 | /* 4017 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 1894 | /* 4021 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1895 | /* 4025 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1896 | /* 4029 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1897 | /* 4033 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1898 | /* 4037 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1899 | /* 4041 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1900 | /* 4045 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1901 | /* 4049 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1902 | /* 4054 */ // MIs[2] Operand 2 |
| 1903 | /* 4054 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1904 | /* 4065 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1905 | /* 4069 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1906 | /* 4073 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1907 | /* 4077 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 1908 | /* 4082 */ // MIs[3] Operand 2 |
| 1909 | /* 4082 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1910 | /* 4093 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1911 | /* 4095 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 1912 | /* 4095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB), |
| 1913 | /* 4098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1914 | /* 4100 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1915 | /* 4104 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1916 | /* 4108 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1917 | /* 4110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1918 | /* 4113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1919 | /* 4119 */ GIR_RootConstrainSelectedInstOperands, |
| 1920 | /* 4120 */ // GIR_Coverage, 188, |
| 1921 | /* 4120 */ GIR_EraseRootFromParent_Done, |
| 1922 | /* 4121 */ // Label 142: @4121 |
| 1923 | /* 4121 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 143*/ GIMT_Encode4(4236), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 517 // |
| 1924 | /* 4128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1925 | /* 4132 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1926 | /* 4136 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 1927 | /* 4140 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1928 | /* 4144 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 1929 | /* 4148 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 1930 | /* 4152 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1931 | /* 4156 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1932 | /* 4160 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 1933 | /* 4164 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1934 | /* 4169 */ // MIs[2] Operand 2 |
| 1935 | /* 4169 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 1936 | /* 4180 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3] |
| 1937 | /* 4184 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 1938 | /* 4188 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 1939 | /* 4192 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 1940 | /* 4197 */ // MIs[3] Operand 2 |
| 1941 | /* 4197 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16), |
| 1942 | /* 4208 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 1943 | /* 4210 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 1944 | /* 4210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB), |
| 1945 | /* 4213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 1946 | /* 4215 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 1947 | /* 4219 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 1948 | /* 4223 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 1949 | /* 4225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 1950 | /* 4228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1951 | /* 4234 */ GIR_RootConstrainSelectedInstOperands, |
| 1952 | /* 4235 */ // GIR_Coverage, 517, |
| 1953 | /* 4235 */ GIR_EraseRootFromParent_Done, |
| 1954 | /* 4236 */ // Label 143: @4236 |
| 1955 | /* 4236 */ GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(4740), |
| 1956 | /* 4241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 1957 | /* 4245 */ GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(4492), |
| 1958 | /* 4250 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 1959 | /* 4254 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 146*/ GIMT_Encode4(4333), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3636 // |
| 1960 | /* 4261 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1961 | /* 4265 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 1962 | /* 4269 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1963 | /* 4273 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1964 | /* 4277 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1965 | /* 4281 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 1966 | /* 4285 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 1967 | /* 4289 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 1968 | /* 4294 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 1969 | /* 4299 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1970 | /* 4301 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 1971 | /* 4301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32), |
| 1972 | /* 4304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 1973 | /* 4306 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3 |
| 1974 | /* 4308 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 1975 | /* 4312 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 1976 | /* 4316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 1977 | /* 4319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1978 | /* 4325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 1979 | /* 4331 */ GIR_RootConstrainSelectedInstOperands, |
| 1980 | /* 4332 */ // GIR_Coverage, 3636, |
| 1981 | /* 4332 */ GIR_EraseRootFromParent_Done, |
| 1982 | /* 4333 */ // Label 146: @4333 |
| 1983 | /* 4333 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 147*/ GIMT_Encode4(4412), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3637 // |
| 1984 | /* 4340 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 1985 | /* 4344 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 1986 | /* 4348 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 1987 | /* 4352 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 1988 | /* 4356 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 1989 | /* 4360 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 1990 | /* 4364 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 1991 | /* 4368 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 1992 | /* 4373 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 1993 | /* 4378 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 1994 | /* 4380 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 1995 | /* 4380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16), |
| 1996 | /* 4383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 1997 | /* 4385 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3 |
| 1998 | /* 4387 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 1999 | /* 4391 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2000 | /* 4395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2001 | /* 4398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2002 | /* 4404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2003 | /* 4410 */ GIR_RootConstrainSelectedInstOperands, |
| 2004 | /* 4411 */ // GIR_Coverage, 3637, |
| 2005 | /* 4411 */ GIR_EraseRootFromParent_Done, |
| 2006 | /* 4412 */ // Label 147: @4412 |
| 2007 | /* 4412 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 148*/ GIMT_Encode4(4491), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3640 // |
| 2008 | /* 4419 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2009 | /* 4423 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2010 | /* 4427 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2011 | /* 4431 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2012 | /* 4435 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2013 | /* 4439 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2014 | /* 4443 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2015 | /* 4447 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2016 | /* 4452 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2017 | /* 4457 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2018 | /* 4459 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 2019 | /* 4459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8), |
| 2020 | /* 4462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2021 | /* 4464 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3 |
| 2022 | /* 4466 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2023 | /* 4470 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2024 | /* 4474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2025 | /* 4477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2026 | /* 4483 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2027 | /* 4489 */ GIR_RootConstrainSelectedInstOperands, |
| 2028 | /* 4490 */ // GIR_Coverage, 3640, |
| 2029 | /* 4490 */ GIR_EraseRootFromParent_Done, |
| 2030 | /* 4491 */ // Label 148: @4491 |
| 2031 | /* 4491 */ GIM_Reject, |
| 2032 | /* 4492 */ // Label 145: @4492 |
| 2033 | /* 4492 */ GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(4739), |
| 2034 | /* 4497 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2035 | /* 4501 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 150*/ GIMT_Encode4(4580), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6574 // |
| 2036 | /* 4508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2037 | /* 4512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2038 | /* 4516 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2039 | /* 4520 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2040 | /* 4524 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2041 | /* 4528 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2042 | /* 4532 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32, |
| 2043 | /* 4536 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2044 | /* 4541 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2045 | /* 4546 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2046 | /* 4548 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2))) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 2047 | /* 4548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32), |
| 2048 | /* 4551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2049 | /* 4553 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3 |
| 2050 | /* 4555 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2051 | /* 4559 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2052 | /* 4563 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2053 | /* 4566 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2054 | /* 4572 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2055 | /* 4578 */ GIR_RootConstrainSelectedInstOperands, |
| 2056 | /* 4579 */ // GIR_Coverage, 6574, |
| 2057 | /* 4579 */ GIR_EraseRootFromParent_Done, |
| 2058 | /* 4580 */ // Label 150: @4580 |
| 2059 | /* 4580 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 151*/ GIMT_Encode4(4659), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6575 // |
| 2060 | /* 4587 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2061 | /* 4591 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2062 | /* 4595 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2063 | /* 4599 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2064 | /* 4603 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2065 | /* 4607 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2066 | /* 4611 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16, |
| 2067 | /* 4615 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2068 | /* 4620 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2069 | /* 4625 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2070 | /* 4627 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2))) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 2071 | /* 4627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16), |
| 2072 | /* 4630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2073 | /* 4632 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3 |
| 2074 | /* 4634 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2075 | /* 4638 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2076 | /* 4642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2077 | /* 4645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2078 | /* 4651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2079 | /* 4657 */ GIR_RootConstrainSelectedInstOperands, |
| 2080 | /* 4658 */ // GIR_Coverage, 6575, |
| 2081 | /* 4658 */ GIR_EraseRootFromParent_Done, |
| 2082 | /* 4659 */ // Label 151: @4659 |
| 2083 | /* 4659 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 152*/ GIMT_Encode4(4738), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6578 // |
| 2084 | /* 4666 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2085 | /* 4670 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2086 | /* 4674 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2087 | /* 4678 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 2088 | /* 4682 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2089 | /* 4686 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2090 | /* 4690 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2091 | /* 4694 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2092 | /* 4699 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2093 | /* 4704 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 2094 | /* 4706 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2))) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 2095 | /* 4706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8), |
| 2096 | /* 4709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 2097 | /* 4711 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3 |
| 2098 | /* 4713 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2099 | /* 4717 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 2100 | /* 4721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2101 | /* 4724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2102 | /* 4730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2103 | /* 4736 */ GIR_RootConstrainSelectedInstOperands, |
| 2104 | /* 4737 */ // GIR_Coverage, 6578, |
| 2105 | /* 4737 */ GIR_EraseRootFromParent_Done, |
| 2106 | /* 4738 */ // Label 152: @4738 |
| 2107 | /* 4738 */ GIM_Reject, |
| 2108 | /* 4739 */ // Label 149: @4739 |
| 2109 | /* 4739 */ GIM_Reject, |
| 2110 | /* 4740 */ // Label 144: @4740 |
| 2111 | /* 4740 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 153*/ GIMT_Encode4(4796), GIMT_Encode2(GIFBS_IsARM), // Rule ID 71 // |
| 2112 | /* 4747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2113 | /* 4751 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2114 | /* 4755 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2115 | /* 4759 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2116 | /* 4763 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 2117 | /* 4767 */ // MIs[1] Operand 1 |
| 2118 | /* 4767 */ // No operand predicates |
| 2119 | /* 4767 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2120 | /* 4769 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2121 | /* 4769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDri), |
| 2122 | /* 4772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2123 | /* 4774 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2124 | /* 4776 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2125 | /* 4779 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2126 | /* 4782 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2127 | /* 4788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2128 | /* 4794 */ GIR_RootConstrainSelectedInstOperands, |
| 2129 | /* 4795 */ // GIR_Coverage, 71, |
| 2130 | /* 4795 */ GIR_EraseRootFromParent_Done, |
| 2131 | /* 4796 */ // Label 153: @4796 |
| 2132 | /* 4796 */ GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(4906), |
| 2133 | /* 4801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2134 | /* 4805 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2135 | /* 4809 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 155*/ GIMT_Encode4(4857), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 302 // |
| 2136 | /* 4816 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2137 | /* 4820 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2138 | /* 4824 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 2139 | /* 4828 */ // MIs[1] Operand 1 |
| 2140 | /* 4828 */ // No operand predicates |
| 2141 | /* 4828 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2142 | /* 4830 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm3) => (tADDi3:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm3) |
| 2143 | /* 4830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi3), |
| 2144 | /* 4833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2145 | /* 4835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 2146 | /* 4841 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 2147 | /* 4843 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm3 |
| 2148 | /* 4846 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2149 | /* 4849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2150 | /* 4855 */ GIR_RootConstrainSelectedInstOperands, |
| 2151 | /* 4856 */ // GIR_Coverage, 302, |
| 2152 | /* 4856 */ GIR_EraseRootFromParent_Done, |
| 2153 | /* 4857 */ // Label 155: @4857 |
| 2154 | /* 4857 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 156*/ GIMT_Encode4(4905), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 303 // |
| 2155 | /* 4864 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2156 | /* 4868 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2157 | /* 4872 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr), |
| 2158 | /* 4876 */ // MIs[1] Operand 1 |
| 2159 | /* 4876 */ // No operand predicates |
| 2160 | /* 4876 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2161 | /* 4878 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8) => (tADDi8:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm8) |
| 2162 | /* 4878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi8), |
| 2163 | /* 4881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 2164 | /* 4883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 2165 | /* 4889 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2166 | /* 4891 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8 |
| 2167 | /* 4894 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2168 | /* 4897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2169 | /* 4903 */ GIR_RootConstrainSelectedInstOperands, |
| 2170 | /* 4904 */ // GIR_Coverage, 303, |
| 2171 | /* 4904 */ GIR_EraseRootFromParent_Done, |
| 2172 | /* 4905 */ // Label 156: @4905 |
| 2173 | /* 4905 */ GIM_Reject, |
| 2174 | /* 4906 */ // Label 154: @4906 |
| 2175 | /* 4906 */ GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(5014), |
| 2176 | /* 4911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2177 | /* 4915 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 158*/ GIMT_Encode4(4967), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 406 // |
| 2178 | /* 4922 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2179 | /* 4926 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2180 | /* 4930 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2181 | /* 4934 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 2182 | /* 4938 */ // MIs[1] Operand 1 |
| 2183 | /* 4938 */ // No operand predicates |
| 2184 | /* 4938 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2185 | /* 4940 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2186 | /* 4940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri), |
| 2187 | /* 4943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2188 | /* 4945 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2189 | /* 4947 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2190 | /* 4950 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2191 | /* 4953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2192 | /* 4959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2193 | /* 4965 */ GIR_RootConstrainSelectedInstOperands, |
| 2194 | /* 4966 */ // GIR_Coverage, 406, |
| 2195 | /* 4966 */ GIR_EraseRootFromParent_Done, |
| 2196 | /* 4967 */ // Label 158: @4967 |
| 2197 | /* 4967 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 159*/ GIMT_Encode4(5013), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 407 // |
| 2198 | /* 4974 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2199 | /* 4978 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2200 | /* 4982 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2201 | /* 4986 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095), |
| 2202 | /* 4990 */ // MIs[1] Operand 1 |
| 2203 | /* 4990 */ // No operand predicates |
| 2204 | /* 4990 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2205 | /* 4992 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 2206 | /* 4992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri12), |
| 2207 | /* 4995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2208 | /* 4997 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2209 | /* 4999 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 2210 | /* 5002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2211 | /* 5005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2212 | /* 5011 */ GIR_RootConstrainSelectedInstOperands, |
| 2213 | /* 5012 */ // GIR_Coverage, 407, |
| 2214 | /* 5012 */ GIR_EraseRootFromParent_Done, |
| 2215 | /* 5013 */ // Label 159: @5013 |
| 2216 | /* 5013 */ GIM_Reject, |
| 2217 | /* 5014 */ // Label 157: @5014 |
| 2218 | /* 5014 */ GIM_Try, /*On fail goto*//*Label 160*/ GIMT_Encode4(5162), |
| 2219 | /* 5019 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2220 | /* 5023 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2221 | /* 5027 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 161*/ GIMT_Encode4(5094), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 170 // |
| 2222 | /* 5034 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2223 | /* 5038 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2224 | /* 5042 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2225 | /* 5046 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2226 | /* 5050 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2227 | /* 5055 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2228 | /* 5060 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2229 | /* 5062 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2230 | /* 5062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA), |
| 2231 | /* 5065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2232 | /* 5067 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2233 | /* 5071 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2234 | /* 5075 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2235 | /* 5077 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2236 | /* 5080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2237 | /* 5086 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2238 | /* 5092 */ GIR_RootConstrainSelectedInstOperands, |
| 2239 | /* 5093 */ // GIR_Coverage, 170, |
| 2240 | /* 5093 */ GIR_EraseRootFromParent_Done, |
| 2241 | /* 5094 */ // Label 161: @5094 |
| 2242 | /* 5094 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 162*/ GIMT_Encode4(5161), GIMT_Encode2(GIFBS_IsARM_NoV6), // Rule ID 171 // |
| 2243 | /* 5101 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2244 | /* 5105 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2245 | /* 5109 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2246 | /* 5113 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2247 | /* 5117 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2248 | /* 5122 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2249 | /* 5127 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2250 | /* 5129 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2251 | /* 5129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5), |
| 2252 | /* 5132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2253 | /* 5134 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2254 | /* 5138 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2255 | /* 5142 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2256 | /* 5144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2257 | /* 5147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2258 | /* 5153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2259 | /* 5159 */ GIR_RootConstrainSelectedInstOperands, |
| 2260 | /* 5160 */ // GIR_Coverage, 171, |
| 2261 | /* 5160 */ GIR_EraseRootFromParent_Done, |
| 2262 | /* 5161 */ // Label 162: @5161 |
| 2263 | /* 5161 */ GIM_Reject, |
| 2264 | /* 5162 */ // Label 160: @5162 |
| 2265 | /* 5162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 163*/ GIMT_Encode4(5231), GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), // Rule ID 502 // |
| 2266 | /* 5169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2267 | /* 5173 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2268 | /* 5177 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2269 | /* 5181 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2270 | /* 5185 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2271 | /* 5189 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2272 | /* 5194 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2273 | /* 5199 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2274 | /* 5203 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2275 | /* 5205 */ // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2276 | /* 5205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA), |
| 2277 | /* 5208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2278 | /* 5210 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2279 | /* 5214 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2280 | /* 5218 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2281 | /* 5220 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2282 | /* 5223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2283 | /* 5229 */ GIR_RootConstrainSelectedInstOperands, |
| 2284 | /* 5230 */ // GIR_Coverage, 502, |
| 2285 | /* 5230 */ GIR_EraseRootFromParent_Done, |
| 2286 | /* 5231 */ // Label 163: @5231 |
| 2287 | /* 5231 */ GIM_Try, /*On fail goto*//*Label 164*/ GIMT_Encode4(5369), |
| 2288 | /* 5236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2289 | /* 5240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2290 | /* 5244 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 165*/ GIMT_Encode4(5306), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6266 // |
| 2291 | /* 5251 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2292 | /* 5255 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2293 | /* 5259 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2294 | /* 5263 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2295 | /* 5268 */ // MIs[1] Operand 2 |
| 2296 | /* 5268 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2297 | /* 5279 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2298 | /* 5281 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2299 | /* 5281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB), |
| 2300 | /* 5284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2301 | /* 5286 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2302 | /* 5288 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2303 | /* 5292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2304 | /* 5295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2305 | /* 5298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2306 | /* 5304 */ GIR_RootConstrainSelectedInstOperands, |
| 2307 | /* 5305 */ // GIR_Coverage, 6266, |
| 2308 | /* 5305 */ GIR_EraseRootFromParent_Done, |
| 2309 | /* 5306 */ // Label 165: @5306 |
| 2310 | /* 5306 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 166*/ GIMT_Encode4(5368), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6267 // |
| 2311 | /* 5313 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2312 | /* 5317 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2313 | /* 5321 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2314 | /* 5325 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2315 | /* 5330 */ // MIs[1] Operand 2 |
| 2316 | /* 5330 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2317 | /* 5341 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2318 | /* 5343 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2319 | /* 5343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH), |
| 2320 | /* 5346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2321 | /* 5348 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2322 | /* 5350 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2323 | /* 5354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2324 | /* 5357 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2325 | /* 5360 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2326 | /* 5366 */ GIR_RootConstrainSelectedInstOperands, |
| 2327 | /* 5367 */ // GIR_Coverage, 6267, |
| 2328 | /* 5367 */ GIR_EraseRootFromParent_Done, |
| 2329 | /* 5368 */ // Label 166: @5368 |
| 2330 | /* 5368 */ GIM_Reject, |
| 2331 | /* 5369 */ // Label 164: @5369 |
| 2332 | /* 5369 */ GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(5507), |
| 2333 | /* 5374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2334 | /* 5378 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2335 | /* 5382 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 168*/ GIMT_Encode4(5444), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6304 // |
| 2336 | /* 5389 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2337 | /* 5393 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2338 | /* 5397 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2339 | /* 5401 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2340 | /* 5406 */ // MIs[1] Operand 2 |
| 2341 | /* 5406 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2342 | /* 5417 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2343 | /* 5419 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2344 | /* 5419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB), |
| 2345 | /* 5422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2346 | /* 5424 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2347 | /* 5426 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2348 | /* 5430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2349 | /* 5433 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2350 | /* 5436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2351 | /* 5442 */ GIR_RootConstrainSelectedInstOperands, |
| 2352 | /* 5443 */ // GIR_Coverage, 6304, |
| 2353 | /* 5443 */ GIR_EraseRootFromParent_Done, |
| 2354 | /* 5444 */ // Label 168: @5444 |
| 2355 | /* 5444 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 169*/ GIMT_Encode4(5506), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6305 // |
| 2356 | /* 5451 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2357 | /* 5455 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2358 | /* 5459 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2359 | /* 5463 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2360 | /* 5468 */ // MIs[1] Operand 2 |
| 2361 | /* 5468 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2362 | /* 5479 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2363 | /* 5481 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2364 | /* 5481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 2365 | /* 5484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2366 | /* 5486 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2367 | /* 5488 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2368 | /* 5492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2369 | /* 5495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2370 | /* 5498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2371 | /* 5504 */ GIR_RootConstrainSelectedInstOperands, |
| 2372 | /* 5505 */ // GIR_Coverage, 6305, |
| 2373 | /* 5505 */ GIR_EraseRootFromParent_Done, |
| 2374 | /* 5506 */ // Label 169: @5506 |
| 2375 | /* 5506 */ GIM_Reject, |
| 2376 | /* 5507 */ // Label 167: @5507 |
| 2377 | /* 5507 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 170*/ GIMT_Encode4(5576), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 179 // |
| 2378 | /* 5514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2379 | /* 5518 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2380 | /* 5522 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2381 | /* 5526 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2382 | /* 5530 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2383 | /* 5534 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2384 | /* 5539 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2385 | /* 5544 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2386 | /* 5548 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2387 | /* 5550 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 2388 | /* 5550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA), |
| 2389 | /* 5553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2390 | /* 5555 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2391 | /* 5559 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2392 | /* 5563 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2393 | /* 5565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2394 | /* 5568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2395 | /* 5574 */ GIR_RootConstrainSelectedInstOperands, |
| 2396 | /* 5575 */ // GIR_Coverage, 179, |
| 2397 | /* 5575 */ GIR_EraseRootFromParent_Done, |
| 2398 | /* 5576 */ // Label 170: @5576 |
| 2399 | /* 5576 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 171*/ GIMT_Encode4(5645), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 508 // |
| 2400 | /* 5583 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2401 | /* 5587 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2402 | /* 5591 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2403 | /* 5595 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2404 | /* 5599 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2405 | /* 5603 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2406 | /* 5608 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2407 | /* 5613 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2408 | /* 5617 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2409 | /* 5619 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2410 | /* 5619 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA), |
| 2411 | /* 5622 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2412 | /* 5624 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2413 | /* 5628 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2414 | /* 5632 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra |
| 2415 | /* 5634 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2416 | /* 5637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2417 | /* 5643 */ GIR_RootConstrainSelectedInstOperands, |
| 2418 | /* 5644 */ // GIR_Coverage, 508, |
| 2419 | /* 5644 */ GIR_EraseRootFromParent_Done, |
| 2420 | /* 5645 */ // Label 171: @5645 |
| 2421 | /* 5645 */ GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(5821), |
| 2422 | /* 5650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2423 | /* 5654 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2424 | /* 5658 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 173*/ GIMT_Encode4(5712), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3441 // |
| 2425 | /* 5665 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2426 | /* 5669 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2427 | /* 5673 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2428 | /* 5677 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2429 | /* 5682 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2430 | /* 5684 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec) |
| 2431 | /* 5684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc), |
| 2432 | /* 5687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2433 | /* 5689 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc |
| 2434 | /* 5691 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2435 | /* 5695 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2436 | /* 5698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2437 | /* 5704 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2438 | /* 5710 */ GIR_RootConstrainSelectedInstOperands, |
| 2439 | /* 5711 */ // GIR_Coverage, 3441, |
| 2440 | /* 5711 */ GIR_EraseRootFromParent_Done, |
| 2441 | /* 5712 */ // Label 173: @5712 |
| 2442 | /* 5712 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 174*/ GIMT_Encode4(5766), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3469 // |
| 2443 | /* 5719 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2444 | /* 5723 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2445 | /* 5727 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2446 | /* 5731 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2447 | /* 5736 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2448 | /* 5738 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec) |
| 2449 | /* 5738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc), |
| 2450 | /* 5741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2451 | /* 5743 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc |
| 2452 | /* 5745 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2453 | /* 5749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2454 | /* 5752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2455 | /* 5758 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2456 | /* 5764 */ GIR_RootConstrainSelectedInstOperands, |
| 2457 | /* 5765 */ // GIR_Coverage, 3469, |
| 2458 | /* 5765 */ GIR_EraseRootFromParent_Done, |
| 2459 | /* 5766 */ // Label 174: @5766 |
| 2460 | /* 5766 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 175*/ GIMT_Encode4(5820), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3479 // |
| 2461 | /* 5773 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2462 | /* 5777 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2463 | /* 5781 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2464 | /* 5785 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2465 | /* 5790 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2466 | /* 5792 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec) |
| 2467 | /* 5792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc), |
| 2468 | /* 5795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2469 | /* 5797 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc |
| 2470 | /* 5799 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2471 | /* 5803 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2472 | /* 5806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2473 | /* 5812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2474 | /* 5818 */ GIR_RootConstrainSelectedInstOperands, |
| 2475 | /* 5819 */ // GIR_Coverage, 3479, |
| 2476 | /* 5819 */ GIR_EraseRootFromParent_Done, |
| 2477 | /* 5820 */ // Label 175: @5820 |
| 2478 | /* 5820 */ GIM_Reject, |
| 2479 | /* 5821 */ // Label 172: @5821 |
| 2480 | /* 5821 */ GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(5969), |
| 2481 | /* 5826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2482 | /* 5830 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2483 | /* 5834 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 177*/ GIMT_Encode4(5901), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 5969 // |
| 2484 | /* 5841 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2485 | /* 5845 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2486 | /* 5849 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2487 | /* 5853 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2488 | /* 5857 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2489 | /* 5862 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2490 | /* 5867 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2491 | /* 5869 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2492 | /* 5869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA), |
| 2493 | /* 5872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2494 | /* 5874 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2495 | /* 5878 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2496 | /* 5882 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2497 | /* 5884 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2498 | /* 5887 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2499 | /* 5893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2500 | /* 5899 */ GIR_RootConstrainSelectedInstOperands, |
| 2501 | /* 5900 */ // GIR_Coverage, 5969, |
| 2502 | /* 5900 */ GIR_EraseRootFromParent_Done, |
| 2503 | /* 5901 */ // Label 177: @5901 |
| 2504 | /* 5901 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 178*/ GIMT_Encode4(5968), GIMT_Encode2(GIFBS_IsARM_NoV6), // Rule ID 5970 // |
| 2505 | /* 5908 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2506 | /* 5912 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2507 | /* 5916 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2508 | /* 5920 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2509 | /* 5924 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2510 | /* 5929 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2511 | /* 5934 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2512 | /* 5936 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 2513 | /* 5936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5), |
| 2514 | /* 5939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2515 | /* 5941 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2516 | /* 5945 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2517 | /* 5949 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2518 | /* 5951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2519 | /* 5954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2520 | /* 5960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2521 | /* 5966 */ GIR_RootConstrainSelectedInstOperands, |
| 2522 | /* 5967 */ // GIR_Coverage, 5970, |
| 2523 | /* 5967 */ GIR_EraseRootFromParent_Done, |
| 2524 | /* 5968 */ // Label 178: @5968 |
| 2525 | /* 5968 */ GIM_Reject, |
| 2526 | /* 5969 */ // Label 176: @5969 |
| 2527 | /* 5969 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 179*/ GIMT_Encode4(6038), GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), // Rule ID 6005 // |
| 2528 | /* 5976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2529 | /* 5980 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2530 | /* 5984 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2531 | /* 5988 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2532 | /* 5992 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2533 | /* 5996 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2534 | /* 6000 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2535 | /* 6005 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2536 | /* 6010 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2537 | /* 6012 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2538 | /* 6012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA), |
| 2539 | /* 6015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2540 | /* 6017 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2541 | /* 6021 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2542 | /* 6025 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2543 | /* 6027 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2544 | /* 6030 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2545 | /* 6036 */ GIR_RootConstrainSelectedInstOperands, |
| 2546 | /* 6037 */ // GIR_Coverage, 6005, |
| 2547 | /* 6037 */ GIR_EraseRootFromParent_Done, |
| 2548 | /* 6038 */ // Label 179: @6038 |
| 2549 | /* 6038 */ GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(6176), |
| 2550 | /* 6043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2551 | /* 6047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2552 | /* 6051 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 181*/ GIMT_Encode4(6113), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2197 // |
| 2553 | /* 6058 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2554 | /* 6062 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2555 | /* 6066 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2556 | /* 6070 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2557 | /* 6075 */ // MIs[1] Operand 2 |
| 2558 | /* 6075 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2559 | /* 6086 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2560 | /* 6088 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2561 | /* 6088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB), |
| 2562 | /* 6091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2563 | /* 6093 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2564 | /* 6095 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2565 | /* 6099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2566 | /* 6102 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2567 | /* 6105 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2568 | /* 6111 */ GIR_RootConstrainSelectedInstOperands, |
| 2569 | /* 6112 */ // GIR_Coverage, 2197, |
| 2570 | /* 6112 */ GIR_EraseRootFromParent_Done, |
| 2571 | /* 6113 */ // Label 181: @6113 |
| 2572 | /* 6113 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 182*/ GIMT_Encode4(6175), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2198 // |
| 2573 | /* 6120 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2574 | /* 6124 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2575 | /* 6128 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2576 | /* 6132 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2577 | /* 6137 */ // MIs[1] Operand 2 |
| 2578 | /* 6137 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2579 | /* 6148 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2580 | /* 6150 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2581 | /* 6150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH), |
| 2582 | /* 6153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2583 | /* 6155 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2584 | /* 6157 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2585 | /* 6161 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2586 | /* 6164 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2587 | /* 6167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2588 | /* 6173 */ GIR_RootConstrainSelectedInstOperands, |
| 2589 | /* 6174 */ // GIR_Coverage, 2198, |
| 2590 | /* 6174 */ GIR_EraseRootFromParent_Done, |
| 2591 | /* 6175 */ // Label 182: @6175 |
| 2592 | /* 6175 */ GIM_Reject, |
| 2593 | /* 6176 */ // Label 180: @6176 |
| 2594 | /* 6176 */ GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(6314), |
| 2595 | /* 6181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2596 | /* 6185 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2597 | /* 6189 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 184*/ GIMT_Encode4(6251), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2440 // |
| 2598 | /* 6196 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2599 | /* 6200 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2600 | /* 6204 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2601 | /* 6208 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2602 | /* 6213 */ // MIs[1] Operand 2 |
| 2603 | /* 6213 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 2604 | /* 6224 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2605 | /* 6226 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2606 | /* 6226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB), |
| 2607 | /* 6229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2608 | /* 6231 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2609 | /* 6233 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2610 | /* 6237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2611 | /* 6240 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2612 | /* 6243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2613 | /* 6249 */ GIR_RootConstrainSelectedInstOperands, |
| 2614 | /* 6250 */ // GIR_Coverage, 2440, |
| 2615 | /* 6250 */ GIR_EraseRootFromParent_Done, |
| 2616 | /* 6251 */ // Label 184: @6251 |
| 2617 | /* 6251 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 185*/ GIMT_Encode4(6313), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2441 // |
| 2618 | /* 6258 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2619 | /* 6262 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 2620 | /* 6266 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2621 | /* 6270 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2622 | /* 6275 */ // MIs[1] Operand 2 |
| 2623 | /* 6275 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 2624 | /* 6286 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2625 | /* 6288 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 2626 | /* 6288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH), |
| 2627 | /* 6291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2628 | /* 6293 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2629 | /* 6295 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2630 | /* 6299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2631 | /* 6302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2632 | /* 6305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2633 | /* 6311 */ GIR_RootConstrainSelectedInstOperands, |
| 2634 | /* 6312 */ // GIR_Coverage, 2441, |
| 2635 | /* 6312 */ GIR_EraseRootFromParent_Done, |
| 2636 | /* 6313 */ // Label 185: @6313 |
| 2637 | /* 6313 */ GIM_Reject, |
| 2638 | /* 6314 */ // Label 183: @6314 |
| 2639 | /* 6314 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 186*/ GIMT_Encode4(6383), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 5971 // |
| 2640 | /* 6321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2641 | /* 6325 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2642 | /* 6329 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2643 | /* 6333 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2644 | /* 6337 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2645 | /* 6341 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2646 | /* 6345 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2647 | /* 6350 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2648 | /* 6355 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2649 | /* 6357 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 2650 | /* 6357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA), |
| 2651 | /* 6360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2652 | /* 6362 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 2653 | /* 6366 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 2654 | /* 6370 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2655 | /* 6372 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2656 | /* 6375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2657 | /* 6381 */ GIR_RootConstrainSelectedInstOperands, |
| 2658 | /* 6382 */ // GIR_Coverage, 5971, |
| 2659 | /* 6382 */ GIR_EraseRootFromParent_Done, |
| 2660 | /* 6383 */ // Label 186: @6383 |
| 2661 | /* 6383 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 187*/ GIMT_Encode4(6452), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6006 // |
| 2662 | /* 6390 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2663 | /* 6394 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2664 | /* 6398 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2665 | /* 6402 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH), |
| 2666 | /* 6406 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2667 | /* 6410 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2668 | /* 6414 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2669 | /* 6419 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2670 | /* 6424 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2671 | /* 6426 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 2672 | /* 6426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA), |
| 2673 | /* 6429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2674 | /* 6431 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 2675 | /* 6435 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 2676 | /* 6439 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 2677 | /* 6441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2678 | /* 6444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2679 | /* 6450 */ GIR_RootConstrainSelectedInstOperands, |
| 2680 | /* 6451 */ // GIR_Coverage, 6006, |
| 2681 | /* 6451 */ GIR_EraseRootFromParent_Done, |
| 2682 | /* 6452 */ // Label 187: @6452 |
| 2683 | /* 6452 */ GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(6628), |
| 2684 | /* 6457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2685 | /* 6461 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 2686 | /* 6465 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 189*/ GIMT_Encode4(6519), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6550 // |
| 2687 | /* 6472 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2688 | /* 6476 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2689 | /* 6480 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2690 | /* 6484 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2691 | /* 6489 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2692 | /* 6491 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec)) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec) |
| 2693 | /* 6491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc), |
| 2694 | /* 6494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2695 | /* 6496 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc |
| 2696 | /* 6498 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2697 | /* 6502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2698 | /* 6505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2699 | /* 6511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2700 | /* 6517 */ GIR_RootConstrainSelectedInstOperands, |
| 2701 | /* 6518 */ // GIR_Coverage, 6550, |
| 2702 | /* 6518 */ GIR_EraseRootFromParent_Done, |
| 2703 | /* 6519 */ // Label 189: @6519 |
| 2704 | /* 6519 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 190*/ GIMT_Encode4(6573), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6564 // |
| 2705 | /* 6526 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2706 | /* 6530 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2707 | /* 6534 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 2708 | /* 6538 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2709 | /* 6543 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2710 | /* 6545 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec)) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec) |
| 2711 | /* 6545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc), |
| 2712 | /* 6548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2713 | /* 6550 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc |
| 2714 | /* 6552 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2715 | /* 6556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2716 | /* 6559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2717 | /* 6565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2718 | /* 6571 */ GIR_RootConstrainSelectedInstOperands, |
| 2719 | /* 6572 */ // GIR_Coverage, 6564, |
| 2720 | /* 6572 */ GIR_EraseRootFromParent_Done, |
| 2721 | /* 6573 */ // Label 190: @6573 |
| 2722 | /* 6573 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 191*/ GIMT_Encode4(6627), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6569 // |
| 2723 | /* 6580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2724 | /* 6584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD), |
| 2725 | /* 6588 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 2726 | /* 6592 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 2727 | /* 6597 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2728 | /* 6599 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec)) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec) |
| 2729 | /* 6599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc), |
| 2730 | /* 6602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 2731 | /* 6604 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc |
| 2732 | /* 6606 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec |
| 2733 | /* 6610 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2734 | /* 6613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2735 | /* 6619 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2736 | /* 6625 */ GIR_RootConstrainSelectedInstOperands, |
| 2737 | /* 6626 */ // GIR_Coverage, 6569, |
| 2738 | /* 6626 */ GIR_EraseRootFromParent_Done, |
| 2739 | /* 6627 */ // Label 191: @6627 |
| 2740 | /* 6627 */ GIM_Reject, |
| 2741 | /* 6628 */ // Label 188: @6628 |
| 2742 | /* 6628 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 192*/ GIMT_Encode4(6673), GIMT_Encode2(GIFBS_IsARM), // Rule ID 72 // |
| 2743 | /* 6635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2744 | /* 6639 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2745 | /* 6643 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 2746 | /* 6647 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 2747 | /* 6647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDrr), |
| 2748 | /* 6650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2749 | /* 6652 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2750 | /* 6654 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 2751 | /* 6656 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2752 | /* 6659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2753 | /* 6665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2754 | /* 6671 */ GIR_RootConstrainSelectedInstOperands, |
| 2755 | /* 6672 */ // GIR_Coverage, 72, |
| 2756 | /* 6672 */ GIR_EraseRootFromParent_Done, |
| 2757 | /* 6673 */ // Label 192: @6673 |
| 2758 | /* 6673 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 193*/ GIMT_Encode4(6718), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 304 // |
| 2759 | /* 6680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2760 | /* 6684 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2761 | /* 6688 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 2762 | /* 6692 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tADDrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 2763 | /* 6692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDrr), |
| 2764 | /* 6695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2765 | /* 6697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 2766 | /* 6703 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2767 | /* 6705 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 2768 | /* 6707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2769 | /* 6710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2770 | /* 6716 */ GIR_RootConstrainSelectedInstOperands, |
| 2771 | /* 6717 */ // GIR_Coverage, 304, |
| 2772 | /* 6717 */ GIR_EraseRootFromParent_Done, |
| 2773 | /* 6718 */ // Label 193: @6718 |
| 2774 | /* 6718 */ GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(6810), |
| 2775 | /* 6723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2776 | /* 6727 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 195*/ GIMT_Encode4(6768), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 408 // |
| 2777 | /* 6734 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2778 | /* 6738 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2779 | /* 6742 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 2780 | /* 6742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr), |
| 2781 | /* 6745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2782 | /* 6747 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 2783 | /* 6749 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 2784 | /* 6751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2785 | /* 6754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2786 | /* 6760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2787 | /* 6766 */ GIR_RootConstrainSelectedInstOperands, |
| 2788 | /* 6767 */ // GIR_Coverage, 408, |
| 2789 | /* 6767 */ GIR_EraseRootFromParent_Done, |
| 2790 | /* 6768 */ // Label 195: @6768 |
| 2791 | /* 6768 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 196*/ GIMT_Encode4(6809), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 5987 // |
| 2792 | /* 6775 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 2793 | /* 6779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 2794 | /* 6783 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 2795 | /* 6783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr), |
| 2796 | /* 6786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 2797 | /* 6788 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 2798 | /* 6790 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 2799 | /* 6792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2800 | /* 6795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2801 | /* 6801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2802 | /* 6807 */ GIR_RootConstrainSelectedInstOperands, |
| 2803 | /* 6808 */ // GIR_Coverage, 5987, |
| 2804 | /* 6808 */ GIR_EraseRootFromParent_Done, |
| 2805 | /* 6809 */ // Label 196: @6809 |
| 2806 | /* 6809 */ GIM_Reject, |
| 2807 | /* 6810 */ // Label 194: @6810 |
| 2808 | /* 6810 */ GIM_Reject, |
| 2809 | /* 6811 */ // Label 105: @6811 |
| 2810 | /* 6811 */ GIM_Reject, |
| 2811 | /* 6812 */ // Label 96: @6812 |
| 2812 | /* 6812 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 197*/ GIMT_Encode4(6857), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 882 // |
| 2813 | /* 6819 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 2814 | /* 6822 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 2815 | /* 6825 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2816 | /* 6829 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2817 | /* 6833 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2818 | /* 6837 */ // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 2819 | /* 6837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv1i64), |
| 2820 | /* 6840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2821 | /* 6842 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2822 | /* 6844 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 2823 | /* 6846 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2824 | /* 6849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2825 | /* 6855 */ GIR_RootConstrainSelectedInstOperands, |
| 2826 | /* 6856 */ // GIR_Coverage, 882, |
| 2827 | /* 6856 */ GIR_EraseRootFromParent_Done, |
| 2828 | /* 6857 */ // Label 197: @6857 |
| 2829 | /* 6857 */ GIM_Reject, |
| 2830 | /* 6858 */ // Label 97: @6858 |
| 2831 | /* 6858 */ GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(7291), |
| 2832 | /* 6863 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2833 | /* 6866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2834 | /* 6869 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2835 | /* 6873 */ GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(7066), |
| 2836 | /* 6878 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2837 | /* 6882 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 200*/ GIMT_Encode4(6943), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6191 // |
| 2838 | /* 6889 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2839 | /* 6893 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 2840 | /* 6897 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2841 | /* 6901 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2842 | /* 6905 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2843 | /* 6910 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2844 | /* 6915 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2845 | /* 6917 */ // (add:{ *:[v8i8] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2846 | /* 6917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8), |
| 2847 | /* 6920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2848 | /* 6922 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2849 | /* 6924 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2850 | /* 6928 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2851 | /* 6932 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2852 | /* 6935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2853 | /* 6941 */ GIR_RootConstrainSelectedInstOperands, |
| 2854 | /* 6942 */ // GIR_Coverage, 6191, |
| 2855 | /* 6942 */ GIR_EraseRootFromParent_Done, |
| 2856 | /* 6943 */ // Label 200: @6943 |
| 2857 | /* 6943 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 201*/ GIMT_Encode4(7004), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6197 // |
| 2858 | /* 6950 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2859 | /* 6954 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 2860 | /* 6958 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2861 | /* 6962 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2862 | /* 6966 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2863 | /* 6971 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2864 | /* 6976 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2865 | /* 6978 */ // (add:{ *:[v8i8] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2866 | /* 6978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8), |
| 2867 | /* 6981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2868 | /* 6983 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2869 | /* 6985 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2870 | /* 6989 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2871 | /* 6993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2872 | /* 6996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2873 | /* 7002 */ GIR_RootConstrainSelectedInstOperands, |
| 2874 | /* 7003 */ // GIR_Coverage, 6197, |
| 2875 | /* 7003 */ GIR_EraseRootFromParent_Done, |
| 2876 | /* 7004 */ // Label 201: @7004 |
| 2877 | /* 7004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 202*/ GIMT_Encode4(7065), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6079 // |
| 2878 | /* 7011 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2879 | /* 7015 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2880 | /* 7019 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2881 | /* 7023 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2882 | /* 7027 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2883 | /* 7032 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2884 | /* 7037 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2885 | /* 7039 */ // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2886 | /* 7039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8), |
| 2887 | /* 7042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2888 | /* 7044 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2889 | /* 7046 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2890 | /* 7050 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2891 | /* 7054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2892 | /* 7057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2893 | /* 7063 */ GIR_RootConstrainSelectedInstOperands, |
| 2894 | /* 7064 */ // GIR_Coverage, 6079, |
| 2895 | /* 7064 */ GIR_EraseRootFromParent_Done, |
| 2896 | /* 7065 */ // Label 202: @7065 |
| 2897 | /* 7065 */ GIM_Reject, |
| 2898 | /* 7066 */ // Label 199: @7066 |
| 2899 | /* 7066 */ GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(7290), |
| 2900 | /* 7071 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2901 | /* 7075 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 204*/ GIMT_Encode4(7136), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1341 // |
| 2902 | /* 7082 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2903 | /* 7086 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 2904 | /* 7090 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2905 | /* 7094 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2906 | /* 7098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2907 | /* 7103 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2908 | /* 7108 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2909 | /* 7110 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2910 | /* 7110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8), |
| 2911 | /* 7113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2912 | /* 7115 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2913 | /* 7117 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2914 | /* 7121 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2915 | /* 7125 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2916 | /* 7128 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2917 | /* 7134 */ GIR_RootConstrainSelectedInstOperands, |
| 2918 | /* 7135 */ // GIR_Coverage, 1341, |
| 2919 | /* 7135 */ GIR_EraseRootFromParent_Done, |
| 2920 | /* 7136 */ // Label 204: @7136 |
| 2921 | /* 7136 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 205*/ GIMT_Encode4(7197), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1347 // |
| 2922 | /* 7143 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2923 | /* 7147 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 2924 | /* 7151 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2925 | /* 7155 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2926 | /* 7159 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2927 | /* 7164 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2928 | /* 7169 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2929 | /* 7171 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2930 | /* 7171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8), |
| 2931 | /* 7174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2932 | /* 7176 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2933 | /* 7178 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2934 | /* 7182 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2935 | /* 7186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2936 | /* 7189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2937 | /* 7195 */ GIR_RootConstrainSelectedInstOperands, |
| 2938 | /* 7196 */ // GIR_Coverage, 1347, |
| 2939 | /* 7196 */ GIR_EraseRootFromParent_Done, |
| 2940 | /* 7197 */ // Label 205: @7197 |
| 2941 | /* 7197 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 206*/ GIMT_Encode4(7258), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1007 // |
| 2942 | /* 7204 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2943 | /* 7208 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2944 | /* 7212 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 2945 | /* 7216 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 2946 | /* 7220 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2947 | /* 7225 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2948 | /* 7230 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2949 | /* 7232 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2950 | /* 7232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8), |
| 2951 | /* 7235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2952 | /* 7237 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2953 | /* 7239 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 2954 | /* 7243 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 2955 | /* 7247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2956 | /* 7250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2957 | /* 7256 */ GIR_RootConstrainSelectedInstOperands, |
| 2958 | /* 7257 */ // GIR_Coverage, 1007, |
| 2959 | /* 7257 */ GIR_EraseRootFromParent_Done, |
| 2960 | /* 7258 */ // Label 206: @7258 |
| 2961 | /* 7258 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 207*/ GIMT_Encode4(7289), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 876 // |
| 2962 | /* 7265 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 2963 | /* 7269 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 2964 | /* 7269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i8), |
| 2965 | /* 7272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2966 | /* 7274 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 2967 | /* 7276 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 2968 | /* 7278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 2969 | /* 7281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 2970 | /* 7287 */ GIR_RootConstrainSelectedInstOperands, |
| 2971 | /* 7288 */ // GIR_Coverage, 876, |
| 2972 | /* 7288 */ GIR_EraseRootFromParent_Done, |
| 2973 | /* 7289 */ // Label 207: @7289 |
| 2974 | /* 7289 */ GIM_Reject, |
| 2975 | /* 7290 */ // Label 203: @7290 |
| 2976 | /* 7290 */ GIM_Reject, |
| 2977 | /* 7291 */ // Label 198: @7291 |
| 2978 | /* 7291 */ GIM_Reject, |
| 2979 | /* 7292 */ // Label 98: @7292 |
| 2980 | /* 7292 */ GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(7791), |
| 2981 | /* 7297 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2982 | /* 7300 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2983 | /* 7303 */ GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(7730), |
| 2984 | /* 7308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2985 | /* 7312 */ GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(7505), |
| 2986 | /* 7317 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2987 | /* 7321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 211*/ GIMT_Encode4(7382), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6194 // |
| 2988 | /* 7328 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2989 | /* 7332 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 2990 | /* 7336 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 2991 | /* 7340 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 2992 | /* 7344 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2993 | /* 7349 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 2994 | /* 7354 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2995 | /* 7356 */ // (add:{ *:[v16i8] } (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 2996 | /* 7356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8), |
| 2997 | /* 7359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 2998 | /* 7361 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2999 | /* 7363 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3000 | /* 7367 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3001 | /* 7371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3002 | /* 7374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3003 | /* 7380 */ GIR_RootConstrainSelectedInstOperands, |
| 3004 | /* 7381 */ // GIR_Coverage, 6194, |
| 3005 | /* 7381 */ GIR_EraseRootFromParent_Done, |
| 3006 | /* 7382 */ // Label 211: @7382 |
| 3007 | /* 7382 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 212*/ GIMT_Encode4(7443), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6200 // |
| 3008 | /* 7389 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3009 | /* 7393 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3010 | /* 7397 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3011 | /* 7401 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3012 | /* 7405 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3013 | /* 7410 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3014 | /* 7415 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3015 | /* 7417 */ // (add:{ *:[v16i8] } (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3016 | /* 7417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8), |
| 3017 | /* 7420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3018 | /* 7422 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3019 | /* 7424 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3020 | /* 7428 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3021 | /* 7432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3022 | /* 7435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3023 | /* 7441 */ GIR_RootConstrainSelectedInstOperands, |
| 3024 | /* 7442 */ // GIR_Coverage, 6200, |
| 3025 | /* 7442 */ GIR_EraseRootFromParent_Done, |
| 3026 | /* 7443 */ // Label 212: @7443 |
| 3027 | /* 7443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 213*/ GIMT_Encode4(7504), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6082 // |
| 3028 | /* 7450 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3029 | /* 7454 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3030 | /* 7458 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3031 | /* 7462 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3032 | /* 7466 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3033 | /* 7471 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3034 | /* 7476 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3035 | /* 7478 */ // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3036 | /* 7478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8), |
| 3037 | /* 7481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3038 | /* 7483 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3039 | /* 7485 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3040 | /* 7489 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3041 | /* 7493 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3042 | /* 7496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3043 | /* 7502 */ GIR_RootConstrainSelectedInstOperands, |
| 3044 | /* 7503 */ // GIR_Coverage, 6082, |
| 3045 | /* 7503 */ GIR_EraseRootFromParent_Done, |
| 3046 | /* 7504 */ // Label 213: @7504 |
| 3047 | /* 7504 */ GIM_Reject, |
| 3048 | /* 7505 */ // Label 210: @7505 |
| 3049 | /* 7505 */ GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(7729), |
| 3050 | /* 7510 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3051 | /* 7514 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 215*/ GIMT_Encode4(7575), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1344 // |
| 3052 | /* 7521 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3053 | /* 7525 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3054 | /* 7529 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3055 | /* 7533 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3056 | /* 7537 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3057 | /* 7542 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3058 | /* 7547 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3059 | /* 7549 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3060 | /* 7549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8), |
| 3061 | /* 7552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3062 | /* 7554 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3063 | /* 7556 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3064 | /* 7560 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3065 | /* 7564 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3066 | /* 7567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3067 | /* 7573 */ GIR_RootConstrainSelectedInstOperands, |
| 3068 | /* 7574 */ // GIR_Coverage, 1344, |
| 3069 | /* 7574 */ GIR_EraseRootFromParent_Done, |
| 3070 | /* 7575 */ // Label 215: @7575 |
| 3071 | /* 7575 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 216*/ GIMT_Encode4(7636), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1350 // |
| 3072 | /* 7582 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3073 | /* 7586 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3074 | /* 7590 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3075 | /* 7594 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3076 | /* 7598 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3077 | /* 7603 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3078 | /* 7608 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3079 | /* 7610 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3080 | /* 7610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8), |
| 3081 | /* 7613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3082 | /* 7615 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3083 | /* 7617 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3084 | /* 7621 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3085 | /* 7625 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3086 | /* 7628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3087 | /* 7634 */ GIR_RootConstrainSelectedInstOperands, |
| 3088 | /* 7635 */ // GIR_Coverage, 1350, |
| 3089 | /* 7635 */ GIR_EraseRootFromParent_Done, |
| 3090 | /* 7636 */ // Label 216: @7636 |
| 3091 | /* 7636 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 217*/ GIMT_Encode4(7697), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1010 // |
| 3092 | /* 7643 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3093 | /* 7647 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3094 | /* 7651 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 3095 | /* 7655 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 3096 | /* 7659 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3097 | /* 7664 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3098 | /* 7669 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3099 | /* 7671 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3100 | /* 7671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8), |
| 3101 | /* 7674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3102 | /* 7676 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3103 | /* 7678 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3104 | /* 7682 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3105 | /* 7686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3106 | /* 7689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3107 | /* 7695 */ GIR_RootConstrainSelectedInstOperands, |
| 3108 | /* 7696 */ // GIR_Coverage, 1010, |
| 3109 | /* 7696 */ GIR_EraseRootFromParent_Done, |
| 3110 | /* 7697 */ // Label 217: @7697 |
| 3111 | /* 7697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 218*/ GIMT_Encode4(7728), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 879 // |
| 3112 | /* 7704 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3113 | /* 7708 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 3114 | /* 7708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv16i8), |
| 3115 | /* 7711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3116 | /* 7713 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3117 | /* 7715 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3118 | /* 7717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3119 | /* 7720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3120 | /* 7726 */ GIR_RootConstrainSelectedInstOperands, |
| 3121 | /* 7727 */ // GIR_Coverage, 879, |
| 3122 | /* 7727 */ GIR_EraseRootFromParent_Done, |
| 3123 | /* 7728 */ // Label 218: @7728 |
| 3124 | /* 7728 */ GIM_Reject, |
| 3125 | /* 7729 */ // Label 214: @7729 |
| 3126 | /* 7729 */ GIM_Reject, |
| 3127 | /* 7730 */ // Label 209: @7730 |
| 3128 | /* 7730 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 219*/ GIMT_Encode4(7790), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3882 // |
| 3129 | /* 7737 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3130 | /* 7741 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3131 | /* 7745 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3132 | /* 7749 */ // (add:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 3133 | /* 7749 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3134 | /* 7752 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3135 | /* 7756 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 3136 | /* 7761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi8), |
| 3137 | /* 7764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 3138 | /* 7766 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 3139 | /* 7768 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 3140 | /* 7770 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3141 | /* 7773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3142 | /* 7779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3143 | /* 7785 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3144 | /* 7788 */ GIR_RootConstrainSelectedInstOperands, |
| 3145 | /* 7789 */ // GIR_Coverage, 3882, |
| 3146 | /* 7789 */ GIR_EraseRootFromParent_Done, |
| 3147 | /* 7790 */ // Label 219: @7790 |
| 3148 | /* 7790 */ GIM_Reject, |
| 3149 | /* 7791 */ // Label 208: @7791 |
| 3150 | /* 7791 */ GIM_Reject, |
| 3151 | /* 7792 */ // Label 99: @7792 |
| 3152 | /* 7792 */ GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(8225), |
| 3153 | /* 7797 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3154 | /* 7800 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3155 | /* 7803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3156 | /* 7807 */ GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(8000), |
| 3157 | /* 7812 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3158 | /* 7816 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 222*/ GIMT_Encode4(7877), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6192 // |
| 3159 | /* 7823 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3160 | /* 7827 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3161 | /* 7831 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3162 | /* 7835 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3163 | /* 7839 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3164 | /* 7844 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3165 | /* 7849 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3166 | /* 7851 */ // (add:{ *:[v4i16] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3167 | /* 7851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16), |
| 3168 | /* 7854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3169 | /* 7856 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3170 | /* 7858 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3171 | /* 7862 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3172 | /* 7866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3173 | /* 7869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3174 | /* 7875 */ GIR_RootConstrainSelectedInstOperands, |
| 3175 | /* 7876 */ // GIR_Coverage, 6192, |
| 3176 | /* 7876 */ GIR_EraseRootFromParent_Done, |
| 3177 | /* 7877 */ // Label 222: @7877 |
| 3178 | /* 7877 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 223*/ GIMT_Encode4(7938), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6198 // |
| 3179 | /* 7884 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3180 | /* 7888 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3181 | /* 7892 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3182 | /* 7896 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3183 | /* 7900 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3184 | /* 7905 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3185 | /* 7910 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3186 | /* 7912 */ // (add:{ *:[v4i16] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3187 | /* 7912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16), |
| 3188 | /* 7915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3189 | /* 7917 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3190 | /* 7919 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3191 | /* 7923 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3192 | /* 7927 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3193 | /* 7930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3194 | /* 7936 */ GIR_RootConstrainSelectedInstOperands, |
| 3195 | /* 7937 */ // GIR_Coverage, 6198, |
| 3196 | /* 7937 */ GIR_EraseRootFromParent_Done, |
| 3197 | /* 7938 */ // Label 223: @7938 |
| 3198 | /* 7938 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 224*/ GIMT_Encode4(7999), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6080 // |
| 3199 | /* 7945 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3200 | /* 7949 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3201 | /* 7953 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3202 | /* 7957 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3203 | /* 7961 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3204 | /* 7966 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3205 | /* 7971 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3206 | /* 7973 */ // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3207 | /* 7973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16), |
| 3208 | /* 7976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3209 | /* 7978 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3210 | /* 7980 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3211 | /* 7984 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3212 | /* 7988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3213 | /* 7991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3214 | /* 7997 */ GIR_RootConstrainSelectedInstOperands, |
| 3215 | /* 7998 */ // GIR_Coverage, 6080, |
| 3216 | /* 7998 */ GIR_EraseRootFromParent_Done, |
| 3217 | /* 7999 */ // Label 224: @7999 |
| 3218 | /* 7999 */ GIM_Reject, |
| 3219 | /* 8000 */ // Label 221: @8000 |
| 3220 | /* 8000 */ GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(8224), |
| 3221 | /* 8005 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3222 | /* 8009 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 226*/ GIMT_Encode4(8070), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1342 // |
| 3223 | /* 8016 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3224 | /* 8020 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3225 | /* 8024 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3226 | /* 8028 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3227 | /* 8032 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3228 | /* 8037 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3229 | /* 8042 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3230 | /* 8044 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3231 | /* 8044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16), |
| 3232 | /* 8047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3233 | /* 8049 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3234 | /* 8051 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3235 | /* 8055 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3236 | /* 8059 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3237 | /* 8062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3238 | /* 8068 */ GIR_RootConstrainSelectedInstOperands, |
| 3239 | /* 8069 */ // GIR_Coverage, 1342, |
| 3240 | /* 8069 */ GIR_EraseRootFromParent_Done, |
| 3241 | /* 8070 */ // Label 226: @8070 |
| 3242 | /* 8070 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 227*/ GIMT_Encode4(8131), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1348 // |
| 3243 | /* 8077 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3244 | /* 8081 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3245 | /* 8085 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3246 | /* 8089 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3247 | /* 8093 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3248 | /* 8098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3249 | /* 8103 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3250 | /* 8105 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3251 | /* 8105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16), |
| 3252 | /* 8108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3253 | /* 8110 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3254 | /* 8112 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3255 | /* 8116 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3256 | /* 8120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3257 | /* 8123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3258 | /* 8129 */ GIR_RootConstrainSelectedInstOperands, |
| 3259 | /* 8130 */ // GIR_Coverage, 1348, |
| 3260 | /* 8130 */ GIR_EraseRootFromParent_Done, |
| 3261 | /* 8131 */ // Label 227: @8131 |
| 3262 | /* 8131 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 228*/ GIMT_Encode4(8192), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1008 // |
| 3263 | /* 8138 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3264 | /* 8142 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3265 | /* 8146 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3266 | /* 8150 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 3267 | /* 8154 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3268 | /* 8159 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3269 | /* 8164 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3270 | /* 8166 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3271 | /* 8166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16), |
| 3272 | /* 8169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3273 | /* 8171 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3274 | /* 8173 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3275 | /* 8177 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3276 | /* 8181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3277 | /* 8184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3278 | /* 8190 */ GIR_RootConstrainSelectedInstOperands, |
| 3279 | /* 8191 */ // GIR_Coverage, 1008, |
| 3280 | /* 8191 */ GIR_EraseRootFromParent_Done, |
| 3281 | /* 8192 */ // Label 228: @8192 |
| 3282 | /* 8192 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 229*/ GIMT_Encode4(8223), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 877 // |
| 3283 | /* 8199 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3284 | /* 8203 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3285 | /* 8203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i16), |
| 3286 | /* 8206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3287 | /* 8208 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3288 | /* 8210 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3289 | /* 8212 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3290 | /* 8215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3291 | /* 8221 */ GIR_RootConstrainSelectedInstOperands, |
| 3292 | /* 8222 */ // GIR_Coverage, 877, |
| 3293 | /* 8222 */ GIR_EraseRootFromParent_Done, |
| 3294 | /* 8223 */ // Label 229: @8223 |
| 3295 | /* 8223 */ GIM_Reject, |
| 3296 | /* 8224 */ // Label 225: @8224 |
| 3297 | /* 8224 */ GIM_Reject, |
| 3298 | /* 8225 */ // Label 220: @8225 |
| 3299 | /* 8225 */ GIM_Reject, |
| 3300 | /* 8226 */ // Label 100: @8226 |
| 3301 | /* 8226 */ GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(9660), |
| 3302 | /* 8231 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3303 | /* 8234 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3304 | /* 8237 */ GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(9599), |
| 3305 | /* 8242 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3306 | /* 8246 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 232*/ GIMT_Encode4(8313), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 894 // |
| 3307 | /* 8253 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3308 | /* 8257 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3309 | /* 8261 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3310 | /* 8265 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3311 | /* 8270 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3312 | /* 8274 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3313 | /* 8278 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3314 | /* 8282 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3315 | /* 8287 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3316 | /* 8289 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3317 | /* 8289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 3318 | /* 8292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3319 | /* 8294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3320 | /* 8298 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3321 | /* 8302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3322 | /* 8305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3323 | /* 8311 */ GIR_RootConstrainSelectedInstOperands, |
| 3324 | /* 8312 */ // GIR_Coverage, 894, |
| 3325 | /* 8312 */ GIR_EraseRootFromParent_Done, |
| 3326 | /* 8313 */ // Label 232: @8313 |
| 3327 | /* 8313 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 233*/ GIMT_Encode4(8380), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 893 // |
| 3328 | /* 8320 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3329 | /* 8324 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3330 | /* 8328 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3331 | /* 8332 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3332 | /* 8337 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3333 | /* 8341 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3334 | /* 8345 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3335 | /* 8349 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3336 | /* 8354 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3337 | /* 8356 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3338 | /* 8356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 3339 | /* 8359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3340 | /* 8361 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3341 | /* 8365 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3342 | /* 8369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3343 | /* 8372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3344 | /* 8378 */ GIR_RootConstrainSelectedInstOperands, |
| 3345 | /* 8379 */ // GIR_Coverage, 893, |
| 3346 | /* 8379 */ GIR_EraseRootFromParent_Done, |
| 3347 | /* 8380 */ // Label 233: @8380 |
| 3348 | /* 8380 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 234*/ GIMT_Encode4(8447), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 888 // |
| 3349 | /* 8387 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3350 | /* 8391 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3351 | /* 8395 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3352 | /* 8399 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3353 | /* 8404 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3354 | /* 8408 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3355 | /* 8412 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3356 | /* 8416 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3357 | /* 8421 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3358 | /* 8423 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3359 | /* 8423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv8i16), |
| 3360 | /* 8426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3361 | /* 8428 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3362 | /* 8432 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3363 | /* 8436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3364 | /* 8439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3365 | /* 8445 */ GIR_RootConstrainSelectedInstOperands, |
| 3366 | /* 8446 */ // GIR_Coverage, 888, |
| 3367 | /* 8446 */ GIR_EraseRootFromParent_Done, |
| 3368 | /* 8447 */ // Label 234: @8447 |
| 3369 | /* 8447 */ GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(8603), |
| 3370 | /* 8452 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3371 | /* 8456 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 236*/ GIMT_Encode4(8529), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6203 // |
| 3372 | /* 8463 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3373 | /* 8467 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3374 | /* 8471 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3375 | /* 8475 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3376 | /* 8479 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3377 | /* 8483 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3378 | /* 8487 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3379 | /* 8491 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3380 | /* 8496 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3381 | /* 8501 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3382 | /* 8503 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3383 | /* 8503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16), |
| 3384 | /* 8506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3385 | /* 8508 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3386 | /* 8510 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3387 | /* 8514 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3388 | /* 8518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3389 | /* 8521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3390 | /* 8527 */ GIR_RootConstrainSelectedInstOperands, |
| 3391 | /* 8528 */ // GIR_Coverage, 6203, |
| 3392 | /* 8528 */ GIR_EraseRootFromParent_Done, |
| 3393 | /* 8529 */ // Label 236: @8529 |
| 3394 | /* 8529 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 237*/ GIMT_Encode4(8602), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6206 // |
| 3395 | /* 8536 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3396 | /* 8540 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3397 | /* 8544 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3398 | /* 8548 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3399 | /* 8552 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3400 | /* 8556 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3401 | /* 8560 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3402 | /* 8564 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3403 | /* 8569 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3404 | /* 8574 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3405 | /* 8576 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3406 | /* 8576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16), |
| 3407 | /* 8579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3408 | /* 8581 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3409 | /* 8583 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3410 | /* 8587 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3411 | /* 8591 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3412 | /* 8594 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3413 | /* 8600 */ GIR_RootConstrainSelectedInstOperands, |
| 3414 | /* 8601 */ // GIR_Coverage, 6206, |
| 3415 | /* 8601 */ GIR_EraseRootFromParent_Done, |
| 3416 | /* 8602 */ // Label 237: @8602 |
| 3417 | /* 8602 */ GIM_Reject, |
| 3418 | /* 8603 */ // Label 235: @8603 |
| 3419 | /* 8603 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 238*/ GIMT_Encode4(8670), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 892 // |
| 3420 | /* 8610 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3421 | /* 8614 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3422 | /* 8618 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3423 | /* 8622 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3424 | /* 8627 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3425 | /* 8631 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3426 | /* 8635 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3427 | /* 8639 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3428 | /* 8644 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3429 | /* 8646 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3430 | /* 8646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 3431 | /* 8649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3432 | /* 8651 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3433 | /* 8655 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3434 | /* 8659 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3435 | /* 8662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3436 | /* 8668 */ GIR_RootConstrainSelectedInstOperands, |
| 3437 | /* 8669 */ // GIR_Coverage, 892, |
| 3438 | /* 8669 */ GIR_EraseRootFromParent_Done, |
| 3439 | /* 8670 */ // Label 238: @8670 |
| 3440 | /* 8670 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 239*/ GIMT_Encode4(8737), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 891 // |
| 3441 | /* 8677 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3442 | /* 8681 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3443 | /* 8685 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3444 | /* 8689 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3445 | /* 8694 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3446 | /* 8698 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3447 | /* 8702 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3448 | /* 8706 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3449 | /* 8711 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3450 | /* 8713 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3451 | /* 8713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16), |
| 3452 | /* 8716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3453 | /* 8718 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3454 | /* 8722 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3455 | /* 8726 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3456 | /* 8729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3457 | /* 8735 */ GIR_RootConstrainSelectedInstOperands, |
| 3458 | /* 8736 */ // GIR_Coverage, 891, |
| 3459 | /* 8736 */ GIR_EraseRootFromParent_Done, |
| 3460 | /* 8737 */ // Label 239: @8737 |
| 3461 | /* 8737 */ GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(8893), |
| 3462 | /* 8742 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3463 | /* 8746 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 241*/ GIMT_Encode4(8819), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1353 // |
| 3464 | /* 8753 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3465 | /* 8757 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3466 | /* 8761 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3467 | /* 8765 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3468 | /* 8769 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3469 | /* 8773 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3470 | /* 8777 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3471 | /* 8781 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3472 | /* 8786 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3473 | /* 8791 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3474 | /* 8793 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3475 | /* 8793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16), |
| 3476 | /* 8796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3477 | /* 8798 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3478 | /* 8800 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3479 | /* 8804 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3480 | /* 8808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3481 | /* 8811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3482 | /* 8817 */ GIR_RootConstrainSelectedInstOperands, |
| 3483 | /* 8818 */ // GIR_Coverage, 1353, |
| 3484 | /* 8818 */ GIR_EraseRootFromParent_Done, |
| 3485 | /* 8819 */ // Label 241: @8819 |
| 3486 | /* 8819 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 242*/ GIMT_Encode4(8892), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1356 // |
| 3487 | /* 8826 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3488 | /* 8830 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3489 | /* 8834 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3490 | /* 8838 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 3491 | /* 8842 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3492 | /* 8846 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3493 | /* 8850 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8, |
| 3494 | /* 8854 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3495 | /* 8859 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3496 | /* 8864 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3497 | /* 8866 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3498 | /* 8866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16), |
| 3499 | /* 8869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3500 | /* 8871 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3501 | /* 8873 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 3502 | /* 8877 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 3503 | /* 8881 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3504 | /* 8884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3505 | /* 8890 */ GIR_RootConstrainSelectedInstOperands, |
| 3506 | /* 8891 */ // GIR_Coverage, 1356, |
| 3507 | /* 8891 */ GIR_EraseRootFromParent_Done, |
| 3508 | /* 8892 */ // Label 242: @8892 |
| 3509 | /* 8892 */ GIM_Reject, |
| 3510 | /* 8893 */ // Label 240: @8893 |
| 3511 | /* 8893 */ GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(9230), |
| 3512 | /* 8898 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3513 | /* 8902 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 244*/ GIMT_Encode4(8963), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6195 // |
| 3514 | /* 8909 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3515 | /* 8913 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3516 | /* 8917 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3517 | /* 8921 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3518 | /* 8925 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3519 | /* 8930 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3520 | /* 8935 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3521 | /* 8937 */ // (add:{ *:[v8i16] } (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3522 | /* 8937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16), |
| 3523 | /* 8940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3524 | /* 8942 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3525 | /* 8944 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3526 | /* 8948 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3527 | /* 8952 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3528 | /* 8955 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3529 | /* 8961 */ GIR_RootConstrainSelectedInstOperands, |
| 3530 | /* 8962 */ // GIR_Coverage, 6195, |
| 3531 | /* 8962 */ GIR_EraseRootFromParent_Done, |
| 3532 | /* 8963 */ // Label 244: @8963 |
| 3533 | /* 8963 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 245*/ GIMT_Encode4(9024), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6201 // |
| 3534 | /* 8970 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3535 | /* 8974 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3536 | /* 8978 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3537 | /* 8982 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3538 | /* 8986 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3539 | /* 8991 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3540 | /* 8996 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3541 | /* 8998 */ // (add:{ *:[v8i16] } (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3542 | /* 8998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16), |
| 3543 | /* 9001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3544 | /* 9003 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3545 | /* 9005 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3546 | /* 9009 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3547 | /* 9013 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3548 | /* 9016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3549 | /* 9022 */ GIR_RootConstrainSelectedInstOperands, |
| 3550 | /* 9023 */ // GIR_Coverage, 6201, |
| 3551 | /* 9023 */ GIR_EraseRootFromParent_Done, |
| 3552 | /* 9024 */ // Label 245: @9024 |
| 3553 | /* 9024 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 246*/ GIMT_Encode4(9085), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6083 // |
| 3554 | /* 9031 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3555 | /* 9035 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3556 | /* 9039 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3557 | /* 9043 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3558 | /* 9047 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3559 | /* 9052 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3560 | /* 9057 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3561 | /* 9059 */ // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3562 | /* 9059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16), |
| 3563 | /* 9062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3564 | /* 9064 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3565 | /* 9066 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3566 | /* 9070 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3567 | /* 9074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3568 | /* 9077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3569 | /* 9083 */ GIR_RootConstrainSelectedInstOperands, |
| 3570 | /* 9084 */ // GIR_Coverage, 6083, |
| 3571 | /* 9084 */ GIR_EraseRootFromParent_Done, |
| 3572 | /* 9085 */ // Label 246: @9085 |
| 3573 | /* 9085 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 247*/ GIMT_Encode4(9133), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6056 // |
| 3574 | /* 9092 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3575 | /* 9096 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3576 | /* 9100 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3577 | /* 9104 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3578 | /* 9109 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3579 | /* 9111 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3580 | /* 9111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 3581 | /* 9114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3582 | /* 9116 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3583 | /* 9118 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3584 | /* 9122 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3585 | /* 9125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3586 | /* 9131 */ GIR_RootConstrainSelectedInstOperands, |
| 3587 | /* 9132 */ // GIR_Coverage, 6056, |
| 3588 | /* 9132 */ GIR_EraseRootFromParent_Done, |
| 3589 | /* 9133 */ // Label 247: @9133 |
| 3590 | /* 9133 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 248*/ GIMT_Encode4(9181), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6052 // |
| 3591 | /* 9140 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3592 | /* 9144 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3593 | /* 9148 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3594 | /* 9152 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3595 | /* 9157 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3596 | /* 9159 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3597 | /* 9159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16), |
| 3598 | /* 9162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3599 | /* 9164 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3600 | /* 9166 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3601 | /* 9170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3602 | /* 9173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3603 | /* 9179 */ GIR_RootConstrainSelectedInstOperands, |
| 3604 | /* 9180 */ // GIR_Coverage, 6052, |
| 3605 | /* 9180 */ GIR_EraseRootFromParent_Done, |
| 3606 | /* 9181 */ // Label 248: @9181 |
| 3607 | /* 9181 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 249*/ GIMT_Encode4(9229), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6055 // |
| 3608 | /* 9188 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3609 | /* 9192 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3610 | /* 9196 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3611 | /* 9200 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3612 | /* 9205 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3613 | /* 9207 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3614 | /* 9207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 3615 | /* 9210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3616 | /* 9212 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 3617 | /* 9214 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3618 | /* 9218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3619 | /* 9221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3620 | /* 9227 */ GIR_RootConstrainSelectedInstOperands, |
| 3621 | /* 9228 */ // GIR_Coverage, 6055, |
| 3622 | /* 9228 */ GIR_EraseRootFromParent_Done, |
| 3623 | /* 9229 */ // Label 249: @9229 |
| 3624 | /* 9229 */ GIM_Reject, |
| 3625 | /* 9230 */ // Label 243: @9230 |
| 3626 | /* 9230 */ GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(9598), |
| 3627 | /* 9235 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3628 | /* 9239 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 251*/ GIMT_Encode4(9300), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1345 // |
| 3629 | /* 9246 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3630 | /* 9250 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3631 | /* 9254 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3632 | /* 9258 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3633 | /* 9262 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3634 | /* 9267 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3635 | /* 9272 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3636 | /* 9274 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3637 | /* 9274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16), |
| 3638 | /* 9277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3639 | /* 9279 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3640 | /* 9281 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3641 | /* 9285 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3642 | /* 9289 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3643 | /* 9292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3644 | /* 9298 */ GIR_RootConstrainSelectedInstOperands, |
| 3645 | /* 9299 */ // GIR_Coverage, 1345, |
| 3646 | /* 9299 */ GIR_EraseRootFromParent_Done, |
| 3647 | /* 9300 */ // Label 251: @9300 |
| 3648 | /* 9300 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 252*/ GIMT_Encode4(9361), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1351 // |
| 3649 | /* 9307 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3650 | /* 9311 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3651 | /* 9315 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3652 | /* 9319 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3653 | /* 9323 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3654 | /* 9328 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3655 | /* 9333 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3656 | /* 9335 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3657 | /* 9335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16), |
| 3658 | /* 9338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3659 | /* 9340 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3660 | /* 9342 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3661 | /* 9346 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3662 | /* 9350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3663 | /* 9353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3664 | /* 9359 */ GIR_RootConstrainSelectedInstOperands, |
| 3665 | /* 9360 */ // GIR_Coverage, 1351, |
| 3666 | /* 9360 */ GIR_EraseRootFromParent_Done, |
| 3667 | /* 9361 */ // Label 252: @9361 |
| 3668 | /* 9361 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 253*/ GIMT_Encode4(9422), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1011 // |
| 3669 | /* 9368 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3670 | /* 9372 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3671 | /* 9376 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 3672 | /* 9380 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 3673 | /* 9384 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3674 | /* 9389 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3675 | /* 9394 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3676 | /* 9396 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3677 | /* 9396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16), |
| 3678 | /* 9399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3679 | /* 9401 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3680 | /* 9403 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3681 | /* 9407 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3682 | /* 9411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3683 | /* 9414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3684 | /* 9420 */ GIR_RootConstrainSelectedInstOperands, |
| 3685 | /* 9421 */ // GIR_Coverage, 1011, |
| 3686 | /* 9421 */ GIR_EraseRootFromParent_Done, |
| 3687 | /* 9422 */ // Label 253: @9422 |
| 3688 | /* 9422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 254*/ GIMT_Encode4(9470), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 907 // |
| 3689 | /* 9429 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3690 | /* 9433 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3691 | /* 9437 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3692 | /* 9441 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3693 | /* 9446 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3694 | /* 9448 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3695 | /* 9448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 3696 | /* 9451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3697 | /* 9453 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3698 | /* 9455 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3699 | /* 9459 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3700 | /* 9462 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3701 | /* 9468 */ GIR_RootConstrainSelectedInstOperands, |
| 3702 | /* 9469 */ // GIR_Coverage, 907, |
| 3703 | /* 9469 */ GIR_EraseRootFromParent_Done, |
| 3704 | /* 9470 */ // Label 254: @9470 |
| 3705 | /* 9470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 255*/ GIMT_Encode4(9518), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 903 // |
| 3706 | /* 9477 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3707 | /* 9481 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3708 | /* 9485 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3709 | /* 9489 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3710 | /* 9494 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3711 | /* 9496 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3712 | /* 9496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16), |
| 3713 | /* 9499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3714 | /* 9501 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3715 | /* 9503 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3716 | /* 9507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3717 | /* 9510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3718 | /* 9516 */ GIR_RootConstrainSelectedInstOperands, |
| 3719 | /* 9517 */ // GIR_Coverage, 903, |
| 3720 | /* 9517 */ GIR_EraseRootFromParent_Done, |
| 3721 | /* 9518 */ // Label 255: @9518 |
| 3722 | /* 9518 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 256*/ GIMT_Encode4(9566), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 906 // |
| 3723 | /* 9525 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3724 | /* 9529 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3725 | /* 9533 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 3726 | /* 9537 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3727 | /* 9542 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3728 | /* 9544 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 3729 | /* 9544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16), |
| 3730 | /* 9547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3731 | /* 9549 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3732 | /* 9551 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 3733 | /* 9555 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3734 | /* 9558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3735 | /* 9564 */ GIR_RootConstrainSelectedInstOperands, |
| 3736 | /* 9565 */ // GIR_Coverage, 906, |
| 3737 | /* 9565 */ GIR_EraseRootFromParent_Done, |
| 3738 | /* 9566 */ // Label 256: @9566 |
| 3739 | /* 9566 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 257*/ GIMT_Encode4(9597), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 880 // |
| 3740 | /* 9573 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3741 | /* 9577 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 3742 | /* 9577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i16), |
| 3743 | /* 9580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3744 | /* 9582 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3745 | /* 9584 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3746 | /* 9586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3747 | /* 9589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3748 | /* 9595 */ GIR_RootConstrainSelectedInstOperands, |
| 3749 | /* 9596 */ // GIR_Coverage, 880, |
| 3750 | /* 9596 */ GIR_EraseRootFromParent_Done, |
| 3751 | /* 9597 */ // Label 257: @9597 |
| 3752 | /* 9597 */ GIM_Reject, |
| 3753 | /* 9598 */ // Label 250: @9598 |
| 3754 | /* 9598 */ GIM_Reject, |
| 3755 | /* 9599 */ // Label 231: @9599 |
| 3756 | /* 9599 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 258*/ GIMT_Encode4(9659), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3886 // |
| 3757 | /* 9606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3758 | /* 9610 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3759 | /* 9614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 3760 | /* 9618 */ // (add:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 3761 | /* 9618 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 3762 | /* 9621 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3763 | /* 9625 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 3764 | /* 9630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi16), |
| 3765 | /* 9633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 3766 | /* 9635 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 3767 | /* 9637 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 3768 | /* 9639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3769 | /* 9642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3770 | /* 9648 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3771 | /* 9654 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 3772 | /* 9657 */ GIR_RootConstrainSelectedInstOperands, |
| 3773 | /* 9658 */ // GIR_Coverage, 3886, |
| 3774 | /* 9658 */ GIR_EraseRootFromParent_Done, |
| 3775 | /* 9659 */ // Label 258: @9659 |
| 3776 | /* 9659 */ GIM_Reject, |
| 3777 | /* 9660 */ // Label 230: @9660 |
| 3778 | /* 9660 */ GIM_Reject, |
| 3779 | /* 9661 */ // Label 101: @9661 |
| 3780 | /* 9661 */ GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(10094), |
| 3781 | /* 9666 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3782 | /* 9669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3783 | /* 9672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3784 | /* 9676 */ GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(9869), |
| 3785 | /* 9681 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3786 | /* 9685 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 261*/ GIMT_Encode4(9746), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6193 // |
| 3787 | /* 9692 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3788 | /* 9696 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3789 | /* 9700 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3790 | /* 9704 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3791 | /* 9708 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3792 | /* 9713 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3793 | /* 9718 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3794 | /* 9720 */ // (add:{ *:[v2i32] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3795 | /* 9720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32), |
| 3796 | /* 9723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3797 | /* 9725 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3798 | /* 9727 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3799 | /* 9731 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3800 | /* 9735 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3801 | /* 9738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3802 | /* 9744 */ GIR_RootConstrainSelectedInstOperands, |
| 3803 | /* 9745 */ // GIR_Coverage, 6193, |
| 3804 | /* 9745 */ GIR_EraseRootFromParent_Done, |
| 3805 | /* 9746 */ // Label 261: @9746 |
| 3806 | /* 9746 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 262*/ GIMT_Encode4(9807), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6199 // |
| 3807 | /* 9753 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3808 | /* 9757 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3809 | /* 9761 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3810 | /* 9765 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3811 | /* 9769 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3812 | /* 9774 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3813 | /* 9779 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3814 | /* 9781 */ // (add:{ *:[v2i32] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3815 | /* 9781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32), |
| 3816 | /* 9784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3817 | /* 9786 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3818 | /* 9788 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3819 | /* 9792 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3820 | /* 9796 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3821 | /* 9799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3822 | /* 9805 */ GIR_RootConstrainSelectedInstOperands, |
| 3823 | /* 9806 */ // GIR_Coverage, 6199, |
| 3824 | /* 9806 */ GIR_EraseRootFromParent_Done, |
| 3825 | /* 9807 */ // Label 262: @9807 |
| 3826 | /* 9807 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 263*/ GIMT_Encode4(9868), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6081 // |
| 3827 | /* 9814 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3828 | /* 9818 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3829 | /* 9822 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3830 | /* 9826 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3831 | /* 9830 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3832 | /* 9835 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3833 | /* 9840 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3834 | /* 9842 */ // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3835 | /* 9842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32), |
| 3836 | /* 9845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3837 | /* 9847 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3838 | /* 9849 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3839 | /* 9853 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3840 | /* 9857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3841 | /* 9860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3842 | /* 9866 */ GIR_RootConstrainSelectedInstOperands, |
| 3843 | /* 9867 */ // GIR_Coverage, 6081, |
| 3844 | /* 9867 */ GIR_EraseRootFromParent_Done, |
| 3845 | /* 9868 */ // Label 263: @9868 |
| 3846 | /* 9868 */ GIM_Reject, |
| 3847 | /* 9869 */ // Label 260: @9869 |
| 3848 | /* 9869 */ GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(10093), |
| 3849 | /* 9874 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3850 | /* 9878 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 265*/ GIMT_Encode4(9939), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1343 // |
| 3851 | /* 9885 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3852 | /* 9889 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 3853 | /* 9893 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3854 | /* 9897 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3855 | /* 9901 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3856 | /* 9906 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3857 | /* 9911 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3858 | /* 9913 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3859 | /* 9913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32), |
| 3860 | /* 9916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3861 | /* 9918 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3862 | /* 9920 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3863 | /* 9924 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3864 | /* 9928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3865 | /* 9931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3866 | /* 9937 */ GIR_RootConstrainSelectedInstOperands, |
| 3867 | /* 9938 */ // GIR_Coverage, 1343, |
| 3868 | /* 9938 */ GIR_EraseRootFromParent_Done, |
| 3869 | /* 9939 */ // Label 265: @9939 |
| 3870 | /* 9939 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 266*/ GIMT_Encode4(10000), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1349 // |
| 3871 | /* 9946 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3872 | /* 9950 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 3873 | /* 9954 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3874 | /* 9958 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3875 | /* 9962 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3876 | /* 9967 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3877 | /* 9972 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3878 | /* 9974 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3879 | /* 9974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32), |
| 3880 | /* 9977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3881 | /* 9979 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3882 | /* 9981 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3883 | /* 9985 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3884 | /* 9989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3885 | /* 9992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3886 | /* 9998 */ GIR_RootConstrainSelectedInstOperands, |
| 3887 | /* 9999 */ // GIR_Coverage, 1349, |
| 3888 | /* 9999 */ GIR_EraseRootFromParent_Done, |
| 3889 | /* 10000 */ // Label 266: @10000 |
| 3890 | /* 10000 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 267*/ GIMT_Encode4(10061), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1009 // |
| 3891 | /* 10007 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3892 | /* 10011 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3893 | /* 10015 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 3894 | /* 10019 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 3895 | /* 10023 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3896 | /* 10028 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3897 | /* 10033 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3898 | /* 10035 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3899 | /* 10035 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32), |
| 3900 | /* 10038 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3901 | /* 10040 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3902 | /* 10042 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3903 | /* 10046 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 3904 | /* 10050 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3905 | /* 10053 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3906 | /* 10059 */ GIR_RootConstrainSelectedInstOperands, |
| 3907 | /* 10060 */ // GIR_Coverage, 1009, |
| 3908 | /* 10060 */ GIR_EraseRootFromParent_Done, |
| 3909 | /* 10061 */ // Label 267: @10061 |
| 3910 | /* 10061 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 268*/ GIMT_Encode4(10092), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 878 // |
| 3911 | /* 10068 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3912 | /* 10072 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 3913 | /* 10072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i32), |
| 3914 | /* 10075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3915 | /* 10077 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 3916 | /* 10079 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 3917 | /* 10081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3918 | /* 10084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3919 | /* 10090 */ GIR_RootConstrainSelectedInstOperands, |
| 3920 | /* 10091 */ // GIR_Coverage, 878, |
| 3921 | /* 10091 */ GIR_EraseRootFromParent_Done, |
| 3922 | /* 10092 */ // Label 268: @10092 |
| 3923 | /* 10092 */ GIM_Reject, |
| 3924 | /* 10093 */ // Label 264: @10093 |
| 3925 | /* 10093 */ GIM_Reject, |
| 3926 | /* 10094 */ // Label 259: @10094 |
| 3927 | /* 10094 */ GIM_Reject, |
| 3928 | /* 10095 */ // Label 102: @10095 |
| 3929 | /* 10095 */ GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(11529), |
| 3930 | /* 10100 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 3931 | /* 10103 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 3932 | /* 10106 */ GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(11468), |
| 3933 | /* 10111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3934 | /* 10115 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 271*/ GIMT_Encode4(10182), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 898 // |
| 3935 | /* 10122 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3936 | /* 10126 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3937 | /* 10130 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3938 | /* 10134 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3939 | /* 10139 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3940 | /* 10143 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3941 | /* 10147 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3942 | /* 10151 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3943 | /* 10156 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3944 | /* 10158 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3945 | /* 10158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 3946 | /* 10161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3947 | /* 10163 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3948 | /* 10167 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3949 | /* 10171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3950 | /* 10174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3951 | /* 10180 */ GIR_RootConstrainSelectedInstOperands, |
| 3952 | /* 10181 */ // GIR_Coverage, 898, |
| 3953 | /* 10181 */ GIR_EraseRootFromParent_Done, |
| 3954 | /* 10182 */ // Label 271: @10182 |
| 3955 | /* 10182 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 272*/ GIMT_Encode4(10249), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 897 // |
| 3956 | /* 10189 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3957 | /* 10193 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 3958 | /* 10197 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3959 | /* 10201 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3960 | /* 10206 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3961 | /* 10210 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 3962 | /* 10214 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3963 | /* 10218 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3964 | /* 10223 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3965 | /* 10225 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3966 | /* 10225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 3967 | /* 10228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3968 | /* 10230 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3969 | /* 10234 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3970 | /* 10238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3971 | /* 10241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3972 | /* 10247 */ GIR_RootConstrainSelectedInstOperands, |
| 3973 | /* 10248 */ // GIR_Coverage, 897, |
| 3974 | /* 10248 */ GIR_EraseRootFromParent_Done, |
| 3975 | /* 10249 */ // Label 272: @10249 |
| 3976 | /* 10249 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 273*/ GIMT_Encode4(10316), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 889 // |
| 3977 | /* 10256 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3978 | /* 10260 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3979 | /* 10264 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3980 | /* 10268 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3981 | /* 10273 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 3982 | /* 10277 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 3983 | /* 10281 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 3984 | /* 10285 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 3985 | /* 10290 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 3986 | /* 10292 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 3987 | /* 10292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv4i32), |
| 3988 | /* 10295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 3989 | /* 10297 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 3990 | /* 10301 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 3991 | /* 10305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 3992 | /* 10308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 3993 | /* 10314 */ GIR_RootConstrainSelectedInstOperands, |
| 3994 | /* 10315 */ // GIR_Coverage, 889, |
| 3995 | /* 10315 */ GIR_EraseRootFromParent_Done, |
| 3996 | /* 10316 */ // Label 273: @10316 |
| 3997 | /* 10316 */ GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(10472), |
| 3998 | /* 10321 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 3999 | /* 10325 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 275*/ GIMT_Encode4(10398), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6204 // |
| 4000 | /* 10332 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4001 | /* 10336 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4002 | /* 10340 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4003 | /* 10344 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4004 | /* 10348 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4005 | /* 10352 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4006 | /* 10356 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4007 | /* 10360 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4008 | /* 10365 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4009 | /* 10370 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4010 | /* 10372 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4011 | /* 10372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32), |
| 4012 | /* 10375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4013 | /* 10377 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4014 | /* 10379 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4015 | /* 10383 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4016 | /* 10387 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4017 | /* 10390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4018 | /* 10396 */ GIR_RootConstrainSelectedInstOperands, |
| 4019 | /* 10397 */ // GIR_Coverage, 6204, |
| 4020 | /* 10397 */ GIR_EraseRootFromParent_Done, |
| 4021 | /* 10398 */ // Label 275: @10398 |
| 4022 | /* 10398 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 276*/ GIMT_Encode4(10471), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6207 // |
| 4023 | /* 10405 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4024 | /* 10409 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4025 | /* 10413 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4026 | /* 10417 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4027 | /* 10421 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4028 | /* 10425 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4029 | /* 10429 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4030 | /* 10433 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4031 | /* 10438 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4032 | /* 10443 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4033 | /* 10445 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4034 | /* 10445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32), |
| 4035 | /* 10448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4036 | /* 10450 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4037 | /* 10452 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4038 | /* 10456 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4039 | /* 10460 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4040 | /* 10463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4041 | /* 10469 */ GIR_RootConstrainSelectedInstOperands, |
| 4042 | /* 10470 */ // GIR_Coverage, 6207, |
| 4043 | /* 10470 */ GIR_EraseRootFromParent_Done, |
| 4044 | /* 10471 */ // Label 276: @10471 |
| 4045 | /* 10471 */ GIM_Reject, |
| 4046 | /* 10472 */ // Label 274: @10472 |
| 4047 | /* 10472 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 277*/ GIMT_Encode4(10539), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 896 // |
| 4048 | /* 10479 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4049 | /* 10483 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4050 | /* 10487 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4051 | /* 10491 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4052 | /* 10496 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4053 | /* 10500 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4054 | /* 10504 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4055 | /* 10508 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4056 | /* 10513 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4057 | /* 10515 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4058 | /* 10515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 4059 | /* 10518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4060 | /* 10520 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4061 | /* 10524 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4062 | /* 10528 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4063 | /* 10531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4064 | /* 10537 */ GIR_RootConstrainSelectedInstOperands, |
| 4065 | /* 10538 */ // GIR_Coverage, 896, |
| 4066 | /* 10538 */ GIR_EraseRootFromParent_Done, |
| 4067 | /* 10539 */ // Label 277: @10539 |
| 4068 | /* 10539 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 278*/ GIMT_Encode4(10606), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 895 // |
| 4069 | /* 10546 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4070 | /* 10550 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4071 | /* 10554 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4072 | /* 10558 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4073 | /* 10563 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4074 | /* 10567 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4075 | /* 10571 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4076 | /* 10575 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4077 | /* 10580 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4078 | /* 10582 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4079 | /* 10582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32), |
| 4080 | /* 10585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4081 | /* 10587 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4082 | /* 10591 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4083 | /* 10595 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4084 | /* 10598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4085 | /* 10604 */ GIR_RootConstrainSelectedInstOperands, |
| 4086 | /* 10605 */ // GIR_Coverage, 895, |
| 4087 | /* 10605 */ GIR_EraseRootFromParent_Done, |
| 4088 | /* 10606 */ // Label 278: @10606 |
| 4089 | /* 10606 */ GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(10762), |
| 4090 | /* 10611 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4091 | /* 10615 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 280*/ GIMT_Encode4(10688), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1354 // |
| 4092 | /* 10622 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4093 | /* 10626 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4094 | /* 10630 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4095 | /* 10634 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4096 | /* 10638 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4097 | /* 10642 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4098 | /* 10646 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4099 | /* 10650 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4100 | /* 10655 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4101 | /* 10660 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4102 | /* 10662 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4103 | /* 10662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32), |
| 4104 | /* 10665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4105 | /* 10667 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4106 | /* 10669 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4107 | /* 10673 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4108 | /* 10677 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4109 | /* 10680 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4110 | /* 10686 */ GIR_RootConstrainSelectedInstOperands, |
| 4111 | /* 10687 */ // GIR_Coverage, 1354, |
| 4112 | /* 10687 */ GIR_EraseRootFromParent_Done, |
| 4113 | /* 10688 */ // Label 280: @10688 |
| 4114 | /* 10688 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 281*/ GIMT_Encode4(10761), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1357 // |
| 4115 | /* 10695 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4116 | /* 10699 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4117 | /* 10703 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4118 | /* 10707 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4119 | /* 10711 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4120 | /* 10715 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4121 | /* 10719 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4122 | /* 10723 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4123 | /* 10728 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4124 | /* 10733 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4125 | /* 10735 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4126 | /* 10735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32), |
| 4127 | /* 10738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4128 | /* 10740 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4129 | /* 10742 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4130 | /* 10746 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4131 | /* 10750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4132 | /* 10753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4133 | /* 10759 */ GIR_RootConstrainSelectedInstOperands, |
| 4134 | /* 10760 */ // GIR_Coverage, 1357, |
| 4135 | /* 10760 */ GIR_EraseRootFromParent_Done, |
| 4136 | /* 10761 */ // Label 281: @10761 |
| 4137 | /* 10761 */ GIM_Reject, |
| 4138 | /* 10762 */ // Label 279: @10762 |
| 4139 | /* 10762 */ GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(11099), |
| 4140 | /* 10767 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4141 | /* 10771 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 283*/ GIMT_Encode4(10832), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6196 // |
| 4142 | /* 10778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4143 | /* 10782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4144 | /* 10786 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4145 | /* 10790 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4146 | /* 10794 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4147 | /* 10799 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4148 | /* 10804 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4149 | /* 10806 */ // (add:{ *:[v4i32] } (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4150 | /* 10806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32), |
| 4151 | /* 10809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4152 | /* 10811 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4153 | /* 10813 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4154 | /* 10817 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4155 | /* 10821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4156 | /* 10824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4157 | /* 10830 */ GIR_RootConstrainSelectedInstOperands, |
| 4158 | /* 10831 */ // GIR_Coverage, 6196, |
| 4159 | /* 10831 */ GIR_EraseRootFromParent_Done, |
| 4160 | /* 10832 */ // Label 283: @10832 |
| 4161 | /* 10832 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 284*/ GIMT_Encode4(10893), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6202 // |
| 4162 | /* 10839 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4163 | /* 10843 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4164 | /* 10847 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4165 | /* 10851 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4166 | /* 10855 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4167 | /* 10860 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4168 | /* 10865 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4169 | /* 10867 */ // (add:{ *:[v4i32] } (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4170 | /* 10867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32), |
| 4171 | /* 10870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4172 | /* 10872 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4173 | /* 10874 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4174 | /* 10878 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4175 | /* 10882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4176 | /* 10885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4177 | /* 10891 */ GIR_RootConstrainSelectedInstOperands, |
| 4178 | /* 10892 */ // GIR_Coverage, 6202, |
| 4179 | /* 10892 */ GIR_EraseRootFromParent_Done, |
| 4180 | /* 10893 */ // Label 284: @10893 |
| 4181 | /* 10893 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 285*/ GIMT_Encode4(10954), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6084 // |
| 4182 | /* 10900 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4183 | /* 10904 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4184 | /* 10908 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4185 | /* 10912 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4186 | /* 10916 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4187 | /* 10921 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4188 | /* 10926 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4189 | /* 10928 */ // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4190 | /* 10928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32), |
| 4191 | /* 10931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4192 | /* 10933 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4193 | /* 10935 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4194 | /* 10939 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4195 | /* 10943 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4196 | /* 10946 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4197 | /* 10952 */ GIR_RootConstrainSelectedInstOperands, |
| 4198 | /* 10953 */ // GIR_Coverage, 6084, |
| 4199 | /* 10953 */ GIR_EraseRootFromParent_Done, |
| 4200 | /* 10954 */ // Label 285: @10954 |
| 4201 | /* 10954 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 286*/ GIMT_Encode4(11002), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6058 // |
| 4202 | /* 10961 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4203 | /* 10965 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4204 | /* 10969 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4205 | /* 10973 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4206 | /* 10978 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4207 | /* 10980 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4208 | /* 10980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 4209 | /* 10983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4210 | /* 10985 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 4211 | /* 10987 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4212 | /* 10991 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4213 | /* 10994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4214 | /* 11000 */ GIR_RootConstrainSelectedInstOperands, |
| 4215 | /* 11001 */ // GIR_Coverage, 6058, |
| 4216 | /* 11001 */ GIR_EraseRootFromParent_Done, |
| 4217 | /* 11002 */ // Label 286: @11002 |
| 4218 | /* 11002 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 287*/ GIMT_Encode4(11050), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6053 // |
| 4219 | /* 11009 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4220 | /* 11013 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4221 | /* 11017 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4222 | /* 11021 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4223 | /* 11026 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4224 | /* 11028 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4225 | /* 11028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32), |
| 4226 | /* 11031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4227 | /* 11033 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 4228 | /* 11035 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4229 | /* 11039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4230 | /* 11042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4231 | /* 11048 */ GIR_RootConstrainSelectedInstOperands, |
| 4232 | /* 11049 */ // GIR_Coverage, 6053, |
| 4233 | /* 11049 */ GIR_EraseRootFromParent_Done, |
| 4234 | /* 11050 */ // Label 287: @11050 |
| 4235 | /* 11050 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 288*/ GIMT_Encode4(11098), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6057 // |
| 4236 | /* 11057 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4237 | /* 11061 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4238 | /* 11065 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4239 | /* 11069 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4240 | /* 11074 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4241 | /* 11076 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4242 | /* 11076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 4243 | /* 11079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4244 | /* 11081 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 4245 | /* 11083 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4246 | /* 11087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4247 | /* 11090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4248 | /* 11096 */ GIR_RootConstrainSelectedInstOperands, |
| 4249 | /* 11097 */ // GIR_Coverage, 6057, |
| 4250 | /* 11097 */ GIR_EraseRootFromParent_Done, |
| 4251 | /* 11098 */ // Label 288: @11098 |
| 4252 | /* 11098 */ GIM_Reject, |
| 4253 | /* 11099 */ // Label 282: @11099 |
| 4254 | /* 11099 */ GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(11467), |
| 4255 | /* 11104 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4256 | /* 11108 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 290*/ GIMT_Encode4(11169), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1346 // |
| 4257 | /* 11115 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4258 | /* 11119 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4259 | /* 11123 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4260 | /* 11127 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4261 | /* 11131 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4262 | /* 11136 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4263 | /* 11141 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4264 | /* 11143 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4265 | /* 11143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32), |
| 4266 | /* 11146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4267 | /* 11148 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4268 | /* 11150 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4269 | /* 11154 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4270 | /* 11158 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4271 | /* 11161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4272 | /* 11167 */ GIR_RootConstrainSelectedInstOperands, |
| 4273 | /* 11168 */ // GIR_Coverage, 1346, |
| 4274 | /* 11168 */ GIR_EraseRootFromParent_Done, |
| 4275 | /* 11169 */ // Label 290: @11169 |
| 4276 | /* 11169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 291*/ GIMT_Encode4(11230), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1352 // |
| 4277 | /* 11176 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4278 | /* 11180 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4279 | /* 11184 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4280 | /* 11188 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4281 | /* 11192 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4282 | /* 11197 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4283 | /* 11202 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4284 | /* 11204 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4285 | /* 11204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32), |
| 4286 | /* 11207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4287 | /* 11209 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4288 | /* 11211 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4289 | /* 11215 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4290 | /* 11219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4291 | /* 11222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4292 | /* 11228 */ GIR_RootConstrainSelectedInstOperands, |
| 4293 | /* 11229 */ // GIR_Coverage, 1352, |
| 4294 | /* 11229 */ GIR_EraseRootFromParent_Done, |
| 4295 | /* 11230 */ // Label 291: @11230 |
| 4296 | /* 11230 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 292*/ GIMT_Encode4(11291), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1012 // |
| 4297 | /* 11237 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4298 | /* 11241 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4299 | /* 11245 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 4300 | /* 11249 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 4301 | /* 11253 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4302 | /* 11258 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4303 | /* 11263 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4304 | /* 11265 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4305 | /* 11265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32), |
| 4306 | /* 11268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4307 | /* 11270 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4308 | /* 11272 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4309 | /* 11276 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 4310 | /* 11280 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4311 | /* 11283 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4312 | /* 11289 */ GIR_RootConstrainSelectedInstOperands, |
| 4313 | /* 11290 */ // GIR_Coverage, 1012, |
| 4314 | /* 11290 */ GIR_EraseRootFromParent_Done, |
| 4315 | /* 11291 */ // Label 292: @11291 |
| 4316 | /* 11291 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 293*/ GIMT_Encode4(11339), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 909 // |
| 4317 | /* 11298 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4318 | /* 11302 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4319 | /* 11306 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4320 | /* 11310 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4321 | /* 11315 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4322 | /* 11317 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4323 | /* 11317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 4324 | /* 11320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4325 | /* 11322 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4326 | /* 11324 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4327 | /* 11328 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4328 | /* 11331 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4329 | /* 11337 */ GIR_RootConstrainSelectedInstOperands, |
| 4330 | /* 11338 */ // GIR_Coverage, 909, |
| 4331 | /* 11338 */ GIR_EraseRootFromParent_Done, |
| 4332 | /* 11339 */ // Label 293: @11339 |
| 4333 | /* 11339 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 294*/ GIMT_Encode4(11387), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 904 // |
| 4334 | /* 11346 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4335 | /* 11350 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4336 | /* 11354 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4337 | /* 11358 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4338 | /* 11363 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4339 | /* 11365 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4340 | /* 11365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32), |
| 4341 | /* 11368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4342 | /* 11370 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4343 | /* 11372 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4344 | /* 11376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4345 | /* 11379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4346 | /* 11385 */ GIR_RootConstrainSelectedInstOperands, |
| 4347 | /* 11386 */ // GIR_Coverage, 904, |
| 4348 | /* 11386 */ GIR_EraseRootFromParent_Done, |
| 4349 | /* 11387 */ // Label 294: @11387 |
| 4350 | /* 11387 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 295*/ GIMT_Encode4(11435), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 908 // |
| 4351 | /* 11394 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4352 | /* 11398 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4353 | /* 11402 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4354 | /* 11406 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4355 | /* 11411 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4356 | /* 11413 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 4357 | /* 11413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32), |
| 4358 | /* 11416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4359 | /* 11418 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4360 | /* 11420 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4361 | /* 11424 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4362 | /* 11427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4363 | /* 11433 */ GIR_RootConstrainSelectedInstOperands, |
| 4364 | /* 11434 */ // GIR_Coverage, 908, |
| 4365 | /* 11434 */ GIR_EraseRootFromParent_Done, |
| 4366 | /* 11435 */ // Label 295: @11435 |
| 4367 | /* 11435 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 296*/ GIMT_Encode4(11466), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 881 // |
| 4368 | /* 11442 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4369 | /* 11446 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 4370 | /* 11446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i32), |
| 4371 | /* 11449 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4372 | /* 11451 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4373 | /* 11453 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4374 | /* 11455 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4375 | /* 11458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4376 | /* 11464 */ GIR_RootConstrainSelectedInstOperands, |
| 4377 | /* 11465 */ // GIR_Coverage, 881, |
| 4378 | /* 11465 */ GIR_EraseRootFromParent_Done, |
| 4379 | /* 11466 */ // Label 296: @11466 |
| 4380 | /* 11466 */ GIM_Reject, |
| 4381 | /* 11467 */ // Label 289: @11467 |
| 4382 | /* 11467 */ GIM_Reject, |
| 4383 | /* 11468 */ // Label 270: @11468 |
| 4384 | /* 11468 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 297*/ GIMT_Encode4(11528), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3890 // |
| 4385 | /* 11475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4386 | /* 11479 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4387 | /* 11483 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 4388 | /* 11487 */ // (add:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 4389 | /* 11487 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 4390 | /* 11490 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 4391 | /* 11494 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 4392 | /* 11499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi32), |
| 4393 | /* 11502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 4394 | /* 11504 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 4395 | /* 11506 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 4396 | /* 11508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4397 | /* 11511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4398 | /* 11517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4399 | /* 11523 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4400 | /* 11526 */ GIR_RootConstrainSelectedInstOperands, |
| 4401 | /* 11527 */ // GIR_Coverage, 3890, |
| 4402 | /* 11527 */ GIR_EraseRootFromParent_Done, |
| 4403 | /* 11528 */ // Label 297: @11528 |
| 4404 | /* 11528 */ GIM_Reject, |
| 4405 | /* 11529 */ // Label 269: @11529 |
| 4406 | /* 11529 */ GIM_Reject, |
| 4407 | /* 11530 */ // Label 103: @11530 |
| 4408 | /* 11530 */ GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(12532), |
| 4409 | /* 11535 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 4410 | /* 11538 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 4411 | /* 11541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4412 | /* 11545 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 299*/ GIMT_Encode4(11612), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 902 // |
| 4413 | /* 11552 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4414 | /* 11556 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4415 | /* 11560 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4416 | /* 11564 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4417 | /* 11569 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4418 | /* 11573 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4419 | /* 11577 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4420 | /* 11581 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4421 | /* 11586 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4422 | /* 11588 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4423 | /* 11588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 4424 | /* 11591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4425 | /* 11593 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4426 | /* 11597 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4427 | /* 11601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4428 | /* 11604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4429 | /* 11610 */ GIR_RootConstrainSelectedInstOperands, |
| 4430 | /* 11611 */ // GIR_Coverage, 902, |
| 4431 | /* 11611 */ GIR_EraseRootFromParent_Done, |
| 4432 | /* 11612 */ // Label 299: @11612 |
| 4433 | /* 11612 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 300*/ GIMT_Encode4(11679), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 901 // |
| 4434 | /* 11619 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4435 | /* 11623 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4436 | /* 11627 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4437 | /* 11631 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4438 | /* 11636 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4439 | /* 11640 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4440 | /* 11644 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4441 | /* 11648 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4442 | /* 11653 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4443 | /* 11655 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4444 | /* 11655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 4445 | /* 11658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4446 | /* 11660 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4447 | /* 11664 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4448 | /* 11668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4449 | /* 11671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4450 | /* 11677 */ GIR_RootConstrainSelectedInstOperands, |
| 4451 | /* 11678 */ // GIR_Coverage, 901, |
| 4452 | /* 11678 */ GIR_EraseRootFromParent_Done, |
| 4453 | /* 11679 */ // Label 300: @11679 |
| 4454 | /* 11679 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 301*/ GIMT_Encode4(11746), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 890 // |
| 4455 | /* 11686 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4456 | /* 11690 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4457 | /* 11694 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4458 | /* 11698 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4459 | /* 11703 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4460 | /* 11707 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4461 | /* 11711 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4462 | /* 11715 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4463 | /* 11720 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4464 | /* 11722 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4465 | /* 11722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv2i64), |
| 4466 | /* 11725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4467 | /* 11727 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4468 | /* 11731 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4469 | /* 11735 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4470 | /* 11738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4471 | /* 11744 */ GIR_RootConstrainSelectedInstOperands, |
| 4472 | /* 11745 */ // GIR_Coverage, 890, |
| 4473 | /* 11745 */ GIR_EraseRootFromParent_Done, |
| 4474 | /* 11746 */ // Label 301: @11746 |
| 4475 | /* 11746 */ GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(11902), |
| 4476 | /* 11751 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4477 | /* 11755 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 303*/ GIMT_Encode4(11828), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6205 // |
| 4478 | /* 11762 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4479 | /* 11766 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4480 | /* 11770 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4481 | /* 11774 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4482 | /* 11778 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4483 | /* 11782 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4484 | /* 11786 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 4485 | /* 11790 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4486 | /* 11795 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4487 | /* 11800 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4488 | /* 11802 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4489 | /* 11802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64), |
| 4490 | /* 11805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4491 | /* 11807 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4492 | /* 11809 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4493 | /* 11813 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4494 | /* 11817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4495 | /* 11820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4496 | /* 11826 */ GIR_RootConstrainSelectedInstOperands, |
| 4497 | /* 11827 */ // GIR_Coverage, 6205, |
| 4498 | /* 11827 */ GIR_EraseRootFromParent_Done, |
| 4499 | /* 11828 */ // Label 303: @11828 |
| 4500 | /* 11828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 304*/ GIMT_Encode4(11901), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6208 // |
| 4501 | /* 11835 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4502 | /* 11839 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4503 | /* 11843 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4504 | /* 11847 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4505 | /* 11851 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4506 | /* 11855 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4507 | /* 11859 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 4508 | /* 11863 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4509 | /* 11868 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4510 | /* 11873 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4511 | /* 11875 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4512 | /* 11875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64), |
| 4513 | /* 11878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4514 | /* 11880 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4515 | /* 11882 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4516 | /* 11886 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4517 | /* 11890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4518 | /* 11893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4519 | /* 11899 */ GIR_RootConstrainSelectedInstOperands, |
| 4520 | /* 11900 */ // GIR_Coverage, 6208, |
| 4521 | /* 11900 */ GIR_EraseRootFromParent_Done, |
| 4522 | /* 11901 */ // Label 304: @11901 |
| 4523 | /* 11901 */ GIM_Reject, |
| 4524 | /* 11902 */ // Label 302: @11902 |
| 4525 | /* 11902 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 305*/ GIMT_Encode4(11969), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 900 // |
| 4526 | /* 11909 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4527 | /* 11913 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4528 | /* 11917 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4529 | /* 11921 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4530 | /* 11926 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4531 | /* 11930 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4532 | /* 11934 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4533 | /* 11938 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4534 | /* 11943 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4535 | /* 11945 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4536 | /* 11945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 4537 | /* 11948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4538 | /* 11950 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4539 | /* 11954 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4540 | /* 11958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4541 | /* 11961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4542 | /* 11967 */ GIR_RootConstrainSelectedInstOperands, |
| 4543 | /* 11968 */ // GIR_Coverage, 900, |
| 4544 | /* 11968 */ GIR_EraseRootFromParent_Done, |
| 4545 | /* 11969 */ // Label 305: @11969 |
| 4546 | /* 11969 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 306*/ GIMT_Encode4(12036), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 899 // |
| 4547 | /* 11976 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4548 | /* 11980 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4549 | /* 11984 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4550 | /* 11988 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4551 | /* 11993 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4552 | /* 11997 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4553 | /* 12001 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4554 | /* 12005 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4555 | /* 12010 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4556 | /* 12012 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4557 | /* 12012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64), |
| 4558 | /* 12015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4559 | /* 12017 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 4560 | /* 12021 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 4561 | /* 12025 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4562 | /* 12028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4563 | /* 12034 */ GIR_RootConstrainSelectedInstOperands, |
| 4564 | /* 12035 */ // GIR_Coverage, 899, |
| 4565 | /* 12035 */ GIR_EraseRootFromParent_Done, |
| 4566 | /* 12036 */ // Label 306: @12036 |
| 4567 | /* 12036 */ GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(12192), |
| 4568 | /* 12041 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4569 | /* 12045 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 308*/ GIMT_Encode4(12118), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1355 // |
| 4570 | /* 12052 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4571 | /* 12056 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4572 | /* 12060 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4573 | /* 12064 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4574 | /* 12068 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 4575 | /* 12072 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4576 | /* 12076 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 4577 | /* 12080 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4578 | /* 12085 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4579 | /* 12090 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4580 | /* 12092 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4581 | /* 12092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64), |
| 4582 | /* 12095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4583 | /* 12097 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4584 | /* 12099 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4585 | /* 12103 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4586 | /* 12107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4587 | /* 12110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4588 | /* 12116 */ GIR_RootConstrainSelectedInstOperands, |
| 4589 | /* 12117 */ // GIR_Coverage, 1355, |
| 4590 | /* 12117 */ GIR_EraseRootFromParent_Done, |
| 4591 | /* 12118 */ // Label 308: @12118 |
| 4592 | /* 12118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 309*/ GIMT_Encode4(12191), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1358 // |
| 4593 | /* 12125 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4594 | /* 12129 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4595 | /* 12133 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4596 | /* 12137 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4597 | /* 12141 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 4598 | /* 12145 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4599 | /* 12149 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32, |
| 4600 | /* 12153 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4601 | /* 12158 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4602 | /* 12163 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4603 | /* 12165 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4604 | /* 12165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64), |
| 4605 | /* 12168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4606 | /* 12170 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4607 | /* 12172 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn |
| 4608 | /* 12176 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm |
| 4609 | /* 12180 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4610 | /* 12183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4611 | /* 12189 */ GIR_RootConstrainSelectedInstOperands, |
| 4612 | /* 12190 */ // GIR_Coverage, 1358, |
| 4613 | /* 12190 */ GIR_EraseRootFromParent_Done, |
| 4614 | /* 12191 */ // Label 309: @12191 |
| 4615 | /* 12191 */ GIM_Reject, |
| 4616 | /* 12192 */ // Label 307: @12192 |
| 4617 | /* 12192 */ GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(12346), |
| 4618 | /* 12197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4619 | /* 12201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 311*/ GIMT_Encode4(12249), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6060 // |
| 4620 | /* 12208 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4621 | /* 12212 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4622 | /* 12216 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4623 | /* 12220 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4624 | /* 12225 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4625 | /* 12227 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4626 | /* 12227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 4627 | /* 12230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4628 | /* 12232 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 4629 | /* 12234 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4630 | /* 12238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4631 | /* 12241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4632 | /* 12247 */ GIR_RootConstrainSelectedInstOperands, |
| 4633 | /* 12248 */ // GIR_Coverage, 6060, |
| 4634 | /* 12248 */ GIR_EraseRootFromParent_Done, |
| 4635 | /* 12249 */ // Label 311: @12249 |
| 4636 | /* 12249 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 312*/ GIMT_Encode4(12297), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6054 // |
| 4637 | /* 12256 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4638 | /* 12260 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4639 | /* 12264 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4640 | /* 12268 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4641 | /* 12273 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4642 | /* 12275 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4643 | /* 12275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64), |
| 4644 | /* 12278 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4645 | /* 12280 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 4646 | /* 12282 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4647 | /* 12286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4648 | /* 12289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4649 | /* 12295 */ GIR_RootConstrainSelectedInstOperands, |
| 4650 | /* 12296 */ // GIR_Coverage, 6054, |
| 4651 | /* 12296 */ GIR_EraseRootFromParent_Done, |
| 4652 | /* 12297 */ // Label 312: @12297 |
| 4653 | /* 12297 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 313*/ GIMT_Encode4(12345), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6059 // |
| 4654 | /* 12304 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4655 | /* 12308 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4656 | /* 12312 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4657 | /* 12316 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4658 | /* 12321 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4659 | /* 12323 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4660 | /* 12323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 4661 | /* 12326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4662 | /* 12328 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 4663 | /* 12330 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4664 | /* 12334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4665 | /* 12337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4666 | /* 12343 */ GIR_RootConstrainSelectedInstOperands, |
| 4667 | /* 12344 */ // GIR_Coverage, 6059, |
| 4668 | /* 12344 */ GIR_EraseRootFromParent_Done, |
| 4669 | /* 12345 */ // Label 313: @12345 |
| 4670 | /* 12345 */ GIM_Reject, |
| 4671 | /* 12346 */ // Label 310: @12346 |
| 4672 | /* 12346 */ GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(12531), |
| 4673 | /* 12351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4674 | /* 12355 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 315*/ GIMT_Encode4(12403), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 911 // |
| 4675 | /* 12362 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4676 | /* 12366 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 4677 | /* 12370 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4678 | /* 12374 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4679 | /* 12379 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4680 | /* 12381 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4681 | /* 12381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 4682 | /* 12384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4683 | /* 12386 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4684 | /* 12388 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4685 | /* 12392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4686 | /* 12395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4687 | /* 12401 */ GIR_RootConstrainSelectedInstOperands, |
| 4688 | /* 12402 */ // GIR_Coverage, 911, |
| 4689 | /* 12402 */ GIR_EraseRootFromParent_Done, |
| 4690 | /* 12403 */ // Label 315: @12403 |
| 4691 | /* 12403 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 316*/ GIMT_Encode4(12451), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 905 // |
| 4692 | /* 12410 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4693 | /* 12414 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 4694 | /* 12418 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4695 | /* 12422 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4696 | /* 12427 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4697 | /* 12429 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4698 | /* 12429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64), |
| 4699 | /* 12432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4700 | /* 12434 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4701 | /* 12436 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4702 | /* 12440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4703 | /* 12443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4704 | /* 12449 */ GIR_RootConstrainSelectedInstOperands, |
| 4705 | /* 12450 */ // GIR_Coverage, 905, |
| 4706 | /* 12450 */ GIR_EraseRootFromParent_Done, |
| 4707 | /* 12451 */ // Label 316: @12451 |
| 4708 | /* 12451 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 317*/ GIMT_Encode4(12499), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 910 // |
| 4709 | /* 12458 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4710 | /* 12462 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 4711 | /* 12466 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4712 | /* 12470 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4713 | /* 12475 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4714 | /* 12477 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 4715 | /* 12477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64), |
| 4716 | /* 12480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4717 | /* 12482 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4718 | /* 12484 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 4719 | /* 12488 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4720 | /* 12491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4721 | /* 12497 */ GIR_RootConstrainSelectedInstOperands, |
| 4722 | /* 12498 */ // GIR_Coverage, 910, |
| 4723 | /* 12498 */ GIR_EraseRootFromParent_Done, |
| 4724 | /* 12499 */ // Label 317: @12499 |
| 4725 | /* 12499 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 318*/ GIMT_Encode4(12530), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 883 // |
| 4726 | /* 12506 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 4727 | /* 12510 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 4728 | /* 12510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i64), |
| 4729 | /* 12513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4730 | /* 12515 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4731 | /* 12517 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4732 | /* 12519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4733 | /* 12522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4734 | /* 12528 */ GIR_RootConstrainSelectedInstOperands, |
| 4735 | /* 12529 */ // GIR_Coverage, 883, |
| 4736 | /* 12529 */ GIR_EraseRootFromParent_Done, |
| 4737 | /* 12530 */ // Label 318: @12530 |
| 4738 | /* 12530 */ GIM_Reject, |
| 4739 | /* 12531 */ // Label 314: @12531 |
| 4740 | /* 12531 */ GIM_Reject, |
| 4741 | /* 12532 */ // Label 298: @12532 |
| 4742 | /* 12532 */ GIM_Reject, |
| 4743 | /* 12533 */ // Label 104: @12533 |
| 4744 | /* 12533 */ GIM_Reject, |
| 4745 | /* 12534 */ // Label 1: @12534 |
| 4746 | /* 12534 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 328*/ GIMT_Encode4(15631), |
| 4747 | /* 12545 */ /*GILLT_s32*//*Label 319*/ GIMT_Encode4(12597), |
| 4748 | /* 12549 */ /*GILLT_s64*//*Label 320*/ GIMT_Encode4(13202), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 4749 | /* 12569 */ /*GILLT_v8s8*//*Label 321*/ GIMT_Encode4(13248), |
| 4750 | /* 12573 */ /*GILLT_v16s8*//*Label 322*/ GIMT_Encode4(13361), |
| 4751 | /* 12577 */ /*GILLT_v4s16*//*Label 323*/ GIMT_Encode4(13540), |
| 4752 | /* 12581 */ /*GILLT_v8s16*//*Label 324*/ GIMT_Encode4(13653), |
| 4753 | /* 12585 */ /*GILLT_v2s32*//*Label 325*/ GIMT_Encode4(14317), |
| 4754 | /* 12589 */ /*GILLT_v4s32*//*Label 326*/ GIMT_Encode4(14430), |
| 4755 | /* 12593 */ /*GILLT_v2s64*//*Label 327*/ GIMT_Encode4(15094), |
| 4756 | /* 12597 */ // Label 319: @12597 |
| 4757 | /* 12597 */ GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(13201), |
| 4758 | /* 12602 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 4759 | /* 12605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4760 | /* 12608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 330*/ GIMT_Encode4(12651), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 329 // |
| 4761 | /* 12615 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4762 | /* 12619 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, |
| 4763 | /* 12623 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4764 | /* 12627 */ // (sub:{ *:[i32] } 0:{ *:[i32] }, tGPR:{ *:[i32] }:$Rn) => (tRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn) |
| 4765 | /* 12627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tRSB), |
| 4766 | /* 12630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4767 | /* 12632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 4768 | /* 12638 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4769 | /* 12640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4770 | /* 12643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4771 | /* 12649 */ GIR_RootConstrainSelectedInstOperands, |
| 4772 | /* 12650 */ // GIR_Coverage, 329, |
| 4773 | /* 12650 */ GIR_EraseRootFromParent_Done, |
| 4774 | /* 12651 */ // Label 330: @12651 |
| 4775 | /* 12651 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 331*/ GIMT_Encode4(12707), GIMT_Encode2(GIFBS_IsARM), // Rule ID 95 // |
| 4776 | /* 12658 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4777 | /* 12662 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4778 | /* 12666 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4779 | /* 12670 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 4780 | /* 12674 */ // MIs[1] Operand 1 |
| 4781 | /* 12674 */ // No operand predicates |
| 4782 | /* 12674 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4783 | /* 12678 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4784 | /* 12680 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn) => (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4785 | /* 12680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RSBri), |
| 4786 | /* 12683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4787 | /* 12685 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4788 | /* 12687 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4789 | /* 12690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4790 | /* 12693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4791 | /* 12699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4792 | /* 12705 */ GIR_RootConstrainSelectedInstOperands, |
| 4793 | /* 12706 */ // GIR_Coverage, 95, |
| 4794 | /* 12706 */ GIR_EraseRootFromParent_Done, |
| 4795 | /* 12707 */ // Label 331: @12707 |
| 4796 | /* 12707 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 332*/ GIMT_Encode4(12763), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 426 // |
| 4797 | /* 12714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4798 | /* 12718 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4799 | /* 12722 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4800 | /* 12726 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 4801 | /* 12730 */ // MIs[1] Operand 1 |
| 4802 | /* 12730 */ // No operand predicates |
| 4803 | /* 12730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4804 | /* 12734 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4805 | /* 12736 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn) => (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4806 | /* 12736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RSBri), |
| 4807 | /* 12739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4808 | /* 12741 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 4809 | /* 12743 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4810 | /* 12746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4811 | /* 12749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4812 | /* 12755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4813 | /* 12761 */ GIR_RootConstrainSelectedInstOperands, |
| 4814 | /* 12762 */ // GIR_Coverage, 426, |
| 4815 | /* 12762 */ GIR_EraseRootFromParent_Done, |
| 4816 | /* 12763 */ // Label 332: @12763 |
| 4817 | /* 12763 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 333*/ GIMT_Encode4(12819), GIMT_Encode2(GIFBS_IsARM), // Rule ID 75 // |
| 4818 | /* 12770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4819 | /* 12774 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4820 | /* 12778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4821 | /* 12782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4822 | /* 12786 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 4823 | /* 12790 */ // MIs[1] Operand 1 |
| 4824 | /* 12790 */ // No operand predicates |
| 4825 | /* 12790 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4826 | /* 12792 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4827 | /* 12792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBri), |
| 4828 | /* 12795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4829 | /* 12797 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4830 | /* 12799 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4831 | /* 12802 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4832 | /* 12805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4833 | /* 12811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4834 | /* 12817 */ GIR_RootConstrainSelectedInstOperands, |
| 4835 | /* 12818 */ // GIR_Coverage, 75, |
| 4836 | /* 12818 */ GIR_EraseRootFromParent_Done, |
| 4837 | /* 12819 */ // Label 333: @12819 |
| 4838 | /* 12819 */ GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(12927), |
| 4839 | /* 12824 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4840 | /* 12828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 335*/ GIMT_Encode4(12880), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 410 // |
| 4841 | /* 12835 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4842 | /* 12839 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4843 | /* 12843 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4844 | /* 12847 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 4845 | /* 12851 */ // MIs[1] Operand 1 |
| 4846 | /* 12851 */ // No operand predicates |
| 4847 | /* 12851 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4848 | /* 12853 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4849 | /* 12853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri), |
| 4850 | /* 12856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4851 | /* 12858 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4852 | /* 12860 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4853 | /* 12863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4854 | /* 12866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4855 | /* 12872 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4856 | /* 12878 */ GIR_RootConstrainSelectedInstOperands, |
| 4857 | /* 12879 */ // GIR_Coverage, 410, |
| 4858 | /* 12879 */ GIR_EraseRootFromParent_Done, |
| 4859 | /* 12880 */ // Label 335: @12880 |
| 4860 | /* 12880 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 336*/ GIMT_Encode4(12926), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 411 // |
| 4861 | /* 12887 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4862 | /* 12891 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4863 | /* 12895 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4864 | /* 12899 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095), |
| 4865 | /* 12903 */ // MIs[1] Operand 1 |
| 4866 | /* 12903 */ // No operand predicates |
| 4867 | /* 12903 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4868 | /* 12905 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 4869 | /* 12905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri12), |
| 4870 | /* 12908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4871 | /* 12910 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4872 | /* 12912 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 4873 | /* 12915 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4874 | /* 12918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4875 | /* 12924 */ GIR_RootConstrainSelectedInstOperands, |
| 4876 | /* 12925 */ // GIR_Coverage, 411, |
| 4877 | /* 12925 */ GIR_EraseRootFromParent_Done, |
| 4878 | /* 12926 */ // Label 336: @12926 |
| 4879 | /* 12926 */ GIM_Reject, |
| 4880 | /* 12927 */ // Label 334: @12927 |
| 4881 | /* 12927 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 337*/ GIMT_Encode4(12996), GIMT_Encode2(GIFBS_HasV6T2_IsARM_UseMulOps), // Rule ID 172 // |
| 4882 | /* 12934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4883 | /* 12938 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4884 | /* 12942 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4885 | /* 12946 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4886 | /* 12950 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4887 | /* 12954 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4888 | /* 12958 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4889 | /* 12963 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4890 | /* 12968 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4891 | /* 12970 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 4892 | /* 12970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLS), |
| 4893 | /* 12973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4894 | /* 12975 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4895 | /* 12979 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 4896 | /* 12983 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 4897 | /* 12985 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4898 | /* 12988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4899 | /* 12994 */ GIR_RootConstrainSelectedInstOperands, |
| 4900 | /* 12995 */ // GIR_Coverage, 172, |
| 4901 | /* 12995 */ GIR_EraseRootFromParent_Done, |
| 4902 | /* 12996 */ // Label 337: @12996 |
| 4903 | /* 12996 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 338*/ GIMT_Encode4(13065), GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), // Rule ID 503 // |
| 4904 | /* 13003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4905 | /* 13007 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4906 | /* 13011 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4907 | /* 13015 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 4908 | /* 13019 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4909 | /* 13023 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4910 | /* 13027 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4911 | /* 13032 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4912 | /* 13037 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4913 | /* 13039 */ // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 4914 | /* 13039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLS), |
| 4915 | /* 13042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4916 | /* 13044 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 4917 | /* 13048 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm |
| 4918 | /* 13052 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra |
| 4919 | /* 13054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4920 | /* 13057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4921 | /* 13063 */ GIR_RootConstrainSelectedInstOperands, |
| 4922 | /* 13064 */ // GIR_Coverage, 503, |
| 4923 | /* 13064 */ GIR_EraseRootFromParent_Done, |
| 4924 | /* 13065 */ // Label 338: @13065 |
| 4925 | /* 13065 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 339*/ GIMT_Encode4(13110), GIMT_Encode2(GIFBS_IsARM), // Rule ID 76 // |
| 4926 | /* 13072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4927 | /* 13076 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4928 | /* 13080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 4929 | /* 13084 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 4930 | /* 13084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBrr), |
| 4931 | /* 13087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4932 | /* 13089 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4933 | /* 13091 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4934 | /* 13093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4935 | /* 13096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4936 | /* 13102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4937 | /* 13108 */ GIR_RootConstrainSelectedInstOperands, |
| 4938 | /* 13109 */ // GIR_Coverage, 76, |
| 4939 | /* 13109 */ GIR_EraseRootFromParent_Done, |
| 4940 | /* 13110 */ // Label 339: @13110 |
| 4941 | /* 13110 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 340*/ GIMT_Encode4(13155), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 332 // |
| 4942 | /* 13117 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4943 | /* 13121 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4944 | /* 13125 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 4945 | /* 13129 */ // (sub:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tSUBrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 4946 | /* 13129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSUBrr), |
| 4947 | /* 13132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4948 | /* 13134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 4949 | /* 13140 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4950 | /* 13142 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4951 | /* 13144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4952 | /* 13147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4953 | /* 13153 */ GIR_RootConstrainSelectedInstOperands, |
| 4954 | /* 13154 */ // GIR_Coverage, 332, |
| 4955 | /* 13154 */ GIR_EraseRootFromParent_Done, |
| 4956 | /* 13155 */ // Label 340: @13155 |
| 4957 | /* 13155 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 341*/ GIMT_Encode4(13200), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 412 // |
| 4958 | /* 13162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4959 | /* 13166 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 4960 | /* 13170 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 4961 | /* 13174 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 4962 | /* 13174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBrr), |
| 4963 | /* 13177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 4964 | /* 13179 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 4965 | /* 13181 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 4966 | /* 13183 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4967 | /* 13186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4968 | /* 13192 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4969 | /* 13198 */ GIR_RootConstrainSelectedInstOperands, |
| 4970 | /* 13199 */ // GIR_Coverage, 412, |
| 4971 | /* 13199 */ GIR_EraseRootFromParent_Done, |
| 4972 | /* 13200 */ // Label 341: @13200 |
| 4973 | /* 13200 */ GIM_Reject, |
| 4974 | /* 13201 */ // Label 329: @13201 |
| 4975 | /* 13201 */ GIM_Reject, |
| 4976 | /* 13202 */ // Label 320: @13202 |
| 4977 | /* 13202 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 342*/ GIMT_Encode4(13247), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1128 // |
| 4978 | /* 13209 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 4979 | /* 13212 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 4980 | /* 13215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4981 | /* 13219 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4982 | /* 13223 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 4983 | /* 13227 */ // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 4984 | /* 13227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv1i64), |
| 4985 | /* 13230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 4986 | /* 13232 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 4987 | /* 13234 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 4988 | /* 13236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 4989 | /* 13239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 4990 | /* 13245 */ GIR_RootConstrainSelectedInstOperands, |
| 4991 | /* 13246 */ // GIR_Coverage, 1128, |
| 4992 | /* 13246 */ GIR_EraseRootFromParent_Done, |
| 4993 | /* 13247 */ // Label 342: @13247 |
| 4994 | /* 13247 */ GIM_Reject, |
| 4995 | /* 13248 */ // Label 321: @13248 |
| 4996 | /* 13248 */ GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(13360), |
| 4997 | /* 13253 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 4998 | /* 13256 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 4999 | /* 13259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5000 | /* 13263 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5001 | /* 13267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 344*/ GIMT_Encode4(13328), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1053 // |
| 5002 | /* 13274 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5003 | /* 13278 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5004 | /* 13282 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5005 | /* 13286 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 5006 | /* 13290 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5007 | /* 13295 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5008 | /* 13300 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5009 | /* 13302 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5010 | /* 13302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i8), |
| 5011 | /* 13305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5012 | /* 13307 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5013 | /* 13309 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5014 | /* 13313 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5015 | /* 13317 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5016 | /* 13320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5017 | /* 13326 */ GIR_RootConstrainSelectedInstOperands, |
| 5018 | /* 13327 */ // GIR_Coverage, 1053, |
| 5019 | /* 13327 */ GIR_EraseRootFromParent_Done, |
| 5020 | /* 13328 */ // Label 344: @13328 |
| 5021 | /* 13328 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 345*/ GIMT_Encode4(13359), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1122 // |
| 5022 | /* 13335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5023 | /* 13339 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5024 | /* 13339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i8), |
| 5025 | /* 13342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5026 | /* 13344 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5027 | /* 13346 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5028 | /* 13348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5029 | /* 13351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5030 | /* 13357 */ GIR_RootConstrainSelectedInstOperands, |
| 5031 | /* 13358 */ // GIR_Coverage, 1122, |
| 5032 | /* 13358 */ GIR_EraseRootFromParent_Done, |
| 5033 | /* 13359 */ // Label 345: @13359 |
| 5034 | /* 13359 */ GIM_Reject, |
| 5035 | /* 13360 */ // Label 343: @13360 |
| 5036 | /* 13360 */ GIM_Reject, |
| 5037 | /* 13361 */ // Label 322: @13361 |
| 5038 | /* 13361 */ GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(13539), |
| 5039 | /* 13366 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 5040 | /* 13369 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5041 | /* 13372 */ GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(13478), |
| 5042 | /* 13377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5043 | /* 13381 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5044 | /* 13385 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 348*/ GIMT_Encode4(13446), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1056 // |
| 5045 | /* 13392 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5046 | /* 13396 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5047 | /* 13400 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 5048 | /* 13404 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 5049 | /* 13408 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5050 | /* 13413 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5051 | /* 13418 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5052 | /* 13420 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 5053 | /* 13420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv16i8), |
| 5054 | /* 13423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5055 | /* 13425 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5056 | /* 13427 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5057 | /* 13431 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5058 | /* 13435 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5059 | /* 13438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5060 | /* 13444 */ GIR_RootConstrainSelectedInstOperands, |
| 5061 | /* 13445 */ // GIR_Coverage, 1056, |
| 5062 | /* 13445 */ GIR_EraseRootFromParent_Done, |
| 5063 | /* 13446 */ // Label 348: @13446 |
| 5064 | /* 13446 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 349*/ GIMT_Encode4(13477), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1125 // |
| 5065 | /* 13453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5066 | /* 13457 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 5067 | /* 13457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv16i8), |
| 5068 | /* 13460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5069 | /* 13462 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5070 | /* 13464 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5071 | /* 13466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5072 | /* 13469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5073 | /* 13475 */ GIR_RootConstrainSelectedInstOperands, |
| 5074 | /* 13476 */ // GIR_Coverage, 1125, |
| 5075 | /* 13476 */ GIR_EraseRootFromParent_Done, |
| 5076 | /* 13477 */ // Label 349: @13477 |
| 5077 | /* 13477 */ GIM_Reject, |
| 5078 | /* 13478 */ // Label 347: @13478 |
| 5079 | /* 13478 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 350*/ GIMT_Encode4(13538), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3894 // |
| 5080 | /* 13485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5081 | /* 13489 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5082 | /* 13493 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5083 | /* 13497 */ // (sub:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VSUBi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 5084 | /* 13497 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5085 | /* 13500 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5086 | /* 13504 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 5087 | /* 13509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi8), |
| 5088 | /* 13512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5089 | /* 13514 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5090 | /* 13516 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5091 | /* 13518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5092 | /* 13521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5093 | /* 13527 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5094 | /* 13533 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5095 | /* 13536 */ GIR_RootConstrainSelectedInstOperands, |
| 5096 | /* 13537 */ // GIR_Coverage, 3894, |
| 5097 | /* 13537 */ GIR_EraseRootFromParent_Done, |
| 5098 | /* 13538 */ // Label 350: @13538 |
| 5099 | /* 13538 */ GIM_Reject, |
| 5100 | /* 13539 */ // Label 346: @13539 |
| 5101 | /* 13539 */ GIM_Reject, |
| 5102 | /* 13540 */ // Label 323: @13540 |
| 5103 | /* 13540 */ GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(13652), |
| 5104 | /* 13545 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5105 | /* 13548 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 5106 | /* 13551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5107 | /* 13555 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5108 | /* 13559 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 352*/ GIMT_Encode4(13620), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1054 // |
| 5109 | /* 13566 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5110 | /* 13570 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5111 | /* 13574 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5112 | /* 13578 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 5113 | /* 13582 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5114 | /* 13587 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5115 | /* 13592 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5116 | /* 13594 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5117 | /* 13594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i16), |
| 5118 | /* 13597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5119 | /* 13599 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5120 | /* 13601 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5121 | /* 13605 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5122 | /* 13609 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5123 | /* 13612 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5124 | /* 13618 */ GIR_RootConstrainSelectedInstOperands, |
| 5125 | /* 13619 */ // GIR_Coverage, 1054, |
| 5126 | /* 13619 */ GIR_EraseRootFromParent_Done, |
| 5127 | /* 13620 */ // Label 352: @13620 |
| 5128 | /* 13620 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 353*/ GIMT_Encode4(13651), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1123 // |
| 5129 | /* 13627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5130 | /* 13631 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5131 | /* 13631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i16), |
| 5132 | /* 13634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5133 | /* 13636 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5134 | /* 13638 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5135 | /* 13640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5136 | /* 13643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5137 | /* 13649 */ GIR_RootConstrainSelectedInstOperands, |
| 5138 | /* 13650 */ // GIR_Coverage, 1123, |
| 5139 | /* 13650 */ GIR_EraseRootFromParent_Done, |
| 5140 | /* 13651 */ // Label 353: @13651 |
| 5141 | /* 13651 */ GIM_Reject, |
| 5142 | /* 13652 */ // Label 351: @13652 |
| 5143 | /* 13652 */ GIM_Reject, |
| 5144 | /* 13653 */ // Label 324: @13653 |
| 5145 | /* 13653 */ GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(14316), |
| 5146 | /* 13658 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 5147 | /* 13661 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5148 | /* 13664 */ GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(14255), |
| 5149 | /* 13669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5150 | /* 13673 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 356*/ GIMT_Encode4(13740), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1140 // |
| 5151 | /* 13680 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5152 | /* 13684 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5153 | /* 13688 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5154 | /* 13692 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5155 | /* 13697 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5156 | /* 13701 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5157 | /* 13705 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5158 | /* 13709 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5159 | /* 13714 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5160 | /* 13716 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5161 | /* 13716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 5162 | /* 13719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5163 | /* 13721 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5164 | /* 13725 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5165 | /* 13729 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5166 | /* 13732 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5167 | /* 13738 */ GIR_RootConstrainSelectedInstOperands, |
| 5168 | /* 13739 */ // GIR_Coverage, 1140, |
| 5169 | /* 13739 */ GIR_EraseRootFromParent_Done, |
| 5170 | /* 13740 */ // Label 356: @13740 |
| 5171 | /* 13740 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 357*/ GIMT_Encode4(13807), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1139 // |
| 5172 | /* 13747 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5173 | /* 13751 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5174 | /* 13755 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5175 | /* 13759 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5176 | /* 13764 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5177 | /* 13768 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5178 | /* 13772 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5179 | /* 13776 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5180 | /* 13781 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5181 | /* 13783 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5182 | /* 13783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 5183 | /* 13786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5184 | /* 13788 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5185 | /* 13792 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5186 | /* 13796 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5187 | /* 13799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5188 | /* 13805 */ GIR_RootConstrainSelectedInstOperands, |
| 5189 | /* 13806 */ // GIR_Coverage, 1139, |
| 5190 | /* 13806 */ GIR_EraseRootFromParent_Done, |
| 5191 | /* 13807 */ // Label 357: @13807 |
| 5192 | /* 13807 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 358*/ GIMT_Encode4(13874), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1134 // |
| 5193 | /* 13814 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5194 | /* 13818 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5195 | /* 13822 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5196 | /* 13826 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5197 | /* 13831 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5198 | /* 13835 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5199 | /* 13839 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5200 | /* 13843 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5201 | /* 13848 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5202 | /* 13850 */ // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5203 | /* 13850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv8i16), |
| 5204 | /* 13853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5205 | /* 13855 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5206 | /* 13859 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5207 | /* 13863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5208 | /* 13866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5209 | /* 13872 */ GIR_RootConstrainSelectedInstOperands, |
| 5210 | /* 13873 */ // GIR_Coverage, 1134, |
| 5211 | /* 13873 */ GIR_EraseRootFromParent_Done, |
| 5212 | /* 13874 */ // Label 358: @13874 |
| 5213 | /* 13874 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 359*/ GIMT_Encode4(13941), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1138 // |
| 5214 | /* 13881 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5215 | /* 13885 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5216 | /* 13889 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5217 | /* 13893 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5218 | /* 13898 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5219 | /* 13902 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5220 | /* 13906 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5221 | /* 13910 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5222 | /* 13915 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5223 | /* 13917 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5224 | /* 13917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 5225 | /* 13920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5226 | /* 13922 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5227 | /* 13926 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5228 | /* 13930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5229 | /* 13933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5230 | /* 13939 */ GIR_RootConstrainSelectedInstOperands, |
| 5231 | /* 13940 */ // GIR_Coverage, 1138, |
| 5232 | /* 13940 */ GIR_EraseRootFromParent_Done, |
| 5233 | /* 13941 */ // Label 359: @13941 |
| 5234 | /* 13941 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 360*/ GIMT_Encode4(14008), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1137 // |
| 5235 | /* 13948 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5236 | /* 13952 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5237 | /* 13956 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5238 | /* 13960 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5239 | /* 13965 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5240 | /* 13969 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5241 | /* 13973 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5242 | /* 13977 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5243 | /* 13982 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5244 | /* 13984 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5245 | /* 13984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16), |
| 5246 | /* 13987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5247 | /* 13989 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5248 | /* 13993 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5249 | /* 13997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5250 | /* 14000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5251 | /* 14006 */ GIR_RootConstrainSelectedInstOperands, |
| 5252 | /* 14007 */ // GIR_Coverage, 1137, |
| 5253 | /* 14007 */ GIR_EraseRootFromParent_Done, |
| 5254 | /* 14008 */ // Label 360: @14008 |
| 5255 | /* 14008 */ GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(14254), |
| 5256 | /* 14013 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5257 | /* 14017 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 362*/ GIMT_Encode4(14078), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1057 // |
| 5258 | /* 14024 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5259 | /* 14028 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5260 | /* 14032 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 5261 | /* 14036 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 5262 | /* 14040 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5263 | /* 14045 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5264 | /* 14050 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5265 | /* 14052 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 5266 | /* 14052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i16), |
| 5267 | /* 14055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5268 | /* 14057 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5269 | /* 14059 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5270 | /* 14063 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5271 | /* 14067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5272 | /* 14070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5273 | /* 14076 */ GIR_RootConstrainSelectedInstOperands, |
| 5274 | /* 14077 */ // GIR_Coverage, 1057, |
| 5275 | /* 14077 */ GIR_EraseRootFromParent_Done, |
| 5276 | /* 14078 */ // Label 362: @14078 |
| 5277 | /* 14078 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 363*/ GIMT_Encode4(14126), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1153 // |
| 5278 | /* 14085 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5279 | /* 14089 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5280 | /* 14093 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5281 | /* 14097 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5282 | /* 14102 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5283 | /* 14104 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5284 | /* 14104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16), |
| 5285 | /* 14107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5286 | /* 14109 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5287 | /* 14111 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5288 | /* 14115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5289 | /* 14118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5290 | /* 14124 */ GIR_RootConstrainSelectedInstOperands, |
| 5291 | /* 14125 */ // GIR_Coverage, 1153, |
| 5292 | /* 14125 */ GIR_EraseRootFromParent_Done, |
| 5293 | /* 14126 */ // Label 363: @14126 |
| 5294 | /* 14126 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 364*/ GIMT_Encode4(14174), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1149 // |
| 5295 | /* 14133 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5296 | /* 14137 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5297 | /* 14141 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5298 | /* 14145 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5299 | /* 14150 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5300 | /* 14152 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5301 | /* 14152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv8i16), |
| 5302 | /* 14155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5303 | /* 14157 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5304 | /* 14159 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5305 | /* 14163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5306 | /* 14166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5307 | /* 14172 */ GIR_RootConstrainSelectedInstOperands, |
| 5308 | /* 14173 */ // GIR_Coverage, 1149, |
| 5309 | /* 14173 */ GIR_EraseRootFromParent_Done, |
| 5310 | /* 14174 */ // Label 364: @14174 |
| 5311 | /* 14174 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 365*/ GIMT_Encode4(14222), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1152 // |
| 5312 | /* 14181 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5313 | /* 14185 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5314 | /* 14189 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 5315 | /* 14193 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5316 | /* 14198 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5317 | /* 14200 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 5318 | /* 14200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16), |
| 5319 | /* 14203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5320 | /* 14205 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5321 | /* 14207 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5322 | /* 14211 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5323 | /* 14214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5324 | /* 14220 */ GIR_RootConstrainSelectedInstOperands, |
| 5325 | /* 14221 */ // GIR_Coverage, 1152, |
| 5326 | /* 14221 */ GIR_EraseRootFromParent_Done, |
| 5327 | /* 14222 */ // Label 365: @14222 |
| 5328 | /* 14222 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 366*/ GIMT_Encode4(14253), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1126 // |
| 5329 | /* 14229 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5330 | /* 14233 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 5331 | /* 14233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i16), |
| 5332 | /* 14236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5333 | /* 14238 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5334 | /* 14240 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5335 | /* 14242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5336 | /* 14245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5337 | /* 14251 */ GIR_RootConstrainSelectedInstOperands, |
| 5338 | /* 14252 */ // GIR_Coverage, 1126, |
| 5339 | /* 14252 */ GIR_EraseRootFromParent_Done, |
| 5340 | /* 14253 */ // Label 366: @14253 |
| 5341 | /* 14253 */ GIM_Reject, |
| 5342 | /* 14254 */ // Label 361: @14254 |
| 5343 | /* 14254 */ GIM_Reject, |
| 5344 | /* 14255 */ // Label 355: @14255 |
| 5345 | /* 14255 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 367*/ GIMT_Encode4(14315), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3898 // |
| 5346 | /* 14262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5347 | /* 14266 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5348 | /* 14270 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5349 | /* 14274 */ // (sub:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VSUBi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 5350 | /* 14274 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5351 | /* 14277 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5352 | /* 14281 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 5353 | /* 14286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi16), |
| 5354 | /* 14289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5355 | /* 14291 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5356 | /* 14293 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5357 | /* 14295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5358 | /* 14298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5359 | /* 14304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5360 | /* 14310 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5361 | /* 14313 */ GIR_RootConstrainSelectedInstOperands, |
| 5362 | /* 14314 */ // GIR_Coverage, 3898, |
| 5363 | /* 14314 */ GIR_EraseRootFromParent_Done, |
| 5364 | /* 14315 */ // Label 367: @14315 |
| 5365 | /* 14315 */ GIM_Reject, |
| 5366 | /* 14316 */ // Label 354: @14316 |
| 5367 | /* 14316 */ GIM_Reject, |
| 5368 | /* 14317 */ // Label 325: @14317 |
| 5369 | /* 14317 */ GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(14429), |
| 5370 | /* 14322 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5371 | /* 14325 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 5372 | /* 14328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5373 | /* 14332 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5374 | /* 14336 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 369*/ GIMT_Encode4(14397), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1055 // |
| 5375 | /* 14343 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5376 | /* 14347 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5377 | /* 14351 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5378 | /* 14355 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 5379 | /* 14359 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5380 | /* 14364 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5381 | /* 14369 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5382 | /* 14371 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5383 | /* 14371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv2i32), |
| 5384 | /* 14374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5385 | /* 14376 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5386 | /* 14378 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5387 | /* 14382 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5388 | /* 14386 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5389 | /* 14389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5390 | /* 14395 */ GIR_RootConstrainSelectedInstOperands, |
| 5391 | /* 14396 */ // GIR_Coverage, 1055, |
| 5392 | /* 14396 */ GIR_EraseRootFromParent_Done, |
| 5393 | /* 14397 */ // Label 369: @14397 |
| 5394 | /* 14397 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 370*/ GIMT_Encode4(14428), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1124 // |
| 5395 | /* 14404 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5396 | /* 14408 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5397 | /* 14408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i32), |
| 5398 | /* 14411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5399 | /* 14413 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5400 | /* 14415 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5401 | /* 14417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5402 | /* 14420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5403 | /* 14426 */ GIR_RootConstrainSelectedInstOperands, |
| 5404 | /* 14427 */ // GIR_Coverage, 1124, |
| 5405 | /* 14427 */ GIR_EraseRootFromParent_Done, |
| 5406 | /* 14428 */ // Label 370: @14428 |
| 5407 | /* 14428 */ GIM_Reject, |
| 5408 | /* 14429 */ // Label 368: @14429 |
| 5409 | /* 14429 */ GIM_Reject, |
| 5410 | /* 14430 */ // Label 326: @14430 |
| 5411 | /* 14430 */ GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(15093), |
| 5412 | /* 14435 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 5413 | /* 14438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5414 | /* 14441 */ GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(15032), |
| 5415 | /* 14446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5416 | /* 14450 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 373*/ GIMT_Encode4(14517), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1144 // |
| 5417 | /* 14457 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5418 | /* 14461 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5419 | /* 14465 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5420 | /* 14469 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5421 | /* 14474 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5422 | /* 14478 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5423 | /* 14482 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5424 | /* 14486 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5425 | /* 14491 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5426 | /* 14493 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5427 | /* 14493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 5428 | /* 14496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5429 | /* 14498 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5430 | /* 14502 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5431 | /* 14506 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5432 | /* 14509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5433 | /* 14515 */ GIR_RootConstrainSelectedInstOperands, |
| 5434 | /* 14516 */ // GIR_Coverage, 1144, |
| 5435 | /* 14516 */ GIR_EraseRootFromParent_Done, |
| 5436 | /* 14517 */ // Label 373: @14517 |
| 5437 | /* 14517 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 374*/ GIMT_Encode4(14584), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1143 // |
| 5438 | /* 14524 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5439 | /* 14528 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5440 | /* 14532 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5441 | /* 14536 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5442 | /* 14541 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5443 | /* 14545 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5444 | /* 14549 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5445 | /* 14553 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5446 | /* 14558 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5447 | /* 14560 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5448 | /* 14560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 5449 | /* 14563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5450 | /* 14565 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5451 | /* 14569 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5452 | /* 14573 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5453 | /* 14576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5454 | /* 14582 */ GIR_RootConstrainSelectedInstOperands, |
| 5455 | /* 14583 */ // GIR_Coverage, 1143, |
| 5456 | /* 14583 */ GIR_EraseRootFromParent_Done, |
| 5457 | /* 14584 */ // Label 374: @14584 |
| 5458 | /* 14584 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 375*/ GIMT_Encode4(14651), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1135 // |
| 5459 | /* 14591 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5460 | /* 14595 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5461 | /* 14599 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5462 | /* 14603 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5463 | /* 14608 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5464 | /* 14612 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5465 | /* 14616 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5466 | /* 14620 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5467 | /* 14625 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5468 | /* 14627 */ // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5469 | /* 14627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv4i32), |
| 5470 | /* 14630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5471 | /* 14632 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5472 | /* 14636 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5473 | /* 14640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5474 | /* 14643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5475 | /* 14649 */ GIR_RootConstrainSelectedInstOperands, |
| 5476 | /* 14650 */ // GIR_Coverage, 1135, |
| 5477 | /* 14650 */ GIR_EraseRootFromParent_Done, |
| 5478 | /* 14651 */ // Label 375: @14651 |
| 5479 | /* 14651 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 376*/ GIMT_Encode4(14718), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1142 // |
| 5480 | /* 14658 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5481 | /* 14662 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5482 | /* 14666 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5483 | /* 14670 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5484 | /* 14675 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5485 | /* 14679 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5486 | /* 14683 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5487 | /* 14687 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5488 | /* 14692 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5489 | /* 14694 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5490 | /* 14694 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 5491 | /* 14697 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5492 | /* 14699 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5493 | /* 14703 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5494 | /* 14707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5495 | /* 14710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5496 | /* 14716 */ GIR_RootConstrainSelectedInstOperands, |
| 5497 | /* 14717 */ // GIR_Coverage, 1142, |
| 5498 | /* 14717 */ GIR_EraseRootFromParent_Done, |
| 5499 | /* 14718 */ // Label 376: @14718 |
| 5500 | /* 14718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 377*/ GIMT_Encode4(14785), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1141 // |
| 5501 | /* 14725 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5502 | /* 14729 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5503 | /* 14733 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5504 | /* 14737 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5505 | /* 14742 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5506 | /* 14746 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5507 | /* 14750 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5508 | /* 14754 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5509 | /* 14759 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5510 | /* 14761 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5511 | /* 14761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32), |
| 5512 | /* 14764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5513 | /* 14766 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5514 | /* 14770 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5515 | /* 14774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5516 | /* 14777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5517 | /* 14783 */ GIR_RootConstrainSelectedInstOperands, |
| 5518 | /* 14784 */ // GIR_Coverage, 1141, |
| 5519 | /* 14784 */ GIR_EraseRootFromParent_Done, |
| 5520 | /* 14785 */ // Label 377: @14785 |
| 5521 | /* 14785 */ GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(15031), |
| 5522 | /* 14790 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5523 | /* 14794 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 379*/ GIMT_Encode4(14855), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1058 // |
| 5524 | /* 14801 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5525 | /* 14805 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 5526 | /* 14809 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 5527 | /* 14813 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 5528 | /* 14817 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5529 | /* 14822 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5530 | /* 14827 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5531 | /* 14829 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 5532 | /* 14829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i32), |
| 5533 | /* 14832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5534 | /* 14834 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 5535 | /* 14836 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5536 | /* 14840 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 5537 | /* 14844 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5538 | /* 14847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5539 | /* 14853 */ GIR_RootConstrainSelectedInstOperands, |
| 5540 | /* 14854 */ // GIR_Coverage, 1058, |
| 5541 | /* 14854 */ GIR_EraseRootFromParent_Done, |
| 5542 | /* 14855 */ // Label 379: @14855 |
| 5543 | /* 14855 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 380*/ GIMT_Encode4(14903), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1155 // |
| 5544 | /* 14862 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5545 | /* 14866 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5546 | /* 14870 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5547 | /* 14874 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5548 | /* 14879 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5549 | /* 14881 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5550 | /* 14881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32), |
| 5551 | /* 14884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5552 | /* 14886 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5553 | /* 14888 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5554 | /* 14892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5555 | /* 14895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5556 | /* 14901 */ GIR_RootConstrainSelectedInstOperands, |
| 5557 | /* 14902 */ // GIR_Coverage, 1155, |
| 5558 | /* 14902 */ GIR_EraseRootFromParent_Done, |
| 5559 | /* 14903 */ // Label 380: @14903 |
| 5560 | /* 14903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 381*/ GIMT_Encode4(14951), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1150 // |
| 5561 | /* 14910 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5562 | /* 14914 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5563 | /* 14918 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5564 | /* 14922 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5565 | /* 14927 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5566 | /* 14929 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5567 | /* 14929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv4i32), |
| 5568 | /* 14932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5569 | /* 14934 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5570 | /* 14936 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5571 | /* 14940 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5572 | /* 14943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5573 | /* 14949 */ GIR_RootConstrainSelectedInstOperands, |
| 5574 | /* 14950 */ // GIR_Coverage, 1150, |
| 5575 | /* 14950 */ GIR_EraseRootFromParent_Done, |
| 5576 | /* 14951 */ // Label 381: @14951 |
| 5577 | /* 14951 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 382*/ GIMT_Encode4(14999), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1154 // |
| 5578 | /* 14958 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5579 | /* 14962 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5580 | /* 14966 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 5581 | /* 14970 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5582 | /* 14975 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5583 | /* 14977 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 5584 | /* 14977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32), |
| 5585 | /* 14980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5586 | /* 14982 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5587 | /* 14984 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5588 | /* 14988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5589 | /* 14991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5590 | /* 14997 */ GIR_RootConstrainSelectedInstOperands, |
| 5591 | /* 14998 */ // GIR_Coverage, 1154, |
| 5592 | /* 14998 */ GIR_EraseRootFromParent_Done, |
| 5593 | /* 14999 */ // Label 382: @14999 |
| 5594 | /* 14999 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 383*/ GIMT_Encode4(15030), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1127 // |
| 5595 | /* 15006 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5596 | /* 15010 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 5597 | /* 15010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i32), |
| 5598 | /* 15013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5599 | /* 15015 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5600 | /* 15017 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5601 | /* 15019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5602 | /* 15022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5603 | /* 15028 */ GIR_RootConstrainSelectedInstOperands, |
| 5604 | /* 15029 */ // GIR_Coverage, 1127, |
| 5605 | /* 15029 */ GIR_EraseRootFromParent_Done, |
| 5606 | /* 15030 */ // Label 383: @15030 |
| 5607 | /* 15030 */ GIM_Reject, |
| 5608 | /* 15031 */ // Label 378: @15031 |
| 5609 | /* 15031 */ GIM_Reject, |
| 5610 | /* 15032 */ // Label 372: @15032 |
| 5611 | /* 15032 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 384*/ GIMT_Encode4(15092), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3902 // |
| 5612 | /* 15039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5613 | /* 15043 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5614 | /* 15047 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 5615 | /* 15051 */ // (sub:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VSUBi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 5616 | /* 15051 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 5617 | /* 15054 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 5618 | /* 15058 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 5619 | /* 15063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi32), |
| 5620 | /* 15066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 5621 | /* 15068 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 5622 | /* 15070 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 5623 | /* 15072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 5624 | /* 15075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5625 | /* 15081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5626 | /* 15087 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5627 | /* 15090 */ GIR_RootConstrainSelectedInstOperands, |
| 5628 | /* 15091 */ // GIR_Coverage, 3902, |
| 5629 | /* 15091 */ GIR_EraseRootFromParent_Done, |
| 5630 | /* 15092 */ // Label 384: @15092 |
| 5631 | /* 15092 */ GIM_Reject, |
| 5632 | /* 15093 */ // Label 371: @15093 |
| 5633 | /* 15093 */ GIM_Reject, |
| 5634 | /* 15094 */ // Label 327: @15094 |
| 5635 | /* 15094 */ GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(15630), |
| 5636 | /* 15099 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 5637 | /* 15102 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 5638 | /* 15105 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5639 | /* 15109 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 386*/ GIMT_Encode4(15176), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1148 // |
| 5640 | /* 15116 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5641 | /* 15120 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5642 | /* 15124 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5643 | /* 15128 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5644 | /* 15133 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5645 | /* 15137 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5646 | /* 15141 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5647 | /* 15145 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5648 | /* 15150 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5649 | /* 15152 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5650 | /* 15152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 5651 | /* 15155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5652 | /* 15157 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5653 | /* 15161 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5654 | /* 15165 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5655 | /* 15168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5656 | /* 15174 */ GIR_RootConstrainSelectedInstOperands, |
| 5657 | /* 15175 */ // GIR_Coverage, 1148, |
| 5658 | /* 15175 */ GIR_EraseRootFromParent_Done, |
| 5659 | /* 15176 */ // Label 386: @15176 |
| 5660 | /* 15176 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 387*/ GIMT_Encode4(15243), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1147 // |
| 5661 | /* 15183 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5662 | /* 15187 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5663 | /* 15191 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5664 | /* 15195 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5665 | /* 15200 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5666 | /* 15204 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5667 | /* 15208 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5668 | /* 15212 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5669 | /* 15217 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5670 | /* 15219 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5671 | /* 15219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 5672 | /* 15222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5673 | /* 15224 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5674 | /* 15228 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5675 | /* 15232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5676 | /* 15235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5677 | /* 15241 */ GIR_RootConstrainSelectedInstOperands, |
| 5678 | /* 15242 */ // GIR_Coverage, 1147, |
| 5679 | /* 15242 */ GIR_EraseRootFromParent_Done, |
| 5680 | /* 15243 */ // Label 387: @15243 |
| 5681 | /* 15243 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 388*/ GIMT_Encode4(15310), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1136 // |
| 5682 | /* 15250 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5683 | /* 15254 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5684 | /* 15258 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5685 | /* 15262 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5686 | /* 15267 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5687 | /* 15271 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5688 | /* 15275 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5689 | /* 15279 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5690 | /* 15284 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5691 | /* 15286 */ // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5692 | /* 15286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv2i64), |
| 5693 | /* 15289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5694 | /* 15291 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5695 | /* 15295 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5696 | /* 15299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5697 | /* 15302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5698 | /* 15308 */ GIR_RootConstrainSelectedInstOperands, |
| 5699 | /* 15309 */ // GIR_Coverage, 1136, |
| 5700 | /* 15309 */ GIR_EraseRootFromParent_Done, |
| 5701 | /* 15310 */ // Label 388: @15310 |
| 5702 | /* 15310 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 389*/ GIMT_Encode4(15377), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1146 // |
| 5703 | /* 15317 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5704 | /* 15321 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5705 | /* 15325 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5706 | /* 15329 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5707 | /* 15334 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5708 | /* 15338 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5709 | /* 15342 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5710 | /* 15346 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5711 | /* 15351 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5712 | /* 15353 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5713 | /* 15353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 5714 | /* 15356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5715 | /* 15358 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5716 | /* 15362 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5717 | /* 15366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5718 | /* 15369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5719 | /* 15375 */ GIR_RootConstrainSelectedInstOperands, |
| 5720 | /* 15376 */ // GIR_Coverage, 1146, |
| 5721 | /* 15376 */ GIR_EraseRootFromParent_Done, |
| 5722 | /* 15377 */ // Label 389: @15377 |
| 5723 | /* 15377 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 390*/ GIMT_Encode4(15444), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1145 // |
| 5724 | /* 15384 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5725 | /* 15388 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5726 | /* 15392 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5727 | /* 15396 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5728 | /* 15401 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5729 | /* 15405 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5730 | /* 15409 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5731 | /* 15413 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5732 | /* 15418 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5733 | /* 15420 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5734 | /* 15420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64), |
| 5735 | /* 15423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5736 | /* 15425 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 5737 | /* 15429 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm |
| 5738 | /* 15433 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5739 | /* 15436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5740 | /* 15442 */ GIR_RootConstrainSelectedInstOperands, |
| 5741 | /* 15443 */ // GIR_Coverage, 1145, |
| 5742 | /* 15443 */ GIR_EraseRootFromParent_Done, |
| 5743 | /* 15444 */ // Label 390: @15444 |
| 5744 | /* 15444 */ GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(15629), |
| 5745 | /* 15449 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5746 | /* 15453 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 392*/ GIMT_Encode4(15501), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1157 // |
| 5747 | /* 15460 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5748 | /* 15464 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT), |
| 5749 | /* 15468 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5750 | /* 15472 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5751 | /* 15477 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5752 | /* 15479 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5753 | /* 15479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64), |
| 5754 | /* 15482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5755 | /* 15484 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5756 | /* 15486 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5757 | /* 15490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5758 | /* 15493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5759 | /* 15499 */ GIR_RootConstrainSelectedInstOperands, |
| 5760 | /* 15500 */ // GIR_Coverage, 1157, |
| 5761 | /* 15500 */ GIR_EraseRootFromParent_Done, |
| 5762 | /* 15501 */ // Label 392: @15501 |
| 5763 | /* 15501 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 393*/ GIMT_Encode4(15549), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1151 // |
| 5764 | /* 15508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5765 | /* 15512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT), |
| 5766 | /* 15516 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5767 | /* 15520 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5768 | /* 15525 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5769 | /* 15527 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5770 | /* 15527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv2i64), |
| 5771 | /* 15530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5772 | /* 15532 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5773 | /* 15534 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5774 | /* 15538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5775 | /* 15541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5776 | /* 15547 */ GIR_RootConstrainSelectedInstOperands, |
| 5777 | /* 15548 */ // GIR_Coverage, 1151, |
| 5778 | /* 15548 */ GIR_EraseRootFromParent_Done, |
| 5779 | /* 15549 */ // Label 393: @15549 |
| 5780 | /* 15549 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 394*/ GIMT_Encode4(15597), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1156 // |
| 5781 | /* 15556 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5782 | /* 15560 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT), |
| 5783 | /* 15564 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 5784 | /* 15568 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 5785 | /* 15573 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5786 | /* 15575 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 5787 | /* 15575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64), |
| 5788 | /* 15578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5789 | /* 15580 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5790 | /* 15582 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm |
| 5791 | /* 15586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5792 | /* 15589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5793 | /* 15595 */ GIR_RootConstrainSelectedInstOperands, |
| 5794 | /* 15596 */ // GIR_Coverage, 1156, |
| 5795 | /* 15596 */ GIR_EraseRootFromParent_Done, |
| 5796 | /* 15597 */ // Label 394: @15597 |
| 5797 | /* 15597 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 395*/ GIMT_Encode4(15628), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1129 // |
| 5798 | /* 15604 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 5799 | /* 15608 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 5800 | /* 15608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i64), |
| 5801 | /* 15611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 5802 | /* 15613 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 5803 | /* 15615 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 5804 | /* 15617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5805 | /* 15620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5806 | /* 15626 */ GIR_RootConstrainSelectedInstOperands, |
| 5807 | /* 15627 */ // GIR_Coverage, 1129, |
| 5808 | /* 15627 */ GIR_EraseRootFromParent_Done, |
| 5809 | /* 15628 */ // Label 395: @15628 |
| 5810 | /* 15628 */ GIM_Reject, |
| 5811 | /* 15629 */ // Label 391: @15629 |
| 5812 | /* 15629 */ GIM_Reject, |
| 5813 | /* 15630 */ // Label 385: @15630 |
| 5814 | /* 15630 */ GIM_Reject, |
| 5815 | /* 15631 */ // Label 328: @15631 |
| 5816 | /* 15631 */ GIM_Reject, |
| 5817 | /* 15632 */ // Label 2: @15632 |
| 5818 | /* 15632 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 403*/ GIMT_Encode4(17294), |
| 5819 | /* 15643 */ /*GILLT_s32*//*Label 396*/ GIMT_Encode4(15691), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 5820 | /* 15667 */ /*GILLT_v8s8*//*Label 397*/ GIMT_Encode4(16592), |
| 5821 | /* 15671 */ /*GILLT_v16s8*//*Label 398*/ GIMT_Encode4(16638), |
| 5822 | /* 15675 */ /*GILLT_v4s16*//*Label 399*/ GIMT_Encode4(16750), |
| 5823 | /* 15679 */ /*GILLT_v8s16*//*Label 400*/ GIMT_Encode4(16796), |
| 5824 | /* 15683 */ /*GILLT_v2s32*//*Label 401*/ GIMT_Encode4(17022), |
| 5825 | /* 15687 */ /*GILLT_v4s32*//*Label 402*/ GIMT_Encode4(17068), |
| 5826 | /* 15691 */ // Label 396: @15691 |
| 5827 | /* 15691 */ GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(16591), |
| 5828 | /* 15696 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 5829 | /* 15699 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 5830 | /* 15702 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 405*/ GIMT_Encode4(15789), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 185 // |
| 5831 | /* 15709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5832 | /* 15713 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5833 | /* 15717 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5834 | /* 15721 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5835 | /* 15725 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5836 | /* 15729 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5837 | /* 15734 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 5838 | /* 15738 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5839 | /* 15742 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5840 | /* 15746 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5841 | /* 15750 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5842 | /* 15754 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5843 | /* 15759 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 5844 | /* 15763 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5845 | /* 15765 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 5846 | /* 15765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT), |
| 5847 | /* 15768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5848 | /* 15770 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5849 | /* 15774 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5850 | /* 15778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5851 | /* 15781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5852 | /* 15787 */ GIR_RootConstrainSelectedInstOperands, |
| 5853 | /* 15788 */ // GIR_Coverage, 185, |
| 5854 | /* 15788 */ GIR_EraseRootFromParent_Done, |
| 5855 | /* 15789 */ // Label 405: @15789 |
| 5856 | /* 15789 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 406*/ GIMT_Encode4(15876), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 514 // |
| 5857 | /* 15796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5858 | /* 15800 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5859 | /* 15804 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5860 | /* 15808 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5861 | /* 15812 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5862 | /* 15816 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5863 | /* 15821 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 5864 | /* 15825 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5865 | /* 15829 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5866 | /* 15833 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5867 | /* 15837 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5868 | /* 15841 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5869 | /* 15846 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 5870 | /* 15850 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5871 | /* 15852 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 5872 | /* 15852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT), |
| 5873 | /* 15855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5874 | /* 15857 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5875 | /* 15861 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5876 | /* 15865 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5877 | /* 15868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5878 | /* 15874 */ GIR_RootConstrainSelectedInstOperands, |
| 5879 | /* 15875 */ // GIR_Coverage, 514, |
| 5880 | /* 15875 */ GIR_EraseRootFromParent_Done, |
| 5881 | /* 15876 */ // Label 406: @15876 |
| 5882 | /* 15876 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 407*/ GIMT_Encode4(15966), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 184 // |
| 5883 | /* 15883 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5884 | /* 15887 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5885 | /* 15891 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5886 | /* 15895 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5887 | /* 15899 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5888 | /* 15903 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5889 | /* 15908 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 5890 | /* 15912 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5891 | /* 15916 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5892 | /* 15920 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5893 | /* 15924 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5894 | /* 15929 */ // MIs[2] Operand 2 |
| 5895 | /* 15929 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 5896 | /* 15940 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5897 | /* 15942 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 5898 | /* 15942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB), |
| 5899 | /* 15945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5900 | /* 15947 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5901 | /* 15951 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5902 | /* 15955 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5903 | /* 15958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5904 | /* 15964 */ GIR_RootConstrainSelectedInstOperands, |
| 5905 | /* 15965 */ // GIR_Coverage, 184, |
| 5906 | /* 15965 */ GIR_EraseRootFromParent_Done, |
| 5907 | /* 15966 */ // Label 407: @15966 |
| 5908 | /* 15966 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 408*/ GIMT_Encode4(16056), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 513 // |
| 5909 | /* 15973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5910 | /* 15977 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5911 | /* 15981 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5912 | /* 15985 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5913 | /* 15989 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5914 | /* 15993 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5915 | /* 15998 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 5916 | /* 16002 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5917 | /* 16006 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5918 | /* 16010 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5919 | /* 16014 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5920 | /* 16019 */ // MIs[2] Operand 2 |
| 5921 | /* 16019 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 5922 | /* 16030 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5923 | /* 16032 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 5924 | /* 16032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB), |
| 5925 | /* 16035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5926 | /* 16037 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5927 | /* 16041 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5928 | /* 16045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5929 | /* 16048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5930 | /* 16054 */ GIR_RootConstrainSelectedInstOperands, |
| 5931 | /* 16055 */ // GIR_Coverage, 513, |
| 5932 | /* 16055 */ GIR_EraseRootFromParent_Done, |
| 5933 | /* 16056 */ // Label 408: @16056 |
| 5934 | /* 16056 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 409*/ GIMT_Encode4(16146), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 183 // |
| 5935 | /* 16063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5936 | /* 16067 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5937 | /* 16071 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5938 | /* 16075 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5939 | /* 16079 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5940 | /* 16084 */ // MIs[1] Operand 2 |
| 5941 | /* 16084 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 5942 | /* 16095 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5943 | /* 16099 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5944 | /* 16103 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5945 | /* 16107 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5946 | /* 16111 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5947 | /* 16116 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 5948 | /* 16120 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5949 | /* 16122 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 5950 | /* 16122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT), |
| 5951 | /* 16125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5952 | /* 16127 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5953 | /* 16131 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5954 | /* 16135 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5955 | /* 16138 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5956 | /* 16144 */ GIR_RootConstrainSelectedInstOperands, |
| 5957 | /* 16145 */ // GIR_Coverage, 183, |
| 5958 | /* 16145 */ GIR_EraseRootFromParent_Done, |
| 5959 | /* 16146 */ // Label 409: @16146 |
| 5960 | /* 16146 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 410*/ GIMT_Encode4(16236), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 512 // |
| 5961 | /* 16153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5962 | /* 16157 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5963 | /* 16161 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5964 | /* 16165 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5965 | /* 16169 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5966 | /* 16174 */ // MIs[1] Operand 2 |
| 5967 | /* 16174 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 5968 | /* 16185 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5969 | /* 16189 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 5970 | /* 16193 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5971 | /* 16197 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5972 | /* 16201 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 5973 | /* 16206 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 5974 | /* 16210 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 5975 | /* 16212 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 5976 | /* 16212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT), |
| 5977 | /* 16215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 5978 | /* 16217 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 5979 | /* 16221 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 5980 | /* 16225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 5981 | /* 16228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 5982 | /* 16234 */ GIR_RootConstrainSelectedInstOperands, |
| 5983 | /* 16235 */ // GIR_Coverage, 512, |
| 5984 | /* 16235 */ GIR_EraseRootFromParent_Done, |
| 5985 | /* 16236 */ // Label 410: @16236 |
| 5986 | /* 16236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 411*/ GIMT_Encode4(16329), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 182 // |
| 5987 | /* 16243 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5988 | /* 16247 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5989 | /* 16251 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5990 | /* 16255 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5991 | /* 16259 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5992 | /* 16264 */ // MIs[1] Operand 2 |
| 5993 | /* 16264 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 5994 | /* 16275 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5995 | /* 16279 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 5996 | /* 16283 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5997 | /* 16287 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 5998 | /* 16292 */ // MIs[2] Operand 2 |
| 5999 | /* 16292 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 6000 | /* 16303 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6001 | /* 16305 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6002 | /* 16305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB), |
| 6003 | /* 16308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6004 | /* 16310 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6005 | /* 16314 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6006 | /* 16318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6007 | /* 16321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6008 | /* 16327 */ GIR_RootConstrainSelectedInstOperands, |
| 6009 | /* 16328 */ // GIR_Coverage, 182, |
| 6010 | /* 16328 */ GIR_EraseRootFromParent_Done, |
| 6011 | /* 16329 */ // Label 411: @16329 |
| 6012 | /* 16329 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 412*/ GIMT_Encode4(16422), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 511 // |
| 6013 | /* 16336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6014 | /* 16340 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6015 | /* 16344 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6016 | /* 16348 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6017 | /* 16352 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6018 | /* 16357 */ // MIs[1] Operand 2 |
| 6019 | /* 16357 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 6020 | /* 16368 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6021 | /* 16372 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6022 | /* 16376 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 6023 | /* 16380 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6024 | /* 16385 */ // MIs[2] Operand 2 |
| 6025 | /* 16385 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 6026 | /* 16396 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6027 | /* 16398 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6028 | /* 16398 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB), |
| 6029 | /* 16401 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6030 | /* 16403 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 6031 | /* 16407 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 6032 | /* 16411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6033 | /* 16414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6034 | /* 16420 */ GIR_RootConstrainSelectedInstOperands, |
| 6035 | /* 16421 */ // GIR_Coverage, 511, |
| 6036 | /* 16421 */ GIR_EraseRootFromParent_Done, |
| 6037 | /* 16422 */ // Label 412: @16422 |
| 6038 | /* 16422 */ GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(16506), |
| 6039 | /* 16427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6040 | /* 16431 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6041 | /* 16435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6042 | /* 16439 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 414*/ GIMT_Encode4(16472), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 168 // |
| 6043 | /* 16446 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 6044 | /* 16446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MUL), |
| 6045 | /* 16449 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6046 | /* 16451 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6047 | /* 16453 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6048 | /* 16455 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6049 | /* 16458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6050 | /* 16464 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6051 | /* 16470 */ GIR_RootConstrainSelectedInstOperands, |
| 6052 | /* 16471 */ // GIR_Coverage, 168, |
| 6053 | /* 16471 */ GIR_EraseRootFromParent_Done, |
| 6054 | /* 16472 */ // Label 414: @16472 |
| 6055 | /* 16472 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 415*/ GIMT_Encode4(16505), GIMT_Encode2(GIFBS_IsARM_NoV6_UseMulOps), // Rule ID 169 // |
| 6056 | /* 16479 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 6057 | /* 16479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MULv5), |
| 6058 | /* 16482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6059 | /* 16484 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6060 | /* 16486 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6061 | /* 16488 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6062 | /* 16491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6063 | /* 16497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6064 | /* 16503 */ GIR_RootConstrainSelectedInstOperands, |
| 6065 | /* 16504 */ // GIR_Coverage, 169, |
| 6066 | /* 16504 */ GIR_EraseRootFromParent_Done, |
| 6067 | /* 16505 */ // Label 415: @16505 |
| 6068 | /* 16505 */ GIM_Reject, |
| 6069 | /* 16506 */ // Label 413: @16506 |
| 6070 | /* 16506 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 416*/ GIMT_Encode4(16551), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 322 // |
| 6071 | /* 16513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6072 | /* 16517 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6073 | /* 16521 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6074 | /* 16525 */ // (mul:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tMUL:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 6075 | /* 16525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMUL), |
| 6076 | /* 16528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6077 | /* 16530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 6078 | /* 16536 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6079 | /* 16538 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6080 | /* 16540 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6081 | /* 16543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6082 | /* 16549 */ GIR_RootConstrainSelectedInstOperands, |
| 6083 | /* 16550 */ // GIR_Coverage, 322, |
| 6084 | /* 16550 */ GIR_EraseRootFromParent_Done, |
| 6085 | /* 16551 */ // Label 416: @16551 |
| 6086 | /* 16551 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 417*/ GIMT_Encode4(16590), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 501 // |
| 6087 | /* 16558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6088 | /* 16562 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6089 | /* 16566 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6090 | /* 16570 */ // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6091 | /* 16570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MUL), |
| 6092 | /* 16573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6093 | /* 16575 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6094 | /* 16577 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6095 | /* 16579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6096 | /* 16582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6097 | /* 16588 */ GIR_RootConstrainSelectedInstOperands, |
| 6098 | /* 16589 */ // GIR_Coverage, 501, |
| 6099 | /* 16589 */ GIR_EraseRootFromParent_Done, |
| 6100 | /* 16590 */ // Label 417: @16590 |
| 6101 | /* 16590 */ GIM_Reject, |
| 6102 | /* 16591 */ // Label 404: @16591 |
| 6103 | /* 16591 */ GIM_Reject, |
| 6104 | /* 16592 */ // Label 397: @16592 |
| 6105 | /* 16592 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 418*/ GIMT_Encode4(16637), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 955 // |
| 6106 | /* 16599 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 6107 | /* 16602 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 6108 | /* 16605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6109 | /* 16609 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6110 | /* 16613 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6111 | /* 16617 */ // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 6112 | /* 16617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i8), |
| 6113 | /* 16620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6114 | /* 16622 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6115 | /* 16624 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6116 | /* 16626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6117 | /* 16629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6118 | /* 16635 */ GIR_RootConstrainSelectedInstOperands, |
| 6119 | /* 16636 */ // GIR_Coverage, 955, |
| 6120 | /* 16636 */ GIR_EraseRootFromParent_Done, |
| 6121 | /* 16637 */ // Label 418: @16637 |
| 6122 | /* 16637 */ GIM_Reject, |
| 6123 | /* 16638 */ // Label 398: @16638 |
| 6124 | /* 16638 */ GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(16749), |
| 6125 | /* 16643 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 6126 | /* 16646 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 6127 | /* 16649 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 420*/ GIMT_Encode4(16688), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 958 // |
| 6128 | /* 16656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6129 | /* 16660 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6130 | /* 16664 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6131 | /* 16668 */ // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 6132 | /* 16668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv16i8), |
| 6133 | /* 16671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6134 | /* 16673 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6135 | /* 16675 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6136 | /* 16677 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6137 | /* 16680 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6138 | /* 16686 */ GIR_RootConstrainSelectedInstOperands, |
| 6139 | /* 16687 */ // GIR_Coverage, 958, |
| 6140 | /* 16687 */ GIR_EraseRootFromParent_Done, |
| 6141 | /* 16688 */ // Label 420: @16688 |
| 6142 | /* 16688 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 421*/ GIMT_Encode4(16748), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3852 // |
| 6143 | /* 16695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6144 | /* 16699 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6145 | /* 16703 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6146 | /* 16707 */ // (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 6147 | /* 16707 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6148 | /* 16710 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6149 | /* 16714 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6150 | /* 16719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi8), |
| 6151 | /* 16722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6152 | /* 16724 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 6153 | /* 16726 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 6154 | /* 16728 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6155 | /* 16731 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6156 | /* 16737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6157 | /* 16743 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6158 | /* 16746 */ GIR_RootConstrainSelectedInstOperands, |
| 6159 | /* 16747 */ // GIR_Coverage, 3852, |
| 6160 | /* 16747 */ GIR_EraseRootFromParent_Done, |
| 6161 | /* 16748 */ // Label 421: @16748 |
| 6162 | /* 16748 */ GIM_Reject, |
| 6163 | /* 16749 */ // Label 419: @16749 |
| 6164 | /* 16749 */ GIM_Reject, |
| 6165 | /* 16750 */ // Label 399: @16750 |
| 6166 | /* 16750 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 422*/ GIMT_Encode4(16795), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 956 // |
| 6167 | /* 16757 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 6168 | /* 16760 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 6169 | /* 16763 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6170 | /* 16767 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6171 | /* 16771 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6172 | /* 16775 */ // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 6173 | /* 16775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i16), |
| 6174 | /* 16778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6175 | /* 16780 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6176 | /* 16782 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6177 | /* 16784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6178 | /* 16787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6179 | /* 16793 */ GIR_RootConstrainSelectedInstOperands, |
| 6180 | /* 16794 */ // GIR_Coverage, 956, |
| 6181 | /* 16794 */ GIR_EraseRootFromParent_Done, |
| 6182 | /* 16795 */ // Label 422: @16795 |
| 6183 | /* 16795 */ GIM_Reject, |
| 6184 | /* 16796 */ // Label 400: @16796 |
| 6185 | /* 16796 */ GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(17021), |
| 6186 | /* 16801 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 6187 | /* 16804 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 6188 | /* 16807 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 424*/ GIMT_Encode4(16921), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4928 // |
| 6189 | /* 16814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6190 | /* 16818 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6191 | /* 16822 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6192 | /* 16826 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 6193 | /* 16830 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6194 | /* 16835 */ // MIs[1] Operand 2 |
| 6195 | /* 16835 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8), |
| 6196 | /* 16846 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6197 | /* 16850 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6198 | /* 16854 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 6199 | /* 16858 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6200 | /* 16863 */ // MIs[2] Operand 2 |
| 6201 | /* 16863 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8), |
| 6202 | /* 16874 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6203 | /* 16876 */ // (mul:{ *:[v8i16] } (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, v8i8:{ *:[Other] }), (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src2, v8i8:{ *:[Other] })) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2) |
| 6204 | /* 16876 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6205 | /* 16879 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6206 | /* 16883 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6207 | /* 16888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8), |
| 6208 | /* 16891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6209 | /* 16893 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 6210 | /* 16897 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 6211 | /* 16901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6212 | /* 16904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6213 | /* 16910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6214 | /* 16916 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6215 | /* 16919 */ GIR_RootConstrainSelectedInstOperands, |
| 6216 | /* 16920 */ // GIR_Coverage, 4928, |
| 6217 | /* 16920 */ GIR_EraseRootFromParent_Done, |
| 6218 | /* 16921 */ // Label 424: @16921 |
| 6219 | /* 16921 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 425*/ GIMT_Encode4(16960), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 959 // |
| 6220 | /* 16928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6221 | /* 16932 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6222 | /* 16936 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6223 | /* 16940 */ // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 6224 | /* 16940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i16), |
| 6225 | /* 16943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6226 | /* 16945 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6227 | /* 16947 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6228 | /* 16949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6229 | /* 16952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6230 | /* 16958 */ GIR_RootConstrainSelectedInstOperands, |
| 6231 | /* 16959 */ // GIR_Coverage, 959, |
| 6232 | /* 16959 */ GIR_EraseRootFromParent_Done, |
| 6233 | /* 16960 */ // Label 425: @16960 |
| 6234 | /* 16960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 426*/ GIMT_Encode4(17020), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3856 // |
| 6235 | /* 16967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6236 | /* 16971 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6237 | /* 16975 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6238 | /* 16979 */ // (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 6239 | /* 16979 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6240 | /* 16982 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6241 | /* 16986 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6242 | /* 16991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi16), |
| 6243 | /* 16994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6244 | /* 16996 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 6245 | /* 16998 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 6246 | /* 17000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6247 | /* 17003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6248 | /* 17009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6249 | /* 17015 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6250 | /* 17018 */ GIR_RootConstrainSelectedInstOperands, |
| 6251 | /* 17019 */ // GIR_Coverage, 3856, |
| 6252 | /* 17019 */ GIR_EraseRootFromParent_Done, |
| 6253 | /* 17020 */ // Label 426: @17020 |
| 6254 | /* 17020 */ GIM_Reject, |
| 6255 | /* 17021 */ // Label 423: @17021 |
| 6256 | /* 17021 */ GIM_Reject, |
| 6257 | /* 17022 */ // Label 401: @17022 |
| 6258 | /* 17022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 427*/ GIMT_Encode4(17067), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 957 // |
| 6259 | /* 17029 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 6260 | /* 17032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 6261 | /* 17035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6262 | /* 17039 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6263 | /* 17043 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 6264 | /* 17047 */ // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 6265 | /* 17047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv2i32), |
| 6266 | /* 17050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6267 | /* 17052 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6268 | /* 17054 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6269 | /* 17056 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6270 | /* 17059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6271 | /* 17065 */ GIR_RootConstrainSelectedInstOperands, |
| 6272 | /* 17066 */ // GIR_Coverage, 957, |
| 6273 | /* 17066 */ GIR_EraseRootFromParent_Done, |
| 6274 | /* 17067 */ // Label 427: @17067 |
| 6275 | /* 17067 */ GIM_Reject, |
| 6276 | /* 17068 */ // Label 402: @17068 |
| 6277 | /* 17068 */ GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(17293), |
| 6278 | /* 17073 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 6279 | /* 17076 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 6280 | /* 17079 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 429*/ GIMT_Encode4(17193), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4923 // |
| 6281 | /* 17086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6282 | /* 17090 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6283 | /* 17094 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6284 | /* 17098 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 6285 | /* 17102 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6286 | /* 17107 */ // MIs[1] Operand 2 |
| 6287 | /* 17107 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16), |
| 6288 | /* 17118 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6289 | /* 17122 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG), |
| 6290 | /* 17126 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 6291 | /* 17130 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6292 | /* 17135 */ // MIs[2] Operand 2 |
| 6293 | /* 17135 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16), |
| 6294 | /* 17146 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6295 | /* 17148 */ // (mul:{ *:[v4i32] } (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, v4i16:{ *:[Other] }), (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src2, v4i16:{ *:[Other] })) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2) |
| 6296 | /* 17148 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6297 | /* 17151 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6298 | /* 17155 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6299 | /* 17160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16), |
| 6300 | /* 17163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6301 | /* 17165 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 6302 | /* 17169 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 6303 | /* 17173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6304 | /* 17176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6305 | /* 17182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6306 | /* 17188 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6307 | /* 17191 */ GIR_RootConstrainSelectedInstOperands, |
| 6308 | /* 17192 */ // GIR_Coverage, 4923, |
| 6309 | /* 17192 */ GIR_EraseRootFromParent_Done, |
| 6310 | /* 17193 */ // Label 429: @17193 |
| 6311 | /* 17193 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 430*/ GIMT_Encode4(17232), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 960 // |
| 6312 | /* 17200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6313 | /* 17204 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6314 | /* 17208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 6315 | /* 17212 */ // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 6316 | /* 17212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i32), |
| 6317 | /* 17215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 6318 | /* 17217 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 6319 | /* 17219 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 6320 | /* 17221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6321 | /* 17224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6322 | /* 17230 */ GIR_RootConstrainSelectedInstOperands, |
| 6323 | /* 17231 */ // GIR_Coverage, 960, |
| 6324 | /* 17231 */ GIR_EraseRootFromParent_Done, |
| 6325 | /* 17232 */ // Label 430: @17232 |
| 6326 | /* 17232 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 431*/ GIMT_Encode4(17292), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3860 // |
| 6327 | /* 17239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6328 | /* 17243 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6329 | /* 17247 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 6330 | /* 17251 */ // (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 6331 | /* 17251 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 6332 | /* 17254 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 6333 | /* 17258 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 6334 | /* 17263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi32), |
| 6335 | /* 17266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 6336 | /* 17268 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 6337 | /* 17270 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 6338 | /* 17272 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6339 | /* 17275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6340 | /* 17281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6341 | /* 17287 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6342 | /* 17290 */ GIR_RootConstrainSelectedInstOperands, |
| 6343 | /* 17291 */ // GIR_Coverage, 3860, |
| 6344 | /* 17291 */ GIR_EraseRootFromParent_Done, |
| 6345 | /* 17292 */ // Label 431: @17292 |
| 6346 | /* 17292 */ GIM_Reject, |
| 6347 | /* 17293 */ // Label 428: @17293 |
| 6348 | /* 17293 */ GIM_Reject, |
| 6349 | /* 17294 */ // Label 403: @17294 |
| 6350 | /* 17294 */ GIM_Reject, |
| 6351 | /* 17295 */ // Label 3: @17295 |
| 6352 | /* 17295 */ GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(17388), |
| 6353 | /* 17300 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 6354 | /* 17303 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 6355 | /* 17306 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6356 | /* 17309 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 433*/ GIMT_Encode4(17348), GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), // Rule ID 194 // |
| 6357 | /* 17316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6358 | /* 17320 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6359 | /* 17324 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6360 | /* 17328 */ // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6361 | /* 17328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SDIV), |
| 6362 | /* 17331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6363 | /* 17333 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6364 | /* 17335 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6365 | /* 17337 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6366 | /* 17340 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6367 | /* 17346 */ GIR_RootConstrainSelectedInstOperands, |
| 6368 | /* 17347 */ // GIR_Coverage, 194, |
| 6369 | /* 17347 */ GIR_EraseRootFromParent_Done, |
| 6370 | /* 17348 */ // Label 433: @17348 |
| 6371 | /* 17348 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 434*/ GIMT_Encode4(17387), GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), // Rule ID 531 // |
| 6372 | /* 17355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6373 | /* 17359 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6374 | /* 17363 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6375 | /* 17367 */ // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6376 | /* 17367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SDIV), |
| 6377 | /* 17370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6378 | /* 17372 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6379 | /* 17374 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6380 | /* 17376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6381 | /* 17379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6382 | /* 17385 */ GIR_RootConstrainSelectedInstOperands, |
| 6383 | /* 17386 */ // GIR_Coverage, 531, |
| 6384 | /* 17386 */ GIR_EraseRootFromParent_Done, |
| 6385 | /* 17387 */ // Label 434: @17387 |
| 6386 | /* 17387 */ GIM_Reject, |
| 6387 | /* 17388 */ // Label 432: @17388 |
| 6388 | /* 17388 */ GIM_Reject, |
| 6389 | /* 17389 */ // Label 4: @17389 |
| 6390 | /* 17389 */ GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(17482), |
| 6391 | /* 17394 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 6392 | /* 17397 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 6393 | /* 17400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6394 | /* 17403 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 436*/ GIMT_Encode4(17442), GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), // Rule ID 195 // |
| 6395 | /* 17410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6396 | /* 17414 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6397 | /* 17418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6398 | /* 17422 */ // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6399 | /* 17422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDIV), |
| 6400 | /* 17425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6401 | /* 17427 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6402 | /* 17429 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6403 | /* 17431 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6404 | /* 17434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6405 | /* 17440 */ GIR_RootConstrainSelectedInstOperands, |
| 6406 | /* 17441 */ // GIR_Coverage, 195, |
| 6407 | /* 17441 */ GIR_EraseRootFromParent_Done, |
| 6408 | /* 17442 */ // Label 436: @17442 |
| 6409 | /* 17442 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 437*/ GIMT_Encode4(17481), GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), // Rule ID 532 // |
| 6410 | /* 17449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6411 | /* 17453 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6412 | /* 17457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6413 | /* 17461 */ // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6414 | /* 17461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDIV), |
| 6415 | /* 17464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6416 | /* 17466 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6417 | /* 17468 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 6418 | /* 17470 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6419 | /* 17473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6420 | /* 17479 */ GIR_RootConstrainSelectedInstOperands, |
| 6421 | /* 17480 */ // GIR_Coverage, 532, |
| 6422 | /* 17480 */ GIR_EraseRootFromParent_Done, |
| 6423 | /* 17481 */ // Label 437: @17481 |
| 6424 | /* 17481 */ GIM_Reject, |
| 6425 | /* 17482 */ // Label 435: @17482 |
| 6426 | /* 17482 */ GIM_Reject, |
| 6427 | /* 17483 */ // Label 5: @17483 |
| 6428 | /* 17483 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 451*/ GIMT_Encode4(20582), |
| 6429 | /* 17494 */ /*GILLT_s32*//*Label 438*/ GIMT_Encode4(17546), |
| 6430 | /* 17498 */ /*GILLT_s64*//*Label 439*/ GIMT_Encode4(19482), |
| 6431 | /* 17502 */ /*GILLT_v2s1*//*Label 440*/ GIMT_Encode4(19528), |
| 6432 | /* 17506 */ /*GILLT_v4s1*//*Label 441*/ GIMT_Encode4(19645), |
| 6433 | /* 17510 */ /*GILLT_v8s1*//*Label 442*/ GIMT_Encode4(19762), |
| 6434 | /* 17514 */ /*GILLT_v16s1*//*Label 443*/ GIMT_Encode4(19879), |
| 6435 | /* 17518 */ /*GILLT_v8s8*//*Label 444*/ GIMT_Encode4(19996), |
| 6436 | /* 17522 */ /*GILLT_v16s8*//*Label 445*/ GIMT_Encode4(20042), |
| 6437 | /* 17526 */ /*GILLT_v4s16*//*Label 446*/ GIMT_Encode4(20154), |
| 6438 | /* 17530 */ /*GILLT_v8s16*//*Label 447*/ GIMT_Encode4(20200), |
| 6439 | /* 17534 */ /*GILLT_v2s32*//*Label 448*/ GIMT_Encode4(20312), |
| 6440 | /* 17538 */ /*GILLT_v4s32*//*Label 449*/ GIMT_Encode4(20358), |
| 6441 | /* 17542 */ /*GILLT_v2s64*//*Label 450*/ GIMT_Encode4(20470), |
| 6442 | /* 17546 */ // Label 438: @17546 |
| 6443 | /* 17546 */ GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(19481), |
| 6444 | /* 17551 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 6445 | /* 17554 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 6446 | /* 17557 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 453*/ GIMT_Encode4(17629), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2043 // |
| 6447 | /* 17564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6448 | /* 17568 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6449 | /* 17572 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 6450 | /* 17576 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6451 | /* 17580 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6452 | /* 17584 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6453 | /* 17589 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8, |
| 6454 | /* 17593 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 6455 | /* 17604 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6456 | /* 17606 */ // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] }) |
| 6457 | /* 17606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), |
| 6458 | /* 17609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6459 | /* 17611 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src |
| 6460 | /* 17615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 6461 | /* 17618 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6462 | /* 17621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6463 | /* 17627 */ GIR_RootConstrainSelectedInstOperands, |
| 6464 | /* 17628 */ // GIR_Coverage, 2043, |
| 6465 | /* 17628 */ GIR_EraseRootFromParent_Done, |
| 6466 | /* 17629 */ // Label 453: @17629 |
| 6467 | /* 17629 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 454*/ GIMT_Encode4(17701), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2306 // |
| 6468 | /* 17636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6469 | /* 17640 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6470 | /* 17644 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 6471 | /* 17648 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6472 | /* 17652 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6473 | /* 17656 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6474 | /* 17661 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8, |
| 6475 | /* 17665 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 6476 | /* 17676 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6477 | /* 17678 */ // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] }) |
| 6478 | /* 17678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), |
| 6479 | /* 17681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6480 | /* 17683 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src |
| 6481 | /* 17687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 6482 | /* 17690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6483 | /* 17693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6484 | /* 17699 */ GIR_RootConstrainSelectedInstOperands, |
| 6485 | /* 17700 */ // GIR_Coverage, 2306, |
| 6486 | /* 17700 */ GIR_EraseRootFromParent_Done, |
| 6487 | /* 17701 */ // Label 454: @17701 |
| 6488 | /* 17701 */ GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(17832), |
| 6489 | /* 17706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 6490 | /* 17710 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6491 | /* 17714 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 456*/ GIMT_Encode4(17753), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2190 // |
| 6492 | /* 17721 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), |
| 6493 | /* 17732 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] }) => (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 6494 | /* 17732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB), |
| 6495 | /* 17735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6496 | /* 17737 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 6497 | /* 17739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6498 | /* 17742 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6499 | /* 17745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6500 | /* 17751 */ GIR_RootConstrainSelectedInstOperands, |
| 6501 | /* 17752 */ // GIR_Coverage, 2190, |
| 6502 | /* 17752 */ GIR_EraseRootFromParent_Done, |
| 6503 | /* 17753 */ // Label 456: @17753 |
| 6504 | /* 17753 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 457*/ GIMT_Encode4(17792), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2191 // |
| 6505 | /* 17760 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 6506 | /* 17771 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] }) => (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 6507 | /* 17771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTH), |
| 6508 | /* 17774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6509 | /* 17776 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 6510 | /* 17778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6511 | /* 17781 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6512 | /* 17784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6513 | /* 17790 */ GIR_RootConstrainSelectedInstOperands, |
| 6514 | /* 17791 */ // GIR_Coverage, 2191, |
| 6515 | /* 17791 */ GIR_EraseRootFromParent_Done, |
| 6516 | /* 17792 */ // Label 457: @17792 |
| 6517 | /* 17792 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 458*/ GIMT_Encode4(17831), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2192 // |
| 6518 | /* 17799 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 6519 | /* 17810 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 6520 | /* 17810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), |
| 6521 | /* 17813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6522 | /* 17815 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 6523 | /* 17817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6524 | /* 17820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6525 | /* 17823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6526 | /* 17829 */ GIR_RootConstrainSelectedInstOperands, |
| 6527 | /* 17830 */ // GIR_Coverage, 2192, |
| 6528 | /* 17830 */ GIR_EraseRootFromParent_Done, |
| 6529 | /* 17831 */ // Label 458: @17831 |
| 6530 | /* 17831 */ GIM_Reject, |
| 6531 | /* 17832 */ // Label 455: @17832 |
| 6532 | /* 17832 */ GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(17963), |
| 6533 | /* 17837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6534 | /* 17841 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6535 | /* 17845 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 460*/ GIMT_Encode4(17884), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2433 // |
| 6536 | /* 17852 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), |
| 6537 | /* 17863 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 6538 | /* 17863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB), |
| 6539 | /* 17866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6540 | /* 17868 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 6541 | /* 17870 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6542 | /* 17873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6543 | /* 17876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6544 | /* 17882 */ GIR_RootConstrainSelectedInstOperands, |
| 6545 | /* 17883 */ // GIR_Coverage, 2433, |
| 6546 | /* 17883 */ GIR_EraseRootFromParent_Done, |
| 6547 | /* 17884 */ // Label 460: @17884 |
| 6548 | /* 17884 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 461*/ GIMT_Encode4(17923), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2434 // |
| 6549 | /* 17891 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 6550 | /* 17902 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 6551 | /* 17902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTH), |
| 6552 | /* 17905 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6553 | /* 17907 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 6554 | /* 17909 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6555 | /* 17912 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6556 | /* 17915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6557 | /* 17921 */ GIR_RootConstrainSelectedInstOperands, |
| 6558 | /* 17922 */ // GIR_Coverage, 2434, |
| 6559 | /* 17922 */ GIR_EraseRootFromParent_Done, |
| 6560 | /* 17923 */ // Label 461: @17923 |
| 6561 | /* 17923 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 462*/ GIMT_Encode4(17962), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2435 // |
| 6562 | /* 17930 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935), |
| 6563 | /* 17941 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 6564 | /* 17941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), |
| 6565 | /* 17944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6566 | /* 17946 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 6567 | /* 17948 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 6568 | /* 17951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6569 | /* 17954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6570 | /* 17960 */ GIR_RootConstrainSelectedInstOperands, |
| 6571 | /* 17961 */ // GIR_Coverage, 2435, |
| 6572 | /* 17961 */ GIR_EraseRootFromParent_Done, |
| 6573 | /* 17962 */ // Label 462: @17962 |
| 6574 | /* 17962 */ GIM_Reject, |
| 6575 | /* 17963 */ // Label 459: @17963 |
| 6576 | /* 17963 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 463*/ GIMT_Encode4(18039), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5965 // |
| 6577 | /* 17970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6578 | /* 17974 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6579 | /* 17978 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6580 | /* 17982 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6581 | /* 17986 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6582 | /* 17990 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 6583 | /* 17994 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6584 | /* 17998 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6585 | /* 18002 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6586 | /* 18006 */ // MIs[2] Operand 1 |
| 6587 | /* 18006 */ // No operand predicates |
| 6588 | /* 18006 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6589 | /* 18010 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6590 | /* 18012 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6591 | /* 18012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6592 | /* 18015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6593 | /* 18017 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6594 | /* 18019 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6595 | /* 18022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6596 | /* 18025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6597 | /* 18031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6598 | /* 18037 */ GIR_RootConstrainSelectedInstOperands, |
| 6599 | /* 18038 */ // GIR_Coverage, 5965, |
| 6600 | /* 18038 */ GIR_EraseRootFromParent_Done, |
| 6601 | /* 18039 */ // Label 463: @18039 |
| 6602 | /* 18039 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 464*/ GIMT_Encode4(18115), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 5996 // |
| 6603 | /* 18046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6604 | /* 18050 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6605 | /* 18054 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6606 | /* 18058 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6607 | /* 18062 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6608 | /* 18066 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 6609 | /* 18070 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6610 | /* 18074 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6611 | /* 18078 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6612 | /* 18082 */ // MIs[2] Operand 1 |
| 6613 | /* 18082 */ // No operand predicates |
| 6614 | /* 18082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6615 | /* 18086 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6616 | /* 18088 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6617 | /* 18088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 6618 | /* 18091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6619 | /* 18093 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6620 | /* 18095 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6621 | /* 18098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6622 | /* 18101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6623 | /* 18107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6624 | /* 18113 */ GIR_RootConstrainSelectedInstOperands, |
| 6625 | /* 18114 */ // GIR_Coverage, 5996, |
| 6626 | /* 18114 */ GIR_EraseRootFromParent_Done, |
| 6627 | /* 18115 */ // Label 464: @18115 |
| 6628 | /* 18115 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 465*/ GIMT_Encode4(18191), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5964 // |
| 6629 | /* 18122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6630 | /* 18126 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6631 | /* 18130 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6632 | /* 18134 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6633 | /* 18138 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6634 | /* 18142 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6635 | /* 18146 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6636 | /* 18150 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6637 | /* 18154 */ // MIs[2] Operand 1 |
| 6638 | /* 18154 */ // No operand predicates |
| 6639 | /* 18154 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6640 | /* 18158 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6641 | /* 18162 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6642 | /* 18164 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6643 | /* 18164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6644 | /* 18167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6645 | /* 18169 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6646 | /* 18171 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6647 | /* 18174 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6648 | /* 18177 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6649 | /* 18183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6650 | /* 18189 */ GIR_RootConstrainSelectedInstOperands, |
| 6651 | /* 18190 */ // GIR_Coverage, 5964, |
| 6652 | /* 18190 */ GIR_EraseRootFromParent_Done, |
| 6653 | /* 18191 */ // Label 465: @18191 |
| 6654 | /* 18191 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 466*/ GIMT_Encode4(18267), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 5995 // |
| 6655 | /* 18198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6656 | /* 18202 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6657 | /* 18206 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6658 | /* 18210 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6659 | /* 18214 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6660 | /* 18218 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6661 | /* 18222 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6662 | /* 18226 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6663 | /* 18230 */ // MIs[2] Operand 1 |
| 6664 | /* 18230 */ // No operand predicates |
| 6665 | /* 18230 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6666 | /* 18234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6667 | /* 18238 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6668 | /* 18240 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6669 | /* 18240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 6670 | /* 18243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6671 | /* 18245 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6672 | /* 18247 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6673 | /* 18250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6674 | /* 18253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6675 | /* 18259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6676 | /* 18265 */ GIR_RootConstrainSelectedInstOperands, |
| 6677 | /* 18266 */ // GIR_Coverage, 5995, |
| 6678 | /* 18266 */ GIR_EraseRootFromParent_Done, |
| 6679 | /* 18267 */ // Label 466: @18267 |
| 6680 | /* 18267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 467*/ GIMT_Encode4(18343), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5963 // |
| 6681 | /* 18274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6682 | /* 18278 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6683 | /* 18282 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6684 | /* 18286 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6685 | /* 18290 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6686 | /* 18294 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6687 | /* 18298 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 6688 | /* 18302 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6689 | /* 18306 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6690 | /* 18310 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6691 | /* 18314 */ // MIs[2] Operand 1 |
| 6692 | /* 18314 */ // No operand predicates |
| 6693 | /* 18314 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6694 | /* 18316 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6695 | /* 18316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6696 | /* 18319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6697 | /* 18321 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6698 | /* 18323 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6699 | /* 18326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6700 | /* 18329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6701 | /* 18335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6702 | /* 18341 */ GIR_RootConstrainSelectedInstOperands, |
| 6703 | /* 18342 */ // GIR_Coverage, 5963, |
| 6704 | /* 18342 */ GIR_EraseRootFromParent_Done, |
| 6705 | /* 18343 */ // Label 467: @18343 |
| 6706 | /* 18343 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 468*/ GIMT_Encode4(18419), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 5994 // |
| 6707 | /* 18350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6708 | /* 18354 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6709 | /* 18358 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6710 | /* 18362 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6711 | /* 18366 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6712 | /* 18370 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6713 | /* 18374 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 6714 | /* 18378 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6715 | /* 18382 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6716 | /* 18386 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6717 | /* 18390 */ // MIs[2] Operand 1 |
| 6718 | /* 18390 */ // No operand predicates |
| 6719 | /* 18390 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6720 | /* 18392 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6721 | /* 18392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 6722 | /* 18395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6723 | /* 18397 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6724 | /* 18399 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6725 | /* 18402 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6726 | /* 18405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6727 | /* 18411 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6728 | /* 18417 */ GIR_RootConstrainSelectedInstOperands, |
| 6729 | /* 18418 */ // GIR_Coverage, 5994, |
| 6730 | /* 18418 */ GIR_EraseRootFromParent_Done, |
| 6731 | /* 18419 */ // Label 468: @18419 |
| 6732 | /* 18419 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 469*/ GIMT_Encode4(18495), GIMT_Encode2(GIFBS_IsARM), // Rule ID 158 // |
| 6733 | /* 18426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6734 | /* 18430 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6735 | /* 18434 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6736 | /* 18438 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6737 | /* 18442 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6738 | /* 18446 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6739 | /* 18450 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6740 | /* 18454 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6741 | /* 18458 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6742 | /* 18462 */ // MIs[2] Operand 1 |
| 6743 | /* 18462 */ // No operand predicates |
| 6744 | /* 18462 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6745 | /* 18466 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6746 | /* 18468 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] })) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6747 | /* 18468 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6748 | /* 18471 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6749 | /* 18473 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6750 | /* 18475 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6751 | /* 18478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6752 | /* 18481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6753 | /* 18487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6754 | /* 18493 */ GIR_RootConstrainSelectedInstOperands, |
| 6755 | /* 18494 */ // GIR_Coverage, 158, |
| 6756 | /* 18494 */ GIR_EraseRootFromParent_Done, |
| 6757 | /* 18495 */ // Label 469: @18495 |
| 6758 | /* 18495 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 470*/ GIMT_Encode4(18571), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 489 // |
| 6759 | /* 18502 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6760 | /* 18506 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6761 | /* 18510 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6762 | /* 18514 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6763 | /* 18518 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6764 | /* 18522 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6765 | /* 18526 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6766 | /* 18530 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6767 | /* 18534 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6768 | /* 18538 */ // MIs[2] Operand 1 |
| 6769 | /* 18538 */ // No operand predicates |
| 6770 | /* 18538 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6771 | /* 18542 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 6772 | /* 18544 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6773 | /* 18544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri), |
| 6774 | /* 18547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6775 | /* 18549 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6776 | /* 18551 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 6777 | /* 18554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6778 | /* 18557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6779 | /* 18563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6780 | /* 18569 */ GIR_RootConstrainSelectedInstOperands, |
| 6781 | /* 18570 */ // GIR_Coverage, 489, |
| 6782 | /* 18570 */ GIR_EraseRootFromParent_Done, |
| 6783 | /* 18571 */ // Label 470: @18571 |
| 6784 | /* 18571 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 471*/ GIMT_Encode4(18641), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5966 // |
| 6785 | /* 18578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6786 | /* 18582 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6787 | /* 18586 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6788 | /* 18590 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6789 | /* 18594 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6790 | /* 18598 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6791 | /* 18603 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6792 | /* 18607 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6793 | /* 18611 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6794 | /* 18613 */ // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6795 | /* 18613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr), |
| 6796 | /* 18616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6797 | /* 18618 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6798 | /* 18620 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6799 | /* 18624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6800 | /* 18627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6801 | /* 18633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6802 | /* 18639 */ GIR_RootConstrainSelectedInstOperands, |
| 6803 | /* 18640 */ // GIR_Coverage, 5966, |
| 6804 | /* 18640 */ GIR_EraseRootFromParent_Done, |
| 6805 | /* 18641 */ // Label 471: @18641 |
| 6806 | /* 18641 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 472*/ GIMT_Encode4(18711), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 5986 // |
| 6807 | /* 18648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6808 | /* 18652 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6809 | /* 18656 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6810 | /* 18660 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6811 | /* 18664 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6812 | /* 18668 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6813 | /* 18673 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6814 | /* 18677 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6815 | /* 18681 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6816 | /* 18683 */ // (and:{ *:[i32] } (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), tGPR:{ *:[i32] }:$Rn) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 6817 | /* 18683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC), |
| 6818 | /* 18686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 6819 | /* 18688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 6820 | /* 18694 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6821 | /* 18696 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6822 | /* 18700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6823 | /* 18703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6824 | /* 18709 */ GIR_RootConstrainSelectedInstOperands, |
| 6825 | /* 18710 */ // GIR_Coverage, 5986, |
| 6826 | /* 18710 */ GIR_EraseRootFromParent_Done, |
| 6827 | /* 18711 */ // Label 472: @18711 |
| 6828 | /* 18711 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 473*/ GIMT_Encode4(18781), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 5997 // |
| 6829 | /* 18718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6830 | /* 18722 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6831 | /* 18726 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6832 | /* 18730 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6833 | /* 18734 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6834 | /* 18738 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6835 | /* 18743 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6836 | /* 18747 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6837 | /* 18751 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6838 | /* 18753 */ // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6839 | /* 18753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr), |
| 6840 | /* 18756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6841 | /* 18758 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 6842 | /* 18760 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6843 | /* 18764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6844 | /* 18767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6845 | /* 18773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6846 | /* 18779 */ GIR_RootConstrainSelectedInstOperands, |
| 6847 | /* 18780 */ // GIR_Coverage, 5997, |
| 6848 | /* 18780 */ GIR_EraseRootFromParent_Done, |
| 6849 | /* 18781 */ // Label 473: @18781 |
| 6850 | /* 18781 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 474*/ GIMT_Encode4(18851), GIMT_Encode2(GIFBS_IsARM), // Rule ID 159 // |
| 6851 | /* 18788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6852 | /* 18792 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6853 | /* 18796 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6854 | /* 18800 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6855 | /* 18804 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6856 | /* 18808 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6857 | /* 18812 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6858 | /* 18817 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6859 | /* 18821 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6860 | /* 18823 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 6861 | /* 18823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr), |
| 6862 | /* 18826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6863 | /* 18828 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6864 | /* 18830 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6865 | /* 18834 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6866 | /* 18837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6867 | /* 18843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6868 | /* 18849 */ GIR_RootConstrainSelectedInstOperands, |
| 6869 | /* 18850 */ // GIR_Coverage, 159, |
| 6870 | /* 18850 */ GIR_EraseRootFromParent_Done, |
| 6871 | /* 18851 */ // Label 474: @18851 |
| 6872 | /* 18851 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 475*/ GIMT_Encode4(18921), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 312 // |
| 6873 | /* 18858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6874 | /* 18862 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6875 | /* 18866 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6876 | /* 18870 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6877 | /* 18874 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6878 | /* 18878 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6879 | /* 18882 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6880 | /* 18887 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6881 | /* 18891 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6882 | /* 18893 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 6883 | /* 18893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC), |
| 6884 | /* 18896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 6885 | /* 18898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 6886 | /* 18904 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6887 | /* 18906 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6888 | /* 18910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6889 | /* 18913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6890 | /* 18919 */ GIR_RootConstrainSelectedInstOperands, |
| 6891 | /* 18920 */ // GIR_Coverage, 312, |
| 6892 | /* 18920 */ GIR_EraseRootFromParent_Done, |
| 6893 | /* 18921 */ // Label 475: @18921 |
| 6894 | /* 18921 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 476*/ GIMT_Encode4(18991), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 490 // |
| 6895 | /* 18928 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6896 | /* 18932 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6897 | /* 18936 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6898 | /* 18940 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6899 | /* 18944 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 6900 | /* 18948 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 6901 | /* 18952 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6902 | /* 18957 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 6903 | /* 18961 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6904 | /* 18963 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 6905 | /* 18963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr), |
| 6906 | /* 18966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6907 | /* 18968 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6908 | /* 18970 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 6909 | /* 18974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6910 | /* 18977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6911 | /* 18983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6912 | /* 18989 */ GIR_RootConstrainSelectedInstOperands, |
| 6913 | /* 18990 */ // GIR_Coverage, 490, |
| 6914 | /* 18990 */ GIR_EraseRootFromParent_Done, |
| 6915 | /* 18991 */ // Label 476: @18991 |
| 6916 | /* 18991 */ GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(19077), |
| 6917 | /* 18996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6918 | /* 19000 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 6919 | /* 19004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 478*/ GIMT_Encode4(19040), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 344 // |
| 6920 | /* 19011 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255), |
| 6921 | /* 19022 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 6922 | /* 19022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTB), |
| 6923 | /* 19025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6924 | /* 19027 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 6925 | /* 19029 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6926 | /* 19032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6927 | /* 19038 */ GIR_RootConstrainSelectedInstOperands, |
| 6928 | /* 19039 */ // GIR_Coverage, 344, |
| 6929 | /* 19039 */ GIR_EraseRootFromParent_Done, |
| 6930 | /* 19040 */ // Label 478: @19040 |
| 6931 | /* 19040 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 479*/ GIMT_Encode4(19076), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 345 // |
| 6932 | /* 19047 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535), |
| 6933 | /* 19058 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 6934 | /* 19058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTH), |
| 6935 | /* 19061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6936 | /* 19063 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 6937 | /* 19065 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6938 | /* 19068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6939 | /* 19074 */ GIR_RootConstrainSelectedInstOperands, |
| 6940 | /* 19075 */ // GIR_Coverage, 345, |
| 6941 | /* 19075 */ GIR_EraseRootFromParent_Done, |
| 6942 | /* 19076 */ // Label 479: @19076 |
| 6943 | /* 19076 */ GIM_Reject, |
| 6944 | /* 19077 */ // Label 477: @19077 |
| 6945 | /* 19077 */ GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(19189), |
| 6946 | /* 19082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6947 | /* 19086 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 6948 | /* 19090 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 481*/ GIMT_Encode4(19140), GIMT_Encode2(GIFBS_IsARM), // Rule ID 2082 // |
| 6949 | /* 19097 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6950 | /* 19101 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6951 | /* 19105 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not), |
| 6952 | /* 19109 */ // MIs[1] Operand 1 |
| 6953 | /* 19109 */ // No operand predicates |
| 6954 | /* 19109 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6955 | /* 19111 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>>:$imm)) |
| 6956 | /* 19111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri), |
| 6957 | /* 19114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6958 | /* 19116 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 6959 | /* 19118 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm |
| 6960 | /* 19123 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6961 | /* 19126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6962 | /* 19132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6963 | /* 19138 */ GIR_RootConstrainSelectedInstOperands, |
| 6964 | /* 19139 */ // GIR_Coverage, 2082, |
| 6965 | /* 19139 */ GIR_EraseRootFromParent_Done, |
| 6966 | /* 19140 */ // Label 481: @19140 |
| 6967 | /* 19140 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 482*/ GIMT_Encode4(19188), GIMT_Encode2(GIFBS_IsARM), // Rule ID 146 // |
| 6968 | /* 19147 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6969 | /* 19151 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6970 | /* 19155 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 6971 | /* 19159 */ // MIs[1] Operand 1 |
| 6972 | /* 19159 */ // No operand predicates |
| 6973 | /* 19159 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6974 | /* 19161 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6975 | /* 19161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDri), |
| 6976 | /* 19164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 6977 | /* 19166 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 6978 | /* 19168 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 6979 | /* 19171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 6980 | /* 19174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6981 | /* 19180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 6982 | /* 19186 */ GIR_RootConstrainSelectedInstOperands, |
| 6983 | /* 19187 */ // GIR_Coverage, 146, |
| 6984 | /* 19187 */ GIR_EraseRootFromParent_Done, |
| 6985 | /* 19188 */ // Label 482: @19188 |
| 6986 | /* 19188 */ GIM_Reject, |
| 6987 | /* 19189 */ // Label 480: @19189 |
| 6988 | /* 19189 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 483*/ GIMT_Encode4(19245), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 480 // |
| 6989 | /* 19196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6990 | /* 19200 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 6991 | /* 19204 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 6992 | /* 19208 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 6993 | /* 19212 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 6994 | /* 19216 */ // MIs[1] Operand 1 |
| 6995 | /* 19216 */ // No operand predicates |
| 6996 | /* 19216 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 6997 | /* 19218 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 6998 | /* 19218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDri), |
| 6999 | /* 19221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7000 | /* 19223 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7001 | /* 19225 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 7002 | /* 19228 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7003 | /* 19231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7004 | /* 19237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7005 | /* 19243 */ GIR_RootConstrainSelectedInstOperands, |
| 7006 | /* 19244 */ // GIR_Coverage, 480, |
| 7007 | /* 19244 */ GIR_EraseRootFromParent_Done, |
| 7008 | /* 19245 */ // Label 483: @19245 |
| 7009 | /* 19245 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 484*/ GIMT_Encode4(19295), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 162 // |
| 7010 | /* 19252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7011 | /* 19256 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7012 | /* 19260 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7013 | /* 19264 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7014 | /* 19268 */ // MIs[1] Operand 1 |
| 7015 | /* 19268 */ // No operand predicates |
| 7016 | /* 19268 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm), |
| 7017 | /* 19272 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7018 | /* 19274 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm) |
| 7019 | /* 19274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BFC), |
| 7020 | /* 19277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7021 | /* 19279 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 7022 | /* 19281 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 7023 | /* 19284 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7024 | /* 19287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7025 | /* 19293 */ GIR_RootConstrainSelectedInstOperands, |
| 7026 | /* 19294 */ // GIR_Coverage, 162, |
| 7027 | /* 19294 */ GIR_EraseRootFromParent_Done, |
| 7028 | /* 19295 */ // Label 484: @19295 |
| 7029 | /* 19295 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 485*/ GIMT_Encode4(19345), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 492 // |
| 7030 | /* 19302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7031 | /* 19306 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7032 | /* 19310 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 7033 | /* 19314 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7034 | /* 19318 */ // MIs[1] Operand 1 |
| 7035 | /* 19318 */ // No operand predicates |
| 7036 | /* 19318 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm), |
| 7037 | /* 19322 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 7038 | /* 19324 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm) |
| 7039 | /* 19324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BFC), |
| 7040 | /* 19327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7041 | /* 19329 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 7042 | /* 19331 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 7043 | /* 19334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7044 | /* 19337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7045 | /* 19343 */ GIR_RootConstrainSelectedInstOperands, |
| 7046 | /* 19344 */ // GIR_Coverage, 492, |
| 7047 | /* 19344 */ GIR_EraseRootFromParent_Done, |
| 7048 | /* 19345 */ // Label 485: @19345 |
| 7049 | /* 19345 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 486*/ GIMT_Encode4(19390), GIMT_Encode2(GIFBS_IsARM), // Rule ID 147 // |
| 7050 | /* 19352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7051 | /* 19356 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7052 | /* 19360 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7053 | /* 19364 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 7054 | /* 19364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDrr), |
| 7055 | /* 19367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7056 | /* 19369 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7057 | /* 19371 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 7058 | /* 19373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7059 | /* 19376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7060 | /* 19382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7061 | /* 19388 */ GIR_RootConstrainSelectedInstOperands, |
| 7062 | /* 19389 */ // GIR_Coverage, 147, |
| 7063 | /* 19389 */ GIR_EraseRootFromParent_Done, |
| 7064 | /* 19390 */ // Label 486: @19390 |
| 7065 | /* 19390 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 487*/ GIMT_Encode4(19435), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 309 // |
| 7066 | /* 19397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7067 | /* 19401 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7068 | /* 19405 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 7069 | /* 19409 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tAND:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 7070 | /* 19409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tAND), |
| 7071 | /* 19412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 7072 | /* 19414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 7073 | /* 19420 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7074 | /* 19422 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 7075 | /* 19424 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7076 | /* 19427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7077 | /* 19433 */ GIR_RootConstrainSelectedInstOperands, |
| 7078 | /* 19434 */ // GIR_Coverage, 309, |
| 7079 | /* 19434 */ GIR_EraseRootFromParent_Done, |
| 7080 | /* 19435 */ // Label 487: @19435 |
| 7081 | /* 19435 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 488*/ GIMT_Encode4(19480), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 481 // |
| 7082 | /* 19442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7083 | /* 19446 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7084 | /* 19450 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7085 | /* 19454 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 7086 | /* 19454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 7087 | /* 19457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7088 | /* 19459 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 7089 | /* 19461 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 7090 | /* 19463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7091 | /* 19466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7092 | /* 19472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7093 | /* 19478 */ GIR_RootConstrainSelectedInstOperands, |
| 7094 | /* 19479 */ // GIR_Coverage, 481, |
| 7095 | /* 19479 */ GIR_EraseRootFromParent_Done, |
| 7096 | /* 19480 */ // Label 488: @19480 |
| 7097 | /* 19480 */ GIM_Reject, |
| 7098 | /* 19481 */ // Label 452: @19481 |
| 7099 | /* 19481 */ GIM_Reject, |
| 7100 | /* 19482 */ // Label 439: @19482 |
| 7101 | /* 19482 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 489*/ GIMT_Encode4(19527), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2912 // |
| 7102 | /* 19489 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 7103 | /* 19492 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 7104 | /* 19495 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7105 | /* 19499 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7106 | /* 19503 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7107 | /* 19507 */ // (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VANDd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) |
| 7108 | /* 19507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 7109 | /* 19510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7110 | /* 19512 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7111 | /* 19514 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7112 | /* 19516 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7113 | /* 19519 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7114 | /* 19525 */ GIR_RootConstrainSelectedInstOperands, |
| 7115 | /* 19526 */ // GIR_Coverage, 2912, |
| 7116 | /* 19526 */ GIR_EraseRootFromParent_Done, |
| 7117 | /* 19527 */ // Label 489: @19527 |
| 7118 | /* 19527 */ GIM_Reject, |
| 7119 | /* 19528 */ // Label 440: @19528 |
| 7120 | /* 19528 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 490*/ GIMT_Encode4(19644), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2014 // |
| 7121 | /* 19535 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, |
| 7122 | /* 19538 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, |
| 7123 | /* 19541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7124 | /* 19545 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7125 | /* 19549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7126 | /* 19553 */ // (and:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7127 | /* 19553 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7128 | /* 19556 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7129 | /* 19560 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7130 | /* 19565 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7131 | /* 19569 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7132 | /* 19574 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7133 | /* 19577 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7134 | /* 19581 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7135 | /* 19586 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7136 | /* 19590 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7137 | /* 19595 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7138 | /* 19598 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 7139 | /* 19602 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7140 | /* 19607 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7141 | /* 19610 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7142 | /* 19613 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7143 | /* 19616 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7144 | /* 19622 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7145 | /* 19628 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7146 | /* 19630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7147 | /* 19633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7148 | /* 19635 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7149 | /* 19638 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7150 | /* 19643 */ // GIR_Coverage, 2014, |
| 7151 | /* 19643 */ GIR_EraseRootFromParent_Done, |
| 7152 | /* 19644 */ // Label 490: @19644 |
| 7153 | /* 19644 */ GIM_Reject, |
| 7154 | /* 19645 */ // Label 441: @19645 |
| 7155 | /* 19645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 491*/ GIMT_Encode4(19761), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2015 // |
| 7156 | /* 19652 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, |
| 7157 | /* 19655 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, |
| 7158 | /* 19658 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7159 | /* 19662 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7160 | /* 19666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7161 | /* 19670 */ // (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7162 | /* 19670 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7163 | /* 19673 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7164 | /* 19677 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7165 | /* 19682 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7166 | /* 19686 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7167 | /* 19691 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7168 | /* 19694 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7169 | /* 19698 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7170 | /* 19703 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7171 | /* 19707 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7172 | /* 19712 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7173 | /* 19715 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 7174 | /* 19719 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7175 | /* 19724 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7176 | /* 19727 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7177 | /* 19730 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7178 | /* 19733 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7179 | /* 19739 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7180 | /* 19745 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7181 | /* 19747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7182 | /* 19750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7183 | /* 19752 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7184 | /* 19755 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7185 | /* 19760 */ // GIR_Coverage, 2015, |
| 7186 | /* 19760 */ GIR_EraseRootFromParent_Done, |
| 7187 | /* 19761 */ // Label 491: @19761 |
| 7188 | /* 19761 */ GIM_Reject, |
| 7189 | /* 19762 */ // Label 442: @19762 |
| 7190 | /* 19762 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 492*/ GIMT_Encode4(19878), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2016 // |
| 7191 | /* 19769 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, |
| 7192 | /* 19772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, |
| 7193 | /* 19775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7194 | /* 19779 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7195 | /* 19783 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7196 | /* 19787 */ // (and:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7197 | /* 19787 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7198 | /* 19790 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7199 | /* 19794 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7200 | /* 19799 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7201 | /* 19803 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7202 | /* 19808 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7203 | /* 19811 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7204 | /* 19815 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7205 | /* 19820 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7206 | /* 19824 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7207 | /* 19829 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7208 | /* 19832 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 7209 | /* 19836 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7210 | /* 19841 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7211 | /* 19844 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7212 | /* 19847 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7213 | /* 19850 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7214 | /* 19856 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7215 | /* 19862 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7216 | /* 19864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7217 | /* 19867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7218 | /* 19869 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7219 | /* 19872 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7220 | /* 19877 */ // GIR_Coverage, 2016, |
| 7221 | /* 19877 */ GIR_EraseRootFromParent_Done, |
| 7222 | /* 19878 */ // Label 492: @19878 |
| 7223 | /* 19878 */ GIM_Reject, |
| 7224 | /* 19879 */ // Label 443: @19879 |
| 7225 | /* 19879 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 493*/ GIMT_Encode4(19995), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2017 // |
| 7226 | /* 19886 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, |
| 7227 | /* 19889 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, |
| 7228 | /* 19892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7229 | /* 19896 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7230 | /* 19900 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 7231 | /* 19904 */ // (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 7232 | /* 19904 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7233 | /* 19907 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7234 | /* 19911 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7235 | /* 19916 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 7236 | /* 19920 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7237 | /* 19925 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 7238 | /* 19928 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7239 | /* 19932 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7240 | /* 19937 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 7241 | /* 19941 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 7242 | /* 19946 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 7243 | /* 19949 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr), |
| 7244 | /* 19953 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7245 | /* 19958 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7246 | /* 19961 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 7247 | /* 19964 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 7248 | /* 19967 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7249 | /* 19973 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7250 | /* 19979 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7251 | /* 19981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7252 | /* 19984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7253 | /* 19986 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7254 | /* 19989 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 7255 | /* 19994 */ // GIR_Coverage, 2017, |
| 7256 | /* 19994 */ GIR_EraseRootFromParent_Done, |
| 7257 | /* 19995 */ // Label 493: @19995 |
| 7258 | /* 19995 */ GIM_Reject, |
| 7259 | /* 19996 */ // Label 444: @19996 |
| 7260 | /* 19996 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 494*/ GIMT_Encode4(20041), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2910 // |
| 7261 | /* 20003 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 7262 | /* 20006 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 7263 | /* 20009 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7264 | /* 20013 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7265 | /* 20017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7266 | /* 20021 */ // (and:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VANDd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) |
| 7267 | /* 20021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 7268 | /* 20024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7269 | /* 20026 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7270 | /* 20028 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7271 | /* 20030 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7272 | /* 20033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7273 | /* 20039 */ GIR_RootConstrainSelectedInstOperands, |
| 7274 | /* 20040 */ // GIR_Coverage, 2910, |
| 7275 | /* 20040 */ GIR_EraseRootFromParent_Done, |
| 7276 | /* 20041 */ // Label 494: @20041 |
| 7277 | /* 20041 */ GIM_Reject, |
| 7278 | /* 20042 */ // Label 445: @20042 |
| 7279 | /* 20042 */ GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(20153), |
| 7280 | /* 20047 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 7281 | /* 20050 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 7282 | /* 20053 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 496*/ GIMT_Encode4(20092), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2913 // |
| 7283 | /* 20060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7284 | /* 20064 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7285 | /* 20068 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7286 | /* 20072 */ // (and:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VANDq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) |
| 7287 | /* 20072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 7288 | /* 20075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7289 | /* 20077 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7290 | /* 20079 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7291 | /* 20081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7292 | /* 20084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7293 | /* 20090 */ GIR_RootConstrainSelectedInstOperands, |
| 7294 | /* 20091 */ // GIR_Coverage, 2913, |
| 7295 | /* 20091 */ GIR_EraseRootFromParent_Done, |
| 7296 | /* 20092 */ // Label 496: @20092 |
| 7297 | /* 20092 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 497*/ GIMT_Encode4(20152), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3752 // |
| 7298 | /* 20099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7299 | /* 20103 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7300 | /* 20107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7301 | /* 20111 */ // (and:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VAND:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 7302 | /* 20111 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7303 | /* 20114 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7304 | /* 20118 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7305 | /* 20123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 7306 | /* 20126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7307 | /* 20128 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7308 | /* 20130 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7309 | /* 20132 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7310 | /* 20135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7311 | /* 20141 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7312 | /* 20147 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7313 | /* 20150 */ GIR_RootConstrainSelectedInstOperands, |
| 7314 | /* 20151 */ // GIR_Coverage, 3752, |
| 7315 | /* 20151 */ GIR_EraseRootFromParent_Done, |
| 7316 | /* 20152 */ // Label 497: @20152 |
| 7317 | /* 20152 */ GIM_Reject, |
| 7318 | /* 20153 */ // Label 495: @20153 |
| 7319 | /* 20153 */ GIM_Reject, |
| 7320 | /* 20154 */ // Label 446: @20154 |
| 7321 | /* 20154 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 498*/ GIMT_Encode4(20199), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2911 // |
| 7322 | /* 20161 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 7323 | /* 20164 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 7324 | /* 20167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7325 | /* 20171 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7326 | /* 20175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7327 | /* 20179 */ // (and:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VANDd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) |
| 7328 | /* 20179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 7329 | /* 20182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7330 | /* 20184 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7331 | /* 20186 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7332 | /* 20188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7333 | /* 20191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7334 | /* 20197 */ GIR_RootConstrainSelectedInstOperands, |
| 7335 | /* 20198 */ // GIR_Coverage, 2911, |
| 7336 | /* 20198 */ GIR_EraseRootFromParent_Done, |
| 7337 | /* 20199 */ // Label 498: @20199 |
| 7338 | /* 20199 */ GIM_Reject, |
| 7339 | /* 20200 */ // Label 447: @20200 |
| 7340 | /* 20200 */ GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(20311), |
| 7341 | /* 20205 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 7342 | /* 20208 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 7343 | /* 20211 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 500*/ GIMT_Encode4(20250), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2914 // |
| 7344 | /* 20218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7345 | /* 20222 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7346 | /* 20226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7347 | /* 20230 */ // (and:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VANDq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) |
| 7348 | /* 20230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 7349 | /* 20233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7350 | /* 20235 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7351 | /* 20237 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7352 | /* 20239 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7353 | /* 20242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7354 | /* 20248 */ GIR_RootConstrainSelectedInstOperands, |
| 7355 | /* 20249 */ // GIR_Coverage, 2914, |
| 7356 | /* 20249 */ GIR_EraseRootFromParent_Done, |
| 7357 | /* 20250 */ // Label 500: @20250 |
| 7358 | /* 20250 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 501*/ GIMT_Encode4(20310), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3756 // |
| 7359 | /* 20257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7360 | /* 20261 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7361 | /* 20265 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7362 | /* 20269 */ // (and:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VAND:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 7363 | /* 20269 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7364 | /* 20272 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7365 | /* 20276 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7366 | /* 20281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 7367 | /* 20284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7368 | /* 20286 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7369 | /* 20288 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7370 | /* 20290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7371 | /* 20293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7372 | /* 20299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7373 | /* 20305 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7374 | /* 20308 */ GIR_RootConstrainSelectedInstOperands, |
| 7375 | /* 20309 */ // GIR_Coverage, 3756, |
| 7376 | /* 20309 */ GIR_EraseRootFromParent_Done, |
| 7377 | /* 20310 */ // Label 501: @20310 |
| 7378 | /* 20310 */ GIM_Reject, |
| 7379 | /* 20311 */ // Label 499: @20311 |
| 7380 | /* 20311 */ GIM_Reject, |
| 7381 | /* 20312 */ // Label 448: @20312 |
| 7382 | /* 20312 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 502*/ GIMT_Encode4(20357), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1295 // |
| 7383 | /* 20319 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 7384 | /* 20322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 7385 | /* 20325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7386 | /* 20329 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7387 | /* 20333 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 7388 | /* 20337 */ // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 7389 | /* 20337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd), |
| 7390 | /* 20340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7391 | /* 20342 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 7392 | /* 20344 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 7393 | /* 20346 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7394 | /* 20349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7395 | /* 20355 */ GIR_RootConstrainSelectedInstOperands, |
| 7396 | /* 20356 */ // GIR_Coverage, 1295, |
| 7397 | /* 20356 */ GIR_EraseRootFromParent_Done, |
| 7398 | /* 20357 */ // Label 502: @20357 |
| 7399 | /* 20357 */ GIM_Reject, |
| 7400 | /* 20358 */ // Label 449: @20358 |
| 7401 | /* 20358 */ GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(20469), |
| 7402 | /* 20363 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 7403 | /* 20366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 7404 | /* 20369 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 504*/ GIMT_Encode4(20408), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1296 // |
| 7405 | /* 20376 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7406 | /* 20380 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7407 | /* 20384 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7408 | /* 20388 */ // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 7409 | /* 20388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 7410 | /* 20391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7411 | /* 20393 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 7412 | /* 20395 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 7413 | /* 20397 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7414 | /* 20400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7415 | /* 20406 */ GIR_RootConstrainSelectedInstOperands, |
| 7416 | /* 20407 */ // GIR_Coverage, 1296, |
| 7417 | /* 20407 */ GIR_EraseRootFromParent_Done, |
| 7418 | /* 20408 */ // Label 504: @20408 |
| 7419 | /* 20408 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 505*/ GIMT_Encode4(20468), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3760 // |
| 7420 | /* 20415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7421 | /* 20419 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7422 | /* 20423 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7423 | /* 20427 */ // (and:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VAND:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 7424 | /* 20427 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7425 | /* 20430 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7426 | /* 20434 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7427 | /* 20439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 7428 | /* 20442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7429 | /* 20444 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7430 | /* 20446 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7431 | /* 20448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7432 | /* 20451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7433 | /* 20457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7434 | /* 20463 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7435 | /* 20466 */ GIR_RootConstrainSelectedInstOperands, |
| 7436 | /* 20467 */ // GIR_Coverage, 3760, |
| 7437 | /* 20467 */ GIR_EraseRootFromParent_Done, |
| 7438 | /* 20468 */ // Label 505: @20468 |
| 7439 | /* 20468 */ GIM_Reject, |
| 7440 | /* 20469 */ // Label 503: @20469 |
| 7441 | /* 20469 */ GIM_Reject, |
| 7442 | /* 20470 */ // Label 450: @20470 |
| 7443 | /* 20470 */ GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(20581), |
| 7444 | /* 20475 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 7445 | /* 20478 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 7446 | /* 20481 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 507*/ GIMT_Encode4(20520), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2915 // |
| 7447 | /* 20488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7448 | /* 20492 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7449 | /* 20496 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 7450 | /* 20500 */ // (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VANDq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) |
| 7451 | /* 20500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq), |
| 7452 | /* 20503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 7453 | /* 20505 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 7454 | /* 20507 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 7455 | /* 20509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7456 | /* 20512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7457 | /* 20518 */ GIR_RootConstrainSelectedInstOperands, |
| 7458 | /* 20519 */ // GIR_Coverage, 2915, |
| 7459 | /* 20519 */ GIR_EraseRootFromParent_Done, |
| 7460 | /* 20520 */ // Label 507: @20520 |
| 7461 | /* 20520 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 508*/ GIMT_Encode4(20580), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3764 // |
| 7462 | /* 20527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7463 | /* 20531 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7464 | /* 20535 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 7465 | /* 20539 */ // (and:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VAND:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) |
| 7466 | /* 20539 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 7467 | /* 20542 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 7468 | /* 20546 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 7469 | /* 20551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND), |
| 7470 | /* 20554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 7471 | /* 20556 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 7472 | /* 20558 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 7473 | /* 20560 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 7474 | /* 20563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7475 | /* 20569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7476 | /* 20575 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7477 | /* 20578 */ GIR_RootConstrainSelectedInstOperands, |
| 7478 | /* 20579 */ // GIR_Coverage, 3764, |
| 7479 | /* 20579 */ GIR_EraseRootFromParent_Done, |
| 7480 | /* 20580 */ // Label 508: @20580 |
| 7481 | /* 20580 */ GIM_Reject, |
| 7482 | /* 20581 */ // Label 506: @20581 |
| 7483 | /* 20581 */ GIM_Reject, |
| 7484 | /* 20582 */ // Label 451: @20582 |
| 7485 | /* 20582 */ GIM_Reject, |
| 7486 | /* 20583 */ // Label 6: @20583 |
| 7487 | /* 20583 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 522*/ GIMT_Encode4(26308), |
| 7488 | /* 20594 */ /*GILLT_s32*//*Label 509*/ GIMT_Encode4(20646), |
| 7489 | /* 20598 */ /*GILLT_s64*//*Label 510*/ GIMT_Encode4(25208), |
| 7490 | /* 20602 */ /*GILLT_v2s1*//*Label 511*/ GIMT_Encode4(25254), |
| 7491 | /* 20606 */ /*GILLT_v4s1*//*Label 512*/ GIMT_Encode4(25371), |
| 7492 | /* 20610 */ /*GILLT_v8s1*//*Label 513*/ GIMT_Encode4(25488), |
| 7493 | /* 20614 */ /*GILLT_v16s1*//*Label 514*/ GIMT_Encode4(25605), |
| 7494 | /* 20618 */ /*GILLT_v8s8*//*Label 515*/ GIMT_Encode4(25722), |
| 7495 | /* 20622 */ /*GILLT_v16s8*//*Label 516*/ GIMT_Encode4(25768), |
| 7496 | /* 20626 */ /*GILLT_v4s16*//*Label 517*/ GIMT_Encode4(25880), |
| 7497 | /* 20630 */ /*GILLT_v8s16*//*Label 518*/ GIMT_Encode4(25926), |
| 7498 | /* 20634 */ /*GILLT_v2s32*//*Label 519*/ GIMT_Encode4(26038), |
| 7499 | /* 20638 */ /*GILLT_v4s32*//*Label 520*/ GIMT_Encode4(26084), |
| 7500 | /* 20642 */ /*GILLT_v2s64*//*Label 521*/ GIMT_Encode4(26196), |
| 7501 | /* 20646 */ // Label 509: @20646 |
| 7502 | /* 20646 */ GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(25207), |
| 7503 | /* 20651 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 7504 | /* 20654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 7505 | /* 20657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 524*/ GIMT_Encode4(20783), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6246 // |
| 7506 | /* 20664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7507 | /* 20668 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7508 | /* 20672 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7509 | /* 20676 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7510 | /* 20680 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7511 | /* 20684 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7512 | /* 20688 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7513 | /* 20692 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7514 | /* 20696 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7515 | /* 20700 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7516 | /* 20705 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8, |
| 7517 | /* 20709 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 7518 | /* 20720 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7519 | /* 20724 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7520 | /* 20728 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7521 | /* 20732 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7522 | /* 20736 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 7523 | /* 20740 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7524 | /* 20744 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7525 | /* 20748 */ // MIs[4] Rm |
| 7526 | /* 20748 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7527 | /* 20753 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 7528 | /* 20757 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 7529 | /* 20761 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7530 | /* 20763 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 7531 | /* 20763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), |
| 7532 | /* 20766 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7533 | /* 20768 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7534 | /* 20772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7535 | /* 20775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7536 | /* 20781 */ GIR_RootConstrainSelectedInstOperands, |
| 7537 | /* 20782 */ // GIR_Coverage, 6246, |
| 7538 | /* 20782 */ GIR_EraseRootFromParent_Done, |
| 7539 | /* 20783 */ // Label 524: @20783 |
| 7540 | /* 20783 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 525*/ GIMT_Encode4(20909), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6292 // |
| 7541 | /* 20790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7542 | /* 20794 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7543 | /* 20798 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7544 | /* 20802 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7545 | /* 20806 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7546 | /* 20810 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7547 | /* 20814 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7548 | /* 20818 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7549 | /* 20822 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7550 | /* 20826 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7551 | /* 20831 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8, |
| 7552 | /* 20835 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255), |
| 7553 | /* 20846 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7554 | /* 20850 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7555 | /* 20854 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7556 | /* 20858 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7557 | /* 20862 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 7558 | /* 20866 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7559 | /* 20870 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7560 | /* 20874 */ // MIs[4] Rm |
| 7561 | /* 20874 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7562 | /* 20879 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24, |
| 7563 | /* 20883 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 7564 | /* 20887 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7565 | /* 20889 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 7566 | /* 20889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), |
| 7567 | /* 20892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7568 | /* 20894 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7569 | /* 20898 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7570 | /* 20901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7571 | /* 20907 */ GIR_RootConstrainSelectedInstOperands, |
| 7572 | /* 20908 */ // GIR_Coverage, 6292, |
| 7573 | /* 20908 */ GIR_EraseRootFromParent_Done, |
| 7574 | /* 20909 */ // Label 525: @20909 |
| 7575 | /* 20909 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 526*/ GIMT_Encode4(21035), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2102 // |
| 7576 | /* 20916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7577 | /* 20920 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7578 | /* 20924 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7579 | /* 20928 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7580 | /* 20932 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7581 | /* 20936 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7582 | /* 20940 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7583 | /* 20944 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7584 | /* 20948 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7585 | /* 20952 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 7586 | /* 20957 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 7587 | /* 20961 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 7588 | /* 20965 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7589 | /* 20969 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7590 | /* 20973 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7591 | /* 20977 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7592 | /* 20981 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 7593 | /* 20985 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7594 | /* 20989 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7595 | /* 20993 */ // MIs[4] Rm |
| 7596 | /* 20993 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7597 | /* 20998 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 7598 | /* 21002 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255), |
| 7599 | /* 21013 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7600 | /* 21015 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 7601 | /* 21015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), |
| 7602 | /* 21018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7603 | /* 21020 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7604 | /* 21024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7605 | /* 21027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7606 | /* 21033 */ GIR_RootConstrainSelectedInstOperands, |
| 7607 | /* 21034 */ // GIR_Coverage, 2102, |
| 7608 | /* 21034 */ GIR_EraseRootFromParent_Done, |
| 7609 | /* 21035 */ // Label 526: @21035 |
| 7610 | /* 21035 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 527*/ GIMT_Encode4(21161), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2390 // |
| 7611 | /* 21042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7612 | /* 21046 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7613 | /* 21050 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7614 | /* 21054 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7615 | /* 21058 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7616 | /* 21062 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7617 | /* 21066 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7618 | /* 21070 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7619 | /* 21074 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7620 | /* 21078 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7621 | /* 21083 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24, |
| 7622 | /* 21087 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 7623 | /* 21091 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7624 | /* 21095 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7625 | /* 21099 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7626 | /* 21103 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7627 | /* 21107 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 7628 | /* 21111 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7629 | /* 21115 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7630 | /* 21119 */ // MIs[4] Rm |
| 7631 | /* 21119 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7632 | /* 21124 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8, |
| 7633 | /* 21128 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255), |
| 7634 | /* 21139 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7635 | /* 21141 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 7636 | /* 21141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), |
| 7637 | /* 21144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7638 | /* 21146 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7639 | /* 21150 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7640 | /* 21153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7641 | /* 21159 */ GIR_RootConstrainSelectedInstOperands, |
| 7642 | /* 21160 */ // GIR_Coverage, 2390, |
| 7643 | /* 21160 */ GIR_EraseRootFromParent_Done, |
| 7644 | /* 21161 */ // Label 527: @21161 |
| 7645 | /* 21161 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 528*/ GIMT_Encode4(21293), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 5979 // |
| 7646 | /* 21168 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7647 | /* 21172 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7648 | /* 21176 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7649 | /* 21180 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7650 | /* 21184 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7651 | /* 21188 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7652 | /* 21192 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7653 | /* 21196 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7654 | /* 21200 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7655 | /* 21204 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7656 | /* 21209 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7657 | /* 21213 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7658 | /* 21217 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 7659 | /* 21221 */ // MIs[3] Operand 1 |
| 7660 | /* 21221 */ // No operand predicates |
| 7661 | /* 21221 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7662 | /* 21232 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7663 | /* 21236 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7664 | /* 21240 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7665 | /* 21244 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7666 | /* 21248 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7667 | /* 21253 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 7668 | /* 21264 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7669 | /* 21266 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7670 | /* 21266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7671 | /* 21269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7672 | /* 21271 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 7673 | /* 21275 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7674 | /* 21279 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7675 | /* 21282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7676 | /* 21285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7677 | /* 21291 */ GIR_RootConstrainSelectedInstOperands, |
| 7678 | /* 21292 */ // GIR_Coverage, 5979, |
| 7679 | /* 21292 */ GIR_EraseRootFromParent_Done, |
| 7680 | /* 21293 */ // Label 528: @21293 |
| 7681 | /* 21293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 529*/ GIMT_Encode4(21425), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6014 // |
| 7682 | /* 21300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7683 | /* 21304 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7684 | /* 21308 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7685 | /* 21312 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7686 | /* 21316 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7687 | /* 21320 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7688 | /* 21324 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7689 | /* 21328 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7690 | /* 21332 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7691 | /* 21336 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7692 | /* 21341 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7693 | /* 21345 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7694 | /* 21349 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 7695 | /* 21353 */ // MIs[3] Operand 1 |
| 7696 | /* 21353 */ // No operand predicates |
| 7697 | /* 21353 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7698 | /* 21364 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7699 | /* 21368 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7700 | /* 21372 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7701 | /* 21376 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7702 | /* 21380 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7703 | /* 21385 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 7704 | /* 21396 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7705 | /* 21398 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7706 | /* 21398 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 7707 | /* 21401 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7708 | /* 21403 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 7709 | /* 21407 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7710 | /* 21411 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7711 | /* 21414 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7712 | /* 21417 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7713 | /* 21423 */ GIR_RootConstrainSelectedInstOperands, |
| 7714 | /* 21424 */ // GIR_Coverage, 6014, |
| 7715 | /* 21424 */ GIR_EraseRootFromParent_Done, |
| 7716 | /* 21425 */ // Label 529: @21425 |
| 7717 | /* 21425 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 530*/ GIMT_Encode4(21557), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6251 // |
| 7718 | /* 21432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7719 | /* 21436 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7720 | /* 21440 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7721 | /* 21444 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7722 | /* 21448 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7723 | /* 21452 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7724 | /* 21456 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7725 | /* 21460 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7726 | /* 21464 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7727 | /* 21468 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7728 | /* 21473 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7729 | /* 21477 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7730 | /* 21481 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 7731 | /* 21485 */ // MIs[3] Operand 1 |
| 7732 | /* 21485 */ // No operand predicates |
| 7733 | /* 21485 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7734 | /* 21496 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7735 | /* 21500 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7736 | /* 21504 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7737 | /* 21508 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7738 | /* 21512 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7739 | /* 21517 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 7740 | /* 21528 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7741 | /* 21530 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 7742 | /* 21530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7743 | /* 21533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7744 | /* 21535 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1 |
| 7745 | /* 21539 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 7746 | /* 21543 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7747 | /* 21546 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7748 | /* 21549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7749 | /* 21555 */ GIR_RootConstrainSelectedInstOperands, |
| 7750 | /* 21556 */ // GIR_Coverage, 6251, |
| 7751 | /* 21556 */ GIR_EraseRootFromParent_Done, |
| 7752 | /* 21557 */ // Label 530: @21557 |
| 7753 | /* 21557 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 531*/ GIMT_Encode4(21689), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6297 // |
| 7754 | /* 21564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7755 | /* 21568 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7756 | /* 21572 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7757 | /* 21576 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7758 | /* 21580 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7759 | /* 21584 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7760 | /* 21588 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7761 | /* 21592 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7762 | /* 21596 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7763 | /* 21600 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7764 | /* 21605 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7765 | /* 21609 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7766 | /* 21613 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 7767 | /* 21617 */ // MIs[3] Operand 1 |
| 7768 | /* 21617 */ // No operand predicates |
| 7769 | /* 21617 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 7770 | /* 21628 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7771 | /* 21632 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7772 | /* 21636 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7773 | /* 21640 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7774 | /* 21644 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7775 | /* 21649 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760), |
| 7776 | /* 21660 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7777 | /* 21662 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 7778 | /* 21662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 7779 | /* 21665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7780 | /* 21667 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1 |
| 7781 | /* 21671 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 7782 | /* 21675 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7783 | /* 21678 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7784 | /* 21681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7785 | /* 21687 */ GIR_RootConstrainSelectedInstOperands, |
| 7786 | /* 21688 */ // GIR_Coverage, 6297, |
| 7787 | /* 21688 */ GIR_EraseRootFromParent_Done, |
| 7788 | /* 21689 */ // Label 531: @21689 |
| 7789 | /* 21689 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 532*/ GIMT_Encode4(21821), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 5978 // |
| 7790 | /* 21696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7791 | /* 21700 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7792 | /* 21704 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7793 | /* 21708 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7794 | /* 21712 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7795 | /* 21716 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7796 | /* 21720 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7797 | /* 21724 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7798 | /* 21728 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7799 | /* 21732 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7800 | /* 21737 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7801 | /* 21741 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7802 | /* 21745 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 7803 | /* 21749 */ // MIs[3] Operand 1 |
| 7804 | /* 21749 */ // No operand predicates |
| 7805 | /* 21749 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7806 | /* 21760 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7807 | /* 21764 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7808 | /* 21768 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7809 | /* 21772 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7810 | /* 21776 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7811 | /* 21781 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535), |
| 7812 | /* 21792 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7813 | /* 21794 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7814 | /* 21794 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 7815 | /* 21797 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7816 | /* 21799 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 7817 | /* 21803 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7818 | /* 21807 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7819 | /* 21810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7820 | /* 21813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7821 | /* 21819 */ GIR_RootConstrainSelectedInstOperands, |
| 7822 | /* 21820 */ // GIR_Coverage, 5978, |
| 7823 | /* 21820 */ GIR_EraseRootFromParent_Done, |
| 7824 | /* 21821 */ // Label 532: @21821 |
| 7825 | /* 21821 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 533*/ GIMT_Encode4(21953), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6013 // |
| 7826 | /* 21828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7827 | /* 21832 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7828 | /* 21836 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7829 | /* 21840 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7830 | /* 21844 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7831 | /* 21848 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7832 | /* 21852 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 7833 | /* 21856 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7834 | /* 21860 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7835 | /* 21864 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7836 | /* 21869 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7837 | /* 21873 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7838 | /* 21877 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 7839 | /* 21881 */ // MIs[3] Operand 1 |
| 7840 | /* 21881 */ // No operand predicates |
| 7841 | /* 21881 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7842 | /* 21892 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 7843 | /* 21896 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND), |
| 7844 | /* 21900 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 7845 | /* 21904 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 7846 | /* 21908 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7847 | /* 21913 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535), |
| 7848 | /* 21924 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7849 | /* 21926 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7850 | /* 21926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 7851 | /* 21929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7852 | /* 21931 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn |
| 7853 | /* 21935 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 7854 | /* 21939 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 7855 | /* 21942 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7856 | /* 21945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7857 | /* 21951 */ GIR_RootConstrainSelectedInstOperands, |
| 7858 | /* 21952 */ // GIR_Coverage, 6013, |
| 7859 | /* 21952 */ GIR_EraseRootFromParent_Done, |
| 7860 | /* 21953 */ // Label 533: @21953 |
| 7861 | /* 21953 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 534*/ GIMT_Encode4(22085), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 202 // |
| 7862 | /* 21960 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7863 | /* 21964 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7864 | /* 21968 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7865 | /* 21972 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7866 | /* 21976 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7867 | /* 21980 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7868 | /* 21985 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7869 | /* 21996 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7870 | /* 22000 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7871 | /* 22004 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7872 | /* 22008 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7873 | /* 22012 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7874 | /* 22016 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7875 | /* 22020 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7876 | /* 22024 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7877 | /* 22028 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7878 | /* 22033 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 7879 | /* 22037 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7880 | /* 22041 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 7881 | /* 22045 */ // MIs[4] Operand 1 |
| 7882 | /* 22045 */ // No operand predicates |
| 7883 | /* 22045 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 7884 | /* 22056 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7885 | /* 22058 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7886 | /* 22058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7887 | /* 22061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7888 | /* 22063 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7889 | /* 22067 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 7890 | /* 22071 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 7891 | /* 22074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7892 | /* 22077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7893 | /* 22083 */ GIR_RootConstrainSelectedInstOperands, |
| 7894 | /* 22084 */ // GIR_Coverage, 202, |
| 7895 | /* 22084 */ GIR_EraseRootFromParent_Done, |
| 7896 | /* 22085 */ // Label 534: @22085 |
| 7897 | /* 22085 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 535*/ GIMT_Encode4(22217), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 539 // |
| 7898 | /* 22092 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7899 | /* 22096 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7900 | /* 22100 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7901 | /* 22104 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7902 | /* 22108 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7903 | /* 22112 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7904 | /* 22117 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7905 | /* 22128 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7906 | /* 22132 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7907 | /* 22136 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7908 | /* 22140 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7909 | /* 22144 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7910 | /* 22148 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 7911 | /* 22152 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7912 | /* 22156 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7913 | /* 22160 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7914 | /* 22165 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 7915 | /* 22169 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7916 | /* 22173 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt), |
| 7917 | /* 22177 */ // MIs[4] Operand 1 |
| 7918 | /* 22177 */ // No operand predicates |
| 7919 | /* 22177 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 7920 | /* 22188 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7921 | /* 22190 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 7922 | /* 22190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 7923 | /* 22193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7924 | /* 22195 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 7925 | /* 22199 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 7926 | /* 22203 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 7927 | /* 22206 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7928 | /* 22209 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7929 | /* 22215 */ GIR_RootConstrainSelectedInstOperands, |
| 7930 | /* 22216 */ // GIR_Coverage, 539, |
| 7931 | /* 22216 */ GIR_EraseRootFromParent_Done, |
| 7932 | /* 22217 */ // Label 535: @22217 |
| 7933 | /* 22217 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 536*/ GIMT_Encode4(22349), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2107 // |
| 7934 | /* 22224 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7935 | /* 22228 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7936 | /* 22232 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7937 | /* 22236 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7938 | /* 22240 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7939 | /* 22244 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7940 | /* 22249 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7941 | /* 22260 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7942 | /* 22264 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7943 | /* 22268 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7944 | /* 22272 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7945 | /* 22276 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7946 | /* 22280 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7947 | /* 22284 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7948 | /* 22288 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7949 | /* 22292 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 7950 | /* 22297 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 7951 | /* 22301 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7952 | /* 22305 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 7953 | /* 22309 */ // MIs[4] Operand 1 |
| 7954 | /* 22309 */ // No operand predicates |
| 7955 | /* 22309 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 7956 | /* 22320 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7957 | /* 22322 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 7958 | /* 22322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 7959 | /* 22325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7960 | /* 22327 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 7961 | /* 22331 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2 |
| 7962 | /* 22335 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 7963 | /* 22338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 7964 | /* 22341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 7965 | /* 22347 */ GIR_RootConstrainSelectedInstOperands, |
| 7966 | /* 22348 */ // GIR_Coverage, 2107, |
| 7967 | /* 22348 */ GIR_EraseRootFromParent_Done, |
| 7968 | /* 22349 */ // Label 536: @22349 |
| 7969 | /* 22349 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 537*/ GIMT_Encode4(22481), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2395 // |
| 7970 | /* 22356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7971 | /* 22360 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7972 | /* 22364 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7973 | /* 22368 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 7974 | /* 22372 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 7975 | /* 22376 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7976 | /* 22381 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 7977 | /* 22392 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7978 | /* 22396 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7979 | /* 22400 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 7980 | /* 22404 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 7981 | /* 22408 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7982 | /* 22412 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 7983 | /* 22416 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 7984 | /* 22420 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 7985 | /* 22424 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 7986 | /* 22429 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 7987 | /* 22433 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 7988 | /* 22437 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15), |
| 7989 | /* 22441 */ // MIs[4] Operand 1 |
| 7990 | /* 22441 */ // No operand predicates |
| 7991 | /* 22441 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 7992 | /* 22452 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 7993 | /* 22454 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh) |
| 7994 | /* 22454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 7995 | /* 22457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 7996 | /* 22459 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 7997 | /* 22463 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2 |
| 7998 | /* 22467 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 7999 | /* 22470 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8000 | /* 22473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8001 | /* 22479 */ GIR_RootConstrainSelectedInstOperands, |
| 8002 | /* 22480 */ // GIR_Coverage, 2395, |
| 8003 | /* 22480 */ GIR_EraseRootFromParent_Done, |
| 8004 | /* 22481 */ // Label 537: @22481 |
| 8005 | /* 22481 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 538*/ GIMT_Encode4(22613), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 201 // |
| 8006 | /* 22488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8007 | /* 22492 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8008 | /* 22496 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8009 | /* 22500 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8010 | /* 22504 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8011 | /* 22508 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8012 | /* 22513 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8013 | /* 22524 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8014 | /* 22528 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8015 | /* 22532 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8016 | /* 22536 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8017 | /* 22540 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 8018 | /* 22544 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8019 | /* 22548 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8020 | /* 22552 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8021 | /* 22556 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8022 | /* 22561 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 8023 | /* 22565 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8024 | /* 22569 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 8025 | /* 22573 */ // MIs[4] Operand 1 |
| 8026 | /* 22573 */ // No operand predicates |
| 8027 | /* 22573 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 8028 | /* 22584 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8029 | /* 22586 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 8030 | /* 22586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8031 | /* 22589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8032 | /* 22591 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 8033 | /* 22595 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 8034 | /* 22599 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 8035 | /* 22602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8036 | /* 22605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8037 | /* 22611 */ GIR_RootConstrainSelectedInstOperands, |
| 8038 | /* 22612 */ // GIR_Coverage, 201, |
| 8039 | /* 22612 */ GIR_EraseRootFromParent_Done, |
| 8040 | /* 22613 */ // Label 538: @22613 |
| 8041 | /* 22613 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 539*/ GIMT_Encode4(22745), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 538 // |
| 8042 | /* 22620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8043 | /* 22624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8044 | /* 22628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8045 | /* 22632 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8046 | /* 22636 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8047 | /* 22640 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8048 | /* 22645 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8049 | /* 22656 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8050 | /* 22660 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8051 | /* 22664 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8052 | /* 22668 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8053 | /* 22672 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 8054 | /* 22676 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8055 | /* 22680 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8056 | /* 22684 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8057 | /* 22688 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8058 | /* 22693 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4] |
| 8059 | /* 22697 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8060 | /* 22701 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt), |
| 8061 | /* 22705 */ // MIs[4] Operand 1 |
| 8062 | /* 22705 */ // No operand predicates |
| 8063 | /* 22705 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 8064 | /* 22716 */ GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 8065 | /* 22718 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh) |
| 8066 | /* 22718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8067 | /* 22721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8068 | /* 22723 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 8069 | /* 22727 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm |
| 8070 | /* 22731 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh |
| 8071 | /* 22734 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8072 | /* 22737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8073 | /* 22743 */ GIR_RootConstrainSelectedInstOperands, |
| 8074 | /* 22744 */ // GIR_Coverage, 538, |
| 8075 | /* 22744 */ GIR_EraseRootFromParent_Done, |
| 8076 | /* 22745 */ // Label 539: @22745 |
| 8077 | /* 22745 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 540*/ GIMT_Encode4(22849), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2103 // |
| 8078 | /* 22752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8079 | /* 22756 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8080 | /* 22760 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8081 | /* 22764 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8082 | /* 22768 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8083 | /* 22772 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8084 | /* 22777 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8085 | /* 22788 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8086 | /* 22792 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8087 | /* 22796 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8088 | /* 22800 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8089 | /* 22804 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8090 | /* 22809 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 8091 | /* 22820 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8092 | /* 22822 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 8093 | /* 22822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8094 | /* 22825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8095 | /* 22827 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 8096 | /* 22831 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 8097 | /* 22835 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8098 | /* 22838 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8099 | /* 22841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8100 | /* 22847 */ GIR_RootConstrainSelectedInstOperands, |
| 8101 | /* 22848 */ // GIR_Coverage, 2103, |
| 8102 | /* 22848 */ GIR_EraseRootFromParent_Done, |
| 8103 | /* 22849 */ // Label 540: @22849 |
| 8104 | /* 22849 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 541*/ GIMT_Encode4(22953), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2391 // |
| 8105 | /* 22856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8106 | /* 22860 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8107 | /* 22864 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8108 | /* 22868 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8109 | /* 22872 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8110 | /* 22876 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8111 | /* 22881 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8112 | /* 22892 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8113 | /* 22896 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8114 | /* 22900 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8115 | /* 22904 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8116 | /* 22908 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8117 | /* 22913 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760), |
| 8118 | /* 22924 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8119 | /* 22926 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] }) |
| 8120 | /* 22926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8121 | /* 22929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8122 | /* 22931 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8123 | /* 22935 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8124 | /* 22939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8125 | /* 22942 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8126 | /* 22945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8127 | /* 22951 */ GIR_RootConstrainSelectedInstOperands, |
| 8128 | /* 22952 */ // GIR_Coverage, 2391, |
| 8129 | /* 22952 */ GIR_EraseRootFromParent_Done, |
| 8130 | /* 22953 */ // Label 541: @22953 |
| 8131 | /* 22953 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 542*/ GIMT_Encode4(23057), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6247 // |
| 8132 | /* 22960 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8133 | /* 22964 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8134 | /* 22968 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8135 | /* 22972 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8136 | /* 22976 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8137 | /* 22980 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8138 | /* 22985 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8139 | /* 22996 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8140 | /* 23000 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8141 | /* 23004 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8142 | /* 23008 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8143 | /* 23012 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8144 | /* 23017 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 8145 | /* 23028 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8146 | /* 23030 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 8147 | /* 23030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8148 | /* 23033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8149 | /* 23035 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn |
| 8150 | /* 23039 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8151 | /* 23043 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8152 | /* 23046 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8153 | /* 23049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8154 | /* 23055 */ GIR_RootConstrainSelectedInstOperands, |
| 8155 | /* 23056 */ // GIR_Coverage, 6247, |
| 8156 | /* 23056 */ GIR_EraseRootFromParent_Done, |
| 8157 | /* 23057 */ // Label 542: @23057 |
| 8158 | /* 23057 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 543*/ GIMT_Encode4(23161), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6293 // |
| 8159 | /* 23064 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8160 | /* 23068 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8161 | /* 23072 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8162 | /* 23076 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8163 | /* 23080 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8164 | /* 23084 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8165 | /* 23089 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8166 | /* 23100 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8167 | /* 23104 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8168 | /* 23108 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8169 | /* 23112 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8170 | /* 23116 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8171 | /* 23121 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535), |
| 8172 | /* 23132 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8173 | /* 23134 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] }) |
| 8174 | /* 23134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8175 | /* 23137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8176 | /* 23139 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 8177 | /* 23143 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8178 | /* 23147 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 8179 | /* 23150 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8180 | /* 23153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8181 | /* 23159 */ GIR_RootConstrainSelectedInstOperands, |
| 8182 | /* 23160 */ // GIR_Coverage, 6293, |
| 8183 | /* 23160 */ GIR_EraseRootFromParent_Done, |
| 8184 | /* 23161 */ // Label 543: @23161 |
| 8185 | /* 23161 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 544*/ GIMT_Encode4(23266), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2106 // |
| 8186 | /* 23168 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8187 | /* 23172 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8188 | /* 23176 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8189 | /* 23180 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8190 | /* 23184 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8191 | /* 23188 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8192 | /* 23193 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8193 | /* 23204 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8194 | /* 23208 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 8195 | /* 23212 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8196 | /* 23216 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8197 | /* 23220 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8198 | /* 23225 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8199 | /* 23229 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8200 | /* 23233 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8201 | /* 23237 */ // MIs[3] Operand 1 |
| 8202 | /* 23237 */ // No operand predicates |
| 8203 | /* 23237 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8204 | /* 23239 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8205 | /* 23239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 8206 | /* 23242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8207 | /* 23244 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8208 | /* 23248 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8209 | /* 23252 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8210 | /* 23255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8211 | /* 23258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8212 | /* 23264 */ GIR_RootConstrainSelectedInstOperands, |
| 8213 | /* 23265 */ // GIR_Coverage, 2106, |
| 8214 | /* 23265 */ GIR_EraseRootFromParent_Done, |
| 8215 | /* 23266 */ // Label 544: @23266 |
| 8216 | /* 23266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 545*/ GIMT_Encode4(23371), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2394 // |
| 8217 | /* 23273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8218 | /* 23277 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8219 | /* 23281 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8220 | /* 23285 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8221 | /* 23289 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8222 | /* 23293 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8223 | /* 23298 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8224 | /* 23309 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8225 | /* 23313 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 8226 | /* 23317 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8227 | /* 23321 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8228 | /* 23325 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8229 | /* 23330 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8230 | /* 23334 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8231 | /* 23338 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8232 | /* 23342 */ // MIs[3] Operand 1 |
| 8233 | /* 23342 */ // No operand predicates |
| 8234 | /* 23342 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8235 | /* 23344 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8236 | /* 23344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8237 | /* 23347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8238 | /* 23349 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8239 | /* 23353 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8240 | /* 23357 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8241 | /* 23360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8242 | /* 23363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8243 | /* 23369 */ GIR_RootConstrainSelectedInstOperands, |
| 8244 | /* 23370 */ // GIR_Coverage, 2394, |
| 8245 | /* 23370 */ GIR_EraseRootFromParent_Done, |
| 8246 | /* 23371 */ // Label 545: @23371 |
| 8247 | /* 23371 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 546*/ GIMT_Encode4(23476), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2105 // |
| 8248 | /* 23378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8249 | /* 23382 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8250 | /* 23386 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8251 | /* 23390 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8252 | /* 23394 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8253 | /* 23398 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8254 | /* 23403 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8255 | /* 23414 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8256 | /* 23418 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8257 | /* 23422 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8258 | /* 23426 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8259 | /* 23430 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8260 | /* 23435 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8261 | /* 23439 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8262 | /* 23443 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 8263 | /* 23447 */ // MIs[3] Operand 1 |
| 8264 | /* 23447 */ // No operand predicates |
| 8265 | /* 23447 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8266 | /* 23449 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 8267 | /* 23449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 8268 | /* 23452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8269 | /* 23454 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8270 | /* 23458 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8271 | /* 23462 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8272 | /* 23465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8273 | /* 23468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8274 | /* 23474 */ GIR_RootConstrainSelectedInstOperands, |
| 8275 | /* 23475 */ // GIR_Coverage, 2105, |
| 8276 | /* 23475 */ GIR_EraseRootFromParent_Done, |
| 8277 | /* 23476 */ // Label 546: @23476 |
| 8278 | /* 23476 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 547*/ GIMT_Encode4(23581), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2393 // |
| 8279 | /* 23483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8280 | /* 23487 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8281 | /* 23491 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8282 | /* 23495 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8283 | /* 23499 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8284 | /* 23503 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8285 | /* 23508 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760), |
| 8286 | /* 23519 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8287 | /* 23523 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8288 | /* 23527 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8289 | /* 23531 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8290 | /* 23535 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8291 | /* 23540 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8292 | /* 23544 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8293 | /* 23548 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 8294 | /* 23552 */ // MIs[3] Operand 1 |
| 8295 | /* 23552 */ // No operand predicates |
| 8296 | /* 23552 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8297 | /* 23554 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 8298 | /* 23554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8299 | /* 23557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8300 | /* 23559 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8301 | /* 23563 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8302 | /* 23567 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8303 | /* 23570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8304 | /* 23573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8305 | /* 23579 */ GIR_RootConstrainSelectedInstOperands, |
| 8306 | /* 23580 */ // GIR_Coverage, 2393, |
| 8307 | /* 23580 */ GIR_EraseRootFromParent_Done, |
| 8308 | /* 23581 */ // Label 547: @23581 |
| 8309 | /* 23581 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 548*/ GIMT_Encode4(23686), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2104 // |
| 8310 | /* 23588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8311 | /* 23592 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8312 | /* 23596 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8313 | /* 23600 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8314 | /* 23604 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8315 | /* 23608 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8316 | /* 23613 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8317 | /* 23624 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8318 | /* 23628 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8319 | /* 23632 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8320 | /* 23636 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8321 | /* 23640 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8322 | /* 23645 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8323 | /* 23649 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8324 | /* 23653 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8325 | /* 23657 */ // MIs[3] Operand 1 |
| 8326 | /* 23657 */ // No operand predicates |
| 8327 | /* 23657 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8328 | /* 23659 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8329 | /* 23659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8330 | /* 23662 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8331 | /* 23664 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 8332 | /* 23668 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm |
| 8333 | /* 23672 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8334 | /* 23675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8335 | /* 23678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8336 | /* 23684 */ GIR_RootConstrainSelectedInstOperands, |
| 8337 | /* 23685 */ // GIR_Coverage, 2104, |
| 8338 | /* 23685 */ GIR_EraseRootFromParent_Done, |
| 8339 | /* 23686 */ // Label 548: @23686 |
| 8340 | /* 23686 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 549*/ GIMT_Encode4(23791), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2392 // |
| 8341 | /* 23693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8342 | /* 23697 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8343 | /* 23701 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8344 | /* 23705 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8345 | /* 23709 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8346 | /* 23713 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8347 | /* 23718 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535), |
| 8348 | /* 23729 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8349 | /* 23733 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8350 | /* 23737 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8351 | /* 23741 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8352 | /* 23745 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8353 | /* 23750 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8354 | /* 23754 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8355 | /* 23758 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8356 | /* 23762 */ // MIs[3] Operand 1 |
| 8357 | /* 23762 */ // No operand predicates |
| 8358 | /* 23762 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8359 | /* 23764 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8360 | /* 23764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8361 | /* 23767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8362 | /* 23769 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8363 | /* 23773 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 8364 | /* 23777 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh |
| 8365 | /* 23780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8366 | /* 23783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8367 | /* 23789 */ GIR_RootConstrainSelectedInstOperands, |
| 8368 | /* 23790 */ // GIR_Coverage, 2392, |
| 8369 | /* 23790 */ GIR_EraseRootFromParent_Done, |
| 8370 | /* 23791 */ // Label 549: @23791 |
| 8371 | /* 23791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 550*/ GIMT_Encode4(23896), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6250 // |
| 8372 | /* 23798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8373 | /* 23802 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8374 | /* 23806 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 8375 | /* 23810 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8376 | /* 23814 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8377 | /* 23818 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8378 | /* 23823 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8379 | /* 23827 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8380 | /* 23831 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8381 | /* 23835 */ // MIs[2] Operand 1 |
| 8382 | /* 23835 */ // No operand predicates |
| 8383 | /* 23835 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8384 | /* 23839 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8385 | /* 23843 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8386 | /* 23847 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8387 | /* 23851 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8388 | /* 23856 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 8389 | /* 23867 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8390 | /* 23869 */ // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8391 | /* 23869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 8392 | /* 23872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8393 | /* 23874 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8394 | /* 23878 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8395 | /* 23882 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8396 | /* 23885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8397 | /* 23888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8398 | /* 23894 */ GIR_RootConstrainSelectedInstOperands, |
| 8399 | /* 23895 */ // GIR_Coverage, 6250, |
| 8400 | /* 23895 */ GIR_EraseRootFromParent_Done, |
| 8401 | /* 23896 */ // Label 550: @23896 |
| 8402 | /* 23896 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 551*/ GIMT_Encode4(24001), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6296 // |
| 8403 | /* 23903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8404 | /* 23907 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8405 | /* 23911 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 8406 | /* 23915 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8407 | /* 23919 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8408 | /* 23923 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8409 | /* 23928 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8410 | /* 23932 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8411 | /* 23936 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8412 | /* 23940 */ // MIs[2] Operand 1 |
| 8413 | /* 23940 */ // No operand predicates |
| 8414 | /* 23940 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8415 | /* 23944 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8416 | /* 23948 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8417 | /* 23952 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8418 | /* 23956 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8419 | /* 23961 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 8420 | /* 23972 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8421 | /* 23974 */ // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8422 | /* 23974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8423 | /* 23977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8424 | /* 23979 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8425 | /* 23983 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8426 | /* 23987 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8427 | /* 23990 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8428 | /* 23993 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8429 | /* 23999 */ GIR_RootConstrainSelectedInstOperands, |
| 8430 | /* 24000 */ // GIR_Coverage, 6296, |
| 8431 | /* 24000 */ GIR_EraseRootFromParent_Done, |
| 8432 | /* 24001 */ // Label 551: @24001 |
| 8433 | /* 24001 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 552*/ GIMT_Encode4(24106), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6249 // |
| 8434 | /* 24008 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8435 | /* 24012 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8436 | /* 24016 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8437 | /* 24020 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8438 | /* 24024 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8439 | /* 24028 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8440 | /* 24033 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8441 | /* 24037 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8442 | /* 24041 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 8443 | /* 24045 */ // MIs[2] Operand 1 |
| 8444 | /* 24045 */ // No operand predicates |
| 8445 | /* 24045 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8446 | /* 24049 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8447 | /* 24053 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8448 | /* 24057 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8449 | /* 24061 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8450 | /* 24066 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 8451 | /* 24077 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8452 | /* 24079 */ // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 8453 | /* 24079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB), |
| 8454 | /* 24082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8455 | /* 24084 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8456 | /* 24088 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8457 | /* 24092 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8458 | /* 24095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8459 | /* 24098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8460 | /* 24104 */ GIR_RootConstrainSelectedInstOperands, |
| 8461 | /* 24105 */ // GIR_Coverage, 6249, |
| 8462 | /* 24105 */ GIR_EraseRootFromParent_Done, |
| 8463 | /* 24106 */ // Label 552: @24106 |
| 8464 | /* 24106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 553*/ GIMT_Encode4(24211), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6295 // |
| 8465 | /* 24113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8466 | /* 24117 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8467 | /* 24121 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 8468 | /* 24125 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8469 | /* 24129 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8470 | /* 24133 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8471 | /* 24138 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8472 | /* 24142 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8473 | /* 24146 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16), |
| 8474 | /* 24150 */ // MIs[2] Operand 1 |
| 8475 | /* 24150 */ // No operand predicates |
| 8476 | /* 24150 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8477 | /* 24154 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8478 | /* 24158 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8479 | /* 24162 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8480 | /* 24166 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8481 | /* 24171 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760), |
| 8482 | /* 24182 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8483 | /* 24184 */ // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh) |
| 8484 | /* 24184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB), |
| 8485 | /* 24187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8486 | /* 24189 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8487 | /* 24193 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8488 | /* 24197 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8489 | /* 24200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8490 | /* 24203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8491 | /* 24209 */ GIR_RootConstrainSelectedInstOperands, |
| 8492 | /* 24210 */ // GIR_Coverage, 6295, |
| 8493 | /* 24210 */ GIR_EraseRootFromParent_Done, |
| 8494 | /* 24211 */ // Label 553: @24211 |
| 8495 | /* 24211 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 554*/ GIMT_Encode4(24316), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6248 // |
| 8496 | /* 24218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8497 | /* 24222 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8498 | /* 24226 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8499 | /* 24230 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8500 | /* 24234 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8501 | /* 24238 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8502 | /* 24243 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8503 | /* 24247 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8504 | /* 24251 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8505 | /* 24255 */ // MIs[2] Operand 1 |
| 8506 | /* 24255 */ // No operand predicates |
| 8507 | /* 24255 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8508 | /* 24259 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8509 | /* 24263 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8510 | /* 24267 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8511 | /* 24271 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8512 | /* 24276 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535), |
| 8513 | /* 24287 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8514 | /* 24289 */ // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8515 | /* 24289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT), |
| 8516 | /* 24292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8517 | /* 24294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn |
| 8518 | /* 24298 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8519 | /* 24302 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8520 | /* 24305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8521 | /* 24308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8522 | /* 24314 */ GIR_RootConstrainSelectedInstOperands, |
| 8523 | /* 24315 */ // GIR_Coverage, 6248, |
| 8524 | /* 24315 */ GIR_EraseRootFromParent_Done, |
| 8525 | /* 24316 */ // Label 554: @24316 |
| 8526 | /* 24316 */ GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(24851), |
| 8527 | /* 24321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8528 | /* 24325 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 556*/ GIMT_Encode4(24426), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6294 // |
| 8529 | /* 24332 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8530 | /* 24336 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 8531 | /* 24340 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8532 | /* 24344 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8533 | /* 24348 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8534 | /* 24353 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8535 | /* 24357 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8536 | /* 24361 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31), |
| 8537 | /* 24365 */ // MIs[2] Operand 1 |
| 8538 | /* 24365 */ // No operand predicates |
| 8539 | /* 24365 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 8540 | /* 24369 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 8541 | /* 24373 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 8542 | /* 24377 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 8543 | /* 24381 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8544 | /* 24386 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535), |
| 8545 | /* 24397 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8546 | /* 24399 */ // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh) |
| 8547 | /* 24399 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT), |
| 8548 | /* 24402 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8549 | /* 24404 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1 |
| 8550 | /* 24408 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 8551 | /* 24412 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh |
| 8552 | /* 24415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8553 | /* 24418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8554 | /* 24424 */ GIR_RootConstrainSelectedInstOperands, |
| 8555 | /* 24425 */ // GIR_Coverage, 6294, |
| 8556 | /* 24425 */ GIR_EraseRootFromParent_Done, |
| 8557 | /* 24426 */ // Label 556: @24426 |
| 8558 | /* 24426 */ GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(24572), |
| 8559 | /* 24431 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8560 | /* 24435 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 558*/ GIMT_Encode4(24503), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6001 // |
| 8561 | /* 24442 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8562 | /* 24446 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8563 | /* 24450 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8564 | /* 24454 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8565 | /* 24458 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 8566 | /* 24462 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8567 | /* 24466 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8568 | /* 24470 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8569 | /* 24474 */ // MIs[2] Operand 1 |
| 8570 | /* 24474 */ // No operand predicates |
| 8571 | /* 24474 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8572 | /* 24476 */ // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8573 | /* 24476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8574 | /* 24479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8575 | /* 24481 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 8576 | /* 24483 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 8577 | /* 24486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8578 | /* 24489 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8579 | /* 24495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8580 | /* 24501 */ GIR_RootConstrainSelectedInstOperands, |
| 8581 | /* 24502 */ // GIR_Coverage, 6001, |
| 8582 | /* 24502 */ GIR_EraseRootFromParent_Done, |
| 8583 | /* 24503 */ // Label 558: @24503 |
| 8584 | /* 24503 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 559*/ GIMT_Encode4(24571), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6000 // |
| 8585 | /* 24510 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8586 | /* 24514 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8587 | /* 24518 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8588 | /* 24522 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8589 | /* 24526 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8590 | /* 24530 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8591 | /* 24534 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8592 | /* 24538 */ // MIs[2] Operand 1 |
| 8593 | /* 24538 */ // No operand predicates |
| 8594 | /* 24538 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 8595 | /* 24542 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8596 | /* 24544 */ // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8597 | /* 24544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8598 | /* 24547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8599 | /* 24549 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 8600 | /* 24551 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 8601 | /* 24554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8602 | /* 24557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8603 | /* 24563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8604 | /* 24569 */ GIR_RootConstrainSelectedInstOperands, |
| 8605 | /* 24570 */ // GIR_Coverage, 6000, |
| 8606 | /* 24570 */ GIR_EraseRootFromParent_Done, |
| 8607 | /* 24571 */ // Label 559: @24571 |
| 8608 | /* 24571 */ GIM_Reject, |
| 8609 | /* 24572 */ // Label 557: @24572 |
| 8610 | /* 24572 */ GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(24718), |
| 8611 | /* 24577 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8612 | /* 24581 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 561*/ GIMT_Encode4(24649), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 5999 // |
| 8613 | /* 24588 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8614 | /* 24592 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8615 | /* 24596 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8616 | /* 24600 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8617 | /* 24604 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255, |
| 8618 | /* 24608 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8619 | /* 24612 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8620 | /* 24616 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8621 | /* 24620 */ // MIs[2] Operand 1 |
| 8622 | /* 24620 */ // No operand predicates |
| 8623 | /* 24620 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8624 | /* 24622 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8625 | /* 24622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8626 | /* 24625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8627 | /* 24627 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8628 | /* 24629 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 8629 | /* 24632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8630 | /* 24635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8631 | /* 24641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8632 | /* 24647 */ GIR_RootConstrainSelectedInstOperands, |
| 8633 | /* 24648 */ // GIR_Coverage, 5999, |
| 8634 | /* 24648 */ GIR_EraseRootFromParent_Done, |
| 8635 | /* 24649 */ // Label 561: @24649 |
| 8636 | /* 24649 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 562*/ GIMT_Encode4(24717), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 495 // |
| 8637 | /* 24656 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8638 | /* 24660 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8639 | /* 24664 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8640 | /* 24668 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8641 | /* 24672 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8642 | /* 24676 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8643 | /* 24680 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8644 | /* 24684 */ // MIs[2] Operand 1 |
| 8645 | /* 24684 */ // No operand predicates |
| 8646 | /* 24684 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 8647 | /* 24688 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8648 | /* 24690 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8649 | /* 24690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri), |
| 8650 | /* 24693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8651 | /* 24695 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8652 | /* 24697 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm |
| 8653 | /* 24700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8654 | /* 24703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8655 | /* 24709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8656 | /* 24715 */ GIR_RootConstrainSelectedInstOperands, |
| 8657 | /* 24716 */ // GIR_Coverage, 495, |
| 8658 | /* 24716 */ GIR_EraseRootFromParent_Done, |
| 8659 | /* 24717 */ // Label 562: @24717 |
| 8660 | /* 24717 */ GIM_Reject, |
| 8661 | /* 24718 */ // Label 560: @24718 |
| 8662 | /* 24718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 563*/ GIMT_Encode4(24784), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6002 // |
| 8663 | /* 24725 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8664 | /* 24729 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8665 | /* 24733 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8666 | /* 24737 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8667 | /* 24741 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8668 | /* 24746 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 8669 | /* 24750 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8670 | /* 24754 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8671 | /* 24756 */ // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 8672 | /* 24756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr), |
| 8673 | /* 24759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8674 | /* 24761 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 8675 | /* 24763 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8676 | /* 24767 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8677 | /* 24770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8678 | /* 24776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8679 | /* 24782 */ GIR_RootConstrainSelectedInstOperands, |
| 8680 | /* 24783 */ // GIR_Coverage, 6002, |
| 8681 | /* 24783 */ GIR_EraseRootFromParent_Done, |
| 8682 | /* 24784 */ // Label 563: @24784 |
| 8683 | /* 24784 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 564*/ GIMT_Encode4(24850), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 496 // |
| 8684 | /* 24791 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8685 | /* 24795 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8686 | /* 24799 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8687 | /* 24803 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8688 | /* 24807 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8689 | /* 24811 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8690 | /* 24816 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255, |
| 8691 | /* 24820 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8692 | /* 24822 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 8693 | /* 24822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr), |
| 8694 | /* 24825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8695 | /* 24827 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8696 | /* 24829 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 8697 | /* 24833 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8698 | /* 24836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8699 | /* 24842 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8700 | /* 24848 */ GIR_RootConstrainSelectedInstOperands, |
| 8701 | /* 24849 */ // GIR_Coverage, 496, |
| 8702 | /* 24849 */ GIR_EraseRootFromParent_Done, |
| 8703 | /* 24850 */ // Label 564: @24850 |
| 8704 | /* 24850 */ GIM_Reject, |
| 8705 | /* 24851 */ // Label 555: @24851 |
| 8706 | /* 24851 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 565*/ GIMT_Encode4(24905), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 2036 // |
| 8707 | /* 24858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 8708 | /* 24862 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8709 | /* 24866 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760), |
| 8710 | /* 24877 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] }) |
| 8711 | /* 24877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVTi16), |
| 8712 | /* 24880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8713 | /* 24882 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8714 | /* 24884 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535), |
| 8715 | /* 24894 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8716 | /* 24897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8717 | /* 24903 */ GIR_RootConstrainSelectedInstOperands, |
| 8718 | /* 24904 */ // GIR_Coverage, 2036, |
| 8719 | /* 24904 */ GIR_EraseRootFromParent_Done, |
| 8720 | /* 24905 */ // Label 565: @24905 |
| 8721 | /* 24905 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 566*/ GIMT_Encode4(24959), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2288 // |
| 8722 | /* 24912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8723 | /* 24916 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8724 | /* 24920 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760), |
| 8725 | /* 24931 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] }) |
| 8726 | /* 24931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVTi16), |
| 8727 | /* 24934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8728 | /* 24936 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 8729 | /* 24938 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535), |
| 8730 | /* 24948 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8731 | /* 24951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8732 | /* 24957 */ GIR_RootConstrainSelectedInstOperands, |
| 8733 | /* 24958 */ // GIR_Coverage, 2288, |
| 8734 | /* 24958 */ GIR_EraseRootFromParent_Done, |
| 8735 | /* 24959 */ // Label 566: @24959 |
| 8736 | /* 24959 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 567*/ GIMT_Encode4(25015), GIMT_Encode2(GIFBS_IsARM), // Rule ID 150 // |
| 8737 | /* 24966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8738 | /* 24970 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8739 | /* 24974 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8740 | /* 24978 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8741 | /* 24982 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 8742 | /* 24986 */ // MIs[1] Operand 1 |
| 8743 | /* 24986 */ // No operand predicates |
| 8744 | /* 24986 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8745 | /* 24988 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8746 | /* 24988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRri), |
| 8747 | /* 24991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8748 | /* 24993 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8749 | /* 24995 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 8750 | /* 24998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8751 | /* 25001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8752 | /* 25007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8753 | /* 25013 */ GIR_RootConstrainSelectedInstOperands, |
| 8754 | /* 25014 */ // GIR_Coverage, 150, |
| 8755 | /* 25014 */ GIR_EraseRootFromParent_Done, |
| 8756 | /* 25015 */ // Label 567: @25015 |
| 8757 | /* 25015 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 568*/ GIMT_Encode4(25071), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 483 // |
| 8758 | /* 25022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8759 | /* 25026 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8760 | /* 25030 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8761 | /* 25034 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 8762 | /* 25038 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 8763 | /* 25042 */ // MIs[1] Operand 1 |
| 8764 | /* 25042 */ // No operand predicates |
| 8765 | /* 25042 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8766 | /* 25044 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 8767 | /* 25044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRri), |
| 8768 | /* 25047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8769 | /* 25049 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8770 | /* 25051 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 8771 | /* 25054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8772 | /* 25057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8773 | /* 25063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8774 | /* 25069 */ GIR_RootConstrainSelectedInstOperands, |
| 8775 | /* 25070 */ // GIR_Coverage, 483, |
| 8776 | /* 25070 */ GIR_EraseRootFromParent_Done, |
| 8777 | /* 25071 */ // Label 568: @25071 |
| 8778 | /* 25071 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 569*/ GIMT_Encode4(25116), GIMT_Encode2(GIFBS_IsARM), // Rule ID 151 // |
| 8779 | /* 25078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8780 | /* 25082 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8781 | /* 25086 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 8782 | /* 25090 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 8783 | /* 25090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRrr), |
| 8784 | /* 25093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8785 | /* 25095 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8786 | /* 25097 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 8787 | /* 25099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8788 | /* 25102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8789 | /* 25108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8790 | /* 25114 */ GIR_RootConstrainSelectedInstOperands, |
| 8791 | /* 25115 */ // GIR_Coverage, 151, |
| 8792 | /* 25115 */ GIR_EraseRootFromParent_Done, |
| 8793 | /* 25116 */ // Label 569: @25116 |
| 8794 | /* 25116 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 570*/ GIMT_Encode4(25161), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 324 // |
| 8795 | /* 25123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 8796 | /* 25127 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 8797 | /* 25131 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 8798 | /* 25135 */ // (or:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tORR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 8799 | /* 25135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tORR), |
| 8800 | /* 25138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 8801 | /* 25140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 8802 | /* 25146 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8803 | /* 25148 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 8804 | /* 25150 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8805 | /* 25153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8806 | /* 25159 */ GIR_RootConstrainSelectedInstOperands, |
| 8807 | /* 25160 */ // GIR_Coverage, 324, |
| 8808 | /* 25160 */ GIR_EraseRootFromParent_Done, |
| 8809 | /* 25161 */ // Label 570: @25161 |
| 8810 | /* 25161 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 571*/ GIMT_Encode4(25206), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 484 // |
| 8811 | /* 25168 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8812 | /* 25172 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8813 | /* 25176 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 8814 | /* 25180 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 8815 | /* 25180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 8816 | /* 25183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 8817 | /* 25185 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 8818 | /* 25187 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 8819 | /* 25189 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8820 | /* 25192 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8821 | /* 25198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8822 | /* 25204 */ GIR_RootConstrainSelectedInstOperands, |
| 8823 | /* 25205 */ // GIR_Coverage, 484, |
| 8824 | /* 25205 */ GIR_EraseRootFromParent_Done, |
| 8825 | /* 25206 */ // Label 571: @25206 |
| 8826 | /* 25206 */ GIM_Reject, |
| 8827 | /* 25207 */ // Label 523: @25207 |
| 8828 | /* 25207 */ GIM_Reject, |
| 8829 | /* 25208 */ // Label 510: @25208 |
| 8830 | /* 25208 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 572*/ GIMT_Encode4(25253), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2918 // |
| 8831 | /* 25215 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 8832 | /* 25218 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 8833 | /* 25221 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8834 | /* 25225 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8835 | /* 25229 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8836 | /* 25233 */ // (or:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VORRd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) |
| 8837 | /* 25233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 8838 | /* 25236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8839 | /* 25238 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 8840 | /* 25240 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 8841 | /* 25242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 8842 | /* 25245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8843 | /* 25251 */ GIR_RootConstrainSelectedInstOperands, |
| 8844 | /* 25252 */ // GIR_Coverage, 2918, |
| 8845 | /* 25252 */ GIR_EraseRootFromParent_Done, |
| 8846 | /* 25253 */ // Label 572: @25253 |
| 8847 | /* 25253 */ GIM_Reject, |
| 8848 | /* 25254 */ // Label 511: @25254 |
| 8849 | /* 25254 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 573*/ GIMT_Encode4(25370), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2022 // |
| 8850 | /* 25261 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, |
| 8851 | /* 25264 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, |
| 8852 | /* 25267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8853 | /* 25271 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8854 | /* 25275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8855 | /* 25279 */ // (or:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 8856 | /* 25279 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8857 | /* 25282 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8858 | /* 25286 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8859 | /* 25291 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 8860 | /* 25295 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8861 | /* 25300 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 8862 | /* 25303 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8863 | /* 25307 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8864 | /* 25312 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 8865 | /* 25316 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8866 | /* 25321 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8867 | /* 25324 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 8868 | /* 25328 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8869 | /* 25333 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8870 | /* 25336 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 8871 | /* 25339 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 8872 | /* 25342 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8873 | /* 25348 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8874 | /* 25354 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8875 | /* 25356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8876 | /* 25359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8877 | /* 25361 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8878 | /* 25364 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 8879 | /* 25369 */ // GIR_Coverage, 2022, |
| 8880 | /* 25369 */ GIR_EraseRootFromParent_Done, |
| 8881 | /* 25370 */ // Label 573: @25370 |
| 8882 | /* 25370 */ GIM_Reject, |
| 8883 | /* 25371 */ // Label 512: @25371 |
| 8884 | /* 25371 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 574*/ GIMT_Encode4(25487), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2023 // |
| 8885 | /* 25378 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, |
| 8886 | /* 25381 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, |
| 8887 | /* 25384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8888 | /* 25388 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8889 | /* 25392 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8890 | /* 25396 */ // (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 8891 | /* 25396 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8892 | /* 25399 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8893 | /* 25403 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8894 | /* 25408 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 8895 | /* 25412 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8896 | /* 25417 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 8897 | /* 25420 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8898 | /* 25424 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8899 | /* 25429 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 8900 | /* 25433 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8901 | /* 25438 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8902 | /* 25441 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 8903 | /* 25445 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8904 | /* 25450 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8905 | /* 25453 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 8906 | /* 25456 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 8907 | /* 25459 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8908 | /* 25465 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8909 | /* 25471 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8910 | /* 25473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8911 | /* 25476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8912 | /* 25478 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8913 | /* 25481 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 8914 | /* 25486 */ // GIR_Coverage, 2023, |
| 8915 | /* 25486 */ GIR_EraseRootFromParent_Done, |
| 8916 | /* 25487 */ // Label 574: @25487 |
| 8917 | /* 25487 */ GIM_Reject, |
| 8918 | /* 25488 */ // Label 513: @25488 |
| 8919 | /* 25488 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 575*/ GIMT_Encode4(25604), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2024 // |
| 8920 | /* 25495 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, |
| 8921 | /* 25498 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, |
| 8922 | /* 25501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8923 | /* 25505 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8924 | /* 25509 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8925 | /* 25513 */ // (or:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 8926 | /* 25513 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8927 | /* 25516 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8928 | /* 25520 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8929 | /* 25525 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 8930 | /* 25529 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8931 | /* 25534 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 8932 | /* 25537 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8933 | /* 25541 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8934 | /* 25546 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 8935 | /* 25550 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8936 | /* 25555 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8937 | /* 25558 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 8938 | /* 25562 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8939 | /* 25567 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8940 | /* 25570 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 8941 | /* 25573 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 8942 | /* 25576 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8943 | /* 25582 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8944 | /* 25588 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8945 | /* 25590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8946 | /* 25593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8947 | /* 25595 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8948 | /* 25598 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 8949 | /* 25603 */ // GIR_Coverage, 2024, |
| 8950 | /* 25603 */ GIR_EraseRootFromParent_Done, |
| 8951 | /* 25604 */ // Label 575: @25604 |
| 8952 | /* 25604 */ GIM_Reject, |
| 8953 | /* 25605 */ // Label 514: @25605 |
| 8954 | /* 25605 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 576*/ GIMT_Encode4(25721), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2025 // |
| 8955 | /* 25612 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, |
| 8956 | /* 25615 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, |
| 8957 | /* 25618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8958 | /* 25622 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8959 | /* 25626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 8960 | /* 25630 */ // (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 8961 | /* 25630 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8962 | /* 25633 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8963 | /* 25637 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8964 | /* 25642 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 8965 | /* 25646 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8966 | /* 25651 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 8967 | /* 25654 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8968 | /* 25658 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8969 | /* 25663 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 8970 | /* 25667 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 8971 | /* 25672 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 8972 | /* 25675 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr), |
| 8973 | /* 25679 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 8974 | /* 25684 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8975 | /* 25687 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 8976 | /* 25690 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 8977 | /* 25693 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8978 | /* 25699 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 8979 | /* 25705 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8980 | /* 25707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8981 | /* 25710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8982 | /* 25712 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8983 | /* 25715 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 8984 | /* 25720 */ // GIR_Coverage, 2025, |
| 8985 | /* 25720 */ GIR_EraseRootFromParent_Done, |
| 8986 | /* 25721 */ // Label 576: @25721 |
| 8987 | /* 25721 */ GIM_Reject, |
| 8988 | /* 25722 */ // Label 515: @25722 |
| 8989 | /* 25722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 577*/ GIMT_Encode4(25767), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2916 // |
| 8990 | /* 25729 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 8991 | /* 25732 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 8992 | /* 25735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8993 | /* 25739 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8994 | /* 25743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 8995 | /* 25747 */ // (or:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VORRd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) |
| 8996 | /* 25747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 8997 | /* 25750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 8998 | /* 25752 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 8999 | /* 25754 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9000 | /* 25756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9001 | /* 25759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9002 | /* 25765 */ GIR_RootConstrainSelectedInstOperands, |
| 9003 | /* 25766 */ // GIR_Coverage, 2916, |
| 9004 | /* 25766 */ GIR_EraseRootFromParent_Done, |
| 9005 | /* 25767 */ // Label 577: @25767 |
| 9006 | /* 25767 */ GIM_Reject, |
| 9007 | /* 25768 */ // Label 516: @25768 |
| 9008 | /* 25768 */ GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(25879), |
| 9009 | /* 25773 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9010 | /* 25776 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9011 | /* 25779 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 579*/ GIMT_Encode4(25818), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2919 // |
| 9012 | /* 25786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9013 | /* 25790 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9014 | /* 25794 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9015 | /* 25798 */ // (or:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VORRq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) |
| 9016 | /* 25798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 9017 | /* 25801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9018 | /* 25803 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9019 | /* 25805 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9020 | /* 25807 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9021 | /* 25810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9022 | /* 25816 */ GIR_RootConstrainSelectedInstOperands, |
| 9023 | /* 25817 */ // GIR_Coverage, 2919, |
| 9024 | /* 25817 */ GIR_EraseRootFromParent_Done, |
| 9025 | /* 25818 */ // Label 579: @25818 |
| 9026 | /* 25818 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 580*/ GIMT_Encode4(25878), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3766 // |
| 9027 | /* 25825 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9028 | /* 25829 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9029 | /* 25833 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9030 | /* 25837 */ // (or:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VORR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 9031 | /* 25837 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9032 | /* 25840 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9033 | /* 25844 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9034 | /* 25849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 9035 | /* 25852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9036 | /* 25854 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9037 | /* 25856 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9038 | /* 25858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9039 | /* 25861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9040 | /* 25867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9041 | /* 25873 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9042 | /* 25876 */ GIR_RootConstrainSelectedInstOperands, |
| 9043 | /* 25877 */ // GIR_Coverage, 3766, |
| 9044 | /* 25877 */ GIR_EraseRootFromParent_Done, |
| 9045 | /* 25878 */ // Label 580: @25878 |
| 9046 | /* 25878 */ GIM_Reject, |
| 9047 | /* 25879 */ // Label 578: @25879 |
| 9048 | /* 25879 */ GIM_Reject, |
| 9049 | /* 25880 */ // Label 517: @25880 |
| 9050 | /* 25880 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 581*/ GIMT_Encode4(25925), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2917 // |
| 9051 | /* 25887 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9052 | /* 25890 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 9053 | /* 25893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9054 | /* 25897 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9055 | /* 25901 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9056 | /* 25905 */ // (or:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VORRd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) |
| 9057 | /* 25905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 9058 | /* 25908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9059 | /* 25910 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9060 | /* 25912 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9061 | /* 25914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9062 | /* 25917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9063 | /* 25923 */ GIR_RootConstrainSelectedInstOperands, |
| 9064 | /* 25924 */ // GIR_Coverage, 2917, |
| 9065 | /* 25924 */ GIR_EraseRootFromParent_Done, |
| 9066 | /* 25925 */ // Label 581: @25925 |
| 9067 | /* 25925 */ GIM_Reject, |
| 9068 | /* 25926 */ // Label 518: @25926 |
| 9069 | /* 25926 */ GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(26037), |
| 9070 | /* 25931 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9071 | /* 25934 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9072 | /* 25937 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 583*/ GIMT_Encode4(25976), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2920 // |
| 9073 | /* 25944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9074 | /* 25948 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9075 | /* 25952 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9076 | /* 25956 */ // (or:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VORRq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) |
| 9077 | /* 25956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 9078 | /* 25959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9079 | /* 25961 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9080 | /* 25963 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9081 | /* 25965 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9082 | /* 25968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9083 | /* 25974 */ GIR_RootConstrainSelectedInstOperands, |
| 9084 | /* 25975 */ // GIR_Coverage, 2920, |
| 9085 | /* 25975 */ GIR_EraseRootFromParent_Done, |
| 9086 | /* 25976 */ // Label 583: @25976 |
| 9087 | /* 25976 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 584*/ GIMT_Encode4(26036), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3770 // |
| 9088 | /* 25983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9089 | /* 25987 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9090 | /* 25991 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9091 | /* 25995 */ // (or:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VORR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 9092 | /* 25995 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9093 | /* 25998 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9094 | /* 26002 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9095 | /* 26007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 9096 | /* 26010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9097 | /* 26012 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9098 | /* 26014 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9099 | /* 26016 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9100 | /* 26019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9101 | /* 26025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9102 | /* 26031 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9103 | /* 26034 */ GIR_RootConstrainSelectedInstOperands, |
| 9104 | /* 26035 */ // GIR_Coverage, 3770, |
| 9105 | /* 26035 */ GIR_EraseRootFromParent_Done, |
| 9106 | /* 26036 */ // Label 584: @26036 |
| 9107 | /* 26036 */ GIM_Reject, |
| 9108 | /* 26037 */ // Label 582: @26037 |
| 9109 | /* 26037 */ GIM_Reject, |
| 9110 | /* 26038 */ // Label 519: @26038 |
| 9111 | /* 26038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 585*/ GIMT_Encode4(26083), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1299 // |
| 9112 | /* 26045 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9113 | /* 26048 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 9114 | /* 26051 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9115 | /* 26055 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9116 | /* 26059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9117 | /* 26063 */ // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 9118 | /* 26063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd), |
| 9119 | /* 26066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9120 | /* 26068 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9121 | /* 26070 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9122 | /* 26072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9123 | /* 26075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9124 | /* 26081 */ GIR_RootConstrainSelectedInstOperands, |
| 9125 | /* 26082 */ // GIR_Coverage, 1299, |
| 9126 | /* 26082 */ GIR_EraseRootFromParent_Done, |
| 9127 | /* 26083 */ // Label 585: @26083 |
| 9128 | /* 26083 */ GIM_Reject, |
| 9129 | /* 26084 */ // Label 520: @26084 |
| 9130 | /* 26084 */ GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(26195), |
| 9131 | /* 26089 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9132 | /* 26092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9133 | /* 26095 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 587*/ GIMT_Encode4(26134), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1300 // |
| 9134 | /* 26102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9135 | /* 26106 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9136 | /* 26110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9137 | /* 26114 */ // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 9138 | /* 26114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 9139 | /* 26117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9140 | /* 26119 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9141 | /* 26121 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9142 | /* 26123 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9143 | /* 26126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9144 | /* 26132 */ GIR_RootConstrainSelectedInstOperands, |
| 9145 | /* 26133 */ // GIR_Coverage, 1300, |
| 9146 | /* 26133 */ GIR_EraseRootFromParent_Done, |
| 9147 | /* 26134 */ // Label 587: @26134 |
| 9148 | /* 26134 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 588*/ GIMT_Encode4(26194), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3774 // |
| 9149 | /* 26141 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9150 | /* 26145 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9151 | /* 26149 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9152 | /* 26153 */ // (or:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VORR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 9153 | /* 26153 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9154 | /* 26156 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9155 | /* 26160 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9156 | /* 26165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 9157 | /* 26168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9158 | /* 26170 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9159 | /* 26172 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9160 | /* 26174 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9161 | /* 26177 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9162 | /* 26183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9163 | /* 26189 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9164 | /* 26192 */ GIR_RootConstrainSelectedInstOperands, |
| 9165 | /* 26193 */ // GIR_Coverage, 3774, |
| 9166 | /* 26193 */ GIR_EraseRootFromParent_Done, |
| 9167 | /* 26194 */ // Label 588: @26194 |
| 9168 | /* 26194 */ GIM_Reject, |
| 9169 | /* 26195 */ // Label 586: @26195 |
| 9170 | /* 26195 */ GIM_Reject, |
| 9171 | /* 26196 */ // Label 521: @26196 |
| 9172 | /* 26196 */ GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(26307), |
| 9173 | /* 26201 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 9174 | /* 26204 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9175 | /* 26207 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 590*/ GIMT_Encode4(26246), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2921 // |
| 9176 | /* 26214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9177 | /* 26218 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9178 | /* 26222 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9179 | /* 26226 */ // (or:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VORRq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) |
| 9180 | /* 26226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq), |
| 9181 | /* 26229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9182 | /* 26231 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9183 | /* 26233 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9184 | /* 26235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9185 | /* 26238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9186 | /* 26244 */ GIR_RootConstrainSelectedInstOperands, |
| 9187 | /* 26245 */ // GIR_Coverage, 2921, |
| 9188 | /* 26245 */ GIR_EraseRootFromParent_Done, |
| 9189 | /* 26246 */ // Label 590: @26246 |
| 9190 | /* 26246 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 591*/ GIMT_Encode4(26306), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3778 // |
| 9191 | /* 26253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9192 | /* 26257 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9193 | /* 26261 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9194 | /* 26265 */ // (or:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VORR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) |
| 9195 | /* 26265 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9196 | /* 26268 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9197 | /* 26272 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9198 | /* 26277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR), |
| 9199 | /* 26280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9200 | /* 26282 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9201 | /* 26284 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9202 | /* 26286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9203 | /* 26289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9204 | /* 26295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9205 | /* 26301 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9206 | /* 26304 */ GIR_RootConstrainSelectedInstOperands, |
| 9207 | /* 26305 */ // GIR_Coverage, 3778, |
| 9208 | /* 26305 */ GIR_EraseRootFromParent_Done, |
| 9209 | /* 26306 */ // Label 591: @26306 |
| 9210 | /* 26306 */ GIM_Reject, |
| 9211 | /* 26307 */ // Label 589: @26307 |
| 9212 | /* 26307 */ GIM_Reject, |
| 9213 | /* 26308 */ // Label 522: @26308 |
| 9214 | /* 26308 */ GIM_Reject, |
| 9215 | /* 26309 */ // Label 7: @26309 |
| 9216 | /* 26309 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 605*/ GIMT_Encode4(27967), |
| 9217 | /* 26320 */ /*GILLT_s32*//*Label 592*/ GIMT_Encode4(26372), |
| 9218 | /* 26324 */ /*GILLT_s64*//*Label 593*/ GIMT_Encode4(26867), |
| 9219 | /* 26328 */ /*GILLT_v2s1*//*Label 594*/ GIMT_Encode4(26913), |
| 9220 | /* 26332 */ /*GILLT_v4s1*//*Label 595*/ GIMT_Encode4(27030), |
| 9221 | /* 26336 */ /*GILLT_v8s1*//*Label 596*/ GIMT_Encode4(27147), |
| 9222 | /* 26340 */ /*GILLT_v16s1*//*Label 597*/ GIMT_Encode4(27264), |
| 9223 | /* 26344 */ /*GILLT_v8s8*//*Label 598*/ GIMT_Encode4(27381), |
| 9224 | /* 26348 */ /*GILLT_v16s8*//*Label 599*/ GIMT_Encode4(27427), |
| 9225 | /* 26352 */ /*GILLT_v4s16*//*Label 600*/ GIMT_Encode4(27539), |
| 9226 | /* 26356 */ /*GILLT_v8s16*//*Label 601*/ GIMT_Encode4(27585), |
| 9227 | /* 26360 */ /*GILLT_v2s32*//*Label 602*/ GIMT_Encode4(27697), |
| 9228 | /* 26364 */ /*GILLT_v4s32*//*Label 603*/ GIMT_Encode4(27743), |
| 9229 | /* 26368 */ /*GILLT_v2s64*//*Label 604*/ GIMT_Encode4(27855), |
| 9230 | /* 26372 */ // Label 592: @26372 |
| 9231 | /* 26372 */ GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(26866), |
| 9232 | /* 26377 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 9233 | /* 26380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 9234 | /* 26383 */ GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(26532), |
| 9235 | /* 26388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9236 | /* 26392 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 608*/ GIMT_Encode4(26442), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6004 // |
| 9237 | /* 26399 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 255, |
| 9238 | /* 26403 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9239 | /* 26407 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 9240 | /* 26411 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 9241 | /* 26415 */ // MIs[1] Operand 1 |
| 9242 | /* 26415 */ // No operand predicates |
| 9243 | /* 26415 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9244 | /* 26417 */ // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 9245 | /* 26417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 9246 | /* 26420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9247 | /* 26422 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 9248 | /* 26425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9249 | /* 26428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9250 | /* 26434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9251 | /* 26440 */ GIR_RootConstrainSelectedInstOperands, |
| 9252 | /* 26441 */ // GIR_Coverage, 6004, |
| 9253 | /* 26441 */ GIR_EraseRootFromParent_Done, |
| 9254 | /* 26442 */ // Label 608: @26442 |
| 9255 | /* 26442 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 609*/ GIMT_Encode4(26492), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 498 // |
| 9256 | /* 26449 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9257 | /* 26453 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 9258 | /* 26457 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 9259 | /* 26461 */ // MIs[1] Operand 1 |
| 9260 | /* 26461 */ // No operand predicates |
| 9261 | /* 26461 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255, |
| 9262 | /* 26465 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9263 | /* 26467 */ // (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 9264 | /* 26467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 9265 | /* 26470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9266 | /* 26472 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 9267 | /* 26475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9268 | /* 26478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9269 | /* 26484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9270 | /* 26490 */ GIR_RootConstrainSelectedInstOperands, |
| 9271 | /* 26491 */ // GIR_Coverage, 498, |
| 9272 | /* 26491 */ GIR_EraseRootFromParent_Done, |
| 9273 | /* 26492 */ // Label 609: @26492 |
| 9274 | /* 26492 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 610*/ GIMT_Encode4(26531), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 499 // |
| 9275 | /* 26499 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9276 | /* 26503 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255, |
| 9277 | /* 26507 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 9278 | /* 26507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNr), |
| 9279 | /* 26510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9280 | /* 26512 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 9281 | /* 26514 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9282 | /* 26517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9283 | /* 26523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9284 | /* 26529 */ GIR_RootConstrainSelectedInstOperands, |
| 9285 | /* 26530 */ // GIR_Coverage, 499, |
| 9286 | /* 26530 */ GIR_EraseRootFromParent_Done, |
| 9287 | /* 26531 */ // Label 610: @26531 |
| 9288 | /* 26531 */ GIM_Reject, |
| 9289 | /* 26532 */ // Label 607: @26532 |
| 9290 | /* 26532 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 611*/ GIMT_Encode4(26575), GIMT_Encode2(GIFBS_IsARM), // Rule ID 164 // |
| 9291 | /* 26539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9292 | /* 26543 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9293 | /* 26547 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255, |
| 9294 | /* 26551 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 9295 | /* 26551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNr), |
| 9296 | /* 26554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9297 | /* 26556 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 9298 | /* 26558 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9299 | /* 26561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9300 | /* 26567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9301 | /* 26573 */ GIR_RootConstrainSelectedInstOperands, |
| 9302 | /* 26574 */ // GIR_Coverage, 164, |
| 9303 | /* 26574 */ GIR_EraseRootFromParent_Done, |
| 9304 | /* 26575 */ // Label 611: @26575 |
| 9305 | /* 26575 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 612*/ GIMT_Encode4(26618), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 323 // |
| 9306 | /* 26582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9307 | /* 26586 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9308 | /* 26590 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255, |
| 9309 | /* 26594 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, -1:{ *:[i32] }) => (tMVN:{ *:[i32] } tGPR:{ *:[i32] }:$Rn) |
| 9310 | /* 26594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMVN), |
| 9311 | /* 26597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9312 | /* 26599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 9313 | /* 26605 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9314 | /* 26607 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9315 | /* 26610 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9316 | /* 26616 */ GIR_RootConstrainSelectedInstOperands, |
| 9317 | /* 26617 */ // GIR_Coverage, 323, |
| 9318 | /* 26617 */ GIR_EraseRootFromParent_Done, |
| 9319 | /* 26618 */ // Label 612: @26618 |
| 9320 | /* 26618 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 613*/ GIMT_Encode4(26674), GIMT_Encode2(GIFBS_IsARM), // Rule ID 154 // |
| 9321 | /* 26625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9322 | /* 26629 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9323 | /* 26633 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9324 | /* 26637 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 9325 | /* 26641 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 9326 | /* 26645 */ // MIs[1] Operand 1 |
| 9327 | /* 26645 */ // No operand predicates |
| 9328 | /* 26645 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9329 | /* 26647 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 9330 | /* 26647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORri), |
| 9331 | /* 26650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9332 | /* 26652 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9333 | /* 26654 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 9334 | /* 26657 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9335 | /* 26660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9336 | /* 26666 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9337 | /* 26672 */ GIR_RootConstrainSelectedInstOperands, |
| 9338 | /* 26673 */ // GIR_Coverage, 154, |
| 9339 | /* 26673 */ GIR_EraseRootFromParent_Done, |
| 9340 | /* 26674 */ // Label 613: @26674 |
| 9341 | /* 26674 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 614*/ GIMT_Encode4(26730), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 486 // |
| 9342 | /* 26681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9343 | /* 26685 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9344 | /* 26689 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9345 | /* 26693 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 9346 | /* 26697 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 9347 | /* 26701 */ // MIs[1] Operand 1 |
| 9348 | /* 26701 */ // No operand predicates |
| 9349 | /* 26701 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9350 | /* 26703 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm) |
| 9351 | /* 26703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORri), |
| 9352 | /* 26706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9353 | /* 26708 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9354 | /* 26710 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 9355 | /* 26713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9356 | /* 26716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9357 | /* 26722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9358 | /* 26728 */ GIR_RootConstrainSelectedInstOperands, |
| 9359 | /* 26729 */ // GIR_Coverage, 486, |
| 9360 | /* 26729 */ GIR_EraseRootFromParent_Done, |
| 9361 | /* 26730 */ // Label 614: @26730 |
| 9362 | /* 26730 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 615*/ GIMT_Encode4(26775), GIMT_Encode2(GIFBS_IsARM), // Rule ID 155 // |
| 9363 | /* 26737 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9364 | /* 26741 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9365 | /* 26745 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 9366 | /* 26749 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 9367 | /* 26749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORrr), |
| 9368 | /* 26752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9369 | /* 26754 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9370 | /* 26756 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 9371 | /* 26758 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9372 | /* 26761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9373 | /* 26767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9374 | /* 26773 */ GIR_RootConstrainSelectedInstOperands, |
| 9375 | /* 26774 */ // GIR_Coverage, 155, |
| 9376 | /* 26774 */ GIR_EraseRootFromParent_Done, |
| 9377 | /* 26775 */ // Label 615: @26775 |
| 9378 | /* 26775 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 616*/ GIMT_Encode4(26820), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 316 // |
| 9379 | /* 26782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9380 | /* 26786 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9381 | /* 26790 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 9382 | /* 26794 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tEOR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 9383 | /* 26794 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tEOR), |
| 9384 | /* 26797 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 9385 | /* 26799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 9386 | /* 26805 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9387 | /* 26807 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 9388 | /* 26809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9389 | /* 26812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9390 | /* 26818 */ GIR_RootConstrainSelectedInstOperands, |
| 9391 | /* 26819 */ // GIR_Coverage, 316, |
| 9392 | /* 26819 */ GIR_EraseRootFromParent_Done, |
| 9393 | /* 26820 */ // Label 616: @26820 |
| 9394 | /* 26820 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 617*/ GIMT_Encode4(26865), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 487 // |
| 9395 | /* 26827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9396 | /* 26831 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9397 | /* 26835 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 9398 | /* 26839 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 9399 | /* 26839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9400 | /* 26842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 9401 | /* 26844 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 9402 | /* 26846 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 9403 | /* 26848 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9404 | /* 26851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9405 | /* 26857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9406 | /* 26863 */ GIR_RootConstrainSelectedInstOperands, |
| 9407 | /* 26864 */ // GIR_Coverage, 487, |
| 9408 | /* 26864 */ GIR_EraseRootFromParent_Done, |
| 9409 | /* 26865 */ // Label 617: @26865 |
| 9410 | /* 26865 */ GIM_Reject, |
| 9411 | /* 26866 */ // Label 606: @26866 |
| 9412 | /* 26866 */ GIM_Reject, |
| 9413 | /* 26867 */ // Label 593: @26867 |
| 9414 | /* 26867 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 618*/ GIMT_Encode4(26912), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2924 // |
| 9415 | /* 26874 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9416 | /* 26877 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9417 | /* 26880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9418 | /* 26884 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9419 | /* 26888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9420 | /* 26892 */ // (xor:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VEORd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) |
| 9421 | /* 26892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 9422 | /* 26895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9423 | /* 26897 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9424 | /* 26899 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9425 | /* 26901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9426 | /* 26904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9427 | /* 26910 */ GIR_RootConstrainSelectedInstOperands, |
| 9428 | /* 26911 */ // GIR_Coverage, 2924, |
| 9429 | /* 26911 */ GIR_EraseRootFromParent_Done, |
| 9430 | /* 26912 */ // Label 618: @26912 |
| 9431 | /* 26912 */ GIM_Reject, |
| 9432 | /* 26913 */ // Label 594: @26913 |
| 9433 | /* 26913 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 619*/ GIMT_Encode4(27029), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2018 // |
| 9434 | /* 26920 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1, |
| 9435 | /* 26923 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1, |
| 9436 | /* 26926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9437 | /* 26930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9438 | /* 26934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9439 | /* 26938 */ // (xor:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9440 | /* 26938 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9441 | /* 26941 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9442 | /* 26945 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9443 | /* 26950 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9444 | /* 26954 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9445 | /* 26959 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9446 | /* 26962 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9447 | /* 26966 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9448 | /* 26971 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9449 | /* 26975 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9450 | /* 26980 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9451 | /* 26983 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9452 | /* 26987 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9453 | /* 26992 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9454 | /* 26995 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9455 | /* 26998 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9456 | /* 27001 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9457 | /* 27007 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9458 | /* 27013 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9459 | /* 27015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9460 | /* 27018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9461 | /* 27020 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9462 | /* 27023 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9463 | /* 27028 */ // GIR_Coverage, 2018, |
| 9464 | /* 27028 */ GIR_EraseRootFromParent_Done, |
| 9465 | /* 27029 */ // Label 619: @27029 |
| 9466 | /* 27029 */ GIM_Reject, |
| 9467 | /* 27030 */ // Label 595: @27030 |
| 9468 | /* 27030 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 620*/ GIMT_Encode4(27146), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2019 // |
| 9469 | /* 27037 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1, |
| 9470 | /* 27040 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1, |
| 9471 | /* 27043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9472 | /* 27047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9473 | /* 27051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9474 | /* 27055 */ // (xor:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9475 | /* 27055 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9476 | /* 27058 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9477 | /* 27062 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9478 | /* 27067 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9479 | /* 27071 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9480 | /* 27076 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9481 | /* 27079 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9482 | /* 27083 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9483 | /* 27088 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9484 | /* 27092 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9485 | /* 27097 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9486 | /* 27100 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9487 | /* 27104 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9488 | /* 27109 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9489 | /* 27112 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9490 | /* 27115 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9491 | /* 27118 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9492 | /* 27124 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9493 | /* 27130 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9494 | /* 27132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9495 | /* 27135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9496 | /* 27137 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9497 | /* 27140 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9498 | /* 27145 */ // GIR_Coverage, 2019, |
| 9499 | /* 27145 */ GIR_EraseRootFromParent_Done, |
| 9500 | /* 27146 */ // Label 620: @27146 |
| 9501 | /* 27146 */ GIM_Reject, |
| 9502 | /* 27147 */ // Label 596: @27147 |
| 9503 | /* 27147 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 621*/ GIMT_Encode4(27263), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2020 // |
| 9504 | /* 27154 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1, |
| 9505 | /* 27157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1, |
| 9506 | /* 27160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9507 | /* 27164 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9508 | /* 27168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9509 | /* 27172 */ // (xor:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9510 | /* 27172 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9511 | /* 27175 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9512 | /* 27179 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9513 | /* 27184 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9514 | /* 27188 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9515 | /* 27193 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9516 | /* 27196 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9517 | /* 27200 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9518 | /* 27205 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9519 | /* 27209 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9520 | /* 27214 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9521 | /* 27217 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9522 | /* 27221 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9523 | /* 27226 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9524 | /* 27229 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9525 | /* 27232 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9526 | /* 27235 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9527 | /* 27241 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9528 | /* 27247 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9529 | /* 27249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9530 | /* 27252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9531 | /* 27254 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9532 | /* 27257 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9533 | /* 27262 */ // GIR_Coverage, 2020, |
| 9534 | /* 27262 */ GIR_EraseRootFromParent_Done, |
| 9535 | /* 27263 */ // Label 621: @27263 |
| 9536 | /* 27263 */ GIM_Reject, |
| 9537 | /* 27264 */ // Label 597: @27264 |
| 9538 | /* 27264 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 622*/ GIMT_Encode4(27380), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2021 // |
| 9539 | /* 27271 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1, |
| 9540 | /* 27274 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1, |
| 9541 | /* 27277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9542 | /* 27281 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9543 | /* 27285 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 9544 | /* 27289 */ // (xor:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] }) |
| 9545 | /* 27289 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9546 | /* 27292 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9547 | /* 27296 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9548 | /* 27301 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2 |
| 9549 | /* 27305 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9550 | /* 27310 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9551 | /* 27313 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9552 | /* 27317 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9553 | /* 27322 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1 |
| 9554 | /* 27326 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 9555 | /* 27331 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 9556 | /* 27334 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr), |
| 9557 | /* 27338 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9558 | /* 27343 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9559 | /* 27346 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9560 | /* 27349 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 9561 | /* 27352 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9562 | /* 27358 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9563 | /* 27364 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9564 | /* 27366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9565 | /* 27369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9566 | /* 27371 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9567 | /* 27374 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID), |
| 9568 | /* 27379 */ // GIR_Coverage, 2021, |
| 9569 | /* 27379 */ GIR_EraseRootFromParent_Done, |
| 9570 | /* 27380 */ // Label 622: @27380 |
| 9571 | /* 27380 */ GIM_Reject, |
| 9572 | /* 27381 */ // Label 598: @27381 |
| 9573 | /* 27381 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 623*/ GIMT_Encode4(27426), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2922 // |
| 9574 | /* 27388 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9575 | /* 27391 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 9576 | /* 27394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9577 | /* 27398 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9578 | /* 27402 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9579 | /* 27406 */ // (xor:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VEORd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) |
| 9580 | /* 27406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 9581 | /* 27409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9582 | /* 27411 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9583 | /* 27413 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9584 | /* 27415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9585 | /* 27418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9586 | /* 27424 */ GIR_RootConstrainSelectedInstOperands, |
| 9587 | /* 27425 */ // GIR_Coverage, 2922, |
| 9588 | /* 27425 */ GIR_EraseRootFromParent_Done, |
| 9589 | /* 27426 */ // Label 623: @27426 |
| 9590 | /* 27426 */ GIM_Reject, |
| 9591 | /* 27427 */ // Label 599: @27427 |
| 9592 | /* 27427 */ GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(27538), |
| 9593 | /* 27432 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9594 | /* 27435 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9595 | /* 27438 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 625*/ GIMT_Encode4(27477), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2925 // |
| 9596 | /* 27445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9597 | /* 27449 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9598 | /* 27453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9599 | /* 27457 */ // (xor:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VEORq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) |
| 9600 | /* 27457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 9601 | /* 27460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9602 | /* 27462 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9603 | /* 27464 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9604 | /* 27466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9605 | /* 27469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9606 | /* 27475 */ GIR_RootConstrainSelectedInstOperands, |
| 9607 | /* 27476 */ // GIR_Coverage, 2925, |
| 9608 | /* 27476 */ GIR_EraseRootFromParent_Done, |
| 9609 | /* 27477 */ // Label 625: @27477 |
| 9610 | /* 27477 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 626*/ GIMT_Encode4(27537), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3780 // |
| 9611 | /* 27484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9612 | /* 27488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9613 | /* 27492 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9614 | /* 27496 */ // (xor:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VEOR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 9615 | /* 27496 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9616 | /* 27499 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9617 | /* 27503 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9618 | /* 27508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 9619 | /* 27511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9620 | /* 27513 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9621 | /* 27515 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9622 | /* 27517 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9623 | /* 27520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9624 | /* 27526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9625 | /* 27532 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9626 | /* 27535 */ GIR_RootConstrainSelectedInstOperands, |
| 9627 | /* 27536 */ // GIR_Coverage, 3780, |
| 9628 | /* 27536 */ GIR_EraseRootFromParent_Done, |
| 9629 | /* 27537 */ // Label 626: @27537 |
| 9630 | /* 27537 */ GIM_Reject, |
| 9631 | /* 27538 */ // Label 624: @27538 |
| 9632 | /* 27538 */ GIM_Reject, |
| 9633 | /* 27539 */ // Label 600: @27539 |
| 9634 | /* 27539 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 627*/ GIMT_Encode4(27584), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2923 // |
| 9635 | /* 27546 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9636 | /* 27549 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 9637 | /* 27552 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9638 | /* 27556 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9639 | /* 27560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9640 | /* 27564 */ // (xor:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VEORd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) |
| 9641 | /* 27564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 9642 | /* 27567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9643 | /* 27569 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9644 | /* 27571 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9645 | /* 27573 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9646 | /* 27576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9647 | /* 27582 */ GIR_RootConstrainSelectedInstOperands, |
| 9648 | /* 27583 */ // GIR_Coverage, 2923, |
| 9649 | /* 27583 */ GIR_EraseRootFromParent_Done, |
| 9650 | /* 27584 */ // Label 627: @27584 |
| 9651 | /* 27584 */ GIM_Reject, |
| 9652 | /* 27585 */ // Label 601: @27585 |
| 9653 | /* 27585 */ GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(27696), |
| 9654 | /* 27590 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9655 | /* 27593 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9656 | /* 27596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 629*/ GIMT_Encode4(27635), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2926 // |
| 9657 | /* 27603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9658 | /* 27607 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9659 | /* 27611 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9660 | /* 27615 */ // (xor:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VEORq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) |
| 9661 | /* 27615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 9662 | /* 27618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9663 | /* 27620 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9664 | /* 27622 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9665 | /* 27624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9666 | /* 27627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9667 | /* 27633 */ GIR_RootConstrainSelectedInstOperands, |
| 9668 | /* 27634 */ // GIR_Coverage, 2926, |
| 9669 | /* 27634 */ GIR_EraseRootFromParent_Done, |
| 9670 | /* 27635 */ // Label 629: @27635 |
| 9671 | /* 27635 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 630*/ GIMT_Encode4(27695), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3784 // |
| 9672 | /* 27642 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9673 | /* 27646 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9674 | /* 27650 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9675 | /* 27654 */ // (xor:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VEOR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 9676 | /* 27654 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9677 | /* 27657 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9678 | /* 27661 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9679 | /* 27666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 9680 | /* 27669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9681 | /* 27671 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9682 | /* 27673 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9683 | /* 27675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9684 | /* 27678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9685 | /* 27684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9686 | /* 27690 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9687 | /* 27693 */ GIR_RootConstrainSelectedInstOperands, |
| 9688 | /* 27694 */ // GIR_Coverage, 3784, |
| 9689 | /* 27694 */ GIR_EraseRootFromParent_Done, |
| 9690 | /* 27695 */ // Label 630: @27695 |
| 9691 | /* 27695 */ GIM_Reject, |
| 9692 | /* 27696 */ // Label 628: @27696 |
| 9693 | /* 27696 */ GIM_Reject, |
| 9694 | /* 27697 */ // Label 602: @27697 |
| 9695 | /* 27697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 631*/ GIMT_Encode4(27742), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1297 // |
| 9696 | /* 27704 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9697 | /* 27707 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 9698 | /* 27710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9699 | /* 27714 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9700 | /* 27718 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9701 | /* 27722 */ // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 9702 | /* 27722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd), |
| 9703 | /* 27725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9704 | /* 27727 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9705 | /* 27729 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9706 | /* 27731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9707 | /* 27734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9708 | /* 27740 */ GIR_RootConstrainSelectedInstOperands, |
| 9709 | /* 27741 */ // GIR_Coverage, 1297, |
| 9710 | /* 27741 */ GIR_EraseRootFromParent_Done, |
| 9711 | /* 27742 */ // Label 631: @27742 |
| 9712 | /* 27742 */ GIM_Reject, |
| 9713 | /* 27743 */ // Label 603: @27743 |
| 9714 | /* 27743 */ GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(27854), |
| 9715 | /* 27748 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9716 | /* 27751 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9717 | /* 27754 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 633*/ GIMT_Encode4(27793), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1298 // |
| 9718 | /* 27761 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9719 | /* 27765 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9720 | /* 27769 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9721 | /* 27773 */ // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 9722 | /* 27773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 9723 | /* 27776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9724 | /* 27778 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9725 | /* 27780 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9726 | /* 27782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9727 | /* 27785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9728 | /* 27791 */ GIR_RootConstrainSelectedInstOperands, |
| 9729 | /* 27792 */ // GIR_Coverage, 1298, |
| 9730 | /* 27792 */ GIR_EraseRootFromParent_Done, |
| 9731 | /* 27793 */ // Label 633: @27793 |
| 9732 | /* 27793 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 634*/ GIMT_Encode4(27853), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3788 // |
| 9733 | /* 27800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9734 | /* 27804 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9735 | /* 27808 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9736 | /* 27812 */ // (xor:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VEOR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 9737 | /* 27812 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9738 | /* 27815 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9739 | /* 27819 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9740 | /* 27824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 9741 | /* 27827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9742 | /* 27829 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9743 | /* 27831 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9744 | /* 27833 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9745 | /* 27836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9746 | /* 27842 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9747 | /* 27848 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9748 | /* 27851 */ GIR_RootConstrainSelectedInstOperands, |
| 9749 | /* 27852 */ // GIR_Coverage, 3788, |
| 9750 | /* 27852 */ GIR_EraseRootFromParent_Done, |
| 9751 | /* 27853 */ // Label 634: @27853 |
| 9752 | /* 27853 */ GIM_Reject, |
| 9753 | /* 27854 */ // Label 632: @27854 |
| 9754 | /* 27854 */ GIM_Reject, |
| 9755 | /* 27855 */ // Label 604: @27855 |
| 9756 | /* 27855 */ GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(27966), |
| 9757 | /* 27860 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 9758 | /* 27863 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 9759 | /* 27866 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 636*/ GIMT_Encode4(27905), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2927 // |
| 9760 | /* 27873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9761 | /* 27877 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9762 | /* 27881 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9763 | /* 27885 */ // (xor:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VEORq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) |
| 9764 | /* 27885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq), |
| 9765 | /* 27888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9766 | /* 27890 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS |
| 9767 | /* 27892 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS |
| 9768 | /* 27894 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9769 | /* 27897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9770 | /* 27903 */ GIR_RootConstrainSelectedInstOperands, |
| 9771 | /* 27904 */ // GIR_Coverage, 2927, |
| 9772 | /* 27904 */ GIR_EraseRootFromParent_Done, |
| 9773 | /* 27905 */ // Label 636: @27905 |
| 9774 | /* 27905 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 637*/ GIMT_Encode4(27965), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3792 // |
| 9775 | /* 27912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9776 | /* 27916 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9777 | /* 27920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9778 | /* 27924 */ // (xor:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VEOR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) |
| 9779 | /* 27924 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9780 | /* 27927 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9781 | /* 27931 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9782 | /* 27936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR), |
| 9783 | /* 27939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9784 | /* 27941 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9785 | /* 27943 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9786 | /* 27945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9787 | /* 27948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9788 | /* 27954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9789 | /* 27960 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9790 | /* 27963 */ GIR_RootConstrainSelectedInstOperands, |
| 9791 | /* 27964 */ // GIR_Coverage, 3792, |
| 9792 | /* 27964 */ GIR_EraseRootFromParent_Done, |
| 9793 | /* 27965 */ // Label 637: @27965 |
| 9794 | /* 27965 */ GIM_Reject, |
| 9795 | /* 27966 */ // Label 635: @27966 |
| 9796 | /* 27966 */ GIM_Reject, |
| 9797 | /* 27967 */ // Label 605: @27967 |
| 9798 | /* 27967 */ GIM_Reject, |
| 9799 | /* 27968 */ // Label 8: @27968 |
| 9800 | /* 27968 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 644*/ GIMT_Encode4(28477), |
| 9801 | /* 27979 */ /*GILLT_v8s8*//*Label 638*/ GIMT_Encode4(28003), |
| 9802 | /* 27983 */ /*GILLT_v16s8*//*Label 639*/ GIMT_Encode4(28049), |
| 9803 | /* 27987 */ /*GILLT_v4s16*//*Label 640*/ GIMT_Encode4(28161), |
| 9804 | /* 27991 */ /*GILLT_v8s16*//*Label 641*/ GIMT_Encode4(28207), |
| 9805 | /* 27995 */ /*GILLT_v2s32*//*Label 642*/ GIMT_Encode4(28319), |
| 9806 | /* 27999 */ /*GILLT_v4s32*//*Label 643*/ GIMT_Encode4(28365), |
| 9807 | /* 28003 */ // Label 638: @28003 |
| 9808 | /* 28003 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 645*/ GIMT_Encode4(28048), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1323 // |
| 9809 | /* 28010 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 9810 | /* 28013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 9811 | /* 28016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9812 | /* 28020 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9813 | /* 28024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9814 | /* 28028 */ // (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 9815 | /* 28028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i8), |
| 9816 | /* 28031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9817 | /* 28033 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9818 | /* 28035 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9819 | /* 28037 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9820 | /* 28040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9821 | /* 28046 */ GIR_RootConstrainSelectedInstOperands, |
| 9822 | /* 28047 */ // GIR_Coverage, 1323, |
| 9823 | /* 28047 */ GIR_EraseRootFromParent_Done, |
| 9824 | /* 28048 */ // Label 645: @28048 |
| 9825 | /* 28048 */ GIM_Reject, |
| 9826 | /* 28049 */ // Label 639: @28049 |
| 9827 | /* 28049 */ GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(28160), |
| 9828 | /* 28054 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 9829 | /* 28057 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 9830 | /* 28060 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 647*/ GIMT_Encode4(28099), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1324 // |
| 9831 | /* 28067 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9832 | /* 28071 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9833 | /* 28075 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9834 | /* 28079 */ // (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 9835 | /* 28079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv16i8), |
| 9836 | /* 28082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9837 | /* 28084 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9838 | /* 28086 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9839 | /* 28088 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9840 | /* 28091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9841 | /* 28097 */ GIR_RootConstrainSelectedInstOperands, |
| 9842 | /* 28098 */ // GIR_Coverage, 1324, |
| 9843 | /* 28098 */ GIR_EraseRootFromParent_Done, |
| 9844 | /* 28099 */ // Label 647: @28099 |
| 9845 | /* 28099 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 648*/ GIMT_Encode4(28159), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3943 // |
| 9846 | /* 28106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9847 | /* 28110 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9848 | /* 28114 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9849 | /* 28118 */ // (abds:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 9850 | /* 28118 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9851 | /* 28121 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9852 | /* 28125 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9853 | /* 28130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8), |
| 9854 | /* 28133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9855 | /* 28135 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9856 | /* 28137 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9857 | /* 28139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9858 | /* 28142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9859 | /* 28148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9860 | /* 28154 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9861 | /* 28157 */ GIR_RootConstrainSelectedInstOperands, |
| 9862 | /* 28158 */ // GIR_Coverage, 3943, |
| 9863 | /* 28158 */ GIR_EraseRootFromParent_Done, |
| 9864 | /* 28159 */ // Label 648: @28159 |
| 9865 | /* 28159 */ GIM_Reject, |
| 9866 | /* 28160 */ // Label 646: @28160 |
| 9867 | /* 28160 */ GIM_Reject, |
| 9868 | /* 28161 */ // Label 640: @28161 |
| 9869 | /* 28161 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 649*/ GIMT_Encode4(28206), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1319 // |
| 9870 | /* 28168 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 9871 | /* 28171 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 9872 | /* 28174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9873 | /* 28178 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9874 | /* 28182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9875 | /* 28186 */ // (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 9876 | /* 28186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i16), |
| 9877 | /* 28189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9878 | /* 28191 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9879 | /* 28193 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9880 | /* 28195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9881 | /* 28198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9882 | /* 28204 */ GIR_RootConstrainSelectedInstOperands, |
| 9883 | /* 28205 */ // GIR_Coverage, 1319, |
| 9884 | /* 28205 */ GIR_EraseRootFromParent_Done, |
| 9885 | /* 28206 */ // Label 649: @28206 |
| 9886 | /* 28206 */ GIM_Reject, |
| 9887 | /* 28207 */ // Label 641: @28207 |
| 9888 | /* 28207 */ GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(28318), |
| 9889 | /* 28212 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 9890 | /* 28215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 9891 | /* 28218 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 651*/ GIMT_Encode4(28257), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1321 // |
| 9892 | /* 28225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9893 | /* 28229 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9894 | /* 28233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9895 | /* 28237 */ // (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 9896 | /* 28237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i16), |
| 9897 | /* 28240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9898 | /* 28242 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9899 | /* 28244 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9900 | /* 28246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9901 | /* 28249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9902 | /* 28255 */ GIR_RootConstrainSelectedInstOperands, |
| 9903 | /* 28256 */ // GIR_Coverage, 1321, |
| 9904 | /* 28256 */ GIR_EraseRootFromParent_Done, |
| 9905 | /* 28257 */ // Label 651: @28257 |
| 9906 | /* 28257 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 652*/ GIMT_Encode4(28317), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3946 // |
| 9907 | /* 28264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9908 | /* 28268 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9909 | /* 28272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9910 | /* 28276 */ // (abds:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 9911 | /* 28276 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9912 | /* 28279 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9913 | /* 28283 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9914 | /* 28288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16), |
| 9915 | /* 28291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9916 | /* 28293 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9917 | /* 28295 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9918 | /* 28297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9919 | /* 28300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9920 | /* 28306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9921 | /* 28312 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9922 | /* 28315 */ GIR_RootConstrainSelectedInstOperands, |
| 9923 | /* 28316 */ // GIR_Coverage, 3946, |
| 9924 | /* 28316 */ GIR_EraseRootFromParent_Done, |
| 9925 | /* 28317 */ // Label 652: @28317 |
| 9926 | /* 28317 */ GIM_Reject, |
| 9927 | /* 28318 */ // Label 650: @28318 |
| 9928 | /* 28318 */ GIM_Reject, |
| 9929 | /* 28319 */ // Label 642: @28319 |
| 9930 | /* 28319 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 653*/ GIMT_Encode4(28364), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1320 // |
| 9931 | /* 28326 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 9932 | /* 28329 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 9933 | /* 28332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9934 | /* 28336 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9935 | /* 28340 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 9936 | /* 28344 */ // (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 9937 | /* 28344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv2i32), |
| 9938 | /* 28347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9939 | /* 28349 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9940 | /* 28351 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9941 | /* 28353 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9942 | /* 28356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9943 | /* 28362 */ GIR_RootConstrainSelectedInstOperands, |
| 9944 | /* 28363 */ // GIR_Coverage, 1320, |
| 9945 | /* 28363 */ GIR_EraseRootFromParent_Done, |
| 9946 | /* 28364 */ // Label 653: @28364 |
| 9947 | /* 28364 */ GIM_Reject, |
| 9948 | /* 28365 */ // Label 643: @28365 |
| 9949 | /* 28365 */ GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(28476), |
| 9950 | /* 28370 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 9951 | /* 28373 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 9952 | /* 28376 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 655*/ GIMT_Encode4(28415), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1322 // |
| 9953 | /* 28383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9954 | /* 28387 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9955 | /* 28391 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 9956 | /* 28395 */ // (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 9957 | /* 28395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i32), |
| 9958 | /* 28398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 9959 | /* 28400 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 9960 | /* 28402 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 9961 | /* 28404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 9962 | /* 28407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9963 | /* 28413 */ GIR_RootConstrainSelectedInstOperands, |
| 9964 | /* 28414 */ // GIR_Coverage, 1322, |
| 9965 | /* 28414 */ GIR_EraseRootFromParent_Done, |
| 9966 | /* 28415 */ // Label 655: @28415 |
| 9967 | /* 28415 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 656*/ GIMT_Encode4(28475), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3950 // |
| 9968 | /* 28422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9969 | /* 28426 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9970 | /* 28430 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 9971 | /* 28434 */ // (abds:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 9972 | /* 28434 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 9973 | /* 28437 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 9974 | /* 28441 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 9975 | /* 28446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32), |
| 9976 | /* 28449 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 9977 | /* 28451 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 9978 | /* 28453 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 9979 | /* 28455 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9980 | /* 28458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9981 | /* 28464 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 9982 | /* 28470 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9983 | /* 28473 */ GIR_RootConstrainSelectedInstOperands, |
| 9984 | /* 28474 */ // GIR_Coverage, 3950, |
| 9985 | /* 28474 */ GIR_EraseRootFromParent_Done, |
| 9986 | /* 28475 */ // Label 656: @28475 |
| 9987 | /* 28475 */ GIM_Reject, |
| 9988 | /* 28476 */ // Label 654: @28476 |
| 9989 | /* 28476 */ GIM_Reject, |
| 9990 | /* 28477 */ // Label 644: @28477 |
| 9991 | /* 28477 */ GIM_Reject, |
| 9992 | /* 28478 */ // Label 9: @28478 |
| 9993 | /* 28478 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 663*/ GIMT_Encode4(28987), |
| 9994 | /* 28489 */ /*GILLT_v8s8*//*Label 657*/ GIMT_Encode4(28513), |
| 9995 | /* 28493 */ /*GILLT_v16s8*//*Label 658*/ GIMT_Encode4(28559), |
| 9996 | /* 28497 */ /*GILLT_v4s16*//*Label 659*/ GIMT_Encode4(28671), |
| 9997 | /* 28501 */ /*GILLT_v8s16*//*Label 660*/ GIMT_Encode4(28717), |
| 9998 | /* 28505 */ /*GILLT_v2s32*//*Label 661*/ GIMT_Encode4(28829), |
| 9999 | /* 28509 */ /*GILLT_v4s32*//*Label 662*/ GIMT_Encode4(28875), |
| 10000 | /* 28513 */ // Label 657: @28513 |
| 10001 | /* 28513 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 664*/ GIMT_Encode4(28558), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1329 // |
| 10002 | /* 28520 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 10003 | /* 28523 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 10004 | /* 28526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10005 | /* 28530 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10006 | /* 28534 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10007 | /* 28538 */ // (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 10008 | /* 28538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i8), |
| 10009 | /* 28541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10010 | /* 28543 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10011 | /* 28545 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10012 | /* 28547 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10013 | /* 28550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10014 | /* 28556 */ GIR_RootConstrainSelectedInstOperands, |
| 10015 | /* 28557 */ // GIR_Coverage, 1329, |
| 10016 | /* 28557 */ GIR_EraseRootFromParent_Done, |
| 10017 | /* 28558 */ // Label 664: @28558 |
| 10018 | /* 28558 */ GIM_Reject, |
| 10019 | /* 28559 */ // Label 658: @28559 |
| 10020 | /* 28559 */ GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(28670), |
| 10021 | /* 28564 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10022 | /* 28567 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10023 | /* 28570 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 666*/ GIMT_Encode4(28609), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1330 // |
| 10024 | /* 28577 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10025 | /* 28581 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10026 | /* 28585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10027 | /* 28589 */ // (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 10028 | /* 28589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv16i8), |
| 10029 | /* 28592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10030 | /* 28594 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10031 | /* 28596 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10032 | /* 28598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10033 | /* 28601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10034 | /* 28607 */ GIR_RootConstrainSelectedInstOperands, |
| 10035 | /* 28608 */ // GIR_Coverage, 1330, |
| 10036 | /* 28608 */ GIR_EraseRootFromParent_Done, |
| 10037 | /* 28609 */ // Label 666: @28609 |
| 10038 | /* 28609 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 667*/ GIMT_Encode4(28669), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3954 // |
| 10039 | /* 28616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10040 | /* 28620 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10041 | /* 28624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10042 | /* 28628 */ // (abdu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10043 | /* 28628 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10044 | /* 28631 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10045 | /* 28635 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10046 | /* 28640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8), |
| 10047 | /* 28643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10048 | /* 28645 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10049 | /* 28647 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10050 | /* 28649 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10051 | /* 28652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10052 | /* 28658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10053 | /* 28664 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10054 | /* 28667 */ GIR_RootConstrainSelectedInstOperands, |
| 10055 | /* 28668 */ // GIR_Coverage, 3954, |
| 10056 | /* 28668 */ GIR_EraseRootFromParent_Done, |
| 10057 | /* 28669 */ // Label 667: @28669 |
| 10058 | /* 28669 */ GIM_Reject, |
| 10059 | /* 28670 */ // Label 665: @28670 |
| 10060 | /* 28670 */ GIM_Reject, |
| 10061 | /* 28671 */ // Label 659: @28671 |
| 10062 | /* 28671 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 668*/ GIMT_Encode4(28716), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1325 // |
| 10063 | /* 28678 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10064 | /* 28681 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 10065 | /* 28684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10066 | /* 28688 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10067 | /* 28692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10068 | /* 28696 */ // (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 10069 | /* 28696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i16), |
| 10070 | /* 28699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10071 | /* 28701 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10072 | /* 28703 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10073 | /* 28705 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10074 | /* 28708 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10075 | /* 28714 */ GIR_RootConstrainSelectedInstOperands, |
| 10076 | /* 28715 */ // GIR_Coverage, 1325, |
| 10077 | /* 28715 */ GIR_EraseRootFromParent_Done, |
| 10078 | /* 28716 */ // Label 668: @28716 |
| 10079 | /* 28716 */ GIM_Reject, |
| 10080 | /* 28717 */ // Label 660: @28717 |
| 10081 | /* 28717 */ GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(28828), |
| 10082 | /* 28722 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10083 | /* 28725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10084 | /* 28728 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 670*/ GIMT_Encode4(28767), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1327 // |
| 10085 | /* 28735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10086 | /* 28739 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10087 | /* 28743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10088 | /* 28747 */ // (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 10089 | /* 28747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i16), |
| 10090 | /* 28750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10091 | /* 28752 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10092 | /* 28754 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10093 | /* 28756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10094 | /* 28759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10095 | /* 28765 */ GIR_RootConstrainSelectedInstOperands, |
| 10096 | /* 28766 */ // GIR_Coverage, 1327, |
| 10097 | /* 28766 */ GIR_EraseRootFromParent_Done, |
| 10098 | /* 28767 */ // Label 670: @28767 |
| 10099 | /* 28767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 671*/ GIMT_Encode4(28827), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3958 // |
| 10100 | /* 28774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10101 | /* 28778 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10102 | /* 28782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10103 | /* 28786 */ // (abdu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10104 | /* 28786 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10105 | /* 28789 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10106 | /* 28793 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10107 | /* 28798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16), |
| 10108 | /* 28801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10109 | /* 28803 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10110 | /* 28805 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10111 | /* 28807 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10112 | /* 28810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10113 | /* 28816 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10114 | /* 28822 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10115 | /* 28825 */ GIR_RootConstrainSelectedInstOperands, |
| 10116 | /* 28826 */ // GIR_Coverage, 3958, |
| 10117 | /* 28826 */ GIR_EraseRootFromParent_Done, |
| 10118 | /* 28827 */ // Label 671: @28827 |
| 10119 | /* 28827 */ GIM_Reject, |
| 10120 | /* 28828 */ // Label 669: @28828 |
| 10121 | /* 28828 */ GIM_Reject, |
| 10122 | /* 28829 */ // Label 661: @28829 |
| 10123 | /* 28829 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 672*/ GIMT_Encode4(28874), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1326 // |
| 10124 | /* 28836 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10125 | /* 28839 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10126 | /* 28842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10127 | /* 28846 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10128 | /* 28850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10129 | /* 28854 */ // (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 10130 | /* 28854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv2i32), |
| 10131 | /* 28857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10132 | /* 28859 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10133 | /* 28861 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10134 | /* 28863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10135 | /* 28866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10136 | /* 28872 */ GIR_RootConstrainSelectedInstOperands, |
| 10137 | /* 28873 */ // GIR_Coverage, 1326, |
| 10138 | /* 28873 */ GIR_EraseRootFromParent_Done, |
| 10139 | /* 28874 */ // Label 672: @28874 |
| 10140 | /* 28874 */ GIM_Reject, |
| 10141 | /* 28875 */ // Label 662: @28875 |
| 10142 | /* 28875 */ GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(28986), |
| 10143 | /* 28880 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10144 | /* 28883 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10145 | /* 28886 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 674*/ GIMT_Encode4(28925), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1328 // |
| 10146 | /* 28893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10147 | /* 28897 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10148 | /* 28901 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10149 | /* 28905 */ // (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 10150 | /* 28905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i32), |
| 10151 | /* 28908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10152 | /* 28910 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 10153 | /* 28912 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 10154 | /* 28914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10155 | /* 28917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10156 | /* 28923 */ GIR_RootConstrainSelectedInstOperands, |
| 10157 | /* 28924 */ // GIR_Coverage, 1328, |
| 10158 | /* 28924 */ GIR_EraseRootFromParent_Done, |
| 10159 | /* 28925 */ // Label 674: @28925 |
| 10160 | /* 28925 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 675*/ GIMT_Encode4(28985), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3962 // |
| 10161 | /* 28932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10162 | /* 28936 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10163 | /* 28940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10164 | /* 28944 */ // (abdu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10165 | /* 28944 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10166 | /* 28947 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10167 | /* 28951 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10168 | /* 28956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32), |
| 10169 | /* 28959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10170 | /* 28961 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10171 | /* 28963 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10172 | /* 28965 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10173 | /* 28968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10174 | /* 28974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10175 | /* 28980 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10176 | /* 28983 */ GIR_RootConstrainSelectedInstOperands, |
| 10177 | /* 28984 */ // GIR_Coverage, 3962, |
| 10178 | /* 28984 */ GIR_EraseRootFromParent_Done, |
| 10179 | /* 28985 */ // Label 675: @28985 |
| 10180 | /* 28985 */ GIM_Reject, |
| 10181 | /* 28986 */ // Label 673: @28986 |
| 10182 | /* 28986 */ GIM_Reject, |
| 10183 | /* 28987 */ // Label 663: @28987 |
| 10184 | /* 28987 */ GIM_Reject, |
| 10185 | /* 28988 */ // Label 10: @28988 |
| 10186 | /* 28988 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 679*/ GIMT_Encode4(29214), |
| 10187 | /* 28999 */ /*GILLT_v16s8*//*Label 676*/ GIMT_Encode4(29019), GIMT_Encode4(0), |
| 10188 | /* 29007 */ /*GILLT_v8s16*//*Label 677*/ GIMT_Encode4(29084), GIMT_Encode4(0), |
| 10189 | /* 29015 */ /*GILLT_v4s32*//*Label 678*/ GIMT_Encode4(29149), |
| 10190 | /* 29019 */ // Label 676: @29019 |
| 10191 | /* 29019 */ GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(29083), // Rule ID 4002 // |
| 10192 | /* 29024 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10193 | /* 29027 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10194 | /* 29030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10195 | /* 29034 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10196 | /* 29038 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10197 | /* 29042 */ // (avgflooru:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10198 | /* 29042 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10199 | /* 29045 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10200 | /* 29049 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10201 | /* 29054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8), |
| 10202 | /* 29057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10203 | /* 29059 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10204 | /* 29061 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10205 | /* 29063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10206 | /* 29066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10207 | /* 29072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10208 | /* 29078 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10209 | /* 29081 */ GIR_RootConstrainSelectedInstOperands, |
| 10210 | /* 29082 */ // GIR_Coverage, 4002, |
| 10211 | /* 29082 */ GIR_EraseRootFromParent_Done, |
| 10212 | /* 29083 */ // Label 680: @29083 |
| 10213 | /* 29083 */ GIM_Reject, |
| 10214 | /* 29084 */ // Label 677: @29084 |
| 10215 | /* 29084 */ GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(29148), // Rule ID 4006 // |
| 10216 | /* 29089 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10217 | /* 29092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10218 | /* 29095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10219 | /* 29099 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10220 | /* 29103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10221 | /* 29107 */ // (avgflooru:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10222 | /* 29107 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10223 | /* 29110 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10224 | /* 29114 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10225 | /* 29119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16), |
| 10226 | /* 29122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10227 | /* 29124 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10228 | /* 29126 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10229 | /* 29128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10230 | /* 29131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10231 | /* 29137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10232 | /* 29143 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10233 | /* 29146 */ GIR_RootConstrainSelectedInstOperands, |
| 10234 | /* 29147 */ // GIR_Coverage, 4006, |
| 10235 | /* 29147 */ GIR_EraseRootFromParent_Done, |
| 10236 | /* 29148 */ // Label 681: @29148 |
| 10237 | /* 29148 */ GIM_Reject, |
| 10238 | /* 29149 */ // Label 678: @29149 |
| 10239 | /* 29149 */ GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(29213), // Rule ID 4010 // |
| 10240 | /* 29154 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10241 | /* 29157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10242 | /* 29160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10243 | /* 29164 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10244 | /* 29168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10245 | /* 29172 */ // (avgflooru:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10246 | /* 29172 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10247 | /* 29175 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10248 | /* 29179 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10249 | /* 29184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32), |
| 10250 | /* 29187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10251 | /* 29189 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10252 | /* 29191 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10253 | /* 29193 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10254 | /* 29196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10255 | /* 29202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10256 | /* 29208 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10257 | /* 29211 */ GIR_RootConstrainSelectedInstOperands, |
| 10258 | /* 29212 */ // GIR_Coverage, 4010, |
| 10259 | /* 29212 */ GIR_EraseRootFromParent_Done, |
| 10260 | /* 29213 */ // Label 682: @29213 |
| 10261 | /* 29213 */ GIM_Reject, |
| 10262 | /* 29214 */ // Label 679: @29214 |
| 10263 | /* 29214 */ GIM_Reject, |
| 10264 | /* 29215 */ // Label 11: @29215 |
| 10265 | /* 29215 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 686*/ GIMT_Encode4(29441), |
| 10266 | /* 29226 */ /*GILLT_v16s8*//*Label 683*/ GIMT_Encode4(29246), GIMT_Encode4(0), |
| 10267 | /* 29234 */ /*GILLT_v8s16*//*Label 684*/ GIMT_Encode4(29311), GIMT_Encode4(0), |
| 10268 | /* 29242 */ /*GILLT_v4s32*//*Label 685*/ GIMT_Encode4(29376), |
| 10269 | /* 29246 */ // Label 683: @29246 |
| 10270 | /* 29246 */ GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(29310), // Rule ID 3978 // |
| 10271 | /* 29251 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10272 | /* 29254 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10273 | /* 29257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10274 | /* 29261 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10275 | /* 29265 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10276 | /* 29269 */ // (avgceilu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10277 | /* 29269 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10278 | /* 29272 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10279 | /* 29276 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10280 | /* 29281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8), |
| 10281 | /* 29284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10282 | /* 29286 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10283 | /* 29288 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10284 | /* 29290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10285 | /* 29293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10286 | /* 29299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10287 | /* 29305 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10288 | /* 29308 */ GIR_RootConstrainSelectedInstOperands, |
| 10289 | /* 29309 */ // GIR_Coverage, 3978, |
| 10290 | /* 29309 */ GIR_EraseRootFromParent_Done, |
| 10291 | /* 29310 */ // Label 687: @29310 |
| 10292 | /* 29310 */ GIM_Reject, |
| 10293 | /* 29311 */ // Label 684: @29311 |
| 10294 | /* 29311 */ GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(29375), // Rule ID 3982 // |
| 10295 | /* 29316 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10296 | /* 29319 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10297 | /* 29322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10298 | /* 29326 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10299 | /* 29330 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10300 | /* 29334 */ // (avgceilu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10301 | /* 29334 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10302 | /* 29337 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10303 | /* 29341 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10304 | /* 29346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16), |
| 10305 | /* 29349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10306 | /* 29351 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10307 | /* 29353 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10308 | /* 29355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10309 | /* 29358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10310 | /* 29364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10311 | /* 29370 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10312 | /* 29373 */ GIR_RootConstrainSelectedInstOperands, |
| 10313 | /* 29374 */ // GIR_Coverage, 3982, |
| 10314 | /* 29374 */ GIR_EraseRootFromParent_Done, |
| 10315 | /* 29375 */ // Label 688: @29375 |
| 10316 | /* 29375 */ GIM_Reject, |
| 10317 | /* 29376 */ // Label 685: @29376 |
| 10318 | /* 29376 */ GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(29440), // Rule ID 3986 // |
| 10319 | /* 29381 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10320 | /* 29384 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10321 | /* 29387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10322 | /* 29391 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10323 | /* 29395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10324 | /* 29399 */ // (avgceilu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10325 | /* 29399 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10326 | /* 29402 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10327 | /* 29406 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10328 | /* 29411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32), |
| 10329 | /* 29414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10330 | /* 29416 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10331 | /* 29418 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10332 | /* 29420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10333 | /* 29423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10334 | /* 29429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10335 | /* 29435 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10336 | /* 29438 */ GIR_RootConstrainSelectedInstOperands, |
| 10337 | /* 29439 */ // GIR_Coverage, 3986, |
| 10338 | /* 29439 */ GIR_EraseRootFromParent_Done, |
| 10339 | /* 29440 */ // Label 689: @29440 |
| 10340 | /* 29440 */ GIM_Reject, |
| 10341 | /* 29441 */ // Label 686: @29441 |
| 10342 | /* 29441 */ GIM_Reject, |
| 10343 | /* 29442 */ // Label 12: @29442 |
| 10344 | /* 29442 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 693*/ GIMT_Encode4(29668), |
| 10345 | /* 29453 */ /*GILLT_v16s8*//*Label 690*/ GIMT_Encode4(29473), GIMT_Encode4(0), |
| 10346 | /* 29461 */ /*GILLT_v8s16*//*Label 691*/ GIMT_Encode4(29538), GIMT_Encode4(0), |
| 10347 | /* 29469 */ /*GILLT_v4s32*//*Label 692*/ GIMT_Encode4(29603), |
| 10348 | /* 29473 */ // Label 690: @29473 |
| 10349 | /* 29473 */ GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(29537), // Rule ID 3991 // |
| 10350 | /* 29478 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10351 | /* 29481 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10352 | /* 29484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10353 | /* 29488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10354 | /* 29492 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10355 | /* 29496 */ // (avgfloors:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10356 | /* 29496 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10357 | /* 29499 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10358 | /* 29503 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10359 | /* 29508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8), |
| 10360 | /* 29511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10361 | /* 29513 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10362 | /* 29515 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10363 | /* 29517 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10364 | /* 29520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10365 | /* 29526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10366 | /* 29532 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10367 | /* 29535 */ GIR_RootConstrainSelectedInstOperands, |
| 10368 | /* 29536 */ // GIR_Coverage, 3991, |
| 10369 | /* 29536 */ GIR_EraseRootFromParent_Done, |
| 10370 | /* 29537 */ // Label 694: @29537 |
| 10371 | /* 29537 */ GIM_Reject, |
| 10372 | /* 29538 */ // Label 691: @29538 |
| 10373 | /* 29538 */ GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(29602), // Rule ID 3994 // |
| 10374 | /* 29543 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10375 | /* 29546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10376 | /* 29549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10377 | /* 29553 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10378 | /* 29557 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10379 | /* 29561 */ // (avgfloors:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10380 | /* 29561 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10381 | /* 29564 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10382 | /* 29568 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10383 | /* 29573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16), |
| 10384 | /* 29576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10385 | /* 29578 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10386 | /* 29580 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10387 | /* 29582 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10388 | /* 29585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10389 | /* 29591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10390 | /* 29597 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10391 | /* 29600 */ GIR_RootConstrainSelectedInstOperands, |
| 10392 | /* 29601 */ // GIR_Coverage, 3994, |
| 10393 | /* 29601 */ GIR_EraseRootFromParent_Done, |
| 10394 | /* 29602 */ // Label 695: @29602 |
| 10395 | /* 29602 */ GIM_Reject, |
| 10396 | /* 29603 */ // Label 692: @29603 |
| 10397 | /* 29603 */ GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(29667), // Rule ID 3998 // |
| 10398 | /* 29608 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10399 | /* 29611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10400 | /* 29614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10401 | /* 29618 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10402 | /* 29622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10403 | /* 29626 */ // (avgfloors:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10404 | /* 29626 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10405 | /* 29629 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10406 | /* 29633 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10407 | /* 29638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32), |
| 10408 | /* 29641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10409 | /* 29643 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10410 | /* 29645 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10411 | /* 29647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10412 | /* 29650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10413 | /* 29656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10414 | /* 29662 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10415 | /* 29665 */ GIR_RootConstrainSelectedInstOperands, |
| 10416 | /* 29666 */ // GIR_Coverage, 3998, |
| 10417 | /* 29666 */ GIR_EraseRootFromParent_Done, |
| 10418 | /* 29667 */ // Label 696: @29667 |
| 10419 | /* 29667 */ GIM_Reject, |
| 10420 | /* 29668 */ // Label 693: @29668 |
| 10421 | /* 29668 */ GIM_Reject, |
| 10422 | /* 29669 */ // Label 13: @29669 |
| 10423 | /* 29669 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 700*/ GIMT_Encode4(29895), |
| 10424 | /* 29680 */ /*GILLT_v16s8*//*Label 697*/ GIMT_Encode4(29700), GIMT_Encode4(0), |
| 10425 | /* 29688 */ /*GILLT_v8s16*//*Label 698*/ GIMT_Encode4(29765), GIMT_Encode4(0), |
| 10426 | /* 29696 */ /*GILLT_v4s32*//*Label 699*/ GIMT_Encode4(29830), |
| 10427 | /* 29700 */ // Label 697: @29700 |
| 10428 | /* 29700 */ GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(29764), // Rule ID 3967 // |
| 10429 | /* 29705 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 10430 | /* 29708 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 10431 | /* 29711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10432 | /* 29715 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10433 | /* 29719 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10434 | /* 29723 */ // (avgceils:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 10435 | /* 29723 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10436 | /* 29726 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10437 | /* 29730 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10438 | /* 29735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8), |
| 10439 | /* 29738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10440 | /* 29740 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10441 | /* 29742 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10442 | /* 29744 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10443 | /* 29747 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10444 | /* 29753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10445 | /* 29759 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10446 | /* 29762 */ GIR_RootConstrainSelectedInstOperands, |
| 10447 | /* 29763 */ // GIR_Coverage, 3967, |
| 10448 | /* 29763 */ GIR_EraseRootFromParent_Done, |
| 10449 | /* 29764 */ // Label 701: @29764 |
| 10450 | /* 29764 */ GIM_Reject, |
| 10451 | /* 29765 */ // Label 698: @29765 |
| 10452 | /* 29765 */ GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(29829), // Rule ID 3970 // |
| 10453 | /* 29770 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 10454 | /* 29773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 10455 | /* 29776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10456 | /* 29780 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10457 | /* 29784 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10458 | /* 29788 */ // (avgceils:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 10459 | /* 29788 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10460 | /* 29791 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10461 | /* 29795 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10462 | /* 29800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16), |
| 10463 | /* 29803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10464 | /* 29805 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10465 | /* 29807 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10466 | /* 29809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10467 | /* 29812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10468 | /* 29818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10469 | /* 29824 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10470 | /* 29827 */ GIR_RootConstrainSelectedInstOperands, |
| 10471 | /* 29828 */ // GIR_Coverage, 3970, |
| 10472 | /* 29828 */ GIR_EraseRootFromParent_Done, |
| 10473 | /* 29829 */ // Label 702: @29829 |
| 10474 | /* 29829 */ GIM_Reject, |
| 10475 | /* 29830 */ // Label 699: @29830 |
| 10476 | /* 29830 */ GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(29894), // Rule ID 3974 // |
| 10477 | /* 29835 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 10478 | /* 29838 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 10479 | /* 29841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10480 | /* 29845 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10481 | /* 29849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 10482 | /* 29853 */ // (avgceils:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 10483 | /* 29853 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10484 | /* 29856 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10485 | /* 29860 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10486 | /* 29865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32), |
| 10487 | /* 29868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 10488 | /* 29870 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 10489 | /* 29872 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 10490 | /* 29874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10491 | /* 29877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10492 | /* 29883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10493 | /* 29889 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10494 | /* 29892 */ GIR_RootConstrainSelectedInstOperands, |
| 10495 | /* 29893 */ // GIR_Coverage, 3974, |
| 10496 | /* 29893 */ GIR_EraseRootFromParent_Done, |
| 10497 | /* 29894 */ // Label 703: @29894 |
| 10498 | /* 29894 */ GIM_Reject, |
| 10499 | /* 29895 */ // Label 700: @29895 |
| 10500 | /* 29895 */ GIM_Reject, |
| 10501 | /* 29896 */ // Label 14: @29896 |
| 10502 | /* 29896 */ GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(30562), |
| 10503 | /* 29901 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 10504 | /* 29904 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 709*/ GIMT_Encode4(30561), |
| 10505 | /* 29915 */ /*GILLT_v16s8*//*Label 705*/ GIMT_Encode4(29939), GIMT_Encode4(0), |
| 10506 | /* 29923 */ /*GILLT_v8s16*//*Label 706*/ GIMT_Encode4(30045), GIMT_Encode4(0), |
| 10507 | /* 29931 */ /*GILLT_v4s32*//*Label 707*/ GIMT_Encode4(30256), |
| 10508 | /* 29935 */ /*GILLT_v2s64*//*Label 708*/ GIMT_Encode4(30455), |
| 10509 | /* 29939 */ // Label 705: @29939 |
| 10510 | /* 29939 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 710*/ GIMT_Encode4(30044), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3413 // |
| 10511 | /* 29946 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 10512 | /* 29949 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 10513 | /* 29952 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID), |
| 10514 | /* 29956 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10515 | /* 29960 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10516 | /* 29964 */ // (concat_vectors:{ *:[v16i8] } DPR:{ *:[v8i8] }:$Dn, DPR:{ *:[v8i8] }:$Dm) => (INSERT_SUBREG:{ *:[v16i8] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), DPR:{ *:[v8i8] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v8i8] }:$Dm, dsub_1:{ *:[i32] }) |
| 10517 | /* 29964 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 10518 | /* 29967 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10519 | /* 29971 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10520 | /* 29976 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10521 | /* 29978 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 10522 | /* 29981 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10523 | /* 29985 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10524 | /* 29990 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10525 | /* 29993 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn |
| 10526 | /* 29997 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 10527 | /* 30000 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10528 | /* 30005 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10529 | /* 30010 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10530 | /* 30015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10531 | /* 30018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10532 | /* 30020 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10533 | /* 30023 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 10534 | /* 30025 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 10535 | /* 30028 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10536 | /* 30033 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10537 | /* 30038 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10538 | /* 30043 */ // GIR_Coverage, 3413, |
| 10539 | /* 30043 */ GIR_EraseRootFromParent_Done, |
| 10540 | /* 30044 */ // Label 710: @30044 |
| 10541 | /* 30044 */ GIM_Reject, |
| 10542 | /* 30045 */ // Label 706: @30045 |
| 10543 | /* 30045 */ GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(30255), |
| 10544 | /* 30050 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 10545 | /* 30053 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 10546 | /* 30056 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 712*/ GIMT_Encode4(30155), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3412 // |
| 10547 | /* 30063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID), |
| 10548 | /* 30067 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10549 | /* 30071 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10550 | /* 30075 */ // (concat_vectors:{ *:[v8i16] } DPR:{ *:[v4i16] }:$Dn, DPR:{ *:[v4i16] }:$Dm) => (INSERT_SUBREG:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), DPR:{ *:[v4i16] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v4i16] }:$Dm, dsub_1:{ *:[i32] }) |
| 10551 | /* 30075 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 10552 | /* 30078 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10553 | /* 30082 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10554 | /* 30087 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10555 | /* 30089 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 10556 | /* 30092 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10557 | /* 30096 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10558 | /* 30101 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10559 | /* 30104 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn |
| 10560 | /* 30108 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 10561 | /* 30111 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10562 | /* 30116 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10563 | /* 30121 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10564 | /* 30126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10565 | /* 30129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10566 | /* 30131 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10567 | /* 30134 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 10568 | /* 30136 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 10569 | /* 30139 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10570 | /* 30144 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10571 | /* 30149 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10572 | /* 30154 */ // GIR_Coverage, 3412, |
| 10573 | /* 30154 */ GIR_EraseRootFromParent_Done, |
| 10574 | /* 30155 */ // Label 712: @30155 |
| 10575 | /* 30155 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 713*/ GIMT_Encode4(30254), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3415 // |
| 10576 | /* 30162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 10577 | /* 30166 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10578 | /* 30170 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10579 | /* 30174 */ // (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm) => (INSERT_SUBREG:{ *:[v8f16] } (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), DPR:{ *:[v4f16] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v4f16] }:$Dm, dsub_1:{ *:[i32] }) |
| 10580 | /* 30174 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 10581 | /* 30177 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10582 | /* 30181 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10583 | /* 30186 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10584 | /* 30188 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 10585 | /* 30191 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10586 | /* 30195 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10587 | /* 30200 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10588 | /* 30203 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn |
| 10589 | /* 30207 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 10590 | /* 30210 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10591 | /* 30215 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::QPRRegClassID), |
| 10592 | /* 30220 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10593 | /* 30225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10594 | /* 30228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10595 | /* 30230 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10596 | /* 30233 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 10597 | /* 30235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 10598 | /* 30238 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 10599 | /* 30243 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::QPRRegClassID), |
| 10600 | /* 30248 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10601 | /* 30253 */ // GIR_Coverage, 3415, |
| 10602 | /* 30253 */ GIR_EraseRootFromParent_Done, |
| 10603 | /* 30254 */ // Label 713: @30254 |
| 10604 | /* 30254 */ GIM_Reject, |
| 10605 | /* 30255 */ // Label 711: @30255 |
| 10606 | /* 30255 */ GIM_Reject, |
| 10607 | /* 30256 */ // Label 707: @30256 |
| 10608 | /* 30256 */ GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(30454), |
| 10609 | /* 30261 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 10610 | /* 30264 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 10611 | /* 30267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID), |
| 10612 | /* 30271 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10613 | /* 30275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10614 | /* 30279 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 715*/ GIMT_Encode4(30366), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3411 // |
| 10615 | /* 30286 */ // (concat_vectors:{ *:[v4i32] } DPR:{ *:[v2i32] }:$Dn, DPR:{ *:[v2i32] }:$Dm) => (INSERT_SUBREG:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), DPR:{ *:[v2i32] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v2i32] }:$Dm, dsub_1:{ *:[i32] }) |
| 10616 | /* 30286 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10617 | /* 30289 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10618 | /* 30293 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10619 | /* 30298 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10620 | /* 30300 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10621 | /* 30303 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10622 | /* 30307 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10623 | /* 30312 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10624 | /* 30315 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn |
| 10625 | /* 30319 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 10626 | /* 30322 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10627 | /* 30327 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10628 | /* 30332 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10629 | /* 30337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10630 | /* 30340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10631 | /* 30342 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10632 | /* 30345 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 10633 | /* 30347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 10634 | /* 30350 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10635 | /* 30355 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10636 | /* 30360 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10637 | /* 30365 */ // GIR_Coverage, 3411, |
| 10638 | /* 30365 */ GIR_EraseRootFromParent_Done, |
| 10639 | /* 30366 */ // Label 715: @30366 |
| 10640 | /* 30366 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 716*/ GIMT_Encode4(30453), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3414 // |
| 10641 | /* 30373 */ // (concat_vectors:{ *:[v4f32] } DPR:{ *:[v2f32] }:$Dn, DPR:{ *:[v2f32] }:$Dm) => (INSERT_SUBREG:{ *:[v4f32] } (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), DPR:{ *:[v2f32] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v2f32] }:$Dm, dsub_1:{ *:[i32] }) |
| 10642 | /* 30373 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 10643 | /* 30376 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10644 | /* 30380 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10645 | /* 30385 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10646 | /* 30387 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 10647 | /* 30390 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10648 | /* 30394 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10649 | /* 30399 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10650 | /* 30402 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn |
| 10651 | /* 30406 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 10652 | /* 30409 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10653 | /* 30414 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10654 | /* 30419 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10655 | /* 30424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10656 | /* 30427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10657 | /* 30429 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10658 | /* 30432 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 10659 | /* 30434 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 10660 | /* 30437 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10661 | /* 30442 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10662 | /* 30447 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10663 | /* 30452 */ // GIR_Coverage, 3414, |
| 10664 | /* 30452 */ GIR_EraseRootFromParent_Done, |
| 10665 | /* 30453 */ // Label 716: @30453 |
| 10666 | /* 30453 */ GIM_Reject, |
| 10667 | /* 30454 */ // Label 714: @30454 |
| 10668 | /* 30454 */ GIM_Reject, |
| 10669 | /* 30455 */ // Label 708: @30455 |
| 10670 | /* 30455 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 717*/ GIMT_Encode4(30560), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3410 // |
| 10671 | /* 30462 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 10672 | /* 30465 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 10673 | /* 30468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID), |
| 10674 | /* 30472 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10675 | /* 30476 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10676 | /* 30480 */ // (concat_vectors:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm) => (INSERT_SUBREG:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), DPR:{ *:[v1i64] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v1i64] }:$Dm, dsub_1:{ *:[i32] }) |
| 10677 | /* 30480 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64, |
| 10678 | /* 30483 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 10679 | /* 30487 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10680 | /* 30492 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10681 | /* 30494 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64, |
| 10682 | /* 30497 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10683 | /* 30501 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10684 | /* 30506 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10685 | /* 30509 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn |
| 10686 | /* 30513 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 10687 | /* 30516 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10688 | /* 30521 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10689 | /* 30526 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10690 | /* 30531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 10691 | /* 30534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10692 | /* 30536 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10693 | /* 30539 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 10694 | /* 30541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 10695 | /* 30544 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 10696 | /* 30549 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID), |
| 10697 | /* 30554 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID), |
| 10698 | /* 30559 */ // GIR_Coverage, 3410, |
| 10699 | /* 30559 */ GIR_EraseRootFromParent_Done, |
| 10700 | /* 30560 */ // Label 717: @30560 |
| 10701 | /* 30560 */ GIM_Reject, |
| 10702 | /* 30561 */ // Label 709: @30561 |
| 10703 | /* 30561 */ GIM_Reject, |
| 10704 | /* 30562 */ // Label 704: @30562 |
| 10705 | /* 30562 */ GIM_Reject, |
| 10706 | /* 30563 */ // Label 15: @30563 |
| 10707 | /* 30563 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 727*/ GIMT_Encode4(37749), |
| 10708 | /* 30574 */ /*GILLT_s32*//*Label 718*/ GIMT_Encode4(30626), |
| 10709 | /* 30578 */ /*GILLT_s64*//*Label 719*/ GIMT_Encode4(30769), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10710 | /* 30598 */ /*GILLT_v8s8*//*Label 720*/ GIMT_Encode4(31371), |
| 10711 | /* 30602 */ /*GILLT_v16s8*//*Label 721*/ GIMT_Encode4(31738), |
| 10712 | /* 30606 */ /*GILLT_v4s16*//*Label 722*/ GIMT_Encode4(32519), |
| 10713 | /* 30610 */ /*GILLT_v8s16*//*Label 723*/ GIMT_Encode4(33121), |
| 10714 | /* 30614 */ /*GILLT_v2s32*//*Label 724*/ GIMT_Encode4(34463), |
| 10715 | /* 30618 */ /*GILLT_v4s32*//*Label 725*/ GIMT_Encode4(35065), |
| 10716 | /* 30622 */ /*GILLT_v2s64*//*Label 726*/ GIMT_Encode4(36407), |
| 10717 | /* 30626 */ // Label 718: @30626 |
| 10718 | /* 30626 */ GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(30768), |
| 10719 | /* 30631 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 10720 | /* 30634 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 729*/ GIMT_Encode4(30667), GIMT_Encode2(GIFBS_HasFPRegs), // Rule ID 740 // |
| 10721 | /* 30641 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 10722 | /* 30645 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 10723 | /* 30649 */ // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn) => (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn) |
| 10724 | /* 30649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVRS), |
| 10725 | /* 30652 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 10726 | /* 30654 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 10727 | /* 30656 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10728 | /* 30659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10729 | /* 30665 */ GIR_RootConstrainSelectedInstOperands, |
| 10730 | /* 30666 */ // GIR_Coverage, 740, |
| 10731 | /* 30666 */ GIR_EraseRootFromParent_Done, |
| 10732 | /* 30667 */ // Label 729: @30667 |
| 10733 | /* 30667 */ GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(30767), |
| 10734 | /* 30672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 10735 | /* 30676 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 10736 | /* 30680 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 731*/ GIMT_Encode4(30705), GIMT_Encode2(GIFBS_HasFPRegs_UseVMOVSR), // Rule ID 741 // |
| 10737 | /* 30687 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt) => (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt) |
| 10738 | /* 30687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVSR), |
| 10739 | /* 30690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sn] |
| 10740 | /* 30692 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt |
| 10741 | /* 30694 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10742 | /* 30697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10743 | /* 30703 */ GIR_RootConstrainSelectedInstOperands, |
| 10744 | /* 30704 */ // GIR_Coverage, 741, |
| 10745 | /* 30704 */ GIR_EraseRootFromParent_Done, |
| 10746 | /* 30705 */ // Label 731: @30705 |
| 10747 | /* 30705 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 732*/ GIMT_Encode4(30766), GIMT_Encode2(GIFBS_DontUseVMOVSR_HasNEON), // Rule ID 3104 // |
| 10748 | /* 30712 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VMOVDRR:{ *:[f64] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$a), ssub_0:{ *:[i32] }) |
| 10749 | /* 30712 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 10750 | /* 30715 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VMOVDRR), |
| 10751 | /* 30719 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 10752 | /* 30724 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 10753 | /* 30728 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 10754 | /* 30732 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 10755 | /* 30735 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10756 | /* 30741 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10757 | /* 30743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10758 | /* 30746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10759 | /* 30748 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 10760 | /* 30755 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 10761 | /* 30760 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 10762 | /* 30765 */ // GIR_Coverage, 3104, |
| 10763 | /* 30765 */ GIR_EraseRootFromParent_Done, |
| 10764 | /* 30766 */ // Label 732: @30766 |
| 10765 | /* 30766 */ GIM_Reject, |
| 10766 | /* 30767 */ // Label 730: @30767 |
| 10767 | /* 30767 */ GIM_Reject, |
| 10768 | /* 30768 */ // Label 728: @30768 |
| 10769 | /* 30768 */ GIM_Reject, |
| 10770 | /* 30769 */ // Label 719: @30769 |
| 10771 | /* 30769 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 737*/ GIMT_Encode4(31370), |
| 10772 | /* 30780 */ /*GILLT_s64*//*Label 733*/ GIMT_Encode4(30820), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 10773 | /* 30800 */ /*GILLT_v8s8*//*Label 734*/ GIMT_Encode4(30875), GIMT_Encode4(0), |
| 10774 | /* 30808 */ /*GILLT_v4s16*//*Label 735*/ GIMT_Encode4(30980), GIMT_Encode4(0), |
| 10775 | /* 30816 */ /*GILLT_v2s32*//*Label 736*/ GIMT_Encode4(31175), |
| 10776 | /* 30820 */ // Label 733: @30820 |
| 10777 | /* 30820 */ GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(30874), |
| 10778 | /* 30825 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10779 | /* 30829 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10780 | /* 30833 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 739*/ GIMT_Encode4(30853), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3106 // |
| 10781 | /* 30840 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[f64] }:$src |
| 10782 | /* 30840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10783 | /* 30843 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10784 | /* 30845 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10785 | /* 30847 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10786 | /* 30852 */ // GIR_Coverage, 3106, |
| 10787 | /* 30852 */ GIR_EraseRootFromParent_Done, |
| 10788 | /* 30853 */ // Label 739: @30853 |
| 10789 | /* 30853 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 740*/ GIMT_Encode4(30873), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3107 // |
| 10790 | /* 30860 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v1i64] }:$src |
| 10791 | /* 30860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10792 | /* 30863 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10793 | /* 30865 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10794 | /* 30867 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10795 | /* 30872 */ // GIR_Coverage, 3107, |
| 10796 | /* 30872 */ GIR_EraseRootFromParent_Done, |
| 10797 | /* 30873 */ // Label 740: @30873 |
| 10798 | /* 30873 */ GIM_Reject, |
| 10799 | /* 30874 */ // Label 738: @30874 |
| 10800 | /* 30874 */ GIM_Reject, |
| 10801 | /* 30875 */ // Label 734: @30875 |
| 10802 | /* 30875 */ GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(30979), |
| 10803 | /* 30880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10804 | /* 30884 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10805 | /* 30888 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 742*/ GIMT_Encode4(30908), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3122 // |
| 10806 | /* 30895 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[f64] }:$src |
| 10807 | /* 30895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10808 | /* 30898 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10809 | /* 30900 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10810 | /* 30902 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10811 | /* 30907 */ // GIR_Coverage, 3122, |
| 10812 | /* 30907 */ GIR_EraseRootFromParent_Done, |
| 10813 | /* 30908 */ // Label 742: @30908 |
| 10814 | /* 30908 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 743*/ GIMT_Encode4(30928), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3127 // |
| 10815 | /* 30915 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v1i64] }:$src |
| 10816 | /* 30915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10817 | /* 30918 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10818 | /* 30920 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10819 | /* 30922 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10820 | /* 30927 */ // GIR_Coverage, 3127, |
| 10821 | /* 30927 */ GIR_EraseRootFromParent_Done, |
| 10822 | /* 30928 */ // Label 743: @30928 |
| 10823 | /* 30928 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 744*/ GIMT_Encode4(30953), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3194 // |
| 10824 | /* 30935 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src) |
| 10825 | /* 30935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 10826 | /* 30938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10827 | /* 30940 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10828 | /* 30942 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10829 | /* 30945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10830 | /* 30951 */ GIR_RootConstrainSelectedInstOperands, |
| 10831 | /* 30952 */ // GIR_Coverage, 3194, |
| 10832 | /* 30952 */ GIR_EraseRootFromParent_Done, |
| 10833 | /* 30953 */ // Label 744: @30953 |
| 10834 | /* 30953 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 745*/ GIMT_Encode4(30978), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3199 // |
| 10835 | /* 30960 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) |
| 10836 | /* 30960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 10837 | /* 30963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10838 | /* 30965 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10839 | /* 30967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10840 | /* 30970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10841 | /* 30976 */ GIR_RootConstrainSelectedInstOperands, |
| 10842 | /* 30977 */ // GIR_Coverage, 3199, |
| 10843 | /* 30977 */ GIR_EraseRootFromParent_Done, |
| 10844 | /* 30978 */ // Label 745: @30978 |
| 10845 | /* 30978 */ GIM_Reject, |
| 10846 | /* 30979 */ // Label 741: @30979 |
| 10847 | /* 30979 */ GIM_Reject, |
| 10848 | /* 30980 */ // Label 735: @30980 |
| 10849 | /* 30980 */ GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(31174), |
| 10850 | /* 30985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10851 | /* 30989 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10852 | /* 30993 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 747*/ GIMT_Encode4(31013), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3120 // |
| 10853 | /* 31000 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[f64] }:$src |
| 10854 | /* 31000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10855 | /* 31003 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10856 | /* 31005 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10857 | /* 31007 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10858 | /* 31012 */ // GIR_Coverage, 3120, |
| 10859 | /* 31012 */ GIR_EraseRootFromParent_Done, |
| 10860 | /* 31013 */ // Label 747: @31013 |
| 10861 | /* 31013 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 748*/ GIMT_Encode4(31033), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3121 // |
| 10862 | /* 31020 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[f64] }:$src |
| 10863 | /* 31020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10864 | /* 31023 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10865 | /* 31025 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10866 | /* 31027 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10867 | /* 31032 */ // GIR_Coverage, 3121, |
| 10868 | /* 31032 */ GIR_EraseRootFromParent_Done, |
| 10869 | /* 31033 */ // Label 748: @31033 |
| 10870 | /* 31033 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 749*/ GIMT_Encode4(31053), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3125 // |
| 10871 | /* 31040 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v1i64] }:$src |
| 10872 | /* 31040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10873 | /* 31043 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10874 | /* 31045 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10875 | /* 31047 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10876 | /* 31052 */ // GIR_Coverage, 3125, |
| 10877 | /* 31052 */ GIR_EraseRootFromParent_Done, |
| 10878 | /* 31053 */ // Label 749: @31053 |
| 10879 | /* 31053 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 750*/ GIMT_Encode4(31073), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3126 // |
| 10880 | /* 31060 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v1i64] }:$src |
| 10881 | /* 31060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10882 | /* 31063 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10883 | /* 31065 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10884 | /* 31067 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10885 | /* 31072 */ // GIR_Coverage, 3126, |
| 10886 | /* 31072 */ GIR_EraseRootFromParent_Done, |
| 10887 | /* 31073 */ // Label 750: @31073 |
| 10888 | /* 31073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 751*/ GIMT_Encode4(31098), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3192 // |
| 10889 | /* 31080 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src) |
| 10890 | /* 31080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 10891 | /* 31083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10892 | /* 31085 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10893 | /* 31087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10894 | /* 31090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10895 | /* 31096 */ GIR_RootConstrainSelectedInstOperands, |
| 10896 | /* 31097 */ // GIR_Coverage, 3192, |
| 10897 | /* 31097 */ GIR_EraseRootFromParent_Done, |
| 10898 | /* 31098 */ // Label 751: @31098 |
| 10899 | /* 31098 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 752*/ GIMT_Encode4(31123), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3193 // |
| 10900 | /* 31105 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src) |
| 10901 | /* 31105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 10902 | /* 31108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10903 | /* 31110 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10904 | /* 31112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10905 | /* 31115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10906 | /* 31121 */ GIR_RootConstrainSelectedInstOperands, |
| 10907 | /* 31122 */ // GIR_Coverage, 3193, |
| 10908 | /* 31122 */ GIR_EraseRootFromParent_Done, |
| 10909 | /* 31123 */ // Label 752: @31123 |
| 10910 | /* 31123 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 753*/ GIMT_Encode4(31148), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3197 // |
| 10911 | /* 31130 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) |
| 10912 | /* 31130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 10913 | /* 31133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10914 | /* 31135 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10915 | /* 31137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10916 | /* 31140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10917 | /* 31146 */ GIR_RootConstrainSelectedInstOperands, |
| 10918 | /* 31147 */ // GIR_Coverage, 3197, |
| 10919 | /* 31147 */ GIR_EraseRootFromParent_Done, |
| 10920 | /* 31148 */ // Label 753: @31148 |
| 10921 | /* 31148 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 754*/ GIMT_Encode4(31173), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3198 // |
| 10922 | /* 31155 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) |
| 10923 | /* 31155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 10924 | /* 31158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10925 | /* 31160 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10926 | /* 31162 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10927 | /* 31165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10928 | /* 31171 */ GIR_RootConstrainSelectedInstOperands, |
| 10929 | /* 31172 */ // GIR_Coverage, 3198, |
| 10930 | /* 31172 */ GIR_EraseRootFromParent_Done, |
| 10931 | /* 31173 */ // Label 754: @31173 |
| 10932 | /* 31173 */ GIM_Reject, |
| 10933 | /* 31174 */ // Label 746: @31174 |
| 10934 | /* 31174 */ GIM_Reject, |
| 10935 | /* 31175 */ // Label 736: @31175 |
| 10936 | /* 31175 */ GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(31369), |
| 10937 | /* 31180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10938 | /* 31184 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 10939 | /* 31188 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 756*/ GIMT_Encode4(31208), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3118 // |
| 10940 | /* 31195 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[f64] }:$src |
| 10941 | /* 31195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10942 | /* 31198 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10943 | /* 31200 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10944 | /* 31202 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10945 | /* 31207 */ // GIR_Coverage, 3118, |
| 10946 | /* 31207 */ GIR_EraseRootFromParent_Done, |
| 10947 | /* 31208 */ // Label 756: @31208 |
| 10948 | /* 31208 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 757*/ GIMT_Encode4(31228), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3119 // |
| 10949 | /* 31215 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[f64] }:$src |
| 10950 | /* 31215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10951 | /* 31218 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10952 | /* 31220 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10953 | /* 31222 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10954 | /* 31227 */ // GIR_Coverage, 3119, |
| 10955 | /* 31227 */ GIR_EraseRootFromParent_Done, |
| 10956 | /* 31228 */ // Label 757: @31228 |
| 10957 | /* 31228 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 758*/ GIMT_Encode4(31248), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3123 // |
| 10958 | /* 31235 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v1i64] }:$src |
| 10959 | /* 31235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10960 | /* 31238 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10961 | /* 31240 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10962 | /* 31242 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10963 | /* 31247 */ // GIR_Coverage, 3123, |
| 10964 | /* 31247 */ GIR_EraseRootFromParent_Done, |
| 10965 | /* 31248 */ // Label 758: @31248 |
| 10966 | /* 31248 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 759*/ GIMT_Encode4(31268), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3124 // |
| 10967 | /* 31255 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v1i64] }:$src |
| 10968 | /* 31255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10969 | /* 31258 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10970 | /* 31260 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10971 | /* 31262 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 10972 | /* 31267 */ // GIR_Coverage, 3124, |
| 10973 | /* 31267 */ GIR_EraseRootFromParent_Done, |
| 10974 | /* 31268 */ // Label 759: @31268 |
| 10975 | /* 31268 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 760*/ GIMT_Encode4(31293), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3190 // |
| 10976 | /* 31275 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src) |
| 10977 | /* 31275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 10978 | /* 31278 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10979 | /* 31280 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10980 | /* 31282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10981 | /* 31285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10982 | /* 31291 */ GIR_RootConstrainSelectedInstOperands, |
| 10983 | /* 31292 */ // GIR_Coverage, 3190, |
| 10984 | /* 31292 */ GIR_EraseRootFromParent_Done, |
| 10985 | /* 31293 */ // Label 760: @31293 |
| 10986 | /* 31293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 761*/ GIMT_Encode4(31318), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3191 // |
| 10987 | /* 31300 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src) |
| 10988 | /* 31300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 10989 | /* 31303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 10990 | /* 31305 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 10991 | /* 31307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 10992 | /* 31310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 10993 | /* 31316 */ GIR_RootConstrainSelectedInstOperands, |
| 10994 | /* 31317 */ // GIR_Coverage, 3191, |
| 10995 | /* 31317 */ GIR_EraseRootFromParent_Done, |
| 10996 | /* 31318 */ // Label 761: @31318 |
| 10997 | /* 31318 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 762*/ GIMT_Encode4(31343), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3195 // |
| 10998 | /* 31325 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) |
| 10999 | /* 31325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 11000 | /* 31328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11001 | /* 31330 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11002 | /* 31332 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11003 | /* 31335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11004 | /* 31341 */ GIR_RootConstrainSelectedInstOperands, |
| 11005 | /* 31342 */ // GIR_Coverage, 3195, |
| 11006 | /* 31342 */ GIR_EraseRootFromParent_Done, |
| 11007 | /* 31343 */ // Label 762: @31343 |
| 11008 | /* 31343 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 763*/ GIMT_Encode4(31368), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3196 // |
| 11009 | /* 31350 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) |
| 11010 | /* 31350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 11011 | /* 31353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11012 | /* 31355 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11013 | /* 31357 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11014 | /* 31360 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11015 | /* 31366 */ GIR_RootConstrainSelectedInstOperands, |
| 11016 | /* 31367 */ // GIR_Coverage, 3196, |
| 11017 | /* 31367 */ GIR_EraseRootFromParent_Done, |
| 11018 | /* 31368 */ // Label 763: @31368 |
| 11019 | /* 31368 */ GIM_Reject, |
| 11020 | /* 31369 */ // Label 755: @31369 |
| 11021 | /* 31369 */ GIM_Reject, |
| 11022 | /* 31370 */ // Label 737: @31370 |
| 11023 | /* 31370 */ GIM_Reject, |
| 11024 | /* 31371 */ // Label 720: @31371 |
| 11025 | /* 31371 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 767*/ GIMT_Encode4(31737), |
| 11026 | /* 31382 */ /*GILLT_s64*//*Label 764*/ GIMT_Encode4(31422), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 11027 | /* 31410 */ /*GILLT_v4s16*//*Label 765*/ GIMT_Encode4(31527), GIMT_Encode4(0), |
| 11028 | /* 31418 */ /*GILLT_v2s32*//*Label 766*/ GIMT_Encode4(31632), |
| 11029 | /* 31422 */ // Label 764: @31422 |
| 11030 | /* 31422 */ GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(31526), |
| 11031 | /* 31427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11032 | /* 31431 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11033 | /* 31435 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 769*/ GIMT_Encode4(31455), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3148 // |
| 11034 | /* 31442 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11035 | /* 31442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11036 | /* 31445 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11037 | /* 31447 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11038 | /* 31449 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11039 | /* 31454 */ // GIR_Coverage, 3148, |
| 11040 | /* 31454 */ GIR_EraseRootFromParent_Done, |
| 11041 | /* 31455 */ // Label 769: @31455 |
| 11042 | /* 31455 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 770*/ GIMT_Encode4(31475), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3149 // |
| 11043 | /* 31462 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11044 | /* 31462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11045 | /* 31465 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11046 | /* 31467 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11047 | /* 31469 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11048 | /* 31474 */ // GIR_Coverage, 3149, |
| 11049 | /* 31474 */ GIR_EraseRootFromParent_Done, |
| 11050 | /* 31475 */ // Label 770: @31475 |
| 11051 | /* 31475 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 771*/ GIMT_Encode4(31500), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3220 // |
| 11052 | /* 31482 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src) |
| 11053 | /* 31482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 11054 | /* 31485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11055 | /* 31487 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11056 | /* 31489 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11057 | /* 31492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11058 | /* 31498 */ GIR_RootConstrainSelectedInstOperands, |
| 11059 | /* 31499 */ // GIR_Coverage, 3220, |
| 11060 | /* 31499 */ GIR_EraseRootFromParent_Done, |
| 11061 | /* 31500 */ // Label 771: @31500 |
| 11062 | /* 31500 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 772*/ GIMT_Encode4(31525), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3221 // |
| 11063 | /* 31507 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) |
| 11064 | /* 31507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8), |
| 11065 | /* 31510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11066 | /* 31512 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11067 | /* 31514 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11068 | /* 31517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11069 | /* 31523 */ GIR_RootConstrainSelectedInstOperands, |
| 11070 | /* 31524 */ // GIR_Coverage, 3221, |
| 11071 | /* 31524 */ GIR_EraseRootFromParent_Done, |
| 11072 | /* 31525 */ // Label 772: @31525 |
| 11073 | /* 31525 */ GIM_Reject, |
| 11074 | /* 31526 */ // Label 768: @31526 |
| 11075 | /* 31526 */ GIM_Reject, |
| 11076 | /* 31527 */ // Label 765: @31527 |
| 11077 | /* 31527 */ GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(31631), |
| 11078 | /* 31532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11079 | /* 31536 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11080 | /* 31540 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 774*/ GIMT_Encode4(31560), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3152 // |
| 11081 | /* 31547 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11082 | /* 31547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11083 | /* 31550 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11084 | /* 31552 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11085 | /* 31554 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11086 | /* 31559 */ // GIR_Coverage, 3152, |
| 11087 | /* 31559 */ GIR_EraseRootFromParent_Done, |
| 11088 | /* 31560 */ // Label 774: @31560 |
| 11089 | /* 31560 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 775*/ GIMT_Encode4(31580), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3153 // |
| 11090 | /* 31567 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11091 | /* 31567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11092 | /* 31570 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11093 | /* 31572 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11094 | /* 31574 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11095 | /* 31579 */ // GIR_Coverage, 3153, |
| 11096 | /* 31579 */ GIR_EraseRootFromParent_Done, |
| 11097 | /* 31580 */ // Label 775: @31580 |
| 11098 | /* 31580 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 776*/ GIMT_Encode4(31605), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3224 // |
| 11099 | /* 31587 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) |
| 11100 | /* 31587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 11101 | /* 31590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11102 | /* 31592 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11103 | /* 31594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11104 | /* 31597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11105 | /* 31603 */ GIR_RootConstrainSelectedInstOperands, |
| 11106 | /* 31604 */ // GIR_Coverage, 3224, |
| 11107 | /* 31604 */ GIR_EraseRootFromParent_Done, |
| 11108 | /* 31605 */ // Label 776: @31605 |
| 11109 | /* 31605 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 777*/ GIMT_Encode4(31630), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3225 // |
| 11110 | /* 31612 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) |
| 11111 | /* 31612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 11112 | /* 31615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11113 | /* 31617 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11114 | /* 31619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11115 | /* 31622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11116 | /* 31628 */ GIR_RootConstrainSelectedInstOperands, |
| 11117 | /* 31629 */ // GIR_Coverage, 3225, |
| 11118 | /* 31629 */ GIR_EraseRootFromParent_Done, |
| 11119 | /* 31630 */ // Label 777: @31630 |
| 11120 | /* 31630 */ GIM_Reject, |
| 11121 | /* 31631 */ // Label 773: @31631 |
| 11122 | /* 31631 */ GIM_Reject, |
| 11123 | /* 31632 */ // Label 766: @31632 |
| 11124 | /* 31632 */ GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(31736), |
| 11125 | /* 31637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11126 | /* 31641 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11127 | /* 31645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 779*/ GIMT_Encode4(31665), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3150 // |
| 11128 | /* 31652 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11129 | /* 31652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11130 | /* 31655 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11131 | /* 31657 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11132 | /* 31659 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11133 | /* 31664 */ // GIR_Coverage, 3150, |
| 11134 | /* 31664 */ GIR_EraseRootFromParent_Done, |
| 11135 | /* 31665 */ // Label 779: @31665 |
| 11136 | /* 31665 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 780*/ GIMT_Encode4(31685), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3151 // |
| 11137 | /* 31672 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v8i8] }:$src |
| 11138 | /* 31672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11139 | /* 31675 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11140 | /* 31677 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11141 | /* 31679 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11142 | /* 31684 */ // GIR_Coverage, 3151, |
| 11143 | /* 31684 */ GIR_EraseRootFromParent_Done, |
| 11144 | /* 31685 */ // Label 780: @31685 |
| 11145 | /* 31685 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 781*/ GIMT_Encode4(31710), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3222 // |
| 11146 | /* 31692 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) |
| 11147 | /* 31692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 11148 | /* 31695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11149 | /* 31697 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11150 | /* 31699 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11151 | /* 31702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11152 | /* 31708 */ GIR_RootConstrainSelectedInstOperands, |
| 11153 | /* 31709 */ // GIR_Coverage, 3222, |
| 11154 | /* 31709 */ GIR_EraseRootFromParent_Done, |
| 11155 | /* 31710 */ // Label 781: @31710 |
| 11156 | /* 31710 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 782*/ GIMT_Encode4(31735), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3223 // |
| 11157 | /* 31717 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) |
| 11158 | /* 31717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 11159 | /* 31720 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11160 | /* 31722 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11161 | /* 31724 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11162 | /* 31727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11163 | /* 31733 */ GIR_RootConstrainSelectedInstOperands, |
| 11164 | /* 31734 */ // GIR_Coverage, 3223, |
| 11165 | /* 31734 */ GIR_EraseRootFromParent_Done, |
| 11166 | /* 31735 */ // Label 782: @31735 |
| 11167 | /* 31735 */ GIM_Reject, |
| 11168 | /* 31736 */ // Label 778: @31736 |
| 11169 | /* 31736 */ GIM_Reject, |
| 11170 | /* 31737 */ // Label 767: @31737 |
| 11171 | /* 31737 */ GIM_Reject, |
| 11172 | /* 31738 */ // Label 721: @31738 |
| 11173 | /* 31738 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 786*/ GIMT_Encode4(32518), |
| 11174 | /* 31749 */ /*GILLT_v8s16*//*Label 783*/ GIMT_Encode4(31765), GIMT_Encode4(0), |
| 11175 | /* 31757 */ /*GILLT_v4s32*//*Label 784*/ GIMT_Encode4(32016), |
| 11176 | /* 31761 */ /*GILLT_v2s64*//*Label 785*/ GIMT_Encode4(32267), |
| 11177 | /* 31765 */ // Label 783: @31765 |
| 11178 | /* 31765 */ GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(31869), |
| 11179 | /* 31770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11180 | /* 31774 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11181 | /* 31778 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 788*/ GIMT_Encode4(31798), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3188 // |
| 11182 | /* 31785 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11183 | /* 31785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11184 | /* 31788 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11185 | /* 31790 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11186 | /* 31792 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11187 | /* 31797 */ // GIR_Coverage, 3188, |
| 11188 | /* 31797 */ GIR_EraseRootFromParent_Done, |
| 11189 | /* 31798 */ // Label 788: @31798 |
| 11190 | /* 31798 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 789*/ GIMT_Encode4(31818), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3189 // |
| 11191 | /* 31805 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11192 | /* 31805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11193 | /* 31808 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11194 | /* 31810 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11195 | /* 31812 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11196 | /* 31817 */ // GIR_Coverage, 3189, |
| 11197 | /* 31817 */ GIR_EraseRootFromParent_Done, |
| 11198 | /* 31818 */ // Label 789: @31818 |
| 11199 | /* 31818 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 790*/ GIMT_Encode4(31843), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3260 // |
| 11200 | /* 31825 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) |
| 11201 | /* 31825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 11202 | /* 31828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11203 | /* 31830 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11204 | /* 31832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11205 | /* 31835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11206 | /* 31841 */ GIR_RootConstrainSelectedInstOperands, |
| 11207 | /* 31842 */ // GIR_Coverage, 3260, |
| 11208 | /* 31842 */ GIR_EraseRootFromParent_Done, |
| 11209 | /* 31843 */ // Label 790: @31843 |
| 11210 | /* 31843 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 791*/ GIMT_Encode4(31868), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3261 // |
| 11211 | /* 31850 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) |
| 11212 | /* 31850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 11213 | /* 31853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11214 | /* 31855 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11215 | /* 31857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11216 | /* 31860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11217 | /* 31866 */ GIR_RootConstrainSelectedInstOperands, |
| 11218 | /* 31867 */ // GIR_Coverage, 3261, |
| 11219 | /* 31867 */ GIR_EraseRootFromParent_Done, |
| 11220 | /* 31868 */ // Label 791: @31868 |
| 11221 | /* 31868 */ GIM_Reject, |
| 11222 | /* 31869 */ // Label 787: @31869 |
| 11223 | /* 31869 */ GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(32015), |
| 11224 | /* 31874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11225 | /* 31878 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11226 | /* 31882 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 793*/ GIMT_Encode4(31902), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5849 // |
| 11227 | /* 31889 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11228 | /* 31889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11229 | /* 31892 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11230 | /* 31894 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11231 | /* 31896 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11232 | /* 31901 */ // GIR_Coverage, 5849, |
| 11233 | /* 31901 */ GIR_EraseRootFromParent_Done, |
| 11234 | /* 31902 */ // Label 793: @31902 |
| 11235 | /* 31902 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 794*/ GIMT_Encode4(31922), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5850 // |
| 11236 | /* 31909 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11237 | /* 31909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11238 | /* 31912 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11239 | /* 31914 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11240 | /* 31916 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11241 | /* 31921 */ // GIR_Coverage, 5850, |
| 11242 | /* 31921 */ GIR_EraseRootFromParent_Done, |
| 11243 | /* 31922 */ // Label 794: @31922 |
| 11244 | /* 31922 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 795*/ GIMT_Encode4(31968), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5885 // |
| 11245 | /* 31929 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) |
| 11246 | /* 31929 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11247 | /* 31932 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11248 | /* 31936 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11249 | /* 31941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 11250 | /* 31944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11251 | /* 31946 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11252 | /* 31948 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11253 | /* 31951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11254 | /* 31957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11255 | /* 31963 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11256 | /* 31966 */ GIR_RootConstrainSelectedInstOperands, |
| 11257 | /* 31967 */ // GIR_Coverage, 5885, |
| 11258 | /* 31967 */ GIR_EraseRootFromParent_Done, |
| 11259 | /* 31968 */ // Label 795: @31968 |
| 11260 | /* 31968 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 796*/ GIMT_Encode4(32014), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5886 // |
| 11261 | /* 31975 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) |
| 11262 | /* 31975 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11263 | /* 31978 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11264 | /* 31982 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11265 | /* 31987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 11266 | /* 31990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11267 | /* 31992 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11268 | /* 31994 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11269 | /* 31997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11270 | /* 32003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11271 | /* 32009 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11272 | /* 32012 */ GIR_RootConstrainSelectedInstOperands, |
| 11273 | /* 32013 */ // GIR_Coverage, 5886, |
| 11274 | /* 32013 */ GIR_EraseRootFromParent_Done, |
| 11275 | /* 32014 */ // Label 796: @32014 |
| 11276 | /* 32014 */ GIM_Reject, |
| 11277 | /* 32015 */ // Label 792: @32015 |
| 11278 | /* 32015 */ GIM_Reject, |
| 11279 | /* 32016 */ // Label 784: @32016 |
| 11280 | /* 32016 */ GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(32120), |
| 11281 | /* 32021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11282 | /* 32025 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11283 | /* 32029 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 798*/ GIMT_Encode4(32049), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3186 // |
| 11284 | /* 32036 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11285 | /* 32036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11286 | /* 32039 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11287 | /* 32041 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11288 | /* 32043 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11289 | /* 32048 */ // GIR_Coverage, 3186, |
| 11290 | /* 32048 */ GIR_EraseRootFromParent_Done, |
| 11291 | /* 32049 */ // Label 798: @32049 |
| 11292 | /* 32049 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 799*/ GIMT_Encode4(32069), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3187 // |
| 11293 | /* 32056 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11294 | /* 32056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11295 | /* 32059 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11296 | /* 32061 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11297 | /* 32063 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11298 | /* 32068 */ // GIR_Coverage, 3187, |
| 11299 | /* 32068 */ GIR_EraseRootFromParent_Done, |
| 11300 | /* 32069 */ // Label 799: @32069 |
| 11301 | /* 32069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 800*/ GIMT_Encode4(32094), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3258 // |
| 11302 | /* 32076 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) |
| 11303 | /* 32076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 11304 | /* 32079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11305 | /* 32081 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11306 | /* 32083 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11307 | /* 32086 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11308 | /* 32092 */ GIR_RootConstrainSelectedInstOperands, |
| 11309 | /* 32093 */ // GIR_Coverage, 3258, |
| 11310 | /* 32093 */ GIR_EraseRootFromParent_Done, |
| 11311 | /* 32094 */ // Label 800: @32094 |
| 11312 | /* 32094 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 801*/ GIMT_Encode4(32119), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3259 // |
| 11313 | /* 32101 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) |
| 11314 | /* 32101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 11315 | /* 32104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11316 | /* 32106 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11317 | /* 32108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11318 | /* 32111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11319 | /* 32117 */ GIR_RootConstrainSelectedInstOperands, |
| 11320 | /* 32118 */ // GIR_Coverage, 3259, |
| 11321 | /* 32118 */ GIR_EraseRootFromParent_Done, |
| 11322 | /* 32119 */ // Label 801: @32119 |
| 11323 | /* 32119 */ GIM_Reject, |
| 11324 | /* 32120 */ // Label 797: @32120 |
| 11325 | /* 32120 */ GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(32266), |
| 11326 | /* 32125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11327 | /* 32129 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11328 | /* 32133 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 803*/ GIMT_Encode4(32153), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5847 // |
| 11329 | /* 32140 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11330 | /* 32140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11331 | /* 32143 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11332 | /* 32145 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11333 | /* 32147 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11334 | /* 32152 */ // GIR_Coverage, 5847, |
| 11335 | /* 32152 */ GIR_EraseRootFromParent_Done, |
| 11336 | /* 32153 */ // Label 803: @32153 |
| 11337 | /* 32153 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 804*/ GIMT_Encode4(32173), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5848 // |
| 11338 | /* 32160 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11339 | /* 32160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11340 | /* 32163 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11341 | /* 32165 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11342 | /* 32167 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11343 | /* 32172 */ // GIR_Coverage, 5848, |
| 11344 | /* 32172 */ GIR_EraseRootFromParent_Done, |
| 11345 | /* 32173 */ // Label 804: @32173 |
| 11346 | /* 32173 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 805*/ GIMT_Encode4(32219), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5883 // |
| 11347 | /* 32180 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) |
| 11348 | /* 32180 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11349 | /* 32183 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11350 | /* 32187 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11351 | /* 32192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 11352 | /* 32195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11353 | /* 32197 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11354 | /* 32199 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11355 | /* 32202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11356 | /* 32208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11357 | /* 32214 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11358 | /* 32217 */ GIR_RootConstrainSelectedInstOperands, |
| 11359 | /* 32218 */ // GIR_Coverage, 5883, |
| 11360 | /* 32218 */ GIR_EraseRootFromParent_Done, |
| 11361 | /* 32219 */ // Label 805: @32219 |
| 11362 | /* 32219 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 806*/ GIMT_Encode4(32265), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5884 // |
| 11363 | /* 32226 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) |
| 11364 | /* 32226 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11365 | /* 32229 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11366 | /* 32233 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11367 | /* 32238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 11368 | /* 32241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11369 | /* 32243 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11370 | /* 32245 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11371 | /* 32248 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11372 | /* 32254 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11373 | /* 32260 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11374 | /* 32263 */ GIR_RootConstrainSelectedInstOperands, |
| 11375 | /* 32264 */ // GIR_Coverage, 5884, |
| 11376 | /* 32264 */ GIR_EraseRootFromParent_Done, |
| 11377 | /* 32265 */ // Label 806: @32265 |
| 11378 | /* 32265 */ GIM_Reject, |
| 11379 | /* 32266 */ // Label 802: @32266 |
| 11380 | /* 32266 */ GIM_Reject, |
| 11381 | /* 32267 */ // Label 785: @32267 |
| 11382 | /* 32267 */ GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(32371), |
| 11383 | /* 32272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11384 | /* 32276 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11385 | /* 32280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 808*/ GIMT_Encode4(32300), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3184 // |
| 11386 | /* 32287 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11387 | /* 32287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11388 | /* 32290 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11389 | /* 32292 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11390 | /* 32294 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11391 | /* 32299 */ // GIR_Coverage, 3184, |
| 11392 | /* 32299 */ GIR_EraseRootFromParent_Done, |
| 11393 | /* 32300 */ // Label 808: @32300 |
| 11394 | /* 32300 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 809*/ GIMT_Encode4(32320), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3185 // |
| 11395 | /* 32307 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v16i8] }:$src |
| 11396 | /* 32307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11397 | /* 32310 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11398 | /* 32312 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11399 | /* 32314 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11400 | /* 32319 */ // GIR_Coverage, 3185, |
| 11401 | /* 32319 */ GIR_EraseRootFromParent_Done, |
| 11402 | /* 32320 */ // Label 809: @32320 |
| 11403 | /* 32320 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 810*/ GIMT_Encode4(32345), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3256 // |
| 11404 | /* 32327 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) |
| 11405 | /* 32327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 11406 | /* 32330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11407 | /* 32332 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11408 | /* 32334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11409 | /* 32337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11410 | /* 32343 */ GIR_RootConstrainSelectedInstOperands, |
| 11411 | /* 32344 */ // GIR_Coverage, 3256, |
| 11412 | /* 32344 */ GIR_EraseRootFromParent_Done, |
| 11413 | /* 32345 */ // Label 810: @32345 |
| 11414 | /* 32345 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 811*/ GIMT_Encode4(32370), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3257 // |
| 11415 | /* 32352 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) |
| 11416 | /* 32352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 11417 | /* 32355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11418 | /* 32357 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11419 | /* 32359 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11420 | /* 32362 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11421 | /* 32368 */ GIR_RootConstrainSelectedInstOperands, |
| 11422 | /* 32369 */ // GIR_Coverage, 3257, |
| 11423 | /* 32369 */ GIR_EraseRootFromParent_Done, |
| 11424 | /* 32370 */ // Label 811: @32370 |
| 11425 | /* 32370 */ GIM_Reject, |
| 11426 | /* 32371 */ // Label 807: @32371 |
| 11427 | /* 32371 */ GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(32517), |
| 11428 | /* 32376 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11429 | /* 32380 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11430 | /* 32384 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 813*/ GIMT_Encode4(32404), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5845 // |
| 11431 | /* 32391 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11432 | /* 32391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11433 | /* 32394 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11434 | /* 32396 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11435 | /* 32398 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11436 | /* 32403 */ // GIR_Coverage, 5845, |
| 11437 | /* 32403 */ GIR_EraseRootFromParent_Done, |
| 11438 | /* 32404 */ // Label 813: @32404 |
| 11439 | /* 32404 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 814*/ GIMT_Encode4(32424), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5846 // |
| 11440 | /* 32411 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v16i8] }:$src |
| 11441 | /* 32411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11442 | /* 32414 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11443 | /* 32416 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11444 | /* 32418 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11445 | /* 32423 */ // GIR_Coverage, 5846, |
| 11446 | /* 32423 */ GIR_EraseRootFromParent_Done, |
| 11447 | /* 32424 */ // Label 814: @32424 |
| 11448 | /* 32424 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 815*/ GIMT_Encode4(32470), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5881 // |
| 11449 | /* 32431 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) |
| 11450 | /* 32431 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11451 | /* 32434 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11452 | /* 32438 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11453 | /* 32443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 11454 | /* 32446 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11455 | /* 32448 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11456 | /* 32450 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11457 | /* 32453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11458 | /* 32459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11459 | /* 32465 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11460 | /* 32468 */ GIR_RootConstrainSelectedInstOperands, |
| 11461 | /* 32469 */ // GIR_Coverage, 5881, |
| 11462 | /* 32469 */ GIR_EraseRootFromParent_Done, |
| 11463 | /* 32470 */ // Label 815: @32470 |
| 11464 | /* 32470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 816*/ GIMT_Encode4(32516), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5882 // |
| 11465 | /* 32477 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) |
| 11466 | /* 32477 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11467 | /* 32480 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11468 | /* 32484 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11469 | /* 32489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 11470 | /* 32492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11471 | /* 32494 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11472 | /* 32496 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11473 | /* 32499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11474 | /* 32505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11475 | /* 32511 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11476 | /* 32514 */ GIR_RootConstrainSelectedInstOperands, |
| 11477 | /* 32515 */ // GIR_Coverage, 5882, |
| 11478 | /* 32515 */ GIR_EraseRootFromParent_Done, |
| 11479 | /* 32516 */ // Label 816: @32516 |
| 11480 | /* 32516 */ GIM_Reject, |
| 11481 | /* 32517 */ // Label 812: @32517 |
| 11482 | /* 32517 */ GIM_Reject, |
| 11483 | /* 32518 */ // Label 786: @32518 |
| 11484 | /* 32518 */ GIM_Reject, |
| 11485 | /* 32519 */ // Label 722: @32519 |
| 11486 | /* 32519 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 821*/ GIMT_Encode4(33120), |
| 11487 | /* 32530 */ /*GILLT_s64*//*Label 817*/ GIMT_Encode4(32570), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 11488 | /* 32550 */ /*GILLT_v8s8*//*Label 818*/ GIMT_Encode4(32765), GIMT_Encode4(0), |
| 11489 | /* 32558 */ /*GILLT_v4s16*//*Label 819*/ GIMT_Encode4(32870), GIMT_Encode4(0), |
| 11490 | /* 32566 */ /*GILLT_v2s32*//*Label 820*/ GIMT_Encode4(32925), |
| 11491 | /* 32570 */ // Label 817: @32570 |
| 11492 | /* 32570 */ GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(32764), |
| 11493 | /* 32575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11494 | /* 32579 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11495 | /* 32583 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 823*/ GIMT_Encode4(32603), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3138 // |
| 11496 | /* 32590 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4f16] }:$src |
| 11497 | /* 32590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11498 | /* 32593 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11499 | /* 32595 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11500 | /* 32597 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11501 | /* 32602 */ // GIR_Coverage, 3138, |
| 11502 | /* 32602 */ GIR_EraseRootFromParent_Done, |
| 11503 | /* 32603 */ // Label 823: @32603 |
| 11504 | /* 32603 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 824*/ GIMT_Encode4(32623), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3139 // |
| 11505 | /* 32610 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4f16] }:$src |
| 11506 | /* 32610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11507 | /* 32613 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11508 | /* 32615 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11509 | /* 32617 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11510 | /* 32622 */ // GIR_Coverage, 3139, |
| 11511 | /* 32622 */ GIR_EraseRootFromParent_Done, |
| 11512 | /* 32623 */ // Label 824: @32623 |
| 11513 | /* 32623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 825*/ GIMT_Encode4(32643), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3143 // |
| 11514 | /* 32630 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4i16] }:$src |
| 11515 | /* 32630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11516 | /* 32633 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11517 | /* 32635 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11518 | /* 32637 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11519 | /* 32642 */ // GIR_Coverage, 3143, |
| 11520 | /* 32642 */ GIR_EraseRootFromParent_Done, |
| 11521 | /* 32643 */ // Label 825: @32643 |
| 11522 | /* 32643 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 826*/ GIMT_Encode4(32663), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3144 // |
| 11523 | /* 32650 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4i16] }:$src |
| 11524 | /* 32650 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11525 | /* 32653 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11526 | /* 32655 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11527 | /* 32657 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11528 | /* 32662 */ // GIR_Coverage, 3144, |
| 11529 | /* 32662 */ GIR_EraseRootFromParent_Done, |
| 11530 | /* 32663 */ // Label 826: @32663 |
| 11531 | /* 32663 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 827*/ GIMT_Encode4(32688), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3210 // |
| 11532 | /* 32670 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[f64] }:$src) |
| 11533 | /* 32670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 11534 | /* 32673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11535 | /* 32675 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11536 | /* 32677 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11537 | /* 32680 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11538 | /* 32686 */ GIR_RootConstrainSelectedInstOperands, |
| 11539 | /* 32687 */ // GIR_Coverage, 3210, |
| 11540 | /* 32687 */ GIR_EraseRootFromParent_Done, |
| 11541 | /* 32688 */ // Label 827: @32688 |
| 11542 | /* 32688 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 828*/ GIMT_Encode4(32713), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3211 // |
| 11543 | /* 32695 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) |
| 11544 | /* 32695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 11545 | /* 32698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11546 | /* 32700 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11547 | /* 32702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11548 | /* 32705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11549 | /* 32711 */ GIR_RootConstrainSelectedInstOperands, |
| 11550 | /* 32712 */ // GIR_Coverage, 3211, |
| 11551 | /* 32712 */ GIR_EraseRootFromParent_Done, |
| 11552 | /* 32713 */ // Label 828: @32713 |
| 11553 | /* 32713 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 829*/ GIMT_Encode4(32738), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3215 // |
| 11554 | /* 32720 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src) |
| 11555 | /* 32720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 11556 | /* 32723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11557 | /* 32725 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11558 | /* 32727 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11559 | /* 32730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11560 | /* 32736 */ GIR_RootConstrainSelectedInstOperands, |
| 11561 | /* 32737 */ // GIR_Coverage, 3215, |
| 11562 | /* 32737 */ GIR_EraseRootFromParent_Done, |
| 11563 | /* 32738 */ // Label 829: @32738 |
| 11564 | /* 32738 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 830*/ GIMT_Encode4(32763), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3216 // |
| 11565 | /* 32745 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) |
| 11566 | /* 32745 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16), |
| 11567 | /* 32748 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11568 | /* 32750 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11569 | /* 32752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11570 | /* 32755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11571 | /* 32761 */ GIR_RootConstrainSelectedInstOperands, |
| 11572 | /* 32762 */ // GIR_Coverage, 3216, |
| 11573 | /* 32762 */ GIR_EraseRootFromParent_Done, |
| 11574 | /* 32763 */ // Label 830: @32763 |
| 11575 | /* 32763 */ GIM_Reject, |
| 11576 | /* 32764 */ // Label 822: @32764 |
| 11577 | /* 32764 */ GIM_Reject, |
| 11578 | /* 32765 */ // Label 818: @32765 |
| 11579 | /* 32765 */ GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(32869), |
| 11580 | /* 32770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11581 | /* 32774 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11582 | /* 32778 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 832*/ GIMT_Encode4(32798), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3142 // |
| 11583 | /* 32785 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4f16] }:$src |
| 11584 | /* 32785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11585 | /* 32788 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11586 | /* 32790 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11587 | /* 32792 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11588 | /* 32797 */ // GIR_Coverage, 3142, |
| 11589 | /* 32797 */ GIR_EraseRootFromParent_Done, |
| 11590 | /* 32798 */ // Label 832: @32798 |
| 11591 | /* 32798 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 833*/ GIMT_Encode4(32818), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3147 // |
| 11592 | /* 32805 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4i16] }:$src |
| 11593 | /* 32805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11594 | /* 32808 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11595 | /* 32810 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11596 | /* 32812 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11597 | /* 32817 */ // GIR_Coverage, 3147, |
| 11598 | /* 32817 */ GIR_EraseRootFromParent_Done, |
| 11599 | /* 32818 */ // Label 833: @32818 |
| 11600 | /* 32818 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 834*/ GIMT_Encode4(32843), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3214 // |
| 11601 | /* 32825 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) |
| 11602 | /* 32825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 11603 | /* 32828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11604 | /* 32830 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11605 | /* 32832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11606 | /* 32835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11607 | /* 32841 */ GIR_RootConstrainSelectedInstOperands, |
| 11608 | /* 32842 */ // GIR_Coverage, 3214, |
| 11609 | /* 32842 */ GIR_EraseRootFromParent_Done, |
| 11610 | /* 32843 */ // Label 834: @32843 |
| 11611 | /* 32843 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 835*/ GIMT_Encode4(32868), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3219 // |
| 11612 | /* 32850 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) |
| 11613 | /* 32850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8), |
| 11614 | /* 32853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11615 | /* 32855 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11616 | /* 32857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11617 | /* 32860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11618 | /* 32866 */ GIR_RootConstrainSelectedInstOperands, |
| 11619 | /* 32867 */ // GIR_Coverage, 3219, |
| 11620 | /* 32867 */ GIR_EraseRootFromParent_Done, |
| 11621 | /* 32868 */ // Label 835: @32868 |
| 11622 | /* 32868 */ GIM_Reject, |
| 11623 | /* 32869 */ // Label 831: @32869 |
| 11624 | /* 32869 */ GIM_Reject, |
| 11625 | /* 32870 */ // Label 819: @32870 |
| 11626 | /* 32870 */ GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(32924), |
| 11627 | /* 32875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11628 | /* 32879 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11629 | /* 32883 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 837*/ GIMT_Encode4(32903), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3110 // |
| 11630 | /* 32890 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v4i16] }:$src |
| 11631 | /* 32890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11632 | /* 32893 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11633 | /* 32895 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11634 | /* 32897 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11635 | /* 32902 */ // GIR_Coverage, 3110, |
| 11636 | /* 32902 */ GIR_EraseRootFromParent_Done, |
| 11637 | /* 32903 */ // Label 837: @32903 |
| 11638 | /* 32903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 838*/ GIMT_Encode4(32923), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3111 // |
| 11639 | /* 32910 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v4f16] }:$src |
| 11640 | /* 32910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11641 | /* 32913 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11642 | /* 32915 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11643 | /* 32917 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11644 | /* 32922 */ // GIR_Coverage, 3111, |
| 11645 | /* 32922 */ GIR_EraseRootFromParent_Done, |
| 11646 | /* 32923 */ // Label 838: @32923 |
| 11647 | /* 32923 */ GIM_Reject, |
| 11648 | /* 32924 */ // Label 836: @32924 |
| 11649 | /* 32924 */ GIM_Reject, |
| 11650 | /* 32925 */ // Label 820: @32925 |
| 11651 | /* 32925 */ GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(33119), |
| 11652 | /* 32930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11653 | /* 32934 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 11654 | /* 32938 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 840*/ GIMT_Encode4(32958), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3140 // |
| 11655 | /* 32945 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4f16] }:$src |
| 11656 | /* 32945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11657 | /* 32948 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11658 | /* 32950 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11659 | /* 32952 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11660 | /* 32957 */ // GIR_Coverage, 3140, |
| 11661 | /* 32957 */ GIR_EraseRootFromParent_Done, |
| 11662 | /* 32958 */ // Label 840: @32958 |
| 11663 | /* 32958 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 841*/ GIMT_Encode4(32978), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3141 // |
| 11664 | /* 32965 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4f16] }:$src |
| 11665 | /* 32965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11666 | /* 32968 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11667 | /* 32970 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11668 | /* 32972 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11669 | /* 32977 */ // GIR_Coverage, 3141, |
| 11670 | /* 32977 */ GIR_EraseRootFromParent_Done, |
| 11671 | /* 32978 */ // Label 841: @32978 |
| 11672 | /* 32978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 842*/ GIMT_Encode4(32998), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3145 // |
| 11673 | /* 32985 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4i16] }:$src |
| 11674 | /* 32985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11675 | /* 32988 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11676 | /* 32990 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11677 | /* 32992 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11678 | /* 32997 */ // GIR_Coverage, 3145, |
| 11679 | /* 32997 */ GIR_EraseRootFromParent_Done, |
| 11680 | /* 32998 */ // Label 842: @32998 |
| 11681 | /* 32998 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 843*/ GIMT_Encode4(33018), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3146 // |
| 11682 | /* 33005 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4i16] }:$src |
| 11683 | /* 33005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11684 | /* 33008 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11685 | /* 33010 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11686 | /* 33012 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 11687 | /* 33017 */ // GIR_Coverage, 3146, |
| 11688 | /* 33017 */ GIR_EraseRootFromParent_Done, |
| 11689 | /* 33018 */ // Label 843: @33018 |
| 11690 | /* 33018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 844*/ GIMT_Encode4(33043), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3212 // |
| 11691 | /* 33025 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) |
| 11692 | /* 33025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 11693 | /* 33028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11694 | /* 33030 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11695 | /* 33032 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11696 | /* 33035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11697 | /* 33041 */ GIR_RootConstrainSelectedInstOperands, |
| 11698 | /* 33042 */ // GIR_Coverage, 3212, |
| 11699 | /* 33042 */ GIR_EraseRootFromParent_Done, |
| 11700 | /* 33043 */ // Label 844: @33043 |
| 11701 | /* 33043 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 845*/ GIMT_Encode4(33068), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3213 // |
| 11702 | /* 33050 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) |
| 11703 | /* 33050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 11704 | /* 33053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11705 | /* 33055 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11706 | /* 33057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11707 | /* 33060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11708 | /* 33066 */ GIR_RootConstrainSelectedInstOperands, |
| 11709 | /* 33067 */ // GIR_Coverage, 3213, |
| 11710 | /* 33067 */ GIR_EraseRootFromParent_Done, |
| 11711 | /* 33068 */ // Label 845: @33068 |
| 11712 | /* 33068 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 846*/ GIMT_Encode4(33093), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3217 // |
| 11713 | /* 33075 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) |
| 11714 | /* 33075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 11715 | /* 33078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11716 | /* 33080 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11717 | /* 33082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11718 | /* 33085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11719 | /* 33091 */ GIR_RootConstrainSelectedInstOperands, |
| 11720 | /* 33092 */ // GIR_Coverage, 3217, |
| 11721 | /* 33092 */ GIR_EraseRootFromParent_Done, |
| 11722 | /* 33093 */ // Label 846: @33093 |
| 11723 | /* 33093 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 847*/ GIMT_Encode4(33118), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3218 // |
| 11724 | /* 33100 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) |
| 11725 | /* 33100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 11726 | /* 33103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11727 | /* 33105 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11728 | /* 33107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11729 | /* 33110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11730 | /* 33116 */ GIR_RootConstrainSelectedInstOperands, |
| 11731 | /* 33117 */ // GIR_Coverage, 3218, |
| 11732 | /* 33117 */ GIR_EraseRootFromParent_Done, |
| 11733 | /* 33118 */ // Label 847: @33118 |
| 11734 | /* 33118 */ GIM_Reject, |
| 11735 | /* 33119 */ // Label 839: @33119 |
| 11736 | /* 33119 */ GIM_Reject, |
| 11737 | /* 33120 */ // Label 821: @33120 |
| 11738 | /* 33120 */ GIM_Reject, |
| 11739 | /* 33121 */ // Label 723: @33121 |
| 11740 | /* 33121 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 852*/ GIMT_Encode4(34462), |
| 11741 | /* 33132 */ /*GILLT_v16s8*//*Label 848*/ GIMT_Encode4(33156), GIMT_Encode4(0), |
| 11742 | /* 33140 */ /*GILLT_v8s16*//*Label 849*/ GIMT_Encode4(33407), GIMT_Encode4(0), |
| 11743 | /* 33148 */ /*GILLT_v4s32*//*Label 850*/ GIMT_Encode4(33516), |
| 11744 | /* 33152 */ /*GILLT_v2s64*//*Label 851*/ GIMT_Encode4(33989), |
| 11745 | /* 33156 */ // Label 848: @33156 |
| 11746 | /* 33156 */ GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(33260), |
| 11747 | /* 33161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11748 | /* 33165 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11749 | /* 33169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 854*/ GIMT_Encode4(33189), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3178 // |
| 11750 | /* 33176 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8f16] }:$src |
| 11751 | /* 33176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11752 | /* 33179 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11753 | /* 33181 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11754 | /* 33183 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11755 | /* 33188 */ // GIR_Coverage, 3178, |
| 11756 | /* 33188 */ GIR_EraseRootFromParent_Done, |
| 11757 | /* 33189 */ // Label 854: @33189 |
| 11758 | /* 33189 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 855*/ GIMT_Encode4(33209), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3183 // |
| 11759 | /* 33196 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8i16] }:$src |
| 11760 | /* 33196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11761 | /* 33199 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11762 | /* 33201 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11763 | /* 33203 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11764 | /* 33208 */ // GIR_Coverage, 3183, |
| 11765 | /* 33208 */ GIR_EraseRootFromParent_Done, |
| 11766 | /* 33209 */ // Label 855: @33209 |
| 11767 | /* 33209 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 856*/ GIMT_Encode4(33234), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3250 // |
| 11768 | /* 33216 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) |
| 11769 | /* 33216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 11770 | /* 33219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11771 | /* 33221 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11772 | /* 33223 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11773 | /* 33226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11774 | /* 33232 */ GIR_RootConstrainSelectedInstOperands, |
| 11775 | /* 33233 */ // GIR_Coverage, 3250, |
| 11776 | /* 33233 */ GIR_EraseRootFromParent_Done, |
| 11777 | /* 33234 */ // Label 856: @33234 |
| 11778 | /* 33234 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 857*/ GIMT_Encode4(33259), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3255 // |
| 11779 | /* 33241 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) |
| 11780 | /* 33241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8), |
| 11781 | /* 33244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11782 | /* 33246 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11783 | /* 33248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11784 | /* 33251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11785 | /* 33257 */ GIR_RootConstrainSelectedInstOperands, |
| 11786 | /* 33258 */ // GIR_Coverage, 3255, |
| 11787 | /* 33258 */ GIR_EraseRootFromParent_Done, |
| 11788 | /* 33259 */ // Label 857: @33259 |
| 11789 | /* 33259 */ GIM_Reject, |
| 11790 | /* 33260 */ // Label 853: @33260 |
| 11791 | /* 33260 */ GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(33406), |
| 11792 | /* 33265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11793 | /* 33269 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11794 | /* 33273 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 859*/ GIMT_Encode4(33293), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5839 // |
| 11795 | /* 33280 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 11796 | /* 33280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11797 | /* 33283 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11798 | /* 33285 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11799 | /* 33287 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11800 | /* 33292 */ // GIR_Coverage, 5839, |
| 11801 | /* 33292 */ GIR_EraseRootFromParent_Done, |
| 11802 | /* 33293 */ // Label 859: @33293 |
| 11803 | /* 33293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 860*/ GIMT_Encode4(33313), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5844 // |
| 11804 | /* 33300 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 11805 | /* 33300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11806 | /* 33303 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11807 | /* 33305 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11808 | /* 33307 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11809 | /* 33312 */ // GIR_Coverage, 5844, |
| 11810 | /* 33312 */ GIR_EraseRootFromParent_Done, |
| 11811 | /* 33313 */ // Label 860: @33313 |
| 11812 | /* 33313 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 861*/ GIMT_Encode4(33359), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5875 // |
| 11813 | /* 33320 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) |
| 11814 | /* 33320 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11815 | /* 33323 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11816 | /* 33327 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11817 | /* 33332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 11818 | /* 33335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11819 | /* 33337 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11820 | /* 33339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11821 | /* 33342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11822 | /* 33348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11823 | /* 33354 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11824 | /* 33357 */ GIR_RootConstrainSelectedInstOperands, |
| 11825 | /* 33358 */ // GIR_Coverage, 5875, |
| 11826 | /* 33358 */ GIR_EraseRootFromParent_Done, |
| 11827 | /* 33359 */ // Label 861: @33359 |
| 11828 | /* 33359 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 862*/ GIMT_Encode4(33405), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5880 // |
| 11829 | /* 33366 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 11830 | /* 33366 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 11831 | /* 33369 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 11832 | /* 33373 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 11833 | /* 33378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 11834 | /* 33381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 11835 | /* 33383 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11836 | /* 33385 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 11837 | /* 33388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11838 | /* 33394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11839 | /* 33400 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 11840 | /* 33403 */ GIR_RootConstrainSelectedInstOperands, |
| 11841 | /* 33404 */ // GIR_Coverage, 5880, |
| 11842 | /* 33404 */ GIR_EraseRootFromParent_Done, |
| 11843 | /* 33405 */ // Label 862: @33405 |
| 11844 | /* 33405 */ GIM_Reject, |
| 11845 | /* 33406 */ // Label 858: @33406 |
| 11846 | /* 33406 */ GIM_Reject, |
| 11847 | /* 33407 */ // Label 849: @33407 |
| 11848 | /* 33407 */ GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(33461), |
| 11849 | /* 33412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11850 | /* 33416 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11851 | /* 33420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 864*/ GIMT_Encode4(33440), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3116 // |
| 11852 | /* 33427 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v8i16] }:$src |
| 11853 | /* 33427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11854 | /* 33430 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11855 | /* 33432 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11856 | /* 33434 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11857 | /* 33439 */ // GIR_Coverage, 3116, |
| 11858 | /* 33439 */ GIR_EraseRootFromParent_Done, |
| 11859 | /* 33440 */ // Label 864: @33440 |
| 11860 | /* 33440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 865*/ GIMT_Encode4(33460), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3117 // |
| 11861 | /* 33447 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v8f16] }:$src |
| 11862 | /* 33447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11863 | /* 33450 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11864 | /* 33452 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11865 | /* 33454 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11866 | /* 33459 */ // GIR_Coverage, 3117, |
| 11867 | /* 33459 */ GIR_EraseRootFromParent_Done, |
| 11868 | /* 33460 */ // Label 865: @33460 |
| 11869 | /* 33460 */ GIM_Reject, |
| 11870 | /* 33461 */ // Label 863: @33461 |
| 11871 | /* 33461 */ GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(33515), |
| 11872 | /* 33466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11873 | /* 33470 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11874 | /* 33474 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 867*/ GIMT_Encode4(33494), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5813 // |
| 11875 | /* 33481 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 11876 | /* 33481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11877 | /* 33484 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11878 | /* 33486 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11879 | /* 33488 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11880 | /* 33493 */ // GIR_Coverage, 5813, |
| 11881 | /* 33493 */ GIR_EraseRootFromParent_Done, |
| 11882 | /* 33494 */ // Label 867: @33494 |
| 11883 | /* 33494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 868*/ GIMT_Encode4(33514), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5814 // |
| 11884 | /* 33501 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 11885 | /* 33501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11886 | /* 33504 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11887 | /* 33506 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11888 | /* 33508 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11889 | /* 33513 */ // GIR_Coverage, 5814, |
| 11890 | /* 33513 */ GIR_EraseRootFromParent_Done, |
| 11891 | /* 33514 */ // Label 868: @33514 |
| 11892 | /* 33514 */ GIM_Reject, |
| 11893 | /* 33515 */ // Label 866: @33515 |
| 11894 | /* 33515 */ GIM_Reject, |
| 11895 | /* 33516 */ // Label 850: @33516 |
| 11896 | /* 33516 */ GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(33710), |
| 11897 | /* 33521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11898 | /* 33525 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 11899 | /* 33529 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 870*/ GIMT_Encode4(33549), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3176 // |
| 11900 | /* 33536 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8f16] }:$src |
| 11901 | /* 33536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11902 | /* 33539 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11903 | /* 33541 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11904 | /* 33543 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11905 | /* 33548 */ // GIR_Coverage, 3176, |
| 11906 | /* 33548 */ GIR_EraseRootFromParent_Done, |
| 11907 | /* 33549 */ // Label 870: @33549 |
| 11908 | /* 33549 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 871*/ GIMT_Encode4(33569), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3177 // |
| 11909 | /* 33556 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8f16] }:$src |
| 11910 | /* 33556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11911 | /* 33559 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11912 | /* 33561 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11913 | /* 33563 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11914 | /* 33568 */ // GIR_Coverage, 3177, |
| 11915 | /* 33568 */ GIR_EraseRootFromParent_Done, |
| 11916 | /* 33569 */ // Label 871: @33569 |
| 11917 | /* 33569 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 872*/ GIMT_Encode4(33589), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3181 // |
| 11918 | /* 33576 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8i16] }:$src |
| 11919 | /* 33576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11920 | /* 33579 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11921 | /* 33581 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11922 | /* 33583 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11923 | /* 33588 */ // GIR_Coverage, 3181, |
| 11924 | /* 33588 */ GIR_EraseRootFromParent_Done, |
| 11925 | /* 33589 */ // Label 872: @33589 |
| 11926 | /* 33589 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 873*/ GIMT_Encode4(33609), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3182 // |
| 11927 | /* 33596 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8i16] }:$src |
| 11928 | /* 33596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11929 | /* 33599 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11930 | /* 33601 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11931 | /* 33603 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 11932 | /* 33608 */ // GIR_Coverage, 3182, |
| 11933 | /* 33608 */ GIR_EraseRootFromParent_Done, |
| 11934 | /* 33609 */ // Label 873: @33609 |
| 11935 | /* 33609 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 874*/ GIMT_Encode4(33634), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3248 // |
| 11936 | /* 33616 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) |
| 11937 | /* 33616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11938 | /* 33619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11939 | /* 33621 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11940 | /* 33623 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11941 | /* 33626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11942 | /* 33632 */ GIR_RootConstrainSelectedInstOperands, |
| 11943 | /* 33633 */ // GIR_Coverage, 3248, |
| 11944 | /* 33633 */ GIR_EraseRootFromParent_Done, |
| 11945 | /* 33634 */ // Label 874: @33634 |
| 11946 | /* 33634 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 875*/ GIMT_Encode4(33659), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3249 // |
| 11947 | /* 33641 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) |
| 11948 | /* 33641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11949 | /* 33644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11950 | /* 33646 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11951 | /* 33648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11952 | /* 33651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11953 | /* 33657 */ GIR_RootConstrainSelectedInstOperands, |
| 11954 | /* 33658 */ // GIR_Coverage, 3249, |
| 11955 | /* 33658 */ GIR_EraseRootFromParent_Done, |
| 11956 | /* 33659 */ // Label 875: @33659 |
| 11957 | /* 33659 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 876*/ GIMT_Encode4(33684), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3253 // |
| 11958 | /* 33666 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) |
| 11959 | /* 33666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11960 | /* 33669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11961 | /* 33671 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11962 | /* 33673 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11963 | /* 33676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11964 | /* 33682 */ GIR_RootConstrainSelectedInstOperands, |
| 11965 | /* 33683 */ // GIR_Coverage, 3253, |
| 11966 | /* 33683 */ GIR_EraseRootFromParent_Done, |
| 11967 | /* 33684 */ // Label 876: @33684 |
| 11968 | /* 33684 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 877*/ GIMT_Encode4(33709), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3254 // |
| 11969 | /* 33691 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) |
| 11970 | /* 33691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 11971 | /* 33694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 11972 | /* 33696 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11973 | /* 33698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 11974 | /* 33701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 11975 | /* 33707 */ GIR_RootConstrainSelectedInstOperands, |
| 11976 | /* 33708 */ // GIR_Coverage, 3254, |
| 11977 | /* 33708 */ GIR_EraseRootFromParent_Done, |
| 11978 | /* 33709 */ // Label 877: @33709 |
| 11979 | /* 33709 */ GIM_Reject, |
| 11980 | /* 33710 */ // Label 869: @33710 |
| 11981 | /* 33710 */ GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(33988), |
| 11982 | /* 33715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11983 | /* 33719 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 11984 | /* 33723 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 879*/ GIMT_Encode4(33743), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5837 // |
| 11985 | /* 33730 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 11986 | /* 33730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11987 | /* 33733 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11988 | /* 33735 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11989 | /* 33737 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11990 | /* 33742 */ // GIR_Coverage, 5837, |
| 11991 | /* 33742 */ GIR_EraseRootFromParent_Done, |
| 11992 | /* 33743 */ // Label 879: @33743 |
| 11993 | /* 33743 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 880*/ GIMT_Encode4(33763), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5838 // |
| 11994 | /* 33750 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 11995 | /* 33750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11996 | /* 33753 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11997 | /* 33755 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 11998 | /* 33757 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 11999 | /* 33762 */ // GIR_Coverage, 5838, |
| 12000 | /* 33762 */ GIR_EraseRootFromParent_Done, |
| 12001 | /* 33763 */ // Label 880: @33763 |
| 12002 | /* 33763 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 881*/ GIMT_Encode4(33783), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5842 // |
| 12003 | /* 33770 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 12004 | /* 33770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12005 | /* 33773 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12006 | /* 33775 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12007 | /* 33777 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12008 | /* 33782 */ // GIR_Coverage, 5842, |
| 12009 | /* 33782 */ GIR_EraseRootFromParent_Done, |
| 12010 | /* 33783 */ // Label 881: @33783 |
| 12011 | /* 33783 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 882*/ GIMT_Encode4(33803), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5843 // |
| 12012 | /* 33790 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 12013 | /* 33790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12014 | /* 33793 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12015 | /* 33795 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12016 | /* 33797 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12017 | /* 33802 */ // GIR_Coverage, 5843, |
| 12018 | /* 33802 */ GIR_EraseRootFromParent_Done, |
| 12019 | /* 33803 */ // Label 882: @33803 |
| 12020 | /* 33803 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 883*/ GIMT_Encode4(33849), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5873 // |
| 12021 | /* 33810 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) |
| 12022 | /* 33810 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12023 | /* 33813 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12024 | /* 33817 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12025 | /* 33822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12026 | /* 33825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12027 | /* 33827 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12028 | /* 33829 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12029 | /* 33832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12030 | /* 33838 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12031 | /* 33844 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12032 | /* 33847 */ GIR_RootConstrainSelectedInstOperands, |
| 12033 | /* 33848 */ // GIR_Coverage, 5873, |
| 12034 | /* 33848 */ GIR_EraseRootFromParent_Done, |
| 12035 | /* 33849 */ // Label 883: @33849 |
| 12036 | /* 33849 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 884*/ GIMT_Encode4(33895), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5874 // |
| 12037 | /* 33856 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) |
| 12038 | /* 33856 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12039 | /* 33859 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12040 | /* 33863 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12041 | /* 33868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12042 | /* 33871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12043 | /* 33873 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12044 | /* 33875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12045 | /* 33878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12046 | /* 33884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12047 | /* 33890 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12048 | /* 33893 */ GIR_RootConstrainSelectedInstOperands, |
| 12049 | /* 33894 */ // GIR_Coverage, 5874, |
| 12050 | /* 33894 */ GIR_EraseRootFromParent_Done, |
| 12051 | /* 33895 */ // Label 884: @33895 |
| 12052 | /* 33895 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 885*/ GIMT_Encode4(33941), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5878 // |
| 12053 | /* 33902 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) |
| 12054 | /* 33902 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12055 | /* 33905 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12056 | /* 33909 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12057 | /* 33914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12058 | /* 33917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12059 | /* 33919 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12060 | /* 33921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12061 | /* 33924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12062 | /* 33930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12063 | /* 33936 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12064 | /* 33939 */ GIR_RootConstrainSelectedInstOperands, |
| 12065 | /* 33940 */ // GIR_Coverage, 5878, |
| 12066 | /* 33940 */ GIR_EraseRootFromParent_Done, |
| 12067 | /* 33941 */ // Label 885: @33941 |
| 12068 | /* 33941 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 886*/ GIMT_Encode4(33987), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5879 // |
| 12069 | /* 33948 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) |
| 12070 | /* 33948 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12071 | /* 33951 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12072 | /* 33955 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12073 | /* 33960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12074 | /* 33963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12075 | /* 33965 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12076 | /* 33967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12077 | /* 33970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12078 | /* 33976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12079 | /* 33982 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12080 | /* 33985 */ GIR_RootConstrainSelectedInstOperands, |
| 12081 | /* 33986 */ // GIR_Coverage, 5879, |
| 12082 | /* 33986 */ GIR_EraseRootFromParent_Done, |
| 12083 | /* 33987 */ // Label 886: @33987 |
| 12084 | /* 33987 */ GIM_Reject, |
| 12085 | /* 33988 */ // Label 878: @33988 |
| 12086 | /* 33988 */ GIM_Reject, |
| 12087 | /* 33989 */ // Label 851: @33989 |
| 12088 | /* 33989 */ GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(34183), |
| 12089 | /* 33994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12090 | /* 33998 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12091 | /* 34002 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 888*/ GIMT_Encode4(34022), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3174 // |
| 12092 | /* 34009 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8f16] }:$src |
| 12093 | /* 34009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12094 | /* 34012 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12095 | /* 34014 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12096 | /* 34016 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12097 | /* 34021 */ // GIR_Coverage, 3174, |
| 12098 | /* 34021 */ GIR_EraseRootFromParent_Done, |
| 12099 | /* 34022 */ // Label 888: @34022 |
| 12100 | /* 34022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 889*/ GIMT_Encode4(34042), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3175 // |
| 12101 | /* 34029 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8f16] }:$src |
| 12102 | /* 34029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12103 | /* 34032 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12104 | /* 34034 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12105 | /* 34036 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12106 | /* 34041 */ // GIR_Coverage, 3175, |
| 12107 | /* 34041 */ GIR_EraseRootFromParent_Done, |
| 12108 | /* 34042 */ // Label 889: @34042 |
| 12109 | /* 34042 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 890*/ GIMT_Encode4(34062), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3179 // |
| 12110 | /* 34049 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8i16] }:$src |
| 12111 | /* 34049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12112 | /* 34052 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12113 | /* 34054 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12114 | /* 34056 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12115 | /* 34061 */ // GIR_Coverage, 3179, |
| 12116 | /* 34061 */ GIR_EraseRootFromParent_Done, |
| 12117 | /* 34062 */ // Label 890: @34062 |
| 12118 | /* 34062 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 891*/ GIMT_Encode4(34082), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3180 // |
| 12119 | /* 34069 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8i16] }:$src |
| 12120 | /* 34069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12121 | /* 34072 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12122 | /* 34074 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12123 | /* 34076 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12124 | /* 34081 */ // GIR_Coverage, 3180, |
| 12125 | /* 34081 */ GIR_EraseRootFromParent_Done, |
| 12126 | /* 34082 */ // Label 891: @34082 |
| 12127 | /* 34082 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 892*/ GIMT_Encode4(34107), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3246 // |
| 12128 | /* 34089 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) |
| 12129 | /* 34089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 12130 | /* 34092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12131 | /* 34094 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12132 | /* 34096 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12133 | /* 34099 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12134 | /* 34105 */ GIR_RootConstrainSelectedInstOperands, |
| 12135 | /* 34106 */ // GIR_Coverage, 3246, |
| 12136 | /* 34106 */ GIR_EraseRootFromParent_Done, |
| 12137 | /* 34107 */ // Label 892: @34107 |
| 12138 | /* 34107 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 893*/ GIMT_Encode4(34132), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3247 // |
| 12139 | /* 34114 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) |
| 12140 | /* 34114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 12141 | /* 34117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12142 | /* 34119 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12143 | /* 34121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12144 | /* 34124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12145 | /* 34130 */ GIR_RootConstrainSelectedInstOperands, |
| 12146 | /* 34131 */ // GIR_Coverage, 3247, |
| 12147 | /* 34131 */ GIR_EraseRootFromParent_Done, |
| 12148 | /* 34132 */ // Label 893: @34132 |
| 12149 | /* 34132 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 894*/ GIMT_Encode4(34157), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3251 // |
| 12150 | /* 34139 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) |
| 12151 | /* 34139 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 12152 | /* 34142 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12153 | /* 34144 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12154 | /* 34146 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12155 | /* 34149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12156 | /* 34155 */ GIR_RootConstrainSelectedInstOperands, |
| 12157 | /* 34156 */ // GIR_Coverage, 3251, |
| 12158 | /* 34156 */ GIR_EraseRootFromParent_Done, |
| 12159 | /* 34157 */ // Label 894: @34157 |
| 12160 | /* 34157 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 895*/ GIMT_Encode4(34182), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3252 // |
| 12161 | /* 34164 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) |
| 12162 | /* 34164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 12163 | /* 34167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12164 | /* 34169 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12165 | /* 34171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12166 | /* 34174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12167 | /* 34180 */ GIR_RootConstrainSelectedInstOperands, |
| 12168 | /* 34181 */ // GIR_Coverage, 3252, |
| 12169 | /* 34181 */ GIR_EraseRootFromParent_Done, |
| 12170 | /* 34182 */ // Label 895: @34182 |
| 12171 | /* 34182 */ GIM_Reject, |
| 12172 | /* 34183 */ // Label 887: @34183 |
| 12173 | /* 34183 */ GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(34461), |
| 12174 | /* 34188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12175 | /* 34192 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12176 | /* 34196 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 897*/ GIMT_Encode4(34216), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5835 // |
| 12177 | /* 34203 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 12178 | /* 34203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12179 | /* 34206 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12180 | /* 34208 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12181 | /* 34210 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12182 | /* 34215 */ // GIR_Coverage, 5835, |
| 12183 | /* 34215 */ GIR_EraseRootFromParent_Done, |
| 12184 | /* 34216 */ // Label 897: @34216 |
| 12185 | /* 34216 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 898*/ GIMT_Encode4(34236), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5836 // |
| 12186 | /* 34223 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8f16] }:$src |
| 12187 | /* 34223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12188 | /* 34226 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12189 | /* 34228 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12190 | /* 34230 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12191 | /* 34235 */ // GIR_Coverage, 5836, |
| 12192 | /* 34235 */ GIR_EraseRootFromParent_Done, |
| 12193 | /* 34236 */ // Label 898: @34236 |
| 12194 | /* 34236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 899*/ GIMT_Encode4(34256), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5840 // |
| 12195 | /* 34243 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 12196 | /* 34243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12197 | /* 34246 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12198 | /* 34248 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12199 | /* 34250 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12200 | /* 34255 */ // GIR_Coverage, 5840, |
| 12201 | /* 34255 */ GIR_EraseRootFromParent_Done, |
| 12202 | /* 34256 */ // Label 899: @34256 |
| 12203 | /* 34256 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 900*/ GIMT_Encode4(34276), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5841 // |
| 12204 | /* 34263 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8i16] }:$src |
| 12205 | /* 34263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12206 | /* 34266 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12207 | /* 34268 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12208 | /* 34270 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12209 | /* 34275 */ // GIR_Coverage, 5841, |
| 12210 | /* 34275 */ GIR_EraseRootFromParent_Done, |
| 12211 | /* 34276 */ // Label 900: @34276 |
| 12212 | /* 34276 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 901*/ GIMT_Encode4(34322), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5871 // |
| 12213 | /* 34283 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) |
| 12214 | /* 34283 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12215 | /* 34286 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12216 | /* 34290 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12217 | /* 34295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12218 | /* 34298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12219 | /* 34300 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12220 | /* 34302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12221 | /* 34305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12222 | /* 34311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12223 | /* 34317 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12224 | /* 34320 */ GIR_RootConstrainSelectedInstOperands, |
| 12225 | /* 34321 */ // GIR_Coverage, 5871, |
| 12226 | /* 34321 */ GIR_EraseRootFromParent_Done, |
| 12227 | /* 34322 */ // Label 901: @34322 |
| 12228 | /* 34322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 902*/ GIMT_Encode4(34368), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5872 // |
| 12229 | /* 34329 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) |
| 12230 | /* 34329 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12231 | /* 34332 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12232 | /* 34336 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12233 | /* 34341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12234 | /* 34344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12235 | /* 34346 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12236 | /* 34348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12237 | /* 34351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12238 | /* 34357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12239 | /* 34363 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12240 | /* 34366 */ GIR_RootConstrainSelectedInstOperands, |
| 12241 | /* 34367 */ // GIR_Coverage, 5872, |
| 12242 | /* 34367 */ GIR_EraseRootFromParent_Done, |
| 12243 | /* 34368 */ // Label 902: @34368 |
| 12244 | /* 34368 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 903*/ GIMT_Encode4(34414), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5876 // |
| 12245 | /* 34375 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) |
| 12246 | /* 34375 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12247 | /* 34378 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12248 | /* 34382 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12249 | /* 34387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12250 | /* 34390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12251 | /* 34392 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12252 | /* 34394 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12253 | /* 34397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12254 | /* 34403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12255 | /* 34409 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12256 | /* 34412 */ GIR_RootConstrainSelectedInstOperands, |
| 12257 | /* 34413 */ // GIR_Coverage, 5876, |
| 12258 | /* 34413 */ GIR_EraseRootFromParent_Done, |
| 12259 | /* 34414 */ // Label 903: @34414 |
| 12260 | /* 34414 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 904*/ GIMT_Encode4(34460), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5877 // |
| 12261 | /* 34421 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) |
| 12262 | /* 34421 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12263 | /* 34424 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12264 | /* 34428 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12265 | /* 34433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 12266 | /* 34436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12267 | /* 34438 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12268 | /* 34440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12269 | /* 34443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12270 | /* 34449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12271 | /* 34455 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12272 | /* 34458 */ GIR_RootConstrainSelectedInstOperands, |
| 12273 | /* 34459 */ // GIR_Coverage, 5877, |
| 12274 | /* 34459 */ GIR_EraseRootFromParent_Done, |
| 12275 | /* 34460 */ // Label 904: @34460 |
| 12276 | /* 34460 */ GIM_Reject, |
| 12277 | /* 34461 */ // Label 896: @34461 |
| 12278 | /* 34461 */ GIM_Reject, |
| 12279 | /* 34462 */ // Label 852: @34462 |
| 12280 | /* 34462 */ GIM_Reject, |
| 12281 | /* 34463 */ // Label 724: @34463 |
| 12282 | /* 34463 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 909*/ GIMT_Encode4(35064), |
| 12283 | /* 34474 */ /*GILLT_s64*//*Label 905*/ GIMT_Encode4(34514), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 12284 | /* 34494 */ /*GILLT_v8s8*//*Label 906*/ GIMT_Encode4(34709), GIMT_Encode4(0), |
| 12285 | /* 34502 */ /*GILLT_v4s16*//*Label 907*/ GIMT_Encode4(34814), GIMT_Encode4(0), |
| 12286 | /* 34510 */ /*GILLT_v2s32*//*Label 908*/ GIMT_Encode4(35009), |
| 12287 | /* 34514 */ // Label 905: @34514 |
| 12288 | /* 34514 */ GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(34708), |
| 12289 | /* 34519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12290 | /* 34523 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12291 | /* 34527 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 911*/ GIMT_Encode4(34547), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3128 // |
| 12292 | /* 34534 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2f32] }:$src |
| 12293 | /* 34534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12294 | /* 34537 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12295 | /* 34539 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12296 | /* 34541 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12297 | /* 34546 */ // GIR_Coverage, 3128, |
| 12298 | /* 34546 */ GIR_EraseRootFromParent_Done, |
| 12299 | /* 34547 */ // Label 911: @34547 |
| 12300 | /* 34547 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 912*/ GIMT_Encode4(34567), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3129 // |
| 12301 | /* 34554 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2f32] }:$src |
| 12302 | /* 34554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12303 | /* 34557 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12304 | /* 34559 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12305 | /* 34561 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12306 | /* 34566 */ // GIR_Coverage, 3129, |
| 12307 | /* 34566 */ GIR_EraseRootFromParent_Done, |
| 12308 | /* 34567 */ // Label 912: @34567 |
| 12309 | /* 34567 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 913*/ GIMT_Encode4(34587), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3133 // |
| 12310 | /* 34574 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2i32] }:$src |
| 12311 | /* 34574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12312 | /* 34577 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12313 | /* 34579 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12314 | /* 34581 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12315 | /* 34586 */ // GIR_Coverage, 3133, |
| 12316 | /* 34586 */ GIR_EraseRootFromParent_Done, |
| 12317 | /* 34587 */ // Label 913: @34587 |
| 12318 | /* 34587 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 914*/ GIMT_Encode4(34607), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3134 // |
| 12319 | /* 34594 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2i32] }:$src |
| 12320 | /* 34594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12321 | /* 34597 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12322 | /* 34599 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12323 | /* 34601 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12324 | /* 34606 */ // GIR_Coverage, 3134, |
| 12325 | /* 34606 */ GIR_EraseRootFromParent_Done, |
| 12326 | /* 34607 */ // Label 914: @34607 |
| 12327 | /* 34607 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 915*/ GIMT_Encode4(34632), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3200 // |
| 12328 | /* 34614 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src) |
| 12329 | /* 34614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 12330 | /* 34617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12331 | /* 34619 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12332 | /* 34621 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12333 | /* 34624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12334 | /* 34630 */ GIR_RootConstrainSelectedInstOperands, |
| 12335 | /* 34631 */ // GIR_Coverage, 3200, |
| 12336 | /* 34631 */ GIR_EraseRootFromParent_Done, |
| 12337 | /* 34632 */ // Label 915: @34632 |
| 12338 | /* 34632 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 916*/ GIMT_Encode4(34657), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3201 // |
| 12339 | /* 34639 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) |
| 12340 | /* 34639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 12341 | /* 34642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12342 | /* 34644 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12343 | /* 34646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12344 | /* 34649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12345 | /* 34655 */ GIR_RootConstrainSelectedInstOperands, |
| 12346 | /* 34656 */ // GIR_Coverage, 3201, |
| 12347 | /* 34656 */ GIR_EraseRootFromParent_Done, |
| 12348 | /* 34657 */ // Label 916: @34657 |
| 12349 | /* 34657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 917*/ GIMT_Encode4(34682), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3205 // |
| 12350 | /* 34664 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src) |
| 12351 | /* 34664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 12352 | /* 34667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12353 | /* 34669 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12354 | /* 34671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12355 | /* 34674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12356 | /* 34680 */ GIR_RootConstrainSelectedInstOperands, |
| 12357 | /* 34681 */ // GIR_Coverage, 3205, |
| 12358 | /* 34681 */ GIR_EraseRootFromParent_Done, |
| 12359 | /* 34682 */ // Label 917: @34682 |
| 12360 | /* 34682 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 918*/ GIMT_Encode4(34707), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3206 // |
| 12361 | /* 34689 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) |
| 12362 | /* 34689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32), |
| 12363 | /* 34692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12364 | /* 34694 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12365 | /* 34696 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12366 | /* 34699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12367 | /* 34705 */ GIR_RootConstrainSelectedInstOperands, |
| 12368 | /* 34706 */ // GIR_Coverage, 3206, |
| 12369 | /* 34706 */ GIR_EraseRootFromParent_Done, |
| 12370 | /* 34707 */ // Label 918: @34707 |
| 12371 | /* 34707 */ GIM_Reject, |
| 12372 | /* 34708 */ // Label 910: @34708 |
| 12373 | /* 34708 */ GIM_Reject, |
| 12374 | /* 34709 */ // Label 906: @34709 |
| 12375 | /* 34709 */ GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(34813), |
| 12376 | /* 34714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12377 | /* 34718 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12378 | /* 34722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 920*/ GIMT_Encode4(34742), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3132 // |
| 12379 | /* 34729 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2f32] }:$src |
| 12380 | /* 34729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12381 | /* 34732 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12382 | /* 34734 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12383 | /* 34736 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12384 | /* 34741 */ // GIR_Coverage, 3132, |
| 12385 | /* 34741 */ GIR_EraseRootFromParent_Done, |
| 12386 | /* 34742 */ // Label 920: @34742 |
| 12387 | /* 34742 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 921*/ GIMT_Encode4(34762), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3137 // |
| 12388 | /* 34749 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2i32] }:$src |
| 12389 | /* 34749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12390 | /* 34752 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12391 | /* 34754 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12392 | /* 34756 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12393 | /* 34761 */ // GIR_Coverage, 3137, |
| 12394 | /* 34761 */ GIR_EraseRootFromParent_Done, |
| 12395 | /* 34762 */ // Label 921: @34762 |
| 12396 | /* 34762 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 922*/ GIMT_Encode4(34787), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3204 // |
| 12397 | /* 34769 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) |
| 12398 | /* 34769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 12399 | /* 34772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12400 | /* 34774 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12401 | /* 34776 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12402 | /* 34779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12403 | /* 34785 */ GIR_RootConstrainSelectedInstOperands, |
| 12404 | /* 34786 */ // GIR_Coverage, 3204, |
| 12405 | /* 34786 */ GIR_EraseRootFromParent_Done, |
| 12406 | /* 34787 */ // Label 922: @34787 |
| 12407 | /* 34787 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 923*/ GIMT_Encode4(34812), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3209 // |
| 12408 | /* 34794 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) |
| 12409 | /* 34794 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8), |
| 12410 | /* 34797 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12411 | /* 34799 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12412 | /* 34801 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12413 | /* 34804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12414 | /* 34810 */ GIR_RootConstrainSelectedInstOperands, |
| 12415 | /* 34811 */ // GIR_Coverage, 3209, |
| 12416 | /* 34811 */ GIR_EraseRootFromParent_Done, |
| 12417 | /* 34812 */ // Label 923: @34812 |
| 12418 | /* 34812 */ GIM_Reject, |
| 12419 | /* 34813 */ // Label 919: @34813 |
| 12420 | /* 34813 */ GIM_Reject, |
| 12421 | /* 34814 */ // Label 907: @34814 |
| 12422 | /* 34814 */ GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(35008), |
| 12423 | /* 34819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12424 | /* 34823 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12425 | /* 34827 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 925*/ GIMT_Encode4(34847), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3130 // |
| 12426 | /* 34834 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2f32] }:$src |
| 12427 | /* 34834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12428 | /* 34837 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12429 | /* 34839 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12430 | /* 34841 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12431 | /* 34846 */ // GIR_Coverage, 3130, |
| 12432 | /* 34846 */ GIR_EraseRootFromParent_Done, |
| 12433 | /* 34847 */ // Label 925: @34847 |
| 12434 | /* 34847 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 926*/ GIMT_Encode4(34867), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3131 // |
| 12435 | /* 34854 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2f32] }:$src |
| 12436 | /* 34854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12437 | /* 34857 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12438 | /* 34859 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12439 | /* 34861 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12440 | /* 34866 */ // GIR_Coverage, 3131, |
| 12441 | /* 34866 */ GIR_EraseRootFromParent_Done, |
| 12442 | /* 34867 */ // Label 926: @34867 |
| 12443 | /* 34867 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 927*/ GIMT_Encode4(34887), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3135 // |
| 12444 | /* 34874 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2i32] }:$src |
| 12445 | /* 34874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12446 | /* 34877 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12447 | /* 34879 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12448 | /* 34881 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12449 | /* 34886 */ // GIR_Coverage, 3135, |
| 12450 | /* 34886 */ GIR_EraseRootFromParent_Done, |
| 12451 | /* 34887 */ // Label 927: @34887 |
| 12452 | /* 34887 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 928*/ GIMT_Encode4(34907), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3136 // |
| 12453 | /* 34894 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2i32] }:$src |
| 12454 | /* 34894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12455 | /* 34897 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12456 | /* 34899 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12457 | /* 34901 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12458 | /* 34906 */ // GIR_Coverage, 3136, |
| 12459 | /* 34906 */ GIR_EraseRootFromParent_Done, |
| 12460 | /* 34907 */ // Label 928: @34907 |
| 12461 | /* 34907 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 929*/ GIMT_Encode4(34932), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3202 // |
| 12462 | /* 34914 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) |
| 12463 | /* 34914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 12464 | /* 34917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12465 | /* 34919 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12466 | /* 34921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12467 | /* 34924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12468 | /* 34930 */ GIR_RootConstrainSelectedInstOperands, |
| 12469 | /* 34931 */ // GIR_Coverage, 3202, |
| 12470 | /* 34931 */ GIR_EraseRootFromParent_Done, |
| 12471 | /* 34932 */ // Label 929: @34932 |
| 12472 | /* 34932 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 930*/ GIMT_Encode4(34957), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3203 // |
| 12473 | /* 34939 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) |
| 12474 | /* 34939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 12475 | /* 34942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12476 | /* 34944 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12477 | /* 34946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12478 | /* 34949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12479 | /* 34955 */ GIR_RootConstrainSelectedInstOperands, |
| 12480 | /* 34956 */ // GIR_Coverage, 3203, |
| 12481 | /* 34956 */ GIR_EraseRootFromParent_Done, |
| 12482 | /* 34957 */ // Label 930: @34957 |
| 12483 | /* 34957 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 931*/ GIMT_Encode4(34982), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3207 // |
| 12484 | /* 34964 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) |
| 12485 | /* 34964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 12486 | /* 34967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12487 | /* 34969 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12488 | /* 34971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12489 | /* 34974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12490 | /* 34980 */ GIR_RootConstrainSelectedInstOperands, |
| 12491 | /* 34981 */ // GIR_Coverage, 3207, |
| 12492 | /* 34981 */ GIR_EraseRootFromParent_Done, |
| 12493 | /* 34982 */ // Label 931: @34982 |
| 12494 | /* 34982 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 932*/ GIMT_Encode4(35007), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3208 // |
| 12495 | /* 34989 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) |
| 12496 | /* 34989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16), |
| 12497 | /* 34992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12498 | /* 34994 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12499 | /* 34996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12500 | /* 34999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12501 | /* 35005 */ GIR_RootConstrainSelectedInstOperands, |
| 12502 | /* 35006 */ // GIR_Coverage, 3208, |
| 12503 | /* 35006 */ GIR_EraseRootFromParent_Done, |
| 12504 | /* 35007 */ // Label 932: @35007 |
| 12505 | /* 35007 */ GIM_Reject, |
| 12506 | /* 35008 */ // Label 924: @35008 |
| 12507 | /* 35008 */ GIM_Reject, |
| 12508 | /* 35009 */ // Label 908: @35009 |
| 12509 | /* 35009 */ GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(35063), |
| 12510 | /* 35014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12511 | /* 35018 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 12512 | /* 35022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 934*/ GIMT_Encode4(35042), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3108 // |
| 12513 | /* 35029 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v2f32] }:$src |
| 12514 | /* 35029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12515 | /* 35032 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12516 | /* 35034 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12517 | /* 35036 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12518 | /* 35041 */ // GIR_Coverage, 3108, |
| 12519 | /* 35041 */ GIR_EraseRootFromParent_Done, |
| 12520 | /* 35042 */ // Label 934: @35042 |
| 12521 | /* 35042 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 935*/ GIMT_Encode4(35062), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3109 // |
| 12522 | /* 35049 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v2i32] }:$src |
| 12523 | /* 35049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12524 | /* 35052 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12525 | /* 35054 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12526 | /* 35056 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID), |
| 12527 | /* 35061 */ // GIR_Coverage, 3109, |
| 12528 | /* 35061 */ GIR_EraseRootFromParent_Done, |
| 12529 | /* 35062 */ // Label 935: @35062 |
| 12530 | /* 35062 */ GIM_Reject, |
| 12531 | /* 35063 */ // Label 933: @35063 |
| 12532 | /* 35063 */ GIM_Reject, |
| 12533 | /* 35064 */ // Label 909: @35064 |
| 12534 | /* 35064 */ GIM_Reject, |
| 12535 | /* 35065 */ // Label 725: @35065 |
| 12536 | /* 35065 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 940*/ GIMT_Encode4(36406), |
| 12537 | /* 35076 */ /*GILLT_v16s8*//*Label 936*/ GIMT_Encode4(35100), GIMT_Encode4(0), |
| 12538 | /* 35084 */ /*GILLT_v8s16*//*Label 937*/ GIMT_Encode4(35351), GIMT_Encode4(0), |
| 12539 | /* 35092 */ /*GILLT_v4s32*//*Label 938*/ GIMT_Encode4(35824), |
| 12540 | /* 35096 */ /*GILLT_v2s64*//*Label 939*/ GIMT_Encode4(35933), |
| 12541 | /* 35100 */ // Label 936: @35100 |
| 12542 | /* 35100 */ GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(35204), |
| 12543 | /* 35105 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12544 | /* 35109 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12545 | /* 35113 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 942*/ GIMT_Encode4(35133), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3168 // |
| 12546 | /* 35120 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12547 | /* 35120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12548 | /* 35123 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12549 | /* 35125 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12550 | /* 35127 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12551 | /* 35132 */ // GIR_Coverage, 3168, |
| 12552 | /* 35132 */ GIR_EraseRootFromParent_Done, |
| 12553 | /* 35133 */ // Label 942: @35133 |
| 12554 | /* 35133 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 943*/ GIMT_Encode4(35153), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3173 // |
| 12555 | /* 35140 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12556 | /* 35140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12557 | /* 35143 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12558 | /* 35145 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12559 | /* 35147 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12560 | /* 35152 */ // GIR_Coverage, 3173, |
| 12561 | /* 35152 */ GIR_EraseRootFromParent_Done, |
| 12562 | /* 35153 */ // Label 943: @35153 |
| 12563 | /* 35153 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 944*/ GIMT_Encode4(35178), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3240 // |
| 12564 | /* 35160 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) |
| 12565 | /* 35160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 12566 | /* 35163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12567 | /* 35165 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12568 | /* 35167 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12569 | /* 35170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12570 | /* 35176 */ GIR_RootConstrainSelectedInstOperands, |
| 12571 | /* 35177 */ // GIR_Coverage, 3240, |
| 12572 | /* 35177 */ GIR_EraseRootFromParent_Done, |
| 12573 | /* 35178 */ // Label 944: @35178 |
| 12574 | /* 35178 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 945*/ GIMT_Encode4(35203), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3245 // |
| 12575 | /* 35185 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) |
| 12576 | /* 35185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8), |
| 12577 | /* 35188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12578 | /* 35190 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12579 | /* 35192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12580 | /* 35195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12581 | /* 35201 */ GIR_RootConstrainSelectedInstOperands, |
| 12582 | /* 35202 */ // GIR_Coverage, 3245, |
| 12583 | /* 35202 */ GIR_EraseRootFromParent_Done, |
| 12584 | /* 35203 */ // Label 945: @35203 |
| 12585 | /* 35203 */ GIM_Reject, |
| 12586 | /* 35204 */ // Label 941: @35204 |
| 12587 | /* 35204 */ GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(35350), |
| 12588 | /* 35209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12589 | /* 35213 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12590 | /* 35217 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 947*/ GIMT_Encode4(35237), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5829 // |
| 12591 | /* 35224 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 12592 | /* 35224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12593 | /* 35227 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12594 | /* 35229 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12595 | /* 35231 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12596 | /* 35236 */ // GIR_Coverage, 5829, |
| 12597 | /* 35236 */ GIR_EraseRootFromParent_Done, |
| 12598 | /* 35237 */ // Label 947: @35237 |
| 12599 | /* 35237 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 948*/ GIMT_Encode4(35257), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5834 // |
| 12600 | /* 35244 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 12601 | /* 35244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12602 | /* 35247 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12603 | /* 35249 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12604 | /* 35251 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12605 | /* 35256 */ // GIR_Coverage, 5834, |
| 12606 | /* 35256 */ GIR_EraseRootFromParent_Done, |
| 12607 | /* 35257 */ // Label 948: @35257 |
| 12608 | /* 35257 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 949*/ GIMT_Encode4(35303), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5865 // |
| 12609 | /* 35264 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) |
| 12610 | /* 35264 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12611 | /* 35267 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12612 | /* 35271 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12613 | /* 35276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 12614 | /* 35279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12615 | /* 35281 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12616 | /* 35283 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12617 | /* 35286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12618 | /* 35292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12619 | /* 35298 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12620 | /* 35301 */ GIR_RootConstrainSelectedInstOperands, |
| 12621 | /* 35302 */ // GIR_Coverage, 5865, |
| 12622 | /* 35302 */ GIR_EraseRootFromParent_Done, |
| 12623 | /* 35303 */ // Label 949: @35303 |
| 12624 | /* 35303 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 950*/ GIMT_Encode4(35349), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5870 // |
| 12625 | /* 35310 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) |
| 12626 | /* 35310 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12627 | /* 35313 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12628 | /* 35317 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12629 | /* 35322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 12630 | /* 35325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12631 | /* 35327 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12632 | /* 35329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12633 | /* 35332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12634 | /* 35338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12635 | /* 35344 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12636 | /* 35347 */ GIR_RootConstrainSelectedInstOperands, |
| 12637 | /* 35348 */ // GIR_Coverage, 5870, |
| 12638 | /* 35348 */ GIR_EraseRootFromParent_Done, |
| 12639 | /* 35349 */ // Label 950: @35349 |
| 12640 | /* 35349 */ GIM_Reject, |
| 12641 | /* 35350 */ // Label 946: @35350 |
| 12642 | /* 35350 */ GIM_Reject, |
| 12643 | /* 35351 */ // Label 937: @35351 |
| 12644 | /* 35351 */ GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(35545), |
| 12645 | /* 35356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12646 | /* 35360 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12647 | /* 35364 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 952*/ GIMT_Encode4(35384), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3166 // |
| 12648 | /* 35371 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12649 | /* 35371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12650 | /* 35374 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12651 | /* 35376 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12652 | /* 35378 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12653 | /* 35383 */ // GIR_Coverage, 3166, |
| 12654 | /* 35383 */ GIR_EraseRootFromParent_Done, |
| 12655 | /* 35384 */ // Label 952: @35384 |
| 12656 | /* 35384 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 953*/ GIMT_Encode4(35404), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3167 // |
| 12657 | /* 35391 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12658 | /* 35391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12659 | /* 35394 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12660 | /* 35396 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12661 | /* 35398 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12662 | /* 35403 */ // GIR_Coverage, 3167, |
| 12663 | /* 35403 */ GIR_EraseRootFromParent_Done, |
| 12664 | /* 35404 */ // Label 953: @35404 |
| 12665 | /* 35404 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 954*/ GIMT_Encode4(35424), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3171 // |
| 12666 | /* 35411 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12667 | /* 35411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12668 | /* 35414 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12669 | /* 35416 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12670 | /* 35418 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12671 | /* 35423 */ // GIR_Coverage, 3171, |
| 12672 | /* 35423 */ GIR_EraseRootFromParent_Done, |
| 12673 | /* 35424 */ // Label 954: @35424 |
| 12674 | /* 35424 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 955*/ GIMT_Encode4(35444), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3172 // |
| 12675 | /* 35431 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12676 | /* 35431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12677 | /* 35434 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12678 | /* 35436 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12679 | /* 35438 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12680 | /* 35443 */ // GIR_Coverage, 3172, |
| 12681 | /* 35443 */ GIR_EraseRootFromParent_Done, |
| 12682 | /* 35444 */ // Label 955: @35444 |
| 12683 | /* 35444 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 956*/ GIMT_Encode4(35469), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3238 // |
| 12684 | /* 35451 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) |
| 12685 | /* 35451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12686 | /* 35454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12687 | /* 35456 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12688 | /* 35458 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12689 | /* 35461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12690 | /* 35467 */ GIR_RootConstrainSelectedInstOperands, |
| 12691 | /* 35468 */ // GIR_Coverage, 3238, |
| 12692 | /* 35468 */ GIR_EraseRootFromParent_Done, |
| 12693 | /* 35469 */ // Label 956: @35469 |
| 12694 | /* 35469 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 957*/ GIMT_Encode4(35494), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3239 // |
| 12695 | /* 35476 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) |
| 12696 | /* 35476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12697 | /* 35479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12698 | /* 35481 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12699 | /* 35483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12700 | /* 35486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12701 | /* 35492 */ GIR_RootConstrainSelectedInstOperands, |
| 12702 | /* 35493 */ // GIR_Coverage, 3239, |
| 12703 | /* 35493 */ GIR_EraseRootFromParent_Done, |
| 12704 | /* 35494 */ // Label 957: @35494 |
| 12705 | /* 35494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 958*/ GIMT_Encode4(35519), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3243 // |
| 12706 | /* 35501 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) |
| 12707 | /* 35501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12708 | /* 35504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12709 | /* 35506 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12710 | /* 35508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12711 | /* 35511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12712 | /* 35517 */ GIR_RootConstrainSelectedInstOperands, |
| 12713 | /* 35518 */ // GIR_Coverage, 3243, |
| 12714 | /* 35518 */ GIR_EraseRootFromParent_Done, |
| 12715 | /* 35519 */ // Label 958: @35519 |
| 12716 | /* 35519 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 959*/ GIMT_Encode4(35544), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3244 // |
| 12717 | /* 35526 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) |
| 12718 | /* 35526 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16), |
| 12719 | /* 35529 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12720 | /* 35531 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12721 | /* 35533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12722 | /* 35536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12723 | /* 35542 */ GIR_RootConstrainSelectedInstOperands, |
| 12724 | /* 35543 */ // GIR_Coverage, 3244, |
| 12725 | /* 35543 */ GIR_EraseRootFromParent_Done, |
| 12726 | /* 35544 */ // Label 959: @35544 |
| 12727 | /* 35544 */ GIM_Reject, |
| 12728 | /* 35545 */ // Label 951: @35545 |
| 12729 | /* 35545 */ GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(35823), |
| 12730 | /* 35550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12731 | /* 35554 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12732 | /* 35558 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 961*/ GIMT_Encode4(35578), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5827 // |
| 12733 | /* 35565 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 12734 | /* 35565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12735 | /* 35568 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12736 | /* 35570 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12737 | /* 35572 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12738 | /* 35577 */ // GIR_Coverage, 5827, |
| 12739 | /* 35577 */ GIR_EraseRootFromParent_Done, |
| 12740 | /* 35578 */ // Label 961: @35578 |
| 12741 | /* 35578 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 962*/ GIMT_Encode4(35598), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5828 // |
| 12742 | /* 35585 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 12743 | /* 35585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12744 | /* 35588 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12745 | /* 35590 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12746 | /* 35592 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12747 | /* 35597 */ // GIR_Coverage, 5828, |
| 12748 | /* 35597 */ GIR_EraseRootFromParent_Done, |
| 12749 | /* 35598 */ // Label 962: @35598 |
| 12750 | /* 35598 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 963*/ GIMT_Encode4(35618), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5832 // |
| 12751 | /* 35605 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 12752 | /* 35605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12753 | /* 35608 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12754 | /* 35610 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12755 | /* 35612 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12756 | /* 35617 */ // GIR_Coverage, 5832, |
| 12757 | /* 35617 */ GIR_EraseRootFromParent_Done, |
| 12758 | /* 35618 */ // Label 963: @35618 |
| 12759 | /* 35618 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 964*/ GIMT_Encode4(35638), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5833 // |
| 12760 | /* 35625 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 12761 | /* 35625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12762 | /* 35628 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12763 | /* 35630 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12764 | /* 35632 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12765 | /* 35637 */ // GIR_Coverage, 5833, |
| 12766 | /* 35637 */ GIR_EraseRootFromParent_Done, |
| 12767 | /* 35638 */ // Label 964: @35638 |
| 12768 | /* 35638 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 965*/ GIMT_Encode4(35684), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5863 // |
| 12769 | /* 35645 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) |
| 12770 | /* 35645 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12771 | /* 35648 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12772 | /* 35652 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12773 | /* 35657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12774 | /* 35660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12775 | /* 35662 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12776 | /* 35664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12777 | /* 35667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12778 | /* 35673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12779 | /* 35679 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12780 | /* 35682 */ GIR_RootConstrainSelectedInstOperands, |
| 12781 | /* 35683 */ // GIR_Coverage, 5863, |
| 12782 | /* 35683 */ GIR_EraseRootFromParent_Done, |
| 12783 | /* 35684 */ // Label 965: @35684 |
| 12784 | /* 35684 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 966*/ GIMT_Encode4(35730), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5864 // |
| 12785 | /* 35691 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) |
| 12786 | /* 35691 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12787 | /* 35694 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12788 | /* 35698 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12789 | /* 35703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12790 | /* 35706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12791 | /* 35708 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12792 | /* 35710 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12793 | /* 35713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12794 | /* 35719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12795 | /* 35725 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12796 | /* 35728 */ GIR_RootConstrainSelectedInstOperands, |
| 12797 | /* 35729 */ // GIR_Coverage, 5864, |
| 12798 | /* 35729 */ GIR_EraseRootFromParent_Done, |
| 12799 | /* 35730 */ // Label 966: @35730 |
| 12800 | /* 35730 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 967*/ GIMT_Encode4(35776), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5868 // |
| 12801 | /* 35737 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) |
| 12802 | /* 35737 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12803 | /* 35740 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12804 | /* 35744 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12805 | /* 35749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12806 | /* 35752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12807 | /* 35754 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12808 | /* 35756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12809 | /* 35759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12810 | /* 35765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12811 | /* 35771 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12812 | /* 35774 */ GIR_RootConstrainSelectedInstOperands, |
| 12813 | /* 35775 */ // GIR_Coverage, 5868, |
| 12814 | /* 35775 */ GIR_EraseRootFromParent_Done, |
| 12815 | /* 35776 */ // Label 967: @35776 |
| 12816 | /* 35776 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 968*/ GIMT_Encode4(35822), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5869 // |
| 12817 | /* 35783 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 12818 | /* 35783 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 12819 | /* 35786 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 12820 | /* 35790 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 12821 | /* 35795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16), |
| 12822 | /* 35798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 12823 | /* 35800 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12824 | /* 35802 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 12825 | /* 35805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12826 | /* 35811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12827 | /* 35817 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 12828 | /* 35820 */ GIR_RootConstrainSelectedInstOperands, |
| 12829 | /* 35821 */ // GIR_Coverage, 5869, |
| 12830 | /* 35821 */ GIR_EraseRootFromParent_Done, |
| 12831 | /* 35822 */ // Label 968: @35822 |
| 12832 | /* 35822 */ GIM_Reject, |
| 12833 | /* 35823 */ // Label 960: @35823 |
| 12834 | /* 35823 */ GIM_Reject, |
| 12835 | /* 35824 */ // Label 938: @35824 |
| 12836 | /* 35824 */ GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(35878), |
| 12837 | /* 35829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12838 | /* 35833 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12839 | /* 35837 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 970*/ GIMT_Encode4(35857), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3114 // |
| 12840 | /* 35844 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12841 | /* 35844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12842 | /* 35847 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12843 | /* 35849 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12844 | /* 35851 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12845 | /* 35856 */ // GIR_Coverage, 3114, |
| 12846 | /* 35856 */ GIR_EraseRootFromParent_Done, |
| 12847 | /* 35857 */ // Label 970: @35857 |
| 12848 | /* 35857 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 971*/ GIMT_Encode4(35877), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3115 // |
| 12849 | /* 35864 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12850 | /* 35864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12851 | /* 35867 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12852 | /* 35869 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12853 | /* 35871 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12854 | /* 35876 */ // GIR_Coverage, 3115, |
| 12855 | /* 35876 */ GIR_EraseRootFromParent_Done, |
| 12856 | /* 35877 */ // Label 971: @35877 |
| 12857 | /* 35877 */ GIM_Reject, |
| 12858 | /* 35878 */ // Label 969: @35878 |
| 12859 | /* 35878 */ GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(35932), |
| 12860 | /* 35883 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12861 | /* 35887 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12862 | /* 35891 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 973*/ GIMT_Encode4(35911), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5811 // |
| 12863 | /* 35898 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 12864 | /* 35898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12865 | /* 35901 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12866 | /* 35903 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12867 | /* 35905 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12868 | /* 35910 */ // GIR_Coverage, 5811, |
| 12869 | /* 35910 */ GIR_EraseRootFromParent_Done, |
| 12870 | /* 35911 */ // Label 973: @35911 |
| 12871 | /* 35911 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 974*/ GIMT_Encode4(35931), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5812 // |
| 12872 | /* 35918 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 12873 | /* 35918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12874 | /* 35921 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12875 | /* 35923 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12876 | /* 35925 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12877 | /* 35930 */ // GIR_Coverage, 5812, |
| 12878 | /* 35930 */ GIR_EraseRootFromParent_Done, |
| 12879 | /* 35931 */ // Label 974: @35931 |
| 12880 | /* 35931 */ GIM_Reject, |
| 12881 | /* 35932 */ // Label 972: @35932 |
| 12882 | /* 35932 */ GIM_Reject, |
| 12883 | /* 35933 */ // Label 939: @35933 |
| 12884 | /* 35933 */ GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(36127), |
| 12885 | /* 35938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12886 | /* 35942 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 12887 | /* 35946 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 976*/ GIMT_Encode4(35966), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3164 // |
| 12888 | /* 35953 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12889 | /* 35953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12890 | /* 35956 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12891 | /* 35958 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12892 | /* 35960 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12893 | /* 35965 */ // GIR_Coverage, 3164, |
| 12894 | /* 35965 */ GIR_EraseRootFromParent_Done, |
| 12895 | /* 35966 */ // Label 976: @35966 |
| 12896 | /* 35966 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 977*/ GIMT_Encode4(35986), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3165 // |
| 12897 | /* 35973 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4f32] }:$src |
| 12898 | /* 35973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12899 | /* 35976 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12900 | /* 35978 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12901 | /* 35980 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12902 | /* 35985 */ // GIR_Coverage, 3165, |
| 12903 | /* 35985 */ GIR_EraseRootFromParent_Done, |
| 12904 | /* 35986 */ // Label 977: @35986 |
| 12905 | /* 35986 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 978*/ GIMT_Encode4(36006), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3169 // |
| 12906 | /* 35993 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12907 | /* 35993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12908 | /* 35996 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12909 | /* 35998 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12910 | /* 36000 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12911 | /* 36005 */ // GIR_Coverage, 3169, |
| 12912 | /* 36005 */ GIR_EraseRootFromParent_Done, |
| 12913 | /* 36006 */ // Label 978: @36006 |
| 12914 | /* 36006 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 979*/ GIMT_Encode4(36026), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3170 // |
| 12915 | /* 36013 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4i32] }:$src |
| 12916 | /* 36013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12917 | /* 36016 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12918 | /* 36018 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12919 | /* 36020 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 12920 | /* 36025 */ // GIR_Coverage, 3170, |
| 12921 | /* 36025 */ GIR_EraseRootFromParent_Done, |
| 12922 | /* 36026 */ // Label 979: @36026 |
| 12923 | /* 36026 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 980*/ GIMT_Encode4(36051), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3236 // |
| 12924 | /* 36033 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) |
| 12925 | /* 36033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 12926 | /* 36036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12927 | /* 36038 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12928 | /* 36040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12929 | /* 36043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12930 | /* 36049 */ GIR_RootConstrainSelectedInstOperands, |
| 12931 | /* 36050 */ // GIR_Coverage, 3236, |
| 12932 | /* 36050 */ GIR_EraseRootFromParent_Done, |
| 12933 | /* 36051 */ // Label 980: @36051 |
| 12934 | /* 36051 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 981*/ GIMT_Encode4(36076), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3237 // |
| 12935 | /* 36058 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) |
| 12936 | /* 36058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 12937 | /* 36061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12938 | /* 36063 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12939 | /* 36065 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12940 | /* 36068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12941 | /* 36074 */ GIR_RootConstrainSelectedInstOperands, |
| 12942 | /* 36075 */ // GIR_Coverage, 3237, |
| 12943 | /* 36075 */ GIR_EraseRootFromParent_Done, |
| 12944 | /* 36076 */ // Label 981: @36076 |
| 12945 | /* 36076 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 982*/ GIMT_Encode4(36101), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3241 // |
| 12946 | /* 36083 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) |
| 12947 | /* 36083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 12948 | /* 36086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12949 | /* 36088 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12950 | /* 36090 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12951 | /* 36093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12952 | /* 36099 */ GIR_RootConstrainSelectedInstOperands, |
| 12953 | /* 36100 */ // GIR_Coverage, 3241, |
| 12954 | /* 36100 */ GIR_EraseRootFromParent_Done, |
| 12955 | /* 36101 */ // Label 982: @36101 |
| 12956 | /* 36101 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 983*/ GIMT_Encode4(36126), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3242 // |
| 12957 | /* 36108 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) |
| 12958 | /* 36108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 12959 | /* 36111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 12960 | /* 36113 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12961 | /* 36115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 12962 | /* 36118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 12963 | /* 36124 */ GIR_RootConstrainSelectedInstOperands, |
| 12964 | /* 36125 */ // GIR_Coverage, 3242, |
| 12965 | /* 36125 */ GIR_EraseRootFromParent_Done, |
| 12966 | /* 36126 */ // Label 983: @36126 |
| 12967 | /* 36126 */ GIM_Reject, |
| 12968 | /* 36127 */ // Label 975: @36127 |
| 12969 | /* 36127 */ GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(36405), |
| 12970 | /* 36132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12971 | /* 36136 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 12972 | /* 36140 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 985*/ GIMT_Encode4(36160), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5825 // |
| 12973 | /* 36147 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 12974 | /* 36147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12975 | /* 36150 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12976 | /* 36152 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12977 | /* 36154 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12978 | /* 36159 */ // GIR_Coverage, 5825, |
| 12979 | /* 36159 */ GIR_EraseRootFromParent_Done, |
| 12980 | /* 36160 */ // Label 985: @36160 |
| 12981 | /* 36160 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 986*/ GIMT_Encode4(36180), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5826 // |
| 12982 | /* 36167 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4f32] }:$src |
| 12983 | /* 36167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12984 | /* 36170 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12985 | /* 36172 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12986 | /* 36174 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12987 | /* 36179 */ // GIR_Coverage, 5826, |
| 12988 | /* 36179 */ GIR_EraseRootFromParent_Done, |
| 12989 | /* 36180 */ // Label 986: @36180 |
| 12990 | /* 36180 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 987*/ GIMT_Encode4(36200), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5830 // |
| 12991 | /* 36187 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 12992 | /* 36187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12993 | /* 36190 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12994 | /* 36192 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 12995 | /* 36194 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 12996 | /* 36199 */ // GIR_Coverage, 5830, |
| 12997 | /* 36199 */ GIR_EraseRootFromParent_Done, |
| 12998 | /* 36200 */ // Label 987: @36200 |
| 12999 | /* 36200 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 988*/ GIMT_Encode4(36220), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5831 // |
| 13000 | /* 36207 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4i32] }:$src |
| 13001 | /* 36207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13002 | /* 36210 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13003 | /* 36212 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13004 | /* 36214 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13005 | /* 36219 */ // GIR_Coverage, 5831, |
| 13006 | /* 36219 */ GIR_EraseRootFromParent_Done, |
| 13007 | /* 36220 */ // Label 988: @36220 |
| 13008 | /* 36220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 989*/ GIMT_Encode4(36266), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5861 // |
| 13009 | /* 36227 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) |
| 13010 | /* 36227 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13011 | /* 36230 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13012 | /* 36234 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13013 | /* 36239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13014 | /* 36242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13015 | /* 36244 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13016 | /* 36246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13017 | /* 36249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13018 | /* 36255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13019 | /* 36261 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13020 | /* 36264 */ GIR_RootConstrainSelectedInstOperands, |
| 13021 | /* 36265 */ // GIR_Coverage, 5861, |
| 13022 | /* 36265 */ GIR_EraseRootFromParent_Done, |
| 13023 | /* 36266 */ // Label 989: @36266 |
| 13024 | /* 36266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 990*/ GIMT_Encode4(36312), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5862 // |
| 13025 | /* 36273 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) |
| 13026 | /* 36273 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13027 | /* 36276 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13028 | /* 36280 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13029 | /* 36285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13030 | /* 36288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13031 | /* 36290 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13032 | /* 36292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13033 | /* 36295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13034 | /* 36301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13035 | /* 36307 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13036 | /* 36310 */ GIR_RootConstrainSelectedInstOperands, |
| 13037 | /* 36311 */ // GIR_Coverage, 5862, |
| 13038 | /* 36311 */ GIR_EraseRootFromParent_Done, |
| 13039 | /* 36312 */ // Label 990: @36312 |
| 13040 | /* 36312 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 991*/ GIMT_Encode4(36358), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5866 // |
| 13041 | /* 36319 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) |
| 13042 | /* 36319 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13043 | /* 36322 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13044 | /* 36326 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13045 | /* 36331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13046 | /* 36334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13047 | /* 36336 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13048 | /* 36338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13049 | /* 36341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13050 | /* 36347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13051 | /* 36353 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13052 | /* 36356 */ GIR_RootConstrainSelectedInstOperands, |
| 13053 | /* 36357 */ // GIR_Coverage, 5866, |
| 13054 | /* 36357 */ GIR_EraseRootFromParent_Done, |
| 13055 | /* 36358 */ // Label 991: @36358 |
| 13056 | /* 36358 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 992*/ GIMT_Encode4(36404), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5867 // |
| 13057 | /* 36365 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) |
| 13058 | /* 36365 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13059 | /* 36368 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13060 | /* 36372 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13061 | /* 36377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13062 | /* 36380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13063 | /* 36382 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13064 | /* 36384 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13065 | /* 36387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13066 | /* 36393 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13067 | /* 36399 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13068 | /* 36402 */ GIR_RootConstrainSelectedInstOperands, |
| 13069 | /* 36403 */ // GIR_Coverage, 5867, |
| 13070 | /* 36403 */ GIR_EraseRootFromParent_Done, |
| 13071 | /* 36404 */ // Label 992: @36404 |
| 13072 | /* 36404 */ GIM_Reject, |
| 13073 | /* 36405 */ // Label 984: @36405 |
| 13074 | /* 36405 */ GIM_Reject, |
| 13075 | /* 36406 */ // Label 940: @36406 |
| 13076 | /* 36406 */ GIM_Reject, |
| 13077 | /* 36407 */ // Label 726: @36407 |
| 13078 | /* 36407 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 997*/ GIMT_Encode4(37748), |
| 13079 | /* 36418 */ /*GILLT_v16s8*//*Label 993*/ GIMT_Encode4(36442), GIMT_Encode4(0), |
| 13080 | /* 36426 */ /*GILLT_v8s16*//*Label 994*/ GIMT_Encode4(36693), GIMT_Encode4(0), |
| 13081 | /* 36434 */ /*GILLT_v4s32*//*Label 995*/ GIMT_Encode4(37166), |
| 13082 | /* 36438 */ /*GILLT_v2s64*//*Label 996*/ GIMT_Encode4(37639), |
| 13083 | /* 36442 */ // Label 993: @36442 |
| 13084 | /* 36442 */ GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(36546), |
| 13085 | /* 36447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13086 | /* 36451 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13087 | /* 36455 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 999*/ GIMT_Encode4(36475), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3158 // |
| 13088 | /* 36462 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2f64] }:$src |
| 13089 | /* 36462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13090 | /* 36465 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13091 | /* 36467 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13092 | /* 36469 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13093 | /* 36474 */ // GIR_Coverage, 3158, |
| 13094 | /* 36474 */ GIR_EraseRootFromParent_Done, |
| 13095 | /* 36475 */ // Label 999: @36475 |
| 13096 | /* 36475 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1000*/ GIMT_Encode4(36495), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3163 // |
| 13097 | /* 36482 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2i64] }:$src |
| 13098 | /* 36482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13099 | /* 36485 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13100 | /* 36487 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13101 | /* 36489 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13102 | /* 36494 */ // GIR_Coverage, 3163, |
| 13103 | /* 36494 */ GIR_EraseRootFromParent_Done, |
| 13104 | /* 36495 */ // Label 1000: @36495 |
| 13105 | /* 36495 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1001*/ GIMT_Encode4(36520), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3230 // |
| 13106 | /* 36502 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) |
| 13107 | /* 36502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 13108 | /* 36505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13109 | /* 36507 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13110 | /* 36509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13111 | /* 36512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13112 | /* 36518 */ GIR_RootConstrainSelectedInstOperands, |
| 13113 | /* 36519 */ // GIR_Coverage, 3230, |
| 13114 | /* 36519 */ GIR_EraseRootFromParent_Done, |
| 13115 | /* 36520 */ // Label 1001: @36520 |
| 13116 | /* 36520 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1002*/ GIMT_Encode4(36545), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3235 // |
| 13117 | /* 36527 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) |
| 13118 | /* 36527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8), |
| 13119 | /* 36530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13120 | /* 36532 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13121 | /* 36534 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13122 | /* 36537 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13123 | /* 36543 */ GIR_RootConstrainSelectedInstOperands, |
| 13124 | /* 36544 */ // GIR_Coverage, 3235, |
| 13125 | /* 36544 */ GIR_EraseRootFromParent_Done, |
| 13126 | /* 36545 */ // Label 1002: @36545 |
| 13127 | /* 36545 */ GIM_Reject, |
| 13128 | /* 36546 */ // Label 998: @36546 |
| 13129 | /* 36546 */ GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(36692), |
| 13130 | /* 36551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13131 | /* 36555 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13132 | /* 36559 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1004*/ GIMT_Encode4(36579), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5819 // |
| 13133 | /* 36566 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 13134 | /* 36566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13135 | /* 36569 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13136 | /* 36571 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13137 | /* 36573 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13138 | /* 36578 */ // GIR_Coverage, 5819, |
| 13139 | /* 36578 */ GIR_EraseRootFromParent_Done, |
| 13140 | /* 36579 */ // Label 1004: @36579 |
| 13141 | /* 36579 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1005*/ GIMT_Encode4(36599), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5824 // |
| 13142 | /* 36586 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 13143 | /* 36586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13144 | /* 36589 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13145 | /* 36591 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13146 | /* 36593 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13147 | /* 36598 */ // GIR_Coverage, 5824, |
| 13148 | /* 36598 */ GIR_EraseRootFromParent_Done, |
| 13149 | /* 36599 */ // Label 1005: @36599 |
| 13150 | /* 36599 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1006*/ GIMT_Encode4(36645), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5855 // |
| 13151 | /* 36606 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) |
| 13152 | /* 36606 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13153 | /* 36609 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13154 | /* 36613 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13155 | /* 36618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 13156 | /* 36621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13157 | /* 36623 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13158 | /* 36625 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13159 | /* 36628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13160 | /* 36634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13161 | /* 36640 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13162 | /* 36643 */ GIR_RootConstrainSelectedInstOperands, |
| 13163 | /* 36644 */ // GIR_Coverage, 5855, |
| 13164 | /* 36644 */ GIR_EraseRootFromParent_Done, |
| 13165 | /* 36645 */ // Label 1006: @36645 |
| 13166 | /* 36645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1007*/ GIMT_Encode4(36691), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5860 // |
| 13167 | /* 36652 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) |
| 13168 | /* 36652 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13169 | /* 36655 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13170 | /* 36659 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13171 | /* 36664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8), |
| 13172 | /* 36667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13173 | /* 36669 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13174 | /* 36671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13175 | /* 36674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13176 | /* 36680 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13177 | /* 36686 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13178 | /* 36689 */ GIR_RootConstrainSelectedInstOperands, |
| 13179 | /* 36690 */ // GIR_Coverage, 5860, |
| 13180 | /* 36690 */ GIR_EraseRootFromParent_Done, |
| 13181 | /* 36691 */ // Label 1007: @36691 |
| 13182 | /* 36691 */ GIM_Reject, |
| 13183 | /* 36692 */ // Label 1003: @36692 |
| 13184 | /* 36692 */ GIM_Reject, |
| 13185 | /* 36693 */ // Label 994: @36693 |
| 13186 | /* 36693 */ GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(36887), |
| 13187 | /* 36698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13188 | /* 36702 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13189 | /* 36706 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1009*/ GIMT_Encode4(36726), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3156 // |
| 13190 | /* 36713 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2f64] }:$src |
| 13191 | /* 36713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13192 | /* 36716 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13193 | /* 36718 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13194 | /* 36720 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13195 | /* 36725 */ // GIR_Coverage, 3156, |
| 13196 | /* 36725 */ GIR_EraseRootFromParent_Done, |
| 13197 | /* 36726 */ // Label 1009: @36726 |
| 13198 | /* 36726 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1010*/ GIMT_Encode4(36746), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3157 // |
| 13199 | /* 36733 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2f64] }:$src |
| 13200 | /* 36733 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13201 | /* 36736 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13202 | /* 36738 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13203 | /* 36740 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13204 | /* 36745 */ // GIR_Coverage, 3157, |
| 13205 | /* 36745 */ GIR_EraseRootFromParent_Done, |
| 13206 | /* 36746 */ // Label 1010: @36746 |
| 13207 | /* 36746 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1011*/ GIMT_Encode4(36766), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3161 // |
| 13208 | /* 36753 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2i64] }:$src |
| 13209 | /* 36753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13210 | /* 36756 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13211 | /* 36758 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13212 | /* 36760 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13213 | /* 36765 */ // GIR_Coverage, 3161, |
| 13214 | /* 36765 */ GIR_EraseRootFromParent_Done, |
| 13215 | /* 36766 */ // Label 1011: @36766 |
| 13216 | /* 36766 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1012*/ GIMT_Encode4(36786), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3162 // |
| 13217 | /* 36773 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2i64] }:$src |
| 13218 | /* 36773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13219 | /* 36776 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13220 | /* 36778 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13221 | /* 36780 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13222 | /* 36785 */ // GIR_Coverage, 3162, |
| 13223 | /* 36785 */ GIR_EraseRootFromParent_Done, |
| 13224 | /* 36786 */ // Label 1012: @36786 |
| 13225 | /* 36786 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1013*/ GIMT_Encode4(36811), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3228 // |
| 13226 | /* 36793 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) |
| 13227 | /* 36793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 13228 | /* 36796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13229 | /* 36798 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13230 | /* 36800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13231 | /* 36803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13232 | /* 36809 */ GIR_RootConstrainSelectedInstOperands, |
| 13233 | /* 36810 */ // GIR_Coverage, 3228, |
| 13234 | /* 36810 */ GIR_EraseRootFromParent_Done, |
| 13235 | /* 36811 */ // Label 1013: @36811 |
| 13236 | /* 36811 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1014*/ GIMT_Encode4(36836), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3229 // |
| 13237 | /* 36818 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) |
| 13238 | /* 36818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 13239 | /* 36821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13240 | /* 36823 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13241 | /* 36825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13242 | /* 36828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13243 | /* 36834 */ GIR_RootConstrainSelectedInstOperands, |
| 13244 | /* 36835 */ // GIR_Coverage, 3229, |
| 13245 | /* 36835 */ GIR_EraseRootFromParent_Done, |
| 13246 | /* 36836 */ // Label 1014: @36836 |
| 13247 | /* 36836 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1015*/ GIMT_Encode4(36861), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3233 // |
| 13248 | /* 36843 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) |
| 13249 | /* 36843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 13250 | /* 36846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13251 | /* 36848 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13252 | /* 36850 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13253 | /* 36853 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13254 | /* 36859 */ GIR_RootConstrainSelectedInstOperands, |
| 13255 | /* 36860 */ // GIR_Coverage, 3233, |
| 13256 | /* 36860 */ GIR_EraseRootFromParent_Done, |
| 13257 | /* 36861 */ // Label 1015: @36861 |
| 13258 | /* 36861 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1016*/ GIMT_Encode4(36886), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3234 // |
| 13259 | /* 36868 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) |
| 13260 | /* 36868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16), |
| 13261 | /* 36871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13262 | /* 36873 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13263 | /* 36875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13264 | /* 36878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13265 | /* 36884 */ GIR_RootConstrainSelectedInstOperands, |
| 13266 | /* 36885 */ // GIR_Coverage, 3234, |
| 13267 | /* 36885 */ GIR_EraseRootFromParent_Done, |
| 13268 | /* 36886 */ // Label 1016: @36886 |
| 13269 | /* 36886 */ GIM_Reject, |
| 13270 | /* 36887 */ // Label 1008: @36887 |
| 13271 | /* 36887 */ GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(37165), |
| 13272 | /* 36892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13273 | /* 36896 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13274 | /* 36900 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1018*/ GIMT_Encode4(36920), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5817 // |
| 13275 | /* 36907 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 13276 | /* 36907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13277 | /* 36910 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13278 | /* 36912 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13279 | /* 36914 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13280 | /* 36919 */ // GIR_Coverage, 5817, |
| 13281 | /* 36919 */ GIR_EraseRootFromParent_Done, |
| 13282 | /* 36920 */ // Label 1018: @36920 |
| 13283 | /* 36920 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1019*/ GIMT_Encode4(36940), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5818 // |
| 13284 | /* 36927 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 13285 | /* 36927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13286 | /* 36930 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13287 | /* 36932 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13288 | /* 36934 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13289 | /* 36939 */ // GIR_Coverage, 5818, |
| 13290 | /* 36939 */ GIR_EraseRootFromParent_Done, |
| 13291 | /* 36940 */ // Label 1019: @36940 |
| 13292 | /* 36940 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1020*/ GIMT_Encode4(36960), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5822 // |
| 13293 | /* 36947 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 13294 | /* 36947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13295 | /* 36950 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13296 | /* 36952 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13297 | /* 36954 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13298 | /* 36959 */ // GIR_Coverage, 5822, |
| 13299 | /* 36959 */ GIR_EraseRootFromParent_Done, |
| 13300 | /* 36960 */ // Label 1020: @36960 |
| 13301 | /* 36960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1021*/ GIMT_Encode4(36980), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5823 // |
| 13302 | /* 36967 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 13303 | /* 36967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13304 | /* 36970 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13305 | /* 36972 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13306 | /* 36974 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13307 | /* 36979 */ // GIR_Coverage, 5823, |
| 13308 | /* 36979 */ GIR_EraseRootFromParent_Done, |
| 13309 | /* 36980 */ // Label 1021: @36980 |
| 13310 | /* 36980 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1022*/ GIMT_Encode4(37026), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5853 // |
| 13311 | /* 36987 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) |
| 13312 | /* 36987 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13313 | /* 36990 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13314 | /* 36994 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13315 | /* 36999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 13316 | /* 37002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13317 | /* 37004 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13318 | /* 37006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13319 | /* 37009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13320 | /* 37015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13321 | /* 37021 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13322 | /* 37024 */ GIR_RootConstrainSelectedInstOperands, |
| 13323 | /* 37025 */ // GIR_Coverage, 5853, |
| 13324 | /* 37025 */ GIR_EraseRootFromParent_Done, |
| 13325 | /* 37026 */ // Label 1022: @37026 |
| 13326 | /* 37026 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1023*/ GIMT_Encode4(37072), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5854 // |
| 13327 | /* 37033 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) |
| 13328 | /* 37033 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13329 | /* 37036 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13330 | /* 37040 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13331 | /* 37045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 13332 | /* 37048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13333 | /* 37050 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13334 | /* 37052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13335 | /* 37055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13336 | /* 37061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13337 | /* 37067 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13338 | /* 37070 */ GIR_RootConstrainSelectedInstOperands, |
| 13339 | /* 37071 */ // GIR_Coverage, 5854, |
| 13340 | /* 37071 */ GIR_EraseRootFromParent_Done, |
| 13341 | /* 37072 */ // Label 1023: @37072 |
| 13342 | /* 37072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1024*/ GIMT_Encode4(37118), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5858 // |
| 13343 | /* 37079 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) |
| 13344 | /* 37079 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13345 | /* 37082 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13346 | /* 37086 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13347 | /* 37091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 13348 | /* 37094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13349 | /* 37096 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13350 | /* 37098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13351 | /* 37101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13352 | /* 37107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13353 | /* 37113 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13354 | /* 37116 */ GIR_RootConstrainSelectedInstOperands, |
| 13355 | /* 37117 */ // GIR_Coverage, 5858, |
| 13356 | /* 37117 */ GIR_EraseRootFromParent_Done, |
| 13357 | /* 37118 */ // Label 1024: @37118 |
| 13358 | /* 37118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1025*/ GIMT_Encode4(37164), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5859 // |
| 13359 | /* 37125 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) |
| 13360 | /* 37125 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13361 | /* 37128 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13362 | /* 37132 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13363 | /* 37137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16), |
| 13364 | /* 37140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13365 | /* 37142 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13366 | /* 37144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13367 | /* 37147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13368 | /* 37153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13369 | /* 37159 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13370 | /* 37162 */ GIR_RootConstrainSelectedInstOperands, |
| 13371 | /* 37163 */ // GIR_Coverage, 5859, |
| 13372 | /* 37163 */ GIR_EraseRootFromParent_Done, |
| 13373 | /* 37164 */ // Label 1025: @37164 |
| 13374 | /* 37164 */ GIM_Reject, |
| 13375 | /* 37165 */ // Label 1017: @37165 |
| 13376 | /* 37165 */ GIM_Reject, |
| 13377 | /* 37166 */ // Label 995: @37166 |
| 13378 | /* 37166 */ GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(37360), |
| 13379 | /* 37171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13380 | /* 37175 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13381 | /* 37179 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1027*/ GIMT_Encode4(37199), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3154 // |
| 13382 | /* 37186 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2f64] }:$src |
| 13383 | /* 37186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13384 | /* 37189 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13385 | /* 37191 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13386 | /* 37193 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13387 | /* 37198 */ // GIR_Coverage, 3154, |
| 13388 | /* 37198 */ GIR_EraseRootFromParent_Done, |
| 13389 | /* 37199 */ // Label 1027: @37199 |
| 13390 | /* 37199 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1028*/ GIMT_Encode4(37219), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3155 // |
| 13391 | /* 37206 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2f64] }:$src |
| 13392 | /* 37206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13393 | /* 37209 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13394 | /* 37211 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13395 | /* 37213 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13396 | /* 37218 */ // GIR_Coverage, 3155, |
| 13397 | /* 37218 */ GIR_EraseRootFromParent_Done, |
| 13398 | /* 37219 */ // Label 1028: @37219 |
| 13399 | /* 37219 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1029*/ GIMT_Encode4(37239), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3159 // |
| 13400 | /* 37226 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2i64] }:$src |
| 13401 | /* 37226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13402 | /* 37229 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13403 | /* 37231 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13404 | /* 37233 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13405 | /* 37238 */ // GIR_Coverage, 3159, |
| 13406 | /* 37238 */ GIR_EraseRootFromParent_Done, |
| 13407 | /* 37239 */ // Label 1029: @37239 |
| 13408 | /* 37239 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1030*/ GIMT_Encode4(37259), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3160 // |
| 13409 | /* 37246 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2i64] }:$src |
| 13410 | /* 37246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13411 | /* 37249 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13412 | /* 37251 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13413 | /* 37253 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13414 | /* 37258 */ // GIR_Coverage, 3160, |
| 13415 | /* 37258 */ GIR_EraseRootFromParent_Done, |
| 13416 | /* 37259 */ // Label 1030: @37259 |
| 13417 | /* 37259 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1031*/ GIMT_Encode4(37284), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3226 // |
| 13418 | /* 37266 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) |
| 13419 | /* 37266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 13420 | /* 37269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13421 | /* 37271 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13422 | /* 37273 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13423 | /* 37276 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13424 | /* 37282 */ GIR_RootConstrainSelectedInstOperands, |
| 13425 | /* 37283 */ // GIR_Coverage, 3226, |
| 13426 | /* 37283 */ GIR_EraseRootFromParent_Done, |
| 13427 | /* 37284 */ // Label 1031: @37284 |
| 13428 | /* 37284 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1032*/ GIMT_Encode4(37309), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3227 // |
| 13429 | /* 37291 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) |
| 13430 | /* 37291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 13431 | /* 37294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13432 | /* 37296 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13433 | /* 37298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13434 | /* 37301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13435 | /* 37307 */ GIR_RootConstrainSelectedInstOperands, |
| 13436 | /* 37308 */ // GIR_Coverage, 3227, |
| 13437 | /* 37308 */ GIR_EraseRootFromParent_Done, |
| 13438 | /* 37309 */ // Label 1032: @37309 |
| 13439 | /* 37309 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1033*/ GIMT_Encode4(37334), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3231 // |
| 13440 | /* 37316 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) |
| 13441 | /* 37316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 13442 | /* 37319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13443 | /* 37321 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13444 | /* 37323 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13445 | /* 37326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13446 | /* 37332 */ GIR_RootConstrainSelectedInstOperands, |
| 13447 | /* 37333 */ // GIR_Coverage, 3231, |
| 13448 | /* 37333 */ GIR_EraseRootFromParent_Done, |
| 13449 | /* 37334 */ // Label 1033: @37334 |
| 13450 | /* 37334 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1034*/ GIMT_Encode4(37359), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3232 // |
| 13451 | /* 37341 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) |
| 13452 | /* 37341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32), |
| 13453 | /* 37344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 13454 | /* 37346 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13455 | /* 37348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13456 | /* 37351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13457 | /* 37357 */ GIR_RootConstrainSelectedInstOperands, |
| 13458 | /* 37358 */ // GIR_Coverage, 3232, |
| 13459 | /* 37358 */ GIR_EraseRootFromParent_Done, |
| 13460 | /* 37359 */ // Label 1034: @37359 |
| 13461 | /* 37359 */ GIM_Reject, |
| 13462 | /* 37360 */ // Label 1026: @37360 |
| 13463 | /* 37360 */ GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(37638), |
| 13464 | /* 37365 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13465 | /* 37369 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13466 | /* 37373 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1036*/ GIMT_Encode4(37393), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5815 // |
| 13467 | /* 37380 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 13468 | /* 37380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13469 | /* 37383 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13470 | /* 37385 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13471 | /* 37387 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13472 | /* 37392 */ // GIR_Coverage, 5815, |
| 13473 | /* 37392 */ GIR_EraseRootFromParent_Done, |
| 13474 | /* 37393 */ // Label 1036: @37393 |
| 13475 | /* 37393 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1037*/ GIMT_Encode4(37413), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5816 // |
| 13476 | /* 37400 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 13477 | /* 37400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13478 | /* 37403 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13479 | /* 37405 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13480 | /* 37407 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13481 | /* 37412 */ // GIR_Coverage, 5816, |
| 13482 | /* 37412 */ GIR_EraseRootFromParent_Done, |
| 13483 | /* 37413 */ // Label 1037: @37413 |
| 13484 | /* 37413 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1038*/ GIMT_Encode4(37433), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5820 // |
| 13485 | /* 37420 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 13486 | /* 37420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13487 | /* 37423 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13488 | /* 37425 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13489 | /* 37427 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13490 | /* 37432 */ // GIR_Coverage, 5820, |
| 13491 | /* 37432 */ GIR_EraseRootFromParent_Done, |
| 13492 | /* 37433 */ // Label 1038: @37433 |
| 13493 | /* 37433 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1039*/ GIMT_Encode4(37453), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5821 // |
| 13494 | /* 37440 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 13495 | /* 37440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13496 | /* 37443 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13497 | /* 37445 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13498 | /* 37447 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13499 | /* 37452 */ // GIR_Coverage, 5821, |
| 13500 | /* 37452 */ GIR_EraseRootFromParent_Done, |
| 13501 | /* 37453 */ // Label 1039: @37453 |
| 13502 | /* 37453 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1040*/ GIMT_Encode4(37499), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5851 // |
| 13503 | /* 37460 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) |
| 13504 | /* 37460 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13505 | /* 37463 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13506 | /* 37467 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13507 | /* 37472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13508 | /* 37475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13509 | /* 37477 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13510 | /* 37479 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13511 | /* 37482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13512 | /* 37488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13513 | /* 37494 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13514 | /* 37497 */ GIR_RootConstrainSelectedInstOperands, |
| 13515 | /* 37498 */ // GIR_Coverage, 5851, |
| 13516 | /* 37498 */ GIR_EraseRootFromParent_Done, |
| 13517 | /* 37499 */ // Label 1040: @37499 |
| 13518 | /* 37499 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1041*/ GIMT_Encode4(37545), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5852 // |
| 13519 | /* 37506 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) |
| 13520 | /* 37506 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13521 | /* 37509 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13522 | /* 37513 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13523 | /* 37518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13524 | /* 37521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13525 | /* 37523 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13526 | /* 37525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13527 | /* 37528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13528 | /* 37534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13529 | /* 37540 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13530 | /* 37543 */ GIR_RootConstrainSelectedInstOperands, |
| 13531 | /* 37544 */ // GIR_Coverage, 5852, |
| 13532 | /* 37544 */ GIR_EraseRootFromParent_Done, |
| 13533 | /* 37545 */ // Label 1041: @37545 |
| 13534 | /* 37545 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1042*/ GIMT_Encode4(37591), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5856 // |
| 13535 | /* 37552 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) |
| 13536 | /* 37552 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13537 | /* 37555 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13538 | /* 37559 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13539 | /* 37564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13540 | /* 37567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13541 | /* 37569 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13542 | /* 37571 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13543 | /* 37574 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13544 | /* 37580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13545 | /* 37586 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13546 | /* 37589 */ GIR_RootConstrainSelectedInstOperands, |
| 13547 | /* 37590 */ // GIR_Coverage, 5856, |
| 13548 | /* 37590 */ GIR_EraseRootFromParent_Done, |
| 13549 | /* 37591 */ // Label 1042: @37591 |
| 13550 | /* 37591 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1043*/ GIMT_Encode4(37637), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5857 // |
| 13551 | /* 37598 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) |
| 13552 | /* 37598 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13553 | /* 37601 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13554 | /* 37605 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13555 | /* 37610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32), |
| 13556 | /* 37613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13557 | /* 37615 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13558 | /* 37617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13559 | /* 37620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13560 | /* 37626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13561 | /* 37632 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13562 | /* 37635 */ GIR_RootConstrainSelectedInstOperands, |
| 13563 | /* 37636 */ // GIR_Coverage, 5857, |
| 13564 | /* 37636 */ GIR_EraseRootFromParent_Done, |
| 13565 | /* 37637 */ // Label 1043: @37637 |
| 13566 | /* 37637 */ GIM_Reject, |
| 13567 | /* 37638 */ // Label 1035: @37638 |
| 13568 | /* 37638 */ GIM_Reject, |
| 13569 | /* 37639 */ // Label 996: @37639 |
| 13570 | /* 37639 */ GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(37693), |
| 13571 | /* 37644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13572 | /* 37648 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13573 | /* 37652 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1045*/ GIMT_Encode4(37672), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3112 // |
| 13574 | /* 37659 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v2f64] }:$src |
| 13575 | /* 37659 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13576 | /* 37662 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13577 | /* 37664 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13578 | /* 37666 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13579 | /* 37671 */ // GIR_Coverage, 3112, |
| 13580 | /* 37671 */ GIR_EraseRootFromParent_Done, |
| 13581 | /* 37672 */ // Label 1045: @37672 |
| 13582 | /* 37672 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1046*/ GIMT_Encode4(37692), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3113 // |
| 13583 | /* 37679 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v2i64] }:$src |
| 13584 | /* 37679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13585 | /* 37682 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13586 | /* 37684 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13587 | /* 37686 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID), |
| 13588 | /* 37691 */ // GIR_Coverage, 3113, |
| 13589 | /* 37691 */ GIR_EraseRootFromParent_Done, |
| 13590 | /* 37692 */ // Label 1046: @37692 |
| 13591 | /* 37692 */ GIM_Reject, |
| 13592 | /* 37693 */ // Label 1044: @37693 |
| 13593 | /* 37693 */ GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(37747), |
| 13594 | /* 37698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13595 | /* 37702 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13596 | /* 37706 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1048*/ GIMT_Encode4(37726), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5809 // |
| 13597 | /* 37713 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v2f64] }:$src |
| 13598 | /* 37713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13599 | /* 37716 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13600 | /* 37718 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13601 | /* 37720 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13602 | /* 37725 */ // GIR_Coverage, 5809, |
| 13603 | /* 37725 */ GIR_EraseRootFromParent_Done, |
| 13604 | /* 37726 */ // Label 1048: @37726 |
| 13605 | /* 37726 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1049*/ GIMT_Encode4(37746), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5810 // |
| 13606 | /* 37733 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v2i64] }:$src |
| 13607 | /* 37733 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13608 | /* 37736 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13609 | /* 37738 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 13610 | /* 37740 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID), |
| 13611 | /* 37745 */ // GIR_Coverage, 5810, |
| 13612 | /* 37745 */ GIR_EraseRootFromParent_Done, |
| 13613 | /* 37746 */ // Label 1049: @37746 |
| 13614 | /* 37746 */ GIM_Reject, |
| 13615 | /* 37747 */ // Label 1047: @37747 |
| 13616 | /* 37747 */ GIM_Reject, |
| 13617 | /* 37748 */ // Label 997: @37748 |
| 13618 | /* 37748 */ GIM_Reject, |
| 13619 | /* 37749 */ // Label 727: @37749 |
| 13620 | /* 37749 */ GIM_Reject, |
| 13621 | /* 37750 */ // Label 16: @37750 |
| 13622 | /* 37750 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 1057*/ GIMT_Encode4(38148), |
| 13623 | /* 37761 */ /*GILLT_s16*//*Label 1050*/ GIMT_Encode4(37813), |
| 13624 | /* 37765 */ /*GILLT_s32*//*Label 1051*/ GIMT_Encode4(37850), |
| 13625 | /* 37769 */ /*GILLT_s64*//*Label 1052*/ GIMT_Encode4(37887), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 13626 | /* 37797 */ /*GILLT_v4s16*//*Label 1053*/ GIMT_Encode4(37924), |
| 13627 | /* 37801 */ /*GILLT_v8s16*//*Label 1054*/ GIMT_Encode4(37950), |
| 13628 | /* 37805 */ /*GILLT_v2s32*//*Label 1055*/ GIMT_Encode4(38036), |
| 13629 | /* 37809 */ /*GILLT_v4s32*//*Label 1056*/ GIMT_Encode4(38062), |
| 13630 | /* 37813 */ // Label 1050: @37813 |
| 13631 | /* 37813 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1058*/ GIMT_Encode4(37849), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 693 // |
| 13632 | /* 37820 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 13633 | /* 37823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13634 | /* 37827 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13635 | /* 37831 */ // (ftrunc:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTZH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 13636 | /* 37831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZH), |
| 13637 | /* 37834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 13638 | /* 37836 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 13639 | /* 37838 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13640 | /* 37841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13641 | /* 37847 */ GIR_RootConstrainSelectedInstOperands, |
| 13642 | /* 37848 */ // GIR_Coverage, 693, |
| 13643 | /* 37848 */ GIR_EraseRootFromParent_Done, |
| 13644 | /* 37849 */ // Label 1058: @37849 |
| 13645 | /* 37849 */ GIM_Reject, |
| 13646 | /* 37850 */ // Label 1051: @37850 |
| 13647 | /* 37850 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1059*/ GIMT_Encode4(37886), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 695 // |
| 13648 | /* 37857 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 13649 | /* 37860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13650 | /* 37864 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13651 | /* 37868 */ // (ftrunc:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTZS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 13652 | /* 37868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZS), |
| 13653 | /* 37871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 13654 | /* 37873 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 13655 | /* 37875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13656 | /* 37878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13657 | /* 37884 */ GIR_RootConstrainSelectedInstOperands, |
| 13658 | /* 37885 */ // GIR_Coverage, 695, |
| 13659 | /* 37885 */ GIR_EraseRootFromParent_Done, |
| 13660 | /* 37886 */ // Label 1059: @37886 |
| 13661 | /* 37886 */ GIM_Reject, |
| 13662 | /* 37887 */ // Label 1052: @37887 |
| 13663 | /* 37887 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1060*/ GIMT_Encode4(37923), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 697 // |
| 13664 | /* 37894 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 13665 | /* 37897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13666 | /* 37901 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13667 | /* 37905 */ // (ftrunc:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTZD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 13668 | /* 37905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZD), |
| 13669 | /* 37908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 13670 | /* 37910 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 13671 | /* 37912 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 13672 | /* 37915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13673 | /* 37921 */ GIR_RootConstrainSelectedInstOperands, |
| 13674 | /* 37922 */ // GIR_Coverage, 697, |
| 13675 | /* 37922 */ GIR_EraseRootFromParent_Done, |
| 13676 | /* 37923 */ // Label 1060: @37923 |
| 13677 | /* 37923 */ GIM_Reject, |
| 13678 | /* 37924 */ // Label 1053: @37924 |
| 13679 | /* 37924 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1061*/ GIMT_Encode4(37949), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1882 // |
| 13680 | /* 37931 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 13681 | /* 37934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13682 | /* 37938 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13683 | /* 37942 */ // (ftrunc:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTZNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 13684 | /* 37942 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDh), |
| 13685 | /* 37947 */ GIR_RootConstrainSelectedInstOperands, |
| 13686 | /* 37948 */ // GIR_Coverage, 1882, |
| 13687 | /* 37948 */ GIR_Done, |
| 13688 | /* 37949 */ // Label 1061: @37949 |
| 13689 | /* 37949 */ GIM_Reject, |
| 13690 | /* 37950 */ // Label 1054: @37950 |
| 13691 | /* 37950 */ GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(38035), |
| 13692 | /* 37955 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13693 | /* 37958 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1063*/ GIMT_Encode4(37980), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1884 // |
| 13694 | /* 37965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13695 | /* 37969 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13696 | /* 37973 */ // (ftrunc:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTZNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 13697 | /* 37973 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQh), |
| 13698 | /* 37978 */ GIR_RootConstrainSelectedInstOperands, |
| 13699 | /* 37979 */ // GIR_Coverage, 1884, |
| 13700 | /* 37979 */ GIR_Done, |
| 13701 | /* 37980 */ // Label 1063: @37980 |
| 13702 | /* 37980 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1064*/ GIMT_Encode4(38034), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4371 // |
| 13703 | /* 37987 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13704 | /* 37991 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13705 | /* 37995 */ // (ftrunc:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 13706 | /* 37995 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13707 | /* 37998 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13708 | /* 38002 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13709 | /* 38007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z), |
| 13710 | /* 38010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13711 | /* 38012 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 13712 | /* 38014 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13713 | /* 38017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13714 | /* 38023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13715 | /* 38029 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13716 | /* 38032 */ GIR_RootConstrainSelectedInstOperands, |
| 13717 | /* 38033 */ // GIR_Coverage, 4371, |
| 13718 | /* 38033 */ GIR_EraseRootFromParent_Done, |
| 13719 | /* 38034 */ // Label 1064: @38034 |
| 13720 | /* 38034 */ GIM_Reject, |
| 13721 | /* 38035 */ // Label 1062: @38035 |
| 13722 | /* 38035 */ GIM_Reject, |
| 13723 | /* 38036 */ // Label 1055: @38036 |
| 13724 | /* 38036 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1065*/ GIMT_Encode4(38061), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1878 // |
| 13725 | /* 38043 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 13726 | /* 38046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13727 | /* 38050 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13728 | /* 38054 */ // (ftrunc:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTZNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 13729 | /* 38054 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDf), |
| 13730 | /* 38059 */ GIR_RootConstrainSelectedInstOperands, |
| 13731 | /* 38060 */ // GIR_Coverage, 1878, |
| 13732 | /* 38060 */ GIR_Done, |
| 13733 | /* 38061 */ // Label 1065: @38061 |
| 13734 | /* 38061 */ GIM_Reject, |
| 13735 | /* 38062 */ // Label 1056: @38062 |
| 13736 | /* 38062 */ GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(38147), |
| 13737 | /* 38067 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13738 | /* 38070 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1067*/ GIMT_Encode4(38092), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1880 // |
| 13739 | /* 38077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13740 | /* 38081 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13741 | /* 38085 */ // (ftrunc:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTZNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 13742 | /* 38085 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQf), |
| 13743 | /* 38090 */ GIR_RootConstrainSelectedInstOperands, |
| 13744 | /* 38091 */ // GIR_Coverage, 1880, |
| 13745 | /* 38091 */ GIR_Done, |
| 13746 | /* 38092 */ // Label 1067: @38092 |
| 13747 | /* 38092 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1068*/ GIMT_Encode4(38146), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4395 // |
| 13748 | /* 38099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13749 | /* 38103 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13750 | /* 38107 */ // (ftrunc:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 13751 | /* 38107 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13752 | /* 38110 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13753 | /* 38114 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13754 | /* 38119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z), |
| 13755 | /* 38122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13756 | /* 38124 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 13757 | /* 38126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13758 | /* 38129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13759 | /* 38135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13760 | /* 38141 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13761 | /* 38144 */ GIR_RootConstrainSelectedInstOperands, |
| 13762 | /* 38145 */ // GIR_Coverage, 4395, |
| 13763 | /* 38145 */ GIR_EraseRootFromParent_Done, |
| 13764 | /* 38146 */ // Label 1068: @38146 |
| 13765 | /* 38146 */ GIM_Reject, |
| 13766 | /* 38147 */ // Label 1066: @38147 |
| 13767 | /* 38147 */ GIM_Reject, |
| 13768 | /* 38148 */ // Label 1057: @38148 |
| 13769 | /* 38148 */ GIM_Reject, |
| 13770 | /* 38149 */ // Label 17: @38149 |
| 13771 | /* 38149 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 1076*/ GIMT_Encode4(38514), |
| 13772 | /* 38160 */ /*GILLT_s16*//*Label 1069*/ GIMT_Encode4(38212), |
| 13773 | /* 38164 */ /*GILLT_s32*//*Label 1070*/ GIMT_Encode4(38238), |
| 13774 | /* 38168 */ /*GILLT_s64*//*Label 1071*/ GIMT_Encode4(38264), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 13775 | /* 38196 */ /*GILLT_v4s16*//*Label 1072*/ GIMT_Encode4(38290), |
| 13776 | /* 38200 */ /*GILLT_v8s16*//*Label 1073*/ GIMT_Encode4(38316), |
| 13777 | /* 38204 */ /*GILLT_v2s32*//*Label 1074*/ GIMT_Encode4(38402), |
| 13778 | /* 38208 */ /*GILLT_v4s32*//*Label 1075*/ GIMT_Encode4(38428), |
| 13779 | /* 38212 */ // Label 1069: @38212 |
| 13780 | /* 38212 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1077*/ GIMT_Encode4(38237), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 711 // |
| 13781 | /* 38219 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 13782 | /* 38222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13783 | /* 38226 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13784 | /* 38230 */ // (fround:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTAH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 13785 | /* 38230 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAH), |
| 13786 | /* 38235 */ GIR_RootConstrainSelectedInstOperands, |
| 13787 | /* 38236 */ // GIR_Coverage, 711, |
| 13788 | /* 38236 */ GIR_Done, |
| 13789 | /* 38237 */ // Label 1077: @38237 |
| 13790 | /* 38237 */ GIM_Reject, |
| 13791 | /* 38238 */ // Label 1070: @38238 |
| 13792 | /* 38238 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1078*/ GIMT_Encode4(38263), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 713 // |
| 13793 | /* 38245 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 13794 | /* 38248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13795 | /* 38252 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13796 | /* 38256 */ // (fround:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTAS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 13797 | /* 38256 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAS), |
| 13798 | /* 38261 */ GIR_RootConstrainSelectedInstOperands, |
| 13799 | /* 38262 */ // GIR_Coverage, 713, |
| 13800 | /* 38262 */ GIR_Done, |
| 13801 | /* 38263 */ // Label 1078: @38263 |
| 13802 | /* 38263 */ GIM_Reject, |
| 13803 | /* 38264 */ // Label 1071: @38264 |
| 13804 | /* 38264 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1079*/ GIMT_Encode4(38289), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 715 // |
| 13805 | /* 38271 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 13806 | /* 38274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13807 | /* 38278 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13808 | /* 38282 */ // (fround:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTAD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 13809 | /* 38282 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAD), |
| 13810 | /* 38287 */ GIR_RootConstrainSelectedInstOperands, |
| 13811 | /* 38288 */ // GIR_Coverage, 715, |
| 13812 | /* 38288 */ GIR_Done, |
| 13813 | /* 38289 */ // Label 1079: @38289 |
| 13814 | /* 38289 */ GIM_Reject, |
| 13815 | /* 38290 */ // Label 1072: @38290 |
| 13816 | /* 38290 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1080*/ GIMT_Encode4(38315), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1874 // |
| 13817 | /* 38297 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 13818 | /* 38300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13819 | /* 38304 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13820 | /* 38308 */ // (fround:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTANDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 13821 | /* 38308 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDh), |
| 13822 | /* 38313 */ GIR_RootConstrainSelectedInstOperands, |
| 13823 | /* 38314 */ // GIR_Coverage, 1874, |
| 13824 | /* 38314 */ GIR_Done, |
| 13825 | /* 38315 */ // Label 1080: @38315 |
| 13826 | /* 38315 */ GIM_Reject, |
| 13827 | /* 38316 */ // Label 1073: @38316 |
| 13828 | /* 38316 */ GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(38401), |
| 13829 | /* 38321 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13830 | /* 38324 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1082*/ GIMT_Encode4(38346), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1876 // |
| 13831 | /* 38331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13832 | /* 38335 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13833 | /* 38339 */ // (fround:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTANQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 13834 | /* 38339 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQh), |
| 13835 | /* 38344 */ GIR_RootConstrainSelectedInstOperands, |
| 13836 | /* 38345 */ // GIR_Coverage, 1876, |
| 13837 | /* 38345 */ GIR_Done, |
| 13838 | /* 38346 */ // Label 1082: @38346 |
| 13839 | /* 38346 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1083*/ GIMT_Encode4(38400), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4367 // |
| 13840 | /* 38353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13841 | /* 38357 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13842 | /* 38361 */ // (fround:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 13843 | /* 38361 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13844 | /* 38364 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13845 | /* 38368 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13846 | /* 38373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A), |
| 13847 | /* 38376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13848 | /* 38378 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 13849 | /* 38380 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13850 | /* 38383 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13851 | /* 38389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13852 | /* 38395 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13853 | /* 38398 */ GIR_RootConstrainSelectedInstOperands, |
| 13854 | /* 38399 */ // GIR_Coverage, 4367, |
| 13855 | /* 38399 */ GIR_EraseRootFromParent_Done, |
| 13856 | /* 38400 */ // Label 1083: @38400 |
| 13857 | /* 38400 */ GIM_Reject, |
| 13858 | /* 38401 */ // Label 1081: @38401 |
| 13859 | /* 38401 */ GIM_Reject, |
| 13860 | /* 38402 */ // Label 1074: @38402 |
| 13861 | /* 38402 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1084*/ GIMT_Encode4(38427), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1870 // |
| 13862 | /* 38409 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 13863 | /* 38412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13864 | /* 38416 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13865 | /* 38420 */ // (fround:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTANDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 13866 | /* 38420 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDf), |
| 13867 | /* 38425 */ GIR_RootConstrainSelectedInstOperands, |
| 13868 | /* 38426 */ // GIR_Coverage, 1870, |
| 13869 | /* 38426 */ GIR_Done, |
| 13870 | /* 38427 */ // Label 1084: @38427 |
| 13871 | /* 38427 */ GIM_Reject, |
| 13872 | /* 38428 */ // Label 1075: @38428 |
| 13873 | /* 38428 */ GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(38513), |
| 13874 | /* 38433 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 13875 | /* 38436 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1086*/ GIMT_Encode4(38458), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1872 // |
| 13876 | /* 38443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13877 | /* 38447 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13878 | /* 38451 */ // (fround:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTANQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 13879 | /* 38451 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQf), |
| 13880 | /* 38456 */ GIR_RootConstrainSelectedInstOperands, |
| 13881 | /* 38457 */ // GIR_Coverage, 1872, |
| 13882 | /* 38457 */ GIR_Done, |
| 13883 | /* 38458 */ // Label 1086: @38458 |
| 13884 | /* 38458 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1087*/ GIMT_Encode4(38512), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4391 // |
| 13885 | /* 38465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13886 | /* 38469 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13887 | /* 38473 */ // (fround:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 13888 | /* 38473 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13889 | /* 38476 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13890 | /* 38480 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13891 | /* 38485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A), |
| 13892 | /* 38488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13893 | /* 38490 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 13894 | /* 38492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13895 | /* 38495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13896 | /* 38501 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13897 | /* 38507 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13898 | /* 38510 */ GIR_RootConstrainSelectedInstOperands, |
| 13899 | /* 38511 */ // GIR_Coverage, 4391, |
| 13900 | /* 38511 */ GIR_EraseRootFromParent_Done, |
| 13901 | /* 38512 */ // Label 1087: @38512 |
| 13902 | /* 38512 */ GIM_Reject, |
| 13903 | /* 38513 */ // Label 1085: @38513 |
| 13904 | /* 38513 */ GIM_Reject, |
| 13905 | /* 38514 */ // Label 1076: @38514 |
| 13906 | /* 38514 */ GIM_Reject, |
| 13907 | /* 38515 */ // Label 18: @38515 |
| 13908 | /* 38515 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 1095*/ GIMT_Encode4(38880), |
| 13909 | /* 38526 */ /*GILLT_s16*//*Label 1088*/ GIMT_Encode4(38578), |
| 13910 | /* 38530 */ /*GILLT_s32*//*Label 1089*/ GIMT_Encode4(38604), |
| 13911 | /* 38534 */ /*GILLT_s64*//*Label 1090*/ GIMT_Encode4(38630), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 13912 | /* 38562 */ /*GILLT_v4s16*//*Label 1091*/ GIMT_Encode4(38656), |
| 13913 | /* 38566 */ /*GILLT_v8s16*//*Label 1092*/ GIMT_Encode4(38682), |
| 13914 | /* 38570 */ /*GILLT_v2s32*//*Label 1093*/ GIMT_Encode4(38768), |
| 13915 | /* 38574 */ /*GILLT_v4s32*//*Label 1094*/ GIMT_Encode4(38794), |
| 13916 | /* 38578 */ // Label 1088: @38578 |
| 13917 | /* 38578 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1096*/ GIMT_Encode4(38603), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 717 // |
| 13918 | /* 38585 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 13919 | /* 38588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13920 | /* 38592 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 13921 | /* 38596 */ // (froundeven:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 13922 | /* 38596 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNH), |
| 13923 | /* 38601 */ GIR_RootConstrainSelectedInstOperands, |
| 13924 | /* 38602 */ // GIR_Coverage, 717, |
| 13925 | /* 38602 */ GIR_Done, |
| 13926 | /* 38603 */ // Label 1096: @38603 |
| 13927 | /* 38603 */ GIM_Reject, |
| 13928 | /* 38604 */ // Label 1089: @38604 |
| 13929 | /* 38604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1097*/ GIMT_Encode4(38629), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 719 // |
| 13930 | /* 38611 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 13931 | /* 38614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13932 | /* 38618 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 13933 | /* 38622 */ // (froundeven:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 13934 | /* 38622 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNS), |
| 13935 | /* 38627 */ GIR_RootConstrainSelectedInstOperands, |
| 13936 | /* 38628 */ // GIR_Coverage, 719, |
| 13937 | /* 38628 */ GIR_Done, |
| 13938 | /* 38629 */ // Label 1097: @38629 |
| 13939 | /* 38629 */ GIM_Reject, |
| 13940 | /* 38630 */ // Label 1090: @38630 |
| 13941 | /* 38630 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1098*/ GIMT_Encode4(38655), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 721 // |
| 13942 | /* 38637 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 13943 | /* 38640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13944 | /* 38644 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13945 | /* 38648 */ // (froundeven:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 13946 | /* 38648 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTND), |
| 13947 | /* 38653 */ GIR_RootConstrainSelectedInstOperands, |
| 13948 | /* 38654 */ // GIR_Coverage, 721, |
| 13949 | /* 38654 */ GIR_Done, |
| 13950 | /* 38655 */ // Label 1098: @38655 |
| 13951 | /* 38655 */ GIM_Reject, |
| 13952 | /* 38656 */ // Label 1091: @38656 |
| 13953 | /* 38656 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1099*/ GIMT_Encode4(38681), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1858 // |
| 13954 | /* 38663 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 13955 | /* 38666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13956 | /* 38670 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 13957 | /* 38674 */ // (froundeven:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 13958 | /* 38674 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDh), |
| 13959 | /* 38679 */ GIR_RootConstrainSelectedInstOperands, |
| 13960 | /* 38680 */ // GIR_Coverage, 1858, |
| 13961 | /* 38680 */ GIR_Done, |
| 13962 | /* 38681 */ // Label 1099: @38681 |
| 13963 | /* 38681 */ GIM_Reject, |
| 13964 | /* 38682 */ // Label 1092: @38682 |
| 13965 | /* 38682 */ GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(38767), |
| 13966 | /* 38687 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13967 | /* 38690 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1101*/ GIMT_Encode4(38712), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1860 // |
| 13968 | /* 38697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13969 | /* 38701 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 13970 | /* 38705 */ // (froundeven:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 13971 | /* 38705 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQh), |
| 13972 | /* 38710 */ GIR_RootConstrainSelectedInstOperands, |
| 13973 | /* 38711 */ // GIR_Coverage, 1860, |
| 13974 | /* 38711 */ GIR_Done, |
| 13975 | /* 38712 */ // Label 1101: @38712 |
| 13976 | /* 38712 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1102*/ GIMT_Encode4(38766), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4359 // |
| 13977 | /* 38719 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13978 | /* 38723 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 13979 | /* 38727 */ // (froundeven:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 13980 | /* 38727 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 13981 | /* 38730 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 13982 | /* 38734 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 13983 | /* 38739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N), |
| 13984 | /* 38742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 13985 | /* 38744 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 13986 | /* 38746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 13987 | /* 38749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13988 | /* 38755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 13989 | /* 38761 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 13990 | /* 38764 */ GIR_RootConstrainSelectedInstOperands, |
| 13991 | /* 38765 */ // GIR_Coverage, 4359, |
| 13992 | /* 38765 */ GIR_EraseRootFromParent_Done, |
| 13993 | /* 38766 */ // Label 1102: @38766 |
| 13994 | /* 38766 */ GIM_Reject, |
| 13995 | /* 38767 */ // Label 1100: @38767 |
| 13996 | /* 38767 */ GIM_Reject, |
| 13997 | /* 38768 */ // Label 1093: @38768 |
| 13998 | /* 38768 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1103*/ GIMT_Encode4(38793), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1854 // |
| 13999 | /* 38775 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 14000 | /* 38778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14001 | /* 38782 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14002 | /* 38786 */ // (froundeven:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTNNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 14003 | /* 38786 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDf), |
| 14004 | /* 38791 */ GIR_RootConstrainSelectedInstOperands, |
| 14005 | /* 38792 */ // GIR_Coverage, 1854, |
| 14006 | /* 38792 */ GIR_Done, |
| 14007 | /* 38793 */ // Label 1103: @38793 |
| 14008 | /* 38793 */ GIM_Reject, |
| 14009 | /* 38794 */ // Label 1094: @38794 |
| 14010 | /* 38794 */ GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(38879), |
| 14011 | /* 38799 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 14012 | /* 38802 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1105*/ GIMT_Encode4(38824), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1856 // |
| 14013 | /* 38809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14014 | /* 38813 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14015 | /* 38817 */ // (froundeven:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTNNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 14016 | /* 38817 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQf), |
| 14017 | /* 38822 */ GIR_RootConstrainSelectedInstOperands, |
| 14018 | /* 38823 */ // GIR_Coverage, 1856, |
| 14019 | /* 38823 */ GIR_Done, |
| 14020 | /* 38824 */ // Label 1105: @38824 |
| 14021 | /* 38824 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1106*/ GIMT_Encode4(38878), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4383 // |
| 14022 | /* 38831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14023 | /* 38835 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 14024 | /* 38839 */ // (froundeven:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 14025 | /* 38839 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 14026 | /* 38842 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 14027 | /* 38846 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14028 | /* 38851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N), |
| 14029 | /* 38854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 14030 | /* 38856 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 14031 | /* 38858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14032 | /* 38861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14033 | /* 38867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14034 | /* 38873 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14035 | /* 38876 */ GIR_RootConstrainSelectedInstOperands, |
| 14036 | /* 38877 */ // GIR_Coverage, 4383, |
| 14037 | /* 38877 */ GIR_EraseRootFromParent_Done, |
| 14038 | /* 38878 */ // Label 1106: @38878 |
| 14039 | /* 38878 */ GIM_Reject, |
| 14040 | /* 38879 */ // Label 1104: @38879 |
| 14041 | /* 38879 */ GIM_Reject, |
| 14042 | /* 38880 */ // Label 1095: @38880 |
| 14043 | /* 38880 */ GIM_Reject, |
| 14044 | /* 38881 */ // Label 19: @38881 |
| 14045 | /* 38881 */ GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(39041), |
| 14046 | /* 38886 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14047 | /* 38889 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 14048 | /* 38892 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1108*/ GIMT_Encode4(38966), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 2247 // |
| 14049 | /* 38899 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 14050 | /* 38906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 14051 | /* 38910 */ // MIs[0] Rn |
| 14052 | /* 38910 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 14053 | /* 38914 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 14054 | /* 38918 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (tLDRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] })) |
| 14055 | /* 38918 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 14056 | /* 38921 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 14057 | /* 38925 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14058 | /* 38930 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 14059 | /* 38936 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 14060 | /* 38939 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 14061 | /* 38942 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14062 | /* 38948 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14063 | /* 38950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSB), |
| 14064 | /* 38953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 14065 | /* 38955 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 14066 | /* 38957 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14067 | /* 38960 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14068 | /* 38964 */ GIR_RootConstrainSelectedInstOperands, |
| 14069 | /* 38965 */ // GIR_Coverage, 2247, |
| 14070 | /* 38965 */ GIR_EraseRootFromParent_Done, |
| 14071 | /* 38966 */ // Label 1108: @38966 |
| 14072 | /* 38966 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1109*/ GIMT_Encode4(39040), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 2248 // |
| 14073 | /* 38973 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 14074 | /* 38980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 14075 | /* 38984 */ // MIs[0] Rn |
| 14076 | /* 38984 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 14077 | /* 38988 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 14078 | /* 38992 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (tLDRSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] })) |
| 14079 | /* 38992 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 14080 | /* 38995 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 14081 | /* 38999 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 14082 | /* 39004 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 14083 | /* 39010 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 14084 | /* 39013 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 14085 | /* 39016 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14086 | /* 39022 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14087 | /* 39024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSH), |
| 14088 | /* 39027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 14089 | /* 39029 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 14090 | /* 39031 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14091 | /* 39034 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14092 | /* 39038 */ GIR_RootConstrainSelectedInstOperands, |
| 14093 | /* 39039 */ // GIR_Coverage, 2248, |
| 14094 | /* 39039 */ GIR_EraseRootFromParent_Done, |
| 14095 | /* 39040 */ // Label 1109: @39040 |
| 14096 | /* 39040 */ GIM_Reject, |
| 14097 | /* 39041 */ // Label 1107: @39041 |
| 14098 | /* 39041 */ GIM_Reject, |
| 14099 | /* 39042 */ // Label 20: @39042 |
| 14100 | /* 39042 */ GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(39062), // Rule ID 5947 // |
| 14101 | /* 39047 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 14102 | /* 39050 */ // MIs[0] Operand 0 |
| 14103 | /* 39050 */ GIM_CheckIsImm, /*MI*/0, /*Op*/0, |
| 14104 | /* 39053 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, |
| 14105 | /* 39057 */ // (atomic_fence (timm:{ *:[i32] }), 0:{ *:[i32] }) => (MEMBARRIER) |
| 14106 | /* 39057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::MEMBARRIER), |
| 14107 | /* 39060 */ GIR_RootConstrainSelectedInstOperands, |
| 14108 | /* 39061 */ // GIR_Coverage, 5947, |
| 14109 | /* 39061 */ GIR_EraseRootFromParent_Done, |
| 14110 | /* 39062 */ // Label 1110: @39062 |
| 14111 | /* 39062 */ GIM_Reject, |
| 14112 | /* 39063 */ // Label 21: @39063 |
| 14113 | /* 39063 */ GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(44374), |
| 14114 | /* 39068 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 14115 | /* 39071 */ GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(39160), |
| 14116 | /* 39076 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16), |
| 14117 | /* 39081 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14118 | /* 39084 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 14119 | /* 39087 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1113*/ GIMT_Encode4(39123), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2044 // |
| 14120 | /* 39094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 14121 | /* 39098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 14122 | /* 39102 */ // (intrinsic_wo_chain:{ *:[i32] } 4231:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 14123 | /* 39102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16), |
| 14124 | /* 39105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 14125 | /* 39107 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src |
| 14126 | /* 39109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14127 | /* 39112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14128 | /* 39115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14129 | /* 39121 */ GIR_RootConstrainSelectedInstOperands, |
| 14130 | /* 39122 */ // GIR_Coverage, 2044, |
| 14131 | /* 39122 */ GIR_EraseRootFromParent_Done, |
| 14132 | /* 39123 */ // Label 1113: @39123 |
| 14133 | /* 39123 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1114*/ GIMT_Encode4(39159), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2304 // |
| 14134 | /* 39130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14135 | /* 39134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 14136 | /* 39138 */ // (intrinsic_wo_chain:{ *:[i32] } 4231:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 14137 | /* 39138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16), |
| 14138 | /* 39141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 14139 | /* 39143 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 14140 | /* 39145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14141 | /* 39148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14142 | /* 39151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14143 | /* 39157 */ GIR_RootConstrainSelectedInstOperands, |
| 14144 | /* 39158 */ // GIR_Coverage, 2304, |
| 14145 | /* 39158 */ GIR_EraseRootFromParent_Done, |
| 14146 | /* 39159 */ // Label 1114: @39159 |
| 14147 | /* 39159 */ GIM_Reject, |
| 14148 | /* 39160 */ // Label 1112: @39160 |
| 14149 | /* 39160 */ GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(39261), |
| 14150 | /* 39165 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr), |
| 14151 | /* 39170 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14152 | /* 39173 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1118*/ GIMT_Encode4(39260), |
| 14153 | /* 39184 */ /*GILLT_s32*//*Label 1116*/ GIMT_Encode4(39192), |
| 14154 | /* 39188 */ /*GILLT_s64*//*Label 1117*/ GIMT_Encode4(39226), |
| 14155 | /* 39192 */ // Label 1116: @39192 |
| 14156 | /* 39192 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1119*/ GIMT_Encode4(39225), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 745 // |
| 14157 | /* 39199 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14158 | /* 39203 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14159 | /* 39207 */ // (intrinsic_wo_chain:{ *:[f32] } 4232:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 14160 | /* 39207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRS), |
| 14161 | /* 39210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 14162 | /* 39212 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 14163 | /* 39214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14164 | /* 39217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14165 | /* 39223 */ GIR_RootConstrainSelectedInstOperands, |
| 14166 | /* 39224 */ // GIR_Coverage, 745, |
| 14167 | /* 39224 */ GIR_EraseRootFromParent_Done, |
| 14168 | /* 39225 */ // Label 1119: @39225 |
| 14169 | /* 39225 */ GIM_Reject, |
| 14170 | /* 39226 */ // Label 1117: @39226 |
| 14171 | /* 39226 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1120*/ GIMT_Encode4(39259), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 744 // |
| 14172 | /* 39233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14173 | /* 39237 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14174 | /* 39241 */ // (intrinsic_wo_chain:{ *:[f32] } 4232:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) |
| 14175 | /* 39241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRD), |
| 14176 | /* 39244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 14177 | /* 39246 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 14178 | /* 39248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14179 | /* 39251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14180 | /* 39257 */ GIR_RootConstrainSelectedInstOperands, |
| 14181 | /* 39258 */ // GIR_Coverage, 744, |
| 14182 | /* 39258 */ GIR_EraseRootFromParent_Done, |
| 14183 | /* 39259 */ // Label 1120: @39259 |
| 14184 | /* 39259 */ GIM_Reject, |
| 14185 | /* 39260 */ // Label 1118: @39260 |
| 14186 | /* 39260 */ GIM_Reject, |
| 14187 | /* 39261 */ // Label 1115: @39261 |
| 14188 | /* 39261 */ GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(39362), |
| 14189 | /* 39266 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru), |
| 14190 | /* 39271 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 14191 | /* 39274 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1124*/ GIMT_Encode4(39361), |
| 14192 | /* 39285 */ /*GILLT_s32*//*Label 1122*/ GIMT_Encode4(39293), |
| 14193 | /* 39289 */ /*GILLT_s64*//*Label 1123*/ GIMT_Encode4(39327), |
| 14194 | /* 39293 */ // Label 1122: @39293 |
| 14195 | /* 39293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1125*/ GIMT_Encode4(39326), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 747 // |
| 14196 | /* 39300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14197 | /* 39304 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14198 | /* 39308 */ // (intrinsic_wo_chain:{ *:[f32] } 4233:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 14199 | /* 39308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRS), |
| 14200 | /* 39311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 14201 | /* 39313 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 14202 | /* 39315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14203 | /* 39318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14204 | /* 39324 */ GIR_RootConstrainSelectedInstOperands, |
| 14205 | /* 39325 */ // GIR_Coverage, 747, |
| 14206 | /* 39325 */ GIR_EraseRootFromParent_Done, |
| 14207 | /* 39326 */ // Label 1125: @39326 |
| 14208 | /* 39326 */ GIM_Reject, |
| 14209 | /* 39327 */ // Label 1123: @39327 |
| 14210 | /* 39327 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1126*/ GIMT_Encode4(39360), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 746 // |
| 14211 | /* 39334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 14212 | /* 39338 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14213 | /* 39342 */ // (intrinsic_wo_chain:{ *:[f32] } 4233:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) |
| 14214 | /* 39342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRD), |
| 14215 | /* 39345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 14216 | /* 39347 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 14217 | /* 39349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14218 | /* 39352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14219 | /* 39358 */ GIR_RootConstrainSelectedInstOperands, |
| 14220 | /* 39359 */ // GIR_Coverage, 746, |
| 14221 | /* 39359 */ GIR_EraseRootFromParent_Done, |
| 14222 | /* 39360 */ // Label 1126: @39360 |
| 14223 | /* 39360 */ GIM_Reject, |
| 14224 | /* 39361 */ // Label 1124: @39361 |
| 14225 | /* 39361 */ GIM_Reject, |
| 14226 | /* 39362 */ // Label 1121: @39362 |
| 14227 | /* 39362 */ GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(39654), |
| 14228 | /* 39367 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls), |
| 14229 | /* 39372 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1134*/ GIMT_Encode4(39653), |
| 14230 | /* 39383 */ /*GILLT_s64*//*Label 1128*/ GIMT_Encode4(39431), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 14231 | /* 39411 */ /*GILLT_v4s16*//*Label 1129*/ GIMT_Encode4(39468), |
| 14232 | /* 39415 */ /*GILLT_v8s16*//*Label 1130*/ GIMT_Encode4(39505), |
| 14233 | /* 39419 */ /*GILLT_v2s32*//*Label 1131*/ GIMT_Encode4(39542), |
| 14234 | /* 39423 */ /*GILLT_v4s32*//*Label 1132*/ GIMT_Encode4(39579), |
| 14235 | /* 39427 */ /*GILLT_v2s64*//*Label 1133*/ GIMT_Encode4(39616), |
| 14236 | /* 39431 */ // Label 1128: @39431 |
| 14237 | /* 39431 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1135*/ GIMT_Encode4(39467), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1406 // |
| 14238 | /* 39438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14239 | /* 39441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14240 | /* 39445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14241 | /* 39449 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4089:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm) |
| 14242 | /* 39449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv2i32), |
| 14243 | /* 39452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14244 | /* 39454 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14245 | /* 39456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14246 | /* 39459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14247 | /* 39465 */ GIR_RootConstrainSelectedInstOperands, |
| 14248 | /* 39466 */ // GIR_Coverage, 1406, |
| 14249 | /* 39466 */ GIR_EraseRootFromParent_Done, |
| 14250 | /* 39467 */ // Label 1135: @39467 |
| 14251 | /* 39467 */ GIM_Reject, |
| 14252 | /* 39468 */ // Label 1129: @39468 |
| 14253 | /* 39468 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1136*/ GIMT_Encode4(39504), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1404 // |
| 14254 | /* 39475 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 14255 | /* 39478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14256 | /* 39482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14257 | /* 39486 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4089:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm) |
| 14258 | /* 39486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i8), |
| 14259 | /* 39489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14260 | /* 39491 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14261 | /* 39493 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14262 | /* 39496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14263 | /* 39502 */ GIR_RootConstrainSelectedInstOperands, |
| 14264 | /* 39503 */ // GIR_Coverage, 1404, |
| 14265 | /* 39503 */ GIR_EraseRootFromParent_Done, |
| 14266 | /* 39504 */ // Label 1136: @39504 |
| 14267 | /* 39504 */ GIM_Reject, |
| 14268 | /* 39505 */ // Label 1130: @39505 |
| 14269 | /* 39505 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1137*/ GIMT_Encode4(39541), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1407 // |
| 14270 | /* 39512 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14271 | /* 39515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14272 | /* 39519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14273 | /* 39523 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4089:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm) |
| 14274 | /* 39523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv16i8), |
| 14275 | /* 39526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14276 | /* 39528 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14277 | /* 39530 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14278 | /* 39533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14279 | /* 39539 */ GIR_RootConstrainSelectedInstOperands, |
| 14280 | /* 39540 */ // GIR_Coverage, 1407, |
| 14281 | /* 39540 */ GIR_EraseRootFromParent_Done, |
| 14282 | /* 39541 */ // Label 1137: @39541 |
| 14283 | /* 39541 */ GIM_Reject, |
| 14284 | /* 39542 */ // Label 1131: @39542 |
| 14285 | /* 39542 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1138*/ GIMT_Encode4(39578), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1405 // |
| 14286 | /* 39549 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14287 | /* 39552 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14288 | /* 39556 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14289 | /* 39560 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4089:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm) |
| 14290 | /* 39560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i16), |
| 14291 | /* 39563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14292 | /* 39565 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14293 | /* 39567 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14294 | /* 39570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14295 | /* 39576 */ GIR_RootConstrainSelectedInstOperands, |
| 14296 | /* 39577 */ // GIR_Coverage, 1405, |
| 14297 | /* 39577 */ GIR_EraseRootFromParent_Done, |
| 14298 | /* 39578 */ // Label 1138: @39578 |
| 14299 | /* 39578 */ GIM_Reject, |
| 14300 | /* 39579 */ // Label 1132: @39579 |
| 14301 | /* 39579 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1139*/ GIMT_Encode4(39615), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1408 // |
| 14302 | /* 39586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14303 | /* 39589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14304 | /* 39593 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14305 | /* 39597 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4089:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm) |
| 14306 | /* 39597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i16), |
| 14307 | /* 39600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14308 | /* 39602 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14309 | /* 39604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14310 | /* 39607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14311 | /* 39613 */ GIR_RootConstrainSelectedInstOperands, |
| 14312 | /* 39614 */ // GIR_Coverage, 1408, |
| 14313 | /* 39614 */ GIR_EraseRootFromParent_Done, |
| 14314 | /* 39615 */ // Label 1139: @39615 |
| 14315 | /* 39615 */ GIM_Reject, |
| 14316 | /* 39616 */ // Label 1133: @39616 |
| 14317 | /* 39616 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1140*/ GIMT_Encode4(39652), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1409 // |
| 14318 | /* 39623 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14319 | /* 39626 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14320 | /* 39630 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14321 | /* 39634 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4089:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm) |
| 14322 | /* 39634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i32), |
| 14323 | /* 39637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14324 | /* 39639 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14325 | /* 39641 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14326 | /* 39644 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14327 | /* 39650 */ GIR_RootConstrainSelectedInstOperands, |
| 14328 | /* 39651 */ // GIR_Coverage, 1409, |
| 14329 | /* 39651 */ GIR_EraseRootFromParent_Done, |
| 14330 | /* 39652 */ // Label 1140: @39652 |
| 14331 | /* 39652 */ GIM_Reject, |
| 14332 | /* 39653 */ // Label 1134: @39653 |
| 14333 | /* 39653 */ GIM_Reject, |
| 14334 | /* 39654 */ // Label 1127: @39654 |
| 14335 | /* 39654 */ GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(39946), |
| 14336 | /* 39659 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu), |
| 14337 | /* 39664 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1148*/ GIMT_Encode4(39945), |
| 14338 | /* 39675 */ /*GILLT_s64*//*Label 1142*/ GIMT_Encode4(39723), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 14339 | /* 39703 */ /*GILLT_v4s16*//*Label 1143*/ GIMT_Encode4(39760), |
| 14340 | /* 39707 */ /*GILLT_v8s16*//*Label 1144*/ GIMT_Encode4(39797), |
| 14341 | /* 39711 */ /*GILLT_v2s32*//*Label 1145*/ GIMT_Encode4(39834), |
| 14342 | /* 39715 */ /*GILLT_v4s32*//*Label 1146*/ GIMT_Encode4(39871), |
| 14343 | /* 39719 */ /*GILLT_v2s64*//*Label 1147*/ GIMT_Encode4(39908), |
| 14344 | /* 39723 */ // Label 1142: @39723 |
| 14345 | /* 39723 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1149*/ GIMT_Encode4(39759), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1412 // |
| 14346 | /* 39730 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14347 | /* 39733 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14348 | /* 39737 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14349 | /* 39741 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4090:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm) |
| 14350 | /* 39741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv2i32), |
| 14351 | /* 39744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14352 | /* 39746 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14353 | /* 39748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14354 | /* 39751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14355 | /* 39757 */ GIR_RootConstrainSelectedInstOperands, |
| 14356 | /* 39758 */ // GIR_Coverage, 1412, |
| 14357 | /* 39758 */ GIR_EraseRootFromParent_Done, |
| 14358 | /* 39759 */ // Label 1149: @39759 |
| 14359 | /* 39759 */ GIM_Reject, |
| 14360 | /* 39760 */ // Label 1143: @39760 |
| 14361 | /* 39760 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1150*/ GIMT_Encode4(39796), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1410 // |
| 14362 | /* 39767 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 14363 | /* 39770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14364 | /* 39774 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14365 | /* 39778 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4090:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm) |
| 14366 | /* 39778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i8), |
| 14367 | /* 39781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14368 | /* 39783 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14369 | /* 39785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14370 | /* 39788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14371 | /* 39794 */ GIR_RootConstrainSelectedInstOperands, |
| 14372 | /* 39795 */ // GIR_Coverage, 1410, |
| 14373 | /* 39795 */ GIR_EraseRootFromParent_Done, |
| 14374 | /* 39796 */ // Label 1150: @39796 |
| 14375 | /* 39796 */ GIM_Reject, |
| 14376 | /* 39797 */ // Label 1144: @39797 |
| 14377 | /* 39797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1151*/ GIMT_Encode4(39833), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1413 // |
| 14378 | /* 39804 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14379 | /* 39807 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14380 | /* 39811 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14381 | /* 39815 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4090:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm) |
| 14382 | /* 39815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv16i8), |
| 14383 | /* 39818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14384 | /* 39820 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14385 | /* 39822 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14386 | /* 39825 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14387 | /* 39831 */ GIR_RootConstrainSelectedInstOperands, |
| 14388 | /* 39832 */ // GIR_Coverage, 1413, |
| 14389 | /* 39832 */ GIR_EraseRootFromParent_Done, |
| 14390 | /* 39833 */ // Label 1151: @39833 |
| 14391 | /* 39833 */ GIM_Reject, |
| 14392 | /* 39834 */ // Label 1145: @39834 |
| 14393 | /* 39834 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1152*/ GIMT_Encode4(39870), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1411 // |
| 14394 | /* 39841 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14395 | /* 39844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14396 | /* 39848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14397 | /* 39852 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4090:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm) |
| 14398 | /* 39852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i16), |
| 14399 | /* 39855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14400 | /* 39857 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14401 | /* 39859 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14402 | /* 39862 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14403 | /* 39868 */ GIR_RootConstrainSelectedInstOperands, |
| 14404 | /* 39869 */ // GIR_Coverage, 1411, |
| 14405 | /* 39869 */ GIR_EraseRootFromParent_Done, |
| 14406 | /* 39870 */ // Label 1152: @39870 |
| 14407 | /* 39870 */ GIM_Reject, |
| 14408 | /* 39871 */ // Label 1146: @39871 |
| 14409 | /* 39871 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1153*/ GIMT_Encode4(39907), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1414 // |
| 14410 | /* 39878 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14411 | /* 39881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14412 | /* 39885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14413 | /* 39889 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4090:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm) |
| 14414 | /* 39889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i16), |
| 14415 | /* 39892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14416 | /* 39894 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14417 | /* 39896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14418 | /* 39899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14419 | /* 39905 */ GIR_RootConstrainSelectedInstOperands, |
| 14420 | /* 39906 */ // GIR_Coverage, 1414, |
| 14421 | /* 39906 */ GIR_EraseRootFromParent_Done, |
| 14422 | /* 39907 */ // Label 1153: @39907 |
| 14423 | /* 39907 */ GIM_Reject, |
| 14424 | /* 39908 */ // Label 1147: @39908 |
| 14425 | /* 39908 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1154*/ GIMT_Encode4(39944), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1415 // |
| 14426 | /* 39915 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14427 | /* 39918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14428 | /* 39922 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14429 | /* 39926 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4090:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm) |
| 14430 | /* 39926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i32), |
| 14431 | /* 39929 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14432 | /* 39931 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14433 | /* 39933 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14434 | /* 39936 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14435 | /* 39942 */ GIR_RootConstrainSelectedInstOperands, |
| 14436 | /* 39943 */ // GIR_Coverage, 1415, |
| 14437 | /* 39943 */ GIR_EraseRootFromParent_Done, |
| 14438 | /* 39944 */ // Label 1154: @39944 |
| 14439 | /* 39944 */ GIM_Reject, |
| 14440 | /* 39945 */ // Label 1148: @39945 |
| 14441 | /* 39945 */ GIM_Reject, |
| 14442 | /* 39946 */ // Label 1141: @39946 |
| 14443 | /* 39946 */ GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(40194), |
| 14444 | /* 39951 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe), |
| 14445 | /* 39956 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1160*/ GIMT_Encode4(40193), |
| 14446 | /* 39967 */ /*GILLT_v4s16*//*Label 1156*/ GIMT_Encode4(39983), |
| 14447 | /* 39971 */ /*GILLT_v8s16*//*Label 1157*/ GIMT_Encode4(40020), |
| 14448 | /* 39975 */ /*GILLT_v2s32*//*Label 1158*/ GIMT_Encode4(40057), |
| 14449 | /* 39979 */ /*GILLT_v4s32*//*Label 1159*/ GIMT_Encode4(40125), |
| 14450 | /* 39983 */ // Label 1156: @39983 |
| 14451 | /* 39983 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1161*/ GIMT_Encode4(40019), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1448 // |
| 14452 | /* 39990 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14453 | /* 39993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14454 | /* 39997 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14455 | /* 40001 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4117:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 14456 | /* 40001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhd), |
| 14457 | /* 40004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14458 | /* 40006 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14459 | /* 40008 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14460 | /* 40011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14461 | /* 40017 */ GIR_RootConstrainSelectedInstOperands, |
| 14462 | /* 40018 */ // GIR_Coverage, 1448, |
| 14463 | /* 40018 */ GIR_EraseRootFromParent_Done, |
| 14464 | /* 40019 */ // Label 1161: @40019 |
| 14465 | /* 40019 */ GIM_Reject, |
| 14466 | /* 40020 */ // Label 1157: @40020 |
| 14467 | /* 40020 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1162*/ GIMT_Encode4(40056), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1449 // |
| 14468 | /* 40027 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14469 | /* 40030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14470 | /* 40034 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14471 | /* 40038 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4117:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 14472 | /* 40038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhq), |
| 14473 | /* 40041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14474 | /* 40043 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14475 | /* 40045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14476 | /* 40048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14477 | /* 40054 */ GIR_RootConstrainSelectedInstOperands, |
| 14478 | /* 40055 */ // GIR_Coverage, 1449, |
| 14479 | /* 40055 */ GIR_EraseRootFromParent_Done, |
| 14480 | /* 40056 */ // Label 1162: @40056 |
| 14481 | /* 40056 */ GIM_Reject, |
| 14482 | /* 40057 */ // Label 1158: @40057 |
| 14483 | /* 40057 */ GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(40124), |
| 14484 | /* 40062 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14485 | /* 40065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14486 | /* 40069 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14487 | /* 40073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1164*/ GIMT_Encode4(40098), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1444 // |
| 14488 | /* 40080 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4117:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 14489 | /* 40080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEd), |
| 14490 | /* 40083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14491 | /* 40085 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14492 | /* 40087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14493 | /* 40090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14494 | /* 40096 */ GIR_RootConstrainSelectedInstOperands, |
| 14495 | /* 40097 */ // GIR_Coverage, 1444, |
| 14496 | /* 40097 */ GIR_EraseRootFromParent_Done, |
| 14497 | /* 40098 */ // Label 1164: @40098 |
| 14498 | /* 40098 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1165*/ GIMT_Encode4(40123), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1446 // |
| 14499 | /* 40105 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4117:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 14500 | /* 40105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfd), |
| 14501 | /* 40108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14502 | /* 40110 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14503 | /* 40112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14504 | /* 40115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14505 | /* 40121 */ GIR_RootConstrainSelectedInstOperands, |
| 14506 | /* 40122 */ // GIR_Coverage, 1446, |
| 14507 | /* 40122 */ GIR_EraseRootFromParent_Done, |
| 14508 | /* 40123 */ // Label 1165: @40123 |
| 14509 | /* 40123 */ GIM_Reject, |
| 14510 | /* 40124 */ // Label 1163: @40124 |
| 14511 | /* 40124 */ GIM_Reject, |
| 14512 | /* 40125 */ // Label 1159: @40125 |
| 14513 | /* 40125 */ GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(40192), |
| 14514 | /* 40130 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14515 | /* 40133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14516 | /* 40137 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14517 | /* 40141 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1167*/ GIMT_Encode4(40166), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1445 // |
| 14518 | /* 40148 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4117:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 14519 | /* 40148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEq), |
| 14520 | /* 40151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14521 | /* 40153 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14522 | /* 40155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14523 | /* 40158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14524 | /* 40164 */ GIR_RootConstrainSelectedInstOperands, |
| 14525 | /* 40165 */ // GIR_Coverage, 1445, |
| 14526 | /* 40165 */ GIR_EraseRootFromParent_Done, |
| 14527 | /* 40166 */ // Label 1167: @40166 |
| 14528 | /* 40166 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1168*/ GIMT_Encode4(40191), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1447 // |
| 14529 | /* 40173 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4117:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 14530 | /* 40173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfq), |
| 14531 | /* 40176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14532 | /* 40178 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14533 | /* 40180 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14534 | /* 40183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14535 | /* 40189 */ GIR_RootConstrainSelectedInstOperands, |
| 14536 | /* 40190 */ // GIR_Coverage, 1447, |
| 14537 | /* 40190 */ GIR_EraseRootFromParent_Done, |
| 14538 | /* 40191 */ // Label 1168: @40191 |
| 14539 | /* 40191 */ GIM_Reject, |
| 14540 | /* 40192 */ // Label 1166: @40192 |
| 14541 | /* 40192 */ GIM_Reject, |
| 14542 | /* 40193 */ // Label 1160: @40193 |
| 14543 | /* 40193 */ GIM_Reject, |
| 14544 | /* 40194 */ // Label 1155: @40194 |
| 14545 | /* 40194 */ GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(40442), |
| 14546 | /* 40199 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte), |
| 14547 | /* 40204 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1174*/ GIMT_Encode4(40441), |
| 14548 | /* 40215 */ /*GILLT_v4s16*//*Label 1170*/ GIMT_Encode4(40231), |
| 14549 | /* 40219 */ /*GILLT_v8s16*//*Label 1171*/ GIMT_Encode4(40268), |
| 14550 | /* 40223 */ /*GILLT_v2s32*//*Label 1172*/ GIMT_Encode4(40305), |
| 14551 | /* 40227 */ /*GILLT_v4s32*//*Label 1173*/ GIMT_Encode4(40373), |
| 14552 | /* 40231 */ // Label 1170: @40231 |
| 14553 | /* 40231 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1175*/ GIMT_Encode4(40267), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1458 // |
| 14554 | /* 40238 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14555 | /* 40241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14556 | /* 40245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14557 | /* 40249 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4124:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 14558 | /* 40249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhd), |
| 14559 | /* 40252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14560 | /* 40254 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14561 | /* 40256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14562 | /* 40259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14563 | /* 40265 */ GIR_RootConstrainSelectedInstOperands, |
| 14564 | /* 40266 */ // GIR_Coverage, 1458, |
| 14565 | /* 40266 */ GIR_EraseRootFromParent_Done, |
| 14566 | /* 40267 */ // Label 1175: @40267 |
| 14567 | /* 40267 */ GIM_Reject, |
| 14568 | /* 40268 */ // Label 1171: @40268 |
| 14569 | /* 40268 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1176*/ GIMT_Encode4(40304), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1459 // |
| 14570 | /* 40275 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14571 | /* 40278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14572 | /* 40282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14573 | /* 40286 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4124:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 14574 | /* 40286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhq), |
| 14575 | /* 40289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14576 | /* 40291 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14577 | /* 40293 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14578 | /* 40296 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14579 | /* 40302 */ GIR_RootConstrainSelectedInstOperands, |
| 14580 | /* 40303 */ // GIR_Coverage, 1459, |
| 14581 | /* 40303 */ GIR_EraseRootFromParent_Done, |
| 14582 | /* 40304 */ // Label 1176: @40304 |
| 14583 | /* 40304 */ GIM_Reject, |
| 14584 | /* 40305 */ // Label 1172: @40305 |
| 14585 | /* 40305 */ GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(40372), |
| 14586 | /* 40310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14587 | /* 40313 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14588 | /* 40317 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14589 | /* 40321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1178*/ GIMT_Encode4(40346), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1454 // |
| 14590 | /* 40328 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4124:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 14591 | /* 40328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEd), |
| 14592 | /* 40331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14593 | /* 40333 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14594 | /* 40335 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14595 | /* 40338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14596 | /* 40344 */ GIR_RootConstrainSelectedInstOperands, |
| 14597 | /* 40345 */ // GIR_Coverage, 1454, |
| 14598 | /* 40345 */ GIR_EraseRootFromParent_Done, |
| 14599 | /* 40346 */ // Label 1178: @40346 |
| 14600 | /* 40346 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1179*/ GIMT_Encode4(40371), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1456 // |
| 14601 | /* 40353 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4124:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 14602 | /* 40353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfd), |
| 14603 | /* 40356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14604 | /* 40358 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14605 | /* 40360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14606 | /* 40363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14607 | /* 40369 */ GIR_RootConstrainSelectedInstOperands, |
| 14608 | /* 40370 */ // GIR_Coverage, 1456, |
| 14609 | /* 40370 */ GIR_EraseRootFromParent_Done, |
| 14610 | /* 40371 */ // Label 1179: @40371 |
| 14611 | /* 40371 */ GIM_Reject, |
| 14612 | /* 40372 */ // Label 1177: @40372 |
| 14613 | /* 40372 */ GIM_Reject, |
| 14614 | /* 40373 */ // Label 1173: @40373 |
| 14615 | /* 40373 */ GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(40440), |
| 14616 | /* 40378 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14617 | /* 40381 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14618 | /* 40385 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14619 | /* 40389 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1181*/ GIMT_Encode4(40414), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1455 // |
| 14620 | /* 40396 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4124:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 14621 | /* 40396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEq), |
| 14622 | /* 40399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14623 | /* 40401 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14624 | /* 40403 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14625 | /* 40406 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14626 | /* 40412 */ GIR_RootConstrainSelectedInstOperands, |
| 14627 | /* 40413 */ // GIR_Coverage, 1455, |
| 14628 | /* 40413 */ GIR_EraseRootFromParent_Done, |
| 14629 | /* 40414 */ // Label 1181: @40414 |
| 14630 | /* 40414 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1182*/ GIMT_Encode4(40439), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1457 // |
| 14631 | /* 40421 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4124:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 14632 | /* 40421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfq), |
| 14633 | /* 40424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14634 | /* 40426 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14635 | /* 40428 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14636 | /* 40431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14637 | /* 40437 */ GIR_RootConstrainSelectedInstOperands, |
| 14638 | /* 40438 */ // GIR_Coverage, 1457, |
| 14639 | /* 40438 */ GIR_EraseRootFromParent_Done, |
| 14640 | /* 40439 */ // Label 1182: @40439 |
| 14641 | /* 40439 */ GIM_Reject, |
| 14642 | /* 40440 */ // Label 1180: @40440 |
| 14643 | /* 40440 */ GIM_Reject, |
| 14644 | /* 40441 */ // Label 1174: @40441 |
| 14645 | /* 40441 */ GIM_Reject, |
| 14646 | /* 40442 */ // Label 1169: @40442 |
| 14647 | /* 40442 */ GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(40710), |
| 14648 | /* 40447 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs), |
| 14649 | /* 40452 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1190*/ GIMT_Encode4(40709), |
| 14650 | /* 40463 */ /*GILLT_v8s8*//*Label 1184*/ GIMT_Encode4(40487), |
| 14651 | /* 40467 */ /*GILLT_v16s8*//*Label 1185*/ GIMT_Encode4(40524), |
| 14652 | /* 40471 */ /*GILLT_v4s16*//*Label 1186*/ GIMT_Encode4(40561), |
| 14653 | /* 40475 */ /*GILLT_v8s16*//*Label 1187*/ GIMT_Encode4(40598), |
| 14654 | /* 40479 */ /*GILLT_v2s32*//*Label 1188*/ GIMT_Encode4(40635), |
| 14655 | /* 40483 */ /*GILLT_v4s32*//*Label 1189*/ GIMT_Encode4(40672), |
| 14656 | /* 40487 */ // Label 1184: @40487 |
| 14657 | /* 40487 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1191*/ GIMT_Encode4(40523), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1680 // |
| 14658 | /* 40494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 14659 | /* 40497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14660 | /* 40501 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14661 | /* 40505 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4095:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 14662 | /* 40505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i8), |
| 14663 | /* 40508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14664 | /* 40510 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14665 | /* 40512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14666 | /* 40515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14667 | /* 40521 */ GIR_RootConstrainSelectedInstOperands, |
| 14668 | /* 40522 */ // GIR_Coverage, 1680, |
| 14669 | /* 40522 */ GIR_EraseRootFromParent_Done, |
| 14670 | /* 40523 */ // Label 1191: @40523 |
| 14671 | /* 40523 */ GIM_Reject, |
| 14672 | /* 40524 */ // Label 1185: @40524 |
| 14673 | /* 40524 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1192*/ GIMT_Encode4(40560), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1683 // |
| 14674 | /* 40531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14675 | /* 40534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14676 | /* 40538 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14677 | /* 40542 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4095:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 14678 | /* 40542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv16i8), |
| 14679 | /* 40545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14680 | /* 40547 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14681 | /* 40549 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14682 | /* 40552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14683 | /* 40558 */ GIR_RootConstrainSelectedInstOperands, |
| 14684 | /* 40559 */ // GIR_Coverage, 1683, |
| 14685 | /* 40559 */ GIR_EraseRootFromParent_Done, |
| 14686 | /* 40560 */ // Label 1192: @40560 |
| 14687 | /* 40560 */ GIM_Reject, |
| 14688 | /* 40561 */ // Label 1186: @40561 |
| 14689 | /* 40561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1193*/ GIMT_Encode4(40597), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1681 // |
| 14690 | /* 40568 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14691 | /* 40571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14692 | /* 40575 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14693 | /* 40579 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4095:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 14694 | /* 40579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i16), |
| 14695 | /* 40582 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14696 | /* 40584 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14697 | /* 40586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14698 | /* 40589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14699 | /* 40595 */ GIR_RootConstrainSelectedInstOperands, |
| 14700 | /* 40596 */ // GIR_Coverage, 1681, |
| 14701 | /* 40596 */ GIR_EraseRootFromParent_Done, |
| 14702 | /* 40597 */ // Label 1193: @40597 |
| 14703 | /* 40597 */ GIM_Reject, |
| 14704 | /* 40598 */ // Label 1187: @40598 |
| 14705 | /* 40598 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1194*/ GIMT_Encode4(40634), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1684 // |
| 14706 | /* 40605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14707 | /* 40608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14708 | /* 40612 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14709 | /* 40616 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4095:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 14710 | /* 40616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i16), |
| 14711 | /* 40619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14712 | /* 40621 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14713 | /* 40623 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14714 | /* 40626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14715 | /* 40632 */ GIR_RootConstrainSelectedInstOperands, |
| 14716 | /* 40633 */ // GIR_Coverage, 1684, |
| 14717 | /* 40633 */ GIR_EraseRootFromParent_Done, |
| 14718 | /* 40634 */ // Label 1194: @40634 |
| 14719 | /* 40634 */ GIM_Reject, |
| 14720 | /* 40635 */ // Label 1188: @40635 |
| 14721 | /* 40635 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1195*/ GIMT_Encode4(40671), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1682 // |
| 14722 | /* 40642 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14723 | /* 40645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14724 | /* 40649 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14725 | /* 40653 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4095:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 14726 | /* 40653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv2i32), |
| 14727 | /* 40656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14728 | /* 40658 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14729 | /* 40660 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14730 | /* 40663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14731 | /* 40669 */ GIR_RootConstrainSelectedInstOperands, |
| 14732 | /* 40670 */ // GIR_Coverage, 1682, |
| 14733 | /* 40670 */ GIR_EraseRootFromParent_Done, |
| 14734 | /* 40671 */ // Label 1195: @40671 |
| 14735 | /* 40671 */ GIM_Reject, |
| 14736 | /* 40672 */ // Label 1189: @40672 |
| 14737 | /* 40672 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1196*/ GIMT_Encode4(40708), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1685 // |
| 14738 | /* 40679 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14739 | /* 40682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14740 | /* 40686 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14741 | /* 40690 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4095:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 14742 | /* 40690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i32), |
| 14743 | /* 40693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14744 | /* 40695 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14745 | /* 40697 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14746 | /* 40700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14747 | /* 40706 */ GIR_RootConstrainSelectedInstOperands, |
| 14748 | /* 40707 */ // GIR_Coverage, 1685, |
| 14749 | /* 40707 */ GIR_EraseRootFromParent_Done, |
| 14750 | /* 40708 */ // Label 1196: @40708 |
| 14751 | /* 40708 */ GIM_Reject, |
| 14752 | /* 40709 */ // Label 1190: @40709 |
| 14753 | /* 40709 */ GIM_Reject, |
| 14754 | /* 40710 */ // Label 1183: @40710 |
| 14755 | /* 40710 */ GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(40978), |
| 14756 | /* 40715 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg), |
| 14757 | /* 40720 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1204*/ GIMT_Encode4(40977), |
| 14758 | /* 40731 */ /*GILLT_v8s8*//*Label 1198*/ GIMT_Encode4(40755), |
| 14759 | /* 40735 */ /*GILLT_v16s8*//*Label 1199*/ GIMT_Encode4(40792), |
| 14760 | /* 40739 */ /*GILLT_v4s16*//*Label 1200*/ GIMT_Encode4(40829), |
| 14761 | /* 40743 */ /*GILLT_v8s16*//*Label 1201*/ GIMT_Encode4(40866), |
| 14762 | /* 40747 */ /*GILLT_v2s32*//*Label 1202*/ GIMT_Encode4(40903), |
| 14763 | /* 40751 */ /*GILLT_v4s32*//*Label 1203*/ GIMT_Encode4(40940), |
| 14764 | /* 40755 */ // Label 1198: @40755 |
| 14765 | /* 40755 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1205*/ GIMT_Encode4(40791), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1696 // |
| 14766 | /* 40762 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 14767 | /* 40765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14768 | /* 40769 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14769 | /* 40773 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4101:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQNEGv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 14770 | /* 40773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i8), |
| 14771 | /* 40776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14772 | /* 40778 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14773 | /* 40780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14774 | /* 40783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14775 | /* 40789 */ GIR_RootConstrainSelectedInstOperands, |
| 14776 | /* 40790 */ // GIR_Coverage, 1696, |
| 14777 | /* 40790 */ GIR_EraseRootFromParent_Done, |
| 14778 | /* 40791 */ // Label 1205: @40791 |
| 14779 | /* 40791 */ GIM_Reject, |
| 14780 | /* 40792 */ // Label 1199: @40792 |
| 14781 | /* 40792 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1206*/ GIMT_Encode4(40828), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1699 // |
| 14782 | /* 40799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 14783 | /* 40802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14784 | /* 40806 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14785 | /* 40810 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4101:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQNEGv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 14786 | /* 40810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv16i8), |
| 14787 | /* 40813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14788 | /* 40815 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14789 | /* 40817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14790 | /* 40820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14791 | /* 40826 */ GIR_RootConstrainSelectedInstOperands, |
| 14792 | /* 40827 */ // GIR_Coverage, 1699, |
| 14793 | /* 40827 */ GIR_EraseRootFromParent_Done, |
| 14794 | /* 40828 */ // Label 1206: @40828 |
| 14795 | /* 40828 */ GIM_Reject, |
| 14796 | /* 40829 */ // Label 1200: @40829 |
| 14797 | /* 40829 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1207*/ GIMT_Encode4(40865), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1697 // |
| 14798 | /* 40836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 14799 | /* 40839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14800 | /* 40843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14801 | /* 40847 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4101:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQNEGv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 14802 | /* 40847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i16), |
| 14803 | /* 40850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14804 | /* 40852 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14805 | /* 40854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14806 | /* 40857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14807 | /* 40863 */ GIR_RootConstrainSelectedInstOperands, |
| 14808 | /* 40864 */ // GIR_Coverage, 1697, |
| 14809 | /* 40864 */ GIR_EraseRootFromParent_Done, |
| 14810 | /* 40865 */ // Label 1207: @40865 |
| 14811 | /* 40865 */ GIM_Reject, |
| 14812 | /* 40866 */ // Label 1201: @40866 |
| 14813 | /* 40866 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1208*/ GIMT_Encode4(40902), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1700 // |
| 14814 | /* 40873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14815 | /* 40876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14816 | /* 40880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14817 | /* 40884 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4101:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQNEGv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 14818 | /* 40884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i16), |
| 14819 | /* 40887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14820 | /* 40889 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14821 | /* 40891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14822 | /* 40894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14823 | /* 40900 */ GIR_RootConstrainSelectedInstOperands, |
| 14824 | /* 40901 */ // GIR_Coverage, 1700, |
| 14825 | /* 40901 */ GIR_EraseRootFromParent_Done, |
| 14826 | /* 40902 */ // Label 1208: @40902 |
| 14827 | /* 40902 */ GIM_Reject, |
| 14828 | /* 40903 */ // Label 1202: @40903 |
| 14829 | /* 40903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1209*/ GIMT_Encode4(40939), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1698 // |
| 14830 | /* 40910 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 14831 | /* 40913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14832 | /* 40917 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14833 | /* 40921 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4101:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQNEGv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 14834 | /* 40921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv2i32), |
| 14835 | /* 40924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14836 | /* 40926 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14837 | /* 40928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14838 | /* 40931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14839 | /* 40937 */ GIR_RootConstrainSelectedInstOperands, |
| 14840 | /* 40938 */ // GIR_Coverage, 1698, |
| 14841 | /* 40938 */ GIR_EraseRootFromParent_Done, |
| 14842 | /* 40939 */ // Label 1209: @40939 |
| 14843 | /* 40939 */ GIM_Reject, |
| 14844 | /* 40940 */ // Label 1203: @40940 |
| 14845 | /* 40940 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1210*/ GIMT_Encode4(40976), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1701 // |
| 14846 | /* 40947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14847 | /* 40950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14848 | /* 40954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14849 | /* 40958 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4101:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQNEGv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 14850 | /* 40958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i32), |
| 14851 | /* 40961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14852 | /* 40963 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14853 | /* 40965 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14854 | /* 40968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14855 | /* 40974 */ GIR_RootConstrainSelectedInstOperands, |
| 14856 | /* 40975 */ // GIR_Coverage, 1701, |
| 14857 | /* 40975 */ GIR_EraseRootFromParent_Done, |
| 14858 | /* 40976 */ // Label 1210: @40976 |
| 14859 | /* 40976 */ GIM_Reject, |
| 14860 | /* 40977 */ // Label 1204: @40977 |
| 14861 | /* 40977 */ GIM_Reject, |
| 14862 | /* 40978 */ // Label 1197: @40978 |
| 14863 | /* 40978 */ GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(41131), |
| 14864 | /* 40983 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns), |
| 14865 | /* 40988 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1215*/ GIMT_Encode4(41130), |
| 14866 | /* 40999 */ /*GILLT_v8s8*//*Label 1212*/ GIMT_Encode4(41019), GIMT_Encode4(0), |
| 14867 | /* 41007 */ /*GILLT_v4s16*//*Label 1213*/ GIMT_Encode4(41056), GIMT_Encode4(0), |
| 14868 | /* 41015 */ /*GILLT_v2s32*//*Label 1214*/ GIMT_Encode4(41093), |
| 14869 | /* 41019 */ // Label 1212: @41019 |
| 14870 | /* 41019 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1216*/ GIMT_Encode4(41055), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1751 // |
| 14871 | /* 41026 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14872 | /* 41029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14873 | /* 41033 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14874 | /* 41037 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4098:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 14875 | /* 41037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv8i8), |
| 14876 | /* 41040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14877 | /* 41042 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14878 | /* 41044 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14879 | /* 41047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14880 | /* 41053 */ GIR_RootConstrainSelectedInstOperands, |
| 14881 | /* 41054 */ // GIR_Coverage, 1751, |
| 14882 | /* 41054 */ GIR_EraseRootFromParent_Done, |
| 14883 | /* 41055 */ // Label 1216: @41055 |
| 14884 | /* 41055 */ GIM_Reject, |
| 14885 | /* 41056 */ // Label 1213: @41056 |
| 14886 | /* 41056 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1217*/ GIMT_Encode4(41092), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1752 // |
| 14887 | /* 41063 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14888 | /* 41066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14889 | /* 41070 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14890 | /* 41074 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4098:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 14891 | /* 41074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv4i16), |
| 14892 | /* 41077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14893 | /* 41079 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14894 | /* 41081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14895 | /* 41084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14896 | /* 41090 */ GIR_RootConstrainSelectedInstOperands, |
| 14897 | /* 41091 */ // GIR_Coverage, 1752, |
| 14898 | /* 41091 */ GIR_EraseRootFromParent_Done, |
| 14899 | /* 41092 */ // Label 1217: @41092 |
| 14900 | /* 41092 */ GIM_Reject, |
| 14901 | /* 41093 */ // Label 1214: @41093 |
| 14902 | /* 41093 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1218*/ GIMT_Encode4(41129), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1753 // |
| 14903 | /* 41100 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 14904 | /* 41103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14905 | /* 41107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14906 | /* 41111 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4098:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 14907 | /* 41111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv2i32), |
| 14908 | /* 41114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14909 | /* 41116 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14910 | /* 41118 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14911 | /* 41121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14912 | /* 41127 */ GIR_RootConstrainSelectedInstOperands, |
| 14913 | /* 41128 */ // GIR_Coverage, 1753, |
| 14914 | /* 41128 */ GIR_EraseRootFromParent_Done, |
| 14915 | /* 41129 */ // Label 1218: @41129 |
| 14916 | /* 41129 */ GIM_Reject, |
| 14917 | /* 41130 */ // Label 1215: @41130 |
| 14918 | /* 41130 */ GIM_Reject, |
| 14919 | /* 41131 */ // Label 1211: @41131 |
| 14920 | /* 41131 */ GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(41284), |
| 14921 | /* 41136 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu), |
| 14922 | /* 41141 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1223*/ GIMT_Encode4(41283), |
| 14923 | /* 41152 */ /*GILLT_v8s8*//*Label 1220*/ GIMT_Encode4(41172), GIMT_Encode4(0), |
| 14924 | /* 41160 */ /*GILLT_v4s16*//*Label 1221*/ GIMT_Encode4(41209), GIMT_Encode4(0), |
| 14925 | /* 41168 */ /*GILLT_v2s32*//*Label 1222*/ GIMT_Encode4(41246), |
| 14926 | /* 41172 */ // Label 1220: @41172 |
| 14927 | /* 41172 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1224*/ GIMT_Encode4(41208), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1754 // |
| 14928 | /* 41179 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14929 | /* 41182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14930 | /* 41186 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14931 | /* 41190 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4100:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 14932 | /* 41190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv8i8), |
| 14933 | /* 41193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14934 | /* 41195 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14935 | /* 41197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14936 | /* 41200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14937 | /* 41206 */ GIR_RootConstrainSelectedInstOperands, |
| 14938 | /* 41207 */ // GIR_Coverage, 1754, |
| 14939 | /* 41207 */ GIR_EraseRootFromParent_Done, |
| 14940 | /* 41208 */ // Label 1224: @41208 |
| 14941 | /* 41208 */ GIM_Reject, |
| 14942 | /* 41209 */ // Label 1221: @41209 |
| 14943 | /* 41209 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1225*/ GIMT_Encode4(41245), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1755 // |
| 14944 | /* 41216 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 14945 | /* 41219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14946 | /* 41223 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14947 | /* 41227 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4100:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 14948 | /* 41227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv4i16), |
| 14949 | /* 41230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14950 | /* 41232 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14951 | /* 41234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14952 | /* 41237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14953 | /* 41243 */ GIR_RootConstrainSelectedInstOperands, |
| 14954 | /* 41244 */ // GIR_Coverage, 1755, |
| 14955 | /* 41244 */ GIR_EraseRootFromParent_Done, |
| 14956 | /* 41245 */ // Label 1225: @41245 |
| 14957 | /* 41245 */ GIM_Reject, |
| 14958 | /* 41246 */ // Label 1222: @41246 |
| 14959 | /* 41246 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1226*/ GIMT_Encode4(41282), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1756 // |
| 14960 | /* 41253 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 14961 | /* 41256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14962 | /* 41260 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14963 | /* 41264 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4100:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 14964 | /* 41264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv2i32), |
| 14965 | /* 41267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14966 | /* 41269 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14967 | /* 41271 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14968 | /* 41274 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14969 | /* 41280 */ GIR_RootConstrainSelectedInstOperands, |
| 14970 | /* 41281 */ // GIR_Coverage, 1756, |
| 14971 | /* 41281 */ GIR_EraseRootFromParent_Done, |
| 14972 | /* 41282 */ // Label 1226: @41282 |
| 14973 | /* 41282 */ GIM_Reject, |
| 14974 | /* 41283 */ // Label 1223: @41283 |
| 14975 | /* 41283 */ GIM_Reject, |
| 14976 | /* 41284 */ // Label 1219: @41284 |
| 14977 | /* 41284 */ GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(41437), |
| 14978 | /* 41289 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu), |
| 14979 | /* 41294 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1231*/ GIMT_Encode4(41436), |
| 14980 | /* 41305 */ /*GILLT_v8s8*//*Label 1228*/ GIMT_Encode4(41325), GIMT_Encode4(0), |
| 14981 | /* 41313 */ /*GILLT_v4s16*//*Label 1229*/ GIMT_Encode4(41362), GIMT_Encode4(0), |
| 14982 | /* 41321 */ /*GILLT_v2s32*//*Label 1230*/ GIMT_Encode4(41399), |
| 14983 | /* 41325 */ // Label 1228: @41325 |
| 14984 | /* 41325 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1232*/ GIMT_Encode4(41361), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1757 // |
| 14985 | /* 41332 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 14986 | /* 41335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 14987 | /* 41339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 14988 | /* 41343 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4099:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 14989 | /* 41343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv8i8), |
| 14990 | /* 41346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 14991 | /* 41348 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 14992 | /* 41350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 14993 | /* 41353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 14994 | /* 41359 */ GIR_RootConstrainSelectedInstOperands, |
| 14995 | /* 41360 */ // GIR_Coverage, 1757, |
| 14996 | /* 41360 */ GIR_EraseRootFromParent_Done, |
| 14997 | /* 41361 */ // Label 1232: @41361 |
| 14998 | /* 41361 */ GIM_Reject, |
| 14999 | /* 41362 */ // Label 1229: @41362 |
| 15000 | /* 41362 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1233*/ GIMT_Encode4(41398), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1758 // |
| 15001 | /* 41369 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15002 | /* 41372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15003 | /* 41376 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15004 | /* 41380 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4099:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 15005 | /* 41380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv4i16), |
| 15006 | /* 41383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15007 | /* 41385 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15008 | /* 41387 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15009 | /* 41390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15010 | /* 41396 */ GIR_RootConstrainSelectedInstOperands, |
| 15011 | /* 41397 */ // GIR_Coverage, 1758, |
| 15012 | /* 41397 */ GIR_EraseRootFromParent_Done, |
| 15013 | /* 41398 */ // Label 1233: @41398 |
| 15014 | /* 41398 */ GIM_Reject, |
| 15015 | /* 41399 */ // Label 1230: @41399 |
| 15016 | /* 41399 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1234*/ GIMT_Encode4(41435), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1759 // |
| 15017 | /* 41406 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 15018 | /* 41409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15019 | /* 41413 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15020 | /* 41417 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4099:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 15021 | /* 41417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv2i32), |
| 15022 | /* 41420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15023 | /* 41422 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15024 | /* 41424 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15025 | /* 41427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15026 | /* 41433 */ GIR_RootConstrainSelectedInstOperands, |
| 15027 | /* 41434 */ // GIR_Coverage, 1759, |
| 15028 | /* 41434 */ GIR_EraseRootFromParent_Done, |
| 15029 | /* 41435 */ // Label 1234: @41435 |
| 15030 | /* 41435 */ GIM_Reject, |
| 15031 | /* 41436 */ // Label 1231: @41436 |
| 15032 | /* 41436 */ GIM_Reject, |
| 15033 | /* 41437 */ // Label 1227: @41437 |
| 15034 | /* 41437 */ GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(41523), |
| 15035 | /* 41442 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 15036 | /* 41447 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1238*/ GIMT_Encode4(41522), |
| 15037 | /* 41458 */ /*GILLT_v2s32*//*Label 1236*/ GIMT_Encode4(41466), |
| 15038 | /* 41462 */ /*GILLT_v4s32*//*Label 1237*/ GIMT_Encode4(41494), |
| 15039 | /* 41466 */ // Label 1236: @41466 |
| 15040 | /* 41466 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1239*/ GIMT_Encode4(41493), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1782 // |
| 15041 | /* 41473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15042 | /* 41476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15043 | /* 41480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15044 | /* 41484 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4043:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15045 | /* 41484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDf), |
| 15046 | /* 41487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15047 | /* 41489 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15048 | /* 41491 */ GIR_RootConstrainSelectedInstOperands, |
| 15049 | /* 41492 */ // GIR_Coverage, 1782, |
| 15050 | /* 41492 */ GIR_EraseRootFromParent_Done, |
| 15051 | /* 41493 */ // Label 1239: @41493 |
| 15052 | /* 41493 */ GIM_Reject, |
| 15053 | /* 41494 */ // Label 1237: @41494 |
| 15054 | /* 41494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1240*/ GIMT_Encode4(41521), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1783 // |
| 15055 | /* 41501 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15056 | /* 41504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15057 | /* 41508 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15058 | /* 41512 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4043:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15059 | /* 41512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQf), |
| 15060 | /* 41515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15061 | /* 41517 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15062 | /* 41519 */ GIR_RootConstrainSelectedInstOperands, |
| 15063 | /* 41520 */ // GIR_Coverage, 1783, |
| 15064 | /* 41520 */ GIR_EraseRootFromParent_Done, |
| 15065 | /* 41521 */ // Label 1240: @41521 |
| 15066 | /* 41521 */ GIM_Reject, |
| 15067 | /* 41522 */ // Label 1238: @41522 |
| 15068 | /* 41522 */ GIM_Reject, |
| 15069 | /* 41523 */ // Label 1235: @41523 |
| 15070 | /* 41523 */ GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(41609), |
| 15071 | /* 41528 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 15072 | /* 41533 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1244*/ GIMT_Encode4(41608), |
| 15073 | /* 41544 */ /*GILLT_v2s32*//*Label 1242*/ GIMT_Encode4(41552), |
| 15074 | /* 41548 */ /*GILLT_v4s32*//*Label 1243*/ GIMT_Encode4(41580), |
| 15075 | /* 41552 */ // Label 1242: @41552 |
| 15076 | /* 41552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1245*/ GIMT_Encode4(41579), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1784 // |
| 15077 | /* 41559 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15078 | /* 41562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15079 | /* 41566 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15080 | /* 41570 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4044:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15081 | /* 41570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDf), |
| 15082 | /* 41573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15083 | /* 41575 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15084 | /* 41577 */ GIR_RootConstrainSelectedInstOperands, |
| 15085 | /* 41578 */ // GIR_Coverage, 1784, |
| 15086 | /* 41578 */ GIR_EraseRootFromParent_Done, |
| 15087 | /* 41579 */ // Label 1245: @41579 |
| 15088 | /* 41579 */ GIM_Reject, |
| 15089 | /* 41580 */ // Label 1243: @41580 |
| 15090 | /* 41580 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1246*/ GIMT_Encode4(41607), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1785 // |
| 15091 | /* 41587 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15092 | /* 41590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15093 | /* 41594 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15094 | /* 41598 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4044:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15095 | /* 41598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQf), |
| 15096 | /* 41601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15097 | /* 41603 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15098 | /* 41605 */ GIR_RootConstrainSelectedInstOperands, |
| 15099 | /* 41606 */ // GIR_Coverage, 1785, |
| 15100 | /* 41606 */ GIR_EraseRootFromParent_Done, |
| 15101 | /* 41607 */ // Label 1246: @41607 |
| 15102 | /* 41607 */ GIM_Reject, |
| 15103 | /* 41608 */ // Label 1244: @41608 |
| 15104 | /* 41608 */ GIM_Reject, |
| 15105 | /* 41609 */ // Label 1241: @41609 |
| 15106 | /* 41609 */ GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(41695), |
| 15107 | /* 41614 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas), |
| 15108 | /* 41619 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1250*/ GIMT_Encode4(41694), |
| 15109 | /* 41630 */ /*GILLT_v4s16*//*Label 1248*/ GIMT_Encode4(41638), |
| 15110 | /* 41634 */ /*GILLT_v8s16*//*Label 1249*/ GIMT_Encode4(41666), |
| 15111 | /* 41638 */ // Label 1248: @41638 |
| 15112 | /* 41638 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1251*/ GIMT_Encode4(41665), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1786 // |
| 15113 | /* 41645 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15114 | /* 41648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15115 | /* 41652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15116 | /* 41656 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4043:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15117 | /* 41656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDh), |
| 15118 | /* 41659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15119 | /* 41661 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15120 | /* 41663 */ GIR_RootConstrainSelectedInstOperands, |
| 15121 | /* 41664 */ // GIR_Coverage, 1786, |
| 15122 | /* 41664 */ GIR_EraseRootFromParent_Done, |
| 15123 | /* 41665 */ // Label 1251: @41665 |
| 15124 | /* 41665 */ GIM_Reject, |
| 15125 | /* 41666 */ // Label 1249: @41666 |
| 15126 | /* 41666 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1252*/ GIMT_Encode4(41693), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1787 // |
| 15127 | /* 41673 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15128 | /* 41676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15129 | /* 41680 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15130 | /* 41684 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4043:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15131 | /* 41684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQh), |
| 15132 | /* 41687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15133 | /* 41689 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15134 | /* 41691 */ GIR_RootConstrainSelectedInstOperands, |
| 15135 | /* 41692 */ // GIR_Coverage, 1787, |
| 15136 | /* 41692 */ GIR_EraseRootFromParent_Done, |
| 15137 | /* 41693 */ // Label 1252: @41693 |
| 15138 | /* 41693 */ GIM_Reject, |
| 15139 | /* 41694 */ // Label 1250: @41694 |
| 15140 | /* 41694 */ GIM_Reject, |
| 15141 | /* 41695 */ // Label 1247: @41695 |
| 15142 | /* 41695 */ GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(41781), |
| 15143 | /* 41700 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau), |
| 15144 | /* 41705 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1256*/ GIMT_Encode4(41780), |
| 15145 | /* 41716 */ /*GILLT_v4s16*//*Label 1254*/ GIMT_Encode4(41724), |
| 15146 | /* 41720 */ /*GILLT_v8s16*//*Label 1255*/ GIMT_Encode4(41752), |
| 15147 | /* 41724 */ // Label 1254: @41724 |
| 15148 | /* 41724 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1257*/ GIMT_Encode4(41751), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1788 // |
| 15149 | /* 41731 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15150 | /* 41734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15151 | /* 41738 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15152 | /* 41742 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4044:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15153 | /* 41742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDh), |
| 15154 | /* 41745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15155 | /* 41747 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15156 | /* 41749 */ GIR_RootConstrainSelectedInstOperands, |
| 15157 | /* 41750 */ // GIR_Coverage, 1788, |
| 15158 | /* 41750 */ GIR_EraseRootFromParent_Done, |
| 15159 | /* 41751 */ // Label 1257: @41751 |
| 15160 | /* 41751 */ GIM_Reject, |
| 15161 | /* 41752 */ // Label 1255: @41752 |
| 15162 | /* 41752 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1258*/ GIMT_Encode4(41779), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1789 // |
| 15163 | /* 41759 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15164 | /* 41762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15165 | /* 41766 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15166 | /* 41770 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4044:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15167 | /* 41770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQh), |
| 15168 | /* 41773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15169 | /* 41775 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15170 | /* 41777 */ GIR_RootConstrainSelectedInstOperands, |
| 15171 | /* 41778 */ // GIR_Coverage, 1789, |
| 15172 | /* 41778 */ GIR_EraseRootFromParent_Done, |
| 15173 | /* 41779 */ // Label 1258: @41779 |
| 15174 | /* 41779 */ GIM_Reject, |
| 15175 | /* 41780 */ // Label 1256: @41780 |
| 15176 | /* 41780 */ GIM_Reject, |
| 15177 | /* 41781 */ // Label 1253: @41781 |
| 15178 | /* 41781 */ GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(41867), |
| 15179 | /* 41786 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 15180 | /* 41791 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1262*/ GIMT_Encode4(41866), |
| 15181 | /* 41802 */ /*GILLT_v2s32*//*Label 1260*/ GIMT_Encode4(41810), |
| 15182 | /* 41806 */ /*GILLT_v4s32*//*Label 1261*/ GIMT_Encode4(41838), |
| 15183 | /* 41810 */ // Label 1260: @41810 |
| 15184 | /* 41810 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1263*/ GIMT_Encode4(41837), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1790 // |
| 15185 | /* 41817 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15186 | /* 41820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15187 | /* 41824 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15188 | /* 41828 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4055:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15189 | /* 41828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDf), |
| 15190 | /* 41831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15191 | /* 41833 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15192 | /* 41835 */ GIR_RootConstrainSelectedInstOperands, |
| 15193 | /* 41836 */ // GIR_Coverage, 1790, |
| 15194 | /* 41836 */ GIR_EraseRootFromParent_Done, |
| 15195 | /* 41837 */ // Label 1263: @41837 |
| 15196 | /* 41837 */ GIM_Reject, |
| 15197 | /* 41838 */ // Label 1261: @41838 |
| 15198 | /* 41838 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1264*/ GIMT_Encode4(41865), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1791 // |
| 15199 | /* 41845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15200 | /* 41848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15201 | /* 41852 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15202 | /* 41856 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4055:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15203 | /* 41856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQf), |
| 15204 | /* 41859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15205 | /* 41861 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15206 | /* 41863 */ GIR_RootConstrainSelectedInstOperands, |
| 15207 | /* 41864 */ // GIR_Coverage, 1791, |
| 15208 | /* 41864 */ GIR_EraseRootFromParent_Done, |
| 15209 | /* 41865 */ // Label 1264: @41865 |
| 15210 | /* 41865 */ GIM_Reject, |
| 15211 | /* 41866 */ // Label 1262: @41866 |
| 15212 | /* 41866 */ GIM_Reject, |
| 15213 | /* 41867 */ // Label 1259: @41867 |
| 15214 | /* 41867 */ GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(41953), |
| 15215 | /* 41872 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 15216 | /* 41877 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1268*/ GIMT_Encode4(41952), |
| 15217 | /* 41888 */ /*GILLT_v2s32*//*Label 1266*/ GIMT_Encode4(41896), |
| 15218 | /* 41892 */ /*GILLT_v4s32*//*Label 1267*/ GIMT_Encode4(41924), |
| 15219 | /* 41896 */ // Label 1266: @41896 |
| 15220 | /* 41896 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1269*/ GIMT_Encode4(41923), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1792 // |
| 15221 | /* 41903 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15222 | /* 41906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15223 | /* 41910 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15224 | /* 41914 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4056:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15225 | /* 41914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDf), |
| 15226 | /* 41917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15227 | /* 41919 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15228 | /* 41921 */ GIR_RootConstrainSelectedInstOperands, |
| 15229 | /* 41922 */ // GIR_Coverage, 1792, |
| 15230 | /* 41922 */ GIR_EraseRootFromParent_Done, |
| 15231 | /* 41923 */ // Label 1269: @41923 |
| 15232 | /* 41923 */ GIM_Reject, |
| 15233 | /* 41924 */ // Label 1267: @41924 |
| 15234 | /* 41924 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1270*/ GIMT_Encode4(41951), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1793 // |
| 15235 | /* 41931 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15236 | /* 41934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15237 | /* 41938 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15238 | /* 41942 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4056:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15239 | /* 41942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQf), |
| 15240 | /* 41945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15241 | /* 41947 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15242 | /* 41949 */ GIR_RootConstrainSelectedInstOperands, |
| 15243 | /* 41950 */ // GIR_Coverage, 1793, |
| 15244 | /* 41950 */ GIR_EraseRootFromParent_Done, |
| 15245 | /* 41951 */ // Label 1270: @41951 |
| 15246 | /* 41951 */ GIM_Reject, |
| 15247 | /* 41952 */ // Label 1268: @41952 |
| 15248 | /* 41952 */ GIM_Reject, |
| 15249 | /* 41953 */ // Label 1265: @41953 |
| 15250 | /* 41953 */ GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(42039), |
| 15251 | /* 41958 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns), |
| 15252 | /* 41963 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1274*/ GIMT_Encode4(42038), |
| 15253 | /* 41974 */ /*GILLT_v4s16*//*Label 1272*/ GIMT_Encode4(41982), |
| 15254 | /* 41978 */ /*GILLT_v8s16*//*Label 1273*/ GIMT_Encode4(42010), |
| 15255 | /* 41982 */ // Label 1272: @41982 |
| 15256 | /* 41982 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1275*/ GIMT_Encode4(42009), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1794 // |
| 15257 | /* 41989 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15258 | /* 41992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15259 | /* 41996 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15260 | /* 42000 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4055:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15261 | /* 42000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDh), |
| 15262 | /* 42003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15263 | /* 42005 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15264 | /* 42007 */ GIR_RootConstrainSelectedInstOperands, |
| 15265 | /* 42008 */ // GIR_Coverage, 1794, |
| 15266 | /* 42008 */ GIR_EraseRootFromParent_Done, |
| 15267 | /* 42009 */ // Label 1275: @42009 |
| 15268 | /* 42009 */ GIM_Reject, |
| 15269 | /* 42010 */ // Label 1273: @42010 |
| 15270 | /* 42010 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1276*/ GIMT_Encode4(42037), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1795 // |
| 15271 | /* 42017 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15272 | /* 42020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15273 | /* 42024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15274 | /* 42028 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4055:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15275 | /* 42028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQh), |
| 15276 | /* 42031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15277 | /* 42033 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15278 | /* 42035 */ GIR_RootConstrainSelectedInstOperands, |
| 15279 | /* 42036 */ // GIR_Coverage, 1795, |
| 15280 | /* 42036 */ GIR_EraseRootFromParent_Done, |
| 15281 | /* 42037 */ // Label 1276: @42037 |
| 15282 | /* 42037 */ GIM_Reject, |
| 15283 | /* 42038 */ // Label 1274: @42038 |
| 15284 | /* 42038 */ GIM_Reject, |
| 15285 | /* 42039 */ // Label 1271: @42039 |
| 15286 | /* 42039 */ GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(42125), |
| 15287 | /* 42044 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu), |
| 15288 | /* 42049 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1280*/ GIMT_Encode4(42124), |
| 15289 | /* 42060 */ /*GILLT_v4s16*//*Label 1278*/ GIMT_Encode4(42068), |
| 15290 | /* 42064 */ /*GILLT_v8s16*//*Label 1279*/ GIMT_Encode4(42096), |
| 15291 | /* 42068 */ // Label 1278: @42068 |
| 15292 | /* 42068 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1281*/ GIMT_Encode4(42095), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1796 // |
| 15293 | /* 42075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15294 | /* 42078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15295 | /* 42082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15296 | /* 42086 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4056:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15297 | /* 42086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDh), |
| 15298 | /* 42089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15299 | /* 42091 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15300 | /* 42093 */ GIR_RootConstrainSelectedInstOperands, |
| 15301 | /* 42094 */ // GIR_Coverage, 1796, |
| 15302 | /* 42094 */ GIR_EraseRootFromParent_Done, |
| 15303 | /* 42095 */ // Label 1281: @42095 |
| 15304 | /* 42095 */ GIM_Reject, |
| 15305 | /* 42096 */ // Label 1279: @42096 |
| 15306 | /* 42096 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1282*/ GIMT_Encode4(42123), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1797 // |
| 15307 | /* 42103 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15308 | /* 42106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15309 | /* 42110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15310 | /* 42114 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4056:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15311 | /* 42114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQh), |
| 15312 | /* 42117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15313 | /* 42119 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15314 | /* 42121 */ GIR_RootConstrainSelectedInstOperands, |
| 15315 | /* 42122 */ // GIR_Coverage, 1797, |
| 15316 | /* 42122 */ GIR_EraseRootFromParent_Done, |
| 15317 | /* 42123 */ // Label 1282: @42123 |
| 15318 | /* 42123 */ GIM_Reject, |
| 15319 | /* 42124 */ // Label 1280: @42124 |
| 15320 | /* 42124 */ GIM_Reject, |
| 15321 | /* 42125 */ // Label 1277: @42125 |
| 15322 | /* 42125 */ GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(42211), |
| 15323 | /* 42130 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 15324 | /* 42135 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1286*/ GIMT_Encode4(42210), |
| 15325 | /* 42146 */ /*GILLT_v2s32*//*Label 1284*/ GIMT_Encode4(42154), |
| 15326 | /* 42150 */ /*GILLT_v4s32*//*Label 1285*/ GIMT_Encode4(42182), |
| 15327 | /* 42154 */ // Label 1284: @42154 |
| 15328 | /* 42154 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1287*/ GIMT_Encode4(42181), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1798 // |
| 15329 | /* 42161 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15330 | /* 42164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15331 | /* 42168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15332 | /* 42172 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4057:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15333 | /* 42172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDf), |
| 15334 | /* 42175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15335 | /* 42177 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15336 | /* 42179 */ GIR_RootConstrainSelectedInstOperands, |
| 15337 | /* 42180 */ // GIR_Coverage, 1798, |
| 15338 | /* 42180 */ GIR_EraseRootFromParent_Done, |
| 15339 | /* 42181 */ // Label 1287: @42181 |
| 15340 | /* 42181 */ GIM_Reject, |
| 15341 | /* 42182 */ // Label 1285: @42182 |
| 15342 | /* 42182 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1288*/ GIMT_Encode4(42209), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1799 // |
| 15343 | /* 42189 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15344 | /* 42192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15345 | /* 42196 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15346 | /* 42200 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4057:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15347 | /* 42200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQf), |
| 15348 | /* 42203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15349 | /* 42205 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15350 | /* 42207 */ GIR_RootConstrainSelectedInstOperands, |
| 15351 | /* 42208 */ // GIR_Coverage, 1799, |
| 15352 | /* 42208 */ GIR_EraseRootFromParent_Done, |
| 15353 | /* 42209 */ // Label 1288: @42209 |
| 15354 | /* 42209 */ GIM_Reject, |
| 15355 | /* 42210 */ // Label 1286: @42210 |
| 15356 | /* 42210 */ GIM_Reject, |
| 15357 | /* 42211 */ // Label 1283: @42211 |
| 15358 | /* 42211 */ GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(42297), |
| 15359 | /* 42216 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 15360 | /* 42221 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1292*/ GIMT_Encode4(42296), |
| 15361 | /* 42232 */ /*GILLT_v2s32*//*Label 1290*/ GIMT_Encode4(42240), |
| 15362 | /* 42236 */ /*GILLT_v4s32*//*Label 1291*/ GIMT_Encode4(42268), |
| 15363 | /* 42240 */ // Label 1290: @42240 |
| 15364 | /* 42240 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1293*/ GIMT_Encode4(42267), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1800 // |
| 15365 | /* 42247 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15366 | /* 42250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15367 | /* 42254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15368 | /* 42258 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4058:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15369 | /* 42258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDf), |
| 15370 | /* 42261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15371 | /* 42263 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15372 | /* 42265 */ GIR_RootConstrainSelectedInstOperands, |
| 15373 | /* 42266 */ // GIR_Coverage, 1800, |
| 15374 | /* 42266 */ GIR_EraseRootFromParent_Done, |
| 15375 | /* 42267 */ // Label 1293: @42267 |
| 15376 | /* 42267 */ GIM_Reject, |
| 15377 | /* 42268 */ // Label 1291: @42268 |
| 15378 | /* 42268 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1294*/ GIMT_Encode4(42295), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1801 // |
| 15379 | /* 42275 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15380 | /* 42278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15381 | /* 42282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15382 | /* 42286 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4058:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15383 | /* 42286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQf), |
| 15384 | /* 42289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15385 | /* 42291 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15386 | /* 42293 */ GIR_RootConstrainSelectedInstOperands, |
| 15387 | /* 42294 */ // GIR_Coverage, 1801, |
| 15388 | /* 42294 */ GIR_EraseRootFromParent_Done, |
| 15389 | /* 42295 */ // Label 1294: @42295 |
| 15390 | /* 42295 */ GIM_Reject, |
| 15391 | /* 42296 */ // Label 1292: @42296 |
| 15392 | /* 42296 */ GIM_Reject, |
| 15393 | /* 42297 */ // Label 1289: @42297 |
| 15394 | /* 42297 */ GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(42383), |
| 15395 | /* 42302 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps), |
| 15396 | /* 42307 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1298*/ GIMT_Encode4(42382), |
| 15397 | /* 42318 */ /*GILLT_v4s16*//*Label 1296*/ GIMT_Encode4(42326), |
| 15398 | /* 42322 */ /*GILLT_v8s16*//*Label 1297*/ GIMT_Encode4(42354), |
| 15399 | /* 42326 */ // Label 1296: @42326 |
| 15400 | /* 42326 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1299*/ GIMT_Encode4(42353), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1802 // |
| 15401 | /* 42333 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15402 | /* 42336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15403 | /* 42340 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15404 | /* 42344 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4057:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15405 | /* 42344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDh), |
| 15406 | /* 42347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15407 | /* 42349 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15408 | /* 42351 */ GIR_RootConstrainSelectedInstOperands, |
| 15409 | /* 42352 */ // GIR_Coverage, 1802, |
| 15410 | /* 42352 */ GIR_EraseRootFromParent_Done, |
| 15411 | /* 42353 */ // Label 1299: @42353 |
| 15412 | /* 42353 */ GIM_Reject, |
| 15413 | /* 42354 */ // Label 1297: @42354 |
| 15414 | /* 42354 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1300*/ GIMT_Encode4(42381), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1803 // |
| 15415 | /* 42361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15416 | /* 42364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15417 | /* 42368 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15418 | /* 42372 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4057:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15419 | /* 42372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQh), |
| 15420 | /* 42375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15421 | /* 42377 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15422 | /* 42379 */ GIR_RootConstrainSelectedInstOperands, |
| 15423 | /* 42380 */ // GIR_Coverage, 1803, |
| 15424 | /* 42380 */ GIR_EraseRootFromParent_Done, |
| 15425 | /* 42381 */ // Label 1300: @42381 |
| 15426 | /* 42381 */ GIM_Reject, |
| 15427 | /* 42382 */ // Label 1298: @42382 |
| 15428 | /* 42382 */ GIM_Reject, |
| 15429 | /* 42383 */ // Label 1295: @42383 |
| 15430 | /* 42383 */ GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(42469), |
| 15431 | /* 42388 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu), |
| 15432 | /* 42393 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1304*/ GIMT_Encode4(42468), |
| 15433 | /* 42404 */ /*GILLT_v4s16*//*Label 1302*/ GIMT_Encode4(42412), |
| 15434 | /* 42408 */ /*GILLT_v8s16*//*Label 1303*/ GIMT_Encode4(42440), |
| 15435 | /* 42412 */ // Label 1302: @42412 |
| 15436 | /* 42412 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1305*/ GIMT_Encode4(42439), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1804 // |
| 15437 | /* 42419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15438 | /* 42422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15439 | /* 42426 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15440 | /* 42430 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4058:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15441 | /* 42430 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDh), |
| 15442 | /* 42433 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15443 | /* 42435 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15444 | /* 42437 */ GIR_RootConstrainSelectedInstOperands, |
| 15445 | /* 42438 */ // GIR_Coverage, 1804, |
| 15446 | /* 42438 */ GIR_EraseRootFromParent_Done, |
| 15447 | /* 42439 */ // Label 1305: @42439 |
| 15448 | /* 42439 */ GIM_Reject, |
| 15449 | /* 42440 */ // Label 1303: @42440 |
| 15450 | /* 42440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1306*/ GIMT_Encode4(42467), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1805 // |
| 15451 | /* 42447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15452 | /* 42450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15453 | /* 42454 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15454 | /* 42458 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4058:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15455 | /* 42458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQh), |
| 15456 | /* 42461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15457 | /* 42463 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15458 | /* 42465 */ GIR_RootConstrainSelectedInstOperands, |
| 15459 | /* 42466 */ // GIR_Coverage, 1805, |
| 15460 | /* 42466 */ GIR_EraseRootFromParent_Done, |
| 15461 | /* 42467 */ // Label 1306: @42467 |
| 15462 | /* 42467 */ GIM_Reject, |
| 15463 | /* 42468 */ // Label 1304: @42468 |
| 15464 | /* 42468 */ GIM_Reject, |
| 15465 | /* 42469 */ // Label 1301: @42469 |
| 15466 | /* 42469 */ GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(42555), |
| 15467 | /* 42474 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 15468 | /* 42479 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1310*/ GIMT_Encode4(42554), |
| 15469 | /* 42490 */ /*GILLT_v2s32*//*Label 1308*/ GIMT_Encode4(42498), |
| 15470 | /* 42494 */ /*GILLT_v4s32*//*Label 1309*/ GIMT_Encode4(42526), |
| 15471 | /* 42498 */ // Label 1308: @42498 |
| 15472 | /* 42498 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1311*/ GIMT_Encode4(42525), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1806 // |
| 15473 | /* 42505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15474 | /* 42508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15475 | /* 42512 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15476 | /* 42516 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4053:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15477 | /* 42516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDf), |
| 15478 | /* 42519 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15479 | /* 42521 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15480 | /* 42523 */ GIR_RootConstrainSelectedInstOperands, |
| 15481 | /* 42524 */ // GIR_Coverage, 1806, |
| 15482 | /* 42524 */ GIR_EraseRootFromParent_Done, |
| 15483 | /* 42525 */ // Label 1311: @42525 |
| 15484 | /* 42525 */ GIM_Reject, |
| 15485 | /* 42526 */ // Label 1309: @42526 |
| 15486 | /* 42526 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1312*/ GIMT_Encode4(42553), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1807 // |
| 15487 | /* 42533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15488 | /* 42536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15489 | /* 42540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15490 | /* 42544 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4053:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15491 | /* 42544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQf), |
| 15492 | /* 42547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15493 | /* 42549 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15494 | /* 42551 */ GIR_RootConstrainSelectedInstOperands, |
| 15495 | /* 42552 */ // GIR_Coverage, 1807, |
| 15496 | /* 42552 */ GIR_EraseRootFromParent_Done, |
| 15497 | /* 42553 */ // Label 1312: @42553 |
| 15498 | /* 42553 */ GIM_Reject, |
| 15499 | /* 42554 */ // Label 1310: @42554 |
| 15500 | /* 42554 */ GIM_Reject, |
| 15501 | /* 42555 */ // Label 1307: @42555 |
| 15502 | /* 42555 */ GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(42641), |
| 15503 | /* 42560 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 15504 | /* 42565 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1316*/ GIMT_Encode4(42640), |
| 15505 | /* 42576 */ /*GILLT_v2s32*//*Label 1314*/ GIMT_Encode4(42584), |
| 15506 | /* 42580 */ /*GILLT_v4s32*//*Label 1315*/ GIMT_Encode4(42612), |
| 15507 | /* 42584 */ // Label 1314: @42584 |
| 15508 | /* 42584 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1317*/ GIMT_Encode4(42611), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1808 // |
| 15509 | /* 42591 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 15510 | /* 42594 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15511 | /* 42598 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15512 | /* 42602 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4054:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 15513 | /* 42602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDf), |
| 15514 | /* 42605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15515 | /* 42607 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15516 | /* 42609 */ GIR_RootConstrainSelectedInstOperands, |
| 15517 | /* 42610 */ // GIR_Coverage, 1808, |
| 15518 | /* 42610 */ GIR_EraseRootFromParent_Done, |
| 15519 | /* 42611 */ // Label 1317: @42611 |
| 15520 | /* 42611 */ GIM_Reject, |
| 15521 | /* 42612 */ // Label 1315: @42612 |
| 15522 | /* 42612 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1318*/ GIMT_Encode4(42639), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1809 // |
| 15523 | /* 42619 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15524 | /* 42622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15525 | /* 42626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15526 | /* 42630 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4054:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 15527 | /* 42630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQf), |
| 15528 | /* 42633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15529 | /* 42635 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15530 | /* 42637 */ GIR_RootConstrainSelectedInstOperands, |
| 15531 | /* 42638 */ // GIR_Coverage, 1809, |
| 15532 | /* 42638 */ GIR_EraseRootFromParent_Done, |
| 15533 | /* 42639 */ // Label 1318: @42639 |
| 15534 | /* 42639 */ GIM_Reject, |
| 15535 | /* 42640 */ // Label 1316: @42640 |
| 15536 | /* 42640 */ GIM_Reject, |
| 15537 | /* 42641 */ // Label 1313: @42641 |
| 15538 | /* 42641 */ GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(42727), |
| 15539 | /* 42646 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms), |
| 15540 | /* 42651 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1322*/ GIMT_Encode4(42726), |
| 15541 | /* 42662 */ /*GILLT_v4s16*//*Label 1320*/ GIMT_Encode4(42670), |
| 15542 | /* 42666 */ /*GILLT_v8s16*//*Label 1321*/ GIMT_Encode4(42698), |
| 15543 | /* 42670 */ // Label 1320: @42670 |
| 15544 | /* 42670 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1323*/ GIMT_Encode4(42697), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1810 // |
| 15545 | /* 42677 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15546 | /* 42680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15547 | /* 42684 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15548 | /* 42688 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4053:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15549 | /* 42688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDh), |
| 15550 | /* 42691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15551 | /* 42693 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15552 | /* 42695 */ GIR_RootConstrainSelectedInstOperands, |
| 15553 | /* 42696 */ // GIR_Coverage, 1810, |
| 15554 | /* 42696 */ GIR_EraseRootFromParent_Done, |
| 15555 | /* 42697 */ // Label 1323: @42697 |
| 15556 | /* 42697 */ GIM_Reject, |
| 15557 | /* 42698 */ // Label 1321: @42698 |
| 15558 | /* 42698 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1324*/ GIMT_Encode4(42725), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1811 // |
| 15559 | /* 42705 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15560 | /* 42708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15561 | /* 42712 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15562 | /* 42716 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4053:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15563 | /* 42716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQh), |
| 15564 | /* 42719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15565 | /* 42721 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15566 | /* 42723 */ GIR_RootConstrainSelectedInstOperands, |
| 15567 | /* 42724 */ // GIR_Coverage, 1811, |
| 15568 | /* 42724 */ GIR_EraseRootFromParent_Done, |
| 15569 | /* 42725 */ // Label 1324: @42725 |
| 15570 | /* 42725 */ GIM_Reject, |
| 15571 | /* 42726 */ // Label 1322: @42726 |
| 15572 | /* 42726 */ GIM_Reject, |
| 15573 | /* 42727 */ // Label 1319: @42727 |
| 15574 | /* 42727 */ GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(42813), |
| 15575 | /* 42732 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu), |
| 15576 | /* 42737 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1328*/ GIMT_Encode4(42812), |
| 15577 | /* 42748 */ /*GILLT_v4s16*//*Label 1326*/ GIMT_Encode4(42756), |
| 15578 | /* 42752 */ /*GILLT_v8s16*//*Label 1327*/ GIMT_Encode4(42784), |
| 15579 | /* 42756 */ // Label 1326: @42756 |
| 15580 | /* 42756 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1329*/ GIMT_Encode4(42783), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1812 // |
| 15581 | /* 42763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15582 | /* 42766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15583 | /* 42770 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15584 | /* 42774 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4054:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 15585 | /* 42774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDh), |
| 15586 | /* 42777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15587 | /* 42779 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15588 | /* 42781 */ GIR_RootConstrainSelectedInstOperands, |
| 15589 | /* 42782 */ // GIR_Coverage, 1812, |
| 15590 | /* 42782 */ GIR_EraseRootFromParent_Done, |
| 15591 | /* 42783 */ // Label 1329: @42783 |
| 15592 | /* 42783 */ GIM_Reject, |
| 15593 | /* 42784 */ // Label 1327: @42784 |
| 15594 | /* 42784 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1330*/ GIMT_Encode4(42811), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1813 // |
| 15595 | /* 42791 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15596 | /* 42794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15597 | /* 42798 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15598 | /* 42802 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4054:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 15599 | /* 42802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQh), |
| 15600 | /* 42805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15601 | /* 42807 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15602 | /* 42809 */ GIR_RootConstrainSelectedInstOperands, |
| 15603 | /* 42810 */ // GIR_Coverage, 1813, |
| 15604 | /* 42810 */ GIR_EraseRootFromParent_Done, |
| 15605 | /* 42811 */ // Label 1330: @42811 |
| 15606 | /* 42811 */ GIM_Reject, |
| 15607 | /* 42812 */ // Label 1328: @42812 |
| 15608 | /* 42812 */ GIM_Reject, |
| 15609 | /* 42813 */ // Label 1325: @42813 |
| 15610 | /* 42813 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1331*/ GIMT_Encode4(42857), GIMT_Encode2(GIFBS_HasFP16_HasNEON), // Rule ID 1830 // |
| 15611 | /* 42820 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2hf), |
| 15612 | /* 42825 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 15613 | /* 42828 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15614 | /* 42831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15615 | /* 42835 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15616 | /* 42839 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4049:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTf2h:{ *:[v4i16] } QPR:{ *:[v4f32] }:$Vm) |
| 15617 | /* 42839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h), |
| 15618 | /* 42842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15619 | /* 42844 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15620 | /* 42846 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15621 | /* 42849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15622 | /* 42855 */ GIR_RootConstrainSelectedInstOperands, |
| 15623 | /* 42856 */ // GIR_Coverage, 1830, |
| 15624 | /* 42856 */ GIR_EraseRootFromParent_Done, |
| 15625 | /* 42857 */ // Label 1331: @42857 |
| 15626 | /* 42857 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1332*/ GIMT_Encode4(42901), GIMT_Encode2(GIFBS_HasFP16_HasNEON), // Rule ID 1831 // |
| 15627 | /* 42864 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvthf2fp), |
| 15628 | /* 42869 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15629 | /* 42872 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 15630 | /* 42875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15631 | /* 42879 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 15632 | /* 42883 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4052:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4i16] }:$Vm) |
| 15633 | /* 42883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f), |
| 15634 | /* 42886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15635 | /* 42888 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15636 | /* 42890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15637 | /* 42893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15638 | /* 42899 */ GIR_RootConstrainSelectedInstOperands, |
| 15639 | /* 42900 */ // GIR_Coverage, 1831, |
| 15640 | /* 42900 */ GIR_EraseRootFromParent_Done, |
| 15641 | /* 42901 */ // Label 1332: @42901 |
| 15642 | /* 42901 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1333*/ GIMT_Encode4(42936), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1903 // |
| 15643 | /* 42908 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesimc), |
| 15644 | /* 42913 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 15645 | /* 42916 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15646 | /* 42919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15647 | /* 42923 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15648 | /* 42927 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4012:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESIMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 15649 | /* 42927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESIMC), |
| 15650 | /* 42930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15651 | /* 42932 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15652 | /* 42934 */ GIR_RootConstrainSelectedInstOperands, |
| 15653 | /* 42935 */ // GIR_Coverage, 1903, |
| 15654 | /* 42935 */ GIR_EraseRootFromParent_Done, |
| 15655 | /* 42936 */ // Label 1333: @42936 |
| 15656 | /* 42936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1334*/ GIMT_Encode4(42971), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1904 // |
| 15657 | /* 42943 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesmc), |
| 15658 | /* 42948 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 15659 | /* 42951 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 15660 | /* 42954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15661 | /* 42958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 15662 | /* 42962 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4013:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 15663 | /* 42962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESMC), |
| 15664 | /* 42965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 15665 | /* 42967 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 15666 | /* 42969 */ GIR_RootConstrainSelectedInstOperands, |
| 15667 | /* 42970 */ // GIR_Coverage, 1904, |
| 15668 | /* 42970 */ GIR_EraseRootFromParent_Done, |
| 15669 | /* 42971 */ // Label 1334: @42971 |
| 15670 | /* 42971 */ GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(43060), |
| 15671 | /* 42976 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16), |
| 15672 | /* 42981 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 15673 | /* 42984 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15674 | /* 42987 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1336*/ GIMT_Encode4(43023), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2039 // |
| 15675 | /* 42994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 15676 | /* 42998 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 15677 | /* 43002 */ // (intrinsic_wo_chain:{ *:[i32] } 4206:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (SXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 15678 | /* 43002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB16), |
| 15679 | /* 43005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15680 | /* 43007 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src |
| 15681 | /* 43009 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15682 | /* 43012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15683 | /* 43015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15684 | /* 43021 */ GIR_RootConstrainSelectedInstOperands, |
| 15685 | /* 43022 */ // GIR_Coverage, 2039, |
| 15686 | /* 43022 */ GIR_EraseRootFromParent_Done, |
| 15687 | /* 43023 */ // Label 1336: @43023 |
| 15688 | /* 43023 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1337*/ GIMT_Encode4(43059), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2293 // |
| 15689 | /* 43030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15690 | /* 43034 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15691 | /* 43038 */ // (intrinsic_wo_chain:{ *:[i32] } 4206:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (t2SXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 0:{ *:[i32] }) |
| 15692 | /* 43038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB16), |
| 15693 | /* 43041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 15694 | /* 43043 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15695 | /* 43045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15696 | /* 43048 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 15697 | /* 43051 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15698 | /* 43057 */ GIR_RootConstrainSelectedInstOperands, |
| 15699 | /* 43058 */ // GIR_Coverage, 2293, |
| 15700 | /* 43058 */ GIR_EraseRootFromParent_Done, |
| 15701 | /* 43059 */ // Label 1337: @43059 |
| 15702 | /* 43059 */ GIM_Reject, |
| 15703 | /* 43060 */ // Label 1335: @43060 |
| 15704 | /* 43060 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1338*/ GIMT_Encode4(43125), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4360 // |
| 15705 | /* 43067 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn), |
| 15706 | /* 43072 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15707 | /* 43075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15708 | /* 43078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15709 | /* 43082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15710 | /* 43086 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3972:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 15711 | /* 43086 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15712 | /* 43089 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15713 | /* 43093 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15714 | /* 43098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N), |
| 15715 | /* 43101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15716 | /* 43103 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15717 | /* 43105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15718 | /* 43108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15719 | /* 43114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15720 | /* 43120 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15721 | /* 43123 */ GIR_RootConstrainSelectedInstOperands, |
| 15722 | /* 43124 */ // GIR_Coverage, 4360, |
| 15723 | /* 43124 */ GIR_EraseRootFromParent_Done, |
| 15724 | /* 43125 */ // Label 1338: @43125 |
| 15725 | /* 43125 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1339*/ GIMT_Encode4(43190), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4364 // |
| 15726 | /* 43132 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintx), |
| 15727 | /* 43137 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15728 | /* 43140 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15729 | /* 43143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15730 | /* 43147 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15731 | /* 43151 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3976:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 15732 | /* 43151 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15733 | /* 43154 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15734 | /* 43158 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15735 | /* 43163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X), |
| 15736 | /* 43166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15737 | /* 43168 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15738 | /* 43170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15739 | /* 43173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15740 | /* 43179 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15741 | /* 43185 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15742 | /* 43188 */ GIR_RootConstrainSelectedInstOperands, |
| 15743 | /* 43189 */ // GIR_Coverage, 4364, |
| 15744 | /* 43189 */ GIR_EraseRootFromParent_Done, |
| 15745 | /* 43190 */ // Label 1339: @43190 |
| 15746 | /* 43190 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1340*/ GIMT_Encode4(43255), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4368 // |
| 15747 | /* 43197 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrinta), |
| 15748 | /* 43202 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15749 | /* 43205 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15750 | /* 43208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15751 | /* 43212 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15752 | /* 43216 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3968:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 15753 | /* 43216 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15754 | /* 43219 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15755 | /* 43223 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15756 | /* 43228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A), |
| 15757 | /* 43231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15758 | /* 43233 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15759 | /* 43235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15760 | /* 43238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15761 | /* 43244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15762 | /* 43250 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15763 | /* 43253 */ GIR_RootConstrainSelectedInstOperands, |
| 15764 | /* 43254 */ // GIR_Coverage, 4368, |
| 15765 | /* 43254 */ GIR_EraseRootFromParent_Done, |
| 15766 | /* 43255 */ // Label 1340: @43255 |
| 15767 | /* 43255 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1341*/ GIMT_Encode4(43320), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4372 // |
| 15768 | /* 43262 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintz), |
| 15769 | /* 43267 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15770 | /* 43270 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15771 | /* 43273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15772 | /* 43277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15773 | /* 43281 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3978:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 15774 | /* 43281 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15775 | /* 43284 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15776 | /* 43288 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15777 | /* 43293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z), |
| 15778 | /* 43296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15779 | /* 43298 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15780 | /* 43300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15781 | /* 43303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15782 | /* 43309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15783 | /* 43315 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15784 | /* 43318 */ GIR_RootConstrainSelectedInstOperands, |
| 15785 | /* 43319 */ // GIR_Coverage, 4372, |
| 15786 | /* 43319 */ GIR_EraseRootFromParent_Done, |
| 15787 | /* 43320 */ // Label 1341: @43320 |
| 15788 | /* 43320 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1342*/ GIMT_Encode4(43385), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4376 // |
| 15789 | /* 43327 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintm), |
| 15790 | /* 43332 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15791 | /* 43335 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15792 | /* 43338 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15793 | /* 43342 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15794 | /* 43346 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3970:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 15795 | /* 43346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15796 | /* 43349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15797 | /* 43353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15798 | /* 43358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M), |
| 15799 | /* 43361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15800 | /* 43363 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15801 | /* 43365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15802 | /* 43368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15803 | /* 43374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15804 | /* 43380 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15805 | /* 43383 */ GIR_RootConstrainSelectedInstOperands, |
| 15806 | /* 43384 */ // GIR_Coverage, 4376, |
| 15807 | /* 43384 */ GIR_EraseRootFromParent_Done, |
| 15808 | /* 43385 */ // Label 1342: @43385 |
| 15809 | /* 43385 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1343*/ GIMT_Encode4(43450), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4380 // |
| 15810 | /* 43392 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintp), |
| 15811 | /* 43397 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 15812 | /* 43400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 15813 | /* 43403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15814 | /* 43407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15815 | /* 43411 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3974:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 15816 | /* 43411 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15817 | /* 43414 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15818 | /* 43418 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15819 | /* 43423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P), |
| 15820 | /* 43426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15821 | /* 43428 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15822 | /* 43430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15823 | /* 43433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15824 | /* 43439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15825 | /* 43445 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15826 | /* 43448 */ GIR_RootConstrainSelectedInstOperands, |
| 15827 | /* 43449 */ // GIR_Coverage, 4380, |
| 15828 | /* 43449 */ GIR_EraseRootFromParent_Done, |
| 15829 | /* 43450 */ // Label 1343: @43450 |
| 15830 | /* 43450 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1344*/ GIMT_Encode4(43515), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4384 // |
| 15831 | /* 43457 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn), |
| 15832 | /* 43462 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15833 | /* 43465 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15834 | /* 43468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15835 | /* 43472 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15836 | /* 43476 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3972:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 15837 | /* 43476 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15838 | /* 43479 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15839 | /* 43483 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15840 | /* 43488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N), |
| 15841 | /* 43491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15842 | /* 43493 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15843 | /* 43495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15844 | /* 43498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15845 | /* 43504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15846 | /* 43510 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15847 | /* 43513 */ GIR_RootConstrainSelectedInstOperands, |
| 15848 | /* 43514 */ // GIR_Coverage, 4384, |
| 15849 | /* 43514 */ GIR_EraseRootFromParent_Done, |
| 15850 | /* 43515 */ // Label 1344: @43515 |
| 15851 | /* 43515 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1345*/ GIMT_Encode4(43580), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4388 // |
| 15852 | /* 43522 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintx), |
| 15853 | /* 43527 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15854 | /* 43530 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15855 | /* 43533 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15856 | /* 43537 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15857 | /* 43541 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3976:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 15858 | /* 43541 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15859 | /* 43544 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15860 | /* 43548 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15861 | /* 43553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X), |
| 15862 | /* 43556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15863 | /* 43558 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15864 | /* 43560 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15865 | /* 43563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15866 | /* 43569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15867 | /* 43575 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15868 | /* 43578 */ GIR_RootConstrainSelectedInstOperands, |
| 15869 | /* 43579 */ // GIR_Coverage, 4388, |
| 15870 | /* 43579 */ GIR_EraseRootFromParent_Done, |
| 15871 | /* 43580 */ // Label 1345: @43580 |
| 15872 | /* 43580 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1346*/ GIMT_Encode4(43645), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4392 // |
| 15873 | /* 43587 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrinta), |
| 15874 | /* 43592 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15875 | /* 43595 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15876 | /* 43598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15877 | /* 43602 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15878 | /* 43606 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3968:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 15879 | /* 43606 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15880 | /* 43609 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15881 | /* 43613 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15882 | /* 43618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A), |
| 15883 | /* 43621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15884 | /* 43623 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15885 | /* 43625 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15886 | /* 43628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15887 | /* 43634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15888 | /* 43640 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15889 | /* 43643 */ GIR_RootConstrainSelectedInstOperands, |
| 15890 | /* 43644 */ // GIR_Coverage, 4392, |
| 15891 | /* 43644 */ GIR_EraseRootFromParent_Done, |
| 15892 | /* 43645 */ // Label 1346: @43645 |
| 15893 | /* 43645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1347*/ GIMT_Encode4(43710), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4396 // |
| 15894 | /* 43652 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintz), |
| 15895 | /* 43657 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15896 | /* 43660 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15897 | /* 43663 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15898 | /* 43667 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15899 | /* 43671 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3978:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 15900 | /* 43671 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15901 | /* 43674 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15902 | /* 43678 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15903 | /* 43683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z), |
| 15904 | /* 43686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15905 | /* 43688 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15906 | /* 43690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15907 | /* 43693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15908 | /* 43699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15909 | /* 43705 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15910 | /* 43708 */ GIR_RootConstrainSelectedInstOperands, |
| 15911 | /* 43709 */ // GIR_Coverage, 4396, |
| 15912 | /* 43709 */ GIR_EraseRootFromParent_Done, |
| 15913 | /* 43710 */ // Label 1347: @43710 |
| 15914 | /* 43710 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1348*/ GIMT_Encode4(43775), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4400 // |
| 15915 | /* 43717 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintm), |
| 15916 | /* 43722 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15917 | /* 43725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15918 | /* 43728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15919 | /* 43732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15920 | /* 43736 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3970:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 15921 | /* 43736 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15922 | /* 43739 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15923 | /* 43743 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15924 | /* 43748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M), |
| 15925 | /* 43751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15926 | /* 43753 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15927 | /* 43755 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15928 | /* 43758 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15929 | /* 43764 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15930 | /* 43770 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15931 | /* 43773 */ GIR_RootConstrainSelectedInstOperands, |
| 15932 | /* 43774 */ // GIR_Coverage, 4400, |
| 15933 | /* 43774 */ GIR_EraseRootFromParent_Done, |
| 15934 | /* 43775 */ // Label 1348: @43775 |
| 15935 | /* 43775 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1349*/ GIMT_Encode4(43840), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4404 // |
| 15936 | /* 43782 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintp), |
| 15937 | /* 43787 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 15938 | /* 43790 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 15939 | /* 43793 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15940 | /* 43797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 15941 | /* 43801 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3974:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 15942 | /* 43801 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 15943 | /* 43804 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 15944 | /* 43808 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 15945 | /* 43813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P), |
| 15946 | /* 43816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 15947 | /* 43818 */ GIR_RootToRootCopy, /*OpIdx*/2, // val |
| 15948 | /* 43820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15949 | /* 43823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15950 | /* 43829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15951 | /* 43835 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 15952 | /* 43838 */ GIR_RootConstrainSelectedInstOperands, |
| 15953 | /* 43839 */ // GIR_Coverage, 4404, |
| 15954 | /* 43839 */ GIR_EraseRootFromParent_Done, |
| 15955 | /* 43840 */ // Label 1349: @43840 |
| 15956 | /* 43840 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1350*/ GIMT_Encode4(43890), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5390 // |
| 15957 | /* 43847 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp8), |
| 15958 | /* 43852 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s1, |
| 15959 | /* 43855 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15960 | /* 43858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 15961 | /* 43862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15962 | /* 43866 */ // (intrinsic_wo_chain:{ *:[v16i1] } 3891:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP8:{ *:[v16i1] } rGPR:{ *:[i32] }:$Rn) |
| 15963 | /* 43866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP8), |
| 15964 | /* 43869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 15965 | /* 43871 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15966 | /* 43873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15967 | /* 43876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15968 | /* 43882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15969 | /* 43888 */ GIR_RootConstrainSelectedInstOperands, |
| 15970 | /* 43889 */ // GIR_Coverage, 5390, |
| 15971 | /* 43889 */ GIR_EraseRootFromParent_Done, |
| 15972 | /* 43890 */ // Label 1350: @43890 |
| 15973 | /* 43890 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1351*/ GIMT_Encode4(43940), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5392 // |
| 15974 | /* 43897 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp16), |
| 15975 | /* 43902 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1, |
| 15976 | /* 43905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15977 | /* 43908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 15978 | /* 43912 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15979 | /* 43916 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3888:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP16:{ *:[v8i1] } rGPR:{ *:[i32] }:$Rn) |
| 15980 | /* 43916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP16), |
| 15981 | /* 43919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 15982 | /* 43921 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 15983 | /* 43923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15984 | /* 43926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15985 | /* 43932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 15986 | /* 43938 */ GIR_RootConstrainSelectedInstOperands, |
| 15987 | /* 43939 */ // GIR_Coverage, 5392, |
| 15988 | /* 43939 */ GIR_EraseRootFromParent_Done, |
| 15989 | /* 43940 */ // Label 1351: @43940 |
| 15990 | /* 43940 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1352*/ GIMT_Encode4(43990), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5394 // |
| 15991 | /* 43947 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp32), |
| 15992 | /* 43952 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1, |
| 15993 | /* 43955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 15994 | /* 43958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 15995 | /* 43962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 15996 | /* 43966 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3889:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP32:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn) |
| 15997 | /* 43966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP32), |
| 15998 | /* 43969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 15999 | /* 43971 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16000 | /* 43973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16001 | /* 43976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16002 | /* 43982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16003 | /* 43988 */ GIR_RootConstrainSelectedInstOperands, |
| 16004 | /* 43989 */ // GIR_Coverage, 5394, |
| 16005 | /* 43989 */ GIR_EraseRootFromParent_Done, |
| 16006 | /* 43990 */ // Label 1352: @43990 |
| 16007 | /* 43990 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1353*/ GIMT_Encode4(44040), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5396 // |
| 16008 | /* 43997 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp64), |
| 16009 | /* 44002 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s1, |
| 16010 | /* 44005 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16011 | /* 44008 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 16012 | /* 44012 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16013 | /* 44016 */ // (intrinsic_wo_chain:{ *:[v2i1] } 3890:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP64:{ *:[v2i1] } rGPR:{ *:[i32] }:$Rn) |
| 16014 | /* 44016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP64), |
| 16015 | /* 44019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 16016 | /* 44021 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16017 | /* 44023 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16018 | /* 44026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16019 | /* 44032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16020 | /* 44038 */ GIR_RootConstrainSelectedInstOperands, |
| 16021 | /* 44039 */ // GIR_Coverage, 5396, |
| 16022 | /* 44039 */ GIR_EraseRootFromParent_Done, |
| 16023 | /* 44040 */ // Label 1353: @44040 |
| 16024 | /* 44040 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1354*/ GIMT_Encode4(44085), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 599 // |
| 16025 | /* 44047 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tt), |
| 16026 | /* 44052 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16027 | /* 44055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16028 | /* 44059 */ // MIs[0] Rn |
| 16029 | /* 44059 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 16030 | /* 44063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16031 | /* 44067 */ // (intrinsic_wo_chain:{ *:[i32] } 3765:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 16032 | /* 44067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TT), |
| 16033 | /* 44070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 16034 | /* 44072 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16035 | /* 44074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16036 | /* 44077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16037 | /* 44083 */ GIR_RootConstrainSelectedInstOperands, |
| 16038 | /* 44084 */ // GIR_Coverage, 599, |
| 16039 | /* 44084 */ GIR_EraseRootFromParent_Done, |
| 16040 | /* 44085 */ // Label 1354: @44085 |
| 16041 | /* 44085 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1355*/ GIMT_Encode4(44130), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 600 // |
| 16042 | /* 44092 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttt), |
| 16043 | /* 44097 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16044 | /* 44100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16045 | /* 44104 */ // MIs[0] Rn |
| 16046 | /* 44104 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 16047 | /* 44108 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16048 | /* 44112 */ // (intrinsic_wo_chain:{ *:[i32] } 3768:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 16049 | /* 44112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTT), |
| 16050 | /* 44115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 16051 | /* 44117 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16052 | /* 44119 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16053 | /* 44122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16054 | /* 44128 */ GIR_RootConstrainSelectedInstOperands, |
| 16055 | /* 44129 */ // GIR_Coverage, 600, |
| 16056 | /* 44129 */ GIR_EraseRootFromParent_Done, |
| 16057 | /* 44130 */ // Label 1355: @44130 |
| 16058 | /* 44130 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1356*/ GIMT_Encode4(44175), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 601 // |
| 16059 | /* 44137 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tta), |
| 16060 | /* 44142 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16061 | /* 44145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16062 | /* 44149 */ // MIs[0] Rn |
| 16063 | /* 44149 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 16064 | /* 44153 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16065 | /* 44157 */ // (intrinsic_wo_chain:{ *:[i32] } 3766:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 16066 | /* 44157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTA), |
| 16067 | /* 44160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 16068 | /* 44162 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16069 | /* 44164 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16070 | /* 44167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16071 | /* 44173 */ GIR_RootConstrainSelectedInstOperands, |
| 16072 | /* 44174 */ // GIR_Coverage, 601, |
| 16073 | /* 44174 */ GIR_EraseRootFromParent_Done, |
| 16074 | /* 44175 */ // Label 1356: @44175 |
| 16075 | /* 44175 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1357*/ GIMT_Encode4(44220), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 602 // |
| 16076 | /* 44182 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttat), |
| 16077 | /* 44187 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16078 | /* 44190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16079 | /* 44194 */ // MIs[0] Rn |
| 16080 | /* 44194 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 16081 | /* 44198 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16082 | /* 44202 */ // (intrinsic_wo_chain:{ *:[i32] } 3767:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTAT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn) |
| 16083 | /* 44202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTAT), |
| 16084 | /* 44205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 16085 | /* 44207 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16086 | /* 44209 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16087 | /* 44212 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16088 | /* 44218 */ GIR_RootConstrainSelectedInstOperands, |
| 16089 | /* 44219 */ // GIR_Coverage, 602, |
| 16090 | /* 44219 */ GIR_EraseRootFromParent_Done, |
| 16091 | /* 44220 */ // Label 1357: @44220 |
| 16092 | /* 44220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1358*/ GIMT_Encode4(44373), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3079 // |
| 16093 | /* 44227 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1h), |
| 16094 | /* 44232 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16095 | /* 44235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16096 | /* 44238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 16097 | /* 44242 */ // (intrinsic_wo_chain:{ *:[i32] } 4020:{ *:[iPTR] }, i32:{ *:[i32] }:$Rn) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[f32] } (SHA1H:{ *:[v16i8] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$Rn, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }), GPR:{ *:[i32] }) |
| 16098 | /* 44242 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 16099 | /* 44245 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16100 | /* 44249 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16101 | /* 44254 */ GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/2, // Rn |
| 16102 | /* 44258 */ GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 16103 | /* 44263 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8, |
| 16104 | /* 44266 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16105 | /* 44270 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16106 | /* 44275 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 16107 | /* 44277 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8, |
| 16108 | /* 44280 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 16109 | /* 44284 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16110 | /* 44289 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 16111 | /* 44292 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4, |
| 16112 | /* 44295 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 16113 | /* 44298 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 16114 | /* 44303 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 16115 | /* 44308 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 16116 | /* 44313 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 16117 | /* 44316 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::SHA1H), |
| 16118 | /* 44320 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16119 | /* 44325 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 16120 | /* 44328 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 16121 | /* 44330 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 16122 | /* 44333 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16123 | /* 44337 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16124 | /* 44342 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 16125 | /* 44349 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 16126 | /* 44354 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::MQPRRegClassID), |
| 16127 | /* 44359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 16128 | /* 44362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 16129 | /* 44364 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16130 | /* 44367 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 16131 | /* 44372 */ // GIR_Coverage, 3079, |
| 16132 | /* 44372 */ GIR_EraseRootFromParent_Done, |
| 16133 | /* 44373 */ // Label 1358: @44373 |
| 16134 | /* 44373 */ GIM_Reject, |
| 16135 | /* 44374 */ // Label 1111: @44374 |
| 16136 | /* 44374 */ GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(67737), |
| 16137 | /* 44379 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 16138 | /* 44382 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1360*/ GIMT_Encode4(44438), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2311 // |
| 16139 | /* 44389 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16), |
| 16140 | /* 44394 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16141 | /* 44397 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16142 | /* 44400 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16143 | /* 44403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16144 | /* 44407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16145 | /* 44411 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16146 | /* 44415 */ // (intrinsic_wo_chain:{ *:[i32] } 4230:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 16147 | /* 44415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB16), |
| 16148 | /* 44418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16149 | /* 44420 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 16150 | /* 44422 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16151 | /* 44424 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16152 | /* 44427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16153 | /* 44430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16154 | /* 44436 */ GIR_RootConstrainSelectedInstOperands, |
| 16155 | /* 44437 */ // GIR_Coverage, 2311, |
| 16156 | /* 44437 */ GIR_EraseRootFromParent_Done, |
| 16157 | /* 44438 */ // Label 1360: @44438 |
| 16158 | /* 44438 */ GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(44626), |
| 16159 | /* 44443 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 16160 | /* 44448 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16161 | /* 44451 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16162 | /* 44454 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16163 | /* 44457 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1362*/ GIMT_Encode4(44541), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2076 // |
| 16164 | /* 44464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16165 | /* 44468 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16166 | /* 44472 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 16167 | /* 44476 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 16168 | /* 44480 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16169 | /* 44484 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16170 | /* 44489 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 16171 | /* 44493 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16172 | /* 44497 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 16173 | /* 44501 */ // MIs[2] Operand 1 |
| 16174 | /* 44501 */ // No operand predicates |
| 16175 | /* 44501 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3] |
| 16176 | /* 44505 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16177 | /* 44509 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 16178 | /* 44513 */ // MIs[3] Operand 1 |
| 16179 | /* 44513 */ // No operand predicates |
| 16180 | /* 44513 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 16181 | /* 44515 */ // (intrinsic_wo_chain:{ *:[i32] } 4225:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft) |
| 16182 | /* 44515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT), |
| 16183 | /* 44518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16184 | /* 44520 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos |
| 16185 | /* 44523 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 16186 | /* 44527 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft |
| 16187 | /* 44530 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16188 | /* 44533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16189 | /* 44539 */ GIR_RootConstrainSelectedInstOperands, |
| 16190 | /* 44540 */ // GIR_Coverage, 2076, |
| 16191 | /* 44540 */ GIR_EraseRootFromParent_Done, |
| 16192 | /* 44541 */ // Label 1362: @44541 |
| 16193 | /* 44541 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1363*/ GIMT_Encode4(44625), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2348 // |
| 16194 | /* 44548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16195 | /* 44552 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16196 | /* 44556 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 16197 | /* 44560 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 16198 | /* 44564 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16199 | /* 44568 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16200 | /* 44573 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 16201 | /* 44577 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16202 | /* 44581 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 16203 | /* 44585 */ // MIs[2] Operand 1 |
| 16204 | /* 44585 */ // No operand predicates |
| 16205 | /* 44585 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3] |
| 16206 | /* 44589 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 16207 | /* 44593 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 16208 | /* 44597 */ // MIs[3] Operand 1 |
| 16209 | /* 44597 */ // No operand predicates |
| 16210 | /* 44597 */ GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 16211 | /* 44599 */ // (intrinsic_wo_chain:{ *:[i32] } 4225:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft) |
| 16212 | /* 44599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT), |
| 16213 | /* 44602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16214 | /* 44604 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos |
| 16215 | /* 44607 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 16216 | /* 44611 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft |
| 16217 | /* 44614 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16218 | /* 44617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16219 | /* 44623 */ GIR_RootConstrainSelectedInstOperands, |
| 16220 | /* 44624 */ // GIR_Coverage, 2348, |
| 16221 | /* 44624 */ GIR_EraseRootFromParent_Done, |
| 16222 | /* 44625 */ // Label 1363: @44625 |
| 16223 | /* 44625 */ GIM_Reject, |
| 16224 | /* 44626 */ // Label 1361: @44626 |
| 16225 | /* 44626 */ GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(44853), |
| 16226 | /* 44631 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16227 | /* 44636 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16228 | /* 44639 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16229 | /* 44642 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16230 | /* 44645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1365*/ GIMT_Encode4(44714), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5956 // |
| 16231 | /* 44652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16232 | /* 44656 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16233 | /* 44660 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 16234 | /* 44664 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16235 | /* 44667 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16236 | /* 44672 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16237 | /* 44676 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16238 | /* 44681 */ // MIs[1] Rn |
| 16239 | /* 44681 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 16240 | /* 44686 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16241 | /* 44690 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16242 | /* 44692 */ // (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn), GPRnopc:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 16243 | /* 44692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 16244 | /* 44695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16245 | /* 44697 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16246 | /* 44699 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16247 | /* 44703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16248 | /* 44706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16249 | /* 44712 */ GIR_RootConstrainSelectedInstOperands, |
| 16250 | /* 44713 */ // GIR_Coverage, 5956, |
| 16251 | /* 44713 */ GIR_EraseRootFromParent_Done, |
| 16252 | /* 44714 */ // Label 1365: @44714 |
| 16253 | /* 44714 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1366*/ GIMT_Encode4(44783), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6282 // |
| 16254 | /* 44721 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16255 | /* 44725 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16256 | /* 44729 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 16257 | /* 44733 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16258 | /* 44736 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16259 | /* 44741 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16260 | /* 44745 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16261 | /* 44750 */ // MIs[1] Rn |
| 16262 | /* 44750 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 16263 | /* 44755 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16264 | /* 44759 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16265 | /* 44761 */ // (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 16266 | /* 44761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 16267 | /* 44764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16268 | /* 44766 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 16269 | /* 44768 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16270 | /* 44772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16271 | /* 44775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16272 | /* 44781 */ GIR_RootConstrainSelectedInstOperands, |
| 16273 | /* 44782 */ // GIR_Coverage, 6282, |
| 16274 | /* 44782 */ GIR_EraseRootFromParent_Done, |
| 16275 | /* 44783 */ // Label 1366: @44783 |
| 16276 | /* 44783 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1367*/ GIMT_Encode4(44852), GIMT_Encode2(GIFBS_IsARM), // Rule ID 108 // |
| 16277 | /* 44790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16278 | /* 44794 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16279 | /* 44798 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16280 | /* 44802 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 16281 | /* 44806 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16282 | /* 44809 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16283 | /* 44814 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16284 | /* 44818 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16285 | /* 44823 */ // MIs[1] Rn |
| 16286 | /* 44823 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 16287 | /* 44828 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16288 | /* 44830 */ // (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 16289 | /* 44830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 16290 | /* 44833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16291 | /* 44835 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 16292 | /* 44837 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16293 | /* 44841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16294 | /* 44844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16295 | /* 44850 */ GIR_RootConstrainSelectedInstOperands, |
| 16296 | /* 44851 */ // GIR_Coverage, 108, |
| 16297 | /* 44851 */ GIR_EraseRootFromParent_Done, |
| 16298 | /* 44852 */ // Label 1367: @44852 |
| 16299 | /* 44852 */ GIM_Reject, |
| 16300 | /* 44853 */ // Label 1364: @44853 |
| 16301 | /* 44853 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1368*/ GIMT_Encode4(44936), GIMT_Encode2(GIFBS_IsARM), // Rule ID 109 // |
| 16302 | /* 44860 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 16303 | /* 44865 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16304 | /* 44868 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16305 | /* 44871 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16306 | /* 44874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16307 | /* 44878 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16308 | /* 44882 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16309 | /* 44886 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 16310 | /* 44890 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16311 | /* 44893 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16312 | /* 44898 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16313 | /* 44902 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 16314 | /* 44907 */ // MIs[1] Rn |
| 16315 | /* 44907 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 16316 | /* 44912 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16317 | /* 44914 */ // (intrinsic_wo_chain:{ *:[i32] } 4153:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 16318 | /* 44914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB), |
| 16319 | /* 44917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16320 | /* 44919 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 16321 | /* 44921 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16322 | /* 44925 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16323 | /* 44928 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16324 | /* 44934 */ GIR_RootConstrainSelectedInstOperands, |
| 16325 | /* 44935 */ // GIR_Coverage, 109, |
| 16326 | /* 44935 */ GIR_EraseRootFromParent_Done, |
| 16327 | /* 44936 */ // Label 1368: @44936 |
| 16328 | /* 44936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1369*/ GIMT_Encode4(45019), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2326 // |
| 16329 | /* 44943 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16330 | /* 44948 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16331 | /* 44951 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16332 | /* 44954 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16333 | /* 44957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16334 | /* 44961 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16335 | /* 44965 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16336 | /* 44969 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 16337 | /* 44973 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16338 | /* 44976 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16339 | /* 44981 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16340 | /* 44985 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16341 | /* 44990 */ // MIs[1] Rn |
| 16342 | /* 44990 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 16343 | /* 44995 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16344 | /* 44997 */ // (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 16345 | /* 44997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 16346 | /* 45000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16347 | /* 45002 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 16348 | /* 45004 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16349 | /* 45008 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16350 | /* 45011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16351 | /* 45017 */ GIR_RootConstrainSelectedInstOperands, |
| 16352 | /* 45018 */ // GIR_Coverage, 2326, |
| 16353 | /* 45018 */ GIR_EraseRootFromParent_Done, |
| 16354 | /* 45019 */ // Label 1369: @45019 |
| 16355 | /* 45019 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1370*/ GIMT_Encode4(45102), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2327 // |
| 16356 | /* 45026 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 16357 | /* 45031 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 16358 | /* 45034 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16359 | /* 45037 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16360 | /* 45040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16361 | /* 45044 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16362 | /* 45048 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 16363 | /* 45052 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 16364 | /* 45056 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 16365 | /* 45059 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 16366 | /* 45064 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 16367 | /* 45068 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 16368 | /* 45073 */ // MIs[1] Rn |
| 16369 | /* 45073 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 16370 | /* 45078 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 16371 | /* 45080 */ // (intrinsic_wo_chain:{ *:[i32] } 4153:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 16372 | /* 45080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB), |
| 16373 | /* 45083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 16374 | /* 45085 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 16375 | /* 45087 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn |
| 16376 | /* 45091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 16377 | /* 45094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16378 | /* 45100 */ GIR_RootConstrainSelectedInstOperands, |
| 16379 | /* 45101 */ // GIR_Coverage, 2327, |
| 16380 | /* 45101 */ GIR_EraseRootFromParent_Done, |
| 16381 | /* 45102 */ // Label 1370: @45102 |
| 16382 | /* 45102 */ GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(45304), |
| 16383 | /* 45107 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm), |
| 16384 | /* 45112 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1374*/ GIMT_Encode4(45303), |
| 16385 | /* 45123 */ /*GILLT_v8s16*//*Label 1372*/ GIMT_Encode4(45135), GIMT_Encode4(0), |
| 16386 | /* 45131 */ /*GILLT_v4s32*//*Label 1373*/ GIMT_Encode4(45219), |
| 16387 | /* 45135 */ // Label 1372: @45135 |
| 16388 | /* 45135 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1375*/ GIMT_Encode4(45218), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4572 // |
| 16389 | /* 45142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16390 | /* 45145 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16391 | /* 45148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16392 | /* 45152 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16393 | /* 45156 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16394 | /* 45160 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 16395 | /* 45164 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16396 | /* 45169 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 16397 | /* 45173 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16398 | /* 45177 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 16399 | /* 45181 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16400 | /* 45186 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16401 | /* 45188 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3928:{ *:[iPTR] }, (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 16402 | /* 45188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16), |
| 16403 | /* 45191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16404 | /* 45193 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 16405 | /* 45197 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 16406 | /* 45201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16407 | /* 45204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16408 | /* 45210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16409 | /* 45216 */ GIR_RootConstrainSelectedInstOperands, |
| 16410 | /* 45217 */ // GIR_Coverage, 4572, |
| 16411 | /* 45217 */ GIR_EraseRootFromParent_Done, |
| 16412 | /* 45218 */ // Label 1375: @45218 |
| 16413 | /* 45218 */ GIM_Reject, |
| 16414 | /* 45219 */ // Label 1373: @45219 |
| 16415 | /* 45219 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1376*/ GIMT_Encode4(45302), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4569 // |
| 16416 | /* 45226 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16417 | /* 45229 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16418 | /* 45232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16419 | /* 45236 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16420 | /* 45240 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16421 | /* 45244 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 16422 | /* 45248 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16423 | /* 45253 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 16424 | /* 45257 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16425 | /* 45261 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 16426 | /* 45265 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16427 | /* 45270 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16428 | /* 45272 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3928:{ *:[iPTR] }, (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 16429 | /* 45272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32), |
| 16430 | /* 45275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16431 | /* 45277 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 16432 | /* 45281 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 16433 | /* 45285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16434 | /* 45288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16435 | /* 45294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16436 | /* 45300 */ GIR_RootConstrainSelectedInstOperands, |
| 16437 | /* 45301 */ // GIR_Coverage, 4569, |
| 16438 | /* 45301 */ GIR_EraseRootFromParent_Done, |
| 16439 | /* 45302 */ // Label 1376: @45302 |
| 16440 | /* 45302 */ GIM_Reject, |
| 16441 | /* 45303 */ // Label 1374: @45303 |
| 16442 | /* 45303 */ GIM_Reject, |
| 16443 | /* 45304 */ // Label 1371: @45304 |
| 16444 | /* 45304 */ GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(45506), |
| 16445 | /* 45309 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm), |
| 16446 | /* 45314 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1380*/ GIMT_Encode4(45505), |
| 16447 | /* 45325 */ /*GILLT_v8s16*//*Label 1378*/ GIMT_Encode4(45337), GIMT_Encode4(0), |
| 16448 | /* 45333 */ /*GILLT_v4s32*//*Label 1379*/ GIMT_Encode4(45421), |
| 16449 | /* 45337 */ // Label 1378: @45337 |
| 16450 | /* 45337 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1381*/ GIMT_Encode4(45420), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4578 // |
| 16451 | /* 45344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16452 | /* 45347 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16453 | /* 45350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16454 | /* 45354 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16455 | /* 45358 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16456 | /* 45362 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 16457 | /* 45366 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16458 | /* 45371 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 16459 | /* 45375 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16460 | /* 45379 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 16461 | /* 45383 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16462 | /* 45388 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16463 | /* 45390 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3931:{ *:[iPTR] }, (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 16464 | /* 45390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16), |
| 16465 | /* 45393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16466 | /* 45395 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 16467 | /* 45399 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 16468 | /* 45403 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16469 | /* 45406 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16470 | /* 45412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16471 | /* 45418 */ GIR_RootConstrainSelectedInstOperands, |
| 16472 | /* 45419 */ // GIR_Coverage, 4578, |
| 16473 | /* 45419 */ GIR_EraseRootFromParent_Done, |
| 16474 | /* 45420 */ // Label 1381: @45420 |
| 16475 | /* 45420 */ GIM_Reject, |
| 16476 | /* 45421 */ // Label 1379: @45421 |
| 16477 | /* 45421 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1382*/ GIMT_Encode4(45504), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4575 // |
| 16478 | /* 45428 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16479 | /* 45431 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16480 | /* 45434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16481 | /* 45438 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 16482 | /* 45442 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16483 | /* 45446 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 16484 | /* 45450 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16485 | /* 45455 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 16486 | /* 45459 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 16487 | /* 45463 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 16488 | /* 45467 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16489 | /* 45472 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 16490 | /* 45474 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3931:{ *:[iPTR] }, (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 16491 | /* 45474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32), |
| 16492 | /* 45477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16493 | /* 45479 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 16494 | /* 45483 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 16495 | /* 45487 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16496 | /* 45490 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16497 | /* 45496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16498 | /* 45502 */ GIR_RootConstrainSelectedInstOperands, |
| 16499 | /* 45503 */ // GIR_Coverage, 4575, |
| 16500 | /* 45503 */ GIR_EraseRootFromParent_Done, |
| 16501 | /* 45504 */ // Label 1382: @45504 |
| 16502 | /* 45504 */ GIM_Reject, |
| 16503 | /* 45505 */ // Label 1380: @45505 |
| 16504 | /* 45505 */ GIM_Reject, |
| 16505 | /* 45506 */ // Label 1377: @45506 |
| 16506 | /* 45506 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1383*/ GIMT_Encode4(45578), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4500 // |
| 16507 | /* 45513 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 16508 | /* 45518 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16509 | /* 45521 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16510 | /* 45524 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16511 | /* 45527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16512 | /* 45531 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16513 | /* 45535 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16514 | /* 45539 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16515 | /* 45539 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16516 | /* 45542 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16517 | /* 45546 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16518 | /* 45551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16a), |
| 16519 | /* 45554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16520 | /* 45556 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16521 | /* 45558 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16522 | /* 45561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16523 | /* 45567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16524 | /* 45573 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16525 | /* 45576 */ GIR_RootConstrainSelectedInstOperands, |
| 16526 | /* 45577 */ // GIR_Coverage, 4500, |
| 16527 | /* 45577 */ GIR_EraseRootFromParent_Done, |
| 16528 | /* 45578 */ // Label 1383: @45578 |
| 16529 | /* 45578 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1384*/ GIMT_Encode4(45650), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4502 // |
| 16530 | /* 45585 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 16531 | /* 45590 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16532 | /* 45593 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16533 | /* 45596 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16534 | /* 45599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16535 | /* 45603 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16536 | /* 45607 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16537 | /* 45611 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16538 | /* 45611 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16539 | /* 45614 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16540 | /* 45618 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16541 | /* 45623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16n), |
| 16542 | /* 45626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16543 | /* 45628 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16544 | /* 45630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16545 | /* 45633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16546 | /* 45639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16547 | /* 45645 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16548 | /* 45648 */ GIR_RootConstrainSelectedInstOperands, |
| 16549 | /* 45649 */ // GIR_Coverage, 4502, |
| 16550 | /* 45649 */ GIR_EraseRootFromParent_Done, |
| 16551 | /* 45650 */ // Label 1384: @45650 |
| 16552 | /* 45650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1385*/ GIMT_Encode4(45722), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4504 // |
| 16553 | /* 45657 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 16554 | /* 45662 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16555 | /* 45665 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16556 | /* 45668 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16557 | /* 45671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16558 | /* 45675 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16559 | /* 45679 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16560 | /* 45683 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3907:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16561 | /* 45683 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16562 | /* 45686 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16563 | /* 45690 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16564 | /* 45695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16p), |
| 16565 | /* 45698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16566 | /* 45700 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16567 | /* 45702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16568 | /* 45705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16569 | /* 45711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16570 | /* 45717 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16571 | /* 45720 */ GIR_RootConstrainSelectedInstOperands, |
| 16572 | /* 45721 */ // GIR_Coverage, 4504, |
| 16573 | /* 45721 */ GIR_EraseRootFromParent_Done, |
| 16574 | /* 45722 */ // Label 1385: @45722 |
| 16575 | /* 45722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1386*/ GIMT_Encode4(45794), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4506 // |
| 16576 | /* 45729 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 16577 | /* 45734 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16578 | /* 45737 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16579 | /* 45740 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16580 | /* 45743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16581 | /* 45747 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16582 | /* 45751 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16583 | /* 45755 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3903:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16584 | /* 45755 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16585 | /* 45758 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16586 | /* 45762 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16587 | /* 45767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16m), |
| 16588 | /* 45770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16589 | /* 45772 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16590 | /* 45774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16591 | /* 45777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16592 | /* 45783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16593 | /* 45789 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16594 | /* 45792 */ GIR_RootConstrainSelectedInstOperands, |
| 16595 | /* 45793 */ // GIR_Coverage, 4506, |
| 16596 | /* 45793 */ GIR_EraseRootFromParent_Done, |
| 16597 | /* 45794 */ // Label 1386: @45794 |
| 16598 | /* 45794 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1387*/ GIMT_Encode4(45866), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4508 // |
| 16599 | /* 45801 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 16600 | /* 45806 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16601 | /* 45809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16602 | /* 45812 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16603 | /* 45815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16604 | /* 45819 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16605 | /* 45823 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16606 | /* 45827 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3901:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16607 | /* 45827 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16608 | /* 45830 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16609 | /* 45834 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16610 | /* 45839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16a), |
| 16611 | /* 45842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16612 | /* 45844 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16613 | /* 45846 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16614 | /* 45849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16615 | /* 45855 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16616 | /* 45861 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16617 | /* 45864 */ GIR_RootConstrainSelectedInstOperands, |
| 16618 | /* 45865 */ // GIR_Coverage, 4508, |
| 16619 | /* 45865 */ GIR_EraseRootFromParent_Done, |
| 16620 | /* 45866 */ // Label 1387: @45866 |
| 16621 | /* 45866 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1388*/ GIMT_Encode4(45938), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4510 // |
| 16622 | /* 45873 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 16623 | /* 45878 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16624 | /* 45881 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16625 | /* 45884 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16626 | /* 45887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16627 | /* 45891 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16628 | /* 45895 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16629 | /* 45899 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3905:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16630 | /* 45899 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16631 | /* 45902 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16632 | /* 45906 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16633 | /* 45911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16n), |
| 16634 | /* 45914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16635 | /* 45916 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16636 | /* 45918 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16637 | /* 45921 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16638 | /* 45927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16639 | /* 45933 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16640 | /* 45936 */ GIR_RootConstrainSelectedInstOperands, |
| 16641 | /* 45937 */ // GIR_Coverage, 4510, |
| 16642 | /* 45937 */ GIR_EraseRootFromParent_Done, |
| 16643 | /* 45938 */ // Label 1388: @45938 |
| 16644 | /* 45938 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1389*/ GIMT_Encode4(46010), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4512 // |
| 16645 | /* 45945 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 16646 | /* 45950 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16647 | /* 45953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16648 | /* 45956 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16649 | /* 45959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16650 | /* 45963 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16651 | /* 45967 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16652 | /* 45971 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3907:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16653 | /* 45971 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16654 | /* 45974 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16655 | /* 45978 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16656 | /* 45983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16p), |
| 16657 | /* 45986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16658 | /* 45988 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16659 | /* 45990 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16660 | /* 45993 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16661 | /* 45999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16662 | /* 46005 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16663 | /* 46008 */ GIR_RootConstrainSelectedInstOperands, |
| 16664 | /* 46009 */ // GIR_Coverage, 4512, |
| 16665 | /* 46009 */ GIR_EraseRootFromParent_Done, |
| 16666 | /* 46010 */ // Label 1389: @46010 |
| 16667 | /* 46010 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1390*/ GIMT_Encode4(46082), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4514 // |
| 16668 | /* 46017 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 16669 | /* 46022 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 16670 | /* 46025 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16671 | /* 46028 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 16672 | /* 46031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16673 | /* 46035 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16674 | /* 46039 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16675 | /* 46043 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3903:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in) |
| 16676 | /* 46043 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16677 | /* 46046 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16678 | /* 46050 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16679 | /* 46055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16m), |
| 16680 | /* 46058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16681 | /* 46060 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16682 | /* 46062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16683 | /* 46065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16684 | /* 46071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16685 | /* 46077 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16686 | /* 46080 */ GIR_RootConstrainSelectedInstOperands, |
| 16687 | /* 46081 */ // GIR_Coverage, 4514, |
| 16688 | /* 46081 */ GIR_EraseRootFromParent_Done, |
| 16689 | /* 46082 */ // Label 1390: @46082 |
| 16690 | /* 46082 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1391*/ GIMT_Encode4(46154), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4516 // |
| 16691 | /* 46089 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 16692 | /* 46094 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16693 | /* 46097 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16694 | /* 46100 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16695 | /* 46103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16696 | /* 46107 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16697 | /* 46111 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16698 | /* 46115 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3901:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16699 | /* 46115 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16700 | /* 46118 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16701 | /* 46122 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16702 | /* 46127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32a), |
| 16703 | /* 46130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16704 | /* 46132 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16705 | /* 46134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16706 | /* 46137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16707 | /* 46143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16708 | /* 46149 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16709 | /* 46152 */ GIR_RootConstrainSelectedInstOperands, |
| 16710 | /* 46153 */ // GIR_Coverage, 4516, |
| 16711 | /* 46153 */ GIR_EraseRootFromParent_Done, |
| 16712 | /* 46154 */ // Label 1391: @46154 |
| 16713 | /* 46154 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1392*/ GIMT_Encode4(46226), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4518 // |
| 16714 | /* 46161 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 16715 | /* 46166 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16716 | /* 46169 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16717 | /* 46172 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16718 | /* 46175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16719 | /* 46179 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16720 | /* 46183 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16721 | /* 46187 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3905:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16722 | /* 46187 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16723 | /* 46190 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16724 | /* 46194 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16725 | /* 46199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32n), |
| 16726 | /* 46202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16727 | /* 46204 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16728 | /* 46206 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16729 | /* 46209 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16730 | /* 46215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16731 | /* 46221 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16732 | /* 46224 */ GIR_RootConstrainSelectedInstOperands, |
| 16733 | /* 46225 */ // GIR_Coverage, 4518, |
| 16734 | /* 46225 */ GIR_EraseRootFromParent_Done, |
| 16735 | /* 46226 */ // Label 1392: @46226 |
| 16736 | /* 46226 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1393*/ GIMT_Encode4(46298), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4520 // |
| 16737 | /* 46233 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 16738 | /* 46238 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16739 | /* 46241 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16740 | /* 46244 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16741 | /* 46247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16742 | /* 46251 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16743 | /* 46255 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16744 | /* 46259 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3907:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16745 | /* 46259 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16746 | /* 46262 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16747 | /* 46266 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16748 | /* 46271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32p), |
| 16749 | /* 46274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16750 | /* 46276 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16751 | /* 46278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16752 | /* 46281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16753 | /* 46287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16754 | /* 46293 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16755 | /* 46296 */ GIR_RootConstrainSelectedInstOperands, |
| 16756 | /* 46297 */ // GIR_Coverage, 4520, |
| 16757 | /* 46297 */ GIR_EraseRootFromParent_Done, |
| 16758 | /* 46298 */ // Label 1393: @46298 |
| 16759 | /* 46298 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1394*/ GIMT_Encode4(46370), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4522 // |
| 16760 | /* 46305 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 16761 | /* 46310 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16762 | /* 46313 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16763 | /* 46316 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16764 | /* 46319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16765 | /* 46323 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 16766 | /* 46327 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16767 | /* 46331 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3903:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16768 | /* 46331 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16769 | /* 46334 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16770 | /* 46338 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16771 | /* 46343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32m), |
| 16772 | /* 46346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16773 | /* 46348 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16774 | /* 46350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16775 | /* 46353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16776 | /* 46359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16777 | /* 46365 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16778 | /* 46368 */ GIR_RootConstrainSelectedInstOperands, |
| 16779 | /* 46369 */ // GIR_Coverage, 4522, |
| 16780 | /* 46369 */ GIR_EraseRootFromParent_Done, |
| 16781 | /* 46370 */ // Label 1394: @46370 |
| 16782 | /* 46370 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1395*/ GIMT_Encode4(46442), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4524 // |
| 16783 | /* 46377 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta), |
| 16784 | /* 46382 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16785 | /* 46385 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16786 | /* 46388 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16787 | /* 46391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16788 | /* 46395 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16789 | /* 46399 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16790 | /* 46403 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3901:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16791 | /* 46403 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16792 | /* 46406 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16793 | /* 46410 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16794 | /* 46415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32a), |
| 16795 | /* 46418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16796 | /* 46420 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16797 | /* 46422 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16798 | /* 46425 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16799 | /* 46431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16800 | /* 46437 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16801 | /* 46440 */ GIR_RootConstrainSelectedInstOperands, |
| 16802 | /* 46441 */ // GIR_Coverage, 4524, |
| 16803 | /* 46441 */ GIR_EraseRootFromParent_Done, |
| 16804 | /* 46442 */ // Label 1395: @46442 |
| 16805 | /* 46442 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1396*/ GIMT_Encode4(46514), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4526 // |
| 16806 | /* 46449 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn), |
| 16807 | /* 46454 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16808 | /* 46457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16809 | /* 46460 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16810 | /* 46463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16811 | /* 46467 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16812 | /* 46471 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16813 | /* 46475 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3905:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16814 | /* 46475 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16815 | /* 46478 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16816 | /* 46482 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16817 | /* 46487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32n), |
| 16818 | /* 46490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16819 | /* 46492 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16820 | /* 46494 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16821 | /* 46497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16822 | /* 46503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16823 | /* 46509 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16824 | /* 46512 */ GIR_RootConstrainSelectedInstOperands, |
| 16825 | /* 46513 */ // GIR_Coverage, 4526, |
| 16826 | /* 46513 */ GIR_EraseRootFromParent_Done, |
| 16827 | /* 46514 */ // Label 1396: @46514 |
| 16828 | /* 46514 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1397*/ GIMT_Encode4(46586), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4528 // |
| 16829 | /* 46521 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp), |
| 16830 | /* 46526 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16831 | /* 46529 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16832 | /* 46532 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16833 | /* 46535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16834 | /* 46539 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16835 | /* 46543 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16836 | /* 46547 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3907:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16837 | /* 46547 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16838 | /* 46550 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16839 | /* 46554 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16840 | /* 46559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32p), |
| 16841 | /* 46562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16842 | /* 46564 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16843 | /* 46566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16844 | /* 46569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16845 | /* 46575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16846 | /* 46581 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16847 | /* 46584 */ GIR_RootConstrainSelectedInstOperands, |
| 16848 | /* 46585 */ // GIR_Coverage, 4528, |
| 16849 | /* 46585 */ GIR_EraseRootFromParent_Done, |
| 16850 | /* 46586 */ // Label 1397: @46586 |
| 16851 | /* 46586 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1398*/ GIMT_Encode4(46658), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4530 // |
| 16852 | /* 46593 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm), |
| 16853 | /* 46598 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 16854 | /* 46601 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 16855 | /* 46604 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 16856 | /* 46607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16857 | /* 46611 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 16858 | /* 46615 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16859 | /* 46619 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3903:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in) |
| 16860 | /* 46619 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16861 | /* 46622 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16862 | /* 46626 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16863 | /* 46631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32m), |
| 16864 | /* 46634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16865 | /* 46636 */ GIR_RootToRootCopy, /*OpIdx*/3, // in |
| 16866 | /* 46638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16867 | /* 46641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16868 | /* 46647 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16869 | /* 46653 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16870 | /* 46656 */ GIR_RootConstrainSelectedInstOperands, |
| 16871 | /* 46657 */ // GIR_Coverage, 4530, |
| 16872 | /* 46657 */ GIR_EraseRootFromParent_Done, |
| 16873 | /* 46658 */ // Label 1398: @46658 |
| 16874 | /* 46658 */ GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(46934), |
| 16875 | /* 46663 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp), |
| 16876 | /* 46668 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1402*/ GIMT_Encode4(46933), |
| 16877 | /* 46679 */ /*GILLT_v8s16*//*Label 1400*/ GIMT_Encode4(46691), GIMT_Encode4(0), |
| 16878 | /* 46687 */ /*GILLT_v4s32*//*Label 1401*/ GIMT_Encode4(46812), |
| 16879 | /* 46691 */ // Label 1400: @46691 |
| 16880 | /* 46691 */ GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(46811), |
| 16881 | /* 46696 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16882 | /* 46699 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16883 | /* 46702 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16884 | /* 46706 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16885 | /* 46710 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1404*/ GIMT_Encode4(46760), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4533 // |
| 16886 | /* 46717 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 16887 | /* 46721 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3896:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$src, 0:{ *:[i32] }) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 16888 | /* 46721 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16889 | /* 46724 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16890 | /* 46728 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16891 | /* 46733 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z), |
| 16892 | /* 46736 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16893 | /* 46738 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 16894 | /* 46740 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16895 | /* 46743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16896 | /* 46749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16897 | /* 46755 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16898 | /* 46758 */ GIR_RootConstrainSelectedInstOperands, |
| 16899 | /* 46759 */ // GIR_Coverage, 4533, |
| 16900 | /* 46759 */ GIR_EraseRootFromParent_Done, |
| 16901 | /* 46760 */ // Label 1404: @46760 |
| 16902 | /* 46760 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1405*/ GIMT_Encode4(46810), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4536 // |
| 16903 | /* 46767 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 16904 | /* 46771 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3896:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$src, 1:{ *:[i32] }) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 16905 | /* 46771 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16906 | /* 46774 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16907 | /* 46778 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16908 | /* 46783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z), |
| 16909 | /* 46786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16910 | /* 46788 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 16911 | /* 46790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16912 | /* 46793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16913 | /* 46799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16914 | /* 46805 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16915 | /* 46808 */ GIR_RootConstrainSelectedInstOperands, |
| 16916 | /* 46809 */ // GIR_Coverage, 4536, |
| 16917 | /* 46809 */ GIR_EraseRootFromParent_Done, |
| 16918 | /* 46810 */ // Label 1405: @46810 |
| 16919 | /* 46810 */ GIM_Reject, |
| 16920 | /* 46811 */ // Label 1403: @46811 |
| 16921 | /* 46811 */ GIM_Reject, |
| 16922 | /* 46812 */ // Label 1401: @46812 |
| 16923 | /* 46812 */ GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(46932), |
| 16924 | /* 46817 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 16925 | /* 46820 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16926 | /* 46823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16927 | /* 46827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16928 | /* 46831 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1407*/ GIMT_Encode4(46881), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4539 // |
| 16929 | /* 46838 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 16930 | /* 46842 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3896:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$src, 0:{ *:[i32] }) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 16931 | /* 46842 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16932 | /* 46845 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16933 | /* 46849 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16934 | /* 46854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z), |
| 16935 | /* 46857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16936 | /* 46859 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 16937 | /* 46861 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16938 | /* 46864 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16939 | /* 46870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16940 | /* 46876 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16941 | /* 46879 */ GIR_RootConstrainSelectedInstOperands, |
| 16942 | /* 46880 */ // GIR_Coverage, 4539, |
| 16943 | /* 46880 */ GIR_EraseRootFromParent_Done, |
| 16944 | /* 46881 */ // Label 1407: @46881 |
| 16945 | /* 46881 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1408*/ GIMT_Encode4(46931), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4542 // |
| 16946 | /* 46888 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 16947 | /* 46892 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3896:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$src, 1:{ *:[i32] }) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 16948 | /* 46892 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16949 | /* 46895 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16950 | /* 46899 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16951 | /* 46904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z), |
| 16952 | /* 46907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16953 | /* 46909 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 16954 | /* 46911 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16955 | /* 46914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16956 | /* 46920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16957 | /* 46926 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16958 | /* 46929 */ GIR_RootConstrainSelectedInstOperands, |
| 16959 | /* 46930 */ // GIR_Coverage, 4542, |
| 16960 | /* 46930 */ GIR_EraseRootFromParent_Done, |
| 16961 | /* 46931 */ // Label 1408: @46931 |
| 16962 | /* 46931 */ GIM_Reject, |
| 16963 | /* 46932 */ // Label 1406: @46932 |
| 16964 | /* 46932 */ GIM_Reject, |
| 16965 | /* 46933 */ // Label 1402: @46933 |
| 16966 | /* 46933 */ GIM_Reject, |
| 16967 | /* 46934 */ // Label 1399: @46934 |
| 16968 | /* 46934 */ GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(47210), |
| 16969 | /* 46939 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int), |
| 16970 | /* 46944 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1412*/ GIMT_Encode4(47209), |
| 16971 | /* 46955 */ /*GILLT_v8s16*//*Label 1410*/ GIMT_Encode4(46967), GIMT_Encode4(0), |
| 16972 | /* 46963 */ /*GILLT_v4s32*//*Label 1411*/ GIMT_Encode4(47088), |
| 16973 | /* 46967 */ // Label 1410: @46967 |
| 16974 | /* 46967 */ GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(47087), |
| 16975 | /* 46972 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 16976 | /* 46975 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 16977 | /* 46978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16978 | /* 46982 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 16979 | /* 46986 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1414*/ GIMT_Encode4(47036), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4545 // |
| 16980 | /* 46993 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 16981 | /* 46997 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3894:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 0:{ *:[i32] }) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 16982 | /* 46997 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 16983 | /* 47000 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 16984 | /* 47004 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 16985 | /* 47009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n), |
| 16986 | /* 47012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 16987 | /* 47014 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 16988 | /* 47016 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16989 | /* 47019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16990 | /* 47025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 16991 | /* 47031 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 16992 | /* 47034 */ GIR_RootConstrainSelectedInstOperands, |
| 16993 | /* 47035 */ // GIR_Coverage, 4545, |
| 16994 | /* 47035 */ GIR_EraseRootFromParent_Done, |
| 16995 | /* 47036 */ // Label 1414: @47036 |
| 16996 | /* 47036 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1415*/ GIMT_Encode4(47086), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4548 // |
| 16997 | /* 47043 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 16998 | /* 47047 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3894:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 1:{ *:[i32] }) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 16999 | /* 47047 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17000 | /* 47050 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17001 | /* 47054 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17002 | /* 47059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n), |
| 17003 | /* 47062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17004 | /* 47064 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17005 | /* 47066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17006 | /* 47069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17007 | /* 47075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17008 | /* 47081 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17009 | /* 47084 */ GIR_RootConstrainSelectedInstOperands, |
| 17010 | /* 47085 */ // GIR_Coverage, 4548, |
| 17011 | /* 47085 */ GIR_EraseRootFromParent_Done, |
| 17012 | /* 47086 */ // Label 1415: @47086 |
| 17013 | /* 47086 */ GIM_Reject, |
| 17014 | /* 47087 */ // Label 1413: @47087 |
| 17015 | /* 47087 */ GIM_Reject, |
| 17016 | /* 47088 */ // Label 1411: @47088 |
| 17017 | /* 47088 */ GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(47208), |
| 17018 | /* 47093 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17019 | /* 47096 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17020 | /* 47099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17021 | /* 47103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17022 | /* 47107 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1417*/ GIMT_Encode4(47157), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4551 // |
| 17023 | /* 47114 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 17024 | /* 47118 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3894:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, 0:{ *:[i32] }) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 17025 | /* 47118 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17026 | /* 47121 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17027 | /* 47125 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17028 | /* 47130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n), |
| 17029 | /* 47133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17030 | /* 47135 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17031 | /* 47137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17032 | /* 47140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17033 | /* 47146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17034 | /* 47152 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17035 | /* 47155 */ GIR_RootConstrainSelectedInstOperands, |
| 17036 | /* 47156 */ // GIR_Coverage, 4551, |
| 17037 | /* 47156 */ GIR_EraseRootFromParent_Done, |
| 17038 | /* 47157 */ // Label 1417: @47157 |
| 17039 | /* 47157 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1418*/ GIMT_Encode4(47207), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4554 // |
| 17040 | /* 47164 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 17041 | /* 47168 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3894:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, 1:{ *:[i32] }) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 17042 | /* 47168 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17043 | /* 47171 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17044 | /* 47175 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17045 | /* 47180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n), |
| 17046 | /* 47183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17047 | /* 47185 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17048 | /* 47187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17049 | /* 47190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17050 | /* 47196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17051 | /* 47202 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17052 | /* 47205 */ GIR_RootConstrainSelectedInstOperands, |
| 17053 | /* 47206 */ // GIR_Coverage, 4554, |
| 17054 | /* 47206 */ GIR_EraseRootFromParent_Done, |
| 17055 | /* 47207 */ // Label 1418: @47207 |
| 17056 | /* 47207 */ GIM_Reject, |
| 17057 | /* 47208 */ // Label 1416: @47208 |
| 17058 | /* 47208 */ GIM_Reject, |
| 17059 | /* 47209 */ // Label 1412: @47209 |
| 17060 | /* 47209 */ GIM_Reject, |
| 17061 | /* 47210 */ // Label 1409: @47210 |
| 17062 | /* 47210 */ GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(47338), |
| 17063 | /* 47215 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen), |
| 17064 | /* 47220 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17065 | /* 47223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17066 | /* 47226 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17067 | /* 47229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17068 | /* 47233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17069 | /* 47237 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1420*/ GIMT_Encode4(47287), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5034 // |
| 17070 | /* 47244 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 17071 | /* 47248 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3899:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf32f16bh:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm) |
| 17072 | /* 47248 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17073 | /* 47251 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17074 | /* 47255 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17075 | /* 47260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16bh), |
| 17076 | /* 47263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17077 | /* 47265 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 17078 | /* 47267 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17079 | /* 47270 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17080 | /* 47276 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17081 | /* 47282 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17082 | /* 47285 */ GIR_RootConstrainSelectedInstOperands, |
| 17083 | /* 47286 */ // GIR_Coverage, 5034, |
| 17084 | /* 47286 */ GIR_EraseRootFromParent_Done, |
| 17085 | /* 47287 */ // Label 1420: @47287 |
| 17086 | /* 47287 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1421*/ GIMT_Encode4(47337), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5040 // |
| 17087 | /* 47294 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 17088 | /* 47298 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3899:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf32f16th:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm) |
| 17089 | /* 47298 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17090 | /* 47301 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17091 | /* 47305 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17092 | /* 47310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16th), |
| 17093 | /* 47313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17094 | /* 47315 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 17095 | /* 47317 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17096 | /* 47320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17097 | /* 47326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17098 | /* 47332 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17099 | /* 47335 */ GIR_RootConstrainSelectedInstOperands, |
| 17100 | /* 47336 */ // GIR_Coverage, 5040, |
| 17101 | /* 47336 */ GIR_EraseRootFromParent_Done, |
| 17102 | /* 47337 */ // Label 1421: @47337 |
| 17103 | /* 47337 */ GIM_Reject, |
| 17104 | /* 47338 */ // Label 1419: @47338 |
| 17105 | /* 47338 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1422*/ GIMT_Encode4(47405), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2069 // |
| 17106 | /* 47345 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 17107 | /* 47350 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17108 | /* 47353 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17109 | /* 47356 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17110 | /* 47359 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17111 | /* 47363 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17112 | /* 47367 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17113 | /* 47371 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17114 | /* 47375 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 17115 | /* 47379 */ // MIs[1] Operand 1 |
| 17116 | /* 47379 */ // No operand predicates |
| 17117 | /* 47379 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17118 | /* 47381 */ // (intrinsic_wo_chain:{ *:[i32] } 4225:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, 0:{ *:[i32] }) |
| 17119 | /* 47381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT), |
| 17120 | /* 47384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17121 | /* 47386 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 17122 | /* 47389 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 17123 | /* 47391 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17124 | /* 47394 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17125 | /* 47397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17126 | /* 47403 */ GIR_RootConstrainSelectedInstOperands, |
| 17127 | /* 47404 */ // GIR_Coverage, 2069, |
| 17128 | /* 47404 */ GIR_EraseRootFromParent_Done, |
| 17129 | /* 47405 */ // Label 1422: @47405 |
| 17130 | /* 47405 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1423*/ GIMT_Encode4(47469), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2073 // |
| 17131 | /* 47412 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16), |
| 17132 | /* 47417 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17133 | /* 47420 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17134 | /* 47423 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17135 | /* 47426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17136 | /* 47430 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17137 | /* 47434 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17138 | /* 47438 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17139 | /* 47442 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 17140 | /* 47446 */ // MIs[1] Operand 1 |
| 17141 | /* 47446 */ // No operand predicates |
| 17142 | /* 47446 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17143 | /* 47448 */ // (intrinsic_wo_chain:{ *:[i32] } 4226:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPRnopc:{ *:[i32] }:$a) |
| 17144 | /* 47448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT16), |
| 17145 | /* 47451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17146 | /* 47453 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 17147 | /* 47456 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 17148 | /* 47458 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17149 | /* 47461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17150 | /* 47467 */ GIR_RootConstrainSelectedInstOperands, |
| 17151 | /* 47468 */ // GIR_Coverage, 2073, |
| 17152 | /* 47468 */ GIR_EraseRootFromParent_Done, |
| 17153 | /* 47469 */ // Label 1423: @47469 |
| 17154 | /* 47469 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1424*/ GIMT_Encode4(47536), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2343 // |
| 17155 | /* 47476 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat), |
| 17156 | /* 47481 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17157 | /* 47484 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17158 | /* 47487 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17159 | /* 47490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17160 | /* 47494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 17161 | /* 47498 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17162 | /* 47502 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17163 | /* 47506 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 17164 | /* 47510 */ // MIs[1] Operand 1 |
| 17165 | /* 47510 */ // No operand predicates |
| 17166 | /* 47510 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17167 | /* 47512 */ // (intrinsic_wo_chain:{ *:[i32] } 4225:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPR:{ *:[i32] }:$a, 0:{ *:[i32] }) |
| 17168 | /* 47512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT), |
| 17169 | /* 47515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17170 | /* 47517 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 17171 | /* 47520 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 17172 | /* 47522 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17173 | /* 47525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17174 | /* 47528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17175 | /* 47534 */ GIR_RootConstrainSelectedInstOperands, |
| 17176 | /* 47535 */ // GIR_Coverage, 2343, |
| 17177 | /* 47535 */ GIR_EraseRootFromParent_Done, |
| 17178 | /* 47536 */ // Label 1424: @47536 |
| 17179 | /* 47536 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1425*/ GIMT_Encode4(47600), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2345 // |
| 17180 | /* 47543 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16), |
| 17181 | /* 47548 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17182 | /* 47551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17183 | /* 47554 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17184 | /* 47557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17185 | /* 47561 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 17186 | /* 47565 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17187 | /* 47569 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17188 | /* 47573 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 17189 | /* 47577 */ // MIs[1] Operand 1 |
| 17190 | /* 47577 */ // No operand predicates |
| 17191 | /* 47577 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17192 | /* 47579 */ // (intrinsic_wo_chain:{ *:[i32] } 4226:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (t2USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPR:{ *:[i32] }:$a) |
| 17193 | /* 47579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT16), |
| 17194 | /* 47582 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17195 | /* 47584 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos |
| 17196 | /* 47587 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 17197 | /* 47589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17198 | /* 47592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17199 | /* 47598 */ GIR_RootConstrainSelectedInstOperands, |
| 17200 | /* 47599 */ // GIR_Coverage, 2345, |
| 17201 | /* 47599 */ GIR_EraseRootFromParent_Done, |
| 17202 | /* 47600 */ // Label 1425: @47600 |
| 17203 | /* 47600 */ GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(47870), |
| 17204 | /* 47605 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm), |
| 17205 | /* 47610 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 1430*/ GIMT_Encode4(47869), |
| 17206 | /* 47621 */ /*GILLT_v16s8*//*Label 1427*/ GIMT_Encode4(47641), GIMT_Encode4(0), |
| 17207 | /* 47629 */ /*GILLT_v8s16*//*Label 1428*/ GIMT_Encode4(47717), GIMT_Encode4(0), |
| 17208 | /* 47637 */ /*GILLT_v4s32*//*Label 1429*/ GIMT_Encode4(47793), |
| 17209 | /* 47641 */ // Label 1427: @47641 |
| 17210 | /* 47641 */ GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(47716), // Rule ID 4322 // |
| 17211 | /* 47646 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 17212 | /* 47649 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17213 | /* 47652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17214 | /* 47656 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17215 | /* 47660 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17216 | /* 47664 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17217 | /* 47668 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 17218 | /* 47672 */ // MIs[1] Operand 1 |
| 17219 | /* 47672 */ // No operand predicates |
| 17220 | /* 47672 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17221 | /* 47674 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3963:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) => (MVE_VQSHLU_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 17222 | /* 47674 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17223 | /* 47677 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17224 | /* 47681 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17225 | /* 47686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms8), |
| 17226 | /* 47689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17227 | /* 47691 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17228 | /* 47693 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 17229 | /* 47696 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17230 | /* 47699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17231 | /* 47705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17232 | /* 47711 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17233 | /* 47714 */ GIR_RootConstrainSelectedInstOperands, |
| 17234 | /* 47715 */ // GIR_Coverage, 4322, |
| 17235 | /* 47715 */ GIR_EraseRootFromParent_Done, |
| 17236 | /* 47716 */ // Label 1431: @47716 |
| 17237 | /* 47716 */ GIM_Reject, |
| 17238 | /* 47717 */ // Label 1428: @47717 |
| 17239 | /* 47717 */ GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(47792), // Rule ID 4324 // |
| 17240 | /* 47722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17241 | /* 47725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17242 | /* 47728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17243 | /* 47732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17244 | /* 47736 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17245 | /* 47740 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17246 | /* 47744 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 17247 | /* 47748 */ // MIs[1] Operand 1 |
| 17248 | /* 47748 */ // No operand predicates |
| 17249 | /* 47748 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17250 | /* 47750 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3963:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (MVE_VQSHLU_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 17251 | /* 47750 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17252 | /* 47753 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17253 | /* 47757 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17254 | /* 47762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms16), |
| 17255 | /* 47765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17256 | /* 47767 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17257 | /* 47769 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 17258 | /* 47772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17259 | /* 47775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17260 | /* 47781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17261 | /* 47787 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17262 | /* 47790 */ GIR_RootConstrainSelectedInstOperands, |
| 17263 | /* 47791 */ // GIR_Coverage, 4324, |
| 17264 | /* 47791 */ GIR_EraseRootFromParent_Done, |
| 17265 | /* 47792 */ // Label 1432: @47792 |
| 17266 | /* 47792 */ GIM_Reject, |
| 17267 | /* 47793 */ // Label 1429: @47793 |
| 17268 | /* 47793 */ GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(47868), // Rule ID 4326 // |
| 17269 | /* 47798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17270 | /* 47801 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17271 | /* 47804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17272 | /* 47808 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 17273 | /* 47812 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17274 | /* 47816 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17275 | /* 47820 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 17276 | /* 47824 */ // MIs[1] Operand 1 |
| 17277 | /* 47824 */ // No operand predicates |
| 17278 | /* 47824 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17279 | /* 47826 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3963:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) => (MVE_VQSHLU_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 17280 | /* 47826 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 17281 | /* 47829 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 17282 | /* 47833 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 17283 | /* 47838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms32), |
| 17284 | /* 47841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 17285 | /* 47843 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 17286 | /* 47845 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 17287 | /* 47848 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17288 | /* 47851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17289 | /* 47857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17290 | /* 47863 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 17291 | /* 47866 */ GIR_RootConstrainSelectedInstOperands, |
| 17292 | /* 47867 */ // GIR_Coverage, 4326, |
| 17293 | /* 47867 */ GIR_EraseRootFromParent_Done, |
| 17294 | /* 47868 */ // Label 1433: @47868 |
| 17295 | /* 47868 */ GIM_Reject, |
| 17296 | /* 47869 */ // Label 1430: @47869 |
| 17297 | /* 47869 */ GIM_Reject, |
| 17298 | /* 47870 */ // Label 1426: @47870 |
| 17299 | /* 47870 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1434*/ GIMT_Encode4(47930), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1814 // |
| 17300 | /* 47877 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 17301 | /* 47882 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 17302 | /* 47885 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 17303 | /* 47888 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17304 | /* 47891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17305 | /* 47895 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17306 | /* 47899 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17307 | /* 47903 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17308 | /* 47907 */ // MIs[1] Operand 1 |
| 17309 | /* 47907 */ // No operand predicates |
| 17310 | /* 47907 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17311 | /* 47909 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4047:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17312 | /* 47909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsd), |
| 17313 | /* 47912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17314 | /* 47914 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17315 | /* 47916 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17316 | /* 47919 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17317 | /* 47922 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17318 | /* 47928 */ GIR_RootConstrainSelectedInstOperands, |
| 17319 | /* 47929 */ // GIR_Coverage, 1814, |
| 17320 | /* 47929 */ GIR_EraseRootFromParent_Done, |
| 17321 | /* 47930 */ // Label 1434: @47930 |
| 17322 | /* 47930 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1435*/ GIMT_Encode4(47990), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1815 // |
| 17323 | /* 47937 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 17324 | /* 47942 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 17325 | /* 47945 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 17326 | /* 47948 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17327 | /* 47951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17328 | /* 47955 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17329 | /* 47959 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17330 | /* 47963 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17331 | /* 47967 */ // MIs[1] Operand 1 |
| 17332 | /* 47967 */ // No operand predicates |
| 17333 | /* 47967 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17334 | /* 47969 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4048:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17335 | /* 47969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xud), |
| 17336 | /* 47972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17337 | /* 47974 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17338 | /* 47976 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17339 | /* 47979 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17340 | /* 47982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17341 | /* 47988 */ GIR_RootConstrainSelectedInstOperands, |
| 17342 | /* 47989 */ // GIR_Coverage, 1815, |
| 17343 | /* 47989 */ GIR_EraseRootFromParent_Done, |
| 17344 | /* 47990 */ // Label 1435: @47990 |
| 17345 | /* 47990 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1436*/ GIMT_Encode4(48050), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1816 // |
| 17346 | /* 47997 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 17347 | /* 48002 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 17348 | /* 48005 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 17349 | /* 48008 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17350 | /* 48011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17351 | /* 48015 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17352 | /* 48019 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17353 | /* 48023 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17354 | /* 48027 */ // MIs[1] Operand 1 |
| 17355 | /* 48027 */ // No operand predicates |
| 17356 | /* 48027 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17357 | /* 48029 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4050:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17358 | /* 48029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fd), |
| 17359 | /* 48032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17360 | /* 48034 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17361 | /* 48036 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17362 | /* 48039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17363 | /* 48042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17364 | /* 48048 */ GIR_RootConstrainSelectedInstOperands, |
| 17365 | /* 48049 */ // GIR_Coverage, 1816, |
| 17366 | /* 48049 */ GIR_EraseRootFromParent_Done, |
| 17367 | /* 48050 */ // Label 1436: @48050 |
| 17368 | /* 48050 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1437*/ GIMT_Encode4(48110), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1817 // |
| 17369 | /* 48057 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 17370 | /* 48062 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 17371 | /* 48065 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 17372 | /* 48068 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17373 | /* 48071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17374 | /* 48075 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17375 | /* 48079 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17376 | /* 48083 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17377 | /* 48087 */ // MIs[1] Operand 1 |
| 17378 | /* 48087 */ // No operand predicates |
| 17379 | /* 48087 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17380 | /* 48089 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4051:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17381 | /* 48089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fd), |
| 17382 | /* 48092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17383 | /* 48094 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17384 | /* 48096 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17385 | /* 48099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17386 | /* 48102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17387 | /* 48108 */ GIR_RootConstrainSelectedInstOperands, |
| 17388 | /* 48109 */ // GIR_Coverage, 1817, |
| 17389 | /* 48109 */ GIR_EraseRootFromParent_Done, |
| 17390 | /* 48110 */ // Label 1437: @48110 |
| 17391 | /* 48110 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1438*/ GIMT_Encode4(48170), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1818 // |
| 17392 | /* 48117 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 17393 | /* 48122 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 17394 | /* 48125 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 17395 | /* 48128 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17396 | /* 48131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17397 | /* 48135 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17398 | /* 48139 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17399 | /* 48143 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17400 | /* 48147 */ // MIs[1] Operand 1 |
| 17401 | /* 48147 */ // No operand predicates |
| 17402 | /* 48147 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17403 | /* 48149 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4047:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17404 | /* 48149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsd), |
| 17405 | /* 48152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17406 | /* 48154 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17407 | /* 48156 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17408 | /* 48159 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17409 | /* 48162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17410 | /* 48168 */ GIR_RootConstrainSelectedInstOperands, |
| 17411 | /* 48169 */ // GIR_Coverage, 1818, |
| 17412 | /* 48169 */ GIR_EraseRootFromParent_Done, |
| 17413 | /* 48170 */ // Label 1438: @48170 |
| 17414 | /* 48170 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1439*/ GIMT_Encode4(48230), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1819 // |
| 17415 | /* 48177 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 17416 | /* 48182 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 17417 | /* 48185 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 17418 | /* 48188 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17419 | /* 48191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17420 | /* 48195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17421 | /* 48199 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17422 | /* 48203 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17423 | /* 48207 */ // MIs[1] Operand 1 |
| 17424 | /* 48207 */ // No operand predicates |
| 17425 | /* 48207 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17426 | /* 48209 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4048:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17427 | /* 48209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xud), |
| 17428 | /* 48212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17429 | /* 48214 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17430 | /* 48216 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17431 | /* 48219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17432 | /* 48222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17433 | /* 48228 */ GIR_RootConstrainSelectedInstOperands, |
| 17434 | /* 48229 */ // GIR_Coverage, 1819, |
| 17435 | /* 48229 */ GIR_EraseRootFromParent_Done, |
| 17436 | /* 48230 */ // Label 1439: @48230 |
| 17437 | /* 48230 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1440*/ GIMT_Encode4(48290), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1820 // |
| 17438 | /* 48237 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 17439 | /* 48242 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 17440 | /* 48245 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 17441 | /* 48248 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17442 | /* 48251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17443 | /* 48255 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17444 | /* 48259 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17445 | /* 48263 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17446 | /* 48267 */ // MIs[1] Operand 1 |
| 17447 | /* 48267 */ // No operand predicates |
| 17448 | /* 48267 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17449 | /* 48269 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4050:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17450 | /* 48269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hd), |
| 17451 | /* 48272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17452 | /* 48274 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17453 | /* 48276 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17454 | /* 48279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17455 | /* 48282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17456 | /* 48288 */ GIR_RootConstrainSelectedInstOperands, |
| 17457 | /* 48289 */ // GIR_Coverage, 1820, |
| 17458 | /* 48289 */ GIR_EraseRootFromParent_Done, |
| 17459 | /* 48290 */ // Label 1440: @48290 |
| 17460 | /* 48290 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1441*/ GIMT_Encode4(48350), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1821 // |
| 17461 | /* 48297 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 17462 | /* 48302 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 17463 | /* 48305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 17464 | /* 48308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17465 | /* 48311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17466 | /* 48315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 17467 | /* 48319 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17468 | /* 48323 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17469 | /* 48327 */ // MIs[1] Operand 1 |
| 17470 | /* 48327 */ // No operand predicates |
| 17471 | /* 48327 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17472 | /* 48329 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4051:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17473 | /* 48329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hd), |
| 17474 | /* 48332 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17475 | /* 48334 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17476 | /* 48336 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17477 | /* 48339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17478 | /* 48342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17479 | /* 48348 */ GIR_RootConstrainSelectedInstOperands, |
| 17480 | /* 48349 */ // GIR_Coverage, 1821, |
| 17481 | /* 48349 */ GIR_EraseRootFromParent_Done, |
| 17482 | /* 48350 */ // Label 1441: @48350 |
| 17483 | /* 48350 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1442*/ GIMT_Encode4(48410), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1822 // |
| 17484 | /* 48357 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 17485 | /* 48362 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17486 | /* 48365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17487 | /* 48368 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17488 | /* 48371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17489 | /* 48375 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17490 | /* 48379 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17491 | /* 48383 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17492 | /* 48387 */ // MIs[1] Operand 1 |
| 17493 | /* 48387 */ // No operand predicates |
| 17494 | /* 48387 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17495 | /* 48389 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4047:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17496 | /* 48389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsq), |
| 17497 | /* 48392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17498 | /* 48394 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17499 | /* 48396 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17500 | /* 48399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17501 | /* 48402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17502 | /* 48408 */ GIR_RootConstrainSelectedInstOperands, |
| 17503 | /* 48409 */ // GIR_Coverage, 1822, |
| 17504 | /* 48409 */ GIR_EraseRootFromParent_Done, |
| 17505 | /* 48410 */ // Label 1442: @48410 |
| 17506 | /* 48410 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1443*/ GIMT_Encode4(48470), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1823 // |
| 17507 | /* 48417 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 17508 | /* 48422 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17509 | /* 48425 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17510 | /* 48428 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17511 | /* 48431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17512 | /* 48435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17513 | /* 48439 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17514 | /* 48443 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17515 | /* 48447 */ // MIs[1] Operand 1 |
| 17516 | /* 48447 */ // No operand predicates |
| 17517 | /* 48447 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17518 | /* 48449 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4048:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xuq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17519 | /* 48449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xuq), |
| 17520 | /* 48452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17521 | /* 48454 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17522 | /* 48456 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17523 | /* 48459 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17524 | /* 48462 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17525 | /* 48468 */ GIR_RootConstrainSelectedInstOperands, |
| 17526 | /* 48469 */ // GIR_Coverage, 1823, |
| 17527 | /* 48469 */ GIR_EraseRootFromParent_Done, |
| 17528 | /* 48470 */ // Label 1443: @48470 |
| 17529 | /* 48470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1444*/ GIMT_Encode4(48530), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1824 // |
| 17530 | /* 48477 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 17531 | /* 48482 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17532 | /* 48485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17533 | /* 48488 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17534 | /* 48491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17535 | /* 48495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17536 | /* 48499 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17537 | /* 48503 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17538 | /* 48507 */ // MIs[1] Operand 1 |
| 17539 | /* 48507 */ // No operand predicates |
| 17540 | /* 48507 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17541 | /* 48509 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4050:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17542 | /* 48509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fq), |
| 17543 | /* 48512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17544 | /* 48514 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17545 | /* 48516 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17546 | /* 48519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17547 | /* 48522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17548 | /* 48528 */ GIR_RootConstrainSelectedInstOperands, |
| 17549 | /* 48529 */ // GIR_Coverage, 1824, |
| 17550 | /* 48529 */ GIR_EraseRootFromParent_Done, |
| 17551 | /* 48530 */ // Label 1444: @48530 |
| 17552 | /* 48530 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1445*/ GIMT_Encode4(48590), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1825 // |
| 17553 | /* 48537 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 17554 | /* 48542 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 17555 | /* 48545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 17556 | /* 48548 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17557 | /* 48551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17558 | /* 48555 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17559 | /* 48559 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17560 | /* 48563 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17561 | /* 48567 */ // MIs[1] Operand 1 |
| 17562 | /* 48567 */ // No operand predicates |
| 17563 | /* 48567 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17564 | /* 48569 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4051:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17565 | /* 48569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fq), |
| 17566 | /* 48572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17567 | /* 48574 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17568 | /* 48576 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17569 | /* 48579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17570 | /* 48582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17571 | /* 48588 */ GIR_RootConstrainSelectedInstOperands, |
| 17572 | /* 48589 */ // GIR_Coverage, 1825, |
| 17573 | /* 48589 */ GIR_EraseRootFromParent_Done, |
| 17574 | /* 48590 */ // Label 1445: @48590 |
| 17575 | /* 48590 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1446*/ GIMT_Encode4(48650), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1826 // |
| 17576 | /* 48597 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs), |
| 17577 | /* 48602 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17578 | /* 48605 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17579 | /* 48608 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17580 | /* 48611 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17581 | /* 48615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17582 | /* 48619 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17583 | /* 48623 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17584 | /* 48627 */ // MIs[1] Operand 1 |
| 17585 | /* 48627 */ // No operand predicates |
| 17586 | /* 48627 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17587 | /* 48629 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4047:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17588 | /* 48629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsq), |
| 17589 | /* 48632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17590 | /* 48634 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17591 | /* 48636 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17592 | /* 48639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17593 | /* 48642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17594 | /* 48648 */ GIR_RootConstrainSelectedInstOperands, |
| 17595 | /* 48649 */ // GIR_Coverage, 1826, |
| 17596 | /* 48649 */ GIR_EraseRootFromParent_Done, |
| 17597 | /* 48650 */ // Label 1446: @48650 |
| 17598 | /* 48650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1447*/ GIMT_Encode4(48710), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1827 // |
| 17599 | /* 48657 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu), |
| 17600 | /* 48662 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17601 | /* 48665 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17602 | /* 48668 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17603 | /* 48671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17604 | /* 48675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17605 | /* 48679 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17606 | /* 48683 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17607 | /* 48687 */ // MIs[1] Operand 1 |
| 17608 | /* 48687 */ // No operand predicates |
| 17609 | /* 48687 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17610 | /* 48689 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4048:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xuq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17611 | /* 48689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xuq), |
| 17612 | /* 48692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17613 | /* 48694 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17614 | /* 48696 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17615 | /* 48699 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17616 | /* 48702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17617 | /* 48708 */ GIR_RootConstrainSelectedInstOperands, |
| 17618 | /* 48709 */ // GIR_Coverage, 1827, |
| 17619 | /* 48709 */ GIR_EraseRootFromParent_Done, |
| 17620 | /* 48710 */ // Label 1447: @48710 |
| 17621 | /* 48710 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1448*/ GIMT_Encode4(48770), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1828 // |
| 17622 | /* 48717 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp), |
| 17623 | /* 48722 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17624 | /* 48725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17625 | /* 48728 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17626 | /* 48731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17627 | /* 48735 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17628 | /* 48739 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17629 | /* 48743 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17630 | /* 48747 */ // MIs[1] Operand 1 |
| 17631 | /* 48747 */ // No operand predicates |
| 17632 | /* 48747 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17633 | /* 48749 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4050:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17634 | /* 48749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hq), |
| 17635 | /* 48752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17636 | /* 48754 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17637 | /* 48756 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17638 | /* 48759 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17639 | /* 48762 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17640 | /* 48768 */ GIR_RootConstrainSelectedInstOperands, |
| 17641 | /* 48769 */ // GIR_Coverage, 1828, |
| 17642 | /* 48769 */ GIR_EraseRootFromParent_Done, |
| 17643 | /* 48770 */ // Label 1448: @48770 |
| 17644 | /* 48770 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1449*/ GIMT_Encode4(48830), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1829 // |
| 17645 | /* 48777 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp), |
| 17646 | /* 48782 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 17647 | /* 48785 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 17648 | /* 48788 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17649 | /* 48791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17650 | /* 48795 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 17651 | /* 48799 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17652 | /* 48803 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17653 | /* 48807 */ // MIs[1] Operand 1 |
| 17654 | /* 48807 */ // No operand predicates |
| 17655 | /* 48807 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17656 | /* 48809 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4051:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) |
| 17657 | /* 48809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hq), |
| 17658 | /* 48812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 17659 | /* 48814 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 17660 | /* 48816 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM |
| 17661 | /* 48819 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17662 | /* 48822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17663 | /* 48828 */ GIR_RootConstrainSelectedInstOperands, |
| 17664 | /* 48829 */ // GIR_Coverage, 1829, |
| 17665 | /* 48829 */ GIR_EraseRootFromParent_Done, |
| 17666 | /* 48830 */ // Label 1449: @48830 |
| 17667 | /* 48830 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1450*/ GIMT_Encode4(48890), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1911 // |
| 17668 | /* 48837 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqshl), |
| 17669 | /* 48842 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17670 | /* 48845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17671 | /* 48848 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17672 | /* 48851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17673 | /* 48855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17674 | /* 48859 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17675 | /* 48863 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17676 | /* 48867 */ // MIs[1] Operand 1 |
| 17677 | /* 48867 */ // No operand predicates |
| 17678 | /* 48867 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17679 | /* 48869 */ // (intrinsic_wo_chain:{ *:[i32] } 3862:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 17680 | /* 48869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQSHL), |
| 17681 | /* 48872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 17682 | /* 48874 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 17683 | /* 48876 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 17684 | /* 48879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17685 | /* 48882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17686 | /* 48888 */ GIR_RootConstrainSelectedInstOperands, |
| 17687 | /* 48889 */ // GIR_Coverage, 1911, |
| 17688 | /* 48889 */ GIR_EraseRootFromParent_Done, |
| 17689 | /* 48890 */ // Label 1450: @48890 |
| 17690 | /* 48890 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1451*/ GIMT_Encode4(48950), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1912 // |
| 17691 | /* 48897 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_srshr), |
| 17692 | /* 48902 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17693 | /* 48905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17694 | /* 48908 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17695 | /* 48911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17696 | /* 48915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17697 | /* 48919 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17698 | /* 48923 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17699 | /* 48927 */ // MIs[1] Operand 1 |
| 17700 | /* 48927 */ // No operand predicates |
| 17701 | /* 48927 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17702 | /* 48929 */ // (intrinsic_wo_chain:{ *:[i32] } 3864:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 17703 | /* 48929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SRSHR), |
| 17704 | /* 48932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 17705 | /* 48934 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 17706 | /* 48936 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 17707 | /* 48939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17708 | /* 48942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17709 | /* 48948 */ GIR_RootConstrainSelectedInstOperands, |
| 17710 | /* 48949 */ // GIR_Coverage, 1912, |
| 17711 | /* 48949 */ GIR_EraseRootFromParent_Done, |
| 17712 | /* 48950 */ // Label 1451: @48950 |
| 17713 | /* 48950 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1452*/ GIMT_Encode4(49010), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1913 // |
| 17714 | /* 48957 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqshl), |
| 17715 | /* 48962 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17716 | /* 48965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17717 | /* 48968 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17718 | /* 48971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17719 | /* 48975 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17720 | /* 48979 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17721 | /* 48983 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17722 | /* 48987 */ // MIs[1] Operand 1 |
| 17723 | /* 48987 */ // No operand predicates |
| 17724 | /* 48987 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17725 | /* 48989 */ // (intrinsic_wo_chain:{ *:[i32] } 3869:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_UQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 17726 | /* 48989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQSHL), |
| 17727 | /* 48992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 17728 | /* 48994 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 17729 | /* 48996 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 17730 | /* 48999 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17731 | /* 49002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17732 | /* 49008 */ GIR_RootConstrainSelectedInstOperands, |
| 17733 | /* 49009 */ // GIR_Coverage, 1913, |
| 17734 | /* 49009 */ GIR_EraseRootFromParent_Done, |
| 17735 | /* 49010 */ // Label 1452: @49010 |
| 17736 | /* 49010 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1453*/ GIMT_Encode4(49070), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1914 // |
| 17737 | /* 49017 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_urshr), |
| 17738 | /* 49022 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17739 | /* 49025 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17740 | /* 49028 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17741 | /* 49031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17742 | /* 49035 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 17743 | /* 49039 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 17744 | /* 49043 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 17745 | /* 49047 */ // MIs[1] Operand 1 |
| 17746 | /* 49047 */ // No operand predicates |
| 17747 | /* 49047 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 17748 | /* 49049 */ // (intrinsic_wo_chain:{ *:[i32] } 3871:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_URSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) |
| 17749 | /* 49049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_URSHR), |
| 17750 | /* 49052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 17751 | /* 49054 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 17752 | /* 49056 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 17753 | /* 49059 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17754 | /* 49062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17755 | /* 49068 */ GIR_RootConstrainSelectedInstOperands, |
| 17756 | /* 49069 */ // GIR_Coverage, 1914, |
| 17757 | /* 49069 */ GIR_EraseRootFromParent_Done, |
| 17758 | /* 49070 */ // Label 1453: @49070 |
| 17759 | /* 49070 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1454*/ GIMT_Encode4(49123), GIMT_Encode2(GIFBS_IsARM), // Rule ID 104 // |
| 17760 | /* 49077 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8), |
| 17761 | /* 49082 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17762 | /* 49085 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17763 | /* 49088 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17764 | /* 49091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17765 | /* 49095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17766 | /* 49099 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17767 | /* 49103 */ // (intrinsic_wo_chain:{ *:[i32] } 4150:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17768 | /* 49103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD8), |
| 17769 | /* 49106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17770 | /* 49108 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17771 | /* 49110 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17772 | /* 49112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17773 | /* 49115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17774 | /* 49121 */ GIR_RootConstrainSelectedInstOperands, |
| 17775 | /* 49122 */ // GIR_Coverage, 104, |
| 17776 | /* 49122 */ GIR_EraseRootFromParent_Done, |
| 17777 | /* 49123 */ // Label 1454: @49123 |
| 17778 | /* 49123 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1455*/ GIMT_Encode4(49176), GIMT_Encode2(GIFBS_IsARM), // Rule ID 105 // |
| 17779 | /* 49130 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16), |
| 17780 | /* 49135 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17781 | /* 49138 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17782 | /* 49141 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17783 | /* 49144 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17784 | /* 49148 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17785 | /* 49152 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17786 | /* 49156 */ // (intrinsic_wo_chain:{ *:[i32] } 4149:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17787 | /* 49156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD16), |
| 17788 | /* 49159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17789 | /* 49161 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17790 | /* 49163 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17791 | /* 49165 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17792 | /* 49168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17793 | /* 49174 */ GIR_RootConstrainSelectedInstOperands, |
| 17794 | /* 49175 */ // GIR_Coverage, 105, |
| 17795 | /* 49175 */ GIR_EraseRootFromParent_Done, |
| 17796 | /* 49176 */ // Label 1455: @49176 |
| 17797 | /* 49176 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1456*/ GIMT_Encode4(49229), GIMT_Encode2(GIFBS_IsARM), // Rule ID 106 // |
| 17798 | /* 49183 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16), |
| 17799 | /* 49188 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17800 | /* 49191 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17801 | /* 49194 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17802 | /* 49197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17803 | /* 49201 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17804 | /* 49205 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17805 | /* 49209 */ // (intrinsic_wo_chain:{ *:[i32] } 4154:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17806 | /* 49209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB16), |
| 17807 | /* 49212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17808 | /* 49214 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17809 | /* 49216 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17810 | /* 49218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17811 | /* 49221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17812 | /* 49227 */ GIR_RootConstrainSelectedInstOperands, |
| 17813 | /* 49228 */ // GIR_Coverage, 106, |
| 17814 | /* 49228 */ GIR_EraseRootFromParent_Done, |
| 17815 | /* 49229 */ // Label 1456: @49229 |
| 17816 | /* 49229 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1457*/ GIMT_Encode4(49282), GIMT_Encode2(GIFBS_IsARM), // Rule ID 107 // |
| 17817 | /* 49236 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8), |
| 17818 | /* 49241 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17819 | /* 49244 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17820 | /* 49247 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17821 | /* 49250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17822 | /* 49254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17823 | /* 49258 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17824 | /* 49262 */ // (intrinsic_wo_chain:{ *:[i32] } 4155:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17825 | /* 49262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB8), |
| 17826 | /* 49265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17827 | /* 49267 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17828 | /* 49269 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17829 | /* 49271 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17830 | /* 49274 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17831 | /* 49280 */ GIR_RootConstrainSelectedInstOperands, |
| 17832 | /* 49281 */ // GIR_Coverage, 107, |
| 17833 | /* 49281 */ GIR_EraseRootFromParent_Done, |
| 17834 | /* 49282 */ // Label 1457: @49282 |
| 17835 | /* 49282 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1458*/ GIMT_Encode4(49335), GIMT_Encode2(GIFBS_IsARM), // Rule ID 110 // |
| 17836 | /* 49289 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 17837 | /* 49294 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17838 | /* 49297 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17839 | /* 49300 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17840 | /* 49303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17841 | /* 49307 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17842 | /* 49311 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17843 | /* 49315 */ // (intrinsic_wo_chain:{ *:[i32] } 4153:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 17844 | /* 49315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB), |
| 17845 | /* 49318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17846 | /* 49320 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 17847 | /* 49322 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 17848 | /* 49324 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17849 | /* 49327 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17850 | /* 49333 */ GIR_RootConstrainSelectedInstOperands, |
| 17851 | /* 49334 */ // GIR_Coverage, 110, |
| 17852 | /* 49334 */ GIR_EraseRootFromParent_Done, |
| 17853 | /* 49335 */ // Label 1458: @49335 |
| 17854 | /* 49335 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1459*/ GIMT_Encode4(49388), GIMT_Encode2(GIFBS_IsARM), // Rule ID 111 // |
| 17855 | /* 49342 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 17856 | /* 49347 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17857 | /* 49350 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17858 | /* 49353 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17859 | /* 49356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17860 | /* 49360 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17861 | /* 49364 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17862 | /* 49368 */ // (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) |
| 17863 | /* 49368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD), |
| 17864 | /* 49371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17865 | /* 49373 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 17866 | /* 49375 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 17867 | /* 49377 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17868 | /* 49380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17869 | /* 49386 */ GIR_RootConstrainSelectedInstOperands, |
| 17870 | /* 49387 */ // GIR_Coverage, 111, |
| 17871 | /* 49387 */ GIR_EraseRootFromParent_Done, |
| 17872 | /* 49388 */ // Label 1459: @49388 |
| 17873 | /* 49388 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1460*/ GIMT_Encode4(49441), GIMT_Encode2(GIFBS_IsARM), // Rule ID 112 // |
| 17874 | /* 49395 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16), |
| 17875 | /* 49400 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17876 | /* 49403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17877 | /* 49406 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17878 | /* 49409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17879 | /* 49413 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17880 | /* 49417 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17881 | /* 49421 */ // (intrinsic_wo_chain:{ *:[i32] } 4217:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17882 | /* 49421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD16), |
| 17883 | /* 49424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17884 | /* 49426 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17885 | /* 49428 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17886 | /* 49430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17887 | /* 49433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17888 | /* 49439 */ GIR_RootConstrainSelectedInstOperands, |
| 17889 | /* 49440 */ // GIR_Coverage, 112, |
| 17890 | /* 49440 */ GIR_EraseRootFromParent_Done, |
| 17891 | /* 49441 */ // Label 1460: @49441 |
| 17892 | /* 49441 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1461*/ GIMT_Encode4(49494), GIMT_Encode2(GIFBS_IsARM), // Rule ID 113 // |
| 17893 | /* 49448 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8), |
| 17894 | /* 49453 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17895 | /* 49456 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17896 | /* 49459 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17897 | /* 49462 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17898 | /* 49466 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17899 | /* 49470 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17900 | /* 49474 */ // (intrinsic_wo_chain:{ *:[i32] } 4218:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17901 | /* 49474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD8), |
| 17902 | /* 49477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17903 | /* 49479 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17904 | /* 49481 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17905 | /* 49483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17906 | /* 49486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17907 | /* 49492 */ GIR_RootConstrainSelectedInstOperands, |
| 17908 | /* 49493 */ // GIR_Coverage, 113, |
| 17909 | /* 49493 */ GIR_EraseRootFromParent_Done, |
| 17910 | /* 49494 */ // Label 1461: @49494 |
| 17911 | /* 49494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1462*/ GIMT_Encode4(49547), GIMT_Encode2(GIFBS_IsARM), // Rule ID 114 // |
| 17912 | /* 49501 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16), |
| 17913 | /* 49506 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17914 | /* 49509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17915 | /* 49512 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17916 | /* 49515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17917 | /* 49519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17918 | /* 49523 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17919 | /* 49527 */ // (intrinsic_wo_chain:{ *:[i32] } 4221:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17920 | /* 49527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB16), |
| 17921 | /* 49530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17922 | /* 49532 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17923 | /* 49534 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17924 | /* 49536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17925 | /* 49539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17926 | /* 49545 */ GIR_RootConstrainSelectedInstOperands, |
| 17927 | /* 49546 */ // GIR_Coverage, 114, |
| 17928 | /* 49546 */ GIR_EraseRootFromParent_Done, |
| 17929 | /* 49547 */ // Label 1462: @49547 |
| 17930 | /* 49547 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1463*/ GIMT_Encode4(49600), GIMT_Encode2(GIFBS_IsARM), // Rule ID 115 // |
| 17931 | /* 49554 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8), |
| 17932 | /* 49559 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17933 | /* 49562 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17934 | /* 49565 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17935 | /* 49568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17936 | /* 49572 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17937 | /* 49576 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17938 | /* 49580 */ // (intrinsic_wo_chain:{ *:[i32] } 4222:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17939 | /* 49580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB8), |
| 17940 | /* 49583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17941 | /* 49585 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17942 | /* 49587 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17943 | /* 49589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17944 | /* 49592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17945 | /* 49598 */ GIR_RootConstrainSelectedInstOperands, |
| 17946 | /* 49599 */ // GIR_Coverage, 115, |
| 17947 | /* 49599 */ GIR_EraseRootFromParent_Done, |
| 17948 | /* 49600 */ // Label 1463: @49600 |
| 17949 | /* 49600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1464*/ GIMT_Encode4(49653), GIMT_Encode2(GIFBS_IsARM), // Rule ID 116 // |
| 17950 | /* 49607 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx), |
| 17951 | /* 49612 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17952 | /* 49615 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17953 | /* 49618 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17954 | /* 49621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17955 | /* 49625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17956 | /* 49629 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17957 | /* 49633 */ // (intrinsic_wo_chain:{ *:[i32] } 4151:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17958 | /* 49633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QASX), |
| 17959 | /* 49636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17960 | /* 49638 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17961 | /* 49640 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17962 | /* 49642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17963 | /* 49645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17964 | /* 49651 */ GIR_RootConstrainSelectedInstOperands, |
| 17965 | /* 49652 */ // GIR_Coverage, 116, |
| 17966 | /* 49652 */ GIR_EraseRootFromParent_Done, |
| 17967 | /* 49653 */ // Label 1464: @49653 |
| 17968 | /* 49653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1465*/ GIMT_Encode4(49706), GIMT_Encode2(GIFBS_IsARM), // Rule ID 117 // |
| 17969 | /* 49660 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax), |
| 17970 | /* 49665 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17971 | /* 49668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17972 | /* 49671 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17973 | /* 49674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17974 | /* 49678 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17975 | /* 49682 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17976 | /* 49686 */ // (intrinsic_wo_chain:{ *:[i32] } 4152:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17977 | /* 49686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSAX), |
| 17978 | /* 49689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17979 | /* 49691 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17980 | /* 49693 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 17981 | /* 49695 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 17982 | /* 49698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 17983 | /* 49704 */ GIR_RootConstrainSelectedInstOperands, |
| 17984 | /* 49705 */ // GIR_Coverage, 117, |
| 17985 | /* 49705 */ GIR_EraseRootFromParent_Done, |
| 17986 | /* 49706 */ // Label 1465: @49706 |
| 17987 | /* 49706 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1466*/ GIMT_Encode4(49759), GIMT_Encode2(GIFBS_IsARM), // Rule ID 118 // |
| 17988 | /* 49713 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx), |
| 17989 | /* 49718 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 17990 | /* 49721 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 17991 | /* 49724 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 17992 | /* 49727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17993 | /* 49731 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17994 | /* 49735 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 17995 | /* 49739 */ // (intrinsic_wo_chain:{ *:[i32] } 4219:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 17996 | /* 49739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQASX), |
| 17997 | /* 49742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 17998 | /* 49744 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 17999 | /* 49746 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18000 | /* 49748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18001 | /* 49751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18002 | /* 49757 */ GIR_RootConstrainSelectedInstOperands, |
| 18003 | /* 49758 */ // GIR_Coverage, 118, |
| 18004 | /* 49758 */ GIR_EraseRootFromParent_Done, |
| 18005 | /* 49759 */ // Label 1466: @49759 |
| 18006 | /* 49759 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1467*/ GIMT_Encode4(49812), GIMT_Encode2(GIFBS_IsARM), // Rule ID 119 // |
| 18007 | /* 49766 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax), |
| 18008 | /* 49771 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18009 | /* 49774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18010 | /* 49777 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18011 | /* 49780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18012 | /* 49784 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18013 | /* 49788 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18014 | /* 49792 */ // (intrinsic_wo_chain:{ *:[i32] } 4220:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18015 | /* 49792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSAX), |
| 18016 | /* 49795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18017 | /* 49797 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18018 | /* 49799 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18019 | /* 49801 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18020 | /* 49804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18021 | /* 49810 */ GIR_RootConstrainSelectedInstOperands, |
| 18022 | /* 49811 */ // GIR_Coverage, 119, |
| 18023 | /* 49811 */ GIR_EraseRootFromParent_Done, |
| 18024 | /* 49812 */ // Label 1467: @49812 |
| 18025 | /* 49812 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1468*/ GIMT_Encode4(49865), GIMT_Encode2(GIFBS_IsARM), // Rule ID 132 // |
| 18026 | /* 49819 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx), |
| 18027 | /* 49824 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18028 | /* 49827 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18029 | /* 49830 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18030 | /* 49833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18031 | /* 49837 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18032 | /* 49841 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18033 | /* 49845 */ // (intrinsic_wo_chain:{ *:[i32] } 4163:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18034 | /* 49845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHASX), |
| 18035 | /* 49848 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18036 | /* 49850 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18037 | /* 49852 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18038 | /* 49854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18039 | /* 49857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18040 | /* 49863 */ GIR_RootConstrainSelectedInstOperands, |
| 18041 | /* 49864 */ // GIR_Coverage, 132, |
| 18042 | /* 49864 */ GIR_EraseRootFromParent_Done, |
| 18043 | /* 49865 */ // Label 1468: @49865 |
| 18044 | /* 49865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1469*/ GIMT_Encode4(49918), GIMT_Encode2(GIFBS_IsARM), // Rule ID 133 // |
| 18045 | /* 49872 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16), |
| 18046 | /* 49877 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18047 | /* 49880 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18048 | /* 49883 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18049 | /* 49886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18050 | /* 49890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18051 | /* 49894 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18052 | /* 49898 */ // (intrinsic_wo_chain:{ *:[i32] } 4161:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18053 | /* 49898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD16), |
| 18054 | /* 49901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18055 | /* 49903 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18056 | /* 49905 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18057 | /* 49907 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18058 | /* 49910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18059 | /* 49916 */ GIR_RootConstrainSelectedInstOperands, |
| 18060 | /* 49917 */ // GIR_Coverage, 133, |
| 18061 | /* 49917 */ GIR_EraseRootFromParent_Done, |
| 18062 | /* 49918 */ // Label 1469: @49918 |
| 18063 | /* 49918 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1470*/ GIMT_Encode4(49971), GIMT_Encode2(GIFBS_IsARM), // Rule ID 134 // |
| 18064 | /* 49925 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8), |
| 18065 | /* 49930 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18066 | /* 49933 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18067 | /* 49936 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18068 | /* 49939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18069 | /* 49943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18070 | /* 49947 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18071 | /* 49951 */ // (intrinsic_wo_chain:{ *:[i32] } 4162:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18072 | /* 49951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD8), |
| 18073 | /* 49954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18074 | /* 49956 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18075 | /* 49958 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18076 | /* 49960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18077 | /* 49963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18078 | /* 49969 */ GIR_RootConstrainSelectedInstOperands, |
| 18079 | /* 49970 */ // GIR_Coverage, 134, |
| 18080 | /* 49970 */ GIR_EraseRootFromParent_Done, |
| 18081 | /* 49971 */ // Label 1470: @49971 |
| 18082 | /* 49971 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1471*/ GIMT_Encode4(50024), GIMT_Encode2(GIFBS_IsARM), // Rule ID 135 // |
| 18083 | /* 49978 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax), |
| 18084 | /* 49983 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18085 | /* 49986 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18086 | /* 49989 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18087 | /* 49992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18088 | /* 49996 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18089 | /* 50000 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18090 | /* 50004 */ // (intrinsic_wo_chain:{ *:[i32] } 4164:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18091 | /* 50004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSAX), |
| 18092 | /* 50007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18093 | /* 50009 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18094 | /* 50011 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18095 | /* 50013 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18096 | /* 50016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18097 | /* 50022 */ GIR_RootConstrainSelectedInstOperands, |
| 18098 | /* 50023 */ // GIR_Coverage, 135, |
| 18099 | /* 50023 */ GIR_EraseRootFromParent_Done, |
| 18100 | /* 50024 */ // Label 1471: @50024 |
| 18101 | /* 50024 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1472*/ GIMT_Encode4(50077), GIMT_Encode2(GIFBS_IsARM), // Rule ID 136 // |
| 18102 | /* 50031 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16), |
| 18103 | /* 50036 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18104 | /* 50039 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18105 | /* 50042 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18106 | /* 50045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18107 | /* 50049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18108 | /* 50053 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18109 | /* 50057 */ // (intrinsic_wo_chain:{ *:[i32] } 4165:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18110 | /* 50057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB16), |
| 18111 | /* 50060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18112 | /* 50062 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18113 | /* 50064 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18114 | /* 50066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18115 | /* 50069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18116 | /* 50075 */ GIR_RootConstrainSelectedInstOperands, |
| 18117 | /* 50076 */ // GIR_Coverage, 136, |
| 18118 | /* 50076 */ GIR_EraseRootFromParent_Done, |
| 18119 | /* 50077 */ // Label 1472: @50077 |
| 18120 | /* 50077 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1473*/ GIMT_Encode4(50130), GIMT_Encode2(GIFBS_IsARM), // Rule ID 137 // |
| 18121 | /* 50084 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8), |
| 18122 | /* 50089 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18123 | /* 50092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18124 | /* 50095 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18125 | /* 50098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18126 | /* 50102 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18127 | /* 50106 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18128 | /* 50110 */ // (intrinsic_wo_chain:{ *:[i32] } 4166:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18129 | /* 50110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB8), |
| 18130 | /* 50113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18131 | /* 50115 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18132 | /* 50117 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18133 | /* 50119 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18134 | /* 50122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18135 | /* 50128 */ GIR_RootConstrainSelectedInstOperands, |
| 18136 | /* 50129 */ // GIR_Coverage, 137, |
| 18137 | /* 50129 */ GIR_EraseRootFromParent_Done, |
| 18138 | /* 50130 */ // Label 1473: @50130 |
| 18139 | /* 50130 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1474*/ GIMT_Encode4(50183), GIMT_Encode2(GIFBS_IsARM), // Rule ID 138 // |
| 18140 | /* 50137 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx), |
| 18141 | /* 50142 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18142 | /* 50145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18143 | /* 50148 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18144 | /* 50151 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18145 | /* 50155 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18146 | /* 50159 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18147 | /* 50163 */ // (intrinsic_wo_chain:{ *:[i32] } 4212:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18148 | /* 50163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHASX), |
| 18149 | /* 50166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18150 | /* 50168 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18151 | /* 50170 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18152 | /* 50172 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18153 | /* 50175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18154 | /* 50181 */ GIR_RootConstrainSelectedInstOperands, |
| 18155 | /* 50182 */ // GIR_Coverage, 138, |
| 18156 | /* 50182 */ GIR_EraseRootFromParent_Done, |
| 18157 | /* 50183 */ // Label 1474: @50183 |
| 18158 | /* 50183 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1475*/ GIMT_Encode4(50236), GIMT_Encode2(GIFBS_IsARM), // Rule ID 139 // |
| 18159 | /* 50190 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16), |
| 18160 | /* 50195 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18161 | /* 50198 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18162 | /* 50201 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18163 | /* 50204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18164 | /* 50208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18165 | /* 50212 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18166 | /* 50216 */ // (intrinsic_wo_chain:{ *:[i32] } 4210:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18167 | /* 50216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD16), |
| 18168 | /* 50219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18169 | /* 50221 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18170 | /* 50223 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18171 | /* 50225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18172 | /* 50228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18173 | /* 50234 */ GIR_RootConstrainSelectedInstOperands, |
| 18174 | /* 50235 */ // GIR_Coverage, 139, |
| 18175 | /* 50235 */ GIR_EraseRootFromParent_Done, |
| 18176 | /* 50236 */ // Label 1475: @50236 |
| 18177 | /* 50236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1476*/ GIMT_Encode4(50289), GIMT_Encode2(GIFBS_IsARM), // Rule ID 140 // |
| 18178 | /* 50243 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8), |
| 18179 | /* 50248 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18180 | /* 50251 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18181 | /* 50254 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18182 | /* 50257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18183 | /* 50261 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18184 | /* 50265 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18185 | /* 50269 */ // (intrinsic_wo_chain:{ *:[i32] } 4211:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18186 | /* 50269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD8), |
| 18187 | /* 50272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18188 | /* 50274 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18189 | /* 50276 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18190 | /* 50278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18191 | /* 50281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18192 | /* 50287 */ GIR_RootConstrainSelectedInstOperands, |
| 18193 | /* 50288 */ // GIR_Coverage, 140, |
| 18194 | /* 50288 */ GIR_EraseRootFromParent_Done, |
| 18195 | /* 50289 */ // Label 1476: @50289 |
| 18196 | /* 50289 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1477*/ GIMT_Encode4(50342), GIMT_Encode2(GIFBS_IsARM), // Rule ID 141 // |
| 18197 | /* 50296 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax), |
| 18198 | /* 50301 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18199 | /* 50304 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18200 | /* 50307 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18201 | /* 50310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18202 | /* 50314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18203 | /* 50318 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18204 | /* 50322 */ // (intrinsic_wo_chain:{ *:[i32] } 4213:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18205 | /* 50322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSAX), |
| 18206 | /* 50325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18207 | /* 50327 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18208 | /* 50329 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18209 | /* 50331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18210 | /* 50334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18211 | /* 50340 */ GIR_RootConstrainSelectedInstOperands, |
| 18212 | /* 50341 */ // GIR_Coverage, 141, |
| 18213 | /* 50341 */ GIR_EraseRootFromParent_Done, |
| 18214 | /* 50342 */ // Label 1477: @50342 |
| 18215 | /* 50342 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1478*/ GIMT_Encode4(50395), GIMT_Encode2(GIFBS_IsARM), // Rule ID 142 // |
| 18216 | /* 50349 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16), |
| 18217 | /* 50354 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18218 | /* 50357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18219 | /* 50360 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18220 | /* 50363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18221 | /* 50367 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18222 | /* 50371 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18223 | /* 50375 */ // (intrinsic_wo_chain:{ *:[i32] } 4214:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18224 | /* 50375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB16), |
| 18225 | /* 50378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18226 | /* 50380 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18227 | /* 50382 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18228 | /* 50384 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18229 | /* 50387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18230 | /* 50393 */ GIR_RootConstrainSelectedInstOperands, |
| 18231 | /* 50394 */ // GIR_Coverage, 142, |
| 18232 | /* 50394 */ GIR_EraseRootFromParent_Done, |
| 18233 | /* 50395 */ // Label 1478: @50395 |
| 18234 | /* 50395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1479*/ GIMT_Encode4(50448), GIMT_Encode2(GIFBS_IsARM), // Rule ID 143 // |
| 18235 | /* 50402 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8), |
| 18236 | /* 50407 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18237 | /* 50410 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18238 | /* 50413 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18239 | /* 50416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18240 | /* 50420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18241 | /* 50424 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18242 | /* 50428 */ // (intrinsic_wo_chain:{ *:[i32] } 4215:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18243 | /* 50428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB8), |
| 18244 | /* 50431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18245 | /* 50433 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18246 | /* 50435 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18247 | /* 50437 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18248 | /* 50440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18249 | /* 50446 */ GIR_RootConstrainSelectedInstOperands, |
| 18250 | /* 50447 */ // GIR_Coverage, 143, |
| 18251 | /* 50447 */ GIR_EraseRootFromParent_Done, |
| 18252 | /* 50448 */ // Label 1479: @50448 |
| 18253 | /* 50448 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1480*/ GIMT_Encode4(50501), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 144 // |
| 18254 | /* 50455 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8), |
| 18255 | /* 50460 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18256 | /* 50463 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18257 | /* 50466 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18258 | /* 50469 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 18259 | /* 50473 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 18260 | /* 50477 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 18261 | /* 50481 */ // (intrinsic_wo_chain:{ *:[i32] } 4223:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (USAD8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 18262 | /* 50481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAD8), |
| 18263 | /* 50484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18264 | /* 50486 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18265 | /* 50488 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18266 | /* 50490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18267 | /* 50493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18268 | /* 50499 */ GIR_RootConstrainSelectedInstOperands, |
| 18269 | /* 50500 */ // GIR_Coverage, 144, |
| 18270 | /* 50500 */ GIR_EraseRootFromParent_Done, |
| 18271 | /* 50501 */ // Label 1480: @50501 |
| 18272 | /* 50501 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1481*/ GIMT_Encode4(50545), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 203 // |
| 18273 | /* 50508 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b), |
| 18274 | /* 50513 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18275 | /* 50516 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18276 | /* 50519 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18277 | /* 50522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18278 | /* 50526 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18279 | /* 50530 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18280 | /* 50534 */ // (intrinsic_wo_chain:{ *:[i32] } 3769:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32B:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18281 | /* 50534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32B), |
| 18282 | /* 50537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18283 | /* 50539 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18284 | /* 50541 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18285 | /* 50543 */ GIR_RootConstrainSelectedInstOperands, |
| 18286 | /* 50544 */ // GIR_Coverage, 203, |
| 18287 | /* 50544 */ GIR_EraseRootFromParent_Done, |
| 18288 | /* 50545 */ // Label 1481: @50545 |
| 18289 | /* 50545 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1482*/ GIMT_Encode4(50589), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 204 // |
| 18290 | /* 50552 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb), |
| 18291 | /* 50557 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18292 | /* 50560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18293 | /* 50563 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18294 | /* 50566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18295 | /* 50570 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18296 | /* 50574 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18297 | /* 50578 */ // (intrinsic_wo_chain:{ *:[i32] } 3770:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18298 | /* 50578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CB), |
| 18299 | /* 50581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18300 | /* 50583 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18301 | /* 50585 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18302 | /* 50587 */ GIR_RootConstrainSelectedInstOperands, |
| 18303 | /* 50588 */ // GIR_Coverage, 204, |
| 18304 | /* 50588 */ GIR_EraseRootFromParent_Done, |
| 18305 | /* 50589 */ // Label 1482: @50589 |
| 18306 | /* 50589 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1483*/ GIMT_Encode4(50633), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 205 // |
| 18307 | /* 50596 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h), |
| 18308 | /* 50601 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18309 | /* 50604 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18310 | /* 50607 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18311 | /* 50610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18312 | /* 50614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18313 | /* 50618 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18314 | /* 50622 */ // (intrinsic_wo_chain:{ *:[i32] } 3773:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32H:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18315 | /* 50622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32H), |
| 18316 | /* 50625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18317 | /* 50627 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18318 | /* 50629 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18319 | /* 50631 */ GIR_RootConstrainSelectedInstOperands, |
| 18320 | /* 50632 */ // GIR_Coverage, 205, |
| 18321 | /* 50632 */ GIR_EraseRootFromParent_Done, |
| 18322 | /* 50633 */ // Label 1483: @50633 |
| 18323 | /* 50633 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1484*/ GIMT_Encode4(50677), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 206 // |
| 18324 | /* 50640 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch), |
| 18325 | /* 50645 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18326 | /* 50648 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18327 | /* 50651 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18328 | /* 50654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18329 | /* 50658 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18330 | /* 50662 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18331 | /* 50666 */ // (intrinsic_wo_chain:{ *:[i32] } 3771:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CH:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18332 | /* 50666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CH), |
| 18333 | /* 50669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18334 | /* 50671 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18335 | /* 50673 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18336 | /* 50675 */ GIR_RootConstrainSelectedInstOperands, |
| 18337 | /* 50676 */ // GIR_Coverage, 206, |
| 18338 | /* 50676 */ GIR_EraseRootFromParent_Done, |
| 18339 | /* 50677 */ // Label 1484: @50677 |
| 18340 | /* 50677 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1485*/ GIMT_Encode4(50721), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 207 // |
| 18341 | /* 50684 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w), |
| 18342 | /* 50689 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18343 | /* 50692 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18344 | /* 50695 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18345 | /* 50698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18346 | /* 50702 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18347 | /* 50706 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18348 | /* 50710 */ // (intrinsic_wo_chain:{ *:[i32] } 3774:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32W:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18349 | /* 50710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32W), |
| 18350 | /* 50713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18351 | /* 50715 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18352 | /* 50717 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18353 | /* 50719 */ GIR_RootConstrainSelectedInstOperands, |
| 18354 | /* 50720 */ // GIR_Coverage, 207, |
| 18355 | /* 50720 */ GIR_EraseRootFromParent_Done, |
| 18356 | /* 50721 */ // Label 1485: @50721 |
| 18357 | /* 50721 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1486*/ GIMT_Encode4(50765), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 208 // |
| 18358 | /* 50728 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw), |
| 18359 | /* 50733 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18360 | /* 50736 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18361 | /* 50739 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18362 | /* 50742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18363 | /* 50746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18364 | /* 50750 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 18365 | /* 50754 */ // (intrinsic_wo_chain:{ *:[i32] } 3772:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CW:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 18366 | /* 50754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CW), |
| 18367 | /* 50757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18368 | /* 50759 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18369 | /* 50761 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18370 | /* 50763 */ GIR_RootConstrainSelectedInstOperands, |
| 18371 | /* 50764 */ // GIR_Coverage, 208, |
| 18372 | /* 50764 */ GIR_EraseRootFromParent_Done, |
| 18373 | /* 50765 */ // Label 1486: @50765 |
| 18374 | /* 50765 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1487*/ GIMT_Encode4(50818), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 431 // |
| 18375 | /* 50772 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16), |
| 18376 | /* 50777 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18377 | /* 50780 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18378 | /* 50783 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18379 | /* 50786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18380 | /* 50790 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18381 | /* 50794 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18382 | /* 50798 */ // (intrinsic_wo_chain:{ *:[i32] } 4149:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18383 | /* 50798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD16), |
| 18384 | /* 50801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18385 | /* 50803 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18386 | /* 50805 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18387 | /* 50807 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18388 | /* 50810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18389 | /* 50816 */ GIR_RootConstrainSelectedInstOperands, |
| 18390 | /* 50817 */ // GIR_Coverage, 431, |
| 18391 | /* 50817 */ GIR_EraseRootFromParent_Done, |
| 18392 | /* 50818 */ // Label 1487: @50818 |
| 18393 | /* 50818 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1488*/ GIMT_Encode4(50871), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 432 // |
| 18394 | /* 50825 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8), |
| 18395 | /* 50830 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18396 | /* 50833 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18397 | /* 50836 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18398 | /* 50839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18399 | /* 50843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18400 | /* 50847 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18401 | /* 50851 */ // (intrinsic_wo_chain:{ *:[i32] } 4150:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18402 | /* 50851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD8), |
| 18403 | /* 50854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18404 | /* 50856 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18405 | /* 50858 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18406 | /* 50860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18407 | /* 50863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18408 | /* 50869 */ GIR_RootConstrainSelectedInstOperands, |
| 18409 | /* 50870 */ // GIR_Coverage, 432, |
| 18410 | /* 50870 */ GIR_EraseRootFromParent_Done, |
| 18411 | /* 50871 */ // Label 1488: @50871 |
| 18412 | /* 50871 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1489*/ GIMT_Encode4(50924), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 433 // |
| 18413 | /* 50878 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx), |
| 18414 | /* 50883 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18415 | /* 50886 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18416 | /* 50889 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18417 | /* 50892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18418 | /* 50896 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18419 | /* 50900 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18420 | /* 50904 */ // (intrinsic_wo_chain:{ *:[i32] } 4151:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18421 | /* 50904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QASX), |
| 18422 | /* 50907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18423 | /* 50909 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18424 | /* 50911 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18425 | /* 50913 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18426 | /* 50916 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18427 | /* 50922 */ GIR_RootConstrainSelectedInstOperands, |
| 18428 | /* 50923 */ // GIR_Coverage, 433, |
| 18429 | /* 50923 */ GIR_EraseRootFromParent_Done, |
| 18430 | /* 50924 */ // Label 1489: @50924 |
| 18431 | /* 50924 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1490*/ GIMT_Encode4(50977), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 434 // |
| 18432 | /* 50931 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8), |
| 18433 | /* 50936 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18434 | /* 50939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18435 | /* 50942 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18436 | /* 50945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18437 | /* 50949 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18438 | /* 50953 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18439 | /* 50957 */ // (intrinsic_wo_chain:{ *:[i32] } 4222:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18440 | /* 50957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB8), |
| 18441 | /* 50960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18442 | /* 50962 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18443 | /* 50964 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18444 | /* 50966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18445 | /* 50969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18446 | /* 50975 */ GIR_RootConstrainSelectedInstOperands, |
| 18447 | /* 50976 */ // GIR_Coverage, 434, |
| 18448 | /* 50976 */ GIR_EraseRootFromParent_Done, |
| 18449 | /* 50977 */ // Label 1490: @50977 |
| 18450 | /* 50977 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1491*/ GIMT_Encode4(51030), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 435 // |
| 18451 | /* 50984 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax), |
| 18452 | /* 50989 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18453 | /* 50992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18454 | /* 50995 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18455 | /* 50998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18456 | /* 51002 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18457 | /* 51006 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18458 | /* 51010 */ // (intrinsic_wo_chain:{ *:[i32] } 4152:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18459 | /* 51010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSAX), |
| 18460 | /* 51013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18461 | /* 51015 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18462 | /* 51017 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18463 | /* 51019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18464 | /* 51022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18465 | /* 51028 */ GIR_RootConstrainSelectedInstOperands, |
| 18466 | /* 51029 */ // GIR_Coverage, 435, |
| 18467 | /* 51029 */ GIR_EraseRootFromParent_Done, |
| 18468 | /* 51030 */ // Label 1491: @51030 |
| 18469 | /* 51030 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1492*/ GIMT_Encode4(51083), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 436 // |
| 18470 | /* 51037 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16), |
| 18471 | /* 51042 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18472 | /* 51045 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18473 | /* 51048 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18474 | /* 51051 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18475 | /* 51055 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18476 | /* 51059 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18477 | /* 51063 */ // (intrinsic_wo_chain:{ *:[i32] } 4154:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18478 | /* 51063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB16), |
| 18479 | /* 51066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18480 | /* 51068 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18481 | /* 51070 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18482 | /* 51072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18483 | /* 51075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18484 | /* 51081 */ GIR_RootConstrainSelectedInstOperands, |
| 18485 | /* 51082 */ // GIR_Coverage, 436, |
| 18486 | /* 51082 */ GIR_EraseRootFromParent_Done, |
| 18487 | /* 51083 */ // Label 1492: @51083 |
| 18488 | /* 51083 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1493*/ GIMT_Encode4(51136), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 437 // |
| 18489 | /* 51090 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8), |
| 18490 | /* 51095 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18491 | /* 51098 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18492 | /* 51101 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18493 | /* 51104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18494 | /* 51108 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18495 | /* 51112 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18496 | /* 51116 */ // (intrinsic_wo_chain:{ *:[i32] } 4155:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18497 | /* 51116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB8), |
| 18498 | /* 51119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18499 | /* 51121 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18500 | /* 51123 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18501 | /* 51125 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18502 | /* 51128 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18503 | /* 51134 */ GIR_RootConstrainSelectedInstOperands, |
| 18504 | /* 51135 */ // GIR_Coverage, 437, |
| 18505 | /* 51135 */ GIR_EraseRootFromParent_Done, |
| 18506 | /* 51136 */ // Label 1493: @51136 |
| 18507 | /* 51136 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1494*/ GIMT_Encode4(51189), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 438 // |
| 18508 | /* 51143 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16), |
| 18509 | /* 51148 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18510 | /* 51151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18511 | /* 51154 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18512 | /* 51157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18513 | /* 51161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18514 | /* 51165 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18515 | /* 51169 */ // (intrinsic_wo_chain:{ *:[i32] } 4217:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18516 | /* 51169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD16), |
| 18517 | /* 51172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18518 | /* 51174 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18519 | /* 51176 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18520 | /* 51178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18521 | /* 51181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18522 | /* 51187 */ GIR_RootConstrainSelectedInstOperands, |
| 18523 | /* 51188 */ // GIR_Coverage, 438, |
| 18524 | /* 51188 */ GIR_EraseRootFromParent_Done, |
| 18525 | /* 51189 */ // Label 1494: @51189 |
| 18526 | /* 51189 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1495*/ GIMT_Encode4(51242), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 439 // |
| 18527 | /* 51196 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8), |
| 18528 | /* 51201 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18529 | /* 51204 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18530 | /* 51207 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18531 | /* 51210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18532 | /* 51214 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18533 | /* 51218 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18534 | /* 51222 */ // (intrinsic_wo_chain:{ *:[i32] } 4218:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18535 | /* 51222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD8), |
| 18536 | /* 51225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18537 | /* 51227 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18538 | /* 51229 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18539 | /* 51231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18540 | /* 51234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18541 | /* 51240 */ GIR_RootConstrainSelectedInstOperands, |
| 18542 | /* 51241 */ // GIR_Coverage, 439, |
| 18543 | /* 51241 */ GIR_EraseRootFromParent_Done, |
| 18544 | /* 51242 */ // Label 1495: @51242 |
| 18545 | /* 51242 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1496*/ GIMT_Encode4(51295), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 440 // |
| 18546 | /* 51249 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx), |
| 18547 | /* 51254 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18548 | /* 51257 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18549 | /* 51260 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18550 | /* 51263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18551 | /* 51267 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18552 | /* 51271 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18553 | /* 51275 */ // (intrinsic_wo_chain:{ *:[i32] } 4219:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18554 | /* 51275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQASX), |
| 18555 | /* 51278 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18556 | /* 51280 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18557 | /* 51282 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18558 | /* 51284 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18559 | /* 51287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18560 | /* 51293 */ GIR_RootConstrainSelectedInstOperands, |
| 18561 | /* 51294 */ // GIR_Coverage, 440, |
| 18562 | /* 51294 */ GIR_EraseRootFromParent_Done, |
| 18563 | /* 51295 */ // Label 1496: @51295 |
| 18564 | /* 51295 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1497*/ GIMT_Encode4(51348), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 441 // |
| 18565 | /* 51302 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax), |
| 18566 | /* 51307 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18567 | /* 51310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18568 | /* 51313 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18569 | /* 51316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18570 | /* 51320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18571 | /* 51324 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18572 | /* 51328 */ // (intrinsic_wo_chain:{ *:[i32] } 4220:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18573 | /* 51328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSAX), |
| 18574 | /* 51331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18575 | /* 51333 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18576 | /* 51335 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18577 | /* 51337 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18578 | /* 51340 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18579 | /* 51346 */ GIR_RootConstrainSelectedInstOperands, |
| 18580 | /* 51347 */ // GIR_Coverage, 441, |
| 18581 | /* 51347 */ GIR_EraseRootFromParent_Done, |
| 18582 | /* 51348 */ // Label 1497: @51348 |
| 18583 | /* 51348 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1498*/ GIMT_Encode4(51401), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 442 // |
| 18584 | /* 51355 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16), |
| 18585 | /* 51360 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18586 | /* 51363 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18587 | /* 51366 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18588 | /* 51369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18589 | /* 51373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18590 | /* 51377 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18591 | /* 51381 */ // (intrinsic_wo_chain:{ *:[i32] } 4221:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18592 | /* 51381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB16), |
| 18593 | /* 51384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18594 | /* 51386 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18595 | /* 51388 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18596 | /* 51390 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18597 | /* 51393 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18598 | /* 51399 */ GIR_RootConstrainSelectedInstOperands, |
| 18599 | /* 51400 */ // GIR_Coverage, 442, |
| 18600 | /* 51400 */ GIR_EraseRootFromParent_Done, |
| 18601 | /* 51401 */ // Label 1498: @51401 |
| 18602 | /* 51401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1499*/ GIMT_Encode4(51454), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 455 // |
| 18603 | /* 51408 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx), |
| 18604 | /* 51413 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18605 | /* 51416 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18606 | /* 51419 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18607 | /* 51422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18608 | /* 51426 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18609 | /* 51430 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18610 | /* 51434 */ // (intrinsic_wo_chain:{ *:[i32] } 4163:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18611 | /* 51434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHASX), |
| 18612 | /* 51437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18613 | /* 51439 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18614 | /* 51441 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18615 | /* 51443 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18616 | /* 51446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18617 | /* 51452 */ GIR_RootConstrainSelectedInstOperands, |
| 18618 | /* 51453 */ // GIR_Coverage, 455, |
| 18619 | /* 51453 */ GIR_EraseRootFromParent_Done, |
| 18620 | /* 51454 */ // Label 1499: @51454 |
| 18621 | /* 51454 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1500*/ GIMT_Encode4(51507), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 456 // |
| 18622 | /* 51461 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16), |
| 18623 | /* 51466 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18624 | /* 51469 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18625 | /* 51472 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18626 | /* 51475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18627 | /* 51479 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18628 | /* 51483 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18629 | /* 51487 */ // (intrinsic_wo_chain:{ *:[i32] } 4161:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18630 | /* 51487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD16), |
| 18631 | /* 51490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18632 | /* 51492 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18633 | /* 51494 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18634 | /* 51496 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18635 | /* 51499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18636 | /* 51505 */ GIR_RootConstrainSelectedInstOperands, |
| 18637 | /* 51506 */ // GIR_Coverage, 456, |
| 18638 | /* 51506 */ GIR_EraseRootFromParent_Done, |
| 18639 | /* 51507 */ // Label 1500: @51507 |
| 18640 | /* 51507 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1501*/ GIMT_Encode4(51560), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 457 // |
| 18641 | /* 51514 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8), |
| 18642 | /* 51519 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18643 | /* 51522 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18644 | /* 51525 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18645 | /* 51528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18646 | /* 51532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18647 | /* 51536 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18648 | /* 51540 */ // (intrinsic_wo_chain:{ *:[i32] } 4162:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18649 | /* 51540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD8), |
| 18650 | /* 51543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18651 | /* 51545 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18652 | /* 51547 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18653 | /* 51549 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18654 | /* 51552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18655 | /* 51558 */ GIR_RootConstrainSelectedInstOperands, |
| 18656 | /* 51559 */ // GIR_Coverage, 457, |
| 18657 | /* 51559 */ GIR_EraseRootFromParent_Done, |
| 18658 | /* 51560 */ // Label 1501: @51560 |
| 18659 | /* 51560 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1502*/ GIMT_Encode4(51613), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 458 // |
| 18660 | /* 51567 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax), |
| 18661 | /* 51572 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18662 | /* 51575 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18663 | /* 51578 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18664 | /* 51581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18665 | /* 51585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18666 | /* 51589 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18667 | /* 51593 */ // (intrinsic_wo_chain:{ *:[i32] } 4164:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18668 | /* 51593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSAX), |
| 18669 | /* 51596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18670 | /* 51598 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18671 | /* 51600 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18672 | /* 51602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18673 | /* 51605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18674 | /* 51611 */ GIR_RootConstrainSelectedInstOperands, |
| 18675 | /* 51612 */ // GIR_Coverage, 458, |
| 18676 | /* 51612 */ GIR_EraseRootFromParent_Done, |
| 18677 | /* 51613 */ // Label 1502: @51613 |
| 18678 | /* 51613 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1503*/ GIMT_Encode4(51666), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 459 // |
| 18679 | /* 51620 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16), |
| 18680 | /* 51625 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18681 | /* 51628 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18682 | /* 51631 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18683 | /* 51634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18684 | /* 51638 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18685 | /* 51642 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18686 | /* 51646 */ // (intrinsic_wo_chain:{ *:[i32] } 4165:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18687 | /* 51646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB16), |
| 18688 | /* 51649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18689 | /* 51651 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18690 | /* 51653 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18691 | /* 51655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18692 | /* 51658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18693 | /* 51664 */ GIR_RootConstrainSelectedInstOperands, |
| 18694 | /* 51665 */ // GIR_Coverage, 459, |
| 18695 | /* 51665 */ GIR_EraseRootFromParent_Done, |
| 18696 | /* 51666 */ // Label 1503: @51666 |
| 18697 | /* 51666 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1504*/ GIMT_Encode4(51719), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 460 // |
| 18698 | /* 51673 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8), |
| 18699 | /* 51678 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18700 | /* 51681 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18701 | /* 51684 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18702 | /* 51687 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18703 | /* 51691 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18704 | /* 51695 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18705 | /* 51699 */ // (intrinsic_wo_chain:{ *:[i32] } 4166:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18706 | /* 51699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB8), |
| 18707 | /* 51702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18708 | /* 51704 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18709 | /* 51706 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18710 | /* 51708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18711 | /* 51711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18712 | /* 51717 */ GIR_RootConstrainSelectedInstOperands, |
| 18713 | /* 51718 */ // GIR_Coverage, 460, |
| 18714 | /* 51718 */ GIR_EraseRootFromParent_Done, |
| 18715 | /* 51719 */ // Label 1504: @51719 |
| 18716 | /* 51719 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1505*/ GIMT_Encode4(51772), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 461 // |
| 18717 | /* 51726 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx), |
| 18718 | /* 51731 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18719 | /* 51734 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18720 | /* 51737 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18721 | /* 51740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18722 | /* 51744 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18723 | /* 51748 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18724 | /* 51752 */ // (intrinsic_wo_chain:{ *:[i32] } 4212:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18725 | /* 51752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHASX), |
| 18726 | /* 51755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18727 | /* 51757 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18728 | /* 51759 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18729 | /* 51761 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18730 | /* 51764 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18731 | /* 51770 */ GIR_RootConstrainSelectedInstOperands, |
| 18732 | /* 51771 */ // GIR_Coverage, 461, |
| 18733 | /* 51771 */ GIR_EraseRootFromParent_Done, |
| 18734 | /* 51772 */ // Label 1505: @51772 |
| 18735 | /* 51772 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1506*/ GIMT_Encode4(51825), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 462 // |
| 18736 | /* 51779 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16), |
| 18737 | /* 51784 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18738 | /* 51787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18739 | /* 51790 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18740 | /* 51793 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18741 | /* 51797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18742 | /* 51801 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18743 | /* 51805 */ // (intrinsic_wo_chain:{ *:[i32] } 4210:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18744 | /* 51805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD16), |
| 18745 | /* 51808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18746 | /* 51810 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18747 | /* 51812 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18748 | /* 51814 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18749 | /* 51817 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18750 | /* 51823 */ GIR_RootConstrainSelectedInstOperands, |
| 18751 | /* 51824 */ // GIR_Coverage, 462, |
| 18752 | /* 51824 */ GIR_EraseRootFromParent_Done, |
| 18753 | /* 51825 */ // Label 1506: @51825 |
| 18754 | /* 51825 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1507*/ GIMT_Encode4(51878), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 463 // |
| 18755 | /* 51832 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8), |
| 18756 | /* 51837 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18757 | /* 51840 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18758 | /* 51843 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18759 | /* 51846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18760 | /* 51850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18761 | /* 51854 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18762 | /* 51858 */ // (intrinsic_wo_chain:{ *:[i32] } 4211:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18763 | /* 51858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD8), |
| 18764 | /* 51861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18765 | /* 51863 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18766 | /* 51865 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18767 | /* 51867 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18768 | /* 51870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18769 | /* 51876 */ GIR_RootConstrainSelectedInstOperands, |
| 18770 | /* 51877 */ // GIR_Coverage, 463, |
| 18771 | /* 51877 */ GIR_EraseRootFromParent_Done, |
| 18772 | /* 51878 */ // Label 1507: @51878 |
| 18773 | /* 51878 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1508*/ GIMT_Encode4(51931), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 464 // |
| 18774 | /* 51885 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax), |
| 18775 | /* 51890 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18776 | /* 51893 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18777 | /* 51896 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18778 | /* 51899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18779 | /* 51903 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18780 | /* 51907 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18781 | /* 51911 */ // (intrinsic_wo_chain:{ *:[i32] } 4213:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18782 | /* 51911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSAX), |
| 18783 | /* 51914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18784 | /* 51916 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18785 | /* 51918 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18786 | /* 51920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18787 | /* 51923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18788 | /* 51929 */ GIR_RootConstrainSelectedInstOperands, |
| 18789 | /* 51930 */ // GIR_Coverage, 464, |
| 18790 | /* 51930 */ GIR_EraseRootFromParent_Done, |
| 18791 | /* 51931 */ // Label 1508: @51931 |
| 18792 | /* 51931 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1509*/ GIMT_Encode4(51984), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 465 // |
| 18793 | /* 51938 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16), |
| 18794 | /* 51943 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18795 | /* 51946 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18796 | /* 51949 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18797 | /* 51952 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18798 | /* 51956 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18799 | /* 51960 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18800 | /* 51964 */ // (intrinsic_wo_chain:{ *:[i32] } 4214:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18801 | /* 51964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB16), |
| 18802 | /* 51967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18803 | /* 51969 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18804 | /* 51971 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18805 | /* 51973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18806 | /* 51976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18807 | /* 51982 */ GIR_RootConstrainSelectedInstOperands, |
| 18808 | /* 51983 */ // GIR_Coverage, 465, |
| 18809 | /* 51983 */ GIR_EraseRootFromParent_Done, |
| 18810 | /* 51984 */ // Label 1509: @51984 |
| 18811 | /* 51984 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1510*/ GIMT_Encode4(52037), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 466 // |
| 18812 | /* 51991 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8), |
| 18813 | /* 51996 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18814 | /* 51999 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18815 | /* 52002 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18816 | /* 52005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18817 | /* 52009 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18818 | /* 52013 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18819 | /* 52017 */ // (intrinsic_wo_chain:{ *:[i32] } 4215:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18820 | /* 52017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB8), |
| 18821 | /* 52020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18822 | /* 52022 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18823 | /* 52024 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18824 | /* 52026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18825 | /* 52029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18826 | /* 52035 */ GIR_RootConstrainSelectedInstOperands, |
| 18827 | /* 52036 */ // GIR_Coverage, 466, |
| 18828 | /* 52036 */ GIR_EraseRootFromParent_Done, |
| 18829 | /* 52037 */ // Label 1510: @52037 |
| 18830 | /* 52037 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1511*/ GIMT_Encode4(52090), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 467 // |
| 18831 | /* 52044 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8), |
| 18832 | /* 52049 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18833 | /* 52052 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18834 | /* 52055 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18835 | /* 52058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18836 | /* 52062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18837 | /* 52066 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18838 | /* 52070 */ // (intrinsic_wo_chain:{ *:[i32] } 4223:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18839 | /* 52070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAD8), |
| 18840 | /* 52073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18841 | /* 52075 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18842 | /* 52077 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18843 | /* 52079 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18844 | /* 52082 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18845 | /* 52088 */ GIR_RootConstrainSelectedInstOperands, |
| 18846 | /* 52089 */ // GIR_Coverage, 467, |
| 18847 | /* 52089 */ GIR_EraseRootFromParent_Done, |
| 18848 | /* 52090 */ // Label 1511: @52090 |
| 18849 | /* 52090 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1512*/ GIMT_Encode4(52143), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 523 // |
| 18850 | /* 52097 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad), |
| 18851 | /* 52102 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18852 | /* 52105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18853 | /* 52108 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18854 | /* 52111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18855 | /* 52115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18856 | /* 52119 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18857 | /* 52123 */ // (intrinsic_wo_chain:{ *:[i32] } 4181:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18858 | /* 52123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUAD), |
| 18859 | /* 52126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18860 | /* 52128 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18861 | /* 52130 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18862 | /* 52132 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18863 | /* 52135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18864 | /* 52141 */ GIR_RootConstrainSelectedInstOperands, |
| 18865 | /* 52142 */ // GIR_Coverage, 523, |
| 18866 | /* 52142 */ GIR_EraseRootFromParent_Done, |
| 18867 | /* 52143 */ // Label 1512: @52143 |
| 18868 | /* 52143 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1513*/ GIMT_Encode4(52196), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 524 // |
| 18869 | /* 52150 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx), |
| 18870 | /* 52155 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18871 | /* 52158 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18872 | /* 52161 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18873 | /* 52164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18874 | /* 52168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18875 | /* 52172 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18876 | /* 52176 */ // (intrinsic_wo_chain:{ *:[i32] } 4182:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18877 | /* 52176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUADX), |
| 18878 | /* 52179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18879 | /* 52181 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18880 | /* 52183 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18881 | /* 52185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18882 | /* 52188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18883 | /* 52194 */ GIR_RootConstrainSelectedInstOperands, |
| 18884 | /* 52195 */ // GIR_Coverage, 524, |
| 18885 | /* 52195 */ GIR_EraseRootFromParent_Done, |
| 18886 | /* 52196 */ // Label 1513: @52196 |
| 18887 | /* 52196 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1514*/ GIMT_Encode4(52249), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 525 // |
| 18888 | /* 52203 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd), |
| 18889 | /* 52208 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18890 | /* 52211 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18891 | /* 52214 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18892 | /* 52217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18893 | /* 52221 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18894 | /* 52225 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18895 | /* 52229 */ // (intrinsic_wo_chain:{ *:[i32] } 4189:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18896 | /* 52229 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSD), |
| 18897 | /* 52232 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18898 | /* 52234 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18899 | /* 52236 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18900 | /* 52238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18901 | /* 52241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18902 | /* 52247 */ GIR_RootConstrainSelectedInstOperands, |
| 18903 | /* 52248 */ // GIR_Coverage, 525, |
| 18904 | /* 52248 */ GIR_EraseRootFromParent_Done, |
| 18905 | /* 52249 */ // Label 1514: @52249 |
| 18906 | /* 52249 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1515*/ GIMT_Encode4(52302), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 526 // |
| 18907 | /* 52256 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx), |
| 18908 | /* 52261 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18909 | /* 52264 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18910 | /* 52267 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18911 | /* 52270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18912 | /* 52274 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18913 | /* 52278 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18914 | /* 52282 */ // (intrinsic_wo_chain:{ *:[i32] } 4190:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18915 | /* 52282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSDX), |
| 18916 | /* 52285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18917 | /* 52287 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18918 | /* 52289 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18919 | /* 52291 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 18920 | /* 52294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 18921 | /* 52300 */ GIR_RootConstrainSelectedInstOperands, |
| 18922 | /* 52301 */ // GIR_Coverage, 526, |
| 18923 | /* 52301 */ GIR_EraseRootFromParent_Done, |
| 18924 | /* 52302 */ // Label 1515: @52302 |
| 18925 | /* 52302 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1516*/ GIMT_Encode4(52346), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 540 // |
| 18926 | /* 52309 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b), |
| 18927 | /* 52314 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18928 | /* 52317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18929 | /* 52320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18930 | /* 52323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18931 | /* 52327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18932 | /* 52331 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18933 | /* 52335 */ // (intrinsic_wo_chain:{ *:[i32] } 3769:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32B:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18934 | /* 52335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32B), |
| 18935 | /* 52338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18936 | /* 52340 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18937 | /* 52342 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18938 | /* 52344 */ GIR_RootConstrainSelectedInstOperands, |
| 18939 | /* 52345 */ // GIR_Coverage, 540, |
| 18940 | /* 52345 */ GIR_EraseRootFromParent_Done, |
| 18941 | /* 52346 */ // Label 1516: @52346 |
| 18942 | /* 52346 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1517*/ GIMT_Encode4(52390), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 541 // |
| 18943 | /* 52353 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb), |
| 18944 | /* 52358 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18945 | /* 52361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18946 | /* 52364 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18947 | /* 52367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18948 | /* 52371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18949 | /* 52375 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18950 | /* 52379 */ // (intrinsic_wo_chain:{ *:[i32] } 3770:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18951 | /* 52379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CB), |
| 18952 | /* 52382 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18953 | /* 52384 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18954 | /* 52386 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18955 | /* 52388 */ GIR_RootConstrainSelectedInstOperands, |
| 18956 | /* 52389 */ // GIR_Coverage, 541, |
| 18957 | /* 52389 */ GIR_EraseRootFromParent_Done, |
| 18958 | /* 52390 */ // Label 1517: @52390 |
| 18959 | /* 52390 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1518*/ GIMT_Encode4(52434), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 542 // |
| 18960 | /* 52397 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h), |
| 18961 | /* 52402 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18962 | /* 52405 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18963 | /* 52408 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18964 | /* 52411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18965 | /* 52415 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18966 | /* 52419 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18967 | /* 52423 */ // (intrinsic_wo_chain:{ *:[i32] } 3773:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32H:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18968 | /* 52423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32H), |
| 18969 | /* 52426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18970 | /* 52428 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18971 | /* 52430 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18972 | /* 52432 */ GIR_RootConstrainSelectedInstOperands, |
| 18973 | /* 52433 */ // GIR_Coverage, 542, |
| 18974 | /* 52433 */ GIR_EraseRootFromParent_Done, |
| 18975 | /* 52434 */ // Label 1518: @52434 |
| 18976 | /* 52434 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1519*/ GIMT_Encode4(52478), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 543 // |
| 18977 | /* 52441 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch), |
| 18978 | /* 52446 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18979 | /* 52449 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18980 | /* 52452 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18981 | /* 52455 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18982 | /* 52459 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18983 | /* 52463 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18984 | /* 52467 */ // (intrinsic_wo_chain:{ *:[i32] } 3771:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 18985 | /* 52467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CH), |
| 18986 | /* 52470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 18987 | /* 52472 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 18988 | /* 52474 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 18989 | /* 52476 */ GIR_RootConstrainSelectedInstOperands, |
| 18990 | /* 52477 */ // GIR_Coverage, 543, |
| 18991 | /* 52477 */ GIR_EraseRootFromParent_Done, |
| 18992 | /* 52478 */ // Label 1519: @52478 |
| 18993 | /* 52478 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1520*/ GIMT_Encode4(52522), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 544 // |
| 18994 | /* 52485 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w), |
| 18995 | /* 52490 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 18996 | /* 52493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 18997 | /* 52496 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 18998 | /* 52499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 18999 | /* 52503 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19000 | /* 52507 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19001 | /* 52511 */ // (intrinsic_wo_chain:{ *:[i32] } 3774:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32W:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19002 | /* 52511 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32W), |
| 19003 | /* 52514 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19004 | /* 52516 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19005 | /* 52518 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19006 | /* 52520 */ GIR_RootConstrainSelectedInstOperands, |
| 19007 | /* 52521 */ // GIR_Coverage, 544, |
| 19008 | /* 52521 */ GIR_EraseRootFromParent_Done, |
| 19009 | /* 52522 */ // Label 1520: @52522 |
| 19010 | /* 52522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1521*/ GIMT_Encode4(52566), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 545 // |
| 19011 | /* 52529 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw), |
| 19012 | /* 52534 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 19013 | /* 52537 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 19014 | /* 52540 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 19015 | /* 52543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19016 | /* 52547 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19017 | /* 52551 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 19018 | /* 52555 */ // (intrinsic_wo_chain:{ *:[i32] } 3772:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CW:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 19019 | /* 52555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CW), |
| 19020 | /* 52558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 19021 | /* 52560 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 19022 | /* 52562 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 19023 | /* 52564 */ GIR_RootConstrainSelectedInstOperands, |
| 19024 | /* 52565 */ // GIR_Coverage, 545, |
| 19025 | /* 52565 */ GIR_EraseRootFromParent_Done, |
| 19026 | /* 52566 */ // Label 1521: @52566 |
| 19027 | /* 52566 */ GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(52888), |
| 19028 | /* 52571 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds), |
| 19029 | /* 52576 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1529*/ GIMT_Encode4(52887), |
| 19030 | /* 52587 */ /*GILLT_v8s8*//*Label 1523*/ GIMT_Encode4(52611), |
| 19031 | /* 52591 */ /*GILLT_v16s8*//*Label 1524*/ GIMT_Encode4(52657), |
| 19032 | /* 52595 */ /*GILLT_v4s16*//*Label 1525*/ GIMT_Encode4(52703), |
| 19033 | /* 52599 */ /*GILLT_v8s16*//*Label 1526*/ GIMT_Encode4(52749), |
| 19034 | /* 52603 */ /*GILLT_v2s32*//*Label 1527*/ GIMT_Encode4(52795), |
| 19035 | /* 52607 */ /*GILLT_v4s32*//*Label 1528*/ GIMT_Encode4(52841), |
| 19036 | /* 52611 */ // Label 1523: @52611 |
| 19037 | /* 52611 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1530*/ GIMT_Encode4(52656), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 916 // |
| 19038 | /* 52618 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19039 | /* 52621 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19040 | /* 52624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19041 | /* 52628 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19042 | /* 52632 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19043 | /* 52636 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4059:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19044 | /* 52636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i8), |
| 19045 | /* 52639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19046 | /* 52641 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19047 | /* 52643 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19048 | /* 52645 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19049 | /* 52648 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19050 | /* 52654 */ GIR_RootConstrainSelectedInstOperands, |
| 19051 | /* 52655 */ // GIR_Coverage, 916, |
| 19052 | /* 52655 */ GIR_EraseRootFromParent_Done, |
| 19053 | /* 52656 */ // Label 1530: @52656 |
| 19054 | /* 52656 */ GIM_Reject, |
| 19055 | /* 52657 */ // Label 1524: @52657 |
| 19056 | /* 52657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1531*/ GIMT_Encode4(52702), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 917 // |
| 19057 | /* 52664 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19058 | /* 52667 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19059 | /* 52670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19060 | /* 52674 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19061 | /* 52678 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19062 | /* 52682 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4059:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 19063 | /* 52682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv16i8), |
| 19064 | /* 52685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19065 | /* 52687 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19066 | /* 52689 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19067 | /* 52691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19068 | /* 52694 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19069 | /* 52700 */ GIR_RootConstrainSelectedInstOperands, |
| 19070 | /* 52701 */ // GIR_Coverage, 917, |
| 19071 | /* 52701 */ GIR_EraseRootFromParent_Done, |
| 19072 | /* 52702 */ // Label 1531: @52702 |
| 19073 | /* 52702 */ GIM_Reject, |
| 19074 | /* 52703 */ // Label 1525: @52703 |
| 19075 | /* 52703 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1532*/ GIMT_Encode4(52748), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 912 // |
| 19076 | /* 52710 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19077 | /* 52713 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19078 | /* 52716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19079 | /* 52720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19080 | /* 52724 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19081 | /* 52728 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4059:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19082 | /* 52728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i16), |
| 19083 | /* 52731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19084 | /* 52733 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19085 | /* 52735 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19086 | /* 52737 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19087 | /* 52740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19088 | /* 52746 */ GIR_RootConstrainSelectedInstOperands, |
| 19089 | /* 52747 */ // GIR_Coverage, 912, |
| 19090 | /* 52747 */ GIR_EraseRootFromParent_Done, |
| 19091 | /* 52748 */ // Label 1532: @52748 |
| 19092 | /* 52748 */ GIM_Reject, |
| 19093 | /* 52749 */ // Label 1526: @52749 |
| 19094 | /* 52749 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1533*/ GIMT_Encode4(52794), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 914 // |
| 19095 | /* 52756 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19096 | /* 52759 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19097 | /* 52762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19098 | /* 52766 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19099 | /* 52770 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19100 | /* 52774 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4059:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19101 | /* 52774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i16), |
| 19102 | /* 52777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19103 | /* 52779 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19104 | /* 52781 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19105 | /* 52783 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19106 | /* 52786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19107 | /* 52792 */ GIR_RootConstrainSelectedInstOperands, |
| 19108 | /* 52793 */ // GIR_Coverage, 914, |
| 19109 | /* 52793 */ GIR_EraseRootFromParent_Done, |
| 19110 | /* 52794 */ // Label 1533: @52794 |
| 19111 | /* 52794 */ GIM_Reject, |
| 19112 | /* 52795 */ // Label 1527: @52795 |
| 19113 | /* 52795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1534*/ GIMT_Encode4(52840), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 913 // |
| 19114 | /* 52802 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19115 | /* 52805 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19116 | /* 52808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19117 | /* 52812 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19118 | /* 52816 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19119 | /* 52820 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4059:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19120 | /* 52820 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv2i32), |
| 19121 | /* 52823 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19122 | /* 52825 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19123 | /* 52827 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19124 | /* 52829 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19125 | /* 52832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19126 | /* 52838 */ GIR_RootConstrainSelectedInstOperands, |
| 19127 | /* 52839 */ // GIR_Coverage, 913, |
| 19128 | /* 52839 */ GIR_EraseRootFromParent_Done, |
| 19129 | /* 52840 */ // Label 1534: @52840 |
| 19130 | /* 52840 */ GIM_Reject, |
| 19131 | /* 52841 */ // Label 1528: @52841 |
| 19132 | /* 52841 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1535*/ GIMT_Encode4(52886), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 915 // |
| 19133 | /* 52848 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19134 | /* 52851 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19135 | /* 52854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19136 | /* 52858 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19137 | /* 52862 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19138 | /* 52866 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4059:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19139 | /* 52866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i32), |
| 19140 | /* 52869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19141 | /* 52871 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19142 | /* 52873 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19143 | /* 52875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19144 | /* 52878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19145 | /* 52884 */ GIR_RootConstrainSelectedInstOperands, |
| 19146 | /* 52885 */ // GIR_Coverage, 915, |
| 19147 | /* 52885 */ GIR_EraseRootFromParent_Done, |
| 19148 | /* 52886 */ // Label 1535: @52886 |
| 19149 | /* 52886 */ GIM_Reject, |
| 19150 | /* 52887 */ // Label 1529: @52887 |
| 19151 | /* 52887 */ GIM_Reject, |
| 19152 | /* 52888 */ // Label 1522: @52888 |
| 19153 | /* 52888 */ GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(53210), |
| 19154 | /* 52893 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu), |
| 19155 | /* 52898 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1543*/ GIMT_Encode4(53209), |
| 19156 | /* 52909 */ /*GILLT_v8s8*//*Label 1537*/ GIMT_Encode4(52933), |
| 19157 | /* 52913 */ /*GILLT_v16s8*//*Label 1538*/ GIMT_Encode4(52979), |
| 19158 | /* 52917 */ /*GILLT_v4s16*//*Label 1539*/ GIMT_Encode4(53025), |
| 19159 | /* 52921 */ /*GILLT_v8s16*//*Label 1540*/ GIMT_Encode4(53071), |
| 19160 | /* 52925 */ /*GILLT_v2s32*//*Label 1541*/ GIMT_Encode4(53117), |
| 19161 | /* 52929 */ /*GILLT_v4s32*//*Label 1542*/ GIMT_Encode4(53163), |
| 19162 | /* 52933 */ // Label 1537: @52933 |
| 19163 | /* 52933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1544*/ GIMT_Encode4(52978), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 922 // |
| 19164 | /* 52940 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19165 | /* 52943 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19166 | /* 52946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19167 | /* 52950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19168 | /* 52954 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19169 | /* 52958 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4060:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19170 | /* 52958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i8), |
| 19171 | /* 52961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19172 | /* 52963 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19173 | /* 52965 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19174 | /* 52967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19175 | /* 52970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19176 | /* 52976 */ GIR_RootConstrainSelectedInstOperands, |
| 19177 | /* 52977 */ // GIR_Coverage, 922, |
| 19178 | /* 52977 */ GIR_EraseRootFromParent_Done, |
| 19179 | /* 52978 */ // Label 1544: @52978 |
| 19180 | /* 52978 */ GIM_Reject, |
| 19181 | /* 52979 */ // Label 1538: @52979 |
| 19182 | /* 52979 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1545*/ GIMT_Encode4(53024), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 923 // |
| 19183 | /* 52986 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19184 | /* 52989 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19185 | /* 52992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19186 | /* 52996 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19187 | /* 53000 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19188 | /* 53004 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4060:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 19189 | /* 53004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv16i8), |
| 19190 | /* 53007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19191 | /* 53009 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19192 | /* 53011 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19193 | /* 53013 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19194 | /* 53016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19195 | /* 53022 */ GIR_RootConstrainSelectedInstOperands, |
| 19196 | /* 53023 */ // GIR_Coverage, 923, |
| 19197 | /* 53023 */ GIR_EraseRootFromParent_Done, |
| 19198 | /* 53024 */ // Label 1545: @53024 |
| 19199 | /* 53024 */ GIM_Reject, |
| 19200 | /* 53025 */ // Label 1539: @53025 |
| 19201 | /* 53025 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1546*/ GIMT_Encode4(53070), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 918 // |
| 19202 | /* 53032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19203 | /* 53035 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19204 | /* 53038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19205 | /* 53042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19206 | /* 53046 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19207 | /* 53050 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4060:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19208 | /* 53050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i16), |
| 19209 | /* 53053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19210 | /* 53055 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19211 | /* 53057 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19212 | /* 53059 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19213 | /* 53062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19214 | /* 53068 */ GIR_RootConstrainSelectedInstOperands, |
| 19215 | /* 53069 */ // GIR_Coverage, 918, |
| 19216 | /* 53069 */ GIR_EraseRootFromParent_Done, |
| 19217 | /* 53070 */ // Label 1546: @53070 |
| 19218 | /* 53070 */ GIM_Reject, |
| 19219 | /* 53071 */ // Label 1540: @53071 |
| 19220 | /* 53071 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1547*/ GIMT_Encode4(53116), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 920 // |
| 19221 | /* 53078 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19222 | /* 53081 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19223 | /* 53084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19224 | /* 53088 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19225 | /* 53092 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19226 | /* 53096 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4060:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19227 | /* 53096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i16), |
| 19228 | /* 53099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19229 | /* 53101 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19230 | /* 53103 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19231 | /* 53105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19232 | /* 53108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19233 | /* 53114 */ GIR_RootConstrainSelectedInstOperands, |
| 19234 | /* 53115 */ // GIR_Coverage, 920, |
| 19235 | /* 53115 */ GIR_EraseRootFromParent_Done, |
| 19236 | /* 53116 */ // Label 1547: @53116 |
| 19237 | /* 53116 */ GIM_Reject, |
| 19238 | /* 53117 */ // Label 1541: @53117 |
| 19239 | /* 53117 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1548*/ GIMT_Encode4(53162), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 919 // |
| 19240 | /* 53124 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19241 | /* 53127 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19242 | /* 53130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19243 | /* 53134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19244 | /* 53138 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19245 | /* 53142 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4060:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19246 | /* 53142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv2i32), |
| 19247 | /* 53145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19248 | /* 53147 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19249 | /* 53149 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19250 | /* 53151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19251 | /* 53154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19252 | /* 53160 */ GIR_RootConstrainSelectedInstOperands, |
| 19253 | /* 53161 */ // GIR_Coverage, 919, |
| 19254 | /* 53161 */ GIR_EraseRootFromParent_Done, |
| 19255 | /* 53162 */ // Label 1548: @53162 |
| 19256 | /* 53162 */ GIM_Reject, |
| 19257 | /* 53163 */ // Label 1542: @53163 |
| 19258 | /* 53163 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1549*/ GIMT_Encode4(53208), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 921 // |
| 19259 | /* 53170 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19260 | /* 53173 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19261 | /* 53176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19262 | /* 53180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19263 | /* 53184 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19264 | /* 53188 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4060:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19265 | /* 53188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i32), |
| 19266 | /* 53191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19267 | /* 53193 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19268 | /* 53195 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19269 | /* 53197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19270 | /* 53200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19271 | /* 53206 */ GIR_RootConstrainSelectedInstOperands, |
| 19272 | /* 53207 */ // GIR_Coverage, 921, |
| 19273 | /* 53207 */ GIR_EraseRootFromParent_Done, |
| 19274 | /* 53208 */ // Label 1549: @53208 |
| 19275 | /* 53208 */ GIM_Reject, |
| 19276 | /* 53209 */ // Label 1543: @53209 |
| 19277 | /* 53209 */ GIM_Reject, |
| 19278 | /* 53210 */ // Label 1536: @53210 |
| 19279 | /* 53210 */ GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(53532), |
| 19280 | /* 53215 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds), |
| 19281 | /* 53220 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1557*/ GIMT_Encode4(53531), |
| 19282 | /* 53231 */ /*GILLT_v8s8*//*Label 1551*/ GIMT_Encode4(53255), |
| 19283 | /* 53235 */ /*GILLT_v16s8*//*Label 1552*/ GIMT_Encode4(53301), |
| 19284 | /* 53239 */ /*GILLT_v4s16*//*Label 1553*/ GIMT_Encode4(53347), |
| 19285 | /* 53243 */ /*GILLT_v8s16*//*Label 1554*/ GIMT_Encode4(53393), |
| 19286 | /* 53247 */ /*GILLT_v2s32*//*Label 1555*/ GIMT_Encode4(53439), |
| 19287 | /* 53251 */ /*GILLT_v4s32*//*Label 1556*/ GIMT_Encode4(53485), |
| 19288 | /* 53255 */ // Label 1551: @53255 |
| 19289 | /* 53255 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1558*/ GIMT_Encode4(53300), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 928 // |
| 19290 | /* 53262 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19291 | /* 53265 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19292 | /* 53268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19293 | /* 53272 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19294 | /* 53276 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19295 | /* 53280 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4119:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19296 | /* 53280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i8), |
| 19297 | /* 53283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19298 | /* 53285 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19299 | /* 53287 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19300 | /* 53289 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19301 | /* 53292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19302 | /* 53298 */ GIR_RootConstrainSelectedInstOperands, |
| 19303 | /* 53299 */ // GIR_Coverage, 928, |
| 19304 | /* 53299 */ GIR_EraseRootFromParent_Done, |
| 19305 | /* 53300 */ // Label 1558: @53300 |
| 19306 | /* 53300 */ GIM_Reject, |
| 19307 | /* 53301 */ // Label 1552: @53301 |
| 19308 | /* 53301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1559*/ GIMT_Encode4(53346), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 929 // |
| 19309 | /* 53308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19310 | /* 53311 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19311 | /* 53314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19312 | /* 53318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19313 | /* 53322 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19314 | /* 53326 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4119:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 19315 | /* 53326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv16i8), |
| 19316 | /* 53329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19317 | /* 53331 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19318 | /* 53333 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19319 | /* 53335 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19320 | /* 53338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19321 | /* 53344 */ GIR_RootConstrainSelectedInstOperands, |
| 19322 | /* 53345 */ // GIR_Coverage, 929, |
| 19323 | /* 53345 */ GIR_EraseRootFromParent_Done, |
| 19324 | /* 53346 */ // Label 1559: @53346 |
| 19325 | /* 53346 */ GIM_Reject, |
| 19326 | /* 53347 */ // Label 1553: @53347 |
| 19327 | /* 53347 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1560*/ GIMT_Encode4(53392), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 924 // |
| 19328 | /* 53354 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19329 | /* 53357 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19330 | /* 53360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19331 | /* 53364 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19332 | /* 53368 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19333 | /* 53372 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4119:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19334 | /* 53372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i16), |
| 19335 | /* 53375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19336 | /* 53377 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19337 | /* 53379 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19338 | /* 53381 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19339 | /* 53384 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19340 | /* 53390 */ GIR_RootConstrainSelectedInstOperands, |
| 19341 | /* 53391 */ // GIR_Coverage, 924, |
| 19342 | /* 53391 */ GIR_EraseRootFromParent_Done, |
| 19343 | /* 53392 */ // Label 1560: @53392 |
| 19344 | /* 53392 */ GIM_Reject, |
| 19345 | /* 53393 */ // Label 1554: @53393 |
| 19346 | /* 53393 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1561*/ GIMT_Encode4(53438), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 926 // |
| 19347 | /* 53400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19348 | /* 53403 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19349 | /* 53406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19350 | /* 53410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19351 | /* 53414 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19352 | /* 53418 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4119:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19353 | /* 53418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i16), |
| 19354 | /* 53421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19355 | /* 53423 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19356 | /* 53425 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19357 | /* 53427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19358 | /* 53430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19359 | /* 53436 */ GIR_RootConstrainSelectedInstOperands, |
| 19360 | /* 53437 */ // GIR_Coverage, 926, |
| 19361 | /* 53437 */ GIR_EraseRootFromParent_Done, |
| 19362 | /* 53438 */ // Label 1561: @53438 |
| 19363 | /* 53438 */ GIM_Reject, |
| 19364 | /* 53439 */ // Label 1555: @53439 |
| 19365 | /* 53439 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1562*/ GIMT_Encode4(53484), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 925 // |
| 19366 | /* 53446 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19367 | /* 53449 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19368 | /* 53452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19369 | /* 53456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19370 | /* 53460 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19371 | /* 53464 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4119:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19372 | /* 53464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv2i32), |
| 19373 | /* 53467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19374 | /* 53469 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19375 | /* 53471 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19376 | /* 53473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19377 | /* 53476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19378 | /* 53482 */ GIR_RootConstrainSelectedInstOperands, |
| 19379 | /* 53483 */ // GIR_Coverage, 925, |
| 19380 | /* 53483 */ GIR_EraseRootFromParent_Done, |
| 19381 | /* 53484 */ // Label 1562: @53484 |
| 19382 | /* 53484 */ GIM_Reject, |
| 19383 | /* 53485 */ // Label 1556: @53485 |
| 19384 | /* 53485 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1563*/ GIMT_Encode4(53530), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 927 // |
| 19385 | /* 53492 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19386 | /* 53495 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19387 | /* 53498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19388 | /* 53502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19389 | /* 53506 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19390 | /* 53510 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4119:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19391 | /* 53510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i32), |
| 19392 | /* 53513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19393 | /* 53515 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19394 | /* 53517 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19395 | /* 53519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19396 | /* 53522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19397 | /* 53528 */ GIR_RootConstrainSelectedInstOperands, |
| 19398 | /* 53529 */ // GIR_Coverage, 927, |
| 19399 | /* 53529 */ GIR_EraseRootFromParent_Done, |
| 19400 | /* 53530 */ // Label 1563: @53530 |
| 19401 | /* 53530 */ GIM_Reject, |
| 19402 | /* 53531 */ // Label 1557: @53531 |
| 19403 | /* 53531 */ GIM_Reject, |
| 19404 | /* 53532 */ // Label 1550: @53532 |
| 19405 | /* 53532 */ GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(53854), |
| 19406 | /* 53537 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu), |
| 19407 | /* 53542 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1571*/ GIMT_Encode4(53853), |
| 19408 | /* 53553 */ /*GILLT_v8s8*//*Label 1565*/ GIMT_Encode4(53577), |
| 19409 | /* 53557 */ /*GILLT_v16s8*//*Label 1566*/ GIMT_Encode4(53623), |
| 19410 | /* 53561 */ /*GILLT_v4s16*//*Label 1567*/ GIMT_Encode4(53669), |
| 19411 | /* 53565 */ /*GILLT_v8s16*//*Label 1568*/ GIMT_Encode4(53715), |
| 19412 | /* 53569 */ /*GILLT_v2s32*//*Label 1569*/ GIMT_Encode4(53761), |
| 19413 | /* 53573 */ /*GILLT_v4s32*//*Label 1570*/ GIMT_Encode4(53807), |
| 19414 | /* 53577 */ // Label 1565: @53577 |
| 19415 | /* 53577 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1572*/ GIMT_Encode4(53622), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 934 // |
| 19416 | /* 53584 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19417 | /* 53587 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19418 | /* 53590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19419 | /* 53594 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19420 | /* 53598 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19421 | /* 53602 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4120:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19422 | /* 53602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i8), |
| 19423 | /* 53605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19424 | /* 53607 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19425 | /* 53609 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19426 | /* 53611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19427 | /* 53614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19428 | /* 53620 */ GIR_RootConstrainSelectedInstOperands, |
| 19429 | /* 53621 */ // GIR_Coverage, 934, |
| 19430 | /* 53621 */ GIR_EraseRootFromParent_Done, |
| 19431 | /* 53622 */ // Label 1572: @53622 |
| 19432 | /* 53622 */ GIM_Reject, |
| 19433 | /* 53623 */ // Label 1566: @53623 |
| 19434 | /* 53623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1573*/ GIMT_Encode4(53668), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 935 // |
| 19435 | /* 53630 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19436 | /* 53633 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19437 | /* 53636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19438 | /* 53640 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19439 | /* 53644 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19440 | /* 53648 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4120:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 19441 | /* 53648 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv16i8), |
| 19442 | /* 53651 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19443 | /* 53653 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19444 | /* 53655 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19445 | /* 53657 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19446 | /* 53660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19447 | /* 53666 */ GIR_RootConstrainSelectedInstOperands, |
| 19448 | /* 53667 */ // GIR_Coverage, 935, |
| 19449 | /* 53667 */ GIR_EraseRootFromParent_Done, |
| 19450 | /* 53668 */ // Label 1573: @53668 |
| 19451 | /* 53668 */ GIM_Reject, |
| 19452 | /* 53669 */ // Label 1567: @53669 |
| 19453 | /* 53669 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1574*/ GIMT_Encode4(53714), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 930 // |
| 19454 | /* 53676 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19455 | /* 53679 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19456 | /* 53682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19457 | /* 53686 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19458 | /* 53690 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19459 | /* 53694 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4120:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19460 | /* 53694 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i16), |
| 19461 | /* 53697 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19462 | /* 53699 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19463 | /* 53701 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19464 | /* 53703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19465 | /* 53706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19466 | /* 53712 */ GIR_RootConstrainSelectedInstOperands, |
| 19467 | /* 53713 */ // GIR_Coverage, 930, |
| 19468 | /* 53713 */ GIR_EraseRootFromParent_Done, |
| 19469 | /* 53714 */ // Label 1574: @53714 |
| 19470 | /* 53714 */ GIM_Reject, |
| 19471 | /* 53715 */ // Label 1568: @53715 |
| 19472 | /* 53715 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1575*/ GIMT_Encode4(53760), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 932 // |
| 19473 | /* 53722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19474 | /* 53725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19475 | /* 53728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19476 | /* 53732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19477 | /* 53736 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19478 | /* 53740 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4120:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19479 | /* 53740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i16), |
| 19480 | /* 53743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19481 | /* 53745 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19482 | /* 53747 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19483 | /* 53749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19484 | /* 53752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19485 | /* 53758 */ GIR_RootConstrainSelectedInstOperands, |
| 19486 | /* 53759 */ // GIR_Coverage, 932, |
| 19487 | /* 53759 */ GIR_EraseRootFromParent_Done, |
| 19488 | /* 53760 */ // Label 1575: @53760 |
| 19489 | /* 53760 */ GIM_Reject, |
| 19490 | /* 53761 */ // Label 1569: @53761 |
| 19491 | /* 53761 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1576*/ GIMT_Encode4(53806), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 931 // |
| 19492 | /* 53768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19493 | /* 53771 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19494 | /* 53774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19495 | /* 53778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19496 | /* 53782 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19497 | /* 53786 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4120:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19498 | /* 53786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv2i32), |
| 19499 | /* 53789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19500 | /* 53791 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19501 | /* 53793 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19502 | /* 53795 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19503 | /* 53798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19504 | /* 53804 */ GIR_RootConstrainSelectedInstOperands, |
| 19505 | /* 53805 */ // GIR_Coverage, 931, |
| 19506 | /* 53805 */ GIR_EraseRootFromParent_Done, |
| 19507 | /* 53806 */ // Label 1576: @53806 |
| 19508 | /* 53806 */ GIM_Reject, |
| 19509 | /* 53807 */ // Label 1570: @53807 |
| 19510 | /* 53807 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1577*/ GIMT_Encode4(53852), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 933 // |
| 19511 | /* 53814 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19512 | /* 53817 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19513 | /* 53820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19514 | /* 53824 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19515 | /* 53828 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19516 | /* 53832 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4120:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19517 | /* 53832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i32), |
| 19518 | /* 53835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19519 | /* 53837 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19520 | /* 53839 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19521 | /* 53841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19522 | /* 53844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19523 | /* 53850 */ GIR_RootConstrainSelectedInstOperands, |
| 19524 | /* 53851 */ // GIR_Coverage, 933, |
| 19525 | /* 53851 */ GIR_EraseRootFromParent_Done, |
| 19526 | /* 53852 */ // Label 1577: @53852 |
| 19527 | /* 53852 */ GIM_Reject, |
| 19528 | /* 53853 */ // Label 1571: @53853 |
| 19529 | /* 53853 */ GIM_Reject, |
| 19530 | /* 53854 */ // Label 1564: @53854 |
| 19531 | /* 53854 */ GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(54034), |
| 19532 | /* 53859 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn), |
| 19533 | /* 53864 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1582*/ GIMT_Encode4(54033), |
| 19534 | /* 53875 */ /*GILLT_v8s8*//*Label 1579*/ GIMT_Encode4(53895), GIMT_Encode4(0), |
| 19535 | /* 53883 */ /*GILLT_v4s16*//*Label 1580*/ GIMT_Encode4(53941), GIMT_Encode4(0), |
| 19536 | /* 53891 */ /*GILLT_v2s32*//*Label 1581*/ GIMT_Encode4(53987), |
| 19537 | /* 53895 */ // Label 1579: @53895 |
| 19538 | /* 53895 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1583*/ GIMT_Encode4(53940), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 952 // |
| 19539 | /* 53902 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19540 | /* 53905 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19541 | /* 53908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19542 | /* 53912 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19543 | /* 53916 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19544 | /* 53920 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4116:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRADDHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19545 | /* 53920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv8i8), |
| 19546 | /* 53923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19547 | /* 53925 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19548 | /* 53927 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19549 | /* 53929 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19550 | /* 53932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19551 | /* 53938 */ GIR_RootConstrainSelectedInstOperands, |
| 19552 | /* 53939 */ // GIR_Coverage, 952, |
| 19553 | /* 53939 */ GIR_EraseRootFromParent_Done, |
| 19554 | /* 53940 */ // Label 1583: @53940 |
| 19555 | /* 53940 */ GIM_Reject, |
| 19556 | /* 53941 */ // Label 1580: @53941 |
| 19557 | /* 53941 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1584*/ GIMT_Encode4(53986), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 953 // |
| 19558 | /* 53948 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19559 | /* 53951 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19560 | /* 53954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19561 | /* 53958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19562 | /* 53962 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19563 | /* 53966 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4116:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRADDHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19564 | /* 53966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv4i16), |
| 19565 | /* 53969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19566 | /* 53971 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19567 | /* 53973 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19568 | /* 53975 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19569 | /* 53978 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19570 | /* 53984 */ GIR_RootConstrainSelectedInstOperands, |
| 19571 | /* 53985 */ // GIR_Coverage, 953, |
| 19572 | /* 53985 */ GIR_EraseRootFromParent_Done, |
| 19573 | /* 53986 */ // Label 1584: @53986 |
| 19574 | /* 53986 */ GIM_Reject, |
| 19575 | /* 53987 */ // Label 1581: @53987 |
| 19576 | /* 53987 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1585*/ GIMT_Encode4(54032), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 954 // |
| 19577 | /* 53994 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 19578 | /* 53997 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 19579 | /* 54000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19580 | /* 54004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19581 | /* 54008 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19582 | /* 54012 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4116:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRADDHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 19583 | /* 54012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv2i32), |
| 19584 | /* 54015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19585 | /* 54017 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19586 | /* 54019 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19587 | /* 54021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19588 | /* 54024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19589 | /* 54030 */ GIR_RootConstrainSelectedInstOperands, |
| 19590 | /* 54031 */ // GIR_Coverage, 954, |
| 19591 | /* 54031 */ GIR_EraseRootFromParent_Done, |
| 19592 | /* 54032 */ // Label 1585: @54032 |
| 19593 | /* 54032 */ GIM_Reject, |
| 19594 | /* 54033 */ // Label 1582: @54033 |
| 19595 | /* 54033 */ GIM_Reject, |
| 19596 | /* 54034 */ // Label 1578: @54034 |
| 19597 | /* 54034 */ GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(54156), |
| 19598 | /* 54039 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp), |
| 19599 | /* 54044 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 1589*/ GIMT_Encode4(54155), |
| 19600 | /* 54055 */ /*GILLT_v8s8*//*Label 1587*/ GIMT_Encode4(54063), |
| 19601 | /* 54059 */ /*GILLT_v16s8*//*Label 1588*/ GIMT_Encode4(54109), |
| 19602 | /* 54063 */ // Label 1587: @54063 |
| 19603 | /* 54063 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1590*/ GIMT_Encode4(54108), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 961 // |
| 19604 | /* 54070 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19605 | /* 54073 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19606 | /* 54076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19607 | /* 54080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19608 | /* 54084 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19609 | /* 54088 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4085:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULpd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19610 | /* 54088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpd), |
| 19611 | /* 54091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19612 | /* 54093 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19613 | /* 54095 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19614 | /* 54097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19615 | /* 54100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19616 | /* 54106 */ GIR_RootConstrainSelectedInstOperands, |
| 19617 | /* 54107 */ // GIR_Coverage, 961, |
| 19618 | /* 54107 */ GIR_EraseRootFromParent_Done, |
| 19619 | /* 54108 */ // Label 1590: @54108 |
| 19620 | /* 54108 */ GIM_Reject, |
| 19621 | /* 54109 */ // Label 1588: @54109 |
| 19622 | /* 54109 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1591*/ GIMT_Encode4(54154), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 962 // |
| 19623 | /* 54116 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19624 | /* 54119 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19625 | /* 54122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19626 | /* 54126 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19627 | /* 54130 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19628 | /* 54134 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4085:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULpq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 19629 | /* 54134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpq), |
| 19630 | /* 54137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19631 | /* 54139 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19632 | /* 54141 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19633 | /* 54143 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19634 | /* 54146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19635 | /* 54152 */ GIR_RootConstrainSelectedInstOperands, |
| 19636 | /* 54153 */ // GIR_Coverage, 962, |
| 19637 | /* 54153 */ GIR_EraseRootFromParent_Done, |
| 19638 | /* 54154 */ // Label 1591: @54154 |
| 19639 | /* 54154 */ GIM_Reject, |
| 19640 | /* 54155 */ // Label 1589: @54155 |
| 19641 | /* 54155 */ GIM_Reject, |
| 19642 | /* 54156 */ // Label 1586: @54156 |
| 19643 | /* 54156 */ GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(54378), |
| 19644 | /* 54161 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh), |
| 19645 | /* 54166 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1597*/ GIMT_Encode4(54377), |
| 19646 | /* 54177 */ /*GILLT_v4s16*//*Label 1593*/ GIMT_Encode4(54193), |
| 19647 | /* 54181 */ /*GILLT_v8s16*//*Label 1594*/ GIMT_Encode4(54239), |
| 19648 | /* 54185 */ /*GILLT_v2s32*//*Label 1595*/ GIMT_Encode4(54285), |
| 19649 | /* 54189 */ /*GILLT_v4s32*//*Label 1596*/ GIMT_Encode4(54331), |
| 19650 | /* 54193 */ // Label 1593: @54193 |
| 19651 | /* 54193 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1598*/ GIMT_Encode4(54238), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 975 // |
| 19652 | /* 54200 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19653 | /* 54203 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19654 | /* 54206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19655 | /* 54210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19656 | /* 54214 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19657 | /* 54218 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4096:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19658 | /* 54218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i16), |
| 19659 | /* 54221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19660 | /* 54223 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19661 | /* 54225 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19662 | /* 54227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19663 | /* 54230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19664 | /* 54236 */ GIR_RootConstrainSelectedInstOperands, |
| 19665 | /* 54237 */ // GIR_Coverage, 975, |
| 19666 | /* 54237 */ GIR_EraseRootFromParent_Done, |
| 19667 | /* 54238 */ // Label 1598: @54238 |
| 19668 | /* 54238 */ GIM_Reject, |
| 19669 | /* 54239 */ // Label 1594: @54239 |
| 19670 | /* 54239 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1599*/ GIMT_Encode4(54284), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 977 // |
| 19671 | /* 54246 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19672 | /* 54249 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19673 | /* 54252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19674 | /* 54256 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19675 | /* 54260 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19676 | /* 54264 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4096:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19677 | /* 54264 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv8i16), |
| 19678 | /* 54267 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19679 | /* 54269 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19680 | /* 54271 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19681 | /* 54273 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19682 | /* 54276 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19683 | /* 54282 */ GIR_RootConstrainSelectedInstOperands, |
| 19684 | /* 54283 */ // GIR_Coverage, 977, |
| 19685 | /* 54283 */ GIR_EraseRootFromParent_Done, |
| 19686 | /* 54284 */ // Label 1599: @54284 |
| 19687 | /* 54284 */ GIM_Reject, |
| 19688 | /* 54285 */ // Label 1595: @54285 |
| 19689 | /* 54285 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1600*/ GIMT_Encode4(54330), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 976 // |
| 19690 | /* 54292 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19691 | /* 54295 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19692 | /* 54298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19693 | /* 54302 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19694 | /* 54306 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19695 | /* 54310 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4096:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19696 | /* 54310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv2i32), |
| 19697 | /* 54313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19698 | /* 54315 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19699 | /* 54317 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19700 | /* 54319 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19701 | /* 54322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19702 | /* 54328 */ GIR_RootConstrainSelectedInstOperands, |
| 19703 | /* 54329 */ // GIR_Coverage, 976, |
| 19704 | /* 54329 */ GIR_EraseRootFromParent_Done, |
| 19705 | /* 54330 */ // Label 1600: @54330 |
| 19706 | /* 54330 */ GIM_Reject, |
| 19707 | /* 54331 */ // Label 1596: @54331 |
| 19708 | /* 54331 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1601*/ GIMT_Encode4(54376), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 978 // |
| 19709 | /* 54338 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19710 | /* 54341 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19711 | /* 54344 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19712 | /* 54348 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19713 | /* 54352 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19714 | /* 54356 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4096:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19715 | /* 54356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i32), |
| 19716 | /* 54359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19717 | /* 54361 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19718 | /* 54363 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19719 | /* 54365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19720 | /* 54368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19721 | /* 54374 */ GIR_RootConstrainSelectedInstOperands, |
| 19722 | /* 54375 */ // GIR_Coverage, 978, |
| 19723 | /* 54375 */ GIR_EraseRootFromParent_Done, |
| 19724 | /* 54376 */ // Label 1601: @54376 |
| 19725 | /* 54376 */ GIM_Reject, |
| 19726 | /* 54377 */ // Label 1597: @54377 |
| 19727 | /* 54377 */ GIM_Reject, |
| 19728 | /* 54378 */ // Label 1592: @54378 |
| 19729 | /* 54378 */ GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(54600), |
| 19730 | /* 54383 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh), |
| 19731 | /* 54388 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1607*/ GIMT_Encode4(54599), |
| 19732 | /* 54399 */ /*GILLT_v4s16*//*Label 1603*/ GIMT_Encode4(54415), |
| 19733 | /* 54403 */ /*GILLT_v8s16*//*Label 1604*/ GIMT_Encode4(54461), |
| 19734 | /* 54407 */ /*GILLT_v2s32*//*Label 1605*/ GIMT_Encode4(54507), |
| 19735 | /* 54411 */ /*GILLT_v4s32*//*Label 1606*/ GIMT_Encode4(54553), |
| 19736 | /* 54415 */ // Label 1603: @54415 |
| 19737 | /* 54415 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1608*/ GIMT_Encode4(54460), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 983 // |
| 19738 | /* 54422 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19739 | /* 54425 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19740 | /* 54428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19741 | /* 54432 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19742 | /* 54436 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19743 | /* 54440 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4104:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19744 | /* 54440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i16), |
| 19745 | /* 54443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19746 | /* 54445 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19747 | /* 54447 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19748 | /* 54449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19749 | /* 54452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19750 | /* 54458 */ GIR_RootConstrainSelectedInstOperands, |
| 19751 | /* 54459 */ // GIR_Coverage, 983, |
| 19752 | /* 54459 */ GIR_EraseRootFromParent_Done, |
| 19753 | /* 54460 */ // Label 1608: @54460 |
| 19754 | /* 54460 */ GIM_Reject, |
| 19755 | /* 54461 */ // Label 1604: @54461 |
| 19756 | /* 54461 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1609*/ GIMT_Encode4(54506), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 985 // |
| 19757 | /* 54468 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19758 | /* 54471 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19759 | /* 54474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19760 | /* 54478 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19761 | /* 54482 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19762 | /* 54486 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4104:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19763 | /* 54486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv8i16), |
| 19764 | /* 54489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19765 | /* 54491 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19766 | /* 54493 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19767 | /* 54495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19768 | /* 54498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19769 | /* 54504 */ GIR_RootConstrainSelectedInstOperands, |
| 19770 | /* 54505 */ // GIR_Coverage, 985, |
| 19771 | /* 54505 */ GIR_EraseRootFromParent_Done, |
| 19772 | /* 54506 */ // Label 1609: @54506 |
| 19773 | /* 54506 */ GIM_Reject, |
| 19774 | /* 54507 */ // Label 1605: @54507 |
| 19775 | /* 54507 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1610*/ GIMT_Encode4(54552), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 984 // |
| 19776 | /* 54514 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19777 | /* 54517 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19778 | /* 54520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19779 | /* 54524 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19780 | /* 54528 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19781 | /* 54532 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4104:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19782 | /* 54532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv2i32), |
| 19783 | /* 54535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19784 | /* 54537 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19785 | /* 54539 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19786 | /* 54541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19787 | /* 54544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19788 | /* 54550 */ GIR_RootConstrainSelectedInstOperands, |
| 19789 | /* 54551 */ // GIR_Coverage, 984, |
| 19790 | /* 54551 */ GIR_EraseRootFromParent_Done, |
| 19791 | /* 54552 */ // Label 1610: @54552 |
| 19792 | /* 54552 */ GIM_Reject, |
| 19793 | /* 54553 */ // Label 1606: @54553 |
| 19794 | /* 54553 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1611*/ GIMT_Encode4(54598), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 986 // |
| 19795 | /* 54560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 19796 | /* 54563 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 19797 | /* 54566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19798 | /* 54570 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19799 | /* 54574 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19800 | /* 54578 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4104:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 19801 | /* 54578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i32), |
| 19802 | /* 54581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19803 | /* 54583 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19804 | /* 54585 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19805 | /* 54587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19806 | /* 54590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19807 | /* 54596 */ GIR_RootConstrainSelectedInstOperands, |
| 19808 | /* 54597 */ // GIR_Coverage, 986, |
| 19809 | /* 54597 */ GIR_EraseRootFromParent_Done, |
| 19810 | /* 54598 */ // Label 1611: @54598 |
| 19811 | /* 54598 */ GIM_Reject, |
| 19812 | /* 54599 */ // Label 1607: @54599 |
| 19813 | /* 54599 */ GIM_Reject, |
| 19814 | /* 54600 */ // Label 1602: @54600 |
| 19815 | /* 54600 */ GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(54721), |
| 19816 | /* 54605 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp), |
| 19817 | /* 54610 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 1615*/ GIMT_Encode4(54720), |
| 19818 | /* 54621 */ /*GILLT_v8s16*//*Label 1613*/ GIMT_Encode4(54637), GIMT_Encode4(0), GIMT_Encode4(0), |
| 19819 | /* 54633 */ /*GILLT_v2s64*//*Label 1614*/ GIMT_Encode4(54683), |
| 19820 | /* 54637 */ // Label 1613: @54637 |
| 19821 | /* 54637 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1616*/ GIMT_Encode4(54682), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 997 // |
| 19822 | /* 54644 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19823 | /* 54647 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19824 | /* 54650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19825 | /* 54654 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19826 | /* 54658 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19827 | /* 54662 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4082:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULLp8:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19828 | /* 54662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp8), |
| 19829 | /* 54665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19830 | /* 54667 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19831 | /* 54669 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19832 | /* 54671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19833 | /* 54674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19834 | /* 54680 */ GIR_RootConstrainSelectedInstOperands, |
| 19835 | /* 54681 */ // GIR_Coverage, 997, |
| 19836 | /* 54681 */ GIR_EraseRootFromParent_Done, |
| 19837 | /* 54682 */ // Label 1616: @54682 |
| 19838 | /* 54682 */ GIM_Reject, |
| 19839 | /* 54683 */ // Label 1614: @54683 |
| 19840 | /* 54683 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1617*/ GIMT_Encode4(54719), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 998 // |
| 19841 | /* 54690 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 19842 | /* 54693 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 19843 | /* 54696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19844 | /* 54700 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19845 | /* 54704 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19846 | /* 54708 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4082:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VMULLp64:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 19847 | /* 54708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp64), |
| 19848 | /* 54711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19849 | /* 54713 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19850 | /* 54715 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19851 | /* 54717 */ GIR_RootConstrainSelectedInstOperands, |
| 19852 | /* 54718 */ // GIR_Coverage, 998, |
| 19853 | /* 54718 */ GIR_EraseRootFromParent_Done, |
| 19854 | /* 54719 */ // Label 1617: @54719 |
| 19855 | /* 54719 */ GIM_Reject, |
| 19856 | /* 54720 */ // Label 1615: @54720 |
| 19857 | /* 54720 */ GIM_Reject, |
| 19858 | /* 54721 */ // Label 1612: @54721 |
| 19859 | /* 54721 */ GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(54843), |
| 19860 | /* 54726 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 19861 | /* 54731 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 1621*/ GIMT_Encode4(54842), |
| 19862 | /* 54742 */ /*GILLT_v4s32*//*Label 1619*/ GIMT_Encode4(54750), |
| 19863 | /* 54746 */ /*GILLT_v2s64*//*Label 1620*/ GIMT_Encode4(54796), |
| 19864 | /* 54750 */ // Label 1619: @54750 |
| 19865 | /* 54750 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1622*/ GIMT_Encode4(54795), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1003 // |
| 19866 | /* 54757 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19867 | /* 54760 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19868 | /* 54763 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19869 | /* 54767 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19870 | /* 54771 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19871 | /* 54775 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4097:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULLv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19872 | /* 54775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv4i32), |
| 19873 | /* 54778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19874 | /* 54780 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19875 | /* 54782 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19876 | /* 54784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19877 | /* 54787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19878 | /* 54793 */ GIR_RootConstrainSelectedInstOperands, |
| 19879 | /* 54794 */ // GIR_Coverage, 1003, |
| 19880 | /* 54794 */ GIR_EraseRootFromParent_Done, |
| 19881 | /* 54795 */ // Label 1622: @54795 |
| 19882 | /* 54795 */ GIM_Reject, |
| 19883 | /* 54796 */ // Label 1620: @54796 |
| 19884 | /* 54796 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1623*/ GIMT_Encode4(54841), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1004 // |
| 19885 | /* 54803 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19886 | /* 54806 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19887 | /* 54809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19888 | /* 54813 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19889 | /* 54817 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19890 | /* 54821 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4097:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULLv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19891 | /* 54821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv2i64), |
| 19892 | /* 54824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19893 | /* 54826 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19894 | /* 54828 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19895 | /* 54830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19896 | /* 54833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19897 | /* 54839 */ GIR_RootConstrainSelectedInstOperands, |
| 19898 | /* 54840 */ // GIR_Coverage, 1004, |
| 19899 | /* 54840 */ GIR_EraseRootFromParent_Done, |
| 19900 | /* 54841 */ // Label 1623: @54841 |
| 19901 | /* 54841 */ GIM_Reject, |
| 19902 | /* 54842 */ // Label 1621: @54842 |
| 19903 | /* 54842 */ GIM_Reject, |
| 19904 | /* 54843 */ // Label 1618: @54843 |
| 19905 | /* 54843 */ GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(55165), |
| 19906 | /* 54848 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs), |
| 19907 | /* 54853 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1631*/ GIMT_Encode4(55164), |
| 19908 | /* 54864 */ /*GILLT_v8s8*//*Label 1625*/ GIMT_Encode4(54888), |
| 19909 | /* 54868 */ /*GILLT_v16s8*//*Label 1626*/ GIMT_Encode4(54934), |
| 19910 | /* 54872 */ /*GILLT_v4s16*//*Label 1627*/ GIMT_Encode4(54980), |
| 19911 | /* 54876 */ /*GILLT_v8s16*//*Label 1628*/ GIMT_Encode4(55026), |
| 19912 | /* 54880 */ /*GILLT_v2s32*//*Label 1629*/ GIMT_Encode4(55072), |
| 19913 | /* 54884 */ /*GILLT_v4s32*//*Label 1630*/ GIMT_Encode4(55118), |
| 19914 | /* 54888 */ // Label 1625: @54888 |
| 19915 | /* 54888 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1632*/ GIMT_Encode4(54933), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1162 // |
| 19916 | /* 54895 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 19917 | /* 54898 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 19918 | /* 54901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19919 | /* 54905 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19920 | /* 54909 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19921 | /* 54913 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4061:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 19922 | /* 54913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i8), |
| 19923 | /* 54916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19924 | /* 54918 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19925 | /* 54920 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19926 | /* 54922 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19927 | /* 54925 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19928 | /* 54931 */ GIR_RootConstrainSelectedInstOperands, |
| 19929 | /* 54932 */ // GIR_Coverage, 1162, |
| 19930 | /* 54932 */ GIR_EraseRootFromParent_Done, |
| 19931 | /* 54933 */ // Label 1632: @54933 |
| 19932 | /* 54933 */ GIM_Reject, |
| 19933 | /* 54934 */ // Label 1626: @54934 |
| 19934 | /* 54934 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1633*/ GIMT_Encode4(54979), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1163 // |
| 19935 | /* 54941 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 19936 | /* 54944 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 19937 | /* 54947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19938 | /* 54951 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19939 | /* 54955 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19940 | /* 54959 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4061:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 19941 | /* 54959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv16i8), |
| 19942 | /* 54962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19943 | /* 54964 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19944 | /* 54966 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19945 | /* 54968 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19946 | /* 54971 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19947 | /* 54977 */ GIR_RootConstrainSelectedInstOperands, |
| 19948 | /* 54978 */ // GIR_Coverage, 1163, |
| 19949 | /* 54978 */ GIR_EraseRootFromParent_Done, |
| 19950 | /* 54979 */ // Label 1633: @54979 |
| 19951 | /* 54979 */ GIM_Reject, |
| 19952 | /* 54980 */ // Label 1627: @54980 |
| 19953 | /* 54980 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1634*/ GIMT_Encode4(55025), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1158 // |
| 19954 | /* 54987 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 19955 | /* 54990 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 19956 | /* 54993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19957 | /* 54997 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19958 | /* 55001 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19959 | /* 55005 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4061:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 19960 | /* 55005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i16), |
| 19961 | /* 55008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19962 | /* 55010 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19963 | /* 55012 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19964 | /* 55014 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19965 | /* 55017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19966 | /* 55023 */ GIR_RootConstrainSelectedInstOperands, |
| 19967 | /* 55024 */ // GIR_Coverage, 1158, |
| 19968 | /* 55024 */ GIR_EraseRootFromParent_Done, |
| 19969 | /* 55025 */ // Label 1634: @55025 |
| 19970 | /* 55025 */ GIM_Reject, |
| 19971 | /* 55026 */ // Label 1628: @55026 |
| 19972 | /* 55026 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1635*/ GIMT_Encode4(55071), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1160 // |
| 19973 | /* 55033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 19974 | /* 55036 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 19975 | /* 55039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19976 | /* 55043 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19977 | /* 55047 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 19978 | /* 55051 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4061:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 19979 | /* 55051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i16), |
| 19980 | /* 55054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 19981 | /* 55056 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 19982 | /* 55058 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 19983 | /* 55060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 19984 | /* 55063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 19985 | /* 55069 */ GIR_RootConstrainSelectedInstOperands, |
| 19986 | /* 55070 */ // GIR_Coverage, 1160, |
| 19987 | /* 55070 */ GIR_EraseRootFromParent_Done, |
| 19988 | /* 55071 */ // Label 1635: @55071 |
| 19989 | /* 55071 */ GIM_Reject, |
| 19990 | /* 55072 */ // Label 1629: @55072 |
| 19991 | /* 55072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1636*/ GIMT_Encode4(55117), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1159 // |
| 19992 | /* 55079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 19993 | /* 55082 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 19994 | /* 55085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19995 | /* 55089 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19996 | /* 55093 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 19997 | /* 55097 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4061:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 19998 | /* 55097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv2i32), |
| 19999 | /* 55100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20000 | /* 55102 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20001 | /* 55104 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20002 | /* 55106 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20003 | /* 55109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20004 | /* 55115 */ GIR_RootConstrainSelectedInstOperands, |
| 20005 | /* 55116 */ // GIR_Coverage, 1159, |
| 20006 | /* 55116 */ GIR_EraseRootFromParent_Done, |
| 20007 | /* 55117 */ // Label 1636: @55117 |
| 20008 | /* 55117 */ GIM_Reject, |
| 20009 | /* 55118 */ // Label 1630: @55118 |
| 20010 | /* 55118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1637*/ GIMT_Encode4(55163), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1161 // |
| 20011 | /* 55125 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20012 | /* 55128 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20013 | /* 55131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20014 | /* 55135 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20015 | /* 55139 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20016 | /* 55143 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4061:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 20017 | /* 55143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i32), |
| 20018 | /* 55146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20019 | /* 55148 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20020 | /* 55150 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20021 | /* 55152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20022 | /* 55155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20023 | /* 55161 */ GIR_RootConstrainSelectedInstOperands, |
| 20024 | /* 55162 */ // GIR_Coverage, 1161, |
| 20025 | /* 55162 */ GIR_EraseRootFromParent_Done, |
| 20026 | /* 55163 */ // Label 1637: @55163 |
| 20027 | /* 55163 */ GIM_Reject, |
| 20028 | /* 55164 */ // Label 1631: @55164 |
| 20029 | /* 55164 */ GIM_Reject, |
| 20030 | /* 55165 */ // Label 1624: @55165 |
| 20031 | /* 55165 */ GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(55487), |
| 20032 | /* 55170 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu), |
| 20033 | /* 55175 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1645*/ GIMT_Encode4(55486), |
| 20034 | /* 55186 */ /*GILLT_v8s8*//*Label 1639*/ GIMT_Encode4(55210), |
| 20035 | /* 55190 */ /*GILLT_v16s8*//*Label 1640*/ GIMT_Encode4(55256), |
| 20036 | /* 55194 */ /*GILLT_v4s16*//*Label 1641*/ GIMT_Encode4(55302), |
| 20037 | /* 55198 */ /*GILLT_v8s16*//*Label 1642*/ GIMT_Encode4(55348), |
| 20038 | /* 55202 */ /*GILLT_v2s32*//*Label 1643*/ GIMT_Encode4(55394), |
| 20039 | /* 55206 */ /*GILLT_v4s32*//*Label 1644*/ GIMT_Encode4(55440), |
| 20040 | /* 55210 */ // Label 1639: @55210 |
| 20041 | /* 55210 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1646*/ GIMT_Encode4(55255), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1168 // |
| 20042 | /* 55217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20043 | /* 55220 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20044 | /* 55223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20045 | /* 55227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20046 | /* 55231 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20047 | /* 55235 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4062:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 20048 | /* 55235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i8), |
| 20049 | /* 55238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20050 | /* 55240 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20051 | /* 55242 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20052 | /* 55244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20053 | /* 55247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20054 | /* 55253 */ GIR_RootConstrainSelectedInstOperands, |
| 20055 | /* 55254 */ // GIR_Coverage, 1168, |
| 20056 | /* 55254 */ GIR_EraseRootFromParent_Done, |
| 20057 | /* 55255 */ // Label 1646: @55255 |
| 20058 | /* 55255 */ GIM_Reject, |
| 20059 | /* 55256 */ // Label 1640: @55256 |
| 20060 | /* 55256 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1647*/ GIMT_Encode4(55301), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1169 // |
| 20061 | /* 55263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 20062 | /* 55266 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20063 | /* 55269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20064 | /* 55273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20065 | /* 55277 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20066 | /* 55281 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4062:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 20067 | /* 55281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv16i8), |
| 20068 | /* 55284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20069 | /* 55286 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20070 | /* 55288 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20071 | /* 55290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20072 | /* 55293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20073 | /* 55299 */ GIR_RootConstrainSelectedInstOperands, |
| 20074 | /* 55300 */ // GIR_Coverage, 1169, |
| 20075 | /* 55300 */ GIR_EraseRootFromParent_Done, |
| 20076 | /* 55301 */ // Label 1647: @55301 |
| 20077 | /* 55301 */ GIM_Reject, |
| 20078 | /* 55302 */ // Label 1641: @55302 |
| 20079 | /* 55302 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1648*/ GIMT_Encode4(55347), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1164 // |
| 20080 | /* 55309 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20081 | /* 55312 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20082 | /* 55315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20083 | /* 55319 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20084 | /* 55323 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20085 | /* 55327 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4062:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20086 | /* 55327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i16), |
| 20087 | /* 55330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20088 | /* 55332 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20089 | /* 55334 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20090 | /* 55336 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20091 | /* 55339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20092 | /* 55345 */ GIR_RootConstrainSelectedInstOperands, |
| 20093 | /* 55346 */ // GIR_Coverage, 1164, |
| 20094 | /* 55346 */ GIR_EraseRootFromParent_Done, |
| 20095 | /* 55347 */ // Label 1648: @55347 |
| 20096 | /* 55347 */ GIM_Reject, |
| 20097 | /* 55348 */ // Label 1642: @55348 |
| 20098 | /* 55348 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1649*/ GIMT_Encode4(55393), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1166 // |
| 20099 | /* 55355 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20100 | /* 55358 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20101 | /* 55361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20102 | /* 55365 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20103 | /* 55369 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20104 | /* 55373 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4062:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 20105 | /* 55373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i16), |
| 20106 | /* 55376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20107 | /* 55378 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20108 | /* 55380 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20109 | /* 55382 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20110 | /* 55385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20111 | /* 55391 */ GIR_RootConstrainSelectedInstOperands, |
| 20112 | /* 55392 */ // GIR_Coverage, 1166, |
| 20113 | /* 55392 */ GIR_EraseRootFromParent_Done, |
| 20114 | /* 55393 */ // Label 1649: @55393 |
| 20115 | /* 55393 */ GIM_Reject, |
| 20116 | /* 55394 */ // Label 1643: @55394 |
| 20117 | /* 55394 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1650*/ GIMT_Encode4(55439), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1165 // |
| 20118 | /* 55401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20119 | /* 55404 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20120 | /* 55407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20121 | /* 55411 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20122 | /* 55415 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20123 | /* 55419 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4062:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20124 | /* 55419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv2i32), |
| 20125 | /* 55422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20126 | /* 55424 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20127 | /* 55426 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20128 | /* 55428 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20129 | /* 55431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20130 | /* 55437 */ GIR_RootConstrainSelectedInstOperands, |
| 20131 | /* 55438 */ // GIR_Coverage, 1165, |
| 20132 | /* 55438 */ GIR_EraseRootFromParent_Done, |
| 20133 | /* 55439 */ // Label 1650: @55439 |
| 20134 | /* 55439 */ GIM_Reject, |
| 20135 | /* 55440 */ // Label 1644: @55440 |
| 20136 | /* 55440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1651*/ GIMT_Encode4(55485), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1167 // |
| 20137 | /* 55447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20138 | /* 55450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20139 | /* 55453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20140 | /* 55457 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20141 | /* 55461 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20142 | /* 55465 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4062:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 20143 | /* 55465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i32), |
| 20144 | /* 55468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20145 | /* 55470 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20146 | /* 55472 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20147 | /* 55474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20148 | /* 55477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20149 | /* 55483 */ GIR_RootConstrainSelectedInstOperands, |
| 20150 | /* 55484 */ // GIR_Coverage, 1167, |
| 20151 | /* 55484 */ GIR_EraseRootFromParent_Done, |
| 20152 | /* 55485 */ // Label 1651: @55485 |
| 20153 | /* 55485 */ GIM_Reject, |
| 20154 | /* 55486 */ // Label 1645: @55486 |
| 20155 | /* 55486 */ GIM_Reject, |
| 20156 | /* 55487 */ // Label 1638: @55487 |
| 20157 | /* 55487 */ GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(55667), |
| 20158 | /* 55492 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn), |
| 20159 | /* 55497 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1656*/ GIMT_Encode4(55666), |
| 20160 | /* 55508 */ /*GILLT_v8s8*//*Label 1653*/ GIMT_Encode4(55528), GIMT_Encode4(0), |
| 20161 | /* 55516 */ /*GILLT_v4s16*//*Label 1654*/ GIMT_Encode4(55574), GIMT_Encode4(0), |
| 20162 | /* 55524 */ /*GILLT_v2s32*//*Label 1655*/ GIMT_Encode4(55620), |
| 20163 | /* 55528 */ // Label 1653: @55528 |
| 20164 | /* 55528 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1657*/ GIMT_Encode4(55573), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1186 // |
| 20165 | /* 55535 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20166 | /* 55538 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20167 | /* 55541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20168 | /* 55545 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20169 | /* 55549 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20170 | /* 55553 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4126:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRSUBHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 20171 | /* 55553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv8i8), |
| 20172 | /* 55556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20173 | /* 55558 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20174 | /* 55560 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20175 | /* 55562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20176 | /* 55565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20177 | /* 55571 */ GIR_RootConstrainSelectedInstOperands, |
| 20178 | /* 55572 */ // GIR_Coverage, 1186, |
| 20179 | /* 55572 */ GIR_EraseRootFromParent_Done, |
| 20180 | /* 55573 */ // Label 1657: @55573 |
| 20181 | /* 55573 */ GIM_Reject, |
| 20182 | /* 55574 */ // Label 1654: @55574 |
| 20183 | /* 55574 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1658*/ GIMT_Encode4(55619), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1187 // |
| 20184 | /* 55581 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20185 | /* 55584 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20186 | /* 55587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20187 | /* 55591 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20188 | /* 55595 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20189 | /* 55599 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4126:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRSUBHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 20190 | /* 55599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv4i16), |
| 20191 | /* 55602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20192 | /* 55604 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20193 | /* 55606 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20194 | /* 55608 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20195 | /* 55611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20196 | /* 55617 */ GIR_RootConstrainSelectedInstOperands, |
| 20197 | /* 55618 */ // GIR_Coverage, 1187, |
| 20198 | /* 55618 */ GIR_EraseRootFromParent_Done, |
| 20199 | /* 55619 */ // Label 1658: @55619 |
| 20200 | /* 55619 */ GIM_Reject, |
| 20201 | /* 55620 */ // Label 1655: @55620 |
| 20202 | /* 55620 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1659*/ GIMT_Encode4(55665), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1188 // |
| 20203 | /* 55627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20204 | /* 55630 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 20205 | /* 55633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20206 | /* 55637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20207 | /* 55641 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20208 | /* 55645 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4126:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRSUBHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 20209 | /* 55645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv2i32), |
| 20210 | /* 55648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20211 | /* 55650 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20212 | /* 55652 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20213 | /* 55654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20214 | /* 55657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20215 | /* 55663 */ GIR_RootConstrainSelectedInstOperands, |
| 20216 | /* 55664 */ // GIR_Coverage, 1188, |
| 20217 | /* 55664 */ GIR_EraseRootFromParent_Done, |
| 20218 | /* 55665 */ // Label 1659: @55665 |
| 20219 | /* 55665 */ GIM_Reject, |
| 20220 | /* 55666 */ // Label 1656: @55666 |
| 20221 | /* 55666 */ GIM_Reject, |
| 20222 | /* 55667 */ // Label 1652: @55667 |
| 20223 | /* 55667 */ GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(55889), |
| 20224 | /* 55672 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge), |
| 20225 | /* 55677 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1665*/ GIMT_Encode4(55888), |
| 20226 | /* 55688 */ /*GILLT_v4s16*//*Label 1661*/ GIMT_Encode4(55704), |
| 20227 | /* 55692 */ /*GILLT_v8s16*//*Label 1662*/ GIMT_Encode4(55750), |
| 20228 | /* 55696 */ /*GILLT_v2s32*//*Label 1663*/ GIMT_Encode4(55796), |
| 20229 | /* 55700 */ /*GILLT_v4s32*//*Label 1664*/ GIMT_Encode4(55842), |
| 20230 | /* 55704 */ // Label 1661: @55704 |
| 20231 | /* 55704 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1666*/ GIMT_Encode4(55749), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1283 // |
| 20232 | /* 55711 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20233 | /* 55714 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20234 | /* 55717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20235 | /* 55721 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20236 | /* 55725 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20237 | /* 55729 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4037:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGEhd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 20238 | /* 55729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhd), |
| 20239 | /* 55732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20240 | /* 55734 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20241 | /* 55736 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20242 | /* 55738 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20243 | /* 55741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20244 | /* 55747 */ GIR_RootConstrainSelectedInstOperands, |
| 20245 | /* 55748 */ // GIR_Coverage, 1283, |
| 20246 | /* 55748 */ GIR_EraseRootFromParent_Done, |
| 20247 | /* 55749 */ // Label 1666: @55749 |
| 20248 | /* 55749 */ GIM_Reject, |
| 20249 | /* 55750 */ // Label 1662: @55750 |
| 20250 | /* 55750 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1667*/ GIMT_Encode4(55795), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1284 // |
| 20251 | /* 55757 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20252 | /* 55760 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20253 | /* 55763 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20254 | /* 55767 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20255 | /* 55771 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20256 | /* 55775 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4037:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGEhq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 20257 | /* 55775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhq), |
| 20258 | /* 55778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20259 | /* 55780 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20260 | /* 55782 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20261 | /* 55784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20262 | /* 55787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20263 | /* 55793 */ GIR_RootConstrainSelectedInstOperands, |
| 20264 | /* 55794 */ // GIR_Coverage, 1284, |
| 20265 | /* 55794 */ GIR_EraseRootFromParent_Done, |
| 20266 | /* 55795 */ // Label 1667: @55795 |
| 20267 | /* 55795 */ GIM_Reject, |
| 20268 | /* 55796 */ // Label 1663: @55796 |
| 20269 | /* 55796 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1668*/ GIMT_Encode4(55841), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1281 // |
| 20270 | /* 55803 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20271 | /* 55806 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20272 | /* 55809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20273 | /* 55813 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20274 | /* 55817 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20275 | /* 55821 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4037:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGEfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 20276 | /* 55821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfd), |
| 20277 | /* 55824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20278 | /* 55826 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20279 | /* 55828 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20280 | /* 55830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20281 | /* 55833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20282 | /* 55839 */ GIR_RootConstrainSelectedInstOperands, |
| 20283 | /* 55840 */ // GIR_Coverage, 1281, |
| 20284 | /* 55840 */ GIR_EraseRootFromParent_Done, |
| 20285 | /* 55841 */ // Label 1668: @55841 |
| 20286 | /* 55841 */ GIM_Reject, |
| 20287 | /* 55842 */ // Label 1664: @55842 |
| 20288 | /* 55842 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1669*/ GIMT_Encode4(55887), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1282 // |
| 20289 | /* 55849 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20290 | /* 55852 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20291 | /* 55855 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20292 | /* 55859 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20293 | /* 55863 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20294 | /* 55867 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4037:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGEfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 20295 | /* 55867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfq), |
| 20296 | /* 55870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20297 | /* 55872 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20298 | /* 55874 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20299 | /* 55876 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20300 | /* 55879 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20301 | /* 55885 */ GIR_RootConstrainSelectedInstOperands, |
| 20302 | /* 55886 */ // GIR_Coverage, 1282, |
| 20303 | /* 55886 */ GIR_EraseRootFromParent_Done, |
| 20304 | /* 55887 */ // Label 1669: @55887 |
| 20305 | /* 55887 */ GIM_Reject, |
| 20306 | /* 55888 */ // Label 1665: @55888 |
| 20307 | /* 55888 */ GIM_Reject, |
| 20308 | /* 55889 */ // Label 1660: @55889 |
| 20309 | /* 55889 */ GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(56111), |
| 20310 | /* 55894 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt), |
| 20311 | /* 55899 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1675*/ GIMT_Encode4(56110), |
| 20312 | /* 55910 */ /*GILLT_v4s16*//*Label 1671*/ GIMT_Encode4(55926), |
| 20313 | /* 55914 */ /*GILLT_v8s16*//*Label 1672*/ GIMT_Encode4(55972), |
| 20314 | /* 55918 */ /*GILLT_v2s32*//*Label 1673*/ GIMT_Encode4(56018), |
| 20315 | /* 55922 */ /*GILLT_v4s32*//*Label 1674*/ GIMT_Encode4(56064), |
| 20316 | /* 55926 */ // Label 1671: @55926 |
| 20317 | /* 55926 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1676*/ GIMT_Encode4(55971), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1287 // |
| 20318 | /* 55933 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20319 | /* 55936 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20320 | /* 55939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20321 | /* 55943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20322 | /* 55947 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20323 | /* 55951 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4038:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGThd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 20324 | /* 55951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThd), |
| 20325 | /* 55954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20326 | /* 55956 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20327 | /* 55958 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20328 | /* 55960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20329 | /* 55963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20330 | /* 55969 */ GIR_RootConstrainSelectedInstOperands, |
| 20331 | /* 55970 */ // GIR_Coverage, 1287, |
| 20332 | /* 55970 */ GIR_EraseRootFromParent_Done, |
| 20333 | /* 55971 */ // Label 1676: @55971 |
| 20334 | /* 55971 */ GIM_Reject, |
| 20335 | /* 55972 */ // Label 1672: @55972 |
| 20336 | /* 55972 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1677*/ GIMT_Encode4(56017), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1288 // |
| 20337 | /* 55979 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20338 | /* 55982 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20339 | /* 55985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20340 | /* 55989 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20341 | /* 55993 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20342 | /* 55997 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4038:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGThq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 20343 | /* 55997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThq), |
| 20344 | /* 56000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20345 | /* 56002 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20346 | /* 56004 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20347 | /* 56006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20348 | /* 56009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20349 | /* 56015 */ GIR_RootConstrainSelectedInstOperands, |
| 20350 | /* 56016 */ // GIR_Coverage, 1288, |
| 20351 | /* 56016 */ GIR_EraseRootFromParent_Done, |
| 20352 | /* 56017 */ // Label 1677: @56017 |
| 20353 | /* 56017 */ GIM_Reject, |
| 20354 | /* 56018 */ // Label 1673: @56018 |
| 20355 | /* 56018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1678*/ GIMT_Encode4(56063), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1285 // |
| 20356 | /* 56025 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20357 | /* 56028 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20358 | /* 56031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20359 | /* 56035 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20360 | /* 56039 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20361 | /* 56043 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4038:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGTfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 20362 | /* 56043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfd), |
| 20363 | /* 56046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20364 | /* 56048 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20365 | /* 56050 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20366 | /* 56052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20367 | /* 56055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20368 | /* 56061 */ GIR_RootConstrainSelectedInstOperands, |
| 20369 | /* 56062 */ // GIR_Coverage, 1285, |
| 20370 | /* 56062 */ GIR_EraseRootFromParent_Done, |
| 20371 | /* 56063 */ // Label 1678: @56063 |
| 20372 | /* 56063 */ GIM_Reject, |
| 20373 | /* 56064 */ // Label 1674: @56064 |
| 20374 | /* 56064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1679*/ GIMT_Encode4(56109), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1286 // |
| 20375 | /* 56071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20376 | /* 56074 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20377 | /* 56077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20378 | /* 56081 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20379 | /* 56085 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20380 | /* 56089 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4038:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGTfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 20381 | /* 56089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfq), |
| 20382 | /* 56092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20383 | /* 56094 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20384 | /* 56096 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20385 | /* 56098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20386 | /* 56101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20387 | /* 56107 */ GIR_RootConstrainSelectedInstOperands, |
| 20388 | /* 56108 */ // GIR_Coverage, 1286, |
| 20389 | /* 56108 */ GIR_EraseRootFromParent_Done, |
| 20390 | /* 56109 */ // Label 1679: @56109 |
| 20391 | /* 56109 */ GIM_Reject, |
| 20392 | /* 56110 */ // Label 1675: @56110 |
| 20393 | /* 56110 */ GIM_Reject, |
| 20394 | /* 56111 */ // Label 1670: @56111 |
| 20395 | /* 56111 */ GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(56333), |
| 20396 | /* 56116 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds), |
| 20397 | /* 56121 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1685*/ GIMT_Encode4(56332), |
| 20398 | /* 56132 */ /*GILLT_v4s16*//*Label 1681*/ GIMT_Encode4(56148), |
| 20399 | /* 56136 */ /*GILLT_v8s16*//*Label 1682*/ GIMT_Encode4(56194), |
| 20400 | /* 56140 */ /*GILLT_v2s32*//*Label 1683*/ GIMT_Encode4(56240), |
| 20401 | /* 56144 */ /*GILLT_v4s32*//*Label 1684*/ GIMT_Encode4(56286), |
| 20402 | /* 56148 */ // Label 1681: @56148 |
| 20403 | /* 56148 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1686*/ GIMT_Encode4(56193), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1333 // |
| 20404 | /* 56155 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20405 | /* 56158 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20406 | /* 56161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20407 | /* 56165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20408 | /* 56169 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20409 | /* 56173 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4034:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VABDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 20410 | /* 56173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhd), |
| 20411 | /* 56176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20412 | /* 56178 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20413 | /* 56180 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20414 | /* 56182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20415 | /* 56185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20416 | /* 56191 */ GIR_RootConstrainSelectedInstOperands, |
| 20417 | /* 56192 */ // GIR_Coverage, 1333, |
| 20418 | /* 56192 */ GIR_EraseRootFromParent_Done, |
| 20419 | /* 56193 */ // Label 1686: @56193 |
| 20420 | /* 56193 */ GIM_Reject, |
| 20421 | /* 56194 */ // Label 1682: @56194 |
| 20422 | /* 56194 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1687*/ GIMT_Encode4(56239), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1334 // |
| 20423 | /* 56201 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20424 | /* 56204 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20425 | /* 56207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20426 | /* 56211 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20427 | /* 56215 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20428 | /* 56219 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4034:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VABDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 20429 | /* 56219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhq), |
| 20430 | /* 56222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20431 | /* 56224 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20432 | /* 56226 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20433 | /* 56228 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20434 | /* 56231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20435 | /* 56237 */ GIR_RootConstrainSelectedInstOperands, |
| 20436 | /* 56238 */ // GIR_Coverage, 1334, |
| 20437 | /* 56238 */ GIR_EraseRootFromParent_Done, |
| 20438 | /* 56239 */ // Label 1687: @56239 |
| 20439 | /* 56239 */ GIM_Reject, |
| 20440 | /* 56240 */ // Label 1683: @56240 |
| 20441 | /* 56240 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1688*/ GIMT_Encode4(56285), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1331 // |
| 20442 | /* 56247 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20443 | /* 56250 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20444 | /* 56253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20445 | /* 56257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20446 | /* 56261 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20447 | /* 56265 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4034:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VABDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 20448 | /* 56265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfd), |
| 20449 | /* 56268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20450 | /* 56270 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20451 | /* 56272 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20452 | /* 56274 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20453 | /* 56277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20454 | /* 56283 */ GIR_RootConstrainSelectedInstOperands, |
| 20455 | /* 56284 */ // GIR_Coverage, 1331, |
| 20456 | /* 56284 */ GIR_EraseRootFromParent_Done, |
| 20457 | /* 56285 */ // Label 1688: @56285 |
| 20458 | /* 56285 */ GIM_Reject, |
| 20459 | /* 56286 */ // Label 1684: @56286 |
| 20460 | /* 56286 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1689*/ GIMT_Encode4(56331), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1332 // |
| 20461 | /* 56293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20462 | /* 56296 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20463 | /* 56299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20464 | /* 56303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20465 | /* 56307 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20466 | /* 56311 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4034:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VABDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 20467 | /* 56311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfq), |
| 20468 | /* 56314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20469 | /* 56316 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20470 | /* 56318 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20471 | /* 56320 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20472 | /* 56323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20473 | /* 56329 */ GIR_RootConstrainSelectedInstOperands, |
| 20474 | /* 56330 */ // GIR_Coverage, 1332, |
| 20475 | /* 56330 */ GIR_EraseRootFromParent_Done, |
| 20476 | /* 56331 */ // Label 1689: @56331 |
| 20477 | /* 56331 */ GIM_Reject, |
| 20478 | /* 56332 */ // Label 1685: @56332 |
| 20479 | /* 56332 */ GIM_Reject, |
| 20480 | /* 56333 */ // Label 1680: @56333 |
| 20481 | /* 56333 */ GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(56579), |
| 20482 | /* 56338 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd), |
| 20483 | /* 56343 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1694*/ GIMT_Encode4(56578), |
| 20484 | /* 56354 */ /*GILLT_v8s8*//*Label 1691*/ GIMT_Encode4(56374), GIMT_Encode4(0), |
| 20485 | /* 56362 */ /*GILLT_v4s16*//*Label 1692*/ GIMT_Encode4(56420), GIMT_Encode4(0), |
| 20486 | /* 56370 */ /*GILLT_v2s32*//*Label 1693*/ GIMT_Encode4(56499), |
| 20487 | /* 56374 */ // Label 1691: @56374 |
| 20488 | /* 56374 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1695*/ GIMT_Encode4(56419), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1399 // |
| 20489 | /* 56381 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20490 | /* 56384 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20491 | /* 56387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20492 | /* 56391 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20493 | /* 56395 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20494 | /* 56399 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4088:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPADDi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 20495 | /* 56399 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi8), |
| 20496 | /* 56402 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20497 | /* 56404 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20498 | /* 56406 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20499 | /* 56408 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20500 | /* 56411 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20501 | /* 56417 */ GIR_RootConstrainSelectedInstOperands, |
| 20502 | /* 56418 */ // GIR_Coverage, 1399, |
| 20503 | /* 56418 */ GIR_EraseRootFromParent_Done, |
| 20504 | /* 56419 */ // Label 1695: @56419 |
| 20505 | /* 56419 */ GIM_Reject, |
| 20506 | /* 56420 */ // Label 1692: @56420 |
| 20507 | /* 56420 */ GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(56498), |
| 20508 | /* 56425 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20509 | /* 56428 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20510 | /* 56431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20511 | /* 56435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20512 | /* 56439 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20513 | /* 56443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1697*/ GIMT_Encode4(56470), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1400 // |
| 20514 | /* 56450 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4088:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPADDi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20515 | /* 56450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi16), |
| 20516 | /* 56453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20517 | /* 56455 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20518 | /* 56457 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20519 | /* 56459 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20520 | /* 56462 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20521 | /* 56468 */ GIR_RootConstrainSelectedInstOperands, |
| 20522 | /* 56469 */ // GIR_Coverage, 1400, |
| 20523 | /* 56469 */ GIR_EraseRootFromParent_Done, |
| 20524 | /* 56470 */ // Label 1697: @56470 |
| 20525 | /* 56470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1698*/ GIMT_Encode4(56497), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1403 // |
| 20526 | /* 56477 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4088:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPADDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 20527 | /* 56477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDh), |
| 20528 | /* 56480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20529 | /* 56482 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20530 | /* 56484 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20531 | /* 56486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20532 | /* 56489 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20533 | /* 56495 */ GIR_RootConstrainSelectedInstOperands, |
| 20534 | /* 56496 */ // GIR_Coverage, 1403, |
| 20535 | /* 56496 */ GIR_EraseRootFromParent_Done, |
| 20536 | /* 56497 */ // Label 1698: @56497 |
| 20537 | /* 56497 */ GIM_Reject, |
| 20538 | /* 56498 */ // Label 1696: @56498 |
| 20539 | /* 56498 */ GIM_Reject, |
| 20540 | /* 56499 */ // Label 1693: @56499 |
| 20541 | /* 56499 */ GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(56577), |
| 20542 | /* 56504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20543 | /* 56507 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20544 | /* 56510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20545 | /* 56514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20546 | /* 56518 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20547 | /* 56522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1700*/ GIMT_Encode4(56549), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1401 // |
| 20548 | /* 56529 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4088:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPADDi32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20549 | /* 56529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi32), |
| 20550 | /* 56532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20551 | /* 56534 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20552 | /* 56536 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20553 | /* 56538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20554 | /* 56541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20555 | /* 56547 */ GIR_RootConstrainSelectedInstOperands, |
| 20556 | /* 56548 */ // GIR_Coverage, 1401, |
| 20557 | /* 56548 */ GIR_EraseRootFromParent_Done, |
| 20558 | /* 56549 */ // Label 1700: @56549 |
| 20559 | /* 56549 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1701*/ GIMT_Encode4(56576), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1402 // |
| 20560 | /* 56556 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4088:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPADDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 20561 | /* 56556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDf), |
| 20562 | /* 56559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20563 | /* 56561 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20564 | /* 56563 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20565 | /* 56565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20566 | /* 56568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20567 | /* 56574 */ GIR_RootConstrainSelectedInstOperands, |
| 20568 | /* 56575 */ // GIR_Coverage, 1402, |
| 20569 | /* 56575 */ GIR_EraseRootFromParent_Done, |
| 20570 | /* 56576 */ // Label 1701: @56576 |
| 20571 | /* 56576 */ GIM_Reject, |
| 20572 | /* 56577 */ // Label 1699: @56577 |
| 20573 | /* 56577 */ GIM_Reject, |
| 20574 | /* 56578 */ // Label 1694: @56578 |
| 20575 | /* 56578 */ GIM_Reject, |
| 20576 | /* 56579 */ // Label 1690: @56579 |
| 20577 | /* 56579 */ GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(56925), |
| 20578 | /* 56584 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals), |
| 20579 | /* 56589 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1709*/ GIMT_Encode4(56924), |
| 20580 | /* 56600 */ /*GILLT_s64*//*Label 1703*/ GIMT_Encode4(56648), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 20581 | /* 56628 */ /*GILLT_v4s16*//*Label 1704*/ GIMT_Encode4(56694), |
| 20582 | /* 56632 */ /*GILLT_v8s16*//*Label 1705*/ GIMT_Encode4(56740), |
| 20583 | /* 56636 */ /*GILLT_v2s32*//*Label 1706*/ GIMT_Encode4(56786), |
| 20584 | /* 56640 */ /*GILLT_v4s32*//*Label 1707*/ GIMT_Encode4(56832), |
| 20585 | /* 56644 */ /*GILLT_v2s64*//*Label 1708*/ GIMT_Encode4(56878), |
| 20586 | /* 56648 */ // Label 1703: @56648 |
| 20587 | /* 56648 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1710*/ GIMT_Encode4(56693), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1418 // |
| 20588 | /* 56655 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20589 | /* 56658 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20590 | /* 56661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20591 | /* 56665 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20592 | /* 56669 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20593 | /* 56673 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4086:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALsv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) |
| 20594 | /* 56673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv2i32), |
| 20595 | /* 56676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20596 | /* 56678 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20597 | /* 56680 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20598 | /* 56682 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20599 | /* 56685 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20600 | /* 56691 */ GIR_RootConstrainSelectedInstOperands, |
| 20601 | /* 56692 */ // GIR_Coverage, 1418, |
| 20602 | /* 56692 */ GIR_EraseRootFromParent_Done, |
| 20603 | /* 56693 */ // Label 1710: @56693 |
| 20604 | /* 56693 */ GIM_Reject, |
| 20605 | /* 56694 */ // Label 1704: @56694 |
| 20606 | /* 56694 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1711*/ GIMT_Encode4(56739), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1416 // |
| 20607 | /* 56701 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20608 | /* 56704 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20609 | /* 56707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20610 | /* 56711 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20611 | /* 56715 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20612 | /* 56719 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4086:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALsv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) |
| 20613 | /* 56719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i8), |
| 20614 | /* 56722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20615 | /* 56724 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20616 | /* 56726 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20617 | /* 56728 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20618 | /* 56731 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20619 | /* 56737 */ GIR_RootConstrainSelectedInstOperands, |
| 20620 | /* 56738 */ // GIR_Coverage, 1416, |
| 20621 | /* 56738 */ GIR_EraseRootFromParent_Done, |
| 20622 | /* 56739 */ // Label 1711: @56739 |
| 20623 | /* 56739 */ GIM_Reject, |
| 20624 | /* 56740 */ // Label 1705: @56740 |
| 20625 | /* 56740 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1712*/ GIMT_Encode4(56785), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1419 // |
| 20626 | /* 56747 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20627 | /* 56750 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20628 | /* 56753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20629 | /* 56757 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20630 | /* 56761 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20631 | /* 56765 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4086:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALsv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) |
| 20632 | /* 56765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv16i8), |
| 20633 | /* 56768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20634 | /* 56770 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20635 | /* 56772 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20636 | /* 56774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20637 | /* 56777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20638 | /* 56783 */ GIR_RootConstrainSelectedInstOperands, |
| 20639 | /* 56784 */ // GIR_Coverage, 1419, |
| 20640 | /* 56784 */ GIR_EraseRootFromParent_Done, |
| 20641 | /* 56785 */ // Label 1712: @56785 |
| 20642 | /* 56785 */ GIM_Reject, |
| 20643 | /* 56786 */ // Label 1706: @56786 |
| 20644 | /* 56786 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1713*/ GIMT_Encode4(56831), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1417 // |
| 20645 | /* 56793 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20646 | /* 56796 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20647 | /* 56799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20648 | /* 56803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20649 | /* 56807 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20650 | /* 56811 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4086:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALsv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) |
| 20651 | /* 56811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i16), |
| 20652 | /* 56814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20653 | /* 56816 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20654 | /* 56818 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20655 | /* 56820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20656 | /* 56823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20657 | /* 56829 */ GIR_RootConstrainSelectedInstOperands, |
| 20658 | /* 56830 */ // GIR_Coverage, 1417, |
| 20659 | /* 56830 */ GIR_EraseRootFromParent_Done, |
| 20660 | /* 56831 */ // Label 1713: @56831 |
| 20661 | /* 56831 */ GIM_Reject, |
| 20662 | /* 56832 */ // Label 1707: @56832 |
| 20663 | /* 56832 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1714*/ GIMT_Encode4(56877), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1420 // |
| 20664 | /* 56839 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20665 | /* 56842 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20666 | /* 56845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20667 | /* 56849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20668 | /* 56853 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20669 | /* 56857 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4086:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALsv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) |
| 20670 | /* 56857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i16), |
| 20671 | /* 56860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20672 | /* 56862 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20673 | /* 56864 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20674 | /* 56866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20675 | /* 56869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20676 | /* 56875 */ GIR_RootConstrainSelectedInstOperands, |
| 20677 | /* 56876 */ // GIR_Coverage, 1420, |
| 20678 | /* 56876 */ GIR_EraseRootFromParent_Done, |
| 20679 | /* 56877 */ // Label 1714: @56877 |
| 20680 | /* 56877 */ GIM_Reject, |
| 20681 | /* 56878 */ // Label 1708: @56878 |
| 20682 | /* 56878 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1715*/ GIMT_Encode4(56923), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1421 // |
| 20683 | /* 56885 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20684 | /* 56888 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20685 | /* 56891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20686 | /* 56895 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20687 | /* 56899 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20688 | /* 56903 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4086:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALsv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) |
| 20689 | /* 56903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i32), |
| 20690 | /* 56906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20691 | /* 56908 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20692 | /* 56910 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20693 | /* 56912 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20694 | /* 56915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20695 | /* 56921 */ GIR_RootConstrainSelectedInstOperands, |
| 20696 | /* 56922 */ // GIR_Coverage, 1421, |
| 20697 | /* 56922 */ GIR_EraseRootFromParent_Done, |
| 20698 | /* 56923 */ // Label 1715: @56923 |
| 20699 | /* 56923 */ GIM_Reject, |
| 20700 | /* 56924 */ // Label 1709: @56924 |
| 20701 | /* 56924 */ GIM_Reject, |
| 20702 | /* 56925 */ // Label 1702: @56925 |
| 20703 | /* 56925 */ GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(57271), |
| 20704 | /* 56930 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu), |
| 20705 | /* 56935 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1723*/ GIMT_Encode4(57270), |
| 20706 | /* 56946 */ /*GILLT_s64*//*Label 1717*/ GIMT_Encode4(56994), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 20707 | /* 56974 */ /*GILLT_v4s16*//*Label 1718*/ GIMT_Encode4(57040), |
| 20708 | /* 56978 */ /*GILLT_v8s16*//*Label 1719*/ GIMT_Encode4(57086), |
| 20709 | /* 56982 */ /*GILLT_v2s32*//*Label 1720*/ GIMT_Encode4(57132), |
| 20710 | /* 56986 */ /*GILLT_v4s32*//*Label 1721*/ GIMT_Encode4(57178), |
| 20711 | /* 56990 */ /*GILLT_v2s64*//*Label 1722*/ GIMT_Encode4(57224), |
| 20712 | /* 56994 */ // Label 1717: @56994 |
| 20713 | /* 56994 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1724*/ GIMT_Encode4(57039), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1424 // |
| 20714 | /* 57001 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 20715 | /* 57004 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20716 | /* 57007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20717 | /* 57011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20718 | /* 57015 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20719 | /* 57019 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4087:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALuv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) |
| 20720 | /* 57019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv2i32), |
| 20721 | /* 57022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20722 | /* 57024 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20723 | /* 57026 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20724 | /* 57028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20725 | /* 57031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20726 | /* 57037 */ GIR_RootConstrainSelectedInstOperands, |
| 20727 | /* 57038 */ // GIR_Coverage, 1424, |
| 20728 | /* 57038 */ GIR_EraseRootFromParent_Done, |
| 20729 | /* 57039 */ // Label 1724: @57039 |
| 20730 | /* 57039 */ GIM_Reject, |
| 20731 | /* 57040 */ // Label 1718: @57040 |
| 20732 | /* 57040 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1725*/ GIMT_Encode4(57085), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1422 // |
| 20733 | /* 57047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20734 | /* 57050 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20735 | /* 57053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20736 | /* 57057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20737 | /* 57061 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20738 | /* 57065 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4087:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALuv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) |
| 20739 | /* 57065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i8), |
| 20740 | /* 57068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20741 | /* 57070 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20742 | /* 57072 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20743 | /* 57074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20744 | /* 57077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20745 | /* 57083 */ GIR_RootConstrainSelectedInstOperands, |
| 20746 | /* 57084 */ // GIR_Coverage, 1422, |
| 20747 | /* 57084 */ GIR_EraseRootFromParent_Done, |
| 20748 | /* 57085 */ // Label 1725: @57085 |
| 20749 | /* 57085 */ GIM_Reject, |
| 20750 | /* 57086 */ // Label 1719: @57086 |
| 20751 | /* 57086 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1726*/ GIMT_Encode4(57131), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1425 // |
| 20752 | /* 57093 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 20753 | /* 57096 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 20754 | /* 57099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20755 | /* 57103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20756 | /* 57107 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20757 | /* 57111 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4087:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALuv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) |
| 20758 | /* 57111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv16i8), |
| 20759 | /* 57114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20760 | /* 57116 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20761 | /* 57118 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20762 | /* 57120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20763 | /* 57123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20764 | /* 57129 */ GIR_RootConstrainSelectedInstOperands, |
| 20765 | /* 57130 */ // GIR_Coverage, 1425, |
| 20766 | /* 57130 */ GIR_EraseRootFromParent_Done, |
| 20767 | /* 57131 */ // Label 1726: @57131 |
| 20768 | /* 57131 */ GIM_Reject, |
| 20769 | /* 57132 */ // Label 1720: @57132 |
| 20770 | /* 57132 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1727*/ GIMT_Encode4(57177), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1423 // |
| 20771 | /* 57139 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20772 | /* 57142 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20773 | /* 57145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20774 | /* 57149 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20775 | /* 57153 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20776 | /* 57157 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4087:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALuv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) |
| 20777 | /* 57157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i16), |
| 20778 | /* 57160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20779 | /* 57162 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20780 | /* 57164 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20781 | /* 57166 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20782 | /* 57169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20783 | /* 57175 */ GIR_RootConstrainSelectedInstOperands, |
| 20784 | /* 57176 */ // GIR_Coverage, 1423, |
| 20785 | /* 57176 */ GIR_EraseRootFromParent_Done, |
| 20786 | /* 57177 */ // Label 1727: @57177 |
| 20787 | /* 57177 */ GIM_Reject, |
| 20788 | /* 57178 */ // Label 1721: @57178 |
| 20789 | /* 57178 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1728*/ GIMT_Encode4(57223), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1426 // |
| 20790 | /* 57185 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 20791 | /* 57188 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 20792 | /* 57191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20793 | /* 57195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20794 | /* 57199 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20795 | /* 57203 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4087:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALuv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) |
| 20796 | /* 57203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i16), |
| 20797 | /* 57206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20798 | /* 57208 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20799 | /* 57210 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20800 | /* 57212 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20801 | /* 57215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20802 | /* 57221 */ GIR_RootConstrainSelectedInstOperands, |
| 20803 | /* 57222 */ // GIR_Coverage, 1426, |
| 20804 | /* 57222 */ GIR_EraseRootFromParent_Done, |
| 20805 | /* 57223 */ // Label 1728: @57223 |
| 20806 | /* 57223 */ GIM_Reject, |
| 20807 | /* 57224 */ // Label 1722: @57224 |
| 20808 | /* 57224 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1729*/ GIMT_Encode4(57269), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1427 // |
| 20809 | /* 57231 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 20810 | /* 57234 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 20811 | /* 57237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20812 | /* 57241 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20813 | /* 57245 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 20814 | /* 57249 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4087:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALuv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) |
| 20815 | /* 57249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i32), |
| 20816 | /* 57252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20817 | /* 57254 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 20818 | /* 57256 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20819 | /* 57258 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20820 | /* 57261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20821 | /* 57267 */ GIR_RootConstrainSelectedInstOperands, |
| 20822 | /* 57268 */ // GIR_Coverage, 1427, |
| 20823 | /* 57268 */ GIR_EraseRootFromParent_Done, |
| 20824 | /* 57269 */ // Label 1729: @57269 |
| 20825 | /* 57269 */ GIM_Reject, |
| 20826 | /* 57270 */ // Label 1723: @57270 |
| 20827 | /* 57270 */ GIM_Reject, |
| 20828 | /* 57271 */ // Label 1716: @57271 |
| 20829 | /* 57271 */ GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(57451), |
| 20830 | /* 57276 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 20831 | /* 57281 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1734*/ GIMT_Encode4(57450), |
| 20832 | /* 57292 */ /*GILLT_v8s8*//*Label 1731*/ GIMT_Encode4(57312), GIMT_Encode4(0), |
| 20833 | /* 57300 */ /*GILLT_v4s16*//*Label 1732*/ GIMT_Encode4(57358), GIMT_Encode4(0), |
| 20834 | /* 57308 */ /*GILLT_v2s32*//*Label 1733*/ GIMT_Encode4(57404), |
| 20835 | /* 57312 */ // Label 1731: @57312 |
| 20836 | /* 57312 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1735*/ GIMT_Encode4(57357), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1428 // |
| 20837 | /* 57319 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20838 | /* 57322 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20839 | /* 57325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20840 | /* 57329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20841 | /* 57333 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20842 | /* 57337 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4091:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 20843 | /* 57337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs8), |
| 20844 | /* 57340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20845 | /* 57342 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20846 | /* 57344 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20847 | /* 57346 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20848 | /* 57349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20849 | /* 57355 */ GIR_RootConstrainSelectedInstOperands, |
| 20850 | /* 57356 */ // GIR_Coverage, 1428, |
| 20851 | /* 57356 */ GIR_EraseRootFromParent_Done, |
| 20852 | /* 57357 */ // Label 1735: @57357 |
| 20853 | /* 57357 */ GIM_Reject, |
| 20854 | /* 57358 */ // Label 1732: @57358 |
| 20855 | /* 57358 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1736*/ GIMT_Encode4(57403), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1429 // |
| 20856 | /* 57365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20857 | /* 57368 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20858 | /* 57371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20859 | /* 57375 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20860 | /* 57379 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20861 | /* 57383 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4091:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20862 | /* 57383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs16), |
| 20863 | /* 57386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20864 | /* 57388 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20865 | /* 57390 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20866 | /* 57392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20867 | /* 57395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20868 | /* 57401 */ GIR_RootConstrainSelectedInstOperands, |
| 20869 | /* 57402 */ // GIR_Coverage, 1429, |
| 20870 | /* 57402 */ GIR_EraseRootFromParent_Done, |
| 20871 | /* 57403 */ // Label 1736: @57403 |
| 20872 | /* 57403 */ GIM_Reject, |
| 20873 | /* 57404 */ // Label 1733: @57404 |
| 20874 | /* 57404 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1737*/ GIMT_Encode4(57449), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1430 // |
| 20875 | /* 57411 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20876 | /* 57414 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20877 | /* 57417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20878 | /* 57421 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20879 | /* 57425 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20880 | /* 57429 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4091:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20881 | /* 57429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs32), |
| 20882 | /* 57432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20883 | /* 57434 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20884 | /* 57436 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20885 | /* 57438 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20886 | /* 57441 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20887 | /* 57447 */ GIR_RootConstrainSelectedInstOperands, |
| 20888 | /* 57448 */ // GIR_Coverage, 1430, |
| 20889 | /* 57448 */ GIR_EraseRootFromParent_Done, |
| 20890 | /* 57449 */ // Label 1737: @57449 |
| 20891 | /* 57449 */ GIM_Reject, |
| 20892 | /* 57450 */ // Label 1734: @57450 |
| 20893 | /* 57450 */ GIM_Reject, |
| 20894 | /* 57451 */ // Label 1730: @57451 |
| 20895 | /* 57451 */ GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(57631), |
| 20896 | /* 57456 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu), |
| 20897 | /* 57461 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1742*/ GIMT_Encode4(57630), |
| 20898 | /* 57472 */ /*GILLT_v8s8*//*Label 1739*/ GIMT_Encode4(57492), GIMT_Encode4(0), |
| 20899 | /* 57480 */ /*GILLT_v4s16*//*Label 1740*/ GIMT_Encode4(57538), GIMT_Encode4(0), |
| 20900 | /* 57488 */ /*GILLT_v2s32*//*Label 1741*/ GIMT_Encode4(57584), |
| 20901 | /* 57492 */ // Label 1739: @57492 |
| 20902 | /* 57492 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1743*/ GIMT_Encode4(57537), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1431 // |
| 20903 | /* 57499 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 20904 | /* 57502 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 20905 | /* 57505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20906 | /* 57509 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20907 | /* 57513 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20908 | /* 57517 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4092:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 20909 | /* 57517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu8), |
| 20910 | /* 57520 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20911 | /* 57522 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20912 | /* 57524 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20913 | /* 57526 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20914 | /* 57529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20915 | /* 57535 */ GIR_RootConstrainSelectedInstOperands, |
| 20916 | /* 57536 */ // GIR_Coverage, 1431, |
| 20917 | /* 57536 */ GIR_EraseRootFromParent_Done, |
| 20918 | /* 57537 */ // Label 1743: @57537 |
| 20919 | /* 57537 */ GIM_Reject, |
| 20920 | /* 57538 */ // Label 1740: @57538 |
| 20921 | /* 57538 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1744*/ GIMT_Encode4(57583), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1432 // |
| 20922 | /* 57545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20923 | /* 57548 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20924 | /* 57551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20925 | /* 57555 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20926 | /* 57559 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20927 | /* 57563 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4092:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 20928 | /* 57563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu16), |
| 20929 | /* 57566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20930 | /* 57568 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20931 | /* 57570 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20932 | /* 57572 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20933 | /* 57575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20934 | /* 57581 */ GIR_RootConstrainSelectedInstOperands, |
| 20935 | /* 57582 */ // GIR_Coverage, 1432, |
| 20936 | /* 57582 */ GIR_EraseRootFromParent_Done, |
| 20937 | /* 57583 */ // Label 1744: @57583 |
| 20938 | /* 57583 */ GIM_Reject, |
| 20939 | /* 57584 */ // Label 1741: @57584 |
| 20940 | /* 57584 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1745*/ GIMT_Encode4(57629), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1433 // |
| 20941 | /* 57591 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20942 | /* 57594 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20943 | /* 57597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20944 | /* 57601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20945 | /* 57605 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20946 | /* 57609 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4092:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 20947 | /* 57609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu32), |
| 20948 | /* 57612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20949 | /* 57614 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20950 | /* 57616 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20951 | /* 57618 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20952 | /* 57621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20953 | /* 57627 */ GIR_RootConstrainSelectedInstOperands, |
| 20954 | /* 57628 */ // GIR_Coverage, 1433, |
| 20955 | /* 57628 */ GIR_EraseRootFromParent_Done, |
| 20956 | /* 57629 */ // Label 1745: @57629 |
| 20957 | /* 57629 */ GIM_Reject, |
| 20958 | /* 57630 */ // Label 1742: @57630 |
| 20959 | /* 57630 */ GIM_Reject, |
| 20960 | /* 57631 */ // Label 1738: @57631 |
| 20961 | /* 57631 */ GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(57757), |
| 20962 | /* 57636 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs), |
| 20963 | /* 57641 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 1749*/ GIMT_Encode4(57756), |
| 20964 | /* 57652 */ /*GILLT_v4s16*//*Label 1747*/ GIMT_Encode4(57664), GIMT_Encode4(0), |
| 20965 | /* 57660 */ /*GILLT_v2s32*//*Label 1748*/ GIMT_Encode4(57710), |
| 20966 | /* 57664 */ // Label 1747: @57664 |
| 20967 | /* 57664 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1750*/ GIMT_Encode4(57709), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1435 // |
| 20968 | /* 57671 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 20969 | /* 57674 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 20970 | /* 57677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20971 | /* 57681 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20972 | /* 57685 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20973 | /* 57689 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4091:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMAXh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 20974 | /* 57689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXh), |
| 20975 | /* 57692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20976 | /* 57694 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20977 | /* 57696 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20978 | /* 57698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20979 | /* 57701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20980 | /* 57707 */ GIR_RootConstrainSelectedInstOperands, |
| 20981 | /* 57708 */ // GIR_Coverage, 1435, |
| 20982 | /* 57708 */ GIR_EraseRootFromParent_Done, |
| 20983 | /* 57709 */ // Label 1750: @57709 |
| 20984 | /* 57709 */ GIM_Reject, |
| 20985 | /* 57710 */ // Label 1748: @57710 |
| 20986 | /* 57710 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1751*/ GIMT_Encode4(57755), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1434 // |
| 20987 | /* 57717 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 20988 | /* 57720 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 20989 | /* 57723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20990 | /* 57727 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20991 | /* 57731 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 20992 | /* 57735 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4091:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMAXf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 20993 | /* 57735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXf), |
| 20994 | /* 57738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 20995 | /* 57740 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 20996 | /* 57742 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 20997 | /* 57744 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 20998 | /* 57747 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 20999 | /* 57753 */ GIR_RootConstrainSelectedInstOperands, |
| 21000 | /* 57754 */ // GIR_Coverage, 1434, |
| 21001 | /* 57754 */ GIR_EraseRootFromParent_Done, |
| 21002 | /* 57755 */ // Label 1751: @57755 |
| 21003 | /* 57755 */ GIM_Reject, |
| 21004 | /* 57756 */ // Label 1749: @57756 |
| 21005 | /* 57756 */ GIM_Reject, |
| 21006 | /* 57757 */ // Label 1746: @57757 |
| 21007 | /* 57757 */ GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(57937), |
| 21008 | /* 57762 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 21009 | /* 57767 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1756*/ GIMT_Encode4(57936), |
| 21010 | /* 57778 */ /*GILLT_v8s8*//*Label 1753*/ GIMT_Encode4(57798), GIMT_Encode4(0), |
| 21011 | /* 57786 */ /*GILLT_v4s16*//*Label 1754*/ GIMT_Encode4(57844), GIMT_Encode4(0), |
| 21012 | /* 57794 */ /*GILLT_v2s32*//*Label 1755*/ GIMT_Encode4(57890), |
| 21013 | /* 57798 */ // Label 1753: @57798 |
| 21014 | /* 57798 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1757*/ GIMT_Encode4(57843), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1436 // |
| 21015 | /* 57805 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21016 | /* 57808 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21017 | /* 57811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21018 | /* 57815 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21019 | /* 57819 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21020 | /* 57823 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4093:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 21021 | /* 57823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs8), |
| 21022 | /* 57826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21023 | /* 57828 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21024 | /* 57830 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21025 | /* 57832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21026 | /* 57835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21027 | /* 57841 */ GIR_RootConstrainSelectedInstOperands, |
| 21028 | /* 57842 */ // GIR_Coverage, 1436, |
| 21029 | /* 57842 */ GIR_EraseRootFromParent_Done, |
| 21030 | /* 57843 */ // Label 1757: @57843 |
| 21031 | /* 57843 */ GIM_Reject, |
| 21032 | /* 57844 */ // Label 1754: @57844 |
| 21033 | /* 57844 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1758*/ GIMT_Encode4(57889), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1437 // |
| 21034 | /* 57851 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21035 | /* 57854 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21036 | /* 57857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21037 | /* 57861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21038 | /* 57865 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21039 | /* 57869 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4093:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 21040 | /* 57869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs16), |
| 21041 | /* 57872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21042 | /* 57874 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21043 | /* 57876 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21044 | /* 57878 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21045 | /* 57881 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21046 | /* 57887 */ GIR_RootConstrainSelectedInstOperands, |
| 21047 | /* 57888 */ // GIR_Coverage, 1437, |
| 21048 | /* 57888 */ GIR_EraseRootFromParent_Done, |
| 21049 | /* 57889 */ // Label 1758: @57889 |
| 21050 | /* 57889 */ GIM_Reject, |
| 21051 | /* 57890 */ // Label 1755: @57890 |
| 21052 | /* 57890 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1759*/ GIMT_Encode4(57935), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1438 // |
| 21053 | /* 57897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21054 | /* 57900 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21055 | /* 57903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21056 | /* 57907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21057 | /* 57911 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21058 | /* 57915 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4093:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 21059 | /* 57915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs32), |
| 21060 | /* 57918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21061 | /* 57920 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21062 | /* 57922 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21063 | /* 57924 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21064 | /* 57927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21065 | /* 57933 */ GIR_RootConstrainSelectedInstOperands, |
| 21066 | /* 57934 */ // GIR_Coverage, 1438, |
| 21067 | /* 57934 */ GIR_EraseRootFromParent_Done, |
| 21068 | /* 57935 */ // Label 1759: @57935 |
| 21069 | /* 57935 */ GIM_Reject, |
| 21070 | /* 57936 */ // Label 1756: @57936 |
| 21071 | /* 57936 */ GIM_Reject, |
| 21072 | /* 57937 */ // Label 1752: @57937 |
| 21073 | /* 57937 */ GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(58117), |
| 21074 | /* 57942 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu), |
| 21075 | /* 57947 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1764*/ GIMT_Encode4(58116), |
| 21076 | /* 57958 */ /*GILLT_v8s8*//*Label 1761*/ GIMT_Encode4(57978), GIMT_Encode4(0), |
| 21077 | /* 57966 */ /*GILLT_v4s16*//*Label 1762*/ GIMT_Encode4(58024), GIMT_Encode4(0), |
| 21078 | /* 57974 */ /*GILLT_v2s32*//*Label 1763*/ GIMT_Encode4(58070), |
| 21079 | /* 57978 */ // Label 1761: @57978 |
| 21080 | /* 57978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1765*/ GIMT_Encode4(58023), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1439 // |
| 21081 | /* 57985 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21082 | /* 57988 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21083 | /* 57991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21084 | /* 57995 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21085 | /* 57999 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21086 | /* 58003 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4094:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 21087 | /* 58003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu8), |
| 21088 | /* 58006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21089 | /* 58008 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21090 | /* 58010 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21091 | /* 58012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21092 | /* 58015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21093 | /* 58021 */ GIR_RootConstrainSelectedInstOperands, |
| 21094 | /* 58022 */ // GIR_Coverage, 1439, |
| 21095 | /* 58022 */ GIR_EraseRootFromParent_Done, |
| 21096 | /* 58023 */ // Label 1765: @58023 |
| 21097 | /* 58023 */ GIM_Reject, |
| 21098 | /* 58024 */ // Label 1762: @58024 |
| 21099 | /* 58024 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1766*/ GIMT_Encode4(58069), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1440 // |
| 21100 | /* 58031 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21101 | /* 58034 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21102 | /* 58037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21103 | /* 58041 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21104 | /* 58045 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21105 | /* 58049 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4094:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 21106 | /* 58049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu16), |
| 21107 | /* 58052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21108 | /* 58054 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21109 | /* 58056 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21110 | /* 58058 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21111 | /* 58061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21112 | /* 58067 */ GIR_RootConstrainSelectedInstOperands, |
| 21113 | /* 58068 */ // GIR_Coverage, 1440, |
| 21114 | /* 58068 */ GIR_EraseRootFromParent_Done, |
| 21115 | /* 58069 */ // Label 1766: @58069 |
| 21116 | /* 58069 */ GIM_Reject, |
| 21117 | /* 58070 */ // Label 1763: @58070 |
| 21118 | /* 58070 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1767*/ GIMT_Encode4(58115), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1441 // |
| 21119 | /* 58077 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21120 | /* 58080 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21121 | /* 58083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21122 | /* 58087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21123 | /* 58091 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21124 | /* 58095 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4094:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 21125 | /* 58095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu32), |
| 21126 | /* 58098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21127 | /* 58100 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21128 | /* 58102 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21129 | /* 58104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21130 | /* 58107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21131 | /* 58113 */ GIR_RootConstrainSelectedInstOperands, |
| 21132 | /* 58114 */ // GIR_Coverage, 1441, |
| 21133 | /* 58114 */ GIR_EraseRootFromParent_Done, |
| 21134 | /* 58115 */ // Label 1767: @58115 |
| 21135 | /* 58115 */ GIM_Reject, |
| 21136 | /* 58116 */ // Label 1764: @58116 |
| 21137 | /* 58116 */ GIM_Reject, |
| 21138 | /* 58117 */ // Label 1760: @58117 |
| 21139 | /* 58117 */ GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(58243), |
| 21140 | /* 58122 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins), |
| 21141 | /* 58127 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 1771*/ GIMT_Encode4(58242), |
| 21142 | /* 58138 */ /*GILLT_v4s16*//*Label 1769*/ GIMT_Encode4(58150), GIMT_Encode4(0), |
| 21143 | /* 58146 */ /*GILLT_v2s32*//*Label 1770*/ GIMT_Encode4(58196), |
| 21144 | /* 58150 */ // Label 1769: @58150 |
| 21145 | /* 58150 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1772*/ GIMT_Encode4(58195), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1443 // |
| 21146 | /* 58157 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21147 | /* 58160 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21148 | /* 58163 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21149 | /* 58167 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21150 | /* 58171 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21151 | /* 58175 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4093:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMINh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 21152 | /* 58175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINh), |
| 21153 | /* 58178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21154 | /* 58180 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21155 | /* 58182 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21156 | /* 58184 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21157 | /* 58187 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21158 | /* 58193 */ GIR_RootConstrainSelectedInstOperands, |
| 21159 | /* 58194 */ // GIR_Coverage, 1443, |
| 21160 | /* 58194 */ GIR_EraseRootFromParent_Done, |
| 21161 | /* 58195 */ // Label 1772: @58195 |
| 21162 | /* 58195 */ GIM_Reject, |
| 21163 | /* 58196 */ // Label 1770: @58196 |
| 21164 | /* 58196 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1773*/ GIMT_Encode4(58241), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1442 // |
| 21165 | /* 58203 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21166 | /* 58206 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21167 | /* 58209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21168 | /* 58213 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21169 | /* 58217 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21170 | /* 58221 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4093:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMINf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 21171 | /* 58221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINf), |
| 21172 | /* 58224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21173 | /* 58226 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21174 | /* 58228 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21175 | /* 58230 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21176 | /* 58233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21177 | /* 58239 */ GIR_RootConstrainSelectedInstOperands, |
| 21178 | /* 58240 */ // GIR_Coverage, 1442, |
| 21179 | /* 58240 */ GIR_EraseRootFromParent_Done, |
| 21180 | /* 58241 */ // Label 1773: @58241 |
| 21181 | /* 58241 */ GIM_Reject, |
| 21182 | /* 58242 */ // Label 1771: @58242 |
| 21183 | /* 58242 */ GIM_Reject, |
| 21184 | /* 58243 */ // Label 1768: @58243 |
| 21185 | /* 58243 */ GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(58465), |
| 21186 | /* 58248 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps), |
| 21187 | /* 58253 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1779*/ GIMT_Encode4(58464), |
| 21188 | /* 58264 */ /*GILLT_v4s16*//*Label 1775*/ GIMT_Encode4(58280), |
| 21189 | /* 58268 */ /*GILLT_v8s16*//*Label 1776*/ GIMT_Encode4(58326), |
| 21190 | /* 58272 */ /*GILLT_v2s32*//*Label 1777*/ GIMT_Encode4(58372), |
| 21191 | /* 58276 */ /*GILLT_v4s32*//*Label 1778*/ GIMT_Encode4(58418), |
| 21192 | /* 58280 */ // Label 1775: @58280 |
| 21193 | /* 58280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1780*/ GIMT_Encode4(58325), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1452 // |
| 21194 | /* 58287 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21195 | /* 58290 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21196 | /* 58293 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21197 | /* 58297 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21198 | /* 58301 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21199 | /* 58305 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4118:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRECPShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 21200 | /* 58305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShd), |
| 21201 | /* 58308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21202 | /* 58310 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21203 | /* 58312 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21204 | /* 58314 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21205 | /* 58317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21206 | /* 58323 */ GIR_RootConstrainSelectedInstOperands, |
| 21207 | /* 58324 */ // GIR_Coverage, 1452, |
| 21208 | /* 58324 */ GIR_EraseRootFromParent_Done, |
| 21209 | /* 58325 */ // Label 1780: @58325 |
| 21210 | /* 58325 */ GIM_Reject, |
| 21211 | /* 58326 */ // Label 1776: @58326 |
| 21212 | /* 58326 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1781*/ GIMT_Encode4(58371), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1453 // |
| 21213 | /* 58333 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21214 | /* 58336 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21215 | /* 58339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21216 | /* 58343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21217 | /* 58347 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21218 | /* 58351 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4118:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRECPShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 21219 | /* 58351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShq), |
| 21220 | /* 58354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21221 | /* 58356 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21222 | /* 58358 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21223 | /* 58360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21224 | /* 58363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21225 | /* 58369 */ GIR_RootConstrainSelectedInstOperands, |
| 21226 | /* 58370 */ // GIR_Coverage, 1453, |
| 21227 | /* 58370 */ GIR_EraseRootFromParent_Done, |
| 21228 | /* 58371 */ // Label 1781: @58371 |
| 21229 | /* 58371 */ GIM_Reject, |
| 21230 | /* 58372 */ // Label 1777: @58372 |
| 21231 | /* 58372 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1782*/ GIMT_Encode4(58417), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1450 // |
| 21232 | /* 58379 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21233 | /* 58382 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21234 | /* 58385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21235 | /* 58389 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21236 | /* 58393 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21237 | /* 58397 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4118:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRECPSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 21238 | /* 58397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfd), |
| 21239 | /* 58400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21240 | /* 58402 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21241 | /* 58404 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21242 | /* 58406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21243 | /* 58409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21244 | /* 58415 */ GIR_RootConstrainSelectedInstOperands, |
| 21245 | /* 58416 */ // GIR_Coverage, 1450, |
| 21246 | /* 58416 */ GIR_EraseRootFromParent_Done, |
| 21247 | /* 58417 */ // Label 1782: @58417 |
| 21248 | /* 58417 */ GIM_Reject, |
| 21249 | /* 58418 */ // Label 1778: @58418 |
| 21250 | /* 58418 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1783*/ GIMT_Encode4(58463), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1451 // |
| 21251 | /* 58425 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21252 | /* 58428 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21253 | /* 58431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21254 | /* 58435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21255 | /* 58439 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21256 | /* 58443 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4118:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRECPSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 21257 | /* 58443 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfq), |
| 21258 | /* 58446 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21259 | /* 58448 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21260 | /* 58450 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21261 | /* 58452 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21262 | /* 58455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21263 | /* 58461 */ GIR_RootConstrainSelectedInstOperands, |
| 21264 | /* 58462 */ // GIR_Coverage, 1451, |
| 21265 | /* 58462 */ GIR_EraseRootFromParent_Done, |
| 21266 | /* 58463 */ // Label 1783: @58463 |
| 21267 | /* 58463 */ GIM_Reject, |
| 21268 | /* 58464 */ // Label 1779: @58464 |
| 21269 | /* 58464 */ GIM_Reject, |
| 21270 | /* 58465 */ // Label 1774: @58465 |
| 21271 | /* 58465 */ GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(58687), |
| 21272 | /* 58470 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts), |
| 21273 | /* 58475 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1789*/ GIMT_Encode4(58686), |
| 21274 | /* 58486 */ /*GILLT_v4s16*//*Label 1785*/ GIMT_Encode4(58502), |
| 21275 | /* 58490 */ /*GILLT_v8s16*//*Label 1786*/ GIMT_Encode4(58548), |
| 21276 | /* 58494 */ /*GILLT_v2s32*//*Label 1787*/ GIMT_Encode4(58594), |
| 21277 | /* 58498 */ /*GILLT_v4s32*//*Label 1788*/ GIMT_Encode4(58640), |
| 21278 | /* 58502 */ // Label 1785: @58502 |
| 21279 | /* 58502 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1790*/ GIMT_Encode4(58547), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1462 // |
| 21280 | /* 58509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21281 | /* 58512 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21282 | /* 58515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21283 | /* 58519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21284 | /* 58523 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21285 | /* 58527 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4125:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 21286 | /* 58527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShd), |
| 21287 | /* 58530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21288 | /* 58532 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21289 | /* 58534 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21290 | /* 58536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21291 | /* 58539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21292 | /* 58545 */ GIR_RootConstrainSelectedInstOperands, |
| 21293 | /* 58546 */ // GIR_Coverage, 1462, |
| 21294 | /* 58546 */ GIR_EraseRootFromParent_Done, |
| 21295 | /* 58547 */ // Label 1790: @58547 |
| 21296 | /* 58547 */ GIM_Reject, |
| 21297 | /* 58548 */ // Label 1786: @58548 |
| 21298 | /* 58548 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1791*/ GIMT_Encode4(58593), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1463 // |
| 21299 | /* 58555 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21300 | /* 58558 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21301 | /* 58561 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21302 | /* 58565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21303 | /* 58569 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21304 | /* 58573 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4125:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 21305 | /* 58573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShq), |
| 21306 | /* 58576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21307 | /* 58578 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21308 | /* 58580 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21309 | /* 58582 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21310 | /* 58585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21311 | /* 58591 */ GIR_RootConstrainSelectedInstOperands, |
| 21312 | /* 58592 */ // GIR_Coverage, 1463, |
| 21313 | /* 58592 */ GIR_EraseRootFromParent_Done, |
| 21314 | /* 58593 */ // Label 1791: @58593 |
| 21315 | /* 58593 */ GIM_Reject, |
| 21316 | /* 58594 */ // Label 1787: @58594 |
| 21317 | /* 58594 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1792*/ GIMT_Encode4(58639), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1460 // |
| 21318 | /* 58601 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21319 | /* 58604 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21320 | /* 58607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21321 | /* 58611 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21322 | /* 58615 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21323 | /* 58619 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4125:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 21324 | /* 58619 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfd), |
| 21325 | /* 58622 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21326 | /* 58624 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21327 | /* 58626 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21328 | /* 58628 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21329 | /* 58631 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21330 | /* 58637 */ GIR_RootConstrainSelectedInstOperands, |
| 21331 | /* 58638 */ // GIR_Coverage, 1460, |
| 21332 | /* 58638 */ GIR_EraseRootFromParent_Done, |
| 21333 | /* 58639 */ // Label 1792: @58639 |
| 21334 | /* 58639 */ GIM_Reject, |
| 21335 | /* 58640 */ // Label 1788: @58640 |
| 21336 | /* 58640 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1793*/ GIMT_Encode4(58685), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1461 // |
| 21337 | /* 58647 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21338 | /* 58650 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21339 | /* 58653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21340 | /* 58657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21341 | /* 58661 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21342 | /* 58665 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4125:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 21343 | /* 58665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfq), |
| 21344 | /* 58668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21345 | /* 58670 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn |
| 21346 | /* 58672 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 21347 | /* 58674 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21348 | /* 58677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21349 | /* 58683 */ GIR_RootConstrainSelectedInstOperands, |
| 21350 | /* 58684 */ // GIR_Coverage, 1461, |
| 21351 | /* 58684 */ GIR_EraseRootFromParent_Done, |
| 21352 | /* 58685 */ // Label 1793: @58685 |
| 21353 | /* 58685 */ GIM_Reject, |
| 21354 | /* 58686 */ // Label 1789: @58686 |
| 21355 | /* 58686 */ GIM_Reject, |
| 21356 | /* 58687 */ // Label 1784: @58687 |
| 21357 | /* 58687 */ GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(59125), |
| 21358 | /* 58692 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts), |
| 21359 | /* 58697 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1803*/ GIMT_Encode4(59124), |
| 21360 | /* 58708 */ /*GILLT_s64*//*Label 1795*/ GIMT_Encode4(58756), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 21361 | /* 58728 */ /*GILLT_v8s8*//*Label 1796*/ GIMT_Encode4(58802), |
| 21362 | /* 58732 */ /*GILLT_v16s8*//*Label 1797*/ GIMT_Encode4(58848), |
| 21363 | /* 58736 */ /*GILLT_v4s16*//*Label 1798*/ GIMT_Encode4(58894), |
| 21364 | /* 58740 */ /*GILLT_v8s16*//*Label 1799*/ GIMT_Encode4(58940), |
| 21365 | /* 58744 */ /*GILLT_v2s32*//*Label 1800*/ GIMT_Encode4(58986), |
| 21366 | /* 58748 */ /*GILLT_v4s32*//*Label 1801*/ GIMT_Encode4(59032), |
| 21367 | /* 58752 */ /*GILLT_v2s64*//*Label 1802*/ GIMT_Encode4(59078), |
| 21368 | /* 58756 */ // Label 1795: @58756 |
| 21369 | /* 58756 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1804*/ GIMT_Encode4(58801), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1470 // |
| 21370 | /* 58763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 21371 | /* 58766 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 21372 | /* 58769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21373 | /* 58773 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21374 | /* 58777 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21375 | /* 58781 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4128:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 21376 | /* 58781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv1i64), |
| 21377 | /* 58784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21378 | /* 58786 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21379 | /* 58788 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21380 | /* 58790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21381 | /* 58793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21382 | /* 58799 */ GIR_RootConstrainSelectedInstOperands, |
| 21383 | /* 58800 */ // GIR_Coverage, 1470, |
| 21384 | /* 58800 */ GIR_EraseRootFromParent_Done, |
| 21385 | /* 58801 */ // Label 1804: @58801 |
| 21386 | /* 58801 */ GIM_Reject, |
| 21387 | /* 58802 */ // Label 1796: @58802 |
| 21388 | /* 58802 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1805*/ GIMT_Encode4(58847), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1468 // |
| 21389 | /* 58809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21390 | /* 58812 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21391 | /* 58815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21392 | /* 58819 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21393 | /* 58823 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21394 | /* 58827 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4128:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 21395 | /* 58827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i8), |
| 21396 | /* 58830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21397 | /* 58832 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21398 | /* 58834 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21399 | /* 58836 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21400 | /* 58839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21401 | /* 58845 */ GIR_RootConstrainSelectedInstOperands, |
| 21402 | /* 58846 */ // GIR_Coverage, 1468, |
| 21403 | /* 58846 */ GIR_EraseRootFromParent_Done, |
| 21404 | /* 58847 */ // Label 1805: @58847 |
| 21405 | /* 58847 */ GIM_Reject, |
| 21406 | /* 58848 */ // Label 1797: @58848 |
| 21407 | /* 58848 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1806*/ GIMT_Encode4(58893), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1469 // |
| 21408 | /* 58855 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21409 | /* 58858 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21410 | /* 58861 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21411 | /* 58865 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21412 | /* 58869 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21413 | /* 58873 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4128:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 21414 | /* 58873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv16i8), |
| 21415 | /* 58876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21416 | /* 58878 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21417 | /* 58880 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21418 | /* 58882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21419 | /* 58885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21420 | /* 58891 */ GIR_RootConstrainSelectedInstOperands, |
| 21421 | /* 58892 */ // GIR_Coverage, 1469, |
| 21422 | /* 58892 */ GIR_EraseRootFromParent_Done, |
| 21423 | /* 58893 */ // Label 1806: @58893 |
| 21424 | /* 58893 */ GIM_Reject, |
| 21425 | /* 58894 */ // Label 1798: @58894 |
| 21426 | /* 58894 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1807*/ GIMT_Encode4(58939), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1464 // |
| 21427 | /* 58901 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21428 | /* 58904 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21429 | /* 58907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21430 | /* 58911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21431 | /* 58915 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21432 | /* 58919 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4128:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 21433 | /* 58919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i16), |
| 21434 | /* 58922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21435 | /* 58924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21436 | /* 58926 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21437 | /* 58928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21438 | /* 58931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21439 | /* 58937 */ GIR_RootConstrainSelectedInstOperands, |
| 21440 | /* 58938 */ // GIR_Coverage, 1464, |
| 21441 | /* 58938 */ GIR_EraseRootFromParent_Done, |
| 21442 | /* 58939 */ // Label 1807: @58939 |
| 21443 | /* 58939 */ GIM_Reject, |
| 21444 | /* 58940 */ // Label 1799: @58940 |
| 21445 | /* 58940 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1808*/ GIMT_Encode4(58985), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1466 // |
| 21446 | /* 58947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21447 | /* 58950 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21448 | /* 58953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21449 | /* 58957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21450 | /* 58961 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21451 | /* 58965 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4128:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 21452 | /* 58965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i16), |
| 21453 | /* 58968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21454 | /* 58970 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21455 | /* 58972 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21456 | /* 58974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21457 | /* 58977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21458 | /* 58983 */ GIR_RootConstrainSelectedInstOperands, |
| 21459 | /* 58984 */ // GIR_Coverage, 1466, |
| 21460 | /* 58984 */ GIR_EraseRootFromParent_Done, |
| 21461 | /* 58985 */ // Label 1808: @58985 |
| 21462 | /* 58985 */ GIM_Reject, |
| 21463 | /* 58986 */ // Label 1800: @58986 |
| 21464 | /* 58986 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1809*/ GIMT_Encode4(59031), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1465 // |
| 21465 | /* 58993 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21466 | /* 58996 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21467 | /* 58999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21468 | /* 59003 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21469 | /* 59007 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21470 | /* 59011 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4128:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 21471 | /* 59011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i32), |
| 21472 | /* 59014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21473 | /* 59016 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21474 | /* 59018 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21475 | /* 59020 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21476 | /* 59023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21477 | /* 59029 */ GIR_RootConstrainSelectedInstOperands, |
| 21478 | /* 59030 */ // GIR_Coverage, 1465, |
| 21479 | /* 59030 */ GIR_EraseRootFromParent_Done, |
| 21480 | /* 59031 */ // Label 1809: @59031 |
| 21481 | /* 59031 */ GIM_Reject, |
| 21482 | /* 59032 */ // Label 1801: @59032 |
| 21483 | /* 59032 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1810*/ GIMT_Encode4(59077), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1467 // |
| 21484 | /* 59039 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21485 | /* 59042 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21486 | /* 59045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21487 | /* 59049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21488 | /* 59053 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21489 | /* 59057 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4128:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 21490 | /* 59057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i32), |
| 21491 | /* 59060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21492 | /* 59062 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21493 | /* 59064 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21494 | /* 59066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21495 | /* 59069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21496 | /* 59075 */ GIR_RootConstrainSelectedInstOperands, |
| 21497 | /* 59076 */ // GIR_Coverage, 1467, |
| 21498 | /* 59076 */ GIR_EraseRootFromParent_Done, |
| 21499 | /* 59077 */ // Label 1810: @59077 |
| 21500 | /* 59077 */ GIM_Reject, |
| 21501 | /* 59078 */ // Label 1802: @59078 |
| 21502 | /* 59078 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1811*/ GIMT_Encode4(59123), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1471 // |
| 21503 | /* 59085 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21504 | /* 59088 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 21505 | /* 59091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21506 | /* 59095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21507 | /* 59099 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21508 | /* 59103 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4128:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 21509 | /* 59103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i64), |
| 21510 | /* 59106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21511 | /* 59108 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21512 | /* 59110 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21513 | /* 59112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21514 | /* 59115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21515 | /* 59121 */ GIR_RootConstrainSelectedInstOperands, |
| 21516 | /* 59122 */ // GIR_Coverage, 1471, |
| 21517 | /* 59122 */ GIR_EraseRootFromParent_Done, |
| 21518 | /* 59123 */ // Label 1811: @59123 |
| 21519 | /* 59123 */ GIM_Reject, |
| 21520 | /* 59124 */ // Label 1803: @59124 |
| 21521 | /* 59124 */ GIM_Reject, |
| 21522 | /* 59125 */ // Label 1794: @59125 |
| 21523 | /* 59125 */ GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(59563), |
| 21524 | /* 59130 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu), |
| 21525 | /* 59135 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1821*/ GIMT_Encode4(59562), |
| 21526 | /* 59146 */ /*GILLT_s64*//*Label 1813*/ GIMT_Encode4(59194), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 21527 | /* 59166 */ /*GILLT_v8s8*//*Label 1814*/ GIMT_Encode4(59240), |
| 21528 | /* 59170 */ /*GILLT_v16s8*//*Label 1815*/ GIMT_Encode4(59286), |
| 21529 | /* 59174 */ /*GILLT_v4s16*//*Label 1816*/ GIMT_Encode4(59332), |
| 21530 | /* 59178 */ /*GILLT_v8s16*//*Label 1817*/ GIMT_Encode4(59378), |
| 21531 | /* 59182 */ /*GILLT_v2s32*//*Label 1818*/ GIMT_Encode4(59424), |
| 21532 | /* 59186 */ /*GILLT_v4s32*//*Label 1819*/ GIMT_Encode4(59470), |
| 21533 | /* 59190 */ /*GILLT_v2s64*//*Label 1820*/ GIMT_Encode4(59516), |
| 21534 | /* 59194 */ // Label 1813: @59194 |
| 21535 | /* 59194 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1822*/ GIMT_Encode4(59239), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1478 // |
| 21536 | /* 59201 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 21537 | /* 59204 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 21538 | /* 59207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21539 | /* 59211 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21540 | /* 59215 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21541 | /* 59219 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4129:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 21542 | /* 59219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv1i64), |
| 21543 | /* 59222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21544 | /* 59224 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21545 | /* 59226 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21546 | /* 59228 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21547 | /* 59231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21548 | /* 59237 */ GIR_RootConstrainSelectedInstOperands, |
| 21549 | /* 59238 */ // GIR_Coverage, 1478, |
| 21550 | /* 59238 */ GIR_EraseRootFromParent_Done, |
| 21551 | /* 59239 */ // Label 1822: @59239 |
| 21552 | /* 59239 */ GIM_Reject, |
| 21553 | /* 59240 */ // Label 1814: @59240 |
| 21554 | /* 59240 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1823*/ GIMT_Encode4(59285), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1476 // |
| 21555 | /* 59247 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21556 | /* 59250 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21557 | /* 59253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21558 | /* 59257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21559 | /* 59261 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21560 | /* 59265 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4129:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 21561 | /* 59265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i8), |
| 21562 | /* 59268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21563 | /* 59270 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21564 | /* 59272 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21565 | /* 59274 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21566 | /* 59277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21567 | /* 59283 */ GIR_RootConstrainSelectedInstOperands, |
| 21568 | /* 59284 */ // GIR_Coverage, 1476, |
| 21569 | /* 59284 */ GIR_EraseRootFromParent_Done, |
| 21570 | /* 59285 */ // Label 1823: @59285 |
| 21571 | /* 59285 */ GIM_Reject, |
| 21572 | /* 59286 */ // Label 1815: @59286 |
| 21573 | /* 59286 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1824*/ GIMT_Encode4(59331), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1477 // |
| 21574 | /* 59293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21575 | /* 59296 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21576 | /* 59299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21577 | /* 59303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21578 | /* 59307 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21579 | /* 59311 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4129:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 21580 | /* 59311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv16i8), |
| 21581 | /* 59314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21582 | /* 59316 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21583 | /* 59318 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21584 | /* 59320 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21585 | /* 59323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21586 | /* 59329 */ GIR_RootConstrainSelectedInstOperands, |
| 21587 | /* 59330 */ // GIR_Coverage, 1477, |
| 21588 | /* 59330 */ GIR_EraseRootFromParent_Done, |
| 21589 | /* 59331 */ // Label 1824: @59331 |
| 21590 | /* 59331 */ GIM_Reject, |
| 21591 | /* 59332 */ // Label 1816: @59332 |
| 21592 | /* 59332 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1825*/ GIMT_Encode4(59377), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1472 // |
| 21593 | /* 59339 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21594 | /* 59342 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21595 | /* 59345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21596 | /* 59349 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21597 | /* 59353 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21598 | /* 59357 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4129:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 21599 | /* 59357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i16), |
| 21600 | /* 59360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21601 | /* 59362 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21602 | /* 59364 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21603 | /* 59366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21604 | /* 59369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21605 | /* 59375 */ GIR_RootConstrainSelectedInstOperands, |
| 21606 | /* 59376 */ // GIR_Coverage, 1472, |
| 21607 | /* 59376 */ GIR_EraseRootFromParent_Done, |
| 21608 | /* 59377 */ // Label 1825: @59377 |
| 21609 | /* 59377 */ GIM_Reject, |
| 21610 | /* 59378 */ // Label 1817: @59378 |
| 21611 | /* 59378 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1826*/ GIMT_Encode4(59423), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1474 // |
| 21612 | /* 59385 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21613 | /* 59388 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21614 | /* 59391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21615 | /* 59395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21616 | /* 59399 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21617 | /* 59403 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4129:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 21618 | /* 59403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i16), |
| 21619 | /* 59406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21620 | /* 59408 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21621 | /* 59410 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21622 | /* 59412 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21623 | /* 59415 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21624 | /* 59421 */ GIR_RootConstrainSelectedInstOperands, |
| 21625 | /* 59422 */ // GIR_Coverage, 1474, |
| 21626 | /* 59422 */ GIR_EraseRootFromParent_Done, |
| 21627 | /* 59423 */ // Label 1826: @59423 |
| 21628 | /* 59423 */ GIM_Reject, |
| 21629 | /* 59424 */ // Label 1818: @59424 |
| 21630 | /* 59424 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1827*/ GIMT_Encode4(59469), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1473 // |
| 21631 | /* 59431 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21632 | /* 59434 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21633 | /* 59437 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21634 | /* 59441 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21635 | /* 59445 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21636 | /* 59449 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4129:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 21637 | /* 59449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i32), |
| 21638 | /* 59452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21639 | /* 59454 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21640 | /* 59456 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21641 | /* 59458 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21642 | /* 59461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21643 | /* 59467 */ GIR_RootConstrainSelectedInstOperands, |
| 21644 | /* 59468 */ // GIR_Coverage, 1473, |
| 21645 | /* 59468 */ GIR_EraseRootFromParent_Done, |
| 21646 | /* 59469 */ // Label 1827: @59469 |
| 21647 | /* 59469 */ GIM_Reject, |
| 21648 | /* 59470 */ // Label 1819: @59470 |
| 21649 | /* 59470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1828*/ GIMT_Encode4(59515), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1475 // |
| 21650 | /* 59477 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21651 | /* 59480 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21652 | /* 59483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21653 | /* 59487 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21654 | /* 59491 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21655 | /* 59495 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4129:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 21656 | /* 59495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i32), |
| 21657 | /* 59498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21658 | /* 59500 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21659 | /* 59502 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21660 | /* 59504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21661 | /* 59507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21662 | /* 59513 */ GIR_RootConstrainSelectedInstOperands, |
| 21663 | /* 59514 */ // GIR_Coverage, 1475, |
| 21664 | /* 59514 */ GIR_EraseRootFromParent_Done, |
| 21665 | /* 59515 */ // Label 1828: @59515 |
| 21666 | /* 59515 */ GIM_Reject, |
| 21667 | /* 59516 */ // Label 1820: @59516 |
| 21668 | /* 59516 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1829*/ GIMT_Encode4(59561), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1479 // |
| 21669 | /* 59523 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21670 | /* 59526 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 21671 | /* 59529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21672 | /* 59533 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21673 | /* 59537 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21674 | /* 59541 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4129:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 21675 | /* 59541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i64), |
| 21676 | /* 59544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21677 | /* 59546 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21678 | /* 59548 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21679 | /* 59550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21680 | /* 59553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21681 | /* 59559 */ GIR_RootConstrainSelectedInstOperands, |
| 21682 | /* 59560 */ // GIR_Coverage, 1479, |
| 21683 | /* 59560 */ GIR_EraseRootFromParent_Done, |
| 21684 | /* 59561 */ // Label 1829: @59561 |
| 21685 | /* 59561 */ GIM_Reject, |
| 21686 | /* 59562 */ // Label 1821: @59562 |
| 21687 | /* 59562 */ GIM_Reject, |
| 21688 | /* 59563 */ // Label 1812: @59563 |
| 21689 | /* 59563 */ GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(60001), |
| 21690 | /* 59568 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts), |
| 21691 | /* 59573 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1839*/ GIMT_Encode4(60000), |
| 21692 | /* 59584 */ /*GILLT_s64*//*Label 1831*/ GIMT_Encode4(59632), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 21693 | /* 59604 */ /*GILLT_v8s8*//*Label 1832*/ GIMT_Encode4(59678), |
| 21694 | /* 59608 */ /*GILLT_v16s8*//*Label 1833*/ GIMT_Encode4(59724), |
| 21695 | /* 59612 */ /*GILLT_v4s16*//*Label 1834*/ GIMT_Encode4(59770), |
| 21696 | /* 59616 */ /*GILLT_v8s16*//*Label 1835*/ GIMT_Encode4(59816), |
| 21697 | /* 59620 */ /*GILLT_v2s32*//*Label 1836*/ GIMT_Encode4(59862), |
| 21698 | /* 59624 */ /*GILLT_v4s32*//*Label 1837*/ GIMT_Encode4(59908), |
| 21699 | /* 59628 */ /*GILLT_v2s64*//*Label 1838*/ GIMT_Encode4(59954), |
| 21700 | /* 59632 */ // Label 1831: @59632 |
| 21701 | /* 59632 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1840*/ GIMT_Encode4(59677), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1519 // |
| 21702 | /* 59639 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 21703 | /* 59642 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 21704 | /* 59645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21705 | /* 59649 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21706 | /* 59653 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21707 | /* 59657 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4122:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 21708 | /* 59657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv1i64), |
| 21709 | /* 59660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21710 | /* 59662 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21711 | /* 59664 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21712 | /* 59666 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21713 | /* 59669 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21714 | /* 59675 */ GIR_RootConstrainSelectedInstOperands, |
| 21715 | /* 59676 */ // GIR_Coverage, 1519, |
| 21716 | /* 59676 */ GIR_EraseRootFromParent_Done, |
| 21717 | /* 59677 */ // Label 1840: @59677 |
| 21718 | /* 59677 */ GIM_Reject, |
| 21719 | /* 59678 */ // Label 1832: @59678 |
| 21720 | /* 59678 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1841*/ GIMT_Encode4(59723), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1517 // |
| 21721 | /* 59685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21722 | /* 59688 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21723 | /* 59691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21724 | /* 59695 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21725 | /* 59699 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21726 | /* 59703 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4122:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 21727 | /* 59703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i8), |
| 21728 | /* 59706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21729 | /* 59708 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21730 | /* 59710 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21731 | /* 59712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21732 | /* 59715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21733 | /* 59721 */ GIR_RootConstrainSelectedInstOperands, |
| 21734 | /* 59722 */ // GIR_Coverage, 1517, |
| 21735 | /* 59722 */ GIR_EraseRootFromParent_Done, |
| 21736 | /* 59723 */ // Label 1841: @59723 |
| 21737 | /* 59723 */ GIM_Reject, |
| 21738 | /* 59724 */ // Label 1833: @59724 |
| 21739 | /* 59724 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1842*/ GIMT_Encode4(59769), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1518 // |
| 21740 | /* 59731 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21741 | /* 59734 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21742 | /* 59737 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21743 | /* 59741 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21744 | /* 59745 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21745 | /* 59749 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4122:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 21746 | /* 59749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv16i8), |
| 21747 | /* 59752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21748 | /* 59754 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21749 | /* 59756 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21750 | /* 59758 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21751 | /* 59761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21752 | /* 59767 */ GIR_RootConstrainSelectedInstOperands, |
| 21753 | /* 59768 */ // GIR_Coverage, 1518, |
| 21754 | /* 59768 */ GIR_EraseRootFromParent_Done, |
| 21755 | /* 59769 */ // Label 1842: @59769 |
| 21756 | /* 59769 */ GIM_Reject, |
| 21757 | /* 59770 */ // Label 1834: @59770 |
| 21758 | /* 59770 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1843*/ GIMT_Encode4(59815), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1513 // |
| 21759 | /* 59777 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21760 | /* 59780 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21761 | /* 59783 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21762 | /* 59787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21763 | /* 59791 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21764 | /* 59795 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4122:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 21765 | /* 59795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i16), |
| 21766 | /* 59798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21767 | /* 59800 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21768 | /* 59802 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21769 | /* 59804 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21770 | /* 59807 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21771 | /* 59813 */ GIR_RootConstrainSelectedInstOperands, |
| 21772 | /* 59814 */ // GIR_Coverage, 1513, |
| 21773 | /* 59814 */ GIR_EraseRootFromParent_Done, |
| 21774 | /* 59815 */ // Label 1843: @59815 |
| 21775 | /* 59815 */ GIM_Reject, |
| 21776 | /* 59816 */ // Label 1835: @59816 |
| 21777 | /* 59816 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1844*/ GIMT_Encode4(59861), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1515 // |
| 21778 | /* 59823 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21779 | /* 59826 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21780 | /* 59829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21781 | /* 59833 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21782 | /* 59837 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21783 | /* 59841 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4122:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 21784 | /* 59841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i16), |
| 21785 | /* 59844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21786 | /* 59846 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21787 | /* 59848 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21788 | /* 59850 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21789 | /* 59853 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21790 | /* 59859 */ GIR_RootConstrainSelectedInstOperands, |
| 21791 | /* 59860 */ // GIR_Coverage, 1515, |
| 21792 | /* 59860 */ GIR_EraseRootFromParent_Done, |
| 21793 | /* 59861 */ // Label 1844: @59861 |
| 21794 | /* 59861 */ GIM_Reject, |
| 21795 | /* 59862 */ // Label 1836: @59862 |
| 21796 | /* 59862 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1845*/ GIMT_Encode4(59907), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1514 // |
| 21797 | /* 59869 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21798 | /* 59872 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21799 | /* 59875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21800 | /* 59879 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21801 | /* 59883 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21802 | /* 59887 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4122:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 21803 | /* 59887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i32), |
| 21804 | /* 59890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21805 | /* 59892 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21806 | /* 59894 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21807 | /* 59896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21808 | /* 59899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21809 | /* 59905 */ GIR_RootConstrainSelectedInstOperands, |
| 21810 | /* 59906 */ // GIR_Coverage, 1514, |
| 21811 | /* 59906 */ GIR_EraseRootFromParent_Done, |
| 21812 | /* 59907 */ // Label 1845: @59907 |
| 21813 | /* 59907 */ GIM_Reject, |
| 21814 | /* 59908 */ // Label 1837: @59908 |
| 21815 | /* 59908 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1846*/ GIMT_Encode4(59953), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1516 // |
| 21816 | /* 59915 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21817 | /* 59918 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21818 | /* 59921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21819 | /* 59925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21820 | /* 59929 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21821 | /* 59933 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4122:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 21822 | /* 59933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i32), |
| 21823 | /* 59936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21824 | /* 59938 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21825 | /* 59940 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21826 | /* 59942 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21827 | /* 59945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21828 | /* 59951 */ GIR_RootConstrainSelectedInstOperands, |
| 21829 | /* 59952 */ // GIR_Coverage, 1516, |
| 21830 | /* 59952 */ GIR_EraseRootFromParent_Done, |
| 21831 | /* 59953 */ // Label 1846: @59953 |
| 21832 | /* 59953 */ GIM_Reject, |
| 21833 | /* 59954 */ // Label 1838: @59954 |
| 21834 | /* 59954 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1847*/ GIMT_Encode4(59999), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1520 // |
| 21835 | /* 59961 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 21836 | /* 59964 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 21837 | /* 59967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21838 | /* 59971 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21839 | /* 59975 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21840 | /* 59979 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4122:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 21841 | /* 59979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i64), |
| 21842 | /* 59982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21843 | /* 59984 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21844 | /* 59986 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21845 | /* 59988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21846 | /* 59991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21847 | /* 59997 */ GIR_RootConstrainSelectedInstOperands, |
| 21848 | /* 59998 */ // GIR_Coverage, 1520, |
| 21849 | /* 59998 */ GIR_EraseRootFromParent_Done, |
| 21850 | /* 59999 */ // Label 1847: @59999 |
| 21851 | /* 59999 */ GIM_Reject, |
| 21852 | /* 60000 */ // Label 1839: @60000 |
| 21853 | /* 60000 */ GIM_Reject, |
| 21854 | /* 60001 */ // Label 1830: @60001 |
| 21855 | /* 60001 */ GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(60439), |
| 21856 | /* 60006 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu), |
| 21857 | /* 60011 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1857*/ GIMT_Encode4(60438), |
| 21858 | /* 60022 */ /*GILLT_s64*//*Label 1849*/ GIMT_Encode4(60070), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 21859 | /* 60042 */ /*GILLT_v8s8*//*Label 1850*/ GIMT_Encode4(60116), |
| 21860 | /* 60046 */ /*GILLT_v16s8*//*Label 1851*/ GIMT_Encode4(60162), |
| 21861 | /* 60050 */ /*GILLT_v4s16*//*Label 1852*/ GIMT_Encode4(60208), |
| 21862 | /* 60054 */ /*GILLT_v8s16*//*Label 1853*/ GIMT_Encode4(60254), |
| 21863 | /* 60058 */ /*GILLT_v2s32*//*Label 1854*/ GIMT_Encode4(60300), |
| 21864 | /* 60062 */ /*GILLT_v4s32*//*Label 1855*/ GIMT_Encode4(60346), |
| 21865 | /* 60066 */ /*GILLT_v2s64*//*Label 1856*/ GIMT_Encode4(60392), |
| 21866 | /* 60070 */ // Label 1849: @60070 |
| 21867 | /* 60070 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1858*/ GIMT_Encode4(60115), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1527 // |
| 21868 | /* 60077 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 21869 | /* 60080 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 21870 | /* 60083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21871 | /* 60087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21872 | /* 60091 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21873 | /* 60095 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4123:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 21874 | /* 60095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv1i64), |
| 21875 | /* 60098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21876 | /* 60100 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21877 | /* 60102 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21878 | /* 60104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21879 | /* 60107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21880 | /* 60113 */ GIR_RootConstrainSelectedInstOperands, |
| 21881 | /* 60114 */ // GIR_Coverage, 1527, |
| 21882 | /* 60114 */ GIR_EraseRootFromParent_Done, |
| 21883 | /* 60115 */ // Label 1858: @60115 |
| 21884 | /* 60115 */ GIM_Reject, |
| 21885 | /* 60116 */ // Label 1850: @60116 |
| 21886 | /* 60116 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1859*/ GIMT_Encode4(60161), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1525 // |
| 21887 | /* 60123 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 21888 | /* 60126 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 21889 | /* 60129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21890 | /* 60133 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21891 | /* 60137 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21892 | /* 60141 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4123:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 21893 | /* 60141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i8), |
| 21894 | /* 60144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21895 | /* 60146 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21896 | /* 60148 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21897 | /* 60150 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21898 | /* 60153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21899 | /* 60159 */ GIR_RootConstrainSelectedInstOperands, |
| 21900 | /* 60160 */ // GIR_Coverage, 1525, |
| 21901 | /* 60160 */ GIR_EraseRootFromParent_Done, |
| 21902 | /* 60161 */ // Label 1859: @60161 |
| 21903 | /* 60161 */ GIM_Reject, |
| 21904 | /* 60162 */ // Label 1851: @60162 |
| 21905 | /* 60162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1860*/ GIMT_Encode4(60207), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1526 // |
| 21906 | /* 60169 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 21907 | /* 60172 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 21908 | /* 60175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21909 | /* 60179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21910 | /* 60183 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21911 | /* 60187 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4123:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 21912 | /* 60187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv16i8), |
| 21913 | /* 60190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21914 | /* 60192 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21915 | /* 60194 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21916 | /* 60196 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21917 | /* 60199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21918 | /* 60205 */ GIR_RootConstrainSelectedInstOperands, |
| 21919 | /* 60206 */ // GIR_Coverage, 1526, |
| 21920 | /* 60206 */ GIR_EraseRootFromParent_Done, |
| 21921 | /* 60207 */ // Label 1860: @60207 |
| 21922 | /* 60207 */ GIM_Reject, |
| 21923 | /* 60208 */ // Label 1852: @60208 |
| 21924 | /* 60208 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1861*/ GIMT_Encode4(60253), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1521 // |
| 21925 | /* 60215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 21926 | /* 60218 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 21927 | /* 60221 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21928 | /* 60225 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21929 | /* 60229 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21930 | /* 60233 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4123:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 21931 | /* 60233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i16), |
| 21932 | /* 60236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21933 | /* 60238 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21934 | /* 60240 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21935 | /* 60242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21936 | /* 60245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21937 | /* 60251 */ GIR_RootConstrainSelectedInstOperands, |
| 21938 | /* 60252 */ // GIR_Coverage, 1521, |
| 21939 | /* 60252 */ GIR_EraseRootFromParent_Done, |
| 21940 | /* 60253 */ // Label 1861: @60253 |
| 21941 | /* 60253 */ GIM_Reject, |
| 21942 | /* 60254 */ // Label 1853: @60254 |
| 21943 | /* 60254 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1862*/ GIMT_Encode4(60299), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1523 // |
| 21944 | /* 60261 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 21945 | /* 60264 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 21946 | /* 60267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21947 | /* 60271 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21948 | /* 60275 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21949 | /* 60279 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4123:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 21950 | /* 60279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i16), |
| 21951 | /* 60282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21952 | /* 60284 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21953 | /* 60286 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21954 | /* 60288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21955 | /* 60291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21956 | /* 60297 */ GIR_RootConstrainSelectedInstOperands, |
| 21957 | /* 60298 */ // GIR_Coverage, 1523, |
| 21958 | /* 60298 */ GIR_EraseRootFromParent_Done, |
| 21959 | /* 60299 */ // Label 1862: @60299 |
| 21960 | /* 60299 */ GIM_Reject, |
| 21961 | /* 60300 */ // Label 1854: @60300 |
| 21962 | /* 60300 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1863*/ GIMT_Encode4(60345), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1522 // |
| 21963 | /* 60307 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 21964 | /* 60310 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 21965 | /* 60313 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21966 | /* 60317 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21967 | /* 60321 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 21968 | /* 60325 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4123:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 21969 | /* 60325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i32), |
| 21970 | /* 60328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21971 | /* 60330 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21972 | /* 60332 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21973 | /* 60334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21974 | /* 60337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21975 | /* 60343 */ GIR_RootConstrainSelectedInstOperands, |
| 21976 | /* 60344 */ // GIR_Coverage, 1522, |
| 21977 | /* 60344 */ GIR_EraseRootFromParent_Done, |
| 21978 | /* 60345 */ // Label 1863: @60345 |
| 21979 | /* 60345 */ GIM_Reject, |
| 21980 | /* 60346 */ // Label 1855: @60346 |
| 21981 | /* 60346 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1864*/ GIMT_Encode4(60391), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1524 // |
| 21982 | /* 60353 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 21983 | /* 60356 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 21984 | /* 60359 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21985 | /* 60363 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21986 | /* 60367 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 21987 | /* 60371 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4123:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 21988 | /* 60371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i32), |
| 21989 | /* 60374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 21990 | /* 60376 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 21991 | /* 60378 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 21992 | /* 60380 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 21993 | /* 60383 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 21994 | /* 60389 */ GIR_RootConstrainSelectedInstOperands, |
| 21995 | /* 60390 */ // GIR_Coverage, 1524, |
| 21996 | /* 60390 */ GIR_EraseRootFromParent_Done, |
| 21997 | /* 60391 */ // Label 1864: @60391 |
| 21998 | /* 60391 */ GIM_Reject, |
| 21999 | /* 60392 */ // Label 1856: @60392 |
| 22000 | /* 60392 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1865*/ GIMT_Encode4(60437), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1528 // |
| 22001 | /* 60399 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22002 | /* 60402 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22003 | /* 60405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22004 | /* 60409 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22005 | /* 60413 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22006 | /* 60417 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4123:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 22007 | /* 60417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i64), |
| 22008 | /* 60420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22009 | /* 60422 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22010 | /* 60424 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22011 | /* 60426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22012 | /* 60429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22013 | /* 60435 */ GIR_RootConstrainSelectedInstOperands, |
| 22014 | /* 60436 */ // GIR_Coverage, 1528, |
| 22015 | /* 60436 */ GIR_EraseRootFromParent_Done, |
| 22016 | /* 60437 */ // Label 1865: @60437 |
| 22017 | /* 60437 */ GIM_Reject, |
| 22018 | /* 60438 */ // Label 1857: @60438 |
| 22019 | /* 60438 */ GIM_Reject, |
| 22020 | /* 60439 */ // Label 1848: @60439 |
| 22021 | /* 60439 */ GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(60877), |
| 22022 | /* 60444 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts), |
| 22023 | /* 60449 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1875*/ GIMT_Encode4(60876), |
| 22024 | /* 60460 */ /*GILLT_s64*//*Label 1867*/ GIMT_Encode4(60508), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 22025 | /* 60480 */ /*GILLT_v8s8*//*Label 1868*/ GIMT_Encode4(60554), |
| 22026 | /* 60484 */ /*GILLT_v16s8*//*Label 1869*/ GIMT_Encode4(60600), |
| 22027 | /* 60488 */ /*GILLT_v4s16*//*Label 1870*/ GIMT_Encode4(60646), |
| 22028 | /* 60492 */ /*GILLT_v8s16*//*Label 1871*/ GIMT_Encode4(60692), |
| 22029 | /* 60496 */ /*GILLT_v2s32*//*Label 1872*/ GIMT_Encode4(60738), |
| 22030 | /* 60500 */ /*GILLT_v4s32*//*Label 1873*/ GIMT_Encode4(60784), |
| 22031 | /* 60504 */ /*GILLT_v2s64*//*Label 1874*/ GIMT_Encode4(60830), |
| 22032 | /* 60508 */ // Label 1867: @60508 |
| 22033 | /* 60508 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1876*/ GIMT_Encode4(60553), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1554 // |
| 22034 | /* 60515 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22035 | /* 60518 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 22036 | /* 60521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22037 | /* 60525 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22038 | /* 60529 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22039 | /* 60533 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4113:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 22040 | /* 60533 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv1i64), |
| 22041 | /* 60536 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22042 | /* 60538 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22043 | /* 60540 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22044 | /* 60542 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22045 | /* 60545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22046 | /* 60551 */ GIR_RootConstrainSelectedInstOperands, |
| 22047 | /* 60552 */ // GIR_Coverage, 1554, |
| 22048 | /* 60552 */ GIR_EraseRootFromParent_Done, |
| 22049 | /* 60553 */ // Label 1876: @60553 |
| 22050 | /* 60553 */ GIM_Reject, |
| 22051 | /* 60554 */ // Label 1868: @60554 |
| 22052 | /* 60554 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1877*/ GIMT_Encode4(60599), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1552 // |
| 22053 | /* 60561 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 22054 | /* 60564 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 22055 | /* 60567 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22056 | /* 60571 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22057 | /* 60575 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22058 | /* 60579 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4113:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 22059 | /* 60579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i8), |
| 22060 | /* 60582 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22061 | /* 60584 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22062 | /* 60586 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22063 | /* 60588 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22064 | /* 60591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22065 | /* 60597 */ GIR_RootConstrainSelectedInstOperands, |
| 22066 | /* 60598 */ // GIR_Coverage, 1552, |
| 22067 | /* 60598 */ GIR_EraseRootFromParent_Done, |
| 22068 | /* 60599 */ // Label 1877: @60599 |
| 22069 | /* 60599 */ GIM_Reject, |
| 22070 | /* 60600 */ // Label 1869: @60600 |
| 22071 | /* 60600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1878*/ GIMT_Encode4(60645), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1553 // |
| 22072 | /* 60607 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22073 | /* 60610 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22074 | /* 60613 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22075 | /* 60617 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22076 | /* 60621 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22077 | /* 60625 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4113:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 22078 | /* 60625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv16i8), |
| 22079 | /* 60628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22080 | /* 60630 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22081 | /* 60632 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22082 | /* 60634 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22083 | /* 60637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22084 | /* 60643 */ GIR_RootConstrainSelectedInstOperands, |
| 22085 | /* 60644 */ // GIR_Coverage, 1553, |
| 22086 | /* 60644 */ GIR_EraseRootFromParent_Done, |
| 22087 | /* 60645 */ // Label 1878: @60645 |
| 22088 | /* 60645 */ GIM_Reject, |
| 22089 | /* 60646 */ // Label 1870: @60646 |
| 22090 | /* 60646 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1879*/ GIMT_Encode4(60691), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1548 // |
| 22091 | /* 60653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22092 | /* 60656 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22093 | /* 60659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22094 | /* 60663 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22095 | /* 60667 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22096 | /* 60671 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4113:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 22097 | /* 60671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i16), |
| 22098 | /* 60674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22099 | /* 60676 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22100 | /* 60678 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22101 | /* 60680 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22102 | /* 60683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22103 | /* 60689 */ GIR_RootConstrainSelectedInstOperands, |
| 22104 | /* 60690 */ // GIR_Coverage, 1548, |
| 22105 | /* 60690 */ GIR_EraseRootFromParent_Done, |
| 22106 | /* 60691 */ // Label 1879: @60691 |
| 22107 | /* 60691 */ GIM_Reject, |
| 22108 | /* 60692 */ // Label 1871: @60692 |
| 22109 | /* 60692 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1880*/ GIMT_Encode4(60737), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1550 // |
| 22110 | /* 60699 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22111 | /* 60702 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22112 | /* 60705 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22113 | /* 60709 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22114 | /* 60713 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22115 | /* 60717 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4113:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 22116 | /* 60717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i16), |
| 22117 | /* 60720 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22118 | /* 60722 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22119 | /* 60724 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22120 | /* 60726 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22121 | /* 60729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22122 | /* 60735 */ GIR_RootConstrainSelectedInstOperands, |
| 22123 | /* 60736 */ // GIR_Coverage, 1550, |
| 22124 | /* 60736 */ GIR_EraseRootFromParent_Done, |
| 22125 | /* 60737 */ // Label 1880: @60737 |
| 22126 | /* 60737 */ GIM_Reject, |
| 22127 | /* 60738 */ // Label 1872: @60738 |
| 22128 | /* 60738 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1881*/ GIMT_Encode4(60783), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1549 // |
| 22129 | /* 60745 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22130 | /* 60748 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22131 | /* 60751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22132 | /* 60755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22133 | /* 60759 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22134 | /* 60763 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4113:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 22135 | /* 60763 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i32), |
| 22136 | /* 60766 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22137 | /* 60768 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22138 | /* 60770 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22139 | /* 60772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22140 | /* 60775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22141 | /* 60781 */ GIR_RootConstrainSelectedInstOperands, |
| 22142 | /* 60782 */ // GIR_Coverage, 1549, |
| 22143 | /* 60782 */ GIR_EraseRootFromParent_Done, |
| 22144 | /* 60783 */ // Label 1881: @60783 |
| 22145 | /* 60783 */ GIM_Reject, |
| 22146 | /* 60784 */ // Label 1873: @60784 |
| 22147 | /* 60784 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1882*/ GIMT_Encode4(60829), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1551 // |
| 22148 | /* 60791 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22149 | /* 60794 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22150 | /* 60797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22151 | /* 60801 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22152 | /* 60805 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22153 | /* 60809 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4113:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 22154 | /* 60809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i32), |
| 22155 | /* 60812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22156 | /* 60814 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22157 | /* 60816 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22158 | /* 60818 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22159 | /* 60821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22160 | /* 60827 */ GIR_RootConstrainSelectedInstOperands, |
| 22161 | /* 60828 */ // GIR_Coverage, 1551, |
| 22162 | /* 60828 */ GIR_EraseRootFromParent_Done, |
| 22163 | /* 60829 */ // Label 1882: @60829 |
| 22164 | /* 60829 */ GIM_Reject, |
| 22165 | /* 60830 */ // Label 1874: @60830 |
| 22166 | /* 60830 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1883*/ GIMT_Encode4(60875), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1555 // |
| 22167 | /* 60837 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22168 | /* 60840 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22169 | /* 60843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22170 | /* 60847 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22171 | /* 60851 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22172 | /* 60855 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4113:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 22173 | /* 60855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i64), |
| 22174 | /* 60858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22175 | /* 60860 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22176 | /* 60862 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22177 | /* 60864 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22178 | /* 60867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22179 | /* 60873 */ GIR_RootConstrainSelectedInstOperands, |
| 22180 | /* 60874 */ // GIR_Coverage, 1555, |
| 22181 | /* 60874 */ GIR_EraseRootFromParent_Done, |
| 22182 | /* 60875 */ // Label 1883: @60875 |
| 22183 | /* 60875 */ GIM_Reject, |
| 22184 | /* 60876 */ // Label 1875: @60876 |
| 22185 | /* 60876 */ GIM_Reject, |
| 22186 | /* 60877 */ // Label 1866: @60877 |
| 22187 | /* 60877 */ GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(61315), |
| 22188 | /* 60882 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu), |
| 22189 | /* 60887 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1893*/ GIMT_Encode4(61314), |
| 22190 | /* 60898 */ /*GILLT_s64*//*Label 1885*/ GIMT_Encode4(60946), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 22191 | /* 60918 */ /*GILLT_v8s8*//*Label 1886*/ GIMT_Encode4(60992), |
| 22192 | /* 60922 */ /*GILLT_v16s8*//*Label 1887*/ GIMT_Encode4(61038), |
| 22193 | /* 60926 */ /*GILLT_v4s16*//*Label 1888*/ GIMT_Encode4(61084), |
| 22194 | /* 60930 */ /*GILLT_v8s16*//*Label 1889*/ GIMT_Encode4(61130), |
| 22195 | /* 60934 */ /*GILLT_v2s32*//*Label 1890*/ GIMT_Encode4(61176), |
| 22196 | /* 60938 */ /*GILLT_v4s32*//*Label 1891*/ GIMT_Encode4(61222), |
| 22197 | /* 60942 */ /*GILLT_v2s64*//*Label 1892*/ GIMT_Encode4(61268), |
| 22198 | /* 60946 */ // Label 1885: @60946 |
| 22199 | /* 60946 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1894*/ GIMT_Encode4(60991), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1562 // |
| 22200 | /* 60953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22201 | /* 60956 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 22202 | /* 60959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22203 | /* 60963 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22204 | /* 60967 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22205 | /* 60971 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4115:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 22206 | /* 60971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv1i64), |
| 22207 | /* 60974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22208 | /* 60976 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22209 | /* 60978 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22210 | /* 60980 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22211 | /* 60983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22212 | /* 60989 */ GIR_RootConstrainSelectedInstOperands, |
| 22213 | /* 60990 */ // GIR_Coverage, 1562, |
| 22214 | /* 60990 */ GIR_EraseRootFromParent_Done, |
| 22215 | /* 60991 */ // Label 1894: @60991 |
| 22216 | /* 60991 */ GIM_Reject, |
| 22217 | /* 60992 */ // Label 1886: @60992 |
| 22218 | /* 60992 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1895*/ GIMT_Encode4(61037), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1560 // |
| 22219 | /* 60999 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 22220 | /* 61002 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 22221 | /* 61005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22222 | /* 61009 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22223 | /* 61013 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22224 | /* 61017 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4115:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 22225 | /* 61017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i8), |
| 22226 | /* 61020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22227 | /* 61022 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22228 | /* 61024 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22229 | /* 61026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22230 | /* 61029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22231 | /* 61035 */ GIR_RootConstrainSelectedInstOperands, |
| 22232 | /* 61036 */ // GIR_Coverage, 1560, |
| 22233 | /* 61036 */ GIR_EraseRootFromParent_Done, |
| 22234 | /* 61037 */ // Label 1895: @61037 |
| 22235 | /* 61037 */ GIM_Reject, |
| 22236 | /* 61038 */ // Label 1887: @61038 |
| 22237 | /* 61038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1896*/ GIMT_Encode4(61083), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1561 // |
| 22238 | /* 61045 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22239 | /* 61048 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22240 | /* 61051 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22241 | /* 61055 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22242 | /* 61059 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22243 | /* 61063 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4115:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 22244 | /* 61063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv16i8), |
| 22245 | /* 61066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22246 | /* 61068 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22247 | /* 61070 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22248 | /* 61072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22249 | /* 61075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22250 | /* 61081 */ GIR_RootConstrainSelectedInstOperands, |
| 22251 | /* 61082 */ // GIR_Coverage, 1561, |
| 22252 | /* 61082 */ GIR_EraseRootFromParent_Done, |
| 22253 | /* 61083 */ // Label 1896: @61083 |
| 22254 | /* 61083 */ GIM_Reject, |
| 22255 | /* 61084 */ // Label 1888: @61084 |
| 22256 | /* 61084 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1897*/ GIMT_Encode4(61129), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1556 // |
| 22257 | /* 61091 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22258 | /* 61094 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22259 | /* 61097 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22260 | /* 61101 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22261 | /* 61105 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22262 | /* 61109 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4115:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 22263 | /* 61109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i16), |
| 22264 | /* 61112 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22265 | /* 61114 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22266 | /* 61116 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22267 | /* 61118 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22268 | /* 61121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22269 | /* 61127 */ GIR_RootConstrainSelectedInstOperands, |
| 22270 | /* 61128 */ // GIR_Coverage, 1556, |
| 22271 | /* 61128 */ GIR_EraseRootFromParent_Done, |
| 22272 | /* 61129 */ // Label 1897: @61129 |
| 22273 | /* 61129 */ GIM_Reject, |
| 22274 | /* 61130 */ // Label 1889: @61130 |
| 22275 | /* 61130 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1898*/ GIMT_Encode4(61175), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1558 // |
| 22276 | /* 61137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22277 | /* 61140 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22278 | /* 61143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22279 | /* 61147 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22280 | /* 61151 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22281 | /* 61155 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4115:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 22282 | /* 61155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i16), |
| 22283 | /* 61158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22284 | /* 61160 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22285 | /* 61162 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22286 | /* 61164 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22287 | /* 61167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22288 | /* 61173 */ GIR_RootConstrainSelectedInstOperands, |
| 22289 | /* 61174 */ // GIR_Coverage, 1558, |
| 22290 | /* 61174 */ GIR_EraseRootFromParent_Done, |
| 22291 | /* 61175 */ // Label 1898: @61175 |
| 22292 | /* 61175 */ GIM_Reject, |
| 22293 | /* 61176 */ // Label 1890: @61176 |
| 22294 | /* 61176 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1899*/ GIMT_Encode4(61221), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1557 // |
| 22295 | /* 61183 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22296 | /* 61186 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22297 | /* 61189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22298 | /* 61193 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22299 | /* 61197 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22300 | /* 61201 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4115:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 22301 | /* 61201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i32), |
| 22302 | /* 61204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22303 | /* 61206 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22304 | /* 61208 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22305 | /* 61210 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22306 | /* 61213 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22307 | /* 61219 */ GIR_RootConstrainSelectedInstOperands, |
| 22308 | /* 61220 */ // GIR_Coverage, 1557, |
| 22309 | /* 61220 */ GIR_EraseRootFromParent_Done, |
| 22310 | /* 61221 */ // Label 1899: @61221 |
| 22311 | /* 61221 */ GIM_Reject, |
| 22312 | /* 61222 */ // Label 1891: @61222 |
| 22313 | /* 61222 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1900*/ GIMT_Encode4(61267), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1559 // |
| 22314 | /* 61229 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22315 | /* 61232 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22316 | /* 61235 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22317 | /* 61239 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22318 | /* 61243 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22319 | /* 61247 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4115:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 22320 | /* 61247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i32), |
| 22321 | /* 61250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22322 | /* 61252 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22323 | /* 61254 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22324 | /* 61256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22325 | /* 61259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22326 | /* 61265 */ GIR_RootConstrainSelectedInstOperands, |
| 22327 | /* 61266 */ // GIR_Coverage, 1559, |
| 22328 | /* 61266 */ GIR_EraseRootFromParent_Done, |
| 22329 | /* 61267 */ // Label 1900: @61267 |
| 22330 | /* 61267 */ GIM_Reject, |
| 22331 | /* 61268 */ // Label 1892: @61268 |
| 22332 | /* 61268 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1901*/ GIMT_Encode4(61313), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1563 // |
| 22333 | /* 61275 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22334 | /* 61278 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22335 | /* 61281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22336 | /* 61285 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22337 | /* 61289 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22338 | /* 61293 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4115:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 22339 | /* 61293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i64), |
| 22340 | /* 61296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22341 | /* 61298 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22342 | /* 61300 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22343 | /* 61302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22344 | /* 61305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22345 | /* 61311 */ GIR_RootConstrainSelectedInstOperands, |
| 22346 | /* 61312 */ // GIR_Coverage, 1563, |
| 22347 | /* 61312 */ GIR_EraseRootFromParent_Done, |
| 22348 | /* 61313 */ // Label 1901: @61313 |
| 22349 | /* 61313 */ GIM_Reject, |
| 22350 | /* 61314 */ // Label 1893: @61314 |
| 22351 | /* 61314 */ GIM_Reject, |
| 22352 | /* 61315 */ // Label 1884: @61315 |
| 22353 | /* 61315 */ GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(61753), |
| 22354 | /* 61320 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts), |
| 22355 | /* 61325 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1911*/ GIMT_Encode4(61752), |
| 22356 | /* 61336 */ /*GILLT_s64*//*Label 1903*/ GIMT_Encode4(61384), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 22357 | /* 61356 */ /*GILLT_v8s8*//*Label 1904*/ GIMT_Encode4(61430), |
| 22358 | /* 61360 */ /*GILLT_v16s8*//*Label 1905*/ GIMT_Encode4(61476), |
| 22359 | /* 61364 */ /*GILLT_v4s16*//*Label 1906*/ GIMT_Encode4(61522), |
| 22360 | /* 61368 */ /*GILLT_v8s16*//*Label 1907*/ GIMT_Encode4(61568), |
| 22361 | /* 61372 */ /*GILLT_v2s32*//*Label 1908*/ GIMT_Encode4(61614), |
| 22362 | /* 61376 */ /*GILLT_v4s32*//*Label 1909*/ GIMT_Encode4(61660), |
| 22363 | /* 61380 */ /*GILLT_v2s64*//*Label 1910*/ GIMT_Encode4(61706), |
| 22364 | /* 61384 */ // Label 1903: @61384 |
| 22365 | /* 61384 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1912*/ GIMT_Encode4(61429), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1603 // |
| 22366 | /* 61391 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22367 | /* 61394 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 22368 | /* 61397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22369 | /* 61401 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22370 | /* 61405 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22371 | /* 61409 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4108:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 22372 | /* 61409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv1i64), |
| 22373 | /* 61412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22374 | /* 61414 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22375 | /* 61416 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22376 | /* 61418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22377 | /* 61421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22378 | /* 61427 */ GIR_RootConstrainSelectedInstOperands, |
| 22379 | /* 61428 */ // GIR_Coverage, 1603, |
| 22380 | /* 61428 */ GIR_EraseRootFromParent_Done, |
| 22381 | /* 61429 */ // Label 1912: @61429 |
| 22382 | /* 61429 */ GIM_Reject, |
| 22383 | /* 61430 */ // Label 1904: @61430 |
| 22384 | /* 61430 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1913*/ GIMT_Encode4(61475), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1601 // |
| 22385 | /* 61437 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 22386 | /* 61440 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 22387 | /* 61443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22388 | /* 61447 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22389 | /* 61451 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22390 | /* 61455 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4108:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 22391 | /* 61455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i8), |
| 22392 | /* 61458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22393 | /* 61460 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22394 | /* 61462 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22395 | /* 61464 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22396 | /* 61467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22397 | /* 61473 */ GIR_RootConstrainSelectedInstOperands, |
| 22398 | /* 61474 */ // GIR_Coverage, 1601, |
| 22399 | /* 61474 */ GIR_EraseRootFromParent_Done, |
| 22400 | /* 61475 */ // Label 1913: @61475 |
| 22401 | /* 61475 */ GIM_Reject, |
| 22402 | /* 61476 */ // Label 1905: @61476 |
| 22403 | /* 61476 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1914*/ GIMT_Encode4(61521), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1602 // |
| 22404 | /* 61483 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22405 | /* 61486 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22406 | /* 61489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22407 | /* 61493 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22408 | /* 61497 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22409 | /* 61501 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4108:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 22410 | /* 61501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv16i8), |
| 22411 | /* 61504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22412 | /* 61506 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22413 | /* 61508 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22414 | /* 61510 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22415 | /* 61513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22416 | /* 61519 */ GIR_RootConstrainSelectedInstOperands, |
| 22417 | /* 61520 */ // GIR_Coverage, 1602, |
| 22418 | /* 61520 */ GIR_EraseRootFromParent_Done, |
| 22419 | /* 61521 */ // Label 1914: @61521 |
| 22420 | /* 61521 */ GIM_Reject, |
| 22421 | /* 61522 */ // Label 1906: @61522 |
| 22422 | /* 61522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1915*/ GIMT_Encode4(61567), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1597 // |
| 22423 | /* 61529 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22424 | /* 61532 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22425 | /* 61535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22426 | /* 61539 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22427 | /* 61543 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22428 | /* 61547 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4108:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 22429 | /* 61547 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i16), |
| 22430 | /* 61550 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22431 | /* 61552 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22432 | /* 61554 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22433 | /* 61556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22434 | /* 61559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22435 | /* 61565 */ GIR_RootConstrainSelectedInstOperands, |
| 22436 | /* 61566 */ // GIR_Coverage, 1597, |
| 22437 | /* 61566 */ GIR_EraseRootFromParent_Done, |
| 22438 | /* 61567 */ // Label 1915: @61567 |
| 22439 | /* 61567 */ GIM_Reject, |
| 22440 | /* 61568 */ // Label 1907: @61568 |
| 22441 | /* 61568 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1916*/ GIMT_Encode4(61613), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1599 // |
| 22442 | /* 61575 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22443 | /* 61578 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22444 | /* 61581 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22445 | /* 61585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22446 | /* 61589 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22447 | /* 61593 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4108:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 22448 | /* 61593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i16), |
| 22449 | /* 61596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22450 | /* 61598 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22451 | /* 61600 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22452 | /* 61602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22453 | /* 61605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22454 | /* 61611 */ GIR_RootConstrainSelectedInstOperands, |
| 22455 | /* 61612 */ // GIR_Coverage, 1599, |
| 22456 | /* 61612 */ GIR_EraseRootFromParent_Done, |
| 22457 | /* 61613 */ // Label 1916: @61613 |
| 22458 | /* 61613 */ GIM_Reject, |
| 22459 | /* 61614 */ // Label 1908: @61614 |
| 22460 | /* 61614 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1917*/ GIMT_Encode4(61659), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1598 // |
| 22461 | /* 61621 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22462 | /* 61624 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22463 | /* 61627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22464 | /* 61631 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22465 | /* 61635 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22466 | /* 61639 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4108:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 22467 | /* 61639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i32), |
| 22468 | /* 61642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22469 | /* 61644 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22470 | /* 61646 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22471 | /* 61648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22472 | /* 61651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22473 | /* 61657 */ GIR_RootConstrainSelectedInstOperands, |
| 22474 | /* 61658 */ // GIR_Coverage, 1598, |
| 22475 | /* 61658 */ GIR_EraseRootFromParent_Done, |
| 22476 | /* 61659 */ // Label 1917: @61659 |
| 22477 | /* 61659 */ GIM_Reject, |
| 22478 | /* 61660 */ // Label 1909: @61660 |
| 22479 | /* 61660 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1918*/ GIMT_Encode4(61705), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1600 // |
| 22480 | /* 61667 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22481 | /* 61670 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22482 | /* 61673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22483 | /* 61677 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22484 | /* 61681 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22485 | /* 61685 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4108:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 22486 | /* 61685 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i32), |
| 22487 | /* 61688 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22488 | /* 61690 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22489 | /* 61692 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22490 | /* 61694 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22491 | /* 61697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22492 | /* 61703 */ GIR_RootConstrainSelectedInstOperands, |
| 22493 | /* 61704 */ // GIR_Coverage, 1600, |
| 22494 | /* 61704 */ GIR_EraseRootFromParent_Done, |
| 22495 | /* 61705 */ // Label 1918: @61705 |
| 22496 | /* 61705 */ GIM_Reject, |
| 22497 | /* 61706 */ // Label 1910: @61706 |
| 22498 | /* 61706 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1919*/ GIMT_Encode4(61751), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1604 // |
| 22499 | /* 61713 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22500 | /* 61716 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22501 | /* 61719 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22502 | /* 61723 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22503 | /* 61727 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22504 | /* 61731 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4108:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 22505 | /* 61731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i64), |
| 22506 | /* 61734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22507 | /* 61736 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22508 | /* 61738 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22509 | /* 61740 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22510 | /* 61743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22511 | /* 61749 */ GIR_RootConstrainSelectedInstOperands, |
| 22512 | /* 61750 */ // GIR_Coverage, 1604, |
| 22513 | /* 61750 */ GIR_EraseRootFromParent_Done, |
| 22514 | /* 61751 */ // Label 1919: @61751 |
| 22515 | /* 61751 */ GIM_Reject, |
| 22516 | /* 61752 */ // Label 1911: @61752 |
| 22517 | /* 61752 */ GIM_Reject, |
| 22518 | /* 61753 */ // Label 1902: @61753 |
| 22519 | /* 61753 */ GIM_Try, /*On fail goto*//*Label 1920*/ GIMT_Encode4(62191), |
| 22520 | /* 61758 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu), |
| 22521 | /* 61763 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1929*/ GIMT_Encode4(62190), |
| 22522 | /* 61774 */ /*GILLT_s64*//*Label 1921*/ GIMT_Encode4(61822), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 22523 | /* 61794 */ /*GILLT_v8s8*//*Label 1922*/ GIMT_Encode4(61868), |
| 22524 | /* 61798 */ /*GILLT_v16s8*//*Label 1923*/ GIMT_Encode4(61914), |
| 22525 | /* 61802 */ /*GILLT_v4s16*//*Label 1924*/ GIMT_Encode4(61960), |
| 22526 | /* 61806 */ /*GILLT_v8s16*//*Label 1925*/ GIMT_Encode4(62006), |
| 22527 | /* 61810 */ /*GILLT_v2s32*//*Label 1926*/ GIMT_Encode4(62052), |
| 22528 | /* 61814 */ /*GILLT_v4s32*//*Label 1927*/ GIMT_Encode4(62098), |
| 22529 | /* 61818 */ /*GILLT_v2s64*//*Label 1928*/ GIMT_Encode4(62144), |
| 22530 | /* 61822 */ // Label 1921: @61822 |
| 22531 | /* 61822 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1930*/ GIMT_Encode4(61867), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1611 // |
| 22532 | /* 61829 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 22533 | /* 61832 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 22534 | /* 61835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22535 | /* 61839 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22536 | /* 61843 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22537 | /* 61847 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4109:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) |
| 22538 | /* 61847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv1i64), |
| 22539 | /* 61850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22540 | /* 61852 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22541 | /* 61854 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22542 | /* 61856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22543 | /* 61859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22544 | /* 61865 */ GIR_RootConstrainSelectedInstOperands, |
| 22545 | /* 61866 */ // GIR_Coverage, 1611, |
| 22546 | /* 61866 */ GIR_EraseRootFromParent_Done, |
| 22547 | /* 61867 */ // Label 1930: @61867 |
| 22548 | /* 61867 */ GIM_Reject, |
| 22549 | /* 61868 */ // Label 1922: @61868 |
| 22550 | /* 61868 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1931*/ GIMT_Encode4(61913), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1609 // |
| 22551 | /* 61875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 22552 | /* 61878 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 22553 | /* 61881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22554 | /* 61885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22555 | /* 61889 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22556 | /* 61893 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4109:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) |
| 22557 | /* 61893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i8), |
| 22558 | /* 61896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22559 | /* 61898 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22560 | /* 61900 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22561 | /* 61902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22562 | /* 61905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22563 | /* 61911 */ GIR_RootConstrainSelectedInstOperands, |
| 22564 | /* 61912 */ // GIR_Coverage, 1609, |
| 22565 | /* 61912 */ GIR_EraseRootFromParent_Done, |
| 22566 | /* 61913 */ // Label 1931: @61913 |
| 22567 | /* 61913 */ GIM_Reject, |
| 22568 | /* 61914 */ // Label 1923: @61914 |
| 22569 | /* 61914 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1932*/ GIMT_Encode4(61959), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1610 // |
| 22570 | /* 61921 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22571 | /* 61924 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22572 | /* 61927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22573 | /* 61931 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22574 | /* 61935 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22575 | /* 61939 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4109:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) |
| 22576 | /* 61939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv16i8), |
| 22577 | /* 61942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22578 | /* 61944 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22579 | /* 61946 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22580 | /* 61948 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22581 | /* 61951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22582 | /* 61957 */ GIR_RootConstrainSelectedInstOperands, |
| 22583 | /* 61958 */ // GIR_Coverage, 1610, |
| 22584 | /* 61958 */ GIR_EraseRootFromParent_Done, |
| 22585 | /* 61959 */ // Label 1932: @61959 |
| 22586 | /* 61959 */ GIM_Reject, |
| 22587 | /* 61960 */ // Label 1924: @61960 |
| 22588 | /* 61960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1933*/ GIMT_Encode4(62005), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1605 // |
| 22589 | /* 61967 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 22590 | /* 61970 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 22591 | /* 61973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22592 | /* 61977 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22593 | /* 61981 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22594 | /* 61985 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4109:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) |
| 22595 | /* 61985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i16), |
| 22596 | /* 61988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22597 | /* 61990 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22598 | /* 61992 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22599 | /* 61994 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22600 | /* 61997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22601 | /* 62003 */ GIR_RootConstrainSelectedInstOperands, |
| 22602 | /* 62004 */ // GIR_Coverage, 1605, |
| 22603 | /* 62004 */ GIR_EraseRootFromParent_Done, |
| 22604 | /* 62005 */ // Label 1933: @62005 |
| 22605 | /* 62005 */ GIM_Reject, |
| 22606 | /* 62006 */ // Label 1925: @62006 |
| 22607 | /* 62006 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1934*/ GIMT_Encode4(62051), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1607 // |
| 22608 | /* 62013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 22609 | /* 62016 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 22610 | /* 62019 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22611 | /* 62023 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22612 | /* 62027 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22613 | /* 62031 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4109:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) |
| 22614 | /* 62031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i16), |
| 22615 | /* 62034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22616 | /* 62036 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22617 | /* 62038 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22618 | /* 62040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22619 | /* 62043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22620 | /* 62049 */ GIR_RootConstrainSelectedInstOperands, |
| 22621 | /* 62050 */ // GIR_Coverage, 1607, |
| 22622 | /* 62050 */ GIR_EraseRootFromParent_Done, |
| 22623 | /* 62051 */ // Label 1934: @62051 |
| 22624 | /* 62051 */ GIM_Reject, |
| 22625 | /* 62052 */ // Label 1926: @62052 |
| 22626 | /* 62052 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1935*/ GIMT_Encode4(62097), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1606 // |
| 22627 | /* 62059 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 22628 | /* 62062 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 22629 | /* 62065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22630 | /* 62069 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22631 | /* 62073 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 22632 | /* 62077 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4109:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) |
| 22633 | /* 62077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i32), |
| 22634 | /* 62080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22635 | /* 62082 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22636 | /* 62084 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22637 | /* 62086 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22638 | /* 62089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22639 | /* 62095 */ GIR_RootConstrainSelectedInstOperands, |
| 22640 | /* 62096 */ // GIR_Coverage, 1606, |
| 22641 | /* 62096 */ GIR_EraseRootFromParent_Done, |
| 22642 | /* 62097 */ // Label 1935: @62097 |
| 22643 | /* 62097 */ GIM_Reject, |
| 22644 | /* 62098 */ // Label 1927: @62098 |
| 22645 | /* 62098 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1936*/ GIMT_Encode4(62143), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1608 // |
| 22646 | /* 62105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22647 | /* 62108 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22648 | /* 62111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22649 | /* 62115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22650 | /* 62119 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22651 | /* 62123 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4109:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) |
| 22652 | /* 62123 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i32), |
| 22653 | /* 62126 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22654 | /* 62128 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22655 | /* 62130 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22656 | /* 62132 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22657 | /* 62135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22658 | /* 62141 */ GIR_RootConstrainSelectedInstOperands, |
| 22659 | /* 62142 */ // GIR_Coverage, 1608, |
| 22660 | /* 62142 */ GIR_EraseRootFromParent_Done, |
| 22661 | /* 62143 */ // Label 1936: @62143 |
| 22662 | /* 62143 */ GIM_Reject, |
| 22663 | /* 62144 */ // Label 1928: @62144 |
| 22664 | /* 62144 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1937*/ GIMT_Encode4(62189), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1612 // |
| 22665 | /* 62151 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 22666 | /* 62154 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 22667 | /* 62157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22668 | /* 62161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22669 | /* 62165 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22670 | /* 62169 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4109:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) |
| 22671 | /* 62169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i64), |
| 22672 | /* 62172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22673 | /* 62174 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 22674 | /* 62176 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 22675 | /* 62178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22676 | /* 62181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22677 | /* 62187 */ GIR_RootConstrainSelectedInstOperands, |
| 22678 | /* 62188 */ // GIR_Coverage, 1612, |
| 22679 | /* 62188 */ GIR_EraseRootFromParent_Done, |
| 22680 | /* 62189 */ // Label 1937: @62189 |
| 22681 | /* 62189 */ GIM_Reject, |
| 22682 | /* 62190 */ // Label 1929: @62190 |
| 22683 | /* 62190 */ GIM_Reject, |
| 22684 | /* 62191 */ // Label 1920: @62191 |
| 22685 | /* 62191 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1938*/ GIMT_Encode4(62235), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1901 // |
| 22686 | /* 62198 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesd), |
| 22687 | /* 62203 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22688 | /* 62206 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22689 | /* 62209 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22690 | /* 62212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22691 | /* 62216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22692 | /* 62220 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22693 | /* 62224 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4010:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESD:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) |
| 22694 | /* 62224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESD), |
| 22695 | /* 62227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22696 | /* 62229 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22697 | /* 62231 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22698 | /* 62233 */ GIR_RootConstrainSelectedInstOperands, |
| 22699 | /* 62234 */ // GIR_Coverage, 1901, |
| 22700 | /* 62234 */ GIR_EraseRootFromParent_Done, |
| 22701 | /* 62235 */ // Label 1938: @62235 |
| 22702 | /* 62235 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1939*/ GIMT_Encode4(62279), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1902 // |
| 22703 | /* 62242 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aese), |
| 22704 | /* 62247 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8, |
| 22705 | /* 62250 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 22706 | /* 62253 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 22707 | /* 62256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22708 | /* 62260 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22709 | /* 62264 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22710 | /* 62268 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4011:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESE:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) |
| 22711 | /* 62268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESE), |
| 22712 | /* 62271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22713 | /* 62273 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22714 | /* 62275 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22715 | /* 62277 */ GIR_RootConstrainSelectedInstOperands, |
| 22716 | /* 62278 */ // GIR_Coverage, 1902, |
| 22717 | /* 62278 */ GIR_EraseRootFromParent_Done, |
| 22718 | /* 62279 */ // Label 1939: @62279 |
| 22719 | /* 62279 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1940*/ GIMT_Encode4(62323), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1905 // |
| 22720 | /* 62286 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su1), |
| 22721 | /* 62291 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22722 | /* 62294 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22723 | /* 62297 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22724 | /* 62300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22725 | /* 62304 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22726 | /* 62308 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22727 | /* 62312 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4024:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) |
| 22728 | /* 62312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU1), |
| 22729 | /* 62315 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22730 | /* 62317 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22731 | /* 62319 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22732 | /* 62321 */ GIR_RootConstrainSelectedInstOperands, |
| 22733 | /* 62322 */ // GIR_Coverage, 1905, |
| 22734 | /* 62322 */ GIR_EraseRootFromParent_Done, |
| 22735 | /* 62323 */ // Label 1940: @62323 |
| 22736 | /* 62323 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1941*/ GIMT_Encode4(62367), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1906 // |
| 22737 | /* 62330 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su0), |
| 22738 | /* 62335 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 22739 | /* 62338 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 22740 | /* 62341 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 22741 | /* 62344 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22742 | /* 62348 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22743 | /* 62352 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 22744 | /* 62356 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4027:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) |
| 22745 | /* 62356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU0), |
| 22746 | /* 62359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 22747 | /* 62361 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 22748 | /* 62363 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm |
| 22749 | /* 62365 */ GIR_RootConstrainSelectedInstOperands, |
| 22750 | /* 62366 */ // GIR_Coverage, 1906, |
| 22751 | /* 62366 */ GIR_EraseRootFromParent_Done, |
| 22752 | /* 62367 */ // Label 1941: @62367 |
| 22753 | /* 62367 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1942*/ GIMT_Encode4(62420), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1915 // |
| 22754 | /* 62374 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqrshr), |
| 22755 | /* 62379 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22756 | /* 62382 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22757 | /* 62385 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22758 | /* 62388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22759 | /* 62392 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22760 | /* 62396 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22761 | /* 62400 */ // (intrinsic_wo_chain:{ *:[i32] } 3860:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_SQRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) |
| 22762 | /* 62400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQRSHR), |
| 22763 | /* 62403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22764 | /* 62405 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 22765 | /* 62407 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22766 | /* 62409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22767 | /* 62412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22768 | /* 62418 */ GIR_RootConstrainSelectedInstOperands, |
| 22769 | /* 62419 */ // GIR_Coverage, 1915, |
| 22770 | /* 62419 */ GIR_EraseRootFromParent_Done, |
| 22771 | /* 62420 */ // Label 1942: @62420 |
| 22772 | /* 62420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1943*/ GIMT_Encode4(62473), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1916 // |
| 22773 | /* 62427 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqrshl), |
| 22774 | /* 62432 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22775 | /* 62435 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22776 | /* 62438 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22777 | /* 62441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22778 | /* 62445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22779 | /* 62449 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 22780 | /* 62453 */ // (intrinsic_wo_chain:{ *:[i32] } 3867:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_UQRSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) |
| 22781 | /* 62453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQRSHL), |
| 22782 | /* 62456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 22783 | /* 62458 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc |
| 22784 | /* 62460 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22785 | /* 62462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22786 | /* 62465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22787 | /* 62471 */ GIR_RootConstrainSelectedInstOperands, |
| 22788 | /* 62472 */ // GIR_Coverage, 1916, |
| 22789 | /* 62472 */ GIR_EraseRootFromParent_Done, |
| 22790 | /* 62473 */ // Label 1943: @62473 |
| 22791 | /* 62473 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1944*/ GIMT_Encode4(62529), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2041 // |
| 22792 | /* 62480 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16), |
| 22793 | /* 62485 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22794 | /* 62488 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22795 | /* 62491 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22796 | /* 62494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22797 | /* 62498 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22798 | /* 62502 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22799 | /* 62506 */ // (intrinsic_wo_chain:{ *:[i32] } 4205:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (SXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] }) |
| 22800 | /* 62506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB16), |
| 22801 | /* 62509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22802 | /* 62511 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS |
| 22803 | /* 62513 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS |
| 22804 | /* 62515 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22805 | /* 62518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22806 | /* 62521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22807 | /* 62527 */ GIR_RootConstrainSelectedInstOperands, |
| 22808 | /* 62528 */ // GIR_Coverage, 2041, |
| 22809 | /* 62528 */ GIR_EraseRootFromParent_Done, |
| 22810 | /* 62529 */ // Label 1944: @62529 |
| 22811 | /* 62529 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1945*/ GIMT_Encode4(62585), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2048 // |
| 22812 | /* 62536 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16), |
| 22813 | /* 62541 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22814 | /* 62544 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22815 | /* 62547 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22816 | /* 62550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22817 | /* 62554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22818 | /* 62558 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22819 | /* 62562 */ // (intrinsic_wo_chain:{ *:[i32] } 4230:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (UXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] }) |
| 22820 | /* 62562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB16), |
| 22821 | /* 62565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22822 | /* 62567 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS |
| 22823 | /* 62569 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS |
| 22824 | /* 62571 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22825 | /* 62574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22826 | /* 62577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22827 | /* 62583 */ GIR_RootConstrainSelectedInstOperands, |
| 22828 | /* 62584 */ // GIR_Coverage, 2048, |
| 22829 | /* 62584 */ GIR_EraseRootFromParent_Done, |
| 22830 | /* 62585 */ // Label 1945: @62585 |
| 22831 | /* 62585 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1946*/ GIMT_Encode4(62638), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2095 // |
| 22832 | /* 62592 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad), |
| 22833 | /* 62597 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22834 | /* 62600 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22835 | /* 62603 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22836 | /* 62606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22837 | /* 62610 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22838 | /* 62614 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22839 | /* 62618 */ // (intrinsic_wo_chain:{ *:[i32] } 4181:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 22840 | /* 62618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUAD), |
| 22841 | /* 62621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22842 | /* 62623 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22843 | /* 62625 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22844 | /* 62627 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22845 | /* 62630 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22846 | /* 62636 */ GIR_RootConstrainSelectedInstOperands, |
| 22847 | /* 62637 */ // GIR_Coverage, 2095, |
| 22848 | /* 62637 */ GIR_EraseRootFromParent_Done, |
| 22849 | /* 62638 */ // Label 1946: @62638 |
| 22850 | /* 62638 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1947*/ GIMT_Encode4(62691), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2096 // |
| 22851 | /* 62645 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx), |
| 22852 | /* 62650 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22853 | /* 62653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22854 | /* 62656 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22855 | /* 62659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22856 | /* 62663 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22857 | /* 62667 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22858 | /* 62671 */ // (intrinsic_wo_chain:{ *:[i32] } 4182:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 22859 | /* 62671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUADX), |
| 22860 | /* 62674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22861 | /* 62676 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22862 | /* 62678 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22863 | /* 62680 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22864 | /* 62683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22865 | /* 62689 */ GIR_RootConstrainSelectedInstOperands, |
| 22866 | /* 62690 */ // GIR_Coverage, 2096, |
| 22867 | /* 62690 */ GIR_EraseRootFromParent_Done, |
| 22868 | /* 62691 */ // Label 1947: @62691 |
| 22869 | /* 62691 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1948*/ GIMT_Encode4(62744), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2097 // |
| 22870 | /* 62698 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd), |
| 22871 | /* 62703 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22872 | /* 62706 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22873 | /* 62709 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22874 | /* 62712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22875 | /* 62716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22876 | /* 62720 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22877 | /* 62724 */ // (intrinsic_wo_chain:{ *:[i32] } 4189:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 22878 | /* 62724 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSD), |
| 22879 | /* 62727 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22880 | /* 62729 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22881 | /* 62731 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22882 | /* 62733 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22883 | /* 62736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22884 | /* 62742 */ GIR_RootConstrainSelectedInstOperands, |
| 22885 | /* 62743 */ // GIR_Coverage, 2097, |
| 22886 | /* 62743 */ GIR_EraseRootFromParent_Done, |
| 22887 | /* 62744 */ // Label 1948: @62744 |
| 22888 | /* 62744 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1949*/ GIMT_Encode4(62797), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2098 // |
| 22889 | /* 62751 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx), |
| 22890 | /* 62756 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22891 | /* 62759 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22892 | /* 62762 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22893 | /* 62765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22894 | /* 62769 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22895 | /* 62773 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 22896 | /* 62777 */ // (intrinsic_wo_chain:{ *:[i32] } 4190:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 22897 | /* 62777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSDX), |
| 22898 | /* 62780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22899 | /* 62782 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 22900 | /* 62784 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 22901 | /* 62786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22902 | /* 62789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22903 | /* 62795 */ GIR_RootConstrainSelectedInstOperands, |
| 22904 | /* 62796 */ // GIR_Coverage, 2098, |
| 22905 | /* 62796 */ GIR_EraseRootFromParent_Done, |
| 22906 | /* 62797 */ // Label 1949: @62797 |
| 22907 | /* 62797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1950*/ GIMT_Encode4(62850), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2177 // |
| 22908 | /* 62804 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb), |
| 22909 | /* 62809 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22910 | /* 62812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22911 | /* 62815 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22912 | /* 62818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22913 | /* 62822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22914 | /* 62826 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22915 | /* 62830 */ // (intrinsic_wo_chain:{ *:[i32] } 4183:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 22916 | /* 62830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB), |
| 22917 | /* 62833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22918 | /* 62835 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 22919 | /* 62837 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 22920 | /* 62839 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22921 | /* 62842 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22922 | /* 62848 */ GIR_RootConstrainSelectedInstOperands, |
| 22923 | /* 62849 */ // GIR_Coverage, 2177, |
| 22924 | /* 62849 */ GIR_EraseRootFromParent_Done, |
| 22925 | /* 62850 */ // Label 1950: @62850 |
| 22926 | /* 62850 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1951*/ GIMT_Encode4(62903), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2178 // |
| 22927 | /* 62857 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt), |
| 22928 | /* 62862 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22929 | /* 62865 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22930 | /* 62868 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22931 | /* 62871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22932 | /* 62875 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22933 | /* 62879 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22934 | /* 62883 */ // (intrinsic_wo_chain:{ *:[i32] } 4184:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 22935 | /* 62883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT), |
| 22936 | /* 62886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22937 | /* 62888 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 22938 | /* 62890 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 22939 | /* 62892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22940 | /* 62895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22941 | /* 62901 */ GIR_RootConstrainSelectedInstOperands, |
| 22942 | /* 62902 */ // GIR_Coverage, 2178, |
| 22943 | /* 62902 */ GIR_EraseRootFromParent_Done, |
| 22944 | /* 62903 */ // Label 1951: @62903 |
| 22945 | /* 62903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1952*/ GIMT_Encode4(62956), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2179 // |
| 22946 | /* 62910 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb), |
| 22947 | /* 62915 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22948 | /* 62918 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22949 | /* 62921 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22950 | /* 62924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22951 | /* 62928 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22952 | /* 62932 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22953 | /* 62936 */ // (intrinsic_wo_chain:{ *:[i32] } 4185:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 22954 | /* 62936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB), |
| 22955 | /* 62939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22956 | /* 62941 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 22957 | /* 62943 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 22958 | /* 62945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22959 | /* 62948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22960 | /* 62954 */ GIR_RootConstrainSelectedInstOperands, |
| 22961 | /* 62955 */ // GIR_Coverage, 2179, |
| 22962 | /* 62955 */ GIR_EraseRootFromParent_Done, |
| 22963 | /* 62956 */ // Label 1952: @62956 |
| 22964 | /* 62956 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1953*/ GIMT_Encode4(63009), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2180 // |
| 22965 | /* 62963 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt), |
| 22966 | /* 62968 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22967 | /* 62971 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22968 | /* 62974 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22969 | /* 62977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22970 | /* 62981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22971 | /* 62985 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22972 | /* 62989 */ // (intrinsic_wo_chain:{ *:[i32] } 4186:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 22973 | /* 62989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT), |
| 22974 | /* 62992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22975 | /* 62994 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 22976 | /* 62996 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 22977 | /* 62998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22978 | /* 63001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22979 | /* 63007 */ GIR_RootConstrainSelectedInstOperands, |
| 22980 | /* 63008 */ // GIR_Coverage, 2180, |
| 22981 | /* 63008 */ GIR_EraseRootFromParent_Done, |
| 22982 | /* 63009 */ // Label 1953: @63009 |
| 22983 | /* 63009 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1954*/ GIMT_Encode4(63062), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2181 // |
| 22984 | /* 63016 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb), |
| 22985 | /* 63021 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 22986 | /* 63024 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 22987 | /* 63027 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 22988 | /* 63030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22989 | /* 63034 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22990 | /* 63038 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 22991 | /* 63042 */ // (intrinsic_wo_chain:{ *:[i32] } 4187:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 22992 | /* 63042 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWB), |
| 22993 | /* 63045 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 22994 | /* 63047 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 22995 | /* 63049 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 22996 | /* 63051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 22997 | /* 63054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 22998 | /* 63060 */ GIR_RootConstrainSelectedInstOperands, |
| 22999 | /* 63061 */ // GIR_Coverage, 2181, |
| 23000 | /* 63061 */ GIR_EraseRootFromParent_Done, |
| 23001 | /* 63062 */ // Label 1954: @63062 |
| 23002 | /* 63062 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1955*/ GIMT_Encode4(63115), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2182 // |
| 23003 | /* 63069 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt), |
| 23004 | /* 63074 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23005 | /* 63077 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23006 | /* 63080 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23007 | /* 63083 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23008 | /* 63087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23009 | /* 63091 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 23010 | /* 63095 */ // (intrinsic_wo_chain:{ *:[i32] } 4188:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 23011 | /* 63095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWT), |
| 23012 | /* 63098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23013 | /* 63100 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 23014 | /* 63102 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 23015 | /* 63104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23016 | /* 63107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23017 | /* 63113 */ GIR_RootConstrainSelectedInstOperands, |
| 23018 | /* 63114 */ // GIR_Coverage, 2182, |
| 23019 | /* 63114 */ GIR_EraseRootFromParent_Done, |
| 23020 | /* 63115 */ // Label 1955: @63115 |
| 23021 | /* 63115 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1956*/ GIMT_Encode4(63171), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2294 // |
| 23022 | /* 63122 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16), |
| 23023 | /* 63127 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23024 | /* 63130 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23025 | /* 63133 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23026 | /* 63136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23027 | /* 63140 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23028 | /* 63144 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23029 | /* 63148 */ // (intrinsic_wo_chain:{ *:[i32] } 4205:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] }) |
| 23030 | /* 63148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB16), |
| 23031 | /* 63151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23032 | /* 63153 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23033 | /* 63155 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23034 | /* 63157 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23035 | /* 63160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23036 | /* 63163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23037 | /* 63169 */ GIR_RootConstrainSelectedInstOperands, |
| 23038 | /* 63170 */ // GIR_Coverage, 2294, |
| 23039 | /* 63170 */ GIR_EraseRootFromParent_Done, |
| 23040 | /* 63171 */ // Label 1956: @63171 |
| 23041 | /* 63171 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1957*/ GIMT_Encode4(63224), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2324 // |
| 23042 | /* 63178 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd), |
| 23043 | /* 63183 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23044 | /* 63186 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23045 | /* 63189 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23046 | /* 63192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23047 | /* 63196 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23048 | /* 63200 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23049 | /* 63204 */ // (intrinsic_wo_chain:{ *:[i32] } 4148:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 23050 | /* 63204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD), |
| 23051 | /* 63207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23052 | /* 63209 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 23053 | /* 63211 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 23054 | /* 63213 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23055 | /* 63216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23056 | /* 63222 */ GIR_RootConstrainSelectedInstOperands, |
| 23057 | /* 63223 */ // GIR_Coverage, 2324, |
| 23058 | /* 63223 */ GIR_EraseRootFromParent_Done, |
| 23059 | /* 63224 */ // Label 1957: @63224 |
| 23060 | /* 63224 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1958*/ GIMT_Encode4(63277), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2325 // |
| 23061 | /* 63231 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub), |
| 23062 | /* 63236 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23063 | /* 63239 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23064 | /* 63242 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23065 | /* 63245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23066 | /* 63249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23067 | /* 63253 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23068 | /* 63257 */ // (intrinsic_wo_chain:{ *:[i32] } 4153:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 23069 | /* 63257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB), |
| 23070 | /* 63260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23071 | /* 63262 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 23072 | /* 63264 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 23073 | /* 63266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23074 | /* 63269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23075 | /* 63275 */ GIR_RootConstrainSelectedInstOperands, |
| 23076 | /* 63276 */ // GIR_Coverage, 2325, |
| 23077 | /* 63276 */ GIR_EraseRootFromParent_Done, |
| 23078 | /* 63277 */ // Label 1958: @63277 |
| 23079 | /* 63277 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1959*/ GIMT_Encode4(63330), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2365 // |
| 23080 | /* 63284 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb), |
| 23081 | /* 63289 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23082 | /* 63292 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23083 | /* 63295 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23084 | /* 63298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23085 | /* 63302 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23086 | /* 63306 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23087 | /* 63310 */ // (intrinsic_wo_chain:{ *:[i32] } 4183:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23088 | /* 63310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB), |
| 23089 | /* 63313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23090 | /* 63315 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23091 | /* 63317 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23092 | /* 63319 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23093 | /* 63322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23094 | /* 63328 */ GIR_RootConstrainSelectedInstOperands, |
| 23095 | /* 63329 */ // GIR_Coverage, 2365, |
| 23096 | /* 63329 */ GIR_EraseRootFromParent_Done, |
| 23097 | /* 63330 */ // Label 1959: @63330 |
| 23098 | /* 63330 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1960*/ GIMT_Encode4(63383), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2366 // |
| 23099 | /* 63337 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt), |
| 23100 | /* 63342 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23101 | /* 63345 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23102 | /* 63348 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23103 | /* 63351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23104 | /* 63355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23105 | /* 63359 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23106 | /* 63363 */ // (intrinsic_wo_chain:{ *:[i32] } 4184:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23107 | /* 63363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT), |
| 23108 | /* 63366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23109 | /* 63368 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23110 | /* 63370 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23111 | /* 63372 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23112 | /* 63375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23113 | /* 63381 */ GIR_RootConstrainSelectedInstOperands, |
| 23114 | /* 63382 */ // GIR_Coverage, 2366, |
| 23115 | /* 63382 */ GIR_EraseRootFromParent_Done, |
| 23116 | /* 63383 */ // Label 1960: @63383 |
| 23117 | /* 63383 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1961*/ GIMT_Encode4(63436), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2367 // |
| 23118 | /* 63390 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb), |
| 23119 | /* 63395 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23120 | /* 63398 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23121 | /* 63401 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23122 | /* 63404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23123 | /* 63408 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23124 | /* 63412 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23125 | /* 63416 */ // (intrinsic_wo_chain:{ *:[i32] } 4185:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23126 | /* 63416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB), |
| 23127 | /* 63419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23128 | /* 63421 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23129 | /* 63423 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23130 | /* 63425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23131 | /* 63428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23132 | /* 63434 */ GIR_RootConstrainSelectedInstOperands, |
| 23133 | /* 63435 */ // GIR_Coverage, 2367, |
| 23134 | /* 63435 */ GIR_EraseRootFromParent_Done, |
| 23135 | /* 63436 */ // Label 1961: @63436 |
| 23136 | /* 63436 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1962*/ GIMT_Encode4(63489), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2368 // |
| 23137 | /* 63443 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt), |
| 23138 | /* 63448 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23139 | /* 63451 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23140 | /* 63454 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23141 | /* 63457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23142 | /* 63461 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23143 | /* 63465 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23144 | /* 63469 */ // (intrinsic_wo_chain:{ *:[i32] } 4186:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23145 | /* 63469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT), |
| 23146 | /* 63472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23147 | /* 63474 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23148 | /* 63476 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23149 | /* 63478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23150 | /* 63481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23151 | /* 63487 */ GIR_RootConstrainSelectedInstOperands, |
| 23152 | /* 63488 */ // GIR_Coverage, 2368, |
| 23153 | /* 63488 */ GIR_EraseRootFromParent_Done, |
| 23154 | /* 63489 */ // Label 1962: @63489 |
| 23155 | /* 63489 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1963*/ GIMT_Encode4(63542), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2369 // |
| 23156 | /* 63496 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb), |
| 23157 | /* 63501 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23158 | /* 63504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23159 | /* 63507 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23160 | /* 63510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23161 | /* 63514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23162 | /* 63518 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23163 | /* 63522 */ // (intrinsic_wo_chain:{ *:[i32] } 4187:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23164 | /* 63522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWB), |
| 23165 | /* 63525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23166 | /* 63527 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23167 | /* 63529 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23168 | /* 63531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23169 | /* 63534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23170 | /* 63540 */ GIR_RootConstrainSelectedInstOperands, |
| 23171 | /* 63541 */ // GIR_Coverage, 2369, |
| 23172 | /* 63541 */ GIR_EraseRootFromParent_Done, |
| 23173 | /* 63542 */ // Label 1963: @63542 |
| 23174 | /* 63542 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1964*/ GIMT_Encode4(63595), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2370 // |
| 23175 | /* 63549 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt), |
| 23176 | /* 63554 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23177 | /* 63557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23178 | /* 63560 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 23179 | /* 63563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23180 | /* 63567 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23181 | /* 63571 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23182 | /* 63575 */ // (intrinsic_wo_chain:{ *:[i32] } 4188:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 23183 | /* 63575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWT), |
| 23184 | /* 63578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 23185 | /* 63580 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23186 | /* 63582 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23187 | /* 63584 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 23188 | /* 63587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23189 | /* 63593 */ GIR_RootConstrainSelectedInstOperands, |
| 23190 | /* 63594 */ // GIR_Coverage, 2370, |
| 23191 | /* 63594 */ GIR_EraseRootFromParent_Done, |
| 23192 | /* 63595 */ // Label 1964: @63595 |
| 23193 | /* 63595 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1965*/ GIMT_Encode4(63642), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2899 // |
| 23194 | /* 63602 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 23195 | /* 63607 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 23196 | /* 63610 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 23197 | /* 63613 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 23198 | /* 63616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23199 | /* 63620 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23200 | /* 63624 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23201 | /* 63628 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4041:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 0:{ *:[i32] }) |
| 23202 | /* 63628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16), |
| 23203 | /* 63631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23204 | /* 63633 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23205 | /* 63635 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23206 | /* 63637 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23207 | /* 63640 */ GIR_RootConstrainSelectedInstOperands, |
| 23208 | /* 63641 */ // GIR_Coverage, 2899, |
| 23209 | /* 63641 */ GIR_EraseRootFromParent_Done, |
| 23210 | /* 63642 */ // Label 1965: @63642 |
| 23211 | /* 63642 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1966*/ GIMT_Encode4(63689), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2900 // |
| 23212 | /* 63649 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 23213 | /* 63654 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 23214 | /* 63657 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 23215 | /* 63660 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 23216 | /* 63663 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23217 | /* 63667 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23218 | /* 63671 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23219 | /* 63675 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4040:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 1:{ *:[i32] }) |
| 23220 | /* 63675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16), |
| 23221 | /* 63678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23222 | /* 63680 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23223 | /* 63682 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23224 | /* 63684 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 23225 | /* 63687 */ GIR_RootConstrainSelectedInstOperands, |
| 23226 | /* 63688 */ // GIR_Coverage, 2900, |
| 23227 | /* 63688 */ GIR_EraseRootFromParent_Done, |
| 23228 | /* 63689 */ // Label 1966: @63689 |
| 23229 | /* 63689 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1967*/ GIMT_Encode4(63736), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2901 // |
| 23230 | /* 63696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 23231 | /* 63701 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23232 | /* 63704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23233 | /* 63707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23234 | /* 63710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23235 | /* 63714 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23236 | /* 63718 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23237 | /* 63722 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4041:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 0:{ *:[i32] }) |
| 23238 | /* 63722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16), |
| 23239 | /* 63725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23240 | /* 63727 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23241 | /* 63729 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23242 | /* 63731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23243 | /* 63734 */ GIR_RootConstrainSelectedInstOperands, |
| 23244 | /* 63735 */ // GIR_Coverage, 2901, |
| 23245 | /* 63735 */ GIR_EraseRootFromParent_Done, |
| 23246 | /* 63736 */ // Label 1967: @63736 |
| 23247 | /* 63736 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1968*/ GIMT_Encode4(63783), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2902 // |
| 23248 | /* 63743 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 23249 | /* 63748 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23250 | /* 63751 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23251 | /* 63754 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23252 | /* 63757 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23253 | /* 63761 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23254 | /* 63765 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23255 | /* 63769 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4040:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 1:{ *:[i32] }) |
| 23256 | /* 63769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16), |
| 23257 | /* 63772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23258 | /* 63774 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23259 | /* 63776 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23260 | /* 63778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 23261 | /* 63781 */ GIR_RootConstrainSelectedInstOperands, |
| 23262 | /* 63782 */ // GIR_Coverage, 2902, |
| 23263 | /* 63782 */ GIR_EraseRootFromParent_Done, |
| 23264 | /* 63783 */ // Label 1968: @63783 |
| 23265 | /* 63783 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1969*/ GIMT_Encode4(63830), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2903 // |
| 23266 | /* 63790 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 23267 | /* 63795 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 23268 | /* 63798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 23269 | /* 63801 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 23270 | /* 63804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23271 | /* 63808 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23272 | /* 63812 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23273 | /* 63816 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4041:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 0:{ *:[i32] }) |
| 23274 | /* 63816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32), |
| 23275 | /* 63819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23276 | /* 63821 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23277 | /* 63823 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23278 | /* 63825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23279 | /* 63828 */ GIR_RootConstrainSelectedInstOperands, |
| 23280 | /* 63829 */ // GIR_Coverage, 2903, |
| 23281 | /* 63829 */ GIR_EraseRootFromParent_Done, |
| 23282 | /* 63830 */ // Label 1969: @63830 |
| 23283 | /* 63830 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1970*/ GIMT_Encode4(63877), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2904 // |
| 23284 | /* 63837 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 23285 | /* 63842 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 23286 | /* 63845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 23287 | /* 63848 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 23288 | /* 63851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23289 | /* 63855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23290 | /* 63859 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 23291 | /* 63863 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4040:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 1:{ *:[i32] }) |
| 23292 | /* 63863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32), |
| 23293 | /* 63866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23294 | /* 63868 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23295 | /* 63870 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23296 | /* 63872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 23297 | /* 63875 */ GIR_RootConstrainSelectedInstOperands, |
| 23298 | /* 63876 */ // GIR_Coverage, 2904, |
| 23299 | /* 63876 */ GIR_EraseRootFromParent_Done, |
| 23300 | /* 63877 */ // Label 1970: @63877 |
| 23301 | /* 63877 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1971*/ GIMT_Encode4(63924), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2905 // |
| 23302 | /* 63884 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90), |
| 23303 | /* 63889 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23304 | /* 63892 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23305 | /* 63895 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23306 | /* 63898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23307 | /* 63902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23308 | /* 63906 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23309 | /* 63910 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4041:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 0:{ *:[i32] }) |
| 23310 | /* 63910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32), |
| 23311 | /* 63913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23312 | /* 63915 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23313 | /* 63917 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23314 | /* 63919 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23315 | /* 63922 */ GIR_RootConstrainSelectedInstOperands, |
| 23316 | /* 63923 */ // GIR_Coverage, 2905, |
| 23317 | /* 63923 */ GIR_EraseRootFromParent_Done, |
| 23318 | /* 63924 */ // Label 1971: @63924 |
| 23319 | /* 63924 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1972*/ GIMT_Encode4(63971), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2906 // |
| 23320 | /* 63931 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270), |
| 23321 | /* 63936 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23322 | /* 63939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23323 | /* 63942 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23324 | /* 63945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23325 | /* 63949 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23326 | /* 63953 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 23327 | /* 63957 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4040:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 1:{ *:[i32] }) |
| 23328 | /* 63957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32), |
| 23329 | /* 63960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 23330 | /* 63962 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 23331 | /* 63964 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 23332 | /* 63966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 23333 | /* 63969 */ GIR_RootConstrainSelectedInstOperands, |
| 23334 | /* 63970 */ // GIR_Coverage, 2906, |
| 23335 | /* 63970 */ GIR_EraseRootFromParent_Done, |
| 23336 | /* 63971 */ // Label 1972: @63971 |
| 23337 | /* 63971 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1973*/ GIMT_Encode4(64045), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3417 // |
| 23338 | /* 63978 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm), |
| 23339 | /* 63983 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 23340 | /* 63986 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23341 | /* 63989 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23342 | /* 63992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23343 | /* 63996 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23344 | /* 64000 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23345 | /* 64004 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3928:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 23346 | /* 64004 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23347 | /* 64007 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23348 | /* 64011 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23349 | /* 64016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32), |
| 23350 | /* 64019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23351 | /* 64021 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23352 | /* 64023 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23353 | /* 64025 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23354 | /* 64028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23355 | /* 64034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23356 | /* 64040 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23357 | /* 64043 */ GIR_RootConstrainSelectedInstOperands, |
| 23358 | /* 64044 */ // GIR_Coverage, 3417, |
| 23359 | /* 64044 */ GIR_EraseRootFromParent_Done, |
| 23360 | /* 64045 */ // Label 1973: @64045 |
| 23361 | /* 64045 */ GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(64269), |
| 23362 | /* 64050 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv), |
| 23363 | /* 64055 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1977*/ GIMT_Encode4(64268), |
| 23364 | /* 64066 */ /*GILLT_s16*//*Label 1975*/ GIMT_Encode4(64074), |
| 23365 | /* 64070 */ /*GILLT_s32*//*Label 1976*/ GIMT_Encode4(64171), |
| 23366 | /* 64074 */ // Label 1975: @64074 |
| 23367 | /* 64074 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1978*/ GIMT_Encode4(64170), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3495 // |
| 23368 | /* 64081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 23369 | /* 64084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23370 | /* 64087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23371 | /* 64091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23372 | /* 64095 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23373 | /* 64099 */ // (intrinsic_wo_chain:{ *:[f16] } 3836:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 23374 | /* 64099 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23375 | /* 64102 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23376 | /* 64106 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23377 | /* 64111 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23378 | /* 64115 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23379 | /* 64120 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23380 | /* 64123 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf16), |
| 23381 | /* 64127 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23382 | /* 64132 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23383 | /* 64135 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23384 | /* 64139 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23385 | /* 64142 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23386 | /* 64148 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23387 | /* 64154 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23388 | /* 64156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23389 | /* 64159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23390 | /* 64161 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23391 | /* 64164 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 23392 | /* 64169 */ // GIR_Coverage, 3495, |
| 23393 | /* 64169 */ GIR_EraseRootFromParent_Done, |
| 23394 | /* 64170 */ // Label 1978: @64170 |
| 23395 | /* 64170 */ GIM_Reject, |
| 23396 | /* 64171 */ // Label 1976: @64171 |
| 23397 | /* 64171 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1979*/ GIMT_Encode4(64267), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3493 // |
| 23398 | /* 64178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23399 | /* 64181 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23400 | /* 64184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23401 | /* 64188 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23402 | /* 64192 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23403 | /* 64196 */ // (intrinsic_wo_chain:{ *:[f32] } 3836:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 23404 | /* 64196 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23405 | /* 64199 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23406 | /* 64203 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23407 | /* 64208 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23408 | /* 64212 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23409 | /* 64217 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23410 | /* 64220 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf32), |
| 23411 | /* 64224 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23412 | /* 64229 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23413 | /* 64232 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23414 | /* 64236 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23415 | /* 64239 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23416 | /* 64245 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23417 | /* 64251 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23418 | /* 64253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23419 | /* 64256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23420 | /* 64258 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23421 | /* 64261 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 23422 | /* 64266 */ // GIR_Coverage, 3493, |
| 23423 | /* 64266 */ GIR_EraseRootFromParent_Done, |
| 23424 | /* 64267 */ // Label 1979: @64267 |
| 23425 | /* 64267 */ GIM_Reject, |
| 23426 | /* 64268 */ // Label 1977: @64268 |
| 23427 | /* 64268 */ GIM_Reject, |
| 23428 | /* 64269 */ // Label 1974: @64269 |
| 23429 | /* 64269 */ GIM_Try, /*On fail goto*//*Label 1980*/ GIMT_Encode4(64493), |
| 23430 | /* 64274 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv), |
| 23431 | /* 64279 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1983*/ GIMT_Encode4(64492), |
| 23432 | /* 64290 */ /*GILLT_s16*//*Label 1981*/ GIMT_Encode4(64298), |
| 23433 | /* 64294 */ /*GILLT_s32*//*Label 1982*/ GIMT_Encode4(64395), |
| 23434 | /* 64298 */ // Label 1981: @64298 |
| 23435 | /* 64298 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1984*/ GIMT_Encode4(64394), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3499 // |
| 23436 | /* 64305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 23437 | /* 64308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23438 | /* 64311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23439 | /* 64315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23440 | /* 64319 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23441 | /* 64323 */ // (intrinsic_wo_chain:{ *:[f16] } 3827:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 23442 | /* 64323 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23443 | /* 64326 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23444 | /* 64330 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23445 | /* 64335 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23446 | /* 64339 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23447 | /* 64344 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23448 | /* 64347 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf16), |
| 23449 | /* 64351 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23450 | /* 64356 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23451 | /* 64359 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23452 | /* 64363 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23453 | /* 64366 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23454 | /* 64372 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23455 | /* 64378 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23456 | /* 64380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23457 | /* 64383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23458 | /* 64385 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23459 | /* 64388 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 23460 | /* 64393 */ // GIR_Coverage, 3499, |
| 23461 | /* 64393 */ GIR_EraseRootFromParent_Done, |
| 23462 | /* 64394 */ // Label 1984: @64394 |
| 23463 | /* 64394 */ GIM_Reject, |
| 23464 | /* 64395 */ // Label 1982: @64395 |
| 23465 | /* 64395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1985*/ GIMT_Encode4(64491), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3497 // |
| 23466 | /* 64402 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23467 | /* 64405 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23468 | /* 64408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23469 | /* 64412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23470 | /* 64416 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23471 | /* 64420 */ // (intrinsic_wo_chain:{ *:[f32] } 3827:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 23472 | /* 64420 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23473 | /* 64423 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23474 | /* 64427 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23475 | /* 64432 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23476 | /* 64436 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23477 | /* 64441 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23478 | /* 64444 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf32), |
| 23479 | /* 64448 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23480 | /* 64453 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23481 | /* 64456 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23482 | /* 64460 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23483 | /* 64463 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23484 | /* 64469 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23485 | /* 64475 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23486 | /* 64477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23487 | /* 64480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23488 | /* 64482 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23489 | /* 64485 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 23490 | /* 64490 */ // GIR_Coverage, 3497, |
| 23491 | /* 64490 */ GIR_EraseRootFromParent_Done, |
| 23492 | /* 64491 */ // Label 1985: @64491 |
| 23493 | /* 64491 */ GIM_Reject, |
| 23494 | /* 64492 */ // Label 1983: @64492 |
| 23495 | /* 64492 */ GIM_Reject, |
| 23496 | /* 64493 */ // Label 1980: @64493 |
| 23497 | /* 64493 */ GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(64717), |
| 23498 | /* 64498 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav), |
| 23499 | /* 64503 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1989*/ GIMT_Encode4(64716), |
| 23500 | /* 64514 */ /*GILLT_s16*//*Label 1987*/ GIMT_Encode4(64522), |
| 23501 | /* 64518 */ /*GILLT_s32*//*Label 1988*/ GIMT_Encode4(64619), |
| 23502 | /* 64522 */ // Label 1987: @64522 |
| 23503 | /* 64522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1990*/ GIMT_Encode4(64618), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3503 // |
| 23504 | /* 64529 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 23505 | /* 64532 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23506 | /* 64535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23507 | /* 64539 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23508 | /* 64543 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23509 | /* 64547 */ // (intrinsic_wo_chain:{ *:[f16] } 3834:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 23510 | /* 64547 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23511 | /* 64550 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23512 | /* 64554 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23513 | /* 64559 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23514 | /* 64563 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23515 | /* 64568 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23516 | /* 64571 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf16), |
| 23517 | /* 64575 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23518 | /* 64580 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23519 | /* 64583 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23520 | /* 64587 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23521 | /* 64590 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23522 | /* 64596 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23523 | /* 64602 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23524 | /* 64604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23525 | /* 64607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23526 | /* 64609 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23527 | /* 64612 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 23528 | /* 64617 */ // GIR_Coverage, 3503, |
| 23529 | /* 64617 */ GIR_EraseRootFromParent_Done, |
| 23530 | /* 64618 */ // Label 1990: @64618 |
| 23531 | /* 64618 */ GIM_Reject, |
| 23532 | /* 64619 */ // Label 1988: @64619 |
| 23533 | /* 64619 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1991*/ GIMT_Encode4(64715), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3501 // |
| 23534 | /* 64626 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23535 | /* 64629 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23536 | /* 64632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23537 | /* 64636 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23538 | /* 64640 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23539 | /* 64644 */ // (intrinsic_wo_chain:{ *:[f32] } 3834:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 23540 | /* 64644 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23541 | /* 64647 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23542 | /* 64651 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23543 | /* 64656 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23544 | /* 64660 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23545 | /* 64665 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23546 | /* 64668 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf32), |
| 23547 | /* 64672 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23548 | /* 64677 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23549 | /* 64680 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23550 | /* 64684 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23551 | /* 64687 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23552 | /* 64693 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23553 | /* 64699 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23554 | /* 64701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23555 | /* 64704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23556 | /* 64706 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23557 | /* 64709 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 23558 | /* 64714 */ // GIR_Coverage, 3501, |
| 23559 | /* 64714 */ GIR_EraseRootFromParent_Done, |
| 23560 | /* 64715 */ // Label 1991: @64715 |
| 23561 | /* 64715 */ GIM_Reject, |
| 23562 | /* 64716 */ // Label 1989: @64716 |
| 23563 | /* 64716 */ GIM_Reject, |
| 23564 | /* 64717 */ // Label 1986: @64717 |
| 23565 | /* 64717 */ GIM_Try, /*On fail goto*//*Label 1992*/ GIMT_Encode4(64941), |
| 23566 | /* 64722 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav), |
| 23567 | /* 64727 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1995*/ GIMT_Encode4(64940), |
| 23568 | /* 64738 */ /*GILLT_s16*//*Label 1993*/ GIMT_Encode4(64746), |
| 23569 | /* 64742 */ /*GILLT_s32*//*Label 1994*/ GIMT_Encode4(64843), |
| 23570 | /* 64746 */ // Label 1993: @64746 |
| 23571 | /* 64746 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1996*/ GIMT_Encode4(64842), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3507 // |
| 23572 | /* 64753 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 23573 | /* 64756 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23574 | /* 64759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23575 | /* 64763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 23576 | /* 64767 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23577 | /* 64771 */ // (intrinsic_wo_chain:{ *:[f16] } 3825:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] }) |
| 23578 | /* 64771 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23579 | /* 64774 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23580 | /* 64778 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23581 | /* 64783 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23582 | /* 64787 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23583 | /* 64792 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23584 | /* 64795 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf16), |
| 23585 | /* 64799 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23586 | /* 64804 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23587 | /* 64807 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23588 | /* 64811 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23589 | /* 64814 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23590 | /* 64820 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23591 | /* 64826 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23592 | /* 64828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23593 | /* 64831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23594 | /* 64833 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23595 | /* 64836 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 23596 | /* 64841 */ // GIR_Coverage, 3507, |
| 23597 | /* 64841 */ GIR_EraseRootFromParent_Done, |
| 23598 | /* 64842 */ // Label 1996: @64842 |
| 23599 | /* 64842 */ GIM_Reject, |
| 23600 | /* 64843 */ // Label 1994: @64843 |
| 23601 | /* 64843 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1997*/ GIMT_Encode4(64939), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3505 // |
| 23602 | /* 64850 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23603 | /* 64853 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23604 | /* 64856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23605 | /* 64860 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 23606 | /* 64864 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23607 | /* 64868 */ // (intrinsic_wo_chain:{ *:[f32] } 3825:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] }) |
| 23608 | /* 64868 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 23609 | /* 64871 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23610 | /* 64875 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23611 | /* 64880 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev |
| 23612 | /* 64884 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID), |
| 23613 | /* 64889 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 23614 | /* 64892 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf32), |
| 23615 | /* 64896 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23616 | /* 64901 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 23617 | /* 64904 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec |
| 23618 | /* 64908 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 23619 | /* 64911 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23620 | /* 64917 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23621 | /* 64923 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 23622 | /* 64925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 23623 | /* 64928 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 23624 | /* 64930 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23625 | /* 64933 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 23626 | /* 64938 */ // GIR_Coverage, 3505, |
| 23627 | /* 64938 */ GIR_EraseRootFromParent_Done, |
| 23628 | /* 64939 */ // Label 1997: @64939 |
| 23629 | /* 64939 */ GIM_Reject, |
| 23630 | /* 64940 */ // Label 1995: @64940 |
| 23631 | /* 64940 */ GIM_Reject, |
| 23632 | /* 64941 */ // Label 1992: @64941 |
| 23633 | /* 64941 */ GIM_Try, /*On fail goto*//*Label 1998*/ GIMT_Encode4(65127), |
| 23634 | /* 64946 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav), |
| 23635 | /* 64951 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23636 | /* 64954 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23637 | /* 64957 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2002*/ GIMT_Encode4(65126), |
| 23638 | /* 64968 */ /*GILLT_v16s8*//*Label 1999*/ GIMT_Encode4(64988), GIMT_Encode4(0), |
| 23639 | /* 64976 */ /*GILLT_v8s16*//*Label 2000*/ GIMT_Encode4(65034), GIMT_Encode4(0), |
| 23640 | /* 64984 */ /*GILLT_v4s32*//*Label 2001*/ GIMT_Encode4(65080), |
| 23641 | /* 64988 */ // Label 1999: @64988 |
| 23642 | /* 64988 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2003*/ GIMT_Encode4(65033), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3557 // |
| 23643 | /* 64995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23644 | /* 64999 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23645 | /* 65003 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23646 | /* 65007 */ // (intrinsic_wo_chain:{ *:[i32] } 3832:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMINAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 23647 | /* 65007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs8), |
| 23648 | /* 65010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23649 | /* 65012 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23650 | /* 65014 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23651 | /* 65016 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23652 | /* 65019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23653 | /* 65025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23654 | /* 65031 */ GIR_RootConstrainSelectedInstOperands, |
| 23655 | /* 65032 */ // GIR_Coverage, 3557, |
| 23656 | /* 65032 */ GIR_EraseRootFromParent_Done, |
| 23657 | /* 65033 */ // Label 2003: @65033 |
| 23658 | /* 65033 */ GIM_Reject, |
| 23659 | /* 65034 */ // Label 2000: @65034 |
| 23660 | /* 65034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2004*/ GIMT_Encode4(65079), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3559 // |
| 23661 | /* 65041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23662 | /* 65045 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23663 | /* 65049 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23664 | /* 65053 */ // (intrinsic_wo_chain:{ *:[i32] } 3832:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMINAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 23665 | /* 65053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs16), |
| 23666 | /* 65056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23667 | /* 65058 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23668 | /* 65060 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23669 | /* 65062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23670 | /* 65065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23671 | /* 65071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23672 | /* 65077 */ GIR_RootConstrainSelectedInstOperands, |
| 23673 | /* 65078 */ // GIR_Coverage, 3559, |
| 23674 | /* 65078 */ GIR_EraseRootFromParent_Done, |
| 23675 | /* 65079 */ // Label 2004: @65079 |
| 23676 | /* 65079 */ GIM_Reject, |
| 23677 | /* 65080 */ // Label 2001: @65080 |
| 23678 | /* 65080 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2005*/ GIMT_Encode4(65125), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3561 // |
| 23679 | /* 65087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23680 | /* 65091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23681 | /* 65095 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23682 | /* 65099 */ // (intrinsic_wo_chain:{ *:[i32] } 3832:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMINAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 23683 | /* 65099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs32), |
| 23684 | /* 65102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23685 | /* 65104 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23686 | /* 65106 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23687 | /* 65108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23688 | /* 65111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23689 | /* 65117 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23690 | /* 65123 */ GIR_RootConstrainSelectedInstOperands, |
| 23691 | /* 65124 */ // GIR_Coverage, 3561, |
| 23692 | /* 65124 */ GIR_EraseRootFromParent_Done, |
| 23693 | /* 65125 */ // Label 2005: @65125 |
| 23694 | /* 65125 */ GIM_Reject, |
| 23695 | /* 65126 */ // Label 2002: @65126 |
| 23696 | /* 65126 */ GIM_Reject, |
| 23697 | /* 65127 */ // Label 1998: @65127 |
| 23698 | /* 65127 */ GIM_Try, /*On fail goto*//*Label 2006*/ GIMT_Encode4(65313), |
| 23699 | /* 65132 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav), |
| 23700 | /* 65137 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 23701 | /* 65140 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 23702 | /* 65143 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2010*/ GIMT_Encode4(65312), |
| 23703 | /* 65154 */ /*GILLT_v16s8*//*Label 2007*/ GIMT_Encode4(65174), GIMT_Encode4(0), |
| 23704 | /* 65162 */ /*GILLT_v8s16*//*Label 2008*/ GIMT_Encode4(65220), GIMT_Encode4(0), |
| 23705 | /* 65170 */ /*GILLT_v4s32*//*Label 2009*/ GIMT_Encode4(65266), |
| 23706 | /* 65174 */ // Label 2007: @65174 |
| 23707 | /* 65174 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2011*/ GIMT_Encode4(65219), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3563 // |
| 23708 | /* 65181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23709 | /* 65185 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23710 | /* 65189 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23711 | /* 65193 */ // (intrinsic_wo_chain:{ *:[i32] } 3823:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMAXAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 23712 | /* 65193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs8), |
| 23713 | /* 65196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23714 | /* 65198 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23715 | /* 65200 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23716 | /* 65202 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23717 | /* 65205 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23718 | /* 65211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23719 | /* 65217 */ GIR_RootConstrainSelectedInstOperands, |
| 23720 | /* 65218 */ // GIR_Coverage, 3563, |
| 23721 | /* 65218 */ GIR_EraseRootFromParent_Done, |
| 23722 | /* 65219 */ // Label 2011: @65219 |
| 23723 | /* 65219 */ GIM_Reject, |
| 23724 | /* 65220 */ // Label 2008: @65220 |
| 23725 | /* 65220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2012*/ GIMT_Encode4(65265), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3565 // |
| 23726 | /* 65227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23727 | /* 65231 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23728 | /* 65235 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23729 | /* 65239 */ // (intrinsic_wo_chain:{ *:[i32] } 3823:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMAXAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 23730 | /* 65239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs16), |
| 23731 | /* 65242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23732 | /* 65244 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23733 | /* 65246 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23734 | /* 65248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23735 | /* 65251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23736 | /* 65257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23737 | /* 65263 */ GIR_RootConstrainSelectedInstOperands, |
| 23738 | /* 65264 */ // GIR_Coverage, 3565, |
| 23739 | /* 65264 */ GIR_EraseRootFromParent_Done, |
| 23740 | /* 65265 */ // Label 2012: @65265 |
| 23741 | /* 65265 */ GIM_Reject, |
| 23742 | /* 65266 */ // Label 2009: @65266 |
| 23743 | /* 65266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2013*/ GIMT_Encode4(65311), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3567 // |
| 23744 | /* 65273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23745 | /* 65277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 23746 | /* 65281 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23747 | /* 65285 */ // (intrinsic_wo_chain:{ *:[i32] } 3823:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMAXAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 23748 | /* 65285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs32), |
| 23749 | /* 65288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 23750 | /* 65290 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 23751 | /* 65292 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 23752 | /* 65294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23753 | /* 65297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23754 | /* 65303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23755 | /* 65309 */ GIR_RootConstrainSelectedInstOperands, |
| 23756 | /* 65310 */ // GIR_Coverage, 3567, |
| 23757 | /* 65310 */ GIR_EraseRootFromParent_Done, |
| 23758 | /* 65311 */ // Label 2013: @65311 |
| 23759 | /* 65311 */ GIM_Reject, |
| 23760 | /* 65312 */ // Label 2010: @65312 |
| 23761 | /* 65312 */ GIM_Reject, |
| 23762 | /* 65313 */ // Label 2006: @65313 |
| 23763 | /* 65313 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2014*/ GIMT_Encode4(65387), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3674 // |
| 23764 | /* 65320 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm), |
| 23765 | /* 65325 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 23766 | /* 65328 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23767 | /* 65331 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23768 | /* 65334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23769 | /* 65338 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23770 | /* 65342 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23771 | /* 65346 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3928:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 23772 | /* 65346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23773 | /* 65349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23774 | /* 65353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23775 | /* 65358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16), |
| 23776 | /* 65361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23777 | /* 65363 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23778 | /* 65365 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23779 | /* 65367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23780 | /* 65370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23781 | /* 65376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23782 | /* 65382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23783 | /* 65385 */ GIR_RootConstrainSelectedInstOperands, |
| 23784 | /* 65386 */ // GIR_Coverage, 3674, |
| 23785 | /* 65386 */ GIR_EraseRootFromParent_Done, |
| 23786 | /* 65387 */ // Label 2014: @65387 |
| 23787 | /* 65387 */ GIM_Try, /*On fail goto*//*Label 2015*/ GIMT_Encode4(65555), |
| 23788 | /* 65392 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm), |
| 23789 | /* 65397 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2018*/ GIMT_Encode4(65554), |
| 23790 | /* 65408 */ /*GILLT_v8s16*//*Label 2016*/ GIMT_Encode4(65420), GIMT_Encode4(0), |
| 23791 | /* 65416 */ /*GILLT_v4s32*//*Label 2017*/ GIMT_Encode4(65487), |
| 23792 | /* 65420 */ // Label 2016: @65420 |
| 23793 | /* 65420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2019*/ GIMT_Encode4(65486), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3684 // |
| 23794 | /* 65427 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23795 | /* 65430 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23796 | /* 65433 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23797 | /* 65437 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23798 | /* 65441 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23799 | /* 65445 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3931:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 23800 | /* 65445 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23801 | /* 65448 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23802 | /* 65452 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23803 | /* 65457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16), |
| 23804 | /* 65460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23805 | /* 65462 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23806 | /* 65464 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23807 | /* 65466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23808 | /* 65469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23809 | /* 65475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23810 | /* 65481 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23811 | /* 65484 */ GIR_RootConstrainSelectedInstOperands, |
| 23812 | /* 65485 */ // GIR_Coverage, 3684, |
| 23813 | /* 65485 */ GIR_EraseRootFromParent_Done, |
| 23814 | /* 65486 */ // Label 2019: @65486 |
| 23815 | /* 65486 */ GIM_Reject, |
| 23816 | /* 65487 */ // Label 2017: @65487 |
| 23817 | /* 65487 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2020*/ GIMT_Encode4(65553), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3679 // |
| 23818 | /* 65494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23819 | /* 65497 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23820 | /* 65500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23821 | /* 65504 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23822 | /* 65508 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23823 | /* 65512 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3931:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 23824 | /* 65512 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23825 | /* 65515 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23826 | /* 65519 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23827 | /* 65524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32), |
| 23828 | /* 65527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23829 | /* 65529 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23830 | /* 65531 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23831 | /* 65533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23832 | /* 65536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23833 | /* 65542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23834 | /* 65548 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23835 | /* 65551 */ GIR_RootConstrainSelectedInstOperands, |
| 23836 | /* 65552 */ // GIR_Coverage, 3679, |
| 23837 | /* 65552 */ GIR_EraseRootFromParent_Done, |
| 23838 | /* 65553 */ // Label 2020: @65553 |
| 23839 | /* 65553 */ GIM_Reject, |
| 23840 | /* 65554 */ // Label 2018: @65554 |
| 23841 | /* 65554 */ GIM_Reject, |
| 23842 | /* 65555 */ // Label 2015: @65555 |
| 23843 | /* 65555 */ GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(65798), |
| 23844 | /* 65560 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh), |
| 23845 | /* 65565 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2025*/ GIMT_Encode4(65797), |
| 23846 | /* 65576 */ /*GILLT_v16s8*//*Label 2022*/ GIMT_Encode4(65596), GIMT_Encode4(0), |
| 23847 | /* 65584 */ /*GILLT_v8s16*//*Label 2023*/ GIMT_Encode4(65663), GIMT_Encode4(0), |
| 23848 | /* 65592 */ /*GILLT_v4s32*//*Label 2024*/ GIMT_Encode4(65730), |
| 23849 | /* 65596 */ // Label 2022: @65596 |
| 23850 | /* 65596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2026*/ GIMT_Encode4(65662), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3864 // |
| 23851 | /* 65603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23852 | /* 65606 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23853 | /* 65609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23854 | /* 65613 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23855 | /* 65617 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23856 | /* 65621 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3951:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23857 | /* 65621 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23858 | /* 65624 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23859 | /* 65628 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23860 | /* 65633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi8), |
| 23861 | /* 65636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23862 | /* 65638 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23863 | /* 65640 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23864 | /* 65642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23865 | /* 65645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23866 | /* 65651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23867 | /* 65657 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23868 | /* 65660 */ GIR_RootConstrainSelectedInstOperands, |
| 23869 | /* 65661 */ // GIR_Coverage, 3864, |
| 23870 | /* 65661 */ GIR_EraseRootFromParent_Done, |
| 23871 | /* 65662 */ // Label 2026: @65662 |
| 23872 | /* 65662 */ GIM_Reject, |
| 23873 | /* 65663 */ // Label 2023: @65663 |
| 23874 | /* 65663 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2027*/ GIMT_Encode4(65729), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3871 // |
| 23875 | /* 65670 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23876 | /* 65673 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23877 | /* 65676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23878 | /* 65680 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23879 | /* 65684 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23880 | /* 65688 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3951:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23881 | /* 65688 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23882 | /* 65691 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23883 | /* 65695 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23884 | /* 65700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi16), |
| 23885 | /* 65703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23886 | /* 65705 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23887 | /* 65707 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23888 | /* 65709 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23889 | /* 65712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23890 | /* 65718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23891 | /* 65724 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23892 | /* 65727 */ GIR_RootConstrainSelectedInstOperands, |
| 23893 | /* 65728 */ // GIR_Coverage, 3871, |
| 23894 | /* 65728 */ GIR_EraseRootFromParent_Done, |
| 23895 | /* 65729 */ // Label 2027: @65729 |
| 23896 | /* 65729 */ GIM_Reject, |
| 23897 | /* 65730 */ // Label 2024: @65730 |
| 23898 | /* 65730 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2028*/ GIMT_Encode4(65796), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3875 // |
| 23899 | /* 65737 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23900 | /* 65740 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23901 | /* 65743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23902 | /* 65747 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23903 | /* 65751 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23904 | /* 65755 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3951:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23905 | /* 65755 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23906 | /* 65758 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23907 | /* 65762 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23908 | /* 65767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi32), |
| 23909 | /* 65770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23910 | /* 65772 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23911 | /* 65774 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23912 | /* 65776 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23913 | /* 65779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23914 | /* 65785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23915 | /* 65791 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23916 | /* 65794 */ GIR_RootConstrainSelectedInstOperands, |
| 23917 | /* 65795 */ // GIR_Coverage, 3875, |
| 23918 | /* 65795 */ GIR_EraseRootFromParent_Done, |
| 23919 | /* 65796 */ // Label 2028: @65796 |
| 23920 | /* 65796 */ GIM_Reject, |
| 23921 | /* 65797 */ // Label 2025: @65797 |
| 23922 | /* 65797 */ GIM_Reject, |
| 23923 | /* 65798 */ // Label 2021: @65798 |
| 23924 | /* 65798 */ GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(66041), |
| 23925 | /* 65803 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh), |
| 23926 | /* 65808 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2033*/ GIMT_Encode4(66040), |
| 23927 | /* 65819 */ /*GILLT_v16s8*//*Label 2030*/ GIMT_Encode4(65839), GIMT_Encode4(0), |
| 23928 | /* 65827 */ /*GILLT_v8s16*//*Label 2031*/ GIMT_Encode4(65906), GIMT_Encode4(0), |
| 23929 | /* 65835 */ /*GILLT_v4s32*//*Label 2032*/ GIMT_Encode4(65973), |
| 23930 | /* 65839 */ // Label 2030: @65839 |
| 23931 | /* 65839 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2034*/ GIMT_Encode4(65905), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3877 // |
| 23932 | /* 65846 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 23933 | /* 65849 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 23934 | /* 65852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23935 | /* 65856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23936 | /* 65860 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23937 | /* 65864 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3960:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQRDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 23938 | /* 65864 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23939 | /* 65867 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23940 | /* 65871 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23941 | /* 65876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi8), |
| 23942 | /* 65879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23943 | /* 65881 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23944 | /* 65883 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23945 | /* 65885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23946 | /* 65888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23947 | /* 65894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23948 | /* 65900 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23949 | /* 65903 */ GIR_RootConstrainSelectedInstOperands, |
| 23950 | /* 65904 */ // GIR_Coverage, 3877, |
| 23951 | /* 65904 */ GIR_EraseRootFromParent_Done, |
| 23952 | /* 65905 */ // Label 2034: @65905 |
| 23953 | /* 65905 */ GIM_Reject, |
| 23954 | /* 65906 */ // Label 2031: @65906 |
| 23955 | /* 65906 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2035*/ GIMT_Encode4(65972), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3879 // |
| 23956 | /* 65913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 23957 | /* 65916 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 23958 | /* 65919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23959 | /* 65923 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23960 | /* 65927 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23961 | /* 65931 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3960:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQRDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 23962 | /* 65931 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23963 | /* 65934 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23964 | /* 65938 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23965 | /* 65943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi16), |
| 23966 | /* 65946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23967 | /* 65948 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23968 | /* 65950 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23969 | /* 65952 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23970 | /* 65955 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23971 | /* 65961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23972 | /* 65967 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23973 | /* 65970 */ GIR_RootConstrainSelectedInstOperands, |
| 23974 | /* 65971 */ // GIR_Coverage, 3879, |
| 23975 | /* 65971 */ GIR_EraseRootFromParent_Done, |
| 23976 | /* 65972 */ // Label 2035: @65972 |
| 23977 | /* 65972 */ GIM_Reject, |
| 23978 | /* 65973 */ // Label 2032: @65973 |
| 23979 | /* 65973 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2036*/ GIMT_Encode4(66039), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3881 // |
| 23980 | /* 65980 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 23981 | /* 65983 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 23982 | /* 65986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23983 | /* 65990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23984 | /* 65994 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 23985 | /* 65998 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3960:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQRDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 23986 | /* 65998 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 23987 | /* 66001 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 23988 | /* 66005 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 23989 | /* 66010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi32), |
| 23990 | /* 66013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 23991 | /* 66015 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 23992 | /* 66017 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 23993 | /* 66019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23994 | /* 66022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23995 | /* 66028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 23996 | /* 66034 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 23997 | /* 66037 */ GIR_RootConstrainSelectedInstOperands, |
| 23998 | /* 66038 */ // GIR_Coverage, 3881, |
| 23999 | /* 66038 */ GIR_EraseRootFromParent_Done, |
| 24000 | /* 66039 */ // Label 2036: @66039 |
| 24001 | /* 66039 */ GIM_Reject, |
| 24002 | /* 66040 */ // Label 2033: @66040 |
| 24003 | /* 66040 */ GIM_Reject, |
| 24004 | /* 66041 */ // Label 2029: @66041 |
| 24005 | /* 66041 */ GIM_Try, /*On fail goto*//*Label 2037*/ GIMT_Encode4(66209), |
| 24006 | /* 66046 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmul), |
| 24007 | /* 66051 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2040*/ GIMT_Encode4(66208), |
| 24008 | /* 66062 */ /*GILLT_v8s16*//*Label 2038*/ GIMT_Encode4(66074), GIMT_Encode4(0), |
| 24009 | /* 66070 */ /*GILLT_v4s32*//*Label 2039*/ GIMT_Encode4(66141), |
| 24010 | /* 66074 */ // Label 2038: @66074 |
| 24011 | /* 66074 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2041*/ GIMT_Encode4(66140), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4414 // |
| 24012 | /* 66081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24013 | /* 66084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24014 | /* 66087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24015 | /* 66091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24016 | /* 66095 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24017 | /* 66099 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3941:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 24018 | /* 66099 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24019 | /* 66102 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24020 | /* 66106 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24021 | /* 66111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16), |
| 24022 | /* 66114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24023 | /* 66116 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24024 | /* 66118 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24025 | /* 66120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24026 | /* 66123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24027 | /* 66129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24028 | /* 66135 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24029 | /* 66138 */ GIR_RootConstrainSelectedInstOperands, |
| 24030 | /* 66139 */ // GIR_Coverage, 4414, |
| 24031 | /* 66139 */ GIR_EraseRootFromParent_Done, |
| 24032 | /* 66140 */ // Label 2041: @66140 |
| 24033 | /* 66140 */ GIM_Reject, |
| 24034 | /* 66141 */ // Label 2039: @66141 |
| 24035 | /* 66141 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2042*/ GIMT_Encode4(66207), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4407 // |
| 24036 | /* 66148 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24037 | /* 66151 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24038 | /* 66154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24039 | /* 66158 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24040 | /* 66162 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24041 | /* 66166 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3941:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 24042 | /* 66166 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24043 | /* 66169 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24044 | /* 66173 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24045 | /* 66178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32), |
| 24046 | /* 66181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24047 | /* 66183 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24048 | /* 66185 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24049 | /* 66187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24050 | /* 66190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24051 | /* 66196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24052 | /* 66202 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24053 | /* 66205 */ GIR_RootConstrainSelectedInstOperands, |
| 24054 | /* 66206 */ // GIR_Coverage, 4407, |
| 24055 | /* 66206 */ GIR_EraseRootFromParent_Done, |
| 24056 | /* 66207 */ // Label 2042: @66207 |
| 24057 | /* 66207 */ GIM_Reject, |
| 24058 | /* 66208 */ // Label 2040: @66208 |
| 24059 | /* 66208 */ GIM_Reject, |
| 24060 | /* 66209 */ // Label 2037: @66209 |
| 24061 | /* 66209 */ GIM_Try, /*On fail goto*//*Label 2043*/ GIMT_Encode4(66377), |
| 24062 | /* 66214 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vadd), |
| 24063 | /* 66219 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2046*/ GIMT_Encode4(66376), |
| 24064 | /* 66230 */ /*GILLT_v8s16*//*Label 2044*/ GIMT_Encode4(66242), GIMT_Encode4(0), |
| 24065 | /* 66238 */ /*GILLT_v4s32*//*Label 2045*/ GIMT_Encode4(66309), |
| 24066 | /* 66242 */ // Label 2044: @66242 |
| 24067 | /* 66242 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2047*/ GIMT_Encode4(66308), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4454 // |
| 24068 | /* 66249 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24069 | /* 66252 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24070 | /* 66255 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24071 | /* 66259 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24072 | /* 66263 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24073 | /* 66267 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3878:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 24074 | /* 66267 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24075 | /* 66270 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24076 | /* 66274 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24077 | /* 66279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16), |
| 24078 | /* 66282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24079 | /* 66284 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24080 | /* 66286 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24081 | /* 66288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24082 | /* 66291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24083 | /* 66297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24084 | /* 66303 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24085 | /* 66306 */ GIR_RootConstrainSelectedInstOperands, |
| 24086 | /* 66307 */ // GIR_Coverage, 4454, |
| 24087 | /* 66307 */ GIR_EraseRootFromParent_Done, |
| 24088 | /* 66308 */ // Label 2047: @66308 |
| 24089 | /* 66308 */ GIM_Reject, |
| 24090 | /* 66309 */ // Label 2045: @66309 |
| 24091 | /* 66309 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2048*/ GIMT_Encode4(66375), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4447 // |
| 24092 | /* 66316 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24093 | /* 66319 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24094 | /* 66322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24095 | /* 66326 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24096 | /* 66330 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24097 | /* 66334 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3878:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 24098 | /* 66334 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24099 | /* 66337 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24100 | /* 66341 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24101 | /* 66346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32), |
| 24102 | /* 66349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24103 | /* 66351 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24104 | /* 66353 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24105 | /* 66355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24106 | /* 66358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24107 | /* 66364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24108 | /* 66370 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24109 | /* 66373 */ GIR_RootConstrainSelectedInstOperands, |
| 24110 | /* 66374 */ // GIR_Coverage, 4447, |
| 24111 | /* 66374 */ GIR_EraseRootFromParent_Done, |
| 24112 | /* 66375 */ // Label 2048: @66375 |
| 24113 | /* 66375 */ GIM_Reject, |
| 24114 | /* 66376 */ // Label 2046: @66376 |
| 24115 | /* 66376 */ GIM_Reject, |
| 24116 | /* 66377 */ // Label 2043: @66377 |
| 24117 | /* 66377 */ GIM_Try, /*On fail goto*//*Label 2049*/ GIMT_Encode4(66545), |
| 24118 | /* 66382 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsub), |
| 24119 | /* 66387 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2052*/ GIMT_Encode4(66544), |
| 24120 | /* 66398 */ /*GILLT_v8s16*//*Label 2050*/ GIMT_Encode4(66410), GIMT_Encode4(0), |
| 24121 | /* 66406 */ /*GILLT_v4s32*//*Label 2051*/ GIMT_Encode4(66477), |
| 24122 | /* 66410 */ // Label 2050: @66410 |
| 24123 | /* 66410 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2053*/ GIMT_Encode4(66476), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4468 // |
| 24124 | /* 66417 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24125 | /* 66420 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24126 | /* 66423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24127 | /* 66427 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24128 | /* 66431 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24129 | /* 66435 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4009:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 24130 | /* 66435 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24131 | /* 66438 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24132 | /* 66442 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24133 | /* 66447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16), |
| 24134 | /* 66450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24135 | /* 66452 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24136 | /* 66454 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24137 | /* 66456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24138 | /* 66459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24139 | /* 66465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24140 | /* 66471 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24141 | /* 66474 */ GIR_RootConstrainSelectedInstOperands, |
| 24142 | /* 66475 */ // GIR_Coverage, 4468, |
| 24143 | /* 66475 */ GIR_EraseRootFromParent_Done, |
| 24144 | /* 66476 */ // Label 2053: @66476 |
| 24145 | /* 66476 */ GIM_Reject, |
| 24146 | /* 66477 */ // Label 2051: @66477 |
| 24147 | /* 66477 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2054*/ GIMT_Encode4(66543), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4461 // |
| 24148 | /* 66484 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24149 | /* 66487 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24150 | /* 66490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24151 | /* 66494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24152 | /* 66498 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24153 | /* 66502 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4009:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 24154 | /* 66502 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24155 | /* 66505 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24156 | /* 66509 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24157 | /* 66514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32), |
| 24158 | /* 66517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24159 | /* 66519 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 24160 | /* 66521 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 24161 | /* 66523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24162 | /* 66526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24163 | /* 66532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24164 | /* 66538 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24165 | /* 66541 */ GIR_RootConstrainSelectedInstOperands, |
| 24166 | /* 66542 */ // GIR_Coverage, 4461, |
| 24167 | /* 66542 */ GIR_EraseRootFromParent_Done, |
| 24168 | /* 66543 */ // Label 2054: @66543 |
| 24169 | /* 66543 */ GIM_Reject, |
| 24170 | /* 66544 */ // Label 2052: @66544 |
| 24171 | /* 66544 */ GIM_Reject, |
| 24172 | /* 66545 */ // Label 2049: @66545 |
| 24173 | /* 66545 */ GIM_Try, /*On fail goto*//*Label 2055*/ GIMT_Encode4(66685), |
| 24174 | /* 66550 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_eq), |
| 24175 | /* 66555 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2058*/ GIMT_Encode4(66684), |
| 24176 | /* 66566 */ /*GILLT_v4s1*//*Label 2056*/ GIMT_Encode4(66574), |
| 24177 | /* 66570 */ /*GILLT_v8s1*//*Label 2057*/ GIMT_Encode4(66629), |
| 24178 | /* 66574 */ // Label 2056: @66574 |
| 24179 | /* 66574 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2059*/ GIMT_Encode4(66628), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4594 // |
| 24180 | /* 66581 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24181 | /* 66584 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24182 | /* 66587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24183 | /* 66591 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24184 | /* 66595 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24185 | /* 66599 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3810:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 0:{ *:[i32] }) |
| 24186 | /* 66599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 24187 | /* 66602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24188 | /* 66604 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24189 | /* 66606 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24190 | /* 66608 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24191 | /* 66611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24192 | /* 66614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24193 | /* 66620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24194 | /* 66626 */ GIR_RootConstrainSelectedInstOperands, |
| 24195 | /* 66627 */ // GIR_Coverage, 4594, |
| 24196 | /* 66627 */ GIR_EraseRootFromParent_Done, |
| 24197 | /* 66628 */ // Label 2059: @66628 |
| 24198 | /* 66628 */ GIM_Reject, |
| 24199 | /* 66629 */ // Label 2057: @66629 |
| 24200 | /* 66629 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2060*/ GIMT_Encode4(66683), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4592 // |
| 24201 | /* 66636 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24202 | /* 66639 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24203 | /* 66642 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24204 | /* 66646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24205 | /* 66650 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24206 | /* 66654 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3810:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 0:{ *:[i32] }) |
| 24207 | /* 66654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 24208 | /* 66657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24209 | /* 66659 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24210 | /* 66661 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24211 | /* 66663 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24212 | /* 66666 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24213 | /* 66669 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24214 | /* 66675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24215 | /* 66681 */ GIR_RootConstrainSelectedInstOperands, |
| 24216 | /* 66682 */ // GIR_Coverage, 4592, |
| 24217 | /* 66682 */ GIR_EraseRootFromParent_Done, |
| 24218 | /* 66683 */ // Label 2060: @66683 |
| 24219 | /* 66683 */ GIM_Reject, |
| 24220 | /* 66684 */ // Label 2058: @66684 |
| 24221 | /* 66684 */ GIM_Reject, |
| 24222 | /* 66685 */ // Label 2055: @66685 |
| 24223 | /* 66685 */ GIM_Try, /*On fail goto*//*Label 2061*/ GIMT_Encode4(66825), |
| 24224 | /* 66690 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ne), |
| 24225 | /* 66695 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2064*/ GIMT_Encode4(66824), |
| 24226 | /* 66706 */ /*GILLT_v4s1*//*Label 2062*/ GIMT_Encode4(66714), |
| 24227 | /* 66710 */ /*GILLT_v8s1*//*Label 2063*/ GIMT_Encode4(66769), |
| 24228 | /* 66714 */ // Label 2062: @66714 |
| 24229 | /* 66714 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2065*/ GIMT_Encode4(66768), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4683 // |
| 24230 | /* 66721 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24231 | /* 66724 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24232 | /* 66727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24233 | /* 66731 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24234 | /* 66735 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24235 | /* 66739 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3815:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 1:{ *:[i32] }) |
| 24236 | /* 66739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 24237 | /* 66742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24238 | /* 66744 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24239 | /* 66746 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24240 | /* 66748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 24241 | /* 66751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24242 | /* 66754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24243 | /* 66760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24244 | /* 66766 */ GIR_RootConstrainSelectedInstOperands, |
| 24245 | /* 66767 */ // GIR_Coverage, 4683, |
| 24246 | /* 66767 */ GIR_EraseRootFromParent_Done, |
| 24247 | /* 66768 */ // Label 2065: @66768 |
| 24248 | /* 66768 */ GIM_Reject, |
| 24249 | /* 66769 */ // Label 2063: @66769 |
| 24250 | /* 66769 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2066*/ GIMT_Encode4(66823), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4681 // |
| 24251 | /* 66776 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24252 | /* 66779 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24253 | /* 66782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24254 | /* 66786 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24255 | /* 66790 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24256 | /* 66794 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3815:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 1:{ *:[i32] }) |
| 24257 | /* 66794 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 24258 | /* 66797 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24259 | /* 66799 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24260 | /* 66801 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24261 | /* 66803 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 24262 | /* 66806 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24263 | /* 66809 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24264 | /* 66815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24265 | /* 66821 */ GIR_RootConstrainSelectedInstOperands, |
| 24266 | /* 66822 */ // GIR_Coverage, 4681, |
| 24267 | /* 66822 */ GIR_EraseRootFromParent_Done, |
| 24268 | /* 66823 */ // Label 2066: @66823 |
| 24269 | /* 66823 */ GIM_Reject, |
| 24270 | /* 66824 */ // Label 2064: @66824 |
| 24271 | /* 66824 */ GIM_Reject, |
| 24272 | /* 66825 */ // Label 2061: @66825 |
| 24273 | /* 66825 */ GIM_Try, /*On fail goto*//*Label 2067*/ GIMT_Encode4(66965), |
| 24274 | /* 66830 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ge), |
| 24275 | /* 66835 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2070*/ GIMT_Encode4(66964), |
| 24276 | /* 66846 */ /*GILLT_v4s1*//*Label 2068*/ GIMT_Encode4(66854), |
| 24277 | /* 66850 */ /*GILLT_v8s1*//*Label 2069*/ GIMT_Encode4(66909), |
| 24278 | /* 66854 */ // Label 2068: @66854 |
| 24279 | /* 66854 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2071*/ GIMT_Encode4(66908), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4699 // |
| 24280 | /* 66861 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24281 | /* 66864 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24282 | /* 66867 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24283 | /* 66871 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24284 | /* 66875 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24285 | /* 66879 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3811:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 10:{ *:[i32] }) |
| 24286 | /* 66879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 24287 | /* 66882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24288 | /* 66884 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24289 | /* 66886 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24290 | /* 66888 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/10, |
| 24291 | /* 66891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24292 | /* 66894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24293 | /* 66900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24294 | /* 66906 */ GIR_RootConstrainSelectedInstOperands, |
| 24295 | /* 66907 */ // GIR_Coverage, 4699, |
| 24296 | /* 66907 */ GIR_EraseRootFromParent_Done, |
| 24297 | /* 66908 */ // Label 2071: @66908 |
| 24298 | /* 66908 */ GIM_Reject, |
| 24299 | /* 66909 */ // Label 2069: @66909 |
| 24300 | /* 66909 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2072*/ GIMT_Encode4(66963), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4697 // |
| 24301 | /* 66916 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24302 | /* 66919 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24303 | /* 66922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24304 | /* 66926 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24305 | /* 66930 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24306 | /* 66934 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3811:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 10:{ *:[i32] }) |
| 24307 | /* 66934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 24308 | /* 66937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24309 | /* 66939 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24310 | /* 66941 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24311 | /* 66943 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/10, |
| 24312 | /* 66946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24313 | /* 66949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24314 | /* 66955 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24315 | /* 66961 */ GIR_RootConstrainSelectedInstOperands, |
| 24316 | /* 66962 */ // GIR_Coverage, 4697, |
| 24317 | /* 66962 */ GIR_EraseRootFromParent_Done, |
| 24318 | /* 66963 */ // Label 2072: @66963 |
| 24319 | /* 66963 */ GIM_Reject, |
| 24320 | /* 66964 */ // Label 2070: @66964 |
| 24321 | /* 66964 */ GIM_Reject, |
| 24322 | /* 66965 */ // Label 2067: @66965 |
| 24323 | /* 66965 */ GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(67105), |
| 24324 | /* 66970 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_lt), |
| 24325 | /* 66975 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2076*/ GIMT_Encode4(67104), |
| 24326 | /* 66986 */ /*GILLT_v4s1*//*Label 2074*/ GIMT_Encode4(66994), |
| 24327 | /* 66990 */ /*GILLT_v8s1*//*Label 2075*/ GIMT_Encode4(67049), |
| 24328 | /* 66994 */ // Label 2074: @66994 |
| 24329 | /* 66994 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2077*/ GIMT_Encode4(67048), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4715 // |
| 24330 | /* 67001 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24331 | /* 67004 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24332 | /* 67007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24333 | /* 67011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24334 | /* 67015 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24335 | /* 67019 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3814:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 11:{ *:[i32] }) |
| 24336 | /* 67019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 24337 | /* 67022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24338 | /* 67024 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24339 | /* 67026 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24340 | /* 67028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/11, |
| 24341 | /* 67031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24342 | /* 67034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24343 | /* 67040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24344 | /* 67046 */ GIR_RootConstrainSelectedInstOperands, |
| 24345 | /* 67047 */ // GIR_Coverage, 4715, |
| 24346 | /* 67047 */ GIR_EraseRootFromParent_Done, |
| 24347 | /* 67048 */ // Label 2077: @67048 |
| 24348 | /* 67048 */ GIM_Reject, |
| 24349 | /* 67049 */ // Label 2075: @67049 |
| 24350 | /* 67049 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2078*/ GIMT_Encode4(67103), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4713 // |
| 24351 | /* 67056 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24352 | /* 67059 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24353 | /* 67062 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24354 | /* 67066 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24355 | /* 67070 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24356 | /* 67074 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3814:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 11:{ *:[i32] }) |
| 24357 | /* 67074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 24358 | /* 67077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24359 | /* 67079 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24360 | /* 67081 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24361 | /* 67083 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/11, |
| 24362 | /* 67086 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24363 | /* 67089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24364 | /* 67095 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24365 | /* 67101 */ GIR_RootConstrainSelectedInstOperands, |
| 24366 | /* 67102 */ // GIR_Coverage, 4713, |
| 24367 | /* 67102 */ GIR_EraseRootFromParent_Done, |
| 24368 | /* 67103 */ // Label 2078: @67103 |
| 24369 | /* 67103 */ GIM_Reject, |
| 24370 | /* 67104 */ // Label 2076: @67104 |
| 24371 | /* 67104 */ GIM_Reject, |
| 24372 | /* 67105 */ // Label 2073: @67105 |
| 24373 | /* 67105 */ GIM_Try, /*On fail goto*//*Label 2079*/ GIMT_Encode4(67245), |
| 24374 | /* 67110 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_gt), |
| 24375 | /* 67115 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2082*/ GIMT_Encode4(67244), |
| 24376 | /* 67126 */ /*GILLT_v4s1*//*Label 2080*/ GIMT_Encode4(67134), |
| 24377 | /* 67130 */ /*GILLT_v8s1*//*Label 2081*/ GIMT_Encode4(67189), |
| 24378 | /* 67134 */ // Label 2080: @67134 |
| 24379 | /* 67134 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2083*/ GIMT_Encode4(67188), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4731 // |
| 24380 | /* 67141 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24381 | /* 67144 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24382 | /* 67147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24383 | /* 67151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24384 | /* 67155 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24385 | /* 67159 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3812:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 12:{ *:[i32] }) |
| 24386 | /* 67159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 24387 | /* 67162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24388 | /* 67164 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24389 | /* 67166 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24390 | /* 67168 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/12, |
| 24391 | /* 67171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24392 | /* 67174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24393 | /* 67180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24394 | /* 67186 */ GIR_RootConstrainSelectedInstOperands, |
| 24395 | /* 67187 */ // GIR_Coverage, 4731, |
| 24396 | /* 67187 */ GIR_EraseRootFromParent_Done, |
| 24397 | /* 67188 */ // Label 2083: @67188 |
| 24398 | /* 67188 */ GIM_Reject, |
| 24399 | /* 67189 */ // Label 2081: @67189 |
| 24400 | /* 67189 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2084*/ GIMT_Encode4(67243), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4729 // |
| 24401 | /* 67196 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24402 | /* 67199 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24403 | /* 67202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24404 | /* 67206 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24405 | /* 67210 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24406 | /* 67214 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3812:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 12:{ *:[i32] }) |
| 24407 | /* 67214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 24408 | /* 67217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24409 | /* 67219 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24410 | /* 67221 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24411 | /* 67223 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/12, |
| 24412 | /* 67226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24413 | /* 67229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24414 | /* 67235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24415 | /* 67241 */ GIR_RootConstrainSelectedInstOperands, |
| 24416 | /* 67242 */ // GIR_Coverage, 4729, |
| 24417 | /* 67242 */ GIR_EraseRootFromParent_Done, |
| 24418 | /* 67243 */ // Label 2084: @67243 |
| 24419 | /* 67243 */ GIM_Reject, |
| 24420 | /* 67244 */ // Label 2082: @67244 |
| 24421 | /* 67244 */ GIM_Reject, |
| 24422 | /* 67245 */ // Label 2079: @67245 |
| 24423 | /* 67245 */ GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(67385), |
| 24424 | /* 67250 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_le), |
| 24425 | /* 67255 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2088*/ GIMT_Encode4(67384), |
| 24426 | /* 67266 */ /*GILLT_v4s1*//*Label 2086*/ GIMT_Encode4(67274), |
| 24427 | /* 67270 */ /*GILLT_v8s1*//*Label 2087*/ GIMT_Encode4(67329), |
| 24428 | /* 67274 */ // Label 2086: @67274 |
| 24429 | /* 67274 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2089*/ GIMT_Encode4(67328), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4747 // |
| 24430 | /* 67281 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24431 | /* 67284 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 24432 | /* 67287 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24433 | /* 67291 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24434 | /* 67295 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24435 | /* 67299 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3813:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 13:{ *:[i32] }) |
| 24436 | /* 67299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32), |
| 24437 | /* 67302 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24438 | /* 67304 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24439 | /* 67306 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24440 | /* 67308 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/13, |
| 24441 | /* 67311 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24442 | /* 67314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24443 | /* 67320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24444 | /* 67326 */ GIR_RootConstrainSelectedInstOperands, |
| 24445 | /* 67327 */ // GIR_Coverage, 4747, |
| 24446 | /* 67327 */ GIR_EraseRootFromParent_Done, |
| 24447 | /* 67328 */ // Label 2089: @67328 |
| 24448 | /* 67328 */ GIM_Reject, |
| 24449 | /* 67329 */ // Label 2087: @67329 |
| 24450 | /* 67329 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2090*/ GIMT_Encode4(67383), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4745 // |
| 24451 | /* 67336 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24452 | /* 67339 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24453 | /* 67342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 24454 | /* 67346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24455 | /* 67350 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24456 | /* 67354 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3813:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 13:{ *:[i32] }) |
| 24457 | /* 67354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16), |
| 24458 | /* 67357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 24459 | /* 67359 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 24460 | /* 67361 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 24461 | /* 67363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/13, |
| 24462 | /* 67366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24463 | /* 67369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24464 | /* 67375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24465 | /* 67381 */ GIR_RootConstrainSelectedInstOperands, |
| 24466 | /* 67382 */ // GIR_Coverage, 4745, |
| 24467 | /* 67382 */ GIR_EraseRootFromParent_Done, |
| 24468 | /* 67383 */ // Label 2090: @67383 |
| 24469 | /* 67383 */ GIM_Reject, |
| 24470 | /* 67384 */ // Label 2088: @67384 |
| 24471 | /* 67384 */ GIM_Reject, |
| 24472 | /* 67385 */ // Label 2085: @67385 |
| 24473 | /* 67385 */ GIM_Try, /*On fail goto*//*Label 2091*/ GIMT_Encode4(67736), |
| 24474 | /* 67390 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr), |
| 24475 | /* 67395 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2095*/ GIMT_Encode4(67735), |
| 24476 | /* 67406 */ /*GILLT_v16s8*//*Label 2092*/ GIMT_Encode4(67426), GIMT_Encode4(0), |
| 24477 | /* 67414 */ /*GILLT_v8s16*//*Label 2093*/ GIMT_Encode4(67493), GIMT_Encode4(0), |
| 24478 | /* 67422 */ /*GILLT_v4s32*//*Label 2094*/ GIMT_Encode4(67614), |
| 24479 | /* 67426 */ // Label 2092: @67426 |
| 24480 | /* 67426 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2096*/ GIMT_Encode4(67492), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5269 // |
| 24481 | /* 67433 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24482 | /* 67436 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24483 | /* 67439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24484 | /* 67443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24485 | /* 67447 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24486 | /* 67451 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3879:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 24487 | /* 67451 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24488 | /* 67454 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24489 | /* 67458 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24490 | /* 67463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8), |
| 24491 | /* 67466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24492 | /* 67468 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 24493 | /* 67470 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24494 | /* 67472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24495 | /* 67475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24496 | /* 67481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24497 | /* 67487 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24498 | /* 67490 */ GIR_RootConstrainSelectedInstOperands, |
| 24499 | /* 67491 */ // GIR_Coverage, 5269, |
| 24500 | /* 67491 */ GIR_EraseRootFromParent_Done, |
| 24501 | /* 67492 */ // Label 2096: @67492 |
| 24502 | /* 67492 */ GIM_Reject, |
| 24503 | /* 67493 */ // Label 2093: @67493 |
| 24504 | /* 67493 */ GIM_Try, /*On fail goto*//*Label 2097*/ GIMT_Encode4(67613), |
| 24505 | /* 67498 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24506 | /* 67501 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24507 | /* 67504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24508 | /* 67508 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24509 | /* 67512 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24510 | /* 67516 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2098*/ GIMT_Encode4(67564), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5274 // |
| 24511 | /* 67523 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3879:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 24512 | /* 67523 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24513 | /* 67526 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24514 | /* 67530 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24515 | /* 67535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16), |
| 24516 | /* 67538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24517 | /* 67540 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 24518 | /* 67542 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24519 | /* 67544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24520 | /* 67547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24521 | /* 67553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24522 | /* 67559 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24523 | /* 67562 */ GIR_RootConstrainSelectedInstOperands, |
| 24524 | /* 67563 */ // GIR_Coverage, 5274, |
| 24525 | /* 67563 */ GIR_EraseRootFromParent_Done, |
| 24526 | /* 67564 */ // Label 2098: @67564 |
| 24527 | /* 67564 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2099*/ GIMT_Encode4(67612), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5278 // |
| 24528 | /* 67571 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3879:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 24529 | /* 67571 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24530 | /* 67574 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24531 | /* 67578 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24532 | /* 67583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16), |
| 24533 | /* 67586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24534 | /* 67588 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 24535 | /* 67590 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24536 | /* 67592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24537 | /* 67595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24538 | /* 67601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24539 | /* 67607 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24540 | /* 67610 */ GIR_RootConstrainSelectedInstOperands, |
| 24541 | /* 67611 */ // GIR_Coverage, 5278, |
| 24542 | /* 67611 */ GIR_EraseRootFromParent_Done, |
| 24543 | /* 67612 */ // Label 2099: @67612 |
| 24544 | /* 67612 */ GIM_Reject, |
| 24545 | /* 67613 */ // Label 2097: @67613 |
| 24546 | /* 67613 */ GIM_Reject, |
| 24547 | /* 67614 */ // Label 2094: @67614 |
| 24548 | /* 67614 */ GIM_Try, /*On fail goto*//*Label 2100*/ GIMT_Encode4(67734), |
| 24549 | /* 67619 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24550 | /* 67622 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24551 | /* 67625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24552 | /* 67629 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24553 | /* 67633 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 24554 | /* 67637 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2101*/ GIMT_Encode4(67685), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5276 // |
| 24555 | /* 67644 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3879:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 24556 | /* 67644 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24557 | /* 67647 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24558 | /* 67651 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24559 | /* 67656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32), |
| 24560 | /* 67659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24561 | /* 67661 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 24562 | /* 67663 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24563 | /* 67665 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24564 | /* 67668 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24565 | /* 67674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24566 | /* 67680 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24567 | /* 67683 */ GIR_RootConstrainSelectedInstOperands, |
| 24568 | /* 67684 */ // GIR_Coverage, 5276, |
| 24569 | /* 67684 */ GIR_EraseRootFromParent_Done, |
| 24570 | /* 67685 */ // Label 2101: @67685 |
| 24571 | /* 67685 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2102*/ GIMT_Encode4(67733), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5280 // |
| 24572 | /* 67692 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3879:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm) |
| 24573 | /* 67692 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24574 | /* 67695 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24575 | /* 67699 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24576 | /* 67704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32), |
| 24577 | /* 67707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24578 | /* 67709 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 24579 | /* 67711 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 24580 | /* 67713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24581 | /* 67716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24582 | /* 67722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24583 | /* 67728 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24584 | /* 67731 */ GIR_RootConstrainSelectedInstOperands, |
| 24585 | /* 67732 */ // GIR_Coverage, 5280, |
| 24586 | /* 67732 */ GIR_EraseRootFromParent_Done, |
| 24587 | /* 67733 */ // Label 2102: @67733 |
| 24588 | /* 67733 */ GIM_Reject, |
| 24589 | /* 67734 */ // Label 2100: @67734 |
| 24590 | /* 67734 */ GIM_Reject, |
| 24591 | /* 67735 */ // Label 2095: @67735 |
| 24592 | /* 67735 */ GIM_Reject, |
| 24593 | /* 67736 */ // Label 2091: @67736 |
| 24594 | /* 67736 */ GIM_Reject, |
| 24595 | /* 67737 */ // Label 1359: @67737 |
| 24596 | /* 67737 */ GIM_Try, /*On fail goto*//*Label 2103*/ GIMT_Encode4(78150), |
| 24597 | /* 67742 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 24598 | /* 67745 */ GIM_Try, /*On fail goto*//*Label 2104*/ GIMT_Encode4(68249), |
| 24599 | /* 67750 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm), |
| 24600 | /* 67755 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2108*/ GIMT_Encode4(68248), |
| 24601 | /* 67766 */ /*GILLT_v16s8*//*Label 2105*/ GIMT_Encode4(67786), GIMT_Encode4(0), |
| 24602 | /* 67774 */ /*GILLT_v8s16*//*Label 2106*/ GIMT_Encode4(67940), GIMT_Encode4(0), |
| 24603 | /* 67782 */ /*GILLT_v4s32*//*Label 2107*/ GIMT_Encode4(68094), |
| 24604 | /* 67786 */ // Label 2105: @67786 |
| 24605 | /* 67786 */ GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(67939), |
| 24606 | /* 67791 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24607 | /* 67794 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24608 | /* 67797 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24609 | /* 67800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24610 | /* 67804 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24611 | /* 67808 */ GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(67873), // Rule ID 4310 // |
| 24612 | /* 67813 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24613 | /* 67817 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24614 | /* 67821 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 24615 | /* 67825 */ // MIs[1] Operand 1 |
| 24616 | /* 67825 */ // No operand predicates |
| 24617 | /* 67825 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24618 | /* 67829 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24619 | /* 67831 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 24620 | /* 67831 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24621 | /* 67834 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24622 | /* 67838 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24623 | /* 67843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms8), |
| 24624 | /* 67846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24625 | /* 67848 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24626 | /* 67850 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24627 | /* 67853 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24628 | /* 67856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24629 | /* 67862 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24630 | /* 67868 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24631 | /* 67871 */ GIR_RootConstrainSelectedInstOperands, |
| 24632 | /* 67872 */ // GIR_Coverage, 4310, |
| 24633 | /* 67872 */ GIR_EraseRootFromParent_Done, |
| 24634 | /* 67873 */ // Label 2110: @67873 |
| 24635 | /* 67873 */ GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(67938), // Rule ID 4312 // |
| 24636 | /* 67878 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24637 | /* 67882 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24638 | /* 67886 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7), |
| 24639 | /* 67890 */ // MIs[1] Operand 1 |
| 24640 | /* 67890 */ // No operand predicates |
| 24641 | /* 67890 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24642 | /* 67894 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24643 | /* 67896 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3961:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) |
| 24644 | /* 67896 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24645 | /* 67899 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24646 | /* 67903 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24647 | /* 67908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu8), |
| 24648 | /* 67911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24649 | /* 67913 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24650 | /* 67915 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24651 | /* 67918 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24652 | /* 67921 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24653 | /* 67927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24654 | /* 67933 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24655 | /* 67936 */ GIR_RootConstrainSelectedInstOperands, |
| 24656 | /* 67937 */ // GIR_Coverage, 4312, |
| 24657 | /* 67937 */ GIR_EraseRootFromParent_Done, |
| 24658 | /* 67938 */ // Label 2111: @67938 |
| 24659 | /* 67938 */ GIM_Reject, |
| 24660 | /* 67939 */ // Label 2109: @67939 |
| 24661 | /* 67939 */ GIM_Reject, |
| 24662 | /* 67940 */ // Label 2106: @67940 |
| 24663 | /* 67940 */ GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(68093), |
| 24664 | /* 67945 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24665 | /* 67948 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24666 | /* 67951 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24667 | /* 67954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24668 | /* 67958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24669 | /* 67962 */ GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(68027), // Rule ID 4314 // |
| 24670 | /* 67967 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24671 | /* 67971 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24672 | /* 67975 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 24673 | /* 67979 */ // MIs[1] Operand 1 |
| 24674 | /* 67979 */ // No operand predicates |
| 24675 | /* 67979 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24676 | /* 67983 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24677 | /* 67985 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 24678 | /* 67985 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24679 | /* 67988 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24680 | /* 67992 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24681 | /* 67997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms16), |
| 24682 | /* 68000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24683 | /* 68002 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24684 | /* 68004 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24685 | /* 68007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24686 | /* 68010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24687 | /* 68016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24688 | /* 68022 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24689 | /* 68025 */ GIR_RootConstrainSelectedInstOperands, |
| 24690 | /* 68026 */ // GIR_Coverage, 4314, |
| 24691 | /* 68026 */ GIR_EraseRootFromParent_Done, |
| 24692 | /* 68027 */ // Label 2113: @68027 |
| 24693 | /* 68027 */ GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(68092), // Rule ID 4316 // |
| 24694 | /* 68032 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24695 | /* 68036 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24696 | /* 68040 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 24697 | /* 68044 */ // MIs[1] Operand 1 |
| 24698 | /* 68044 */ // No operand predicates |
| 24699 | /* 68044 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24700 | /* 68048 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24701 | /* 68050 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3961:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) |
| 24702 | /* 68050 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24703 | /* 68053 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24704 | /* 68057 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24705 | /* 68062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu16), |
| 24706 | /* 68065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24707 | /* 68067 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24708 | /* 68069 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24709 | /* 68072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24710 | /* 68075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24711 | /* 68081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24712 | /* 68087 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24713 | /* 68090 */ GIR_RootConstrainSelectedInstOperands, |
| 24714 | /* 68091 */ // GIR_Coverage, 4316, |
| 24715 | /* 68091 */ GIR_EraseRootFromParent_Done, |
| 24716 | /* 68092 */ // Label 2114: @68092 |
| 24717 | /* 68092 */ GIM_Reject, |
| 24718 | /* 68093 */ // Label 2112: @68093 |
| 24719 | /* 68093 */ GIM_Reject, |
| 24720 | /* 68094 */ // Label 2107: @68094 |
| 24721 | /* 68094 */ GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(68247), |
| 24722 | /* 68099 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24723 | /* 68102 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24724 | /* 68105 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24725 | /* 68108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24726 | /* 68112 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24727 | /* 68116 */ GIM_Try, /*On fail goto*//*Label 2116*/ GIMT_Encode4(68181), // Rule ID 4318 // |
| 24728 | /* 68121 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24729 | /* 68125 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24730 | /* 68129 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 24731 | /* 68133 */ // MIs[1] Operand 1 |
| 24732 | /* 68133 */ // No operand predicates |
| 24733 | /* 68133 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24734 | /* 68137 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24735 | /* 68139 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3961:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 24736 | /* 68139 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24737 | /* 68142 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24738 | /* 68146 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24739 | /* 68151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms32), |
| 24740 | /* 68154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24741 | /* 68156 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24742 | /* 68158 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24743 | /* 68161 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24744 | /* 68164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24745 | /* 68170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24746 | /* 68176 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24747 | /* 68179 */ GIR_RootConstrainSelectedInstOperands, |
| 24748 | /* 68180 */ // GIR_Coverage, 4318, |
| 24749 | /* 68180 */ GIR_EraseRootFromParent_Done, |
| 24750 | /* 68181 */ // Label 2116: @68181 |
| 24751 | /* 68181 */ GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(68246), // Rule ID 4320 // |
| 24752 | /* 68186 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24753 | /* 68190 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24754 | /* 68194 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31), |
| 24755 | /* 68198 */ // MIs[1] Operand 1 |
| 24756 | /* 68198 */ // No operand predicates |
| 24757 | /* 68198 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24758 | /* 68202 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24759 | /* 68204 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3961:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) |
| 24760 | /* 68204 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24761 | /* 68207 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24762 | /* 68211 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24763 | /* 68216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu32), |
| 24764 | /* 68219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24765 | /* 68221 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24766 | /* 68223 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24767 | /* 68226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24768 | /* 68229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24769 | /* 68235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24770 | /* 68241 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24771 | /* 68244 */ GIR_RootConstrainSelectedInstOperands, |
| 24772 | /* 68245 */ // GIR_Coverage, 4320, |
| 24773 | /* 68245 */ GIR_EraseRootFromParent_Done, |
| 24774 | /* 68246 */ // Label 2117: @68246 |
| 24775 | /* 68246 */ GIM_Reject, |
| 24776 | /* 68247 */ // Label 2115: @68247 |
| 24777 | /* 68247 */ GIM_Reject, |
| 24778 | /* 68248 */ // Label 2108: @68248 |
| 24779 | /* 68248 */ GIM_Reject, |
| 24780 | /* 68249 */ // Label 2104: @68249 |
| 24781 | /* 68249 */ GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(68753), |
| 24782 | /* 68254 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm), |
| 24783 | /* 68259 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2122*/ GIMT_Encode4(68752), |
| 24784 | /* 68270 */ /*GILLT_v16s8*//*Label 2119*/ GIMT_Encode4(68290), GIMT_Encode4(0), |
| 24785 | /* 68278 */ /*GILLT_v8s16*//*Label 2120*/ GIMT_Encode4(68444), GIMT_Encode4(0), |
| 24786 | /* 68286 */ /*GILLT_v4s32*//*Label 2121*/ GIMT_Encode4(68598), |
| 24787 | /* 68290 */ // Label 2119: @68290 |
| 24788 | /* 68290 */ GIM_Try, /*On fail goto*//*Label 2123*/ GIMT_Encode4(68443), |
| 24789 | /* 68295 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 24790 | /* 68298 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24791 | /* 68301 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24792 | /* 68304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24793 | /* 68308 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24794 | /* 68312 */ GIM_Try, /*On fail goto*//*Label 2124*/ GIMT_Encode4(68377), // Rule ID 4328 // |
| 24795 | /* 68317 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24796 | /* 68321 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24797 | /* 68325 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 24798 | /* 68329 */ // MIs[1] Operand 1 |
| 24799 | /* 68329 */ // No operand predicates |
| 24800 | /* 68329 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24801 | /* 68333 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24802 | /* 68335 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3983:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) |
| 24803 | /* 68335 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24804 | /* 68338 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24805 | /* 68342 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24806 | /* 68347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms8), |
| 24807 | /* 68350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24808 | /* 68352 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24809 | /* 68354 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24810 | /* 68357 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24811 | /* 68360 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24812 | /* 68366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24813 | /* 68372 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24814 | /* 68375 */ GIR_RootConstrainSelectedInstOperands, |
| 24815 | /* 68376 */ // GIR_Coverage, 4328, |
| 24816 | /* 68376 */ GIR_EraseRootFromParent_Done, |
| 24817 | /* 68377 */ // Label 2124: @68377 |
| 24818 | /* 68377 */ GIM_Try, /*On fail goto*//*Label 2125*/ GIMT_Encode4(68442), // Rule ID 4330 // |
| 24819 | /* 68382 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24820 | /* 68386 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24821 | /* 68390 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 24822 | /* 68394 */ // MIs[1] Operand 1 |
| 24823 | /* 68394 */ // No operand predicates |
| 24824 | /* 68394 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24825 | /* 68398 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24826 | /* 68400 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3983:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) |
| 24827 | /* 68400 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24828 | /* 68403 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24829 | /* 68407 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24830 | /* 68412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu8), |
| 24831 | /* 68415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24832 | /* 68417 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24833 | /* 68419 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24834 | /* 68422 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24835 | /* 68425 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24836 | /* 68431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24837 | /* 68437 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24838 | /* 68440 */ GIR_RootConstrainSelectedInstOperands, |
| 24839 | /* 68441 */ // GIR_Coverage, 4330, |
| 24840 | /* 68441 */ GIR_EraseRootFromParent_Done, |
| 24841 | /* 68442 */ // Label 2125: @68442 |
| 24842 | /* 68442 */ GIM_Reject, |
| 24843 | /* 68443 */ // Label 2123: @68443 |
| 24844 | /* 68443 */ GIM_Reject, |
| 24845 | /* 68444 */ // Label 2120: @68444 |
| 24846 | /* 68444 */ GIM_Try, /*On fail goto*//*Label 2126*/ GIMT_Encode4(68597), |
| 24847 | /* 68449 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 24848 | /* 68452 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24849 | /* 68455 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24850 | /* 68458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24851 | /* 68462 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24852 | /* 68466 */ GIM_Try, /*On fail goto*//*Label 2127*/ GIMT_Encode4(68531), // Rule ID 4332 // |
| 24853 | /* 68471 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24854 | /* 68475 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24855 | /* 68479 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 24856 | /* 68483 */ // MIs[1] Operand 1 |
| 24857 | /* 68483 */ // No operand predicates |
| 24858 | /* 68483 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24859 | /* 68487 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24860 | /* 68489 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3983:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) |
| 24861 | /* 68489 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24862 | /* 68492 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24863 | /* 68496 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24864 | /* 68501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms16), |
| 24865 | /* 68504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24866 | /* 68506 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24867 | /* 68508 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24868 | /* 68511 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24869 | /* 68514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24870 | /* 68520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24871 | /* 68526 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24872 | /* 68529 */ GIR_RootConstrainSelectedInstOperands, |
| 24873 | /* 68530 */ // GIR_Coverage, 4332, |
| 24874 | /* 68530 */ GIR_EraseRootFromParent_Done, |
| 24875 | /* 68531 */ // Label 2127: @68531 |
| 24876 | /* 68531 */ GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(68596), // Rule ID 4334 // |
| 24877 | /* 68536 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24878 | /* 68540 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24879 | /* 68544 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 24880 | /* 68548 */ // MIs[1] Operand 1 |
| 24881 | /* 68548 */ // No operand predicates |
| 24882 | /* 68548 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24883 | /* 68552 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24884 | /* 68554 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3983:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) |
| 24885 | /* 68554 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24886 | /* 68557 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24887 | /* 68561 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24888 | /* 68566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu16), |
| 24889 | /* 68569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24890 | /* 68571 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24891 | /* 68573 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24892 | /* 68576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24893 | /* 68579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24894 | /* 68585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24895 | /* 68591 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24896 | /* 68594 */ GIR_RootConstrainSelectedInstOperands, |
| 24897 | /* 68595 */ // GIR_Coverage, 4334, |
| 24898 | /* 68595 */ GIR_EraseRootFromParent_Done, |
| 24899 | /* 68596 */ // Label 2128: @68596 |
| 24900 | /* 68596 */ GIM_Reject, |
| 24901 | /* 68597 */ // Label 2126: @68597 |
| 24902 | /* 68597 */ GIM_Reject, |
| 24903 | /* 68598 */ // Label 2121: @68598 |
| 24904 | /* 68598 */ GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(68751), |
| 24905 | /* 68603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 24906 | /* 68606 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 24907 | /* 68609 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24908 | /* 68612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24909 | /* 68616 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24910 | /* 68620 */ GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(68685), // Rule ID 4336 // |
| 24911 | /* 68625 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24912 | /* 68629 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24913 | /* 68633 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32), |
| 24914 | /* 68637 */ // MIs[1] Operand 1 |
| 24915 | /* 68637 */ // No operand predicates |
| 24916 | /* 68637 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 24917 | /* 68641 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24918 | /* 68643 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3983:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) |
| 24919 | /* 68643 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24920 | /* 68646 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24921 | /* 68650 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24922 | /* 68655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms32), |
| 24923 | /* 68658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24924 | /* 68660 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24925 | /* 68662 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24926 | /* 68665 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24927 | /* 68668 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24928 | /* 68674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24929 | /* 68680 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24930 | /* 68683 */ GIR_RootConstrainSelectedInstOperands, |
| 24931 | /* 68684 */ // GIR_Coverage, 4336, |
| 24932 | /* 68684 */ GIR_EraseRootFromParent_Done, |
| 24933 | /* 68685 */ // Label 2130: @68685 |
| 24934 | /* 68685 */ GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(68750), // Rule ID 4338 // |
| 24935 | /* 68690 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 24936 | /* 68694 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24937 | /* 68698 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32), |
| 24938 | /* 68702 */ // MIs[1] Operand 1 |
| 24939 | /* 68702 */ // No operand predicates |
| 24940 | /* 68702 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 24941 | /* 68706 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24942 | /* 68708 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3983:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) |
| 24943 | /* 68708 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24944 | /* 68711 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24945 | /* 68715 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24946 | /* 68720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu32), |
| 24947 | /* 68723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24948 | /* 68725 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 24949 | /* 68727 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 24950 | /* 68730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24951 | /* 68733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24952 | /* 68739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24953 | /* 68745 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24954 | /* 68748 */ GIR_RootConstrainSelectedInstOperands, |
| 24955 | /* 68749 */ // GIR_Coverage, 4338, |
| 24956 | /* 68749 */ GIR_EraseRootFromParent_Done, |
| 24957 | /* 68750 */ // Label 2131: @68750 |
| 24958 | /* 68750 */ GIM_Reject, |
| 24959 | /* 68751 */ // Label 2129: @68751 |
| 24960 | /* 68751 */ GIM_Reject, |
| 24961 | /* 68752 */ // Label 2122: @68752 |
| 24962 | /* 68752 */ GIM_Reject, |
| 24963 | /* 68753 */ // Label 2118: @68753 |
| 24964 | /* 68753 */ GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(69355), |
| 24965 | /* 68758 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix), |
| 24966 | /* 68763 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2135*/ GIMT_Encode4(69354), |
| 24967 | /* 68774 */ /*GILLT_v8s16*//*Label 2133*/ GIMT_Encode4(68786), GIMT_Encode4(0), |
| 24968 | /* 68782 */ /*GILLT_v4s32*//*Label 2134*/ GIMT_Encode4(69070), |
| 24969 | /* 68786 */ // Label 2133: @68786 |
| 24970 | /* 68786 */ GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(69069), |
| 24971 | /* 68791 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 24972 | /* 68794 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 24973 | /* 68797 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 24974 | /* 68800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24975 | /* 68804 */ GIM_Try, /*On fail goto*//*Label 2137*/ GIMT_Encode4(68936), |
| 24976 | /* 68809 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 24977 | /* 68813 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 24978 | /* 68817 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2138*/ GIMT_Encode4(68876), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4484 // |
| 24979 | /* 68824 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 24980 | /* 68828 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 24981 | /* 68832 */ // MIs[1] Operand 1 |
| 24982 | /* 68832 */ // No operand predicates |
| 24983 | /* 68832 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 24984 | /* 68834 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3892:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16s16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 24985 | /* 68834 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 24986 | /* 68837 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 24987 | /* 68841 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 24988 | /* 68846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16_fix), |
| 24989 | /* 68849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 24990 | /* 68851 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 24991 | /* 68853 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 24992 | /* 68856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24993 | /* 68859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24994 | /* 68865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 24995 | /* 68871 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 24996 | /* 68874 */ GIR_RootConstrainSelectedInstOperands, |
| 24997 | /* 68875 */ // GIR_Coverage, 4484, |
| 24998 | /* 68875 */ GIR_EraseRootFromParent_Done, |
| 24999 | /* 68876 */ // Label 2138: @68876 |
| 25000 | /* 68876 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2139*/ GIMT_Encode4(68935), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4486 // |
| 25001 | /* 68883 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25002 | /* 68887 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25003 | /* 68891 */ // MIs[1] Operand 1 |
| 25004 | /* 68891 */ // No operand predicates |
| 25005 | /* 68891 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25006 | /* 68893 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3892:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25007 | /* 68893 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25008 | /* 68896 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25009 | /* 68900 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25010 | /* 68905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16_fix), |
| 25011 | /* 68908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25012 | /* 68910 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25013 | /* 68912 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25014 | /* 68915 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25015 | /* 68918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25016 | /* 68924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25017 | /* 68930 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25018 | /* 68933 */ GIR_RootConstrainSelectedInstOperands, |
| 25019 | /* 68934 */ // GIR_Coverage, 4486, |
| 25020 | /* 68934 */ GIR_EraseRootFromParent_Done, |
| 25021 | /* 68935 */ // Label 2139: @68935 |
| 25022 | /* 68935 */ GIM_Reject, |
| 25023 | /* 68936 */ // Label 2137: @68936 |
| 25024 | /* 68936 */ GIM_Try, /*On fail goto*//*Label 2140*/ GIMT_Encode4(69068), |
| 25025 | /* 68941 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 25026 | /* 68945 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25027 | /* 68949 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2141*/ GIMT_Encode4(69008), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4488 // |
| 25028 | /* 68956 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25029 | /* 68960 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25030 | /* 68964 */ // MIs[1] Operand 1 |
| 25031 | /* 68964 */ // No operand predicates |
| 25032 | /* 68964 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25033 | /* 68966 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3892:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16u16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25034 | /* 68966 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25035 | /* 68969 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25036 | /* 68973 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25037 | /* 68978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16_fix), |
| 25038 | /* 68981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25039 | /* 68983 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25040 | /* 68985 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25041 | /* 68988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25042 | /* 68991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25043 | /* 68997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25044 | /* 69003 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25045 | /* 69006 */ GIR_RootConstrainSelectedInstOperands, |
| 25046 | /* 69007 */ // GIR_Coverage, 4488, |
| 25047 | /* 69007 */ GIR_EraseRootFromParent_Done, |
| 25048 | /* 69008 */ // Label 2141: @69008 |
| 25049 | /* 69008 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2142*/ GIMT_Encode4(69067), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4490 // |
| 25050 | /* 69015 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25051 | /* 69019 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25052 | /* 69023 */ // MIs[1] Operand 1 |
| 25053 | /* 69023 */ // No operand predicates |
| 25054 | /* 69023 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25055 | /* 69025 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3892:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25056 | /* 69025 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25057 | /* 69028 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25058 | /* 69032 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25059 | /* 69037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16_fix), |
| 25060 | /* 69040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25061 | /* 69042 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25062 | /* 69044 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25063 | /* 69047 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25064 | /* 69050 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25065 | /* 69056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25066 | /* 69062 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25067 | /* 69065 */ GIR_RootConstrainSelectedInstOperands, |
| 25068 | /* 69066 */ // GIR_Coverage, 4490, |
| 25069 | /* 69066 */ GIR_EraseRootFromParent_Done, |
| 25070 | /* 69067 */ // Label 2142: @69067 |
| 25071 | /* 69067 */ GIM_Reject, |
| 25072 | /* 69068 */ // Label 2140: @69068 |
| 25073 | /* 69068 */ GIM_Reject, |
| 25074 | /* 69069 */ // Label 2136: @69069 |
| 25075 | /* 69069 */ GIM_Reject, |
| 25076 | /* 69070 */ // Label 2134: @69070 |
| 25077 | /* 69070 */ GIM_Try, /*On fail goto*//*Label 2143*/ GIMT_Encode4(69353), |
| 25078 | /* 69075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25079 | /* 69078 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25080 | /* 69081 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25081 | /* 69084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25082 | /* 69088 */ GIM_Try, /*On fail goto*//*Label 2144*/ GIMT_Encode4(69220), |
| 25083 | /* 69093 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 25084 | /* 69097 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25085 | /* 69101 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2145*/ GIMT_Encode4(69160), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4492 // |
| 25086 | /* 69108 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25087 | /* 69112 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25088 | /* 69116 */ // MIs[1] Operand 1 |
| 25089 | /* 69116 */ // No operand predicates |
| 25090 | /* 69116 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25091 | /* 69118 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3892:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32s32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25092 | /* 69118 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25093 | /* 69121 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25094 | /* 69125 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25095 | /* 69130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32_fix), |
| 25096 | /* 69133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25097 | /* 69135 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25098 | /* 69137 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25099 | /* 69140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25100 | /* 69143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25101 | /* 69149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25102 | /* 69155 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25103 | /* 69158 */ GIR_RootConstrainSelectedInstOperands, |
| 25104 | /* 69159 */ // GIR_Coverage, 4492, |
| 25105 | /* 69159 */ GIR_EraseRootFromParent_Done, |
| 25106 | /* 69160 */ // Label 2145: @69160 |
| 25107 | /* 69160 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2146*/ GIMT_Encode4(69219), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4494 // |
| 25108 | /* 69167 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25109 | /* 69171 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25110 | /* 69175 */ // MIs[1] Operand 1 |
| 25111 | /* 69175 */ // No operand predicates |
| 25112 | /* 69175 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25113 | /* 69177 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3892:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25114 | /* 69177 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25115 | /* 69180 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25116 | /* 69184 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25117 | /* 69189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32_fix), |
| 25118 | /* 69192 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25119 | /* 69194 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25120 | /* 69196 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25121 | /* 69199 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25122 | /* 69202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25123 | /* 69208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25124 | /* 69214 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25125 | /* 69217 */ GIR_RootConstrainSelectedInstOperands, |
| 25126 | /* 69218 */ // GIR_Coverage, 4494, |
| 25127 | /* 69218 */ GIR_EraseRootFromParent_Done, |
| 25128 | /* 69219 */ // Label 2146: @69219 |
| 25129 | /* 69219 */ GIM_Reject, |
| 25130 | /* 69220 */ // Label 2144: @69220 |
| 25131 | /* 69220 */ GIM_Try, /*On fail goto*//*Label 2147*/ GIMT_Encode4(69352), |
| 25132 | /* 69225 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 25133 | /* 69229 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25134 | /* 69233 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2148*/ GIMT_Encode4(69292), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4496 // |
| 25135 | /* 69240 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25136 | /* 69244 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25137 | /* 69248 */ // MIs[1] Operand 1 |
| 25138 | /* 69248 */ // No operand predicates |
| 25139 | /* 69248 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25140 | /* 69250 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3892:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32u32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25141 | /* 69250 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25142 | /* 69253 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25143 | /* 69257 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25144 | /* 69262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32_fix), |
| 25145 | /* 69265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25146 | /* 69267 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25147 | /* 69269 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25148 | /* 69272 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25149 | /* 69275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25150 | /* 69281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25151 | /* 69287 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25152 | /* 69290 */ GIR_RootConstrainSelectedInstOperands, |
| 25153 | /* 69291 */ // GIR_Coverage, 4496, |
| 25154 | /* 69291 */ GIR_EraseRootFromParent_Done, |
| 25155 | /* 69292 */ // Label 2148: @69292 |
| 25156 | /* 69292 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2149*/ GIMT_Encode4(69351), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4498 // |
| 25157 | /* 69299 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 25158 | /* 69303 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 25159 | /* 69307 */ // MIs[1] Operand 1 |
| 25160 | /* 69307 */ // No operand predicates |
| 25161 | /* 69307 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 25162 | /* 69309 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3892:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) |
| 25163 | /* 69309 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25164 | /* 69312 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25165 | /* 69316 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25166 | /* 69321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32_fix), |
| 25167 | /* 69324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25168 | /* 69326 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 25169 | /* 69328 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale |
| 25170 | /* 69331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25171 | /* 69334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25172 | /* 69340 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25173 | /* 69346 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25174 | /* 69349 */ GIR_RootConstrainSelectedInstOperands, |
| 25175 | /* 69350 */ // GIR_Coverage, 4498, |
| 25176 | /* 69350 */ GIR_EraseRootFromParent_Done, |
| 25177 | /* 69351 */ // Label 2149: @69351 |
| 25178 | /* 69351 */ GIM_Reject, |
| 25179 | /* 69352 */ // Label 2147: @69352 |
| 25180 | /* 69352 */ GIM_Reject, |
| 25181 | /* 69353 */ // Label 2143: @69353 |
| 25182 | /* 69353 */ GIM_Reject, |
| 25183 | /* 69354 */ // Label 2135: @69354 |
| 25184 | /* 69354 */ GIM_Reject, |
| 25185 | /* 69355 */ // Label 2132: @69355 |
| 25186 | /* 69355 */ GIM_Try, /*On fail goto*//*Label 2150*/ GIMT_Encode4(69691), |
| 25187 | /* 69360 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv), |
| 25188 | /* 69365 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25189 | /* 69368 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25190 | /* 69371 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2154*/ GIMT_Encode4(69690), |
| 25191 | /* 69382 */ /*GILLT_v16s8*//*Label 2151*/ GIMT_Encode4(69402), GIMT_Encode4(0), |
| 25192 | /* 69390 */ /*GILLT_v8s16*//*Label 2152*/ GIMT_Encode4(69498), GIMT_Encode4(0), |
| 25193 | /* 69398 */ /*GILLT_v4s32*//*Label 2153*/ GIMT_Encode4(69594), |
| 25194 | /* 69402 */ // Label 2151: @69402 |
| 25195 | /* 69402 */ GIM_Try, /*On fail goto*//*Label 2155*/ GIMT_Encode4(69497), |
| 25196 | /* 69407 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25197 | /* 69410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25198 | /* 69414 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25199 | /* 69418 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25200 | /* 69422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2156*/ GIMT_Encode4(69459), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3509 // |
| 25201 | /* 69429 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25202 | /* 69433 */ // (intrinsic_wo_chain:{ *:[i32] } 3838:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 25203 | /* 69433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8), |
| 25204 | /* 69436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25205 | /* 69438 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25206 | /* 69440 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25207 | /* 69442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25208 | /* 69445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25209 | /* 69451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25210 | /* 69457 */ GIR_RootConstrainSelectedInstOperands, |
| 25211 | /* 69458 */ // GIR_Coverage, 3509, |
| 25212 | /* 69458 */ GIR_EraseRootFromParent_Done, |
| 25213 | /* 69459 */ // Label 2156: @69459 |
| 25214 | /* 69459 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2157*/ GIMT_Encode4(69496), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3515 // |
| 25215 | /* 69466 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25216 | /* 69470 */ // (intrinsic_wo_chain:{ *:[i32] } 3838:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 25217 | /* 69470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8), |
| 25218 | /* 69473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25219 | /* 69475 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25220 | /* 69477 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25221 | /* 69479 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25222 | /* 69482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25223 | /* 69488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25224 | /* 69494 */ GIR_RootConstrainSelectedInstOperands, |
| 25225 | /* 69495 */ // GIR_Coverage, 3515, |
| 25226 | /* 69495 */ GIR_EraseRootFromParent_Done, |
| 25227 | /* 69496 */ // Label 2157: @69496 |
| 25228 | /* 69496 */ GIM_Reject, |
| 25229 | /* 69497 */ // Label 2155: @69497 |
| 25230 | /* 69497 */ GIM_Reject, |
| 25231 | /* 69498 */ // Label 2152: @69498 |
| 25232 | /* 69498 */ GIM_Try, /*On fail goto*//*Label 2158*/ GIMT_Encode4(69593), |
| 25233 | /* 69503 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25234 | /* 69506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25235 | /* 69510 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25236 | /* 69514 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25237 | /* 69518 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2159*/ GIMT_Encode4(69555), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3511 // |
| 25238 | /* 69525 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25239 | /* 69529 */ // (intrinsic_wo_chain:{ *:[i32] } 3838:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 25240 | /* 69529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16), |
| 25241 | /* 69532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25242 | /* 69534 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25243 | /* 69536 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25244 | /* 69538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25245 | /* 69541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25246 | /* 69547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25247 | /* 69553 */ GIR_RootConstrainSelectedInstOperands, |
| 25248 | /* 69554 */ // GIR_Coverage, 3511, |
| 25249 | /* 69554 */ GIR_EraseRootFromParent_Done, |
| 25250 | /* 69555 */ // Label 2159: @69555 |
| 25251 | /* 69555 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2160*/ GIMT_Encode4(69592), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3517 // |
| 25252 | /* 69562 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25253 | /* 69566 */ // (intrinsic_wo_chain:{ *:[i32] } 3838:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 25254 | /* 69566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16), |
| 25255 | /* 69569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25256 | /* 69571 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25257 | /* 69573 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25258 | /* 69575 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25259 | /* 69578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25260 | /* 69584 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25261 | /* 69590 */ GIR_RootConstrainSelectedInstOperands, |
| 25262 | /* 69591 */ // GIR_Coverage, 3517, |
| 25263 | /* 69591 */ GIR_EraseRootFromParent_Done, |
| 25264 | /* 69592 */ // Label 2160: @69592 |
| 25265 | /* 69592 */ GIM_Reject, |
| 25266 | /* 69593 */ // Label 2158: @69593 |
| 25267 | /* 69593 */ GIM_Reject, |
| 25268 | /* 69594 */ // Label 2153: @69594 |
| 25269 | /* 69594 */ GIM_Try, /*On fail goto*//*Label 2161*/ GIMT_Encode4(69689), |
| 25270 | /* 69599 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25271 | /* 69602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25272 | /* 69606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25273 | /* 69610 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25274 | /* 69614 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2162*/ GIMT_Encode4(69651), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3513 // |
| 25275 | /* 69621 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25276 | /* 69625 */ // (intrinsic_wo_chain:{ *:[i32] } 3838:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 25277 | /* 69625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32), |
| 25278 | /* 69628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25279 | /* 69630 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25280 | /* 69632 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25281 | /* 69634 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25282 | /* 69637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25283 | /* 69643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25284 | /* 69649 */ GIR_RootConstrainSelectedInstOperands, |
| 25285 | /* 69650 */ // GIR_Coverage, 3513, |
| 25286 | /* 69650 */ GIR_EraseRootFromParent_Done, |
| 25287 | /* 69651 */ // Label 2162: @69651 |
| 25288 | /* 69651 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2163*/ GIMT_Encode4(69688), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3519 // |
| 25289 | /* 69658 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25290 | /* 69662 */ // (intrinsic_wo_chain:{ *:[i32] } 3838:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 25291 | /* 69662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32), |
| 25292 | /* 69665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25293 | /* 69667 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25294 | /* 69669 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25295 | /* 69671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25296 | /* 69674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25297 | /* 69680 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25298 | /* 69686 */ GIR_RootConstrainSelectedInstOperands, |
| 25299 | /* 69687 */ // GIR_Coverage, 3519, |
| 25300 | /* 69687 */ GIR_EraseRootFromParent_Done, |
| 25301 | /* 69688 */ // Label 2163: @69688 |
| 25302 | /* 69688 */ GIM_Reject, |
| 25303 | /* 69689 */ // Label 2161: @69689 |
| 25304 | /* 69689 */ GIM_Reject, |
| 25305 | /* 69690 */ // Label 2154: @69690 |
| 25306 | /* 69690 */ GIM_Reject, |
| 25307 | /* 69691 */ // Label 2150: @69691 |
| 25308 | /* 69691 */ GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(70027), |
| 25309 | /* 69696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv), |
| 25310 | /* 69701 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 25311 | /* 69704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 25312 | /* 69707 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2168*/ GIMT_Encode4(70026), |
| 25313 | /* 69718 */ /*GILLT_v16s8*//*Label 2165*/ GIMT_Encode4(69738), GIMT_Encode4(0), |
| 25314 | /* 69726 */ /*GILLT_v8s16*//*Label 2166*/ GIMT_Encode4(69834), GIMT_Encode4(0), |
| 25315 | /* 69734 */ /*GILLT_v4s32*//*Label 2167*/ GIMT_Encode4(69930), |
| 25316 | /* 69738 */ // Label 2165: @69738 |
| 25317 | /* 69738 */ GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(69833), |
| 25318 | /* 69743 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25319 | /* 69746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25320 | /* 69750 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25321 | /* 69754 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25322 | /* 69758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2170*/ GIMT_Encode4(69795), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3521 // |
| 25323 | /* 69765 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25324 | /* 69769 */ // (intrinsic_wo_chain:{ *:[i32] } 3829:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 25325 | /* 69769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8), |
| 25326 | /* 69772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25327 | /* 69774 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25328 | /* 69776 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25329 | /* 69778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25330 | /* 69781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25331 | /* 69787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25332 | /* 69793 */ GIR_RootConstrainSelectedInstOperands, |
| 25333 | /* 69794 */ // GIR_Coverage, 3521, |
| 25334 | /* 69794 */ GIR_EraseRootFromParent_Done, |
| 25335 | /* 69795 */ // Label 2170: @69795 |
| 25336 | /* 69795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2171*/ GIMT_Encode4(69832), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3527 // |
| 25337 | /* 69802 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25338 | /* 69806 */ // (intrinsic_wo_chain:{ *:[i32] } 3829:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) |
| 25339 | /* 69806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8), |
| 25340 | /* 69809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25341 | /* 69811 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25342 | /* 69813 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25343 | /* 69815 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25344 | /* 69818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25345 | /* 69824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25346 | /* 69830 */ GIR_RootConstrainSelectedInstOperands, |
| 25347 | /* 69831 */ // GIR_Coverage, 3527, |
| 25348 | /* 69831 */ GIR_EraseRootFromParent_Done, |
| 25349 | /* 69832 */ // Label 2171: @69832 |
| 25350 | /* 69832 */ GIM_Reject, |
| 25351 | /* 69833 */ // Label 2169: @69833 |
| 25352 | /* 69833 */ GIM_Reject, |
| 25353 | /* 69834 */ // Label 2166: @69834 |
| 25354 | /* 69834 */ GIM_Try, /*On fail goto*//*Label 2172*/ GIMT_Encode4(69929), |
| 25355 | /* 69839 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25356 | /* 69842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25357 | /* 69846 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25358 | /* 69850 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25359 | /* 69854 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2173*/ GIMT_Encode4(69891), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3523 // |
| 25360 | /* 69861 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25361 | /* 69865 */ // (intrinsic_wo_chain:{ *:[i32] } 3829:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 25362 | /* 69865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16), |
| 25363 | /* 69868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25364 | /* 69870 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25365 | /* 69872 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25366 | /* 69874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25367 | /* 69877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25368 | /* 69883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25369 | /* 69889 */ GIR_RootConstrainSelectedInstOperands, |
| 25370 | /* 69890 */ // GIR_Coverage, 3523, |
| 25371 | /* 69890 */ GIR_EraseRootFromParent_Done, |
| 25372 | /* 69891 */ // Label 2173: @69891 |
| 25373 | /* 69891 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2174*/ GIMT_Encode4(69928), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3529 // |
| 25374 | /* 69898 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25375 | /* 69902 */ // (intrinsic_wo_chain:{ *:[i32] } 3829:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) |
| 25376 | /* 69902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16), |
| 25377 | /* 69905 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25378 | /* 69907 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25379 | /* 69909 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25380 | /* 69911 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25381 | /* 69914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25382 | /* 69920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25383 | /* 69926 */ GIR_RootConstrainSelectedInstOperands, |
| 25384 | /* 69927 */ // GIR_Coverage, 3529, |
| 25385 | /* 69927 */ GIR_EraseRootFromParent_Done, |
| 25386 | /* 69928 */ // Label 2174: @69928 |
| 25387 | /* 69928 */ GIM_Reject, |
| 25388 | /* 69929 */ // Label 2172: @69929 |
| 25389 | /* 69929 */ GIM_Reject, |
| 25390 | /* 69930 */ // Label 2167: @69930 |
| 25391 | /* 69930 */ GIM_Try, /*On fail goto*//*Label 2175*/ GIMT_Encode4(70025), |
| 25392 | /* 69935 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25393 | /* 69938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25394 | /* 69942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 25395 | /* 69946 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25396 | /* 69950 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2176*/ GIMT_Encode4(69987), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3525 // |
| 25397 | /* 69957 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25398 | /* 69961 */ // (intrinsic_wo_chain:{ *:[i32] } 3829:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 25399 | /* 69961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32), |
| 25400 | /* 69964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25401 | /* 69966 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25402 | /* 69968 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25403 | /* 69970 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25404 | /* 69973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25405 | /* 69979 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25406 | /* 69985 */ GIR_RootConstrainSelectedInstOperands, |
| 25407 | /* 69986 */ // GIR_Coverage, 3525, |
| 25408 | /* 69986 */ GIR_EraseRootFromParent_Done, |
| 25409 | /* 69987 */ // Label 2176: @69987 |
| 25410 | /* 69987 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2177*/ GIMT_Encode4(70024), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3531 // |
| 25411 | /* 69994 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25412 | /* 69998 */ // (intrinsic_wo_chain:{ *:[i32] } 3829:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) |
| 25413 | /* 69998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32), |
| 25414 | /* 70001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 25415 | /* 70003 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev |
| 25416 | /* 70005 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec |
| 25417 | /* 70007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25418 | /* 70010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25419 | /* 70016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25420 | /* 70022 */ GIR_RootConstrainSelectedInstOperands, |
| 25421 | /* 70023 */ // GIR_Coverage, 3531, |
| 25422 | /* 70023 */ GIR_EraseRootFromParent_Done, |
| 25423 | /* 70024 */ // Label 2177: @70024 |
| 25424 | /* 70024 */ GIM_Reject, |
| 25425 | /* 70025 */ // Label 2175: @70025 |
| 25426 | /* 70025 */ GIM_Reject, |
| 25427 | /* 70026 */ // Label 2168: @70026 |
| 25428 | /* 70026 */ GIM_Reject, |
| 25429 | /* 70027 */ // Label 2164: @70027 |
| 25430 | /* 70027 */ GIM_Try, /*On fail goto*//*Label 2178*/ GIMT_Encode4(70465), |
| 25431 | /* 70032 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 25432 | /* 70037 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2182*/ GIMT_Encode4(70464), |
| 25433 | /* 70048 */ /*GILLT_v16s8*//*Label 2179*/ GIMT_Encode4(70068), GIMT_Encode4(0), |
| 25434 | /* 70056 */ /*GILLT_v8s16*//*Label 2180*/ GIMT_Encode4(70200), GIMT_Encode4(0), |
| 25435 | /* 70064 */ /*GILLT_v4s32*//*Label 2181*/ GIMT_Encode4(70332), |
| 25436 | /* 70068 */ // Label 2179: @70068 |
| 25437 | /* 70068 */ GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(70199), |
| 25438 | /* 70073 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25439 | /* 70076 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25440 | /* 70079 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25441 | /* 70082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25442 | /* 70086 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25443 | /* 70090 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25444 | /* 70094 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2184*/ GIMT_Encode4(70146), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3942 // |
| 25445 | /* 70101 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25446 | /* 70105 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3875:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25447 | /* 70105 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25448 | /* 70108 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25449 | /* 70112 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25450 | /* 70117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8), |
| 25451 | /* 70120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25452 | /* 70122 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25453 | /* 70124 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25454 | /* 70126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25455 | /* 70129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25456 | /* 70135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25457 | /* 70141 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25458 | /* 70144 */ GIR_RootConstrainSelectedInstOperands, |
| 25459 | /* 70145 */ // GIR_Coverage, 3942, |
| 25460 | /* 70145 */ GIR_EraseRootFromParent_Done, |
| 25461 | /* 70146 */ // Label 2184: @70146 |
| 25462 | /* 70146 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2185*/ GIMT_Encode4(70198), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3957 // |
| 25463 | /* 70153 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25464 | /* 70157 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3875:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25465 | /* 70157 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25466 | /* 70160 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25467 | /* 70164 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25468 | /* 70169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8), |
| 25469 | /* 70172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25470 | /* 70174 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25471 | /* 70176 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25472 | /* 70178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25473 | /* 70181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25474 | /* 70187 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25475 | /* 70193 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25476 | /* 70196 */ GIR_RootConstrainSelectedInstOperands, |
| 25477 | /* 70197 */ // GIR_Coverage, 3957, |
| 25478 | /* 70197 */ GIR_EraseRootFromParent_Done, |
| 25479 | /* 70198 */ // Label 2185: @70198 |
| 25480 | /* 70198 */ GIM_Reject, |
| 25481 | /* 70199 */ // Label 2183: @70199 |
| 25482 | /* 70199 */ GIM_Reject, |
| 25483 | /* 70200 */ // Label 2180: @70200 |
| 25484 | /* 70200 */ GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(70331), |
| 25485 | /* 70205 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25486 | /* 70208 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25487 | /* 70211 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25488 | /* 70214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25489 | /* 70218 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25490 | /* 70222 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25491 | /* 70226 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2187*/ GIMT_Encode4(70278), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3949 // |
| 25492 | /* 70233 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25493 | /* 70237 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3875:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25494 | /* 70237 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25495 | /* 70240 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25496 | /* 70244 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25497 | /* 70249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16), |
| 25498 | /* 70252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25499 | /* 70254 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25500 | /* 70256 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25501 | /* 70258 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25502 | /* 70261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25503 | /* 70267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25504 | /* 70273 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25505 | /* 70276 */ GIR_RootConstrainSelectedInstOperands, |
| 25506 | /* 70277 */ // GIR_Coverage, 3949, |
| 25507 | /* 70277 */ GIR_EraseRootFromParent_Done, |
| 25508 | /* 70278 */ // Label 2187: @70278 |
| 25509 | /* 70278 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2188*/ GIMT_Encode4(70330), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3961 // |
| 25510 | /* 70285 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25511 | /* 70289 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3875:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25512 | /* 70289 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25513 | /* 70292 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25514 | /* 70296 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25515 | /* 70301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16), |
| 25516 | /* 70304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25517 | /* 70306 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25518 | /* 70308 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25519 | /* 70310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25520 | /* 70313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25521 | /* 70319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25522 | /* 70325 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25523 | /* 70328 */ GIR_RootConstrainSelectedInstOperands, |
| 25524 | /* 70329 */ // GIR_Coverage, 3961, |
| 25525 | /* 70329 */ GIR_EraseRootFromParent_Done, |
| 25526 | /* 70330 */ // Label 2188: @70330 |
| 25527 | /* 70330 */ GIM_Reject, |
| 25528 | /* 70331 */ // Label 2186: @70331 |
| 25529 | /* 70331 */ GIM_Reject, |
| 25530 | /* 70332 */ // Label 2181: @70332 |
| 25531 | /* 70332 */ GIM_Try, /*On fail goto*//*Label 2189*/ GIMT_Encode4(70463), |
| 25532 | /* 70337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25533 | /* 70340 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25534 | /* 70343 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25535 | /* 70346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25536 | /* 70350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25537 | /* 70354 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25538 | /* 70358 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2190*/ GIMT_Encode4(70410), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3953 // |
| 25539 | /* 70365 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25540 | /* 70369 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3875:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 25541 | /* 70369 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25542 | /* 70372 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25543 | /* 70376 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25544 | /* 70381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32), |
| 25545 | /* 70384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25546 | /* 70386 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25547 | /* 70388 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25548 | /* 70390 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25549 | /* 70393 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25550 | /* 70399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25551 | /* 70405 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25552 | /* 70408 */ GIR_RootConstrainSelectedInstOperands, |
| 25553 | /* 70409 */ // GIR_Coverage, 3953, |
| 25554 | /* 70409 */ GIR_EraseRootFromParent_Done, |
| 25555 | /* 70410 */ // Label 2190: @70410 |
| 25556 | /* 70410 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2191*/ GIMT_Encode4(70462), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3965 // |
| 25557 | /* 70417 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25558 | /* 70421 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3875:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 25559 | /* 70421 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25560 | /* 70424 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25561 | /* 70428 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25562 | /* 70433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32), |
| 25563 | /* 70436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25564 | /* 70438 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25565 | /* 70440 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25566 | /* 70442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25567 | /* 70445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25568 | /* 70451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25569 | /* 70457 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25570 | /* 70460 */ GIR_RootConstrainSelectedInstOperands, |
| 25571 | /* 70461 */ // GIR_Coverage, 3965, |
| 25572 | /* 70461 */ GIR_EraseRootFromParent_Done, |
| 25573 | /* 70462 */ // Label 2191: @70462 |
| 25574 | /* 70462 */ GIM_Reject, |
| 25575 | /* 70463 */ // Label 2189: @70463 |
| 25576 | /* 70463 */ GIM_Reject, |
| 25577 | /* 70464 */ // Label 2182: @70464 |
| 25578 | /* 70464 */ GIM_Reject, |
| 25579 | /* 70465 */ // Label 2178: @70465 |
| 25580 | /* 70465 */ GIM_Try, /*On fail goto*//*Label 2192*/ GIMT_Encode4(70903), |
| 25581 | /* 70470 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd), |
| 25582 | /* 70475 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2196*/ GIMT_Encode4(70902), |
| 25583 | /* 70486 */ /*GILLT_v16s8*//*Label 2193*/ GIMT_Encode4(70506), GIMT_Encode4(0), |
| 25584 | /* 70494 */ /*GILLT_v8s16*//*Label 2194*/ GIMT_Encode4(70638), GIMT_Encode4(0), |
| 25585 | /* 70502 */ /*GILLT_v4s32*//*Label 2195*/ GIMT_Encode4(70770), |
| 25586 | /* 70506 */ // Label 2193: @70506 |
| 25587 | /* 70506 */ GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(70637), |
| 25588 | /* 70511 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25589 | /* 70514 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25590 | /* 70517 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25591 | /* 70520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25592 | /* 70524 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25593 | /* 70528 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25594 | /* 70532 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2198*/ GIMT_Encode4(70584), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3966 // |
| 25595 | /* 70539 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25596 | /* 70543 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3967:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25597 | /* 70543 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25598 | /* 70546 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25599 | /* 70550 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25600 | /* 70555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8), |
| 25601 | /* 70558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25602 | /* 70560 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25603 | /* 70562 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25604 | /* 70564 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25605 | /* 70567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25606 | /* 70573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25607 | /* 70579 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25608 | /* 70582 */ GIR_RootConstrainSelectedInstOperands, |
| 25609 | /* 70583 */ // GIR_Coverage, 3966, |
| 25610 | /* 70583 */ GIR_EraseRootFromParent_Done, |
| 25611 | /* 70584 */ // Label 2198: @70584 |
| 25612 | /* 70584 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2199*/ GIMT_Encode4(70636), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3981 // |
| 25613 | /* 70591 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25614 | /* 70595 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3967:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25615 | /* 70595 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25616 | /* 70598 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25617 | /* 70602 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25618 | /* 70607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8), |
| 25619 | /* 70610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25620 | /* 70612 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25621 | /* 70614 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25622 | /* 70616 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25623 | /* 70619 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25624 | /* 70625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25625 | /* 70631 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25626 | /* 70634 */ GIR_RootConstrainSelectedInstOperands, |
| 25627 | /* 70635 */ // GIR_Coverage, 3981, |
| 25628 | /* 70635 */ GIR_EraseRootFromParent_Done, |
| 25629 | /* 70636 */ // Label 2199: @70636 |
| 25630 | /* 70636 */ GIM_Reject, |
| 25631 | /* 70637 */ // Label 2197: @70637 |
| 25632 | /* 70637 */ GIM_Reject, |
| 25633 | /* 70638 */ // Label 2194: @70638 |
| 25634 | /* 70638 */ GIM_Try, /*On fail goto*//*Label 2200*/ GIMT_Encode4(70769), |
| 25635 | /* 70643 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25636 | /* 70646 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25637 | /* 70649 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25638 | /* 70652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25639 | /* 70656 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25640 | /* 70660 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25641 | /* 70664 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2201*/ GIMT_Encode4(70716), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3973 // |
| 25642 | /* 70671 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25643 | /* 70675 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3967:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25644 | /* 70675 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25645 | /* 70678 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25646 | /* 70682 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25647 | /* 70687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16), |
| 25648 | /* 70690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25649 | /* 70692 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25650 | /* 70694 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25651 | /* 70696 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25652 | /* 70699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25653 | /* 70705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25654 | /* 70711 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25655 | /* 70714 */ GIR_RootConstrainSelectedInstOperands, |
| 25656 | /* 70715 */ // GIR_Coverage, 3973, |
| 25657 | /* 70715 */ GIR_EraseRootFromParent_Done, |
| 25658 | /* 70716 */ // Label 2201: @70716 |
| 25659 | /* 70716 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2202*/ GIMT_Encode4(70768), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3985 // |
| 25660 | /* 70723 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25661 | /* 70727 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3967:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25662 | /* 70727 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25663 | /* 70730 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25664 | /* 70734 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25665 | /* 70739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16), |
| 25666 | /* 70742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25667 | /* 70744 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25668 | /* 70746 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25669 | /* 70748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25670 | /* 70751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25671 | /* 70757 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25672 | /* 70763 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25673 | /* 70766 */ GIR_RootConstrainSelectedInstOperands, |
| 25674 | /* 70767 */ // GIR_Coverage, 3985, |
| 25675 | /* 70767 */ GIR_EraseRootFromParent_Done, |
| 25676 | /* 70768 */ // Label 2202: @70768 |
| 25677 | /* 70768 */ GIM_Reject, |
| 25678 | /* 70769 */ // Label 2200: @70769 |
| 25679 | /* 70769 */ GIM_Reject, |
| 25680 | /* 70770 */ // Label 2195: @70770 |
| 25681 | /* 70770 */ GIM_Try, /*On fail goto*//*Label 2203*/ GIMT_Encode4(70901), |
| 25682 | /* 70775 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25683 | /* 70778 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25684 | /* 70781 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25685 | /* 70784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25686 | /* 70788 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25687 | /* 70792 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25688 | /* 70796 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2204*/ GIMT_Encode4(70848), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3977 // |
| 25689 | /* 70803 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25690 | /* 70807 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3967:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 25691 | /* 70807 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25692 | /* 70810 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25693 | /* 70814 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25694 | /* 70819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32), |
| 25695 | /* 70822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25696 | /* 70824 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25697 | /* 70826 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25698 | /* 70828 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25699 | /* 70831 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25700 | /* 70837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25701 | /* 70843 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25702 | /* 70846 */ GIR_RootConstrainSelectedInstOperands, |
| 25703 | /* 70847 */ // GIR_Coverage, 3977, |
| 25704 | /* 70847 */ GIR_EraseRootFromParent_Done, |
| 25705 | /* 70848 */ // Label 2204: @70848 |
| 25706 | /* 70848 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2205*/ GIMT_Encode4(70900), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3989 // |
| 25707 | /* 70855 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25708 | /* 70859 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3967:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 25709 | /* 70859 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25710 | /* 70862 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25711 | /* 70866 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25712 | /* 70871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32), |
| 25713 | /* 70874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25714 | /* 70876 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25715 | /* 70878 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25716 | /* 70880 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25717 | /* 70883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25718 | /* 70889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25719 | /* 70895 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25720 | /* 70898 */ GIR_RootConstrainSelectedInstOperands, |
| 25721 | /* 70899 */ // GIR_Coverage, 3989, |
| 25722 | /* 70899 */ GIR_EraseRootFromParent_Done, |
| 25723 | /* 70900 */ // Label 2205: @70900 |
| 25724 | /* 70900 */ GIM_Reject, |
| 25725 | /* 70901 */ // Label 2203: @70901 |
| 25726 | /* 70901 */ GIM_Reject, |
| 25727 | /* 70902 */ // Label 2196: @70902 |
| 25728 | /* 70902 */ GIM_Reject, |
| 25729 | /* 70903 */ // Label 2192: @70903 |
| 25730 | /* 70903 */ GIM_Try, /*On fail goto*//*Label 2206*/ GIMT_Encode4(71341), |
| 25731 | /* 70908 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd), |
| 25732 | /* 70913 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2210*/ GIMT_Encode4(71340), |
| 25733 | /* 70924 */ /*GILLT_v16s8*//*Label 2207*/ GIMT_Encode4(70944), GIMT_Encode4(0), |
| 25734 | /* 70932 */ /*GILLT_v8s16*//*Label 2208*/ GIMT_Encode4(71076), GIMT_Encode4(0), |
| 25735 | /* 70940 */ /*GILLT_v4s32*//*Label 2209*/ GIMT_Encode4(71208), |
| 25736 | /* 70944 */ // Label 2207: @70944 |
| 25737 | /* 70944 */ GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(71075), |
| 25738 | /* 70949 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25739 | /* 70952 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25740 | /* 70955 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25741 | /* 70958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25742 | /* 70962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25743 | /* 70966 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25744 | /* 70970 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2212*/ GIMT_Encode4(71022), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3990 // |
| 25745 | /* 70977 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25746 | /* 70981 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3913:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25747 | /* 70981 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25748 | /* 70984 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25749 | /* 70988 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25750 | /* 70993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8), |
| 25751 | /* 70996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25752 | /* 70998 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25753 | /* 71000 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25754 | /* 71002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25755 | /* 71005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25756 | /* 71011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25757 | /* 71017 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25758 | /* 71020 */ GIR_RootConstrainSelectedInstOperands, |
| 25759 | /* 71021 */ // GIR_Coverage, 3990, |
| 25760 | /* 71021 */ GIR_EraseRootFromParent_Done, |
| 25761 | /* 71022 */ // Label 2212: @71022 |
| 25762 | /* 71022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2213*/ GIMT_Encode4(71074), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4005 // |
| 25763 | /* 71029 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25764 | /* 71033 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3913:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25765 | /* 71033 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25766 | /* 71036 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25767 | /* 71040 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25768 | /* 71045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8), |
| 25769 | /* 71048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25770 | /* 71050 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25771 | /* 71052 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25772 | /* 71054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25773 | /* 71057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25774 | /* 71063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25775 | /* 71069 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25776 | /* 71072 */ GIR_RootConstrainSelectedInstOperands, |
| 25777 | /* 71073 */ // GIR_Coverage, 4005, |
| 25778 | /* 71073 */ GIR_EraseRootFromParent_Done, |
| 25779 | /* 71074 */ // Label 2213: @71074 |
| 25780 | /* 71074 */ GIM_Reject, |
| 25781 | /* 71075 */ // Label 2211: @71075 |
| 25782 | /* 71075 */ GIM_Reject, |
| 25783 | /* 71076 */ // Label 2208: @71076 |
| 25784 | /* 71076 */ GIM_Try, /*On fail goto*//*Label 2214*/ GIMT_Encode4(71207), |
| 25785 | /* 71081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25786 | /* 71084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25787 | /* 71087 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25788 | /* 71090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25789 | /* 71094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25790 | /* 71098 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25791 | /* 71102 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2215*/ GIMT_Encode4(71154), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3997 // |
| 25792 | /* 71109 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25793 | /* 71113 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3913:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25794 | /* 71113 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25795 | /* 71116 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25796 | /* 71120 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25797 | /* 71125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16), |
| 25798 | /* 71128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25799 | /* 71130 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25800 | /* 71132 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25801 | /* 71134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25802 | /* 71137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25803 | /* 71143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25804 | /* 71149 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25805 | /* 71152 */ GIR_RootConstrainSelectedInstOperands, |
| 25806 | /* 71153 */ // GIR_Coverage, 3997, |
| 25807 | /* 71153 */ GIR_EraseRootFromParent_Done, |
| 25808 | /* 71154 */ // Label 2215: @71154 |
| 25809 | /* 71154 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2216*/ GIMT_Encode4(71206), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4009 // |
| 25810 | /* 71161 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25811 | /* 71165 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3913:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25812 | /* 71165 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25813 | /* 71168 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25814 | /* 71172 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25815 | /* 71177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16), |
| 25816 | /* 71180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25817 | /* 71182 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25818 | /* 71184 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25819 | /* 71186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25820 | /* 71189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25821 | /* 71195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25822 | /* 71201 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25823 | /* 71204 */ GIR_RootConstrainSelectedInstOperands, |
| 25824 | /* 71205 */ // GIR_Coverage, 4009, |
| 25825 | /* 71205 */ GIR_EraseRootFromParent_Done, |
| 25826 | /* 71206 */ // Label 2216: @71206 |
| 25827 | /* 71206 */ GIM_Reject, |
| 25828 | /* 71207 */ // Label 2214: @71207 |
| 25829 | /* 71207 */ GIM_Reject, |
| 25830 | /* 71208 */ // Label 2209: @71208 |
| 25831 | /* 71208 */ GIM_Try, /*On fail goto*//*Label 2217*/ GIMT_Encode4(71339), |
| 25832 | /* 71213 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25833 | /* 71216 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25834 | /* 71219 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25835 | /* 71222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25836 | /* 71226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25837 | /* 71230 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25838 | /* 71234 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2218*/ GIMT_Encode4(71286), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4001 // |
| 25839 | /* 71241 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25840 | /* 71245 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3913:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 25841 | /* 71245 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25842 | /* 71248 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25843 | /* 71252 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25844 | /* 71257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32), |
| 25845 | /* 71260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25846 | /* 71262 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25847 | /* 71264 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25848 | /* 71266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25849 | /* 71269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25850 | /* 71275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25851 | /* 71281 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25852 | /* 71284 */ GIR_RootConstrainSelectedInstOperands, |
| 25853 | /* 71285 */ // GIR_Coverage, 4001, |
| 25854 | /* 71285 */ GIR_EraseRootFromParent_Done, |
| 25855 | /* 71286 */ // Label 2218: @71286 |
| 25856 | /* 71286 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2219*/ GIMT_Encode4(71338), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4013 // |
| 25857 | /* 71293 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25858 | /* 71297 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3913:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 25859 | /* 71297 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25860 | /* 71300 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25861 | /* 71304 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25862 | /* 71309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32), |
| 25863 | /* 71312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25864 | /* 71314 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25865 | /* 71316 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25866 | /* 71318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25867 | /* 71321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25868 | /* 71327 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25869 | /* 71333 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25870 | /* 71336 */ GIR_RootConstrainSelectedInstOperands, |
| 25871 | /* 71337 */ // GIR_Coverage, 4013, |
| 25872 | /* 71337 */ GIR_EraseRootFromParent_Done, |
| 25873 | /* 71338 */ // Label 2219: @71338 |
| 25874 | /* 71338 */ GIM_Reject, |
| 25875 | /* 71339 */ // Label 2217: @71339 |
| 25876 | /* 71339 */ GIM_Reject, |
| 25877 | /* 71340 */ // Label 2210: @71340 |
| 25878 | /* 71340 */ GIM_Reject, |
| 25879 | /* 71341 */ // Label 2206: @71341 |
| 25880 | /* 71341 */ GIM_Try, /*On fail goto*//*Label 2220*/ GIMT_Encode4(71779), |
| 25881 | /* 71346 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub), |
| 25882 | /* 71351 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2224*/ GIMT_Encode4(71778), |
| 25883 | /* 71362 */ /*GILLT_v16s8*//*Label 2221*/ GIMT_Encode4(71382), GIMT_Encode4(0), |
| 25884 | /* 71370 */ /*GILLT_v8s16*//*Label 2222*/ GIMT_Encode4(71514), GIMT_Encode4(0), |
| 25885 | /* 71378 */ /*GILLT_v4s32*//*Label 2223*/ GIMT_Encode4(71646), |
| 25886 | /* 71382 */ // Label 2221: @71382 |
| 25887 | /* 71382 */ GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(71513), |
| 25888 | /* 71387 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 25889 | /* 71390 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 25890 | /* 71393 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25891 | /* 71396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25892 | /* 71400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25893 | /* 71404 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25894 | /* 71408 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2226*/ GIMT_Encode4(71460), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4014 // |
| 25895 | /* 71415 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25896 | /* 71419 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3914:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25897 | /* 71419 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25898 | /* 71422 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25899 | /* 71426 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25900 | /* 71431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs8), |
| 25901 | /* 71434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25902 | /* 71436 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25903 | /* 71438 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25904 | /* 71440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25905 | /* 71443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25906 | /* 71449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25907 | /* 71455 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25908 | /* 71458 */ GIR_RootConstrainSelectedInstOperands, |
| 25909 | /* 71459 */ // GIR_Coverage, 4014, |
| 25910 | /* 71459 */ GIR_EraseRootFromParent_Done, |
| 25911 | /* 71460 */ // Label 2226: @71460 |
| 25912 | /* 71460 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2227*/ GIMT_Encode4(71512), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4023 // |
| 25913 | /* 71467 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25914 | /* 71471 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3914:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 25915 | /* 71471 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25916 | /* 71474 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25917 | /* 71478 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25918 | /* 71483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu8), |
| 25919 | /* 71486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25920 | /* 71488 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25921 | /* 71490 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25922 | /* 71492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25923 | /* 71495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25924 | /* 71501 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25925 | /* 71507 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25926 | /* 71510 */ GIR_RootConstrainSelectedInstOperands, |
| 25927 | /* 71511 */ // GIR_Coverage, 4023, |
| 25928 | /* 71511 */ GIR_EraseRootFromParent_Done, |
| 25929 | /* 71512 */ // Label 2227: @71512 |
| 25930 | /* 71512 */ GIM_Reject, |
| 25931 | /* 71513 */ // Label 2225: @71513 |
| 25932 | /* 71513 */ GIM_Reject, |
| 25933 | /* 71514 */ // Label 2222: @71514 |
| 25934 | /* 71514 */ GIM_Try, /*On fail goto*//*Label 2228*/ GIMT_Encode4(71645), |
| 25935 | /* 71519 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 25936 | /* 71522 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 25937 | /* 71525 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25938 | /* 71528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25939 | /* 71532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25940 | /* 71536 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25941 | /* 71540 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2229*/ GIMT_Encode4(71592), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4017 // |
| 25942 | /* 71547 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25943 | /* 71551 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3914:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25944 | /* 71551 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25945 | /* 71554 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25946 | /* 71558 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25947 | /* 71563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs16), |
| 25948 | /* 71566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25949 | /* 71568 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25950 | /* 71570 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25951 | /* 71572 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25952 | /* 71575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25953 | /* 71581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25954 | /* 71587 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25955 | /* 71590 */ GIR_RootConstrainSelectedInstOperands, |
| 25956 | /* 71591 */ // GIR_Coverage, 4017, |
| 25957 | /* 71591 */ GIR_EraseRootFromParent_Done, |
| 25958 | /* 71592 */ // Label 2229: @71592 |
| 25959 | /* 71592 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2230*/ GIMT_Encode4(71644), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4026 // |
| 25960 | /* 71599 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 25961 | /* 71603 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3914:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 25962 | /* 71603 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25963 | /* 71606 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25964 | /* 71610 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25965 | /* 71615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu16), |
| 25966 | /* 71618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25967 | /* 71620 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25968 | /* 71622 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25969 | /* 71624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25970 | /* 71627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25971 | /* 71633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 25972 | /* 71639 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 25973 | /* 71642 */ GIR_RootConstrainSelectedInstOperands, |
| 25974 | /* 71643 */ // GIR_Coverage, 4026, |
| 25975 | /* 71643 */ GIR_EraseRootFromParent_Done, |
| 25976 | /* 71644 */ // Label 2230: @71644 |
| 25977 | /* 71644 */ GIM_Reject, |
| 25978 | /* 71645 */ // Label 2228: @71645 |
| 25979 | /* 71645 */ GIM_Reject, |
| 25980 | /* 71646 */ // Label 2223: @71646 |
| 25981 | /* 71646 */ GIM_Try, /*On fail goto*//*Label 2231*/ GIMT_Encode4(71777), |
| 25982 | /* 71651 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 25983 | /* 71654 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 25984 | /* 71657 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 25985 | /* 71660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25986 | /* 71664 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25987 | /* 71668 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 25988 | /* 71672 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2232*/ GIMT_Encode4(71724), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4020 // |
| 25989 | /* 71679 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 25990 | /* 71683 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3914:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 25991 | /* 71683 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 25992 | /* 71686 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 25993 | /* 71690 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 25994 | /* 71695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs32), |
| 25995 | /* 71698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 25996 | /* 71700 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 25997 | /* 71702 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 25998 | /* 71704 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25999 | /* 71707 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26000 | /* 71713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26001 | /* 71719 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26002 | /* 71722 */ GIR_RootConstrainSelectedInstOperands, |
| 26003 | /* 71723 */ // GIR_Coverage, 4020, |
| 26004 | /* 71723 */ GIR_EraseRootFromParent_Done, |
| 26005 | /* 71724 */ // Label 2232: @71724 |
| 26006 | /* 71724 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2233*/ GIMT_Encode4(71776), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4029 // |
| 26007 | /* 71731 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26008 | /* 71735 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3914:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26009 | /* 71735 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26010 | /* 71738 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26011 | /* 71742 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26012 | /* 71747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu32), |
| 26013 | /* 71750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26014 | /* 71752 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26015 | /* 71754 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26016 | /* 71756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26017 | /* 71759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26018 | /* 71765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26019 | /* 71771 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26020 | /* 71774 */ GIR_RootConstrainSelectedInstOperands, |
| 26021 | /* 71775 */ // GIR_Coverage, 4029, |
| 26022 | /* 71775 */ GIR_EraseRootFromParent_Done, |
| 26023 | /* 71776 */ // Label 2233: @71776 |
| 26024 | /* 71776 */ GIM_Reject, |
| 26025 | /* 71777 */ // Label 2231: @71777 |
| 26026 | /* 71777 */ GIM_Reject, |
| 26027 | /* 71778 */ // Label 2224: @71778 |
| 26028 | /* 71778 */ GIM_Reject, |
| 26029 | /* 71779 */ // Label 2220: @71779 |
| 26030 | /* 71779 */ GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(71961), |
| 26031 | /* 71784 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd), |
| 26032 | /* 71789 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2237*/ GIMT_Encode4(71960), |
| 26033 | /* 71800 */ /*GILLT_v8s16*//*Label 2235*/ GIMT_Encode4(71812), GIMT_Encode4(0), |
| 26034 | /* 71808 */ /*GILLT_v4s32*//*Label 2236*/ GIMT_Encode4(71886), |
| 26035 | /* 71812 */ // Label 2235: @71812 |
| 26036 | /* 71812 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2238*/ GIMT_Encode4(71885), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4480 // |
| 26037 | /* 71819 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26038 | /* 71822 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26039 | /* 71825 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26040 | /* 71828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26041 | /* 71832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26042 | /* 71836 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26043 | /* 71840 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26044 | /* 71844 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3875:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 26045 | /* 71844 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26046 | /* 71847 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26047 | /* 71851 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26048 | /* 71856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16), |
| 26049 | /* 71859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26050 | /* 71861 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26051 | /* 71863 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26052 | /* 71865 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26053 | /* 71868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26054 | /* 71874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26055 | /* 71880 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26056 | /* 71883 */ GIR_RootConstrainSelectedInstOperands, |
| 26057 | /* 71884 */ // GIR_Coverage, 4480, |
| 26058 | /* 71884 */ GIR_EraseRootFromParent_Done, |
| 26059 | /* 71885 */ // Label 2238: @71885 |
| 26060 | /* 71885 */ GIM_Reject, |
| 26061 | /* 71886 */ // Label 2236: @71886 |
| 26062 | /* 71886 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2239*/ GIMT_Encode4(71959), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4478 // |
| 26063 | /* 71893 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26064 | /* 71896 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26065 | /* 71899 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26066 | /* 71902 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26067 | /* 71906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26068 | /* 71910 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26069 | /* 71914 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26070 | /* 71918 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3875:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 26071 | /* 71918 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26072 | /* 71921 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26073 | /* 71925 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26074 | /* 71930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32), |
| 26075 | /* 71933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26076 | /* 71935 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26077 | /* 71937 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26078 | /* 71939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26079 | /* 71942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26080 | /* 71948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26081 | /* 71954 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26082 | /* 71957 */ GIR_RootConstrainSelectedInstOperands, |
| 26083 | /* 71958 */ // GIR_Coverage, 4478, |
| 26084 | /* 71958 */ GIR_EraseRootFromParent_Done, |
| 26085 | /* 71959 */ // Label 2239: @71959 |
| 26086 | /* 71959 */ GIM_Reject, |
| 26087 | /* 71960 */ // Label 2237: @71960 |
| 26088 | /* 71960 */ GIM_Reject, |
| 26089 | /* 71961 */ // Label 2234: @71961 |
| 26090 | /* 71961 */ GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(72259), |
| 26091 | /* 71966 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly), |
| 26092 | /* 71971 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2243*/ GIMT_Encode4(72258), |
| 26093 | /* 71982 */ /*GILLT_v8s16*//*Label 2241*/ GIMT_Encode4(71994), GIMT_Encode4(0), |
| 26094 | /* 71990 */ /*GILLT_v4s32*//*Label 2242*/ GIMT_Encode4(72126), |
| 26095 | /* 71994 */ // Label 2241: @71994 |
| 26096 | /* 71994 */ GIM_Try, /*On fail goto*//*Label 2244*/ GIMT_Encode4(72125), |
| 26097 | /* 71999 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26098 | /* 72002 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26099 | /* 72005 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26100 | /* 72008 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26101 | /* 72012 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26102 | /* 72016 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26103 | /* 72020 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2245*/ GIMT_Encode4(72072), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4913 // |
| 26104 | /* 72027 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26105 | /* 72031 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3944:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26106 | /* 72031 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26107 | /* 72034 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26108 | /* 72038 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26109 | /* 72043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp8), |
| 26110 | /* 72046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26111 | /* 72048 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26112 | /* 72050 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26113 | /* 72052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26114 | /* 72055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26115 | /* 72061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26116 | /* 72067 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26117 | /* 72070 */ GIR_RootConstrainSelectedInstOperands, |
| 26118 | /* 72071 */ // GIR_Coverage, 4913, |
| 26119 | /* 72071 */ GIR_EraseRootFromParent_Done, |
| 26120 | /* 72072 */ // Label 2245: @72072 |
| 26121 | /* 72072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2246*/ GIMT_Encode4(72124), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4915 // |
| 26122 | /* 72079 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26123 | /* 72083 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3944:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26124 | /* 72083 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26125 | /* 72086 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26126 | /* 72090 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26127 | /* 72095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp8), |
| 26128 | /* 72098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26129 | /* 72100 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26130 | /* 72102 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26131 | /* 72104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26132 | /* 72107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26133 | /* 72113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26134 | /* 72119 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26135 | /* 72122 */ GIR_RootConstrainSelectedInstOperands, |
| 26136 | /* 72123 */ // GIR_Coverage, 4915, |
| 26137 | /* 72123 */ GIR_EraseRootFromParent_Done, |
| 26138 | /* 72124 */ // Label 2246: @72124 |
| 26139 | /* 72124 */ GIM_Reject, |
| 26140 | /* 72125 */ // Label 2244: @72125 |
| 26141 | /* 72125 */ GIM_Reject, |
| 26142 | /* 72126 */ // Label 2242: @72126 |
| 26143 | /* 72126 */ GIM_Try, /*On fail goto*//*Label 2247*/ GIMT_Encode4(72257), |
| 26144 | /* 72131 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26145 | /* 72134 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26146 | /* 72137 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26147 | /* 72140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26148 | /* 72144 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26149 | /* 72148 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26150 | /* 72152 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2248*/ GIMT_Encode4(72204), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4917 // |
| 26151 | /* 72159 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26152 | /* 72163 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3944:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26153 | /* 72163 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26154 | /* 72166 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26155 | /* 72170 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26156 | /* 72175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp16), |
| 26157 | /* 72178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26158 | /* 72180 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26159 | /* 72182 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26160 | /* 72184 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26161 | /* 72187 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26162 | /* 72193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26163 | /* 72199 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26164 | /* 72202 */ GIR_RootConstrainSelectedInstOperands, |
| 26165 | /* 72203 */ // GIR_Coverage, 4917, |
| 26166 | /* 72203 */ GIR_EraseRootFromParent_Done, |
| 26167 | /* 72204 */ // Label 2248: @72204 |
| 26168 | /* 72204 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2249*/ GIMT_Encode4(72256), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4919 // |
| 26169 | /* 72211 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26170 | /* 72215 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3944:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26171 | /* 72215 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26172 | /* 72218 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26173 | /* 72222 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26174 | /* 72227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp16), |
| 26175 | /* 72230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26176 | /* 72232 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26177 | /* 72234 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26178 | /* 72236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26179 | /* 72239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26180 | /* 72245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26181 | /* 72251 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26182 | /* 72254 */ GIR_RootConstrainSelectedInstOperands, |
| 26183 | /* 72255 */ // GIR_Coverage, 4919, |
| 26184 | /* 72255 */ GIR_EraseRootFromParent_Done, |
| 26185 | /* 72256 */ // Label 2249: @72256 |
| 26186 | /* 72256 */ GIM_Reject, |
| 26187 | /* 72257 */ // Label 2247: @72257 |
| 26188 | /* 72257 */ GIM_Reject, |
| 26189 | /* 72258 */ // Label 2243: @72258 |
| 26190 | /* 72258 */ GIM_Reject, |
| 26191 | /* 72259 */ // Label 2240: @72259 |
| 26192 | /* 72259 */ GIM_Try, /*On fail goto*//*Label 2250*/ GIMT_Encode4(72697), |
| 26193 | /* 72264 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh), |
| 26194 | /* 72269 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2254*/ GIMT_Encode4(72696), |
| 26195 | /* 72280 */ /*GILLT_v16s8*//*Label 2251*/ GIMT_Encode4(72300), GIMT_Encode4(0), |
| 26196 | /* 72288 */ /*GILLT_v8s16*//*Label 2252*/ GIMT_Encode4(72432), GIMT_Encode4(0), |
| 26197 | /* 72296 */ /*GILLT_v4s32*//*Label 2253*/ GIMT_Encode4(72564), |
| 26198 | /* 72300 */ // Label 2251: @72300 |
| 26199 | /* 72300 */ GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(72431), |
| 26200 | /* 72305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26201 | /* 72308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26202 | /* 72311 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26203 | /* 72314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26204 | /* 72318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26205 | /* 72322 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26206 | /* 72326 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2256*/ GIMT_Encode4(72378), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4946 // |
| 26207 | /* 72333 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26208 | /* 72337 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26209 | /* 72337 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26210 | /* 72340 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26211 | /* 72344 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26212 | /* 72349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8), |
| 26213 | /* 72352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26214 | /* 72354 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26215 | /* 72356 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26216 | /* 72358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26217 | /* 72361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26218 | /* 72367 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26219 | /* 72373 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26220 | /* 72376 */ GIR_RootConstrainSelectedInstOperands, |
| 26221 | /* 72377 */ // GIR_Coverage, 4946, |
| 26222 | /* 72377 */ GIR_EraseRootFromParent_Done, |
| 26223 | /* 72378 */ // Label 2256: @72378 |
| 26224 | /* 72378 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2257*/ GIMT_Encode4(72430), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4961 // |
| 26225 | /* 72385 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26226 | /* 72389 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26227 | /* 72389 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26228 | /* 72392 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26229 | /* 72396 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26230 | /* 72401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8), |
| 26231 | /* 72404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26232 | /* 72406 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26233 | /* 72408 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26234 | /* 72410 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26235 | /* 72413 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26236 | /* 72419 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26237 | /* 72425 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26238 | /* 72428 */ GIR_RootConstrainSelectedInstOperands, |
| 26239 | /* 72429 */ // GIR_Coverage, 4961, |
| 26240 | /* 72429 */ GIR_EraseRootFromParent_Done, |
| 26241 | /* 72430 */ // Label 2257: @72430 |
| 26242 | /* 72430 */ GIM_Reject, |
| 26243 | /* 72431 */ // Label 2255: @72431 |
| 26244 | /* 72431 */ GIM_Reject, |
| 26245 | /* 72432 */ // Label 2252: @72432 |
| 26246 | /* 72432 */ GIM_Try, /*On fail goto*//*Label 2258*/ GIMT_Encode4(72563), |
| 26247 | /* 72437 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26248 | /* 72440 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26249 | /* 72443 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26250 | /* 72446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26251 | /* 72450 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26252 | /* 72454 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26253 | /* 72458 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2259*/ GIMT_Encode4(72510), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4953 // |
| 26254 | /* 72465 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26255 | /* 72469 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26256 | /* 72469 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26257 | /* 72472 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26258 | /* 72476 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26259 | /* 72481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16), |
| 26260 | /* 72484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26261 | /* 72486 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26262 | /* 72488 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26263 | /* 72490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26264 | /* 72493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26265 | /* 72499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26266 | /* 72505 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26267 | /* 72508 */ GIR_RootConstrainSelectedInstOperands, |
| 26268 | /* 72509 */ // GIR_Coverage, 4953, |
| 26269 | /* 72509 */ GIR_EraseRootFromParent_Done, |
| 26270 | /* 72510 */ // Label 2259: @72510 |
| 26271 | /* 72510 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2260*/ GIMT_Encode4(72562), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4965 // |
| 26272 | /* 72517 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26273 | /* 72521 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26274 | /* 72521 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26275 | /* 72524 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26276 | /* 72528 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26277 | /* 72533 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16), |
| 26278 | /* 72536 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26279 | /* 72538 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26280 | /* 72540 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26281 | /* 72542 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26282 | /* 72545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26283 | /* 72551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26284 | /* 72557 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26285 | /* 72560 */ GIR_RootConstrainSelectedInstOperands, |
| 26286 | /* 72561 */ // GIR_Coverage, 4965, |
| 26287 | /* 72561 */ GIR_EraseRootFromParent_Done, |
| 26288 | /* 72562 */ // Label 2260: @72562 |
| 26289 | /* 72562 */ GIM_Reject, |
| 26290 | /* 72563 */ // Label 2258: @72563 |
| 26291 | /* 72563 */ GIM_Reject, |
| 26292 | /* 72564 */ // Label 2253: @72564 |
| 26293 | /* 72564 */ GIM_Try, /*On fail goto*//*Label 2261*/ GIMT_Encode4(72695), |
| 26294 | /* 72569 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26295 | /* 72572 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26296 | /* 72575 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26297 | /* 72578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26298 | /* 72582 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26299 | /* 72586 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26300 | /* 72590 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2262*/ GIMT_Encode4(72642), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4957 // |
| 26301 | /* 72597 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26302 | /* 72601 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3942:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26303 | /* 72601 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26304 | /* 72604 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26305 | /* 72608 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26306 | /* 72613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32), |
| 26307 | /* 72616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26308 | /* 72618 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26309 | /* 72620 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26310 | /* 72622 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26311 | /* 72625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26312 | /* 72631 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26313 | /* 72637 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26314 | /* 72640 */ GIR_RootConstrainSelectedInstOperands, |
| 26315 | /* 72641 */ // GIR_Coverage, 4957, |
| 26316 | /* 72641 */ GIR_EraseRootFromParent_Done, |
| 26317 | /* 72642 */ // Label 2262: @72642 |
| 26318 | /* 72642 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2263*/ GIMT_Encode4(72694), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4969 // |
| 26319 | /* 72649 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26320 | /* 72653 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3942:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26321 | /* 72653 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26322 | /* 72656 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26323 | /* 72660 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26324 | /* 72665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32), |
| 26325 | /* 72668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26326 | /* 72670 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26327 | /* 72672 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26328 | /* 72674 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26329 | /* 72677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26330 | /* 72683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26331 | /* 72689 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26332 | /* 72692 */ GIR_RootConstrainSelectedInstOperands, |
| 26333 | /* 72693 */ // GIR_Coverage, 4969, |
| 26334 | /* 72693 */ GIR_EraseRootFromParent_Done, |
| 26335 | /* 72694 */ // Label 2263: @72694 |
| 26336 | /* 72694 */ GIM_Reject, |
| 26337 | /* 72695 */ // Label 2261: @72695 |
| 26338 | /* 72695 */ GIM_Reject, |
| 26339 | /* 72696 */ // Label 2254: @72696 |
| 26340 | /* 72696 */ GIM_Reject, |
| 26341 | /* 72697 */ // Label 2250: @72697 |
| 26342 | /* 72697 */ GIM_Try, /*On fail goto*//*Label 2264*/ GIMT_Encode4(73135), |
| 26343 | /* 72702 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh), |
| 26344 | /* 72707 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2268*/ GIMT_Encode4(73134), |
| 26345 | /* 72718 */ /*GILLT_v16s8*//*Label 2265*/ GIMT_Encode4(72738), GIMT_Encode4(0), |
| 26346 | /* 72726 */ /*GILLT_v8s16*//*Label 2266*/ GIMT_Encode4(72870), GIMT_Encode4(0), |
| 26347 | /* 72734 */ /*GILLT_v4s32*//*Label 2267*/ GIMT_Encode4(73002), |
| 26348 | /* 72738 */ // Label 2265: @72738 |
| 26349 | /* 72738 */ GIM_Try, /*On fail goto*//*Label 2269*/ GIMT_Encode4(72869), |
| 26350 | /* 72743 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 26351 | /* 72746 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 26352 | /* 72749 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26353 | /* 72752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26354 | /* 72756 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26355 | /* 72760 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26356 | /* 72764 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2270*/ GIMT_Encode4(72816), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4970 // |
| 26357 | /* 72771 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26358 | /* 72775 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3982:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26359 | /* 72775 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26360 | /* 72778 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26361 | /* 72782 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26362 | /* 72787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs8), |
| 26363 | /* 72790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26364 | /* 72792 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26365 | /* 72794 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26366 | /* 72796 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26367 | /* 72799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26368 | /* 72805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26369 | /* 72811 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26370 | /* 72814 */ GIR_RootConstrainSelectedInstOperands, |
| 26371 | /* 72815 */ // GIR_Coverage, 4970, |
| 26372 | /* 72815 */ GIR_EraseRootFromParent_Done, |
| 26373 | /* 72816 */ // Label 2270: @72816 |
| 26374 | /* 72816 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2271*/ GIMT_Encode4(72868), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4976 // |
| 26375 | /* 72823 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26376 | /* 72827 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3982:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 26377 | /* 72827 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26378 | /* 72830 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26379 | /* 72834 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26380 | /* 72839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu8), |
| 26381 | /* 72842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26382 | /* 72844 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26383 | /* 72846 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26384 | /* 72848 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26385 | /* 72851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26386 | /* 72857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26387 | /* 72863 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26388 | /* 72866 */ GIR_RootConstrainSelectedInstOperands, |
| 26389 | /* 72867 */ // GIR_Coverage, 4976, |
| 26390 | /* 72867 */ GIR_EraseRootFromParent_Done, |
| 26391 | /* 72868 */ // Label 2271: @72868 |
| 26392 | /* 72868 */ GIM_Reject, |
| 26393 | /* 72869 */ // Label 2269: @72869 |
| 26394 | /* 72869 */ GIM_Reject, |
| 26395 | /* 72870 */ // Label 2266: @72870 |
| 26396 | /* 72870 */ GIM_Try, /*On fail goto*//*Label 2272*/ GIMT_Encode4(73001), |
| 26397 | /* 72875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26398 | /* 72878 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26399 | /* 72881 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26400 | /* 72884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26401 | /* 72888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26402 | /* 72892 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26403 | /* 72896 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2273*/ GIMT_Encode4(72948), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4972 // |
| 26404 | /* 72903 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26405 | /* 72907 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3982:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26406 | /* 72907 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26407 | /* 72910 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26408 | /* 72914 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26409 | /* 72919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs16), |
| 26410 | /* 72922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26411 | /* 72924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26412 | /* 72926 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26413 | /* 72928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26414 | /* 72931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26415 | /* 72937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26416 | /* 72943 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26417 | /* 72946 */ GIR_RootConstrainSelectedInstOperands, |
| 26418 | /* 72947 */ // GIR_Coverage, 4972, |
| 26419 | /* 72947 */ GIR_EraseRootFromParent_Done, |
| 26420 | /* 72948 */ // Label 2273: @72948 |
| 26421 | /* 72948 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2274*/ GIMT_Encode4(73000), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4978 // |
| 26422 | /* 72955 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26423 | /* 72959 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3982:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26424 | /* 72959 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26425 | /* 72962 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26426 | /* 72966 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26427 | /* 72971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu16), |
| 26428 | /* 72974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26429 | /* 72976 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26430 | /* 72978 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26431 | /* 72980 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26432 | /* 72983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26433 | /* 72989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26434 | /* 72995 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26435 | /* 72998 */ GIR_RootConstrainSelectedInstOperands, |
| 26436 | /* 72999 */ // GIR_Coverage, 4978, |
| 26437 | /* 72999 */ GIR_EraseRootFromParent_Done, |
| 26438 | /* 73000 */ // Label 2274: @73000 |
| 26439 | /* 73000 */ GIM_Reject, |
| 26440 | /* 73001 */ // Label 2272: @73001 |
| 26441 | /* 73001 */ GIM_Reject, |
| 26442 | /* 73002 */ // Label 2267: @73002 |
| 26443 | /* 73002 */ GIM_Try, /*On fail goto*//*Label 2275*/ GIMT_Encode4(73133), |
| 26444 | /* 73007 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26445 | /* 73010 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26446 | /* 73013 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26447 | /* 73016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26448 | /* 73020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26449 | /* 73024 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26450 | /* 73028 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2276*/ GIMT_Encode4(73080), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4974 // |
| 26451 | /* 73035 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26452 | /* 73039 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3982:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26453 | /* 73039 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26454 | /* 73042 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26455 | /* 73046 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26456 | /* 73051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs32), |
| 26457 | /* 73054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26458 | /* 73056 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26459 | /* 73058 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26460 | /* 73060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26461 | /* 73063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26462 | /* 73069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26463 | /* 73075 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26464 | /* 73078 */ GIR_RootConstrainSelectedInstOperands, |
| 26465 | /* 73079 */ // GIR_Coverage, 4974, |
| 26466 | /* 73079 */ GIR_EraseRootFromParent_Done, |
| 26467 | /* 73080 */ // Label 2276: @73080 |
| 26468 | /* 73080 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2277*/ GIMT_Encode4(73132), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4980 // |
| 26469 | /* 73087 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26470 | /* 73091 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3982:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26471 | /* 73091 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26472 | /* 73094 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26473 | /* 73098 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26474 | /* 73103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu32), |
| 26475 | /* 73106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26476 | /* 73108 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26477 | /* 73110 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26478 | /* 73112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26479 | /* 73115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26480 | /* 73121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26481 | /* 73127 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26482 | /* 73130 */ GIR_RootConstrainSelectedInstOperands, |
| 26483 | /* 73131 */ // GIR_Coverage, 4980, |
| 26484 | /* 73131 */ GIR_EraseRootFromParent_Done, |
| 26485 | /* 73132 */ // Label 2277: @73132 |
| 26486 | /* 73132 */ GIM_Reject, |
| 26487 | /* 73133 */ // Label 2275: @73133 |
| 26488 | /* 73133 */ GIM_Reject, |
| 26489 | /* 73134 */ // Label 2268: @73134 |
| 26490 | /* 73134 */ GIM_Reject, |
| 26491 | /* 73135 */ // Label 2264: @73135 |
| 26492 | /* 73135 */ GIM_Try, /*On fail goto*//*Label 2278*/ GIMT_Encode4(73244), |
| 26493 | /* 73140 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow), |
| 26494 | /* 73145 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 26495 | /* 73148 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26496 | /* 73151 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26497 | /* 73154 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26498 | /* 73157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26499 | /* 73161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26500 | /* 73165 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26501 | /* 73169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2279*/ GIMT_Encode4(73206), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5031 // |
| 26502 | /* 73176 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26503 | /* 73180 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3897:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf16f32bh:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm) |
| 26504 | /* 73180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32bh), |
| 26505 | /* 73183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26506 | /* 73185 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 26507 | /* 73187 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 26508 | /* 73189 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26509 | /* 73192 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26510 | /* 73198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26511 | /* 73204 */ GIR_RootConstrainSelectedInstOperands, |
| 26512 | /* 73205 */ // GIR_Coverage, 5031, |
| 26513 | /* 73205 */ GIR_EraseRootFromParent_Done, |
| 26514 | /* 73206 */ // Label 2279: @73206 |
| 26515 | /* 73206 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2280*/ GIMT_Encode4(73243), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5037 // |
| 26516 | /* 73213 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26517 | /* 73217 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3897:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf16f32th:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm) |
| 26518 | /* 73217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32th), |
| 26519 | /* 73220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26520 | /* 73222 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 26521 | /* 73224 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 26522 | /* 73226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26523 | /* 73229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26524 | /* 73235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26525 | /* 73241 */ GIR_RootConstrainSelectedInstOperands, |
| 26526 | /* 73242 */ // GIR_Coverage, 5037, |
| 26527 | /* 73242 */ GIR_EraseRootFromParent_Done, |
| 26528 | /* 73243 */ // Label 2280: @73243 |
| 26529 | /* 73243 */ GIM_Reject, |
| 26530 | /* 73244 */ // Label 2278: @73244 |
| 26531 | /* 73244 */ GIM_Try, /*On fail goto*//*Label 2281*/ GIMT_Encode4(73538), |
| 26532 | /* 73249 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull), |
| 26533 | /* 73254 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2284*/ GIMT_Encode4(73537), |
| 26534 | /* 73265 */ /*GILLT_v4s32*//*Label 2282*/ GIMT_Encode4(73273), |
| 26535 | /* 73269 */ /*GILLT_v2s64*//*Label 2283*/ GIMT_Encode4(73405), |
| 26536 | /* 73273 */ // Label 2282: @73273 |
| 26537 | /* 73273 */ GIM_Try, /*On fail goto*//*Label 2285*/ GIMT_Encode4(73404), |
| 26538 | /* 73278 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26539 | /* 73281 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26540 | /* 73284 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26541 | /* 73287 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26542 | /* 73291 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26543 | /* 73295 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26544 | /* 73299 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2286*/ GIMT_Encode4(73351), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5055 // |
| 26545 | /* 73306 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26546 | /* 73310 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3952:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26547 | /* 73310 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26548 | /* 73313 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26549 | /* 73317 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26550 | /* 73322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16bh), |
| 26551 | /* 73325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26552 | /* 73327 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26553 | /* 73329 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26554 | /* 73331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26555 | /* 73334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26556 | /* 73340 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26557 | /* 73346 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26558 | /* 73349 */ GIR_RootConstrainSelectedInstOperands, |
| 26559 | /* 73350 */ // GIR_Coverage, 5055, |
| 26560 | /* 73350 */ GIR_EraseRootFromParent_Done, |
| 26561 | /* 73351 */ // Label 2286: @73351 |
| 26562 | /* 73351 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2287*/ GIMT_Encode4(73403), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5057 // |
| 26563 | /* 73358 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26564 | /* 73362 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3952:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 26565 | /* 73362 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26566 | /* 73365 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26567 | /* 73369 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26568 | /* 73374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16th), |
| 26569 | /* 73377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26570 | /* 73379 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26571 | /* 73381 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26572 | /* 73383 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26573 | /* 73386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26574 | /* 73392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26575 | /* 73398 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26576 | /* 73401 */ GIR_RootConstrainSelectedInstOperands, |
| 26577 | /* 73402 */ // GIR_Coverage, 5057, |
| 26578 | /* 73402 */ GIR_EraseRootFromParent_Done, |
| 26579 | /* 73403 */ // Label 2287: @73403 |
| 26580 | /* 73403 */ GIM_Reject, |
| 26581 | /* 73404 */ // Label 2285: @73404 |
| 26582 | /* 73404 */ GIM_Reject, |
| 26583 | /* 73405 */ // Label 2283: @73405 |
| 26584 | /* 73405 */ GIM_Try, /*On fail goto*//*Label 2288*/ GIMT_Encode4(73536), |
| 26585 | /* 73410 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26586 | /* 73413 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26587 | /* 73416 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26588 | /* 73419 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26589 | /* 73423 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26590 | /* 73427 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26591 | /* 73431 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2289*/ GIMT_Encode4(73483), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5059 // |
| 26592 | /* 73438 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 26593 | /* 73442 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3952:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs32bh:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26594 | /* 73442 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26595 | /* 73445 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26596 | /* 73449 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26597 | /* 73454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32bh), |
| 26598 | /* 73457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26599 | /* 73459 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26600 | /* 73461 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26601 | /* 73463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26602 | /* 73466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26603 | /* 73472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26604 | /* 73478 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26605 | /* 73481 */ GIR_RootConstrainSelectedInstOperands, |
| 26606 | /* 73482 */ // GIR_Coverage, 5059, |
| 26607 | /* 73482 */ GIR_EraseRootFromParent_Done, |
| 26608 | /* 73483 */ // Label 2289: @73483 |
| 26609 | /* 73483 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2290*/ GIMT_Encode4(73535), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5061 // |
| 26610 | /* 73490 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 26611 | /* 73494 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3952:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs32th:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 26612 | /* 73494 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26613 | /* 73497 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26614 | /* 73501 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26615 | /* 73506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32th), |
| 26616 | /* 73509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26617 | /* 73511 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 26618 | /* 73513 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26619 | /* 73515 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26620 | /* 73518 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26621 | /* 73524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26622 | /* 73530 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26623 | /* 73533 */ GIR_RootConstrainSelectedInstOperands, |
| 26624 | /* 73534 */ // GIR_Coverage, 5061, |
| 26625 | /* 73534 */ GIR_EraseRootFromParent_Done, |
| 26626 | /* 73535 */ // Label 2290: @73535 |
| 26627 | /* 73535 */ GIM_Reject, |
| 26628 | /* 73536 */ // Label 2288: @73536 |
| 26629 | /* 73536 */ GIM_Reject, |
| 26630 | /* 73537 */ // Label 2284: @73537 |
| 26631 | /* 73537 */ GIM_Reject, |
| 26632 | /* 73538 */ // Label 2281: @73538 |
| 26633 | /* 73538 */ GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(73728), |
| 26634 | /* 73543 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma), |
| 26635 | /* 73548 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2294*/ GIMT_Encode4(73727), |
| 26636 | /* 73559 */ /*GILLT_v8s16*//*Label 2292*/ GIMT_Encode4(73571), GIMT_Encode4(0), |
| 26637 | /* 73567 */ /*GILLT_v4s32*//*Label 2293*/ GIMT_Encode4(73649), |
| 26638 | /* 73571 */ // Label 2292: @73571 |
| 26639 | /* 73571 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2295*/ GIMT_Encode4(73648), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4441 // |
| 26640 | /* 73578 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26641 | /* 73581 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26642 | /* 73584 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 26643 | /* 73587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26644 | /* 73591 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 26645 | /* 73595 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 26646 | /* 73599 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 26647 | /* 73603 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26648 | /* 73608 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26649 | /* 73612 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26650 | /* 73616 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26651 | /* 73618 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3817:{ *:[iPTR] }, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 26652 | /* 73618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16), |
| 26653 | /* 73621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26654 | /* 73623 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 26655 | /* 73625 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 26656 | /* 73629 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2 |
| 26657 | /* 73631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26658 | /* 73634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26659 | /* 73640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26660 | /* 73646 */ GIR_RootConstrainSelectedInstOperands, |
| 26661 | /* 73647 */ // GIR_Coverage, 4441, |
| 26662 | /* 73647 */ GIR_EraseRootFromParent_Done, |
| 26663 | /* 73648 */ // Label 2295: @73648 |
| 26664 | /* 73648 */ GIM_Reject, |
| 26665 | /* 73649 */ // Label 2293: @73649 |
| 26666 | /* 73649 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2296*/ GIMT_Encode4(73726), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4427 // |
| 26667 | /* 73656 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26668 | /* 73659 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26669 | /* 73662 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26670 | /* 73665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26671 | /* 73669 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 26672 | /* 73673 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 26673 | /* 73677 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 26674 | /* 73681 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26675 | /* 73686 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26676 | /* 73690 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26677 | /* 73694 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26678 | /* 73696 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3817:{ *:[iPTR] }, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 26679 | /* 73696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32), |
| 26680 | /* 73699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26681 | /* 73701 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 26682 | /* 73703 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 26683 | /* 73707 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2 |
| 26684 | /* 73709 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26685 | /* 73712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26686 | /* 73718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26687 | /* 73724 */ GIR_RootConstrainSelectedInstOperands, |
| 26688 | /* 73725 */ // GIR_Coverage, 4427, |
| 26689 | /* 73725 */ GIR_EraseRootFromParent_Done, |
| 26690 | /* 73726 */ // Label 2296: @73726 |
| 26691 | /* 73726 */ GIM_Reject, |
| 26692 | /* 73727 */ // Label 2294: @73727 |
| 26693 | /* 73727 */ GIM_Reject, |
| 26694 | /* 73728 */ // Label 2291: @73728 |
| 26695 | /* 73728 */ GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(73928), |
| 26696 | /* 73733 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq), |
| 26697 | /* 73738 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2300*/ GIMT_Encode4(73927), |
| 26698 | /* 73749 */ /*GILLT_v8s16*//*Label 2298*/ GIMT_Encode4(73761), GIMT_Encode4(0), |
| 26699 | /* 73757 */ /*GILLT_v4s32*//*Label 2299*/ GIMT_Encode4(73844), |
| 26700 | /* 73761 */ // Label 2298: @73761 |
| 26701 | /* 73761 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2301*/ GIMT_Encode4(73843), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4885 // |
| 26702 | /* 73768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26703 | /* 73771 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26704 | /* 73774 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 26705 | /* 73777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26706 | /* 73781 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 26707 | /* 73785 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 26708 | /* 73789 */ // MIs[1] Operand 1 |
| 26709 | /* 73789 */ // No operand predicates |
| 26710 | /* 73789 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26711 | /* 73793 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26712 | /* 73797 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26713 | /* 73799 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3886:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 26714 | /* 73799 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26715 | /* 73802 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26716 | /* 73806 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26717 | /* 73811 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf16), |
| 26718 | /* 73814 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26719 | /* 73816 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26720 | /* 73818 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm |
| 26721 | /* 73820 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 26722 | /* 73823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26723 | /* 73826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26724 | /* 73832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26725 | /* 73838 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26726 | /* 73841 */ GIR_RootConstrainSelectedInstOperands, |
| 26727 | /* 73842 */ // GIR_Coverage, 4885, |
| 26728 | /* 73842 */ GIR_EraseRootFromParent_Done, |
| 26729 | /* 73843 */ // Label 2301: @73843 |
| 26730 | /* 73843 */ GIM_Reject, |
| 26731 | /* 73844 */ // Label 2299: @73844 |
| 26732 | /* 73844 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2302*/ GIMT_Encode4(73926), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4887 // |
| 26733 | /* 73851 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26734 | /* 73854 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26735 | /* 73857 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26736 | /* 73860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26737 | /* 73864 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 26738 | /* 73868 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 26739 | /* 73872 */ // MIs[1] Operand 1 |
| 26740 | /* 73872 */ // No operand predicates |
| 26741 | /* 73872 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26742 | /* 73876 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26743 | /* 73880 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26744 | /* 73882 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3886:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 26745 | /* 73882 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 26746 | /* 73885 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 26747 | /* 73889 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 26748 | /* 73894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf32), |
| 26749 | /* 73897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26750 | /* 73899 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 26751 | /* 73901 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm |
| 26752 | /* 73903 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 26753 | /* 73906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26754 | /* 73909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26755 | /* 73915 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26756 | /* 73921 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 26757 | /* 73924 */ GIR_RootConstrainSelectedInstOperands, |
| 26758 | /* 73925 */ // GIR_Coverage, 4887, |
| 26759 | /* 73925 */ GIR_EraseRootFromParent_Done, |
| 26760 | /* 73926 */ // Label 2302: @73926 |
| 26761 | /* 73926 */ GIM_Reject, |
| 26762 | /* 73927 */ // Label 2300: @73927 |
| 26763 | /* 73927 */ GIM_Reject, |
| 26764 | /* 73928 */ // Label 2297: @73928 |
| 26765 | /* 73928 */ GIM_Try, /*On fail goto*//*Label 2303*/ GIMT_Encode4(74118), |
| 26766 | /* 73933 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma), |
| 26767 | /* 73938 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2306*/ GIMT_Encode4(74117), |
| 26768 | /* 73949 */ /*GILLT_v8s16*//*Label 2304*/ GIMT_Encode4(73961), GIMT_Encode4(0), |
| 26769 | /* 73957 */ /*GILLT_v4s32*//*Label 2305*/ GIMT_Encode4(74039), |
| 26770 | /* 73961 */ // Label 2304: @73961 |
| 26771 | /* 73961 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2307*/ GIMT_Encode4(74038), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4442 // |
| 26772 | /* 73968 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 26773 | /* 73971 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 26774 | /* 73974 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 26775 | /* 73977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26776 | /* 73981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26777 | /* 73985 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 26778 | /* 73989 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 26779 | /* 73993 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 26780 | /* 73997 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26781 | /* 74002 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26782 | /* 74006 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26783 | /* 74008 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3817:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$m1, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m2), MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 26784 | /* 74008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16), |
| 26785 | /* 74011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26786 | /* 74013 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 26787 | /* 74015 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1 |
| 26788 | /* 74017 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m2 |
| 26789 | /* 74021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26790 | /* 74024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26791 | /* 74030 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26792 | /* 74036 */ GIR_RootConstrainSelectedInstOperands, |
| 26793 | /* 74037 */ // GIR_Coverage, 4442, |
| 26794 | /* 74037 */ GIR_EraseRootFromParent_Done, |
| 26795 | /* 74038 */ // Label 2307: @74038 |
| 26796 | /* 74038 */ GIM_Reject, |
| 26797 | /* 74039 */ // Label 2305: @74039 |
| 26798 | /* 74039 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2308*/ GIMT_Encode4(74116), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4428 // |
| 26799 | /* 74046 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 26800 | /* 74049 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 26801 | /* 74052 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 26802 | /* 74055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26803 | /* 74059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26804 | /* 74063 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 26805 | /* 74067 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 26806 | /* 74071 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 26807 | /* 74075 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26808 | /* 74080 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 26809 | /* 74084 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 26810 | /* 74086 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3817:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$m1, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m2), MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 26811 | /* 74086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32), |
| 26812 | /* 74089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 26813 | /* 74091 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 26814 | /* 74093 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1 |
| 26815 | /* 74095 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m2 |
| 26816 | /* 74099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26817 | /* 74102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26818 | /* 74108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26819 | /* 74114 */ GIR_RootConstrainSelectedInstOperands, |
| 26820 | /* 74115 */ // GIR_Coverage, 4428, |
| 26821 | /* 74115 */ GIR_EraseRootFromParent_Done, |
| 26822 | /* 74116 */ // Label 2308: @74116 |
| 26823 | /* 74116 */ GIM_Reject, |
| 26824 | /* 74117 */ // Label 2306: @74117 |
| 26825 | /* 74117 */ GIM_Reject, |
| 26826 | /* 74118 */ // Label 2303: @74118 |
| 26827 | /* 74118 */ GIM_Try, /*On fail goto*//*Label 2309*/ GIMT_Encode4(74231), |
| 26828 | /* 74123 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8), |
| 26829 | /* 74128 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26830 | /* 74131 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26831 | /* 74134 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26832 | /* 74137 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26833 | /* 74140 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2310*/ GIMT_Encode4(74185), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 145 // |
| 26834 | /* 74147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26835 | /* 74151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26836 | /* 74155 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26837 | /* 74159 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 26838 | /* 74163 */ // (intrinsic_wo_chain:{ *:[i32] } 4224:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (USADA8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) |
| 26839 | /* 74163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USADA8), |
| 26840 | /* 74166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 26841 | /* 74168 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 26842 | /* 74170 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 26843 | /* 74172 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 26844 | /* 74174 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26845 | /* 74177 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26846 | /* 74183 */ GIR_RootConstrainSelectedInstOperands, |
| 26847 | /* 74184 */ // GIR_Coverage, 145, |
| 26848 | /* 74184 */ GIR_EraseRootFromParent_Done, |
| 26849 | /* 74185 */ // Label 2310: @74185 |
| 26850 | /* 74185 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2311*/ GIMT_Encode4(74230), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 468 // |
| 26851 | /* 74192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26852 | /* 74196 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26853 | /* 74200 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26854 | /* 74204 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26855 | /* 74208 */ // (intrinsic_wo_chain:{ *:[i32] } 4224:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2USADA8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 26856 | /* 74208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USADA8), |
| 26857 | /* 74211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 26858 | /* 74213 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 26859 | /* 74215 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 26860 | /* 74217 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 26861 | /* 74219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26862 | /* 74222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26863 | /* 74228 */ GIR_RootConstrainSelectedInstOperands, |
| 26864 | /* 74229 */ // GIR_Coverage, 468, |
| 26865 | /* 74229 */ GIR_EraseRootFromParent_Done, |
| 26866 | /* 74230 */ // Label 2311: @74230 |
| 26867 | /* 74230 */ GIM_Reject, |
| 26868 | /* 74231 */ // Label 2309: @74231 |
| 26869 | /* 74231 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2312*/ GIMT_Encode4(74293), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 527 // |
| 26870 | /* 74238 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad), |
| 26871 | /* 74243 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26872 | /* 74246 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26873 | /* 74249 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26874 | /* 74252 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26875 | /* 74255 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26876 | /* 74259 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26877 | /* 74263 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26878 | /* 74267 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26879 | /* 74271 */ // (intrinsic_wo_chain:{ *:[i32] } 4169:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 26880 | /* 74271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAD), |
| 26881 | /* 74274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 26882 | /* 74276 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 26883 | /* 74278 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 26884 | /* 74280 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 26885 | /* 74282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26886 | /* 74285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26887 | /* 74291 */ GIR_RootConstrainSelectedInstOperands, |
| 26888 | /* 74292 */ // GIR_Coverage, 527, |
| 26889 | /* 74292 */ GIR_EraseRootFromParent_Done, |
| 26890 | /* 74293 */ // Label 2312: @74293 |
| 26891 | /* 74293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2313*/ GIMT_Encode4(74355), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 528 // |
| 26892 | /* 74300 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx), |
| 26893 | /* 74305 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26894 | /* 74308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26895 | /* 74311 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26896 | /* 74314 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26897 | /* 74317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26898 | /* 74321 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26899 | /* 74325 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26900 | /* 74329 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26901 | /* 74333 */ // (intrinsic_wo_chain:{ *:[i32] } 4170:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 26902 | /* 74333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLADX), |
| 26903 | /* 74336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 26904 | /* 74338 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 26905 | /* 74340 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 26906 | /* 74342 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 26907 | /* 74344 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26908 | /* 74347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26909 | /* 74353 */ GIR_RootConstrainSelectedInstOperands, |
| 26910 | /* 74354 */ // GIR_Coverage, 528, |
| 26911 | /* 74354 */ GIR_EraseRootFromParent_Done, |
| 26912 | /* 74355 */ // Label 2313: @74355 |
| 26913 | /* 74355 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2314*/ GIMT_Encode4(74417), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 529 // |
| 26914 | /* 74362 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd), |
| 26915 | /* 74367 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26916 | /* 74370 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26917 | /* 74373 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26918 | /* 74376 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26919 | /* 74379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26920 | /* 74383 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26921 | /* 74387 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26922 | /* 74391 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26923 | /* 74395 */ // (intrinsic_wo_chain:{ *:[i32] } 4177:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 26924 | /* 74395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSD), |
| 26925 | /* 74398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 26926 | /* 74400 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 26927 | /* 74402 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 26928 | /* 74404 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 26929 | /* 74406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26930 | /* 74409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26931 | /* 74415 */ GIR_RootConstrainSelectedInstOperands, |
| 26932 | /* 74416 */ // GIR_Coverage, 529, |
| 26933 | /* 74416 */ GIR_EraseRootFromParent_Done, |
| 26934 | /* 74417 */ // Label 2314: @74417 |
| 26935 | /* 74417 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2315*/ GIMT_Encode4(74479), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 530 // |
| 26936 | /* 74424 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx), |
| 26937 | /* 74429 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 26938 | /* 74432 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 26939 | /* 74435 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 26940 | /* 74438 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 26941 | /* 74441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26942 | /* 74445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26943 | /* 74449 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26944 | /* 74453 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 26945 | /* 74457 */ // (intrinsic_wo_chain:{ *:[i32] } 4178:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) |
| 26946 | /* 74457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSDX), |
| 26947 | /* 74460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 26948 | /* 74462 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 26949 | /* 74464 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 26950 | /* 74466 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 26951 | /* 74468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 26952 | /* 74471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 26953 | /* 74477 */ GIR_RootConstrainSelectedInstOperands, |
| 26954 | /* 74478 */ // GIR_Coverage, 530, |
| 26955 | /* 74478 */ GIR_EraseRootFromParent_Done, |
| 26956 | /* 74479 */ // Label 2315: @74479 |
| 26957 | /* 74479 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2316*/ GIMT_Encode4(74532), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1113 // |
| 26958 | /* 74486 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot), |
| 26959 | /* 74491 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 26960 | /* 74494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 26961 | /* 74497 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 26962 | /* 74500 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 26963 | /* 74503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26964 | /* 74507 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26965 | /* 74511 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26966 | /* 74515 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26967 | /* 74519 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4030:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 26968 | /* 74519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTD), |
| 26969 | /* 74522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 26970 | /* 74524 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 26971 | /* 74526 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 26972 | /* 74528 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 26973 | /* 74530 */ GIR_RootConstrainSelectedInstOperands, |
| 26974 | /* 74531 */ // GIR_Coverage, 1113, |
| 26975 | /* 74531 */ GIR_EraseRootFromParent_Done, |
| 26976 | /* 74532 */ // Label 2316: @74532 |
| 26977 | /* 74532 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2317*/ GIMT_Encode4(74585), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1114 // |
| 26978 | /* 74539 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot), |
| 26979 | /* 74544 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 26980 | /* 74547 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 26981 | /* 74550 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 26982 | /* 74553 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 26983 | /* 74556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26984 | /* 74560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26985 | /* 74564 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26986 | /* 74568 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 26987 | /* 74572 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4018:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 26988 | /* 74572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTD), |
| 26989 | /* 74575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 26990 | /* 74577 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 26991 | /* 74579 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 26992 | /* 74581 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 26993 | /* 74583 */ GIR_RootConstrainSelectedInstOperands, |
| 26994 | /* 74584 */ // GIR_Coverage, 1114, |
| 26995 | /* 74584 */ GIR_EraseRootFromParent_Done, |
| 26996 | /* 74585 */ // Label 2317: @74585 |
| 26997 | /* 74585 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2318*/ GIMT_Encode4(74638), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1115 // |
| 26998 | /* 74592 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot), |
| 26999 | /* 74597 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27000 | /* 74600 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27001 | /* 74603 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27002 | /* 74606 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27003 | /* 74609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27004 | /* 74613 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27005 | /* 74617 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27006 | /* 74621 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27007 | /* 74625 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4030:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 27008 | /* 74625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTQ), |
| 27009 | /* 74628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27010 | /* 74630 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27011 | /* 74632 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27012 | /* 74634 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27013 | /* 74636 */ GIR_RootConstrainSelectedInstOperands, |
| 27014 | /* 74637 */ // GIR_Coverage, 1115, |
| 27015 | /* 74637 */ GIR_EraseRootFromParent_Done, |
| 27016 | /* 74638 */ // Label 2318: @74638 |
| 27017 | /* 74638 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2319*/ GIMT_Encode4(74691), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1116 // |
| 27018 | /* 74645 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot), |
| 27019 | /* 74650 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27020 | /* 74653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27021 | /* 74656 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27022 | /* 74659 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27023 | /* 74662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27024 | /* 74666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27025 | /* 74670 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27026 | /* 74674 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27027 | /* 74678 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4018:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 27028 | /* 74678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTQ), |
| 27029 | /* 74681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27030 | /* 74683 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27031 | /* 74685 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27032 | /* 74687 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27033 | /* 74689 */ GIR_RootConstrainSelectedInstOperands, |
| 27034 | /* 74690 */ // GIR_Coverage, 1116, |
| 27035 | /* 74690 */ GIR_EraseRootFromParent_Done, |
| 27036 | /* 74691 */ // Label 2319: @74691 |
| 27037 | /* 74691 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2320*/ GIMT_Encode4(74744), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1117 // |
| 27038 | /* 74698 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_smmla), |
| 27039 | /* 74703 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27040 | /* 74706 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27041 | /* 74709 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27042 | /* 74712 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27043 | /* 74715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27044 | /* 74719 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27045 | /* 74723 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27046 | /* 74727 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27047 | /* 74731 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4029:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 27048 | /* 74731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSMMLA), |
| 27049 | /* 74734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27050 | /* 74736 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27051 | /* 74738 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27052 | /* 74740 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27053 | /* 74742 */ GIR_RootConstrainSelectedInstOperands, |
| 27054 | /* 74743 */ // GIR_Coverage, 1117, |
| 27055 | /* 74743 */ GIR_EraseRootFromParent_Done, |
| 27056 | /* 74744 */ // Label 2320: @74744 |
| 27057 | /* 74744 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2321*/ GIMT_Encode4(74797), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1118 // |
| 27058 | /* 74751 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_ummla), |
| 27059 | /* 74756 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27060 | /* 74759 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27061 | /* 74762 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27062 | /* 74765 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27063 | /* 74768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27064 | /* 74772 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27065 | /* 74776 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27066 | /* 74780 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27067 | /* 74784 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4031:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 27068 | /* 74784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUMMLA), |
| 27069 | /* 74787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27070 | /* 74789 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27071 | /* 74791 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27072 | /* 74793 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27073 | /* 74795 */ GIR_RootConstrainSelectedInstOperands, |
| 27074 | /* 74796 */ // GIR_Coverage, 1118, |
| 27075 | /* 74796 */ GIR_EraseRootFromParent_Done, |
| 27076 | /* 74797 */ // Label 2321: @74797 |
| 27077 | /* 74797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2322*/ GIMT_Encode4(74850), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1119 // |
| 27078 | /* 74804 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usmmla), |
| 27079 | /* 74809 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27080 | /* 74812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27081 | /* 74815 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27082 | /* 74818 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27083 | /* 74821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27084 | /* 74825 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27085 | /* 74829 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27086 | /* 74833 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27087 | /* 74837 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4033:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 27088 | /* 74837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSMMLA), |
| 27089 | /* 74840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27090 | /* 74842 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27091 | /* 74844 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27092 | /* 74846 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27093 | /* 74848 */ GIR_RootConstrainSelectedInstOperands, |
| 27094 | /* 74849 */ // GIR_Coverage, 1119, |
| 27095 | /* 74849 */ GIR_EraseRootFromParent_Done, |
| 27096 | /* 74850 */ // Label 2322: @74850 |
| 27097 | /* 74850 */ GIM_Try, /*On fail goto*//*Label 2323*/ GIMT_Encode4(74972), |
| 27098 | /* 74855 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot), |
| 27099 | /* 74860 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 2326*/ GIMT_Encode4(74971), |
| 27100 | /* 74871 */ /*GILLT_v2s32*//*Label 2324*/ GIMT_Encode4(74879), |
| 27101 | /* 74875 */ /*GILLT_v4s32*//*Label 2325*/ GIMT_Encode4(74925), |
| 27102 | /* 74879 */ // Label 2324: @74879 |
| 27103 | /* 74879 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2327*/ GIMT_Encode4(74924), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1120 // |
| 27104 | /* 74886 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 27105 | /* 74889 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 27106 | /* 74892 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 27107 | /* 74895 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27108 | /* 74899 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27109 | /* 74903 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27110 | /* 74907 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27111 | /* 74911 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4032:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 27112 | /* 74911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTD), |
| 27113 | /* 74914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27114 | /* 74916 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27115 | /* 74918 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27116 | /* 74920 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27117 | /* 74922 */ GIR_RootConstrainSelectedInstOperands, |
| 27118 | /* 74923 */ // GIR_Coverage, 1120, |
| 27119 | /* 74923 */ GIR_EraseRootFromParent_Done, |
| 27120 | /* 74924 */ // Label 2327: @74924 |
| 27121 | /* 74924 */ GIM_Reject, |
| 27122 | /* 74925 */ // Label 2325: @74925 |
| 27123 | /* 74925 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2328*/ GIMT_Encode4(74970), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1121 // |
| 27124 | /* 74932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27125 | /* 74935 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27126 | /* 74938 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 27127 | /* 74941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27128 | /* 74945 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27129 | /* 74949 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27130 | /* 74953 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27131 | /* 74957 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4032:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 27132 | /* 74957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTQ), |
| 27133 | /* 74960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 27134 | /* 74962 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd |
| 27135 | /* 74964 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27136 | /* 74966 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27137 | /* 74968 */ GIR_RootConstrainSelectedInstOperands, |
| 27138 | /* 74969 */ // GIR_Coverage, 1121, |
| 27139 | /* 74969 */ GIR_EraseRootFromParent_Done, |
| 27140 | /* 74970 */ // Label 2328: @74970 |
| 27141 | /* 74970 */ GIM_Reject, |
| 27142 | /* 74971 */ // Label 2326: @74971 |
| 27143 | /* 74971 */ GIM_Reject, |
| 27144 | /* 74972 */ // Label 2323: @74972 |
| 27145 | /* 74972 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2329*/ GIMT_Encode4(75034), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1852 // |
| 27146 | /* 74979 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx1), |
| 27147 | /* 74984 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 27148 | /* 74987 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 27149 | /* 74990 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 27150 | /* 74993 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 27151 | /* 74996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27152 | /* 75000 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27153 | /* 75004 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27154 | /* 75008 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27155 | /* 75012 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4144:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VTBX1:{ *:[v8i8] } DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 27156 | /* 75012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX1), |
| 27157 | /* 75015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27158 | /* 75017 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 27159 | /* 75019 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27160 | /* 75021 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27161 | /* 75023 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27162 | /* 75026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27163 | /* 75032 */ GIR_RootConstrainSelectedInstOperands, |
| 27164 | /* 75033 */ // GIR_Coverage, 1852, |
| 27165 | /* 75033 */ GIR_EraseRootFromParent_Done, |
| 27166 | /* 75034 */ // Label 2329: @75034 |
| 27167 | /* 75034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2330*/ GIMT_Encode4(75087), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1907 // |
| 27168 | /* 75041 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su0), |
| 27169 | /* 75046 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27170 | /* 75049 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27171 | /* 75052 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27172 | /* 75055 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27173 | /* 75058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27174 | /* 75062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27175 | /* 75066 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27176 | /* 75070 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27177 | /* 75074 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4023:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 27178 | /* 75074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU0), |
| 27179 | /* 75077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27180 | /* 75079 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 27181 | /* 75081 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27182 | /* 75083 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27183 | /* 75085 */ GIR_RootConstrainSelectedInstOperands, |
| 27184 | /* 75086 */ // GIR_Coverage, 1907, |
| 27185 | /* 75086 */ GIR_EraseRootFromParent_Done, |
| 27186 | /* 75087 */ // Label 2330: @75087 |
| 27187 | /* 75087 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2331*/ GIMT_Encode4(75140), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1908 // |
| 27188 | /* 75094 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h), |
| 27189 | /* 75099 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27190 | /* 75102 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27191 | /* 75105 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27192 | /* 75108 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27193 | /* 75111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27194 | /* 75115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27195 | /* 75119 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27196 | /* 75123 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27197 | /* 75127 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4025:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 27198 | /* 75127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H), |
| 27199 | /* 75130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27200 | /* 75132 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 27201 | /* 75134 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27202 | /* 75136 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27203 | /* 75138 */ GIR_RootConstrainSelectedInstOperands, |
| 27204 | /* 75139 */ // GIR_Coverage, 1908, |
| 27205 | /* 75139 */ GIR_EraseRootFromParent_Done, |
| 27206 | /* 75140 */ // Label 2331: @75140 |
| 27207 | /* 75140 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2332*/ GIMT_Encode4(75193), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1909 // |
| 27208 | /* 75147 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h2), |
| 27209 | /* 75152 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27210 | /* 75155 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27211 | /* 75158 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27212 | /* 75161 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27213 | /* 75164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27214 | /* 75168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27215 | /* 75172 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27216 | /* 75176 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27217 | /* 75180 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4026:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H2:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 27218 | /* 75180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H2), |
| 27219 | /* 75183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27220 | /* 75185 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 27221 | /* 75187 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27222 | /* 75189 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27223 | /* 75191 */ GIR_RootConstrainSelectedInstOperands, |
| 27224 | /* 75192 */ // GIR_Coverage, 1909, |
| 27225 | /* 75192 */ GIR_EraseRootFromParent_Done, |
| 27226 | /* 75193 */ // Label 2332: @75193 |
| 27227 | /* 75193 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2333*/ GIMT_Encode4(75246), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1910 // |
| 27228 | /* 75200 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su1), |
| 27229 | /* 75205 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 27230 | /* 75208 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27231 | /* 75211 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27232 | /* 75214 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27233 | /* 75217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27234 | /* 75221 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27235 | /* 75225 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27236 | /* 75229 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27237 | /* 75233 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4028:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 27238 | /* 75233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU1), |
| 27239 | /* 75236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27240 | /* 75238 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 27241 | /* 75240 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27242 | /* 75242 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27243 | /* 75244 */ GIR_RootConstrainSelectedInstOperands, |
| 27244 | /* 75245 */ // GIR_Coverage, 1910, |
| 27245 | /* 75245 */ GIR_EraseRootFromParent_Done, |
| 27246 | /* 75246 */ // Label 2333: @75246 |
| 27247 | /* 75246 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2334*/ GIMT_Encode4(75308), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2087 // |
| 27248 | /* 75253 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad), |
| 27249 | /* 75258 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27250 | /* 75261 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27251 | /* 75264 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27252 | /* 75267 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27253 | /* 75270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27254 | /* 75274 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27255 | /* 75278 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27256 | /* 75282 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27257 | /* 75286 */ // (intrinsic_wo_chain:{ *:[i32] } 4169:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 27258 | /* 75286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAD), |
| 27259 | /* 75289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27260 | /* 75291 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 27261 | /* 75293 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 27262 | /* 75295 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 27263 | /* 75297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27264 | /* 75300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27265 | /* 75306 */ GIR_RootConstrainSelectedInstOperands, |
| 27266 | /* 75307 */ // GIR_Coverage, 2087, |
| 27267 | /* 75307 */ GIR_EraseRootFromParent_Done, |
| 27268 | /* 75308 */ // Label 2334: @75308 |
| 27269 | /* 75308 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2335*/ GIMT_Encode4(75370), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2088 // |
| 27270 | /* 75315 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx), |
| 27271 | /* 75320 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27272 | /* 75323 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27273 | /* 75326 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27274 | /* 75329 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27275 | /* 75332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27276 | /* 75336 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27277 | /* 75340 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27278 | /* 75344 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27279 | /* 75348 */ // (intrinsic_wo_chain:{ *:[i32] } 4170:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 27280 | /* 75348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLADX), |
| 27281 | /* 75351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27282 | /* 75353 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 27283 | /* 75355 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 27284 | /* 75357 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 27285 | /* 75359 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27286 | /* 75362 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27287 | /* 75368 */ GIR_RootConstrainSelectedInstOperands, |
| 27288 | /* 75369 */ // GIR_Coverage, 2088, |
| 27289 | /* 75369 */ GIR_EraseRootFromParent_Done, |
| 27290 | /* 75370 */ // Label 2335: @75370 |
| 27291 | /* 75370 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2336*/ GIMT_Encode4(75432), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2089 // |
| 27292 | /* 75377 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd), |
| 27293 | /* 75382 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27294 | /* 75385 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27295 | /* 75388 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27296 | /* 75391 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27297 | /* 75394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27298 | /* 75398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27299 | /* 75402 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27300 | /* 75406 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27301 | /* 75410 */ // (intrinsic_wo_chain:{ *:[i32] } 4177:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 27302 | /* 75410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSD), |
| 27303 | /* 75413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27304 | /* 75415 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 27305 | /* 75417 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 27306 | /* 75419 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 27307 | /* 75421 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27308 | /* 75424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27309 | /* 75430 */ GIR_RootConstrainSelectedInstOperands, |
| 27310 | /* 75431 */ // GIR_Coverage, 2089, |
| 27311 | /* 75431 */ GIR_EraseRootFromParent_Done, |
| 27312 | /* 75432 */ // Label 2336: @75432 |
| 27313 | /* 75432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2337*/ GIMT_Encode4(75494), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2090 // |
| 27314 | /* 75439 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx), |
| 27315 | /* 75444 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27316 | /* 75447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27317 | /* 75450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27318 | /* 75453 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27319 | /* 75456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27320 | /* 75460 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27321 | /* 75464 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27322 | /* 75468 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27323 | /* 75472 */ // (intrinsic_wo_chain:{ *:[i32] } 4178:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra) |
| 27324 | /* 75472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSDX), |
| 27325 | /* 75475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27326 | /* 75477 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 27327 | /* 75479 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 27328 | /* 75481 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra |
| 27329 | /* 75483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27330 | /* 75486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27331 | /* 75492 */ GIR_RootConstrainSelectedInstOperands, |
| 27332 | /* 75493 */ // GIR_Coverage, 2090, |
| 27333 | /* 75493 */ GIR_EraseRootFromParent_Done, |
| 27334 | /* 75494 */ // Label 2337: @75494 |
| 27335 | /* 75494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2338*/ GIMT_Encode4(75556), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2183 // |
| 27336 | /* 75501 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb), |
| 27337 | /* 75506 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27338 | /* 75509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27339 | /* 75512 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27340 | /* 75515 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27341 | /* 75518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27342 | /* 75522 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27343 | /* 75526 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27344 | /* 75530 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27345 | /* 75534 */ // (intrinsic_wo_chain:{ *:[i32] } 4167:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27346 | /* 75534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB), |
| 27347 | /* 75537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27348 | /* 75539 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27349 | /* 75541 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27350 | /* 75543 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27351 | /* 75545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27352 | /* 75548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27353 | /* 75554 */ GIR_RootConstrainSelectedInstOperands, |
| 27354 | /* 75555 */ // GIR_Coverage, 2183, |
| 27355 | /* 75555 */ GIR_EraseRootFromParent_Done, |
| 27356 | /* 75556 */ // Label 2338: @75556 |
| 27357 | /* 75556 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2339*/ GIMT_Encode4(75618), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2184 // |
| 27358 | /* 75563 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt), |
| 27359 | /* 75568 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27360 | /* 75571 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27361 | /* 75574 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27362 | /* 75577 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27363 | /* 75580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27364 | /* 75584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27365 | /* 75588 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27366 | /* 75592 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27367 | /* 75596 */ // (intrinsic_wo_chain:{ *:[i32] } 4168:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27368 | /* 75596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT), |
| 27369 | /* 75599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27370 | /* 75601 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27371 | /* 75603 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27372 | /* 75605 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27373 | /* 75607 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27374 | /* 75610 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27375 | /* 75616 */ GIR_RootConstrainSelectedInstOperands, |
| 27376 | /* 75617 */ // GIR_Coverage, 2184, |
| 27377 | /* 75617 */ GIR_EraseRootFromParent_Done, |
| 27378 | /* 75618 */ // Label 2339: @75618 |
| 27379 | /* 75618 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2340*/ GIMT_Encode4(75680), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2185 // |
| 27380 | /* 75625 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb), |
| 27381 | /* 75630 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27382 | /* 75633 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27383 | /* 75636 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27384 | /* 75639 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27385 | /* 75642 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27386 | /* 75646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27387 | /* 75650 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27388 | /* 75654 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27389 | /* 75658 */ // (intrinsic_wo_chain:{ *:[i32] } 4173:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27390 | /* 75658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB), |
| 27391 | /* 75661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27392 | /* 75663 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27393 | /* 75665 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27394 | /* 75667 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27395 | /* 75669 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27396 | /* 75672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27397 | /* 75678 */ GIR_RootConstrainSelectedInstOperands, |
| 27398 | /* 75679 */ // GIR_Coverage, 2185, |
| 27399 | /* 75679 */ GIR_EraseRootFromParent_Done, |
| 27400 | /* 75680 */ // Label 2340: @75680 |
| 27401 | /* 75680 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2341*/ GIMT_Encode4(75742), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2186 // |
| 27402 | /* 75687 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt), |
| 27403 | /* 75692 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27404 | /* 75695 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27405 | /* 75698 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27406 | /* 75701 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27407 | /* 75704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27408 | /* 75708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27409 | /* 75712 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27410 | /* 75716 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27411 | /* 75720 */ // (intrinsic_wo_chain:{ *:[i32] } 4174:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27412 | /* 75720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT), |
| 27413 | /* 75723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27414 | /* 75725 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27415 | /* 75727 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27416 | /* 75729 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27417 | /* 75731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27418 | /* 75734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27419 | /* 75740 */ GIR_RootConstrainSelectedInstOperands, |
| 27420 | /* 75741 */ // GIR_Coverage, 2186, |
| 27421 | /* 75741 */ GIR_EraseRootFromParent_Done, |
| 27422 | /* 75742 */ // Label 2341: @75742 |
| 27423 | /* 75742 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2342*/ GIMT_Encode4(75804), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2187 // |
| 27424 | /* 75749 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb), |
| 27425 | /* 75754 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27426 | /* 75757 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27427 | /* 75760 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27428 | /* 75763 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27429 | /* 75766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27430 | /* 75770 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27431 | /* 75774 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27432 | /* 75778 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27433 | /* 75782 */ // (intrinsic_wo_chain:{ *:[i32] } 4175:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27434 | /* 75782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWB), |
| 27435 | /* 75785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27436 | /* 75787 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27437 | /* 75789 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27438 | /* 75791 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27439 | /* 75793 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27440 | /* 75796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27441 | /* 75802 */ GIR_RootConstrainSelectedInstOperands, |
| 27442 | /* 75803 */ // GIR_Coverage, 2187, |
| 27443 | /* 75803 */ GIR_EraseRootFromParent_Done, |
| 27444 | /* 75804 */ // Label 2342: @75804 |
| 27445 | /* 75804 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2343*/ GIMT_Encode4(75866), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2188 // |
| 27446 | /* 75811 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt), |
| 27447 | /* 75816 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27448 | /* 75819 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27449 | /* 75822 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27450 | /* 75825 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27451 | /* 75828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 27452 | /* 75832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27453 | /* 75836 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27454 | /* 75840 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27455 | /* 75844 */ // (intrinsic_wo_chain:{ *:[i32] } 4176:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27456 | /* 75844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWT), |
| 27457 | /* 75847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27458 | /* 75849 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27459 | /* 75851 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27460 | /* 75853 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27461 | /* 75855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27462 | /* 75858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27463 | /* 75864 */ GIR_RootConstrainSelectedInstOperands, |
| 27464 | /* 75865 */ // GIR_Coverage, 2188, |
| 27465 | /* 75865 */ GIR_EraseRootFromParent_Done, |
| 27466 | /* 75866 */ // Label 2343: @75866 |
| 27467 | /* 75866 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2344*/ GIMT_Encode4(75928), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2375 // |
| 27468 | /* 75873 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb), |
| 27469 | /* 75878 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27470 | /* 75881 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27471 | /* 75884 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27472 | /* 75887 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27473 | /* 75890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27474 | /* 75894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27475 | /* 75898 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27476 | /* 75902 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27477 | /* 75906 */ // (intrinsic_wo_chain:{ *:[i32] } 4167:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27478 | /* 75906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB), |
| 27479 | /* 75909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27480 | /* 75911 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27481 | /* 75913 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27482 | /* 75915 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27483 | /* 75917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27484 | /* 75920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27485 | /* 75926 */ GIR_RootConstrainSelectedInstOperands, |
| 27486 | /* 75927 */ // GIR_Coverage, 2375, |
| 27487 | /* 75927 */ GIR_EraseRootFromParent_Done, |
| 27488 | /* 75928 */ // Label 2344: @75928 |
| 27489 | /* 75928 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2345*/ GIMT_Encode4(75990), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2376 // |
| 27490 | /* 75935 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt), |
| 27491 | /* 75940 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27492 | /* 75943 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27493 | /* 75946 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27494 | /* 75949 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27495 | /* 75952 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27496 | /* 75956 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27497 | /* 75960 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27498 | /* 75964 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27499 | /* 75968 */ // (intrinsic_wo_chain:{ *:[i32] } 4168:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27500 | /* 75968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT), |
| 27501 | /* 75971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27502 | /* 75973 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27503 | /* 75975 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27504 | /* 75977 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27505 | /* 75979 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27506 | /* 75982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27507 | /* 75988 */ GIR_RootConstrainSelectedInstOperands, |
| 27508 | /* 75989 */ // GIR_Coverage, 2376, |
| 27509 | /* 75989 */ GIR_EraseRootFromParent_Done, |
| 27510 | /* 75990 */ // Label 2345: @75990 |
| 27511 | /* 75990 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2346*/ GIMT_Encode4(76052), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2377 // |
| 27512 | /* 75997 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb), |
| 27513 | /* 76002 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27514 | /* 76005 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27515 | /* 76008 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27516 | /* 76011 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27517 | /* 76014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27518 | /* 76018 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27519 | /* 76022 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27520 | /* 76026 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27521 | /* 76030 */ // (intrinsic_wo_chain:{ *:[i32] } 4173:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27522 | /* 76030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB), |
| 27523 | /* 76033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27524 | /* 76035 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27525 | /* 76037 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27526 | /* 76039 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27527 | /* 76041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27528 | /* 76044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27529 | /* 76050 */ GIR_RootConstrainSelectedInstOperands, |
| 27530 | /* 76051 */ // GIR_Coverage, 2377, |
| 27531 | /* 76051 */ GIR_EraseRootFromParent_Done, |
| 27532 | /* 76052 */ // Label 2346: @76052 |
| 27533 | /* 76052 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2347*/ GIMT_Encode4(76114), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2378 // |
| 27534 | /* 76059 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt), |
| 27535 | /* 76064 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27536 | /* 76067 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27537 | /* 76070 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27538 | /* 76073 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27539 | /* 76076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27540 | /* 76080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27541 | /* 76084 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27542 | /* 76088 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27543 | /* 76092 */ // (intrinsic_wo_chain:{ *:[i32] } 4174:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27544 | /* 76092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT), |
| 27545 | /* 76095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27546 | /* 76097 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27547 | /* 76099 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27548 | /* 76101 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27549 | /* 76103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27550 | /* 76106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27551 | /* 76112 */ GIR_RootConstrainSelectedInstOperands, |
| 27552 | /* 76113 */ // GIR_Coverage, 2378, |
| 27553 | /* 76113 */ GIR_EraseRootFromParent_Done, |
| 27554 | /* 76114 */ // Label 2347: @76114 |
| 27555 | /* 76114 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2348*/ GIMT_Encode4(76176), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2379 // |
| 27556 | /* 76121 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb), |
| 27557 | /* 76126 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27558 | /* 76129 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27559 | /* 76132 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27560 | /* 76135 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27561 | /* 76138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27562 | /* 76142 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27563 | /* 76146 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27564 | /* 76150 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27565 | /* 76154 */ // (intrinsic_wo_chain:{ *:[i32] } 4175:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27566 | /* 76154 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWB), |
| 27567 | /* 76157 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27568 | /* 76159 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27569 | /* 76161 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27570 | /* 76163 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27571 | /* 76165 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27572 | /* 76168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27573 | /* 76174 */ GIR_RootConstrainSelectedInstOperands, |
| 27574 | /* 76175 */ // GIR_Coverage, 2379, |
| 27575 | /* 76175 */ GIR_EraseRootFromParent_Done, |
| 27576 | /* 76176 */ // Label 2348: @76176 |
| 27577 | /* 76176 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2349*/ GIMT_Encode4(76238), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2380 // |
| 27578 | /* 76183 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt), |
| 27579 | /* 76188 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 27580 | /* 76191 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 27581 | /* 76194 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 27582 | /* 76197 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27583 | /* 76200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27584 | /* 76204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27585 | /* 76208 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27586 | /* 76212 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 27587 | /* 76216 */ // (intrinsic_wo_chain:{ *:[i32] } 4176:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) |
| 27588 | /* 76216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWT), |
| 27589 | /* 76219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 27590 | /* 76221 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 27591 | /* 76223 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 27592 | /* 76225 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc |
| 27593 | /* 76227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27594 | /* 76230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27595 | /* 76236 */ GIR_RootConstrainSelectedInstOperands, |
| 27596 | /* 76237 */ // GIR_Coverage, 2380, |
| 27597 | /* 76237 */ GIR_EraseRootFromParent_Done, |
| 27598 | /* 76238 */ // Label 2349: @76238 |
| 27599 | /* 76238 */ GIM_Try, /*On fail goto*//*Label 2350*/ GIMT_Encode4(76496), |
| 27600 | /* 76243 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah), |
| 27601 | /* 76248 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 2355*/ GIMT_Encode4(76495), |
| 27602 | /* 76259 */ /*GILLT_v4s16*//*Label 2351*/ GIMT_Encode4(76275), |
| 27603 | /* 76263 */ /*GILLT_v8s16*//*Label 2352*/ GIMT_Encode4(76330), |
| 27604 | /* 76267 */ /*GILLT_v2s32*//*Label 2353*/ GIMT_Encode4(76385), |
| 27605 | /* 76271 */ /*GILLT_v4s32*//*Label 2354*/ GIMT_Encode4(76440), |
| 27606 | /* 76275 */ // Label 2351: @76275 |
| 27607 | /* 76275 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2356*/ GIMT_Encode4(76329), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2853 // |
| 27608 | /* 76282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 27609 | /* 76285 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 27610 | /* 76288 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 27611 | /* 76291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27612 | /* 76295 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27613 | /* 76299 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27614 | /* 76303 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27615 | /* 76307 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4102:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLAHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 27616 | /* 76307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i16), |
| 27617 | /* 76310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27618 | /* 76312 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27619 | /* 76314 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27620 | /* 76316 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27621 | /* 76318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27622 | /* 76321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27623 | /* 76327 */ GIR_RootConstrainSelectedInstOperands, |
| 27624 | /* 76328 */ // GIR_Coverage, 2853, |
| 27625 | /* 76328 */ GIR_EraseRootFromParent_Done, |
| 27626 | /* 76329 */ // Label 2356: @76329 |
| 27627 | /* 76329 */ GIM_Reject, |
| 27628 | /* 76330 */ // Label 2352: @76330 |
| 27629 | /* 76330 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2357*/ GIMT_Encode4(76384), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2855 // |
| 27630 | /* 76337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27631 | /* 76340 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27632 | /* 76343 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27633 | /* 76346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27634 | /* 76350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27635 | /* 76354 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27636 | /* 76358 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27637 | /* 76362 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4102:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLAHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 27638 | /* 76362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv8i16), |
| 27639 | /* 76365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27640 | /* 76367 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27641 | /* 76369 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27642 | /* 76371 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27643 | /* 76373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27644 | /* 76376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27645 | /* 76382 */ GIR_RootConstrainSelectedInstOperands, |
| 27646 | /* 76383 */ // GIR_Coverage, 2855, |
| 27647 | /* 76383 */ GIR_EraseRootFromParent_Done, |
| 27648 | /* 76384 */ // Label 2357: @76384 |
| 27649 | /* 76384 */ GIM_Reject, |
| 27650 | /* 76385 */ // Label 2353: @76385 |
| 27651 | /* 76385 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2358*/ GIMT_Encode4(76439), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2854 // |
| 27652 | /* 76392 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 27653 | /* 76395 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 27654 | /* 76398 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32, |
| 27655 | /* 76401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27656 | /* 76405 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27657 | /* 76409 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27658 | /* 76413 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27659 | /* 76417 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4102:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLAHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 27660 | /* 76417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv2i32), |
| 27661 | /* 76420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27662 | /* 76422 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27663 | /* 76424 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27664 | /* 76426 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27665 | /* 76428 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27666 | /* 76431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27667 | /* 76437 */ GIR_RootConstrainSelectedInstOperands, |
| 27668 | /* 76438 */ // GIR_Coverage, 2854, |
| 27669 | /* 76438 */ GIR_EraseRootFromParent_Done, |
| 27670 | /* 76439 */ // Label 2358: @76439 |
| 27671 | /* 76439 */ GIM_Reject, |
| 27672 | /* 76440 */ // Label 2354: @76440 |
| 27673 | /* 76440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2359*/ GIMT_Encode4(76494), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2856 // |
| 27674 | /* 76447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27675 | /* 76450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27676 | /* 76453 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27677 | /* 76456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27678 | /* 76460 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27679 | /* 76464 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27680 | /* 76468 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27681 | /* 76472 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4102:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLAHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 27682 | /* 76472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i32), |
| 27683 | /* 76475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27684 | /* 76477 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27685 | /* 76479 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27686 | /* 76481 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27687 | /* 76483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27688 | /* 76486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27689 | /* 76492 */ GIR_RootConstrainSelectedInstOperands, |
| 27690 | /* 76493 */ // GIR_Coverage, 2856, |
| 27691 | /* 76493 */ GIR_EraseRootFromParent_Done, |
| 27692 | /* 76494 */ // Label 2359: @76494 |
| 27693 | /* 76494 */ GIM_Reject, |
| 27694 | /* 76495 */ // Label 2355: @76495 |
| 27695 | /* 76495 */ GIM_Reject, |
| 27696 | /* 76496 */ // Label 2350: @76496 |
| 27697 | /* 76496 */ GIM_Try, /*On fail goto*//*Label 2360*/ GIMT_Encode4(76754), |
| 27698 | /* 76501 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh), |
| 27699 | /* 76506 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 2365*/ GIMT_Encode4(76753), |
| 27700 | /* 76517 */ /*GILLT_v4s16*//*Label 2361*/ GIMT_Encode4(76533), |
| 27701 | /* 76521 */ /*GILLT_v8s16*//*Label 2362*/ GIMT_Encode4(76588), |
| 27702 | /* 76525 */ /*GILLT_v2s32*//*Label 2363*/ GIMT_Encode4(76643), |
| 27703 | /* 76529 */ /*GILLT_v4s32*//*Label 2364*/ GIMT_Encode4(76698), |
| 27704 | /* 76533 */ // Label 2361: @76533 |
| 27705 | /* 76533 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2366*/ GIMT_Encode4(76587), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2861 // |
| 27706 | /* 76540 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 27707 | /* 76543 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 27708 | /* 76546 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 27709 | /* 76549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27710 | /* 76553 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27711 | /* 76557 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27712 | /* 76561 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27713 | /* 76565 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4103:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLSHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 27714 | /* 76565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i16), |
| 27715 | /* 76568 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27716 | /* 76570 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27717 | /* 76572 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27718 | /* 76574 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27719 | /* 76576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27720 | /* 76579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27721 | /* 76585 */ GIR_RootConstrainSelectedInstOperands, |
| 27722 | /* 76586 */ // GIR_Coverage, 2861, |
| 27723 | /* 76586 */ GIR_EraseRootFromParent_Done, |
| 27724 | /* 76587 */ // Label 2366: @76587 |
| 27725 | /* 76587 */ GIM_Reject, |
| 27726 | /* 76588 */ // Label 2362: @76588 |
| 27727 | /* 76588 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2367*/ GIMT_Encode4(76642), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2863 // |
| 27728 | /* 76595 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27729 | /* 76598 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27730 | /* 76601 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27731 | /* 76604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27732 | /* 76608 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27733 | /* 76612 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27734 | /* 76616 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27735 | /* 76620 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4103:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLSHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 27736 | /* 76620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv8i16), |
| 27737 | /* 76623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27738 | /* 76625 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27739 | /* 76627 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27740 | /* 76629 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27741 | /* 76631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27742 | /* 76634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27743 | /* 76640 */ GIR_RootConstrainSelectedInstOperands, |
| 27744 | /* 76641 */ // GIR_Coverage, 2863, |
| 27745 | /* 76641 */ GIR_EraseRootFromParent_Done, |
| 27746 | /* 76642 */ // Label 2367: @76642 |
| 27747 | /* 76642 */ GIM_Reject, |
| 27748 | /* 76643 */ // Label 2363: @76643 |
| 27749 | /* 76643 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2368*/ GIMT_Encode4(76697), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2862 // |
| 27750 | /* 76650 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 27751 | /* 76653 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 27752 | /* 76656 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32, |
| 27753 | /* 76659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27754 | /* 76663 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27755 | /* 76667 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27756 | /* 76671 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 27757 | /* 76675 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4103:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLSHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 27758 | /* 76675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv2i32), |
| 27759 | /* 76678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27760 | /* 76680 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27761 | /* 76682 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27762 | /* 76684 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27763 | /* 76686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27764 | /* 76689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27765 | /* 76695 */ GIR_RootConstrainSelectedInstOperands, |
| 27766 | /* 76696 */ // GIR_Coverage, 2862, |
| 27767 | /* 76696 */ GIR_EraseRootFromParent_Done, |
| 27768 | /* 76697 */ // Label 2368: @76697 |
| 27769 | /* 76697 */ GIM_Reject, |
| 27770 | /* 76698 */ // Label 2364: @76698 |
| 27771 | /* 76698 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2369*/ GIMT_Encode4(76752), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2864 // |
| 27772 | /* 76705 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27773 | /* 76708 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27774 | /* 76711 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27775 | /* 76714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27776 | /* 76718 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27777 | /* 76722 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27778 | /* 76726 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 27779 | /* 76730 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4103:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLSHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 27780 | /* 76730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i32), |
| 27781 | /* 76733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 27782 | /* 76735 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 27783 | /* 76737 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn |
| 27784 | /* 76739 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm |
| 27785 | /* 76741 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 27786 | /* 76744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27787 | /* 76750 */ GIR_RootConstrainSelectedInstOperands, |
| 27788 | /* 76751 */ // GIR_Coverage, 2864, |
| 27789 | /* 76751 */ GIR_EraseRootFromParent_Done, |
| 27790 | /* 76752 */ // Label 2369: @76752 |
| 27791 | /* 76752 */ GIM_Reject, |
| 27792 | /* 76753 */ // Label 2365: @76753 |
| 27793 | /* 76753 */ GIM_Reject, |
| 27794 | /* 76754 */ // Label 2360: @76754 |
| 27795 | /* 76754 */ GIM_Try, /*On fail goto*//*Label 2370*/ GIMT_Encode4(76910), |
| 27796 | /* 76759 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma), |
| 27797 | /* 76764 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2373*/ GIMT_Encode4(76909), |
| 27798 | /* 76775 */ /*GILLT_v8s16*//*Label 2371*/ GIMT_Encode4(76787), GIMT_Encode4(0), |
| 27799 | /* 76783 */ /*GILLT_v4s32*//*Label 2372*/ GIMT_Encode4(76848), |
| 27800 | /* 76787 */ // Label 2371: @76787 |
| 27801 | /* 76787 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2374*/ GIMT_Encode4(76847), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4437 // |
| 27802 | /* 76794 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27803 | /* 76797 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27804 | /* 76800 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 27805 | /* 76803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27806 | /* 76807 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27807 | /* 76811 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27808 | /* 76815 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27809 | /* 76819 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3817:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 27810 | /* 76819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16), |
| 27811 | /* 76822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27812 | /* 76824 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 27813 | /* 76826 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1 |
| 27814 | /* 76828 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2 |
| 27815 | /* 76830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27816 | /* 76833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27817 | /* 76839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27818 | /* 76845 */ GIR_RootConstrainSelectedInstOperands, |
| 27819 | /* 76846 */ // GIR_Coverage, 4437, |
| 27820 | /* 76846 */ GIR_EraseRootFromParent_Done, |
| 27821 | /* 76847 */ // Label 2374: @76847 |
| 27822 | /* 76847 */ GIM_Reject, |
| 27823 | /* 76848 */ // Label 2372: @76848 |
| 27824 | /* 76848 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2375*/ GIMT_Encode4(76908), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4433 // |
| 27825 | /* 76855 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27826 | /* 76858 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27827 | /* 76861 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 27828 | /* 76864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27829 | /* 76868 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27830 | /* 76872 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27831 | /* 76876 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27832 | /* 76880 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3817:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 27833 | /* 76880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32), |
| 27834 | /* 76883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27835 | /* 76885 */ GIR_RootToRootCopy, /*OpIdx*/4, // add |
| 27836 | /* 76887 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1 |
| 27837 | /* 76889 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2 |
| 27838 | /* 76891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27839 | /* 76894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27840 | /* 76900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27841 | /* 76906 */ GIR_RootConstrainSelectedInstOperands, |
| 27842 | /* 76907 */ // GIR_Coverage, 4433, |
| 27843 | /* 76907 */ GIR_EraseRootFromParent_Done, |
| 27844 | /* 76908 */ // Label 2375: @76908 |
| 27845 | /* 76908 */ GIM_Reject, |
| 27846 | /* 76909 */ // Label 2373: @76909 |
| 27847 | /* 76909 */ GIM_Reject, |
| 27848 | /* 76910 */ // Label 2370: @76910 |
| 27849 | /* 76910 */ GIM_Try, /*On fail goto*//*Label 2376*/ GIMT_Encode4(77135), |
| 27850 | /* 76915 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah), |
| 27851 | /* 76920 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2380*/ GIMT_Encode4(77134), |
| 27852 | /* 76931 */ /*GILLT_v16s8*//*Label 2377*/ GIMT_Encode4(76951), GIMT_Encode4(0), |
| 27853 | /* 76939 */ /*GILLT_v8s16*//*Label 2378*/ GIMT_Encode4(77012), GIMT_Encode4(0), |
| 27854 | /* 76947 */ /*GILLT_v4s32*//*Label 2379*/ GIMT_Encode4(77073), |
| 27855 | /* 76951 */ // Label 2377: @76951 |
| 27856 | /* 76951 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2381*/ GIMT_Encode4(77011), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5366 // |
| 27857 | /* 76958 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27858 | /* 76961 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27859 | /* 76964 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27860 | /* 76967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27861 | /* 76971 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27862 | /* 76975 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27863 | /* 76979 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27864 | /* 76983 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3947:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 27865 | /* 76983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs8), |
| 27866 | /* 76986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27867 | /* 76988 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 27868 | /* 76990 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 27869 | /* 76992 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 27870 | /* 76994 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27871 | /* 76997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27872 | /* 77003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27873 | /* 77009 */ GIR_RootConstrainSelectedInstOperands, |
| 27874 | /* 77010 */ // GIR_Coverage, 5366, |
| 27875 | /* 77010 */ GIR_EraseRootFromParent_Done, |
| 27876 | /* 77011 */ // Label 2381: @77011 |
| 27877 | /* 77011 */ GIM_Reject, |
| 27878 | /* 77012 */ // Label 2378: @77012 |
| 27879 | /* 77012 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2382*/ GIMT_Encode4(77072), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5368 // |
| 27880 | /* 77019 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27881 | /* 77022 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27882 | /* 77025 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27883 | /* 77028 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27884 | /* 77032 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27885 | /* 77036 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27886 | /* 77040 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27887 | /* 77044 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3947:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 27888 | /* 77044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs16), |
| 27889 | /* 77047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27890 | /* 77049 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 27891 | /* 77051 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 27892 | /* 77053 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 27893 | /* 77055 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27894 | /* 77058 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27895 | /* 77064 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27896 | /* 77070 */ GIR_RootConstrainSelectedInstOperands, |
| 27897 | /* 77071 */ // GIR_Coverage, 5368, |
| 27898 | /* 77071 */ GIR_EraseRootFromParent_Done, |
| 27899 | /* 77072 */ // Label 2382: @77072 |
| 27900 | /* 77072 */ GIM_Reject, |
| 27901 | /* 77073 */ // Label 2379: @77073 |
| 27902 | /* 77073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2383*/ GIMT_Encode4(77133), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5370 // |
| 27903 | /* 77080 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27904 | /* 77083 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27905 | /* 77086 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27906 | /* 77089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27907 | /* 77093 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27908 | /* 77097 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27909 | /* 77101 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27910 | /* 77105 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3947:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 27911 | /* 77105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs32), |
| 27912 | /* 77108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27913 | /* 77110 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 27914 | /* 77112 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 27915 | /* 77114 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 27916 | /* 77116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27917 | /* 77119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27918 | /* 77125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27919 | /* 77131 */ GIR_RootConstrainSelectedInstOperands, |
| 27920 | /* 77132 */ // GIR_Coverage, 5370, |
| 27921 | /* 77132 */ GIR_EraseRootFromParent_Done, |
| 27922 | /* 77133 */ // Label 2383: @77133 |
| 27923 | /* 77133 */ GIM_Reject, |
| 27924 | /* 77134 */ // Label 2380: @77134 |
| 27925 | /* 77134 */ GIM_Reject, |
| 27926 | /* 77135 */ // Label 2376: @77135 |
| 27927 | /* 77135 */ GIM_Try, /*On fail goto*//*Label 2384*/ GIMT_Encode4(77360), |
| 27928 | /* 77140 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah), |
| 27929 | /* 77145 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2388*/ GIMT_Encode4(77359), |
| 27930 | /* 77156 */ /*GILLT_v16s8*//*Label 2385*/ GIMT_Encode4(77176), GIMT_Encode4(0), |
| 27931 | /* 77164 */ /*GILLT_v8s16*//*Label 2386*/ GIMT_Encode4(77237), GIMT_Encode4(0), |
| 27932 | /* 77172 */ /*GILLT_v4s32*//*Label 2387*/ GIMT_Encode4(77298), |
| 27933 | /* 77176 */ // Label 2385: @77176 |
| 27934 | /* 77176 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2389*/ GIMT_Encode4(77236), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5372 // |
| 27935 | /* 77183 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 27936 | /* 77186 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 27937 | /* 77189 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27938 | /* 77192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27939 | /* 77196 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27940 | /* 77200 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27941 | /* 77204 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27942 | /* 77208 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3956:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 27943 | /* 77208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs8), |
| 27944 | /* 77211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27945 | /* 77213 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 27946 | /* 77215 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 27947 | /* 77217 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 27948 | /* 77219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27949 | /* 77222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27950 | /* 77228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27951 | /* 77234 */ GIR_RootConstrainSelectedInstOperands, |
| 27952 | /* 77235 */ // GIR_Coverage, 5372, |
| 27953 | /* 77235 */ GIR_EraseRootFromParent_Done, |
| 27954 | /* 77236 */ // Label 2389: @77236 |
| 27955 | /* 77236 */ GIM_Reject, |
| 27956 | /* 77237 */ // Label 2386: @77237 |
| 27957 | /* 77237 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2390*/ GIMT_Encode4(77297), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5374 // |
| 27958 | /* 77244 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 27959 | /* 77247 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 27960 | /* 77250 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27961 | /* 77253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27962 | /* 77257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27963 | /* 77261 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27964 | /* 77265 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27965 | /* 77269 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3956:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 27966 | /* 77269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs16), |
| 27967 | /* 77272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27968 | /* 77274 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 27969 | /* 77276 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 27970 | /* 77278 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 27971 | /* 77280 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27972 | /* 77283 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27973 | /* 77289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27974 | /* 77295 */ GIR_RootConstrainSelectedInstOperands, |
| 27975 | /* 77296 */ // GIR_Coverage, 5374, |
| 27976 | /* 77296 */ GIR_EraseRootFromParent_Done, |
| 27977 | /* 77297 */ // Label 2390: @77297 |
| 27978 | /* 77297 */ GIM_Reject, |
| 27979 | /* 77298 */ // Label 2387: @77298 |
| 27980 | /* 77298 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2391*/ GIMT_Encode4(77358), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5376 // |
| 27981 | /* 77305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 27982 | /* 77308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 27983 | /* 77311 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 27984 | /* 77314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27985 | /* 77318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27986 | /* 77322 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 27987 | /* 77326 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 27988 | /* 77330 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3956:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 27989 | /* 77330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs32), |
| 27990 | /* 77333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 27991 | /* 77335 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 27992 | /* 77337 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 27993 | /* 77339 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 27994 | /* 77341 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27995 | /* 77344 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27996 | /* 77350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 27997 | /* 77356 */ GIR_RootConstrainSelectedInstOperands, |
| 27998 | /* 77357 */ // GIR_Coverage, 5376, |
| 27999 | /* 77357 */ GIR_EraseRootFromParent_Done, |
| 28000 | /* 77358 */ // Label 2391: @77358 |
| 28001 | /* 77358 */ GIM_Reject, |
| 28002 | /* 77359 */ // Label 2388: @77359 |
| 28003 | /* 77359 */ GIM_Reject, |
| 28004 | /* 77360 */ // Label 2384: @77360 |
| 28005 | /* 77360 */ GIM_Try, /*On fail goto*//*Label 2392*/ GIMT_Encode4(77585), |
| 28006 | /* 77365 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash), |
| 28007 | /* 77370 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2396*/ GIMT_Encode4(77584), |
| 28008 | /* 77381 */ /*GILLT_v16s8*//*Label 2393*/ GIMT_Encode4(77401), GIMT_Encode4(0), |
| 28009 | /* 77389 */ /*GILLT_v8s16*//*Label 2394*/ GIMT_Encode4(77462), GIMT_Encode4(0), |
| 28010 | /* 77397 */ /*GILLT_v4s32*//*Label 2395*/ GIMT_Encode4(77523), |
| 28011 | /* 77401 */ // Label 2393: @77401 |
| 28012 | /* 77401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2397*/ GIMT_Encode4(77461), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5378 // |
| 28013 | /* 77408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28014 | /* 77411 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28015 | /* 77414 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28016 | /* 77417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28017 | /* 77421 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28018 | /* 77425 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28019 | /* 77429 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28020 | /* 77433 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3949:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28021 | /* 77433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs8), |
| 28022 | /* 77436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28023 | /* 77438 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28024 | /* 77440 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28025 | /* 77442 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28026 | /* 77444 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28027 | /* 77447 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28028 | /* 77453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28029 | /* 77459 */ GIR_RootConstrainSelectedInstOperands, |
| 28030 | /* 77460 */ // GIR_Coverage, 5378, |
| 28031 | /* 77460 */ GIR_EraseRootFromParent_Done, |
| 28032 | /* 77461 */ // Label 2397: @77461 |
| 28033 | /* 77461 */ GIM_Reject, |
| 28034 | /* 77462 */ // Label 2394: @77462 |
| 28035 | /* 77462 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2398*/ GIMT_Encode4(77522), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5380 // |
| 28036 | /* 77469 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28037 | /* 77472 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28038 | /* 77475 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28039 | /* 77478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28040 | /* 77482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28041 | /* 77486 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28042 | /* 77490 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28043 | /* 77494 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3949:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28044 | /* 77494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs16), |
| 28045 | /* 77497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28046 | /* 77499 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28047 | /* 77501 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28048 | /* 77503 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28049 | /* 77505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28050 | /* 77508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28051 | /* 77514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28052 | /* 77520 */ GIR_RootConstrainSelectedInstOperands, |
| 28053 | /* 77521 */ // GIR_Coverage, 5380, |
| 28054 | /* 77521 */ GIR_EraseRootFromParent_Done, |
| 28055 | /* 77522 */ // Label 2398: @77522 |
| 28056 | /* 77522 */ GIM_Reject, |
| 28057 | /* 77523 */ // Label 2395: @77523 |
| 28058 | /* 77523 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2399*/ GIMT_Encode4(77583), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5382 // |
| 28059 | /* 77530 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28060 | /* 77533 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28061 | /* 77536 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28062 | /* 77539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28063 | /* 77543 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28064 | /* 77547 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28065 | /* 77551 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28066 | /* 77555 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3949:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28067 | /* 77555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs32), |
| 28068 | /* 77558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28069 | /* 77560 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28070 | /* 77562 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28071 | /* 77564 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28072 | /* 77566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28073 | /* 77569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28074 | /* 77575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28075 | /* 77581 */ GIR_RootConstrainSelectedInstOperands, |
| 28076 | /* 77582 */ // GIR_Coverage, 5382, |
| 28077 | /* 77582 */ GIR_EraseRootFromParent_Done, |
| 28078 | /* 77583 */ // Label 2399: @77583 |
| 28079 | /* 77583 */ GIM_Reject, |
| 28080 | /* 77584 */ // Label 2396: @77584 |
| 28081 | /* 77584 */ GIM_Reject, |
| 28082 | /* 77585 */ // Label 2392: @77585 |
| 28083 | /* 77585 */ GIM_Try, /*On fail goto*//*Label 2400*/ GIMT_Encode4(77810), |
| 28084 | /* 77590 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash), |
| 28085 | /* 77595 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2404*/ GIMT_Encode4(77809), |
| 28086 | /* 77606 */ /*GILLT_v16s8*//*Label 2401*/ GIMT_Encode4(77626), GIMT_Encode4(0), |
| 28087 | /* 77614 */ /*GILLT_v8s16*//*Label 2402*/ GIMT_Encode4(77687), GIMT_Encode4(0), |
| 28088 | /* 77622 */ /*GILLT_v4s32*//*Label 2403*/ GIMT_Encode4(77748), |
| 28089 | /* 77626 */ // Label 2401: @77626 |
| 28090 | /* 77626 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2405*/ GIMT_Encode4(77686), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5384 // |
| 28091 | /* 77633 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28092 | /* 77636 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28093 | /* 77639 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28094 | /* 77642 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28095 | /* 77646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28096 | /* 77650 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28097 | /* 77654 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28098 | /* 77658 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3958:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28099 | /* 77658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs8), |
| 28100 | /* 77661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28101 | /* 77663 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28102 | /* 77665 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28103 | /* 77667 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28104 | /* 77669 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28105 | /* 77672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28106 | /* 77678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28107 | /* 77684 */ GIR_RootConstrainSelectedInstOperands, |
| 28108 | /* 77685 */ // GIR_Coverage, 5384, |
| 28109 | /* 77685 */ GIR_EraseRootFromParent_Done, |
| 28110 | /* 77686 */ // Label 2405: @77686 |
| 28111 | /* 77686 */ GIM_Reject, |
| 28112 | /* 77687 */ // Label 2402: @77687 |
| 28113 | /* 77687 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2406*/ GIMT_Encode4(77747), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5386 // |
| 28114 | /* 77694 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28115 | /* 77697 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28116 | /* 77700 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28117 | /* 77703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28118 | /* 77707 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28119 | /* 77711 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28120 | /* 77715 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28121 | /* 77719 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3958:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28122 | /* 77719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs16), |
| 28123 | /* 77722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28124 | /* 77724 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28125 | /* 77726 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28126 | /* 77728 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28127 | /* 77730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28128 | /* 77733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28129 | /* 77739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28130 | /* 77745 */ GIR_RootConstrainSelectedInstOperands, |
| 28131 | /* 77746 */ // GIR_Coverage, 5386, |
| 28132 | /* 77746 */ GIR_EraseRootFromParent_Done, |
| 28133 | /* 77747 */ // Label 2406: @77747 |
| 28134 | /* 77747 */ GIM_Reject, |
| 28135 | /* 77748 */ // Label 2403: @77748 |
| 28136 | /* 77748 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2407*/ GIMT_Encode4(77808), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5388 // |
| 28137 | /* 77755 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28138 | /* 77758 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28139 | /* 77761 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28140 | /* 77764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28141 | /* 77768 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28142 | /* 77772 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28143 | /* 77776 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28144 | /* 77780 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3958:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) |
| 28145 | /* 77780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs32), |
| 28146 | /* 77783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28147 | /* 77785 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1 |
| 28148 | /* 77787 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2 |
| 28149 | /* 77789 */ GIR_RootToRootCopy, /*OpIdx*/4, // s |
| 28150 | /* 77791 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28151 | /* 77794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28152 | /* 77800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28153 | /* 77806 */ GIR_RootConstrainSelectedInstOperands, |
| 28154 | /* 77807 */ // GIR_Coverage, 5388, |
| 28155 | /* 77807 */ GIR_EraseRootFromParent_Done, |
| 28156 | /* 77808 */ // Label 2407: @77808 |
| 28157 | /* 77808 */ GIM_Reject, |
| 28158 | /* 77809 */ // Label 2404: @77809 |
| 28159 | /* 77809 */ GIM_Reject, |
| 28160 | /* 77810 */ // Label 2400: @77810 |
| 28161 | /* 77810 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2408*/ GIMT_Encode4(77923), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3080 // |
| 28162 | /* 77817 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1c), |
| 28163 | /* 77822 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28164 | /* 77825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28165 | /* 77828 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28166 | /* 77831 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 28167 | /* 77834 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28168 | /* 77838 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4019:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1C:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) |
| 28169 | /* 77838 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 28170 | /* 77841 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 28171 | /* 77845 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28172 | /* 77850 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e |
| 28173 | /* 77854 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 28174 | /* 77859 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 28175 | /* 77862 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28176 | /* 77866 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28177 | /* 77871 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 28178 | /* 77873 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 28179 | /* 77876 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28180 | /* 77880 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28181 | /* 77885 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 28182 | /* 77888 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 28183 | /* 77891 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17, |
| 28184 | /* 77894 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 28185 | /* 77899 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 28186 | /* 77904 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 28187 | /* 77909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1C), |
| 28188 | /* 77912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28189 | /* 77914 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd |
| 28190 | /* 77916 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28191 | /* 77919 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk |
| 28192 | /* 77921 */ GIR_RootConstrainSelectedInstOperands, |
| 28193 | /* 77922 */ // GIR_Coverage, 3080, |
| 28194 | /* 77922 */ GIR_EraseRootFromParent_Done, |
| 28195 | /* 77923 */ // Label 2408: @77923 |
| 28196 | /* 77923 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2409*/ GIMT_Encode4(78036), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3081 // |
| 28197 | /* 77930 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1m), |
| 28198 | /* 77935 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28199 | /* 77938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28200 | /* 77941 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28201 | /* 77944 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 28202 | /* 77947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28203 | /* 77951 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4021:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1M:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) |
| 28204 | /* 77951 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 28205 | /* 77954 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 28206 | /* 77958 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28207 | /* 77963 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e |
| 28208 | /* 77967 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 28209 | /* 77972 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 28210 | /* 77975 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28211 | /* 77979 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28212 | /* 77984 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 28213 | /* 77986 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 28214 | /* 77989 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28215 | /* 77993 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28216 | /* 77998 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 28217 | /* 78001 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 28218 | /* 78004 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17, |
| 28219 | /* 78007 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 28220 | /* 78012 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 28221 | /* 78017 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 28222 | /* 78022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1M), |
| 28223 | /* 78025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28224 | /* 78027 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd |
| 28225 | /* 78029 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28226 | /* 78032 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk |
| 28227 | /* 78034 */ GIR_RootConstrainSelectedInstOperands, |
| 28228 | /* 78035 */ // GIR_Coverage, 3081, |
| 28229 | /* 78035 */ GIR_EraseRootFromParent_Done, |
| 28230 | /* 78036 */ // Label 2409: @78036 |
| 28231 | /* 78036 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2410*/ GIMT_Encode4(78149), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3082 // |
| 28232 | /* 78043 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1p), |
| 28233 | /* 78048 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 28234 | /* 78051 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28235 | /* 78054 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28236 | /* 78057 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 28237 | /* 78060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 28238 | /* 78064 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4022:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1P:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk) |
| 28239 | /* 78064 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 28240 | /* 78067 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 28241 | /* 78071 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28242 | /* 78076 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e |
| 28243 | /* 78080 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 28244 | /* 78085 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8, |
| 28245 | /* 78088 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28246 | /* 78092 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28247 | /* 78097 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 28248 | /* 78099 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 28249 | /* 78102 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 28250 | /* 78106 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28251 | /* 78111 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 28252 | /* 78114 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 28253 | /* 78117 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17, |
| 28254 | /* 78120 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 28255 | /* 78125 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID), |
| 28256 | /* 78130 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 28257 | /* 78135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1P), |
| 28258 | /* 78138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 28259 | /* 78140 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd |
| 28260 | /* 78142 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28261 | /* 78145 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk |
| 28262 | /* 78147 */ GIR_RootConstrainSelectedInstOperands, |
| 28263 | /* 78148 */ // GIR_Coverage, 3082, |
| 28264 | /* 78148 */ GIR_EraseRootFromParent_Done, |
| 28265 | /* 78149 */ // Label 2410: @78149 |
| 28266 | /* 78149 */ GIM_Reject, |
| 28267 | /* 78150 */ // Label 2103: @78150 |
| 28268 | /* 78150 */ GIM_Try, /*On fail goto*//*Label 2411*/ GIMT_Encode4(80989), |
| 28269 | /* 78155 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 28270 | /* 78158 */ GIM_Try, /*On fail goto*//*Label 2412*/ GIMT_Encode4(78678), |
| 28271 | /* 78163 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm), |
| 28272 | /* 78168 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2415*/ GIMT_Encode4(78677), |
| 28273 | /* 78179 */ /*GILLT_v8s16*//*Label 2413*/ GIMT_Encode4(78191), GIMT_Encode4(0), |
| 28274 | /* 78187 */ /*GILLT_v4s32*//*Label 2414*/ GIMT_Encode4(78434), |
| 28275 | /* 78191 */ // Label 2413: @78191 |
| 28276 | /* 78191 */ GIM_Try, /*On fail goto*//*Label 2416*/ GIMT_Encode4(78433), |
| 28277 | /* 78196 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28278 | /* 78199 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28279 | /* 78202 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28280 | /* 78205 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28281 | /* 78208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28282 | /* 78212 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28283 | /* 78216 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8, |
| 28284 | /* 78220 */ GIM_Try, /*On fail goto*//*Label 2417*/ GIMT_Encode4(78326), |
| 28285 | /* 78225 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28286 | /* 78229 */ GIM_Try, /*On fail goto*//*Label 2418*/ GIMT_Encode4(78277), // Rule ID 4121 // |
| 28287 | /* 78234 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28288 | /* 78238 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3993:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 28289 | /* 78238 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28290 | /* 78241 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28291 | /* 78245 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28292 | /* 78250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8bh), |
| 28293 | /* 78253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28294 | /* 78255 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28295 | /* 78257 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28296 | /* 78260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28297 | /* 78266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28298 | /* 78272 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28299 | /* 78275 */ GIR_RootConstrainSelectedInstOperands, |
| 28300 | /* 78276 */ // GIR_Coverage, 4121, |
| 28301 | /* 78276 */ GIR_EraseRootFromParent_Done, |
| 28302 | /* 78277 */ // Label 2418: @78277 |
| 28303 | /* 78277 */ GIM_Try, /*On fail goto*//*Label 2419*/ GIMT_Encode4(78325), // Rule ID 4125 // |
| 28304 | /* 78282 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28305 | /* 78286 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3993:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 28306 | /* 78286 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28307 | /* 78289 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28308 | /* 78293 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28309 | /* 78298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8th), |
| 28310 | /* 78301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28311 | /* 78303 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28312 | /* 78305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28313 | /* 78308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28314 | /* 78314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28315 | /* 78320 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28316 | /* 78323 */ GIR_RootConstrainSelectedInstOperands, |
| 28317 | /* 78324 */ // GIR_Coverage, 4125, |
| 28318 | /* 78324 */ GIR_EraseRootFromParent_Done, |
| 28319 | /* 78325 */ // Label 2419: @78325 |
| 28320 | /* 78325 */ GIM_Reject, |
| 28321 | /* 78326 */ // Label 2417: @78326 |
| 28322 | /* 78326 */ GIM_Try, /*On fail goto*//*Label 2420*/ GIMT_Encode4(78432), |
| 28323 | /* 78331 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28324 | /* 78335 */ GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(78383), // Rule ID 4137 // |
| 28325 | /* 78340 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28326 | /* 78344 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3993:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 28327 | /* 78344 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28328 | /* 78347 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28329 | /* 78351 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28330 | /* 78356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8bh), |
| 28331 | /* 78359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28332 | /* 78361 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28333 | /* 78363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28334 | /* 78366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28335 | /* 78372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28336 | /* 78378 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28337 | /* 78381 */ GIR_RootConstrainSelectedInstOperands, |
| 28338 | /* 78382 */ // GIR_Coverage, 4137, |
| 28339 | /* 78382 */ GIR_EraseRootFromParent_Done, |
| 28340 | /* 78383 */ // Label 2421: @78383 |
| 28341 | /* 78383 */ GIM_Try, /*On fail goto*//*Label 2422*/ GIMT_Encode4(78431), // Rule ID 4141 // |
| 28342 | /* 78388 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28343 | /* 78392 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3993:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) |
| 28344 | /* 78392 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28345 | /* 78395 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28346 | /* 78399 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28347 | /* 78404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8th), |
| 28348 | /* 78407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28349 | /* 78409 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28350 | /* 78411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28351 | /* 78414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28352 | /* 78420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28353 | /* 78426 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28354 | /* 78429 */ GIR_RootConstrainSelectedInstOperands, |
| 28355 | /* 78430 */ // GIR_Coverage, 4141, |
| 28356 | /* 78430 */ GIR_EraseRootFromParent_Done, |
| 28357 | /* 78431 */ // Label 2422: @78431 |
| 28358 | /* 78431 */ GIM_Reject, |
| 28359 | /* 78432 */ // Label 2420: @78432 |
| 28360 | /* 78432 */ GIM_Reject, |
| 28361 | /* 78433 */ // Label 2416: @78433 |
| 28362 | /* 78433 */ GIM_Reject, |
| 28363 | /* 78434 */ // Label 2414: @78434 |
| 28364 | /* 78434 */ GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(78676), |
| 28365 | /* 78439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28366 | /* 78442 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28367 | /* 78445 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28368 | /* 78448 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28369 | /* 78451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28370 | /* 78455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28371 | /* 78459 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16, |
| 28372 | /* 78463 */ GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(78569), |
| 28373 | /* 78468 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28374 | /* 78472 */ GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(78520), // Rule ID 4129 // |
| 28375 | /* 78477 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28376 | /* 78481 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3993:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 28377 | /* 78481 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28378 | /* 78484 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28379 | /* 78488 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28380 | /* 78493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16bh), |
| 28381 | /* 78496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28382 | /* 78498 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28383 | /* 78500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28384 | /* 78503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28385 | /* 78509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28386 | /* 78515 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28387 | /* 78518 */ GIR_RootConstrainSelectedInstOperands, |
| 28388 | /* 78519 */ // GIR_Coverage, 4129, |
| 28389 | /* 78519 */ GIR_EraseRootFromParent_Done, |
| 28390 | /* 78520 */ // Label 2425: @78520 |
| 28391 | /* 78520 */ GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(78568), // Rule ID 4133 // |
| 28392 | /* 78525 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28393 | /* 78529 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3993:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 28394 | /* 78529 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28395 | /* 78532 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28396 | /* 78536 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28397 | /* 78541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16th), |
| 28398 | /* 78544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28399 | /* 78546 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28400 | /* 78548 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28401 | /* 78551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28402 | /* 78557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28403 | /* 78563 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28404 | /* 78566 */ GIR_RootConstrainSelectedInstOperands, |
| 28405 | /* 78567 */ // GIR_Coverage, 4133, |
| 28406 | /* 78567 */ GIR_EraseRootFromParent_Done, |
| 28407 | /* 78568 */ // Label 2426: @78568 |
| 28408 | /* 78568 */ GIM_Reject, |
| 28409 | /* 78569 */ // Label 2424: @78569 |
| 28410 | /* 78569 */ GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(78675), |
| 28411 | /* 78574 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28412 | /* 78578 */ GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(78626), // Rule ID 4145 // |
| 28413 | /* 78583 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28414 | /* 78587 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3993:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 28415 | /* 78587 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28416 | /* 78590 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28417 | /* 78594 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28418 | /* 78599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16bh), |
| 28419 | /* 78602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28420 | /* 78604 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28421 | /* 78606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28422 | /* 78609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28423 | /* 78615 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28424 | /* 78621 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28425 | /* 78624 */ GIR_RootConstrainSelectedInstOperands, |
| 28426 | /* 78625 */ // GIR_Coverage, 4145, |
| 28427 | /* 78625 */ GIR_EraseRootFromParent_Done, |
| 28428 | /* 78626 */ // Label 2428: @78626 |
| 28429 | /* 78626 */ GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(78674), // Rule ID 4149 // |
| 28430 | /* 78631 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28431 | /* 78635 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3993:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) |
| 28432 | /* 78635 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28433 | /* 78638 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28434 | /* 78642 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28435 | /* 78647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16th), |
| 28436 | /* 78650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28437 | /* 78652 */ GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 28438 | /* 78654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28439 | /* 78657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28440 | /* 78663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28441 | /* 78669 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28442 | /* 78672 */ GIR_RootConstrainSelectedInstOperands, |
| 28443 | /* 78673 */ // GIR_Coverage, 4149, |
| 28444 | /* 78673 */ GIR_EraseRootFromParent_Done, |
| 28445 | /* 78674 */ // Label 2429: @78674 |
| 28446 | /* 78674 */ GIM_Reject, |
| 28447 | /* 78675 */ // Label 2427: @78675 |
| 28448 | /* 78675 */ GIM_Reject, |
| 28449 | /* 78676 */ // Label 2423: @78676 |
| 28450 | /* 78676 */ GIM_Reject, |
| 28451 | /* 78677 */ // Label 2415: @78677 |
| 28452 | /* 78677 */ GIM_Reject, |
| 28453 | /* 78678 */ // Label 2412: @78678 |
| 28454 | /* 78678 */ GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(79493), |
| 28455 | /* 78683 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull), |
| 28456 | /* 78688 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 2434*/ GIMT_Encode4(79492), |
| 28457 | /* 78699 */ /*GILLT_v8s16*//*Label 2431*/ GIMT_Encode4(78715), GIMT_Encode4(0), |
| 28458 | /* 78707 */ /*GILLT_v4s32*//*Label 2432*/ GIMT_Encode4(78974), |
| 28459 | /* 78711 */ /*GILLT_v2s64*//*Label 2433*/ GIMT_Encode4(79233), |
| 28460 | /* 78715 */ // Label 2431: @78715 |
| 28461 | /* 78715 */ GIM_Try, /*On fail goto*//*Label 2435*/ GIMT_Encode4(78973), |
| 28462 | /* 78720 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 28463 | /* 78723 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 28464 | /* 78726 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28465 | /* 78729 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28466 | /* 78732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28467 | /* 78736 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28468 | /* 78740 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28469 | /* 78744 */ GIM_Try, /*On fail goto*//*Label 2436*/ GIMT_Encode4(78858), |
| 28470 | /* 78749 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28471 | /* 78753 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2437*/ GIMT_Encode4(78805), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4889 // |
| 28472 | /* 78760 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28473 | /* 78764 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3943:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 28474 | /* 78764 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28475 | /* 78767 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28476 | /* 78771 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28477 | /* 78776 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8), |
| 28478 | /* 78779 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28479 | /* 78781 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28480 | /* 78783 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28481 | /* 78785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28482 | /* 78788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28483 | /* 78794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28484 | /* 78800 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28485 | /* 78803 */ GIR_RootConstrainSelectedInstOperands, |
| 28486 | /* 78804 */ // GIR_Coverage, 4889, |
| 28487 | /* 78804 */ GIR_EraseRootFromParent_Done, |
| 28488 | /* 78805 */ // Label 2437: @78805 |
| 28489 | /* 78805 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2438*/ GIMT_Encode4(78857), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4891 // |
| 28490 | /* 78812 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28491 | /* 78816 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3943:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 28492 | /* 78816 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28493 | /* 78819 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28494 | /* 78823 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28495 | /* 78828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs8), |
| 28496 | /* 78831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28497 | /* 78833 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28498 | /* 78835 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28499 | /* 78837 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28500 | /* 78840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28501 | /* 78846 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28502 | /* 78852 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28503 | /* 78855 */ GIR_RootConstrainSelectedInstOperands, |
| 28504 | /* 78856 */ // GIR_Coverage, 4891, |
| 28505 | /* 78856 */ GIR_EraseRootFromParent_Done, |
| 28506 | /* 78857 */ // Label 2438: @78857 |
| 28507 | /* 78857 */ GIM_Reject, |
| 28508 | /* 78858 */ // Label 2436: @78858 |
| 28509 | /* 78858 */ GIM_Try, /*On fail goto*//*Label 2439*/ GIMT_Encode4(78972), |
| 28510 | /* 78863 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28511 | /* 78867 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2440*/ GIMT_Encode4(78919), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4901 // |
| 28512 | /* 78874 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28513 | /* 78878 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3943:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 28514 | /* 78878 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28515 | /* 78881 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28516 | /* 78885 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28517 | /* 78890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu8), |
| 28518 | /* 78893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28519 | /* 78895 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28520 | /* 78897 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28521 | /* 78899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28522 | /* 78902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28523 | /* 78908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28524 | /* 78914 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28525 | /* 78917 */ GIR_RootConstrainSelectedInstOperands, |
| 28526 | /* 78918 */ // GIR_Coverage, 4901, |
| 28527 | /* 78918 */ GIR_EraseRootFromParent_Done, |
| 28528 | /* 78919 */ // Label 2440: @78919 |
| 28529 | /* 78919 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2441*/ GIMT_Encode4(78971), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4903 // |
| 28530 | /* 78926 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28531 | /* 78930 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3943:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 28532 | /* 78930 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28533 | /* 78933 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28534 | /* 78937 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28535 | /* 78942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu8), |
| 28536 | /* 78945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28537 | /* 78947 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28538 | /* 78949 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28539 | /* 78951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28540 | /* 78954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28541 | /* 78960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28542 | /* 78966 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28543 | /* 78969 */ GIR_RootConstrainSelectedInstOperands, |
| 28544 | /* 78970 */ // GIR_Coverage, 4903, |
| 28545 | /* 78970 */ GIR_EraseRootFromParent_Done, |
| 28546 | /* 78971 */ // Label 2441: @78971 |
| 28547 | /* 78971 */ GIM_Reject, |
| 28548 | /* 78972 */ // Label 2439: @78972 |
| 28549 | /* 78972 */ GIM_Reject, |
| 28550 | /* 78973 */ // Label 2435: @78973 |
| 28551 | /* 78973 */ GIM_Reject, |
| 28552 | /* 78974 */ // Label 2432: @78974 |
| 28553 | /* 78974 */ GIM_Try, /*On fail goto*//*Label 2442*/ GIMT_Encode4(79232), |
| 28554 | /* 78979 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 28555 | /* 78982 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 28556 | /* 78985 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28557 | /* 78988 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28558 | /* 78991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28559 | /* 78995 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28560 | /* 78999 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28561 | /* 79003 */ GIM_Try, /*On fail goto*//*Label 2443*/ GIMT_Encode4(79117), |
| 28562 | /* 79008 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28563 | /* 79012 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2444*/ GIMT_Encode4(79064), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4893 // |
| 28564 | /* 79019 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28565 | /* 79023 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3943:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 28566 | /* 79023 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28567 | /* 79026 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28568 | /* 79030 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28569 | /* 79035 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16), |
| 28570 | /* 79038 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28571 | /* 79040 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28572 | /* 79042 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28573 | /* 79044 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28574 | /* 79047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28575 | /* 79053 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28576 | /* 79059 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28577 | /* 79062 */ GIR_RootConstrainSelectedInstOperands, |
| 28578 | /* 79063 */ // GIR_Coverage, 4893, |
| 28579 | /* 79063 */ GIR_EraseRootFromParent_Done, |
| 28580 | /* 79064 */ // Label 2444: @79064 |
| 28581 | /* 79064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2445*/ GIMT_Encode4(79116), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4895 // |
| 28582 | /* 79071 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28583 | /* 79075 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3943:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 28584 | /* 79075 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28585 | /* 79078 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28586 | /* 79082 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28587 | /* 79087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs16), |
| 28588 | /* 79090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28589 | /* 79092 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28590 | /* 79094 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28591 | /* 79096 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28592 | /* 79099 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28593 | /* 79105 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28594 | /* 79111 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28595 | /* 79114 */ GIR_RootConstrainSelectedInstOperands, |
| 28596 | /* 79115 */ // GIR_Coverage, 4895, |
| 28597 | /* 79115 */ GIR_EraseRootFromParent_Done, |
| 28598 | /* 79116 */ // Label 2445: @79116 |
| 28599 | /* 79116 */ GIM_Reject, |
| 28600 | /* 79117 */ // Label 2443: @79117 |
| 28601 | /* 79117 */ GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(79231), |
| 28602 | /* 79122 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28603 | /* 79126 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2447*/ GIMT_Encode4(79178), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4905 // |
| 28604 | /* 79133 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28605 | /* 79137 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3943:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 28606 | /* 79137 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28607 | /* 79140 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28608 | /* 79144 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28609 | /* 79149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu16), |
| 28610 | /* 79152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28611 | /* 79154 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28612 | /* 79156 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28613 | /* 79158 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28614 | /* 79161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28615 | /* 79167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28616 | /* 79173 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28617 | /* 79176 */ GIR_RootConstrainSelectedInstOperands, |
| 28618 | /* 79177 */ // GIR_Coverage, 4905, |
| 28619 | /* 79177 */ GIR_EraseRootFromParent_Done, |
| 28620 | /* 79178 */ // Label 2447: @79178 |
| 28621 | /* 79178 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2448*/ GIMT_Encode4(79230), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4907 // |
| 28622 | /* 79185 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28623 | /* 79189 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3943:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 28624 | /* 79189 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28625 | /* 79192 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28626 | /* 79196 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28627 | /* 79201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu16), |
| 28628 | /* 79204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28629 | /* 79206 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28630 | /* 79208 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28631 | /* 79210 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28632 | /* 79213 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28633 | /* 79219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28634 | /* 79225 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28635 | /* 79228 */ GIR_RootConstrainSelectedInstOperands, |
| 28636 | /* 79229 */ // GIR_Coverage, 4907, |
| 28637 | /* 79229 */ GIR_EraseRootFromParent_Done, |
| 28638 | /* 79230 */ // Label 2448: @79230 |
| 28639 | /* 79230 */ GIM_Reject, |
| 28640 | /* 79231 */ // Label 2446: @79231 |
| 28641 | /* 79231 */ GIM_Reject, |
| 28642 | /* 79232 */ // Label 2442: @79232 |
| 28643 | /* 79232 */ GIM_Reject, |
| 28644 | /* 79233 */ // Label 2433: @79233 |
| 28645 | /* 79233 */ GIM_Try, /*On fail goto*//*Label 2449*/ GIMT_Encode4(79491), |
| 28646 | /* 79238 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 28647 | /* 79241 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 28648 | /* 79244 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 28649 | /* 79247 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 28650 | /* 79250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28651 | /* 79254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28652 | /* 79258 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28653 | /* 79262 */ GIM_Try, /*On fail goto*//*Label 2450*/ GIMT_Encode4(79376), |
| 28654 | /* 79267 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 28655 | /* 79271 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2451*/ GIMT_Encode4(79323), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4897 // |
| 28656 | /* 79278 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28657 | /* 79282 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3943:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 28658 | /* 79282 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28659 | /* 79285 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28660 | /* 79289 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28661 | /* 79294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs32), |
| 28662 | /* 79297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28663 | /* 79299 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28664 | /* 79301 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28665 | /* 79303 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28666 | /* 79306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28667 | /* 79312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28668 | /* 79318 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28669 | /* 79321 */ GIR_RootConstrainSelectedInstOperands, |
| 28670 | /* 79322 */ // GIR_Coverage, 4897, |
| 28671 | /* 79322 */ GIR_EraseRootFromParent_Done, |
| 28672 | /* 79323 */ // Label 2451: @79323 |
| 28673 | /* 79323 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2452*/ GIMT_Encode4(79375), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4899 // |
| 28674 | /* 79330 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28675 | /* 79334 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3943:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 28676 | /* 79334 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28677 | /* 79337 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28678 | /* 79341 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28679 | /* 79346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs32), |
| 28680 | /* 79349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28681 | /* 79351 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28682 | /* 79353 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28683 | /* 79355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28684 | /* 79358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28685 | /* 79364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28686 | /* 79370 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28687 | /* 79373 */ GIR_RootConstrainSelectedInstOperands, |
| 28688 | /* 79374 */ // GIR_Coverage, 4899, |
| 28689 | /* 79374 */ GIR_EraseRootFromParent_Done, |
| 28690 | /* 79375 */ // Label 2452: @79375 |
| 28691 | /* 79375 */ GIM_Reject, |
| 28692 | /* 79376 */ // Label 2450: @79376 |
| 28693 | /* 79376 */ GIM_Try, /*On fail goto*//*Label 2453*/ GIMT_Encode4(79490), |
| 28694 | /* 79381 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 28695 | /* 79385 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2454*/ GIMT_Encode4(79437), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4909 // |
| 28696 | /* 79392 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 28697 | /* 79396 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3943:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 28698 | /* 79396 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28699 | /* 79399 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28700 | /* 79403 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28701 | /* 79408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu32), |
| 28702 | /* 79411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28703 | /* 79413 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28704 | /* 79415 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28705 | /* 79417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28706 | /* 79420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28707 | /* 79426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28708 | /* 79432 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28709 | /* 79435 */ GIR_RootConstrainSelectedInstOperands, |
| 28710 | /* 79436 */ // GIR_Coverage, 4909, |
| 28711 | /* 79436 */ GIR_EraseRootFromParent_Done, |
| 28712 | /* 79437 */ // Label 2454: @79437 |
| 28713 | /* 79437 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2455*/ GIMT_Encode4(79489), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4911 // |
| 28714 | /* 79444 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 28715 | /* 79448 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3943:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 28716 | /* 79448 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28717 | /* 79451 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28718 | /* 79455 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28719 | /* 79460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu32), |
| 28720 | /* 79463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28721 | /* 79465 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm |
| 28722 | /* 79467 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn |
| 28723 | /* 79469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28724 | /* 79472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28725 | /* 79478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28726 | /* 79484 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28727 | /* 79487 */ GIR_RootConstrainSelectedInstOperands, |
| 28728 | /* 79488 */ // GIR_Coverage, 4911, |
| 28729 | /* 79488 */ GIR_EraseRootFromParent_Done, |
| 28730 | /* 79489 */ // Label 2455: @79489 |
| 28731 | /* 79489 */ GIM_Reject, |
| 28732 | /* 79490 */ // Label 2453: @79490 |
| 28733 | /* 79490 */ GIM_Reject, |
| 28734 | /* 79491 */ // Label 2449: @79491 |
| 28735 | /* 79491 */ GIM_Reject, |
| 28736 | /* 79492 */ // Label 2434: @79492 |
| 28737 | /* 79492 */ GIM_Reject, |
| 28738 | /* 79493 */ // Label 2430: @79493 |
| 28739 | /* 79493 */ GIM_Try, /*On fail goto*//*Label 2456*/ GIMT_Encode4(80176), |
| 28740 | /* 79498 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq), |
| 28741 | /* 79503 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2460*/ GIMT_Encode4(80175), |
| 28742 | /* 79514 */ /*GILLT_v16s8*//*Label 2457*/ GIMT_Encode4(79534), GIMT_Encode4(0), |
| 28743 | /* 79522 */ /*GILLT_v8s16*//*Label 2458*/ GIMT_Encode4(79703), GIMT_Encode4(0), |
| 28744 | /* 79530 */ /*GILLT_v4s32*//*Label 2459*/ GIMT_Encode4(79939), |
| 28745 | /* 79534 */ // Label 2457: @79534 |
| 28746 | /* 79534 */ GIM_Try, /*On fail goto*//*Label 2461*/ GIMT_Encode4(79702), |
| 28747 | /* 79539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28748 | /* 79542 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28749 | /* 79545 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 28750 | /* 79548 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 28751 | /* 79551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28752 | /* 79555 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2462*/ GIMT_Encode4(79628), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5043 // |
| 28753 | /* 79562 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 28754 | /* 79566 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28755 | /* 79570 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28756 | /* 79574 */ // MIs[1] Operand 1 |
| 28757 | /* 79574 */ // No operand predicates |
| 28758 | /* 79574 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28759 | /* 79578 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28760 | /* 79582 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28761 | /* 79584 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3881:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VCADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28762 | /* 79584 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28763 | /* 79587 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28764 | /* 79591 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28765 | /* 79596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi8), |
| 28766 | /* 79599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28767 | /* 79601 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 28768 | /* 79603 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 28769 | /* 79605 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 28770 | /* 79608 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28771 | /* 79611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28772 | /* 79617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28773 | /* 79623 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28774 | /* 79626 */ GIR_RootConstrainSelectedInstOperands, |
| 28775 | /* 79627 */ // GIR_Coverage, 5043, |
| 28776 | /* 79627 */ GIR_EraseRootFromParent_Done, |
| 28777 | /* 79628 */ // Label 2462: @79628 |
| 28778 | /* 79628 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2463*/ GIMT_Encode4(79701), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5049 // |
| 28779 | /* 79635 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 28780 | /* 79639 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28781 | /* 79643 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28782 | /* 79647 */ // MIs[1] Operand 1 |
| 28783 | /* 79647 */ // No operand predicates |
| 28784 | /* 79647 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28785 | /* 79651 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28786 | /* 79655 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28787 | /* 79657 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3881:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VHCADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28788 | /* 79657 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28789 | /* 79660 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28790 | /* 79664 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28791 | /* 79669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs8), |
| 28792 | /* 79672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28793 | /* 79674 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 28794 | /* 79676 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 28795 | /* 79678 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 28796 | /* 79681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28797 | /* 79684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28798 | /* 79690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28799 | /* 79696 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28800 | /* 79699 */ GIR_RootConstrainSelectedInstOperands, |
| 28801 | /* 79700 */ // GIR_Coverage, 5049, |
| 28802 | /* 79700 */ GIR_EraseRootFromParent_Done, |
| 28803 | /* 79701 */ // Label 2463: @79701 |
| 28804 | /* 79701 */ GIM_Reject, |
| 28805 | /* 79702 */ // Label 2461: @79702 |
| 28806 | /* 79702 */ GIM_Reject, |
| 28807 | /* 79703 */ // Label 2458: @79703 |
| 28808 | /* 79703 */ GIM_Try, /*On fail goto*//*Label 2464*/ GIMT_Encode4(79938), |
| 28809 | /* 79708 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28810 | /* 79711 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28811 | /* 79714 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 28812 | /* 79717 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 28813 | /* 79720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28814 | /* 79724 */ GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(79864), |
| 28815 | /* 79729 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 28816 | /* 79733 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28817 | /* 79737 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28818 | /* 79741 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2466*/ GIMT_Encode4(79802), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4474 // |
| 28819 | /* 79748 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28820 | /* 79752 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28821 | /* 79756 */ // MIs[1] Operand 1 |
| 28822 | /* 79756 */ // No operand predicates |
| 28823 | /* 79756 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28824 | /* 79758 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3881:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28825 | /* 79758 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28826 | /* 79761 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28827 | /* 79765 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28828 | /* 79770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf16), |
| 28829 | /* 79773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28830 | /* 79775 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 28831 | /* 79777 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 28832 | /* 79779 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 28833 | /* 79782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28834 | /* 79785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28835 | /* 79791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28836 | /* 79797 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28837 | /* 79800 */ GIR_RootConstrainSelectedInstOperands, |
| 28838 | /* 79801 */ // GIR_Coverage, 4474, |
| 28839 | /* 79801 */ GIR_EraseRootFromParent_Done, |
| 28840 | /* 79802 */ // Label 2466: @79802 |
| 28841 | /* 79802 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2467*/ GIMT_Encode4(79863), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5045 // |
| 28842 | /* 79809 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28843 | /* 79813 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28844 | /* 79817 */ // MIs[1] Operand 1 |
| 28845 | /* 79817 */ // No operand predicates |
| 28846 | /* 79817 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28847 | /* 79819 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3881:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VCADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28848 | /* 79819 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28849 | /* 79822 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28850 | /* 79826 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28851 | /* 79831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi16), |
| 28852 | /* 79834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28853 | /* 79836 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 28854 | /* 79838 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 28855 | /* 79840 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 28856 | /* 79843 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28857 | /* 79846 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28858 | /* 79852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28859 | /* 79858 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28860 | /* 79861 */ GIR_RootConstrainSelectedInstOperands, |
| 28861 | /* 79862 */ // GIR_Coverage, 5045, |
| 28862 | /* 79862 */ GIR_EraseRootFromParent_Done, |
| 28863 | /* 79863 */ // Label 2467: @79863 |
| 28864 | /* 79863 */ GIM_Reject, |
| 28865 | /* 79864 */ // Label 2465: @79864 |
| 28866 | /* 79864 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2468*/ GIMT_Encode4(79937), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5051 // |
| 28867 | /* 79871 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 28868 | /* 79875 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28869 | /* 79879 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28870 | /* 79883 */ // MIs[1] Operand 1 |
| 28871 | /* 79883 */ // No operand predicates |
| 28872 | /* 79883 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28873 | /* 79887 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28874 | /* 79891 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28875 | /* 79893 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3881:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VHCADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28876 | /* 79893 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28877 | /* 79896 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28878 | /* 79900 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28879 | /* 79905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs16), |
| 28880 | /* 79908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28881 | /* 79910 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 28882 | /* 79912 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 28883 | /* 79914 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 28884 | /* 79917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28885 | /* 79920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28886 | /* 79926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28887 | /* 79932 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28888 | /* 79935 */ GIR_RootConstrainSelectedInstOperands, |
| 28889 | /* 79936 */ // GIR_Coverage, 5051, |
| 28890 | /* 79936 */ GIR_EraseRootFromParent_Done, |
| 28891 | /* 79937 */ // Label 2468: @79937 |
| 28892 | /* 79937 */ GIM_Reject, |
| 28893 | /* 79938 */ // Label 2464: @79938 |
| 28894 | /* 79938 */ GIM_Reject, |
| 28895 | /* 79939 */ // Label 2459: @79939 |
| 28896 | /* 79939 */ GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(80174), |
| 28897 | /* 79944 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28898 | /* 79947 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28899 | /* 79950 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 28900 | /* 79953 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 28901 | /* 79956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28902 | /* 79960 */ GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(80100), |
| 28903 | /* 79965 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 28904 | /* 79969 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28905 | /* 79973 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28906 | /* 79977 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2471*/ GIMT_Encode4(80038), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4476 // |
| 28907 | /* 79984 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28908 | /* 79988 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28909 | /* 79992 */ // MIs[1] Operand 1 |
| 28910 | /* 79992 */ // No operand predicates |
| 28911 | /* 79992 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28912 | /* 79994 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3881:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28913 | /* 79994 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28914 | /* 79997 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28915 | /* 80001 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28916 | /* 80006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf32), |
| 28917 | /* 80009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28918 | /* 80011 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 28919 | /* 80013 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 28920 | /* 80015 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 28921 | /* 80018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28922 | /* 80021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28923 | /* 80027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28924 | /* 80033 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28925 | /* 80036 */ GIR_RootConstrainSelectedInstOperands, |
| 28926 | /* 80037 */ // GIR_Coverage, 4476, |
| 28927 | /* 80037 */ GIR_EraseRootFromParent_Done, |
| 28928 | /* 80038 */ // Label 2471: @80038 |
| 28929 | /* 80038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2472*/ GIMT_Encode4(80099), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5047 // |
| 28930 | /* 80045 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28931 | /* 80049 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28932 | /* 80053 */ // MIs[1] Operand 1 |
| 28933 | /* 80053 */ // No operand predicates |
| 28934 | /* 80053 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28935 | /* 80055 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3881:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VCADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28936 | /* 80055 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28937 | /* 80058 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28938 | /* 80062 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28939 | /* 80067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi32), |
| 28940 | /* 80070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28941 | /* 80072 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 28942 | /* 80074 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 28943 | /* 80076 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 28944 | /* 80079 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28945 | /* 80082 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28946 | /* 80088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28947 | /* 80094 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28948 | /* 80097 */ GIR_RootConstrainSelectedInstOperands, |
| 28949 | /* 80098 */ // GIR_Coverage, 5047, |
| 28950 | /* 80098 */ GIR_EraseRootFromParent_Done, |
| 28951 | /* 80099 */ // Label 2472: @80099 |
| 28952 | /* 80099 */ GIM_Reject, |
| 28953 | /* 80100 */ // Label 2470: @80100 |
| 28954 | /* 80100 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2473*/ GIMT_Encode4(80173), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5053 // |
| 28955 | /* 80107 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 28956 | /* 80111 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 28957 | /* 80115 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 28958 | /* 80119 */ // MIs[1] Operand 1 |
| 28959 | /* 80119 */ // No operand predicates |
| 28960 | /* 80119 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28961 | /* 80123 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 28962 | /* 80127 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 28963 | /* 80129 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3881:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VHCADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 28964 | /* 80129 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 28965 | /* 80132 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 28966 | /* 80136 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 28967 | /* 80141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs32), |
| 28968 | /* 80144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 28969 | /* 80146 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 28970 | /* 80148 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 28971 | /* 80150 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 28972 | /* 80153 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28973 | /* 80156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28974 | /* 80162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 28975 | /* 80168 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 28976 | /* 80171 */ GIR_RootConstrainSelectedInstOperands, |
| 28977 | /* 80172 */ // GIR_Coverage, 5053, |
| 28978 | /* 80172 */ GIR_EraseRootFromParent_Done, |
| 28979 | /* 80173 */ // Label 2473: @80173 |
| 28980 | /* 80173 */ GIM_Reject, |
| 28981 | /* 80174 */ // Label 2469: @80174 |
| 28982 | /* 80174 */ GIM_Reject, |
| 28983 | /* 80175 */ // Label 2460: @80175 |
| 28984 | /* 80175 */ GIM_Reject, |
| 28985 | /* 80176 */ // Label 2456: @80176 |
| 28986 | /* 80176 */ GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(80575), |
| 28987 | /* 80181 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav), |
| 28988 | /* 80186 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 28989 | /* 80189 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 28990 | /* 80192 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 28991 | /* 80195 */ GIM_SwitchType, /*MI*/0, /*Op*/4, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2478*/ GIMT_Encode4(80574), |
| 28992 | /* 80206 */ /*GILLT_v16s8*//*Label 2475*/ GIMT_Encode4(80226), GIMT_Encode4(0), |
| 28993 | /* 80214 */ /*GILLT_v8s16*//*Label 2476*/ GIMT_Encode4(80342), GIMT_Encode4(0), |
| 28994 | /* 80222 */ /*GILLT_v4s32*//*Label 2477*/ GIMT_Encode4(80458), |
| 28995 | /* 80226 */ // Label 2475: @80226 |
| 28996 | /* 80226 */ GIM_Try, /*On fail goto*//*Label 2479*/ GIMT_Encode4(80341), |
| 28997 | /* 80231 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8, |
| 28998 | /* 80234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 28999 | /* 80238 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2480*/ GIMT_Encode4(80289), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3425 // |
| 29000 | /* 80245 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29001 | /* 80249 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29002 | /* 80253 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29003 | /* 80257 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29004 | /* 80261 */ // (intrinsic_wo_chain:{ *:[i32] } 3873:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29005 | /* 80261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs8), |
| 29006 | /* 80264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 29007 | /* 80266 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 29008 | /* 80268 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29009 | /* 80270 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29010 | /* 80272 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29011 | /* 80275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29012 | /* 80281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29013 | /* 80287 */ GIR_RootConstrainSelectedInstOperands, |
| 29014 | /* 80288 */ // GIR_Coverage, 3425, |
| 29015 | /* 80288 */ GIR_EraseRootFromParent_Done, |
| 29016 | /* 80289 */ // Label 2480: @80289 |
| 29017 | /* 80289 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2481*/ GIMT_Encode4(80340), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3431 // |
| 29018 | /* 80296 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29019 | /* 80300 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29020 | /* 80304 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29021 | /* 80308 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29022 | /* 80312 */ // (intrinsic_wo_chain:{ *:[i32] } 3873:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVu8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 29023 | /* 80312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu8), |
| 29024 | /* 80315 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 29025 | /* 80317 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 29026 | /* 80319 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29027 | /* 80321 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29028 | /* 80323 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29029 | /* 80326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29030 | /* 80332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29031 | /* 80338 */ GIR_RootConstrainSelectedInstOperands, |
| 29032 | /* 80339 */ // GIR_Coverage, 3431, |
| 29033 | /* 80339 */ GIR_EraseRootFromParent_Done, |
| 29034 | /* 80340 */ // Label 2481: @80340 |
| 29035 | /* 80340 */ GIM_Reject, |
| 29036 | /* 80341 */ // Label 2479: @80341 |
| 29037 | /* 80341 */ GIM_Reject, |
| 29038 | /* 80342 */ // Label 2476: @80342 |
| 29039 | /* 80342 */ GIM_Try, /*On fail goto*//*Label 2482*/ GIMT_Encode4(80457), |
| 29040 | /* 80347 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 29041 | /* 80350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29042 | /* 80354 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2483*/ GIMT_Encode4(80405), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3427 // |
| 29043 | /* 80361 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29044 | /* 80365 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29045 | /* 80369 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29046 | /* 80373 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29047 | /* 80377 */ // (intrinsic_wo_chain:{ *:[i32] } 3873:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29048 | /* 80377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs16), |
| 29049 | /* 80380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 29050 | /* 80382 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 29051 | /* 80384 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29052 | /* 80386 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29053 | /* 80388 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29054 | /* 80391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29055 | /* 80397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29056 | /* 80403 */ GIR_RootConstrainSelectedInstOperands, |
| 29057 | /* 80404 */ // GIR_Coverage, 3427, |
| 29058 | /* 80404 */ GIR_EraseRootFromParent_Done, |
| 29059 | /* 80405 */ // Label 2483: @80405 |
| 29060 | /* 80405 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2484*/ GIMT_Encode4(80456), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3433 // |
| 29061 | /* 80412 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29062 | /* 80416 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29063 | /* 80420 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29064 | /* 80424 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29065 | /* 80428 */ // (intrinsic_wo_chain:{ *:[i32] } 3873:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVu16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 29066 | /* 80428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu16), |
| 29067 | /* 80431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 29068 | /* 80433 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 29069 | /* 80435 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29070 | /* 80437 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29071 | /* 80439 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29072 | /* 80442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29073 | /* 80448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29074 | /* 80454 */ GIR_RootConstrainSelectedInstOperands, |
| 29075 | /* 80455 */ // GIR_Coverage, 3433, |
| 29076 | /* 80455 */ GIR_EraseRootFromParent_Done, |
| 29077 | /* 80456 */ // Label 2484: @80456 |
| 29078 | /* 80456 */ GIM_Reject, |
| 29079 | /* 80457 */ // Label 2482: @80457 |
| 29080 | /* 80457 */ GIM_Reject, |
| 29081 | /* 80458 */ // Label 2477: @80458 |
| 29082 | /* 80458 */ GIM_Try, /*On fail goto*//*Label 2485*/ GIMT_Encode4(80573), |
| 29083 | /* 80463 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 29084 | /* 80466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29085 | /* 80470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2486*/ GIMT_Encode4(80521), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3429 // |
| 29086 | /* 80477 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 29087 | /* 80481 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29088 | /* 80485 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29089 | /* 80489 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29090 | /* 80493 */ // (intrinsic_wo_chain:{ *:[i32] } 3873:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29091 | /* 80493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs32), |
| 29092 | /* 80496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 29093 | /* 80498 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 29094 | /* 80500 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29095 | /* 80502 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29096 | /* 80504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29097 | /* 80507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29098 | /* 80513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29099 | /* 80519 */ GIR_RootConstrainSelectedInstOperands, |
| 29100 | /* 80520 */ // GIR_Coverage, 3429, |
| 29101 | /* 80520 */ GIR_EraseRootFromParent_Done, |
| 29102 | /* 80521 */ // Label 2486: @80521 |
| 29103 | /* 80521 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2487*/ GIMT_Encode4(80572), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3435 // |
| 29104 | /* 80528 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 29105 | /* 80532 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 29106 | /* 80536 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29107 | /* 80540 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29108 | /* 80544 */ // (intrinsic_wo_chain:{ *:[i32] } 3873:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVu32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 29109 | /* 80544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu32), |
| 29110 | /* 80547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 29111 | /* 80549 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src |
| 29112 | /* 80551 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29113 | /* 80553 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29114 | /* 80555 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29115 | /* 80558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29116 | /* 80564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29117 | /* 80570 */ GIR_RootConstrainSelectedInstOperands, |
| 29118 | /* 80571 */ // GIR_Coverage, 3435, |
| 29119 | /* 80571 */ GIR_EraseRootFromParent_Done, |
| 29120 | /* 80572 */ // Label 2487: @80572 |
| 29121 | /* 80572 */ GIM_Reject, |
| 29122 | /* 80573 */ // Label 2485: @80573 |
| 29123 | /* 80573 */ GIM_Reject, |
| 29124 | /* 80574 */ // Label 2478: @80574 |
| 29125 | /* 80574 */ GIM_Reject, |
| 29126 | /* 80575 */ // Label 2474: @80575 |
| 29127 | /* 80575 */ GIM_Try, /*On fail goto*//*Label 2488*/ GIMT_Encode4(80763), |
| 29128 | /* 80580 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq), |
| 29129 | /* 80585 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2491*/ GIMT_Encode4(80762), |
| 29130 | /* 80596 */ /*GILLT_v8s16*//*Label 2489*/ GIMT_Encode4(80608), GIMT_Encode4(0), |
| 29131 | /* 80604 */ /*GILLT_v4s32*//*Label 2490*/ GIMT_Encode4(80685), |
| 29132 | /* 80608 */ // Label 2489: @80608 |
| 29133 | /* 80608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2492*/ GIMT_Encode4(80684), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4420 // |
| 29134 | /* 80615 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29135 | /* 80618 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 29136 | /* 80621 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 29137 | /* 80624 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16, |
| 29138 | /* 80627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29139 | /* 80631 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 29140 | /* 80635 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 29141 | /* 80639 */ // MIs[1] Operand 1 |
| 29142 | /* 80639 */ // No operand predicates |
| 29143 | /* 80639 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29144 | /* 80643 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29145 | /* 80647 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29146 | /* 80651 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 29147 | /* 80653 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3884:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 29148 | /* 80653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf16), |
| 29149 | /* 80656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29150 | /* 80658 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src |
| 29151 | /* 80660 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29152 | /* 80662 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29153 | /* 80664 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 29154 | /* 80667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29155 | /* 80670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29156 | /* 80676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29157 | /* 80682 */ GIR_RootConstrainSelectedInstOperands, |
| 29158 | /* 80683 */ // GIR_Coverage, 4420, |
| 29159 | /* 80683 */ GIR_EraseRootFromParent_Done, |
| 29160 | /* 80684 */ // Label 2492: @80684 |
| 29161 | /* 80684 */ GIM_Reject, |
| 29162 | /* 80685 */ // Label 2490: @80685 |
| 29163 | /* 80685 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2493*/ GIMT_Encode4(80761), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4423 // |
| 29164 | /* 80692 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 29165 | /* 80695 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 29166 | /* 80698 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 29167 | /* 80701 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 29168 | /* 80704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29169 | /* 80708 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 29170 | /* 80712 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 29171 | /* 80716 */ // MIs[1] Operand 1 |
| 29172 | /* 80716 */ // No operand predicates |
| 29173 | /* 80716 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29174 | /* 80720 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29175 | /* 80724 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29176 | /* 80728 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 29177 | /* 80730 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3884:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot) |
| 29178 | /* 80730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf32), |
| 29179 | /* 80733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29180 | /* 80735 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src |
| 29181 | /* 80737 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn |
| 29182 | /* 80739 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm |
| 29183 | /* 80741 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot |
| 29184 | /* 80744 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29185 | /* 80747 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29186 | /* 80753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29187 | /* 80759 */ GIR_RootConstrainSelectedInstOperands, |
| 29188 | /* 80760 */ // GIR_Coverage, 4423, |
| 29189 | /* 80760 */ GIR_EraseRootFromParent_Done, |
| 29190 | /* 80761 */ // Label 2493: @80761 |
| 29191 | /* 80761 */ GIM_Reject, |
| 29192 | /* 80762 */ // Label 2491: @80762 |
| 29193 | /* 80762 */ GIM_Reject, |
| 29194 | /* 80763 */ // Label 2488: @80763 |
| 29195 | /* 80763 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2494*/ GIMT_Encode4(80858), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3074 // |
| 29196 | /* 80770 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx2), |
| 29197 | /* 80775 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 29198 | /* 80778 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 29199 | /* 80781 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 29200 | /* 80784 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 29201 | /* 80787 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 29202 | /* 80790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 29203 | /* 80794 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4145:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vm) => (VTBX2:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v16i8] } DPair:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 29204 | /* 80794 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 29205 | /* 80797 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 29206 | /* 80801 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29207 | /* 80806 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 |
| 29208 | /* 80810 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 29209 | /* 80813 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 |
| 29210 | /* 80817 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 29211 | /* 80820 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID), |
| 29212 | /* 80825 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 29213 | /* 80830 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 29214 | /* 80835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX2), |
| 29215 | /* 80838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 29216 | /* 80840 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 29217 | /* 80842 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29218 | /* 80845 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm |
| 29219 | /* 80847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 29220 | /* 80850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29221 | /* 80856 */ GIR_RootConstrainSelectedInstOperands, |
| 29222 | /* 80857 */ // GIR_Coverage, 3074, |
| 29223 | /* 80857 */ GIR_EraseRootFromParent_Done, |
| 29224 | /* 80858 */ // Label 2494: @80858 |
| 29225 | /* 80858 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2495*/ GIMT_Encode4(80988), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3075 // |
| 29226 | /* 80865 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl3), |
| 29227 | /* 80870 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 29228 | /* 80873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 29229 | /* 80876 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 29230 | /* 80879 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 29231 | /* 80882 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 29232 | /* 80885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 29233 | /* 80889 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4142:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBL3Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 29234 | /* 80889 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8, |
| 29235 | /* 80892 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29236 | /* 80896 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29237 | /* 80901 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 29238 | /* 80903 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 29239 | /* 80906 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 29240 | /* 80910 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29241 | /* 80915 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0 |
| 29242 | /* 80919 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 29243 | /* 80922 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1 |
| 29244 | /* 80926 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 29245 | /* 80929 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2 |
| 29246 | /* 80933 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 29247 | /* 80936 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 29248 | /* 80939 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 29249 | /* 80942 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 29250 | /* 80947 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 29251 | /* 80952 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 29252 | /* 80957 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 29253 | /* 80962 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 29254 | /* 80967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL3Pseudo), |
| 29255 | /* 80970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 29256 | /* 80972 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29257 | /* 80975 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm |
| 29258 | /* 80977 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 29259 | /* 80980 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29260 | /* 80986 */ GIR_RootConstrainSelectedInstOperands, |
| 29261 | /* 80987 */ // GIR_Coverage, 3075, |
| 29262 | /* 80987 */ GIR_EraseRootFromParent_Done, |
| 29263 | /* 80988 */ // Label 2495: @80988 |
| 29264 | /* 80988 */ GIM_Reject, |
| 29265 | /* 80989 */ // Label 2411: @80989 |
| 29266 | /* 80989 */ GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(84545), |
| 29267 | /* 80994 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, |
| 29268 | /* 80997 */ GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(82515), |
| 29269 | /* 81002 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector), |
| 29270 | /* 81007 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2501*/ GIMT_Encode4(82514), |
| 29271 | /* 81018 */ /*GILLT_v16s8*//*Label 2498*/ GIMT_Encode4(81038), GIMT_Encode4(0), |
| 29272 | /* 81026 */ /*GILLT_v8s16*//*Label 2499*/ GIMT_Encode4(81530), GIMT_Encode4(0), |
| 29273 | /* 81034 */ /*GILLT_v4s32*//*Label 2500*/ GIMT_Encode4(82022), |
| 29274 | /* 81038 */ // Label 2498: @81038 |
| 29275 | /* 81038 */ GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(81529), |
| 29276 | /* 81043 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29277 | /* 81046 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 29278 | /* 81049 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29279 | /* 81052 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29280 | /* 81055 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29281 | /* 81058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29282 | /* 81062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29283 | /* 81066 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29284 | /* 81070 */ GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(81184), |
| 29285 | /* 81075 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29286 | /* 81079 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29287 | /* 81083 */ GIM_Try, /*On fail goto*//*Label 2504*/ GIMT_Encode4(81133), // Rule ID 4232 // |
| 29288 | /* 81088 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29289 | /* 81092 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3989:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29290 | /* 81092 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29291 | /* 81095 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29292 | /* 81099 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29293 | /* 81104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs8), |
| 29294 | /* 81107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29295 | /* 81109 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29296 | /* 81111 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29297 | /* 81113 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29298 | /* 81116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29299 | /* 81122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29300 | /* 81128 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29301 | /* 81131 */ GIR_RootConstrainSelectedInstOperands, |
| 29302 | /* 81132 */ // GIR_Coverage, 4232, |
| 29303 | /* 81132 */ GIR_EraseRootFromParent_Done, |
| 29304 | /* 81133 */ // Label 2504: @81133 |
| 29305 | /* 81133 */ GIM_Try, /*On fail goto*//*Label 2505*/ GIMT_Encode4(81183), // Rule ID 4238 // |
| 29306 | /* 81138 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29307 | /* 81142 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3989:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29308 | /* 81142 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29309 | /* 81145 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29310 | /* 81149 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29311 | /* 81154 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu8), |
| 29312 | /* 81157 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29313 | /* 81159 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29314 | /* 81161 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29315 | /* 81163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29316 | /* 81166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29317 | /* 81172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29318 | /* 81178 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29319 | /* 81181 */ GIR_RootConstrainSelectedInstOperands, |
| 29320 | /* 81182 */ // GIR_Coverage, 4238, |
| 29321 | /* 81182 */ GIR_EraseRootFromParent_Done, |
| 29322 | /* 81183 */ // Label 2505: @81183 |
| 29323 | /* 81183 */ GIM_Reject, |
| 29324 | /* 81184 */ // Label 2503: @81184 |
| 29325 | /* 81184 */ GIM_Try, /*On fail goto*//*Label 2506*/ GIMT_Encode4(81414), |
| 29326 | /* 81189 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29327 | /* 81193 */ GIM_Try, /*On fail goto*//*Label 2507*/ GIMT_Encode4(81303), |
| 29328 | /* 81198 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29329 | /* 81202 */ GIM_Try, /*On fail goto*//*Label 2508*/ GIMT_Encode4(81252), // Rule ID 4244 // |
| 29330 | /* 81207 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29331 | /* 81211 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3989:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29332 | /* 81211 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29333 | /* 81214 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29334 | /* 81218 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29335 | /* 81223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs8), |
| 29336 | /* 81226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29337 | /* 81228 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29338 | /* 81230 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29339 | /* 81232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29340 | /* 81235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29341 | /* 81241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29342 | /* 81247 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29343 | /* 81250 */ GIR_RootConstrainSelectedInstOperands, |
| 29344 | /* 81251 */ // GIR_Coverage, 4244, |
| 29345 | /* 81251 */ GIR_EraseRootFromParent_Done, |
| 29346 | /* 81252 */ // Label 2508: @81252 |
| 29347 | /* 81252 */ GIM_Try, /*On fail goto*//*Label 2509*/ GIMT_Encode4(81302), // Rule ID 4250 // |
| 29348 | /* 81257 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29349 | /* 81261 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3989:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29350 | /* 81261 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29351 | /* 81264 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29352 | /* 81268 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29353 | /* 81273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu8), |
| 29354 | /* 81276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29355 | /* 81278 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29356 | /* 81280 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29357 | /* 81282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29358 | /* 81285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29359 | /* 81291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29360 | /* 81297 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29361 | /* 81300 */ GIR_RootConstrainSelectedInstOperands, |
| 29362 | /* 81301 */ // GIR_Coverage, 4250, |
| 29363 | /* 81301 */ GIR_EraseRootFromParent_Done, |
| 29364 | /* 81302 */ // Label 2509: @81302 |
| 29365 | /* 81302 */ GIM_Reject, |
| 29366 | /* 81303 */ // Label 2507: @81303 |
| 29367 | /* 81303 */ GIM_Try, /*On fail goto*//*Label 2510*/ GIMT_Encode4(81413), |
| 29368 | /* 81308 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29369 | /* 81312 */ GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(81362), // Rule ID 4256 // |
| 29370 | /* 81317 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29371 | /* 81321 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3989:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29372 | /* 81321 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29373 | /* 81324 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29374 | /* 81328 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29375 | /* 81333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs8), |
| 29376 | /* 81336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29377 | /* 81338 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29378 | /* 81340 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29379 | /* 81342 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29380 | /* 81345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29381 | /* 81351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29382 | /* 81357 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29383 | /* 81360 */ GIR_RootConstrainSelectedInstOperands, |
| 29384 | /* 81361 */ // GIR_Coverage, 4256, |
| 29385 | /* 81361 */ GIR_EraseRootFromParent_Done, |
| 29386 | /* 81362 */ // Label 2511: @81362 |
| 29387 | /* 81362 */ GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(81412), // Rule ID 4262 // |
| 29388 | /* 81367 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29389 | /* 81371 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3989:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29390 | /* 81371 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29391 | /* 81374 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29392 | /* 81378 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29393 | /* 81383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu8), |
| 29394 | /* 81386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29395 | /* 81388 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29396 | /* 81390 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29397 | /* 81392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29398 | /* 81395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29399 | /* 81401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29400 | /* 81407 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29401 | /* 81410 */ GIR_RootConstrainSelectedInstOperands, |
| 29402 | /* 81411 */ // GIR_Coverage, 4262, |
| 29403 | /* 81411 */ GIR_EraseRootFromParent_Done, |
| 29404 | /* 81412 */ // Label 2512: @81412 |
| 29405 | /* 81412 */ GIM_Reject, |
| 29406 | /* 81413 */ // Label 2510: @81413 |
| 29407 | /* 81413 */ GIM_Reject, |
| 29408 | /* 81414 */ // Label 2506: @81414 |
| 29409 | /* 81414 */ GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(81528), |
| 29410 | /* 81419 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29411 | /* 81423 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29412 | /* 81427 */ GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(81477), // Rule ID 4268 // |
| 29413 | /* 81432 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29414 | /* 81436 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3989:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29415 | /* 81436 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29416 | /* 81439 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29417 | /* 81443 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29418 | /* 81448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs8), |
| 29419 | /* 81451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29420 | /* 81453 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29421 | /* 81455 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29422 | /* 81457 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29423 | /* 81460 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29424 | /* 81466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29425 | /* 81472 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29426 | /* 81475 */ GIR_RootConstrainSelectedInstOperands, |
| 29427 | /* 81476 */ // GIR_Coverage, 4268, |
| 29428 | /* 81476 */ GIR_EraseRootFromParent_Done, |
| 29429 | /* 81477 */ // Label 2514: @81477 |
| 29430 | /* 81477 */ GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(81527), // Rule ID 4274 // |
| 29431 | /* 81482 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29432 | /* 81486 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3989:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh) |
| 29433 | /* 81486 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29434 | /* 81489 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29435 | /* 81493 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29436 | /* 81498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu8), |
| 29437 | /* 81501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29438 | /* 81503 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29439 | /* 81505 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29440 | /* 81507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29441 | /* 81510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29442 | /* 81516 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29443 | /* 81522 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29444 | /* 81525 */ GIR_RootConstrainSelectedInstOperands, |
| 29445 | /* 81526 */ // GIR_Coverage, 4274, |
| 29446 | /* 81526 */ GIR_EraseRootFromParent_Done, |
| 29447 | /* 81527 */ // Label 2515: @81527 |
| 29448 | /* 81527 */ GIM_Reject, |
| 29449 | /* 81528 */ // Label 2513: @81528 |
| 29450 | /* 81528 */ GIM_Reject, |
| 29451 | /* 81529 */ // Label 2502: @81529 |
| 29452 | /* 81529 */ GIM_Reject, |
| 29453 | /* 81530 */ // Label 2499: @81530 |
| 29454 | /* 81530 */ GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(82021), |
| 29455 | /* 81535 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29456 | /* 81538 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 29457 | /* 81541 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29458 | /* 81544 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29459 | /* 81547 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29460 | /* 81550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29461 | /* 81554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29462 | /* 81558 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29463 | /* 81562 */ GIM_Try, /*On fail goto*//*Label 2517*/ GIMT_Encode4(81676), |
| 29464 | /* 81567 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29465 | /* 81571 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29466 | /* 81575 */ GIM_Try, /*On fail goto*//*Label 2518*/ GIMT_Encode4(81625), // Rule ID 4234 // |
| 29467 | /* 81580 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29468 | /* 81584 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3989:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29469 | /* 81584 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29470 | /* 81587 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29471 | /* 81591 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29472 | /* 81596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs16), |
| 29473 | /* 81599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29474 | /* 81601 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29475 | /* 81603 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29476 | /* 81605 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29477 | /* 81608 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29478 | /* 81614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29479 | /* 81620 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29480 | /* 81623 */ GIR_RootConstrainSelectedInstOperands, |
| 29481 | /* 81624 */ // GIR_Coverage, 4234, |
| 29482 | /* 81624 */ GIR_EraseRootFromParent_Done, |
| 29483 | /* 81625 */ // Label 2518: @81625 |
| 29484 | /* 81625 */ GIM_Try, /*On fail goto*//*Label 2519*/ GIMT_Encode4(81675), // Rule ID 4240 // |
| 29485 | /* 81630 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29486 | /* 81634 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3989:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29487 | /* 81634 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29488 | /* 81637 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29489 | /* 81641 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29490 | /* 81646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu16), |
| 29491 | /* 81649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29492 | /* 81651 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29493 | /* 81653 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29494 | /* 81655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29495 | /* 81658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29496 | /* 81664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29497 | /* 81670 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29498 | /* 81673 */ GIR_RootConstrainSelectedInstOperands, |
| 29499 | /* 81674 */ // GIR_Coverage, 4240, |
| 29500 | /* 81674 */ GIR_EraseRootFromParent_Done, |
| 29501 | /* 81675 */ // Label 2519: @81675 |
| 29502 | /* 81675 */ GIM_Reject, |
| 29503 | /* 81676 */ // Label 2517: @81676 |
| 29504 | /* 81676 */ GIM_Try, /*On fail goto*//*Label 2520*/ GIMT_Encode4(81906), |
| 29505 | /* 81681 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29506 | /* 81685 */ GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(81795), |
| 29507 | /* 81690 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29508 | /* 81694 */ GIM_Try, /*On fail goto*//*Label 2522*/ GIMT_Encode4(81744), // Rule ID 4246 // |
| 29509 | /* 81699 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29510 | /* 81703 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3989:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29511 | /* 81703 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29512 | /* 81706 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29513 | /* 81710 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29514 | /* 81715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs16), |
| 29515 | /* 81718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29516 | /* 81720 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29517 | /* 81722 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29518 | /* 81724 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29519 | /* 81727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29520 | /* 81733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29521 | /* 81739 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29522 | /* 81742 */ GIR_RootConstrainSelectedInstOperands, |
| 29523 | /* 81743 */ // GIR_Coverage, 4246, |
| 29524 | /* 81743 */ GIR_EraseRootFromParent_Done, |
| 29525 | /* 81744 */ // Label 2522: @81744 |
| 29526 | /* 81744 */ GIM_Try, /*On fail goto*//*Label 2523*/ GIMT_Encode4(81794), // Rule ID 4252 // |
| 29527 | /* 81749 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29528 | /* 81753 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3989:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29529 | /* 81753 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29530 | /* 81756 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29531 | /* 81760 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29532 | /* 81765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu16), |
| 29533 | /* 81768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29534 | /* 81770 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29535 | /* 81772 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29536 | /* 81774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29537 | /* 81777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29538 | /* 81783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29539 | /* 81789 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29540 | /* 81792 */ GIR_RootConstrainSelectedInstOperands, |
| 29541 | /* 81793 */ // GIR_Coverage, 4252, |
| 29542 | /* 81793 */ GIR_EraseRootFromParent_Done, |
| 29543 | /* 81794 */ // Label 2523: @81794 |
| 29544 | /* 81794 */ GIM_Reject, |
| 29545 | /* 81795 */ // Label 2521: @81795 |
| 29546 | /* 81795 */ GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(81905), |
| 29547 | /* 81800 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29548 | /* 81804 */ GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(81854), // Rule ID 4258 // |
| 29549 | /* 81809 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29550 | /* 81813 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3989:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29551 | /* 81813 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29552 | /* 81816 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29553 | /* 81820 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29554 | /* 81825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs16), |
| 29555 | /* 81828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29556 | /* 81830 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29557 | /* 81832 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29558 | /* 81834 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29559 | /* 81837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29560 | /* 81843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29561 | /* 81849 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29562 | /* 81852 */ GIR_RootConstrainSelectedInstOperands, |
| 29563 | /* 81853 */ // GIR_Coverage, 4258, |
| 29564 | /* 81853 */ GIR_EraseRootFromParent_Done, |
| 29565 | /* 81854 */ // Label 2525: @81854 |
| 29566 | /* 81854 */ GIM_Try, /*On fail goto*//*Label 2526*/ GIMT_Encode4(81904), // Rule ID 4264 // |
| 29567 | /* 81859 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29568 | /* 81863 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3989:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29569 | /* 81863 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29570 | /* 81866 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29571 | /* 81870 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29572 | /* 81875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu16), |
| 29573 | /* 81878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29574 | /* 81880 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29575 | /* 81882 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29576 | /* 81884 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29577 | /* 81887 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29578 | /* 81893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29579 | /* 81899 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29580 | /* 81902 */ GIR_RootConstrainSelectedInstOperands, |
| 29581 | /* 81903 */ // GIR_Coverage, 4264, |
| 29582 | /* 81903 */ GIR_EraseRootFromParent_Done, |
| 29583 | /* 81904 */ // Label 2526: @81904 |
| 29584 | /* 81904 */ GIM_Reject, |
| 29585 | /* 81905 */ // Label 2524: @81905 |
| 29586 | /* 81905 */ GIM_Reject, |
| 29587 | /* 81906 */ // Label 2520: @81906 |
| 29588 | /* 81906 */ GIM_Try, /*On fail goto*//*Label 2527*/ GIMT_Encode4(82020), |
| 29589 | /* 81911 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29590 | /* 81915 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29591 | /* 81919 */ GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(81969), // Rule ID 4270 // |
| 29592 | /* 81924 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29593 | /* 81928 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3989:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29594 | /* 81928 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29595 | /* 81931 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29596 | /* 81935 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29597 | /* 81940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs16), |
| 29598 | /* 81943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29599 | /* 81945 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29600 | /* 81947 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29601 | /* 81949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29602 | /* 81952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29603 | /* 81958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29604 | /* 81964 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29605 | /* 81967 */ GIR_RootConstrainSelectedInstOperands, |
| 29606 | /* 81968 */ // GIR_Coverage, 4270, |
| 29607 | /* 81968 */ GIR_EraseRootFromParent_Done, |
| 29608 | /* 81969 */ // Label 2528: @81969 |
| 29609 | /* 81969 */ GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(82019), // Rule ID 4276 // |
| 29610 | /* 81974 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29611 | /* 81978 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3989:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh) |
| 29612 | /* 81978 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29613 | /* 81981 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29614 | /* 81985 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29615 | /* 81990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu16), |
| 29616 | /* 81993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29617 | /* 81995 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29618 | /* 81997 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29619 | /* 81999 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29620 | /* 82002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29621 | /* 82008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29622 | /* 82014 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29623 | /* 82017 */ GIR_RootConstrainSelectedInstOperands, |
| 29624 | /* 82018 */ // GIR_Coverage, 4276, |
| 29625 | /* 82018 */ GIR_EraseRootFromParent_Done, |
| 29626 | /* 82019 */ // Label 2529: @82019 |
| 29627 | /* 82019 */ GIM_Reject, |
| 29628 | /* 82020 */ // Label 2527: @82020 |
| 29629 | /* 82020 */ GIM_Reject, |
| 29630 | /* 82021 */ // Label 2516: @82021 |
| 29631 | /* 82021 */ GIM_Reject, |
| 29632 | /* 82022 */ // Label 2500: @82022 |
| 29633 | /* 82022 */ GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(82513), |
| 29634 | /* 82027 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 29635 | /* 82030 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 29636 | /* 82033 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29637 | /* 82036 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29638 | /* 82039 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29639 | /* 82042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29640 | /* 82046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29641 | /* 82050 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29642 | /* 82054 */ GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(82168), |
| 29643 | /* 82059 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29644 | /* 82063 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29645 | /* 82067 */ GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(82117), // Rule ID 4236 // |
| 29646 | /* 82072 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29647 | /* 82076 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3989:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29648 | /* 82076 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29649 | /* 82079 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29650 | /* 82083 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29651 | /* 82088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs32), |
| 29652 | /* 82091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29653 | /* 82093 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29654 | /* 82095 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29655 | /* 82097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29656 | /* 82100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29657 | /* 82106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29658 | /* 82112 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29659 | /* 82115 */ GIR_RootConstrainSelectedInstOperands, |
| 29660 | /* 82116 */ // GIR_Coverage, 4236, |
| 29661 | /* 82116 */ GIR_EraseRootFromParent_Done, |
| 29662 | /* 82117 */ // Label 2532: @82117 |
| 29663 | /* 82117 */ GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(82167), // Rule ID 4242 // |
| 29664 | /* 82122 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29665 | /* 82126 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3989:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29666 | /* 82126 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29667 | /* 82129 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29668 | /* 82133 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29669 | /* 82138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu32), |
| 29670 | /* 82141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29671 | /* 82143 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29672 | /* 82145 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29673 | /* 82147 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29674 | /* 82150 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29675 | /* 82156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29676 | /* 82162 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29677 | /* 82165 */ GIR_RootConstrainSelectedInstOperands, |
| 29678 | /* 82166 */ // GIR_Coverage, 4242, |
| 29679 | /* 82166 */ GIR_EraseRootFromParent_Done, |
| 29680 | /* 82167 */ // Label 2533: @82167 |
| 29681 | /* 82167 */ GIM_Reject, |
| 29682 | /* 82168 */ // Label 2531: @82168 |
| 29683 | /* 82168 */ GIM_Try, /*On fail goto*//*Label 2534*/ GIMT_Encode4(82398), |
| 29684 | /* 82173 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29685 | /* 82177 */ GIM_Try, /*On fail goto*//*Label 2535*/ GIMT_Encode4(82287), |
| 29686 | /* 82182 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29687 | /* 82186 */ GIM_Try, /*On fail goto*//*Label 2536*/ GIMT_Encode4(82236), // Rule ID 4248 // |
| 29688 | /* 82191 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29689 | /* 82195 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3989:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29690 | /* 82195 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29691 | /* 82198 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29692 | /* 82202 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29693 | /* 82207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs32), |
| 29694 | /* 82210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29695 | /* 82212 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29696 | /* 82214 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29697 | /* 82216 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29698 | /* 82219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29699 | /* 82225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29700 | /* 82231 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29701 | /* 82234 */ GIR_RootConstrainSelectedInstOperands, |
| 29702 | /* 82235 */ // GIR_Coverage, 4248, |
| 29703 | /* 82235 */ GIR_EraseRootFromParent_Done, |
| 29704 | /* 82236 */ // Label 2536: @82236 |
| 29705 | /* 82236 */ GIM_Try, /*On fail goto*//*Label 2537*/ GIMT_Encode4(82286), // Rule ID 4254 // |
| 29706 | /* 82241 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29707 | /* 82245 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3989:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29708 | /* 82245 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29709 | /* 82248 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29710 | /* 82252 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29711 | /* 82257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu32), |
| 29712 | /* 82260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29713 | /* 82262 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29714 | /* 82264 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29715 | /* 82266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29716 | /* 82269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29717 | /* 82275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29718 | /* 82281 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29719 | /* 82284 */ GIR_RootConstrainSelectedInstOperands, |
| 29720 | /* 82285 */ // GIR_Coverage, 4254, |
| 29721 | /* 82285 */ GIR_EraseRootFromParent_Done, |
| 29722 | /* 82286 */ // Label 2537: @82286 |
| 29723 | /* 82286 */ GIM_Reject, |
| 29724 | /* 82287 */ // Label 2535: @82287 |
| 29725 | /* 82287 */ GIM_Try, /*On fail goto*//*Label 2538*/ GIMT_Encode4(82397), |
| 29726 | /* 82292 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29727 | /* 82296 */ GIM_Try, /*On fail goto*//*Label 2539*/ GIMT_Encode4(82346), // Rule ID 4260 // |
| 29728 | /* 82301 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29729 | /* 82305 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3989:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29730 | /* 82305 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29731 | /* 82308 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29732 | /* 82312 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29733 | /* 82317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs32), |
| 29734 | /* 82320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29735 | /* 82322 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29736 | /* 82324 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29737 | /* 82326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29738 | /* 82329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29739 | /* 82335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29740 | /* 82341 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29741 | /* 82344 */ GIR_RootConstrainSelectedInstOperands, |
| 29742 | /* 82345 */ // GIR_Coverage, 4260, |
| 29743 | /* 82345 */ GIR_EraseRootFromParent_Done, |
| 29744 | /* 82346 */ // Label 2539: @82346 |
| 29745 | /* 82346 */ GIM_Try, /*On fail goto*//*Label 2540*/ GIMT_Encode4(82396), // Rule ID 4266 // |
| 29746 | /* 82351 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29747 | /* 82355 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3989:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29748 | /* 82355 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29749 | /* 82358 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29750 | /* 82362 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29751 | /* 82367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu32), |
| 29752 | /* 82370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29753 | /* 82372 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29754 | /* 82374 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29755 | /* 82376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29756 | /* 82379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29757 | /* 82385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29758 | /* 82391 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29759 | /* 82394 */ GIR_RootConstrainSelectedInstOperands, |
| 29760 | /* 82395 */ // GIR_Coverage, 4266, |
| 29761 | /* 82395 */ GIR_EraseRootFromParent_Done, |
| 29762 | /* 82396 */ // Label 2540: @82396 |
| 29763 | /* 82396 */ GIM_Reject, |
| 29764 | /* 82397 */ // Label 2538: @82397 |
| 29765 | /* 82397 */ GIM_Reject, |
| 29766 | /* 82398 */ // Label 2534: @82398 |
| 29767 | /* 82398 */ GIM_Try, /*On fail goto*//*Label 2541*/ GIMT_Encode4(82512), |
| 29768 | /* 82403 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29769 | /* 82407 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29770 | /* 82411 */ GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(82461), // Rule ID 4272 // |
| 29771 | /* 82416 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29772 | /* 82420 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3989:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29773 | /* 82420 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29774 | /* 82423 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29775 | /* 82427 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29776 | /* 82432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs32), |
| 29777 | /* 82435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29778 | /* 82437 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29779 | /* 82439 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29780 | /* 82441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29781 | /* 82444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29782 | /* 82450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29783 | /* 82456 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29784 | /* 82459 */ GIR_RootConstrainSelectedInstOperands, |
| 29785 | /* 82460 */ // GIR_Coverage, 4272, |
| 29786 | /* 82460 */ GIR_EraseRootFromParent_Done, |
| 29787 | /* 82461 */ // Label 2542: @82461 |
| 29788 | /* 82461 */ GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(82511), // Rule ID 4278 // |
| 29789 | /* 82466 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29790 | /* 82470 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3989:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh) |
| 29791 | /* 82470 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 29792 | /* 82473 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 29793 | /* 82477 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 29794 | /* 82482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu32), |
| 29795 | /* 82485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29796 | /* 82487 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 29797 | /* 82489 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 29798 | /* 82491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29799 | /* 82494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29800 | /* 82500 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29801 | /* 82506 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 29802 | /* 82509 */ GIR_RootConstrainSelectedInstOperands, |
| 29803 | /* 82510 */ // GIR_Coverage, 4278, |
| 29804 | /* 82510 */ GIR_EraseRootFromParent_Done, |
| 29805 | /* 82511 */ // Label 2543: @82511 |
| 29806 | /* 82511 */ GIM_Reject, |
| 29807 | /* 82512 */ // Label 2541: @82512 |
| 29808 | /* 82512 */ GIM_Reject, |
| 29809 | /* 82513 */ // Label 2530: @82513 |
| 29810 | /* 82513 */ GIM_Reject, |
| 29811 | /* 82514 */ // Label 2501: @82514 |
| 29812 | /* 82514 */ GIM_Reject, |
| 29813 | /* 82515 */ // Label 2497: @82515 |
| 29814 | /* 82515 */ GIM_Try, /*On fail goto*//*Label 2544*/ GIMT_Encode4(83125), |
| 29815 | /* 82520 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn), |
| 29816 | /* 82525 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 2547*/ GIMT_Encode4(83124), |
| 29817 | /* 82536 */ /*GILLT_v16s8*//*Label 2545*/ GIMT_Encode4(82548), GIMT_Encode4(0), |
| 29818 | /* 82544 */ /*GILLT_v8s16*//*Label 2546*/ GIMT_Encode4(82836), |
| 29819 | /* 82548 */ // Label 2545: @82548 |
| 29820 | /* 82548 */ GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(82835), |
| 29821 | /* 82553 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 29822 | /* 82556 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 29823 | /* 82559 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29824 | /* 82562 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29825 | /* 82565 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29826 | /* 82568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29827 | /* 82572 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29828 | /* 82576 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29829 | /* 82580 */ GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(82664), |
| 29830 | /* 82585 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29831 | /* 82589 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29832 | /* 82593 */ GIM_Try, /*On fail goto*//*Label 2550*/ GIMT_Encode4(82628), // Rule ID 4995 // |
| 29833 | /* 82598 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29834 | /* 82602 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3954:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 29835 | /* 82602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16bh), |
| 29836 | /* 82605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29837 | /* 82607 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29838 | /* 82609 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29839 | /* 82611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29840 | /* 82614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29841 | /* 82620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29842 | /* 82626 */ GIR_RootConstrainSelectedInstOperands, |
| 29843 | /* 82627 */ // GIR_Coverage, 4995, |
| 29844 | /* 82627 */ GIR_EraseRootFromParent_Done, |
| 29845 | /* 82628 */ // Label 2550: @82628 |
| 29846 | /* 82628 */ GIM_Try, /*On fail goto*//*Label 2551*/ GIMT_Encode4(82663), // Rule ID 4997 // |
| 29847 | /* 82633 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29848 | /* 82637 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3954:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 29849 | /* 82637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16th), |
| 29850 | /* 82640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29851 | /* 82642 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29852 | /* 82644 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29853 | /* 82646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29854 | /* 82649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29855 | /* 82655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29856 | /* 82661 */ GIR_RootConstrainSelectedInstOperands, |
| 29857 | /* 82662 */ // GIR_Coverage, 4997, |
| 29858 | /* 82662 */ GIR_EraseRootFromParent_Done, |
| 29859 | /* 82663 */ // Label 2551: @82663 |
| 29860 | /* 82663 */ GIM_Reject, |
| 29861 | /* 82664 */ // Label 2549: @82664 |
| 29862 | /* 82664 */ GIM_Try, /*On fail goto*//*Label 2552*/ GIMT_Encode4(82834), |
| 29863 | /* 82669 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29864 | /* 82673 */ GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(82753), |
| 29865 | /* 82678 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29866 | /* 82682 */ GIM_Try, /*On fail goto*//*Label 2554*/ GIMT_Encode4(82717), // Rule ID 5003 // |
| 29867 | /* 82687 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29868 | /* 82691 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3954:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 29869 | /* 82691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16bh), |
| 29870 | /* 82694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29871 | /* 82696 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29872 | /* 82698 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29873 | /* 82700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29874 | /* 82703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29875 | /* 82709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29876 | /* 82715 */ GIR_RootConstrainSelectedInstOperands, |
| 29877 | /* 82716 */ // GIR_Coverage, 5003, |
| 29878 | /* 82716 */ GIR_EraseRootFromParent_Done, |
| 29879 | /* 82717 */ // Label 2554: @82717 |
| 29880 | /* 82717 */ GIM_Try, /*On fail goto*//*Label 2555*/ GIMT_Encode4(82752), // Rule ID 5005 // |
| 29881 | /* 82722 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29882 | /* 82726 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3954:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 29883 | /* 82726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16th), |
| 29884 | /* 82729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29885 | /* 82731 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29886 | /* 82733 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29887 | /* 82735 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29888 | /* 82738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29889 | /* 82744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29890 | /* 82750 */ GIR_RootConstrainSelectedInstOperands, |
| 29891 | /* 82751 */ // GIR_Coverage, 5005, |
| 29892 | /* 82751 */ GIR_EraseRootFromParent_Done, |
| 29893 | /* 82752 */ // Label 2555: @82752 |
| 29894 | /* 82752 */ GIM_Reject, |
| 29895 | /* 82753 */ // Label 2553: @82753 |
| 29896 | /* 82753 */ GIM_Try, /*On fail goto*//*Label 2556*/ GIMT_Encode4(82833), |
| 29897 | /* 82758 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29898 | /* 82762 */ GIM_Try, /*On fail goto*//*Label 2557*/ GIMT_Encode4(82797), // Rule ID 5011 // |
| 29899 | /* 82767 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29900 | /* 82771 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3954:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 29901 | /* 82771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16bh), |
| 29902 | /* 82774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29903 | /* 82776 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29904 | /* 82778 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29905 | /* 82780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29906 | /* 82783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29907 | /* 82789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29908 | /* 82795 */ GIR_RootConstrainSelectedInstOperands, |
| 29909 | /* 82796 */ // GIR_Coverage, 5011, |
| 29910 | /* 82796 */ GIR_EraseRootFromParent_Done, |
| 29911 | /* 82797 */ // Label 2557: @82797 |
| 29912 | /* 82797 */ GIM_Try, /*On fail goto*//*Label 2558*/ GIMT_Encode4(82832), // Rule ID 5013 // |
| 29913 | /* 82802 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29914 | /* 82806 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3954:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm) |
| 29915 | /* 82806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16th), |
| 29916 | /* 82809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29917 | /* 82811 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29918 | /* 82813 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29919 | /* 82815 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29920 | /* 82818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29921 | /* 82824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29922 | /* 82830 */ GIR_RootConstrainSelectedInstOperands, |
| 29923 | /* 82831 */ // GIR_Coverage, 5013, |
| 29924 | /* 82831 */ GIR_EraseRootFromParent_Done, |
| 29925 | /* 82832 */ // Label 2558: @82832 |
| 29926 | /* 82832 */ GIM_Reject, |
| 29927 | /* 82833 */ // Label 2556: @82833 |
| 29928 | /* 82833 */ GIM_Reject, |
| 29929 | /* 82834 */ // Label 2552: @82834 |
| 29930 | /* 82834 */ GIM_Reject, |
| 29931 | /* 82835 */ // Label 2548: @82835 |
| 29932 | /* 82835 */ GIM_Reject, |
| 29933 | /* 82836 */ // Label 2546: @82836 |
| 29934 | /* 82836 */ GIM_Try, /*On fail goto*//*Label 2559*/ GIMT_Encode4(83123), |
| 29935 | /* 82841 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 29936 | /* 82844 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 29937 | /* 82847 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 29938 | /* 82850 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 29939 | /* 82853 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 29940 | /* 82856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29941 | /* 82860 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29942 | /* 82864 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 29943 | /* 82868 */ GIM_Try, /*On fail goto*//*Label 2560*/ GIMT_Encode4(82952), |
| 29944 | /* 82873 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 29945 | /* 82877 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 29946 | /* 82881 */ GIM_Try, /*On fail goto*//*Label 2561*/ GIMT_Encode4(82916), // Rule ID 4991 // |
| 29947 | /* 82886 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29948 | /* 82890 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3954:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 29949 | /* 82890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32bh), |
| 29950 | /* 82893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29951 | /* 82895 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29952 | /* 82897 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29953 | /* 82899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29954 | /* 82902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29955 | /* 82908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29956 | /* 82914 */ GIR_RootConstrainSelectedInstOperands, |
| 29957 | /* 82915 */ // GIR_Coverage, 4991, |
| 29958 | /* 82915 */ GIR_EraseRootFromParent_Done, |
| 29959 | /* 82916 */ // Label 2561: @82916 |
| 29960 | /* 82916 */ GIM_Try, /*On fail goto*//*Label 2562*/ GIMT_Encode4(82951), // Rule ID 4993 // |
| 29961 | /* 82921 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29962 | /* 82925 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3954:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 29963 | /* 82925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32th), |
| 29964 | /* 82928 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29965 | /* 82930 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29966 | /* 82932 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29967 | /* 82934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29968 | /* 82937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29969 | /* 82943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29970 | /* 82949 */ GIR_RootConstrainSelectedInstOperands, |
| 29971 | /* 82950 */ // GIR_Coverage, 4993, |
| 29972 | /* 82950 */ GIR_EraseRootFromParent_Done, |
| 29973 | /* 82951 */ // Label 2562: @82951 |
| 29974 | /* 82951 */ GIM_Reject, |
| 29975 | /* 82952 */ // Label 2560: @82952 |
| 29976 | /* 82952 */ GIM_Try, /*On fail goto*//*Label 2563*/ GIMT_Encode4(83122), |
| 29977 | /* 82957 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 29978 | /* 82961 */ GIM_Try, /*On fail goto*//*Label 2564*/ GIMT_Encode4(83041), |
| 29979 | /* 82966 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 29980 | /* 82970 */ GIM_Try, /*On fail goto*//*Label 2565*/ GIMT_Encode4(83005), // Rule ID 4999 // |
| 29981 | /* 82975 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 29982 | /* 82979 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3954:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 29983 | /* 82979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32bh), |
| 29984 | /* 82982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29985 | /* 82984 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 29986 | /* 82986 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 29987 | /* 82988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29988 | /* 82991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29989 | /* 82997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 29990 | /* 83003 */ GIR_RootConstrainSelectedInstOperands, |
| 29991 | /* 83004 */ // GIR_Coverage, 4999, |
| 29992 | /* 83004 */ GIR_EraseRootFromParent_Done, |
| 29993 | /* 83005 */ // Label 2565: @83005 |
| 29994 | /* 83005 */ GIM_Try, /*On fail goto*//*Label 2566*/ GIMT_Encode4(83040), // Rule ID 5001 // |
| 29995 | /* 83010 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 29996 | /* 83014 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3954:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 29997 | /* 83014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32th), |
| 29998 | /* 83017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 29999 | /* 83019 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 30000 | /* 83021 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30001 | /* 83023 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30002 | /* 83026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30003 | /* 83032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30004 | /* 83038 */ GIR_RootConstrainSelectedInstOperands, |
| 30005 | /* 83039 */ // GIR_Coverage, 5001, |
| 30006 | /* 83039 */ GIR_EraseRootFromParent_Done, |
| 30007 | /* 83040 */ // Label 2566: @83040 |
| 30008 | /* 83040 */ GIM_Reject, |
| 30009 | /* 83041 */ // Label 2564: @83041 |
| 30010 | /* 83041 */ GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(83121), |
| 30011 | /* 83046 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30012 | /* 83050 */ GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(83085), // Rule ID 5007 // |
| 30013 | /* 83055 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30014 | /* 83059 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3954:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 30015 | /* 83059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32bh), |
| 30016 | /* 83062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30017 | /* 83064 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 30018 | /* 83066 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30019 | /* 83068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30020 | /* 83071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30021 | /* 83077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30022 | /* 83083 */ GIR_RootConstrainSelectedInstOperands, |
| 30023 | /* 83084 */ // GIR_Coverage, 5007, |
| 30024 | /* 83084 */ GIR_EraseRootFromParent_Done, |
| 30025 | /* 83085 */ // Label 2568: @83085 |
| 30026 | /* 83085 */ GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(83120), // Rule ID 5009 // |
| 30027 | /* 83090 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30028 | /* 83094 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3954:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm) |
| 30029 | /* 83094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32th), |
| 30030 | /* 83097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30031 | /* 83099 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src |
| 30032 | /* 83101 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 30033 | /* 83103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30034 | /* 83106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30035 | /* 83112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30036 | /* 83118 */ GIR_RootConstrainSelectedInstOperands, |
| 30037 | /* 83119 */ // GIR_Coverage, 5009, |
| 30038 | /* 83119 */ GIR_EraseRootFromParent_Done, |
| 30039 | /* 83120 */ // Label 2569: @83120 |
| 30040 | /* 83120 */ GIM_Reject, |
| 30041 | /* 83121 */ // Label 2567: @83121 |
| 30042 | /* 83121 */ GIM_Reject, |
| 30043 | /* 83122 */ // Label 2563: @83122 |
| 30044 | /* 83122 */ GIM_Reject, |
| 30045 | /* 83123 */ // Label 2559: @83123 |
| 30046 | /* 83123 */ GIM_Reject, |
| 30047 | /* 83124 */ // Label 2547: @83124 |
| 30048 | /* 83124 */ GIM_Reject, |
| 30049 | /* 83125 */ // Label 2544: @83125 |
| 30050 | /* 83125 */ GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(84289), |
| 30051 | /* 83130 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar), |
| 30052 | /* 83135 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2574*/ GIMT_Encode4(84288), |
| 30053 | /* 83146 */ /*GILLT_v16s8*//*Label 2571*/ GIMT_Encode4(83166), GIMT_Encode4(0), |
| 30054 | /* 83154 */ /*GILLT_v8s16*//*Label 2572*/ GIMT_Encode4(83540), GIMT_Encode4(0), |
| 30055 | /* 83162 */ /*GILLT_v4s32*//*Label 2573*/ GIMT_Encode4(83914), |
| 30056 | /* 83166 */ // Label 2571: @83166 |
| 30057 | /* 83166 */ GIM_Try, /*On fail goto*//*Label 2575*/ GIMT_Encode4(83539), |
| 30058 | /* 83171 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 30059 | /* 83174 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30060 | /* 83177 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30061 | /* 83180 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30062 | /* 83183 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30063 | /* 83186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30064 | /* 83190 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30065 | /* 83194 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30066 | /* 83198 */ GIM_Try, /*On fail goto*//*Label 2576*/ GIMT_Encode4(83368), |
| 30067 | /* 83203 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30068 | /* 83207 */ GIM_Try, /*On fail goto*//*Label 2577*/ GIMT_Encode4(83287), |
| 30069 | /* 83212 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30070 | /* 83216 */ GIM_Try, /*On fail goto*//*Label 2578*/ GIMT_Encode4(83251), // Rule ID 5215 // |
| 30071 | /* 83221 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30072 | /* 83225 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3987:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30073 | /* 83225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs8), |
| 30074 | /* 83228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30075 | /* 83230 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30076 | /* 83232 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30077 | /* 83234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30078 | /* 83237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30079 | /* 83243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30080 | /* 83249 */ GIR_RootConstrainSelectedInstOperands, |
| 30081 | /* 83250 */ // GIR_Coverage, 5215, |
| 30082 | /* 83250 */ GIR_EraseRootFromParent_Done, |
| 30083 | /* 83251 */ // Label 2578: @83251 |
| 30084 | /* 83251 */ GIM_Try, /*On fail goto*//*Label 2579*/ GIMT_Encode4(83286), // Rule ID 5221 // |
| 30085 | /* 83256 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30086 | /* 83260 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3987:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30087 | /* 83260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru8), |
| 30088 | /* 83263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30089 | /* 83265 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30090 | /* 83267 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30091 | /* 83269 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30092 | /* 83272 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30093 | /* 83278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30094 | /* 83284 */ GIR_RootConstrainSelectedInstOperands, |
| 30095 | /* 83285 */ // GIR_Coverage, 5221, |
| 30096 | /* 83285 */ GIR_EraseRootFromParent_Done, |
| 30097 | /* 83286 */ // Label 2579: @83286 |
| 30098 | /* 83286 */ GIM_Reject, |
| 30099 | /* 83287 */ // Label 2577: @83287 |
| 30100 | /* 83287 */ GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(83367), |
| 30101 | /* 83292 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30102 | /* 83296 */ GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(83331), // Rule ID 5227 // |
| 30103 | /* 83301 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30104 | /* 83305 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3987:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30105 | /* 83305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs8), |
| 30106 | /* 83308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30107 | /* 83310 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30108 | /* 83312 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30109 | /* 83314 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30110 | /* 83317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30111 | /* 83323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30112 | /* 83329 */ GIR_RootConstrainSelectedInstOperands, |
| 30113 | /* 83330 */ // GIR_Coverage, 5227, |
| 30114 | /* 83330 */ GIR_EraseRootFromParent_Done, |
| 30115 | /* 83331 */ // Label 2581: @83331 |
| 30116 | /* 83331 */ GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(83366), // Rule ID 5233 // |
| 30117 | /* 83336 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30118 | /* 83340 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3987:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30119 | /* 83340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru8), |
| 30120 | /* 83343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30121 | /* 83345 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30122 | /* 83347 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30123 | /* 83349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30124 | /* 83352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30125 | /* 83358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30126 | /* 83364 */ GIR_RootConstrainSelectedInstOperands, |
| 30127 | /* 83365 */ // GIR_Coverage, 5233, |
| 30128 | /* 83365 */ GIR_EraseRootFromParent_Done, |
| 30129 | /* 83366 */ // Label 2582: @83366 |
| 30130 | /* 83366 */ GIM_Reject, |
| 30131 | /* 83367 */ // Label 2580: @83367 |
| 30132 | /* 83367 */ GIM_Reject, |
| 30133 | /* 83368 */ // Label 2576: @83368 |
| 30134 | /* 83368 */ GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(83538), |
| 30135 | /* 83373 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30136 | /* 83377 */ GIM_Try, /*On fail goto*//*Label 2584*/ GIMT_Encode4(83457), |
| 30137 | /* 83382 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30138 | /* 83386 */ GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(83421), // Rule ID 5239 // |
| 30139 | /* 83391 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30140 | /* 83395 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3987:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30141 | /* 83395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs8), |
| 30142 | /* 83398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30143 | /* 83400 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30144 | /* 83402 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30145 | /* 83404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30146 | /* 83407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30147 | /* 83413 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30148 | /* 83419 */ GIR_RootConstrainSelectedInstOperands, |
| 30149 | /* 83420 */ // GIR_Coverage, 5239, |
| 30150 | /* 83420 */ GIR_EraseRootFromParent_Done, |
| 30151 | /* 83421 */ // Label 2585: @83421 |
| 30152 | /* 83421 */ GIM_Try, /*On fail goto*//*Label 2586*/ GIMT_Encode4(83456), // Rule ID 5245 // |
| 30153 | /* 83426 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30154 | /* 83430 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3987:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30155 | /* 83430 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru8), |
| 30156 | /* 83433 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30157 | /* 83435 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30158 | /* 83437 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30159 | /* 83439 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30160 | /* 83442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30161 | /* 83448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30162 | /* 83454 */ GIR_RootConstrainSelectedInstOperands, |
| 30163 | /* 83455 */ // GIR_Coverage, 5245, |
| 30164 | /* 83455 */ GIR_EraseRootFromParent_Done, |
| 30165 | /* 83456 */ // Label 2586: @83456 |
| 30166 | /* 83456 */ GIM_Reject, |
| 30167 | /* 83457 */ // Label 2584: @83457 |
| 30168 | /* 83457 */ GIM_Try, /*On fail goto*//*Label 2587*/ GIMT_Encode4(83537), |
| 30169 | /* 83462 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30170 | /* 83466 */ GIM_Try, /*On fail goto*//*Label 2588*/ GIMT_Encode4(83501), // Rule ID 5251 // |
| 30171 | /* 83471 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30172 | /* 83475 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3987:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30173 | /* 83475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs8), |
| 30174 | /* 83478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30175 | /* 83480 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30176 | /* 83482 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30177 | /* 83484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30178 | /* 83487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30179 | /* 83493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30180 | /* 83499 */ GIR_RootConstrainSelectedInstOperands, |
| 30181 | /* 83500 */ // GIR_Coverage, 5251, |
| 30182 | /* 83500 */ GIR_EraseRootFromParent_Done, |
| 30183 | /* 83501 */ // Label 2588: @83501 |
| 30184 | /* 83501 */ GIM_Try, /*On fail goto*//*Label 2589*/ GIMT_Encode4(83536), // Rule ID 5257 // |
| 30185 | /* 83506 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30186 | /* 83510 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3987:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30187 | /* 83510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru8), |
| 30188 | /* 83513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30189 | /* 83515 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30190 | /* 83517 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30191 | /* 83519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30192 | /* 83522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30193 | /* 83528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30194 | /* 83534 */ GIR_RootConstrainSelectedInstOperands, |
| 30195 | /* 83535 */ // GIR_Coverage, 5257, |
| 30196 | /* 83535 */ GIR_EraseRootFromParent_Done, |
| 30197 | /* 83536 */ // Label 2589: @83536 |
| 30198 | /* 83536 */ GIM_Reject, |
| 30199 | /* 83537 */ // Label 2587: @83537 |
| 30200 | /* 83537 */ GIM_Reject, |
| 30201 | /* 83538 */ // Label 2583: @83538 |
| 30202 | /* 83538 */ GIM_Reject, |
| 30203 | /* 83539 */ // Label 2575: @83539 |
| 30204 | /* 83539 */ GIM_Reject, |
| 30205 | /* 83540 */ // Label 2572: @83540 |
| 30206 | /* 83540 */ GIM_Try, /*On fail goto*//*Label 2590*/ GIMT_Encode4(83913), |
| 30207 | /* 83545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 30208 | /* 83548 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30209 | /* 83551 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30210 | /* 83554 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30211 | /* 83557 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30212 | /* 83560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30213 | /* 83564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30214 | /* 83568 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30215 | /* 83572 */ GIM_Try, /*On fail goto*//*Label 2591*/ GIMT_Encode4(83742), |
| 30216 | /* 83577 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30217 | /* 83581 */ GIM_Try, /*On fail goto*//*Label 2592*/ GIMT_Encode4(83661), |
| 30218 | /* 83586 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30219 | /* 83590 */ GIM_Try, /*On fail goto*//*Label 2593*/ GIMT_Encode4(83625), // Rule ID 5217 // |
| 30220 | /* 83595 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30221 | /* 83599 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3987:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30222 | /* 83599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs16), |
| 30223 | /* 83602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30224 | /* 83604 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30225 | /* 83606 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30226 | /* 83608 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30227 | /* 83611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30228 | /* 83617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30229 | /* 83623 */ GIR_RootConstrainSelectedInstOperands, |
| 30230 | /* 83624 */ // GIR_Coverage, 5217, |
| 30231 | /* 83624 */ GIR_EraseRootFromParent_Done, |
| 30232 | /* 83625 */ // Label 2593: @83625 |
| 30233 | /* 83625 */ GIM_Try, /*On fail goto*//*Label 2594*/ GIMT_Encode4(83660), // Rule ID 5223 // |
| 30234 | /* 83630 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30235 | /* 83634 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3987:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30236 | /* 83634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru16), |
| 30237 | /* 83637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30238 | /* 83639 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30239 | /* 83641 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30240 | /* 83643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30241 | /* 83646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30242 | /* 83652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30243 | /* 83658 */ GIR_RootConstrainSelectedInstOperands, |
| 30244 | /* 83659 */ // GIR_Coverage, 5223, |
| 30245 | /* 83659 */ GIR_EraseRootFromParent_Done, |
| 30246 | /* 83660 */ // Label 2594: @83660 |
| 30247 | /* 83660 */ GIM_Reject, |
| 30248 | /* 83661 */ // Label 2592: @83661 |
| 30249 | /* 83661 */ GIM_Try, /*On fail goto*//*Label 2595*/ GIMT_Encode4(83741), |
| 30250 | /* 83666 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30251 | /* 83670 */ GIM_Try, /*On fail goto*//*Label 2596*/ GIMT_Encode4(83705), // Rule ID 5229 // |
| 30252 | /* 83675 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30253 | /* 83679 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3987:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30254 | /* 83679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs16), |
| 30255 | /* 83682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30256 | /* 83684 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30257 | /* 83686 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30258 | /* 83688 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30259 | /* 83691 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30260 | /* 83697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30261 | /* 83703 */ GIR_RootConstrainSelectedInstOperands, |
| 30262 | /* 83704 */ // GIR_Coverage, 5229, |
| 30263 | /* 83704 */ GIR_EraseRootFromParent_Done, |
| 30264 | /* 83705 */ // Label 2596: @83705 |
| 30265 | /* 83705 */ GIM_Try, /*On fail goto*//*Label 2597*/ GIMT_Encode4(83740), // Rule ID 5235 // |
| 30266 | /* 83710 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30267 | /* 83714 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3987:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30268 | /* 83714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru16), |
| 30269 | /* 83717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30270 | /* 83719 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30271 | /* 83721 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30272 | /* 83723 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30273 | /* 83726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30274 | /* 83732 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30275 | /* 83738 */ GIR_RootConstrainSelectedInstOperands, |
| 30276 | /* 83739 */ // GIR_Coverage, 5235, |
| 30277 | /* 83739 */ GIR_EraseRootFromParent_Done, |
| 30278 | /* 83740 */ // Label 2597: @83740 |
| 30279 | /* 83740 */ GIM_Reject, |
| 30280 | /* 83741 */ // Label 2595: @83741 |
| 30281 | /* 83741 */ GIM_Reject, |
| 30282 | /* 83742 */ // Label 2591: @83742 |
| 30283 | /* 83742 */ GIM_Try, /*On fail goto*//*Label 2598*/ GIMT_Encode4(83912), |
| 30284 | /* 83747 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30285 | /* 83751 */ GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(83831), |
| 30286 | /* 83756 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30287 | /* 83760 */ GIM_Try, /*On fail goto*//*Label 2600*/ GIMT_Encode4(83795), // Rule ID 5241 // |
| 30288 | /* 83765 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30289 | /* 83769 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3987:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30290 | /* 83769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs16), |
| 30291 | /* 83772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30292 | /* 83774 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30293 | /* 83776 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30294 | /* 83778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30295 | /* 83781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30296 | /* 83787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30297 | /* 83793 */ GIR_RootConstrainSelectedInstOperands, |
| 30298 | /* 83794 */ // GIR_Coverage, 5241, |
| 30299 | /* 83794 */ GIR_EraseRootFromParent_Done, |
| 30300 | /* 83795 */ // Label 2600: @83795 |
| 30301 | /* 83795 */ GIM_Try, /*On fail goto*//*Label 2601*/ GIMT_Encode4(83830), // Rule ID 5247 // |
| 30302 | /* 83800 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30303 | /* 83804 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3987:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30304 | /* 83804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru16), |
| 30305 | /* 83807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30306 | /* 83809 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30307 | /* 83811 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30308 | /* 83813 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30309 | /* 83816 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30310 | /* 83822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30311 | /* 83828 */ GIR_RootConstrainSelectedInstOperands, |
| 30312 | /* 83829 */ // GIR_Coverage, 5247, |
| 30313 | /* 83829 */ GIR_EraseRootFromParent_Done, |
| 30314 | /* 83830 */ // Label 2601: @83830 |
| 30315 | /* 83830 */ GIM_Reject, |
| 30316 | /* 83831 */ // Label 2599: @83831 |
| 30317 | /* 83831 */ GIM_Try, /*On fail goto*//*Label 2602*/ GIMT_Encode4(83911), |
| 30318 | /* 83836 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30319 | /* 83840 */ GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(83875), // Rule ID 5253 // |
| 30320 | /* 83845 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30321 | /* 83849 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3987:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30322 | /* 83849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs16), |
| 30323 | /* 83852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30324 | /* 83854 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30325 | /* 83856 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30326 | /* 83858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30327 | /* 83861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30328 | /* 83867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30329 | /* 83873 */ GIR_RootConstrainSelectedInstOperands, |
| 30330 | /* 83874 */ // GIR_Coverage, 5253, |
| 30331 | /* 83874 */ GIR_EraseRootFromParent_Done, |
| 30332 | /* 83875 */ // Label 2603: @83875 |
| 30333 | /* 83875 */ GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(83910), // Rule ID 5259 // |
| 30334 | /* 83880 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30335 | /* 83884 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3987:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30336 | /* 83884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru16), |
| 30337 | /* 83887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30338 | /* 83889 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30339 | /* 83891 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30340 | /* 83893 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30341 | /* 83896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30342 | /* 83902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30343 | /* 83908 */ GIR_RootConstrainSelectedInstOperands, |
| 30344 | /* 83909 */ // GIR_Coverage, 5259, |
| 30345 | /* 83909 */ GIR_EraseRootFromParent_Done, |
| 30346 | /* 83910 */ // Label 2604: @83910 |
| 30347 | /* 83910 */ GIM_Reject, |
| 30348 | /* 83911 */ // Label 2602: @83911 |
| 30349 | /* 83911 */ GIM_Reject, |
| 30350 | /* 83912 */ // Label 2598: @83912 |
| 30351 | /* 83912 */ GIM_Reject, |
| 30352 | /* 83913 */ // Label 2590: @83913 |
| 30353 | /* 83913 */ GIM_Reject, |
| 30354 | /* 83914 */ // Label 2573: @83914 |
| 30355 | /* 83914 */ GIM_Try, /*On fail goto*//*Label 2605*/ GIMT_Encode4(84287), |
| 30356 | /* 83919 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 30357 | /* 83922 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30358 | /* 83925 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30359 | /* 83928 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30360 | /* 83931 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 30361 | /* 83934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30362 | /* 83938 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30363 | /* 83942 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 30364 | /* 83946 */ GIM_Try, /*On fail goto*//*Label 2606*/ GIMT_Encode4(84116), |
| 30365 | /* 83951 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30366 | /* 83955 */ GIM_Try, /*On fail goto*//*Label 2607*/ GIMT_Encode4(84035), |
| 30367 | /* 83960 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30368 | /* 83964 */ GIM_Try, /*On fail goto*//*Label 2608*/ GIMT_Encode4(83999), // Rule ID 5219 // |
| 30369 | /* 83969 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30370 | /* 83973 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3987:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30371 | /* 83973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs32), |
| 30372 | /* 83976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30373 | /* 83978 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30374 | /* 83980 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30375 | /* 83982 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30376 | /* 83985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30377 | /* 83991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30378 | /* 83997 */ GIR_RootConstrainSelectedInstOperands, |
| 30379 | /* 83998 */ // GIR_Coverage, 5219, |
| 30380 | /* 83998 */ GIR_EraseRootFromParent_Done, |
| 30381 | /* 83999 */ // Label 2608: @83999 |
| 30382 | /* 83999 */ GIM_Try, /*On fail goto*//*Label 2609*/ GIMT_Encode4(84034), // Rule ID 5225 // |
| 30383 | /* 84004 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30384 | /* 84008 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3987:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30385 | /* 84008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru32), |
| 30386 | /* 84011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30387 | /* 84013 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30388 | /* 84015 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30389 | /* 84017 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30390 | /* 84020 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30391 | /* 84026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30392 | /* 84032 */ GIR_RootConstrainSelectedInstOperands, |
| 30393 | /* 84033 */ // GIR_Coverage, 5225, |
| 30394 | /* 84033 */ GIR_EraseRootFromParent_Done, |
| 30395 | /* 84034 */ // Label 2609: @84034 |
| 30396 | /* 84034 */ GIM_Reject, |
| 30397 | /* 84035 */ // Label 2607: @84035 |
| 30398 | /* 84035 */ GIM_Try, /*On fail goto*//*Label 2610*/ GIMT_Encode4(84115), |
| 30399 | /* 84040 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30400 | /* 84044 */ GIM_Try, /*On fail goto*//*Label 2611*/ GIMT_Encode4(84079), // Rule ID 5231 // |
| 30401 | /* 84049 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30402 | /* 84053 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3987:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30403 | /* 84053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs32), |
| 30404 | /* 84056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30405 | /* 84058 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30406 | /* 84060 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30407 | /* 84062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30408 | /* 84065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30409 | /* 84071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30410 | /* 84077 */ GIR_RootConstrainSelectedInstOperands, |
| 30411 | /* 84078 */ // GIR_Coverage, 5231, |
| 30412 | /* 84078 */ GIR_EraseRootFromParent_Done, |
| 30413 | /* 84079 */ // Label 2611: @84079 |
| 30414 | /* 84079 */ GIM_Try, /*On fail goto*//*Label 2612*/ GIMT_Encode4(84114), // Rule ID 5237 // |
| 30415 | /* 84084 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30416 | /* 84088 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3987:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30417 | /* 84088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru32), |
| 30418 | /* 84091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30419 | /* 84093 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30420 | /* 84095 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30421 | /* 84097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30422 | /* 84100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30423 | /* 84106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30424 | /* 84112 */ GIR_RootConstrainSelectedInstOperands, |
| 30425 | /* 84113 */ // GIR_Coverage, 5237, |
| 30426 | /* 84113 */ GIR_EraseRootFromParent_Done, |
| 30427 | /* 84114 */ // Label 2612: @84114 |
| 30428 | /* 84114 */ GIM_Reject, |
| 30429 | /* 84115 */ // Label 2610: @84115 |
| 30430 | /* 84115 */ GIM_Reject, |
| 30431 | /* 84116 */ // Label 2606: @84116 |
| 30432 | /* 84116 */ GIM_Try, /*On fail goto*//*Label 2613*/ GIMT_Encode4(84286), |
| 30433 | /* 84121 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30434 | /* 84125 */ GIM_Try, /*On fail goto*//*Label 2614*/ GIMT_Encode4(84205), |
| 30435 | /* 84130 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30436 | /* 84134 */ GIM_Try, /*On fail goto*//*Label 2615*/ GIMT_Encode4(84169), // Rule ID 5243 // |
| 30437 | /* 84139 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30438 | /* 84143 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3987:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30439 | /* 84143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs32), |
| 30440 | /* 84146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30441 | /* 84148 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30442 | /* 84150 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30443 | /* 84152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30444 | /* 84155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30445 | /* 84161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30446 | /* 84167 */ GIR_RootConstrainSelectedInstOperands, |
| 30447 | /* 84168 */ // GIR_Coverage, 5243, |
| 30448 | /* 84168 */ GIR_EraseRootFromParent_Done, |
| 30449 | /* 84169 */ // Label 2615: @84169 |
| 30450 | /* 84169 */ GIM_Try, /*On fail goto*//*Label 2616*/ GIMT_Encode4(84204), // Rule ID 5249 // |
| 30451 | /* 84174 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30452 | /* 84178 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3987:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30453 | /* 84178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru32), |
| 30454 | /* 84181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30455 | /* 84183 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30456 | /* 84185 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30457 | /* 84187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30458 | /* 84190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30459 | /* 84196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30460 | /* 84202 */ GIR_RootConstrainSelectedInstOperands, |
| 30461 | /* 84203 */ // GIR_Coverage, 5249, |
| 30462 | /* 84203 */ GIR_EraseRootFromParent_Done, |
| 30463 | /* 84204 */ // Label 2616: @84204 |
| 30464 | /* 84204 */ GIM_Reject, |
| 30465 | /* 84205 */ // Label 2614: @84205 |
| 30466 | /* 84205 */ GIM_Try, /*On fail goto*//*Label 2617*/ GIMT_Encode4(84285), |
| 30467 | /* 84210 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 30468 | /* 84214 */ GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(84249), // Rule ID 5255 // |
| 30469 | /* 84219 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 30470 | /* 84223 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3987:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30471 | /* 84223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs32), |
| 30472 | /* 84226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30473 | /* 84228 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30474 | /* 84230 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30475 | /* 84232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30476 | /* 84235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30477 | /* 84241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30478 | /* 84247 */ GIR_RootConstrainSelectedInstOperands, |
| 30479 | /* 84248 */ // GIR_Coverage, 5255, |
| 30480 | /* 84248 */ GIR_EraseRootFromParent_Done, |
| 30481 | /* 84249 */ // Label 2618: @84249 |
| 30482 | /* 84249 */ GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(84284), // Rule ID 5261 // |
| 30483 | /* 84254 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 30484 | /* 84258 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3987:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh) |
| 30485 | /* 84258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru32), |
| 30486 | /* 84261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 30487 | /* 84263 */ GIR_RootToRootCopy, /*OpIdx*/2, // in |
| 30488 | /* 84265 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh |
| 30489 | /* 84267 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30490 | /* 84270 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30491 | /* 84276 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30492 | /* 84282 */ GIR_RootConstrainSelectedInstOperands, |
| 30493 | /* 84283 */ // GIR_Coverage, 5261, |
| 30494 | /* 84283 */ GIR_EraseRootFromParent_Done, |
| 30495 | /* 84284 */ // Label 2619: @84284 |
| 30496 | /* 84284 */ GIM_Reject, |
| 30497 | /* 84285 */ // Label 2617: @84285 |
| 30498 | /* 84285 */ GIM_Reject, |
| 30499 | /* 84286 */ // Label 2613: @84286 |
| 30500 | /* 84286 */ GIM_Reject, |
| 30501 | /* 84287 */ // Label 2605: @84287 |
| 30502 | /* 84287 */ GIM_Reject, |
| 30503 | /* 84288 */ // Label 2574: @84288 |
| 30504 | /* 84288 */ GIM_Reject, |
| 30505 | /* 84289 */ // Label 2570: @84289 |
| 30506 | /* 84289 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2620*/ GIMT_Encode4(84424), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3076 // |
| 30507 | /* 84296 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx3), |
| 30508 | /* 84301 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 30509 | /* 84304 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 30510 | /* 84307 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 30511 | /* 84310 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 30512 | /* 84313 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 30513 | /* 84316 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8, |
| 30514 | /* 84319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 30515 | /* 84323 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4146:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBX3Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 30516 | /* 84323 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8, |
| 30517 | /* 84326 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 30518 | /* 84330 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30519 | /* 84335 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 30520 | /* 84337 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 30521 | /* 84340 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 30522 | /* 84344 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30523 | /* 84349 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 |
| 30524 | /* 84353 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 30525 | /* 84356 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 |
| 30526 | /* 84360 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 30527 | /* 84363 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2 |
| 30528 | /* 84367 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 30529 | /* 84370 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 30530 | /* 84373 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 30531 | /* 84376 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 30532 | /* 84381 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 30533 | /* 84386 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 30534 | /* 84391 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 30535 | /* 84396 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 30536 | /* 84401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX3Pseudo), |
| 30537 | /* 84404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 30538 | /* 84406 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 30539 | /* 84408 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30540 | /* 84411 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm |
| 30541 | /* 84413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 30542 | /* 84416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30543 | /* 84422 */ GIR_RootConstrainSelectedInstOperands, |
| 30544 | /* 84423 */ // GIR_Coverage, 3076, |
| 30545 | /* 84423 */ GIR_EraseRootFromParent_Done, |
| 30546 | /* 84424 */ // Label 2620: @84424 |
| 30547 | /* 84424 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2621*/ GIMT_Encode4(84544), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3077 // |
| 30548 | /* 84431 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl4), |
| 30549 | /* 84436 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 30550 | /* 84439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 30551 | /* 84442 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 30552 | /* 84445 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 30553 | /* 84448 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 30554 | /* 84451 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8, |
| 30555 | /* 84454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 30556 | /* 84458 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4143:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBL4Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 30557 | /* 84458 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 30558 | /* 84461 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 30559 | /* 84465 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 30560 | /* 84470 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0 |
| 30561 | /* 84474 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 30562 | /* 84477 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1 |
| 30563 | /* 84481 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 30564 | /* 84484 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2 |
| 30565 | /* 84488 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 30566 | /* 84491 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn3 |
| 30567 | /* 84495 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 30568 | /* 84498 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 30569 | /* 84503 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 30570 | /* 84508 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 30571 | /* 84513 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 30572 | /* 84518 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 30573 | /* 84523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL4Pseudo), |
| 30574 | /* 84526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 30575 | /* 84528 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 30576 | /* 84531 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm |
| 30577 | /* 84533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 30578 | /* 84536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30579 | /* 84542 */ GIR_RootConstrainSelectedInstOperands, |
| 30580 | /* 84543 */ // GIR_Coverage, 3077, |
| 30581 | /* 84543 */ GIR_EraseRootFromParent_Done, |
| 30582 | /* 84544 */ // Label 2621: @84544 |
| 30583 | /* 84544 */ GIM_Reject, |
| 30584 | /* 84545 */ // Label 2496: @84545 |
| 30585 | /* 84545 */ GIM_Try, /*On fail goto*//*Label 2622*/ GIMT_Encode4(87739), |
| 30586 | /* 84550 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/8, |
| 30587 | /* 84553 */ GIM_Try, /*On fail goto*//*Label 2623*/ GIMT_Encode4(86368), |
| 30588 | /* 84558 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava), |
| 30589 | /* 84563 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 30590 | /* 84566 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 30591 | /* 84569 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 30592 | /* 84572 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 30593 | /* 84575 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 30594 | /* 84578 */ GIM_SwitchType, /*MI*/0, /*Op*/6, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2627*/ GIMT_Encode4(86367), |
| 30595 | /* 84589 */ /*GILLT_v16s8*//*Label 2624*/ GIMT_Encode4(84609), GIMT_Encode4(0), |
| 30596 | /* 84597 */ /*GILLT_v8s16*//*Label 2625*/ GIMT_Encode4(85195), GIMT_Encode4(0), |
| 30597 | /* 84605 */ /*GILLT_v4s32*//*Label 2626*/ GIMT_Encode4(85781), |
| 30598 | /* 84609 */ // Label 2624: @84609 |
| 30599 | /* 84609 */ GIM_Try, /*On fail goto*//*Label 2628*/ GIMT_Encode4(85194), |
| 30600 | /* 84614 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8, |
| 30601 | /* 84617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30602 | /* 84621 */ GIM_Try, /*On fail goto*//*Label 2629*/ GIMT_Encode4(84733), |
| 30603 | /* 84626 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30604 | /* 84630 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30605 | /* 84634 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2630*/ GIMT_Encode4(84683), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3569 // |
| 30606 | /* 84641 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30607 | /* 84645 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30608 | /* 84649 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30609 | /* 84653 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30610 | /* 84657 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30611 | /* 84657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs8), |
| 30612 | /* 84660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30613 | /* 84662 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30614 | /* 84664 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30615 | /* 84666 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30616 | /* 84669 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30617 | /* 84675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30618 | /* 84681 */ GIR_RootConstrainSelectedInstOperands, |
| 30619 | /* 84682 */ // GIR_Coverage, 3569, |
| 30620 | /* 84682 */ GIR_EraseRootFromParent_Done, |
| 30621 | /* 84683 */ // Label 2630: @84683 |
| 30622 | /* 84683 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2631*/ GIMT_Encode4(84732), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3573 // |
| 30623 | /* 84690 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30624 | /* 84694 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30625 | /* 84698 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30626 | /* 84702 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30627 | /* 84706 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30628 | /* 84706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs8), |
| 30629 | /* 84709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30630 | /* 84711 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30631 | /* 84713 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30632 | /* 84715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30633 | /* 84718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30634 | /* 84724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30635 | /* 84730 */ GIR_RootConstrainSelectedInstOperands, |
| 30636 | /* 84731 */ // GIR_Coverage, 3573, |
| 30637 | /* 84731 */ GIR_EraseRootFromParent_Done, |
| 30638 | /* 84732 */ // Label 2631: @84732 |
| 30639 | /* 84732 */ GIM_Reject, |
| 30640 | /* 84733 */ // Label 2629: @84733 |
| 30641 | /* 84733 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2632*/ GIMT_Encode4(84790), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3577 // |
| 30642 | /* 84740 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 30643 | /* 84744 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30644 | /* 84748 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30645 | /* 84752 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30646 | /* 84756 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30647 | /* 84760 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30648 | /* 84764 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVu8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30649 | /* 84764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8), |
| 30650 | /* 84767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30651 | /* 84769 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30652 | /* 84771 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30653 | /* 84773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30654 | /* 84776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30655 | /* 84782 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30656 | /* 84788 */ GIR_RootConstrainSelectedInstOperands, |
| 30657 | /* 84789 */ // GIR_Coverage, 3577, |
| 30658 | /* 84789 */ GIR_EraseRootFromParent_Done, |
| 30659 | /* 84790 */ // Label 2632: @84790 |
| 30660 | /* 84790 */ GIM_Try, /*On fail goto*//*Label 2633*/ GIMT_Encode4(84902), |
| 30661 | /* 84795 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30662 | /* 84799 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 30663 | /* 84803 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2634*/ GIMT_Encode4(84852), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3605 // |
| 30664 | /* 84810 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30665 | /* 84814 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30666 | /* 84818 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30667 | /* 84822 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30668 | /* 84826 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30669 | /* 84826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs8), |
| 30670 | /* 84829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30671 | /* 84831 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30672 | /* 84833 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30673 | /* 84835 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30674 | /* 84838 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30675 | /* 84844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30676 | /* 84850 */ GIR_RootConstrainSelectedInstOperands, |
| 30677 | /* 84851 */ // GIR_Coverage, 3605, |
| 30678 | /* 84851 */ GIR_EraseRootFromParent_Done, |
| 30679 | /* 84852 */ // Label 2634: @84852 |
| 30680 | /* 84852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2635*/ GIMT_Encode4(84901), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3609 // |
| 30681 | /* 84859 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30682 | /* 84863 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30683 | /* 84867 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30684 | /* 84871 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30685 | /* 84875 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30686 | /* 84875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs8), |
| 30687 | /* 84878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30688 | /* 84880 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30689 | /* 84882 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30690 | /* 84884 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30691 | /* 84887 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30692 | /* 84893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30693 | /* 84899 */ GIR_RootConstrainSelectedInstOperands, |
| 30694 | /* 84900 */ // GIR_Coverage, 3609, |
| 30695 | /* 84900 */ GIR_EraseRootFromParent_Done, |
| 30696 | /* 84901 */ // Label 2635: @84901 |
| 30697 | /* 84901 */ GIM_Reject, |
| 30698 | /* 84902 */ // Label 2633: @84902 |
| 30699 | /* 84902 */ GIM_Try, /*On fail goto*//*Label 2636*/ GIMT_Encode4(85018), |
| 30700 | /* 84907 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30701 | /* 84911 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30702 | /* 84915 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2637*/ GIMT_Encode4(84966), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3571 // |
| 30703 | /* 84922 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30704 | /* 84926 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30705 | /* 84930 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30706 | /* 84934 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30707 | /* 84938 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30708 | /* 84938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas8), |
| 30709 | /* 84941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30710 | /* 84943 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30711 | /* 84945 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30712 | /* 84947 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30713 | /* 84949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30714 | /* 84952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30715 | /* 84958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30716 | /* 84964 */ GIR_RootConstrainSelectedInstOperands, |
| 30717 | /* 84965 */ // GIR_Coverage, 3571, |
| 30718 | /* 84965 */ GIR_EraseRootFromParent_Done, |
| 30719 | /* 84966 */ // Label 2637: @84966 |
| 30720 | /* 84966 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2638*/ GIMT_Encode4(85017), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3575 // |
| 30721 | /* 84973 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30722 | /* 84977 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30723 | /* 84981 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30724 | /* 84985 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30725 | /* 84989 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30726 | /* 84989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs8), |
| 30727 | /* 84992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30728 | /* 84994 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30729 | /* 84996 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30730 | /* 84998 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30731 | /* 85000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30732 | /* 85003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30733 | /* 85009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30734 | /* 85015 */ GIR_RootConstrainSelectedInstOperands, |
| 30735 | /* 85016 */ // GIR_Coverage, 3575, |
| 30736 | /* 85016 */ GIR_EraseRootFromParent_Done, |
| 30737 | /* 85017 */ // Label 2638: @85017 |
| 30738 | /* 85017 */ GIM_Reject, |
| 30739 | /* 85018 */ // Label 2636: @85018 |
| 30740 | /* 85018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2639*/ GIMT_Encode4(85077), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3579 // |
| 30741 | /* 85025 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 30742 | /* 85029 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30743 | /* 85033 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30744 | /* 85037 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30745 | /* 85041 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30746 | /* 85045 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30747 | /* 85049 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVau8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30748 | /* 85049 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8), |
| 30749 | /* 85052 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30750 | /* 85054 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30751 | /* 85056 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30752 | /* 85058 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30753 | /* 85060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30754 | /* 85063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30755 | /* 85069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30756 | /* 85075 */ GIR_RootConstrainSelectedInstOperands, |
| 30757 | /* 85076 */ // GIR_Coverage, 3579, |
| 30758 | /* 85076 */ GIR_EraseRootFromParent_Done, |
| 30759 | /* 85077 */ // Label 2639: @85077 |
| 30760 | /* 85077 */ GIM_Try, /*On fail goto*//*Label 2640*/ GIMT_Encode4(85193), |
| 30761 | /* 85082 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30762 | /* 85086 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 30763 | /* 85090 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2641*/ GIMT_Encode4(85141), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3607 // |
| 30764 | /* 85097 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30765 | /* 85101 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30766 | /* 85105 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30767 | /* 85109 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30768 | /* 85113 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30769 | /* 85113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas8), |
| 30770 | /* 85116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30771 | /* 85118 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30772 | /* 85120 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30773 | /* 85122 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30774 | /* 85124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30775 | /* 85127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30776 | /* 85133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30777 | /* 85139 */ GIR_RootConstrainSelectedInstOperands, |
| 30778 | /* 85140 */ // GIR_Coverage, 3607, |
| 30779 | /* 85140 */ GIR_EraseRootFromParent_Done, |
| 30780 | /* 85141 */ // Label 2641: @85141 |
| 30781 | /* 85141 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2642*/ GIMT_Encode4(85192), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3611 // |
| 30782 | /* 85148 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30783 | /* 85152 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30784 | /* 85156 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30785 | /* 85160 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30786 | /* 85164 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) |
| 30787 | /* 85164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs8), |
| 30788 | /* 85167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30789 | /* 85169 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30790 | /* 85171 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30791 | /* 85173 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30792 | /* 85175 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30793 | /* 85178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30794 | /* 85184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30795 | /* 85190 */ GIR_RootConstrainSelectedInstOperands, |
| 30796 | /* 85191 */ // GIR_Coverage, 3611, |
| 30797 | /* 85191 */ GIR_EraseRootFromParent_Done, |
| 30798 | /* 85192 */ // Label 2642: @85192 |
| 30799 | /* 85192 */ GIM_Reject, |
| 30800 | /* 85193 */ // Label 2640: @85193 |
| 30801 | /* 85193 */ GIM_Reject, |
| 30802 | /* 85194 */ // Label 2628: @85194 |
| 30803 | /* 85194 */ GIM_Reject, |
| 30804 | /* 85195 */ // Label 2625: @85195 |
| 30805 | /* 85195 */ GIM_Try, /*On fail goto*//*Label 2643*/ GIMT_Encode4(85780), |
| 30806 | /* 85200 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16, |
| 30807 | /* 85203 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30808 | /* 85207 */ GIM_Try, /*On fail goto*//*Label 2644*/ GIMT_Encode4(85319), |
| 30809 | /* 85212 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30810 | /* 85216 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30811 | /* 85220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2645*/ GIMT_Encode4(85269), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3581 // |
| 30812 | /* 85227 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30813 | /* 85231 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30814 | /* 85235 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30815 | /* 85239 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30816 | /* 85243 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30817 | /* 85243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs16), |
| 30818 | /* 85246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30819 | /* 85248 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30820 | /* 85250 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30821 | /* 85252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30822 | /* 85255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30823 | /* 85261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30824 | /* 85267 */ GIR_RootConstrainSelectedInstOperands, |
| 30825 | /* 85268 */ // GIR_Coverage, 3581, |
| 30826 | /* 85268 */ GIR_EraseRootFromParent_Done, |
| 30827 | /* 85269 */ // Label 2645: @85269 |
| 30828 | /* 85269 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2646*/ GIMT_Encode4(85318), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3585 // |
| 30829 | /* 85276 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30830 | /* 85280 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30831 | /* 85284 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30832 | /* 85288 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30833 | /* 85292 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30834 | /* 85292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs16), |
| 30835 | /* 85295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30836 | /* 85297 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30837 | /* 85299 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30838 | /* 85301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30839 | /* 85304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30840 | /* 85310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30841 | /* 85316 */ GIR_RootConstrainSelectedInstOperands, |
| 30842 | /* 85317 */ // GIR_Coverage, 3585, |
| 30843 | /* 85317 */ GIR_EraseRootFromParent_Done, |
| 30844 | /* 85318 */ // Label 2646: @85318 |
| 30845 | /* 85318 */ GIM_Reject, |
| 30846 | /* 85319 */ // Label 2644: @85319 |
| 30847 | /* 85319 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2647*/ GIMT_Encode4(85376), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3589 // |
| 30848 | /* 85326 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 30849 | /* 85330 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30850 | /* 85334 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30851 | /* 85338 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30852 | /* 85342 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30853 | /* 85346 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30854 | /* 85350 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVu16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30855 | /* 85350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16), |
| 30856 | /* 85353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30857 | /* 85355 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30858 | /* 85357 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30859 | /* 85359 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30860 | /* 85362 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30861 | /* 85368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30862 | /* 85374 */ GIR_RootConstrainSelectedInstOperands, |
| 30863 | /* 85375 */ // GIR_Coverage, 3589, |
| 30864 | /* 85375 */ GIR_EraseRootFromParent_Done, |
| 30865 | /* 85376 */ // Label 2647: @85376 |
| 30866 | /* 85376 */ GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(85488), |
| 30867 | /* 85381 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30868 | /* 85385 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 30869 | /* 85389 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2649*/ GIMT_Encode4(85438), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3613 // |
| 30870 | /* 85396 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30871 | /* 85400 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30872 | /* 85404 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30873 | /* 85408 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30874 | /* 85412 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30875 | /* 85412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs16), |
| 30876 | /* 85415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30877 | /* 85417 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30878 | /* 85419 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30879 | /* 85421 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30880 | /* 85424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30881 | /* 85430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30882 | /* 85436 */ GIR_RootConstrainSelectedInstOperands, |
| 30883 | /* 85437 */ // GIR_Coverage, 3613, |
| 30884 | /* 85437 */ GIR_EraseRootFromParent_Done, |
| 30885 | /* 85438 */ // Label 2649: @85438 |
| 30886 | /* 85438 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2650*/ GIMT_Encode4(85487), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3617 // |
| 30887 | /* 85445 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30888 | /* 85449 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 30889 | /* 85453 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30890 | /* 85457 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30891 | /* 85461 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30892 | /* 85461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs16), |
| 30893 | /* 85464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30894 | /* 85466 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30895 | /* 85468 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30896 | /* 85470 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30897 | /* 85473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30898 | /* 85479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30899 | /* 85485 */ GIR_RootConstrainSelectedInstOperands, |
| 30900 | /* 85486 */ // GIR_Coverage, 3617, |
| 30901 | /* 85486 */ GIR_EraseRootFromParent_Done, |
| 30902 | /* 85487 */ // Label 2650: @85487 |
| 30903 | /* 85487 */ GIM_Reject, |
| 30904 | /* 85488 */ // Label 2648: @85488 |
| 30905 | /* 85488 */ GIM_Try, /*On fail goto*//*Label 2651*/ GIMT_Encode4(85604), |
| 30906 | /* 85493 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30907 | /* 85497 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30908 | /* 85501 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2652*/ GIMT_Encode4(85552), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3583 // |
| 30909 | /* 85508 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30910 | /* 85512 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30911 | /* 85516 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30912 | /* 85520 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30913 | /* 85524 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30914 | /* 85524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas16), |
| 30915 | /* 85527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30916 | /* 85529 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30917 | /* 85531 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30918 | /* 85533 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30919 | /* 85535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30920 | /* 85538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30921 | /* 85544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30922 | /* 85550 */ GIR_RootConstrainSelectedInstOperands, |
| 30923 | /* 85551 */ // GIR_Coverage, 3583, |
| 30924 | /* 85551 */ GIR_EraseRootFromParent_Done, |
| 30925 | /* 85552 */ // Label 2652: @85552 |
| 30926 | /* 85552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2653*/ GIMT_Encode4(85603), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3587 // |
| 30927 | /* 85559 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30928 | /* 85563 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30929 | /* 85567 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30930 | /* 85571 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30931 | /* 85575 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30932 | /* 85575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs16), |
| 30933 | /* 85578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30934 | /* 85580 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30935 | /* 85582 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30936 | /* 85584 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30937 | /* 85586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30938 | /* 85589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30939 | /* 85595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30940 | /* 85601 */ GIR_RootConstrainSelectedInstOperands, |
| 30941 | /* 85602 */ // GIR_Coverage, 3587, |
| 30942 | /* 85602 */ GIR_EraseRootFromParent_Done, |
| 30943 | /* 85603 */ // Label 2653: @85603 |
| 30944 | /* 85603 */ GIM_Reject, |
| 30945 | /* 85604 */ // Label 2651: @85604 |
| 30946 | /* 85604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2654*/ GIMT_Encode4(85663), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3591 // |
| 30947 | /* 85611 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 30948 | /* 85615 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 30949 | /* 85619 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30950 | /* 85623 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30951 | /* 85627 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30952 | /* 85631 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30953 | /* 85635 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVau16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30954 | /* 85635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16), |
| 30955 | /* 85638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30956 | /* 85640 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30957 | /* 85642 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30958 | /* 85644 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30959 | /* 85646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30960 | /* 85649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30961 | /* 85655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30962 | /* 85661 */ GIR_RootConstrainSelectedInstOperands, |
| 30963 | /* 85662 */ // GIR_Coverage, 3591, |
| 30964 | /* 85662 */ GIR_EraseRootFromParent_Done, |
| 30965 | /* 85663 */ // Label 2654: @85663 |
| 30966 | /* 85663 */ GIM_Try, /*On fail goto*//*Label 2655*/ GIMT_Encode4(85779), |
| 30967 | /* 85668 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 30968 | /* 85672 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 30969 | /* 85676 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2656*/ GIMT_Encode4(85727), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3615 // |
| 30970 | /* 85683 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 30971 | /* 85687 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30972 | /* 85691 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30973 | /* 85695 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30974 | /* 85699 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30975 | /* 85699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas16), |
| 30976 | /* 85702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30977 | /* 85704 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30978 | /* 85706 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30979 | /* 85708 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30980 | /* 85710 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30981 | /* 85713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30982 | /* 85719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 30983 | /* 85725 */ GIR_RootConstrainSelectedInstOperands, |
| 30984 | /* 85726 */ // GIR_Coverage, 3615, |
| 30985 | /* 85726 */ GIR_EraseRootFromParent_Done, |
| 30986 | /* 85727 */ // Label 2656: @85727 |
| 30987 | /* 85727 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2657*/ GIMT_Encode4(85778), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3619 // |
| 30988 | /* 85734 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 30989 | /* 85738 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 30990 | /* 85742 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30991 | /* 85746 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 30992 | /* 85750 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) |
| 30993 | /* 85750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs16), |
| 30994 | /* 85753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 30995 | /* 85755 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 30996 | /* 85757 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 30997 | /* 85759 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 30998 | /* 85761 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30999 | /* 85764 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31000 | /* 85770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31001 | /* 85776 */ GIR_RootConstrainSelectedInstOperands, |
| 31002 | /* 85777 */ // GIR_Coverage, 3619, |
| 31003 | /* 85777 */ GIR_EraseRootFromParent_Done, |
| 31004 | /* 85778 */ // Label 2657: @85778 |
| 31005 | /* 85778 */ GIM_Reject, |
| 31006 | /* 85779 */ // Label 2655: @85779 |
| 31007 | /* 85779 */ GIM_Reject, |
| 31008 | /* 85780 */ // Label 2643: @85780 |
| 31009 | /* 85780 */ GIM_Reject, |
| 31010 | /* 85781 */ // Label 2626: @85781 |
| 31011 | /* 85781 */ GIM_Try, /*On fail goto*//*Label 2658*/ GIMT_Encode4(86366), |
| 31012 | /* 85786 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32, |
| 31013 | /* 85789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 31014 | /* 85793 */ GIM_Try, /*On fail goto*//*Label 2659*/ GIMT_Encode4(85905), |
| 31015 | /* 85798 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 31016 | /* 85802 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 31017 | /* 85806 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2660*/ GIMT_Encode4(85855), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3593 // |
| 31018 | /* 85813 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31019 | /* 85817 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31020 | /* 85821 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31021 | /* 85825 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31022 | /* 85829 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31023 | /* 85829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs32), |
| 31024 | /* 85832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31025 | /* 85834 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31026 | /* 85836 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31027 | /* 85838 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31028 | /* 85841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31029 | /* 85847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31030 | /* 85853 */ GIR_RootConstrainSelectedInstOperands, |
| 31031 | /* 85854 */ // GIR_Coverage, 3593, |
| 31032 | /* 85854 */ GIR_EraseRootFromParent_Done, |
| 31033 | /* 85855 */ // Label 2660: @85855 |
| 31034 | /* 85855 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2661*/ GIMT_Encode4(85904), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3597 // |
| 31035 | /* 85862 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31036 | /* 85866 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31037 | /* 85870 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31038 | /* 85874 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31039 | /* 85878 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31040 | /* 85878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs32), |
| 31041 | /* 85881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31042 | /* 85883 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31043 | /* 85885 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31044 | /* 85887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31045 | /* 85890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31046 | /* 85896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31047 | /* 85902 */ GIR_RootConstrainSelectedInstOperands, |
| 31048 | /* 85903 */ // GIR_Coverage, 3597, |
| 31049 | /* 85903 */ GIR_EraseRootFromParent_Done, |
| 31050 | /* 85904 */ // Label 2661: @85904 |
| 31051 | /* 85904 */ GIM_Reject, |
| 31052 | /* 85905 */ // Label 2659: @85905 |
| 31053 | /* 85905 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2662*/ GIMT_Encode4(85962), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3601 // |
| 31054 | /* 85912 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 31055 | /* 85916 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 31056 | /* 85920 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31057 | /* 85924 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31058 | /* 85928 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31059 | /* 85932 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31060 | /* 85936 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVu32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31061 | /* 85936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32), |
| 31062 | /* 85939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31063 | /* 85941 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31064 | /* 85943 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31065 | /* 85945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31066 | /* 85948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31067 | /* 85954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31068 | /* 85960 */ GIR_RootConstrainSelectedInstOperands, |
| 31069 | /* 85961 */ // GIR_Coverage, 3601, |
| 31070 | /* 85961 */ GIR_EraseRootFromParent_Done, |
| 31071 | /* 85962 */ // Label 2662: @85962 |
| 31072 | /* 85962 */ GIM_Try, /*On fail goto*//*Label 2663*/ GIMT_Encode4(86074), |
| 31073 | /* 85967 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 31074 | /* 85971 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 31075 | /* 85975 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2664*/ GIMT_Encode4(86024), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3621 // |
| 31076 | /* 85982 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31077 | /* 85986 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31078 | /* 85990 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31079 | /* 85994 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31080 | /* 85998 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31081 | /* 85998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs32), |
| 31082 | /* 86001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31083 | /* 86003 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31084 | /* 86005 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31085 | /* 86007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31086 | /* 86010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31087 | /* 86016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31088 | /* 86022 */ GIR_RootConstrainSelectedInstOperands, |
| 31089 | /* 86023 */ // GIR_Coverage, 3621, |
| 31090 | /* 86023 */ GIR_EraseRootFromParent_Done, |
| 31091 | /* 86024 */ // Label 2664: @86024 |
| 31092 | /* 86024 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2665*/ GIMT_Encode4(86073), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3625 // |
| 31093 | /* 86031 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31094 | /* 86035 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31095 | /* 86039 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31096 | /* 86043 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31097 | /* 86047 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31098 | /* 86047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs32), |
| 31099 | /* 86050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31100 | /* 86052 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31101 | /* 86054 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31102 | /* 86056 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31103 | /* 86059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31104 | /* 86065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31105 | /* 86071 */ GIR_RootConstrainSelectedInstOperands, |
| 31106 | /* 86072 */ // GIR_Coverage, 3625, |
| 31107 | /* 86072 */ GIR_EraseRootFromParent_Done, |
| 31108 | /* 86073 */ // Label 2665: @86073 |
| 31109 | /* 86073 */ GIM_Reject, |
| 31110 | /* 86074 */ // Label 2663: @86074 |
| 31111 | /* 86074 */ GIM_Try, /*On fail goto*//*Label 2666*/ GIMT_Encode4(86190), |
| 31112 | /* 86079 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 31113 | /* 86083 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 31114 | /* 86087 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2667*/ GIMT_Encode4(86138), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3595 // |
| 31115 | /* 86094 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31116 | /* 86098 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 31117 | /* 86102 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31118 | /* 86106 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31119 | /* 86110 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31120 | /* 86110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas32), |
| 31121 | /* 86113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31122 | /* 86115 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 31123 | /* 86117 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31124 | /* 86119 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31125 | /* 86121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31126 | /* 86124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31127 | /* 86130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31128 | /* 86136 */ GIR_RootConstrainSelectedInstOperands, |
| 31129 | /* 86137 */ // GIR_Coverage, 3595, |
| 31130 | /* 86137 */ GIR_EraseRootFromParent_Done, |
| 31131 | /* 86138 */ // Label 2667: @86138 |
| 31132 | /* 86138 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2668*/ GIMT_Encode4(86189), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3599 // |
| 31133 | /* 86145 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31134 | /* 86149 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 31135 | /* 86153 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31136 | /* 86157 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31137 | /* 86161 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31138 | /* 86161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs32), |
| 31139 | /* 86164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31140 | /* 86166 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 31141 | /* 86168 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31142 | /* 86170 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31143 | /* 86172 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31144 | /* 86175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31145 | /* 86181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31146 | /* 86187 */ GIR_RootConstrainSelectedInstOperands, |
| 31147 | /* 86188 */ // GIR_Coverage, 3599, |
| 31148 | /* 86188 */ GIR_EraseRootFromParent_Done, |
| 31149 | /* 86189 */ // Label 2668: @86189 |
| 31150 | /* 86189 */ GIM_Reject, |
| 31151 | /* 86190 */ // Label 2666: @86190 |
| 31152 | /* 86190 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2669*/ GIMT_Encode4(86249), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3603 // |
| 31153 | /* 86197 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1, |
| 31154 | /* 86201 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 31155 | /* 86205 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31156 | /* 86209 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 31157 | /* 86213 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31158 | /* 86217 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31159 | /* 86221 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVau32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31160 | /* 86221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32), |
| 31161 | /* 86224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31162 | /* 86226 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 31163 | /* 86228 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31164 | /* 86230 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31165 | /* 86232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31166 | /* 86235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31167 | /* 86241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31168 | /* 86247 */ GIR_RootConstrainSelectedInstOperands, |
| 31169 | /* 86248 */ // GIR_Coverage, 3603, |
| 31170 | /* 86248 */ GIR_EraseRootFromParent_Done, |
| 31171 | /* 86249 */ // Label 2669: @86249 |
| 31172 | /* 86249 */ GIM_Try, /*On fail goto*//*Label 2670*/ GIMT_Encode4(86365), |
| 31173 | /* 86254 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 31174 | /* 86258 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1, |
| 31175 | /* 86262 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2671*/ GIMT_Encode4(86313), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3623 // |
| 31176 | /* 86269 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 31177 | /* 86273 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 31178 | /* 86277 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31179 | /* 86281 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31180 | /* 86285 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31181 | /* 86285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas32), |
| 31182 | /* 86288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31183 | /* 86290 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 31184 | /* 86292 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31185 | /* 86294 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31186 | /* 86296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31187 | /* 86299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31188 | /* 86305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31189 | /* 86311 */ GIR_RootConstrainSelectedInstOperands, |
| 31190 | /* 86312 */ // GIR_Coverage, 3623, |
| 31191 | /* 86312 */ GIR_EraseRootFromParent_Done, |
| 31192 | /* 86313 */ // Label 2671: @86313 |
| 31193 | /* 86313 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2672*/ GIMT_Encode4(86364), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3627 // |
| 31194 | /* 86320 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1, |
| 31195 | /* 86324 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 31196 | /* 86328 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31197 | /* 86332 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31198 | /* 86336 */ // (intrinsic_wo_chain:{ *:[i32] } 3935:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) |
| 31199 | /* 86336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs32), |
| 31200 | /* 86339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 31201 | /* 86341 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc |
| 31202 | /* 86343 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn |
| 31203 | /* 86345 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm |
| 31204 | /* 86347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31205 | /* 86350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31206 | /* 86356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31207 | /* 86362 */ GIR_RootConstrainSelectedInstOperands, |
| 31208 | /* 86363 */ // GIR_Coverage, 3627, |
| 31209 | /* 86363 */ GIR_EraseRootFromParent_Done, |
| 31210 | /* 86364 */ // Label 2672: @86364 |
| 31211 | /* 86364 */ GIM_Reject, |
| 31212 | /* 86365 */ // Label 2670: @86365 |
| 31213 | /* 86365 */ GIM_Reject, |
| 31214 | /* 86366 */ // Label 2658: @86366 |
| 31215 | /* 86366 */ GIM_Reject, |
| 31216 | /* 86367 */ // Label 2627: @86367 |
| 31217 | /* 86367 */ GIM_Reject, |
| 31218 | /* 86368 */ // Label 2623: @86368 |
| 31219 | /* 86368 */ GIM_Try, /*On fail goto*//*Label 2673*/ GIMT_Encode4(87613), |
| 31220 | /* 86373 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad), |
| 31221 | /* 86378 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2677*/ GIMT_Encode4(87612), |
| 31222 | /* 86389 */ /*GILLT_v16s8*//*Label 2674*/ GIMT_Encode4(86409), GIMT_Encode4(0), |
| 31223 | /* 86397 */ /*GILLT_v8s16*//*Label 2675*/ GIMT_Encode4(86810), GIMT_Encode4(0), |
| 31224 | /* 86405 */ /*GILLT_v4s32*//*Label 2676*/ GIMT_Encode4(87211), |
| 31225 | /* 86409 */ // Label 2674: @86409 |
| 31226 | /* 86409 */ GIM_Try, /*On fail goto*//*Label 2678*/ GIMT_Encode4(86809), |
| 31227 | /* 86414 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31228 | /* 86417 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 31229 | /* 86420 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8, |
| 31230 | /* 86423 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31231 | /* 86426 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31232 | /* 86429 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31233 | /* 86432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31234 | /* 86436 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31235 | /* 86440 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31236 | /* 86444 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31237 | /* 86448 */ GIM_Try, /*On fail goto*//*Label 2679*/ GIMT_Encode4(86493), // Rule ID 4837 // |
| 31238 | /* 86453 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31239 | /* 86457 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31240 | /* 86461 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31241 | /* 86465 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3945:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31242 | /* 86465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs8), |
| 31243 | /* 86468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31244 | /* 86470 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31245 | /* 86472 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31246 | /* 86474 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31247 | /* 86476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31248 | /* 86479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31249 | /* 86485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31250 | /* 86491 */ GIR_RootConstrainSelectedInstOperands, |
| 31251 | /* 86492 */ // GIR_Coverage, 4837, |
| 31252 | /* 86492 */ GIR_EraseRootFromParent_Done, |
| 31253 | /* 86493 */ // Label 2679: @86493 |
| 31254 | /* 86493 */ GIM_Try, /*On fail goto*//*Label 2680*/ GIMT_Encode4(86538), // Rule ID 4843 // |
| 31255 | /* 86498 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31256 | /* 86502 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31257 | /* 86506 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31258 | /* 86510 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3945:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31259 | /* 86510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs8), |
| 31260 | /* 86513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31261 | /* 86515 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31262 | /* 86517 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31263 | /* 86519 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31264 | /* 86521 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31265 | /* 86524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31266 | /* 86530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31267 | /* 86536 */ GIR_RootConstrainSelectedInstOperands, |
| 31268 | /* 86537 */ // GIR_Coverage, 4843, |
| 31269 | /* 86537 */ GIR_EraseRootFromParent_Done, |
| 31270 | /* 86538 */ // Label 2680: @86538 |
| 31271 | /* 86538 */ GIM_Try, /*On fail goto*//*Label 2681*/ GIMT_Encode4(86583), // Rule ID 4849 // |
| 31272 | /* 86543 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31273 | /* 86547 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31274 | /* 86551 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31275 | /* 86555 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3945:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31276 | /* 86555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs8), |
| 31277 | /* 86558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31278 | /* 86560 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31279 | /* 86562 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31280 | /* 86564 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31281 | /* 86566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31282 | /* 86569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31283 | /* 86575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31284 | /* 86581 */ GIR_RootConstrainSelectedInstOperands, |
| 31285 | /* 86582 */ // GIR_Coverage, 4849, |
| 31286 | /* 86582 */ GIR_EraseRootFromParent_Done, |
| 31287 | /* 86583 */ // Label 2681: @86583 |
| 31288 | /* 86583 */ GIM_Try, /*On fail goto*//*Label 2682*/ GIMT_Encode4(86628), // Rule ID 4855 // |
| 31289 | /* 86588 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31290 | /* 86592 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31291 | /* 86596 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31292 | /* 86600 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3945:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31293 | /* 86600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs8), |
| 31294 | /* 86603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31295 | /* 86605 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31296 | /* 86607 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31297 | /* 86609 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31298 | /* 86611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31299 | /* 86614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31300 | /* 86620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31301 | /* 86626 */ GIR_RootConstrainSelectedInstOperands, |
| 31302 | /* 86627 */ // GIR_Coverage, 4855, |
| 31303 | /* 86627 */ GIR_EraseRootFromParent_Done, |
| 31304 | /* 86628 */ // Label 2682: @86628 |
| 31305 | /* 86628 */ GIM_Try, /*On fail goto*//*Label 2683*/ GIMT_Encode4(86673), // Rule ID 4861 // |
| 31306 | /* 86633 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31307 | /* 86637 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31308 | /* 86641 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31309 | /* 86645 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3945:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31310 | /* 86645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs8), |
| 31311 | /* 86648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31312 | /* 86650 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31313 | /* 86652 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31314 | /* 86654 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31315 | /* 86656 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31316 | /* 86659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31317 | /* 86665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31318 | /* 86671 */ GIR_RootConstrainSelectedInstOperands, |
| 31319 | /* 86672 */ // GIR_Coverage, 4861, |
| 31320 | /* 86672 */ GIR_EraseRootFromParent_Done, |
| 31321 | /* 86673 */ // Label 2683: @86673 |
| 31322 | /* 86673 */ GIM_Try, /*On fail goto*//*Label 2684*/ GIMT_Encode4(86718), // Rule ID 4867 // |
| 31323 | /* 86678 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31324 | /* 86682 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31325 | /* 86686 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31326 | /* 86690 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3945:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31327 | /* 86690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs8), |
| 31328 | /* 86693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31329 | /* 86695 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31330 | /* 86697 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31331 | /* 86699 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31332 | /* 86701 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31333 | /* 86704 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31334 | /* 86710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31335 | /* 86716 */ GIR_RootConstrainSelectedInstOperands, |
| 31336 | /* 86717 */ // GIR_Coverage, 4867, |
| 31337 | /* 86717 */ GIR_EraseRootFromParent_Done, |
| 31338 | /* 86718 */ // Label 2684: @86718 |
| 31339 | /* 86718 */ GIM_Try, /*On fail goto*//*Label 2685*/ GIMT_Encode4(86763), // Rule ID 4873 // |
| 31340 | /* 86723 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31341 | /* 86727 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31342 | /* 86731 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31343 | /* 86735 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3945:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31344 | /* 86735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs8), |
| 31345 | /* 86738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31346 | /* 86740 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31347 | /* 86742 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31348 | /* 86744 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31349 | /* 86746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31350 | /* 86749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31351 | /* 86755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31352 | /* 86761 */ GIR_RootConstrainSelectedInstOperands, |
| 31353 | /* 86762 */ // GIR_Coverage, 4873, |
| 31354 | /* 86762 */ GIR_EraseRootFromParent_Done, |
| 31355 | /* 86763 */ // Label 2685: @86763 |
| 31356 | /* 86763 */ GIM_Try, /*On fail goto*//*Label 2686*/ GIMT_Encode4(86808), // Rule ID 4879 // |
| 31357 | /* 86768 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31358 | /* 86772 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31359 | /* 86776 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31360 | /* 86780 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3945:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c) |
| 31361 | /* 86780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs8), |
| 31362 | /* 86783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31363 | /* 86785 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31364 | /* 86787 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31365 | /* 86789 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31366 | /* 86791 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31367 | /* 86794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31368 | /* 86800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31369 | /* 86806 */ GIR_RootConstrainSelectedInstOperands, |
| 31370 | /* 86807 */ // GIR_Coverage, 4879, |
| 31371 | /* 86807 */ GIR_EraseRootFromParent_Done, |
| 31372 | /* 86808 */ // Label 2686: @86808 |
| 31373 | /* 86808 */ GIM_Reject, |
| 31374 | /* 86809 */ // Label 2678: @86809 |
| 31375 | /* 86809 */ GIM_Reject, |
| 31376 | /* 86810 */ // Label 2675: @86810 |
| 31377 | /* 86810 */ GIM_Try, /*On fail goto*//*Label 2687*/ GIMT_Encode4(87210), |
| 31378 | /* 86815 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 31379 | /* 86818 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31380 | /* 86821 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 31381 | /* 86824 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31382 | /* 86827 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31383 | /* 86830 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31384 | /* 86833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31385 | /* 86837 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31386 | /* 86841 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31387 | /* 86845 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31388 | /* 86849 */ GIM_Try, /*On fail goto*//*Label 2688*/ GIMT_Encode4(86894), // Rule ID 4839 // |
| 31389 | /* 86854 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31390 | /* 86858 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31391 | /* 86862 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31392 | /* 86866 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3945:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31393 | /* 86866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs16), |
| 31394 | /* 86869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31395 | /* 86871 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31396 | /* 86873 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31397 | /* 86875 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31398 | /* 86877 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31399 | /* 86880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31400 | /* 86886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31401 | /* 86892 */ GIR_RootConstrainSelectedInstOperands, |
| 31402 | /* 86893 */ // GIR_Coverage, 4839, |
| 31403 | /* 86893 */ GIR_EraseRootFromParent_Done, |
| 31404 | /* 86894 */ // Label 2688: @86894 |
| 31405 | /* 86894 */ GIM_Try, /*On fail goto*//*Label 2689*/ GIMT_Encode4(86939), // Rule ID 4845 // |
| 31406 | /* 86899 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31407 | /* 86903 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31408 | /* 86907 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31409 | /* 86911 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3945:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31410 | /* 86911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs16), |
| 31411 | /* 86914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31412 | /* 86916 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31413 | /* 86918 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31414 | /* 86920 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31415 | /* 86922 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31416 | /* 86925 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31417 | /* 86931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31418 | /* 86937 */ GIR_RootConstrainSelectedInstOperands, |
| 31419 | /* 86938 */ // GIR_Coverage, 4845, |
| 31420 | /* 86938 */ GIR_EraseRootFromParent_Done, |
| 31421 | /* 86939 */ // Label 2689: @86939 |
| 31422 | /* 86939 */ GIM_Try, /*On fail goto*//*Label 2690*/ GIMT_Encode4(86984), // Rule ID 4851 // |
| 31423 | /* 86944 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31424 | /* 86948 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31425 | /* 86952 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31426 | /* 86956 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3945:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31427 | /* 86956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs16), |
| 31428 | /* 86959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31429 | /* 86961 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31430 | /* 86963 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31431 | /* 86965 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31432 | /* 86967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31433 | /* 86970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31434 | /* 86976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31435 | /* 86982 */ GIR_RootConstrainSelectedInstOperands, |
| 31436 | /* 86983 */ // GIR_Coverage, 4851, |
| 31437 | /* 86983 */ GIR_EraseRootFromParent_Done, |
| 31438 | /* 86984 */ // Label 2690: @86984 |
| 31439 | /* 86984 */ GIM_Try, /*On fail goto*//*Label 2691*/ GIMT_Encode4(87029), // Rule ID 4857 // |
| 31440 | /* 86989 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31441 | /* 86993 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31442 | /* 86997 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31443 | /* 87001 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3945:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31444 | /* 87001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs16), |
| 31445 | /* 87004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31446 | /* 87006 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31447 | /* 87008 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31448 | /* 87010 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31449 | /* 87012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31450 | /* 87015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31451 | /* 87021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31452 | /* 87027 */ GIR_RootConstrainSelectedInstOperands, |
| 31453 | /* 87028 */ // GIR_Coverage, 4857, |
| 31454 | /* 87028 */ GIR_EraseRootFromParent_Done, |
| 31455 | /* 87029 */ // Label 2691: @87029 |
| 31456 | /* 87029 */ GIM_Try, /*On fail goto*//*Label 2692*/ GIMT_Encode4(87074), // Rule ID 4863 // |
| 31457 | /* 87034 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31458 | /* 87038 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31459 | /* 87042 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31460 | /* 87046 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3945:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31461 | /* 87046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs16), |
| 31462 | /* 87049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31463 | /* 87051 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31464 | /* 87053 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31465 | /* 87055 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31466 | /* 87057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31467 | /* 87060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31468 | /* 87066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31469 | /* 87072 */ GIR_RootConstrainSelectedInstOperands, |
| 31470 | /* 87073 */ // GIR_Coverage, 4863, |
| 31471 | /* 87073 */ GIR_EraseRootFromParent_Done, |
| 31472 | /* 87074 */ // Label 2692: @87074 |
| 31473 | /* 87074 */ GIM_Try, /*On fail goto*//*Label 2693*/ GIMT_Encode4(87119), // Rule ID 4869 // |
| 31474 | /* 87079 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31475 | /* 87083 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31476 | /* 87087 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31477 | /* 87091 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3945:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31478 | /* 87091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs16), |
| 31479 | /* 87094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31480 | /* 87096 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31481 | /* 87098 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31482 | /* 87100 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31483 | /* 87102 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31484 | /* 87105 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31485 | /* 87111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31486 | /* 87117 */ GIR_RootConstrainSelectedInstOperands, |
| 31487 | /* 87118 */ // GIR_Coverage, 4869, |
| 31488 | /* 87118 */ GIR_EraseRootFromParent_Done, |
| 31489 | /* 87119 */ // Label 2693: @87119 |
| 31490 | /* 87119 */ GIM_Try, /*On fail goto*//*Label 2694*/ GIMT_Encode4(87164), // Rule ID 4875 // |
| 31491 | /* 87124 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31492 | /* 87128 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31493 | /* 87132 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31494 | /* 87136 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3945:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31495 | /* 87136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs16), |
| 31496 | /* 87139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31497 | /* 87141 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31498 | /* 87143 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31499 | /* 87145 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31500 | /* 87147 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31501 | /* 87150 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31502 | /* 87156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31503 | /* 87162 */ GIR_RootConstrainSelectedInstOperands, |
| 31504 | /* 87163 */ // GIR_Coverage, 4875, |
| 31505 | /* 87163 */ GIR_EraseRootFromParent_Done, |
| 31506 | /* 87164 */ // Label 2694: @87164 |
| 31507 | /* 87164 */ GIM_Try, /*On fail goto*//*Label 2695*/ GIMT_Encode4(87209), // Rule ID 4881 // |
| 31508 | /* 87169 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31509 | /* 87173 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31510 | /* 87177 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31511 | /* 87181 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3945:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c) |
| 31512 | /* 87181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs16), |
| 31513 | /* 87184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31514 | /* 87186 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31515 | /* 87188 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31516 | /* 87190 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31517 | /* 87192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31518 | /* 87195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31519 | /* 87201 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31520 | /* 87207 */ GIR_RootConstrainSelectedInstOperands, |
| 31521 | /* 87208 */ // GIR_Coverage, 4881, |
| 31522 | /* 87208 */ GIR_EraseRootFromParent_Done, |
| 31523 | /* 87209 */ // Label 2695: @87209 |
| 31524 | /* 87209 */ GIM_Reject, |
| 31525 | /* 87210 */ // Label 2687: @87210 |
| 31526 | /* 87210 */ GIM_Reject, |
| 31527 | /* 87211 */ // Label 2676: @87211 |
| 31528 | /* 87211 */ GIM_Try, /*On fail goto*//*Label 2696*/ GIMT_Encode4(87611), |
| 31529 | /* 87216 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 31530 | /* 87219 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 31531 | /* 87222 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 31532 | /* 87225 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31533 | /* 87228 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31534 | /* 87231 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31535 | /* 87234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31536 | /* 87238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31537 | /* 87242 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31538 | /* 87246 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31539 | /* 87250 */ GIM_Try, /*On fail goto*//*Label 2697*/ GIMT_Encode4(87295), // Rule ID 4841 // |
| 31540 | /* 87255 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31541 | /* 87259 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31542 | /* 87263 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31543 | /* 87267 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3945:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31544 | /* 87267 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs32), |
| 31545 | /* 87270 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31546 | /* 87272 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31547 | /* 87274 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31548 | /* 87276 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31549 | /* 87278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31550 | /* 87281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31551 | /* 87287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31552 | /* 87293 */ GIR_RootConstrainSelectedInstOperands, |
| 31553 | /* 87294 */ // GIR_Coverage, 4841, |
| 31554 | /* 87294 */ GIR_EraseRootFromParent_Done, |
| 31555 | /* 87295 */ // Label 2697: @87295 |
| 31556 | /* 87295 */ GIM_Try, /*On fail goto*//*Label 2698*/ GIMT_Encode4(87340), // Rule ID 4847 // |
| 31557 | /* 87300 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31558 | /* 87304 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31559 | /* 87308 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31560 | /* 87312 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3945:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31561 | /* 87312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs32), |
| 31562 | /* 87315 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31563 | /* 87317 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31564 | /* 87319 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31565 | /* 87321 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31566 | /* 87323 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31567 | /* 87326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31568 | /* 87332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31569 | /* 87338 */ GIR_RootConstrainSelectedInstOperands, |
| 31570 | /* 87339 */ // GIR_Coverage, 4847, |
| 31571 | /* 87339 */ GIR_EraseRootFromParent_Done, |
| 31572 | /* 87340 */ // Label 2698: @87340 |
| 31573 | /* 87340 */ GIM_Try, /*On fail goto*//*Label 2699*/ GIMT_Encode4(87385), // Rule ID 4853 // |
| 31574 | /* 87345 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31575 | /* 87349 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31576 | /* 87353 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31577 | /* 87357 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3945:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31578 | /* 87357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs32), |
| 31579 | /* 87360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31580 | /* 87362 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31581 | /* 87364 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31582 | /* 87366 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31583 | /* 87368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31584 | /* 87371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31585 | /* 87377 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31586 | /* 87383 */ GIR_RootConstrainSelectedInstOperands, |
| 31587 | /* 87384 */ // GIR_Coverage, 4853, |
| 31588 | /* 87384 */ GIR_EraseRootFromParent_Done, |
| 31589 | /* 87385 */ // Label 2699: @87385 |
| 31590 | /* 87385 */ GIM_Try, /*On fail goto*//*Label 2700*/ GIMT_Encode4(87430), // Rule ID 4859 // |
| 31591 | /* 87390 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31592 | /* 87394 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31593 | /* 87398 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31594 | /* 87402 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3945:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31595 | /* 87402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs32), |
| 31596 | /* 87405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31597 | /* 87407 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31598 | /* 87409 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31599 | /* 87411 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31600 | /* 87413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31601 | /* 87416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31602 | /* 87422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31603 | /* 87428 */ GIR_RootConstrainSelectedInstOperands, |
| 31604 | /* 87429 */ // GIR_Coverage, 4859, |
| 31605 | /* 87429 */ GIR_EraseRootFromParent_Done, |
| 31606 | /* 87430 */ // Label 2700: @87430 |
| 31607 | /* 87430 */ GIM_Try, /*On fail goto*//*Label 2701*/ GIMT_Encode4(87475), // Rule ID 4865 // |
| 31608 | /* 87435 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31609 | /* 87439 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31610 | /* 87443 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31611 | /* 87447 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3945:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31612 | /* 87447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs32), |
| 31613 | /* 87450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31614 | /* 87452 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31615 | /* 87454 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31616 | /* 87456 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31617 | /* 87458 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31618 | /* 87461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31619 | /* 87467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31620 | /* 87473 */ GIR_RootConstrainSelectedInstOperands, |
| 31621 | /* 87474 */ // GIR_Coverage, 4865, |
| 31622 | /* 87474 */ GIR_EraseRootFromParent_Done, |
| 31623 | /* 87475 */ // Label 2701: @87475 |
| 31624 | /* 87475 */ GIM_Try, /*On fail goto*//*Label 2702*/ GIMT_Encode4(87520), // Rule ID 4871 // |
| 31625 | /* 87480 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31626 | /* 87484 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31627 | /* 87488 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31628 | /* 87492 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3945:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31629 | /* 87492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs32), |
| 31630 | /* 87495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31631 | /* 87497 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31632 | /* 87499 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31633 | /* 87501 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31634 | /* 87503 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31635 | /* 87506 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31636 | /* 87512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31637 | /* 87518 */ GIR_RootConstrainSelectedInstOperands, |
| 31638 | /* 87519 */ // GIR_Coverage, 4871, |
| 31639 | /* 87519 */ GIR_EraseRootFromParent_Done, |
| 31640 | /* 87520 */ // Label 2702: @87520 |
| 31641 | /* 87520 */ GIM_Try, /*On fail goto*//*Label 2703*/ GIMT_Encode4(87565), // Rule ID 4877 // |
| 31642 | /* 87525 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31643 | /* 87529 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31644 | /* 87533 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31645 | /* 87537 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3945:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31646 | /* 87537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs32), |
| 31647 | /* 87540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31648 | /* 87542 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31649 | /* 87544 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31650 | /* 87546 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31651 | /* 87548 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31652 | /* 87551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31653 | /* 87557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31654 | /* 87563 */ GIR_RootConstrainSelectedInstOperands, |
| 31655 | /* 87564 */ // GIR_Coverage, 4877, |
| 31656 | /* 87564 */ GIR_EraseRootFromParent_Done, |
| 31657 | /* 87565 */ // Label 2703: @87565 |
| 31658 | /* 87565 */ GIM_Try, /*On fail goto*//*Label 2704*/ GIMT_Encode4(87610), // Rule ID 4883 // |
| 31659 | /* 87570 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31660 | /* 87574 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31661 | /* 87578 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31662 | /* 87582 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3945:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c) |
| 31663 | /* 87582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs32), |
| 31664 | /* 87585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31665 | /* 87587 */ GIR_RootToRootCopy, /*OpIdx*/2, // a |
| 31666 | /* 87589 */ GIR_RootToRootCopy, /*OpIdx*/3, // b |
| 31667 | /* 87591 */ GIR_RootToRootCopy, /*OpIdx*/4, // c |
| 31668 | /* 87593 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31669 | /* 87596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31670 | /* 87602 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31671 | /* 87608 */ GIR_RootConstrainSelectedInstOperands, |
| 31672 | /* 87609 */ // GIR_Coverage, 4883, |
| 31673 | /* 87609 */ GIR_EraseRootFromParent_Done, |
| 31674 | /* 87610 */ // Label 2704: @87610 |
| 31675 | /* 87610 */ GIM_Reject, |
| 31676 | /* 87611 */ // Label 2696: @87611 |
| 31677 | /* 87611 */ GIM_Reject, |
| 31678 | /* 87612 */ // Label 2677: @87612 |
| 31679 | /* 87612 */ GIM_Reject, |
| 31680 | /* 87613 */ // Label 2673: @87613 |
| 31681 | /* 87613 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2705*/ GIMT_Encode4(87738), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3078 // |
| 31682 | /* 87620 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx4), |
| 31683 | /* 87625 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8, |
| 31684 | /* 87628 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 31685 | /* 87631 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8, |
| 31686 | /* 87634 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8, |
| 31687 | /* 87637 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8, |
| 31688 | /* 87640 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8, |
| 31689 | /* 87643 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s8, |
| 31690 | /* 87646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 31691 | /* 87650 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4147:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBX4Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm) |
| 31692 | /* 87650 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64, |
| 31693 | /* 87653 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 31694 | /* 87657 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 31695 | /* 87662 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0 |
| 31696 | /* 87666 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1, |
| 31697 | /* 87669 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1 |
| 31698 | /* 87673 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2, |
| 31699 | /* 87676 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2 |
| 31700 | /* 87680 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 31701 | /* 87683 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // Vn3 |
| 31702 | /* 87687 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 31703 | /* 87690 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID), |
| 31704 | /* 87695 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID), |
| 31705 | /* 87700 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID), |
| 31706 | /* 87705 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID), |
| 31707 | /* 87710 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID), |
| 31708 | /* 87715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX4Pseudo), |
| 31709 | /* 87718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 31710 | /* 87720 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig |
| 31711 | /* 87722 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 31712 | /* 87725 */ GIR_RootToRootCopy, /*OpIdx*/7, // Vm |
| 31713 | /* 87727 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 31714 | /* 87730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31715 | /* 87736 */ GIR_RootConstrainSelectedInstOperands, |
| 31716 | /* 87737 */ // GIR_Coverage, 3078, |
| 31717 | /* 87737 */ GIR_EraseRootFromParent_Done, |
| 31718 | /* 87738 */ // Label 2705: @87738 |
| 31719 | /* 87738 */ GIM_Reject, |
| 31720 | /* 87739 */ // Label 2622: @87739 |
| 31721 | /* 87739 */ GIM_Try, /*On fail goto*//*Label 2706*/ GIMT_Encode4(90358), |
| 31722 | /* 87744 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/10, |
| 31723 | /* 87747 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshrn), |
| 31724 | /* 87752 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 2709*/ GIMT_Encode4(90357), |
| 31725 | /* 87763 */ /*GILLT_v16s8*//*Label 2707*/ GIMT_Encode4(87775), GIMT_Encode4(0), |
| 31726 | /* 87771 */ /*GILLT_v8s16*//*Label 2708*/ GIMT_Encode4(89066), |
| 31727 | /* 87775 */ // Label 2707: @87775 |
| 31728 | /* 87775 */ GIM_Try, /*On fail goto*//*Label 2710*/ GIMT_Encode4(89065), |
| 31729 | /* 87780 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 31730 | /* 87783 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 31731 | /* 87786 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 31732 | /* 87789 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 31733 | /* 87792 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 31734 | /* 87795 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 31735 | /* 87798 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 31736 | /* 87801 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 31737 | /* 87804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31738 | /* 87808 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31739 | /* 87812 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 31740 | /* 87816 */ GIM_Try, /*On fail goto*//*Label 2711*/ GIMT_Encode4(88318), |
| 31741 | /* 87821 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 31742 | /* 87825 */ GIM_Try, /*On fail goto*//*Label 2712*/ GIMT_Encode4(88071), |
| 31743 | /* 87830 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31744 | /* 87834 */ GIM_Try, /*On fail goto*//*Label 2713*/ GIMT_Encode4(87952), |
| 31745 | /* 87839 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31746 | /* 87843 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31747 | /* 87847 */ GIM_Try, /*On fail goto*//*Label 2714*/ GIMT_Encode4(87899), // Rule ID 4152 // |
| 31748 | /* 87852 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31749 | /* 87856 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31750 | /* 87860 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31751 | /* 87864 */ // MIs[1] Operand 1 |
| 31752 | /* 87864 */ // No operand predicates |
| 31753 | /* 87864 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31754 | /* 87868 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31755 | /* 87870 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31756 | /* 87870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh), |
| 31757 | /* 87873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31758 | /* 87875 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31759 | /* 87877 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31760 | /* 87879 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31761 | /* 87882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31762 | /* 87885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31763 | /* 87891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31764 | /* 87897 */ GIR_RootConstrainSelectedInstOperands, |
| 31765 | /* 87898 */ // GIR_Coverage, 4152, |
| 31766 | /* 87898 */ GIR_EraseRootFromParent_Done, |
| 31767 | /* 87899 */ // Label 2714: @87899 |
| 31768 | /* 87899 */ GIM_Try, /*On fail goto*//*Label 2715*/ GIMT_Encode4(87951), // Rule ID 4154 // |
| 31769 | /* 87904 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31770 | /* 87908 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31771 | /* 87912 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31772 | /* 87916 */ // MIs[1] Operand 1 |
| 31773 | /* 87916 */ // No operand predicates |
| 31774 | /* 87916 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31775 | /* 87920 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31776 | /* 87922 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31777 | /* 87922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th), |
| 31778 | /* 87925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31779 | /* 87927 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31780 | /* 87929 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31781 | /* 87931 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31782 | /* 87934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31783 | /* 87937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31784 | /* 87943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31785 | /* 87949 */ GIR_RootConstrainSelectedInstOperands, |
| 31786 | /* 87950 */ // GIR_Coverage, 4154, |
| 31787 | /* 87950 */ GIR_EraseRootFromParent_Done, |
| 31788 | /* 87951 */ // Label 2715: @87951 |
| 31789 | /* 87951 */ GIM_Reject, |
| 31790 | /* 87952 */ // Label 2713: @87952 |
| 31791 | /* 87952 */ GIM_Try, /*On fail goto*//*Label 2716*/ GIMT_Encode4(88070), |
| 31792 | /* 87957 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31793 | /* 87961 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31794 | /* 87965 */ GIM_Try, /*On fail goto*//*Label 2717*/ GIMT_Encode4(88017), // Rule ID 4160 // |
| 31795 | /* 87970 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31796 | /* 87974 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31797 | /* 87978 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31798 | /* 87982 */ // MIs[1] Operand 1 |
| 31799 | /* 87982 */ // No operand predicates |
| 31800 | /* 87982 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31801 | /* 87986 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31802 | /* 87988 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31803 | /* 87988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh), |
| 31804 | /* 87991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31805 | /* 87993 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31806 | /* 87995 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31807 | /* 87997 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31808 | /* 88000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31809 | /* 88003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31810 | /* 88009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31811 | /* 88015 */ GIR_RootConstrainSelectedInstOperands, |
| 31812 | /* 88016 */ // GIR_Coverage, 4160, |
| 31813 | /* 88016 */ GIR_EraseRootFromParent_Done, |
| 31814 | /* 88017 */ // Label 2717: @88017 |
| 31815 | /* 88017 */ GIM_Try, /*On fail goto*//*Label 2718*/ GIMT_Encode4(88069), // Rule ID 4162 // |
| 31816 | /* 88022 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31817 | /* 88026 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31818 | /* 88030 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31819 | /* 88034 */ // MIs[1] Operand 1 |
| 31820 | /* 88034 */ // No operand predicates |
| 31821 | /* 88034 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31822 | /* 88038 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31823 | /* 88040 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31824 | /* 88040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th), |
| 31825 | /* 88043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31826 | /* 88045 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31827 | /* 88047 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31828 | /* 88049 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31829 | /* 88052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31830 | /* 88055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31831 | /* 88061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31832 | /* 88067 */ GIR_RootConstrainSelectedInstOperands, |
| 31833 | /* 88068 */ // GIR_Coverage, 4162, |
| 31834 | /* 88068 */ GIR_EraseRootFromParent_Done, |
| 31835 | /* 88069 */ // Label 2718: @88069 |
| 31836 | /* 88069 */ GIM_Reject, |
| 31837 | /* 88070 */ // Label 2716: @88070 |
| 31838 | /* 88070 */ GIM_Reject, |
| 31839 | /* 88071 */ // Label 2712: @88071 |
| 31840 | /* 88071 */ GIM_Try, /*On fail goto*//*Label 2719*/ GIMT_Encode4(88317), |
| 31841 | /* 88076 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 31842 | /* 88080 */ GIM_Try, /*On fail goto*//*Label 2720*/ GIMT_Encode4(88198), |
| 31843 | /* 88085 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31844 | /* 88089 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31845 | /* 88093 */ GIM_Try, /*On fail goto*//*Label 2721*/ GIMT_Encode4(88145), // Rule ID 4168 // |
| 31846 | /* 88098 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31847 | /* 88102 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31848 | /* 88106 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31849 | /* 88110 */ // MIs[1] Operand 1 |
| 31850 | /* 88110 */ // No operand predicates |
| 31851 | /* 88110 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31852 | /* 88114 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31853 | /* 88116 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31854 | /* 88116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh), |
| 31855 | /* 88119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31856 | /* 88121 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31857 | /* 88123 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31858 | /* 88125 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31859 | /* 88128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31860 | /* 88131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31861 | /* 88137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31862 | /* 88143 */ GIR_RootConstrainSelectedInstOperands, |
| 31863 | /* 88144 */ // GIR_Coverage, 4168, |
| 31864 | /* 88144 */ GIR_EraseRootFromParent_Done, |
| 31865 | /* 88145 */ // Label 2721: @88145 |
| 31866 | /* 88145 */ GIM_Try, /*On fail goto*//*Label 2722*/ GIMT_Encode4(88197), // Rule ID 4170 // |
| 31867 | /* 88150 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31868 | /* 88154 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31869 | /* 88158 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31870 | /* 88162 */ // MIs[1] Operand 1 |
| 31871 | /* 88162 */ // No operand predicates |
| 31872 | /* 88162 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31873 | /* 88166 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31874 | /* 88168 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31875 | /* 88168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th), |
| 31876 | /* 88171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31877 | /* 88173 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31878 | /* 88175 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31879 | /* 88177 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31880 | /* 88180 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31881 | /* 88183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31882 | /* 88189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31883 | /* 88195 */ GIR_RootConstrainSelectedInstOperands, |
| 31884 | /* 88196 */ // GIR_Coverage, 4170, |
| 31885 | /* 88196 */ GIR_EraseRootFromParent_Done, |
| 31886 | /* 88197 */ // Label 2722: @88197 |
| 31887 | /* 88197 */ GIM_Reject, |
| 31888 | /* 88198 */ // Label 2720: @88198 |
| 31889 | /* 88198 */ GIM_Try, /*On fail goto*//*Label 2723*/ GIMT_Encode4(88316), |
| 31890 | /* 88203 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31891 | /* 88207 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31892 | /* 88211 */ GIM_Try, /*On fail goto*//*Label 2724*/ GIMT_Encode4(88263), // Rule ID 4176 // |
| 31893 | /* 88216 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31894 | /* 88220 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31895 | /* 88224 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31896 | /* 88228 */ // MIs[1] Operand 1 |
| 31897 | /* 88228 */ // No operand predicates |
| 31898 | /* 88228 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31899 | /* 88232 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31900 | /* 88234 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31901 | /* 88234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh), |
| 31902 | /* 88237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31903 | /* 88239 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31904 | /* 88241 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31905 | /* 88243 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31906 | /* 88246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31907 | /* 88249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31908 | /* 88255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31909 | /* 88261 */ GIR_RootConstrainSelectedInstOperands, |
| 31910 | /* 88262 */ // GIR_Coverage, 4176, |
| 31911 | /* 88262 */ GIR_EraseRootFromParent_Done, |
| 31912 | /* 88263 */ // Label 2724: @88263 |
| 31913 | /* 88263 */ GIM_Try, /*On fail goto*//*Label 2725*/ GIMT_Encode4(88315), // Rule ID 4178 // |
| 31914 | /* 88268 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31915 | /* 88272 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31916 | /* 88276 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31917 | /* 88280 */ // MIs[1] Operand 1 |
| 31918 | /* 88280 */ // No operand predicates |
| 31919 | /* 88280 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31920 | /* 88284 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31921 | /* 88286 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31922 | /* 88286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th), |
| 31923 | /* 88289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31924 | /* 88291 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31925 | /* 88293 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31926 | /* 88295 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31927 | /* 88298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31928 | /* 88301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31929 | /* 88307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31930 | /* 88313 */ GIR_RootConstrainSelectedInstOperands, |
| 31931 | /* 88314 */ // GIR_Coverage, 4178, |
| 31932 | /* 88314 */ GIR_EraseRootFromParent_Done, |
| 31933 | /* 88315 */ // Label 2725: @88315 |
| 31934 | /* 88315 */ GIM_Reject, |
| 31935 | /* 88316 */ // Label 2723: @88316 |
| 31936 | /* 88316 */ GIM_Reject, |
| 31937 | /* 88317 */ // Label 2719: @88317 |
| 31938 | /* 88317 */ GIM_Reject, |
| 31939 | /* 88318 */ // Label 2711: @88318 |
| 31940 | /* 88318 */ GIM_Try, /*On fail goto*//*Label 2726*/ GIMT_Encode4(89064), |
| 31941 | /* 88323 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 31942 | /* 88327 */ GIM_Try, /*On fail goto*//*Label 2727*/ GIMT_Encode4(88573), |
| 31943 | /* 88332 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 31944 | /* 88336 */ GIM_Try, /*On fail goto*//*Label 2728*/ GIMT_Encode4(88454), |
| 31945 | /* 88341 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 31946 | /* 88345 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 31947 | /* 88349 */ GIM_Try, /*On fail goto*//*Label 2729*/ GIMT_Encode4(88401), // Rule ID 4184 // |
| 31948 | /* 88354 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31949 | /* 88358 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31950 | /* 88362 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31951 | /* 88366 */ // MIs[1] Operand 1 |
| 31952 | /* 88366 */ // No operand predicates |
| 31953 | /* 88366 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 31954 | /* 88370 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31955 | /* 88372 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31956 | /* 88372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs16), |
| 31957 | /* 88375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31958 | /* 88377 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31959 | /* 88379 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31960 | /* 88381 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31961 | /* 88384 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31962 | /* 88387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31963 | /* 88393 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31964 | /* 88399 */ GIR_RootConstrainSelectedInstOperands, |
| 31965 | /* 88400 */ // GIR_Coverage, 4184, |
| 31966 | /* 88400 */ GIR_EraseRootFromParent_Done, |
| 31967 | /* 88401 */ // Label 2729: @88401 |
| 31968 | /* 88401 */ GIM_Try, /*On fail goto*//*Label 2730*/ GIMT_Encode4(88453), // Rule ID 4186 // |
| 31969 | /* 88406 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31970 | /* 88410 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31971 | /* 88414 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31972 | /* 88418 */ // MIs[1] Operand 1 |
| 31973 | /* 88418 */ // No operand predicates |
| 31974 | /* 88418 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 31975 | /* 88422 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 31976 | /* 88424 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 31977 | /* 88424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths16), |
| 31978 | /* 88427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 31979 | /* 88429 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 31980 | /* 88431 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 31981 | /* 88433 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 31982 | /* 88436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31983 | /* 88439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31984 | /* 88445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 31985 | /* 88451 */ GIR_RootConstrainSelectedInstOperands, |
| 31986 | /* 88452 */ // GIR_Coverage, 4186, |
| 31987 | /* 88452 */ GIR_EraseRootFromParent_Done, |
| 31988 | /* 88453 */ // Label 2730: @88453 |
| 31989 | /* 88453 */ GIM_Reject, |
| 31990 | /* 88454 */ // Label 2728: @88454 |
| 31991 | /* 88454 */ GIM_Try, /*On fail goto*//*Label 2731*/ GIMT_Encode4(88572), |
| 31992 | /* 88459 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 31993 | /* 88463 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 31994 | /* 88467 */ GIM_Try, /*On fail goto*//*Label 2732*/ GIMT_Encode4(88519), // Rule ID 4192 // |
| 31995 | /* 88472 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 31996 | /* 88476 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 31997 | /* 88480 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 31998 | /* 88484 */ // MIs[1] Operand 1 |
| 31999 | /* 88484 */ // No operand predicates |
| 32000 | /* 88484 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32001 | /* 88488 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32002 | /* 88490 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32003 | /* 88490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu16), |
| 32004 | /* 88493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32005 | /* 88495 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32006 | /* 88497 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32007 | /* 88499 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32008 | /* 88502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32009 | /* 88505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32010 | /* 88511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32011 | /* 88517 */ GIR_RootConstrainSelectedInstOperands, |
| 32012 | /* 88518 */ // GIR_Coverage, 4192, |
| 32013 | /* 88518 */ GIR_EraseRootFromParent_Done, |
| 32014 | /* 88519 */ // Label 2732: @88519 |
| 32015 | /* 88519 */ GIM_Try, /*On fail goto*//*Label 2733*/ GIMT_Encode4(88571), // Rule ID 4194 // |
| 32016 | /* 88524 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32017 | /* 88528 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32018 | /* 88532 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32019 | /* 88536 */ // MIs[1] Operand 1 |
| 32020 | /* 88536 */ // No operand predicates |
| 32021 | /* 88536 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32022 | /* 88540 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32023 | /* 88542 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32024 | /* 88542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu16), |
| 32025 | /* 88545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32026 | /* 88547 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32027 | /* 88549 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32028 | /* 88551 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32029 | /* 88554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32030 | /* 88557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32031 | /* 88563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32032 | /* 88569 */ GIR_RootConstrainSelectedInstOperands, |
| 32033 | /* 88570 */ // GIR_Coverage, 4194, |
| 32034 | /* 88570 */ GIR_EraseRootFromParent_Done, |
| 32035 | /* 88571 */ // Label 2733: @88571 |
| 32036 | /* 88571 */ GIM_Reject, |
| 32037 | /* 88572 */ // Label 2731: @88572 |
| 32038 | /* 88572 */ GIM_Reject, |
| 32039 | /* 88573 */ // Label 2727: @88573 |
| 32040 | /* 88573 */ GIM_Try, /*On fail goto*//*Label 2734*/ GIMT_Encode4(88819), |
| 32041 | /* 88578 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32042 | /* 88582 */ GIM_Try, /*On fail goto*//*Label 2735*/ GIMT_Encode4(88700), |
| 32043 | /* 88587 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 32044 | /* 88591 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32045 | /* 88595 */ GIM_Try, /*On fail goto*//*Label 2736*/ GIMT_Encode4(88647), // Rule ID 4200 // |
| 32046 | /* 88600 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32047 | /* 88604 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32048 | /* 88608 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32049 | /* 88612 */ // MIs[1] Operand 1 |
| 32050 | /* 88612 */ // No operand predicates |
| 32051 | /* 88612 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32052 | /* 88616 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32053 | /* 88618 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32054 | /* 88618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs16), |
| 32055 | /* 88621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32056 | /* 88623 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32057 | /* 88625 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32058 | /* 88627 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32059 | /* 88630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32060 | /* 88633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32061 | /* 88639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32062 | /* 88645 */ GIR_RootConstrainSelectedInstOperands, |
| 32063 | /* 88646 */ // GIR_Coverage, 4200, |
| 32064 | /* 88646 */ GIR_EraseRootFromParent_Done, |
| 32065 | /* 88647 */ // Label 2736: @88647 |
| 32066 | /* 88647 */ GIM_Try, /*On fail goto*//*Label 2737*/ GIMT_Encode4(88699), // Rule ID 4202 // |
| 32067 | /* 88652 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32068 | /* 88656 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32069 | /* 88660 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32070 | /* 88664 */ // MIs[1] Operand 1 |
| 32071 | /* 88664 */ // No operand predicates |
| 32072 | /* 88664 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32073 | /* 88668 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32074 | /* 88670 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32075 | /* 88670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths16), |
| 32076 | /* 88673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32077 | /* 88675 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32078 | /* 88677 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32079 | /* 88679 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32080 | /* 88682 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32081 | /* 88685 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32082 | /* 88691 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32083 | /* 88697 */ GIR_RootConstrainSelectedInstOperands, |
| 32084 | /* 88698 */ // GIR_Coverage, 4202, |
| 32085 | /* 88698 */ GIR_EraseRootFromParent_Done, |
| 32086 | /* 88699 */ // Label 2737: @88699 |
| 32087 | /* 88699 */ GIM_Reject, |
| 32088 | /* 88700 */ // Label 2735: @88700 |
| 32089 | /* 88700 */ GIM_Try, /*On fail goto*//*Label 2738*/ GIMT_Encode4(88818), |
| 32090 | /* 88705 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32091 | /* 88709 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32092 | /* 88713 */ GIM_Try, /*On fail goto*//*Label 2739*/ GIMT_Encode4(88765), // Rule ID 4208 // |
| 32093 | /* 88718 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32094 | /* 88722 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32095 | /* 88726 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32096 | /* 88730 */ // MIs[1] Operand 1 |
| 32097 | /* 88730 */ // No operand predicates |
| 32098 | /* 88730 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32099 | /* 88734 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32100 | /* 88736 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32101 | /* 88736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu16), |
| 32102 | /* 88739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32103 | /* 88741 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32104 | /* 88743 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32105 | /* 88745 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32106 | /* 88748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32107 | /* 88751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32108 | /* 88757 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32109 | /* 88763 */ GIR_RootConstrainSelectedInstOperands, |
| 32110 | /* 88764 */ // GIR_Coverage, 4208, |
| 32111 | /* 88764 */ GIR_EraseRootFromParent_Done, |
| 32112 | /* 88765 */ // Label 2739: @88765 |
| 32113 | /* 88765 */ GIM_Try, /*On fail goto*//*Label 2740*/ GIMT_Encode4(88817), // Rule ID 4210 // |
| 32114 | /* 88770 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32115 | /* 88774 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32116 | /* 88778 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32117 | /* 88782 */ // MIs[1] Operand 1 |
| 32118 | /* 88782 */ // No operand predicates |
| 32119 | /* 88782 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32120 | /* 88786 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32121 | /* 88788 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32122 | /* 88788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu16), |
| 32123 | /* 88791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32124 | /* 88793 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32125 | /* 88795 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32126 | /* 88797 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32127 | /* 88800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32128 | /* 88803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32129 | /* 88809 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32130 | /* 88815 */ GIR_RootConstrainSelectedInstOperands, |
| 32131 | /* 88816 */ // GIR_Coverage, 4210, |
| 32132 | /* 88816 */ GIR_EraseRootFromParent_Done, |
| 32133 | /* 88817 */ // Label 2740: @88817 |
| 32134 | /* 88817 */ GIM_Reject, |
| 32135 | /* 88818 */ // Label 2738: @88818 |
| 32136 | /* 88818 */ GIM_Reject, |
| 32137 | /* 88819 */ // Label 2734: @88819 |
| 32138 | /* 88819 */ GIM_Try, /*On fail goto*//*Label 2741*/ GIMT_Encode4(88941), |
| 32139 | /* 88824 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 32140 | /* 88828 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32141 | /* 88832 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32142 | /* 88836 */ GIM_Try, /*On fail goto*//*Label 2742*/ GIMT_Encode4(88888), // Rule ID 4216 // |
| 32143 | /* 88841 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32144 | /* 88845 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32145 | /* 88849 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32146 | /* 88853 */ // MIs[1] Operand 1 |
| 32147 | /* 88853 */ // No operand predicates |
| 32148 | /* 88853 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32149 | /* 88857 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32150 | /* 88859 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32151 | /* 88859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16bh), |
| 32152 | /* 88862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32153 | /* 88864 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32154 | /* 88866 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32155 | /* 88868 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32156 | /* 88871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32157 | /* 88874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32158 | /* 88880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32159 | /* 88886 */ GIR_RootConstrainSelectedInstOperands, |
| 32160 | /* 88887 */ // GIR_Coverage, 4216, |
| 32161 | /* 88887 */ GIR_EraseRootFromParent_Done, |
| 32162 | /* 88888 */ // Label 2742: @88888 |
| 32163 | /* 88888 */ GIM_Try, /*On fail goto*//*Label 2743*/ GIMT_Encode4(88940), // Rule ID 4218 // |
| 32164 | /* 88893 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32165 | /* 88897 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32166 | /* 88901 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32167 | /* 88905 */ // MIs[1] Operand 1 |
| 32168 | /* 88905 */ // No operand predicates |
| 32169 | /* 88905 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32170 | /* 88909 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32171 | /* 88911 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32172 | /* 88911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16th), |
| 32173 | /* 88914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32174 | /* 88916 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32175 | /* 88918 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32176 | /* 88920 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32177 | /* 88923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32178 | /* 88926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32179 | /* 88932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32180 | /* 88938 */ GIR_RootConstrainSelectedInstOperands, |
| 32181 | /* 88939 */ // GIR_Coverage, 4218, |
| 32182 | /* 88939 */ GIR_EraseRootFromParent_Done, |
| 32183 | /* 88940 */ // Label 2743: @88940 |
| 32184 | /* 88940 */ GIM_Reject, |
| 32185 | /* 88941 */ // Label 2741: @88941 |
| 32186 | /* 88941 */ GIM_Try, /*On fail goto*//*Label 2744*/ GIMT_Encode4(89063), |
| 32187 | /* 88946 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32188 | /* 88950 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32189 | /* 88954 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32190 | /* 88958 */ GIM_Try, /*On fail goto*//*Label 2745*/ GIMT_Encode4(89010), // Rule ID 4224 // |
| 32191 | /* 88963 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32192 | /* 88967 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32193 | /* 88971 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32194 | /* 88975 */ // MIs[1] Operand 1 |
| 32195 | /* 88975 */ // No operand predicates |
| 32196 | /* 88975 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32197 | /* 88979 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32198 | /* 88981 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32199 | /* 88981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16bh), |
| 32200 | /* 88984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32201 | /* 88986 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32202 | /* 88988 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32203 | /* 88990 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32204 | /* 88993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32205 | /* 88996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32206 | /* 89002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32207 | /* 89008 */ GIR_RootConstrainSelectedInstOperands, |
| 32208 | /* 89009 */ // GIR_Coverage, 4224, |
| 32209 | /* 89009 */ GIR_EraseRootFromParent_Done, |
| 32210 | /* 89010 */ // Label 2745: @89010 |
| 32211 | /* 89010 */ GIM_Try, /*On fail goto*//*Label 2746*/ GIMT_Encode4(89062), // Rule ID 4226 // |
| 32212 | /* 89015 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32213 | /* 89019 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32214 | /* 89023 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8), |
| 32215 | /* 89027 */ // MIs[1] Operand 1 |
| 32216 | /* 89027 */ // No operand predicates |
| 32217 | /* 89027 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32218 | /* 89031 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32219 | /* 89033 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3995:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32220 | /* 89033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16th), |
| 32221 | /* 89036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32222 | /* 89038 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32223 | /* 89040 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32224 | /* 89042 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32225 | /* 89045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32226 | /* 89048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32227 | /* 89054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32228 | /* 89060 */ GIR_RootConstrainSelectedInstOperands, |
| 32229 | /* 89061 */ // GIR_Coverage, 4226, |
| 32230 | /* 89061 */ GIR_EraseRootFromParent_Done, |
| 32231 | /* 89062 */ // Label 2746: @89062 |
| 32232 | /* 89062 */ GIM_Reject, |
| 32233 | /* 89063 */ // Label 2744: @89063 |
| 32234 | /* 89063 */ GIM_Reject, |
| 32235 | /* 89064 */ // Label 2726: @89064 |
| 32236 | /* 89064 */ GIM_Reject, |
| 32237 | /* 89065 */ // Label 2710: @89065 |
| 32238 | /* 89065 */ GIM_Reject, |
| 32239 | /* 89066 */ // Label 2708: @89066 |
| 32240 | /* 89066 */ GIM_Try, /*On fail goto*//*Label 2747*/ GIMT_Encode4(90356), |
| 32241 | /* 89071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 32242 | /* 89074 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 32243 | /* 89077 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 32244 | /* 89080 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 32245 | /* 89083 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 32246 | /* 89086 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 32247 | /* 89089 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 32248 | /* 89092 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32, |
| 32249 | /* 89095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32250 | /* 89099 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32251 | /* 89103 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 32252 | /* 89107 */ GIM_Try, /*On fail goto*//*Label 2748*/ GIMT_Encode4(89609), |
| 32253 | /* 89112 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 32254 | /* 89116 */ GIM_Try, /*On fail goto*//*Label 2749*/ GIMT_Encode4(89362), |
| 32255 | /* 89121 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 32256 | /* 89125 */ GIM_Try, /*On fail goto*//*Label 2750*/ GIMT_Encode4(89243), |
| 32257 | /* 89130 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 32258 | /* 89134 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32259 | /* 89138 */ GIM_Try, /*On fail goto*//*Label 2751*/ GIMT_Encode4(89190), // Rule ID 4156 // |
| 32260 | /* 89143 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32261 | /* 89147 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32262 | /* 89151 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32263 | /* 89155 */ // MIs[1] Operand 1 |
| 32264 | /* 89155 */ // No operand predicates |
| 32265 | /* 89155 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32266 | /* 89159 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32267 | /* 89161 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32268 | /* 89161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh), |
| 32269 | /* 89164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32270 | /* 89166 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32271 | /* 89168 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32272 | /* 89170 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32273 | /* 89173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32274 | /* 89176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32275 | /* 89182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32276 | /* 89188 */ GIR_RootConstrainSelectedInstOperands, |
| 32277 | /* 89189 */ // GIR_Coverage, 4156, |
| 32278 | /* 89189 */ GIR_EraseRootFromParent_Done, |
| 32279 | /* 89190 */ // Label 2751: @89190 |
| 32280 | /* 89190 */ GIM_Try, /*On fail goto*//*Label 2752*/ GIMT_Encode4(89242), // Rule ID 4158 // |
| 32281 | /* 89195 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32282 | /* 89199 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32283 | /* 89203 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32284 | /* 89207 */ // MIs[1] Operand 1 |
| 32285 | /* 89207 */ // No operand predicates |
| 32286 | /* 89207 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32287 | /* 89211 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32288 | /* 89213 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32289 | /* 89213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th), |
| 32290 | /* 89216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32291 | /* 89218 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32292 | /* 89220 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32293 | /* 89222 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32294 | /* 89225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32295 | /* 89228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32296 | /* 89234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32297 | /* 89240 */ GIR_RootConstrainSelectedInstOperands, |
| 32298 | /* 89241 */ // GIR_Coverage, 4158, |
| 32299 | /* 89241 */ GIR_EraseRootFromParent_Done, |
| 32300 | /* 89242 */ // Label 2752: @89242 |
| 32301 | /* 89242 */ GIM_Reject, |
| 32302 | /* 89243 */ // Label 2750: @89243 |
| 32303 | /* 89243 */ GIM_Try, /*On fail goto*//*Label 2753*/ GIMT_Encode4(89361), |
| 32304 | /* 89248 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32305 | /* 89252 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32306 | /* 89256 */ GIM_Try, /*On fail goto*//*Label 2754*/ GIMT_Encode4(89308), // Rule ID 4164 // |
| 32307 | /* 89261 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32308 | /* 89265 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32309 | /* 89269 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32310 | /* 89273 */ // MIs[1] Operand 1 |
| 32311 | /* 89273 */ // No operand predicates |
| 32312 | /* 89273 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32313 | /* 89277 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32314 | /* 89279 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32315 | /* 89279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh), |
| 32316 | /* 89282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32317 | /* 89284 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32318 | /* 89286 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32319 | /* 89288 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32320 | /* 89291 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32321 | /* 89294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32322 | /* 89300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32323 | /* 89306 */ GIR_RootConstrainSelectedInstOperands, |
| 32324 | /* 89307 */ // GIR_Coverage, 4164, |
| 32325 | /* 89307 */ GIR_EraseRootFromParent_Done, |
| 32326 | /* 89308 */ // Label 2754: @89308 |
| 32327 | /* 89308 */ GIM_Try, /*On fail goto*//*Label 2755*/ GIMT_Encode4(89360), // Rule ID 4166 // |
| 32328 | /* 89313 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32329 | /* 89317 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32330 | /* 89321 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32331 | /* 89325 */ // MIs[1] Operand 1 |
| 32332 | /* 89325 */ // No operand predicates |
| 32333 | /* 89325 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32334 | /* 89329 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32335 | /* 89331 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32336 | /* 89331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th), |
| 32337 | /* 89334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32338 | /* 89336 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32339 | /* 89338 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32340 | /* 89340 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32341 | /* 89343 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32342 | /* 89346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32343 | /* 89352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32344 | /* 89358 */ GIR_RootConstrainSelectedInstOperands, |
| 32345 | /* 89359 */ // GIR_Coverage, 4166, |
| 32346 | /* 89359 */ GIR_EraseRootFromParent_Done, |
| 32347 | /* 89360 */ // Label 2755: @89360 |
| 32348 | /* 89360 */ GIM_Reject, |
| 32349 | /* 89361 */ // Label 2753: @89361 |
| 32350 | /* 89361 */ GIM_Reject, |
| 32351 | /* 89362 */ // Label 2749: @89362 |
| 32352 | /* 89362 */ GIM_Try, /*On fail goto*//*Label 2756*/ GIMT_Encode4(89608), |
| 32353 | /* 89367 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32354 | /* 89371 */ GIM_Try, /*On fail goto*//*Label 2757*/ GIMT_Encode4(89489), |
| 32355 | /* 89376 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 32356 | /* 89380 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32357 | /* 89384 */ GIM_Try, /*On fail goto*//*Label 2758*/ GIMT_Encode4(89436), // Rule ID 4172 // |
| 32358 | /* 89389 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32359 | /* 89393 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32360 | /* 89397 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32361 | /* 89401 */ // MIs[1] Operand 1 |
| 32362 | /* 89401 */ // No operand predicates |
| 32363 | /* 89401 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32364 | /* 89405 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32365 | /* 89407 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32366 | /* 89407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh), |
| 32367 | /* 89410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32368 | /* 89412 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32369 | /* 89414 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32370 | /* 89416 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32371 | /* 89419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32372 | /* 89422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32373 | /* 89428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32374 | /* 89434 */ GIR_RootConstrainSelectedInstOperands, |
| 32375 | /* 89435 */ // GIR_Coverage, 4172, |
| 32376 | /* 89435 */ GIR_EraseRootFromParent_Done, |
| 32377 | /* 89436 */ // Label 2758: @89436 |
| 32378 | /* 89436 */ GIM_Try, /*On fail goto*//*Label 2759*/ GIMT_Encode4(89488), // Rule ID 4174 // |
| 32379 | /* 89441 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32380 | /* 89445 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32381 | /* 89449 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32382 | /* 89453 */ // MIs[1] Operand 1 |
| 32383 | /* 89453 */ // No operand predicates |
| 32384 | /* 89453 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32385 | /* 89457 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32386 | /* 89459 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32387 | /* 89459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th), |
| 32388 | /* 89462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32389 | /* 89464 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32390 | /* 89466 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32391 | /* 89468 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32392 | /* 89471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32393 | /* 89474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32394 | /* 89480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32395 | /* 89486 */ GIR_RootConstrainSelectedInstOperands, |
| 32396 | /* 89487 */ // GIR_Coverage, 4174, |
| 32397 | /* 89487 */ GIR_EraseRootFromParent_Done, |
| 32398 | /* 89488 */ // Label 2759: @89488 |
| 32399 | /* 89488 */ GIM_Reject, |
| 32400 | /* 89489 */ // Label 2757: @89489 |
| 32401 | /* 89489 */ GIM_Try, /*On fail goto*//*Label 2760*/ GIMT_Encode4(89607), |
| 32402 | /* 89494 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32403 | /* 89498 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32404 | /* 89502 */ GIM_Try, /*On fail goto*//*Label 2761*/ GIMT_Encode4(89554), // Rule ID 4180 // |
| 32405 | /* 89507 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32406 | /* 89511 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32407 | /* 89515 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32408 | /* 89519 */ // MIs[1] Operand 1 |
| 32409 | /* 89519 */ // No operand predicates |
| 32410 | /* 89519 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32411 | /* 89523 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32412 | /* 89525 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32413 | /* 89525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh), |
| 32414 | /* 89528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32415 | /* 89530 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32416 | /* 89532 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32417 | /* 89534 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32418 | /* 89537 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32419 | /* 89540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32420 | /* 89546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32421 | /* 89552 */ GIR_RootConstrainSelectedInstOperands, |
| 32422 | /* 89553 */ // GIR_Coverage, 4180, |
| 32423 | /* 89553 */ GIR_EraseRootFromParent_Done, |
| 32424 | /* 89554 */ // Label 2761: @89554 |
| 32425 | /* 89554 */ GIM_Try, /*On fail goto*//*Label 2762*/ GIMT_Encode4(89606), // Rule ID 4182 // |
| 32426 | /* 89559 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32427 | /* 89563 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32428 | /* 89567 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32429 | /* 89571 */ // MIs[1] Operand 1 |
| 32430 | /* 89571 */ // No operand predicates |
| 32431 | /* 89571 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32432 | /* 89575 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32433 | /* 89577 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32434 | /* 89577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th), |
| 32435 | /* 89580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32436 | /* 89582 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32437 | /* 89584 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32438 | /* 89586 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32439 | /* 89589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32440 | /* 89592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32441 | /* 89598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32442 | /* 89604 */ GIR_RootConstrainSelectedInstOperands, |
| 32443 | /* 89605 */ // GIR_Coverage, 4182, |
| 32444 | /* 89605 */ GIR_EraseRootFromParent_Done, |
| 32445 | /* 89606 */ // Label 2762: @89606 |
| 32446 | /* 89606 */ GIM_Reject, |
| 32447 | /* 89607 */ // Label 2760: @89607 |
| 32448 | /* 89607 */ GIM_Reject, |
| 32449 | /* 89608 */ // Label 2756: @89608 |
| 32450 | /* 89608 */ GIM_Reject, |
| 32451 | /* 89609 */ // Label 2748: @89609 |
| 32452 | /* 89609 */ GIM_Try, /*On fail goto*//*Label 2763*/ GIMT_Encode4(90355), |
| 32453 | /* 89614 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 32454 | /* 89618 */ GIM_Try, /*On fail goto*//*Label 2764*/ GIMT_Encode4(89864), |
| 32455 | /* 89623 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 32456 | /* 89627 */ GIM_Try, /*On fail goto*//*Label 2765*/ GIMT_Encode4(89745), |
| 32457 | /* 89632 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 32458 | /* 89636 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32459 | /* 89640 */ GIM_Try, /*On fail goto*//*Label 2766*/ GIMT_Encode4(89692), // Rule ID 4188 // |
| 32460 | /* 89645 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32461 | /* 89649 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32462 | /* 89653 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32463 | /* 89657 */ // MIs[1] Operand 1 |
| 32464 | /* 89657 */ // No operand predicates |
| 32465 | /* 89657 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32466 | /* 89661 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32467 | /* 89663 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32468 | /* 89663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs32), |
| 32469 | /* 89666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32470 | /* 89668 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32471 | /* 89670 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32472 | /* 89672 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32473 | /* 89675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32474 | /* 89678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32475 | /* 89684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32476 | /* 89690 */ GIR_RootConstrainSelectedInstOperands, |
| 32477 | /* 89691 */ // GIR_Coverage, 4188, |
| 32478 | /* 89691 */ GIR_EraseRootFromParent_Done, |
| 32479 | /* 89692 */ // Label 2766: @89692 |
| 32480 | /* 89692 */ GIM_Try, /*On fail goto*//*Label 2767*/ GIMT_Encode4(89744), // Rule ID 4190 // |
| 32481 | /* 89697 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32482 | /* 89701 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32483 | /* 89705 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32484 | /* 89709 */ // MIs[1] Operand 1 |
| 32485 | /* 89709 */ // No operand predicates |
| 32486 | /* 89709 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32487 | /* 89713 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32488 | /* 89715 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32489 | /* 89715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths32), |
| 32490 | /* 89718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32491 | /* 89720 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32492 | /* 89722 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32493 | /* 89724 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32494 | /* 89727 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32495 | /* 89730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32496 | /* 89736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32497 | /* 89742 */ GIR_RootConstrainSelectedInstOperands, |
| 32498 | /* 89743 */ // GIR_Coverage, 4190, |
| 32499 | /* 89743 */ GIR_EraseRootFromParent_Done, |
| 32500 | /* 89744 */ // Label 2767: @89744 |
| 32501 | /* 89744 */ GIM_Reject, |
| 32502 | /* 89745 */ // Label 2765: @89745 |
| 32503 | /* 89745 */ GIM_Try, /*On fail goto*//*Label 2768*/ GIMT_Encode4(89863), |
| 32504 | /* 89750 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32505 | /* 89754 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32506 | /* 89758 */ GIM_Try, /*On fail goto*//*Label 2769*/ GIMT_Encode4(89810), // Rule ID 4196 // |
| 32507 | /* 89763 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32508 | /* 89767 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32509 | /* 89771 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32510 | /* 89775 */ // MIs[1] Operand 1 |
| 32511 | /* 89775 */ // No operand predicates |
| 32512 | /* 89775 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32513 | /* 89779 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32514 | /* 89781 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32515 | /* 89781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu32), |
| 32516 | /* 89784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32517 | /* 89786 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32518 | /* 89788 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32519 | /* 89790 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32520 | /* 89793 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32521 | /* 89796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32522 | /* 89802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32523 | /* 89808 */ GIR_RootConstrainSelectedInstOperands, |
| 32524 | /* 89809 */ // GIR_Coverage, 4196, |
| 32525 | /* 89809 */ GIR_EraseRootFromParent_Done, |
| 32526 | /* 89810 */ // Label 2769: @89810 |
| 32527 | /* 89810 */ GIM_Try, /*On fail goto*//*Label 2770*/ GIMT_Encode4(89862), // Rule ID 4198 // |
| 32528 | /* 89815 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32529 | /* 89819 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32530 | /* 89823 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32531 | /* 89827 */ // MIs[1] Operand 1 |
| 32532 | /* 89827 */ // No operand predicates |
| 32533 | /* 89827 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32534 | /* 89831 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32535 | /* 89833 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32536 | /* 89833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu32), |
| 32537 | /* 89836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32538 | /* 89838 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32539 | /* 89840 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32540 | /* 89842 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32541 | /* 89845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32542 | /* 89848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32543 | /* 89854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32544 | /* 89860 */ GIR_RootConstrainSelectedInstOperands, |
| 32545 | /* 89861 */ // GIR_Coverage, 4198, |
| 32546 | /* 89861 */ GIR_EraseRootFromParent_Done, |
| 32547 | /* 89862 */ // Label 2770: @89862 |
| 32548 | /* 89862 */ GIM_Reject, |
| 32549 | /* 89863 */ // Label 2768: @89863 |
| 32550 | /* 89863 */ GIM_Reject, |
| 32551 | /* 89864 */ // Label 2764: @89864 |
| 32552 | /* 89864 */ GIM_Try, /*On fail goto*//*Label 2771*/ GIMT_Encode4(90110), |
| 32553 | /* 89869 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32554 | /* 89873 */ GIM_Try, /*On fail goto*//*Label 2772*/ GIMT_Encode4(89991), |
| 32555 | /* 89878 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0, |
| 32556 | /* 89882 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32557 | /* 89886 */ GIM_Try, /*On fail goto*//*Label 2773*/ GIMT_Encode4(89938), // Rule ID 4204 // |
| 32558 | /* 89891 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32559 | /* 89895 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32560 | /* 89899 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32561 | /* 89903 */ // MIs[1] Operand 1 |
| 32562 | /* 89903 */ // No operand predicates |
| 32563 | /* 89903 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32564 | /* 89907 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32565 | /* 89909 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32566 | /* 89909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs32), |
| 32567 | /* 89912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32568 | /* 89914 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32569 | /* 89916 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32570 | /* 89918 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32571 | /* 89921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32572 | /* 89924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32573 | /* 89930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32574 | /* 89936 */ GIR_RootConstrainSelectedInstOperands, |
| 32575 | /* 89937 */ // GIR_Coverage, 4204, |
| 32576 | /* 89937 */ GIR_EraseRootFromParent_Done, |
| 32577 | /* 89938 */ // Label 2773: @89938 |
| 32578 | /* 89938 */ GIM_Try, /*On fail goto*//*Label 2774*/ GIMT_Encode4(89990), // Rule ID 4206 // |
| 32579 | /* 89943 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32580 | /* 89947 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32581 | /* 89951 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32582 | /* 89955 */ // MIs[1] Operand 1 |
| 32583 | /* 89955 */ // No operand predicates |
| 32584 | /* 89955 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32585 | /* 89959 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32586 | /* 89961 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32587 | /* 89961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths32), |
| 32588 | /* 89964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32589 | /* 89966 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32590 | /* 89968 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32591 | /* 89970 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32592 | /* 89973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32593 | /* 89976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32594 | /* 89982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32595 | /* 89988 */ GIR_RootConstrainSelectedInstOperands, |
| 32596 | /* 89989 */ // GIR_Coverage, 4206, |
| 32597 | /* 89989 */ GIR_EraseRootFromParent_Done, |
| 32598 | /* 89990 */ // Label 2774: @89990 |
| 32599 | /* 89990 */ GIM_Reject, |
| 32600 | /* 89991 */ // Label 2772: @89991 |
| 32601 | /* 89991 */ GIM_Try, /*On fail goto*//*Label 2775*/ GIMT_Encode4(90109), |
| 32602 | /* 89996 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32603 | /* 90000 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1, |
| 32604 | /* 90004 */ GIM_Try, /*On fail goto*//*Label 2776*/ GIMT_Encode4(90056), // Rule ID 4212 // |
| 32605 | /* 90009 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32606 | /* 90013 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32607 | /* 90017 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32608 | /* 90021 */ // MIs[1] Operand 1 |
| 32609 | /* 90021 */ // No operand predicates |
| 32610 | /* 90021 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32611 | /* 90025 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32612 | /* 90027 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32613 | /* 90027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu32), |
| 32614 | /* 90030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32615 | /* 90032 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32616 | /* 90034 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32617 | /* 90036 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32618 | /* 90039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32619 | /* 90042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32620 | /* 90048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32621 | /* 90054 */ GIR_RootConstrainSelectedInstOperands, |
| 32622 | /* 90055 */ // GIR_Coverage, 4212, |
| 32623 | /* 90055 */ GIR_EraseRootFromParent_Done, |
| 32624 | /* 90056 */ // Label 2776: @90056 |
| 32625 | /* 90056 */ GIM_Try, /*On fail goto*//*Label 2777*/ GIMT_Encode4(90108), // Rule ID 4214 // |
| 32626 | /* 90061 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32627 | /* 90065 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32628 | /* 90069 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32629 | /* 90073 */ // MIs[1] Operand 1 |
| 32630 | /* 90073 */ // No operand predicates |
| 32631 | /* 90073 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32632 | /* 90077 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32633 | /* 90079 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32634 | /* 90079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu32), |
| 32635 | /* 90082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32636 | /* 90084 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32637 | /* 90086 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32638 | /* 90088 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32639 | /* 90091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32640 | /* 90094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32641 | /* 90100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32642 | /* 90106 */ GIR_RootConstrainSelectedInstOperands, |
| 32643 | /* 90107 */ // GIR_Coverage, 4214, |
| 32644 | /* 90107 */ GIR_EraseRootFromParent_Done, |
| 32645 | /* 90108 */ // Label 2777: @90108 |
| 32646 | /* 90108 */ GIM_Reject, |
| 32647 | /* 90109 */ // Label 2775: @90109 |
| 32648 | /* 90109 */ GIM_Reject, |
| 32649 | /* 90110 */ // Label 2771: @90110 |
| 32650 | /* 90110 */ GIM_Try, /*On fail goto*//*Label 2778*/ GIMT_Encode4(90232), |
| 32651 | /* 90115 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 32652 | /* 90119 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32653 | /* 90123 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32654 | /* 90127 */ GIM_Try, /*On fail goto*//*Label 2779*/ GIMT_Encode4(90179), // Rule ID 4220 // |
| 32655 | /* 90132 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32656 | /* 90136 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32657 | /* 90140 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32658 | /* 90144 */ // MIs[1] Operand 1 |
| 32659 | /* 90144 */ // No operand predicates |
| 32660 | /* 90144 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32661 | /* 90148 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32662 | /* 90150 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32663 | /* 90150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32bh), |
| 32664 | /* 90153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32665 | /* 90155 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32666 | /* 90157 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32667 | /* 90159 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32668 | /* 90162 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32669 | /* 90165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32670 | /* 90171 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32671 | /* 90177 */ GIR_RootConstrainSelectedInstOperands, |
| 32672 | /* 90178 */ // GIR_Coverage, 4220, |
| 32673 | /* 90178 */ GIR_EraseRootFromParent_Done, |
| 32674 | /* 90179 */ // Label 2779: @90179 |
| 32675 | /* 90179 */ GIM_Try, /*On fail goto*//*Label 2780*/ GIMT_Encode4(90231), // Rule ID 4222 // |
| 32676 | /* 90184 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32677 | /* 90188 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32678 | /* 90192 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32679 | /* 90196 */ // MIs[1] Operand 1 |
| 32680 | /* 90196 */ // No operand predicates |
| 32681 | /* 90196 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32682 | /* 90200 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32683 | /* 90202 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32684 | /* 90202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32th), |
| 32685 | /* 90205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32686 | /* 90207 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32687 | /* 90209 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32688 | /* 90211 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32689 | /* 90214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32690 | /* 90217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32691 | /* 90223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32692 | /* 90229 */ GIR_RootConstrainSelectedInstOperands, |
| 32693 | /* 90230 */ // GIR_Coverage, 4222, |
| 32694 | /* 90230 */ GIR_EraseRootFromParent_Done, |
| 32695 | /* 90231 */ // Label 2780: @90231 |
| 32696 | /* 90231 */ GIM_Reject, |
| 32697 | /* 90232 */ // Label 2778: @90232 |
| 32698 | /* 90232 */ GIM_Try, /*On fail goto*//*Label 2781*/ GIMT_Encode4(90354), |
| 32699 | /* 90237 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 32700 | /* 90241 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1, |
| 32701 | /* 90245 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0, |
| 32702 | /* 90249 */ GIM_Try, /*On fail goto*//*Label 2782*/ GIMT_Encode4(90301), // Rule ID 4228 // |
| 32703 | /* 90254 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32704 | /* 90258 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32705 | /* 90262 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32706 | /* 90266 */ // MIs[1] Operand 1 |
| 32707 | /* 90266 */ // No operand predicates |
| 32708 | /* 90266 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0, |
| 32709 | /* 90270 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32710 | /* 90272 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32711 | /* 90272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32bh), |
| 32712 | /* 90275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32713 | /* 90277 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32714 | /* 90279 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32715 | /* 90281 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32716 | /* 90284 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32717 | /* 90287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32718 | /* 90293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32719 | /* 90299 */ GIR_RootConstrainSelectedInstOperands, |
| 32720 | /* 90300 */ // GIR_Coverage, 4228, |
| 32721 | /* 90300 */ GIR_EraseRootFromParent_Done, |
| 32722 | /* 90301 */ // Label 2782: @90301 |
| 32723 | /* 90301 */ GIM_Try, /*On fail goto*//*Label 2783*/ GIMT_Encode4(90353), // Rule ID 4230 // |
| 32724 | /* 90306 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1] |
| 32725 | /* 90310 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32726 | /* 90314 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16), |
| 32727 | /* 90318 */ // MIs[1] Operand 1 |
| 32728 | /* 90318 */ // No operand predicates |
| 32729 | /* 90318 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1, |
| 32730 | /* 90322 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32731 | /* 90324 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3995:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm) |
| 32732 | /* 90324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32th), |
| 32733 | /* 90327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 32734 | /* 90329 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc |
| 32735 | /* 90331 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm |
| 32736 | /* 90333 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32737 | /* 90336 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32738 | /* 90339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32739 | /* 90345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32740 | /* 90351 */ GIR_RootConstrainSelectedInstOperands, |
| 32741 | /* 90352 */ // GIR_Coverage, 4230, |
| 32742 | /* 90352 */ GIR_EraseRootFromParent_Done, |
| 32743 | /* 90353 */ // Label 2783: @90353 |
| 32744 | /* 90353 */ GIM_Reject, |
| 32745 | /* 90354 */ // Label 2781: @90354 |
| 32746 | /* 90354 */ GIM_Reject, |
| 32747 | /* 90355 */ // Label 2763: @90355 |
| 32748 | /* 90355 */ GIM_Reject, |
| 32749 | /* 90356 */ // Label 2747: @90356 |
| 32750 | /* 90356 */ GIM_Reject, |
| 32751 | /* 90357 */ // Label 2709: @90357 |
| 32752 | /* 90357 */ GIM_Reject, |
| 32753 | /* 90358 */ // Label 2706: @90358 |
| 32754 | /* 90358 */ GIM_Reject, |
| 32755 | /* 90359 */ // Label 22: @90359 |
| 32756 | /* 90359 */ GIM_Try, /*On fail goto*//*Label 2784*/ GIMT_Encode4(90414), |
| 32757 | /* 90364 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, |
| 32758 | /* 90367 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_clrex), |
| 32759 | /* 90372 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2785*/ GIMT_Encode4(90388), GIMT_Encode2(GIFBS_HasV6K_IsARM), // Rule ID 244 // |
| 32760 | /* 90379 */ // (intrinsic_void 3762:{ *:[iPTR] }) => (CLREX) |
| 32761 | /* 90379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLREX), |
| 32762 | /* 90382 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32763 | /* 90386 */ GIR_RootConstrainSelectedInstOperands, |
| 32764 | /* 90387 */ // GIR_Coverage, 244, |
| 32765 | /* 90387 */ GIR_EraseRootFromParent_Done, |
| 32766 | /* 90388 */ // Label 2785: @90388 |
| 32767 | /* 90388 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2786*/ GIMT_Encode4(90413), GIMT_Encode2(GIFBS_HasV7Clrex_IsThumb), // Rule ID 573 // |
| 32768 | /* 90395 */ // (intrinsic_void 3762:{ *:[iPTR] }) => (t2CLREX) |
| 32769 | /* 90395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLREX), |
| 32770 | /* 90398 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32771 | /* 90401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32772 | /* 90407 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32773 | /* 90411 */ GIR_RootConstrainSelectedInstOperands, |
| 32774 | /* 90412 */ // GIR_Coverage, 573, |
| 32775 | /* 90412 */ GIR_EraseRootFromParent_Done, |
| 32776 | /* 90413 */ // Label 2786: @90413 |
| 32777 | /* 90413 */ GIM_Reject, |
| 32778 | /* 90414 */ // Label 2784: @90414 |
| 32779 | /* 90414 */ GIM_Try, /*On fail goto*//*Label 2787*/ GIMT_Encode4(91197), |
| 32780 | /* 90419 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, |
| 32781 | /* 90422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2788*/ GIMT_Encode4(90457), GIMT_Encode2(GIFBS_IsThumb_IsWindows), // Rule ID 343 // |
| 32782 | /* 90429 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 32783 | /* 90434 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32784 | /* 90437 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/1, GIMT_Encode8(249), |
| 32785 | /* 90448 */ // (intrinsic_void 4216:{ *:[iPTR] }, 249:{ *:[i32] }) => (t__brkdiv0) |
| 32786 | /* 90448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t__brkdiv0), |
| 32787 | /* 90451 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32788 | /* 90455 */ GIR_RootConstrainSelectedInstOperands, |
| 32789 | /* 90456 */ // GIR_Coverage, 343, |
| 32790 | /* 90456 */ GIR_EraseRootFromParent_Done, |
| 32791 | /* 90457 */ // Label 2788: @90457 |
| 32792 | /* 90457 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2789*/ GIMT_Encode4(90508), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2 // |
| 32793 | /* 90464 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint), |
| 32794 | /* 90469 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32795 | /* 90472 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32796 | /* 90476 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32797 | /* 90480 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239), |
| 32798 | /* 90484 */ // MIs[1] Operand 1 |
| 32799 | /* 90484 */ // No operand predicates |
| 32800 | /* 90484 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32801 | /* 90486 */ // (intrinsic_void 3780:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (HINT (imm:{ *:[i32] }):$imm) |
| 32802 | /* 90486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::HINT), |
| 32803 | /* 90489 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32804 | /* 90492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32805 | /* 90495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32806 | /* 90501 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32807 | /* 90506 */ GIR_RootConstrainSelectedInstOperands, |
| 32808 | /* 90507 */ // GIR_Coverage, 2, |
| 32809 | /* 90507 */ GIR_EraseRootFromParent_Done, |
| 32810 | /* 90508 */ // Label 2789: @90508 |
| 32811 | /* 90508 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2790*/ GIMT_Encode4(90559), GIMT_Encode2(GIFBS_HasV7_IsARM), // Rule ID 10 // |
| 32812 | /* 90515 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg), |
| 32813 | /* 90520 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32814 | /* 90523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32815 | /* 90527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32816 | /* 90531 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32817 | /* 90535 */ // MIs[1] Operand 1 |
| 32818 | /* 90535 */ // No operand predicates |
| 32819 | /* 90535 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32820 | /* 90537 */ // (intrinsic_void 3775:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DBG (imm:{ *:[i32] }):$opt) |
| 32821 | /* 90537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DBG), |
| 32822 | /* 90540 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32823 | /* 90543 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32824 | /* 90546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32825 | /* 90552 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32826 | /* 90557 */ GIR_RootConstrainSelectedInstOperands, |
| 32827 | /* 90558 */ // GIR_Coverage, 10, |
| 32828 | /* 90558 */ GIR_EraseRootFromParent_Done, |
| 32829 | /* 90559 */ // Label 2790: @90559 |
| 32830 | /* 90559 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2791*/ GIMT_Encode4(90601), GIMT_Encode2(GIFBS_IsARM), // Rule ID 11 // |
| 32831 | /* 90566 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 32832 | /* 90571 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32833 | /* 90574 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32834 | /* 90578 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32835 | /* 90582 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 32836 | /* 90586 */ // MIs[1] Operand 1 |
| 32837 | /* 90586 */ // No operand predicates |
| 32838 | /* 90586 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32839 | /* 90588 */ // (intrinsic_void 4216:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (UDF (imm:{ *:[i32] }):$imm16) |
| 32840 | /* 90588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF), |
| 32841 | /* 90591 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
| 32842 | /* 90594 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32843 | /* 90599 */ GIR_RootConstrainSelectedInstOperands, |
| 32844 | /* 90600 */ // GIR_Coverage, 11, |
| 32845 | /* 90600 */ GIR_EraseRootFromParent_Done, |
| 32846 | /* 90601 */ // Label 2791: @90601 |
| 32847 | /* 90601 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2792*/ GIMT_Encode4(90643), GIMT_Encode2(GIFBS_HasDB_IsARM), // Rule ID 227 // |
| 32848 | /* 90608 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb), |
| 32849 | /* 90613 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32850 | /* 90616 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32851 | /* 90620 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32852 | /* 90624 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32853 | /* 90628 */ // MIs[1] Operand 1 |
| 32854 | /* 90628 */ // No operand predicates |
| 32855 | /* 90628 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32856 | /* 90630 */ // (intrinsic_void 3776:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DMB (imm:{ *:[i32] }):$opt) |
| 32857 | /* 90630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DMB), |
| 32858 | /* 90633 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32859 | /* 90636 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32860 | /* 90641 */ GIR_RootConstrainSelectedInstOperands, |
| 32861 | /* 90642 */ // GIR_Coverage, 227, |
| 32862 | /* 90642 */ GIR_EraseRootFromParent_Done, |
| 32863 | /* 90643 */ // Label 2792: @90643 |
| 32864 | /* 90643 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2793*/ GIMT_Encode4(90685), GIMT_Encode2(GIFBS_HasDB_IsARM), // Rule ID 228 // |
| 32865 | /* 90650 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb), |
| 32866 | /* 90655 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32867 | /* 90658 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32868 | /* 90662 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32869 | /* 90666 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32870 | /* 90670 */ // MIs[1] Operand 1 |
| 32871 | /* 90670 */ // No operand predicates |
| 32872 | /* 90670 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32873 | /* 90672 */ // (intrinsic_void 3777:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DSB (imm:{ *:[i32] }):$opt) |
| 32874 | /* 90672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DSB), |
| 32875 | /* 90675 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32876 | /* 90678 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32877 | /* 90683 */ GIR_RootConstrainSelectedInstOperands, |
| 32878 | /* 90684 */ // GIR_Coverage, 228, |
| 32879 | /* 90684 */ GIR_EraseRootFromParent_Done, |
| 32880 | /* 90685 */ // Label 2793: @90685 |
| 32881 | /* 90685 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2794*/ GIMT_Encode4(90727), GIMT_Encode2(GIFBS_HasDB_IsARM), // Rule ID 229 // |
| 32882 | /* 90692 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb), |
| 32883 | /* 90697 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32884 | /* 90700 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32885 | /* 90704 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32886 | /* 90708 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32887 | /* 90712 */ // MIs[1] Operand 1 |
| 32888 | /* 90712 */ // No operand predicates |
| 32889 | /* 90712 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32890 | /* 90714 */ // (intrinsic_void 3781:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (ISB (imm:{ *:[i32] }):$opt) |
| 32891 | /* 90714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ISB), |
| 32892 | /* 90717 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32893 | /* 90720 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32894 | /* 90725 */ GIR_RootConstrainSelectedInstOperands, |
| 32895 | /* 90726 */ // GIR_Coverage, 229, |
| 32896 | /* 90726 */ GIR_EraseRootFromParent_Done, |
| 32897 | /* 90727 */ // Label 2794: @90727 |
| 32898 | /* 90727 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2795*/ GIMT_Encode4(90778), GIMT_Encode2(GIFBS_HasV6M_IsThumb), // Rule ID 275 // |
| 32899 | /* 90734 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint), |
| 32900 | /* 90739 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32901 | /* 90742 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32902 | /* 90746 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32903 | /* 90750 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32904 | /* 90754 */ // MIs[1] Operand 1 |
| 32905 | /* 90754 */ // No operand predicates |
| 32906 | /* 90754 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32907 | /* 90756 */ // (intrinsic_void 3780:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (tHINT (imm:{ *:[i32] }):$imm) |
| 32908 | /* 90756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tHINT), |
| 32909 | /* 90759 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 32910 | /* 90762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32911 | /* 90765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32912 | /* 90771 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32913 | /* 90776 */ GIR_RootConstrainSelectedInstOperands, |
| 32914 | /* 90777 */ // GIR_Coverage, 275, |
| 32915 | /* 90777 */ GIR_EraseRootFromParent_Done, |
| 32916 | /* 90778 */ // Label 2795: @90778 |
| 32917 | /* 90778 */ GIM_Try, /*On fail goto*//*Label 2796*/ GIMT_Encode4(90860), |
| 32918 | /* 90783 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined), |
| 32919 | /* 90788 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32920 | /* 90791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2797*/ GIMT_Encode4(90825), GIMT_Encode2(GIFBS_IsThumb), // Rule ID 342 // |
| 32921 | /* 90798 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32922 | /* 90802 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32923 | /* 90806 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255), |
| 32924 | /* 90810 */ // MIs[1] Operand 1 |
| 32925 | /* 90810 */ // No operand predicates |
| 32926 | /* 90810 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32927 | /* 90812 */ // (intrinsic_void 4216:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$imm8) => (tUDF (imm:{ *:[i32] }):$imm8) |
| 32928 | /* 90812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF), |
| 32929 | /* 90815 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8 |
| 32930 | /* 90818 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32931 | /* 90823 */ GIR_RootConstrainSelectedInstOperands, |
| 32932 | /* 90824 */ // GIR_Coverage, 342, |
| 32933 | /* 90824 */ GIR_EraseRootFromParent_Done, |
| 32934 | /* 90825 */ // Label 2797: @90825 |
| 32935 | /* 90825 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2798*/ GIMT_Encode4(90859), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 493 // |
| 32936 | /* 90832 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32937 | /* 90836 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32938 | /* 90840 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 32939 | /* 90844 */ // MIs[1] Operand 1 |
| 32940 | /* 90844 */ // No operand predicates |
| 32941 | /* 90844 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32942 | /* 90846 */ // (intrinsic_void 4216:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (t2UDF (imm:{ *:[i32] }):$imm16) |
| 32943 | /* 90846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDF), |
| 32944 | /* 90849 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16 |
| 32945 | /* 90852 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32946 | /* 90857 */ GIR_RootConstrainSelectedInstOperands, |
| 32947 | /* 90858 */ // GIR_Coverage, 493, |
| 32948 | /* 90858 */ GIR_EraseRootFromParent_Done, |
| 32949 | /* 90859 */ // Label 2798: @90859 |
| 32950 | /* 90859 */ GIM_Reject, |
| 32951 | /* 90860 */ // Label 2796: @90860 |
| 32952 | /* 90860 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2799*/ GIMT_Encode4(90911), GIMT_Encode2(GIFBS_HasDB_IsThumb), // Rule ID 558 // |
| 32953 | /* 90867 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb), |
| 32954 | /* 90872 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32955 | /* 90875 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32956 | /* 90879 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32957 | /* 90883 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32958 | /* 90887 */ // MIs[1] Operand 1 |
| 32959 | /* 90887 */ // No operand predicates |
| 32960 | /* 90887 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32961 | /* 90889 */ // (intrinsic_void 3776:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DMB (imm:{ *:[i32] }):$opt) |
| 32962 | /* 90889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DMB), |
| 32963 | /* 90892 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32964 | /* 90895 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32965 | /* 90898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32966 | /* 90904 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32967 | /* 90909 */ GIR_RootConstrainSelectedInstOperands, |
| 32968 | /* 90910 */ // GIR_Coverage, 558, |
| 32969 | /* 90910 */ GIR_EraseRootFromParent_Done, |
| 32970 | /* 90911 */ // Label 2799: @90911 |
| 32971 | /* 90911 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2800*/ GIMT_Encode4(90962), GIMT_Encode2(GIFBS_HasDB_IsThumb), // Rule ID 559 // |
| 32972 | /* 90918 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb), |
| 32973 | /* 90923 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32974 | /* 90926 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32975 | /* 90930 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32976 | /* 90934 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32977 | /* 90938 */ // MIs[1] Operand 1 |
| 32978 | /* 90938 */ // No operand predicates |
| 32979 | /* 90938 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32980 | /* 90940 */ // (intrinsic_void 3777:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DSB (imm:{ *:[i32] }):$opt) |
| 32981 | /* 90940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DSB), |
| 32982 | /* 90943 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 32983 | /* 90946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 32984 | /* 90949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 32985 | /* 90955 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 32986 | /* 90960 */ GIR_RootConstrainSelectedInstOperands, |
| 32987 | /* 90961 */ // GIR_Coverage, 559, |
| 32988 | /* 90961 */ GIR_EraseRootFromParent_Done, |
| 32989 | /* 90962 */ // Label 2800: @90962 |
| 32990 | /* 90962 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2801*/ GIMT_Encode4(91013), GIMT_Encode2(GIFBS_HasDB_IsThumb), // Rule ID 560 // |
| 32991 | /* 90969 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb), |
| 32992 | /* 90974 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 32993 | /* 90977 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 32994 | /* 90981 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 32995 | /* 90985 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 32996 | /* 90989 */ // MIs[1] Operand 1 |
| 32997 | /* 90989 */ // No operand predicates |
| 32998 | /* 90989 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 32999 | /* 90991 */ // (intrinsic_void 3781:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2ISB (imm:{ *:[i32] }):$opt) |
| 33000 | /* 90991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ISB), |
| 33001 | /* 90994 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 33002 | /* 90997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33003 | /* 91000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33004 | /* 91006 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33005 | /* 91011 */ GIR_RootConstrainSelectedInstOperands, |
| 33006 | /* 91012 */ // GIR_Coverage, 560, |
| 33007 | /* 91012 */ GIR_EraseRootFromParent_Done, |
| 33008 | /* 91013 */ // Label 2801: @91013 |
| 33009 | /* 91013 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2802*/ GIMT_Encode4(91064), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 578 // |
| 33010 | /* 91020 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint), |
| 33011 | /* 91025 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 33012 | /* 91028 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 33013 | /* 91032 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33014 | /* 91036 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239), |
| 33015 | /* 91040 */ // MIs[1] Operand 1 |
| 33016 | /* 91040 */ // No operand predicates |
| 33017 | /* 91040 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33018 | /* 91042 */ // (intrinsic_void 3780:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (t2HINT (imm:{ *:[i32] }):$imm) |
| 33019 | /* 91042 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2HINT), |
| 33020 | /* 91045 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 33021 | /* 91048 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33022 | /* 91051 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33023 | /* 91057 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33024 | /* 91062 */ GIR_RootConstrainSelectedInstOperands, |
| 33025 | /* 91063 */ // GIR_Coverage, 578, |
| 33026 | /* 91063 */ GIR_EraseRootFromParent_Done, |
| 33027 | /* 91064 */ // Label 2802: @91064 |
| 33028 | /* 91064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2803*/ GIMT_Encode4(91115), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 579 // |
| 33029 | /* 91071 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg), |
| 33030 | /* 91076 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 33031 | /* 91079 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 33032 | /* 91083 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33033 | /* 91087 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15), |
| 33034 | /* 91091 */ // MIs[1] Operand 1 |
| 33035 | /* 91091 */ // No operand predicates |
| 33036 | /* 91091 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33037 | /* 91093 */ // (intrinsic_void 3775:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DBG (imm:{ *:[i32] }):$opt) |
| 33038 | /* 91093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DBG), |
| 33039 | /* 91096 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt |
| 33040 | /* 91099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33041 | /* 91102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33042 | /* 91108 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33043 | /* 91113 */ GIR_RootConstrainSelectedInstOperands, |
| 33044 | /* 91114 */ // GIR_Coverage, 579, |
| 33045 | /* 91114 */ GIR_EraseRootFromParent_Done, |
| 33046 | /* 91115 */ // Label 2803: @91115 |
| 33047 | /* 91115 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2804*/ GIMT_Encode4(91154), GIMT_Encode2(GIFBS_HasFPRegs), // Rule ID 845 // |
| 33048 | /* 91122 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_get_fpscr), |
| 33049 | /* 91127 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33050 | /* 91130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33051 | /* 91134 */ // (intrinsic_w_chain:{ *:[i32] } 3778:{ *:[iPTR] }) => (VMRS:{ *:[i32] }) |
| 33052 | /* 91134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS), |
| 33053 | /* 91137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 33054 | /* 91139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33055 | /* 91142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33056 | /* 91148 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33057 | /* 91152 */ GIR_RootConstrainSelectedInstOperands, |
| 33058 | /* 91153 */ // GIR_Coverage, 845, |
| 33059 | /* 91153 */ GIR_EraseRootFromParent_Done, |
| 33060 | /* 91154 */ // Label 2804: @91154 |
| 33061 | /* 91154 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2805*/ GIMT_Encode4(91196), GIMT_Encode2(GIFBS_HasFPRegs), // Rule ID 846 // |
| 33062 | /* 91161 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_set_fpscr), |
| 33063 | /* 91166 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 33064 | /* 91169 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33065 | /* 91173 */ // (intrinsic_void 4160:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt) |
| 33066 | /* 91173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 33067 | /* 91176 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt |
| 33068 | /* 91178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33069 | /* 91181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33070 | /* 91187 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 33071 | /* 91190 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33072 | /* 91194 */ GIR_RootConstrainSelectedInstOperands, |
| 33073 | /* 91195 */ // GIR_Coverage, 846, |
| 33074 | /* 91195 */ GIR_EraseRootFromParent_Done, |
| 33075 | /* 91196 */ // Label 2805: @91196 |
| 33076 | /* 91196 */ GIM_Reject, |
| 33077 | /* 91197 */ // Label 2787: @91197 |
| 33078 | /* 91197 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2806*/ GIMT_Encode4(91239), GIMT_Encode2(GIFBS_HasLOB_HasV8_1MMainline_IsThumb2), // Rule ID 603 // |
| 33079 | /* 91204 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 33080 | /* 91207 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::start_loop_iterations), |
| 33081 | /* 91212 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33082 | /* 91215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33083 | /* 91218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRlrRegClassID), |
| 33084 | /* 91222 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33085 | /* 91226 */ // (intrinsic_w_chain:{ *:[i32] } 368:{ *:[iPTR] }, rGPR:{ *:[i32] }:$tc) => (t2DoLoopStart:{ *:[i32] } rGPR:{ *:[i32] }:$tc) |
| 33086 | /* 91226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DoLoopStart), |
| 33087 | /* 91229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[X] |
| 33088 | /* 91231 */ GIR_RootToRootCopy, /*OpIdx*/2, // tc |
| 33089 | /* 91233 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33090 | /* 91237 */ GIR_RootConstrainSelectedInstOperands, |
| 33091 | /* 91238 */ // GIR_Coverage, 603, |
| 33092 | /* 91238 */ GIR_EraseRootFromParent_Done, |
| 33093 | /* 91239 */ // Label 2806: @91239 |
| 33094 | /* 91239 */ GIM_Try, /*On fail goto*//*Label 2807*/ GIMT_Encode4(93172), |
| 33095 | /* 91244 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 33096 | /* 91247 */ GIM_Try, /*On fail goto*//*Label 2808*/ GIMT_Encode4(91447), |
| 33097 | /* 91252 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base), |
| 33098 | /* 91257 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2811*/ GIMT_Encode4(91446), |
| 33099 | /* 91268 */ /*GILLT_v4s32*//*Label 2809*/ GIMT_Encode4(91276), |
| 33100 | /* 91272 */ /*GILLT_v2s64*//*Label 2810*/ GIMT_Encode4(91361), |
| 33101 | /* 91276 */ // Label 2809: @91276 |
| 33102 | /* 91276 */ GIM_Try, /*On fail goto*//*Label 2812*/ GIMT_Encode4(91360), |
| 33103 | /* 91281 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33104 | /* 91284 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33105 | /* 91287 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33106 | /* 91291 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33107 | /* 91295 */ GIM_Try, /*On fail goto*//*Label 2813*/ GIMT_Encode4(91327), // Rule ID 5577 // |
| 33108 | /* 91300 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33109 | /* 91304 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33110 | /* 91308 */ // MIs[1] Operand 1 |
| 33111 | /* 91308 */ // No operand predicates |
| 33112 | /* 91308 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33113 | /* 91310 */ // (intrinsic_w_chain:{ *:[v4i32] } 3921:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33114 | /* 91310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi), |
| 33115 | /* 91313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33116 | /* 91315 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33117 | /* 91317 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33118 | /* 91320 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33119 | /* 91325 */ GIR_RootConstrainSelectedInstOperands, |
| 33120 | /* 91326 */ // GIR_Coverage, 5577, |
| 33121 | /* 91326 */ GIR_EraseRootFromParent_Done, |
| 33122 | /* 91327 */ // Label 2813: @91327 |
| 33123 | /* 91327 */ GIM_Try, /*On fail goto*//*Label 2814*/ GIMT_Encode4(91359), // Rule ID 5583 // |
| 33124 | /* 91332 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33125 | /* 91336 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33126 | /* 91340 */ // MIs[1] Operand 1 |
| 33127 | /* 91340 */ // No operand predicates |
| 33128 | /* 91340 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33129 | /* 91342 */ // (intrinsic_w_chain:{ *:[v4f32] } 3921:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33130 | /* 91342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi), |
| 33131 | /* 91345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33132 | /* 91347 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33133 | /* 91349 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33134 | /* 91352 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33135 | /* 91357 */ GIR_RootConstrainSelectedInstOperands, |
| 33136 | /* 91358 */ // GIR_Coverage, 5583, |
| 33137 | /* 91358 */ GIR_EraseRootFromParent_Done, |
| 33138 | /* 91359 */ // Label 2814: @91359 |
| 33139 | /* 91359 */ GIM_Reject, |
| 33140 | /* 91360 */ // Label 2812: @91360 |
| 33141 | /* 91360 */ GIM_Reject, |
| 33142 | /* 91361 */ // Label 2810: @91361 |
| 33143 | /* 91361 */ GIM_Try, /*On fail goto*//*Label 2815*/ GIMT_Encode4(91445), |
| 33144 | /* 91366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 33145 | /* 91369 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33146 | /* 91372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33147 | /* 91376 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33148 | /* 91380 */ GIM_Try, /*On fail goto*//*Label 2816*/ GIMT_Encode4(91412), // Rule ID 5585 // |
| 33149 | /* 91385 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33150 | /* 91389 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33151 | /* 91393 */ // MIs[1] Operand 1 |
| 33152 | /* 91393 */ // No operand predicates |
| 33153 | /* 91393 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33154 | /* 91395 */ // (intrinsic_w_chain:{ *:[v2i64] } 3921:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33155 | /* 91395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi), |
| 33156 | /* 91398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33157 | /* 91400 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33158 | /* 91402 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33159 | /* 91405 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33160 | /* 91410 */ GIR_RootConstrainSelectedInstOperands, |
| 33161 | /* 91411 */ // GIR_Coverage, 5585, |
| 33162 | /* 91411 */ GIR_EraseRootFromParent_Done, |
| 33163 | /* 91412 */ // Label 2816: @91412 |
| 33164 | /* 91412 */ GIM_Try, /*On fail goto*//*Label 2817*/ GIMT_Encode4(91444), // Rule ID 5587 // |
| 33165 | /* 91417 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33166 | /* 91421 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33167 | /* 91425 */ // MIs[1] Operand 1 |
| 33168 | /* 91425 */ // No operand predicates |
| 33169 | /* 91425 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33170 | /* 91427 */ // (intrinsic_w_chain:{ *:[v2f64] } 3921:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33171 | /* 91427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi), |
| 33172 | /* 91430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 33173 | /* 91432 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33174 | /* 91434 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33175 | /* 91437 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33176 | /* 91442 */ GIR_RootConstrainSelectedInstOperands, |
| 33177 | /* 91443 */ // GIR_Coverage, 5587, |
| 33178 | /* 91443 */ GIR_EraseRootFromParent_Done, |
| 33179 | /* 91444 */ // Label 2817: @91444 |
| 33180 | /* 91444 */ GIM_Reject, |
| 33181 | /* 91445 */ // Label 2815: @91445 |
| 33182 | /* 91445 */ GIM_Reject, |
| 33183 | /* 91446 */ // Label 2811: @91446 |
| 33184 | /* 91446 */ GIM_Reject, |
| 33185 | /* 91447 */ // Label 2808: @91447 |
| 33186 | /* 91447 */ GIM_Try, /*On fail goto*//*Label 2818*/ GIMT_Encode4(91489), // Rule ID 1927 // |
| 33187 | /* 91452 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_space), |
| 33188 | /* 91457 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33189 | /* 91460 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33190 | /* 91463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33191 | /* 91467 */ // MIs[0] size |
| 33192 | /* 91467 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 33193 | /* 91470 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33194 | /* 91474 */ // (intrinsic_w_chain:{ *:[i32] } 4191:{ *:[iPTR] }, (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) => (SPACE:{ *:[i32] } (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) |
| 33195 | /* 91474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SPACE), |
| 33196 | /* 91477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33197 | /* 91479 */ GIR_RootToRootCopy, /*OpIdx*/2, // size |
| 33198 | /* 91481 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn |
| 33199 | /* 91483 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33200 | /* 91487 */ GIR_RootConstrainSelectedInstOperands, |
| 33201 | /* 91488 */ // GIR_Coverage, 1927, |
| 33202 | /* 91488 */ GIR_EraseRootFromParent_Done, |
| 33203 | /* 91489 */ // Label 2818: @91489 |
| 33204 | /* 91489 */ GIM_Try, /*On fail goto*//*Label 2819*/ GIMT_Encode4(91689), |
| 33205 | /* 91494 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base), |
| 33206 | /* 91499 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2822*/ GIMT_Encode4(91688), |
| 33207 | /* 91510 */ /*GILLT_v4s32*//*Label 2820*/ GIMT_Encode4(91518), |
| 33208 | /* 91514 */ /*GILLT_v2s64*//*Label 2821*/ GIMT_Encode4(91603), |
| 33209 | /* 91518 */ // Label 2820: @91518 |
| 33210 | /* 91518 */ GIM_Try, /*On fail goto*//*Label 2823*/ GIMT_Encode4(91602), |
| 33211 | /* 91523 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33212 | /* 91526 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 33213 | /* 91529 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33214 | /* 91533 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33215 | /* 91537 */ GIM_Try, /*On fail goto*//*Label 2824*/ GIMT_Encode4(91569), // Rule ID 5579 // |
| 33216 | /* 91542 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 33217 | /* 91546 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33218 | /* 91550 */ // MIs[1] Operand 1 |
| 33219 | /* 91550 */ // No operand predicates |
| 33220 | /* 91550 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33221 | /* 91552 */ // (intrinsic_void 4003:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33222 | /* 91552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi), |
| 33223 | /* 91555 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33224 | /* 91557 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 33225 | /* 91559 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33226 | /* 91562 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33227 | /* 91567 */ GIR_RootConstrainSelectedInstOperands, |
| 33228 | /* 91568 */ // GIR_Coverage, 5579, |
| 33229 | /* 91568 */ GIR_EraseRootFromParent_Done, |
| 33230 | /* 91569 */ // Label 2824: @91569 |
| 33231 | /* 91569 */ GIM_Try, /*On fail goto*//*Label 2825*/ GIMT_Encode4(91601), // Rule ID 5589 // |
| 33232 | /* 91574 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 33233 | /* 91578 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33234 | /* 91582 */ // MIs[1] Operand 1 |
| 33235 | /* 91582 */ // No operand predicates |
| 33236 | /* 91582 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33237 | /* 91584 */ // (intrinsic_void 4003:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33238 | /* 91584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi), |
| 33239 | /* 91587 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33240 | /* 91589 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 33241 | /* 91591 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33242 | /* 91594 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33243 | /* 91599 */ GIR_RootConstrainSelectedInstOperands, |
| 33244 | /* 91600 */ // GIR_Coverage, 5589, |
| 33245 | /* 91600 */ GIR_EraseRootFromParent_Done, |
| 33246 | /* 91601 */ // Label 2825: @91601 |
| 33247 | /* 91601 */ GIM_Reject, |
| 33248 | /* 91602 */ // Label 2823: @91602 |
| 33249 | /* 91602 */ GIM_Reject, |
| 33250 | /* 91603 */ // Label 2821: @91603 |
| 33251 | /* 91603 */ GIM_Try, /*On fail goto*//*Label 2826*/ GIMT_Encode4(91687), |
| 33252 | /* 91608 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33253 | /* 91611 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 33254 | /* 91614 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33255 | /* 91618 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33256 | /* 91622 */ GIM_Try, /*On fail goto*//*Label 2827*/ GIMT_Encode4(91654), // Rule ID 5593 // |
| 33257 | /* 91627 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 33258 | /* 91631 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33259 | /* 91635 */ // MIs[1] Operand 1 |
| 33260 | /* 91635 */ // No operand predicates |
| 33261 | /* 91635 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33262 | /* 91637 */ // (intrinsic_void 4003:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33263 | /* 91637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi), |
| 33264 | /* 91640 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33265 | /* 91642 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 33266 | /* 91644 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33267 | /* 91647 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33268 | /* 91652 */ GIR_RootConstrainSelectedInstOperands, |
| 33269 | /* 91653 */ // GIR_Coverage, 5593, |
| 33270 | /* 91653 */ GIR_EraseRootFromParent_Done, |
| 33271 | /* 91654 */ // Label 2827: @91654 |
| 33272 | /* 91654 */ GIM_Try, /*On fail goto*//*Label 2828*/ GIMT_Encode4(91686), // Rule ID 5597 // |
| 33273 | /* 91659 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 33274 | /* 91663 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33275 | /* 91667 */ // MIs[1] Operand 1 |
| 33276 | /* 91667 */ // No operand predicates |
| 33277 | /* 91667 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33278 | /* 91669 */ // (intrinsic_void 4003:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33279 | /* 91669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi), |
| 33280 | /* 91672 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33281 | /* 91674 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr |
| 33282 | /* 91676 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33283 | /* 91679 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33284 | /* 91684 */ GIR_RootConstrainSelectedInstOperands, |
| 33285 | /* 91685 */ // GIR_Coverage, 5597, |
| 33286 | /* 91685 */ GIR_EraseRootFromParent_Done, |
| 33287 | /* 91686 */ // Label 2828: @91686 |
| 33288 | /* 91686 */ GIM_Reject, |
| 33289 | /* 91687 */ // Label 2826: @91687 |
| 33290 | /* 91687 */ GIM_Reject, |
| 33291 | /* 91688 */ // Label 2822: @91688 |
| 33292 | /* 91688 */ GIM_Reject, |
| 33293 | /* 91689 */ // Label 2819: @91689 |
| 33294 | /* 91689 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2829*/ GIMT_Encode4(91746), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 3 // |
| 33295 | /* 91696 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel), |
| 33296 | /* 91701 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33297 | /* 91704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33298 | /* 91707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33299 | /* 91710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33300 | /* 91714 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33301 | /* 91718 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33302 | /* 91722 */ // (intrinsic_w_chain:{ *:[i32] } 4159:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 33303 | /* 91722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SEL), |
| 33304 | /* 91725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33305 | /* 91727 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33306 | /* 91729 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33307 | /* 91731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33308 | /* 91734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33309 | /* 91740 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33310 | /* 91744 */ GIR_RootConstrainSelectedInstOperands, |
| 33311 | /* 91745 */ // GIR_Coverage, 3, |
| 33312 | /* 91745 */ GIR_EraseRootFromParent_Done, |
| 33313 | /* 91746 */ // Label 2829: @91746 |
| 33314 | /* 91746 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2830*/ GIMT_Encode4(91803), GIMT_Encode2(GIFBS_IsARM), // Rule ID 120 // |
| 33315 | /* 91753 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx), |
| 33316 | /* 91758 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33317 | /* 91761 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33318 | /* 91764 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33319 | /* 91767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33320 | /* 91771 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33321 | /* 91775 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33322 | /* 91779 */ // (intrinsic_w_chain:{ *:[i32] } 4158:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33323 | /* 91779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SASX), |
| 33324 | /* 91782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33325 | /* 91784 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33326 | /* 91786 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33327 | /* 91788 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33328 | /* 91791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33329 | /* 91797 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33330 | /* 91801 */ GIR_RootConstrainSelectedInstOperands, |
| 33331 | /* 91802 */ // GIR_Coverage, 120, |
| 33332 | /* 91802 */ GIR_EraseRootFromParent_Done, |
| 33333 | /* 91803 */ // Label 2830: @91803 |
| 33334 | /* 91803 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2831*/ GIMT_Encode4(91860), GIMT_Encode2(GIFBS_IsARM), // Rule ID 121 // |
| 33335 | /* 91810 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16), |
| 33336 | /* 91815 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33337 | /* 91818 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33338 | /* 91821 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33339 | /* 91824 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33340 | /* 91828 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33341 | /* 91832 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33342 | /* 91836 */ // (intrinsic_w_chain:{ *:[i32] } 4156:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33343 | /* 91836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD16), |
| 33344 | /* 91839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33345 | /* 91841 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33346 | /* 91843 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33347 | /* 91845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33348 | /* 91848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33349 | /* 91854 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33350 | /* 91858 */ GIR_RootConstrainSelectedInstOperands, |
| 33351 | /* 91859 */ // GIR_Coverage, 121, |
| 33352 | /* 91859 */ GIR_EraseRootFromParent_Done, |
| 33353 | /* 91860 */ // Label 2831: @91860 |
| 33354 | /* 91860 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2832*/ GIMT_Encode4(91917), GIMT_Encode2(GIFBS_IsARM), // Rule ID 122 // |
| 33355 | /* 91867 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8), |
| 33356 | /* 91872 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33357 | /* 91875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33358 | /* 91878 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33359 | /* 91881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33360 | /* 91885 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33361 | /* 91889 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33362 | /* 91893 */ // (intrinsic_w_chain:{ *:[i32] } 4157:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33363 | /* 91893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD8), |
| 33364 | /* 91896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33365 | /* 91898 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33366 | /* 91900 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33367 | /* 91902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33368 | /* 91905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33369 | /* 91911 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33370 | /* 91915 */ GIR_RootConstrainSelectedInstOperands, |
| 33371 | /* 91916 */ // GIR_Coverage, 122, |
| 33372 | /* 91916 */ GIR_EraseRootFromParent_Done, |
| 33373 | /* 91917 */ // Label 2832: @91917 |
| 33374 | /* 91917 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2833*/ GIMT_Encode4(91974), GIMT_Encode2(GIFBS_IsARM), // Rule ID 123 // |
| 33375 | /* 91924 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax), |
| 33376 | /* 91929 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33377 | /* 91932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33378 | /* 91935 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33379 | /* 91938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33380 | /* 91942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33381 | /* 91946 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33382 | /* 91950 */ // (intrinsic_w_chain:{ *:[i32] } 4194:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33383 | /* 91950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSAX), |
| 33384 | /* 91953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33385 | /* 91955 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33386 | /* 91957 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33387 | /* 91959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33388 | /* 91962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33389 | /* 91968 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33390 | /* 91972 */ GIR_RootConstrainSelectedInstOperands, |
| 33391 | /* 91973 */ // GIR_Coverage, 123, |
| 33392 | /* 91973 */ GIR_EraseRootFromParent_Done, |
| 33393 | /* 91974 */ // Label 2833: @91974 |
| 33394 | /* 91974 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2834*/ GIMT_Encode4(92031), GIMT_Encode2(GIFBS_IsARM), // Rule ID 124 // |
| 33395 | /* 91981 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16), |
| 33396 | /* 91986 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33397 | /* 91989 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33398 | /* 91992 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33399 | /* 91995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33400 | /* 91999 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33401 | /* 92003 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33402 | /* 92007 */ // (intrinsic_w_chain:{ *:[i32] } 4195:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33403 | /* 92007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB16), |
| 33404 | /* 92010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33405 | /* 92012 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33406 | /* 92014 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33407 | /* 92016 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33408 | /* 92019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33409 | /* 92025 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33410 | /* 92029 */ GIR_RootConstrainSelectedInstOperands, |
| 33411 | /* 92030 */ // GIR_Coverage, 124, |
| 33412 | /* 92030 */ GIR_EraseRootFromParent_Done, |
| 33413 | /* 92031 */ // Label 2834: @92031 |
| 33414 | /* 92031 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2835*/ GIMT_Encode4(92088), GIMT_Encode2(GIFBS_IsARM), // Rule ID 125 // |
| 33415 | /* 92038 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8), |
| 33416 | /* 92043 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33417 | /* 92046 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33418 | /* 92049 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33419 | /* 92052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33420 | /* 92056 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33421 | /* 92060 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33422 | /* 92064 */ // (intrinsic_w_chain:{ *:[i32] } 4196:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33423 | /* 92064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB8), |
| 33424 | /* 92067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33425 | /* 92069 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33426 | /* 92071 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33427 | /* 92073 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33428 | /* 92076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33429 | /* 92082 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33430 | /* 92086 */ GIR_RootConstrainSelectedInstOperands, |
| 33431 | /* 92087 */ // GIR_Coverage, 125, |
| 33432 | /* 92087 */ GIR_EraseRootFromParent_Done, |
| 33433 | /* 92088 */ // Label 2835: @92088 |
| 33434 | /* 92088 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2836*/ GIMT_Encode4(92145), GIMT_Encode2(GIFBS_IsARM), // Rule ID 126 // |
| 33435 | /* 92095 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx), |
| 33436 | /* 92100 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33437 | /* 92103 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33438 | /* 92106 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33439 | /* 92109 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33440 | /* 92113 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33441 | /* 92117 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33442 | /* 92121 */ // (intrinsic_w_chain:{ *:[i32] } 4209:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33443 | /* 92121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UASX), |
| 33444 | /* 92124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33445 | /* 92126 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33446 | /* 92128 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33447 | /* 92130 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33448 | /* 92133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33449 | /* 92139 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33450 | /* 92143 */ GIR_RootConstrainSelectedInstOperands, |
| 33451 | /* 92144 */ // GIR_Coverage, 126, |
| 33452 | /* 92144 */ GIR_EraseRootFromParent_Done, |
| 33453 | /* 92145 */ // Label 2836: @92145 |
| 33454 | /* 92145 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2837*/ GIMT_Encode4(92202), GIMT_Encode2(GIFBS_IsARM), // Rule ID 127 // |
| 33455 | /* 92152 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16), |
| 33456 | /* 92157 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33457 | /* 92160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33458 | /* 92163 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33459 | /* 92166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33460 | /* 92170 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33461 | /* 92174 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33462 | /* 92178 */ // (intrinsic_w_chain:{ *:[i32] } 4207:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33463 | /* 92178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD16), |
| 33464 | /* 92181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33465 | /* 92183 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33466 | /* 92185 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33467 | /* 92187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33468 | /* 92190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33469 | /* 92196 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33470 | /* 92200 */ GIR_RootConstrainSelectedInstOperands, |
| 33471 | /* 92201 */ // GIR_Coverage, 127, |
| 33472 | /* 92201 */ GIR_EraseRootFromParent_Done, |
| 33473 | /* 92202 */ // Label 2837: @92202 |
| 33474 | /* 92202 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2838*/ GIMT_Encode4(92259), GIMT_Encode2(GIFBS_IsARM), // Rule ID 128 // |
| 33475 | /* 92209 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8), |
| 33476 | /* 92214 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33477 | /* 92217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33478 | /* 92220 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33479 | /* 92223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33480 | /* 92227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33481 | /* 92231 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33482 | /* 92235 */ // (intrinsic_w_chain:{ *:[i32] } 4208:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33483 | /* 92235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD8), |
| 33484 | /* 92238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33485 | /* 92240 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33486 | /* 92242 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33487 | /* 92244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33488 | /* 92247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33489 | /* 92253 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33490 | /* 92257 */ GIR_RootConstrainSelectedInstOperands, |
| 33491 | /* 92258 */ // GIR_Coverage, 128, |
| 33492 | /* 92258 */ GIR_EraseRootFromParent_Done, |
| 33493 | /* 92259 */ // Label 2838: @92259 |
| 33494 | /* 92259 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2839*/ GIMT_Encode4(92316), GIMT_Encode2(GIFBS_IsARM), // Rule ID 129 // |
| 33495 | /* 92266 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax), |
| 33496 | /* 92271 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33497 | /* 92274 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33498 | /* 92277 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33499 | /* 92280 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33500 | /* 92284 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33501 | /* 92288 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33502 | /* 92292 */ // (intrinsic_w_chain:{ *:[i32] } 4227:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33503 | /* 92292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAX), |
| 33504 | /* 92295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33505 | /* 92297 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33506 | /* 92299 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33507 | /* 92301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33508 | /* 92304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33509 | /* 92310 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33510 | /* 92314 */ GIR_RootConstrainSelectedInstOperands, |
| 33511 | /* 92315 */ // GIR_Coverage, 129, |
| 33512 | /* 92315 */ GIR_EraseRootFromParent_Done, |
| 33513 | /* 92316 */ // Label 2839: @92316 |
| 33514 | /* 92316 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2840*/ GIMT_Encode4(92373), GIMT_Encode2(GIFBS_IsARM), // Rule ID 130 // |
| 33515 | /* 92323 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16), |
| 33516 | /* 92328 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33517 | /* 92331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33518 | /* 92334 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33519 | /* 92337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33520 | /* 92341 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33521 | /* 92345 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33522 | /* 92349 */ // (intrinsic_w_chain:{ *:[i32] } 4228:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33523 | /* 92349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB16), |
| 33524 | /* 92352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33525 | /* 92354 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33526 | /* 92356 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33527 | /* 92358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33528 | /* 92361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33529 | /* 92367 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33530 | /* 92371 */ GIR_RootConstrainSelectedInstOperands, |
| 33531 | /* 92372 */ // GIR_Coverage, 130, |
| 33532 | /* 92372 */ GIR_EraseRootFromParent_Done, |
| 33533 | /* 92373 */ // Label 2840: @92373 |
| 33534 | /* 92373 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2841*/ GIMT_Encode4(92430), GIMT_Encode2(GIFBS_IsARM), // Rule ID 131 // |
| 33535 | /* 92380 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8), |
| 33536 | /* 92385 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33537 | /* 92388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33538 | /* 92391 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33539 | /* 92394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33540 | /* 92398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33541 | /* 92402 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 33542 | /* 92406 */ // (intrinsic_w_chain:{ *:[i32] } 4229:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) |
| 33543 | /* 92406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB8), |
| 33544 | /* 92409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33545 | /* 92411 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33546 | /* 92413 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33547 | /* 92415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33548 | /* 92418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33549 | /* 92424 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33550 | /* 92428 */ GIR_RootConstrainSelectedInstOperands, |
| 33551 | /* 92429 */ // GIR_Coverage, 131, |
| 33552 | /* 92429 */ GIR_EraseRootFromParent_Done, |
| 33553 | /* 92430 */ // Label 2841: @92430 |
| 33554 | /* 92430 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2842*/ GIMT_Encode4(92487), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 430 // |
| 33555 | /* 92437 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel), |
| 33556 | /* 92442 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33557 | /* 92445 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33558 | /* 92448 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33559 | /* 92451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33560 | /* 92455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33561 | /* 92459 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33562 | /* 92463 */ // (intrinsic_w_chain:{ *:[i32] } 4159:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (t2SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 33563 | /* 92463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SEL), |
| 33564 | /* 92466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33565 | /* 92468 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33566 | /* 92470 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33567 | /* 92472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33568 | /* 92475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33569 | /* 92481 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33570 | /* 92485 */ GIR_RootConstrainSelectedInstOperands, |
| 33571 | /* 92486 */ // GIR_Coverage, 430, |
| 33572 | /* 92486 */ GIR_EraseRootFromParent_Done, |
| 33573 | /* 92487 */ // Label 2842: @92487 |
| 33574 | /* 92487 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2843*/ GIMT_Encode4(92544), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 443 // |
| 33575 | /* 92494 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx), |
| 33576 | /* 92499 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33577 | /* 92502 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33578 | /* 92505 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33579 | /* 92508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33580 | /* 92512 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33581 | /* 92516 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33582 | /* 92520 */ // (intrinsic_w_chain:{ *:[i32] } 4158:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33583 | /* 92520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SASX), |
| 33584 | /* 92523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33585 | /* 92525 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33586 | /* 92527 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33587 | /* 92529 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33588 | /* 92532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33589 | /* 92538 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33590 | /* 92542 */ GIR_RootConstrainSelectedInstOperands, |
| 33591 | /* 92543 */ // GIR_Coverage, 443, |
| 33592 | /* 92543 */ GIR_EraseRootFromParent_Done, |
| 33593 | /* 92544 */ // Label 2843: @92544 |
| 33594 | /* 92544 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2844*/ GIMT_Encode4(92601), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 444 // |
| 33595 | /* 92551 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16), |
| 33596 | /* 92556 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33597 | /* 92559 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33598 | /* 92562 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33599 | /* 92565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33600 | /* 92569 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33601 | /* 92573 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33602 | /* 92577 */ // (intrinsic_w_chain:{ *:[i32] } 4156:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33603 | /* 92577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD16), |
| 33604 | /* 92580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33605 | /* 92582 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33606 | /* 92584 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33607 | /* 92586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33608 | /* 92589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33609 | /* 92595 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33610 | /* 92599 */ GIR_RootConstrainSelectedInstOperands, |
| 33611 | /* 92600 */ // GIR_Coverage, 444, |
| 33612 | /* 92600 */ GIR_EraseRootFromParent_Done, |
| 33613 | /* 92601 */ // Label 2844: @92601 |
| 33614 | /* 92601 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2845*/ GIMT_Encode4(92658), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 445 // |
| 33615 | /* 92608 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8), |
| 33616 | /* 92613 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33617 | /* 92616 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33618 | /* 92619 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33619 | /* 92622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33620 | /* 92626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33621 | /* 92630 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33622 | /* 92634 */ // (intrinsic_w_chain:{ *:[i32] } 4157:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33623 | /* 92634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD8), |
| 33624 | /* 92637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33625 | /* 92639 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33626 | /* 92641 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33627 | /* 92643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33628 | /* 92646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33629 | /* 92652 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33630 | /* 92656 */ GIR_RootConstrainSelectedInstOperands, |
| 33631 | /* 92657 */ // GIR_Coverage, 445, |
| 33632 | /* 92657 */ GIR_EraseRootFromParent_Done, |
| 33633 | /* 92658 */ // Label 2845: @92658 |
| 33634 | /* 92658 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2846*/ GIMT_Encode4(92715), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 446 // |
| 33635 | /* 92665 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax), |
| 33636 | /* 92670 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33637 | /* 92673 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33638 | /* 92676 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33639 | /* 92679 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33640 | /* 92683 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33641 | /* 92687 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33642 | /* 92691 */ // (intrinsic_w_chain:{ *:[i32] } 4194:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33643 | /* 92691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSAX), |
| 33644 | /* 92694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33645 | /* 92696 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33646 | /* 92698 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33647 | /* 92700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33648 | /* 92703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33649 | /* 92709 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33650 | /* 92713 */ GIR_RootConstrainSelectedInstOperands, |
| 33651 | /* 92714 */ // GIR_Coverage, 446, |
| 33652 | /* 92714 */ GIR_EraseRootFromParent_Done, |
| 33653 | /* 92715 */ // Label 2846: @92715 |
| 33654 | /* 92715 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2847*/ GIMT_Encode4(92772), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 447 // |
| 33655 | /* 92722 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16), |
| 33656 | /* 92727 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33657 | /* 92730 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33658 | /* 92733 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33659 | /* 92736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33660 | /* 92740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33661 | /* 92744 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33662 | /* 92748 */ // (intrinsic_w_chain:{ *:[i32] } 4195:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33663 | /* 92748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB16), |
| 33664 | /* 92751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33665 | /* 92753 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33666 | /* 92755 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33667 | /* 92757 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33668 | /* 92760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33669 | /* 92766 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33670 | /* 92770 */ GIR_RootConstrainSelectedInstOperands, |
| 33671 | /* 92771 */ // GIR_Coverage, 447, |
| 33672 | /* 92771 */ GIR_EraseRootFromParent_Done, |
| 33673 | /* 92772 */ // Label 2847: @92772 |
| 33674 | /* 92772 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2848*/ GIMT_Encode4(92829), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 448 // |
| 33675 | /* 92779 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8), |
| 33676 | /* 92784 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33677 | /* 92787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33678 | /* 92790 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33679 | /* 92793 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33680 | /* 92797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33681 | /* 92801 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33682 | /* 92805 */ // (intrinsic_w_chain:{ *:[i32] } 4196:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33683 | /* 92805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB8), |
| 33684 | /* 92808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33685 | /* 92810 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33686 | /* 92812 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33687 | /* 92814 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33688 | /* 92817 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33689 | /* 92823 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33690 | /* 92827 */ GIR_RootConstrainSelectedInstOperands, |
| 33691 | /* 92828 */ // GIR_Coverage, 448, |
| 33692 | /* 92828 */ GIR_EraseRootFromParent_Done, |
| 33693 | /* 92829 */ // Label 2848: @92829 |
| 33694 | /* 92829 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2849*/ GIMT_Encode4(92886), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 449 // |
| 33695 | /* 92836 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx), |
| 33696 | /* 92841 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33697 | /* 92844 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33698 | /* 92847 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33699 | /* 92850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33700 | /* 92854 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33701 | /* 92858 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33702 | /* 92862 */ // (intrinsic_w_chain:{ *:[i32] } 4209:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33703 | /* 92862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UASX), |
| 33704 | /* 92865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33705 | /* 92867 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33706 | /* 92869 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33707 | /* 92871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33708 | /* 92874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33709 | /* 92880 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33710 | /* 92884 */ GIR_RootConstrainSelectedInstOperands, |
| 33711 | /* 92885 */ // GIR_Coverage, 449, |
| 33712 | /* 92885 */ GIR_EraseRootFromParent_Done, |
| 33713 | /* 92886 */ // Label 2849: @92886 |
| 33714 | /* 92886 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2850*/ GIMT_Encode4(92943), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 450 // |
| 33715 | /* 92893 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16), |
| 33716 | /* 92898 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33717 | /* 92901 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33718 | /* 92904 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33719 | /* 92907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33720 | /* 92911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33721 | /* 92915 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33722 | /* 92919 */ // (intrinsic_w_chain:{ *:[i32] } 4207:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33723 | /* 92919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD16), |
| 33724 | /* 92922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33725 | /* 92924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33726 | /* 92926 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33727 | /* 92928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33728 | /* 92931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33729 | /* 92937 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33730 | /* 92941 */ GIR_RootConstrainSelectedInstOperands, |
| 33731 | /* 92942 */ // GIR_Coverage, 450, |
| 33732 | /* 92942 */ GIR_EraseRootFromParent_Done, |
| 33733 | /* 92943 */ // Label 2850: @92943 |
| 33734 | /* 92943 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2851*/ GIMT_Encode4(93000), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 451 // |
| 33735 | /* 92950 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8), |
| 33736 | /* 92955 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33737 | /* 92958 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33738 | /* 92961 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33739 | /* 92964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33740 | /* 92968 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33741 | /* 92972 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33742 | /* 92976 */ // (intrinsic_w_chain:{ *:[i32] } 4208:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33743 | /* 92976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD8), |
| 33744 | /* 92979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33745 | /* 92981 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33746 | /* 92983 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33747 | /* 92985 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33748 | /* 92988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33749 | /* 92994 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33750 | /* 92998 */ GIR_RootConstrainSelectedInstOperands, |
| 33751 | /* 92999 */ // GIR_Coverage, 451, |
| 33752 | /* 92999 */ GIR_EraseRootFromParent_Done, |
| 33753 | /* 93000 */ // Label 2851: @93000 |
| 33754 | /* 93000 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2852*/ GIMT_Encode4(93057), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 452 // |
| 33755 | /* 93007 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax), |
| 33756 | /* 93012 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33757 | /* 93015 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33758 | /* 93018 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33759 | /* 93021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33760 | /* 93025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33761 | /* 93029 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33762 | /* 93033 */ // (intrinsic_w_chain:{ *:[i32] } 4227:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33763 | /* 93033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAX), |
| 33764 | /* 93036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33765 | /* 93038 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33766 | /* 93040 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33767 | /* 93042 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33768 | /* 93045 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33769 | /* 93051 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33770 | /* 93055 */ GIR_RootConstrainSelectedInstOperands, |
| 33771 | /* 93056 */ // GIR_Coverage, 452, |
| 33772 | /* 93056 */ GIR_EraseRootFromParent_Done, |
| 33773 | /* 93057 */ // Label 2852: @93057 |
| 33774 | /* 93057 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2853*/ GIMT_Encode4(93114), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 453 // |
| 33775 | /* 93064 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16), |
| 33776 | /* 93069 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33777 | /* 93072 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33778 | /* 93075 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33779 | /* 93078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33780 | /* 93082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33781 | /* 93086 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33782 | /* 93090 */ // (intrinsic_w_chain:{ *:[i32] } 4228:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33783 | /* 93090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB16), |
| 33784 | /* 93093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33785 | /* 93095 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33786 | /* 93097 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33787 | /* 93099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33788 | /* 93102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33789 | /* 93108 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33790 | /* 93112 */ GIR_RootConstrainSelectedInstOperands, |
| 33791 | /* 93113 */ // GIR_Coverage, 453, |
| 33792 | /* 93113 */ GIR_EraseRootFromParent_Done, |
| 33793 | /* 93114 */ // Label 2853: @93114 |
| 33794 | /* 93114 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2854*/ GIMT_Encode4(93171), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 454 // |
| 33795 | /* 93121 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8), |
| 33796 | /* 93126 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 33797 | /* 93129 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 33798 | /* 93132 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33799 | /* 93135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33800 | /* 93139 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33801 | /* 93143 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 33802 | /* 93147 */ // (intrinsic_w_chain:{ *:[i32] } 4229:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 33803 | /* 93147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB8), |
| 33804 | /* 93150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 33805 | /* 93152 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 33806 | /* 93154 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm |
| 33807 | /* 93156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 33808 | /* 93159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 33809 | /* 93165 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33810 | /* 93169 */ GIR_RootConstrainSelectedInstOperands, |
| 33811 | /* 93170 */ // GIR_Coverage, 454, |
| 33812 | /* 93170 */ GIR_EraseRootFromParent_Done, |
| 33813 | /* 93171 */ // Label 2854: @93171 |
| 33814 | /* 93171 */ GIM_Reject, |
| 33815 | /* 93172 */ // Label 2807: @93172 |
| 33816 | /* 93172 */ GIM_Try, /*On fail goto*//*Label 2855*/ GIMT_Encode4(93397), |
| 33817 | /* 93177 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 33818 | /* 93180 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base_wb), |
| 33819 | /* 93185 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2858*/ GIMT_Encode4(93396), |
| 33820 | /* 93196 */ /*GILLT_v4s32*//*Label 2856*/ GIMT_Encode4(93204), |
| 33821 | /* 93200 */ /*GILLT_v2s64*//*Label 2857*/ GIMT_Encode4(93300), |
| 33822 | /* 93204 */ // Label 2856: @93204 |
| 33823 | /* 93204 */ GIM_Try, /*On fail goto*//*Label 2859*/ GIMT_Encode4(93299), |
| 33824 | /* 93209 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 33825 | /* 93212 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33826 | /* 93215 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 33827 | /* 93218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33828 | /* 93222 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33829 | /* 93226 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33830 | /* 93230 */ GIM_Try, /*On fail goto*//*Label 2860*/ GIMT_Encode4(93264), // Rule ID 5581 // |
| 33831 | /* 93235 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33832 | /* 93239 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33833 | /* 93243 */ // MIs[1] Operand 1 |
| 33834 | /* 93243 */ // No operand predicates |
| 33835 | /* 93243 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33836 | /* 93245 */ // (intrinsic_w_chain:{ *:[v4i32] } 4005:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33837 | /* 93245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre), |
| 33838 | /* 93248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33839 | /* 93250 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33840 | /* 93252 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33841 | /* 93254 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33842 | /* 93257 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33843 | /* 93262 */ GIR_RootConstrainSelectedInstOperands, |
| 33844 | /* 93263 */ // GIR_Coverage, 5581, |
| 33845 | /* 93263 */ GIR_EraseRootFromParent_Done, |
| 33846 | /* 93264 */ // Label 2860: @93264 |
| 33847 | /* 93264 */ GIM_Try, /*On fail goto*//*Label 2861*/ GIMT_Encode4(93298), // Rule ID 5591 // |
| 33848 | /* 93269 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33849 | /* 93273 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33850 | /* 93277 */ // MIs[1] Operand 1 |
| 33851 | /* 93277 */ // No operand predicates |
| 33852 | /* 93277 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33853 | /* 93279 */ // (intrinsic_w_chain:{ *:[v4i32] } 4005:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33854 | /* 93279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre), |
| 33855 | /* 93282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33856 | /* 93284 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33857 | /* 93286 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33858 | /* 93288 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33859 | /* 93291 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33860 | /* 93296 */ GIR_RootConstrainSelectedInstOperands, |
| 33861 | /* 93297 */ // GIR_Coverage, 5591, |
| 33862 | /* 93297 */ GIR_EraseRootFromParent_Done, |
| 33863 | /* 93298 */ // Label 2861: @93298 |
| 33864 | /* 93298 */ GIM_Reject, |
| 33865 | /* 93299 */ // Label 2859: @93299 |
| 33866 | /* 93299 */ GIM_Reject, |
| 33867 | /* 93300 */ // Label 2857: @93300 |
| 33868 | /* 93300 */ GIM_Try, /*On fail goto*//*Label 2862*/ GIMT_Encode4(93395), |
| 33869 | /* 93305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 33870 | /* 93308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 33871 | /* 93311 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64, |
| 33872 | /* 93314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33873 | /* 93318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33874 | /* 93322 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33875 | /* 93326 */ GIM_Try, /*On fail goto*//*Label 2863*/ GIMT_Encode4(93360), // Rule ID 5595 // |
| 33876 | /* 93331 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33877 | /* 93335 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33878 | /* 93339 */ // MIs[1] Operand 1 |
| 33879 | /* 93339 */ // No operand predicates |
| 33880 | /* 93339 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33881 | /* 93341 */ // (intrinsic_w_chain:{ *:[v2i64] } 4005:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33882 | /* 93341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre), |
| 33883 | /* 93344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33884 | /* 93346 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33885 | /* 93348 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33886 | /* 93350 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33887 | /* 93353 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33888 | /* 93358 */ GIR_RootConstrainSelectedInstOperands, |
| 33889 | /* 93359 */ // GIR_Coverage, 5595, |
| 33890 | /* 93359 */ GIR_EraseRootFromParent_Done, |
| 33891 | /* 93360 */ // Label 2863: @93360 |
| 33892 | /* 93360 */ GIM_Try, /*On fail goto*//*Label 2864*/ GIMT_Encode4(93394), // Rule ID 5599 // |
| 33893 | /* 93365 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 33894 | /* 93369 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 33895 | /* 93373 */ // MIs[1] Operand 1 |
| 33896 | /* 93373 */ // No operand predicates |
| 33897 | /* 93373 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 33898 | /* 93375 */ // (intrinsic_w_chain:{ *:[v2i64] } 4005:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) |
| 33899 | /* 93375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre), |
| 33900 | /* 93378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb] |
| 33901 | /* 93380 */ GIR_RootToRootCopy, /*OpIdx*/4, // data |
| 33902 | /* 93382 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr |
| 33903 | /* 93384 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset |
| 33904 | /* 93387 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 33905 | /* 93392 */ GIR_RootConstrainSelectedInstOperands, |
| 33906 | /* 93393 */ // GIR_Coverage, 5599, |
| 33907 | /* 93393 */ GIR_EraseRootFromParent_Done, |
| 33908 | /* 93394 */ // Label 2864: @93394 |
| 33909 | /* 93394 */ GIM_Reject, |
| 33910 | /* 93395 */ // Label 2862: @93395 |
| 33911 | /* 93395 */ GIM_Reject, |
| 33912 | /* 93396 */ // Label 2858: @93396 |
| 33913 | /* 93396 */ GIM_Reject, |
| 33914 | /* 93397 */ // Label 2855: @93397 |
| 33915 | /* 93397 */ GIM_Try, /*On fail goto*//*Label 2865*/ GIMT_Encode4(94233), |
| 33916 | /* 93402 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 33917 | /* 93405 */ GIM_Try, /*On fail goto*//*Label 2866*/ GIMT_Encode4(93989), |
| 33918 | /* 93410 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset), |
| 33919 | /* 93415 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 2871*/ GIMT_Encode4(93988), |
| 33920 | /* 93426 */ /*GILLT_v16s8*//*Label 2867*/ GIMT_Encode4(93450), GIMT_Encode4(0), |
| 33921 | /* 93434 */ /*GILLT_v8s16*//*Label 2868*/ GIMT_Encode4(93504), GIMT_Encode4(0), |
| 33922 | /* 93442 */ /*GILLT_v4s32*//*Label 2869*/ GIMT_Encode4(93680), |
| 33923 | /* 93446 */ /*GILLT_v2s64*//*Label 2870*/ GIMT_Encode4(93904), |
| 33924 | /* 93450 */ // Label 2867: @93450 |
| 33925 | /* 93450 */ GIM_Try, /*On fail goto*//*Label 2872*/ GIMT_Encode4(93503), // Rule ID 5473 // |
| 33926 | /* 93455 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 33927 | /* 93458 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33928 | /* 93461 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33929 | /* 93464 */ // MIs[0] base |
| 33930 | /* 93464 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33931 | /* 93468 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33932 | /* 93472 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33933 | /* 93476 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33934 | /* 93480 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 33935 | /* 93484 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33936 | /* 93488 */ // (intrinsic_void 4007:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, MQPR:{ *:[v16i8] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB8_rq MQPR:{ *:[v16i8] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) |
| 33937 | /* 93488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB8_rq), |
| 33938 | /* 93491 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33939 | /* 93493 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33940 | /* 93495 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33941 | /* 93497 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33942 | /* 93501 */ GIR_RootConstrainSelectedInstOperands, |
| 33943 | /* 93502 */ // GIR_Coverage, 5473, |
| 33944 | /* 93502 */ GIR_EraseRootFromParent_Done, |
| 33945 | /* 93503 */ // Label 2872: @93503 |
| 33946 | /* 93503 */ GIM_Reject, |
| 33947 | /* 93504 */ // Label 2868: @93504 |
| 33948 | /* 93504 */ GIM_Try, /*On fail goto*//*Label 2873*/ GIMT_Encode4(93679), |
| 33949 | /* 93509 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 33950 | /* 93512 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 33951 | /* 93515 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 33952 | /* 93518 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 33953 | /* 93522 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 33954 | /* 93526 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33955 | /* 93530 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 33956 | /* 93534 */ GIM_Try, /*On fail goto*//*Label 2874*/ GIMT_Encode4(93592), |
| 33957 | /* 93539 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33958 | /* 93543 */ GIM_Try, /*On fail goto*//*Label 2875*/ GIMT_Encode4(93567), // Rule ID 5469 // |
| 33959 | /* 93548 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33960 | /* 93552 */ // (intrinsic_void 4007:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33961 | /* 93552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u), |
| 33962 | /* 93555 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33963 | /* 93557 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33964 | /* 93559 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33965 | /* 93561 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33966 | /* 93565 */ GIR_RootConstrainSelectedInstOperands, |
| 33967 | /* 93566 */ // GIR_Coverage, 5469, |
| 33968 | /* 93566 */ GIR_EraseRootFromParent_Done, |
| 33969 | /* 93567 */ // Label 2875: @93567 |
| 33970 | /* 93567 */ GIM_Try, /*On fail goto*//*Label 2876*/ GIMT_Encode4(93591), // Rule ID 5470 // |
| 33971 | /* 93572 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 33972 | /* 93576 */ // (intrinsic_void 4007:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33973 | /* 93576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq), |
| 33974 | /* 93579 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33975 | /* 93581 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33976 | /* 93583 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33977 | /* 93585 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33978 | /* 93589 */ GIR_RootConstrainSelectedInstOperands, |
| 33979 | /* 93590 */ // GIR_Coverage, 5470, |
| 33980 | /* 93590 */ GIR_EraseRootFromParent_Done, |
| 33981 | /* 93591 */ // Label 2876: @93591 |
| 33982 | /* 93591 */ GIM_Reject, |
| 33983 | /* 93592 */ // Label 2874: @93592 |
| 33984 | /* 93592 */ GIM_Try, /*On fail goto*//*Label 2877*/ GIMT_Encode4(93620), // Rule ID 5553 // |
| 33985 | /* 93597 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 33986 | /* 93601 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 33987 | /* 93605 */ // (intrinsic_void 4007:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 33988 | /* 93605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB16_rq), |
| 33989 | /* 93608 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 33990 | /* 93610 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 33991 | /* 93612 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 33992 | /* 93614 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33993 | /* 93618 */ GIR_RootConstrainSelectedInstOperands, |
| 33994 | /* 93619 */ // GIR_Coverage, 5553, |
| 33995 | /* 93619 */ GIR_EraseRootFromParent_Done, |
| 33996 | /* 93620 */ // Label 2877: @93620 |
| 33997 | /* 93620 */ GIM_Try, /*On fail goto*//*Label 2878*/ GIMT_Encode4(93678), |
| 33998 | /* 93625 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 33999 | /* 93629 */ GIM_Try, /*On fail goto*//*Label 2879*/ GIMT_Encode4(93653), // Rule ID 5557 // |
| 34000 | /* 93634 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34001 | /* 93638 */ // (intrinsic_void 4007:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34002 | /* 93638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u), |
| 34003 | /* 93641 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34004 | /* 93643 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34005 | /* 93645 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34006 | /* 93647 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34007 | /* 93651 */ GIR_RootConstrainSelectedInstOperands, |
| 34008 | /* 93652 */ // GIR_Coverage, 5557, |
| 34009 | /* 93652 */ GIR_EraseRootFromParent_Done, |
| 34010 | /* 93653 */ // Label 2879: @93653 |
| 34011 | /* 93653 */ GIM_Try, /*On fail goto*//*Label 2880*/ GIMT_Encode4(93677), // Rule ID 5558 // |
| 34012 | /* 93658 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34013 | /* 93662 */ // (intrinsic_void 4007:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34014 | /* 93662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq), |
| 34015 | /* 93665 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34016 | /* 93667 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34017 | /* 93669 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34018 | /* 93671 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34019 | /* 93675 */ GIR_RootConstrainSelectedInstOperands, |
| 34020 | /* 93676 */ // GIR_Coverage, 5558, |
| 34021 | /* 93676 */ GIR_EraseRootFromParent_Done, |
| 34022 | /* 93677 */ // Label 2880: @93677 |
| 34023 | /* 93677 */ GIM_Reject, |
| 34024 | /* 93678 */ // Label 2878: @93678 |
| 34025 | /* 93678 */ GIM_Reject, |
| 34026 | /* 93679 */ // Label 2873: @93679 |
| 34027 | /* 93679 */ GIM_Reject, |
| 34028 | /* 93680 */ // Label 2869: @93680 |
| 34029 | /* 93680 */ GIM_Try, /*On fail goto*//*Label 2881*/ GIMT_Encode4(93903), |
| 34030 | /* 93685 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34031 | /* 93688 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34032 | /* 93691 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34033 | /* 93694 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34034 | /* 93698 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34035 | /* 93702 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34036 | /* 93706 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34037 | /* 93710 */ GIM_Try, /*On fail goto*//*Label 2882*/ GIMT_Encode4(93738), // Rule ID 5555 // |
| 34038 | /* 93715 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34039 | /* 93719 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34040 | /* 93723 */ // (intrinsic_void 4007:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34041 | /* 93723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB32_rq), |
| 34042 | /* 93726 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34043 | /* 93728 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34044 | /* 93730 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34045 | /* 93732 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34046 | /* 93736 */ GIR_RootConstrainSelectedInstOperands, |
| 34047 | /* 93737 */ // GIR_Coverage, 5555, |
| 34048 | /* 93737 */ GIR_EraseRootFromParent_Done, |
| 34049 | /* 93738 */ // Label 2882: @93738 |
| 34050 | /* 93738 */ GIM_Try, /*On fail goto*//*Label 2883*/ GIMT_Encode4(93796), |
| 34051 | /* 93743 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34052 | /* 93747 */ GIM_Try, /*On fail goto*//*Label 2884*/ GIMT_Encode4(93771), // Rule ID 5561 // |
| 34053 | /* 93752 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34054 | /* 93756 */ // (intrinsic_void 4007:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34055 | /* 93756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq_u), |
| 34056 | /* 93759 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34057 | /* 93761 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34058 | /* 93763 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34059 | /* 93765 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34060 | /* 93769 */ GIR_RootConstrainSelectedInstOperands, |
| 34061 | /* 93770 */ // GIR_Coverage, 5561, |
| 34062 | /* 93770 */ GIR_EraseRootFromParent_Done, |
| 34063 | /* 93771 */ // Label 2884: @93771 |
| 34064 | /* 93771 */ GIM_Try, /*On fail goto*//*Label 2885*/ GIMT_Encode4(93795), // Rule ID 5562 // |
| 34065 | /* 93776 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34066 | /* 93780 */ // (intrinsic_void 4007:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34067 | /* 93780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq), |
| 34068 | /* 93783 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34069 | /* 93785 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34070 | /* 93787 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34071 | /* 93789 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34072 | /* 93793 */ GIR_RootConstrainSelectedInstOperands, |
| 34073 | /* 93794 */ // GIR_Coverage, 5562, |
| 34074 | /* 93794 */ GIR_EraseRootFromParent_Done, |
| 34075 | /* 93795 */ // Label 2885: @93795 |
| 34076 | /* 93795 */ GIM_Reject, |
| 34077 | /* 93796 */ // Label 2883: @93796 |
| 34078 | /* 93796 */ GIM_Try, /*On fail goto*//*Label 2886*/ GIMT_Encode4(93902), |
| 34079 | /* 93801 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34080 | /* 93805 */ GIM_Try, /*On fail goto*//*Label 2887*/ GIMT_Encode4(93829), // Rule ID 5565 // |
| 34081 | /* 93810 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34082 | /* 93814 */ // (intrinsic_void 4007:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34083 | /* 93814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u), |
| 34084 | /* 93817 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34085 | /* 93819 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34086 | /* 93821 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34087 | /* 93823 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34088 | /* 93827 */ GIR_RootConstrainSelectedInstOperands, |
| 34089 | /* 93828 */ // GIR_Coverage, 5565, |
| 34090 | /* 93828 */ GIR_EraseRootFromParent_Done, |
| 34091 | /* 93829 */ // Label 2887: @93829 |
| 34092 | /* 93829 */ GIM_Try, /*On fail goto*//*Label 2888*/ GIMT_Encode4(93853), // Rule ID 5566 // |
| 34093 | /* 93834 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34094 | /* 93838 */ // (intrinsic_void 4007:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34095 | /* 93838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq), |
| 34096 | /* 93841 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34097 | /* 93843 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34098 | /* 93845 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34099 | /* 93847 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34100 | /* 93851 */ GIR_RootConstrainSelectedInstOperands, |
| 34101 | /* 93852 */ // GIR_Coverage, 5566, |
| 34102 | /* 93852 */ GIR_EraseRootFromParent_Done, |
| 34103 | /* 93853 */ // Label 2888: @93853 |
| 34104 | /* 93853 */ GIM_Try, /*On fail goto*//*Label 2889*/ GIMT_Encode4(93877), // Rule ID 5569 // |
| 34105 | /* 93858 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34106 | /* 93862 */ // (intrinsic_void 4007:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34107 | /* 93862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u), |
| 34108 | /* 93865 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34109 | /* 93867 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34110 | /* 93869 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34111 | /* 93871 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34112 | /* 93875 */ GIR_RootConstrainSelectedInstOperands, |
| 34113 | /* 93876 */ // GIR_Coverage, 5569, |
| 34114 | /* 93876 */ GIR_EraseRootFromParent_Done, |
| 34115 | /* 93877 */ // Label 2889: @93877 |
| 34116 | /* 93877 */ GIM_Try, /*On fail goto*//*Label 2890*/ GIMT_Encode4(93901), // Rule ID 5570 // |
| 34117 | /* 93882 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34118 | /* 93886 */ // (intrinsic_void 4007:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34119 | /* 93886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq), |
| 34120 | /* 93889 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34121 | /* 93891 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34122 | /* 93893 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34123 | /* 93895 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34124 | /* 93899 */ GIR_RootConstrainSelectedInstOperands, |
| 34125 | /* 93900 */ // GIR_Coverage, 5570, |
| 34126 | /* 93900 */ GIR_EraseRootFromParent_Done, |
| 34127 | /* 93901 */ // Label 2890: @93901 |
| 34128 | /* 93901 */ GIM_Reject, |
| 34129 | /* 93902 */ // Label 2886: @93902 |
| 34130 | /* 93902 */ GIM_Reject, |
| 34131 | /* 93903 */ // Label 2881: @93903 |
| 34132 | /* 93903 */ GIM_Reject, |
| 34133 | /* 93904 */ // Label 2870: @93904 |
| 34134 | /* 93904 */ GIM_Try, /*On fail goto*//*Label 2891*/ GIMT_Encode4(93987), |
| 34135 | /* 93909 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 34136 | /* 93912 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34137 | /* 93915 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34138 | /* 93918 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 34139 | /* 93922 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34140 | /* 93926 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34141 | /* 93930 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34142 | /* 93934 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 34143 | /* 93938 */ GIM_Try, /*On fail goto*//*Label 2892*/ GIMT_Encode4(93962), // Rule ID 5573 // |
| 34144 | /* 93943 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34145 | /* 93947 */ // (intrinsic_void 4007:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRD64_rq_u MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34146 | /* 93947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq_u), |
| 34147 | /* 93950 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34148 | /* 93952 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34149 | /* 93954 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34150 | /* 93956 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34151 | /* 93960 */ GIR_RootConstrainSelectedInstOperands, |
| 34152 | /* 93961 */ // GIR_Coverage, 5573, |
| 34153 | /* 93961 */ GIR_EraseRootFromParent_Done, |
| 34154 | /* 93962 */ // Label 2892: @93962 |
| 34155 | /* 93962 */ GIM_Try, /*On fail goto*//*Label 2893*/ GIMT_Encode4(93986), // Rule ID 5574 // |
| 34156 | /* 93967 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 34157 | /* 93971 */ // (intrinsic_void 4007:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 3:{ *:[i32] }) => (MVE_VSTRD64_rq MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34158 | /* 93971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq), |
| 34159 | /* 93974 */ GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 34160 | /* 93976 */ GIR_RootToRootCopy, /*OpIdx*/1, // base |
| 34161 | /* 93978 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets |
| 34162 | /* 93980 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34163 | /* 93984 */ GIR_RootConstrainSelectedInstOperands, |
| 34164 | /* 93985 */ // GIR_Coverage, 5574, |
| 34165 | /* 93985 */ GIR_EraseRootFromParent_Done, |
| 34166 | /* 93986 */ // Label 2893: @93986 |
| 34167 | /* 93986 */ GIM_Reject, |
| 34168 | /* 93987 */ // Label 2891: @93987 |
| 34169 | /* 93987 */ GIM_Reject, |
| 34170 | /* 93988 */ // Label 2871: @93988 |
| 34171 | /* 93988 */ GIM_Reject, |
| 34172 | /* 93989 */ // Label 2866: @93989 |
| 34173 | /* 93989 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2894*/ GIMT_Encode4(94052), GIMT_Encode2(GIFBS_IsARM), // Rule ID 257 // |
| 34174 | /* 93996 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr), |
| 34175 | /* 94001 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 34176 | /* 94004 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34177 | /* 94007 */ // MIs[0] cop |
| 34178 | /* 94007 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34179 | /* 94010 */ // MIs[0] opc1 |
| 34180 | /* 94010 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34181 | /* 94013 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 34182 | /* 94017 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 34183 | /* 94021 */ // MIs[0] CRm |
| 34184 | /* 94021 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34185 | /* 94024 */ // (intrinsic_void 3792:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 34186 | /* 94024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR), |
| 34187 | /* 94027 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34188 | /* 94029 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34189 | /* 94031 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 34190 | /* 94033 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 34191 | /* 94035 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34192 | /* 94037 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34193 | /* 94040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34194 | /* 94046 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34195 | /* 94050 */ GIR_RootConstrainSelectedInstOperands, |
| 34196 | /* 94051 */ // GIR_Coverage, 257, |
| 34197 | /* 94051 */ GIR_EraseRootFromParent_Done, |
| 34198 | /* 94052 */ // Label 2894: @94052 |
| 34199 | /* 94052 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2895*/ GIMT_Encode4(94106), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 258 // |
| 34200 | /* 94059 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2), |
| 34201 | /* 94064 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 34202 | /* 94067 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34203 | /* 94070 */ // MIs[0] cop |
| 34204 | /* 94070 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34205 | /* 94073 */ // MIs[0] opc1 |
| 34206 | /* 94073 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34207 | /* 94076 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 34208 | /* 94080 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 34209 | /* 94084 */ // MIs[0] CRm |
| 34210 | /* 94084 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34211 | /* 94087 */ // (intrinsic_void 3793:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 34212 | /* 94087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR2), |
| 34213 | /* 94090 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34214 | /* 94092 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34215 | /* 94094 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 34216 | /* 94096 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 34217 | /* 94098 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34218 | /* 94100 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34219 | /* 94104 */ GIR_RootConstrainSelectedInstOperands, |
| 34220 | /* 94105 */ // GIR_Coverage, 258, |
| 34221 | /* 94105 */ GIR_EraseRootFromParent_Done, |
| 34222 | /* 94106 */ // Label 2895: @94106 |
| 34223 | /* 94106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2896*/ GIMT_Encode4(94169), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 595 // |
| 34224 | /* 94113 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr), |
| 34225 | /* 94118 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 34226 | /* 94121 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34227 | /* 94124 */ // MIs[0] cop |
| 34228 | /* 94124 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34229 | /* 94127 */ // MIs[0] opc1 |
| 34230 | /* 94127 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34231 | /* 94130 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34232 | /* 94134 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34233 | /* 94138 */ // MIs[0] CRm |
| 34234 | /* 94138 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34235 | /* 94141 */ // (intrinsic_void 3792:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 34236 | /* 94141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR), |
| 34237 | /* 94144 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34238 | /* 94146 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34239 | /* 94148 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 34240 | /* 94150 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 34241 | /* 94152 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34242 | /* 94154 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34243 | /* 94157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34244 | /* 94163 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34245 | /* 94167 */ GIR_RootConstrainSelectedInstOperands, |
| 34246 | /* 94168 */ // GIR_Coverage, 595, |
| 34247 | /* 94168 */ GIR_EraseRootFromParent_Done, |
| 34248 | /* 94169 */ // Label 2896: @94169 |
| 34249 | /* 94169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2897*/ GIMT_Encode4(94232), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 596 // |
| 34250 | /* 94176 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2), |
| 34251 | /* 94181 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 34252 | /* 94184 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34253 | /* 94187 */ // MIs[0] cop |
| 34254 | /* 94187 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34255 | /* 94190 */ // MIs[0] opc1 |
| 34256 | /* 94190 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34257 | /* 94193 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34258 | /* 94197 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34259 | /* 94201 */ // MIs[0] CRm |
| 34260 | /* 94201 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34261 | /* 94204 */ // (intrinsic_void 3793:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) |
| 34262 | /* 94204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR2), |
| 34263 | /* 94207 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34264 | /* 94209 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34265 | /* 94211 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 34266 | /* 94213 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2 |
| 34267 | /* 94215 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34268 | /* 94217 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34269 | /* 94220 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34270 | /* 94226 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34271 | /* 94230 */ GIR_RootConstrainSelectedInstOperands, |
| 34272 | /* 94231 */ // GIR_Coverage, 596, |
| 34273 | /* 94231 */ GIR_EraseRootFromParent_Done, |
| 34274 | /* 94232 */ // Label 2897: @94232 |
| 34275 | /* 94232 */ GIM_Reject, |
| 34276 | /* 94233 */ // Label 2865: @94233 |
| 34277 | /* 94233 */ GIM_Try, /*On fail goto*//*Label 2898*/ GIMT_Encode4(96138), |
| 34278 | /* 94238 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, |
| 34279 | /* 94241 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2899*/ GIMT_Encode4(94301), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 245 // |
| 34280 | /* 94248 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp), |
| 34281 | /* 94253 */ // MIs[0] cop |
| 34282 | /* 94253 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34283 | /* 94256 */ // MIs[0] opc1 |
| 34284 | /* 94256 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34285 | /* 94259 */ // MIs[0] CRd |
| 34286 | /* 94259 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 34287 | /* 94262 */ // MIs[0] CRn |
| 34288 | /* 94262 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 34289 | /* 94265 */ // MIs[0] CRm |
| 34290 | /* 94265 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34291 | /* 94268 */ // MIs[0] opc2 |
| 34292 | /* 94268 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 34293 | /* 94271 */ // (intrinsic_void 3760:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 34294 | /* 94271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP), |
| 34295 | /* 94274 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34296 | /* 94276 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34297 | /* 94278 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 34298 | /* 94280 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 34299 | /* 94282 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34300 | /* 94284 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 34301 | /* 94286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34302 | /* 94289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34303 | /* 94295 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34304 | /* 94299 */ GIR_RootConstrainSelectedInstOperands, |
| 34305 | /* 94300 */ // GIR_Coverage, 245, |
| 34306 | /* 94300 */ GIR_EraseRootFromParent_Done, |
| 34307 | /* 94301 */ // Label 2899: @94301 |
| 34308 | /* 94301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2900*/ GIMT_Encode4(94352), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 246 // |
| 34309 | /* 94308 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2), |
| 34310 | /* 94313 */ // MIs[0] cop |
| 34311 | /* 94313 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34312 | /* 94316 */ // MIs[0] opc1 |
| 34313 | /* 94316 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34314 | /* 94319 */ // MIs[0] CRd |
| 34315 | /* 94319 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 34316 | /* 94322 */ // MIs[0] CRn |
| 34317 | /* 94322 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 34318 | /* 94325 */ // MIs[0] CRm |
| 34319 | /* 94325 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34320 | /* 94328 */ // MIs[0] opc2 |
| 34321 | /* 94328 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 34322 | /* 94331 */ // (intrinsic_void 3761:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 34323 | /* 94331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP2), |
| 34324 | /* 94334 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34325 | /* 94336 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34326 | /* 94338 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 34327 | /* 94340 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 34328 | /* 94342 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34329 | /* 94344 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 34330 | /* 94346 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34331 | /* 94350 */ GIR_RootConstrainSelectedInstOperands, |
| 34332 | /* 94351 */ // GIR_Coverage, 246, |
| 34333 | /* 94351 */ GIR_EraseRootFromParent_Done, |
| 34334 | /* 94352 */ // Label 2900: @94352 |
| 34335 | /* 94352 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2901*/ GIMT_Encode4(94412), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 597 // |
| 34336 | /* 94359 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp), |
| 34337 | /* 94364 */ // MIs[0] cop |
| 34338 | /* 94364 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34339 | /* 94367 */ // MIs[0] opc1 |
| 34340 | /* 94367 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34341 | /* 94370 */ // MIs[0] CRd |
| 34342 | /* 94370 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 34343 | /* 94373 */ // MIs[0] CRn |
| 34344 | /* 94373 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 34345 | /* 94376 */ // MIs[0] CRm |
| 34346 | /* 94376 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34347 | /* 94379 */ // MIs[0] opc2 |
| 34348 | /* 94379 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 34349 | /* 94382 */ // (intrinsic_void 3760:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 34350 | /* 94382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP), |
| 34351 | /* 94385 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34352 | /* 94387 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34353 | /* 94389 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 34354 | /* 94391 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 34355 | /* 94393 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34356 | /* 94395 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 34357 | /* 94397 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34358 | /* 94400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34359 | /* 94406 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34360 | /* 94410 */ GIR_RootConstrainSelectedInstOperands, |
| 34361 | /* 94411 */ // GIR_Coverage, 597, |
| 34362 | /* 94411 */ GIR_EraseRootFromParent_Done, |
| 34363 | /* 94412 */ // Label 2901: @94412 |
| 34364 | /* 94412 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2902*/ GIMT_Encode4(94472), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 598 // |
| 34365 | /* 94419 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2), |
| 34366 | /* 94424 */ // MIs[0] cop |
| 34367 | /* 94424 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 34368 | /* 94427 */ // MIs[0] opc1 |
| 34369 | /* 94427 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 34370 | /* 94430 */ // MIs[0] CRd |
| 34371 | /* 94430 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 34372 | /* 94433 */ // MIs[0] CRn |
| 34373 | /* 94433 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 34374 | /* 94436 */ // MIs[0] CRm |
| 34375 | /* 94436 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 34376 | /* 94439 */ // MIs[0] opc2 |
| 34377 | /* 94439 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 34378 | /* 94442 */ // (intrinsic_void 3761:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 34379 | /* 94442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP2), |
| 34380 | /* 94445 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 34381 | /* 94447 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 34382 | /* 94449 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd |
| 34383 | /* 94451 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 34384 | /* 94453 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 34385 | /* 94455 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 34386 | /* 94457 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 34387 | /* 94460 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 34388 | /* 94466 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34389 | /* 94470 */ GIR_RootConstrainSelectedInstOperands, |
| 34390 | /* 94471 */ // GIR_Coverage, 598, |
| 34391 | /* 94471 */ GIR_EraseRootFromParent_Done, |
| 34392 | /* 94472 */ // Label 2902: @94472 |
| 34393 | /* 94472 */ GIM_Try, /*On fail goto*//*Label 2903*/ GIMT_Encode4(95890), |
| 34394 | /* 94477 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset), |
| 34395 | /* 94482 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 2908*/ GIMT_Encode4(95889), |
| 34396 | /* 94493 */ /*GILLT_v16s8*//*Label 2904*/ GIMT_Encode4(94517), GIMT_Encode4(0), |
| 34397 | /* 94501 */ /*GILLT_v8s16*//*Label 2905*/ GIMT_Encode4(94608), GIMT_Encode4(0), |
| 34398 | /* 94509 */ /*GILLT_v4s32*//*Label 2906*/ GIMT_Encode4(95061), |
| 34399 | /* 94513 */ /*GILLT_v2s64*//*Label 2907*/ GIMT_Encode4(95626), |
| 34400 | /* 94517 */ // Label 2904: @94517 |
| 34401 | /* 94517 */ GIM_Try, /*On fail goto*//*Label 2909*/ GIMT_Encode4(94607), |
| 34402 | /* 94522 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8, |
| 34403 | /* 94525 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34404 | /* 94528 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34405 | /* 94531 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34406 | /* 94534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34407 | /* 94538 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34408 | /* 94542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34409 | /* 94546 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34410 | /* 94550 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34411 | /* 94554 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34412 | /* 94558 */ GIM_Try, /*On fail goto*//*Label 2910*/ GIMT_Encode4(94582), // Rule ID 5467 // |
| 34413 | /* 94563 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34414 | /* 94567 */ // (intrinsic_w_chain:{ *:[v16i8] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) |
| 34415 | /* 94567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq), |
| 34416 | /* 94570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34417 | /* 94572 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34418 | /* 94574 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34419 | /* 94576 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34420 | /* 94580 */ GIR_RootConstrainSelectedInstOperands, |
| 34421 | /* 94581 */ // GIR_Coverage, 5467, |
| 34422 | /* 94581 */ GIR_EraseRootFromParent_Done, |
| 34423 | /* 94582 */ // Label 2910: @94582 |
| 34424 | /* 94582 */ GIM_Try, /*On fail goto*//*Label 2911*/ GIMT_Encode4(94606), // Rule ID 5475 // |
| 34425 | /* 94587 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34426 | /* 94591 */ // (intrinsic_w_chain:{ *:[v16i8] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets) |
| 34427 | /* 94591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq), |
| 34428 | /* 94594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34429 | /* 94596 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34430 | /* 94598 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34431 | /* 94600 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34432 | /* 94604 */ GIR_RootConstrainSelectedInstOperands, |
| 34433 | /* 94605 */ // GIR_Coverage, 5475, |
| 34434 | /* 94605 */ GIR_EraseRootFromParent_Done, |
| 34435 | /* 94606 */ // Label 2911: @94606 |
| 34436 | /* 94606 */ GIM_Reject, |
| 34437 | /* 94607 */ // Label 2909: @94607 |
| 34438 | /* 94607 */ GIM_Reject, |
| 34439 | /* 94608 */ // Label 2905: @94608 |
| 34440 | /* 94608 */ GIM_Try, /*On fail goto*//*Label 2912*/ GIMT_Encode4(95060), |
| 34441 | /* 94613 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 34442 | /* 94616 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34443 | /* 94619 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34444 | /* 94622 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34445 | /* 94625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34446 | /* 94629 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34447 | /* 94633 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34448 | /* 94637 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34449 | /* 94641 */ GIM_Try, /*On fail goto*//*Label 2913*/ GIMT_Encode4(94707), |
| 34450 | /* 94646 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34451 | /* 94650 */ GIM_Try, /*On fail goto*//*Label 2914*/ GIMT_Encode4(94678), // Rule ID 5463 // |
| 34452 | /* 94655 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34453 | /* 94659 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34454 | /* 94663 */ // (intrinsic_w_chain:{ *:[v8i16] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34455 | /* 94663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34456 | /* 94666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34457 | /* 94668 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34458 | /* 94670 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34459 | /* 94672 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34460 | /* 94676 */ GIR_RootConstrainSelectedInstOperands, |
| 34461 | /* 94677 */ // GIR_Coverage, 5463, |
| 34462 | /* 94677 */ GIR_EraseRootFromParent_Done, |
| 34463 | /* 94678 */ // Label 2914: @94678 |
| 34464 | /* 94678 */ GIM_Try, /*On fail goto*//*Label 2915*/ GIMT_Encode4(94706), // Rule ID 5464 // |
| 34465 | /* 94683 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34466 | /* 94687 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34467 | /* 94691 */ // (intrinsic_w_chain:{ *:[v8i16] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34468 | /* 94691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34469 | /* 94694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34470 | /* 94696 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34471 | /* 94698 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34472 | /* 94700 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34473 | /* 94704 */ GIR_RootConstrainSelectedInstOperands, |
| 34474 | /* 94705 */ // GIR_Coverage, 5464, |
| 34475 | /* 94705 */ GIR_EraseRootFromParent_Done, |
| 34476 | /* 94706 */ // Label 2915: @94706 |
| 34477 | /* 94706 */ GIM_Reject, |
| 34478 | /* 94707 */ // Label 2913: @94707 |
| 34479 | /* 94707 */ GIM_Try, /*On fail goto*//*Label 2916*/ GIMT_Encode4(94769), |
| 34480 | /* 94712 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34481 | /* 94716 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34482 | /* 94720 */ GIM_Try, /*On fail goto*//*Label 2917*/ GIMT_Encode4(94744), // Rule ID 5477 // |
| 34483 | /* 94725 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34484 | /* 94729 */ // (intrinsic_w_chain:{ *:[v8i16] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34485 | /* 94729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU16_rq), |
| 34486 | /* 94732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34487 | /* 94734 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34488 | /* 94736 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34489 | /* 94738 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34490 | /* 94742 */ GIR_RootConstrainSelectedInstOperands, |
| 34491 | /* 94743 */ // GIR_Coverage, 5477, |
| 34492 | /* 94743 */ GIR_EraseRootFromParent_Done, |
| 34493 | /* 94744 */ // Label 2917: @94744 |
| 34494 | /* 94744 */ GIM_Try, /*On fail goto*//*Label 2918*/ GIMT_Encode4(94768), // Rule ID 5479 // |
| 34495 | /* 94749 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34496 | /* 94753 */ // (intrinsic_w_chain:{ *:[v8i16] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34497 | /* 94753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS16_rq), |
| 34498 | /* 94756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34499 | /* 94758 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34500 | /* 94760 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34501 | /* 94762 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34502 | /* 94766 */ GIR_RootConstrainSelectedInstOperands, |
| 34503 | /* 94767 */ // GIR_Coverage, 5479, |
| 34504 | /* 94767 */ GIR_EraseRootFromParent_Done, |
| 34505 | /* 94768 */ // Label 2918: @94768 |
| 34506 | /* 94768 */ GIM_Reject, |
| 34507 | /* 94769 */ // Label 2916: @94769 |
| 34508 | /* 94769 */ GIM_Try, /*On fail goto*//*Label 2919*/ GIMT_Encode4(95059), |
| 34509 | /* 94774 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34510 | /* 94778 */ GIM_Try, /*On fail goto*//*Label 2920*/ GIMT_Encode4(94806), // Rule ID 5485 // |
| 34511 | /* 94783 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34512 | /* 94787 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34513 | /* 94791 */ // (intrinsic_w_chain:{ *:[v8i16] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34514 | /* 94791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34515 | /* 94794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34516 | /* 94796 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34517 | /* 94798 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34518 | /* 94800 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34519 | /* 94804 */ GIR_RootConstrainSelectedInstOperands, |
| 34520 | /* 94805 */ // GIR_Coverage, 5485, |
| 34521 | /* 94805 */ GIR_EraseRootFromParent_Done, |
| 34522 | /* 94806 */ // Label 2920: @94806 |
| 34523 | /* 94806 */ GIM_Try, /*On fail goto*//*Label 2921*/ GIMT_Encode4(94834), // Rule ID 5486 // |
| 34524 | /* 94811 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34525 | /* 94815 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34526 | /* 94819 */ // (intrinsic_w_chain:{ *:[v8i16] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34527 | /* 94819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34528 | /* 94822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34529 | /* 94824 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34530 | /* 94826 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34531 | /* 94828 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34532 | /* 94832 */ GIR_RootConstrainSelectedInstOperands, |
| 34533 | /* 94833 */ // GIR_Coverage, 5486, |
| 34534 | /* 94833 */ GIR_EraseRootFromParent_Done, |
| 34535 | /* 94834 */ // Label 2921: @94834 |
| 34536 | /* 94834 */ GIM_Try, /*On fail goto*//*Label 2922*/ GIMT_Encode4(94862), // Rule ID 5489 // |
| 34537 | /* 94839 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34538 | /* 94843 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34539 | /* 94847 */ // (intrinsic_w_chain:{ *:[v8i16] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34540 | /* 94847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34541 | /* 94850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34542 | /* 94852 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34543 | /* 94854 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34544 | /* 94856 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34545 | /* 94860 */ GIR_RootConstrainSelectedInstOperands, |
| 34546 | /* 94861 */ // GIR_Coverage, 5489, |
| 34547 | /* 94861 */ GIR_EraseRootFromParent_Done, |
| 34548 | /* 94862 */ // Label 2922: @94862 |
| 34549 | /* 94862 */ GIM_Try, /*On fail goto*//*Label 2923*/ GIMT_Encode4(94890), // Rule ID 5490 // |
| 34550 | /* 94867 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34551 | /* 94871 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34552 | /* 94875 */ // (intrinsic_w_chain:{ *:[v8i16] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34553 | /* 94875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34554 | /* 94878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34555 | /* 94880 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34556 | /* 94882 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34557 | /* 94884 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34558 | /* 94888 */ GIR_RootConstrainSelectedInstOperands, |
| 34559 | /* 94889 */ // GIR_Coverage, 5490, |
| 34560 | /* 94889 */ GIR_EraseRootFromParent_Done, |
| 34561 | /* 94890 */ // Label 2923: @94890 |
| 34562 | /* 94890 */ GIM_Try, /*On fail goto*//*Label 2924*/ GIMT_Encode4(94918), // Rule ID 5493 // |
| 34563 | /* 94895 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34564 | /* 94899 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34565 | /* 94903 */ // (intrinsic_w_chain:{ *:[v8i16] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34566 | /* 94903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34567 | /* 94906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34568 | /* 94908 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34569 | /* 94910 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34570 | /* 94912 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34571 | /* 94916 */ GIR_RootConstrainSelectedInstOperands, |
| 34572 | /* 94917 */ // GIR_Coverage, 5493, |
| 34573 | /* 94917 */ GIR_EraseRootFromParent_Done, |
| 34574 | /* 94918 */ // Label 2924: @94918 |
| 34575 | /* 94918 */ GIM_Try, /*On fail goto*//*Label 2925*/ GIMT_Encode4(94946), // Rule ID 5494 // |
| 34576 | /* 94923 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34577 | /* 94927 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34578 | /* 94931 */ // (intrinsic_w_chain:{ *:[v8i16] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34579 | /* 94931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34580 | /* 94934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34581 | /* 94936 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34582 | /* 94938 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34583 | /* 94940 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34584 | /* 94944 */ GIR_RootConstrainSelectedInstOperands, |
| 34585 | /* 94945 */ // GIR_Coverage, 5494, |
| 34586 | /* 94945 */ GIR_EraseRootFromParent_Done, |
| 34587 | /* 94946 */ // Label 2925: @94946 |
| 34588 | /* 94946 */ GIM_Try, /*On fail goto*//*Label 2926*/ GIMT_Encode4(94974), // Rule ID 5497 // |
| 34589 | /* 94951 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34590 | /* 94955 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34591 | /* 94959 */ // (intrinsic_w_chain:{ *:[v8f16] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34592 | /* 94959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34593 | /* 94962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34594 | /* 94964 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34595 | /* 94966 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34596 | /* 94968 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34597 | /* 94972 */ GIR_RootConstrainSelectedInstOperands, |
| 34598 | /* 94973 */ // GIR_Coverage, 5497, |
| 34599 | /* 94973 */ GIR_EraseRootFromParent_Done, |
| 34600 | /* 94974 */ // Label 2926: @94974 |
| 34601 | /* 94974 */ GIM_Try, /*On fail goto*//*Label 2927*/ GIMT_Encode4(95002), // Rule ID 5498 // |
| 34602 | /* 94979 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34603 | /* 94983 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34604 | /* 94987 */ // (intrinsic_w_chain:{ *:[v8f16] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34605 | /* 94987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34606 | /* 94990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34607 | /* 94992 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34608 | /* 94994 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34609 | /* 94996 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34610 | /* 95000 */ GIR_RootConstrainSelectedInstOperands, |
| 34611 | /* 95001 */ // GIR_Coverage, 5498, |
| 34612 | /* 95001 */ GIR_EraseRootFromParent_Done, |
| 34613 | /* 95002 */ // Label 2927: @95002 |
| 34614 | /* 95002 */ GIM_Try, /*On fail goto*//*Label 2928*/ GIMT_Encode4(95030), // Rule ID 5501 // |
| 34615 | /* 95007 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34616 | /* 95011 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34617 | /* 95015 */ // (intrinsic_w_chain:{ *:[v8f16] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34618 | /* 95015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u), |
| 34619 | /* 95018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34620 | /* 95020 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34621 | /* 95022 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34622 | /* 95024 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34623 | /* 95028 */ GIR_RootConstrainSelectedInstOperands, |
| 34624 | /* 95029 */ // GIR_Coverage, 5501, |
| 34625 | /* 95029 */ GIR_EraseRootFromParent_Done, |
| 34626 | /* 95030 */ // Label 2928: @95030 |
| 34627 | /* 95030 */ GIM_Try, /*On fail goto*//*Label 2929*/ GIMT_Encode4(95058), // Rule ID 5502 // |
| 34628 | /* 95035 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34629 | /* 95039 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34630 | /* 95043 */ // (intrinsic_w_chain:{ *:[v8f16] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets) |
| 34631 | /* 95043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq), |
| 34632 | /* 95046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34633 | /* 95048 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34634 | /* 95050 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34635 | /* 95052 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34636 | /* 95056 */ GIR_RootConstrainSelectedInstOperands, |
| 34637 | /* 95057 */ // GIR_Coverage, 5502, |
| 34638 | /* 95057 */ GIR_EraseRootFromParent_Done, |
| 34639 | /* 95058 */ // Label 2929: @95058 |
| 34640 | /* 95058 */ GIM_Reject, |
| 34641 | /* 95059 */ // Label 2919: @95059 |
| 34642 | /* 95059 */ GIM_Reject, |
| 34643 | /* 95060 */ // Label 2912: @95060 |
| 34644 | /* 95060 */ GIM_Reject, |
| 34645 | /* 95061 */ // Label 2906: @95061 |
| 34646 | /* 95061 */ GIM_Try, /*On fail goto*//*Label 2930*/ GIMT_Encode4(95625), |
| 34647 | /* 95066 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 34648 | /* 95069 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34649 | /* 95072 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34650 | /* 95075 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34651 | /* 95078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34652 | /* 95082 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34653 | /* 95086 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34654 | /* 95090 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34655 | /* 95094 */ GIM_Try, /*On fail goto*//*Label 2931*/ GIMT_Encode4(95156), |
| 34656 | /* 95099 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8, |
| 34657 | /* 95103 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34658 | /* 95107 */ GIM_Try, /*On fail goto*//*Label 2932*/ GIMT_Encode4(95131), // Rule ID 5481 // |
| 34659 | /* 95112 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34660 | /* 95116 */ // (intrinsic_w_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34661 | /* 95116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU32_rq), |
| 34662 | /* 95119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34663 | /* 95121 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34664 | /* 95123 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34665 | /* 95125 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34666 | /* 95129 */ GIR_RootConstrainSelectedInstOperands, |
| 34667 | /* 95130 */ // GIR_Coverage, 5481, |
| 34668 | /* 95130 */ GIR_EraseRootFromParent_Done, |
| 34669 | /* 95131 */ // Label 2932: @95131 |
| 34670 | /* 95131 */ GIM_Try, /*On fail goto*//*Label 2933*/ GIMT_Encode4(95155), // Rule ID 5483 // |
| 34671 | /* 95136 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34672 | /* 95140 */ // (intrinsic_w_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34673 | /* 95140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS32_rq), |
| 34674 | /* 95143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34675 | /* 95145 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34676 | /* 95147 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34677 | /* 95149 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34678 | /* 95153 */ GIR_RootConstrainSelectedInstOperands, |
| 34679 | /* 95154 */ // GIR_Coverage, 5483, |
| 34680 | /* 95154 */ GIR_EraseRootFromParent_Done, |
| 34681 | /* 95155 */ // Label 2933: @95155 |
| 34682 | /* 95155 */ GIM_Reject, |
| 34683 | /* 95156 */ // Label 2931: @95156 |
| 34684 | /* 95156 */ GIM_Try, /*On fail goto*//*Label 2934*/ GIMT_Encode4(95278), |
| 34685 | /* 95161 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16, |
| 34686 | /* 95165 */ GIM_Try, /*On fail goto*//*Label 2935*/ GIMT_Encode4(95193), // Rule ID 5505 // |
| 34687 | /* 95170 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34688 | /* 95174 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34689 | /* 95178 */ // (intrinsic_w_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34690 | /* 95178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq_u), |
| 34691 | /* 95181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34692 | /* 95183 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34693 | /* 95185 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34694 | /* 95187 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34695 | /* 95191 */ GIR_RootConstrainSelectedInstOperands, |
| 34696 | /* 95192 */ // GIR_Coverage, 5505, |
| 34697 | /* 95192 */ GIR_EraseRootFromParent_Done, |
| 34698 | /* 95193 */ // Label 2935: @95193 |
| 34699 | /* 95193 */ GIM_Try, /*On fail goto*//*Label 2936*/ GIMT_Encode4(95221), // Rule ID 5506 // |
| 34700 | /* 95198 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34701 | /* 95202 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34702 | /* 95206 */ // (intrinsic_w_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34703 | /* 95206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq), |
| 34704 | /* 95209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34705 | /* 95211 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34706 | /* 95213 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34707 | /* 95215 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34708 | /* 95219 */ GIR_RootConstrainSelectedInstOperands, |
| 34709 | /* 95220 */ // GIR_Coverage, 5506, |
| 34710 | /* 95220 */ GIR_EraseRootFromParent_Done, |
| 34711 | /* 95221 */ // Label 2936: @95221 |
| 34712 | /* 95221 */ GIM_Try, /*On fail goto*//*Label 2937*/ GIMT_Encode4(95249), // Rule ID 5509 // |
| 34713 | /* 95226 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34714 | /* 95230 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34715 | /* 95234 */ // (intrinsic_w_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34716 | /* 95234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq_u), |
| 34717 | /* 95237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34718 | /* 95239 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34719 | /* 95241 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34720 | /* 95243 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34721 | /* 95247 */ GIR_RootConstrainSelectedInstOperands, |
| 34722 | /* 95248 */ // GIR_Coverage, 5509, |
| 34723 | /* 95248 */ GIR_EraseRootFromParent_Done, |
| 34724 | /* 95249 */ // Label 2937: @95249 |
| 34725 | /* 95249 */ GIM_Try, /*On fail goto*//*Label 2938*/ GIMT_Encode4(95277), // Rule ID 5510 // |
| 34726 | /* 95254 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1, |
| 34727 | /* 95258 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34728 | /* 95262 */ // (intrinsic_w_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34729 | /* 95262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq), |
| 34730 | /* 95265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34731 | /* 95267 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34732 | /* 95269 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34733 | /* 95271 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34734 | /* 95275 */ GIR_RootConstrainSelectedInstOperands, |
| 34735 | /* 95276 */ // GIR_Coverage, 5510, |
| 34736 | /* 95276 */ GIR_EraseRootFromParent_Done, |
| 34737 | /* 95277 */ // Label 2938: @95277 |
| 34738 | /* 95277 */ GIM_Reject, |
| 34739 | /* 95278 */ // Label 2934: @95278 |
| 34740 | /* 95278 */ GIM_Try, /*On fail goto*//*Label 2939*/ GIMT_Encode4(95624), |
| 34741 | /* 95283 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32, |
| 34742 | /* 95287 */ GIM_Try, /*On fail goto*//*Label 2940*/ GIMT_Encode4(95315), // Rule ID 5513 // |
| 34743 | /* 95292 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34744 | /* 95296 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34745 | /* 95300 */ // (intrinsic_w_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34746 | /* 95300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34747 | /* 95303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34748 | /* 95305 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34749 | /* 95307 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34750 | /* 95309 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34751 | /* 95313 */ GIR_RootConstrainSelectedInstOperands, |
| 34752 | /* 95314 */ // GIR_Coverage, 5513, |
| 34753 | /* 95314 */ GIR_EraseRootFromParent_Done, |
| 34754 | /* 95315 */ // Label 2940: @95315 |
| 34755 | /* 95315 */ GIM_Try, /*On fail goto*//*Label 2941*/ GIMT_Encode4(95343), // Rule ID 5514 // |
| 34756 | /* 95320 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34757 | /* 95324 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34758 | /* 95328 */ // (intrinsic_w_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34759 | /* 95328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34760 | /* 95331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34761 | /* 95333 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34762 | /* 95335 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34763 | /* 95337 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34764 | /* 95341 */ GIR_RootConstrainSelectedInstOperands, |
| 34765 | /* 95342 */ // GIR_Coverage, 5514, |
| 34766 | /* 95342 */ GIR_EraseRootFromParent_Done, |
| 34767 | /* 95343 */ // Label 2941: @95343 |
| 34768 | /* 95343 */ GIM_Try, /*On fail goto*//*Label 2942*/ GIMT_Encode4(95371), // Rule ID 5517 // |
| 34769 | /* 95348 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34770 | /* 95352 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34771 | /* 95356 */ // (intrinsic_w_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34772 | /* 95356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34773 | /* 95359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34774 | /* 95361 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34775 | /* 95363 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34776 | /* 95365 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34777 | /* 95369 */ GIR_RootConstrainSelectedInstOperands, |
| 34778 | /* 95370 */ // GIR_Coverage, 5517, |
| 34779 | /* 95370 */ GIR_EraseRootFromParent_Done, |
| 34780 | /* 95371 */ // Label 2942: @95371 |
| 34781 | /* 95371 */ GIM_Try, /*On fail goto*//*Label 2943*/ GIMT_Encode4(95399), // Rule ID 5518 // |
| 34782 | /* 95376 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34783 | /* 95380 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34784 | /* 95384 */ // (intrinsic_w_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34785 | /* 95384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34786 | /* 95387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34787 | /* 95389 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34788 | /* 95391 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34789 | /* 95393 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34790 | /* 95397 */ GIR_RootConstrainSelectedInstOperands, |
| 34791 | /* 95398 */ // GIR_Coverage, 5518, |
| 34792 | /* 95398 */ GIR_EraseRootFromParent_Done, |
| 34793 | /* 95399 */ // Label 2943: @95399 |
| 34794 | /* 95399 */ GIM_Try, /*On fail goto*//*Label 2944*/ GIMT_Encode4(95427), // Rule ID 5521 // |
| 34795 | /* 95404 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34796 | /* 95408 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34797 | /* 95412 */ // (intrinsic_w_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34798 | /* 95412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34799 | /* 95415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34800 | /* 95417 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34801 | /* 95419 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34802 | /* 95421 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34803 | /* 95425 */ GIR_RootConstrainSelectedInstOperands, |
| 34804 | /* 95426 */ // GIR_Coverage, 5521, |
| 34805 | /* 95426 */ GIR_EraseRootFromParent_Done, |
| 34806 | /* 95427 */ // Label 2944: @95427 |
| 34807 | /* 95427 */ GIM_Try, /*On fail goto*//*Label 2945*/ GIMT_Encode4(95455), // Rule ID 5522 // |
| 34808 | /* 95432 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34809 | /* 95436 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34810 | /* 95440 */ // (intrinsic_w_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34811 | /* 95440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34812 | /* 95443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34813 | /* 95445 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34814 | /* 95447 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34815 | /* 95449 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34816 | /* 95453 */ GIR_RootConstrainSelectedInstOperands, |
| 34817 | /* 95454 */ // GIR_Coverage, 5522, |
| 34818 | /* 95454 */ GIR_EraseRootFromParent_Done, |
| 34819 | /* 95455 */ // Label 2945: @95455 |
| 34820 | /* 95455 */ GIM_Try, /*On fail goto*//*Label 2946*/ GIMT_Encode4(95483), // Rule ID 5525 // |
| 34821 | /* 95460 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34822 | /* 95464 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34823 | /* 95468 */ // (intrinsic_w_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34824 | /* 95468 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34825 | /* 95471 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34826 | /* 95473 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34827 | /* 95475 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34828 | /* 95477 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34829 | /* 95481 */ GIR_RootConstrainSelectedInstOperands, |
| 34830 | /* 95482 */ // GIR_Coverage, 5525, |
| 34831 | /* 95482 */ GIR_EraseRootFromParent_Done, |
| 34832 | /* 95483 */ // Label 2946: @95483 |
| 34833 | /* 95483 */ GIM_Try, /*On fail goto*//*Label 2947*/ GIMT_Encode4(95511), // Rule ID 5526 // |
| 34834 | /* 95488 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34835 | /* 95492 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34836 | /* 95496 */ // (intrinsic_w_chain:{ *:[v4i32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34837 | /* 95496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34838 | /* 95499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34839 | /* 95501 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34840 | /* 95503 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34841 | /* 95505 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34842 | /* 95509 */ GIR_RootConstrainSelectedInstOperands, |
| 34843 | /* 95510 */ // GIR_Coverage, 5526, |
| 34844 | /* 95510 */ GIR_EraseRootFromParent_Done, |
| 34845 | /* 95511 */ // Label 2947: @95511 |
| 34846 | /* 95511 */ GIM_Try, /*On fail goto*//*Label 2948*/ GIMT_Encode4(95539), // Rule ID 5529 // |
| 34847 | /* 95516 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34848 | /* 95520 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34849 | /* 95524 */ // (intrinsic_w_chain:{ *:[v4f32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34850 | /* 95524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34851 | /* 95527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34852 | /* 95529 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34853 | /* 95531 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34854 | /* 95533 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34855 | /* 95537 */ GIR_RootConstrainSelectedInstOperands, |
| 34856 | /* 95538 */ // GIR_Coverage, 5529, |
| 34857 | /* 95538 */ GIR_EraseRootFromParent_Done, |
| 34858 | /* 95539 */ // Label 2948: @95539 |
| 34859 | /* 95539 */ GIM_Try, /*On fail goto*//*Label 2949*/ GIMT_Encode4(95567), // Rule ID 5530 // |
| 34860 | /* 95544 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34861 | /* 95548 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34862 | /* 95552 */ // (intrinsic_w_chain:{ *:[v4f32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34863 | /* 95552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34864 | /* 95555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34865 | /* 95557 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34866 | /* 95559 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34867 | /* 95561 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34868 | /* 95565 */ GIR_RootConstrainSelectedInstOperands, |
| 34869 | /* 95566 */ // GIR_Coverage, 5530, |
| 34870 | /* 95566 */ GIR_EraseRootFromParent_Done, |
| 34871 | /* 95567 */ // Label 2949: @95567 |
| 34872 | /* 95567 */ GIM_Try, /*On fail goto*//*Label 2950*/ GIMT_Encode4(95595), // Rule ID 5533 // |
| 34873 | /* 95572 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34874 | /* 95576 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34875 | /* 95580 */ // (intrinsic_w_chain:{ *:[v4f32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34876 | /* 95580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u), |
| 34877 | /* 95583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34878 | /* 95585 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34879 | /* 95587 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34880 | /* 95589 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34881 | /* 95593 */ GIR_RootConstrainSelectedInstOperands, |
| 34882 | /* 95594 */ // GIR_Coverage, 5533, |
| 34883 | /* 95594 */ GIR_EraseRootFromParent_Done, |
| 34884 | /* 95595 */ // Label 2950: @95595 |
| 34885 | /* 95595 */ GIM_Try, /*On fail goto*//*Label 2951*/ GIMT_Encode4(95623), // Rule ID 5534 // |
| 34886 | /* 95600 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2, |
| 34887 | /* 95604 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34888 | /* 95608 */ // (intrinsic_w_chain:{ *:[v4f32] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets) |
| 34889 | /* 95608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq), |
| 34890 | /* 95611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34891 | /* 95613 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34892 | /* 95615 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34893 | /* 95617 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34894 | /* 95621 */ GIR_RootConstrainSelectedInstOperands, |
| 34895 | /* 95622 */ // GIR_Coverage, 5534, |
| 34896 | /* 95622 */ GIR_EraseRootFromParent_Done, |
| 34897 | /* 95623 */ // Label 2951: @95623 |
| 34898 | /* 95623 */ GIM_Reject, |
| 34899 | /* 95624 */ // Label 2939: @95624 |
| 34900 | /* 95624 */ GIM_Reject, |
| 34901 | /* 95625 */ // Label 2930: @95625 |
| 34902 | /* 95625 */ GIM_Reject, |
| 34903 | /* 95626 */ // Label 2907: @95626 |
| 34904 | /* 95626 */ GIM_Try, /*On fail goto*//*Label 2952*/ GIMT_Encode4(95888), |
| 34905 | /* 95631 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64, |
| 34906 | /* 95634 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 34907 | /* 95637 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 34908 | /* 95640 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 34909 | /* 95643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34910 | /* 95647 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, |
| 34911 | /* 95651 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 34912 | /* 95655 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 34913 | /* 95659 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64, |
| 34914 | /* 95663 */ GIM_Try, /*On fail goto*//*Label 2953*/ GIMT_Encode4(95691), // Rule ID 5537 // |
| 34915 | /* 95668 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34916 | /* 95672 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34917 | /* 95676 */ // (intrinsic_w_chain:{ *:[v2i64] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34918 | /* 95676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 34919 | /* 95679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34920 | /* 95681 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34921 | /* 95683 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34922 | /* 95685 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34923 | /* 95689 */ GIR_RootConstrainSelectedInstOperands, |
| 34924 | /* 95690 */ // GIR_Coverage, 5537, |
| 34925 | /* 95690 */ GIR_EraseRootFromParent_Done, |
| 34926 | /* 95691 */ // Label 2953: @95691 |
| 34927 | /* 95691 */ GIM_Try, /*On fail goto*//*Label 2954*/ GIMT_Encode4(95719), // Rule ID 5538 // |
| 34928 | /* 95696 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 34929 | /* 95700 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34930 | /* 95704 */ // (intrinsic_w_chain:{ *:[v2i64] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34931 | /* 95704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 34932 | /* 95707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34933 | /* 95709 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34934 | /* 95711 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34935 | /* 95713 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34936 | /* 95717 */ GIR_RootConstrainSelectedInstOperands, |
| 34937 | /* 95718 */ // GIR_Coverage, 5538, |
| 34938 | /* 95718 */ GIR_EraseRootFromParent_Done, |
| 34939 | /* 95719 */ // Label 2954: @95719 |
| 34940 | /* 95719 */ GIM_Try, /*On fail goto*//*Label 2955*/ GIMT_Encode4(95747), // Rule ID 5541 // |
| 34941 | /* 95724 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34942 | /* 95728 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34943 | /* 95732 */ // (intrinsic_w_chain:{ *:[v2i64] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34944 | /* 95732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 34945 | /* 95735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34946 | /* 95737 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34947 | /* 95739 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34948 | /* 95741 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34949 | /* 95745 */ GIR_RootConstrainSelectedInstOperands, |
| 34950 | /* 95746 */ // GIR_Coverage, 5541, |
| 34951 | /* 95746 */ GIR_EraseRootFromParent_Done, |
| 34952 | /* 95747 */ // Label 2955: @95747 |
| 34953 | /* 95747 */ GIM_Try, /*On fail goto*//*Label 2956*/ GIMT_Encode4(95775), // Rule ID 5542 // |
| 34954 | /* 95752 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 34955 | /* 95756 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34956 | /* 95760 */ // (intrinsic_w_chain:{ *:[v2i64] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34957 | /* 95760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 34958 | /* 95763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34959 | /* 95765 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34960 | /* 95767 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34961 | /* 95769 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34962 | /* 95773 */ GIR_RootConstrainSelectedInstOperands, |
| 34963 | /* 95774 */ // GIR_Coverage, 5542, |
| 34964 | /* 95774 */ GIR_EraseRootFromParent_Done, |
| 34965 | /* 95775 */ // Label 2956: @95775 |
| 34966 | /* 95775 */ GIM_Try, /*On fail goto*//*Label 2957*/ GIMT_Encode4(95803), // Rule ID 5545 // |
| 34967 | /* 95780 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34968 | /* 95784 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34969 | /* 95788 */ // (intrinsic_w_chain:{ *:[v2i64] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34970 | /* 95788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 34971 | /* 95791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34972 | /* 95793 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34973 | /* 95795 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34974 | /* 95797 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34975 | /* 95801 */ GIR_RootConstrainSelectedInstOperands, |
| 34976 | /* 95802 */ // GIR_Coverage, 5545, |
| 34977 | /* 95802 */ GIR_EraseRootFromParent_Done, |
| 34978 | /* 95803 */ // Label 2957: @95803 |
| 34979 | /* 95803 */ GIM_Try, /*On fail goto*//*Label 2958*/ GIMT_Encode4(95831), // Rule ID 5546 // |
| 34980 | /* 95808 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 34981 | /* 95812 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0, |
| 34982 | /* 95816 */ // (intrinsic_w_chain:{ *:[v2i64] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34983 | /* 95816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 34984 | /* 95819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34985 | /* 95821 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34986 | /* 95823 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 34987 | /* 95825 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34988 | /* 95829 */ GIR_RootConstrainSelectedInstOperands, |
| 34989 | /* 95830 */ // GIR_Coverage, 5546, |
| 34990 | /* 95830 */ GIR_EraseRootFromParent_Done, |
| 34991 | /* 95831 */ // Label 2958: @95831 |
| 34992 | /* 95831 */ GIM_Try, /*On fail goto*//*Label 2959*/ GIMT_Encode4(95859), // Rule ID 5549 // |
| 34993 | /* 95836 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 34994 | /* 95840 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 34995 | /* 95844 */ // (intrinsic_w_chain:{ *:[v2i64] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 34996 | /* 95844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u), |
| 34997 | /* 95847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 34998 | /* 95849 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 34999 | /* 95851 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35000 | /* 95853 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35001 | /* 95857 */ GIR_RootConstrainSelectedInstOperands, |
| 35002 | /* 95858 */ // GIR_Coverage, 5549, |
| 35003 | /* 95858 */ GIR_EraseRootFromParent_Done, |
| 35004 | /* 95859 */ // Label 2959: @95859 |
| 35005 | /* 95859 */ GIM_Try, /*On fail goto*//*Label 2960*/ GIMT_Encode4(95887), // Rule ID 5550 // |
| 35006 | /* 95864 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3, |
| 35007 | /* 95868 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1, |
| 35008 | /* 95872 */ // (intrinsic_w_chain:{ *:[v2i64] } 3925:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets) |
| 35009 | /* 95872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq), |
| 35010 | /* 95875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35011 | /* 95877 */ GIR_RootToRootCopy, /*OpIdx*/2, // base |
| 35012 | /* 95879 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets |
| 35013 | /* 95881 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35014 | /* 95885 */ GIR_RootConstrainSelectedInstOperands, |
| 35015 | /* 95886 */ // GIR_Coverage, 5550, |
| 35016 | /* 95886 */ GIR_EraseRootFromParent_Done, |
| 35017 | /* 95887 */ // Label 2960: @95887 |
| 35018 | /* 95887 */ GIM_Reject, |
| 35019 | /* 95888 */ // Label 2952: @95888 |
| 35020 | /* 95888 */ GIM_Reject, |
| 35021 | /* 95889 */ // Label 2908: @95889 |
| 35022 | /* 95889 */ GIM_Reject, |
| 35023 | /* 95890 */ // Label 2903: @95890 |
| 35024 | /* 95890 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2961*/ GIMT_Encode4(95954), GIMT_Encode2(GIFBS_IsARM), // Rule ID 255 // |
| 35025 | /* 95897 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr), |
| 35026 | /* 95902 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35027 | /* 95905 */ // MIs[0] cop |
| 35028 | /* 95905 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 35029 | /* 95908 */ // MIs[0] opc1 |
| 35030 | /* 95908 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 35031 | /* 95911 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35032 | /* 95915 */ // MIs[0] CRn |
| 35033 | /* 95915 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 35034 | /* 95918 */ // MIs[0] CRm |
| 35035 | /* 95918 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 35036 | /* 95921 */ // MIs[0] opc2 |
| 35037 | /* 95921 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 35038 | /* 95924 */ // (intrinsic_void 3790:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 35039 | /* 95924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR), |
| 35040 | /* 95927 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 35041 | /* 95929 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 35042 | /* 95931 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 35043 | /* 95933 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 35044 | /* 95935 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 35045 | /* 95937 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 35046 | /* 95939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35047 | /* 95942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35048 | /* 95948 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35049 | /* 95952 */ GIR_RootConstrainSelectedInstOperands, |
| 35050 | /* 95953 */ // GIR_Coverage, 255, |
| 35051 | /* 95953 */ GIR_EraseRootFromParent_Done, |
| 35052 | /* 95954 */ // Label 2961: @95954 |
| 35053 | /* 95954 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2962*/ GIMT_Encode4(96009), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 256 // |
| 35054 | /* 95961 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2), |
| 35055 | /* 95966 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35056 | /* 95969 */ // MIs[0] cop |
| 35057 | /* 95969 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 35058 | /* 95972 */ // MIs[0] opc1 |
| 35059 | /* 95972 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 35060 | /* 95975 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35061 | /* 95979 */ // MIs[0] CRn |
| 35062 | /* 95979 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 35063 | /* 95982 */ // MIs[0] CRm |
| 35064 | /* 95982 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 35065 | /* 95985 */ // MIs[0] opc2 |
| 35066 | /* 95985 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 35067 | /* 95988 */ // (intrinsic_void 3791:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 35068 | /* 95988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR2), |
| 35069 | /* 95991 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 35070 | /* 95993 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 35071 | /* 95995 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 35072 | /* 95997 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 35073 | /* 95999 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 35074 | /* 96001 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 35075 | /* 96003 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35076 | /* 96007 */ GIR_RootConstrainSelectedInstOperands, |
| 35077 | /* 96008 */ // GIR_Coverage, 256, |
| 35078 | /* 96008 */ GIR_EraseRootFromParent_Done, |
| 35079 | /* 96009 */ // Label 2962: @96009 |
| 35080 | /* 96009 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2963*/ GIMT_Encode4(96073), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 593 // |
| 35081 | /* 96016 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr), |
| 35082 | /* 96021 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35083 | /* 96024 */ // MIs[0] cop |
| 35084 | /* 96024 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 35085 | /* 96027 */ // MIs[0] opc1 |
| 35086 | /* 96027 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 35087 | /* 96030 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35088 | /* 96034 */ // MIs[0] CRn |
| 35089 | /* 96034 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 35090 | /* 96037 */ // MIs[0] CRm |
| 35091 | /* 96037 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 35092 | /* 96040 */ // MIs[0] opc2 |
| 35093 | /* 96040 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 35094 | /* 96043 */ // (intrinsic_void 3790:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 35095 | /* 96043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR), |
| 35096 | /* 96046 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 35097 | /* 96048 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 35098 | /* 96050 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 35099 | /* 96052 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 35100 | /* 96054 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 35101 | /* 96056 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 35102 | /* 96058 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35103 | /* 96061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35104 | /* 96067 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35105 | /* 96071 */ GIR_RootConstrainSelectedInstOperands, |
| 35106 | /* 96072 */ // GIR_Coverage, 593, |
| 35107 | /* 96072 */ GIR_EraseRootFromParent_Done, |
| 35108 | /* 96073 */ // Label 2963: @96073 |
| 35109 | /* 96073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2964*/ GIMT_Encode4(96137), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 594 // |
| 35110 | /* 96080 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2), |
| 35111 | /* 96085 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 35112 | /* 96088 */ // MIs[0] cop |
| 35113 | /* 96088 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 35114 | /* 96091 */ // MIs[0] opc1 |
| 35115 | /* 96091 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 35116 | /* 96094 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35117 | /* 96098 */ // MIs[0] CRn |
| 35118 | /* 96098 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 35119 | /* 96101 */ // MIs[0] CRm |
| 35120 | /* 96101 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 35121 | /* 96104 */ // MIs[0] opc2 |
| 35122 | /* 96104 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 35123 | /* 96107 */ // (intrinsic_void 3791:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) |
| 35124 | /* 96107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR2), |
| 35125 | /* 96110 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop |
| 35126 | /* 96112 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1 |
| 35127 | /* 96114 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt |
| 35128 | /* 96116 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn |
| 35129 | /* 96118 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm |
| 35130 | /* 96120 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2 |
| 35131 | /* 96122 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35132 | /* 96125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35133 | /* 96131 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35134 | /* 96135 */ GIR_RootConstrainSelectedInstOperands, |
| 35135 | /* 96136 */ // GIR_Coverage, 594, |
| 35136 | /* 96136 */ GIR_EraseRootFromParent_Done, |
| 35137 | /* 96137 */ // Label 2964: @96137 |
| 35138 | /* 96137 */ GIM_Reject, |
| 35139 | /* 96138 */ // Label 2898: @96138 |
| 35140 | /* 96138 */ GIM_Reject, |
| 35141 | /* 96139 */ // Label 23: @96139 |
| 35142 | /* 96139 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 2968*/ GIMT_Encode4(96277), |
| 35143 | /* 96150 */ /*GILLT_v8s16*//*Label 2965*/ GIMT_Encode4(96166), GIMT_Encode4(0), |
| 35144 | /* 96158 */ /*GILLT_v4s32*//*Label 2966*/ GIMT_Encode4(96203), |
| 35145 | /* 96162 */ /*GILLT_v2s64*//*Label 2967*/ GIMT_Encode4(96240), |
| 35146 | /* 96166 */ // Label 2965: @96166 |
| 35147 | /* 96166 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2969*/ GIMT_Encode4(96202), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3052 // |
| 35148 | /* 96173 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35149 | /* 96176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35150 | /* 96180 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35151 | /* 96184 */ // (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) |
| 35152 | /* 96184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16), |
| 35153 | /* 96187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35154 | /* 96189 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35155 | /* 96191 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35156 | /* 96194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35157 | /* 96200 */ GIR_RootConstrainSelectedInstOperands, |
| 35158 | /* 96201 */ // GIR_Coverage, 3052, |
| 35159 | /* 96201 */ GIR_EraseRootFromParent_Done, |
| 35160 | /* 96202 */ // Label 2969: @96202 |
| 35161 | /* 96202 */ GIM_Reject, |
| 35162 | /* 96203 */ // Label 2966: @96203 |
| 35163 | /* 96203 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2970*/ GIMT_Encode4(96239), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3053 // |
| 35164 | /* 96210 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35165 | /* 96213 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35166 | /* 96217 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35167 | /* 96221 */ // (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) |
| 35168 | /* 96221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32), |
| 35169 | /* 96224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35170 | /* 96226 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35171 | /* 96228 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35172 | /* 96231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35173 | /* 96237 */ GIR_RootConstrainSelectedInstOperands, |
| 35174 | /* 96238 */ // GIR_Coverage, 3053, |
| 35175 | /* 96238 */ GIR_EraseRootFromParent_Done, |
| 35176 | /* 96239 */ // Label 2970: @96239 |
| 35177 | /* 96239 */ GIM_Reject, |
| 35178 | /* 96240 */ // Label 2967: @96240 |
| 35179 | /* 96240 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2971*/ GIMT_Encode4(96276), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3054 // |
| 35180 | /* 96247 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35181 | /* 96250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35182 | /* 96254 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35183 | /* 96258 */ // (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) |
| 35184 | /* 96258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64), |
| 35185 | /* 96261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35186 | /* 96263 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35187 | /* 96265 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35188 | /* 96268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35189 | /* 96274 */ GIR_RootConstrainSelectedInstOperands, |
| 35190 | /* 96275 */ // GIR_Coverage, 3054, |
| 35191 | /* 96275 */ GIR_EraseRootFromParent_Done, |
| 35192 | /* 96276 */ // Label 2971: @96276 |
| 35193 | /* 96276 */ GIM_Reject, |
| 35194 | /* 96277 */ // Label 2968: @96277 |
| 35195 | /* 96277 */ GIM_Reject, |
| 35196 | /* 96278 */ // Label 24: @96278 |
| 35197 | /* 96278 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 2975*/ GIMT_Encode4(96420), |
| 35198 | /* 96289 */ /*GILLT_v8s8*//*Label 2972*/ GIMT_Encode4(96309), GIMT_Encode4(0), |
| 35199 | /* 96297 */ /*GILLT_v4s16*//*Label 2973*/ GIMT_Encode4(96346), GIMT_Encode4(0), |
| 35200 | /* 96305 */ /*GILLT_v2s32*//*Label 2974*/ GIMT_Encode4(96383), |
| 35201 | /* 96309 */ // Label 2972: @96309 |
| 35202 | /* 96309 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2976*/ GIMT_Encode4(96345), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1748 // |
| 35203 | /* 96316 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 35204 | /* 96319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35205 | /* 96323 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35206 | /* 96327 */ // (trunc:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) => (VMOVNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) |
| 35207 | /* 96327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv8i8), |
| 35208 | /* 96330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35209 | /* 96332 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35210 | /* 96334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35211 | /* 96337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35212 | /* 96343 */ GIR_RootConstrainSelectedInstOperands, |
| 35213 | /* 96344 */ // GIR_Coverage, 1748, |
| 35214 | /* 96344 */ GIR_EraseRootFromParent_Done, |
| 35215 | /* 96345 */ // Label 2976: @96345 |
| 35216 | /* 96345 */ GIM_Reject, |
| 35217 | /* 96346 */ // Label 2973: @96346 |
| 35218 | /* 96346 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2977*/ GIMT_Encode4(96382), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1749 // |
| 35219 | /* 96353 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 35220 | /* 96356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35221 | /* 96360 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35222 | /* 96364 */ // (trunc:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) => (VMOVNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) |
| 35223 | /* 96364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv4i16), |
| 35224 | /* 96367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35225 | /* 96369 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35226 | /* 96371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35227 | /* 96374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35228 | /* 96380 */ GIR_RootConstrainSelectedInstOperands, |
| 35229 | /* 96381 */ // GIR_Coverage, 1749, |
| 35230 | /* 96381 */ GIR_EraseRootFromParent_Done, |
| 35231 | /* 96382 */ // Label 2977: @96382 |
| 35232 | /* 96382 */ GIM_Reject, |
| 35233 | /* 96383 */ // Label 2974: @96383 |
| 35234 | /* 96383 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2978*/ GIMT_Encode4(96419), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1750 // |
| 35235 | /* 96390 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 35236 | /* 96393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35237 | /* 96397 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35238 | /* 96401 */ // (trunc:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) => (VMOVNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) |
| 35239 | /* 96401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv2i32), |
| 35240 | /* 96404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35241 | /* 96406 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35242 | /* 96408 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35243 | /* 96411 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35244 | /* 96417 */ GIR_RootConstrainSelectedInstOperands, |
| 35245 | /* 96418 */ // GIR_Coverage, 1750, |
| 35246 | /* 96418 */ GIR_EraseRootFromParent_Done, |
| 35247 | /* 96419 */ // Label 2978: @96419 |
| 35248 | /* 96419 */ GIM_Reject, |
| 35249 | /* 96420 */ // Label 2975: @96420 |
| 35250 | /* 96420 */ GIM_Reject, |
| 35251 | /* 96421 */ // Label 25: @96421 |
| 35252 | /* 96421 */ GIM_Try, /*On fail goto*//*Label 2979*/ GIMT_Encode4(96732), |
| 35253 | /* 96426 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35254 | /* 96429 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2980*/ GIMT_Encode4(96469), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 403 // |
| 35255 | /* 96436 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm), |
| 35256 | /* 96440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35257 | /* 96444 */ // MIs[0] Operand 1 |
| 35258 | /* 96444 */ // No operand predicates |
| 35259 | /* 96444 */ // (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm => (t2MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35260 | /* 96444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 35261 | /* 96447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35262 | /* 96449 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35263 | /* 96452 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35264 | /* 96455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35265 | /* 96461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35266 | /* 96467 */ GIR_RootConstrainSelectedInstOperands, |
| 35267 | /* 96468 */ // GIR_Coverage, 403, |
| 35268 | /* 96468 */ GIR_EraseRootFromParent_Done, |
| 35269 | /* 96469 */ // Label 2980: @96469 |
| 35270 | /* 96469 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2981*/ GIMT_Encode4(96509), GIMT_Encode2(GIFBS_IsARM), // Rule ID 56 // |
| 35271 | /* 96476 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm), |
| 35272 | /* 96480 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35273 | /* 96484 */ // MIs[0] Operand 1 |
| 35274 | /* 96484 */ // No operand predicates |
| 35275 | /* 96484 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm => (MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35276 | /* 96484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi), |
| 35277 | /* 96487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35278 | /* 96489 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35279 | /* 96492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35280 | /* 96495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35281 | /* 96501 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35282 | /* 96507 */ GIR_RootConstrainSelectedInstOperands, |
| 35283 | /* 96508 */ // GIR_Coverage, 56, |
| 35284 | /* 96508 */ GIR_EraseRootFromParent_Done, |
| 35285 | /* 96509 */ // Label 2981: @96509 |
| 35286 | /* 96509 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2982*/ GIMT_Encode4(96543), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 57 // |
| 35287 | /* 96516 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 35288 | /* 96520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35289 | /* 96524 */ // MIs[0] Operand 1 |
| 35290 | /* 96524 */ // No operand predicates |
| 35291 | /* 96524 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35292 | /* 96524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi16), |
| 35293 | /* 96527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35294 | /* 96529 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35295 | /* 96532 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35296 | /* 96535 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35297 | /* 96541 */ GIR_RootConstrainSelectedInstOperands, |
| 35298 | /* 96542 */ // GIR_Coverage, 57, |
| 35299 | /* 96542 */ GIR_EraseRootFromParent_Done, |
| 35300 | /* 96543 */ // Label 2982: @96543 |
| 35301 | /* 96543 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2983*/ GIMT_Encode4(96585), GIMT_Encode2(GIFBS_IsARM), // Rule ID 167 // |
| 35302 | /* 96550 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not), |
| 35303 | /* 96554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35304 | /* 96558 */ // MIs[0] Operand 1 |
| 35305 | /* 96558 */ // No operand predicates |
| 35306 | /* 96558 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm => (MVNi:{ *:[i32] } (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm)) |
| 35307 | /* 96558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNi), |
| 35308 | /* 96561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35309 | /* 96563 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm |
| 35310 | /* 96568 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35311 | /* 96571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35312 | /* 96577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35313 | /* 96583 */ GIR_RootConstrainSelectedInstOperands, |
| 35314 | /* 96584 */ // GIR_Coverage, 167, |
| 35315 | /* 96584 */ GIR_EraseRootFromParent_Done, |
| 35316 | /* 96585 */ // Label 2983: @96585 |
| 35317 | /* 96585 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2984*/ GIMT_Encode4(96610), GIMT_Encode2(GIFBS_IsARM), // Rule ID 267 // |
| 35318 | /* 96592 */ GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_arm_i32imm), |
| 35319 | /* 96596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35320 | /* 96600 */ // MIs[0] Operand 1 |
| 35321 | /* 96600 */ // No operand predicates |
| 35322 | /* 96600 */ // (imm:{ *:[i32] })<<P:Predicate_arm_i32imm>>:$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 35323 | /* 96600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi32imm), |
| 35324 | /* 96603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 35325 | /* 96605 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 35326 | /* 96608 */ GIR_RootConstrainSelectedInstOperands, |
| 35327 | /* 96609 */ // GIR_Coverage, 267, |
| 35328 | /* 96609 */ GIR_EraseRootFromParent_Done, |
| 35329 | /* 96610 */ // Label 2984: @96610 |
| 35330 | /* 96610 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2985*/ GIMT_Encode4(96650), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 321 // |
| 35331 | /* 96617 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr), |
| 35332 | /* 96621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35333 | /* 96625 */ // MIs[0] Operand 1 |
| 35334 | /* 96625 */ // No operand predicates |
| 35335 | /* 96625 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8 => (tMOVi8:{ *:[i32] } (imm:{ *:[i32] }):$imm8) |
| 35336 | /* 96625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 35337 | /* 96628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35338 | /* 96630 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 35339 | /* 96636 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm8 |
| 35340 | /* 96639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35341 | /* 96642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35342 | /* 96648 */ GIR_RootConstrainSelectedInstOperands, |
| 35343 | /* 96649 */ // GIR_Coverage, 321, |
| 35344 | /* 96649 */ GIR_EraseRootFromParent_Done, |
| 35345 | /* 96650 */ // Label 2985: @96650 |
| 35346 | /* 96650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2986*/ GIMT_Encode4(96684), GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb), // Rule ID 404 // |
| 35347 | /* 96657 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535), |
| 35348 | /* 96661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35349 | /* 96665 */ // MIs[0] Operand 1 |
| 35350 | /* 96665 */ // No operand predicates |
| 35351 | /* 96665 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (t2MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 35352 | /* 96665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16), |
| 35353 | /* 96668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35354 | /* 96670 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 35355 | /* 96673 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35356 | /* 96676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35357 | /* 96682 */ GIR_RootConstrainSelectedInstOperands, |
| 35358 | /* 96683 */ // GIR_Coverage, 404, |
| 35359 | /* 96683 */ GIR_EraseRootFromParent_Done, |
| 35360 | /* 96684 */ // Label 2986: @96684 |
| 35361 | /* 96684 */ GIM_Try, /*On fail goto*//*Label 2987*/ GIMT_Encode4(96731), |
| 35362 | /* 96689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35363 | /* 96693 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2988*/ GIMT_Encode4(96713), GIMT_Encode2(GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only), // Rule ID 352 // |
| 35364 | /* 96700 */ // MIs[0] Operand 1 |
| 35365 | /* 96700 */ // No operand predicates |
| 35366 | /* 96700 */ // (imm:{ *:[i32] }):$src => (tMOVi32imm:{ *:[i32] }:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 35367 | /* 96700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi32imm), |
| 35368 | /* 96703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 35369 | /* 96705 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 35370 | /* 96708 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::CPSR*/0, |
| 35371 | /* 96711 */ GIR_RootConstrainSelectedInstOperands, |
| 35372 | /* 96712 */ // GIR_Coverage, 352, |
| 35373 | /* 96712 */ GIR_EraseRootFromParent_Done, |
| 35374 | /* 96713 */ // Label 2988: @96713 |
| 35375 | /* 96713 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2989*/ GIMT_Encode4(96730), GIMT_Encode2(GIFBS_IsThumb_UseMovt), // Rule ID 581 // |
| 35376 | /* 96720 */ // MIs[0] Operand 1 |
| 35377 | /* 96720 */ // No operand predicates |
| 35378 | /* 96720 */ // (imm:{ *:[i32] }):$src => (t2MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src) |
| 35379 | /* 96720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm), |
| 35380 | /* 96723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 35381 | /* 96725 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src |
| 35382 | /* 96728 */ GIR_RootConstrainSelectedInstOperands, |
| 35383 | /* 96729 */ // GIR_Coverage, 581, |
| 35384 | /* 96729 */ GIR_EraseRootFromParent_Done, |
| 35385 | /* 96730 */ // Label 2989: @96730 |
| 35386 | /* 96730 */ GIM_Reject, |
| 35387 | /* 96731 */ // Label 2987: @96731 |
| 35388 | /* 96731 */ GIM_Reject, |
| 35389 | /* 96732 */ // Label 2979: @96732 |
| 35390 | /* 96732 */ GIM_Reject, |
| 35391 | /* 96733 */ // Label 26: @96733 |
| 35392 | /* 96733 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2992*/ GIMT_Encode4(96826), |
| 35393 | /* 96744 */ /*GILLT_s32*//*Label 2990*/ GIMT_Encode4(96752), |
| 35394 | /* 96748 */ /*GILLT_s64*//*Label 2991*/ GIMT_Encode4(96789), |
| 35395 | /* 96752 */ // Label 2990: @96752 |
| 35396 | /* 96752 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2993*/ GIMT_Encode4(96788), GIMT_Encode2(GIFBS_HasVFP3), // Rule ID 848 // |
| 35397 | /* 96759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 35398 | /* 96763 */ // MIs[0] Operand 1 |
| 35399 | /* 96763 */ // No operand predicates |
| 35400 | /* 96763 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f32imm), |
| 35401 | /* 96767 */ // (fpimm:{ *:[f32] })<<P:Predicate_vfp_f32imm>><<X:vfp_f32imm_xform>>:$imm => (FCONSTS:{ *:[f32] } (vfp_f32imm_xform:{ *:[f32] } (fpimm:{ *:[f32] }):$imm)) |
| 35402 | /* 96767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTS), |
| 35403 | /* 96770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 35404 | /* 96772 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF32Imm), // imm |
| 35405 | /* 96777 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35406 | /* 96780 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35407 | /* 96786 */ GIR_RootConstrainSelectedInstOperands, |
| 35408 | /* 96787 */ // GIR_Coverage, 848, |
| 35409 | /* 96787 */ GIR_EraseRootFromParent_Done, |
| 35410 | /* 96788 */ // Label 2993: @96788 |
| 35411 | /* 96788 */ GIM_Reject, |
| 35412 | /* 96789 */ // Label 2991: @96789 |
| 35413 | /* 96789 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2994*/ GIMT_Encode4(96825), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP3), // Rule ID 847 // |
| 35414 | /* 96796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35415 | /* 96800 */ // MIs[0] Operand 1 |
| 35416 | /* 96800 */ // No operand predicates |
| 35417 | /* 96800 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f64imm), |
| 35418 | /* 96804 */ // (fpimm:{ *:[f64] })<<P:Predicate_vfp_f64imm>><<X:vfp_f64imm_xform>>:$imm => (FCONSTD:{ *:[f64] } (vfp_f64imm_xform:{ *:[f64] } (fpimm:{ *:[f64] }):$imm)) |
| 35419 | /* 96804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTD), |
| 35420 | /* 96807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 35421 | /* 96809 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF64Imm), // imm |
| 35422 | /* 96814 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35423 | /* 96817 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35424 | /* 96823 */ GIR_RootConstrainSelectedInstOperands, |
| 35425 | /* 96824 */ // GIR_Coverage, 847, |
| 35426 | /* 96824 */ GIR_EraseRootFromParent_Done, |
| 35427 | /* 96825 */ // Label 2994: @96825 |
| 35428 | /* 96825 */ GIM_Reject, |
| 35429 | /* 96826 */ // Label 2992: @96826 |
| 35430 | /* 96826 */ GIM_Reject, |
| 35431 | /* 96827 */ // Label 27: @96827 |
| 35432 | /* 96827 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 2998*/ GIMT_Encode4(96965), |
| 35433 | /* 96838 */ /*GILLT_v8s16*//*Label 2995*/ GIMT_Encode4(96854), GIMT_Encode4(0), |
| 35434 | /* 96846 */ /*GILLT_v4s32*//*Label 2996*/ GIMT_Encode4(96891), |
| 35435 | /* 96850 */ /*GILLT_v2s64*//*Label 2997*/ GIMT_Encode4(96928), |
| 35436 | /* 96854 */ // Label 2995: @96854 |
| 35437 | /* 96854 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2999*/ GIMT_Encode4(96890), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1760 // |
| 35438 | /* 96861 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35439 | /* 96864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35440 | /* 96868 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35441 | /* 96872 */ // (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) |
| 35442 | /* 96872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv8i16), |
| 35443 | /* 96875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35444 | /* 96877 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35445 | /* 96879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35446 | /* 96882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35447 | /* 96888 */ GIR_RootConstrainSelectedInstOperands, |
| 35448 | /* 96889 */ // GIR_Coverage, 1760, |
| 35449 | /* 96889 */ GIR_EraseRootFromParent_Done, |
| 35450 | /* 96890 */ // Label 2999: @96890 |
| 35451 | /* 96890 */ GIM_Reject, |
| 35452 | /* 96891 */ // Label 2996: @96891 |
| 35453 | /* 96891 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3000*/ GIMT_Encode4(96927), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1761 // |
| 35454 | /* 96898 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35455 | /* 96901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35456 | /* 96905 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35457 | /* 96909 */ // (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) |
| 35458 | /* 96909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv4i32), |
| 35459 | /* 96912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35460 | /* 96914 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35461 | /* 96916 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35462 | /* 96919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35463 | /* 96925 */ GIR_RootConstrainSelectedInstOperands, |
| 35464 | /* 96926 */ // GIR_Coverage, 1761, |
| 35465 | /* 96926 */ GIR_EraseRootFromParent_Done, |
| 35466 | /* 96927 */ // Label 3000: @96927 |
| 35467 | /* 96927 */ GIM_Reject, |
| 35468 | /* 96928 */ // Label 2997: @96928 |
| 35469 | /* 96928 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3001*/ GIMT_Encode4(96964), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1762 // |
| 35470 | /* 96935 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35471 | /* 96938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35472 | /* 96942 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35473 | /* 96946 */ // (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) |
| 35474 | /* 96946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv2i64), |
| 35475 | /* 96949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35476 | /* 96951 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35477 | /* 96953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35478 | /* 96956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35479 | /* 96962 */ GIR_RootConstrainSelectedInstOperands, |
| 35480 | /* 96963 */ // GIR_Coverage, 1762, |
| 35481 | /* 96963 */ GIR_EraseRootFromParent_Done, |
| 35482 | /* 96964 */ // Label 3001: @96964 |
| 35483 | /* 96964 */ GIM_Reject, |
| 35484 | /* 96965 */ // Label 2998: @96965 |
| 35485 | /* 96965 */ GIM_Reject, |
| 35486 | /* 96966 */ // Label 28: @96966 |
| 35487 | /* 96966 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3005*/ GIMT_Encode4(97555), |
| 35488 | /* 96977 */ /*GILLT_s32*//*Label 3002*/ GIMT_Encode4(97025), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 35489 | /* 97013 */ /*GILLT_v8s16*//*Label 3003*/ GIMT_Encode4(97305), GIMT_Encode4(0), |
| 35490 | /* 97021 */ /*GILLT_v4s32*//*Label 3004*/ GIMT_Encode4(97374), |
| 35491 | /* 97025 */ // Label 3002: @97025 |
| 35492 | /* 97025 */ GIM_Try, /*On fail goto*//*Label 3006*/ GIMT_Encode4(97304), |
| 35493 | /* 97030 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35494 | /* 97033 */ GIM_Try, /*On fail goto*//*Label 3007*/ GIMT_Encode4(97119), |
| 35495 | /* 97038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35496 | /* 97042 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35497 | /* 97046 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3008*/ GIMT_Encode4(97082), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 339 // |
| 35498 | /* 97053 */ // MIs[0] Operand 2 |
| 35499 | /* 97053 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 35500 | /* 97064 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }) => (tSXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 35501 | /* 97064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTB), |
| 35502 | /* 97067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35503 | /* 97069 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 35504 | /* 97071 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35505 | /* 97074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35506 | /* 97080 */ GIR_RootConstrainSelectedInstOperands, |
| 35507 | /* 97081 */ // GIR_Coverage, 339, |
| 35508 | /* 97081 */ GIR_EraseRootFromParent_Done, |
| 35509 | /* 97082 */ // Label 3008: @97082 |
| 35510 | /* 97082 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3009*/ GIMT_Encode4(97118), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 340 // |
| 35511 | /* 97089 */ // MIs[0] Operand 2 |
| 35512 | /* 97089 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 35513 | /* 97100 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }) => (tSXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 35514 | /* 97100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTH), |
| 35515 | /* 97103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35516 | /* 97105 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 35517 | /* 97107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35518 | /* 97110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35519 | /* 97116 */ GIR_RootConstrainSelectedInstOperands, |
| 35520 | /* 97117 */ // GIR_Coverage, 340, |
| 35521 | /* 97117 */ GIR_EraseRootFromParent_Done, |
| 35522 | /* 97118 */ // Label 3009: @97118 |
| 35523 | /* 97118 */ GIM_Reject, |
| 35524 | /* 97119 */ // Label 3007: @97119 |
| 35525 | /* 97119 */ GIM_Try, /*On fail goto*//*Label 3010*/ GIMT_Encode4(97211), |
| 35526 | /* 97124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 35527 | /* 97128 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 35528 | /* 97132 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3011*/ GIMT_Encode4(97171), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2195 // |
| 35529 | /* 97139 */ // MIs[0] Operand 2 |
| 35530 | /* 97139 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 35531 | /* 97150 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (SXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 35532 | /* 97150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB), |
| 35533 | /* 97153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35534 | /* 97155 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 35535 | /* 97157 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35536 | /* 97160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35537 | /* 97163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35538 | /* 97169 */ GIR_RootConstrainSelectedInstOperands, |
| 35539 | /* 97170 */ // GIR_Coverage, 2195, |
| 35540 | /* 97170 */ GIR_EraseRootFromParent_Done, |
| 35541 | /* 97171 */ // Label 3011: @97171 |
| 35542 | /* 97171 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3012*/ GIMT_Encode4(97210), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2196 // |
| 35543 | /* 97178 */ // MIs[0] Operand 2 |
| 35544 | /* 97178 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 35545 | /* 97189 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (SXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 35546 | /* 97189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTH), |
| 35547 | /* 97192 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35548 | /* 97194 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 35549 | /* 97196 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35550 | /* 97199 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35551 | /* 97202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35552 | /* 97208 */ GIR_RootConstrainSelectedInstOperands, |
| 35553 | /* 97209 */ // GIR_Coverage, 2196, |
| 35554 | /* 97209 */ GIR_EraseRootFromParent_Done, |
| 35555 | /* 97210 */ // Label 3012: @97210 |
| 35556 | /* 97210 */ GIM_Reject, |
| 35557 | /* 97211 */ // Label 3010: @97211 |
| 35558 | /* 97211 */ GIM_Try, /*On fail goto*//*Label 3013*/ GIMT_Encode4(97303), |
| 35559 | /* 97216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35560 | /* 97220 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35561 | /* 97224 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3014*/ GIMT_Encode4(97263), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2438 // |
| 35562 | /* 97231 */ // MIs[0] Operand 2 |
| 35563 | /* 97231 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 35564 | /* 97242 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (t2SXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 35565 | /* 97242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB), |
| 35566 | /* 97245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35567 | /* 97247 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 35568 | /* 97249 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35569 | /* 97252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35570 | /* 97255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35571 | /* 97261 */ GIR_RootConstrainSelectedInstOperands, |
| 35572 | /* 97262 */ // GIR_Coverage, 2438, |
| 35573 | /* 97262 */ GIR_EraseRootFromParent_Done, |
| 35574 | /* 97263 */ // Label 3014: @97263 |
| 35575 | /* 97263 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3015*/ GIMT_Encode4(97302), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2439 // |
| 35576 | /* 97270 */ // MIs[0] Operand 2 |
| 35577 | /* 97270 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 35578 | /* 97281 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (t2SXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] }) |
| 35579 | /* 97281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTH), |
| 35580 | /* 97284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35581 | /* 97286 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src |
| 35582 | /* 97288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35583 | /* 97291 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35584 | /* 97294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35585 | /* 97300 */ GIR_RootConstrainSelectedInstOperands, |
| 35586 | /* 97301 */ // GIR_Coverage, 2439, |
| 35587 | /* 97301 */ GIR_EraseRootFromParent_Done, |
| 35588 | /* 97302 */ // Label 3015: @97302 |
| 35589 | /* 97302 */ GIM_Reject, |
| 35590 | /* 97303 */ // Label 3013: @97303 |
| 35591 | /* 97303 */ GIM_Reject, |
| 35592 | /* 97304 */ // Label 3006: @97304 |
| 35593 | /* 97304 */ GIM_Reject, |
| 35594 | /* 97305 */ // Label 3003: @97305 |
| 35595 | /* 97305 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3016*/ GIMT_Encode4(97373), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4108 // |
| 35596 | /* 97312 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 35597 | /* 97315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35598 | /* 97319 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35599 | /* 97323 */ // MIs[0] Operand 2 |
| 35600 | /* 97323 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 35601 | /* 97334 */ // (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, v8i8:{ *:[Other] }) => (MVE_VMOVLs8bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) |
| 35602 | /* 97334 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 35603 | /* 97337 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 35604 | /* 97341 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 35605 | /* 97346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh), |
| 35606 | /* 97349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35607 | /* 97351 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 35608 | /* 97353 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35609 | /* 97356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35610 | /* 97362 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35611 | /* 97368 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 35612 | /* 97371 */ GIR_RootConstrainSelectedInstOperands, |
| 35613 | /* 97372 */ // GIR_Coverage, 4108, |
| 35614 | /* 97372 */ GIR_EraseRootFromParent_Done, |
| 35615 | /* 97373 */ // Label 3016: @97373 |
| 35616 | /* 97373 */ GIM_Reject, |
| 35617 | /* 97374 */ // Label 3004: @97374 |
| 35618 | /* 97374 */ GIM_Try, /*On fail goto*//*Label 3017*/ GIMT_Encode4(97554), |
| 35619 | /* 97379 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 35620 | /* 97382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35621 | /* 97386 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 35622 | /* 97390 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3018*/ GIMT_Encode4(97447), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4107 // |
| 35623 | /* 97397 */ // MIs[0] Operand 2 |
| 35624 | /* 97397 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16), |
| 35625 | /* 97408 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i16:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) |
| 35626 | /* 97408 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 35627 | /* 97411 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 35628 | /* 97415 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 35629 | /* 97420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh), |
| 35630 | /* 97423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35631 | /* 97425 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 35632 | /* 97427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35633 | /* 97430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35634 | /* 97436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35635 | /* 97442 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 35636 | /* 97445 */ GIR_RootConstrainSelectedInstOperands, |
| 35637 | /* 97446 */ // GIR_Coverage, 4107, |
| 35638 | /* 97446 */ GIR_EraseRootFromParent_Done, |
| 35639 | /* 97447 */ // Label 3018: @97447 |
| 35640 | /* 97447 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3019*/ GIMT_Encode4(97553), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4109 // |
| 35641 | /* 97454 */ // MIs[0] Operand 2 |
| 35642 | /* 97454 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8), |
| 35643 | /* 97465 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i8:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } (MVE_VMOVLs8bh:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)) |
| 35644 | /* 97465 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 35645 | /* 97468 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 35646 | /* 97472 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 35647 | /* 97477 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32, |
| 35648 | /* 97480 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 35649 | /* 97484 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 35650 | /* 97489 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8, |
| 35651 | /* 97492 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh), |
| 35652 | /* 97496 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 35653 | /* 97501 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 35654 | /* 97505 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 35655 | /* 97508 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35656 | /* 97514 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35657 | /* 97520 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 35658 | /* 97523 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 35659 | /* 97525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh), |
| 35660 | /* 97528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 35661 | /* 97530 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 35662 | /* 97533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35663 | /* 97536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35664 | /* 97542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35665 | /* 97548 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 35666 | /* 97551 */ GIR_RootConstrainSelectedInstOperands, |
| 35667 | /* 97552 */ // GIR_Coverage, 4109, |
| 35668 | /* 97552 */ GIR_EraseRootFromParent_Done, |
| 35669 | /* 97553 */ // Label 3019: @97553 |
| 35670 | /* 97553 */ GIM_Reject, |
| 35671 | /* 97554 */ // Label 3017: @97554 |
| 35672 | /* 97554 */ GIM_Reject, |
| 35673 | /* 97555 */ // Label 3005: @97555 |
| 35674 | /* 97555 */ GIM_Reject, |
| 35675 | /* 97556 */ // Label 29: @97556 |
| 35676 | /* 97556 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 3023*/ GIMT_Encode4(98243), |
| 35677 | /* 97567 */ /*GILLT_v8s16*//*Label 3020*/ GIMT_Encode4(97583), GIMT_Encode4(0), |
| 35678 | /* 97575 */ /*GILLT_v4s32*//*Label 3021*/ GIMT_Encode4(97803), |
| 35679 | /* 97579 */ /*GILLT_v2s64*//*Label 3022*/ GIMT_Encode4(98023), |
| 35680 | /* 97583 */ // Label 3020: @97583 |
| 35681 | /* 97583 */ GIM_Try, /*On fail goto*//*Label 3024*/ GIMT_Encode4(97802), |
| 35682 | /* 97588 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35683 | /* 97591 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35684 | /* 97595 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3025*/ GIMT_Encode4(97654), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1335 // |
| 35685 | /* 97602 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35686 | /* 97606 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 35687 | /* 97610 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35688 | /* 97614 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 35689 | /* 97618 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35690 | /* 97623 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35691 | /* 97628 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35692 | /* 97630 */ // (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 35693 | /* 97630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv8i16), |
| 35694 | /* 97633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35695 | /* 97635 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 35696 | /* 97639 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 35697 | /* 97643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35698 | /* 97646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35699 | /* 97652 */ GIR_RootConstrainSelectedInstOperands, |
| 35700 | /* 97653 */ // GIR_Coverage, 1335, |
| 35701 | /* 97653 */ GIR_EraseRootFromParent_Done, |
| 35702 | /* 97654 */ // Label 3025: @97654 |
| 35703 | /* 97654 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3026*/ GIMT_Encode4(97713), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1338 // |
| 35704 | /* 97661 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35705 | /* 97665 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 35706 | /* 97669 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35707 | /* 97673 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 35708 | /* 97677 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35709 | /* 97682 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35710 | /* 97687 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35711 | /* 97689 */ // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 35712 | /* 97689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16), |
| 35713 | /* 97692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35714 | /* 97694 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 35715 | /* 97698 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 35716 | /* 97702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35717 | /* 97705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35718 | /* 97711 */ GIR_RootConstrainSelectedInstOperands, |
| 35719 | /* 97712 */ // GIR_Coverage, 1338, |
| 35720 | /* 97712 */ GIR_EraseRootFromParent_Done, |
| 35721 | /* 97713 */ // Label 3026: @97713 |
| 35722 | /* 97713 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3027*/ GIMT_Encode4(97772), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2964 // |
| 35723 | /* 97720 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35724 | /* 97724 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 35725 | /* 97728 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8, |
| 35726 | /* 97732 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8, |
| 35727 | /* 97736 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35728 | /* 97741 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35729 | /* 97746 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35730 | /* 97748 */ // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB) |
| 35731 | /* 97748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16), |
| 35732 | /* 97751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35733 | /* 97753 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA |
| 35734 | /* 97757 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB |
| 35735 | /* 97761 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35736 | /* 97764 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35737 | /* 97770 */ GIR_RootConstrainSelectedInstOperands, |
| 35738 | /* 97771 */ // GIR_Coverage, 2964, |
| 35739 | /* 97771 */ GIR_EraseRootFromParent_Done, |
| 35740 | /* 97772 */ // Label 3027: @97772 |
| 35741 | /* 97772 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3028*/ GIMT_Encode4(97801), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1763 // |
| 35742 | /* 97779 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35743 | /* 97783 */ // (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) |
| 35744 | /* 97783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16), |
| 35745 | /* 97786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35746 | /* 97788 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35747 | /* 97790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35748 | /* 97793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35749 | /* 97799 */ GIR_RootConstrainSelectedInstOperands, |
| 35750 | /* 97800 */ // GIR_Coverage, 1763, |
| 35751 | /* 97800 */ GIR_EraseRootFromParent_Done, |
| 35752 | /* 97801 */ // Label 3028: @97801 |
| 35753 | /* 97801 */ GIM_Reject, |
| 35754 | /* 97802 */ // Label 3024: @97802 |
| 35755 | /* 97802 */ GIM_Reject, |
| 35756 | /* 97803 */ // Label 3021: @97803 |
| 35757 | /* 97803 */ GIM_Try, /*On fail goto*//*Label 3029*/ GIMT_Encode4(98022), |
| 35758 | /* 97808 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35759 | /* 97811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35760 | /* 97815 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3030*/ GIMT_Encode4(97874), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1336 // |
| 35761 | /* 97822 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35762 | /* 97826 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 35763 | /* 97830 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35764 | /* 97834 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35765 | /* 97838 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35766 | /* 97843 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35767 | /* 97848 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35768 | /* 97850 */ // (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 35769 | /* 97850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv4i32), |
| 35770 | /* 97853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35771 | /* 97855 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 35772 | /* 97859 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 35773 | /* 97863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35774 | /* 97866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35775 | /* 97872 */ GIR_RootConstrainSelectedInstOperands, |
| 35776 | /* 97873 */ // GIR_Coverage, 1336, |
| 35777 | /* 97873 */ GIR_EraseRootFromParent_Done, |
| 35778 | /* 97874 */ // Label 3030: @97874 |
| 35779 | /* 97874 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3031*/ GIMT_Encode4(97933), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1339 // |
| 35780 | /* 97881 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35781 | /* 97885 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 35782 | /* 97889 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35783 | /* 97893 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35784 | /* 97897 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35785 | /* 97902 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35786 | /* 97907 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35787 | /* 97909 */ // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 35788 | /* 97909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32), |
| 35789 | /* 97912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35790 | /* 97914 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 35791 | /* 97918 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 35792 | /* 97922 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35793 | /* 97925 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35794 | /* 97931 */ GIR_RootConstrainSelectedInstOperands, |
| 35795 | /* 97932 */ // GIR_Coverage, 1339, |
| 35796 | /* 97932 */ GIR_EraseRootFromParent_Done, |
| 35797 | /* 97933 */ // Label 3031: @97933 |
| 35798 | /* 97933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3032*/ GIMT_Encode4(97992), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2965 // |
| 35799 | /* 97940 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35800 | /* 97944 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 35801 | /* 97948 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 35802 | /* 97952 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 35803 | /* 97956 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35804 | /* 97961 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35805 | /* 97966 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35806 | /* 97968 */ // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB) |
| 35807 | /* 97968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32), |
| 35808 | /* 97971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35809 | /* 97973 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA |
| 35810 | /* 97977 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB |
| 35811 | /* 97981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35812 | /* 97984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35813 | /* 97990 */ GIR_RootConstrainSelectedInstOperands, |
| 35814 | /* 97991 */ // GIR_Coverage, 2965, |
| 35815 | /* 97991 */ GIR_EraseRootFromParent_Done, |
| 35816 | /* 97992 */ // Label 3032: @97992 |
| 35817 | /* 97992 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3033*/ GIMT_Encode4(98021), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1764 // |
| 35818 | /* 97999 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35819 | /* 98003 */ // (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) |
| 35820 | /* 98003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32), |
| 35821 | /* 98006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35822 | /* 98008 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35823 | /* 98010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35824 | /* 98013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35825 | /* 98019 */ GIR_RootConstrainSelectedInstOperands, |
| 35826 | /* 98020 */ // GIR_Coverage, 1764, |
| 35827 | /* 98020 */ GIR_EraseRootFromParent_Done, |
| 35828 | /* 98021 */ // Label 3033: @98021 |
| 35829 | /* 98021 */ GIM_Reject, |
| 35830 | /* 98022 */ // Label 3029: @98022 |
| 35831 | /* 98022 */ GIM_Reject, |
| 35832 | /* 98023 */ // Label 3022: @98023 |
| 35833 | /* 98023 */ GIM_Try, /*On fail goto*//*Label 3034*/ GIMT_Encode4(98242), |
| 35834 | /* 98028 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35835 | /* 98031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 35836 | /* 98035 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3035*/ GIMT_Encode4(98094), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1337 // |
| 35837 | /* 98042 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35838 | /* 98046 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS), |
| 35839 | /* 98050 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35840 | /* 98054 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35841 | /* 98058 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35842 | /* 98063 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35843 | /* 98068 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35844 | /* 98070 */ // (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 35845 | /* 98070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv2i64), |
| 35846 | /* 98073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35847 | /* 98075 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 35848 | /* 98079 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 35849 | /* 98083 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35850 | /* 98086 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35851 | /* 98092 */ GIR_RootConstrainSelectedInstOperands, |
| 35852 | /* 98093 */ // GIR_Coverage, 1337, |
| 35853 | /* 98093 */ GIR_EraseRootFromParent_Done, |
| 35854 | /* 98094 */ // Label 3035: @98094 |
| 35855 | /* 98094 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3036*/ GIMT_Encode4(98153), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1340 // |
| 35856 | /* 98101 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35857 | /* 98105 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 35858 | /* 98109 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35859 | /* 98113 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35860 | /* 98117 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35861 | /* 98122 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35862 | /* 98127 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35863 | /* 98129 */ // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 35864 | /* 98129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv2i64), |
| 35865 | /* 98132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35866 | /* 98134 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 35867 | /* 98138 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 35868 | /* 98142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35869 | /* 98145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35870 | /* 98151 */ GIR_RootConstrainSelectedInstOperands, |
| 35871 | /* 98152 */ // GIR_Coverage, 1340, |
| 35872 | /* 98152 */ GIR_EraseRootFromParent_Done, |
| 35873 | /* 98153 */ // Label 3036: @98153 |
| 35874 | /* 98153 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3037*/ GIMT_Encode4(98212), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2966 // |
| 35875 | /* 98160 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 35876 | /* 98164 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU), |
| 35877 | /* 98168 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 35878 | /* 98172 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 35879 | /* 98176 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35880 | /* 98181 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35881 | /* 98186 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35882 | /* 98188 */ // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$opA, DPR:{ *:[v2i32] }:$opB)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$opA, DPR:{ *:[v2i32] }:$opB) |
| 35883 | /* 98188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv2i64), |
| 35884 | /* 98191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35885 | /* 98193 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA |
| 35886 | /* 98197 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB |
| 35887 | /* 98201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35888 | /* 98204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35889 | /* 98210 */ GIR_RootConstrainSelectedInstOperands, |
| 35890 | /* 98211 */ // GIR_Coverage, 2966, |
| 35891 | /* 98211 */ GIR_EraseRootFromParent_Done, |
| 35892 | /* 98212 */ // Label 3037: @98212 |
| 35893 | /* 98212 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3038*/ GIMT_Encode4(98241), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1765 // |
| 35894 | /* 98219 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 35895 | /* 98223 */ // (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) |
| 35896 | /* 98223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64), |
| 35897 | /* 98226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 35898 | /* 98228 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 35899 | /* 98230 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35900 | /* 98233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35901 | /* 98239 */ GIR_RootConstrainSelectedInstOperands, |
| 35902 | /* 98240 */ // GIR_Coverage, 1765, |
| 35903 | /* 98240 */ GIR_EraseRootFromParent_Done, |
| 35904 | /* 98241 */ // Label 3038: @98241 |
| 35905 | /* 98241 */ GIM_Reject, |
| 35906 | /* 98242 */ // Label 3034: @98242 |
| 35907 | /* 98242 */ GIM_Reject, |
| 35908 | /* 98243 */ // Label 3023: @98243 |
| 35909 | /* 98243 */ GIM_Reject, |
| 35910 | /* 98244 */ // Label 30: @98244 |
| 35911 | /* 98244 */ GIM_Try, /*On fail goto*//*Label 3039*/ GIMT_Encode4(98455), |
| 35912 | /* 98249 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35913 | /* 98252 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35914 | /* 98255 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35915 | /* 98258 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3040*/ GIMT_Encode4(98314), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 469 // |
| 35916 | /* 98265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35917 | /* 98269 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35918 | /* 98273 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 35919 | /* 98277 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35920 | /* 98281 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31), |
| 35921 | /* 98285 */ // MIs[1] Operand 1 |
| 35922 | /* 98285 */ // No operand predicates |
| 35923 | /* 98285 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35924 | /* 98287 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2LSLri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 35925 | /* 98287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLri), |
| 35926 | /* 98290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35927 | /* 98292 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 35928 | /* 98294 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 35929 | /* 98297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35930 | /* 98300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35931 | /* 98306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35932 | /* 98312 */ GIR_RootConstrainSelectedInstOperands, |
| 35933 | /* 98313 */ // GIR_Coverage, 469, |
| 35934 | /* 98313 */ GIR_EraseRootFromParent_Done, |
| 35935 | /* 98314 */ // Label 3040: @98314 |
| 35936 | /* 98314 */ GIM_Try, /*On fail goto*//*Label 3041*/ GIMT_Encode4(98409), |
| 35937 | /* 98319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35938 | /* 98323 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35939 | /* 98327 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3042*/ GIMT_Encode4(98371), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 317 // |
| 35940 | /* 98334 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 35941 | /* 98338 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 35942 | /* 98342 */ // MIs[1] Operand 1 |
| 35943 | /* 98342 */ // No operand predicates |
| 35944 | /* 98342 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 35945 | /* 98344 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5) => (tLSLri:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5) |
| 35946 | /* 98344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLri), |
| 35947 | /* 98347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35948 | /* 98349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 35949 | /* 98355 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 35950 | /* 98357 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm5 |
| 35951 | /* 98360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35952 | /* 98363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35953 | /* 98369 */ GIR_RootConstrainSelectedInstOperands, |
| 35954 | /* 98370 */ // GIR_Coverage, 317, |
| 35955 | /* 98370 */ GIR_EraseRootFromParent_Done, |
| 35956 | /* 98371 */ // Label 3042: @98371 |
| 35957 | /* 98371 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3043*/ GIMT_Encode4(98408), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 318 // |
| 35958 | /* 98378 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35959 | /* 98382 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSLrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 35960 | /* 98382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLrr), |
| 35961 | /* 98385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 35962 | /* 98387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 35963 | /* 98393 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 35964 | /* 98395 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 35965 | /* 98397 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35966 | /* 98400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35967 | /* 98406 */ GIR_RootConstrainSelectedInstOperands, |
| 35968 | /* 98407 */ // GIR_Coverage, 318, |
| 35969 | /* 98407 */ GIR_EraseRootFromParent_Done, |
| 35970 | /* 98408 */ // Label 3043: @98408 |
| 35971 | /* 98408 */ GIM_Reject, |
| 35972 | /* 98409 */ // Label 3041: @98409 |
| 35973 | /* 98409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3044*/ GIMT_Encode4(98454), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 470 // |
| 35974 | /* 98416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35975 | /* 98420 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35976 | /* 98424 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 35977 | /* 98428 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSLrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 35978 | /* 98428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLrr), |
| 35979 | /* 98431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 35980 | /* 98433 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 35981 | /* 98435 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 35982 | /* 98437 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 35983 | /* 98440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35984 | /* 98446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 35985 | /* 98452 */ GIR_RootConstrainSelectedInstOperands, |
| 35986 | /* 98453 */ // GIR_Coverage, 470, |
| 35987 | /* 98453 */ GIR_EraseRootFromParent_Done, |
| 35988 | /* 98454 */ // Label 3044: @98454 |
| 35989 | /* 98454 */ GIM_Reject, |
| 35990 | /* 98455 */ // Label 3039: @98455 |
| 35991 | /* 98455 */ GIM_Reject, |
| 35992 | /* 98456 */ // Label 31: @98456 |
| 35993 | /* 98456 */ GIM_Try, /*On fail goto*//*Label 3045*/ GIMT_Encode4(98561), |
| 35994 | /* 98461 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 35995 | /* 98464 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 35996 | /* 98467 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 35997 | /* 98470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3046*/ GIMT_Encode4(98515), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 320 // |
| 35998 | /* 98477 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 35999 | /* 98481 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36000 | /* 98485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36001 | /* 98489 */ // (srl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 36002 | /* 98489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSRrr), |
| 36003 | /* 98492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 36004 | /* 98494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 36005 | /* 98500 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36006 | /* 98502 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36007 | /* 98504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36008 | /* 98507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36009 | /* 98513 */ GIR_RootConstrainSelectedInstOperands, |
| 36010 | /* 98514 */ // GIR_Coverage, 320, |
| 36011 | /* 98514 */ GIR_EraseRootFromParent_Done, |
| 36012 | /* 98515 */ // Label 3046: @98515 |
| 36013 | /* 98515 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3047*/ GIMT_Encode4(98560), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 472 // |
| 36014 | /* 98522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36015 | /* 98526 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36016 | /* 98530 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36017 | /* 98534 */ // (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36018 | /* 98534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSRrr), |
| 36019 | /* 98537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36020 | /* 98539 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36021 | /* 98541 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36022 | /* 98543 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36023 | /* 98546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36024 | /* 98552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36025 | /* 98558 */ GIR_RootConstrainSelectedInstOperands, |
| 36026 | /* 98559 */ // GIR_Coverage, 472, |
| 36027 | /* 98559 */ GIR_EraseRootFromParent_Done, |
| 36028 | /* 98560 */ // Label 3047: @98560 |
| 36029 | /* 98560 */ GIM_Reject, |
| 36030 | /* 98561 */ // Label 3045: @98561 |
| 36031 | /* 98561 */ GIM_Reject, |
| 36032 | /* 98562 */ // Label 32: @98562 |
| 36033 | /* 98562 */ GIM_Try, /*On fail goto*//*Label 3048*/ GIMT_Encode4(98829), |
| 36034 | /* 98567 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36035 | /* 98570 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36036 | /* 98573 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36037 | /* 98576 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3049*/ GIMT_Encode4(98630), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 200 // |
| 36038 | /* 98583 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36039 | /* 98587 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36040 | /* 98591 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36041 | /* 98595 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36042 | /* 98599 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36043 | /* 98604 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36044 | /* 98608 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36045 | /* 98610 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 36046 | /* 98610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH), |
| 36047 | /* 98613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36048 | /* 98615 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36049 | /* 98619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36050 | /* 98622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36051 | /* 98628 */ GIR_RootConstrainSelectedInstOperands, |
| 36052 | /* 98629 */ // GIR_Coverage, 200, |
| 36053 | /* 98629 */ GIR_EraseRootFromParent_Done, |
| 36054 | /* 98630 */ // Label 3049: @98630 |
| 36055 | /* 98630 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3050*/ GIMT_Encode4(98684), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 327 // |
| 36056 | /* 98637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36057 | /* 98641 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36058 | /* 98645 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36059 | /* 98649 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36060 | /* 98653 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36061 | /* 98658 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36062 | /* 98662 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36063 | /* 98664 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREVSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 36064 | /* 98664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREVSH), |
| 36065 | /* 98667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36066 | /* 98669 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36067 | /* 98673 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36068 | /* 98676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36069 | /* 98682 */ GIR_RootConstrainSelectedInstOperands, |
| 36070 | /* 98683 */ // GIR_Coverage, 327, |
| 36071 | /* 98683 */ GIR_EraseRootFromParent_Done, |
| 36072 | /* 98684 */ // Label 3050: @98684 |
| 36073 | /* 98684 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3051*/ GIMT_Encode4(98738), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 537 // |
| 36074 | /* 98691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36075 | /* 98695 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36076 | /* 98699 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36077 | /* 98703 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36078 | /* 98707 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36079 | /* 98712 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36080 | /* 98716 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36081 | /* 98718 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 36082 | /* 98718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH), |
| 36083 | /* 98721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36084 | /* 98723 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36085 | /* 98727 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36086 | /* 98730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36087 | /* 98736 */ GIR_RootConstrainSelectedInstOperands, |
| 36088 | /* 98737 */ // GIR_Coverage, 537, |
| 36089 | /* 98737 */ GIR_EraseRootFromParent_Done, |
| 36090 | /* 98738 */ // Label 3051: @98738 |
| 36091 | /* 98738 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3052*/ GIMT_Encode4(98783), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 311 // |
| 36092 | /* 98745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36093 | /* 98749 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36094 | /* 98753 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36095 | /* 98757 */ // (sra:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tASRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 36096 | /* 98757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tASRrr), |
| 36097 | /* 98760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 36098 | /* 98762 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 36099 | /* 98768 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36100 | /* 98770 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36101 | /* 98772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36102 | /* 98775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36103 | /* 98781 */ GIR_RootConstrainSelectedInstOperands, |
| 36104 | /* 98782 */ // GIR_Coverage, 311, |
| 36105 | /* 98782 */ GIR_EraseRootFromParent_Done, |
| 36106 | /* 98783 */ // Label 3052: @98783 |
| 36107 | /* 98783 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3053*/ GIMT_Encode4(98828), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 474 // |
| 36108 | /* 98790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36109 | /* 98794 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36110 | /* 98798 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36111 | /* 98802 */ // (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ASRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36112 | /* 98802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ASRrr), |
| 36113 | /* 98805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36114 | /* 98807 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36115 | /* 98809 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36116 | /* 98811 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36117 | /* 98814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36118 | /* 98820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36119 | /* 98826 */ GIR_RootConstrainSelectedInstOperands, |
| 36120 | /* 98827 */ // GIR_Coverage, 474, |
| 36121 | /* 98827 */ GIR_EraseRootFromParent_Done, |
| 36122 | /* 98828 */ // Label 3053: @98828 |
| 36123 | /* 98828 */ GIM_Reject, |
| 36124 | /* 98829 */ // Label 3048: @98829 |
| 36125 | /* 98829 */ GIM_Reject, |
| 36126 | /* 98830 */ // Label 33: @98830 |
| 36127 | /* 98830 */ GIM_Try, /*On fail goto*//*Label 3054*/ GIMT_Encode4(99155), |
| 36128 | /* 98835 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 36129 | /* 98838 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36130 | /* 98841 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36131 | /* 98844 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3055*/ GIMT_Encode4(98898), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 199 // |
| 36132 | /* 98851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36133 | /* 98855 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36134 | /* 98859 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36135 | /* 98863 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36136 | /* 98867 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36137 | /* 98872 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36138 | /* 98876 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36139 | /* 98878 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REV16:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 36140 | /* 98878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV16), |
| 36141 | /* 98881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36142 | /* 98883 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36143 | /* 98887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36144 | /* 98890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36145 | /* 98896 */ GIR_RootConstrainSelectedInstOperands, |
| 36146 | /* 98897 */ // GIR_Coverage, 199, |
| 36147 | /* 98897 */ GIR_EraseRootFromParent_Done, |
| 36148 | /* 98898 */ // Label 3055: @98898 |
| 36149 | /* 98898 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3056*/ GIMT_Encode4(98952), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 326 // |
| 36150 | /* 98905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36151 | /* 98909 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36152 | /* 98913 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36153 | /* 98917 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36154 | /* 98921 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36155 | /* 98926 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36156 | /* 98930 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36157 | /* 98932 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREV16:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 36158 | /* 98932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV16), |
| 36159 | /* 98935 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36160 | /* 98937 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36161 | /* 98941 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36162 | /* 98944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36163 | /* 98950 */ GIR_RootConstrainSelectedInstOperands, |
| 36164 | /* 98951 */ // GIR_Coverage, 326, |
| 36165 | /* 98951 */ GIR_EraseRootFromParent_Done, |
| 36166 | /* 98952 */ // Label 3056: @98952 |
| 36167 | /* 98952 */ GIM_Try, /*On fail goto*//*Label 3057*/ GIMT_Encode4(99064), |
| 36168 | /* 98957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36169 | /* 98961 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3058*/ GIMT_Encode4(99011), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 536 // |
| 36170 | /* 98968 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36171 | /* 98972 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 36172 | /* 98976 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36173 | /* 98980 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36174 | /* 98985 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16, |
| 36175 | /* 98989 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36176 | /* 98991 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REV16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 36177 | /* 98991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV16), |
| 36178 | /* 98994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36179 | /* 98996 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm |
| 36180 | /* 99000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36181 | /* 99003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36182 | /* 99009 */ GIR_RootConstrainSelectedInstOperands, |
| 36183 | /* 99010 */ // GIR_Coverage, 536, |
| 36184 | /* 99010 */ GIR_EraseRootFromParent_Done, |
| 36185 | /* 99011 */ // Label 3058: @99011 |
| 36186 | /* 99011 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3059*/ GIMT_Encode4(99063), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 475 // |
| 36187 | /* 99018 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36188 | /* 99022 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36189 | /* 99026 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 36190 | /* 99030 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31), |
| 36191 | /* 99034 */ // MIs[1] Operand 1 |
| 36192 | /* 99034 */ // No operand predicates |
| 36193 | /* 99034 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36194 | /* 99036 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2RORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm) |
| 36195 | /* 99036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORri), |
| 36196 | /* 99039 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36197 | /* 99041 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36198 | /* 99043 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm |
| 36199 | /* 99046 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36200 | /* 99049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36201 | /* 99055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36202 | /* 99061 */ GIR_RootConstrainSelectedInstOperands, |
| 36203 | /* 99062 */ // GIR_Coverage, 475, |
| 36204 | /* 99062 */ GIR_EraseRootFromParent_Done, |
| 36205 | /* 99063 */ // Label 3059: @99063 |
| 36206 | /* 99063 */ GIM_Reject, |
| 36207 | /* 99064 */ // Label 3057: @99064 |
| 36208 | /* 99064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3060*/ GIMT_Encode4(99109), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 328 // |
| 36209 | /* 99071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36210 | /* 99075 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36211 | /* 99079 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 36212 | /* 99083 */ // (rotr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tROR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) |
| 36213 | /* 99083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tROR), |
| 36214 | /* 99086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn] |
| 36215 | /* 99088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 36216 | /* 99094 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36217 | /* 99096 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36218 | /* 99098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36219 | /* 99101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36220 | /* 99107 */ GIR_RootConstrainSelectedInstOperands, |
| 36221 | /* 99108 */ // GIR_Coverage, 328, |
| 36222 | /* 99108 */ GIR_EraseRootFromParent_Done, |
| 36223 | /* 99109 */ // Label 3060: @99109 |
| 36224 | /* 99109 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3061*/ GIMT_Encode4(99154), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 476 // |
| 36225 | /* 99116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36226 | /* 99120 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36227 | /* 99124 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36228 | /* 99128 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2RORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36229 | /* 99128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORrr), |
| 36230 | /* 99131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36231 | /* 99133 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36232 | /* 99135 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36233 | /* 99137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36234 | /* 99140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36235 | /* 99146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36236 | /* 99152 */ GIR_RootConstrainSelectedInstOperands, |
| 36237 | /* 99153 */ // GIR_Coverage, 476, |
| 36238 | /* 99153 */ GIR_EraseRootFromParent_Done, |
| 36239 | /* 99154 */ // Label 3061: @99154 |
| 36240 | /* 99154 */ GIM_Reject, |
| 36241 | /* 99155 */ // Label 3054: @99155 |
| 36242 | /* 99155 */ GIM_Reject, |
| 36243 | /* 99156 */ // Label 34: @99156 |
| 36244 | /* 99156 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 3065*/ GIMT_Encode4(99388), |
| 36245 | /* 99167 */ /*GILLT_v16s8*//*Label 3062*/ GIMT_Encode4(99187), GIMT_Encode4(0), |
| 36246 | /* 99175 */ /*GILLT_v8s16*//*Label 3063*/ GIMT_Encode4(99254), GIMT_Encode4(0), |
| 36247 | /* 99183 */ /*GILLT_v4s32*//*Label 3064*/ GIMT_Encode4(99321), |
| 36248 | /* 99187 */ // Label 3062: @99187 |
| 36249 | /* 99187 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3066*/ GIMT_Encode4(99253), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4958 // |
| 36250 | /* 99194 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 36251 | /* 99197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36252 | /* 99200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36253 | /* 99204 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36254 | /* 99208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36255 | /* 99212 */ // (mulhu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 36256 | /* 99212 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36257 | /* 99215 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36258 | /* 99219 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36259 | /* 99224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8), |
| 36260 | /* 99227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36261 | /* 99229 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36262 | /* 99231 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36263 | /* 99233 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36264 | /* 99236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36265 | /* 99242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36266 | /* 99248 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36267 | /* 99251 */ GIR_RootConstrainSelectedInstOperands, |
| 36268 | /* 99252 */ // GIR_Coverage, 4958, |
| 36269 | /* 99252 */ GIR_EraseRootFromParent_Done, |
| 36270 | /* 99253 */ // Label 3066: @99253 |
| 36271 | /* 99253 */ GIM_Reject, |
| 36272 | /* 99254 */ // Label 3063: @99254 |
| 36273 | /* 99254 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3067*/ GIMT_Encode4(99320), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4962 // |
| 36274 | /* 99261 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 36275 | /* 99264 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36276 | /* 99267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36277 | /* 99271 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36278 | /* 99275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36279 | /* 99279 */ // (mulhu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 36280 | /* 99279 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36281 | /* 99282 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36282 | /* 99286 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36283 | /* 99291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16), |
| 36284 | /* 99294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36285 | /* 99296 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36286 | /* 99298 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36287 | /* 99300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36288 | /* 99303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36289 | /* 99309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36290 | /* 99315 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36291 | /* 99318 */ GIR_RootConstrainSelectedInstOperands, |
| 36292 | /* 99319 */ // GIR_Coverage, 4962, |
| 36293 | /* 99319 */ GIR_EraseRootFromParent_Done, |
| 36294 | /* 99320 */ // Label 3067: @99320 |
| 36295 | /* 99320 */ GIM_Reject, |
| 36296 | /* 99321 */ // Label 3064: @99321 |
| 36297 | /* 99321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3068*/ GIMT_Encode4(99387), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4966 // |
| 36298 | /* 99328 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 36299 | /* 99331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36300 | /* 99334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36301 | /* 99338 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36302 | /* 99342 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36303 | /* 99346 */ // (mulhu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 36304 | /* 99346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36305 | /* 99349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36306 | /* 99353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36307 | /* 99358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32), |
| 36308 | /* 99361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36309 | /* 99363 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36310 | /* 99365 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36311 | /* 99367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36312 | /* 99370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36313 | /* 99376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36314 | /* 99382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36315 | /* 99385 */ GIR_RootConstrainSelectedInstOperands, |
| 36316 | /* 99386 */ // GIR_Coverage, 4966, |
| 36317 | /* 99386 */ GIR_EraseRootFromParent_Done, |
| 36318 | /* 99387 */ // Label 3068: @99387 |
| 36319 | /* 99387 */ GIM_Reject, |
| 36320 | /* 99388 */ // Label 3065: @99388 |
| 36321 | /* 99388 */ GIM_Reject, |
| 36322 | /* 99389 */ // Label 35: @99389 |
| 36323 | /* 99389 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3073*/ GIMT_Encode4(99740), |
| 36324 | /* 99400 */ /*GILLT_s32*//*Label 3069*/ GIMT_Encode4(99448), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36325 | /* 99428 */ /*GILLT_v16s8*//*Label 3070*/ GIMT_Encode4(99539), GIMT_Encode4(0), |
| 36326 | /* 99436 */ /*GILLT_v8s16*//*Label 3071*/ GIMT_Encode4(99606), GIMT_Encode4(0), |
| 36327 | /* 99444 */ /*GILLT_v4s32*//*Label 3072*/ GIMT_Encode4(99673), |
| 36328 | /* 99448 */ // Label 3069: @99448 |
| 36329 | /* 99448 */ GIM_Try, /*On fail goto*//*Label 3074*/ GIMT_Encode4(99538), |
| 36330 | /* 99453 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36331 | /* 99456 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36332 | /* 99459 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3075*/ GIMT_Encode4(99498), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 177 // |
| 36333 | /* 99466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36334 | /* 99470 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36335 | /* 99474 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36336 | /* 99478 */ // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SMMUL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) |
| 36337 | /* 99478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMUL), |
| 36338 | /* 99481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36339 | /* 99483 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36340 | /* 99485 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36341 | /* 99487 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36342 | /* 99490 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36343 | /* 99496 */ GIR_RootConstrainSelectedInstOperands, |
| 36344 | /* 99497 */ // GIR_Coverage, 177, |
| 36345 | /* 99497 */ GIR_EraseRootFromParent_Done, |
| 36346 | /* 99498 */ // Label 3075: @99498 |
| 36347 | /* 99498 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3076*/ GIMT_Encode4(99537), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 506 // |
| 36348 | /* 99505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36349 | /* 99509 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36350 | /* 99513 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36351 | /* 99517 */ // (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMMUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) |
| 36352 | /* 99517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMUL), |
| 36353 | /* 99520 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36354 | /* 99522 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn |
| 36355 | /* 99524 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36356 | /* 99526 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36357 | /* 99529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36358 | /* 99535 */ GIR_RootConstrainSelectedInstOperands, |
| 36359 | /* 99536 */ // GIR_Coverage, 506, |
| 36360 | /* 99536 */ GIR_EraseRootFromParent_Done, |
| 36361 | /* 99537 */ // Label 3076: @99537 |
| 36362 | /* 99537 */ GIM_Reject, |
| 36363 | /* 99538 */ // Label 3074: @99538 |
| 36364 | /* 99538 */ GIM_Reject, |
| 36365 | /* 99539 */ // Label 3070: @99539 |
| 36366 | /* 99539 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3077*/ GIMT_Encode4(99605), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4947 // |
| 36367 | /* 99546 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 36368 | /* 99549 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36369 | /* 99552 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36370 | /* 99556 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36371 | /* 99560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36372 | /* 99564 */ // (mulhs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 36373 | /* 99564 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36374 | /* 99567 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36375 | /* 99571 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36376 | /* 99576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8), |
| 36377 | /* 99579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36378 | /* 99581 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36379 | /* 99583 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36380 | /* 99585 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36381 | /* 99588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36382 | /* 99594 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36383 | /* 99600 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36384 | /* 99603 */ GIR_RootConstrainSelectedInstOperands, |
| 36385 | /* 99604 */ // GIR_Coverage, 4947, |
| 36386 | /* 99604 */ GIR_EraseRootFromParent_Done, |
| 36387 | /* 99605 */ // Label 3077: @99605 |
| 36388 | /* 99605 */ GIM_Reject, |
| 36389 | /* 99606 */ // Label 3071: @99606 |
| 36390 | /* 99606 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3078*/ GIMT_Encode4(99672), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4950 // |
| 36391 | /* 99613 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 36392 | /* 99616 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36393 | /* 99619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36394 | /* 99623 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36395 | /* 99627 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36396 | /* 99631 */ // (mulhs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 36397 | /* 99631 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36398 | /* 99634 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36399 | /* 99638 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36400 | /* 99643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16), |
| 36401 | /* 99646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36402 | /* 99648 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36403 | /* 99650 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36404 | /* 99652 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36405 | /* 99655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36406 | /* 99661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36407 | /* 99667 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36408 | /* 99670 */ GIR_RootConstrainSelectedInstOperands, |
| 36409 | /* 99671 */ // GIR_Coverage, 4950, |
| 36410 | /* 99671 */ GIR_EraseRootFromParent_Done, |
| 36411 | /* 99672 */ // Label 3078: @99672 |
| 36412 | /* 99672 */ GIM_Reject, |
| 36413 | /* 99673 */ // Label 3072: @99673 |
| 36414 | /* 99673 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3079*/ GIMT_Encode4(99739), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4954 // |
| 36415 | /* 99680 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 36416 | /* 99683 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36417 | /* 99686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36418 | /* 99690 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36419 | /* 99694 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36420 | /* 99698 */ // (mulhs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 36421 | /* 99698 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36422 | /* 99701 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36423 | /* 99705 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36424 | /* 99710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32), |
| 36425 | /* 99713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36426 | /* 99715 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36427 | /* 99717 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36428 | /* 99719 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36429 | /* 99722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36430 | /* 99728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36431 | /* 99734 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36432 | /* 99737 */ GIR_RootConstrainSelectedInstOperands, |
| 36433 | /* 99738 */ // GIR_Coverage, 4954, |
| 36434 | /* 99738 */ GIR_EraseRootFromParent_Done, |
| 36435 | /* 99739 */ // Label 3079: @99739 |
| 36436 | /* 99739 */ GIM_Reject, |
| 36437 | /* 99740 */ // Label 3073: @99740 |
| 36438 | /* 99740 */ GIM_Reject, |
| 36439 | /* 99741 */ // Label 36: @99741 |
| 36440 | /* 99741 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 3088*/ GIMT_Encode4(100366), |
| 36441 | /* 99752 */ /*GILLT_s64*//*Label 3080*/ GIMT_Encode4(99800), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36442 | /* 99772 */ /*GILLT_v8s8*//*Label 3081*/ GIMT_Encode4(99846), |
| 36443 | /* 99776 */ /*GILLT_v16s8*//*Label 3082*/ GIMT_Encode4(99892), |
| 36444 | /* 99780 */ /*GILLT_v4s16*//*Label 3083*/ GIMT_Encode4(100004), |
| 36445 | /* 99784 */ /*GILLT_v8s16*//*Label 3084*/ GIMT_Encode4(100050), |
| 36446 | /* 99788 */ /*GILLT_v2s32*//*Label 3085*/ GIMT_Encode4(100162), |
| 36447 | /* 99792 */ /*GILLT_v4s32*//*Label 3086*/ GIMT_Encode4(100208), |
| 36448 | /* 99796 */ /*GILLT_v2s64*//*Label 3087*/ GIMT_Encode4(100320), |
| 36449 | /* 99800 */ // Label 3080: @99800 |
| 36450 | /* 99800 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3089*/ GIMT_Encode4(99845), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 950 // |
| 36451 | /* 99807 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 36452 | /* 99810 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 36453 | /* 99813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36454 | /* 99817 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36455 | /* 99821 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36456 | /* 99825 */ // (uaddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 36457 | /* 99825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv1i64), |
| 36458 | /* 99828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36459 | /* 99830 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36460 | /* 99832 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36461 | /* 99834 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36462 | /* 99837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36463 | /* 99843 */ GIR_RootConstrainSelectedInstOperands, |
| 36464 | /* 99844 */ // GIR_Coverage, 950, |
| 36465 | /* 99844 */ GIR_EraseRootFromParent_Done, |
| 36466 | /* 99845 */ // Label 3089: @99845 |
| 36467 | /* 99845 */ GIM_Reject, |
| 36468 | /* 99846 */ // Label 3081: @99846 |
| 36469 | /* 99846 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3090*/ GIMT_Encode4(99891), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 948 // |
| 36470 | /* 99853 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 36471 | /* 99856 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 36472 | /* 99859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36473 | /* 99863 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36474 | /* 99867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36475 | /* 99871 */ // (uaddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 36476 | /* 99871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i8), |
| 36477 | /* 99874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36478 | /* 99876 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36479 | /* 99878 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36480 | /* 99880 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36481 | /* 99883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36482 | /* 99889 */ GIR_RootConstrainSelectedInstOperands, |
| 36483 | /* 99890 */ // GIR_Coverage, 948, |
| 36484 | /* 99890 */ GIR_EraseRootFromParent_Done, |
| 36485 | /* 99891 */ // Label 3090: @99891 |
| 36486 | /* 99891 */ GIM_Reject, |
| 36487 | /* 99892 */ // Label 3082: @99892 |
| 36488 | /* 99892 */ GIM_Try, /*On fail goto*//*Label 3091*/ GIMT_Encode4(100003), |
| 36489 | /* 99897 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 36490 | /* 99900 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36491 | /* 99903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3092*/ GIMT_Encode4(99942), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 949 // |
| 36492 | /* 99910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36493 | /* 99914 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36494 | /* 99918 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36495 | /* 99922 */ // (uaddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 36496 | /* 99922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv16i8), |
| 36497 | /* 99925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36498 | /* 99927 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36499 | /* 99929 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36500 | /* 99931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36501 | /* 99934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36502 | /* 99940 */ GIR_RootConstrainSelectedInstOperands, |
| 36503 | /* 99941 */ // GIR_Coverage, 949, |
| 36504 | /* 99941 */ GIR_EraseRootFromParent_Done, |
| 36505 | /* 99942 */ // Label 3092: @99942 |
| 36506 | /* 99942 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3093*/ GIMT_Encode4(100002), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3915 // |
| 36507 | /* 99949 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36508 | /* 99953 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36509 | /* 99957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36510 | /* 99961 */ // (uaddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 36511 | /* 99961 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36512 | /* 99964 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36513 | /* 99968 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36514 | /* 99973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu8), |
| 36515 | /* 99976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36516 | /* 99978 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36517 | /* 99980 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36518 | /* 99982 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36519 | /* 99985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36520 | /* 99991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36521 | /* 99997 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36522 | /* 100000 */ GIR_RootConstrainSelectedInstOperands, |
| 36523 | /* 100001 */ // GIR_Coverage, 3915, |
| 36524 | /* 100001 */ GIR_EraseRootFromParent_Done, |
| 36525 | /* 100002 */ // Label 3093: @100002 |
| 36526 | /* 100002 */ GIM_Reject, |
| 36527 | /* 100003 */ // Label 3091: @100003 |
| 36528 | /* 100003 */ GIM_Reject, |
| 36529 | /* 100004 */ // Label 3083: @100004 |
| 36530 | /* 100004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3094*/ GIMT_Encode4(100049), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 944 // |
| 36531 | /* 100011 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 36532 | /* 100014 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36533 | /* 100017 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36534 | /* 100021 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36535 | /* 100025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36536 | /* 100029 */ // (uaddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 36537 | /* 100029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i16), |
| 36538 | /* 100032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36539 | /* 100034 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36540 | /* 100036 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36541 | /* 100038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36542 | /* 100041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36543 | /* 100047 */ GIR_RootConstrainSelectedInstOperands, |
| 36544 | /* 100048 */ // GIR_Coverage, 944, |
| 36545 | /* 100048 */ GIR_EraseRootFromParent_Done, |
| 36546 | /* 100049 */ // Label 3094: @100049 |
| 36547 | /* 100049 */ GIM_Reject, |
| 36548 | /* 100050 */ // Label 3084: @100050 |
| 36549 | /* 100050 */ GIM_Try, /*On fail goto*//*Label 3095*/ GIMT_Encode4(100161), |
| 36550 | /* 100055 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 36551 | /* 100058 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36552 | /* 100061 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3096*/ GIMT_Encode4(100100), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 946 // |
| 36553 | /* 100068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36554 | /* 100072 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36555 | /* 100076 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36556 | /* 100080 */ // (uaddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 36557 | /* 100080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i16), |
| 36558 | /* 100083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36559 | /* 100085 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36560 | /* 100087 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36561 | /* 100089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36562 | /* 100092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36563 | /* 100098 */ GIR_RootConstrainSelectedInstOperands, |
| 36564 | /* 100099 */ // GIR_Coverage, 946, |
| 36565 | /* 100099 */ GIR_EraseRootFromParent_Done, |
| 36566 | /* 100100 */ // Label 3096: @100100 |
| 36567 | /* 100100 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3097*/ GIMT_Encode4(100160), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3918 // |
| 36568 | /* 100107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36569 | /* 100111 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36570 | /* 100115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36571 | /* 100119 */ // (uaddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 36572 | /* 100119 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36573 | /* 100122 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36574 | /* 100126 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36575 | /* 100131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu16), |
| 36576 | /* 100134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36577 | /* 100136 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36578 | /* 100138 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36579 | /* 100140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36580 | /* 100143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36581 | /* 100149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36582 | /* 100155 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36583 | /* 100158 */ GIR_RootConstrainSelectedInstOperands, |
| 36584 | /* 100159 */ // GIR_Coverage, 3918, |
| 36585 | /* 100159 */ GIR_EraseRootFromParent_Done, |
| 36586 | /* 100160 */ // Label 3097: @100160 |
| 36587 | /* 100160 */ GIM_Reject, |
| 36588 | /* 100161 */ // Label 3095: @100161 |
| 36589 | /* 100161 */ GIM_Reject, |
| 36590 | /* 100162 */ // Label 3085: @100162 |
| 36591 | /* 100162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3098*/ GIMT_Encode4(100207), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 945 // |
| 36592 | /* 100169 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 36593 | /* 100172 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 36594 | /* 100175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36595 | /* 100179 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36596 | /* 100183 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36597 | /* 100187 */ // (uaddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 36598 | /* 100187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i32), |
| 36599 | /* 100190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36600 | /* 100192 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36601 | /* 100194 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36602 | /* 100196 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36603 | /* 100199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36604 | /* 100205 */ GIR_RootConstrainSelectedInstOperands, |
| 36605 | /* 100206 */ // GIR_Coverage, 945, |
| 36606 | /* 100206 */ GIR_EraseRootFromParent_Done, |
| 36607 | /* 100207 */ // Label 3098: @100207 |
| 36608 | /* 100207 */ GIM_Reject, |
| 36609 | /* 100208 */ // Label 3086: @100208 |
| 36610 | /* 100208 */ GIM_Try, /*On fail goto*//*Label 3099*/ GIMT_Encode4(100319), |
| 36611 | /* 100213 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 36612 | /* 100216 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36613 | /* 100219 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3100*/ GIMT_Encode4(100258), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 947 // |
| 36614 | /* 100226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36615 | /* 100230 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36616 | /* 100234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36617 | /* 100238 */ // (uaddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 36618 | /* 100238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i32), |
| 36619 | /* 100241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36620 | /* 100243 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36621 | /* 100245 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36622 | /* 100247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36623 | /* 100250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36624 | /* 100256 */ GIR_RootConstrainSelectedInstOperands, |
| 36625 | /* 100257 */ // GIR_Coverage, 947, |
| 36626 | /* 100257 */ GIR_EraseRootFromParent_Done, |
| 36627 | /* 100258 */ // Label 3100: @100258 |
| 36628 | /* 100258 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3101*/ GIMT_Encode4(100318), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3921 // |
| 36629 | /* 100265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36630 | /* 100269 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36631 | /* 100273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36632 | /* 100277 */ // (uaddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 36633 | /* 100277 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36634 | /* 100280 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36635 | /* 100284 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36636 | /* 100289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu32), |
| 36637 | /* 100292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36638 | /* 100294 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36639 | /* 100296 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36640 | /* 100298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36641 | /* 100301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36642 | /* 100307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36643 | /* 100313 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36644 | /* 100316 */ GIR_RootConstrainSelectedInstOperands, |
| 36645 | /* 100317 */ // GIR_Coverage, 3921, |
| 36646 | /* 100317 */ GIR_EraseRootFromParent_Done, |
| 36647 | /* 100318 */ // Label 3101: @100318 |
| 36648 | /* 100318 */ GIM_Reject, |
| 36649 | /* 100319 */ // Label 3099: @100319 |
| 36650 | /* 100319 */ GIM_Reject, |
| 36651 | /* 100320 */ // Label 3087: @100320 |
| 36652 | /* 100320 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3102*/ GIMT_Encode4(100365), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 951 // |
| 36653 | /* 100327 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 36654 | /* 100330 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 36655 | /* 100333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36656 | /* 100337 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36657 | /* 100341 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36658 | /* 100345 */ // (uaddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 36659 | /* 100345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i64), |
| 36660 | /* 100348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36661 | /* 100350 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36662 | /* 100352 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36663 | /* 100354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36664 | /* 100357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36665 | /* 100363 */ GIR_RootConstrainSelectedInstOperands, |
| 36666 | /* 100364 */ // GIR_Coverage, 951, |
| 36667 | /* 100364 */ GIR_EraseRootFromParent_Done, |
| 36668 | /* 100365 */ // Label 3102: @100365 |
| 36669 | /* 100365 */ GIM_Reject, |
| 36670 | /* 100366 */ // Label 3088: @100366 |
| 36671 | /* 100366 */ GIM_Reject, |
| 36672 | /* 100367 */ // Label 37: @100367 |
| 36673 | /* 100367 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 3112*/ GIMT_Encode4(101639), |
| 36674 | /* 100378 */ /*GILLT_s32*//*Label 3103*/ GIMT_Encode4(100430), |
| 36675 | /* 100382 */ /*GILLT_s64*//*Label 3104*/ GIMT_Encode4(100765), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 36676 | /* 100402 */ /*GILLT_v8s8*//*Label 3105*/ GIMT_Encode4(100811), |
| 36677 | /* 100406 */ /*GILLT_v16s8*//*Label 3106*/ GIMT_Encode4(100857), |
| 36678 | /* 100410 */ /*GILLT_v4s16*//*Label 3107*/ GIMT_Encode4(100969), |
| 36679 | /* 100414 */ /*GILLT_v8s16*//*Label 3108*/ GIMT_Encode4(101015), |
| 36680 | /* 100418 */ /*GILLT_v2s32*//*Label 3109*/ GIMT_Encode4(101127), |
| 36681 | /* 100422 */ /*GILLT_v4s32*//*Label 3110*/ GIMT_Encode4(101173), |
| 36682 | /* 100426 */ /*GILLT_v2s64*//*Label 3111*/ GIMT_Encode4(101439), |
| 36683 | /* 100430 */ // Label 3103: @100430 |
| 36684 | /* 100430 */ GIM_Try, /*On fail goto*//*Label 3113*/ GIMT_Encode4(100764), |
| 36685 | /* 100435 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 36686 | /* 100438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 36687 | /* 100441 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3114*/ GIMT_Encode4(100502), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 6245 // |
| 36688 | /* 100448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36689 | /* 100452 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36690 | /* 100456 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 36691 | /* 100460 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36692 | /* 100464 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36693 | /* 100469 */ // MIs[1] Rn |
| 36694 | /* 100469 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 36695 | /* 100474 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36696 | /* 100478 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36697 | /* 100480 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36698 | /* 100480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 36699 | /* 100483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36700 | /* 100485 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36701 | /* 100487 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 36702 | /* 100491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36703 | /* 100494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36704 | /* 100500 */ GIR_RootConstrainSelectedInstOperands, |
| 36705 | /* 100501 */ // GIR_Coverage, 6245, |
| 36706 | /* 100501 */ GIR_EraseRootFromParent_Done, |
| 36707 | /* 100502 */ // Label 3114: @100502 |
| 36708 | /* 100502 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3115*/ GIMT_Encode4(100563), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6283 // |
| 36709 | /* 100509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36710 | /* 100513 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36711 | /* 100517 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 36712 | /* 100521 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36713 | /* 100525 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36714 | /* 100530 */ // MIs[1] Rn |
| 36715 | /* 100530 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 36716 | /* 100535 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36717 | /* 100539 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36718 | /* 100541 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36719 | /* 100541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 36720 | /* 100544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36721 | /* 100546 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm |
| 36722 | /* 100548 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 36723 | /* 100552 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36724 | /* 100555 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36725 | /* 100561 */ GIR_RootConstrainSelectedInstOperands, |
| 36726 | /* 100562 */ // GIR_Coverage, 6283, |
| 36727 | /* 100562 */ GIR_EraseRootFromParent_Done, |
| 36728 | /* 100563 */ // Label 3115: @100563 |
| 36729 | /* 100563 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3116*/ GIMT_Encode4(100624), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2058 // |
| 36730 | /* 100570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36731 | /* 100574 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36732 | /* 100578 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36733 | /* 100582 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 36734 | /* 100586 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36735 | /* 100590 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36736 | /* 100595 */ // MIs[1] Rn |
| 36737 | /* 100595 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 36738 | /* 100600 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36739 | /* 100602 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36740 | /* 100602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD), |
| 36741 | /* 100605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36742 | /* 100607 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36743 | /* 100609 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 36744 | /* 100613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36745 | /* 100616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36746 | /* 100622 */ GIR_RootConstrainSelectedInstOperands, |
| 36747 | /* 100623 */ // GIR_Coverage, 2058, |
| 36748 | /* 100623 */ GIR_EraseRootFromParent_Done, |
| 36749 | /* 100624 */ // Label 3116: @100624 |
| 36750 | /* 100624 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3117*/ GIMT_Encode4(100685), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2330 // |
| 36751 | /* 100631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36752 | /* 100635 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36753 | /* 100639 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36754 | /* 100643 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 36755 | /* 100647 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 36756 | /* 100651 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36757 | /* 100656 */ // MIs[1] Rn |
| 36758 | /* 100656 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 36759 | /* 100661 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36760 | /* 100663 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36761 | /* 100663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD), |
| 36762 | /* 100666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36763 | /* 100668 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36764 | /* 100670 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 36765 | /* 100674 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36766 | /* 100677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36767 | /* 100683 */ GIR_RootConstrainSelectedInstOperands, |
| 36768 | /* 100684 */ // GIR_Coverage, 2330, |
| 36769 | /* 100684 */ GIR_EraseRootFromParent_Done, |
| 36770 | /* 100685 */ // Label 3117: @100685 |
| 36771 | /* 100685 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3118*/ GIMT_Encode4(100724), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2056 // |
| 36772 | /* 100692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 36773 | /* 100696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36774 | /* 100700 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 36775 | /* 100704 */ // (saddsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QADD:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 36776 | /* 100704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD), |
| 36777 | /* 100707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36778 | /* 100709 */ GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 36779 | /* 100711 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 36780 | /* 100713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36781 | /* 100716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36782 | /* 100722 */ GIR_RootConstrainSelectedInstOperands, |
| 36783 | /* 100723 */ // GIR_Coverage, 2056, |
| 36784 | /* 100723 */ GIR_EraseRootFromParent_Done, |
| 36785 | /* 100724 */ // Label 3118: @100724 |
| 36786 | /* 100724 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3119*/ GIMT_Encode4(100763), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2328 // |
| 36787 | /* 100731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36788 | /* 100735 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36789 | /* 100739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 36790 | /* 100743 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 36791 | /* 100743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD), |
| 36792 | /* 100746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 36793 | /* 100748 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 36794 | /* 100750 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 36795 | /* 100752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36796 | /* 100755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36797 | /* 100761 */ GIR_RootConstrainSelectedInstOperands, |
| 36798 | /* 100762 */ // GIR_Coverage, 2328, |
| 36799 | /* 100762 */ GIR_EraseRootFromParent_Done, |
| 36800 | /* 100763 */ // Label 3119: @100763 |
| 36801 | /* 100763 */ GIM_Reject, |
| 36802 | /* 100764 */ // Label 3113: @100764 |
| 36803 | /* 100764 */ GIM_Reject, |
| 36804 | /* 100765 */ // Label 3104: @100765 |
| 36805 | /* 100765 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3120*/ GIMT_Encode4(100810), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 942 // |
| 36806 | /* 100772 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 36807 | /* 100775 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 36808 | /* 100778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36809 | /* 100782 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36810 | /* 100786 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36811 | /* 100790 */ // (saddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 36812 | /* 100790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv1i64), |
| 36813 | /* 100793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36814 | /* 100795 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36815 | /* 100797 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36816 | /* 100799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36817 | /* 100802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36818 | /* 100808 */ GIR_RootConstrainSelectedInstOperands, |
| 36819 | /* 100809 */ // GIR_Coverage, 942, |
| 36820 | /* 100809 */ GIR_EraseRootFromParent_Done, |
| 36821 | /* 100810 */ // Label 3120: @100810 |
| 36822 | /* 100810 */ GIM_Reject, |
| 36823 | /* 100811 */ // Label 3105: @100811 |
| 36824 | /* 100811 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3121*/ GIMT_Encode4(100856), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 940 // |
| 36825 | /* 100818 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 36826 | /* 100821 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 36827 | /* 100824 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36828 | /* 100828 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36829 | /* 100832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36830 | /* 100836 */ // (saddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 36831 | /* 100836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i8), |
| 36832 | /* 100839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36833 | /* 100841 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36834 | /* 100843 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36835 | /* 100845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36836 | /* 100848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36837 | /* 100854 */ GIR_RootConstrainSelectedInstOperands, |
| 36838 | /* 100855 */ // GIR_Coverage, 940, |
| 36839 | /* 100855 */ GIR_EraseRootFromParent_Done, |
| 36840 | /* 100856 */ // Label 3121: @100856 |
| 36841 | /* 100856 */ GIM_Reject, |
| 36842 | /* 100857 */ // Label 3106: @100857 |
| 36843 | /* 100857 */ GIM_Try, /*On fail goto*//*Label 3122*/ GIMT_Encode4(100968), |
| 36844 | /* 100862 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 36845 | /* 100865 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 36846 | /* 100868 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3123*/ GIMT_Encode4(100907), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 941 // |
| 36847 | /* 100875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36848 | /* 100879 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36849 | /* 100883 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36850 | /* 100887 */ // (saddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 36851 | /* 100887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv16i8), |
| 36852 | /* 100890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36853 | /* 100892 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36854 | /* 100894 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36855 | /* 100896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36856 | /* 100899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36857 | /* 100905 */ GIR_RootConstrainSelectedInstOperands, |
| 36858 | /* 100906 */ // GIR_Coverage, 941, |
| 36859 | /* 100906 */ GIR_EraseRootFromParent_Done, |
| 36860 | /* 100907 */ // Label 3123: @100907 |
| 36861 | /* 100907 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3124*/ GIMT_Encode4(100967), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3906 // |
| 36862 | /* 100914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36863 | /* 100918 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36864 | /* 100922 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36865 | /* 100926 */ // (saddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 36866 | /* 100926 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36867 | /* 100929 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36868 | /* 100933 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36869 | /* 100938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs8), |
| 36870 | /* 100941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36871 | /* 100943 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36872 | /* 100945 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36873 | /* 100947 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36874 | /* 100950 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36875 | /* 100956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36876 | /* 100962 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36877 | /* 100965 */ GIR_RootConstrainSelectedInstOperands, |
| 36878 | /* 100966 */ // GIR_Coverage, 3906, |
| 36879 | /* 100966 */ GIR_EraseRootFromParent_Done, |
| 36880 | /* 100967 */ // Label 3124: @100967 |
| 36881 | /* 100967 */ GIM_Reject, |
| 36882 | /* 100968 */ // Label 3122: @100968 |
| 36883 | /* 100968 */ GIM_Reject, |
| 36884 | /* 100969 */ // Label 3107: @100969 |
| 36885 | /* 100969 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3125*/ GIMT_Encode4(101014), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 936 // |
| 36886 | /* 100976 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 36887 | /* 100979 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36888 | /* 100982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36889 | /* 100986 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36890 | /* 100990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36891 | /* 100994 */ // (saddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 36892 | /* 100994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i16), |
| 36893 | /* 100997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36894 | /* 100999 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36895 | /* 101001 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36896 | /* 101003 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36897 | /* 101006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36898 | /* 101012 */ GIR_RootConstrainSelectedInstOperands, |
| 36899 | /* 101013 */ // GIR_Coverage, 936, |
| 36900 | /* 101013 */ GIR_EraseRootFromParent_Done, |
| 36901 | /* 101014 */ // Label 3125: @101014 |
| 36902 | /* 101014 */ GIM_Reject, |
| 36903 | /* 101015 */ // Label 3108: @101015 |
| 36904 | /* 101015 */ GIM_Try, /*On fail goto*//*Label 3126*/ GIMT_Encode4(101126), |
| 36905 | /* 101020 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 36906 | /* 101023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 36907 | /* 101026 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3127*/ GIMT_Encode4(101065), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 938 // |
| 36908 | /* 101033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36909 | /* 101037 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36910 | /* 101041 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36911 | /* 101045 */ // (saddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 36912 | /* 101045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i16), |
| 36913 | /* 101048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36914 | /* 101050 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36915 | /* 101052 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36916 | /* 101054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36917 | /* 101057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36918 | /* 101063 */ GIR_RootConstrainSelectedInstOperands, |
| 36919 | /* 101064 */ // GIR_Coverage, 938, |
| 36920 | /* 101064 */ GIR_EraseRootFromParent_Done, |
| 36921 | /* 101065 */ // Label 3127: @101065 |
| 36922 | /* 101065 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3128*/ GIMT_Encode4(101125), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3909 // |
| 36923 | /* 101072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36924 | /* 101076 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36925 | /* 101080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 36926 | /* 101084 */ // (saddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 36927 | /* 101084 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 36928 | /* 101087 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 36929 | /* 101091 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 36930 | /* 101096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs16), |
| 36931 | /* 101099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 36932 | /* 101101 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 36933 | /* 101103 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 36934 | /* 101105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36935 | /* 101108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36936 | /* 101114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36937 | /* 101120 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 36938 | /* 101123 */ GIR_RootConstrainSelectedInstOperands, |
| 36939 | /* 101124 */ // GIR_Coverage, 3909, |
| 36940 | /* 101124 */ GIR_EraseRootFromParent_Done, |
| 36941 | /* 101125 */ // Label 3128: @101125 |
| 36942 | /* 101125 */ GIM_Reject, |
| 36943 | /* 101126 */ // Label 3126: @101126 |
| 36944 | /* 101126 */ GIM_Reject, |
| 36945 | /* 101127 */ // Label 3109: @101127 |
| 36946 | /* 101127 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3129*/ GIMT_Encode4(101172), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 937 // |
| 36947 | /* 101134 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 36948 | /* 101137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 36949 | /* 101140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36950 | /* 101144 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36951 | /* 101148 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36952 | /* 101152 */ // (saddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 36953 | /* 101152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i32), |
| 36954 | /* 101155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36955 | /* 101157 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 36956 | /* 101159 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 36957 | /* 101161 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36958 | /* 101164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36959 | /* 101170 */ GIR_RootConstrainSelectedInstOperands, |
| 36960 | /* 101171 */ // GIR_Coverage, 937, |
| 36961 | /* 101171 */ GIR_EraseRootFromParent_Done, |
| 36962 | /* 101172 */ // Label 3129: @101172 |
| 36963 | /* 101172 */ GIM_Reject, |
| 36964 | /* 101173 */ // Label 3110: @101173 |
| 36965 | /* 101173 */ GIM_Try, /*On fail goto*//*Label 3130*/ GIMT_Encode4(101438), |
| 36966 | /* 101178 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 36967 | /* 101181 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 36968 | /* 101184 */ GIM_Try, /*On fail goto*//*Label 3131*/ GIMT_Encode4(101377), |
| 36969 | /* 101189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36970 | /* 101193 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3132*/ GIMT_Encode4(101266), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6365 // |
| 36971 | /* 101200 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 36972 | /* 101204 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 36973 | /* 101208 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 36974 | /* 101211 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 36975 | /* 101216 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 36976 | /* 101220 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 36977 | /* 101224 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36978 | /* 101229 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 36979 | /* 101234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36980 | /* 101238 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 36981 | /* 101240 */ // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 4097:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 36982 | /* 101240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32), |
| 36983 | /* 101243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 36984 | /* 101245 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 36985 | /* 101247 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 36986 | /* 101251 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 36987 | /* 101255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 36988 | /* 101258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 36989 | /* 101264 */ GIR_RootConstrainSelectedInstOperands, |
| 36990 | /* 101265 */ // GIR_Coverage, 6365, |
| 36991 | /* 101265 */ GIR_EraseRootFromParent_Done, |
| 36992 | /* 101266 */ // Label 3132: @101266 |
| 36993 | /* 101266 */ GIM_Try, /*On fail goto*//*Label 3133*/ GIMT_Encode4(101376), |
| 36994 | /* 101271 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 36995 | /* 101275 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3134*/ GIMT_Encode4(101344), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2869 // |
| 36996 | /* 101282 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 36997 | /* 101286 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 36998 | /* 101290 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 36999 | /* 101293 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37000 | /* 101298 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37001 | /* 101302 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 37002 | /* 101306 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37003 | /* 101311 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37004 | /* 101316 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37005 | /* 101318 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 4097:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37006 | /* 101318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32), |
| 37007 | /* 101321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37008 | /* 101323 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37009 | /* 101325 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37010 | /* 101329 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37011 | /* 101333 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37012 | /* 101336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37013 | /* 101342 */ GIR_RootConstrainSelectedInstOperands, |
| 37014 | /* 101343 */ // GIR_Coverage, 2869, |
| 37015 | /* 101343 */ GIR_EraseRootFromParent_Done, |
| 37016 | /* 101344 */ // Label 3134: @101344 |
| 37017 | /* 101344 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3135*/ GIMT_Encode4(101375), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 939 // |
| 37018 | /* 101351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37019 | /* 101355 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 37020 | /* 101355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i32), |
| 37021 | /* 101358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37022 | /* 101360 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37023 | /* 101362 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37024 | /* 101364 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37025 | /* 101367 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37026 | /* 101373 */ GIR_RootConstrainSelectedInstOperands, |
| 37027 | /* 101374 */ // GIR_Coverage, 939, |
| 37028 | /* 101374 */ GIR_EraseRootFromParent_Done, |
| 37029 | /* 101375 */ // Label 3135: @101375 |
| 37030 | /* 101375 */ GIM_Reject, |
| 37031 | /* 101376 */ // Label 3133: @101376 |
| 37032 | /* 101376 */ GIM_Reject, |
| 37033 | /* 101377 */ // Label 3131: @101377 |
| 37034 | /* 101377 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3136*/ GIMT_Encode4(101437), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3912 // |
| 37035 | /* 101384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37036 | /* 101388 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37037 | /* 101392 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37038 | /* 101396 */ // (saddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 37039 | /* 101396 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37040 | /* 101399 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37041 | /* 101403 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37042 | /* 101408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs32), |
| 37043 | /* 101411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37044 | /* 101413 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37045 | /* 101415 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37046 | /* 101417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37047 | /* 101420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37048 | /* 101426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37049 | /* 101432 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37050 | /* 101435 */ GIR_RootConstrainSelectedInstOperands, |
| 37051 | /* 101436 */ // GIR_Coverage, 3912, |
| 37052 | /* 101436 */ GIR_EraseRootFromParent_Done, |
| 37053 | /* 101437 */ // Label 3136: @101437 |
| 37054 | /* 101437 */ GIM_Reject, |
| 37055 | /* 101438 */ // Label 3130: @101438 |
| 37056 | /* 101438 */ GIM_Reject, |
| 37057 | /* 101439 */ // Label 3111: @101439 |
| 37058 | /* 101439 */ GIM_Try, /*On fail goto*//*Label 3137*/ GIMT_Encode4(101638), |
| 37059 | /* 101444 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 37060 | /* 101447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 37061 | /* 101450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37062 | /* 101454 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3138*/ GIMT_Encode4(101527), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6366 // |
| 37063 | /* 101461 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 37064 | /* 101465 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37065 | /* 101469 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37066 | /* 101472 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37067 | /* 101477 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37068 | /* 101481 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 37069 | /* 101485 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37070 | /* 101490 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37071 | /* 101495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37072 | /* 101499 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37073 | /* 101501 */ // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 4097:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$src1) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37074 | /* 101501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64), |
| 37075 | /* 101504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37076 | /* 101506 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 37077 | /* 101508 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37078 | /* 101512 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37079 | /* 101516 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37080 | /* 101519 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37081 | /* 101525 */ GIR_RootConstrainSelectedInstOperands, |
| 37082 | /* 101526 */ // GIR_Coverage, 6366, |
| 37083 | /* 101526 */ GIR_EraseRootFromParent_Done, |
| 37084 | /* 101527 */ // Label 3138: @101527 |
| 37085 | /* 101527 */ GIM_Try, /*On fail goto*//*Label 3139*/ GIMT_Encode4(101637), |
| 37086 | /* 101532 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37087 | /* 101536 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3140*/ GIMT_Encode4(101605), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2870 // |
| 37088 | /* 101543 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37089 | /* 101547 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37090 | /* 101551 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37091 | /* 101554 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37092 | /* 101559 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37093 | /* 101563 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 37094 | /* 101567 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37095 | /* 101572 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37096 | /* 101577 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37097 | /* 101579 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 4097:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37098 | /* 101579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64), |
| 37099 | /* 101582 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37100 | /* 101584 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37101 | /* 101586 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37102 | /* 101590 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37103 | /* 101594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37104 | /* 101597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37105 | /* 101603 */ GIR_RootConstrainSelectedInstOperands, |
| 37106 | /* 101604 */ // GIR_Coverage, 2870, |
| 37107 | /* 101604 */ GIR_EraseRootFromParent_Done, |
| 37108 | /* 101605 */ // Label 3140: @101605 |
| 37109 | /* 101605 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3141*/ GIMT_Encode4(101636), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 943 // |
| 37110 | /* 101612 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37111 | /* 101616 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 37112 | /* 101616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i64), |
| 37113 | /* 101619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37114 | /* 101621 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37115 | /* 101623 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37116 | /* 101625 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37117 | /* 101628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37118 | /* 101634 */ GIR_RootConstrainSelectedInstOperands, |
| 37119 | /* 101635 */ // GIR_Coverage, 943, |
| 37120 | /* 101635 */ GIR_EraseRootFromParent_Done, |
| 37121 | /* 101636 */ // Label 3141: @101636 |
| 37122 | /* 101636 */ GIM_Reject, |
| 37123 | /* 101637 */ // Label 3139: @101637 |
| 37124 | /* 101637 */ GIM_Reject, |
| 37125 | /* 101638 */ // Label 3137: @101638 |
| 37126 | /* 101638 */ GIM_Reject, |
| 37127 | /* 101639 */ // Label 3112: @101639 |
| 37128 | /* 101639 */ GIM_Reject, |
| 37129 | /* 101640 */ // Label 38: @101640 |
| 37130 | /* 101640 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 3150*/ GIMT_Encode4(102265), |
| 37131 | /* 101651 */ /*GILLT_s64*//*Label 3142*/ GIMT_Encode4(101699), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 37132 | /* 101671 */ /*GILLT_v8s8*//*Label 3143*/ GIMT_Encode4(101745), |
| 37133 | /* 101675 */ /*GILLT_v16s8*//*Label 3144*/ GIMT_Encode4(101791), |
| 37134 | /* 101679 */ /*GILLT_v4s16*//*Label 3145*/ GIMT_Encode4(101903), |
| 37135 | /* 101683 */ /*GILLT_v8s16*//*Label 3146*/ GIMT_Encode4(101949), |
| 37136 | /* 101687 */ /*GILLT_v2s32*//*Label 3147*/ GIMT_Encode4(102061), |
| 37137 | /* 101691 */ /*GILLT_v4s32*//*Label 3148*/ GIMT_Encode4(102107), |
| 37138 | /* 101695 */ /*GILLT_v2s64*//*Label 3149*/ GIMT_Encode4(102219), |
| 37139 | /* 101699 */ // Label 3142: @101699 |
| 37140 | /* 101699 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3151*/ GIMT_Encode4(101744), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1184 // |
| 37141 | /* 101706 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 37142 | /* 101709 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 37143 | /* 101712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37144 | /* 101716 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37145 | /* 101720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37146 | /* 101724 */ // (usubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 37147 | /* 101724 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv1i64), |
| 37148 | /* 101727 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37149 | /* 101729 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37150 | /* 101731 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37151 | /* 101733 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37152 | /* 101736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37153 | /* 101742 */ GIR_RootConstrainSelectedInstOperands, |
| 37154 | /* 101743 */ // GIR_Coverage, 1184, |
| 37155 | /* 101743 */ GIR_EraseRootFromParent_Done, |
| 37156 | /* 101744 */ // Label 3151: @101744 |
| 37157 | /* 101744 */ GIM_Reject, |
| 37158 | /* 101745 */ // Label 3143: @101745 |
| 37159 | /* 101745 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3152*/ GIMT_Encode4(101790), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1182 // |
| 37160 | /* 101752 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 37161 | /* 101755 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 37162 | /* 101758 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37163 | /* 101762 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37164 | /* 101766 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37165 | /* 101770 */ // (usubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 37166 | /* 101770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i8), |
| 37167 | /* 101773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37168 | /* 101775 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37169 | /* 101777 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37170 | /* 101779 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37171 | /* 101782 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37172 | /* 101788 */ GIR_RootConstrainSelectedInstOperands, |
| 37173 | /* 101789 */ // GIR_Coverage, 1182, |
| 37174 | /* 101789 */ GIR_EraseRootFromParent_Done, |
| 37175 | /* 101790 */ // Label 3152: @101790 |
| 37176 | /* 101790 */ GIM_Reject, |
| 37177 | /* 101791 */ // Label 3144: @101791 |
| 37178 | /* 101791 */ GIM_Try, /*On fail goto*//*Label 3153*/ GIMT_Encode4(101902), |
| 37179 | /* 101796 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 37180 | /* 101799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 37181 | /* 101802 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3154*/ GIMT_Encode4(101841), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1183 // |
| 37182 | /* 101809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37183 | /* 101813 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37184 | /* 101817 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37185 | /* 101821 */ // (usubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 37186 | /* 101821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv16i8), |
| 37187 | /* 101824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37188 | /* 101826 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37189 | /* 101828 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37190 | /* 101830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37191 | /* 101833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37192 | /* 101839 */ GIR_RootConstrainSelectedInstOperands, |
| 37193 | /* 101840 */ // GIR_Coverage, 1183, |
| 37194 | /* 101840 */ GIR_EraseRootFromParent_Done, |
| 37195 | /* 101841 */ // Label 3154: @101841 |
| 37196 | /* 101841 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3155*/ GIMT_Encode4(101901), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3933 // |
| 37197 | /* 101848 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37198 | /* 101852 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37199 | /* 101856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37200 | /* 101860 */ // (usubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 37201 | /* 101860 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37202 | /* 101863 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37203 | /* 101867 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37204 | /* 101872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu8), |
| 37205 | /* 101875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37206 | /* 101877 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37207 | /* 101879 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37208 | /* 101881 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37209 | /* 101884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37210 | /* 101890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37211 | /* 101896 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37212 | /* 101899 */ GIR_RootConstrainSelectedInstOperands, |
| 37213 | /* 101900 */ // GIR_Coverage, 3933, |
| 37214 | /* 101900 */ GIR_EraseRootFromParent_Done, |
| 37215 | /* 101901 */ // Label 3155: @101901 |
| 37216 | /* 101901 */ GIM_Reject, |
| 37217 | /* 101902 */ // Label 3153: @101902 |
| 37218 | /* 101902 */ GIM_Reject, |
| 37219 | /* 101903 */ // Label 3145: @101903 |
| 37220 | /* 101903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3156*/ GIMT_Encode4(101948), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1178 // |
| 37221 | /* 101910 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 37222 | /* 101913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37223 | /* 101916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37224 | /* 101920 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37225 | /* 101924 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37226 | /* 101928 */ // (usubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37227 | /* 101928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i16), |
| 37228 | /* 101931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37229 | /* 101933 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37230 | /* 101935 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37231 | /* 101937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37232 | /* 101940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37233 | /* 101946 */ GIR_RootConstrainSelectedInstOperands, |
| 37234 | /* 101947 */ // GIR_Coverage, 1178, |
| 37235 | /* 101947 */ GIR_EraseRootFromParent_Done, |
| 37236 | /* 101948 */ // Label 3156: @101948 |
| 37237 | /* 101948 */ GIM_Reject, |
| 37238 | /* 101949 */ // Label 3146: @101949 |
| 37239 | /* 101949 */ GIM_Try, /*On fail goto*//*Label 3157*/ GIMT_Encode4(102060), |
| 37240 | /* 101954 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 37241 | /* 101957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 37242 | /* 101960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3158*/ GIMT_Encode4(101999), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1180 // |
| 37243 | /* 101967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37244 | /* 101971 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37245 | /* 101975 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37246 | /* 101979 */ // (usubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 37247 | /* 101979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i16), |
| 37248 | /* 101982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37249 | /* 101984 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37250 | /* 101986 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37251 | /* 101988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37252 | /* 101991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37253 | /* 101997 */ GIR_RootConstrainSelectedInstOperands, |
| 37254 | /* 101998 */ // GIR_Coverage, 1180, |
| 37255 | /* 101998 */ GIR_EraseRootFromParent_Done, |
| 37256 | /* 101999 */ // Label 3158: @101999 |
| 37257 | /* 101999 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3159*/ GIMT_Encode4(102059), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3936 // |
| 37258 | /* 102006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37259 | /* 102010 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37260 | /* 102014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37261 | /* 102018 */ // (usubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 37262 | /* 102018 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37263 | /* 102021 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37264 | /* 102025 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37265 | /* 102030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu16), |
| 37266 | /* 102033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37267 | /* 102035 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37268 | /* 102037 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37269 | /* 102039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37270 | /* 102042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37271 | /* 102048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37272 | /* 102054 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37273 | /* 102057 */ GIR_RootConstrainSelectedInstOperands, |
| 37274 | /* 102058 */ // GIR_Coverage, 3936, |
| 37275 | /* 102058 */ GIR_EraseRootFromParent_Done, |
| 37276 | /* 102059 */ // Label 3159: @102059 |
| 37277 | /* 102059 */ GIM_Reject, |
| 37278 | /* 102060 */ // Label 3157: @102060 |
| 37279 | /* 102060 */ GIM_Reject, |
| 37280 | /* 102061 */ // Label 3147: @102061 |
| 37281 | /* 102061 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3160*/ GIMT_Encode4(102106), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1179 // |
| 37282 | /* 102068 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 37283 | /* 102071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37284 | /* 102074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37285 | /* 102078 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37286 | /* 102082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37287 | /* 102086 */ // (usubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37288 | /* 102086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i32), |
| 37289 | /* 102089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37290 | /* 102091 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37291 | /* 102093 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37292 | /* 102095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37293 | /* 102098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37294 | /* 102104 */ GIR_RootConstrainSelectedInstOperands, |
| 37295 | /* 102105 */ // GIR_Coverage, 1179, |
| 37296 | /* 102105 */ GIR_EraseRootFromParent_Done, |
| 37297 | /* 102106 */ // Label 3160: @102106 |
| 37298 | /* 102106 */ GIM_Reject, |
| 37299 | /* 102107 */ // Label 3148: @102107 |
| 37300 | /* 102107 */ GIM_Try, /*On fail goto*//*Label 3161*/ GIMT_Encode4(102218), |
| 37301 | /* 102112 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 37302 | /* 102115 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 37303 | /* 102118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3162*/ GIMT_Encode4(102157), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1181 // |
| 37304 | /* 102125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37305 | /* 102129 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37306 | /* 102133 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37307 | /* 102137 */ // (usubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 37308 | /* 102137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i32), |
| 37309 | /* 102140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37310 | /* 102142 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37311 | /* 102144 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37312 | /* 102146 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37313 | /* 102149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37314 | /* 102155 */ GIR_RootConstrainSelectedInstOperands, |
| 37315 | /* 102156 */ // GIR_Coverage, 1181, |
| 37316 | /* 102156 */ GIR_EraseRootFromParent_Done, |
| 37317 | /* 102157 */ // Label 3162: @102157 |
| 37318 | /* 102157 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3163*/ GIMT_Encode4(102217), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3939 // |
| 37319 | /* 102164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37320 | /* 102168 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37321 | /* 102172 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37322 | /* 102176 */ // (usubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 37323 | /* 102176 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37324 | /* 102179 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37325 | /* 102183 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37326 | /* 102188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu32), |
| 37327 | /* 102191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37328 | /* 102193 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37329 | /* 102195 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37330 | /* 102197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37331 | /* 102200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37332 | /* 102206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37333 | /* 102212 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37334 | /* 102215 */ GIR_RootConstrainSelectedInstOperands, |
| 37335 | /* 102216 */ // GIR_Coverage, 3939, |
| 37336 | /* 102216 */ GIR_EraseRootFromParent_Done, |
| 37337 | /* 102217 */ // Label 3163: @102217 |
| 37338 | /* 102217 */ GIM_Reject, |
| 37339 | /* 102218 */ // Label 3161: @102218 |
| 37340 | /* 102218 */ GIM_Reject, |
| 37341 | /* 102219 */ // Label 3149: @102219 |
| 37342 | /* 102219 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3164*/ GIMT_Encode4(102264), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1185 // |
| 37343 | /* 102226 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 37344 | /* 102229 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 37345 | /* 102232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37346 | /* 102236 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37347 | /* 102240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37348 | /* 102244 */ // (usubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 37349 | /* 102244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i64), |
| 37350 | /* 102247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37351 | /* 102249 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37352 | /* 102251 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37353 | /* 102253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37354 | /* 102256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37355 | /* 102262 */ GIR_RootConstrainSelectedInstOperands, |
| 37356 | /* 102263 */ // GIR_Coverage, 1185, |
| 37357 | /* 102263 */ GIR_EraseRootFromParent_Done, |
| 37358 | /* 102264 */ // Label 3164: @102264 |
| 37359 | /* 102264 */ GIM_Reject, |
| 37360 | /* 102265 */ // Label 3150: @102265 |
| 37361 | /* 102265 */ GIM_Reject, |
| 37362 | /* 102266 */ // Label 39: @102266 |
| 37363 | /* 102266 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 3174*/ GIMT_Encode4(103258), |
| 37364 | /* 102277 */ /*GILLT_s32*//*Label 3165*/ GIMT_Encode4(102329), |
| 37365 | /* 102281 */ /*GILLT_s64*//*Label 3166*/ GIMT_Encode4(102542), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 37366 | /* 102301 */ /*GILLT_v8s8*//*Label 3167*/ GIMT_Encode4(102588), |
| 37367 | /* 102305 */ /*GILLT_v16s8*//*Label 3168*/ GIMT_Encode4(102634), |
| 37368 | /* 102309 */ /*GILLT_v4s16*//*Label 3169*/ GIMT_Encode4(102746), |
| 37369 | /* 102313 */ /*GILLT_v8s16*//*Label 3170*/ GIMT_Encode4(102792), |
| 37370 | /* 102317 */ /*GILLT_v2s32*//*Label 3171*/ GIMT_Encode4(102904), |
| 37371 | /* 102321 */ /*GILLT_v4s32*//*Label 3172*/ GIMT_Encode4(102950), |
| 37372 | /* 102325 */ /*GILLT_v2s64*//*Label 3173*/ GIMT_Encode4(103137), |
| 37373 | /* 102329 */ // Label 3165: @102329 |
| 37374 | /* 102329 */ GIM_Try, /*On fail goto*//*Label 3175*/ GIMT_Encode4(102541), |
| 37375 | /* 102334 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 37376 | /* 102337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 37377 | /* 102340 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3176*/ GIMT_Encode4(102401), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2059 // |
| 37378 | /* 102347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 37379 | /* 102351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37380 | /* 102355 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37381 | /* 102359 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 37382 | /* 102363 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37383 | /* 102367 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37384 | /* 102372 */ // MIs[1] Rn |
| 37385 | /* 102372 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 37386 | /* 102377 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37387 | /* 102379 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 37388 | /* 102379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB), |
| 37389 | /* 102382 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37390 | /* 102384 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 37391 | /* 102386 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 37392 | /* 102390 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37393 | /* 102393 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37394 | /* 102399 */ GIR_RootConstrainSelectedInstOperands, |
| 37395 | /* 102400 */ // GIR_Coverage, 2059, |
| 37396 | /* 102400 */ GIR_EraseRootFromParent_Done, |
| 37397 | /* 102401 */ // Label 3176: @102401 |
| 37398 | /* 102401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3177*/ GIMT_Encode4(102462), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2331 // |
| 37399 | /* 102408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37400 | /* 102412 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37401 | /* 102416 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37402 | /* 102420 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT), |
| 37403 | /* 102424 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37404 | /* 102428 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37405 | /* 102433 */ // MIs[1] Rn |
| 37406 | /* 102433 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 37407 | /* 102438 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37408 | /* 102440 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 37409 | /* 102440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB), |
| 37410 | /* 102443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37411 | /* 102445 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 37412 | /* 102447 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn |
| 37413 | /* 102451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37414 | /* 102454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37415 | /* 102460 */ GIR_RootConstrainSelectedInstOperands, |
| 37416 | /* 102461 */ // GIR_Coverage, 2331, |
| 37417 | /* 102461 */ GIR_EraseRootFromParent_Done, |
| 37418 | /* 102462 */ // Label 3177: @102462 |
| 37419 | /* 102462 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3178*/ GIMT_Encode4(102501), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2057 // |
| 37420 | /* 102469 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 37421 | /* 102473 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37422 | /* 102477 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 37423 | /* 102481 */ // (ssubsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QSUB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) |
| 37424 | /* 102481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB), |
| 37425 | /* 102484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37426 | /* 102486 */ GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 37427 | /* 102488 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 37428 | /* 102490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37429 | /* 102493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37430 | /* 102499 */ GIR_RootConstrainSelectedInstOperands, |
| 37431 | /* 102500 */ // GIR_Coverage, 2057, |
| 37432 | /* 102500 */ GIR_EraseRootFromParent_Done, |
| 37433 | /* 102501 */ // Label 3178: @102501 |
| 37434 | /* 102501 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3179*/ GIMT_Encode4(102540), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2329 // |
| 37435 | /* 102508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37436 | /* 102512 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37437 | /* 102516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 37438 | /* 102520 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) |
| 37439 | /* 102520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB), |
| 37440 | /* 102523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 37441 | /* 102525 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 37442 | /* 102527 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn |
| 37443 | /* 102529 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37444 | /* 102532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37445 | /* 102538 */ GIR_RootConstrainSelectedInstOperands, |
| 37446 | /* 102539 */ // GIR_Coverage, 2329, |
| 37447 | /* 102539 */ GIR_EraseRootFromParent_Done, |
| 37448 | /* 102540 */ // Label 3179: @102540 |
| 37449 | /* 102540 */ GIM_Reject, |
| 37450 | /* 102541 */ // Label 3175: @102541 |
| 37451 | /* 102541 */ GIM_Reject, |
| 37452 | /* 102542 */ // Label 3166: @102542 |
| 37453 | /* 102542 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3180*/ GIMT_Encode4(102587), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1176 // |
| 37454 | /* 102549 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 37455 | /* 102552 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 37456 | /* 102555 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37457 | /* 102559 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37458 | /* 102563 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37459 | /* 102567 */ // (ssubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) |
| 37460 | /* 102567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv1i64), |
| 37461 | /* 102570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37462 | /* 102572 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37463 | /* 102574 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37464 | /* 102576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37465 | /* 102579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37466 | /* 102585 */ GIR_RootConstrainSelectedInstOperands, |
| 37467 | /* 102586 */ // GIR_Coverage, 1176, |
| 37468 | /* 102586 */ GIR_EraseRootFromParent_Done, |
| 37469 | /* 102587 */ // Label 3180: @102587 |
| 37470 | /* 102587 */ GIM_Reject, |
| 37471 | /* 102588 */ // Label 3167: @102588 |
| 37472 | /* 102588 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3181*/ GIMT_Encode4(102633), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1174 // |
| 37473 | /* 102595 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 37474 | /* 102598 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 37475 | /* 102601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37476 | /* 102605 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37477 | /* 102609 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37478 | /* 102613 */ // (ssubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 37479 | /* 102613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i8), |
| 37480 | /* 102616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37481 | /* 102618 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37482 | /* 102620 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37483 | /* 102622 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37484 | /* 102625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37485 | /* 102631 */ GIR_RootConstrainSelectedInstOperands, |
| 37486 | /* 102632 */ // GIR_Coverage, 1174, |
| 37487 | /* 102632 */ GIR_EraseRootFromParent_Done, |
| 37488 | /* 102633 */ // Label 3181: @102633 |
| 37489 | /* 102633 */ GIM_Reject, |
| 37490 | /* 102634 */ // Label 3168: @102634 |
| 37491 | /* 102634 */ GIM_Try, /*On fail goto*//*Label 3182*/ GIMT_Encode4(102745), |
| 37492 | /* 102639 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 37493 | /* 102642 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 37494 | /* 102645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3183*/ GIMT_Encode4(102684), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1175 // |
| 37495 | /* 102652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37496 | /* 102656 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37497 | /* 102660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37498 | /* 102664 */ // (ssubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 37499 | /* 102664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv16i8), |
| 37500 | /* 102667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37501 | /* 102669 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37502 | /* 102671 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37503 | /* 102673 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37504 | /* 102676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37505 | /* 102682 */ GIR_RootConstrainSelectedInstOperands, |
| 37506 | /* 102683 */ // GIR_Coverage, 1175, |
| 37507 | /* 102683 */ GIR_EraseRootFromParent_Done, |
| 37508 | /* 102684 */ // Label 3183: @102684 |
| 37509 | /* 102684 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3184*/ GIMT_Encode4(102744), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3924 // |
| 37510 | /* 102691 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37511 | /* 102695 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37512 | /* 102699 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37513 | /* 102703 */ // (ssubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 37514 | /* 102703 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37515 | /* 102706 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37516 | /* 102710 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37517 | /* 102715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs8), |
| 37518 | /* 102718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37519 | /* 102720 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37520 | /* 102722 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37521 | /* 102724 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37522 | /* 102727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37523 | /* 102733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37524 | /* 102739 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37525 | /* 102742 */ GIR_RootConstrainSelectedInstOperands, |
| 37526 | /* 102743 */ // GIR_Coverage, 3924, |
| 37527 | /* 102743 */ GIR_EraseRootFromParent_Done, |
| 37528 | /* 102744 */ // Label 3184: @102744 |
| 37529 | /* 102744 */ GIM_Reject, |
| 37530 | /* 102745 */ // Label 3182: @102745 |
| 37531 | /* 102745 */ GIM_Reject, |
| 37532 | /* 102746 */ // Label 3169: @102746 |
| 37533 | /* 102746 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3185*/ GIMT_Encode4(102791), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1170 // |
| 37534 | /* 102753 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 37535 | /* 102756 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37536 | /* 102759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37537 | /* 102763 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37538 | /* 102767 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37539 | /* 102771 */ // (ssubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37540 | /* 102771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i16), |
| 37541 | /* 102774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37542 | /* 102776 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37543 | /* 102778 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37544 | /* 102780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37545 | /* 102783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37546 | /* 102789 */ GIR_RootConstrainSelectedInstOperands, |
| 37547 | /* 102790 */ // GIR_Coverage, 1170, |
| 37548 | /* 102790 */ GIR_EraseRootFromParent_Done, |
| 37549 | /* 102791 */ // Label 3185: @102791 |
| 37550 | /* 102791 */ GIM_Reject, |
| 37551 | /* 102792 */ // Label 3170: @102792 |
| 37552 | /* 102792 */ GIM_Try, /*On fail goto*//*Label 3186*/ GIMT_Encode4(102903), |
| 37553 | /* 102797 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 37554 | /* 102800 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 37555 | /* 102803 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3187*/ GIMT_Encode4(102842), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1172 // |
| 37556 | /* 102810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37557 | /* 102814 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37558 | /* 102818 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37559 | /* 102822 */ // (ssubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 37560 | /* 102822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i16), |
| 37561 | /* 102825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37562 | /* 102827 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37563 | /* 102829 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37564 | /* 102831 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37565 | /* 102834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37566 | /* 102840 */ GIR_RootConstrainSelectedInstOperands, |
| 37567 | /* 102841 */ // GIR_Coverage, 1172, |
| 37568 | /* 102841 */ GIR_EraseRootFromParent_Done, |
| 37569 | /* 102842 */ // Label 3187: @102842 |
| 37570 | /* 102842 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3188*/ GIMT_Encode4(102902), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3927 // |
| 37571 | /* 102849 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37572 | /* 102853 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37573 | /* 102857 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37574 | /* 102861 */ // (ssubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 37575 | /* 102861 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37576 | /* 102864 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37577 | /* 102868 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37578 | /* 102873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs16), |
| 37579 | /* 102876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37580 | /* 102878 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37581 | /* 102880 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37582 | /* 102882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37583 | /* 102885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37584 | /* 102891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37585 | /* 102897 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37586 | /* 102900 */ GIR_RootConstrainSelectedInstOperands, |
| 37587 | /* 102901 */ // GIR_Coverage, 3927, |
| 37588 | /* 102901 */ GIR_EraseRootFromParent_Done, |
| 37589 | /* 102902 */ // Label 3188: @102902 |
| 37590 | /* 102902 */ GIM_Reject, |
| 37591 | /* 102903 */ // Label 3186: @102903 |
| 37592 | /* 102903 */ GIM_Reject, |
| 37593 | /* 102904 */ // Label 3171: @102904 |
| 37594 | /* 102904 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3189*/ GIMT_Encode4(102949), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1171 // |
| 37595 | /* 102911 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 37596 | /* 102914 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37597 | /* 102917 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37598 | /* 102921 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37599 | /* 102925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37600 | /* 102929 */ // (ssubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37601 | /* 102929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i32), |
| 37602 | /* 102932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37603 | /* 102934 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37604 | /* 102936 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37605 | /* 102938 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37606 | /* 102941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37607 | /* 102947 */ GIR_RootConstrainSelectedInstOperands, |
| 37608 | /* 102948 */ // GIR_Coverage, 1171, |
| 37609 | /* 102948 */ GIR_EraseRootFromParent_Done, |
| 37610 | /* 102949 */ // Label 3189: @102949 |
| 37611 | /* 102949 */ GIM_Reject, |
| 37612 | /* 102950 */ // Label 3172: @102950 |
| 37613 | /* 102950 */ GIM_Try, /*On fail goto*//*Label 3190*/ GIMT_Encode4(103136), |
| 37614 | /* 102955 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 37615 | /* 102958 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 37616 | /* 102961 */ GIM_Try, /*On fail goto*//*Label 3191*/ GIMT_Encode4(103075), |
| 37617 | /* 102966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37618 | /* 102970 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37619 | /* 102974 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3192*/ GIMT_Encode4(103043), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2879 // |
| 37620 | /* 102981 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37621 | /* 102985 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37622 | /* 102989 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37623 | /* 102992 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37624 | /* 102997 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 37625 | /* 103001 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16, |
| 37626 | /* 103005 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37627 | /* 103010 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37628 | /* 103015 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37629 | /* 103017 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 4097:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLSLv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 37630 | /* 103017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv4i32), |
| 37631 | /* 103020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37632 | /* 103022 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37633 | /* 103024 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37634 | /* 103028 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37635 | /* 103032 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37636 | /* 103035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37637 | /* 103041 */ GIR_RootConstrainSelectedInstOperands, |
| 37638 | /* 103042 */ // GIR_Coverage, 2879, |
| 37639 | /* 103042 */ GIR_EraseRootFromParent_Done, |
| 37640 | /* 103043 */ // Label 3192: @103043 |
| 37641 | /* 103043 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3193*/ GIMT_Encode4(103074), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1173 // |
| 37642 | /* 103050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37643 | /* 103054 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 37644 | /* 103054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i32), |
| 37645 | /* 103057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37646 | /* 103059 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37647 | /* 103061 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37648 | /* 103063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37649 | /* 103066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37650 | /* 103072 */ GIR_RootConstrainSelectedInstOperands, |
| 37651 | /* 103073 */ // GIR_Coverage, 1173, |
| 37652 | /* 103073 */ GIR_EraseRootFromParent_Done, |
| 37653 | /* 103074 */ // Label 3193: @103074 |
| 37654 | /* 103074 */ GIM_Reject, |
| 37655 | /* 103075 */ // Label 3191: @103075 |
| 37656 | /* 103075 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3194*/ GIMT_Encode4(103135), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3930 // |
| 37657 | /* 103082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37658 | /* 103086 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37659 | /* 103090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 37660 | /* 103094 */ // (ssubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 37661 | /* 103094 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 37662 | /* 103097 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37663 | /* 103101 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37664 | /* 103106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs32), |
| 37665 | /* 103109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 37666 | /* 103111 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 37667 | /* 103113 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 37668 | /* 103115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37669 | /* 103118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37670 | /* 103124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37671 | /* 103130 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 37672 | /* 103133 */ GIR_RootConstrainSelectedInstOperands, |
| 37673 | /* 103134 */ // GIR_Coverage, 3930, |
| 37674 | /* 103134 */ GIR_EraseRootFromParent_Done, |
| 37675 | /* 103135 */ // Label 3194: @103135 |
| 37676 | /* 103135 */ GIM_Reject, |
| 37677 | /* 103136 */ // Label 3190: @103136 |
| 37678 | /* 103136 */ GIM_Reject, |
| 37679 | /* 103137 */ // Label 3173: @103137 |
| 37680 | /* 103137 */ GIM_Try, /*On fail goto*//*Label 3195*/ GIMT_Encode4(103257), |
| 37681 | /* 103142 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 37682 | /* 103145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 37683 | /* 103148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37684 | /* 103152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37685 | /* 103156 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3196*/ GIMT_Encode4(103225), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2880 // |
| 37686 | /* 103163 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37687 | /* 103167 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 37688 | /* 103171 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 37689 | /* 103174 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull), |
| 37690 | /* 103179 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 37691 | /* 103183 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32, |
| 37692 | /* 103187 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37693 | /* 103192 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 37694 | /* 103197 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37695 | /* 103199 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 4097:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLSLv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 37696 | /* 103199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv2i64), |
| 37697 | /* 103202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37698 | /* 103204 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 37699 | /* 103206 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn |
| 37700 | /* 103210 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm |
| 37701 | /* 103214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37702 | /* 103217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37703 | /* 103223 */ GIR_RootConstrainSelectedInstOperands, |
| 37704 | /* 103224 */ // GIR_Coverage, 2880, |
| 37705 | /* 103224 */ GIR_EraseRootFromParent_Done, |
| 37706 | /* 103225 */ // Label 3196: @103225 |
| 37707 | /* 103225 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3197*/ GIMT_Encode4(103256), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1177 // |
| 37708 | /* 103232 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 37709 | /* 103236 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) |
| 37710 | /* 103236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i64), |
| 37711 | /* 103239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 37712 | /* 103241 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 37713 | /* 103243 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 37714 | /* 103245 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37715 | /* 103248 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37716 | /* 103254 */ GIR_RootConstrainSelectedInstOperands, |
| 37717 | /* 103255 */ // GIR_Coverage, 1177, |
| 37718 | /* 103255 */ GIR_EraseRootFromParent_Done, |
| 37719 | /* 103256 */ // Label 3197: @103256 |
| 37720 | /* 103256 */ GIM_Reject, |
| 37721 | /* 103257 */ // Label 3195: @103257 |
| 37722 | /* 103257 */ GIM_Reject, |
| 37723 | /* 103258 */ // Label 3174: @103258 |
| 37724 | /* 103258 */ GIM_Reject, |
| 37725 | /* 103259 */ // Label 40: @103259 |
| 37726 | /* 103259 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3205*/ GIMT_Encode4(105593), |
| 37727 | /* 103270 */ /*GILLT_s16*//*Label 3198*/ GIMT_Encode4(103322), |
| 37728 | /* 103274 */ /*GILLT_s32*//*Label 3199*/ GIMT_Encode4(103368), |
| 37729 | /* 103278 */ /*GILLT_s64*//*Label 3200*/ GIMT_Encode4(104955), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 37730 | /* 103306 */ /*GILLT_v4s16*//*Label 3201*/ GIMT_Encode4(105001), |
| 37731 | /* 103310 */ /*GILLT_v8s16*//*Label 3202*/ GIMT_Encode4(105185), |
| 37732 | /* 103314 */ /*GILLT_v2s32*//*Label 3203*/ GIMT_Encode4(105435), |
| 37733 | /* 103318 */ /*GILLT_v4s32*//*Label 3204*/ GIMT_Encode4(105481), |
| 37734 | /* 103322 */ // Label 3198: @103322 |
| 37735 | /* 103322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3206*/ GIMT_Encode4(103367), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 621 // |
| 37736 | /* 103329 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 37737 | /* 103332 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 37738 | /* 103335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 37739 | /* 103339 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 37740 | /* 103343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 37741 | /* 103347 */ // (fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 37742 | /* 103347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH), |
| 37743 | /* 103350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 37744 | /* 103352 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 37745 | /* 103354 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 37746 | /* 103356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 37747 | /* 103359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37748 | /* 103365 */ GIR_RootConstrainSelectedInstOperands, |
| 37749 | /* 103366 */ // GIR_Coverage, 621, |
| 37750 | /* 103366 */ GIR_EraseRootFromParent_Done, |
| 37751 | /* 103367 */ // Label 3206: @103367 |
| 37752 | /* 103367 */ GIM_Reject, |
| 37753 | /* 103368 */ // Label 3199: @103368 |
| 37754 | /* 103368 */ GIM_Try, /*On fail goto*//*Label 3207*/ GIMT_Encode4(104954), |
| 37755 | /* 103373 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 37756 | /* 103376 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 37757 | /* 103379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37758 | /* 103383 */ GIM_Try, /*On fail goto*//*Label 3208*/ GIMT_Encode4(104039), |
| 37759 | /* 103388 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37760 | /* 103392 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3209*/ GIMT_Encode4(103715), GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), // Rule ID 6545 // |
| 37761 | /* 103399 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 37762 | /* 103403 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 37763 | /* 103407 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37764 | /* 103411 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 37765 | /* 103415 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37766 | /* 103420 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37767 | /* 103425 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37768 | /* 103427 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 37769 | /* 103427 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 37770 | /* 103430 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37771 | /* 103434 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37772 | /* 103439 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 37773 | /* 103441 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 37774 | /* 103444 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37775 | /* 103448 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37776 | /* 103453 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 37777 | /* 103456 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37778 | /* 103461 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 37779 | /* 103464 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37780 | /* 103468 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37781 | /* 103473 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 37782 | /* 103476 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 37783 | /* 103480 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 37784 | /* 103483 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37785 | /* 103488 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37786 | /* 103493 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37787 | /* 103498 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 37788 | /* 103501 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37789 | /* 103505 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37790 | /* 103510 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 37791 | /* 103512 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 37792 | /* 103515 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37793 | /* 103519 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37794 | /* 103524 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 37795 | /* 103527 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37796 | /* 103532 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 37797 | /* 103535 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37798 | /* 103539 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37799 | /* 103544 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 37800 | /* 103547 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 37801 | /* 103551 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 37802 | /* 103554 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37803 | /* 103559 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37804 | /* 103564 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37805 | /* 103569 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 37806 | /* 103572 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37807 | /* 103576 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37808 | /* 103581 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 37809 | /* 103583 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 37810 | /* 103586 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37811 | /* 103590 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37812 | /* 103595 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 37813 | /* 103598 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37814 | /* 103603 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 37815 | /* 103606 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37816 | /* 103610 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37817 | /* 103615 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 37818 | /* 103618 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc |
| 37819 | /* 103622 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 37820 | /* 103625 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37821 | /* 103630 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37822 | /* 103635 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37823 | /* 103640 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 37824 | /* 103643 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd), |
| 37825 | /* 103647 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37826 | /* 103652 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 37827 | /* 103655 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 37828 | /* 103658 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 37829 | /* 103661 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 37830 | /* 103664 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37831 | /* 103670 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37832 | /* 103672 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 37833 | /* 103675 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37834 | /* 103679 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37835 | /* 103684 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 37836 | /* 103687 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37837 | /* 103692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37838 | /* 103695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 37839 | /* 103697 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 37840 | /* 103704 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 37841 | /* 103709 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37842 | /* 103714 */ // GIR_Coverage, 6545, |
| 37843 | /* 103714 */ GIR_EraseRootFromParent_Done, |
| 37844 | /* 103715 */ // Label 3209: @103715 |
| 37845 | /* 103715 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3210*/ GIMT_Encode4(104038), GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), // Rule ID 6546 // |
| 37846 | /* 103722 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 37847 | /* 103726 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 37848 | /* 103730 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37849 | /* 103734 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 37850 | /* 103738 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37851 | /* 103743 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37852 | /* 103748 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37853 | /* 103750 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 37854 | /* 103750 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 37855 | /* 103753 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37856 | /* 103757 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37857 | /* 103762 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 37858 | /* 103764 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 37859 | /* 103767 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37860 | /* 103771 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37861 | /* 103776 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 37862 | /* 103779 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37863 | /* 103784 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 37864 | /* 103787 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37865 | /* 103791 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37866 | /* 103796 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 37867 | /* 103799 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 37868 | /* 103803 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 37869 | /* 103806 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37870 | /* 103811 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37871 | /* 103816 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37872 | /* 103821 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 37873 | /* 103824 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37874 | /* 103828 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37875 | /* 103833 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 37876 | /* 103835 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 37877 | /* 103838 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37878 | /* 103842 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37879 | /* 103847 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 37880 | /* 103850 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37881 | /* 103855 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 37882 | /* 103858 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37883 | /* 103862 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37884 | /* 103867 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 37885 | /* 103870 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 37886 | /* 103874 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 37887 | /* 103877 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37888 | /* 103882 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37889 | /* 103887 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37890 | /* 103892 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 37891 | /* 103895 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37892 | /* 103899 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37893 | /* 103904 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 37894 | /* 103906 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 37895 | /* 103909 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37896 | /* 103913 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37897 | /* 103918 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 37898 | /* 103921 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37899 | /* 103926 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 37900 | /* 103929 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37901 | /* 103933 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37902 | /* 103938 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 37903 | /* 103941 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc |
| 37904 | /* 103945 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 37905 | /* 103948 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37906 | /* 103953 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37907 | /* 103958 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37908 | /* 103963 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 37909 | /* 103966 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd), |
| 37910 | /* 103970 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37911 | /* 103975 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 37912 | /* 103978 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 37913 | /* 103981 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 37914 | /* 103984 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 37915 | /* 103987 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 37916 | /* 103993 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 37917 | /* 103995 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 37918 | /* 103998 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37919 | /* 104002 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37920 | /* 104007 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 37921 | /* 104010 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37922 | /* 104015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37923 | /* 104018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 37924 | /* 104020 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 37925 | /* 104027 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 37926 | /* 104032 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37927 | /* 104037 */ // GIR_Coverage, 6546, |
| 37928 | /* 104037 */ GIR_EraseRootFromParent_Done, |
| 37929 | /* 104038 */ // Label 3210: @104038 |
| 37930 | /* 104038 */ GIM_Reject, |
| 37931 | /* 104039 */ // Label 3208: @104039 |
| 37932 | /* 104039 */ GIM_Try, /*On fail goto*//*Label 3211*/ GIMT_Encode4(104953), |
| 37933 | /* 104044 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37934 | /* 104048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3212*/ GIMT_Encode4(104371), GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), // Rule ID 3086 // |
| 37935 | /* 104055 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 37936 | /* 104059 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 37937 | /* 104063 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 37938 | /* 104067 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 37939 | /* 104071 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37940 | /* 104076 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 37941 | /* 104081 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 37942 | /* 104083 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 37943 | /* 104083 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 37944 | /* 104086 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37945 | /* 104090 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37946 | /* 104095 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 37947 | /* 104097 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 37948 | /* 104100 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37949 | /* 104104 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37950 | /* 104109 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 37951 | /* 104112 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37952 | /* 104117 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 37953 | /* 104120 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37954 | /* 104124 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37955 | /* 104129 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 37956 | /* 104132 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 37957 | /* 104136 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 37958 | /* 104139 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37959 | /* 104144 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37960 | /* 104149 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37961 | /* 104154 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 37962 | /* 104157 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37963 | /* 104161 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37964 | /* 104166 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 37965 | /* 104168 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 37966 | /* 104171 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37967 | /* 104175 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37968 | /* 104180 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 37969 | /* 104183 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37970 | /* 104188 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 37971 | /* 104191 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37972 | /* 104195 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37973 | /* 104200 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 37974 | /* 104203 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 37975 | /* 104207 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 37976 | /* 104210 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37977 | /* 104215 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37978 | /* 104220 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37979 | /* 104225 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 37980 | /* 104228 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 37981 | /* 104232 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37982 | /* 104237 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 37983 | /* 104239 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 37984 | /* 104242 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 37985 | /* 104246 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37986 | /* 104251 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 37987 | /* 104254 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37988 | /* 104259 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 37989 | /* 104262 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 37990 | /* 104266 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 37991 | /* 104271 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 37992 | /* 104274 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 37993 | /* 104278 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 37994 | /* 104281 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37995 | /* 104286 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 37996 | /* 104291 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 37997 | /* 104296 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 37998 | /* 104299 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd), |
| 37999 | /* 104303 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38000 | /* 104308 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38001 | /* 104311 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38002 | /* 104314 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38003 | /* 104317 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38004 | /* 104320 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38005 | /* 104326 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38006 | /* 104328 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38007 | /* 104331 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38008 | /* 104335 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38009 | /* 104340 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38010 | /* 104343 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38011 | /* 104348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38012 | /* 104351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38013 | /* 104353 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38014 | /* 104360 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38015 | /* 104365 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38016 | /* 104370 */ // GIR_Coverage, 3086, |
| 38017 | /* 104370 */ GIR_EraseRootFromParent_Done, |
| 38018 | /* 104371 */ // Label 3212: @104371 |
| 38019 | /* 104371 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3213*/ GIMT_Encode4(104694), GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), // Rule ID 3088 // |
| 38020 | /* 104378 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38021 | /* 104382 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38022 | /* 104386 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38023 | /* 104390 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38024 | /* 104394 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38025 | /* 104399 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38026 | /* 104404 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38027 | /* 104406 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38028 | /* 104406 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 38029 | /* 104409 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38030 | /* 104413 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38031 | /* 104418 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 38032 | /* 104420 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 38033 | /* 104423 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38034 | /* 104427 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38035 | /* 104432 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 38036 | /* 104435 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38037 | /* 104440 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 38038 | /* 104443 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38039 | /* 104447 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38040 | /* 104452 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 38041 | /* 104455 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 38042 | /* 104459 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 38043 | /* 104462 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38044 | /* 104467 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38045 | /* 104472 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38046 | /* 104477 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38047 | /* 104480 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38048 | /* 104484 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38049 | /* 104489 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38050 | /* 104491 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38051 | /* 104494 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38052 | /* 104498 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38053 | /* 104503 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38054 | /* 104506 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38055 | /* 104511 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38056 | /* 104514 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38057 | /* 104518 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38058 | /* 104523 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38059 | /* 104526 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38060 | /* 104530 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38061 | /* 104533 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38062 | /* 104538 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38063 | /* 104543 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38064 | /* 104548 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38065 | /* 104551 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38066 | /* 104555 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38067 | /* 104560 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38068 | /* 104562 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38069 | /* 104565 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38070 | /* 104569 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38071 | /* 104574 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38072 | /* 104577 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38073 | /* 104582 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38074 | /* 104585 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38075 | /* 104589 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38076 | /* 104594 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38077 | /* 104597 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 38078 | /* 104601 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38079 | /* 104604 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38080 | /* 104609 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38081 | /* 104614 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38082 | /* 104619 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38083 | /* 104622 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd), |
| 38084 | /* 104626 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38085 | /* 104631 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38086 | /* 104634 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38087 | /* 104637 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38088 | /* 104640 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38089 | /* 104643 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38090 | /* 104649 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38091 | /* 104651 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38092 | /* 104654 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38093 | /* 104658 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38094 | /* 104663 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38095 | /* 104666 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38096 | /* 104671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38097 | /* 104674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38098 | /* 104676 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38099 | /* 104683 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38100 | /* 104688 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38101 | /* 104693 */ // GIR_Coverage, 3088, |
| 38102 | /* 104693 */ GIR_EraseRootFromParent_Done, |
| 38103 | /* 104694 */ // Label 3213: @104694 |
| 38104 | /* 104694 */ GIM_Try, /*On fail goto*//*Label 3214*/ GIMT_Encode4(104952), |
| 38105 | /* 104699 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38106 | /* 104703 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3215*/ GIMT_Encode4(104730), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 619 // |
| 38107 | /* 104710 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 38108 | /* 104710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS), |
| 38109 | /* 104713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38110 | /* 104715 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38111 | /* 104717 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38112 | /* 104719 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38113 | /* 104722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38114 | /* 104728 */ GIR_RootConstrainSelectedInstOperands, |
| 38115 | /* 104729 */ // GIR_Coverage, 619, |
| 38116 | /* 104729 */ GIR_EraseRootFromParent_Done, |
| 38117 | /* 104730 */ // Label 3215: @104730 |
| 38118 | /* 104730 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3216*/ GIMT_Encode4(104951), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3083 // |
| 38119 | /* 104737 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VADDfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38120 | /* 104737 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38121 | /* 104740 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38122 | /* 104744 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38123 | /* 104749 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38124 | /* 104751 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38125 | /* 104754 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38126 | /* 104758 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38127 | /* 104763 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38128 | /* 104766 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38129 | /* 104771 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38130 | /* 104774 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38131 | /* 104778 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38132 | /* 104783 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38133 | /* 104786 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 38134 | /* 104790 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38135 | /* 104793 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38136 | /* 104798 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38137 | /* 104803 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38138 | /* 104808 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38139 | /* 104811 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38140 | /* 104815 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38141 | /* 104820 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38142 | /* 104822 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38143 | /* 104825 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38144 | /* 104829 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38145 | /* 104834 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38146 | /* 104837 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38147 | /* 104842 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38148 | /* 104845 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38149 | /* 104849 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38150 | /* 104854 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38151 | /* 104857 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 38152 | /* 104861 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38153 | /* 104864 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38154 | /* 104869 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38155 | /* 104874 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38156 | /* 104879 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38157 | /* 104882 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VADDfd), |
| 38158 | /* 104886 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38159 | /* 104891 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38160 | /* 104894 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38161 | /* 104897 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38162 | /* 104900 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38163 | /* 104906 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38164 | /* 104908 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38165 | /* 104911 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38166 | /* 104915 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38167 | /* 104920 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38168 | /* 104923 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38169 | /* 104928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38170 | /* 104931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38171 | /* 104933 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38172 | /* 104940 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38173 | /* 104945 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38174 | /* 104950 */ // GIR_Coverage, 3083, |
| 38175 | /* 104950 */ GIR_EraseRootFromParent_Done, |
| 38176 | /* 104951 */ // Label 3216: @104951 |
| 38177 | /* 104951 */ GIM_Reject, |
| 38178 | /* 104952 */ // Label 3214: @104952 |
| 38179 | /* 104952 */ GIM_Reject, |
| 38180 | /* 104953 */ // Label 3211: @104953 |
| 38181 | /* 104953 */ GIM_Reject, |
| 38182 | /* 104954 */ // Label 3207: @104954 |
| 38183 | /* 104954 */ GIM_Reject, |
| 38184 | /* 104955 */ // Label 3200: @104955 |
| 38185 | /* 104955 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3217*/ GIMT_Encode4(105000), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 617 // |
| 38186 | /* 104962 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 38187 | /* 104965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 38188 | /* 104968 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38189 | /* 104972 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38190 | /* 104976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38191 | /* 104980 */ // (fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 38192 | /* 104980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD), |
| 38193 | /* 104983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 38194 | /* 104985 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 38195 | /* 104987 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 38196 | /* 104989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38197 | /* 104992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38198 | /* 104998 */ GIR_RootConstrainSelectedInstOperands, |
| 38199 | /* 104999 */ // GIR_Coverage, 617, |
| 38200 | /* 104999 */ GIR_EraseRootFromParent_Done, |
| 38201 | /* 105000 */ // Label 3217: @105000 |
| 38202 | /* 105000 */ GIM_Reject, |
| 38203 | /* 105001 */ // Label 3201: @105001 |
| 38204 | /* 105001 */ GIM_Try, /*On fail goto*//*Label 3218*/ GIMT_Encode4(105184), |
| 38205 | /* 105006 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38206 | /* 105009 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38207 | /* 105012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38208 | /* 105016 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3219*/ GIMT_Encode4(105081), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 6175 // |
| 38209 | /* 105023 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38210 | /* 105027 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38211 | /* 105031 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38212 | /* 105035 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38213 | /* 105039 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38214 | /* 105044 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38215 | /* 105049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38216 | /* 105053 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38217 | /* 105055 */ // (fadd:{ *:[v4f16] } (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm), DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38218 | /* 105055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd), |
| 38219 | /* 105058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38220 | /* 105060 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 38221 | /* 105062 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38222 | /* 105066 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38223 | /* 105070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38224 | /* 105073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38225 | /* 105079 */ GIR_RootConstrainSelectedInstOperands, |
| 38226 | /* 105080 */ // GIR_Coverage, 6175, |
| 38227 | /* 105080 */ GIR_EraseRootFromParent_Done, |
| 38228 | /* 105081 */ // Label 3219: @105081 |
| 38229 | /* 105081 */ GIM_Try, /*On fail goto*//*Label 3220*/ GIMT_Encode4(105183), |
| 38230 | /* 105086 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38231 | /* 105090 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3221*/ GIMT_Encode4(105151), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1101 // |
| 38232 | /* 105097 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38233 | /* 105101 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38234 | /* 105105 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38235 | /* 105109 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38236 | /* 105113 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38237 | /* 105118 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38238 | /* 105123 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38239 | /* 105125 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38240 | /* 105125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd), |
| 38241 | /* 105128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38242 | /* 105130 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38243 | /* 105132 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38244 | /* 105136 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38245 | /* 105140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38246 | /* 105143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38247 | /* 105149 */ GIR_RootConstrainSelectedInstOperands, |
| 38248 | /* 105150 */ // GIR_Coverage, 1101, |
| 38249 | /* 105150 */ GIR_EraseRootFromParent_Done, |
| 38250 | /* 105151 */ // Label 3221: @105151 |
| 38251 | /* 105151 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3222*/ GIMT_Encode4(105182), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 886 // |
| 38252 | /* 105158 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38253 | /* 105162 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VADDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38254 | /* 105162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhd), |
| 38255 | /* 105165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38256 | /* 105167 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38257 | /* 105169 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38258 | /* 105171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38259 | /* 105174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38260 | /* 105180 */ GIR_RootConstrainSelectedInstOperands, |
| 38261 | /* 105181 */ // GIR_Coverage, 886, |
| 38262 | /* 105181 */ GIR_EraseRootFromParent_Done, |
| 38263 | /* 105182 */ // Label 3222: @105182 |
| 38264 | /* 105182 */ GIM_Reject, |
| 38265 | /* 105183 */ // Label 3220: @105183 |
| 38266 | /* 105183 */ GIM_Reject, |
| 38267 | /* 105184 */ // Label 3218: @105184 |
| 38268 | /* 105184 */ GIM_Reject, |
| 38269 | /* 105185 */ // Label 3202: @105185 |
| 38270 | /* 105185 */ GIM_Try, /*On fail goto*//*Label 3223*/ GIMT_Encode4(105434), |
| 38271 | /* 105190 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38272 | /* 105193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38273 | /* 105196 */ GIM_Try, /*On fail goto*//*Label 3224*/ GIMT_Encode4(105373), |
| 38274 | /* 105201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38275 | /* 105205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3225*/ GIMT_Encode4(105270), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 6176 // |
| 38276 | /* 105212 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38277 | /* 105216 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38278 | /* 105220 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38279 | /* 105224 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38280 | /* 105228 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38281 | /* 105233 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38282 | /* 105238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38283 | /* 105242 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38284 | /* 105244 */ // (fadd:{ *:[v8f16] } (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm), QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38285 | /* 105244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq), |
| 38286 | /* 105247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38287 | /* 105249 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 38288 | /* 105251 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38289 | /* 105255 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38290 | /* 105259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38291 | /* 105262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38292 | /* 105268 */ GIR_RootConstrainSelectedInstOperands, |
| 38293 | /* 105269 */ // GIR_Coverage, 6176, |
| 38294 | /* 105269 */ GIR_EraseRootFromParent_Done, |
| 38295 | /* 105270 */ // Label 3225: @105270 |
| 38296 | /* 105270 */ GIM_Try, /*On fail goto*//*Label 3226*/ GIMT_Encode4(105372), |
| 38297 | /* 105275 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38298 | /* 105279 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3227*/ GIMT_Encode4(105340), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1102 // |
| 38299 | /* 105286 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38300 | /* 105290 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38301 | /* 105294 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38302 | /* 105298 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38303 | /* 105302 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38304 | /* 105307 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38305 | /* 105312 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38306 | /* 105314 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38307 | /* 105314 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq), |
| 38308 | /* 105317 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38309 | /* 105319 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38310 | /* 105321 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38311 | /* 105325 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38312 | /* 105329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38313 | /* 105332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38314 | /* 105338 */ GIR_RootConstrainSelectedInstOperands, |
| 38315 | /* 105339 */ // GIR_Coverage, 1102, |
| 38316 | /* 105339 */ GIR_EraseRootFromParent_Done, |
| 38317 | /* 105340 */ // Label 3227: @105340 |
| 38318 | /* 105340 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3228*/ GIMT_Encode4(105371), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 887 // |
| 38319 | /* 105347 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38320 | /* 105351 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VADDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38321 | /* 105351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhq), |
| 38322 | /* 105354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38323 | /* 105356 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38324 | /* 105358 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38325 | /* 105360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38326 | /* 105363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38327 | /* 105369 */ GIR_RootConstrainSelectedInstOperands, |
| 38328 | /* 105370 */ // GIR_Coverage, 887, |
| 38329 | /* 105370 */ GIR_EraseRootFromParent_Done, |
| 38330 | /* 105371 */ // Label 3228: @105371 |
| 38331 | /* 105371 */ GIM_Reject, |
| 38332 | /* 105372 */ // Label 3226: @105372 |
| 38333 | /* 105372 */ GIM_Reject, |
| 38334 | /* 105373 */ // Label 3224: @105373 |
| 38335 | /* 105373 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3229*/ GIMT_Encode4(105433), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4453 // |
| 38336 | /* 105380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38337 | /* 105384 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38338 | /* 105388 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38339 | /* 105392 */ // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 38340 | /* 105392 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38341 | /* 105395 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38342 | /* 105399 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38343 | /* 105404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16), |
| 38344 | /* 105407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38345 | /* 105409 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 38346 | /* 105411 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 38347 | /* 105413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38348 | /* 105416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38349 | /* 105422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38350 | /* 105428 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38351 | /* 105431 */ GIR_RootConstrainSelectedInstOperands, |
| 38352 | /* 105432 */ // GIR_Coverage, 4453, |
| 38353 | /* 105432 */ GIR_EraseRootFromParent_Done, |
| 38354 | /* 105433 */ // Label 3229: @105433 |
| 38355 | /* 105433 */ GIM_Reject, |
| 38356 | /* 105434 */ // Label 3223: @105434 |
| 38357 | /* 105434 */ GIM_Reject, |
| 38358 | /* 105435 */ // Label 3203: @105435 |
| 38359 | /* 105435 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3230*/ GIMT_Encode4(105480), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 884 // |
| 38360 | /* 105442 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 38361 | /* 105445 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38362 | /* 105448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38363 | /* 105452 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38364 | /* 105456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38365 | /* 105460 */ // (fadd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VADDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 38366 | /* 105460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfd), |
| 38367 | /* 105463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38368 | /* 105465 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38369 | /* 105467 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38370 | /* 105469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38371 | /* 105472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38372 | /* 105478 */ GIR_RootConstrainSelectedInstOperands, |
| 38373 | /* 105479 */ // GIR_Coverage, 884, |
| 38374 | /* 105479 */ GIR_EraseRootFromParent_Done, |
| 38375 | /* 105480 */ // Label 3230: @105480 |
| 38376 | /* 105480 */ GIM_Reject, |
| 38377 | /* 105481 */ // Label 3204: @105481 |
| 38378 | /* 105481 */ GIM_Try, /*On fail goto*//*Label 3231*/ GIMT_Encode4(105592), |
| 38379 | /* 105486 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38380 | /* 105489 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38381 | /* 105492 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3232*/ GIMT_Encode4(105531), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 885 // |
| 38382 | /* 105499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38383 | /* 105503 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38384 | /* 105507 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38385 | /* 105511 */ // (fadd:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VADDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 38386 | /* 105511 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfq), |
| 38387 | /* 105514 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38388 | /* 105516 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38389 | /* 105518 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38390 | /* 105520 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38391 | /* 105523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38392 | /* 105529 */ GIR_RootConstrainSelectedInstOperands, |
| 38393 | /* 105530 */ // GIR_Coverage, 885, |
| 38394 | /* 105530 */ GIR_EraseRootFromParent_Done, |
| 38395 | /* 105531 */ // Label 3232: @105531 |
| 38396 | /* 105531 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3233*/ GIMT_Encode4(105591), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4446 // |
| 38397 | /* 105538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38398 | /* 105542 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38399 | /* 105546 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38400 | /* 105550 */ // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 38401 | /* 105550 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38402 | /* 105553 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38403 | /* 105557 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38404 | /* 105562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32), |
| 38405 | /* 105565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38406 | /* 105567 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 38407 | /* 105569 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 38408 | /* 105571 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38409 | /* 105574 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38410 | /* 105580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38411 | /* 105586 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38412 | /* 105589 */ GIR_RootConstrainSelectedInstOperands, |
| 38413 | /* 105590 */ // GIR_Coverage, 4446, |
| 38414 | /* 105590 */ GIR_EraseRootFromParent_Done, |
| 38415 | /* 105591 */ // Label 3233: @105591 |
| 38416 | /* 105591 */ GIM_Reject, |
| 38417 | /* 105592 */ // Label 3231: @105592 |
| 38418 | /* 105592 */ GIM_Reject, |
| 38419 | /* 105593 */ // Label 3205: @105593 |
| 38420 | /* 105593 */ GIM_Reject, |
| 38421 | /* 105594 */ // Label 41: @105594 |
| 38422 | /* 105594 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3241*/ GIMT_Encode4(107246), |
| 38423 | /* 105605 */ /*GILLT_s16*//*Label 3234*/ GIMT_Encode4(105657), |
| 38424 | /* 105609 */ /*GILLT_s32*//*Label 3235*/ GIMT_Encode4(105703), |
| 38425 | /* 105613 */ /*GILLT_s64*//*Label 3236*/ GIMT_Encode4(106628), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38426 | /* 105641 */ /*GILLT_v4s16*//*Label 3237*/ GIMT_Encode4(106674), |
| 38427 | /* 105645 */ /*GILLT_v8s16*//*Label 3238*/ GIMT_Encode4(106848), |
| 38428 | /* 105649 */ /*GILLT_v2s32*//*Label 3239*/ GIMT_Encode4(107088), |
| 38429 | /* 105653 */ /*GILLT_v4s32*//*Label 3240*/ GIMT_Encode4(107134), |
| 38430 | /* 105657 */ // Label 3234: @105657 |
| 38431 | /* 105657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3242*/ GIMT_Encode4(105702), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 627 // |
| 38432 | /* 105664 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 38433 | /* 105667 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 38434 | /* 105670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38435 | /* 105674 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38436 | /* 105678 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38437 | /* 105682 */ // (fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 38438 | /* 105682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH), |
| 38439 | /* 105685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38440 | /* 105687 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38441 | /* 105689 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38442 | /* 105691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38443 | /* 105694 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38444 | /* 105700 */ GIR_RootConstrainSelectedInstOperands, |
| 38445 | /* 105701 */ // GIR_Coverage, 627, |
| 38446 | /* 105701 */ GIR_EraseRootFromParent_Done, |
| 38447 | /* 105702 */ // Label 3242: @105702 |
| 38448 | /* 105702 */ GIM_Reject, |
| 38449 | /* 105703 */ // Label 3235: @105703 |
| 38450 | /* 105703 */ GIM_Try, /*On fail goto*//*Label 3243*/ GIMT_Encode4(106627), |
| 38451 | /* 105708 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 38452 | /* 105711 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 38453 | /* 105714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38454 | /* 105718 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38455 | /* 105722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3244*/ GIMT_Encode4(106045), GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), // Rule ID 3087 // |
| 38456 | /* 105729 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38457 | /* 105733 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38458 | /* 105737 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38459 | /* 105741 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38460 | /* 105745 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38461 | /* 105750 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38462 | /* 105755 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38463 | /* 105757 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38464 | /* 105757 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 38465 | /* 105760 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38466 | /* 105764 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38467 | /* 105769 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 38468 | /* 105771 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 38469 | /* 105774 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38470 | /* 105778 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38471 | /* 105783 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 38472 | /* 105786 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38473 | /* 105791 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 38474 | /* 105794 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38475 | /* 105798 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38476 | /* 105803 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 38477 | /* 105806 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 38478 | /* 105810 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 38479 | /* 105813 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38480 | /* 105818 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38481 | /* 105823 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38482 | /* 105828 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38483 | /* 105831 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38484 | /* 105835 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38485 | /* 105840 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38486 | /* 105842 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38487 | /* 105845 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38488 | /* 105849 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38489 | /* 105854 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38490 | /* 105857 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38491 | /* 105862 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38492 | /* 105865 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38493 | /* 105869 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38494 | /* 105874 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38495 | /* 105877 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38496 | /* 105881 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38497 | /* 105884 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38498 | /* 105889 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38499 | /* 105894 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38500 | /* 105899 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38501 | /* 105902 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38502 | /* 105906 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38503 | /* 105911 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38504 | /* 105913 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38505 | /* 105916 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38506 | /* 105920 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38507 | /* 105925 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38508 | /* 105928 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38509 | /* 105933 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38510 | /* 105936 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38511 | /* 105940 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38512 | /* 105945 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38513 | /* 105948 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 38514 | /* 105952 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38515 | /* 105955 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38516 | /* 105960 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38517 | /* 105965 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38518 | /* 105970 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38519 | /* 105973 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLSfd), |
| 38520 | /* 105977 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38521 | /* 105982 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38522 | /* 105985 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38523 | /* 105988 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38524 | /* 105991 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38525 | /* 105994 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38526 | /* 106000 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38527 | /* 106002 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38528 | /* 106005 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38529 | /* 106009 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38530 | /* 106014 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38531 | /* 106017 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38532 | /* 106022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38533 | /* 106025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38534 | /* 106027 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38535 | /* 106034 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38536 | /* 106039 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38537 | /* 106044 */ // GIR_Coverage, 3087, |
| 38538 | /* 106044 */ GIR_EraseRootFromParent_Done, |
| 38539 | /* 106045 */ // Label 3244: @106045 |
| 38540 | /* 106045 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3245*/ GIMT_Encode4(106368), GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), // Rule ID 3089 // |
| 38541 | /* 106052 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38542 | /* 106056 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38543 | /* 106060 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38544 | /* 106064 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 38545 | /* 106068 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38546 | /* 106073 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38547 | /* 106078 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38548 | /* 106080 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38549 | /* 106080 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32, |
| 38550 | /* 106083 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38551 | /* 106087 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38552 | /* 106092 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 38553 | /* 106094 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32, |
| 38554 | /* 106097 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38555 | /* 106101 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38556 | /* 106106 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10, |
| 38557 | /* 106109 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38558 | /* 106114 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32, |
| 38559 | /* 106117 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38560 | /* 106121 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38561 | /* 106126 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 38562 | /* 106129 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b |
| 38563 | /* 106133 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17, |
| 38564 | /* 106136 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38565 | /* 106141 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38566 | /* 106146 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38567 | /* 106151 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38568 | /* 106154 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38569 | /* 106158 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38570 | /* 106163 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38571 | /* 106165 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38572 | /* 106168 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38573 | /* 106172 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38574 | /* 106177 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38575 | /* 106180 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38576 | /* 106185 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38577 | /* 106188 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38578 | /* 106192 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38579 | /* 106197 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38580 | /* 106200 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38581 | /* 106204 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38582 | /* 106207 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38583 | /* 106212 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38584 | /* 106217 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38585 | /* 106222 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38586 | /* 106225 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38587 | /* 106229 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38588 | /* 106234 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38589 | /* 106236 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38590 | /* 106239 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38591 | /* 106243 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38592 | /* 106248 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38593 | /* 106251 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38594 | /* 106256 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38595 | /* 106259 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38596 | /* 106263 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38597 | /* 106268 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38598 | /* 106271 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc |
| 38599 | /* 106275 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38600 | /* 106278 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38601 | /* 106283 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38602 | /* 106288 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38603 | /* 106293 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38604 | /* 106296 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMSfd), |
| 38605 | /* 106300 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38606 | /* 106305 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38607 | /* 106308 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38608 | /* 106311 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8, |
| 38609 | /* 106314 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38610 | /* 106317 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38611 | /* 106323 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38612 | /* 106325 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38613 | /* 106328 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38614 | /* 106332 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38615 | /* 106337 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38616 | /* 106340 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38617 | /* 106345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38618 | /* 106348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38619 | /* 106350 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38620 | /* 106357 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38621 | /* 106362 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38622 | /* 106367 */ // GIR_Coverage, 3089, |
| 38623 | /* 106367 */ GIR_EraseRootFromParent_Done, |
| 38624 | /* 106368 */ // Label 3245: @106368 |
| 38625 | /* 106368 */ GIM_Try, /*On fail goto*//*Label 3246*/ GIMT_Encode4(106626), |
| 38626 | /* 106373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38627 | /* 106377 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3247*/ GIMT_Encode4(106404), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 625 // |
| 38628 | /* 106384 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 38629 | /* 106384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS), |
| 38630 | /* 106387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38631 | /* 106389 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38632 | /* 106391 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38633 | /* 106393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38634 | /* 106396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38635 | /* 106402 */ GIR_RootConstrainSelectedInstOperands, |
| 38636 | /* 106403 */ // GIR_Coverage, 625, |
| 38637 | /* 106403 */ GIR_EraseRootFromParent_Done, |
| 38638 | /* 106404 */ // Label 3247: @106404 |
| 38639 | /* 106404 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3248*/ GIMT_Encode4(106625), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3084 // |
| 38640 | /* 106411 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VSUBfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 38641 | /* 106411 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 38642 | /* 106414 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38643 | /* 106418 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38644 | /* 106423 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 38645 | /* 106425 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 38646 | /* 106428 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38647 | /* 106432 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38648 | /* 106437 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 38649 | /* 106440 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38650 | /* 106445 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 38651 | /* 106448 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38652 | /* 106452 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38653 | /* 106457 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 38654 | /* 106460 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 38655 | /* 106464 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 38656 | /* 106467 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38657 | /* 106472 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38658 | /* 106477 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38659 | /* 106482 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 38660 | /* 106485 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38661 | /* 106489 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38662 | /* 106494 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 38663 | /* 106496 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 38664 | /* 106499 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38665 | /* 106503 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38666 | /* 106508 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 38667 | /* 106511 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38668 | /* 106516 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 38669 | /* 106519 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 38670 | /* 106523 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38671 | /* 106528 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 38672 | /* 106531 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 38673 | /* 106535 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 38674 | /* 106538 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38675 | /* 106543 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38676 | /* 106548 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 38677 | /* 106553 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 38678 | /* 106556 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VSUBfd), |
| 38679 | /* 106560 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38680 | /* 106565 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 38681 | /* 106568 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 38682 | /* 106571 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 38683 | /* 106574 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38684 | /* 106580 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 38685 | /* 106582 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 38686 | /* 106585 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38687 | /* 106589 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38688 | /* 106594 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 38689 | /* 106597 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38690 | /* 106602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 38691 | /* 106605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 38692 | /* 106607 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 38693 | /* 106614 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 38694 | /* 106619 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 38695 | /* 106624 */ // GIR_Coverage, 3084, |
| 38696 | /* 106624 */ GIR_EraseRootFromParent_Done, |
| 38697 | /* 106625 */ // Label 3248: @106625 |
| 38698 | /* 106625 */ GIM_Reject, |
| 38699 | /* 106626 */ // Label 3246: @106626 |
| 38700 | /* 106626 */ GIM_Reject, |
| 38701 | /* 106627 */ // Label 3243: @106627 |
| 38702 | /* 106627 */ GIM_Reject, |
| 38703 | /* 106628 */ // Label 3236: @106628 |
| 38704 | /* 106628 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3249*/ GIMT_Encode4(106673), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 623 // |
| 38705 | /* 106635 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 38706 | /* 106638 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 38707 | /* 106641 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38708 | /* 106645 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38709 | /* 106649 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38710 | /* 106653 */ // (fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 38711 | /* 106653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD), |
| 38712 | /* 106656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 38713 | /* 106658 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 38714 | /* 106660 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 38715 | /* 106662 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38716 | /* 106665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38717 | /* 106671 */ GIR_RootConstrainSelectedInstOperands, |
| 38718 | /* 106672 */ // GIR_Coverage, 623, |
| 38719 | /* 106672 */ GIR_EraseRootFromParent_Done, |
| 38720 | /* 106673 */ // Label 3249: @106673 |
| 38721 | /* 106673 */ GIM_Reject, |
| 38722 | /* 106674 */ // Label 3237: @106674 |
| 38723 | /* 106674 */ GIM_Try, /*On fail goto*//*Label 3250*/ GIMT_Encode4(106847), |
| 38724 | /* 106679 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38725 | /* 106682 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38726 | /* 106685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38727 | /* 106689 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38728 | /* 106693 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3251*/ GIMT_Encode4(106754), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx), // Rule ID 1067 // |
| 38729 | /* 106700 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38730 | /* 106704 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38731 | /* 106708 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38732 | /* 106712 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38733 | /* 106716 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38734 | /* 106721 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38735 | /* 106726 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38736 | /* 106728 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VMLShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38737 | /* 106728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShd), |
| 38738 | /* 106731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38739 | /* 106733 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38740 | /* 106735 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38741 | /* 106739 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38742 | /* 106743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38743 | /* 106746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38744 | /* 106752 */ GIR_RootConstrainSelectedInstOperands, |
| 38745 | /* 106753 */ // GIR_Coverage, 1067, |
| 38746 | /* 106753 */ GIR_EraseRootFromParent_Done, |
| 38747 | /* 106754 */ // Label 3251: @106754 |
| 38748 | /* 106754 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3252*/ GIMT_Encode4(106815), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1111 // |
| 38749 | /* 106761 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38750 | /* 106765 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38751 | /* 106769 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 38752 | /* 106773 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 38753 | /* 106777 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38754 | /* 106782 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38755 | /* 106787 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38756 | /* 106789 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38757 | /* 106789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShd), |
| 38758 | /* 106792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38759 | /* 106794 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38760 | /* 106796 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38761 | /* 106800 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38762 | /* 106804 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38763 | /* 106807 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38764 | /* 106813 */ GIR_RootConstrainSelectedInstOperands, |
| 38765 | /* 106814 */ // GIR_Coverage, 1111, |
| 38766 | /* 106814 */ GIR_EraseRootFromParent_Done, |
| 38767 | /* 106815 */ // Label 3252: @106815 |
| 38768 | /* 106815 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3253*/ GIMT_Encode4(106846), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1132 // |
| 38769 | /* 106822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38770 | /* 106826 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VSUBhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 38771 | /* 106826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhd), |
| 38772 | /* 106829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38773 | /* 106831 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38774 | /* 106833 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38775 | /* 106835 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38776 | /* 106838 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38777 | /* 106844 */ GIR_RootConstrainSelectedInstOperands, |
| 38778 | /* 106845 */ // GIR_Coverage, 1132, |
| 38779 | /* 106845 */ GIR_EraseRootFromParent_Done, |
| 38780 | /* 106846 */ // Label 3253: @106846 |
| 38781 | /* 106846 */ GIM_Reject, |
| 38782 | /* 106847 */ // Label 3250: @106847 |
| 38783 | /* 106847 */ GIM_Reject, |
| 38784 | /* 106848 */ // Label 3238: @106848 |
| 38785 | /* 106848 */ GIM_Try, /*On fail goto*//*Label 3254*/ GIMT_Encode4(107087), |
| 38786 | /* 106853 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38787 | /* 106856 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38788 | /* 106859 */ GIM_Try, /*On fail goto*//*Label 3255*/ GIMT_Encode4(107026), |
| 38789 | /* 106864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38790 | /* 106868 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38791 | /* 106872 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3256*/ GIMT_Encode4(106933), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx), // Rule ID 1068 // |
| 38792 | /* 106879 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38793 | /* 106883 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38794 | /* 106887 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38795 | /* 106891 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38796 | /* 106895 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38797 | /* 106900 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38798 | /* 106905 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38799 | /* 106907 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VMLShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38800 | /* 106907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShq), |
| 38801 | /* 106910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38802 | /* 106912 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38803 | /* 106914 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38804 | /* 106918 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38805 | /* 106922 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38806 | /* 106925 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38807 | /* 106931 */ GIR_RootConstrainSelectedInstOperands, |
| 38808 | /* 106932 */ // GIR_Coverage, 1068, |
| 38809 | /* 106932 */ GIR_EraseRootFromParent_Done, |
| 38810 | /* 106933 */ // Label 3256: @106933 |
| 38811 | /* 106933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3257*/ GIMT_Encode4(106994), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1112 // |
| 38812 | /* 106940 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38813 | /* 106944 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 38814 | /* 106948 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 38815 | /* 106952 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 38816 | /* 106956 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38817 | /* 106961 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38818 | /* 106966 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38819 | /* 106968 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38820 | /* 106968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShq), |
| 38821 | /* 106971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38822 | /* 106973 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 38823 | /* 106975 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 38824 | /* 106979 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm |
| 38825 | /* 106983 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38826 | /* 106986 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38827 | /* 106992 */ GIR_RootConstrainSelectedInstOperands, |
| 38828 | /* 106993 */ // GIR_Coverage, 1112, |
| 38829 | /* 106993 */ GIR_EraseRootFromParent_Done, |
| 38830 | /* 106994 */ // Label 3257: @106994 |
| 38831 | /* 106994 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3258*/ GIMT_Encode4(107025), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1133 // |
| 38832 | /* 107001 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38833 | /* 107005 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VSUBhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 38834 | /* 107005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhq), |
| 38835 | /* 107008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38836 | /* 107010 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38837 | /* 107012 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38838 | /* 107014 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38839 | /* 107017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38840 | /* 107023 */ GIR_RootConstrainSelectedInstOperands, |
| 38841 | /* 107024 */ // GIR_Coverage, 1133, |
| 38842 | /* 107024 */ GIR_EraseRootFromParent_Done, |
| 38843 | /* 107025 */ // Label 3258: @107025 |
| 38844 | /* 107025 */ GIM_Reject, |
| 38845 | /* 107026 */ // Label 3255: @107026 |
| 38846 | /* 107026 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3259*/ GIMT_Encode4(107086), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4467 // |
| 38847 | /* 107033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38848 | /* 107037 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38849 | /* 107041 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38850 | /* 107045 */ // (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 38851 | /* 107045 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38852 | /* 107048 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38853 | /* 107052 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38854 | /* 107057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16), |
| 38855 | /* 107060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38856 | /* 107062 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 38857 | /* 107064 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 38858 | /* 107066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38859 | /* 107069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38860 | /* 107075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38861 | /* 107081 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38862 | /* 107084 */ GIR_RootConstrainSelectedInstOperands, |
| 38863 | /* 107085 */ // GIR_Coverage, 4467, |
| 38864 | /* 107085 */ GIR_EraseRootFromParent_Done, |
| 38865 | /* 107086 */ // Label 3259: @107086 |
| 38866 | /* 107086 */ GIM_Reject, |
| 38867 | /* 107087 */ // Label 3254: @107087 |
| 38868 | /* 107087 */ GIM_Reject, |
| 38869 | /* 107088 */ // Label 3239: @107088 |
| 38870 | /* 107088 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3260*/ GIMT_Encode4(107133), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1130 // |
| 38871 | /* 107095 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 38872 | /* 107098 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 38873 | /* 107101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38874 | /* 107105 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38875 | /* 107109 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 38876 | /* 107113 */ // (fsub:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VSUBfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 38877 | /* 107113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfd), |
| 38878 | /* 107116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38879 | /* 107118 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38880 | /* 107120 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38881 | /* 107122 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38882 | /* 107125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38883 | /* 107131 */ GIR_RootConstrainSelectedInstOperands, |
| 38884 | /* 107132 */ // GIR_Coverage, 1130, |
| 38885 | /* 107132 */ GIR_EraseRootFromParent_Done, |
| 38886 | /* 107133 */ // Label 3260: @107133 |
| 38887 | /* 107133 */ GIM_Reject, |
| 38888 | /* 107134 */ // Label 3240: @107134 |
| 38889 | /* 107134 */ GIM_Try, /*On fail goto*//*Label 3261*/ GIMT_Encode4(107245), |
| 38890 | /* 107139 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 38891 | /* 107142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 38892 | /* 107145 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3262*/ GIMT_Encode4(107184), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1131 // |
| 38893 | /* 107152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38894 | /* 107156 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38895 | /* 107160 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 38896 | /* 107164 */ // (fsub:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VSUBfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 38897 | /* 107164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfq), |
| 38898 | /* 107167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 38899 | /* 107169 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 38900 | /* 107171 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 38901 | /* 107173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38902 | /* 107176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38903 | /* 107182 */ GIR_RootConstrainSelectedInstOperands, |
| 38904 | /* 107183 */ // GIR_Coverage, 1131, |
| 38905 | /* 107183 */ GIR_EraseRootFromParent_Done, |
| 38906 | /* 107184 */ // Label 3262: @107184 |
| 38907 | /* 107184 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3263*/ GIMT_Encode4(107244), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4460 // |
| 38908 | /* 107191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38909 | /* 107195 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38910 | /* 107199 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 38911 | /* 107203 */ // (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 38912 | /* 107203 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 38913 | /* 107206 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 38914 | /* 107210 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 38915 | /* 107215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32), |
| 38916 | /* 107218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 38917 | /* 107220 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 38918 | /* 107222 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 38919 | /* 107224 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38920 | /* 107227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38921 | /* 107233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38922 | /* 107239 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 38923 | /* 107242 */ GIR_RootConstrainSelectedInstOperands, |
| 38924 | /* 107243 */ // GIR_Coverage, 4460, |
| 38925 | /* 107243 */ GIR_EraseRootFromParent_Done, |
| 38926 | /* 107244 */ // Label 3263: @107244 |
| 38927 | /* 107244 */ GIM_Reject, |
| 38928 | /* 107245 */ // Label 3261: @107245 |
| 38929 | /* 107245 */ GIM_Reject, |
| 38930 | /* 107246 */ // Label 3241: @107246 |
| 38931 | /* 107246 */ GIM_Reject, |
| 38932 | /* 107247 */ // Label 42: @107247 |
| 38933 | /* 107247 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3271*/ GIMT_Encode4(108215), |
| 38934 | /* 107258 */ /*GILLT_s16*//*Label 3264*/ GIMT_Encode4(107310), |
| 38935 | /* 107262 */ /*GILLT_s32*//*Label 3265*/ GIMT_Encode4(107356), |
| 38936 | /* 107266 */ /*GILLT_s64*//*Label 3266*/ GIMT_Encode4(107741), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 38937 | /* 107294 */ /*GILLT_v4s16*//*Label 3267*/ GIMT_Encode4(107899), |
| 38938 | /* 107298 */ /*GILLT_v8s16*//*Label 3268*/ GIMT_Encode4(107945), |
| 38939 | /* 107302 */ /*GILLT_v2s32*//*Label 3269*/ GIMT_Encode4(108057), |
| 38940 | /* 107306 */ /*GILLT_v4s32*//*Label 3270*/ GIMT_Encode4(108103), |
| 38941 | /* 107310 */ // Label 3264: @107310 |
| 38942 | /* 107310 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3272*/ GIMT_Encode4(107355), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 639 // |
| 38943 | /* 107317 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 38944 | /* 107320 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 38945 | /* 107323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38946 | /* 107327 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38947 | /* 107331 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 38948 | /* 107335 */ // (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 38949 | /* 107335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH), |
| 38950 | /* 107338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38951 | /* 107340 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 38952 | /* 107342 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 38953 | /* 107344 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38954 | /* 107347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38955 | /* 107353 */ GIR_RootConstrainSelectedInstOperands, |
| 38956 | /* 107354 */ // GIR_Coverage, 639, |
| 38957 | /* 107354 */ GIR_EraseRootFromParent_Done, |
| 38958 | /* 107355 */ // Label 3272: @107355 |
| 38959 | /* 107355 */ GIM_Reject, |
| 38960 | /* 107356 */ // Label 3265: @107356 |
| 38961 | /* 107356 */ GIM_Try, /*On fail goto*//*Label 3273*/ GIMT_Encode4(107740), |
| 38962 | /* 107361 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 38963 | /* 107364 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 38964 | /* 107367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38965 | /* 107371 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3274*/ GIMT_Encode4(107423), GIMT_Encode2(GIFBS_NoHonorSignDependentRounding), // Rule ID 2499 // |
| 38966 | /* 107378 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 38967 | /* 107382 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 38968 | /* 107386 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38969 | /* 107390 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38970 | /* 107395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38971 | /* 107399 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38972 | /* 107401 */ // (fmul:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) |
| 38973 | /* 107401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 38974 | /* 107404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38975 | /* 107406 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38976 | /* 107410 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 38977 | /* 107412 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38978 | /* 107415 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38979 | /* 107421 */ GIR_RootConstrainSelectedInstOperands, |
| 38980 | /* 107422 */ // GIR_Coverage, 2499, |
| 38981 | /* 107422 */ GIR_EraseRootFromParent_Done, |
| 38982 | /* 107423 */ // Label 3274: @107423 |
| 38983 | /* 107423 */ GIM_Try, /*On fail goto*//*Label 3275*/ GIMT_Encode4(107739), |
| 38984 | /* 107428 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38985 | /* 107432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3276*/ GIMT_Encode4(107480), GIMT_Encode2(GIFBS_NoHonorSignDependentRounding), // Rule ID 6308 // |
| 38986 | /* 107439 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 38987 | /* 107443 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 38988 | /* 107447 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 38989 | /* 107451 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 38990 | /* 107456 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 38991 | /* 107458 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) |
| 38992 | /* 107458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 38993 | /* 107461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 38994 | /* 107463 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 38995 | /* 107467 */ GIR_RootToRootCopy, /*OpIdx*/1, // b |
| 38996 | /* 107469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 38997 | /* 107472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 38998 | /* 107478 */ GIR_RootConstrainSelectedInstOperands, |
| 38999 | /* 107479 */ // GIR_Coverage, 6308, |
| 39000 | /* 107479 */ GIR_EraseRootFromParent_Done, |
| 39001 | /* 107480 */ // Label 3276: @107480 |
| 39002 | /* 107480 */ GIM_Try, /*On fail goto*//*Label 3277*/ GIMT_Encode4(107738), |
| 39003 | /* 107485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39004 | /* 107489 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3278*/ GIMT_Encode4(107516), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 637 // |
| 39005 | /* 107496 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39006 | /* 107496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS), |
| 39007 | /* 107499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39008 | /* 107501 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39009 | /* 107503 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39010 | /* 107505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39011 | /* 107508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39012 | /* 107514 */ GIR_RootConstrainSelectedInstOperands, |
| 39013 | /* 107515 */ // GIR_Coverage, 637, |
| 39014 | /* 107515 */ GIR_EraseRootFromParent_Done, |
| 39015 | /* 107516 */ // Label 3278: @107516 |
| 39016 | /* 107516 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3279*/ GIMT_Encode4(107737), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3085 // |
| 39017 | /* 107523 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMULfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 39018 | /* 107523 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 39019 | /* 107526 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39020 | /* 107530 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39021 | /* 107535 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 39022 | /* 107537 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 39023 | /* 107540 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39024 | /* 107544 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39025 | /* 107549 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 39026 | /* 107552 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39027 | /* 107557 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 39028 | /* 107560 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 39029 | /* 107564 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39030 | /* 107569 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 39031 | /* 107572 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 39032 | /* 107576 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 39033 | /* 107579 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39034 | /* 107584 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39035 | /* 107589 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 39036 | /* 107594 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 39037 | /* 107597 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39038 | /* 107601 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39039 | /* 107606 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 39040 | /* 107608 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 39041 | /* 107611 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39042 | /* 107615 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39043 | /* 107620 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 39044 | /* 107623 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39045 | /* 107628 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 39046 | /* 107631 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 39047 | /* 107635 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39048 | /* 107640 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 39049 | /* 107643 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 39050 | /* 107647 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 39051 | /* 107650 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39052 | /* 107655 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39053 | /* 107660 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 39054 | /* 107665 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 39055 | /* 107668 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMULfd), |
| 39056 | /* 107672 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39057 | /* 107677 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 39058 | /* 107680 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 39059 | /* 107683 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 39060 | /* 107686 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39061 | /* 107692 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 39062 | /* 107694 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 39063 | /* 107697 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39064 | /* 107701 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39065 | /* 107706 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 39066 | /* 107709 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39067 | /* 107714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 39068 | /* 107717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 39069 | /* 107719 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 39070 | /* 107726 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 39071 | /* 107731 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 39072 | /* 107736 */ // GIR_Coverage, 3085, |
| 39073 | /* 107736 */ GIR_EraseRootFromParent_Done, |
| 39074 | /* 107737 */ // Label 3279: @107737 |
| 39075 | /* 107737 */ GIM_Reject, |
| 39076 | /* 107738 */ // Label 3277: @107738 |
| 39077 | /* 107738 */ GIM_Reject, |
| 39078 | /* 107739 */ // Label 3275: @107739 |
| 39079 | /* 107739 */ GIM_Reject, |
| 39080 | /* 107740 */ // Label 3273: @107740 |
| 39081 | /* 107740 */ GIM_Reject, |
| 39082 | /* 107741 */ // Label 3266: @107741 |
| 39083 | /* 107741 */ GIM_Try, /*On fail goto*//*Label 3280*/ GIMT_Encode4(107898), |
| 39084 | /* 107746 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 39085 | /* 107749 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 39086 | /* 107752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39087 | /* 107756 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3281*/ GIMT_Encode4(107808), GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding), // Rule ID 2498 // |
| 39088 | /* 107763 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39089 | /* 107767 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39090 | /* 107771 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39091 | /* 107775 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39092 | /* 107780 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39093 | /* 107784 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39094 | /* 107786 */ // (fmul:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a), DPR:{ *:[f64] }:$b) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b) |
| 39095 | /* 107786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 39096 | /* 107789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39097 | /* 107791 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 39098 | /* 107795 */ GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 39099 | /* 107797 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39100 | /* 107800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39101 | /* 107806 */ GIR_RootConstrainSelectedInstOperands, |
| 39102 | /* 107807 */ // GIR_Coverage, 2498, |
| 39103 | /* 107807 */ GIR_EraseRootFromParent_Done, |
| 39104 | /* 107808 */ // Label 3281: @107808 |
| 39105 | /* 107808 */ GIM_Try, /*On fail goto*//*Label 3282*/ GIMT_Encode4(107897), |
| 39106 | /* 107813 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39107 | /* 107817 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3283*/ GIMT_Encode4(107865), GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding), // Rule ID 6307 // |
| 39108 | /* 107824 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39109 | /* 107828 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39110 | /* 107832 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39111 | /* 107836 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39112 | /* 107841 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39113 | /* 107843 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$b, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b) |
| 39114 | /* 107843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 39115 | /* 107846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39116 | /* 107848 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 39117 | /* 107852 */ GIR_RootToRootCopy, /*OpIdx*/1, // b |
| 39118 | /* 107854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39119 | /* 107857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39120 | /* 107863 */ GIR_RootConstrainSelectedInstOperands, |
| 39121 | /* 107864 */ // GIR_Coverage, 6307, |
| 39122 | /* 107864 */ GIR_EraseRootFromParent_Done, |
| 39123 | /* 107865 */ // Label 3283: @107865 |
| 39124 | /* 107865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3284*/ GIMT_Encode4(107896), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 635 // |
| 39125 | /* 107872 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39126 | /* 107876 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39127 | /* 107876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD), |
| 39128 | /* 107879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39129 | /* 107881 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 39130 | /* 107883 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39131 | /* 107885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39132 | /* 107888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39133 | /* 107894 */ GIR_RootConstrainSelectedInstOperands, |
| 39134 | /* 107895 */ // GIR_Coverage, 635, |
| 39135 | /* 107895 */ GIR_EraseRootFromParent_Done, |
| 39136 | /* 107896 */ // Label 3284: @107896 |
| 39137 | /* 107896 */ GIM_Reject, |
| 39138 | /* 107897 */ // Label 3282: @107897 |
| 39139 | /* 107897 */ GIM_Reject, |
| 39140 | /* 107898 */ // Label 3280: @107898 |
| 39141 | /* 107898 */ GIM_Reject, |
| 39142 | /* 107899 */ // Label 3267: @107899 |
| 39143 | /* 107899 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3285*/ GIMT_Encode4(107944), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 965 // |
| 39144 | /* 107906 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 39145 | /* 107909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39146 | /* 107912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39147 | /* 107916 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39148 | /* 107920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39149 | /* 107924 */ // (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMULhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 39150 | /* 107924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhd), |
| 39151 | /* 107927 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39152 | /* 107929 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39153 | /* 107931 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39154 | /* 107933 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39155 | /* 107936 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39156 | /* 107942 */ GIR_RootConstrainSelectedInstOperands, |
| 39157 | /* 107943 */ // GIR_Coverage, 965, |
| 39158 | /* 107943 */ GIR_EraseRootFromParent_Done, |
| 39159 | /* 107944 */ // Label 3285: @107944 |
| 39160 | /* 107944 */ GIM_Reject, |
| 39161 | /* 107945 */ // Label 3268: @107945 |
| 39162 | /* 107945 */ GIM_Try, /*On fail goto*//*Label 3286*/ GIMT_Encode4(108056), |
| 39163 | /* 107950 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39164 | /* 107953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39165 | /* 107956 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3287*/ GIMT_Encode4(107995), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 966 // |
| 39166 | /* 107963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39167 | /* 107967 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39168 | /* 107971 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39169 | /* 107975 */ // (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMULhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 39170 | /* 107975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhq), |
| 39171 | /* 107978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39172 | /* 107980 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39173 | /* 107982 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39174 | /* 107984 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39175 | /* 107987 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39176 | /* 107993 */ GIR_RootConstrainSelectedInstOperands, |
| 39177 | /* 107994 */ // GIR_Coverage, 966, |
| 39178 | /* 107994 */ GIR_EraseRootFromParent_Done, |
| 39179 | /* 107995 */ // Label 3287: @107995 |
| 39180 | /* 107995 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3288*/ GIMT_Encode4(108055), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4413 // |
| 39181 | /* 108002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39182 | /* 108006 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39183 | /* 108010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39184 | /* 108014 */ // (fmul:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 39185 | /* 108014 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39186 | /* 108017 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39187 | /* 108021 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39188 | /* 108026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16), |
| 39189 | /* 108029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39190 | /* 108031 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39191 | /* 108033 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39192 | /* 108035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39193 | /* 108038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39194 | /* 108044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39195 | /* 108050 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39196 | /* 108053 */ GIR_RootConstrainSelectedInstOperands, |
| 39197 | /* 108054 */ // GIR_Coverage, 4413, |
| 39198 | /* 108054 */ GIR_EraseRootFromParent_Done, |
| 39199 | /* 108055 */ // Label 3288: @108055 |
| 39200 | /* 108055 */ GIM_Reject, |
| 39201 | /* 108056 */ // Label 3286: @108056 |
| 39202 | /* 108056 */ GIM_Reject, |
| 39203 | /* 108057 */ // Label 3269: @108057 |
| 39204 | /* 108057 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3289*/ GIMT_Encode4(108102), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 963 // |
| 39205 | /* 108064 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39206 | /* 108067 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39207 | /* 108070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39208 | /* 108074 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39209 | /* 108078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39210 | /* 108082 */ // (fmul:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMULfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 39211 | /* 108082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfd), |
| 39212 | /* 108085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39213 | /* 108087 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39214 | /* 108089 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39215 | /* 108091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39216 | /* 108094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39217 | /* 108100 */ GIR_RootConstrainSelectedInstOperands, |
| 39218 | /* 108101 */ // GIR_Coverage, 963, |
| 39219 | /* 108101 */ GIR_EraseRootFromParent_Done, |
| 39220 | /* 108102 */ // Label 3289: @108102 |
| 39221 | /* 108102 */ GIM_Reject, |
| 39222 | /* 108103 */ // Label 3270: @108103 |
| 39223 | /* 108103 */ GIM_Try, /*On fail goto*//*Label 3290*/ GIMT_Encode4(108214), |
| 39224 | /* 108108 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39225 | /* 108111 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39226 | /* 108114 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3291*/ GIMT_Encode4(108153), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 964 // |
| 39227 | /* 108121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39228 | /* 108125 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39229 | /* 108129 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39230 | /* 108133 */ // (fmul:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMULfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 39231 | /* 108133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfq), |
| 39232 | /* 108136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39233 | /* 108138 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39234 | /* 108140 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39235 | /* 108142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39236 | /* 108145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39237 | /* 108151 */ GIR_RootConstrainSelectedInstOperands, |
| 39238 | /* 108152 */ // GIR_Coverage, 964, |
| 39239 | /* 108152 */ GIR_EraseRootFromParent_Done, |
| 39240 | /* 108153 */ // Label 3291: @108153 |
| 39241 | /* 108153 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3292*/ GIMT_Encode4(108213), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4406 // |
| 39242 | /* 108160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39243 | /* 108164 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39244 | /* 108168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39245 | /* 108172 */ // (fmul:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 39246 | /* 108172 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 39247 | /* 108175 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 39248 | /* 108179 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 39249 | /* 108184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32), |
| 39250 | /* 108187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39251 | /* 108189 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 39252 | /* 108191 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 39253 | /* 108193 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39254 | /* 108196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39255 | /* 108202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39256 | /* 108208 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 39257 | /* 108211 */ GIR_RootConstrainSelectedInstOperands, |
| 39258 | /* 108212 */ // GIR_Coverage, 4406, |
| 39259 | /* 108212 */ GIR_EraseRootFromParent_Done, |
| 39260 | /* 108213 */ // Label 3292: @108213 |
| 39261 | /* 108213 */ GIM_Reject, |
| 39262 | /* 108214 */ // Label 3290: @108214 |
| 39263 | /* 108214 */ GIM_Reject, |
| 39264 | /* 108215 */ // Label 3271: @108215 |
| 39265 | /* 108215 */ GIM_Reject, |
| 39266 | /* 108216 */ // Label 43: @108216 |
| 39267 | /* 108216 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3300*/ GIMT_Encode4(110278), |
| 39268 | /* 108227 */ /*GILLT_s16*//*Label 3293*/ GIMT_Encode4(108279), |
| 39269 | /* 108231 */ /*GILLT_s32*//*Label 3294*/ GIMT_Encode4(108660), |
| 39270 | /* 108235 */ /*GILLT_s64*//*Label 3295*/ GIMT_Encode4(109041), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 39271 | /* 108263 */ /*GILLT_v4s16*//*Label 3296*/ GIMT_Encode4(109422), |
| 39272 | /* 108267 */ /*GILLT_v8s16*//*Label 3297*/ GIMT_Encode4(109477), |
| 39273 | /* 108271 */ /*GILLT_v2s32*//*Label 3298*/ GIMT_Encode4(109727), |
| 39274 | /* 108275 */ /*GILLT_v4s32*//*Label 3299*/ GIMT_Encode4(109906), |
| 39275 | /* 108279 */ // Label 3293: @108279 |
| 39276 | /* 108279 */ GIM_Try, /*On fail goto*//*Label 3301*/ GIMT_Encode4(108659), |
| 39277 | /* 108284 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 39278 | /* 108287 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 39279 | /* 108290 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 39280 | /* 108293 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39281 | /* 108297 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3302*/ GIMT_Encode4(108370), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2772 // |
| 39282 | /* 108304 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39283 | /* 108308 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39284 | /* 108312 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39285 | /* 108316 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39286 | /* 108321 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39287 | /* 108325 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39288 | /* 108329 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39289 | /* 108333 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 39290 | /* 108337 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39291 | /* 108342 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39292 | /* 108344 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39293 | /* 108344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 39294 | /* 108347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39295 | /* 108349 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 39296 | /* 108353 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39297 | /* 108357 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39298 | /* 108359 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39299 | /* 108362 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39300 | /* 108368 */ GIR_RootConstrainSelectedInstOperands, |
| 39301 | /* 108369 */ // GIR_Coverage, 2772, |
| 39302 | /* 108369 */ GIR_EraseRootFromParent_Done, |
| 39303 | /* 108370 */ // Label 3302: @108370 |
| 39304 | /* 108370 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3303*/ GIMT_Encode4(108443), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6328 // |
| 39305 | /* 108377 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39306 | /* 108381 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39307 | /* 108385 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39308 | /* 108389 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39309 | /* 108393 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39310 | /* 108398 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39311 | /* 108402 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39312 | /* 108406 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 39313 | /* 108410 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39314 | /* 108415 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39315 | /* 108417 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39316 | /* 108417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 39317 | /* 108420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39318 | /* 108422 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 39319 | /* 108426 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39320 | /* 108430 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39321 | /* 108432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39322 | /* 108435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39323 | /* 108441 */ GIR_RootConstrainSelectedInstOperands, |
| 39324 | /* 108442 */ // GIR_Coverage, 6328, |
| 39325 | /* 108442 */ GIR_EraseRootFromParent_Done, |
| 39326 | /* 108443 */ // Label 3303: @108443 |
| 39327 | /* 108443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3304*/ GIMT_Encode4(108501), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2752 // |
| 39328 | /* 108450 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39329 | /* 108454 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39330 | /* 108458 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39331 | /* 108462 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39332 | /* 108467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39333 | /* 108471 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39334 | /* 108475 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39335 | /* 108477 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39336 | /* 108477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 39337 | /* 108480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39338 | /* 108482 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39339 | /* 108484 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39340 | /* 108488 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39341 | /* 108490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39342 | /* 108493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39343 | /* 108499 */ GIR_RootConstrainSelectedInstOperands, |
| 39344 | /* 108500 */ // GIR_Coverage, 2752, |
| 39345 | /* 108500 */ GIR_EraseRootFromParent_Done, |
| 39346 | /* 108501 */ // Label 3304: @108501 |
| 39347 | /* 108501 */ GIM_Try, /*On fail goto*//*Label 3305*/ GIMT_Encode4(108658), |
| 39348 | /* 108506 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39349 | /* 108510 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3306*/ GIMT_Encode4(108564), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6322 // |
| 39350 | /* 108517 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39351 | /* 108521 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39352 | /* 108525 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39353 | /* 108529 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39354 | /* 108534 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39355 | /* 108538 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39356 | /* 108540 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39357 | /* 108540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 39358 | /* 108543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39359 | /* 108545 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39360 | /* 108547 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39361 | /* 108551 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39362 | /* 108553 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39363 | /* 108556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39364 | /* 108562 */ GIR_RootConstrainSelectedInstOperands, |
| 39365 | /* 108563 */ // GIR_Coverage, 6322, |
| 39366 | /* 108563 */ GIR_EraseRootFromParent_Done, |
| 39367 | /* 108564 */ // Label 3306: @108564 |
| 39368 | /* 108564 */ GIM_Try, /*On fail goto*//*Label 3307*/ GIMT_Encode4(108657), |
| 39369 | /* 108569 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39370 | /* 108573 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3308*/ GIMT_Encode4(108623), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2786 // |
| 39371 | /* 108580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39372 | /* 108584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39373 | /* 108588 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 39374 | /* 108592 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39375 | /* 108597 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39376 | /* 108599 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39377 | /* 108599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 39378 | /* 108602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39379 | /* 108604 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 39380 | /* 108608 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39381 | /* 108610 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39382 | /* 108612 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39383 | /* 108615 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39384 | /* 108621 */ GIR_RootConstrainSelectedInstOperands, |
| 39385 | /* 108622 */ // GIR_Coverage, 2786, |
| 39386 | /* 108622 */ GIR_EraseRootFromParent_Done, |
| 39387 | /* 108623 */ // Label 3308: @108623 |
| 39388 | /* 108623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3309*/ GIMT_Encode4(108656), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2734 // |
| 39389 | /* 108630 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39390 | /* 108634 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39391 | /* 108634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH), |
| 39392 | /* 108637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39393 | /* 108639 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39394 | /* 108641 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39395 | /* 108643 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39396 | /* 108645 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39397 | /* 108648 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39398 | /* 108654 */ GIR_RootConstrainSelectedInstOperands, |
| 39399 | /* 108655 */ // GIR_Coverage, 2734, |
| 39400 | /* 108655 */ GIR_EraseRootFromParent_Done, |
| 39401 | /* 108656 */ // Label 3309: @108656 |
| 39402 | /* 108656 */ GIM_Reject, |
| 39403 | /* 108657 */ // Label 3307: @108657 |
| 39404 | /* 108657 */ GIM_Reject, |
| 39405 | /* 108658 */ // Label 3305: @108658 |
| 39406 | /* 108658 */ GIM_Reject, |
| 39407 | /* 108659 */ // Label 3301: @108659 |
| 39408 | /* 108659 */ GIM_Reject, |
| 39409 | /* 108660 */ // Label 3294: @108660 |
| 39410 | /* 108660 */ GIM_Try, /*On fail goto*//*Label 3310*/ GIMT_Encode4(109040), |
| 39411 | /* 108665 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 39412 | /* 108668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 39413 | /* 108671 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 39414 | /* 108674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39415 | /* 108678 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3311*/ GIMT_Encode4(108751), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2770 // |
| 39416 | /* 108685 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39417 | /* 108689 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39418 | /* 108693 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39419 | /* 108697 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39420 | /* 108702 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39421 | /* 108706 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39422 | /* 108710 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39423 | /* 108714 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 39424 | /* 108718 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39425 | /* 108723 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39426 | /* 108725 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39427 | /* 108725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 39428 | /* 108728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39429 | /* 108730 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 39430 | /* 108734 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39431 | /* 108738 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39432 | /* 108740 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39433 | /* 108743 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39434 | /* 108749 */ GIR_RootConstrainSelectedInstOperands, |
| 39435 | /* 108750 */ // GIR_Coverage, 2770, |
| 39436 | /* 108750 */ GIR_EraseRootFromParent_Done, |
| 39437 | /* 108751 */ // Label 3311: @108751 |
| 39438 | /* 108751 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3312*/ GIMT_Encode4(108824), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6326 // |
| 39439 | /* 108758 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39440 | /* 108762 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39441 | /* 108766 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39442 | /* 108770 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39443 | /* 108774 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39444 | /* 108779 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39445 | /* 108783 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39446 | /* 108787 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 39447 | /* 108791 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39448 | /* 108796 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39449 | /* 108798 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39450 | /* 108798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 39451 | /* 108801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39452 | /* 108803 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 39453 | /* 108807 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39454 | /* 108811 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39455 | /* 108813 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39456 | /* 108816 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39457 | /* 108822 */ GIR_RootConstrainSelectedInstOperands, |
| 39458 | /* 108823 */ // GIR_Coverage, 6326, |
| 39459 | /* 108823 */ GIR_EraseRootFromParent_Done, |
| 39460 | /* 108824 */ // Label 3312: @108824 |
| 39461 | /* 108824 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3313*/ GIMT_Encode4(108882), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2750 // |
| 39462 | /* 108831 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39463 | /* 108835 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39464 | /* 108839 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39465 | /* 108843 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39466 | /* 108848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39467 | /* 108852 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39468 | /* 108856 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39469 | /* 108858 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39470 | /* 108858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 39471 | /* 108861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39472 | /* 108863 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39473 | /* 108865 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39474 | /* 108869 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39475 | /* 108871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39476 | /* 108874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39477 | /* 108880 */ GIR_RootConstrainSelectedInstOperands, |
| 39478 | /* 108881 */ // GIR_Coverage, 2750, |
| 39479 | /* 108881 */ GIR_EraseRootFromParent_Done, |
| 39480 | /* 108882 */ // Label 3313: @108882 |
| 39481 | /* 108882 */ GIM_Try, /*On fail goto*//*Label 3314*/ GIMT_Encode4(109039), |
| 39482 | /* 108887 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39483 | /* 108891 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3315*/ GIMT_Encode4(108945), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6320 // |
| 39484 | /* 108898 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39485 | /* 108902 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39486 | /* 108906 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39487 | /* 108910 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39488 | /* 108915 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39489 | /* 108919 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39490 | /* 108921 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39491 | /* 108921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 39492 | /* 108924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39493 | /* 108926 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39494 | /* 108928 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 39495 | /* 108932 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 39496 | /* 108934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39497 | /* 108937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39498 | /* 108943 */ GIR_RootConstrainSelectedInstOperands, |
| 39499 | /* 108944 */ // GIR_Coverage, 6320, |
| 39500 | /* 108944 */ GIR_EraseRootFromParent_Done, |
| 39501 | /* 108945 */ // Label 3315: @108945 |
| 39502 | /* 108945 */ GIM_Try, /*On fail goto*//*Label 3316*/ GIMT_Encode4(109038), |
| 39503 | /* 108950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39504 | /* 108954 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3317*/ GIMT_Encode4(109004), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2784 // |
| 39505 | /* 108961 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39506 | /* 108965 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39507 | /* 108969 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 39508 | /* 108973 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39509 | /* 108978 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39510 | /* 108980 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39511 | /* 108980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 39512 | /* 108983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39513 | /* 108985 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 39514 | /* 108989 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39515 | /* 108991 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39516 | /* 108993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39517 | /* 108996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39518 | /* 109002 */ GIR_RootConstrainSelectedInstOperands, |
| 39519 | /* 109003 */ // GIR_Coverage, 2784, |
| 39520 | /* 109003 */ GIR_EraseRootFromParent_Done, |
| 39521 | /* 109004 */ // Label 3317: @109004 |
| 39522 | /* 109004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3318*/ GIMT_Encode4(109037), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2732 // |
| 39523 | /* 109011 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 39524 | /* 109015 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 39525 | /* 109015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS), |
| 39526 | /* 109018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 39527 | /* 109020 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 39528 | /* 109022 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 39529 | /* 109024 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 39530 | /* 109026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39531 | /* 109029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39532 | /* 109035 */ GIR_RootConstrainSelectedInstOperands, |
| 39533 | /* 109036 */ // GIR_Coverage, 2732, |
| 39534 | /* 109036 */ GIR_EraseRootFromParent_Done, |
| 39535 | /* 109037 */ // Label 3318: @109037 |
| 39536 | /* 109037 */ GIM_Reject, |
| 39537 | /* 109038 */ // Label 3316: @109038 |
| 39538 | /* 109038 */ GIM_Reject, |
| 39539 | /* 109039 */ // Label 3314: @109039 |
| 39540 | /* 109039 */ GIM_Reject, |
| 39541 | /* 109040 */ // Label 3310: @109040 |
| 39542 | /* 109040 */ GIM_Reject, |
| 39543 | /* 109041 */ // Label 3295: @109041 |
| 39544 | /* 109041 */ GIM_Try, /*On fail goto*//*Label 3319*/ GIMT_Encode4(109421), |
| 39545 | /* 109046 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 39546 | /* 109049 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 39547 | /* 109052 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 39548 | /* 109055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39549 | /* 109059 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3320*/ GIMT_Encode4(109132), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2768 // |
| 39550 | /* 109066 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39551 | /* 109070 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39552 | /* 109074 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39553 | /* 109078 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39554 | /* 109083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39555 | /* 109087 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39556 | /* 109091 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39557 | /* 109095 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 39558 | /* 109099 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39559 | /* 109104 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39560 | /* 109106 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39561 | /* 109106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 39562 | /* 109109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39563 | /* 109111 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 39564 | /* 109115 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39565 | /* 109119 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39566 | /* 109121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39567 | /* 109124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39568 | /* 109130 */ GIR_RootConstrainSelectedInstOperands, |
| 39569 | /* 109131 */ // GIR_Coverage, 2768, |
| 39570 | /* 109131 */ GIR_EraseRootFromParent_Done, |
| 39571 | /* 109132 */ // Label 3320: @109132 |
| 39572 | /* 109132 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3321*/ GIMT_Encode4(109205), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6324 // |
| 39573 | /* 109139 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39574 | /* 109143 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39575 | /* 109147 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39576 | /* 109151 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39577 | /* 109155 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39578 | /* 109160 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 39579 | /* 109164 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39580 | /* 109168 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 39581 | /* 109172 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39582 | /* 109177 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 39583 | /* 109179 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39584 | /* 109179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 39585 | /* 109182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39586 | /* 109184 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 39587 | /* 109188 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39588 | /* 109192 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 39589 | /* 109194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39590 | /* 109197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39591 | /* 109203 */ GIR_RootConstrainSelectedInstOperands, |
| 39592 | /* 109204 */ // GIR_Coverage, 6324, |
| 39593 | /* 109204 */ GIR_EraseRootFromParent_Done, |
| 39594 | /* 109205 */ // Label 3321: @109205 |
| 39595 | /* 109205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3322*/ GIMT_Encode4(109263), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2748 // |
| 39596 | /* 109212 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39597 | /* 109216 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39598 | /* 109220 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39599 | /* 109224 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39600 | /* 109229 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39601 | /* 109233 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39602 | /* 109237 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39603 | /* 109239 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39604 | /* 109239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 39605 | /* 109242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39606 | /* 109244 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 39607 | /* 109246 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39608 | /* 109250 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39609 | /* 109252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39610 | /* 109255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39611 | /* 109261 */ GIR_RootConstrainSelectedInstOperands, |
| 39612 | /* 109262 */ // GIR_Coverage, 2748, |
| 39613 | /* 109262 */ GIR_EraseRootFromParent_Done, |
| 39614 | /* 109263 */ // Label 3322: @109263 |
| 39615 | /* 109263 */ GIM_Try, /*On fail goto*//*Label 3323*/ GIMT_Encode4(109420), |
| 39616 | /* 109268 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39617 | /* 109272 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3324*/ GIMT_Encode4(109326), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6318 // |
| 39618 | /* 109279 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39619 | /* 109283 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39620 | /* 109287 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39621 | /* 109291 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39622 | /* 109296 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39623 | /* 109300 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39624 | /* 109302 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39625 | /* 109302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 39626 | /* 109305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39627 | /* 109307 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 39628 | /* 109309 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 39629 | /* 109313 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 39630 | /* 109315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39631 | /* 109318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39632 | /* 109324 */ GIR_RootConstrainSelectedInstOperands, |
| 39633 | /* 109325 */ // GIR_Coverage, 6318, |
| 39634 | /* 109325 */ GIR_EraseRootFromParent_Done, |
| 39635 | /* 109326 */ // Label 3324: @109326 |
| 39636 | /* 109326 */ GIM_Try, /*On fail goto*//*Label 3325*/ GIMT_Encode4(109419), |
| 39637 | /* 109331 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39638 | /* 109335 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3326*/ GIMT_Encode4(109385), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2782 // |
| 39639 | /* 109342 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 39640 | /* 109346 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39641 | /* 109350 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 39642 | /* 109354 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39643 | /* 109359 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39644 | /* 109361 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39645 | /* 109361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 39646 | /* 109364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39647 | /* 109366 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin |
| 39648 | /* 109370 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 39649 | /* 109372 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39650 | /* 109374 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39651 | /* 109377 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39652 | /* 109383 */ GIR_RootConstrainSelectedInstOperands, |
| 39653 | /* 109384 */ // GIR_Coverage, 2782, |
| 39654 | /* 109384 */ GIR_EraseRootFromParent_Done, |
| 39655 | /* 109385 */ // Label 3326: @109385 |
| 39656 | /* 109385 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3327*/ GIMT_Encode4(109418), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2730 // |
| 39657 | /* 109392 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39658 | /* 109396 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 39659 | /* 109396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD), |
| 39660 | /* 109399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 39661 | /* 109401 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 39662 | /* 109403 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 39663 | /* 109405 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 39664 | /* 109407 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39665 | /* 109410 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39666 | /* 109416 */ GIR_RootConstrainSelectedInstOperands, |
| 39667 | /* 109417 */ // GIR_Coverage, 2730, |
| 39668 | /* 109417 */ GIR_EraseRootFromParent_Done, |
| 39669 | /* 109418 */ // Label 3327: @109418 |
| 39670 | /* 109418 */ GIM_Reject, |
| 39671 | /* 109419 */ // Label 3325: @109419 |
| 39672 | /* 109419 */ GIM_Reject, |
| 39673 | /* 109420 */ // Label 3323: @109420 |
| 39674 | /* 109420 */ GIM_Reject, |
| 39675 | /* 109421 */ // Label 3319: @109421 |
| 39676 | /* 109421 */ GIM_Reject, |
| 39677 | /* 109422 */ // Label 3296: @109422 |
| 39678 | /* 109422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3328*/ GIMT_Encode4(109476), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 2883 // |
| 39679 | /* 109429 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 39680 | /* 109432 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 39681 | /* 109435 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 39682 | /* 109438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39683 | /* 109442 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39684 | /* 109446 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39685 | /* 109450 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39686 | /* 109454 */ // (fma:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm, DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 39687 | /* 109454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd), |
| 39688 | /* 109457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39689 | /* 109459 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39690 | /* 109461 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39691 | /* 109463 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39692 | /* 109465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39693 | /* 109468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39694 | /* 109474 */ GIR_RootConstrainSelectedInstOperands, |
| 39695 | /* 109475 */ // GIR_Coverage, 2883, |
| 39696 | /* 109475 */ GIR_EraseRootFromParent_Done, |
| 39697 | /* 109476 */ // Label 3328: @109476 |
| 39698 | /* 109476 */ GIM_Reject, |
| 39699 | /* 109477 */ // Label 3297: @109477 |
| 39700 | /* 109477 */ GIM_Try, /*On fail goto*//*Label 3329*/ GIMT_Encode4(109726), |
| 39701 | /* 109482 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39702 | /* 109485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 39703 | /* 109488 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 39704 | /* 109491 */ GIM_Try, /*On fail goto*//*Label 3330*/ GIMT_Encode4(109629), |
| 39705 | /* 109496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39706 | /* 109500 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3331*/ GIMT_Encode4(109564), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4440 // |
| 39707 | /* 109507 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39708 | /* 109511 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39709 | /* 109515 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39710 | /* 109519 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39711 | /* 109524 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39712 | /* 109528 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39713 | /* 109532 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39714 | /* 109534 */ // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 39715 | /* 109534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16), |
| 39716 | /* 109537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39717 | /* 109539 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 39718 | /* 109541 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 39719 | /* 109545 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 39720 | /* 109547 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39721 | /* 109550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39722 | /* 109556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39723 | /* 109562 */ GIR_RootConstrainSelectedInstOperands, |
| 39724 | /* 109563 */ // GIR_Coverage, 4440, |
| 39725 | /* 109563 */ GIR_EraseRootFromParent_Done, |
| 39726 | /* 109564 */ // Label 3331: @109564 |
| 39727 | /* 109564 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3332*/ GIMT_Encode4(109628), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 6664 // |
| 39728 | /* 109571 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39729 | /* 109575 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39730 | /* 109579 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39731 | /* 109583 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 39732 | /* 109587 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39733 | /* 109592 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39734 | /* 109596 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39735 | /* 109598 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m2, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 39736 | /* 109598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16), |
| 39737 | /* 109601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39738 | /* 109603 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 39739 | /* 109605 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 39740 | /* 109609 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2 |
| 39741 | /* 109611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39742 | /* 109614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39743 | /* 109620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39744 | /* 109626 */ GIR_RootConstrainSelectedInstOperands, |
| 39745 | /* 109627 */ // GIR_Coverage, 6664, |
| 39746 | /* 109627 */ GIR_EraseRootFromParent_Done, |
| 39747 | /* 109628 */ // Label 3332: @109628 |
| 39748 | /* 109628 */ GIM_Reject, |
| 39749 | /* 109629 */ // Label 3330: @109629 |
| 39750 | /* 109629 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3333*/ GIMT_Encode4(109674), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 2884 // |
| 39751 | /* 109636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39752 | /* 109640 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39753 | /* 109644 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39754 | /* 109648 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39755 | /* 109652 */ // (fma:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm, QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 39756 | /* 109652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq), |
| 39757 | /* 109655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39758 | /* 109657 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39759 | /* 109659 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39760 | /* 109661 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39761 | /* 109663 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39762 | /* 109666 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39763 | /* 109672 */ GIR_RootConstrainSelectedInstOperands, |
| 39764 | /* 109673 */ // GIR_Coverage, 2884, |
| 39765 | /* 109673 */ GIR_EraseRootFromParent_Done, |
| 39766 | /* 109674 */ // Label 3333: @109674 |
| 39767 | /* 109674 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3334*/ GIMT_Encode4(109725), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4436 // |
| 39768 | /* 109681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39769 | /* 109685 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39770 | /* 109689 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39771 | /* 109693 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39772 | /* 109697 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2) |
| 39773 | /* 109697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16), |
| 39774 | /* 109700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39775 | /* 109702 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 39776 | /* 109704 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1 |
| 39777 | /* 109706 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 39778 | /* 109708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39779 | /* 109711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39780 | /* 109717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39781 | /* 109723 */ GIR_RootConstrainSelectedInstOperands, |
| 39782 | /* 109724 */ // GIR_Coverage, 4436, |
| 39783 | /* 109724 */ GIR_EraseRootFromParent_Done, |
| 39784 | /* 109725 */ // Label 3334: @109725 |
| 39785 | /* 109725 */ GIM_Reject, |
| 39786 | /* 109726 */ // Label 3329: @109726 |
| 39787 | /* 109726 */ GIM_Reject, |
| 39788 | /* 109727 */ // Label 3298: @109727 |
| 39789 | /* 109727 */ GIM_Try, /*On fail goto*//*Label 3335*/ GIMT_Encode4(109905), |
| 39790 | /* 109732 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39791 | /* 109735 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 39792 | /* 109738 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 39793 | /* 109741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39794 | /* 109745 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3336*/ GIMT_Encode4(109803), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2887 // |
| 39795 | /* 109752 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39796 | /* 109756 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39797 | /* 109760 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39798 | /* 109764 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39799 | /* 109769 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39800 | /* 109773 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39801 | /* 109777 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39802 | /* 109779 */ // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 39803 | /* 109779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd), |
| 39804 | /* 109782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39805 | /* 109784 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39806 | /* 109786 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 39807 | /* 109790 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39808 | /* 109792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39809 | /* 109795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39810 | /* 109801 */ GIR_RootConstrainSelectedInstOperands, |
| 39811 | /* 109802 */ // GIR_Coverage, 2887, |
| 39812 | /* 109802 */ GIR_EraseRootFromParent_Done, |
| 39813 | /* 109803 */ // Label 3336: @109803 |
| 39814 | /* 109803 */ GIM_Try, /*On fail goto*//*Label 3337*/ GIMT_Encode4(109904), |
| 39815 | /* 109808 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39816 | /* 109812 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3338*/ GIMT_Encode4(109866), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 6381 // |
| 39817 | /* 109819 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39818 | /* 109823 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39819 | /* 109827 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 39820 | /* 109831 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39821 | /* 109836 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39822 | /* 109840 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39823 | /* 109842 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm, (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 39824 | /* 109842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd), |
| 39825 | /* 109845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39826 | /* 109847 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39827 | /* 109849 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 39828 | /* 109853 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 39829 | /* 109855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39830 | /* 109858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39831 | /* 109864 */ GIR_RootConstrainSelectedInstOperands, |
| 39832 | /* 109865 */ // GIR_Coverage, 6381, |
| 39833 | /* 109865 */ GIR_EraseRootFromParent_Done, |
| 39834 | /* 109866 */ // Label 3338: @109866 |
| 39835 | /* 109866 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3339*/ GIMT_Encode4(109903), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2885 // |
| 39836 | /* 109873 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39837 | /* 109877 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 39838 | /* 109881 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMAfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 39839 | /* 109881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfd), |
| 39840 | /* 109884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39841 | /* 109886 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39842 | /* 109888 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39843 | /* 109890 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39844 | /* 109892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39845 | /* 109895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39846 | /* 109901 */ GIR_RootConstrainSelectedInstOperands, |
| 39847 | /* 109902 */ // GIR_Coverage, 2885, |
| 39848 | /* 109902 */ GIR_EraseRootFromParent_Done, |
| 39849 | /* 109903 */ // Label 3339: @109903 |
| 39850 | /* 109903 */ GIM_Reject, |
| 39851 | /* 109904 */ // Label 3337: @109904 |
| 39852 | /* 109904 */ GIM_Reject, |
| 39853 | /* 109905 */ // Label 3335: @109905 |
| 39854 | /* 109905 */ GIM_Reject, |
| 39855 | /* 109906 */ // Label 3299: @109906 |
| 39856 | /* 109906 */ GIM_Try, /*On fail goto*//*Label 3340*/ GIMT_Encode4(110277), |
| 39857 | /* 109911 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39858 | /* 109914 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 39859 | /* 109917 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 39860 | /* 109920 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3341*/ GIMT_Encode4(109982), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2888 // |
| 39861 | /* 109927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39862 | /* 109931 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39863 | /* 109935 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39864 | /* 109939 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39865 | /* 109943 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39866 | /* 109948 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39867 | /* 109952 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39868 | /* 109956 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39869 | /* 109958 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 39870 | /* 109958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq), |
| 39871 | /* 109961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39872 | /* 109963 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39873 | /* 109965 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 39874 | /* 109969 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39875 | /* 109971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39876 | /* 109974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39877 | /* 109980 */ GIR_RootConstrainSelectedInstOperands, |
| 39878 | /* 109981 */ // GIR_Coverage, 2888, |
| 39879 | /* 109981 */ GIR_EraseRootFromParent_Done, |
| 39880 | /* 109982 */ // Label 3341: @109982 |
| 39881 | /* 109982 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3342*/ GIMT_Encode4(110050), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4426 // |
| 39882 | /* 109989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39883 | /* 109993 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 39884 | /* 109997 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39885 | /* 110001 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39886 | /* 110005 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39887 | /* 110010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39888 | /* 110014 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39889 | /* 110018 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39890 | /* 110020 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 39891 | /* 110020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32), |
| 39892 | /* 110023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39893 | /* 110025 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 39894 | /* 110027 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 39895 | /* 110031 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 39896 | /* 110033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39897 | /* 110036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39898 | /* 110042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39899 | /* 110048 */ GIR_RootConstrainSelectedInstOperands, |
| 39900 | /* 110049 */ // GIR_Coverage, 4426, |
| 39901 | /* 110049 */ GIR_EraseRootFromParent_Done, |
| 39902 | /* 110050 */ // Label 3342: @110050 |
| 39903 | /* 110050 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3343*/ GIMT_Encode4(110112), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 6382 // |
| 39904 | /* 110057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39905 | /* 110061 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39906 | /* 110065 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39907 | /* 110069 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39908 | /* 110073 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39909 | /* 110077 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39910 | /* 110082 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39911 | /* 110086 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39912 | /* 110088 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm, (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 39913 | /* 110088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq), |
| 39914 | /* 110091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39915 | /* 110093 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39916 | /* 110095 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn |
| 39917 | /* 110099 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 39918 | /* 110101 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39919 | /* 110104 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39920 | /* 110110 */ GIR_RootConstrainSelectedInstOperands, |
| 39921 | /* 110111 */ // GIR_Coverage, 6382, |
| 39922 | /* 110111 */ GIR_EraseRootFromParent_Done, |
| 39923 | /* 110112 */ // Label 3343: @110112 |
| 39924 | /* 110112 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3344*/ GIMT_Encode4(110180), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 6662 // |
| 39925 | /* 110119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39926 | /* 110123 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39927 | /* 110127 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 39928 | /* 110131 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 39929 | /* 110135 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 39930 | /* 110139 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39931 | /* 110144 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39932 | /* 110148 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 39933 | /* 110150 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m2, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 39934 | /* 110150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32), |
| 39935 | /* 110153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39936 | /* 110155 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 39937 | /* 110157 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1 |
| 39938 | /* 110161 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2 |
| 39939 | /* 110163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39940 | /* 110166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39941 | /* 110172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39942 | /* 110178 */ GIR_RootConstrainSelectedInstOperands, |
| 39943 | /* 110179 */ // GIR_Coverage, 6662, |
| 39944 | /* 110179 */ GIR_EraseRootFromParent_Done, |
| 39945 | /* 110180 */ // Label 3344: @110180 |
| 39946 | /* 110180 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3345*/ GIMT_Encode4(110225), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2886 // |
| 39947 | /* 110187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39948 | /* 110191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39949 | /* 110195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39950 | /* 110199 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 39951 | /* 110203 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMAfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 39952 | /* 110203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfq), |
| 39953 | /* 110206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 39954 | /* 110208 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 39955 | /* 110210 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 39956 | /* 110212 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 39957 | /* 110214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 39958 | /* 110217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39959 | /* 110223 */ GIR_RootConstrainSelectedInstOperands, |
| 39960 | /* 110224 */ // GIR_Coverage, 2886, |
| 39961 | /* 110224 */ GIR_EraseRootFromParent_Done, |
| 39962 | /* 110225 */ // Label 3345: @110225 |
| 39963 | /* 110225 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3346*/ GIMT_Encode4(110276), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4432 // |
| 39964 | /* 110232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39965 | /* 110236 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39966 | /* 110240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39967 | /* 110244 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 39968 | /* 110248 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2) |
| 39969 | /* 110248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32), |
| 39970 | /* 110251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 39971 | /* 110253 */ GIR_RootToRootCopy, /*OpIdx*/3, // add |
| 39972 | /* 110255 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1 |
| 39973 | /* 110257 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2 |
| 39974 | /* 110259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39975 | /* 110262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39976 | /* 110268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 39977 | /* 110274 */ GIR_RootConstrainSelectedInstOperands, |
| 39978 | /* 110275 */ // GIR_Coverage, 4432, |
| 39979 | /* 110275 */ GIR_EraseRootFromParent_Done, |
| 39980 | /* 110276 */ // Label 3346: @110276 |
| 39981 | /* 110276 */ GIM_Reject, |
| 39982 | /* 110277 */ // Label 3340: @110277 |
| 39983 | /* 110277 */ GIM_Reject, |
| 39984 | /* 110278 */ // Label 3300: @110278 |
| 39985 | /* 110278 */ GIM_Reject, |
| 39986 | /* 110279 */ // Label 44: @110279 |
| 39987 | /* 110279 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3350*/ GIMT_Encode4(110440), |
| 39988 | /* 110290 */ /*GILLT_s16*//*Label 3347*/ GIMT_Encode4(110302), |
| 39989 | /* 110294 */ /*GILLT_s32*//*Label 3348*/ GIMT_Encode4(110348), |
| 39990 | /* 110298 */ /*GILLT_s64*//*Label 3349*/ GIMT_Encode4(110394), |
| 39991 | /* 110302 */ // Label 3347: @110302 |
| 39992 | /* 110302 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3351*/ GIMT_Encode4(110347), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 633 // |
| 39993 | /* 110309 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 39994 | /* 110312 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 39995 | /* 110315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39996 | /* 110319 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39997 | /* 110323 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 39998 | /* 110327 */ // (fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 39999 | /* 110327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH), |
| 40000 | /* 110330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40001 | /* 110332 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 40002 | /* 110334 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 40003 | /* 110336 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40004 | /* 110339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40005 | /* 110345 */ GIR_RootConstrainSelectedInstOperands, |
| 40006 | /* 110346 */ // GIR_Coverage, 633, |
| 40007 | /* 110346 */ GIR_EraseRootFromParent_Done, |
| 40008 | /* 110347 */ // Label 3351: @110347 |
| 40009 | /* 110347 */ GIM_Reject, |
| 40010 | /* 110348 */ // Label 3348: @110348 |
| 40011 | /* 110348 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3352*/ GIMT_Encode4(110393), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 631 // |
| 40012 | /* 110355 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40013 | /* 110358 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 40014 | /* 110361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40015 | /* 110365 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40016 | /* 110369 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40017 | /* 110373 */ // (fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40018 | /* 110373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS), |
| 40019 | /* 110376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40020 | /* 110378 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 40021 | /* 110380 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 40022 | /* 110382 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40023 | /* 110385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40024 | /* 110391 */ GIR_RootConstrainSelectedInstOperands, |
| 40025 | /* 110392 */ // GIR_Coverage, 631, |
| 40026 | /* 110392 */ GIR_EraseRootFromParent_Done, |
| 40027 | /* 110393 */ // Label 3352: @110393 |
| 40028 | /* 110393 */ GIM_Reject, |
| 40029 | /* 110394 */ // Label 3349: @110394 |
| 40030 | /* 110394 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3353*/ GIMT_Encode4(110439), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 629 // |
| 40031 | /* 110401 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40032 | /* 110404 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 40033 | /* 110407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40034 | /* 110411 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40035 | /* 110415 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40036 | /* 110419 */ // (fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40037 | /* 110419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD), |
| 40038 | /* 110422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40039 | /* 110424 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 40040 | /* 110426 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 40041 | /* 110428 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40042 | /* 110431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40043 | /* 110437 */ GIR_RootConstrainSelectedInstOperands, |
| 40044 | /* 110438 */ // GIR_Coverage, 629, |
| 40045 | /* 110438 */ GIR_EraseRootFromParent_Done, |
| 40046 | /* 110439 */ // Label 3353: @110439 |
| 40047 | /* 110439 */ GIM_Reject, |
| 40048 | /* 110440 */ // Label 3350: @110440 |
| 40049 | /* 110440 */ GIM_Reject, |
| 40050 | /* 110441 */ // Label 45: @110441 |
| 40051 | /* 110441 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3361*/ GIMT_Encode4(112848), |
| 40052 | /* 110452 */ /*GILLT_s16*//*Label 3354*/ GIMT_Encode4(110504), |
| 40053 | /* 110456 */ /*GILLT_s32*//*Label 3355*/ GIMT_Encode4(111145), |
| 40054 | /* 110460 */ /*GILLT_s64*//*Label 3356*/ GIMT_Encode4(111939), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40055 | /* 110488 */ /*GILLT_v4s16*//*Label 3357*/ GIMT_Encode4(112580), |
| 40056 | /* 110492 */ /*GILLT_v8s16*//*Label 3358*/ GIMT_Encode4(112617), |
| 40057 | /* 110496 */ /*GILLT_v2s32*//*Label 3359*/ GIMT_Encode4(112714), |
| 40058 | /* 110500 */ /*GILLT_v4s32*//*Label 3360*/ GIMT_Encode4(112751), |
| 40059 | /* 110504 */ // Label 3354: @110504 |
| 40060 | /* 110504 */ GIM_Try, /*On fail goto*//*Label 3362*/ GIMT_Encode4(111144), |
| 40061 | /* 110509 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40062 | /* 110512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40063 | /* 110516 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3363*/ GIMT_Encode4(110600), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2792 // |
| 40064 | /* 110523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40065 | /* 110527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40066 | /* 110531 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40067 | /* 110535 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40068 | /* 110539 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 40069 | /* 110543 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 40070 | /* 110547 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40071 | /* 110551 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 40072 | /* 110555 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40073 | /* 110560 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40074 | /* 110565 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40075 | /* 110570 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40076 | /* 110572 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40077 | /* 110572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 40078 | /* 110575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40079 | /* 110577 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40080 | /* 110581 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40081 | /* 110585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40082 | /* 110589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40083 | /* 110592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40084 | /* 110598 */ GIR_RootConstrainSelectedInstOperands, |
| 40085 | /* 110599 */ // GIR_Coverage, 2792, |
| 40086 | /* 110599 */ GIR_EraseRootFromParent_Done, |
| 40087 | /* 110600 */ // Label 3363: @110600 |
| 40088 | /* 110600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3364*/ GIMT_Encode4(110684), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6334 // |
| 40089 | /* 110607 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40090 | /* 110611 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40091 | /* 110615 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40092 | /* 110619 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40093 | /* 110623 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 40094 | /* 110627 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40095 | /* 110632 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40096 | /* 110636 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40097 | /* 110640 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 40098 | /* 110644 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40099 | /* 110649 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40100 | /* 110654 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40101 | /* 110656 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40102 | /* 110656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 40103 | /* 110659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40104 | /* 110661 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40105 | /* 110665 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40106 | /* 110669 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 40107 | /* 110673 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40108 | /* 110676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40109 | /* 110682 */ GIR_RootConstrainSelectedInstOperands, |
| 40110 | /* 110683 */ // GIR_Coverage, 6334, |
| 40111 | /* 110683 */ GIR_EraseRootFromParent_Done, |
| 40112 | /* 110684 */ // Label 3364: @110684 |
| 40113 | /* 110684 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3365*/ GIMT_Encode4(110768), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2791 // |
| 40114 | /* 110691 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40115 | /* 110695 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40116 | /* 110699 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40117 | /* 110703 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40118 | /* 110707 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 40119 | /* 110711 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 40120 | /* 110715 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40121 | /* 110719 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 40122 | /* 110723 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40123 | /* 110728 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40124 | /* 110733 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40125 | /* 110738 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40126 | /* 110740 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40127 | /* 110740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 40128 | /* 110743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40129 | /* 110745 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40130 | /* 110749 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40131 | /* 110753 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40132 | /* 110757 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40133 | /* 110760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40134 | /* 110766 */ GIR_RootConstrainSelectedInstOperands, |
| 40135 | /* 110767 */ // GIR_Coverage, 2791, |
| 40136 | /* 110767 */ GIR_EraseRootFromParent_Done, |
| 40137 | /* 110768 */ // Label 3365: @110768 |
| 40138 | /* 110768 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3366*/ GIMT_Encode4(110852), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6333 // |
| 40139 | /* 110775 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40140 | /* 110779 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40141 | /* 110783 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40142 | /* 110787 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40143 | /* 110791 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 40144 | /* 110795 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40145 | /* 110800 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40146 | /* 110804 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40147 | /* 110808 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 40148 | /* 110812 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40149 | /* 110817 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40150 | /* 110822 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40151 | /* 110824 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40152 | /* 110824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 40153 | /* 110827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40154 | /* 110829 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40155 | /* 110833 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40156 | /* 110837 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 40157 | /* 110841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40158 | /* 110844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40159 | /* 110850 */ GIR_RootConstrainSelectedInstOperands, |
| 40160 | /* 110851 */ // GIR_Coverage, 6333, |
| 40161 | /* 110851 */ GIR_EraseRootFromParent_Done, |
| 40162 | /* 110852 */ // Label 3366: @110852 |
| 40163 | /* 110852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3367*/ GIMT_Encode4(110924), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2766 // |
| 40164 | /* 110859 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40165 | /* 110863 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40166 | /* 110867 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40167 | /* 110871 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40168 | /* 110875 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 40169 | /* 110879 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40170 | /* 110884 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40171 | /* 110889 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40172 | /* 110894 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40173 | /* 110896 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40174 | /* 110896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 40175 | /* 110899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40176 | /* 110901 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40177 | /* 110905 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40178 | /* 110909 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40179 | /* 110913 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40180 | /* 110916 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40181 | /* 110922 */ GIR_RootConstrainSelectedInstOperands, |
| 40182 | /* 110923 */ // GIR_Coverage, 2766, |
| 40183 | /* 110923 */ GIR_EraseRootFromParent_Done, |
| 40184 | /* 110924 */ // Label 3367: @110924 |
| 40185 | /* 110924 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3368*/ GIMT_Encode4(110996), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2765 // |
| 40186 | /* 110931 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40187 | /* 110935 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40188 | /* 110939 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40189 | /* 110943 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40190 | /* 110947 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16, |
| 40191 | /* 110951 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40192 | /* 110956 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40193 | /* 110961 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40194 | /* 110966 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40195 | /* 110968 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40196 | /* 110968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 40197 | /* 110971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40198 | /* 110973 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40199 | /* 110977 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40200 | /* 110981 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40201 | /* 110985 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40202 | /* 110988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40203 | /* 110994 */ GIR_RootConstrainSelectedInstOperands, |
| 40204 | /* 110995 */ // GIR_Coverage, 2765, |
| 40205 | /* 110995 */ GIR_EraseRootFromParent_Done, |
| 40206 | /* 110996 */ // Label 3368: @110996 |
| 40207 | /* 110996 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3369*/ GIMT_Encode4(111055), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 645 // |
| 40208 | /* 111003 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40209 | /* 111007 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 40210 | /* 111011 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40211 | /* 111015 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40212 | /* 111019 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40213 | /* 111024 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40214 | /* 111029 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40215 | /* 111031 */ // (fneg:{ *:[f16] } (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40216 | /* 111031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH), |
| 40217 | /* 111034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40218 | /* 111036 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40219 | /* 111040 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40220 | /* 111044 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40221 | /* 111047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40222 | /* 111053 */ GIR_RootConstrainSelectedInstOperands, |
| 40223 | /* 111054 */ // GIR_Coverage, 645, |
| 40224 | /* 111054 */ GIR_EraseRootFromParent_Done, |
| 40225 | /* 111055 */ // Label 3369: @111055 |
| 40226 | /* 111055 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3370*/ GIMT_Encode4(111114), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 644 // |
| 40227 | /* 111062 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40228 | /* 111066 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL), |
| 40229 | /* 111070 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 40230 | /* 111074 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 40231 | /* 111078 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40232 | /* 111083 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40233 | /* 111088 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40234 | /* 111090 */ // (fneg:{ *:[f16] } (strict_fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 40235 | /* 111090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH), |
| 40236 | /* 111093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40237 | /* 111095 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40238 | /* 111099 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40239 | /* 111103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40240 | /* 111106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40241 | /* 111112 */ GIR_RootConstrainSelectedInstOperands, |
| 40242 | /* 111113 */ // GIR_Coverage, 644, |
| 40243 | /* 111113 */ GIR_EraseRootFromParent_Done, |
| 40244 | /* 111114 */ // Label 3370: @111114 |
| 40245 | /* 111114 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3371*/ GIMT_Encode4(111143), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 691 // |
| 40246 | /* 111121 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40247 | /* 111125 */ // (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VNEGH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 40248 | /* 111125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGH), |
| 40249 | /* 111128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40250 | /* 111130 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 40251 | /* 111132 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40252 | /* 111135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40253 | /* 111141 */ GIR_RootConstrainSelectedInstOperands, |
| 40254 | /* 111142 */ // GIR_Coverage, 691, |
| 40255 | /* 111142 */ GIR_EraseRootFromParent_Done, |
| 40256 | /* 111143 */ // Label 3371: @111143 |
| 40257 | /* 111143 */ GIM_Reject, |
| 40258 | /* 111144 */ // Label 3362: @111144 |
| 40259 | /* 111144 */ GIM_Reject, |
| 40260 | /* 111145 */ // Label 3355: @111145 |
| 40261 | /* 111145 */ GIM_Try, /*On fail goto*//*Label 3372*/ GIMT_Encode4(111938), |
| 40262 | /* 111150 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 40263 | /* 111153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40264 | /* 111157 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3373*/ GIMT_Encode4(111241), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2790 // |
| 40265 | /* 111164 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40266 | /* 111168 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40267 | /* 111172 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40268 | /* 111176 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40269 | /* 111180 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 40270 | /* 111184 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 40271 | /* 111188 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40272 | /* 111192 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 40273 | /* 111196 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40274 | /* 111201 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40275 | /* 111206 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40276 | /* 111211 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40277 | /* 111213 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40278 | /* 111213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 40279 | /* 111216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40280 | /* 111218 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40281 | /* 111222 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40282 | /* 111226 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40283 | /* 111230 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40284 | /* 111233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40285 | /* 111239 */ GIR_RootConstrainSelectedInstOperands, |
| 40286 | /* 111240 */ // GIR_Coverage, 2790, |
| 40287 | /* 111240 */ GIR_EraseRootFromParent_Done, |
| 40288 | /* 111241 */ // Label 3373: @111241 |
| 40289 | /* 111241 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3374*/ GIMT_Encode4(111325), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6332 // |
| 40290 | /* 111248 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40291 | /* 111252 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40292 | /* 111256 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40293 | /* 111260 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40294 | /* 111264 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 40295 | /* 111268 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40296 | /* 111273 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40297 | /* 111277 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40298 | /* 111281 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 40299 | /* 111285 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40300 | /* 111290 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40301 | /* 111295 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40302 | /* 111297 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40303 | /* 111297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 40304 | /* 111300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40305 | /* 111302 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40306 | /* 111306 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40307 | /* 111310 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 40308 | /* 111314 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40309 | /* 111317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40310 | /* 111323 */ GIR_RootConstrainSelectedInstOperands, |
| 40311 | /* 111324 */ // GIR_Coverage, 6332, |
| 40312 | /* 111324 */ GIR_EraseRootFromParent_Done, |
| 40313 | /* 111325 */ // Label 3374: @111325 |
| 40314 | /* 111325 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3375*/ GIMT_Encode4(111409), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2789 // |
| 40315 | /* 111332 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40316 | /* 111336 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40317 | /* 111340 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40318 | /* 111344 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40319 | /* 111348 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 40320 | /* 111352 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 40321 | /* 111356 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40322 | /* 111360 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 40323 | /* 111364 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40324 | /* 111369 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40325 | /* 111374 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40326 | /* 111379 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40327 | /* 111381 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40328 | /* 111381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 40329 | /* 111384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40330 | /* 111386 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40331 | /* 111390 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40332 | /* 111394 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40333 | /* 111398 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40334 | /* 111401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40335 | /* 111407 */ GIR_RootConstrainSelectedInstOperands, |
| 40336 | /* 111408 */ // GIR_Coverage, 2789, |
| 40337 | /* 111408 */ GIR_EraseRootFromParent_Done, |
| 40338 | /* 111409 */ // Label 3375: @111409 |
| 40339 | /* 111409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3376*/ GIMT_Encode4(111493), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6331 // |
| 40340 | /* 111416 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40341 | /* 111420 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40342 | /* 111424 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40343 | /* 111428 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40344 | /* 111432 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 40345 | /* 111436 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40346 | /* 111441 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40347 | /* 111445 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40348 | /* 111449 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 40349 | /* 111453 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40350 | /* 111458 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40351 | /* 111463 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40352 | /* 111465 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40353 | /* 111465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 40354 | /* 111468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40355 | /* 111470 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40356 | /* 111474 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn |
| 40357 | /* 111478 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm |
| 40358 | /* 111482 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40359 | /* 111485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40360 | /* 111491 */ GIR_RootConstrainSelectedInstOperands, |
| 40361 | /* 111492 */ // GIR_Coverage, 6331, |
| 40362 | /* 111492 */ GIR_EraseRootFromParent_Done, |
| 40363 | /* 111493 */ // Label 3376: @111493 |
| 40364 | /* 111493 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3377*/ GIMT_Encode4(111565), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2764 // |
| 40365 | /* 111500 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40366 | /* 111504 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40367 | /* 111508 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40368 | /* 111512 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40369 | /* 111516 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 40370 | /* 111520 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40371 | /* 111525 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40372 | /* 111530 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40373 | /* 111535 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40374 | /* 111537 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40375 | /* 111537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 40376 | /* 111540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40377 | /* 111542 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40378 | /* 111546 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40379 | /* 111550 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40380 | /* 111554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40381 | /* 111557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40382 | /* 111563 */ GIR_RootConstrainSelectedInstOperands, |
| 40383 | /* 111564 */ // GIR_Coverage, 2764, |
| 40384 | /* 111564 */ GIR_EraseRootFromParent_Done, |
| 40385 | /* 111565 */ // Label 3377: @111565 |
| 40386 | /* 111565 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3378*/ GIMT_Encode4(111637), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2763 // |
| 40387 | /* 111572 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40388 | /* 111576 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40389 | /* 111580 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40390 | /* 111584 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40391 | /* 111588 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 40392 | /* 111592 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40393 | /* 111597 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40394 | /* 111602 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40395 | /* 111607 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40396 | /* 111609 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40397 | /* 111609 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 40398 | /* 111612 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40399 | /* 111614 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin |
| 40400 | /* 111618 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40401 | /* 111622 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40402 | /* 111626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40403 | /* 111629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40404 | /* 111635 */ GIR_RootConstrainSelectedInstOperands, |
| 40405 | /* 111636 */ // GIR_Coverage, 2763, |
| 40406 | /* 111636 */ GIR_EraseRootFromParent_Done, |
| 40407 | /* 111637 */ // Label 3378: @111637 |
| 40408 | /* 111637 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3379*/ GIMT_Encode4(111696), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 643 // |
| 40409 | /* 111644 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40410 | /* 111648 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 40411 | /* 111652 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40412 | /* 111656 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40413 | /* 111660 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40414 | /* 111665 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40415 | /* 111670 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40416 | /* 111672 */ // (fneg:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40417 | /* 111672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 40418 | /* 111675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40419 | /* 111677 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40420 | /* 111681 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40421 | /* 111685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40422 | /* 111688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40423 | /* 111694 */ GIR_RootConstrainSelectedInstOperands, |
| 40424 | /* 111695 */ // GIR_Coverage, 643, |
| 40425 | /* 111695 */ GIR_EraseRootFromParent_Done, |
| 40426 | /* 111696 */ // Label 3379: @111696 |
| 40427 | /* 111696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3380*/ GIMT_Encode4(111755), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 642 // |
| 40428 | /* 111703 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40429 | /* 111707 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL), |
| 40430 | /* 111711 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 40431 | /* 111715 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 40432 | /* 111719 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40433 | /* 111724 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40434 | /* 111729 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40435 | /* 111731 */ // (fneg:{ *:[f32] } (strict_fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 40436 | /* 111731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS), |
| 40437 | /* 111734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40438 | /* 111736 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 40439 | /* 111740 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm |
| 40440 | /* 111744 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40441 | /* 111747 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40442 | /* 111753 */ GIR_RootConstrainSelectedInstOperands, |
| 40443 | /* 111754 */ // GIR_Coverage, 642, |
| 40444 | /* 111754 */ GIR_EraseRootFromParent_Done, |
| 40445 | /* 111755 */ // Label 3380: @111755 |
| 40446 | /* 111755 */ GIM_Try, /*On fail goto*//*Label 3381*/ GIMT_Encode4(111937), |
| 40447 | /* 111760 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40448 | /* 111764 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3382*/ GIMT_Encode4(111789), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 690 // |
| 40449 | /* 111771 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VNEGS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 40450 | /* 111771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGS), |
| 40451 | /* 111774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40452 | /* 111776 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 40453 | /* 111778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40454 | /* 111781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40455 | /* 111787 */ GIR_RootConstrainSelectedInstOperands, |
| 40456 | /* 111788 */ // GIR_Coverage, 690, |
| 40457 | /* 111788 */ GIR_EraseRootFromParent_Done, |
| 40458 | /* 111789 */ // Label 3382: @111789 |
| 40459 | /* 111789 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3383*/ GIMT_Encode4(111936), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3091 // |
| 40460 | /* 111796 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VNEGfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 40461 | /* 111796 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 40462 | /* 111799 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40463 | /* 111803 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40464 | /* 111808 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 40465 | /* 111810 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 40466 | /* 111813 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40467 | /* 111817 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40468 | /* 111822 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 40469 | /* 111825 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40470 | /* 111830 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 40471 | /* 111833 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 40472 | /* 111837 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40473 | /* 111842 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 40474 | /* 111845 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 40475 | /* 111849 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 40476 | /* 111852 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40477 | /* 111857 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40478 | /* 111862 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 40479 | /* 111867 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 40480 | /* 111870 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VNEGfd), |
| 40481 | /* 111874 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40482 | /* 111879 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 40483 | /* 111882 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 40484 | /* 111885 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40485 | /* 111891 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 40486 | /* 111893 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 40487 | /* 111896 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40488 | /* 111900 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40489 | /* 111905 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 40490 | /* 111908 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40491 | /* 111913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40492 | /* 111916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40493 | /* 111918 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 40494 | /* 111925 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 40495 | /* 111930 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 40496 | /* 111935 */ // GIR_Coverage, 3091, |
| 40497 | /* 111935 */ GIR_EraseRootFromParent_Done, |
| 40498 | /* 111936 */ // Label 3383: @111936 |
| 40499 | /* 111936 */ GIM_Reject, |
| 40500 | /* 111937 */ // Label 3381: @111937 |
| 40501 | /* 111937 */ GIM_Reject, |
| 40502 | /* 111938 */ // Label 3372: @111938 |
| 40503 | /* 111938 */ GIM_Reject, |
| 40504 | /* 111939 */ // Label 3356: @111939 |
| 40505 | /* 111939 */ GIM_Try, /*On fail goto*//*Label 3384*/ GIMT_Encode4(112579), |
| 40506 | /* 111944 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40507 | /* 111947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40508 | /* 111951 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3385*/ GIMT_Encode4(112035), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2788 // |
| 40509 | /* 111958 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40510 | /* 111962 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40511 | /* 111966 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40512 | /* 111970 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40513 | /* 111974 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 40514 | /* 111978 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 40515 | /* 111982 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40516 | /* 111986 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 40517 | /* 111990 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40518 | /* 111995 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40519 | /* 112000 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40520 | /* 112005 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40521 | /* 112007 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40522 | /* 112007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 40523 | /* 112010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40524 | /* 112012 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 40525 | /* 112016 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 40526 | /* 112020 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 40527 | /* 112024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40528 | /* 112027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40529 | /* 112033 */ GIR_RootConstrainSelectedInstOperands, |
| 40530 | /* 112034 */ // GIR_Coverage, 2788, |
| 40531 | /* 112034 */ GIR_EraseRootFromParent_Done, |
| 40532 | /* 112035 */ // Label 3385: @112035 |
| 40533 | /* 112035 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3386*/ GIMT_Encode4(112119), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6330 // |
| 40534 | /* 112042 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40535 | /* 112046 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40536 | /* 112050 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40537 | /* 112054 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40538 | /* 112058 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 40539 | /* 112062 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40540 | /* 112067 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40541 | /* 112071 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40542 | /* 112075 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 40543 | /* 112079 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40544 | /* 112084 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40545 | /* 112089 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40546 | /* 112091 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40547 | /* 112091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 40548 | /* 112094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40549 | /* 112096 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 40550 | /* 112100 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 40551 | /* 112104 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm |
| 40552 | /* 112108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40553 | /* 112111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40554 | /* 112117 */ GIR_RootConstrainSelectedInstOperands, |
| 40555 | /* 112118 */ // GIR_Coverage, 6330, |
| 40556 | /* 112118 */ GIR_EraseRootFromParent_Done, |
| 40557 | /* 112119 */ // Label 3386: @112119 |
| 40558 | /* 112119 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3387*/ GIMT_Encode4(112203), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2787 // |
| 40559 | /* 112126 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40560 | /* 112130 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40561 | /* 112134 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40562 | /* 112138 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40563 | /* 112142 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 40564 | /* 112146 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 40565 | /* 112150 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40566 | /* 112154 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 40567 | /* 112158 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40568 | /* 112163 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40569 | /* 112168 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40570 | /* 112173 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40571 | /* 112175 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40572 | /* 112175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 40573 | /* 112178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40574 | /* 112180 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 40575 | /* 112184 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 40576 | /* 112188 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 40577 | /* 112192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40578 | /* 112195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40579 | /* 112201 */ GIR_RootConstrainSelectedInstOperands, |
| 40580 | /* 112202 */ // GIR_Coverage, 2787, |
| 40581 | /* 112202 */ GIR_EraseRootFromParent_Done, |
| 40582 | /* 112203 */ // Label 3387: @112203 |
| 40583 | /* 112203 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3388*/ GIMT_Encode4(112287), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6329 // |
| 40584 | /* 112210 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40585 | /* 112214 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40586 | /* 112218 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40587 | /* 112222 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40588 | /* 112226 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 40589 | /* 112230 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40590 | /* 112235 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 40591 | /* 112239 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 40592 | /* 112243 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 40593 | /* 112247 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40594 | /* 112252 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40595 | /* 112257 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 40596 | /* 112259 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40597 | /* 112259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 40598 | /* 112262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40599 | /* 112264 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 40600 | /* 112268 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn |
| 40601 | /* 112272 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm |
| 40602 | /* 112276 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40603 | /* 112279 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40604 | /* 112285 */ GIR_RootConstrainSelectedInstOperands, |
| 40605 | /* 112286 */ // GIR_Coverage, 6329, |
| 40606 | /* 112286 */ GIR_EraseRootFromParent_Done, |
| 40607 | /* 112287 */ // Label 3388: @112287 |
| 40608 | /* 112287 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3389*/ GIMT_Encode4(112359), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2762 // |
| 40609 | /* 112294 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40610 | /* 112298 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 40611 | /* 112302 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40612 | /* 112306 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40613 | /* 112310 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 40614 | /* 112314 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40615 | /* 112319 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40616 | /* 112324 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40617 | /* 112329 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40618 | /* 112331 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40619 | /* 112331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 40620 | /* 112334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40621 | /* 112336 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 40622 | /* 112340 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 40623 | /* 112344 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 40624 | /* 112348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40625 | /* 112351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40626 | /* 112357 */ GIR_RootConstrainSelectedInstOperands, |
| 40627 | /* 112358 */ // GIR_Coverage, 2762, |
| 40628 | /* 112358 */ GIR_EraseRootFromParent_Done, |
| 40629 | /* 112359 */ // Label 3389: @112359 |
| 40630 | /* 112359 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3390*/ GIMT_Encode4(112431), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2761 // |
| 40631 | /* 112366 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40632 | /* 112370 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA), |
| 40633 | /* 112374 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40634 | /* 112378 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40635 | /* 112382 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64, |
| 40636 | /* 112386 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40637 | /* 112391 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40638 | /* 112396 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40639 | /* 112401 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40640 | /* 112403 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40641 | /* 112403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 40642 | /* 112406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40643 | /* 112408 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin |
| 40644 | /* 112412 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 40645 | /* 112416 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 40646 | /* 112420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40647 | /* 112423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40648 | /* 112429 */ GIR_RootConstrainSelectedInstOperands, |
| 40649 | /* 112430 */ // GIR_Coverage, 2761, |
| 40650 | /* 112430 */ GIR_EraseRootFromParent_Done, |
| 40651 | /* 112431 */ // Label 3390: @112431 |
| 40652 | /* 112431 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3391*/ GIMT_Encode4(112490), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 641 // |
| 40653 | /* 112438 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40654 | /* 112442 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 40655 | /* 112446 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40656 | /* 112450 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40657 | /* 112454 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40658 | /* 112459 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40659 | /* 112464 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40660 | /* 112466 */ // (fneg:{ *:[f64] } (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40661 | /* 112466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 40662 | /* 112469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40663 | /* 112471 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 40664 | /* 112475 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 40665 | /* 112479 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40666 | /* 112482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40667 | /* 112488 */ GIR_RootConstrainSelectedInstOperands, |
| 40668 | /* 112489 */ // GIR_Coverage, 641, |
| 40669 | /* 112489 */ GIR_EraseRootFromParent_Done, |
| 40670 | /* 112490 */ // Label 3391: @112490 |
| 40671 | /* 112490 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3392*/ GIMT_Encode4(112549), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 640 // |
| 40672 | /* 112497 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 40673 | /* 112501 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL), |
| 40674 | /* 112505 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 40675 | /* 112509 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 40676 | /* 112513 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40677 | /* 112518 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40678 | /* 112523 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 40679 | /* 112525 */ // (fneg:{ *:[f64] } (strict_fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 40680 | /* 112525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD), |
| 40681 | /* 112528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40682 | /* 112530 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 40683 | /* 112534 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm |
| 40684 | /* 112538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40685 | /* 112541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40686 | /* 112547 */ GIR_RootConstrainSelectedInstOperands, |
| 40687 | /* 112548 */ // GIR_Coverage, 640, |
| 40688 | /* 112548 */ GIR_EraseRootFromParent_Done, |
| 40689 | /* 112549 */ // Label 3392: @112549 |
| 40690 | /* 112549 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3393*/ GIMT_Encode4(112578), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 689 // |
| 40691 | /* 112556 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40692 | /* 112560 */ // (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VNEGD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 40693 | /* 112560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGD), |
| 40694 | /* 112563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40695 | /* 112565 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 40696 | /* 112567 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40697 | /* 112570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40698 | /* 112576 */ GIR_RootConstrainSelectedInstOperands, |
| 40699 | /* 112577 */ // GIR_Coverage, 689, |
| 40700 | /* 112577 */ GIR_EraseRootFromParent_Done, |
| 40701 | /* 112578 */ // Label 3393: @112578 |
| 40702 | /* 112578 */ GIM_Reject, |
| 40703 | /* 112579 */ // Label 3384: @112579 |
| 40704 | /* 112579 */ GIM_Reject, |
| 40705 | /* 112580 */ // Label 3357: @112580 |
| 40706 | /* 112580 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3394*/ GIMT_Encode4(112616), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1694 // |
| 40707 | /* 112587 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 40708 | /* 112590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40709 | /* 112594 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40710 | /* 112598 */ // (fneg:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VNEGhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 40711 | /* 112598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhd), |
| 40712 | /* 112601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40713 | /* 112603 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40714 | /* 112605 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40715 | /* 112608 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40716 | /* 112614 */ GIR_RootConstrainSelectedInstOperands, |
| 40717 | /* 112615 */ // GIR_Coverage, 1694, |
| 40718 | /* 112615 */ GIR_EraseRootFromParent_Done, |
| 40719 | /* 112616 */ // Label 3394: @112616 |
| 40720 | /* 112616 */ GIM_Reject, |
| 40721 | /* 112617 */ // Label 3358: @112617 |
| 40722 | /* 112617 */ GIM_Try, /*On fail goto*//*Label 3395*/ GIMT_Encode4(112713), |
| 40723 | /* 112622 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 40724 | /* 112625 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3396*/ GIMT_Encode4(112658), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1695 // |
| 40725 | /* 112632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40726 | /* 112636 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40727 | /* 112640 */ // (fneg:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VNEGhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 40728 | /* 112640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhq), |
| 40729 | /* 112643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40730 | /* 112645 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40731 | /* 112647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40732 | /* 112650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40733 | /* 112656 */ GIR_RootConstrainSelectedInstOperands, |
| 40734 | /* 112657 */ // GIR_Coverage, 1695, |
| 40735 | /* 112657 */ GIR_EraseRootFromParent_Done, |
| 40736 | /* 112658 */ // Label 3396: @112658 |
| 40737 | /* 112658 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3397*/ GIMT_Encode4(112712), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4564 // |
| 40738 | /* 112665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40739 | /* 112669 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40740 | /* 112673 */ // (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VNEGf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v) |
| 40741 | /* 112673 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40742 | /* 112676 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40743 | /* 112680 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40744 | /* 112685 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf16), |
| 40745 | /* 112688 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40746 | /* 112690 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 40747 | /* 112692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40748 | /* 112695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40749 | /* 112701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40750 | /* 112707 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40751 | /* 112710 */ GIR_RootConstrainSelectedInstOperands, |
| 40752 | /* 112711 */ // GIR_Coverage, 4564, |
| 40753 | /* 112711 */ GIR_EraseRootFromParent_Done, |
| 40754 | /* 112712 */ // Label 3397: @112712 |
| 40755 | /* 112712 */ GIM_Reject, |
| 40756 | /* 112713 */ // Label 3395: @112713 |
| 40757 | /* 112713 */ GIM_Reject, |
| 40758 | /* 112714 */ // Label 3359: @112714 |
| 40759 | /* 112714 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3398*/ GIMT_Encode4(112750), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1692 // |
| 40760 | /* 112721 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 40761 | /* 112724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40762 | /* 112728 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40763 | /* 112732 */ // (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VNEGfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 40764 | /* 112732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGfd), |
| 40765 | /* 112735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40766 | /* 112737 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40767 | /* 112739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40768 | /* 112742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40769 | /* 112748 */ GIR_RootConstrainSelectedInstOperands, |
| 40770 | /* 112749 */ // GIR_Coverage, 1692, |
| 40771 | /* 112749 */ GIR_EraseRootFromParent_Done, |
| 40772 | /* 112750 */ // Label 3398: @112750 |
| 40773 | /* 112750 */ GIM_Reject, |
| 40774 | /* 112751 */ // Label 3360: @112751 |
| 40775 | /* 112751 */ GIM_Try, /*On fail goto*//*Label 3399*/ GIMT_Encode4(112847), |
| 40776 | /* 112756 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40777 | /* 112759 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3400*/ GIMT_Encode4(112792), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1693 // |
| 40778 | /* 112766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40779 | /* 112770 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40780 | /* 112774 */ // (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VNEGf32q:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 40781 | /* 112774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGf32q), |
| 40782 | /* 112777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40783 | /* 112779 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 40784 | /* 112781 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40785 | /* 112784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40786 | /* 112790 */ GIR_RootConstrainSelectedInstOperands, |
| 40787 | /* 112791 */ // GIR_Coverage, 1693, |
| 40788 | /* 112791 */ GIR_EraseRootFromParent_Done, |
| 40789 | /* 112792 */ // Label 3400: @112792 |
| 40790 | /* 112792 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3401*/ GIMT_Encode4(112846), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4566 // |
| 40791 | /* 112799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40792 | /* 112803 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 40793 | /* 112807 */ // (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VNEGf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v) |
| 40794 | /* 112807 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 40795 | /* 112810 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40796 | /* 112814 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40797 | /* 112819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf32), |
| 40798 | /* 112822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 40799 | /* 112824 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 40800 | /* 112826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40801 | /* 112829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40802 | /* 112835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40803 | /* 112841 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40804 | /* 112844 */ GIR_RootConstrainSelectedInstOperands, |
| 40805 | /* 112845 */ // GIR_Coverage, 4566, |
| 40806 | /* 112845 */ GIR_EraseRootFromParent_Done, |
| 40807 | /* 112846 */ // Label 3401: @112846 |
| 40808 | /* 112846 */ GIM_Reject, |
| 40809 | /* 112847 */ // Label 3399: @112847 |
| 40810 | /* 112847 */ GIM_Reject, |
| 40811 | /* 112848 */ // Label 3361: @112848 |
| 40812 | /* 112848 */ GIM_Reject, |
| 40813 | /* 112849 */ // Label 46: @112849 |
| 40814 | /* 112849 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3405*/ GIMT_Encode4(113112), |
| 40815 | /* 112860 */ /*GILLT_s32*//*Label 3402*/ GIMT_Encode4(112908), |
| 40816 | /* 112864 */ /*GILLT_s64*//*Label 3403*/ GIMT_Encode4(112967), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40817 | /* 112904 */ /*GILLT_v4s32*//*Label 3404*/ GIMT_Encode4(113077), |
| 40818 | /* 112908 */ // Label 3402: @112908 |
| 40819 | /* 112908 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3406*/ GIMT_Encode4(112966), GIMT_Encode2(GIFBS_HasFP16), // Rule ID 2501 // |
| 40820 | /* 112915 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 40821 | /* 112918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40822 | /* 112922 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40823 | /* 112926 */ // (fpextend:{ *:[f32] } HPR:{ *:[f16] }:$Sm) => (VCVTBHS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] })) |
| 40824 | /* 112926 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40825 | /* 112929 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40826 | /* 112933 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40827 | /* 112938 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm |
| 40828 | /* 112942 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 40829 | /* 112947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHS), |
| 40830 | /* 112950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40831 | /* 112952 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40832 | /* 112955 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40833 | /* 112958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40834 | /* 112964 */ GIR_RootConstrainSelectedInstOperands, |
| 40835 | /* 112965 */ // GIR_Coverage, 2501, |
| 40836 | /* 112965 */ GIR_EraseRootFromParent_Done, |
| 40837 | /* 112966 */ // Label 3406: @112966 |
| 40838 | /* 112966 */ GIM_Reject, |
| 40839 | /* 112967 */ // Label 3403: @112967 |
| 40840 | /* 112967 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 3409*/ GIMT_Encode4(113076), |
| 40841 | /* 112978 */ /*GILLT_s16*//*Label 3407*/ GIMT_Encode4(112986), |
| 40842 | /* 112982 */ /*GILLT_s32*//*Label 3408*/ GIMT_Encode4(113042), |
| 40843 | /* 112986 */ // Label 3407: @112986 |
| 40844 | /* 112986 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3410*/ GIMT_Encode4(113041), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2521 // |
| 40845 | /* 112993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40846 | /* 112997 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40847 | /* 113001 */ // (fpextend:{ *:[f64] } HPR:{ *:[f16] }:$Sm) => (VCVTBHD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] })) |
| 40848 | /* 113001 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40849 | /* 113004 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40850 | /* 113008 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40851 | /* 113013 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm |
| 40852 | /* 113017 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 40853 | /* 113022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHD), |
| 40854 | /* 113025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40855 | /* 113027 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40856 | /* 113030 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40857 | /* 113033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40858 | /* 113039 */ GIR_RootConstrainSelectedInstOperands, |
| 40859 | /* 113040 */ // GIR_Coverage, 2521, |
| 40860 | /* 113040 */ GIR_EraseRootFromParent_Done, |
| 40861 | /* 113041 */ // Label 3410: @113041 |
| 40862 | /* 113041 */ GIM_Reject, |
| 40863 | /* 113042 */ // Label 3408: @113042 |
| 40864 | /* 113042 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3411*/ GIMT_Encode4(113075), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 686 // |
| 40865 | /* 113049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40866 | /* 113053 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40867 | /* 113057 */ // (fpextend:{ *:[f64] } SPR:{ *:[f32] }:$Sm) => (VCVTDS:{ *:[f64] } SPR:{ *:[f32] }:$Sm) |
| 40868 | /* 113057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTDS), |
| 40869 | /* 113060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 40870 | /* 113062 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 40871 | /* 113064 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40872 | /* 113067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40873 | /* 113073 */ GIR_RootConstrainSelectedInstOperands, |
| 40874 | /* 113074 */ // GIR_Coverage, 686, |
| 40875 | /* 113074 */ GIR_EraseRootFromParent_Done, |
| 40876 | /* 113075 */ // Label 3411: @113075 |
| 40877 | /* 113075 */ GIM_Reject, |
| 40878 | /* 113076 */ // Label 3409: @113076 |
| 40879 | /* 113076 */ GIM_Reject, |
| 40880 | /* 113077 */ // Label 3404: @113077 |
| 40881 | /* 113077 */ GIM_Try, /*On fail goto*//*Label 3412*/ GIMT_Encode4(113111), // Rule ID 3056 // |
| 40882 | /* 113082 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 40883 | /* 113085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40884 | /* 113089 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40885 | /* 113093 */ // (fpextend:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src) |
| 40886 | /* 113093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f), |
| 40887 | /* 113096 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40888 | /* 113098 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 40889 | /* 113100 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40890 | /* 113103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40891 | /* 113109 */ GIR_RootConstrainSelectedInstOperands, |
| 40892 | /* 113110 */ // GIR_Coverage, 3056, |
| 40893 | /* 113110 */ GIR_EraseRootFromParent_Done, |
| 40894 | /* 113111 */ // Label 3412: @113111 |
| 40895 | /* 113111 */ GIM_Reject, |
| 40896 | /* 113112 */ // Label 3405: @113112 |
| 40897 | /* 113112 */ GIM_Reject, |
| 40898 | /* 113113 */ // Label 47: @113113 |
| 40899 | /* 113113 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(10), /*)*//*default:*//*Label 3416*/ GIMT_Encode4(113404), |
| 40900 | /* 113124 */ /*GILLT_s16*//*Label 3413*/ GIMT_Encode4(113164), |
| 40901 | /* 113128 */ /*GILLT_s32*//*Label 3414*/ GIMT_Encode4(113332), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40902 | /* 113160 */ /*GILLT_v4s16*//*Label 3415*/ GIMT_Encode4(113369), |
| 40903 | /* 113164 */ // Label 3413: @113164 |
| 40904 | /* 113164 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 3419*/ GIMT_Encode4(113331), |
| 40905 | /* 113175 */ /*GILLT_s32*//*Label 3417*/ GIMT_Encode4(113183), |
| 40906 | /* 113179 */ /*GILLT_s64*//*Label 3418*/ GIMT_Encode4(113257), |
| 40907 | /* 113183 */ // Label 3417: @113183 |
| 40908 | /* 113183 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3420*/ GIMT_Encode4(113256), GIMT_Encode2(GIFBS_HasFP16), // Rule ID 2505 // |
| 40909 | /* 113190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40910 | /* 113194 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40911 | /* 113198 */ // (fpround:{ *:[f16] } SPR:{ *:[f32] }:$Sm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBSH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), SPR:{ *:[f32] }:$Sm), HPR:{ *:[i32] }) |
| 40912 | /* 113198 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 40913 | /* 113201 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40914 | /* 113205 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40915 | /* 113210 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 40916 | /* 113212 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40917 | /* 113215 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBSH), |
| 40918 | /* 113219 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40919 | /* 113224 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 40920 | /* 113227 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm |
| 40921 | /* 113231 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 40922 | /* 113234 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40923 | /* 113240 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40924 | /* 113242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40925 | /* 113245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40926 | /* 113247 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40927 | /* 113250 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 40928 | /* 113255 */ // GIR_Coverage, 2505, |
| 40929 | /* 113255 */ GIR_EraseRootFromParent_Done, |
| 40930 | /* 113256 */ // Label 3420: @113256 |
| 40931 | /* 113256 */ GIM_Reject, |
| 40932 | /* 113257 */ // Label 3418: @113257 |
| 40933 | /* 113257 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3421*/ GIMT_Encode4(113330), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2525 // |
| 40934 | /* 113264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 40935 | /* 113268 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40936 | /* 113272 */ // (fpround:{ *:[f16] } DPR:{ *:[f64] }:$Dm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBDH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), DPR:{ *:[f64] }:$Dm), HPR:{ *:[i32] }) |
| 40937 | /* 113272 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 40938 | /* 113275 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 40939 | /* 113279 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40940 | /* 113284 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 40941 | /* 113286 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 40942 | /* 113289 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBDH), |
| 40943 | /* 113293 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 40944 | /* 113298 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 40945 | /* 113301 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dm |
| 40946 | /* 113305 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 40947 | /* 113308 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40948 | /* 113314 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 40949 | /* 113316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 40950 | /* 113319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 40951 | /* 113321 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 40952 | /* 113324 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID), |
| 40953 | /* 113329 */ // GIR_Coverage, 2525, |
| 40954 | /* 113329 */ GIR_EraseRootFromParent_Done, |
| 40955 | /* 113330 */ // Label 3421: @113330 |
| 40956 | /* 113330 */ GIM_Reject, |
| 40957 | /* 113331 */ // Label 3419: @113331 |
| 40958 | /* 113331 */ GIM_Reject, |
| 40959 | /* 113332 */ // Label 3414: @113332 |
| 40960 | /* 113332 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3422*/ GIMT_Encode4(113368), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 688 // |
| 40961 | /* 113339 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 40962 | /* 113342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 40963 | /* 113346 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40964 | /* 113350 */ // (fpround:{ *:[f32] } DPR:{ *:[f64] }:$Dm) => (VCVTSD:{ *:[f32] } DPR:{ *:[f64] }:$Dm) |
| 40965 | /* 113350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTSD), |
| 40966 | /* 113353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 40967 | /* 113355 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 40968 | /* 113357 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40969 | /* 113360 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40970 | /* 113366 */ GIR_RootConstrainSelectedInstOperands, |
| 40971 | /* 113367 */ // GIR_Coverage, 688, |
| 40972 | /* 113367 */ GIR_EraseRootFromParent_Done, |
| 40973 | /* 113368 */ // Label 3422: @113368 |
| 40974 | /* 113368 */ GIM_Reject, |
| 40975 | /* 113369 */ // Label 3415: @113369 |
| 40976 | /* 113369 */ GIM_Try, /*On fail goto*//*Label 3423*/ GIMT_Encode4(113403), // Rule ID 3055 // |
| 40977 | /* 113374 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 40978 | /* 113377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 40979 | /* 113381 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 40980 | /* 113385 */ // (fpround:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src) => (VCVTf2h:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src) |
| 40981 | /* 113385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h), |
| 40982 | /* 113388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 40983 | /* 113390 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 40984 | /* 113392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 40985 | /* 113395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 40986 | /* 113401 */ GIR_RootConstrainSelectedInstOperands, |
| 40987 | /* 113402 */ // GIR_Coverage, 3055, |
| 40988 | /* 113402 */ GIR_EraseRootFromParent_Done, |
| 40989 | /* 113403 */ // Label 3423: @113403 |
| 40990 | /* 113403 */ GIM_Reject, |
| 40991 | /* 113404 */ // Label 3416: @113404 |
| 40992 | /* 113404 */ GIM_Reject, |
| 40993 | /* 113405 */ // Label 48: @113405 |
| 40994 | /* 113405 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3431*/ GIMT_Encode4(114686), |
| 40995 | /* 113416 */ /*GILLT_s32*//*Label 3424*/ GIMT_Encode4(113464), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40996 | /* 113428 */ /*GILLT_v4s1*//*Label 3425*/ GIMT_Encode4(114314), |
| 40997 | /* 113432 */ /*GILLT_v8s1*//*Label 3426*/ GIMT_Encode4(114366), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 40998 | /* 113448 */ /*GILLT_v4s16*//*Label 3427*/ GIMT_Encode4(114418), |
| 40999 | /* 113452 */ /*GILLT_v8s16*//*Label 3428*/ GIMT_Encode4(114455), |
| 41000 | /* 113456 */ /*GILLT_v2s32*//*Label 3429*/ GIMT_Encode4(114552), |
| 41001 | /* 113460 */ /*GILLT_v4s32*//*Label 3430*/ GIMT_Encode4(114589), |
| 41002 | /* 113464 */ // Label 3424: @113464 |
| 41003 | /* 113464 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3435*/ GIMT_Encode4(114313), |
| 41004 | /* 113475 */ /*GILLT_s16*//*Label 3432*/ GIMT_Encode4(113487), |
| 41005 | /* 113479 */ /*GILLT_s32*//*Label 3433*/ GIMT_Encode4(113724), |
| 41006 | /* 113483 */ /*GILLT_s64*//*Label 3434*/ GIMT_Encode4(114076), |
| 41007 | /* 113487 */ // Label 3432: @113487 |
| 41008 | /* 113487 */ GIM_Try, /*On fail goto*//*Label 3436*/ GIMT_Encode4(113723), |
| 41009 | /* 113492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41010 | /* 113496 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3437*/ GIMT_Encode4(113554), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2555 // |
| 41011 | /* 113503 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41012 | /* 113507 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41013 | /* 113511 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41014 | /* 113515 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41015 | /* 113520 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41016 | /* 113522 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41017 | /* 113522 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41018 | /* 113525 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSH), |
| 41019 | /* 113529 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41020 | /* 113534 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41021 | /* 113538 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41022 | /* 113540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41023 | /* 113543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41024 | /* 113545 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41025 | /* 113548 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41026 | /* 113553 */ // GIR_Coverage, 2555, |
| 41027 | /* 113553 */ GIR_EraseRootFromParent_Done, |
| 41028 | /* 113554 */ // Label 3437: @113554 |
| 41029 | /* 113554 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3438*/ GIMT_Encode4(113612), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2579 // |
| 41030 | /* 113561 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41031 | /* 113565 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41032 | /* 113569 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41033 | /* 113573 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41034 | /* 113578 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41035 | /* 113580 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41036 | /* 113580 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41037 | /* 113583 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSH), |
| 41038 | /* 113587 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41039 | /* 113592 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41040 | /* 113596 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41041 | /* 113598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41042 | /* 113601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41043 | /* 113603 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41044 | /* 113606 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41045 | /* 113611 */ // GIR_Coverage, 2579, |
| 41046 | /* 113611 */ GIR_EraseRootFromParent_Done, |
| 41047 | /* 113612 */ // Label 3438: @113612 |
| 41048 | /* 113612 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3439*/ GIMT_Encode4(113670), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2531 // |
| 41049 | /* 113619 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41050 | /* 113623 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41051 | /* 113627 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41052 | /* 113631 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41053 | /* 113636 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41054 | /* 113638 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41055 | /* 113638 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41056 | /* 113641 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASH), |
| 41057 | /* 113645 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41058 | /* 113650 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41059 | /* 113654 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41060 | /* 113656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41061 | /* 113659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41062 | /* 113661 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41063 | /* 113664 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41064 | /* 113669 */ // GIR_Coverage, 2531, |
| 41065 | /* 113669 */ GIR_EraseRootFromParent_Done, |
| 41066 | /* 113670 */ // Label 3439: @113670 |
| 41067 | /* 113670 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3440*/ GIMT_Encode4(113722), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2640 // |
| 41068 | /* 113677 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41069 | /* 113681 */ // (fp_to_sint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41070 | /* 113681 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41071 | /* 113684 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZH), |
| 41072 | /* 113688 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41073 | /* 113693 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41074 | /* 113697 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41075 | /* 113700 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41076 | /* 113706 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41077 | /* 113708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41078 | /* 113711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41079 | /* 113713 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41080 | /* 113716 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41081 | /* 113721 */ // GIR_Coverage, 2640, |
| 41082 | /* 113721 */ GIR_EraseRootFromParent_Done, |
| 41083 | /* 113722 */ // Label 3440: @113722 |
| 41084 | /* 113722 */ GIM_Reject, |
| 41085 | /* 113723 */ // Label 3436: @113723 |
| 41086 | /* 113723 */ GIM_Reject, |
| 41087 | /* 113724 */ // Label 3433: @113724 |
| 41088 | /* 113724 */ GIM_Try, /*On fail goto*//*Label 3441*/ GIMT_Encode4(113960), |
| 41089 | /* 113729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41090 | /* 113733 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3442*/ GIMT_Encode4(113791), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2563 // |
| 41091 | /* 113740 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41092 | /* 113744 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41093 | /* 113748 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41094 | /* 113752 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41095 | /* 113757 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41096 | /* 113759 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41097 | /* 113759 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41098 | /* 113762 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSS), |
| 41099 | /* 113766 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41100 | /* 113771 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41101 | /* 113775 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41102 | /* 113777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41103 | /* 113780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41104 | /* 113782 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41105 | /* 113785 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41106 | /* 113790 */ // GIR_Coverage, 2563, |
| 41107 | /* 113790 */ GIR_EraseRootFromParent_Done, |
| 41108 | /* 113791 */ // Label 3442: @113791 |
| 41109 | /* 113791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3443*/ GIMT_Encode4(113849), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2587 // |
| 41110 | /* 113798 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41111 | /* 113802 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41112 | /* 113806 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41113 | /* 113810 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41114 | /* 113815 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41115 | /* 113817 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41116 | /* 113817 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41117 | /* 113820 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSS), |
| 41118 | /* 113824 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41119 | /* 113829 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41120 | /* 113833 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41121 | /* 113835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41122 | /* 113838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41123 | /* 113840 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41124 | /* 113843 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41125 | /* 113848 */ // GIR_Coverage, 2587, |
| 41126 | /* 113848 */ GIR_EraseRootFromParent_Done, |
| 41127 | /* 113849 */ // Label 3443: @113849 |
| 41128 | /* 113849 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3444*/ GIMT_Encode4(113907), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2539 // |
| 41129 | /* 113856 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41130 | /* 113860 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41131 | /* 113864 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41132 | /* 113868 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41133 | /* 113873 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41134 | /* 113875 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41135 | /* 113875 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41136 | /* 113878 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASS), |
| 41137 | /* 113882 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41138 | /* 113887 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41139 | /* 113891 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41140 | /* 113893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41141 | /* 113896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41142 | /* 113898 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41143 | /* 113901 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41144 | /* 113906 */ // GIR_Coverage, 2539, |
| 41145 | /* 113906 */ GIR_EraseRootFromParent_Done, |
| 41146 | /* 113907 */ // Label 3444: @113907 |
| 41147 | /* 113907 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3445*/ GIMT_Encode4(113959), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2634 // |
| 41148 | /* 113914 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41149 | /* 113918 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41150 | /* 113918 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41151 | /* 113921 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZS), |
| 41152 | /* 113925 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41153 | /* 113930 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41154 | /* 113934 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41155 | /* 113937 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41156 | /* 113943 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41157 | /* 113945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41158 | /* 113948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41159 | /* 113950 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41160 | /* 113953 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41161 | /* 113958 */ // GIR_Coverage, 2634, |
| 41162 | /* 113958 */ GIR_EraseRootFromParent_Done, |
| 41163 | /* 113959 */ // Label 3445: @113959 |
| 41164 | /* 113959 */ GIM_Reject, |
| 41165 | /* 113960 */ // Label 3441: @113960 |
| 41166 | /* 113960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3446*/ GIMT_Encode4(114075), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3096 // |
| 41167 | /* 113967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41168 | /* 113971 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41169 | /* 113975 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2sd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 41170 | /* 113975 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41171 | /* 113978 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41172 | /* 113982 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41173 | /* 113987 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 41174 | /* 113989 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 41175 | /* 113992 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41176 | /* 113996 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41177 | /* 114001 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41178 | /* 114004 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41179 | /* 114008 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 41180 | /* 114011 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41181 | /* 114016 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41182 | /* 114021 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41183 | /* 114026 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41184 | /* 114029 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd), |
| 41185 | /* 114033 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41186 | /* 114038 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41187 | /* 114041 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41188 | /* 114044 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41189 | /* 114050 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41190 | /* 114052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41191 | /* 114055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41192 | /* 114057 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41193 | /* 114064 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41194 | /* 114069 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41195 | /* 114074 */ // GIR_Coverage, 3096, |
| 41196 | /* 114074 */ GIR_EraseRootFromParent_Done, |
| 41197 | /* 114075 */ // Label 3446: @114075 |
| 41198 | /* 114075 */ GIM_Reject, |
| 41199 | /* 114076 */ // Label 3434: @114076 |
| 41200 | /* 114076 */ GIM_Try, /*On fail goto*//*Label 3447*/ GIMT_Encode4(114312), |
| 41201 | /* 114081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41202 | /* 114085 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3448*/ GIMT_Encode4(114143), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2571 // |
| 41203 | /* 114092 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41204 | /* 114096 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41205 | /* 114100 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41206 | /* 114104 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41207 | /* 114109 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41208 | /* 114111 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41209 | /* 114111 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41210 | /* 114114 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSD), |
| 41211 | /* 114118 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41212 | /* 114123 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41213 | /* 114127 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41214 | /* 114129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41215 | /* 114132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41216 | /* 114134 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41217 | /* 114137 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41218 | /* 114142 */ // GIR_Coverage, 2571, |
| 41219 | /* 114142 */ GIR_EraseRootFromParent_Done, |
| 41220 | /* 114143 */ // Label 3448: @114143 |
| 41221 | /* 114143 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3449*/ GIMT_Encode4(114201), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2595 // |
| 41222 | /* 114150 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41223 | /* 114154 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41224 | /* 114158 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41225 | /* 114162 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41226 | /* 114167 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41227 | /* 114169 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41228 | /* 114169 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41229 | /* 114172 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSD), |
| 41230 | /* 114176 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41231 | /* 114181 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41232 | /* 114185 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41233 | /* 114187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41234 | /* 114190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41235 | /* 114192 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41236 | /* 114195 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41237 | /* 114200 */ // GIR_Coverage, 2595, |
| 41238 | /* 114200 */ GIR_EraseRootFromParent_Done, |
| 41239 | /* 114201 */ // Label 3449: @114201 |
| 41240 | /* 114201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3450*/ GIMT_Encode4(114259), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2547 // |
| 41241 | /* 114208 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41242 | /* 114212 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41243 | /* 114216 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41244 | /* 114220 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41245 | /* 114225 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41246 | /* 114227 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41247 | /* 114227 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41248 | /* 114230 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASD), |
| 41249 | /* 114234 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41250 | /* 114239 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41251 | /* 114243 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41252 | /* 114245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41253 | /* 114248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41254 | /* 114250 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41255 | /* 114253 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41256 | /* 114258 */ // GIR_Coverage, 2547, |
| 41257 | /* 114258 */ GIR_EraseRootFromParent_Done, |
| 41258 | /* 114259 */ // Label 3450: @114259 |
| 41259 | /* 114259 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3451*/ GIMT_Encode4(114311), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2628 // |
| 41260 | /* 114266 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41261 | /* 114270 */ // (fp_to_sint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41262 | /* 114270 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41263 | /* 114273 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZD), |
| 41264 | /* 114277 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41265 | /* 114282 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41266 | /* 114286 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41267 | /* 114289 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41268 | /* 114295 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41269 | /* 114297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41270 | /* 114300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41271 | /* 114302 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41272 | /* 114305 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41273 | /* 114310 */ // GIR_Coverage, 2628, |
| 41274 | /* 114310 */ GIR_EraseRootFromParent_Done, |
| 41275 | /* 114311 */ // Label 3451: @114311 |
| 41276 | /* 114311 */ GIM_Reject, |
| 41277 | /* 114312 */ // Label 3447: @114312 |
| 41278 | /* 114312 */ GIM_Reject, |
| 41279 | /* 114313 */ // Label 3435: @114313 |
| 41280 | /* 114313 */ GIM_Reject, |
| 41281 | /* 114314 */ // Label 3425: @114314 |
| 41282 | /* 114314 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3452*/ GIMT_Encode4(114365), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5631 // |
| 41283 | /* 114321 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41284 | /* 114324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 41285 | /* 114328 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41286 | /* 114332 */ // (fp_to_sint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 41287 | /* 114332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r), |
| 41288 | /* 114335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 41289 | /* 114337 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 41290 | /* 114339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41291 | /* 114345 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 41292 | /* 114348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41293 | /* 114351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41294 | /* 114357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41295 | /* 114363 */ GIR_RootConstrainSelectedInstOperands, |
| 41296 | /* 114364 */ // GIR_Coverage, 5631, |
| 41297 | /* 114364 */ GIR_EraseRootFromParent_Done, |
| 41298 | /* 114365 */ // Label 3452: @114365 |
| 41299 | /* 114365 */ GIM_Reject, |
| 41300 | /* 114366 */ // Label 3426: @114366 |
| 41301 | /* 114366 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3453*/ GIMT_Encode4(114417), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5632 // |
| 41302 | /* 114373 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41303 | /* 114376 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 41304 | /* 114380 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41305 | /* 114384 */ // (fp_to_sint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 41306 | /* 114384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r), |
| 41307 | /* 114387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 41308 | /* 114389 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 41309 | /* 114391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41310 | /* 114397 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 41311 | /* 114400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41312 | /* 114403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41313 | /* 114409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41314 | /* 114415 */ GIR_RootConstrainSelectedInstOperands, |
| 41315 | /* 114416 */ // GIR_Coverage, 5632, |
| 41316 | /* 114416 */ GIR_EraseRootFromParent_Done, |
| 41317 | /* 114417 */ // Label 3453: @114417 |
| 41318 | /* 114417 */ GIM_Reject, |
| 41319 | /* 114418 */ // Label 3427: @114418 |
| 41320 | /* 114418 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3454*/ GIMT_Encode4(114454), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1774 // |
| 41321 | /* 114425 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41322 | /* 114428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41323 | /* 114432 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41324 | /* 114436 */ // (fp_to_sint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2sd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 41325 | /* 114436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sd), |
| 41326 | /* 114439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41327 | /* 114441 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41328 | /* 114443 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41329 | /* 114446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41330 | /* 114452 */ GIR_RootConstrainSelectedInstOperands, |
| 41331 | /* 114453 */ // GIR_Coverage, 1774, |
| 41332 | /* 114453 */ GIR_EraseRootFromParent_Done, |
| 41333 | /* 114454 */ // Label 3454: @114454 |
| 41334 | /* 114454 */ GIM_Reject, |
| 41335 | /* 114455 */ // Label 3428: @114455 |
| 41336 | /* 114455 */ GIM_Try, /*On fail goto*//*Label 3455*/ GIMT_Encode4(114551), |
| 41337 | /* 114460 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41338 | /* 114463 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3456*/ GIMT_Encode4(114496), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1778 // |
| 41339 | /* 114470 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41340 | /* 114474 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41341 | /* 114478 */ // (fp_to_sint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2sq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 41342 | /* 114478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sq), |
| 41343 | /* 114481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41344 | /* 114483 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41345 | /* 114485 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41346 | /* 114488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41347 | /* 114494 */ GIR_RootConstrainSelectedInstOperands, |
| 41348 | /* 114495 */ // GIR_Coverage, 1778, |
| 41349 | /* 114495 */ GIR_EraseRootFromParent_Done, |
| 41350 | /* 114496 */ // Label 3456: @114496 |
| 41351 | /* 114496 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3457*/ GIMT_Encode4(114550), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4532 // |
| 41352 | /* 114503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41353 | /* 114507 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41354 | /* 114511 */ // (fp_to_sint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 41355 | /* 114511 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41356 | /* 114514 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41357 | /* 114518 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41358 | /* 114523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z), |
| 41359 | /* 114526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41360 | /* 114528 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41361 | /* 114530 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41362 | /* 114533 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41363 | /* 114539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41364 | /* 114545 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41365 | /* 114548 */ GIR_RootConstrainSelectedInstOperands, |
| 41366 | /* 114549 */ // GIR_Coverage, 4532, |
| 41367 | /* 114549 */ GIR_EraseRootFromParent_Done, |
| 41368 | /* 114550 */ // Label 3457: @114550 |
| 41369 | /* 114550 */ GIM_Reject, |
| 41370 | /* 114551 */ // Label 3455: @114551 |
| 41371 | /* 114551 */ GIM_Reject, |
| 41372 | /* 114552 */ // Label 3429: @114552 |
| 41373 | /* 114552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3458*/ GIMT_Encode4(114588), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1766 // |
| 41374 | /* 114559 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 41375 | /* 114562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41376 | /* 114566 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41377 | /* 114570 */ // (fp_to_sint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2sd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 41378 | /* 114570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd), |
| 41379 | /* 114573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41380 | /* 114575 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41381 | /* 114577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41382 | /* 114580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41383 | /* 114586 */ GIR_RootConstrainSelectedInstOperands, |
| 41384 | /* 114587 */ // GIR_Coverage, 1766, |
| 41385 | /* 114587 */ GIR_EraseRootFromParent_Done, |
| 41386 | /* 114588 */ // Label 3458: @114588 |
| 41387 | /* 114588 */ GIM_Reject, |
| 41388 | /* 114589 */ // Label 3430: @114589 |
| 41389 | /* 114589 */ GIM_Try, /*On fail goto*//*Label 3459*/ GIMT_Encode4(114685), |
| 41390 | /* 114594 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41391 | /* 114597 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3460*/ GIMT_Encode4(114630), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1770 // |
| 41392 | /* 114604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41393 | /* 114608 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41394 | /* 114612 */ // (fp_to_sint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2sq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 41395 | /* 114612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sq), |
| 41396 | /* 114615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41397 | /* 114617 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41398 | /* 114619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41399 | /* 114622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41400 | /* 114628 */ GIR_RootConstrainSelectedInstOperands, |
| 41401 | /* 114629 */ // GIR_Coverage, 1770, |
| 41402 | /* 114629 */ GIR_EraseRootFromParent_Done, |
| 41403 | /* 114630 */ // Label 3460: @114630 |
| 41404 | /* 114630 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3461*/ GIMT_Encode4(114684), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4538 // |
| 41405 | /* 114637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41406 | /* 114641 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41407 | /* 114645 */ // (fp_to_sint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 41408 | /* 114645 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41409 | /* 114648 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41410 | /* 114652 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41411 | /* 114657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z), |
| 41412 | /* 114660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41413 | /* 114662 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41414 | /* 114664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41415 | /* 114667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41416 | /* 114673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41417 | /* 114679 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41418 | /* 114682 */ GIR_RootConstrainSelectedInstOperands, |
| 41419 | /* 114683 */ // GIR_Coverage, 4538, |
| 41420 | /* 114683 */ GIR_EraseRootFromParent_Done, |
| 41421 | /* 114684 */ // Label 3461: @114684 |
| 41422 | /* 114684 */ GIM_Reject, |
| 41423 | /* 114685 */ // Label 3459: @114685 |
| 41424 | /* 114685 */ GIM_Reject, |
| 41425 | /* 114686 */ // Label 3431: @114686 |
| 41426 | /* 114686 */ GIM_Reject, |
| 41427 | /* 114687 */ // Label 49: @114687 |
| 41428 | /* 114687 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3469*/ GIMT_Encode4(115968), |
| 41429 | /* 114698 */ /*GILLT_s32*//*Label 3462*/ GIMT_Encode4(114746), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41430 | /* 114710 */ /*GILLT_v4s1*//*Label 3463*/ GIMT_Encode4(115596), |
| 41431 | /* 114714 */ /*GILLT_v8s1*//*Label 3464*/ GIMT_Encode4(115648), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41432 | /* 114730 */ /*GILLT_v4s16*//*Label 3465*/ GIMT_Encode4(115700), |
| 41433 | /* 114734 */ /*GILLT_v8s16*//*Label 3466*/ GIMT_Encode4(115737), |
| 41434 | /* 114738 */ /*GILLT_v2s32*//*Label 3467*/ GIMT_Encode4(115834), |
| 41435 | /* 114742 */ /*GILLT_v4s32*//*Label 3468*/ GIMT_Encode4(115871), |
| 41436 | /* 114746 */ // Label 3462: @114746 |
| 41437 | /* 114746 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3473*/ GIMT_Encode4(115595), |
| 41438 | /* 114757 */ /*GILLT_s16*//*Label 3470*/ GIMT_Encode4(114769), |
| 41439 | /* 114761 */ /*GILLT_s32*//*Label 3471*/ GIMT_Encode4(115006), |
| 41440 | /* 114765 */ /*GILLT_s64*//*Label 3472*/ GIMT_Encode4(115358), |
| 41441 | /* 114769 */ // Label 3470: @114769 |
| 41442 | /* 114769 */ GIM_Try, /*On fail goto*//*Label 3474*/ GIMT_Encode4(115005), |
| 41443 | /* 114774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41444 | /* 114778 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3475*/ GIMT_Encode4(114836), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2559 // |
| 41445 | /* 114785 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41446 | /* 114789 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41447 | /* 114793 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41448 | /* 114797 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41449 | /* 114802 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41450 | /* 114804 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41451 | /* 114804 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41452 | /* 114807 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUH), |
| 41453 | /* 114811 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41454 | /* 114816 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41455 | /* 114820 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41456 | /* 114822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41457 | /* 114825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41458 | /* 114827 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41459 | /* 114830 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41460 | /* 114835 */ // GIR_Coverage, 2559, |
| 41461 | /* 114835 */ GIR_EraseRootFromParent_Done, |
| 41462 | /* 114836 */ // Label 3475: @114836 |
| 41463 | /* 114836 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3476*/ GIMT_Encode4(114894), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2583 // |
| 41464 | /* 114843 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41465 | /* 114847 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41466 | /* 114851 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41467 | /* 114855 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41468 | /* 114860 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41469 | /* 114862 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41470 | /* 114862 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41471 | /* 114865 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUH), |
| 41472 | /* 114869 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41473 | /* 114874 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41474 | /* 114878 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41475 | /* 114880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41476 | /* 114883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41477 | /* 114885 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41478 | /* 114888 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41479 | /* 114893 */ // GIR_Coverage, 2583, |
| 41480 | /* 114893 */ GIR_EraseRootFromParent_Done, |
| 41481 | /* 114894 */ // Label 3476: @114894 |
| 41482 | /* 114894 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3477*/ GIMT_Encode4(114952), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2535 // |
| 41483 | /* 114901 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41484 | /* 114905 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41485 | /* 114909 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 41486 | /* 114913 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41487 | /* 114918 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41488 | /* 114920 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41489 | /* 114920 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41490 | /* 114923 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUH), |
| 41491 | /* 114927 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41492 | /* 114932 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41493 | /* 114936 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41494 | /* 114938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41495 | /* 114941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41496 | /* 114943 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41497 | /* 114946 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41498 | /* 114951 */ // GIR_Coverage, 2535, |
| 41499 | /* 114951 */ GIR_EraseRootFromParent_Done, |
| 41500 | /* 114952 */ // Label 3477: @114952 |
| 41501 | /* 114952 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3478*/ GIMT_Encode4(115004), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2655 // |
| 41502 | /* 114959 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41503 | /* 114963 */ // (fp_to_uint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 41504 | /* 114963 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41505 | /* 114966 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZH), |
| 41506 | /* 114970 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41507 | /* 114975 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41508 | /* 114979 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41509 | /* 114982 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41510 | /* 114988 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41511 | /* 114990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41512 | /* 114993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41513 | /* 114995 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41514 | /* 114998 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41515 | /* 115003 */ // GIR_Coverage, 2655, |
| 41516 | /* 115003 */ GIR_EraseRootFromParent_Done, |
| 41517 | /* 115004 */ // Label 3478: @115004 |
| 41518 | /* 115004 */ GIM_Reject, |
| 41519 | /* 115005 */ // Label 3474: @115005 |
| 41520 | /* 115005 */ GIM_Reject, |
| 41521 | /* 115006 */ // Label 3471: @115006 |
| 41522 | /* 115006 */ GIM_Try, /*On fail goto*//*Label 3479*/ GIMT_Encode4(115242), |
| 41523 | /* 115011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41524 | /* 115015 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3480*/ GIMT_Encode4(115073), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2567 // |
| 41525 | /* 115022 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41526 | /* 115026 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41527 | /* 115030 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41528 | /* 115034 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41529 | /* 115039 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41530 | /* 115041 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41531 | /* 115041 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41532 | /* 115044 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUS), |
| 41533 | /* 115048 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41534 | /* 115053 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41535 | /* 115057 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41536 | /* 115059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41537 | /* 115062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41538 | /* 115064 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41539 | /* 115067 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41540 | /* 115072 */ // GIR_Coverage, 2567, |
| 41541 | /* 115072 */ GIR_EraseRootFromParent_Done, |
| 41542 | /* 115073 */ // Label 3480: @115073 |
| 41543 | /* 115073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3481*/ GIMT_Encode4(115131), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2591 // |
| 41544 | /* 115080 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41545 | /* 115084 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41546 | /* 115088 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41547 | /* 115092 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41548 | /* 115097 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41549 | /* 115099 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41550 | /* 115099 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41551 | /* 115102 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUS), |
| 41552 | /* 115106 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41553 | /* 115111 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41554 | /* 115115 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41555 | /* 115117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41556 | /* 115120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41557 | /* 115122 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41558 | /* 115125 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41559 | /* 115130 */ // GIR_Coverage, 2591, |
| 41560 | /* 115130 */ GIR_EraseRootFromParent_Done, |
| 41561 | /* 115131 */ // Label 3481: @115131 |
| 41562 | /* 115131 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3482*/ GIMT_Encode4(115189), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2543 // |
| 41563 | /* 115138 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41564 | /* 115142 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41565 | /* 115146 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 41566 | /* 115150 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41567 | /* 115155 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41568 | /* 115157 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41569 | /* 115157 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41570 | /* 115160 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUS), |
| 41571 | /* 115164 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41572 | /* 115169 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41573 | /* 115173 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41574 | /* 115175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41575 | /* 115178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41576 | /* 115180 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41577 | /* 115183 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41578 | /* 115188 */ // GIR_Coverage, 2543, |
| 41579 | /* 115188 */ GIR_EraseRootFromParent_Done, |
| 41580 | /* 115189 */ // Label 3482: @115189 |
| 41581 | /* 115189 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3483*/ GIMT_Encode4(115241), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2649 // |
| 41582 | /* 115196 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41583 | /* 115200 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 41584 | /* 115200 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41585 | /* 115203 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZS), |
| 41586 | /* 115207 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41587 | /* 115212 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41588 | /* 115216 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41589 | /* 115219 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41590 | /* 115225 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41591 | /* 115227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41592 | /* 115230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41593 | /* 115232 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41594 | /* 115235 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41595 | /* 115240 */ // GIR_Coverage, 2649, |
| 41596 | /* 115240 */ GIR_EraseRootFromParent_Done, |
| 41597 | /* 115241 */ // Label 3483: @115241 |
| 41598 | /* 115241 */ GIM_Reject, |
| 41599 | /* 115242 */ // Label 3479: @115242 |
| 41600 | /* 115242 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3484*/ GIMT_Encode4(115357), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3097 // |
| 41601 | /* 115249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41602 | /* 115253 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41603 | /* 115257 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2ud:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 41604 | /* 115257 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41605 | /* 115260 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41606 | /* 115264 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41607 | /* 115269 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 41608 | /* 115271 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 41609 | /* 115274 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41610 | /* 115278 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41611 | /* 115283 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41612 | /* 115286 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41613 | /* 115290 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 41614 | /* 115293 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41615 | /* 115298 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41616 | /* 115303 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41617 | /* 115308 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41618 | /* 115311 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud), |
| 41619 | /* 115315 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41620 | /* 115320 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41621 | /* 115323 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41622 | /* 115326 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41623 | /* 115332 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41624 | /* 115334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41625 | /* 115337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41626 | /* 115339 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41627 | /* 115346 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41628 | /* 115351 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41629 | /* 115356 */ // GIR_Coverage, 3097, |
| 41630 | /* 115356 */ GIR_EraseRootFromParent_Done, |
| 41631 | /* 115357 */ // Label 3484: @115357 |
| 41632 | /* 115357 */ GIM_Reject, |
| 41633 | /* 115358 */ // Label 3472: @115358 |
| 41634 | /* 115358 */ GIM_Try, /*On fail goto*//*Label 3485*/ GIMT_Encode4(115594), |
| 41635 | /* 115363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41636 | /* 115367 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3486*/ GIMT_Encode4(115425), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2575 // |
| 41637 | /* 115374 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41638 | /* 115378 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL), |
| 41639 | /* 115382 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41640 | /* 115386 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41641 | /* 115391 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41642 | /* 115393 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41643 | /* 115393 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41644 | /* 115396 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUD), |
| 41645 | /* 115400 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41646 | /* 115405 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41647 | /* 115409 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41648 | /* 115411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41649 | /* 115414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41650 | /* 115416 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41651 | /* 115419 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41652 | /* 115424 */ // GIR_Coverage, 2575, |
| 41653 | /* 115424 */ GIR_EraseRootFromParent_Done, |
| 41654 | /* 115425 */ // Label 3486: @115425 |
| 41655 | /* 115425 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3487*/ GIMT_Encode4(115483), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2599 // |
| 41656 | /* 115432 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41657 | /* 115436 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR), |
| 41658 | /* 115440 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41659 | /* 115444 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41660 | /* 115449 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41661 | /* 115451 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41662 | /* 115451 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41663 | /* 115454 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUD), |
| 41664 | /* 115458 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41665 | /* 115463 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41666 | /* 115467 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41667 | /* 115469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41668 | /* 115472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41669 | /* 115474 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41670 | /* 115477 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41671 | /* 115482 */ // GIR_Coverage, 2599, |
| 41672 | /* 115482 */ GIR_EraseRootFromParent_Done, |
| 41673 | /* 115483 */ // Label 3487: @115483 |
| 41674 | /* 115483 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3488*/ GIMT_Encode4(115541), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2551 // |
| 41675 | /* 115490 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 41676 | /* 115494 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), |
| 41677 | /* 115498 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 41678 | /* 115502 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41679 | /* 115507 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 41680 | /* 115509 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41681 | /* 115509 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41682 | /* 115512 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUD), |
| 41683 | /* 115516 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41684 | /* 115521 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 41685 | /* 115525 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41686 | /* 115527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41687 | /* 115530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41688 | /* 115532 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41689 | /* 115535 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41690 | /* 115540 */ // GIR_Coverage, 2551, |
| 41691 | /* 115540 */ GIR_EraseRootFromParent_Done, |
| 41692 | /* 115541 */ // Label 3488: @115541 |
| 41693 | /* 115541 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3489*/ GIMT_Encode4(115593), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2643 // |
| 41694 | /* 115548 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41695 | /* 115552 */ // (fp_to_uint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 41696 | /* 115552 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41697 | /* 115555 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZD), |
| 41698 | /* 115559 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41699 | /* 115564 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41700 | /* 115568 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41701 | /* 115571 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41702 | /* 115577 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41703 | /* 115579 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41704 | /* 115582 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41705 | /* 115584 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41706 | /* 115587 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 41707 | /* 115592 */ // GIR_Coverage, 2643, |
| 41708 | /* 115592 */ GIR_EraseRootFromParent_Done, |
| 41709 | /* 115593 */ // Label 3489: @115593 |
| 41710 | /* 115593 */ GIM_Reject, |
| 41711 | /* 115594 */ // Label 3485: @115594 |
| 41712 | /* 115594 */ GIM_Reject, |
| 41713 | /* 115595 */ // Label 3473: @115595 |
| 41714 | /* 115595 */ GIM_Reject, |
| 41715 | /* 115596 */ // Label 3463: @115596 |
| 41716 | /* 115596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3490*/ GIMT_Encode4(115647), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5629 // |
| 41717 | /* 115603 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41718 | /* 115606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 41719 | /* 115610 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41720 | /* 115614 */ // (fp_to_uint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 41721 | /* 115614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r), |
| 41722 | /* 115617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 41723 | /* 115619 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 41724 | /* 115621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41725 | /* 115627 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 41726 | /* 115630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41727 | /* 115633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41728 | /* 115639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41729 | /* 115645 */ GIR_RootConstrainSelectedInstOperands, |
| 41730 | /* 115646 */ // GIR_Coverage, 5629, |
| 41731 | /* 115646 */ GIR_EraseRootFromParent_Done, |
| 41732 | /* 115647 */ // Label 3490: @115647 |
| 41733 | /* 115647 */ GIM_Reject, |
| 41734 | /* 115648 */ // Label 3464: @115648 |
| 41735 | /* 115648 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3491*/ GIMT_Encode4(115699), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5630 // |
| 41736 | /* 115655 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41737 | /* 115658 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID), |
| 41738 | /* 115662 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41739 | /* 115666 */ // (fp_to_uint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] }) |
| 41740 | /* 115666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r), |
| 41741 | /* 115669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0] |
| 41742 | /* 115671 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1 |
| 41743 | /* 115673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41744 | /* 115679 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 41745 | /* 115682 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41746 | /* 115685 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41747 | /* 115691 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41748 | /* 115697 */ GIR_RootConstrainSelectedInstOperands, |
| 41749 | /* 115698 */ // GIR_Coverage, 5630, |
| 41750 | /* 115698 */ GIR_EraseRootFromParent_Done, |
| 41751 | /* 115699 */ // Label 3491: @115699 |
| 41752 | /* 115699 */ GIM_Reject, |
| 41753 | /* 115700 */ // Label 3465: @115700 |
| 41754 | /* 115700 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3492*/ GIMT_Encode4(115736), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1775 // |
| 41755 | /* 115707 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41756 | /* 115710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41757 | /* 115714 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41758 | /* 115718 */ // (fp_to_uint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2ud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) |
| 41759 | /* 115718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2ud), |
| 41760 | /* 115721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41761 | /* 115723 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41762 | /* 115725 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41763 | /* 115728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41764 | /* 115734 */ GIR_RootConstrainSelectedInstOperands, |
| 41765 | /* 115735 */ // GIR_Coverage, 1775, |
| 41766 | /* 115735 */ GIR_EraseRootFromParent_Done, |
| 41767 | /* 115736 */ // Label 3492: @115736 |
| 41768 | /* 115736 */ GIM_Reject, |
| 41769 | /* 115737 */ // Label 3466: @115737 |
| 41770 | /* 115737 */ GIM_Try, /*On fail goto*//*Label 3493*/ GIMT_Encode4(115833), |
| 41771 | /* 115742 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41772 | /* 115745 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3494*/ GIMT_Encode4(115778), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1779 // |
| 41773 | /* 115752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41774 | /* 115756 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41775 | /* 115760 */ // (fp_to_uint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2uq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) |
| 41776 | /* 115760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2uq), |
| 41777 | /* 115763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41778 | /* 115765 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41779 | /* 115767 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41780 | /* 115770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41781 | /* 115776 */ GIR_RootConstrainSelectedInstOperands, |
| 41782 | /* 115777 */ // GIR_Coverage, 1779, |
| 41783 | /* 115777 */ GIR_EraseRootFromParent_Done, |
| 41784 | /* 115778 */ // Label 3494: @115778 |
| 41785 | /* 115778 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3495*/ GIMT_Encode4(115832), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4535 // |
| 41786 | /* 115785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41787 | /* 115789 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41788 | /* 115793 */ // (fp_to_uint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) |
| 41789 | /* 115793 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41790 | /* 115796 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41791 | /* 115800 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41792 | /* 115805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z), |
| 41793 | /* 115808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41794 | /* 115810 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41795 | /* 115812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41796 | /* 115815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41797 | /* 115821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41798 | /* 115827 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41799 | /* 115830 */ GIR_RootConstrainSelectedInstOperands, |
| 41800 | /* 115831 */ // GIR_Coverage, 4535, |
| 41801 | /* 115831 */ GIR_EraseRootFromParent_Done, |
| 41802 | /* 115832 */ // Label 3495: @115832 |
| 41803 | /* 115832 */ GIM_Reject, |
| 41804 | /* 115833 */ // Label 3493: @115833 |
| 41805 | /* 115833 */ GIM_Reject, |
| 41806 | /* 115834 */ // Label 3467: @115834 |
| 41807 | /* 115834 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3496*/ GIMT_Encode4(115870), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1767 // |
| 41808 | /* 115841 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 41809 | /* 115844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41810 | /* 115848 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41811 | /* 115852 */ // (fp_to_uint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2ud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) |
| 41812 | /* 115852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud), |
| 41813 | /* 115855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41814 | /* 115857 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41815 | /* 115859 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41816 | /* 115862 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41817 | /* 115868 */ GIR_RootConstrainSelectedInstOperands, |
| 41818 | /* 115869 */ // GIR_Coverage, 1767, |
| 41819 | /* 115869 */ GIR_EraseRootFromParent_Done, |
| 41820 | /* 115870 */ // Label 3496: @115870 |
| 41821 | /* 115870 */ GIM_Reject, |
| 41822 | /* 115871 */ // Label 3468: @115871 |
| 41823 | /* 115871 */ GIM_Try, /*On fail goto*//*Label 3497*/ GIMT_Encode4(115967), |
| 41824 | /* 115876 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 41825 | /* 115879 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3498*/ GIMT_Encode4(115912), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1771 // |
| 41826 | /* 115886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41827 | /* 115890 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41828 | /* 115894 */ // (fp_to_uint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2uq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) |
| 41829 | /* 115894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2uq), |
| 41830 | /* 115897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41831 | /* 115899 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41832 | /* 115901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41833 | /* 115904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41834 | /* 115910 */ GIR_RootConstrainSelectedInstOperands, |
| 41835 | /* 115911 */ // GIR_Coverage, 1771, |
| 41836 | /* 115911 */ GIR_EraseRootFromParent_Done, |
| 41837 | /* 115912 */ // Label 3498: @115912 |
| 41838 | /* 115912 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3499*/ GIMT_Encode4(115966), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4541 // |
| 41839 | /* 115919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41840 | /* 115923 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 41841 | /* 115927 */ // (fp_to_uint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) |
| 41842 | /* 115927 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 41843 | /* 115930 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41844 | /* 115934 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41845 | /* 115939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z), |
| 41846 | /* 115942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 41847 | /* 115944 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 41848 | /* 115946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41849 | /* 115949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41850 | /* 115955 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41851 | /* 115961 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41852 | /* 115964 */ GIR_RootConstrainSelectedInstOperands, |
| 41853 | /* 115965 */ // GIR_Coverage, 4541, |
| 41854 | /* 115965 */ GIR_EraseRootFromParent_Done, |
| 41855 | /* 115966 */ // Label 3499: @115966 |
| 41856 | /* 115966 */ GIM_Reject, |
| 41857 | /* 115967 */ // Label 3497: @115967 |
| 41858 | /* 115967 */ GIM_Reject, |
| 41859 | /* 115968 */ // Label 3469: @115968 |
| 41860 | /* 115968 */ GIM_Reject, |
| 41861 | /* 115969 */ // Label 50: @115969 |
| 41862 | /* 115969 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3507*/ GIMT_Encode4(116610), |
| 41863 | /* 115980 */ /*GILLT_s16*//*Label 3500*/ GIMT_Encode4(116032), |
| 41864 | /* 115984 */ /*GILLT_s32*//*Label 3501*/ GIMT_Encode4(116091), |
| 41865 | /* 115988 */ /*GILLT_s64*//*Label 3502*/ GIMT_Encode4(116283), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41866 | /* 116016 */ /*GILLT_v4s16*//*Label 3503*/ GIMT_Encode4(116342), |
| 41867 | /* 116020 */ /*GILLT_v8s16*//*Label 3504*/ GIMT_Encode4(116379), |
| 41868 | /* 116024 */ /*GILLT_v2s32*//*Label 3505*/ GIMT_Encode4(116476), |
| 41869 | /* 116028 */ /*GILLT_v4s32*//*Label 3506*/ GIMT_Encode4(116513), |
| 41870 | /* 116032 */ // Label 3500: @116032 |
| 41871 | /* 116032 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3508*/ GIMT_Encode4(116090), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2616 // |
| 41872 | /* 116039 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41873 | /* 116042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 41874 | /* 116046 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41875 | /* 116050 */ // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VSITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 41876 | /* 116050 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41877 | /* 116053 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41878 | /* 116057 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41879 | /* 116062 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41880 | /* 116066 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41881 | /* 116071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOH), |
| 41882 | /* 116074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 41883 | /* 116076 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41884 | /* 116079 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41885 | /* 116082 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41886 | /* 116088 */ GIR_RootConstrainSelectedInstOperands, |
| 41887 | /* 116089 */ // GIR_Coverage, 2616, |
| 41888 | /* 116089 */ GIR_EraseRootFromParent_Done, |
| 41889 | /* 116090 */ // Label 3508: @116090 |
| 41890 | /* 116090 */ GIM_Reject, |
| 41891 | /* 116091 */ // Label 3501: @116091 |
| 41892 | /* 116091 */ GIM_Try, /*On fail goto*//*Label 3509*/ GIMT_Encode4(116282), |
| 41893 | /* 116096 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41894 | /* 116099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 41895 | /* 116103 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41896 | /* 116107 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3510*/ GIMT_Encode4(116154), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2612 // |
| 41897 | /* 116114 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VSITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 41898 | /* 116114 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41899 | /* 116117 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41900 | /* 116121 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41901 | /* 116126 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41902 | /* 116130 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41903 | /* 116135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOS), |
| 41904 | /* 116138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 41905 | /* 116140 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41906 | /* 116143 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41907 | /* 116146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41908 | /* 116152 */ GIR_RootConstrainSelectedInstOperands, |
| 41909 | /* 116153 */ // GIR_Coverage, 2612, |
| 41910 | /* 116153 */ GIR_EraseRootFromParent_Done, |
| 41911 | /* 116154 */ // Label 3510: @116154 |
| 41912 | /* 116154 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3511*/ GIMT_Encode4(116281), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3098 // |
| 41913 | /* 116161 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTs2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 41914 | /* 116161 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 41915 | /* 116164 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41916 | /* 116168 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41917 | /* 116173 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41918 | /* 116177 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41919 | /* 116182 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 41920 | /* 116185 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 41921 | /* 116189 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41922 | /* 116194 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 41923 | /* 116196 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 41924 | /* 116199 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 41925 | /* 116203 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41926 | /* 116208 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 41927 | /* 116211 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 41928 | /* 116214 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 41929 | /* 116217 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41930 | /* 116222 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41931 | /* 116227 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 41932 | /* 116232 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 41933 | /* 116235 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd), |
| 41934 | /* 116239 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41935 | /* 116244 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 41936 | /* 116247 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 41937 | /* 116250 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41938 | /* 116256 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 41939 | /* 116258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41940 | /* 116261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 41941 | /* 116263 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 41942 | /* 116270 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41943 | /* 116275 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 41944 | /* 116280 */ // GIR_Coverage, 3098, |
| 41945 | /* 116280 */ GIR_EraseRootFromParent_Done, |
| 41946 | /* 116281 */ // Label 3511: @116281 |
| 41947 | /* 116281 */ GIM_Reject, |
| 41948 | /* 116282 */ // Label 3509: @116282 |
| 41949 | /* 116282 */ GIM_Reject, |
| 41950 | /* 116283 */ // Label 3502: @116283 |
| 41951 | /* 116283 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3512*/ GIMT_Encode4(116341), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2608 // |
| 41952 | /* 116290 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 41953 | /* 116293 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41954 | /* 116297 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 41955 | /* 116301 */ // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VSITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 41956 | /* 116301 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41957 | /* 116304 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41958 | /* 116308 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 41959 | /* 116313 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 41960 | /* 116317 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 41961 | /* 116322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOD), |
| 41962 | /* 116325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 41963 | /* 116327 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41964 | /* 116330 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41965 | /* 116333 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41966 | /* 116339 */ GIR_RootConstrainSelectedInstOperands, |
| 41967 | /* 116340 */ // GIR_Coverage, 2608, |
| 41968 | /* 116340 */ GIR_EraseRootFromParent_Done, |
| 41969 | /* 116341 */ // Label 3512: @116341 |
| 41970 | /* 116341 */ GIM_Reject, |
| 41971 | /* 116342 */ // Label 3503: @116342 |
| 41972 | /* 116342 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3513*/ GIMT_Encode4(116378), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1776 // |
| 41973 | /* 116349 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 41974 | /* 116352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41975 | /* 116356 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 41976 | /* 116360 */ // (sint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) |
| 41977 | /* 116360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hd), |
| 41978 | /* 116363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41979 | /* 116365 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41980 | /* 116367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41981 | /* 116370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41982 | /* 116376 */ GIR_RootConstrainSelectedInstOperands, |
| 41983 | /* 116377 */ // GIR_Coverage, 1776, |
| 41984 | /* 116377 */ GIR_EraseRootFromParent_Done, |
| 41985 | /* 116378 */ // Label 3513: @116378 |
| 41986 | /* 116378 */ GIM_Reject, |
| 41987 | /* 116379 */ // Label 3504: @116379 |
| 41988 | /* 116379 */ GIM_Try, /*On fail goto*//*Label 3514*/ GIMT_Encode4(116475), |
| 41989 | /* 116384 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 41990 | /* 116387 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3515*/ GIMT_Encode4(116420), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1780 // |
| 41991 | /* 116394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41992 | /* 116398 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 41993 | /* 116402 */ // (sint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) |
| 41994 | /* 116402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hq), |
| 41995 | /* 116405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 41996 | /* 116407 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 41997 | /* 116409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 41998 | /* 116412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 41999 | /* 116418 */ GIR_RootConstrainSelectedInstOperands, |
| 42000 | /* 116419 */ // GIR_Coverage, 1780, |
| 42001 | /* 116419 */ GIR_EraseRootFromParent_Done, |
| 42002 | /* 116420 */ // Label 3515: @116420 |
| 42003 | /* 116420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3516*/ GIMT_Encode4(116474), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4544 // |
| 42004 | /* 116427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42005 | /* 116431 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42006 | /* 116435 */ // (sint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 42007 | /* 116435 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42008 | /* 116438 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42009 | /* 116442 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42010 | /* 116447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n), |
| 42011 | /* 116450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42012 | /* 116452 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42013 | /* 116454 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42014 | /* 116457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42015 | /* 116463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42016 | /* 116469 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42017 | /* 116472 */ GIR_RootConstrainSelectedInstOperands, |
| 42018 | /* 116473 */ // GIR_Coverage, 4544, |
| 42019 | /* 116473 */ GIR_EraseRootFromParent_Done, |
| 42020 | /* 116474 */ // Label 3516: @116474 |
| 42021 | /* 116474 */ GIM_Reject, |
| 42022 | /* 116475 */ // Label 3514: @116475 |
| 42023 | /* 116475 */ GIM_Reject, |
| 42024 | /* 116476 */ // Label 3505: @116476 |
| 42025 | /* 116476 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3517*/ GIMT_Encode4(116512), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1768 // |
| 42026 | /* 116483 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42027 | /* 116486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42028 | /* 116490 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42029 | /* 116494 */ // (sint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) |
| 42030 | /* 116494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd), |
| 42031 | /* 116497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42032 | /* 116499 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42033 | /* 116501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42034 | /* 116504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42035 | /* 116510 */ GIR_RootConstrainSelectedInstOperands, |
| 42036 | /* 116511 */ // GIR_Coverage, 1768, |
| 42037 | /* 116511 */ GIR_EraseRootFromParent_Done, |
| 42038 | /* 116512 */ // Label 3517: @116512 |
| 42039 | /* 116512 */ GIM_Reject, |
| 42040 | /* 116513 */ // Label 3506: @116513 |
| 42041 | /* 116513 */ GIM_Try, /*On fail goto*//*Label 3518*/ GIMT_Encode4(116609), |
| 42042 | /* 116518 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42043 | /* 116521 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3519*/ GIMT_Encode4(116554), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1772 // |
| 42044 | /* 116528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42045 | /* 116532 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42046 | /* 116536 */ // (sint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) |
| 42047 | /* 116536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fq), |
| 42048 | /* 116539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42049 | /* 116541 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42050 | /* 116543 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42051 | /* 116546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42052 | /* 116552 */ GIR_RootConstrainSelectedInstOperands, |
| 42053 | /* 116553 */ // GIR_Coverage, 1772, |
| 42054 | /* 116553 */ GIR_EraseRootFromParent_Done, |
| 42055 | /* 116554 */ // Label 3519: @116554 |
| 42056 | /* 116554 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3520*/ GIMT_Encode4(116608), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4550 // |
| 42057 | /* 116561 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42058 | /* 116565 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42059 | /* 116569 */ // (sint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 42060 | /* 116569 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42061 | /* 116572 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42062 | /* 116576 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42063 | /* 116581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n), |
| 42064 | /* 116584 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42065 | /* 116586 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42066 | /* 116588 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42067 | /* 116591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42068 | /* 116597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42069 | /* 116603 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42070 | /* 116606 */ GIR_RootConstrainSelectedInstOperands, |
| 42071 | /* 116607 */ // GIR_Coverage, 4550, |
| 42072 | /* 116607 */ GIR_EraseRootFromParent_Done, |
| 42073 | /* 116608 */ // Label 3520: @116608 |
| 42074 | /* 116608 */ GIM_Reject, |
| 42075 | /* 116609 */ // Label 3518: @116609 |
| 42076 | /* 116609 */ GIM_Reject, |
| 42077 | /* 116610 */ // Label 3507: @116610 |
| 42078 | /* 116610 */ GIM_Reject, |
| 42079 | /* 116611 */ // Label 51: @116611 |
| 42080 | /* 116611 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3528*/ GIMT_Encode4(117252), |
| 42081 | /* 116622 */ /*GILLT_s16*//*Label 3521*/ GIMT_Encode4(116674), |
| 42082 | /* 116626 */ /*GILLT_s32*//*Label 3522*/ GIMT_Encode4(116733), |
| 42083 | /* 116630 */ /*GILLT_s64*//*Label 3523*/ GIMT_Encode4(116925), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42084 | /* 116658 */ /*GILLT_v4s16*//*Label 3524*/ GIMT_Encode4(116984), |
| 42085 | /* 116662 */ /*GILLT_v8s16*//*Label 3525*/ GIMT_Encode4(117021), |
| 42086 | /* 116666 */ /*GILLT_v2s32*//*Label 3526*/ GIMT_Encode4(117118), |
| 42087 | /* 116670 */ /*GILLT_v4s32*//*Label 3527*/ GIMT_Encode4(117155), |
| 42088 | /* 116674 */ // Label 3521: @116674 |
| 42089 | /* 116674 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3529*/ GIMT_Encode4(116732), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2626 // |
| 42090 | /* 116681 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42091 | /* 116684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42092 | /* 116688 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42093 | /* 116692 */ // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VUITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 42094 | /* 116692 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42095 | /* 116695 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42096 | /* 116699 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42097 | /* 116704 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42098 | /* 116708 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42099 | /* 116713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOH), |
| 42100 | /* 116716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42101 | /* 116718 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42102 | /* 116721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42103 | /* 116724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42104 | /* 116730 */ GIR_RootConstrainSelectedInstOperands, |
| 42105 | /* 116731 */ // GIR_Coverage, 2626, |
| 42106 | /* 116731 */ GIR_EraseRootFromParent_Done, |
| 42107 | /* 116732 */ // Label 3529: @116732 |
| 42108 | /* 116732 */ GIM_Reject, |
| 42109 | /* 116733 */ // Label 3522: @116733 |
| 42110 | /* 116733 */ GIM_Try, /*On fail goto*//*Label 3530*/ GIMT_Encode4(116924), |
| 42111 | /* 116738 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42112 | /* 116741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42113 | /* 116745 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42114 | /* 116749 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3531*/ GIMT_Encode4(116796), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2622 // |
| 42115 | /* 116756 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VUITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 42116 | /* 116756 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42117 | /* 116759 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42118 | /* 116763 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42119 | /* 116768 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42120 | /* 116772 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42121 | /* 116777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOS), |
| 42122 | /* 116780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42123 | /* 116782 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42124 | /* 116785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42125 | /* 116788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42126 | /* 116794 */ GIR_RootConstrainSelectedInstOperands, |
| 42127 | /* 116795 */ // GIR_Coverage, 2622, |
| 42128 | /* 116795 */ GIR_EraseRootFromParent_Done, |
| 42129 | /* 116796 */ // Label 3531: @116796 |
| 42130 | /* 116796 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3532*/ GIMT_Encode4(116923), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3099 // |
| 42131 | /* 116803 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTu2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }) |
| 42132 | /* 116803 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 42133 | /* 116806 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42134 | /* 116810 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42135 | /* 116815 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42136 | /* 116819 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42137 | /* 116824 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 42138 | /* 116827 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42139 | /* 116831 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42140 | /* 116836 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 42141 | /* 116838 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32, |
| 42142 | /* 116841 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42143 | /* 116845 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42144 | /* 116850 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 42145 | /* 116853 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 42146 | /* 116856 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17, |
| 42147 | /* 116859 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42148 | /* 116864 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42149 | /* 116869 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 42150 | /* 116874 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 42151 | /* 116877 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd), |
| 42152 | /* 116881 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42153 | /* 116886 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 42154 | /* 116889 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42155 | /* 116892 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42156 | /* 116898 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42157 | /* 116900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42158 | /* 116903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42159 | /* 116905 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 42160 | /* 116912 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42161 | /* 116917 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42162 | /* 116922 */ // GIR_Coverage, 3099, |
| 42163 | /* 116922 */ GIR_EraseRootFromParent_Done, |
| 42164 | /* 116923 */ // Label 3532: @116923 |
| 42165 | /* 116923 */ GIM_Reject, |
| 42166 | /* 116924 */ // Label 3530: @116924 |
| 42167 | /* 116924 */ GIM_Reject, |
| 42168 | /* 116925 */ // Label 3523: @116925 |
| 42169 | /* 116925 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3533*/ GIMT_Encode4(116983), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2618 // |
| 42170 | /* 116932 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42171 | /* 116935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42172 | /* 116939 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42173 | /* 116943 */ // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VUITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] })) |
| 42174 | /* 116943 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42175 | /* 116946 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42176 | /* 116950 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42177 | /* 116955 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42178 | /* 116959 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42179 | /* 116964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOD), |
| 42180 | /* 116967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42181 | /* 116969 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42182 | /* 116972 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42183 | /* 116975 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42184 | /* 116981 */ GIR_RootConstrainSelectedInstOperands, |
| 42185 | /* 116982 */ // GIR_Coverage, 2618, |
| 42186 | /* 116982 */ GIR_EraseRootFromParent_Done, |
| 42187 | /* 116983 */ // Label 3533: @116983 |
| 42188 | /* 116983 */ GIM_Reject, |
| 42189 | /* 116984 */ // Label 3524: @116984 |
| 42190 | /* 116984 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3534*/ GIMT_Encode4(117020), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1777 // |
| 42191 | /* 116991 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42192 | /* 116994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42193 | /* 116998 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42194 | /* 117002 */ // (uint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) |
| 42195 | /* 117002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hd), |
| 42196 | /* 117005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42197 | /* 117007 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42198 | /* 117009 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42199 | /* 117012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42200 | /* 117018 */ GIR_RootConstrainSelectedInstOperands, |
| 42201 | /* 117019 */ // GIR_Coverage, 1777, |
| 42202 | /* 117019 */ GIR_EraseRootFromParent_Done, |
| 42203 | /* 117020 */ // Label 3534: @117020 |
| 42204 | /* 117020 */ GIM_Reject, |
| 42205 | /* 117021 */ // Label 3525: @117021 |
| 42206 | /* 117021 */ GIM_Try, /*On fail goto*//*Label 3535*/ GIMT_Encode4(117117), |
| 42207 | /* 117026 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42208 | /* 117029 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3536*/ GIMT_Encode4(117062), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1781 // |
| 42209 | /* 117036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42210 | /* 117040 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42211 | /* 117044 */ // (uint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) |
| 42212 | /* 117044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hq), |
| 42213 | /* 117047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42214 | /* 117049 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42215 | /* 117051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42216 | /* 117054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42217 | /* 117060 */ GIR_RootConstrainSelectedInstOperands, |
| 42218 | /* 117061 */ // GIR_Coverage, 1781, |
| 42219 | /* 117061 */ GIR_EraseRootFromParent_Done, |
| 42220 | /* 117062 */ // Label 3536: @117062 |
| 42221 | /* 117062 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3537*/ GIMT_Encode4(117116), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4547 // |
| 42222 | /* 117069 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42223 | /* 117073 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42224 | /* 117077 */ // (uint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) |
| 42225 | /* 117077 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42226 | /* 117080 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42227 | /* 117084 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42228 | /* 117089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n), |
| 42229 | /* 117092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42230 | /* 117094 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42231 | /* 117096 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42232 | /* 117099 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42233 | /* 117105 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42234 | /* 117111 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42235 | /* 117114 */ GIR_RootConstrainSelectedInstOperands, |
| 42236 | /* 117115 */ // GIR_Coverage, 4547, |
| 42237 | /* 117115 */ GIR_EraseRootFromParent_Done, |
| 42238 | /* 117116 */ // Label 3537: @117116 |
| 42239 | /* 117116 */ GIM_Reject, |
| 42240 | /* 117117 */ // Label 3535: @117117 |
| 42241 | /* 117117 */ GIM_Reject, |
| 42242 | /* 117118 */ // Label 3526: @117118 |
| 42243 | /* 117118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3538*/ GIMT_Encode4(117154), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1769 // |
| 42244 | /* 117125 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42245 | /* 117128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42246 | /* 117132 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42247 | /* 117136 */ // (uint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) |
| 42248 | /* 117136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd), |
| 42249 | /* 117139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42250 | /* 117141 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42251 | /* 117143 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42252 | /* 117146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42253 | /* 117152 */ GIR_RootConstrainSelectedInstOperands, |
| 42254 | /* 117153 */ // GIR_Coverage, 1769, |
| 42255 | /* 117153 */ GIR_EraseRootFromParent_Done, |
| 42256 | /* 117154 */ // Label 3538: @117154 |
| 42257 | /* 117154 */ GIM_Reject, |
| 42258 | /* 117155 */ // Label 3527: @117155 |
| 42259 | /* 117155 */ GIM_Try, /*On fail goto*//*Label 3539*/ GIMT_Encode4(117251), |
| 42260 | /* 117160 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42261 | /* 117163 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3540*/ GIMT_Encode4(117196), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1773 // |
| 42262 | /* 117170 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42263 | /* 117174 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42264 | /* 117178 */ // (uint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) |
| 42265 | /* 117178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fq), |
| 42266 | /* 117181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42267 | /* 117183 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42268 | /* 117185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42269 | /* 117188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42270 | /* 117194 */ GIR_RootConstrainSelectedInstOperands, |
| 42271 | /* 117195 */ // GIR_Coverage, 1773, |
| 42272 | /* 117195 */ GIR_EraseRootFromParent_Done, |
| 42273 | /* 117196 */ // Label 3540: @117196 |
| 42274 | /* 117196 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3541*/ GIMT_Encode4(117250), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4553 // |
| 42275 | /* 117203 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42276 | /* 117207 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42277 | /* 117211 */ // (uint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) |
| 42278 | /* 117211 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42279 | /* 117214 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42280 | /* 117218 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42281 | /* 117223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n), |
| 42282 | /* 117226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42283 | /* 117228 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42284 | /* 117230 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42285 | /* 117233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42286 | /* 117239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42287 | /* 117245 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42288 | /* 117248 */ GIR_RootConstrainSelectedInstOperands, |
| 42289 | /* 117249 */ // GIR_Coverage, 4553, |
| 42290 | /* 117249 */ GIR_EraseRootFromParent_Done, |
| 42291 | /* 117250 */ // Label 3541: @117250 |
| 42292 | /* 117250 */ GIM_Reject, |
| 42293 | /* 117251 */ // Label 3539: @117251 |
| 42294 | /* 117251 */ GIM_Reject, |
| 42295 | /* 117252 */ // Label 3528: @117252 |
| 42296 | /* 117252 */ GIM_Reject, |
| 42297 | /* 117253 */ // Label 52: @117253 |
| 42298 | /* 117253 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3545*/ GIMT_Encode4(117615), |
| 42299 | /* 117264 */ /*GILLT_s32*//*Label 3542*/ GIMT_Encode4(117312), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42300 | /* 117300 */ /*GILLT_v8s16*//*Label 3543*/ GIMT_Encode4(117507), GIMT_Encode4(0), |
| 42301 | /* 117308 */ /*GILLT_v4s32*//*Label 3544*/ GIMT_Encode4(117561), |
| 42302 | /* 117312 */ // Label 3542: @117312 |
| 42303 | /* 117312 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3549*/ GIMT_Encode4(117506), |
| 42304 | /* 117323 */ /*GILLT_s16*//*Label 3546*/ GIMT_Encode4(117335), |
| 42305 | /* 117327 */ /*GILLT_s32*//*Label 3547*/ GIMT_Encode4(117392), |
| 42306 | /* 117331 */ /*GILLT_s64*//*Label 3548*/ GIMT_Encode4(117449), |
| 42307 | /* 117335 */ // Label 3546: @117335 |
| 42308 | /* 117335 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3550*/ GIMT_Encode4(117391), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2641 // |
| 42309 | /* 117342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42310 | /* 117346 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42311 | /* 117350 */ // (fp_to_sint_sat:{ *:[i32] } HPR:{ *:[f16] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 42312 | /* 117350 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42313 | /* 117353 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZH), |
| 42314 | /* 117357 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42315 | /* 117362 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42316 | /* 117366 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42317 | /* 117369 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42318 | /* 117375 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42319 | /* 117377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42320 | /* 117380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42321 | /* 117382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42322 | /* 117385 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 42323 | /* 117390 */ // GIR_Coverage, 2641, |
| 42324 | /* 117390 */ GIR_EraseRootFromParent_Done, |
| 42325 | /* 117391 */ // Label 3550: @117391 |
| 42326 | /* 117391 */ GIM_Reject, |
| 42327 | /* 117392 */ // Label 3547: @117392 |
| 42328 | /* 117392 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3551*/ GIMT_Encode4(117448), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2635 // |
| 42329 | /* 117399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42330 | /* 117403 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42331 | /* 117407 */ // (fp_to_sint_sat:{ *:[i32] } SPR:{ *:[f32] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 42332 | /* 117407 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42333 | /* 117410 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZS), |
| 42334 | /* 117414 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42335 | /* 117419 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42336 | /* 117423 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42337 | /* 117426 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42338 | /* 117432 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42339 | /* 117434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42340 | /* 117437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42341 | /* 117439 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42342 | /* 117442 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 42343 | /* 117447 */ // GIR_Coverage, 2635, |
| 42344 | /* 117447 */ GIR_EraseRootFromParent_Done, |
| 42345 | /* 117448 */ // Label 3551: @117448 |
| 42346 | /* 117448 */ GIM_Reject, |
| 42347 | /* 117449 */ // Label 3548: @117449 |
| 42348 | /* 117449 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3552*/ GIMT_Encode4(117505), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2629 // |
| 42349 | /* 117456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42350 | /* 117460 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42351 | /* 117464 */ // (fp_to_sint_sat:{ *:[i32] } DPR:{ *:[f64] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 42352 | /* 117464 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42353 | /* 117467 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZD), |
| 42354 | /* 117471 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42355 | /* 117476 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42356 | /* 117480 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42357 | /* 117483 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42358 | /* 117489 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42359 | /* 117491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42360 | /* 117494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42361 | /* 117496 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42362 | /* 117499 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 42363 | /* 117504 */ // GIR_Coverage, 2629, |
| 42364 | /* 117504 */ GIR_EraseRootFromParent_Done, |
| 42365 | /* 117505 */ // Label 3552: @117505 |
| 42366 | /* 117505 */ GIM_Reject, |
| 42367 | /* 117506 */ // Label 3549: @117506 |
| 42368 | /* 117506 */ GIM_Reject, |
| 42369 | /* 117507 */ // Label 3543: @117507 |
| 42370 | /* 117507 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3553*/ GIMT_Encode4(117560), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4558 // |
| 42371 | /* 117514 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42372 | /* 117517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42373 | /* 117521 */ // (fp_to_sint_sat:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, i16:{ *:[Other] }) => (MVE_VCVTs16f16z:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) |
| 42374 | /* 117521 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42375 | /* 117524 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42376 | /* 117528 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42377 | /* 117533 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z), |
| 42378 | /* 117536 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42379 | /* 117538 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42380 | /* 117540 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42381 | /* 117543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42382 | /* 117549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42383 | /* 117555 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42384 | /* 117558 */ GIR_RootConstrainSelectedInstOperands, |
| 42385 | /* 117559 */ // GIR_Coverage, 4558, |
| 42386 | /* 117559 */ GIR_EraseRootFromParent_Done, |
| 42387 | /* 117560 */ // Label 3553: @117560 |
| 42388 | /* 117560 */ GIM_Reject, |
| 42389 | /* 117561 */ // Label 3544: @117561 |
| 42390 | /* 117561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3554*/ GIMT_Encode4(117614), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4556 // |
| 42391 | /* 117568 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42392 | /* 117571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42393 | /* 117575 */ // (fp_to_sint_sat:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, i32:{ *:[Other] }) => (MVE_VCVTs32f32z:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) |
| 42394 | /* 117575 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42395 | /* 117578 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42396 | /* 117582 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42397 | /* 117587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z), |
| 42398 | /* 117590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42399 | /* 117592 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42400 | /* 117594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42401 | /* 117597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42402 | /* 117603 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42403 | /* 117609 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42404 | /* 117612 */ GIR_RootConstrainSelectedInstOperands, |
| 42405 | /* 117613 */ // GIR_Coverage, 4556, |
| 42406 | /* 117613 */ GIR_EraseRootFromParent_Done, |
| 42407 | /* 117614 */ // Label 3554: @117614 |
| 42408 | /* 117614 */ GIM_Reject, |
| 42409 | /* 117615 */ // Label 3545: @117615 |
| 42410 | /* 117615 */ GIM_Reject, |
| 42411 | /* 117616 */ // Label 53: @117616 |
| 42412 | /* 117616 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3558*/ GIMT_Encode4(117978), |
| 42413 | /* 117627 */ /*GILLT_s32*//*Label 3555*/ GIMT_Encode4(117675), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42414 | /* 117663 */ /*GILLT_v8s16*//*Label 3556*/ GIMT_Encode4(117870), GIMT_Encode4(0), |
| 42415 | /* 117671 */ /*GILLT_v4s32*//*Label 3557*/ GIMT_Encode4(117924), |
| 42416 | /* 117675 */ // Label 3555: @117675 |
| 42417 | /* 117675 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3562*/ GIMT_Encode4(117869), |
| 42418 | /* 117686 */ /*GILLT_s16*//*Label 3559*/ GIMT_Encode4(117698), |
| 42419 | /* 117690 */ /*GILLT_s32*//*Label 3560*/ GIMT_Encode4(117755), |
| 42420 | /* 117694 */ /*GILLT_s64*//*Label 3561*/ GIMT_Encode4(117812), |
| 42421 | /* 117698 */ // Label 3559: @117698 |
| 42422 | /* 117698 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3563*/ GIMT_Encode4(117754), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2656 // |
| 42423 | /* 117705 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42424 | /* 117709 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42425 | /* 117713 */ // (fp_to_uint_sat:{ *:[i32] } HPR:{ *:[f16] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] }) |
| 42426 | /* 117713 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42427 | /* 117716 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZH), |
| 42428 | /* 117720 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42429 | /* 117725 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42430 | /* 117729 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42431 | /* 117732 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42432 | /* 117738 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42433 | /* 117740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42434 | /* 117743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42435 | /* 117745 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42436 | /* 117748 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 42437 | /* 117753 */ // GIR_Coverage, 2656, |
| 42438 | /* 117753 */ GIR_EraseRootFromParent_Done, |
| 42439 | /* 117754 */ // Label 3563: @117754 |
| 42440 | /* 117754 */ GIM_Reject, |
| 42441 | /* 117755 */ // Label 3560: @117755 |
| 42442 | /* 117755 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3564*/ GIMT_Encode4(117811), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2650 // |
| 42443 | /* 117762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42444 | /* 117766 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42445 | /* 117770 */ // (fp_to_uint_sat:{ *:[i32] } SPR:{ *:[f32] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] }) |
| 42446 | /* 117770 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42447 | /* 117773 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZS), |
| 42448 | /* 117777 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42449 | /* 117782 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42450 | /* 117786 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42451 | /* 117789 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42452 | /* 117795 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42453 | /* 117797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42454 | /* 117800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42455 | /* 117802 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42456 | /* 117805 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 42457 | /* 117810 */ // GIR_Coverage, 2650, |
| 42458 | /* 117810 */ GIR_EraseRootFromParent_Done, |
| 42459 | /* 117811 */ // Label 3564: @117811 |
| 42460 | /* 117811 */ GIM_Reject, |
| 42461 | /* 117812 */ // Label 3561: @117812 |
| 42462 | /* 117812 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3565*/ GIMT_Encode4(117868), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2644 // |
| 42463 | /* 117819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 42464 | /* 117823 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42465 | /* 117827 */ // (fp_to_uint_sat:{ *:[i32] } DPR:{ *:[f64] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] }) |
| 42466 | /* 117827 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42467 | /* 117830 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZD), |
| 42468 | /* 117834 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42469 | /* 117839 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42470 | /* 117843 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 42471 | /* 117846 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42472 | /* 117852 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 42473 | /* 117854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42474 | /* 117857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42475 | /* 117859 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42476 | /* 117862 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID), |
| 42477 | /* 117867 */ // GIR_Coverage, 2644, |
| 42478 | /* 117867 */ GIR_EraseRootFromParent_Done, |
| 42479 | /* 117868 */ // Label 3565: @117868 |
| 42480 | /* 117868 */ GIM_Reject, |
| 42481 | /* 117869 */ // Label 3562: @117869 |
| 42482 | /* 117869 */ GIM_Reject, |
| 42483 | /* 117870 */ // Label 3556: @117870 |
| 42484 | /* 117870 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3566*/ GIMT_Encode4(117923), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4559 // |
| 42485 | /* 117877 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42486 | /* 117880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42487 | /* 117884 */ // (fp_to_uint_sat:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, i16:{ *:[Other] }) => (MVE_VCVTu16f16z:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src) |
| 42488 | /* 117884 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42489 | /* 117887 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42490 | /* 117891 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42491 | /* 117896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z), |
| 42492 | /* 117899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42493 | /* 117901 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42494 | /* 117903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42495 | /* 117906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42496 | /* 117912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42497 | /* 117918 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42498 | /* 117921 */ GIR_RootConstrainSelectedInstOperands, |
| 42499 | /* 117922 */ // GIR_Coverage, 4559, |
| 42500 | /* 117922 */ GIR_EraseRootFromParent_Done, |
| 42501 | /* 117923 */ // Label 3566: @117923 |
| 42502 | /* 117923 */ GIM_Reject, |
| 42503 | /* 117924 */ // Label 3557: @117924 |
| 42504 | /* 117924 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3567*/ GIMT_Encode4(117977), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4557 // |
| 42505 | /* 117931 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42506 | /* 117934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42507 | /* 117938 */ // (fp_to_uint_sat:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, i32:{ *:[Other] }) => (MVE_VCVTu32f32z:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src) |
| 42508 | /* 117938 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42509 | /* 117941 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42510 | /* 117945 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42511 | /* 117950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z), |
| 42512 | /* 117953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42513 | /* 117955 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 42514 | /* 117957 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42515 | /* 117960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42516 | /* 117966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42517 | /* 117972 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42518 | /* 117975 */ GIR_RootConstrainSelectedInstOperands, |
| 42519 | /* 117976 */ // GIR_Coverage, 4557, |
| 42520 | /* 117976 */ GIR_EraseRootFromParent_Done, |
| 42521 | /* 117977 */ // Label 3567: @117977 |
| 42522 | /* 117977 */ GIM_Reject, |
| 42523 | /* 117978 */ // Label 3558: @117978 |
| 42524 | /* 117978 */ GIM_Reject, |
| 42525 | /* 117979 */ // Label 54: @117979 |
| 42526 | /* 117979 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3575*/ GIMT_Encode4(118742), |
| 42527 | /* 117990 */ /*GILLT_s16*//*Label 3568*/ GIMT_Encode4(118042), |
| 42528 | /* 117994 */ /*GILLT_s32*//*Label 3569*/ GIMT_Encode4(118079), |
| 42529 | /* 117998 */ /*GILLT_s64*//*Label 3570*/ GIMT_Encode4(118269), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42530 | /* 118026 */ /*GILLT_v4s16*//*Label 3571*/ GIMT_Encode4(118306), |
| 42531 | /* 118030 */ /*GILLT_v8s16*//*Label 3572*/ GIMT_Encode4(118343), |
| 42532 | /* 118034 */ /*GILLT_v2s32*//*Label 3573*/ GIMT_Encode4(118524), |
| 42533 | /* 118038 */ /*GILLT_v4s32*//*Label 3574*/ GIMT_Encode4(118561), |
| 42534 | /* 118042 */ // Label 3568: @118042 |
| 42535 | /* 118042 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3576*/ GIMT_Encode4(118078), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 678 // |
| 42536 | /* 118049 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 42537 | /* 118052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42538 | /* 118056 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42539 | /* 118060 */ // (fabs:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VABSH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 42540 | /* 118060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSH), |
| 42541 | /* 118063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42542 | /* 118065 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 42543 | /* 118067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42544 | /* 118070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42545 | /* 118076 */ GIR_RootConstrainSelectedInstOperands, |
| 42546 | /* 118077 */ // GIR_Coverage, 678, |
| 42547 | /* 118077 */ GIR_EraseRootFromParent_Done, |
| 42548 | /* 118078 */ // Label 3576: @118078 |
| 42549 | /* 118078 */ GIM_Reject, |
| 42550 | /* 118079 */ // Label 3569: @118079 |
| 42551 | /* 118079 */ GIM_Try, /*On fail goto*//*Label 3577*/ GIMT_Encode4(118268), |
| 42552 | /* 118084 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42553 | /* 118087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42554 | /* 118091 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42555 | /* 118095 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3578*/ GIMT_Encode4(118120), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 677 // |
| 42556 | /* 118102 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VABSS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 42557 | /* 118102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSS), |
| 42558 | /* 118105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 42559 | /* 118107 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 42560 | /* 118109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42561 | /* 118112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42562 | /* 118118 */ GIR_RootConstrainSelectedInstOperands, |
| 42563 | /* 118119 */ // GIR_Coverage, 677, |
| 42564 | /* 118119 */ GIR_EraseRootFromParent_Done, |
| 42565 | /* 118120 */ // Label 3578: @118120 |
| 42566 | /* 118120 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3579*/ GIMT_Encode4(118267), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3090 // |
| 42567 | /* 118127 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VABSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 42568 | /* 118127 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 42569 | /* 118130 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42570 | /* 118134 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42571 | /* 118139 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 42572 | /* 118141 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 42573 | /* 118144 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42574 | /* 118148 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42575 | /* 118153 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 42576 | /* 118156 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42577 | /* 118161 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 42578 | /* 118164 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 42579 | /* 118168 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42580 | /* 118173 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 42581 | /* 118176 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 42582 | /* 118180 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 42583 | /* 118183 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42584 | /* 118188 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42585 | /* 118193 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 42586 | /* 118198 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 42587 | /* 118201 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VABSfd), |
| 42588 | /* 118205 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42589 | /* 118210 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 42590 | /* 118213 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 42591 | /* 118216 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42592 | /* 118222 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 42593 | /* 118224 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 42594 | /* 118227 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42595 | /* 118231 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42596 | /* 118236 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 42597 | /* 118239 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42598 | /* 118244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42599 | /* 118247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 42600 | /* 118249 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 42601 | /* 118256 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 42602 | /* 118261 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 42603 | /* 118266 */ // GIR_Coverage, 3090, |
| 42604 | /* 118266 */ GIR_EraseRootFromParent_Done, |
| 42605 | /* 118267 */ // Label 3579: @118267 |
| 42606 | /* 118267 */ GIM_Reject, |
| 42607 | /* 118268 */ // Label 3577: @118268 |
| 42608 | /* 118268 */ GIM_Reject, |
| 42609 | /* 118269 */ // Label 3570: @118269 |
| 42610 | /* 118269 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3580*/ GIMT_Encode4(118305), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 676 // |
| 42611 | /* 118276 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 42612 | /* 118279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42613 | /* 118283 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42614 | /* 118287 */ // (fabs:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VABSD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 42615 | /* 118287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSD), |
| 42616 | /* 118290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 42617 | /* 118292 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 42618 | /* 118294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42619 | /* 118297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42620 | /* 118303 */ GIR_RootConstrainSelectedInstOperands, |
| 42621 | /* 118304 */ // GIR_Coverage, 676, |
| 42622 | /* 118304 */ GIR_EraseRootFromParent_Done, |
| 42623 | /* 118305 */ // Label 3580: @118305 |
| 42624 | /* 118305 */ GIM_Reject, |
| 42625 | /* 118306 */ // Label 3571: @118306 |
| 42626 | /* 118306 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3581*/ GIMT_Encode4(118342), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1678 // |
| 42627 | /* 118313 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42628 | /* 118316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42629 | /* 118320 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42630 | /* 118324 */ // (fabs:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VABShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 42631 | /* 118324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShd), |
| 42632 | /* 118327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42633 | /* 118329 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42634 | /* 118331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42635 | /* 118334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42636 | /* 118340 */ GIR_RootConstrainSelectedInstOperands, |
| 42637 | /* 118341 */ // GIR_Coverage, 1678, |
| 42638 | /* 118341 */ GIR_EraseRootFromParent_Done, |
| 42639 | /* 118342 */ // Label 3581: @118342 |
| 42640 | /* 118342 */ GIM_Reject, |
| 42641 | /* 118343 */ // Label 3572: @118343 |
| 42642 | /* 118343 */ GIM_Try, /*On fail goto*//*Label 3582*/ GIMT_Encode4(118523), |
| 42643 | /* 118348 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42644 | /* 118351 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3583*/ GIMT_Encode4(118435), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4482 // |
| 42645 | /* 118358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42646 | /* 118362 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42647 | /* 118366 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB), |
| 42648 | /* 118370 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42649 | /* 118374 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42650 | /* 118378 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42651 | /* 118383 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42652 | /* 118388 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42653 | /* 118390 */ // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 42654 | /* 118390 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42655 | /* 118393 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42656 | /* 118397 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42657 | /* 118402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16), |
| 42658 | /* 118405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42659 | /* 118407 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 42660 | /* 118411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn |
| 42661 | /* 118415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42662 | /* 118418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42663 | /* 118424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42664 | /* 118430 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42665 | /* 118433 */ GIR_RootConstrainSelectedInstOperands, |
| 42666 | /* 118434 */ // GIR_Coverage, 4482, |
| 42667 | /* 118434 */ GIR_EraseRootFromParent_Done, |
| 42668 | /* 118435 */ // Label 3583: @118435 |
| 42669 | /* 118435 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3584*/ GIMT_Encode4(118468), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1679 // |
| 42670 | /* 118442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42671 | /* 118446 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42672 | /* 118450 */ // (fabs:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VABShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 42673 | /* 118450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShq), |
| 42674 | /* 118453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42675 | /* 118455 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42676 | /* 118457 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42677 | /* 118460 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42678 | /* 118466 */ GIR_RootConstrainSelectedInstOperands, |
| 42679 | /* 118467 */ // GIR_Coverage, 1679, |
| 42680 | /* 118467 */ GIR_EraseRootFromParent_Done, |
| 42681 | /* 118468 */ // Label 3584: @118468 |
| 42682 | /* 118468 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3585*/ GIMT_Encode4(118522), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4560 // |
| 42683 | /* 118475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42684 | /* 118479 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42685 | /* 118483 */ // (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VABSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v) |
| 42686 | /* 118483 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42687 | /* 118486 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42688 | /* 118490 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42689 | /* 118495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf16), |
| 42690 | /* 118498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42691 | /* 118500 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 42692 | /* 118502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42693 | /* 118505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42694 | /* 118511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42695 | /* 118517 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42696 | /* 118520 */ GIR_RootConstrainSelectedInstOperands, |
| 42697 | /* 118521 */ // GIR_Coverage, 4560, |
| 42698 | /* 118521 */ GIR_EraseRootFromParent_Done, |
| 42699 | /* 118522 */ // Label 3585: @118522 |
| 42700 | /* 118522 */ GIM_Reject, |
| 42701 | /* 118523 */ // Label 3582: @118523 |
| 42702 | /* 118523 */ GIM_Reject, |
| 42703 | /* 118524 */ // Label 3573: @118524 |
| 42704 | /* 118524 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3586*/ GIMT_Encode4(118560), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1676 // |
| 42705 | /* 118531 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42706 | /* 118534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42707 | /* 118538 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42708 | /* 118542 */ // (fabs:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VABSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 42709 | /* 118542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfd), |
| 42710 | /* 118545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42711 | /* 118547 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42712 | /* 118549 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42713 | /* 118552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42714 | /* 118558 */ GIR_RootConstrainSelectedInstOperands, |
| 42715 | /* 118559 */ // GIR_Coverage, 1676, |
| 42716 | /* 118559 */ GIR_EraseRootFromParent_Done, |
| 42717 | /* 118560 */ // Label 3586: @118560 |
| 42718 | /* 118560 */ GIM_Reject, |
| 42719 | /* 118561 */ // Label 3574: @118561 |
| 42720 | /* 118561 */ GIM_Try, /*On fail goto*//*Label 3587*/ GIMT_Encode4(118741), |
| 42721 | /* 118566 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42722 | /* 118569 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3588*/ GIMT_Encode4(118653), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4483 // |
| 42723 | /* 118576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42724 | /* 118580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42725 | /* 118584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB), |
| 42726 | /* 118588 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42727 | /* 118592 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42728 | /* 118596 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42729 | /* 118601 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42730 | /* 118606 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 42731 | /* 118608 */ // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 42732 | /* 118608 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42733 | /* 118611 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42734 | /* 118615 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42735 | /* 118620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32), |
| 42736 | /* 118623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42737 | /* 118625 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 42738 | /* 118629 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn |
| 42739 | /* 118633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42740 | /* 118636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42741 | /* 118642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42742 | /* 118648 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42743 | /* 118651 */ GIR_RootConstrainSelectedInstOperands, |
| 42744 | /* 118652 */ // GIR_Coverage, 4483, |
| 42745 | /* 118652 */ GIR_EraseRootFromParent_Done, |
| 42746 | /* 118653 */ // Label 3588: @118653 |
| 42747 | /* 118653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3589*/ GIMT_Encode4(118686), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1677 // |
| 42748 | /* 118660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42749 | /* 118664 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42750 | /* 118668 */ // (fabs:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VABSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 42751 | /* 118668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfq), |
| 42752 | /* 118671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 42753 | /* 118673 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 42754 | /* 118675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 42755 | /* 118678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42756 | /* 118684 */ GIR_RootConstrainSelectedInstOperands, |
| 42757 | /* 118685 */ // GIR_Coverage, 1677, |
| 42758 | /* 118685 */ GIR_EraseRootFromParent_Done, |
| 42759 | /* 118686 */ // Label 3589: @118686 |
| 42760 | /* 118686 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3590*/ GIMT_Encode4(118740), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4562 // |
| 42761 | /* 118693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42762 | /* 118697 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42763 | /* 118701 */ // (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VABSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v) |
| 42764 | /* 118701 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42765 | /* 118704 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42766 | /* 118708 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42767 | /* 118713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf32), |
| 42768 | /* 118716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42769 | /* 118718 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 42770 | /* 118720 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42771 | /* 118723 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42772 | /* 118729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42773 | /* 118735 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42774 | /* 118738 */ GIR_RootConstrainSelectedInstOperands, |
| 42775 | /* 118739 */ // GIR_Coverage, 4562, |
| 42776 | /* 118739 */ GIR_EraseRootFromParent_Done, |
| 42777 | /* 118740 */ // Label 3590: @118740 |
| 42778 | /* 118740 */ GIM_Reject, |
| 42779 | /* 118741 */ // Label 3587: @118741 |
| 42780 | /* 118741 */ GIM_Reject, |
| 42781 | /* 118742 */ // Label 3575: @118742 |
| 42782 | /* 118742 */ GIM_Reject, |
| 42783 | /* 118743 */ // Label 55: @118743 |
| 42784 | /* 118743 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3598*/ GIMT_Encode4(119323), |
| 42785 | /* 118754 */ /*GILLT_s16*//*Label 3591*/ GIMT_Encode4(118806), |
| 42786 | /* 118758 */ /*GILLT_s32*//*Label 3592*/ GIMT_Encode4(118839), |
| 42787 | /* 118762 */ /*GILLT_s64*//*Label 3593*/ GIMT_Encode4(118872), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42788 | /* 118790 */ /*GILLT_v4s16*//*Label 3594*/ GIMT_Encode4(118905), |
| 42789 | /* 118794 */ /*GILLT_v8s16*//*Label 3595*/ GIMT_Encode4(118938), |
| 42790 | /* 118798 */ /*GILLT_v2s32*//*Label 3596*/ GIMT_Encode4(119114), |
| 42791 | /* 118802 */ /*GILLT_v4s32*//*Label 3597*/ GIMT_Encode4(119147), |
| 42792 | /* 118806 */ // Label 3591: @118806 |
| 42793 | /* 118806 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3599*/ GIMT_Encode4(118838), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 665 // |
| 42794 | /* 118813 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 42795 | /* 118816 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 42796 | /* 118819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42797 | /* 118823 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42798 | /* 118827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42799 | /* 118831 */ // (fminnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMINNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 42800 | /* 118831 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMH), |
| 42801 | /* 118836 */ GIR_RootConstrainSelectedInstOperands, |
| 42802 | /* 118837 */ // GIR_Coverage, 665, |
| 42803 | /* 118837 */ GIR_Done, |
| 42804 | /* 118838 */ // Label 3599: @118838 |
| 42805 | /* 118838 */ GIM_Reject, |
| 42806 | /* 118839 */ // Label 3592: @118839 |
| 42807 | /* 118839 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3600*/ GIMT_Encode4(118871), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 667 // |
| 42808 | /* 118846 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 42809 | /* 118849 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 42810 | /* 118852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42811 | /* 118856 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42812 | /* 118860 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 42813 | /* 118864 */ // (fminnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMINNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 42814 | /* 118864 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMS), |
| 42815 | /* 118869 */ GIR_RootConstrainSelectedInstOperands, |
| 42816 | /* 118870 */ // GIR_Coverage, 667, |
| 42817 | /* 118870 */ GIR_Done, |
| 42818 | /* 118871 */ // Label 3600: @118871 |
| 42819 | /* 118871 */ GIM_Reject, |
| 42820 | /* 118872 */ // Label 3593: @118872 |
| 42821 | /* 118872 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3601*/ GIMT_Encode4(118904), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 669 // |
| 42822 | /* 118879 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 42823 | /* 118882 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 42824 | /* 118885 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42825 | /* 118889 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42826 | /* 118893 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42827 | /* 118897 */ // (fminnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMINNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 42828 | /* 118897 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMD), |
| 42829 | /* 118902 */ GIR_RootConstrainSelectedInstOperands, |
| 42830 | /* 118903 */ // GIR_Coverage, 669, |
| 42831 | /* 118903 */ GIR_Done, |
| 42832 | /* 118904 */ // Label 3601: @118904 |
| 42833 | /* 118904 */ GIM_Reject, |
| 42834 | /* 118905 */ // Label 3594: @118905 |
| 42835 | /* 118905 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3602*/ GIMT_Encode4(118937), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1397 // |
| 42836 | /* 118912 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 42837 | /* 118915 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 42838 | /* 118918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42839 | /* 118922 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42840 | /* 118926 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42841 | /* 118930 */ // (fminnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMINNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 42842 | /* 118930 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDh), |
| 42843 | /* 118935 */ GIR_RootConstrainSelectedInstOperands, |
| 42844 | /* 118936 */ // GIR_Coverage, 1397, |
| 42845 | /* 118936 */ GIR_Done, |
| 42846 | /* 118937 */ // Label 3602: @118937 |
| 42847 | /* 118937 */ GIM_Reject, |
| 42848 | /* 118938 */ // Label 3595: @118938 |
| 42849 | /* 118938 */ GIM_Try, /*On fail goto*//*Label 3603*/ GIMT_Encode4(119113), |
| 42850 | /* 118943 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42851 | /* 118946 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 42852 | /* 118949 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3604*/ GIMT_Encode4(119026), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4577 // |
| 42853 | /* 118956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42854 | /* 118960 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42855 | /* 118964 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42856 | /* 118968 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42857 | /* 118972 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42858 | /* 118977 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 42859 | /* 118981 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42860 | /* 118985 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 42861 | /* 118989 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42862 | /* 118994 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 42863 | /* 118996 */ // (fminnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 42864 | /* 118996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16), |
| 42865 | /* 118999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42866 | /* 119001 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 42867 | /* 119005 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 42868 | /* 119009 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42869 | /* 119012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42870 | /* 119018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42871 | /* 119024 */ GIR_RootConstrainSelectedInstOperands, |
| 42872 | /* 119025 */ // GIR_Coverage, 4577, |
| 42873 | /* 119025 */ GIR_EraseRootFromParent_Done, |
| 42874 | /* 119026 */ // Label 3604: @119026 |
| 42875 | /* 119026 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3605*/ GIMT_Encode4(119052), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1398 // |
| 42876 | /* 119033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42877 | /* 119037 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42878 | /* 119041 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42879 | /* 119045 */ // (fminnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMINNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 42880 | /* 119045 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQh), |
| 42881 | /* 119050 */ GIR_RootConstrainSelectedInstOperands, |
| 42882 | /* 119051 */ // GIR_Coverage, 1398, |
| 42883 | /* 119051 */ GIR_Done, |
| 42884 | /* 119052 */ // Label 3605: @119052 |
| 42885 | /* 119052 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3606*/ GIMT_Encode4(119112), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3683 // |
| 42886 | /* 119059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42887 | /* 119063 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42888 | /* 119067 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42889 | /* 119071 */ // (fminnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 42890 | /* 119071 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42891 | /* 119074 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42892 | /* 119078 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42893 | /* 119083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16), |
| 42894 | /* 119086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42895 | /* 119088 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 42896 | /* 119090 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 42897 | /* 119092 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42898 | /* 119095 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42899 | /* 119101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42900 | /* 119107 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42901 | /* 119110 */ GIR_RootConstrainSelectedInstOperands, |
| 42902 | /* 119111 */ // GIR_Coverage, 3683, |
| 42903 | /* 119111 */ GIR_EraseRootFromParent_Done, |
| 42904 | /* 119112 */ // Label 3606: @119112 |
| 42905 | /* 119112 */ GIM_Reject, |
| 42906 | /* 119113 */ // Label 3603: @119113 |
| 42907 | /* 119113 */ GIM_Reject, |
| 42908 | /* 119114 */ // Label 3596: @119114 |
| 42909 | /* 119114 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3607*/ GIMT_Encode4(119146), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1395 // |
| 42910 | /* 119121 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 42911 | /* 119124 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 42912 | /* 119127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42913 | /* 119131 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42914 | /* 119135 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 42915 | /* 119139 */ // (fminnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMINNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 42916 | /* 119139 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDf), |
| 42917 | /* 119144 */ GIR_RootConstrainSelectedInstOperands, |
| 42918 | /* 119145 */ // GIR_Coverage, 1395, |
| 42919 | /* 119145 */ GIR_Done, |
| 42920 | /* 119146 */ // Label 3607: @119146 |
| 42921 | /* 119146 */ GIM_Reject, |
| 42922 | /* 119147 */ // Label 3597: @119147 |
| 42923 | /* 119147 */ GIM_Try, /*On fail goto*//*Label 3608*/ GIMT_Encode4(119322), |
| 42924 | /* 119152 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42925 | /* 119155 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 42926 | /* 119158 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3609*/ GIMT_Encode4(119235), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4574 // |
| 42927 | /* 119165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42928 | /* 119169 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 42929 | /* 119173 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42930 | /* 119177 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42931 | /* 119181 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42932 | /* 119186 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 42933 | /* 119190 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 42934 | /* 119194 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 42935 | /* 119198 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42936 | /* 119203 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 42937 | /* 119205 */ // (fminnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 42938 | /* 119205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32), |
| 42939 | /* 119208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42940 | /* 119210 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 42941 | /* 119214 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 42942 | /* 119218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42943 | /* 119221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42944 | /* 119227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42945 | /* 119233 */ GIR_RootConstrainSelectedInstOperands, |
| 42946 | /* 119234 */ // GIR_Coverage, 4574, |
| 42947 | /* 119234 */ GIR_EraseRootFromParent_Done, |
| 42948 | /* 119235 */ // Label 3609: @119235 |
| 42949 | /* 119235 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3610*/ GIMT_Encode4(119261), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1396 // |
| 42950 | /* 119242 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42951 | /* 119246 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42952 | /* 119250 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 42953 | /* 119254 */ // (fminnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMINNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 42954 | /* 119254 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQf), |
| 42955 | /* 119259 */ GIR_RootConstrainSelectedInstOperands, |
| 42956 | /* 119260 */ // GIR_Coverage, 1396, |
| 42957 | /* 119260 */ GIR_Done, |
| 42958 | /* 119261 */ // Label 3610: @119261 |
| 42959 | /* 119261 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3611*/ GIMT_Encode4(119321), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3678 // |
| 42960 | /* 119268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42961 | /* 119272 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42962 | /* 119276 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 42963 | /* 119280 */ // (fminnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 42964 | /* 119280 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 42965 | /* 119283 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 42966 | /* 119287 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 42967 | /* 119292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32), |
| 42968 | /* 119295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 42969 | /* 119297 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 42970 | /* 119299 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 42971 | /* 119301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42972 | /* 119304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42973 | /* 119310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 42974 | /* 119316 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42975 | /* 119319 */ GIR_RootConstrainSelectedInstOperands, |
| 42976 | /* 119320 */ // GIR_Coverage, 3678, |
| 42977 | /* 119320 */ GIR_EraseRootFromParent_Done, |
| 42978 | /* 119321 */ // Label 3611: @119321 |
| 42979 | /* 119321 */ GIM_Reject, |
| 42980 | /* 119322 */ // Label 3608: @119322 |
| 42981 | /* 119322 */ GIM_Reject, |
| 42982 | /* 119323 */ // Label 3598: @119323 |
| 42983 | /* 119323 */ GIM_Reject, |
| 42984 | /* 119324 */ // Label 56: @119324 |
| 42985 | /* 119324 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3619*/ GIMT_Encode4(119904), |
| 42986 | /* 119335 */ /*GILLT_s16*//*Label 3612*/ GIMT_Encode4(119387), |
| 42987 | /* 119339 */ /*GILLT_s32*//*Label 3613*/ GIMT_Encode4(119420), |
| 42988 | /* 119343 */ /*GILLT_s64*//*Label 3614*/ GIMT_Encode4(119453), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 42989 | /* 119371 */ /*GILLT_v4s16*//*Label 3615*/ GIMT_Encode4(119486), |
| 42990 | /* 119375 */ /*GILLT_v8s16*//*Label 3616*/ GIMT_Encode4(119519), |
| 42991 | /* 119379 */ /*GILLT_v2s32*//*Label 3617*/ GIMT_Encode4(119695), |
| 42992 | /* 119383 */ /*GILLT_v4s32*//*Label 3618*/ GIMT_Encode4(119728), |
| 42993 | /* 119387 */ // Label 3612: @119387 |
| 42994 | /* 119387 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3620*/ GIMT_Encode4(119419), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 659 // |
| 42995 | /* 119394 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 42996 | /* 119397 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 42997 | /* 119400 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42998 | /* 119404 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 42999 | /* 119408 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43000 | /* 119412 */ // (fmaxnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMAXNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 43001 | /* 119412 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMH), |
| 43002 | /* 119417 */ GIR_RootConstrainSelectedInstOperands, |
| 43003 | /* 119418 */ // GIR_Coverage, 659, |
| 43004 | /* 119418 */ GIR_Done, |
| 43005 | /* 119419 */ // Label 3620: @119419 |
| 43006 | /* 119419 */ GIM_Reject, |
| 43007 | /* 119420 */ // Label 3613: @119420 |
| 43008 | /* 119420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3621*/ GIMT_Encode4(119452), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 661 // |
| 43009 | /* 119427 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 43010 | /* 119430 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43011 | /* 119433 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43012 | /* 119437 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43013 | /* 119441 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43014 | /* 119445 */ // (fmaxnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMAXNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 43015 | /* 119445 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMS), |
| 43016 | /* 119450 */ GIR_RootConstrainSelectedInstOperands, |
| 43017 | /* 119451 */ // GIR_Coverage, 661, |
| 43018 | /* 119451 */ GIR_Done, |
| 43019 | /* 119452 */ // Label 3621: @119452 |
| 43020 | /* 119452 */ GIM_Reject, |
| 43021 | /* 119453 */ // Label 3614: @119453 |
| 43022 | /* 119453 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3622*/ GIMT_Encode4(119485), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 663 // |
| 43023 | /* 119460 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 43024 | /* 119463 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 43025 | /* 119466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43026 | /* 119470 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43027 | /* 119474 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43028 | /* 119478 */ // (fmaxnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMAXNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 43029 | /* 119478 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMD), |
| 43030 | /* 119483 */ GIR_RootConstrainSelectedInstOperands, |
| 43031 | /* 119484 */ // GIR_Coverage, 663, |
| 43032 | /* 119484 */ GIR_Done, |
| 43033 | /* 119485 */ // Label 3622: @119485 |
| 43034 | /* 119485 */ GIM_Reject, |
| 43035 | /* 119486 */ // Label 3615: @119486 |
| 43036 | /* 119486 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3623*/ GIMT_Encode4(119518), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1377 // |
| 43037 | /* 119493 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43038 | /* 119496 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43039 | /* 119499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43040 | /* 119503 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43041 | /* 119507 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43042 | /* 119511 */ // (fmaxnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMAXNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 43043 | /* 119511 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDh), |
| 43044 | /* 119516 */ GIR_RootConstrainSelectedInstOperands, |
| 43045 | /* 119517 */ // GIR_Coverage, 1377, |
| 43046 | /* 119517 */ GIR_Done, |
| 43047 | /* 119518 */ // Label 3623: @119518 |
| 43048 | /* 119518 */ GIM_Reject, |
| 43049 | /* 119519 */ // Label 3616: @119519 |
| 43050 | /* 119519 */ GIM_Try, /*On fail goto*//*Label 3624*/ GIMT_Encode4(119694), |
| 43051 | /* 119524 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43052 | /* 119527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43053 | /* 119530 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3625*/ GIMT_Encode4(119607), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4571 // |
| 43054 | /* 119537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43055 | /* 119541 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43056 | /* 119545 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43057 | /* 119549 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43058 | /* 119553 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43059 | /* 119558 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 43060 | /* 119562 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43061 | /* 119566 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43062 | /* 119570 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43063 | /* 119575 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43064 | /* 119577 */ // (fmaxnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm) |
| 43065 | /* 119577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16), |
| 43066 | /* 119580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43067 | /* 119582 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 43068 | /* 119586 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 43069 | /* 119590 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43070 | /* 119593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43071 | /* 119599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43072 | /* 119605 */ GIR_RootConstrainSelectedInstOperands, |
| 43073 | /* 119606 */ // GIR_Coverage, 4571, |
| 43074 | /* 119606 */ GIR_EraseRootFromParent_Done, |
| 43075 | /* 119607 */ // Label 3625: @119607 |
| 43076 | /* 119607 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3626*/ GIMT_Encode4(119633), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1378 // |
| 43077 | /* 119614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43078 | /* 119618 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43079 | /* 119622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43080 | /* 119626 */ // (fmaxnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMAXNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 43081 | /* 119626 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQh), |
| 43082 | /* 119631 */ GIR_RootConstrainSelectedInstOperands, |
| 43083 | /* 119632 */ // GIR_Coverage, 1378, |
| 43084 | /* 119632 */ GIR_Done, |
| 43085 | /* 119633 */ // Label 3626: @119633 |
| 43086 | /* 119633 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3627*/ GIMT_Encode4(119693), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3673 // |
| 43087 | /* 119640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43088 | /* 119644 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43089 | /* 119648 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43090 | /* 119652 */ // (fmaxnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) |
| 43091 | /* 119652 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43092 | /* 119655 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43093 | /* 119659 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43094 | /* 119664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16), |
| 43095 | /* 119667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43096 | /* 119669 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43097 | /* 119671 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43098 | /* 119673 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43099 | /* 119676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43100 | /* 119682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43101 | /* 119688 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43102 | /* 119691 */ GIR_RootConstrainSelectedInstOperands, |
| 43103 | /* 119692 */ // GIR_Coverage, 3673, |
| 43104 | /* 119692 */ GIR_EraseRootFromParent_Done, |
| 43105 | /* 119693 */ // Label 3627: @119693 |
| 43106 | /* 119693 */ GIM_Reject, |
| 43107 | /* 119694 */ // Label 3624: @119694 |
| 43108 | /* 119694 */ GIM_Reject, |
| 43109 | /* 119695 */ // Label 3617: @119695 |
| 43110 | /* 119695 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3628*/ GIMT_Encode4(119727), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1375 // |
| 43111 | /* 119702 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43112 | /* 119705 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43113 | /* 119708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43114 | /* 119712 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43115 | /* 119716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43116 | /* 119720 */ // (fmaxnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMAXNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 43117 | /* 119720 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDf), |
| 43118 | /* 119725 */ GIR_RootConstrainSelectedInstOperands, |
| 43119 | /* 119726 */ // GIR_Coverage, 1375, |
| 43120 | /* 119726 */ GIR_Done, |
| 43121 | /* 119727 */ // Label 3628: @119727 |
| 43122 | /* 119727 */ GIM_Reject, |
| 43123 | /* 119728 */ // Label 3618: @119728 |
| 43124 | /* 119728 */ GIM_Try, /*On fail goto*//*Label 3629*/ GIMT_Encode4(119903), |
| 43125 | /* 119733 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43126 | /* 119736 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43127 | /* 119739 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3630*/ GIMT_Encode4(119816), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4568 // |
| 43128 | /* 119746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43129 | /* 119750 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 43130 | /* 119754 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43131 | /* 119758 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43132 | /* 119762 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43133 | /* 119767 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 43134 | /* 119771 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 43135 | /* 119775 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43136 | /* 119779 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43137 | /* 119784 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 43138 | /* 119786 */ // (fmaxnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm) |
| 43139 | /* 119786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32), |
| 43140 | /* 119789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43141 | /* 119791 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd |
| 43142 | /* 119795 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm |
| 43143 | /* 119799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43144 | /* 119802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43145 | /* 119808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43146 | /* 119814 */ GIR_RootConstrainSelectedInstOperands, |
| 43147 | /* 119815 */ // GIR_Coverage, 4568, |
| 43148 | /* 119815 */ GIR_EraseRootFromParent_Done, |
| 43149 | /* 119816 */ // Label 3630: @119816 |
| 43150 | /* 119816 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3631*/ GIMT_Encode4(119842), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1376 // |
| 43151 | /* 119823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43152 | /* 119827 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43153 | /* 119831 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43154 | /* 119835 */ // (fmaxnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMAXNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 43155 | /* 119835 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQf), |
| 43156 | /* 119840 */ GIR_RootConstrainSelectedInstOperands, |
| 43157 | /* 119841 */ // GIR_Coverage, 1376, |
| 43158 | /* 119841 */ GIR_Done, |
| 43159 | /* 119842 */ // Label 3631: @119842 |
| 43160 | /* 119842 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3632*/ GIMT_Encode4(119902), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3416 // |
| 43161 | /* 119849 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43162 | /* 119853 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43163 | /* 119857 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43164 | /* 119861 */ // (fmaxnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) |
| 43165 | /* 119861 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43166 | /* 119864 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43167 | /* 119868 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43168 | /* 119873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32), |
| 43169 | /* 119876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43170 | /* 119878 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43171 | /* 119880 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43172 | /* 119882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43173 | /* 119885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43174 | /* 119891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43175 | /* 119897 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43176 | /* 119900 */ GIR_RootConstrainSelectedInstOperands, |
| 43177 | /* 119901 */ // GIR_Coverage, 3416, |
| 43178 | /* 119901 */ GIR_EraseRootFromParent_Done, |
| 43179 | /* 119902 */ // Label 3632: @119902 |
| 43180 | /* 119902 */ GIM_Reject, |
| 43181 | /* 119903 */ // Label 3629: @119903 |
| 43182 | /* 119903 */ GIM_Reject, |
| 43183 | /* 119904 */ // Label 3619: @119904 |
| 43184 | /* 119904 */ GIM_Reject, |
| 43185 | /* 119905 */ // Label 57: @119905 |
| 43186 | /* 119905 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3639*/ GIMT_Encode4(120632), |
| 43187 | /* 119916 */ /*GILLT_s16*//*Label 3633*/ GIMT_Encode4(119968), |
| 43188 | /* 119920 */ /*GILLT_s32*//*Label 3634*/ GIMT_Encode4(120208), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43189 | /* 119952 */ /*GILLT_v4s16*//*Label 3635*/ GIMT_Encode4(120448), |
| 43190 | /* 119956 */ /*GILLT_v8s16*//*Label 3636*/ GIMT_Encode4(120494), |
| 43191 | /* 119960 */ /*GILLT_v2s32*//*Label 3637*/ GIMT_Encode4(120540), |
| 43192 | /* 119964 */ /*GILLT_v4s32*//*Label 3638*/ GIMT_Encode4(120586), |
| 43193 | /* 119968 */ // Label 3633: @119968 |
| 43194 | /* 119968 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3640*/ GIMT_Encode4(120207), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 3093 // |
| 43195 | /* 119975 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 43196 | /* 119978 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 43197 | /* 119981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43198 | /* 119985 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43199 | /* 119989 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43200 | /* 119993 */ // (fminimum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMINhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 43201 | /* 119993 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16, |
| 43202 | /* 119996 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43203 | /* 120000 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43204 | /* 120005 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 43205 | /* 120007 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16, |
| 43206 | /* 120010 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43207 | /* 120014 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43208 | /* 120019 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 43209 | /* 120022 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43210 | /* 120027 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16, |
| 43211 | /* 120030 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43212 | /* 120034 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43213 | /* 120039 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 43214 | /* 120042 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 43215 | /* 120046 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 43216 | /* 120049 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43217 | /* 120054 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43218 | /* 120059 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 43219 | /* 120064 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16, |
| 43220 | /* 120067 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43221 | /* 120071 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43222 | /* 120076 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 43223 | /* 120078 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16, |
| 43224 | /* 120081 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43225 | /* 120085 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43226 | /* 120090 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 43227 | /* 120093 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43228 | /* 120098 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16, |
| 43229 | /* 120101 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43230 | /* 120105 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43231 | /* 120110 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 43232 | /* 120113 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 43233 | /* 120117 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 43234 | /* 120120 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43235 | /* 120125 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43236 | /* 120130 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 43237 | /* 120135 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 43238 | /* 120138 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINhd), |
| 43239 | /* 120142 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43240 | /* 120147 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 43241 | /* 120150 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 43242 | /* 120153 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 43243 | /* 120156 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43244 | /* 120162 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 43245 | /* 120164 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16, |
| 43246 | /* 120167 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43247 | /* 120171 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43248 | /* 120176 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 43249 | /* 120179 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43250 | /* 120184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43251 | /* 120187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 43252 | /* 120189 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 43253 | /* 120196 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 43254 | /* 120201 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43255 | /* 120206 */ // GIR_Coverage, 3093, |
| 43256 | /* 120206 */ GIR_EraseRootFromParent_Done, |
| 43257 | /* 120207 */ // Label 3640: @120207 |
| 43258 | /* 120207 */ GIM_Reject, |
| 43259 | /* 120208 */ // Label 3634: @120208 |
| 43260 | /* 120208 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3641*/ GIMT_Encode4(120447), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3095 // |
| 43261 | /* 120215 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 43262 | /* 120218 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43263 | /* 120221 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43264 | /* 120225 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43265 | /* 120229 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43266 | /* 120233 */ // (fminimum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMINfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 43267 | /* 120233 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 43268 | /* 120236 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43269 | /* 120240 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43270 | /* 120245 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 43271 | /* 120247 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 43272 | /* 120250 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43273 | /* 120254 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43274 | /* 120259 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 43275 | /* 120262 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43276 | /* 120267 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 43277 | /* 120270 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43278 | /* 120274 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43279 | /* 120279 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 43280 | /* 120282 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 43281 | /* 120286 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 43282 | /* 120289 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43283 | /* 120294 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43284 | /* 120299 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 43285 | /* 120304 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 43286 | /* 120307 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43287 | /* 120311 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43288 | /* 120316 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 43289 | /* 120318 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 43290 | /* 120321 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43291 | /* 120325 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43292 | /* 120330 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 43293 | /* 120333 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43294 | /* 120338 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 43295 | /* 120341 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43296 | /* 120345 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43297 | /* 120350 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 43298 | /* 120353 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 43299 | /* 120357 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 43300 | /* 120360 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43301 | /* 120365 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43302 | /* 120370 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 43303 | /* 120375 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 43304 | /* 120378 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINfd), |
| 43305 | /* 120382 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43306 | /* 120387 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 43307 | /* 120390 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 43308 | /* 120393 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 43309 | /* 120396 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43310 | /* 120402 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 43311 | /* 120404 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 43312 | /* 120407 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43313 | /* 120411 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43314 | /* 120416 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 43315 | /* 120419 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43316 | /* 120424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43317 | /* 120427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 43318 | /* 120429 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 43319 | /* 120436 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 43320 | /* 120441 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43321 | /* 120446 */ // GIR_Coverage, 3095, |
| 43322 | /* 120446 */ GIR_EraseRootFromParent_Done, |
| 43323 | /* 120447 */ // Label 3641: @120447 |
| 43324 | /* 120447 */ GIM_Reject, |
| 43325 | /* 120448 */ // Label 3635: @120448 |
| 43326 | /* 120448 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3642*/ GIMT_Encode4(120493), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1393 // |
| 43327 | /* 120455 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43328 | /* 120458 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43329 | /* 120461 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43330 | /* 120465 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43331 | /* 120469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43332 | /* 120473 */ // (fminimum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMINhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 43333 | /* 120473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhd), |
| 43334 | /* 120476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43335 | /* 120478 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43336 | /* 120480 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43337 | /* 120482 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43338 | /* 120485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43339 | /* 120491 */ GIR_RootConstrainSelectedInstOperands, |
| 43340 | /* 120492 */ // GIR_Coverage, 1393, |
| 43341 | /* 120492 */ GIR_EraseRootFromParent_Done, |
| 43342 | /* 120493 */ // Label 3642: @120493 |
| 43343 | /* 120493 */ GIM_Reject, |
| 43344 | /* 120494 */ // Label 3636: @120494 |
| 43345 | /* 120494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3643*/ GIMT_Encode4(120539), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1394 // |
| 43346 | /* 120501 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43347 | /* 120504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43348 | /* 120507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43349 | /* 120511 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43350 | /* 120515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43351 | /* 120519 */ // (fminimum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMINhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 43352 | /* 120519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhq), |
| 43353 | /* 120522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43354 | /* 120524 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43355 | /* 120526 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43356 | /* 120528 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43357 | /* 120531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43358 | /* 120537 */ GIR_RootConstrainSelectedInstOperands, |
| 43359 | /* 120538 */ // GIR_Coverage, 1394, |
| 43360 | /* 120538 */ GIR_EraseRootFromParent_Done, |
| 43361 | /* 120539 */ // Label 3643: @120539 |
| 43362 | /* 120539 */ GIM_Reject, |
| 43363 | /* 120540 */ // Label 3637: @120540 |
| 43364 | /* 120540 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3644*/ GIMT_Encode4(120585), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1391 // |
| 43365 | /* 120547 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43366 | /* 120550 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43367 | /* 120553 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43368 | /* 120557 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43369 | /* 120561 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43370 | /* 120565 */ // (fminimum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMINfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 43371 | /* 120565 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfd), |
| 43372 | /* 120568 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43373 | /* 120570 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43374 | /* 120572 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43375 | /* 120574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43376 | /* 120577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43377 | /* 120583 */ GIR_RootConstrainSelectedInstOperands, |
| 43378 | /* 120584 */ // GIR_Coverage, 1391, |
| 43379 | /* 120584 */ GIR_EraseRootFromParent_Done, |
| 43380 | /* 120585 */ // Label 3644: @120585 |
| 43381 | /* 120585 */ GIM_Reject, |
| 43382 | /* 120586 */ // Label 3638: @120586 |
| 43383 | /* 120586 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3645*/ GIMT_Encode4(120631), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1392 // |
| 43384 | /* 120593 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43385 | /* 120596 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43386 | /* 120599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43387 | /* 120603 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43388 | /* 120607 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43389 | /* 120611 */ // (fminimum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMINfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 43390 | /* 120611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfq), |
| 43391 | /* 120614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43392 | /* 120616 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43393 | /* 120618 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43394 | /* 120620 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43395 | /* 120623 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43396 | /* 120629 */ GIR_RootConstrainSelectedInstOperands, |
| 43397 | /* 120630 */ // GIR_Coverage, 1392, |
| 43398 | /* 120630 */ GIR_EraseRootFromParent_Done, |
| 43399 | /* 120631 */ // Label 3645: @120631 |
| 43400 | /* 120631 */ GIM_Reject, |
| 43401 | /* 120632 */ // Label 3639: @120632 |
| 43402 | /* 120632 */ GIM_Reject, |
| 43403 | /* 120633 */ // Label 58: @120633 |
| 43404 | /* 120633 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3652*/ GIMT_Encode4(121360), |
| 43405 | /* 120644 */ /*GILLT_s16*//*Label 3646*/ GIMT_Encode4(120696), |
| 43406 | /* 120648 */ /*GILLT_s32*//*Label 3647*/ GIMT_Encode4(120936), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 43407 | /* 120680 */ /*GILLT_v4s16*//*Label 3648*/ GIMT_Encode4(121176), |
| 43408 | /* 120684 */ /*GILLT_v8s16*//*Label 3649*/ GIMT_Encode4(121222), |
| 43409 | /* 120688 */ /*GILLT_v2s32*//*Label 3650*/ GIMT_Encode4(121268), |
| 43410 | /* 120692 */ /*GILLT_v4s32*//*Label 3651*/ GIMT_Encode4(121314), |
| 43411 | /* 120696 */ // Label 3646: @120696 |
| 43412 | /* 120696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3653*/ GIMT_Encode4(120935), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 3092 // |
| 43413 | /* 120703 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 43414 | /* 120706 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 43415 | /* 120709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43416 | /* 120713 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43417 | /* 120717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 43418 | /* 120721 */ // (fmaximum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMAXhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 43419 | /* 120721 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16, |
| 43420 | /* 120724 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43421 | /* 120728 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43422 | /* 120733 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 43423 | /* 120735 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16, |
| 43424 | /* 120738 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43425 | /* 120742 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43426 | /* 120747 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 43427 | /* 120750 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43428 | /* 120755 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16, |
| 43429 | /* 120758 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43430 | /* 120762 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43431 | /* 120767 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 43432 | /* 120770 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 43433 | /* 120774 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 43434 | /* 120777 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43435 | /* 120782 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43436 | /* 120787 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 43437 | /* 120792 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16, |
| 43438 | /* 120795 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43439 | /* 120799 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43440 | /* 120804 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 43441 | /* 120806 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16, |
| 43442 | /* 120809 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43443 | /* 120813 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43444 | /* 120818 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 43445 | /* 120821 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43446 | /* 120826 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16, |
| 43447 | /* 120829 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43448 | /* 120833 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43449 | /* 120838 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 43450 | /* 120841 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 43451 | /* 120845 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 43452 | /* 120848 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43453 | /* 120853 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43454 | /* 120858 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID), |
| 43455 | /* 120863 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 43456 | /* 120866 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXhd), |
| 43457 | /* 120870 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43458 | /* 120875 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 43459 | /* 120878 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 43460 | /* 120881 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 43461 | /* 120884 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43462 | /* 120890 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 43463 | /* 120892 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16, |
| 43464 | /* 120895 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43465 | /* 120899 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43466 | /* 120904 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 43467 | /* 120907 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43468 | /* 120912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43469 | /* 120915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 43470 | /* 120917 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 43471 | /* 120924 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 43472 | /* 120929 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43473 | /* 120934 */ // GIR_Coverage, 3092, |
| 43474 | /* 120934 */ GIR_EraseRootFromParent_Done, |
| 43475 | /* 120935 */ // Label 3653: @120935 |
| 43476 | /* 120935 */ GIM_Reject, |
| 43477 | /* 120936 */ // Label 3647: @120936 |
| 43478 | /* 120936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3654*/ GIMT_Encode4(121175), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3094 // |
| 43479 | /* 120943 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 43480 | /* 120946 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 43481 | /* 120949 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43482 | /* 120953 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43483 | /* 120957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 43484 | /* 120961 */ // (fmaximum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMAXfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] }) |
| 43485 | /* 120961 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32, |
| 43486 | /* 120964 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43487 | /* 120968 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43488 | /* 120973 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 43489 | /* 120975 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32, |
| 43490 | /* 120978 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43491 | /* 120982 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43492 | /* 120987 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 43493 | /* 120990 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43494 | /* 120995 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32, |
| 43495 | /* 120998 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43496 | /* 121002 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43497 | /* 121007 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 43498 | /* 121010 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b |
| 43499 | /* 121014 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17, |
| 43500 | /* 121017 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43501 | /* 121022 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43502 | /* 121027 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 43503 | /* 121032 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32, |
| 43504 | /* 121035 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43505 | /* 121039 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43506 | /* 121044 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 43507 | /* 121046 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32, |
| 43508 | /* 121049 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43509 | /* 121053 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43510 | /* 121058 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 43511 | /* 121061 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43512 | /* 121066 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32, |
| 43513 | /* 121069 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), |
| 43514 | /* 121073 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43515 | /* 121078 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 43516 | /* 121081 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 43517 | /* 121085 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17, |
| 43518 | /* 121088 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43519 | /* 121093 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43520 | /* 121098 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID), |
| 43521 | /* 121103 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 43522 | /* 121106 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXfd), |
| 43523 | /* 121110 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43524 | /* 121115 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 43525 | /* 121118 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5, |
| 43526 | /* 121121 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14, |
| 43527 | /* 121124 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43528 | /* 121130 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 43529 | /* 121132 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32, |
| 43530 | /* 121135 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43531 | /* 121139 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43532 | /* 121144 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 43533 | /* 121147 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43534 | /* 121152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43535 | /* 121155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 43536 | /* 121157 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0), |
| 43537 | /* 121164 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID), |
| 43538 | /* 121169 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID), |
| 43539 | /* 121174 */ // GIR_Coverage, 3094, |
| 43540 | /* 121174 */ GIR_EraseRootFromParent_Done, |
| 43541 | /* 121175 */ // Label 3654: @121175 |
| 43542 | /* 121175 */ GIM_Reject, |
| 43543 | /* 121176 */ // Label 3648: @121176 |
| 43544 | /* 121176 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3655*/ GIMT_Encode4(121221), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1373 // |
| 43545 | /* 121183 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43546 | /* 121186 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43547 | /* 121189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43548 | /* 121193 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43549 | /* 121197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43550 | /* 121201 */ // (fmaximum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMAXhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) |
| 43551 | /* 121201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhd), |
| 43552 | /* 121204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43553 | /* 121206 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43554 | /* 121208 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43555 | /* 121210 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43556 | /* 121213 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43557 | /* 121219 */ GIR_RootConstrainSelectedInstOperands, |
| 43558 | /* 121220 */ // GIR_Coverage, 1373, |
| 43559 | /* 121220 */ GIR_EraseRootFromParent_Done, |
| 43560 | /* 121221 */ // Label 3655: @121221 |
| 43561 | /* 121221 */ GIM_Reject, |
| 43562 | /* 121222 */ // Label 3649: @121222 |
| 43563 | /* 121222 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3656*/ GIMT_Encode4(121267), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1374 // |
| 43564 | /* 121229 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43565 | /* 121232 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43566 | /* 121235 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43567 | /* 121239 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43568 | /* 121243 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43569 | /* 121247 */ // (fmaximum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMAXhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) |
| 43570 | /* 121247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhq), |
| 43571 | /* 121250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43572 | /* 121252 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43573 | /* 121254 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43574 | /* 121256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43575 | /* 121259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43576 | /* 121265 */ GIR_RootConstrainSelectedInstOperands, |
| 43577 | /* 121266 */ // GIR_Coverage, 1374, |
| 43578 | /* 121266 */ GIR_EraseRootFromParent_Done, |
| 43579 | /* 121267 */ // Label 3656: @121267 |
| 43580 | /* 121267 */ GIM_Reject, |
| 43581 | /* 121268 */ // Label 3650: @121268 |
| 43582 | /* 121268 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3657*/ GIMT_Encode4(121313), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1371 // |
| 43583 | /* 121275 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43584 | /* 121278 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43585 | /* 121281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43586 | /* 121285 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43587 | /* 121289 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43588 | /* 121293 */ // (fmaximum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMAXfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) |
| 43589 | /* 121293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfd), |
| 43590 | /* 121296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43591 | /* 121298 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43592 | /* 121300 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43593 | /* 121302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43594 | /* 121305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43595 | /* 121311 */ GIR_RootConstrainSelectedInstOperands, |
| 43596 | /* 121312 */ // GIR_Coverage, 1371, |
| 43597 | /* 121312 */ GIR_EraseRootFromParent_Done, |
| 43598 | /* 121313 */ // Label 3657: @121313 |
| 43599 | /* 121313 */ GIM_Reject, |
| 43600 | /* 121314 */ // Label 3651: @121314 |
| 43601 | /* 121314 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3658*/ GIMT_Encode4(121359), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1372 // |
| 43602 | /* 121321 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43603 | /* 121324 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43604 | /* 121327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43605 | /* 121331 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43606 | /* 121335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43607 | /* 121339 */ // (fmaximum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMAXfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) |
| 43608 | /* 121339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfq), |
| 43609 | /* 121342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43610 | /* 121344 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43611 | /* 121346 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43612 | /* 121348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43613 | /* 121351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43614 | /* 121357 */ GIR_RootConstrainSelectedInstOperands, |
| 43615 | /* 121358 */ // GIR_Coverage, 1372, |
| 43616 | /* 121358 */ GIR_EraseRootFromParent_Done, |
| 43617 | /* 121359 */ // Label 3658: @121359 |
| 43618 | /* 121359 */ GIM_Reject, |
| 43619 | /* 121360 */ // Label 3652: @121360 |
| 43620 | /* 121360 */ GIM_Reject, |
| 43621 | /* 121361 */ // Label 59: @121361 |
| 43622 | /* 121361 */ GIM_Try, /*On fail goto*//*Label 3659*/ GIMT_Encode4(121393), // Rule ID 2797 // |
| 43623 | /* 121366 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43624 | /* 121369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 43625 | /* 121373 */ // (get_fpenv:{ *:[i32] }) => (VMRS:{ *:[i32] }) |
| 43626 | /* 121373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS), |
| 43627 | /* 121376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 43628 | /* 121378 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43629 | /* 121381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43630 | /* 121387 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43631 | /* 121391 */ GIR_RootConstrainSelectedInstOperands, |
| 43632 | /* 121392 */ // GIR_Coverage, 2797, |
| 43633 | /* 121392 */ GIR_EraseRootFromParent_Done, |
| 43634 | /* 121393 */ // Label 3659: @121393 |
| 43635 | /* 121393 */ GIM_Reject, |
| 43636 | /* 121394 */ // Label 60: @121394 |
| 43637 | /* 121394 */ GIM_Try, /*On fail goto*//*Label 3660*/ GIMT_Encode4(121429), // Rule ID 2798 // |
| 43638 | /* 121399 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43639 | /* 121402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 43640 | /* 121406 */ // (set_fpenv GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt) |
| 43641 | /* 121406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 43642 | /* 121409 */ GIR_RootToRootCopy, /*OpIdx*/0, // Rt |
| 43643 | /* 121411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43644 | /* 121414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43645 | /* 121420 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 43646 | /* 121423 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43647 | /* 121427 */ GIR_RootConstrainSelectedInstOperands, |
| 43648 | /* 121428 */ // GIR_Coverage, 2798, |
| 43649 | /* 121428 */ GIR_EraseRootFromParent_Done, |
| 43650 | /* 121429 */ // Label 3660: @121429 |
| 43651 | /* 121429 */ GIM_Reject, |
| 43652 | /* 121430 */ // Label 61: @121430 |
| 43653 | /* 121430 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3661*/ GIMT_Encode4(121493), GIMT_Encode2(GIFBS_IsARM), // Rule ID 2799 // |
| 43654 | /* 121437 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (MOVi:{ *:[i32] } 0:{ *:[i32] })) |
| 43655 | /* 121437 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 43656 | /* 121440 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MOVi), |
| 43657 | /* 121444 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43658 | /* 121449 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 43659 | /* 121452 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 43660 | /* 121455 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43661 | /* 121461 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43662 | /* 121467 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 43663 | /* 121469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 43664 | /* 121472 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43665 | /* 121475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43666 | /* 121478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43667 | /* 121484 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 43668 | /* 121487 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43669 | /* 121491 */ GIR_RootConstrainSelectedInstOperands, |
| 43670 | /* 121492 */ // GIR_Coverage, 2799, |
| 43671 | /* 121492 */ GIR_EraseRootFromParent_Done, |
| 43672 | /* 121493 */ // Label 3661: @121493 |
| 43673 | /* 121493 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3662*/ GIMT_Encode4(121556), GIMT_Encode2(GIFBS_IsThumb), // Rule ID 2800 // |
| 43674 | /* 121500 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (tMOVi8:{ *:[i32] } 0:{ *:[i32] })) |
| 43675 | /* 121500 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 43676 | /* 121503 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8), |
| 43677 | /* 121507 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43678 | /* 121512 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)), |
| 43679 | /* 121518 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 43680 | /* 121521 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 43681 | /* 121524 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43682 | /* 121530 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 43683 | /* 121532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR), |
| 43684 | /* 121535 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43685 | /* 121538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43686 | /* 121541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43687 | /* 121547 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0, |
| 43688 | /* 121550 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43689 | /* 121554 */ GIR_RootConstrainSelectedInstOperands, |
| 43690 | /* 121555 */ // GIR_Coverage, 2800, |
| 43691 | /* 121555 */ GIR_EraseRootFromParent_Done, |
| 43692 | /* 121556 */ // Label 3662: @121556 |
| 43693 | /* 121556 */ GIM_Reject, |
| 43694 | /* 121557 */ // Label 62: @121557 |
| 43695 | /* 121557 */ GIM_Try, /*On fail goto*//*Label 3663*/ GIMT_Encode4(121589), // Rule ID 2801 // |
| 43696 | /* 121562 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 43697 | /* 121565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID), |
| 43698 | /* 121569 */ // (get_fpmode:{ *:[i32] }) => (VMRS:{ *:[i32] }) |
| 43699 | /* 121569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS), |
| 43700 | /* 121572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt] |
| 43701 | /* 121574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43702 | /* 121577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43703 | /* 121583 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43704 | /* 121587 */ GIR_RootConstrainSelectedInstOperands, |
| 43705 | /* 121588 */ // GIR_Coverage, 2801, |
| 43706 | /* 121588 */ GIR_EraseRootFromParent_Done, |
| 43707 | /* 121589 */ // Label 3663: @121589 |
| 43708 | /* 121589 */ GIM_Reject, |
| 43709 | /* 121590 */ // Label 63: @121590 |
| 43710 | /* 121590 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3670*/ GIMT_Encode4(122099), |
| 43711 | /* 121601 */ /*GILLT_v8s8*//*Label 3664*/ GIMT_Encode4(121625), |
| 43712 | /* 121605 */ /*GILLT_v16s8*//*Label 3665*/ GIMT_Encode4(121671), |
| 43713 | /* 121609 */ /*GILLT_v4s16*//*Label 3666*/ GIMT_Encode4(121783), |
| 43714 | /* 121613 */ /*GILLT_v8s16*//*Label 3667*/ GIMT_Encode4(121829), |
| 43715 | /* 121617 */ /*GILLT_v2s32*//*Label 3668*/ GIMT_Encode4(121941), |
| 43716 | /* 121621 */ /*GILLT_v4s32*//*Label 3669*/ GIMT_Encode4(121987), |
| 43717 | /* 121625 */ // Label 3664: @121625 |
| 43718 | /* 121625 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3671*/ GIMT_Encode4(121670), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1383 // |
| 43719 | /* 121632 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 43720 | /* 121635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 43721 | /* 121638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43722 | /* 121642 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43723 | /* 121646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43724 | /* 121650 */ // (smin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 43725 | /* 121650 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i8), |
| 43726 | /* 121653 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43727 | /* 121655 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43728 | /* 121657 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43729 | /* 121659 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43730 | /* 121662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43731 | /* 121668 */ GIR_RootConstrainSelectedInstOperands, |
| 43732 | /* 121669 */ // GIR_Coverage, 1383, |
| 43733 | /* 121669 */ GIR_EraseRootFromParent_Done, |
| 43734 | /* 121670 */ // Label 3671: @121670 |
| 43735 | /* 121670 */ GIM_Reject, |
| 43736 | /* 121671 */ // Label 3665: @121671 |
| 43737 | /* 121671 */ GIM_Try, /*On fail goto*//*Label 3672*/ GIMT_Encode4(121782), |
| 43738 | /* 121676 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 43739 | /* 121679 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 43740 | /* 121682 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3673*/ GIMT_Encode4(121721), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1384 // |
| 43741 | /* 121689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43742 | /* 121693 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43743 | /* 121697 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43744 | /* 121701 */ // (smin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 43745 | /* 121701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv16i8), |
| 43746 | /* 121704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43747 | /* 121706 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43748 | /* 121708 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43749 | /* 121710 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43750 | /* 121713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43751 | /* 121719 */ GIR_RootConstrainSelectedInstOperands, |
| 43752 | /* 121720 */ // GIR_Coverage, 1384, |
| 43753 | /* 121720 */ GIR_EraseRootFromParent_Done, |
| 43754 | /* 121721 */ // Label 3673: @121721 |
| 43755 | /* 121721 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3674*/ GIMT_Encode4(121781), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3688 // |
| 43756 | /* 121728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43757 | /* 121732 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43758 | /* 121736 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43759 | /* 121740 */ // (smin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 43760 | /* 121740 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43761 | /* 121743 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43762 | /* 121747 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43763 | /* 121752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs8), |
| 43764 | /* 121755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43765 | /* 121757 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43766 | /* 121759 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43767 | /* 121761 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43768 | /* 121764 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43769 | /* 121770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43770 | /* 121776 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43771 | /* 121779 */ GIR_RootConstrainSelectedInstOperands, |
| 43772 | /* 121780 */ // GIR_Coverage, 3688, |
| 43773 | /* 121780 */ GIR_EraseRootFromParent_Done, |
| 43774 | /* 121781 */ // Label 3674: @121781 |
| 43775 | /* 121781 */ GIM_Reject, |
| 43776 | /* 121782 */ // Label 3672: @121782 |
| 43777 | /* 121782 */ GIM_Reject, |
| 43778 | /* 121783 */ // Label 3666: @121783 |
| 43779 | /* 121783 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3675*/ GIMT_Encode4(121828), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1379 // |
| 43780 | /* 121790 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43781 | /* 121793 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43782 | /* 121796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43783 | /* 121800 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43784 | /* 121804 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43785 | /* 121808 */ // (smin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 43786 | /* 121808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i16), |
| 43787 | /* 121811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43788 | /* 121813 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43789 | /* 121815 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43790 | /* 121817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43791 | /* 121820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43792 | /* 121826 */ GIR_RootConstrainSelectedInstOperands, |
| 43793 | /* 121827 */ // GIR_Coverage, 1379, |
| 43794 | /* 121827 */ GIR_EraseRootFromParent_Done, |
| 43795 | /* 121828 */ // Label 3675: @121828 |
| 43796 | /* 121828 */ GIM_Reject, |
| 43797 | /* 121829 */ // Label 3667: @121829 |
| 43798 | /* 121829 */ GIM_Try, /*On fail goto*//*Label 3676*/ GIMT_Encode4(121940), |
| 43799 | /* 121834 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43800 | /* 121837 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43801 | /* 121840 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3677*/ GIMT_Encode4(121879), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1381 // |
| 43802 | /* 121847 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43803 | /* 121851 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43804 | /* 121855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43805 | /* 121859 */ // (smin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 43806 | /* 121859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i16), |
| 43807 | /* 121862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43808 | /* 121864 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43809 | /* 121866 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43810 | /* 121868 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43811 | /* 121871 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43812 | /* 121877 */ GIR_RootConstrainSelectedInstOperands, |
| 43813 | /* 121878 */ // GIR_Coverage, 1381, |
| 43814 | /* 121878 */ GIR_EraseRootFromParent_Done, |
| 43815 | /* 121879 */ // Label 3677: @121879 |
| 43816 | /* 121879 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3678*/ GIMT_Encode4(121939), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3691 // |
| 43817 | /* 121886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43818 | /* 121890 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43819 | /* 121894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43820 | /* 121898 */ // (smin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 43821 | /* 121898 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43822 | /* 121901 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43823 | /* 121905 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43824 | /* 121910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs16), |
| 43825 | /* 121913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43826 | /* 121915 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43827 | /* 121917 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43828 | /* 121919 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43829 | /* 121922 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43830 | /* 121928 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43831 | /* 121934 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43832 | /* 121937 */ GIR_RootConstrainSelectedInstOperands, |
| 43833 | /* 121938 */ // GIR_Coverage, 3691, |
| 43834 | /* 121938 */ GIR_EraseRootFromParent_Done, |
| 43835 | /* 121939 */ // Label 3678: @121939 |
| 43836 | /* 121939 */ GIM_Reject, |
| 43837 | /* 121940 */ // Label 3676: @121940 |
| 43838 | /* 121940 */ GIM_Reject, |
| 43839 | /* 121941 */ // Label 3668: @121941 |
| 43840 | /* 121941 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3679*/ GIMT_Encode4(121986), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1380 // |
| 43841 | /* 121948 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 43842 | /* 121951 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 43843 | /* 121954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43844 | /* 121958 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43845 | /* 121962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43846 | /* 121966 */ // (smin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 43847 | /* 121966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv2i32), |
| 43848 | /* 121969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43849 | /* 121971 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43850 | /* 121973 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43851 | /* 121975 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43852 | /* 121978 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43853 | /* 121984 */ GIR_RootConstrainSelectedInstOperands, |
| 43854 | /* 121985 */ // GIR_Coverage, 1380, |
| 43855 | /* 121985 */ GIR_EraseRootFromParent_Done, |
| 43856 | /* 121986 */ // Label 3679: @121986 |
| 43857 | /* 121986 */ GIM_Reject, |
| 43858 | /* 121987 */ // Label 3669: @121987 |
| 43859 | /* 121987 */ GIM_Try, /*On fail goto*//*Label 3680*/ GIMT_Encode4(122098), |
| 43860 | /* 121992 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 43861 | /* 121995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 43862 | /* 121998 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3681*/ GIMT_Encode4(122037), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1382 // |
| 43863 | /* 122005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43864 | /* 122009 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43865 | /* 122013 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43866 | /* 122017 */ // (smin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 43867 | /* 122017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i32), |
| 43868 | /* 122020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43869 | /* 122022 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43870 | /* 122024 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43871 | /* 122026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43872 | /* 122029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43873 | /* 122035 */ GIR_RootConstrainSelectedInstOperands, |
| 43874 | /* 122036 */ // GIR_Coverage, 1382, |
| 43875 | /* 122036 */ GIR_EraseRootFromParent_Done, |
| 43876 | /* 122037 */ // Label 3681: @122037 |
| 43877 | /* 122037 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3682*/ GIMT_Encode4(122097), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3694 // |
| 43878 | /* 122044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43879 | /* 122048 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43880 | /* 122052 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43881 | /* 122056 */ // (smin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 43882 | /* 122056 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43883 | /* 122059 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43884 | /* 122063 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43885 | /* 122068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs32), |
| 43886 | /* 122071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43887 | /* 122073 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43888 | /* 122075 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43889 | /* 122077 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43890 | /* 122080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43891 | /* 122086 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43892 | /* 122092 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43893 | /* 122095 */ GIR_RootConstrainSelectedInstOperands, |
| 43894 | /* 122096 */ // GIR_Coverage, 3694, |
| 43895 | /* 122096 */ GIR_EraseRootFromParent_Done, |
| 43896 | /* 122097 */ // Label 3682: @122097 |
| 43897 | /* 122097 */ GIM_Reject, |
| 43898 | /* 122098 */ // Label 3680: @122098 |
| 43899 | /* 122098 */ GIM_Reject, |
| 43900 | /* 122099 */ // Label 3670: @122099 |
| 43901 | /* 122099 */ GIM_Reject, |
| 43902 | /* 122100 */ // Label 64: @122100 |
| 43903 | /* 122100 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3689*/ GIMT_Encode4(122609), |
| 43904 | /* 122111 */ /*GILLT_v8s8*//*Label 3683*/ GIMT_Encode4(122135), |
| 43905 | /* 122115 */ /*GILLT_v16s8*//*Label 3684*/ GIMT_Encode4(122181), |
| 43906 | /* 122119 */ /*GILLT_v4s16*//*Label 3685*/ GIMT_Encode4(122293), |
| 43907 | /* 122123 */ /*GILLT_v8s16*//*Label 3686*/ GIMT_Encode4(122339), |
| 43908 | /* 122127 */ /*GILLT_v2s32*//*Label 3687*/ GIMT_Encode4(122451), |
| 43909 | /* 122131 */ /*GILLT_v4s32*//*Label 3688*/ GIMT_Encode4(122497), |
| 43910 | /* 122135 */ // Label 3683: @122135 |
| 43911 | /* 122135 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3690*/ GIMT_Encode4(122180), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1363 // |
| 43912 | /* 122142 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 43913 | /* 122145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 43914 | /* 122148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43915 | /* 122152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43916 | /* 122156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43917 | /* 122160 */ // (smax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 43918 | /* 122160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i8), |
| 43919 | /* 122163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43920 | /* 122165 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43921 | /* 122167 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43922 | /* 122169 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43923 | /* 122172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43924 | /* 122178 */ GIR_RootConstrainSelectedInstOperands, |
| 43925 | /* 122179 */ // GIR_Coverage, 1363, |
| 43926 | /* 122179 */ GIR_EraseRootFromParent_Done, |
| 43927 | /* 122180 */ // Label 3690: @122180 |
| 43928 | /* 122180 */ GIM_Reject, |
| 43929 | /* 122181 */ // Label 3684: @122181 |
| 43930 | /* 122181 */ GIM_Try, /*On fail goto*//*Label 3691*/ GIMT_Encode4(122292), |
| 43931 | /* 122186 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 43932 | /* 122189 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 43933 | /* 122192 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3692*/ GIMT_Encode4(122231), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1364 // |
| 43934 | /* 122199 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43935 | /* 122203 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43936 | /* 122207 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43937 | /* 122211 */ // (smax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 43938 | /* 122211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv16i8), |
| 43939 | /* 122214 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43940 | /* 122216 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43941 | /* 122218 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43942 | /* 122220 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43943 | /* 122223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43944 | /* 122229 */ GIR_RootConstrainSelectedInstOperands, |
| 43945 | /* 122230 */ // GIR_Coverage, 1364, |
| 43946 | /* 122230 */ GIR_EraseRootFromParent_Done, |
| 43947 | /* 122231 */ // Label 3692: @122231 |
| 43948 | /* 122231 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3693*/ GIMT_Encode4(122291), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3706 // |
| 43949 | /* 122238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43950 | /* 122242 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43951 | /* 122246 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 43952 | /* 122250 */ // (smax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 43953 | /* 122250 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 43954 | /* 122253 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 43955 | /* 122257 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 43956 | /* 122262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs8), |
| 43957 | /* 122265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 43958 | /* 122267 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 43959 | /* 122269 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 43960 | /* 122271 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43961 | /* 122274 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43962 | /* 122280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43963 | /* 122286 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43964 | /* 122289 */ GIR_RootConstrainSelectedInstOperands, |
| 43965 | /* 122290 */ // GIR_Coverage, 3706, |
| 43966 | /* 122290 */ GIR_EraseRootFromParent_Done, |
| 43967 | /* 122291 */ // Label 3693: @122291 |
| 43968 | /* 122291 */ GIM_Reject, |
| 43969 | /* 122292 */ // Label 3691: @122292 |
| 43970 | /* 122292 */ GIM_Reject, |
| 43971 | /* 122293 */ // Label 3685: @122293 |
| 43972 | /* 122293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3694*/ GIMT_Encode4(122338), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1359 // |
| 43973 | /* 122300 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 43974 | /* 122303 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 43975 | /* 122306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43976 | /* 122310 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43977 | /* 122314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 43978 | /* 122318 */ // (smax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 43979 | /* 122318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i16), |
| 43980 | /* 122321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 43981 | /* 122323 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 43982 | /* 122325 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 43983 | /* 122327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 43984 | /* 122330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 43985 | /* 122336 */ GIR_RootConstrainSelectedInstOperands, |
| 43986 | /* 122337 */ // GIR_Coverage, 1359, |
| 43987 | /* 122337 */ GIR_EraseRootFromParent_Done, |
| 43988 | /* 122338 */ // Label 3694: @122338 |
| 43989 | /* 122338 */ GIM_Reject, |
| 43990 | /* 122339 */ // Label 3686: @122339 |
| 43991 | /* 122339 */ GIM_Try, /*On fail goto*//*Label 3695*/ GIMT_Encode4(122450), |
| 43992 | /* 122344 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 43993 | /* 122347 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 43994 | /* 122350 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3696*/ GIMT_Encode4(122389), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1361 // |
| 43995 | /* 122357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43996 | /* 122361 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43997 | /* 122365 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 43998 | /* 122369 */ // (smax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 43999 | /* 122369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i16), |
| 44000 | /* 122372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44001 | /* 122374 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44002 | /* 122376 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44003 | /* 122378 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44004 | /* 122381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44005 | /* 122387 */ GIR_RootConstrainSelectedInstOperands, |
| 44006 | /* 122388 */ // GIR_Coverage, 1361, |
| 44007 | /* 122388 */ GIR_EraseRootFromParent_Done, |
| 44008 | /* 122389 */ // Label 3696: @122389 |
| 44009 | /* 122389 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3697*/ GIMT_Encode4(122449), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3709 // |
| 44010 | /* 122396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44011 | /* 122400 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44012 | /* 122404 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44013 | /* 122408 */ // (smax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 44014 | /* 122408 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44015 | /* 122411 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44016 | /* 122415 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44017 | /* 122420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs16), |
| 44018 | /* 122423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44019 | /* 122425 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44020 | /* 122427 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44021 | /* 122429 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44022 | /* 122432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44023 | /* 122438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44024 | /* 122444 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44025 | /* 122447 */ GIR_RootConstrainSelectedInstOperands, |
| 44026 | /* 122448 */ // GIR_Coverage, 3709, |
| 44027 | /* 122448 */ GIR_EraseRootFromParent_Done, |
| 44028 | /* 122449 */ // Label 3697: @122449 |
| 44029 | /* 122449 */ GIM_Reject, |
| 44030 | /* 122450 */ // Label 3695: @122450 |
| 44031 | /* 122450 */ GIM_Reject, |
| 44032 | /* 122451 */ // Label 3687: @122451 |
| 44033 | /* 122451 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3698*/ GIMT_Encode4(122496), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1360 // |
| 44034 | /* 122458 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 44035 | /* 122461 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44036 | /* 122464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44037 | /* 122468 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44038 | /* 122472 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44039 | /* 122476 */ // (smax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 44040 | /* 122476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv2i32), |
| 44041 | /* 122479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44042 | /* 122481 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44043 | /* 122483 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44044 | /* 122485 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44045 | /* 122488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44046 | /* 122494 */ GIR_RootConstrainSelectedInstOperands, |
| 44047 | /* 122495 */ // GIR_Coverage, 1360, |
| 44048 | /* 122495 */ GIR_EraseRootFromParent_Done, |
| 44049 | /* 122496 */ // Label 3698: @122496 |
| 44050 | /* 122496 */ GIM_Reject, |
| 44051 | /* 122497 */ // Label 3688: @122497 |
| 44052 | /* 122497 */ GIM_Try, /*On fail goto*//*Label 3699*/ GIMT_Encode4(122608), |
| 44053 | /* 122502 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44054 | /* 122505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44055 | /* 122508 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3700*/ GIMT_Encode4(122547), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1362 // |
| 44056 | /* 122515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44057 | /* 122519 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44058 | /* 122523 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44059 | /* 122527 */ // (smax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 44060 | /* 122527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i32), |
| 44061 | /* 122530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44062 | /* 122532 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44063 | /* 122534 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44064 | /* 122536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44065 | /* 122539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44066 | /* 122545 */ GIR_RootConstrainSelectedInstOperands, |
| 44067 | /* 122546 */ // GIR_Coverage, 1362, |
| 44068 | /* 122546 */ GIR_EraseRootFromParent_Done, |
| 44069 | /* 122547 */ // Label 3700: @122547 |
| 44070 | /* 122547 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3701*/ GIMT_Encode4(122607), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3712 // |
| 44071 | /* 122554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44072 | /* 122558 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44073 | /* 122562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44074 | /* 122566 */ // (smax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 44075 | /* 122566 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44076 | /* 122569 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44077 | /* 122573 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44078 | /* 122578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs32), |
| 44079 | /* 122581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44080 | /* 122583 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44081 | /* 122585 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44082 | /* 122587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44083 | /* 122590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44084 | /* 122596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44085 | /* 122602 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44086 | /* 122605 */ GIR_RootConstrainSelectedInstOperands, |
| 44087 | /* 122606 */ // GIR_Coverage, 3712, |
| 44088 | /* 122606 */ GIR_EraseRootFromParent_Done, |
| 44089 | /* 122607 */ // Label 3701: @122607 |
| 44090 | /* 122607 */ GIM_Reject, |
| 44091 | /* 122608 */ // Label 3699: @122608 |
| 44092 | /* 122608 */ GIM_Reject, |
| 44093 | /* 122609 */ // Label 3689: @122609 |
| 44094 | /* 122609 */ GIM_Reject, |
| 44095 | /* 122610 */ // Label 65: @122610 |
| 44096 | /* 122610 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3708*/ GIMT_Encode4(123497), |
| 44097 | /* 122621 */ /*GILLT_v8s8*//*Label 3702*/ GIMT_Encode4(122645), |
| 44098 | /* 122625 */ /*GILLT_v16s8*//*Label 3703*/ GIMT_Encode4(122691), |
| 44099 | /* 122629 */ /*GILLT_v4s16*//*Label 3704*/ GIMT_Encode4(122929), |
| 44100 | /* 122633 */ /*GILLT_v8s16*//*Label 3705*/ GIMT_Encode4(122975), |
| 44101 | /* 122637 */ /*GILLT_v2s32*//*Label 3706*/ GIMT_Encode4(123213), |
| 44102 | /* 122641 */ /*GILLT_v4s32*//*Label 3707*/ GIMT_Encode4(123259), |
| 44103 | /* 122645 */ // Label 3702: @122645 |
| 44104 | /* 122645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3709*/ GIMT_Encode4(122690), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1389 // |
| 44105 | /* 122652 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44106 | /* 122655 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 44107 | /* 122658 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44108 | /* 122662 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44109 | /* 122666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44110 | /* 122670 */ // (umin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 44111 | /* 122670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i8), |
| 44112 | /* 122673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44113 | /* 122675 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44114 | /* 122677 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44115 | /* 122679 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44116 | /* 122682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44117 | /* 122688 */ GIR_RootConstrainSelectedInstOperands, |
| 44118 | /* 122689 */ // GIR_Coverage, 1389, |
| 44119 | /* 122689 */ GIR_EraseRootFromParent_Done, |
| 44120 | /* 122690 */ // Label 3709: @122690 |
| 44121 | /* 122690 */ GIM_Reject, |
| 44122 | /* 122691 */ // Label 3703: @122691 |
| 44123 | /* 122691 */ GIM_Try, /*On fail goto*//*Label 3710*/ GIMT_Encode4(122928), |
| 44124 | /* 122696 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44125 | /* 122699 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 44126 | /* 122702 */ GIM_Try, /*On fail goto*//*Label 3711*/ GIMT_Encode4(122828), |
| 44127 | /* 122707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44128 | /* 122711 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3712*/ GIMT_Encode4(122769), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6649 // |
| 44129 | /* 122718 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44130 | /* 122722 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44131 | /* 122726 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44132 | /* 122730 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44133 | /* 122735 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44134 | /* 122739 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44135 | /* 122741 */ // (umin:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 44136 | /* 122741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8), |
| 44137 | /* 122744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44138 | /* 122746 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44139 | /* 122748 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44140 | /* 122752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44141 | /* 122755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44142 | /* 122761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44143 | /* 122767 */ GIR_RootConstrainSelectedInstOperands, |
| 44144 | /* 122768 */ // GIR_Coverage, 6649, |
| 44145 | /* 122768 */ GIR_EraseRootFromParent_Done, |
| 44146 | /* 122769 */ // Label 3712: @122769 |
| 44147 | /* 122769 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3713*/ GIMT_Encode4(122827), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4087 // |
| 44148 | /* 122776 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44149 | /* 122780 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44150 | /* 122784 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44151 | /* 122788 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44152 | /* 122792 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44153 | /* 122797 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44154 | /* 122799 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 44155 | /* 122799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8), |
| 44156 | /* 122802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44157 | /* 122804 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44158 | /* 122806 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44159 | /* 122810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44160 | /* 122813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44161 | /* 122819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44162 | /* 122825 */ GIR_RootConstrainSelectedInstOperands, |
| 44163 | /* 122826 */ // GIR_Coverage, 4087, |
| 44164 | /* 122826 */ GIR_EraseRootFromParent_Done, |
| 44165 | /* 122827 */ // Label 3713: @122827 |
| 44166 | /* 122827 */ GIM_Reject, |
| 44167 | /* 122828 */ // Label 3711: @122828 |
| 44168 | /* 122828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3714*/ GIMT_Encode4(122867), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1390 // |
| 44169 | /* 122835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44170 | /* 122839 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44171 | /* 122843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44172 | /* 122847 */ // (umin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 44173 | /* 122847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv16i8), |
| 44174 | /* 122850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44175 | /* 122852 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44176 | /* 122854 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44177 | /* 122856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44178 | /* 122859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44179 | /* 122865 */ GIR_RootConstrainSelectedInstOperands, |
| 44180 | /* 122866 */ // GIR_Coverage, 1390, |
| 44181 | /* 122866 */ GIR_EraseRootFromParent_Done, |
| 44182 | /* 122867 */ // Label 3714: @122867 |
| 44183 | /* 122867 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3715*/ GIMT_Encode4(122927), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3697 // |
| 44184 | /* 122874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44185 | /* 122878 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44186 | /* 122882 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44187 | /* 122886 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 44188 | /* 122886 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44189 | /* 122889 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44190 | /* 122893 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44191 | /* 122898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu8), |
| 44192 | /* 122901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44193 | /* 122903 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44194 | /* 122905 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44195 | /* 122907 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44196 | /* 122910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44197 | /* 122916 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44198 | /* 122922 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44199 | /* 122925 */ GIR_RootConstrainSelectedInstOperands, |
| 44200 | /* 122926 */ // GIR_Coverage, 3697, |
| 44201 | /* 122926 */ GIR_EraseRootFromParent_Done, |
| 44202 | /* 122927 */ // Label 3715: @122927 |
| 44203 | /* 122927 */ GIM_Reject, |
| 44204 | /* 122928 */ // Label 3710: @122928 |
| 44205 | /* 122928 */ GIM_Reject, |
| 44206 | /* 122929 */ // Label 3704: @122929 |
| 44207 | /* 122929 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3716*/ GIMT_Encode4(122974), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1385 // |
| 44208 | /* 122936 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44209 | /* 122939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44210 | /* 122942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44211 | /* 122946 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44212 | /* 122950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44213 | /* 122954 */ // (umin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 44214 | /* 122954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i16), |
| 44215 | /* 122957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44216 | /* 122959 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44217 | /* 122961 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44218 | /* 122963 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44219 | /* 122966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44220 | /* 122972 */ GIR_RootConstrainSelectedInstOperands, |
| 44221 | /* 122973 */ // GIR_Coverage, 1385, |
| 44222 | /* 122973 */ GIR_EraseRootFromParent_Done, |
| 44223 | /* 122974 */ // Label 3716: @122974 |
| 44224 | /* 122974 */ GIM_Reject, |
| 44225 | /* 122975 */ // Label 3705: @122975 |
| 44226 | /* 122975 */ GIM_Try, /*On fail goto*//*Label 3717*/ GIMT_Encode4(123212), |
| 44227 | /* 122980 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44228 | /* 122983 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44229 | /* 122986 */ GIM_Try, /*On fail goto*//*Label 3718*/ GIMT_Encode4(123112), |
| 44230 | /* 122991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44231 | /* 122995 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3719*/ GIMT_Encode4(123053), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6650 // |
| 44232 | /* 123002 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44233 | /* 123006 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44234 | /* 123010 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44235 | /* 123014 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44236 | /* 123019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44237 | /* 123023 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44238 | /* 123025 */ // (umin:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 44239 | /* 123025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16), |
| 44240 | /* 123028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44241 | /* 123030 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44242 | /* 123032 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44243 | /* 123036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44244 | /* 123039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44245 | /* 123045 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44246 | /* 123051 */ GIR_RootConstrainSelectedInstOperands, |
| 44247 | /* 123052 */ // GIR_Coverage, 6650, |
| 44248 | /* 123052 */ GIR_EraseRootFromParent_Done, |
| 44249 | /* 123053 */ // Label 3719: @123053 |
| 44250 | /* 123053 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3720*/ GIMT_Encode4(123111), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4089 // |
| 44251 | /* 123060 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44252 | /* 123064 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44253 | /* 123068 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44254 | /* 123072 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44255 | /* 123076 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44256 | /* 123081 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44257 | /* 123083 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 44258 | /* 123083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16), |
| 44259 | /* 123086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44260 | /* 123088 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44261 | /* 123090 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44262 | /* 123094 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44263 | /* 123097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44264 | /* 123103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44265 | /* 123109 */ GIR_RootConstrainSelectedInstOperands, |
| 44266 | /* 123110 */ // GIR_Coverage, 4089, |
| 44267 | /* 123110 */ GIR_EraseRootFromParent_Done, |
| 44268 | /* 123111 */ // Label 3720: @123111 |
| 44269 | /* 123111 */ GIM_Reject, |
| 44270 | /* 123112 */ // Label 3718: @123112 |
| 44271 | /* 123112 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3721*/ GIMT_Encode4(123151), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1387 // |
| 44272 | /* 123119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44273 | /* 123123 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44274 | /* 123127 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44275 | /* 123131 */ // (umin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 44276 | /* 123131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i16), |
| 44277 | /* 123134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44278 | /* 123136 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44279 | /* 123138 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44280 | /* 123140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44281 | /* 123143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44282 | /* 123149 */ GIR_RootConstrainSelectedInstOperands, |
| 44283 | /* 123150 */ // GIR_Coverage, 1387, |
| 44284 | /* 123150 */ GIR_EraseRootFromParent_Done, |
| 44285 | /* 123151 */ // Label 3721: @123151 |
| 44286 | /* 123151 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3722*/ GIMT_Encode4(123211), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3700 // |
| 44287 | /* 123158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44288 | /* 123162 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44289 | /* 123166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44290 | /* 123170 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 44291 | /* 123170 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44292 | /* 123173 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44293 | /* 123177 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44294 | /* 123182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu16), |
| 44295 | /* 123185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44296 | /* 123187 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44297 | /* 123189 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44298 | /* 123191 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44299 | /* 123194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44300 | /* 123200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44301 | /* 123206 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44302 | /* 123209 */ GIR_RootConstrainSelectedInstOperands, |
| 44303 | /* 123210 */ // GIR_Coverage, 3700, |
| 44304 | /* 123210 */ GIR_EraseRootFromParent_Done, |
| 44305 | /* 123211 */ // Label 3722: @123211 |
| 44306 | /* 123211 */ GIM_Reject, |
| 44307 | /* 123212 */ // Label 3717: @123212 |
| 44308 | /* 123212 */ GIM_Reject, |
| 44309 | /* 123213 */ // Label 3706: @123213 |
| 44310 | /* 123213 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3723*/ GIMT_Encode4(123258), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1386 // |
| 44311 | /* 123220 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 44312 | /* 123223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44313 | /* 123226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44314 | /* 123230 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44315 | /* 123234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44316 | /* 123238 */ // (umin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 44317 | /* 123238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv2i32), |
| 44318 | /* 123241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44319 | /* 123243 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44320 | /* 123245 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44321 | /* 123247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44322 | /* 123250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44323 | /* 123256 */ GIR_RootConstrainSelectedInstOperands, |
| 44324 | /* 123257 */ // GIR_Coverage, 1386, |
| 44325 | /* 123257 */ GIR_EraseRootFromParent_Done, |
| 44326 | /* 123258 */ // Label 3723: @123258 |
| 44327 | /* 123258 */ GIM_Reject, |
| 44328 | /* 123259 */ // Label 3707: @123259 |
| 44329 | /* 123259 */ GIM_Try, /*On fail goto*//*Label 3724*/ GIMT_Encode4(123496), |
| 44330 | /* 123264 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44331 | /* 123267 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44332 | /* 123270 */ GIM_Try, /*On fail goto*//*Label 3725*/ GIMT_Encode4(123396), |
| 44333 | /* 123275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44334 | /* 123279 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3726*/ GIMT_Encode4(123337), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6651 // |
| 44335 | /* 123286 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44336 | /* 123290 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44337 | /* 123294 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44338 | /* 123298 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44339 | /* 123303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44340 | /* 123307 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44341 | /* 123309 */ // (umin:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 44342 | /* 123309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32), |
| 44343 | /* 123312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44344 | /* 123314 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44345 | /* 123316 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44346 | /* 123320 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44347 | /* 123323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44348 | /* 123329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44349 | /* 123335 */ GIR_RootConstrainSelectedInstOperands, |
| 44350 | /* 123336 */ // GIR_Coverage, 6651, |
| 44351 | /* 123336 */ GIR_EraseRootFromParent_Done, |
| 44352 | /* 123337 */ // Label 3726: @123337 |
| 44353 | /* 123337 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3727*/ GIMT_Encode4(123395), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4091 // |
| 44354 | /* 123344 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44355 | /* 123348 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44356 | /* 123352 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44357 | /* 123356 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44358 | /* 123360 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44359 | /* 123365 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44360 | /* 123367 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 44361 | /* 123367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32), |
| 44362 | /* 123370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44363 | /* 123372 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44364 | /* 123374 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44365 | /* 123378 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44366 | /* 123381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44367 | /* 123387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44368 | /* 123393 */ GIR_RootConstrainSelectedInstOperands, |
| 44369 | /* 123394 */ // GIR_Coverage, 4091, |
| 44370 | /* 123394 */ GIR_EraseRootFromParent_Done, |
| 44371 | /* 123395 */ // Label 3727: @123395 |
| 44372 | /* 123395 */ GIM_Reject, |
| 44373 | /* 123396 */ // Label 3725: @123396 |
| 44374 | /* 123396 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3728*/ GIMT_Encode4(123435), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1388 // |
| 44375 | /* 123403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44376 | /* 123407 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44377 | /* 123411 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44378 | /* 123415 */ // (umin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 44379 | /* 123415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i32), |
| 44380 | /* 123418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44381 | /* 123420 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44382 | /* 123422 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44383 | /* 123424 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44384 | /* 123427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44385 | /* 123433 */ GIR_RootConstrainSelectedInstOperands, |
| 44386 | /* 123434 */ // GIR_Coverage, 1388, |
| 44387 | /* 123434 */ GIR_EraseRootFromParent_Done, |
| 44388 | /* 123435 */ // Label 3728: @123435 |
| 44389 | /* 123435 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3729*/ GIMT_Encode4(123495), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3703 // |
| 44390 | /* 123442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44391 | /* 123446 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44392 | /* 123450 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44393 | /* 123454 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 44394 | /* 123454 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44395 | /* 123457 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44396 | /* 123461 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44397 | /* 123466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu32), |
| 44398 | /* 123469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44399 | /* 123471 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44400 | /* 123473 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44401 | /* 123475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44402 | /* 123478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44403 | /* 123484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44404 | /* 123490 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44405 | /* 123493 */ GIR_RootConstrainSelectedInstOperands, |
| 44406 | /* 123494 */ // GIR_Coverage, 3703, |
| 44407 | /* 123494 */ GIR_EraseRootFromParent_Done, |
| 44408 | /* 123495 */ // Label 3729: @123495 |
| 44409 | /* 123495 */ GIM_Reject, |
| 44410 | /* 123496 */ // Label 3724: @123496 |
| 44411 | /* 123496 */ GIM_Reject, |
| 44412 | /* 123497 */ // Label 3708: @123497 |
| 44413 | /* 123497 */ GIM_Reject, |
| 44414 | /* 123498 */ // Label 66: @123498 |
| 44415 | /* 123498 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3736*/ GIMT_Encode4(124385), |
| 44416 | /* 123509 */ /*GILLT_v8s8*//*Label 3730*/ GIMT_Encode4(123533), |
| 44417 | /* 123513 */ /*GILLT_v16s8*//*Label 3731*/ GIMT_Encode4(123579), |
| 44418 | /* 123517 */ /*GILLT_v4s16*//*Label 3732*/ GIMT_Encode4(123817), |
| 44419 | /* 123521 */ /*GILLT_v8s16*//*Label 3733*/ GIMT_Encode4(123863), |
| 44420 | /* 123525 */ /*GILLT_v2s32*//*Label 3734*/ GIMT_Encode4(124101), |
| 44421 | /* 123529 */ /*GILLT_v4s32*//*Label 3735*/ GIMT_Encode4(124147), |
| 44422 | /* 123533 */ // Label 3730: @123533 |
| 44423 | /* 123533 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3737*/ GIMT_Encode4(123578), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1369 // |
| 44424 | /* 123540 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44425 | /* 123543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8, |
| 44426 | /* 123546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44427 | /* 123550 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44428 | /* 123554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44429 | /* 123558 */ // (umax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) |
| 44430 | /* 123558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i8), |
| 44431 | /* 123561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44432 | /* 123563 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44433 | /* 123565 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44434 | /* 123567 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44435 | /* 123570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44436 | /* 123576 */ GIR_RootConstrainSelectedInstOperands, |
| 44437 | /* 123577 */ // GIR_Coverage, 1369, |
| 44438 | /* 123577 */ GIR_EraseRootFromParent_Done, |
| 44439 | /* 123578 */ // Label 3737: @123578 |
| 44440 | /* 123578 */ GIM_Reject, |
| 44441 | /* 123579 */ // Label 3731: @123579 |
| 44442 | /* 123579 */ GIM_Try, /*On fail goto*//*Label 3738*/ GIMT_Encode4(123816), |
| 44443 | /* 123584 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44444 | /* 123587 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8, |
| 44445 | /* 123590 */ GIM_Try, /*On fail goto*//*Label 3739*/ GIMT_Encode4(123716), |
| 44446 | /* 123595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44447 | /* 123599 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3740*/ GIMT_Encode4(123657), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6652 // |
| 44448 | /* 123606 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44449 | /* 123610 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44450 | /* 123614 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44451 | /* 123618 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44452 | /* 123623 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44453 | /* 123627 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44454 | /* 123629 */ // (umax:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 44455 | /* 123629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8), |
| 44456 | /* 123632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44457 | /* 123634 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44458 | /* 123636 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44459 | /* 123640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44460 | /* 123643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44461 | /* 123649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44462 | /* 123655 */ GIR_RootConstrainSelectedInstOperands, |
| 44463 | /* 123656 */ // GIR_Coverage, 6652, |
| 44464 | /* 123656 */ GIR_EraseRootFromParent_Done, |
| 44465 | /* 123657 */ // Label 3740: @123657 |
| 44466 | /* 123657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3741*/ GIMT_Encode4(123715), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4093 // |
| 44467 | /* 123664 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44468 | /* 123668 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44469 | /* 123672 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44470 | /* 123676 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44471 | /* 123680 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44472 | /* 123685 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44473 | /* 123687 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm) |
| 44474 | /* 123687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8), |
| 44475 | /* 123690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44476 | /* 123692 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44477 | /* 123694 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44478 | /* 123698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44479 | /* 123701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44480 | /* 123707 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44481 | /* 123713 */ GIR_RootConstrainSelectedInstOperands, |
| 44482 | /* 123714 */ // GIR_Coverage, 4093, |
| 44483 | /* 123714 */ GIR_EraseRootFromParent_Done, |
| 44484 | /* 123715 */ // Label 3741: @123715 |
| 44485 | /* 123715 */ GIM_Reject, |
| 44486 | /* 123716 */ // Label 3739: @123716 |
| 44487 | /* 123716 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3742*/ GIMT_Encode4(123755), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1370 // |
| 44488 | /* 123723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44489 | /* 123727 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44490 | /* 123731 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44491 | /* 123735 */ // (umax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) |
| 44492 | /* 123735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv16i8), |
| 44493 | /* 123738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44494 | /* 123740 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44495 | /* 123742 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44496 | /* 123744 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44497 | /* 123747 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44498 | /* 123753 */ GIR_RootConstrainSelectedInstOperands, |
| 44499 | /* 123754 */ // GIR_Coverage, 1370, |
| 44500 | /* 123754 */ GIR_EraseRootFromParent_Done, |
| 44501 | /* 123755 */ // Label 3742: @123755 |
| 44502 | /* 123755 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3743*/ GIMT_Encode4(123815), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3715 // |
| 44503 | /* 123762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44504 | /* 123766 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44505 | /* 123770 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44506 | /* 123774 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) |
| 44507 | /* 123774 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44508 | /* 123777 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44509 | /* 123781 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44510 | /* 123786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu8), |
| 44511 | /* 123789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44512 | /* 123791 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44513 | /* 123793 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44514 | /* 123795 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44515 | /* 123798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44516 | /* 123804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44517 | /* 123810 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44518 | /* 123813 */ GIR_RootConstrainSelectedInstOperands, |
| 44519 | /* 123814 */ // GIR_Coverage, 3715, |
| 44520 | /* 123814 */ GIR_EraseRootFromParent_Done, |
| 44521 | /* 123815 */ // Label 3743: @123815 |
| 44522 | /* 123815 */ GIM_Reject, |
| 44523 | /* 123816 */ // Label 3738: @123816 |
| 44524 | /* 123816 */ GIM_Reject, |
| 44525 | /* 123817 */ // Label 3732: @123817 |
| 44526 | /* 123817 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3744*/ GIMT_Encode4(123862), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1365 // |
| 44527 | /* 123824 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44528 | /* 123827 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 44529 | /* 123830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44530 | /* 123834 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44531 | /* 123838 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44532 | /* 123842 */ // (umax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) |
| 44533 | /* 123842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i16), |
| 44534 | /* 123845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44535 | /* 123847 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44536 | /* 123849 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44537 | /* 123851 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44538 | /* 123854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44539 | /* 123860 */ GIR_RootConstrainSelectedInstOperands, |
| 44540 | /* 123861 */ // GIR_Coverage, 1365, |
| 44541 | /* 123861 */ GIR_EraseRootFromParent_Done, |
| 44542 | /* 123862 */ // Label 3744: @123862 |
| 44543 | /* 123862 */ GIM_Reject, |
| 44544 | /* 123863 */ // Label 3733: @123863 |
| 44545 | /* 123863 */ GIM_Try, /*On fail goto*//*Label 3745*/ GIMT_Encode4(124100), |
| 44546 | /* 123868 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44547 | /* 123871 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 44548 | /* 123874 */ GIM_Try, /*On fail goto*//*Label 3746*/ GIMT_Encode4(124000), |
| 44549 | /* 123879 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44550 | /* 123883 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3747*/ GIMT_Encode4(123941), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6653 // |
| 44551 | /* 123890 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44552 | /* 123894 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44553 | /* 123898 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44554 | /* 123902 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44555 | /* 123907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44556 | /* 123911 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44557 | /* 123913 */ // (umax:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 44558 | /* 123913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16), |
| 44559 | /* 123916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44560 | /* 123918 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44561 | /* 123920 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44562 | /* 123924 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44563 | /* 123927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44564 | /* 123933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44565 | /* 123939 */ GIR_RootConstrainSelectedInstOperands, |
| 44566 | /* 123940 */ // GIR_Coverage, 6653, |
| 44567 | /* 123940 */ GIR_EraseRootFromParent_Done, |
| 44568 | /* 123941 */ // Label 3747: @123941 |
| 44569 | /* 123941 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3748*/ GIMT_Encode4(123999), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4095 // |
| 44570 | /* 123948 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44571 | /* 123952 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44572 | /* 123956 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44573 | /* 123960 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44574 | /* 123964 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44575 | /* 123969 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44576 | /* 123971 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm) |
| 44577 | /* 123971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16), |
| 44578 | /* 123974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44579 | /* 123976 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44580 | /* 123978 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44581 | /* 123982 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44582 | /* 123985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44583 | /* 123991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44584 | /* 123997 */ GIR_RootConstrainSelectedInstOperands, |
| 44585 | /* 123998 */ // GIR_Coverage, 4095, |
| 44586 | /* 123998 */ GIR_EraseRootFromParent_Done, |
| 44587 | /* 123999 */ // Label 3748: @123999 |
| 44588 | /* 123999 */ GIM_Reject, |
| 44589 | /* 124000 */ // Label 3746: @124000 |
| 44590 | /* 124000 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3749*/ GIMT_Encode4(124039), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1367 // |
| 44591 | /* 124007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44592 | /* 124011 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44593 | /* 124015 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44594 | /* 124019 */ // (umax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) |
| 44595 | /* 124019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i16), |
| 44596 | /* 124022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44597 | /* 124024 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44598 | /* 124026 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44599 | /* 124028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44600 | /* 124031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44601 | /* 124037 */ GIR_RootConstrainSelectedInstOperands, |
| 44602 | /* 124038 */ // GIR_Coverage, 1367, |
| 44603 | /* 124038 */ GIR_EraseRootFromParent_Done, |
| 44604 | /* 124039 */ // Label 3749: @124039 |
| 44605 | /* 124039 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3750*/ GIMT_Encode4(124099), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3718 // |
| 44606 | /* 124046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44607 | /* 124050 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44608 | /* 124054 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44609 | /* 124058 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) |
| 44610 | /* 124058 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44611 | /* 124061 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44612 | /* 124065 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44613 | /* 124070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu16), |
| 44614 | /* 124073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44615 | /* 124075 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44616 | /* 124077 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44617 | /* 124079 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44618 | /* 124082 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44619 | /* 124088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44620 | /* 124094 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44621 | /* 124097 */ GIR_RootConstrainSelectedInstOperands, |
| 44622 | /* 124098 */ // GIR_Coverage, 3718, |
| 44623 | /* 124098 */ GIR_EraseRootFromParent_Done, |
| 44624 | /* 124099 */ // Label 3750: @124099 |
| 44625 | /* 124099 */ GIM_Reject, |
| 44626 | /* 124100 */ // Label 3745: @124100 |
| 44627 | /* 124100 */ GIM_Reject, |
| 44628 | /* 124101 */ // Label 3734: @124101 |
| 44629 | /* 124101 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3751*/ GIMT_Encode4(124146), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1366 // |
| 44630 | /* 124108 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 44631 | /* 124111 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 44632 | /* 124114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44633 | /* 124118 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44634 | /* 124122 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44635 | /* 124126 */ // (umax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) |
| 44636 | /* 124126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv2i32), |
| 44637 | /* 124129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44638 | /* 124131 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44639 | /* 124133 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44640 | /* 124135 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44641 | /* 124138 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44642 | /* 124144 */ GIR_RootConstrainSelectedInstOperands, |
| 44643 | /* 124145 */ // GIR_Coverage, 1366, |
| 44644 | /* 124145 */ GIR_EraseRootFromParent_Done, |
| 44645 | /* 124146 */ // Label 3751: @124146 |
| 44646 | /* 124146 */ GIM_Reject, |
| 44647 | /* 124147 */ // Label 3735: @124147 |
| 44648 | /* 124147 */ GIM_Try, /*On fail goto*//*Label 3752*/ GIMT_Encode4(124384), |
| 44649 | /* 124152 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44650 | /* 124155 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 44651 | /* 124158 */ GIM_Try, /*On fail goto*//*Label 3753*/ GIMT_Encode4(124284), |
| 44652 | /* 124163 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44653 | /* 124167 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3754*/ GIMT_Encode4(124225), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6654 // |
| 44654 | /* 124174 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 44655 | /* 124178 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44656 | /* 124182 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44657 | /* 124186 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44658 | /* 124191 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44659 | /* 124195 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44660 | /* 124197 */ // (umax:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 44661 | /* 124197 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32), |
| 44662 | /* 124200 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44663 | /* 124202 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd |
| 44664 | /* 124204 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44665 | /* 124208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44666 | /* 124211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44667 | /* 124217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44668 | /* 124223 */ GIR_RootConstrainSelectedInstOperands, |
| 44669 | /* 124224 */ // GIR_Coverage, 6654, |
| 44670 | /* 124224 */ GIR_EraseRootFromParent_Done, |
| 44671 | /* 124225 */ // Label 3754: @124225 |
| 44672 | /* 124225 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3755*/ GIMT_Encode4(124283), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4097 // |
| 44673 | /* 124232 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44674 | /* 124236 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 44675 | /* 124240 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS), |
| 44676 | /* 124244 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44677 | /* 124248 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44678 | /* 124253 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44679 | /* 124255 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm) |
| 44680 | /* 124255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32), |
| 44681 | /* 124258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44682 | /* 124260 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd |
| 44683 | /* 124262 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm |
| 44684 | /* 124266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44685 | /* 124269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44686 | /* 124275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44687 | /* 124281 */ GIR_RootConstrainSelectedInstOperands, |
| 44688 | /* 124282 */ // GIR_Coverage, 4097, |
| 44689 | /* 124282 */ GIR_EraseRootFromParent_Done, |
| 44690 | /* 124283 */ // Label 3755: @124283 |
| 44691 | /* 124283 */ GIM_Reject, |
| 44692 | /* 124284 */ // Label 3753: @124284 |
| 44693 | /* 124284 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3756*/ GIMT_Encode4(124323), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1368 // |
| 44694 | /* 124291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44695 | /* 124295 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44696 | /* 124299 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44697 | /* 124303 */ // (umax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) |
| 44698 | /* 124303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i32), |
| 44699 | /* 124306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44700 | /* 124308 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn |
| 44701 | /* 124310 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm |
| 44702 | /* 124312 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44703 | /* 124315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44704 | /* 124321 */ GIR_RootConstrainSelectedInstOperands, |
| 44705 | /* 124322 */ // GIR_Coverage, 1368, |
| 44706 | /* 124322 */ GIR_EraseRootFromParent_Done, |
| 44707 | /* 124323 */ // Label 3756: @124323 |
| 44708 | /* 124323 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3757*/ GIMT_Encode4(124383), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3721 // |
| 44709 | /* 124330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44710 | /* 124334 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44711 | /* 124338 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44712 | /* 124342 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) |
| 44713 | /* 124342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44714 | /* 124345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44715 | /* 124349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44716 | /* 124354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu32), |
| 44717 | /* 124357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44718 | /* 124359 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm |
| 44719 | /* 124361 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn |
| 44720 | /* 124363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44721 | /* 124366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44722 | /* 124372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44723 | /* 124378 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44724 | /* 124381 */ GIR_RootConstrainSelectedInstOperands, |
| 44725 | /* 124382 */ // GIR_Coverage, 3721, |
| 44726 | /* 124382 */ GIR_EraseRootFromParent_Done, |
| 44727 | /* 124383 */ // Label 3757: @124383 |
| 44728 | /* 124383 */ GIM_Reject, |
| 44729 | /* 124384 */ // Label 3752: @124384 |
| 44730 | /* 124384 */ GIM_Reject, |
| 44731 | /* 124385 */ // Label 3736: @124385 |
| 44732 | /* 124385 */ GIM_Reject, |
| 44733 | /* 124386 */ // Label 67: @124386 |
| 44734 | /* 124386 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3764*/ GIMT_Encode4(124823), |
| 44735 | /* 124397 */ /*GILLT_v8s8*//*Label 3758*/ GIMT_Encode4(124421), |
| 44736 | /* 124401 */ /*GILLT_v16s8*//*Label 3759*/ GIMT_Encode4(124458), |
| 44737 | /* 124405 */ /*GILLT_v4s16*//*Label 3760*/ GIMT_Encode4(124555), |
| 44738 | /* 124409 */ /*GILLT_v8s16*//*Label 3761*/ GIMT_Encode4(124592), |
| 44739 | /* 124413 */ /*GILLT_v2s32*//*Label 3762*/ GIMT_Encode4(124689), |
| 44740 | /* 124417 */ /*GILLT_v4s32*//*Label 3763*/ GIMT_Encode4(124726), |
| 44741 | /* 124421 */ // Label 3758: @124421 |
| 44742 | /* 124421 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3765*/ GIMT_Encode4(124457), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1670 // |
| 44743 | /* 124428 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44744 | /* 124431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44745 | /* 124435 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44746 | /* 124439 */ // (abs:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 44747 | /* 124439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i8), |
| 44748 | /* 124442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44749 | /* 124444 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44750 | /* 124446 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44751 | /* 124449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44752 | /* 124455 */ GIR_RootConstrainSelectedInstOperands, |
| 44753 | /* 124456 */ // GIR_Coverage, 1670, |
| 44754 | /* 124456 */ GIR_EraseRootFromParent_Done, |
| 44755 | /* 124457 */ // Label 3765: @124457 |
| 44756 | /* 124457 */ GIM_Reject, |
| 44757 | /* 124458 */ // Label 3759: @124458 |
| 44758 | /* 124458 */ GIM_Try, /*On fail goto*//*Label 3766*/ GIMT_Encode4(124554), |
| 44759 | /* 124463 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44760 | /* 124466 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3767*/ GIMT_Encode4(124499), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1673 // |
| 44761 | /* 124473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44762 | /* 124477 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44763 | /* 124481 */ // (abs:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 44764 | /* 124481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv16i8), |
| 44765 | /* 124484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44766 | /* 124486 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44767 | /* 124488 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44768 | /* 124491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44769 | /* 124497 */ GIR_RootConstrainSelectedInstOperands, |
| 44770 | /* 124498 */ // GIR_Coverage, 1673, |
| 44771 | /* 124498 */ GIR_EraseRootFromParent_Done, |
| 44772 | /* 124499 */ // Label 3767: @124499 |
| 44773 | /* 124499 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3768*/ GIMT_Encode4(124553), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4054 // |
| 44774 | /* 124506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44775 | /* 124510 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44776 | /* 124514 */ // (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v) => (MVE_VABSs8:{ *:[v16i8] } ?:{ *:[v16i8] }:$v) |
| 44777 | /* 124514 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44778 | /* 124517 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44779 | /* 124521 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44780 | /* 124526 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs8), |
| 44781 | /* 124529 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44782 | /* 124531 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 44783 | /* 124533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44784 | /* 124536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44785 | /* 124542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44786 | /* 124548 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44787 | /* 124551 */ GIR_RootConstrainSelectedInstOperands, |
| 44788 | /* 124552 */ // GIR_Coverage, 4054, |
| 44789 | /* 124552 */ GIR_EraseRootFromParent_Done, |
| 44790 | /* 124553 */ // Label 3768: @124553 |
| 44791 | /* 124553 */ GIM_Reject, |
| 44792 | /* 124554 */ // Label 3766: @124554 |
| 44793 | /* 124554 */ GIM_Reject, |
| 44794 | /* 124555 */ // Label 3760: @124555 |
| 44795 | /* 124555 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3769*/ GIMT_Encode4(124591), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1671 // |
| 44796 | /* 124562 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44797 | /* 124565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44798 | /* 124569 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44799 | /* 124573 */ // (abs:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 44800 | /* 124573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i16), |
| 44801 | /* 124576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44802 | /* 124578 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44803 | /* 124580 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44804 | /* 124583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44805 | /* 124589 */ GIR_RootConstrainSelectedInstOperands, |
| 44806 | /* 124590 */ // GIR_Coverage, 1671, |
| 44807 | /* 124590 */ GIR_EraseRootFromParent_Done, |
| 44808 | /* 124591 */ // Label 3769: @124591 |
| 44809 | /* 124591 */ GIM_Reject, |
| 44810 | /* 124592 */ // Label 3761: @124592 |
| 44811 | /* 124592 */ GIM_Try, /*On fail goto*//*Label 3770*/ GIMT_Encode4(124688), |
| 44812 | /* 124597 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 44813 | /* 124600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3771*/ GIMT_Encode4(124633), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1674 // |
| 44814 | /* 124607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44815 | /* 124611 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44816 | /* 124615 */ // (abs:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 44817 | /* 124615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i16), |
| 44818 | /* 124618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44819 | /* 124620 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44820 | /* 124622 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44821 | /* 124625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44822 | /* 124631 */ GIR_RootConstrainSelectedInstOperands, |
| 44823 | /* 124632 */ // GIR_Coverage, 1674, |
| 44824 | /* 124632 */ GIR_EraseRootFromParent_Done, |
| 44825 | /* 124633 */ // Label 3771: @124633 |
| 44826 | /* 124633 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3772*/ GIMT_Encode4(124687), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4060 // |
| 44827 | /* 124640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44828 | /* 124644 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44829 | /* 124648 */ // (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v) => (MVE_VABSs16:{ *:[v8i16] } ?:{ *:[v8i16] }:$v) |
| 44830 | /* 124648 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44831 | /* 124651 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44832 | /* 124655 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44833 | /* 124660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs16), |
| 44834 | /* 124663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44835 | /* 124665 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 44836 | /* 124667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44837 | /* 124670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44838 | /* 124676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44839 | /* 124682 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44840 | /* 124685 */ GIR_RootConstrainSelectedInstOperands, |
| 44841 | /* 124686 */ // GIR_Coverage, 4060, |
| 44842 | /* 124686 */ GIR_EraseRootFromParent_Done, |
| 44843 | /* 124687 */ // Label 3772: @124687 |
| 44844 | /* 124687 */ GIM_Reject, |
| 44845 | /* 124688 */ // Label 3770: @124688 |
| 44846 | /* 124688 */ GIM_Reject, |
| 44847 | /* 124689 */ // Label 3762: @124689 |
| 44848 | /* 124689 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3773*/ GIMT_Encode4(124725), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1672 // |
| 44849 | /* 124696 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 44850 | /* 124699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44851 | /* 124703 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44852 | /* 124707 */ // (abs:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 44853 | /* 124707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv2i32), |
| 44854 | /* 124710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44855 | /* 124712 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44856 | /* 124714 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44857 | /* 124717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44858 | /* 124723 */ GIR_RootConstrainSelectedInstOperands, |
| 44859 | /* 124724 */ // GIR_Coverage, 1672, |
| 44860 | /* 124724 */ GIR_EraseRootFromParent_Done, |
| 44861 | /* 124725 */ // Label 3773: @124725 |
| 44862 | /* 124725 */ GIM_Reject, |
| 44863 | /* 124726 */ // Label 3763: @124726 |
| 44864 | /* 124726 */ GIM_Try, /*On fail goto*//*Label 3774*/ GIMT_Encode4(124822), |
| 44865 | /* 124731 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 44866 | /* 124734 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3775*/ GIMT_Encode4(124767), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1675 // |
| 44867 | /* 124741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44868 | /* 124745 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 44869 | /* 124749 */ // (abs:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 44870 | /* 124749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i32), |
| 44871 | /* 124752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 44872 | /* 124754 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 44873 | /* 124756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44874 | /* 124759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44875 | /* 124765 */ GIR_RootConstrainSelectedInstOperands, |
| 44876 | /* 124766 */ // GIR_Coverage, 1675, |
| 44877 | /* 124766 */ GIR_EraseRootFromParent_Done, |
| 44878 | /* 124767 */ // Label 3775: @124767 |
| 44879 | /* 124767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3776*/ GIMT_Encode4(124821), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4066 // |
| 44880 | /* 124774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44881 | /* 124778 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44882 | /* 124782 */ // (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v) => (MVE_VABSs32:{ *:[v4i32] } ?:{ *:[v4i32] }:$v) |
| 44883 | /* 124782 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 44884 | /* 124785 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 44885 | /* 124789 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 44886 | /* 124794 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs32), |
| 44887 | /* 124797 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44888 | /* 124799 */ GIR_RootToRootCopy, /*OpIdx*/1, // v |
| 44889 | /* 124801 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44890 | /* 124804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44891 | /* 124810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44892 | /* 124816 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 44893 | /* 124819 */ GIR_RootConstrainSelectedInstOperands, |
| 44894 | /* 124820 */ // GIR_Coverage, 4066, |
| 44895 | /* 124820 */ GIR_EraseRootFromParent_Done, |
| 44896 | /* 124821 */ // Label 3776: @124821 |
| 44897 | /* 124821 */ GIM_Reject, |
| 44898 | /* 124822 */ // Label 3774: @124822 |
| 44899 | /* 124822 */ GIM_Reject, |
| 44900 | /* 124823 */ // Label 3764: @124823 |
| 44901 | /* 124823 */ GIM_Reject, |
| 44902 | /* 124824 */ // Label 68: @124824 |
| 44903 | /* 124824 */ GIM_Try, /*On fail goto*//*Label 3777*/ GIMT_Encode4(124893), |
| 44904 | /* 124829 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/0, |
| 44905 | /* 124832 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3778*/ GIMT_Encode4(124846), GIMT_Encode2(GIFBS_IsARM), // Rule ID 31 // |
| 44906 | /* 124839 */ // (br (bb:{ *:[Other] }):$target) => (B (bb:{ *:[Other] }):$target) |
| 44907 | /* 124839 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::B), |
| 44908 | /* 124844 */ GIR_RootConstrainSelectedInstOperands, |
| 44909 | /* 124845 */ // GIR_Coverage, 31, |
| 44910 | /* 124845 */ GIR_Done, |
| 44911 | /* 124846 */ // Label 3778: @124846 |
| 44912 | /* 124846 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3779*/ GIMT_Encode4(124869), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 282 // |
| 44913 | /* 124853 */ // (br (bb:{ *:[Other] }):$target) => (tB (bb:{ *:[Other] }):$target) |
| 44914 | /* 124853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tB), |
| 44915 | /* 124856 */ GIR_RootToRootCopy, /*OpIdx*/0, // target |
| 44916 | /* 124858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44917 | /* 124861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44918 | /* 124867 */ GIR_RootConstrainSelectedInstOperands, |
| 44919 | /* 124868 */ // GIR_Coverage, 282, |
| 44920 | /* 124868 */ GIR_EraseRootFromParent_Done, |
| 44921 | /* 124869 */ // Label 3779: @124869 |
| 44922 | /* 124869 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3780*/ GIMT_Encode4(124892), GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb), // Rule ID 576 // |
| 44923 | /* 124876 */ // (br (bb:{ *:[Other] }):$target) => (t2B (bb:{ *:[Other] }):$target) |
| 44924 | /* 124876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2B), |
| 44925 | /* 124879 */ GIR_RootToRootCopy, /*OpIdx*/0, // target |
| 44926 | /* 124881 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44927 | /* 124884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44928 | /* 124890 */ GIR_RootConstrainSelectedInstOperands, |
| 44929 | /* 124891 */ // GIR_Coverage, 576, |
| 44930 | /* 124891 */ GIR_EraseRootFromParent_Done, |
| 44931 | /* 124892 */ // Label 3780: @124892 |
| 44932 | /* 124892 */ GIM_Reject, |
| 44933 | /* 124893 */ // Label 3777: @124893 |
| 44934 | /* 124893 */ GIM_Reject, |
| 44935 | /* 124894 */ // Label 69: @124894 |
| 44936 | /* 124894 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(11), /*)*//*default:*//*Label 3785*/ GIMT_Encode4(125169), |
| 44937 | /* 124905 */ /*GILLT_v8s8*//*Label 3781*/ GIMT_Encode4(124921), |
| 44938 | /* 124909 */ /*GILLT_v16s8*//*Label 3782*/ GIMT_Encode4(124983), |
| 44939 | /* 124913 */ /*GILLT_v4s16*//*Label 3783*/ GIMT_Encode4(125045), |
| 44940 | /* 124917 */ /*GILLT_v8s16*//*Label 3784*/ GIMT_Encode4(125107), |
| 44941 | /* 124921 */ // Label 3781: @124921 |
| 44942 | /* 124921 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3786*/ GIMT_Encode4(124982), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1733 // |
| 44943 | /* 124928 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 44944 | /* 124931 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 44945 | /* 124934 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44946 | /* 124937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44947 | /* 124941 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44948 | /* 124945 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 44949 | /* 124949 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 44950 | /* 124953 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 44951 | /* 124957 */ // MIs[1] Operand 1 |
| 44952 | /* 124957 */ // No operand predicates |
| 44953 | /* 124957 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44954 | /* 124959 */ // (vector_insert:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) |
| 44955 | /* 124959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi8), |
| 44956 | /* 124962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V] |
| 44957 | /* 124964 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 44958 | /* 124966 */ GIR_RootToRootCopy, /*OpIdx*/2, // R |
| 44959 | /* 124968 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 44960 | /* 124971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44961 | /* 124974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44962 | /* 124980 */ GIR_RootConstrainSelectedInstOperands, |
| 44963 | /* 124981 */ // GIR_Coverage, 1733, |
| 44964 | /* 124981 */ GIR_EraseRootFromParent_Done, |
| 44965 | /* 124982 */ // Label 3786: @124982 |
| 44966 | /* 124982 */ GIM_Reject, |
| 44967 | /* 124983 */ // Label 3782: @124983 |
| 44968 | /* 124983 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3787*/ GIMT_Encode4(125044), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3829 // |
| 44969 | /* 124990 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 44970 | /* 124993 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 44971 | /* 124996 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44972 | /* 124999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44973 | /* 125003 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 44974 | /* 125007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 44975 | /* 125011 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 44976 | /* 125015 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 44977 | /* 125019 */ // MIs[1] Operand 1 |
| 44978 | /* 125019 */ // No operand predicates |
| 44979 | /* 125019 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44980 | /* 125021 */ // (vector_insert:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) |
| 44981 | /* 125021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_8), |
| 44982 | /* 125024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 44983 | /* 125026 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 44984 | /* 125028 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 44985 | /* 125030 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 44986 | /* 125033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 44987 | /* 125036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 44988 | /* 125042 */ GIR_RootConstrainSelectedInstOperands, |
| 44989 | /* 125043 */ // GIR_Coverage, 3829, |
| 44990 | /* 125043 */ GIR_EraseRootFromParent_Done, |
| 44991 | /* 125044 */ // Label 3787: @125044 |
| 44992 | /* 125044 */ GIM_Reject, |
| 44993 | /* 125045 */ // Label 3783: @125045 |
| 44994 | /* 125045 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3788*/ GIMT_Encode4(125106), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1734 // |
| 44995 | /* 125052 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 44996 | /* 125055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 44997 | /* 125058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 44998 | /* 125061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 44999 | /* 125065 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45000 | /* 125069 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45001 | /* 125073 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 45002 | /* 125077 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 45003 | /* 125081 */ // MIs[1] Operand 1 |
| 45004 | /* 125081 */ // No operand predicates |
| 45005 | /* 125081 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45006 | /* 125083 */ // (vector_insert:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) |
| 45007 | /* 125083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi16), |
| 45008 | /* 125086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V] |
| 45009 | /* 125088 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 45010 | /* 125090 */ GIR_RootToRootCopy, /*OpIdx*/2, // R |
| 45011 | /* 125092 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 45012 | /* 125095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45013 | /* 125098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45014 | /* 125104 */ GIR_RootConstrainSelectedInstOperands, |
| 45015 | /* 125105 */ // GIR_Coverage, 1734, |
| 45016 | /* 125105 */ GIR_EraseRootFromParent_Done, |
| 45017 | /* 125106 */ // Label 3788: @125106 |
| 45018 | /* 125106 */ GIM_Reject, |
| 45019 | /* 125107 */ // Label 3784: @125107 |
| 45020 | /* 125107 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3789*/ GIMT_Encode4(125168), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3830 // |
| 45021 | /* 125114 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45022 | /* 125117 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 45023 | /* 125120 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 45024 | /* 125123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45025 | /* 125127 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45026 | /* 125131 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45027 | /* 125135 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 45028 | /* 125139 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 45029 | /* 125143 */ // MIs[1] Operand 1 |
| 45030 | /* 125143 */ // No operand predicates |
| 45031 | /* 125143 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45032 | /* 125145 */ // (vector_insert:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) |
| 45033 | /* 125145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_16), |
| 45034 | /* 125148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45035 | /* 125150 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 45036 | /* 125152 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 45037 | /* 125154 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 45038 | /* 125157 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45039 | /* 125160 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45040 | /* 125166 */ GIR_RootConstrainSelectedInstOperands, |
| 45041 | /* 125167 */ // GIR_Coverage, 3830, |
| 45042 | /* 125167 */ GIR_EraseRootFromParent_Done, |
| 45043 | /* 125168 */ // Label 3789: @125168 |
| 45044 | /* 125168 */ GIM_Reject, |
| 45045 | /* 125169 */ // Label 3785: @125169 |
| 45046 | /* 125169 */ GIM_Reject, |
| 45047 | /* 125170 */ // Label 70: @125170 |
| 45048 | /* 125170 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3790*/ GIMT_Encode4(125225), GIMT_Encode2(GIFBS_HasFPRegs_HasFastVGETLNi32), // Rule ID 1732 // |
| 45049 | /* 125177 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 45050 | /* 125180 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45051 | /* 125183 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 45052 | /* 125186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45053 | /* 125190 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45054 | /* 125194 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 45055 | /* 125198 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 45056 | /* 125202 */ // MIs[1] Operand 1 |
| 45057 | /* 125202 */ // No operand predicates |
| 45058 | /* 125202 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45059 | /* 125204 */ // (extractelt:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane) => (VGETLNi32:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane) |
| 45060 | /* 125204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VGETLNi32), |
| 45061 | /* 125207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[R] |
| 45062 | /* 125209 */ GIR_RootToRootCopy, /*OpIdx*/1, // V |
| 45063 | /* 125211 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane |
| 45064 | /* 125214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45065 | /* 125217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45066 | /* 125223 */ GIR_RootConstrainSelectedInstOperands, |
| 45067 | /* 125224 */ // GIR_Coverage, 1732, |
| 45068 | /* 125224 */ GIR_EraseRootFromParent_Done, |
| 45069 | /* 125225 */ // Label 3790: @125225 |
| 45070 | /* 125225 */ GIM_Reject, |
| 45071 | /* 125226 */ // Label 71: @125226 |
| 45072 | /* 125226 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3798*/ GIMT_Encode4(125763), |
| 45073 | /* 125237 */ /*GILLT_s32*//*Label 3791*/ GIMT_Encode4(125285), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45074 | /* 125261 */ /*GILLT_v8s8*//*Label 3792*/ GIMT_Encode4(125361), |
| 45075 | /* 125265 */ /*GILLT_v16s8*//*Label 3793*/ GIMT_Encode4(125398), |
| 45076 | /* 125269 */ /*GILLT_v4s16*//*Label 3794*/ GIMT_Encode4(125495), |
| 45077 | /* 125273 */ /*GILLT_v8s16*//*Label 3795*/ GIMT_Encode4(125532), |
| 45078 | /* 125277 */ /*GILLT_v2s32*//*Label 3796*/ GIMT_Encode4(125629), |
| 45079 | /* 125281 */ /*GILLT_v4s32*//*Label 3797*/ GIMT_Encode4(125666), |
| 45080 | /* 125285 */ // Label 3791: @125285 |
| 45081 | /* 125285 */ GIM_Try, /*On fail goto*//*Label 3799*/ GIMT_Encode4(125360), |
| 45082 | /* 125290 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45083 | /* 125293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3800*/ GIMT_Encode4(125326), GIMT_Encode2(GIFBS_HasV5T_IsARM), // Rule ID 196 // |
| 45084 | /* 125300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45085 | /* 125304 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45086 | /* 125308 */ // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 45087 | /* 125308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLZ), |
| 45088 | /* 125311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45089 | /* 125313 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45090 | /* 125315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45091 | /* 125318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45092 | /* 125324 */ GIR_RootConstrainSelectedInstOperands, |
| 45093 | /* 125325 */ // GIR_Coverage, 196, |
| 45094 | /* 125325 */ GIR_EraseRootFromParent_Done, |
| 45095 | /* 125326 */ // Label 3800: @125326 |
| 45096 | /* 125326 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3801*/ GIMT_Encode4(125359), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 533 // |
| 45097 | /* 125333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45098 | /* 125337 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45099 | /* 125341 */ // (ctlz:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2CLZ:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 45100 | /* 125341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLZ), |
| 45101 | /* 125344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45102 | /* 125346 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45103 | /* 125348 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45104 | /* 125351 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45105 | /* 125357 */ GIR_RootConstrainSelectedInstOperands, |
| 45106 | /* 125358 */ // GIR_Coverage, 533, |
| 45107 | /* 125358 */ GIR_EraseRootFromParent_Done, |
| 45108 | /* 125359 */ // Label 3801: @125359 |
| 45109 | /* 125359 */ GIM_Reject, |
| 45110 | /* 125360 */ // Label 3799: @125360 |
| 45111 | /* 125360 */ GIM_Reject, |
| 45112 | /* 125361 */ // Label 3792: @125361 |
| 45113 | /* 125361 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3802*/ GIMT_Encode4(125397), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1708 // |
| 45114 | /* 125368 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 45115 | /* 125371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45116 | /* 125375 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45117 | /* 125379 */ // (ctlz:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLZv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 45118 | /* 125379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i8), |
| 45119 | /* 125382 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45120 | /* 125384 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45121 | /* 125386 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45122 | /* 125389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45123 | /* 125395 */ GIR_RootConstrainSelectedInstOperands, |
| 45124 | /* 125396 */ // GIR_Coverage, 1708, |
| 45125 | /* 125396 */ GIR_EraseRootFromParent_Done, |
| 45126 | /* 125397 */ // Label 3802: @125397 |
| 45127 | /* 125397 */ GIM_Reject, |
| 45128 | /* 125398 */ // Label 3793: @125398 |
| 45129 | /* 125398 */ GIM_Try, /*On fail goto*//*Label 3803*/ GIMT_Encode4(125494), |
| 45130 | /* 125403 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 45131 | /* 125406 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3804*/ GIMT_Encode4(125439), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1711 // |
| 45132 | /* 125413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45133 | /* 125417 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45134 | /* 125421 */ // (ctlz:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLZv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 45135 | /* 125421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv16i8), |
| 45136 | /* 125424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45137 | /* 125426 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45138 | /* 125428 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45139 | /* 125431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45140 | /* 125437 */ GIR_RootConstrainSelectedInstOperands, |
| 45141 | /* 125438 */ // GIR_Coverage, 1711, |
| 45142 | /* 125438 */ GIR_EraseRootFromParent_Done, |
| 45143 | /* 125439 */ // Label 3804: @125439 |
| 45144 | /* 125439 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3805*/ GIMT_Encode4(125493), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4048 // |
| 45145 | /* 125446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45146 | /* 125450 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45147 | /* 125454 */ // (ctlz:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLZs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) |
| 45148 | /* 125454 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45149 | /* 125457 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45150 | /* 125461 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45151 | /* 125466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs8), |
| 45152 | /* 125469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45153 | /* 125471 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45154 | /* 125473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45155 | /* 125476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45156 | /* 125482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45157 | /* 125488 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45158 | /* 125491 */ GIR_RootConstrainSelectedInstOperands, |
| 45159 | /* 125492 */ // GIR_Coverage, 4048, |
| 45160 | /* 125492 */ GIR_EraseRootFromParent_Done, |
| 45161 | /* 125493 */ // Label 3805: @125493 |
| 45162 | /* 125493 */ GIM_Reject, |
| 45163 | /* 125494 */ // Label 3803: @125494 |
| 45164 | /* 125494 */ GIM_Reject, |
| 45165 | /* 125495 */ // Label 3794: @125495 |
| 45166 | /* 125495 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3806*/ GIMT_Encode4(125531), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1709 // |
| 45167 | /* 125502 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45168 | /* 125505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45169 | /* 125509 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45170 | /* 125513 */ // (ctlz:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLZv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 45171 | /* 125513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i16), |
| 45172 | /* 125516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45173 | /* 125518 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45174 | /* 125520 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45175 | /* 125523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45176 | /* 125529 */ GIR_RootConstrainSelectedInstOperands, |
| 45177 | /* 125530 */ // GIR_Coverage, 1709, |
| 45178 | /* 125530 */ GIR_EraseRootFromParent_Done, |
| 45179 | /* 125531 */ // Label 3806: @125531 |
| 45180 | /* 125531 */ GIM_Reject, |
| 45181 | /* 125532 */ // Label 3795: @125532 |
| 45182 | /* 125532 */ GIM_Try, /*On fail goto*//*Label 3807*/ GIMT_Encode4(125628), |
| 45183 | /* 125537 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45184 | /* 125540 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3808*/ GIMT_Encode4(125573), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1712 // |
| 45185 | /* 125547 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45186 | /* 125551 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45187 | /* 125555 */ // (ctlz:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLZv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 45188 | /* 125555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i16), |
| 45189 | /* 125558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45190 | /* 125560 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45191 | /* 125562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45192 | /* 125565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45193 | /* 125571 */ GIR_RootConstrainSelectedInstOperands, |
| 45194 | /* 125572 */ // GIR_Coverage, 1712, |
| 45195 | /* 125572 */ GIR_EraseRootFromParent_Done, |
| 45196 | /* 125573 */ // Label 3808: @125573 |
| 45197 | /* 125573 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3809*/ GIMT_Encode4(125627), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4050 // |
| 45198 | /* 125580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45199 | /* 125584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45200 | /* 125588 */ // (ctlz:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLZs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) |
| 45201 | /* 125588 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45202 | /* 125591 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45203 | /* 125595 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45204 | /* 125600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs16), |
| 45205 | /* 125603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45206 | /* 125605 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45207 | /* 125607 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45208 | /* 125610 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45209 | /* 125616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45210 | /* 125622 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45211 | /* 125625 */ GIR_RootConstrainSelectedInstOperands, |
| 45212 | /* 125626 */ // GIR_Coverage, 4050, |
| 45213 | /* 125626 */ GIR_EraseRootFromParent_Done, |
| 45214 | /* 125627 */ // Label 3809: @125627 |
| 45215 | /* 125627 */ GIM_Reject, |
| 45216 | /* 125628 */ // Label 3807: @125628 |
| 45217 | /* 125628 */ GIM_Reject, |
| 45218 | /* 125629 */ // Label 3796: @125629 |
| 45219 | /* 125629 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3810*/ GIMT_Encode4(125665), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1710 // |
| 45220 | /* 125636 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45221 | /* 125639 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45222 | /* 125643 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45223 | /* 125647 */ // (ctlz:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLZv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 45224 | /* 125647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv2i32), |
| 45225 | /* 125650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45226 | /* 125652 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45227 | /* 125654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45228 | /* 125657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45229 | /* 125663 */ GIR_RootConstrainSelectedInstOperands, |
| 45230 | /* 125664 */ // GIR_Coverage, 1710, |
| 45231 | /* 125664 */ GIR_EraseRootFromParent_Done, |
| 45232 | /* 125665 */ // Label 3810: @125665 |
| 45233 | /* 125665 */ GIM_Reject, |
| 45234 | /* 125666 */ // Label 3797: @125666 |
| 45235 | /* 125666 */ GIM_Try, /*On fail goto*//*Label 3811*/ GIMT_Encode4(125762), |
| 45236 | /* 125671 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45237 | /* 125674 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3812*/ GIMT_Encode4(125707), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1713 // |
| 45238 | /* 125681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45239 | /* 125685 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45240 | /* 125689 */ // (ctlz:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLZv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 45241 | /* 125689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i32), |
| 45242 | /* 125692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45243 | /* 125694 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45244 | /* 125696 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45245 | /* 125699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45246 | /* 125705 */ GIR_RootConstrainSelectedInstOperands, |
| 45247 | /* 125706 */ // GIR_Coverage, 1713, |
| 45248 | /* 125706 */ GIR_EraseRootFromParent_Done, |
| 45249 | /* 125707 */ // Label 3812: @125707 |
| 45250 | /* 125707 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3813*/ GIMT_Encode4(125761), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4052 // |
| 45251 | /* 125714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45252 | /* 125718 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45253 | /* 125722 */ // (ctlz:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLZs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) |
| 45254 | /* 125722 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45255 | /* 125725 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45256 | /* 125729 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45257 | /* 125734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs32), |
| 45258 | /* 125737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45259 | /* 125739 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45260 | /* 125741 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45261 | /* 125744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45262 | /* 125750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45263 | /* 125756 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45264 | /* 125759 */ GIR_RootConstrainSelectedInstOperands, |
| 45265 | /* 125760 */ // GIR_Coverage, 4052, |
| 45266 | /* 125760 */ GIR_EraseRootFromParent_Done, |
| 45267 | /* 125761 */ // Label 3813: @125761 |
| 45268 | /* 125761 */ GIM_Reject, |
| 45269 | /* 125762 */ // Label 3811: @125762 |
| 45270 | /* 125762 */ GIM_Reject, |
| 45271 | /* 125763 */ // Label 3798: @125763 |
| 45272 | /* 125763 */ GIM_Reject, |
| 45273 | /* 125764 */ // Label 72: @125764 |
| 45274 | /* 125764 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3820*/ GIMT_Encode4(126201), |
| 45275 | /* 125775 */ /*GILLT_v8s8*//*Label 3814*/ GIMT_Encode4(125799), |
| 45276 | /* 125779 */ /*GILLT_v16s8*//*Label 3815*/ GIMT_Encode4(125836), |
| 45277 | /* 125783 */ /*GILLT_v4s16*//*Label 3816*/ GIMT_Encode4(125933), |
| 45278 | /* 125787 */ /*GILLT_v8s16*//*Label 3817*/ GIMT_Encode4(125970), |
| 45279 | /* 125791 */ /*GILLT_v2s32*//*Label 3818*/ GIMT_Encode4(126067), |
| 45280 | /* 125795 */ /*GILLT_v4s32*//*Label 3819*/ GIMT_Encode4(126104), |
| 45281 | /* 125799 */ // Label 3814: @125799 |
| 45282 | /* 125799 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3821*/ GIMT_Encode4(125835), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1702 // |
| 45283 | /* 125806 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 45284 | /* 125809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45285 | /* 125813 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45286 | /* 125817 */ // (ctls:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 45287 | /* 125817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i8), |
| 45288 | /* 125820 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45289 | /* 125822 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45290 | /* 125824 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45291 | /* 125827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45292 | /* 125833 */ GIR_RootConstrainSelectedInstOperands, |
| 45293 | /* 125834 */ // GIR_Coverage, 1702, |
| 45294 | /* 125834 */ GIR_EraseRootFromParent_Done, |
| 45295 | /* 125835 */ // Label 3821: @125835 |
| 45296 | /* 125835 */ GIM_Reject, |
| 45297 | /* 125836 */ // Label 3815: @125836 |
| 45298 | /* 125836 */ GIM_Try, /*On fail goto*//*Label 3822*/ GIMT_Encode4(125932), |
| 45299 | /* 125841 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 45300 | /* 125844 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3823*/ GIMT_Encode4(125877), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1705 // |
| 45301 | /* 125851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45302 | /* 125855 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45303 | /* 125859 */ // (ctls:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 45304 | /* 125859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv16i8), |
| 45305 | /* 125862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45306 | /* 125864 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45307 | /* 125866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45308 | /* 125869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45309 | /* 125875 */ GIR_RootConstrainSelectedInstOperands, |
| 45310 | /* 125876 */ // GIR_Coverage, 1705, |
| 45311 | /* 125876 */ GIR_EraseRootFromParent_Done, |
| 45312 | /* 125877 */ // Label 3823: @125877 |
| 45313 | /* 125877 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3824*/ GIMT_Encode4(125931), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4042 // |
| 45314 | /* 125884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45315 | /* 125888 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45316 | /* 125892 */ // (ctls:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLSs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) |
| 45317 | /* 125892 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45318 | /* 125895 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45319 | /* 125899 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45320 | /* 125904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs8), |
| 45321 | /* 125907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45322 | /* 125909 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45323 | /* 125911 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45324 | /* 125914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45325 | /* 125920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45326 | /* 125926 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45327 | /* 125929 */ GIR_RootConstrainSelectedInstOperands, |
| 45328 | /* 125930 */ // GIR_Coverage, 4042, |
| 45329 | /* 125930 */ GIR_EraseRootFromParent_Done, |
| 45330 | /* 125931 */ // Label 3824: @125931 |
| 45331 | /* 125931 */ GIM_Reject, |
| 45332 | /* 125932 */ // Label 3822: @125932 |
| 45333 | /* 125932 */ GIM_Reject, |
| 45334 | /* 125933 */ // Label 3816: @125933 |
| 45335 | /* 125933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3825*/ GIMT_Encode4(125969), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1703 // |
| 45336 | /* 125940 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45337 | /* 125943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45338 | /* 125947 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45339 | /* 125951 */ // (ctls:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) |
| 45340 | /* 125951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i16), |
| 45341 | /* 125954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45342 | /* 125956 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45343 | /* 125958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45344 | /* 125961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45345 | /* 125967 */ GIR_RootConstrainSelectedInstOperands, |
| 45346 | /* 125968 */ // GIR_Coverage, 1703, |
| 45347 | /* 125968 */ GIR_EraseRootFromParent_Done, |
| 45348 | /* 125969 */ // Label 3825: @125969 |
| 45349 | /* 125969 */ GIM_Reject, |
| 45350 | /* 125970 */ // Label 3817: @125970 |
| 45351 | /* 125970 */ GIM_Try, /*On fail goto*//*Label 3826*/ GIMT_Encode4(126066), |
| 45352 | /* 125975 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45353 | /* 125978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3827*/ GIMT_Encode4(126011), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1706 // |
| 45354 | /* 125985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45355 | /* 125989 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45356 | /* 125993 */ // (ctls:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) |
| 45357 | /* 125993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i16), |
| 45358 | /* 125996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45359 | /* 125998 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45360 | /* 126000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45361 | /* 126003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45362 | /* 126009 */ GIR_RootConstrainSelectedInstOperands, |
| 45363 | /* 126010 */ // GIR_Coverage, 1706, |
| 45364 | /* 126010 */ GIR_EraseRootFromParent_Done, |
| 45365 | /* 126011 */ // Label 3827: @126011 |
| 45366 | /* 126011 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3828*/ GIMT_Encode4(126065), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4044 // |
| 45367 | /* 126018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45368 | /* 126022 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45369 | /* 126026 */ // (ctls:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLSs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) |
| 45370 | /* 126026 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45371 | /* 126029 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45372 | /* 126033 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45373 | /* 126038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs16), |
| 45374 | /* 126041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45375 | /* 126043 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45376 | /* 126045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45377 | /* 126048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45378 | /* 126054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45379 | /* 126060 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45380 | /* 126063 */ GIR_RootConstrainSelectedInstOperands, |
| 45381 | /* 126064 */ // GIR_Coverage, 4044, |
| 45382 | /* 126064 */ GIR_EraseRootFromParent_Done, |
| 45383 | /* 126065 */ // Label 3828: @126065 |
| 45384 | /* 126065 */ GIM_Reject, |
| 45385 | /* 126066 */ // Label 3826: @126066 |
| 45386 | /* 126066 */ GIM_Reject, |
| 45387 | /* 126067 */ // Label 3818: @126067 |
| 45388 | /* 126067 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3829*/ GIMT_Encode4(126103), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1704 // |
| 45389 | /* 126074 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45390 | /* 126077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45391 | /* 126081 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45392 | /* 126085 */ // (ctls:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) |
| 45393 | /* 126085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv2i32), |
| 45394 | /* 126088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45395 | /* 126090 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45396 | /* 126092 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45397 | /* 126095 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45398 | /* 126101 */ GIR_RootConstrainSelectedInstOperands, |
| 45399 | /* 126102 */ // GIR_Coverage, 1704, |
| 45400 | /* 126102 */ GIR_EraseRootFromParent_Done, |
| 45401 | /* 126103 */ // Label 3829: @126103 |
| 45402 | /* 126103 */ GIM_Reject, |
| 45403 | /* 126104 */ // Label 3819: @126104 |
| 45404 | /* 126104 */ GIM_Try, /*On fail goto*//*Label 3830*/ GIMT_Encode4(126200), |
| 45405 | /* 126109 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45406 | /* 126112 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3831*/ GIMT_Encode4(126145), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1707 // |
| 45407 | /* 126119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45408 | /* 126123 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45409 | /* 126127 */ // (ctls:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) |
| 45410 | /* 126127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i32), |
| 45411 | /* 126130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45412 | /* 126132 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45413 | /* 126134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45414 | /* 126137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45415 | /* 126143 */ GIR_RootConstrainSelectedInstOperands, |
| 45416 | /* 126144 */ // GIR_Coverage, 1707, |
| 45417 | /* 126144 */ GIR_EraseRootFromParent_Done, |
| 45418 | /* 126145 */ // Label 3831: @126145 |
| 45419 | /* 126145 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3832*/ GIMT_Encode4(126199), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4046 // |
| 45420 | /* 126152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45421 | /* 126156 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45422 | /* 126160 */ // (ctls:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLSs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) |
| 45423 | /* 126160 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45424 | /* 126163 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45425 | /* 126167 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45426 | /* 126172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs32), |
| 45427 | /* 126175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45428 | /* 126177 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45429 | /* 126179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45430 | /* 126182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45431 | /* 126188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45432 | /* 126194 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45433 | /* 126197 */ GIR_RootConstrainSelectedInstOperands, |
| 45434 | /* 126198 */ // GIR_Coverage, 4046, |
| 45435 | /* 126198 */ GIR_EraseRootFromParent_Done, |
| 45436 | /* 126199 */ // Label 3832: @126199 |
| 45437 | /* 126199 */ GIM_Reject, |
| 45438 | /* 126200 */ // Label 3830: @126200 |
| 45439 | /* 126200 */ GIM_Reject, |
| 45440 | /* 126201 */ // Label 3820: @126201 |
| 45441 | /* 126201 */ GIM_Reject, |
| 45442 | /* 126202 */ // Label 73: @126202 |
| 45443 | /* 126202 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 3835*/ GIMT_Encode4(126295), |
| 45444 | /* 126213 */ /*GILLT_v8s8*//*Label 3833*/ GIMT_Encode4(126221), |
| 45445 | /* 126217 */ /*GILLT_v16s8*//*Label 3834*/ GIMT_Encode4(126258), |
| 45446 | /* 126221 */ // Label 3833: @126221 |
| 45447 | /* 126221 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3836*/ GIMT_Encode4(126257), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1714 // |
| 45448 | /* 126228 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8, |
| 45449 | /* 126231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45450 | /* 126235 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45451 | /* 126239 */ // (ctpop:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCNTd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) |
| 45452 | /* 126239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTd), |
| 45453 | /* 126242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45454 | /* 126244 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45455 | /* 126246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45456 | /* 126249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45457 | /* 126255 */ GIR_RootConstrainSelectedInstOperands, |
| 45458 | /* 126256 */ // GIR_Coverage, 1714, |
| 45459 | /* 126256 */ GIR_EraseRootFromParent_Done, |
| 45460 | /* 126257 */ // Label 3836: @126257 |
| 45461 | /* 126257 */ GIM_Reject, |
| 45462 | /* 126258 */ // Label 3834: @126258 |
| 45463 | /* 126258 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3837*/ GIMT_Encode4(126294), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1715 // |
| 45464 | /* 126265 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 45465 | /* 126268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45466 | /* 126272 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45467 | /* 126276 */ // (ctpop:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCNTq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) |
| 45468 | /* 126276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTq), |
| 45469 | /* 126279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd] |
| 45470 | /* 126281 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm |
| 45471 | /* 126283 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45472 | /* 126286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45473 | /* 126292 */ GIR_RootConstrainSelectedInstOperands, |
| 45474 | /* 126293 */ // GIR_Coverage, 1715, |
| 45475 | /* 126293 */ GIR_EraseRootFromParent_Done, |
| 45476 | /* 126294 */ // Label 3837: @126294 |
| 45477 | /* 126294 */ GIM_Reject, |
| 45478 | /* 126295 */ // Label 3835: @126295 |
| 45479 | /* 126295 */ GIM_Reject, |
| 45480 | /* 126296 */ // Label 74: @126296 |
| 45481 | /* 126296 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3841*/ GIMT_Encode4(126580), |
| 45482 | /* 126307 */ /*GILLT_s32*//*Label 3838*/ GIMT_Encode4(126355), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45483 | /* 126343 */ /*GILLT_v8s16*//*Label 3839*/ GIMT_Encode4(126464), GIMT_Encode4(0), |
| 45484 | /* 126351 */ /*GILLT_v4s32*//*Label 3840*/ GIMT_Encode4(126522), |
| 45485 | /* 126355 */ // Label 3838: @126355 |
| 45486 | /* 126355 */ GIM_Try, /*On fail goto*//*Label 3842*/ GIMT_Encode4(126463), |
| 45487 | /* 126360 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45488 | /* 126363 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3843*/ GIMT_Encode4(126396), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 198 // |
| 45489 | /* 126370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45490 | /* 126374 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45491 | /* 126378 */ // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (REV:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 45492 | /* 126378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV), |
| 45493 | /* 126381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45494 | /* 126383 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45495 | /* 126385 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45496 | /* 126388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45497 | /* 126394 */ GIR_RootConstrainSelectedInstOperands, |
| 45498 | /* 126395 */ // GIR_Coverage, 198, |
| 45499 | /* 126395 */ GIR_EraseRootFromParent_Done, |
| 45500 | /* 126396 */ // Label 3843: @126396 |
| 45501 | /* 126396 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3844*/ GIMT_Encode4(126429), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 325 // |
| 45502 | /* 126403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 45503 | /* 126407 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID), |
| 45504 | /* 126411 */ // (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) => (tREV:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) |
| 45505 | /* 126411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV), |
| 45506 | /* 126414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45507 | /* 126416 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45508 | /* 126418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45509 | /* 126421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45510 | /* 126427 */ GIR_RootConstrainSelectedInstOperands, |
| 45511 | /* 126428 */ // GIR_Coverage, 325, |
| 45512 | /* 126428 */ GIR_EraseRootFromParent_Done, |
| 45513 | /* 126429 */ // Label 3844: @126429 |
| 45514 | /* 126429 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3845*/ GIMT_Encode4(126462), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 535 // |
| 45515 | /* 126436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45516 | /* 126440 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45517 | /* 126444 */ // (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2REV:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 45518 | /* 126444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV), |
| 45519 | /* 126447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45520 | /* 126449 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45521 | /* 126451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45522 | /* 126454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45523 | /* 126460 */ GIR_RootConstrainSelectedInstOperands, |
| 45524 | /* 126461 */ // GIR_Coverage, 535, |
| 45525 | /* 126461 */ GIR_EraseRootFromParent_Done, |
| 45526 | /* 126462 */ // Label 3845: @126462 |
| 45527 | /* 126462 */ GIM_Reject, |
| 45528 | /* 126463 */ // Label 3842: @126463 |
| 45529 | /* 126463 */ GIM_Reject, |
| 45530 | /* 126464 */ // Label 3839: @126464 |
| 45531 | /* 126464 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3846*/ GIMT_Encode4(126521), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3724 // |
| 45532 | /* 126471 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45533 | /* 126474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45534 | /* 126478 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45535 | /* 126482 */ // (bswap:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) |
| 45536 | /* 126482 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45537 | /* 126485 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45538 | /* 126489 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45539 | /* 126494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8), |
| 45540 | /* 126497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45541 | /* 126499 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45542 | /* 126501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45543 | /* 126504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45544 | /* 126510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45545 | /* 126516 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45546 | /* 126519 */ GIR_RootConstrainSelectedInstOperands, |
| 45547 | /* 126520 */ // GIR_Coverage, 3724, |
| 45548 | /* 126520 */ GIR_EraseRootFromParent_Done, |
| 45549 | /* 126521 */ // Label 3846: @126521 |
| 45550 | /* 126521 */ GIM_Reject, |
| 45551 | /* 126522 */ // Label 3840: @126522 |
| 45552 | /* 126522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3847*/ GIMT_Encode4(126579), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3725 // |
| 45553 | /* 126529 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45554 | /* 126532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45555 | /* 126536 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45556 | /* 126540 */ // (bswap:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) |
| 45557 | /* 126540 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45558 | /* 126543 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45559 | /* 126547 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45560 | /* 126552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8), |
| 45561 | /* 126555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45562 | /* 126557 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 45563 | /* 126559 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45564 | /* 126562 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45565 | /* 126568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45566 | /* 126574 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45567 | /* 126577 */ GIR_RootConstrainSelectedInstOperands, |
| 45568 | /* 126578 */ // GIR_Coverage, 3725, |
| 45569 | /* 126578 */ GIR_EraseRootFromParent_Done, |
| 45570 | /* 126579 */ // Label 3847: @126579 |
| 45571 | /* 126579 */ GIM_Reject, |
| 45572 | /* 126580 */ // Label 3841: @126580 |
| 45573 | /* 126580 */ GIM_Reject, |
| 45574 | /* 126581 */ // Label 75: @126581 |
| 45575 | /* 126581 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3852*/ GIMT_Encode4(126995), |
| 45576 | /* 126592 */ /*GILLT_s32*//*Label 3848*/ GIMT_Encode4(126640), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45577 | /* 126620 */ /*GILLT_v16s8*//*Label 3849*/ GIMT_Encode4(126716), GIMT_Encode4(0), |
| 45578 | /* 126628 */ /*GILLT_v8s16*//*Label 3850*/ GIMT_Encode4(126809), GIMT_Encode4(0), |
| 45579 | /* 126636 */ /*GILLT_v4s32*//*Label 3851*/ GIMT_Encode4(126902), |
| 45580 | /* 126640 */ // Label 3848: @126640 |
| 45581 | /* 126640 */ GIM_Try, /*On fail goto*//*Label 3853*/ GIMT_Encode4(126715), |
| 45582 | /* 126645 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45583 | /* 126648 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3854*/ GIMT_Encode4(126681), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 197 // |
| 45584 | /* 126655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45585 | /* 126659 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID), |
| 45586 | /* 126663 */ // (bitreverse:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (RBIT:{ *:[i32] } GPR:{ *:[i32] }:$Rm) |
| 45587 | /* 126663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RBIT), |
| 45588 | /* 126666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45589 | /* 126668 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45590 | /* 126670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45591 | /* 126673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45592 | /* 126679 */ GIR_RootConstrainSelectedInstOperands, |
| 45593 | /* 126680 */ // GIR_Coverage, 197, |
| 45594 | /* 126680 */ GIR_EraseRootFromParent_Done, |
| 45595 | /* 126681 */ // Label 3854: @126681 |
| 45596 | /* 126681 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3855*/ GIMT_Encode4(126714), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 534 // |
| 45597 | /* 126688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45598 | /* 126692 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 45599 | /* 126696 */ // (bitreverse:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2RBIT:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) |
| 45600 | /* 126696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RBIT), |
| 45601 | /* 126699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd] |
| 45602 | /* 126701 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm |
| 45603 | /* 126703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45604 | /* 126706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45605 | /* 126712 */ GIR_RootConstrainSelectedInstOperands, |
| 45606 | /* 126713 */ // GIR_Coverage, 534, |
| 45607 | /* 126713 */ GIR_EraseRootFromParent_Done, |
| 45608 | /* 126714 */ // Label 3855: @126714 |
| 45609 | /* 126714 */ GIM_Reject, |
| 45610 | /* 126715 */ // Label 3853: @126715 |
| 45611 | /* 126715 */ GIM_Reject, |
| 45612 | /* 126716 */ // Label 3849: @126716 |
| 45613 | /* 126716 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3856*/ GIMT_Encode4(126808), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5271 // |
| 45614 | /* 126723 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8, |
| 45615 | /* 126726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45616 | /* 126730 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45617 | /* 126734 */ // (bitreverse:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1, (t2MOVi:{ *:[i32] } 8:{ *:[i32] })) |
| 45618 | /* 126734 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 45619 | /* 126737 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45620 | /* 126741 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45621 | /* 126746 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45622 | /* 126749 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45623 | /* 126753 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45624 | /* 126758 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/8, |
| 45625 | /* 126761 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45626 | /* 126764 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45627 | /* 126770 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45628 | /* 126776 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45629 | /* 126778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8), |
| 45630 | /* 126781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45631 | /* 126783 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1 |
| 45632 | /* 126785 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45633 | /* 126788 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45634 | /* 126791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45635 | /* 126797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45636 | /* 126803 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 45637 | /* 126806 */ GIR_RootConstrainSelectedInstOperands, |
| 45638 | /* 126807 */ // GIR_Coverage, 5271, |
| 45639 | /* 126807 */ GIR_EraseRootFromParent_Done, |
| 45640 | /* 126808 */ // Label 3856: @126808 |
| 45641 | /* 126808 */ GIM_Reject, |
| 45642 | /* 126809 */ // Label 3850: @126809 |
| 45643 | /* 126809 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3857*/ GIMT_Encode4(126901), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5273 // |
| 45644 | /* 126816 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45645 | /* 126819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45646 | /* 126823 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45647 | /* 126827 */ // (bitreverse:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1, (t2MOVi:{ *:[i32] } 16:{ *:[i32] })) |
| 45648 | /* 126827 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 45649 | /* 126830 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45650 | /* 126834 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45651 | /* 126839 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45652 | /* 126842 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45653 | /* 126846 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45654 | /* 126851 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/16, |
| 45655 | /* 126854 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45656 | /* 126857 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45657 | /* 126863 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45658 | /* 126869 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45659 | /* 126871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16), |
| 45660 | /* 126874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45661 | /* 126876 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1 |
| 45662 | /* 126878 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45663 | /* 126881 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45664 | /* 126884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45665 | /* 126890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45666 | /* 126896 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 45667 | /* 126899 */ GIR_RootConstrainSelectedInstOperands, |
| 45668 | /* 126900 */ // GIR_Coverage, 5273, |
| 45669 | /* 126900 */ GIR_EraseRootFromParent_Done, |
| 45670 | /* 126901 */ // Label 3857: @126901 |
| 45671 | /* 126901 */ GIM_Reject, |
| 45672 | /* 126902 */ // Label 3851: @126902 |
| 45673 | /* 126902 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3858*/ GIMT_Encode4(126994), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5272 // |
| 45674 | /* 126909 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45675 | /* 126912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45676 | /* 126916 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45677 | /* 126920 */ // (bitreverse:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1, (t2MOVi:{ *:[i32] } 32:{ *:[i32] })) |
| 45678 | /* 126920 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32, |
| 45679 | /* 126923 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45680 | /* 126927 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45681 | /* 126932 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 45682 | /* 126935 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 45683 | /* 126939 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45684 | /* 126944 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/32, |
| 45685 | /* 126947 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 45686 | /* 126950 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45687 | /* 126956 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45688 | /* 126962 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 45689 | /* 126964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32), |
| 45690 | /* 126967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45691 | /* 126969 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1 |
| 45692 | /* 126971 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45693 | /* 126974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45694 | /* 126977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45695 | /* 126983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45696 | /* 126989 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 45697 | /* 126992 */ GIR_RootConstrainSelectedInstOperands, |
| 45698 | /* 126993 */ // GIR_Coverage, 5272, |
| 45699 | /* 126993 */ GIR_EraseRootFromParent_Done, |
| 45700 | /* 126994 */ // Label 3858: @126994 |
| 45701 | /* 126994 */ GIM_Reject, |
| 45702 | /* 126995 */ // Label 3852: @126995 |
| 45703 | /* 126995 */ GIM_Reject, |
| 45704 | /* 126996 */ // Label 76: @126996 |
| 45705 | /* 126996 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3866*/ GIMT_Encode4(127361), |
| 45706 | /* 127007 */ /*GILLT_s16*//*Label 3859*/ GIMT_Encode4(127059), |
| 45707 | /* 127011 */ /*GILLT_s32*//*Label 3860*/ GIMT_Encode4(127085), |
| 45708 | /* 127015 */ /*GILLT_s64*//*Label 3861*/ GIMT_Encode4(127111), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45709 | /* 127043 */ /*GILLT_v4s16*//*Label 3862*/ GIMT_Encode4(127137), |
| 45710 | /* 127047 */ /*GILLT_v8s16*//*Label 3863*/ GIMT_Encode4(127163), |
| 45711 | /* 127051 */ /*GILLT_v2s32*//*Label 3864*/ GIMT_Encode4(127249), |
| 45712 | /* 127055 */ /*GILLT_v4s32*//*Label 3865*/ GIMT_Encode4(127275), |
| 45713 | /* 127059 */ // Label 3859: @127059 |
| 45714 | /* 127059 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3867*/ GIMT_Encode4(127084), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 723 // |
| 45715 | /* 127066 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 45716 | /* 127069 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45717 | /* 127073 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45718 | /* 127077 */ // (fceil:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTPH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 45719 | /* 127077 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPH), |
| 45720 | /* 127082 */ GIR_RootConstrainSelectedInstOperands, |
| 45721 | /* 127083 */ // GIR_Coverage, 723, |
| 45722 | /* 127083 */ GIR_Done, |
| 45723 | /* 127084 */ // Label 3867: @127084 |
| 45724 | /* 127084 */ GIM_Reject, |
| 45725 | /* 127085 */ // Label 3860: @127085 |
| 45726 | /* 127085 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3868*/ GIMT_Encode4(127110), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 725 // |
| 45727 | /* 127092 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45728 | /* 127095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45729 | /* 127099 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45730 | /* 127103 */ // (fceil:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTPS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 45731 | /* 127103 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPS), |
| 45732 | /* 127108 */ GIR_RootConstrainSelectedInstOperands, |
| 45733 | /* 127109 */ // GIR_Coverage, 725, |
| 45734 | /* 127109 */ GIR_Done, |
| 45735 | /* 127110 */ // Label 3868: @127110 |
| 45736 | /* 127110 */ GIM_Reject, |
| 45737 | /* 127111 */ // Label 3861: @127111 |
| 45738 | /* 127111 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3869*/ GIMT_Encode4(127136), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 727 // |
| 45739 | /* 127118 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 45740 | /* 127121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45741 | /* 127125 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45742 | /* 127129 */ // (fceil:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTPD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 45743 | /* 127129 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPD), |
| 45744 | /* 127134 */ GIR_RootConstrainSelectedInstOperands, |
| 45745 | /* 127135 */ // GIR_Coverage, 727, |
| 45746 | /* 127135 */ GIR_Done, |
| 45747 | /* 127136 */ // Label 3869: @127136 |
| 45748 | /* 127136 */ GIM_Reject, |
| 45749 | /* 127137 */ // Label 3862: @127137 |
| 45750 | /* 127137 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3870*/ GIMT_Encode4(127162), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1898 // |
| 45751 | /* 127144 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45752 | /* 127147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45753 | /* 127151 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45754 | /* 127155 */ // (fceil:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTPNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 45755 | /* 127155 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDh), |
| 45756 | /* 127160 */ GIR_RootConstrainSelectedInstOperands, |
| 45757 | /* 127161 */ // GIR_Coverage, 1898, |
| 45758 | /* 127161 */ GIR_Done, |
| 45759 | /* 127162 */ // Label 3870: @127162 |
| 45760 | /* 127162 */ GIM_Reject, |
| 45761 | /* 127163 */ // Label 3863: @127163 |
| 45762 | /* 127163 */ GIM_Try, /*On fail goto*//*Label 3871*/ GIMT_Encode4(127248), |
| 45763 | /* 127168 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45764 | /* 127171 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3872*/ GIMT_Encode4(127193), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1900 // |
| 45765 | /* 127178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45766 | /* 127182 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45767 | /* 127186 */ // (fceil:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTPNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 45768 | /* 127186 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQh), |
| 45769 | /* 127191 */ GIR_RootConstrainSelectedInstOperands, |
| 45770 | /* 127192 */ // GIR_Coverage, 1900, |
| 45771 | /* 127192 */ GIR_Done, |
| 45772 | /* 127193 */ // Label 3872: @127193 |
| 45773 | /* 127193 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3873*/ GIMT_Encode4(127247), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4379 // |
| 45774 | /* 127200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45775 | /* 127204 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45776 | /* 127208 */ // (fceil:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 45777 | /* 127208 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45778 | /* 127211 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45779 | /* 127215 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45780 | /* 127220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P), |
| 45781 | /* 127223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45782 | /* 127225 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45783 | /* 127227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45784 | /* 127230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45785 | /* 127236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45786 | /* 127242 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45787 | /* 127245 */ GIR_RootConstrainSelectedInstOperands, |
| 45788 | /* 127246 */ // GIR_Coverage, 4379, |
| 45789 | /* 127246 */ GIR_EraseRootFromParent_Done, |
| 45790 | /* 127247 */ // Label 3873: @127247 |
| 45791 | /* 127247 */ GIM_Reject, |
| 45792 | /* 127248 */ // Label 3871: @127248 |
| 45793 | /* 127248 */ GIM_Reject, |
| 45794 | /* 127249 */ // Label 3864: @127249 |
| 45795 | /* 127249 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3874*/ GIMT_Encode4(127274), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1894 // |
| 45796 | /* 127256 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45797 | /* 127259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45798 | /* 127263 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45799 | /* 127267 */ // (fceil:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTPNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 45800 | /* 127267 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDf), |
| 45801 | /* 127272 */ GIR_RootConstrainSelectedInstOperands, |
| 45802 | /* 127273 */ // GIR_Coverage, 1894, |
| 45803 | /* 127273 */ GIR_Done, |
| 45804 | /* 127274 */ // Label 3874: @127274 |
| 45805 | /* 127274 */ GIM_Reject, |
| 45806 | /* 127275 */ // Label 3865: @127275 |
| 45807 | /* 127275 */ GIM_Try, /*On fail goto*//*Label 3875*/ GIMT_Encode4(127360), |
| 45808 | /* 127280 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 45809 | /* 127283 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3876*/ GIMT_Encode4(127305), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1896 // |
| 45810 | /* 127290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45811 | /* 127294 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45812 | /* 127298 */ // (fceil:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTPNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 45813 | /* 127298 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQf), |
| 45814 | /* 127303 */ GIR_RootConstrainSelectedInstOperands, |
| 45815 | /* 127304 */ // GIR_Coverage, 1896, |
| 45816 | /* 127304 */ GIR_Done, |
| 45817 | /* 127305 */ // Label 3876: @127305 |
| 45818 | /* 127305 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3877*/ GIMT_Encode4(127359), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4403 // |
| 45819 | /* 127312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45820 | /* 127316 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45821 | /* 127320 */ // (fceil:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 45822 | /* 127320 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45823 | /* 127323 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45824 | /* 127327 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45825 | /* 127332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P), |
| 45826 | /* 127335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45827 | /* 127337 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45828 | /* 127339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45829 | /* 127342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45830 | /* 127348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45831 | /* 127354 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45832 | /* 127357 */ GIR_RootConstrainSelectedInstOperands, |
| 45833 | /* 127358 */ // GIR_Coverage, 4403, |
| 45834 | /* 127358 */ GIR_EraseRootFromParent_Done, |
| 45835 | /* 127359 */ // Label 3877: @127359 |
| 45836 | /* 127359 */ GIM_Reject, |
| 45837 | /* 127360 */ // Label 3875: @127360 |
| 45838 | /* 127360 */ GIM_Reject, |
| 45839 | /* 127361 */ // Label 3866: @127361 |
| 45840 | /* 127361 */ GIM_Reject, |
| 45841 | /* 127362 */ // Label 77: @127362 |
| 45842 | /* 127362 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3881*/ GIMT_Encode4(127496), |
| 45843 | /* 127373 */ /*GILLT_s16*//*Label 3878*/ GIMT_Encode4(127385), |
| 45844 | /* 127377 */ /*GILLT_s32*//*Label 3879*/ GIMT_Encode4(127422), |
| 45845 | /* 127381 */ /*GILLT_s64*//*Label 3880*/ GIMT_Encode4(127459), |
| 45846 | /* 127385 */ // Label 3878: @127385 |
| 45847 | /* 127385 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3882*/ GIMT_Encode4(127421), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 739 // |
| 45848 | /* 127392 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 45849 | /* 127395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45850 | /* 127399 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45851 | /* 127403 */ // (fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 45852 | /* 127403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH), |
| 45853 | /* 127406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 45854 | /* 127408 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 45855 | /* 127410 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45856 | /* 127413 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45857 | /* 127419 */ GIR_RootConstrainSelectedInstOperands, |
| 45858 | /* 127420 */ // GIR_Coverage, 739, |
| 45859 | /* 127420 */ GIR_EraseRootFromParent_Done, |
| 45860 | /* 127421 */ // Label 3882: @127421 |
| 45861 | /* 127421 */ GIM_Reject, |
| 45862 | /* 127422 */ // Label 3879: @127422 |
| 45863 | /* 127422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3883*/ GIMT_Encode4(127458), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 737 // |
| 45864 | /* 127429 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45865 | /* 127432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45866 | /* 127436 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45867 | /* 127440 */ // (fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 45868 | /* 127440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS), |
| 45869 | /* 127443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 45870 | /* 127445 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 45871 | /* 127447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45872 | /* 127450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45873 | /* 127456 */ GIR_RootConstrainSelectedInstOperands, |
| 45874 | /* 127457 */ // GIR_Coverage, 737, |
| 45875 | /* 127457 */ GIR_EraseRootFromParent_Done, |
| 45876 | /* 127458 */ // Label 3883: @127458 |
| 45877 | /* 127458 */ GIM_Reject, |
| 45878 | /* 127459 */ // Label 3880: @127459 |
| 45879 | /* 127459 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3884*/ GIMT_Encode4(127495), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 735 // |
| 45880 | /* 127466 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 45881 | /* 127469 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45882 | /* 127473 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45883 | /* 127477 */ // (fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 45884 | /* 127477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD), |
| 45885 | /* 127480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 45886 | /* 127482 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 45887 | /* 127484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 45888 | /* 127487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45889 | /* 127493 */ GIR_RootConstrainSelectedInstOperands, |
| 45890 | /* 127494 */ // GIR_Coverage, 735, |
| 45891 | /* 127494 */ GIR_EraseRootFromParent_Done, |
| 45892 | /* 127495 */ // Label 3884: @127495 |
| 45893 | /* 127495 */ GIM_Reject, |
| 45894 | /* 127496 */ // Label 3881: @127496 |
| 45895 | /* 127496 */ GIM_Reject, |
| 45896 | /* 127497 */ // Label 78: @127497 |
| 45897 | /* 127497 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3892*/ GIMT_Encode4(127862), |
| 45898 | /* 127508 */ /*GILLT_s16*//*Label 3885*/ GIMT_Encode4(127560), |
| 45899 | /* 127512 */ /*GILLT_s32*//*Label 3886*/ GIMT_Encode4(127586), |
| 45900 | /* 127516 */ /*GILLT_s64*//*Label 3887*/ GIMT_Encode4(127612), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 45901 | /* 127544 */ /*GILLT_v4s16*//*Label 3888*/ GIMT_Encode4(127638), |
| 45902 | /* 127548 */ /*GILLT_v8s16*//*Label 3889*/ GIMT_Encode4(127664), |
| 45903 | /* 127552 */ /*GILLT_v2s32*//*Label 3890*/ GIMT_Encode4(127750), |
| 45904 | /* 127556 */ /*GILLT_v4s32*//*Label 3891*/ GIMT_Encode4(127776), |
| 45905 | /* 127560 */ // Label 3885: @127560 |
| 45906 | /* 127560 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3893*/ GIMT_Encode4(127585), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 729 // |
| 45907 | /* 127567 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 45908 | /* 127570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45909 | /* 127574 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 45910 | /* 127578 */ // (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTMH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 45911 | /* 127578 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMH), |
| 45912 | /* 127583 */ GIR_RootConstrainSelectedInstOperands, |
| 45913 | /* 127584 */ // GIR_Coverage, 729, |
| 45914 | /* 127584 */ GIR_Done, |
| 45915 | /* 127585 */ // Label 3893: @127585 |
| 45916 | /* 127585 */ GIM_Reject, |
| 45917 | /* 127586 */ // Label 3886: @127586 |
| 45918 | /* 127586 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3894*/ GIMT_Encode4(127611), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 731 // |
| 45919 | /* 127593 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 45920 | /* 127596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45921 | /* 127600 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 45922 | /* 127604 */ // (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTMS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 45923 | /* 127604 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMS), |
| 45924 | /* 127609 */ GIR_RootConstrainSelectedInstOperands, |
| 45925 | /* 127610 */ // GIR_Coverage, 731, |
| 45926 | /* 127610 */ GIR_Done, |
| 45927 | /* 127611 */ // Label 3894: @127611 |
| 45928 | /* 127611 */ GIM_Reject, |
| 45929 | /* 127612 */ // Label 3887: @127612 |
| 45930 | /* 127612 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3895*/ GIMT_Encode4(127637), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 733 // |
| 45931 | /* 127619 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 45932 | /* 127622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45933 | /* 127626 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45934 | /* 127630 */ // (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTMD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 45935 | /* 127630 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMD), |
| 45936 | /* 127635 */ GIR_RootConstrainSelectedInstOperands, |
| 45937 | /* 127636 */ // GIR_Coverage, 733, |
| 45938 | /* 127636 */ GIR_Done, |
| 45939 | /* 127637 */ // Label 3895: @127637 |
| 45940 | /* 127637 */ GIM_Reject, |
| 45941 | /* 127638 */ // Label 3888: @127638 |
| 45942 | /* 127638 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3896*/ GIMT_Encode4(127663), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1890 // |
| 45943 | /* 127645 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 45944 | /* 127648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45945 | /* 127652 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45946 | /* 127656 */ // (ffloor:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 45947 | /* 127656 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDh), |
| 45948 | /* 127661 */ GIR_RootConstrainSelectedInstOperands, |
| 45949 | /* 127662 */ // GIR_Coverage, 1890, |
| 45950 | /* 127662 */ GIR_Done, |
| 45951 | /* 127663 */ // Label 3896: @127663 |
| 45952 | /* 127663 */ GIM_Reject, |
| 45953 | /* 127664 */ // Label 3889: @127664 |
| 45954 | /* 127664 */ GIM_Try, /*On fail goto*//*Label 3897*/ GIMT_Encode4(127749), |
| 45955 | /* 127669 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 45956 | /* 127672 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3898*/ GIMT_Encode4(127694), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1892 // |
| 45957 | /* 127679 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45958 | /* 127683 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 45959 | /* 127687 */ // (ffloor:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 45960 | /* 127687 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQh), |
| 45961 | /* 127692 */ GIR_RootConstrainSelectedInstOperands, |
| 45962 | /* 127693 */ // GIR_Coverage, 1892, |
| 45963 | /* 127693 */ GIR_Done, |
| 45964 | /* 127694 */ // Label 3898: @127694 |
| 45965 | /* 127694 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3899*/ GIMT_Encode4(127748), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4375 // |
| 45966 | /* 127701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45967 | /* 127705 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 45968 | /* 127709 */ // (ffloor:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 45969 | /* 127709 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 45970 | /* 127712 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 45971 | /* 127716 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 45972 | /* 127721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M), |
| 45973 | /* 127724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 45974 | /* 127726 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 45975 | /* 127728 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45976 | /* 127731 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45977 | /* 127737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 45978 | /* 127743 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 45979 | /* 127746 */ GIR_RootConstrainSelectedInstOperands, |
| 45980 | /* 127747 */ // GIR_Coverage, 4375, |
| 45981 | /* 127747 */ GIR_EraseRootFromParent_Done, |
| 45982 | /* 127748 */ // Label 3899: @127748 |
| 45983 | /* 127748 */ GIM_Reject, |
| 45984 | /* 127749 */ // Label 3897: @127749 |
| 45985 | /* 127749 */ GIM_Reject, |
| 45986 | /* 127750 */ // Label 3890: @127750 |
| 45987 | /* 127750 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3900*/ GIMT_Encode4(127775), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1886 // |
| 45988 | /* 127757 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 45989 | /* 127760 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45990 | /* 127764 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 45991 | /* 127768 */ // (ffloor:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 45992 | /* 127768 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDf), |
| 45993 | /* 127773 */ GIR_RootConstrainSelectedInstOperands, |
| 45994 | /* 127774 */ // GIR_Coverage, 1886, |
| 45995 | /* 127774 */ GIR_Done, |
| 45996 | /* 127775 */ // Label 3900: @127775 |
| 45997 | /* 127775 */ GIM_Reject, |
| 45998 | /* 127776 */ // Label 3891: @127776 |
| 45999 | /* 127776 */ GIM_Try, /*On fail goto*//*Label 3901*/ GIMT_Encode4(127861), |
| 46000 | /* 127781 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 46001 | /* 127784 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3902*/ GIMT_Encode4(127806), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1888 // |
| 46002 | /* 127791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46003 | /* 127795 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46004 | /* 127799 */ // (ffloor:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 46005 | /* 127799 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQf), |
| 46006 | /* 127804 */ GIR_RootConstrainSelectedInstOperands, |
| 46007 | /* 127805 */ // GIR_Coverage, 1888, |
| 46008 | /* 127805 */ GIR_Done, |
| 46009 | /* 127806 */ // Label 3902: @127806 |
| 46010 | /* 127806 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3903*/ GIMT_Encode4(127860), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4399 // |
| 46011 | /* 127813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46012 | /* 127817 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46013 | /* 127821 */ // (ffloor:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 46014 | /* 127821 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46015 | /* 127824 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46016 | /* 127828 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46017 | /* 127833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M), |
| 46018 | /* 127836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46019 | /* 127838 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 46020 | /* 127840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46021 | /* 127843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46022 | /* 127849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46023 | /* 127855 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46024 | /* 127858 */ GIR_RootConstrainSelectedInstOperands, |
| 46025 | /* 127859 */ // GIR_Coverage, 4399, |
| 46026 | /* 127859 */ GIR_EraseRootFromParent_Done, |
| 46027 | /* 127860 */ // Label 3903: @127860 |
| 46028 | /* 127860 */ GIM_Reject, |
| 46029 | /* 127861 */ // Label 3901: @127861 |
| 46030 | /* 127861 */ GIM_Reject, |
| 46031 | /* 127862 */ // Label 3892: @127862 |
| 46032 | /* 127862 */ GIM_Reject, |
| 46033 | /* 127863 */ // Label 79: @127863 |
| 46034 | /* 127863 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3911*/ GIMT_Encode4(128261), |
| 46035 | /* 127874 */ /*GILLT_s16*//*Label 3904*/ GIMT_Encode4(127926), |
| 46036 | /* 127878 */ /*GILLT_s32*//*Label 3905*/ GIMT_Encode4(127963), |
| 46037 | /* 127882 */ /*GILLT_s64*//*Label 3906*/ GIMT_Encode4(128000), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 46038 | /* 127910 */ /*GILLT_v4s16*//*Label 3907*/ GIMT_Encode4(128037), |
| 46039 | /* 127914 */ /*GILLT_v8s16*//*Label 3908*/ GIMT_Encode4(128063), |
| 46040 | /* 127918 */ /*GILLT_v2s32*//*Label 3909*/ GIMT_Encode4(128149), |
| 46041 | /* 127922 */ /*GILLT_v4s32*//*Label 3910*/ GIMT_Encode4(128175), |
| 46042 | /* 127926 */ // Label 3904: @127926 |
| 46043 | /* 127926 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3912*/ GIMT_Encode4(127962), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 705 // |
| 46044 | /* 127933 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46045 | /* 127936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46046 | /* 127940 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46047 | /* 127944 */ // (frint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTXH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 46048 | /* 127944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXH), |
| 46049 | /* 127947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46050 | /* 127949 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46051 | /* 127951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46052 | /* 127954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46053 | /* 127960 */ GIR_RootConstrainSelectedInstOperands, |
| 46054 | /* 127961 */ // GIR_Coverage, 705, |
| 46055 | /* 127961 */ GIR_EraseRootFromParent_Done, |
| 46056 | /* 127962 */ // Label 3912: @127962 |
| 46057 | /* 127962 */ GIM_Reject, |
| 46058 | /* 127963 */ // Label 3905: @127963 |
| 46059 | /* 127963 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3913*/ GIMT_Encode4(127999), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 707 // |
| 46060 | /* 127970 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46061 | /* 127973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46062 | /* 127977 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46063 | /* 127981 */ // (frint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTXS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 46064 | /* 127981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXS), |
| 46065 | /* 127984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46066 | /* 127986 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46067 | /* 127988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46068 | /* 127991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46069 | /* 127997 */ GIR_RootConstrainSelectedInstOperands, |
| 46070 | /* 127998 */ // GIR_Coverage, 707, |
| 46071 | /* 127998 */ GIR_EraseRootFromParent_Done, |
| 46072 | /* 127999 */ // Label 3913: @127999 |
| 46073 | /* 127999 */ GIM_Reject, |
| 46074 | /* 128000 */ // Label 3906: @128000 |
| 46075 | /* 128000 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3914*/ GIMT_Encode4(128036), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 709 // |
| 46076 | /* 128007 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46077 | /* 128010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46078 | /* 128014 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46079 | /* 128018 */ // (frint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTXD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 46080 | /* 128018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXD), |
| 46081 | /* 128021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46082 | /* 128023 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 46083 | /* 128025 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46084 | /* 128028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46085 | /* 128034 */ GIR_RootConstrainSelectedInstOperands, |
| 46086 | /* 128035 */ // GIR_Coverage, 709, |
| 46087 | /* 128035 */ GIR_EraseRootFromParent_Done, |
| 46088 | /* 128036 */ // Label 3914: @128036 |
| 46089 | /* 128036 */ GIM_Reject, |
| 46090 | /* 128037 */ // Label 3907: @128037 |
| 46091 | /* 128037 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3915*/ GIMT_Encode4(128062), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1866 // |
| 46092 | /* 128044 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 46093 | /* 128047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46094 | /* 128051 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46095 | /* 128055 */ // (frint:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTXNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) |
| 46096 | /* 128055 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDh), |
| 46097 | /* 128060 */ GIR_RootConstrainSelectedInstOperands, |
| 46098 | /* 128061 */ // GIR_Coverage, 1866, |
| 46099 | /* 128061 */ GIR_Done, |
| 46100 | /* 128062 */ // Label 3915: @128062 |
| 46101 | /* 128062 */ GIM_Reject, |
| 46102 | /* 128063 */ // Label 3908: @128063 |
| 46103 | /* 128063 */ GIM_Try, /*On fail goto*//*Label 3916*/ GIMT_Encode4(128148), |
| 46104 | /* 128068 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 46105 | /* 128071 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3917*/ GIMT_Encode4(128093), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1868 // |
| 46106 | /* 128078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46107 | /* 128082 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46108 | /* 128086 */ // (frint:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTXNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) |
| 46109 | /* 128086 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQh), |
| 46110 | /* 128091 */ GIR_RootConstrainSelectedInstOperands, |
| 46111 | /* 128092 */ // GIR_Coverage, 1868, |
| 46112 | /* 128092 */ GIR_Done, |
| 46113 | /* 128093 */ // Label 3917: @128093 |
| 46114 | /* 128093 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3918*/ GIMT_Encode4(128147), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4363 // |
| 46115 | /* 128100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46116 | /* 128104 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46117 | /* 128108 */ // (frint:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) |
| 46118 | /* 128108 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46119 | /* 128111 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46120 | /* 128115 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46121 | /* 128120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X), |
| 46122 | /* 128123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46123 | /* 128125 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 46124 | /* 128127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46125 | /* 128130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46126 | /* 128136 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46127 | /* 128142 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46128 | /* 128145 */ GIR_RootConstrainSelectedInstOperands, |
| 46129 | /* 128146 */ // GIR_Coverage, 4363, |
| 46130 | /* 128146 */ GIR_EraseRootFromParent_Done, |
| 46131 | /* 128147 */ // Label 3918: @128147 |
| 46132 | /* 128147 */ GIM_Reject, |
| 46133 | /* 128148 */ // Label 3916: @128148 |
| 46134 | /* 128148 */ GIM_Reject, |
| 46135 | /* 128149 */ // Label 3909: @128149 |
| 46136 | /* 128149 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3919*/ GIMT_Encode4(128174), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1862 // |
| 46137 | /* 128156 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 46138 | /* 128159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46139 | /* 128163 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46140 | /* 128167 */ // (frint:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTXNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) |
| 46141 | /* 128167 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDf), |
| 46142 | /* 128172 */ GIR_RootConstrainSelectedInstOperands, |
| 46143 | /* 128173 */ // GIR_Coverage, 1862, |
| 46144 | /* 128173 */ GIR_Done, |
| 46145 | /* 128174 */ // Label 3919: @128174 |
| 46146 | /* 128174 */ GIM_Reject, |
| 46147 | /* 128175 */ // Label 3910: @128175 |
| 46148 | /* 128175 */ GIM_Try, /*On fail goto*//*Label 3920*/ GIMT_Encode4(128260), |
| 46149 | /* 128180 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 46150 | /* 128183 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3921*/ GIMT_Encode4(128205), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1864 // |
| 46151 | /* 128190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46152 | /* 128194 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID), |
| 46153 | /* 128198 */ // (frint:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTXNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) |
| 46154 | /* 128198 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQf), |
| 46155 | /* 128203 */ GIR_RootConstrainSelectedInstOperands, |
| 46156 | /* 128204 */ // GIR_Coverage, 1864, |
| 46157 | /* 128204 */ GIR_Done, |
| 46158 | /* 128205 */ // Label 3921: @128205 |
| 46159 | /* 128205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3922*/ GIMT_Encode4(128259), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4387 // |
| 46160 | /* 128212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46161 | /* 128216 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 46162 | /* 128220 */ // (frint:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) |
| 46163 | /* 128220 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32, |
| 46164 | /* 128223 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 46165 | /* 128227 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 46166 | /* 128232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X), |
| 46167 | /* 128235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd] |
| 46168 | /* 128237 */ GIR_RootToRootCopy, /*OpIdx*/1, // val |
| 46169 | /* 128239 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46170 | /* 128242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46171 | /* 128248 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46172 | /* 128254 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 46173 | /* 128257 */ GIR_RootConstrainSelectedInstOperands, |
| 46174 | /* 128258 */ // GIR_Coverage, 4387, |
| 46175 | /* 128258 */ GIR_EraseRootFromParent_Done, |
| 46176 | /* 128259 */ // Label 3922: @128259 |
| 46177 | /* 128259 */ GIM_Reject, |
| 46178 | /* 128260 */ // Label 3920: @128260 |
| 46179 | /* 128260 */ GIM_Reject, |
| 46180 | /* 128261 */ // Label 3911: @128261 |
| 46181 | /* 128261 */ GIM_Reject, |
| 46182 | /* 128262 */ // Label 80: @128262 |
| 46183 | /* 128262 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3926*/ GIMT_Encode4(128396), |
| 46184 | /* 128273 */ /*GILLT_s16*//*Label 3923*/ GIMT_Encode4(128285), |
| 46185 | /* 128277 */ /*GILLT_s32*//*Label 3924*/ GIMT_Encode4(128322), |
| 46186 | /* 128281 */ /*GILLT_s64*//*Label 3925*/ GIMT_Encode4(128359), |
| 46187 | /* 128285 */ // Label 3923: @128285 |
| 46188 | /* 128285 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3927*/ GIMT_Encode4(128321), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 699 // |
| 46189 | /* 128292 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46190 | /* 128295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46191 | /* 128299 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46192 | /* 128303 */ // (fnearbyint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTRH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 46193 | /* 128303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRH), |
| 46194 | /* 128306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46195 | /* 128308 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46196 | /* 128310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46197 | /* 128313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46198 | /* 128319 */ GIR_RootConstrainSelectedInstOperands, |
| 46199 | /* 128320 */ // GIR_Coverage, 699, |
| 46200 | /* 128320 */ GIR_EraseRootFromParent_Done, |
| 46201 | /* 128321 */ // Label 3927: @128321 |
| 46202 | /* 128321 */ GIM_Reject, |
| 46203 | /* 128322 */ // Label 3924: @128322 |
| 46204 | /* 128322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3928*/ GIMT_Encode4(128358), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 701 // |
| 46205 | /* 128329 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46206 | /* 128332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46207 | /* 128336 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46208 | /* 128340 */ // (fnearbyint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 46209 | /* 128340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRS), |
| 46210 | /* 128343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46211 | /* 128345 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46212 | /* 128347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46213 | /* 128350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46214 | /* 128356 */ GIR_RootConstrainSelectedInstOperands, |
| 46215 | /* 128357 */ // GIR_Coverage, 701, |
| 46216 | /* 128357 */ GIR_EraseRootFromParent_Done, |
| 46217 | /* 128358 */ // Label 3928: @128358 |
| 46218 | /* 128358 */ GIM_Reject, |
| 46219 | /* 128359 */ // Label 3925: @128359 |
| 46220 | /* 128359 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3929*/ GIMT_Encode4(128395), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 703 // |
| 46221 | /* 128366 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46222 | /* 128369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46223 | /* 128373 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46224 | /* 128377 */ // (fnearbyint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTRD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 46225 | /* 128377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRD), |
| 46226 | /* 128380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46227 | /* 128382 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 46228 | /* 128384 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46229 | /* 128387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46230 | /* 128393 */ GIR_RootConstrainSelectedInstOperands, |
| 46231 | /* 128394 */ // GIR_Coverage, 703, |
| 46232 | /* 128394 */ GIR_EraseRootFromParent_Done, |
| 46233 | /* 128395 */ // Label 3929: @128395 |
| 46234 | /* 128395 */ GIM_Reject, |
| 46235 | /* 128396 */ // Label 3926: @128396 |
| 46236 | /* 128396 */ GIM_Reject, |
| 46237 | /* 128397 */ // Label 81: @128397 |
| 46238 | /* 128397 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3933*/ GIMT_Encode4(128558), |
| 46239 | /* 128408 */ /*GILLT_s16*//*Label 3930*/ GIMT_Encode4(128420), |
| 46240 | /* 128412 */ /*GILLT_s32*//*Label 3931*/ GIMT_Encode4(128466), |
| 46241 | /* 128416 */ /*GILLT_s64*//*Label 3932*/ GIMT_Encode4(128512), |
| 46242 | /* 128420 */ // Label 3930: @128420 |
| 46243 | /* 128420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3934*/ GIMT_Encode4(128465), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 620 // |
| 46244 | /* 128427 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46245 | /* 128430 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 46246 | /* 128433 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46247 | /* 128437 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46248 | /* 128441 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46249 | /* 128445 */ // (strict_fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46250 | /* 128445 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH), |
| 46251 | /* 128448 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46252 | /* 128450 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46253 | /* 128452 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46254 | /* 128454 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46255 | /* 128457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46256 | /* 128463 */ GIR_RootConstrainSelectedInstOperands, |
| 46257 | /* 128464 */ // GIR_Coverage, 620, |
| 46258 | /* 128464 */ GIR_EraseRootFromParent_Done, |
| 46259 | /* 128465 */ // Label 3934: @128465 |
| 46260 | /* 128465 */ GIM_Reject, |
| 46261 | /* 128466 */ // Label 3931: @128466 |
| 46262 | /* 128466 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3935*/ GIMT_Encode4(128511), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 618 // |
| 46263 | /* 128473 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46264 | /* 128476 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 46265 | /* 128479 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46266 | /* 128483 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46267 | /* 128487 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46268 | /* 128491 */ // (strict_fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46269 | /* 128491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS), |
| 46270 | /* 128494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46271 | /* 128496 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46272 | /* 128498 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46273 | /* 128500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46274 | /* 128503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46275 | /* 128509 */ GIR_RootConstrainSelectedInstOperands, |
| 46276 | /* 128510 */ // GIR_Coverage, 618, |
| 46277 | /* 128510 */ GIR_EraseRootFromParent_Done, |
| 46278 | /* 128511 */ // Label 3935: @128511 |
| 46279 | /* 128511 */ GIM_Reject, |
| 46280 | /* 128512 */ // Label 3932: @128512 |
| 46281 | /* 128512 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3936*/ GIMT_Encode4(128557), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 616 // |
| 46282 | /* 128519 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46283 | /* 128522 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 46284 | /* 128525 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46285 | /* 128529 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46286 | /* 128533 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46287 | /* 128537 */ // (strict_fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46288 | /* 128537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD), |
| 46289 | /* 128540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46290 | /* 128542 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 46291 | /* 128544 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 46292 | /* 128546 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46293 | /* 128549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46294 | /* 128555 */ GIR_RootConstrainSelectedInstOperands, |
| 46295 | /* 128556 */ // GIR_Coverage, 616, |
| 46296 | /* 128556 */ GIR_EraseRootFromParent_Done, |
| 46297 | /* 128557 */ // Label 3936: @128557 |
| 46298 | /* 128557 */ GIM_Reject, |
| 46299 | /* 128558 */ // Label 3933: @128558 |
| 46300 | /* 128558 */ GIM_Reject, |
| 46301 | /* 128559 */ // Label 82: @128559 |
| 46302 | /* 128559 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3940*/ GIMT_Encode4(128720), |
| 46303 | /* 128570 */ /*GILLT_s16*//*Label 3937*/ GIMT_Encode4(128582), |
| 46304 | /* 128574 */ /*GILLT_s32*//*Label 3938*/ GIMT_Encode4(128628), |
| 46305 | /* 128578 */ /*GILLT_s64*//*Label 3939*/ GIMT_Encode4(128674), |
| 46306 | /* 128582 */ // Label 3937: @128582 |
| 46307 | /* 128582 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3941*/ GIMT_Encode4(128627), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 626 // |
| 46308 | /* 128589 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46309 | /* 128592 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 46310 | /* 128595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46311 | /* 128599 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46312 | /* 128603 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46313 | /* 128607 */ // (strict_fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46314 | /* 128607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH), |
| 46315 | /* 128610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46316 | /* 128612 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46317 | /* 128614 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46318 | /* 128616 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46319 | /* 128619 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46320 | /* 128625 */ GIR_RootConstrainSelectedInstOperands, |
| 46321 | /* 128626 */ // GIR_Coverage, 626, |
| 46322 | /* 128626 */ GIR_EraseRootFromParent_Done, |
| 46323 | /* 128627 */ // Label 3941: @128627 |
| 46324 | /* 128627 */ GIM_Reject, |
| 46325 | /* 128628 */ // Label 3938: @128628 |
| 46326 | /* 128628 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3942*/ GIMT_Encode4(128673), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 624 // |
| 46327 | /* 128635 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46328 | /* 128638 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 46329 | /* 128641 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46330 | /* 128645 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46331 | /* 128649 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46332 | /* 128653 */ // (strict_fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46333 | /* 128653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS), |
| 46334 | /* 128656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46335 | /* 128658 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46336 | /* 128660 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46337 | /* 128662 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46338 | /* 128665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46339 | /* 128671 */ GIR_RootConstrainSelectedInstOperands, |
| 46340 | /* 128672 */ // GIR_Coverage, 624, |
| 46341 | /* 128672 */ GIR_EraseRootFromParent_Done, |
| 46342 | /* 128673 */ // Label 3942: @128673 |
| 46343 | /* 128673 */ GIM_Reject, |
| 46344 | /* 128674 */ // Label 3939: @128674 |
| 46345 | /* 128674 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3943*/ GIMT_Encode4(128719), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 622 // |
| 46346 | /* 128681 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46347 | /* 128684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 46348 | /* 128687 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46349 | /* 128691 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46350 | /* 128695 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46351 | /* 128699 */ // (strict_fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46352 | /* 128699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD), |
| 46353 | /* 128702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46354 | /* 128704 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 46355 | /* 128706 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 46356 | /* 128708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46357 | /* 128711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46358 | /* 128717 */ GIR_RootConstrainSelectedInstOperands, |
| 46359 | /* 128718 */ // GIR_Coverage, 622, |
| 46360 | /* 128718 */ GIR_EraseRootFromParent_Done, |
| 46361 | /* 128719 */ // Label 3943: @128719 |
| 46362 | /* 128719 */ GIM_Reject, |
| 46363 | /* 128720 */ // Label 3940: @128720 |
| 46364 | /* 128720 */ GIM_Reject, |
| 46365 | /* 128721 */ // Label 83: @128721 |
| 46366 | /* 128721 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3947*/ GIMT_Encode4(128882), |
| 46367 | /* 128732 */ /*GILLT_s16*//*Label 3944*/ GIMT_Encode4(128744), |
| 46368 | /* 128736 */ /*GILLT_s32*//*Label 3945*/ GIMT_Encode4(128790), |
| 46369 | /* 128740 */ /*GILLT_s64*//*Label 3946*/ GIMT_Encode4(128836), |
| 46370 | /* 128744 */ // Label 3944: @128744 |
| 46371 | /* 128744 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3948*/ GIMT_Encode4(128789), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 638 // |
| 46372 | /* 128751 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46373 | /* 128754 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 46374 | /* 128757 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46375 | /* 128761 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46376 | /* 128765 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46377 | /* 128769 */ // (strict_fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46378 | /* 128769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH), |
| 46379 | /* 128772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46380 | /* 128774 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46381 | /* 128776 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46382 | /* 128778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46383 | /* 128781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46384 | /* 128787 */ GIR_RootConstrainSelectedInstOperands, |
| 46385 | /* 128788 */ // GIR_Coverage, 638, |
| 46386 | /* 128788 */ GIR_EraseRootFromParent_Done, |
| 46387 | /* 128789 */ // Label 3948: @128789 |
| 46388 | /* 128789 */ GIM_Reject, |
| 46389 | /* 128790 */ // Label 3945: @128790 |
| 46390 | /* 128790 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3949*/ GIMT_Encode4(128835), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 636 // |
| 46391 | /* 128797 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46392 | /* 128800 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 46393 | /* 128803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46394 | /* 128807 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46395 | /* 128811 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46396 | /* 128815 */ // (strict_fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46397 | /* 128815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS), |
| 46398 | /* 128818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46399 | /* 128820 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46400 | /* 128822 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46401 | /* 128824 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46402 | /* 128827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46403 | /* 128833 */ GIR_RootConstrainSelectedInstOperands, |
| 46404 | /* 128834 */ // GIR_Coverage, 636, |
| 46405 | /* 128834 */ GIR_EraseRootFromParent_Done, |
| 46406 | /* 128835 */ // Label 3949: @128835 |
| 46407 | /* 128835 */ GIM_Reject, |
| 46408 | /* 128836 */ // Label 3946: @128836 |
| 46409 | /* 128836 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3950*/ GIMT_Encode4(128881), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 634 // |
| 46410 | /* 128843 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46411 | /* 128846 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 46412 | /* 128849 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46413 | /* 128853 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46414 | /* 128857 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46415 | /* 128861 */ // (strict_fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46416 | /* 128861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD), |
| 46417 | /* 128864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46418 | /* 128866 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 46419 | /* 128868 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 46420 | /* 128870 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46421 | /* 128873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46422 | /* 128879 */ GIR_RootConstrainSelectedInstOperands, |
| 46423 | /* 128880 */ // GIR_Coverage, 634, |
| 46424 | /* 128880 */ GIR_EraseRootFromParent_Done, |
| 46425 | /* 128881 */ // Label 3950: @128881 |
| 46426 | /* 128881 */ GIM_Reject, |
| 46427 | /* 128882 */ // Label 3947: @128882 |
| 46428 | /* 128882 */ GIM_Reject, |
| 46429 | /* 128883 */ // Label 84: @128883 |
| 46430 | /* 128883 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3954*/ GIMT_Encode4(129044), |
| 46431 | /* 128894 */ /*GILLT_s16*//*Label 3951*/ GIMT_Encode4(128906), |
| 46432 | /* 128898 */ /*GILLT_s32*//*Label 3952*/ GIMT_Encode4(128952), |
| 46433 | /* 128902 */ /*GILLT_s64*//*Label 3953*/ GIMT_Encode4(128998), |
| 46434 | /* 128906 */ // Label 3951: @128906 |
| 46435 | /* 128906 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3955*/ GIMT_Encode4(128951), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 632 // |
| 46436 | /* 128913 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46437 | /* 128916 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 46438 | /* 128919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46439 | /* 128923 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46440 | /* 128927 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46441 | /* 128931 */ // (strict_fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46442 | /* 128931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH), |
| 46443 | /* 128934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46444 | /* 128936 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46445 | /* 128938 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46446 | /* 128940 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46447 | /* 128943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46448 | /* 128949 */ GIR_RootConstrainSelectedInstOperands, |
| 46449 | /* 128950 */ // GIR_Coverage, 632, |
| 46450 | /* 128950 */ GIR_EraseRootFromParent_Done, |
| 46451 | /* 128951 */ // Label 3955: @128951 |
| 46452 | /* 128951 */ GIM_Reject, |
| 46453 | /* 128952 */ // Label 3952: @128952 |
| 46454 | /* 128952 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3956*/ GIMT_Encode4(128997), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 630 // |
| 46455 | /* 128959 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46456 | /* 128962 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 46457 | /* 128965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46458 | /* 128969 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46459 | /* 128973 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46460 | /* 128977 */ // (strict_fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46461 | /* 128977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS), |
| 46462 | /* 128980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46463 | /* 128982 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46464 | /* 128984 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46465 | /* 128986 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46466 | /* 128989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46467 | /* 128995 */ GIR_RootConstrainSelectedInstOperands, |
| 46468 | /* 128996 */ // GIR_Coverage, 630, |
| 46469 | /* 128996 */ GIR_EraseRootFromParent_Done, |
| 46470 | /* 128997 */ // Label 3956: @128997 |
| 46471 | /* 128997 */ GIM_Reject, |
| 46472 | /* 128998 */ // Label 3953: @128998 |
| 46473 | /* 128998 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3957*/ GIMT_Encode4(129043), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 628 // |
| 46474 | /* 129005 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46475 | /* 129008 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 46476 | /* 129011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46477 | /* 129015 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46478 | /* 129019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46479 | /* 129023 */ // (strict_fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46480 | /* 129023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD), |
| 46481 | /* 129026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46482 | /* 129028 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 46483 | /* 129030 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 46484 | /* 129032 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46485 | /* 129035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46486 | /* 129041 */ GIR_RootConstrainSelectedInstOperands, |
| 46487 | /* 129042 */ // GIR_Coverage, 628, |
| 46488 | /* 129042 */ GIR_EraseRootFromParent_Done, |
| 46489 | /* 129043 */ // Label 3957: @129043 |
| 46490 | /* 129043 */ GIM_Reject, |
| 46491 | /* 129044 */ // Label 3954: @129044 |
| 46492 | /* 129044 */ GIM_Reject, |
| 46493 | /* 129045 */ // Label 85: @129045 |
| 46494 | /* 129045 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3961*/ GIMT_Encode4(130211), |
| 46495 | /* 129056 */ /*GILLT_s16*//*Label 3958*/ GIMT_Encode4(129068), |
| 46496 | /* 129060 */ /*GILLT_s32*//*Label 3959*/ GIMT_Encode4(129449), |
| 46497 | /* 129064 */ /*GILLT_s64*//*Label 3960*/ GIMT_Encode4(129830), |
| 46498 | /* 129068 */ // Label 3958: @129068 |
| 46499 | /* 129068 */ GIM_Try, /*On fail goto*//*Label 3962*/ GIMT_Encode4(129448), |
| 46500 | /* 129073 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46501 | /* 129076 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 46502 | /* 129079 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 46503 | /* 129082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46504 | /* 129086 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3963*/ GIMT_Encode4(129159), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2771 // |
| 46505 | /* 129093 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46506 | /* 129097 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46507 | /* 129101 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 46508 | /* 129105 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46509 | /* 129110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46510 | /* 129114 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 46511 | /* 129118 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46512 | /* 129122 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 46513 | /* 129126 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46514 | /* 129131 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 46515 | /* 129133 */ // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46516 | /* 129133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 46517 | /* 129136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46518 | /* 129138 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 46519 | /* 129142 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46520 | /* 129146 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46521 | /* 129148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46522 | /* 129151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46523 | /* 129157 */ GIR_RootConstrainSelectedInstOperands, |
| 46524 | /* 129158 */ // GIR_Coverage, 2771, |
| 46525 | /* 129158 */ GIR_EraseRootFromParent_Done, |
| 46526 | /* 129159 */ // Label 3963: @129159 |
| 46527 | /* 129159 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3964*/ GIMT_Encode4(129232), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6327 // |
| 46528 | /* 129166 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46529 | /* 129170 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 46530 | /* 129174 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46531 | /* 129178 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 46532 | /* 129182 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46533 | /* 129187 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 46534 | /* 129191 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46535 | /* 129195 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 46536 | /* 129199 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46537 | /* 129204 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 46538 | /* 129206 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46539 | /* 129206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH), |
| 46540 | /* 129209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46541 | /* 129211 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 46542 | /* 129215 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46543 | /* 129219 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46544 | /* 129221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46545 | /* 129224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46546 | /* 129230 */ GIR_RootConstrainSelectedInstOperands, |
| 46547 | /* 129231 */ // GIR_Coverage, 6327, |
| 46548 | /* 129231 */ GIR_EraseRootFromParent_Done, |
| 46549 | /* 129232 */ // Label 3964: @129232 |
| 46550 | /* 129232 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3965*/ GIMT_Encode4(129290), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2751 // |
| 46551 | /* 129239 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46552 | /* 129243 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46553 | /* 129247 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 46554 | /* 129251 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46555 | /* 129256 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46556 | /* 129260 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46557 | /* 129264 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46558 | /* 129266 */ // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46559 | /* 129266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 46560 | /* 129269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46561 | /* 129271 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 46562 | /* 129273 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46563 | /* 129277 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46564 | /* 129279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46565 | /* 129282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46566 | /* 129288 */ GIR_RootConstrainSelectedInstOperands, |
| 46567 | /* 129289 */ // GIR_Coverage, 2751, |
| 46568 | /* 129289 */ GIR_EraseRootFromParent_Done, |
| 46569 | /* 129290 */ // Label 3965: @129290 |
| 46570 | /* 129290 */ GIM_Try, /*On fail goto*//*Label 3966*/ GIMT_Encode4(129447), |
| 46571 | /* 129295 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46572 | /* 129299 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3967*/ GIMT_Encode4(129353), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6321 // |
| 46573 | /* 129306 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 46574 | /* 129310 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46575 | /* 129314 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 46576 | /* 129318 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46577 | /* 129323 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46578 | /* 129327 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46579 | /* 129329 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46580 | /* 129329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH), |
| 46581 | /* 129332 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46582 | /* 129334 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 46583 | /* 129336 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46584 | /* 129340 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46585 | /* 129342 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46586 | /* 129345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46587 | /* 129351 */ GIR_RootConstrainSelectedInstOperands, |
| 46588 | /* 129352 */ // GIR_Coverage, 6321, |
| 46589 | /* 129352 */ GIR_EraseRootFromParent_Done, |
| 46590 | /* 129353 */ // Label 3967: @129353 |
| 46591 | /* 129353 */ GIM_Try, /*On fail goto*//*Label 3968*/ GIMT_Encode4(129446), |
| 46592 | /* 129358 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46593 | /* 129362 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3969*/ GIMT_Encode4(129412), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2785 // |
| 46594 | /* 129369 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 46595 | /* 129373 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46596 | /* 129377 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 46597 | /* 129381 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46598 | /* 129386 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46599 | /* 129388 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46600 | /* 129388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH), |
| 46601 | /* 129391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46602 | /* 129393 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 46603 | /* 129397 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46604 | /* 129399 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46605 | /* 129401 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46606 | /* 129404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46607 | /* 129410 */ GIR_RootConstrainSelectedInstOperands, |
| 46608 | /* 129411 */ // GIR_Coverage, 2785, |
| 46609 | /* 129411 */ GIR_EraseRootFromParent_Done, |
| 46610 | /* 129412 */ // Label 3969: @129412 |
| 46611 | /* 129412 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3970*/ GIMT_Encode4(129445), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2733 // |
| 46612 | /* 129419 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46613 | /* 129423 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) |
| 46614 | /* 129423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH), |
| 46615 | /* 129426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46616 | /* 129428 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 46617 | /* 129430 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46618 | /* 129432 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46619 | /* 129434 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46620 | /* 129437 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46621 | /* 129443 */ GIR_RootConstrainSelectedInstOperands, |
| 46622 | /* 129444 */ // GIR_Coverage, 2733, |
| 46623 | /* 129444 */ GIR_EraseRootFromParent_Done, |
| 46624 | /* 129445 */ // Label 3970: @129445 |
| 46625 | /* 129445 */ GIM_Reject, |
| 46626 | /* 129446 */ // Label 3968: @129446 |
| 46627 | /* 129446 */ GIM_Reject, |
| 46628 | /* 129447 */ // Label 3966: @129447 |
| 46629 | /* 129447 */ GIM_Reject, |
| 46630 | /* 129448 */ // Label 3962: @129448 |
| 46631 | /* 129448 */ GIM_Reject, |
| 46632 | /* 129449 */ // Label 3959: @129449 |
| 46633 | /* 129449 */ GIM_Try, /*On fail goto*//*Label 3971*/ GIMT_Encode4(129829), |
| 46634 | /* 129454 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46635 | /* 129457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 46636 | /* 129460 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 46637 | /* 129463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46638 | /* 129467 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3972*/ GIMT_Encode4(129540), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2769 // |
| 46639 | /* 129474 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46640 | /* 129478 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46641 | /* 129482 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 46642 | /* 129486 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46643 | /* 129491 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46644 | /* 129495 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 46645 | /* 129499 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46646 | /* 129503 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 46647 | /* 129507 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46648 | /* 129512 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 46649 | /* 129514 */ // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46650 | /* 129514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 46651 | /* 129517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46652 | /* 129519 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 46653 | /* 129523 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46654 | /* 129527 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46655 | /* 129529 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46656 | /* 129532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46657 | /* 129538 */ GIR_RootConstrainSelectedInstOperands, |
| 46658 | /* 129539 */ // GIR_Coverage, 2769, |
| 46659 | /* 129539 */ GIR_EraseRootFromParent_Done, |
| 46660 | /* 129540 */ // Label 3972: @129540 |
| 46661 | /* 129540 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3973*/ GIMT_Encode4(129613), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6325 // |
| 46662 | /* 129547 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46663 | /* 129551 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 46664 | /* 129555 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46665 | /* 129559 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 46666 | /* 129563 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46667 | /* 129568 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 46668 | /* 129572 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46669 | /* 129576 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 46670 | /* 129580 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46671 | /* 129585 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 46672 | /* 129587 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46673 | /* 129587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS), |
| 46674 | /* 129590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46675 | /* 129592 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin |
| 46676 | /* 129596 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46677 | /* 129600 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46678 | /* 129602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46679 | /* 129605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46680 | /* 129611 */ GIR_RootConstrainSelectedInstOperands, |
| 46681 | /* 129612 */ // GIR_Coverage, 6325, |
| 46682 | /* 129612 */ GIR_EraseRootFromParent_Done, |
| 46683 | /* 129613 */ // Label 3973: @129613 |
| 46684 | /* 129613 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3974*/ GIMT_Encode4(129671), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2749 // |
| 46685 | /* 129620 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46686 | /* 129624 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46687 | /* 129628 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 46688 | /* 129632 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46689 | /* 129637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46690 | /* 129641 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46691 | /* 129645 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46692 | /* 129647 */ // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46693 | /* 129647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 46694 | /* 129650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46695 | /* 129652 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 46696 | /* 129654 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46697 | /* 129658 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46698 | /* 129660 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46699 | /* 129663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46700 | /* 129669 */ GIR_RootConstrainSelectedInstOperands, |
| 46701 | /* 129670 */ // GIR_Coverage, 2749, |
| 46702 | /* 129670 */ GIR_EraseRootFromParent_Done, |
| 46703 | /* 129671 */ // Label 3974: @129671 |
| 46704 | /* 129671 */ GIM_Try, /*On fail goto*//*Label 3975*/ GIMT_Encode4(129828), |
| 46705 | /* 129676 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46706 | /* 129680 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3976*/ GIMT_Encode4(129734), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6319 // |
| 46707 | /* 129687 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 46708 | /* 129691 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46709 | /* 129695 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 46710 | /* 129699 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46711 | /* 129704 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46712 | /* 129708 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46713 | /* 129710 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46714 | /* 129710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS), |
| 46715 | /* 129713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46716 | /* 129715 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 46717 | /* 129717 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn |
| 46718 | /* 129721 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46719 | /* 129723 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46720 | /* 129726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46721 | /* 129732 */ GIR_RootConstrainSelectedInstOperands, |
| 46722 | /* 129733 */ // GIR_Coverage, 6319, |
| 46723 | /* 129733 */ GIR_EraseRootFromParent_Done, |
| 46724 | /* 129734 */ // Label 3976: @129734 |
| 46725 | /* 129734 */ GIM_Try, /*On fail goto*//*Label 3977*/ GIMT_Encode4(129827), |
| 46726 | /* 129739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46727 | /* 129743 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3978*/ GIMT_Encode4(129793), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2783 // |
| 46728 | /* 129750 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 46729 | /* 129754 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46730 | /* 129758 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 46731 | /* 129762 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46732 | /* 129767 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46733 | /* 129769 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46734 | /* 129769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS), |
| 46735 | /* 129772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46736 | /* 129774 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin |
| 46737 | /* 129778 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46738 | /* 129780 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46739 | /* 129782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46740 | /* 129785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46741 | /* 129791 */ GIR_RootConstrainSelectedInstOperands, |
| 46742 | /* 129792 */ // GIR_Coverage, 2783, |
| 46743 | /* 129792 */ GIR_EraseRootFromParent_Done, |
| 46744 | /* 129793 */ // Label 3978: @129793 |
| 46745 | /* 129793 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3979*/ GIMT_Encode4(129826), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2731 // |
| 46746 | /* 129800 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46747 | /* 129804 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) |
| 46748 | /* 129804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS), |
| 46749 | /* 129807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46750 | /* 129809 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin |
| 46751 | /* 129811 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn |
| 46752 | /* 129813 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm |
| 46753 | /* 129815 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46754 | /* 129818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46755 | /* 129824 */ GIR_RootConstrainSelectedInstOperands, |
| 46756 | /* 129825 */ // GIR_Coverage, 2731, |
| 46757 | /* 129825 */ GIR_EraseRootFromParent_Done, |
| 46758 | /* 129826 */ // Label 3979: @129826 |
| 46759 | /* 129826 */ GIM_Reject, |
| 46760 | /* 129827 */ // Label 3977: @129827 |
| 46761 | /* 129827 */ GIM_Reject, |
| 46762 | /* 129828 */ // Label 3975: @129828 |
| 46763 | /* 129828 */ GIM_Reject, |
| 46764 | /* 129829 */ // Label 3971: @129829 |
| 46765 | /* 129829 */ GIM_Reject, |
| 46766 | /* 129830 */ // Label 3960: @129830 |
| 46767 | /* 129830 */ GIM_Try, /*On fail goto*//*Label 3980*/ GIMT_Encode4(130210), |
| 46768 | /* 129835 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46769 | /* 129838 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 46770 | /* 129841 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 46771 | /* 129844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46772 | /* 129848 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3981*/ GIMT_Encode4(129921), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2767 // |
| 46773 | /* 129855 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46774 | /* 129859 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46775 | /* 129863 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 46776 | /* 129867 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46777 | /* 129872 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46778 | /* 129876 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 46779 | /* 129880 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46780 | /* 129884 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 46781 | /* 129888 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46782 | /* 129893 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 46783 | /* 129895 */ // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46784 | /* 129895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 46785 | /* 129898 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46786 | /* 129900 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 46787 | /* 129904 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 46788 | /* 129908 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 46789 | /* 129910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46790 | /* 129913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46791 | /* 129919 */ GIR_RootConstrainSelectedInstOperands, |
| 46792 | /* 129920 */ // GIR_Coverage, 2767, |
| 46793 | /* 129920 */ GIR_EraseRootFromParent_Done, |
| 46794 | /* 129921 */ // Label 3981: @129921 |
| 46795 | /* 129921 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3982*/ GIMT_Encode4(129994), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6323 // |
| 46796 | /* 129928 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46797 | /* 129932 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 46798 | /* 129936 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46799 | /* 129940 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 46800 | /* 129944 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46801 | /* 129949 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2] |
| 46802 | /* 129953 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46803 | /* 129957 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 46804 | /* 129961 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46805 | /* 129966 */ GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 46806 | /* 129968 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46807 | /* 129968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD), |
| 46808 | /* 129971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46809 | /* 129973 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin |
| 46810 | /* 129977 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 46811 | /* 129981 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 46812 | /* 129983 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46813 | /* 129986 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46814 | /* 129992 */ GIR_RootConstrainSelectedInstOperands, |
| 46815 | /* 129993 */ // GIR_Coverage, 6323, |
| 46816 | /* 129993 */ GIR_EraseRootFromParent_Done, |
| 46817 | /* 129994 */ // Label 3982: @129994 |
| 46818 | /* 129994 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3983*/ GIMT_Encode4(130052), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2747 // |
| 46819 | /* 130001 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 46820 | /* 130005 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46821 | /* 130009 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 46822 | /* 130013 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46823 | /* 130018 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46824 | /* 130022 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46825 | /* 130026 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46826 | /* 130028 */ // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46827 | /* 130028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 46828 | /* 130031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46829 | /* 130033 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 46830 | /* 130035 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 46831 | /* 130039 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 46832 | /* 130041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46833 | /* 130044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46834 | /* 130050 */ GIR_RootConstrainSelectedInstOperands, |
| 46835 | /* 130051 */ // GIR_Coverage, 2747, |
| 46836 | /* 130051 */ GIR_EraseRootFromParent_Done, |
| 46837 | /* 130052 */ // Label 3983: @130052 |
| 46838 | /* 130052 */ GIM_Try, /*On fail goto*//*Label 3984*/ GIMT_Encode4(130209), |
| 46839 | /* 130057 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46840 | /* 130061 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3985*/ GIMT_Encode4(130115), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6317 // |
| 46841 | /* 130068 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 46842 | /* 130072 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46843 | /* 130076 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 46844 | /* 130080 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46845 | /* 130085 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46846 | /* 130089 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46847 | /* 130091 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46848 | /* 130091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD), |
| 46849 | /* 130094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46850 | /* 130096 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 46851 | /* 130098 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn |
| 46852 | /* 130102 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 46853 | /* 130104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46854 | /* 130107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46855 | /* 130113 */ GIR_RootConstrainSelectedInstOperands, |
| 46856 | /* 130114 */ // GIR_Coverage, 6317, |
| 46857 | /* 130114 */ GIR_EraseRootFromParent_Done, |
| 46858 | /* 130115 */ // Label 3985: @130115 |
| 46859 | /* 130115 */ GIM_Try, /*On fail goto*//*Label 3986*/ GIMT_Encode4(130208), |
| 46860 | /* 130120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46861 | /* 130124 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3987*/ GIMT_Encode4(130174), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2781 // |
| 46862 | /* 130131 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] |
| 46863 | /* 130135 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 46864 | /* 130139 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 46865 | /* 130143 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46866 | /* 130148 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46867 | /* 130150 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46868 | /* 130150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD), |
| 46869 | /* 130153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46870 | /* 130155 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin |
| 46871 | /* 130159 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 46872 | /* 130161 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 46873 | /* 130163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46874 | /* 130166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46875 | /* 130172 */ GIR_RootConstrainSelectedInstOperands, |
| 46876 | /* 130173 */ // GIR_Coverage, 2781, |
| 46877 | /* 130173 */ GIR_EraseRootFromParent_Done, |
| 46878 | /* 130174 */ // Label 3987: @130174 |
| 46879 | /* 130174 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3988*/ GIMT_Encode4(130207), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2729 // |
| 46880 | /* 130181 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46881 | /* 130185 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) |
| 46882 | /* 130185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD), |
| 46883 | /* 130188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46884 | /* 130190 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin |
| 46885 | /* 130192 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn |
| 46886 | /* 130194 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm |
| 46887 | /* 130196 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46888 | /* 130199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46889 | /* 130205 */ GIR_RootConstrainSelectedInstOperands, |
| 46890 | /* 130206 */ // GIR_Coverage, 2729, |
| 46891 | /* 130206 */ GIR_EraseRootFromParent_Done, |
| 46892 | /* 130207 */ // Label 3988: @130207 |
| 46893 | /* 130207 */ GIM_Reject, |
| 46894 | /* 130208 */ // Label 3986: @130208 |
| 46895 | /* 130208 */ GIM_Reject, |
| 46896 | /* 130209 */ // Label 3984: @130209 |
| 46897 | /* 130209 */ GIM_Reject, |
| 46898 | /* 130210 */ // Label 3980: @130210 |
| 46899 | /* 130210 */ GIM_Reject, |
| 46900 | /* 130211 */ // Label 3961: @130211 |
| 46901 | /* 130211 */ GIM_Reject, |
| 46902 | /* 130212 */ // Label 86: @130212 |
| 46903 | /* 130212 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3992*/ GIMT_Encode4(130346), |
| 46904 | /* 130223 */ /*GILLT_s16*//*Label 3989*/ GIMT_Encode4(130235), |
| 46905 | /* 130227 */ /*GILLT_s32*//*Label 3990*/ GIMT_Encode4(130272), |
| 46906 | /* 130231 */ /*GILLT_s64*//*Label 3991*/ GIMT_Encode4(130309), |
| 46907 | /* 130235 */ // Label 3989: @130235 |
| 46908 | /* 130235 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3993*/ GIMT_Encode4(130271), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 738 // |
| 46909 | /* 130242 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 46910 | /* 130245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46911 | /* 130249 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID), |
| 46912 | /* 130253 */ // (strict_fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm) |
| 46913 | /* 130253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH), |
| 46914 | /* 130256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46915 | /* 130258 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46916 | /* 130260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46917 | /* 130263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46918 | /* 130269 */ GIR_RootConstrainSelectedInstOperands, |
| 46919 | /* 130270 */ // GIR_Coverage, 738, |
| 46920 | /* 130270 */ GIR_EraseRootFromParent_Done, |
| 46921 | /* 130271 */ // Label 3993: @130271 |
| 46922 | /* 130271 */ GIM_Reject, |
| 46923 | /* 130272 */ // Label 3990: @130272 |
| 46924 | /* 130272 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3994*/ GIMT_Encode4(130308), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 736 // |
| 46925 | /* 130279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 46926 | /* 130282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46927 | /* 130286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID), |
| 46928 | /* 130290 */ // (strict_fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm) |
| 46929 | /* 130290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS), |
| 46930 | /* 130293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd] |
| 46931 | /* 130295 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm |
| 46932 | /* 130297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46933 | /* 130300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46934 | /* 130306 */ GIR_RootConstrainSelectedInstOperands, |
| 46935 | /* 130307 */ // GIR_Coverage, 736, |
| 46936 | /* 130307 */ GIR_EraseRootFromParent_Done, |
| 46937 | /* 130308 */ // Label 3994: @130308 |
| 46938 | /* 130308 */ GIM_Reject, |
| 46939 | /* 130309 */ // Label 3991: @130309 |
| 46940 | /* 130309 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3995*/ GIMT_Encode4(130345), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 734 // |
| 46941 | /* 130316 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 46942 | /* 130319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46943 | /* 130323 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID), |
| 46944 | /* 130327 */ // (strict_fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm) |
| 46945 | /* 130327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD), |
| 46946 | /* 130330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd] |
| 46947 | /* 130332 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm |
| 46948 | /* 130334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14, |
| 46949 | /* 130337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 46950 | /* 130343 */ GIR_RootConstrainSelectedInstOperands, |
| 46951 | /* 130344 */ // GIR_Coverage, 734, |
| 46952 | /* 130344 */ GIR_EraseRootFromParent_Done, |
| 46953 | /* 130345 */ // Label 3995: @130345 |
| 46954 | /* 130345 */ GIM_Reject, |
| 46955 | /* 130346 */ // Label 3992: @130346 |
| 46956 | /* 130346 */ GIM_Reject, |
| 46957 | /* 130347 */ // Label 87: @130347 |
| 46958 | /* 130347 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3996*/ GIMT_Encode4(130361), GIMT_Encode2(GIFBS_IsARM), // Rule ID 12 // |
| 46959 | /* 130354 */ // (trap) => (TRAP) |
| 46960 | /* 130354 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::TRAP), |
| 46961 | /* 130359 */ GIR_RootConstrainSelectedInstOperands, |
| 46962 | /* 130360 */ // GIR_Coverage, 12, |
| 46963 | /* 130360 */ GIR_Done, |
| 46964 | /* 130361 */ // Label 3996: @130361 |
| 46965 | /* 130361 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3997*/ GIMT_Encode4(130375), GIMT_Encode2(GIFBS_IsThumb), // Rule ID 284 // |
| 46966 | /* 130368 */ // (trap) => (tTRAP) |
| 46967 | /* 130368 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tTRAP), |
| 46968 | /* 130373 */ GIR_RootConstrainSelectedInstOperands, |
| 46969 | /* 130374 */ // GIR_Coverage, 284, |
| 46970 | /* 130374 */ GIR_Done, |
| 46971 | /* 130375 */ // Label 3997: @130375 |
| 46972 | /* 130375 */ GIM_Reject, |
| 46973 | /* 130376 */ // Label 88: @130376 |
| 46974 | /* 130376 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3998*/ GIMT_Encode4(130391), GIMT_Encode2(GIFBS_HasV5T_IsARM), // Rule ID 2026 // |
| 46975 | /* 130383 */ // (debugtrap) => (BKPT 0:{ *:[i32] }) |
| 46976 | /* 130383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BKPT), |
| 46977 | /* 130386 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46978 | /* 130389 */ GIR_RootConstrainSelectedInstOperands, |
| 46979 | /* 130390 */ // GIR_Coverage, 2026, |
| 46980 | /* 130390 */ GIR_EraseRootFromParent_Done, |
| 46981 | /* 130391 */ // Label 3998: @130391 |
| 46982 | /* 130391 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3999*/ GIMT_Encode4(130417), GIMT_Encode2(GIFBS_IsARM_NoV5T), // Rule ID 2027 // |
| 46983 | /* 130398 */ // (debugtrap) => (UDF 254:{ *:[i32] }) |
| 46984 | /* 130398 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF), |
| 46985 | /* 130401 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254), |
| 46986 | /* 130411 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46987 | /* 130415 */ GIR_RootConstrainSelectedInstOperands, |
| 46988 | /* 130416 */ // GIR_Coverage, 2027, |
| 46989 | /* 130416 */ GIR_EraseRootFromParent_Done, |
| 46990 | /* 130417 */ // Label 3999: @130417 |
| 46991 | /* 130417 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4000*/ GIMT_Encode4(130432), GIMT_Encode2(GIFBS_HasV5T_IsThumb), // Rule ID 2217 // |
| 46992 | /* 130424 */ // (debugtrap) => (tBKPT 0:{ *:[i32] }) |
| 46993 | /* 130424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBKPT), |
| 46994 | /* 130427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46995 | /* 130430 */ GIR_RootConstrainSelectedInstOperands, |
| 46996 | /* 130431 */ // GIR_Coverage, 2217, |
| 46997 | /* 130431 */ GIR_EraseRootFromParent_Done, |
| 46998 | /* 130432 */ // Label 4000: @130432 |
| 46999 | /* 130432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4001*/ GIMT_Encode4(130458), GIMT_Encode2(GIFBS_IsThumb_NoV5T), // Rule ID 2218 // |
| 47000 | /* 130439 */ // (debugtrap) => (tUDF 254:{ *:[i32] }) |
| 47001 | /* 130439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF), |
| 47002 | /* 130442 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254), |
| 47003 | /* 130452 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47004 | /* 130456 */ GIR_RootConstrainSelectedInstOperands, |
| 47005 | /* 130457 */ // GIR_Coverage, 2218, |
| 47006 | /* 130457 */ GIR_EraseRootFromParent_Done, |
| 47007 | /* 130458 */ // Label 4001: @130458 |
| 47008 | /* 130458 */ GIM_Reject, |
| 47009 | /* 130459 */ // Label 89: @130459 |
| 47010 | /* 130459 */ GIM_Try, /*On fail goto*//*Label 4002*/ GIMT_Encode4(130832), |
| 47011 | /* 130464 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 47012 | /* 130467 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4006*/ GIMT_Encode4(130831), |
| 47013 | /* 130478 */ /*GILLT_v16s8*//*Label 4003*/ GIMT_Encode4(130498), GIMT_Encode4(0), |
| 47014 | /* 130486 */ /*GILLT_v8s16*//*Label 4004*/ GIMT_Encode4(130609), GIMT_Encode4(0), |
| 47015 | /* 130494 */ /*GILLT_v4s32*//*Label 4005*/ GIMT_Encode4(130720), |
| 47016 | /* 130498 */ // Label 4003: @130498 |
| 47017 | /* 130498 */ GIM_Try, /*On fail goto*//*Label 4007*/ GIMT_Encode4(130608), |
| 47018 | /* 130503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 47019 | /* 130507 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4008*/ GIMT_Encode4(130572), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3633 // |
| 47020 | /* 130514 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 47021 | /* 130518 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 47022 | /* 130522 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8, |
| 47023 | /* 130526 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8, |
| 47024 | /* 130530 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47025 | /* 130535 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47026 | /* 130540 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47027 | /* 130542 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)) => (MVE_VMLADAVu8:{ *:[i32] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2) |
| 47028 | /* 130542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8), |
| 47029 | /* 130545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47030 | /* 130547 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 47031 | /* 130551 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 47032 | /* 130555 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47033 | /* 130558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47034 | /* 130564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47035 | /* 130570 */ GIR_RootConstrainSelectedInstOperands, |
| 47036 | /* 130571 */ // GIR_Coverage, 3633, |
| 47037 | /* 130571 */ GIR_EraseRootFromParent_Done, |
| 47038 | /* 130572 */ // Label 4008: @130572 |
| 47039 | /* 130572 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4009*/ GIMT_Encode4(130607), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3437 // |
| 47040 | /* 130579 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47041 | /* 130583 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec) => (MVE_VADDVu8no_acc:{ *:[i32] } ?:{ *:[v16i8] }:$vec) |
| 47042 | /* 130583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8no_acc), |
| 47043 | /* 130586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 47044 | /* 130588 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec |
| 47045 | /* 130590 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47046 | /* 130593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47047 | /* 130599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47048 | /* 130605 */ GIR_RootConstrainSelectedInstOperands, |
| 47049 | /* 130606 */ // GIR_Coverage, 3437, |
| 47050 | /* 130606 */ GIR_EraseRootFromParent_Done, |
| 47051 | /* 130607 */ // Label 4009: @130607 |
| 47052 | /* 130607 */ GIM_Reject, |
| 47053 | /* 130608 */ // Label 4007: @130608 |
| 47054 | /* 130608 */ GIM_Reject, |
| 47055 | /* 130609 */ // Label 4004: @130609 |
| 47056 | /* 130609 */ GIM_Try, /*On fail goto*//*Label 4010*/ GIMT_Encode4(130719), |
| 47057 | /* 130614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 47058 | /* 130618 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4011*/ GIMT_Encode4(130683), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3630 // |
| 47059 | /* 130625 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 47060 | /* 130629 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 47061 | /* 130633 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16, |
| 47062 | /* 130637 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16, |
| 47063 | /* 130641 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47064 | /* 130646 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47065 | /* 130651 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47066 | /* 130653 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)) => (MVE_VMLADAVu16:{ *:[i32] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2) |
| 47067 | /* 130653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16), |
| 47068 | /* 130656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47069 | /* 130658 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 47070 | /* 130662 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 47071 | /* 130666 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47072 | /* 130669 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47073 | /* 130675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47074 | /* 130681 */ GIR_RootConstrainSelectedInstOperands, |
| 47075 | /* 130682 */ // GIR_Coverage, 3630, |
| 47076 | /* 130682 */ GIR_EraseRootFromParent_Done, |
| 47077 | /* 130683 */ // Label 4011: @130683 |
| 47078 | /* 130683 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4012*/ GIMT_Encode4(130718), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3465 // |
| 47079 | /* 130690 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47080 | /* 130694 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec) => (MVE_VADDVu16no_acc:{ *:[i32] } ?:{ *:[v8i16] }:$vec) |
| 47081 | /* 130694 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16no_acc), |
| 47082 | /* 130697 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 47083 | /* 130699 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec |
| 47084 | /* 130701 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47085 | /* 130704 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47086 | /* 130710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47087 | /* 130716 */ GIR_RootConstrainSelectedInstOperands, |
| 47088 | /* 130717 */ // GIR_Coverage, 3465, |
| 47089 | /* 130717 */ GIR_EraseRootFromParent_Done, |
| 47090 | /* 130718 */ // Label 4012: @130718 |
| 47091 | /* 130718 */ GIM_Reject, |
| 47092 | /* 130719 */ // Label 4010: @130719 |
| 47093 | /* 130719 */ GIM_Reject, |
| 47094 | /* 130720 */ // Label 4005: @130720 |
| 47095 | /* 130720 */ GIM_Try, /*On fail goto*//*Label 4013*/ GIMT_Encode4(130830), |
| 47096 | /* 130725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID), |
| 47097 | /* 130729 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4014*/ GIMT_Encode4(130794), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3629 // |
| 47098 | /* 130736 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 47099 | /* 130740 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 47100 | /* 130744 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32, |
| 47101 | /* 130748 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32, |
| 47102 | /* 130752 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47103 | /* 130757 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47104 | /* 130762 */ GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 47105 | /* 130764 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)) => (MVE_VMLADAVu32:{ *:[i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2) |
| 47106 | /* 130764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32), |
| 47107 | /* 130767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47108 | /* 130769 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 47109 | /* 130773 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 47110 | /* 130777 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47111 | /* 130780 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47112 | /* 130786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47113 | /* 130792 */ GIR_RootConstrainSelectedInstOperands, |
| 47114 | /* 130793 */ // GIR_Coverage, 3629, |
| 47115 | /* 130793 */ GIR_EraseRootFromParent_Done, |
| 47116 | /* 130794 */ // Label 4014: @130794 |
| 47117 | /* 130794 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4015*/ GIMT_Encode4(130829), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3475 // |
| 47118 | /* 130801 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47119 | /* 130805 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec) => (MVE_VADDVu32no_acc:{ *:[i32] } ?:{ *:[v4i32] }:$vec) |
| 47120 | /* 130805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32no_acc), |
| 47121 | /* 130808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda] |
| 47122 | /* 130810 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec |
| 47123 | /* 130812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47124 | /* 130815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47125 | /* 130821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47126 | /* 130827 */ GIR_RootConstrainSelectedInstOperands, |
| 47127 | /* 130828 */ // GIR_Coverage, 3475, |
| 47128 | /* 130828 */ GIR_EraseRootFromParent_Done, |
| 47129 | /* 130829 */ // Label 4015: @130829 |
| 47130 | /* 130829 */ GIM_Reject, |
| 47131 | /* 130830 */ // Label 4013: @130830 |
| 47132 | /* 130830 */ GIM_Reject, |
| 47133 | /* 130831 */ // Label 4006: @130831 |
| 47134 | /* 130831 */ GIM_Reject, |
| 47135 | /* 130832 */ // Label 4002: @130832 |
| 47136 | /* 130832 */ GIM_Reject, |
| 47137 | /* 130833 */ // Label 90: @130833 |
| 47138 | /* 130833 */ GIM_Try, /*On fail goto*//*Label 4016*/ GIMT_Encode4(131097), |
| 47139 | /* 130838 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 47140 | /* 130841 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4020*/ GIMT_Encode4(131096), |
| 47141 | /* 130852 */ /*GILLT_v16s8*//*Label 4017*/ GIMT_Encode4(130872), GIMT_Encode4(0), |
| 47142 | /* 130860 */ /*GILLT_v8s16*//*Label 4018*/ GIMT_Encode4(130947), GIMT_Encode4(0), |
| 47143 | /* 130868 */ /*GILLT_v4s32*//*Label 4019*/ GIMT_Encode4(131014), |
| 47144 | /* 130872 */ // Label 4017: @130872 |
| 47145 | /* 130872 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4021*/ GIMT_Encode4(130946), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3533 // |
| 47146 | /* 130879 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47147 | /* 130883 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47148 | /* 130887 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVs8:{ *:[i32] } (t2MVNi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 47149 | /* 130887 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47150 | /* 130890 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 47151 | /* 130894 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47152 | /* 130899 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127, |
| 47153 | /* 130902 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47154 | /* 130905 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47155 | /* 130911 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47156 | /* 130917 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47157 | /* 130919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8), |
| 47158 | /* 130922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47159 | /* 130924 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47160 | /* 130927 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47161 | /* 130929 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47162 | /* 130932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47163 | /* 130938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47164 | /* 130944 */ GIR_RootConstrainSelectedInstOperands, |
| 47165 | /* 130945 */ // GIR_Coverage, 3533, |
| 47166 | /* 130945 */ GIR_EraseRootFromParent_Done, |
| 47167 | /* 130946 */ // Label 4021: @130946 |
| 47168 | /* 130946 */ GIM_Reject, |
| 47169 | /* 130947 */ // Label 4018: @130947 |
| 47170 | /* 130947 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4022*/ GIMT_Encode4(131013), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3534 // |
| 47171 | /* 130954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47172 | /* 130958 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47173 | /* 130962 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVs16:{ *:[i32] } (t2MOVi32imm:{ *:[i32] } -32768:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 47174 | /* 130962 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47175 | /* 130965 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm), |
| 47176 | /* 130969 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47177 | /* 130974 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744073709518848u), |
| 47178 | /* 130984 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47179 | /* 130986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16), |
| 47180 | /* 130989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47181 | /* 130991 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47182 | /* 130994 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47183 | /* 130996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47184 | /* 130999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47185 | /* 131005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47186 | /* 131011 */ GIR_RootConstrainSelectedInstOperands, |
| 47187 | /* 131012 */ // GIR_Coverage, 3534, |
| 47188 | /* 131012 */ GIR_EraseRootFromParent_Done, |
| 47189 | /* 131013 */ // Label 4022: @131013 |
| 47190 | /* 131013 */ GIM_Reject, |
| 47191 | /* 131014 */ // Label 4019: @131014 |
| 47192 | /* 131014 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4023*/ GIMT_Encode4(131095), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3535 // |
| 47193 | /* 131021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47194 | /* 131025 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47195 | /* 131029 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVs32:{ *:[i32] } (t2MOVi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 47196 | /* 131029 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47197 | /* 131032 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 47198 | /* 131036 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47199 | /* 131041 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744071562067968u), |
| 47200 | /* 131051 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47201 | /* 131054 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47202 | /* 131060 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47203 | /* 131066 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47204 | /* 131068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32), |
| 47205 | /* 131071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47206 | /* 131073 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47207 | /* 131076 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47208 | /* 131078 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47209 | /* 131081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47210 | /* 131087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47211 | /* 131093 */ GIR_RootConstrainSelectedInstOperands, |
| 47212 | /* 131094 */ // GIR_Coverage, 3535, |
| 47213 | /* 131094 */ GIR_EraseRootFromParent_Done, |
| 47214 | /* 131095 */ // Label 4023: @131095 |
| 47215 | /* 131095 */ GIM_Reject, |
| 47216 | /* 131096 */ // Label 4020: @131096 |
| 47217 | /* 131096 */ GIM_Reject, |
| 47218 | /* 131097 */ // Label 4016: @131097 |
| 47219 | /* 131097 */ GIM_Reject, |
| 47220 | /* 131098 */ // Label 91: @131098 |
| 47221 | /* 131098 */ GIM_Try, /*On fail goto*//*Label 4024*/ GIMT_Encode4(131371), |
| 47222 | /* 131103 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 47223 | /* 131106 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4028*/ GIMT_Encode4(131370), |
| 47224 | /* 131117 */ /*GILLT_v16s8*//*Label 4025*/ GIMT_Encode4(131137), GIMT_Encode4(0), |
| 47225 | /* 131125 */ /*GILLT_v8s16*//*Label 4026*/ GIMT_Encode4(131212), GIMT_Encode4(0), |
| 47226 | /* 131133 */ /*GILLT_v4s32*//*Label 4027*/ GIMT_Encode4(131288), |
| 47227 | /* 131137 */ // Label 4025: @131137 |
| 47228 | /* 131137 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4029*/ GIMT_Encode4(131211), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3539 // |
| 47229 | /* 131144 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47230 | /* 131148 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47231 | /* 131152 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVs8:{ *:[i32] } (t2MOVi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 47232 | /* 131152 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47233 | /* 131155 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 47234 | /* 131159 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47235 | /* 131164 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127, |
| 47236 | /* 131167 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47237 | /* 131170 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47238 | /* 131176 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47239 | /* 131182 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47240 | /* 131184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8), |
| 47241 | /* 131187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47242 | /* 131189 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47243 | /* 131192 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47244 | /* 131194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47245 | /* 131197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47246 | /* 131203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47247 | /* 131209 */ GIR_RootConstrainSelectedInstOperands, |
| 47248 | /* 131210 */ // GIR_Coverage, 3539, |
| 47249 | /* 131210 */ GIR_EraseRootFromParent_Done, |
| 47250 | /* 131211 */ // Label 4029: @131211 |
| 47251 | /* 131211 */ GIM_Reject, |
| 47252 | /* 131212 */ // Label 4026: @131212 |
| 47253 | /* 131212 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4030*/ GIMT_Encode4(131287), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3540 // |
| 47254 | /* 131219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47255 | /* 131223 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47256 | /* 131227 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVs16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 32767:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 47257 | /* 131227 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47258 | /* 131230 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16), |
| 47259 | /* 131234 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47260 | /* 131239 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767), |
| 47261 | /* 131249 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47262 | /* 131252 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47263 | /* 131258 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47264 | /* 131260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16), |
| 47265 | /* 131263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47266 | /* 131265 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47267 | /* 131268 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47268 | /* 131270 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47269 | /* 131273 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47270 | /* 131279 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47271 | /* 131285 */ GIR_RootConstrainSelectedInstOperands, |
| 47272 | /* 131286 */ // GIR_Coverage, 3540, |
| 47273 | /* 131286 */ GIR_EraseRootFromParent_Done, |
| 47274 | /* 131287 */ // Label 4030: @131287 |
| 47275 | /* 131287 */ GIM_Reject, |
| 47276 | /* 131288 */ // Label 4027: @131288 |
| 47277 | /* 131288 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4031*/ GIMT_Encode4(131369), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3541 // |
| 47278 | /* 131295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47279 | /* 131299 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47280 | /* 131303 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVs32:{ *:[i32] } (t2MVNi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 47281 | /* 131303 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47282 | /* 131306 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi), |
| 47283 | /* 131310 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47284 | /* 131315 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744071562067968u), |
| 47285 | /* 131325 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47286 | /* 131328 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47287 | /* 131334 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47288 | /* 131340 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47289 | /* 131342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32), |
| 47290 | /* 131345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47291 | /* 131347 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47292 | /* 131350 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47293 | /* 131352 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47294 | /* 131355 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47295 | /* 131361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47296 | /* 131367 */ GIR_RootConstrainSelectedInstOperands, |
| 47297 | /* 131368 */ // GIR_Coverage, 3541, |
| 47298 | /* 131368 */ GIR_EraseRootFromParent_Done, |
| 47299 | /* 131369 */ // Label 4031: @131369 |
| 47300 | /* 131369 */ GIM_Reject, |
| 47301 | /* 131370 */ // Label 4028: @131370 |
| 47302 | /* 131370 */ GIM_Reject, |
| 47303 | /* 131371 */ // Label 4024: @131371 |
| 47304 | /* 131371 */ GIM_Reject, |
| 47305 | /* 131372 */ // Label 92: @131372 |
| 47306 | /* 131372 */ GIM_Try, /*On fail goto*//*Label 4032*/ GIMT_Encode4(131637), |
| 47307 | /* 131377 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 47308 | /* 131380 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4036*/ GIMT_Encode4(131636), |
| 47309 | /* 131391 */ /*GILLT_v16s8*//*Label 4033*/ GIMT_Encode4(131411), GIMT_Encode4(0), |
| 47310 | /* 131399 */ /*GILLT_v8s16*//*Label 4034*/ GIMT_Encode4(131486), GIMT_Encode4(0), |
| 47311 | /* 131407 */ /*GILLT_v4s32*//*Label 4035*/ GIMT_Encode4(131561), |
| 47312 | /* 131411 */ // Label 4033: @131411 |
| 47313 | /* 131411 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4037*/ GIMT_Encode4(131485), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3536 // |
| 47314 | /* 131418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47315 | /* 131422 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47316 | /* 131426 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 47317 | /* 131426 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47318 | /* 131429 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 47319 | /* 131433 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47320 | /* 131438 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 47321 | /* 131441 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47322 | /* 131444 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47323 | /* 131450 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47324 | /* 131456 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47325 | /* 131458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8), |
| 47326 | /* 131461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47327 | /* 131463 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47328 | /* 131466 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47329 | /* 131468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47330 | /* 131471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47331 | /* 131477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47332 | /* 131483 */ GIR_RootConstrainSelectedInstOperands, |
| 47333 | /* 131484 */ // GIR_Coverage, 3536, |
| 47334 | /* 131484 */ GIR_EraseRootFromParent_Done, |
| 47335 | /* 131485 */ // Label 4037: @131485 |
| 47336 | /* 131485 */ GIM_Reject, |
| 47337 | /* 131486 */ // Label 4034: @131486 |
| 47338 | /* 131486 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4038*/ GIMT_Encode4(131560), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3537 // |
| 47339 | /* 131493 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47340 | /* 131497 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47341 | /* 131501 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVu16:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 47342 | /* 131501 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47343 | /* 131504 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 47344 | /* 131508 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47345 | /* 131513 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 47346 | /* 131516 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47347 | /* 131519 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47348 | /* 131525 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47349 | /* 131531 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47350 | /* 131533 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16), |
| 47351 | /* 131536 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47352 | /* 131538 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47353 | /* 131541 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47354 | /* 131543 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47355 | /* 131546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47356 | /* 131552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47357 | /* 131558 */ GIR_RootConstrainSelectedInstOperands, |
| 47358 | /* 131559 */ // GIR_Coverage, 3537, |
| 47359 | /* 131559 */ GIR_EraseRootFromParent_Done, |
| 47360 | /* 131560 */ // Label 4038: @131560 |
| 47361 | /* 131560 */ GIM_Reject, |
| 47362 | /* 131561 */ // Label 4035: @131561 |
| 47363 | /* 131561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4039*/ GIMT_Encode4(131635), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3538 // |
| 47364 | /* 131568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47365 | /* 131572 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47366 | /* 131576 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 47367 | /* 131576 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47368 | /* 131579 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 47369 | /* 131583 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47370 | /* 131588 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 47371 | /* 131591 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47372 | /* 131594 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47373 | /* 131600 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47374 | /* 131606 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47375 | /* 131608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32), |
| 47376 | /* 131611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47377 | /* 131613 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47378 | /* 131616 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47379 | /* 131618 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47380 | /* 131621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47381 | /* 131627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47382 | /* 131633 */ GIR_RootConstrainSelectedInstOperands, |
| 47383 | /* 131634 */ // GIR_Coverage, 3538, |
| 47384 | /* 131634 */ GIR_EraseRootFromParent_Done, |
| 47385 | /* 131635 */ // Label 4039: @131635 |
| 47386 | /* 131635 */ GIM_Reject, |
| 47387 | /* 131636 */ // Label 4036: @131636 |
| 47388 | /* 131636 */ GIM_Reject, |
| 47389 | /* 131637 */ // Label 4032: @131637 |
| 47390 | /* 131637 */ GIM_Reject, |
| 47391 | /* 131638 */ // Label 93: @131638 |
| 47392 | /* 131638 */ GIM_Try, /*On fail goto*//*Label 4040*/ GIMT_Encode4(131918), |
| 47393 | /* 131643 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 47394 | /* 131646 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4044*/ GIMT_Encode4(131917), |
| 47395 | /* 131657 */ /*GILLT_v16s8*//*Label 4041*/ GIMT_Encode4(131677), GIMT_Encode4(0), |
| 47396 | /* 131665 */ /*GILLT_v8s16*//*Label 4042*/ GIMT_Encode4(131759), GIMT_Encode4(0), |
| 47397 | /* 131673 */ /*GILLT_v4s32*//*Label 4043*/ GIMT_Encode4(131835), |
| 47398 | /* 131677 */ // Label 4041: @131677 |
| 47399 | /* 131677 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4045*/ GIMT_Encode4(131758), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3542 // |
| 47400 | /* 131684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47401 | /* 131688 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47402 | /* 131692 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 255:{ *:[i32] }), ?:{ *:[v16i8] }:$src) |
| 47403 | /* 131692 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47404 | /* 131695 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 47405 | /* 131699 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47406 | /* 131704 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(255), |
| 47407 | /* 131714 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47408 | /* 131717 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47409 | /* 131723 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47410 | /* 131729 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47411 | /* 131731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8), |
| 47412 | /* 131734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47413 | /* 131736 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47414 | /* 131739 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47415 | /* 131741 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47416 | /* 131744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47417 | /* 131750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47418 | /* 131756 */ GIR_RootConstrainSelectedInstOperands, |
| 47419 | /* 131757 */ // GIR_Coverage, 3542, |
| 47420 | /* 131757 */ GIR_EraseRootFromParent_Done, |
| 47421 | /* 131758 */ // Label 4045: @131758 |
| 47422 | /* 131758 */ GIM_Reject, |
| 47423 | /* 131759 */ // Label 4042: @131759 |
| 47424 | /* 131759 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4046*/ GIMT_Encode4(131834), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3543 // |
| 47425 | /* 131766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47426 | /* 131770 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47427 | /* 131774 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVu16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 65535:{ *:[i32] }), ?:{ *:[v8i16] }:$src) |
| 47428 | /* 131774 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47429 | /* 131777 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16), |
| 47430 | /* 131781 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47431 | /* 131786 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535), |
| 47432 | /* 131796 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47433 | /* 131799 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47434 | /* 131805 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47435 | /* 131807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16), |
| 47436 | /* 131810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47437 | /* 131812 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47438 | /* 131815 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47439 | /* 131817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47440 | /* 131820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47441 | /* 131826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47442 | /* 131832 */ GIR_RootConstrainSelectedInstOperands, |
| 47443 | /* 131833 */ // GIR_Coverage, 3543, |
| 47444 | /* 131833 */ GIR_EraseRootFromParent_Done, |
| 47445 | /* 131834 */ // Label 4046: @131834 |
| 47446 | /* 131834 */ GIM_Reject, |
| 47447 | /* 131835 */ // Label 4043: @131835 |
| 47448 | /* 131835 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4047*/ GIMT_Encode4(131916), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3544 // |
| 47449 | /* 131842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID), |
| 47450 | /* 131846 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID), |
| 47451 | /* 131850 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 4294967295:{ *:[i32] }), ?:{ *:[v4i32] }:$src) |
| 47452 | /* 131850 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47453 | /* 131853 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi), |
| 47454 | /* 131857 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)), |
| 47455 | /* 131862 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(4294967295), |
| 47456 | /* 131872 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14, |
| 47457 | /* 131875 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47458 | /* 131881 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47459 | /* 131887 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 47460 | /* 131889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32), |
| 47461 | /* 131892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest] |
| 47462 | /* 131894 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47463 | /* 131897 */ GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 47464 | /* 131899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47465 | /* 131902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47466 | /* 131908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 47467 | /* 131914 */ GIR_RootConstrainSelectedInstOperands, |
| 47468 | /* 131915 */ // GIR_Coverage, 3544, |
| 47469 | /* 131915 */ GIR_EraseRootFromParent_Done, |
| 47470 | /* 131916 */ // Label 4047: @131916 |
| 47471 | /* 131916 */ GIM_Reject, |
| 47472 | /* 131917 */ // Label 4044: @131917 |
| 47473 | /* 131917 */ GIM_Reject, |
| 47474 | /* 131918 */ // Label 4040: @131918 |
| 47475 | /* 131918 */ GIM_Reject, |
| 47476 | /* 131919 */ // Label 94: @131919 |
| 47477 | /* 131919 */ GIM_Reject, |
| 47478 | /* 131920 */ }; // Size: 131920 bytes |
| 47479 | return MatchTable0; |
| 47480 | } |
| 47481 | #undef GIMT_Encode2 |
| 47482 | #undef GIMT_Encode4 |
| 47483 | #undef GIMT_Encode8 |
| 47484 | |
| 47485 | |
| 47486 | #endif // GET_GLOBALISEL_IMPL |
| 47487 | |
| 47488 | #ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 47489 | |
| 47490 | PredicateBitset AvailableModuleFeatures; |
| 47491 | mutable PredicateBitset AvailableFunctionFeatures; |
| 47492 | PredicateBitset getAvailableFeatures() const { |
| 47493 | return AvailableModuleFeatures | AvailableFunctionFeatures; |
| 47494 | } |
| 47495 | PredicateBitset |
| 47496 | computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const; |
| 47497 | PredicateBitset |
| 47498 | computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, |
| 47499 | const MachineFunction *MF) const; |
| 47500 | void setupGeneratedPerFunctionState(MachineFunction &MF) override; |
| 47501 | |
| 47502 | #endif // GET_GLOBALISEL_PREDICATES_DECL |
| 47503 | |
| 47504 | #ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 47505 | |
| 47506 | AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), |
| 47507 | AvailableFunctionFeatures() |
| 47508 | |
| 47509 | #endif // GET_GLOBALISEL_PREDICATES_INIT |
| 47510 | |
| 47511 |
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