1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Global Instruction Selector for the ARM target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10
11const unsigned MAX_SUBTARGET_PREDICATES = 83;
12using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
13
14#endif // GET_GLOBALISEL_PREDICATE_BITSET
15
16#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
17
18 mutable MatcherState State;
19 typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
20 typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
21 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
22 static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
23 static ARMInstructionSelector::CustomRendererFn CustomRenderers[];
24 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
25 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
26 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
27 const uint8_t *getMatchTable() const override;
28 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
29 bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override;
30 bool testSimplePredicate(unsigned PredicateID) const override;
31 bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
32
33#endif // GET_GLOBALISEL_TEMPORARIES_DECL
34
35#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
36
37, State(0),
38ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
39
40#endif // GET_GLOBALISEL_TEMPORARIES_INIT
41
42#ifdef GET_GLOBALISEL_IMPL
43
44// LLT Objects.
45enum {
46 GILLT_s16,
47 GILLT_s32,
48 GILLT_s64,
49 GILLT_v2s1,
50 GILLT_v4s1,
51 GILLT_v8s1,
52 GILLT_v16s1,
53 GILLT_v8s8,
54 GILLT_v16s8,
55 GILLT_v4s16,
56 GILLT_v8s16,
57 GILLT_v2s32,
58 GILLT_v4s32,
59 GILLT_v2s64,
60 GILLT_v4s64,
61 GILLT_v8s64,
62};
63const static size_t NumTypeObjects = 16;
64const static LLT TypeObjects[] = {
65 LLT::scalar(16),
66 LLT::scalar(32),
67 LLT::scalar(64),
68 LLT::vector(ElementCount::getFixed(2), LLT::scalar(1)),
69 LLT::vector(ElementCount::getFixed(4), LLT::scalar(1)),
70 LLT::vector(ElementCount::getFixed(8), LLT::scalar(1)),
71 LLT::vector(ElementCount::getFixed(16), LLT::scalar(1)),
72 LLT::vector(ElementCount::getFixed(8), LLT::scalar(8)),
73 LLT::vector(ElementCount::getFixed(16), LLT::scalar(8)),
74 LLT::vector(ElementCount::getFixed(4), LLT::scalar(16)),
75 LLT::vector(ElementCount::getFixed(8), LLT::scalar(16)),
76 LLT::vector(ElementCount::getFixed(2), LLT::scalar(32)),
77 LLT::vector(ElementCount::getFixed(4), LLT::scalar(32)),
78 LLT::vector(ElementCount::getFixed(2), LLT::scalar(64)),
79 LLT::vector(ElementCount::getFixed(4), LLT::scalar(64)),
80 LLT::vector(ElementCount::getFixed(8), LLT::scalar(64)),
81};
82
83// Bits for subtarget features that participate in instruction matching.
84enum SubtargetFeatureBits : uint8_t {
85 Feature_NoHonorSignDependentRoundingBit = 73,
86 Feature_HasV4TBit = 4,
87 Feature_NoV4TBit = 5,
88 Feature_HasV5TBit = 11,
89 Feature_NoV5TBit = 63,
90 Feature_HasV5TEBit = 9,
91 Feature_HasV6Bit = 0,
92 Feature_NoV6Bit = 7,
93 Feature_HasV6MBit = 26,
94 Feature_HasV8MBaselineBit = 33,
95 Feature_HasV8_1MMainlineBit = 39,
96 Feature_HasMVEIntBit = 61,
97 Feature_HasMVEFloatBit = 62,
98 Feature_HasCDEBit = 82,
99 Feature_HasFPRegsBit = 40,
100 Feature_HasFPRegs16Bit = 41,
101 Feature_HasFPRegs64Bit = 74,
102 Feature_HasV6T2Bit = 6,
103 Feature_HasV6KBit = 16,
104 Feature_HasV7Bit = 3,
105 Feature_HasV8Bit = 53,
106 Feature_PreV8Bit = 17,
107 Feature_HasV8_1aBit = 76,
108 Feature_HasV8_3aBit = 77,
109 Feature_NoVFPBit = 20,
110 Feature_HasVFP2Bit = 19,
111 Feature_HasVFP3Bit = 50,
112 Feature_HasVFP4Bit = 48,
113 Feature_HasDPVFPBit = 42,
114 Feature_HasFPARMv8Bit = 45,
115 Feature_HasNEONBit = 51,
116 Feature_HasSHA2Bit = 60,
117 Feature_HasAESBit = 52,
118 Feature_HasDotProdBit = 54,
119 Feature_HasCRCBit = 12,
120 Feature_HasLOBBit = 38,
121 Feature_HasFP16Bit = 59,
122 Feature_HasFullFP16Bit = 44,
123 Feature_HasMatMulInt8Bit = 55,
124 Feature_HasDivideInThumbBit = 35,
125 Feature_HasDivideInARMBit = 10,
126 Feature_HasDSPBit = 34,
127 Feature_HasDBBit = 13,
128 Feature_HasV7ClrexBit = 15,
129 Feature_HasAcquireReleaseBit = 14,
130 Feature_HasMPBit = 2,
131 Feature_Has8MSecExtBit = 27,
132 Feature_HasZCZBit = 56,
133 Feature_UseNEONForFPBit = 80,
134 Feature_DontUseNEONForFPBit = 43,
135 Feature_IsThumbBit = 24,
136 Feature_IsThumb1OnlyBit = 25,
137 Feature_IsThumb2Bit = 32,
138 Feature_IsNotMClassBit = 36,
139 Feature_IsARMBit = 1,
140 Feature_IsWindowsBit = 28,
141 Feature_IsNotWindowsBit = 29,
142 Feature_IsReadTPTPIDRURWBit = 66,
143 Feature_IsReadTPTPIDRUROBit = 67,
144 Feature_IsReadTPTPIDRPRWBit = 68,
145 Feature_IsReadTPSoftBit = 18,
146 Feature_UseMovtBit = 37,
147 Feature_DontUseMovtBit = 21,
148 Feature_UseMovtInPicBit = 22,
149 Feature_DontUseMovtInPicBit = 23,
150 Feature_UseFPVMLxBit = 47,
151 Feature_SLSBLRMitigationBit = 65,
152 Feature_NoSLSBLRMitigationBit = 64,
153 Feature_UseMulOpsBit = 8,
154 Feature_UseFusedMACBit = 49,
155 Feature_HasFastVGETLNi32Bit = 57,
156 Feature_HasSlowVGETLNi32Bit = 78,
157 Feature_HasFastVDUP32Bit = 58,
158 Feature_HasSlowVDUP32Bit = 79,
159 Feature_UseVMOVSRBit = 46,
160 Feature_DontUseVMOVSRBit = 81,
161 Feature_IsLEBit = 72,
162 Feature_IsBEBit = 75,
163 Feature_GenExecuteOnlyBit = 31,
164 Feature_DontGenExecuteOnlyBit = 30,
165 Feature_GenT1ExecuteOnlyBit = 71,
166 Feature_SignRetAddrBit = 70,
167 Feature_NoSignRetAddrBit = 69,
168};
169
170PredicateBitset ARMInstructionSelector::
171computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const {
172 PredicateBitset Features{};
173 if (!TM.Options.HonorSignDependentRoundingFPMath())
174 Features.set(Feature_NoHonorSignDependentRoundingBit);
175 if (Subtarget->hasV4TOps())
176 Features.set(Feature_HasV4TBit);
177 if (!Subtarget->hasV4TOps())
178 Features.set(Feature_NoV4TBit);
179 if (Subtarget->hasV5TOps())
180 Features.set(Feature_HasV5TBit);
181 if (!Subtarget->hasV5TOps())
182 Features.set(Feature_NoV5TBit);
183 if (Subtarget->hasV5TEOps())
184 Features.set(Feature_HasV5TEBit);
185 if (Subtarget->hasV6Ops())
186 Features.set(Feature_HasV6Bit);
187 if (!Subtarget->hasV6Ops())
188 Features.set(Feature_NoV6Bit);
189 if (Subtarget->hasV6MOps())
190 Features.set(Feature_HasV6MBit);
191 if (Subtarget->hasV8MBaselineOps())
192 Features.set(Feature_HasV8MBaselineBit);
193 if (Subtarget->hasV8_1MMainlineOps())
194 Features.set(Feature_HasV8_1MMainlineBit);
195 if (Subtarget->hasMVEIntegerOps())
196 Features.set(Feature_HasMVEIntBit);
197 if (Subtarget->hasMVEFloatOps())
198 Features.set(Feature_HasMVEFloatBit);
199 if (Subtarget->hasCDEOps())
200 Features.set(Feature_HasCDEBit);
201 if (Subtarget->hasFPRegs())
202 Features.set(Feature_HasFPRegsBit);
203 if (Subtarget->hasFPRegs16())
204 Features.set(Feature_HasFPRegs16Bit);
205 if (Subtarget->hasFPRegs64())
206 Features.set(Feature_HasFPRegs64Bit);
207 if (Subtarget->hasV6T2Ops())
208 Features.set(Feature_HasV6T2Bit);
209 if (Subtarget->hasV6KOps())
210 Features.set(Feature_HasV6KBit);
211 if (Subtarget->hasV7Ops())
212 Features.set(Feature_HasV7Bit);
213 if (Subtarget->hasV8Ops())
214 Features.set(Feature_HasV8Bit);
215 if (!Subtarget->hasV8Ops())
216 Features.set(Feature_PreV8Bit);
217 if (Subtarget->hasV8_1aOps())
218 Features.set(Feature_HasV8_1aBit);
219 if (Subtarget->hasV8_3aOps())
220 Features.set(Feature_HasV8_3aBit);
221 if (!Subtarget->hasVFP2Base())
222 Features.set(Feature_NoVFPBit);
223 if (Subtarget->hasVFP2Base())
224 Features.set(Feature_HasVFP2Bit);
225 if (Subtarget->hasVFP3Base())
226 Features.set(Feature_HasVFP3Bit);
227 if (Subtarget->hasVFP4Base())
228 Features.set(Feature_HasVFP4Bit);
229 if (Subtarget->hasFP64())
230 Features.set(Feature_HasDPVFPBit);
231 if (Subtarget->hasFPARMv8Base())
232 Features.set(Feature_HasFPARMv8Bit);
233 if (Subtarget->hasNEON())
234 Features.set(Feature_HasNEONBit);
235 if (Subtarget->hasSHA2())
236 Features.set(Feature_HasSHA2Bit);
237 if (Subtarget->hasAES())
238 Features.set(Feature_HasAESBit);
239 if (Subtarget->hasDotProd())
240 Features.set(Feature_HasDotProdBit);
241 if (Subtarget->hasCRC())
242 Features.set(Feature_HasCRCBit);
243 if (Subtarget->hasLOB())
244 Features.set(Feature_HasLOBBit);
245 if (Subtarget->hasFP16())
246 Features.set(Feature_HasFP16Bit);
247 if (Subtarget->hasFullFP16())
248 Features.set(Feature_HasFullFP16Bit);
249 if (Subtarget->hasMatMulInt8())
250 Features.set(Feature_HasMatMulInt8Bit);
251 if (Subtarget->hasDivideInThumbMode())
252 Features.set(Feature_HasDivideInThumbBit);
253 if (Subtarget->hasDivideInARMMode())
254 Features.set(Feature_HasDivideInARMBit);
255 if (Subtarget->hasDSP())
256 Features.set(Feature_HasDSPBit);
257 if (Subtarget->hasDataBarrier())
258 Features.set(Feature_HasDBBit);
259 if (Subtarget->hasV7Clrex())
260 Features.set(Feature_HasV7ClrexBit);
261 if (Subtarget->hasAcquireRelease())
262 Features.set(Feature_HasAcquireReleaseBit);
263 if (Subtarget->hasMPExtension())
264 Features.set(Feature_HasMPBit);
265 if (Subtarget->has8MSecExt())
266 Features.set(Feature_Has8MSecExtBit);
267 if (Subtarget->hasZeroCycleZeroing())
268 Features.set(Feature_HasZCZBit);
269 if (Subtarget->useNEONForSinglePrecisionFP())
270 Features.set(Feature_UseNEONForFPBit);
271 if (!Subtarget->useNEONForSinglePrecisionFP())
272 Features.set(Feature_DontUseNEONForFPBit);
273 if (Subtarget->isThumb())
274 Features.set(Feature_IsThumbBit);
275 if (Subtarget->isThumb1Only())
276 Features.set(Feature_IsThumb1OnlyBit);
277 if (Subtarget->isThumb2())
278 Features.set(Feature_IsThumb2Bit);
279 if (!Subtarget->isMClass())
280 Features.set(Feature_IsNotMClassBit);
281 if (!Subtarget->isThumb())
282 Features.set(Feature_IsARMBit);
283 if (Subtarget->isTargetWindows())
284 Features.set(Feature_IsWindowsBit);
285 if (!Subtarget->isTargetWindows())
286 Features.set(Feature_IsNotWindowsBit);
287 if (Subtarget->isReadTPTPIDRURW())
288 Features.set(Feature_IsReadTPTPIDRURWBit);
289 if (Subtarget->isReadTPTPIDRURO())
290 Features.set(Feature_IsReadTPTPIDRUROBit);
291 if (Subtarget->isReadTPTPIDRPRW())
292 Features.set(Feature_IsReadTPTPIDRPRWBit);
293 if (Subtarget->isReadTPSoft())
294 Features.set(Feature_IsReadTPSoftBit);
295 if (Subtarget->useMulOps())
296 Features.set(Feature_UseMulOpsBit);
297 if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast && Subtarget->useFPVFMx())
298 Features.set(Feature_UseFusedMACBit);
299 if (!Subtarget->hasSlowVGETLNi32())
300 Features.set(Feature_HasFastVGETLNi32Bit);
301 if (Subtarget->hasSlowVGETLNi32())
302 Features.set(Feature_HasSlowVGETLNi32Bit);
303 if (!Subtarget->hasSlowVDUP32())
304 Features.set(Feature_HasFastVDUP32Bit);
305 if (Subtarget->hasSlowVDUP32())
306 Features.set(Feature_HasSlowVDUP32Bit);
307 if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())
308 Features.set(Feature_UseVMOVSRBit);
309 if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP())
310 Features.set(Feature_DontUseVMOVSRBit);
311 if (Subtarget->genExecuteOnly())
312 Features.set(Feature_GenExecuteOnlyBit);
313 if (!Subtarget->genExecuteOnly())
314 Features.set(Feature_DontGenExecuteOnlyBit);
315 if (Subtarget->genExecuteOnly() && Subtarget->isThumb1Only() && !Subtarget->hasV8MBaselineOps())
316 Features.set(Feature_GenT1ExecuteOnlyBit);
317 return Features;
318}
319
320void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
321 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget *)&MF.getSubtarget(), &MF);
322}
323PredicateBitset ARMInstructionSelector::
324computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const {
325 PredicateBitset Features{};
326 if (Subtarget->useMovt())
327 Features.set(Feature_UseMovtBit);
328 if (!Subtarget->useMovt())
329 Features.set(Feature_DontUseMovtBit);
330 if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt())
331 Features.set(Feature_UseMovtInPicBit);
332 if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt())
333 Features.set(Feature_DontUseMovtInPicBit);
334 if (((Subtarget->useFPVMLx() && TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||Subtarget->hasMinSize()))
335 Features.set(Feature_UseFPVMLxBit);
336 if ( MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
337 Features.set(Feature_SLSBLRMitigationBit);
338 if ( !MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
339 Features.set(Feature_NoSLSBLRMitigationBit);
340 if (MF->getDataLayout().isLittleEndian())
341 Features.set(Feature_IsLEBit);
342 if (MF->getDataLayout().isBigEndian())
343 Features.set(Feature_IsBEBit);
344 if ( MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) )
345 Features.set(Feature_SignRetAddrBit);
346 if ( !MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) )
347 Features.set(Feature_NoSignRetAddrBit);
348 return Features;
349}
350
351// Feature bitsets.
352enum {
353 GIFBS_Invalid,
354 GIFBS_HasDotProd,
355 GIFBS_HasFP16,
356 GIFBS_HasFPARMv8,
357 GIFBS_HasFPRegs,
358 GIFBS_HasFullFP16,
359 GIFBS_HasMVEFloat,
360 GIFBS_HasMVEInt,
361 GIFBS_HasMatMulInt8,
362 GIFBS_HasNEON,
363 GIFBS_HasVFP2,
364 GIFBS_HasVFP3,
365 GIFBS_HasVFP4,
366 GIFBS_IsARM,
367 GIFBS_IsThumb,
368 GIFBS_IsThumb2,
369 GIFBS_NoHonorSignDependentRounding,
370 GIFBS_DontUseNEONForFP_HasVFP2,
371 GIFBS_DontUseVMOVSR_HasNEON,
372 GIFBS_Has8MSecExt_IsThumb,
373 GIFBS_HasAES_HasV8,
374 GIFBS_HasCRC_IsARM,
375 GIFBS_HasCRC_IsThumb2,
376 GIFBS_HasDB_IsARM,
377 GIFBS_HasDB_IsThumb,
378 GIFBS_HasDPVFP_HasFPARMv8,
379 GIFBS_HasDPVFP_HasVFP2,
380 GIFBS_HasDPVFP_HasVFP3,
381 GIFBS_HasDPVFP_HasVFP4,
382 GIFBS_HasDPVFP_NoHonorSignDependentRounding,
383 GIFBS_HasDSP_IsThumb2,
384 GIFBS_HasDivideInARM_IsARM,
385 GIFBS_HasFP16_HasNEON,
386 GIFBS_HasFPARMv8_HasNEON,
387 GIFBS_HasFPRegs_HasFastVGETLNi32,
388 GIFBS_HasFPRegs_UseVMOVSR,
389 GIFBS_HasFullFP16_HasNEON,
390 GIFBS_HasMVEInt_HasV8_1MMainline,
391 GIFBS_HasMVEInt_IsBE,
392 GIFBS_HasMVEInt_IsLE,
393 GIFBS_HasNEON_HasV8,
394 GIFBS_HasNEON_HasV8_1a,
395 GIFBS_HasNEON_HasV8_3a,
396 GIFBS_HasNEON_HasVFP4,
397 GIFBS_HasNEON_IsBE,
398 GIFBS_HasNEON_IsLE,
399 GIFBS_HasNEON_UseNEONForFP,
400 GIFBS_HasSHA2_HasV8,
401 GIFBS_HasV5T_IsARM,
402 GIFBS_HasV5T_IsThumb,
403 GIFBS_HasV5TE_IsARM,
404 GIFBS_HasV6_IsARM,
405 GIFBS_HasV6K_IsARM,
406 GIFBS_HasV6M_IsThumb,
407 GIFBS_HasV6T2_IsARM,
408 GIFBS_HasV7_IsARM,
409 GIFBS_HasV7Clrex_IsThumb,
410 GIFBS_HasV8MBaseline_IsThumb,
411 GIFBS_IsARM_NoV5T,
412 GIFBS_IsARM_NoV6,
413 GIFBS_IsARM_PreV8,
414 GIFBS_IsThumb_IsThumb1Only,
415 GIFBS_IsThumb_IsWindows,
416 GIFBS_IsThumb_NoV5T,
417 GIFBS_IsThumb_UseMovt,
418 GIFBS_IsThumb2_PreV8,
419 GIFBS_IsThumb2_UseMulOps,
420 GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only,
421 GIFBS_HasDSP_IsThumb2_UseMulOps,
422 GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
423 GIFBS_HasFPARMv8_HasFullFP16_HasNEON,
424 GIFBS_HasFullFP16_HasNEON_HasV8,
425 GIFBS_HasFullFP16_HasNEON_HasV8_3a,
426 GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
427 GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
428 GIFBS_HasLOB_HasV8_1MMainline_IsThumb2,
429 GIFBS_HasNEON_UseFPVMLx_UseNEONForFP,
430 GIFBS_HasV5TE_IsARM_UseMulOps,
431 GIFBS_HasV6_IsARM_UseMulOps,
432 GIFBS_HasV6_IsThumb_IsThumb1Only,
433 GIFBS_HasV6T2_IsARM_UseMulOps,
434 GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP,
435 GIFBS_IsARM_NoV6_UseMulOps,
436};
437constexpr static PredicateBitset FeatureBitsets[] {
438 {}, // GIFBS_Invalid
439 {Feature_HasDotProdBit, },
440 {Feature_HasFP16Bit, },
441 {Feature_HasFPARMv8Bit, },
442 {Feature_HasFPRegsBit, },
443 {Feature_HasFullFP16Bit, },
444 {Feature_HasMVEFloatBit, },
445 {Feature_HasMVEIntBit, },
446 {Feature_HasMatMulInt8Bit, },
447 {Feature_HasNEONBit, },
448 {Feature_HasVFP2Bit, },
449 {Feature_HasVFP3Bit, },
450 {Feature_HasVFP4Bit, },
451 {Feature_IsARMBit, },
452 {Feature_IsThumbBit, },
453 {Feature_IsThumb2Bit, },
454 {Feature_NoHonorSignDependentRoundingBit, },
455 {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, },
456 {Feature_DontUseVMOVSRBit, Feature_HasNEONBit, },
457 {Feature_Has8MSecExtBit, Feature_IsThumbBit, },
458 {Feature_HasAESBit, Feature_HasV8Bit, },
459 {Feature_HasCRCBit, Feature_IsARMBit, },
460 {Feature_HasCRCBit, Feature_IsThumb2Bit, },
461 {Feature_HasDBBit, Feature_IsARMBit, },
462 {Feature_HasDBBit, Feature_IsThumbBit, },
463 {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, },
464 {Feature_HasDPVFPBit, Feature_HasVFP2Bit, },
465 {Feature_HasDPVFPBit, Feature_HasVFP3Bit, },
466 {Feature_HasDPVFPBit, Feature_HasVFP4Bit, },
467 {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, },
468 {Feature_HasDSPBit, Feature_IsThumb2Bit, },
469 {Feature_HasDivideInARMBit, Feature_IsARMBit, },
470 {Feature_HasFP16Bit, Feature_HasNEONBit, },
471 {Feature_HasFPARMv8Bit, Feature_HasNEONBit, },
472 {Feature_HasFPRegsBit, Feature_HasFastVGETLNi32Bit, },
473 {Feature_HasFPRegsBit, Feature_UseVMOVSRBit, },
474 {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
475 {Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, },
476 {Feature_HasMVEIntBit, Feature_IsBEBit, },
477 {Feature_HasMVEIntBit, Feature_IsLEBit, },
478 {Feature_HasNEONBit, Feature_HasV8Bit, },
479 {Feature_HasNEONBit, Feature_HasV8_1aBit, },
480 {Feature_HasNEONBit, Feature_HasV8_3aBit, },
481 {Feature_HasNEONBit, Feature_HasVFP4Bit, },
482 {Feature_HasNEONBit, Feature_IsBEBit, },
483 {Feature_HasNEONBit, Feature_IsLEBit, },
484 {Feature_HasNEONBit, Feature_UseNEONForFPBit, },
485 {Feature_HasSHA2Bit, Feature_HasV8Bit, },
486 {Feature_HasV5TBit, Feature_IsARMBit, },
487 {Feature_HasV5TBit, Feature_IsThumbBit, },
488 {Feature_HasV5TEBit, Feature_IsARMBit, },
489 {Feature_HasV6Bit, Feature_IsARMBit, },
490 {Feature_HasV6KBit, Feature_IsARMBit, },
491 {Feature_HasV6MBit, Feature_IsThumbBit, },
492 {Feature_HasV6T2Bit, Feature_IsARMBit, },
493 {Feature_HasV7Bit, Feature_IsARMBit, },
494 {Feature_HasV7ClrexBit, Feature_IsThumbBit, },
495 {Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
496 {Feature_IsARMBit, Feature_NoV5TBit, },
497 {Feature_IsARMBit, Feature_NoV6Bit, },
498 {Feature_IsARMBit, Feature_PreV8Bit, },
499 {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
500 {Feature_IsThumbBit, Feature_IsWindowsBit, },
501 {Feature_IsThumbBit, Feature_NoV5TBit, },
502 {Feature_IsThumbBit, Feature_UseMovtBit, },
503 {Feature_IsThumb2Bit, Feature_PreV8Bit, },
504 {Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
505 {Feature_DontUseMovtBit, Feature_GenExecuteOnlyBit, Feature_IsThumb1OnlyBit, },
506 {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
507 {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
508 {Feature_HasFPARMv8Bit, Feature_HasFullFP16Bit, Feature_HasNEONBit, },
509 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, },
510 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, },
511 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, },
512 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, },
513 {Feature_HasLOBBit, Feature_HasV8_1MMainlineBit, Feature_IsThumb2Bit, },
514 {Feature_HasNEONBit, Feature_UseFPVMLxBit, Feature_UseNEONForFPBit, },
515 {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, },
516 {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
517 {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
518 {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
519 {Feature_HasVFP4Bit, Feature_UseFusedMACBit, Feature_UseNEONForFPBit, },
520 {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, },
521};
522
523// ComplexPattern predicates.
524enum {
525 GICP_Invalid,
526};
527// See constructor for table contents
528
529ARMInstructionSelector::ComplexMatcherMemFn
530ARMInstructionSelector::ComplexPredicateFns[] = {
531 nullptr, // GICP_Invalid
532};
533
534// PatFrag predicates.
535enum {
536 GICXXPred_MI_Predicate_bf_inv_mask_imm = GICXXPred_Invalid + 1,
537 GICXXPred_MI_Predicate_ffloor_nnan,
538 GICXXPred_MI_Predicate_or_disjoint,
539 GICXXPred_MI_Predicate_vfp_f32imm,
540 GICXXPred_MI_Predicate_vfp_f64imm,
541};
542bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
543 const MachineFunction &MF = *MI.getParent()->getParent();
544 const MachineRegisterInfo &MRI = MF.getRegInfo();
545 const auto &Operands = State.RecordedOperands;
546 (void)Operands;
547 (void)MRI;
548 switch (PredicateID) {
549 case GICXXPred_MI_Predicate_bf_inv_mask_imm: {
550
551 // There's better methods of implementing this check. IntImmLeaf<> would be
552 // equivalent and have less boilerplate but we need a test for C++
553 // predicates and this one causes new rules to be imported into GlobalISel
554 // without requiring additional features first.
555 const auto &MO = MI.getOperand(1);
556 if (!MO.isCImm())
557 return false;
558 return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue());
559
560 llvm_unreachable("bf_inv_mask_imm should have returned");
561 }
562 case GICXXPred_MI_Predicate_ffloor_nnan: {
563
564 return MI.getFlag(MachineInstr::FmNoNans);
565
566 }
567 case GICXXPred_MI_Predicate_or_disjoint: {
568
569 return MI.getFlag(MachineInstr::Disjoint);
570
571 }
572 case GICXXPred_MI_Predicate_vfp_f32imm: {
573
574 const auto &MO = MI.getOperand(1);
575 if (!MO.isFPImm())
576 return false;
577 return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1;
578
579 llvm_unreachable("vfp_f32imm should have returned");
580 }
581 case GICXXPred_MI_Predicate_vfp_f64imm: {
582
583 const auto &MO = MI.getOperand(1);
584 if (!MO.isFPImm())
585 return false;
586 return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1;
587
588 llvm_unreachable("vfp_f64imm should have returned");
589 }
590 }
591 llvm_unreachable("Unknown predicate");
592 return false;
593}
594// PatFrag predicates.
595bool ARMInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
596 const auto &Operands = State.RecordedOperands;
597 Register Reg = MO.getReg();
598 (void)Operands;
599 (void)Reg;
600 llvm_unreachable("Unknown predicate");
601 return false;
602}
603// PatFrag predicates.
604enum {
605 GICXXPred_I64_Predicate_FPNoSaturation = GICXXPred_Invalid + 1,
606 GICXXPred_I64_Predicate_Float8E4M3FN,
607 GICXXPred_I64_Predicate_Float8E5M2,
608 GICXXPred_I64_Predicate_NearestTiesToEven,
609 GICXXPred_I64_Predicate_VectorIndex8,
610 GICXXPred_I64_Predicate_VectorIndex16,
611 GICXXPred_I64_Predicate_VectorIndex32,
612 GICXXPred_I64_Predicate_VectorIndex32_Hi,
613 GICXXPred_I64_Predicate_VectorIndex64,
614 GICXXPred_I64_Predicate_asr_imm,
615 GICXXPred_I64_Predicate_imm0_7,
616 GICXXPred_I64_Predicate_imm0_15,
617 GICXXPred_I64_Predicate_imm0_31,
618 GICXXPred_I64_Predicate_imm0_32,
619 GICXXPred_I64_Predicate_imm0_63,
620 GICXXPred_I64_Predicate_imm0_239,
621 GICXXPred_I64_Predicate_imm0_255,
622 GICXXPred_I64_Predicate_imm0_255_expr,
623 GICXXPred_I64_Predicate_imm0_4095,
624 GICXXPred_I64_Predicate_imm0_65535,
625 GICXXPred_I64_Predicate_imm0_65535_expr,
626 GICXXPred_I64_Predicate_imm0_65535_neg,
627 GICXXPred_I64_Predicate_imm1_7,
628 GICXXPred_I64_Predicate_imm1_15,
629 GICXXPred_I64_Predicate_imm1_16,
630 GICXXPred_I64_Predicate_imm1_31,
631 GICXXPred_I64_Predicate_imm8,
632 GICXXPred_I64_Predicate_imm8_255,
633 GICXXPred_I64_Predicate_imm8_or_16,
634 GICXXPred_I64_Predicate_imm16,
635 GICXXPred_I64_Predicate_imm16_31,
636 GICXXPred_I64_Predicate_imm24b,
637 GICXXPred_I64_Predicate_imm32,
638 GICXXPred_I64_Predicate_imm256_510,
639 GICXXPred_I64_Predicate_imm_3b,
640 GICXXPred_I64_Predicate_imm_4b,
641 GICXXPred_I64_Predicate_imm_6b,
642 GICXXPred_I64_Predicate_imm_7b,
643 GICXXPred_I64_Predicate_imm_9b,
644 GICXXPred_I64_Predicate_imm_11b,
645 GICXXPred_I64_Predicate_imm_12b,
646 GICXXPred_I64_Predicate_imm_13b,
647 GICXXPred_I64_Predicate_imm_even,
648 GICXXPred_I64_Predicate_imm_odd,
649 GICXXPred_I64_Predicate_imm_sr,
650 GICXXPred_I64_Predicate_long_shift,
651 GICXXPred_I64_Predicate_mod_imm,
652 GICXXPred_I64_Predicate_mod_imm_not,
653 GICXXPred_I64_Predicate_pkh_asr_amt,
654 GICXXPred_I64_Predicate_pkh_lsl_amt,
655 GICXXPred_I64_Predicate_shr_imm8,
656 GICXXPred_I64_Predicate_shr_imm16,
657 GICXXPred_I64_Predicate_shr_imm32,
658 GICXXPred_I64_Predicate_shr_imm64,
659 GICXXPred_I64_Predicate_t2_so_imm,
660 GICXXPred_I64_Predicate_t2_so_imm_neg,
661};
662bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
663 switch (PredicateID) {
664 case GICXXPred_I64_Predicate_FPNoSaturation: {
665 return Imm == 0;
666 }
667 case GICXXPred_I64_Predicate_Float8E4M3FN: {
668 return Imm == APFloatBase::S_Float8E4M3FN;
669 }
670 case GICXXPred_I64_Predicate_Float8E5M2: {
671 return Imm == APFloatBase::S_Float8E5M2;
672 }
673 case GICXXPred_I64_Predicate_NearestTiesToEven: {
674 return Imm == static_cast<int>(RoundingMode::NearestTiesToEven);
675 }
676 case GICXXPred_I64_Predicate_VectorIndex8: {
677
678 return ((uint64_t)Imm) < 8;
679
680 }
681 case GICXXPred_I64_Predicate_VectorIndex16: {
682
683 return ((uint64_t)Imm) < 4;
684
685 }
686 case GICXXPred_I64_Predicate_VectorIndex32: {
687
688 return ((uint64_t)Imm) < 2;
689
690 }
691 case GICXXPred_I64_Predicate_VectorIndex32_Hi: {
692
693 return ((uint64_t)Imm) >= 2 && ((uint64_t)Imm) < 4;
694
695 }
696 case GICXXPred_I64_Predicate_VectorIndex64: {
697
698 return ((uint64_t)Imm) < 1;
699
700 }
701 case GICXXPred_I64_Predicate_asr_imm: {
702 return Imm > 0 && Imm <= 32;
703 }
704 case GICXXPred_I64_Predicate_imm0_7: {
705
706 return Imm >= 0 && Imm < 8;
707
708 }
709 case GICXXPred_I64_Predicate_imm0_15: {
710
711 return Imm >= 0 && Imm < 16;
712
713 }
714 case GICXXPred_I64_Predicate_imm0_31: {
715
716 return Imm >= 0 && Imm < 32;
717
718 }
719 case GICXXPred_I64_Predicate_imm0_32: {
720
721 return Imm >= 0 && Imm < 33;
722
723 }
724 case GICXXPred_I64_Predicate_imm0_63: {
725
726 return Imm >= 0 && Imm < 64;
727
728 }
729 case GICXXPred_I64_Predicate_imm0_239: {
730 return Imm >= 0 && Imm < 240;
731 }
732 case GICXXPred_I64_Predicate_imm0_255: {
733 return Imm >= 0 && Imm < 256;
734 }
735 case GICXXPred_I64_Predicate_imm0_255_expr: {
736 return Imm >= 0 && Imm < 256;
737 }
738 case GICXXPred_I64_Predicate_imm0_4095: {
739
740 return Imm >= 0 && Imm < 4096;
741
742 }
743 case GICXXPred_I64_Predicate_imm0_65535: {
744
745 return Imm >= 0 && Imm < 65536;
746
747 }
748 case GICXXPred_I64_Predicate_imm0_65535_expr: {
749
750 return Imm >= 0 && Imm < 65536;
751
752 }
753 case GICXXPred_I64_Predicate_imm0_65535_neg: {
754
755 return -Imm >= 0 && -Imm < 65536;
756
757 }
758 case GICXXPred_I64_Predicate_imm1_7: {
759 return Imm > 0 && Imm < 8;
760 }
761 case GICXXPred_I64_Predicate_imm1_15: {
762 return Imm > 0 && Imm < 16;
763 }
764 case GICXXPred_I64_Predicate_imm1_16: {
765
766 return Imm > 0 && Imm <= 16;
767
768 }
769 case GICXXPred_I64_Predicate_imm1_31: {
770 return Imm > 0 && Imm < 32;
771 }
772 case GICXXPred_I64_Predicate_imm8: {
773 return Imm == 8;
774 }
775 case GICXXPred_I64_Predicate_imm8_255: {
776
777 return Imm >= 8 && Imm < 256;
778
779 }
780 case GICXXPred_I64_Predicate_imm8_or_16: {
781 return Imm == 8 || Imm == 16;
782 }
783 case GICXXPred_I64_Predicate_imm16: {
784 return Imm == 16;
785 }
786 case GICXXPred_I64_Predicate_imm16_31: {
787
788 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
789
790 }
791 case GICXXPred_I64_Predicate_imm24b: {
792
793 return Imm >= 0 && Imm <= 0xffffff;
794
795 }
796 case GICXXPred_I64_Predicate_imm32: {
797 return Imm == 32;
798 }
799 case GICXXPred_I64_Predicate_imm256_510: {
800
801 return Imm >= 256 && Imm < 511;
802
803 }
804 case GICXXPred_I64_Predicate_imm_3b: {
805 { return Imm >= 0 && Imm < (1 << 3); }
806 llvm_unreachable("imm_3b should have returned");
807 }
808 case GICXXPred_I64_Predicate_imm_4b: {
809 { return Imm >= 0 && Imm < (1 << 4); }
810 llvm_unreachable("imm_4b should have returned");
811 }
812 case GICXXPred_I64_Predicate_imm_6b: {
813 { return Imm >= 0 && Imm < (1 << 6); }
814 llvm_unreachable("imm_6b should have returned");
815 }
816 case GICXXPred_I64_Predicate_imm_7b: {
817 { return Imm >= 0 && Imm < (1 << 7); }
818 llvm_unreachable("imm_7b should have returned");
819 }
820 case GICXXPred_I64_Predicate_imm_9b: {
821 { return Imm >= 0 && Imm < (1 << 9); }
822 llvm_unreachable("imm_9b should have returned");
823 }
824 case GICXXPred_I64_Predicate_imm_11b: {
825 { return Imm >= 0 && Imm < (1 << 11); }
826 llvm_unreachable("imm_11b should have returned");
827 }
828 case GICXXPred_I64_Predicate_imm_12b: {
829 { return Imm >= 0 && Imm < (1 << 12); }
830 llvm_unreachable("imm_12b should have returned");
831 }
832 case GICXXPred_I64_Predicate_imm_13b: {
833 { return Imm >= 0 && Imm < (1 << 13); }
834 llvm_unreachable("imm_13b should have returned");
835 }
836 case GICXXPred_I64_Predicate_imm_even: {
837 return (Imm & 1) == 0;
838 }
839 case GICXXPred_I64_Predicate_imm_odd: {
840 return (Imm & 1) == 1;
841 }
842 case GICXXPred_I64_Predicate_imm_sr: {
843
844 return Imm > 0 && Imm <= 32;
845
846 }
847 case GICXXPred_I64_Predicate_long_shift: {
848 return Imm > 0 && Imm <= 32;
849 }
850 case GICXXPred_I64_Predicate_mod_imm: {
851
852 return ARM_AM::getSOImmVal(Imm) != -1;
853
854 }
855 case GICXXPred_I64_Predicate_mod_imm_not: {
856
857 return ARM_AM::getSOImmVal(~(uint32_t)Imm) != -1;
858
859 }
860 case GICXXPred_I64_Predicate_pkh_asr_amt: {
861 return Imm > 0 && Imm <= 32;
862 }
863 case GICXXPred_I64_Predicate_pkh_lsl_amt: {
864 return Imm >= 0 && Imm < 32;
865 }
866 case GICXXPred_I64_Predicate_shr_imm8: {
867 return Imm > 0 && Imm <= 8;
868 }
869 case GICXXPred_I64_Predicate_shr_imm16: {
870 return Imm > 0 && Imm <= 16;
871 }
872 case GICXXPred_I64_Predicate_shr_imm32: {
873 return Imm > 0 && Imm <= 32;
874 }
875 case GICXXPred_I64_Predicate_shr_imm64: {
876 return Imm > 0 && Imm <= 64;
877 }
878 case GICXXPred_I64_Predicate_t2_so_imm: {
879
880 return ARM_AM::getT2SOImmVal(Imm) != -1;
881
882 }
883 case GICXXPred_I64_Predicate_t2_so_imm_neg: {
884
885 return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
886
887 }
888 }
889 llvm_unreachable("Unknown predicate");
890 return false;
891}
892// PatFrag predicates.
893bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
894 llvm_unreachable("Unknown predicate");
895 return false;
896}
897// PatFrag predicates.
898enum {
899 GICXXPred_APInt_Predicate_arm_i32imm = GICXXPred_Invalid + 1,
900};
901bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
902 switch (PredicateID) {
903 case GICXXPred_APInt_Predicate_arm_i32imm: {
904
905 if (Subtarget->useMovt())
906 return true;
907 if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue()))
908 return true;
909 return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue());
910
911 llvm_unreachable("arm_i32imm should have returned");
912 }
913 }
914 llvm_unreachable("Unknown predicate");
915 return false;
916}
917bool ARMInstructionSelector::testSimplePredicate(unsigned) const {
918 llvm_unreachable("ARMInstructionSelector does not support simple predicates!");
919 return false;
920}
921// Custom renderers.
922enum {
923 GICR_Invalid,
924 GICR_renderFrameIndex,
925 GICR_renderInvertedImm,
926 GICR_renderVFPF32Imm,
927 GICR_renderVFPF64Imm,
928};
929ARMInstructionSelector::CustomRendererFn
930ARMInstructionSelector::CustomRenderers[] = {
931 nullptr, // GICR_Invalid
932 &ARMInstructionSelector::renderFrameIndex,
933 &ARMInstructionSelector::renderInvertedImm,
934 &ARMInstructionSelector::renderVFPF32Imm,
935 &ARMInstructionSelector::renderVFPF64Imm,
936};
937
938bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
939 const PredicateBitset AvailableFeatures = getAvailableFeatures();
940 MachineIRBuilder B(I);
941 State.MIs.clear();
942 State.MIs.push_back(&I);
943
944 if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
945 return true;
946 }
947
948 return false;
949}
950
951bool ARMInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
952 llvm_unreachable("ARMInstructionSelector does not support custom C++ actions!");
953}
954#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
955#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((Val) >> 8)
956#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24)
957#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24), uint8_t(uint64_t(Val) >> 32), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 56)
958#else
959#define GIMT_Encode2(Val) uint8_t((Val) >> 8), uint8_t(Val)
960#define GIMT_Encode4(Val) uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
961#define GIMT_Encode8(Val) uint8_t(uint64_t(Val) >> 56), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 32), uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
962#endif
963const uint8_t *ARMInstructionSelector::getMatchTable() const {
964 constexpr static uint8_t MatchTable0[] = {
965 /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(55), GIMT_Encode2(331), /*)*//*default:*//*Label 94*/ GIMT_Encode4(131927),
966 /* 10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(1114),
967 /* 14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(12542),
968 /* 18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(15640),
969 /* 22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(17303),
970 /* 26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(17397), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
971 /* 46 */ /*TargetOpcode::G_AND*//*Label 5*/ GIMT_Encode4(17491),
972 /* 50 */ /*TargetOpcode::G_OR*//*Label 6*/ GIMT_Encode4(20591),
973 /* 54 */ /*TargetOpcode::G_XOR*//*Label 7*/ GIMT_Encode4(26317),
974 /* 58 */ /*TargetOpcode::G_ABDS*//*Label 8*/ GIMT_Encode4(27976),
975 /* 62 */ /*TargetOpcode::G_ABDU*//*Label 9*/ GIMT_Encode4(28486),
976 /* 66 */ /*TargetOpcode::G_UAVGFLOOR*//*Label 10*/ GIMT_Encode4(28996),
977 /* 70 */ /*TargetOpcode::G_UAVGCEIL*//*Label 11*/ GIMT_Encode4(29223),
978 /* 74 */ /*TargetOpcode::G_SAVGFLOOR*//*Label 12*/ GIMT_Encode4(29450),
979 /* 78 */ /*TargetOpcode::G_SAVGCEIL*//*Label 13*/ GIMT_Encode4(29677), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
980 /* 130 */ /*TargetOpcode::G_CONCAT_VECTORS*//*Label 14*/ GIMT_Encode4(29904), GIMT_Encode4(0), GIMT_Encode4(0),
981 /* 142 */ /*TargetOpcode::G_BITCAST*//*Label 15*/ GIMT_Encode4(30571), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
982 /* 158 */ /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 16*/ GIMT_Encode4(37758),
983 /* 162 */ /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 17*/ GIMT_Encode4(38157), GIMT_Encode4(0), GIMT_Encode4(0),
984 /* 174 */ /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 18*/ GIMT_Encode4(38523), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
985 /* 190 */ /*TargetOpcode::G_SEXTLOAD*//*Label 19*/ GIMT_Encode4(38889), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
986 /* 326 */ /*TargetOpcode::G_FENCE*//*Label 20*/ GIMT_Encode4(39050), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
987 /* 346 */ /*TargetOpcode::G_INTRINSIC*//*Label 21*/ GIMT_Encode4(39071),
988 /* 350 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 22*/ GIMT_Encode4(90367), GIMT_Encode4(0), GIMT_Encode4(0),
989 /* 362 */ /*TargetOpcode::G_ANYEXT*//*Label 23*/ GIMT_Encode4(96147),
990 /* 366 */ /*TargetOpcode::G_TRUNC*//*Label 24*/ GIMT_Encode4(96286), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
991 /* 382 */ /*TargetOpcode::G_CONSTANT*//*Label 25*/ GIMT_Encode4(96429),
992 /* 386 */ /*TargetOpcode::G_FCONSTANT*//*Label 26*/ GIMT_Encode4(96741), GIMT_Encode4(0), GIMT_Encode4(0),
993 /* 398 */ /*TargetOpcode::G_SEXT*//*Label 27*/ GIMT_Encode4(96835),
994 /* 402 */ /*TargetOpcode::G_SEXT_INREG*//*Label 28*/ GIMT_Encode4(96974),
995 /* 406 */ /*TargetOpcode::G_ZEXT*//*Label 29*/ GIMT_Encode4(97564),
996 /* 410 */ /*TargetOpcode::G_SHL*//*Label 30*/ GIMT_Encode4(98252),
997 /* 414 */ /*TargetOpcode::G_LSHR*//*Label 31*/ GIMT_Encode4(98464),
998 /* 418 */ /*TargetOpcode::G_ASHR*//*Label 32*/ GIMT_Encode4(98570), GIMT_Encode4(0), GIMT_Encode4(0),
999 /* 430 */ /*TargetOpcode::G_ROTR*//*Label 33*/ GIMT_Encode4(98838), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1000 /* 498 */ /*TargetOpcode::G_UMULH*//*Label 34*/ GIMT_Encode4(99164),
1001 /* 502 */ /*TargetOpcode::G_SMULH*//*Label 35*/ GIMT_Encode4(99397),
1002 /* 506 */ /*TargetOpcode::G_UADDSAT*//*Label 36*/ GIMT_Encode4(99749),
1003 /* 510 */ /*TargetOpcode::G_SADDSAT*//*Label 37*/ GIMT_Encode4(100375),
1004 /* 514 */ /*TargetOpcode::G_USUBSAT*//*Label 38*/ GIMT_Encode4(101648),
1005 /* 518 */ /*TargetOpcode::G_SSUBSAT*//*Label 39*/ GIMT_Encode4(102274), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1006 /* 562 */ /*TargetOpcode::G_FADD*//*Label 40*/ GIMT_Encode4(103267),
1007 /* 566 */ /*TargetOpcode::G_FSUB*//*Label 41*/ GIMT_Encode4(105602),
1008 /* 570 */ /*TargetOpcode::G_FMUL*//*Label 42*/ GIMT_Encode4(107255),
1009 /* 574 */ /*TargetOpcode::G_FMA*//*Label 43*/ GIMT_Encode4(108224), GIMT_Encode4(0),
1010 /* 582 */ /*TargetOpcode::G_FDIV*//*Label 44*/ GIMT_Encode4(110287), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1011 /* 634 */ /*TargetOpcode::G_FNEG*//*Label 45*/ GIMT_Encode4(110449),
1012 /* 638 */ /*TargetOpcode::G_FPEXT*//*Label 46*/ GIMT_Encode4(112857),
1013 /* 642 */ /*TargetOpcode::G_FPTRUNC*//*Label 47*/ GIMT_Encode4(113121),
1014 /* 646 */ /*TargetOpcode::G_FPTOSI*//*Label 48*/ GIMT_Encode4(113413),
1015 /* 650 */ /*TargetOpcode::G_FPTOUI*//*Label 49*/ GIMT_Encode4(114695),
1016 /* 654 */ /*TargetOpcode::G_SITOFP*//*Label 50*/ GIMT_Encode4(115977),
1017 /* 658 */ /*TargetOpcode::G_UITOFP*//*Label 51*/ GIMT_Encode4(116619),
1018 /* 662 */ /*TargetOpcode::G_FPTOSI_SAT*//*Label 52*/ GIMT_Encode4(117261),
1019 /* 666 */ /*TargetOpcode::G_FPTOUI_SAT*//*Label 53*/ GIMT_Encode4(117624),
1020 /* 670 */ /*TargetOpcode::G_FABS*//*Label 54*/ GIMT_Encode4(117987), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1021 /* 686 */ /*TargetOpcode::G_FMINNUM*//*Label 55*/ GIMT_Encode4(118751),
1022 /* 690 */ /*TargetOpcode::G_FMAXNUM*//*Label 56*/ GIMT_Encode4(119332), GIMT_Encode4(0), GIMT_Encode4(0),
1023 /* 702 */ /*TargetOpcode::G_FMINIMUM*//*Label 57*/ GIMT_Encode4(119913),
1024 /* 706 */ /*TargetOpcode::G_FMAXIMUM*//*Label 58*/ GIMT_Encode4(120641), GIMT_Encode4(0), GIMT_Encode4(0),
1025 /* 718 */ /*TargetOpcode::G_GET_FPENV*//*Label 59*/ GIMT_Encode4(121369),
1026 /* 722 */ /*TargetOpcode::G_SET_FPENV*//*Label 60*/ GIMT_Encode4(121402),
1027 /* 726 */ /*TargetOpcode::G_RESET_FPENV*//*Label 61*/ GIMT_Encode4(121438),
1028 /* 730 */ /*TargetOpcode::G_GET_FPMODE*//*Label 62*/ GIMT_Encode4(121565), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1029 /* 758 */ /*TargetOpcode::G_SMIN*//*Label 63*/ GIMT_Encode4(121598),
1030 /* 762 */ /*TargetOpcode::G_SMAX*//*Label 64*/ GIMT_Encode4(122108),
1031 /* 766 */ /*TargetOpcode::G_UMIN*//*Label 65*/ GIMT_Encode4(122618),
1032 /* 770 */ /*TargetOpcode::G_UMAX*//*Label 66*/ GIMT_Encode4(123506),
1033 /* 774 */ /*TargetOpcode::G_ABS*//*Label 67*/ GIMT_Encode4(124394), GIMT_Encode4(0), GIMT_Encode4(0),
1034 /* 786 */ /*TargetOpcode::G_BR*//*Label 68*/ GIMT_Encode4(124832), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1035 /* 806 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 69*/ GIMT_Encode4(124902),
1036 /* 810 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 70*/ GIMT_Encode4(125178), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1037 /* 838 */ /*TargetOpcode::G_CTLZ*//*Label 71*/ GIMT_Encode4(125234), GIMT_Encode4(0),
1038 /* 846 */ /*TargetOpcode::G_CTLS*//*Label 72*/ GIMT_Encode4(125772),
1039 /* 850 */ /*TargetOpcode::G_CTPOP*//*Label 73*/ GIMT_Encode4(126210),
1040 /* 854 */ /*TargetOpcode::G_BSWAP*//*Label 74*/ GIMT_Encode4(126304),
1041 /* 858 */ /*TargetOpcode::G_BITREVERSE*//*Label 75*/ GIMT_Encode4(126589), GIMT_Encode4(0),
1042 /* 866 */ /*TargetOpcode::G_FCEIL*//*Label 76*/ GIMT_Encode4(127004), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1043 /* 914 */ /*TargetOpcode::G_FSQRT*//*Label 77*/ GIMT_Encode4(127370),
1044 /* 918 */ /*TargetOpcode::G_FFLOOR*//*Label 78*/ GIMT_Encode4(127505),
1045 /* 922 */ /*TargetOpcode::G_FRINT*//*Label 79*/ GIMT_Encode4(127871),
1046 /* 926 */ /*TargetOpcode::G_FNEARBYINT*//*Label 80*/ GIMT_Encode4(128270), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1047 /* 954 */ /*TargetOpcode::G_STRICT_FADD*//*Label 81*/ GIMT_Encode4(128405),
1048 /* 958 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 82*/ GIMT_Encode4(128567),
1049 /* 962 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 83*/ GIMT_Encode4(128729),
1050 /* 966 */ /*TargetOpcode::G_STRICT_FDIV*//*Label 84*/ GIMT_Encode4(128891), GIMT_Encode4(0),
1051 /* 974 */ /*TargetOpcode::G_STRICT_FMA*//*Label 85*/ GIMT_Encode4(129053),
1052 /* 978 */ /*TargetOpcode::G_STRICT_FSQRT*//*Label 86*/ GIMT_Encode4(130220), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1053 /* 1026 */ /*TargetOpcode::G_TRAP*//*Label 87*/ GIMT_Encode4(130355),
1054 /* 1030 */ /*TargetOpcode::G_DEBUGTRAP*//*Label 88*/ GIMT_Encode4(130384), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1055 /* 1078 */ /*TargetOpcode::G_VECREDUCE_ADD*//*Label 89*/ GIMT_Encode4(130467), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1056 /* 1098 */ /*TargetOpcode::G_VECREDUCE_SMAX*//*Label 90*/ GIMT_Encode4(130841),
1057 /* 1102 */ /*TargetOpcode::G_VECREDUCE_SMIN*//*Label 91*/ GIMT_Encode4(131106),
1058 /* 1106 */ /*TargetOpcode::G_VECREDUCE_UMAX*//*Label 92*/ GIMT_Encode4(131380),
1059 /* 1110 */ /*TargetOpcode::G_VECREDUCE_UMIN*//*Label 93*/ GIMT_Encode4(131646),
1060 /* 1114 */ // Label 0: @1114
1061 /* 1114 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 104*/ GIMT_Encode4(12541),
1062 /* 1125 */ /*GILLT_s32*//*Label 95*/ GIMT_Encode4(1177),
1063 /* 1129 */ /*GILLT_s64*//*Label 96*/ GIMT_Encode4(6820), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1064 /* 1149 */ /*GILLT_v8s8*//*Label 97*/ GIMT_Encode4(6866),
1065 /* 1153 */ /*GILLT_v16s8*//*Label 98*/ GIMT_Encode4(7300),
1066 /* 1157 */ /*GILLT_v4s16*//*Label 99*/ GIMT_Encode4(7800),
1067 /* 1161 */ /*GILLT_v8s16*//*Label 100*/ GIMT_Encode4(8234),
1068 /* 1165 */ /*GILLT_v2s32*//*Label 101*/ GIMT_Encode4(9669),
1069 /* 1169 */ /*GILLT_v4s32*//*Label 102*/ GIMT_Encode4(10103),
1070 /* 1173 */ /*GILLT_v2s64*//*Label 103*/ GIMT_Encode4(11538),
1071 /* 1177 */ // Label 95: @1177
1072 /* 1177 */ GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(6819),
1073 /* 1182 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1074 /* 1185 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1075 /* 1188 */ GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(1334),
1076 /* 1193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1077 /* 1197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1078 /* 1201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 107*/ GIMT_Encode4(1267), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6275 //
1079 /* 1208 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1080 /* 1212 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1081 /* 1216 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1082 /* 1220 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1083 /* 1224 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1084 /* 1229 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1085 /* 1240 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1086 /* 1242 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1087 /* 1242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB),
1088 /* 1245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1089 /* 1247 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1090 /* 1249 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1091 /* 1253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1092 /* 1256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1093 /* 1259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1094 /* 1265 */ GIR_RootConstrainSelectedInstOperands,
1095 /* 1266 */ // GIR_Coverage, 6275,
1096 /* 1266 */ GIR_EraseRootFromParent_Done,
1097 /* 1267 */ // Label 107: @1267
1098 /* 1267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 108*/ GIMT_Encode4(1333), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6276 //
1099 /* 1274 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1100 /* 1278 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1101 /* 1282 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1102 /* 1286 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1103 /* 1290 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1104 /* 1295 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1105 /* 1306 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1106 /* 1308 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1107 /* 1308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH),
1108 /* 1311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1109 /* 1313 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1110 /* 1315 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1111 /* 1319 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1112 /* 1322 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1113 /* 1325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1114 /* 1331 */ GIR_RootConstrainSelectedInstOperands,
1115 /* 1332 */ // GIR_Coverage, 6276,
1116 /* 1332 */ GIR_EraseRootFromParent_Done,
1117 /* 1333 */ // Label 108: @1333
1118 /* 1333 */ GIM_Reject,
1119 /* 1334 */ // Label 106: @1334
1120 /* 1334 */ GIM_Try, /*On fail goto*//*Label 109*/ GIMT_Encode4(1480),
1121 /* 1339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1122 /* 1343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1123 /* 1347 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 110*/ GIMT_Encode4(1413), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6314 //
1124 /* 1354 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1125 /* 1358 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1126 /* 1362 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1127 /* 1366 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1128 /* 1370 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1129 /* 1375 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1130 /* 1386 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1131 /* 1388 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1132 /* 1388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB),
1133 /* 1391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1134 /* 1393 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1135 /* 1395 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1136 /* 1399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1137 /* 1402 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1138 /* 1405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1139 /* 1411 */ GIR_RootConstrainSelectedInstOperands,
1140 /* 1412 */ // GIR_Coverage, 6314,
1141 /* 1412 */ GIR_EraseRootFromParent_Done,
1142 /* 1413 */ // Label 110: @1413
1143 /* 1413 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 111*/ GIMT_Encode4(1479), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6315 //
1144 /* 1420 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1145 /* 1424 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1146 /* 1428 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1147 /* 1432 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1148 /* 1436 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1149 /* 1441 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1150 /* 1452 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1151 /* 1454 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1152 /* 1454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH),
1153 /* 1457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1154 /* 1459 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1155 /* 1461 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1156 /* 1465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1157 /* 1468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1158 /* 1471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1159 /* 1477 */ GIR_RootConstrainSelectedInstOperands,
1160 /* 1478 */ // GIR_Coverage, 6315,
1161 /* 1478 */ GIR_EraseRootFromParent_Done,
1162 /* 1479 */ // Label 111: @1479
1163 /* 1479 */ GIM_Reject,
1164 /* 1480 */ // Label 109: @1480
1165 /* 1480 */ GIM_Try, /*On fail goto*//*Label 112*/ GIMT_Encode4(1626),
1166 /* 1485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1167 /* 1489 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1168 /* 1493 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 113*/ GIMT_Encode4(1559), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2195 //
1169 /* 1500 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1170 /* 1504 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1171 /* 1508 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1172 /* 1512 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1173 /* 1516 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1174 /* 1521 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1175 /* 1532 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1176 /* 1534 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1177 /* 1534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB),
1178 /* 1537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1179 /* 1539 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1180 /* 1541 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1181 /* 1545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1182 /* 1548 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1183 /* 1551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1184 /* 1557 */ GIR_RootConstrainSelectedInstOperands,
1185 /* 1558 */ // GIR_Coverage, 2195,
1186 /* 1558 */ GIR_EraseRootFromParent_Done,
1187 /* 1559 */ // Label 113: @1559
1188 /* 1559 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 114*/ GIMT_Encode4(1625), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2196 //
1189 /* 1566 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1190 /* 1570 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1191 /* 1574 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1192 /* 1578 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1193 /* 1582 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1194 /* 1587 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1195 /* 1598 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1196 /* 1600 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1197 /* 1600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH),
1198 /* 1603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1199 /* 1605 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1200 /* 1607 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1201 /* 1611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1202 /* 1614 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1203 /* 1617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1204 /* 1623 */ GIR_RootConstrainSelectedInstOperands,
1205 /* 1624 */ // GIR_Coverage, 2196,
1206 /* 1624 */ GIR_EraseRootFromParent_Done,
1207 /* 1625 */ // Label 114: @1625
1208 /* 1625 */ GIM_Reject,
1209 /* 1626 */ // Label 112: @1626
1210 /* 1626 */ GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(2274),
1211 /* 1631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1212 /* 1635 */ GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(1777),
1213 /* 1640 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1214 /* 1644 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 117*/ GIMT_Encode4(1710), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2439 //
1215 /* 1651 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1216 /* 1655 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1217 /* 1659 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1218 /* 1663 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1219 /* 1667 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1220 /* 1672 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1221 /* 1683 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1222 /* 1685 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1223 /* 1685 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB),
1224 /* 1688 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1225 /* 1690 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1226 /* 1692 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1227 /* 1696 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1228 /* 1699 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1229 /* 1702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1230 /* 1708 */ GIR_RootConstrainSelectedInstOperands,
1231 /* 1709 */ // GIR_Coverage, 2439,
1232 /* 1709 */ GIR_EraseRootFromParent_Done,
1233 /* 1710 */ // Label 117: @1710
1234 /* 1710 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 118*/ GIMT_Encode4(1776), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2440 //
1235 /* 1717 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1236 /* 1721 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1237 /* 1725 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1238 /* 1729 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1239 /* 1733 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1240 /* 1738 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1241 /* 1749 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1242 /* 1751 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1243 /* 1751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH),
1244 /* 1754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1245 /* 1756 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1246 /* 1758 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1247 /* 1762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1248 /* 1765 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1249 /* 1768 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1250 /* 1774 */ GIR_RootConstrainSelectedInstOperands,
1251 /* 1775 */ // GIR_Coverage, 2440,
1252 /* 1775 */ GIR_EraseRootFromParent_Done,
1253 /* 1776 */ // Label 118: @1776
1254 /* 1776 */ GIM_Reject,
1255 /* 1777 */ // Label 116: @1777
1256 /* 1777 */ GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(2025),
1257 /* 1782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1258 /* 1786 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 120*/ GIMT_Encode4(1905), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6287 //
1259 /* 1793 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1260 /* 1797 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1261 /* 1801 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1262 /* 1805 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1263 /* 1809 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1264 /* 1813 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1265 /* 1817 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1266 /* 1821 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1267 /* 1825 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
1268 /* 1829 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1269 /* 1833 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1270 /* 1837 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1271 /* 1842 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
1272 /* 1846 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1273 /* 1850 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
1274 /* 1854 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1275 /* 1858 */ // MIs[4] Rm
1276 /* 1858 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1277 /* 1863 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
1278 /* 1867 */ // MIs[1] Operand 2
1279 /* 1867 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1280 /* 1878 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1281 /* 1880 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1282 /* 1880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1283 /* 1883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1284 /* 1885 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1285 /* 1887 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1286 /* 1891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1287 /* 1894 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1288 /* 1897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1289 /* 1903 */ GIR_RootConstrainSelectedInstOperands,
1290 /* 1904 */ // GIR_Coverage, 6287,
1291 /* 1904 */ GIR_EraseRootFromParent_Done,
1292 /* 1905 */ // Label 120: @1905
1293 /* 1905 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 121*/ GIMT_Encode4(2024), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6288 //
1294 /* 1912 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1295 /* 1916 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1296 /* 1920 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1297 /* 1924 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1298 /* 1928 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1299 /* 1932 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1300 /* 1936 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1301 /* 1940 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1302 /* 1944 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
1303 /* 1948 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1304 /* 1952 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1305 /* 1956 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1306 /* 1961 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8,
1307 /* 1965 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1308 /* 1969 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
1309 /* 1973 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1310 /* 1977 */ // MIs[4] Rm
1311 /* 1977 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1312 /* 1982 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
1313 /* 1986 */ // MIs[1] Operand 2
1314 /* 1986 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1315 /* 1997 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1316 /* 1999 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1317 /* 1999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1318 /* 2002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1319 /* 2004 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1320 /* 2006 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1321 /* 2010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1322 /* 2013 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1323 /* 2016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1324 /* 2022 */ GIR_RootConstrainSelectedInstOperands,
1325 /* 2023 */ // GIR_Coverage, 6288,
1326 /* 2023 */ GIR_EraseRootFromParent_Done,
1327 /* 2024 */ // Label 121: @2024
1328 /* 2024 */ GIM_Reject,
1329 /* 2025 */ // Label 119: @2025
1330 /* 2025 */ GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(2273),
1331 /* 2030 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1332 /* 2034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 123*/ GIMT_Encode4(2153), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2302 //
1333 /* 2041 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1334 /* 2045 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1335 /* 2049 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1336 /* 2053 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1337 /* 2057 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1338 /* 2061 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1339 /* 2065 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1340 /* 2069 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1341 /* 2073 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
1342 /* 2077 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1343 /* 2081 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1344 /* 2085 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1345 /* 2090 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
1346 /* 2094 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1347 /* 2098 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
1348 /* 2102 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1349 /* 2106 */ // MIs[4] Rm
1350 /* 2106 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1351 /* 2111 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
1352 /* 2115 */ // MIs[1] Operand 2
1353 /* 2115 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1354 /* 2126 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1355 /* 2128 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1356 /* 2128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1357 /* 2131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1358 /* 2133 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1359 /* 2135 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1360 /* 2139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1361 /* 2142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1362 /* 2145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1363 /* 2151 */ GIR_RootConstrainSelectedInstOperands,
1364 /* 2152 */ // GIR_Coverage, 2302,
1365 /* 2152 */ GIR_EraseRootFromParent_Done,
1366 /* 2153 */ // Label 123: @2153
1367 /* 2153 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 124*/ GIMT_Encode4(2272), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6286 //
1368 /* 2160 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1369 /* 2164 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1370 /* 2168 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1371 /* 2172 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1372 /* 2176 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1373 /* 2180 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1374 /* 2184 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1375 /* 2188 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1376 /* 2192 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
1377 /* 2196 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1378 /* 2200 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1379 /* 2204 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1380 /* 2209 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8,
1381 /* 2213 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1382 /* 2217 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
1383 /* 2221 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1384 /* 2225 */ // MIs[4] Rm
1385 /* 2225 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1386 /* 2230 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
1387 /* 2234 */ // MIs[1] Operand 2
1388 /* 2234 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1389 /* 2245 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1390 /* 2247 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1391 /* 2247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1392 /* 2250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1393 /* 2252 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1394 /* 2254 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1395 /* 2258 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1396 /* 2261 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1397 /* 2264 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1398 /* 2270 */ GIR_RootConstrainSelectedInstOperands,
1399 /* 2271 */ // GIR_Coverage, 6286,
1400 /* 2271 */ GIR_EraseRootFromParent_Done,
1401 /* 2272 */ // Label 124: @2272
1402 /* 2272 */ GIM_Reject,
1403 /* 2273 */ // Label 122: @2273
1404 /* 2273 */ GIM_Reject,
1405 /* 2274 */ // Label 115: @2274
1406 /* 2274 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 125*/ GIMT_Encode4(2383), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5984 //
1407 /* 2281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1408 /* 2285 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1409 /* 2289 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1410 /* 2293 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1411 /* 2297 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1412 /* 2301 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1413 /* 2305 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1414 /* 2309 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1415 /* 2313 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1416 /* 2317 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1417 /* 2322 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1418 /* 2326 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1419 /* 2330 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1420 /* 2334 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1421 /* 2338 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1422 /* 2342 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1423 /* 2347 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1424 /* 2351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1425 /* 2355 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1426 /* 2357 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1427 /* 2357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT),
1428 /* 2360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1429 /* 2362 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1430 /* 2366 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1431 /* 2370 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1432 /* 2372 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1433 /* 2375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1434 /* 2381 */ GIR_RootConstrainSelectedInstOperands,
1435 /* 2382 */ // GIR_Coverage, 5984,
1436 /* 2382 */ GIR_EraseRootFromParent_Done,
1437 /* 2383 */ // Label 125: @2383
1438 /* 2383 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 126*/ GIMT_Encode4(2492), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6019 //
1439 /* 2390 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1440 /* 2394 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1441 /* 2398 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1442 /* 2402 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1443 /* 2406 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1444 /* 2410 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1445 /* 2414 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1446 /* 2418 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1447 /* 2422 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1448 /* 2426 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1449 /* 2431 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1450 /* 2435 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1451 /* 2439 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1452 /* 2443 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1453 /* 2447 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1454 /* 2451 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1455 /* 2456 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1456 /* 2460 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1457 /* 2464 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1458 /* 2466 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1459 /* 2466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT),
1460 /* 2469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1461 /* 2471 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1462 /* 2475 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1463 /* 2479 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1464 /* 2481 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1465 /* 2484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1466 /* 2490 */ GIR_RootConstrainSelectedInstOperands,
1467 /* 2491 */ // GIR_Coverage, 6019,
1468 /* 2491 */ GIR_EraseRootFromParent_Done,
1469 /* 2492 */ // Label 126: @2492
1470 /* 2492 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 127*/ GIMT_Encode4(2601), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 191 //
1471 /* 2499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1472 /* 2503 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1473 /* 2507 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1474 /* 2511 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1475 /* 2515 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1476 /* 2519 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1477 /* 2523 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1478 /* 2527 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1479 /* 2531 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1480 /* 2535 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1481 /* 2539 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1482 /* 2544 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1483 /* 2548 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1484 /* 2552 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1485 /* 2556 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1486 /* 2560 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1487 /* 2564 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1488 /* 2569 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1489 /* 2573 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1490 /* 2575 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1491 /* 2575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT),
1492 /* 2578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1493 /* 2580 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1494 /* 2584 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1495 /* 2588 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1496 /* 2590 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1497 /* 2593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1498 /* 2599 */ GIR_RootConstrainSelectedInstOperands,
1499 /* 2600 */ // GIR_Coverage, 191,
1500 /* 2600 */ GIR_EraseRootFromParent_Done,
1501 /* 2601 */ // Label 127: @2601
1502 /* 2601 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 128*/ GIMT_Encode4(2710), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 520 //
1503 /* 2608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1504 /* 2612 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1505 /* 2616 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1506 /* 2620 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1507 /* 2624 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1508 /* 2628 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1509 /* 2632 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1510 /* 2636 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1511 /* 2640 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1512 /* 2644 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1513 /* 2648 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1514 /* 2653 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1515 /* 2657 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1516 /* 2661 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1517 /* 2665 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1518 /* 2669 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1519 /* 2673 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1520 /* 2678 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1521 /* 2682 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1522 /* 2684 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1523 /* 2684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT),
1524 /* 2687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1525 /* 2689 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1526 /* 2693 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1527 /* 2697 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1528 /* 2699 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1529 /* 2702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1530 /* 2708 */ GIR_RootConstrainSelectedInstOperands,
1531 /* 2709 */ // GIR_Coverage, 520,
1532 /* 2709 */ GIR_EraseRootFromParent_Done,
1533 /* 2710 */ // Label 128: @2710
1534 /* 2710 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 129*/ GIMT_Encode4(2822), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5983 //
1535 /* 2717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1536 /* 2721 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1537 /* 2725 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1538 /* 2729 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1539 /* 2733 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1540 /* 2737 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1541 /* 2741 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1542 /* 2745 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1543 /* 2749 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1544 /* 2753 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1545 /* 2758 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1546 /* 2762 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1547 /* 2766 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1548 /* 2770 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1549 /* 2774 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1550 /* 2779 */ // MIs[3] Operand 2
1551 /* 2779 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1552 /* 2790 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1553 /* 2794 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1554 /* 2796 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1555 /* 2796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
1556 /* 2799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1557 /* 2801 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
1558 /* 2805 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1559 /* 2809 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1560 /* 2811 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1561 /* 2814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1562 /* 2820 */ GIR_RootConstrainSelectedInstOperands,
1563 /* 2821 */ // GIR_Coverage, 5983,
1564 /* 2821 */ GIR_EraseRootFromParent_Done,
1565 /* 2822 */ // Label 129: @2822
1566 /* 2822 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 130*/ GIMT_Encode4(2934), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6018 //
1567 /* 2829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1568 /* 2833 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1569 /* 2837 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1570 /* 2841 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1571 /* 2845 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1572 /* 2849 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1573 /* 2853 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1574 /* 2857 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1575 /* 2861 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1576 /* 2865 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1577 /* 2870 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1578 /* 2874 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1579 /* 2878 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1580 /* 2882 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1581 /* 2886 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1582 /* 2891 */ // MIs[3] Operand 2
1583 /* 2891 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1584 /* 2902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1585 /* 2906 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1586 /* 2908 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1587 /* 2908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
1588 /* 2911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1589 /* 2913 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
1590 /* 2917 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1591 /* 2921 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1592 /* 2923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1593 /* 2926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1594 /* 2932 */ GIR_RootConstrainSelectedInstOperands,
1595 /* 2933 */ // GIR_Coverage, 6018,
1596 /* 2933 */ GIR_EraseRootFromParent_Done,
1597 /* 2934 */ // Label 130: @2934
1598 /* 2934 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 131*/ GIMT_Encode4(3046), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5982 //
1599 /* 2941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1600 /* 2945 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1601 /* 2949 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1602 /* 2953 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1603 /* 2957 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1604 /* 2961 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1605 /* 2965 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1606 /* 2969 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1607 /* 2973 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1608 /* 2978 */ // MIs[2] Operand 2
1609 /* 2978 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1610 /* 2989 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1611 /* 2993 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1612 /* 2997 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1613 /* 3001 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1614 /* 3005 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1615 /* 3010 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1616 /* 3014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1617 /* 3018 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1618 /* 3020 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1619 /* 3020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
1620 /* 3023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1621 /* 3025 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1622 /* 3029 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1623 /* 3033 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1624 /* 3035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1625 /* 3038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1626 /* 3044 */ GIR_RootConstrainSelectedInstOperands,
1627 /* 3045 */ // GIR_Coverage, 5982,
1628 /* 3045 */ GIR_EraseRootFromParent_Done,
1629 /* 3046 */ // Label 131: @3046
1630 /* 3046 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 132*/ GIMT_Encode4(3158), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6017 //
1631 /* 3053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1632 /* 3057 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1633 /* 3061 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1634 /* 3065 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1635 /* 3069 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1636 /* 3073 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1637 /* 3077 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1638 /* 3081 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1639 /* 3085 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1640 /* 3090 */ // MIs[2] Operand 2
1641 /* 3090 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1642 /* 3101 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1643 /* 3105 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1644 /* 3109 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1645 /* 3113 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1646 /* 3117 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1647 /* 3122 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1648 /* 3126 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1649 /* 3130 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1650 /* 3132 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1651 /* 3132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
1652 /* 3135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1653 /* 3137 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1654 /* 3141 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1655 /* 3145 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1656 /* 3147 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1657 /* 3150 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1658 /* 3156 */ GIR_RootConstrainSelectedInstOperands,
1659 /* 3157 */ // GIR_Coverage, 6017,
1660 /* 3157 */ GIR_EraseRootFromParent_Done,
1661 /* 3158 */ // Label 132: @3158
1662 /* 3158 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 133*/ GIMT_Encode4(3270), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 190 //
1663 /* 3165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1664 /* 3169 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1665 /* 3173 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1666 /* 3177 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1667 /* 3181 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1668 /* 3185 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1669 /* 3189 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1670 /* 3193 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1671 /* 3197 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1672 /* 3201 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1673 /* 3205 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1674 /* 3210 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1675 /* 3214 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1676 /* 3218 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1677 /* 3222 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1678 /* 3226 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1679 /* 3231 */ // MIs[3] Operand 2
1680 /* 3231 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1681 /* 3242 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1682 /* 3244 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLATB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1683 /* 3244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB),
1684 /* 3247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1685 /* 3249 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1686 /* 3253 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1687 /* 3257 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1688 /* 3259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1689 /* 3262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1690 /* 3268 */ GIR_RootConstrainSelectedInstOperands,
1691 /* 3269 */ // GIR_Coverage, 190,
1692 /* 3269 */ GIR_EraseRootFromParent_Done,
1693 /* 3270 */ // Label 133: @3270
1694 /* 3270 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 134*/ GIMT_Encode4(3382), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 519 //
1695 /* 3277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1696 /* 3281 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1697 /* 3285 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1698 /* 3289 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1699 /* 3293 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1700 /* 3297 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1701 /* 3301 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1702 /* 3305 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1703 /* 3309 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1704 /* 3313 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1705 /* 3317 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1706 /* 3322 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1707 /* 3326 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1708 /* 3330 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1709 /* 3334 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1710 /* 3338 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1711 /* 3343 */ // MIs[3] Operand 2
1712 /* 3343 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1713 /* 3354 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1714 /* 3356 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLATB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1715 /* 3356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB),
1716 /* 3359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1717 /* 3361 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1718 /* 3365 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1719 /* 3369 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1720 /* 3371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1721 /* 3374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1722 /* 3380 */ GIR_RootConstrainSelectedInstOperands,
1723 /* 3381 */ // GIR_Coverage, 519,
1724 /* 3381 */ GIR_EraseRootFromParent_Done,
1725 /* 3382 */ // Label 134: @3382
1726 /* 3382 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 135*/ GIMT_Encode4(3494), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 189 //
1727 /* 3389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1728 /* 3393 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1729 /* 3397 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1730 /* 3401 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1731 /* 3405 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1732 /* 3409 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1733 /* 3413 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1734 /* 3417 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1735 /* 3421 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1736 /* 3425 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1737 /* 3430 */ // MIs[2] Operand 2
1738 /* 3430 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1739 /* 3441 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1740 /* 3445 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1741 /* 3449 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1742 /* 3453 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1743 /* 3457 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1744 /* 3462 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1745 /* 3466 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1746 /* 3468 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1747 /* 3468 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
1748 /* 3471 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1749 /* 3473 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1750 /* 3477 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1751 /* 3481 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1752 /* 3483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1753 /* 3486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1754 /* 3492 */ GIR_RootConstrainSelectedInstOperands,
1755 /* 3493 */ // GIR_Coverage, 189,
1756 /* 3493 */ GIR_EraseRootFromParent_Done,
1757 /* 3494 */ // Label 135: @3494
1758 /* 3494 */ GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(3784),
1759 /* 3499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1760 /* 3503 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 137*/ GIMT_Encode4(3611), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 518 //
1761 /* 3510 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1762 /* 3514 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1763 /* 3518 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1764 /* 3522 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1765 /* 3526 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1766 /* 3530 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1767 /* 3534 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1768 /* 3538 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1769 /* 3542 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1770 /* 3547 */ // MIs[2] Operand 2
1771 /* 3547 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1772 /* 3558 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1773 /* 3562 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1774 /* 3566 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1775 /* 3570 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1776 /* 3574 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1777 /* 3579 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1778 /* 3583 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1779 /* 3585 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1780 /* 3585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
1781 /* 3588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1782 /* 3590 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1783 /* 3594 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1784 /* 3598 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1785 /* 3600 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1786 /* 3603 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1787 /* 3609 */ GIR_RootConstrainSelectedInstOperands,
1788 /* 3610 */ // GIR_Coverage, 518,
1789 /* 3610 */ GIR_EraseRootFromParent_Done,
1790 /* 3611 */ // Label 137: @3611
1791 /* 3611 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 138*/ GIMT_Encode4(3697), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6285 //
1792 /* 3618 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1793 /* 3622 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1794 /* 3626 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1795 /* 3630 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1796 /* 3634 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR),
1797 /* 3638 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1798 /* 3642 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1799 /* 3646 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1800 /* 3651 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
1801 /* 3655 */ // MIs[1] Operand 2
1802 /* 3655 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1803 /* 3666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1804 /* 3670 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
1805 /* 3672 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1806 /* 3672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1807 /* 3675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1808 /* 3677 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1809 /* 3679 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1810 /* 3683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1811 /* 3686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1812 /* 3689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1813 /* 3695 */ GIR_RootConstrainSelectedInstOperands,
1814 /* 3696 */ // GIR_Coverage, 6285,
1815 /* 3696 */ GIR_EraseRootFromParent_Done,
1816 /* 3697 */ // Label 138: @3697
1817 /* 3697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 139*/ GIMT_Encode4(3783), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2301 //
1818 /* 3704 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1819 /* 3708 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1820 /* 3712 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1821 /* 3716 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1822 /* 3720 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1823 /* 3724 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR),
1824 /* 3728 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1825 /* 3732 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1826 /* 3736 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1827 /* 3741 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
1828 /* 3745 */ // MIs[1] Operand 2
1829 /* 3745 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1830 /* 3756 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
1831 /* 3758 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1832 /* 3758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1833 /* 3761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1834 /* 3763 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1835 /* 3765 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1836 /* 3769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1837 /* 3772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1838 /* 3775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1839 /* 3781 */ GIR_RootConstrainSelectedInstOperands,
1840 /* 3782 */ // GIR_Coverage, 2301,
1841 /* 3782 */ GIR_EraseRootFromParent_Done,
1842 /* 3783 */ // Label 139: @3783
1843 /* 3783 */ GIM_Reject,
1844 /* 3784 */ // Label 136: @3784
1845 /* 3784 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 140*/ GIMT_Encode4(3899), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 5981 //
1846 /* 3791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1847 /* 3795 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1848 /* 3799 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1849 /* 3803 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1850 /* 3807 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1851 /* 3811 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1852 /* 3815 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1853 /* 3819 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1854 /* 3823 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1855 /* 3828 */ // MIs[2] Operand 2
1856 /* 3828 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1857 /* 3839 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1858 /* 3843 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1859 /* 3847 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1860 /* 3851 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1861 /* 3856 */ // MIs[3] Operand 2
1862 /* 3856 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1863 /* 3867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1864 /* 3871 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1865 /* 3873 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1866 /* 3873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB),
1867 /* 3876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1868 /* 3878 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1869 /* 3882 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1870 /* 3886 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1871 /* 3888 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1872 /* 3891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1873 /* 3897 */ GIR_RootConstrainSelectedInstOperands,
1874 /* 3898 */ // GIR_Coverage, 5981,
1875 /* 3898 */ GIR_EraseRootFromParent_Done,
1876 /* 3899 */ // Label 140: @3899
1877 /* 3899 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 141*/ GIMT_Encode4(4014), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6016 //
1878 /* 3906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1879 /* 3910 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1880 /* 3914 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1881 /* 3918 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1882 /* 3922 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1883 /* 3926 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1884 /* 3930 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1885 /* 3934 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1886 /* 3938 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1887 /* 3943 */ // MIs[2] Operand 2
1888 /* 3943 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1889 /* 3954 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1890 /* 3958 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1891 /* 3962 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1892 /* 3966 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1893 /* 3971 */ // MIs[3] Operand 2
1894 /* 3971 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1895 /* 3982 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1896 /* 3986 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1897 /* 3988 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1898 /* 3988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB),
1899 /* 3991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1900 /* 3993 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1901 /* 3997 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1902 /* 4001 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1903 /* 4003 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1904 /* 4006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1905 /* 4012 */ GIR_RootConstrainSelectedInstOperands,
1906 /* 4013 */ // GIR_Coverage, 6016,
1907 /* 4013 */ GIR_EraseRootFromParent_Done,
1908 /* 4014 */ // Label 141: @4014
1909 /* 4014 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 142*/ GIMT_Encode4(4129), GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps), // Rule ID 188 //
1910 /* 4021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1911 /* 4025 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1912 /* 4029 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1913 /* 4033 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1914 /* 4037 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1915 /* 4041 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1916 /* 4045 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1917 /* 4049 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1918 /* 4053 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1919 /* 4057 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1920 /* 4062 */ // MIs[2] Operand 2
1921 /* 4062 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1922 /* 4073 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1923 /* 4077 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1924 /* 4081 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1925 /* 4085 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1926 /* 4090 */ // MIs[3] Operand 2
1927 /* 4090 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1928 /* 4101 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1929 /* 4103 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1930 /* 4103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB),
1931 /* 4106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1932 /* 4108 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1933 /* 4112 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1934 /* 4116 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1935 /* 4118 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1936 /* 4121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1937 /* 4127 */ GIR_RootConstrainSelectedInstOperands,
1938 /* 4128 */ // GIR_Coverage, 188,
1939 /* 4128 */ GIR_EraseRootFromParent_Done,
1940 /* 4129 */ // Label 142: @4129
1941 /* 4129 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 143*/ GIMT_Encode4(4244), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 517 //
1942 /* 4136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1943 /* 4140 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1944 /* 4144 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1945 /* 4148 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1946 /* 4152 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1947 /* 4156 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1948 /* 4160 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1949 /* 4164 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1950 /* 4168 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1951 /* 4172 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1952 /* 4177 */ // MIs[2] Operand 2
1953 /* 4177 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1954 /* 4188 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1955 /* 4192 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1956 /* 4196 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1957 /* 4200 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1958 /* 4205 */ // MIs[3] Operand 2
1959 /* 4205 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1960 /* 4216 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1961 /* 4218 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1962 /* 4218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB),
1963 /* 4221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1964 /* 4223 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1965 /* 4227 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1966 /* 4231 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1967 /* 4233 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1968 /* 4236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1969 /* 4242 */ GIR_RootConstrainSelectedInstOperands,
1970 /* 4243 */ // GIR_Coverage, 517,
1971 /* 4243 */ GIR_EraseRootFromParent_Done,
1972 /* 4244 */ // Label 143: @4244
1973 /* 4244 */ GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(4748),
1974 /* 4249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
1975 /* 4253 */ GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(4500),
1976 /* 4258 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
1977 /* 4262 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 146*/ GIMT_Encode4(4341), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3639 //
1978 /* 4269 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1979 /* 4273 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
1980 /* 4277 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1981 /* 4281 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1982 /* 4285 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
1983 /* 4289 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1984 /* 4293 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1985 /* 4297 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
1986 /* 4302 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
1987 /* 4307 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
1988 /* 4309 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
1989 /* 4309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32),
1990 /* 4312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
1991 /* 4314 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3
1992 /* 4316 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
1993 /* 4320 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
1994 /* 4324 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1995 /* 4327 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1996 /* 4333 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1997 /* 4339 */ GIR_RootConstrainSelectedInstOperands,
1998 /* 4340 */ // GIR_Coverage, 3639,
1999 /* 4340 */ GIR_EraseRootFromParent_Done,
2000 /* 4341 */ // Label 146: @4341
2001 /* 4341 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 147*/ GIMT_Encode4(4420), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3640 //
2002 /* 4348 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2003 /* 4352 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2004 /* 4356 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2005 /* 4360 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2006 /* 4364 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2007 /* 4368 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
2008 /* 4372 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
2009 /* 4376 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2010 /* 4381 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2011 /* 4386 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2012 /* 4388 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
2013 /* 4388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16),
2014 /* 4391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2015 /* 4393 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3
2016 /* 4395 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2017 /* 4399 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2018 /* 4403 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2019 /* 4406 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2020 /* 4412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2021 /* 4418 */ GIR_RootConstrainSelectedInstOperands,
2022 /* 4419 */ // GIR_Coverage, 3640,
2023 /* 4419 */ GIR_EraseRootFromParent_Done,
2024 /* 4420 */ // Label 147: @4420
2025 /* 4420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 148*/ GIMT_Encode4(4499), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3643 //
2026 /* 4427 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2027 /* 4431 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2028 /* 4435 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2029 /* 4439 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2030 /* 4443 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2031 /* 4447 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
2032 /* 4451 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
2033 /* 4455 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2034 /* 4460 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2035 /* 4465 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2036 /* 4467 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
2037 /* 4467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8),
2038 /* 4470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2039 /* 4472 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3
2040 /* 4474 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2041 /* 4478 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2042 /* 4482 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2043 /* 4485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2044 /* 4491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2045 /* 4497 */ GIR_RootConstrainSelectedInstOperands,
2046 /* 4498 */ // GIR_Coverage, 3643,
2047 /* 4498 */ GIR_EraseRootFromParent_Done,
2048 /* 4499 */ // Label 148: @4499
2049 /* 4499 */ GIM_Reject,
2050 /* 4500 */ // Label 145: @4500
2051 /* 4500 */ GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(4747),
2052 /* 4505 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2053 /* 4509 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 150*/ GIMT_Encode4(4588), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6586 //
2054 /* 4516 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2055 /* 4520 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2056 /* 4524 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2057 /* 4528 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2058 /* 4532 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2059 /* 4536 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2060 /* 4540 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2061 /* 4544 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2062 /* 4549 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2063 /* 4554 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2064 /* 4556 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2))) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
2065 /* 4556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32),
2066 /* 4559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2067 /* 4561 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3
2068 /* 4563 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2069 /* 4567 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2070 /* 4571 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2071 /* 4574 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2072 /* 4580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2073 /* 4586 */ GIR_RootConstrainSelectedInstOperands,
2074 /* 4587 */ // GIR_Coverage, 6586,
2075 /* 4587 */ GIR_EraseRootFromParent_Done,
2076 /* 4588 */ // Label 150: @4588
2077 /* 4588 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 151*/ GIMT_Encode4(4667), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6587 //
2078 /* 4595 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2079 /* 4599 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2080 /* 4603 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2081 /* 4607 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2082 /* 4611 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2083 /* 4615 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
2084 /* 4619 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
2085 /* 4623 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2086 /* 4628 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2087 /* 4633 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2088 /* 4635 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2))) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
2089 /* 4635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16),
2090 /* 4638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2091 /* 4640 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3
2092 /* 4642 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2093 /* 4646 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2094 /* 4650 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2095 /* 4653 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2096 /* 4659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2097 /* 4665 */ GIR_RootConstrainSelectedInstOperands,
2098 /* 4666 */ // GIR_Coverage, 6587,
2099 /* 4666 */ GIR_EraseRootFromParent_Done,
2100 /* 4667 */ // Label 151: @4667
2101 /* 4667 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 152*/ GIMT_Encode4(4746), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6590 //
2102 /* 4674 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2103 /* 4678 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2104 /* 4682 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2105 /* 4686 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2106 /* 4690 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2107 /* 4694 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
2108 /* 4698 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
2109 /* 4702 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2110 /* 4707 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2111 /* 4712 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2112 /* 4714 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2))) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
2113 /* 4714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8),
2114 /* 4717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2115 /* 4719 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3
2116 /* 4721 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2117 /* 4725 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2118 /* 4729 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2119 /* 4732 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2120 /* 4738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2121 /* 4744 */ GIR_RootConstrainSelectedInstOperands,
2122 /* 4745 */ // GIR_Coverage, 6590,
2123 /* 4745 */ GIR_EraseRootFromParent_Done,
2124 /* 4746 */ // Label 152: @4746
2125 /* 4746 */ GIM_Reject,
2126 /* 4747 */ // Label 149: @4747
2127 /* 4747 */ GIM_Reject,
2128 /* 4748 */ // Label 144: @4748
2129 /* 4748 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 153*/ GIMT_Encode4(4804), GIMT_Encode2(GIFBS_IsARM), // Rule ID 71 //
2130 /* 4755 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2131 /* 4759 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2132 /* 4763 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2133 /* 4767 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2134 /* 4771 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
2135 /* 4775 */ // MIs[1] Operand 1
2136 /* 4775 */ // No operand predicates
2137 /* 4775 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2138 /* 4777 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
2139 /* 4777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDri),
2140 /* 4780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2141 /* 4782 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2142 /* 4784 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2143 /* 4787 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2144 /* 4790 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2145 /* 4796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2146 /* 4802 */ GIR_RootConstrainSelectedInstOperands,
2147 /* 4803 */ // GIR_Coverage, 71,
2148 /* 4803 */ GIR_EraseRootFromParent_Done,
2149 /* 4804 */ // Label 153: @4804
2150 /* 4804 */ GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(4914),
2151 /* 4809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2152 /* 4813 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2153 /* 4817 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 155*/ GIMT_Encode4(4865), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 302 //
2154 /* 4824 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2155 /* 4828 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2156 /* 4832 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
2157 /* 4836 */ // MIs[1] Operand 1
2158 /* 4836 */ // No operand predicates
2159 /* 4836 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2160 /* 4838 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm3) => (tADDi3:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm3)
2161 /* 4838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi3),
2162 /* 4841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2163 /* 4843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
2164 /* 4849 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
2165 /* 4851 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm3
2166 /* 4854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2167 /* 4857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2168 /* 4863 */ GIR_RootConstrainSelectedInstOperands,
2169 /* 4864 */ // GIR_Coverage, 302,
2170 /* 4864 */ GIR_EraseRootFromParent_Done,
2171 /* 4865 */ // Label 155: @4865
2172 /* 4865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 156*/ GIMT_Encode4(4913), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 303 //
2173 /* 4872 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2174 /* 4876 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2175 /* 4880 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr),
2176 /* 4884 */ // MIs[1] Operand 1
2177 /* 4884 */ // No operand predicates
2178 /* 4884 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2179 /* 4886 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8) => (tADDi8:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm8)
2180 /* 4886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi8),
2181 /* 4889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
2182 /* 4891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
2183 /* 4897 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2184 /* 4899 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8
2185 /* 4902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2186 /* 4905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2187 /* 4911 */ GIR_RootConstrainSelectedInstOperands,
2188 /* 4912 */ // GIR_Coverage, 303,
2189 /* 4912 */ GIR_EraseRootFromParent_Done,
2190 /* 4913 */ // Label 156: @4913
2191 /* 4913 */ GIM_Reject,
2192 /* 4914 */ // Label 154: @4914
2193 /* 4914 */ GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(5022),
2194 /* 4919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2195 /* 4923 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 158*/ GIMT_Encode4(4975), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 406 //
2196 /* 4930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2197 /* 4934 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2198 /* 4938 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2199 /* 4942 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
2200 /* 4946 */ // MIs[1] Operand 1
2201 /* 4946 */ // No operand predicates
2202 /* 4946 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2203 /* 4948 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
2204 /* 4948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri),
2205 /* 4951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2206 /* 4953 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2207 /* 4955 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2208 /* 4958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2209 /* 4961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2210 /* 4967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2211 /* 4973 */ GIR_RootConstrainSelectedInstOperands,
2212 /* 4974 */ // GIR_Coverage, 406,
2213 /* 4974 */ GIR_EraseRootFromParent_Done,
2214 /* 4975 */ // Label 158: @4975
2215 /* 4975 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 159*/ GIMT_Encode4(5021), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 407 //
2216 /* 4982 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2217 /* 4986 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2218 /* 4990 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2219 /* 4994 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095),
2220 /* 4998 */ // MIs[1] Operand 1
2221 /* 4998 */ // No operand predicates
2222 /* 4998 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2223 /* 5000 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
2224 /* 5000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri12),
2225 /* 5003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2226 /* 5005 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2227 /* 5007 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2228 /* 5010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2229 /* 5013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2230 /* 5019 */ GIR_RootConstrainSelectedInstOperands,
2231 /* 5020 */ // GIR_Coverage, 407,
2232 /* 5020 */ GIR_EraseRootFromParent_Done,
2233 /* 5021 */ // Label 159: @5021
2234 /* 5021 */ GIM_Reject,
2235 /* 5022 */ // Label 157: @5022
2236 /* 5022 */ GIM_Try, /*On fail goto*//*Label 160*/ GIMT_Encode4(5170),
2237 /* 5027 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2238 /* 5031 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2239 /* 5035 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 161*/ GIMT_Encode4(5102), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 170 //
2240 /* 5042 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2241 /* 5046 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2242 /* 5050 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2243 /* 5054 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2244 /* 5058 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2245 /* 5063 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2246 /* 5068 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2247 /* 5070 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2248 /* 5070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA),
2249 /* 5073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2250 /* 5075 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2251 /* 5079 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2252 /* 5083 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2253 /* 5085 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2254 /* 5088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2255 /* 5094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2256 /* 5100 */ GIR_RootConstrainSelectedInstOperands,
2257 /* 5101 */ // GIR_Coverage, 170,
2258 /* 5101 */ GIR_EraseRootFromParent_Done,
2259 /* 5102 */ // Label 161: @5102
2260 /* 5102 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 162*/ GIMT_Encode4(5169), GIMT_Encode2(GIFBS_IsARM_NoV6), // Rule ID 171 //
2261 /* 5109 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2262 /* 5113 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2263 /* 5117 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2264 /* 5121 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2265 /* 5125 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2266 /* 5130 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2267 /* 5135 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2268 /* 5137 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2269 /* 5137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5),
2270 /* 5140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2271 /* 5142 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2272 /* 5146 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2273 /* 5150 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2274 /* 5152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2275 /* 5155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2276 /* 5161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2277 /* 5167 */ GIR_RootConstrainSelectedInstOperands,
2278 /* 5168 */ // GIR_Coverage, 171,
2279 /* 5168 */ GIR_EraseRootFromParent_Done,
2280 /* 5169 */ // Label 162: @5169
2281 /* 5169 */ GIM_Reject,
2282 /* 5170 */ // Label 160: @5170
2283 /* 5170 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 163*/ GIMT_Encode4(5239), GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), // Rule ID 502 //
2284 /* 5177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2285 /* 5181 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2286 /* 5185 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2287 /* 5189 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2288 /* 5193 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2289 /* 5197 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2290 /* 5202 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2291 /* 5207 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2292 /* 5211 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2293 /* 5213 */ // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2294 /* 5213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA),
2295 /* 5216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2296 /* 5218 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2297 /* 5222 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2298 /* 5226 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2299 /* 5228 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2300 /* 5231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2301 /* 5237 */ GIR_RootConstrainSelectedInstOperands,
2302 /* 5238 */ // GIR_Coverage, 502,
2303 /* 5238 */ GIR_EraseRootFromParent_Done,
2304 /* 5239 */ // Label 163: @5239
2305 /* 5239 */ GIM_Try, /*On fail goto*//*Label 164*/ GIMT_Encode4(5377),
2306 /* 5244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2307 /* 5248 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2308 /* 5252 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 165*/ GIMT_Encode4(5314), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6277 //
2309 /* 5259 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2310 /* 5263 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2311 /* 5267 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2312 /* 5271 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2313 /* 5276 */ // MIs[1] Operand 2
2314 /* 5276 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2315 /* 5287 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2316 /* 5289 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2317 /* 5289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB),
2318 /* 5292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2319 /* 5294 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2320 /* 5296 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2321 /* 5300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2322 /* 5303 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2323 /* 5306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2324 /* 5312 */ GIR_RootConstrainSelectedInstOperands,
2325 /* 5313 */ // GIR_Coverage, 6277,
2326 /* 5313 */ GIR_EraseRootFromParent_Done,
2327 /* 5314 */ // Label 165: @5314
2328 /* 5314 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 166*/ GIMT_Encode4(5376), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6278 //
2329 /* 5321 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2330 /* 5325 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2331 /* 5329 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2332 /* 5333 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2333 /* 5338 */ // MIs[1] Operand 2
2334 /* 5338 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2335 /* 5349 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2336 /* 5351 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2337 /* 5351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH),
2338 /* 5354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2339 /* 5356 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2340 /* 5358 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2341 /* 5362 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2342 /* 5365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2343 /* 5368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2344 /* 5374 */ GIR_RootConstrainSelectedInstOperands,
2345 /* 5375 */ // GIR_Coverage, 6278,
2346 /* 5375 */ GIR_EraseRootFromParent_Done,
2347 /* 5376 */ // Label 166: @5376
2348 /* 5376 */ GIM_Reject,
2349 /* 5377 */ // Label 164: @5377
2350 /* 5377 */ GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(5515),
2351 /* 5382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2352 /* 5386 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2353 /* 5390 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 168*/ GIMT_Encode4(5452), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6316 //
2354 /* 5397 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2355 /* 5401 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2356 /* 5405 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2357 /* 5409 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2358 /* 5414 */ // MIs[1] Operand 2
2359 /* 5414 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2360 /* 5425 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2361 /* 5427 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2362 /* 5427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB),
2363 /* 5430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2364 /* 5432 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2365 /* 5434 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2366 /* 5438 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2367 /* 5441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2368 /* 5444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2369 /* 5450 */ GIR_RootConstrainSelectedInstOperands,
2370 /* 5451 */ // GIR_Coverage, 6316,
2371 /* 5451 */ GIR_EraseRootFromParent_Done,
2372 /* 5452 */ // Label 168: @5452
2373 /* 5452 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 169*/ GIMT_Encode4(5514), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6317 //
2374 /* 5459 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2375 /* 5463 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2376 /* 5467 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2377 /* 5471 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2378 /* 5476 */ // MIs[1] Operand 2
2379 /* 5476 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2380 /* 5487 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2381 /* 5489 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2382 /* 5489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
2383 /* 5492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2384 /* 5494 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2385 /* 5496 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2386 /* 5500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2387 /* 5503 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2388 /* 5506 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2389 /* 5512 */ GIR_RootConstrainSelectedInstOperands,
2390 /* 5513 */ // GIR_Coverage, 6317,
2391 /* 5513 */ GIR_EraseRootFromParent_Done,
2392 /* 5514 */ // Label 169: @5514
2393 /* 5514 */ GIM_Reject,
2394 /* 5515 */ // Label 167: @5515
2395 /* 5515 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 170*/ GIMT_Encode4(5584), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 179 //
2396 /* 5522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2397 /* 5526 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2398 /* 5530 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2399 /* 5534 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2400 /* 5538 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2401 /* 5542 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2402 /* 5547 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2403 /* 5552 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2404 /* 5556 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2405 /* 5558 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
2406 /* 5558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA),
2407 /* 5561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2408 /* 5563 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2409 /* 5567 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2410 /* 5571 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2411 /* 5573 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2412 /* 5576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2413 /* 5582 */ GIR_RootConstrainSelectedInstOperands,
2414 /* 5583 */ // GIR_Coverage, 179,
2415 /* 5583 */ GIR_EraseRootFromParent_Done,
2416 /* 5584 */ // Label 170: @5584
2417 /* 5584 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 171*/ GIMT_Encode4(5653), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 508 //
2418 /* 5591 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2419 /* 5595 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2420 /* 5599 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2421 /* 5603 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2422 /* 5607 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2423 /* 5611 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2424 /* 5616 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2425 /* 5621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2426 /* 5625 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2427 /* 5627 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2428 /* 5627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA),
2429 /* 5630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2430 /* 5632 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2431 /* 5636 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2432 /* 5640 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2433 /* 5642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2434 /* 5645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2435 /* 5651 */ GIR_RootConstrainSelectedInstOperands,
2436 /* 5652 */ // GIR_Coverage, 508,
2437 /* 5652 */ GIR_EraseRootFromParent_Done,
2438 /* 5653 */ // Label 171: @5653
2439 /* 5653 */ GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(5829),
2440 /* 5658 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2441 /* 5662 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2442 /* 5666 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 173*/ GIMT_Encode4(5720), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3444 //
2443 /* 5673 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2444 /* 5677 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2445 /* 5681 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2446 /* 5685 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2447 /* 5690 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2448 /* 5692 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec)
2449 /* 5692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc),
2450 /* 5695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2451 /* 5697 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc
2452 /* 5699 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2453 /* 5703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2454 /* 5706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2455 /* 5712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2456 /* 5718 */ GIR_RootConstrainSelectedInstOperands,
2457 /* 5719 */ // GIR_Coverage, 3444,
2458 /* 5719 */ GIR_EraseRootFromParent_Done,
2459 /* 5720 */ // Label 173: @5720
2460 /* 5720 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 174*/ GIMT_Encode4(5774), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3472 //
2461 /* 5727 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2462 /* 5731 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2463 /* 5735 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2464 /* 5739 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2465 /* 5744 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2466 /* 5746 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec)
2467 /* 5746 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc),
2468 /* 5749 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2469 /* 5751 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc
2470 /* 5753 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2471 /* 5757 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2472 /* 5760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2473 /* 5766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2474 /* 5772 */ GIR_RootConstrainSelectedInstOperands,
2475 /* 5773 */ // GIR_Coverage, 3472,
2476 /* 5773 */ GIR_EraseRootFromParent_Done,
2477 /* 5774 */ // Label 174: @5774
2478 /* 5774 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 175*/ GIMT_Encode4(5828), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3482 //
2479 /* 5781 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2480 /* 5785 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2481 /* 5789 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2482 /* 5793 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2483 /* 5798 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2484 /* 5800 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec)
2485 /* 5800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc),
2486 /* 5803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2487 /* 5805 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc
2488 /* 5807 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2489 /* 5811 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2490 /* 5814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2491 /* 5820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2492 /* 5826 */ GIR_RootConstrainSelectedInstOperands,
2493 /* 5827 */ // GIR_Coverage, 3482,
2494 /* 5827 */ GIR_EraseRootFromParent_Done,
2495 /* 5828 */ // Label 175: @5828
2496 /* 5828 */ GIM_Reject,
2497 /* 5829 */ // Label 172: @5829
2498 /* 5829 */ GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(5977),
2499 /* 5834 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2500 /* 5838 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2501 /* 5842 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 177*/ GIMT_Encode4(5909), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 5978 //
2502 /* 5849 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2503 /* 5853 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2504 /* 5857 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2505 /* 5861 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2506 /* 5865 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2507 /* 5870 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2508 /* 5875 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2509 /* 5877 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2510 /* 5877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA),
2511 /* 5880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2512 /* 5882 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2513 /* 5886 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2514 /* 5890 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2515 /* 5892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2516 /* 5895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2517 /* 5901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2518 /* 5907 */ GIR_RootConstrainSelectedInstOperands,
2519 /* 5908 */ // GIR_Coverage, 5978,
2520 /* 5908 */ GIR_EraseRootFromParent_Done,
2521 /* 5909 */ // Label 177: @5909
2522 /* 5909 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 178*/ GIMT_Encode4(5976), GIMT_Encode2(GIFBS_IsARM_NoV6), // Rule ID 5979 //
2523 /* 5916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2524 /* 5920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2525 /* 5924 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2526 /* 5928 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2527 /* 5932 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2528 /* 5937 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2529 /* 5942 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2530 /* 5944 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2531 /* 5944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5),
2532 /* 5947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2533 /* 5949 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2534 /* 5953 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2535 /* 5957 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2536 /* 5959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2537 /* 5962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2538 /* 5968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2539 /* 5974 */ GIR_RootConstrainSelectedInstOperands,
2540 /* 5975 */ // GIR_Coverage, 5979,
2541 /* 5975 */ GIR_EraseRootFromParent_Done,
2542 /* 5976 */ // Label 178: @5976
2543 /* 5976 */ GIM_Reject,
2544 /* 5977 */ // Label 176: @5977
2545 /* 5977 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 179*/ GIMT_Encode4(6046), GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), // Rule ID 6014 //
2546 /* 5984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2547 /* 5988 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2548 /* 5992 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2549 /* 5996 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2550 /* 6000 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2551 /* 6004 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2552 /* 6008 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2553 /* 6013 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2554 /* 6018 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2555 /* 6020 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2556 /* 6020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA),
2557 /* 6023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2558 /* 6025 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2559 /* 6029 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2560 /* 6033 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2561 /* 6035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2562 /* 6038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2563 /* 6044 */ GIR_RootConstrainSelectedInstOperands,
2564 /* 6045 */ // GIR_Coverage, 6014,
2565 /* 6045 */ GIR_EraseRootFromParent_Done,
2566 /* 6046 */ // Label 179: @6046
2567 /* 6046 */ GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(6184),
2568 /* 6051 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2569 /* 6055 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2570 /* 6059 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 181*/ GIMT_Encode4(6121), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2199 //
2571 /* 6066 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2572 /* 6070 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2573 /* 6074 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2574 /* 6078 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2575 /* 6083 */ // MIs[1] Operand 2
2576 /* 6083 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2577 /* 6094 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2578 /* 6096 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2579 /* 6096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB),
2580 /* 6099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2581 /* 6101 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2582 /* 6103 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2583 /* 6107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2584 /* 6110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2585 /* 6113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2586 /* 6119 */ GIR_RootConstrainSelectedInstOperands,
2587 /* 6120 */ // GIR_Coverage, 2199,
2588 /* 6120 */ GIR_EraseRootFromParent_Done,
2589 /* 6121 */ // Label 181: @6121
2590 /* 6121 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 182*/ GIMT_Encode4(6183), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2200 //
2591 /* 6128 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2592 /* 6132 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2593 /* 6136 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2594 /* 6140 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2595 /* 6145 */ // MIs[1] Operand 2
2596 /* 6145 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2597 /* 6156 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2598 /* 6158 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2599 /* 6158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH),
2600 /* 6161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2601 /* 6163 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2602 /* 6165 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2603 /* 6169 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2604 /* 6172 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2605 /* 6175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2606 /* 6181 */ GIR_RootConstrainSelectedInstOperands,
2607 /* 6182 */ // GIR_Coverage, 2200,
2608 /* 6182 */ GIR_EraseRootFromParent_Done,
2609 /* 6183 */ // Label 182: @6183
2610 /* 6183 */ GIM_Reject,
2611 /* 6184 */ // Label 180: @6184
2612 /* 6184 */ GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(6322),
2613 /* 6189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2614 /* 6193 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2615 /* 6197 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 184*/ GIMT_Encode4(6259), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2443 //
2616 /* 6204 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2617 /* 6208 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2618 /* 6212 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2619 /* 6216 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2620 /* 6221 */ // MIs[1] Operand 2
2621 /* 6221 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2622 /* 6232 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2623 /* 6234 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2624 /* 6234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB),
2625 /* 6237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2626 /* 6239 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2627 /* 6241 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2628 /* 6245 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2629 /* 6248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2630 /* 6251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2631 /* 6257 */ GIR_RootConstrainSelectedInstOperands,
2632 /* 6258 */ // GIR_Coverage, 2443,
2633 /* 6258 */ GIR_EraseRootFromParent_Done,
2634 /* 6259 */ // Label 184: @6259
2635 /* 6259 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 185*/ GIMT_Encode4(6321), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2444 //
2636 /* 6266 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2637 /* 6270 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2638 /* 6274 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2639 /* 6278 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2640 /* 6283 */ // MIs[1] Operand 2
2641 /* 6283 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2642 /* 6294 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2643 /* 6296 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2644 /* 6296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
2645 /* 6299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2646 /* 6301 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2647 /* 6303 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2648 /* 6307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2649 /* 6310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2650 /* 6313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2651 /* 6319 */ GIR_RootConstrainSelectedInstOperands,
2652 /* 6320 */ // GIR_Coverage, 2444,
2653 /* 6320 */ GIR_EraseRootFromParent_Done,
2654 /* 6321 */ // Label 185: @6321
2655 /* 6321 */ GIM_Reject,
2656 /* 6322 */ // Label 183: @6322
2657 /* 6322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 186*/ GIMT_Encode4(6391), GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps), // Rule ID 5980 //
2658 /* 6329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2659 /* 6333 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2660 /* 6337 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2661 /* 6341 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2662 /* 6345 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2663 /* 6349 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2664 /* 6353 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2665 /* 6358 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2666 /* 6363 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2667 /* 6365 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
2668 /* 6365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA),
2669 /* 6368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2670 /* 6370 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2671 /* 6374 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2672 /* 6378 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2673 /* 6380 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2674 /* 6383 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2675 /* 6389 */ GIR_RootConstrainSelectedInstOperands,
2676 /* 6390 */ // GIR_Coverage, 5980,
2677 /* 6390 */ GIR_EraseRootFromParent_Done,
2678 /* 6391 */ // Label 186: @6391
2679 /* 6391 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 187*/ GIMT_Encode4(6460), GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps), // Rule ID 6015 //
2680 /* 6398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2681 /* 6402 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2682 /* 6406 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2683 /* 6410 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2684 /* 6414 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2685 /* 6418 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2686 /* 6422 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2687 /* 6427 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2688 /* 6432 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2689 /* 6434 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2690 /* 6434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA),
2691 /* 6437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2692 /* 6439 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2693 /* 6443 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2694 /* 6447 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2695 /* 6449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2696 /* 6452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2697 /* 6458 */ GIR_RootConstrainSelectedInstOperands,
2698 /* 6459 */ // GIR_Coverage, 6015,
2699 /* 6459 */ GIR_EraseRootFromParent_Done,
2700 /* 6460 */ // Label 187: @6460
2701 /* 6460 */ GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(6636),
2702 /* 6465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2703 /* 6469 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2704 /* 6473 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 189*/ GIMT_Encode4(6527), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6562 //
2705 /* 6480 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2706 /* 6484 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2707 /* 6488 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2708 /* 6492 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2709 /* 6497 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2710 /* 6499 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec)) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec)
2711 /* 6499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc),
2712 /* 6502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2713 /* 6504 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc
2714 /* 6506 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2715 /* 6510 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2716 /* 6513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2717 /* 6519 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2718 /* 6525 */ GIR_RootConstrainSelectedInstOperands,
2719 /* 6526 */ // GIR_Coverage, 6562,
2720 /* 6526 */ GIR_EraseRootFromParent_Done,
2721 /* 6527 */ // Label 189: @6527
2722 /* 6527 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 190*/ GIMT_Encode4(6581), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6576 //
2723 /* 6534 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2724 /* 6538 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2725 /* 6542 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2726 /* 6546 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2727 /* 6551 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2728 /* 6553 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec)) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec)
2729 /* 6553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc),
2730 /* 6556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2731 /* 6558 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc
2732 /* 6560 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2733 /* 6564 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2734 /* 6567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2735 /* 6573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2736 /* 6579 */ GIR_RootConstrainSelectedInstOperands,
2737 /* 6580 */ // GIR_Coverage, 6576,
2738 /* 6580 */ GIR_EraseRootFromParent_Done,
2739 /* 6581 */ // Label 190: @6581
2740 /* 6581 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 191*/ GIMT_Encode4(6635), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6581 //
2741 /* 6588 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2742 /* 6592 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2743 /* 6596 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2744 /* 6600 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2745 /* 6605 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2746 /* 6607 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec)) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec)
2747 /* 6607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc),
2748 /* 6610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2749 /* 6612 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc
2750 /* 6614 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2751 /* 6618 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2752 /* 6621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2753 /* 6627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2754 /* 6633 */ GIR_RootConstrainSelectedInstOperands,
2755 /* 6634 */ // GIR_Coverage, 6581,
2756 /* 6634 */ GIR_EraseRootFromParent_Done,
2757 /* 6635 */ // Label 191: @6635
2758 /* 6635 */ GIM_Reject,
2759 /* 6636 */ // Label 188: @6636
2760 /* 6636 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 192*/ GIMT_Encode4(6681), GIMT_Encode2(GIFBS_IsARM), // Rule ID 72 //
2761 /* 6643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2762 /* 6647 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2763 /* 6651 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2764 /* 6655 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
2765 /* 6655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDrr),
2766 /* 6658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2767 /* 6660 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2768 /* 6662 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
2769 /* 6664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2770 /* 6667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2771 /* 6673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2772 /* 6679 */ GIR_RootConstrainSelectedInstOperands,
2773 /* 6680 */ // GIR_Coverage, 72,
2774 /* 6680 */ GIR_EraseRootFromParent_Done,
2775 /* 6681 */ // Label 192: @6681
2776 /* 6681 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 193*/ GIMT_Encode4(6726), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 304 //
2777 /* 6688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2778 /* 6692 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2779 /* 6696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2780 /* 6700 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tADDrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
2781 /* 6700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDrr),
2782 /* 6703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2783 /* 6705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
2784 /* 6711 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2785 /* 6713 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
2786 /* 6715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2787 /* 6718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2788 /* 6724 */ GIR_RootConstrainSelectedInstOperands,
2789 /* 6725 */ // GIR_Coverage, 304,
2790 /* 6725 */ GIR_EraseRootFromParent_Done,
2791 /* 6726 */ // Label 193: @6726
2792 /* 6726 */ GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(6818),
2793 /* 6731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2794 /* 6735 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 195*/ GIMT_Encode4(6776), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 408 //
2795 /* 6742 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2796 /* 6746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2797 /* 6750 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
2798 /* 6750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr),
2799 /* 6753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2800 /* 6755 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2801 /* 6757 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
2802 /* 6759 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2803 /* 6762 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2804 /* 6768 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2805 /* 6774 */ GIR_RootConstrainSelectedInstOperands,
2806 /* 6775 */ // GIR_Coverage, 408,
2807 /* 6775 */ GIR_EraseRootFromParent_Done,
2808 /* 6776 */ // Label 195: @6776
2809 /* 6776 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 196*/ GIMT_Encode4(6817), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 5996 //
2810 /* 6783 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2811 /* 6787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2812 /* 6791 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
2813 /* 6791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr),
2814 /* 6794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2815 /* 6796 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2816 /* 6798 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
2817 /* 6800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2818 /* 6803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2819 /* 6809 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2820 /* 6815 */ GIR_RootConstrainSelectedInstOperands,
2821 /* 6816 */ // GIR_Coverage, 5996,
2822 /* 6816 */ GIR_EraseRootFromParent_Done,
2823 /* 6817 */ // Label 196: @6817
2824 /* 6817 */ GIM_Reject,
2825 /* 6818 */ // Label 194: @6818
2826 /* 6818 */ GIM_Reject,
2827 /* 6819 */ // Label 105: @6819
2828 /* 6819 */ GIM_Reject,
2829 /* 6820 */ // Label 96: @6820
2830 /* 6820 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 197*/ GIMT_Encode4(6865), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 882 //
2831 /* 6827 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2832 /* 6830 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2833 /* 6833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2834 /* 6837 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2835 /* 6841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2836 /* 6845 */ // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
2837 /* 6845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv1i64),
2838 /* 6848 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2839 /* 6850 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
2840 /* 6852 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
2841 /* 6854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2842 /* 6857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2843 /* 6863 */ GIR_RootConstrainSelectedInstOperands,
2844 /* 6864 */ // GIR_Coverage, 882,
2845 /* 6864 */ GIR_EraseRootFromParent_Done,
2846 /* 6865 */ // Label 197: @6865
2847 /* 6865 */ GIM_Reject,
2848 /* 6866 */ // Label 97: @6866
2849 /* 6866 */ GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(7299),
2850 /* 6871 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
2851 /* 6874 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
2852 /* 6877 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2853 /* 6881 */ GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(7074),
2854 /* 6886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2855 /* 6890 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 200*/ GIMT_Encode4(6951), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6200 //
2856 /* 6897 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2857 /* 6901 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
2858 /* 6905 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2859 /* 6909 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2860 /* 6913 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2861 /* 6918 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2862 /* 6923 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2863 /* 6925 */ // (add:{ *:[v8i8] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2864 /* 6925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8),
2865 /* 6928 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2866 /* 6930 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
2867 /* 6932 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2868 /* 6936 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2869 /* 6940 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2870 /* 6943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2871 /* 6949 */ GIR_RootConstrainSelectedInstOperands,
2872 /* 6950 */ // GIR_Coverage, 6200,
2873 /* 6950 */ GIR_EraseRootFromParent_Done,
2874 /* 6951 */ // Label 200: @6951
2875 /* 6951 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 201*/ GIMT_Encode4(7012), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6206 //
2876 /* 6958 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2877 /* 6962 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
2878 /* 6966 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2879 /* 6970 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2880 /* 6974 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2881 /* 6979 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2882 /* 6984 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2883 /* 6986 */ // (add:{ *:[v8i8] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2884 /* 6986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8),
2885 /* 6989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2886 /* 6991 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
2887 /* 6993 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2888 /* 6997 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2889 /* 7001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2890 /* 7004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2891 /* 7010 */ GIR_RootConstrainSelectedInstOperands,
2892 /* 7011 */ // GIR_Coverage, 6206,
2893 /* 7011 */ GIR_EraseRootFromParent_Done,
2894 /* 7012 */ // Label 201: @7012
2895 /* 7012 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 202*/ GIMT_Encode4(7073), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6088 //
2896 /* 7019 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2897 /* 7023 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2898 /* 7027 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2899 /* 7031 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2900 /* 7035 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2901 /* 7040 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2902 /* 7045 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2903 /* 7047 */ // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2904 /* 7047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8),
2905 /* 7050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2906 /* 7052 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
2907 /* 7054 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2908 /* 7058 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2909 /* 7062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2910 /* 7065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2911 /* 7071 */ GIR_RootConstrainSelectedInstOperands,
2912 /* 7072 */ // GIR_Coverage, 6088,
2913 /* 7072 */ GIR_EraseRootFromParent_Done,
2914 /* 7073 */ // Label 202: @7073
2915 /* 7073 */ GIM_Reject,
2916 /* 7074 */ // Label 199: @7074
2917 /* 7074 */ GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(7298),
2918 /* 7079 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2919 /* 7083 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 204*/ GIMT_Encode4(7144), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1341 //
2920 /* 7090 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2921 /* 7094 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
2922 /* 7098 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2923 /* 7102 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2924 /* 7106 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2925 /* 7111 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2926 /* 7116 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2927 /* 7118 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2928 /* 7118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8),
2929 /* 7121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2930 /* 7123 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
2931 /* 7125 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2932 /* 7129 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2933 /* 7133 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2934 /* 7136 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2935 /* 7142 */ GIR_RootConstrainSelectedInstOperands,
2936 /* 7143 */ // GIR_Coverage, 1341,
2937 /* 7143 */ GIR_EraseRootFromParent_Done,
2938 /* 7144 */ // Label 204: @7144
2939 /* 7144 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 205*/ GIMT_Encode4(7205), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1347 //
2940 /* 7151 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2941 /* 7155 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
2942 /* 7159 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2943 /* 7163 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2944 /* 7167 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2945 /* 7172 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2946 /* 7177 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2947 /* 7179 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2948 /* 7179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8),
2949 /* 7182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2950 /* 7184 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
2951 /* 7186 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2952 /* 7190 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2953 /* 7194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2954 /* 7197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2955 /* 7203 */ GIR_RootConstrainSelectedInstOperands,
2956 /* 7204 */ // GIR_Coverage, 1347,
2957 /* 7204 */ GIR_EraseRootFromParent_Done,
2958 /* 7205 */ // Label 205: @7205
2959 /* 7205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 206*/ GIMT_Encode4(7266), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1007 //
2960 /* 7212 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2961 /* 7216 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2962 /* 7220 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
2963 /* 7224 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
2964 /* 7228 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2965 /* 7233 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2966 /* 7238 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2967 /* 7240 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2968 /* 7240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8),
2969 /* 7243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2970 /* 7245 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
2971 /* 7247 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2972 /* 7251 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2973 /* 7255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2974 /* 7258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2975 /* 7264 */ GIR_RootConstrainSelectedInstOperands,
2976 /* 7265 */ // GIR_Coverage, 1007,
2977 /* 7265 */ GIR_EraseRootFromParent_Done,
2978 /* 7266 */ // Label 206: @7266
2979 /* 7266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 207*/ GIMT_Encode4(7297), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 876 //
2980 /* 7273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2981 /* 7277 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
2982 /* 7277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i8),
2983 /* 7280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2984 /* 7282 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
2985 /* 7284 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
2986 /* 7286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2987 /* 7289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2988 /* 7295 */ GIR_RootConstrainSelectedInstOperands,
2989 /* 7296 */ // GIR_Coverage, 876,
2990 /* 7296 */ GIR_EraseRootFromParent_Done,
2991 /* 7297 */ // Label 207: @7297
2992 /* 7297 */ GIM_Reject,
2993 /* 7298 */ // Label 203: @7298
2994 /* 7298 */ GIM_Reject,
2995 /* 7299 */ // Label 198: @7299
2996 /* 7299 */ GIM_Reject,
2997 /* 7300 */ // Label 98: @7300
2998 /* 7300 */ GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(7799),
2999 /* 7305 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
3000 /* 7308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
3001 /* 7311 */ GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(7738),
3002 /* 7316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3003 /* 7320 */ GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(7513),
3004 /* 7325 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3005 /* 7329 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 211*/ GIMT_Encode4(7390), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6203 //
3006 /* 7336 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3007 /* 7340 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3008 /* 7344 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3009 /* 7348 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3010 /* 7352 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3011 /* 7357 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3012 /* 7362 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3013 /* 7364 */ // (add:{ *:[v16i8] } (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3014 /* 7364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8),
3015 /* 7367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3016 /* 7369 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3017 /* 7371 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3018 /* 7375 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3019 /* 7379 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3020 /* 7382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3021 /* 7388 */ GIR_RootConstrainSelectedInstOperands,
3022 /* 7389 */ // GIR_Coverage, 6203,
3023 /* 7389 */ GIR_EraseRootFromParent_Done,
3024 /* 7390 */ // Label 211: @7390
3025 /* 7390 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 212*/ GIMT_Encode4(7451), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6209 //
3026 /* 7397 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3027 /* 7401 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3028 /* 7405 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3029 /* 7409 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3030 /* 7413 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3031 /* 7418 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3032 /* 7423 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3033 /* 7425 */ // (add:{ *:[v16i8] } (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3034 /* 7425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8),
3035 /* 7428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3036 /* 7430 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3037 /* 7432 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3038 /* 7436 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3039 /* 7440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3040 /* 7443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3041 /* 7449 */ GIR_RootConstrainSelectedInstOperands,
3042 /* 7450 */ // GIR_Coverage, 6209,
3043 /* 7450 */ GIR_EraseRootFromParent_Done,
3044 /* 7451 */ // Label 212: @7451
3045 /* 7451 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 213*/ GIMT_Encode4(7512), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6091 //
3046 /* 7458 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3047 /* 7462 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3048 /* 7466 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3049 /* 7470 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3050 /* 7474 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3051 /* 7479 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3052 /* 7484 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3053 /* 7486 */ // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3054 /* 7486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8),
3055 /* 7489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3056 /* 7491 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3057 /* 7493 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3058 /* 7497 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3059 /* 7501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3060 /* 7504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3061 /* 7510 */ GIR_RootConstrainSelectedInstOperands,
3062 /* 7511 */ // GIR_Coverage, 6091,
3063 /* 7511 */ GIR_EraseRootFromParent_Done,
3064 /* 7512 */ // Label 213: @7512
3065 /* 7512 */ GIM_Reject,
3066 /* 7513 */ // Label 210: @7513
3067 /* 7513 */ GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(7737),
3068 /* 7518 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3069 /* 7522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 215*/ GIMT_Encode4(7583), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1344 //
3070 /* 7529 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3071 /* 7533 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3072 /* 7537 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3073 /* 7541 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3074 /* 7545 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3075 /* 7550 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3076 /* 7555 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3077 /* 7557 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3078 /* 7557 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8),
3079 /* 7560 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3080 /* 7562 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3081 /* 7564 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3082 /* 7568 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3083 /* 7572 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3084 /* 7575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3085 /* 7581 */ GIR_RootConstrainSelectedInstOperands,
3086 /* 7582 */ // GIR_Coverage, 1344,
3087 /* 7582 */ GIR_EraseRootFromParent_Done,
3088 /* 7583 */ // Label 215: @7583
3089 /* 7583 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 216*/ GIMT_Encode4(7644), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1350 //
3090 /* 7590 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3091 /* 7594 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3092 /* 7598 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3093 /* 7602 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3094 /* 7606 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3095 /* 7611 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3096 /* 7616 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3097 /* 7618 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3098 /* 7618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8),
3099 /* 7621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3100 /* 7623 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3101 /* 7625 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3102 /* 7629 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3103 /* 7633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3104 /* 7636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3105 /* 7642 */ GIR_RootConstrainSelectedInstOperands,
3106 /* 7643 */ // GIR_Coverage, 1350,
3107 /* 7643 */ GIR_EraseRootFromParent_Done,
3108 /* 7644 */ // Label 216: @7644
3109 /* 7644 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 217*/ GIMT_Encode4(7705), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1010 //
3110 /* 7651 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3111 /* 7655 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3112 /* 7659 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
3113 /* 7663 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
3114 /* 7667 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3115 /* 7672 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3116 /* 7677 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3117 /* 7679 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3118 /* 7679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8),
3119 /* 7682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3120 /* 7684 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3121 /* 7686 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3122 /* 7690 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3123 /* 7694 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3124 /* 7697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3125 /* 7703 */ GIR_RootConstrainSelectedInstOperands,
3126 /* 7704 */ // GIR_Coverage, 1010,
3127 /* 7704 */ GIR_EraseRootFromParent_Done,
3128 /* 7705 */ // Label 217: @7705
3129 /* 7705 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 218*/ GIMT_Encode4(7736), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 879 //
3130 /* 7712 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3131 /* 7716 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
3132 /* 7716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv16i8),
3133 /* 7719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3134 /* 7721 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3135 /* 7723 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3136 /* 7725 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3137 /* 7728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3138 /* 7734 */ GIR_RootConstrainSelectedInstOperands,
3139 /* 7735 */ // GIR_Coverage, 879,
3140 /* 7735 */ GIR_EraseRootFromParent_Done,
3141 /* 7736 */ // Label 218: @7736
3142 /* 7736 */ GIM_Reject,
3143 /* 7737 */ // Label 214: @7737
3144 /* 7737 */ GIM_Reject,
3145 /* 7738 */ // Label 209: @7738
3146 /* 7738 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 219*/ GIMT_Encode4(7798), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3885 //
3147 /* 7745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3148 /* 7749 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3149 /* 7753 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3150 /* 7757 */ // (add:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
3151 /* 7757 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3152 /* 7760 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
3153 /* 7764 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3154 /* 7769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi8),
3155 /* 7772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
3156 /* 7774 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
3157 /* 7776 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
3158 /* 7778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
3159 /* 7781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3160 /* 7787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3161 /* 7793 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3162 /* 7796 */ GIR_RootConstrainSelectedInstOperands,
3163 /* 7797 */ // GIR_Coverage, 3885,
3164 /* 7797 */ GIR_EraseRootFromParent_Done,
3165 /* 7798 */ // Label 219: @7798
3166 /* 7798 */ GIM_Reject,
3167 /* 7799 */ // Label 208: @7799
3168 /* 7799 */ GIM_Reject,
3169 /* 7800 */ // Label 99: @7800
3170 /* 7800 */ GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(8233),
3171 /* 7805 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
3172 /* 7808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
3173 /* 7811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3174 /* 7815 */ GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(8008),
3175 /* 7820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3176 /* 7824 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 222*/ GIMT_Encode4(7885), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6201 //
3177 /* 7831 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3178 /* 7835 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3179 /* 7839 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3180 /* 7843 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3181 /* 7847 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3182 /* 7852 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3183 /* 7857 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3184 /* 7859 */ // (add:{ *:[v4i16] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3185 /* 7859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16),
3186 /* 7862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3187 /* 7864 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3188 /* 7866 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3189 /* 7870 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3190 /* 7874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3191 /* 7877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3192 /* 7883 */ GIR_RootConstrainSelectedInstOperands,
3193 /* 7884 */ // GIR_Coverage, 6201,
3194 /* 7884 */ GIR_EraseRootFromParent_Done,
3195 /* 7885 */ // Label 222: @7885
3196 /* 7885 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 223*/ GIMT_Encode4(7946), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6207 //
3197 /* 7892 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3198 /* 7896 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3199 /* 7900 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3200 /* 7904 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3201 /* 7908 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3202 /* 7913 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3203 /* 7918 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3204 /* 7920 */ // (add:{ *:[v4i16] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3205 /* 7920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16),
3206 /* 7923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3207 /* 7925 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3208 /* 7927 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3209 /* 7931 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3210 /* 7935 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3211 /* 7938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3212 /* 7944 */ GIR_RootConstrainSelectedInstOperands,
3213 /* 7945 */ // GIR_Coverage, 6207,
3214 /* 7945 */ GIR_EraseRootFromParent_Done,
3215 /* 7946 */ // Label 223: @7946
3216 /* 7946 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 224*/ GIMT_Encode4(8007), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6089 //
3217 /* 7953 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3218 /* 7957 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3219 /* 7961 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3220 /* 7965 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3221 /* 7969 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3222 /* 7974 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3223 /* 7979 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3224 /* 7981 */ // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3225 /* 7981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16),
3226 /* 7984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3227 /* 7986 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3228 /* 7988 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3229 /* 7992 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3230 /* 7996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3231 /* 7999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3232 /* 8005 */ GIR_RootConstrainSelectedInstOperands,
3233 /* 8006 */ // GIR_Coverage, 6089,
3234 /* 8006 */ GIR_EraseRootFromParent_Done,
3235 /* 8007 */ // Label 224: @8007
3236 /* 8007 */ GIM_Reject,
3237 /* 8008 */ // Label 221: @8008
3238 /* 8008 */ GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(8232),
3239 /* 8013 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3240 /* 8017 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 226*/ GIMT_Encode4(8078), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1342 //
3241 /* 8024 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3242 /* 8028 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3243 /* 8032 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3244 /* 8036 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3245 /* 8040 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3246 /* 8045 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3247 /* 8050 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3248 /* 8052 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3249 /* 8052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16),
3250 /* 8055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3251 /* 8057 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3252 /* 8059 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3253 /* 8063 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3254 /* 8067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3255 /* 8070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3256 /* 8076 */ GIR_RootConstrainSelectedInstOperands,
3257 /* 8077 */ // GIR_Coverage, 1342,
3258 /* 8077 */ GIR_EraseRootFromParent_Done,
3259 /* 8078 */ // Label 226: @8078
3260 /* 8078 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 227*/ GIMT_Encode4(8139), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1348 //
3261 /* 8085 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3262 /* 8089 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3263 /* 8093 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3264 /* 8097 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3265 /* 8101 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3266 /* 8106 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3267 /* 8111 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3268 /* 8113 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3269 /* 8113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16),
3270 /* 8116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3271 /* 8118 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3272 /* 8120 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3273 /* 8124 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3274 /* 8128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3275 /* 8131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3276 /* 8137 */ GIR_RootConstrainSelectedInstOperands,
3277 /* 8138 */ // GIR_Coverage, 1348,
3278 /* 8138 */ GIR_EraseRootFromParent_Done,
3279 /* 8139 */ // Label 227: @8139
3280 /* 8139 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 228*/ GIMT_Encode4(8200), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1008 //
3281 /* 8146 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3282 /* 8150 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3283 /* 8154 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3284 /* 8158 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3285 /* 8162 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3286 /* 8167 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3287 /* 8172 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3288 /* 8174 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3289 /* 8174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16),
3290 /* 8177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3291 /* 8179 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3292 /* 8181 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3293 /* 8185 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3294 /* 8189 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3295 /* 8192 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3296 /* 8198 */ GIR_RootConstrainSelectedInstOperands,
3297 /* 8199 */ // GIR_Coverage, 1008,
3298 /* 8199 */ GIR_EraseRootFromParent_Done,
3299 /* 8200 */ // Label 228: @8200
3300 /* 8200 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 229*/ GIMT_Encode4(8231), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 877 //
3301 /* 8207 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3302 /* 8211 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3303 /* 8211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i16),
3304 /* 8214 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3305 /* 8216 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3306 /* 8218 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3307 /* 8220 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3308 /* 8223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3309 /* 8229 */ GIR_RootConstrainSelectedInstOperands,
3310 /* 8230 */ // GIR_Coverage, 877,
3311 /* 8230 */ GIR_EraseRootFromParent_Done,
3312 /* 8231 */ // Label 229: @8231
3313 /* 8231 */ GIM_Reject,
3314 /* 8232 */ // Label 225: @8232
3315 /* 8232 */ GIM_Reject,
3316 /* 8233 */ // Label 220: @8233
3317 /* 8233 */ GIM_Reject,
3318 /* 8234 */ // Label 100: @8234
3319 /* 8234 */ GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(9668),
3320 /* 8239 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
3321 /* 8242 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
3322 /* 8245 */ GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(9607),
3323 /* 8250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3324 /* 8254 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 232*/ GIMT_Encode4(8321), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 894 //
3325 /* 8261 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3326 /* 8265 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3327 /* 8269 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3328 /* 8273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3329 /* 8278 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3330 /* 8282 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3331 /* 8286 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3332 /* 8290 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3333 /* 8295 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3334 /* 8297 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3335 /* 8297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3336 /* 8300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3337 /* 8302 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3338 /* 8306 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3339 /* 8310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3340 /* 8313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3341 /* 8319 */ GIR_RootConstrainSelectedInstOperands,
3342 /* 8320 */ // GIR_Coverage, 894,
3343 /* 8320 */ GIR_EraseRootFromParent_Done,
3344 /* 8321 */ // Label 232: @8321
3345 /* 8321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 233*/ GIMT_Encode4(8388), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 893 //
3346 /* 8328 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3347 /* 8332 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3348 /* 8336 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3349 /* 8340 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3350 /* 8345 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3351 /* 8349 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3352 /* 8353 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3353 /* 8357 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3354 /* 8362 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3355 /* 8364 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3356 /* 8364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3357 /* 8367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3358 /* 8369 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3359 /* 8373 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3360 /* 8377 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3361 /* 8380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3362 /* 8386 */ GIR_RootConstrainSelectedInstOperands,
3363 /* 8387 */ // GIR_Coverage, 893,
3364 /* 8387 */ GIR_EraseRootFromParent_Done,
3365 /* 8388 */ // Label 233: @8388
3366 /* 8388 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 234*/ GIMT_Encode4(8455), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 888 //
3367 /* 8395 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3368 /* 8399 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3369 /* 8403 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3370 /* 8407 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3371 /* 8412 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3372 /* 8416 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
3373 /* 8420 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3374 /* 8424 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3375 /* 8429 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3376 /* 8431 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3377 /* 8431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv8i16),
3378 /* 8434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3379 /* 8436 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3380 /* 8440 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3381 /* 8444 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3382 /* 8447 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3383 /* 8453 */ GIR_RootConstrainSelectedInstOperands,
3384 /* 8454 */ // GIR_Coverage, 888,
3385 /* 8454 */ GIR_EraseRootFromParent_Done,
3386 /* 8455 */ // Label 234: @8455
3387 /* 8455 */ GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(8611),
3388 /* 8460 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3389 /* 8464 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 236*/ GIMT_Encode4(8537), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6212 //
3390 /* 8471 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3391 /* 8475 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3392 /* 8479 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3393 /* 8483 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3394 /* 8487 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
3395 /* 8491 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3396 /* 8495 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3397 /* 8499 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3398 /* 8504 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3399 /* 8509 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3400 /* 8511 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3401 /* 8511 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16),
3402 /* 8514 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3403 /* 8516 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3404 /* 8518 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3405 /* 8522 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3406 /* 8526 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3407 /* 8529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3408 /* 8535 */ GIR_RootConstrainSelectedInstOperands,
3409 /* 8536 */ // GIR_Coverage, 6212,
3410 /* 8536 */ GIR_EraseRootFromParent_Done,
3411 /* 8537 */ // Label 236: @8537
3412 /* 8537 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 237*/ GIMT_Encode4(8610), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6215 //
3413 /* 8544 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3414 /* 8548 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3415 /* 8552 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3416 /* 8556 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3417 /* 8560 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
3418 /* 8564 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3419 /* 8568 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3420 /* 8572 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3421 /* 8577 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3422 /* 8582 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3423 /* 8584 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3424 /* 8584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16),
3425 /* 8587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3426 /* 8589 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3427 /* 8591 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3428 /* 8595 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3429 /* 8599 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3430 /* 8602 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3431 /* 8608 */ GIR_RootConstrainSelectedInstOperands,
3432 /* 8609 */ // GIR_Coverage, 6215,
3433 /* 8609 */ GIR_EraseRootFromParent_Done,
3434 /* 8610 */ // Label 237: @8610
3435 /* 8610 */ GIM_Reject,
3436 /* 8611 */ // Label 235: @8611
3437 /* 8611 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 238*/ GIMT_Encode4(8678), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 892 //
3438 /* 8618 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3439 /* 8622 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3440 /* 8626 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3441 /* 8630 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3442 /* 8635 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3443 /* 8639 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3444 /* 8643 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3445 /* 8647 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3446 /* 8652 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3447 /* 8654 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3448 /* 8654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3449 /* 8657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3450 /* 8659 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3451 /* 8663 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3452 /* 8667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3453 /* 8670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3454 /* 8676 */ GIR_RootConstrainSelectedInstOperands,
3455 /* 8677 */ // GIR_Coverage, 892,
3456 /* 8677 */ GIR_EraseRootFromParent_Done,
3457 /* 8678 */ // Label 238: @8678
3458 /* 8678 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 239*/ GIMT_Encode4(8745), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 891 //
3459 /* 8685 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3460 /* 8689 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3461 /* 8693 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3462 /* 8697 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3463 /* 8702 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3464 /* 8706 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3465 /* 8710 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3466 /* 8714 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3467 /* 8719 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3468 /* 8721 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3469 /* 8721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
3470 /* 8724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3471 /* 8726 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3472 /* 8730 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3473 /* 8734 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3474 /* 8737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3475 /* 8743 */ GIR_RootConstrainSelectedInstOperands,
3476 /* 8744 */ // GIR_Coverage, 891,
3477 /* 8744 */ GIR_EraseRootFromParent_Done,
3478 /* 8745 */ // Label 239: @8745
3479 /* 8745 */ GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(8901),
3480 /* 8750 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3481 /* 8754 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 241*/ GIMT_Encode4(8827), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1353 //
3482 /* 8761 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3483 /* 8765 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3484 /* 8769 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3485 /* 8773 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3486 /* 8777 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
3487 /* 8781 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3488 /* 8785 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3489 /* 8789 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3490 /* 8794 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3491 /* 8799 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3492 /* 8801 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3493 /* 8801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16),
3494 /* 8804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3495 /* 8806 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3496 /* 8808 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3497 /* 8812 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3498 /* 8816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3499 /* 8819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3500 /* 8825 */ GIR_RootConstrainSelectedInstOperands,
3501 /* 8826 */ // GIR_Coverage, 1353,
3502 /* 8826 */ GIR_EraseRootFromParent_Done,
3503 /* 8827 */ // Label 241: @8827
3504 /* 8827 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 242*/ GIMT_Encode4(8900), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1356 //
3505 /* 8834 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3506 /* 8838 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3507 /* 8842 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3508 /* 8846 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3509 /* 8850 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
3510 /* 8854 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
3511 /* 8858 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
3512 /* 8862 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3513 /* 8867 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3514 /* 8872 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3515 /* 8874 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3516 /* 8874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16),
3517 /* 8877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3518 /* 8879 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3519 /* 8881 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3520 /* 8885 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3521 /* 8889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3522 /* 8892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3523 /* 8898 */ GIR_RootConstrainSelectedInstOperands,
3524 /* 8899 */ // GIR_Coverage, 1356,
3525 /* 8899 */ GIR_EraseRootFromParent_Done,
3526 /* 8900 */ // Label 242: @8900
3527 /* 8900 */ GIM_Reject,
3528 /* 8901 */ // Label 240: @8901
3529 /* 8901 */ GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(9238),
3530 /* 8906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3531 /* 8910 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 244*/ GIMT_Encode4(8971), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6204 //
3532 /* 8917 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3533 /* 8921 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3534 /* 8925 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3535 /* 8929 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3536 /* 8933 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3537 /* 8938 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3538 /* 8943 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3539 /* 8945 */ // (add:{ *:[v8i16] } (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3540 /* 8945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16),
3541 /* 8948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3542 /* 8950 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3543 /* 8952 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3544 /* 8956 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3545 /* 8960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3546 /* 8963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3547 /* 8969 */ GIR_RootConstrainSelectedInstOperands,
3548 /* 8970 */ // GIR_Coverage, 6204,
3549 /* 8970 */ GIR_EraseRootFromParent_Done,
3550 /* 8971 */ // Label 244: @8971
3551 /* 8971 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 245*/ GIMT_Encode4(9032), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6210 //
3552 /* 8978 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3553 /* 8982 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3554 /* 8986 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3555 /* 8990 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3556 /* 8994 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3557 /* 8999 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3558 /* 9004 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3559 /* 9006 */ // (add:{ *:[v8i16] } (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3560 /* 9006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16),
3561 /* 9009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3562 /* 9011 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3563 /* 9013 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3564 /* 9017 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3565 /* 9021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3566 /* 9024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3567 /* 9030 */ GIR_RootConstrainSelectedInstOperands,
3568 /* 9031 */ // GIR_Coverage, 6210,
3569 /* 9031 */ GIR_EraseRootFromParent_Done,
3570 /* 9032 */ // Label 245: @9032
3571 /* 9032 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 246*/ GIMT_Encode4(9093), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6092 //
3572 /* 9039 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3573 /* 9043 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3574 /* 9047 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3575 /* 9051 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3576 /* 9055 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3577 /* 9060 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3578 /* 9065 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3579 /* 9067 */ // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3580 /* 9067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16),
3581 /* 9070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3582 /* 9072 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3583 /* 9074 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3584 /* 9078 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3585 /* 9082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3586 /* 9085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3587 /* 9091 */ GIR_RootConstrainSelectedInstOperands,
3588 /* 9092 */ // GIR_Coverage, 6092,
3589 /* 9092 */ GIR_EraseRootFromParent_Done,
3590 /* 9093 */ // Label 246: @9093
3591 /* 9093 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 247*/ GIMT_Encode4(9141), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6065 //
3592 /* 9100 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3593 /* 9104 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3594 /* 9108 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3595 /* 9112 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3596 /* 9117 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3597 /* 9119 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3598 /* 9119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3599 /* 9122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3600 /* 9124 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
3601 /* 9126 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3602 /* 9130 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3603 /* 9133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3604 /* 9139 */ GIR_RootConstrainSelectedInstOperands,
3605 /* 9140 */ // GIR_Coverage, 6065,
3606 /* 9140 */ GIR_EraseRootFromParent_Done,
3607 /* 9141 */ // Label 247: @9141
3608 /* 9141 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 248*/ GIMT_Encode4(9189), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6061 //
3609 /* 9148 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3610 /* 9152 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3611 /* 9156 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3612 /* 9160 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3613 /* 9165 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3614 /* 9167 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3615 /* 9167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16),
3616 /* 9170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3617 /* 9172 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
3618 /* 9174 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3619 /* 9178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3620 /* 9181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3621 /* 9187 */ GIR_RootConstrainSelectedInstOperands,
3622 /* 9188 */ // GIR_Coverage, 6061,
3623 /* 9188 */ GIR_EraseRootFromParent_Done,
3624 /* 9189 */ // Label 248: @9189
3625 /* 9189 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 249*/ GIMT_Encode4(9237), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6064 //
3626 /* 9196 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3627 /* 9200 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3628 /* 9204 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3629 /* 9208 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3630 /* 9213 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3631 /* 9215 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3632 /* 9215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3633 /* 9218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3634 /* 9220 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
3635 /* 9222 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3636 /* 9226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3637 /* 9229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3638 /* 9235 */ GIR_RootConstrainSelectedInstOperands,
3639 /* 9236 */ // GIR_Coverage, 6064,
3640 /* 9236 */ GIR_EraseRootFromParent_Done,
3641 /* 9237 */ // Label 249: @9237
3642 /* 9237 */ GIM_Reject,
3643 /* 9238 */ // Label 243: @9238
3644 /* 9238 */ GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(9606),
3645 /* 9243 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3646 /* 9247 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 251*/ GIMT_Encode4(9308), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1345 //
3647 /* 9254 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3648 /* 9258 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3649 /* 9262 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3650 /* 9266 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3651 /* 9270 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3652 /* 9275 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3653 /* 9280 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3654 /* 9282 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3655 /* 9282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16),
3656 /* 9285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3657 /* 9287 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3658 /* 9289 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3659 /* 9293 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3660 /* 9297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3661 /* 9300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3662 /* 9306 */ GIR_RootConstrainSelectedInstOperands,
3663 /* 9307 */ // GIR_Coverage, 1345,
3664 /* 9307 */ GIR_EraseRootFromParent_Done,
3665 /* 9308 */ // Label 251: @9308
3666 /* 9308 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 252*/ GIMT_Encode4(9369), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1351 //
3667 /* 9315 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3668 /* 9319 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3669 /* 9323 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3670 /* 9327 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3671 /* 9331 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3672 /* 9336 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3673 /* 9341 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3674 /* 9343 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3675 /* 9343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16),
3676 /* 9346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3677 /* 9348 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3678 /* 9350 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3679 /* 9354 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3680 /* 9358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3681 /* 9361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3682 /* 9367 */ GIR_RootConstrainSelectedInstOperands,
3683 /* 9368 */ // GIR_Coverage, 1351,
3684 /* 9368 */ GIR_EraseRootFromParent_Done,
3685 /* 9369 */ // Label 252: @9369
3686 /* 9369 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 253*/ GIMT_Encode4(9430), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1011 //
3687 /* 9376 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3688 /* 9380 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3689 /* 9384 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
3690 /* 9388 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
3691 /* 9392 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3692 /* 9397 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3693 /* 9402 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3694 /* 9404 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3695 /* 9404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16),
3696 /* 9407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3697 /* 9409 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3698 /* 9411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3699 /* 9415 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3700 /* 9419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3701 /* 9422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3702 /* 9428 */ GIR_RootConstrainSelectedInstOperands,
3703 /* 9429 */ // GIR_Coverage, 1011,
3704 /* 9429 */ GIR_EraseRootFromParent_Done,
3705 /* 9430 */ // Label 253: @9430
3706 /* 9430 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 254*/ GIMT_Encode4(9478), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 907 //
3707 /* 9437 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3708 /* 9441 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3709 /* 9445 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3710 /* 9449 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3711 /* 9454 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3712 /* 9456 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3713 /* 9456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3714 /* 9459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3715 /* 9461 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3716 /* 9463 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3717 /* 9467 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3718 /* 9470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3719 /* 9476 */ GIR_RootConstrainSelectedInstOperands,
3720 /* 9477 */ // GIR_Coverage, 907,
3721 /* 9477 */ GIR_EraseRootFromParent_Done,
3722 /* 9478 */ // Label 254: @9478
3723 /* 9478 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 255*/ GIMT_Encode4(9526), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 903 //
3724 /* 9485 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3725 /* 9489 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3726 /* 9493 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3727 /* 9497 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3728 /* 9502 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3729 /* 9504 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3730 /* 9504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16),
3731 /* 9507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3732 /* 9509 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3733 /* 9511 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3734 /* 9515 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3735 /* 9518 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3736 /* 9524 */ GIR_RootConstrainSelectedInstOperands,
3737 /* 9525 */ // GIR_Coverage, 903,
3738 /* 9525 */ GIR_EraseRootFromParent_Done,
3739 /* 9526 */ // Label 255: @9526
3740 /* 9526 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 256*/ GIMT_Encode4(9574), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 906 //
3741 /* 9533 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3742 /* 9537 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3743 /* 9541 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
3744 /* 9545 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3745 /* 9550 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3746 /* 9552 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
3747 /* 9552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
3748 /* 9555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3749 /* 9557 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3750 /* 9559 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3751 /* 9563 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3752 /* 9566 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3753 /* 9572 */ GIR_RootConstrainSelectedInstOperands,
3754 /* 9573 */ // GIR_Coverage, 906,
3755 /* 9573 */ GIR_EraseRootFromParent_Done,
3756 /* 9574 */ // Label 256: @9574
3757 /* 9574 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 257*/ GIMT_Encode4(9605), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 880 //
3758 /* 9581 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3759 /* 9585 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
3760 /* 9585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i16),
3761 /* 9588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3762 /* 9590 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3763 /* 9592 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3764 /* 9594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3765 /* 9597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3766 /* 9603 */ GIR_RootConstrainSelectedInstOperands,
3767 /* 9604 */ // GIR_Coverage, 880,
3768 /* 9604 */ GIR_EraseRootFromParent_Done,
3769 /* 9605 */ // Label 257: @9605
3770 /* 9605 */ GIM_Reject,
3771 /* 9606 */ // Label 250: @9606
3772 /* 9606 */ GIM_Reject,
3773 /* 9607 */ // Label 231: @9607
3774 /* 9607 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 258*/ GIMT_Encode4(9667), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3889 //
3775 /* 9614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3776 /* 9618 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3777 /* 9622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
3778 /* 9626 */ // (add:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
3779 /* 9626 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
3780 /* 9629 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
3781 /* 9633 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
3782 /* 9638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi16),
3783 /* 9641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
3784 /* 9643 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
3785 /* 9645 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
3786 /* 9647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
3787 /* 9650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3788 /* 9656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3789 /* 9662 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
3790 /* 9665 */ GIR_RootConstrainSelectedInstOperands,
3791 /* 9666 */ // GIR_Coverage, 3889,
3792 /* 9666 */ GIR_EraseRootFromParent_Done,
3793 /* 9667 */ // Label 258: @9667
3794 /* 9667 */ GIM_Reject,
3795 /* 9668 */ // Label 230: @9668
3796 /* 9668 */ GIM_Reject,
3797 /* 9669 */ // Label 101: @9669
3798 /* 9669 */ GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(10102),
3799 /* 9674 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
3800 /* 9677 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
3801 /* 9680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3802 /* 9684 */ GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(9877),
3803 /* 9689 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3804 /* 9693 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 261*/ GIMT_Encode4(9754), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6202 //
3805 /* 9700 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3806 /* 9704 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3807 /* 9708 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3808 /* 9712 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3809 /* 9716 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3810 /* 9721 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3811 /* 9726 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3812 /* 9728 */ // (add:{ *:[v2i32] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3813 /* 9728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32),
3814 /* 9731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3815 /* 9733 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3816 /* 9735 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3817 /* 9739 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3818 /* 9743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3819 /* 9746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3820 /* 9752 */ GIR_RootConstrainSelectedInstOperands,
3821 /* 9753 */ // GIR_Coverage, 6202,
3822 /* 9753 */ GIR_EraseRootFromParent_Done,
3823 /* 9754 */ // Label 261: @9754
3824 /* 9754 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 262*/ GIMT_Encode4(9815), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6208 //
3825 /* 9761 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3826 /* 9765 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3827 /* 9769 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3828 /* 9773 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3829 /* 9777 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3830 /* 9782 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3831 /* 9787 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3832 /* 9789 */ // (add:{ *:[v2i32] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3833 /* 9789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32),
3834 /* 9792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3835 /* 9794 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3836 /* 9796 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3837 /* 9800 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3838 /* 9804 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3839 /* 9807 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3840 /* 9813 */ GIR_RootConstrainSelectedInstOperands,
3841 /* 9814 */ // GIR_Coverage, 6208,
3842 /* 9814 */ GIR_EraseRootFromParent_Done,
3843 /* 9815 */ // Label 262: @9815
3844 /* 9815 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 263*/ GIMT_Encode4(9876), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6090 //
3845 /* 9822 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3846 /* 9826 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3847 /* 9830 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3848 /* 9834 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3849 /* 9838 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3850 /* 9843 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3851 /* 9848 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3852 /* 9850 */ // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3853 /* 9850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32),
3854 /* 9853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3855 /* 9855 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3856 /* 9857 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3857 /* 9861 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3858 /* 9865 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3859 /* 9868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3860 /* 9874 */ GIR_RootConstrainSelectedInstOperands,
3861 /* 9875 */ // GIR_Coverage, 6090,
3862 /* 9875 */ GIR_EraseRootFromParent_Done,
3863 /* 9876 */ // Label 263: @9876
3864 /* 9876 */ GIM_Reject,
3865 /* 9877 */ // Label 260: @9877
3866 /* 9877 */ GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(10101),
3867 /* 9882 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3868 /* 9886 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 265*/ GIMT_Encode4(9947), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1343 //
3869 /* 9893 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3870 /* 9897 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3871 /* 9901 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3872 /* 9905 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3873 /* 9909 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3874 /* 9914 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3875 /* 9919 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3876 /* 9921 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3877 /* 9921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32),
3878 /* 9924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3879 /* 9926 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3880 /* 9928 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3881 /* 9932 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3882 /* 9936 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3883 /* 9939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3884 /* 9945 */ GIR_RootConstrainSelectedInstOperands,
3885 /* 9946 */ // GIR_Coverage, 1343,
3886 /* 9946 */ GIR_EraseRootFromParent_Done,
3887 /* 9947 */ // Label 265: @9947
3888 /* 9947 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 266*/ GIMT_Encode4(10008), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1349 //
3889 /* 9954 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3890 /* 9958 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3891 /* 9962 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3892 /* 9966 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3893 /* 9970 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3894 /* 9975 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3895 /* 9980 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3896 /* 9982 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3897 /* 9982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32),
3898 /* 9985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3899 /* 9987 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3900 /* 9989 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3901 /* 9993 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3902 /* 9997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3903 /* 10000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3904 /* 10006 */ GIR_RootConstrainSelectedInstOperands,
3905 /* 10007 */ // GIR_Coverage, 1349,
3906 /* 10007 */ GIR_EraseRootFromParent_Done,
3907 /* 10008 */ // Label 266: @10008
3908 /* 10008 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 267*/ GIMT_Encode4(10069), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1009 //
3909 /* 10015 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3910 /* 10019 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3911 /* 10023 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3912 /* 10027 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
3913 /* 10031 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3914 /* 10036 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3915 /* 10041 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3916 /* 10043 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3917 /* 10043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32),
3918 /* 10046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3919 /* 10048 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3920 /* 10050 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3921 /* 10054 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3922 /* 10058 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3923 /* 10061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3924 /* 10067 */ GIR_RootConstrainSelectedInstOperands,
3925 /* 10068 */ // GIR_Coverage, 1009,
3926 /* 10068 */ GIR_EraseRootFromParent_Done,
3927 /* 10069 */ // Label 267: @10069
3928 /* 10069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 268*/ GIMT_Encode4(10100), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 878 //
3929 /* 10076 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3930 /* 10080 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3931 /* 10080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i32),
3932 /* 10083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3933 /* 10085 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3934 /* 10087 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3935 /* 10089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3936 /* 10092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3937 /* 10098 */ GIR_RootConstrainSelectedInstOperands,
3938 /* 10099 */ // GIR_Coverage, 878,
3939 /* 10099 */ GIR_EraseRootFromParent_Done,
3940 /* 10100 */ // Label 268: @10100
3941 /* 10100 */ GIM_Reject,
3942 /* 10101 */ // Label 264: @10101
3943 /* 10101 */ GIM_Reject,
3944 /* 10102 */ // Label 259: @10102
3945 /* 10102 */ GIM_Reject,
3946 /* 10103 */ // Label 102: @10103
3947 /* 10103 */ GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(11537),
3948 /* 10108 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3949 /* 10111 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
3950 /* 10114 */ GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(11476),
3951 /* 10119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3952 /* 10123 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 271*/ GIMT_Encode4(10190), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 898 //
3953 /* 10130 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3954 /* 10134 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3955 /* 10138 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3956 /* 10142 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3957 /* 10147 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3958 /* 10151 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3959 /* 10155 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3960 /* 10159 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3961 /* 10164 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3962 /* 10166 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3963 /* 10166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
3964 /* 10169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3965 /* 10171 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3966 /* 10175 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3967 /* 10179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3968 /* 10182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3969 /* 10188 */ GIR_RootConstrainSelectedInstOperands,
3970 /* 10189 */ // GIR_Coverage, 898,
3971 /* 10189 */ GIR_EraseRootFromParent_Done,
3972 /* 10190 */ // Label 271: @10190
3973 /* 10190 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 272*/ GIMT_Encode4(10257), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 897 //
3974 /* 10197 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3975 /* 10201 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3976 /* 10205 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3977 /* 10209 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3978 /* 10214 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3979 /* 10218 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3980 /* 10222 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3981 /* 10226 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3982 /* 10231 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3983 /* 10233 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3984 /* 10233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
3985 /* 10236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3986 /* 10238 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3987 /* 10242 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3988 /* 10246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3989 /* 10249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3990 /* 10255 */ GIR_RootConstrainSelectedInstOperands,
3991 /* 10256 */ // GIR_Coverage, 897,
3992 /* 10256 */ GIR_EraseRootFromParent_Done,
3993 /* 10257 */ // Label 272: @10257
3994 /* 10257 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 273*/ GIMT_Encode4(10324), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 889 //
3995 /* 10264 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3996 /* 10268 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3997 /* 10272 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3998 /* 10276 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3999 /* 10281 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4000 /* 10285 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
4001 /* 10289 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4002 /* 10293 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4003 /* 10298 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4004 /* 10300 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4005 /* 10300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv4i32),
4006 /* 10303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4007 /* 10305 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4008 /* 10309 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4009 /* 10313 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4010 /* 10316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4011 /* 10322 */ GIR_RootConstrainSelectedInstOperands,
4012 /* 10323 */ // GIR_Coverage, 889,
4013 /* 10323 */ GIR_EraseRootFromParent_Done,
4014 /* 10324 */ // Label 273: @10324
4015 /* 10324 */ GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(10480),
4016 /* 10329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4017 /* 10333 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 275*/ GIMT_Encode4(10406), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6213 //
4018 /* 10340 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4019 /* 10344 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4020 /* 10348 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4021 /* 10352 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4022 /* 10356 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
4023 /* 10360 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4024 /* 10364 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
4025 /* 10368 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4026 /* 10373 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4027 /* 10378 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4028 /* 10380 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4029 /* 10380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32),
4030 /* 10383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4031 /* 10385 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4032 /* 10387 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4033 /* 10391 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4034 /* 10395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4035 /* 10398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4036 /* 10404 */ GIR_RootConstrainSelectedInstOperands,
4037 /* 10405 */ // GIR_Coverage, 6213,
4038 /* 10405 */ GIR_EraseRootFromParent_Done,
4039 /* 10406 */ // Label 275: @10406
4040 /* 10406 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 276*/ GIMT_Encode4(10479), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6216 //
4041 /* 10413 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4042 /* 10417 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4043 /* 10421 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4044 /* 10425 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4045 /* 10429 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
4046 /* 10433 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4047 /* 10437 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
4048 /* 10441 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4049 /* 10446 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4050 /* 10451 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4051 /* 10453 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4052 /* 10453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32),
4053 /* 10456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4054 /* 10458 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4055 /* 10460 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4056 /* 10464 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4057 /* 10468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4058 /* 10471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4059 /* 10477 */ GIR_RootConstrainSelectedInstOperands,
4060 /* 10478 */ // GIR_Coverage, 6216,
4061 /* 10478 */ GIR_EraseRootFromParent_Done,
4062 /* 10479 */ // Label 276: @10479
4063 /* 10479 */ GIM_Reject,
4064 /* 10480 */ // Label 274: @10480
4065 /* 10480 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 277*/ GIMT_Encode4(10547), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 896 //
4066 /* 10487 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4067 /* 10491 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4068 /* 10495 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4069 /* 10499 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4070 /* 10504 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4071 /* 10508 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4072 /* 10512 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4073 /* 10516 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4074 /* 10521 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4075 /* 10523 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4076 /* 10523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
4077 /* 10526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4078 /* 10528 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4079 /* 10532 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4080 /* 10536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4081 /* 10539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4082 /* 10545 */ GIR_RootConstrainSelectedInstOperands,
4083 /* 10546 */ // GIR_Coverage, 896,
4084 /* 10546 */ GIR_EraseRootFromParent_Done,
4085 /* 10547 */ // Label 277: @10547
4086 /* 10547 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 278*/ GIMT_Encode4(10614), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 895 //
4087 /* 10554 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4088 /* 10558 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4089 /* 10562 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4090 /* 10566 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4091 /* 10571 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4092 /* 10575 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4093 /* 10579 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4094 /* 10583 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4095 /* 10588 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4096 /* 10590 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4097 /* 10590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
4098 /* 10593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4099 /* 10595 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4100 /* 10599 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4101 /* 10603 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4102 /* 10606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4103 /* 10612 */ GIR_RootConstrainSelectedInstOperands,
4104 /* 10613 */ // GIR_Coverage, 895,
4105 /* 10613 */ GIR_EraseRootFromParent_Done,
4106 /* 10614 */ // Label 278: @10614
4107 /* 10614 */ GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(10770),
4108 /* 10619 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4109 /* 10623 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 280*/ GIMT_Encode4(10696), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1354 //
4110 /* 10630 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4111 /* 10634 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4112 /* 10638 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4113 /* 10642 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4114 /* 10646 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
4115 /* 10650 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4116 /* 10654 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
4117 /* 10658 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4118 /* 10663 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4119 /* 10668 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4120 /* 10670 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4121 /* 10670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32),
4122 /* 10673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4123 /* 10675 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4124 /* 10677 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4125 /* 10681 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4126 /* 10685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4127 /* 10688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4128 /* 10694 */ GIR_RootConstrainSelectedInstOperands,
4129 /* 10695 */ // GIR_Coverage, 1354,
4130 /* 10695 */ GIR_EraseRootFromParent_Done,
4131 /* 10696 */ // Label 280: @10696
4132 /* 10696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 281*/ GIMT_Encode4(10769), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1357 //
4133 /* 10703 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4134 /* 10707 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4135 /* 10711 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4136 /* 10715 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4137 /* 10719 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
4138 /* 10723 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
4139 /* 10727 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
4140 /* 10731 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4141 /* 10736 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4142 /* 10741 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4143 /* 10743 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4144 /* 10743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32),
4145 /* 10746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4146 /* 10748 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4147 /* 10750 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4148 /* 10754 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4149 /* 10758 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4150 /* 10761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4151 /* 10767 */ GIR_RootConstrainSelectedInstOperands,
4152 /* 10768 */ // GIR_Coverage, 1357,
4153 /* 10768 */ GIR_EraseRootFromParent_Done,
4154 /* 10769 */ // Label 281: @10769
4155 /* 10769 */ GIM_Reject,
4156 /* 10770 */ // Label 279: @10770
4157 /* 10770 */ GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(11107),
4158 /* 10775 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4159 /* 10779 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 283*/ GIMT_Encode4(10840), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6205 //
4160 /* 10786 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4161 /* 10790 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
4162 /* 10794 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4163 /* 10798 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4164 /* 10802 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4165 /* 10807 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4166 /* 10812 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4167 /* 10814 */ // (add:{ *:[v4i32] } (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4168 /* 10814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32),
4169 /* 10817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4170 /* 10819 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4171 /* 10821 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4172 /* 10825 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4173 /* 10829 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4174 /* 10832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4175 /* 10838 */ GIR_RootConstrainSelectedInstOperands,
4176 /* 10839 */ // GIR_Coverage, 6205,
4177 /* 10839 */ GIR_EraseRootFromParent_Done,
4178 /* 10840 */ // Label 283: @10840
4179 /* 10840 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 284*/ GIMT_Encode4(10901), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6211 //
4180 /* 10847 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4181 /* 10851 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
4182 /* 10855 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4183 /* 10859 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4184 /* 10863 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4185 /* 10868 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4186 /* 10873 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4187 /* 10875 */ // (add:{ *:[v4i32] } (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4188 /* 10875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32),
4189 /* 10878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4190 /* 10880 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4191 /* 10882 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4192 /* 10886 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4193 /* 10890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4194 /* 10893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4195 /* 10899 */ GIR_RootConstrainSelectedInstOperands,
4196 /* 10900 */ // GIR_Coverage, 6211,
4197 /* 10900 */ GIR_EraseRootFromParent_Done,
4198 /* 10901 */ // Label 284: @10901
4199 /* 10901 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 285*/ GIMT_Encode4(10962), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6093 //
4200 /* 10908 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4201 /* 10912 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4202 /* 10916 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4203 /* 10920 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4204 /* 10924 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4205 /* 10929 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4206 /* 10934 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4207 /* 10936 */ // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4208 /* 10936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32),
4209 /* 10939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4210 /* 10941 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4211 /* 10943 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4212 /* 10947 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4213 /* 10951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4214 /* 10954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4215 /* 10960 */ GIR_RootConstrainSelectedInstOperands,
4216 /* 10961 */ // GIR_Coverage, 6093,
4217 /* 10961 */ GIR_EraseRootFromParent_Done,
4218 /* 10962 */ // Label 285: @10962
4219 /* 10962 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 286*/ GIMT_Encode4(11010), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6067 //
4220 /* 10969 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4221 /* 10973 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4222 /* 10977 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4223 /* 10981 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4224 /* 10986 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4225 /* 10988 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4226 /* 10988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
4227 /* 10991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4228 /* 10993 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4229 /* 10995 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4230 /* 10999 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4231 /* 11002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4232 /* 11008 */ GIR_RootConstrainSelectedInstOperands,
4233 /* 11009 */ // GIR_Coverage, 6067,
4234 /* 11009 */ GIR_EraseRootFromParent_Done,
4235 /* 11010 */ // Label 286: @11010
4236 /* 11010 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 287*/ GIMT_Encode4(11058), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6062 //
4237 /* 11017 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4238 /* 11021 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4239 /* 11025 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4240 /* 11029 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4241 /* 11034 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4242 /* 11036 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4243 /* 11036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32),
4244 /* 11039 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4245 /* 11041 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4246 /* 11043 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4247 /* 11047 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4248 /* 11050 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4249 /* 11056 */ GIR_RootConstrainSelectedInstOperands,
4250 /* 11057 */ // GIR_Coverage, 6062,
4251 /* 11057 */ GIR_EraseRootFromParent_Done,
4252 /* 11058 */ // Label 287: @11058
4253 /* 11058 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 288*/ GIMT_Encode4(11106), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6066 //
4254 /* 11065 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4255 /* 11069 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4256 /* 11073 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4257 /* 11077 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4258 /* 11082 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4259 /* 11084 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4260 /* 11084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
4261 /* 11087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4262 /* 11089 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4263 /* 11091 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4264 /* 11095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4265 /* 11098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4266 /* 11104 */ GIR_RootConstrainSelectedInstOperands,
4267 /* 11105 */ // GIR_Coverage, 6066,
4268 /* 11105 */ GIR_EraseRootFromParent_Done,
4269 /* 11106 */ // Label 288: @11106
4270 /* 11106 */ GIM_Reject,
4271 /* 11107 */ // Label 282: @11107
4272 /* 11107 */ GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(11475),
4273 /* 11112 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4274 /* 11116 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 290*/ GIMT_Encode4(11177), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1346 //
4275 /* 11123 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4276 /* 11127 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
4277 /* 11131 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4278 /* 11135 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4279 /* 11139 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4280 /* 11144 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4281 /* 11149 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4282 /* 11151 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4283 /* 11151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32),
4284 /* 11154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4285 /* 11156 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4286 /* 11158 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4287 /* 11162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4288 /* 11166 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4289 /* 11169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4290 /* 11175 */ GIR_RootConstrainSelectedInstOperands,
4291 /* 11176 */ // GIR_Coverage, 1346,
4292 /* 11176 */ GIR_EraseRootFromParent_Done,
4293 /* 11177 */ // Label 290: @11177
4294 /* 11177 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 291*/ GIMT_Encode4(11238), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1352 //
4295 /* 11184 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4296 /* 11188 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
4297 /* 11192 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4298 /* 11196 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4299 /* 11200 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4300 /* 11205 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4301 /* 11210 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4302 /* 11212 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4303 /* 11212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32),
4304 /* 11215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4305 /* 11217 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4306 /* 11219 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4307 /* 11223 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4308 /* 11227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4309 /* 11230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4310 /* 11236 */ GIR_RootConstrainSelectedInstOperands,
4311 /* 11237 */ // GIR_Coverage, 1352,
4312 /* 11237 */ GIR_EraseRootFromParent_Done,
4313 /* 11238 */ // Label 291: @11238
4314 /* 11238 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 292*/ GIMT_Encode4(11299), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1012 //
4315 /* 11245 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4316 /* 11249 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4317 /* 11253 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
4318 /* 11257 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
4319 /* 11261 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4320 /* 11266 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4321 /* 11271 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4322 /* 11273 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4323 /* 11273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32),
4324 /* 11276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4325 /* 11278 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4326 /* 11280 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4327 /* 11284 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4328 /* 11288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4329 /* 11291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4330 /* 11297 */ GIR_RootConstrainSelectedInstOperands,
4331 /* 11298 */ // GIR_Coverage, 1012,
4332 /* 11298 */ GIR_EraseRootFromParent_Done,
4333 /* 11299 */ // Label 292: @11299
4334 /* 11299 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 293*/ GIMT_Encode4(11347), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 909 //
4335 /* 11306 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4336 /* 11310 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4337 /* 11314 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4338 /* 11318 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4339 /* 11323 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4340 /* 11325 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4341 /* 11325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
4342 /* 11328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4343 /* 11330 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4344 /* 11332 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4345 /* 11336 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4346 /* 11339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4347 /* 11345 */ GIR_RootConstrainSelectedInstOperands,
4348 /* 11346 */ // GIR_Coverage, 909,
4349 /* 11346 */ GIR_EraseRootFromParent_Done,
4350 /* 11347 */ // Label 293: @11347
4351 /* 11347 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 294*/ GIMT_Encode4(11395), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 904 //
4352 /* 11354 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4353 /* 11358 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4354 /* 11362 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4355 /* 11366 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4356 /* 11371 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4357 /* 11373 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4358 /* 11373 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32),
4359 /* 11376 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4360 /* 11378 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4361 /* 11380 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4362 /* 11384 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4363 /* 11387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4364 /* 11393 */ GIR_RootConstrainSelectedInstOperands,
4365 /* 11394 */ // GIR_Coverage, 904,
4366 /* 11394 */ GIR_EraseRootFromParent_Done,
4367 /* 11395 */ // Label 294: @11395
4368 /* 11395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 295*/ GIMT_Encode4(11443), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 908 //
4369 /* 11402 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4370 /* 11406 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4371 /* 11410 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
4372 /* 11414 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4373 /* 11419 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4374 /* 11421 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4375 /* 11421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
4376 /* 11424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4377 /* 11426 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4378 /* 11428 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4379 /* 11432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4380 /* 11435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4381 /* 11441 */ GIR_RootConstrainSelectedInstOperands,
4382 /* 11442 */ // GIR_Coverage, 908,
4383 /* 11442 */ GIR_EraseRootFromParent_Done,
4384 /* 11443 */ // Label 295: @11443
4385 /* 11443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 296*/ GIMT_Encode4(11474), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 881 //
4386 /* 11450 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4387 /* 11454 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4388 /* 11454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i32),
4389 /* 11457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4390 /* 11459 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4391 /* 11461 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
4392 /* 11463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4393 /* 11466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4394 /* 11472 */ GIR_RootConstrainSelectedInstOperands,
4395 /* 11473 */ // GIR_Coverage, 881,
4396 /* 11473 */ GIR_EraseRootFromParent_Done,
4397 /* 11474 */ // Label 296: @11474
4398 /* 11474 */ GIM_Reject,
4399 /* 11475 */ // Label 289: @11475
4400 /* 11475 */ GIM_Reject,
4401 /* 11476 */ // Label 270: @11476
4402 /* 11476 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 297*/ GIMT_Encode4(11536), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3893 //
4403 /* 11483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4404 /* 11487 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4405 /* 11491 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4406 /* 11495 */ // (add:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
4407 /* 11495 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4408 /* 11498 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
4409 /* 11502 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4410 /* 11507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi32),
4411 /* 11510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
4412 /* 11512 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
4413 /* 11514 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
4414 /* 11516 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
4415 /* 11519 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4416 /* 11525 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4417 /* 11531 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4418 /* 11534 */ GIR_RootConstrainSelectedInstOperands,
4419 /* 11535 */ // GIR_Coverage, 3893,
4420 /* 11535 */ GIR_EraseRootFromParent_Done,
4421 /* 11536 */ // Label 297: @11536
4422 /* 11536 */ GIM_Reject,
4423 /* 11537 */ // Label 269: @11537
4424 /* 11537 */ GIM_Reject,
4425 /* 11538 */ // Label 103: @11538
4426 /* 11538 */ GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(12540),
4427 /* 11543 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
4428 /* 11546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
4429 /* 11549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4430 /* 11553 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 299*/ GIMT_Encode4(11620), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 902 //
4431 /* 11560 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4432 /* 11564 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4433 /* 11568 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4434 /* 11572 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4435 /* 11577 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4436 /* 11581 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4437 /* 11585 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4438 /* 11589 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4439 /* 11594 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4440 /* 11596 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4441 /* 11596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
4442 /* 11599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4443 /* 11601 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4444 /* 11605 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4445 /* 11609 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4446 /* 11612 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4447 /* 11618 */ GIR_RootConstrainSelectedInstOperands,
4448 /* 11619 */ // GIR_Coverage, 902,
4449 /* 11619 */ GIR_EraseRootFromParent_Done,
4450 /* 11620 */ // Label 299: @11620
4451 /* 11620 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 300*/ GIMT_Encode4(11687), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 901 //
4452 /* 11627 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4453 /* 11631 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4454 /* 11635 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4455 /* 11639 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4456 /* 11644 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4457 /* 11648 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4458 /* 11652 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4459 /* 11656 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4460 /* 11661 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4461 /* 11663 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4462 /* 11663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
4463 /* 11666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4464 /* 11668 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4465 /* 11672 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4466 /* 11676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4467 /* 11679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4468 /* 11685 */ GIR_RootConstrainSelectedInstOperands,
4469 /* 11686 */ // GIR_Coverage, 901,
4470 /* 11686 */ GIR_EraseRootFromParent_Done,
4471 /* 11687 */ // Label 300: @11687
4472 /* 11687 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 301*/ GIMT_Encode4(11754), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 890 //
4473 /* 11694 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4474 /* 11698 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4475 /* 11702 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4476 /* 11706 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4477 /* 11711 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4478 /* 11715 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
4479 /* 11719 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4480 /* 11723 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4481 /* 11728 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4482 /* 11730 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4483 /* 11730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv2i64),
4484 /* 11733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4485 /* 11735 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4486 /* 11739 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4487 /* 11743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4488 /* 11746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4489 /* 11752 */ GIR_RootConstrainSelectedInstOperands,
4490 /* 11753 */ // GIR_Coverage, 890,
4491 /* 11753 */ GIR_EraseRootFromParent_Done,
4492 /* 11754 */ // Label 301: @11754
4493 /* 11754 */ GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(11910),
4494 /* 11759 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4495 /* 11763 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 303*/ GIMT_Encode4(11836), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6214 //
4496 /* 11770 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4497 /* 11774 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4498 /* 11778 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4499 /* 11782 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4500 /* 11786 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
4501 /* 11790 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4502 /* 11794 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
4503 /* 11798 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4504 /* 11803 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4505 /* 11808 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4506 /* 11810 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4507 /* 11810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64),
4508 /* 11813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4509 /* 11815 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4510 /* 11817 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4511 /* 11821 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4512 /* 11825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4513 /* 11828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4514 /* 11834 */ GIR_RootConstrainSelectedInstOperands,
4515 /* 11835 */ // GIR_Coverage, 6214,
4516 /* 11835 */ GIR_EraseRootFromParent_Done,
4517 /* 11836 */ // Label 303: @11836
4518 /* 11836 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 304*/ GIMT_Encode4(11909), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6217 //
4519 /* 11843 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4520 /* 11847 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4521 /* 11851 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4522 /* 11855 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4523 /* 11859 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
4524 /* 11863 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4525 /* 11867 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
4526 /* 11871 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4527 /* 11876 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4528 /* 11881 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4529 /* 11883 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4530 /* 11883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64),
4531 /* 11886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4532 /* 11888 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4533 /* 11890 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4534 /* 11894 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4535 /* 11898 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4536 /* 11901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4537 /* 11907 */ GIR_RootConstrainSelectedInstOperands,
4538 /* 11908 */ // GIR_Coverage, 6217,
4539 /* 11908 */ GIR_EraseRootFromParent_Done,
4540 /* 11909 */ // Label 304: @11909
4541 /* 11909 */ GIM_Reject,
4542 /* 11910 */ // Label 302: @11910
4543 /* 11910 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 305*/ GIMT_Encode4(11977), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 900 //
4544 /* 11917 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4545 /* 11921 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4546 /* 11925 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4547 /* 11929 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4548 /* 11934 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4549 /* 11938 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4550 /* 11942 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4551 /* 11946 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4552 /* 11951 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4553 /* 11953 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4554 /* 11953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
4555 /* 11956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4556 /* 11958 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4557 /* 11962 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4558 /* 11966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4559 /* 11969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4560 /* 11975 */ GIR_RootConstrainSelectedInstOperands,
4561 /* 11976 */ // GIR_Coverage, 900,
4562 /* 11976 */ GIR_EraseRootFromParent_Done,
4563 /* 11977 */ // Label 305: @11977
4564 /* 11977 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 306*/ GIMT_Encode4(12044), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 899 //
4565 /* 11984 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4566 /* 11988 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4567 /* 11992 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4568 /* 11996 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4569 /* 12001 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4570 /* 12005 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4571 /* 12009 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4572 /* 12013 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4573 /* 12018 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4574 /* 12020 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4575 /* 12020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
4576 /* 12023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4577 /* 12025 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4578 /* 12029 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4579 /* 12033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4580 /* 12036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4581 /* 12042 */ GIR_RootConstrainSelectedInstOperands,
4582 /* 12043 */ // GIR_Coverage, 899,
4583 /* 12043 */ GIR_EraseRootFromParent_Done,
4584 /* 12044 */ // Label 306: @12044
4585 /* 12044 */ GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(12200),
4586 /* 12049 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4587 /* 12053 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 308*/ GIMT_Encode4(12126), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1355 //
4588 /* 12060 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4589 /* 12064 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4590 /* 12068 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4591 /* 12072 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4592 /* 12076 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
4593 /* 12080 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4594 /* 12084 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
4595 /* 12088 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4596 /* 12093 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4597 /* 12098 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4598 /* 12100 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4599 /* 12100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64),
4600 /* 12103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4601 /* 12105 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4602 /* 12107 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4603 /* 12111 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4604 /* 12115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4605 /* 12118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4606 /* 12124 */ GIR_RootConstrainSelectedInstOperands,
4607 /* 12125 */ // GIR_Coverage, 1355,
4608 /* 12125 */ GIR_EraseRootFromParent_Done,
4609 /* 12126 */ // Label 308: @12126
4610 /* 12126 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 309*/ GIMT_Encode4(12199), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1358 //
4611 /* 12133 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4612 /* 12137 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4613 /* 12141 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4614 /* 12145 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4615 /* 12149 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
4616 /* 12153 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
4617 /* 12157 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
4618 /* 12161 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4619 /* 12166 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4620 /* 12171 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4621 /* 12173 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4622 /* 12173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64),
4623 /* 12176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4624 /* 12178 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4625 /* 12180 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4626 /* 12184 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4627 /* 12188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4628 /* 12191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4629 /* 12197 */ GIR_RootConstrainSelectedInstOperands,
4630 /* 12198 */ // GIR_Coverage, 1358,
4631 /* 12198 */ GIR_EraseRootFromParent_Done,
4632 /* 12199 */ // Label 309: @12199
4633 /* 12199 */ GIM_Reject,
4634 /* 12200 */ // Label 307: @12200
4635 /* 12200 */ GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(12354),
4636 /* 12205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4637 /* 12209 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 311*/ GIMT_Encode4(12257), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6069 //
4638 /* 12216 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4639 /* 12220 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4640 /* 12224 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4641 /* 12228 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4642 /* 12233 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4643 /* 12235 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4644 /* 12235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
4645 /* 12238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4646 /* 12240 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4647 /* 12242 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4648 /* 12246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4649 /* 12249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4650 /* 12255 */ GIR_RootConstrainSelectedInstOperands,
4651 /* 12256 */ // GIR_Coverage, 6069,
4652 /* 12256 */ GIR_EraseRootFromParent_Done,
4653 /* 12257 */ // Label 311: @12257
4654 /* 12257 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 312*/ GIMT_Encode4(12305), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6063 //
4655 /* 12264 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4656 /* 12268 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4657 /* 12272 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4658 /* 12276 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4659 /* 12281 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4660 /* 12283 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4661 /* 12283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64),
4662 /* 12286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4663 /* 12288 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4664 /* 12290 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4665 /* 12294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4666 /* 12297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4667 /* 12303 */ GIR_RootConstrainSelectedInstOperands,
4668 /* 12304 */ // GIR_Coverage, 6063,
4669 /* 12304 */ GIR_EraseRootFromParent_Done,
4670 /* 12305 */ // Label 312: @12305
4671 /* 12305 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 313*/ GIMT_Encode4(12353), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6068 //
4672 /* 12312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4673 /* 12316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4674 /* 12320 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4675 /* 12324 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4676 /* 12329 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4677 /* 12331 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4678 /* 12331 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
4679 /* 12334 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4680 /* 12336 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4681 /* 12338 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4682 /* 12342 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4683 /* 12345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4684 /* 12351 */ GIR_RootConstrainSelectedInstOperands,
4685 /* 12352 */ // GIR_Coverage, 6068,
4686 /* 12352 */ GIR_EraseRootFromParent_Done,
4687 /* 12353 */ // Label 313: @12353
4688 /* 12353 */ GIM_Reject,
4689 /* 12354 */ // Label 310: @12354
4690 /* 12354 */ GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(12539),
4691 /* 12359 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4692 /* 12363 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 315*/ GIMT_Encode4(12411), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 911 //
4693 /* 12370 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4694 /* 12374 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4695 /* 12378 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4696 /* 12382 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4697 /* 12387 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4698 /* 12389 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4699 /* 12389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
4700 /* 12392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4701 /* 12394 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4702 /* 12396 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4703 /* 12400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4704 /* 12403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4705 /* 12409 */ GIR_RootConstrainSelectedInstOperands,
4706 /* 12410 */ // GIR_Coverage, 911,
4707 /* 12410 */ GIR_EraseRootFromParent_Done,
4708 /* 12411 */ // Label 315: @12411
4709 /* 12411 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 316*/ GIMT_Encode4(12459), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 905 //
4710 /* 12418 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4711 /* 12422 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4712 /* 12426 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4713 /* 12430 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4714 /* 12435 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4715 /* 12437 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4716 /* 12437 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64),
4717 /* 12440 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4718 /* 12442 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4719 /* 12444 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4720 /* 12448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4721 /* 12451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4722 /* 12457 */ GIR_RootConstrainSelectedInstOperands,
4723 /* 12458 */ // GIR_Coverage, 905,
4724 /* 12458 */ GIR_EraseRootFromParent_Done,
4725 /* 12459 */ // Label 316: @12459
4726 /* 12459 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 317*/ GIMT_Encode4(12507), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 910 //
4727 /* 12466 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4728 /* 12470 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4729 /* 12474 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
4730 /* 12478 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4731 /* 12483 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4732 /* 12485 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
4733 /* 12485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
4734 /* 12488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4735 /* 12490 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4736 /* 12492 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4737 /* 12496 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4738 /* 12499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4739 /* 12505 */ GIR_RootConstrainSelectedInstOperands,
4740 /* 12506 */ // GIR_Coverage, 910,
4741 /* 12506 */ GIR_EraseRootFromParent_Done,
4742 /* 12507 */ // Label 317: @12507
4743 /* 12507 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 318*/ GIMT_Encode4(12538), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 883 //
4744 /* 12514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4745 /* 12518 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
4746 /* 12518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i64),
4747 /* 12521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4748 /* 12523 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4749 /* 12525 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
4750 /* 12527 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4751 /* 12530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4752 /* 12536 */ GIR_RootConstrainSelectedInstOperands,
4753 /* 12537 */ // GIR_Coverage, 883,
4754 /* 12537 */ GIR_EraseRootFromParent_Done,
4755 /* 12538 */ // Label 318: @12538
4756 /* 12538 */ GIM_Reject,
4757 /* 12539 */ // Label 314: @12539
4758 /* 12539 */ GIM_Reject,
4759 /* 12540 */ // Label 298: @12540
4760 /* 12540 */ GIM_Reject,
4761 /* 12541 */ // Label 104: @12541
4762 /* 12541 */ GIM_Reject,
4763 /* 12542 */ // Label 1: @12542
4764 /* 12542 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 328*/ GIMT_Encode4(15639),
4765 /* 12553 */ /*GILLT_s32*//*Label 319*/ GIMT_Encode4(12605),
4766 /* 12557 */ /*GILLT_s64*//*Label 320*/ GIMT_Encode4(13210), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
4767 /* 12577 */ /*GILLT_v8s8*//*Label 321*/ GIMT_Encode4(13256),
4768 /* 12581 */ /*GILLT_v16s8*//*Label 322*/ GIMT_Encode4(13369),
4769 /* 12585 */ /*GILLT_v4s16*//*Label 323*/ GIMT_Encode4(13548),
4770 /* 12589 */ /*GILLT_v8s16*//*Label 324*/ GIMT_Encode4(13661),
4771 /* 12593 */ /*GILLT_v2s32*//*Label 325*/ GIMT_Encode4(14325),
4772 /* 12597 */ /*GILLT_v4s32*//*Label 326*/ GIMT_Encode4(14438),
4773 /* 12601 */ /*GILLT_v2s64*//*Label 327*/ GIMT_Encode4(15102),
4774 /* 12605 */ // Label 319: @12605
4775 /* 12605 */ GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(13209),
4776 /* 12610 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
4777 /* 12613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4778 /* 12616 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 330*/ GIMT_Encode4(12659), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 329 //
4779 /* 12623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
4780 /* 12627 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
4781 /* 12631 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
4782 /* 12635 */ // (sub:{ *:[i32] } 0:{ *:[i32] }, tGPR:{ *:[i32] }:$Rn) => (tRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)
4783 /* 12635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tRSB),
4784 /* 12638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4785 /* 12640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
4786 /* 12646 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4787 /* 12648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4788 /* 12651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4789 /* 12657 */ GIR_RootConstrainSelectedInstOperands,
4790 /* 12658 */ // GIR_Coverage, 329,
4791 /* 12658 */ GIR_EraseRootFromParent_Done,
4792 /* 12659 */ // Label 330: @12659
4793 /* 12659 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 331*/ GIMT_Encode4(12715), GIMT_Encode2(GIFBS_IsARM), // Rule ID 95 //
4794 /* 12666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4795 /* 12670 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4796 /* 12674 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4797 /* 12678 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
4798 /* 12682 */ // MIs[1] Operand 1
4799 /* 12682 */ // No operand predicates
4800 /* 12682 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4801 /* 12686 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4802 /* 12688 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn) => (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4803 /* 12688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RSBri),
4804 /* 12691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4805 /* 12693 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4806 /* 12695 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4807 /* 12698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4808 /* 12701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4809 /* 12707 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4810 /* 12713 */ GIR_RootConstrainSelectedInstOperands,
4811 /* 12714 */ // GIR_Coverage, 95,
4812 /* 12714 */ GIR_EraseRootFromParent_Done,
4813 /* 12715 */ // Label 331: @12715
4814 /* 12715 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 332*/ GIMT_Encode4(12771), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 426 //
4815 /* 12722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4816 /* 12726 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4817 /* 12730 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4818 /* 12734 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
4819 /* 12738 */ // MIs[1] Operand 1
4820 /* 12738 */ // No operand predicates
4821 /* 12738 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4822 /* 12742 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4823 /* 12744 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn) => (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4824 /* 12744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RSBri),
4825 /* 12747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4826 /* 12749 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4827 /* 12751 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4828 /* 12754 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4829 /* 12757 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4830 /* 12763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4831 /* 12769 */ GIR_RootConstrainSelectedInstOperands,
4832 /* 12770 */ // GIR_Coverage, 426,
4833 /* 12770 */ GIR_EraseRootFromParent_Done,
4834 /* 12771 */ // Label 332: @12771
4835 /* 12771 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 333*/ GIMT_Encode4(12827), GIMT_Encode2(GIFBS_IsARM), // Rule ID 75 //
4836 /* 12778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4837 /* 12782 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4838 /* 12786 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4839 /* 12790 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4840 /* 12794 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
4841 /* 12798 */ // MIs[1] Operand 1
4842 /* 12798 */ // No operand predicates
4843 /* 12798 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4844 /* 12800 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4845 /* 12800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBri),
4846 /* 12803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4847 /* 12805 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4848 /* 12807 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4849 /* 12810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4850 /* 12813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4851 /* 12819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4852 /* 12825 */ GIR_RootConstrainSelectedInstOperands,
4853 /* 12826 */ // GIR_Coverage, 75,
4854 /* 12826 */ GIR_EraseRootFromParent_Done,
4855 /* 12827 */ // Label 333: @12827
4856 /* 12827 */ GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(12935),
4857 /* 12832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4858 /* 12836 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 335*/ GIMT_Encode4(12888), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 410 //
4859 /* 12843 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
4860 /* 12847 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4861 /* 12851 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4862 /* 12855 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
4863 /* 12859 */ // MIs[1] Operand 1
4864 /* 12859 */ // No operand predicates
4865 /* 12859 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4866 /* 12861 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4867 /* 12861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri),
4868 /* 12864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4869 /* 12866 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4870 /* 12868 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4871 /* 12871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4872 /* 12874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4873 /* 12880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4874 /* 12886 */ GIR_RootConstrainSelectedInstOperands,
4875 /* 12887 */ // GIR_Coverage, 410,
4876 /* 12887 */ GIR_EraseRootFromParent_Done,
4877 /* 12888 */ // Label 335: @12888
4878 /* 12888 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 336*/ GIMT_Encode4(12934), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 411 //
4879 /* 12895 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4880 /* 12899 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4881 /* 12903 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4882 /* 12907 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095),
4883 /* 12911 */ // MIs[1] Operand 1
4884 /* 12911 */ // No operand predicates
4885 /* 12911 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4886 /* 12913 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4887 /* 12913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri12),
4888 /* 12916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4889 /* 12918 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4890 /* 12920 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4891 /* 12923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4892 /* 12926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4893 /* 12932 */ GIR_RootConstrainSelectedInstOperands,
4894 /* 12933 */ // GIR_Coverage, 411,
4895 /* 12933 */ GIR_EraseRootFromParent_Done,
4896 /* 12934 */ // Label 336: @12934
4897 /* 12934 */ GIM_Reject,
4898 /* 12935 */ // Label 334: @12935
4899 /* 12935 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 337*/ GIMT_Encode4(13004), GIMT_Encode2(GIFBS_HasV6T2_IsARM_UseMulOps), // Rule ID 172 //
4900 /* 12942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4901 /* 12946 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4902 /* 12950 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4903 /* 12954 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4904 /* 12958 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4905 /* 12962 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4906 /* 12966 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4907 /* 12971 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4908 /* 12976 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4909 /* 12978 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
4910 /* 12978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLS),
4911 /* 12981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4912 /* 12983 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4913 /* 12987 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4914 /* 12991 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
4915 /* 12993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4916 /* 12996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4917 /* 13002 */ GIR_RootConstrainSelectedInstOperands,
4918 /* 13003 */ // GIR_Coverage, 172,
4919 /* 13003 */ GIR_EraseRootFromParent_Done,
4920 /* 13004 */ // Label 337: @13004
4921 /* 13004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 338*/ GIMT_Encode4(13073), GIMT_Encode2(GIFBS_IsThumb2_UseMulOps), // Rule ID 503 //
4922 /* 13011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4923 /* 13015 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4924 /* 13019 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4925 /* 13023 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4926 /* 13027 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
4927 /* 13031 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
4928 /* 13035 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4929 /* 13040 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4930 /* 13045 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4931 /* 13047 */ // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
4932 /* 13047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLS),
4933 /* 13050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4934 /* 13052 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
4935 /* 13056 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
4936 /* 13060 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
4937 /* 13062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4938 /* 13065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4939 /* 13071 */ GIR_RootConstrainSelectedInstOperands,
4940 /* 13072 */ // GIR_Coverage, 503,
4941 /* 13072 */ GIR_EraseRootFromParent_Done,
4942 /* 13073 */ // Label 338: @13073
4943 /* 13073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 339*/ GIMT_Encode4(13118), GIMT_Encode2(GIFBS_IsARM), // Rule ID 76 //
4944 /* 13080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4945 /* 13084 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4946 /* 13088 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4947 /* 13092 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
4948 /* 13092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBrr),
4949 /* 13095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4950 /* 13097 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4951 /* 13099 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
4952 /* 13101 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4953 /* 13104 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4954 /* 13110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4955 /* 13116 */ GIR_RootConstrainSelectedInstOperands,
4956 /* 13117 */ // GIR_Coverage, 76,
4957 /* 13117 */ GIR_EraseRootFromParent_Done,
4958 /* 13118 */ // Label 339: @13118
4959 /* 13118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 340*/ GIMT_Encode4(13163), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 332 //
4960 /* 13125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
4961 /* 13129 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
4962 /* 13133 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
4963 /* 13137 */ // (sub:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tSUBrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
4964 /* 13137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSUBrr),
4965 /* 13140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4966 /* 13142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
4967 /* 13148 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4968 /* 13150 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
4969 /* 13152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4970 /* 13155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4971 /* 13161 */ GIR_RootConstrainSelectedInstOperands,
4972 /* 13162 */ // GIR_Coverage, 332,
4973 /* 13162 */ GIR_EraseRootFromParent_Done,
4974 /* 13163 */ // Label 340: @13163
4975 /* 13163 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 341*/ GIMT_Encode4(13208), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 412 //
4976 /* 13170 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
4977 /* 13174 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
4978 /* 13178 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4979 /* 13182 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
4980 /* 13182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBrr),
4981 /* 13185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4982 /* 13187 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
4983 /* 13189 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
4984 /* 13191 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4985 /* 13194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4986 /* 13200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4987 /* 13206 */ GIR_RootConstrainSelectedInstOperands,
4988 /* 13207 */ // GIR_Coverage, 412,
4989 /* 13207 */ GIR_EraseRootFromParent_Done,
4990 /* 13208 */ // Label 341: @13208
4991 /* 13208 */ GIM_Reject,
4992 /* 13209 */ // Label 329: @13209
4993 /* 13209 */ GIM_Reject,
4994 /* 13210 */ // Label 320: @13210
4995 /* 13210 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 342*/ GIMT_Encode4(13255), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1128 //
4996 /* 13217 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
4997 /* 13220 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
4998 /* 13223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4999 /* 13227 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5000 /* 13231 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5001 /* 13235 */ // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
5002 /* 13235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv1i64),
5003 /* 13238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5004 /* 13240 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5005 /* 13242 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5006 /* 13244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5007 /* 13247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5008 /* 13253 */ GIR_RootConstrainSelectedInstOperands,
5009 /* 13254 */ // GIR_Coverage, 1128,
5010 /* 13254 */ GIR_EraseRootFromParent_Done,
5011 /* 13255 */ // Label 342: @13255
5012 /* 13255 */ GIM_Reject,
5013 /* 13256 */ // Label 321: @13256
5014 /* 13256 */ GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(13368),
5015 /* 13261 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
5016 /* 13264 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
5017 /* 13267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5018 /* 13271 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5019 /* 13275 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 344*/ GIMT_Encode4(13336), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1053 //
5020 /* 13282 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5021 /* 13286 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5022 /* 13290 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5023 /* 13294 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
5024 /* 13298 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5025 /* 13303 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5026 /* 13308 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5027 /* 13310 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5028 /* 13310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i8),
5029 /* 13313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5030 /* 13315 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5031 /* 13317 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5032 /* 13321 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5033 /* 13325 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5034 /* 13328 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5035 /* 13334 */ GIR_RootConstrainSelectedInstOperands,
5036 /* 13335 */ // GIR_Coverage, 1053,
5037 /* 13335 */ GIR_EraseRootFromParent_Done,
5038 /* 13336 */ // Label 344: @13336
5039 /* 13336 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 345*/ GIMT_Encode4(13367), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1122 //
5040 /* 13343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5041 /* 13347 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5042 /* 13347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i8),
5043 /* 13350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5044 /* 13352 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5045 /* 13354 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5046 /* 13356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5047 /* 13359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5048 /* 13365 */ GIR_RootConstrainSelectedInstOperands,
5049 /* 13366 */ // GIR_Coverage, 1122,
5050 /* 13366 */ GIR_EraseRootFromParent_Done,
5051 /* 13367 */ // Label 345: @13367
5052 /* 13367 */ GIM_Reject,
5053 /* 13368 */ // Label 343: @13368
5054 /* 13368 */ GIM_Reject,
5055 /* 13369 */ // Label 322: @13369
5056 /* 13369 */ GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(13547),
5057 /* 13374 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
5058 /* 13377 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
5059 /* 13380 */ GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(13486),
5060 /* 13385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5061 /* 13389 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5062 /* 13393 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 348*/ GIMT_Encode4(13454), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1056 //
5063 /* 13400 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5064 /* 13404 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5065 /* 13408 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
5066 /* 13412 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
5067 /* 13416 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5068 /* 13421 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5069 /* 13426 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5070 /* 13428 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5071 /* 13428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv16i8),
5072 /* 13431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5073 /* 13433 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5074 /* 13435 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5075 /* 13439 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5076 /* 13443 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5077 /* 13446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5078 /* 13452 */ GIR_RootConstrainSelectedInstOperands,
5079 /* 13453 */ // GIR_Coverage, 1056,
5080 /* 13453 */ GIR_EraseRootFromParent_Done,
5081 /* 13454 */ // Label 348: @13454
5082 /* 13454 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 349*/ GIMT_Encode4(13485), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1125 //
5083 /* 13461 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5084 /* 13465 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5085 /* 13465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv16i8),
5086 /* 13468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5087 /* 13470 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5088 /* 13472 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5089 /* 13474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5090 /* 13477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5091 /* 13483 */ GIR_RootConstrainSelectedInstOperands,
5092 /* 13484 */ // GIR_Coverage, 1125,
5093 /* 13484 */ GIR_EraseRootFromParent_Done,
5094 /* 13485 */ // Label 349: @13485
5095 /* 13485 */ GIM_Reject,
5096 /* 13486 */ // Label 347: @13486
5097 /* 13486 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 350*/ GIMT_Encode4(13546), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3897 //
5098 /* 13493 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5099 /* 13497 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5100 /* 13501 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5101 /* 13505 */ // (sub:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VSUBi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
5102 /* 13505 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5103 /* 13508 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5104 /* 13512 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
5105 /* 13517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi8),
5106 /* 13520 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
5107 /* 13522 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
5108 /* 13524 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
5109 /* 13526 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5110 /* 13529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5111 /* 13535 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5112 /* 13541 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5113 /* 13544 */ GIR_RootConstrainSelectedInstOperands,
5114 /* 13545 */ // GIR_Coverage, 3897,
5115 /* 13545 */ GIR_EraseRootFromParent_Done,
5116 /* 13546 */ // Label 350: @13546
5117 /* 13546 */ GIM_Reject,
5118 /* 13547 */ // Label 346: @13547
5119 /* 13547 */ GIM_Reject,
5120 /* 13548 */ // Label 323: @13548
5121 /* 13548 */ GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(13660),
5122 /* 13553 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
5123 /* 13556 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
5124 /* 13559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5125 /* 13563 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5126 /* 13567 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 352*/ GIMT_Encode4(13628), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1054 //
5127 /* 13574 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5128 /* 13578 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5129 /* 13582 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5130 /* 13586 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5131 /* 13590 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5132 /* 13595 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5133 /* 13600 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5134 /* 13602 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5135 /* 13602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i16),
5136 /* 13605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5137 /* 13607 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5138 /* 13609 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5139 /* 13613 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5140 /* 13617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5141 /* 13620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5142 /* 13626 */ GIR_RootConstrainSelectedInstOperands,
5143 /* 13627 */ // GIR_Coverage, 1054,
5144 /* 13627 */ GIR_EraseRootFromParent_Done,
5145 /* 13628 */ // Label 352: @13628
5146 /* 13628 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 353*/ GIMT_Encode4(13659), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1123 //
5147 /* 13635 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5148 /* 13639 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5149 /* 13639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i16),
5150 /* 13642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5151 /* 13644 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5152 /* 13646 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5153 /* 13648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5154 /* 13651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5155 /* 13657 */ GIR_RootConstrainSelectedInstOperands,
5156 /* 13658 */ // GIR_Coverage, 1123,
5157 /* 13658 */ GIR_EraseRootFromParent_Done,
5158 /* 13659 */ // Label 353: @13659
5159 /* 13659 */ GIM_Reject,
5160 /* 13660 */ // Label 351: @13660
5161 /* 13660 */ GIM_Reject,
5162 /* 13661 */ // Label 324: @13661
5163 /* 13661 */ GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(14324),
5164 /* 13666 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
5165 /* 13669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
5166 /* 13672 */ GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(14263),
5167 /* 13677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5168 /* 13681 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 356*/ GIMT_Encode4(13748), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1140 //
5169 /* 13688 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5170 /* 13692 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5171 /* 13696 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5172 /* 13700 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5173 /* 13705 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5174 /* 13709 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5175 /* 13713 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5176 /* 13717 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5177 /* 13722 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5178 /* 13724 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5179 /* 13724 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5180 /* 13727 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5181 /* 13729 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5182 /* 13733 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5183 /* 13737 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5184 /* 13740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5185 /* 13746 */ GIR_RootConstrainSelectedInstOperands,
5186 /* 13747 */ // GIR_Coverage, 1140,
5187 /* 13747 */ GIR_EraseRootFromParent_Done,
5188 /* 13748 */ // Label 356: @13748
5189 /* 13748 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 357*/ GIMT_Encode4(13815), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1139 //
5190 /* 13755 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5191 /* 13759 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5192 /* 13763 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5193 /* 13767 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5194 /* 13772 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5195 /* 13776 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5196 /* 13780 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5197 /* 13784 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5198 /* 13789 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5199 /* 13791 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5200 /* 13791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5201 /* 13794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5202 /* 13796 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5203 /* 13800 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5204 /* 13804 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5205 /* 13807 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5206 /* 13813 */ GIR_RootConstrainSelectedInstOperands,
5207 /* 13814 */ // GIR_Coverage, 1139,
5208 /* 13814 */ GIR_EraseRootFromParent_Done,
5209 /* 13815 */ // Label 357: @13815
5210 /* 13815 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 358*/ GIMT_Encode4(13882), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1134 //
5211 /* 13822 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5212 /* 13826 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5213 /* 13830 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5214 /* 13834 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5215 /* 13839 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5216 /* 13843 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
5217 /* 13847 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5218 /* 13851 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5219 /* 13856 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5220 /* 13858 */ // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5221 /* 13858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv8i16),
5222 /* 13861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5223 /* 13863 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5224 /* 13867 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5225 /* 13871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5226 /* 13874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5227 /* 13880 */ GIR_RootConstrainSelectedInstOperands,
5228 /* 13881 */ // GIR_Coverage, 1134,
5229 /* 13881 */ GIR_EraseRootFromParent_Done,
5230 /* 13882 */ // Label 358: @13882
5231 /* 13882 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 359*/ GIMT_Encode4(13949), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1138 //
5232 /* 13889 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5233 /* 13893 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5234 /* 13897 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5235 /* 13901 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5236 /* 13906 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5237 /* 13910 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5238 /* 13914 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5239 /* 13918 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5240 /* 13923 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5241 /* 13925 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5242 /* 13925 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5243 /* 13928 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5244 /* 13930 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5245 /* 13934 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5246 /* 13938 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5247 /* 13941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5248 /* 13947 */ GIR_RootConstrainSelectedInstOperands,
5249 /* 13948 */ // GIR_Coverage, 1138,
5250 /* 13948 */ GIR_EraseRootFromParent_Done,
5251 /* 13949 */ // Label 359: @13949
5252 /* 13949 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 360*/ GIMT_Encode4(14016), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1137 //
5253 /* 13956 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5254 /* 13960 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5255 /* 13964 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5256 /* 13968 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5257 /* 13973 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5258 /* 13977 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5259 /* 13981 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5260 /* 13985 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5261 /* 13990 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5262 /* 13992 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5263 /* 13992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5264 /* 13995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5265 /* 13997 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5266 /* 14001 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5267 /* 14005 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5268 /* 14008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5269 /* 14014 */ GIR_RootConstrainSelectedInstOperands,
5270 /* 14015 */ // GIR_Coverage, 1137,
5271 /* 14015 */ GIR_EraseRootFromParent_Done,
5272 /* 14016 */ // Label 360: @14016
5273 /* 14016 */ GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(14262),
5274 /* 14021 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5275 /* 14025 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 362*/ GIMT_Encode4(14086), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1057 //
5276 /* 14032 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5277 /* 14036 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5278 /* 14040 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
5279 /* 14044 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
5280 /* 14048 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5281 /* 14053 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5282 /* 14058 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5283 /* 14060 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
5284 /* 14060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i16),
5285 /* 14063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5286 /* 14065 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5287 /* 14067 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5288 /* 14071 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5289 /* 14075 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5290 /* 14078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5291 /* 14084 */ GIR_RootConstrainSelectedInstOperands,
5292 /* 14085 */ // GIR_Coverage, 1057,
5293 /* 14085 */ GIR_EraseRootFromParent_Done,
5294 /* 14086 */ // Label 362: @14086
5295 /* 14086 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 363*/ GIMT_Encode4(14134), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1153 //
5296 /* 14093 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5297 /* 14097 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5298 /* 14101 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5299 /* 14105 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5300 /* 14110 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5301 /* 14112 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5302 /* 14112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16),
5303 /* 14115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5304 /* 14117 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5305 /* 14119 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5306 /* 14123 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5307 /* 14126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5308 /* 14132 */ GIR_RootConstrainSelectedInstOperands,
5309 /* 14133 */ // GIR_Coverage, 1153,
5310 /* 14133 */ GIR_EraseRootFromParent_Done,
5311 /* 14134 */ // Label 363: @14134
5312 /* 14134 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 364*/ GIMT_Encode4(14182), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1149 //
5313 /* 14141 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5314 /* 14145 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5315 /* 14149 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5316 /* 14153 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5317 /* 14158 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5318 /* 14160 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5319 /* 14160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv8i16),
5320 /* 14163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5321 /* 14165 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5322 /* 14167 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5323 /* 14171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5324 /* 14174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5325 /* 14180 */ GIR_RootConstrainSelectedInstOperands,
5326 /* 14181 */ // GIR_Coverage, 1149,
5327 /* 14181 */ GIR_EraseRootFromParent_Done,
5328 /* 14182 */ // Label 364: @14182
5329 /* 14182 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 365*/ GIMT_Encode4(14230), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1152 //
5330 /* 14189 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5331 /* 14193 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5332 /* 14197 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5333 /* 14201 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5334 /* 14206 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5335 /* 14208 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5336 /* 14208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16),
5337 /* 14211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5338 /* 14213 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5339 /* 14215 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5340 /* 14219 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5341 /* 14222 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5342 /* 14228 */ GIR_RootConstrainSelectedInstOperands,
5343 /* 14229 */ // GIR_Coverage, 1152,
5344 /* 14229 */ GIR_EraseRootFromParent_Done,
5345 /* 14230 */ // Label 365: @14230
5346 /* 14230 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 366*/ GIMT_Encode4(14261), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1126 //
5347 /* 14237 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5348 /* 14241 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
5349 /* 14241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i16),
5350 /* 14244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5351 /* 14246 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5352 /* 14248 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5353 /* 14250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5354 /* 14253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5355 /* 14259 */ GIR_RootConstrainSelectedInstOperands,
5356 /* 14260 */ // GIR_Coverage, 1126,
5357 /* 14260 */ GIR_EraseRootFromParent_Done,
5358 /* 14261 */ // Label 366: @14261
5359 /* 14261 */ GIM_Reject,
5360 /* 14262 */ // Label 361: @14262
5361 /* 14262 */ GIM_Reject,
5362 /* 14263 */ // Label 355: @14263
5363 /* 14263 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 367*/ GIMT_Encode4(14323), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3901 //
5364 /* 14270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5365 /* 14274 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5366 /* 14278 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5367 /* 14282 */ // (sub:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VSUBi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
5368 /* 14282 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5369 /* 14285 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5370 /* 14289 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
5371 /* 14294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi16),
5372 /* 14297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
5373 /* 14299 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
5374 /* 14301 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
5375 /* 14303 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5376 /* 14306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5377 /* 14312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5378 /* 14318 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5379 /* 14321 */ GIR_RootConstrainSelectedInstOperands,
5380 /* 14322 */ // GIR_Coverage, 3901,
5381 /* 14322 */ GIR_EraseRootFromParent_Done,
5382 /* 14323 */ // Label 367: @14323
5383 /* 14323 */ GIM_Reject,
5384 /* 14324 */ // Label 354: @14324
5385 /* 14324 */ GIM_Reject,
5386 /* 14325 */ // Label 325: @14325
5387 /* 14325 */ GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(14437),
5388 /* 14330 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
5389 /* 14333 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
5390 /* 14336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5391 /* 14340 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5392 /* 14344 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 369*/ GIMT_Encode4(14405), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1055 //
5393 /* 14351 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5394 /* 14355 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5395 /* 14359 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5396 /* 14363 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
5397 /* 14367 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5398 /* 14372 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5399 /* 14377 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5400 /* 14379 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5401 /* 14379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv2i32),
5402 /* 14382 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5403 /* 14384 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5404 /* 14386 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5405 /* 14390 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5406 /* 14394 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5407 /* 14397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5408 /* 14403 */ GIR_RootConstrainSelectedInstOperands,
5409 /* 14404 */ // GIR_Coverage, 1055,
5410 /* 14404 */ GIR_EraseRootFromParent_Done,
5411 /* 14405 */ // Label 369: @14405
5412 /* 14405 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 370*/ GIMT_Encode4(14436), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1124 //
5413 /* 14412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5414 /* 14416 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5415 /* 14416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i32),
5416 /* 14419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5417 /* 14421 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5418 /* 14423 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5419 /* 14425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5420 /* 14428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5421 /* 14434 */ GIR_RootConstrainSelectedInstOperands,
5422 /* 14435 */ // GIR_Coverage, 1124,
5423 /* 14435 */ GIR_EraseRootFromParent_Done,
5424 /* 14436 */ // Label 370: @14436
5425 /* 14436 */ GIM_Reject,
5426 /* 14437 */ // Label 368: @14437
5427 /* 14437 */ GIM_Reject,
5428 /* 14438 */ // Label 326: @14438
5429 /* 14438 */ GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(15101),
5430 /* 14443 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
5431 /* 14446 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
5432 /* 14449 */ GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(15040),
5433 /* 14454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5434 /* 14458 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 373*/ GIMT_Encode4(14525), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1144 //
5435 /* 14465 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5436 /* 14469 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5437 /* 14473 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5438 /* 14477 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5439 /* 14482 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5440 /* 14486 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5441 /* 14490 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5442 /* 14494 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5443 /* 14499 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5444 /* 14501 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5445 /* 14501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5446 /* 14504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5447 /* 14506 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5448 /* 14510 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5449 /* 14514 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5450 /* 14517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5451 /* 14523 */ GIR_RootConstrainSelectedInstOperands,
5452 /* 14524 */ // GIR_Coverage, 1144,
5453 /* 14524 */ GIR_EraseRootFromParent_Done,
5454 /* 14525 */ // Label 373: @14525
5455 /* 14525 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 374*/ GIMT_Encode4(14592), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1143 //
5456 /* 14532 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5457 /* 14536 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5458 /* 14540 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5459 /* 14544 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5460 /* 14549 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5461 /* 14553 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5462 /* 14557 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5463 /* 14561 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5464 /* 14566 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5465 /* 14568 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5466 /* 14568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5467 /* 14571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5468 /* 14573 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5469 /* 14577 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5470 /* 14581 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5471 /* 14584 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5472 /* 14590 */ GIR_RootConstrainSelectedInstOperands,
5473 /* 14591 */ // GIR_Coverage, 1143,
5474 /* 14591 */ GIR_EraseRootFromParent_Done,
5475 /* 14592 */ // Label 374: @14592
5476 /* 14592 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 375*/ GIMT_Encode4(14659), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1135 //
5477 /* 14599 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5478 /* 14603 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5479 /* 14607 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5480 /* 14611 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5481 /* 14616 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5482 /* 14620 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
5483 /* 14624 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5484 /* 14628 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5485 /* 14633 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5486 /* 14635 */ // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5487 /* 14635 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv4i32),
5488 /* 14638 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5489 /* 14640 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5490 /* 14644 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5491 /* 14648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5492 /* 14651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5493 /* 14657 */ GIR_RootConstrainSelectedInstOperands,
5494 /* 14658 */ // GIR_Coverage, 1135,
5495 /* 14658 */ GIR_EraseRootFromParent_Done,
5496 /* 14659 */ // Label 375: @14659
5497 /* 14659 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 376*/ GIMT_Encode4(14726), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1142 //
5498 /* 14666 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5499 /* 14670 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5500 /* 14674 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5501 /* 14678 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5502 /* 14683 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5503 /* 14687 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5504 /* 14691 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5505 /* 14695 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5506 /* 14700 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5507 /* 14702 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5508 /* 14702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5509 /* 14705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5510 /* 14707 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5511 /* 14711 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5512 /* 14715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5513 /* 14718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5514 /* 14724 */ GIR_RootConstrainSelectedInstOperands,
5515 /* 14725 */ // GIR_Coverage, 1142,
5516 /* 14725 */ GIR_EraseRootFromParent_Done,
5517 /* 14726 */ // Label 376: @14726
5518 /* 14726 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 377*/ GIMT_Encode4(14793), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1141 //
5519 /* 14733 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5520 /* 14737 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5521 /* 14741 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5522 /* 14745 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5523 /* 14750 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5524 /* 14754 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5525 /* 14758 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5526 /* 14762 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5527 /* 14767 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5528 /* 14769 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5529 /* 14769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5530 /* 14772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5531 /* 14774 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5532 /* 14778 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5533 /* 14782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5534 /* 14785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5535 /* 14791 */ GIR_RootConstrainSelectedInstOperands,
5536 /* 14792 */ // GIR_Coverage, 1141,
5537 /* 14792 */ GIR_EraseRootFromParent_Done,
5538 /* 14793 */ // Label 377: @14793
5539 /* 14793 */ GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(15039),
5540 /* 14798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5541 /* 14802 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 379*/ GIMT_Encode4(14863), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1058 //
5542 /* 14809 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5543 /* 14813 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5544 /* 14817 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5545 /* 14821 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5546 /* 14825 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5547 /* 14830 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5548 /* 14835 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5549 /* 14837 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
5550 /* 14837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i32),
5551 /* 14840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5552 /* 14842 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5553 /* 14844 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5554 /* 14848 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5555 /* 14852 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5556 /* 14855 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5557 /* 14861 */ GIR_RootConstrainSelectedInstOperands,
5558 /* 14862 */ // GIR_Coverage, 1058,
5559 /* 14862 */ GIR_EraseRootFromParent_Done,
5560 /* 14863 */ // Label 379: @14863
5561 /* 14863 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 380*/ GIMT_Encode4(14911), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1155 //
5562 /* 14870 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5563 /* 14874 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5564 /* 14878 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5565 /* 14882 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5566 /* 14887 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5567 /* 14889 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5568 /* 14889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32),
5569 /* 14892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5570 /* 14894 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5571 /* 14896 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5572 /* 14900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5573 /* 14903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5574 /* 14909 */ GIR_RootConstrainSelectedInstOperands,
5575 /* 14910 */ // GIR_Coverage, 1155,
5576 /* 14910 */ GIR_EraseRootFromParent_Done,
5577 /* 14911 */ // Label 380: @14911
5578 /* 14911 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 381*/ GIMT_Encode4(14959), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1150 //
5579 /* 14918 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5580 /* 14922 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5581 /* 14926 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5582 /* 14930 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5583 /* 14935 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5584 /* 14937 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5585 /* 14937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv4i32),
5586 /* 14940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5587 /* 14942 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5588 /* 14944 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5589 /* 14948 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5590 /* 14951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5591 /* 14957 */ GIR_RootConstrainSelectedInstOperands,
5592 /* 14958 */ // GIR_Coverage, 1150,
5593 /* 14958 */ GIR_EraseRootFromParent_Done,
5594 /* 14959 */ // Label 381: @14959
5595 /* 14959 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 382*/ GIMT_Encode4(15007), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1154 //
5596 /* 14966 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5597 /* 14970 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5598 /* 14974 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5599 /* 14978 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5600 /* 14983 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5601 /* 14985 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5602 /* 14985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32),
5603 /* 14988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5604 /* 14990 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5605 /* 14992 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5606 /* 14996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5607 /* 14999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5608 /* 15005 */ GIR_RootConstrainSelectedInstOperands,
5609 /* 15006 */ // GIR_Coverage, 1154,
5610 /* 15006 */ GIR_EraseRootFromParent_Done,
5611 /* 15007 */ // Label 382: @15007
5612 /* 15007 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 383*/ GIMT_Encode4(15038), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1127 //
5613 /* 15014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5614 /* 15018 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
5615 /* 15018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i32),
5616 /* 15021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5617 /* 15023 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5618 /* 15025 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5619 /* 15027 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5620 /* 15030 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5621 /* 15036 */ GIR_RootConstrainSelectedInstOperands,
5622 /* 15037 */ // GIR_Coverage, 1127,
5623 /* 15037 */ GIR_EraseRootFromParent_Done,
5624 /* 15038 */ // Label 383: @15038
5625 /* 15038 */ GIM_Reject,
5626 /* 15039 */ // Label 378: @15039
5627 /* 15039 */ GIM_Reject,
5628 /* 15040 */ // Label 372: @15040
5629 /* 15040 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 384*/ GIMT_Encode4(15100), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3905 //
5630 /* 15047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5631 /* 15051 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5632 /* 15055 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5633 /* 15059 */ // (sub:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VSUBi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
5634 /* 15059 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5635 /* 15062 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5636 /* 15066 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
5637 /* 15071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi32),
5638 /* 15074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
5639 /* 15076 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
5640 /* 15078 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
5641 /* 15080 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5642 /* 15083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5643 /* 15089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5644 /* 15095 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5645 /* 15098 */ GIR_RootConstrainSelectedInstOperands,
5646 /* 15099 */ // GIR_Coverage, 3905,
5647 /* 15099 */ GIR_EraseRootFromParent_Done,
5648 /* 15100 */ // Label 384: @15100
5649 /* 15100 */ GIM_Reject,
5650 /* 15101 */ // Label 371: @15101
5651 /* 15101 */ GIM_Reject,
5652 /* 15102 */ // Label 327: @15102
5653 /* 15102 */ GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(15638),
5654 /* 15107 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
5655 /* 15110 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
5656 /* 15113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5657 /* 15117 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 386*/ GIMT_Encode4(15184), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1148 //
5658 /* 15124 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5659 /* 15128 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5660 /* 15132 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5661 /* 15136 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5662 /* 15141 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5663 /* 15145 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5664 /* 15149 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5665 /* 15153 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5666 /* 15158 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5667 /* 15160 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5668 /* 15160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5669 /* 15163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5670 /* 15165 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5671 /* 15169 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5672 /* 15173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5673 /* 15176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5674 /* 15182 */ GIR_RootConstrainSelectedInstOperands,
5675 /* 15183 */ // GIR_Coverage, 1148,
5676 /* 15183 */ GIR_EraseRootFromParent_Done,
5677 /* 15184 */ // Label 386: @15184
5678 /* 15184 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 387*/ GIMT_Encode4(15251), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1147 //
5679 /* 15191 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5680 /* 15195 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5681 /* 15199 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5682 /* 15203 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5683 /* 15208 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5684 /* 15212 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5685 /* 15216 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5686 /* 15220 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5687 /* 15225 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5688 /* 15227 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5689 /* 15227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5690 /* 15230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5691 /* 15232 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5692 /* 15236 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5693 /* 15240 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5694 /* 15243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5695 /* 15249 */ GIR_RootConstrainSelectedInstOperands,
5696 /* 15250 */ // GIR_Coverage, 1147,
5697 /* 15250 */ GIR_EraseRootFromParent_Done,
5698 /* 15251 */ // Label 387: @15251
5699 /* 15251 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 388*/ GIMT_Encode4(15318), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1136 //
5700 /* 15258 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5701 /* 15262 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5702 /* 15266 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5703 /* 15270 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5704 /* 15275 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5705 /* 15279 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
5706 /* 15283 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5707 /* 15287 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5708 /* 15292 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5709 /* 15294 */ // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5710 /* 15294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv2i64),
5711 /* 15297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5712 /* 15299 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5713 /* 15303 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5714 /* 15307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5715 /* 15310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5716 /* 15316 */ GIR_RootConstrainSelectedInstOperands,
5717 /* 15317 */ // GIR_Coverage, 1136,
5718 /* 15317 */ GIR_EraseRootFromParent_Done,
5719 /* 15318 */ // Label 388: @15318
5720 /* 15318 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 389*/ GIMT_Encode4(15385), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1146 //
5721 /* 15325 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5722 /* 15329 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5723 /* 15333 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5724 /* 15337 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5725 /* 15342 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5726 /* 15346 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5727 /* 15350 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5728 /* 15354 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5729 /* 15359 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5730 /* 15361 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5731 /* 15361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5732 /* 15364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5733 /* 15366 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5734 /* 15370 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5735 /* 15374 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5736 /* 15377 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5737 /* 15383 */ GIR_RootConstrainSelectedInstOperands,
5738 /* 15384 */ // GIR_Coverage, 1146,
5739 /* 15384 */ GIR_EraseRootFromParent_Done,
5740 /* 15385 */ // Label 389: @15385
5741 /* 15385 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 390*/ GIMT_Encode4(15452), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1145 //
5742 /* 15392 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5743 /* 15396 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5744 /* 15400 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5745 /* 15404 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5746 /* 15409 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5747 /* 15413 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5748 /* 15417 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5749 /* 15421 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5750 /* 15426 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5751 /* 15428 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5752 /* 15428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5753 /* 15431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5754 /* 15433 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5755 /* 15437 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5756 /* 15441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5757 /* 15444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5758 /* 15450 */ GIR_RootConstrainSelectedInstOperands,
5759 /* 15451 */ // GIR_Coverage, 1145,
5760 /* 15451 */ GIR_EraseRootFromParent_Done,
5761 /* 15452 */ // Label 390: @15452
5762 /* 15452 */ GIM_Try, /*On fail goto*//*Label 391*/ GIMT_Encode4(15637),
5763 /* 15457 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5764 /* 15461 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 392*/ GIMT_Encode4(15509), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1157 //
5765 /* 15468 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5766 /* 15472 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5767 /* 15476 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5768 /* 15480 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5769 /* 15485 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5770 /* 15487 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5771 /* 15487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64),
5772 /* 15490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5773 /* 15492 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5774 /* 15494 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5775 /* 15498 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5776 /* 15501 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5777 /* 15507 */ GIR_RootConstrainSelectedInstOperands,
5778 /* 15508 */ // GIR_Coverage, 1157,
5779 /* 15508 */ GIR_EraseRootFromParent_Done,
5780 /* 15509 */ // Label 392: @15509
5781 /* 15509 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 393*/ GIMT_Encode4(15557), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1151 //
5782 /* 15516 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5783 /* 15520 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5784 /* 15524 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5785 /* 15528 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5786 /* 15533 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5787 /* 15535 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5788 /* 15535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv2i64),
5789 /* 15538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5790 /* 15540 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5791 /* 15542 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5792 /* 15546 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5793 /* 15549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5794 /* 15555 */ GIR_RootConstrainSelectedInstOperands,
5795 /* 15556 */ // GIR_Coverage, 1151,
5796 /* 15556 */ GIR_EraseRootFromParent_Done,
5797 /* 15557 */ // Label 393: @15557
5798 /* 15557 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 394*/ GIMT_Encode4(15605), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1156 //
5799 /* 15564 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5800 /* 15568 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5801 /* 15572 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5802 /* 15576 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5803 /* 15581 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5804 /* 15583 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5805 /* 15583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64),
5806 /* 15586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5807 /* 15588 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5808 /* 15590 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5809 /* 15594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5810 /* 15597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5811 /* 15603 */ GIR_RootConstrainSelectedInstOperands,
5812 /* 15604 */ // GIR_Coverage, 1156,
5813 /* 15604 */ GIR_EraseRootFromParent_Done,
5814 /* 15605 */ // Label 394: @15605
5815 /* 15605 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 395*/ GIMT_Encode4(15636), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1129 //
5816 /* 15612 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5817 /* 15616 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
5818 /* 15616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i64),
5819 /* 15619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5820 /* 15621 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5821 /* 15623 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5822 /* 15625 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5823 /* 15628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5824 /* 15634 */ GIR_RootConstrainSelectedInstOperands,
5825 /* 15635 */ // GIR_Coverage, 1129,
5826 /* 15635 */ GIR_EraseRootFromParent_Done,
5827 /* 15636 */ // Label 395: @15636
5828 /* 15636 */ GIM_Reject,
5829 /* 15637 */ // Label 391: @15637
5830 /* 15637 */ GIM_Reject,
5831 /* 15638 */ // Label 385: @15638
5832 /* 15638 */ GIM_Reject,
5833 /* 15639 */ // Label 328: @15639
5834 /* 15639 */ GIM_Reject,
5835 /* 15640 */ // Label 2: @15640
5836 /* 15640 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 403*/ GIMT_Encode4(17302),
5837 /* 15651 */ /*GILLT_s32*//*Label 396*/ GIMT_Encode4(15699), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
5838 /* 15675 */ /*GILLT_v8s8*//*Label 397*/ GIMT_Encode4(16600),
5839 /* 15679 */ /*GILLT_v16s8*//*Label 398*/ GIMT_Encode4(16646),
5840 /* 15683 */ /*GILLT_v4s16*//*Label 399*/ GIMT_Encode4(16758),
5841 /* 15687 */ /*GILLT_v8s16*//*Label 400*/ GIMT_Encode4(16804),
5842 /* 15691 */ /*GILLT_v2s32*//*Label 401*/ GIMT_Encode4(17030),
5843 /* 15695 */ /*GILLT_v4s32*//*Label 402*/ GIMT_Encode4(17076),
5844 /* 15699 */ // Label 396: @15699
5845 /* 15699 */ GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(16599),
5846 /* 15704 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
5847 /* 15707 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
5848 /* 15710 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 405*/ GIMT_Encode4(15797), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 185 //
5849 /* 15717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5850 /* 15721 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5851 /* 15725 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
5852 /* 15729 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5853 /* 15733 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5854 /* 15737 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5855 /* 15742 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
5856 /* 15746 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5857 /* 15750 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
5858 /* 15754 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5859 /* 15758 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5860 /* 15762 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5861 /* 15767 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
5862 /* 15771 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5863 /* 15773 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5864 /* 15773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT),
5865 /* 15776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5866 /* 15778 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5867 /* 15782 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5868 /* 15786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5869 /* 15789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5870 /* 15795 */ GIR_RootConstrainSelectedInstOperands,
5871 /* 15796 */ // GIR_Coverage, 185,
5872 /* 15796 */ GIR_EraseRootFromParent_Done,
5873 /* 15797 */ // Label 405: @15797
5874 /* 15797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 406*/ GIMT_Encode4(15884), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 514 //
5875 /* 15804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5876 /* 15808 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5877 /* 15812 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
5878 /* 15816 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5879 /* 15820 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5880 /* 15824 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5881 /* 15829 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
5882 /* 15833 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5883 /* 15837 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
5884 /* 15841 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5885 /* 15845 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5886 /* 15849 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5887 /* 15854 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
5888 /* 15858 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5889 /* 15860 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5890 /* 15860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT),
5891 /* 15863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5892 /* 15865 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5893 /* 15869 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5894 /* 15873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5895 /* 15876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5896 /* 15882 */ GIR_RootConstrainSelectedInstOperands,
5897 /* 15883 */ // GIR_Coverage, 514,
5898 /* 15883 */ GIR_EraseRootFromParent_Done,
5899 /* 15884 */ // Label 406: @15884
5900 /* 15884 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 407*/ GIMT_Encode4(15974), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 184 //
5901 /* 15891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5902 /* 15895 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5903 /* 15899 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
5904 /* 15903 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5905 /* 15907 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5906 /* 15911 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5907 /* 15916 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
5908 /* 15920 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5909 /* 15924 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
5910 /* 15928 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5911 /* 15932 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5912 /* 15937 */ // MIs[2] Operand 2
5913 /* 15937 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
5914 /* 15948 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5915 /* 15950 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5916 /* 15950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB),
5917 /* 15953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5918 /* 15955 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5919 /* 15959 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5920 /* 15963 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5921 /* 15966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5922 /* 15972 */ GIR_RootConstrainSelectedInstOperands,
5923 /* 15973 */ // GIR_Coverage, 184,
5924 /* 15973 */ GIR_EraseRootFromParent_Done,
5925 /* 15974 */ // Label 407: @15974
5926 /* 15974 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 408*/ GIMT_Encode4(16064), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 513 //
5927 /* 15981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5928 /* 15985 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5929 /* 15989 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
5930 /* 15993 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5931 /* 15997 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5932 /* 16001 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5933 /* 16006 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
5934 /* 16010 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5935 /* 16014 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
5936 /* 16018 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5937 /* 16022 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5938 /* 16027 */ // MIs[2] Operand 2
5939 /* 16027 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
5940 /* 16038 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5941 /* 16040 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5942 /* 16040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB),
5943 /* 16043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5944 /* 16045 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5945 /* 16049 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5946 /* 16053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5947 /* 16056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5948 /* 16062 */ GIR_RootConstrainSelectedInstOperands,
5949 /* 16063 */ // GIR_Coverage, 513,
5950 /* 16063 */ GIR_EraseRootFromParent_Done,
5951 /* 16064 */ // Label 408: @16064
5952 /* 16064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 409*/ GIMT_Encode4(16154), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 183 //
5953 /* 16071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5954 /* 16075 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5955 /* 16079 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
5956 /* 16083 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5957 /* 16087 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5958 /* 16092 */ // MIs[1] Operand 2
5959 /* 16092 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
5960 /* 16103 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5961 /* 16107 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
5962 /* 16111 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5963 /* 16115 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5964 /* 16119 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5965 /* 16124 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
5966 /* 16128 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5967 /* 16130 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5968 /* 16130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT),
5969 /* 16133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5970 /* 16135 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5971 /* 16139 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5972 /* 16143 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5973 /* 16146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5974 /* 16152 */ GIR_RootConstrainSelectedInstOperands,
5975 /* 16153 */ // GIR_Coverage, 183,
5976 /* 16153 */ GIR_EraseRootFromParent_Done,
5977 /* 16154 */ // Label 409: @16154
5978 /* 16154 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 410*/ GIMT_Encode4(16244), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 512 //
5979 /* 16161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5980 /* 16165 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5981 /* 16169 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
5982 /* 16173 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5983 /* 16177 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5984 /* 16182 */ // MIs[1] Operand 2
5985 /* 16182 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
5986 /* 16193 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5987 /* 16197 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
5988 /* 16201 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
5989 /* 16205 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
5990 /* 16209 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5991 /* 16214 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
5992 /* 16218 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5993 /* 16220 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5994 /* 16220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT),
5995 /* 16223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5996 /* 16225 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5997 /* 16229 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
5998 /* 16233 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5999 /* 16236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6000 /* 16242 */ GIR_RootConstrainSelectedInstOperands,
6001 /* 16243 */ // GIR_Coverage, 512,
6002 /* 16243 */ GIR_EraseRootFromParent_Done,
6003 /* 16244 */ // Label 410: @16244
6004 /* 16244 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 411*/ GIMT_Encode4(16337), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 182 //
6005 /* 16251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6006 /* 16255 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6007 /* 16259 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6008 /* 16263 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6009 /* 16267 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6010 /* 16272 */ // MIs[1] Operand 2
6011 /* 16272 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6012 /* 16283 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6013 /* 16287 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6014 /* 16291 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6015 /* 16295 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6016 /* 16300 */ // MIs[2] Operand 2
6017 /* 16300 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6018 /* 16311 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6019 /* 16313 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6020 /* 16313 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB),
6021 /* 16316 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6022 /* 16318 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6023 /* 16322 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6024 /* 16326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6025 /* 16329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6026 /* 16335 */ GIR_RootConstrainSelectedInstOperands,
6027 /* 16336 */ // GIR_Coverage, 182,
6028 /* 16336 */ GIR_EraseRootFromParent_Done,
6029 /* 16337 */ // Label 411: @16337
6030 /* 16337 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 412*/ GIMT_Encode4(16430), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 511 //
6031 /* 16344 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6032 /* 16348 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6033 /* 16352 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6034 /* 16356 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6035 /* 16360 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6036 /* 16365 */ // MIs[1] Operand 2
6037 /* 16365 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6038 /* 16376 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6039 /* 16380 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6040 /* 16384 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6041 /* 16388 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6042 /* 16393 */ // MIs[2] Operand 2
6043 /* 16393 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6044 /* 16404 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6045 /* 16406 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6046 /* 16406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB),
6047 /* 16409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6048 /* 16411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6049 /* 16415 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6050 /* 16419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6051 /* 16422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6052 /* 16428 */ GIR_RootConstrainSelectedInstOperands,
6053 /* 16429 */ // GIR_Coverage, 511,
6054 /* 16429 */ GIR_EraseRootFromParent_Done,
6055 /* 16430 */ // Label 412: @16430
6056 /* 16430 */ GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(16514),
6057 /* 16435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6058 /* 16439 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6059 /* 16443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6060 /* 16447 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 414*/ GIMT_Encode4(16480), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 168 //
6061 /* 16454 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
6062 /* 16454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MUL),
6063 /* 16457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6064 /* 16459 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6065 /* 16461 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6066 /* 16463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6067 /* 16466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6068 /* 16472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6069 /* 16478 */ GIR_RootConstrainSelectedInstOperands,
6070 /* 16479 */ // GIR_Coverage, 168,
6071 /* 16479 */ GIR_EraseRootFromParent_Done,
6072 /* 16480 */ // Label 414: @16480
6073 /* 16480 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 415*/ GIMT_Encode4(16513), GIMT_Encode2(GIFBS_IsARM_NoV6_UseMulOps), // Rule ID 169 //
6074 /* 16487 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
6075 /* 16487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MULv5),
6076 /* 16490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6077 /* 16492 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6078 /* 16494 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6079 /* 16496 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6080 /* 16499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6081 /* 16505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6082 /* 16511 */ GIR_RootConstrainSelectedInstOperands,
6083 /* 16512 */ // GIR_Coverage, 169,
6084 /* 16512 */ GIR_EraseRootFromParent_Done,
6085 /* 16513 */ // Label 415: @16513
6086 /* 16513 */ GIM_Reject,
6087 /* 16514 */ // Label 413: @16514
6088 /* 16514 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 416*/ GIMT_Encode4(16559), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 322 //
6089 /* 16521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6090 /* 16525 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6091 /* 16529 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6092 /* 16533 */ // (mul:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tMUL:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
6093 /* 16533 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMUL),
6094 /* 16536 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6095 /* 16538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
6096 /* 16544 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6097 /* 16546 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6098 /* 16548 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6099 /* 16551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6100 /* 16557 */ GIR_RootConstrainSelectedInstOperands,
6101 /* 16558 */ // GIR_Coverage, 322,
6102 /* 16558 */ GIR_EraseRootFromParent_Done,
6103 /* 16559 */ // Label 416: @16559
6104 /* 16559 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 417*/ GIMT_Encode4(16598), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 501 //
6105 /* 16566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6106 /* 16570 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6107 /* 16574 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6108 /* 16578 */ // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6109 /* 16578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MUL),
6110 /* 16581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6111 /* 16583 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6112 /* 16585 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6113 /* 16587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6114 /* 16590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6115 /* 16596 */ GIR_RootConstrainSelectedInstOperands,
6116 /* 16597 */ // GIR_Coverage, 501,
6117 /* 16597 */ GIR_EraseRootFromParent_Done,
6118 /* 16598 */ // Label 417: @16598
6119 /* 16598 */ GIM_Reject,
6120 /* 16599 */ // Label 404: @16599
6121 /* 16599 */ GIM_Reject,
6122 /* 16600 */ // Label 397: @16600
6123 /* 16600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 418*/ GIMT_Encode4(16645), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 955 //
6124 /* 16607 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
6125 /* 16610 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
6126 /* 16613 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6127 /* 16617 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6128 /* 16621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6129 /* 16625 */ // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
6130 /* 16625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i8),
6131 /* 16628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6132 /* 16630 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6133 /* 16632 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6134 /* 16634 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6135 /* 16637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6136 /* 16643 */ GIR_RootConstrainSelectedInstOperands,
6137 /* 16644 */ // GIR_Coverage, 955,
6138 /* 16644 */ GIR_EraseRootFromParent_Done,
6139 /* 16645 */ // Label 418: @16645
6140 /* 16645 */ GIM_Reject,
6141 /* 16646 */ // Label 398: @16646
6142 /* 16646 */ GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(16757),
6143 /* 16651 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
6144 /* 16654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
6145 /* 16657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 420*/ GIMT_Encode4(16696), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 958 //
6146 /* 16664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6147 /* 16668 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6148 /* 16672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6149 /* 16676 */ // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
6150 /* 16676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv16i8),
6151 /* 16679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6152 /* 16681 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6153 /* 16683 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6154 /* 16685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6155 /* 16688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6156 /* 16694 */ GIR_RootConstrainSelectedInstOperands,
6157 /* 16695 */ // GIR_Coverage, 958,
6158 /* 16695 */ GIR_EraseRootFromParent_Done,
6159 /* 16696 */ // Label 420: @16696
6160 /* 16696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 421*/ GIMT_Encode4(16756), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3855 //
6161 /* 16703 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6162 /* 16707 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6163 /* 16711 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6164 /* 16715 */ // (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
6165 /* 16715 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6166 /* 16718 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6167 /* 16722 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6168 /* 16727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi8),
6169 /* 16730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6170 /* 16732 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
6171 /* 16734 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
6172 /* 16736 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6173 /* 16739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6174 /* 16745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6175 /* 16751 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6176 /* 16754 */ GIR_RootConstrainSelectedInstOperands,
6177 /* 16755 */ // GIR_Coverage, 3855,
6178 /* 16755 */ GIR_EraseRootFromParent_Done,
6179 /* 16756 */ // Label 421: @16756
6180 /* 16756 */ GIM_Reject,
6181 /* 16757 */ // Label 419: @16757
6182 /* 16757 */ GIM_Reject,
6183 /* 16758 */ // Label 399: @16758
6184 /* 16758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 422*/ GIMT_Encode4(16803), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 956 //
6185 /* 16765 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
6186 /* 16768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
6187 /* 16771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6188 /* 16775 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6189 /* 16779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6190 /* 16783 */ // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
6191 /* 16783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i16),
6192 /* 16786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6193 /* 16788 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6194 /* 16790 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6195 /* 16792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6196 /* 16795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6197 /* 16801 */ GIR_RootConstrainSelectedInstOperands,
6198 /* 16802 */ // GIR_Coverage, 956,
6199 /* 16802 */ GIR_EraseRootFromParent_Done,
6200 /* 16803 */ // Label 422: @16803
6201 /* 16803 */ GIM_Reject,
6202 /* 16804 */ // Label 400: @16804
6203 /* 16804 */ GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(17029),
6204 /* 16809 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
6205 /* 16812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
6206 /* 16815 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 424*/ GIMT_Encode4(16929), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4937 //
6207 /* 16822 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6208 /* 16826 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6209 /* 16830 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6210 /* 16834 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
6211 /* 16838 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6212 /* 16843 */ // MIs[1] Operand 2
6213 /* 16843 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
6214 /* 16854 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6215 /* 16858 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6216 /* 16862 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
6217 /* 16866 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6218 /* 16871 */ // MIs[2] Operand 2
6219 /* 16871 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
6220 /* 16882 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6221 /* 16884 */ // (mul:{ *:[v8i16] } (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, v8i8:{ *:[Other] }), (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src2, v8i8:{ *:[Other] })) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)
6222 /* 16884 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6223 /* 16887 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6224 /* 16891 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6225 /* 16896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8),
6226 /* 16899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6227 /* 16901 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6228 /* 16905 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6229 /* 16909 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6230 /* 16912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6231 /* 16918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6232 /* 16924 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6233 /* 16927 */ GIR_RootConstrainSelectedInstOperands,
6234 /* 16928 */ // GIR_Coverage, 4937,
6235 /* 16928 */ GIR_EraseRootFromParent_Done,
6236 /* 16929 */ // Label 424: @16929
6237 /* 16929 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 425*/ GIMT_Encode4(16968), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 959 //
6238 /* 16936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6239 /* 16940 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6240 /* 16944 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6241 /* 16948 */ // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
6242 /* 16948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i16),
6243 /* 16951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6244 /* 16953 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6245 /* 16955 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6246 /* 16957 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6247 /* 16960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6248 /* 16966 */ GIR_RootConstrainSelectedInstOperands,
6249 /* 16967 */ // GIR_Coverage, 959,
6250 /* 16967 */ GIR_EraseRootFromParent_Done,
6251 /* 16968 */ // Label 425: @16968
6252 /* 16968 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 426*/ GIMT_Encode4(17028), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3859 //
6253 /* 16975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6254 /* 16979 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6255 /* 16983 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6256 /* 16987 */ // (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
6257 /* 16987 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6258 /* 16990 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6259 /* 16994 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6260 /* 16999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi16),
6261 /* 17002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6262 /* 17004 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
6263 /* 17006 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
6264 /* 17008 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6265 /* 17011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6266 /* 17017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6267 /* 17023 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6268 /* 17026 */ GIR_RootConstrainSelectedInstOperands,
6269 /* 17027 */ // GIR_Coverage, 3859,
6270 /* 17027 */ GIR_EraseRootFromParent_Done,
6271 /* 17028 */ // Label 426: @17028
6272 /* 17028 */ GIM_Reject,
6273 /* 17029 */ // Label 423: @17029
6274 /* 17029 */ GIM_Reject,
6275 /* 17030 */ // Label 401: @17030
6276 /* 17030 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 427*/ GIMT_Encode4(17075), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 957 //
6277 /* 17037 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
6278 /* 17040 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
6279 /* 17043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6280 /* 17047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6281 /* 17051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6282 /* 17055 */ // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
6283 /* 17055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv2i32),
6284 /* 17058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6285 /* 17060 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6286 /* 17062 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6287 /* 17064 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6288 /* 17067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6289 /* 17073 */ GIR_RootConstrainSelectedInstOperands,
6290 /* 17074 */ // GIR_Coverage, 957,
6291 /* 17074 */ GIR_EraseRootFromParent_Done,
6292 /* 17075 */ // Label 427: @17075
6293 /* 17075 */ GIM_Reject,
6294 /* 17076 */ // Label 402: @17076
6295 /* 17076 */ GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(17301),
6296 /* 17081 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
6297 /* 17084 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
6298 /* 17087 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 429*/ GIMT_Encode4(17201), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4932 //
6299 /* 17094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6300 /* 17098 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6301 /* 17102 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6302 /* 17106 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6303 /* 17110 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6304 /* 17115 */ // MIs[1] Operand 2
6305 /* 17115 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6306 /* 17126 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6307 /* 17130 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6308 /* 17134 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6309 /* 17138 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6310 /* 17143 */ // MIs[2] Operand 2
6311 /* 17143 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6312 /* 17154 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6313 /* 17156 */ // (mul:{ *:[v4i32] } (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, v4i16:{ *:[Other] }), (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src2, v4i16:{ *:[Other] })) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)
6314 /* 17156 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6315 /* 17159 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6316 /* 17163 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6317 /* 17168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16),
6318 /* 17171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6319 /* 17173 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6320 /* 17177 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6321 /* 17181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6322 /* 17184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6323 /* 17190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6324 /* 17196 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6325 /* 17199 */ GIR_RootConstrainSelectedInstOperands,
6326 /* 17200 */ // GIR_Coverage, 4932,
6327 /* 17200 */ GIR_EraseRootFromParent_Done,
6328 /* 17201 */ // Label 429: @17201
6329 /* 17201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 430*/ GIMT_Encode4(17240), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 960 //
6330 /* 17208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6331 /* 17212 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6332 /* 17216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6333 /* 17220 */ // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
6334 /* 17220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i32),
6335 /* 17223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6336 /* 17225 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6337 /* 17227 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6338 /* 17229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6339 /* 17232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6340 /* 17238 */ GIR_RootConstrainSelectedInstOperands,
6341 /* 17239 */ // GIR_Coverage, 960,
6342 /* 17239 */ GIR_EraseRootFromParent_Done,
6343 /* 17240 */ // Label 430: @17240
6344 /* 17240 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 431*/ GIMT_Encode4(17300), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3863 //
6345 /* 17247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6346 /* 17251 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6347 /* 17255 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6348 /* 17259 */ // (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
6349 /* 17259 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6350 /* 17262 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6351 /* 17266 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6352 /* 17271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi32),
6353 /* 17274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6354 /* 17276 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
6355 /* 17278 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
6356 /* 17280 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6357 /* 17283 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6358 /* 17289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6359 /* 17295 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6360 /* 17298 */ GIR_RootConstrainSelectedInstOperands,
6361 /* 17299 */ // GIR_Coverage, 3863,
6362 /* 17299 */ GIR_EraseRootFromParent_Done,
6363 /* 17300 */ // Label 431: @17300
6364 /* 17300 */ GIM_Reject,
6365 /* 17301 */ // Label 428: @17301
6366 /* 17301 */ GIM_Reject,
6367 /* 17302 */ // Label 403: @17302
6368 /* 17302 */ GIM_Reject,
6369 /* 17303 */ // Label 3: @17303
6370 /* 17303 */ GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(17396),
6371 /* 17308 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
6372 /* 17311 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
6373 /* 17314 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6374 /* 17317 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 433*/ GIMT_Encode4(17356), GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), // Rule ID 194 //
6375 /* 17324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6376 /* 17328 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6377 /* 17332 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6378 /* 17336 */ // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6379 /* 17336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SDIV),
6380 /* 17339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6381 /* 17341 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6382 /* 17343 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6383 /* 17345 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6384 /* 17348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6385 /* 17354 */ GIR_RootConstrainSelectedInstOperands,
6386 /* 17355 */ // GIR_Coverage, 194,
6387 /* 17355 */ GIR_EraseRootFromParent_Done,
6388 /* 17356 */ // Label 433: @17356
6389 /* 17356 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 434*/ GIMT_Encode4(17395), GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), // Rule ID 531 //
6390 /* 17363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6391 /* 17367 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6392 /* 17371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6393 /* 17375 */ // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6394 /* 17375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SDIV),
6395 /* 17378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6396 /* 17380 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6397 /* 17382 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6398 /* 17384 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6399 /* 17387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6400 /* 17393 */ GIR_RootConstrainSelectedInstOperands,
6401 /* 17394 */ // GIR_Coverage, 531,
6402 /* 17394 */ GIR_EraseRootFromParent_Done,
6403 /* 17395 */ // Label 434: @17395
6404 /* 17395 */ GIM_Reject,
6405 /* 17396 */ // Label 432: @17396
6406 /* 17396 */ GIM_Reject,
6407 /* 17397 */ // Label 4: @17397
6408 /* 17397 */ GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(17490),
6409 /* 17402 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
6410 /* 17405 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
6411 /* 17408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6412 /* 17411 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 436*/ GIMT_Encode4(17450), GIMT_Encode2(GIFBS_HasDivideInARM_IsARM), // Rule ID 195 //
6413 /* 17418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6414 /* 17422 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6415 /* 17426 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6416 /* 17430 */ // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6417 /* 17430 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDIV),
6418 /* 17433 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6419 /* 17435 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6420 /* 17437 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6421 /* 17439 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6422 /* 17442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6423 /* 17448 */ GIR_RootConstrainSelectedInstOperands,
6424 /* 17449 */ // GIR_Coverage, 195,
6425 /* 17449 */ GIR_EraseRootFromParent_Done,
6426 /* 17450 */ // Label 436: @17450
6427 /* 17450 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 437*/ GIMT_Encode4(17489), GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb), // Rule ID 532 //
6428 /* 17457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6429 /* 17461 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6430 /* 17465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6431 /* 17469 */ // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6432 /* 17469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDIV),
6433 /* 17472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6434 /* 17474 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6435 /* 17476 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6436 /* 17478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6437 /* 17481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6438 /* 17487 */ GIR_RootConstrainSelectedInstOperands,
6439 /* 17488 */ // GIR_Coverage, 532,
6440 /* 17488 */ GIR_EraseRootFromParent_Done,
6441 /* 17489 */ // Label 437: @17489
6442 /* 17489 */ GIM_Reject,
6443 /* 17490 */ // Label 435: @17490
6444 /* 17490 */ GIM_Reject,
6445 /* 17491 */ // Label 5: @17491
6446 /* 17491 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 451*/ GIMT_Encode4(20590),
6447 /* 17502 */ /*GILLT_s32*//*Label 438*/ GIMT_Encode4(17554),
6448 /* 17506 */ /*GILLT_s64*//*Label 439*/ GIMT_Encode4(19490),
6449 /* 17510 */ /*GILLT_v2s1*//*Label 440*/ GIMT_Encode4(19536),
6450 /* 17514 */ /*GILLT_v4s1*//*Label 441*/ GIMT_Encode4(19653),
6451 /* 17518 */ /*GILLT_v8s1*//*Label 442*/ GIMT_Encode4(19770),
6452 /* 17522 */ /*GILLT_v16s1*//*Label 443*/ GIMT_Encode4(19887),
6453 /* 17526 */ /*GILLT_v8s8*//*Label 444*/ GIMT_Encode4(20004),
6454 /* 17530 */ /*GILLT_v16s8*//*Label 445*/ GIMT_Encode4(20050),
6455 /* 17534 */ /*GILLT_v4s16*//*Label 446*/ GIMT_Encode4(20162),
6456 /* 17538 */ /*GILLT_v8s16*//*Label 447*/ GIMT_Encode4(20208),
6457 /* 17542 */ /*GILLT_v2s32*//*Label 448*/ GIMT_Encode4(20320),
6458 /* 17546 */ /*GILLT_v4s32*//*Label 449*/ GIMT_Encode4(20366),
6459 /* 17550 */ /*GILLT_v2s64*//*Label 450*/ GIMT_Encode4(20478),
6460 /* 17554 */ // Label 438: @17554
6461 /* 17554 */ GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(19489),
6462 /* 17559 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
6463 /* 17562 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6464 /* 17565 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 453*/ GIMT_Encode4(17637), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2043 //
6465 /* 17572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6466 /* 17576 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6467 /* 17580 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
6468 /* 17584 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6469 /* 17588 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6470 /* 17592 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6471 /* 17597 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8,
6472 /* 17601 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6473 /* 17612 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6474 /* 17614 */ // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
6475 /* 17614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16),
6476 /* 17617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6477 /* 17619 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
6478 /* 17623 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
6479 /* 17626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6480 /* 17629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6481 /* 17635 */ GIR_RootConstrainSelectedInstOperands,
6482 /* 17636 */ // GIR_Coverage, 2043,
6483 /* 17636 */ GIR_EraseRootFromParent_Done,
6484 /* 17637 */ // Label 453: @17637
6485 /* 17637 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 454*/ GIMT_Encode4(17709), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2308 //
6486 /* 17644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6487 /* 17648 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6488 /* 17652 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
6489 /* 17656 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6490 /* 17660 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6491 /* 17664 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6492 /* 17669 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8,
6493 /* 17673 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6494 /* 17684 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6495 /* 17686 */ // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
6496 /* 17686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16),
6497 /* 17689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6498 /* 17691 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
6499 /* 17695 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
6500 /* 17698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6501 /* 17701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6502 /* 17707 */ GIR_RootConstrainSelectedInstOperands,
6503 /* 17708 */ // GIR_Coverage, 2308,
6504 /* 17708 */ GIR_EraseRootFromParent_Done,
6505 /* 17709 */ // Label 454: @17709
6506 /* 17709 */ GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(17840),
6507 /* 17714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6508 /* 17718 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6509 /* 17722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 456*/ GIMT_Encode4(17761), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2192 //
6510 /* 17729 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
6511 /* 17740 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] }) => (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
6512 /* 17740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB),
6513 /* 17743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6514 /* 17745 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
6515 /* 17747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6516 /* 17750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6517 /* 17753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6518 /* 17759 */ GIR_RootConstrainSelectedInstOperands,
6519 /* 17760 */ // GIR_Coverage, 2192,
6520 /* 17760 */ GIR_EraseRootFromParent_Done,
6521 /* 17761 */ // Label 456: @17761
6522 /* 17761 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 457*/ GIMT_Encode4(17800), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2193 //
6523 /* 17768 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
6524 /* 17779 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] }) => (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
6525 /* 17779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTH),
6526 /* 17782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6527 /* 17784 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
6528 /* 17786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6529 /* 17789 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6530 /* 17792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6531 /* 17798 */ GIR_RootConstrainSelectedInstOperands,
6532 /* 17799 */ // GIR_Coverage, 2193,
6533 /* 17799 */ GIR_EraseRootFromParent_Done,
6534 /* 17800 */ // Label 457: @17800
6535 /* 17800 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 458*/ GIMT_Encode4(17839), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2194 //
6536 /* 17807 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6537 /* 17818 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
6538 /* 17818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16),
6539 /* 17821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6540 /* 17823 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
6541 /* 17825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6542 /* 17828 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6543 /* 17831 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6544 /* 17837 */ GIR_RootConstrainSelectedInstOperands,
6545 /* 17838 */ // GIR_Coverage, 2194,
6546 /* 17838 */ GIR_EraseRootFromParent_Done,
6547 /* 17839 */ // Label 458: @17839
6548 /* 17839 */ GIM_Reject,
6549 /* 17840 */ // Label 455: @17840
6550 /* 17840 */ GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(17971),
6551 /* 17845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6552 /* 17849 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6553 /* 17853 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 460*/ GIMT_Encode4(17892), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2436 //
6554 /* 17860 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
6555 /* 17871 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
6556 /* 17871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB),
6557 /* 17874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6558 /* 17876 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6559 /* 17878 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6560 /* 17881 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6561 /* 17884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6562 /* 17890 */ GIR_RootConstrainSelectedInstOperands,
6563 /* 17891 */ // GIR_Coverage, 2436,
6564 /* 17891 */ GIR_EraseRootFromParent_Done,
6565 /* 17892 */ // Label 460: @17892
6566 /* 17892 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 461*/ GIMT_Encode4(17931), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2437 //
6567 /* 17899 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
6568 /* 17910 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
6569 /* 17910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTH),
6570 /* 17913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6571 /* 17915 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6572 /* 17917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6573 /* 17920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6574 /* 17923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6575 /* 17929 */ GIR_RootConstrainSelectedInstOperands,
6576 /* 17930 */ // GIR_Coverage, 2437,
6577 /* 17930 */ GIR_EraseRootFromParent_Done,
6578 /* 17931 */ // Label 461: @17931
6579 /* 17931 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 462*/ GIMT_Encode4(17970), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2438 //
6580 /* 17938 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6581 /* 17949 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
6582 /* 17949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16),
6583 /* 17952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6584 /* 17954 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6585 /* 17956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6586 /* 17959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6587 /* 17962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6588 /* 17968 */ GIR_RootConstrainSelectedInstOperands,
6589 /* 17969 */ // GIR_Coverage, 2438,
6590 /* 17969 */ GIR_EraseRootFromParent_Done,
6591 /* 17970 */ // Label 462: @17970
6592 /* 17970 */ GIM_Reject,
6593 /* 17971 */ // Label 459: @17971
6594 /* 17971 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 463*/ GIMT_Encode4(18047), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5974 //
6595 /* 17978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6596 /* 17982 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6597 /* 17986 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6598 /* 17990 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6599 /* 17994 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6600 /* 17998 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6601 /* 18002 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6602 /* 18006 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6603 /* 18010 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6604 /* 18014 */ // MIs[2] Operand 1
6605 /* 18014 */ // No operand predicates
6606 /* 18014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6607 /* 18018 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6608 /* 18020 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6609 /* 18020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6610 /* 18023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6611 /* 18025 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6612 /* 18027 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6613 /* 18030 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6614 /* 18033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6615 /* 18039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6616 /* 18045 */ GIR_RootConstrainSelectedInstOperands,
6617 /* 18046 */ // GIR_Coverage, 5974,
6618 /* 18046 */ GIR_EraseRootFromParent_Done,
6619 /* 18047 */ // Label 463: @18047
6620 /* 18047 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 464*/ GIMT_Encode4(18123), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6005 //
6621 /* 18054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6622 /* 18058 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6623 /* 18062 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6624 /* 18066 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6625 /* 18070 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6626 /* 18074 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6627 /* 18078 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6628 /* 18082 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6629 /* 18086 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
6630 /* 18090 */ // MIs[2] Operand 1
6631 /* 18090 */ // No operand predicates
6632 /* 18090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6633 /* 18094 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6634 /* 18096 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6635 /* 18096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
6636 /* 18099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6637 /* 18101 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6638 /* 18103 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6639 /* 18106 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6640 /* 18109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6641 /* 18115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6642 /* 18121 */ GIR_RootConstrainSelectedInstOperands,
6643 /* 18122 */ // GIR_Coverage, 6005,
6644 /* 18122 */ GIR_EraseRootFromParent_Done,
6645 /* 18123 */ // Label 464: @18123
6646 /* 18123 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 465*/ GIMT_Encode4(18199), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5973 //
6647 /* 18130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6648 /* 18134 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6649 /* 18138 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6650 /* 18142 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6651 /* 18146 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6652 /* 18150 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6653 /* 18154 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6654 /* 18158 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6655 /* 18162 */ // MIs[2] Operand 1
6656 /* 18162 */ // No operand predicates
6657 /* 18162 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6658 /* 18166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6659 /* 18170 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6660 /* 18172 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6661 /* 18172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6662 /* 18175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6663 /* 18177 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6664 /* 18179 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6665 /* 18182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6666 /* 18185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6667 /* 18191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6668 /* 18197 */ GIR_RootConstrainSelectedInstOperands,
6669 /* 18198 */ // GIR_Coverage, 5973,
6670 /* 18198 */ GIR_EraseRootFromParent_Done,
6671 /* 18199 */ // Label 465: @18199
6672 /* 18199 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 466*/ GIMT_Encode4(18275), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6004 //
6673 /* 18206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6674 /* 18210 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6675 /* 18214 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6676 /* 18218 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6677 /* 18222 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6678 /* 18226 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6679 /* 18230 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6680 /* 18234 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
6681 /* 18238 */ // MIs[2] Operand 1
6682 /* 18238 */ // No operand predicates
6683 /* 18238 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6684 /* 18242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6685 /* 18246 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6686 /* 18248 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6687 /* 18248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
6688 /* 18251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6689 /* 18253 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6690 /* 18255 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6691 /* 18258 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6692 /* 18261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6693 /* 18267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6694 /* 18273 */ GIR_RootConstrainSelectedInstOperands,
6695 /* 18274 */ // GIR_Coverage, 6004,
6696 /* 18274 */ GIR_EraseRootFromParent_Done,
6697 /* 18275 */ // Label 466: @18275
6698 /* 18275 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 467*/ GIMT_Encode4(18351), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5972 //
6699 /* 18282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6700 /* 18286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6701 /* 18290 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6702 /* 18294 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6703 /* 18298 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6704 /* 18302 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6705 /* 18306 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6706 /* 18310 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6707 /* 18314 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6708 /* 18318 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6709 /* 18322 */ // MIs[2] Operand 1
6710 /* 18322 */ // No operand predicates
6711 /* 18322 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6712 /* 18324 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6713 /* 18324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6714 /* 18327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6715 /* 18329 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6716 /* 18331 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6717 /* 18334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6718 /* 18337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6719 /* 18343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6720 /* 18349 */ GIR_RootConstrainSelectedInstOperands,
6721 /* 18350 */ // GIR_Coverage, 5972,
6722 /* 18350 */ GIR_EraseRootFromParent_Done,
6723 /* 18351 */ // Label 467: @18351
6724 /* 18351 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 468*/ GIMT_Encode4(18427), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6003 //
6725 /* 18358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6726 /* 18362 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6727 /* 18366 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6728 /* 18370 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6729 /* 18374 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6730 /* 18378 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6731 /* 18382 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6732 /* 18386 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6733 /* 18390 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6734 /* 18394 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
6735 /* 18398 */ // MIs[2] Operand 1
6736 /* 18398 */ // No operand predicates
6737 /* 18398 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6738 /* 18400 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6739 /* 18400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
6740 /* 18403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6741 /* 18405 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6742 /* 18407 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6743 /* 18410 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6744 /* 18413 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6745 /* 18419 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6746 /* 18425 */ GIR_RootConstrainSelectedInstOperands,
6747 /* 18426 */ // GIR_Coverage, 6003,
6748 /* 18426 */ GIR_EraseRootFromParent_Done,
6749 /* 18427 */ // Label 468: @18427
6750 /* 18427 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 469*/ GIMT_Encode4(18503), GIMT_Encode2(GIFBS_IsARM), // Rule ID 158 //
6751 /* 18434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6752 /* 18438 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6753 /* 18442 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6754 /* 18446 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6755 /* 18450 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6756 /* 18454 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6757 /* 18458 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6758 /* 18462 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6759 /* 18466 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6760 /* 18470 */ // MIs[2] Operand 1
6761 /* 18470 */ // No operand predicates
6762 /* 18470 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6763 /* 18474 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6764 /* 18476 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] })) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6765 /* 18476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6766 /* 18479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6767 /* 18481 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6768 /* 18483 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6769 /* 18486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6770 /* 18489 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6771 /* 18495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6772 /* 18501 */ GIR_RootConstrainSelectedInstOperands,
6773 /* 18502 */ // GIR_Coverage, 158,
6774 /* 18502 */ GIR_EraseRootFromParent_Done,
6775 /* 18503 */ // Label 469: @18503
6776 /* 18503 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 470*/ GIMT_Encode4(18579), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 489 //
6777 /* 18510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6778 /* 18514 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6779 /* 18518 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6780 /* 18522 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6781 /* 18526 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6782 /* 18530 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6783 /* 18534 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6784 /* 18538 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6785 /* 18542 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
6786 /* 18546 */ // MIs[2] Operand 1
6787 /* 18546 */ // No operand predicates
6788 /* 18546 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6789 /* 18550 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6790 /* 18552 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6791 /* 18552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
6792 /* 18555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6793 /* 18557 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6794 /* 18559 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6795 /* 18562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6796 /* 18565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6797 /* 18571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6798 /* 18577 */ GIR_RootConstrainSelectedInstOperands,
6799 /* 18578 */ // GIR_Coverage, 489,
6800 /* 18578 */ GIR_EraseRootFromParent_Done,
6801 /* 18579 */ // Label 470: @18579
6802 /* 18579 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 471*/ GIMT_Encode4(18649), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5975 //
6803 /* 18586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6804 /* 18590 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6805 /* 18594 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6806 /* 18598 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6807 /* 18602 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6808 /* 18606 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6809 /* 18611 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6810 /* 18615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6811 /* 18619 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6812 /* 18621 */ // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6813 /* 18621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr),
6814 /* 18624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6815 /* 18626 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6816 /* 18628 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6817 /* 18632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6818 /* 18635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6819 /* 18641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6820 /* 18647 */ GIR_RootConstrainSelectedInstOperands,
6821 /* 18648 */ // GIR_Coverage, 5975,
6822 /* 18648 */ GIR_EraseRootFromParent_Done,
6823 /* 18649 */ // Label 471: @18649
6824 /* 18649 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 472*/ GIMT_Encode4(18719), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 5995 //
6825 /* 18656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6826 /* 18660 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6827 /* 18664 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6828 /* 18668 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6829 /* 18672 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6830 /* 18676 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6831 /* 18681 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6832 /* 18685 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6833 /* 18689 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6834 /* 18691 */ // (and:{ *:[i32] } (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), tGPR:{ *:[i32] }:$Rn) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
6835 /* 18691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC),
6836 /* 18694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
6837 /* 18696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
6838 /* 18702 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6839 /* 18704 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6840 /* 18708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6841 /* 18711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6842 /* 18717 */ GIR_RootConstrainSelectedInstOperands,
6843 /* 18718 */ // GIR_Coverage, 5995,
6844 /* 18718 */ GIR_EraseRootFromParent_Done,
6845 /* 18719 */ // Label 472: @18719
6846 /* 18719 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 473*/ GIMT_Encode4(18789), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6006 //
6847 /* 18726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6848 /* 18730 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6849 /* 18734 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6850 /* 18738 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6851 /* 18742 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6852 /* 18746 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6853 /* 18751 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6854 /* 18755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6855 /* 18759 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6856 /* 18761 */ // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6857 /* 18761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr),
6858 /* 18764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6859 /* 18766 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6860 /* 18768 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6861 /* 18772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6862 /* 18775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6863 /* 18781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6864 /* 18787 */ GIR_RootConstrainSelectedInstOperands,
6865 /* 18788 */ // GIR_Coverage, 6006,
6866 /* 18788 */ GIR_EraseRootFromParent_Done,
6867 /* 18789 */ // Label 473: @18789
6868 /* 18789 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 474*/ GIMT_Encode4(18859), GIMT_Encode2(GIFBS_IsARM), // Rule ID 159 //
6869 /* 18796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6870 /* 18800 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6871 /* 18804 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6872 /* 18808 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6873 /* 18812 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6874 /* 18816 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6875 /* 18820 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6876 /* 18825 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6877 /* 18829 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6878 /* 18831 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6879 /* 18831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr),
6880 /* 18834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6881 /* 18836 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6882 /* 18838 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6883 /* 18842 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6884 /* 18845 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6885 /* 18851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6886 /* 18857 */ GIR_RootConstrainSelectedInstOperands,
6887 /* 18858 */ // GIR_Coverage, 159,
6888 /* 18858 */ GIR_EraseRootFromParent_Done,
6889 /* 18859 */ // Label 474: @18859
6890 /* 18859 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 475*/ GIMT_Encode4(18929), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 312 //
6891 /* 18866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6892 /* 18870 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6893 /* 18874 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6894 /* 18878 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6895 /* 18882 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6896 /* 18886 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6897 /* 18890 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6898 /* 18895 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6899 /* 18899 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6900 /* 18901 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
6901 /* 18901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC),
6902 /* 18904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
6903 /* 18906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
6904 /* 18912 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6905 /* 18914 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6906 /* 18918 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6907 /* 18921 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6908 /* 18927 */ GIR_RootConstrainSelectedInstOperands,
6909 /* 18928 */ // GIR_Coverage, 312,
6910 /* 18928 */ GIR_EraseRootFromParent_Done,
6911 /* 18929 */ // Label 475: @18929
6912 /* 18929 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 476*/ GIMT_Encode4(18999), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 490 //
6913 /* 18936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6914 /* 18940 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6915 /* 18944 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6916 /* 18948 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6917 /* 18952 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6918 /* 18956 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6919 /* 18960 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6920 /* 18965 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6921 /* 18969 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6922 /* 18971 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6923 /* 18971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr),
6924 /* 18974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6925 /* 18976 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6926 /* 18978 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
6927 /* 18982 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6928 /* 18985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6929 /* 18991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6930 /* 18997 */ GIR_RootConstrainSelectedInstOperands,
6931 /* 18998 */ // GIR_Coverage, 490,
6932 /* 18998 */ GIR_EraseRootFromParent_Done,
6933 /* 18999 */ // Label 476: @18999
6934 /* 18999 */ GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(19085),
6935 /* 19004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6936 /* 19008 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6937 /* 19012 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 478*/ GIMT_Encode4(19048), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 344 //
6938 /* 19019 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
6939 /* 19030 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
6940 /* 19030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTB),
6941 /* 19033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6942 /* 19035 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6943 /* 19037 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6944 /* 19040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6945 /* 19046 */ GIR_RootConstrainSelectedInstOperands,
6946 /* 19047 */ // GIR_Coverage, 344,
6947 /* 19047 */ GIR_EraseRootFromParent_Done,
6948 /* 19048 */ // Label 478: @19048
6949 /* 19048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 479*/ GIMT_Encode4(19084), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 345 //
6950 /* 19055 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
6951 /* 19066 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
6952 /* 19066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTH),
6953 /* 19069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6954 /* 19071 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6955 /* 19073 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6956 /* 19076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6957 /* 19082 */ GIR_RootConstrainSelectedInstOperands,
6958 /* 19083 */ // GIR_Coverage, 345,
6959 /* 19083 */ GIR_EraseRootFromParent_Done,
6960 /* 19084 */ // Label 479: @19084
6961 /* 19084 */ GIM_Reject,
6962 /* 19085 */ // Label 477: @19085
6963 /* 19085 */ GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(19197),
6964 /* 19090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6965 /* 19094 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6966 /* 19098 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 481*/ GIMT_Encode4(19148), GIMT_Encode2(GIFBS_IsARM), // Rule ID 2082 //
6967 /* 19105 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6968 /* 19109 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6969 /* 19113 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not),
6970 /* 19117 */ // MIs[1] Operand 1
6971 /* 19117 */ // No operand predicates
6972 /* 19117 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6973 /* 19119 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>>:$imm))
6974 /* 19119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6975 /* 19122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6976 /* 19124 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
6977 /* 19126 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm
6978 /* 19131 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6979 /* 19134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6980 /* 19140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6981 /* 19146 */ GIR_RootConstrainSelectedInstOperands,
6982 /* 19147 */ // GIR_Coverage, 2082,
6983 /* 19147 */ GIR_EraseRootFromParent_Done,
6984 /* 19148 */ // Label 481: @19148
6985 /* 19148 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 482*/ GIMT_Encode4(19196), GIMT_Encode2(GIFBS_IsARM), // Rule ID 146 //
6986 /* 19155 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6987 /* 19159 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6988 /* 19163 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6989 /* 19167 */ // MIs[1] Operand 1
6990 /* 19167 */ // No operand predicates
6991 /* 19167 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6992 /* 19169 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6993 /* 19169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDri),
6994 /* 19172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6995 /* 19174 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6996 /* 19176 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
6997 /* 19179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6998 /* 19182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6999 /* 19188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7000 /* 19194 */ GIR_RootConstrainSelectedInstOperands,
7001 /* 19195 */ // GIR_Coverage, 146,
7002 /* 19195 */ GIR_EraseRootFromParent_Done,
7003 /* 19196 */ // Label 482: @19196
7004 /* 19196 */ GIM_Reject,
7005 /* 19197 */ // Label 480: @19197
7006 /* 19197 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 483*/ GIMT_Encode4(19253), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 480 //
7007 /* 19204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7008 /* 19208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7009 /* 19212 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7010 /* 19216 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7011 /* 19220 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
7012 /* 19224 */ // MIs[1] Operand 1
7013 /* 19224 */ // No operand predicates
7014 /* 19224 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7015 /* 19226 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7016 /* 19226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDri),
7017 /* 19229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7018 /* 19231 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7019 /* 19233 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7020 /* 19236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7021 /* 19239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7022 /* 19245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7023 /* 19251 */ GIR_RootConstrainSelectedInstOperands,
7024 /* 19252 */ // GIR_Coverage, 480,
7025 /* 19252 */ GIR_EraseRootFromParent_Done,
7026 /* 19253 */ // Label 483: @19253
7027 /* 19253 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 484*/ GIMT_Encode4(19303), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 162 //
7028 /* 19260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7029 /* 19264 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7030 /* 19268 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7031 /* 19272 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7032 /* 19276 */ // MIs[1] Operand 1
7033 /* 19276 */ // No operand predicates
7034 /* 19276 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm),
7035 /* 19280 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7036 /* 19282 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
7037 /* 19282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BFC),
7038 /* 19285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7039 /* 19287 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
7040 /* 19289 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7041 /* 19292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7042 /* 19295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7043 /* 19301 */ GIR_RootConstrainSelectedInstOperands,
7044 /* 19302 */ // GIR_Coverage, 162,
7045 /* 19302 */ GIR_EraseRootFromParent_Done,
7046 /* 19303 */ // Label 484: @19303
7047 /* 19303 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 485*/ GIMT_Encode4(19353), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 492 //
7048 /* 19310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7049 /* 19314 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7050 /* 19318 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7051 /* 19322 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7052 /* 19326 */ // MIs[1] Operand 1
7053 /* 19326 */ // No operand predicates
7054 /* 19326 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm),
7055 /* 19330 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7056 /* 19332 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
7057 /* 19332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BFC),
7058 /* 19335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7059 /* 19337 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
7060 /* 19339 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7061 /* 19342 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7062 /* 19345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7063 /* 19351 */ GIR_RootConstrainSelectedInstOperands,
7064 /* 19352 */ // GIR_Coverage, 492,
7065 /* 19352 */ GIR_EraseRootFromParent_Done,
7066 /* 19353 */ // Label 485: @19353
7067 /* 19353 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 486*/ GIMT_Encode4(19398), GIMT_Encode2(GIFBS_IsARM), // Rule ID 147 //
7068 /* 19360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7069 /* 19364 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7070 /* 19368 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7071 /* 19372 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
7072 /* 19372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDrr),
7073 /* 19375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7074 /* 19377 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7075 /* 19379 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
7076 /* 19381 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7077 /* 19384 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7078 /* 19390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7079 /* 19396 */ GIR_RootConstrainSelectedInstOperands,
7080 /* 19397 */ // GIR_Coverage, 147,
7081 /* 19397 */ GIR_EraseRootFromParent_Done,
7082 /* 19398 */ // Label 486: @19398
7083 /* 19398 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 487*/ GIMT_Encode4(19443), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 309 //
7084 /* 19405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7085 /* 19409 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7086 /* 19413 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7087 /* 19417 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tAND:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
7088 /* 19417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tAND),
7089 /* 19420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
7090 /* 19422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
7091 /* 19428 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7092 /* 19430 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
7093 /* 19432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7094 /* 19435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7095 /* 19441 */ GIR_RootConstrainSelectedInstOperands,
7096 /* 19442 */ // GIR_Coverage, 309,
7097 /* 19442 */ GIR_EraseRootFromParent_Done,
7098 /* 19443 */ // Label 487: @19443
7099 /* 19443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 488*/ GIMT_Encode4(19488), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 481 //
7100 /* 19450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7101 /* 19454 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7102 /* 19458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7103 /* 19462 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7104 /* 19462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7105 /* 19465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7106 /* 19467 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7107 /* 19469 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
7108 /* 19471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7109 /* 19474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7110 /* 19480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7111 /* 19486 */ GIR_RootConstrainSelectedInstOperands,
7112 /* 19487 */ // GIR_Coverage, 481,
7113 /* 19487 */ GIR_EraseRootFromParent_Done,
7114 /* 19488 */ // Label 488: @19488
7115 /* 19488 */ GIM_Reject,
7116 /* 19489 */ // Label 452: @19489
7117 /* 19489 */ GIM_Reject,
7118 /* 19490 */ // Label 439: @19490
7119 /* 19490 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 489*/ GIMT_Encode4(19535), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2915 //
7120 /* 19497 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
7121 /* 19500 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
7122 /* 19503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7123 /* 19507 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7124 /* 19511 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7125 /* 19515 */ // (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VANDd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
7126 /* 19515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7127 /* 19518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7128 /* 19520 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7129 /* 19522 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7130 /* 19524 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7131 /* 19527 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7132 /* 19533 */ GIR_RootConstrainSelectedInstOperands,
7133 /* 19534 */ // GIR_Coverage, 2915,
7134 /* 19534 */ GIR_EraseRootFromParent_Done,
7135 /* 19535 */ // Label 489: @19535
7136 /* 19535 */ GIM_Reject,
7137 /* 19536 */ // Label 440: @19536
7138 /* 19536 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 490*/ GIMT_Encode4(19652), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2014 //
7139 /* 19543 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1,
7140 /* 19546 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1,
7141 /* 19549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7142 /* 19553 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7143 /* 19557 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7144 /* 19561 */ // (and:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7145 /* 19561 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7146 /* 19564 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7147 /* 19568 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7148 /* 19573 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7149 /* 19577 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7150 /* 19582 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7151 /* 19585 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7152 /* 19589 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7153 /* 19594 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7154 /* 19598 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7155 /* 19603 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7156 /* 19606 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7157 /* 19610 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7158 /* 19615 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7159 /* 19618 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7160 /* 19621 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7161 /* 19624 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7162 /* 19630 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7163 /* 19636 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7164 /* 19638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7165 /* 19641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7166 /* 19643 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7167 /* 19646 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7168 /* 19651 */ // GIR_Coverage, 2014,
7169 /* 19651 */ GIR_EraseRootFromParent_Done,
7170 /* 19652 */ // Label 490: @19652
7171 /* 19652 */ GIM_Reject,
7172 /* 19653 */ // Label 441: @19653
7173 /* 19653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 491*/ GIMT_Encode4(19769), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2015 //
7174 /* 19660 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1,
7175 /* 19663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1,
7176 /* 19666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7177 /* 19670 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7178 /* 19674 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7179 /* 19678 */ // (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7180 /* 19678 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7181 /* 19681 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7182 /* 19685 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7183 /* 19690 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7184 /* 19694 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7185 /* 19699 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7186 /* 19702 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7187 /* 19706 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7188 /* 19711 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7189 /* 19715 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7190 /* 19720 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7191 /* 19723 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7192 /* 19727 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7193 /* 19732 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7194 /* 19735 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7195 /* 19738 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7196 /* 19741 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7197 /* 19747 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7198 /* 19753 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7199 /* 19755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7200 /* 19758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7201 /* 19760 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7202 /* 19763 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7203 /* 19768 */ // GIR_Coverage, 2015,
7204 /* 19768 */ GIR_EraseRootFromParent_Done,
7205 /* 19769 */ // Label 491: @19769
7206 /* 19769 */ GIM_Reject,
7207 /* 19770 */ // Label 442: @19770
7208 /* 19770 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 492*/ GIMT_Encode4(19886), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2016 //
7209 /* 19777 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1,
7210 /* 19780 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1,
7211 /* 19783 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7212 /* 19787 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7213 /* 19791 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7214 /* 19795 */ // (and:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7215 /* 19795 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7216 /* 19798 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7217 /* 19802 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7218 /* 19807 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7219 /* 19811 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7220 /* 19816 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7221 /* 19819 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7222 /* 19823 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7223 /* 19828 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7224 /* 19832 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7225 /* 19837 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7226 /* 19840 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7227 /* 19844 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7228 /* 19849 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7229 /* 19852 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7230 /* 19855 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7231 /* 19858 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7232 /* 19864 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7233 /* 19870 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7234 /* 19872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7235 /* 19875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7236 /* 19877 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7237 /* 19880 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7238 /* 19885 */ // GIR_Coverage, 2016,
7239 /* 19885 */ GIR_EraseRootFromParent_Done,
7240 /* 19886 */ // Label 492: @19886
7241 /* 19886 */ GIM_Reject,
7242 /* 19887 */ // Label 443: @19887
7243 /* 19887 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 493*/ GIMT_Encode4(20003), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2017 //
7244 /* 19894 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1,
7245 /* 19897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1,
7246 /* 19900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7247 /* 19904 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7248 /* 19908 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7249 /* 19912 */ // (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7250 /* 19912 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7251 /* 19915 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7252 /* 19919 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7253 /* 19924 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7254 /* 19928 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7255 /* 19933 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7256 /* 19936 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7257 /* 19940 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7258 /* 19945 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7259 /* 19949 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7260 /* 19954 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7261 /* 19957 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7262 /* 19961 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7263 /* 19966 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7264 /* 19969 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7265 /* 19972 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7266 /* 19975 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7267 /* 19981 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7268 /* 19987 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7269 /* 19989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7270 /* 19992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7271 /* 19994 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7272 /* 19997 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7273 /* 20002 */ // GIR_Coverage, 2017,
7274 /* 20002 */ GIR_EraseRootFromParent_Done,
7275 /* 20003 */ // Label 493: @20003
7276 /* 20003 */ GIM_Reject,
7277 /* 20004 */ // Label 444: @20004
7278 /* 20004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 494*/ GIMT_Encode4(20049), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2913 //
7279 /* 20011 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
7280 /* 20014 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
7281 /* 20017 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7282 /* 20021 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7283 /* 20025 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7284 /* 20029 */ // (and:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VANDd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
7285 /* 20029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7286 /* 20032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7287 /* 20034 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7288 /* 20036 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7289 /* 20038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7290 /* 20041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7291 /* 20047 */ GIR_RootConstrainSelectedInstOperands,
7292 /* 20048 */ // GIR_Coverage, 2913,
7293 /* 20048 */ GIR_EraseRootFromParent_Done,
7294 /* 20049 */ // Label 494: @20049
7295 /* 20049 */ GIM_Reject,
7296 /* 20050 */ // Label 445: @20050
7297 /* 20050 */ GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(20161),
7298 /* 20055 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
7299 /* 20058 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
7300 /* 20061 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 496*/ GIMT_Encode4(20100), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2916 //
7301 /* 20068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7302 /* 20072 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7303 /* 20076 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7304 /* 20080 */ // (and:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VANDq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
7305 /* 20080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7306 /* 20083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7307 /* 20085 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7308 /* 20087 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7309 /* 20089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7310 /* 20092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7311 /* 20098 */ GIR_RootConstrainSelectedInstOperands,
7312 /* 20099 */ // GIR_Coverage, 2916,
7313 /* 20099 */ GIR_EraseRootFromParent_Done,
7314 /* 20100 */ // Label 496: @20100
7315 /* 20100 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 497*/ GIMT_Encode4(20160), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3755 //
7316 /* 20107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7317 /* 20111 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7318 /* 20115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7319 /* 20119 */ // (and:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VAND:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
7320 /* 20119 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7321 /* 20122 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7322 /* 20126 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7323 /* 20131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7324 /* 20134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7325 /* 20136 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7326 /* 20138 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7327 /* 20140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7328 /* 20143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7329 /* 20149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7330 /* 20155 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7331 /* 20158 */ GIR_RootConstrainSelectedInstOperands,
7332 /* 20159 */ // GIR_Coverage, 3755,
7333 /* 20159 */ GIR_EraseRootFromParent_Done,
7334 /* 20160 */ // Label 497: @20160
7335 /* 20160 */ GIM_Reject,
7336 /* 20161 */ // Label 495: @20161
7337 /* 20161 */ GIM_Reject,
7338 /* 20162 */ // Label 446: @20162
7339 /* 20162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 498*/ GIMT_Encode4(20207), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2914 //
7340 /* 20169 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
7341 /* 20172 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
7342 /* 20175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7343 /* 20179 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7344 /* 20183 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7345 /* 20187 */ // (and:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VANDd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
7346 /* 20187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7347 /* 20190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7348 /* 20192 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7349 /* 20194 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7350 /* 20196 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7351 /* 20199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7352 /* 20205 */ GIR_RootConstrainSelectedInstOperands,
7353 /* 20206 */ // GIR_Coverage, 2914,
7354 /* 20206 */ GIR_EraseRootFromParent_Done,
7355 /* 20207 */ // Label 498: @20207
7356 /* 20207 */ GIM_Reject,
7357 /* 20208 */ // Label 447: @20208
7358 /* 20208 */ GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(20319),
7359 /* 20213 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
7360 /* 20216 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7361 /* 20219 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 500*/ GIMT_Encode4(20258), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2917 //
7362 /* 20226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7363 /* 20230 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7364 /* 20234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7365 /* 20238 */ // (and:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VANDq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
7366 /* 20238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7367 /* 20241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7368 /* 20243 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7369 /* 20245 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7370 /* 20247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7371 /* 20250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7372 /* 20256 */ GIR_RootConstrainSelectedInstOperands,
7373 /* 20257 */ // GIR_Coverage, 2917,
7374 /* 20257 */ GIR_EraseRootFromParent_Done,
7375 /* 20258 */ // Label 500: @20258
7376 /* 20258 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 501*/ GIMT_Encode4(20318), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3759 //
7377 /* 20265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7378 /* 20269 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7379 /* 20273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7380 /* 20277 */ // (and:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VAND:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
7381 /* 20277 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7382 /* 20280 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7383 /* 20284 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7384 /* 20289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7385 /* 20292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7386 /* 20294 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7387 /* 20296 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7388 /* 20298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7389 /* 20301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7390 /* 20307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7391 /* 20313 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7392 /* 20316 */ GIR_RootConstrainSelectedInstOperands,
7393 /* 20317 */ // GIR_Coverage, 3759,
7394 /* 20317 */ GIR_EraseRootFromParent_Done,
7395 /* 20318 */ // Label 501: @20318
7396 /* 20318 */ GIM_Reject,
7397 /* 20319 */ // Label 499: @20319
7398 /* 20319 */ GIM_Reject,
7399 /* 20320 */ // Label 448: @20320
7400 /* 20320 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 502*/ GIMT_Encode4(20365), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1295 //
7401 /* 20327 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
7402 /* 20330 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
7403 /* 20333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7404 /* 20337 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7405 /* 20341 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7406 /* 20345 */ // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
7407 /* 20345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7408 /* 20348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7409 /* 20350 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
7410 /* 20352 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
7411 /* 20354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7412 /* 20357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7413 /* 20363 */ GIR_RootConstrainSelectedInstOperands,
7414 /* 20364 */ // GIR_Coverage, 1295,
7415 /* 20364 */ GIR_EraseRootFromParent_Done,
7416 /* 20365 */ // Label 502: @20365
7417 /* 20365 */ GIM_Reject,
7418 /* 20366 */ // Label 449: @20366
7419 /* 20366 */ GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(20477),
7420 /* 20371 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
7421 /* 20374 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7422 /* 20377 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 504*/ GIMT_Encode4(20416), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1296 //
7423 /* 20384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7424 /* 20388 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7425 /* 20392 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7426 /* 20396 */ // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
7427 /* 20396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7428 /* 20399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7429 /* 20401 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
7430 /* 20403 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
7431 /* 20405 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7432 /* 20408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7433 /* 20414 */ GIR_RootConstrainSelectedInstOperands,
7434 /* 20415 */ // GIR_Coverage, 1296,
7435 /* 20415 */ GIR_EraseRootFromParent_Done,
7436 /* 20416 */ // Label 504: @20416
7437 /* 20416 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 505*/ GIMT_Encode4(20476), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3763 //
7438 /* 20423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7439 /* 20427 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7440 /* 20431 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7441 /* 20435 */ // (and:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VAND:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
7442 /* 20435 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7443 /* 20438 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7444 /* 20442 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7445 /* 20447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7446 /* 20450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7447 /* 20452 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7448 /* 20454 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7449 /* 20456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7450 /* 20459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7451 /* 20465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7452 /* 20471 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7453 /* 20474 */ GIR_RootConstrainSelectedInstOperands,
7454 /* 20475 */ // GIR_Coverage, 3763,
7455 /* 20475 */ GIR_EraseRootFromParent_Done,
7456 /* 20476 */ // Label 505: @20476
7457 /* 20476 */ GIM_Reject,
7458 /* 20477 */ // Label 503: @20477
7459 /* 20477 */ GIM_Reject,
7460 /* 20478 */ // Label 450: @20478
7461 /* 20478 */ GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(20589),
7462 /* 20483 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
7463 /* 20486 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7464 /* 20489 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 507*/ GIMT_Encode4(20528), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2918 //
7465 /* 20496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7466 /* 20500 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7467 /* 20504 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7468 /* 20508 */ // (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VANDq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
7469 /* 20508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7470 /* 20511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7471 /* 20513 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7472 /* 20515 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7473 /* 20517 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7474 /* 20520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7475 /* 20526 */ GIR_RootConstrainSelectedInstOperands,
7476 /* 20527 */ // GIR_Coverage, 2918,
7477 /* 20527 */ GIR_EraseRootFromParent_Done,
7478 /* 20528 */ // Label 507: @20528
7479 /* 20528 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 508*/ GIMT_Encode4(20588), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3767 //
7480 /* 20535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7481 /* 20539 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7482 /* 20543 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7483 /* 20547 */ // (and:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VAND:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
7484 /* 20547 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7485 /* 20550 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7486 /* 20554 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7487 /* 20559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7488 /* 20562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7489 /* 20564 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7490 /* 20566 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7491 /* 20568 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7492 /* 20571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7493 /* 20577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7494 /* 20583 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7495 /* 20586 */ GIR_RootConstrainSelectedInstOperands,
7496 /* 20587 */ // GIR_Coverage, 3767,
7497 /* 20587 */ GIR_EraseRootFromParent_Done,
7498 /* 20588 */ // Label 508: @20588
7499 /* 20588 */ GIM_Reject,
7500 /* 20589 */ // Label 506: @20589
7501 /* 20589 */ GIM_Reject,
7502 /* 20590 */ // Label 451: @20590
7503 /* 20590 */ GIM_Reject,
7504 /* 20591 */ // Label 6: @20591
7505 /* 20591 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 522*/ GIMT_Encode4(26316),
7506 /* 20602 */ /*GILLT_s32*//*Label 509*/ GIMT_Encode4(20654),
7507 /* 20606 */ /*GILLT_s64*//*Label 510*/ GIMT_Encode4(25216),
7508 /* 20610 */ /*GILLT_v2s1*//*Label 511*/ GIMT_Encode4(25262),
7509 /* 20614 */ /*GILLT_v4s1*//*Label 512*/ GIMT_Encode4(25379),
7510 /* 20618 */ /*GILLT_v8s1*//*Label 513*/ GIMT_Encode4(25496),
7511 /* 20622 */ /*GILLT_v16s1*//*Label 514*/ GIMT_Encode4(25613),
7512 /* 20626 */ /*GILLT_v8s8*//*Label 515*/ GIMT_Encode4(25730),
7513 /* 20630 */ /*GILLT_v16s8*//*Label 516*/ GIMT_Encode4(25776),
7514 /* 20634 */ /*GILLT_v4s16*//*Label 517*/ GIMT_Encode4(25888),
7515 /* 20638 */ /*GILLT_v8s16*//*Label 518*/ GIMT_Encode4(25934),
7516 /* 20642 */ /*GILLT_v2s32*//*Label 519*/ GIMT_Encode4(26046),
7517 /* 20646 */ /*GILLT_v4s32*//*Label 520*/ GIMT_Encode4(26092),
7518 /* 20650 */ /*GILLT_v2s64*//*Label 521*/ GIMT_Encode4(26204),
7519 /* 20654 */ // Label 509: @20654
7520 /* 20654 */ GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(25215),
7521 /* 20659 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
7522 /* 20662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7523 /* 20665 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 524*/ GIMT_Encode4(20791), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6255 //
7524 /* 20672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7525 /* 20676 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7526 /* 20680 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7527 /* 20684 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7528 /* 20688 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7529 /* 20692 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7530 /* 20696 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
7531 /* 20700 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7532 /* 20704 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7533 /* 20708 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7534 /* 20713 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
7535 /* 20717 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
7536 /* 20728 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7537 /* 20732 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
7538 /* 20736 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7539 /* 20740 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7540 /* 20744 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7541 /* 20748 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
7542 /* 20752 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7543 /* 20756 */ // MIs[4] Rm
7544 /* 20756 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7545 /* 20761 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
7546 /* 20765 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
7547 /* 20769 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7548 /* 20771 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
7549 /* 20771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH),
7550 /* 20774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7551 /* 20776 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7552 /* 20780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7553 /* 20783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7554 /* 20789 */ GIR_RootConstrainSelectedInstOperands,
7555 /* 20790 */ // GIR_Coverage, 6255,
7556 /* 20790 */ GIR_EraseRootFromParent_Done,
7557 /* 20791 */ // Label 524: @20791
7558 /* 20791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 525*/ GIMT_Encode4(20917), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6303 //
7559 /* 20798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7560 /* 20802 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7561 /* 20806 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7562 /* 20810 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7563 /* 20814 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7564 /* 20818 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7565 /* 20822 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
7566 /* 20826 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7567 /* 20830 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7568 /* 20834 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7569 /* 20839 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
7570 /* 20843 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
7571 /* 20854 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7572 /* 20858 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
7573 /* 20862 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7574 /* 20866 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7575 /* 20870 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7576 /* 20874 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
7577 /* 20878 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7578 /* 20882 */ // MIs[4] Rm
7579 /* 20882 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7580 /* 20887 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
7581 /* 20891 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
7582 /* 20895 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7583 /* 20897 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
7584 /* 20897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH),
7585 /* 20900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7586 /* 20902 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7587 /* 20906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7588 /* 20909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7589 /* 20915 */ GIR_RootConstrainSelectedInstOperands,
7590 /* 20916 */ // GIR_Coverage, 6303,
7591 /* 20916 */ GIR_EraseRootFromParent_Done,
7592 /* 20917 */ // Label 525: @20917
7593 /* 20917 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 526*/ GIMT_Encode4(21043), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2102 //
7594 /* 20924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7595 /* 20928 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7596 /* 20932 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
7597 /* 20936 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7598 /* 20940 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7599 /* 20944 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7600 /* 20948 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
7601 /* 20952 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7602 /* 20956 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7603 /* 20960 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7604 /* 20965 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
7605 /* 20969 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
7606 /* 20973 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7607 /* 20977 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
7608 /* 20981 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7609 /* 20985 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7610 /* 20989 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7611 /* 20993 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
7612 /* 20997 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7613 /* 21001 */ // MIs[4] Rm
7614 /* 21001 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7615 /* 21006 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
7616 /* 21010 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255),
7617 /* 21021 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7618 /* 21023 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
7619 /* 21023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH),
7620 /* 21026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7621 /* 21028 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7622 /* 21032 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7623 /* 21035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7624 /* 21041 */ GIR_RootConstrainSelectedInstOperands,
7625 /* 21042 */ // GIR_Coverage, 2102,
7626 /* 21042 */ GIR_EraseRootFromParent_Done,
7627 /* 21043 */ // Label 526: @21043
7628 /* 21043 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 527*/ GIMT_Encode4(21169), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2392 //
7629 /* 21050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7630 /* 21054 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7631 /* 21058 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
7632 /* 21062 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7633 /* 21066 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7634 /* 21070 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7635 /* 21074 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
7636 /* 21078 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7637 /* 21082 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7638 /* 21086 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7639 /* 21091 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
7640 /* 21095 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
7641 /* 21099 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7642 /* 21103 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
7643 /* 21107 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7644 /* 21111 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7645 /* 21115 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7646 /* 21119 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
7647 /* 21123 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7648 /* 21127 */ // MIs[4] Rm
7649 /* 21127 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7650 /* 21132 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
7651 /* 21136 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255),
7652 /* 21147 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7653 /* 21149 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
7654 /* 21149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH),
7655 /* 21152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7656 /* 21154 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7657 /* 21158 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7658 /* 21161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7659 /* 21167 */ GIR_RootConstrainSelectedInstOperands,
7660 /* 21168 */ // GIR_Coverage, 2392,
7661 /* 21168 */ GIR_EraseRootFromParent_Done,
7662 /* 21169 */ // Label 527: @21169
7663 /* 21169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 528*/ GIMT_Encode4(21301), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 5988 //
7664 /* 21176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7665 /* 21180 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7666 /* 21184 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7667 /* 21188 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7668 /* 21192 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7669 /* 21196 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7670 /* 21200 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
7671 /* 21204 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7672 /* 21208 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7673 /* 21212 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7674 /* 21217 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7675 /* 21221 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7676 /* 21225 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
7677 /* 21229 */ // MIs[3] Operand 1
7678 /* 21229 */ // No operand predicates
7679 /* 21229 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7680 /* 21240 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7681 /* 21244 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
7682 /* 21248 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7683 /* 21252 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7684 /* 21256 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7685 /* 21261 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
7686 /* 21272 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7687 /* 21274 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7688 /* 21274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7689 /* 21277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7690 /* 21279 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
7691 /* 21283 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7692 /* 21287 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7693 /* 21290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7694 /* 21293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7695 /* 21299 */ GIR_RootConstrainSelectedInstOperands,
7696 /* 21300 */ // GIR_Coverage, 5988,
7697 /* 21300 */ GIR_EraseRootFromParent_Done,
7698 /* 21301 */ // Label 528: @21301
7699 /* 21301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 529*/ GIMT_Encode4(21433), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6023 //
7700 /* 21308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7701 /* 21312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7702 /* 21316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7703 /* 21320 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7704 /* 21324 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7705 /* 21328 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7706 /* 21332 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
7707 /* 21336 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7708 /* 21340 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7709 /* 21344 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7710 /* 21349 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7711 /* 21353 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7712 /* 21357 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
7713 /* 21361 */ // MIs[3] Operand 1
7714 /* 21361 */ // No operand predicates
7715 /* 21361 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7716 /* 21372 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7717 /* 21376 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
7718 /* 21380 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7719 /* 21384 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7720 /* 21388 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7721 /* 21393 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
7722 /* 21404 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7723 /* 21406 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7724 /* 21406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
7725 /* 21409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7726 /* 21411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
7727 /* 21415 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7728 /* 21419 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7729 /* 21422 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7730 /* 21425 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7731 /* 21431 */ GIR_RootConstrainSelectedInstOperands,
7732 /* 21432 */ // GIR_Coverage, 6023,
7733 /* 21432 */ GIR_EraseRootFromParent_Done,
7734 /* 21433 */ // Label 529: @21433
7735 /* 21433 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 530*/ GIMT_Encode4(21565), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6260 //
7736 /* 21440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7737 /* 21444 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7738 /* 21448 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7739 /* 21452 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7740 /* 21456 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7741 /* 21460 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7742 /* 21464 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
7743 /* 21468 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7744 /* 21472 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7745 /* 21476 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7746 /* 21481 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7747 /* 21485 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7748 /* 21489 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
7749 /* 21493 */ // MIs[3] Operand 1
7750 /* 21493 */ // No operand predicates
7751 /* 21493 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7752 /* 21504 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7753 /* 21508 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
7754 /* 21512 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7755 /* 21516 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7756 /* 21520 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7757 /* 21525 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
7758 /* 21536 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7759 /* 21538 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
7760 /* 21538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7761 /* 21541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7762 /* 21543 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
7763 /* 21547 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7764 /* 21551 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7765 /* 21554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7766 /* 21557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7767 /* 21563 */ GIR_RootConstrainSelectedInstOperands,
7768 /* 21564 */ // GIR_Coverage, 6260,
7769 /* 21564 */ GIR_EraseRootFromParent_Done,
7770 /* 21565 */ // Label 530: @21565
7771 /* 21565 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 531*/ GIMT_Encode4(21697), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6308 //
7772 /* 21572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7773 /* 21576 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7774 /* 21580 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7775 /* 21584 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7776 /* 21588 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7777 /* 21592 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7778 /* 21596 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
7779 /* 21600 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7780 /* 21604 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7781 /* 21608 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7782 /* 21613 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7783 /* 21617 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7784 /* 21621 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
7785 /* 21625 */ // MIs[3] Operand 1
7786 /* 21625 */ // No operand predicates
7787 /* 21625 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7788 /* 21636 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7789 /* 21640 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
7790 /* 21644 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7791 /* 21648 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7792 /* 21652 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7793 /* 21657 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
7794 /* 21668 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7795 /* 21670 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
7796 /* 21670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
7797 /* 21673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7798 /* 21675 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
7799 /* 21679 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
7800 /* 21683 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7801 /* 21686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7802 /* 21689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7803 /* 21695 */ GIR_RootConstrainSelectedInstOperands,
7804 /* 21696 */ // GIR_Coverage, 6308,
7805 /* 21696 */ GIR_EraseRootFromParent_Done,
7806 /* 21697 */ // Label 531: @21697
7807 /* 21697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 532*/ GIMT_Encode4(21829), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 5987 //
7808 /* 21704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7809 /* 21708 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7810 /* 21712 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7811 /* 21716 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7812 /* 21720 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7813 /* 21724 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7814 /* 21728 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
7815 /* 21732 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7816 /* 21736 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7817 /* 21740 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7818 /* 21745 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7819 /* 21749 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7820 /* 21753 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
7821 /* 21757 */ // MIs[3] Operand 1
7822 /* 21757 */ // No operand predicates
7823 /* 21757 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7824 /* 21768 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7825 /* 21772 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
7826 /* 21776 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7827 /* 21780 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7828 /* 21784 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7829 /* 21789 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535),
7830 /* 21800 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7831 /* 21802 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7832 /* 21802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
7833 /* 21805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7834 /* 21807 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
7835 /* 21811 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7836 /* 21815 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7837 /* 21818 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7838 /* 21821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7839 /* 21827 */ GIR_RootConstrainSelectedInstOperands,
7840 /* 21828 */ // GIR_Coverage, 5987,
7841 /* 21828 */ GIR_EraseRootFromParent_Done,
7842 /* 21829 */ // Label 532: @21829
7843 /* 21829 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 533*/ GIMT_Encode4(21961), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6022 //
7844 /* 21836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7845 /* 21840 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7846 /* 21844 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7847 /* 21848 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7848 /* 21852 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7849 /* 21856 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7850 /* 21860 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
7851 /* 21864 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7852 /* 21868 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7853 /* 21872 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7854 /* 21877 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7855 /* 21881 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7856 /* 21885 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
7857 /* 21889 */ // MIs[3] Operand 1
7858 /* 21889 */ // No operand predicates
7859 /* 21889 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7860 /* 21900 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7861 /* 21904 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
7862 /* 21908 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7863 /* 21912 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7864 /* 21916 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7865 /* 21921 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535),
7866 /* 21932 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7867 /* 21934 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7868 /* 21934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
7869 /* 21937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7870 /* 21939 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
7871 /* 21943 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7872 /* 21947 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7873 /* 21950 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7874 /* 21953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7875 /* 21959 */ GIR_RootConstrainSelectedInstOperands,
7876 /* 21960 */ // GIR_Coverage, 6022,
7877 /* 21960 */ GIR_EraseRootFromParent_Done,
7878 /* 21961 */ // Label 533: @21961
7879 /* 21961 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 534*/ GIMT_Encode4(22093), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 202 //
7880 /* 21968 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7881 /* 21972 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7882 /* 21976 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7883 /* 21980 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7884 /* 21984 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7885 /* 21988 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7886 /* 21993 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7887 /* 22004 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7888 /* 22008 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7889 /* 22012 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7890 /* 22016 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7891 /* 22020 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7892 /* 22024 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
7893 /* 22028 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7894 /* 22032 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7895 /* 22036 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7896 /* 22041 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7897 /* 22045 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7898 /* 22049 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
7899 /* 22053 */ // MIs[4] Operand 1
7900 /* 22053 */ // No operand predicates
7901 /* 22053 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
7902 /* 22064 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7903 /* 22066 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7904 /* 22066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7905 /* 22069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7906 /* 22071 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7907 /* 22075 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
7908 /* 22079 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7909 /* 22082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7910 /* 22085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7911 /* 22091 */ GIR_RootConstrainSelectedInstOperands,
7912 /* 22092 */ // GIR_Coverage, 202,
7913 /* 22092 */ GIR_EraseRootFromParent_Done,
7914 /* 22093 */ // Label 534: @22093
7915 /* 22093 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 535*/ GIMT_Encode4(22225), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 539 //
7916 /* 22100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7917 /* 22104 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7918 /* 22108 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7919 /* 22112 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7920 /* 22116 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7921 /* 22120 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7922 /* 22125 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7923 /* 22136 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7924 /* 22140 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7925 /* 22144 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7926 /* 22148 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7927 /* 22152 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7928 /* 22156 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
7929 /* 22160 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7930 /* 22164 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7931 /* 22168 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7932 /* 22173 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7933 /* 22177 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7934 /* 22181 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
7935 /* 22185 */ // MIs[4] Operand 1
7936 /* 22185 */ // No operand predicates
7937 /* 22185 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
7938 /* 22196 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7939 /* 22198 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7940 /* 22198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
7941 /* 22201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7942 /* 22203 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
7943 /* 22207 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
7944 /* 22211 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7945 /* 22214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7946 /* 22217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7947 /* 22223 */ GIR_RootConstrainSelectedInstOperands,
7948 /* 22224 */ // GIR_Coverage, 539,
7949 /* 22224 */ GIR_EraseRootFromParent_Done,
7950 /* 22225 */ // Label 535: @22225
7951 /* 22225 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 536*/ GIMT_Encode4(22357), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2107 //
7952 /* 22232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7953 /* 22236 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7954 /* 22240 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7955 /* 22244 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7956 /* 22248 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7957 /* 22252 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7958 /* 22257 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7959 /* 22268 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7960 /* 22272 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7961 /* 22276 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7962 /* 22280 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7963 /* 22284 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
7964 /* 22288 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
7965 /* 22292 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7966 /* 22296 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7967 /* 22300 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7968 /* 22305 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
7969 /* 22309 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7970 /* 22313 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
7971 /* 22317 */ // MIs[4] Operand 1
7972 /* 22317 */ // No operand predicates
7973 /* 22317 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
7974 /* 22328 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7975 /* 22330 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
7976 /* 22330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7977 /* 22333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7978 /* 22335 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
7979 /* 22339 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
7980 /* 22343 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
7981 /* 22346 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7982 /* 22349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7983 /* 22355 */ GIR_RootConstrainSelectedInstOperands,
7984 /* 22356 */ // GIR_Coverage, 2107,
7985 /* 22356 */ GIR_EraseRootFromParent_Done,
7986 /* 22357 */ // Label 536: @22357
7987 /* 22357 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 537*/ GIMT_Encode4(22489), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2397 //
7988 /* 22364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7989 /* 22368 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7990 /* 22372 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7991 /* 22376 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7992 /* 22380 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7993 /* 22384 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7994 /* 22389 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
7995 /* 22400 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
7996 /* 22404 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
7997 /* 22408 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7998 /* 22412 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7999 /* 22416 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8000 /* 22420 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
8001 /* 22424 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8002 /* 22428 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8003 /* 22432 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8004 /* 22437 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8005 /* 22441 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8006 /* 22445 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
8007 /* 22449 */ // MIs[4] Operand 1
8008 /* 22449 */ // No operand predicates
8009 /* 22449 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8010 /* 22460 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8011 /* 22462 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
8012 /* 22462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8013 /* 22465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8014 /* 22467 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8015 /* 22471 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
8016 /* 22475 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8017 /* 22478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8018 /* 22481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8019 /* 22487 */ GIR_RootConstrainSelectedInstOperands,
8020 /* 22488 */ // GIR_Coverage, 2397,
8021 /* 22488 */ GIR_EraseRootFromParent_Done,
8022 /* 22489 */ // Label 537: @22489
8023 /* 22489 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 538*/ GIMT_Encode4(22621), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 201 //
8024 /* 22496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8025 /* 22500 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8026 /* 22504 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8027 /* 22508 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8028 /* 22512 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8029 /* 22516 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8030 /* 22521 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8031 /* 22532 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8032 /* 22536 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8033 /* 22540 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8034 /* 22544 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8035 /* 22548 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8036 /* 22552 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
8037 /* 22556 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8038 /* 22560 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8039 /* 22564 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8040 /* 22569 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8041 /* 22573 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8042 /* 22577 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
8043 /* 22581 */ // MIs[4] Operand 1
8044 /* 22581 */ // No operand predicates
8045 /* 22581 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8046 /* 22592 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8047 /* 22594 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8048 /* 22594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8049 /* 22597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8050 /* 22599 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8051 /* 22603 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8052 /* 22607 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8053 /* 22610 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8054 /* 22613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8055 /* 22619 */ GIR_RootConstrainSelectedInstOperands,
8056 /* 22620 */ // GIR_Coverage, 201,
8057 /* 22620 */ GIR_EraseRootFromParent_Done,
8058 /* 22621 */ // Label 538: @22621
8059 /* 22621 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 539*/ GIMT_Encode4(22753), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 538 //
8060 /* 22628 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8061 /* 22632 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8062 /* 22636 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8063 /* 22640 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8064 /* 22644 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8065 /* 22648 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8066 /* 22653 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8067 /* 22664 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8068 /* 22668 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8069 /* 22672 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8070 /* 22676 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8071 /* 22680 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8072 /* 22684 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
8073 /* 22688 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8074 /* 22692 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8075 /* 22696 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8076 /* 22701 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8077 /* 22705 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8078 /* 22709 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
8079 /* 22713 */ // MIs[4] Operand 1
8080 /* 22713 */ // No operand predicates
8081 /* 22713 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8082 /* 22724 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8083 /* 22726 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8084 /* 22726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8085 /* 22729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8086 /* 22731 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8087 /* 22735 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8088 /* 22739 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8089 /* 22742 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8090 /* 22745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8091 /* 22751 */ GIR_RootConstrainSelectedInstOperands,
8092 /* 22752 */ // GIR_Coverage, 538,
8093 /* 22752 */ GIR_EraseRootFromParent_Done,
8094 /* 22753 */ // Label 539: @22753
8095 /* 22753 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 540*/ GIMT_Encode4(22857), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2103 //
8096 /* 22760 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8097 /* 22764 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8098 /* 22768 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8099 /* 22772 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8100 /* 22776 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8101 /* 22780 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8102 /* 22785 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8103 /* 22796 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8104 /* 22800 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8105 /* 22804 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8106 /* 22808 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8107 /* 22812 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8108 /* 22817 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8109 /* 22828 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8110 /* 22830 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
8111 /* 22830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8112 /* 22833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8113 /* 22835 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8114 /* 22839 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
8115 /* 22843 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8116 /* 22846 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8117 /* 22849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8118 /* 22855 */ GIR_RootConstrainSelectedInstOperands,
8119 /* 22856 */ // GIR_Coverage, 2103,
8120 /* 22856 */ GIR_EraseRootFromParent_Done,
8121 /* 22857 */ // Label 540: @22857
8122 /* 22857 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 541*/ GIMT_Encode4(22961), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2393 //
8123 /* 22864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8124 /* 22868 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8125 /* 22872 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8126 /* 22876 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8127 /* 22880 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8128 /* 22884 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8129 /* 22889 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8130 /* 22900 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8131 /* 22904 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8132 /* 22908 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8133 /* 22912 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8134 /* 22916 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8135 /* 22921 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8136 /* 22932 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8137 /* 22934 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
8138 /* 22934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8139 /* 22937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8140 /* 22939 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8141 /* 22943 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8142 /* 22947 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8143 /* 22950 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8144 /* 22953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8145 /* 22959 */ GIR_RootConstrainSelectedInstOperands,
8146 /* 22960 */ // GIR_Coverage, 2393,
8147 /* 22960 */ GIR_EraseRootFromParent_Done,
8148 /* 22961 */ // Label 541: @22961
8149 /* 22961 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 542*/ GIMT_Encode4(23065), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6256 //
8150 /* 22968 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8151 /* 22972 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8152 /* 22976 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8153 /* 22980 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8154 /* 22984 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8155 /* 22988 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8156 /* 22993 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8157 /* 23004 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8158 /* 23008 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8159 /* 23012 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8160 /* 23016 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8161 /* 23020 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8162 /* 23025 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8163 /* 23036 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8164 /* 23038 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
8165 /* 23038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8166 /* 23041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8167 /* 23043 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
8168 /* 23047 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
8169 /* 23051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8170 /* 23054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8171 /* 23057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8172 /* 23063 */ GIR_RootConstrainSelectedInstOperands,
8173 /* 23064 */ // GIR_Coverage, 6256,
8174 /* 23064 */ GIR_EraseRootFromParent_Done,
8175 /* 23065 */ // Label 542: @23065
8176 /* 23065 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 543*/ GIMT_Encode4(23169), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6304 //
8177 /* 23072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8178 /* 23076 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8179 /* 23080 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8180 /* 23084 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8181 /* 23088 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8182 /* 23092 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8183 /* 23097 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8184 /* 23108 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8185 /* 23112 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8186 /* 23116 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8187 /* 23120 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8188 /* 23124 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8189 /* 23129 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8190 /* 23140 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8191 /* 23142 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
8192 /* 23142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8193 /* 23145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8194 /* 23147 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
8195 /* 23151 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8196 /* 23155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8197 /* 23158 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8198 /* 23161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8199 /* 23167 */ GIR_RootConstrainSelectedInstOperands,
8200 /* 23168 */ // GIR_Coverage, 6304,
8201 /* 23168 */ GIR_EraseRootFromParent_Done,
8202 /* 23169 */ // Label 543: @23169
8203 /* 23169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 544*/ GIMT_Encode4(23274), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2106 //
8204 /* 23176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8205 /* 23180 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8206 /* 23184 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8207 /* 23188 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8208 /* 23192 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8209 /* 23196 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8210 /* 23201 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8211 /* 23212 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8212 /* 23216 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
8213 /* 23220 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8214 /* 23224 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8215 /* 23228 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8216 /* 23233 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8217 /* 23237 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8218 /* 23241 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8219 /* 23245 */ // MIs[3] Operand 1
8220 /* 23245 */ // No operand predicates
8221 /* 23245 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8222 /* 23247 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8223 /* 23247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8224 /* 23250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8225 /* 23252 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8226 /* 23256 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8227 /* 23260 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8228 /* 23263 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8229 /* 23266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8230 /* 23272 */ GIR_RootConstrainSelectedInstOperands,
8231 /* 23273 */ // GIR_Coverage, 2106,
8232 /* 23273 */ GIR_EraseRootFromParent_Done,
8233 /* 23274 */ // Label 544: @23274
8234 /* 23274 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 545*/ GIMT_Encode4(23379), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2396 //
8235 /* 23281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8236 /* 23285 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8237 /* 23289 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8238 /* 23293 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8239 /* 23297 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8240 /* 23301 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8241 /* 23306 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8242 /* 23317 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8243 /* 23321 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
8244 /* 23325 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8245 /* 23329 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8246 /* 23333 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8247 /* 23338 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8248 /* 23342 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8249 /* 23346 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8250 /* 23350 */ // MIs[3] Operand 1
8251 /* 23350 */ // No operand predicates
8252 /* 23350 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8253 /* 23352 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8254 /* 23352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8255 /* 23355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8256 /* 23357 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8257 /* 23361 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8258 /* 23365 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8259 /* 23368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8260 /* 23371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8261 /* 23377 */ GIR_RootConstrainSelectedInstOperands,
8262 /* 23378 */ // GIR_Coverage, 2396,
8263 /* 23378 */ GIR_EraseRootFromParent_Done,
8264 /* 23379 */ // Label 545: @23379
8265 /* 23379 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 546*/ GIMT_Encode4(23484), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2105 //
8266 /* 23386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8267 /* 23390 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8268 /* 23394 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8269 /* 23398 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8270 /* 23402 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8271 /* 23406 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8272 /* 23411 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8273 /* 23422 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8274 /* 23426 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
8275 /* 23430 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8276 /* 23434 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8277 /* 23438 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8278 /* 23443 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8279 /* 23447 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8280 /* 23451 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8281 /* 23455 */ // MIs[3] Operand 1
8282 /* 23455 */ // No operand predicates
8283 /* 23455 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8284 /* 23457 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8285 /* 23457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8286 /* 23460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8287 /* 23462 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8288 /* 23466 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8289 /* 23470 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8290 /* 23473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8291 /* 23476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8292 /* 23482 */ GIR_RootConstrainSelectedInstOperands,
8293 /* 23483 */ // GIR_Coverage, 2105,
8294 /* 23483 */ GIR_EraseRootFromParent_Done,
8295 /* 23484 */ // Label 546: @23484
8296 /* 23484 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 547*/ GIMT_Encode4(23589), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2395 //
8297 /* 23491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8298 /* 23495 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8299 /* 23499 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8300 /* 23503 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8301 /* 23507 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8302 /* 23511 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8303 /* 23516 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8304 /* 23527 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8305 /* 23531 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
8306 /* 23535 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8307 /* 23539 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8308 /* 23543 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8309 /* 23548 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8310 /* 23552 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8311 /* 23556 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8312 /* 23560 */ // MIs[3] Operand 1
8313 /* 23560 */ // No operand predicates
8314 /* 23560 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8315 /* 23562 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8316 /* 23562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8317 /* 23565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8318 /* 23567 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8319 /* 23571 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8320 /* 23575 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8321 /* 23578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8322 /* 23581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8323 /* 23587 */ GIR_RootConstrainSelectedInstOperands,
8324 /* 23588 */ // GIR_Coverage, 2395,
8325 /* 23588 */ GIR_EraseRootFromParent_Done,
8326 /* 23589 */ // Label 547: @23589
8327 /* 23589 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 548*/ GIMT_Encode4(23694), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2104 //
8328 /* 23596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8329 /* 23600 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8330 /* 23604 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8331 /* 23608 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8332 /* 23612 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8333 /* 23616 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8334 /* 23621 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8335 /* 23632 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8336 /* 23636 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
8337 /* 23640 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8338 /* 23644 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8339 /* 23648 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8340 /* 23653 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8341 /* 23657 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8342 /* 23661 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8343 /* 23665 */ // MIs[3] Operand 1
8344 /* 23665 */ // No operand predicates
8345 /* 23665 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8346 /* 23667 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8347 /* 23667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8348 /* 23670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8349 /* 23672 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8350 /* 23676 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
8351 /* 23680 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8352 /* 23683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8353 /* 23686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8354 /* 23692 */ GIR_RootConstrainSelectedInstOperands,
8355 /* 23693 */ // GIR_Coverage, 2104,
8356 /* 23693 */ GIR_EraseRootFromParent_Done,
8357 /* 23694 */ // Label 548: @23694
8358 /* 23694 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 549*/ GIMT_Encode4(23799), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2394 //
8359 /* 23701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8360 /* 23705 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8361 /* 23709 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8362 /* 23713 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8363 /* 23717 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8364 /* 23721 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8365 /* 23726 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8366 /* 23737 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8367 /* 23741 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
8368 /* 23745 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8369 /* 23749 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8370 /* 23753 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8371 /* 23758 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8372 /* 23762 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8373 /* 23766 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8374 /* 23770 */ // MIs[3] Operand 1
8375 /* 23770 */ // No operand predicates
8376 /* 23770 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8377 /* 23772 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8378 /* 23772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8379 /* 23775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8380 /* 23777 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8381 /* 23781 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8382 /* 23785 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8383 /* 23788 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8384 /* 23791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8385 /* 23797 */ GIR_RootConstrainSelectedInstOperands,
8386 /* 23798 */ // GIR_Coverage, 2394,
8387 /* 23798 */ GIR_EraseRootFromParent_Done,
8388 /* 23799 */ // Label 549: @23799
8389 /* 23799 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 550*/ GIMT_Encode4(23904), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6259 //
8390 /* 23806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8391 /* 23810 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8392 /* 23814 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
8393 /* 23818 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8394 /* 23822 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8395 /* 23826 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8396 /* 23831 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8397 /* 23835 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8398 /* 23839 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8399 /* 23843 */ // MIs[2] Operand 1
8400 /* 23843 */ // No operand predicates
8401 /* 23843 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8402 /* 23847 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8403 /* 23851 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8404 /* 23855 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8405 /* 23859 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8406 /* 23864 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8407 /* 23875 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8408 /* 23877 */ // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8409 /* 23877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8410 /* 23880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8411 /* 23882 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8412 /* 23886 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8413 /* 23890 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8414 /* 23893 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8415 /* 23896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8416 /* 23902 */ GIR_RootConstrainSelectedInstOperands,
8417 /* 23903 */ // GIR_Coverage, 6259,
8418 /* 23903 */ GIR_EraseRootFromParent_Done,
8419 /* 23904 */ // Label 550: @23904
8420 /* 23904 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 551*/ GIMT_Encode4(24009), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6307 //
8421 /* 23911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8422 /* 23915 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8423 /* 23919 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
8424 /* 23923 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8425 /* 23927 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8426 /* 23931 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8427 /* 23936 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8428 /* 23940 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8429 /* 23944 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8430 /* 23948 */ // MIs[2] Operand 1
8431 /* 23948 */ // No operand predicates
8432 /* 23948 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8433 /* 23952 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8434 /* 23956 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8435 /* 23960 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8436 /* 23964 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8437 /* 23969 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8438 /* 23980 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8439 /* 23982 */ // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8440 /* 23982 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8441 /* 23985 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8442 /* 23987 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8443 /* 23991 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8444 /* 23995 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8445 /* 23998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8446 /* 24001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8447 /* 24007 */ GIR_RootConstrainSelectedInstOperands,
8448 /* 24008 */ // GIR_Coverage, 6307,
8449 /* 24008 */ GIR_EraseRootFromParent_Done,
8450 /* 24009 */ // Label 551: @24009
8451 /* 24009 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 552*/ GIMT_Encode4(24114), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6258 //
8452 /* 24016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8453 /* 24020 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8454 /* 24024 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
8455 /* 24028 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8456 /* 24032 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8457 /* 24036 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8458 /* 24041 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8459 /* 24045 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8460 /* 24049 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8461 /* 24053 */ // MIs[2] Operand 1
8462 /* 24053 */ // No operand predicates
8463 /* 24053 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8464 /* 24057 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8465 /* 24061 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8466 /* 24065 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8467 /* 24069 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8468 /* 24074 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8469 /* 24085 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8470 /* 24087 */ // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8471 /* 24087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8472 /* 24090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8473 /* 24092 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8474 /* 24096 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8475 /* 24100 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8476 /* 24103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8477 /* 24106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8478 /* 24112 */ GIR_RootConstrainSelectedInstOperands,
8479 /* 24113 */ // GIR_Coverage, 6258,
8480 /* 24113 */ GIR_EraseRootFromParent_Done,
8481 /* 24114 */ // Label 552: @24114
8482 /* 24114 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 553*/ GIMT_Encode4(24219), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6306 //
8483 /* 24121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8484 /* 24125 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8485 /* 24129 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
8486 /* 24133 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8487 /* 24137 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8488 /* 24141 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8489 /* 24146 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8490 /* 24150 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8491 /* 24154 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8492 /* 24158 */ // MIs[2] Operand 1
8493 /* 24158 */ // No operand predicates
8494 /* 24158 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8495 /* 24162 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8496 /* 24166 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8497 /* 24170 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8498 /* 24174 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8499 /* 24179 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8500 /* 24190 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8501 /* 24192 */ // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8502 /* 24192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8503 /* 24195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8504 /* 24197 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8505 /* 24201 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8506 /* 24205 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8507 /* 24208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8508 /* 24211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8509 /* 24217 */ GIR_RootConstrainSelectedInstOperands,
8510 /* 24218 */ // GIR_Coverage, 6306,
8511 /* 24218 */ GIR_EraseRootFromParent_Done,
8512 /* 24219 */ // Label 553: @24219
8513 /* 24219 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 554*/ GIMT_Encode4(24324), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 6257 //
8514 /* 24226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8515 /* 24230 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8516 /* 24234 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
8517 /* 24238 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8518 /* 24242 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8519 /* 24246 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8520 /* 24251 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8521 /* 24255 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8522 /* 24259 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8523 /* 24263 */ // MIs[2] Operand 1
8524 /* 24263 */ // No operand predicates
8525 /* 24263 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8526 /* 24267 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8527 /* 24271 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8528 /* 24275 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8529 /* 24279 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8530 /* 24284 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535),
8531 /* 24295 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8532 /* 24297 */ // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8533 /* 24297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8534 /* 24300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8535 /* 24302 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
8536 /* 24306 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
8537 /* 24310 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8538 /* 24313 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8539 /* 24316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8540 /* 24322 */ GIR_RootConstrainSelectedInstOperands,
8541 /* 24323 */ // GIR_Coverage, 6257,
8542 /* 24323 */ GIR_EraseRootFromParent_Done,
8543 /* 24324 */ // Label 554: @24324
8544 /* 24324 */ GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(24859),
8545 /* 24329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8546 /* 24333 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 556*/ GIMT_Encode4(24434), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6305 //
8547 /* 24340 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8548 /* 24344 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
8549 /* 24348 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8550 /* 24352 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8551 /* 24356 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8552 /* 24361 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8553 /* 24365 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8554 /* 24369 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8555 /* 24373 */ // MIs[2] Operand 1
8556 /* 24373 */ // No operand predicates
8557 /* 24373 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8558 /* 24377 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8559 /* 24381 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8560 /* 24385 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8561 /* 24389 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8562 /* 24394 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535),
8563 /* 24405 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8564 /* 24407 */ // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8565 /* 24407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8566 /* 24410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8567 /* 24412 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8568 /* 24416 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8569 /* 24420 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8570 /* 24423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8571 /* 24426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8572 /* 24432 */ GIR_RootConstrainSelectedInstOperands,
8573 /* 24433 */ // GIR_Coverage, 6305,
8574 /* 24433 */ GIR_EraseRootFromParent_Done,
8575 /* 24434 */ // Label 556: @24434
8576 /* 24434 */ GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(24580),
8577 /* 24439 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8578 /* 24443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 558*/ GIMT_Encode4(24511), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6010 //
8579 /* 24450 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8580 /* 24454 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8581 /* 24458 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8582 /* 24462 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8583 /* 24466 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
8584 /* 24470 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8585 /* 24474 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8586 /* 24478 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8587 /* 24482 */ // MIs[2] Operand 1
8588 /* 24482 */ // No operand predicates
8589 /* 24482 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8590 /* 24484 */ // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8591 /* 24484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8592 /* 24487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8593 /* 24489 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
8594 /* 24491 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8595 /* 24494 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8596 /* 24497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8597 /* 24503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8598 /* 24509 */ GIR_RootConstrainSelectedInstOperands,
8599 /* 24510 */ // GIR_Coverage, 6010,
8600 /* 24510 */ GIR_EraseRootFromParent_Done,
8601 /* 24511 */ // Label 558: @24511
8602 /* 24511 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 559*/ GIMT_Encode4(24579), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6009 //
8603 /* 24518 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8604 /* 24522 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8605 /* 24526 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8606 /* 24530 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8607 /* 24534 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8608 /* 24538 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8609 /* 24542 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8610 /* 24546 */ // MIs[2] Operand 1
8611 /* 24546 */ // No operand predicates
8612 /* 24546 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
8613 /* 24550 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8614 /* 24552 */ // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8615 /* 24552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8616 /* 24555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8617 /* 24557 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
8618 /* 24559 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8619 /* 24562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8620 /* 24565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8621 /* 24571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8622 /* 24577 */ GIR_RootConstrainSelectedInstOperands,
8623 /* 24578 */ // GIR_Coverage, 6009,
8624 /* 24578 */ GIR_EraseRootFromParent_Done,
8625 /* 24579 */ // Label 559: @24579
8626 /* 24579 */ GIM_Reject,
8627 /* 24580 */ // Label 557: @24580
8628 /* 24580 */ GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(24726),
8629 /* 24585 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8630 /* 24589 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 561*/ GIMT_Encode4(24657), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6008 //
8631 /* 24596 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8632 /* 24600 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8633 /* 24604 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8634 /* 24608 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8635 /* 24612 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
8636 /* 24616 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8637 /* 24620 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8638 /* 24624 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8639 /* 24628 */ // MIs[2] Operand 1
8640 /* 24628 */ // No operand predicates
8641 /* 24628 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8642 /* 24630 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8643 /* 24630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8644 /* 24633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8645 /* 24635 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8646 /* 24637 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8647 /* 24640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8648 /* 24643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8649 /* 24649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8650 /* 24655 */ GIR_RootConstrainSelectedInstOperands,
8651 /* 24656 */ // GIR_Coverage, 6008,
8652 /* 24656 */ GIR_EraseRootFromParent_Done,
8653 /* 24657 */ // Label 561: @24657
8654 /* 24657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 562*/ GIMT_Encode4(24725), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 495 //
8655 /* 24664 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8656 /* 24668 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8657 /* 24672 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8658 /* 24676 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8659 /* 24680 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8660 /* 24684 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8661 /* 24688 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8662 /* 24692 */ // MIs[2] Operand 1
8663 /* 24692 */ // No operand predicates
8664 /* 24692 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
8665 /* 24696 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8666 /* 24698 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8667 /* 24698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8668 /* 24701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8669 /* 24703 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8670 /* 24705 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8671 /* 24708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8672 /* 24711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8673 /* 24717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8674 /* 24723 */ GIR_RootConstrainSelectedInstOperands,
8675 /* 24724 */ // GIR_Coverage, 495,
8676 /* 24724 */ GIR_EraseRootFromParent_Done,
8677 /* 24725 */ // Label 562: @24725
8678 /* 24725 */ GIM_Reject,
8679 /* 24726 */ // Label 560: @24726
8680 /* 24726 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 563*/ GIMT_Encode4(24792), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6011 //
8681 /* 24733 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8682 /* 24737 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8683 /* 24741 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8684 /* 24745 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8685 /* 24749 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8686 /* 24754 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
8687 /* 24758 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8688 /* 24762 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8689 /* 24764 */ // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
8690 /* 24764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr),
8691 /* 24767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8692 /* 24769 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
8693 /* 24771 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
8694 /* 24775 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8695 /* 24778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8696 /* 24784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8697 /* 24790 */ GIR_RootConstrainSelectedInstOperands,
8698 /* 24791 */ // GIR_Coverage, 6011,
8699 /* 24791 */ GIR_EraseRootFromParent_Done,
8700 /* 24792 */ // Label 563: @24792
8701 /* 24792 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 564*/ GIMT_Encode4(24858), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 496 //
8702 /* 24799 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8703 /* 24803 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8704 /* 24807 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8705 /* 24811 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8706 /* 24815 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8707 /* 24819 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8708 /* 24824 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
8709 /* 24828 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8710 /* 24830 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
8711 /* 24830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr),
8712 /* 24833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8713 /* 24835 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8714 /* 24837 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
8715 /* 24841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8716 /* 24844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8717 /* 24850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8718 /* 24856 */ GIR_RootConstrainSelectedInstOperands,
8719 /* 24857 */ // GIR_Coverage, 496,
8720 /* 24857 */ GIR_EraseRootFromParent_Done,
8721 /* 24858 */ // Label 564: @24858
8722 /* 24858 */ GIM_Reject,
8723 /* 24859 */ // Label 555: @24859
8724 /* 24859 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 565*/ GIMT_Encode4(24913), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 2036 //
8725 /* 24866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8726 /* 24870 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8727 /* 24874 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760),
8728 /* 24885 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
8729 /* 24885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVTi16),
8730 /* 24888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8731 /* 24890 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
8732 /* 24892 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535),
8733 /* 24902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8734 /* 24905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8735 /* 24911 */ GIR_RootConstrainSelectedInstOperands,
8736 /* 24912 */ // GIR_Coverage, 2036,
8737 /* 24912 */ GIR_EraseRootFromParent_Done,
8738 /* 24913 */ // Label 565: @24913
8739 /* 24913 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 566*/ GIMT_Encode4(24967), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2290 //
8740 /* 24920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8741 /* 24924 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8742 /* 24928 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760),
8743 /* 24939 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
8744 /* 24939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVTi16),
8745 /* 24942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8746 /* 24944 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
8747 /* 24946 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535),
8748 /* 24956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8749 /* 24959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8750 /* 24965 */ GIR_RootConstrainSelectedInstOperands,
8751 /* 24966 */ // GIR_Coverage, 2290,
8752 /* 24966 */ GIR_EraseRootFromParent_Done,
8753 /* 24967 */ // Label 566: @24967
8754 /* 24967 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 567*/ GIMT_Encode4(25023), GIMT_Encode2(GIFBS_IsARM), // Rule ID 150 //
8755 /* 24974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8756 /* 24978 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8757 /* 24982 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8758 /* 24986 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8759 /* 24990 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
8760 /* 24994 */ // MIs[1] Operand 1
8761 /* 24994 */ // No operand predicates
8762 /* 24994 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8763 /* 24996 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8764 /* 24996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRri),
8765 /* 24999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8766 /* 25001 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8767 /* 25003 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8768 /* 25006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8769 /* 25009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8770 /* 25015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8771 /* 25021 */ GIR_RootConstrainSelectedInstOperands,
8772 /* 25022 */ // GIR_Coverage, 150,
8773 /* 25022 */ GIR_EraseRootFromParent_Done,
8774 /* 25023 */ // Label 567: @25023
8775 /* 25023 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 568*/ GIMT_Encode4(25079), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 483 //
8776 /* 25030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8777 /* 25034 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8778 /* 25038 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8779 /* 25042 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8780 /* 25046 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8781 /* 25050 */ // MIs[1] Operand 1
8782 /* 25050 */ // No operand predicates
8783 /* 25050 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
8784 /* 25052 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8785 /* 25052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRri),
8786 /* 25055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8787 /* 25057 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8788 /* 25059 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
8789 /* 25062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8790 /* 25065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8791 /* 25071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8792 /* 25077 */ GIR_RootConstrainSelectedInstOperands,
8793 /* 25078 */ // GIR_Coverage, 483,
8794 /* 25078 */ GIR_EraseRootFromParent_Done,
8795 /* 25079 */ // Label 568: @25079
8796 /* 25079 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 569*/ GIMT_Encode4(25124), GIMT_Encode2(GIFBS_IsARM), // Rule ID 151 //
8797 /* 25086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8798 /* 25090 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8799 /* 25094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
8800 /* 25098 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
8801 /* 25098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRrr),
8802 /* 25101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8803 /* 25103 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8804 /* 25105 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
8805 /* 25107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8806 /* 25110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8807 /* 25116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8808 /* 25122 */ GIR_RootConstrainSelectedInstOperands,
8809 /* 25123 */ // GIR_Coverage, 151,
8810 /* 25123 */ GIR_EraseRootFromParent_Done,
8811 /* 25124 */ // Label 569: @25124
8812 /* 25124 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 570*/ GIMT_Encode4(25169), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 324 //
8813 /* 25131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
8814 /* 25135 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
8815 /* 25139 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
8816 /* 25143 */ // (or:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tORR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
8817 /* 25143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tORR),
8818 /* 25146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
8819 /* 25148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
8820 /* 25154 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8821 /* 25156 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
8822 /* 25158 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8823 /* 25161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8824 /* 25167 */ GIR_RootConstrainSelectedInstOperands,
8825 /* 25168 */ // GIR_Coverage, 324,
8826 /* 25168 */ GIR_EraseRootFromParent_Done,
8827 /* 25169 */ // Label 570: @25169
8828 /* 25169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 571*/ GIMT_Encode4(25214), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 484 //
8829 /* 25176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8830 /* 25180 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8831 /* 25184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8832 /* 25188 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
8833 /* 25188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
8834 /* 25191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8835 /* 25193 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8836 /* 25195 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
8837 /* 25197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8838 /* 25200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8839 /* 25206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8840 /* 25212 */ GIR_RootConstrainSelectedInstOperands,
8841 /* 25213 */ // GIR_Coverage, 484,
8842 /* 25213 */ GIR_EraseRootFromParent_Done,
8843 /* 25214 */ // Label 571: @25214
8844 /* 25214 */ GIM_Reject,
8845 /* 25215 */ // Label 523: @25215
8846 /* 25215 */ GIM_Reject,
8847 /* 25216 */ // Label 510: @25216
8848 /* 25216 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 572*/ GIMT_Encode4(25261), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2921 //
8849 /* 25223 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
8850 /* 25226 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
8851 /* 25229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8852 /* 25233 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8853 /* 25237 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
8854 /* 25241 */ // (or:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VORRd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
8855 /* 25241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
8856 /* 25244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
8857 /* 25246 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
8858 /* 25248 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
8859 /* 25250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8860 /* 25253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8861 /* 25259 */ GIR_RootConstrainSelectedInstOperands,
8862 /* 25260 */ // GIR_Coverage, 2921,
8863 /* 25260 */ GIR_EraseRootFromParent_Done,
8864 /* 25261 */ // Label 572: @25261
8865 /* 25261 */ GIM_Reject,
8866 /* 25262 */ // Label 511: @25262
8867 /* 25262 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 573*/ GIMT_Encode4(25378), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2022 //
8868 /* 25269 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1,
8869 /* 25272 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1,
8870 /* 25275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8871 /* 25279 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8872 /* 25283 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8873 /* 25287 */ // (or:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8874 /* 25287 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8875 /* 25290 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8876 /* 25294 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8877 /* 25299 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8878 /* 25303 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
8879 /* 25308 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8880 /* 25311 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8881 /* 25315 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8882 /* 25320 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8883 /* 25324 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
8884 /* 25329 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8885 /* 25332 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
8886 /* 25336 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8887 /* 25341 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8888 /* 25344 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
8889 /* 25347 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
8890 /* 25350 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8891 /* 25356 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8892 /* 25362 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8893 /* 25364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8894 /* 25367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8895 /* 25369 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8896 /* 25372 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
8897 /* 25377 */ // GIR_Coverage, 2022,
8898 /* 25377 */ GIR_EraseRootFromParent_Done,
8899 /* 25378 */ // Label 573: @25378
8900 /* 25378 */ GIM_Reject,
8901 /* 25379 */ // Label 512: @25379
8902 /* 25379 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 574*/ GIMT_Encode4(25495), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2023 //
8903 /* 25386 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1,
8904 /* 25389 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1,
8905 /* 25392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8906 /* 25396 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8907 /* 25400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8908 /* 25404 */ // (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8909 /* 25404 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8910 /* 25407 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8911 /* 25411 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8912 /* 25416 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8913 /* 25420 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
8914 /* 25425 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8915 /* 25428 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8916 /* 25432 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8917 /* 25437 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8918 /* 25441 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
8919 /* 25446 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8920 /* 25449 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
8921 /* 25453 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8922 /* 25458 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8923 /* 25461 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
8924 /* 25464 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
8925 /* 25467 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8926 /* 25473 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8927 /* 25479 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8928 /* 25481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8929 /* 25484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8930 /* 25486 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8931 /* 25489 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
8932 /* 25494 */ // GIR_Coverage, 2023,
8933 /* 25494 */ GIR_EraseRootFromParent_Done,
8934 /* 25495 */ // Label 574: @25495
8935 /* 25495 */ GIM_Reject,
8936 /* 25496 */ // Label 513: @25496
8937 /* 25496 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 575*/ GIMT_Encode4(25612), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2024 //
8938 /* 25503 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1,
8939 /* 25506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1,
8940 /* 25509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8941 /* 25513 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8942 /* 25517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8943 /* 25521 */ // (or:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8944 /* 25521 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8945 /* 25524 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8946 /* 25528 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8947 /* 25533 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8948 /* 25537 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
8949 /* 25542 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8950 /* 25545 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8951 /* 25549 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8952 /* 25554 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8953 /* 25558 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
8954 /* 25563 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8955 /* 25566 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
8956 /* 25570 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8957 /* 25575 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8958 /* 25578 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
8959 /* 25581 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
8960 /* 25584 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8961 /* 25590 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8962 /* 25596 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8963 /* 25598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8964 /* 25601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
8965 /* 25603 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
8966 /* 25606 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
8967 /* 25611 */ // GIR_Coverage, 2024,
8968 /* 25611 */ GIR_EraseRootFromParent_Done,
8969 /* 25612 */ // Label 575: @25612
8970 /* 25612 */ GIM_Reject,
8971 /* 25613 */ // Label 514: @25613
8972 /* 25613 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 576*/ GIMT_Encode4(25729), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2025 //
8973 /* 25620 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1,
8974 /* 25623 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1,
8975 /* 25626 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8976 /* 25630 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8977 /* 25634 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
8978 /* 25638 */ // (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
8979 /* 25638 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
8980 /* 25641 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8981 /* 25645 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8982 /* 25650 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
8983 /* 25654 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
8984 /* 25659 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
8985 /* 25662 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8986 /* 25666 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8987 /* 25671 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
8988 /* 25675 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
8989 /* 25680 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
8990 /* 25683 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
8991 /* 25687 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
8992 /* 25692 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
8993 /* 25695 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
8994 /* 25698 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
8995 /* 25701 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8996 /* 25707 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8997 /* 25713 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
8998 /* 25715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
8999 /* 25718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9000 /* 25720 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9001 /* 25723 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9002 /* 25728 */ // GIR_Coverage, 2025,
9003 /* 25728 */ GIR_EraseRootFromParent_Done,
9004 /* 25729 */ // Label 576: @25729
9005 /* 25729 */ GIM_Reject,
9006 /* 25730 */ // Label 515: @25730
9007 /* 25730 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 577*/ GIMT_Encode4(25775), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2919 //
9008 /* 25737 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
9009 /* 25740 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
9010 /* 25743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9011 /* 25747 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9012 /* 25751 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9013 /* 25755 */ // (or:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VORRd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
9014 /* 25755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
9015 /* 25758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9016 /* 25760 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9017 /* 25762 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9018 /* 25764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9019 /* 25767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9020 /* 25773 */ GIR_RootConstrainSelectedInstOperands,
9021 /* 25774 */ // GIR_Coverage, 2919,
9022 /* 25774 */ GIR_EraseRootFromParent_Done,
9023 /* 25775 */ // Label 577: @25775
9024 /* 25775 */ GIM_Reject,
9025 /* 25776 */ // Label 516: @25776
9026 /* 25776 */ GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(25887),
9027 /* 25781 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
9028 /* 25784 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9029 /* 25787 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 579*/ GIMT_Encode4(25826), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2922 //
9030 /* 25794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9031 /* 25798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9032 /* 25802 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9033 /* 25806 */ // (or:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VORRq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
9034 /* 25806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9035 /* 25809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9036 /* 25811 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9037 /* 25813 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9038 /* 25815 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9039 /* 25818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9040 /* 25824 */ GIR_RootConstrainSelectedInstOperands,
9041 /* 25825 */ // GIR_Coverage, 2922,
9042 /* 25825 */ GIR_EraseRootFromParent_Done,
9043 /* 25826 */ // Label 579: @25826
9044 /* 25826 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 580*/ GIMT_Encode4(25886), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3769 //
9045 /* 25833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9046 /* 25837 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9047 /* 25841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9048 /* 25845 */ // (or:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VORR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
9049 /* 25845 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9050 /* 25848 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9051 /* 25852 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9052 /* 25857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9053 /* 25860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9054 /* 25862 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9055 /* 25864 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9056 /* 25866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9057 /* 25869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9058 /* 25875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9059 /* 25881 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9060 /* 25884 */ GIR_RootConstrainSelectedInstOperands,
9061 /* 25885 */ // GIR_Coverage, 3769,
9062 /* 25885 */ GIR_EraseRootFromParent_Done,
9063 /* 25886 */ // Label 580: @25886
9064 /* 25886 */ GIM_Reject,
9065 /* 25887 */ // Label 578: @25887
9066 /* 25887 */ GIM_Reject,
9067 /* 25888 */ // Label 517: @25888
9068 /* 25888 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 581*/ GIMT_Encode4(25933), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2920 //
9069 /* 25895 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
9070 /* 25898 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
9071 /* 25901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9072 /* 25905 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9073 /* 25909 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9074 /* 25913 */ // (or:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VORRd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
9075 /* 25913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
9076 /* 25916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9077 /* 25918 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9078 /* 25920 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9079 /* 25922 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9080 /* 25925 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9081 /* 25931 */ GIR_RootConstrainSelectedInstOperands,
9082 /* 25932 */ // GIR_Coverage, 2920,
9083 /* 25932 */ GIR_EraseRootFromParent_Done,
9084 /* 25933 */ // Label 581: @25933
9085 /* 25933 */ GIM_Reject,
9086 /* 25934 */ // Label 518: @25934
9087 /* 25934 */ GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(26045),
9088 /* 25939 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
9089 /* 25942 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9090 /* 25945 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 583*/ GIMT_Encode4(25984), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2923 //
9091 /* 25952 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9092 /* 25956 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9093 /* 25960 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9094 /* 25964 */ // (or:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VORRq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
9095 /* 25964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9096 /* 25967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9097 /* 25969 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9098 /* 25971 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9099 /* 25973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9100 /* 25976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9101 /* 25982 */ GIR_RootConstrainSelectedInstOperands,
9102 /* 25983 */ // GIR_Coverage, 2923,
9103 /* 25983 */ GIR_EraseRootFromParent_Done,
9104 /* 25984 */ // Label 583: @25984
9105 /* 25984 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 584*/ GIMT_Encode4(26044), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3773 //
9106 /* 25991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9107 /* 25995 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9108 /* 25999 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9109 /* 26003 */ // (or:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VORR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
9110 /* 26003 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9111 /* 26006 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9112 /* 26010 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9113 /* 26015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9114 /* 26018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9115 /* 26020 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9116 /* 26022 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9117 /* 26024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9118 /* 26027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9119 /* 26033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9120 /* 26039 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9121 /* 26042 */ GIR_RootConstrainSelectedInstOperands,
9122 /* 26043 */ // GIR_Coverage, 3773,
9123 /* 26043 */ GIR_EraseRootFromParent_Done,
9124 /* 26044 */ // Label 584: @26044
9125 /* 26044 */ GIM_Reject,
9126 /* 26045 */ // Label 582: @26045
9127 /* 26045 */ GIM_Reject,
9128 /* 26046 */ // Label 519: @26046
9129 /* 26046 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 585*/ GIMT_Encode4(26091), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1299 //
9130 /* 26053 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
9131 /* 26056 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
9132 /* 26059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9133 /* 26063 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9134 /* 26067 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9135 /* 26071 */ // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
9136 /* 26071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
9137 /* 26074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9138 /* 26076 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9139 /* 26078 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9140 /* 26080 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9141 /* 26083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9142 /* 26089 */ GIR_RootConstrainSelectedInstOperands,
9143 /* 26090 */ // GIR_Coverage, 1299,
9144 /* 26090 */ GIR_EraseRootFromParent_Done,
9145 /* 26091 */ // Label 585: @26091
9146 /* 26091 */ GIM_Reject,
9147 /* 26092 */ // Label 520: @26092
9148 /* 26092 */ GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(26203),
9149 /* 26097 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
9150 /* 26100 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9151 /* 26103 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 587*/ GIMT_Encode4(26142), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1300 //
9152 /* 26110 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9153 /* 26114 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9154 /* 26118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9155 /* 26122 */ // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
9156 /* 26122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9157 /* 26125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9158 /* 26127 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9159 /* 26129 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9160 /* 26131 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9161 /* 26134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9162 /* 26140 */ GIR_RootConstrainSelectedInstOperands,
9163 /* 26141 */ // GIR_Coverage, 1300,
9164 /* 26141 */ GIR_EraseRootFromParent_Done,
9165 /* 26142 */ // Label 587: @26142
9166 /* 26142 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 588*/ GIMT_Encode4(26202), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3777 //
9167 /* 26149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9168 /* 26153 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9169 /* 26157 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9170 /* 26161 */ // (or:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VORR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
9171 /* 26161 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9172 /* 26164 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9173 /* 26168 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9174 /* 26173 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9175 /* 26176 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9176 /* 26178 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9177 /* 26180 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9178 /* 26182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9179 /* 26185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9180 /* 26191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9181 /* 26197 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9182 /* 26200 */ GIR_RootConstrainSelectedInstOperands,
9183 /* 26201 */ // GIR_Coverage, 3777,
9184 /* 26201 */ GIR_EraseRootFromParent_Done,
9185 /* 26202 */ // Label 588: @26202
9186 /* 26202 */ GIM_Reject,
9187 /* 26203 */ // Label 586: @26203
9188 /* 26203 */ GIM_Reject,
9189 /* 26204 */ // Label 521: @26204
9190 /* 26204 */ GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(26315),
9191 /* 26209 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
9192 /* 26212 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9193 /* 26215 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 590*/ GIMT_Encode4(26254), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2924 //
9194 /* 26222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9195 /* 26226 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9196 /* 26230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9197 /* 26234 */ // (or:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VORRq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
9198 /* 26234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9199 /* 26237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9200 /* 26239 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9201 /* 26241 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9202 /* 26243 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9203 /* 26246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9204 /* 26252 */ GIR_RootConstrainSelectedInstOperands,
9205 /* 26253 */ // GIR_Coverage, 2924,
9206 /* 26253 */ GIR_EraseRootFromParent_Done,
9207 /* 26254 */ // Label 590: @26254
9208 /* 26254 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 591*/ GIMT_Encode4(26314), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3781 //
9209 /* 26261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9210 /* 26265 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9211 /* 26269 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9212 /* 26273 */ // (or:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VORR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
9213 /* 26273 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9214 /* 26276 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9215 /* 26280 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9216 /* 26285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9217 /* 26288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9218 /* 26290 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9219 /* 26292 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9220 /* 26294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9221 /* 26297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9222 /* 26303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9223 /* 26309 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9224 /* 26312 */ GIR_RootConstrainSelectedInstOperands,
9225 /* 26313 */ // GIR_Coverage, 3781,
9226 /* 26313 */ GIR_EraseRootFromParent_Done,
9227 /* 26314 */ // Label 591: @26314
9228 /* 26314 */ GIM_Reject,
9229 /* 26315 */ // Label 589: @26315
9230 /* 26315 */ GIM_Reject,
9231 /* 26316 */ // Label 522: @26316
9232 /* 26316 */ GIM_Reject,
9233 /* 26317 */ // Label 7: @26317
9234 /* 26317 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 605*/ GIMT_Encode4(27975),
9235 /* 26328 */ /*GILLT_s32*//*Label 592*/ GIMT_Encode4(26380),
9236 /* 26332 */ /*GILLT_s64*//*Label 593*/ GIMT_Encode4(26875),
9237 /* 26336 */ /*GILLT_v2s1*//*Label 594*/ GIMT_Encode4(26921),
9238 /* 26340 */ /*GILLT_v4s1*//*Label 595*/ GIMT_Encode4(27038),
9239 /* 26344 */ /*GILLT_v8s1*//*Label 596*/ GIMT_Encode4(27155),
9240 /* 26348 */ /*GILLT_v16s1*//*Label 597*/ GIMT_Encode4(27272),
9241 /* 26352 */ /*GILLT_v8s8*//*Label 598*/ GIMT_Encode4(27389),
9242 /* 26356 */ /*GILLT_v16s8*//*Label 599*/ GIMT_Encode4(27435),
9243 /* 26360 */ /*GILLT_v4s16*//*Label 600*/ GIMT_Encode4(27547),
9244 /* 26364 */ /*GILLT_v8s16*//*Label 601*/ GIMT_Encode4(27593),
9245 /* 26368 */ /*GILLT_v2s32*//*Label 602*/ GIMT_Encode4(27705),
9246 /* 26372 */ /*GILLT_v4s32*//*Label 603*/ GIMT_Encode4(27751),
9247 /* 26376 */ /*GILLT_v2s64*//*Label 604*/ GIMT_Encode4(27863),
9248 /* 26380 */ // Label 592: @26380
9249 /* 26380 */ GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(26874),
9250 /* 26385 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
9251 /* 26388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9252 /* 26391 */ GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(26540),
9253 /* 26396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9254 /* 26400 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 608*/ GIMT_Encode4(26450), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 6013 //
9255 /* 26407 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 255,
9256 /* 26411 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9257 /* 26415 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9258 /* 26419 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
9259 /* 26423 */ // MIs[1] Operand 1
9260 /* 26423 */ // No operand predicates
9261 /* 26423 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9262 /* 26425 */ // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
9263 /* 26425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
9264 /* 26428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9265 /* 26430 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9266 /* 26433 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9267 /* 26436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9268 /* 26442 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9269 /* 26448 */ GIR_RootConstrainSelectedInstOperands,
9270 /* 26449 */ // GIR_Coverage, 6013,
9271 /* 26449 */ GIR_EraseRootFromParent_Done,
9272 /* 26450 */ // Label 608: @26450
9273 /* 26450 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 609*/ GIMT_Encode4(26500), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 498 //
9274 /* 26457 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9275 /* 26461 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9276 /* 26465 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
9277 /* 26469 */ // MIs[1] Operand 1
9278 /* 26469 */ // No operand predicates
9279 /* 26469 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9280 /* 26473 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9281 /* 26475 */ // (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
9282 /* 26475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
9283 /* 26478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9284 /* 26480 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9285 /* 26483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9286 /* 26486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9287 /* 26492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9288 /* 26498 */ GIR_RootConstrainSelectedInstOperands,
9289 /* 26499 */ // GIR_Coverage, 498,
9290 /* 26499 */ GIR_EraseRootFromParent_Done,
9291 /* 26500 */ // Label 609: @26500
9292 /* 26500 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 610*/ GIMT_Encode4(26539), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 499 //
9293 /* 26507 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9294 /* 26511 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9295 /* 26515 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
9296 /* 26515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNr),
9297 /* 26518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9298 /* 26520 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
9299 /* 26522 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9300 /* 26525 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9301 /* 26531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9302 /* 26537 */ GIR_RootConstrainSelectedInstOperands,
9303 /* 26538 */ // GIR_Coverage, 499,
9304 /* 26538 */ GIR_EraseRootFromParent_Done,
9305 /* 26539 */ // Label 610: @26539
9306 /* 26539 */ GIM_Reject,
9307 /* 26540 */ // Label 607: @26540
9308 /* 26540 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 611*/ GIMT_Encode4(26583), GIMT_Encode2(GIFBS_IsARM), // Rule ID 164 //
9309 /* 26547 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9310 /* 26551 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9311 /* 26555 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9312 /* 26559 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
9313 /* 26559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNr),
9314 /* 26562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9315 /* 26564 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
9316 /* 26566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9317 /* 26569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9318 /* 26575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9319 /* 26581 */ GIR_RootConstrainSelectedInstOperands,
9320 /* 26582 */ // GIR_Coverage, 164,
9321 /* 26582 */ GIR_EraseRootFromParent_Done,
9322 /* 26583 */ // Label 611: @26583
9323 /* 26583 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 612*/ GIMT_Encode4(26626), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 323 //
9324 /* 26590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9325 /* 26594 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9326 /* 26598 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9327 /* 26602 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, -1:{ *:[i32] }) => (tMVN:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)
9328 /* 26602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMVN),
9329 /* 26605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9330 /* 26607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
9331 /* 26613 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9332 /* 26615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9333 /* 26618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9334 /* 26624 */ GIR_RootConstrainSelectedInstOperands,
9335 /* 26625 */ // GIR_Coverage, 323,
9336 /* 26625 */ GIR_EraseRootFromParent_Done,
9337 /* 26626 */ // Label 612: @26626
9338 /* 26626 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 613*/ GIMT_Encode4(26682), GIMT_Encode2(GIFBS_IsARM), // Rule ID 154 //
9339 /* 26633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9340 /* 26637 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9341 /* 26641 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9342 /* 26645 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9343 /* 26649 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
9344 /* 26653 */ // MIs[1] Operand 1
9345 /* 26653 */ // No operand predicates
9346 /* 26653 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9347 /* 26655 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
9348 /* 26655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORri),
9349 /* 26658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9350 /* 26660 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9351 /* 26662 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9352 /* 26665 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9353 /* 26668 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9354 /* 26674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9355 /* 26680 */ GIR_RootConstrainSelectedInstOperands,
9356 /* 26681 */ // GIR_Coverage, 154,
9357 /* 26681 */ GIR_EraseRootFromParent_Done,
9358 /* 26682 */ // Label 613: @26682
9359 /* 26682 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 614*/ GIMT_Encode4(26738), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 486 //
9360 /* 26689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9361 /* 26693 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9362 /* 26697 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9363 /* 26701 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9364 /* 26705 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
9365 /* 26709 */ // MIs[1] Operand 1
9366 /* 26709 */ // No operand predicates
9367 /* 26709 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9368 /* 26711 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
9369 /* 26711 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORri),
9370 /* 26714 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9371 /* 26716 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9372 /* 26718 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9373 /* 26721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9374 /* 26724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9375 /* 26730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9376 /* 26736 */ GIR_RootConstrainSelectedInstOperands,
9377 /* 26737 */ // GIR_Coverage, 486,
9378 /* 26737 */ GIR_EraseRootFromParent_Done,
9379 /* 26738 */ // Label 614: @26738
9380 /* 26738 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 615*/ GIMT_Encode4(26783), GIMT_Encode2(GIFBS_IsARM), // Rule ID 155 //
9381 /* 26745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9382 /* 26749 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9383 /* 26753 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9384 /* 26757 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
9385 /* 26757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORrr),
9386 /* 26760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9387 /* 26762 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9388 /* 26764 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9389 /* 26766 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9390 /* 26769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9391 /* 26775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9392 /* 26781 */ GIR_RootConstrainSelectedInstOperands,
9393 /* 26782 */ // GIR_Coverage, 155,
9394 /* 26782 */ GIR_EraseRootFromParent_Done,
9395 /* 26783 */ // Label 615: @26783
9396 /* 26783 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 616*/ GIMT_Encode4(26828), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 316 //
9397 /* 26790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9398 /* 26794 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9399 /* 26798 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9400 /* 26802 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tEOR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
9401 /* 26802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tEOR),
9402 /* 26805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
9403 /* 26807 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
9404 /* 26813 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9405 /* 26815 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9406 /* 26817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9407 /* 26820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9408 /* 26826 */ GIR_RootConstrainSelectedInstOperands,
9409 /* 26827 */ // GIR_Coverage, 316,
9410 /* 26827 */ GIR_EraseRootFromParent_Done,
9411 /* 26828 */ // Label 616: @26828
9412 /* 26828 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 617*/ GIMT_Encode4(26873), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 487 //
9413 /* 26835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9414 /* 26839 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9415 /* 26843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9416 /* 26847 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
9417 /* 26847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9418 /* 26850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9419 /* 26852 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9420 /* 26854 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9421 /* 26856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9422 /* 26859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9423 /* 26865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9424 /* 26871 */ GIR_RootConstrainSelectedInstOperands,
9425 /* 26872 */ // GIR_Coverage, 487,
9426 /* 26872 */ GIR_EraseRootFromParent_Done,
9427 /* 26873 */ // Label 617: @26873
9428 /* 26873 */ GIM_Reject,
9429 /* 26874 */ // Label 606: @26874
9430 /* 26874 */ GIM_Reject,
9431 /* 26875 */ // Label 593: @26875
9432 /* 26875 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 618*/ GIMT_Encode4(26920), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2927 //
9433 /* 26882 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
9434 /* 26885 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
9435 /* 26888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9436 /* 26892 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9437 /* 26896 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9438 /* 26900 */ // (xor:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VEORd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
9439 /* 26900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
9440 /* 26903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9441 /* 26905 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9442 /* 26907 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9443 /* 26909 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9444 /* 26912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9445 /* 26918 */ GIR_RootConstrainSelectedInstOperands,
9446 /* 26919 */ // GIR_Coverage, 2927,
9447 /* 26919 */ GIR_EraseRootFromParent_Done,
9448 /* 26920 */ // Label 618: @26920
9449 /* 26920 */ GIM_Reject,
9450 /* 26921 */ // Label 594: @26921
9451 /* 26921 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 619*/ GIMT_Encode4(27037), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2018 //
9452 /* 26928 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1,
9453 /* 26931 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1,
9454 /* 26934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9455 /* 26938 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9456 /* 26942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9457 /* 26946 */ // (xor:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9458 /* 26946 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9459 /* 26949 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9460 /* 26953 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9461 /* 26958 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9462 /* 26962 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9463 /* 26967 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9464 /* 26970 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9465 /* 26974 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9466 /* 26979 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9467 /* 26983 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9468 /* 26988 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9469 /* 26991 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9470 /* 26995 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9471 /* 27000 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9472 /* 27003 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9473 /* 27006 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9474 /* 27009 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9475 /* 27015 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9476 /* 27021 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9477 /* 27023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9478 /* 27026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9479 /* 27028 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9480 /* 27031 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9481 /* 27036 */ // GIR_Coverage, 2018,
9482 /* 27036 */ GIR_EraseRootFromParent_Done,
9483 /* 27037 */ // Label 619: @27037
9484 /* 27037 */ GIM_Reject,
9485 /* 27038 */ // Label 595: @27038
9486 /* 27038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 620*/ GIMT_Encode4(27154), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2019 //
9487 /* 27045 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1,
9488 /* 27048 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1,
9489 /* 27051 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9490 /* 27055 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9491 /* 27059 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9492 /* 27063 */ // (xor:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9493 /* 27063 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9494 /* 27066 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9495 /* 27070 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9496 /* 27075 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9497 /* 27079 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9498 /* 27084 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9499 /* 27087 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9500 /* 27091 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9501 /* 27096 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9502 /* 27100 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9503 /* 27105 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9504 /* 27108 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9505 /* 27112 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9506 /* 27117 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9507 /* 27120 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9508 /* 27123 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9509 /* 27126 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9510 /* 27132 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9511 /* 27138 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9512 /* 27140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9513 /* 27143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9514 /* 27145 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9515 /* 27148 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9516 /* 27153 */ // GIR_Coverage, 2019,
9517 /* 27153 */ GIR_EraseRootFromParent_Done,
9518 /* 27154 */ // Label 620: @27154
9519 /* 27154 */ GIM_Reject,
9520 /* 27155 */ // Label 596: @27155
9521 /* 27155 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 621*/ GIMT_Encode4(27271), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2020 //
9522 /* 27162 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1,
9523 /* 27165 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1,
9524 /* 27168 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9525 /* 27172 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9526 /* 27176 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9527 /* 27180 */ // (xor:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9528 /* 27180 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9529 /* 27183 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9530 /* 27187 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9531 /* 27192 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9532 /* 27196 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9533 /* 27201 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9534 /* 27204 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9535 /* 27208 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9536 /* 27213 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9537 /* 27217 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9538 /* 27222 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9539 /* 27225 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9540 /* 27229 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9541 /* 27234 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9542 /* 27237 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9543 /* 27240 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9544 /* 27243 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9545 /* 27249 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9546 /* 27255 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9547 /* 27257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9548 /* 27260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9549 /* 27262 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9550 /* 27265 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9551 /* 27270 */ // GIR_Coverage, 2020,
9552 /* 27270 */ GIR_EraseRootFromParent_Done,
9553 /* 27271 */ // Label 621: @27271
9554 /* 27271 */ GIM_Reject,
9555 /* 27272 */ // Label 597: @27272
9556 /* 27272 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 622*/ GIMT_Encode4(27388), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 2021 //
9557 /* 27279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1,
9558 /* 27282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1,
9559 /* 27285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9560 /* 27289 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9561 /* 27293 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9562 /* 27297 */ // (xor:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9563 /* 27297 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9564 /* 27300 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9565 /* 27304 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9566 /* 27309 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9567 /* 27313 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9568 /* 27318 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9569 /* 27321 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9570 /* 27325 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9571 /* 27330 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9572 /* 27334 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9573 /* 27339 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9574 /* 27342 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9575 /* 27346 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9576 /* 27351 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9577 /* 27354 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9578 /* 27357 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9579 /* 27360 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9580 /* 27366 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9581 /* 27372 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9582 /* 27374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9583 /* 27377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9584 /* 27379 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9585 /* 27382 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9586 /* 27387 */ // GIR_Coverage, 2021,
9587 /* 27387 */ GIR_EraseRootFromParent_Done,
9588 /* 27388 */ // Label 622: @27388
9589 /* 27388 */ GIM_Reject,
9590 /* 27389 */ // Label 598: @27389
9591 /* 27389 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 623*/ GIMT_Encode4(27434), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2925 //
9592 /* 27396 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
9593 /* 27399 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
9594 /* 27402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9595 /* 27406 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9596 /* 27410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9597 /* 27414 */ // (xor:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VEORd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
9598 /* 27414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
9599 /* 27417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9600 /* 27419 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9601 /* 27421 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9602 /* 27423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9603 /* 27426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9604 /* 27432 */ GIR_RootConstrainSelectedInstOperands,
9605 /* 27433 */ // GIR_Coverage, 2925,
9606 /* 27433 */ GIR_EraseRootFromParent_Done,
9607 /* 27434 */ // Label 623: @27434
9608 /* 27434 */ GIM_Reject,
9609 /* 27435 */ // Label 599: @27435
9610 /* 27435 */ GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(27546),
9611 /* 27440 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
9612 /* 27443 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9613 /* 27446 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 625*/ GIMT_Encode4(27485), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2928 //
9614 /* 27453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9615 /* 27457 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9616 /* 27461 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9617 /* 27465 */ // (xor:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VEORq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
9618 /* 27465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
9619 /* 27468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9620 /* 27470 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9621 /* 27472 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9622 /* 27474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9623 /* 27477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9624 /* 27483 */ GIR_RootConstrainSelectedInstOperands,
9625 /* 27484 */ // GIR_Coverage, 2928,
9626 /* 27484 */ GIR_EraseRootFromParent_Done,
9627 /* 27485 */ // Label 625: @27485
9628 /* 27485 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 626*/ GIMT_Encode4(27545), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3783 //
9629 /* 27492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9630 /* 27496 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9631 /* 27500 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9632 /* 27504 */ // (xor:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VEOR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
9633 /* 27504 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9634 /* 27507 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9635 /* 27511 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9636 /* 27516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
9637 /* 27519 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9638 /* 27521 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9639 /* 27523 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9640 /* 27525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9641 /* 27528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9642 /* 27534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9643 /* 27540 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9644 /* 27543 */ GIR_RootConstrainSelectedInstOperands,
9645 /* 27544 */ // GIR_Coverage, 3783,
9646 /* 27544 */ GIR_EraseRootFromParent_Done,
9647 /* 27545 */ // Label 626: @27545
9648 /* 27545 */ GIM_Reject,
9649 /* 27546 */ // Label 624: @27546
9650 /* 27546 */ GIM_Reject,
9651 /* 27547 */ // Label 600: @27547
9652 /* 27547 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 627*/ GIMT_Encode4(27592), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2926 //
9653 /* 27554 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
9654 /* 27557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
9655 /* 27560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9656 /* 27564 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9657 /* 27568 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9658 /* 27572 */ // (xor:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VEORd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
9659 /* 27572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
9660 /* 27575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9661 /* 27577 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9662 /* 27579 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9663 /* 27581 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9664 /* 27584 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9665 /* 27590 */ GIR_RootConstrainSelectedInstOperands,
9666 /* 27591 */ // GIR_Coverage, 2926,
9667 /* 27591 */ GIR_EraseRootFromParent_Done,
9668 /* 27592 */ // Label 627: @27592
9669 /* 27592 */ GIM_Reject,
9670 /* 27593 */ // Label 601: @27593
9671 /* 27593 */ GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(27704),
9672 /* 27598 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
9673 /* 27601 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9674 /* 27604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 629*/ GIMT_Encode4(27643), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2929 //
9675 /* 27611 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9676 /* 27615 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9677 /* 27619 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9678 /* 27623 */ // (xor:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VEORq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
9679 /* 27623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
9680 /* 27626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9681 /* 27628 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9682 /* 27630 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9683 /* 27632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9684 /* 27635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9685 /* 27641 */ GIR_RootConstrainSelectedInstOperands,
9686 /* 27642 */ // GIR_Coverage, 2929,
9687 /* 27642 */ GIR_EraseRootFromParent_Done,
9688 /* 27643 */ // Label 629: @27643
9689 /* 27643 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 630*/ GIMT_Encode4(27703), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3787 //
9690 /* 27650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9691 /* 27654 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9692 /* 27658 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9693 /* 27662 */ // (xor:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VEOR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
9694 /* 27662 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9695 /* 27665 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9696 /* 27669 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9697 /* 27674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
9698 /* 27677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9699 /* 27679 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9700 /* 27681 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9701 /* 27683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9702 /* 27686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9703 /* 27692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9704 /* 27698 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9705 /* 27701 */ GIR_RootConstrainSelectedInstOperands,
9706 /* 27702 */ // GIR_Coverage, 3787,
9707 /* 27702 */ GIR_EraseRootFromParent_Done,
9708 /* 27703 */ // Label 630: @27703
9709 /* 27703 */ GIM_Reject,
9710 /* 27704 */ // Label 628: @27704
9711 /* 27704 */ GIM_Reject,
9712 /* 27705 */ // Label 602: @27705
9713 /* 27705 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 631*/ GIMT_Encode4(27750), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1297 //
9714 /* 27712 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
9715 /* 27715 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
9716 /* 27718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9717 /* 27722 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9718 /* 27726 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9719 /* 27730 */ // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
9720 /* 27730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
9721 /* 27733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9722 /* 27735 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9723 /* 27737 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9724 /* 27739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9725 /* 27742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9726 /* 27748 */ GIR_RootConstrainSelectedInstOperands,
9727 /* 27749 */ // GIR_Coverage, 1297,
9728 /* 27749 */ GIR_EraseRootFromParent_Done,
9729 /* 27750 */ // Label 631: @27750
9730 /* 27750 */ GIM_Reject,
9731 /* 27751 */ // Label 603: @27751
9732 /* 27751 */ GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(27862),
9733 /* 27756 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
9734 /* 27759 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9735 /* 27762 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 633*/ GIMT_Encode4(27801), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1298 //
9736 /* 27769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9737 /* 27773 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9738 /* 27777 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9739 /* 27781 */ // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
9740 /* 27781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
9741 /* 27784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9742 /* 27786 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9743 /* 27788 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9744 /* 27790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9745 /* 27793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9746 /* 27799 */ GIR_RootConstrainSelectedInstOperands,
9747 /* 27800 */ // GIR_Coverage, 1298,
9748 /* 27800 */ GIR_EraseRootFromParent_Done,
9749 /* 27801 */ // Label 633: @27801
9750 /* 27801 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 634*/ GIMT_Encode4(27861), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3791 //
9751 /* 27808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9752 /* 27812 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9753 /* 27816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9754 /* 27820 */ // (xor:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VEOR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
9755 /* 27820 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9756 /* 27823 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9757 /* 27827 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9758 /* 27832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
9759 /* 27835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9760 /* 27837 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9761 /* 27839 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9762 /* 27841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9763 /* 27844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9764 /* 27850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9765 /* 27856 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9766 /* 27859 */ GIR_RootConstrainSelectedInstOperands,
9767 /* 27860 */ // GIR_Coverage, 3791,
9768 /* 27860 */ GIR_EraseRootFromParent_Done,
9769 /* 27861 */ // Label 634: @27861
9770 /* 27861 */ GIM_Reject,
9771 /* 27862 */ // Label 632: @27862
9772 /* 27862 */ GIM_Reject,
9773 /* 27863 */ // Label 604: @27863
9774 /* 27863 */ GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(27974),
9775 /* 27868 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
9776 /* 27871 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9777 /* 27874 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 636*/ GIMT_Encode4(27913), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2930 //
9778 /* 27881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9779 /* 27885 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9780 /* 27889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9781 /* 27893 */ // (xor:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VEORq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
9782 /* 27893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
9783 /* 27896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9784 /* 27898 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9785 /* 27900 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9786 /* 27902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9787 /* 27905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9788 /* 27911 */ GIR_RootConstrainSelectedInstOperands,
9789 /* 27912 */ // GIR_Coverage, 2930,
9790 /* 27912 */ GIR_EraseRootFromParent_Done,
9791 /* 27913 */ // Label 636: @27913
9792 /* 27913 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 637*/ GIMT_Encode4(27973), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3795 //
9793 /* 27920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9794 /* 27924 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9795 /* 27928 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9796 /* 27932 */ // (xor:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VEOR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
9797 /* 27932 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9798 /* 27935 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9799 /* 27939 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9800 /* 27944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
9801 /* 27947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9802 /* 27949 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9803 /* 27951 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9804 /* 27953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9805 /* 27956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9806 /* 27962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9807 /* 27968 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9808 /* 27971 */ GIR_RootConstrainSelectedInstOperands,
9809 /* 27972 */ // GIR_Coverage, 3795,
9810 /* 27972 */ GIR_EraseRootFromParent_Done,
9811 /* 27973 */ // Label 637: @27973
9812 /* 27973 */ GIM_Reject,
9813 /* 27974 */ // Label 635: @27974
9814 /* 27974 */ GIM_Reject,
9815 /* 27975 */ // Label 605: @27975
9816 /* 27975 */ GIM_Reject,
9817 /* 27976 */ // Label 8: @27976
9818 /* 27976 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 644*/ GIMT_Encode4(28485),
9819 /* 27987 */ /*GILLT_v8s8*//*Label 638*/ GIMT_Encode4(28011),
9820 /* 27991 */ /*GILLT_v16s8*//*Label 639*/ GIMT_Encode4(28057),
9821 /* 27995 */ /*GILLT_v4s16*//*Label 640*/ GIMT_Encode4(28169),
9822 /* 27999 */ /*GILLT_v8s16*//*Label 641*/ GIMT_Encode4(28215),
9823 /* 28003 */ /*GILLT_v2s32*//*Label 642*/ GIMT_Encode4(28327),
9824 /* 28007 */ /*GILLT_v4s32*//*Label 643*/ GIMT_Encode4(28373),
9825 /* 28011 */ // Label 638: @28011
9826 /* 28011 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 645*/ GIMT_Encode4(28056), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1323 //
9827 /* 28018 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
9828 /* 28021 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
9829 /* 28024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9830 /* 28028 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9831 /* 28032 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9832 /* 28036 */ // (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
9833 /* 28036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i8),
9834 /* 28039 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9835 /* 28041 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9836 /* 28043 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9837 /* 28045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9838 /* 28048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9839 /* 28054 */ GIR_RootConstrainSelectedInstOperands,
9840 /* 28055 */ // GIR_Coverage, 1323,
9841 /* 28055 */ GIR_EraseRootFromParent_Done,
9842 /* 28056 */ // Label 645: @28056
9843 /* 28056 */ GIM_Reject,
9844 /* 28057 */ // Label 639: @28057
9845 /* 28057 */ GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(28168),
9846 /* 28062 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
9847 /* 28065 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9848 /* 28068 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 647*/ GIMT_Encode4(28107), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1324 //
9849 /* 28075 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9850 /* 28079 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9851 /* 28083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9852 /* 28087 */ // (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
9853 /* 28087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv16i8),
9854 /* 28090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9855 /* 28092 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9856 /* 28094 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9857 /* 28096 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9858 /* 28099 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9859 /* 28105 */ GIR_RootConstrainSelectedInstOperands,
9860 /* 28106 */ // GIR_Coverage, 1324,
9861 /* 28106 */ GIR_EraseRootFromParent_Done,
9862 /* 28107 */ // Label 647: @28107
9863 /* 28107 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 648*/ GIMT_Encode4(28167), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3946 //
9864 /* 28114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9865 /* 28118 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9866 /* 28122 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9867 /* 28126 */ // (abds:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
9868 /* 28126 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9869 /* 28129 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9870 /* 28133 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9871 /* 28138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8),
9872 /* 28141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9873 /* 28143 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9874 /* 28145 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9875 /* 28147 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9876 /* 28150 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9877 /* 28156 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9878 /* 28162 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9879 /* 28165 */ GIR_RootConstrainSelectedInstOperands,
9880 /* 28166 */ // GIR_Coverage, 3946,
9881 /* 28166 */ GIR_EraseRootFromParent_Done,
9882 /* 28167 */ // Label 648: @28167
9883 /* 28167 */ GIM_Reject,
9884 /* 28168 */ // Label 646: @28168
9885 /* 28168 */ GIM_Reject,
9886 /* 28169 */ // Label 640: @28169
9887 /* 28169 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 649*/ GIMT_Encode4(28214), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1319 //
9888 /* 28176 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
9889 /* 28179 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
9890 /* 28182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9891 /* 28186 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9892 /* 28190 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9893 /* 28194 */ // (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
9894 /* 28194 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i16),
9895 /* 28197 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9896 /* 28199 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9897 /* 28201 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9898 /* 28203 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9899 /* 28206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9900 /* 28212 */ GIR_RootConstrainSelectedInstOperands,
9901 /* 28213 */ // GIR_Coverage, 1319,
9902 /* 28213 */ GIR_EraseRootFromParent_Done,
9903 /* 28214 */ // Label 649: @28214
9904 /* 28214 */ GIM_Reject,
9905 /* 28215 */ // Label 641: @28215
9906 /* 28215 */ GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(28326),
9907 /* 28220 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
9908 /* 28223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9909 /* 28226 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 651*/ GIMT_Encode4(28265), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1321 //
9910 /* 28233 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9911 /* 28237 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9912 /* 28241 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9913 /* 28245 */ // (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
9914 /* 28245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i16),
9915 /* 28248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9916 /* 28250 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9917 /* 28252 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9918 /* 28254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9919 /* 28257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9920 /* 28263 */ GIR_RootConstrainSelectedInstOperands,
9921 /* 28264 */ // GIR_Coverage, 1321,
9922 /* 28264 */ GIR_EraseRootFromParent_Done,
9923 /* 28265 */ // Label 651: @28265
9924 /* 28265 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 652*/ GIMT_Encode4(28325), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3949 //
9925 /* 28272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9926 /* 28276 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9927 /* 28280 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9928 /* 28284 */ // (abds:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
9929 /* 28284 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9930 /* 28287 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9931 /* 28291 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9932 /* 28296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16),
9933 /* 28299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9934 /* 28301 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9935 /* 28303 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9936 /* 28305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9937 /* 28308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9938 /* 28314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9939 /* 28320 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9940 /* 28323 */ GIR_RootConstrainSelectedInstOperands,
9941 /* 28324 */ // GIR_Coverage, 3949,
9942 /* 28324 */ GIR_EraseRootFromParent_Done,
9943 /* 28325 */ // Label 652: @28325
9944 /* 28325 */ GIM_Reject,
9945 /* 28326 */ // Label 650: @28326
9946 /* 28326 */ GIM_Reject,
9947 /* 28327 */ // Label 642: @28327
9948 /* 28327 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 653*/ GIMT_Encode4(28372), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1320 //
9949 /* 28334 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
9950 /* 28337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
9951 /* 28340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9952 /* 28344 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9953 /* 28348 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9954 /* 28352 */ // (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
9955 /* 28352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv2i32),
9956 /* 28355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9957 /* 28357 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9958 /* 28359 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9959 /* 28361 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9960 /* 28364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9961 /* 28370 */ GIR_RootConstrainSelectedInstOperands,
9962 /* 28371 */ // GIR_Coverage, 1320,
9963 /* 28371 */ GIR_EraseRootFromParent_Done,
9964 /* 28372 */ // Label 653: @28372
9965 /* 28372 */ GIM_Reject,
9966 /* 28373 */ // Label 643: @28373
9967 /* 28373 */ GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(28484),
9968 /* 28378 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
9969 /* 28381 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9970 /* 28384 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 655*/ GIMT_Encode4(28423), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1322 //
9971 /* 28391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9972 /* 28395 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9973 /* 28399 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9974 /* 28403 */ // (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
9975 /* 28403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i32),
9976 /* 28406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9977 /* 28408 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9978 /* 28410 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9979 /* 28412 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9980 /* 28415 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9981 /* 28421 */ GIR_RootConstrainSelectedInstOperands,
9982 /* 28422 */ // GIR_Coverage, 1322,
9983 /* 28422 */ GIR_EraseRootFromParent_Done,
9984 /* 28423 */ // Label 655: @28423
9985 /* 28423 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 656*/ GIMT_Encode4(28483), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3953 //
9986 /* 28430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9987 /* 28434 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9988 /* 28438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9989 /* 28442 */ // (abds:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
9990 /* 28442 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9991 /* 28445 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9992 /* 28449 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9993 /* 28454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32),
9994 /* 28457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9995 /* 28459 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9996 /* 28461 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9997 /* 28463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9998 /* 28466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9999 /* 28472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10000 /* 28478 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10001 /* 28481 */ GIR_RootConstrainSelectedInstOperands,
10002 /* 28482 */ // GIR_Coverage, 3953,
10003 /* 28482 */ GIR_EraseRootFromParent_Done,
10004 /* 28483 */ // Label 656: @28483
10005 /* 28483 */ GIM_Reject,
10006 /* 28484 */ // Label 654: @28484
10007 /* 28484 */ GIM_Reject,
10008 /* 28485 */ // Label 644: @28485
10009 /* 28485 */ GIM_Reject,
10010 /* 28486 */ // Label 9: @28486
10011 /* 28486 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 663*/ GIMT_Encode4(28995),
10012 /* 28497 */ /*GILLT_v8s8*//*Label 657*/ GIMT_Encode4(28521),
10013 /* 28501 */ /*GILLT_v16s8*//*Label 658*/ GIMT_Encode4(28567),
10014 /* 28505 */ /*GILLT_v4s16*//*Label 659*/ GIMT_Encode4(28679),
10015 /* 28509 */ /*GILLT_v8s16*//*Label 660*/ GIMT_Encode4(28725),
10016 /* 28513 */ /*GILLT_v2s32*//*Label 661*/ GIMT_Encode4(28837),
10017 /* 28517 */ /*GILLT_v4s32*//*Label 662*/ GIMT_Encode4(28883),
10018 /* 28521 */ // Label 657: @28521
10019 /* 28521 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 664*/ GIMT_Encode4(28566), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1329 //
10020 /* 28528 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
10021 /* 28531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
10022 /* 28534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10023 /* 28538 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10024 /* 28542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10025 /* 28546 */ // (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
10026 /* 28546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i8),
10027 /* 28549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10028 /* 28551 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10029 /* 28553 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10030 /* 28555 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10031 /* 28558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10032 /* 28564 */ GIR_RootConstrainSelectedInstOperands,
10033 /* 28565 */ // GIR_Coverage, 1329,
10034 /* 28565 */ GIR_EraseRootFromParent_Done,
10035 /* 28566 */ // Label 664: @28566
10036 /* 28566 */ GIM_Reject,
10037 /* 28567 */ // Label 658: @28567
10038 /* 28567 */ GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(28678),
10039 /* 28572 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10040 /* 28575 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10041 /* 28578 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 666*/ GIMT_Encode4(28617), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1330 //
10042 /* 28585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10043 /* 28589 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10044 /* 28593 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10045 /* 28597 */ // (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
10046 /* 28597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv16i8),
10047 /* 28600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10048 /* 28602 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10049 /* 28604 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10050 /* 28606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10051 /* 28609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10052 /* 28615 */ GIR_RootConstrainSelectedInstOperands,
10053 /* 28616 */ // GIR_Coverage, 1330,
10054 /* 28616 */ GIR_EraseRootFromParent_Done,
10055 /* 28617 */ // Label 666: @28617
10056 /* 28617 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 667*/ GIMT_Encode4(28677), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3957 //
10057 /* 28624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10058 /* 28628 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10059 /* 28632 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10060 /* 28636 */ // (abdu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10061 /* 28636 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10062 /* 28639 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10063 /* 28643 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10064 /* 28648 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8),
10065 /* 28651 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10066 /* 28653 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10067 /* 28655 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10068 /* 28657 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10069 /* 28660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10070 /* 28666 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10071 /* 28672 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10072 /* 28675 */ GIR_RootConstrainSelectedInstOperands,
10073 /* 28676 */ // GIR_Coverage, 3957,
10074 /* 28676 */ GIR_EraseRootFromParent_Done,
10075 /* 28677 */ // Label 667: @28677
10076 /* 28677 */ GIM_Reject,
10077 /* 28678 */ // Label 665: @28678
10078 /* 28678 */ GIM_Reject,
10079 /* 28679 */ // Label 659: @28679
10080 /* 28679 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 668*/ GIMT_Encode4(28724), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1325 //
10081 /* 28686 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
10082 /* 28689 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
10083 /* 28692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10084 /* 28696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10085 /* 28700 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10086 /* 28704 */ // (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
10087 /* 28704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i16),
10088 /* 28707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10089 /* 28709 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10090 /* 28711 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10091 /* 28713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10092 /* 28716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10093 /* 28722 */ GIR_RootConstrainSelectedInstOperands,
10094 /* 28723 */ // GIR_Coverage, 1325,
10095 /* 28723 */ GIR_EraseRootFromParent_Done,
10096 /* 28724 */ // Label 668: @28724
10097 /* 28724 */ GIM_Reject,
10098 /* 28725 */ // Label 660: @28725
10099 /* 28725 */ GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(28836),
10100 /* 28730 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10101 /* 28733 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10102 /* 28736 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 670*/ GIMT_Encode4(28775), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1327 //
10103 /* 28743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10104 /* 28747 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10105 /* 28751 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10106 /* 28755 */ // (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
10107 /* 28755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i16),
10108 /* 28758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10109 /* 28760 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10110 /* 28762 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10111 /* 28764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10112 /* 28767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10113 /* 28773 */ GIR_RootConstrainSelectedInstOperands,
10114 /* 28774 */ // GIR_Coverage, 1327,
10115 /* 28774 */ GIR_EraseRootFromParent_Done,
10116 /* 28775 */ // Label 670: @28775
10117 /* 28775 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 671*/ GIMT_Encode4(28835), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3961 //
10118 /* 28782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10119 /* 28786 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10120 /* 28790 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10121 /* 28794 */ // (abdu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10122 /* 28794 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10123 /* 28797 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10124 /* 28801 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10125 /* 28806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16),
10126 /* 28809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10127 /* 28811 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10128 /* 28813 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10129 /* 28815 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10130 /* 28818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10131 /* 28824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10132 /* 28830 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10133 /* 28833 */ GIR_RootConstrainSelectedInstOperands,
10134 /* 28834 */ // GIR_Coverage, 3961,
10135 /* 28834 */ GIR_EraseRootFromParent_Done,
10136 /* 28835 */ // Label 671: @28835
10137 /* 28835 */ GIM_Reject,
10138 /* 28836 */ // Label 669: @28836
10139 /* 28836 */ GIM_Reject,
10140 /* 28837 */ // Label 661: @28837
10141 /* 28837 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 672*/ GIMT_Encode4(28882), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1326 //
10142 /* 28844 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
10143 /* 28847 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
10144 /* 28850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10145 /* 28854 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10146 /* 28858 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10147 /* 28862 */ // (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
10148 /* 28862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv2i32),
10149 /* 28865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10150 /* 28867 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10151 /* 28869 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10152 /* 28871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10153 /* 28874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10154 /* 28880 */ GIR_RootConstrainSelectedInstOperands,
10155 /* 28881 */ // GIR_Coverage, 1326,
10156 /* 28881 */ GIR_EraseRootFromParent_Done,
10157 /* 28882 */ // Label 672: @28882
10158 /* 28882 */ GIM_Reject,
10159 /* 28883 */ // Label 662: @28883
10160 /* 28883 */ GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(28994),
10161 /* 28888 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10162 /* 28891 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10163 /* 28894 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 674*/ GIMT_Encode4(28933), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1328 //
10164 /* 28901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10165 /* 28905 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10166 /* 28909 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10167 /* 28913 */ // (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
10168 /* 28913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i32),
10169 /* 28916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10170 /* 28918 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10171 /* 28920 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10172 /* 28922 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10173 /* 28925 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10174 /* 28931 */ GIR_RootConstrainSelectedInstOperands,
10175 /* 28932 */ // GIR_Coverage, 1328,
10176 /* 28932 */ GIR_EraseRootFromParent_Done,
10177 /* 28933 */ // Label 674: @28933
10178 /* 28933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 675*/ GIMT_Encode4(28993), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3965 //
10179 /* 28940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10180 /* 28944 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10181 /* 28948 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10182 /* 28952 */ // (abdu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10183 /* 28952 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10184 /* 28955 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10185 /* 28959 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10186 /* 28964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32),
10187 /* 28967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10188 /* 28969 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10189 /* 28971 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10190 /* 28973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10191 /* 28976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10192 /* 28982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10193 /* 28988 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10194 /* 28991 */ GIR_RootConstrainSelectedInstOperands,
10195 /* 28992 */ // GIR_Coverage, 3965,
10196 /* 28992 */ GIR_EraseRootFromParent_Done,
10197 /* 28993 */ // Label 675: @28993
10198 /* 28993 */ GIM_Reject,
10199 /* 28994 */ // Label 673: @28994
10200 /* 28994 */ GIM_Reject,
10201 /* 28995 */ // Label 663: @28995
10202 /* 28995 */ GIM_Reject,
10203 /* 28996 */ // Label 10: @28996
10204 /* 28996 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 679*/ GIMT_Encode4(29222),
10205 /* 29007 */ /*GILLT_v16s8*//*Label 676*/ GIMT_Encode4(29027), GIMT_Encode4(0),
10206 /* 29015 */ /*GILLT_v8s16*//*Label 677*/ GIMT_Encode4(29092), GIMT_Encode4(0),
10207 /* 29023 */ /*GILLT_v4s32*//*Label 678*/ GIMT_Encode4(29157),
10208 /* 29027 */ // Label 676: @29027
10209 /* 29027 */ GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(29091), // Rule ID 4005 //
10210 /* 29032 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10211 /* 29035 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10212 /* 29038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10213 /* 29042 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10214 /* 29046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10215 /* 29050 */ // (avgflooru:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10216 /* 29050 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10217 /* 29053 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10218 /* 29057 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10219 /* 29062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8),
10220 /* 29065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10221 /* 29067 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10222 /* 29069 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10223 /* 29071 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10224 /* 29074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10225 /* 29080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10226 /* 29086 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10227 /* 29089 */ GIR_RootConstrainSelectedInstOperands,
10228 /* 29090 */ // GIR_Coverage, 4005,
10229 /* 29090 */ GIR_EraseRootFromParent_Done,
10230 /* 29091 */ // Label 680: @29091
10231 /* 29091 */ GIM_Reject,
10232 /* 29092 */ // Label 677: @29092
10233 /* 29092 */ GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(29156), // Rule ID 4009 //
10234 /* 29097 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10235 /* 29100 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10236 /* 29103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10237 /* 29107 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10238 /* 29111 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10239 /* 29115 */ // (avgflooru:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10240 /* 29115 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10241 /* 29118 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10242 /* 29122 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10243 /* 29127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16),
10244 /* 29130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10245 /* 29132 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10246 /* 29134 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10247 /* 29136 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10248 /* 29139 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10249 /* 29145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10250 /* 29151 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10251 /* 29154 */ GIR_RootConstrainSelectedInstOperands,
10252 /* 29155 */ // GIR_Coverage, 4009,
10253 /* 29155 */ GIR_EraseRootFromParent_Done,
10254 /* 29156 */ // Label 681: @29156
10255 /* 29156 */ GIM_Reject,
10256 /* 29157 */ // Label 678: @29157
10257 /* 29157 */ GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(29221), // Rule ID 4013 //
10258 /* 29162 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10259 /* 29165 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10260 /* 29168 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10261 /* 29172 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10262 /* 29176 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10263 /* 29180 */ // (avgflooru:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10264 /* 29180 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10265 /* 29183 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10266 /* 29187 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10267 /* 29192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32),
10268 /* 29195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10269 /* 29197 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10270 /* 29199 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10271 /* 29201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10272 /* 29204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10273 /* 29210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10274 /* 29216 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10275 /* 29219 */ GIR_RootConstrainSelectedInstOperands,
10276 /* 29220 */ // GIR_Coverage, 4013,
10277 /* 29220 */ GIR_EraseRootFromParent_Done,
10278 /* 29221 */ // Label 682: @29221
10279 /* 29221 */ GIM_Reject,
10280 /* 29222 */ // Label 679: @29222
10281 /* 29222 */ GIM_Reject,
10282 /* 29223 */ // Label 11: @29223
10283 /* 29223 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 686*/ GIMT_Encode4(29449),
10284 /* 29234 */ /*GILLT_v16s8*//*Label 683*/ GIMT_Encode4(29254), GIMT_Encode4(0),
10285 /* 29242 */ /*GILLT_v8s16*//*Label 684*/ GIMT_Encode4(29319), GIMT_Encode4(0),
10286 /* 29250 */ /*GILLT_v4s32*//*Label 685*/ GIMT_Encode4(29384),
10287 /* 29254 */ // Label 683: @29254
10288 /* 29254 */ GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(29318), // Rule ID 3981 //
10289 /* 29259 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10290 /* 29262 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10291 /* 29265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10292 /* 29269 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10293 /* 29273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10294 /* 29277 */ // (avgceilu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10295 /* 29277 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10296 /* 29280 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10297 /* 29284 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10298 /* 29289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8),
10299 /* 29292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10300 /* 29294 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10301 /* 29296 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10302 /* 29298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10303 /* 29301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10304 /* 29307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10305 /* 29313 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10306 /* 29316 */ GIR_RootConstrainSelectedInstOperands,
10307 /* 29317 */ // GIR_Coverage, 3981,
10308 /* 29317 */ GIR_EraseRootFromParent_Done,
10309 /* 29318 */ // Label 687: @29318
10310 /* 29318 */ GIM_Reject,
10311 /* 29319 */ // Label 684: @29319
10312 /* 29319 */ GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(29383), // Rule ID 3985 //
10313 /* 29324 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10314 /* 29327 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10315 /* 29330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10316 /* 29334 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10317 /* 29338 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10318 /* 29342 */ // (avgceilu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10319 /* 29342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10320 /* 29345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10321 /* 29349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10322 /* 29354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16),
10323 /* 29357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10324 /* 29359 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10325 /* 29361 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10326 /* 29363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10327 /* 29366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10328 /* 29372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10329 /* 29378 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10330 /* 29381 */ GIR_RootConstrainSelectedInstOperands,
10331 /* 29382 */ // GIR_Coverage, 3985,
10332 /* 29382 */ GIR_EraseRootFromParent_Done,
10333 /* 29383 */ // Label 688: @29383
10334 /* 29383 */ GIM_Reject,
10335 /* 29384 */ // Label 685: @29384
10336 /* 29384 */ GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(29448), // Rule ID 3989 //
10337 /* 29389 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10338 /* 29392 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10339 /* 29395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10340 /* 29399 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10341 /* 29403 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10342 /* 29407 */ // (avgceilu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10343 /* 29407 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10344 /* 29410 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10345 /* 29414 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10346 /* 29419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32),
10347 /* 29422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10348 /* 29424 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10349 /* 29426 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10350 /* 29428 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10351 /* 29431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10352 /* 29437 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10353 /* 29443 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10354 /* 29446 */ GIR_RootConstrainSelectedInstOperands,
10355 /* 29447 */ // GIR_Coverage, 3989,
10356 /* 29447 */ GIR_EraseRootFromParent_Done,
10357 /* 29448 */ // Label 689: @29448
10358 /* 29448 */ GIM_Reject,
10359 /* 29449 */ // Label 686: @29449
10360 /* 29449 */ GIM_Reject,
10361 /* 29450 */ // Label 12: @29450
10362 /* 29450 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 693*/ GIMT_Encode4(29676),
10363 /* 29461 */ /*GILLT_v16s8*//*Label 690*/ GIMT_Encode4(29481), GIMT_Encode4(0),
10364 /* 29469 */ /*GILLT_v8s16*//*Label 691*/ GIMT_Encode4(29546), GIMT_Encode4(0),
10365 /* 29477 */ /*GILLT_v4s32*//*Label 692*/ GIMT_Encode4(29611),
10366 /* 29481 */ // Label 690: @29481
10367 /* 29481 */ GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(29545), // Rule ID 3994 //
10368 /* 29486 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10369 /* 29489 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10370 /* 29492 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10371 /* 29496 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10372 /* 29500 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10373 /* 29504 */ // (avgfloors:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10374 /* 29504 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10375 /* 29507 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10376 /* 29511 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10377 /* 29516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8),
10378 /* 29519 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10379 /* 29521 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10380 /* 29523 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10381 /* 29525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10382 /* 29528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10383 /* 29534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10384 /* 29540 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10385 /* 29543 */ GIR_RootConstrainSelectedInstOperands,
10386 /* 29544 */ // GIR_Coverage, 3994,
10387 /* 29544 */ GIR_EraseRootFromParent_Done,
10388 /* 29545 */ // Label 694: @29545
10389 /* 29545 */ GIM_Reject,
10390 /* 29546 */ // Label 691: @29546
10391 /* 29546 */ GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(29610), // Rule ID 3997 //
10392 /* 29551 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10393 /* 29554 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10394 /* 29557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10395 /* 29561 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10396 /* 29565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10397 /* 29569 */ // (avgfloors:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10398 /* 29569 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10399 /* 29572 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10400 /* 29576 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10401 /* 29581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16),
10402 /* 29584 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10403 /* 29586 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10404 /* 29588 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10405 /* 29590 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10406 /* 29593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10407 /* 29599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10408 /* 29605 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10409 /* 29608 */ GIR_RootConstrainSelectedInstOperands,
10410 /* 29609 */ // GIR_Coverage, 3997,
10411 /* 29609 */ GIR_EraseRootFromParent_Done,
10412 /* 29610 */ // Label 695: @29610
10413 /* 29610 */ GIM_Reject,
10414 /* 29611 */ // Label 692: @29611
10415 /* 29611 */ GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(29675), // Rule ID 4001 //
10416 /* 29616 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10417 /* 29619 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10418 /* 29622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10419 /* 29626 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10420 /* 29630 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10421 /* 29634 */ // (avgfloors:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10422 /* 29634 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10423 /* 29637 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10424 /* 29641 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10425 /* 29646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32),
10426 /* 29649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10427 /* 29651 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10428 /* 29653 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10429 /* 29655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10430 /* 29658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10431 /* 29664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10432 /* 29670 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10433 /* 29673 */ GIR_RootConstrainSelectedInstOperands,
10434 /* 29674 */ // GIR_Coverage, 4001,
10435 /* 29674 */ GIR_EraseRootFromParent_Done,
10436 /* 29675 */ // Label 696: @29675
10437 /* 29675 */ GIM_Reject,
10438 /* 29676 */ // Label 693: @29676
10439 /* 29676 */ GIM_Reject,
10440 /* 29677 */ // Label 13: @29677
10441 /* 29677 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 700*/ GIMT_Encode4(29903),
10442 /* 29688 */ /*GILLT_v16s8*//*Label 697*/ GIMT_Encode4(29708), GIMT_Encode4(0),
10443 /* 29696 */ /*GILLT_v8s16*//*Label 698*/ GIMT_Encode4(29773), GIMT_Encode4(0),
10444 /* 29704 */ /*GILLT_v4s32*//*Label 699*/ GIMT_Encode4(29838),
10445 /* 29708 */ // Label 697: @29708
10446 /* 29708 */ GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(29772), // Rule ID 3970 //
10447 /* 29713 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10448 /* 29716 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10449 /* 29719 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10450 /* 29723 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10451 /* 29727 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10452 /* 29731 */ // (avgceils:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10453 /* 29731 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10454 /* 29734 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10455 /* 29738 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10456 /* 29743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8),
10457 /* 29746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10458 /* 29748 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10459 /* 29750 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10460 /* 29752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10461 /* 29755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10462 /* 29761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10463 /* 29767 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10464 /* 29770 */ GIR_RootConstrainSelectedInstOperands,
10465 /* 29771 */ // GIR_Coverage, 3970,
10466 /* 29771 */ GIR_EraseRootFromParent_Done,
10467 /* 29772 */ // Label 701: @29772
10468 /* 29772 */ GIM_Reject,
10469 /* 29773 */ // Label 698: @29773
10470 /* 29773 */ GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(29837), // Rule ID 3973 //
10471 /* 29778 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10472 /* 29781 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10473 /* 29784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10474 /* 29788 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10475 /* 29792 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10476 /* 29796 */ // (avgceils:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10477 /* 29796 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10478 /* 29799 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10479 /* 29803 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10480 /* 29808 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16),
10481 /* 29811 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10482 /* 29813 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10483 /* 29815 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10484 /* 29817 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10485 /* 29820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10486 /* 29826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10487 /* 29832 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10488 /* 29835 */ GIR_RootConstrainSelectedInstOperands,
10489 /* 29836 */ // GIR_Coverage, 3973,
10490 /* 29836 */ GIR_EraseRootFromParent_Done,
10491 /* 29837 */ // Label 702: @29837
10492 /* 29837 */ GIM_Reject,
10493 /* 29838 */ // Label 699: @29838
10494 /* 29838 */ GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(29902), // Rule ID 3977 //
10495 /* 29843 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10496 /* 29846 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10497 /* 29849 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10498 /* 29853 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10499 /* 29857 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10500 /* 29861 */ // (avgceils:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10501 /* 29861 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10502 /* 29864 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10503 /* 29868 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10504 /* 29873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32),
10505 /* 29876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10506 /* 29878 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10507 /* 29880 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10508 /* 29882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10509 /* 29885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10510 /* 29891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10511 /* 29897 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10512 /* 29900 */ GIR_RootConstrainSelectedInstOperands,
10513 /* 29901 */ // GIR_Coverage, 3977,
10514 /* 29901 */ GIR_EraseRootFromParent_Done,
10515 /* 29902 */ // Label 703: @29902
10516 /* 29902 */ GIM_Reject,
10517 /* 29903 */ // Label 700: @29903
10518 /* 29903 */ GIM_Reject,
10519 /* 29904 */ // Label 14: @29904
10520 /* 29904 */ GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(30570),
10521 /* 29909 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
10522 /* 29912 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 709*/ GIMT_Encode4(30569),
10523 /* 29923 */ /*GILLT_v16s8*//*Label 705*/ GIMT_Encode4(29947), GIMT_Encode4(0),
10524 /* 29931 */ /*GILLT_v8s16*//*Label 706*/ GIMT_Encode4(30053), GIMT_Encode4(0),
10525 /* 29939 */ /*GILLT_v4s32*//*Label 707*/ GIMT_Encode4(30264),
10526 /* 29943 */ /*GILLT_v2s64*//*Label 708*/ GIMT_Encode4(30463),
10527 /* 29947 */ // Label 705: @29947
10528 /* 29947 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 710*/ GIMT_Encode4(30052), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3416 //
10529 /* 29954 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
10530 /* 29957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
10531 /* 29960 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID),
10532 /* 29964 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10533 /* 29968 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10534 /* 29972 */ // (concat_vectors:{ *:[v16i8] } DPR:{ *:[v8i8] }:$Dn, DPR:{ *:[v8i8] }:$Dm) => (INSERT_SUBREG:{ *:[v16i8] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), DPR:{ *:[v8i8] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v8i8] }:$Dm, dsub_1:{ *:[i32] })
10535 /* 29972 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
10536 /* 29975 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10537 /* 29979 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10538 /* 29984 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
10539 /* 29986 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
10540 /* 29989 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10541 /* 29993 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10542 /* 29998 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
10543 /* 30001 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn
10544 /* 30005 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
10545 /* 30008 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10546 /* 30013 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10547 /* 30018 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10548 /* 30023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10549 /* 30026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10550 /* 30028 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10551 /* 30031 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10552 /* 30033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
10553 /* 30036 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10554 /* 30041 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10555 /* 30046 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10556 /* 30051 */ // GIR_Coverage, 3416,
10557 /* 30051 */ GIR_EraseRootFromParent_Done,
10558 /* 30052 */ // Label 710: @30052
10559 /* 30052 */ GIM_Reject,
10560 /* 30053 */ // Label 706: @30053
10561 /* 30053 */ GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(30263),
10562 /* 30058 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
10563 /* 30061 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
10564 /* 30064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 712*/ GIMT_Encode4(30163), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3415 //
10565 /* 30071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID),
10566 /* 30075 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10567 /* 30079 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10568 /* 30083 */ // (concat_vectors:{ *:[v8i16] } DPR:{ *:[v4i16] }:$Dn, DPR:{ *:[v4i16] }:$Dm) => (INSERT_SUBREG:{ *:[v8i16] } (INSERT_SUBREG:{ *:[v8i16] } (IMPLICIT_DEF:{ *:[v8i16] }), DPR:{ *:[v4i16] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v4i16] }:$Dm, dsub_1:{ *:[i32] })
10569 /* 30083 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
10570 /* 30086 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10571 /* 30090 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10572 /* 30095 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
10573 /* 30097 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
10574 /* 30100 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10575 /* 30104 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10576 /* 30109 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
10577 /* 30112 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn
10578 /* 30116 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
10579 /* 30119 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10580 /* 30124 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10581 /* 30129 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10582 /* 30134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10583 /* 30137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10584 /* 30139 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10585 /* 30142 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10586 /* 30144 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
10587 /* 30147 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10588 /* 30152 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10589 /* 30157 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10590 /* 30162 */ // GIR_Coverage, 3415,
10591 /* 30162 */ GIR_EraseRootFromParent_Done,
10592 /* 30163 */ // Label 712: @30163
10593 /* 30163 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 713*/ GIMT_Encode4(30262), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3418 //
10594 /* 30170 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10595 /* 30174 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10596 /* 30178 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10597 /* 30182 */ // (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm) => (INSERT_SUBREG:{ *:[v8f16] } (INSERT_SUBREG:{ *:[v8f16] } (IMPLICIT_DEF:{ *:[v8f16] }), DPR:{ *:[v4f16] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v4f16] }:$Dm, dsub_1:{ *:[i32] })
10598 /* 30182 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16,
10599 /* 30185 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10600 /* 30189 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10601 /* 30194 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
10602 /* 30196 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16,
10603 /* 30199 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10604 /* 30203 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10605 /* 30208 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
10606 /* 30211 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn
10607 /* 30215 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
10608 /* 30218 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10609 /* 30223 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::QPRRegClassID),
10610 /* 30228 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10611 /* 30233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10612 /* 30236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10613 /* 30238 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10614 /* 30241 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10615 /* 30243 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
10616 /* 30246 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10617 /* 30251 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::QPRRegClassID),
10618 /* 30256 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10619 /* 30261 */ // GIR_Coverage, 3418,
10620 /* 30261 */ GIR_EraseRootFromParent_Done,
10621 /* 30262 */ // Label 713: @30262
10622 /* 30262 */ GIM_Reject,
10623 /* 30263 */ // Label 711: @30263
10624 /* 30263 */ GIM_Reject,
10625 /* 30264 */ // Label 707: @30264
10626 /* 30264 */ GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(30462),
10627 /* 30269 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
10628 /* 30272 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
10629 /* 30275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID),
10630 /* 30279 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10631 /* 30283 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10632 /* 30287 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 715*/ GIMT_Encode4(30374), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3414 //
10633 /* 30294 */ // (concat_vectors:{ *:[v4i32] } DPR:{ *:[v2i32] }:$Dn, DPR:{ *:[v2i32] }:$Dm) => (INSERT_SUBREG:{ *:[v4i32] } (INSERT_SUBREG:{ *:[v4i32] } (IMPLICIT_DEF:{ *:[v4i32] }), DPR:{ *:[v2i32] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v2i32] }:$Dm, dsub_1:{ *:[i32] })
10634 /* 30294 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
10635 /* 30297 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10636 /* 30301 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10637 /* 30306 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
10638 /* 30308 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10639 /* 30311 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10640 /* 30315 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10641 /* 30320 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
10642 /* 30323 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn
10643 /* 30327 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
10644 /* 30330 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10645 /* 30335 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10646 /* 30340 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10647 /* 30345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10648 /* 30348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10649 /* 30350 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10650 /* 30353 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10651 /* 30355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
10652 /* 30358 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10653 /* 30363 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10654 /* 30368 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10655 /* 30373 */ // GIR_Coverage, 3414,
10656 /* 30373 */ GIR_EraseRootFromParent_Done,
10657 /* 30374 */ // Label 715: @30374
10658 /* 30374 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 716*/ GIMT_Encode4(30461), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3417 //
10659 /* 30381 */ // (concat_vectors:{ *:[v4f32] } DPR:{ *:[v2f32] }:$Dn, DPR:{ *:[v2f32] }:$Dm) => (INSERT_SUBREG:{ *:[v4f32] } (INSERT_SUBREG:{ *:[v4f32] } (IMPLICIT_DEF:{ *:[v4f32] }), DPR:{ *:[v2f32] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v2f32] }:$Dm, dsub_1:{ *:[i32] })
10660 /* 30381 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
10661 /* 30384 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10662 /* 30388 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10663 /* 30393 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
10664 /* 30395 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10665 /* 30398 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10666 /* 30402 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10667 /* 30407 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
10668 /* 30410 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn
10669 /* 30414 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
10670 /* 30417 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10671 /* 30422 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10672 /* 30427 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10673 /* 30432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10674 /* 30435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10675 /* 30437 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10676 /* 30440 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10677 /* 30442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
10678 /* 30445 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10679 /* 30450 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10680 /* 30455 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10681 /* 30460 */ // GIR_Coverage, 3417,
10682 /* 30460 */ GIR_EraseRootFromParent_Done,
10683 /* 30461 */ // Label 716: @30461
10684 /* 30461 */ GIM_Reject,
10685 /* 30462 */ // Label 714: @30462
10686 /* 30462 */ GIM_Reject,
10687 /* 30463 */ // Label 708: @30463
10688 /* 30463 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 717*/ GIMT_Encode4(30568), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3413 //
10689 /* 30470 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
10690 /* 30473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
10691 /* 30476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPairRegClassID),
10692 /* 30480 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10693 /* 30484 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10694 /* 30488 */ // (concat_vectors:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm) => (INSERT_SUBREG:{ *:[v2i64] } (INSERT_SUBREG:{ *:[v2i64] } (IMPLICIT_DEF:{ *:[v2i64] }), DPR:{ *:[v1i64] }:$Dn, dsub_0:{ *:[i32] }), DPR:{ *:[v1i64] }:$Dm, dsub_1:{ *:[i32] })
10695 /* 30488 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s64,
10696 /* 30491 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10697 /* 30495 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10698 /* 30500 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
10699 /* 30502 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s64,
10700 /* 30505 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10701 /* 30509 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10702 /* 30514 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
10703 /* 30517 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dn
10704 /* 30521 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
10705 /* 30524 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10706 /* 30529 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10707 /* 30534 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10708 /* 30539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
10709 /* 30542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10710 /* 30544 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10711 /* 30547 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10712 /* 30549 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/2,
10713 /* 30552 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
10714 /* 30557 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPairRegClassID),
10715 /* 30562 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(ARM::DPRRegClassID),
10716 /* 30567 */ // GIR_Coverage, 3413,
10717 /* 30567 */ GIR_EraseRootFromParent_Done,
10718 /* 30568 */ // Label 717: @30568
10719 /* 30568 */ GIM_Reject,
10720 /* 30569 */ // Label 709: @30569
10721 /* 30569 */ GIM_Reject,
10722 /* 30570 */ // Label 704: @30570
10723 /* 30570 */ GIM_Reject,
10724 /* 30571 */ // Label 15: @30571
10725 /* 30571 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 727*/ GIMT_Encode4(37757),
10726 /* 30582 */ /*GILLT_s32*//*Label 718*/ GIMT_Encode4(30634),
10727 /* 30586 */ /*GILLT_s64*//*Label 719*/ GIMT_Encode4(30777), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
10728 /* 30606 */ /*GILLT_v8s8*//*Label 720*/ GIMT_Encode4(31379),
10729 /* 30610 */ /*GILLT_v16s8*//*Label 721*/ GIMT_Encode4(31746),
10730 /* 30614 */ /*GILLT_v4s16*//*Label 722*/ GIMT_Encode4(32527),
10731 /* 30618 */ /*GILLT_v8s16*//*Label 723*/ GIMT_Encode4(33129),
10732 /* 30622 */ /*GILLT_v2s32*//*Label 724*/ GIMT_Encode4(34471),
10733 /* 30626 */ /*GILLT_v4s32*//*Label 725*/ GIMT_Encode4(35073),
10734 /* 30630 */ /*GILLT_v2s64*//*Label 726*/ GIMT_Encode4(36415),
10735 /* 30634 */ // Label 718: @30634
10736 /* 30634 */ GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(30776),
10737 /* 30639 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
10738 /* 30642 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 729*/ GIMT_Encode4(30675), GIMT_Encode2(GIFBS_HasFPRegs), // Rule ID 740 //
10739 /* 30649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
10740 /* 30653 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
10741 /* 30657 */ // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn) => (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn)
10742 /* 30657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVRS),
10743 /* 30660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
10744 /* 30662 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
10745 /* 30664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10746 /* 30667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10747 /* 30673 */ GIR_RootConstrainSelectedInstOperands,
10748 /* 30674 */ // GIR_Coverage, 740,
10749 /* 30674 */ GIR_EraseRootFromParent_Done,
10750 /* 30675 */ // Label 729: @30675
10751 /* 30675 */ GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(30775),
10752 /* 30680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
10753 /* 30684 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
10754 /* 30688 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 731*/ GIMT_Encode4(30713), GIMT_Encode2(GIFBS_HasFPRegs_UseVMOVSR), // Rule ID 741 //
10755 /* 30695 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt) => (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt)
10756 /* 30695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVSR),
10757 /* 30698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sn]
10758 /* 30700 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt
10759 /* 30702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10760 /* 30705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10761 /* 30711 */ GIR_RootConstrainSelectedInstOperands,
10762 /* 30712 */ // GIR_Coverage, 741,
10763 /* 30712 */ GIR_EraseRootFromParent_Done,
10764 /* 30713 */ // Label 731: @30713
10765 /* 30713 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 732*/ GIMT_Encode4(30774), GIMT_Encode2(GIFBS_DontUseVMOVSR_HasNEON), // Rule ID 3107 //
10766 /* 30720 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VMOVDRR:{ *:[f64] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$a), ssub_0:{ *:[i32] })
10767 /* 30720 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
10768 /* 30723 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VMOVDRR),
10769 /* 30727 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10770 /* 30732 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
10771 /* 30736 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
10772 /* 30740 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
10773 /* 30743 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10774 /* 30749 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
10775 /* 30751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10776 /* 30754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10777 /* 30756 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
10778 /* 30763 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
10779 /* 30768 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
10780 /* 30773 */ // GIR_Coverage, 3107,
10781 /* 30773 */ GIR_EraseRootFromParent_Done,
10782 /* 30774 */ // Label 732: @30774
10783 /* 30774 */ GIM_Reject,
10784 /* 30775 */ // Label 730: @30775
10785 /* 30775 */ GIM_Reject,
10786 /* 30776 */ // Label 728: @30776
10787 /* 30776 */ GIM_Reject,
10788 /* 30777 */ // Label 719: @30777
10789 /* 30777 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 737*/ GIMT_Encode4(31378),
10790 /* 30788 */ /*GILLT_s64*//*Label 733*/ GIMT_Encode4(30828), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
10791 /* 30808 */ /*GILLT_v8s8*//*Label 734*/ GIMT_Encode4(30883), GIMT_Encode4(0),
10792 /* 30816 */ /*GILLT_v4s16*//*Label 735*/ GIMT_Encode4(30988), GIMT_Encode4(0),
10793 /* 30824 */ /*GILLT_v2s32*//*Label 736*/ GIMT_Encode4(31183),
10794 /* 30828 */ // Label 733: @30828
10795 /* 30828 */ GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(30882),
10796 /* 30833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10797 /* 30837 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10798 /* 30841 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 739*/ GIMT_Encode4(30861), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3109 //
10799 /* 30848 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[f64] }:$src
10800 /* 30848 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10801 /* 30851 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10802 /* 30853 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10803 /* 30855 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10804 /* 30860 */ // GIR_Coverage, 3109,
10805 /* 30860 */ GIR_EraseRootFromParent_Done,
10806 /* 30861 */ // Label 739: @30861
10807 /* 30861 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 740*/ GIMT_Encode4(30881), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3110 //
10808 /* 30868 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v1i64] }:$src
10809 /* 30868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10810 /* 30871 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10811 /* 30873 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10812 /* 30875 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10813 /* 30880 */ // GIR_Coverage, 3110,
10814 /* 30880 */ GIR_EraseRootFromParent_Done,
10815 /* 30881 */ // Label 740: @30881
10816 /* 30881 */ GIM_Reject,
10817 /* 30882 */ // Label 738: @30882
10818 /* 30882 */ GIM_Reject,
10819 /* 30883 */ // Label 734: @30883
10820 /* 30883 */ GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(30987),
10821 /* 30888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10822 /* 30892 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10823 /* 30896 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 742*/ GIMT_Encode4(30916), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3125 //
10824 /* 30903 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[f64] }:$src
10825 /* 30903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10826 /* 30906 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10827 /* 30908 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10828 /* 30910 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10829 /* 30915 */ // GIR_Coverage, 3125,
10830 /* 30915 */ GIR_EraseRootFromParent_Done,
10831 /* 30916 */ // Label 742: @30916
10832 /* 30916 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 743*/ GIMT_Encode4(30936), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3130 //
10833 /* 30923 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v1i64] }:$src
10834 /* 30923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10835 /* 30926 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10836 /* 30928 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10837 /* 30930 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10838 /* 30935 */ // GIR_Coverage, 3130,
10839 /* 30935 */ GIR_EraseRootFromParent_Done,
10840 /* 30936 */ // Label 743: @30936
10841 /* 30936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 744*/ GIMT_Encode4(30961), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3197 //
10842 /* 30943 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src)
10843 /* 30943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
10844 /* 30946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10845 /* 30948 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10846 /* 30950 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10847 /* 30953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10848 /* 30959 */ GIR_RootConstrainSelectedInstOperands,
10849 /* 30960 */ // GIR_Coverage, 3197,
10850 /* 30960 */ GIR_EraseRootFromParent_Done,
10851 /* 30961 */ // Label 744: @30961
10852 /* 30961 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 745*/ GIMT_Encode4(30986), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3202 //
10853 /* 30968 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)
10854 /* 30968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
10855 /* 30971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10856 /* 30973 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10857 /* 30975 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10858 /* 30978 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10859 /* 30984 */ GIR_RootConstrainSelectedInstOperands,
10860 /* 30985 */ // GIR_Coverage, 3202,
10861 /* 30985 */ GIR_EraseRootFromParent_Done,
10862 /* 30986 */ // Label 745: @30986
10863 /* 30986 */ GIM_Reject,
10864 /* 30987 */ // Label 741: @30987
10865 /* 30987 */ GIM_Reject,
10866 /* 30988 */ // Label 735: @30988
10867 /* 30988 */ GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(31182),
10868 /* 30993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10869 /* 30997 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10870 /* 31001 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 747*/ GIMT_Encode4(31021), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3123 //
10871 /* 31008 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[f64] }:$src
10872 /* 31008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10873 /* 31011 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10874 /* 31013 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10875 /* 31015 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10876 /* 31020 */ // GIR_Coverage, 3123,
10877 /* 31020 */ GIR_EraseRootFromParent_Done,
10878 /* 31021 */ // Label 747: @31021
10879 /* 31021 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 748*/ GIMT_Encode4(31041), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3124 //
10880 /* 31028 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[f64] }:$src
10881 /* 31028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10882 /* 31031 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10883 /* 31033 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10884 /* 31035 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10885 /* 31040 */ // GIR_Coverage, 3124,
10886 /* 31040 */ GIR_EraseRootFromParent_Done,
10887 /* 31041 */ // Label 748: @31041
10888 /* 31041 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 749*/ GIMT_Encode4(31061), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3128 //
10889 /* 31048 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v1i64] }:$src
10890 /* 31048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10891 /* 31051 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10892 /* 31053 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10893 /* 31055 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10894 /* 31060 */ // GIR_Coverage, 3128,
10895 /* 31060 */ GIR_EraseRootFromParent_Done,
10896 /* 31061 */ // Label 749: @31061
10897 /* 31061 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 750*/ GIMT_Encode4(31081), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3129 //
10898 /* 31068 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v1i64] }:$src
10899 /* 31068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10900 /* 31071 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10901 /* 31073 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10902 /* 31075 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10903 /* 31080 */ // GIR_Coverage, 3129,
10904 /* 31080 */ GIR_EraseRootFromParent_Done,
10905 /* 31081 */ // Label 750: @31081
10906 /* 31081 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 751*/ GIMT_Encode4(31106), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3195 //
10907 /* 31088 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src)
10908 /* 31088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
10909 /* 31091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10910 /* 31093 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10911 /* 31095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10912 /* 31098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10913 /* 31104 */ GIR_RootConstrainSelectedInstOperands,
10914 /* 31105 */ // GIR_Coverage, 3195,
10915 /* 31105 */ GIR_EraseRootFromParent_Done,
10916 /* 31106 */ // Label 751: @31106
10917 /* 31106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 752*/ GIMT_Encode4(31131), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3196 //
10918 /* 31113 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src)
10919 /* 31113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
10920 /* 31116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10921 /* 31118 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10922 /* 31120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10923 /* 31123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10924 /* 31129 */ GIR_RootConstrainSelectedInstOperands,
10925 /* 31130 */ // GIR_Coverage, 3196,
10926 /* 31130 */ GIR_EraseRootFromParent_Done,
10927 /* 31131 */ // Label 752: @31131
10928 /* 31131 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 753*/ GIMT_Encode4(31156), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3200 //
10929 /* 31138 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src)
10930 /* 31138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
10931 /* 31141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10932 /* 31143 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10933 /* 31145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10934 /* 31148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10935 /* 31154 */ GIR_RootConstrainSelectedInstOperands,
10936 /* 31155 */ // GIR_Coverage, 3200,
10937 /* 31155 */ GIR_EraseRootFromParent_Done,
10938 /* 31156 */ // Label 753: @31156
10939 /* 31156 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 754*/ GIMT_Encode4(31181), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3201 //
10940 /* 31163 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)
10941 /* 31163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
10942 /* 31166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10943 /* 31168 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10944 /* 31170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10945 /* 31173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10946 /* 31179 */ GIR_RootConstrainSelectedInstOperands,
10947 /* 31180 */ // GIR_Coverage, 3201,
10948 /* 31180 */ GIR_EraseRootFromParent_Done,
10949 /* 31181 */ // Label 754: @31181
10950 /* 31181 */ GIM_Reject,
10951 /* 31182 */ // Label 746: @31182
10952 /* 31182 */ GIM_Reject,
10953 /* 31183 */ // Label 736: @31183
10954 /* 31183 */ GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(31377),
10955 /* 31188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10956 /* 31192 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10957 /* 31196 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 756*/ GIMT_Encode4(31216), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3121 //
10958 /* 31203 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[f64] }:$src
10959 /* 31203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10960 /* 31206 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10961 /* 31208 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10962 /* 31210 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10963 /* 31215 */ // GIR_Coverage, 3121,
10964 /* 31215 */ GIR_EraseRootFromParent_Done,
10965 /* 31216 */ // Label 756: @31216
10966 /* 31216 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 757*/ GIMT_Encode4(31236), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3122 //
10967 /* 31223 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[f64] }:$src
10968 /* 31223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10969 /* 31226 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10970 /* 31228 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10971 /* 31230 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10972 /* 31235 */ // GIR_Coverage, 3122,
10973 /* 31235 */ GIR_EraseRootFromParent_Done,
10974 /* 31236 */ // Label 757: @31236
10975 /* 31236 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 758*/ GIMT_Encode4(31256), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3126 //
10976 /* 31243 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v1i64] }:$src
10977 /* 31243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10978 /* 31246 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10979 /* 31248 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10980 /* 31250 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10981 /* 31255 */ // GIR_Coverage, 3126,
10982 /* 31255 */ GIR_EraseRootFromParent_Done,
10983 /* 31256 */ // Label 758: @31256
10984 /* 31256 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 759*/ GIMT_Encode4(31276), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3127 //
10985 /* 31263 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v1i64] }:$src
10986 /* 31263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10987 /* 31266 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
10988 /* 31268 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10989 /* 31270 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
10990 /* 31275 */ // GIR_Coverage, 3127,
10991 /* 31275 */ GIR_EraseRootFromParent_Done,
10992 /* 31276 */ // Label 759: @31276
10993 /* 31276 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 760*/ GIMT_Encode4(31301), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3193 //
10994 /* 31283 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src)
10995 /* 31283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
10996 /* 31286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10997 /* 31288 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
10998 /* 31290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10999 /* 31293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11000 /* 31299 */ GIR_RootConstrainSelectedInstOperands,
11001 /* 31300 */ // GIR_Coverage, 3193,
11002 /* 31300 */ GIR_EraseRootFromParent_Done,
11003 /* 31301 */ // Label 760: @31301
11004 /* 31301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 761*/ GIMT_Encode4(31326), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3194 //
11005 /* 31308 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src)
11006 /* 31308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11007 /* 31311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11008 /* 31313 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11009 /* 31315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11010 /* 31318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11011 /* 31324 */ GIR_RootConstrainSelectedInstOperands,
11012 /* 31325 */ // GIR_Coverage, 3194,
11013 /* 31325 */ GIR_EraseRootFromParent_Done,
11014 /* 31326 */ // Label 761: @31326
11015 /* 31326 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 762*/ GIMT_Encode4(31351), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3198 //
11016 /* 31333 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)
11017 /* 31333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11018 /* 31336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11019 /* 31338 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11020 /* 31340 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11021 /* 31343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11022 /* 31349 */ GIR_RootConstrainSelectedInstOperands,
11023 /* 31350 */ // GIR_Coverage, 3198,
11024 /* 31350 */ GIR_EraseRootFromParent_Done,
11025 /* 31351 */ // Label 762: @31351
11026 /* 31351 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 763*/ GIMT_Encode4(31376), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3199 //
11027 /* 31358 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)
11028 /* 31358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11029 /* 31361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11030 /* 31363 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11031 /* 31365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11032 /* 31368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11033 /* 31374 */ GIR_RootConstrainSelectedInstOperands,
11034 /* 31375 */ // GIR_Coverage, 3199,
11035 /* 31375 */ GIR_EraseRootFromParent_Done,
11036 /* 31376 */ // Label 763: @31376
11037 /* 31376 */ GIM_Reject,
11038 /* 31377 */ // Label 755: @31377
11039 /* 31377 */ GIM_Reject,
11040 /* 31378 */ // Label 737: @31378
11041 /* 31378 */ GIM_Reject,
11042 /* 31379 */ // Label 720: @31379
11043 /* 31379 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 767*/ GIMT_Encode4(31745),
11044 /* 31390 */ /*GILLT_s64*//*Label 764*/ GIMT_Encode4(31430), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
11045 /* 31418 */ /*GILLT_v4s16*//*Label 765*/ GIMT_Encode4(31535), GIMT_Encode4(0),
11046 /* 31426 */ /*GILLT_v2s32*//*Label 766*/ GIMT_Encode4(31640),
11047 /* 31430 */ // Label 764: @31430
11048 /* 31430 */ GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(31534),
11049 /* 31435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11050 /* 31439 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11051 /* 31443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 769*/ GIMT_Encode4(31463), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3151 //
11052 /* 31450 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v8i8] }:$src
11053 /* 31450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11054 /* 31453 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11055 /* 31455 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11056 /* 31457 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11057 /* 31462 */ // GIR_Coverage, 3151,
11058 /* 31462 */ GIR_EraseRootFromParent_Done,
11059 /* 31463 */ // Label 769: @31463
11060 /* 31463 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 770*/ GIMT_Encode4(31483), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3152 //
11061 /* 31470 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v8i8] }:$src
11062 /* 31470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11063 /* 31473 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11064 /* 31475 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11065 /* 31477 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11066 /* 31482 */ // GIR_Coverage, 3152,
11067 /* 31482 */ GIR_EraseRootFromParent_Done,
11068 /* 31483 */ // Label 770: @31483
11069 /* 31483 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 771*/ GIMT_Encode4(31508), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3223 //
11070 /* 31490 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src)
11071 /* 31490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
11072 /* 31493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11073 /* 31495 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11074 /* 31497 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11075 /* 31500 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11076 /* 31506 */ GIR_RootConstrainSelectedInstOperands,
11077 /* 31507 */ // GIR_Coverage, 3223,
11078 /* 31507 */ GIR_EraseRootFromParent_Done,
11079 /* 31508 */ // Label 771: @31508
11080 /* 31508 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 772*/ GIMT_Encode4(31533), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3224 //
11081 /* 31515 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)
11082 /* 31515 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
11083 /* 31518 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11084 /* 31520 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11085 /* 31522 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11086 /* 31525 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11087 /* 31531 */ GIR_RootConstrainSelectedInstOperands,
11088 /* 31532 */ // GIR_Coverage, 3224,
11089 /* 31532 */ GIR_EraseRootFromParent_Done,
11090 /* 31533 */ // Label 772: @31533
11091 /* 31533 */ GIM_Reject,
11092 /* 31534 */ // Label 768: @31534
11093 /* 31534 */ GIM_Reject,
11094 /* 31535 */ // Label 765: @31535
11095 /* 31535 */ GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(31639),
11096 /* 31540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11097 /* 31544 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11098 /* 31548 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 774*/ GIMT_Encode4(31568), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3155 //
11099 /* 31555 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v8i8] }:$src
11100 /* 31555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11101 /* 31558 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11102 /* 31560 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11103 /* 31562 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11104 /* 31567 */ // GIR_Coverage, 3155,
11105 /* 31567 */ GIR_EraseRootFromParent_Done,
11106 /* 31568 */ // Label 774: @31568
11107 /* 31568 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 775*/ GIMT_Encode4(31588), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3156 //
11108 /* 31575 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v8i8] }:$src
11109 /* 31575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11110 /* 31578 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11111 /* 31580 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11112 /* 31582 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11113 /* 31587 */ // GIR_Coverage, 3156,
11114 /* 31587 */ GIR_EraseRootFromParent_Done,
11115 /* 31588 */ // Label 775: @31588
11116 /* 31588 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 776*/ GIMT_Encode4(31613), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3227 //
11117 /* 31595 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src)
11118 /* 31595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
11119 /* 31598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11120 /* 31600 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11121 /* 31602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11122 /* 31605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11123 /* 31611 */ GIR_RootConstrainSelectedInstOperands,
11124 /* 31612 */ // GIR_Coverage, 3227,
11125 /* 31612 */ GIR_EraseRootFromParent_Done,
11126 /* 31613 */ // Label 776: @31613
11127 /* 31613 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 777*/ GIMT_Encode4(31638), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3228 //
11128 /* 31620 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)
11129 /* 31620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
11130 /* 31623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11131 /* 31625 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11132 /* 31627 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11133 /* 31630 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11134 /* 31636 */ GIR_RootConstrainSelectedInstOperands,
11135 /* 31637 */ // GIR_Coverage, 3228,
11136 /* 31637 */ GIR_EraseRootFromParent_Done,
11137 /* 31638 */ // Label 777: @31638
11138 /* 31638 */ GIM_Reject,
11139 /* 31639 */ // Label 773: @31639
11140 /* 31639 */ GIM_Reject,
11141 /* 31640 */ // Label 766: @31640
11142 /* 31640 */ GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(31744),
11143 /* 31645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11144 /* 31649 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11145 /* 31653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 779*/ GIMT_Encode4(31673), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3153 //
11146 /* 31660 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v8i8] }:$src
11147 /* 31660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11148 /* 31663 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11149 /* 31665 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11150 /* 31667 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11151 /* 31672 */ // GIR_Coverage, 3153,
11152 /* 31672 */ GIR_EraseRootFromParent_Done,
11153 /* 31673 */ // Label 779: @31673
11154 /* 31673 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 780*/ GIMT_Encode4(31693), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3154 //
11155 /* 31680 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v8i8] }:$src
11156 /* 31680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11157 /* 31683 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11158 /* 31685 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11159 /* 31687 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11160 /* 31692 */ // GIR_Coverage, 3154,
11161 /* 31692 */ GIR_EraseRootFromParent_Done,
11162 /* 31693 */ // Label 780: @31693
11163 /* 31693 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 781*/ GIMT_Encode4(31718), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3225 //
11164 /* 31700 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)
11165 /* 31700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
11166 /* 31703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11167 /* 31705 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11168 /* 31707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11169 /* 31710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11170 /* 31716 */ GIR_RootConstrainSelectedInstOperands,
11171 /* 31717 */ // GIR_Coverage, 3225,
11172 /* 31717 */ GIR_EraseRootFromParent_Done,
11173 /* 31718 */ // Label 781: @31718
11174 /* 31718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 782*/ GIMT_Encode4(31743), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3226 //
11175 /* 31725 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)
11176 /* 31725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
11177 /* 31728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11178 /* 31730 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11179 /* 31732 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11180 /* 31735 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11181 /* 31741 */ GIR_RootConstrainSelectedInstOperands,
11182 /* 31742 */ // GIR_Coverage, 3226,
11183 /* 31742 */ GIR_EraseRootFromParent_Done,
11184 /* 31743 */ // Label 782: @31743
11185 /* 31743 */ GIM_Reject,
11186 /* 31744 */ // Label 778: @31744
11187 /* 31744 */ GIM_Reject,
11188 /* 31745 */ // Label 767: @31745
11189 /* 31745 */ GIM_Reject,
11190 /* 31746 */ // Label 721: @31746
11191 /* 31746 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 786*/ GIMT_Encode4(32526),
11192 /* 31757 */ /*GILLT_v8s16*//*Label 783*/ GIMT_Encode4(31773), GIMT_Encode4(0),
11193 /* 31765 */ /*GILLT_v4s32*//*Label 784*/ GIMT_Encode4(32024),
11194 /* 31769 */ /*GILLT_v2s64*//*Label 785*/ GIMT_Encode4(32275),
11195 /* 31773 */ // Label 783: @31773
11196 /* 31773 */ GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(31877),
11197 /* 31778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11198 /* 31782 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11199 /* 31786 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 788*/ GIMT_Encode4(31806), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3191 //
11200 /* 31793 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v16i8] }:$src
11201 /* 31793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11202 /* 31796 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11203 /* 31798 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11204 /* 31800 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11205 /* 31805 */ // GIR_Coverage, 3191,
11206 /* 31805 */ GIR_EraseRootFromParent_Done,
11207 /* 31806 */ // Label 788: @31806
11208 /* 31806 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 789*/ GIMT_Encode4(31826), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3192 //
11209 /* 31813 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v16i8] }:$src
11210 /* 31813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11211 /* 31816 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11212 /* 31818 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11213 /* 31820 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11214 /* 31825 */ // GIR_Coverage, 3192,
11215 /* 31825 */ GIR_EraseRootFromParent_Done,
11216 /* 31826 */ // Label 789: @31826
11217 /* 31826 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 790*/ GIMT_Encode4(31851), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3263 //
11218 /* 31833 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src)
11219 /* 31833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
11220 /* 31836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11221 /* 31838 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11222 /* 31840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11223 /* 31843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11224 /* 31849 */ GIR_RootConstrainSelectedInstOperands,
11225 /* 31850 */ // GIR_Coverage, 3263,
11226 /* 31850 */ GIR_EraseRootFromParent_Done,
11227 /* 31851 */ // Label 790: @31851
11228 /* 31851 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 791*/ GIMT_Encode4(31876), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3264 //
11229 /* 31858 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)
11230 /* 31858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
11231 /* 31861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11232 /* 31863 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11233 /* 31865 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11234 /* 31868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11235 /* 31874 */ GIR_RootConstrainSelectedInstOperands,
11236 /* 31875 */ // GIR_Coverage, 3264,
11237 /* 31875 */ GIR_EraseRootFromParent_Done,
11238 /* 31876 */ // Label 791: @31876
11239 /* 31876 */ GIM_Reject,
11240 /* 31877 */ // Label 787: @31877
11241 /* 31877 */ GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(32023),
11242 /* 31882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11243 /* 31886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11244 /* 31890 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 793*/ GIMT_Encode4(31910), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5858 //
11245 /* 31897 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v16i8] }:$src
11246 /* 31897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11247 /* 31900 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11248 /* 31902 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11249 /* 31904 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11250 /* 31909 */ // GIR_Coverage, 5858,
11251 /* 31909 */ GIR_EraseRootFromParent_Done,
11252 /* 31910 */ // Label 793: @31910
11253 /* 31910 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 794*/ GIMT_Encode4(31930), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5859 //
11254 /* 31917 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v16i8] }:$src
11255 /* 31917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11256 /* 31920 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11257 /* 31922 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11258 /* 31924 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11259 /* 31929 */ // GIR_Coverage, 5859,
11260 /* 31929 */ GIR_EraseRootFromParent_Done,
11261 /* 31930 */ // Label 794: @31930
11262 /* 31930 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 795*/ GIMT_Encode4(31976), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5894 //
11263 /* 31937 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src)
11264 /* 31937 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11265 /* 31940 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11266 /* 31944 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11267 /* 31949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
11268 /* 31952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11269 /* 31954 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11270 /* 31956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11271 /* 31959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11272 /* 31965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11273 /* 31971 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11274 /* 31974 */ GIR_RootConstrainSelectedInstOperands,
11275 /* 31975 */ // GIR_Coverage, 5894,
11276 /* 31975 */ GIR_EraseRootFromParent_Done,
11277 /* 31976 */ // Label 795: @31976
11278 /* 31976 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 796*/ GIMT_Encode4(32022), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5895 //
11279 /* 31983 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src)
11280 /* 31983 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11281 /* 31986 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11282 /* 31990 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11283 /* 31995 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
11284 /* 31998 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11285 /* 32000 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11286 /* 32002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11287 /* 32005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11288 /* 32011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11289 /* 32017 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11290 /* 32020 */ GIR_RootConstrainSelectedInstOperands,
11291 /* 32021 */ // GIR_Coverage, 5895,
11292 /* 32021 */ GIR_EraseRootFromParent_Done,
11293 /* 32022 */ // Label 796: @32022
11294 /* 32022 */ GIM_Reject,
11295 /* 32023 */ // Label 792: @32023
11296 /* 32023 */ GIM_Reject,
11297 /* 32024 */ // Label 784: @32024
11298 /* 32024 */ GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(32128),
11299 /* 32029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11300 /* 32033 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11301 /* 32037 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 798*/ GIMT_Encode4(32057), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3189 //
11302 /* 32044 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v16i8] }:$src
11303 /* 32044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11304 /* 32047 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11305 /* 32049 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11306 /* 32051 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11307 /* 32056 */ // GIR_Coverage, 3189,
11308 /* 32056 */ GIR_EraseRootFromParent_Done,
11309 /* 32057 */ // Label 798: @32057
11310 /* 32057 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 799*/ GIMT_Encode4(32077), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3190 //
11311 /* 32064 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v16i8] }:$src
11312 /* 32064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11313 /* 32067 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11314 /* 32069 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11315 /* 32071 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11316 /* 32076 */ // GIR_Coverage, 3190,
11317 /* 32076 */ GIR_EraseRootFromParent_Done,
11318 /* 32077 */ // Label 799: @32077
11319 /* 32077 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 800*/ GIMT_Encode4(32102), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3261 //
11320 /* 32084 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)
11321 /* 32084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
11322 /* 32087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11323 /* 32089 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11324 /* 32091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11325 /* 32094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11326 /* 32100 */ GIR_RootConstrainSelectedInstOperands,
11327 /* 32101 */ // GIR_Coverage, 3261,
11328 /* 32101 */ GIR_EraseRootFromParent_Done,
11329 /* 32102 */ // Label 800: @32102
11330 /* 32102 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 801*/ GIMT_Encode4(32127), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3262 //
11331 /* 32109 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)
11332 /* 32109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
11333 /* 32112 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11334 /* 32114 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11335 /* 32116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11336 /* 32119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11337 /* 32125 */ GIR_RootConstrainSelectedInstOperands,
11338 /* 32126 */ // GIR_Coverage, 3262,
11339 /* 32126 */ GIR_EraseRootFromParent_Done,
11340 /* 32127 */ // Label 801: @32127
11341 /* 32127 */ GIM_Reject,
11342 /* 32128 */ // Label 797: @32128
11343 /* 32128 */ GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(32274),
11344 /* 32133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11345 /* 32137 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11346 /* 32141 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 803*/ GIMT_Encode4(32161), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5856 //
11347 /* 32148 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v16i8] }:$src
11348 /* 32148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11349 /* 32151 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11350 /* 32153 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11351 /* 32155 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11352 /* 32160 */ // GIR_Coverage, 5856,
11353 /* 32160 */ GIR_EraseRootFromParent_Done,
11354 /* 32161 */ // Label 803: @32161
11355 /* 32161 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 804*/ GIMT_Encode4(32181), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5857 //
11356 /* 32168 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v16i8] }:$src
11357 /* 32168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11358 /* 32171 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11359 /* 32173 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11360 /* 32175 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11361 /* 32180 */ // GIR_Coverage, 5857,
11362 /* 32180 */ GIR_EraseRootFromParent_Done,
11363 /* 32181 */ // Label 804: @32181
11364 /* 32181 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 805*/ GIMT_Encode4(32227), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5892 //
11365 /* 32188 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src)
11366 /* 32188 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11367 /* 32191 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11368 /* 32195 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11369 /* 32200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
11370 /* 32203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11371 /* 32205 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11372 /* 32207 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11373 /* 32210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11374 /* 32216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11375 /* 32222 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11376 /* 32225 */ GIR_RootConstrainSelectedInstOperands,
11377 /* 32226 */ // GIR_Coverage, 5892,
11378 /* 32226 */ GIR_EraseRootFromParent_Done,
11379 /* 32227 */ // Label 805: @32227
11380 /* 32227 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 806*/ GIMT_Encode4(32273), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5893 //
11381 /* 32234 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)
11382 /* 32234 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11383 /* 32237 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11384 /* 32241 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11385 /* 32246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
11386 /* 32249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11387 /* 32251 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11388 /* 32253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11389 /* 32256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11390 /* 32262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11391 /* 32268 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11392 /* 32271 */ GIR_RootConstrainSelectedInstOperands,
11393 /* 32272 */ // GIR_Coverage, 5893,
11394 /* 32272 */ GIR_EraseRootFromParent_Done,
11395 /* 32273 */ // Label 806: @32273
11396 /* 32273 */ GIM_Reject,
11397 /* 32274 */ // Label 802: @32274
11398 /* 32274 */ GIM_Reject,
11399 /* 32275 */ // Label 785: @32275
11400 /* 32275 */ GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(32379),
11401 /* 32280 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11402 /* 32284 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11403 /* 32288 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 808*/ GIMT_Encode4(32308), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3187 //
11404 /* 32295 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v16i8] }:$src
11405 /* 32295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11406 /* 32298 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11407 /* 32300 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11408 /* 32302 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11409 /* 32307 */ // GIR_Coverage, 3187,
11410 /* 32307 */ GIR_EraseRootFromParent_Done,
11411 /* 32308 */ // Label 808: @32308
11412 /* 32308 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 809*/ GIMT_Encode4(32328), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3188 //
11413 /* 32315 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v16i8] }:$src
11414 /* 32315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11415 /* 32318 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11416 /* 32320 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11417 /* 32322 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11418 /* 32327 */ // GIR_Coverage, 3188,
11419 /* 32327 */ GIR_EraseRootFromParent_Done,
11420 /* 32328 */ // Label 809: @32328
11421 /* 32328 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 810*/ GIMT_Encode4(32353), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3259 //
11422 /* 32335 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)
11423 /* 32335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
11424 /* 32338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11425 /* 32340 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11426 /* 32342 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11427 /* 32345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11428 /* 32351 */ GIR_RootConstrainSelectedInstOperands,
11429 /* 32352 */ // GIR_Coverage, 3259,
11430 /* 32352 */ GIR_EraseRootFromParent_Done,
11431 /* 32353 */ // Label 810: @32353
11432 /* 32353 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 811*/ GIMT_Encode4(32378), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3260 //
11433 /* 32360 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)
11434 /* 32360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
11435 /* 32363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11436 /* 32365 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11437 /* 32367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11438 /* 32370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11439 /* 32376 */ GIR_RootConstrainSelectedInstOperands,
11440 /* 32377 */ // GIR_Coverage, 3260,
11441 /* 32377 */ GIR_EraseRootFromParent_Done,
11442 /* 32378 */ // Label 811: @32378
11443 /* 32378 */ GIM_Reject,
11444 /* 32379 */ // Label 807: @32379
11445 /* 32379 */ GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(32525),
11446 /* 32384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11447 /* 32388 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11448 /* 32392 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 813*/ GIMT_Encode4(32412), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5854 //
11449 /* 32399 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v16i8] }:$src
11450 /* 32399 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11451 /* 32402 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11452 /* 32404 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11453 /* 32406 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11454 /* 32411 */ // GIR_Coverage, 5854,
11455 /* 32411 */ GIR_EraseRootFromParent_Done,
11456 /* 32412 */ // Label 813: @32412
11457 /* 32412 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 814*/ GIMT_Encode4(32432), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5855 //
11458 /* 32419 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v16i8] }:$src
11459 /* 32419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11460 /* 32422 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11461 /* 32424 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11462 /* 32426 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11463 /* 32431 */ // GIR_Coverage, 5855,
11464 /* 32431 */ GIR_EraseRootFromParent_Done,
11465 /* 32432 */ // Label 814: @32432
11466 /* 32432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 815*/ GIMT_Encode4(32478), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5890 //
11467 /* 32439 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src)
11468 /* 32439 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11469 /* 32442 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11470 /* 32446 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11471 /* 32451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
11472 /* 32454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11473 /* 32456 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11474 /* 32458 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11475 /* 32461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11476 /* 32467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11477 /* 32473 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11478 /* 32476 */ GIR_RootConstrainSelectedInstOperands,
11479 /* 32477 */ // GIR_Coverage, 5890,
11480 /* 32477 */ GIR_EraseRootFromParent_Done,
11481 /* 32478 */ // Label 815: @32478
11482 /* 32478 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 816*/ GIMT_Encode4(32524), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5891 //
11483 /* 32485 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src)
11484 /* 32485 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11485 /* 32488 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11486 /* 32492 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11487 /* 32497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
11488 /* 32500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11489 /* 32502 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11490 /* 32504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11491 /* 32507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11492 /* 32513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11493 /* 32519 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11494 /* 32522 */ GIR_RootConstrainSelectedInstOperands,
11495 /* 32523 */ // GIR_Coverage, 5891,
11496 /* 32523 */ GIR_EraseRootFromParent_Done,
11497 /* 32524 */ // Label 816: @32524
11498 /* 32524 */ GIM_Reject,
11499 /* 32525 */ // Label 812: @32525
11500 /* 32525 */ GIM_Reject,
11501 /* 32526 */ // Label 786: @32526
11502 /* 32526 */ GIM_Reject,
11503 /* 32527 */ // Label 722: @32527
11504 /* 32527 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 821*/ GIMT_Encode4(33128),
11505 /* 32538 */ /*GILLT_s64*//*Label 817*/ GIMT_Encode4(32578), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
11506 /* 32558 */ /*GILLT_v8s8*//*Label 818*/ GIMT_Encode4(32773), GIMT_Encode4(0),
11507 /* 32566 */ /*GILLT_v4s16*//*Label 819*/ GIMT_Encode4(32878), GIMT_Encode4(0),
11508 /* 32574 */ /*GILLT_v2s32*//*Label 820*/ GIMT_Encode4(32933),
11509 /* 32578 */ // Label 817: @32578
11510 /* 32578 */ GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(32772),
11511 /* 32583 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11512 /* 32587 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11513 /* 32591 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 823*/ GIMT_Encode4(32611), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3141 //
11514 /* 32598 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4f16] }:$src
11515 /* 32598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11516 /* 32601 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11517 /* 32603 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11518 /* 32605 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11519 /* 32610 */ // GIR_Coverage, 3141,
11520 /* 32610 */ GIR_EraseRootFromParent_Done,
11521 /* 32611 */ // Label 823: @32611
11522 /* 32611 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 824*/ GIMT_Encode4(32631), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3142 //
11523 /* 32618 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4f16] }:$src
11524 /* 32618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11525 /* 32621 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11526 /* 32623 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11527 /* 32625 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11528 /* 32630 */ // GIR_Coverage, 3142,
11529 /* 32630 */ GIR_EraseRootFromParent_Done,
11530 /* 32631 */ // Label 824: @32631
11531 /* 32631 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 825*/ GIMT_Encode4(32651), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3146 //
11532 /* 32638 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4i16] }:$src
11533 /* 32638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11534 /* 32641 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11535 /* 32643 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11536 /* 32645 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11537 /* 32650 */ // GIR_Coverage, 3146,
11538 /* 32650 */ GIR_EraseRootFromParent_Done,
11539 /* 32651 */ // Label 825: @32651
11540 /* 32651 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 826*/ GIMT_Encode4(32671), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3147 //
11541 /* 32658 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4i16] }:$src
11542 /* 32658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11543 /* 32661 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11544 /* 32663 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11545 /* 32665 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11546 /* 32670 */ // GIR_Coverage, 3147,
11547 /* 32670 */ GIR_EraseRootFromParent_Done,
11548 /* 32671 */ // Label 826: @32671
11549 /* 32671 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 827*/ GIMT_Encode4(32696), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3213 //
11550 /* 32678 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[f64] }:$src)
11551 /* 32678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11552 /* 32681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11553 /* 32683 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11554 /* 32685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11555 /* 32688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11556 /* 32694 */ GIR_RootConstrainSelectedInstOperands,
11557 /* 32695 */ // GIR_Coverage, 3213,
11558 /* 32695 */ GIR_EraseRootFromParent_Done,
11559 /* 32696 */ // Label 827: @32696
11560 /* 32696 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 828*/ GIMT_Encode4(32721), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3214 //
11561 /* 32703 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src)
11562 /* 32703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11563 /* 32706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11564 /* 32708 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11565 /* 32710 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11566 /* 32713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11567 /* 32719 */ GIR_RootConstrainSelectedInstOperands,
11568 /* 32720 */ // GIR_Coverage, 3214,
11569 /* 32720 */ GIR_EraseRootFromParent_Done,
11570 /* 32721 */ // Label 828: @32721
11571 /* 32721 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 829*/ GIMT_Encode4(32746), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3218 //
11572 /* 32728 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src)
11573 /* 32728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11574 /* 32731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11575 /* 32733 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11576 /* 32735 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11577 /* 32738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11578 /* 32744 */ GIR_RootConstrainSelectedInstOperands,
11579 /* 32745 */ // GIR_Coverage, 3218,
11580 /* 32745 */ GIR_EraseRootFromParent_Done,
11581 /* 32746 */ // Label 829: @32746
11582 /* 32746 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 830*/ GIMT_Encode4(32771), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3219 //
11583 /* 32753 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)
11584 /* 32753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11585 /* 32756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11586 /* 32758 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11587 /* 32760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11588 /* 32763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11589 /* 32769 */ GIR_RootConstrainSelectedInstOperands,
11590 /* 32770 */ // GIR_Coverage, 3219,
11591 /* 32770 */ GIR_EraseRootFromParent_Done,
11592 /* 32771 */ // Label 830: @32771
11593 /* 32771 */ GIM_Reject,
11594 /* 32772 */ // Label 822: @32772
11595 /* 32772 */ GIM_Reject,
11596 /* 32773 */ // Label 818: @32773
11597 /* 32773 */ GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(32877),
11598 /* 32778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11599 /* 32782 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11600 /* 32786 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 832*/ GIMT_Encode4(32806), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3145 //
11601 /* 32793 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4f16] }:$src
11602 /* 32793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11603 /* 32796 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11604 /* 32798 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11605 /* 32800 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11606 /* 32805 */ // GIR_Coverage, 3145,
11607 /* 32805 */ GIR_EraseRootFromParent_Done,
11608 /* 32806 */ // Label 832: @32806
11609 /* 32806 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 833*/ GIMT_Encode4(32826), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3150 //
11610 /* 32813 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4i16] }:$src
11611 /* 32813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11612 /* 32816 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11613 /* 32818 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11614 /* 32820 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11615 /* 32825 */ // GIR_Coverage, 3150,
11616 /* 32825 */ GIR_EraseRootFromParent_Done,
11617 /* 32826 */ // Label 833: @32826
11618 /* 32826 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 834*/ GIMT_Encode4(32851), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3217 //
11619 /* 32833 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src)
11620 /* 32833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
11621 /* 32836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11622 /* 32838 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11623 /* 32840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11624 /* 32843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11625 /* 32849 */ GIR_RootConstrainSelectedInstOperands,
11626 /* 32850 */ // GIR_Coverage, 3217,
11627 /* 32850 */ GIR_EraseRootFromParent_Done,
11628 /* 32851 */ // Label 834: @32851
11629 /* 32851 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 835*/ GIMT_Encode4(32876), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3222 //
11630 /* 32858 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)
11631 /* 32858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
11632 /* 32861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11633 /* 32863 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11634 /* 32865 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11635 /* 32868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11636 /* 32874 */ GIR_RootConstrainSelectedInstOperands,
11637 /* 32875 */ // GIR_Coverage, 3222,
11638 /* 32875 */ GIR_EraseRootFromParent_Done,
11639 /* 32876 */ // Label 835: @32876
11640 /* 32876 */ GIM_Reject,
11641 /* 32877 */ // Label 831: @32877
11642 /* 32877 */ GIM_Reject,
11643 /* 32878 */ // Label 819: @32878
11644 /* 32878 */ GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(32932),
11645 /* 32883 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11646 /* 32887 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11647 /* 32891 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 837*/ GIMT_Encode4(32911), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3113 //
11648 /* 32898 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v4i16] }:$src
11649 /* 32898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11650 /* 32901 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11651 /* 32903 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11652 /* 32905 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11653 /* 32910 */ // GIR_Coverage, 3113,
11654 /* 32910 */ GIR_EraseRootFromParent_Done,
11655 /* 32911 */ // Label 837: @32911
11656 /* 32911 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 838*/ GIMT_Encode4(32931), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3114 //
11657 /* 32918 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v4f16] }:$src
11658 /* 32918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11659 /* 32921 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11660 /* 32923 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11661 /* 32925 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11662 /* 32930 */ // GIR_Coverage, 3114,
11663 /* 32930 */ GIR_EraseRootFromParent_Done,
11664 /* 32931 */ // Label 838: @32931
11665 /* 32931 */ GIM_Reject,
11666 /* 32932 */ // Label 836: @32932
11667 /* 32932 */ GIM_Reject,
11668 /* 32933 */ // Label 820: @32933
11669 /* 32933 */ GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(33127),
11670 /* 32938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11671 /* 32942 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11672 /* 32946 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 840*/ GIMT_Encode4(32966), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3143 //
11673 /* 32953 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4f16] }:$src
11674 /* 32953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11675 /* 32956 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11676 /* 32958 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11677 /* 32960 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11678 /* 32965 */ // GIR_Coverage, 3143,
11679 /* 32965 */ GIR_EraseRootFromParent_Done,
11680 /* 32966 */ // Label 840: @32966
11681 /* 32966 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 841*/ GIMT_Encode4(32986), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3144 //
11682 /* 32973 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4f16] }:$src
11683 /* 32973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11684 /* 32976 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11685 /* 32978 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11686 /* 32980 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11687 /* 32985 */ // GIR_Coverage, 3144,
11688 /* 32985 */ GIR_EraseRootFromParent_Done,
11689 /* 32986 */ // Label 841: @32986
11690 /* 32986 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 842*/ GIMT_Encode4(33006), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3148 //
11691 /* 32993 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4i16] }:$src
11692 /* 32993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11693 /* 32996 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11694 /* 32998 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11695 /* 33000 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11696 /* 33005 */ // GIR_Coverage, 3148,
11697 /* 33005 */ GIR_EraseRootFromParent_Done,
11698 /* 33006 */ // Label 842: @33006
11699 /* 33006 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 843*/ GIMT_Encode4(33026), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3149 //
11700 /* 33013 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4i16] }:$src
11701 /* 33013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11702 /* 33016 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11703 /* 33018 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11704 /* 33020 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11705 /* 33025 */ // GIR_Coverage, 3149,
11706 /* 33025 */ GIR_EraseRootFromParent_Done,
11707 /* 33026 */ // Label 843: @33026
11708 /* 33026 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 844*/ GIMT_Encode4(33051), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3215 //
11709 /* 33033 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src)
11710 /* 33033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11711 /* 33036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11712 /* 33038 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11713 /* 33040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11714 /* 33043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11715 /* 33049 */ GIR_RootConstrainSelectedInstOperands,
11716 /* 33050 */ // GIR_Coverage, 3215,
11717 /* 33050 */ GIR_EraseRootFromParent_Done,
11718 /* 33051 */ // Label 844: @33051
11719 /* 33051 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 845*/ GIMT_Encode4(33076), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3216 //
11720 /* 33058 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src)
11721 /* 33058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11722 /* 33061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11723 /* 33063 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11724 /* 33065 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11725 /* 33068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11726 /* 33074 */ GIR_RootConstrainSelectedInstOperands,
11727 /* 33075 */ // GIR_Coverage, 3216,
11728 /* 33075 */ GIR_EraseRootFromParent_Done,
11729 /* 33076 */ // Label 845: @33076
11730 /* 33076 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 846*/ GIMT_Encode4(33101), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3220 //
11731 /* 33083 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)
11732 /* 33083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11733 /* 33086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11734 /* 33088 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11735 /* 33090 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11736 /* 33093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11737 /* 33099 */ GIR_RootConstrainSelectedInstOperands,
11738 /* 33100 */ // GIR_Coverage, 3220,
11739 /* 33100 */ GIR_EraseRootFromParent_Done,
11740 /* 33101 */ // Label 846: @33101
11741 /* 33101 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 847*/ GIMT_Encode4(33126), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3221 //
11742 /* 33108 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)
11743 /* 33108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11744 /* 33111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11745 /* 33113 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11746 /* 33115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11747 /* 33118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11748 /* 33124 */ GIR_RootConstrainSelectedInstOperands,
11749 /* 33125 */ // GIR_Coverage, 3221,
11750 /* 33125 */ GIR_EraseRootFromParent_Done,
11751 /* 33126 */ // Label 847: @33126
11752 /* 33126 */ GIM_Reject,
11753 /* 33127 */ // Label 839: @33127
11754 /* 33127 */ GIM_Reject,
11755 /* 33128 */ // Label 821: @33128
11756 /* 33128 */ GIM_Reject,
11757 /* 33129 */ // Label 723: @33129
11758 /* 33129 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 852*/ GIMT_Encode4(34470),
11759 /* 33140 */ /*GILLT_v16s8*//*Label 848*/ GIMT_Encode4(33164), GIMT_Encode4(0),
11760 /* 33148 */ /*GILLT_v8s16*//*Label 849*/ GIMT_Encode4(33415), GIMT_Encode4(0),
11761 /* 33156 */ /*GILLT_v4s32*//*Label 850*/ GIMT_Encode4(33524),
11762 /* 33160 */ /*GILLT_v2s64*//*Label 851*/ GIMT_Encode4(33997),
11763 /* 33164 */ // Label 848: @33164
11764 /* 33164 */ GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(33268),
11765 /* 33169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11766 /* 33173 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11767 /* 33177 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 854*/ GIMT_Encode4(33197), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3181 //
11768 /* 33184 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8f16] }:$src
11769 /* 33184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11770 /* 33187 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11771 /* 33189 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11772 /* 33191 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11773 /* 33196 */ // GIR_Coverage, 3181,
11774 /* 33196 */ GIR_EraseRootFromParent_Done,
11775 /* 33197 */ // Label 854: @33197
11776 /* 33197 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 855*/ GIMT_Encode4(33217), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3186 //
11777 /* 33204 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8i16] }:$src
11778 /* 33204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11779 /* 33207 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11780 /* 33209 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11781 /* 33211 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11782 /* 33216 */ // GIR_Coverage, 3186,
11783 /* 33216 */ GIR_EraseRootFromParent_Done,
11784 /* 33217 */ // Label 855: @33217
11785 /* 33217 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 856*/ GIMT_Encode4(33242), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3253 //
11786 /* 33224 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src)
11787 /* 33224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
11788 /* 33227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11789 /* 33229 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11790 /* 33231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11791 /* 33234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11792 /* 33240 */ GIR_RootConstrainSelectedInstOperands,
11793 /* 33241 */ // GIR_Coverage, 3253,
11794 /* 33241 */ GIR_EraseRootFromParent_Done,
11795 /* 33242 */ // Label 856: @33242
11796 /* 33242 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 857*/ GIMT_Encode4(33267), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3258 //
11797 /* 33249 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)
11798 /* 33249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
11799 /* 33252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11800 /* 33254 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11801 /* 33256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11802 /* 33259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11803 /* 33265 */ GIR_RootConstrainSelectedInstOperands,
11804 /* 33266 */ // GIR_Coverage, 3258,
11805 /* 33266 */ GIR_EraseRootFromParent_Done,
11806 /* 33267 */ // Label 857: @33267
11807 /* 33267 */ GIM_Reject,
11808 /* 33268 */ // Label 853: @33268
11809 /* 33268 */ GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(33414),
11810 /* 33273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11811 /* 33277 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11812 /* 33281 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 859*/ GIMT_Encode4(33301), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5848 //
11813 /* 33288 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8f16] }:$src
11814 /* 33288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11815 /* 33291 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11816 /* 33293 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11817 /* 33295 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11818 /* 33300 */ // GIR_Coverage, 5848,
11819 /* 33300 */ GIR_EraseRootFromParent_Done,
11820 /* 33301 */ // Label 859: @33301
11821 /* 33301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 860*/ GIMT_Encode4(33321), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5853 //
11822 /* 33308 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8i16] }:$src
11823 /* 33308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11824 /* 33311 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11825 /* 33313 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11826 /* 33315 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11827 /* 33320 */ // GIR_Coverage, 5853,
11828 /* 33320 */ GIR_EraseRootFromParent_Done,
11829 /* 33321 */ // Label 860: @33321
11830 /* 33321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 861*/ GIMT_Encode4(33367), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5884 //
11831 /* 33328 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src)
11832 /* 33328 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11833 /* 33331 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11834 /* 33335 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11835 /* 33340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
11836 /* 33343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11837 /* 33345 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11838 /* 33347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11839 /* 33350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11840 /* 33356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11841 /* 33362 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11842 /* 33365 */ GIR_RootConstrainSelectedInstOperands,
11843 /* 33366 */ // GIR_Coverage, 5884,
11844 /* 33366 */ GIR_EraseRootFromParent_Done,
11845 /* 33367 */ // Label 861: @33367
11846 /* 33367 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 862*/ GIMT_Encode4(33413), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5889 //
11847 /* 33374 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
11848 /* 33374 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
11849 /* 33377 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
11850 /* 33381 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11851 /* 33386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
11852 /* 33389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
11853 /* 33391 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11854 /* 33393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
11855 /* 33396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11856 /* 33402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11857 /* 33408 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
11858 /* 33411 */ GIR_RootConstrainSelectedInstOperands,
11859 /* 33412 */ // GIR_Coverage, 5889,
11860 /* 33412 */ GIR_EraseRootFromParent_Done,
11861 /* 33413 */ // Label 862: @33413
11862 /* 33413 */ GIM_Reject,
11863 /* 33414 */ // Label 858: @33414
11864 /* 33414 */ GIM_Reject,
11865 /* 33415 */ // Label 849: @33415
11866 /* 33415 */ GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(33469),
11867 /* 33420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11868 /* 33424 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11869 /* 33428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 864*/ GIMT_Encode4(33448), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3119 //
11870 /* 33435 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v8i16] }:$src
11871 /* 33435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11872 /* 33438 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11873 /* 33440 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11874 /* 33442 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11875 /* 33447 */ // GIR_Coverage, 3119,
11876 /* 33447 */ GIR_EraseRootFromParent_Done,
11877 /* 33448 */ // Label 864: @33448
11878 /* 33448 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 865*/ GIMT_Encode4(33468), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3120 //
11879 /* 33455 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v8f16] }:$src
11880 /* 33455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11881 /* 33458 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11882 /* 33460 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11883 /* 33462 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11884 /* 33467 */ // GIR_Coverage, 3120,
11885 /* 33467 */ GIR_EraseRootFromParent_Done,
11886 /* 33468 */ // Label 865: @33468
11887 /* 33468 */ GIM_Reject,
11888 /* 33469 */ // Label 863: @33469
11889 /* 33469 */ GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(33523),
11890 /* 33474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11891 /* 33478 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
11892 /* 33482 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 867*/ GIMT_Encode4(33502), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5822 //
11893 /* 33489 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v8i16] }:$src
11894 /* 33489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11895 /* 33492 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11896 /* 33494 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11897 /* 33496 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11898 /* 33501 */ // GIR_Coverage, 5822,
11899 /* 33501 */ GIR_EraseRootFromParent_Done,
11900 /* 33502 */ // Label 867: @33502
11901 /* 33502 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 868*/ GIMT_Encode4(33522), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5823 //
11902 /* 33509 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v8f16] }:$src
11903 /* 33509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11904 /* 33512 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11905 /* 33514 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11906 /* 33516 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
11907 /* 33521 */ // GIR_Coverage, 5823,
11908 /* 33521 */ GIR_EraseRootFromParent_Done,
11909 /* 33522 */ // Label 868: @33522
11910 /* 33522 */ GIM_Reject,
11911 /* 33523 */ // Label 866: @33523
11912 /* 33523 */ GIM_Reject,
11913 /* 33524 */ // Label 850: @33524
11914 /* 33524 */ GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(33718),
11915 /* 33529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11916 /* 33533 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11917 /* 33537 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 870*/ GIMT_Encode4(33557), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3179 //
11918 /* 33544 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8f16] }:$src
11919 /* 33544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11920 /* 33547 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11921 /* 33549 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11922 /* 33551 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11923 /* 33556 */ // GIR_Coverage, 3179,
11924 /* 33556 */ GIR_EraseRootFromParent_Done,
11925 /* 33557 */ // Label 870: @33557
11926 /* 33557 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 871*/ GIMT_Encode4(33577), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3180 //
11927 /* 33564 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8f16] }:$src
11928 /* 33564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11929 /* 33567 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11930 /* 33569 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11931 /* 33571 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11932 /* 33576 */ // GIR_Coverage, 3180,
11933 /* 33576 */ GIR_EraseRootFromParent_Done,
11934 /* 33577 */ // Label 871: @33577
11935 /* 33577 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 872*/ GIMT_Encode4(33597), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3184 //
11936 /* 33584 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8i16] }:$src
11937 /* 33584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11938 /* 33587 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11939 /* 33589 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11940 /* 33591 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11941 /* 33596 */ // GIR_Coverage, 3184,
11942 /* 33596 */ GIR_EraseRootFromParent_Done,
11943 /* 33597 */ // Label 872: @33597
11944 /* 33597 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 873*/ GIMT_Encode4(33617), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3185 //
11945 /* 33604 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8i16] }:$src
11946 /* 33604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11947 /* 33607 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11948 /* 33609 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11949 /* 33611 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11950 /* 33616 */ // GIR_Coverage, 3185,
11951 /* 33616 */ GIR_EraseRootFromParent_Done,
11952 /* 33617 */ // Label 873: @33617
11953 /* 33617 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 874*/ GIMT_Encode4(33642), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3251 //
11954 /* 33624 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src)
11955 /* 33624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
11956 /* 33627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11957 /* 33629 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11958 /* 33631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11959 /* 33634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11960 /* 33640 */ GIR_RootConstrainSelectedInstOperands,
11961 /* 33641 */ // GIR_Coverage, 3251,
11962 /* 33641 */ GIR_EraseRootFromParent_Done,
11963 /* 33642 */ // Label 874: @33642
11964 /* 33642 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 875*/ GIMT_Encode4(33667), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3252 //
11965 /* 33649 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src)
11966 /* 33649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
11967 /* 33652 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11968 /* 33654 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11969 /* 33656 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11970 /* 33659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11971 /* 33665 */ GIR_RootConstrainSelectedInstOperands,
11972 /* 33666 */ // GIR_Coverage, 3252,
11973 /* 33666 */ GIR_EraseRootFromParent_Done,
11974 /* 33667 */ // Label 875: @33667
11975 /* 33667 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 876*/ GIMT_Encode4(33692), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3256 //
11976 /* 33674 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)
11977 /* 33674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
11978 /* 33677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11979 /* 33679 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11980 /* 33681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11981 /* 33684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11982 /* 33690 */ GIR_RootConstrainSelectedInstOperands,
11983 /* 33691 */ // GIR_Coverage, 3256,
11984 /* 33691 */ GIR_EraseRootFromParent_Done,
11985 /* 33692 */ // Label 876: @33692
11986 /* 33692 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 877*/ GIMT_Encode4(33717), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3257 //
11987 /* 33699 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)
11988 /* 33699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
11989 /* 33702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11990 /* 33704 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11991 /* 33706 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11992 /* 33709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11993 /* 33715 */ GIR_RootConstrainSelectedInstOperands,
11994 /* 33716 */ // GIR_Coverage, 3257,
11995 /* 33716 */ GIR_EraseRootFromParent_Done,
11996 /* 33717 */ // Label 877: @33717
11997 /* 33717 */ GIM_Reject,
11998 /* 33718 */ // Label 869: @33718
11999 /* 33718 */ GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(33996),
12000 /* 33723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12001 /* 33727 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12002 /* 33731 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 879*/ GIMT_Encode4(33751), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5846 //
12003 /* 33738 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8f16] }:$src
12004 /* 33738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12005 /* 33741 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12006 /* 33743 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12007 /* 33745 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12008 /* 33750 */ // GIR_Coverage, 5846,
12009 /* 33750 */ GIR_EraseRootFromParent_Done,
12010 /* 33751 */ // Label 879: @33751
12011 /* 33751 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 880*/ GIMT_Encode4(33771), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5847 //
12012 /* 33758 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8f16] }:$src
12013 /* 33758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12014 /* 33761 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12015 /* 33763 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12016 /* 33765 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12017 /* 33770 */ // GIR_Coverage, 5847,
12018 /* 33770 */ GIR_EraseRootFromParent_Done,
12019 /* 33771 */ // Label 880: @33771
12020 /* 33771 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 881*/ GIMT_Encode4(33791), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5851 //
12021 /* 33778 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8i16] }:$src
12022 /* 33778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12023 /* 33781 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12024 /* 33783 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12025 /* 33785 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12026 /* 33790 */ // GIR_Coverage, 5851,
12027 /* 33790 */ GIR_EraseRootFromParent_Done,
12028 /* 33791 */ // Label 881: @33791
12029 /* 33791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 882*/ GIMT_Encode4(33811), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5852 //
12030 /* 33798 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8i16] }:$src
12031 /* 33798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12032 /* 33801 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12033 /* 33803 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12034 /* 33805 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12035 /* 33810 */ // GIR_Coverage, 5852,
12036 /* 33810 */ GIR_EraseRootFromParent_Done,
12037 /* 33811 */ // Label 882: @33811
12038 /* 33811 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 883*/ GIMT_Encode4(33857), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5882 //
12039 /* 33818 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src)
12040 /* 33818 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12041 /* 33821 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12042 /* 33825 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12043 /* 33830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12044 /* 33833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12045 /* 33835 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12046 /* 33837 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12047 /* 33840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12048 /* 33846 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12049 /* 33852 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12050 /* 33855 */ GIR_RootConstrainSelectedInstOperands,
12051 /* 33856 */ // GIR_Coverage, 5882,
12052 /* 33856 */ GIR_EraseRootFromParent_Done,
12053 /* 33857 */ // Label 883: @33857
12054 /* 33857 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 884*/ GIMT_Encode4(33903), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5883 //
12055 /* 33864 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src)
12056 /* 33864 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12057 /* 33867 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12058 /* 33871 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12059 /* 33876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12060 /* 33879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12061 /* 33881 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12062 /* 33883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12063 /* 33886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12064 /* 33892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12065 /* 33898 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12066 /* 33901 */ GIR_RootConstrainSelectedInstOperands,
12067 /* 33902 */ // GIR_Coverage, 5883,
12068 /* 33902 */ GIR_EraseRootFromParent_Done,
12069 /* 33903 */ // Label 884: @33903
12070 /* 33903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 885*/ GIMT_Encode4(33949), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5887 //
12071 /* 33910 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src)
12072 /* 33910 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12073 /* 33913 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12074 /* 33917 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12075 /* 33922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12076 /* 33925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12077 /* 33927 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12078 /* 33929 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12079 /* 33932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12080 /* 33938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12081 /* 33944 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12082 /* 33947 */ GIR_RootConstrainSelectedInstOperands,
12083 /* 33948 */ // GIR_Coverage, 5887,
12084 /* 33948 */ GIR_EraseRootFromParent_Done,
12085 /* 33949 */ // Label 885: @33949
12086 /* 33949 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 886*/ GIMT_Encode4(33995), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5888 //
12087 /* 33956 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src)
12088 /* 33956 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12089 /* 33959 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12090 /* 33963 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12091 /* 33968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12092 /* 33971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12093 /* 33973 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12094 /* 33975 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12095 /* 33978 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12096 /* 33984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12097 /* 33990 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12098 /* 33993 */ GIR_RootConstrainSelectedInstOperands,
12099 /* 33994 */ // GIR_Coverage, 5888,
12100 /* 33994 */ GIR_EraseRootFromParent_Done,
12101 /* 33995 */ // Label 886: @33995
12102 /* 33995 */ GIM_Reject,
12103 /* 33996 */ // Label 878: @33996
12104 /* 33996 */ GIM_Reject,
12105 /* 33997 */ // Label 851: @33997
12106 /* 33997 */ GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(34191),
12107 /* 34002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12108 /* 34006 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12109 /* 34010 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 888*/ GIMT_Encode4(34030), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3177 //
12110 /* 34017 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8f16] }:$src
12111 /* 34017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12112 /* 34020 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12113 /* 34022 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12114 /* 34024 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12115 /* 34029 */ // GIR_Coverage, 3177,
12116 /* 34029 */ GIR_EraseRootFromParent_Done,
12117 /* 34030 */ // Label 888: @34030
12118 /* 34030 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 889*/ GIMT_Encode4(34050), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3178 //
12119 /* 34037 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8f16] }:$src
12120 /* 34037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12121 /* 34040 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12122 /* 34042 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12123 /* 34044 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12124 /* 34049 */ // GIR_Coverage, 3178,
12125 /* 34049 */ GIR_EraseRootFromParent_Done,
12126 /* 34050 */ // Label 889: @34050
12127 /* 34050 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 890*/ GIMT_Encode4(34070), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3182 //
12128 /* 34057 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8i16] }:$src
12129 /* 34057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12130 /* 34060 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12131 /* 34062 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12132 /* 34064 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12133 /* 34069 */ // GIR_Coverage, 3182,
12134 /* 34069 */ GIR_EraseRootFromParent_Done,
12135 /* 34070 */ // Label 890: @34070
12136 /* 34070 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 891*/ GIMT_Encode4(34090), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3183 //
12137 /* 34077 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8i16] }:$src
12138 /* 34077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12139 /* 34080 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12140 /* 34082 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12141 /* 34084 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12142 /* 34089 */ // GIR_Coverage, 3183,
12143 /* 34089 */ GIR_EraseRootFromParent_Done,
12144 /* 34090 */ // Label 891: @34090
12145 /* 34090 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 892*/ GIMT_Encode4(34115), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3249 //
12146 /* 34097 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)
12147 /* 34097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12148 /* 34100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12149 /* 34102 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12150 /* 34104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12151 /* 34107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12152 /* 34113 */ GIR_RootConstrainSelectedInstOperands,
12153 /* 34114 */ // GIR_Coverage, 3249,
12154 /* 34114 */ GIR_EraseRootFromParent_Done,
12155 /* 34115 */ // Label 892: @34115
12156 /* 34115 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 893*/ GIMT_Encode4(34140), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3250 //
12157 /* 34122 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src)
12158 /* 34122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12159 /* 34125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12160 /* 34127 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12161 /* 34129 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12162 /* 34132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12163 /* 34138 */ GIR_RootConstrainSelectedInstOperands,
12164 /* 34139 */ // GIR_Coverage, 3250,
12165 /* 34139 */ GIR_EraseRootFromParent_Done,
12166 /* 34140 */ // Label 893: @34140
12167 /* 34140 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 894*/ GIMT_Encode4(34165), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3254 //
12168 /* 34147 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)
12169 /* 34147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12170 /* 34150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12171 /* 34152 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12172 /* 34154 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12173 /* 34157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12174 /* 34163 */ GIR_RootConstrainSelectedInstOperands,
12175 /* 34164 */ // GIR_Coverage, 3254,
12176 /* 34164 */ GIR_EraseRootFromParent_Done,
12177 /* 34165 */ // Label 894: @34165
12178 /* 34165 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 895*/ GIMT_Encode4(34190), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3255 //
12179 /* 34172 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)
12180 /* 34172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12181 /* 34175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12182 /* 34177 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12183 /* 34179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12184 /* 34182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12185 /* 34188 */ GIR_RootConstrainSelectedInstOperands,
12186 /* 34189 */ // GIR_Coverage, 3255,
12187 /* 34189 */ GIR_EraseRootFromParent_Done,
12188 /* 34190 */ // Label 895: @34190
12189 /* 34190 */ GIM_Reject,
12190 /* 34191 */ // Label 887: @34191
12191 /* 34191 */ GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(34469),
12192 /* 34196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12193 /* 34200 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12194 /* 34204 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 897*/ GIMT_Encode4(34224), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5844 //
12195 /* 34211 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8f16] }:$src
12196 /* 34211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12197 /* 34214 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12198 /* 34216 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12199 /* 34218 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12200 /* 34223 */ // GIR_Coverage, 5844,
12201 /* 34223 */ GIR_EraseRootFromParent_Done,
12202 /* 34224 */ // Label 897: @34224
12203 /* 34224 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 898*/ GIMT_Encode4(34244), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5845 //
12204 /* 34231 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8f16] }:$src
12205 /* 34231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12206 /* 34234 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12207 /* 34236 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12208 /* 34238 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12209 /* 34243 */ // GIR_Coverage, 5845,
12210 /* 34243 */ GIR_EraseRootFromParent_Done,
12211 /* 34244 */ // Label 898: @34244
12212 /* 34244 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 899*/ GIMT_Encode4(34264), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5849 //
12213 /* 34251 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8i16] }:$src
12214 /* 34251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12215 /* 34254 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12216 /* 34256 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12217 /* 34258 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12218 /* 34263 */ // GIR_Coverage, 5849,
12219 /* 34263 */ GIR_EraseRootFromParent_Done,
12220 /* 34264 */ // Label 899: @34264
12221 /* 34264 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 900*/ GIMT_Encode4(34284), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5850 //
12222 /* 34271 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8i16] }:$src
12223 /* 34271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12224 /* 34274 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12225 /* 34276 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12226 /* 34278 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12227 /* 34283 */ // GIR_Coverage, 5850,
12228 /* 34283 */ GIR_EraseRootFromParent_Done,
12229 /* 34284 */ // Label 900: @34284
12230 /* 34284 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 901*/ GIMT_Encode4(34330), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5880 //
12231 /* 34291 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src)
12232 /* 34291 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12233 /* 34294 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12234 /* 34298 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12235 /* 34303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12236 /* 34306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12237 /* 34308 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12238 /* 34310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12239 /* 34313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12240 /* 34319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12241 /* 34325 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12242 /* 34328 */ GIR_RootConstrainSelectedInstOperands,
12243 /* 34329 */ // GIR_Coverage, 5880,
12244 /* 34329 */ GIR_EraseRootFromParent_Done,
12245 /* 34330 */ // Label 901: @34330
12246 /* 34330 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 902*/ GIMT_Encode4(34376), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5881 //
12247 /* 34337 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src)
12248 /* 34337 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12249 /* 34340 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12250 /* 34344 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12251 /* 34349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12252 /* 34352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12253 /* 34354 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12254 /* 34356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12255 /* 34359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12256 /* 34365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12257 /* 34371 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12258 /* 34374 */ GIR_RootConstrainSelectedInstOperands,
12259 /* 34375 */ // GIR_Coverage, 5881,
12260 /* 34375 */ GIR_EraseRootFromParent_Done,
12261 /* 34376 */ // Label 902: @34376
12262 /* 34376 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 903*/ GIMT_Encode4(34422), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5885 //
12263 /* 34383 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src)
12264 /* 34383 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12265 /* 34386 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12266 /* 34390 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12267 /* 34395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12268 /* 34398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12269 /* 34400 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12270 /* 34402 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12271 /* 34405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12272 /* 34411 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12273 /* 34417 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12274 /* 34420 */ GIR_RootConstrainSelectedInstOperands,
12275 /* 34421 */ // GIR_Coverage, 5885,
12276 /* 34421 */ GIR_EraseRootFromParent_Done,
12277 /* 34422 */ // Label 903: @34422
12278 /* 34422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 904*/ GIMT_Encode4(34468), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5886 //
12279 /* 34429 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src)
12280 /* 34429 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12281 /* 34432 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12282 /* 34436 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12283 /* 34441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12284 /* 34444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12285 /* 34446 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12286 /* 34448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12287 /* 34451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12288 /* 34457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12289 /* 34463 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12290 /* 34466 */ GIR_RootConstrainSelectedInstOperands,
12291 /* 34467 */ // GIR_Coverage, 5886,
12292 /* 34467 */ GIR_EraseRootFromParent_Done,
12293 /* 34468 */ // Label 904: @34468
12294 /* 34468 */ GIM_Reject,
12295 /* 34469 */ // Label 896: @34469
12296 /* 34469 */ GIM_Reject,
12297 /* 34470 */ // Label 852: @34470
12298 /* 34470 */ GIM_Reject,
12299 /* 34471 */ // Label 724: @34471
12300 /* 34471 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(2), GIMT_Encode2(12), /*)*//*default:*//*Label 909*/ GIMT_Encode4(35072),
12301 /* 34482 */ /*GILLT_s64*//*Label 905*/ GIMT_Encode4(34522), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
12302 /* 34502 */ /*GILLT_v8s8*//*Label 906*/ GIMT_Encode4(34717), GIMT_Encode4(0),
12303 /* 34510 */ /*GILLT_v4s16*//*Label 907*/ GIMT_Encode4(34822), GIMT_Encode4(0),
12304 /* 34518 */ /*GILLT_v2s32*//*Label 908*/ GIMT_Encode4(35017),
12305 /* 34522 */ // Label 905: @34522
12306 /* 34522 */ GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(34716),
12307 /* 34527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12308 /* 34531 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12309 /* 34535 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 911*/ GIMT_Encode4(34555), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3131 //
12310 /* 34542 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2f32] }:$src
12311 /* 34542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12312 /* 34545 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12313 /* 34547 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12314 /* 34549 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12315 /* 34554 */ // GIR_Coverage, 3131,
12316 /* 34554 */ GIR_EraseRootFromParent_Done,
12317 /* 34555 */ // Label 911: @34555
12318 /* 34555 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 912*/ GIMT_Encode4(34575), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3132 //
12319 /* 34562 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2f32] }:$src
12320 /* 34562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12321 /* 34565 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12322 /* 34567 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12323 /* 34569 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12324 /* 34574 */ // GIR_Coverage, 3132,
12325 /* 34574 */ GIR_EraseRootFromParent_Done,
12326 /* 34575 */ // Label 912: @34575
12327 /* 34575 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 913*/ GIMT_Encode4(34595), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3136 //
12328 /* 34582 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2i32] }:$src
12329 /* 34582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12330 /* 34585 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12331 /* 34587 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12332 /* 34589 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12333 /* 34594 */ // GIR_Coverage, 3136,
12334 /* 34594 */ GIR_EraseRootFromParent_Done,
12335 /* 34595 */ // Label 913: @34595
12336 /* 34595 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 914*/ GIMT_Encode4(34615), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3137 //
12337 /* 34602 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2i32] }:$src
12338 /* 34602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12339 /* 34605 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12340 /* 34607 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12341 /* 34609 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12342 /* 34614 */ // GIR_Coverage, 3137,
12343 /* 34614 */ GIR_EraseRootFromParent_Done,
12344 /* 34615 */ // Label 914: @34615
12345 /* 34615 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 915*/ GIMT_Encode4(34640), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3203 //
12346 /* 34622 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src)
12347 /* 34622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
12348 /* 34625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12349 /* 34627 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12350 /* 34629 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12351 /* 34632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12352 /* 34638 */ GIR_RootConstrainSelectedInstOperands,
12353 /* 34639 */ // GIR_Coverage, 3203,
12354 /* 34639 */ GIR_EraseRootFromParent_Done,
12355 /* 34640 */ // Label 915: @34640
12356 /* 34640 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 916*/ GIMT_Encode4(34665), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3204 //
12357 /* 34647 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)
12358 /* 34647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
12359 /* 34650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12360 /* 34652 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12361 /* 34654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12362 /* 34657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12363 /* 34663 */ GIR_RootConstrainSelectedInstOperands,
12364 /* 34664 */ // GIR_Coverage, 3204,
12365 /* 34664 */ GIR_EraseRootFromParent_Done,
12366 /* 34665 */ // Label 916: @34665
12367 /* 34665 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 917*/ GIMT_Encode4(34690), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3208 //
12368 /* 34672 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src)
12369 /* 34672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
12370 /* 34675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12371 /* 34677 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12372 /* 34679 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12373 /* 34682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12374 /* 34688 */ GIR_RootConstrainSelectedInstOperands,
12375 /* 34689 */ // GIR_Coverage, 3208,
12376 /* 34689 */ GIR_EraseRootFromParent_Done,
12377 /* 34690 */ // Label 917: @34690
12378 /* 34690 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 918*/ GIMT_Encode4(34715), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3209 //
12379 /* 34697 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)
12380 /* 34697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
12381 /* 34700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12382 /* 34702 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12383 /* 34704 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12384 /* 34707 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12385 /* 34713 */ GIR_RootConstrainSelectedInstOperands,
12386 /* 34714 */ // GIR_Coverage, 3209,
12387 /* 34714 */ GIR_EraseRootFromParent_Done,
12388 /* 34715 */ // Label 918: @34715
12389 /* 34715 */ GIM_Reject,
12390 /* 34716 */ // Label 910: @34716
12391 /* 34716 */ GIM_Reject,
12392 /* 34717 */ // Label 906: @34717
12393 /* 34717 */ GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(34821),
12394 /* 34722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12395 /* 34726 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12396 /* 34730 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 920*/ GIMT_Encode4(34750), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3135 //
12397 /* 34737 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2f32] }:$src
12398 /* 34737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12399 /* 34740 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12400 /* 34742 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12401 /* 34744 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12402 /* 34749 */ // GIR_Coverage, 3135,
12403 /* 34749 */ GIR_EraseRootFromParent_Done,
12404 /* 34750 */ // Label 920: @34750
12405 /* 34750 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 921*/ GIMT_Encode4(34770), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3140 //
12406 /* 34757 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2i32] }:$src
12407 /* 34757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12408 /* 34760 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12409 /* 34762 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12410 /* 34764 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12411 /* 34769 */ // GIR_Coverage, 3140,
12412 /* 34769 */ GIR_EraseRootFromParent_Done,
12413 /* 34770 */ // Label 921: @34770
12414 /* 34770 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 922*/ GIMT_Encode4(34795), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3207 //
12415 /* 34777 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)
12416 /* 34777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
12417 /* 34780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12418 /* 34782 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12419 /* 34784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12420 /* 34787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12421 /* 34793 */ GIR_RootConstrainSelectedInstOperands,
12422 /* 34794 */ // GIR_Coverage, 3207,
12423 /* 34794 */ GIR_EraseRootFromParent_Done,
12424 /* 34795 */ // Label 922: @34795
12425 /* 34795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 923*/ GIMT_Encode4(34820), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3212 //
12426 /* 34802 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)
12427 /* 34802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
12428 /* 34805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12429 /* 34807 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12430 /* 34809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12431 /* 34812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12432 /* 34818 */ GIR_RootConstrainSelectedInstOperands,
12433 /* 34819 */ // GIR_Coverage, 3212,
12434 /* 34819 */ GIR_EraseRootFromParent_Done,
12435 /* 34820 */ // Label 923: @34820
12436 /* 34820 */ GIM_Reject,
12437 /* 34821 */ // Label 919: @34821
12438 /* 34821 */ GIM_Reject,
12439 /* 34822 */ // Label 907: @34822
12440 /* 34822 */ GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(35016),
12441 /* 34827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12442 /* 34831 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12443 /* 34835 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 925*/ GIMT_Encode4(34855), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3133 //
12444 /* 34842 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2f32] }:$src
12445 /* 34842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12446 /* 34845 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12447 /* 34847 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12448 /* 34849 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12449 /* 34854 */ // GIR_Coverage, 3133,
12450 /* 34854 */ GIR_EraseRootFromParent_Done,
12451 /* 34855 */ // Label 925: @34855
12452 /* 34855 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 926*/ GIMT_Encode4(34875), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3134 //
12453 /* 34862 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2f32] }:$src
12454 /* 34862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12455 /* 34865 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12456 /* 34867 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12457 /* 34869 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12458 /* 34874 */ // GIR_Coverage, 3134,
12459 /* 34874 */ GIR_EraseRootFromParent_Done,
12460 /* 34875 */ // Label 926: @34875
12461 /* 34875 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 927*/ GIMT_Encode4(34895), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3138 //
12462 /* 34882 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2i32] }:$src
12463 /* 34882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12464 /* 34885 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12465 /* 34887 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12466 /* 34889 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12467 /* 34894 */ // GIR_Coverage, 3138,
12468 /* 34894 */ GIR_EraseRootFromParent_Done,
12469 /* 34895 */ // Label 927: @34895
12470 /* 34895 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 928*/ GIMT_Encode4(34915), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3139 //
12471 /* 34902 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2i32] }:$src
12472 /* 34902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12473 /* 34905 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12474 /* 34907 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12475 /* 34909 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12476 /* 34914 */ // GIR_Coverage, 3139,
12477 /* 34914 */ GIR_EraseRootFromParent_Done,
12478 /* 34915 */ // Label 928: @34915
12479 /* 34915 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 929*/ GIMT_Encode4(34940), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3205 //
12480 /* 34922 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src)
12481 /* 34922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12482 /* 34925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12483 /* 34927 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12484 /* 34929 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12485 /* 34932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12486 /* 34938 */ GIR_RootConstrainSelectedInstOperands,
12487 /* 34939 */ // GIR_Coverage, 3205,
12488 /* 34939 */ GIR_EraseRootFromParent_Done,
12489 /* 34940 */ // Label 929: @34940
12490 /* 34940 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 930*/ GIMT_Encode4(34965), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3206 //
12491 /* 34947 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)
12492 /* 34947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12493 /* 34950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12494 /* 34952 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12495 /* 34954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12496 /* 34957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12497 /* 34963 */ GIR_RootConstrainSelectedInstOperands,
12498 /* 34964 */ // GIR_Coverage, 3206,
12499 /* 34964 */ GIR_EraseRootFromParent_Done,
12500 /* 34965 */ // Label 930: @34965
12501 /* 34965 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 931*/ GIMT_Encode4(34990), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3210 //
12502 /* 34972 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src)
12503 /* 34972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12504 /* 34975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12505 /* 34977 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12506 /* 34979 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12507 /* 34982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12508 /* 34988 */ GIR_RootConstrainSelectedInstOperands,
12509 /* 34989 */ // GIR_Coverage, 3210,
12510 /* 34989 */ GIR_EraseRootFromParent_Done,
12511 /* 34990 */ // Label 931: @34990
12512 /* 34990 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 932*/ GIMT_Encode4(35015), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3211 //
12513 /* 34997 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)
12514 /* 34997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12515 /* 35000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12516 /* 35002 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12517 /* 35004 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12518 /* 35007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12519 /* 35013 */ GIR_RootConstrainSelectedInstOperands,
12520 /* 35014 */ // GIR_Coverage, 3211,
12521 /* 35014 */ GIR_EraseRootFromParent_Done,
12522 /* 35015 */ // Label 932: @35015
12523 /* 35015 */ GIM_Reject,
12524 /* 35016 */ // Label 924: @35016
12525 /* 35016 */ GIM_Reject,
12526 /* 35017 */ // Label 908: @35017
12527 /* 35017 */ GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(35071),
12528 /* 35022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12529 /* 35026 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12530 /* 35030 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 934*/ GIMT_Encode4(35050), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3111 //
12531 /* 35037 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v2f32] }:$src
12532 /* 35037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12533 /* 35040 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12534 /* 35042 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12535 /* 35044 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12536 /* 35049 */ // GIR_Coverage, 3111,
12537 /* 35049 */ GIR_EraseRootFromParent_Done,
12538 /* 35050 */ // Label 934: @35050
12539 /* 35050 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 935*/ GIMT_Encode4(35070), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3112 //
12540 /* 35057 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v2i32] }:$src
12541 /* 35057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12542 /* 35060 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12543 /* 35062 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12544 /* 35064 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12545 /* 35069 */ // GIR_Coverage, 3112,
12546 /* 35069 */ GIR_EraseRootFromParent_Done,
12547 /* 35070 */ // Label 935: @35070
12548 /* 35070 */ GIM_Reject,
12549 /* 35071 */ // Label 933: @35071
12550 /* 35071 */ GIM_Reject,
12551 /* 35072 */ // Label 909: @35072
12552 /* 35072 */ GIM_Reject,
12553 /* 35073 */ // Label 725: @35073
12554 /* 35073 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 940*/ GIMT_Encode4(36414),
12555 /* 35084 */ /*GILLT_v16s8*//*Label 936*/ GIMT_Encode4(35108), GIMT_Encode4(0),
12556 /* 35092 */ /*GILLT_v8s16*//*Label 937*/ GIMT_Encode4(35359), GIMT_Encode4(0),
12557 /* 35100 */ /*GILLT_v4s32*//*Label 938*/ GIMT_Encode4(35832),
12558 /* 35104 */ /*GILLT_v2s64*//*Label 939*/ GIMT_Encode4(35941),
12559 /* 35108 */ // Label 936: @35108
12560 /* 35108 */ GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(35212),
12561 /* 35113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12562 /* 35117 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12563 /* 35121 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 942*/ GIMT_Encode4(35141), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3171 //
12564 /* 35128 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4f32] }:$src
12565 /* 35128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12566 /* 35131 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12567 /* 35133 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12568 /* 35135 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12569 /* 35140 */ // GIR_Coverage, 3171,
12570 /* 35140 */ GIR_EraseRootFromParent_Done,
12571 /* 35141 */ // Label 942: @35141
12572 /* 35141 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 943*/ GIMT_Encode4(35161), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3176 //
12573 /* 35148 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4i32] }:$src
12574 /* 35148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12575 /* 35151 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12576 /* 35153 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12577 /* 35155 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12578 /* 35160 */ // GIR_Coverage, 3176,
12579 /* 35160 */ GIR_EraseRootFromParent_Done,
12580 /* 35161 */ // Label 943: @35161
12581 /* 35161 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 944*/ GIMT_Encode4(35186), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3243 //
12582 /* 35168 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)
12583 /* 35168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
12584 /* 35171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12585 /* 35173 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12586 /* 35175 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12587 /* 35178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12588 /* 35184 */ GIR_RootConstrainSelectedInstOperands,
12589 /* 35185 */ // GIR_Coverage, 3243,
12590 /* 35185 */ GIR_EraseRootFromParent_Done,
12591 /* 35186 */ // Label 944: @35186
12592 /* 35186 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 945*/ GIMT_Encode4(35211), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3248 //
12593 /* 35193 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)
12594 /* 35193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
12595 /* 35196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12596 /* 35198 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12597 /* 35200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12598 /* 35203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12599 /* 35209 */ GIR_RootConstrainSelectedInstOperands,
12600 /* 35210 */ // GIR_Coverage, 3248,
12601 /* 35210 */ GIR_EraseRootFromParent_Done,
12602 /* 35211 */ // Label 945: @35211
12603 /* 35211 */ GIM_Reject,
12604 /* 35212 */ // Label 941: @35212
12605 /* 35212 */ GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(35358),
12606 /* 35217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12607 /* 35221 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12608 /* 35225 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 947*/ GIMT_Encode4(35245), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5838 //
12609 /* 35232 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4f32] }:$src
12610 /* 35232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12611 /* 35235 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12612 /* 35237 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12613 /* 35239 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12614 /* 35244 */ // GIR_Coverage, 5838,
12615 /* 35244 */ GIR_EraseRootFromParent_Done,
12616 /* 35245 */ // Label 947: @35245
12617 /* 35245 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 948*/ GIMT_Encode4(35265), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5843 //
12618 /* 35252 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4i32] }:$src
12619 /* 35252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12620 /* 35255 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12621 /* 35257 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12622 /* 35259 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12623 /* 35264 */ // GIR_Coverage, 5843,
12624 /* 35264 */ GIR_EraseRootFromParent_Done,
12625 /* 35265 */ // Label 948: @35265
12626 /* 35265 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 949*/ GIMT_Encode4(35311), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5874 //
12627 /* 35272 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src)
12628 /* 35272 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12629 /* 35275 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12630 /* 35279 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12631 /* 35284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
12632 /* 35287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12633 /* 35289 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12634 /* 35291 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12635 /* 35294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12636 /* 35300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12637 /* 35306 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12638 /* 35309 */ GIR_RootConstrainSelectedInstOperands,
12639 /* 35310 */ // GIR_Coverage, 5874,
12640 /* 35310 */ GIR_EraseRootFromParent_Done,
12641 /* 35311 */ // Label 949: @35311
12642 /* 35311 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 950*/ GIMT_Encode4(35357), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5879 //
12643 /* 35318 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src)
12644 /* 35318 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12645 /* 35321 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12646 /* 35325 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12647 /* 35330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
12648 /* 35333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12649 /* 35335 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12650 /* 35337 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12651 /* 35340 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12652 /* 35346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12653 /* 35352 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12654 /* 35355 */ GIR_RootConstrainSelectedInstOperands,
12655 /* 35356 */ // GIR_Coverage, 5879,
12656 /* 35356 */ GIR_EraseRootFromParent_Done,
12657 /* 35357 */ // Label 950: @35357
12658 /* 35357 */ GIM_Reject,
12659 /* 35358 */ // Label 946: @35358
12660 /* 35358 */ GIM_Reject,
12661 /* 35359 */ // Label 937: @35359
12662 /* 35359 */ GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(35553),
12663 /* 35364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12664 /* 35368 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12665 /* 35372 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 952*/ GIMT_Encode4(35392), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3169 //
12666 /* 35379 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4f32] }:$src
12667 /* 35379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12668 /* 35382 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12669 /* 35384 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12670 /* 35386 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12671 /* 35391 */ // GIR_Coverage, 3169,
12672 /* 35391 */ GIR_EraseRootFromParent_Done,
12673 /* 35392 */ // Label 952: @35392
12674 /* 35392 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 953*/ GIMT_Encode4(35412), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3170 //
12675 /* 35399 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4f32] }:$src
12676 /* 35399 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12677 /* 35402 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12678 /* 35404 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12679 /* 35406 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12680 /* 35411 */ // GIR_Coverage, 3170,
12681 /* 35411 */ GIR_EraseRootFromParent_Done,
12682 /* 35412 */ // Label 953: @35412
12683 /* 35412 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 954*/ GIMT_Encode4(35432), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3174 //
12684 /* 35419 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4i32] }:$src
12685 /* 35419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12686 /* 35422 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12687 /* 35424 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12688 /* 35426 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12689 /* 35431 */ // GIR_Coverage, 3174,
12690 /* 35431 */ GIR_EraseRootFromParent_Done,
12691 /* 35432 */ // Label 954: @35432
12692 /* 35432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 955*/ GIMT_Encode4(35452), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3175 //
12693 /* 35439 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4i32] }:$src
12694 /* 35439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12695 /* 35442 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12696 /* 35444 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12697 /* 35446 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12698 /* 35451 */ // GIR_Coverage, 3175,
12699 /* 35451 */ GIR_EraseRootFromParent_Done,
12700 /* 35452 */ // Label 955: @35452
12701 /* 35452 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 956*/ GIMT_Encode4(35477), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3241 //
12702 /* 35459 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)
12703 /* 35459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12704 /* 35462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12705 /* 35464 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12706 /* 35466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12707 /* 35469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12708 /* 35475 */ GIR_RootConstrainSelectedInstOperands,
12709 /* 35476 */ // GIR_Coverage, 3241,
12710 /* 35476 */ GIR_EraseRootFromParent_Done,
12711 /* 35477 */ // Label 956: @35477
12712 /* 35477 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 957*/ GIMT_Encode4(35502), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3242 //
12713 /* 35484 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)
12714 /* 35484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12715 /* 35487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12716 /* 35489 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12717 /* 35491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12718 /* 35494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12719 /* 35500 */ GIR_RootConstrainSelectedInstOperands,
12720 /* 35501 */ // GIR_Coverage, 3242,
12721 /* 35501 */ GIR_EraseRootFromParent_Done,
12722 /* 35502 */ // Label 957: @35502
12723 /* 35502 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 958*/ GIMT_Encode4(35527), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3246 //
12724 /* 35509 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src)
12725 /* 35509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12726 /* 35512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12727 /* 35514 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12728 /* 35516 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12729 /* 35519 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12730 /* 35525 */ GIR_RootConstrainSelectedInstOperands,
12731 /* 35526 */ // GIR_Coverage, 3246,
12732 /* 35526 */ GIR_EraseRootFromParent_Done,
12733 /* 35527 */ // Label 958: @35527
12734 /* 35527 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 959*/ GIMT_Encode4(35552), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3247 //
12735 /* 35534 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)
12736 /* 35534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12737 /* 35537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12738 /* 35539 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12739 /* 35541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12740 /* 35544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12741 /* 35550 */ GIR_RootConstrainSelectedInstOperands,
12742 /* 35551 */ // GIR_Coverage, 3247,
12743 /* 35551 */ GIR_EraseRootFromParent_Done,
12744 /* 35552 */ // Label 959: @35552
12745 /* 35552 */ GIM_Reject,
12746 /* 35553 */ // Label 951: @35553
12747 /* 35553 */ GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(35831),
12748 /* 35558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12749 /* 35562 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12750 /* 35566 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 961*/ GIMT_Encode4(35586), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5836 //
12751 /* 35573 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4f32] }:$src
12752 /* 35573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12753 /* 35576 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12754 /* 35578 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12755 /* 35580 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12756 /* 35585 */ // GIR_Coverage, 5836,
12757 /* 35585 */ GIR_EraseRootFromParent_Done,
12758 /* 35586 */ // Label 961: @35586
12759 /* 35586 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 962*/ GIMT_Encode4(35606), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5837 //
12760 /* 35593 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4f32] }:$src
12761 /* 35593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12762 /* 35596 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12763 /* 35598 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12764 /* 35600 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12765 /* 35605 */ // GIR_Coverage, 5837,
12766 /* 35605 */ GIR_EraseRootFromParent_Done,
12767 /* 35606 */ // Label 962: @35606
12768 /* 35606 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 963*/ GIMT_Encode4(35626), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5841 //
12769 /* 35613 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4i32] }:$src
12770 /* 35613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12771 /* 35616 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12772 /* 35618 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12773 /* 35620 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12774 /* 35625 */ // GIR_Coverage, 5841,
12775 /* 35625 */ GIR_EraseRootFromParent_Done,
12776 /* 35626 */ // Label 963: @35626
12777 /* 35626 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 964*/ GIMT_Encode4(35646), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5842 //
12778 /* 35633 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4i32] }:$src
12779 /* 35633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12780 /* 35636 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12781 /* 35638 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12782 /* 35640 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12783 /* 35645 */ // GIR_Coverage, 5842,
12784 /* 35645 */ GIR_EraseRootFromParent_Done,
12785 /* 35646 */ // Label 964: @35646
12786 /* 35646 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 965*/ GIMT_Encode4(35692), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5872 //
12787 /* 35653 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src)
12788 /* 35653 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12789 /* 35656 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12790 /* 35660 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12791 /* 35665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12792 /* 35668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12793 /* 35670 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12794 /* 35672 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12795 /* 35675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12796 /* 35681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12797 /* 35687 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12798 /* 35690 */ GIR_RootConstrainSelectedInstOperands,
12799 /* 35691 */ // GIR_Coverage, 5872,
12800 /* 35691 */ GIR_EraseRootFromParent_Done,
12801 /* 35692 */ // Label 965: @35692
12802 /* 35692 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 966*/ GIMT_Encode4(35738), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5873 //
12803 /* 35699 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src)
12804 /* 35699 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12805 /* 35702 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12806 /* 35706 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12807 /* 35711 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12808 /* 35714 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12809 /* 35716 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12810 /* 35718 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12811 /* 35721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12812 /* 35727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12813 /* 35733 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12814 /* 35736 */ GIR_RootConstrainSelectedInstOperands,
12815 /* 35737 */ // GIR_Coverage, 5873,
12816 /* 35737 */ GIR_EraseRootFromParent_Done,
12817 /* 35738 */ // Label 966: @35738
12818 /* 35738 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 967*/ GIMT_Encode4(35784), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5877 //
12819 /* 35745 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src)
12820 /* 35745 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12821 /* 35748 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12822 /* 35752 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12823 /* 35757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12824 /* 35760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12825 /* 35762 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12826 /* 35764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12827 /* 35767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12828 /* 35773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12829 /* 35779 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12830 /* 35782 */ GIR_RootConstrainSelectedInstOperands,
12831 /* 35783 */ // GIR_Coverage, 5877,
12832 /* 35783 */ GIR_EraseRootFromParent_Done,
12833 /* 35784 */ // Label 967: @35784
12834 /* 35784 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 968*/ GIMT_Encode4(35830), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5878 //
12835 /* 35791 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
12836 /* 35791 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12837 /* 35794 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12838 /* 35798 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12839 /* 35803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
12840 /* 35806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12841 /* 35808 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12842 /* 35810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12843 /* 35813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12844 /* 35819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12845 /* 35825 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12846 /* 35828 */ GIR_RootConstrainSelectedInstOperands,
12847 /* 35829 */ // GIR_Coverage, 5878,
12848 /* 35829 */ GIR_EraseRootFromParent_Done,
12849 /* 35830 */ // Label 968: @35830
12850 /* 35830 */ GIM_Reject,
12851 /* 35831 */ // Label 960: @35831
12852 /* 35831 */ GIM_Reject,
12853 /* 35832 */ // Label 938: @35832
12854 /* 35832 */ GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(35886),
12855 /* 35837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12856 /* 35841 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12857 /* 35845 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 970*/ GIMT_Encode4(35865), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3117 //
12858 /* 35852 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v4i32] }:$src
12859 /* 35852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12860 /* 35855 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12861 /* 35857 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12862 /* 35859 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12863 /* 35864 */ // GIR_Coverage, 3117,
12864 /* 35864 */ GIR_EraseRootFromParent_Done,
12865 /* 35865 */ // Label 970: @35865
12866 /* 35865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 971*/ GIMT_Encode4(35885), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3118 //
12867 /* 35872 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v4f32] }:$src
12868 /* 35872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12869 /* 35875 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12870 /* 35877 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12871 /* 35879 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12872 /* 35884 */ // GIR_Coverage, 3118,
12873 /* 35884 */ GIR_EraseRootFromParent_Done,
12874 /* 35885 */ // Label 971: @35885
12875 /* 35885 */ GIM_Reject,
12876 /* 35886 */ // Label 969: @35886
12877 /* 35886 */ GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(35940),
12878 /* 35891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12879 /* 35895 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12880 /* 35899 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 973*/ GIMT_Encode4(35919), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5820 //
12881 /* 35906 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v4i32] }:$src
12882 /* 35906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12883 /* 35909 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12884 /* 35911 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12885 /* 35913 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12886 /* 35918 */ // GIR_Coverage, 5820,
12887 /* 35918 */ GIR_EraseRootFromParent_Done,
12888 /* 35919 */ // Label 973: @35919
12889 /* 35919 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 974*/ GIMT_Encode4(35939), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5821 //
12890 /* 35926 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v4f32] }:$src
12891 /* 35926 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12892 /* 35929 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12893 /* 35931 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12894 /* 35933 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12895 /* 35938 */ // GIR_Coverage, 5821,
12896 /* 35938 */ GIR_EraseRootFromParent_Done,
12897 /* 35939 */ // Label 974: @35939
12898 /* 35939 */ GIM_Reject,
12899 /* 35940 */ // Label 972: @35940
12900 /* 35940 */ GIM_Reject,
12901 /* 35941 */ // Label 939: @35941
12902 /* 35941 */ GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(36135),
12903 /* 35946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12904 /* 35950 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12905 /* 35954 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 976*/ GIMT_Encode4(35974), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3167 //
12906 /* 35961 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4f32] }:$src
12907 /* 35961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12908 /* 35964 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12909 /* 35966 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12910 /* 35968 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12911 /* 35973 */ // GIR_Coverage, 3167,
12912 /* 35973 */ GIR_EraseRootFromParent_Done,
12913 /* 35974 */ // Label 976: @35974
12914 /* 35974 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 977*/ GIMT_Encode4(35994), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3168 //
12915 /* 35981 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4f32] }:$src
12916 /* 35981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12917 /* 35984 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12918 /* 35986 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12919 /* 35988 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12920 /* 35993 */ // GIR_Coverage, 3168,
12921 /* 35993 */ GIR_EraseRootFromParent_Done,
12922 /* 35994 */ // Label 977: @35994
12923 /* 35994 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 978*/ GIMT_Encode4(36014), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3172 //
12924 /* 36001 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4i32] }:$src
12925 /* 36001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12926 /* 36004 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12927 /* 36006 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12928 /* 36008 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12929 /* 36013 */ // GIR_Coverage, 3172,
12930 /* 36013 */ GIR_EraseRootFromParent_Done,
12931 /* 36014 */ // Label 978: @36014
12932 /* 36014 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 979*/ GIMT_Encode4(36034), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3173 //
12933 /* 36021 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4i32] }:$src
12934 /* 36021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12935 /* 36024 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12936 /* 36026 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12937 /* 36028 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12938 /* 36033 */ // GIR_Coverage, 3173,
12939 /* 36033 */ GIR_EraseRootFromParent_Done,
12940 /* 36034 */ // Label 979: @36034
12941 /* 36034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 980*/ GIMT_Encode4(36059), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3239 //
12942 /* 36041 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)
12943 /* 36041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
12944 /* 36044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12945 /* 36046 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12946 /* 36048 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12947 /* 36051 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12948 /* 36057 */ GIR_RootConstrainSelectedInstOperands,
12949 /* 36058 */ // GIR_Coverage, 3239,
12950 /* 36058 */ GIR_EraseRootFromParent_Done,
12951 /* 36059 */ // Label 980: @36059
12952 /* 36059 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 981*/ GIMT_Encode4(36084), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3240 //
12953 /* 36066 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)
12954 /* 36066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
12955 /* 36069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12956 /* 36071 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12957 /* 36073 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12958 /* 36076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12959 /* 36082 */ GIR_RootConstrainSelectedInstOperands,
12960 /* 36083 */ // GIR_Coverage, 3240,
12961 /* 36083 */ GIR_EraseRootFromParent_Done,
12962 /* 36084 */ // Label 981: @36084
12963 /* 36084 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 982*/ GIMT_Encode4(36109), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3244 //
12964 /* 36091 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)
12965 /* 36091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
12966 /* 36094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12967 /* 36096 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12968 /* 36098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12969 /* 36101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12970 /* 36107 */ GIR_RootConstrainSelectedInstOperands,
12971 /* 36108 */ // GIR_Coverage, 3244,
12972 /* 36108 */ GIR_EraseRootFromParent_Done,
12973 /* 36109 */ // Label 982: @36109
12974 /* 36109 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 983*/ GIMT_Encode4(36134), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3245 //
12975 /* 36116 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)
12976 /* 36116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
12977 /* 36119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12978 /* 36121 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12979 /* 36123 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12980 /* 36126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12981 /* 36132 */ GIR_RootConstrainSelectedInstOperands,
12982 /* 36133 */ // GIR_Coverage, 3245,
12983 /* 36133 */ GIR_EraseRootFromParent_Done,
12984 /* 36134 */ // Label 983: @36134
12985 /* 36134 */ GIM_Reject,
12986 /* 36135 */ // Label 975: @36135
12987 /* 36135 */ GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(36413),
12988 /* 36140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12989 /* 36144 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12990 /* 36148 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 985*/ GIMT_Encode4(36168), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5834 //
12991 /* 36155 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4f32] }:$src
12992 /* 36155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12993 /* 36158 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12994 /* 36160 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12995 /* 36162 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12996 /* 36167 */ // GIR_Coverage, 5834,
12997 /* 36167 */ GIR_EraseRootFromParent_Done,
12998 /* 36168 */ // Label 985: @36168
12999 /* 36168 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 986*/ GIMT_Encode4(36188), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5835 //
13000 /* 36175 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4f32] }:$src
13001 /* 36175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13002 /* 36178 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13003 /* 36180 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13004 /* 36182 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13005 /* 36187 */ // GIR_Coverage, 5835,
13006 /* 36187 */ GIR_EraseRootFromParent_Done,
13007 /* 36188 */ // Label 986: @36188
13008 /* 36188 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 987*/ GIMT_Encode4(36208), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5839 //
13009 /* 36195 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4i32] }:$src
13010 /* 36195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13011 /* 36198 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13012 /* 36200 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13013 /* 36202 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13014 /* 36207 */ // GIR_Coverage, 5839,
13015 /* 36207 */ GIR_EraseRootFromParent_Done,
13016 /* 36208 */ // Label 987: @36208
13017 /* 36208 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 988*/ GIMT_Encode4(36228), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5840 //
13018 /* 36215 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4i32] }:$src
13019 /* 36215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13020 /* 36218 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13021 /* 36220 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13022 /* 36222 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13023 /* 36227 */ // GIR_Coverage, 5840,
13024 /* 36227 */ GIR_EraseRootFromParent_Done,
13025 /* 36228 */ // Label 988: @36228
13026 /* 36228 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 989*/ GIMT_Encode4(36274), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5870 //
13027 /* 36235 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src)
13028 /* 36235 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13029 /* 36238 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13030 /* 36242 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13031 /* 36247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13032 /* 36250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13033 /* 36252 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13034 /* 36254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13035 /* 36257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13036 /* 36263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13037 /* 36269 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13038 /* 36272 */ GIR_RootConstrainSelectedInstOperands,
13039 /* 36273 */ // GIR_Coverage, 5870,
13040 /* 36273 */ GIR_EraseRootFromParent_Done,
13041 /* 36274 */ // Label 989: @36274
13042 /* 36274 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 990*/ GIMT_Encode4(36320), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5871 //
13043 /* 36281 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src)
13044 /* 36281 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13045 /* 36284 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13046 /* 36288 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13047 /* 36293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13048 /* 36296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13049 /* 36298 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13050 /* 36300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13051 /* 36303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13052 /* 36309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13053 /* 36315 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13054 /* 36318 */ GIR_RootConstrainSelectedInstOperands,
13055 /* 36319 */ // GIR_Coverage, 5871,
13056 /* 36319 */ GIR_EraseRootFromParent_Done,
13057 /* 36320 */ // Label 990: @36320
13058 /* 36320 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 991*/ GIMT_Encode4(36366), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5875 //
13059 /* 36327 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src)
13060 /* 36327 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13061 /* 36330 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13062 /* 36334 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13063 /* 36339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13064 /* 36342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13065 /* 36344 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13066 /* 36346 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13067 /* 36349 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13068 /* 36355 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13069 /* 36361 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13070 /* 36364 */ GIR_RootConstrainSelectedInstOperands,
13071 /* 36365 */ // GIR_Coverage, 5875,
13072 /* 36365 */ GIR_EraseRootFromParent_Done,
13073 /* 36366 */ // Label 991: @36366
13074 /* 36366 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 992*/ GIMT_Encode4(36412), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5876 //
13075 /* 36373 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src)
13076 /* 36373 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13077 /* 36376 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13078 /* 36380 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13079 /* 36385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13080 /* 36388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13081 /* 36390 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13082 /* 36392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13083 /* 36395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13084 /* 36401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13085 /* 36407 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13086 /* 36410 */ GIR_RootConstrainSelectedInstOperands,
13087 /* 36411 */ // GIR_Coverage, 5876,
13088 /* 36411 */ GIR_EraseRootFromParent_Done,
13089 /* 36412 */ // Label 992: @36412
13090 /* 36412 */ GIM_Reject,
13091 /* 36413 */ // Label 984: @36413
13092 /* 36413 */ GIM_Reject,
13093 /* 36414 */ // Label 940: @36414
13094 /* 36414 */ GIM_Reject,
13095 /* 36415 */ // Label 726: @36415
13096 /* 36415 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 997*/ GIMT_Encode4(37756),
13097 /* 36426 */ /*GILLT_v16s8*//*Label 993*/ GIMT_Encode4(36450), GIMT_Encode4(0),
13098 /* 36434 */ /*GILLT_v8s16*//*Label 994*/ GIMT_Encode4(36701), GIMT_Encode4(0),
13099 /* 36442 */ /*GILLT_v4s32*//*Label 995*/ GIMT_Encode4(37174),
13100 /* 36446 */ /*GILLT_v2s64*//*Label 996*/ GIMT_Encode4(37647),
13101 /* 36450 */ // Label 993: @36450
13102 /* 36450 */ GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(36554),
13103 /* 36455 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13104 /* 36459 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13105 /* 36463 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 999*/ GIMT_Encode4(36483), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3161 //
13106 /* 36470 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2f64] }:$src
13107 /* 36470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13108 /* 36473 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13109 /* 36475 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13110 /* 36477 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13111 /* 36482 */ // GIR_Coverage, 3161,
13112 /* 36482 */ GIR_EraseRootFromParent_Done,
13113 /* 36483 */ // Label 999: @36483
13114 /* 36483 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1000*/ GIMT_Encode4(36503), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3166 //
13115 /* 36490 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2i64] }:$src
13116 /* 36490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13117 /* 36493 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13118 /* 36495 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13119 /* 36497 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13120 /* 36502 */ // GIR_Coverage, 3166,
13121 /* 36502 */ GIR_EraseRootFromParent_Done,
13122 /* 36503 */ // Label 1000: @36503
13123 /* 36503 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1001*/ GIMT_Encode4(36528), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3233 //
13124 /* 36510 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)
13125 /* 36510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
13126 /* 36513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13127 /* 36515 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13128 /* 36517 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13129 /* 36520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13130 /* 36526 */ GIR_RootConstrainSelectedInstOperands,
13131 /* 36527 */ // GIR_Coverage, 3233,
13132 /* 36527 */ GIR_EraseRootFromParent_Done,
13133 /* 36528 */ // Label 1001: @36528
13134 /* 36528 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1002*/ GIMT_Encode4(36553), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3238 //
13135 /* 36535 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)
13136 /* 36535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
13137 /* 36538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13138 /* 36540 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13139 /* 36542 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13140 /* 36545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13141 /* 36551 */ GIR_RootConstrainSelectedInstOperands,
13142 /* 36552 */ // GIR_Coverage, 3238,
13143 /* 36552 */ GIR_EraseRootFromParent_Done,
13144 /* 36553 */ // Label 1002: @36553
13145 /* 36553 */ GIM_Reject,
13146 /* 36554 */ // Label 998: @36554
13147 /* 36554 */ GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(36700),
13148 /* 36559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13149 /* 36563 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13150 /* 36567 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1004*/ GIMT_Encode4(36587), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5828 //
13151 /* 36574 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2f64] }:$src
13152 /* 36574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13153 /* 36577 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13154 /* 36579 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13155 /* 36581 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13156 /* 36586 */ // GIR_Coverage, 5828,
13157 /* 36586 */ GIR_EraseRootFromParent_Done,
13158 /* 36587 */ // Label 1004: @36587
13159 /* 36587 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1005*/ GIMT_Encode4(36607), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5833 //
13160 /* 36594 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2i64] }:$src
13161 /* 36594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13162 /* 36597 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13163 /* 36599 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13164 /* 36601 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13165 /* 36606 */ // GIR_Coverage, 5833,
13166 /* 36606 */ GIR_EraseRootFromParent_Done,
13167 /* 36607 */ // Label 1005: @36607
13168 /* 36607 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1006*/ GIMT_Encode4(36653), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5864 //
13169 /* 36614 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src)
13170 /* 36614 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13171 /* 36617 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13172 /* 36621 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13173 /* 36626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
13174 /* 36629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13175 /* 36631 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13176 /* 36633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13177 /* 36636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13178 /* 36642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13179 /* 36648 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13180 /* 36651 */ GIR_RootConstrainSelectedInstOperands,
13181 /* 36652 */ // GIR_Coverage, 5864,
13182 /* 36652 */ GIR_EraseRootFromParent_Done,
13183 /* 36653 */ // Label 1006: @36653
13184 /* 36653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1007*/ GIMT_Encode4(36699), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5869 //
13185 /* 36660 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src)
13186 /* 36660 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13187 /* 36663 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13188 /* 36667 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13189 /* 36672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
13190 /* 36675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13191 /* 36677 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13192 /* 36679 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13193 /* 36682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13194 /* 36688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13195 /* 36694 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13196 /* 36697 */ GIR_RootConstrainSelectedInstOperands,
13197 /* 36698 */ // GIR_Coverage, 5869,
13198 /* 36698 */ GIR_EraseRootFromParent_Done,
13199 /* 36699 */ // Label 1007: @36699
13200 /* 36699 */ GIM_Reject,
13201 /* 36700 */ // Label 1003: @36700
13202 /* 36700 */ GIM_Reject,
13203 /* 36701 */ // Label 994: @36701
13204 /* 36701 */ GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(36895),
13205 /* 36706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13206 /* 36710 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13207 /* 36714 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1009*/ GIMT_Encode4(36734), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3159 //
13208 /* 36721 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2f64] }:$src
13209 /* 36721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13210 /* 36724 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13211 /* 36726 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13212 /* 36728 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13213 /* 36733 */ // GIR_Coverage, 3159,
13214 /* 36733 */ GIR_EraseRootFromParent_Done,
13215 /* 36734 */ // Label 1009: @36734
13216 /* 36734 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1010*/ GIMT_Encode4(36754), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3160 //
13217 /* 36741 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2f64] }:$src
13218 /* 36741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13219 /* 36744 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13220 /* 36746 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13221 /* 36748 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13222 /* 36753 */ // GIR_Coverage, 3160,
13223 /* 36753 */ GIR_EraseRootFromParent_Done,
13224 /* 36754 */ // Label 1010: @36754
13225 /* 36754 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1011*/ GIMT_Encode4(36774), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3164 //
13226 /* 36761 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2i64] }:$src
13227 /* 36761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13228 /* 36764 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13229 /* 36766 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13230 /* 36768 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13231 /* 36773 */ // GIR_Coverage, 3164,
13232 /* 36773 */ GIR_EraseRootFromParent_Done,
13233 /* 36774 */ // Label 1011: @36774
13234 /* 36774 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1012*/ GIMT_Encode4(36794), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3165 //
13235 /* 36781 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2i64] }:$src
13236 /* 36781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13237 /* 36784 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13238 /* 36786 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13239 /* 36788 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13240 /* 36793 */ // GIR_Coverage, 3165,
13241 /* 36793 */ GIR_EraseRootFromParent_Done,
13242 /* 36794 */ // Label 1012: @36794
13243 /* 36794 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1013*/ GIMT_Encode4(36819), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3231 //
13244 /* 36801 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)
13245 /* 36801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
13246 /* 36804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13247 /* 36806 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13248 /* 36808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13249 /* 36811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13250 /* 36817 */ GIR_RootConstrainSelectedInstOperands,
13251 /* 36818 */ // GIR_Coverage, 3231,
13252 /* 36818 */ GIR_EraseRootFromParent_Done,
13253 /* 36819 */ // Label 1013: @36819
13254 /* 36819 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1014*/ GIMT_Encode4(36844), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3232 //
13255 /* 36826 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)
13256 /* 36826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
13257 /* 36829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13258 /* 36831 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13259 /* 36833 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13260 /* 36836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13261 /* 36842 */ GIR_RootConstrainSelectedInstOperands,
13262 /* 36843 */ // GIR_Coverage, 3232,
13263 /* 36843 */ GIR_EraseRootFromParent_Done,
13264 /* 36844 */ // Label 1014: @36844
13265 /* 36844 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1015*/ GIMT_Encode4(36869), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3236 //
13266 /* 36851 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src)
13267 /* 36851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
13268 /* 36854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13269 /* 36856 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13270 /* 36858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13271 /* 36861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13272 /* 36867 */ GIR_RootConstrainSelectedInstOperands,
13273 /* 36868 */ // GIR_Coverage, 3236,
13274 /* 36868 */ GIR_EraseRootFromParent_Done,
13275 /* 36869 */ // Label 1015: @36869
13276 /* 36869 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1016*/ GIMT_Encode4(36894), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3237 //
13277 /* 36876 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)
13278 /* 36876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
13279 /* 36879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13280 /* 36881 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13281 /* 36883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13282 /* 36886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13283 /* 36892 */ GIR_RootConstrainSelectedInstOperands,
13284 /* 36893 */ // GIR_Coverage, 3237,
13285 /* 36893 */ GIR_EraseRootFromParent_Done,
13286 /* 36894 */ // Label 1016: @36894
13287 /* 36894 */ GIM_Reject,
13288 /* 36895 */ // Label 1008: @36895
13289 /* 36895 */ GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(37173),
13290 /* 36900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13291 /* 36904 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13292 /* 36908 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1018*/ GIMT_Encode4(36928), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5826 //
13293 /* 36915 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2f64] }:$src
13294 /* 36915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13295 /* 36918 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13296 /* 36920 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13297 /* 36922 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13298 /* 36927 */ // GIR_Coverage, 5826,
13299 /* 36927 */ GIR_EraseRootFromParent_Done,
13300 /* 36928 */ // Label 1018: @36928
13301 /* 36928 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1019*/ GIMT_Encode4(36948), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5827 //
13302 /* 36935 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2f64] }:$src
13303 /* 36935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13304 /* 36938 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13305 /* 36940 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13306 /* 36942 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13307 /* 36947 */ // GIR_Coverage, 5827,
13308 /* 36947 */ GIR_EraseRootFromParent_Done,
13309 /* 36948 */ // Label 1019: @36948
13310 /* 36948 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1020*/ GIMT_Encode4(36968), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5831 //
13311 /* 36955 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2i64] }:$src
13312 /* 36955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13313 /* 36958 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13314 /* 36960 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13315 /* 36962 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13316 /* 36967 */ // GIR_Coverage, 5831,
13317 /* 36967 */ GIR_EraseRootFromParent_Done,
13318 /* 36968 */ // Label 1020: @36968
13319 /* 36968 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1021*/ GIMT_Encode4(36988), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5832 //
13320 /* 36975 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2i64] }:$src
13321 /* 36975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13322 /* 36978 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13323 /* 36980 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13324 /* 36982 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13325 /* 36987 */ // GIR_Coverage, 5832,
13326 /* 36987 */ GIR_EraseRootFromParent_Done,
13327 /* 36988 */ // Label 1021: @36988
13328 /* 36988 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1022*/ GIMT_Encode4(37034), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5862 //
13329 /* 36995 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src)
13330 /* 36995 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13331 /* 36998 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13332 /* 37002 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13333 /* 37007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
13334 /* 37010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13335 /* 37012 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13336 /* 37014 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13337 /* 37017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13338 /* 37023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13339 /* 37029 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13340 /* 37032 */ GIR_RootConstrainSelectedInstOperands,
13341 /* 37033 */ // GIR_Coverage, 5862,
13342 /* 37033 */ GIR_EraseRootFromParent_Done,
13343 /* 37034 */ // Label 1022: @37034
13344 /* 37034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1023*/ GIMT_Encode4(37080), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5863 //
13345 /* 37041 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src)
13346 /* 37041 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13347 /* 37044 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13348 /* 37048 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13349 /* 37053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
13350 /* 37056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13351 /* 37058 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13352 /* 37060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13353 /* 37063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13354 /* 37069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13355 /* 37075 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13356 /* 37078 */ GIR_RootConstrainSelectedInstOperands,
13357 /* 37079 */ // GIR_Coverage, 5863,
13358 /* 37079 */ GIR_EraseRootFromParent_Done,
13359 /* 37080 */ // Label 1023: @37080
13360 /* 37080 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1024*/ GIMT_Encode4(37126), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5867 //
13361 /* 37087 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src)
13362 /* 37087 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13363 /* 37090 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13364 /* 37094 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13365 /* 37099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
13366 /* 37102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13367 /* 37104 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13368 /* 37106 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13369 /* 37109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13370 /* 37115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13371 /* 37121 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13372 /* 37124 */ GIR_RootConstrainSelectedInstOperands,
13373 /* 37125 */ // GIR_Coverage, 5867,
13374 /* 37125 */ GIR_EraseRootFromParent_Done,
13375 /* 37126 */ // Label 1024: @37126
13376 /* 37126 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1025*/ GIMT_Encode4(37172), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5868 //
13377 /* 37133 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src)
13378 /* 37133 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13379 /* 37136 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13380 /* 37140 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13381 /* 37145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
13382 /* 37148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13383 /* 37150 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13384 /* 37152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13385 /* 37155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13386 /* 37161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13387 /* 37167 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13388 /* 37170 */ GIR_RootConstrainSelectedInstOperands,
13389 /* 37171 */ // GIR_Coverage, 5868,
13390 /* 37171 */ GIR_EraseRootFromParent_Done,
13391 /* 37172 */ // Label 1025: @37172
13392 /* 37172 */ GIM_Reject,
13393 /* 37173 */ // Label 1017: @37173
13394 /* 37173 */ GIM_Reject,
13395 /* 37174 */ // Label 995: @37174
13396 /* 37174 */ GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(37368),
13397 /* 37179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13398 /* 37183 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13399 /* 37187 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1027*/ GIMT_Encode4(37207), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3157 //
13400 /* 37194 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2f64] }:$src
13401 /* 37194 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13402 /* 37197 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13403 /* 37199 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13404 /* 37201 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13405 /* 37206 */ // GIR_Coverage, 3157,
13406 /* 37206 */ GIR_EraseRootFromParent_Done,
13407 /* 37207 */ // Label 1027: @37207
13408 /* 37207 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1028*/ GIMT_Encode4(37227), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3158 //
13409 /* 37214 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2f64] }:$src
13410 /* 37214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13411 /* 37217 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13412 /* 37219 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13413 /* 37221 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13414 /* 37226 */ // GIR_Coverage, 3158,
13415 /* 37226 */ GIR_EraseRootFromParent_Done,
13416 /* 37227 */ // Label 1028: @37227
13417 /* 37227 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1029*/ GIMT_Encode4(37247), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3162 //
13418 /* 37234 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2i64] }:$src
13419 /* 37234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13420 /* 37237 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13421 /* 37239 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13422 /* 37241 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13423 /* 37246 */ // GIR_Coverage, 3162,
13424 /* 37246 */ GIR_EraseRootFromParent_Done,
13425 /* 37247 */ // Label 1029: @37247
13426 /* 37247 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1030*/ GIMT_Encode4(37267), GIMT_Encode2(GIFBS_HasNEON_IsLE), // Rule ID 3163 //
13427 /* 37254 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2i64] }:$src
13428 /* 37254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13429 /* 37257 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13430 /* 37259 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13431 /* 37261 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13432 /* 37266 */ // GIR_Coverage, 3163,
13433 /* 37266 */ GIR_EraseRootFromParent_Done,
13434 /* 37267 */ // Label 1030: @37267
13435 /* 37267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1031*/ GIMT_Encode4(37292), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3229 //
13436 /* 37274 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)
13437 /* 37274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
13438 /* 37277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13439 /* 37279 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13440 /* 37281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13441 /* 37284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13442 /* 37290 */ GIR_RootConstrainSelectedInstOperands,
13443 /* 37291 */ // GIR_Coverage, 3229,
13444 /* 37291 */ GIR_EraseRootFromParent_Done,
13445 /* 37292 */ // Label 1031: @37292
13446 /* 37292 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1032*/ GIMT_Encode4(37317), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3230 //
13447 /* 37299 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)
13448 /* 37299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
13449 /* 37302 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13450 /* 37304 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13451 /* 37306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13452 /* 37309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13453 /* 37315 */ GIR_RootConstrainSelectedInstOperands,
13454 /* 37316 */ // GIR_Coverage, 3230,
13455 /* 37316 */ GIR_EraseRootFromParent_Done,
13456 /* 37317 */ // Label 1032: @37317
13457 /* 37317 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1033*/ GIMT_Encode4(37342), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3234 //
13458 /* 37324 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)
13459 /* 37324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
13460 /* 37327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13461 /* 37329 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13462 /* 37331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13463 /* 37334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13464 /* 37340 */ GIR_RootConstrainSelectedInstOperands,
13465 /* 37341 */ // GIR_Coverage, 3234,
13466 /* 37341 */ GIR_EraseRootFromParent_Done,
13467 /* 37342 */ // Label 1033: @37342
13468 /* 37342 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1034*/ GIMT_Encode4(37367), GIMT_Encode2(GIFBS_HasNEON_IsBE), // Rule ID 3235 //
13469 /* 37349 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)
13470 /* 37349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
13471 /* 37352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13472 /* 37354 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13473 /* 37356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13474 /* 37359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13475 /* 37365 */ GIR_RootConstrainSelectedInstOperands,
13476 /* 37366 */ // GIR_Coverage, 3235,
13477 /* 37366 */ GIR_EraseRootFromParent_Done,
13478 /* 37367 */ // Label 1034: @37367
13479 /* 37367 */ GIM_Reject,
13480 /* 37368 */ // Label 1026: @37368
13481 /* 37368 */ GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(37646),
13482 /* 37373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13483 /* 37377 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13484 /* 37381 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1036*/ GIMT_Encode4(37401), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5824 //
13485 /* 37388 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2f64] }:$src
13486 /* 37388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13487 /* 37391 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13488 /* 37393 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13489 /* 37395 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13490 /* 37400 */ // GIR_Coverage, 5824,
13491 /* 37400 */ GIR_EraseRootFromParent_Done,
13492 /* 37401 */ // Label 1036: @37401
13493 /* 37401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1037*/ GIMT_Encode4(37421), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5825 //
13494 /* 37408 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2f64] }:$src
13495 /* 37408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13496 /* 37411 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13497 /* 37413 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13498 /* 37415 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13499 /* 37420 */ // GIR_Coverage, 5825,
13500 /* 37420 */ GIR_EraseRootFromParent_Done,
13501 /* 37421 */ // Label 1037: @37421
13502 /* 37421 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1038*/ GIMT_Encode4(37441), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5829 //
13503 /* 37428 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2i64] }:$src
13504 /* 37428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13505 /* 37431 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13506 /* 37433 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13507 /* 37435 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13508 /* 37440 */ // GIR_Coverage, 5829,
13509 /* 37440 */ GIR_EraseRootFromParent_Done,
13510 /* 37441 */ // Label 1038: @37441
13511 /* 37441 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1039*/ GIMT_Encode4(37461), GIMT_Encode2(GIFBS_HasMVEInt_IsLE), // Rule ID 5830 //
13512 /* 37448 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2i64] }:$src
13513 /* 37448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13514 /* 37451 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13515 /* 37453 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13516 /* 37455 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13517 /* 37460 */ // GIR_Coverage, 5830,
13518 /* 37460 */ GIR_EraseRootFromParent_Done,
13519 /* 37461 */ // Label 1039: @37461
13520 /* 37461 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1040*/ GIMT_Encode4(37507), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5860 //
13521 /* 37468 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src)
13522 /* 37468 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13523 /* 37471 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13524 /* 37475 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13525 /* 37480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13526 /* 37483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13527 /* 37485 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13528 /* 37487 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13529 /* 37490 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13530 /* 37496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13531 /* 37502 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13532 /* 37505 */ GIR_RootConstrainSelectedInstOperands,
13533 /* 37506 */ // GIR_Coverage, 5860,
13534 /* 37506 */ GIR_EraseRootFromParent_Done,
13535 /* 37507 */ // Label 1040: @37507
13536 /* 37507 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1041*/ GIMT_Encode4(37553), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5861 //
13537 /* 37514 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src)
13538 /* 37514 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13539 /* 37517 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13540 /* 37521 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13541 /* 37526 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13542 /* 37529 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13543 /* 37531 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13544 /* 37533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13545 /* 37536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13546 /* 37542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13547 /* 37548 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13548 /* 37551 */ GIR_RootConstrainSelectedInstOperands,
13549 /* 37552 */ // GIR_Coverage, 5861,
13550 /* 37552 */ GIR_EraseRootFromParent_Done,
13551 /* 37553 */ // Label 1041: @37553
13552 /* 37553 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1042*/ GIMT_Encode4(37599), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5865 //
13553 /* 37560 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src)
13554 /* 37560 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13555 /* 37563 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13556 /* 37567 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13557 /* 37572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13558 /* 37575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13559 /* 37577 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13560 /* 37579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13561 /* 37582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13562 /* 37588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13563 /* 37594 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13564 /* 37597 */ GIR_RootConstrainSelectedInstOperands,
13565 /* 37598 */ // GIR_Coverage, 5865,
13566 /* 37598 */ GIR_EraseRootFromParent_Done,
13567 /* 37599 */ // Label 1042: @37599
13568 /* 37599 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1043*/ GIMT_Encode4(37645), GIMT_Encode2(GIFBS_HasMVEInt_IsBE), // Rule ID 5866 //
13569 /* 37606 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src)
13570 /* 37606 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13571 /* 37609 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13572 /* 37613 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13573 /* 37618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13574 /* 37621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13575 /* 37623 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13576 /* 37625 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13577 /* 37628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13578 /* 37634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13579 /* 37640 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13580 /* 37643 */ GIR_RootConstrainSelectedInstOperands,
13581 /* 37644 */ // GIR_Coverage, 5866,
13582 /* 37644 */ GIR_EraseRootFromParent_Done,
13583 /* 37645 */ // Label 1043: @37645
13584 /* 37645 */ GIM_Reject,
13585 /* 37646 */ // Label 1035: @37646
13586 /* 37646 */ GIM_Reject,
13587 /* 37647 */ // Label 996: @37647
13588 /* 37647 */ GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(37701),
13589 /* 37652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13590 /* 37656 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13591 /* 37660 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1045*/ GIMT_Encode4(37680), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3115 //
13592 /* 37667 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v2f64] }:$src
13593 /* 37667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13594 /* 37670 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13595 /* 37672 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13596 /* 37674 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13597 /* 37679 */ // GIR_Coverage, 3115,
13598 /* 37679 */ GIR_EraseRootFromParent_Done,
13599 /* 37680 */ // Label 1045: @37680
13600 /* 37680 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1046*/ GIMT_Encode4(37700), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3116 //
13601 /* 37687 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v2i64] }:$src
13602 /* 37687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13603 /* 37690 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13604 /* 37692 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13605 /* 37694 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13606 /* 37699 */ // GIR_Coverage, 3116,
13607 /* 37699 */ GIR_EraseRootFromParent_Done,
13608 /* 37700 */ // Label 1046: @37700
13609 /* 37700 */ GIM_Reject,
13610 /* 37701 */ // Label 1044: @37701
13611 /* 37701 */ GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(37755),
13612 /* 37706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13613 /* 37710 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13614 /* 37714 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1048*/ GIMT_Encode4(37734), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5818 //
13615 /* 37721 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v2f64] }:$src
13616 /* 37721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13617 /* 37724 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13618 /* 37726 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13619 /* 37728 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13620 /* 37733 */ // GIR_Coverage, 5818,
13621 /* 37733 */ GIR_EraseRootFromParent_Done,
13622 /* 37734 */ // Label 1048: @37734
13623 /* 37734 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1049*/ GIMT_Encode4(37754), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5819 //
13624 /* 37741 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v2i64] }:$src
13625 /* 37741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13626 /* 37744 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13627 /* 37746 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13628 /* 37748 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13629 /* 37753 */ // GIR_Coverage, 5819,
13630 /* 37753 */ GIR_EraseRootFromParent_Done,
13631 /* 37754 */ // Label 1049: @37754
13632 /* 37754 */ GIM_Reject,
13633 /* 37755 */ // Label 1047: @37755
13634 /* 37755 */ GIM_Reject,
13635 /* 37756 */ // Label 997: @37756
13636 /* 37756 */ GIM_Reject,
13637 /* 37757 */ // Label 727: @37757
13638 /* 37757 */ GIM_Reject,
13639 /* 37758 */ // Label 16: @37758
13640 /* 37758 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 1057*/ GIMT_Encode4(38156),
13641 /* 37769 */ /*GILLT_s16*//*Label 1050*/ GIMT_Encode4(37821),
13642 /* 37773 */ /*GILLT_s32*//*Label 1051*/ GIMT_Encode4(37858),
13643 /* 37777 */ /*GILLT_s64*//*Label 1052*/ GIMT_Encode4(37895), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
13644 /* 37805 */ /*GILLT_v4s16*//*Label 1053*/ GIMT_Encode4(37932),
13645 /* 37809 */ /*GILLT_v8s16*//*Label 1054*/ GIMT_Encode4(37958),
13646 /* 37813 */ /*GILLT_v2s32*//*Label 1055*/ GIMT_Encode4(38044),
13647 /* 37817 */ /*GILLT_v4s32*//*Label 1056*/ GIMT_Encode4(38070),
13648 /* 37821 */ // Label 1050: @37821
13649 /* 37821 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1058*/ GIMT_Encode4(37857), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 693 //
13650 /* 37828 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
13651 /* 37831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13652 /* 37835 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13653 /* 37839 */ // (ftrunc:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTZH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
13654 /* 37839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZH),
13655 /* 37842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
13656 /* 37844 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
13657 /* 37846 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13658 /* 37849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13659 /* 37855 */ GIR_RootConstrainSelectedInstOperands,
13660 /* 37856 */ // GIR_Coverage, 693,
13661 /* 37856 */ GIR_EraseRootFromParent_Done,
13662 /* 37857 */ // Label 1058: @37857
13663 /* 37857 */ GIM_Reject,
13664 /* 37858 */ // Label 1051: @37858
13665 /* 37858 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1059*/ GIMT_Encode4(37894), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 695 //
13666 /* 37865 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
13667 /* 37868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13668 /* 37872 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13669 /* 37876 */ // (ftrunc:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTZS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
13670 /* 37876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZS),
13671 /* 37879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
13672 /* 37881 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
13673 /* 37883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13674 /* 37886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13675 /* 37892 */ GIR_RootConstrainSelectedInstOperands,
13676 /* 37893 */ // GIR_Coverage, 695,
13677 /* 37893 */ GIR_EraseRootFromParent_Done,
13678 /* 37894 */ // Label 1059: @37894
13679 /* 37894 */ GIM_Reject,
13680 /* 37895 */ // Label 1052: @37895
13681 /* 37895 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1060*/ GIMT_Encode4(37931), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 697 //
13682 /* 37902 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13683 /* 37905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13684 /* 37909 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13685 /* 37913 */ // (ftrunc:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTZD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
13686 /* 37913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZD),
13687 /* 37916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
13688 /* 37918 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
13689 /* 37920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13690 /* 37923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13691 /* 37929 */ GIR_RootConstrainSelectedInstOperands,
13692 /* 37930 */ // GIR_Coverage, 697,
13693 /* 37930 */ GIR_EraseRootFromParent_Done,
13694 /* 37931 */ // Label 1060: @37931
13695 /* 37931 */ GIM_Reject,
13696 /* 37932 */ // Label 1053: @37932
13697 /* 37932 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1061*/ GIMT_Encode4(37957), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1882 //
13698 /* 37939 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13699 /* 37942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13700 /* 37946 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13701 /* 37950 */ // (ftrunc:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTZNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
13702 /* 37950 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDh),
13703 /* 37955 */ GIR_RootConstrainSelectedInstOperands,
13704 /* 37956 */ // GIR_Coverage, 1882,
13705 /* 37956 */ GIR_Done,
13706 /* 37957 */ // Label 1061: @37957
13707 /* 37957 */ GIM_Reject,
13708 /* 37958 */ // Label 1054: @37958
13709 /* 37958 */ GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(38043),
13710 /* 37963 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13711 /* 37966 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1063*/ GIMT_Encode4(37988), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1884 //
13712 /* 37973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13713 /* 37977 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13714 /* 37981 */ // (ftrunc:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTZNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
13715 /* 37981 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQh),
13716 /* 37986 */ GIR_RootConstrainSelectedInstOperands,
13717 /* 37987 */ // GIR_Coverage, 1884,
13718 /* 37987 */ GIR_Done,
13719 /* 37988 */ // Label 1063: @37988
13720 /* 37988 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1064*/ GIMT_Encode4(38042), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4380 //
13721 /* 37995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13722 /* 37999 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13723 /* 38003 */ // (ftrunc:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
13724 /* 38003 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13725 /* 38006 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13726 /* 38010 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13727 /* 38015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z),
13728 /* 38018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13729 /* 38020 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
13730 /* 38022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13731 /* 38025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13732 /* 38031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13733 /* 38037 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13734 /* 38040 */ GIR_RootConstrainSelectedInstOperands,
13735 /* 38041 */ // GIR_Coverage, 4380,
13736 /* 38041 */ GIR_EraseRootFromParent_Done,
13737 /* 38042 */ // Label 1064: @38042
13738 /* 38042 */ GIM_Reject,
13739 /* 38043 */ // Label 1062: @38043
13740 /* 38043 */ GIM_Reject,
13741 /* 38044 */ // Label 1055: @38044
13742 /* 38044 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1065*/ GIMT_Encode4(38069), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1878 //
13743 /* 38051 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
13744 /* 38054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13745 /* 38058 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13746 /* 38062 */ // (ftrunc:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTZNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
13747 /* 38062 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDf),
13748 /* 38067 */ GIR_RootConstrainSelectedInstOperands,
13749 /* 38068 */ // GIR_Coverage, 1878,
13750 /* 38068 */ GIR_Done,
13751 /* 38069 */ // Label 1065: @38069
13752 /* 38069 */ GIM_Reject,
13753 /* 38070 */ // Label 1056: @38070
13754 /* 38070 */ GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(38155),
13755 /* 38075 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13756 /* 38078 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1067*/ GIMT_Encode4(38100), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1880 //
13757 /* 38085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13758 /* 38089 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13759 /* 38093 */ // (ftrunc:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTZNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
13760 /* 38093 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQf),
13761 /* 38098 */ GIR_RootConstrainSelectedInstOperands,
13762 /* 38099 */ // GIR_Coverage, 1880,
13763 /* 38099 */ GIR_Done,
13764 /* 38100 */ // Label 1067: @38100
13765 /* 38100 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1068*/ GIMT_Encode4(38154), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4404 //
13766 /* 38107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13767 /* 38111 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13768 /* 38115 */ // (ftrunc:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
13769 /* 38115 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13770 /* 38118 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13771 /* 38122 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13772 /* 38127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z),
13773 /* 38130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13774 /* 38132 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
13775 /* 38134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13776 /* 38137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13777 /* 38143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13778 /* 38149 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13779 /* 38152 */ GIR_RootConstrainSelectedInstOperands,
13780 /* 38153 */ // GIR_Coverage, 4404,
13781 /* 38153 */ GIR_EraseRootFromParent_Done,
13782 /* 38154 */ // Label 1068: @38154
13783 /* 38154 */ GIM_Reject,
13784 /* 38155 */ // Label 1066: @38155
13785 /* 38155 */ GIM_Reject,
13786 /* 38156 */ // Label 1057: @38156
13787 /* 38156 */ GIM_Reject,
13788 /* 38157 */ // Label 17: @38157
13789 /* 38157 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 1076*/ GIMT_Encode4(38522),
13790 /* 38168 */ /*GILLT_s16*//*Label 1069*/ GIMT_Encode4(38220),
13791 /* 38172 */ /*GILLT_s32*//*Label 1070*/ GIMT_Encode4(38246),
13792 /* 38176 */ /*GILLT_s64*//*Label 1071*/ GIMT_Encode4(38272), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
13793 /* 38204 */ /*GILLT_v4s16*//*Label 1072*/ GIMT_Encode4(38298),
13794 /* 38208 */ /*GILLT_v8s16*//*Label 1073*/ GIMT_Encode4(38324),
13795 /* 38212 */ /*GILLT_v2s32*//*Label 1074*/ GIMT_Encode4(38410),
13796 /* 38216 */ /*GILLT_v4s32*//*Label 1075*/ GIMT_Encode4(38436),
13797 /* 38220 */ // Label 1069: @38220
13798 /* 38220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1077*/ GIMT_Encode4(38245), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 711 //
13799 /* 38227 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
13800 /* 38230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13801 /* 38234 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13802 /* 38238 */ // (fround:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTAH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
13803 /* 38238 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAH),
13804 /* 38243 */ GIR_RootConstrainSelectedInstOperands,
13805 /* 38244 */ // GIR_Coverage, 711,
13806 /* 38244 */ GIR_Done,
13807 /* 38245 */ // Label 1077: @38245
13808 /* 38245 */ GIM_Reject,
13809 /* 38246 */ // Label 1070: @38246
13810 /* 38246 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1078*/ GIMT_Encode4(38271), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 713 //
13811 /* 38253 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
13812 /* 38256 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13813 /* 38260 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13814 /* 38264 */ // (fround:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTAS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
13815 /* 38264 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAS),
13816 /* 38269 */ GIR_RootConstrainSelectedInstOperands,
13817 /* 38270 */ // GIR_Coverage, 713,
13818 /* 38270 */ GIR_Done,
13819 /* 38271 */ // Label 1078: @38271
13820 /* 38271 */ GIM_Reject,
13821 /* 38272 */ // Label 1071: @38272
13822 /* 38272 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1079*/ GIMT_Encode4(38297), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 715 //
13823 /* 38279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13824 /* 38282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13825 /* 38286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13826 /* 38290 */ // (fround:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTAD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
13827 /* 38290 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAD),
13828 /* 38295 */ GIR_RootConstrainSelectedInstOperands,
13829 /* 38296 */ // GIR_Coverage, 715,
13830 /* 38296 */ GIR_Done,
13831 /* 38297 */ // Label 1079: @38297
13832 /* 38297 */ GIM_Reject,
13833 /* 38298 */ // Label 1072: @38298
13834 /* 38298 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1080*/ GIMT_Encode4(38323), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1874 //
13835 /* 38305 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13836 /* 38308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13837 /* 38312 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13838 /* 38316 */ // (fround:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTANDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
13839 /* 38316 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDh),
13840 /* 38321 */ GIR_RootConstrainSelectedInstOperands,
13841 /* 38322 */ // GIR_Coverage, 1874,
13842 /* 38322 */ GIR_Done,
13843 /* 38323 */ // Label 1080: @38323
13844 /* 38323 */ GIM_Reject,
13845 /* 38324 */ // Label 1073: @38324
13846 /* 38324 */ GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(38409),
13847 /* 38329 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13848 /* 38332 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1082*/ GIMT_Encode4(38354), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1876 //
13849 /* 38339 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13850 /* 38343 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13851 /* 38347 */ // (fround:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTANQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
13852 /* 38347 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQh),
13853 /* 38352 */ GIR_RootConstrainSelectedInstOperands,
13854 /* 38353 */ // GIR_Coverage, 1876,
13855 /* 38353 */ GIR_Done,
13856 /* 38354 */ // Label 1082: @38354
13857 /* 38354 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1083*/ GIMT_Encode4(38408), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4376 //
13858 /* 38361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13859 /* 38365 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13860 /* 38369 */ // (fround:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
13861 /* 38369 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13862 /* 38372 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13863 /* 38376 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13864 /* 38381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A),
13865 /* 38384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13866 /* 38386 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
13867 /* 38388 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13868 /* 38391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13869 /* 38397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13870 /* 38403 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13871 /* 38406 */ GIR_RootConstrainSelectedInstOperands,
13872 /* 38407 */ // GIR_Coverage, 4376,
13873 /* 38407 */ GIR_EraseRootFromParent_Done,
13874 /* 38408 */ // Label 1083: @38408
13875 /* 38408 */ GIM_Reject,
13876 /* 38409 */ // Label 1081: @38409
13877 /* 38409 */ GIM_Reject,
13878 /* 38410 */ // Label 1074: @38410
13879 /* 38410 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1084*/ GIMT_Encode4(38435), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1870 //
13880 /* 38417 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
13881 /* 38420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13882 /* 38424 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13883 /* 38428 */ // (fround:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTANDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
13884 /* 38428 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDf),
13885 /* 38433 */ GIR_RootConstrainSelectedInstOperands,
13886 /* 38434 */ // GIR_Coverage, 1870,
13887 /* 38434 */ GIR_Done,
13888 /* 38435 */ // Label 1084: @38435
13889 /* 38435 */ GIM_Reject,
13890 /* 38436 */ // Label 1075: @38436
13891 /* 38436 */ GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(38521),
13892 /* 38441 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13893 /* 38444 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1086*/ GIMT_Encode4(38466), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1872 //
13894 /* 38451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13895 /* 38455 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13896 /* 38459 */ // (fround:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTANQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
13897 /* 38459 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQf),
13898 /* 38464 */ GIR_RootConstrainSelectedInstOperands,
13899 /* 38465 */ // GIR_Coverage, 1872,
13900 /* 38465 */ GIR_Done,
13901 /* 38466 */ // Label 1086: @38466
13902 /* 38466 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1087*/ GIMT_Encode4(38520), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4400 //
13903 /* 38473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13904 /* 38477 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13905 /* 38481 */ // (fround:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
13906 /* 38481 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13907 /* 38484 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13908 /* 38488 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13909 /* 38493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A),
13910 /* 38496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13911 /* 38498 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
13912 /* 38500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13913 /* 38503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13914 /* 38509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13915 /* 38515 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13916 /* 38518 */ GIR_RootConstrainSelectedInstOperands,
13917 /* 38519 */ // GIR_Coverage, 4400,
13918 /* 38519 */ GIR_EraseRootFromParent_Done,
13919 /* 38520 */ // Label 1087: @38520
13920 /* 38520 */ GIM_Reject,
13921 /* 38521 */ // Label 1085: @38521
13922 /* 38521 */ GIM_Reject,
13923 /* 38522 */ // Label 1076: @38522
13924 /* 38522 */ GIM_Reject,
13925 /* 38523 */ // Label 18: @38523
13926 /* 38523 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 1095*/ GIMT_Encode4(38888),
13927 /* 38534 */ /*GILLT_s16*//*Label 1088*/ GIMT_Encode4(38586),
13928 /* 38538 */ /*GILLT_s32*//*Label 1089*/ GIMT_Encode4(38612),
13929 /* 38542 */ /*GILLT_s64*//*Label 1090*/ GIMT_Encode4(38638), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
13930 /* 38570 */ /*GILLT_v4s16*//*Label 1091*/ GIMT_Encode4(38664),
13931 /* 38574 */ /*GILLT_v8s16*//*Label 1092*/ GIMT_Encode4(38690),
13932 /* 38578 */ /*GILLT_v2s32*//*Label 1093*/ GIMT_Encode4(38776),
13933 /* 38582 */ /*GILLT_v4s32*//*Label 1094*/ GIMT_Encode4(38802),
13934 /* 38586 */ // Label 1088: @38586
13935 /* 38586 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1096*/ GIMT_Encode4(38611), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 717 //
13936 /* 38593 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
13937 /* 38596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13938 /* 38600 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
13939 /* 38604 */ // (froundeven:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
13940 /* 38604 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNH),
13941 /* 38609 */ GIR_RootConstrainSelectedInstOperands,
13942 /* 38610 */ // GIR_Coverage, 717,
13943 /* 38610 */ GIR_Done,
13944 /* 38611 */ // Label 1096: @38611
13945 /* 38611 */ GIM_Reject,
13946 /* 38612 */ // Label 1089: @38612
13947 /* 38612 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1097*/ GIMT_Encode4(38637), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 719 //
13948 /* 38619 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
13949 /* 38622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13950 /* 38626 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
13951 /* 38630 */ // (froundeven:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
13952 /* 38630 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNS),
13953 /* 38635 */ GIR_RootConstrainSelectedInstOperands,
13954 /* 38636 */ // GIR_Coverage, 719,
13955 /* 38636 */ GIR_Done,
13956 /* 38637 */ // Label 1097: @38637
13957 /* 38637 */ GIM_Reject,
13958 /* 38638 */ // Label 1090: @38638
13959 /* 38638 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1098*/ GIMT_Encode4(38663), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 721 //
13960 /* 38645 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13961 /* 38648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13962 /* 38652 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13963 /* 38656 */ // (froundeven:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
13964 /* 38656 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTND),
13965 /* 38661 */ GIR_RootConstrainSelectedInstOperands,
13966 /* 38662 */ // GIR_Coverage, 721,
13967 /* 38662 */ GIR_Done,
13968 /* 38663 */ // Label 1098: @38663
13969 /* 38663 */ GIM_Reject,
13970 /* 38664 */ // Label 1091: @38664
13971 /* 38664 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1099*/ GIMT_Encode4(38689), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1858 //
13972 /* 38671 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13973 /* 38674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13974 /* 38678 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13975 /* 38682 */ // (froundeven:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
13976 /* 38682 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDh),
13977 /* 38687 */ GIR_RootConstrainSelectedInstOperands,
13978 /* 38688 */ // GIR_Coverage, 1858,
13979 /* 38688 */ GIR_Done,
13980 /* 38689 */ // Label 1099: @38689
13981 /* 38689 */ GIM_Reject,
13982 /* 38690 */ // Label 1092: @38690
13983 /* 38690 */ GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(38775),
13984 /* 38695 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13985 /* 38698 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1101*/ GIMT_Encode4(38720), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1860 //
13986 /* 38705 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13987 /* 38709 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13988 /* 38713 */ // (froundeven:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
13989 /* 38713 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQh),
13990 /* 38718 */ GIR_RootConstrainSelectedInstOperands,
13991 /* 38719 */ // GIR_Coverage, 1860,
13992 /* 38719 */ GIR_Done,
13993 /* 38720 */ // Label 1101: @38720
13994 /* 38720 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1102*/ GIMT_Encode4(38774), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4368 //
13995 /* 38727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13996 /* 38731 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13997 /* 38735 */ // (froundeven:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
13998 /* 38735 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13999 /* 38738 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14000 /* 38742 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14001 /* 38747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N),
14002 /* 38750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14003 /* 38752 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
14004 /* 38754 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14005 /* 38757 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14006 /* 38763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14007 /* 38769 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14008 /* 38772 */ GIR_RootConstrainSelectedInstOperands,
14009 /* 38773 */ // GIR_Coverage, 4368,
14010 /* 38773 */ GIR_EraseRootFromParent_Done,
14011 /* 38774 */ // Label 1102: @38774
14012 /* 38774 */ GIM_Reject,
14013 /* 38775 */ // Label 1100: @38775
14014 /* 38775 */ GIM_Reject,
14015 /* 38776 */ // Label 1093: @38776
14016 /* 38776 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1103*/ GIMT_Encode4(38801), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1854 //
14017 /* 38783 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
14018 /* 38786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14019 /* 38790 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14020 /* 38794 */ // (froundeven:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTNNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14021 /* 38794 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDf),
14022 /* 38799 */ GIR_RootConstrainSelectedInstOperands,
14023 /* 38800 */ // GIR_Coverage, 1854,
14024 /* 38800 */ GIR_Done,
14025 /* 38801 */ // Label 1103: @38801
14026 /* 38801 */ GIM_Reject,
14027 /* 38802 */ // Label 1094: @38802
14028 /* 38802 */ GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(38887),
14029 /* 38807 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14030 /* 38810 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1105*/ GIMT_Encode4(38832), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1856 //
14031 /* 38817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14032 /* 38821 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14033 /* 38825 */ // (froundeven:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTNNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14034 /* 38825 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQf),
14035 /* 38830 */ GIR_RootConstrainSelectedInstOperands,
14036 /* 38831 */ // GIR_Coverage, 1856,
14037 /* 38831 */ GIR_Done,
14038 /* 38832 */ // Label 1105: @38832
14039 /* 38832 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1106*/ GIMT_Encode4(38886), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4392 //
14040 /* 38839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14041 /* 38843 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14042 /* 38847 */ // (froundeven:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
14043 /* 38847 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14044 /* 38850 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14045 /* 38854 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14046 /* 38859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N),
14047 /* 38862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14048 /* 38864 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
14049 /* 38866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14050 /* 38869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14051 /* 38875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14052 /* 38881 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14053 /* 38884 */ GIR_RootConstrainSelectedInstOperands,
14054 /* 38885 */ // GIR_Coverage, 4392,
14055 /* 38885 */ GIR_EraseRootFromParent_Done,
14056 /* 38886 */ // Label 1106: @38886
14057 /* 38886 */ GIM_Reject,
14058 /* 38887 */ // Label 1104: @38887
14059 /* 38887 */ GIM_Reject,
14060 /* 38888 */ // Label 1095: @38888
14061 /* 38888 */ GIM_Reject,
14062 /* 38889 */ // Label 19: @38889
14063 /* 38889 */ GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(39049),
14064 /* 38894 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14065 /* 38897 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
14066 /* 38900 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1108*/ GIMT_Encode4(38974), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 2249 //
14067 /* 38907 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
14068 /* 38914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
14069 /* 38918 */ // MIs[0] Rn
14070 /* 38918 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
14071 /* 38922 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
14072 /* 38926 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (tLDRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
14073 /* 38926 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
14074 /* 38929 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
14075 /* 38933 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14076 /* 38938 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
14077 /* 38944 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
14078 /* 38947 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
14079 /* 38950 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14080 /* 38956 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14081 /* 38958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSB),
14082 /* 38961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
14083 /* 38963 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
14084 /* 38965 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14085 /* 38968 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14086 /* 38972 */ GIR_RootConstrainSelectedInstOperands,
14087 /* 38973 */ // GIR_Coverage, 2249,
14088 /* 38973 */ GIR_EraseRootFromParent_Done,
14089 /* 38974 */ // Label 1108: @38974
14090 /* 38974 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1109*/ GIMT_Encode4(39048), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 2250 //
14091 /* 38981 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
14092 /* 38988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
14093 /* 38992 */ // MIs[0] Rn
14094 /* 38992 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
14095 /* 38996 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
14096 /* 39000 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (tLDRSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
14097 /* 39000 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
14098 /* 39003 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
14099 /* 39007 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14100 /* 39012 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
14101 /* 39018 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
14102 /* 39021 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
14103 /* 39024 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14104 /* 39030 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
14105 /* 39032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSH),
14106 /* 39035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
14107 /* 39037 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
14108 /* 39039 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14109 /* 39042 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
14110 /* 39046 */ GIR_RootConstrainSelectedInstOperands,
14111 /* 39047 */ // GIR_Coverage, 2250,
14112 /* 39047 */ GIR_EraseRootFromParent_Done,
14113 /* 39048 */ // Label 1109: @39048
14114 /* 39048 */ GIM_Reject,
14115 /* 39049 */ // Label 1107: @39049
14116 /* 39049 */ GIM_Reject,
14117 /* 39050 */ // Label 20: @39050
14118 /* 39050 */ GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(39070), // Rule ID 5956 //
14119 /* 39055 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14120 /* 39058 */ // MIs[0] Operand 0
14121 /* 39058 */ GIM_CheckIsImm, /*MI*/0, /*Op*/0,
14122 /* 39061 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
14123 /* 39065 */ // (atomic_fence (timm:{ *:[i32] }), 0:{ *:[i32] }) => (MEMBARRIER)
14124 /* 39065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::MEMBARRIER),
14125 /* 39068 */ GIR_RootConstrainSelectedInstOperands,
14126 /* 39069 */ // GIR_Coverage, 5956,
14127 /* 39069 */ GIR_EraseRootFromParent_Done,
14128 /* 39070 */ // Label 1110: @39070
14129 /* 39070 */ GIM_Reject,
14130 /* 39071 */ // Label 21: @39071
14131 /* 39071 */ GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(44382),
14132 /* 39076 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
14133 /* 39079 */ GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(39168),
14134 /* 39084 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16),
14135 /* 39089 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14136 /* 39092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
14137 /* 39095 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1113*/ GIMT_Encode4(39131), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2044 //
14138 /* 39102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
14139 /* 39106 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
14140 /* 39110 */ // (intrinsic_wo_chain:{ *:[i32] } 4175:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
14141 /* 39110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16),
14142 /* 39113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
14143 /* 39115 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src
14144 /* 39117 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14145 /* 39120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14146 /* 39123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14147 /* 39129 */ GIR_RootConstrainSelectedInstOperands,
14148 /* 39130 */ // GIR_Coverage, 2044,
14149 /* 39130 */ GIR_EraseRootFromParent_Done,
14150 /* 39131 */ // Label 1113: @39131
14151 /* 39131 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1114*/ GIMT_Encode4(39167), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2306 //
14152 /* 39138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
14153 /* 39142 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
14154 /* 39146 */ // (intrinsic_wo_chain:{ *:[i32] } 4175:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
14155 /* 39146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16),
14156 /* 39149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
14157 /* 39151 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
14158 /* 39153 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14159 /* 39156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14160 /* 39159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14161 /* 39165 */ GIR_RootConstrainSelectedInstOperands,
14162 /* 39166 */ // GIR_Coverage, 2306,
14163 /* 39166 */ GIR_EraseRootFromParent_Done,
14164 /* 39167 */ // Label 1114: @39167
14165 /* 39167 */ GIM_Reject,
14166 /* 39168 */ // Label 1112: @39168
14167 /* 39168 */ GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(39269),
14168 /* 39173 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr),
14169 /* 39178 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14170 /* 39181 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1118*/ GIMT_Encode4(39268),
14171 /* 39192 */ /*GILLT_s32*//*Label 1116*/ GIMT_Encode4(39200),
14172 /* 39196 */ /*GILLT_s64*//*Label 1117*/ GIMT_Encode4(39234),
14173 /* 39200 */ // Label 1116: @39200
14174 /* 39200 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1119*/ GIMT_Encode4(39233), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 745 //
14175 /* 39207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14176 /* 39211 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14177 /* 39215 */ // (intrinsic_wo_chain:{ *:[f32] } 4176:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14178 /* 39215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRS),
14179 /* 39218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
14180 /* 39220 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
14181 /* 39222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14182 /* 39225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14183 /* 39231 */ GIR_RootConstrainSelectedInstOperands,
14184 /* 39232 */ // GIR_Coverage, 745,
14185 /* 39232 */ GIR_EraseRootFromParent_Done,
14186 /* 39233 */ // Label 1119: @39233
14187 /* 39233 */ GIM_Reject,
14188 /* 39234 */ // Label 1117: @39234
14189 /* 39234 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1120*/ GIMT_Encode4(39267), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 744 //
14190 /* 39241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14191 /* 39245 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14192 /* 39249 */ // (intrinsic_wo_chain:{ *:[f32] } 4176:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
14193 /* 39249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRD),
14194 /* 39252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
14195 /* 39254 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
14196 /* 39256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14197 /* 39259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14198 /* 39265 */ GIR_RootConstrainSelectedInstOperands,
14199 /* 39266 */ // GIR_Coverage, 744,
14200 /* 39266 */ GIR_EraseRootFromParent_Done,
14201 /* 39267 */ // Label 1120: @39267
14202 /* 39267 */ GIM_Reject,
14203 /* 39268 */ // Label 1118: @39268
14204 /* 39268 */ GIM_Reject,
14205 /* 39269 */ // Label 1115: @39269
14206 /* 39269 */ GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(39370),
14207 /* 39274 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru),
14208 /* 39279 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
14209 /* 39282 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1124*/ GIMT_Encode4(39369),
14210 /* 39293 */ /*GILLT_s32*//*Label 1122*/ GIMT_Encode4(39301),
14211 /* 39297 */ /*GILLT_s64*//*Label 1123*/ GIMT_Encode4(39335),
14212 /* 39301 */ // Label 1122: @39301
14213 /* 39301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1125*/ GIMT_Encode4(39334), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 747 //
14214 /* 39308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14215 /* 39312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14216 /* 39316 */ // (intrinsic_wo_chain:{ *:[f32] } 4177:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14217 /* 39316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRS),
14218 /* 39319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
14219 /* 39321 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
14220 /* 39323 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14221 /* 39326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14222 /* 39332 */ GIR_RootConstrainSelectedInstOperands,
14223 /* 39333 */ // GIR_Coverage, 747,
14224 /* 39333 */ GIR_EraseRootFromParent_Done,
14225 /* 39334 */ // Label 1125: @39334
14226 /* 39334 */ GIM_Reject,
14227 /* 39335 */ // Label 1123: @39335
14228 /* 39335 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1126*/ GIMT_Encode4(39368), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 746 //
14229 /* 39342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14230 /* 39346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14231 /* 39350 */ // (intrinsic_wo_chain:{ *:[f32] } 4177:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
14232 /* 39350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRD),
14233 /* 39353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
14234 /* 39355 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
14235 /* 39357 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14236 /* 39360 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14237 /* 39366 */ GIR_RootConstrainSelectedInstOperands,
14238 /* 39367 */ // GIR_Coverage, 746,
14239 /* 39367 */ GIR_EraseRootFromParent_Done,
14240 /* 39368 */ // Label 1126: @39368
14241 /* 39368 */ GIM_Reject,
14242 /* 39369 */ // Label 1124: @39369
14243 /* 39369 */ GIM_Reject,
14244 /* 39370 */ // Label 1121: @39370
14245 /* 39370 */ GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(39662),
14246 /* 39375 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
14247 /* 39380 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1134*/ GIMT_Encode4(39661),
14248 /* 39391 */ /*GILLT_s64*//*Label 1128*/ GIMT_Encode4(39439), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
14249 /* 39419 */ /*GILLT_v4s16*//*Label 1129*/ GIMT_Encode4(39476),
14250 /* 39423 */ /*GILLT_v8s16*//*Label 1130*/ GIMT_Encode4(39513),
14251 /* 39427 */ /*GILLT_v2s32*//*Label 1131*/ GIMT_Encode4(39550),
14252 /* 39431 */ /*GILLT_v4s32*//*Label 1132*/ GIMT_Encode4(39587),
14253 /* 39435 */ /*GILLT_v2s64*//*Label 1133*/ GIMT_Encode4(39624),
14254 /* 39439 */ // Label 1128: @39439
14255 /* 39439 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1135*/ GIMT_Encode4(39475), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1406 //
14256 /* 39446 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
14257 /* 39449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14258 /* 39453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14259 /* 39457 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4033:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
14260 /* 39457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv2i32),
14261 /* 39460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14262 /* 39462 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14263 /* 39464 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14264 /* 39467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14265 /* 39473 */ GIR_RootConstrainSelectedInstOperands,
14266 /* 39474 */ // GIR_Coverage, 1406,
14267 /* 39474 */ GIR_EraseRootFromParent_Done,
14268 /* 39475 */ // Label 1135: @39475
14269 /* 39475 */ GIM_Reject,
14270 /* 39476 */ // Label 1129: @39476
14271 /* 39476 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1136*/ GIMT_Encode4(39512), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1404 //
14272 /* 39483 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
14273 /* 39486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14274 /* 39490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14275 /* 39494 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4033:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
14276 /* 39494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i8),
14277 /* 39497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14278 /* 39499 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14279 /* 39501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14280 /* 39504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14281 /* 39510 */ GIR_RootConstrainSelectedInstOperands,
14282 /* 39511 */ // GIR_Coverage, 1404,
14283 /* 39511 */ GIR_EraseRootFromParent_Done,
14284 /* 39512 */ // Label 1136: @39512
14285 /* 39512 */ GIM_Reject,
14286 /* 39513 */ // Label 1130: @39513
14287 /* 39513 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1137*/ GIMT_Encode4(39549), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1407 //
14288 /* 39520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
14289 /* 39523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14290 /* 39527 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14291 /* 39531 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4033:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
14292 /* 39531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv16i8),
14293 /* 39534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14294 /* 39536 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14295 /* 39538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14296 /* 39541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14297 /* 39547 */ GIR_RootConstrainSelectedInstOperands,
14298 /* 39548 */ // GIR_Coverage, 1407,
14299 /* 39548 */ GIR_EraseRootFromParent_Done,
14300 /* 39549 */ // Label 1137: @39549
14301 /* 39549 */ GIM_Reject,
14302 /* 39550 */ // Label 1131: @39550
14303 /* 39550 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1138*/ GIMT_Encode4(39586), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1405 //
14304 /* 39557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
14305 /* 39560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14306 /* 39564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14307 /* 39568 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4033:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
14308 /* 39568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i16),
14309 /* 39571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14310 /* 39573 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14311 /* 39575 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14312 /* 39578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14313 /* 39584 */ GIR_RootConstrainSelectedInstOperands,
14314 /* 39585 */ // GIR_Coverage, 1405,
14315 /* 39585 */ GIR_EraseRootFromParent_Done,
14316 /* 39586 */ // Label 1138: @39586
14317 /* 39586 */ GIM_Reject,
14318 /* 39587 */ // Label 1132: @39587
14319 /* 39587 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1139*/ GIMT_Encode4(39623), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1408 //
14320 /* 39594 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14321 /* 39597 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14322 /* 39601 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14323 /* 39605 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4033:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
14324 /* 39605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i16),
14325 /* 39608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14326 /* 39610 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14327 /* 39612 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14328 /* 39615 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14329 /* 39621 */ GIR_RootConstrainSelectedInstOperands,
14330 /* 39622 */ // GIR_Coverage, 1408,
14331 /* 39622 */ GIR_EraseRootFromParent_Done,
14332 /* 39623 */ // Label 1139: @39623
14333 /* 39623 */ GIM_Reject,
14334 /* 39624 */ // Label 1133: @39624
14335 /* 39624 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1140*/ GIMT_Encode4(39660), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1409 //
14336 /* 39631 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14337 /* 39634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14338 /* 39638 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14339 /* 39642 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4033:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
14340 /* 39642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i32),
14341 /* 39645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14342 /* 39647 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14343 /* 39649 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14344 /* 39652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14345 /* 39658 */ GIR_RootConstrainSelectedInstOperands,
14346 /* 39659 */ // GIR_Coverage, 1409,
14347 /* 39659 */ GIR_EraseRootFromParent_Done,
14348 /* 39660 */ // Label 1140: @39660
14349 /* 39660 */ GIM_Reject,
14350 /* 39661 */ // Label 1134: @39661
14351 /* 39661 */ GIM_Reject,
14352 /* 39662 */ // Label 1127: @39662
14353 /* 39662 */ GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(39954),
14354 /* 39667 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
14355 /* 39672 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1148*/ GIMT_Encode4(39953),
14356 /* 39683 */ /*GILLT_s64*//*Label 1142*/ GIMT_Encode4(39731), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
14357 /* 39711 */ /*GILLT_v4s16*//*Label 1143*/ GIMT_Encode4(39768),
14358 /* 39715 */ /*GILLT_v8s16*//*Label 1144*/ GIMT_Encode4(39805),
14359 /* 39719 */ /*GILLT_v2s32*//*Label 1145*/ GIMT_Encode4(39842),
14360 /* 39723 */ /*GILLT_v4s32*//*Label 1146*/ GIMT_Encode4(39879),
14361 /* 39727 */ /*GILLT_v2s64*//*Label 1147*/ GIMT_Encode4(39916),
14362 /* 39731 */ // Label 1142: @39731
14363 /* 39731 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1149*/ GIMT_Encode4(39767), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1412 //
14364 /* 39738 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
14365 /* 39741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14366 /* 39745 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14367 /* 39749 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4034:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
14368 /* 39749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv2i32),
14369 /* 39752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14370 /* 39754 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14371 /* 39756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14372 /* 39759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14373 /* 39765 */ GIR_RootConstrainSelectedInstOperands,
14374 /* 39766 */ // GIR_Coverage, 1412,
14375 /* 39766 */ GIR_EraseRootFromParent_Done,
14376 /* 39767 */ // Label 1149: @39767
14377 /* 39767 */ GIM_Reject,
14378 /* 39768 */ // Label 1143: @39768
14379 /* 39768 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1150*/ GIMT_Encode4(39804), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1410 //
14380 /* 39775 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
14381 /* 39778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14382 /* 39782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14383 /* 39786 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4034:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
14384 /* 39786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i8),
14385 /* 39789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14386 /* 39791 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14387 /* 39793 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14388 /* 39796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14389 /* 39802 */ GIR_RootConstrainSelectedInstOperands,
14390 /* 39803 */ // GIR_Coverage, 1410,
14391 /* 39803 */ GIR_EraseRootFromParent_Done,
14392 /* 39804 */ // Label 1150: @39804
14393 /* 39804 */ GIM_Reject,
14394 /* 39805 */ // Label 1144: @39805
14395 /* 39805 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1151*/ GIMT_Encode4(39841), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1413 //
14396 /* 39812 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
14397 /* 39815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14398 /* 39819 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14399 /* 39823 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4034:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
14400 /* 39823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv16i8),
14401 /* 39826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14402 /* 39828 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14403 /* 39830 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14404 /* 39833 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14405 /* 39839 */ GIR_RootConstrainSelectedInstOperands,
14406 /* 39840 */ // GIR_Coverage, 1413,
14407 /* 39840 */ GIR_EraseRootFromParent_Done,
14408 /* 39841 */ // Label 1151: @39841
14409 /* 39841 */ GIM_Reject,
14410 /* 39842 */ // Label 1145: @39842
14411 /* 39842 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1152*/ GIMT_Encode4(39878), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1411 //
14412 /* 39849 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
14413 /* 39852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14414 /* 39856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14415 /* 39860 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4034:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
14416 /* 39860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i16),
14417 /* 39863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14418 /* 39865 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14419 /* 39867 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14420 /* 39870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14421 /* 39876 */ GIR_RootConstrainSelectedInstOperands,
14422 /* 39877 */ // GIR_Coverage, 1411,
14423 /* 39877 */ GIR_EraseRootFromParent_Done,
14424 /* 39878 */ // Label 1152: @39878
14425 /* 39878 */ GIM_Reject,
14426 /* 39879 */ // Label 1146: @39879
14427 /* 39879 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1153*/ GIMT_Encode4(39915), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1414 //
14428 /* 39886 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14429 /* 39889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14430 /* 39893 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14431 /* 39897 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4034:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
14432 /* 39897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i16),
14433 /* 39900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14434 /* 39902 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14435 /* 39904 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14436 /* 39907 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14437 /* 39913 */ GIR_RootConstrainSelectedInstOperands,
14438 /* 39914 */ // GIR_Coverage, 1414,
14439 /* 39914 */ GIR_EraseRootFromParent_Done,
14440 /* 39915 */ // Label 1153: @39915
14441 /* 39915 */ GIM_Reject,
14442 /* 39916 */ // Label 1147: @39916
14443 /* 39916 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1154*/ GIMT_Encode4(39952), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1415 //
14444 /* 39923 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14445 /* 39926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14446 /* 39930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14447 /* 39934 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4034:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
14448 /* 39934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i32),
14449 /* 39937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14450 /* 39939 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14451 /* 39941 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14452 /* 39944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14453 /* 39950 */ GIR_RootConstrainSelectedInstOperands,
14454 /* 39951 */ // GIR_Coverage, 1415,
14455 /* 39951 */ GIR_EraseRootFromParent_Done,
14456 /* 39952 */ // Label 1154: @39952
14457 /* 39952 */ GIM_Reject,
14458 /* 39953 */ // Label 1148: @39953
14459 /* 39953 */ GIM_Reject,
14460 /* 39954 */ // Label 1141: @39954
14461 /* 39954 */ GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(40202),
14462 /* 39959 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
14463 /* 39964 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1160*/ GIMT_Encode4(40201),
14464 /* 39975 */ /*GILLT_v4s16*//*Label 1156*/ GIMT_Encode4(39991),
14465 /* 39979 */ /*GILLT_v8s16*//*Label 1157*/ GIMT_Encode4(40028),
14466 /* 39983 */ /*GILLT_v2s32*//*Label 1158*/ GIMT_Encode4(40065),
14467 /* 39987 */ /*GILLT_v4s32*//*Label 1159*/ GIMT_Encode4(40133),
14468 /* 39991 */ // Label 1156: @39991
14469 /* 39991 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1161*/ GIMT_Encode4(40027), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1448 //
14470 /* 39998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
14471 /* 40001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14472 /* 40005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14473 /* 40009 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4061:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
14474 /* 40009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhd),
14475 /* 40012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14476 /* 40014 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14477 /* 40016 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14478 /* 40019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14479 /* 40025 */ GIR_RootConstrainSelectedInstOperands,
14480 /* 40026 */ // GIR_Coverage, 1448,
14481 /* 40026 */ GIR_EraseRootFromParent_Done,
14482 /* 40027 */ // Label 1161: @40027
14483 /* 40027 */ GIM_Reject,
14484 /* 40028 */ // Label 1157: @40028
14485 /* 40028 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1162*/ GIMT_Encode4(40064), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1449 //
14486 /* 40035 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14487 /* 40038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14488 /* 40042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14489 /* 40046 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4061:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
14490 /* 40046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhq),
14491 /* 40049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14492 /* 40051 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14493 /* 40053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14494 /* 40056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14495 /* 40062 */ GIR_RootConstrainSelectedInstOperands,
14496 /* 40063 */ // GIR_Coverage, 1449,
14497 /* 40063 */ GIR_EraseRootFromParent_Done,
14498 /* 40064 */ // Label 1162: @40064
14499 /* 40064 */ GIM_Reject,
14500 /* 40065 */ // Label 1158: @40065
14501 /* 40065 */ GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(40132),
14502 /* 40070 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
14503 /* 40073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14504 /* 40077 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14505 /* 40081 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1164*/ GIMT_Encode4(40106), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1444 //
14506 /* 40088 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4061:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14507 /* 40088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEd),
14508 /* 40091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14509 /* 40093 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14510 /* 40095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14511 /* 40098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14512 /* 40104 */ GIR_RootConstrainSelectedInstOperands,
14513 /* 40105 */ // GIR_Coverage, 1444,
14514 /* 40105 */ GIR_EraseRootFromParent_Done,
14515 /* 40106 */ // Label 1164: @40106
14516 /* 40106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1165*/ GIMT_Encode4(40131), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1446 //
14517 /* 40113 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4061:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14518 /* 40113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfd),
14519 /* 40116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14520 /* 40118 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14521 /* 40120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14522 /* 40123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14523 /* 40129 */ GIR_RootConstrainSelectedInstOperands,
14524 /* 40130 */ // GIR_Coverage, 1446,
14525 /* 40130 */ GIR_EraseRootFromParent_Done,
14526 /* 40131 */ // Label 1165: @40131
14527 /* 40131 */ GIM_Reject,
14528 /* 40132 */ // Label 1163: @40132
14529 /* 40132 */ GIM_Reject,
14530 /* 40133 */ // Label 1159: @40133
14531 /* 40133 */ GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(40200),
14532 /* 40138 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14533 /* 40141 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14534 /* 40145 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14535 /* 40149 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1167*/ GIMT_Encode4(40174), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1445 //
14536 /* 40156 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4061:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14537 /* 40156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEq),
14538 /* 40159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14539 /* 40161 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14540 /* 40163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14541 /* 40166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14542 /* 40172 */ GIR_RootConstrainSelectedInstOperands,
14543 /* 40173 */ // GIR_Coverage, 1445,
14544 /* 40173 */ GIR_EraseRootFromParent_Done,
14545 /* 40174 */ // Label 1167: @40174
14546 /* 40174 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1168*/ GIMT_Encode4(40199), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1447 //
14547 /* 40181 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4061:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14548 /* 40181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfq),
14549 /* 40184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14550 /* 40186 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14551 /* 40188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14552 /* 40191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14553 /* 40197 */ GIR_RootConstrainSelectedInstOperands,
14554 /* 40198 */ // GIR_Coverage, 1447,
14555 /* 40198 */ GIR_EraseRootFromParent_Done,
14556 /* 40199 */ // Label 1168: @40199
14557 /* 40199 */ GIM_Reject,
14558 /* 40200 */ // Label 1166: @40200
14559 /* 40200 */ GIM_Reject,
14560 /* 40201 */ // Label 1160: @40201
14561 /* 40201 */ GIM_Reject,
14562 /* 40202 */ // Label 1155: @40202
14563 /* 40202 */ GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(40450),
14564 /* 40207 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
14565 /* 40212 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1174*/ GIMT_Encode4(40449),
14566 /* 40223 */ /*GILLT_v4s16*//*Label 1170*/ GIMT_Encode4(40239),
14567 /* 40227 */ /*GILLT_v8s16*//*Label 1171*/ GIMT_Encode4(40276),
14568 /* 40231 */ /*GILLT_v2s32*//*Label 1172*/ GIMT_Encode4(40313),
14569 /* 40235 */ /*GILLT_v4s32*//*Label 1173*/ GIMT_Encode4(40381),
14570 /* 40239 */ // Label 1170: @40239
14571 /* 40239 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1175*/ GIMT_Encode4(40275), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1458 //
14572 /* 40246 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
14573 /* 40249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14574 /* 40253 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14575 /* 40257 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4068:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
14576 /* 40257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhd),
14577 /* 40260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14578 /* 40262 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14579 /* 40264 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14580 /* 40267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14581 /* 40273 */ GIR_RootConstrainSelectedInstOperands,
14582 /* 40274 */ // GIR_Coverage, 1458,
14583 /* 40274 */ GIR_EraseRootFromParent_Done,
14584 /* 40275 */ // Label 1175: @40275
14585 /* 40275 */ GIM_Reject,
14586 /* 40276 */ // Label 1171: @40276
14587 /* 40276 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1176*/ GIMT_Encode4(40312), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1459 //
14588 /* 40283 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14589 /* 40286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14590 /* 40290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14591 /* 40294 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4068:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
14592 /* 40294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhq),
14593 /* 40297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14594 /* 40299 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14595 /* 40301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14596 /* 40304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14597 /* 40310 */ GIR_RootConstrainSelectedInstOperands,
14598 /* 40311 */ // GIR_Coverage, 1459,
14599 /* 40311 */ GIR_EraseRootFromParent_Done,
14600 /* 40312 */ // Label 1176: @40312
14601 /* 40312 */ GIM_Reject,
14602 /* 40313 */ // Label 1172: @40313
14603 /* 40313 */ GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(40380),
14604 /* 40318 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
14605 /* 40321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14606 /* 40325 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14607 /* 40329 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1178*/ GIMT_Encode4(40354), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1454 //
14608 /* 40336 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4068:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14609 /* 40336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEd),
14610 /* 40339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14611 /* 40341 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14612 /* 40343 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14613 /* 40346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14614 /* 40352 */ GIR_RootConstrainSelectedInstOperands,
14615 /* 40353 */ // GIR_Coverage, 1454,
14616 /* 40353 */ GIR_EraseRootFromParent_Done,
14617 /* 40354 */ // Label 1178: @40354
14618 /* 40354 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1179*/ GIMT_Encode4(40379), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1456 //
14619 /* 40361 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4068:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14620 /* 40361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfd),
14621 /* 40364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14622 /* 40366 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14623 /* 40368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14624 /* 40371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14625 /* 40377 */ GIR_RootConstrainSelectedInstOperands,
14626 /* 40378 */ // GIR_Coverage, 1456,
14627 /* 40378 */ GIR_EraseRootFromParent_Done,
14628 /* 40379 */ // Label 1179: @40379
14629 /* 40379 */ GIM_Reject,
14630 /* 40380 */ // Label 1177: @40380
14631 /* 40380 */ GIM_Reject,
14632 /* 40381 */ // Label 1173: @40381
14633 /* 40381 */ GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(40448),
14634 /* 40386 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14635 /* 40389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14636 /* 40393 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14637 /* 40397 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1181*/ GIMT_Encode4(40422), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1455 //
14638 /* 40404 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4068:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14639 /* 40404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEq),
14640 /* 40407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14641 /* 40409 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14642 /* 40411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14643 /* 40414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14644 /* 40420 */ GIR_RootConstrainSelectedInstOperands,
14645 /* 40421 */ // GIR_Coverage, 1455,
14646 /* 40421 */ GIR_EraseRootFromParent_Done,
14647 /* 40422 */ // Label 1181: @40422
14648 /* 40422 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1182*/ GIMT_Encode4(40447), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1457 //
14649 /* 40429 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4068:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14650 /* 40429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfq),
14651 /* 40432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14652 /* 40434 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14653 /* 40436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14654 /* 40439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14655 /* 40445 */ GIR_RootConstrainSelectedInstOperands,
14656 /* 40446 */ // GIR_Coverage, 1457,
14657 /* 40446 */ GIR_EraseRootFromParent_Done,
14658 /* 40447 */ // Label 1182: @40447
14659 /* 40447 */ GIM_Reject,
14660 /* 40448 */ // Label 1180: @40448
14661 /* 40448 */ GIM_Reject,
14662 /* 40449 */ // Label 1174: @40449
14663 /* 40449 */ GIM_Reject,
14664 /* 40450 */ // Label 1169: @40450
14665 /* 40450 */ GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(40718),
14666 /* 40455 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
14667 /* 40460 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1190*/ GIMT_Encode4(40717),
14668 /* 40471 */ /*GILLT_v8s8*//*Label 1184*/ GIMT_Encode4(40495),
14669 /* 40475 */ /*GILLT_v16s8*//*Label 1185*/ GIMT_Encode4(40532),
14670 /* 40479 */ /*GILLT_v4s16*//*Label 1186*/ GIMT_Encode4(40569),
14671 /* 40483 */ /*GILLT_v8s16*//*Label 1187*/ GIMT_Encode4(40606),
14672 /* 40487 */ /*GILLT_v2s32*//*Label 1188*/ GIMT_Encode4(40643),
14673 /* 40491 */ /*GILLT_v4s32*//*Label 1189*/ GIMT_Encode4(40680),
14674 /* 40495 */ // Label 1184: @40495
14675 /* 40495 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1191*/ GIMT_Encode4(40531), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1680 //
14676 /* 40502 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
14677 /* 40505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14678 /* 40509 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14679 /* 40513 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4039:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
14680 /* 40513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i8),
14681 /* 40516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14682 /* 40518 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14683 /* 40520 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14684 /* 40523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14685 /* 40529 */ GIR_RootConstrainSelectedInstOperands,
14686 /* 40530 */ // GIR_Coverage, 1680,
14687 /* 40530 */ GIR_EraseRootFromParent_Done,
14688 /* 40531 */ // Label 1191: @40531
14689 /* 40531 */ GIM_Reject,
14690 /* 40532 */ // Label 1185: @40532
14691 /* 40532 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1192*/ GIMT_Encode4(40568), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1683 //
14692 /* 40539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
14693 /* 40542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14694 /* 40546 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14695 /* 40550 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4039:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
14696 /* 40550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv16i8),
14697 /* 40553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14698 /* 40555 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14699 /* 40557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14700 /* 40560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14701 /* 40566 */ GIR_RootConstrainSelectedInstOperands,
14702 /* 40567 */ // GIR_Coverage, 1683,
14703 /* 40567 */ GIR_EraseRootFromParent_Done,
14704 /* 40568 */ // Label 1192: @40568
14705 /* 40568 */ GIM_Reject,
14706 /* 40569 */ // Label 1186: @40569
14707 /* 40569 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1193*/ GIMT_Encode4(40605), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1681 //
14708 /* 40576 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
14709 /* 40579 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14710 /* 40583 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14711 /* 40587 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4039:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
14712 /* 40587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i16),
14713 /* 40590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14714 /* 40592 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14715 /* 40594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14716 /* 40597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14717 /* 40603 */ GIR_RootConstrainSelectedInstOperands,
14718 /* 40604 */ // GIR_Coverage, 1681,
14719 /* 40604 */ GIR_EraseRootFromParent_Done,
14720 /* 40605 */ // Label 1193: @40605
14721 /* 40605 */ GIM_Reject,
14722 /* 40606 */ // Label 1187: @40606
14723 /* 40606 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1194*/ GIMT_Encode4(40642), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1684 //
14724 /* 40613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14725 /* 40616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14726 /* 40620 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14727 /* 40624 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4039:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
14728 /* 40624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i16),
14729 /* 40627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14730 /* 40629 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14731 /* 40631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14732 /* 40634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14733 /* 40640 */ GIR_RootConstrainSelectedInstOperands,
14734 /* 40641 */ // GIR_Coverage, 1684,
14735 /* 40641 */ GIR_EraseRootFromParent_Done,
14736 /* 40642 */ // Label 1194: @40642
14737 /* 40642 */ GIM_Reject,
14738 /* 40643 */ // Label 1188: @40643
14739 /* 40643 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1195*/ GIMT_Encode4(40679), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1682 //
14740 /* 40650 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
14741 /* 40653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14742 /* 40657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14743 /* 40661 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4039:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14744 /* 40661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv2i32),
14745 /* 40664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14746 /* 40666 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14747 /* 40668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14748 /* 40671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14749 /* 40677 */ GIR_RootConstrainSelectedInstOperands,
14750 /* 40678 */ // GIR_Coverage, 1682,
14751 /* 40678 */ GIR_EraseRootFromParent_Done,
14752 /* 40679 */ // Label 1195: @40679
14753 /* 40679 */ GIM_Reject,
14754 /* 40680 */ // Label 1189: @40680
14755 /* 40680 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1196*/ GIMT_Encode4(40716), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1685 //
14756 /* 40687 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14757 /* 40690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14758 /* 40694 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14759 /* 40698 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4039:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14760 /* 40698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i32),
14761 /* 40701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14762 /* 40703 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14763 /* 40705 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14764 /* 40708 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14765 /* 40714 */ GIR_RootConstrainSelectedInstOperands,
14766 /* 40715 */ // GIR_Coverage, 1685,
14767 /* 40715 */ GIR_EraseRootFromParent_Done,
14768 /* 40716 */ // Label 1196: @40716
14769 /* 40716 */ GIM_Reject,
14770 /* 40717 */ // Label 1190: @40717
14771 /* 40717 */ GIM_Reject,
14772 /* 40718 */ // Label 1183: @40718
14773 /* 40718 */ GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(40986),
14774 /* 40723 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
14775 /* 40728 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1204*/ GIMT_Encode4(40985),
14776 /* 40739 */ /*GILLT_v8s8*//*Label 1198*/ GIMT_Encode4(40763),
14777 /* 40743 */ /*GILLT_v16s8*//*Label 1199*/ GIMT_Encode4(40800),
14778 /* 40747 */ /*GILLT_v4s16*//*Label 1200*/ GIMT_Encode4(40837),
14779 /* 40751 */ /*GILLT_v8s16*//*Label 1201*/ GIMT_Encode4(40874),
14780 /* 40755 */ /*GILLT_v2s32*//*Label 1202*/ GIMT_Encode4(40911),
14781 /* 40759 */ /*GILLT_v4s32*//*Label 1203*/ GIMT_Encode4(40948),
14782 /* 40763 */ // Label 1198: @40763
14783 /* 40763 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1205*/ GIMT_Encode4(40799), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1696 //
14784 /* 40770 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
14785 /* 40773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14786 /* 40777 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14787 /* 40781 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4045:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQNEGv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
14788 /* 40781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i8),
14789 /* 40784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14790 /* 40786 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14791 /* 40788 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14792 /* 40791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14793 /* 40797 */ GIR_RootConstrainSelectedInstOperands,
14794 /* 40798 */ // GIR_Coverage, 1696,
14795 /* 40798 */ GIR_EraseRootFromParent_Done,
14796 /* 40799 */ // Label 1205: @40799
14797 /* 40799 */ GIM_Reject,
14798 /* 40800 */ // Label 1199: @40800
14799 /* 40800 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1206*/ GIMT_Encode4(40836), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1699 //
14800 /* 40807 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
14801 /* 40810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14802 /* 40814 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14803 /* 40818 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4045:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQNEGv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
14804 /* 40818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv16i8),
14805 /* 40821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14806 /* 40823 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14807 /* 40825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14808 /* 40828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14809 /* 40834 */ GIR_RootConstrainSelectedInstOperands,
14810 /* 40835 */ // GIR_Coverage, 1699,
14811 /* 40835 */ GIR_EraseRootFromParent_Done,
14812 /* 40836 */ // Label 1206: @40836
14813 /* 40836 */ GIM_Reject,
14814 /* 40837 */ // Label 1200: @40837
14815 /* 40837 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1207*/ GIMT_Encode4(40873), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1697 //
14816 /* 40844 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
14817 /* 40847 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14818 /* 40851 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14819 /* 40855 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4045:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQNEGv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
14820 /* 40855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i16),
14821 /* 40858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14822 /* 40860 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14823 /* 40862 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14824 /* 40865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14825 /* 40871 */ GIR_RootConstrainSelectedInstOperands,
14826 /* 40872 */ // GIR_Coverage, 1697,
14827 /* 40872 */ GIR_EraseRootFromParent_Done,
14828 /* 40873 */ // Label 1207: @40873
14829 /* 40873 */ GIM_Reject,
14830 /* 40874 */ // Label 1201: @40874
14831 /* 40874 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1208*/ GIMT_Encode4(40910), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1700 //
14832 /* 40881 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14833 /* 40884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14834 /* 40888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14835 /* 40892 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4045:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQNEGv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
14836 /* 40892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i16),
14837 /* 40895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14838 /* 40897 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14839 /* 40899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14840 /* 40902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14841 /* 40908 */ GIR_RootConstrainSelectedInstOperands,
14842 /* 40909 */ // GIR_Coverage, 1700,
14843 /* 40909 */ GIR_EraseRootFromParent_Done,
14844 /* 40910 */ // Label 1208: @40910
14845 /* 40910 */ GIM_Reject,
14846 /* 40911 */ // Label 1202: @40911
14847 /* 40911 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1209*/ GIMT_Encode4(40947), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1698 //
14848 /* 40918 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
14849 /* 40921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14850 /* 40925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14851 /* 40929 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4045:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQNEGv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
14852 /* 40929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv2i32),
14853 /* 40932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14854 /* 40934 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14855 /* 40936 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14856 /* 40939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14857 /* 40945 */ GIR_RootConstrainSelectedInstOperands,
14858 /* 40946 */ // GIR_Coverage, 1698,
14859 /* 40946 */ GIR_EraseRootFromParent_Done,
14860 /* 40947 */ // Label 1209: @40947
14861 /* 40947 */ GIM_Reject,
14862 /* 40948 */ // Label 1203: @40948
14863 /* 40948 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1210*/ GIMT_Encode4(40984), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1701 //
14864 /* 40955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14865 /* 40958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14866 /* 40962 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14867 /* 40966 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4045:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQNEGv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
14868 /* 40966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i32),
14869 /* 40969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14870 /* 40971 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14871 /* 40973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14872 /* 40976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14873 /* 40982 */ GIR_RootConstrainSelectedInstOperands,
14874 /* 40983 */ // GIR_Coverage, 1701,
14875 /* 40983 */ GIR_EraseRootFromParent_Done,
14876 /* 40984 */ // Label 1210: @40984
14877 /* 40984 */ GIM_Reject,
14878 /* 40985 */ // Label 1204: @40985
14879 /* 40985 */ GIM_Reject,
14880 /* 40986 */ // Label 1197: @40986
14881 /* 40986 */ GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(41139),
14882 /* 40991 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns),
14883 /* 40996 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1215*/ GIMT_Encode4(41138),
14884 /* 41007 */ /*GILLT_v8s8*//*Label 1212*/ GIMT_Encode4(41027), GIMT_Encode4(0),
14885 /* 41015 */ /*GILLT_v4s16*//*Label 1213*/ GIMT_Encode4(41064), GIMT_Encode4(0),
14886 /* 41023 */ /*GILLT_v2s32*//*Label 1214*/ GIMT_Encode4(41101),
14887 /* 41027 */ // Label 1212: @41027
14888 /* 41027 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1216*/ GIMT_Encode4(41063), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1751 //
14889 /* 41034 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14890 /* 41037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14891 /* 41041 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14892 /* 41045 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4042:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
14893 /* 41045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv8i8),
14894 /* 41048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14895 /* 41050 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14896 /* 41052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14897 /* 41055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14898 /* 41061 */ GIR_RootConstrainSelectedInstOperands,
14899 /* 41062 */ // GIR_Coverage, 1751,
14900 /* 41062 */ GIR_EraseRootFromParent_Done,
14901 /* 41063 */ // Label 1216: @41063
14902 /* 41063 */ GIM_Reject,
14903 /* 41064 */ // Label 1213: @41064
14904 /* 41064 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1217*/ GIMT_Encode4(41100), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1752 //
14905 /* 41071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14906 /* 41074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14907 /* 41078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14908 /* 41082 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4042:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
14909 /* 41082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv4i16),
14910 /* 41085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14911 /* 41087 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14912 /* 41089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14913 /* 41092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14914 /* 41098 */ GIR_RootConstrainSelectedInstOperands,
14915 /* 41099 */ // GIR_Coverage, 1752,
14916 /* 41099 */ GIR_EraseRootFromParent_Done,
14917 /* 41100 */ // Label 1217: @41100
14918 /* 41100 */ GIM_Reject,
14919 /* 41101 */ // Label 1214: @41101
14920 /* 41101 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1218*/ GIMT_Encode4(41137), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1753 //
14921 /* 41108 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
14922 /* 41111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14923 /* 41115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14924 /* 41119 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4042:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
14925 /* 41119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv2i32),
14926 /* 41122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14927 /* 41124 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14928 /* 41126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14929 /* 41129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14930 /* 41135 */ GIR_RootConstrainSelectedInstOperands,
14931 /* 41136 */ // GIR_Coverage, 1753,
14932 /* 41136 */ GIR_EraseRootFromParent_Done,
14933 /* 41137 */ // Label 1218: @41137
14934 /* 41137 */ GIM_Reject,
14935 /* 41138 */ // Label 1215: @41138
14936 /* 41138 */ GIM_Reject,
14937 /* 41139 */ // Label 1211: @41139
14938 /* 41139 */ GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(41292),
14939 /* 41144 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu),
14940 /* 41149 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1223*/ GIMT_Encode4(41291),
14941 /* 41160 */ /*GILLT_v8s8*//*Label 1220*/ GIMT_Encode4(41180), GIMT_Encode4(0),
14942 /* 41168 */ /*GILLT_v4s16*//*Label 1221*/ GIMT_Encode4(41217), GIMT_Encode4(0),
14943 /* 41176 */ /*GILLT_v2s32*//*Label 1222*/ GIMT_Encode4(41254),
14944 /* 41180 */ // Label 1220: @41180
14945 /* 41180 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1224*/ GIMT_Encode4(41216), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1754 //
14946 /* 41187 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
14947 /* 41190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14948 /* 41194 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14949 /* 41198 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4044:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
14950 /* 41198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv8i8),
14951 /* 41201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14952 /* 41203 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14953 /* 41205 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14954 /* 41208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14955 /* 41214 */ GIR_RootConstrainSelectedInstOperands,
14956 /* 41215 */ // GIR_Coverage, 1754,
14957 /* 41215 */ GIR_EraseRootFromParent_Done,
14958 /* 41216 */ // Label 1224: @41216
14959 /* 41216 */ GIM_Reject,
14960 /* 41217 */ // Label 1221: @41217
14961 /* 41217 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1225*/ GIMT_Encode4(41253), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1755 //
14962 /* 41224 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
14963 /* 41227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14964 /* 41231 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14965 /* 41235 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4044:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
14966 /* 41235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv4i16),
14967 /* 41238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14968 /* 41240 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14969 /* 41242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14970 /* 41245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14971 /* 41251 */ GIR_RootConstrainSelectedInstOperands,
14972 /* 41252 */ // GIR_Coverage, 1755,
14973 /* 41252 */ GIR_EraseRootFromParent_Done,
14974 /* 41253 */ // Label 1225: @41253
14975 /* 41253 */ GIM_Reject,
14976 /* 41254 */ // Label 1222: @41254
14977 /* 41254 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1226*/ GIMT_Encode4(41290), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1756 //
14978 /* 41261 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
14979 /* 41264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14980 /* 41268 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14981 /* 41272 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4044:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
14982 /* 41272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv2i32),
14983 /* 41275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14984 /* 41277 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
14985 /* 41279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14986 /* 41282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14987 /* 41288 */ GIR_RootConstrainSelectedInstOperands,
14988 /* 41289 */ // GIR_Coverage, 1756,
14989 /* 41289 */ GIR_EraseRootFromParent_Done,
14990 /* 41290 */ // Label 1226: @41290
14991 /* 41290 */ GIM_Reject,
14992 /* 41291 */ // Label 1223: @41291
14993 /* 41291 */ GIM_Reject,
14994 /* 41292 */ // Label 1219: @41292
14995 /* 41292 */ GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(41445),
14996 /* 41297 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu),
14997 /* 41302 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1231*/ GIMT_Encode4(41444),
14998 /* 41313 */ /*GILLT_v8s8*//*Label 1228*/ GIMT_Encode4(41333), GIMT_Encode4(0),
14999 /* 41321 */ /*GILLT_v4s16*//*Label 1229*/ GIMT_Encode4(41370), GIMT_Encode4(0),
15000 /* 41329 */ /*GILLT_v2s32*//*Label 1230*/ GIMT_Encode4(41407),
15001 /* 41333 */ // Label 1228: @41333
15002 /* 41333 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1232*/ GIMT_Encode4(41369), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1757 //
15003 /* 41340 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15004 /* 41343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15005 /* 41347 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15006 /* 41351 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4043:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
15007 /* 41351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv8i8),
15008 /* 41354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15009 /* 41356 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15010 /* 41358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15011 /* 41361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15012 /* 41367 */ GIR_RootConstrainSelectedInstOperands,
15013 /* 41368 */ // GIR_Coverage, 1757,
15014 /* 41368 */ GIR_EraseRootFromParent_Done,
15015 /* 41369 */ // Label 1232: @41369
15016 /* 41369 */ GIM_Reject,
15017 /* 41370 */ // Label 1229: @41370
15018 /* 41370 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1233*/ GIMT_Encode4(41406), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1758 //
15019 /* 41377 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15020 /* 41380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15021 /* 41384 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15022 /* 41388 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4043:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
15023 /* 41388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv4i16),
15024 /* 41391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15025 /* 41393 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15026 /* 41395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15027 /* 41398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15028 /* 41404 */ GIR_RootConstrainSelectedInstOperands,
15029 /* 41405 */ // GIR_Coverage, 1758,
15030 /* 41405 */ GIR_EraseRootFromParent_Done,
15031 /* 41406 */ // Label 1233: @41406
15032 /* 41406 */ GIM_Reject,
15033 /* 41407 */ // Label 1230: @41407
15034 /* 41407 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1234*/ GIMT_Encode4(41443), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1759 //
15035 /* 41414 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
15036 /* 41417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15037 /* 41421 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15038 /* 41425 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4043:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
15039 /* 41425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv2i32),
15040 /* 41428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15041 /* 41430 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15042 /* 41432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15043 /* 41435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15044 /* 41441 */ GIR_RootConstrainSelectedInstOperands,
15045 /* 41442 */ // GIR_Coverage, 1759,
15046 /* 41442 */ GIR_EraseRootFromParent_Done,
15047 /* 41443 */ // Label 1234: @41443
15048 /* 41443 */ GIM_Reject,
15049 /* 41444 */ // Label 1231: @41444
15050 /* 41444 */ GIM_Reject,
15051 /* 41445 */ // Label 1227: @41445
15052 /* 41445 */ GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(41531),
15053 /* 41450 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
15054 /* 41455 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1238*/ GIMT_Encode4(41530),
15055 /* 41466 */ /*GILLT_v2s32*//*Label 1236*/ GIMT_Encode4(41474),
15056 /* 41470 */ /*GILLT_v4s32*//*Label 1237*/ GIMT_Encode4(41502),
15057 /* 41474 */ // Label 1236: @41474
15058 /* 41474 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1239*/ GIMT_Encode4(41501), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1782 //
15059 /* 41481 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15060 /* 41484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15061 /* 41488 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15062 /* 41492 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3987:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15063 /* 41492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDf),
15064 /* 41495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15065 /* 41497 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15066 /* 41499 */ GIR_RootConstrainSelectedInstOperands,
15067 /* 41500 */ // GIR_Coverage, 1782,
15068 /* 41500 */ GIR_EraseRootFromParent_Done,
15069 /* 41501 */ // Label 1239: @41501
15070 /* 41501 */ GIM_Reject,
15071 /* 41502 */ // Label 1237: @41502
15072 /* 41502 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1240*/ GIMT_Encode4(41529), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1783 //
15073 /* 41509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15074 /* 41512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15075 /* 41516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15076 /* 41520 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3987:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15077 /* 41520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQf),
15078 /* 41523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15079 /* 41525 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15080 /* 41527 */ GIR_RootConstrainSelectedInstOperands,
15081 /* 41528 */ // GIR_Coverage, 1783,
15082 /* 41528 */ GIR_EraseRootFromParent_Done,
15083 /* 41529 */ // Label 1240: @41529
15084 /* 41529 */ GIM_Reject,
15085 /* 41530 */ // Label 1238: @41530
15086 /* 41530 */ GIM_Reject,
15087 /* 41531 */ // Label 1235: @41531
15088 /* 41531 */ GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(41617),
15089 /* 41536 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
15090 /* 41541 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1244*/ GIMT_Encode4(41616),
15091 /* 41552 */ /*GILLT_v2s32*//*Label 1242*/ GIMT_Encode4(41560),
15092 /* 41556 */ /*GILLT_v4s32*//*Label 1243*/ GIMT_Encode4(41588),
15093 /* 41560 */ // Label 1242: @41560
15094 /* 41560 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1245*/ GIMT_Encode4(41587), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1784 //
15095 /* 41567 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15096 /* 41570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15097 /* 41574 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15098 /* 41578 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3988:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15099 /* 41578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDf),
15100 /* 41581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15101 /* 41583 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15102 /* 41585 */ GIR_RootConstrainSelectedInstOperands,
15103 /* 41586 */ // GIR_Coverage, 1784,
15104 /* 41586 */ GIR_EraseRootFromParent_Done,
15105 /* 41587 */ // Label 1245: @41587
15106 /* 41587 */ GIM_Reject,
15107 /* 41588 */ // Label 1243: @41588
15108 /* 41588 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1246*/ GIMT_Encode4(41615), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1785 //
15109 /* 41595 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15110 /* 41598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15111 /* 41602 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15112 /* 41606 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3988:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15113 /* 41606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQf),
15114 /* 41609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15115 /* 41611 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15116 /* 41613 */ GIR_RootConstrainSelectedInstOperands,
15117 /* 41614 */ // GIR_Coverage, 1785,
15118 /* 41614 */ GIR_EraseRootFromParent_Done,
15119 /* 41615 */ // Label 1246: @41615
15120 /* 41615 */ GIM_Reject,
15121 /* 41616 */ // Label 1244: @41616
15122 /* 41616 */ GIM_Reject,
15123 /* 41617 */ // Label 1241: @41617
15124 /* 41617 */ GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(41703),
15125 /* 41622 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
15126 /* 41627 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1250*/ GIMT_Encode4(41702),
15127 /* 41638 */ /*GILLT_v4s16*//*Label 1248*/ GIMT_Encode4(41646),
15128 /* 41642 */ /*GILLT_v8s16*//*Label 1249*/ GIMT_Encode4(41674),
15129 /* 41646 */ // Label 1248: @41646
15130 /* 41646 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1251*/ GIMT_Encode4(41673), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1786 //
15131 /* 41653 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15132 /* 41656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15133 /* 41660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15134 /* 41664 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3987:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15135 /* 41664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDh),
15136 /* 41667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15137 /* 41669 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15138 /* 41671 */ GIR_RootConstrainSelectedInstOperands,
15139 /* 41672 */ // GIR_Coverage, 1786,
15140 /* 41672 */ GIR_EraseRootFromParent_Done,
15141 /* 41673 */ // Label 1251: @41673
15142 /* 41673 */ GIM_Reject,
15143 /* 41674 */ // Label 1249: @41674
15144 /* 41674 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1252*/ GIMT_Encode4(41701), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1787 //
15145 /* 41681 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15146 /* 41684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15147 /* 41688 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15148 /* 41692 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3987:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15149 /* 41692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQh),
15150 /* 41695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15151 /* 41697 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15152 /* 41699 */ GIR_RootConstrainSelectedInstOperands,
15153 /* 41700 */ // GIR_Coverage, 1787,
15154 /* 41700 */ GIR_EraseRootFromParent_Done,
15155 /* 41701 */ // Label 1252: @41701
15156 /* 41701 */ GIM_Reject,
15157 /* 41702 */ // Label 1250: @41702
15158 /* 41702 */ GIM_Reject,
15159 /* 41703 */ // Label 1247: @41703
15160 /* 41703 */ GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(41789),
15161 /* 41708 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
15162 /* 41713 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1256*/ GIMT_Encode4(41788),
15163 /* 41724 */ /*GILLT_v4s16*//*Label 1254*/ GIMT_Encode4(41732),
15164 /* 41728 */ /*GILLT_v8s16*//*Label 1255*/ GIMT_Encode4(41760),
15165 /* 41732 */ // Label 1254: @41732
15166 /* 41732 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1257*/ GIMT_Encode4(41759), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1788 //
15167 /* 41739 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15168 /* 41742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15169 /* 41746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15170 /* 41750 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3988:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15171 /* 41750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDh),
15172 /* 41753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15173 /* 41755 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15174 /* 41757 */ GIR_RootConstrainSelectedInstOperands,
15175 /* 41758 */ // GIR_Coverage, 1788,
15176 /* 41758 */ GIR_EraseRootFromParent_Done,
15177 /* 41759 */ // Label 1257: @41759
15178 /* 41759 */ GIM_Reject,
15179 /* 41760 */ // Label 1255: @41760
15180 /* 41760 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1258*/ GIMT_Encode4(41787), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1789 //
15181 /* 41767 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15182 /* 41770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15183 /* 41774 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15184 /* 41778 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3988:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15185 /* 41778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQh),
15186 /* 41781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15187 /* 41783 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15188 /* 41785 */ GIR_RootConstrainSelectedInstOperands,
15189 /* 41786 */ // GIR_Coverage, 1789,
15190 /* 41786 */ GIR_EraseRootFromParent_Done,
15191 /* 41787 */ // Label 1258: @41787
15192 /* 41787 */ GIM_Reject,
15193 /* 41788 */ // Label 1256: @41788
15194 /* 41788 */ GIM_Reject,
15195 /* 41789 */ // Label 1253: @41789
15196 /* 41789 */ GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(41875),
15197 /* 41794 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
15198 /* 41799 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1262*/ GIMT_Encode4(41874),
15199 /* 41810 */ /*GILLT_v2s32*//*Label 1260*/ GIMT_Encode4(41818),
15200 /* 41814 */ /*GILLT_v4s32*//*Label 1261*/ GIMT_Encode4(41846),
15201 /* 41818 */ // Label 1260: @41818
15202 /* 41818 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1263*/ GIMT_Encode4(41845), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1790 //
15203 /* 41825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15204 /* 41828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15205 /* 41832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15206 /* 41836 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3999:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15207 /* 41836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDf),
15208 /* 41839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15209 /* 41841 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15210 /* 41843 */ GIR_RootConstrainSelectedInstOperands,
15211 /* 41844 */ // GIR_Coverage, 1790,
15212 /* 41844 */ GIR_EraseRootFromParent_Done,
15213 /* 41845 */ // Label 1263: @41845
15214 /* 41845 */ GIM_Reject,
15215 /* 41846 */ // Label 1261: @41846
15216 /* 41846 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1264*/ GIMT_Encode4(41873), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1791 //
15217 /* 41853 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15218 /* 41856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15219 /* 41860 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15220 /* 41864 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3999:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15221 /* 41864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQf),
15222 /* 41867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15223 /* 41869 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15224 /* 41871 */ GIR_RootConstrainSelectedInstOperands,
15225 /* 41872 */ // GIR_Coverage, 1791,
15226 /* 41872 */ GIR_EraseRootFromParent_Done,
15227 /* 41873 */ // Label 1264: @41873
15228 /* 41873 */ GIM_Reject,
15229 /* 41874 */ // Label 1262: @41874
15230 /* 41874 */ GIM_Reject,
15231 /* 41875 */ // Label 1259: @41875
15232 /* 41875 */ GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(41961),
15233 /* 41880 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
15234 /* 41885 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1268*/ GIMT_Encode4(41960),
15235 /* 41896 */ /*GILLT_v2s32*//*Label 1266*/ GIMT_Encode4(41904),
15236 /* 41900 */ /*GILLT_v4s32*//*Label 1267*/ GIMT_Encode4(41932),
15237 /* 41904 */ // Label 1266: @41904
15238 /* 41904 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1269*/ GIMT_Encode4(41931), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1792 //
15239 /* 41911 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15240 /* 41914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15241 /* 41918 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15242 /* 41922 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4000:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15243 /* 41922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDf),
15244 /* 41925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15245 /* 41927 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15246 /* 41929 */ GIR_RootConstrainSelectedInstOperands,
15247 /* 41930 */ // GIR_Coverage, 1792,
15248 /* 41930 */ GIR_EraseRootFromParent_Done,
15249 /* 41931 */ // Label 1269: @41931
15250 /* 41931 */ GIM_Reject,
15251 /* 41932 */ // Label 1267: @41932
15252 /* 41932 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1270*/ GIMT_Encode4(41959), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1793 //
15253 /* 41939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15254 /* 41942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15255 /* 41946 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15256 /* 41950 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4000:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15257 /* 41950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQf),
15258 /* 41953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15259 /* 41955 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15260 /* 41957 */ GIR_RootConstrainSelectedInstOperands,
15261 /* 41958 */ // GIR_Coverage, 1793,
15262 /* 41958 */ GIR_EraseRootFromParent_Done,
15263 /* 41959 */ // Label 1270: @41959
15264 /* 41959 */ GIM_Reject,
15265 /* 41960 */ // Label 1268: @41960
15266 /* 41960 */ GIM_Reject,
15267 /* 41961 */ // Label 1265: @41961
15268 /* 41961 */ GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(42047),
15269 /* 41966 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
15270 /* 41971 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1274*/ GIMT_Encode4(42046),
15271 /* 41982 */ /*GILLT_v4s16*//*Label 1272*/ GIMT_Encode4(41990),
15272 /* 41986 */ /*GILLT_v8s16*//*Label 1273*/ GIMT_Encode4(42018),
15273 /* 41990 */ // Label 1272: @41990
15274 /* 41990 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1275*/ GIMT_Encode4(42017), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1794 //
15275 /* 41997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15276 /* 42000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15277 /* 42004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15278 /* 42008 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3999:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15279 /* 42008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDh),
15280 /* 42011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15281 /* 42013 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15282 /* 42015 */ GIR_RootConstrainSelectedInstOperands,
15283 /* 42016 */ // GIR_Coverage, 1794,
15284 /* 42016 */ GIR_EraseRootFromParent_Done,
15285 /* 42017 */ // Label 1275: @42017
15286 /* 42017 */ GIM_Reject,
15287 /* 42018 */ // Label 1273: @42018
15288 /* 42018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1276*/ GIMT_Encode4(42045), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1795 //
15289 /* 42025 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15290 /* 42028 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15291 /* 42032 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15292 /* 42036 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3999:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15293 /* 42036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQh),
15294 /* 42039 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15295 /* 42041 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15296 /* 42043 */ GIR_RootConstrainSelectedInstOperands,
15297 /* 42044 */ // GIR_Coverage, 1795,
15298 /* 42044 */ GIR_EraseRootFromParent_Done,
15299 /* 42045 */ // Label 1276: @42045
15300 /* 42045 */ GIM_Reject,
15301 /* 42046 */ // Label 1274: @42046
15302 /* 42046 */ GIM_Reject,
15303 /* 42047 */ // Label 1271: @42047
15304 /* 42047 */ GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(42133),
15305 /* 42052 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
15306 /* 42057 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1280*/ GIMT_Encode4(42132),
15307 /* 42068 */ /*GILLT_v4s16*//*Label 1278*/ GIMT_Encode4(42076),
15308 /* 42072 */ /*GILLT_v8s16*//*Label 1279*/ GIMT_Encode4(42104),
15309 /* 42076 */ // Label 1278: @42076
15310 /* 42076 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1281*/ GIMT_Encode4(42103), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1796 //
15311 /* 42083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15312 /* 42086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15313 /* 42090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15314 /* 42094 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4000:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15315 /* 42094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDh),
15316 /* 42097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15317 /* 42099 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15318 /* 42101 */ GIR_RootConstrainSelectedInstOperands,
15319 /* 42102 */ // GIR_Coverage, 1796,
15320 /* 42102 */ GIR_EraseRootFromParent_Done,
15321 /* 42103 */ // Label 1281: @42103
15322 /* 42103 */ GIM_Reject,
15323 /* 42104 */ // Label 1279: @42104
15324 /* 42104 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1282*/ GIMT_Encode4(42131), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1797 //
15325 /* 42111 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15326 /* 42114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15327 /* 42118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15328 /* 42122 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4000:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15329 /* 42122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQh),
15330 /* 42125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15331 /* 42127 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15332 /* 42129 */ GIR_RootConstrainSelectedInstOperands,
15333 /* 42130 */ // GIR_Coverage, 1797,
15334 /* 42130 */ GIR_EraseRootFromParent_Done,
15335 /* 42131 */ // Label 1282: @42131
15336 /* 42131 */ GIM_Reject,
15337 /* 42132 */ // Label 1280: @42132
15338 /* 42132 */ GIM_Reject,
15339 /* 42133 */ // Label 1277: @42133
15340 /* 42133 */ GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(42219),
15341 /* 42138 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
15342 /* 42143 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1286*/ GIMT_Encode4(42218),
15343 /* 42154 */ /*GILLT_v2s32*//*Label 1284*/ GIMT_Encode4(42162),
15344 /* 42158 */ /*GILLT_v4s32*//*Label 1285*/ GIMT_Encode4(42190),
15345 /* 42162 */ // Label 1284: @42162
15346 /* 42162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1287*/ GIMT_Encode4(42189), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1798 //
15347 /* 42169 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15348 /* 42172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15349 /* 42176 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15350 /* 42180 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4001:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15351 /* 42180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDf),
15352 /* 42183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15353 /* 42185 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15354 /* 42187 */ GIR_RootConstrainSelectedInstOperands,
15355 /* 42188 */ // GIR_Coverage, 1798,
15356 /* 42188 */ GIR_EraseRootFromParent_Done,
15357 /* 42189 */ // Label 1287: @42189
15358 /* 42189 */ GIM_Reject,
15359 /* 42190 */ // Label 1285: @42190
15360 /* 42190 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1288*/ GIMT_Encode4(42217), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1799 //
15361 /* 42197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15362 /* 42200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15363 /* 42204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15364 /* 42208 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4001:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15365 /* 42208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQf),
15366 /* 42211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15367 /* 42213 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15368 /* 42215 */ GIR_RootConstrainSelectedInstOperands,
15369 /* 42216 */ // GIR_Coverage, 1799,
15370 /* 42216 */ GIR_EraseRootFromParent_Done,
15371 /* 42217 */ // Label 1288: @42217
15372 /* 42217 */ GIM_Reject,
15373 /* 42218 */ // Label 1286: @42218
15374 /* 42218 */ GIM_Reject,
15375 /* 42219 */ // Label 1283: @42219
15376 /* 42219 */ GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(42305),
15377 /* 42224 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
15378 /* 42229 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1292*/ GIMT_Encode4(42304),
15379 /* 42240 */ /*GILLT_v2s32*//*Label 1290*/ GIMT_Encode4(42248),
15380 /* 42244 */ /*GILLT_v4s32*//*Label 1291*/ GIMT_Encode4(42276),
15381 /* 42248 */ // Label 1290: @42248
15382 /* 42248 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1293*/ GIMT_Encode4(42275), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1800 //
15383 /* 42255 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15384 /* 42258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15385 /* 42262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15386 /* 42266 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4002:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15387 /* 42266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDf),
15388 /* 42269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15389 /* 42271 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15390 /* 42273 */ GIR_RootConstrainSelectedInstOperands,
15391 /* 42274 */ // GIR_Coverage, 1800,
15392 /* 42274 */ GIR_EraseRootFromParent_Done,
15393 /* 42275 */ // Label 1293: @42275
15394 /* 42275 */ GIM_Reject,
15395 /* 42276 */ // Label 1291: @42276
15396 /* 42276 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1294*/ GIMT_Encode4(42303), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1801 //
15397 /* 42283 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15398 /* 42286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15399 /* 42290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15400 /* 42294 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4002:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15401 /* 42294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQf),
15402 /* 42297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15403 /* 42299 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15404 /* 42301 */ GIR_RootConstrainSelectedInstOperands,
15405 /* 42302 */ // GIR_Coverage, 1801,
15406 /* 42302 */ GIR_EraseRootFromParent_Done,
15407 /* 42303 */ // Label 1294: @42303
15408 /* 42303 */ GIM_Reject,
15409 /* 42304 */ // Label 1292: @42304
15410 /* 42304 */ GIM_Reject,
15411 /* 42305 */ // Label 1289: @42305
15412 /* 42305 */ GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(42391),
15413 /* 42310 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
15414 /* 42315 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1298*/ GIMT_Encode4(42390),
15415 /* 42326 */ /*GILLT_v4s16*//*Label 1296*/ GIMT_Encode4(42334),
15416 /* 42330 */ /*GILLT_v8s16*//*Label 1297*/ GIMT_Encode4(42362),
15417 /* 42334 */ // Label 1296: @42334
15418 /* 42334 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1299*/ GIMT_Encode4(42361), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1802 //
15419 /* 42341 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15420 /* 42344 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15421 /* 42348 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15422 /* 42352 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4001:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15423 /* 42352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDh),
15424 /* 42355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15425 /* 42357 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15426 /* 42359 */ GIR_RootConstrainSelectedInstOperands,
15427 /* 42360 */ // GIR_Coverage, 1802,
15428 /* 42360 */ GIR_EraseRootFromParent_Done,
15429 /* 42361 */ // Label 1299: @42361
15430 /* 42361 */ GIM_Reject,
15431 /* 42362 */ // Label 1297: @42362
15432 /* 42362 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1300*/ GIMT_Encode4(42389), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1803 //
15433 /* 42369 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15434 /* 42372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15435 /* 42376 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15436 /* 42380 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4001:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15437 /* 42380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQh),
15438 /* 42383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15439 /* 42385 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15440 /* 42387 */ GIR_RootConstrainSelectedInstOperands,
15441 /* 42388 */ // GIR_Coverage, 1803,
15442 /* 42388 */ GIR_EraseRootFromParent_Done,
15443 /* 42389 */ // Label 1300: @42389
15444 /* 42389 */ GIM_Reject,
15445 /* 42390 */ // Label 1298: @42390
15446 /* 42390 */ GIM_Reject,
15447 /* 42391 */ // Label 1295: @42391
15448 /* 42391 */ GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(42477),
15449 /* 42396 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
15450 /* 42401 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1304*/ GIMT_Encode4(42476),
15451 /* 42412 */ /*GILLT_v4s16*//*Label 1302*/ GIMT_Encode4(42420),
15452 /* 42416 */ /*GILLT_v8s16*//*Label 1303*/ GIMT_Encode4(42448),
15453 /* 42420 */ // Label 1302: @42420
15454 /* 42420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1305*/ GIMT_Encode4(42447), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1804 //
15455 /* 42427 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15456 /* 42430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15457 /* 42434 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15458 /* 42438 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4002:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15459 /* 42438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDh),
15460 /* 42441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15461 /* 42443 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15462 /* 42445 */ GIR_RootConstrainSelectedInstOperands,
15463 /* 42446 */ // GIR_Coverage, 1804,
15464 /* 42446 */ GIR_EraseRootFromParent_Done,
15465 /* 42447 */ // Label 1305: @42447
15466 /* 42447 */ GIM_Reject,
15467 /* 42448 */ // Label 1303: @42448
15468 /* 42448 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1306*/ GIMT_Encode4(42475), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1805 //
15469 /* 42455 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15470 /* 42458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15471 /* 42462 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15472 /* 42466 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4002:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15473 /* 42466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQh),
15474 /* 42469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15475 /* 42471 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15476 /* 42473 */ GIR_RootConstrainSelectedInstOperands,
15477 /* 42474 */ // GIR_Coverage, 1805,
15478 /* 42474 */ GIR_EraseRootFromParent_Done,
15479 /* 42475 */ // Label 1306: @42475
15480 /* 42475 */ GIM_Reject,
15481 /* 42476 */ // Label 1304: @42476
15482 /* 42476 */ GIM_Reject,
15483 /* 42477 */ // Label 1301: @42477
15484 /* 42477 */ GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(42563),
15485 /* 42482 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
15486 /* 42487 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1310*/ GIMT_Encode4(42562),
15487 /* 42498 */ /*GILLT_v2s32*//*Label 1308*/ GIMT_Encode4(42506),
15488 /* 42502 */ /*GILLT_v4s32*//*Label 1309*/ GIMT_Encode4(42534),
15489 /* 42506 */ // Label 1308: @42506
15490 /* 42506 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1311*/ GIMT_Encode4(42533), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1806 //
15491 /* 42513 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15492 /* 42516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15493 /* 42520 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15494 /* 42524 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3997:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15495 /* 42524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDf),
15496 /* 42527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15497 /* 42529 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15498 /* 42531 */ GIR_RootConstrainSelectedInstOperands,
15499 /* 42532 */ // GIR_Coverage, 1806,
15500 /* 42532 */ GIR_EraseRootFromParent_Done,
15501 /* 42533 */ // Label 1311: @42533
15502 /* 42533 */ GIM_Reject,
15503 /* 42534 */ // Label 1309: @42534
15504 /* 42534 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1312*/ GIMT_Encode4(42561), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1807 //
15505 /* 42541 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15506 /* 42544 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15507 /* 42548 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15508 /* 42552 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3997:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15509 /* 42552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQf),
15510 /* 42555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15511 /* 42557 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15512 /* 42559 */ GIR_RootConstrainSelectedInstOperands,
15513 /* 42560 */ // GIR_Coverage, 1807,
15514 /* 42560 */ GIR_EraseRootFromParent_Done,
15515 /* 42561 */ // Label 1312: @42561
15516 /* 42561 */ GIM_Reject,
15517 /* 42562 */ // Label 1310: @42562
15518 /* 42562 */ GIM_Reject,
15519 /* 42563 */ // Label 1307: @42563
15520 /* 42563 */ GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(42649),
15521 /* 42568 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
15522 /* 42573 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 1316*/ GIMT_Encode4(42648),
15523 /* 42584 */ /*GILLT_v2s32*//*Label 1314*/ GIMT_Encode4(42592),
15524 /* 42588 */ /*GILLT_v4s32*//*Label 1315*/ GIMT_Encode4(42620),
15525 /* 42592 */ // Label 1314: @42592
15526 /* 42592 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1317*/ GIMT_Encode4(42619), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1808 //
15527 /* 42599 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15528 /* 42602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15529 /* 42606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15530 /* 42610 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3998:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
15531 /* 42610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDf),
15532 /* 42613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15533 /* 42615 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15534 /* 42617 */ GIR_RootConstrainSelectedInstOperands,
15535 /* 42618 */ // GIR_Coverage, 1808,
15536 /* 42618 */ GIR_EraseRootFromParent_Done,
15537 /* 42619 */ // Label 1317: @42619
15538 /* 42619 */ GIM_Reject,
15539 /* 42620 */ // Label 1315: @42620
15540 /* 42620 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1318*/ GIMT_Encode4(42647), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1809 //
15541 /* 42627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15542 /* 42630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15543 /* 42634 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15544 /* 42638 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3998:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
15545 /* 42638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQf),
15546 /* 42641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15547 /* 42643 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15548 /* 42645 */ GIR_RootConstrainSelectedInstOperands,
15549 /* 42646 */ // GIR_Coverage, 1809,
15550 /* 42646 */ GIR_EraseRootFromParent_Done,
15551 /* 42647 */ // Label 1318: @42647
15552 /* 42647 */ GIM_Reject,
15553 /* 42648 */ // Label 1316: @42648
15554 /* 42648 */ GIM_Reject,
15555 /* 42649 */ // Label 1313: @42649
15556 /* 42649 */ GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(42735),
15557 /* 42654 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
15558 /* 42659 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1322*/ GIMT_Encode4(42734),
15559 /* 42670 */ /*GILLT_v4s16*//*Label 1320*/ GIMT_Encode4(42678),
15560 /* 42674 */ /*GILLT_v8s16*//*Label 1321*/ GIMT_Encode4(42706),
15561 /* 42678 */ // Label 1320: @42678
15562 /* 42678 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1323*/ GIMT_Encode4(42705), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1810 //
15563 /* 42685 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15564 /* 42688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15565 /* 42692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15566 /* 42696 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3997:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15567 /* 42696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDh),
15568 /* 42699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15569 /* 42701 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15570 /* 42703 */ GIR_RootConstrainSelectedInstOperands,
15571 /* 42704 */ // GIR_Coverage, 1810,
15572 /* 42704 */ GIR_EraseRootFromParent_Done,
15573 /* 42705 */ // Label 1323: @42705
15574 /* 42705 */ GIM_Reject,
15575 /* 42706 */ // Label 1321: @42706
15576 /* 42706 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1324*/ GIMT_Encode4(42733), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1811 //
15577 /* 42713 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15578 /* 42716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15579 /* 42720 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15580 /* 42724 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3997:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15581 /* 42724 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQh),
15582 /* 42727 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15583 /* 42729 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15584 /* 42731 */ GIR_RootConstrainSelectedInstOperands,
15585 /* 42732 */ // GIR_Coverage, 1811,
15586 /* 42732 */ GIR_EraseRootFromParent_Done,
15587 /* 42733 */ // Label 1324: @42733
15588 /* 42733 */ GIM_Reject,
15589 /* 42734 */ // Label 1322: @42734
15590 /* 42734 */ GIM_Reject,
15591 /* 42735 */ // Label 1319: @42735
15592 /* 42735 */ GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(42821),
15593 /* 42740 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
15594 /* 42745 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 1328*/ GIMT_Encode4(42820),
15595 /* 42756 */ /*GILLT_v4s16*//*Label 1326*/ GIMT_Encode4(42764),
15596 /* 42760 */ /*GILLT_v8s16*//*Label 1327*/ GIMT_Encode4(42792),
15597 /* 42764 */ // Label 1326: @42764
15598 /* 42764 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1329*/ GIMT_Encode4(42791), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1812 //
15599 /* 42771 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15600 /* 42774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15601 /* 42778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15602 /* 42782 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3998:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
15603 /* 42782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDh),
15604 /* 42785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15605 /* 42787 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15606 /* 42789 */ GIR_RootConstrainSelectedInstOperands,
15607 /* 42790 */ // GIR_Coverage, 1812,
15608 /* 42790 */ GIR_EraseRootFromParent_Done,
15609 /* 42791 */ // Label 1329: @42791
15610 /* 42791 */ GIM_Reject,
15611 /* 42792 */ // Label 1327: @42792
15612 /* 42792 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1330*/ GIMT_Encode4(42819), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1813 //
15613 /* 42799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15614 /* 42802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15615 /* 42806 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15616 /* 42810 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3998:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
15617 /* 42810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQh),
15618 /* 42813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15619 /* 42815 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15620 /* 42817 */ GIR_RootConstrainSelectedInstOperands,
15621 /* 42818 */ // GIR_Coverage, 1813,
15622 /* 42818 */ GIR_EraseRootFromParent_Done,
15623 /* 42819 */ // Label 1330: @42819
15624 /* 42819 */ GIM_Reject,
15625 /* 42820 */ // Label 1328: @42820
15626 /* 42820 */ GIM_Reject,
15627 /* 42821 */ // Label 1325: @42821
15628 /* 42821 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1331*/ GIMT_Encode4(42865), GIMT_Encode2(GIFBS_HasFP16_HasNEON), // Rule ID 1830 //
15629 /* 42828 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2hf),
15630 /* 42833 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15631 /* 42836 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15632 /* 42839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15633 /* 42843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15634 /* 42847 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3993:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTf2h:{ *:[v4i16] } QPR:{ *:[v4f32] }:$Vm)
15635 /* 42847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h),
15636 /* 42850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15637 /* 42852 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15638 /* 42854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15639 /* 42857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15640 /* 42863 */ GIR_RootConstrainSelectedInstOperands,
15641 /* 42864 */ // GIR_Coverage, 1830,
15642 /* 42864 */ GIR_EraseRootFromParent_Done,
15643 /* 42865 */ // Label 1331: @42865
15644 /* 42865 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1332*/ GIMT_Encode4(42909), GIMT_Encode2(GIFBS_HasFP16_HasNEON), // Rule ID 1831 //
15645 /* 42872 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvthf2fp),
15646 /* 42877 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15647 /* 42880 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15648 /* 42883 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15649 /* 42887 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15650 /* 42891 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3996:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4i16] }:$Vm)
15651 /* 42891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f),
15652 /* 42894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15653 /* 42896 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15654 /* 42898 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15655 /* 42901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15656 /* 42907 */ GIR_RootConstrainSelectedInstOperands,
15657 /* 42908 */ // GIR_Coverage, 1831,
15658 /* 42908 */ GIR_EraseRootFromParent_Done,
15659 /* 42909 */ // Label 1332: @42909
15660 /* 42909 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1333*/ GIMT_Encode4(42944), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1903 //
15661 /* 42916 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesimc),
15662 /* 42921 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
15663 /* 42924 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15664 /* 42927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15665 /* 42931 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15666 /* 42935 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3956:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESIMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
15667 /* 42935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESIMC),
15668 /* 42938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15669 /* 42940 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15670 /* 42942 */ GIR_RootConstrainSelectedInstOperands,
15671 /* 42943 */ // GIR_Coverage, 1903,
15672 /* 42943 */ GIR_EraseRootFromParent_Done,
15673 /* 42944 */ // Label 1333: @42944
15674 /* 42944 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1334*/ GIMT_Encode4(42979), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1904 //
15675 /* 42951 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesmc),
15676 /* 42956 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
15677 /* 42959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15678 /* 42962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15679 /* 42966 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15680 /* 42970 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3957:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
15681 /* 42970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESMC),
15682 /* 42973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15683 /* 42975 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15684 /* 42977 */ GIR_RootConstrainSelectedInstOperands,
15685 /* 42978 */ // GIR_Coverage, 1904,
15686 /* 42978 */ GIR_EraseRootFromParent_Done,
15687 /* 42979 */ // Label 1334: @42979
15688 /* 42979 */ GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(43068),
15689 /* 42984 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16),
15690 /* 42989 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15691 /* 42992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15692 /* 42995 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1336*/ GIMT_Encode4(43031), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2039 //
15693 /* 43002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
15694 /* 43006 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
15695 /* 43010 */ // (intrinsic_wo_chain:{ *:[i32] } 4150:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (SXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
15696 /* 43010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB16),
15697 /* 43013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
15698 /* 43015 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src
15699 /* 43017 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15700 /* 43020 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15701 /* 43023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15702 /* 43029 */ GIR_RootConstrainSelectedInstOperands,
15703 /* 43030 */ // GIR_Coverage, 2039,
15704 /* 43030 */ GIR_EraseRootFromParent_Done,
15705 /* 43031 */ // Label 1336: @43031
15706 /* 43031 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1337*/ GIMT_Encode4(43067), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2295 //
15707 /* 43038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
15708 /* 43042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
15709 /* 43046 */ // (intrinsic_wo_chain:{ *:[i32] } 4150:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (t2SXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 0:{ *:[i32] })
15710 /* 43046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB16),
15711 /* 43049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
15712 /* 43051 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
15713 /* 43053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15714 /* 43056 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15715 /* 43059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15716 /* 43065 */ GIR_RootConstrainSelectedInstOperands,
15717 /* 43066 */ // GIR_Coverage, 2295,
15718 /* 43066 */ GIR_EraseRootFromParent_Done,
15719 /* 43067 */ // Label 1337: @43067
15720 /* 43067 */ GIM_Reject,
15721 /* 43068 */ // Label 1335: @43068
15722 /* 43068 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1338*/ GIMT_Encode4(43133), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4369 //
15723 /* 43075 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn),
15724 /* 43080 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15725 /* 43083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15726 /* 43086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15727 /* 43090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15728 /* 43094 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3916:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
15729 /* 43094 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15730 /* 43097 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15731 /* 43101 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15732 /* 43106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N),
15733 /* 43109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15734 /* 43111 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15735 /* 43113 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15736 /* 43116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15737 /* 43122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15738 /* 43128 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15739 /* 43131 */ GIR_RootConstrainSelectedInstOperands,
15740 /* 43132 */ // GIR_Coverage, 4369,
15741 /* 43132 */ GIR_EraseRootFromParent_Done,
15742 /* 43133 */ // Label 1338: @43133
15743 /* 43133 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1339*/ GIMT_Encode4(43198), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4373 //
15744 /* 43140 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintx),
15745 /* 43145 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15746 /* 43148 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15747 /* 43151 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15748 /* 43155 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15749 /* 43159 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3920:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
15750 /* 43159 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15751 /* 43162 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15752 /* 43166 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15753 /* 43171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X),
15754 /* 43174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15755 /* 43176 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15756 /* 43178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15757 /* 43181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15758 /* 43187 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15759 /* 43193 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15760 /* 43196 */ GIR_RootConstrainSelectedInstOperands,
15761 /* 43197 */ // GIR_Coverage, 4373,
15762 /* 43197 */ GIR_EraseRootFromParent_Done,
15763 /* 43198 */ // Label 1339: @43198
15764 /* 43198 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1340*/ GIMT_Encode4(43263), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4377 //
15765 /* 43205 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrinta),
15766 /* 43210 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15767 /* 43213 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15768 /* 43216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15769 /* 43220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15770 /* 43224 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3912:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
15771 /* 43224 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15772 /* 43227 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15773 /* 43231 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15774 /* 43236 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A),
15775 /* 43239 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15776 /* 43241 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15777 /* 43243 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15778 /* 43246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15779 /* 43252 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15780 /* 43258 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15781 /* 43261 */ GIR_RootConstrainSelectedInstOperands,
15782 /* 43262 */ // GIR_Coverage, 4377,
15783 /* 43262 */ GIR_EraseRootFromParent_Done,
15784 /* 43263 */ // Label 1340: @43263
15785 /* 43263 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1341*/ GIMT_Encode4(43328), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4381 //
15786 /* 43270 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintz),
15787 /* 43275 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15788 /* 43278 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15789 /* 43281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15790 /* 43285 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15791 /* 43289 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3922:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
15792 /* 43289 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15793 /* 43292 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15794 /* 43296 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15795 /* 43301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z),
15796 /* 43304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15797 /* 43306 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15798 /* 43308 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15799 /* 43311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15800 /* 43317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15801 /* 43323 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15802 /* 43326 */ GIR_RootConstrainSelectedInstOperands,
15803 /* 43327 */ // GIR_Coverage, 4381,
15804 /* 43327 */ GIR_EraseRootFromParent_Done,
15805 /* 43328 */ // Label 1341: @43328
15806 /* 43328 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1342*/ GIMT_Encode4(43393), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4385 //
15807 /* 43335 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintm),
15808 /* 43340 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15809 /* 43343 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15810 /* 43346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15811 /* 43350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15812 /* 43354 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3914:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
15813 /* 43354 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15814 /* 43357 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15815 /* 43361 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15816 /* 43366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M),
15817 /* 43369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15818 /* 43371 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15819 /* 43373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15820 /* 43376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15821 /* 43382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15822 /* 43388 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15823 /* 43391 */ GIR_RootConstrainSelectedInstOperands,
15824 /* 43392 */ // GIR_Coverage, 4385,
15825 /* 43392 */ GIR_EraseRootFromParent_Done,
15826 /* 43393 */ // Label 1342: @43393
15827 /* 43393 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1343*/ GIMT_Encode4(43458), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4389 //
15828 /* 43400 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintp),
15829 /* 43405 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15830 /* 43408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15831 /* 43411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15832 /* 43415 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15833 /* 43419 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3918:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
15834 /* 43419 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15835 /* 43422 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15836 /* 43426 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15837 /* 43431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P),
15838 /* 43434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15839 /* 43436 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15840 /* 43438 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15841 /* 43441 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15842 /* 43447 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15843 /* 43453 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15844 /* 43456 */ GIR_RootConstrainSelectedInstOperands,
15845 /* 43457 */ // GIR_Coverage, 4389,
15846 /* 43457 */ GIR_EraseRootFromParent_Done,
15847 /* 43458 */ // Label 1343: @43458
15848 /* 43458 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1344*/ GIMT_Encode4(43523), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4393 //
15849 /* 43465 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn),
15850 /* 43470 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15851 /* 43473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15852 /* 43476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15853 /* 43480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15854 /* 43484 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3916:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
15855 /* 43484 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15856 /* 43487 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15857 /* 43491 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15858 /* 43496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N),
15859 /* 43499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15860 /* 43501 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15861 /* 43503 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15862 /* 43506 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15863 /* 43512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15864 /* 43518 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15865 /* 43521 */ GIR_RootConstrainSelectedInstOperands,
15866 /* 43522 */ // GIR_Coverage, 4393,
15867 /* 43522 */ GIR_EraseRootFromParent_Done,
15868 /* 43523 */ // Label 1344: @43523
15869 /* 43523 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1345*/ GIMT_Encode4(43588), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4397 //
15870 /* 43530 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintx),
15871 /* 43535 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15872 /* 43538 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15873 /* 43541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15874 /* 43545 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15875 /* 43549 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3920:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
15876 /* 43549 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15877 /* 43552 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15878 /* 43556 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15879 /* 43561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X),
15880 /* 43564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15881 /* 43566 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15882 /* 43568 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15883 /* 43571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15884 /* 43577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15885 /* 43583 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15886 /* 43586 */ GIR_RootConstrainSelectedInstOperands,
15887 /* 43587 */ // GIR_Coverage, 4397,
15888 /* 43587 */ GIR_EraseRootFromParent_Done,
15889 /* 43588 */ // Label 1345: @43588
15890 /* 43588 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1346*/ GIMT_Encode4(43653), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4401 //
15891 /* 43595 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrinta),
15892 /* 43600 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15893 /* 43603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15894 /* 43606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15895 /* 43610 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15896 /* 43614 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3912:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
15897 /* 43614 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15898 /* 43617 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15899 /* 43621 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15900 /* 43626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A),
15901 /* 43629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15902 /* 43631 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15903 /* 43633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15904 /* 43636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15905 /* 43642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15906 /* 43648 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15907 /* 43651 */ GIR_RootConstrainSelectedInstOperands,
15908 /* 43652 */ // GIR_Coverage, 4401,
15909 /* 43652 */ GIR_EraseRootFromParent_Done,
15910 /* 43653 */ // Label 1346: @43653
15911 /* 43653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1347*/ GIMT_Encode4(43718), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4405 //
15912 /* 43660 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintz),
15913 /* 43665 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15914 /* 43668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15915 /* 43671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15916 /* 43675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15917 /* 43679 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3922:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
15918 /* 43679 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15919 /* 43682 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15920 /* 43686 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15921 /* 43691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z),
15922 /* 43694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15923 /* 43696 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15924 /* 43698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15925 /* 43701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15926 /* 43707 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15927 /* 43713 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15928 /* 43716 */ GIR_RootConstrainSelectedInstOperands,
15929 /* 43717 */ // GIR_Coverage, 4405,
15930 /* 43717 */ GIR_EraseRootFromParent_Done,
15931 /* 43718 */ // Label 1347: @43718
15932 /* 43718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1348*/ GIMT_Encode4(43783), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4409 //
15933 /* 43725 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintm),
15934 /* 43730 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15935 /* 43733 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15936 /* 43736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15937 /* 43740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15938 /* 43744 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3914:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
15939 /* 43744 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15940 /* 43747 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15941 /* 43751 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15942 /* 43756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M),
15943 /* 43759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15944 /* 43761 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15945 /* 43763 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15946 /* 43766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15947 /* 43772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15948 /* 43778 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15949 /* 43781 */ GIR_RootConstrainSelectedInstOperands,
15950 /* 43782 */ // GIR_Coverage, 4409,
15951 /* 43782 */ GIR_EraseRootFromParent_Done,
15952 /* 43783 */ // Label 1348: @43783
15953 /* 43783 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1349*/ GIMT_Encode4(43848), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4413 //
15954 /* 43790 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintp),
15955 /* 43795 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15956 /* 43798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15957 /* 43801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15958 /* 43805 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
15959 /* 43809 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3918:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
15960 /* 43809 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
15961 /* 43812 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
15962 /* 43816 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15963 /* 43821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P),
15964 /* 43824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15965 /* 43826 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
15966 /* 43828 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15967 /* 43831 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15968 /* 43837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15969 /* 43843 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15970 /* 43846 */ GIR_RootConstrainSelectedInstOperands,
15971 /* 43847 */ // GIR_Coverage, 4413,
15972 /* 43847 */ GIR_EraseRootFromParent_Done,
15973 /* 43848 */ // Label 1349: @43848
15974 /* 43848 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1350*/ GIMT_Encode4(43898), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5399 //
15975 /* 43855 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp8),
15976 /* 43860 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s1,
15977 /* 43863 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15978 /* 43866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
15979 /* 43870 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
15980 /* 43874 */ // (intrinsic_wo_chain:{ *:[v16i1] } 3835:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP8:{ *:[v16i1] } rGPR:{ *:[i32] }:$Rn)
15981 /* 43874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP8),
15982 /* 43877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
15983 /* 43879 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
15984 /* 43881 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15985 /* 43884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15986 /* 43890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15987 /* 43896 */ GIR_RootConstrainSelectedInstOperands,
15988 /* 43897 */ // GIR_Coverage, 5399,
15989 /* 43897 */ GIR_EraseRootFromParent_Done,
15990 /* 43898 */ // Label 1350: @43898
15991 /* 43898 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1351*/ GIMT_Encode4(43948), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5401 //
15992 /* 43905 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp16),
15993 /* 43910 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
15994 /* 43913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15995 /* 43916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
15996 /* 43920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
15997 /* 43924 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3832:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP16:{ *:[v8i1] } rGPR:{ *:[i32] }:$Rn)
15998 /* 43924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP16),
15999 /* 43927 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
16000 /* 43929 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16001 /* 43931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16002 /* 43934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16003 /* 43940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16004 /* 43946 */ GIR_RootConstrainSelectedInstOperands,
16005 /* 43947 */ // GIR_Coverage, 5401,
16006 /* 43947 */ GIR_EraseRootFromParent_Done,
16007 /* 43948 */ // Label 1351: @43948
16008 /* 43948 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1352*/ GIMT_Encode4(43998), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5403 //
16009 /* 43955 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp32),
16010 /* 43960 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
16011 /* 43963 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16012 /* 43966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16013 /* 43970 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16014 /* 43974 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3833:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP32:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn)
16015 /* 43974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP32),
16016 /* 43977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
16017 /* 43979 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16018 /* 43981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16019 /* 43984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16020 /* 43990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16021 /* 43996 */ GIR_RootConstrainSelectedInstOperands,
16022 /* 43997 */ // GIR_Coverage, 5403,
16023 /* 43997 */ GIR_EraseRootFromParent_Done,
16024 /* 43998 */ // Label 1352: @43998
16025 /* 43998 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1353*/ GIMT_Encode4(44048), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5405 //
16026 /* 44005 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp64),
16027 /* 44010 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s1,
16028 /* 44013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16029 /* 44016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16030 /* 44020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16031 /* 44024 */ // (intrinsic_wo_chain:{ *:[v2i1] } 3834:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP64:{ *:[v2i1] } rGPR:{ *:[i32] }:$Rn)
16032 /* 44024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP64),
16033 /* 44027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
16034 /* 44029 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16035 /* 44031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16036 /* 44034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16037 /* 44040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16038 /* 44046 */ GIR_RootConstrainSelectedInstOperands,
16039 /* 44047 */ // GIR_Coverage, 5405,
16040 /* 44047 */ GIR_EraseRootFromParent_Done,
16041 /* 44048 */ // Label 1353: @44048
16042 /* 44048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1354*/ GIMT_Encode4(44093), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 599 //
16043 /* 44055 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tt),
16044 /* 44060 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16045 /* 44063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16046 /* 44067 */ // MIs[0] Rn
16047 /* 44067 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16048 /* 44071 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16049 /* 44075 */ // (intrinsic_wo_chain:{ *:[i32] } 3709:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16050 /* 44075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TT),
16051 /* 44078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
16052 /* 44080 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16053 /* 44082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16054 /* 44085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16055 /* 44091 */ GIR_RootConstrainSelectedInstOperands,
16056 /* 44092 */ // GIR_Coverage, 599,
16057 /* 44092 */ GIR_EraseRootFromParent_Done,
16058 /* 44093 */ // Label 1354: @44093
16059 /* 44093 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1355*/ GIMT_Encode4(44138), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 600 //
16060 /* 44100 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttt),
16061 /* 44105 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16062 /* 44108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16063 /* 44112 */ // MIs[0] Rn
16064 /* 44112 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16065 /* 44116 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16066 /* 44120 */ // (intrinsic_wo_chain:{ *:[i32] } 3712:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16067 /* 44120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTT),
16068 /* 44123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
16069 /* 44125 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16070 /* 44127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16071 /* 44130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16072 /* 44136 */ GIR_RootConstrainSelectedInstOperands,
16073 /* 44137 */ // GIR_Coverage, 600,
16074 /* 44137 */ GIR_EraseRootFromParent_Done,
16075 /* 44138 */ // Label 1355: @44138
16076 /* 44138 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1356*/ GIMT_Encode4(44183), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 601 //
16077 /* 44145 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tta),
16078 /* 44150 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16079 /* 44153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16080 /* 44157 */ // MIs[0] Rn
16081 /* 44157 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16082 /* 44161 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16083 /* 44165 */ // (intrinsic_wo_chain:{ *:[i32] } 3710:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16084 /* 44165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTA),
16085 /* 44168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
16086 /* 44170 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16087 /* 44172 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16088 /* 44175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16089 /* 44181 */ GIR_RootConstrainSelectedInstOperands,
16090 /* 44182 */ // GIR_Coverage, 601,
16091 /* 44182 */ GIR_EraseRootFromParent_Done,
16092 /* 44183 */ // Label 1356: @44183
16093 /* 44183 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1357*/ GIMT_Encode4(44228), GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb), // Rule ID 602 //
16094 /* 44190 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttat),
16095 /* 44195 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16096 /* 44198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16097 /* 44202 */ // MIs[0] Rn
16098 /* 44202 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
16099 /* 44206 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16100 /* 44210 */ // (intrinsic_wo_chain:{ *:[i32] } 3711:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTAT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
16101 /* 44210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTAT),
16102 /* 44213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
16103 /* 44215 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16104 /* 44217 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16105 /* 44220 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16106 /* 44226 */ GIR_RootConstrainSelectedInstOperands,
16107 /* 44227 */ // GIR_Coverage, 602,
16108 /* 44227 */ GIR_EraseRootFromParent_Done,
16109 /* 44228 */ // Label 1357: @44228
16110 /* 44228 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1358*/ GIMT_Encode4(44381), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3082 //
16111 /* 44235 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1h),
16112 /* 44240 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16113 /* 44243 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16114 /* 44246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
16115 /* 44250 */ // (intrinsic_wo_chain:{ *:[i32] } 3964:{ *:[iPTR] }, i32:{ *:[i32] }:$Rn) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[f32] } (SHA1H:{ *:[v16i8] } (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$Rn, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }), GPR:{ *:[i32] })
16116 /* 44250 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32,
16117 /* 44253 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16118 /* 44257 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16119 /* 44262 */ GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/2, // Rn
16120 /* 44266 */ GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
16121 /* 44271 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v16s8,
16122 /* 44274 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16123 /* 44278 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16124 /* 44283 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/4,
16125 /* 44285 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
16126 /* 44288 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
16127 /* 44292 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16128 /* 44297 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
16129 /* 44300 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4,
16130 /* 44303 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
16131 /* 44306 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
16132 /* 44311 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
16133 /* 44316 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
16134 /* 44321 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
16135 /* 44324 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::SHA1H),
16136 /* 44328 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16137 /* 44333 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
16138 /* 44336 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
16139 /* 44338 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
16140 /* 44341 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16141 /* 44345 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16142 /* 44350 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
16143 /* 44357 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
16144 /* 44362 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::MQPRRegClassID),
16145 /* 44367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
16146 /* 44370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
16147 /* 44372 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16148 /* 44375 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
16149 /* 44380 */ // GIR_Coverage, 3082,
16150 /* 44380 */ GIR_EraseRootFromParent_Done,
16151 /* 44381 */ // Label 1358: @44381
16152 /* 44381 */ GIM_Reject,
16153 /* 44382 */ // Label 1111: @44382
16154 /* 44382 */ GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(67745),
16155 /* 44387 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
16156 /* 44390 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1360*/ GIMT_Encode4(44446), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2313 //
16157 /* 44397 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16),
16158 /* 44402 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16159 /* 44405 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16160 /* 44408 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16161 /* 44411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16162 /* 44415 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16163 /* 44419 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16164 /* 44423 */ // (intrinsic_wo_chain:{ *:[i32] } 4174:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
16165 /* 44423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB16),
16166 /* 44426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16167 /* 44428 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16168 /* 44430 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
16169 /* 44432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16170 /* 44435 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16171 /* 44438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16172 /* 44444 */ GIR_RootConstrainSelectedInstOperands,
16173 /* 44445 */ // GIR_Coverage, 2313,
16174 /* 44445 */ GIR_EraseRootFromParent_Done,
16175 /* 44446 */ // Label 1360: @44446
16176 /* 44446 */ GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(44634),
16177 /* 44451 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
16178 /* 44456 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16179 /* 44459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16180 /* 44462 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16181 /* 44465 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1362*/ GIMT_Encode4(44549), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2076 //
16182 /* 44472 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16183 /* 44476 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16184 /* 44480 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
16185 /* 44484 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16186 /* 44488 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16187 /* 44492 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16188 /* 44497 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16189 /* 44501 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16190 /* 44505 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
16191 /* 44509 */ // MIs[2] Operand 1
16192 /* 44509 */ // No operand predicates
16193 /* 44509 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
16194 /* 44513 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16195 /* 44517 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
16196 /* 44521 */ // MIs[3] Operand 1
16197 /* 44521 */ // No operand predicates
16198 /* 44521 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
16199 /* 44523 */ // (intrinsic_wo_chain:{ *:[i32] } 4169:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft)
16200 /* 44523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT),
16201 /* 44526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16202 /* 44528 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos
16203 /* 44531 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
16204 /* 44535 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft
16205 /* 44538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16206 /* 44541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16207 /* 44547 */ GIR_RootConstrainSelectedInstOperands,
16208 /* 44548 */ // GIR_Coverage, 2076,
16209 /* 44548 */ GIR_EraseRootFromParent_Done,
16210 /* 44549 */ // Label 1362: @44549
16211 /* 44549 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1363*/ GIMT_Encode4(44633), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2350 //
16212 /* 44556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16213 /* 44560 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16214 /* 44564 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
16215 /* 44568 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
16216 /* 44572 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16217 /* 44576 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16218 /* 44581 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
16219 /* 44585 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16220 /* 44589 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
16221 /* 44593 */ // MIs[2] Operand 1
16222 /* 44593 */ // No operand predicates
16223 /* 44593 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
16224 /* 44597 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
16225 /* 44601 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
16226 /* 44605 */ // MIs[3] Operand 1
16227 /* 44605 */ // No operand predicates
16228 /* 44605 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
16229 /* 44607 */ // (intrinsic_wo_chain:{ *:[i32] } 4169:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft)
16230 /* 44607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT),
16231 /* 44610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16232 /* 44612 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos
16233 /* 44615 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
16234 /* 44619 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft
16235 /* 44622 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16236 /* 44625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16237 /* 44631 */ GIR_RootConstrainSelectedInstOperands,
16238 /* 44632 */ // GIR_Coverage, 2350,
16239 /* 44632 */ GIR_EraseRootFromParent_Done,
16240 /* 44633 */ // Label 1363: @44633
16241 /* 44633 */ GIM_Reject,
16242 /* 44634 */ // Label 1361: @44634
16243 /* 44634 */ GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(44861),
16244 /* 44639 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16245 /* 44644 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16246 /* 44647 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16247 /* 44650 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16248 /* 44653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1365*/ GIMT_Encode4(44722), GIMT_Encode2(GIFBS_IsARM), // Rule ID 5965 //
16249 /* 44660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16250 /* 44664 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16251 /* 44668 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16252 /* 44672 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16253 /* 44675 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16254 /* 44680 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16255 /* 44684 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16256 /* 44689 */ // MIs[1] Rn
16257 /* 44689 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16258 /* 44694 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16259 /* 44698 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16260 /* 44700 */ // (intrinsic_wo_chain:{ *:[i32] } 4092:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 4092:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn), GPRnopc:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
16261 /* 44700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
16262 /* 44703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16263 /* 44705 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
16264 /* 44707 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16265 /* 44711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16266 /* 44714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16267 /* 44720 */ GIR_RootConstrainSelectedInstOperands,
16268 /* 44721 */ // GIR_Coverage, 5965,
16269 /* 44721 */ GIR_EraseRootFromParent_Done,
16270 /* 44722 */ // Label 1365: @44722
16271 /* 44722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1366*/ GIMT_Encode4(44791), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6293 //
16272 /* 44729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16273 /* 44733 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16274 /* 44737 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16275 /* 44741 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16276 /* 44744 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16277 /* 44749 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16278 /* 44753 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16279 /* 44758 */ // MIs[1] Rn
16280 /* 44758 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16281 /* 44763 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16282 /* 44767 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16283 /* 44769 */ // (intrinsic_wo_chain:{ *:[i32] } 4092:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 4092:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
16284 /* 44769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
16285 /* 44772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16286 /* 44774 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
16287 /* 44776 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16288 /* 44780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16289 /* 44783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16290 /* 44789 */ GIR_RootConstrainSelectedInstOperands,
16291 /* 44790 */ // GIR_Coverage, 6293,
16292 /* 44790 */ GIR_EraseRootFromParent_Done,
16293 /* 44791 */ // Label 1366: @44791
16294 /* 44791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1367*/ GIMT_Encode4(44860), GIMT_Encode2(GIFBS_IsARM), // Rule ID 108 //
16295 /* 44798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16296 /* 44802 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16297 /* 44806 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16298 /* 44810 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16299 /* 44814 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16300 /* 44817 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16301 /* 44822 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16302 /* 44826 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16303 /* 44831 */ // MIs[1] Rn
16304 /* 44831 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16305 /* 44836 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16306 /* 44838 */ // (intrinsic_wo_chain:{ *:[i32] } 4092:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4092:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
16307 /* 44838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
16308 /* 44841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16309 /* 44843 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
16310 /* 44845 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16311 /* 44849 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16312 /* 44852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16313 /* 44858 */ GIR_RootConstrainSelectedInstOperands,
16314 /* 44859 */ // GIR_Coverage, 108,
16315 /* 44859 */ GIR_EraseRootFromParent_Done,
16316 /* 44860 */ // Label 1367: @44860
16317 /* 44860 */ GIM_Reject,
16318 /* 44861 */ // Label 1364: @44861
16319 /* 44861 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1368*/ GIMT_Encode4(44944), GIMT_Encode2(GIFBS_IsARM), // Rule ID 109 //
16320 /* 44868 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
16321 /* 44873 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16322 /* 44876 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16323 /* 44879 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16324 /* 44882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16325 /* 44886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16326 /* 44890 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16327 /* 44894 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16328 /* 44898 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16329 /* 44901 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16330 /* 44906 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16331 /* 44910 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16332 /* 44915 */ // MIs[1] Rn
16333 /* 44915 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16334 /* 44920 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16335 /* 44922 */ // (intrinsic_wo_chain:{ *:[i32] } 4097:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4092:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
16336 /* 44922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB),
16337 /* 44925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16338 /* 44927 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
16339 /* 44929 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16340 /* 44933 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16341 /* 44936 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16342 /* 44942 */ GIR_RootConstrainSelectedInstOperands,
16343 /* 44943 */ // GIR_Coverage, 109,
16344 /* 44943 */ GIR_EraseRootFromParent_Done,
16345 /* 44944 */ // Label 1368: @44944
16346 /* 44944 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1369*/ GIMT_Encode4(45027), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2328 //
16347 /* 44951 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16348 /* 44956 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16349 /* 44959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16350 /* 44962 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16351 /* 44965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16352 /* 44969 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16353 /* 44973 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16354 /* 44977 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16355 /* 44981 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16356 /* 44984 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16357 /* 44989 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16358 /* 44993 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16359 /* 44998 */ // MIs[1] Rn
16360 /* 44998 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16361 /* 45003 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16362 /* 45005 */ // (intrinsic_wo_chain:{ *:[i32] } 4092:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4092:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
16363 /* 45005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
16364 /* 45008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16365 /* 45010 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
16366 /* 45012 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16367 /* 45016 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16368 /* 45019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16369 /* 45025 */ GIR_RootConstrainSelectedInstOperands,
16370 /* 45026 */ // GIR_Coverage, 2328,
16371 /* 45026 */ GIR_EraseRootFromParent_Done,
16372 /* 45027 */ // Label 1369: @45027
16373 /* 45027 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1370*/ GIMT_Encode4(45110), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2329 //
16374 /* 45034 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
16375 /* 45039 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16376 /* 45042 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16377 /* 45045 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16378 /* 45048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16379 /* 45052 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16380 /* 45056 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
16381 /* 45060 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
16382 /* 45064 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
16383 /* 45067 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
16384 /* 45072 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
16385 /* 45076 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16386 /* 45081 */ // MIs[1] Rn
16387 /* 45081 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
16388 /* 45086 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
16389 /* 45088 */ // (intrinsic_wo_chain:{ *:[i32] } 4097:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4092:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
16390 /* 45088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB),
16391 /* 45091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16392 /* 45093 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
16393 /* 45095 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
16394 /* 45099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16395 /* 45102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16396 /* 45108 */ GIR_RootConstrainSelectedInstOperands,
16397 /* 45109 */ // GIR_Coverage, 2329,
16398 /* 45109 */ GIR_EraseRootFromParent_Done,
16399 /* 45110 */ // Label 1370: @45110
16400 /* 45110 */ GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(45312),
16401 /* 45115 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm),
16402 /* 45120 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1374*/ GIMT_Encode4(45311),
16403 /* 45131 */ /*GILLT_v8s16*//*Label 1372*/ GIMT_Encode4(45143), GIMT_Encode4(0),
16404 /* 45139 */ /*GILLT_v4s32*//*Label 1373*/ GIMT_Encode4(45227),
16405 /* 45143 */ // Label 1372: @45143
16406 /* 45143 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1375*/ GIMT_Encode4(45226), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4581 //
16407 /* 45150 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16408 /* 45153 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16409 /* 45156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16410 /* 45160 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16411 /* 45164 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
16412 /* 45168 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16413 /* 45172 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16414 /* 45177 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
16415 /* 45181 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
16416 /* 45185 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
16417 /* 45189 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16418 /* 45194 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
16419 /* 45196 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3872:{ *:[iPTR] }, (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
16420 /* 45196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16),
16421 /* 45199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16422 /* 45201 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
16423 /* 45205 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
16424 /* 45209 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16425 /* 45212 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16426 /* 45218 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16427 /* 45224 */ GIR_RootConstrainSelectedInstOperands,
16428 /* 45225 */ // GIR_Coverage, 4581,
16429 /* 45225 */ GIR_EraseRootFromParent_Done,
16430 /* 45226 */ // Label 1375: @45226
16431 /* 45226 */ GIM_Reject,
16432 /* 45227 */ // Label 1373: @45227
16433 /* 45227 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1376*/ GIMT_Encode4(45310), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4578 //
16434 /* 45234 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16435 /* 45237 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16436 /* 45240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16437 /* 45244 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16438 /* 45248 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
16439 /* 45252 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16440 /* 45256 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16441 /* 45261 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
16442 /* 45265 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
16443 /* 45269 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
16444 /* 45273 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16445 /* 45278 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
16446 /* 45280 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3872:{ *:[iPTR] }, (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
16447 /* 45280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32),
16448 /* 45283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16449 /* 45285 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
16450 /* 45289 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
16451 /* 45293 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16452 /* 45296 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16453 /* 45302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16454 /* 45308 */ GIR_RootConstrainSelectedInstOperands,
16455 /* 45309 */ // GIR_Coverage, 4578,
16456 /* 45309 */ GIR_EraseRootFromParent_Done,
16457 /* 45310 */ // Label 1376: @45310
16458 /* 45310 */ GIM_Reject,
16459 /* 45311 */ // Label 1374: @45311
16460 /* 45311 */ GIM_Reject,
16461 /* 45312 */ // Label 1371: @45312
16462 /* 45312 */ GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(45514),
16463 /* 45317 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm),
16464 /* 45322 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1380*/ GIMT_Encode4(45513),
16465 /* 45333 */ /*GILLT_v8s16*//*Label 1378*/ GIMT_Encode4(45345), GIMT_Encode4(0),
16466 /* 45341 */ /*GILLT_v4s32*//*Label 1379*/ GIMT_Encode4(45429),
16467 /* 45345 */ // Label 1378: @45345
16468 /* 45345 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1381*/ GIMT_Encode4(45428), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4587 //
16469 /* 45352 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16470 /* 45355 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16471 /* 45358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16472 /* 45362 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16473 /* 45366 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
16474 /* 45370 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
16475 /* 45374 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16476 /* 45379 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
16477 /* 45383 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
16478 /* 45387 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
16479 /* 45391 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16480 /* 45396 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
16481 /* 45398 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3875:{ *:[iPTR] }, (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
16482 /* 45398 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16),
16483 /* 45401 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16484 /* 45403 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
16485 /* 45407 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
16486 /* 45411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16487 /* 45414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16488 /* 45420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16489 /* 45426 */ GIR_RootConstrainSelectedInstOperands,
16490 /* 45427 */ // GIR_Coverage, 4587,
16491 /* 45427 */ GIR_EraseRootFromParent_Done,
16492 /* 45428 */ // Label 1381: @45428
16493 /* 45428 */ GIM_Reject,
16494 /* 45429 */ // Label 1379: @45429
16495 /* 45429 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1382*/ GIMT_Encode4(45512), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4584 //
16496 /* 45436 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16497 /* 45439 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16498 /* 45442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16499 /* 45446 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
16500 /* 45450 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
16501 /* 45454 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
16502 /* 45458 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16503 /* 45463 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
16504 /* 45467 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
16505 /* 45471 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
16506 /* 45475 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16507 /* 45480 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
16508 /* 45482 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3875:{ *:[iPTR] }, (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
16509 /* 45482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32),
16510 /* 45485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16511 /* 45487 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
16512 /* 45491 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
16513 /* 45495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16514 /* 45498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16515 /* 45504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16516 /* 45510 */ GIR_RootConstrainSelectedInstOperands,
16517 /* 45511 */ // GIR_Coverage, 4584,
16518 /* 45511 */ GIR_EraseRootFromParent_Done,
16519 /* 45512 */ // Label 1382: @45512
16520 /* 45512 */ GIM_Reject,
16521 /* 45513 */ // Label 1380: @45513
16522 /* 45513 */ GIM_Reject,
16523 /* 45514 */ // Label 1377: @45514
16524 /* 45514 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1383*/ GIMT_Encode4(45586), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4509 //
16525 /* 45521 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
16526 /* 45526 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16527 /* 45529 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16528 /* 45532 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16529 /* 45535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16530 /* 45539 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16531 /* 45543 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16532 /* 45547 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3845:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16533 /* 45547 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16534 /* 45550 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16535 /* 45554 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16536 /* 45559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16a),
16537 /* 45562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16538 /* 45564 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16539 /* 45566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16540 /* 45569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16541 /* 45575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16542 /* 45581 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16543 /* 45584 */ GIR_RootConstrainSelectedInstOperands,
16544 /* 45585 */ // GIR_Coverage, 4509,
16545 /* 45585 */ GIR_EraseRootFromParent_Done,
16546 /* 45586 */ // Label 1383: @45586
16547 /* 45586 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1384*/ GIMT_Encode4(45658), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4511 //
16548 /* 45593 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
16549 /* 45598 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16550 /* 45601 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16551 /* 45604 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16552 /* 45607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16553 /* 45611 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16554 /* 45615 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16555 /* 45619 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3849:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16556 /* 45619 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16557 /* 45622 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16558 /* 45626 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16559 /* 45631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16n),
16560 /* 45634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16561 /* 45636 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16562 /* 45638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16563 /* 45641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16564 /* 45647 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16565 /* 45653 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16566 /* 45656 */ GIR_RootConstrainSelectedInstOperands,
16567 /* 45657 */ // GIR_Coverage, 4511,
16568 /* 45657 */ GIR_EraseRootFromParent_Done,
16569 /* 45658 */ // Label 1384: @45658
16570 /* 45658 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1385*/ GIMT_Encode4(45730), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4513 //
16571 /* 45665 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
16572 /* 45670 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16573 /* 45673 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16574 /* 45676 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16575 /* 45679 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16576 /* 45683 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16577 /* 45687 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16578 /* 45691 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3851:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16579 /* 45691 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16580 /* 45694 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16581 /* 45698 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16582 /* 45703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16p),
16583 /* 45706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16584 /* 45708 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16585 /* 45710 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16586 /* 45713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16587 /* 45719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16588 /* 45725 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16589 /* 45728 */ GIR_RootConstrainSelectedInstOperands,
16590 /* 45729 */ // GIR_Coverage, 4513,
16591 /* 45729 */ GIR_EraseRootFromParent_Done,
16592 /* 45730 */ // Label 1385: @45730
16593 /* 45730 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1386*/ GIMT_Encode4(45802), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4515 //
16594 /* 45737 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
16595 /* 45742 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16596 /* 45745 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16597 /* 45748 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16598 /* 45751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16599 /* 45755 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16600 /* 45759 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16601 /* 45763 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3847:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16602 /* 45763 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16603 /* 45766 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16604 /* 45770 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16605 /* 45775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16m),
16606 /* 45778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16607 /* 45780 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16608 /* 45782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16609 /* 45785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16610 /* 45791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16611 /* 45797 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16612 /* 45800 */ GIR_RootConstrainSelectedInstOperands,
16613 /* 45801 */ // GIR_Coverage, 4515,
16614 /* 45801 */ GIR_EraseRootFromParent_Done,
16615 /* 45802 */ // Label 1386: @45802
16616 /* 45802 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1387*/ GIMT_Encode4(45874), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4517 //
16617 /* 45809 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
16618 /* 45814 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16619 /* 45817 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16620 /* 45820 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16621 /* 45823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16622 /* 45827 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16623 /* 45831 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16624 /* 45835 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3845:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16625 /* 45835 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16626 /* 45838 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16627 /* 45842 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16628 /* 45847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16a),
16629 /* 45850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16630 /* 45852 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16631 /* 45854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16632 /* 45857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16633 /* 45863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16634 /* 45869 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16635 /* 45872 */ GIR_RootConstrainSelectedInstOperands,
16636 /* 45873 */ // GIR_Coverage, 4517,
16637 /* 45873 */ GIR_EraseRootFromParent_Done,
16638 /* 45874 */ // Label 1387: @45874
16639 /* 45874 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1388*/ GIMT_Encode4(45946), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4519 //
16640 /* 45881 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
16641 /* 45886 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16642 /* 45889 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16643 /* 45892 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16644 /* 45895 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16645 /* 45899 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16646 /* 45903 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16647 /* 45907 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3849:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16648 /* 45907 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16649 /* 45910 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16650 /* 45914 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16651 /* 45919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16n),
16652 /* 45922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16653 /* 45924 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16654 /* 45926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16655 /* 45929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16656 /* 45935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16657 /* 45941 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16658 /* 45944 */ GIR_RootConstrainSelectedInstOperands,
16659 /* 45945 */ // GIR_Coverage, 4519,
16660 /* 45945 */ GIR_EraseRootFromParent_Done,
16661 /* 45946 */ // Label 1388: @45946
16662 /* 45946 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1389*/ GIMT_Encode4(46018), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4521 //
16663 /* 45953 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
16664 /* 45958 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16665 /* 45961 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16666 /* 45964 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16667 /* 45967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16668 /* 45971 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16669 /* 45975 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16670 /* 45979 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3851:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16671 /* 45979 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16672 /* 45982 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16673 /* 45986 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16674 /* 45991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16p),
16675 /* 45994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16676 /* 45996 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16677 /* 45998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16678 /* 46001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16679 /* 46007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16680 /* 46013 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16681 /* 46016 */ GIR_RootConstrainSelectedInstOperands,
16682 /* 46017 */ // GIR_Coverage, 4521,
16683 /* 46017 */ GIR_EraseRootFromParent_Done,
16684 /* 46018 */ // Label 1389: @46018
16685 /* 46018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1390*/ GIMT_Encode4(46090), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4523 //
16686 /* 46025 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
16687 /* 46030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16688 /* 46033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16689 /* 46036 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
16690 /* 46039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16691 /* 46043 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16692 /* 46047 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16693 /* 46051 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3847:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
16694 /* 46051 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16695 /* 46054 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16696 /* 46058 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16697 /* 46063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16m),
16698 /* 46066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16699 /* 46068 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16700 /* 46070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16701 /* 46073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16702 /* 46079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16703 /* 46085 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16704 /* 46088 */ GIR_RootConstrainSelectedInstOperands,
16705 /* 46089 */ // GIR_Coverage, 4523,
16706 /* 46089 */ GIR_EraseRootFromParent_Done,
16707 /* 46090 */ // Label 1390: @46090
16708 /* 46090 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1391*/ GIMT_Encode4(46162), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4525 //
16709 /* 46097 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
16710 /* 46102 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16711 /* 46105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16712 /* 46108 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16713 /* 46111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16714 /* 46115 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16715 /* 46119 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16716 /* 46123 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3845:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16717 /* 46123 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16718 /* 46126 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16719 /* 46130 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16720 /* 46135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32a),
16721 /* 46138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16722 /* 46140 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16723 /* 46142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16724 /* 46145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16725 /* 46151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16726 /* 46157 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16727 /* 46160 */ GIR_RootConstrainSelectedInstOperands,
16728 /* 46161 */ // GIR_Coverage, 4525,
16729 /* 46161 */ GIR_EraseRootFromParent_Done,
16730 /* 46162 */ // Label 1391: @46162
16731 /* 46162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1392*/ GIMT_Encode4(46234), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4527 //
16732 /* 46169 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
16733 /* 46174 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16734 /* 46177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16735 /* 46180 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16736 /* 46183 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16737 /* 46187 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16738 /* 46191 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16739 /* 46195 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3849:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16740 /* 46195 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16741 /* 46198 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16742 /* 46202 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16743 /* 46207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32n),
16744 /* 46210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16745 /* 46212 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16746 /* 46214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16747 /* 46217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16748 /* 46223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16749 /* 46229 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16750 /* 46232 */ GIR_RootConstrainSelectedInstOperands,
16751 /* 46233 */ // GIR_Coverage, 4527,
16752 /* 46233 */ GIR_EraseRootFromParent_Done,
16753 /* 46234 */ // Label 1392: @46234
16754 /* 46234 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1393*/ GIMT_Encode4(46306), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4529 //
16755 /* 46241 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
16756 /* 46246 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16757 /* 46249 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16758 /* 46252 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16759 /* 46255 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16760 /* 46259 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16761 /* 46263 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16762 /* 46267 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3851:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16763 /* 46267 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16764 /* 46270 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16765 /* 46274 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16766 /* 46279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32p),
16767 /* 46282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16768 /* 46284 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16769 /* 46286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16770 /* 46289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16771 /* 46295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16772 /* 46301 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16773 /* 46304 */ GIR_RootConstrainSelectedInstOperands,
16774 /* 46305 */ // GIR_Coverage, 4529,
16775 /* 46305 */ GIR_EraseRootFromParent_Done,
16776 /* 46306 */ // Label 1393: @46306
16777 /* 46306 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1394*/ GIMT_Encode4(46378), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4531 //
16778 /* 46313 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
16779 /* 46318 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16780 /* 46321 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16781 /* 46324 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16782 /* 46327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16783 /* 46331 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
16784 /* 46335 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16785 /* 46339 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3847:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16786 /* 46339 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16787 /* 46342 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16788 /* 46346 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16789 /* 46351 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32m),
16790 /* 46354 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16791 /* 46356 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16792 /* 46358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16793 /* 46361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16794 /* 46367 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16795 /* 46373 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16796 /* 46376 */ GIR_RootConstrainSelectedInstOperands,
16797 /* 46377 */ // GIR_Coverage, 4531,
16798 /* 46377 */ GIR_EraseRootFromParent_Done,
16799 /* 46378 */ // Label 1394: @46378
16800 /* 46378 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1395*/ GIMT_Encode4(46450), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4533 //
16801 /* 46385 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
16802 /* 46390 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16803 /* 46393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16804 /* 46396 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16805 /* 46399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16806 /* 46403 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16807 /* 46407 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16808 /* 46411 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3845:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16809 /* 46411 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16810 /* 46414 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16811 /* 46418 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16812 /* 46423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32a),
16813 /* 46426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16814 /* 46428 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16815 /* 46430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16816 /* 46433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16817 /* 46439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16818 /* 46445 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16819 /* 46448 */ GIR_RootConstrainSelectedInstOperands,
16820 /* 46449 */ // GIR_Coverage, 4533,
16821 /* 46449 */ GIR_EraseRootFromParent_Done,
16822 /* 46450 */ // Label 1395: @46450
16823 /* 46450 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1396*/ GIMT_Encode4(46522), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4535 //
16824 /* 46457 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
16825 /* 46462 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16826 /* 46465 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16827 /* 46468 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16828 /* 46471 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16829 /* 46475 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16830 /* 46479 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16831 /* 46483 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3849:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16832 /* 46483 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16833 /* 46486 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16834 /* 46490 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16835 /* 46495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32n),
16836 /* 46498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16837 /* 46500 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16838 /* 46502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16839 /* 46505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16840 /* 46511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16841 /* 46517 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16842 /* 46520 */ GIR_RootConstrainSelectedInstOperands,
16843 /* 46521 */ // GIR_Coverage, 4535,
16844 /* 46521 */ GIR_EraseRootFromParent_Done,
16845 /* 46522 */ // Label 1396: @46522
16846 /* 46522 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1397*/ GIMT_Encode4(46594), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4537 //
16847 /* 46529 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
16848 /* 46534 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16849 /* 46537 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16850 /* 46540 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16851 /* 46543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16852 /* 46547 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16853 /* 46551 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16854 /* 46555 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3851:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16855 /* 46555 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16856 /* 46558 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16857 /* 46562 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16858 /* 46567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32p),
16859 /* 46570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16860 /* 46572 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16861 /* 46574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16862 /* 46577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16863 /* 46583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16864 /* 46589 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16865 /* 46592 */ GIR_RootConstrainSelectedInstOperands,
16866 /* 46593 */ // GIR_Coverage, 4537,
16867 /* 46593 */ GIR_EraseRootFromParent_Done,
16868 /* 46594 */ // Label 1397: @46594
16869 /* 46594 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1398*/ GIMT_Encode4(46666), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4539 //
16870 /* 46601 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
16871 /* 46606 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16872 /* 46609 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16873 /* 46612 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
16874 /* 46615 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16875 /* 46619 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
16876 /* 46623 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16877 /* 46627 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3847:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
16878 /* 46627 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16879 /* 46630 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16880 /* 46634 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16881 /* 46639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32m),
16882 /* 46642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16883 /* 46644 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
16884 /* 46646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16885 /* 46649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16886 /* 46655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16887 /* 46661 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16888 /* 46664 */ GIR_RootConstrainSelectedInstOperands,
16889 /* 46665 */ // GIR_Coverage, 4539,
16890 /* 46665 */ GIR_EraseRootFromParent_Done,
16891 /* 46666 */ // Label 1398: @46666
16892 /* 46666 */ GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(46942),
16893 /* 46671 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp),
16894 /* 46676 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1402*/ GIMT_Encode4(46941),
16895 /* 46687 */ /*GILLT_v8s16*//*Label 1400*/ GIMT_Encode4(46699), GIMT_Encode4(0),
16896 /* 46695 */ /*GILLT_v4s32*//*Label 1401*/ GIMT_Encode4(46820),
16897 /* 46699 */ // Label 1400: @46699
16898 /* 46699 */ GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(46819),
16899 /* 46704 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16900 /* 46707 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16901 /* 46710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16902 /* 46714 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16903 /* 46718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1404*/ GIMT_Encode4(46768), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4542 //
16904 /* 46725 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
16905 /* 46729 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3840:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$src, 0:{ *:[i32] }) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
16906 /* 46729 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16907 /* 46732 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16908 /* 46736 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16909 /* 46741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z),
16910 /* 46744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16911 /* 46746 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
16912 /* 46748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16913 /* 46751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16914 /* 46757 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16915 /* 46763 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16916 /* 46766 */ GIR_RootConstrainSelectedInstOperands,
16917 /* 46767 */ // GIR_Coverage, 4542,
16918 /* 46767 */ GIR_EraseRootFromParent_Done,
16919 /* 46768 */ // Label 1404: @46768
16920 /* 46768 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1405*/ GIMT_Encode4(46818), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4545 //
16921 /* 46775 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
16922 /* 46779 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3840:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$src, 1:{ *:[i32] }) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
16923 /* 46779 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16924 /* 46782 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16925 /* 46786 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16926 /* 46791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z),
16927 /* 46794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16928 /* 46796 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
16929 /* 46798 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16930 /* 46801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16931 /* 46807 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16932 /* 46813 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16933 /* 46816 */ GIR_RootConstrainSelectedInstOperands,
16934 /* 46817 */ // GIR_Coverage, 4545,
16935 /* 46817 */ GIR_EraseRootFromParent_Done,
16936 /* 46818 */ // Label 1405: @46818
16937 /* 46818 */ GIM_Reject,
16938 /* 46819 */ // Label 1403: @46819
16939 /* 46819 */ GIM_Reject,
16940 /* 46820 */ // Label 1401: @46820
16941 /* 46820 */ GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(46940),
16942 /* 46825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16943 /* 46828 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16944 /* 46831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16945 /* 46835 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16946 /* 46839 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1407*/ GIMT_Encode4(46889), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4548 //
16947 /* 46846 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
16948 /* 46850 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3840:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$src, 0:{ *:[i32] }) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
16949 /* 46850 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16950 /* 46853 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16951 /* 46857 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16952 /* 46862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z),
16953 /* 46865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16954 /* 46867 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
16955 /* 46869 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16956 /* 46872 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16957 /* 46878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16958 /* 46884 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16959 /* 46887 */ GIR_RootConstrainSelectedInstOperands,
16960 /* 46888 */ // GIR_Coverage, 4548,
16961 /* 46888 */ GIR_EraseRootFromParent_Done,
16962 /* 46889 */ // Label 1407: @46889
16963 /* 46889 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1408*/ GIMT_Encode4(46939), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4551 //
16964 /* 46896 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
16965 /* 46900 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3840:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$src, 1:{ *:[i32] }) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
16966 /* 46900 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16967 /* 46903 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16968 /* 46907 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16969 /* 46912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z),
16970 /* 46915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16971 /* 46917 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
16972 /* 46919 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16973 /* 46922 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16974 /* 46928 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16975 /* 46934 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16976 /* 46937 */ GIR_RootConstrainSelectedInstOperands,
16977 /* 46938 */ // GIR_Coverage, 4551,
16978 /* 46938 */ GIR_EraseRootFromParent_Done,
16979 /* 46939 */ // Label 1408: @46939
16980 /* 46939 */ GIM_Reject,
16981 /* 46940 */ // Label 1406: @46940
16982 /* 46940 */ GIM_Reject,
16983 /* 46941 */ // Label 1402: @46941
16984 /* 46941 */ GIM_Reject,
16985 /* 46942 */ // Label 1399: @46942
16986 /* 46942 */ GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(47218),
16987 /* 46947 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int),
16988 /* 46952 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 1412*/ GIMT_Encode4(47217),
16989 /* 46963 */ /*GILLT_v8s16*//*Label 1410*/ GIMT_Encode4(46975), GIMT_Encode4(0),
16990 /* 46971 */ /*GILLT_v4s32*//*Label 1411*/ GIMT_Encode4(47096),
16991 /* 46975 */ // Label 1410: @46975
16992 /* 46975 */ GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(47095),
16993 /* 46980 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16994 /* 46983 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
16995 /* 46986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16996 /* 46990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16997 /* 46994 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1414*/ GIMT_Encode4(47044), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4554 //
16998 /* 47001 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
16999 /* 47005 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3838:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 0:{ *:[i32] }) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
17000 /* 47005 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17001 /* 47008 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17002 /* 47012 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17003 /* 47017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n),
17004 /* 47020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17005 /* 47022 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17006 /* 47024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17007 /* 47027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17008 /* 47033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17009 /* 47039 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17010 /* 47042 */ GIR_RootConstrainSelectedInstOperands,
17011 /* 47043 */ // GIR_Coverage, 4554,
17012 /* 47043 */ GIR_EraseRootFromParent_Done,
17013 /* 47044 */ // Label 1414: @47044
17014 /* 47044 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1415*/ GIMT_Encode4(47094), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4557 //
17015 /* 47051 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
17016 /* 47055 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3838:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 1:{ *:[i32] }) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
17017 /* 47055 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17018 /* 47058 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17019 /* 47062 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17020 /* 47067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n),
17021 /* 47070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17022 /* 47072 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17023 /* 47074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17024 /* 47077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17025 /* 47083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17026 /* 47089 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17027 /* 47092 */ GIR_RootConstrainSelectedInstOperands,
17028 /* 47093 */ // GIR_Coverage, 4557,
17029 /* 47093 */ GIR_EraseRootFromParent_Done,
17030 /* 47094 */ // Label 1415: @47094
17031 /* 47094 */ GIM_Reject,
17032 /* 47095 */ // Label 1413: @47095
17033 /* 47095 */ GIM_Reject,
17034 /* 47096 */ // Label 1411: @47096
17035 /* 47096 */ GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(47216),
17036 /* 47101 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17037 /* 47104 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17038 /* 47107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17039 /* 47111 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17040 /* 47115 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1417*/ GIMT_Encode4(47165), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4560 //
17041 /* 47122 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17042 /* 47126 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3838:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, 0:{ *:[i32] }) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
17043 /* 47126 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17044 /* 47129 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17045 /* 47133 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17046 /* 47138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n),
17047 /* 47141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17048 /* 47143 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17049 /* 47145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17050 /* 47148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17051 /* 47154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17052 /* 47160 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17053 /* 47163 */ GIR_RootConstrainSelectedInstOperands,
17054 /* 47164 */ // GIR_Coverage, 4560,
17055 /* 47164 */ GIR_EraseRootFromParent_Done,
17056 /* 47165 */ // Label 1417: @47165
17057 /* 47165 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1418*/ GIMT_Encode4(47215), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4563 //
17058 /* 47172 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
17059 /* 47176 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3838:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, 1:{ *:[i32] }) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
17060 /* 47176 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17061 /* 47179 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17062 /* 47183 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17063 /* 47188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n),
17064 /* 47191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17065 /* 47193 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17066 /* 47195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17067 /* 47198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17068 /* 47204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17069 /* 47210 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17070 /* 47213 */ GIR_RootConstrainSelectedInstOperands,
17071 /* 47214 */ // GIR_Coverage, 4563,
17072 /* 47214 */ GIR_EraseRootFromParent_Done,
17073 /* 47215 */ // Label 1418: @47215
17074 /* 47215 */ GIM_Reject,
17075 /* 47216 */ // Label 1416: @47216
17076 /* 47216 */ GIM_Reject,
17077 /* 47217 */ // Label 1412: @47217
17078 /* 47217 */ GIM_Reject,
17079 /* 47218 */ // Label 1409: @47218
17080 /* 47218 */ GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(47346),
17081 /* 47223 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen),
17082 /* 47228 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17083 /* 47231 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17084 /* 47234 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17085 /* 47237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17086 /* 47241 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17087 /* 47245 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1420*/ GIMT_Encode4(47295), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5043 //
17088 /* 47252 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17089 /* 47256 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3843:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf32f16bh:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm)
17090 /* 47256 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17091 /* 47259 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17092 /* 47263 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17093 /* 47268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16bh),
17094 /* 47271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17095 /* 47273 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
17096 /* 47275 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17097 /* 47278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17098 /* 47284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17099 /* 47290 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17100 /* 47293 */ GIR_RootConstrainSelectedInstOperands,
17101 /* 47294 */ // GIR_Coverage, 5043,
17102 /* 47294 */ GIR_EraseRootFromParent_Done,
17103 /* 47295 */ // Label 1420: @47295
17104 /* 47295 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1421*/ GIMT_Encode4(47345), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5049 //
17105 /* 47302 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
17106 /* 47306 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3843:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf32f16th:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm)
17107 /* 47306 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17108 /* 47309 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17109 /* 47313 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17110 /* 47318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16th),
17111 /* 47321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17112 /* 47323 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
17113 /* 47325 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17114 /* 47328 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17115 /* 47334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17116 /* 47340 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17117 /* 47343 */ GIR_RootConstrainSelectedInstOperands,
17118 /* 47344 */ // GIR_Coverage, 5049,
17119 /* 47344 */ GIR_EraseRootFromParent_Done,
17120 /* 47345 */ // Label 1421: @47345
17121 /* 47345 */ GIM_Reject,
17122 /* 47346 */ // Label 1419: @47346
17123 /* 47346 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1422*/ GIMT_Encode4(47413), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2069 //
17124 /* 47353 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
17125 /* 47358 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17126 /* 47361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17127 /* 47364 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17128 /* 47367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17129 /* 47371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17130 /* 47375 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17131 /* 47379 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17132 /* 47383 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17133 /* 47387 */ // MIs[1] Operand 1
17134 /* 47387 */ // No operand predicates
17135 /* 47387 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17136 /* 47389 */ // (intrinsic_wo_chain:{ *:[i32] } 4169:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, 0:{ *:[i32] })
17137 /* 47389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT),
17138 /* 47392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17139 /* 47394 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17140 /* 47397 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
17141 /* 47399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17142 /* 47402 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17143 /* 47405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17144 /* 47411 */ GIR_RootConstrainSelectedInstOperands,
17145 /* 47412 */ // GIR_Coverage, 2069,
17146 /* 47412 */ GIR_EraseRootFromParent_Done,
17147 /* 47413 */ // Label 1422: @47413
17148 /* 47413 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1423*/ GIMT_Encode4(47477), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2073 //
17149 /* 47420 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16),
17150 /* 47425 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17151 /* 47428 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17152 /* 47431 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17153 /* 47434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17154 /* 47438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17155 /* 47442 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17156 /* 47446 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17157 /* 47450 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
17158 /* 47454 */ // MIs[1] Operand 1
17159 /* 47454 */ // No operand predicates
17160 /* 47454 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17161 /* 47456 */ // (intrinsic_wo_chain:{ *:[i32] } 4170:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPRnopc:{ *:[i32] }:$a)
17162 /* 47456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT16),
17163 /* 47459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17164 /* 47461 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17165 /* 47464 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
17166 /* 47466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17167 /* 47469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17168 /* 47475 */ GIR_RootConstrainSelectedInstOperands,
17169 /* 47476 */ // GIR_Coverage, 2073,
17170 /* 47476 */ GIR_EraseRootFromParent_Done,
17171 /* 47477 */ // Label 1423: @47477
17172 /* 47477 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1424*/ GIMT_Encode4(47544), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2345 //
17173 /* 47484 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
17174 /* 47489 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17175 /* 47492 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17176 /* 47495 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17177 /* 47498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17178 /* 47502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
17179 /* 47506 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17180 /* 47510 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17181 /* 47514 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17182 /* 47518 */ // MIs[1] Operand 1
17183 /* 47518 */ // No operand predicates
17184 /* 47518 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17185 /* 47520 */ // (intrinsic_wo_chain:{ *:[i32] } 4169:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPR:{ *:[i32] }:$a, 0:{ *:[i32] })
17186 /* 47520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT),
17187 /* 47523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17188 /* 47525 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17189 /* 47528 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
17190 /* 47530 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17191 /* 47533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17192 /* 47536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17193 /* 47542 */ GIR_RootConstrainSelectedInstOperands,
17194 /* 47543 */ // GIR_Coverage, 2345,
17195 /* 47543 */ GIR_EraseRootFromParent_Done,
17196 /* 47544 */ // Label 1424: @47544
17197 /* 47544 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1425*/ GIMT_Encode4(47608), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2347 //
17198 /* 47551 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16),
17199 /* 47556 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17200 /* 47559 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17201 /* 47562 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17202 /* 47565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17203 /* 47569 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
17204 /* 47573 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17205 /* 47577 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17206 /* 47581 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
17207 /* 47585 */ // MIs[1] Operand 1
17208 /* 47585 */ // No operand predicates
17209 /* 47585 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17210 /* 47587 */ // (intrinsic_wo_chain:{ *:[i32] } 4170:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (t2USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPR:{ *:[i32] }:$a)
17211 /* 47587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT16),
17212 /* 47590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17213 /* 47592 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
17214 /* 47595 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
17215 /* 47597 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17216 /* 47600 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17217 /* 47606 */ GIR_RootConstrainSelectedInstOperands,
17218 /* 47607 */ // GIR_Coverage, 2347,
17219 /* 47607 */ GIR_EraseRootFromParent_Done,
17220 /* 47608 */ // Label 1425: @47608
17221 /* 47608 */ GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(47878),
17222 /* 47613 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm),
17223 /* 47618 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 1430*/ GIMT_Encode4(47877),
17224 /* 47629 */ /*GILLT_v16s8*//*Label 1427*/ GIMT_Encode4(47649), GIMT_Encode4(0),
17225 /* 47637 */ /*GILLT_v8s16*//*Label 1428*/ GIMT_Encode4(47725), GIMT_Encode4(0),
17226 /* 47645 */ /*GILLT_v4s32*//*Label 1429*/ GIMT_Encode4(47801),
17227 /* 47649 */ // Label 1427: @47649
17228 /* 47649 */ GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(47724), // Rule ID 4331 //
17229 /* 47654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
17230 /* 47657 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17231 /* 47660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17232 /* 47664 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17233 /* 47668 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17234 /* 47672 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17235 /* 47676 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
17236 /* 47680 */ // MIs[1] Operand 1
17237 /* 47680 */ // No operand predicates
17238 /* 47680 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17239 /* 47682 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3907:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) => (MVE_VQSHLU_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
17240 /* 47682 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17241 /* 47685 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17242 /* 47689 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17243 /* 47694 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms8),
17244 /* 47697 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17245 /* 47699 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17246 /* 47701 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17247 /* 47704 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17248 /* 47707 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17249 /* 47713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17250 /* 47719 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17251 /* 47722 */ GIR_RootConstrainSelectedInstOperands,
17252 /* 47723 */ // GIR_Coverage, 4331,
17253 /* 47723 */ GIR_EraseRootFromParent_Done,
17254 /* 47724 */ // Label 1431: @47724
17255 /* 47724 */ GIM_Reject,
17256 /* 47725 */ // Label 1428: @47725
17257 /* 47725 */ GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(47800), // Rule ID 4333 //
17258 /* 47730 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17259 /* 47733 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17260 /* 47736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17261 /* 47740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17262 /* 47744 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17263 /* 47748 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17264 /* 47752 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
17265 /* 47756 */ // MIs[1] Operand 1
17266 /* 47756 */ // No operand predicates
17267 /* 47756 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17268 /* 47758 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3907:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (MVE_VQSHLU_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
17269 /* 47758 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17270 /* 47761 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17271 /* 47765 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17272 /* 47770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms16),
17273 /* 47773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17274 /* 47775 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17275 /* 47777 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17276 /* 47780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17277 /* 47783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17278 /* 47789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17279 /* 47795 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17280 /* 47798 */ GIR_RootConstrainSelectedInstOperands,
17281 /* 47799 */ // GIR_Coverage, 4333,
17282 /* 47799 */ GIR_EraseRootFromParent_Done,
17283 /* 47800 */ // Label 1432: @47800
17284 /* 47800 */ GIM_Reject,
17285 /* 47801 */ // Label 1429: @47801
17286 /* 47801 */ GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(47876), // Rule ID 4335 //
17287 /* 47806 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17288 /* 47809 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17289 /* 47812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17290 /* 47816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17291 /* 47820 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17292 /* 47824 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17293 /* 47828 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17294 /* 47832 */ // MIs[1] Operand 1
17295 /* 47832 */ // No operand predicates
17296 /* 47832 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17297 /* 47834 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3907:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) => (MVE_VQSHLU_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
17298 /* 47834 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17299 /* 47837 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17300 /* 47841 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17301 /* 47846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms32),
17302 /* 47849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17303 /* 47851 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17304 /* 47853 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17305 /* 47856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17306 /* 47859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17307 /* 47865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17308 /* 47871 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17309 /* 47874 */ GIR_RootConstrainSelectedInstOperands,
17310 /* 47875 */ // GIR_Coverage, 4335,
17311 /* 47875 */ GIR_EraseRootFromParent_Done,
17312 /* 47876 */ // Label 1433: @47876
17313 /* 47876 */ GIM_Reject,
17314 /* 47877 */ // Label 1430: @47877
17315 /* 47877 */ GIM_Reject,
17316 /* 47878 */ // Label 1426: @47878
17317 /* 47878 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1434*/ GIMT_Encode4(47938), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1814 //
17318 /* 47885 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
17319 /* 47890 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
17320 /* 47893 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
17321 /* 47896 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17322 /* 47899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17323 /* 47903 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17324 /* 47907 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17325 /* 47911 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17326 /* 47915 */ // MIs[1] Operand 1
17327 /* 47915 */ // No operand predicates
17328 /* 47915 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17329 /* 47917 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3991:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17330 /* 47917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsd),
17331 /* 47920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17332 /* 47922 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17333 /* 47924 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17334 /* 47927 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17335 /* 47930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17336 /* 47936 */ GIR_RootConstrainSelectedInstOperands,
17337 /* 47937 */ // GIR_Coverage, 1814,
17338 /* 47937 */ GIR_EraseRootFromParent_Done,
17339 /* 47938 */ // Label 1434: @47938
17340 /* 47938 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1435*/ GIMT_Encode4(47998), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1815 //
17341 /* 47945 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
17342 /* 47950 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
17343 /* 47953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
17344 /* 47956 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17345 /* 47959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17346 /* 47963 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17347 /* 47967 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17348 /* 47971 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17349 /* 47975 */ // MIs[1] Operand 1
17350 /* 47975 */ // No operand predicates
17351 /* 47975 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17352 /* 47977 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3992:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17353 /* 47977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xud),
17354 /* 47980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17355 /* 47982 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17356 /* 47984 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17357 /* 47987 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17358 /* 47990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17359 /* 47996 */ GIR_RootConstrainSelectedInstOperands,
17360 /* 47997 */ // GIR_Coverage, 1815,
17361 /* 47997 */ GIR_EraseRootFromParent_Done,
17362 /* 47998 */ // Label 1435: @47998
17363 /* 47998 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1436*/ GIMT_Encode4(48058), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1816 //
17364 /* 48005 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
17365 /* 48010 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
17366 /* 48013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
17367 /* 48016 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17368 /* 48019 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17369 /* 48023 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17370 /* 48027 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17371 /* 48031 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17372 /* 48035 */ // MIs[1] Operand 1
17373 /* 48035 */ // No operand predicates
17374 /* 48035 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17375 /* 48037 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3994:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17376 /* 48037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fd),
17377 /* 48040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17378 /* 48042 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17379 /* 48044 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17380 /* 48047 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17381 /* 48050 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17382 /* 48056 */ GIR_RootConstrainSelectedInstOperands,
17383 /* 48057 */ // GIR_Coverage, 1816,
17384 /* 48057 */ GIR_EraseRootFromParent_Done,
17385 /* 48058 */ // Label 1436: @48058
17386 /* 48058 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1437*/ GIMT_Encode4(48118), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1817 //
17387 /* 48065 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
17388 /* 48070 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
17389 /* 48073 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
17390 /* 48076 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17391 /* 48079 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17392 /* 48083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17393 /* 48087 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17394 /* 48091 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17395 /* 48095 */ // MIs[1] Operand 1
17396 /* 48095 */ // No operand predicates
17397 /* 48095 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17398 /* 48097 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3995:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17399 /* 48097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fd),
17400 /* 48100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17401 /* 48102 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17402 /* 48104 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17403 /* 48107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17404 /* 48110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17405 /* 48116 */ GIR_RootConstrainSelectedInstOperands,
17406 /* 48117 */ // GIR_Coverage, 1817,
17407 /* 48117 */ GIR_EraseRootFromParent_Done,
17408 /* 48118 */ // Label 1437: @48118
17409 /* 48118 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1438*/ GIMT_Encode4(48178), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1818 //
17410 /* 48125 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
17411 /* 48130 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
17412 /* 48133 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
17413 /* 48136 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17414 /* 48139 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17415 /* 48143 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17416 /* 48147 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17417 /* 48151 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17418 /* 48155 */ // MIs[1] Operand 1
17419 /* 48155 */ // No operand predicates
17420 /* 48155 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17421 /* 48157 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3991:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17422 /* 48157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsd),
17423 /* 48160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17424 /* 48162 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17425 /* 48164 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17426 /* 48167 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17427 /* 48170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17428 /* 48176 */ GIR_RootConstrainSelectedInstOperands,
17429 /* 48177 */ // GIR_Coverage, 1818,
17430 /* 48177 */ GIR_EraseRootFromParent_Done,
17431 /* 48178 */ // Label 1438: @48178
17432 /* 48178 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1439*/ GIMT_Encode4(48238), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1819 //
17433 /* 48185 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
17434 /* 48190 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
17435 /* 48193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
17436 /* 48196 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17437 /* 48199 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17438 /* 48203 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17439 /* 48207 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17440 /* 48211 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17441 /* 48215 */ // MIs[1] Operand 1
17442 /* 48215 */ // No operand predicates
17443 /* 48215 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17444 /* 48217 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3992:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17445 /* 48217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xud),
17446 /* 48220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17447 /* 48222 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17448 /* 48224 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17449 /* 48227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17450 /* 48230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17451 /* 48236 */ GIR_RootConstrainSelectedInstOperands,
17452 /* 48237 */ // GIR_Coverage, 1819,
17453 /* 48237 */ GIR_EraseRootFromParent_Done,
17454 /* 48238 */ // Label 1439: @48238
17455 /* 48238 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1440*/ GIMT_Encode4(48298), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1820 //
17456 /* 48245 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
17457 /* 48250 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
17458 /* 48253 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
17459 /* 48256 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17460 /* 48259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17461 /* 48263 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17462 /* 48267 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17463 /* 48271 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17464 /* 48275 */ // MIs[1] Operand 1
17465 /* 48275 */ // No operand predicates
17466 /* 48275 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17467 /* 48277 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3994:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17468 /* 48277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hd),
17469 /* 48280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17470 /* 48282 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17471 /* 48284 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17472 /* 48287 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17473 /* 48290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17474 /* 48296 */ GIR_RootConstrainSelectedInstOperands,
17475 /* 48297 */ // GIR_Coverage, 1820,
17476 /* 48297 */ GIR_EraseRootFromParent_Done,
17477 /* 48298 */ // Label 1440: @48298
17478 /* 48298 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1441*/ GIMT_Encode4(48358), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1821 //
17479 /* 48305 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
17480 /* 48310 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
17481 /* 48313 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
17482 /* 48316 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17483 /* 48319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17484 /* 48323 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
17485 /* 48327 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17486 /* 48331 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17487 /* 48335 */ // MIs[1] Operand 1
17488 /* 48335 */ // No operand predicates
17489 /* 48335 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17490 /* 48337 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3995:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17491 /* 48337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hd),
17492 /* 48340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17493 /* 48342 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17494 /* 48344 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17495 /* 48347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17496 /* 48350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17497 /* 48356 */ GIR_RootConstrainSelectedInstOperands,
17498 /* 48357 */ // GIR_Coverage, 1821,
17499 /* 48357 */ GIR_EraseRootFromParent_Done,
17500 /* 48358 */ // Label 1441: @48358
17501 /* 48358 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1442*/ GIMT_Encode4(48418), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1822 //
17502 /* 48365 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
17503 /* 48370 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17504 /* 48373 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17505 /* 48376 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17506 /* 48379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17507 /* 48383 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17508 /* 48387 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17509 /* 48391 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17510 /* 48395 */ // MIs[1] Operand 1
17511 /* 48395 */ // No operand predicates
17512 /* 48395 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17513 /* 48397 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3991:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17514 /* 48397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsq),
17515 /* 48400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17516 /* 48402 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17517 /* 48404 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17518 /* 48407 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17519 /* 48410 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17520 /* 48416 */ GIR_RootConstrainSelectedInstOperands,
17521 /* 48417 */ // GIR_Coverage, 1822,
17522 /* 48417 */ GIR_EraseRootFromParent_Done,
17523 /* 48418 */ // Label 1442: @48418
17524 /* 48418 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1443*/ GIMT_Encode4(48478), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1823 //
17525 /* 48425 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
17526 /* 48430 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17527 /* 48433 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17528 /* 48436 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17529 /* 48439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17530 /* 48443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17531 /* 48447 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17532 /* 48451 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17533 /* 48455 */ // MIs[1] Operand 1
17534 /* 48455 */ // No operand predicates
17535 /* 48455 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17536 /* 48457 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3992:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xuq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17537 /* 48457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xuq),
17538 /* 48460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17539 /* 48462 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17540 /* 48464 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17541 /* 48467 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17542 /* 48470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17543 /* 48476 */ GIR_RootConstrainSelectedInstOperands,
17544 /* 48477 */ // GIR_Coverage, 1823,
17545 /* 48477 */ GIR_EraseRootFromParent_Done,
17546 /* 48478 */ // Label 1443: @48478
17547 /* 48478 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1444*/ GIMT_Encode4(48538), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1824 //
17548 /* 48485 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
17549 /* 48490 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17550 /* 48493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17551 /* 48496 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17552 /* 48499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17553 /* 48503 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17554 /* 48507 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17555 /* 48511 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17556 /* 48515 */ // MIs[1] Operand 1
17557 /* 48515 */ // No operand predicates
17558 /* 48515 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17559 /* 48517 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3994:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17560 /* 48517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fq),
17561 /* 48520 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17562 /* 48522 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17563 /* 48524 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17564 /* 48527 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17565 /* 48530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17566 /* 48536 */ GIR_RootConstrainSelectedInstOperands,
17567 /* 48537 */ // GIR_Coverage, 1824,
17568 /* 48537 */ GIR_EraseRootFromParent_Done,
17569 /* 48538 */ // Label 1444: @48538
17570 /* 48538 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1445*/ GIMT_Encode4(48598), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1825 //
17571 /* 48545 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
17572 /* 48550 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17573 /* 48553 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17574 /* 48556 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17575 /* 48559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17576 /* 48563 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17577 /* 48567 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17578 /* 48571 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17579 /* 48575 */ // MIs[1] Operand 1
17580 /* 48575 */ // No operand predicates
17581 /* 48575 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17582 /* 48577 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3995:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17583 /* 48577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fq),
17584 /* 48580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17585 /* 48582 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17586 /* 48584 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17587 /* 48587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17588 /* 48590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17589 /* 48596 */ GIR_RootConstrainSelectedInstOperands,
17590 /* 48597 */ // GIR_Coverage, 1825,
17591 /* 48597 */ GIR_EraseRootFromParent_Done,
17592 /* 48598 */ // Label 1445: @48598
17593 /* 48598 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1446*/ GIMT_Encode4(48658), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1826 //
17594 /* 48605 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
17595 /* 48610 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17596 /* 48613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17597 /* 48616 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17598 /* 48619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17599 /* 48623 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17600 /* 48627 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17601 /* 48631 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17602 /* 48635 */ // MIs[1] Operand 1
17603 /* 48635 */ // No operand predicates
17604 /* 48635 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17605 /* 48637 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3991:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17606 /* 48637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsq),
17607 /* 48640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17608 /* 48642 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17609 /* 48644 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17610 /* 48647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17611 /* 48650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17612 /* 48656 */ GIR_RootConstrainSelectedInstOperands,
17613 /* 48657 */ // GIR_Coverage, 1826,
17614 /* 48657 */ GIR_EraseRootFromParent_Done,
17615 /* 48658 */ // Label 1446: @48658
17616 /* 48658 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1447*/ GIMT_Encode4(48718), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1827 //
17617 /* 48665 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
17618 /* 48670 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17619 /* 48673 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17620 /* 48676 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17621 /* 48679 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17622 /* 48683 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17623 /* 48687 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17624 /* 48691 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17625 /* 48695 */ // MIs[1] Operand 1
17626 /* 48695 */ // No operand predicates
17627 /* 48695 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17628 /* 48697 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3992:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xuq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17629 /* 48697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xuq),
17630 /* 48700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17631 /* 48702 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17632 /* 48704 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17633 /* 48707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17634 /* 48710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17635 /* 48716 */ GIR_RootConstrainSelectedInstOperands,
17636 /* 48717 */ // GIR_Coverage, 1827,
17637 /* 48717 */ GIR_EraseRootFromParent_Done,
17638 /* 48718 */ // Label 1447: @48718
17639 /* 48718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1448*/ GIMT_Encode4(48778), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1828 //
17640 /* 48725 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
17641 /* 48730 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17642 /* 48733 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17643 /* 48736 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17644 /* 48739 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17645 /* 48743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17646 /* 48747 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17647 /* 48751 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17648 /* 48755 */ // MIs[1] Operand 1
17649 /* 48755 */ // No operand predicates
17650 /* 48755 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17651 /* 48757 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3994:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17652 /* 48757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hq),
17653 /* 48760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17654 /* 48762 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17655 /* 48764 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17656 /* 48767 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17657 /* 48770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17658 /* 48776 */ GIR_RootConstrainSelectedInstOperands,
17659 /* 48777 */ // GIR_Coverage, 1828,
17660 /* 48777 */ GIR_EraseRootFromParent_Done,
17661 /* 48778 */ // Label 1448: @48778
17662 /* 48778 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1449*/ GIMT_Encode4(48838), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1829 //
17663 /* 48785 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
17664 /* 48790 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17665 /* 48793 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17666 /* 48796 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17667 /* 48799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17668 /* 48803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
17669 /* 48807 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17670 /* 48811 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17671 /* 48815 */ // MIs[1] Operand 1
17672 /* 48815 */ // No operand predicates
17673 /* 48815 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17674 /* 48817 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3995:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
17675 /* 48817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hq),
17676 /* 48820 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
17677 /* 48822 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
17678 /* 48824 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
17679 /* 48827 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17680 /* 48830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17681 /* 48836 */ GIR_RootConstrainSelectedInstOperands,
17682 /* 48837 */ // GIR_Coverage, 1829,
17683 /* 48837 */ GIR_EraseRootFromParent_Done,
17684 /* 48838 */ // Label 1449: @48838
17685 /* 48838 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1450*/ GIMT_Encode4(48898), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1911 //
17686 /* 48845 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqshl),
17687 /* 48850 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17688 /* 48853 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17689 /* 48856 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17690 /* 48859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17691 /* 48863 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17692 /* 48867 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17693 /* 48871 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17694 /* 48875 */ // MIs[1] Operand 1
17695 /* 48875 */ // No operand predicates
17696 /* 48875 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17697 /* 48877 */ // (intrinsic_wo_chain:{ *:[i32] } 3806:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17698 /* 48877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQSHL),
17699 /* 48880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
17700 /* 48882 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
17701 /* 48884 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17702 /* 48887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17703 /* 48890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17704 /* 48896 */ GIR_RootConstrainSelectedInstOperands,
17705 /* 48897 */ // GIR_Coverage, 1911,
17706 /* 48897 */ GIR_EraseRootFromParent_Done,
17707 /* 48898 */ // Label 1450: @48898
17708 /* 48898 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1451*/ GIMT_Encode4(48958), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1912 //
17709 /* 48905 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_srshr),
17710 /* 48910 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17711 /* 48913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17712 /* 48916 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17713 /* 48919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17714 /* 48923 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17715 /* 48927 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17716 /* 48931 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17717 /* 48935 */ // MIs[1] Operand 1
17718 /* 48935 */ // No operand predicates
17719 /* 48935 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17720 /* 48937 */ // (intrinsic_wo_chain:{ *:[i32] } 3808:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17721 /* 48937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SRSHR),
17722 /* 48940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
17723 /* 48942 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
17724 /* 48944 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17725 /* 48947 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17726 /* 48950 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17727 /* 48956 */ GIR_RootConstrainSelectedInstOperands,
17728 /* 48957 */ // GIR_Coverage, 1912,
17729 /* 48957 */ GIR_EraseRootFromParent_Done,
17730 /* 48958 */ // Label 1451: @48958
17731 /* 48958 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1452*/ GIMT_Encode4(49018), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1913 //
17732 /* 48965 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqshl),
17733 /* 48970 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17734 /* 48973 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17735 /* 48976 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17736 /* 48979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17737 /* 48983 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17738 /* 48987 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17739 /* 48991 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17740 /* 48995 */ // MIs[1] Operand 1
17741 /* 48995 */ // No operand predicates
17742 /* 48995 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17743 /* 48997 */ // (intrinsic_wo_chain:{ *:[i32] } 3813:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_UQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17744 /* 48997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQSHL),
17745 /* 49000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
17746 /* 49002 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
17747 /* 49004 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17748 /* 49007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17749 /* 49010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17750 /* 49016 */ GIR_RootConstrainSelectedInstOperands,
17751 /* 49017 */ // GIR_Coverage, 1913,
17752 /* 49017 */ GIR_EraseRootFromParent_Done,
17753 /* 49018 */ // Label 1452: @49018
17754 /* 49018 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1453*/ GIMT_Encode4(49078), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1914 //
17755 /* 49025 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_urshr),
17756 /* 49030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17757 /* 49033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17758 /* 49036 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17759 /* 49039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17760 /* 49043 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17761 /* 49047 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17762 /* 49051 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17763 /* 49055 */ // MIs[1] Operand 1
17764 /* 49055 */ // No operand predicates
17765 /* 49055 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17766 /* 49057 */ // (intrinsic_wo_chain:{ *:[i32] } 3815:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_URSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
17767 /* 49057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_URSHR),
17768 /* 49060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
17769 /* 49062 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
17770 /* 49064 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
17771 /* 49067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17772 /* 49070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17773 /* 49076 */ GIR_RootConstrainSelectedInstOperands,
17774 /* 49077 */ // GIR_Coverage, 1914,
17775 /* 49077 */ GIR_EraseRootFromParent_Done,
17776 /* 49078 */ // Label 1453: @49078
17777 /* 49078 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1454*/ GIMT_Encode4(49131), GIMT_Encode2(GIFBS_IsARM), // Rule ID 104 //
17778 /* 49085 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8),
17779 /* 49090 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17780 /* 49093 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17781 /* 49096 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17782 /* 49099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17783 /* 49103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17784 /* 49107 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17785 /* 49111 */ // (intrinsic_wo_chain:{ *:[i32] } 4094:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17786 /* 49111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD8),
17787 /* 49114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17788 /* 49116 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17789 /* 49118 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17790 /* 49120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17791 /* 49123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17792 /* 49129 */ GIR_RootConstrainSelectedInstOperands,
17793 /* 49130 */ // GIR_Coverage, 104,
17794 /* 49130 */ GIR_EraseRootFromParent_Done,
17795 /* 49131 */ // Label 1454: @49131
17796 /* 49131 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1455*/ GIMT_Encode4(49184), GIMT_Encode2(GIFBS_IsARM), // Rule ID 105 //
17797 /* 49138 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16),
17798 /* 49143 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17799 /* 49146 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17800 /* 49149 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17801 /* 49152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17802 /* 49156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17803 /* 49160 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17804 /* 49164 */ // (intrinsic_wo_chain:{ *:[i32] } 4093:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17805 /* 49164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD16),
17806 /* 49167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17807 /* 49169 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17808 /* 49171 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17809 /* 49173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17810 /* 49176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17811 /* 49182 */ GIR_RootConstrainSelectedInstOperands,
17812 /* 49183 */ // GIR_Coverage, 105,
17813 /* 49183 */ GIR_EraseRootFromParent_Done,
17814 /* 49184 */ // Label 1455: @49184
17815 /* 49184 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1456*/ GIMT_Encode4(49237), GIMT_Encode2(GIFBS_IsARM), // Rule ID 106 //
17816 /* 49191 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16),
17817 /* 49196 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17818 /* 49199 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17819 /* 49202 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17820 /* 49205 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17821 /* 49209 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17822 /* 49213 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17823 /* 49217 */ // (intrinsic_wo_chain:{ *:[i32] } 4098:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17824 /* 49217 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB16),
17825 /* 49220 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17826 /* 49222 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17827 /* 49224 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17828 /* 49226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17829 /* 49229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17830 /* 49235 */ GIR_RootConstrainSelectedInstOperands,
17831 /* 49236 */ // GIR_Coverage, 106,
17832 /* 49236 */ GIR_EraseRootFromParent_Done,
17833 /* 49237 */ // Label 1456: @49237
17834 /* 49237 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1457*/ GIMT_Encode4(49290), GIMT_Encode2(GIFBS_IsARM), // Rule ID 107 //
17835 /* 49244 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8),
17836 /* 49249 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17837 /* 49252 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17838 /* 49255 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17839 /* 49258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17840 /* 49262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17841 /* 49266 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17842 /* 49270 */ // (intrinsic_wo_chain:{ *:[i32] } 4099:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17843 /* 49270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB8),
17844 /* 49273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17845 /* 49275 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17846 /* 49277 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17847 /* 49279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17848 /* 49282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17849 /* 49288 */ GIR_RootConstrainSelectedInstOperands,
17850 /* 49289 */ // GIR_Coverage, 107,
17851 /* 49289 */ GIR_EraseRootFromParent_Done,
17852 /* 49290 */ // Label 1457: @49290
17853 /* 49290 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1458*/ GIMT_Encode4(49343), GIMT_Encode2(GIFBS_IsARM), // Rule ID 110 //
17854 /* 49297 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
17855 /* 49302 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17856 /* 49305 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17857 /* 49308 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17858 /* 49311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17859 /* 49315 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17860 /* 49319 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17861 /* 49323 */ // (intrinsic_wo_chain:{ *:[i32] } 4097:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17862 /* 49323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB),
17863 /* 49326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17864 /* 49328 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
17865 /* 49330 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
17866 /* 49332 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17867 /* 49335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17868 /* 49341 */ GIR_RootConstrainSelectedInstOperands,
17869 /* 49342 */ // GIR_Coverage, 110,
17870 /* 49342 */ GIR_EraseRootFromParent_Done,
17871 /* 49343 */ // Label 1458: @49343
17872 /* 49343 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1459*/ GIMT_Encode4(49396), GIMT_Encode2(GIFBS_IsARM), // Rule ID 111 //
17873 /* 49350 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17874 /* 49355 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17875 /* 49358 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17876 /* 49361 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17877 /* 49364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17878 /* 49368 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17879 /* 49372 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17880 /* 49376 */ // (intrinsic_wo_chain:{ *:[i32] } 4092:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17881 /* 49376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD),
17882 /* 49379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17883 /* 49381 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
17884 /* 49383 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
17885 /* 49385 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17886 /* 49388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17887 /* 49394 */ GIR_RootConstrainSelectedInstOperands,
17888 /* 49395 */ // GIR_Coverage, 111,
17889 /* 49395 */ GIR_EraseRootFromParent_Done,
17890 /* 49396 */ // Label 1459: @49396
17891 /* 49396 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1460*/ GIMT_Encode4(49449), GIMT_Encode2(GIFBS_IsARM), // Rule ID 112 //
17892 /* 49403 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16),
17893 /* 49408 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17894 /* 49411 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17895 /* 49414 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17896 /* 49417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17897 /* 49421 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17898 /* 49425 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17899 /* 49429 */ // (intrinsic_wo_chain:{ *:[i32] } 4161:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17900 /* 49429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD16),
17901 /* 49432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17902 /* 49434 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17903 /* 49436 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17904 /* 49438 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17905 /* 49441 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17906 /* 49447 */ GIR_RootConstrainSelectedInstOperands,
17907 /* 49448 */ // GIR_Coverage, 112,
17908 /* 49448 */ GIR_EraseRootFromParent_Done,
17909 /* 49449 */ // Label 1460: @49449
17910 /* 49449 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1461*/ GIMT_Encode4(49502), GIMT_Encode2(GIFBS_IsARM), // Rule ID 113 //
17911 /* 49456 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8),
17912 /* 49461 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17913 /* 49464 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17914 /* 49467 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17915 /* 49470 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17916 /* 49474 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17917 /* 49478 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17918 /* 49482 */ // (intrinsic_wo_chain:{ *:[i32] } 4162:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17919 /* 49482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD8),
17920 /* 49485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17921 /* 49487 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17922 /* 49489 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17923 /* 49491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17924 /* 49494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17925 /* 49500 */ GIR_RootConstrainSelectedInstOperands,
17926 /* 49501 */ // GIR_Coverage, 113,
17927 /* 49501 */ GIR_EraseRootFromParent_Done,
17928 /* 49502 */ // Label 1461: @49502
17929 /* 49502 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1462*/ GIMT_Encode4(49555), GIMT_Encode2(GIFBS_IsARM), // Rule ID 114 //
17930 /* 49509 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16),
17931 /* 49514 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17932 /* 49517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17933 /* 49520 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17934 /* 49523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17935 /* 49527 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17936 /* 49531 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17937 /* 49535 */ // (intrinsic_wo_chain:{ *:[i32] } 4165:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17938 /* 49535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB16),
17939 /* 49538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17940 /* 49540 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17941 /* 49542 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17942 /* 49544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17943 /* 49547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17944 /* 49553 */ GIR_RootConstrainSelectedInstOperands,
17945 /* 49554 */ // GIR_Coverage, 114,
17946 /* 49554 */ GIR_EraseRootFromParent_Done,
17947 /* 49555 */ // Label 1462: @49555
17948 /* 49555 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1463*/ GIMT_Encode4(49608), GIMT_Encode2(GIFBS_IsARM), // Rule ID 115 //
17949 /* 49562 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8),
17950 /* 49567 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17951 /* 49570 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17952 /* 49573 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17953 /* 49576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17954 /* 49580 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17955 /* 49584 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17956 /* 49588 */ // (intrinsic_wo_chain:{ *:[i32] } 4166:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17957 /* 49588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB8),
17958 /* 49591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17959 /* 49593 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17960 /* 49595 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17961 /* 49597 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17962 /* 49600 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17963 /* 49606 */ GIR_RootConstrainSelectedInstOperands,
17964 /* 49607 */ // GIR_Coverage, 115,
17965 /* 49607 */ GIR_EraseRootFromParent_Done,
17966 /* 49608 */ // Label 1463: @49608
17967 /* 49608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1464*/ GIMT_Encode4(49661), GIMT_Encode2(GIFBS_IsARM), // Rule ID 116 //
17968 /* 49615 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx),
17969 /* 49620 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17970 /* 49623 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17971 /* 49626 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17972 /* 49629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17973 /* 49633 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17974 /* 49637 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17975 /* 49641 */ // (intrinsic_wo_chain:{ *:[i32] } 4095:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17976 /* 49641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QASX),
17977 /* 49644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17978 /* 49646 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17979 /* 49648 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17980 /* 49650 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17981 /* 49653 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17982 /* 49659 */ GIR_RootConstrainSelectedInstOperands,
17983 /* 49660 */ // GIR_Coverage, 116,
17984 /* 49660 */ GIR_EraseRootFromParent_Done,
17985 /* 49661 */ // Label 1464: @49661
17986 /* 49661 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1465*/ GIMT_Encode4(49714), GIMT_Encode2(GIFBS_IsARM), // Rule ID 117 //
17987 /* 49668 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax),
17988 /* 49673 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17989 /* 49676 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17990 /* 49679 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17991 /* 49682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17992 /* 49686 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17993 /* 49690 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17994 /* 49694 */ // (intrinsic_wo_chain:{ *:[i32] } 4096:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
17995 /* 49694 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSAX),
17996 /* 49697 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17997 /* 49699 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17998 /* 49701 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17999 /* 49703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18000 /* 49706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18001 /* 49712 */ GIR_RootConstrainSelectedInstOperands,
18002 /* 49713 */ // GIR_Coverage, 117,
18003 /* 49713 */ GIR_EraseRootFromParent_Done,
18004 /* 49714 */ // Label 1465: @49714
18005 /* 49714 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1466*/ GIMT_Encode4(49767), GIMT_Encode2(GIFBS_IsARM), // Rule ID 118 //
18006 /* 49721 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx),
18007 /* 49726 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18008 /* 49729 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18009 /* 49732 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18010 /* 49735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18011 /* 49739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18012 /* 49743 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18013 /* 49747 */ // (intrinsic_wo_chain:{ *:[i32] } 4163:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18014 /* 49747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQASX),
18015 /* 49750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18016 /* 49752 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18017 /* 49754 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18018 /* 49756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18019 /* 49759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18020 /* 49765 */ GIR_RootConstrainSelectedInstOperands,
18021 /* 49766 */ // GIR_Coverage, 118,
18022 /* 49766 */ GIR_EraseRootFromParent_Done,
18023 /* 49767 */ // Label 1466: @49767
18024 /* 49767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1467*/ GIMT_Encode4(49820), GIMT_Encode2(GIFBS_IsARM), // Rule ID 119 //
18025 /* 49774 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax),
18026 /* 49779 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18027 /* 49782 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18028 /* 49785 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18029 /* 49788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18030 /* 49792 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18031 /* 49796 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18032 /* 49800 */ // (intrinsic_wo_chain:{ *:[i32] } 4164:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18033 /* 49800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSAX),
18034 /* 49803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18035 /* 49805 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18036 /* 49807 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18037 /* 49809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18038 /* 49812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18039 /* 49818 */ GIR_RootConstrainSelectedInstOperands,
18040 /* 49819 */ // GIR_Coverage, 119,
18041 /* 49819 */ GIR_EraseRootFromParent_Done,
18042 /* 49820 */ // Label 1467: @49820
18043 /* 49820 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1468*/ GIMT_Encode4(49873), GIMT_Encode2(GIFBS_IsARM), // Rule ID 132 //
18044 /* 49827 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx),
18045 /* 49832 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18046 /* 49835 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18047 /* 49838 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18048 /* 49841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18049 /* 49845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18050 /* 49849 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18051 /* 49853 */ // (intrinsic_wo_chain:{ *:[i32] } 4107:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18052 /* 49853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHASX),
18053 /* 49856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18054 /* 49858 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18055 /* 49860 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18056 /* 49862 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18057 /* 49865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18058 /* 49871 */ GIR_RootConstrainSelectedInstOperands,
18059 /* 49872 */ // GIR_Coverage, 132,
18060 /* 49872 */ GIR_EraseRootFromParent_Done,
18061 /* 49873 */ // Label 1468: @49873
18062 /* 49873 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1469*/ GIMT_Encode4(49926), GIMT_Encode2(GIFBS_IsARM), // Rule ID 133 //
18063 /* 49880 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16),
18064 /* 49885 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18065 /* 49888 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18066 /* 49891 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18067 /* 49894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18068 /* 49898 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18069 /* 49902 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18070 /* 49906 */ // (intrinsic_wo_chain:{ *:[i32] } 4105:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18071 /* 49906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD16),
18072 /* 49909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18073 /* 49911 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18074 /* 49913 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18075 /* 49915 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18076 /* 49918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18077 /* 49924 */ GIR_RootConstrainSelectedInstOperands,
18078 /* 49925 */ // GIR_Coverage, 133,
18079 /* 49925 */ GIR_EraseRootFromParent_Done,
18080 /* 49926 */ // Label 1469: @49926
18081 /* 49926 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1470*/ GIMT_Encode4(49979), GIMT_Encode2(GIFBS_IsARM), // Rule ID 134 //
18082 /* 49933 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8),
18083 /* 49938 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18084 /* 49941 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18085 /* 49944 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18086 /* 49947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18087 /* 49951 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18088 /* 49955 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18089 /* 49959 */ // (intrinsic_wo_chain:{ *:[i32] } 4106:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18090 /* 49959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD8),
18091 /* 49962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18092 /* 49964 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18093 /* 49966 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18094 /* 49968 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18095 /* 49971 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18096 /* 49977 */ GIR_RootConstrainSelectedInstOperands,
18097 /* 49978 */ // GIR_Coverage, 134,
18098 /* 49978 */ GIR_EraseRootFromParent_Done,
18099 /* 49979 */ // Label 1470: @49979
18100 /* 49979 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1471*/ GIMT_Encode4(50032), GIMT_Encode2(GIFBS_IsARM), // Rule ID 135 //
18101 /* 49986 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax),
18102 /* 49991 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18103 /* 49994 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18104 /* 49997 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18105 /* 50000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18106 /* 50004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18107 /* 50008 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18108 /* 50012 */ // (intrinsic_wo_chain:{ *:[i32] } 4108:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18109 /* 50012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSAX),
18110 /* 50015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18111 /* 50017 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18112 /* 50019 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18113 /* 50021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18114 /* 50024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18115 /* 50030 */ GIR_RootConstrainSelectedInstOperands,
18116 /* 50031 */ // GIR_Coverage, 135,
18117 /* 50031 */ GIR_EraseRootFromParent_Done,
18118 /* 50032 */ // Label 1471: @50032
18119 /* 50032 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1472*/ GIMT_Encode4(50085), GIMT_Encode2(GIFBS_IsARM), // Rule ID 136 //
18120 /* 50039 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16),
18121 /* 50044 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18122 /* 50047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18123 /* 50050 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18124 /* 50053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18125 /* 50057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18126 /* 50061 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18127 /* 50065 */ // (intrinsic_wo_chain:{ *:[i32] } 4109:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18128 /* 50065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB16),
18129 /* 50068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18130 /* 50070 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18131 /* 50072 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18132 /* 50074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18133 /* 50077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18134 /* 50083 */ GIR_RootConstrainSelectedInstOperands,
18135 /* 50084 */ // GIR_Coverage, 136,
18136 /* 50084 */ GIR_EraseRootFromParent_Done,
18137 /* 50085 */ // Label 1472: @50085
18138 /* 50085 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1473*/ GIMT_Encode4(50138), GIMT_Encode2(GIFBS_IsARM), // Rule ID 137 //
18139 /* 50092 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8),
18140 /* 50097 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18141 /* 50100 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18142 /* 50103 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18143 /* 50106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18144 /* 50110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18145 /* 50114 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18146 /* 50118 */ // (intrinsic_wo_chain:{ *:[i32] } 4110:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18147 /* 50118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB8),
18148 /* 50121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18149 /* 50123 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18150 /* 50125 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18151 /* 50127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18152 /* 50130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18153 /* 50136 */ GIR_RootConstrainSelectedInstOperands,
18154 /* 50137 */ // GIR_Coverage, 137,
18155 /* 50137 */ GIR_EraseRootFromParent_Done,
18156 /* 50138 */ // Label 1473: @50138
18157 /* 50138 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1474*/ GIMT_Encode4(50191), GIMT_Encode2(GIFBS_IsARM), // Rule ID 138 //
18158 /* 50145 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx),
18159 /* 50150 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18160 /* 50153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18161 /* 50156 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18162 /* 50159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18163 /* 50163 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18164 /* 50167 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18165 /* 50171 */ // (intrinsic_wo_chain:{ *:[i32] } 4156:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18166 /* 50171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHASX),
18167 /* 50174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18168 /* 50176 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18169 /* 50178 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18170 /* 50180 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18171 /* 50183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18172 /* 50189 */ GIR_RootConstrainSelectedInstOperands,
18173 /* 50190 */ // GIR_Coverage, 138,
18174 /* 50190 */ GIR_EraseRootFromParent_Done,
18175 /* 50191 */ // Label 1474: @50191
18176 /* 50191 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1475*/ GIMT_Encode4(50244), GIMT_Encode2(GIFBS_IsARM), // Rule ID 139 //
18177 /* 50198 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16),
18178 /* 50203 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18179 /* 50206 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18180 /* 50209 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18181 /* 50212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18182 /* 50216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18183 /* 50220 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18184 /* 50224 */ // (intrinsic_wo_chain:{ *:[i32] } 4154:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18185 /* 50224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD16),
18186 /* 50227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18187 /* 50229 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18188 /* 50231 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18189 /* 50233 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18190 /* 50236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18191 /* 50242 */ GIR_RootConstrainSelectedInstOperands,
18192 /* 50243 */ // GIR_Coverage, 139,
18193 /* 50243 */ GIR_EraseRootFromParent_Done,
18194 /* 50244 */ // Label 1475: @50244
18195 /* 50244 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1476*/ GIMT_Encode4(50297), GIMT_Encode2(GIFBS_IsARM), // Rule ID 140 //
18196 /* 50251 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8),
18197 /* 50256 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18198 /* 50259 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18199 /* 50262 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18200 /* 50265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18201 /* 50269 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18202 /* 50273 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18203 /* 50277 */ // (intrinsic_wo_chain:{ *:[i32] } 4155:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18204 /* 50277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD8),
18205 /* 50280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18206 /* 50282 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18207 /* 50284 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18208 /* 50286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18209 /* 50289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18210 /* 50295 */ GIR_RootConstrainSelectedInstOperands,
18211 /* 50296 */ // GIR_Coverage, 140,
18212 /* 50296 */ GIR_EraseRootFromParent_Done,
18213 /* 50297 */ // Label 1476: @50297
18214 /* 50297 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1477*/ GIMT_Encode4(50350), GIMT_Encode2(GIFBS_IsARM), // Rule ID 141 //
18215 /* 50304 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax),
18216 /* 50309 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18217 /* 50312 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18218 /* 50315 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18219 /* 50318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18220 /* 50322 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18221 /* 50326 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18222 /* 50330 */ // (intrinsic_wo_chain:{ *:[i32] } 4157:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18223 /* 50330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSAX),
18224 /* 50333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18225 /* 50335 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18226 /* 50337 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18227 /* 50339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18228 /* 50342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18229 /* 50348 */ GIR_RootConstrainSelectedInstOperands,
18230 /* 50349 */ // GIR_Coverage, 141,
18231 /* 50349 */ GIR_EraseRootFromParent_Done,
18232 /* 50350 */ // Label 1477: @50350
18233 /* 50350 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1478*/ GIMT_Encode4(50403), GIMT_Encode2(GIFBS_IsARM), // Rule ID 142 //
18234 /* 50357 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16),
18235 /* 50362 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18236 /* 50365 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18237 /* 50368 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18238 /* 50371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18239 /* 50375 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18240 /* 50379 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18241 /* 50383 */ // (intrinsic_wo_chain:{ *:[i32] } 4158:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18242 /* 50383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB16),
18243 /* 50386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18244 /* 50388 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18245 /* 50390 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18246 /* 50392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18247 /* 50395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18248 /* 50401 */ GIR_RootConstrainSelectedInstOperands,
18249 /* 50402 */ // GIR_Coverage, 142,
18250 /* 50402 */ GIR_EraseRootFromParent_Done,
18251 /* 50403 */ // Label 1478: @50403
18252 /* 50403 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1479*/ GIMT_Encode4(50456), GIMT_Encode2(GIFBS_IsARM), // Rule ID 143 //
18253 /* 50410 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8),
18254 /* 50415 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18255 /* 50418 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18256 /* 50421 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18257 /* 50424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18258 /* 50428 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18259 /* 50432 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18260 /* 50436 */ // (intrinsic_wo_chain:{ *:[i32] } 4159:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18261 /* 50436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB8),
18262 /* 50439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18263 /* 50441 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18264 /* 50443 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18265 /* 50445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18266 /* 50448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18267 /* 50454 */ GIR_RootConstrainSelectedInstOperands,
18268 /* 50455 */ // GIR_Coverage, 143,
18269 /* 50455 */ GIR_EraseRootFromParent_Done,
18270 /* 50456 */ // Label 1479: @50456
18271 /* 50456 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1480*/ GIMT_Encode4(50509), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 144 //
18272 /* 50463 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8),
18273 /* 50468 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18274 /* 50471 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18275 /* 50474 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18276 /* 50477 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
18277 /* 50481 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
18278 /* 50485 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
18279 /* 50489 */ // (intrinsic_wo_chain:{ *:[i32] } 4167:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (USAD8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
18280 /* 50489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAD8),
18281 /* 50492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18282 /* 50494 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18283 /* 50496 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18284 /* 50498 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18285 /* 50501 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18286 /* 50507 */ GIR_RootConstrainSelectedInstOperands,
18287 /* 50508 */ // GIR_Coverage, 144,
18288 /* 50508 */ GIR_EraseRootFromParent_Done,
18289 /* 50509 */ // Label 1480: @50509
18290 /* 50509 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1481*/ GIMT_Encode4(50553), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 203 //
18291 /* 50516 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b),
18292 /* 50521 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18293 /* 50524 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18294 /* 50527 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18295 /* 50530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18296 /* 50534 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18297 /* 50538 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18298 /* 50542 */ // (intrinsic_wo_chain:{ *:[i32] } 3713:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32B:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18299 /* 50542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32B),
18300 /* 50545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18301 /* 50547 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18302 /* 50549 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18303 /* 50551 */ GIR_RootConstrainSelectedInstOperands,
18304 /* 50552 */ // GIR_Coverage, 203,
18305 /* 50552 */ GIR_EraseRootFromParent_Done,
18306 /* 50553 */ // Label 1481: @50553
18307 /* 50553 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1482*/ GIMT_Encode4(50597), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 204 //
18308 /* 50560 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb),
18309 /* 50565 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18310 /* 50568 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18311 /* 50571 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18312 /* 50574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18313 /* 50578 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18314 /* 50582 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18315 /* 50586 */ // (intrinsic_wo_chain:{ *:[i32] } 3714:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18316 /* 50586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CB),
18317 /* 50589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18318 /* 50591 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18319 /* 50593 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18320 /* 50595 */ GIR_RootConstrainSelectedInstOperands,
18321 /* 50596 */ // GIR_Coverage, 204,
18322 /* 50596 */ GIR_EraseRootFromParent_Done,
18323 /* 50597 */ // Label 1482: @50597
18324 /* 50597 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1483*/ GIMT_Encode4(50641), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 205 //
18325 /* 50604 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h),
18326 /* 50609 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18327 /* 50612 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18328 /* 50615 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18329 /* 50618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18330 /* 50622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18331 /* 50626 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18332 /* 50630 */ // (intrinsic_wo_chain:{ *:[i32] } 3717:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32H:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18333 /* 50630 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32H),
18334 /* 50633 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18335 /* 50635 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18336 /* 50637 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18337 /* 50639 */ GIR_RootConstrainSelectedInstOperands,
18338 /* 50640 */ // GIR_Coverage, 205,
18339 /* 50640 */ GIR_EraseRootFromParent_Done,
18340 /* 50641 */ // Label 1483: @50641
18341 /* 50641 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1484*/ GIMT_Encode4(50685), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 206 //
18342 /* 50648 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch),
18343 /* 50653 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18344 /* 50656 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18345 /* 50659 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18346 /* 50662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18347 /* 50666 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18348 /* 50670 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18349 /* 50674 */ // (intrinsic_wo_chain:{ *:[i32] } 3715:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CH:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18350 /* 50674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CH),
18351 /* 50677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18352 /* 50679 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18353 /* 50681 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18354 /* 50683 */ GIR_RootConstrainSelectedInstOperands,
18355 /* 50684 */ // GIR_Coverage, 206,
18356 /* 50684 */ GIR_EraseRootFromParent_Done,
18357 /* 50685 */ // Label 1484: @50685
18358 /* 50685 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1485*/ GIMT_Encode4(50729), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 207 //
18359 /* 50692 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w),
18360 /* 50697 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18361 /* 50700 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18362 /* 50703 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18363 /* 50706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18364 /* 50710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18365 /* 50714 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18366 /* 50718 */ // (intrinsic_wo_chain:{ *:[i32] } 3718:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32W:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18367 /* 50718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32W),
18368 /* 50721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18369 /* 50723 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18370 /* 50725 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18371 /* 50727 */ GIR_RootConstrainSelectedInstOperands,
18372 /* 50728 */ // GIR_Coverage, 207,
18373 /* 50728 */ GIR_EraseRootFromParent_Done,
18374 /* 50729 */ // Label 1485: @50729
18375 /* 50729 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1486*/ GIMT_Encode4(50773), GIMT_Encode2(GIFBS_HasCRC_IsARM), // Rule ID 208 //
18376 /* 50736 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw),
18377 /* 50741 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18378 /* 50744 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18379 /* 50747 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18380 /* 50750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18381 /* 50754 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18382 /* 50758 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18383 /* 50762 */ // (intrinsic_wo_chain:{ *:[i32] } 3716:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CW:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18384 /* 50762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CW),
18385 /* 50765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18386 /* 50767 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18387 /* 50769 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18388 /* 50771 */ GIR_RootConstrainSelectedInstOperands,
18389 /* 50772 */ // GIR_Coverage, 208,
18390 /* 50772 */ GIR_EraseRootFromParent_Done,
18391 /* 50773 */ // Label 1486: @50773
18392 /* 50773 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1487*/ GIMT_Encode4(50826), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 431 //
18393 /* 50780 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16),
18394 /* 50785 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18395 /* 50788 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18396 /* 50791 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18397 /* 50794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18398 /* 50798 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18399 /* 50802 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18400 /* 50806 */ // (intrinsic_wo_chain:{ *:[i32] } 4093:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18401 /* 50806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD16),
18402 /* 50809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18403 /* 50811 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18404 /* 50813 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18405 /* 50815 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18406 /* 50818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18407 /* 50824 */ GIR_RootConstrainSelectedInstOperands,
18408 /* 50825 */ // GIR_Coverage, 431,
18409 /* 50825 */ GIR_EraseRootFromParent_Done,
18410 /* 50826 */ // Label 1487: @50826
18411 /* 50826 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1488*/ GIMT_Encode4(50879), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 432 //
18412 /* 50833 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8),
18413 /* 50838 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18414 /* 50841 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18415 /* 50844 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18416 /* 50847 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18417 /* 50851 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18418 /* 50855 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18419 /* 50859 */ // (intrinsic_wo_chain:{ *:[i32] } 4094:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18420 /* 50859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD8),
18421 /* 50862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18422 /* 50864 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18423 /* 50866 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18424 /* 50868 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18425 /* 50871 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18426 /* 50877 */ GIR_RootConstrainSelectedInstOperands,
18427 /* 50878 */ // GIR_Coverage, 432,
18428 /* 50878 */ GIR_EraseRootFromParent_Done,
18429 /* 50879 */ // Label 1488: @50879
18430 /* 50879 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1489*/ GIMT_Encode4(50932), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 433 //
18431 /* 50886 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx),
18432 /* 50891 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18433 /* 50894 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18434 /* 50897 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18435 /* 50900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18436 /* 50904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18437 /* 50908 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18438 /* 50912 */ // (intrinsic_wo_chain:{ *:[i32] } 4095:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18439 /* 50912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QASX),
18440 /* 50915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18441 /* 50917 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18442 /* 50919 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18443 /* 50921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18444 /* 50924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18445 /* 50930 */ GIR_RootConstrainSelectedInstOperands,
18446 /* 50931 */ // GIR_Coverage, 433,
18447 /* 50931 */ GIR_EraseRootFromParent_Done,
18448 /* 50932 */ // Label 1489: @50932
18449 /* 50932 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1490*/ GIMT_Encode4(50985), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 434 //
18450 /* 50939 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8),
18451 /* 50944 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18452 /* 50947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18453 /* 50950 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18454 /* 50953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18455 /* 50957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18456 /* 50961 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18457 /* 50965 */ // (intrinsic_wo_chain:{ *:[i32] } 4166:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18458 /* 50965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB8),
18459 /* 50968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18460 /* 50970 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18461 /* 50972 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18462 /* 50974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18463 /* 50977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18464 /* 50983 */ GIR_RootConstrainSelectedInstOperands,
18465 /* 50984 */ // GIR_Coverage, 434,
18466 /* 50984 */ GIR_EraseRootFromParent_Done,
18467 /* 50985 */ // Label 1490: @50985
18468 /* 50985 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1491*/ GIMT_Encode4(51038), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 435 //
18469 /* 50992 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax),
18470 /* 50997 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18471 /* 51000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18472 /* 51003 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18473 /* 51006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18474 /* 51010 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18475 /* 51014 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18476 /* 51018 */ // (intrinsic_wo_chain:{ *:[i32] } 4096:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18477 /* 51018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSAX),
18478 /* 51021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18479 /* 51023 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18480 /* 51025 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18481 /* 51027 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18482 /* 51030 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18483 /* 51036 */ GIR_RootConstrainSelectedInstOperands,
18484 /* 51037 */ // GIR_Coverage, 435,
18485 /* 51037 */ GIR_EraseRootFromParent_Done,
18486 /* 51038 */ // Label 1491: @51038
18487 /* 51038 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1492*/ GIMT_Encode4(51091), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 436 //
18488 /* 51045 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16),
18489 /* 51050 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18490 /* 51053 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18491 /* 51056 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18492 /* 51059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18493 /* 51063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18494 /* 51067 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18495 /* 51071 */ // (intrinsic_wo_chain:{ *:[i32] } 4098:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18496 /* 51071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB16),
18497 /* 51074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18498 /* 51076 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18499 /* 51078 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18500 /* 51080 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18501 /* 51083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18502 /* 51089 */ GIR_RootConstrainSelectedInstOperands,
18503 /* 51090 */ // GIR_Coverage, 436,
18504 /* 51090 */ GIR_EraseRootFromParent_Done,
18505 /* 51091 */ // Label 1492: @51091
18506 /* 51091 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1493*/ GIMT_Encode4(51144), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 437 //
18507 /* 51098 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8),
18508 /* 51103 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18509 /* 51106 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18510 /* 51109 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18511 /* 51112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18512 /* 51116 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18513 /* 51120 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18514 /* 51124 */ // (intrinsic_wo_chain:{ *:[i32] } 4099:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18515 /* 51124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB8),
18516 /* 51127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18517 /* 51129 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18518 /* 51131 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18519 /* 51133 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18520 /* 51136 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18521 /* 51142 */ GIR_RootConstrainSelectedInstOperands,
18522 /* 51143 */ // GIR_Coverage, 437,
18523 /* 51143 */ GIR_EraseRootFromParent_Done,
18524 /* 51144 */ // Label 1493: @51144
18525 /* 51144 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1494*/ GIMT_Encode4(51197), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 438 //
18526 /* 51151 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16),
18527 /* 51156 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18528 /* 51159 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18529 /* 51162 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18530 /* 51165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18531 /* 51169 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18532 /* 51173 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18533 /* 51177 */ // (intrinsic_wo_chain:{ *:[i32] } 4161:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18534 /* 51177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD16),
18535 /* 51180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18536 /* 51182 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18537 /* 51184 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18538 /* 51186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18539 /* 51189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18540 /* 51195 */ GIR_RootConstrainSelectedInstOperands,
18541 /* 51196 */ // GIR_Coverage, 438,
18542 /* 51196 */ GIR_EraseRootFromParent_Done,
18543 /* 51197 */ // Label 1494: @51197
18544 /* 51197 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1495*/ GIMT_Encode4(51250), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 439 //
18545 /* 51204 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8),
18546 /* 51209 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18547 /* 51212 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18548 /* 51215 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18549 /* 51218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18550 /* 51222 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18551 /* 51226 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18552 /* 51230 */ // (intrinsic_wo_chain:{ *:[i32] } 4162:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18553 /* 51230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD8),
18554 /* 51233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18555 /* 51235 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18556 /* 51237 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18557 /* 51239 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18558 /* 51242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18559 /* 51248 */ GIR_RootConstrainSelectedInstOperands,
18560 /* 51249 */ // GIR_Coverage, 439,
18561 /* 51249 */ GIR_EraseRootFromParent_Done,
18562 /* 51250 */ // Label 1495: @51250
18563 /* 51250 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1496*/ GIMT_Encode4(51303), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 440 //
18564 /* 51257 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx),
18565 /* 51262 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18566 /* 51265 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18567 /* 51268 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18568 /* 51271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18569 /* 51275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18570 /* 51279 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18571 /* 51283 */ // (intrinsic_wo_chain:{ *:[i32] } 4163:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18572 /* 51283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQASX),
18573 /* 51286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18574 /* 51288 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18575 /* 51290 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18576 /* 51292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18577 /* 51295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18578 /* 51301 */ GIR_RootConstrainSelectedInstOperands,
18579 /* 51302 */ // GIR_Coverage, 440,
18580 /* 51302 */ GIR_EraseRootFromParent_Done,
18581 /* 51303 */ // Label 1496: @51303
18582 /* 51303 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1497*/ GIMT_Encode4(51356), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 441 //
18583 /* 51310 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax),
18584 /* 51315 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18585 /* 51318 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18586 /* 51321 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18587 /* 51324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18588 /* 51328 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18589 /* 51332 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18590 /* 51336 */ // (intrinsic_wo_chain:{ *:[i32] } 4164:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18591 /* 51336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSAX),
18592 /* 51339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18593 /* 51341 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18594 /* 51343 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18595 /* 51345 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18596 /* 51348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18597 /* 51354 */ GIR_RootConstrainSelectedInstOperands,
18598 /* 51355 */ // GIR_Coverage, 441,
18599 /* 51355 */ GIR_EraseRootFromParent_Done,
18600 /* 51356 */ // Label 1497: @51356
18601 /* 51356 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1498*/ GIMT_Encode4(51409), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 442 //
18602 /* 51363 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16),
18603 /* 51368 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18604 /* 51371 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18605 /* 51374 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18606 /* 51377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18607 /* 51381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18608 /* 51385 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18609 /* 51389 */ // (intrinsic_wo_chain:{ *:[i32] } 4165:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18610 /* 51389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB16),
18611 /* 51392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18612 /* 51394 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18613 /* 51396 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18614 /* 51398 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18615 /* 51401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18616 /* 51407 */ GIR_RootConstrainSelectedInstOperands,
18617 /* 51408 */ // GIR_Coverage, 442,
18618 /* 51408 */ GIR_EraseRootFromParent_Done,
18619 /* 51409 */ // Label 1498: @51409
18620 /* 51409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1499*/ GIMT_Encode4(51462), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 455 //
18621 /* 51416 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx),
18622 /* 51421 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18623 /* 51424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18624 /* 51427 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18625 /* 51430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18626 /* 51434 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18627 /* 51438 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18628 /* 51442 */ // (intrinsic_wo_chain:{ *:[i32] } 4107:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18629 /* 51442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHASX),
18630 /* 51445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18631 /* 51447 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18632 /* 51449 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18633 /* 51451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18634 /* 51454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18635 /* 51460 */ GIR_RootConstrainSelectedInstOperands,
18636 /* 51461 */ // GIR_Coverage, 455,
18637 /* 51461 */ GIR_EraseRootFromParent_Done,
18638 /* 51462 */ // Label 1499: @51462
18639 /* 51462 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1500*/ GIMT_Encode4(51515), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 456 //
18640 /* 51469 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16),
18641 /* 51474 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18642 /* 51477 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18643 /* 51480 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18644 /* 51483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18645 /* 51487 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18646 /* 51491 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18647 /* 51495 */ // (intrinsic_wo_chain:{ *:[i32] } 4105:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18648 /* 51495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD16),
18649 /* 51498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18650 /* 51500 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18651 /* 51502 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18652 /* 51504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18653 /* 51507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18654 /* 51513 */ GIR_RootConstrainSelectedInstOperands,
18655 /* 51514 */ // GIR_Coverage, 456,
18656 /* 51514 */ GIR_EraseRootFromParent_Done,
18657 /* 51515 */ // Label 1500: @51515
18658 /* 51515 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1501*/ GIMT_Encode4(51568), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 457 //
18659 /* 51522 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8),
18660 /* 51527 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18661 /* 51530 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18662 /* 51533 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18663 /* 51536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18664 /* 51540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18665 /* 51544 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18666 /* 51548 */ // (intrinsic_wo_chain:{ *:[i32] } 4106:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18667 /* 51548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD8),
18668 /* 51551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18669 /* 51553 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18670 /* 51555 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18671 /* 51557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18672 /* 51560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18673 /* 51566 */ GIR_RootConstrainSelectedInstOperands,
18674 /* 51567 */ // GIR_Coverage, 457,
18675 /* 51567 */ GIR_EraseRootFromParent_Done,
18676 /* 51568 */ // Label 1501: @51568
18677 /* 51568 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1502*/ GIMT_Encode4(51621), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 458 //
18678 /* 51575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax),
18679 /* 51580 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18680 /* 51583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18681 /* 51586 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18682 /* 51589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18683 /* 51593 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18684 /* 51597 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18685 /* 51601 */ // (intrinsic_wo_chain:{ *:[i32] } 4108:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18686 /* 51601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSAX),
18687 /* 51604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18688 /* 51606 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18689 /* 51608 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18690 /* 51610 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18691 /* 51613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18692 /* 51619 */ GIR_RootConstrainSelectedInstOperands,
18693 /* 51620 */ // GIR_Coverage, 458,
18694 /* 51620 */ GIR_EraseRootFromParent_Done,
18695 /* 51621 */ // Label 1502: @51621
18696 /* 51621 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1503*/ GIMT_Encode4(51674), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 459 //
18697 /* 51628 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16),
18698 /* 51633 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18699 /* 51636 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18700 /* 51639 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18701 /* 51642 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18702 /* 51646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18703 /* 51650 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18704 /* 51654 */ // (intrinsic_wo_chain:{ *:[i32] } 4109:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18705 /* 51654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB16),
18706 /* 51657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18707 /* 51659 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18708 /* 51661 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18709 /* 51663 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18710 /* 51666 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18711 /* 51672 */ GIR_RootConstrainSelectedInstOperands,
18712 /* 51673 */ // GIR_Coverage, 459,
18713 /* 51673 */ GIR_EraseRootFromParent_Done,
18714 /* 51674 */ // Label 1503: @51674
18715 /* 51674 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1504*/ GIMT_Encode4(51727), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 460 //
18716 /* 51681 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8),
18717 /* 51686 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18718 /* 51689 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18719 /* 51692 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18720 /* 51695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18721 /* 51699 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18722 /* 51703 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18723 /* 51707 */ // (intrinsic_wo_chain:{ *:[i32] } 4110:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18724 /* 51707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB8),
18725 /* 51710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18726 /* 51712 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18727 /* 51714 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18728 /* 51716 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18729 /* 51719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18730 /* 51725 */ GIR_RootConstrainSelectedInstOperands,
18731 /* 51726 */ // GIR_Coverage, 460,
18732 /* 51726 */ GIR_EraseRootFromParent_Done,
18733 /* 51727 */ // Label 1504: @51727
18734 /* 51727 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1505*/ GIMT_Encode4(51780), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 461 //
18735 /* 51734 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx),
18736 /* 51739 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18737 /* 51742 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18738 /* 51745 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18739 /* 51748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18740 /* 51752 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18741 /* 51756 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18742 /* 51760 */ // (intrinsic_wo_chain:{ *:[i32] } 4156:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18743 /* 51760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHASX),
18744 /* 51763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18745 /* 51765 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18746 /* 51767 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18747 /* 51769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18748 /* 51772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18749 /* 51778 */ GIR_RootConstrainSelectedInstOperands,
18750 /* 51779 */ // GIR_Coverage, 461,
18751 /* 51779 */ GIR_EraseRootFromParent_Done,
18752 /* 51780 */ // Label 1505: @51780
18753 /* 51780 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1506*/ GIMT_Encode4(51833), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 462 //
18754 /* 51787 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16),
18755 /* 51792 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18756 /* 51795 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18757 /* 51798 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18758 /* 51801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18759 /* 51805 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18760 /* 51809 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18761 /* 51813 */ // (intrinsic_wo_chain:{ *:[i32] } 4154:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18762 /* 51813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD16),
18763 /* 51816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18764 /* 51818 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18765 /* 51820 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18766 /* 51822 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18767 /* 51825 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18768 /* 51831 */ GIR_RootConstrainSelectedInstOperands,
18769 /* 51832 */ // GIR_Coverage, 462,
18770 /* 51832 */ GIR_EraseRootFromParent_Done,
18771 /* 51833 */ // Label 1506: @51833
18772 /* 51833 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1507*/ GIMT_Encode4(51886), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 463 //
18773 /* 51840 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8),
18774 /* 51845 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18775 /* 51848 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18776 /* 51851 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18777 /* 51854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18778 /* 51858 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18779 /* 51862 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18780 /* 51866 */ // (intrinsic_wo_chain:{ *:[i32] } 4155:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18781 /* 51866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD8),
18782 /* 51869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18783 /* 51871 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18784 /* 51873 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18785 /* 51875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18786 /* 51878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18787 /* 51884 */ GIR_RootConstrainSelectedInstOperands,
18788 /* 51885 */ // GIR_Coverage, 463,
18789 /* 51885 */ GIR_EraseRootFromParent_Done,
18790 /* 51886 */ // Label 1507: @51886
18791 /* 51886 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1508*/ GIMT_Encode4(51939), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 464 //
18792 /* 51893 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax),
18793 /* 51898 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18794 /* 51901 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18795 /* 51904 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18796 /* 51907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18797 /* 51911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18798 /* 51915 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18799 /* 51919 */ // (intrinsic_wo_chain:{ *:[i32] } 4157:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18800 /* 51919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSAX),
18801 /* 51922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18802 /* 51924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18803 /* 51926 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18804 /* 51928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18805 /* 51931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18806 /* 51937 */ GIR_RootConstrainSelectedInstOperands,
18807 /* 51938 */ // GIR_Coverage, 464,
18808 /* 51938 */ GIR_EraseRootFromParent_Done,
18809 /* 51939 */ // Label 1508: @51939
18810 /* 51939 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1509*/ GIMT_Encode4(51992), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 465 //
18811 /* 51946 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16),
18812 /* 51951 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18813 /* 51954 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18814 /* 51957 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18815 /* 51960 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18816 /* 51964 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18817 /* 51968 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18818 /* 51972 */ // (intrinsic_wo_chain:{ *:[i32] } 4158:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18819 /* 51972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB16),
18820 /* 51975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18821 /* 51977 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18822 /* 51979 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18823 /* 51981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18824 /* 51984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18825 /* 51990 */ GIR_RootConstrainSelectedInstOperands,
18826 /* 51991 */ // GIR_Coverage, 465,
18827 /* 51991 */ GIR_EraseRootFromParent_Done,
18828 /* 51992 */ // Label 1509: @51992
18829 /* 51992 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1510*/ GIMT_Encode4(52045), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 466 //
18830 /* 51999 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8),
18831 /* 52004 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18832 /* 52007 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18833 /* 52010 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18834 /* 52013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18835 /* 52017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18836 /* 52021 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18837 /* 52025 */ // (intrinsic_wo_chain:{ *:[i32] } 4159:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18838 /* 52025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB8),
18839 /* 52028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18840 /* 52030 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18841 /* 52032 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18842 /* 52034 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18843 /* 52037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18844 /* 52043 */ GIR_RootConstrainSelectedInstOperands,
18845 /* 52044 */ // GIR_Coverage, 466,
18846 /* 52044 */ GIR_EraseRootFromParent_Done,
18847 /* 52045 */ // Label 1510: @52045
18848 /* 52045 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1511*/ GIMT_Encode4(52098), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 467 //
18849 /* 52052 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8),
18850 /* 52057 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18851 /* 52060 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18852 /* 52063 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18853 /* 52066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18854 /* 52070 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18855 /* 52074 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18856 /* 52078 */ // (intrinsic_wo_chain:{ *:[i32] } 4167:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18857 /* 52078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAD8),
18858 /* 52081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18859 /* 52083 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18860 /* 52085 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18861 /* 52087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18862 /* 52090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18863 /* 52096 */ GIR_RootConstrainSelectedInstOperands,
18864 /* 52097 */ // GIR_Coverage, 467,
18865 /* 52097 */ GIR_EraseRootFromParent_Done,
18866 /* 52098 */ // Label 1511: @52098
18867 /* 52098 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1512*/ GIMT_Encode4(52151), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 523 //
18868 /* 52105 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad),
18869 /* 52110 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18870 /* 52113 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18871 /* 52116 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18872 /* 52119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18873 /* 52123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18874 /* 52127 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18875 /* 52131 */ // (intrinsic_wo_chain:{ *:[i32] } 4125:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18876 /* 52131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUAD),
18877 /* 52134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18878 /* 52136 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18879 /* 52138 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18880 /* 52140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18881 /* 52143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18882 /* 52149 */ GIR_RootConstrainSelectedInstOperands,
18883 /* 52150 */ // GIR_Coverage, 523,
18884 /* 52150 */ GIR_EraseRootFromParent_Done,
18885 /* 52151 */ // Label 1512: @52151
18886 /* 52151 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1513*/ GIMT_Encode4(52204), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 524 //
18887 /* 52158 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx),
18888 /* 52163 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18889 /* 52166 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18890 /* 52169 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18891 /* 52172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18892 /* 52176 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18893 /* 52180 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18894 /* 52184 */ // (intrinsic_wo_chain:{ *:[i32] } 4126:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18895 /* 52184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUADX),
18896 /* 52187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18897 /* 52189 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18898 /* 52191 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18899 /* 52193 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18900 /* 52196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18901 /* 52202 */ GIR_RootConstrainSelectedInstOperands,
18902 /* 52203 */ // GIR_Coverage, 524,
18903 /* 52203 */ GIR_EraseRootFromParent_Done,
18904 /* 52204 */ // Label 1513: @52204
18905 /* 52204 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1514*/ GIMT_Encode4(52257), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 525 //
18906 /* 52211 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd),
18907 /* 52216 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18908 /* 52219 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18909 /* 52222 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18910 /* 52225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18911 /* 52229 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18912 /* 52233 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18913 /* 52237 */ // (intrinsic_wo_chain:{ *:[i32] } 4133:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18914 /* 52237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSD),
18915 /* 52240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18916 /* 52242 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18917 /* 52244 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18918 /* 52246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18919 /* 52249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18920 /* 52255 */ GIR_RootConstrainSelectedInstOperands,
18921 /* 52256 */ // GIR_Coverage, 525,
18922 /* 52256 */ GIR_EraseRootFromParent_Done,
18923 /* 52257 */ // Label 1514: @52257
18924 /* 52257 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1515*/ GIMT_Encode4(52310), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 526 //
18925 /* 52264 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx),
18926 /* 52269 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18927 /* 52272 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18928 /* 52275 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18929 /* 52278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18930 /* 52282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18931 /* 52286 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18932 /* 52290 */ // (intrinsic_wo_chain:{ *:[i32] } 4134:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18933 /* 52290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSDX),
18934 /* 52293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18935 /* 52295 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18936 /* 52297 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18937 /* 52299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18938 /* 52302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18939 /* 52308 */ GIR_RootConstrainSelectedInstOperands,
18940 /* 52309 */ // GIR_Coverage, 526,
18941 /* 52309 */ GIR_EraseRootFromParent_Done,
18942 /* 52310 */ // Label 1515: @52310
18943 /* 52310 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1516*/ GIMT_Encode4(52354), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 540 //
18944 /* 52317 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b),
18945 /* 52322 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18946 /* 52325 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18947 /* 52328 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18948 /* 52331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18949 /* 52335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18950 /* 52339 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18951 /* 52343 */ // (intrinsic_wo_chain:{ *:[i32] } 3713:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32B:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18952 /* 52343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32B),
18953 /* 52346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18954 /* 52348 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18955 /* 52350 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18956 /* 52352 */ GIR_RootConstrainSelectedInstOperands,
18957 /* 52353 */ // GIR_Coverage, 540,
18958 /* 52353 */ GIR_EraseRootFromParent_Done,
18959 /* 52354 */ // Label 1516: @52354
18960 /* 52354 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1517*/ GIMT_Encode4(52398), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 541 //
18961 /* 52361 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb),
18962 /* 52366 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18963 /* 52369 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18964 /* 52372 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18965 /* 52375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18966 /* 52379 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18967 /* 52383 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18968 /* 52387 */ // (intrinsic_wo_chain:{ *:[i32] } 3714:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18969 /* 52387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CB),
18970 /* 52390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18971 /* 52392 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18972 /* 52394 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18973 /* 52396 */ GIR_RootConstrainSelectedInstOperands,
18974 /* 52397 */ // GIR_Coverage, 541,
18975 /* 52397 */ GIR_EraseRootFromParent_Done,
18976 /* 52398 */ // Label 1517: @52398
18977 /* 52398 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1518*/ GIMT_Encode4(52442), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 542 //
18978 /* 52405 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h),
18979 /* 52410 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18980 /* 52413 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18981 /* 52416 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18982 /* 52419 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18983 /* 52423 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18984 /* 52427 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18985 /* 52431 */ // (intrinsic_wo_chain:{ *:[i32] } 3717:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32H:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
18986 /* 52431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32H),
18987 /* 52434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18988 /* 52436 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18989 /* 52438 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18990 /* 52440 */ GIR_RootConstrainSelectedInstOperands,
18991 /* 52441 */ // GIR_Coverage, 542,
18992 /* 52441 */ GIR_EraseRootFromParent_Done,
18993 /* 52442 */ // Label 1518: @52442
18994 /* 52442 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1519*/ GIMT_Encode4(52486), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 543 //
18995 /* 52449 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch),
18996 /* 52454 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18997 /* 52457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18998 /* 52460 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18999 /* 52463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19000 /* 52467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19001 /* 52471 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19002 /* 52475 */ // (intrinsic_wo_chain:{ *:[i32] } 3715:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19003 /* 52475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CH),
19004 /* 52478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19005 /* 52480 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19006 /* 52482 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19007 /* 52484 */ GIR_RootConstrainSelectedInstOperands,
19008 /* 52485 */ // GIR_Coverage, 543,
19009 /* 52485 */ GIR_EraseRootFromParent_Done,
19010 /* 52486 */ // Label 1519: @52486
19011 /* 52486 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1520*/ GIMT_Encode4(52530), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 544 //
19012 /* 52493 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w),
19013 /* 52498 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19014 /* 52501 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19015 /* 52504 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19016 /* 52507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19017 /* 52511 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19018 /* 52515 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19019 /* 52519 */ // (intrinsic_wo_chain:{ *:[i32] } 3718:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32W:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19020 /* 52519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32W),
19021 /* 52522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19022 /* 52524 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19023 /* 52526 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19024 /* 52528 */ GIR_RootConstrainSelectedInstOperands,
19025 /* 52529 */ // GIR_Coverage, 544,
19026 /* 52529 */ GIR_EraseRootFromParent_Done,
19027 /* 52530 */ // Label 1520: @52530
19028 /* 52530 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1521*/ GIMT_Encode4(52574), GIMT_Encode2(GIFBS_HasCRC_IsThumb2), // Rule ID 545 //
19029 /* 52537 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw),
19030 /* 52542 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19031 /* 52545 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19032 /* 52548 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19033 /* 52551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19034 /* 52555 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19035 /* 52559 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19036 /* 52563 */ // (intrinsic_wo_chain:{ *:[i32] } 3716:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CW:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19037 /* 52563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CW),
19038 /* 52566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19039 /* 52568 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19040 /* 52570 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19041 /* 52572 */ GIR_RootConstrainSelectedInstOperands,
19042 /* 52573 */ // GIR_Coverage, 545,
19043 /* 52573 */ GIR_EraseRootFromParent_Done,
19044 /* 52574 */ // Label 1521: @52574
19045 /* 52574 */ GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(52896),
19046 /* 52579 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
19047 /* 52584 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1529*/ GIMT_Encode4(52895),
19048 /* 52595 */ /*GILLT_v8s8*//*Label 1523*/ GIMT_Encode4(52619),
19049 /* 52599 */ /*GILLT_v16s8*//*Label 1524*/ GIMT_Encode4(52665),
19050 /* 52603 */ /*GILLT_v4s16*//*Label 1525*/ GIMT_Encode4(52711),
19051 /* 52607 */ /*GILLT_v8s16*//*Label 1526*/ GIMT_Encode4(52757),
19052 /* 52611 */ /*GILLT_v2s32*//*Label 1527*/ GIMT_Encode4(52803),
19053 /* 52615 */ /*GILLT_v4s32*//*Label 1528*/ GIMT_Encode4(52849),
19054 /* 52619 */ // Label 1523: @52619
19055 /* 52619 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1530*/ GIMT_Encode4(52664), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 916 //
19056 /* 52626 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
19057 /* 52629 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
19058 /* 52632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19059 /* 52636 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19060 /* 52640 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19061 /* 52644 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4003:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19062 /* 52644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i8),
19063 /* 52647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19064 /* 52649 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19065 /* 52651 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19066 /* 52653 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19067 /* 52656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19068 /* 52662 */ GIR_RootConstrainSelectedInstOperands,
19069 /* 52663 */ // GIR_Coverage, 916,
19070 /* 52663 */ GIR_EraseRootFromParent_Done,
19071 /* 52664 */ // Label 1530: @52664
19072 /* 52664 */ GIM_Reject,
19073 /* 52665 */ // Label 1524: @52665
19074 /* 52665 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1531*/ GIMT_Encode4(52710), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 917 //
19075 /* 52672 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
19076 /* 52675 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
19077 /* 52678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19078 /* 52682 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19079 /* 52686 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19080 /* 52690 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4003:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19081 /* 52690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv16i8),
19082 /* 52693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19083 /* 52695 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19084 /* 52697 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19085 /* 52699 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19086 /* 52702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19087 /* 52708 */ GIR_RootConstrainSelectedInstOperands,
19088 /* 52709 */ // GIR_Coverage, 917,
19089 /* 52709 */ GIR_EraseRootFromParent_Done,
19090 /* 52710 */ // Label 1531: @52710
19091 /* 52710 */ GIM_Reject,
19092 /* 52711 */ // Label 1525: @52711
19093 /* 52711 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1532*/ GIMT_Encode4(52756), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 912 //
19094 /* 52718 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19095 /* 52721 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
19096 /* 52724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19097 /* 52728 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19098 /* 52732 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19099 /* 52736 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4003:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19100 /* 52736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i16),
19101 /* 52739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19102 /* 52741 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19103 /* 52743 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19104 /* 52745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19105 /* 52748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19106 /* 52754 */ GIR_RootConstrainSelectedInstOperands,
19107 /* 52755 */ // GIR_Coverage, 912,
19108 /* 52755 */ GIR_EraseRootFromParent_Done,
19109 /* 52756 */ // Label 1532: @52756
19110 /* 52756 */ GIM_Reject,
19111 /* 52757 */ // Label 1526: @52757
19112 /* 52757 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1533*/ GIMT_Encode4(52802), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 914 //
19113 /* 52764 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
19114 /* 52767 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
19115 /* 52770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19116 /* 52774 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19117 /* 52778 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19118 /* 52782 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4003:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19119 /* 52782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i16),
19120 /* 52785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19121 /* 52787 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19122 /* 52789 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19123 /* 52791 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19124 /* 52794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19125 /* 52800 */ GIR_RootConstrainSelectedInstOperands,
19126 /* 52801 */ // GIR_Coverage, 914,
19127 /* 52801 */ GIR_EraseRootFromParent_Done,
19128 /* 52802 */ // Label 1533: @52802
19129 /* 52802 */ GIM_Reject,
19130 /* 52803 */ // Label 1527: @52803
19131 /* 52803 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1534*/ GIMT_Encode4(52848), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 913 //
19132 /* 52810 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
19133 /* 52813 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
19134 /* 52816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19135 /* 52820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19136 /* 52824 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19137 /* 52828 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4003:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19138 /* 52828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv2i32),
19139 /* 52831 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19140 /* 52833 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19141 /* 52835 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19142 /* 52837 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19143 /* 52840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19144 /* 52846 */ GIR_RootConstrainSelectedInstOperands,
19145 /* 52847 */ // GIR_Coverage, 913,
19146 /* 52847 */ GIR_EraseRootFromParent_Done,
19147 /* 52848 */ // Label 1534: @52848
19148 /* 52848 */ GIM_Reject,
19149 /* 52849 */ // Label 1528: @52849
19150 /* 52849 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1535*/ GIMT_Encode4(52894), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 915 //
19151 /* 52856 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
19152 /* 52859 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
19153 /* 52862 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19154 /* 52866 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19155 /* 52870 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19156 /* 52874 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4003:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19157 /* 52874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i32),
19158 /* 52877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19159 /* 52879 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19160 /* 52881 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19161 /* 52883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19162 /* 52886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19163 /* 52892 */ GIR_RootConstrainSelectedInstOperands,
19164 /* 52893 */ // GIR_Coverage, 915,
19165 /* 52893 */ GIR_EraseRootFromParent_Done,
19166 /* 52894 */ // Label 1535: @52894
19167 /* 52894 */ GIM_Reject,
19168 /* 52895 */ // Label 1529: @52895
19169 /* 52895 */ GIM_Reject,
19170 /* 52896 */ // Label 1522: @52896
19171 /* 52896 */ GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(53218),
19172 /* 52901 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
19173 /* 52906 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1543*/ GIMT_Encode4(53217),
19174 /* 52917 */ /*GILLT_v8s8*//*Label 1537*/ GIMT_Encode4(52941),
19175 /* 52921 */ /*GILLT_v16s8*//*Label 1538*/ GIMT_Encode4(52987),
19176 /* 52925 */ /*GILLT_v4s16*//*Label 1539*/ GIMT_Encode4(53033),
19177 /* 52929 */ /*GILLT_v8s16*//*Label 1540*/ GIMT_Encode4(53079),
19178 /* 52933 */ /*GILLT_v2s32*//*Label 1541*/ GIMT_Encode4(53125),
19179 /* 52937 */ /*GILLT_v4s32*//*Label 1542*/ GIMT_Encode4(53171),
19180 /* 52941 */ // Label 1537: @52941
19181 /* 52941 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1544*/ GIMT_Encode4(52986), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 922 //
19182 /* 52948 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
19183 /* 52951 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
19184 /* 52954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19185 /* 52958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19186 /* 52962 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19187 /* 52966 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4004:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19188 /* 52966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i8),
19189 /* 52969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19190 /* 52971 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19191 /* 52973 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19192 /* 52975 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19193 /* 52978 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19194 /* 52984 */ GIR_RootConstrainSelectedInstOperands,
19195 /* 52985 */ // GIR_Coverage, 922,
19196 /* 52985 */ GIR_EraseRootFromParent_Done,
19197 /* 52986 */ // Label 1544: @52986
19198 /* 52986 */ GIM_Reject,
19199 /* 52987 */ // Label 1538: @52987
19200 /* 52987 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1545*/ GIMT_Encode4(53032), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 923 //
19201 /* 52994 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
19202 /* 52997 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
19203 /* 53000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19204 /* 53004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19205 /* 53008 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19206 /* 53012 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4004:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19207 /* 53012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv16i8),
19208 /* 53015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19209 /* 53017 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19210 /* 53019 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19211 /* 53021 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19212 /* 53024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19213 /* 53030 */ GIR_RootConstrainSelectedInstOperands,
19214 /* 53031 */ // GIR_Coverage, 923,
19215 /* 53031 */ GIR_EraseRootFromParent_Done,
19216 /* 53032 */ // Label 1545: @53032
19217 /* 53032 */ GIM_Reject,
19218 /* 53033 */ // Label 1539: @53033
19219 /* 53033 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1546*/ GIMT_Encode4(53078), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 918 //
19220 /* 53040 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19221 /* 53043 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
19222 /* 53046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19223 /* 53050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19224 /* 53054 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19225 /* 53058 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4004:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19226 /* 53058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i16),
19227 /* 53061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19228 /* 53063 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19229 /* 53065 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19230 /* 53067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19231 /* 53070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19232 /* 53076 */ GIR_RootConstrainSelectedInstOperands,
19233 /* 53077 */ // GIR_Coverage, 918,
19234 /* 53077 */ GIR_EraseRootFromParent_Done,
19235 /* 53078 */ // Label 1546: @53078
19236 /* 53078 */ GIM_Reject,
19237 /* 53079 */ // Label 1540: @53079
19238 /* 53079 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1547*/ GIMT_Encode4(53124), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 920 //
19239 /* 53086 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
19240 /* 53089 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
19241 /* 53092 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19242 /* 53096 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19243 /* 53100 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19244 /* 53104 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4004:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19245 /* 53104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i16),
19246 /* 53107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19247 /* 53109 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19248 /* 53111 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19249 /* 53113 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19250 /* 53116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19251 /* 53122 */ GIR_RootConstrainSelectedInstOperands,
19252 /* 53123 */ // GIR_Coverage, 920,
19253 /* 53123 */ GIR_EraseRootFromParent_Done,
19254 /* 53124 */ // Label 1547: @53124
19255 /* 53124 */ GIM_Reject,
19256 /* 53125 */ // Label 1541: @53125
19257 /* 53125 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1548*/ GIMT_Encode4(53170), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 919 //
19258 /* 53132 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
19259 /* 53135 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
19260 /* 53138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19261 /* 53142 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19262 /* 53146 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19263 /* 53150 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4004:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19264 /* 53150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv2i32),
19265 /* 53153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19266 /* 53155 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19267 /* 53157 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19268 /* 53159 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19269 /* 53162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19270 /* 53168 */ GIR_RootConstrainSelectedInstOperands,
19271 /* 53169 */ // GIR_Coverage, 919,
19272 /* 53169 */ GIR_EraseRootFromParent_Done,
19273 /* 53170 */ // Label 1548: @53170
19274 /* 53170 */ GIM_Reject,
19275 /* 53171 */ // Label 1542: @53171
19276 /* 53171 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1549*/ GIMT_Encode4(53216), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 921 //
19277 /* 53178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
19278 /* 53181 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
19279 /* 53184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19280 /* 53188 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19281 /* 53192 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19282 /* 53196 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4004:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19283 /* 53196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i32),
19284 /* 53199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19285 /* 53201 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19286 /* 53203 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19287 /* 53205 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19288 /* 53208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19289 /* 53214 */ GIR_RootConstrainSelectedInstOperands,
19290 /* 53215 */ // GIR_Coverage, 921,
19291 /* 53215 */ GIR_EraseRootFromParent_Done,
19292 /* 53216 */ // Label 1549: @53216
19293 /* 53216 */ GIM_Reject,
19294 /* 53217 */ // Label 1543: @53217
19295 /* 53217 */ GIM_Reject,
19296 /* 53218 */ // Label 1536: @53218
19297 /* 53218 */ GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(53540),
19298 /* 53223 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
19299 /* 53228 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1557*/ GIMT_Encode4(53539),
19300 /* 53239 */ /*GILLT_v8s8*//*Label 1551*/ GIMT_Encode4(53263),
19301 /* 53243 */ /*GILLT_v16s8*//*Label 1552*/ GIMT_Encode4(53309),
19302 /* 53247 */ /*GILLT_v4s16*//*Label 1553*/ GIMT_Encode4(53355),
19303 /* 53251 */ /*GILLT_v8s16*//*Label 1554*/ GIMT_Encode4(53401),
19304 /* 53255 */ /*GILLT_v2s32*//*Label 1555*/ GIMT_Encode4(53447),
19305 /* 53259 */ /*GILLT_v4s32*//*Label 1556*/ GIMT_Encode4(53493),
19306 /* 53263 */ // Label 1551: @53263
19307 /* 53263 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1558*/ GIMT_Encode4(53308), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 928 //
19308 /* 53270 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
19309 /* 53273 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
19310 /* 53276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19311 /* 53280 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19312 /* 53284 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19313 /* 53288 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4063:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19314 /* 53288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i8),
19315 /* 53291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19316 /* 53293 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19317 /* 53295 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19318 /* 53297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19319 /* 53300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19320 /* 53306 */ GIR_RootConstrainSelectedInstOperands,
19321 /* 53307 */ // GIR_Coverage, 928,
19322 /* 53307 */ GIR_EraseRootFromParent_Done,
19323 /* 53308 */ // Label 1558: @53308
19324 /* 53308 */ GIM_Reject,
19325 /* 53309 */ // Label 1552: @53309
19326 /* 53309 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1559*/ GIMT_Encode4(53354), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 929 //
19327 /* 53316 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
19328 /* 53319 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
19329 /* 53322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19330 /* 53326 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19331 /* 53330 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19332 /* 53334 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4063:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19333 /* 53334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv16i8),
19334 /* 53337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19335 /* 53339 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19336 /* 53341 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19337 /* 53343 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19338 /* 53346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19339 /* 53352 */ GIR_RootConstrainSelectedInstOperands,
19340 /* 53353 */ // GIR_Coverage, 929,
19341 /* 53353 */ GIR_EraseRootFromParent_Done,
19342 /* 53354 */ // Label 1559: @53354
19343 /* 53354 */ GIM_Reject,
19344 /* 53355 */ // Label 1553: @53355
19345 /* 53355 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1560*/ GIMT_Encode4(53400), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 924 //
19346 /* 53362 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19347 /* 53365 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
19348 /* 53368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19349 /* 53372 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19350 /* 53376 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19351 /* 53380 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4063:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19352 /* 53380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i16),
19353 /* 53383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19354 /* 53385 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19355 /* 53387 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19356 /* 53389 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19357 /* 53392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19358 /* 53398 */ GIR_RootConstrainSelectedInstOperands,
19359 /* 53399 */ // GIR_Coverage, 924,
19360 /* 53399 */ GIR_EraseRootFromParent_Done,
19361 /* 53400 */ // Label 1560: @53400
19362 /* 53400 */ GIM_Reject,
19363 /* 53401 */ // Label 1554: @53401
19364 /* 53401 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1561*/ GIMT_Encode4(53446), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 926 //
19365 /* 53408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
19366 /* 53411 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
19367 /* 53414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19368 /* 53418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19369 /* 53422 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19370 /* 53426 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4063:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19371 /* 53426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i16),
19372 /* 53429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19373 /* 53431 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19374 /* 53433 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19375 /* 53435 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19376 /* 53438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19377 /* 53444 */ GIR_RootConstrainSelectedInstOperands,
19378 /* 53445 */ // GIR_Coverage, 926,
19379 /* 53445 */ GIR_EraseRootFromParent_Done,
19380 /* 53446 */ // Label 1561: @53446
19381 /* 53446 */ GIM_Reject,
19382 /* 53447 */ // Label 1555: @53447
19383 /* 53447 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1562*/ GIMT_Encode4(53492), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 925 //
19384 /* 53454 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
19385 /* 53457 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
19386 /* 53460 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19387 /* 53464 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19388 /* 53468 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19389 /* 53472 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4063:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19390 /* 53472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv2i32),
19391 /* 53475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19392 /* 53477 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19393 /* 53479 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19394 /* 53481 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19395 /* 53484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19396 /* 53490 */ GIR_RootConstrainSelectedInstOperands,
19397 /* 53491 */ // GIR_Coverage, 925,
19398 /* 53491 */ GIR_EraseRootFromParent_Done,
19399 /* 53492 */ // Label 1562: @53492
19400 /* 53492 */ GIM_Reject,
19401 /* 53493 */ // Label 1556: @53493
19402 /* 53493 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1563*/ GIMT_Encode4(53538), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 927 //
19403 /* 53500 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
19404 /* 53503 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
19405 /* 53506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19406 /* 53510 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19407 /* 53514 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19408 /* 53518 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4063:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19409 /* 53518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i32),
19410 /* 53521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19411 /* 53523 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19412 /* 53525 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19413 /* 53527 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19414 /* 53530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19415 /* 53536 */ GIR_RootConstrainSelectedInstOperands,
19416 /* 53537 */ // GIR_Coverage, 927,
19417 /* 53537 */ GIR_EraseRootFromParent_Done,
19418 /* 53538 */ // Label 1563: @53538
19419 /* 53538 */ GIM_Reject,
19420 /* 53539 */ // Label 1557: @53539
19421 /* 53539 */ GIM_Reject,
19422 /* 53540 */ // Label 1550: @53540
19423 /* 53540 */ GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(53862),
19424 /* 53545 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
19425 /* 53550 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1571*/ GIMT_Encode4(53861),
19426 /* 53561 */ /*GILLT_v8s8*//*Label 1565*/ GIMT_Encode4(53585),
19427 /* 53565 */ /*GILLT_v16s8*//*Label 1566*/ GIMT_Encode4(53631),
19428 /* 53569 */ /*GILLT_v4s16*//*Label 1567*/ GIMT_Encode4(53677),
19429 /* 53573 */ /*GILLT_v8s16*//*Label 1568*/ GIMT_Encode4(53723),
19430 /* 53577 */ /*GILLT_v2s32*//*Label 1569*/ GIMT_Encode4(53769),
19431 /* 53581 */ /*GILLT_v4s32*//*Label 1570*/ GIMT_Encode4(53815),
19432 /* 53585 */ // Label 1565: @53585
19433 /* 53585 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1572*/ GIMT_Encode4(53630), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 934 //
19434 /* 53592 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
19435 /* 53595 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
19436 /* 53598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19437 /* 53602 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19438 /* 53606 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19439 /* 53610 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4064:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19440 /* 53610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i8),
19441 /* 53613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19442 /* 53615 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19443 /* 53617 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19444 /* 53619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19445 /* 53622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19446 /* 53628 */ GIR_RootConstrainSelectedInstOperands,
19447 /* 53629 */ // GIR_Coverage, 934,
19448 /* 53629 */ GIR_EraseRootFromParent_Done,
19449 /* 53630 */ // Label 1572: @53630
19450 /* 53630 */ GIM_Reject,
19451 /* 53631 */ // Label 1566: @53631
19452 /* 53631 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1573*/ GIMT_Encode4(53676), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 935 //
19453 /* 53638 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
19454 /* 53641 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
19455 /* 53644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19456 /* 53648 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19457 /* 53652 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19458 /* 53656 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4064:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19459 /* 53656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv16i8),
19460 /* 53659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19461 /* 53661 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19462 /* 53663 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19463 /* 53665 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19464 /* 53668 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19465 /* 53674 */ GIR_RootConstrainSelectedInstOperands,
19466 /* 53675 */ // GIR_Coverage, 935,
19467 /* 53675 */ GIR_EraseRootFromParent_Done,
19468 /* 53676 */ // Label 1573: @53676
19469 /* 53676 */ GIM_Reject,
19470 /* 53677 */ // Label 1567: @53677
19471 /* 53677 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1574*/ GIMT_Encode4(53722), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 930 //
19472 /* 53684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19473 /* 53687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
19474 /* 53690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19475 /* 53694 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19476 /* 53698 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19477 /* 53702 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4064:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19478 /* 53702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i16),
19479 /* 53705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19480 /* 53707 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19481 /* 53709 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19482 /* 53711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19483 /* 53714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19484 /* 53720 */ GIR_RootConstrainSelectedInstOperands,
19485 /* 53721 */ // GIR_Coverage, 930,
19486 /* 53721 */ GIR_EraseRootFromParent_Done,
19487 /* 53722 */ // Label 1574: @53722
19488 /* 53722 */ GIM_Reject,
19489 /* 53723 */ // Label 1568: @53723
19490 /* 53723 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1575*/ GIMT_Encode4(53768), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 932 //
19491 /* 53730 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
19492 /* 53733 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
19493 /* 53736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19494 /* 53740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19495 /* 53744 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19496 /* 53748 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4064:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19497 /* 53748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i16),
19498 /* 53751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19499 /* 53753 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19500 /* 53755 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19501 /* 53757 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19502 /* 53760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19503 /* 53766 */ GIR_RootConstrainSelectedInstOperands,
19504 /* 53767 */ // GIR_Coverage, 932,
19505 /* 53767 */ GIR_EraseRootFromParent_Done,
19506 /* 53768 */ // Label 1575: @53768
19507 /* 53768 */ GIM_Reject,
19508 /* 53769 */ // Label 1569: @53769
19509 /* 53769 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1576*/ GIMT_Encode4(53814), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 931 //
19510 /* 53776 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
19511 /* 53779 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
19512 /* 53782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19513 /* 53786 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19514 /* 53790 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19515 /* 53794 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4064:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19516 /* 53794 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv2i32),
19517 /* 53797 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19518 /* 53799 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19519 /* 53801 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19520 /* 53803 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19521 /* 53806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19522 /* 53812 */ GIR_RootConstrainSelectedInstOperands,
19523 /* 53813 */ // GIR_Coverage, 931,
19524 /* 53813 */ GIR_EraseRootFromParent_Done,
19525 /* 53814 */ // Label 1576: @53814
19526 /* 53814 */ GIM_Reject,
19527 /* 53815 */ // Label 1570: @53815
19528 /* 53815 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1577*/ GIMT_Encode4(53860), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 933 //
19529 /* 53822 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
19530 /* 53825 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
19531 /* 53828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19532 /* 53832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19533 /* 53836 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19534 /* 53840 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4064:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19535 /* 53840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i32),
19536 /* 53843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19537 /* 53845 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19538 /* 53847 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19539 /* 53849 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19540 /* 53852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19541 /* 53858 */ GIR_RootConstrainSelectedInstOperands,
19542 /* 53859 */ // GIR_Coverage, 933,
19543 /* 53859 */ GIR_EraseRootFromParent_Done,
19544 /* 53860 */ // Label 1577: @53860
19545 /* 53860 */ GIM_Reject,
19546 /* 53861 */ // Label 1571: @53861
19547 /* 53861 */ GIM_Reject,
19548 /* 53862 */ // Label 1564: @53862
19549 /* 53862 */ GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(54042),
19550 /* 53867 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn),
19551 /* 53872 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1582*/ GIMT_Encode4(54041),
19552 /* 53883 */ /*GILLT_v8s8*//*Label 1579*/ GIMT_Encode4(53903), GIMT_Encode4(0),
19553 /* 53891 */ /*GILLT_v4s16*//*Label 1580*/ GIMT_Encode4(53949), GIMT_Encode4(0),
19554 /* 53899 */ /*GILLT_v2s32*//*Label 1581*/ GIMT_Encode4(53995),
19555 /* 53903 */ // Label 1579: @53903
19556 /* 53903 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1583*/ GIMT_Encode4(53948), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 952 //
19557 /* 53910 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
19558 /* 53913 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
19559 /* 53916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19560 /* 53920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19561 /* 53924 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19562 /* 53928 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4060:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRADDHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19563 /* 53928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv8i8),
19564 /* 53931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19565 /* 53933 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19566 /* 53935 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19567 /* 53937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19568 /* 53940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19569 /* 53946 */ GIR_RootConstrainSelectedInstOperands,
19570 /* 53947 */ // GIR_Coverage, 952,
19571 /* 53947 */ GIR_EraseRootFromParent_Done,
19572 /* 53948 */ // Label 1583: @53948
19573 /* 53948 */ GIM_Reject,
19574 /* 53949 */ // Label 1580: @53949
19575 /* 53949 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1584*/ GIMT_Encode4(53994), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 953 //
19576 /* 53956 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
19577 /* 53959 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
19578 /* 53962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19579 /* 53966 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19580 /* 53970 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19581 /* 53974 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4060:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRADDHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19582 /* 53974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv4i16),
19583 /* 53977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19584 /* 53979 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19585 /* 53981 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19586 /* 53983 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19587 /* 53986 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19588 /* 53992 */ GIR_RootConstrainSelectedInstOperands,
19589 /* 53993 */ // GIR_Coverage, 953,
19590 /* 53993 */ GIR_EraseRootFromParent_Done,
19591 /* 53994 */ // Label 1584: @53994
19592 /* 53994 */ GIM_Reject,
19593 /* 53995 */ // Label 1581: @53995
19594 /* 53995 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1585*/ GIMT_Encode4(54040), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 954 //
19595 /* 54002 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
19596 /* 54005 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
19597 /* 54008 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19598 /* 54012 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19599 /* 54016 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19600 /* 54020 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4060:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRADDHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
19601 /* 54020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv2i32),
19602 /* 54023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19603 /* 54025 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19604 /* 54027 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19605 /* 54029 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19606 /* 54032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19607 /* 54038 */ GIR_RootConstrainSelectedInstOperands,
19608 /* 54039 */ // GIR_Coverage, 954,
19609 /* 54039 */ GIR_EraseRootFromParent_Done,
19610 /* 54040 */ // Label 1585: @54040
19611 /* 54040 */ GIM_Reject,
19612 /* 54041 */ // Label 1582: @54041
19613 /* 54041 */ GIM_Reject,
19614 /* 54042 */ // Label 1578: @54042
19615 /* 54042 */ GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(54164),
19616 /* 54047 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp),
19617 /* 54052 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 1589*/ GIMT_Encode4(54163),
19618 /* 54063 */ /*GILLT_v8s8*//*Label 1587*/ GIMT_Encode4(54071),
19619 /* 54067 */ /*GILLT_v16s8*//*Label 1588*/ GIMT_Encode4(54117),
19620 /* 54071 */ // Label 1587: @54071
19621 /* 54071 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1590*/ GIMT_Encode4(54116), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 961 //
19622 /* 54078 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
19623 /* 54081 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
19624 /* 54084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19625 /* 54088 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19626 /* 54092 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19627 /* 54096 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4029:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULpd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19628 /* 54096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpd),
19629 /* 54099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19630 /* 54101 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19631 /* 54103 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19632 /* 54105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19633 /* 54108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19634 /* 54114 */ GIR_RootConstrainSelectedInstOperands,
19635 /* 54115 */ // GIR_Coverage, 961,
19636 /* 54115 */ GIR_EraseRootFromParent_Done,
19637 /* 54116 */ // Label 1590: @54116
19638 /* 54116 */ GIM_Reject,
19639 /* 54117 */ // Label 1588: @54117
19640 /* 54117 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1591*/ GIMT_Encode4(54162), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 962 //
19641 /* 54124 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
19642 /* 54127 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
19643 /* 54130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19644 /* 54134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19645 /* 54138 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19646 /* 54142 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4029:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULpq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19647 /* 54142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpq),
19648 /* 54145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19649 /* 54147 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19650 /* 54149 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19651 /* 54151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19652 /* 54154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19653 /* 54160 */ GIR_RootConstrainSelectedInstOperands,
19654 /* 54161 */ // GIR_Coverage, 962,
19655 /* 54161 */ GIR_EraseRootFromParent_Done,
19656 /* 54162 */ // Label 1591: @54162
19657 /* 54162 */ GIM_Reject,
19658 /* 54163 */ // Label 1589: @54163
19659 /* 54163 */ GIM_Reject,
19660 /* 54164 */ // Label 1586: @54164
19661 /* 54164 */ GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(54386),
19662 /* 54169 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh),
19663 /* 54174 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1597*/ GIMT_Encode4(54385),
19664 /* 54185 */ /*GILLT_v4s16*//*Label 1593*/ GIMT_Encode4(54201),
19665 /* 54189 */ /*GILLT_v8s16*//*Label 1594*/ GIMT_Encode4(54247),
19666 /* 54193 */ /*GILLT_v2s32*//*Label 1595*/ GIMT_Encode4(54293),
19667 /* 54197 */ /*GILLT_v4s32*//*Label 1596*/ GIMT_Encode4(54339),
19668 /* 54201 */ // Label 1593: @54201
19669 /* 54201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1598*/ GIMT_Encode4(54246), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 975 //
19670 /* 54208 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19671 /* 54211 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
19672 /* 54214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19673 /* 54218 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19674 /* 54222 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19675 /* 54226 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4040:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19676 /* 54226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i16),
19677 /* 54229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19678 /* 54231 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19679 /* 54233 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19680 /* 54235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19681 /* 54238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19682 /* 54244 */ GIR_RootConstrainSelectedInstOperands,
19683 /* 54245 */ // GIR_Coverage, 975,
19684 /* 54245 */ GIR_EraseRootFromParent_Done,
19685 /* 54246 */ // Label 1598: @54246
19686 /* 54246 */ GIM_Reject,
19687 /* 54247 */ // Label 1594: @54247
19688 /* 54247 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1599*/ GIMT_Encode4(54292), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 977 //
19689 /* 54254 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
19690 /* 54257 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
19691 /* 54260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19692 /* 54264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19693 /* 54268 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19694 /* 54272 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4040:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19695 /* 54272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv8i16),
19696 /* 54275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19697 /* 54277 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19698 /* 54279 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19699 /* 54281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19700 /* 54284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19701 /* 54290 */ GIR_RootConstrainSelectedInstOperands,
19702 /* 54291 */ // GIR_Coverage, 977,
19703 /* 54291 */ GIR_EraseRootFromParent_Done,
19704 /* 54292 */ // Label 1599: @54292
19705 /* 54292 */ GIM_Reject,
19706 /* 54293 */ // Label 1595: @54293
19707 /* 54293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1600*/ GIMT_Encode4(54338), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 976 //
19708 /* 54300 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
19709 /* 54303 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
19710 /* 54306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19711 /* 54310 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19712 /* 54314 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19713 /* 54318 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4040:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19714 /* 54318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv2i32),
19715 /* 54321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19716 /* 54323 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19717 /* 54325 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19718 /* 54327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19719 /* 54330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19720 /* 54336 */ GIR_RootConstrainSelectedInstOperands,
19721 /* 54337 */ // GIR_Coverage, 976,
19722 /* 54337 */ GIR_EraseRootFromParent_Done,
19723 /* 54338 */ // Label 1600: @54338
19724 /* 54338 */ GIM_Reject,
19725 /* 54339 */ // Label 1596: @54339
19726 /* 54339 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1601*/ GIMT_Encode4(54384), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 978 //
19727 /* 54346 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
19728 /* 54349 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
19729 /* 54352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19730 /* 54356 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19731 /* 54360 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19732 /* 54364 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4040:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19733 /* 54364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i32),
19734 /* 54367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19735 /* 54369 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19736 /* 54371 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19737 /* 54373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19738 /* 54376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19739 /* 54382 */ GIR_RootConstrainSelectedInstOperands,
19740 /* 54383 */ // GIR_Coverage, 978,
19741 /* 54383 */ GIR_EraseRootFromParent_Done,
19742 /* 54384 */ // Label 1601: @54384
19743 /* 54384 */ GIM_Reject,
19744 /* 54385 */ // Label 1597: @54385
19745 /* 54385 */ GIM_Reject,
19746 /* 54386 */ // Label 1592: @54386
19747 /* 54386 */ GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(54608),
19748 /* 54391 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh),
19749 /* 54396 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1607*/ GIMT_Encode4(54607),
19750 /* 54407 */ /*GILLT_v4s16*//*Label 1603*/ GIMT_Encode4(54423),
19751 /* 54411 */ /*GILLT_v8s16*//*Label 1604*/ GIMT_Encode4(54469),
19752 /* 54415 */ /*GILLT_v2s32*//*Label 1605*/ GIMT_Encode4(54515),
19753 /* 54419 */ /*GILLT_v4s32*//*Label 1606*/ GIMT_Encode4(54561),
19754 /* 54423 */ // Label 1603: @54423
19755 /* 54423 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1608*/ GIMT_Encode4(54468), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 983 //
19756 /* 54430 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19757 /* 54433 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
19758 /* 54436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19759 /* 54440 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19760 /* 54444 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19761 /* 54448 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4048:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19762 /* 54448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i16),
19763 /* 54451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19764 /* 54453 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19765 /* 54455 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19766 /* 54457 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19767 /* 54460 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19768 /* 54466 */ GIR_RootConstrainSelectedInstOperands,
19769 /* 54467 */ // GIR_Coverage, 983,
19770 /* 54467 */ GIR_EraseRootFromParent_Done,
19771 /* 54468 */ // Label 1608: @54468
19772 /* 54468 */ GIM_Reject,
19773 /* 54469 */ // Label 1604: @54469
19774 /* 54469 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1609*/ GIMT_Encode4(54514), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 985 //
19775 /* 54476 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
19776 /* 54479 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
19777 /* 54482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19778 /* 54486 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19779 /* 54490 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19780 /* 54494 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4048:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19781 /* 54494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv8i16),
19782 /* 54497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19783 /* 54499 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19784 /* 54501 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19785 /* 54503 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19786 /* 54506 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19787 /* 54512 */ GIR_RootConstrainSelectedInstOperands,
19788 /* 54513 */ // GIR_Coverage, 985,
19789 /* 54513 */ GIR_EraseRootFromParent_Done,
19790 /* 54514 */ // Label 1609: @54514
19791 /* 54514 */ GIM_Reject,
19792 /* 54515 */ // Label 1605: @54515
19793 /* 54515 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1610*/ GIMT_Encode4(54560), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 984 //
19794 /* 54522 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
19795 /* 54525 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
19796 /* 54528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19797 /* 54532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19798 /* 54536 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19799 /* 54540 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4048:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19800 /* 54540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv2i32),
19801 /* 54543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19802 /* 54545 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19803 /* 54547 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19804 /* 54549 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19805 /* 54552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19806 /* 54558 */ GIR_RootConstrainSelectedInstOperands,
19807 /* 54559 */ // GIR_Coverage, 984,
19808 /* 54559 */ GIR_EraseRootFromParent_Done,
19809 /* 54560 */ // Label 1610: @54560
19810 /* 54560 */ GIM_Reject,
19811 /* 54561 */ // Label 1606: @54561
19812 /* 54561 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1611*/ GIMT_Encode4(54606), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 986 //
19813 /* 54568 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
19814 /* 54571 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
19815 /* 54574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19816 /* 54578 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19817 /* 54582 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19818 /* 54586 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4048:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
19819 /* 54586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i32),
19820 /* 54589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19821 /* 54591 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19822 /* 54593 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19823 /* 54595 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19824 /* 54598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19825 /* 54604 */ GIR_RootConstrainSelectedInstOperands,
19826 /* 54605 */ // GIR_Coverage, 986,
19827 /* 54605 */ GIR_EraseRootFromParent_Done,
19828 /* 54606 */ // Label 1611: @54606
19829 /* 54606 */ GIM_Reject,
19830 /* 54607 */ // Label 1607: @54607
19831 /* 54607 */ GIM_Reject,
19832 /* 54608 */ // Label 1602: @54608
19833 /* 54608 */ GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(54729),
19834 /* 54613 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp),
19835 /* 54618 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 1615*/ GIMT_Encode4(54728),
19836 /* 54629 */ /*GILLT_v8s16*//*Label 1613*/ GIMT_Encode4(54645), GIMT_Encode4(0), GIMT_Encode4(0),
19837 /* 54641 */ /*GILLT_v2s64*//*Label 1614*/ GIMT_Encode4(54691),
19838 /* 54645 */ // Label 1613: @54645
19839 /* 54645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1616*/ GIMT_Encode4(54690), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 997 //
19840 /* 54652 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
19841 /* 54655 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
19842 /* 54658 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19843 /* 54662 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19844 /* 54666 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19845 /* 54670 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4026:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULLp8:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19846 /* 54670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp8),
19847 /* 54673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19848 /* 54675 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19849 /* 54677 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19850 /* 54679 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19851 /* 54682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19852 /* 54688 */ GIR_RootConstrainSelectedInstOperands,
19853 /* 54689 */ // GIR_Coverage, 997,
19854 /* 54689 */ GIR_EraseRootFromParent_Done,
19855 /* 54690 */ // Label 1616: @54690
19856 /* 54690 */ GIM_Reject,
19857 /* 54691 */ // Label 1614: @54691
19858 /* 54691 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1617*/ GIMT_Encode4(54727), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 998 //
19859 /* 54698 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
19860 /* 54701 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
19861 /* 54704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19862 /* 54708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19863 /* 54712 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19864 /* 54716 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4026:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VMULLp64:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
19865 /* 54716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp64),
19866 /* 54719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19867 /* 54721 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19868 /* 54723 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19869 /* 54725 */ GIR_RootConstrainSelectedInstOperands,
19870 /* 54726 */ // GIR_Coverage, 998,
19871 /* 54726 */ GIR_EraseRootFromParent_Done,
19872 /* 54727 */ // Label 1617: @54727
19873 /* 54727 */ GIM_Reject,
19874 /* 54728 */ // Label 1615: @54728
19875 /* 54728 */ GIM_Reject,
19876 /* 54729 */ // Label 1612: @54729
19877 /* 54729 */ GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(54851),
19878 /* 54734 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
19879 /* 54739 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 1621*/ GIMT_Encode4(54850),
19880 /* 54750 */ /*GILLT_v4s32*//*Label 1619*/ GIMT_Encode4(54758),
19881 /* 54754 */ /*GILLT_v2s64*//*Label 1620*/ GIMT_Encode4(54804),
19882 /* 54758 */ // Label 1619: @54758
19883 /* 54758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1622*/ GIMT_Encode4(54803), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1003 //
19884 /* 54765 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19885 /* 54768 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
19886 /* 54771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19887 /* 54775 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19888 /* 54779 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19889 /* 54783 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4041:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULLv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19890 /* 54783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv4i32),
19891 /* 54786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19892 /* 54788 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19893 /* 54790 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19894 /* 54792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19895 /* 54795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19896 /* 54801 */ GIR_RootConstrainSelectedInstOperands,
19897 /* 54802 */ // GIR_Coverage, 1003,
19898 /* 54802 */ GIR_EraseRootFromParent_Done,
19899 /* 54803 */ // Label 1622: @54803
19900 /* 54803 */ GIM_Reject,
19901 /* 54804 */ // Label 1620: @54804
19902 /* 54804 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1623*/ GIMT_Encode4(54849), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1004 //
19903 /* 54811 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
19904 /* 54814 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
19905 /* 54817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19906 /* 54821 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19907 /* 54825 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19908 /* 54829 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4041:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULLv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
19909 /* 54829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv2i64),
19910 /* 54832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19911 /* 54834 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19912 /* 54836 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19913 /* 54838 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19914 /* 54841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19915 /* 54847 */ GIR_RootConstrainSelectedInstOperands,
19916 /* 54848 */ // GIR_Coverage, 1004,
19917 /* 54848 */ GIR_EraseRootFromParent_Done,
19918 /* 54849 */ // Label 1623: @54849
19919 /* 54849 */ GIM_Reject,
19920 /* 54850 */ // Label 1621: @54850
19921 /* 54850 */ GIM_Reject,
19922 /* 54851 */ // Label 1618: @54851
19923 /* 54851 */ GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(55173),
19924 /* 54856 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
19925 /* 54861 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1631*/ GIMT_Encode4(55172),
19926 /* 54872 */ /*GILLT_v8s8*//*Label 1625*/ GIMT_Encode4(54896),
19927 /* 54876 */ /*GILLT_v16s8*//*Label 1626*/ GIMT_Encode4(54942),
19928 /* 54880 */ /*GILLT_v4s16*//*Label 1627*/ GIMT_Encode4(54988),
19929 /* 54884 */ /*GILLT_v8s16*//*Label 1628*/ GIMT_Encode4(55034),
19930 /* 54888 */ /*GILLT_v2s32*//*Label 1629*/ GIMT_Encode4(55080),
19931 /* 54892 */ /*GILLT_v4s32*//*Label 1630*/ GIMT_Encode4(55126),
19932 /* 54896 */ // Label 1625: @54896
19933 /* 54896 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1632*/ GIMT_Encode4(54941), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1162 //
19934 /* 54903 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
19935 /* 54906 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
19936 /* 54909 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19937 /* 54913 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19938 /* 54917 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19939 /* 54921 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4005:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
19940 /* 54921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i8),
19941 /* 54924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19942 /* 54926 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19943 /* 54928 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19944 /* 54930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19945 /* 54933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19946 /* 54939 */ GIR_RootConstrainSelectedInstOperands,
19947 /* 54940 */ // GIR_Coverage, 1162,
19948 /* 54940 */ GIR_EraseRootFromParent_Done,
19949 /* 54941 */ // Label 1632: @54941
19950 /* 54941 */ GIM_Reject,
19951 /* 54942 */ // Label 1626: @54942
19952 /* 54942 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1633*/ GIMT_Encode4(54987), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1163 //
19953 /* 54949 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
19954 /* 54952 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
19955 /* 54955 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19956 /* 54959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19957 /* 54963 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19958 /* 54967 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4005:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
19959 /* 54967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv16i8),
19960 /* 54970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19961 /* 54972 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19962 /* 54974 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19963 /* 54976 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19964 /* 54979 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19965 /* 54985 */ GIR_RootConstrainSelectedInstOperands,
19966 /* 54986 */ // GIR_Coverage, 1163,
19967 /* 54986 */ GIR_EraseRootFromParent_Done,
19968 /* 54987 */ // Label 1633: @54987
19969 /* 54987 */ GIM_Reject,
19970 /* 54988 */ // Label 1627: @54988
19971 /* 54988 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1634*/ GIMT_Encode4(55033), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1158 //
19972 /* 54995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
19973 /* 54998 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
19974 /* 55001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19975 /* 55005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19976 /* 55009 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
19977 /* 55013 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4005:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
19978 /* 55013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i16),
19979 /* 55016 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19980 /* 55018 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
19981 /* 55020 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
19982 /* 55022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19983 /* 55025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19984 /* 55031 */ GIR_RootConstrainSelectedInstOperands,
19985 /* 55032 */ // GIR_Coverage, 1158,
19986 /* 55032 */ GIR_EraseRootFromParent_Done,
19987 /* 55033 */ // Label 1634: @55033
19988 /* 55033 */ GIM_Reject,
19989 /* 55034 */ // Label 1628: @55034
19990 /* 55034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1635*/ GIMT_Encode4(55079), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1160 //
19991 /* 55041 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
19992 /* 55044 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
19993 /* 55047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19994 /* 55051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19995 /* 55055 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
19996 /* 55059 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4005:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
19997 /* 55059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i16),
19998 /* 55062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
19999 /* 55064 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20000 /* 55066 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20001 /* 55068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20002 /* 55071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20003 /* 55077 */ GIR_RootConstrainSelectedInstOperands,
20004 /* 55078 */ // GIR_Coverage, 1160,
20005 /* 55078 */ GIR_EraseRootFromParent_Done,
20006 /* 55079 */ // Label 1635: @55079
20007 /* 55079 */ GIM_Reject,
20008 /* 55080 */ // Label 1629: @55080
20009 /* 55080 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1636*/ GIMT_Encode4(55125), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1159 //
20010 /* 55087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20011 /* 55090 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20012 /* 55093 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20013 /* 55097 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20014 /* 55101 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20015 /* 55105 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4005:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20016 /* 55105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv2i32),
20017 /* 55108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20018 /* 55110 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20019 /* 55112 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20020 /* 55114 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20021 /* 55117 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20022 /* 55123 */ GIR_RootConstrainSelectedInstOperands,
20023 /* 55124 */ // GIR_Coverage, 1159,
20024 /* 55124 */ GIR_EraseRootFromParent_Done,
20025 /* 55125 */ // Label 1636: @55125
20026 /* 55125 */ GIM_Reject,
20027 /* 55126 */ // Label 1630: @55126
20028 /* 55126 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1637*/ GIMT_Encode4(55171), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1161 //
20029 /* 55133 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20030 /* 55136 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20031 /* 55139 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20032 /* 55143 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20033 /* 55147 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20034 /* 55151 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4005:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20035 /* 55151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i32),
20036 /* 55154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20037 /* 55156 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20038 /* 55158 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20039 /* 55160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20040 /* 55163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20041 /* 55169 */ GIR_RootConstrainSelectedInstOperands,
20042 /* 55170 */ // GIR_Coverage, 1161,
20043 /* 55170 */ GIR_EraseRootFromParent_Done,
20044 /* 55171 */ // Label 1637: @55171
20045 /* 55171 */ GIM_Reject,
20046 /* 55172 */ // Label 1631: @55172
20047 /* 55172 */ GIM_Reject,
20048 /* 55173 */ // Label 1624: @55173
20049 /* 55173 */ GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(55495),
20050 /* 55178 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
20051 /* 55183 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 1645*/ GIMT_Encode4(55494),
20052 /* 55194 */ /*GILLT_v8s8*//*Label 1639*/ GIMT_Encode4(55218),
20053 /* 55198 */ /*GILLT_v16s8*//*Label 1640*/ GIMT_Encode4(55264),
20054 /* 55202 */ /*GILLT_v4s16*//*Label 1641*/ GIMT_Encode4(55310),
20055 /* 55206 */ /*GILLT_v8s16*//*Label 1642*/ GIMT_Encode4(55356),
20056 /* 55210 */ /*GILLT_v2s32*//*Label 1643*/ GIMT_Encode4(55402),
20057 /* 55214 */ /*GILLT_v4s32*//*Label 1644*/ GIMT_Encode4(55448),
20058 /* 55218 */ // Label 1639: @55218
20059 /* 55218 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1646*/ GIMT_Encode4(55263), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1168 //
20060 /* 55225 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20061 /* 55228 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20062 /* 55231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20063 /* 55235 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20064 /* 55239 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20065 /* 55243 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4006:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20066 /* 55243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i8),
20067 /* 55246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20068 /* 55248 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20069 /* 55250 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20070 /* 55252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20071 /* 55255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20072 /* 55261 */ GIR_RootConstrainSelectedInstOperands,
20073 /* 55262 */ // GIR_Coverage, 1168,
20074 /* 55262 */ GIR_EraseRootFromParent_Done,
20075 /* 55263 */ // Label 1646: @55263
20076 /* 55263 */ GIM_Reject,
20077 /* 55264 */ // Label 1640: @55264
20078 /* 55264 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1647*/ GIMT_Encode4(55309), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1169 //
20079 /* 55271 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20080 /* 55274 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20081 /* 55277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20082 /* 55281 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20083 /* 55285 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20084 /* 55289 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4006:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20085 /* 55289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv16i8),
20086 /* 55292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20087 /* 55294 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20088 /* 55296 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20089 /* 55298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20090 /* 55301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20091 /* 55307 */ GIR_RootConstrainSelectedInstOperands,
20092 /* 55308 */ // GIR_Coverage, 1169,
20093 /* 55308 */ GIR_EraseRootFromParent_Done,
20094 /* 55309 */ // Label 1647: @55309
20095 /* 55309 */ GIM_Reject,
20096 /* 55310 */ // Label 1641: @55310
20097 /* 55310 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1648*/ GIMT_Encode4(55355), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1164 //
20098 /* 55317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20099 /* 55320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20100 /* 55323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20101 /* 55327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20102 /* 55331 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20103 /* 55335 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4006:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20104 /* 55335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i16),
20105 /* 55338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20106 /* 55340 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20107 /* 55342 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20108 /* 55344 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20109 /* 55347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20110 /* 55353 */ GIR_RootConstrainSelectedInstOperands,
20111 /* 55354 */ // GIR_Coverage, 1164,
20112 /* 55354 */ GIR_EraseRootFromParent_Done,
20113 /* 55355 */ // Label 1648: @55355
20114 /* 55355 */ GIM_Reject,
20115 /* 55356 */ // Label 1642: @55356
20116 /* 55356 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1649*/ GIMT_Encode4(55401), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1166 //
20117 /* 55363 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20118 /* 55366 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20119 /* 55369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20120 /* 55373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20121 /* 55377 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20122 /* 55381 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4006:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20123 /* 55381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i16),
20124 /* 55384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20125 /* 55386 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20126 /* 55388 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20127 /* 55390 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20128 /* 55393 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20129 /* 55399 */ GIR_RootConstrainSelectedInstOperands,
20130 /* 55400 */ // GIR_Coverage, 1166,
20131 /* 55400 */ GIR_EraseRootFromParent_Done,
20132 /* 55401 */ // Label 1649: @55401
20133 /* 55401 */ GIM_Reject,
20134 /* 55402 */ // Label 1643: @55402
20135 /* 55402 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1650*/ GIMT_Encode4(55447), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1165 //
20136 /* 55409 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20137 /* 55412 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20138 /* 55415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20139 /* 55419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20140 /* 55423 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20141 /* 55427 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4006:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20142 /* 55427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv2i32),
20143 /* 55430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20144 /* 55432 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20145 /* 55434 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20146 /* 55436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20147 /* 55439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20148 /* 55445 */ GIR_RootConstrainSelectedInstOperands,
20149 /* 55446 */ // GIR_Coverage, 1165,
20150 /* 55446 */ GIR_EraseRootFromParent_Done,
20151 /* 55447 */ // Label 1650: @55447
20152 /* 55447 */ GIM_Reject,
20153 /* 55448 */ // Label 1644: @55448
20154 /* 55448 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1651*/ GIMT_Encode4(55493), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1167 //
20155 /* 55455 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20156 /* 55458 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20157 /* 55461 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20158 /* 55465 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20159 /* 55469 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20160 /* 55473 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4006:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20161 /* 55473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i32),
20162 /* 55476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20163 /* 55478 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20164 /* 55480 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20165 /* 55482 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20166 /* 55485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20167 /* 55491 */ GIR_RootConstrainSelectedInstOperands,
20168 /* 55492 */ // GIR_Coverage, 1167,
20169 /* 55492 */ GIR_EraseRootFromParent_Done,
20170 /* 55493 */ // Label 1651: @55493
20171 /* 55493 */ GIM_Reject,
20172 /* 55494 */ // Label 1645: @55494
20173 /* 55494 */ GIM_Reject,
20174 /* 55495 */ // Label 1638: @55495
20175 /* 55495 */ GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(55675),
20176 /* 55500 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn),
20177 /* 55505 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1656*/ GIMT_Encode4(55674),
20178 /* 55516 */ /*GILLT_v8s8*//*Label 1653*/ GIMT_Encode4(55536), GIMT_Encode4(0),
20179 /* 55524 */ /*GILLT_v4s16*//*Label 1654*/ GIMT_Encode4(55582), GIMT_Encode4(0),
20180 /* 55532 */ /*GILLT_v2s32*//*Label 1655*/ GIMT_Encode4(55628),
20181 /* 55536 */ // Label 1653: @55536
20182 /* 55536 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1657*/ GIMT_Encode4(55581), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1186 //
20183 /* 55543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20184 /* 55546 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20185 /* 55549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20186 /* 55553 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20187 /* 55557 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20188 /* 55561 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4070:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRSUBHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20189 /* 55561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv8i8),
20190 /* 55564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20191 /* 55566 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20192 /* 55568 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20193 /* 55570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20194 /* 55573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20195 /* 55579 */ GIR_RootConstrainSelectedInstOperands,
20196 /* 55580 */ // GIR_Coverage, 1186,
20197 /* 55580 */ GIR_EraseRootFromParent_Done,
20198 /* 55581 */ // Label 1657: @55581
20199 /* 55581 */ GIM_Reject,
20200 /* 55582 */ // Label 1654: @55582
20201 /* 55582 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1658*/ GIMT_Encode4(55627), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1187 //
20202 /* 55589 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20203 /* 55592 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20204 /* 55595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20205 /* 55599 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20206 /* 55603 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20207 /* 55607 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4070:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRSUBHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20208 /* 55607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv4i16),
20209 /* 55610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20210 /* 55612 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20211 /* 55614 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20212 /* 55616 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20213 /* 55619 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20214 /* 55625 */ GIR_RootConstrainSelectedInstOperands,
20215 /* 55626 */ // GIR_Coverage, 1187,
20216 /* 55626 */ GIR_EraseRootFromParent_Done,
20217 /* 55627 */ // Label 1658: @55627
20218 /* 55627 */ GIM_Reject,
20219 /* 55628 */ // Label 1655: @55628
20220 /* 55628 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1659*/ GIMT_Encode4(55673), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1188 //
20221 /* 55635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20222 /* 55638 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
20223 /* 55641 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20224 /* 55645 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20225 /* 55649 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20226 /* 55653 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4070:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRSUBHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
20227 /* 55653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv2i32),
20228 /* 55656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20229 /* 55658 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20230 /* 55660 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20231 /* 55662 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20232 /* 55665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20233 /* 55671 */ GIR_RootConstrainSelectedInstOperands,
20234 /* 55672 */ // GIR_Coverage, 1188,
20235 /* 55672 */ GIR_EraseRootFromParent_Done,
20236 /* 55673 */ // Label 1659: @55673
20237 /* 55673 */ GIM_Reject,
20238 /* 55674 */ // Label 1656: @55674
20239 /* 55674 */ GIM_Reject,
20240 /* 55675 */ // Label 1652: @55675
20241 /* 55675 */ GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(55897),
20242 /* 55680 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge),
20243 /* 55685 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1665*/ GIMT_Encode4(55896),
20244 /* 55696 */ /*GILLT_v4s16*//*Label 1661*/ GIMT_Encode4(55712),
20245 /* 55700 */ /*GILLT_v8s16*//*Label 1662*/ GIMT_Encode4(55758),
20246 /* 55704 */ /*GILLT_v2s32*//*Label 1663*/ GIMT_Encode4(55804),
20247 /* 55708 */ /*GILLT_v4s32*//*Label 1664*/ GIMT_Encode4(55850),
20248 /* 55712 */ // Label 1661: @55712
20249 /* 55712 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1666*/ GIMT_Encode4(55757), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1283 //
20250 /* 55719 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20251 /* 55722 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20252 /* 55725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20253 /* 55729 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20254 /* 55733 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20255 /* 55737 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3981:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGEhd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20256 /* 55737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhd),
20257 /* 55740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20258 /* 55742 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20259 /* 55744 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20260 /* 55746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20261 /* 55749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20262 /* 55755 */ GIR_RootConstrainSelectedInstOperands,
20263 /* 55756 */ // GIR_Coverage, 1283,
20264 /* 55756 */ GIR_EraseRootFromParent_Done,
20265 /* 55757 */ // Label 1666: @55757
20266 /* 55757 */ GIM_Reject,
20267 /* 55758 */ // Label 1662: @55758
20268 /* 55758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1667*/ GIMT_Encode4(55803), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1284 //
20269 /* 55765 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20270 /* 55768 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20271 /* 55771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20272 /* 55775 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20273 /* 55779 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20274 /* 55783 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3981:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGEhq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
20275 /* 55783 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhq),
20276 /* 55786 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20277 /* 55788 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20278 /* 55790 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20279 /* 55792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20280 /* 55795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20281 /* 55801 */ GIR_RootConstrainSelectedInstOperands,
20282 /* 55802 */ // GIR_Coverage, 1284,
20283 /* 55802 */ GIR_EraseRootFromParent_Done,
20284 /* 55803 */ // Label 1667: @55803
20285 /* 55803 */ GIM_Reject,
20286 /* 55804 */ // Label 1663: @55804
20287 /* 55804 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1668*/ GIMT_Encode4(55849), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1281 //
20288 /* 55811 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20289 /* 55814 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20290 /* 55817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20291 /* 55821 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20292 /* 55825 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20293 /* 55829 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3981:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGEfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20294 /* 55829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfd),
20295 /* 55832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20296 /* 55834 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20297 /* 55836 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20298 /* 55838 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20299 /* 55841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20300 /* 55847 */ GIR_RootConstrainSelectedInstOperands,
20301 /* 55848 */ // GIR_Coverage, 1281,
20302 /* 55848 */ GIR_EraseRootFromParent_Done,
20303 /* 55849 */ // Label 1668: @55849
20304 /* 55849 */ GIM_Reject,
20305 /* 55850 */ // Label 1664: @55850
20306 /* 55850 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1669*/ GIMT_Encode4(55895), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1282 //
20307 /* 55857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20308 /* 55860 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20309 /* 55863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20310 /* 55867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20311 /* 55871 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20312 /* 55875 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3981:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGEfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
20313 /* 55875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfq),
20314 /* 55878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20315 /* 55880 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20316 /* 55882 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20317 /* 55884 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20318 /* 55887 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20319 /* 55893 */ GIR_RootConstrainSelectedInstOperands,
20320 /* 55894 */ // GIR_Coverage, 1282,
20321 /* 55894 */ GIR_EraseRootFromParent_Done,
20322 /* 55895 */ // Label 1669: @55895
20323 /* 55895 */ GIM_Reject,
20324 /* 55896 */ // Label 1665: @55896
20325 /* 55896 */ GIM_Reject,
20326 /* 55897 */ // Label 1660: @55897
20327 /* 55897 */ GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(56119),
20328 /* 55902 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt),
20329 /* 55907 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1675*/ GIMT_Encode4(56118),
20330 /* 55918 */ /*GILLT_v4s16*//*Label 1671*/ GIMT_Encode4(55934),
20331 /* 55922 */ /*GILLT_v8s16*//*Label 1672*/ GIMT_Encode4(55980),
20332 /* 55926 */ /*GILLT_v2s32*//*Label 1673*/ GIMT_Encode4(56026),
20333 /* 55930 */ /*GILLT_v4s32*//*Label 1674*/ GIMT_Encode4(56072),
20334 /* 55934 */ // Label 1671: @55934
20335 /* 55934 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1676*/ GIMT_Encode4(55979), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1287 //
20336 /* 55941 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20337 /* 55944 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20338 /* 55947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20339 /* 55951 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20340 /* 55955 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20341 /* 55959 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3982:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGThd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20342 /* 55959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThd),
20343 /* 55962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20344 /* 55964 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20345 /* 55966 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20346 /* 55968 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20347 /* 55971 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20348 /* 55977 */ GIR_RootConstrainSelectedInstOperands,
20349 /* 55978 */ // GIR_Coverage, 1287,
20350 /* 55978 */ GIR_EraseRootFromParent_Done,
20351 /* 55979 */ // Label 1676: @55979
20352 /* 55979 */ GIM_Reject,
20353 /* 55980 */ // Label 1672: @55980
20354 /* 55980 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1677*/ GIMT_Encode4(56025), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1288 //
20355 /* 55987 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20356 /* 55990 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20357 /* 55993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20358 /* 55997 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20359 /* 56001 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20360 /* 56005 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3982:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGThq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
20361 /* 56005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThq),
20362 /* 56008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20363 /* 56010 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20364 /* 56012 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20365 /* 56014 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20366 /* 56017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20367 /* 56023 */ GIR_RootConstrainSelectedInstOperands,
20368 /* 56024 */ // GIR_Coverage, 1288,
20369 /* 56024 */ GIR_EraseRootFromParent_Done,
20370 /* 56025 */ // Label 1677: @56025
20371 /* 56025 */ GIM_Reject,
20372 /* 56026 */ // Label 1673: @56026
20373 /* 56026 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1678*/ GIMT_Encode4(56071), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1285 //
20374 /* 56033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20375 /* 56036 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20376 /* 56039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20377 /* 56043 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20378 /* 56047 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20379 /* 56051 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3982:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGTfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20380 /* 56051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfd),
20381 /* 56054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20382 /* 56056 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20383 /* 56058 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20384 /* 56060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20385 /* 56063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20386 /* 56069 */ GIR_RootConstrainSelectedInstOperands,
20387 /* 56070 */ // GIR_Coverage, 1285,
20388 /* 56070 */ GIR_EraseRootFromParent_Done,
20389 /* 56071 */ // Label 1678: @56071
20390 /* 56071 */ GIM_Reject,
20391 /* 56072 */ // Label 1674: @56072
20392 /* 56072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1679*/ GIMT_Encode4(56117), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1286 //
20393 /* 56079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20394 /* 56082 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20395 /* 56085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20396 /* 56089 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20397 /* 56093 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20398 /* 56097 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3982:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGTfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
20399 /* 56097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfq),
20400 /* 56100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20401 /* 56102 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20402 /* 56104 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20403 /* 56106 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20404 /* 56109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20405 /* 56115 */ GIR_RootConstrainSelectedInstOperands,
20406 /* 56116 */ // GIR_Coverage, 1286,
20407 /* 56116 */ GIR_EraseRootFromParent_Done,
20408 /* 56117 */ // Label 1679: @56117
20409 /* 56117 */ GIM_Reject,
20410 /* 56118 */ // Label 1675: @56118
20411 /* 56118 */ GIM_Reject,
20412 /* 56119 */ // Label 1670: @56119
20413 /* 56119 */ GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(56341),
20414 /* 56124 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
20415 /* 56129 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1685*/ GIMT_Encode4(56340),
20416 /* 56140 */ /*GILLT_v4s16*//*Label 1681*/ GIMT_Encode4(56156),
20417 /* 56144 */ /*GILLT_v8s16*//*Label 1682*/ GIMT_Encode4(56202),
20418 /* 56148 */ /*GILLT_v2s32*//*Label 1683*/ GIMT_Encode4(56248),
20419 /* 56152 */ /*GILLT_v4s32*//*Label 1684*/ GIMT_Encode4(56294),
20420 /* 56156 */ // Label 1681: @56156
20421 /* 56156 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1686*/ GIMT_Encode4(56201), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1333 //
20422 /* 56163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20423 /* 56166 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20424 /* 56169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20425 /* 56173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20426 /* 56177 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20427 /* 56181 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3978:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VABDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20428 /* 56181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhd),
20429 /* 56184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20430 /* 56186 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20431 /* 56188 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20432 /* 56190 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20433 /* 56193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20434 /* 56199 */ GIR_RootConstrainSelectedInstOperands,
20435 /* 56200 */ // GIR_Coverage, 1333,
20436 /* 56200 */ GIR_EraseRootFromParent_Done,
20437 /* 56201 */ // Label 1686: @56201
20438 /* 56201 */ GIM_Reject,
20439 /* 56202 */ // Label 1682: @56202
20440 /* 56202 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1687*/ GIMT_Encode4(56247), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1334 //
20441 /* 56209 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20442 /* 56212 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20443 /* 56215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20444 /* 56219 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20445 /* 56223 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20446 /* 56227 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3978:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VABDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
20447 /* 56227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhq),
20448 /* 56230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20449 /* 56232 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20450 /* 56234 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20451 /* 56236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20452 /* 56239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20453 /* 56245 */ GIR_RootConstrainSelectedInstOperands,
20454 /* 56246 */ // GIR_Coverage, 1334,
20455 /* 56246 */ GIR_EraseRootFromParent_Done,
20456 /* 56247 */ // Label 1687: @56247
20457 /* 56247 */ GIM_Reject,
20458 /* 56248 */ // Label 1683: @56248
20459 /* 56248 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1688*/ GIMT_Encode4(56293), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1331 //
20460 /* 56255 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20461 /* 56258 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20462 /* 56261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20463 /* 56265 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20464 /* 56269 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20465 /* 56273 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3978:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VABDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20466 /* 56273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfd),
20467 /* 56276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20468 /* 56278 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20469 /* 56280 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20470 /* 56282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20471 /* 56285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20472 /* 56291 */ GIR_RootConstrainSelectedInstOperands,
20473 /* 56292 */ // GIR_Coverage, 1331,
20474 /* 56292 */ GIR_EraseRootFromParent_Done,
20475 /* 56293 */ // Label 1688: @56293
20476 /* 56293 */ GIM_Reject,
20477 /* 56294 */ // Label 1684: @56294
20478 /* 56294 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1689*/ GIMT_Encode4(56339), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1332 //
20479 /* 56301 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20480 /* 56304 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20481 /* 56307 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20482 /* 56311 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20483 /* 56315 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20484 /* 56319 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3978:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VABDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
20485 /* 56319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfq),
20486 /* 56322 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20487 /* 56324 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20488 /* 56326 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20489 /* 56328 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20490 /* 56331 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20491 /* 56337 */ GIR_RootConstrainSelectedInstOperands,
20492 /* 56338 */ // GIR_Coverage, 1332,
20493 /* 56338 */ GIR_EraseRootFromParent_Done,
20494 /* 56339 */ // Label 1689: @56339
20495 /* 56339 */ GIM_Reject,
20496 /* 56340 */ // Label 1685: @56340
20497 /* 56340 */ GIM_Reject,
20498 /* 56341 */ // Label 1680: @56341
20499 /* 56341 */ GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(56587),
20500 /* 56346 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
20501 /* 56351 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1694*/ GIMT_Encode4(56586),
20502 /* 56362 */ /*GILLT_v8s8*//*Label 1691*/ GIMT_Encode4(56382), GIMT_Encode4(0),
20503 /* 56370 */ /*GILLT_v4s16*//*Label 1692*/ GIMT_Encode4(56428), GIMT_Encode4(0),
20504 /* 56378 */ /*GILLT_v2s32*//*Label 1693*/ GIMT_Encode4(56507),
20505 /* 56382 */ // Label 1691: @56382
20506 /* 56382 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1695*/ GIMT_Encode4(56427), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1399 //
20507 /* 56389 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20508 /* 56392 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20509 /* 56395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20510 /* 56399 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20511 /* 56403 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20512 /* 56407 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4032:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPADDi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20513 /* 56407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi8),
20514 /* 56410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20515 /* 56412 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20516 /* 56414 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20517 /* 56416 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20518 /* 56419 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20519 /* 56425 */ GIR_RootConstrainSelectedInstOperands,
20520 /* 56426 */ // GIR_Coverage, 1399,
20521 /* 56426 */ GIR_EraseRootFromParent_Done,
20522 /* 56427 */ // Label 1695: @56427
20523 /* 56427 */ GIM_Reject,
20524 /* 56428 */ // Label 1692: @56428
20525 /* 56428 */ GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(56506),
20526 /* 56433 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20527 /* 56436 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20528 /* 56439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20529 /* 56443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20530 /* 56447 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20531 /* 56451 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1697*/ GIMT_Encode4(56478), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1400 //
20532 /* 56458 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4032:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPADDi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20533 /* 56458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi16),
20534 /* 56461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20535 /* 56463 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20536 /* 56465 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20537 /* 56467 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20538 /* 56470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20539 /* 56476 */ GIR_RootConstrainSelectedInstOperands,
20540 /* 56477 */ // GIR_Coverage, 1400,
20541 /* 56477 */ GIR_EraseRootFromParent_Done,
20542 /* 56478 */ // Label 1697: @56478
20543 /* 56478 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1698*/ GIMT_Encode4(56505), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1403 //
20544 /* 56485 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4032:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPADDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20545 /* 56485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDh),
20546 /* 56488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20547 /* 56490 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20548 /* 56492 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20549 /* 56494 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20550 /* 56497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20551 /* 56503 */ GIR_RootConstrainSelectedInstOperands,
20552 /* 56504 */ // GIR_Coverage, 1403,
20553 /* 56504 */ GIR_EraseRootFromParent_Done,
20554 /* 56505 */ // Label 1698: @56505
20555 /* 56505 */ GIM_Reject,
20556 /* 56506 */ // Label 1696: @56506
20557 /* 56506 */ GIM_Reject,
20558 /* 56507 */ // Label 1693: @56507
20559 /* 56507 */ GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(56585),
20560 /* 56512 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20561 /* 56515 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20562 /* 56518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20563 /* 56522 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20564 /* 56526 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20565 /* 56530 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1700*/ GIMT_Encode4(56557), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1401 //
20566 /* 56537 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4032:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPADDi32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20567 /* 56537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi32),
20568 /* 56540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20569 /* 56542 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20570 /* 56544 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20571 /* 56546 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20572 /* 56549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20573 /* 56555 */ GIR_RootConstrainSelectedInstOperands,
20574 /* 56556 */ // GIR_Coverage, 1401,
20575 /* 56556 */ GIR_EraseRootFromParent_Done,
20576 /* 56557 */ // Label 1700: @56557
20577 /* 56557 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1701*/ GIMT_Encode4(56584), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1402 //
20578 /* 56564 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4032:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPADDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
20579 /* 56564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDf),
20580 /* 56567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20581 /* 56569 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20582 /* 56571 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20583 /* 56573 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20584 /* 56576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20585 /* 56582 */ GIR_RootConstrainSelectedInstOperands,
20586 /* 56583 */ // GIR_Coverage, 1402,
20587 /* 56583 */ GIR_EraseRootFromParent_Done,
20588 /* 56584 */ // Label 1701: @56584
20589 /* 56584 */ GIM_Reject,
20590 /* 56585 */ // Label 1699: @56585
20591 /* 56585 */ GIM_Reject,
20592 /* 56586 */ // Label 1694: @56586
20593 /* 56586 */ GIM_Reject,
20594 /* 56587 */ // Label 1690: @56587
20595 /* 56587 */ GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(56933),
20596 /* 56592 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
20597 /* 56597 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1709*/ GIMT_Encode4(56932),
20598 /* 56608 */ /*GILLT_s64*//*Label 1703*/ GIMT_Encode4(56656), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
20599 /* 56636 */ /*GILLT_v4s16*//*Label 1704*/ GIMT_Encode4(56702),
20600 /* 56640 */ /*GILLT_v8s16*//*Label 1705*/ GIMT_Encode4(56748),
20601 /* 56644 */ /*GILLT_v2s32*//*Label 1706*/ GIMT_Encode4(56794),
20602 /* 56648 */ /*GILLT_v4s32*//*Label 1707*/ GIMT_Encode4(56840),
20603 /* 56652 */ /*GILLT_v2s64*//*Label 1708*/ GIMT_Encode4(56886),
20604 /* 56656 */ // Label 1703: @56656
20605 /* 56656 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1710*/ GIMT_Encode4(56701), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1418 //
20606 /* 56663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20607 /* 56666 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20608 /* 56669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20609 /* 56673 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20610 /* 56677 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20611 /* 56681 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4030:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALsv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
20612 /* 56681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv2i32),
20613 /* 56684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20614 /* 56686 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20615 /* 56688 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20616 /* 56690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20617 /* 56693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20618 /* 56699 */ GIR_RootConstrainSelectedInstOperands,
20619 /* 56700 */ // GIR_Coverage, 1418,
20620 /* 56700 */ GIR_EraseRootFromParent_Done,
20621 /* 56701 */ // Label 1710: @56701
20622 /* 56701 */ GIM_Reject,
20623 /* 56702 */ // Label 1704: @56702
20624 /* 56702 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1711*/ GIMT_Encode4(56747), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1416 //
20625 /* 56709 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20626 /* 56712 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20627 /* 56715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20628 /* 56719 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20629 /* 56723 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20630 /* 56727 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4030:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALsv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
20631 /* 56727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i8),
20632 /* 56730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20633 /* 56732 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20634 /* 56734 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20635 /* 56736 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20636 /* 56739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20637 /* 56745 */ GIR_RootConstrainSelectedInstOperands,
20638 /* 56746 */ // GIR_Coverage, 1416,
20639 /* 56746 */ GIR_EraseRootFromParent_Done,
20640 /* 56747 */ // Label 1711: @56747
20641 /* 56747 */ GIM_Reject,
20642 /* 56748 */ // Label 1705: @56748
20643 /* 56748 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1712*/ GIMT_Encode4(56793), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1419 //
20644 /* 56755 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20645 /* 56758 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20646 /* 56761 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20647 /* 56765 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20648 /* 56769 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20649 /* 56773 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4030:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALsv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
20650 /* 56773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv16i8),
20651 /* 56776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20652 /* 56778 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20653 /* 56780 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20654 /* 56782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20655 /* 56785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20656 /* 56791 */ GIR_RootConstrainSelectedInstOperands,
20657 /* 56792 */ // GIR_Coverage, 1419,
20658 /* 56792 */ GIR_EraseRootFromParent_Done,
20659 /* 56793 */ // Label 1712: @56793
20660 /* 56793 */ GIM_Reject,
20661 /* 56794 */ // Label 1706: @56794
20662 /* 56794 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1713*/ GIMT_Encode4(56839), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1417 //
20663 /* 56801 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20664 /* 56804 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20665 /* 56807 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20666 /* 56811 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20667 /* 56815 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20668 /* 56819 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4030:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALsv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
20669 /* 56819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i16),
20670 /* 56822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20671 /* 56824 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20672 /* 56826 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20673 /* 56828 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20674 /* 56831 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20675 /* 56837 */ GIR_RootConstrainSelectedInstOperands,
20676 /* 56838 */ // GIR_Coverage, 1417,
20677 /* 56838 */ GIR_EraseRootFromParent_Done,
20678 /* 56839 */ // Label 1713: @56839
20679 /* 56839 */ GIM_Reject,
20680 /* 56840 */ // Label 1707: @56840
20681 /* 56840 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1714*/ GIMT_Encode4(56885), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1420 //
20682 /* 56847 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20683 /* 56850 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20684 /* 56853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20685 /* 56857 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20686 /* 56861 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20687 /* 56865 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4030:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALsv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
20688 /* 56865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i16),
20689 /* 56868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20690 /* 56870 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20691 /* 56872 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20692 /* 56874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20693 /* 56877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20694 /* 56883 */ GIR_RootConstrainSelectedInstOperands,
20695 /* 56884 */ // GIR_Coverage, 1420,
20696 /* 56884 */ GIR_EraseRootFromParent_Done,
20697 /* 56885 */ // Label 1714: @56885
20698 /* 56885 */ GIM_Reject,
20699 /* 56886 */ // Label 1708: @56886
20700 /* 56886 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1715*/ GIMT_Encode4(56931), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1421 //
20701 /* 56893 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20702 /* 56896 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20703 /* 56899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20704 /* 56903 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20705 /* 56907 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20706 /* 56911 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4030:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALsv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
20707 /* 56911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i32),
20708 /* 56914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20709 /* 56916 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20710 /* 56918 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20711 /* 56920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20712 /* 56923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20713 /* 56929 */ GIR_RootConstrainSelectedInstOperands,
20714 /* 56930 */ // GIR_Coverage, 1421,
20715 /* 56930 */ GIR_EraseRootFromParent_Done,
20716 /* 56931 */ // Label 1715: @56931
20717 /* 56931 */ GIM_Reject,
20718 /* 56932 */ // Label 1709: @56932
20719 /* 56932 */ GIM_Reject,
20720 /* 56933 */ // Label 1702: @56933
20721 /* 56933 */ GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(57279),
20722 /* 56938 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
20723 /* 56943 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1723*/ GIMT_Encode4(57278),
20724 /* 56954 */ /*GILLT_s64*//*Label 1717*/ GIMT_Encode4(57002), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
20725 /* 56982 */ /*GILLT_v4s16*//*Label 1718*/ GIMT_Encode4(57048),
20726 /* 56986 */ /*GILLT_v8s16*//*Label 1719*/ GIMT_Encode4(57094),
20727 /* 56990 */ /*GILLT_v2s32*//*Label 1720*/ GIMT_Encode4(57140),
20728 /* 56994 */ /*GILLT_v4s32*//*Label 1721*/ GIMT_Encode4(57186),
20729 /* 56998 */ /*GILLT_v2s64*//*Label 1722*/ GIMT_Encode4(57232),
20730 /* 57002 */ // Label 1717: @57002
20731 /* 57002 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1724*/ GIMT_Encode4(57047), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1424 //
20732 /* 57009 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20733 /* 57012 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20734 /* 57015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20735 /* 57019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20736 /* 57023 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20737 /* 57027 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4031:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALuv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
20738 /* 57027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv2i32),
20739 /* 57030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20740 /* 57032 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20741 /* 57034 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20742 /* 57036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20743 /* 57039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20744 /* 57045 */ GIR_RootConstrainSelectedInstOperands,
20745 /* 57046 */ // GIR_Coverage, 1424,
20746 /* 57046 */ GIR_EraseRootFromParent_Done,
20747 /* 57047 */ // Label 1724: @57047
20748 /* 57047 */ GIM_Reject,
20749 /* 57048 */ // Label 1718: @57048
20750 /* 57048 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1725*/ GIMT_Encode4(57093), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1422 //
20751 /* 57055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20752 /* 57058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20753 /* 57061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20754 /* 57065 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20755 /* 57069 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20756 /* 57073 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4031:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALuv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
20757 /* 57073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i8),
20758 /* 57076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20759 /* 57078 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20760 /* 57080 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20761 /* 57082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20762 /* 57085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20763 /* 57091 */ GIR_RootConstrainSelectedInstOperands,
20764 /* 57092 */ // GIR_Coverage, 1422,
20765 /* 57092 */ GIR_EraseRootFromParent_Done,
20766 /* 57093 */ // Label 1725: @57093
20767 /* 57093 */ GIM_Reject,
20768 /* 57094 */ // Label 1719: @57094
20769 /* 57094 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1726*/ GIMT_Encode4(57139), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1425 //
20770 /* 57101 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20771 /* 57104 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20772 /* 57107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20773 /* 57111 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20774 /* 57115 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20775 /* 57119 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4031:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALuv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
20776 /* 57119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv16i8),
20777 /* 57122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20778 /* 57124 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20779 /* 57126 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20780 /* 57128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20781 /* 57131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20782 /* 57137 */ GIR_RootConstrainSelectedInstOperands,
20783 /* 57138 */ // GIR_Coverage, 1425,
20784 /* 57138 */ GIR_EraseRootFromParent_Done,
20785 /* 57139 */ // Label 1726: @57139
20786 /* 57139 */ GIM_Reject,
20787 /* 57140 */ // Label 1720: @57140
20788 /* 57140 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1727*/ GIMT_Encode4(57185), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1423 //
20789 /* 57147 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20790 /* 57150 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20791 /* 57153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20792 /* 57157 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20793 /* 57161 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20794 /* 57165 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4031:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALuv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
20795 /* 57165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i16),
20796 /* 57168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20797 /* 57170 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20798 /* 57172 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20799 /* 57174 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20800 /* 57177 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20801 /* 57183 */ GIR_RootConstrainSelectedInstOperands,
20802 /* 57184 */ // GIR_Coverage, 1423,
20803 /* 57184 */ GIR_EraseRootFromParent_Done,
20804 /* 57185 */ // Label 1727: @57185
20805 /* 57185 */ GIM_Reject,
20806 /* 57186 */ // Label 1721: @57186
20807 /* 57186 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1728*/ GIMT_Encode4(57231), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1426 //
20808 /* 57193 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20809 /* 57196 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20810 /* 57199 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20811 /* 57203 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20812 /* 57207 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20813 /* 57211 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4031:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALuv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
20814 /* 57211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i16),
20815 /* 57214 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20816 /* 57216 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20817 /* 57218 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20818 /* 57220 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20819 /* 57223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20820 /* 57229 */ GIR_RootConstrainSelectedInstOperands,
20821 /* 57230 */ // GIR_Coverage, 1426,
20822 /* 57230 */ GIR_EraseRootFromParent_Done,
20823 /* 57231 */ // Label 1728: @57231
20824 /* 57231 */ GIM_Reject,
20825 /* 57232 */ // Label 1722: @57232
20826 /* 57232 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1729*/ GIMT_Encode4(57277), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1427 //
20827 /* 57239 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20828 /* 57242 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20829 /* 57245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20830 /* 57249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20831 /* 57253 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20832 /* 57257 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4031:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALuv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
20833 /* 57257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i32),
20834 /* 57260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20835 /* 57262 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
20836 /* 57264 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20837 /* 57266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20838 /* 57269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20839 /* 57275 */ GIR_RootConstrainSelectedInstOperands,
20840 /* 57276 */ // GIR_Coverage, 1427,
20841 /* 57276 */ GIR_EraseRootFromParent_Done,
20842 /* 57277 */ // Label 1729: @57277
20843 /* 57277 */ GIM_Reject,
20844 /* 57278 */ // Label 1723: @57278
20845 /* 57278 */ GIM_Reject,
20846 /* 57279 */ // Label 1716: @57279
20847 /* 57279 */ GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(57459),
20848 /* 57284 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
20849 /* 57289 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1734*/ GIMT_Encode4(57458),
20850 /* 57300 */ /*GILLT_v8s8*//*Label 1731*/ GIMT_Encode4(57320), GIMT_Encode4(0),
20851 /* 57308 */ /*GILLT_v4s16*//*Label 1732*/ GIMT_Encode4(57366), GIMT_Encode4(0),
20852 /* 57316 */ /*GILLT_v2s32*//*Label 1733*/ GIMT_Encode4(57412),
20853 /* 57320 */ // Label 1731: @57320
20854 /* 57320 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1735*/ GIMT_Encode4(57365), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1428 //
20855 /* 57327 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20856 /* 57330 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20857 /* 57333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20858 /* 57337 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20859 /* 57341 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20860 /* 57345 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4035:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20861 /* 57345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs8),
20862 /* 57348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20863 /* 57350 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20864 /* 57352 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20865 /* 57354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20866 /* 57357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20867 /* 57363 */ GIR_RootConstrainSelectedInstOperands,
20868 /* 57364 */ // GIR_Coverage, 1428,
20869 /* 57364 */ GIR_EraseRootFromParent_Done,
20870 /* 57365 */ // Label 1735: @57365
20871 /* 57365 */ GIM_Reject,
20872 /* 57366 */ // Label 1732: @57366
20873 /* 57366 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1736*/ GIMT_Encode4(57411), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1429 //
20874 /* 57373 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20875 /* 57376 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20876 /* 57379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20877 /* 57383 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20878 /* 57387 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20879 /* 57391 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4035:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20880 /* 57391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs16),
20881 /* 57394 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20882 /* 57396 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20883 /* 57398 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20884 /* 57400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20885 /* 57403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20886 /* 57409 */ GIR_RootConstrainSelectedInstOperands,
20887 /* 57410 */ // GIR_Coverage, 1429,
20888 /* 57410 */ GIR_EraseRootFromParent_Done,
20889 /* 57411 */ // Label 1736: @57411
20890 /* 57411 */ GIM_Reject,
20891 /* 57412 */ // Label 1733: @57412
20892 /* 57412 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1737*/ GIMT_Encode4(57457), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1430 //
20893 /* 57419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20894 /* 57422 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20895 /* 57425 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20896 /* 57429 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20897 /* 57433 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20898 /* 57437 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4035:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20899 /* 57437 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs32),
20900 /* 57440 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20901 /* 57442 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20902 /* 57444 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20903 /* 57446 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20904 /* 57449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20905 /* 57455 */ GIR_RootConstrainSelectedInstOperands,
20906 /* 57456 */ // GIR_Coverage, 1430,
20907 /* 57456 */ GIR_EraseRootFromParent_Done,
20908 /* 57457 */ // Label 1737: @57457
20909 /* 57457 */ GIM_Reject,
20910 /* 57458 */ // Label 1734: @57458
20911 /* 57458 */ GIM_Reject,
20912 /* 57459 */ // Label 1730: @57459
20913 /* 57459 */ GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(57639),
20914 /* 57464 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu),
20915 /* 57469 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1742*/ GIMT_Encode4(57638),
20916 /* 57480 */ /*GILLT_v8s8*//*Label 1739*/ GIMT_Encode4(57500), GIMT_Encode4(0),
20917 /* 57488 */ /*GILLT_v4s16*//*Label 1740*/ GIMT_Encode4(57546), GIMT_Encode4(0),
20918 /* 57496 */ /*GILLT_v2s32*//*Label 1741*/ GIMT_Encode4(57592),
20919 /* 57500 */ // Label 1739: @57500
20920 /* 57500 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1743*/ GIMT_Encode4(57545), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1431 //
20921 /* 57507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20922 /* 57510 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20923 /* 57513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20924 /* 57517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20925 /* 57521 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20926 /* 57525 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4036:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20927 /* 57525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu8),
20928 /* 57528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20929 /* 57530 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20930 /* 57532 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20931 /* 57534 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20932 /* 57537 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20933 /* 57543 */ GIR_RootConstrainSelectedInstOperands,
20934 /* 57544 */ // GIR_Coverage, 1431,
20935 /* 57544 */ GIR_EraseRootFromParent_Done,
20936 /* 57545 */ // Label 1743: @57545
20937 /* 57545 */ GIM_Reject,
20938 /* 57546 */ // Label 1740: @57546
20939 /* 57546 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1744*/ GIMT_Encode4(57591), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1432 //
20940 /* 57553 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20941 /* 57556 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20942 /* 57559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20943 /* 57563 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20944 /* 57567 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20945 /* 57571 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4036:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20946 /* 57571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu16),
20947 /* 57574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20948 /* 57576 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20949 /* 57578 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20950 /* 57580 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20951 /* 57583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20952 /* 57589 */ GIR_RootConstrainSelectedInstOperands,
20953 /* 57590 */ // GIR_Coverage, 1432,
20954 /* 57590 */ GIR_EraseRootFromParent_Done,
20955 /* 57591 */ // Label 1744: @57591
20956 /* 57591 */ GIM_Reject,
20957 /* 57592 */ // Label 1741: @57592
20958 /* 57592 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1745*/ GIMT_Encode4(57637), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1433 //
20959 /* 57599 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20960 /* 57602 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20961 /* 57605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20962 /* 57609 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20963 /* 57613 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20964 /* 57617 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4036:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20965 /* 57617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu32),
20966 /* 57620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20967 /* 57622 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20968 /* 57624 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20969 /* 57626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20970 /* 57629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20971 /* 57635 */ GIR_RootConstrainSelectedInstOperands,
20972 /* 57636 */ // GIR_Coverage, 1433,
20973 /* 57636 */ GIR_EraseRootFromParent_Done,
20974 /* 57637 */ // Label 1745: @57637
20975 /* 57637 */ GIM_Reject,
20976 /* 57638 */ // Label 1742: @57638
20977 /* 57638 */ GIM_Reject,
20978 /* 57639 */ // Label 1738: @57639
20979 /* 57639 */ GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(57765),
20980 /* 57644 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
20981 /* 57649 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 1749*/ GIMT_Encode4(57764),
20982 /* 57660 */ /*GILLT_v4s16*//*Label 1747*/ GIMT_Encode4(57672), GIMT_Encode4(0),
20983 /* 57668 */ /*GILLT_v2s32*//*Label 1748*/ GIMT_Encode4(57718),
20984 /* 57672 */ // Label 1747: @57672
20985 /* 57672 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1750*/ GIMT_Encode4(57717), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1435 //
20986 /* 57679 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20987 /* 57682 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20988 /* 57685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20989 /* 57689 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20990 /* 57693 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20991 /* 57697 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4035:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMAXh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
20992 /* 57697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXh),
20993 /* 57700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20994 /* 57702 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20995 /* 57704 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20996 /* 57706 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20997 /* 57709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20998 /* 57715 */ GIR_RootConstrainSelectedInstOperands,
20999 /* 57716 */ // GIR_Coverage, 1435,
21000 /* 57716 */ GIR_EraseRootFromParent_Done,
21001 /* 57717 */ // Label 1750: @57717
21002 /* 57717 */ GIM_Reject,
21003 /* 57718 */ // Label 1748: @57718
21004 /* 57718 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1751*/ GIMT_Encode4(57763), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1434 //
21005 /* 57725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21006 /* 57728 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21007 /* 57731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21008 /* 57735 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21009 /* 57739 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21010 /* 57743 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4035:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMAXf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21011 /* 57743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXf),
21012 /* 57746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21013 /* 57748 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21014 /* 57750 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21015 /* 57752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21016 /* 57755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21017 /* 57761 */ GIR_RootConstrainSelectedInstOperands,
21018 /* 57762 */ // GIR_Coverage, 1434,
21019 /* 57762 */ GIR_EraseRootFromParent_Done,
21020 /* 57763 */ // Label 1751: @57763
21021 /* 57763 */ GIM_Reject,
21022 /* 57764 */ // Label 1749: @57764
21023 /* 57764 */ GIM_Reject,
21024 /* 57765 */ // Label 1746: @57765
21025 /* 57765 */ GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(57945),
21026 /* 57770 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
21027 /* 57775 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1756*/ GIMT_Encode4(57944),
21028 /* 57786 */ /*GILLT_v8s8*//*Label 1753*/ GIMT_Encode4(57806), GIMT_Encode4(0),
21029 /* 57794 */ /*GILLT_v4s16*//*Label 1754*/ GIMT_Encode4(57852), GIMT_Encode4(0),
21030 /* 57802 */ /*GILLT_v2s32*//*Label 1755*/ GIMT_Encode4(57898),
21031 /* 57806 */ // Label 1753: @57806
21032 /* 57806 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1757*/ GIMT_Encode4(57851), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1436 //
21033 /* 57813 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21034 /* 57816 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21035 /* 57819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21036 /* 57823 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21037 /* 57827 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21038 /* 57831 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4037:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21039 /* 57831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs8),
21040 /* 57834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21041 /* 57836 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21042 /* 57838 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21043 /* 57840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21044 /* 57843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21045 /* 57849 */ GIR_RootConstrainSelectedInstOperands,
21046 /* 57850 */ // GIR_Coverage, 1436,
21047 /* 57850 */ GIR_EraseRootFromParent_Done,
21048 /* 57851 */ // Label 1757: @57851
21049 /* 57851 */ GIM_Reject,
21050 /* 57852 */ // Label 1754: @57852
21051 /* 57852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1758*/ GIMT_Encode4(57897), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1437 //
21052 /* 57859 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21053 /* 57862 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21054 /* 57865 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21055 /* 57869 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21056 /* 57873 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21057 /* 57877 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4037:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21058 /* 57877 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs16),
21059 /* 57880 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21060 /* 57882 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21061 /* 57884 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21062 /* 57886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21063 /* 57889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21064 /* 57895 */ GIR_RootConstrainSelectedInstOperands,
21065 /* 57896 */ // GIR_Coverage, 1437,
21066 /* 57896 */ GIR_EraseRootFromParent_Done,
21067 /* 57897 */ // Label 1758: @57897
21068 /* 57897 */ GIM_Reject,
21069 /* 57898 */ // Label 1755: @57898
21070 /* 57898 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1759*/ GIMT_Encode4(57943), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1438 //
21071 /* 57905 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21072 /* 57908 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21073 /* 57911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21074 /* 57915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21075 /* 57919 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21076 /* 57923 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4037:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21077 /* 57923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs32),
21078 /* 57926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21079 /* 57928 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21080 /* 57930 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21081 /* 57932 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21082 /* 57935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21083 /* 57941 */ GIR_RootConstrainSelectedInstOperands,
21084 /* 57942 */ // GIR_Coverage, 1438,
21085 /* 57942 */ GIR_EraseRootFromParent_Done,
21086 /* 57943 */ // Label 1759: @57943
21087 /* 57943 */ GIM_Reject,
21088 /* 57944 */ // Label 1756: @57944
21089 /* 57944 */ GIM_Reject,
21090 /* 57945 */ // Label 1752: @57945
21091 /* 57945 */ GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(58125),
21092 /* 57950 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu),
21093 /* 57955 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 1764*/ GIMT_Encode4(58124),
21094 /* 57966 */ /*GILLT_v8s8*//*Label 1761*/ GIMT_Encode4(57986), GIMT_Encode4(0),
21095 /* 57974 */ /*GILLT_v4s16*//*Label 1762*/ GIMT_Encode4(58032), GIMT_Encode4(0),
21096 /* 57982 */ /*GILLT_v2s32*//*Label 1763*/ GIMT_Encode4(58078),
21097 /* 57986 */ // Label 1761: @57986
21098 /* 57986 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1765*/ GIMT_Encode4(58031), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1439 //
21099 /* 57993 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21100 /* 57996 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21101 /* 57999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21102 /* 58003 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21103 /* 58007 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21104 /* 58011 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4038:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21105 /* 58011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu8),
21106 /* 58014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21107 /* 58016 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21108 /* 58018 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21109 /* 58020 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21110 /* 58023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21111 /* 58029 */ GIR_RootConstrainSelectedInstOperands,
21112 /* 58030 */ // GIR_Coverage, 1439,
21113 /* 58030 */ GIR_EraseRootFromParent_Done,
21114 /* 58031 */ // Label 1765: @58031
21115 /* 58031 */ GIM_Reject,
21116 /* 58032 */ // Label 1762: @58032
21117 /* 58032 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1766*/ GIMT_Encode4(58077), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1440 //
21118 /* 58039 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21119 /* 58042 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21120 /* 58045 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21121 /* 58049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21122 /* 58053 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21123 /* 58057 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4038:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21124 /* 58057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu16),
21125 /* 58060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21126 /* 58062 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21127 /* 58064 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21128 /* 58066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21129 /* 58069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21130 /* 58075 */ GIR_RootConstrainSelectedInstOperands,
21131 /* 58076 */ // GIR_Coverage, 1440,
21132 /* 58076 */ GIR_EraseRootFromParent_Done,
21133 /* 58077 */ // Label 1766: @58077
21134 /* 58077 */ GIM_Reject,
21135 /* 58078 */ // Label 1763: @58078
21136 /* 58078 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1767*/ GIMT_Encode4(58123), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1441 //
21137 /* 58085 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21138 /* 58088 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21139 /* 58091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21140 /* 58095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21141 /* 58099 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21142 /* 58103 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4038:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21143 /* 58103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu32),
21144 /* 58106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21145 /* 58108 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21146 /* 58110 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21147 /* 58112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21148 /* 58115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21149 /* 58121 */ GIR_RootConstrainSelectedInstOperands,
21150 /* 58122 */ // GIR_Coverage, 1441,
21151 /* 58122 */ GIR_EraseRootFromParent_Done,
21152 /* 58123 */ // Label 1767: @58123
21153 /* 58123 */ GIM_Reject,
21154 /* 58124 */ // Label 1764: @58124
21155 /* 58124 */ GIM_Reject,
21156 /* 58125 */ // Label 1760: @58125
21157 /* 58125 */ GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(58251),
21158 /* 58130 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
21159 /* 58135 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 1771*/ GIMT_Encode4(58250),
21160 /* 58146 */ /*GILLT_v4s16*//*Label 1769*/ GIMT_Encode4(58158), GIMT_Encode4(0),
21161 /* 58154 */ /*GILLT_v2s32*//*Label 1770*/ GIMT_Encode4(58204),
21162 /* 58158 */ // Label 1769: @58158
21163 /* 58158 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1772*/ GIMT_Encode4(58203), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1443 //
21164 /* 58165 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21165 /* 58168 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21166 /* 58171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21167 /* 58175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21168 /* 58179 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21169 /* 58183 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4037:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMINh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21170 /* 58183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINh),
21171 /* 58186 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21172 /* 58188 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21173 /* 58190 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21174 /* 58192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21175 /* 58195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21176 /* 58201 */ GIR_RootConstrainSelectedInstOperands,
21177 /* 58202 */ // GIR_Coverage, 1443,
21178 /* 58202 */ GIR_EraseRootFromParent_Done,
21179 /* 58203 */ // Label 1772: @58203
21180 /* 58203 */ GIM_Reject,
21181 /* 58204 */ // Label 1770: @58204
21182 /* 58204 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1773*/ GIMT_Encode4(58249), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1442 //
21183 /* 58211 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21184 /* 58214 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21185 /* 58217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21186 /* 58221 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21187 /* 58225 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21188 /* 58229 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4037:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMINf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21189 /* 58229 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINf),
21190 /* 58232 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21191 /* 58234 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21192 /* 58236 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21193 /* 58238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21194 /* 58241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21195 /* 58247 */ GIR_RootConstrainSelectedInstOperands,
21196 /* 58248 */ // GIR_Coverage, 1442,
21197 /* 58248 */ GIR_EraseRootFromParent_Done,
21198 /* 58249 */ // Label 1773: @58249
21199 /* 58249 */ GIM_Reject,
21200 /* 58250 */ // Label 1771: @58250
21201 /* 58250 */ GIM_Reject,
21202 /* 58251 */ // Label 1768: @58251
21203 /* 58251 */ GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(58473),
21204 /* 58256 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps),
21205 /* 58261 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1779*/ GIMT_Encode4(58472),
21206 /* 58272 */ /*GILLT_v4s16*//*Label 1775*/ GIMT_Encode4(58288),
21207 /* 58276 */ /*GILLT_v8s16*//*Label 1776*/ GIMT_Encode4(58334),
21208 /* 58280 */ /*GILLT_v2s32*//*Label 1777*/ GIMT_Encode4(58380),
21209 /* 58284 */ /*GILLT_v4s32*//*Label 1778*/ GIMT_Encode4(58426),
21210 /* 58288 */ // Label 1775: @58288
21211 /* 58288 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1780*/ GIMT_Encode4(58333), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1452 //
21212 /* 58295 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21213 /* 58298 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21214 /* 58301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21215 /* 58305 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21216 /* 58309 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21217 /* 58313 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4062:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRECPShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21218 /* 58313 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShd),
21219 /* 58316 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21220 /* 58318 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21221 /* 58320 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21222 /* 58322 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21223 /* 58325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21224 /* 58331 */ GIR_RootConstrainSelectedInstOperands,
21225 /* 58332 */ // GIR_Coverage, 1452,
21226 /* 58332 */ GIR_EraseRootFromParent_Done,
21227 /* 58333 */ // Label 1780: @58333
21228 /* 58333 */ GIM_Reject,
21229 /* 58334 */ // Label 1776: @58334
21230 /* 58334 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1781*/ GIMT_Encode4(58379), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1453 //
21231 /* 58341 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21232 /* 58344 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21233 /* 58347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21234 /* 58351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21235 /* 58355 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21236 /* 58359 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4062:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRECPShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21237 /* 58359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShq),
21238 /* 58362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21239 /* 58364 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21240 /* 58366 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21241 /* 58368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21242 /* 58371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21243 /* 58377 */ GIR_RootConstrainSelectedInstOperands,
21244 /* 58378 */ // GIR_Coverage, 1453,
21245 /* 58378 */ GIR_EraseRootFromParent_Done,
21246 /* 58379 */ // Label 1781: @58379
21247 /* 58379 */ GIM_Reject,
21248 /* 58380 */ // Label 1777: @58380
21249 /* 58380 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1782*/ GIMT_Encode4(58425), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1450 //
21250 /* 58387 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21251 /* 58390 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21252 /* 58393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21253 /* 58397 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21254 /* 58401 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21255 /* 58405 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4062:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRECPSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21256 /* 58405 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfd),
21257 /* 58408 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21258 /* 58410 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21259 /* 58412 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21260 /* 58414 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21261 /* 58417 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21262 /* 58423 */ GIR_RootConstrainSelectedInstOperands,
21263 /* 58424 */ // GIR_Coverage, 1450,
21264 /* 58424 */ GIR_EraseRootFromParent_Done,
21265 /* 58425 */ // Label 1782: @58425
21266 /* 58425 */ GIM_Reject,
21267 /* 58426 */ // Label 1778: @58426
21268 /* 58426 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1783*/ GIMT_Encode4(58471), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1451 //
21269 /* 58433 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21270 /* 58436 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21271 /* 58439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21272 /* 58443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21273 /* 58447 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21274 /* 58451 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4062:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRECPSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21275 /* 58451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfq),
21276 /* 58454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21277 /* 58456 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21278 /* 58458 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21279 /* 58460 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21280 /* 58463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21281 /* 58469 */ GIR_RootConstrainSelectedInstOperands,
21282 /* 58470 */ // GIR_Coverage, 1451,
21283 /* 58470 */ GIR_EraseRootFromParent_Done,
21284 /* 58471 */ // Label 1783: @58471
21285 /* 58471 */ GIM_Reject,
21286 /* 58472 */ // Label 1779: @58472
21287 /* 58472 */ GIM_Reject,
21288 /* 58473 */ // Label 1774: @58473
21289 /* 58473 */ GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(58695),
21290 /* 58478 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts),
21291 /* 58483 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 1789*/ GIMT_Encode4(58694),
21292 /* 58494 */ /*GILLT_v4s16*//*Label 1785*/ GIMT_Encode4(58510),
21293 /* 58498 */ /*GILLT_v8s16*//*Label 1786*/ GIMT_Encode4(58556),
21294 /* 58502 */ /*GILLT_v2s32*//*Label 1787*/ GIMT_Encode4(58602),
21295 /* 58506 */ /*GILLT_v4s32*//*Label 1788*/ GIMT_Encode4(58648),
21296 /* 58510 */ // Label 1785: @58510
21297 /* 58510 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1790*/ GIMT_Encode4(58555), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1462 //
21298 /* 58517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21299 /* 58520 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21300 /* 58523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21301 /* 58527 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21302 /* 58531 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21303 /* 58535 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4069:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21304 /* 58535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShd),
21305 /* 58538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21306 /* 58540 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21307 /* 58542 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21308 /* 58544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21309 /* 58547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21310 /* 58553 */ GIR_RootConstrainSelectedInstOperands,
21311 /* 58554 */ // GIR_Coverage, 1462,
21312 /* 58554 */ GIR_EraseRootFromParent_Done,
21313 /* 58555 */ // Label 1790: @58555
21314 /* 58555 */ GIM_Reject,
21315 /* 58556 */ // Label 1786: @58556
21316 /* 58556 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1791*/ GIMT_Encode4(58601), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1463 //
21317 /* 58563 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21318 /* 58566 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21319 /* 58569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21320 /* 58573 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21321 /* 58577 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21322 /* 58581 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4069:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21323 /* 58581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShq),
21324 /* 58584 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21325 /* 58586 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21326 /* 58588 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21327 /* 58590 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21328 /* 58593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21329 /* 58599 */ GIR_RootConstrainSelectedInstOperands,
21330 /* 58600 */ // GIR_Coverage, 1463,
21331 /* 58600 */ GIR_EraseRootFromParent_Done,
21332 /* 58601 */ // Label 1791: @58601
21333 /* 58601 */ GIM_Reject,
21334 /* 58602 */ // Label 1787: @58602
21335 /* 58602 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1792*/ GIMT_Encode4(58647), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1460 //
21336 /* 58609 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21337 /* 58612 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21338 /* 58615 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21339 /* 58619 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21340 /* 58623 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21341 /* 58627 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4069:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21342 /* 58627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfd),
21343 /* 58630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21344 /* 58632 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21345 /* 58634 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21346 /* 58636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21347 /* 58639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21348 /* 58645 */ GIR_RootConstrainSelectedInstOperands,
21349 /* 58646 */ // GIR_Coverage, 1460,
21350 /* 58646 */ GIR_EraseRootFromParent_Done,
21351 /* 58647 */ // Label 1792: @58647
21352 /* 58647 */ GIM_Reject,
21353 /* 58648 */ // Label 1788: @58648
21354 /* 58648 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1793*/ GIMT_Encode4(58693), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1461 //
21355 /* 58655 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21356 /* 58658 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21357 /* 58661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21358 /* 58665 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21359 /* 58669 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21360 /* 58673 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4069:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21361 /* 58673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfq),
21362 /* 58676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21363 /* 58678 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21364 /* 58680 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21365 /* 58682 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21366 /* 58685 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21367 /* 58691 */ GIR_RootConstrainSelectedInstOperands,
21368 /* 58692 */ // GIR_Coverage, 1461,
21369 /* 58692 */ GIR_EraseRootFromParent_Done,
21370 /* 58693 */ // Label 1793: @58693
21371 /* 58693 */ GIM_Reject,
21372 /* 58694 */ // Label 1789: @58694
21373 /* 58694 */ GIM_Reject,
21374 /* 58695 */ // Label 1784: @58695
21375 /* 58695 */ GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(59133),
21376 /* 58700 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
21377 /* 58705 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1803*/ GIMT_Encode4(59132),
21378 /* 58716 */ /*GILLT_s64*//*Label 1795*/ GIMT_Encode4(58764), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
21379 /* 58736 */ /*GILLT_v8s8*//*Label 1796*/ GIMT_Encode4(58810),
21380 /* 58740 */ /*GILLT_v16s8*//*Label 1797*/ GIMT_Encode4(58856),
21381 /* 58744 */ /*GILLT_v4s16*//*Label 1798*/ GIMT_Encode4(58902),
21382 /* 58748 */ /*GILLT_v8s16*//*Label 1799*/ GIMT_Encode4(58948),
21383 /* 58752 */ /*GILLT_v2s32*//*Label 1800*/ GIMT_Encode4(58994),
21384 /* 58756 */ /*GILLT_v4s32*//*Label 1801*/ GIMT_Encode4(59040),
21385 /* 58760 */ /*GILLT_v2s64*//*Label 1802*/ GIMT_Encode4(59086),
21386 /* 58764 */ // Label 1795: @58764
21387 /* 58764 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1804*/ GIMT_Encode4(58809), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1470 //
21388 /* 58771 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21389 /* 58774 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21390 /* 58777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21391 /* 58781 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21392 /* 58785 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21393 /* 58789 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4072:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
21394 /* 58789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv1i64),
21395 /* 58792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21396 /* 58794 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21397 /* 58796 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21398 /* 58798 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21399 /* 58801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21400 /* 58807 */ GIR_RootConstrainSelectedInstOperands,
21401 /* 58808 */ // GIR_Coverage, 1470,
21402 /* 58808 */ GIR_EraseRootFromParent_Done,
21403 /* 58809 */ // Label 1804: @58809
21404 /* 58809 */ GIM_Reject,
21405 /* 58810 */ // Label 1796: @58810
21406 /* 58810 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1805*/ GIMT_Encode4(58855), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1468 //
21407 /* 58817 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21408 /* 58820 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21409 /* 58823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21410 /* 58827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21411 /* 58831 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21412 /* 58835 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4072:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21413 /* 58835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i8),
21414 /* 58838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21415 /* 58840 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21416 /* 58842 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21417 /* 58844 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21418 /* 58847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21419 /* 58853 */ GIR_RootConstrainSelectedInstOperands,
21420 /* 58854 */ // GIR_Coverage, 1468,
21421 /* 58854 */ GIR_EraseRootFromParent_Done,
21422 /* 58855 */ // Label 1805: @58855
21423 /* 58855 */ GIM_Reject,
21424 /* 58856 */ // Label 1797: @58856
21425 /* 58856 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1806*/ GIMT_Encode4(58901), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1469 //
21426 /* 58863 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21427 /* 58866 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
21428 /* 58869 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21429 /* 58873 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21430 /* 58877 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21431 /* 58881 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4072:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21432 /* 58881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv16i8),
21433 /* 58884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21434 /* 58886 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21435 /* 58888 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21436 /* 58890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21437 /* 58893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21438 /* 58899 */ GIR_RootConstrainSelectedInstOperands,
21439 /* 58900 */ // GIR_Coverage, 1469,
21440 /* 58900 */ GIR_EraseRootFromParent_Done,
21441 /* 58901 */ // Label 1806: @58901
21442 /* 58901 */ GIM_Reject,
21443 /* 58902 */ // Label 1798: @58902
21444 /* 58902 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1807*/ GIMT_Encode4(58947), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1464 //
21445 /* 58909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21446 /* 58912 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21447 /* 58915 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21448 /* 58919 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21449 /* 58923 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21450 /* 58927 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4072:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21451 /* 58927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i16),
21452 /* 58930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21453 /* 58932 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21454 /* 58934 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21455 /* 58936 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21456 /* 58939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21457 /* 58945 */ GIR_RootConstrainSelectedInstOperands,
21458 /* 58946 */ // GIR_Coverage, 1464,
21459 /* 58946 */ GIR_EraseRootFromParent_Done,
21460 /* 58947 */ // Label 1807: @58947
21461 /* 58947 */ GIM_Reject,
21462 /* 58948 */ // Label 1799: @58948
21463 /* 58948 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1808*/ GIMT_Encode4(58993), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1466 //
21464 /* 58955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21465 /* 58958 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21466 /* 58961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21467 /* 58965 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21468 /* 58969 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21469 /* 58973 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4072:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21470 /* 58973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i16),
21471 /* 58976 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21472 /* 58978 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21473 /* 58980 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21474 /* 58982 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21475 /* 58985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21476 /* 58991 */ GIR_RootConstrainSelectedInstOperands,
21477 /* 58992 */ // GIR_Coverage, 1466,
21478 /* 58992 */ GIR_EraseRootFromParent_Done,
21479 /* 58993 */ // Label 1808: @58993
21480 /* 58993 */ GIM_Reject,
21481 /* 58994 */ // Label 1800: @58994
21482 /* 58994 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1809*/ GIMT_Encode4(59039), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1465 //
21483 /* 59001 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21484 /* 59004 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21485 /* 59007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21486 /* 59011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21487 /* 59015 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21488 /* 59019 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4072:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21489 /* 59019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i32),
21490 /* 59022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21491 /* 59024 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21492 /* 59026 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21493 /* 59028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21494 /* 59031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21495 /* 59037 */ GIR_RootConstrainSelectedInstOperands,
21496 /* 59038 */ // GIR_Coverage, 1465,
21497 /* 59038 */ GIR_EraseRootFromParent_Done,
21498 /* 59039 */ // Label 1809: @59039
21499 /* 59039 */ GIM_Reject,
21500 /* 59040 */ // Label 1801: @59040
21501 /* 59040 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1810*/ GIMT_Encode4(59085), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1467 //
21502 /* 59047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21503 /* 59050 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21504 /* 59053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21505 /* 59057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21506 /* 59061 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21507 /* 59065 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4072:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21508 /* 59065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i32),
21509 /* 59068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21510 /* 59070 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21511 /* 59072 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21512 /* 59074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21513 /* 59077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21514 /* 59083 */ GIR_RootConstrainSelectedInstOperands,
21515 /* 59084 */ // GIR_Coverage, 1467,
21516 /* 59084 */ GIR_EraseRootFromParent_Done,
21517 /* 59085 */ // Label 1810: @59085
21518 /* 59085 */ GIM_Reject,
21519 /* 59086 */ // Label 1802: @59086
21520 /* 59086 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1811*/ GIMT_Encode4(59131), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1471 //
21521 /* 59093 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21522 /* 59096 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21523 /* 59099 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21524 /* 59103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21525 /* 59107 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21526 /* 59111 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4072:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
21527 /* 59111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i64),
21528 /* 59114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21529 /* 59116 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21530 /* 59118 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21531 /* 59120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21532 /* 59123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21533 /* 59129 */ GIR_RootConstrainSelectedInstOperands,
21534 /* 59130 */ // GIR_Coverage, 1471,
21535 /* 59130 */ GIR_EraseRootFromParent_Done,
21536 /* 59131 */ // Label 1811: @59131
21537 /* 59131 */ GIM_Reject,
21538 /* 59132 */ // Label 1803: @59132
21539 /* 59132 */ GIM_Reject,
21540 /* 59133 */ // Label 1794: @59133
21541 /* 59133 */ GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(59571),
21542 /* 59138 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
21543 /* 59143 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1821*/ GIMT_Encode4(59570),
21544 /* 59154 */ /*GILLT_s64*//*Label 1813*/ GIMT_Encode4(59202), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
21545 /* 59174 */ /*GILLT_v8s8*//*Label 1814*/ GIMT_Encode4(59248),
21546 /* 59178 */ /*GILLT_v16s8*//*Label 1815*/ GIMT_Encode4(59294),
21547 /* 59182 */ /*GILLT_v4s16*//*Label 1816*/ GIMT_Encode4(59340),
21548 /* 59186 */ /*GILLT_v8s16*//*Label 1817*/ GIMT_Encode4(59386),
21549 /* 59190 */ /*GILLT_v2s32*//*Label 1818*/ GIMT_Encode4(59432),
21550 /* 59194 */ /*GILLT_v4s32*//*Label 1819*/ GIMT_Encode4(59478),
21551 /* 59198 */ /*GILLT_v2s64*//*Label 1820*/ GIMT_Encode4(59524),
21552 /* 59202 */ // Label 1813: @59202
21553 /* 59202 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1822*/ GIMT_Encode4(59247), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1478 //
21554 /* 59209 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21555 /* 59212 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21556 /* 59215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21557 /* 59219 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21558 /* 59223 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21559 /* 59227 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4073:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
21560 /* 59227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv1i64),
21561 /* 59230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21562 /* 59232 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21563 /* 59234 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21564 /* 59236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21565 /* 59239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21566 /* 59245 */ GIR_RootConstrainSelectedInstOperands,
21567 /* 59246 */ // GIR_Coverage, 1478,
21568 /* 59246 */ GIR_EraseRootFromParent_Done,
21569 /* 59247 */ // Label 1822: @59247
21570 /* 59247 */ GIM_Reject,
21571 /* 59248 */ // Label 1814: @59248
21572 /* 59248 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1823*/ GIMT_Encode4(59293), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1476 //
21573 /* 59255 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21574 /* 59258 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21575 /* 59261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21576 /* 59265 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21577 /* 59269 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21578 /* 59273 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4073:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21579 /* 59273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i8),
21580 /* 59276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21581 /* 59278 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21582 /* 59280 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21583 /* 59282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21584 /* 59285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21585 /* 59291 */ GIR_RootConstrainSelectedInstOperands,
21586 /* 59292 */ // GIR_Coverage, 1476,
21587 /* 59292 */ GIR_EraseRootFromParent_Done,
21588 /* 59293 */ // Label 1823: @59293
21589 /* 59293 */ GIM_Reject,
21590 /* 59294 */ // Label 1815: @59294
21591 /* 59294 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1824*/ GIMT_Encode4(59339), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1477 //
21592 /* 59301 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21593 /* 59304 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
21594 /* 59307 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21595 /* 59311 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21596 /* 59315 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21597 /* 59319 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4073:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21598 /* 59319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv16i8),
21599 /* 59322 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21600 /* 59324 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21601 /* 59326 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21602 /* 59328 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21603 /* 59331 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21604 /* 59337 */ GIR_RootConstrainSelectedInstOperands,
21605 /* 59338 */ // GIR_Coverage, 1477,
21606 /* 59338 */ GIR_EraseRootFromParent_Done,
21607 /* 59339 */ // Label 1824: @59339
21608 /* 59339 */ GIM_Reject,
21609 /* 59340 */ // Label 1816: @59340
21610 /* 59340 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1825*/ GIMT_Encode4(59385), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1472 //
21611 /* 59347 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21612 /* 59350 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21613 /* 59353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21614 /* 59357 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21615 /* 59361 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21616 /* 59365 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4073:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21617 /* 59365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i16),
21618 /* 59368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21619 /* 59370 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21620 /* 59372 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21621 /* 59374 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21622 /* 59377 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21623 /* 59383 */ GIR_RootConstrainSelectedInstOperands,
21624 /* 59384 */ // GIR_Coverage, 1472,
21625 /* 59384 */ GIR_EraseRootFromParent_Done,
21626 /* 59385 */ // Label 1825: @59385
21627 /* 59385 */ GIM_Reject,
21628 /* 59386 */ // Label 1817: @59386
21629 /* 59386 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1826*/ GIMT_Encode4(59431), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1474 //
21630 /* 59393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21631 /* 59396 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21632 /* 59399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21633 /* 59403 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21634 /* 59407 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21635 /* 59411 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4073:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21636 /* 59411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i16),
21637 /* 59414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21638 /* 59416 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21639 /* 59418 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21640 /* 59420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21641 /* 59423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21642 /* 59429 */ GIR_RootConstrainSelectedInstOperands,
21643 /* 59430 */ // GIR_Coverage, 1474,
21644 /* 59430 */ GIR_EraseRootFromParent_Done,
21645 /* 59431 */ // Label 1826: @59431
21646 /* 59431 */ GIM_Reject,
21647 /* 59432 */ // Label 1818: @59432
21648 /* 59432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1827*/ GIMT_Encode4(59477), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1473 //
21649 /* 59439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21650 /* 59442 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21651 /* 59445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21652 /* 59449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21653 /* 59453 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21654 /* 59457 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4073:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21655 /* 59457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i32),
21656 /* 59460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21657 /* 59462 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21658 /* 59464 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21659 /* 59466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21660 /* 59469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21661 /* 59475 */ GIR_RootConstrainSelectedInstOperands,
21662 /* 59476 */ // GIR_Coverage, 1473,
21663 /* 59476 */ GIR_EraseRootFromParent_Done,
21664 /* 59477 */ // Label 1827: @59477
21665 /* 59477 */ GIM_Reject,
21666 /* 59478 */ // Label 1819: @59478
21667 /* 59478 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1828*/ GIMT_Encode4(59523), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1475 //
21668 /* 59485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21669 /* 59488 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21670 /* 59491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21671 /* 59495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21672 /* 59499 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21673 /* 59503 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4073:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21674 /* 59503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i32),
21675 /* 59506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21676 /* 59508 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21677 /* 59510 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21678 /* 59512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21679 /* 59515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21680 /* 59521 */ GIR_RootConstrainSelectedInstOperands,
21681 /* 59522 */ // GIR_Coverage, 1475,
21682 /* 59522 */ GIR_EraseRootFromParent_Done,
21683 /* 59523 */ // Label 1828: @59523
21684 /* 59523 */ GIM_Reject,
21685 /* 59524 */ // Label 1820: @59524
21686 /* 59524 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1829*/ GIMT_Encode4(59569), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1479 //
21687 /* 59531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21688 /* 59534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21689 /* 59537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21690 /* 59541 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21691 /* 59545 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21692 /* 59549 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4073:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
21693 /* 59549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i64),
21694 /* 59552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21695 /* 59554 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21696 /* 59556 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21697 /* 59558 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21698 /* 59561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21699 /* 59567 */ GIR_RootConstrainSelectedInstOperands,
21700 /* 59568 */ // GIR_Coverage, 1479,
21701 /* 59568 */ GIR_EraseRootFromParent_Done,
21702 /* 59569 */ // Label 1829: @59569
21703 /* 59569 */ GIM_Reject,
21704 /* 59570 */ // Label 1821: @59570
21705 /* 59570 */ GIM_Reject,
21706 /* 59571 */ // Label 1812: @59571
21707 /* 59571 */ GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(60009),
21708 /* 59576 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
21709 /* 59581 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1839*/ GIMT_Encode4(60008),
21710 /* 59592 */ /*GILLT_s64*//*Label 1831*/ GIMT_Encode4(59640), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
21711 /* 59612 */ /*GILLT_v8s8*//*Label 1832*/ GIMT_Encode4(59686),
21712 /* 59616 */ /*GILLT_v16s8*//*Label 1833*/ GIMT_Encode4(59732),
21713 /* 59620 */ /*GILLT_v4s16*//*Label 1834*/ GIMT_Encode4(59778),
21714 /* 59624 */ /*GILLT_v8s16*//*Label 1835*/ GIMT_Encode4(59824),
21715 /* 59628 */ /*GILLT_v2s32*//*Label 1836*/ GIMT_Encode4(59870),
21716 /* 59632 */ /*GILLT_v4s32*//*Label 1837*/ GIMT_Encode4(59916),
21717 /* 59636 */ /*GILLT_v2s64*//*Label 1838*/ GIMT_Encode4(59962),
21718 /* 59640 */ // Label 1831: @59640
21719 /* 59640 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1840*/ GIMT_Encode4(59685), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1519 //
21720 /* 59647 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21721 /* 59650 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21722 /* 59653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21723 /* 59657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21724 /* 59661 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21725 /* 59665 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4066:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
21726 /* 59665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv1i64),
21727 /* 59668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21728 /* 59670 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21729 /* 59672 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21730 /* 59674 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21731 /* 59677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21732 /* 59683 */ GIR_RootConstrainSelectedInstOperands,
21733 /* 59684 */ // GIR_Coverage, 1519,
21734 /* 59684 */ GIR_EraseRootFromParent_Done,
21735 /* 59685 */ // Label 1840: @59685
21736 /* 59685 */ GIM_Reject,
21737 /* 59686 */ // Label 1832: @59686
21738 /* 59686 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1841*/ GIMT_Encode4(59731), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1517 //
21739 /* 59693 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21740 /* 59696 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21741 /* 59699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21742 /* 59703 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21743 /* 59707 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21744 /* 59711 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4066:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21745 /* 59711 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i8),
21746 /* 59714 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21747 /* 59716 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21748 /* 59718 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21749 /* 59720 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21750 /* 59723 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21751 /* 59729 */ GIR_RootConstrainSelectedInstOperands,
21752 /* 59730 */ // GIR_Coverage, 1517,
21753 /* 59730 */ GIR_EraseRootFromParent_Done,
21754 /* 59731 */ // Label 1841: @59731
21755 /* 59731 */ GIM_Reject,
21756 /* 59732 */ // Label 1833: @59732
21757 /* 59732 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1842*/ GIMT_Encode4(59777), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1518 //
21758 /* 59739 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21759 /* 59742 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
21760 /* 59745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21761 /* 59749 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21762 /* 59753 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21763 /* 59757 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4066:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21764 /* 59757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv16i8),
21765 /* 59760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21766 /* 59762 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21767 /* 59764 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21768 /* 59766 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21769 /* 59769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21770 /* 59775 */ GIR_RootConstrainSelectedInstOperands,
21771 /* 59776 */ // GIR_Coverage, 1518,
21772 /* 59776 */ GIR_EraseRootFromParent_Done,
21773 /* 59777 */ // Label 1842: @59777
21774 /* 59777 */ GIM_Reject,
21775 /* 59778 */ // Label 1834: @59778
21776 /* 59778 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1843*/ GIMT_Encode4(59823), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1513 //
21777 /* 59785 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21778 /* 59788 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21779 /* 59791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21780 /* 59795 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21781 /* 59799 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21782 /* 59803 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4066:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21783 /* 59803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i16),
21784 /* 59806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21785 /* 59808 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21786 /* 59810 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21787 /* 59812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21788 /* 59815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21789 /* 59821 */ GIR_RootConstrainSelectedInstOperands,
21790 /* 59822 */ // GIR_Coverage, 1513,
21791 /* 59822 */ GIR_EraseRootFromParent_Done,
21792 /* 59823 */ // Label 1843: @59823
21793 /* 59823 */ GIM_Reject,
21794 /* 59824 */ // Label 1835: @59824
21795 /* 59824 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1844*/ GIMT_Encode4(59869), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1515 //
21796 /* 59831 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21797 /* 59834 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21798 /* 59837 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21799 /* 59841 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21800 /* 59845 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21801 /* 59849 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4066:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21802 /* 59849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i16),
21803 /* 59852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21804 /* 59854 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21805 /* 59856 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21806 /* 59858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21807 /* 59861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21808 /* 59867 */ GIR_RootConstrainSelectedInstOperands,
21809 /* 59868 */ // GIR_Coverage, 1515,
21810 /* 59868 */ GIR_EraseRootFromParent_Done,
21811 /* 59869 */ // Label 1844: @59869
21812 /* 59869 */ GIM_Reject,
21813 /* 59870 */ // Label 1836: @59870
21814 /* 59870 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1845*/ GIMT_Encode4(59915), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1514 //
21815 /* 59877 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21816 /* 59880 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21817 /* 59883 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21818 /* 59887 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21819 /* 59891 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21820 /* 59895 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4066:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21821 /* 59895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i32),
21822 /* 59898 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21823 /* 59900 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21824 /* 59902 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21825 /* 59904 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21826 /* 59907 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21827 /* 59913 */ GIR_RootConstrainSelectedInstOperands,
21828 /* 59914 */ // GIR_Coverage, 1514,
21829 /* 59914 */ GIR_EraseRootFromParent_Done,
21830 /* 59915 */ // Label 1845: @59915
21831 /* 59915 */ GIM_Reject,
21832 /* 59916 */ // Label 1837: @59916
21833 /* 59916 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1846*/ GIMT_Encode4(59961), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1516 //
21834 /* 59923 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21835 /* 59926 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21836 /* 59929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21837 /* 59933 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21838 /* 59937 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21839 /* 59941 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4066:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
21840 /* 59941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i32),
21841 /* 59944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21842 /* 59946 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21843 /* 59948 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21844 /* 59950 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21845 /* 59953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21846 /* 59959 */ GIR_RootConstrainSelectedInstOperands,
21847 /* 59960 */ // GIR_Coverage, 1516,
21848 /* 59960 */ GIR_EraseRootFromParent_Done,
21849 /* 59961 */ // Label 1846: @59961
21850 /* 59961 */ GIM_Reject,
21851 /* 59962 */ // Label 1838: @59962
21852 /* 59962 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1847*/ GIMT_Encode4(60007), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1520 //
21853 /* 59969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21854 /* 59972 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21855 /* 59975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21856 /* 59979 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21857 /* 59983 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21858 /* 59987 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4066:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
21859 /* 59987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i64),
21860 /* 59990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21861 /* 59992 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21862 /* 59994 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21863 /* 59996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21864 /* 59999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21865 /* 60005 */ GIR_RootConstrainSelectedInstOperands,
21866 /* 60006 */ // GIR_Coverage, 1520,
21867 /* 60006 */ GIR_EraseRootFromParent_Done,
21868 /* 60007 */ // Label 1847: @60007
21869 /* 60007 */ GIM_Reject,
21870 /* 60008 */ // Label 1839: @60008
21871 /* 60008 */ GIM_Reject,
21872 /* 60009 */ // Label 1830: @60009
21873 /* 60009 */ GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(60447),
21874 /* 60014 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
21875 /* 60019 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1857*/ GIMT_Encode4(60446),
21876 /* 60030 */ /*GILLT_s64*//*Label 1849*/ GIMT_Encode4(60078), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
21877 /* 60050 */ /*GILLT_v8s8*//*Label 1850*/ GIMT_Encode4(60124),
21878 /* 60054 */ /*GILLT_v16s8*//*Label 1851*/ GIMT_Encode4(60170),
21879 /* 60058 */ /*GILLT_v4s16*//*Label 1852*/ GIMT_Encode4(60216),
21880 /* 60062 */ /*GILLT_v8s16*//*Label 1853*/ GIMT_Encode4(60262),
21881 /* 60066 */ /*GILLT_v2s32*//*Label 1854*/ GIMT_Encode4(60308),
21882 /* 60070 */ /*GILLT_v4s32*//*Label 1855*/ GIMT_Encode4(60354),
21883 /* 60074 */ /*GILLT_v2s64*//*Label 1856*/ GIMT_Encode4(60400),
21884 /* 60078 */ // Label 1849: @60078
21885 /* 60078 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1858*/ GIMT_Encode4(60123), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1527 //
21886 /* 60085 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21887 /* 60088 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
21888 /* 60091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21889 /* 60095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21890 /* 60099 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21891 /* 60103 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4067:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
21892 /* 60103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv1i64),
21893 /* 60106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21894 /* 60108 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21895 /* 60110 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21896 /* 60112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21897 /* 60115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21898 /* 60121 */ GIR_RootConstrainSelectedInstOperands,
21899 /* 60122 */ // GIR_Coverage, 1527,
21900 /* 60122 */ GIR_EraseRootFromParent_Done,
21901 /* 60123 */ // Label 1858: @60123
21902 /* 60123 */ GIM_Reject,
21903 /* 60124 */ // Label 1850: @60124
21904 /* 60124 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1859*/ GIMT_Encode4(60169), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1525 //
21905 /* 60131 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21906 /* 60134 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21907 /* 60137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21908 /* 60141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21909 /* 60145 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21910 /* 60149 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4067:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
21911 /* 60149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i8),
21912 /* 60152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21913 /* 60154 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21914 /* 60156 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21915 /* 60158 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21916 /* 60161 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21917 /* 60167 */ GIR_RootConstrainSelectedInstOperands,
21918 /* 60168 */ // GIR_Coverage, 1525,
21919 /* 60168 */ GIR_EraseRootFromParent_Done,
21920 /* 60169 */ // Label 1859: @60169
21921 /* 60169 */ GIM_Reject,
21922 /* 60170 */ // Label 1851: @60170
21923 /* 60170 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1860*/ GIMT_Encode4(60215), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1526 //
21924 /* 60177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21925 /* 60180 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
21926 /* 60183 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21927 /* 60187 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21928 /* 60191 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21929 /* 60195 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4067:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
21930 /* 60195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv16i8),
21931 /* 60198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21932 /* 60200 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21933 /* 60202 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21934 /* 60204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21935 /* 60207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21936 /* 60213 */ GIR_RootConstrainSelectedInstOperands,
21937 /* 60214 */ // GIR_Coverage, 1526,
21938 /* 60214 */ GIR_EraseRootFromParent_Done,
21939 /* 60215 */ // Label 1860: @60215
21940 /* 60215 */ GIM_Reject,
21941 /* 60216 */ // Label 1852: @60216
21942 /* 60216 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1861*/ GIMT_Encode4(60261), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1521 //
21943 /* 60223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21944 /* 60226 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21945 /* 60229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21946 /* 60233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21947 /* 60237 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21948 /* 60241 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4067:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
21949 /* 60241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i16),
21950 /* 60244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21951 /* 60246 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21952 /* 60248 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21953 /* 60250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21954 /* 60253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21955 /* 60259 */ GIR_RootConstrainSelectedInstOperands,
21956 /* 60260 */ // GIR_Coverage, 1521,
21957 /* 60260 */ GIR_EraseRootFromParent_Done,
21958 /* 60261 */ // Label 1861: @60261
21959 /* 60261 */ GIM_Reject,
21960 /* 60262 */ // Label 1853: @60262
21961 /* 60262 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1862*/ GIMT_Encode4(60307), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1523 //
21962 /* 60269 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21963 /* 60272 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21964 /* 60275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21965 /* 60279 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21966 /* 60283 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21967 /* 60287 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4067:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
21968 /* 60287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i16),
21969 /* 60290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21970 /* 60292 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21971 /* 60294 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21972 /* 60296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21973 /* 60299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21974 /* 60305 */ GIR_RootConstrainSelectedInstOperands,
21975 /* 60306 */ // GIR_Coverage, 1523,
21976 /* 60306 */ GIR_EraseRootFromParent_Done,
21977 /* 60307 */ // Label 1862: @60307
21978 /* 60307 */ GIM_Reject,
21979 /* 60308 */ // Label 1854: @60308
21980 /* 60308 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1863*/ GIMT_Encode4(60353), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1522 //
21981 /* 60315 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21982 /* 60318 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21983 /* 60321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21984 /* 60325 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21985 /* 60329 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21986 /* 60333 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4067:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
21987 /* 60333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i32),
21988 /* 60336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21989 /* 60338 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
21990 /* 60340 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
21991 /* 60342 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21992 /* 60345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21993 /* 60351 */ GIR_RootConstrainSelectedInstOperands,
21994 /* 60352 */ // GIR_Coverage, 1522,
21995 /* 60352 */ GIR_EraseRootFromParent_Done,
21996 /* 60353 */ // Label 1863: @60353
21997 /* 60353 */ GIM_Reject,
21998 /* 60354 */ // Label 1855: @60354
21999 /* 60354 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1864*/ GIMT_Encode4(60399), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1524 //
22000 /* 60361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22001 /* 60364 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22002 /* 60367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22003 /* 60371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22004 /* 60375 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22005 /* 60379 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4067:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22006 /* 60379 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i32),
22007 /* 60382 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22008 /* 60384 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22009 /* 60386 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22010 /* 60388 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22011 /* 60391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22012 /* 60397 */ GIR_RootConstrainSelectedInstOperands,
22013 /* 60398 */ // GIR_Coverage, 1524,
22014 /* 60398 */ GIR_EraseRootFromParent_Done,
22015 /* 60399 */ // Label 1864: @60399
22016 /* 60399 */ GIM_Reject,
22017 /* 60400 */ // Label 1856: @60400
22018 /* 60400 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1865*/ GIMT_Encode4(60445), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1528 //
22019 /* 60407 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22020 /* 60410 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22021 /* 60413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22022 /* 60417 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22023 /* 60421 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22024 /* 60425 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4067:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22025 /* 60425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i64),
22026 /* 60428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22027 /* 60430 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22028 /* 60432 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22029 /* 60434 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22030 /* 60437 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22031 /* 60443 */ GIR_RootConstrainSelectedInstOperands,
22032 /* 60444 */ // GIR_Coverage, 1528,
22033 /* 60444 */ GIR_EraseRootFromParent_Done,
22034 /* 60445 */ // Label 1865: @60445
22035 /* 60445 */ GIM_Reject,
22036 /* 60446 */ // Label 1857: @60446
22037 /* 60446 */ GIM_Reject,
22038 /* 60447 */ // Label 1848: @60447
22039 /* 60447 */ GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(60885),
22040 /* 60452 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22041 /* 60457 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1875*/ GIMT_Encode4(60884),
22042 /* 60468 */ /*GILLT_s64*//*Label 1867*/ GIMT_Encode4(60516), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
22043 /* 60488 */ /*GILLT_v8s8*//*Label 1868*/ GIMT_Encode4(60562),
22044 /* 60492 */ /*GILLT_v16s8*//*Label 1869*/ GIMT_Encode4(60608),
22045 /* 60496 */ /*GILLT_v4s16*//*Label 1870*/ GIMT_Encode4(60654),
22046 /* 60500 */ /*GILLT_v8s16*//*Label 1871*/ GIMT_Encode4(60700),
22047 /* 60504 */ /*GILLT_v2s32*//*Label 1872*/ GIMT_Encode4(60746),
22048 /* 60508 */ /*GILLT_v4s32*//*Label 1873*/ GIMT_Encode4(60792),
22049 /* 60512 */ /*GILLT_v2s64*//*Label 1874*/ GIMT_Encode4(60838),
22050 /* 60516 */ // Label 1867: @60516
22051 /* 60516 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1876*/ GIMT_Encode4(60561), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1554 //
22052 /* 60523 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22053 /* 60526 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22054 /* 60529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22055 /* 60533 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22056 /* 60537 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22057 /* 60541 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4057:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22058 /* 60541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv1i64),
22059 /* 60544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22060 /* 60546 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22061 /* 60548 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22062 /* 60550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22063 /* 60553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22064 /* 60559 */ GIR_RootConstrainSelectedInstOperands,
22065 /* 60560 */ // GIR_Coverage, 1554,
22066 /* 60560 */ GIR_EraseRootFromParent_Done,
22067 /* 60561 */ // Label 1876: @60561
22068 /* 60561 */ GIM_Reject,
22069 /* 60562 */ // Label 1868: @60562
22070 /* 60562 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1877*/ GIMT_Encode4(60607), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1552 //
22071 /* 60569 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22072 /* 60572 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22073 /* 60575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22074 /* 60579 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22075 /* 60583 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22076 /* 60587 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4057:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22077 /* 60587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i8),
22078 /* 60590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22079 /* 60592 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22080 /* 60594 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22081 /* 60596 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22082 /* 60599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22083 /* 60605 */ GIR_RootConstrainSelectedInstOperands,
22084 /* 60606 */ // GIR_Coverage, 1552,
22085 /* 60606 */ GIR_EraseRootFromParent_Done,
22086 /* 60607 */ // Label 1877: @60607
22087 /* 60607 */ GIM_Reject,
22088 /* 60608 */ // Label 1869: @60608
22089 /* 60608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1878*/ GIMT_Encode4(60653), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1553 //
22090 /* 60615 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22091 /* 60618 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22092 /* 60621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22093 /* 60625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22094 /* 60629 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22095 /* 60633 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4057:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22096 /* 60633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv16i8),
22097 /* 60636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22098 /* 60638 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22099 /* 60640 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22100 /* 60642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22101 /* 60645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22102 /* 60651 */ GIR_RootConstrainSelectedInstOperands,
22103 /* 60652 */ // GIR_Coverage, 1553,
22104 /* 60652 */ GIR_EraseRootFromParent_Done,
22105 /* 60653 */ // Label 1878: @60653
22106 /* 60653 */ GIM_Reject,
22107 /* 60654 */ // Label 1870: @60654
22108 /* 60654 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1879*/ GIMT_Encode4(60699), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1548 //
22109 /* 60661 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22110 /* 60664 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22111 /* 60667 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22112 /* 60671 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22113 /* 60675 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22114 /* 60679 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4057:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22115 /* 60679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i16),
22116 /* 60682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22117 /* 60684 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22118 /* 60686 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22119 /* 60688 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22120 /* 60691 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22121 /* 60697 */ GIR_RootConstrainSelectedInstOperands,
22122 /* 60698 */ // GIR_Coverage, 1548,
22123 /* 60698 */ GIR_EraseRootFromParent_Done,
22124 /* 60699 */ // Label 1879: @60699
22125 /* 60699 */ GIM_Reject,
22126 /* 60700 */ // Label 1871: @60700
22127 /* 60700 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1880*/ GIMT_Encode4(60745), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1550 //
22128 /* 60707 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22129 /* 60710 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22130 /* 60713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22131 /* 60717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22132 /* 60721 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22133 /* 60725 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4057:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22134 /* 60725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i16),
22135 /* 60728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22136 /* 60730 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22137 /* 60732 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22138 /* 60734 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22139 /* 60737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22140 /* 60743 */ GIR_RootConstrainSelectedInstOperands,
22141 /* 60744 */ // GIR_Coverage, 1550,
22142 /* 60744 */ GIR_EraseRootFromParent_Done,
22143 /* 60745 */ // Label 1880: @60745
22144 /* 60745 */ GIM_Reject,
22145 /* 60746 */ // Label 1872: @60746
22146 /* 60746 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1881*/ GIMT_Encode4(60791), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1549 //
22147 /* 60753 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22148 /* 60756 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22149 /* 60759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22150 /* 60763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22151 /* 60767 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22152 /* 60771 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4057:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22153 /* 60771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i32),
22154 /* 60774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22155 /* 60776 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22156 /* 60778 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22157 /* 60780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22158 /* 60783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22159 /* 60789 */ GIR_RootConstrainSelectedInstOperands,
22160 /* 60790 */ // GIR_Coverage, 1549,
22161 /* 60790 */ GIR_EraseRootFromParent_Done,
22162 /* 60791 */ // Label 1881: @60791
22163 /* 60791 */ GIM_Reject,
22164 /* 60792 */ // Label 1873: @60792
22165 /* 60792 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1882*/ GIMT_Encode4(60837), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1551 //
22166 /* 60799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22167 /* 60802 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22168 /* 60805 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22169 /* 60809 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22170 /* 60813 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22171 /* 60817 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4057:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22172 /* 60817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i32),
22173 /* 60820 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22174 /* 60822 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22175 /* 60824 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22176 /* 60826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22177 /* 60829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22178 /* 60835 */ GIR_RootConstrainSelectedInstOperands,
22179 /* 60836 */ // GIR_Coverage, 1551,
22180 /* 60836 */ GIR_EraseRootFromParent_Done,
22181 /* 60837 */ // Label 1882: @60837
22182 /* 60837 */ GIM_Reject,
22183 /* 60838 */ // Label 1874: @60838
22184 /* 60838 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1883*/ GIMT_Encode4(60883), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1555 //
22185 /* 60845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22186 /* 60848 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22187 /* 60851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22188 /* 60855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22189 /* 60859 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22190 /* 60863 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4057:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22191 /* 60863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i64),
22192 /* 60866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22193 /* 60868 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22194 /* 60870 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22195 /* 60872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22196 /* 60875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22197 /* 60881 */ GIR_RootConstrainSelectedInstOperands,
22198 /* 60882 */ // GIR_Coverage, 1555,
22199 /* 60882 */ GIR_EraseRootFromParent_Done,
22200 /* 60883 */ // Label 1883: @60883
22201 /* 60883 */ GIM_Reject,
22202 /* 60884 */ // Label 1875: @60884
22203 /* 60884 */ GIM_Reject,
22204 /* 60885 */ // Label 1866: @60885
22205 /* 60885 */ GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(61323),
22206 /* 60890 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
22207 /* 60895 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1893*/ GIMT_Encode4(61322),
22208 /* 60906 */ /*GILLT_s64*//*Label 1885*/ GIMT_Encode4(60954), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
22209 /* 60926 */ /*GILLT_v8s8*//*Label 1886*/ GIMT_Encode4(61000),
22210 /* 60930 */ /*GILLT_v16s8*//*Label 1887*/ GIMT_Encode4(61046),
22211 /* 60934 */ /*GILLT_v4s16*//*Label 1888*/ GIMT_Encode4(61092),
22212 /* 60938 */ /*GILLT_v8s16*//*Label 1889*/ GIMT_Encode4(61138),
22213 /* 60942 */ /*GILLT_v2s32*//*Label 1890*/ GIMT_Encode4(61184),
22214 /* 60946 */ /*GILLT_v4s32*//*Label 1891*/ GIMT_Encode4(61230),
22215 /* 60950 */ /*GILLT_v2s64*//*Label 1892*/ GIMT_Encode4(61276),
22216 /* 60954 */ // Label 1885: @60954
22217 /* 60954 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1894*/ GIMT_Encode4(60999), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1562 //
22218 /* 60961 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22219 /* 60964 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22220 /* 60967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22221 /* 60971 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22222 /* 60975 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22223 /* 60979 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4059:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22224 /* 60979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv1i64),
22225 /* 60982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22226 /* 60984 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22227 /* 60986 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22228 /* 60988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22229 /* 60991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22230 /* 60997 */ GIR_RootConstrainSelectedInstOperands,
22231 /* 60998 */ // GIR_Coverage, 1562,
22232 /* 60998 */ GIR_EraseRootFromParent_Done,
22233 /* 60999 */ // Label 1894: @60999
22234 /* 60999 */ GIM_Reject,
22235 /* 61000 */ // Label 1886: @61000
22236 /* 61000 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1895*/ GIMT_Encode4(61045), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1560 //
22237 /* 61007 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22238 /* 61010 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22239 /* 61013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22240 /* 61017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22241 /* 61021 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22242 /* 61025 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4059:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22243 /* 61025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i8),
22244 /* 61028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22245 /* 61030 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22246 /* 61032 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22247 /* 61034 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22248 /* 61037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22249 /* 61043 */ GIR_RootConstrainSelectedInstOperands,
22250 /* 61044 */ // GIR_Coverage, 1560,
22251 /* 61044 */ GIR_EraseRootFromParent_Done,
22252 /* 61045 */ // Label 1895: @61045
22253 /* 61045 */ GIM_Reject,
22254 /* 61046 */ // Label 1887: @61046
22255 /* 61046 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1896*/ GIMT_Encode4(61091), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1561 //
22256 /* 61053 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22257 /* 61056 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22258 /* 61059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22259 /* 61063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22260 /* 61067 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22261 /* 61071 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4059:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22262 /* 61071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv16i8),
22263 /* 61074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22264 /* 61076 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22265 /* 61078 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22266 /* 61080 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22267 /* 61083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22268 /* 61089 */ GIR_RootConstrainSelectedInstOperands,
22269 /* 61090 */ // GIR_Coverage, 1561,
22270 /* 61090 */ GIR_EraseRootFromParent_Done,
22271 /* 61091 */ // Label 1896: @61091
22272 /* 61091 */ GIM_Reject,
22273 /* 61092 */ // Label 1888: @61092
22274 /* 61092 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1897*/ GIMT_Encode4(61137), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1556 //
22275 /* 61099 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22276 /* 61102 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22277 /* 61105 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22278 /* 61109 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22279 /* 61113 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22280 /* 61117 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4059:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22281 /* 61117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i16),
22282 /* 61120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22283 /* 61122 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22284 /* 61124 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22285 /* 61126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22286 /* 61129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22287 /* 61135 */ GIR_RootConstrainSelectedInstOperands,
22288 /* 61136 */ // GIR_Coverage, 1556,
22289 /* 61136 */ GIR_EraseRootFromParent_Done,
22290 /* 61137 */ // Label 1897: @61137
22291 /* 61137 */ GIM_Reject,
22292 /* 61138 */ // Label 1889: @61138
22293 /* 61138 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1898*/ GIMT_Encode4(61183), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1558 //
22294 /* 61145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22295 /* 61148 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22296 /* 61151 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22297 /* 61155 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22298 /* 61159 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22299 /* 61163 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4059:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22300 /* 61163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i16),
22301 /* 61166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22302 /* 61168 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22303 /* 61170 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22304 /* 61172 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22305 /* 61175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22306 /* 61181 */ GIR_RootConstrainSelectedInstOperands,
22307 /* 61182 */ // GIR_Coverage, 1558,
22308 /* 61182 */ GIR_EraseRootFromParent_Done,
22309 /* 61183 */ // Label 1898: @61183
22310 /* 61183 */ GIM_Reject,
22311 /* 61184 */ // Label 1890: @61184
22312 /* 61184 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1899*/ GIMT_Encode4(61229), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1557 //
22313 /* 61191 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22314 /* 61194 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22315 /* 61197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22316 /* 61201 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22317 /* 61205 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22318 /* 61209 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4059:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22319 /* 61209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i32),
22320 /* 61212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22321 /* 61214 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22322 /* 61216 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22323 /* 61218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22324 /* 61221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22325 /* 61227 */ GIR_RootConstrainSelectedInstOperands,
22326 /* 61228 */ // GIR_Coverage, 1557,
22327 /* 61228 */ GIR_EraseRootFromParent_Done,
22328 /* 61229 */ // Label 1899: @61229
22329 /* 61229 */ GIM_Reject,
22330 /* 61230 */ // Label 1891: @61230
22331 /* 61230 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1900*/ GIMT_Encode4(61275), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1559 //
22332 /* 61237 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22333 /* 61240 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22334 /* 61243 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22335 /* 61247 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22336 /* 61251 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22337 /* 61255 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4059:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22338 /* 61255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i32),
22339 /* 61258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22340 /* 61260 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22341 /* 61262 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22342 /* 61264 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22343 /* 61267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22344 /* 61273 */ GIR_RootConstrainSelectedInstOperands,
22345 /* 61274 */ // GIR_Coverage, 1559,
22346 /* 61274 */ GIR_EraseRootFromParent_Done,
22347 /* 61275 */ // Label 1900: @61275
22348 /* 61275 */ GIM_Reject,
22349 /* 61276 */ // Label 1892: @61276
22350 /* 61276 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1901*/ GIMT_Encode4(61321), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1563 //
22351 /* 61283 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22352 /* 61286 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22353 /* 61289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22354 /* 61293 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22355 /* 61297 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22356 /* 61301 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4059:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22357 /* 61301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i64),
22358 /* 61304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22359 /* 61306 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22360 /* 61308 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22361 /* 61310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22362 /* 61313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22363 /* 61319 */ GIR_RootConstrainSelectedInstOperands,
22364 /* 61320 */ // GIR_Coverage, 1563,
22365 /* 61320 */ GIR_EraseRootFromParent_Done,
22366 /* 61321 */ // Label 1901: @61321
22367 /* 61321 */ GIM_Reject,
22368 /* 61322 */ // Label 1893: @61322
22369 /* 61322 */ GIM_Reject,
22370 /* 61323 */ // Label 1884: @61323
22371 /* 61323 */ GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(61761),
22372 /* 61328 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
22373 /* 61333 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1911*/ GIMT_Encode4(61760),
22374 /* 61344 */ /*GILLT_s64*//*Label 1903*/ GIMT_Encode4(61392), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
22375 /* 61364 */ /*GILLT_v8s8*//*Label 1904*/ GIMT_Encode4(61438),
22376 /* 61368 */ /*GILLT_v16s8*//*Label 1905*/ GIMT_Encode4(61484),
22377 /* 61372 */ /*GILLT_v4s16*//*Label 1906*/ GIMT_Encode4(61530),
22378 /* 61376 */ /*GILLT_v8s16*//*Label 1907*/ GIMT_Encode4(61576),
22379 /* 61380 */ /*GILLT_v2s32*//*Label 1908*/ GIMT_Encode4(61622),
22380 /* 61384 */ /*GILLT_v4s32*//*Label 1909*/ GIMT_Encode4(61668),
22381 /* 61388 */ /*GILLT_v2s64*//*Label 1910*/ GIMT_Encode4(61714),
22382 /* 61392 */ // Label 1903: @61392
22383 /* 61392 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1912*/ GIMT_Encode4(61437), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1603 //
22384 /* 61399 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22385 /* 61402 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22386 /* 61405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22387 /* 61409 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22388 /* 61413 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22389 /* 61417 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4052:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22390 /* 61417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv1i64),
22391 /* 61420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22392 /* 61422 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22393 /* 61424 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22394 /* 61426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22395 /* 61429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22396 /* 61435 */ GIR_RootConstrainSelectedInstOperands,
22397 /* 61436 */ // GIR_Coverage, 1603,
22398 /* 61436 */ GIR_EraseRootFromParent_Done,
22399 /* 61437 */ // Label 1912: @61437
22400 /* 61437 */ GIM_Reject,
22401 /* 61438 */ // Label 1904: @61438
22402 /* 61438 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1913*/ GIMT_Encode4(61483), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1601 //
22403 /* 61445 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22404 /* 61448 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22405 /* 61451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22406 /* 61455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22407 /* 61459 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22408 /* 61463 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4052:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22409 /* 61463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i8),
22410 /* 61466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22411 /* 61468 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22412 /* 61470 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22413 /* 61472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22414 /* 61475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22415 /* 61481 */ GIR_RootConstrainSelectedInstOperands,
22416 /* 61482 */ // GIR_Coverage, 1601,
22417 /* 61482 */ GIR_EraseRootFromParent_Done,
22418 /* 61483 */ // Label 1913: @61483
22419 /* 61483 */ GIM_Reject,
22420 /* 61484 */ // Label 1905: @61484
22421 /* 61484 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1914*/ GIMT_Encode4(61529), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1602 //
22422 /* 61491 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22423 /* 61494 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22424 /* 61497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22425 /* 61501 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22426 /* 61505 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22427 /* 61509 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4052:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22428 /* 61509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv16i8),
22429 /* 61512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22430 /* 61514 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22431 /* 61516 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22432 /* 61518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22433 /* 61521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22434 /* 61527 */ GIR_RootConstrainSelectedInstOperands,
22435 /* 61528 */ // GIR_Coverage, 1602,
22436 /* 61528 */ GIR_EraseRootFromParent_Done,
22437 /* 61529 */ // Label 1914: @61529
22438 /* 61529 */ GIM_Reject,
22439 /* 61530 */ // Label 1906: @61530
22440 /* 61530 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1915*/ GIMT_Encode4(61575), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1597 //
22441 /* 61537 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22442 /* 61540 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22443 /* 61543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22444 /* 61547 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22445 /* 61551 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22446 /* 61555 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4052:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22447 /* 61555 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i16),
22448 /* 61558 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22449 /* 61560 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22450 /* 61562 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22451 /* 61564 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22452 /* 61567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22453 /* 61573 */ GIR_RootConstrainSelectedInstOperands,
22454 /* 61574 */ // GIR_Coverage, 1597,
22455 /* 61574 */ GIR_EraseRootFromParent_Done,
22456 /* 61575 */ // Label 1915: @61575
22457 /* 61575 */ GIM_Reject,
22458 /* 61576 */ // Label 1907: @61576
22459 /* 61576 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1916*/ GIMT_Encode4(61621), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1599 //
22460 /* 61583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22461 /* 61586 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22462 /* 61589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22463 /* 61593 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22464 /* 61597 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22465 /* 61601 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4052:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22466 /* 61601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i16),
22467 /* 61604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22468 /* 61606 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22469 /* 61608 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22470 /* 61610 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22471 /* 61613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22472 /* 61619 */ GIR_RootConstrainSelectedInstOperands,
22473 /* 61620 */ // GIR_Coverage, 1599,
22474 /* 61620 */ GIR_EraseRootFromParent_Done,
22475 /* 61621 */ // Label 1916: @61621
22476 /* 61621 */ GIM_Reject,
22477 /* 61622 */ // Label 1908: @61622
22478 /* 61622 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1917*/ GIMT_Encode4(61667), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1598 //
22479 /* 61629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22480 /* 61632 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22481 /* 61635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22482 /* 61639 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22483 /* 61643 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22484 /* 61647 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4052:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22485 /* 61647 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i32),
22486 /* 61650 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22487 /* 61652 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22488 /* 61654 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22489 /* 61656 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22490 /* 61659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22491 /* 61665 */ GIR_RootConstrainSelectedInstOperands,
22492 /* 61666 */ // GIR_Coverage, 1598,
22493 /* 61666 */ GIR_EraseRootFromParent_Done,
22494 /* 61667 */ // Label 1917: @61667
22495 /* 61667 */ GIM_Reject,
22496 /* 61668 */ // Label 1909: @61668
22497 /* 61668 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1918*/ GIMT_Encode4(61713), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1600 //
22498 /* 61675 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22499 /* 61678 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22500 /* 61681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22501 /* 61685 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22502 /* 61689 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22503 /* 61693 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4052:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22504 /* 61693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i32),
22505 /* 61696 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22506 /* 61698 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22507 /* 61700 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22508 /* 61702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22509 /* 61705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22510 /* 61711 */ GIR_RootConstrainSelectedInstOperands,
22511 /* 61712 */ // GIR_Coverage, 1600,
22512 /* 61712 */ GIR_EraseRootFromParent_Done,
22513 /* 61713 */ // Label 1918: @61713
22514 /* 61713 */ GIM_Reject,
22515 /* 61714 */ // Label 1910: @61714
22516 /* 61714 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1919*/ GIMT_Encode4(61759), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1604 //
22517 /* 61721 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22518 /* 61724 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22519 /* 61727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22520 /* 61731 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22521 /* 61735 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22522 /* 61739 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4052:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22523 /* 61739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i64),
22524 /* 61742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22525 /* 61744 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22526 /* 61746 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22527 /* 61748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22528 /* 61751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22529 /* 61757 */ GIR_RootConstrainSelectedInstOperands,
22530 /* 61758 */ // GIR_Coverage, 1604,
22531 /* 61758 */ GIR_EraseRootFromParent_Done,
22532 /* 61759 */ // Label 1919: @61759
22533 /* 61759 */ GIM_Reject,
22534 /* 61760 */ // Label 1911: @61760
22535 /* 61760 */ GIM_Reject,
22536 /* 61761 */ // Label 1902: @61761
22537 /* 61761 */ GIM_Try, /*On fail goto*//*Label 1920*/ GIMT_Encode4(62199),
22538 /* 61766 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
22539 /* 61771 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 1929*/ GIMT_Encode4(62198),
22540 /* 61782 */ /*GILLT_s64*//*Label 1921*/ GIMT_Encode4(61830), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
22541 /* 61802 */ /*GILLT_v8s8*//*Label 1922*/ GIMT_Encode4(61876),
22542 /* 61806 */ /*GILLT_v16s8*//*Label 1923*/ GIMT_Encode4(61922),
22543 /* 61810 */ /*GILLT_v4s16*//*Label 1924*/ GIMT_Encode4(61968),
22544 /* 61814 */ /*GILLT_v8s16*//*Label 1925*/ GIMT_Encode4(62014),
22545 /* 61818 */ /*GILLT_v2s32*//*Label 1926*/ GIMT_Encode4(62060),
22546 /* 61822 */ /*GILLT_v4s32*//*Label 1927*/ GIMT_Encode4(62106),
22547 /* 61826 */ /*GILLT_v2s64*//*Label 1928*/ GIMT_Encode4(62152),
22548 /* 61830 */ // Label 1921: @61830
22549 /* 61830 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1930*/ GIMT_Encode4(61875), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1611 //
22550 /* 61837 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22551 /* 61840 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22552 /* 61843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22553 /* 61847 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22554 /* 61851 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22555 /* 61855 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4053:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22556 /* 61855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv1i64),
22557 /* 61858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22558 /* 61860 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22559 /* 61862 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22560 /* 61864 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22561 /* 61867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22562 /* 61873 */ GIR_RootConstrainSelectedInstOperands,
22563 /* 61874 */ // GIR_Coverage, 1611,
22564 /* 61874 */ GIR_EraseRootFromParent_Done,
22565 /* 61875 */ // Label 1930: @61875
22566 /* 61875 */ GIM_Reject,
22567 /* 61876 */ // Label 1922: @61876
22568 /* 61876 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1931*/ GIMT_Encode4(61921), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1609 //
22569 /* 61883 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22570 /* 61886 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22571 /* 61889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22572 /* 61893 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22573 /* 61897 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22574 /* 61901 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4053:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22575 /* 61901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i8),
22576 /* 61904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22577 /* 61906 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22578 /* 61908 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22579 /* 61910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22580 /* 61913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22581 /* 61919 */ GIR_RootConstrainSelectedInstOperands,
22582 /* 61920 */ // GIR_Coverage, 1609,
22583 /* 61920 */ GIR_EraseRootFromParent_Done,
22584 /* 61921 */ // Label 1931: @61921
22585 /* 61921 */ GIM_Reject,
22586 /* 61922 */ // Label 1923: @61922
22587 /* 61922 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1932*/ GIMT_Encode4(61967), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1610 //
22588 /* 61929 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22589 /* 61932 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22590 /* 61935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22591 /* 61939 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22592 /* 61943 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22593 /* 61947 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4053:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22594 /* 61947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv16i8),
22595 /* 61950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22596 /* 61952 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22597 /* 61954 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22598 /* 61956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22599 /* 61959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22600 /* 61965 */ GIR_RootConstrainSelectedInstOperands,
22601 /* 61966 */ // GIR_Coverage, 1610,
22602 /* 61966 */ GIR_EraseRootFromParent_Done,
22603 /* 61967 */ // Label 1932: @61967
22604 /* 61967 */ GIM_Reject,
22605 /* 61968 */ // Label 1924: @61968
22606 /* 61968 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1933*/ GIMT_Encode4(62013), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1605 //
22607 /* 61975 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22608 /* 61978 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22609 /* 61981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22610 /* 61985 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22611 /* 61989 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22612 /* 61993 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4053:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22613 /* 61993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i16),
22614 /* 61996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22615 /* 61998 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22616 /* 62000 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22617 /* 62002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22618 /* 62005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22619 /* 62011 */ GIR_RootConstrainSelectedInstOperands,
22620 /* 62012 */ // GIR_Coverage, 1605,
22621 /* 62012 */ GIR_EraseRootFromParent_Done,
22622 /* 62013 */ // Label 1933: @62013
22623 /* 62013 */ GIM_Reject,
22624 /* 62014 */ // Label 1925: @62014
22625 /* 62014 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1934*/ GIMT_Encode4(62059), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1607 //
22626 /* 62021 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22627 /* 62024 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22628 /* 62027 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22629 /* 62031 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22630 /* 62035 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22631 /* 62039 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4053:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22632 /* 62039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i16),
22633 /* 62042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22634 /* 62044 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22635 /* 62046 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22636 /* 62048 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22637 /* 62051 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22638 /* 62057 */ GIR_RootConstrainSelectedInstOperands,
22639 /* 62058 */ // GIR_Coverage, 1607,
22640 /* 62058 */ GIR_EraseRootFromParent_Done,
22641 /* 62059 */ // Label 1934: @62059
22642 /* 62059 */ GIM_Reject,
22643 /* 62060 */ // Label 1926: @62060
22644 /* 62060 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1935*/ GIMT_Encode4(62105), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1606 //
22645 /* 62067 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22646 /* 62070 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22647 /* 62073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22648 /* 62077 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22649 /* 62081 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22650 /* 62085 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4053:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22651 /* 62085 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i32),
22652 /* 62088 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22653 /* 62090 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22654 /* 62092 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22655 /* 62094 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22656 /* 62097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22657 /* 62103 */ GIR_RootConstrainSelectedInstOperands,
22658 /* 62104 */ // GIR_Coverage, 1606,
22659 /* 62104 */ GIR_EraseRootFromParent_Done,
22660 /* 62105 */ // Label 1935: @62105
22661 /* 62105 */ GIM_Reject,
22662 /* 62106 */ // Label 1927: @62106
22663 /* 62106 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1936*/ GIMT_Encode4(62151), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1608 //
22664 /* 62113 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22665 /* 62116 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22666 /* 62119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22667 /* 62123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22668 /* 62127 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22669 /* 62131 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4053:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22670 /* 62131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i32),
22671 /* 62134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22672 /* 62136 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22673 /* 62138 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22674 /* 62140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22675 /* 62143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22676 /* 62149 */ GIR_RootConstrainSelectedInstOperands,
22677 /* 62150 */ // GIR_Coverage, 1608,
22678 /* 62150 */ GIR_EraseRootFromParent_Done,
22679 /* 62151 */ // Label 1936: @62151
22680 /* 62151 */ GIM_Reject,
22681 /* 62152 */ // Label 1928: @62152
22682 /* 62152 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1937*/ GIMT_Encode4(62197), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1612 //
22683 /* 62159 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22684 /* 62162 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22685 /* 62165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22686 /* 62169 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22687 /* 62173 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22688 /* 62177 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4053:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22689 /* 62177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i64),
22690 /* 62180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22691 /* 62182 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22692 /* 62184 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22693 /* 62186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22694 /* 62189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22695 /* 62195 */ GIR_RootConstrainSelectedInstOperands,
22696 /* 62196 */ // GIR_Coverage, 1612,
22697 /* 62196 */ GIR_EraseRootFromParent_Done,
22698 /* 62197 */ // Label 1937: @62197
22699 /* 62197 */ GIM_Reject,
22700 /* 62198 */ // Label 1929: @62198
22701 /* 62198 */ GIM_Reject,
22702 /* 62199 */ // Label 1920: @62199
22703 /* 62199 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1938*/ GIMT_Encode4(62243), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1901 //
22704 /* 62206 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesd),
22705 /* 62211 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22706 /* 62214 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22707 /* 62217 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22708 /* 62220 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22709 /* 62224 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22710 /* 62228 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22711 /* 62232 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3954:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESD:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
22712 /* 62232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESD),
22713 /* 62235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22714 /* 62237 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
22715 /* 62239 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22716 /* 62241 */ GIR_RootConstrainSelectedInstOperands,
22717 /* 62242 */ // GIR_Coverage, 1901,
22718 /* 62242 */ GIR_EraseRootFromParent_Done,
22719 /* 62243 */ // Label 1938: @62243
22720 /* 62243 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1939*/ GIMT_Encode4(62287), GIMT_Encode2(GIFBS_HasAES_HasV8), // Rule ID 1902 //
22721 /* 62250 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aese),
22722 /* 62255 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22723 /* 62258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22724 /* 62261 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22725 /* 62264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22726 /* 62268 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22727 /* 62272 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22728 /* 62276 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3955:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESE:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
22729 /* 62276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESE),
22730 /* 62279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22731 /* 62281 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
22732 /* 62283 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22733 /* 62285 */ GIR_RootConstrainSelectedInstOperands,
22734 /* 62286 */ // GIR_Coverage, 1902,
22735 /* 62286 */ GIR_EraseRootFromParent_Done,
22736 /* 62287 */ // Label 1939: @62287
22737 /* 62287 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1940*/ GIMT_Encode4(62331), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1905 //
22738 /* 62294 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su1),
22739 /* 62299 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22740 /* 62302 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22741 /* 62305 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22742 /* 62308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22743 /* 62312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22744 /* 62316 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22745 /* 62320 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3968:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
22746 /* 62320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU1),
22747 /* 62323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22748 /* 62325 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
22749 /* 62327 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22750 /* 62329 */ GIR_RootConstrainSelectedInstOperands,
22751 /* 62330 */ // GIR_Coverage, 1905,
22752 /* 62330 */ GIR_EraseRootFromParent_Done,
22753 /* 62331 */ // Label 1940: @62331
22754 /* 62331 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1941*/ GIMT_Encode4(62375), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1906 //
22755 /* 62338 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su0),
22756 /* 62343 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22757 /* 62346 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22758 /* 62349 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22759 /* 62352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22760 /* 62356 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22761 /* 62360 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22762 /* 62364 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3971:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
22763 /* 62364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU0),
22764 /* 62367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22765 /* 62369 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
22766 /* 62371 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22767 /* 62373 */ GIR_RootConstrainSelectedInstOperands,
22768 /* 62374 */ // GIR_Coverage, 1906,
22769 /* 62374 */ GIR_EraseRootFromParent_Done,
22770 /* 62375 */ // Label 1941: @62375
22771 /* 62375 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1942*/ GIMT_Encode4(62428), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1915 //
22772 /* 62382 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqrshr),
22773 /* 62387 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22774 /* 62390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22775 /* 62393 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22776 /* 62396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
22777 /* 62400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
22778 /* 62404 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
22779 /* 62408 */ // (intrinsic_wo_chain:{ *:[i32] } 3804:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_SQRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
22780 /* 62408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQRSHR),
22781 /* 62411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
22782 /* 62413 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
22783 /* 62415 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
22784 /* 62417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22785 /* 62420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22786 /* 62426 */ GIR_RootConstrainSelectedInstOperands,
22787 /* 62427 */ // GIR_Coverage, 1915,
22788 /* 62427 */ GIR_EraseRootFromParent_Done,
22789 /* 62428 */ // Label 1942: @62428
22790 /* 62428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1943*/ GIMT_Encode4(62481), GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline), // Rule ID 1916 //
22791 /* 62435 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqrshl),
22792 /* 62440 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22793 /* 62443 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22794 /* 62446 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22795 /* 62449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
22796 /* 62453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
22797 /* 62457 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
22798 /* 62461 */ // (intrinsic_wo_chain:{ *:[i32] } 3811:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_UQRSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
22799 /* 62461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQRSHL),
22800 /* 62464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
22801 /* 62466 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
22802 /* 62468 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
22803 /* 62470 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22804 /* 62473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22805 /* 62479 */ GIR_RootConstrainSelectedInstOperands,
22806 /* 62480 */ // GIR_Coverage, 1916,
22807 /* 62480 */ GIR_EraseRootFromParent_Done,
22808 /* 62481 */ // Label 1943: @62481
22809 /* 62481 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1944*/ GIMT_Encode4(62537), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2041 //
22810 /* 62488 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16),
22811 /* 62493 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22812 /* 62496 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22813 /* 62499 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22814 /* 62502 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22815 /* 62506 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22816 /* 62510 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22817 /* 62514 */ // (intrinsic_wo_chain:{ *:[i32] } 4149:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (SXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
22818 /* 62514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB16),
22819 /* 62517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22820 /* 62519 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS
22821 /* 62521 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS
22822 /* 62523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
22823 /* 62526 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22824 /* 62529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22825 /* 62535 */ GIR_RootConstrainSelectedInstOperands,
22826 /* 62536 */ // GIR_Coverage, 2041,
22827 /* 62536 */ GIR_EraseRootFromParent_Done,
22828 /* 62537 */ // Label 1944: @62537
22829 /* 62537 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1945*/ GIMT_Encode4(62593), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2048 //
22830 /* 62544 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16),
22831 /* 62549 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22832 /* 62552 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22833 /* 62555 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22834 /* 62558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22835 /* 62562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22836 /* 62566 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22837 /* 62570 */ // (intrinsic_wo_chain:{ *:[i32] } 4174:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (UXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
22838 /* 62570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB16),
22839 /* 62573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22840 /* 62575 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS
22841 /* 62577 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS
22842 /* 62579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
22843 /* 62582 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22844 /* 62585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22845 /* 62591 */ GIR_RootConstrainSelectedInstOperands,
22846 /* 62592 */ // GIR_Coverage, 2048,
22847 /* 62592 */ GIR_EraseRootFromParent_Done,
22848 /* 62593 */ // Label 1945: @62593
22849 /* 62593 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1946*/ GIMT_Encode4(62646), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2095 //
22850 /* 62600 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad),
22851 /* 62605 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22852 /* 62608 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22853 /* 62611 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22854 /* 62614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22855 /* 62618 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22856 /* 62622 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22857 /* 62626 */ // (intrinsic_wo_chain:{ *:[i32] } 4125:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
22858 /* 62626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUAD),
22859 /* 62629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22860 /* 62631 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
22861 /* 62633 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
22862 /* 62635 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22863 /* 62638 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22864 /* 62644 */ GIR_RootConstrainSelectedInstOperands,
22865 /* 62645 */ // GIR_Coverage, 2095,
22866 /* 62645 */ GIR_EraseRootFromParent_Done,
22867 /* 62646 */ // Label 1946: @62646
22868 /* 62646 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1947*/ GIMT_Encode4(62699), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2096 //
22869 /* 62653 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx),
22870 /* 62658 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22871 /* 62661 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22872 /* 62664 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22873 /* 62667 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22874 /* 62671 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22875 /* 62675 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22876 /* 62679 */ // (intrinsic_wo_chain:{ *:[i32] } 4126:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
22877 /* 62679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUADX),
22878 /* 62682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22879 /* 62684 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
22880 /* 62686 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
22881 /* 62688 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22882 /* 62691 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22883 /* 62697 */ GIR_RootConstrainSelectedInstOperands,
22884 /* 62698 */ // GIR_Coverage, 2096,
22885 /* 62698 */ GIR_EraseRootFromParent_Done,
22886 /* 62699 */ // Label 1947: @62699
22887 /* 62699 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1948*/ GIMT_Encode4(62752), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2097 //
22888 /* 62706 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd),
22889 /* 62711 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22890 /* 62714 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22891 /* 62717 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22892 /* 62720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22893 /* 62724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22894 /* 62728 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22895 /* 62732 */ // (intrinsic_wo_chain:{ *:[i32] } 4133:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
22896 /* 62732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSD),
22897 /* 62735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22898 /* 62737 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
22899 /* 62739 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
22900 /* 62741 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22901 /* 62744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22902 /* 62750 */ GIR_RootConstrainSelectedInstOperands,
22903 /* 62751 */ // GIR_Coverage, 2097,
22904 /* 62751 */ GIR_EraseRootFromParent_Done,
22905 /* 62752 */ // Label 1948: @62752
22906 /* 62752 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1949*/ GIMT_Encode4(62805), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2098 //
22907 /* 62759 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx),
22908 /* 62764 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22909 /* 62767 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22910 /* 62770 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22911 /* 62773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22912 /* 62777 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22913 /* 62781 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
22914 /* 62785 */ // (intrinsic_wo_chain:{ *:[i32] } 4134:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
22915 /* 62785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSDX),
22916 /* 62788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22917 /* 62790 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
22918 /* 62792 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
22919 /* 62794 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22920 /* 62797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22921 /* 62803 */ GIR_RootConstrainSelectedInstOperands,
22922 /* 62804 */ // GIR_Coverage, 2098,
22923 /* 62804 */ GIR_EraseRootFromParent_Done,
22924 /* 62805 */ // Label 1949: @62805
22925 /* 62805 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1950*/ GIMT_Encode4(62858), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2179 //
22926 /* 62812 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb),
22927 /* 62817 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22928 /* 62820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22929 /* 62823 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22930 /* 62826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22931 /* 62830 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22932 /* 62834 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22933 /* 62838 */ // (intrinsic_wo_chain:{ *:[i32] } 4127:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
22934 /* 62838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB),
22935 /* 62841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22936 /* 62843 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
22937 /* 62845 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
22938 /* 62847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22939 /* 62850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22940 /* 62856 */ GIR_RootConstrainSelectedInstOperands,
22941 /* 62857 */ // GIR_Coverage, 2179,
22942 /* 62857 */ GIR_EraseRootFromParent_Done,
22943 /* 62858 */ // Label 1950: @62858
22944 /* 62858 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1951*/ GIMT_Encode4(62911), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2180 //
22945 /* 62865 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt),
22946 /* 62870 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22947 /* 62873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22948 /* 62876 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22949 /* 62879 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22950 /* 62883 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22951 /* 62887 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22952 /* 62891 */ // (intrinsic_wo_chain:{ *:[i32] } 4128:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
22953 /* 62891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT),
22954 /* 62894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22955 /* 62896 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
22956 /* 62898 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
22957 /* 62900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22958 /* 62903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22959 /* 62909 */ GIR_RootConstrainSelectedInstOperands,
22960 /* 62910 */ // GIR_Coverage, 2180,
22961 /* 62910 */ GIR_EraseRootFromParent_Done,
22962 /* 62911 */ // Label 1951: @62911
22963 /* 62911 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1952*/ GIMT_Encode4(62964), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2181 //
22964 /* 62918 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb),
22965 /* 62923 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22966 /* 62926 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22967 /* 62929 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22968 /* 62932 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22969 /* 62936 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22970 /* 62940 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22971 /* 62944 */ // (intrinsic_wo_chain:{ *:[i32] } 4129:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
22972 /* 62944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB),
22973 /* 62947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22974 /* 62949 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
22975 /* 62951 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
22976 /* 62953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22977 /* 62956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22978 /* 62962 */ GIR_RootConstrainSelectedInstOperands,
22979 /* 62963 */ // GIR_Coverage, 2181,
22980 /* 62963 */ GIR_EraseRootFromParent_Done,
22981 /* 62964 */ // Label 1952: @62964
22982 /* 62964 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1953*/ GIMT_Encode4(63017), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2182 //
22983 /* 62971 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt),
22984 /* 62976 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
22985 /* 62979 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
22986 /* 62982 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
22987 /* 62985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22988 /* 62989 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22989 /* 62993 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
22990 /* 62997 */ // (intrinsic_wo_chain:{ *:[i32] } 4130:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
22991 /* 62997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT),
22992 /* 63000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
22993 /* 63002 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
22994 /* 63004 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
22995 /* 63006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22996 /* 63009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22997 /* 63015 */ GIR_RootConstrainSelectedInstOperands,
22998 /* 63016 */ // GIR_Coverage, 2182,
22999 /* 63016 */ GIR_EraseRootFromParent_Done,
23000 /* 63017 */ // Label 1953: @63017
23001 /* 63017 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1954*/ GIMT_Encode4(63070), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2183 //
23002 /* 63024 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb),
23003 /* 63029 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23004 /* 63032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23005 /* 63035 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23006 /* 63038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23007 /* 63042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23008 /* 63046 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23009 /* 63050 */ // (intrinsic_wo_chain:{ *:[i32] } 4131:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23010 /* 63050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWB),
23011 /* 63053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23012 /* 63055 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23013 /* 63057 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23014 /* 63059 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23015 /* 63062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23016 /* 63068 */ GIR_RootConstrainSelectedInstOperands,
23017 /* 63069 */ // GIR_Coverage, 2183,
23018 /* 63069 */ GIR_EraseRootFromParent_Done,
23019 /* 63070 */ // Label 1954: @63070
23020 /* 63070 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1955*/ GIMT_Encode4(63123), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2184 //
23021 /* 63077 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt),
23022 /* 63082 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23023 /* 63085 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23024 /* 63088 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23025 /* 63091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23026 /* 63095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23027 /* 63099 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23028 /* 63103 */ // (intrinsic_wo_chain:{ *:[i32] } 4132:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23029 /* 63103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWT),
23030 /* 63106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23031 /* 63108 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23032 /* 63110 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23033 /* 63112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23034 /* 63115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23035 /* 63121 */ GIR_RootConstrainSelectedInstOperands,
23036 /* 63122 */ // GIR_Coverage, 2184,
23037 /* 63122 */ GIR_EraseRootFromParent_Done,
23038 /* 63123 */ // Label 1955: @63123
23039 /* 63123 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1956*/ GIMT_Encode4(63179), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2296 //
23040 /* 63130 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16),
23041 /* 63135 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23042 /* 63138 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23043 /* 63141 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23044 /* 63144 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23045 /* 63148 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23046 /* 63152 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23047 /* 63156 */ // (intrinsic_wo_chain:{ *:[i32] } 4149:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
23048 /* 63156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB16),
23049 /* 63159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23050 /* 63161 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23051 /* 63163 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23052 /* 63165 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23053 /* 63168 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23054 /* 63171 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23055 /* 63177 */ GIR_RootConstrainSelectedInstOperands,
23056 /* 63178 */ // GIR_Coverage, 2296,
23057 /* 63178 */ GIR_EraseRootFromParent_Done,
23058 /* 63179 */ // Label 1956: @63179
23059 /* 63179 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1957*/ GIMT_Encode4(63232), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2326 //
23060 /* 63186 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
23061 /* 63191 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23062 /* 63194 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23063 /* 63197 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23064 /* 63200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23065 /* 63204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23066 /* 63208 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23067 /* 63212 */ // (intrinsic_wo_chain:{ *:[i32] } 4092:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
23068 /* 63212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD),
23069 /* 63215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23070 /* 63217 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
23071 /* 63219 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
23072 /* 63221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23073 /* 63224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23074 /* 63230 */ GIR_RootConstrainSelectedInstOperands,
23075 /* 63231 */ // GIR_Coverage, 2326,
23076 /* 63231 */ GIR_EraseRootFromParent_Done,
23077 /* 63232 */ // Label 1957: @63232
23078 /* 63232 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1958*/ GIMT_Encode4(63285), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2327 //
23079 /* 63239 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
23080 /* 63244 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23081 /* 63247 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23082 /* 63250 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23083 /* 63253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23084 /* 63257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23085 /* 63261 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23086 /* 63265 */ // (intrinsic_wo_chain:{ *:[i32] } 4097:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
23087 /* 63265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB),
23088 /* 63268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23089 /* 63270 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
23090 /* 63272 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
23091 /* 63274 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23092 /* 63277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23093 /* 63283 */ GIR_RootConstrainSelectedInstOperands,
23094 /* 63284 */ // GIR_Coverage, 2327,
23095 /* 63284 */ GIR_EraseRootFromParent_Done,
23096 /* 63285 */ // Label 1958: @63285
23097 /* 63285 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1959*/ GIMT_Encode4(63338), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2367 //
23098 /* 63292 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb),
23099 /* 63297 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23100 /* 63300 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23101 /* 63303 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23102 /* 63306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23103 /* 63310 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23104 /* 63314 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23105 /* 63318 */ // (intrinsic_wo_chain:{ *:[i32] } 4127:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23106 /* 63318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB),
23107 /* 63321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23108 /* 63323 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23109 /* 63325 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23110 /* 63327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23111 /* 63330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23112 /* 63336 */ GIR_RootConstrainSelectedInstOperands,
23113 /* 63337 */ // GIR_Coverage, 2367,
23114 /* 63337 */ GIR_EraseRootFromParent_Done,
23115 /* 63338 */ // Label 1959: @63338
23116 /* 63338 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1960*/ GIMT_Encode4(63391), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2368 //
23117 /* 63345 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt),
23118 /* 63350 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23119 /* 63353 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23120 /* 63356 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23121 /* 63359 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23122 /* 63363 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23123 /* 63367 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23124 /* 63371 */ // (intrinsic_wo_chain:{ *:[i32] } 4128:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23125 /* 63371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT),
23126 /* 63374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23127 /* 63376 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23128 /* 63378 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23129 /* 63380 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23130 /* 63383 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23131 /* 63389 */ GIR_RootConstrainSelectedInstOperands,
23132 /* 63390 */ // GIR_Coverage, 2368,
23133 /* 63390 */ GIR_EraseRootFromParent_Done,
23134 /* 63391 */ // Label 1960: @63391
23135 /* 63391 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1961*/ GIMT_Encode4(63444), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2369 //
23136 /* 63398 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb),
23137 /* 63403 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23138 /* 63406 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23139 /* 63409 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23140 /* 63412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23141 /* 63416 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23142 /* 63420 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23143 /* 63424 */ // (intrinsic_wo_chain:{ *:[i32] } 4129:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23144 /* 63424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB),
23145 /* 63427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23146 /* 63429 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23147 /* 63431 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23148 /* 63433 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23149 /* 63436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23150 /* 63442 */ GIR_RootConstrainSelectedInstOperands,
23151 /* 63443 */ // GIR_Coverage, 2369,
23152 /* 63443 */ GIR_EraseRootFromParent_Done,
23153 /* 63444 */ // Label 1961: @63444
23154 /* 63444 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1962*/ GIMT_Encode4(63497), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2370 //
23155 /* 63451 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt),
23156 /* 63456 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23157 /* 63459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23158 /* 63462 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23159 /* 63465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23160 /* 63469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23161 /* 63473 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23162 /* 63477 */ // (intrinsic_wo_chain:{ *:[i32] } 4130:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23163 /* 63477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT),
23164 /* 63480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23165 /* 63482 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23166 /* 63484 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23167 /* 63486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23168 /* 63489 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23169 /* 63495 */ GIR_RootConstrainSelectedInstOperands,
23170 /* 63496 */ // GIR_Coverage, 2370,
23171 /* 63496 */ GIR_EraseRootFromParent_Done,
23172 /* 63497 */ // Label 1962: @63497
23173 /* 63497 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1963*/ GIMT_Encode4(63550), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2371 //
23174 /* 63504 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb),
23175 /* 63509 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23176 /* 63512 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23177 /* 63515 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23178 /* 63518 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23179 /* 63522 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23180 /* 63526 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23181 /* 63530 */ // (intrinsic_wo_chain:{ *:[i32] } 4131:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23182 /* 63530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWB),
23183 /* 63533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23184 /* 63535 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23185 /* 63537 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23186 /* 63539 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23187 /* 63542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23188 /* 63548 */ GIR_RootConstrainSelectedInstOperands,
23189 /* 63549 */ // GIR_Coverage, 2371,
23190 /* 63549 */ GIR_EraseRootFromParent_Done,
23191 /* 63550 */ // Label 1963: @63550
23192 /* 63550 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1964*/ GIMT_Encode4(63603), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2372 //
23193 /* 63557 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt),
23194 /* 63562 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23195 /* 63565 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23196 /* 63568 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23197 /* 63571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23198 /* 63575 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23199 /* 63579 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23200 /* 63583 */ // (intrinsic_wo_chain:{ *:[i32] } 4132:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
23201 /* 63583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWT),
23202 /* 63586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23203 /* 63588 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23204 /* 63590 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23205 /* 63592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23206 /* 63595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23207 /* 63601 */ GIR_RootConstrainSelectedInstOperands,
23208 /* 63602 */ // GIR_Coverage, 2372,
23209 /* 63602 */ GIR_EraseRootFromParent_Done,
23210 /* 63603 */ // Label 1964: @63603
23211 /* 63603 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1965*/ GIMT_Encode4(63650), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2902 //
23212 /* 63610 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
23213 /* 63615 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
23214 /* 63618 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
23215 /* 63621 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
23216 /* 63624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23217 /* 63628 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23218 /* 63632 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23219 /* 63636 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3985:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 0:{ *:[i32] })
23220 /* 63636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16),
23221 /* 63639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23222 /* 63641 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23223 /* 63643 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23224 /* 63645 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23225 /* 63648 */ GIR_RootConstrainSelectedInstOperands,
23226 /* 63649 */ // GIR_Coverage, 2902,
23227 /* 63649 */ GIR_EraseRootFromParent_Done,
23228 /* 63650 */ // Label 1965: @63650
23229 /* 63650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1966*/ GIMT_Encode4(63697), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2903 //
23230 /* 63657 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
23231 /* 63662 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
23232 /* 63665 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
23233 /* 63668 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
23234 /* 63671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23235 /* 63675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23236 /* 63679 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23237 /* 63683 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3984:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 1:{ *:[i32] })
23238 /* 63683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16),
23239 /* 63686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23240 /* 63688 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23241 /* 63690 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23242 /* 63692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
23243 /* 63695 */ GIR_RootConstrainSelectedInstOperands,
23244 /* 63696 */ // GIR_Coverage, 2903,
23245 /* 63696 */ GIR_EraseRootFromParent_Done,
23246 /* 63697 */ // Label 1966: @63697
23247 /* 63697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1967*/ GIMT_Encode4(63744), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2904 //
23248 /* 63704 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
23249 /* 63709 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23250 /* 63712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23251 /* 63715 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23252 /* 63718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23253 /* 63722 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23254 /* 63726 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23255 /* 63730 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3985:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 0:{ *:[i32] })
23256 /* 63730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16),
23257 /* 63733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23258 /* 63735 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23259 /* 63737 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23260 /* 63739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23261 /* 63742 */ GIR_RootConstrainSelectedInstOperands,
23262 /* 63743 */ // GIR_Coverage, 2904,
23263 /* 63743 */ GIR_EraseRootFromParent_Done,
23264 /* 63744 */ // Label 1967: @63744
23265 /* 63744 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1968*/ GIMT_Encode4(63791), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a), // Rule ID 2905 //
23266 /* 63751 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
23267 /* 63756 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23268 /* 63759 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23269 /* 63762 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23270 /* 63765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23271 /* 63769 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23272 /* 63773 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23273 /* 63777 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3984:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 1:{ *:[i32] })
23274 /* 63777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16),
23275 /* 63780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23276 /* 63782 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23277 /* 63784 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23278 /* 63786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
23279 /* 63789 */ GIR_RootConstrainSelectedInstOperands,
23280 /* 63790 */ // GIR_Coverage, 2905,
23281 /* 63790 */ GIR_EraseRootFromParent_Done,
23282 /* 63791 */ // Label 1968: @63791
23283 /* 63791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1969*/ GIMT_Encode4(63838), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2906 //
23284 /* 63798 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
23285 /* 63803 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
23286 /* 63806 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
23287 /* 63809 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
23288 /* 63812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23289 /* 63816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23290 /* 63820 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23291 /* 63824 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3985:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 0:{ *:[i32] })
23292 /* 63824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32),
23293 /* 63827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23294 /* 63829 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23295 /* 63831 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23296 /* 63833 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23297 /* 63836 */ GIR_RootConstrainSelectedInstOperands,
23298 /* 63837 */ // GIR_Coverage, 2906,
23299 /* 63837 */ GIR_EraseRootFromParent_Done,
23300 /* 63838 */ // Label 1969: @63838
23301 /* 63838 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1970*/ GIMT_Encode4(63885), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2907 //
23302 /* 63845 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
23303 /* 63850 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
23304 /* 63853 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
23305 /* 63856 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
23306 /* 63859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23307 /* 63863 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23308 /* 63867 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23309 /* 63871 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3984:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 1:{ *:[i32] })
23310 /* 63871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32),
23311 /* 63874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23312 /* 63876 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23313 /* 63878 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23314 /* 63880 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
23315 /* 63883 */ GIR_RootConstrainSelectedInstOperands,
23316 /* 63884 */ // GIR_Coverage, 2907,
23317 /* 63884 */ GIR_EraseRootFromParent_Done,
23318 /* 63885 */ // Label 1970: @63885
23319 /* 63885 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1971*/ GIMT_Encode4(63932), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2908 //
23320 /* 63892 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
23321 /* 63897 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23322 /* 63900 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23323 /* 63903 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23324 /* 63906 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23325 /* 63910 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23326 /* 63914 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23327 /* 63918 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3985:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 0:{ *:[i32] })
23328 /* 63918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32),
23329 /* 63921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23330 /* 63923 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23331 /* 63925 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23332 /* 63927 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23333 /* 63930 */ GIR_RootConstrainSelectedInstOperands,
23334 /* 63931 */ // GIR_Coverage, 2908,
23335 /* 63931 */ GIR_EraseRootFromParent_Done,
23336 /* 63932 */ // Label 1971: @63932
23337 /* 63932 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1972*/ GIMT_Encode4(63979), GIMT_Encode2(GIFBS_HasNEON_HasV8_3a), // Rule ID 2909 //
23338 /* 63939 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
23339 /* 63944 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23340 /* 63947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23341 /* 63950 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23342 /* 63953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23343 /* 63957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23344 /* 63961 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23345 /* 63965 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3984:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 1:{ *:[i32] })
23346 /* 63965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32),
23347 /* 63968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23348 /* 63970 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23349 /* 63972 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23350 /* 63974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
23351 /* 63977 */ GIR_RootConstrainSelectedInstOperands,
23352 /* 63978 */ // GIR_Coverage, 2909,
23353 /* 63978 */ GIR_EraseRootFromParent_Done,
23354 /* 63979 */ // Label 1972: @63979
23355 /* 63979 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1973*/ GIMT_Encode4(64053), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3420 //
23356 /* 63986 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm),
23357 /* 63991 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23358 /* 63994 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23359 /* 63997 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23360 /* 64000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23361 /* 64004 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23362 /* 64008 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23363 /* 64012 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3872:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
23364 /* 64012 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23365 /* 64015 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23366 /* 64019 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23367 /* 64024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32),
23368 /* 64027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23369 /* 64029 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23370 /* 64031 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23371 /* 64033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23372 /* 64036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23373 /* 64042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23374 /* 64048 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23375 /* 64051 */ GIR_RootConstrainSelectedInstOperands,
23376 /* 64052 */ // GIR_Coverage, 3420,
23377 /* 64052 */ GIR_EraseRootFromParent_Done,
23378 /* 64053 */ // Label 1973: @64053
23379 /* 64053 */ GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(64277),
23380 /* 64058 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv),
23381 /* 64063 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1977*/ GIMT_Encode4(64276),
23382 /* 64074 */ /*GILLT_s16*//*Label 1975*/ GIMT_Encode4(64082),
23383 /* 64078 */ /*GILLT_s32*//*Label 1976*/ GIMT_Encode4(64179),
23384 /* 64082 */ // Label 1975: @64082
23385 /* 64082 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1978*/ GIMT_Encode4(64178), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3498 //
23386 /* 64089 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
23387 /* 64092 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23388 /* 64095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23389 /* 64099 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23390 /* 64103 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23391 /* 64107 */ // (intrinsic_wo_chain:{ *:[f16] } 3780:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23392 /* 64107 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23393 /* 64110 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23394 /* 64114 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23395 /* 64119 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23396 /* 64123 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23397 /* 64128 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23398 /* 64131 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf16),
23399 /* 64135 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23400 /* 64140 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23401 /* 64143 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23402 /* 64147 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23403 /* 64150 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23404 /* 64156 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23405 /* 64162 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23406 /* 64164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23407 /* 64167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23408 /* 64169 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23409 /* 64172 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
23410 /* 64177 */ // GIR_Coverage, 3498,
23411 /* 64177 */ GIR_EraseRootFromParent_Done,
23412 /* 64178 */ // Label 1978: @64178
23413 /* 64178 */ GIM_Reject,
23414 /* 64179 */ // Label 1976: @64179
23415 /* 64179 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1979*/ GIMT_Encode4(64275), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3496 //
23416 /* 64186 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23417 /* 64189 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23418 /* 64192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23419 /* 64196 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23420 /* 64200 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23421 /* 64204 */ // (intrinsic_wo_chain:{ *:[f32] } 3780:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23422 /* 64204 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23423 /* 64207 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23424 /* 64211 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23425 /* 64216 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23426 /* 64220 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23427 /* 64225 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23428 /* 64228 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf32),
23429 /* 64232 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23430 /* 64237 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23431 /* 64240 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23432 /* 64244 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23433 /* 64247 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23434 /* 64253 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23435 /* 64259 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23436 /* 64261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23437 /* 64264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23438 /* 64266 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23439 /* 64269 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
23440 /* 64274 */ // GIR_Coverage, 3496,
23441 /* 64274 */ GIR_EraseRootFromParent_Done,
23442 /* 64275 */ // Label 1979: @64275
23443 /* 64275 */ GIM_Reject,
23444 /* 64276 */ // Label 1977: @64276
23445 /* 64276 */ GIM_Reject,
23446 /* 64277 */ // Label 1974: @64277
23447 /* 64277 */ GIM_Try, /*On fail goto*//*Label 1980*/ GIMT_Encode4(64501),
23448 /* 64282 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv),
23449 /* 64287 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1983*/ GIMT_Encode4(64500),
23450 /* 64298 */ /*GILLT_s16*//*Label 1981*/ GIMT_Encode4(64306),
23451 /* 64302 */ /*GILLT_s32*//*Label 1982*/ GIMT_Encode4(64403),
23452 /* 64306 */ // Label 1981: @64306
23453 /* 64306 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1984*/ GIMT_Encode4(64402), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3502 //
23454 /* 64313 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
23455 /* 64316 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23456 /* 64319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23457 /* 64323 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23458 /* 64327 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23459 /* 64331 */ // (intrinsic_wo_chain:{ *:[f16] } 3771:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23460 /* 64331 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23461 /* 64334 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23462 /* 64338 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23463 /* 64343 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23464 /* 64347 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23465 /* 64352 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23466 /* 64355 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf16),
23467 /* 64359 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23468 /* 64364 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23469 /* 64367 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23470 /* 64371 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23471 /* 64374 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23472 /* 64380 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23473 /* 64386 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23474 /* 64388 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23475 /* 64391 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23476 /* 64393 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23477 /* 64396 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
23478 /* 64401 */ // GIR_Coverage, 3502,
23479 /* 64401 */ GIR_EraseRootFromParent_Done,
23480 /* 64402 */ // Label 1984: @64402
23481 /* 64402 */ GIM_Reject,
23482 /* 64403 */ // Label 1982: @64403
23483 /* 64403 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1985*/ GIMT_Encode4(64499), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3500 //
23484 /* 64410 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23485 /* 64413 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23486 /* 64416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23487 /* 64420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23488 /* 64424 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23489 /* 64428 */ // (intrinsic_wo_chain:{ *:[f32] } 3771:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23490 /* 64428 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23491 /* 64431 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23492 /* 64435 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23493 /* 64440 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23494 /* 64444 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23495 /* 64449 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23496 /* 64452 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf32),
23497 /* 64456 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23498 /* 64461 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23499 /* 64464 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23500 /* 64468 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23501 /* 64471 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23502 /* 64477 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23503 /* 64483 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23504 /* 64485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23505 /* 64488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23506 /* 64490 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23507 /* 64493 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
23508 /* 64498 */ // GIR_Coverage, 3500,
23509 /* 64498 */ GIR_EraseRootFromParent_Done,
23510 /* 64499 */ // Label 1985: @64499
23511 /* 64499 */ GIM_Reject,
23512 /* 64500 */ // Label 1983: @64500
23513 /* 64500 */ GIM_Reject,
23514 /* 64501 */ // Label 1980: @64501
23515 /* 64501 */ GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(64725),
23516 /* 64506 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav),
23517 /* 64511 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1989*/ GIMT_Encode4(64724),
23518 /* 64522 */ /*GILLT_s16*//*Label 1987*/ GIMT_Encode4(64530),
23519 /* 64526 */ /*GILLT_s32*//*Label 1988*/ GIMT_Encode4(64627),
23520 /* 64530 */ // Label 1987: @64530
23521 /* 64530 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1990*/ GIMT_Encode4(64626), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3506 //
23522 /* 64537 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
23523 /* 64540 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23524 /* 64543 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23525 /* 64547 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23526 /* 64551 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23527 /* 64555 */ // (intrinsic_wo_chain:{ *:[f16] } 3778:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23528 /* 64555 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23529 /* 64558 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23530 /* 64562 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23531 /* 64567 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23532 /* 64571 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23533 /* 64576 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23534 /* 64579 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf16),
23535 /* 64583 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23536 /* 64588 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23537 /* 64591 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23538 /* 64595 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23539 /* 64598 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23540 /* 64604 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23541 /* 64610 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23542 /* 64612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23543 /* 64615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23544 /* 64617 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23545 /* 64620 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
23546 /* 64625 */ // GIR_Coverage, 3506,
23547 /* 64625 */ GIR_EraseRootFromParent_Done,
23548 /* 64626 */ // Label 1990: @64626
23549 /* 64626 */ GIM_Reject,
23550 /* 64627 */ // Label 1988: @64627
23551 /* 64627 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1991*/ GIMT_Encode4(64723), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3504 //
23552 /* 64634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23553 /* 64637 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23554 /* 64640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23555 /* 64644 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23556 /* 64648 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23557 /* 64652 */ // (intrinsic_wo_chain:{ *:[f32] } 3778:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23558 /* 64652 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23559 /* 64655 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23560 /* 64659 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23561 /* 64664 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23562 /* 64668 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23563 /* 64673 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23564 /* 64676 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf32),
23565 /* 64680 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23566 /* 64685 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23567 /* 64688 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23568 /* 64692 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23569 /* 64695 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23570 /* 64701 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23571 /* 64707 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23572 /* 64709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23573 /* 64712 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23574 /* 64714 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23575 /* 64717 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
23576 /* 64722 */ // GIR_Coverage, 3504,
23577 /* 64722 */ GIR_EraseRootFromParent_Done,
23578 /* 64723 */ // Label 1991: @64723
23579 /* 64723 */ GIM_Reject,
23580 /* 64724 */ // Label 1989: @64724
23581 /* 64724 */ GIM_Reject,
23582 /* 64725 */ // Label 1986: @64725
23583 /* 64725 */ GIM_Try, /*On fail goto*//*Label 1992*/ GIMT_Encode4(64949),
23584 /* 64730 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav),
23585 /* 64735 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 1995*/ GIMT_Encode4(64948),
23586 /* 64746 */ /*GILLT_s16*//*Label 1993*/ GIMT_Encode4(64754),
23587 /* 64750 */ /*GILLT_s32*//*Label 1994*/ GIMT_Encode4(64851),
23588 /* 64754 */ // Label 1993: @64754
23589 /* 64754 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1996*/ GIMT_Encode4(64850), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3510 //
23590 /* 64761 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
23591 /* 64764 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23592 /* 64767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23593 /* 64771 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
23594 /* 64775 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23595 /* 64779 */ // (intrinsic_wo_chain:{ *:[f16] } 3769:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
23596 /* 64779 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23597 /* 64782 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23598 /* 64786 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23599 /* 64791 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23600 /* 64795 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23601 /* 64800 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23602 /* 64803 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf16),
23603 /* 64807 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23604 /* 64812 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23605 /* 64815 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23606 /* 64819 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23607 /* 64822 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23608 /* 64828 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23609 /* 64834 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23610 /* 64836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23611 /* 64839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23612 /* 64841 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23613 /* 64844 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
23614 /* 64849 */ // GIR_Coverage, 3510,
23615 /* 64849 */ GIR_EraseRootFromParent_Done,
23616 /* 64850 */ // Label 1996: @64850
23617 /* 64850 */ GIM_Reject,
23618 /* 64851 */ // Label 1994: @64851
23619 /* 64851 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 1997*/ GIMT_Encode4(64947), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3508 //
23620 /* 64858 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23621 /* 64861 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23622 /* 64864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23623 /* 64868 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
23624 /* 64872 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23625 /* 64876 */ // (intrinsic_wo_chain:{ *:[f32] } 3769:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
23626 /* 64876 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
23627 /* 64879 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23628 /* 64883 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23629 /* 64888 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
23630 /* 64892 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
23631 /* 64897 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
23632 /* 64900 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf32),
23633 /* 64904 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23634 /* 64909 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
23635 /* 64912 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
23636 /* 64916 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
23637 /* 64919 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23638 /* 64925 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23639 /* 64931 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
23640 /* 64933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
23641 /* 64936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
23642 /* 64938 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23643 /* 64941 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
23644 /* 64946 */ // GIR_Coverage, 3508,
23645 /* 64946 */ GIR_EraseRootFromParent_Done,
23646 /* 64947 */ // Label 1997: @64947
23647 /* 64947 */ GIM_Reject,
23648 /* 64948 */ // Label 1995: @64948
23649 /* 64948 */ GIM_Reject,
23650 /* 64949 */ // Label 1992: @64949
23651 /* 64949 */ GIM_Try, /*On fail goto*//*Label 1998*/ GIMT_Encode4(65135),
23652 /* 64954 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav),
23653 /* 64959 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23654 /* 64962 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23655 /* 64965 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2002*/ GIMT_Encode4(65134),
23656 /* 64976 */ /*GILLT_v16s8*//*Label 1999*/ GIMT_Encode4(64996), GIMT_Encode4(0),
23657 /* 64984 */ /*GILLT_v8s16*//*Label 2000*/ GIMT_Encode4(65042), GIMT_Encode4(0),
23658 /* 64992 */ /*GILLT_v4s32*//*Label 2001*/ GIMT_Encode4(65088),
23659 /* 64996 */ // Label 1999: @64996
23660 /* 64996 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2003*/ GIMT_Encode4(65041), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3560 //
23661 /* 65003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23662 /* 65007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23663 /* 65011 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23664 /* 65015 */ // (intrinsic_wo_chain:{ *:[i32] } 3776:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMINAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
23665 /* 65015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs8),
23666 /* 65018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23667 /* 65020 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
23668 /* 65022 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
23669 /* 65024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23670 /* 65027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23671 /* 65033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23672 /* 65039 */ GIR_RootConstrainSelectedInstOperands,
23673 /* 65040 */ // GIR_Coverage, 3560,
23674 /* 65040 */ GIR_EraseRootFromParent_Done,
23675 /* 65041 */ // Label 2003: @65041
23676 /* 65041 */ GIM_Reject,
23677 /* 65042 */ // Label 2000: @65042
23678 /* 65042 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2004*/ GIMT_Encode4(65087), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3562 //
23679 /* 65049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23680 /* 65053 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23681 /* 65057 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23682 /* 65061 */ // (intrinsic_wo_chain:{ *:[i32] } 3776:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMINAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
23683 /* 65061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs16),
23684 /* 65064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23685 /* 65066 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
23686 /* 65068 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
23687 /* 65070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23688 /* 65073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23689 /* 65079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23690 /* 65085 */ GIR_RootConstrainSelectedInstOperands,
23691 /* 65086 */ // GIR_Coverage, 3562,
23692 /* 65086 */ GIR_EraseRootFromParent_Done,
23693 /* 65087 */ // Label 2004: @65087
23694 /* 65087 */ GIM_Reject,
23695 /* 65088 */ // Label 2001: @65088
23696 /* 65088 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2005*/ GIMT_Encode4(65133), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3564 //
23697 /* 65095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23698 /* 65099 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23699 /* 65103 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23700 /* 65107 */ // (intrinsic_wo_chain:{ *:[i32] } 3776:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMINAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
23701 /* 65107 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs32),
23702 /* 65110 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23703 /* 65112 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
23704 /* 65114 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
23705 /* 65116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23706 /* 65119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23707 /* 65125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23708 /* 65131 */ GIR_RootConstrainSelectedInstOperands,
23709 /* 65132 */ // GIR_Coverage, 3564,
23710 /* 65132 */ GIR_EraseRootFromParent_Done,
23711 /* 65133 */ // Label 2005: @65133
23712 /* 65133 */ GIM_Reject,
23713 /* 65134 */ // Label 2002: @65134
23714 /* 65134 */ GIM_Reject,
23715 /* 65135 */ // Label 1998: @65135
23716 /* 65135 */ GIM_Try, /*On fail goto*//*Label 2006*/ GIMT_Encode4(65321),
23717 /* 65140 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav),
23718 /* 65145 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23719 /* 65148 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23720 /* 65151 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2010*/ GIMT_Encode4(65320),
23721 /* 65162 */ /*GILLT_v16s8*//*Label 2007*/ GIMT_Encode4(65182), GIMT_Encode4(0),
23722 /* 65170 */ /*GILLT_v8s16*//*Label 2008*/ GIMT_Encode4(65228), GIMT_Encode4(0),
23723 /* 65178 */ /*GILLT_v4s32*//*Label 2009*/ GIMT_Encode4(65274),
23724 /* 65182 */ // Label 2007: @65182
23725 /* 65182 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2011*/ GIMT_Encode4(65227), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3566 //
23726 /* 65189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23727 /* 65193 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23728 /* 65197 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23729 /* 65201 */ // (intrinsic_wo_chain:{ *:[i32] } 3767:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMAXAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
23730 /* 65201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs8),
23731 /* 65204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23732 /* 65206 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
23733 /* 65208 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
23734 /* 65210 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23735 /* 65213 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23736 /* 65219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23737 /* 65225 */ GIR_RootConstrainSelectedInstOperands,
23738 /* 65226 */ // GIR_Coverage, 3566,
23739 /* 65226 */ GIR_EraseRootFromParent_Done,
23740 /* 65227 */ // Label 2011: @65227
23741 /* 65227 */ GIM_Reject,
23742 /* 65228 */ // Label 2008: @65228
23743 /* 65228 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2012*/ GIMT_Encode4(65273), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3568 //
23744 /* 65235 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23745 /* 65239 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23746 /* 65243 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23747 /* 65247 */ // (intrinsic_wo_chain:{ *:[i32] } 3767:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMAXAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
23748 /* 65247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs16),
23749 /* 65250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23750 /* 65252 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
23751 /* 65254 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
23752 /* 65256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23753 /* 65259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23754 /* 65265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23755 /* 65271 */ GIR_RootConstrainSelectedInstOperands,
23756 /* 65272 */ // GIR_Coverage, 3568,
23757 /* 65272 */ GIR_EraseRootFromParent_Done,
23758 /* 65273 */ // Label 2012: @65273
23759 /* 65273 */ GIM_Reject,
23760 /* 65274 */ // Label 2009: @65274
23761 /* 65274 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2013*/ GIMT_Encode4(65319), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3570 //
23762 /* 65281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23763 /* 65285 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23764 /* 65289 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23765 /* 65293 */ // (intrinsic_wo_chain:{ *:[i32] } 3767:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMAXAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
23766 /* 65293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs32),
23767 /* 65296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23768 /* 65298 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
23769 /* 65300 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
23770 /* 65302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23771 /* 65305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23772 /* 65311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23773 /* 65317 */ GIR_RootConstrainSelectedInstOperands,
23774 /* 65318 */ // GIR_Coverage, 3570,
23775 /* 65318 */ GIR_EraseRootFromParent_Done,
23776 /* 65319 */ // Label 2013: @65319
23777 /* 65319 */ GIM_Reject,
23778 /* 65320 */ // Label 2010: @65320
23779 /* 65320 */ GIM_Reject,
23780 /* 65321 */ // Label 2006: @65321
23781 /* 65321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2014*/ GIMT_Encode4(65395), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3677 //
23782 /* 65328 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm),
23783 /* 65333 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23784 /* 65336 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23785 /* 65339 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23786 /* 65342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23787 /* 65346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23788 /* 65350 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23789 /* 65354 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3872:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
23790 /* 65354 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23791 /* 65357 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23792 /* 65361 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23793 /* 65366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16),
23794 /* 65369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23795 /* 65371 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23796 /* 65373 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23797 /* 65375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23798 /* 65378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23799 /* 65384 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23800 /* 65390 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23801 /* 65393 */ GIR_RootConstrainSelectedInstOperands,
23802 /* 65394 */ // GIR_Coverage, 3677,
23803 /* 65394 */ GIR_EraseRootFromParent_Done,
23804 /* 65395 */ // Label 2014: @65395
23805 /* 65395 */ GIM_Try, /*On fail goto*//*Label 2015*/ GIMT_Encode4(65563),
23806 /* 65400 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm),
23807 /* 65405 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2018*/ GIMT_Encode4(65562),
23808 /* 65416 */ /*GILLT_v8s16*//*Label 2016*/ GIMT_Encode4(65428), GIMT_Encode4(0),
23809 /* 65424 */ /*GILLT_v4s32*//*Label 2017*/ GIMT_Encode4(65495),
23810 /* 65428 */ // Label 2016: @65428
23811 /* 65428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2019*/ GIMT_Encode4(65494), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3687 //
23812 /* 65435 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23813 /* 65438 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23814 /* 65441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23815 /* 65445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23816 /* 65449 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23817 /* 65453 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3875:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
23818 /* 65453 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23819 /* 65456 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23820 /* 65460 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23821 /* 65465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16),
23822 /* 65468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23823 /* 65470 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23824 /* 65472 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23825 /* 65474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23826 /* 65477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23827 /* 65483 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23828 /* 65489 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23829 /* 65492 */ GIR_RootConstrainSelectedInstOperands,
23830 /* 65493 */ // GIR_Coverage, 3687,
23831 /* 65493 */ GIR_EraseRootFromParent_Done,
23832 /* 65494 */ // Label 2019: @65494
23833 /* 65494 */ GIM_Reject,
23834 /* 65495 */ // Label 2017: @65495
23835 /* 65495 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2020*/ GIMT_Encode4(65561), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3682 //
23836 /* 65502 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23837 /* 65505 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23838 /* 65508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23839 /* 65512 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23840 /* 65516 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23841 /* 65520 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3875:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
23842 /* 65520 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23843 /* 65523 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23844 /* 65527 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23845 /* 65532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32),
23846 /* 65535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23847 /* 65537 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23848 /* 65539 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23849 /* 65541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23850 /* 65544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23851 /* 65550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23852 /* 65556 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23853 /* 65559 */ GIR_RootConstrainSelectedInstOperands,
23854 /* 65560 */ // GIR_Coverage, 3682,
23855 /* 65560 */ GIR_EraseRootFromParent_Done,
23856 /* 65561 */ // Label 2020: @65561
23857 /* 65561 */ GIM_Reject,
23858 /* 65562 */ // Label 2018: @65562
23859 /* 65562 */ GIM_Reject,
23860 /* 65563 */ // Label 2015: @65563
23861 /* 65563 */ GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(65806),
23862 /* 65568 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh),
23863 /* 65573 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2025*/ GIMT_Encode4(65805),
23864 /* 65584 */ /*GILLT_v16s8*//*Label 2022*/ GIMT_Encode4(65604), GIMT_Encode4(0),
23865 /* 65592 */ /*GILLT_v8s16*//*Label 2023*/ GIMT_Encode4(65671), GIMT_Encode4(0),
23866 /* 65600 */ /*GILLT_v4s32*//*Label 2024*/ GIMT_Encode4(65738),
23867 /* 65604 */ // Label 2022: @65604
23868 /* 65604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2026*/ GIMT_Encode4(65670), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3867 //
23869 /* 65611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23870 /* 65614 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23871 /* 65617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23872 /* 65621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23873 /* 65625 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23874 /* 65629 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3895:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
23875 /* 65629 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23876 /* 65632 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23877 /* 65636 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23878 /* 65641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi8),
23879 /* 65644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23880 /* 65646 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23881 /* 65648 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23882 /* 65650 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23883 /* 65653 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23884 /* 65659 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23885 /* 65665 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23886 /* 65668 */ GIR_RootConstrainSelectedInstOperands,
23887 /* 65669 */ // GIR_Coverage, 3867,
23888 /* 65669 */ GIR_EraseRootFromParent_Done,
23889 /* 65670 */ // Label 2026: @65670
23890 /* 65670 */ GIM_Reject,
23891 /* 65671 */ // Label 2023: @65671
23892 /* 65671 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2027*/ GIMT_Encode4(65737), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3874 //
23893 /* 65678 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23894 /* 65681 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23895 /* 65684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23896 /* 65688 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23897 /* 65692 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23898 /* 65696 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3895:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
23899 /* 65696 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23900 /* 65699 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23901 /* 65703 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23902 /* 65708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi16),
23903 /* 65711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23904 /* 65713 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23905 /* 65715 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23906 /* 65717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23907 /* 65720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23908 /* 65726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23909 /* 65732 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23910 /* 65735 */ GIR_RootConstrainSelectedInstOperands,
23911 /* 65736 */ // GIR_Coverage, 3874,
23912 /* 65736 */ GIR_EraseRootFromParent_Done,
23913 /* 65737 */ // Label 2027: @65737
23914 /* 65737 */ GIM_Reject,
23915 /* 65738 */ // Label 2024: @65738
23916 /* 65738 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2028*/ GIMT_Encode4(65804), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3878 //
23917 /* 65745 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23918 /* 65748 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23919 /* 65751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23920 /* 65755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23921 /* 65759 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23922 /* 65763 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3895:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
23923 /* 65763 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23924 /* 65766 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23925 /* 65770 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23926 /* 65775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi32),
23927 /* 65778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23928 /* 65780 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23929 /* 65782 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23930 /* 65784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23931 /* 65787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23932 /* 65793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23933 /* 65799 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23934 /* 65802 */ GIR_RootConstrainSelectedInstOperands,
23935 /* 65803 */ // GIR_Coverage, 3878,
23936 /* 65803 */ GIR_EraseRootFromParent_Done,
23937 /* 65804 */ // Label 2028: @65804
23938 /* 65804 */ GIM_Reject,
23939 /* 65805 */ // Label 2025: @65805
23940 /* 65805 */ GIM_Reject,
23941 /* 65806 */ // Label 2021: @65806
23942 /* 65806 */ GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(66049),
23943 /* 65811 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh),
23944 /* 65816 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2033*/ GIMT_Encode4(66048),
23945 /* 65827 */ /*GILLT_v16s8*//*Label 2030*/ GIMT_Encode4(65847), GIMT_Encode4(0),
23946 /* 65835 */ /*GILLT_v8s16*//*Label 2031*/ GIMT_Encode4(65914), GIMT_Encode4(0),
23947 /* 65843 */ /*GILLT_v4s32*//*Label 2032*/ GIMT_Encode4(65981),
23948 /* 65847 */ // Label 2030: @65847
23949 /* 65847 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2034*/ GIMT_Encode4(65913), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3880 //
23950 /* 65854 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23951 /* 65857 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23952 /* 65860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23953 /* 65864 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23954 /* 65868 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23955 /* 65872 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3904:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQRDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
23956 /* 65872 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23957 /* 65875 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23958 /* 65879 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23959 /* 65884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi8),
23960 /* 65887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23961 /* 65889 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23962 /* 65891 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23963 /* 65893 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23964 /* 65896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23965 /* 65902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23966 /* 65908 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23967 /* 65911 */ GIR_RootConstrainSelectedInstOperands,
23968 /* 65912 */ // GIR_Coverage, 3880,
23969 /* 65912 */ GIR_EraseRootFromParent_Done,
23970 /* 65913 */ // Label 2034: @65913
23971 /* 65913 */ GIM_Reject,
23972 /* 65914 */ // Label 2031: @65914
23973 /* 65914 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2035*/ GIMT_Encode4(65980), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3882 //
23974 /* 65921 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23975 /* 65924 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23976 /* 65927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23977 /* 65931 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23978 /* 65935 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
23979 /* 65939 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3904:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQRDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
23980 /* 65939 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
23981 /* 65942 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
23982 /* 65946 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
23983 /* 65951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi16),
23984 /* 65954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
23985 /* 65956 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
23986 /* 65958 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
23987 /* 65960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23988 /* 65963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23989 /* 65969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23990 /* 65975 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
23991 /* 65978 */ GIR_RootConstrainSelectedInstOperands,
23992 /* 65979 */ // GIR_Coverage, 3882,
23993 /* 65979 */ GIR_EraseRootFromParent_Done,
23994 /* 65980 */ // Label 2035: @65980
23995 /* 65980 */ GIM_Reject,
23996 /* 65981 */ // Label 2032: @65981
23997 /* 65981 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2036*/ GIMT_Encode4(66047), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3884 //
23998 /* 65988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23999 /* 65991 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24000 /* 65994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24001 /* 65998 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24002 /* 66002 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24003 /* 66006 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3904:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQRDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24004 /* 66006 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24005 /* 66009 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24006 /* 66013 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24007 /* 66018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi32),
24008 /* 66021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24009 /* 66023 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24010 /* 66025 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24011 /* 66027 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24012 /* 66030 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24013 /* 66036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24014 /* 66042 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24015 /* 66045 */ GIR_RootConstrainSelectedInstOperands,
24016 /* 66046 */ // GIR_Coverage, 3884,
24017 /* 66046 */ GIR_EraseRootFromParent_Done,
24018 /* 66047 */ // Label 2036: @66047
24019 /* 66047 */ GIM_Reject,
24020 /* 66048 */ // Label 2033: @66048
24021 /* 66048 */ GIM_Reject,
24022 /* 66049 */ // Label 2029: @66049
24023 /* 66049 */ GIM_Try, /*On fail goto*//*Label 2037*/ GIMT_Encode4(66217),
24024 /* 66054 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmul),
24025 /* 66059 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2040*/ GIMT_Encode4(66216),
24026 /* 66070 */ /*GILLT_v8s16*//*Label 2038*/ GIMT_Encode4(66082), GIMT_Encode4(0),
24027 /* 66078 */ /*GILLT_v4s32*//*Label 2039*/ GIMT_Encode4(66149),
24028 /* 66082 */ // Label 2038: @66082
24029 /* 66082 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2041*/ GIMT_Encode4(66148), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4423 //
24030 /* 66089 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24031 /* 66092 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24032 /* 66095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24033 /* 66099 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24034 /* 66103 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24035 /* 66107 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3885:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
24036 /* 66107 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24037 /* 66110 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24038 /* 66114 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24039 /* 66119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16),
24040 /* 66122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24041 /* 66124 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24042 /* 66126 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24043 /* 66128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24044 /* 66131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24045 /* 66137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24046 /* 66143 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24047 /* 66146 */ GIR_RootConstrainSelectedInstOperands,
24048 /* 66147 */ // GIR_Coverage, 4423,
24049 /* 66147 */ GIR_EraseRootFromParent_Done,
24050 /* 66148 */ // Label 2041: @66148
24051 /* 66148 */ GIM_Reject,
24052 /* 66149 */ // Label 2039: @66149
24053 /* 66149 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2042*/ GIMT_Encode4(66215), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4416 //
24054 /* 66156 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24055 /* 66159 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24056 /* 66162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24057 /* 66166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24058 /* 66170 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24059 /* 66174 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3885:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
24060 /* 66174 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24061 /* 66177 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24062 /* 66181 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24063 /* 66186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32),
24064 /* 66189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24065 /* 66191 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24066 /* 66193 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24067 /* 66195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24068 /* 66198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24069 /* 66204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24070 /* 66210 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24071 /* 66213 */ GIR_RootConstrainSelectedInstOperands,
24072 /* 66214 */ // GIR_Coverage, 4416,
24073 /* 66214 */ GIR_EraseRootFromParent_Done,
24074 /* 66215 */ // Label 2042: @66215
24075 /* 66215 */ GIM_Reject,
24076 /* 66216 */ // Label 2040: @66216
24077 /* 66216 */ GIM_Reject,
24078 /* 66217 */ // Label 2037: @66217
24079 /* 66217 */ GIM_Try, /*On fail goto*//*Label 2043*/ GIMT_Encode4(66385),
24080 /* 66222 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vadd),
24081 /* 66227 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2046*/ GIMT_Encode4(66384),
24082 /* 66238 */ /*GILLT_v8s16*//*Label 2044*/ GIMT_Encode4(66250), GIMT_Encode4(0),
24083 /* 66246 */ /*GILLT_v4s32*//*Label 2045*/ GIMT_Encode4(66317),
24084 /* 66250 */ // Label 2044: @66250
24085 /* 66250 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2047*/ GIMT_Encode4(66316), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4463 //
24086 /* 66257 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24087 /* 66260 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24088 /* 66263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24089 /* 66267 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24090 /* 66271 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24091 /* 66275 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3822:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
24092 /* 66275 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24093 /* 66278 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24094 /* 66282 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24095 /* 66287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16),
24096 /* 66290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24097 /* 66292 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24098 /* 66294 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24099 /* 66296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24100 /* 66299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24101 /* 66305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24102 /* 66311 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24103 /* 66314 */ GIR_RootConstrainSelectedInstOperands,
24104 /* 66315 */ // GIR_Coverage, 4463,
24105 /* 66315 */ GIR_EraseRootFromParent_Done,
24106 /* 66316 */ // Label 2047: @66316
24107 /* 66316 */ GIM_Reject,
24108 /* 66317 */ // Label 2045: @66317
24109 /* 66317 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2048*/ GIMT_Encode4(66383), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4456 //
24110 /* 66324 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24111 /* 66327 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24112 /* 66330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24113 /* 66334 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24114 /* 66338 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24115 /* 66342 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3822:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
24116 /* 66342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24117 /* 66345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24118 /* 66349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24119 /* 66354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32),
24120 /* 66357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24121 /* 66359 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24122 /* 66361 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24123 /* 66363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24124 /* 66366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24125 /* 66372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24126 /* 66378 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24127 /* 66381 */ GIR_RootConstrainSelectedInstOperands,
24128 /* 66382 */ // GIR_Coverage, 4456,
24129 /* 66382 */ GIR_EraseRootFromParent_Done,
24130 /* 66383 */ // Label 2048: @66383
24131 /* 66383 */ GIM_Reject,
24132 /* 66384 */ // Label 2046: @66384
24133 /* 66384 */ GIM_Reject,
24134 /* 66385 */ // Label 2043: @66385
24135 /* 66385 */ GIM_Try, /*On fail goto*//*Label 2049*/ GIMT_Encode4(66553),
24136 /* 66390 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsub),
24137 /* 66395 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2052*/ GIMT_Encode4(66552),
24138 /* 66406 */ /*GILLT_v8s16*//*Label 2050*/ GIMT_Encode4(66418), GIMT_Encode4(0),
24139 /* 66414 */ /*GILLT_v4s32*//*Label 2051*/ GIMT_Encode4(66485),
24140 /* 66418 */ // Label 2050: @66418
24141 /* 66418 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2053*/ GIMT_Encode4(66484), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4477 //
24142 /* 66425 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24143 /* 66428 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24144 /* 66431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24145 /* 66435 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24146 /* 66439 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24147 /* 66443 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3953:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
24148 /* 66443 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24149 /* 66446 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24150 /* 66450 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24151 /* 66455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16),
24152 /* 66458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24153 /* 66460 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24154 /* 66462 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24155 /* 66464 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24156 /* 66467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24157 /* 66473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24158 /* 66479 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24159 /* 66482 */ GIR_RootConstrainSelectedInstOperands,
24160 /* 66483 */ // GIR_Coverage, 4477,
24161 /* 66483 */ GIR_EraseRootFromParent_Done,
24162 /* 66484 */ // Label 2053: @66484
24163 /* 66484 */ GIM_Reject,
24164 /* 66485 */ // Label 2051: @66485
24165 /* 66485 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2054*/ GIMT_Encode4(66551), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4470 //
24166 /* 66492 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24167 /* 66495 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24168 /* 66498 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24169 /* 66502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24170 /* 66506 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24171 /* 66510 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3953:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
24172 /* 66510 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24173 /* 66513 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24174 /* 66517 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24175 /* 66522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32),
24176 /* 66525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24177 /* 66527 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24178 /* 66529 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24179 /* 66531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24180 /* 66534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24181 /* 66540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24182 /* 66546 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24183 /* 66549 */ GIR_RootConstrainSelectedInstOperands,
24184 /* 66550 */ // GIR_Coverage, 4470,
24185 /* 66550 */ GIR_EraseRootFromParent_Done,
24186 /* 66551 */ // Label 2054: @66551
24187 /* 66551 */ GIM_Reject,
24188 /* 66552 */ // Label 2052: @66552
24189 /* 66552 */ GIM_Reject,
24190 /* 66553 */ // Label 2049: @66553
24191 /* 66553 */ GIM_Try, /*On fail goto*//*Label 2055*/ GIMT_Encode4(66693),
24192 /* 66558 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_eq),
24193 /* 66563 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2058*/ GIMT_Encode4(66692),
24194 /* 66574 */ /*GILLT_v4s1*//*Label 2056*/ GIMT_Encode4(66582),
24195 /* 66578 */ /*GILLT_v8s1*//*Label 2057*/ GIMT_Encode4(66637),
24196 /* 66582 */ // Label 2056: @66582
24197 /* 66582 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2059*/ GIMT_Encode4(66636), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4603 //
24198 /* 66589 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24199 /* 66592 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24200 /* 66595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24201 /* 66599 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24202 /* 66603 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24203 /* 66607 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3754:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 0:{ *:[i32] })
24204 /* 66607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
24205 /* 66610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24206 /* 66612 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24207 /* 66614 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24208 /* 66616 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24209 /* 66619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24210 /* 66622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24211 /* 66628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24212 /* 66634 */ GIR_RootConstrainSelectedInstOperands,
24213 /* 66635 */ // GIR_Coverage, 4603,
24214 /* 66635 */ GIR_EraseRootFromParent_Done,
24215 /* 66636 */ // Label 2059: @66636
24216 /* 66636 */ GIM_Reject,
24217 /* 66637 */ // Label 2057: @66637
24218 /* 66637 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2060*/ GIMT_Encode4(66691), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4601 //
24219 /* 66644 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24220 /* 66647 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24221 /* 66650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24222 /* 66654 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24223 /* 66658 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24224 /* 66662 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3754:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 0:{ *:[i32] })
24225 /* 66662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
24226 /* 66665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24227 /* 66667 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24228 /* 66669 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24229 /* 66671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24230 /* 66674 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24231 /* 66677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24232 /* 66683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24233 /* 66689 */ GIR_RootConstrainSelectedInstOperands,
24234 /* 66690 */ // GIR_Coverage, 4601,
24235 /* 66690 */ GIR_EraseRootFromParent_Done,
24236 /* 66691 */ // Label 2060: @66691
24237 /* 66691 */ GIM_Reject,
24238 /* 66692 */ // Label 2058: @66692
24239 /* 66692 */ GIM_Reject,
24240 /* 66693 */ // Label 2055: @66693
24241 /* 66693 */ GIM_Try, /*On fail goto*//*Label 2061*/ GIMT_Encode4(66833),
24242 /* 66698 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ne),
24243 /* 66703 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2064*/ GIMT_Encode4(66832),
24244 /* 66714 */ /*GILLT_v4s1*//*Label 2062*/ GIMT_Encode4(66722),
24245 /* 66718 */ /*GILLT_v8s1*//*Label 2063*/ GIMT_Encode4(66777),
24246 /* 66722 */ // Label 2062: @66722
24247 /* 66722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2065*/ GIMT_Encode4(66776), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4692 //
24248 /* 66729 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24249 /* 66732 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24250 /* 66735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24251 /* 66739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24252 /* 66743 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24253 /* 66747 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3759:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 1:{ *:[i32] })
24254 /* 66747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
24255 /* 66750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24256 /* 66752 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24257 /* 66754 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24258 /* 66756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
24259 /* 66759 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24260 /* 66762 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24261 /* 66768 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24262 /* 66774 */ GIR_RootConstrainSelectedInstOperands,
24263 /* 66775 */ // GIR_Coverage, 4692,
24264 /* 66775 */ GIR_EraseRootFromParent_Done,
24265 /* 66776 */ // Label 2065: @66776
24266 /* 66776 */ GIM_Reject,
24267 /* 66777 */ // Label 2063: @66777
24268 /* 66777 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2066*/ GIMT_Encode4(66831), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4690 //
24269 /* 66784 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24270 /* 66787 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24271 /* 66790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24272 /* 66794 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24273 /* 66798 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24274 /* 66802 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3759:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 1:{ *:[i32] })
24275 /* 66802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
24276 /* 66805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24277 /* 66807 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24278 /* 66809 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24279 /* 66811 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
24280 /* 66814 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24281 /* 66817 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24282 /* 66823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24283 /* 66829 */ GIR_RootConstrainSelectedInstOperands,
24284 /* 66830 */ // GIR_Coverage, 4690,
24285 /* 66830 */ GIR_EraseRootFromParent_Done,
24286 /* 66831 */ // Label 2066: @66831
24287 /* 66831 */ GIM_Reject,
24288 /* 66832 */ // Label 2064: @66832
24289 /* 66832 */ GIM_Reject,
24290 /* 66833 */ // Label 2061: @66833
24291 /* 66833 */ GIM_Try, /*On fail goto*//*Label 2067*/ GIMT_Encode4(66973),
24292 /* 66838 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ge),
24293 /* 66843 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2070*/ GIMT_Encode4(66972),
24294 /* 66854 */ /*GILLT_v4s1*//*Label 2068*/ GIMT_Encode4(66862),
24295 /* 66858 */ /*GILLT_v8s1*//*Label 2069*/ GIMT_Encode4(66917),
24296 /* 66862 */ // Label 2068: @66862
24297 /* 66862 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2071*/ GIMT_Encode4(66916), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4708 //
24298 /* 66869 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24299 /* 66872 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24300 /* 66875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24301 /* 66879 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24302 /* 66883 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24303 /* 66887 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3755:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 10:{ *:[i32] })
24304 /* 66887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
24305 /* 66890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24306 /* 66892 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24307 /* 66894 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24308 /* 66896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/10,
24309 /* 66899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24310 /* 66902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24311 /* 66908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24312 /* 66914 */ GIR_RootConstrainSelectedInstOperands,
24313 /* 66915 */ // GIR_Coverage, 4708,
24314 /* 66915 */ GIR_EraseRootFromParent_Done,
24315 /* 66916 */ // Label 2071: @66916
24316 /* 66916 */ GIM_Reject,
24317 /* 66917 */ // Label 2069: @66917
24318 /* 66917 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2072*/ GIMT_Encode4(66971), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4706 //
24319 /* 66924 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24320 /* 66927 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24321 /* 66930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24322 /* 66934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24323 /* 66938 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24324 /* 66942 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3755:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 10:{ *:[i32] })
24325 /* 66942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
24326 /* 66945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24327 /* 66947 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24328 /* 66949 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24329 /* 66951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/10,
24330 /* 66954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24331 /* 66957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24332 /* 66963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24333 /* 66969 */ GIR_RootConstrainSelectedInstOperands,
24334 /* 66970 */ // GIR_Coverage, 4706,
24335 /* 66970 */ GIR_EraseRootFromParent_Done,
24336 /* 66971 */ // Label 2072: @66971
24337 /* 66971 */ GIM_Reject,
24338 /* 66972 */ // Label 2070: @66972
24339 /* 66972 */ GIM_Reject,
24340 /* 66973 */ // Label 2067: @66973
24341 /* 66973 */ GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(67113),
24342 /* 66978 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_lt),
24343 /* 66983 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2076*/ GIMT_Encode4(67112),
24344 /* 66994 */ /*GILLT_v4s1*//*Label 2074*/ GIMT_Encode4(67002),
24345 /* 66998 */ /*GILLT_v8s1*//*Label 2075*/ GIMT_Encode4(67057),
24346 /* 67002 */ // Label 2074: @67002
24347 /* 67002 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2077*/ GIMT_Encode4(67056), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4724 //
24348 /* 67009 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24349 /* 67012 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24350 /* 67015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24351 /* 67019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24352 /* 67023 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24353 /* 67027 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3758:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 11:{ *:[i32] })
24354 /* 67027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
24355 /* 67030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24356 /* 67032 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24357 /* 67034 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24358 /* 67036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/11,
24359 /* 67039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24360 /* 67042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24361 /* 67048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24362 /* 67054 */ GIR_RootConstrainSelectedInstOperands,
24363 /* 67055 */ // GIR_Coverage, 4724,
24364 /* 67055 */ GIR_EraseRootFromParent_Done,
24365 /* 67056 */ // Label 2077: @67056
24366 /* 67056 */ GIM_Reject,
24367 /* 67057 */ // Label 2075: @67057
24368 /* 67057 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2078*/ GIMT_Encode4(67111), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4722 //
24369 /* 67064 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24370 /* 67067 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24371 /* 67070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24372 /* 67074 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24373 /* 67078 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24374 /* 67082 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3758:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 11:{ *:[i32] })
24375 /* 67082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
24376 /* 67085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24377 /* 67087 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24378 /* 67089 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24379 /* 67091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/11,
24380 /* 67094 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24381 /* 67097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24382 /* 67103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24383 /* 67109 */ GIR_RootConstrainSelectedInstOperands,
24384 /* 67110 */ // GIR_Coverage, 4722,
24385 /* 67110 */ GIR_EraseRootFromParent_Done,
24386 /* 67111 */ // Label 2078: @67111
24387 /* 67111 */ GIM_Reject,
24388 /* 67112 */ // Label 2076: @67112
24389 /* 67112 */ GIM_Reject,
24390 /* 67113 */ // Label 2073: @67113
24391 /* 67113 */ GIM_Try, /*On fail goto*//*Label 2079*/ GIMT_Encode4(67253),
24392 /* 67118 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_gt),
24393 /* 67123 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2082*/ GIMT_Encode4(67252),
24394 /* 67134 */ /*GILLT_v4s1*//*Label 2080*/ GIMT_Encode4(67142),
24395 /* 67138 */ /*GILLT_v8s1*//*Label 2081*/ GIMT_Encode4(67197),
24396 /* 67142 */ // Label 2080: @67142
24397 /* 67142 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2083*/ GIMT_Encode4(67196), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4740 //
24398 /* 67149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24399 /* 67152 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24400 /* 67155 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24401 /* 67159 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24402 /* 67163 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24403 /* 67167 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3756:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 12:{ *:[i32] })
24404 /* 67167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
24405 /* 67170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24406 /* 67172 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24407 /* 67174 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24408 /* 67176 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/12,
24409 /* 67179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24410 /* 67182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24411 /* 67188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24412 /* 67194 */ GIR_RootConstrainSelectedInstOperands,
24413 /* 67195 */ // GIR_Coverage, 4740,
24414 /* 67195 */ GIR_EraseRootFromParent_Done,
24415 /* 67196 */ // Label 2083: @67196
24416 /* 67196 */ GIM_Reject,
24417 /* 67197 */ // Label 2081: @67197
24418 /* 67197 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2084*/ GIMT_Encode4(67251), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4738 //
24419 /* 67204 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24420 /* 67207 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24421 /* 67210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24422 /* 67214 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24423 /* 67218 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24424 /* 67222 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3756:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 12:{ *:[i32] })
24425 /* 67222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
24426 /* 67225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24427 /* 67227 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24428 /* 67229 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24429 /* 67231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/12,
24430 /* 67234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24431 /* 67237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24432 /* 67243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24433 /* 67249 */ GIR_RootConstrainSelectedInstOperands,
24434 /* 67250 */ // GIR_Coverage, 4738,
24435 /* 67250 */ GIR_EraseRootFromParent_Done,
24436 /* 67251 */ // Label 2084: @67251
24437 /* 67251 */ GIM_Reject,
24438 /* 67252 */ // Label 2082: @67252
24439 /* 67252 */ GIM_Reject,
24440 /* 67253 */ // Label 2079: @67253
24441 /* 67253 */ GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(67393),
24442 /* 67258 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_le),
24443 /* 67263 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(6), /*)*//*default:*//*Label 2088*/ GIMT_Encode4(67392),
24444 /* 67274 */ /*GILLT_v4s1*//*Label 2086*/ GIMT_Encode4(67282),
24445 /* 67278 */ /*GILLT_v8s1*//*Label 2087*/ GIMT_Encode4(67337),
24446 /* 67282 */ // Label 2086: @67282
24447 /* 67282 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2089*/ GIMT_Encode4(67336), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4756 //
24448 /* 67289 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24449 /* 67292 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24450 /* 67295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24451 /* 67299 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24452 /* 67303 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24453 /* 67307 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3757:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 13:{ *:[i32] })
24454 /* 67307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
24455 /* 67310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24456 /* 67312 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24457 /* 67314 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24458 /* 67316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/13,
24459 /* 67319 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24460 /* 67322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24461 /* 67328 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24462 /* 67334 */ GIR_RootConstrainSelectedInstOperands,
24463 /* 67335 */ // GIR_Coverage, 4756,
24464 /* 67335 */ GIR_EraseRootFromParent_Done,
24465 /* 67336 */ // Label 2089: @67336
24466 /* 67336 */ GIM_Reject,
24467 /* 67337 */ // Label 2087: @67337
24468 /* 67337 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2090*/ GIMT_Encode4(67391), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4754 //
24469 /* 67344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24470 /* 67347 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24471 /* 67350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
24472 /* 67354 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24473 /* 67358 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24474 /* 67362 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3757:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 13:{ *:[i32] })
24475 /* 67362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
24476 /* 67365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
24477 /* 67367 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
24478 /* 67369 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
24479 /* 67371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/13,
24480 /* 67374 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24481 /* 67377 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24482 /* 67383 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24483 /* 67389 */ GIR_RootConstrainSelectedInstOperands,
24484 /* 67390 */ // GIR_Coverage, 4754,
24485 /* 67390 */ GIR_EraseRootFromParent_Done,
24486 /* 67391 */ // Label 2090: @67391
24487 /* 67391 */ GIM_Reject,
24488 /* 67392 */ // Label 2088: @67392
24489 /* 67392 */ GIM_Reject,
24490 /* 67393 */ // Label 2085: @67393
24491 /* 67393 */ GIM_Try, /*On fail goto*//*Label 2091*/ GIMT_Encode4(67744),
24492 /* 67398 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
24493 /* 67403 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2095*/ GIMT_Encode4(67743),
24494 /* 67414 */ /*GILLT_v16s8*//*Label 2092*/ GIMT_Encode4(67434), GIMT_Encode4(0),
24495 /* 67422 */ /*GILLT_v8s16*//*Label 2093*/ GIMT_Encode4(67501), GIMT_Encode4(0),
24496 /* 67430 */ /*GILLT_v4s32*//*Label 2094*/ GIMT_Encode4(67622),
24497 /* 67434 */ // Label 2092: @67434
24498 /* 67434 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2096*/ GIMT_Encode4(67500), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5278 //
24499 /* 67441 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24500 /* 67444 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24501 /* 67447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24502 /* 67451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24503 /* 67455 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24504 /* 67459 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3823:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24505 /* 67459 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24506 /* 67462 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24507 /* 67466 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24508 /* 67471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8),
24509 /* 67474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24510 /* 67476 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
24511 /* 67478 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24512 /* 67480 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24513 /* 67483 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24514 /* 67489 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24515 /* 67495 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24516 /* 67498 */ GIR_RootConstrainSelectedInstOperands,
24517 /* 67499 */ // GIR_Coverage, 5278,
24518 /* 67499 */ GIR_EraseRootFromParent_Done,
24519 /* 67500 */ // Label 2096: @67500
24520 /* 67500 */ GIM_Reject,
24521 /* 67501 */ // Label 2093: @67501
24522 /* 67501 */ GIM_Try, /*On fail goto*//*Label 2097*/ GIMT_Encode4(67621),
24523 /* 67506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24524 /* 67509 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24525 /* 67512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24526 /* 67516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24527 /* 67520 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24528 /* 67524 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2098*/ GIMT_Encode4(67572), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5283 //
24529 /* 67531 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3823:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24530 /* 67531 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24531 /* 67534 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24532 /* 67538 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24533 /* 67543 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16),
24534 /* 67546 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24535 /* 67548 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
24536 /* 67550 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24537 /* 67552 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24538 /* 67555 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24539 /* 67561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24540 /* 67567 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24541 /* 67570 */ GIR_RootConstrainSelectedInstOperands,
24542 /* 67571 */ // GIR_Coverage, 5283,
24543 /* 67571 */ GIR_EraseRootFromParent_Done,
24544 /* 67572 */ // Label 2098: @67572
24545 /* 67572 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2099*/ GIMT_Encode4(67620), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5287 //
24546 /* 67579 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3823:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24547 /* 67579 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24548 /* 67582 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24549 /* 67586 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24550 /* 67591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16),
24551 /* 67594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24552 /* 67596 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
24553 /* 67598 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24554 /* 67600 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24555 /* 67603 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24556 /* 67609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24557 /* 67615 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24558 /* 67618 */ GIR_RootConstrainSelectedInstOperands,
24559 /* 67619 */ // GIR_Coverage, 5287,
24560 /* 67619 */ GIR_EraseRootFromParent_Done,
24561 /* 67620 */ // Label 2099: @67620
24562 /* 67620 */ GIM_Reject,
24563 /* 67621 */ // Label 2097: @67621
24564 /* 67621 */ GIM_Reject,
24565 /* 67622 */ // Label 2094: @67622
24566 /* 67622 */ GIM_Try, /*On fail goto*//*Label 2100*/ GIMT_Encode4(67742),
24567 /* 67627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24568 /* 67630 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24569 /* 67633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24570 /* 67637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24571 /* 67641 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24572 /* 67645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2101*/ GIMT_Encode4(67693), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5285 //
24573 /* 67652 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3823:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24574 /* 67652 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24575 /* 67655 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24576 /* 67659 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24577 /* 67664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32),
24578 /* 67667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24579 /* 67669 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
24580 /* 67671 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24581 /* 67673 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24582 /* 67676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24583 /* 67682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24584 /* 67688 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24585 /* 67691 */ GIR_RootConstrainSelectedInstOperands,
24586 /* 67692 */ // GIR_Coverage, 5285,
24587 /* 67692 */ GIR_EraseRootFromParent_Done,
24588 /* 67693 */ // Label 2101: @67693
24589 /* 67693 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2102*/ GIMT_Encode4(67741), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5289 //
24590 /* 67700 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3823:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm)
24591 /* 67700 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24592 /* 67703 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24593 /* 67707 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24594 /* 67712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32),
24595 /* 67715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24596 /* 67717 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
24597 /* 67719 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24598 /* 67721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24599 /* 67724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24600 /* 67730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24601 /* 67736 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24602 /* 67739 */ GIR_RootConstrainSelectedInstOperands,
24603 /* 67740 */ // GIR_Coverage, 5289,
24604 /* 67740 */ GIR_EraseRootFromParent_Done,
24605 /* 67741 */ // Label 2102: @67741
24606 /* 67741 */ GIM_Reject,
24607 /* 67742 */ // Label 2100: @67742
24608 /* 67742 */ GIM_Reject,
24609 /* 67743 */ // Label 2095: @67743
24610 /* 67743 */ GIM_Reject,
24611 /* 67744 */ // Label 2091: @67744
24612 /* 67744 */ GIM_Reject,
24613 /* 67745 */ // Label 1359: @67745
24614 /* 67745 */ GIM_Try, /*On fail goto*//*Label 2103*/ GIMT_Encode4(78158),
24615 /* 67750 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
24616 /* 67753 */ GIM_Try, /*On fail goto*//*Label 2104*/ GIMT_Encode4(68257),
24617 /* 67758 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
24618 /* 67763 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2108*/ GIMT_Encode4(68256),
24619 /* 67774 */ /*GILLT_v16s8*//*Label 2105*/ GIMT_Encode4(67794), GIMT_Encode4(0),
24620 /* 67782 */ /*GILLT_v8s16*//*Label 2106*/ GIMT_Encode4(67948), GIMT_Encode4(0),
24621 /* 67790 */ /*GILLT_v4s32*//*Label 2107*/ GIMT_Encode4(68102),
24622 /* 67794 */ // Label 2105: @67794
24623 /* 67794 */ GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(67947),
24624 /* 67799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24625 /* 67802 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24626 /* 67805 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
24627 /* 67808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24628 /* 67812 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24629 /* 67816 */ GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(67881), // Rule ID 4319 //
24630 /* 67821 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24631 /* 67825 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24632 /* 67829 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
24633 /* 67833 */ // MIs[1] Operand 1
24634 /* 67833 */ // No operand predicates
24635 /* 67833 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24636 /* 67837 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24637 /* 67839 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3905:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
24638 /* 67839 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24639 /* 67842 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24640 /* 67846 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24641 /* 67851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms8),
24642 /* 67854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24643 /* 67856 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24644 /* 67858 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24645 /* 67861 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24646 /* 67864 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24647 /* 67870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24648 /* 67876 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24649 /* 67879 */ GIR_RootConstrainSelectedInstOperands,
24650 /* 67880 */ // GIR_Coverage, 4319,
24651 /* 67880 */ GIR_EraseRootFromParent_Done,
24652 /* 67881 */ // Label 2110: @67881
24653 /* 67881 */ GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(67946), // Rule ID 4321 //
24654 /* 67886 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24655 /* 67890 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24656 /* 67894 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
24657 /* 67898 */ // MIs[1] Operand 1
24658 /* 67898 */ // No operand predicates
24659 /* 67898 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24660 /* 67902 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24661 /* 67904 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3905:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
24662 /* 67904 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24663 /* 67907 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24664 /* 67911 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24665 /* 67916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu8),
24666 /* 67919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24667 /* 67921 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24668 /* 67923 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24669 /* 67926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24670 /* 67929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24671 /* 67935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24672 /* 67941 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24673 /* 67944 */ GIR_RootConstrainSelectedInstOperands,
24674 /* 67945 */ // GIR_Coverage, 4321,
24675 /* 67945 */ GIR_EraseRootFromParent_Done,
24676 /* 67946 */ // Label 2111: @67946
24677 /* 67946 */ GIM_Reject,
24678 /* 67947 */ // Label 2109: @67947
24679 /* 67947 */ GIM_Reject,
24680 /* 67948 */ // Label 2106: @67948
24681 /* 67948 */ GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(68101),
24682 /* 67953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24683 /* 67956 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24684 /* 67959 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
24685 /* 67962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24686 /* 67966 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24687 /* 67970 */ GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(68035), // Rule ID 4323 //
24688 /* 67975 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24689 /* 67979 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24690 /* 67983 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
24691 /* 67987 */ // MIs[1] Operand 1
24692 /* 67987 */ // No operand predicates
24693 /* 67987 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24694 /* 67991 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24695 /* 67993 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3905:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
24696 /* 67993 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24697 /* 67996 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24698 /* 68000 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24699 /* 68005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms16),
24700 /* 68008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24701 /* 68010 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24702 /* 68012 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24703 /* 68015 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24704 /* 68018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24705 /* 68024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24706 /* 68030 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24707 /* 68033 */ GIR_RootConstrainSelectedInstOperands,
24708 /* 68034 */ // GIR_Coverage, 4323,
24709 /* 68034 */ GIR_EraseRootFromParent_Done,
24710 /* 68035 */ // Label 2113: @68035
24711 /* 68035 */ GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(68100), // Rule ID 4325 //
24712 /* 68040 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24713 /* 68044 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24714 /* 68048 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
24715 /* 68052 */ // MIs[1] Operand 1
24716 /* 68052 */ // No operand predicates
24717 /* 68052 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24718 /* 68056 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24719 /* 68058 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3905:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
24720 /* 68058 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24721 /* 68061 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24722 /* 68065 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24723 /* 68070 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu16),
24724 /* 68073 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24725 /* 68075 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24726 /* 68077 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24727 /* 68080 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24728 /* 68083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24729 /* 68089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24730 /* 68095 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24731 /* 68098 */ GIR_RootConstrainSelectedInstOperands,
24732 /* 68099 */ // GIR_Coverage, 4325,
24733 /* 68099 */ GIR_EraseRootFromParent_Done,
24734 /* 68100 */ // Label 2114: @68100
24735 /* 68100 */ GIM_Reject,
24736 /* 68101 */ // Label 2112: @68101
24737 /* 68101 */ GIM_Reject,
24738 /* 68102 */ // Label 2107: @68102
24739 /* 68102 */ GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(68255),
24740 /* 68107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24741 /* 68110 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24742 /* 68113 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
24743 /* 68116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24744 /* 68120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24745 /* 68124 */ GIM_Try, /*On fail goto*//*Label 2116*/ GIMT_Encode4(68189), // Rule ID 4327 //
24746 /* 68129 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24747 /* 68133 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24748 /* 68137 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
24749 /* 68141 */ // MIs[1] Operand 1
24750 /* 68141 */ // No operand predicates
24751 /* 68141 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24752 /* 68145 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24753 /* 68147 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3905:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
24754 /* 68147 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24755 /* 68150 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24756 /* 68154 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24757 /* 68159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms32),
24758 /* 68162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24759 /* 68164 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24760 /* 68166 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24761 /* 68169 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24762 /* 68172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24763 /* 68178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24764 /* 68184 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24765 /* 68187 */ GIR_RootConstrainSelectedInstOperands,
24766 /* 68188 */ // GIR_Coverage, 4327,
24767 /* 68188 */ GIR_EraseRootFromParent_Done,
24768 /* 68189 */ // Label 2116: @68189
24769 /* 68189 */ GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(68254), // Rule ID 4329 //
24770 /* 68194 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24771 /* 68198 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24772 /* 68202 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
24773 /* 68206 */ // MIs[1] Operand 1
24774 /* 68206 */ // No operand predicates
24775 /* 68206 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24776 /* 68210 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24777 /* 68212 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3905:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
24778 /* 68212 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24779 /* 68215 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24780 /* 68219 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24781 /* 68224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu32),
24782 /* 68227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24783 /* 68229 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24784 /* 68231 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24785 /* 68234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24786 /* 68237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24787 /* 68243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24788 /* 68249 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24789 /* 68252 */ GIR_RootConstrainSelectedInstOperands,
24790 /* 68253 */ // GIR_Coverage, 4329,
24791 /* 68253 */ GIR_EraseRootFromParent_Done,
24792 /* 68254 */ // Label 2117: @68254
24793 /* 68254 */ GIM_Reject,
24794 /* 68255 */ // Label 2115: @68255
24795 /* 68255 */ GIM_Reject,
24796 /* 68256 */ // Label 2108: @68256
24797 /* 68256 */ GIM_Reject,
24798 /* 68257 */ // Label 2104: @68257
24799 /* 68257 */ GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(68761),
24800 /* 68262 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
24801 /* 68267 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2122*/ GIMT_Encode4(68760),
24802 /* 68278 */ /*GILLT_v16s8*//*Label 2119*/ GIMT_Encode4(68298), GIMT_Encode4(0),
24803 /* 68286 */ /*GILLT_v8s16*//*Label 2120*/ GIMT_Encode4(68452), GIMT_Encode4(0),
24804 /* 68294 */ /*GILLT_v4s32*//*Label 2121*/ GIMT_Encode4(68606),
24805 /* 68298 */ // Label 2119: @68298
24806 /* 68298 */ GIM_Try, /*On fail goto*//*Label 2123*/ GIMT_Encode4(68451),
24807 /* 68303 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24808 /* 68306 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24809 /* 68309 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
24810 /* 68312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24811 /* 68316 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24812 /* 68320 */ GIM_Try, /*On fail goto*//*Label 2124*/ GIMT_Encode4(68385), // Rule ID 4337 //
24813 /* 68325 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24814 /* 68329 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24815 /* 68333 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
24816 /* 68337 */ // MIs[1] Operand 1
24817 /* 68337 */ // No operand predicates
24818 /* 68337 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24819 /* 68341 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24820 /* 68343 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3927:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
24821 /* 68343 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24822 /* 68346 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24823 /* 68350 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24824 /* 68355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms8),
24825 /* 68358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24826 /* 68360 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24827 /* 68362 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24828 /* 68365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24829 /* 68368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24830 /* 68374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24831 /* 68380 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24832 /* 68383 */ GIR_RootConstrainSelectedInstOperands,
24833 /* 68384 */ // GIR_Coverage, 4337,
24834 /* 68384 */ GIR_EraseRootFromParent_Done,
24835 /* 68385 */ // Label 2124: @68385
24836 /* 68385 */ GIM_Try, /*On fail goto*//*Label 2125*/ GIMT_Encode4(68450), // Rule ID 4339 //
24837 /* 68390 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24838 /* 68394 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24839 /* 68398 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
24840 /* 68402 */ // MIs[1] Operand 1
24841 /* 68402 */ // No operand predicates
24842 /* 68402 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24843 /* 68406 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24844 /* 68408 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3927:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
24845 /* 68408 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24846 /* 68411 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24847 /* 68415 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24848 /* 68420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu8),
24849 /* 68423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24850 /* 68425 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24851 /* 68427 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24852 /* 68430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24853 /* 68433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24854 /* 68439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24855 /* 68445 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24856 /* 68448 */ GIR_RootConstrainSelectedInstOperands,
24857 /* 68449 */ // GIR_Coverage, 4339,
24858 /* 68449 */ GIR_EraseRootFromParent_Done,
24859 /* 68450 */ // Label 2125: @68450
24860 /* 68450 */ GIM_Reject,
24861 /* 68451 */ // Label 2123: @68451
24862 /* 68451 */ GIM_Reject,
24863 /* 68452 */ // Label 2120: @68452
24864 /* 68452 */ GIM_Try, /*On fail goto*//*Label 2126*/ GIMT_Encode4(68605),
24865 /* 68457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24866 /* 68460 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24867 /* 68463 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
24868 /* 68466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24869 /* 68470 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24870 /* 68474 */ GIM_Try, /*On fail goto*//*Label 2127*/ GIMT_Encode4(68539), // Rule ID 4341 //
24871 /* 68479 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24872 /* 68483 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24873 /* 68487 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
24874 /* 68491 */ // MIs[1] Operand 1
24875 /* 68491 */ // No operand predicates
24876 /* 68491 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24877 /* 68495 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24878 /* 68497 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3927:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
24879 /* 68497 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24880 /* 68500 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24881 /* 68504 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24882 /* 68509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms16),
24883 /* 68512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24884 /* 68514 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24885 /* 68516 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24886 /* 68519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24887 /* 68522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24888 /* 68528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24889 /* 68534 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24890 /* 68537 */ GIR_RootConstrainSelectedInstOperands,
24891 /* 68538 */ // GIR_Coverage, 4341,
24892 /* 68538 */ GIR_EraseRootFromParent_Done,
24893 /* 68539 */ // Label 2127: @68539
24894 /* 68539 */ GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(68604), // Rule ID 4343 //
24895 /* 68544 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24896 /* 68548 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24897 /* 68552 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
24898 /* 68556 */ // MIs[1] Operand 1
24899 /* 68556 */ // No operand predicates
24900 /* 68556 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24901 /* 68560 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24902 /* 68562 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3927:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
24903 /* 68562 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24904 /* 68565 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24905 /* 68569 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24906 /* 68574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu16),
24907 /* 68577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24908 /* 68579 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24909 /* 68581 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24910 /* 68584 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24911 /* 68587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24912 /* 68593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24913 /* 68599 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24914 /* 68602 */ GIR_RootConstrainSelectedInstOperands,
24915 /* 68603 */ // GIR_Coverage, 4343,
24916 /* 68603 */ GIR_EraseRootFromParent_Done,
24917 /* 68604 */ // Label 2128: @68604
24918 /* 68604 */ GIM_Reject,
24919 /* 68605 */ // Label 2126: @68605
24920 /* 68605 */ GIM_Reject,
24921 /* 68606 */ // Label 2121: @68606
24922 /* 68606 */ GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(68759),
24923 /* 68611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24924 /* 68614 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24925 /* 68617 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
24926 /* 68620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24927 /* 68624 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24928 /* 68628 */ GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(68693), // Rule ID 4345 //
24929 /* 68633 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24930 /* 68637 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24931 /* 68641 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32),
24932 /* 68645 */ // MIs[1] Operand 1
24933 /* 68645 */ // No operand predicates
24934 /* 68645 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
24935 /* 68649 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24936 /* 68651 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3927:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
24937 /* 68651 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24938 /* 68654 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24939 /* 68658 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24940 /* 68663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms32),
24941 /* 68666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24942 /* 68668 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24943 /* 68670 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24944 /* 68673 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24945 /* 68676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24946 /* 68682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24947 /* 68688 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24948 /* 68691 */ GIR_RootConstrainSelectedInstOperands,
24949 /* 68692 */ // GIR_Coverage, 4345,
24950 /* 68692 */ GIR_EraseRootFromParent_Done,
24951 /* 68693 */ // Label 2130: @68693
24952 /* 68693 */ GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(68758), // Rule ID 4347 //
24953 /* 68698 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
24954 /* 68702 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24955 /* 68706 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32),
24956 /* 68710 */ // MIs[1] Operand 1
24957 /* 68710 */ // No operand predicates
24958 /* 68710 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
24959 /* 68714 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
24960 /* 68716 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3927:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
24961 /* 68716 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24962 /* 68719 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24963 /* 68723 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24964 /* 68728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu32),
24965 /* 68731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24966 /* 68733 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
24967 /* 68735 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
24968 /* 68738 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24969 /* 68741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24970 /* 68747 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24971 /* 68753 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24972 /* 68756 */ GIR_RootConstrainSelectedInstOperands,
24973 /* 68757 */ // GIR_Coverage, 4347,
24974 /* 68757 */ GIR_EraseRootFromParent_Done,
24975 /* 68758 */ // Label 2131: @68758
24976 /* 68758 */ GIM_Reject,
24977 /* 68759 */ // Label 2129: @68759
24978 /* 68759 */ GIM_Reject,
24979 /* 68760 */ // Label 2122: @68760
24980 /* 68760 */ GIM_Reject,
24981 /* 68761 */ // Label 2118: @68761
24982 /* 68761 */ GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(69363),
24983 /* 68766 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
24984 /* 68771 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2135*/ GIMT_Encode4(69362),
24985 /* 68782 */ /*GILLT_v8s16*//*Label 2133*/ GIMT_Encode4(68794), GIMT_Encode4(0),
24986 /* 68790 */ /*GILLT_v4s32*//*Label 2134*/ GIMT_Encode4(69078),
24987 /* 68794 */ // Label 2133: @68794
24988 /* 68794 */ GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(69077),
24989 /* 68799 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24990 /* 68802 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24991 /* 68805 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
24992 /* 68808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24993 /* 68812 */ GIM_Try, /*On fail goto*//*Label 2137*/ GIMT_Encode4(68944),
24994 /* 68817 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
24995 /* 68821 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24996 /* 68825 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2138*/ GIMT_Encode4(68884), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4493 //
24997 /* 68832 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
24998 /* 68836 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
24999 /* 68840 */ // MIs[1] Operand 1
25000 /* 68840 */ // No operand predicates
25001 /* 68840 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25002 /* 68842 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3836:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16s16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)
25003 /* 68842 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25004 /* 68845 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25005 /* 68849 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25006 /* 68854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16_fix),
25007 /* 68857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25008 /* 68859 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25009 /* 68861 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25010 /* 68864 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25011 /* 68867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25012 /* 68873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25013 /* 68879 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25014 /* 68882 */ GIR_RootConstrainSelectedInstOperands,
25015 /* 68883 */ // GIR_Coverage, 4493,
25016 /* 68883 */ GIR_EraseRootFromParent_Done,
25017 /* 68884 */ // Label 2138: @68884
25018 /* 68884 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2139*/ GIMT_Encode4(68943), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4495 //
25019 /* 68891 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25020 /* 68895 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25021 /* 68899 */ // MIs[1] Operand 1
25022 /* 68899 */ // No operand predicates
25023 /* 68899 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25024 /* 68901 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3836:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)
25025 /* 68901 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25026 /* 68904 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25027 /* 68908 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25028 /* 68913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16_fix),
25029 /* 68916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25030 /* 68918 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25031 /* 68920 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25032 /* 68923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25033 /* 68926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25034 /* 68932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25035 /* 68938 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25036 /* 68941 */ GIR_RootConstrainSelectedInstOperands,
25037 /* 68942 */ // GIR_Coverage, 4495,
25038 /* 68942 */ GIR_EraseRootFromParent_Done,
25039 /* 68943 */ // Label 2139: @68943
25040 /* 68943 */ GIM_Reject,
25041 /* 68944 */ // Label 2137: @68944
25042 /* 68944 */ GIM_Try, /*On fail goto*//*Label 2140*/ GIMT_Encode4(69076),
25043 /* 68949 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
25044 /* 68953 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25045 /* 68957 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2141*/ GIMT_Encode4(69016), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4497 //
25046 /* 68964 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25047 /* 68968 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25048 /* 68972 */ // MIs[1] Operand 1
25049 /* 68972 */ // No operand predicates
25050 /* 68972 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25051 /* 68974 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3836:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16u16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)
25052 /* 68974 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25053 /* 68977 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25054 /* 68981 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25055 /* 68986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16_fix),
25056 /* 68989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25057 /* 68991 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25058 /* 68993 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25059 /* 68996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25060 /* 68999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25061 /* 69005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25062 /* 69011 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25063 /* 69014 */ GIR_RootConstrainSelectedInstOperands,
25064 /* 69015 */ // GIR_Coverage, 4497,
25065 /* 69015 */ GIR_EraseRootFromParent_Done,
25066 /* 69016 */ // Label 2141: @69016
25067 /* 69016 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2142*/ GIMT_Encode4(69075), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4499 //
25068 /* 69023 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25069 /* 69027 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25070 /* 69031 */ // MIs[1] Operand 1
25071 /* 69031 */ // No operand predicates
25072 /* 69031 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25073 /* 69033 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3836:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)
25074 /* 69033 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25075 /* 69036 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25076 /* 69040 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25077 /* 69045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16_fix),
25078 /* 69048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25079 /* 69050 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25080 /* 69052 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25081 /* 69055 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25082 /* 69058 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25083 /* 69064 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25084 /* 69070 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25085 /* 69073 */ GIR_RootConstrainSelectedInstOperands,
25086 /* 69074 */ // GIR_Coverage, 4499,
25087 /* 69074 */ GIR_EraseRootFromParent_Done,
25088 /* 69075 */ // Label 2142: @69075
25089 /* 69075 */ GIM_Reject,
25090 /* 69076 */ // Label 2140: @69076
25091 /* 69076 */ GIM_Reject,
25092 /* 69077 */ // Label 2136: @69077
25093 /* 69077 */ GIM_Reject,
25094 /* 69078 */ // Label 2134: @69078
25095 /* 69078 */ GIM_Try, /*On fail goto*//*Label 2143*/ GIMT_Encode4(69361),
25096 /* 69083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25097 /* 69086 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25098 /* 69089 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25099 /* 69092 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25100 /* 69096 */ GIM_Try, /*On fail goto*//*Label 2144*/ GIMT_Encode4(69228),
25101 /* 69101 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
25102 /* 69105 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25103 /* 69109 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2145*/ GIMT_Encode4(69168), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4501 //
25104 /* 69116 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25105 /* 69120 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25106 /* 69124 */ // MIs[1] Operand 1
25107 /* 69124 */ // No operand predicates
25108 /* 69124 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25109 /* 69126 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3836:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32s32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)
25110 /* 69126 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25111 /* 69129 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25112 /* 69133 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25113 /* 69138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32_fix),
25114 /* 69141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25115 /* 69143 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25116 /* 69145 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25117 /* 69148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25118 /* 69151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25119 /* 69157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25120 /* 69163 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25121 /* 69166 */ GIR_RootConstrainSelectedInstOperands,
25122 /* 69167 */ // GIR_Coverage, 4501,
25123 /* 69167 */ GIR_EraseRootFromParent_Done,
25124 /* 69168 */ // Label 2145: @69168
25125 /* 69168 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2146*/ GIMT_Encode4(69227), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4503 //
25126 /* 69175 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25127 /* 69179 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25128 /* 69183 */ // MIs[1] Operand 1
25129 /* 69183 */ // No operand predicates
25130 /* 69183 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25131 /* 69185 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3836:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)
25132 /* 69185 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25133 /* 69188 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25134 /* 69192 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25135 /* 69197 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32_fix),
25136 /* 69200 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25137 /* 69202 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25138 /* 69204 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25139 /* 69207 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25140 /* 69210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25141 /* 69216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25142 /* 69222 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25143 /* 69225 */ GIR_RootConstrainSelectedInstOperands,
25144 /* 69226 */ // GIR_Coverage, 4503,
25145 /* 69226 */ GIR_EraseRootFromParent_Done,
25146 /* 69227 */ // Label 2146: @69227
25147 /* 69227 */ GIM_Reject,
25148 /* 69228 */ // Label 2144: @69228
25149 /* 69228 */ GIM_Try, /*On fail goto*//*Label 2147*/ GIMT_Encode4(69360),
25150 /* 69233 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
25151 /* 69237 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25152 /* 69241 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2148*/ GIMT_Encode4(69300), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4505 //
25153 /* 69248 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25154 /* 69252 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25155 /* 69256 */ // MIs[1] Operand 1
25156 /* 69256 */ // No operand predicates
25157 /* 69256 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25158 /* 69258 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3836:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32u32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)
25159 /* 69258 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25160 /* 69261 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25161 /* 69265 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25162 /* 69270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32_fix),
25163 /* 69273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25164 /* 69275 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25165 /* 69277 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25166 /* 69280 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25167 /* 69283 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25168 /* 69289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25169 /* 69295 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25170 /* 69298 */ GIR_RootConstrainSelectedInstOperands,
25171 /* 69299 */ // GIR_Coverage, 4505,
25172 /* 69299 */ GIR_EraseRootFromParent_Done,
25173 /* 69300 */ // Label 2148: @69300
25174 /* 69300 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2149*/ GIMT_Encode4(69359), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4507 //
25175 /* 69307 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25176 /* 69311 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25177 /* 69315 */ // MIs[1] Operand 1
25178 /* 69315 */ // No operand predicates
25179 /* 69315 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25180 /* 69317 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3836:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)
25181 /* 69317 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25182 /* 69320 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25183 /* 69324 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25184 /* 69329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32_fix),
25185 /* 69332 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25186 /* 69334 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25187 /* 69336 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25188 /* 69339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25189 /* 69342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25190 /* 69348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25191 /* 69354 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25192 /* 69357 */ GIR_RootConstrainSelectedInstOperands,
25193 /* 69358 */ // GIR_Coverage, 4507,
25194 /* 69358 */ GIR_EraseRootFromParent_Done,
25195 /* 69359 */ // Label 2149: @69359
25196 /* 69359 */ GIM_Reject,
25197 /* 69360 */ // Label 2147: @69360
25198 /* 69360 */ GIM_Reject,
25199 /* 69361 */ // Label 2143: @69361
25200 /* 69361 */ GIM_Reject,
25201 /* 69362 */ // Label 2135: @69362
25202 /* 69362 */ GIM_Reject,
25203 /* 69363 */ // Label 2132: @69363
25204 /* 69363 */ GIM_Try, /*On fail goto*//*Label 2150*/ GIMT_Encode4(69699),
25205 /* 69368 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
25206 /* 69373 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
25207 /* 69376 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25208 /* 69379 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2154*/ GIMT_Encode4(69698),
25209 /* 69390 */ /*GILLT_v16s8*//*Label 2151*/ GIMT_Encode4(69410), GIMT_Encode4(0),
25210 /* 69398 */ /*GILLT_v8s16*//*Label 2152*/ GIMT_Encode4(69506), GIMT_Encode4(0),
25211 /* 69406 */ /*GILLT_v4s32*//*Label 2153*/ GIMT_Encode4(69602),
25212 /* 69410 */ // Label 2151: @69410
25213 /* 69410 */ GIM_Try, /*On fail goto*//*Label 2155*/ GIMT_Encode4(69505),
25214 /* 69415 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25215 /* 69418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25216 /* 69422 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25217 /* 69426 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25218 /* 69430 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2156*/ GIMT_Encode4(69467), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3512 //
25219 /* 69437 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25220 /* 69441 */ // (intrinsic_wo_chain:{ *:[i32] } 3782:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25221 /* 69441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8),
25222 /* 69444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25223 /* 69446 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25224 /* 69448 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25225 /* 69450 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25226 /* 69453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25227 /* 69459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25228 /* 69465 */ GIR_RootConstrainSelectedInstOperands,
25229 /* 69466 */ // GIR_Coverage, 3512,
25230 /* 69466 */ GIR_EraseRootFromParent_Done,
25231 /* 69467 */ // Label 2156: @69467
25232 /* 69467 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2157*/ GIMT_Encode4(69504), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3518 //
25233 /* 69474 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25234 /* 69478 */ // (intrinsic_wo_chain:{ *:[i32] } 3782:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25235 /* 69478 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8),
25236 /* 69481 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25237 /* 69483 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25238 /* 69485 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25239 /* 69487 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25240 /* 69490 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25241 /* 69496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25242 /* 69502 */ GIR_RootConstrainSelectedInstOperands,
25243 /* 69503 */ // GIR_Coverage, 3518,
25244 /* 69503 */ GIR_EraseRootFromParent_Done,
25245 /* 69504 */ // Label 2157: @69504
25246 /* 69504 */ GIM_Reject,
25247 /* 69505 */ // Label 2155: @69505
25248 /* 69505 */ GIM_Reject,
25249 /* 69506 */ // Label 2152: @69506
25250 /* 69506 */ GIM_Try, /*On fail goto*//*Label 2158*/ GIMT_Encode4(69601),
25251 /* 69511 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25252 /* 69514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25253 /* 69518 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25254 /* 69522 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25255 /* 69526 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2159*/ GIMT_Encode4(69563), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3514 //
25256 /* 69533 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25257 /* 69537 */ // (intrinsic_wo_chain:{ *:[i32] } 3782:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25258 /* 69537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16),
25259 /* 69540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25260 /* 69542 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25261 /* 69544 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25262 /* 69546 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25263 /* 69549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25264 /* 69555 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25265 /* 69561 */ GIR_RootConstrainSelectedInstOperands,
25266 /* 69562 */ // GIR_Coverage, 3514,
25267 /* 69562 */ GIR_EraseRootFromParent_Done,
25268 /* 69563 */ // Label 2159: @69563
25269 /* 69563 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2160*/ GIMT_Encode4(69600), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3520 //
25270 /* 69570 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25271 /* 69574 */ // (intrinsic_wo_chain:{ *:[i32] } 3782:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25272 /* 69574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16),
25273 /* 69577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25274 /* 69579 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25275 /* 69581 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25276 /* 69583 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25277 /* 69586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25278 /* 69592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25279 /* 69598 */ GIR_RootConstrainSelectedInstOperands,
25280 /* 69599 */ // GIR_Coverage, 3520,
25281 /* 69599 */ GIR_EraseRootFromParent_Done,
25282 /* 69600 */ // Label 2160: @69600
25283 /* 69600 */ GIM_Reject,
25284 /* 69601 */ // Label 2158: @69601
25285 /* 69601 */ GIM_Reject,
25286 /* 69602 */ // Label 2153: @69602
25287 /* 69602 */ GIM_Try, /*On fail goto*//*Label 2161*/ GIMT_Encode4(69697),
25288 /* 69607 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25289 /* 69610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25290 /* 69614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25291 /* 69618 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25292 /* 69622 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2162*/ GIMT_Encode4(69659), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3516 //
25293 /* 69629 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25294 /* 69633 */ // (intrinsic_wo_chain:{ *:[i32] } 3782:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25295 /* 69633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32),
25296 /* 69636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25297 /* 69638 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25298 /* 69640 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25299 /* 69642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25300 /* 69645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25301 /* 69651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25302 /* 69657 */ GIR_RootConstrainSelectedInstOperands,
25303 /* 69658 */ // GIR_Coverage, 3516,
25304 /* 69658 */ GIR_EraseRootFromParent_Done,
25305 /* 69659 */ // Label 2162: @69659
25306 /* 69659 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2163*/ GIMT_Encode4(69696), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3522 //
25307 /* 69666 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25308 /* 69670 */ // (intrinsic_wo_chain:{ *:[i32] } 3782:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25309 /* 69670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32),
25310 /* 69673 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25311 /* 69675 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25312 /* 69677 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25313 /* 69679 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25314 /* 69682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25315 /* 69688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25316 /* 69694 */ GIR_RootConstrainSelectedInstOperands,
25317 /* 69695 */ // GIR_Coverage, 3522,
25318 /* 69695 */ GIR_EraseRootFromParent_Done,
25319 /* 69696 */ // Label 2163: @69696
25320 /* 69696 */ GIM_Reject,
25321 /* 69697 */ // Label 2161: @69697
25322 /* 69697 */ GIM_Reject,
25323 /* 69698 */ // Label 2154: @69698
25324 /* 69698 */ GIM_Reject,
25325 /* 69699 */ // Label 2150: @69699
25326 /* 69699 */ GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(70035),
25327 /* 69704 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
25328 /* 69709 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
25329 /* 69712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25330 /* 69715 */ GIM_SwitchType, /*MI*/0, /*Op*/3, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2168*/ GIMT_Encode4(70034),
25331 /* 69726 */ /*GILLT_v16s8*//*Label 2165*/ GIMT_Encode4(69746), GIMT_Encode4(0),
25332 /* 69734 */ /*GILLT_v8s16*//*Label 2166*/ GIMT_Encode4(69842), GIMT_Encode4(0),
25333 /* 69742 */ /*GILLT_v4s32*//*Label 2167*/ GIMT_Encode4(69938),
25334 /* 69746 */ // Label 2165: @69746
25335 /* 69746 */ GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(69841),
25336 /* 69751 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25337 /* 69754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25338 /* 69758 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25339 /* 69762 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25340 /* 69766 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2170*/ GIMT_Encode4(69803), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3524 //
25341 /* 69773 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25342 /* 69777 */ // (intrinsic_wo_chain:{ *:[i32] } 3773:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25343 /* 69777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8),
25344 /* 69780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25345 /* 69782 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25346 /* 69784 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25347 /* 69786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25348 /* 69789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25349 /* 69795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25350 /* 69801 */ GIR_RootConstrainSelectedInstOperands,
25351 /* 69802 */ // GIR_Coverage, 3524,
25352 /* 69802 */ GIR_EraseRootFromParent_Done,
25353 /* 69803 */ // Label 2170: @69803
25354 /* 69803 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2171*/ GIMT_Encode4(69840), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3530 //
25355 /* 69810 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25356 /* 69814 */ // (intrinsic_wo_chain:{ *:[i32] } 3773:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
25357 /* 69814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8),
25358 /* 69817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25359 /* 69819 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25360 /* 69821 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25361 /* 69823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25362 /* 69826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25363 /* 69832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25364 /* 69838 */ GIR_RootConstrainSelectedInstOperands,
25365 /* 69839 */ // GIR_Coverage, 3530,
25366 /* 69839 */ GIR_EraseRootFromParent_Done,
25367 /* 69840 */ // Label 2171: @69840
25368 /* 69840 */ GIM_Reject,
25369 /* 69841 */ // Label 2169: @69841
25370 /* 69841 */ GIM_Reject,
25371 /* 69842 */ // Label 2166: @69842
25372 /* 69842 */ GIM_Try, /*On fail goto*//*Label 2172*/ GIMT_Encode4(69937),
25373 /* 69847 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25374 /* 69850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25375 /* 69854 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25376 /* 69858 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25377 /* 69862 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2173*/ GIMT_Encode4(69899), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3526 //
25378 /* 69869 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25379 /* 69873 */ // (intrinsic_wo_chain:{ *:[i32] } 3773:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25380 /* 69873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16),
25381 /* 69876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25382 /* 69878 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25383 /* 69880 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25384 /* 69882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25385 /* 69885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25386 /* 69891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25387 /* 69897 */ GIR_RootConstrainSelectedInstOperands,
25388 /* 69898 */ // GIR_Coverage, 3526,
25389 /* 69898 */ GIR_EraseRootFromParent_Done,
25390 /* 69899 */ // Label 2173: @69899
25391 /* 69899 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2174*/ GIMT_Encode4(69936), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3532 //
25392 /* 69906 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25393 /* 69910 */ // (intrinsic_wo_chain:{ *:[i32] } 3773:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
25394 /* 69910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16),
25395 /* 69913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25396 /* 69915 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25397 /* 69917 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25398 /* 69919 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25399 /* 69922 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25400 /* 69928 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25401 /* 69934 */ GIR_RootConstrainSelectedInstOperands,
25402 /* 69935 */ // GIR_Coverage, 3532,
25403 /* 69935 */ GIR_EraseRootFromParent_Done,
25404 /* 69936 */ // Label 2174: @69936
25405 /* 69936 */ GIM_Reject,
25406 /* 69937 */ // Label 2172: @69937
25407 /* 69937 */ GIM_Reject,
25408 /* 69938 */ // Label 2167: @69938
25409 /* 69938 */ GIM_Try, /*On fail goto*//*Label 2175*/ GIMT_Encode4(70033),
25410 /* 69943 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25411 /* 69946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25412 /* 69950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25413 /* 69954 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25414 /* 69958 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2176*/ GIMT_Encode4(69995), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3528 //
25415 /* 69965 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25416 /* 69969 */ // (intrinsic_wo_chain:{ *:[i32] } 3773:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25417 /* 69969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32),
25418 /* 69972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25419 /* 69974 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25420 /* 69976 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25421 /* 69978 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25422 /* 69981 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25423 /* 69987 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25424 /* 69993 */ GIR_RootConstrainSelectedInstOperands,
25425 /* 69994 */ // GIR_Coverage, 3528,
25426 /* 69994 */ GIR_EraseRootFromParent_Done,
25427 /* 69995 */ // Label 2176: @69995
25428 /* 69995 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2177*/ GIMT_Encode4(70032), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3534 //
25429 /* 70002 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25430 /* 70006 */ // (intrinsic_wo_chain:{ *:[i32] } 3773:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
25431 /* 70006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32),
25432 /* 70009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
25433 /* 70011 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
25434 /* 70013 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
25435 /* 70015 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25436 /* 70018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25437 /* 70024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25438 /* 70030 */ GIR_RootConstrainSelectedInstOperands,
25439 /* 70031 */ // GIR_Coverage, 3534,
25440 /* 70031 */ GIR_EraseRootFromParent_Done,
25441 /* 70032 */ // Label 2177: @70032
25442 /* 70032 */ GIM_Reject,
25443 /* 70033 */ // Label 2175: @70033
25444 /* 70033 */ GIM_Reject,
25445 /* 70034 */ // Label 2168: @70034
25446 /* 70034 */ GIM_Reject,
25447 /* 70035 */ // Label 2164: @70035
25448 /* 70035 */ GIM_Try, /*On fail goto*//*Label 2178*/ GIMT_Encode4(70473),
25449 /* 70040 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
25450 /* 70045 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2182*/ GIMT_Encode4(70472),
25451 /* 70056 */ /*GILLT_v16s8*//*Label 2179*/ GIMT_Encode4(70076), GIMT_Encode4(0),
25452 /* 70064 */ /*GILLT_v8s16*//*Label 2180*/ GIMT_Encode4(70208), GIMT_Encode4(0),
25453 /* 70072 */ /*GILLT_v4s32*//*Label 2181*/ GIMT_Encode4(70340),
25454 /* 70076 */ // Label 2179: @70076
25455 /* 70076 */ GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(70207),
25456 /* 70081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25457 /* 70084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25458 /* 70087 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25459 /* 70090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25460 /* 70094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25461 /* 70098 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25462 /* 70102 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2184*/ GIMT_Encode4(70154), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3945 //
25463 /* 70109 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25464 /* 70113 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3819:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25465 /* 70113 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25466 /* 70116 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25467 /* 70120 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25468 /* 70125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8),
25469 /* 70128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25470 /* 70130 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25471 /* 70132 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25472 /* 70134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25473 /* 70137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25474 /* 70143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25475 /* 70149 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25476 /* 70152 */ GIR_RootConstrainSelectedInstOperands,
25477 /* 70153 */ // GIR_Coverage, 3945,
25478 /* 70153 */ GIR_EraseRootFromParent_Done,
25479 /* 70154 */ // Label 2184: @70154
25480 /* 70154 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2185*/ GIMT_Encode4(70206), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3960 //
25481 /* 70161 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25482 /* 70165 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3819:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25483 /* 70165 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25484 /* 70168 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25485 /* 70172 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25486 /* 70177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8),
25487 /* 70180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25488 /* 70182 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25489 /* 70184 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25490 /* 70186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25491 /* 70189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25492 /* 70195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25493 /* 70201 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25494 /* 70204 */ GIR_RootConstrainSelectedInstOperands,
25495 /* 70205 */ // GIR_Coverage, 3960,
25496 /* 70205 */ GIR_EraseRootFromParent_Done,
25497 /* 70206 */ // Label 2185: @70206
25498 /* 70206 */ GIM_Reject,
25499 /* 70207 */ // Label 2183: @70207
25500 /* 70207 */ GIM_Reject,
25501 /* 70208 */ // Label 2180: @70208
25502 /* 70208 */ GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(70339),
25503 /* 70213 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25504 /* 70216 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25505 /* 70219 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25506 /* 70222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25507 /* 70226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25508 /* 70230 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25509 /* 70234 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2187*/ GIMT_Encode4(70286), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3952 //
25510 /* 70241 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25511 /* 70245 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3819:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25512 /* 70245 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25513 /* 70248 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25514 /* 70252 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25515 /* 70257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16),
25516 /* 70260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25517 /* 70262 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25518 /* 70264 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25519 /* 70266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25520 /* 70269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25521 /* 70275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25522 /* 70281 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25523 /* 70284 */ GIR_RootConstrainSelectedInstOperands,
25524 /* 70285 */ // GIR_Coverage, 3952,
25525 /* 70285 */ GIR_EraseRootFromParent_Done,
25526 /* 70286 */ // Label 2187: @70286
25527 /* 70286 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2188*/ GIMT_Encode4(70338), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3964 //
25528 /* 70293 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25529 /* 70297 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3819:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25530 /* 70297 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25531 /* 70300 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25532 /* 70304 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25533 /* 70309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16),
25534 /* 70312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25535 /* 70314 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25536 /* 70316 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25537 /* 70318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25538 /* 70321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25539 /* 70327 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25540 /* 70333 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25541 /* 70336 */ GIR_RootConstrainSelectedInstOperands,
25542 /* 70337 */ // GIR_Coverage, 3964,
25543 /* 70337 */ GIR_EraseRootFromParent_Done,
25544 /* 70338 */ // Label 2188: @70338
25545 /* 70338 */ GIM_Reject,
25546 /* 70339 */ // Label 2186: @70339
25547 /* 70339 */ GIM_Reject,
25548 /* 70340 */ // Label 2181: @70340
25549 /* 70340 */ GIM_Try, /*On fail goto*//*Label 2189*/ GIMT_Encode4(70471),
25550 /* 70345 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25551 /* 70348 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25552 /* 70351 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25553 /* 70354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25554 /* 70358 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25555 /* 70362 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25556 /* 70366 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2190*/ GIMT_Encode4(70418), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3956 //
25557 /* 70373 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25558 /* 70377 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3819:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25559 /* 70377 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25560 /* 70380 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25561 /* 70384 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25562 /* 70389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32),
25563 /* 70392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25564 /* 70394 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25565 /* 70396 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25566 /* 70398 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25567 /* 70401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25568 /* 70407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25569 /* 70413 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25570 /* 70416 */ GIR_RootConstrainSelectedInstOperands,
25571 /* 70417 */ // GIR_Coverage, 3956,
25572 /* 70417 */ GIR_EraseRootFromParent_Done,
25573 /* 70418 */ // Label 2190: @70418
25574 /* 70418 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2191*/ GIMT_Encode4(70470), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3968 //
25575 /* 70425 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25576 /* 70429 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3819:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25577 /* 70429 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25578 /* 70432 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25579 /* 70436 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25580 /* 70441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32),
25581 /* 70444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25582 /* 70446 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25583 /* 70448 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25584 /* 70450 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25585 /* 70453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25586 /* 70459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25587 /* 70465 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25588 /* 70468 */ GIR_RootConstrainSelectedInstOperands,
25589 /* 70469 */ // GIR_Coverage, 3968,
25590 /* 70469 */ GIR_EraseRootFromParent_Done,
25591 /* 70470 */ // Label 2191: @70470
25592 /* 70470 */ GIM_Reject,
25593 /* 70471 */ // Label 2189: @70471
25594 /* 70471 */ GIM_Reject,
25595 /* 70472 */ // Label 2182: @70472
25596 /* 70472 */ GIM_Reject,
25597 /* 70473 */ // Label 2178: @70473
25598 /* 70473 */ GIM_Try, /*On fail goto*//*Label 2192*/ GIMT_Encode4(70911),
25599 /* 70478 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
25600 /* 70483 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2196*/ GIMT_Encode4(70910),
25601 /* 70494 */ /*GILLT_v16s8*//*Label 2193*/ GIMT_Encode4(70514), GIMT_Encode4(0),
25602 /* 70502 */ /*GILLT_v8s16*//*Label 2194*/ GIMT_Encode4(70646), GIMT_Encode4(0),
25603 /* 70510 */ /*GILLT_v4s32*//*Label 2195*/ GIMT_Encode4(70778),
25604 /* 70514 */ // Label 2193: @70514
25605 /* 70514 */ GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(70645),
25606 /* 70519 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25607 /* 70522 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25608 /* 70525 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25609 /* 70528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25610 /* 70532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25611 /* 70536 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25612 /* 70540 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2198*/ GIMT_Encode4(70592), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3969 //
25613 /* 70547 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25614 /* 70551 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3911:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25615 /* 70551 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25616 /* 70554 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25617 /* 70558 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25618 /* 70563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8),
25619 /* 70566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25620 /* 70568 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25621 /* 70570 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25622 /* 70572 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25623 /* 70575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25624 /* 70581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25625 /* 70587 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25626 /* 70590 */ GIR_RootConstrainSelectedInstOperands,
25627 /* 70591 */ // GIR_Coverage, 3969,
25628 /* 70591 */ GIR_EraseRootFromParent_Done,
25629 /* 70592 */ // Label 2198: @70592
25630 /* 70592 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2199*/ GIMT_Encode4(70644), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3984 //
25631 /* 70599 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25632 /* 70603 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3911:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25633 /* 70603 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25634 /* 70606 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25635 /* 70610 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25636 /* 70615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8),
25637 /* 70618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25638 /* 70620 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25639 /* 70622 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25640 /* 70624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25641 /* 70627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25642 /* 70633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25643 /* 70639 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25644 /* 70642 */ GIR_RootConstrainSelectedInstOperands,
25645 /* 70643 */ // GIR_Coverage, 3984,
25646 /* 70643 */ GIR_EraseRootFromParent_Done,
25647 /* 70644 */ // Label 2199: @70644
25648 /* 70644 */ GIM_Reject,
25649 /* 70645 */ // Label 2197: @70645
25650 /* 70645 */ GIM_Reject,
25651 /* 70646 */ // Label 2194: @70646
25652 /* 70646 */ GIM_Try, /*On fail goto*//*Label 2200*/ GIMT_Encode4(70777),
25653 /* 70651 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25654 /* 70654 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25655 /* 70657 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25656 /* 70660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25657 /* 70664 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25658 /* 70668 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25659 /* 70672 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2201*/ GIMT_Encode4(70724), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3976 //
25660 /* 70679 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25661 /* 70683 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3911:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25662 /* 70683 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25663 /* 70686 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25664 /* 70690 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25665 /* 70695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16),
25666 /* 70698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25667 /* 70700 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25668 /* 70702 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25669 /* 70704 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25670 /* 70707 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25671 /* 70713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25672 /* 70719 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25673 /* 70722 */ GIR_RootConstrainSelectedInstOperands,
25674 /* 70723 */ // GIR_Coverage, 3976,
25675 /* 70723 */ GIR_EraseRootFromParent_Done,
25676 /* 70724 */ // Label 2201: @70724
25677 /* 70724 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2202*/ GIMT_Encode4(70776), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3988 //
25678 /* 70731 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25679 /* 70735 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3911:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25680 /* 70735 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25681 /* 70738 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25682 /* 70742 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25683 /* 70747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16),
25684 /* 70750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25685 /* 70752 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25686 /* 70754 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25687 /* 70756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25688 /* 70759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25689 /* 70765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25690 /* 70771 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25691 /* 70774 */ GIR_RootConstrainSelectedInstOperands,
25692 /* 70775 */ // GIR_Coverage, 3988,
25693 /* 70775 */ GIR_EraseRootFromParent_Done,
25694 /* 70776 */ // Label 2202: @70776
25695 /* 70776 */ GIM_Reject,
25696 /* 70777 */ // Label 2200: @70777
25697 /* 70777 */ GIM_Reject,
25698 /* 70778 */ // Label 2195: @70778
25699 /* 70778 */ GIM_Try, /*On fail goto*//*Label 2203*/ GIMT_Encode4(70909),
25700 /* 70783 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25701 /* 70786 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25702 /* 70789 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25703 /* 70792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25704 /* 70796 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25705 /* 70800 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25706 /* 70804 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2204*/ GIMT_Encode4(70856), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3980 //
25707 /* 70811 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25708 /* 70815 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3911:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25709 /* 70815 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25710 /* 70818 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25711 /* 70822 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25712 /* 70827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32),
25713 /* 70830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25714 /* 70832 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25715 /* 70834 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25716 /* 70836 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25717 /* 70839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25718 /* 70845 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25719 /* 70851 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25720 /* 70854 */ GIR_RootConstrainSelectedInstOperands,
25721 /* 70855 */ // GIR_Coverage, 3980,
25722 /* 70855 */ GIR_EraseRootFromParent_Done,
25723 /* 70856 */ // Label 2204: @70856
25724 /* 70856 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2205*/ GIMT_Encode4(70908), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3992 //
25725 /* 70863 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25726 /* 70867 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3911:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25727 /* 70867 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25728 /* 70870 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25729 /* 70874 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25730 /* 70879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32),
25731 /* 70882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25732 /* 70884 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25733 /* 70886 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25734 /* 70888 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25735 /* 70891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25736 /* 70897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25737 /* 70903 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25738 /* 70906 */ GIR_RootConstrainSelectedInstOperands,
25739 /* 70907 */ // GIR_Coverage, 3992,
25740 /* 70907 */ GIR_EraseRootFromParent_Done,
25741 /* 70908 */ // Label 2205: @70908
25742 /* 70908 */ GIM_Reject,
25743 /* 70909 */ // Label 2203: @70909
25744 /* 70909 */ GIM_Reject,
25745 /* 70910 */ // Label 2196: @70910
25746 /* 70910 */ GIM_Reject,
25747 /* 70911 */ // Label 2192: @70911
25748 /* 70911 */ GIM_Try, /*On fail goto*//*Label 2206*/ GIMT_Encode4(71349),
25749 /* 70916 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
25750 /* 70921 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2210*/ GIMT_Encode4(71348),
25751 /* 70932 */ /*GILLT_v16s8*//*Label 2207*/ GIMT_Encode4(70952), GIMT_Encode4(0),
25752 /* 70940 */ /*GILLT_v8s16*//*Label 2208*/ GIMT_Encode4(71084), GIMT_Encode4(0),
25753 /* 70948 */ /*GILLT_v4s32*//*Label 2209*/ GIMT_Encode4(71216),
25754 /* 70952 */ // Label 2207: @70952
25755 /* 70952 */ GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(71083),
25756 /* 70957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25757 /* 70960 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25758 /* 70963 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25759 /* 70966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25760 /* 70970 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25761 /* 70974 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25762 /* 70978 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2212*/ GIMT_Encode4(71030), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3993 //
25763 /* 70985 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25764 /* 70989 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3857:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25765 /* 70989 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25766 /* 70992 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25767 /* 70996 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25768 /* 71001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8),
25769 /* 71004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25770 /* 71006 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25771 /* 71008 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25772 /* 71010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25773 /* 71013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25774 /* 71019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25775 /* 71025 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25776 /* 71028 */ GIR_RootConstrainSelectedInstOperands,
25777 /* 71029 */ // GIR_Coverage, 3993,
25778 /* 71029 */ GIR_EraseRootFromParent_Done,
25779 /* 71030 */ // Label 2212: @71030
25780 /* 71030 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2213*/ GIMT_Encode4(71082), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4008 //
25781 /* 71037 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25782 /* 71041 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3857:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25783 /* 71041 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25784 /* 71044 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25785 /* 71048 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25786 /* 71053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8),
25787 /* 71056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25788 /* 71058 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25789 /* 71060 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25790 /* 71062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25791 /* 71065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25792 /* 71071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25793 /* 71077 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25794 /* 71080 */ GIR_RootConstrainSelectedInstOperands,
25795 /* 71081 */ // GIR_Coverage, 4008,
25796 /* 71081 */ GIR_EraseRootFromParent_Done,
25797 /* 71082 */ // Label 2213: @71082
25798 /* 71082 */ GIM_Reject,
25799 /* 71083 */ // Label 2211: @71083
25800 /* 71083 */ GIM_Reject,
25801 /* 71084 */ // Label 2208: @71084
25802 /* 71084 */ GIM_Try, /*On fail goto*//*Label 2214*/ GIMT_Encode4(71215),
25803 /* 71089 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25804 /* 71092 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25805 /* 71095 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25806 /* 71098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25807 /* 71102 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25808 /* 71106 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25809 /* 71110 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2215*/ GIMT_Encode4(71162), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4000 //
25810 /* 71117 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25811 /* 71121 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3857:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25812 /* 71121 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25813 /* 71124 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25814 /* 71128 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25815 /* 71133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16),
25816 /* 71136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25817 /* 71138 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25818 /* 71140 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25819 /* 71142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25820 /* 71145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25821 /* 71151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25822 /* 71157 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25823 /* 71160 */ GIR_RootConstrainSelectedInstOperands,
25824 /* 71161 */ // GIR_Coverage, 4000,
25825 /* 71161 */ GIR_EraseRootFromParent_Done,
25826 /* 71162 */ // Label 2215: @71162
25827 /* 71162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2216*/ GIMT_Encode4(71214), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4012 //
25828 /* 71169 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25829 /* 71173 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3857:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25830 /* 71173 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25831 /* 71176 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25832 /* 71180 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25833 /* 71185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16),
25834 /* 71188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25835 /* 71190 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25836 /* 71192 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25837 /* 71194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25838 /* 71197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25839 /* 71203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25840 /* 71209 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25841 /* 71212 */ GIR_RootConstrainSelectedInstOperands,
25842 /* 71213 */ // GIR_Coverage, 4012,
25843 /* 71213 */ GIR_EraseRootFromParent_Done,
25844 /* 71214 */ // Label 2216: @71214
25845 /* 71214 */ GIM_Reject,
25846 /* 71215 */ // Label 2214: @71215
25847 /* 71215 */ GIM_Reject,
25848 /* 71216 */ // Label 2209: @71216
25849 /* 71216 */ GIM_Try, /*On fail goto*//*Label 2217*/ GIMT_Encode4(71347),
25850 /* 71221 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25851 /* 71224 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25852 /* 71227 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25853 /* 71230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25854 /* 71234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25855 /* 71238 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25856 /* 71242 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2218*/ GIMT_Encode4(71294), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4004 //
25857 /* 71249 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25858 /* 71253 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3857:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25859 /* 71253 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25860 /* 71256 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25861 /* 71260 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25862 /* 71265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32),
25863 /* 71268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25864 /* 71270 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25865 /* 71272 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25866 /* 71274 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25867 /* 71277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25868 /* 71283 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25869 /* 71289 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25870 /* 71292 */ GIR_RootConstrainSelectedInstOperands,
25871 /* 71293 */ // GIR_Coverage, 4004,
25872 /* 71293 */ GIR_EraseRootFromParent_Done,
25873 /* 71294 */ // Label 2218: @71294
25874 /* 71294 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2219*/ GIMT_Encode4(71346), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4016 //
25875 /* 71301 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25876 /* 71305 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3857:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
25877 /* 71305 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25878 /* 71308 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25879 /* 71312 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25880 /* 71317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32),
25881 /* 71320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25882 /* 71322 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25883 /* 71324 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25884 /* 71326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25885 /* 71329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25886 /* 71335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25887 /* 71341 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25888 /* 71344 */ GIR_RootConstrainSelectedInstOperands,
25889 /* 71345 */ // GIR_Coverage, 4016,
25890 /* 71345 */ GIR_EraseRootFromParent_Done,
25891 /* 71346 */ // Label 2219: @71346
25892 /* 71346 */ GIM_Reject,
25893 /* 71347 */ // Label 2217: @71347
25894 /* 71347 */ GIM_Reject,
25895 /* 71348 */ // Label 2210: @71348
25896 /* 71348 */ GIM_Reject,
25897 /* 71349 */ // Label 2206: @71349
25898 /* 71349 */ GIM_Try, /*On fail goto*//*Label 2220*/ GIMT_Encode4(71787),
25899 /* 71354 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
25900 /* 71359 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2224*/ GIMT_Encode4(71786),
25901 /* 71370 */ /*GILLT_v16s8*//*Label 2221*/ GIMT_Encode4(71390), GIMT_Encode4(0),
25902 /* 71378 */ /*GILLT_v8s16*//*Label 2222*/ GIMT_Encode4(71522), GIMT_Encode4(0),
25903 /* 71386 */ /*GILLT_v4s32*//*Label 2223*/ GIMT_Encode4(71654),
25904 /* 71390 */ // Label 2221: @71390
25905 /* 71390 */ GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(71521),
25906 /* 71395 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25907 /* 71398 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
25908 /* 71401 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25909 /* 71404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25910 /* 71408 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25911 /* 71412 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25912 /* 71416 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2226*/ GIMT_Encode4(71468), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4017 //
25913 /* 71423 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25914 /* 71427 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3858:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25915 /* 71427 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25916 /* 71430 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25917 /* 71434 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25918 /* 71439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs8),
25919 /* 71442 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25920 /* 71444 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25921 /* 71446 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25922 /* 71448 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25923 /* 71451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25924 /* 71457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25925 /* 71463 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25926 /* 71466 */ GIR_RootConstrainSelectedInstOperands,
25927 /* 71467 */ // GIR_Coverage, 4017,
25928 /* 71467 */ GIR_EraseRootFromParent_Done,
25929 /* 71468 */ // Label 2226: @71468
25930 /* 71468 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2227*/ GIMT_Encode4(71520), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4026 //
25931 /* 71475 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25932 /* 71479 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3858:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
25933 /* 71479 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25934 /* 71482 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25935 /* 71486 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25936 /* 71491 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu8),
25937 /* 71494 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25938 /* 71496 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25939 /* 71498 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25940 /* 71500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25941 /* 71503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25942 /* 71509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25943 /* 71515 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25944 /* 71518 */ GIR_RootConstrainSelectedInstOperands,
25945 /* 71519 */ // GIR_Coverage, 4026,
25946 /* 71519 */ GIR_EraseRootFromParent_Done,
25947 /* 71520 */ // Label 2227: @71520
25948 /* 71520 */ GIM_Reject,
25949 /* 71521 */ // Label 2225: @71521
25950 /* 71521 */ GIM_Reject,
25951 /* 71522 */ // Label 2222: @71522
25952 /* 71522 */ GIM_Try, /*On fail goto*//*Label 2228*/ GIMT_Encode4(71653),
25953 /* 71527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25954 /* 71530 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25955 /* 71533 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25956 /* 71536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25957 /* 71540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25958 /* 71544 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25959 /* 71548 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2229*/ GIMT_Encode4(71600), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4020 //
25960 /* 71555 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25961 /* 71559 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3858:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25962 /* 71559 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25963 /* 71562 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25964 /* 71566 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25965 /* 71571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs16),
25966 /* 71574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25967 /* 71576 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25968 /* 71578 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25969 /* 71580 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25970 /* 71583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25971 /* 71589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25972 /* 71595 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25973 /* 71598 */ GIR_RootConstrainSelectedInstOperands,
25974 /* 71599 */ // GIR_Coverage, 4020,
25975 /* 71599 */ GIR_EraseRootFromParent_Done,
25976 /* 71600 */ // Label 2229: @71600
25977 /* 71600 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2230*/ GIMT_Encode4(71652), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4029 //
25978 /* 71607 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25979 /* 71611 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3858:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
25980 /* 71611 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25981 /* 71614 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25982 /* 71618 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25983 /* 71623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu16),
25984 /* 71626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25985 /* 71628 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25986 /* 71630 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25987 /* 71632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25988 /* 71635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25989 /* 71641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25990 /* 71647 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25991 /* 71650 */ GIR_RootConstrainSelectedInstOperands,
25992 /* 71651 */ // GIR_Coverage, 4029,
25993 /* 71651 */ GIR_EraseRootFromParent_Done,
25994 /* 71652 */ // Label 2230: @71652
25995 /* 71652 */ GIM_Reject,
25996 /* 71653 */ // Label 2228: @71653
25997 /* 71653 */ GIM_Reject,
25998 /* 71654 */ // Label 2223: @71654
25999 /* 71654 */ GIM_Try, /*On fail goto*//*Label 2231*/ GIMT_Encode4(71785),
26000 /* 71659 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26001 /* 71662 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26002 /* 71665 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26003 /* 71668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26004 /* 71672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26005 /* 71676 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26006 /* 71680 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2232*/ GIMT_Encode4(71732), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4023 //
26007 /* 71687 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26008 /* 71691 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3858:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26009 /* 71691 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26010 /* 71694 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26011 /* 71698 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26012 /* 71703 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs32),
26013 /* 71706 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26014 /* 71708 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26015 /* 71710 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26016 /* 71712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26017 /* 71715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26018 /* 71721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26019 /* 71727 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26020 /* 71730 */ GIR_RootConstrainSelectedInstOperands,
26021 /* 71731 */ // GIR_Coverage, 4023,
26022 /* 71731 */ GIR_EraseRootFromParent_Done,
26023 /* 71732 */ // Label 2232: @71732
26024 /* 71732 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2233*/ GIMT_Encode4(71784), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4032 //
26025 /* 71739 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26026 /* 71743 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3858:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26027 /* 71743 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26028 /* 71746 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26029 /* 71750 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26030 /* 71755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu32),
26031 /* 71758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26032 /* 71760 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26033 /* 71762 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26034 /* 71764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26035 /* 71767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26036 /* 71773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26037 /* 71779 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26038 /* 71782 */ GIR_RootConstrainSelectedInstOperands,
26039 /* 71783 */ // GIR_Coverage, 4032,
26040 /* 71783 */ GIR_EraseRootFromParent_Done,
26041 /* 71784 */ // Label 2233: @71784
26042 /* 71784 */ GIM_Reject,
26043 /* 71785 */ // Label 2231: @71785
26044 /* 71785 */ GIM_Reject,
26045 /* 71786 */ // Label 2224: @71786
26046 /* 71786 */ GIM_Reject,
26047 /* 71787 */ // Label 2220: @71787
26048 /* 71787 */ GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(71969),
26049 /* 71792 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26050 /* 71797 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2237*/ GIMT_Encode4(71968),
26051 /* 71808 */ /*GILLT_v8s16*//*Label 2235*/ GIMT_Encode4(71820), GIMT_Encode4(0),
26052 /* 71816 */ /*GILLT_v4s32*//*Label 2236*/ GIMT_Encode4(71894),
26053 /* 71820 */ // Label 2235: @71820
26054 /* 71820 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2238*/ GIMT_Encode4(71893), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4489 //
26055 /* 71827 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26056 /* 71830 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26057 /* 71833 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26058 /* 71836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26059 /* 71840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26060 /* 71844 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26061 /* 71848 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26062 /* 71852 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3819:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
26063 /* 71852 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26064 /* 71855 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26065 /* 71859 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26066 /* 71864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16),
26067 /* 71867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26068 /* 71869 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26069 /* 71871 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26070 /* 71873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26071 /* 71876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26072 /* 71882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26073 /* 71888 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26074 /* 71891 */ GIR_RootConstrainSelectedInstOperands,
26075 /* 71892 */ // GIR_Coverage, 4489,
26076 /* 71892 */ GIR_EraseRootFromParent_Done,
26077 /* 71893 */ // Label 2238: @71893
26078 /* 71893 */ GIM_Reject,
26079 /* 71894 */ // Label 2236: @71894
26080 /* 71894 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2239*/ GIMT_Encode4(71967), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4487 //
26081 /* 71901 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26082 /* 71904 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26083 /* 71907 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26084 /* 71910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26085 /* 71914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26086 /* 71918 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26087 /* 71922 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26088 /* 71926 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3819:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
26089 /* 71926 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26090 /* 71929 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26091 /* 71933 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26092 /* 71938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32),
26093 /* 71941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26094 /* 71943 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26095 /* 71945 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26096 /* 71947 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26097 /* 71950 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26098 /* 71956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26099 /* 71962 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26100 /* 71965 */ GIR_RootConstrainSelectedInstOperands,
26101 /* 71966 */ // GIR_Coverage, 4487,
26102 /* 71966 */ GIR_EraseRootFromParent_Done,
26103 /* 71967 */ // Label 2239: @71967
26104 /* 71967 */ GIM_Reject,
26105 /* 71968 */ // Label 2237: @71968
26106 /* 71968 */ GIM_Reject,
26107 /* 71969 */ // Label 2234: @71969
26108 /* 71969 */ GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(72267),
26109 /* 71974 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly),
26110 /* 71979 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2243*/ GIMT_Encode4(72266),
26111 /* 71990 */ /*GILLT_v8s16*//*Label 2241*/ GIMT_Encode4(72002), GIMT_Encode4(0),
26112 /* 71998 */ /*GILLT_v4s32*//*Label 2242*/ GIMT_Encode4(72134),
26113 /* 72002 */ // Label 2241: @72002
26114 /* 72002 */ GIM_Try, /*On fail goto*//*Label 2244*/ GIMT_Encode4(72133),
26115 /* 72007 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26116 /* 72010 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26117 /* 72013 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26118 /* 72016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26119 /* 72020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26120 /* 72024 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26121 /* 72028 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2245*/ GIMT_Encode4(72080), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4922 //
26122 /* 72035 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26123 /* 72039 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3888:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26124 /* 72039 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26125 /* 72042 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26126 /* 72046 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26127 /* 72051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp8),
26128 /* 72054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26129 /* 72056 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26130 /* 72058 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26131 /* 72060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26132 /* 72063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26133 /* 72069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26134 /* 72075 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26135 /* 72078 */ GIR_RootConstrainSelectedInstOperands,
26136 /* 72079 */ // GIR_Coverage, 4922,
26137 /* 72079 */ GIR_EraseRootFromParent_Done,
26138 /* 72080 */ // Label 2245: @72080
26139 /* 72080 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2246*/ GIMT_Encode4(72132), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4924 //
26140 /* 72087 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26141 /* 72091 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3888:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26142 /* 72091 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26143 /* 72094 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26144 /* 72098 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26145 /* 72103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp8),
26146 /* 72106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26147 /* 72108 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26148 /* 72110 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26149 /* 72112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26150 /* 72115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26151 /* 72121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26152 /* 72127 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26153 /* 72130 */ GIR_RootConstrainSelectedInstOperands,
26154 /* 72131 */ // GIR_Coverage, 4924,
26155 /* 72131 */ GIR_EraseRootFromParent_Done,
26156 /* 72132 */ // Label 2246: @72132
26157 /* 72132 */ GIM_Reject,
26158 /* 72133 */ // Label 2244: @72133
26159 /* 72133 */ GIM_Reject,
26160 /* 72134 */ // Label 2242: @72134
26161 /* 72134 */ GIM_Try, /*On fail goto*//*Label 2247*/ GIMT_Encode4(72265),
26162 /* 72139 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26163 /* 72142 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26164 /* 72145 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26165 /* 72148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26166 /* 72152 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26167 /* 72156 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26168 /* 72160 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2248*/ GIMT_Encode4(72212), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4926 //
26169 /* 72167 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26170 /* 72171 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3888:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26171 /* 72171 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26172 /* 72174 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26173 /* 72178 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26174 /* 72183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp16),
26175 /* 72186 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26176 /* 72188 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26177 /* 72190 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26178 /* 72192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26179 /* 72195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26180 /* 72201 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26181 /* 72207 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26182 /* 72210 */ GIR_RootConstrainSelectedInstOperands,
26183 /* 72211 */ // GIR_Coverage, 4926,
26184 /* 72211 */ GIR_EraseRootFromParent_Done,
26185 /* 72212 */ // Label 2248: @72212
26186 /* 72212 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2249*/ GIMT_Encode4(72264), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4928 //
26187 /* 72219 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26188 /* 72223 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3888:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26189 /* 72223 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26190 /* 72226 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26191 /* 72230 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26192 /* 72235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp16),
26193 /* 72238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26194 /* 72240 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26195 /* 72242 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26196 /* 72244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26197 /* 72247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26198 /* 72253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26199 /* 72259 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26200 /* 72262 */ GIR_RootConstrainSelectedInstOperands,
26201 /* 72263 */ // GIR_Coverage, 4928,
26202 /* 72263 */ GIR_EraseRootFromParent_Done,
26203 /* 72264 */ // Label 2249: @72264
26204 /* 72264 */ GIM_Reject,
26205 /* 72265 */ // Label 2247: @72265
26206 /* 72265 */ GIM_Reject,
26207 /* 72266 */ // Label 2243: @72266
26208 /* 72266 */ GIM_Reject,
26209 /* 72267 */ // Label 2240: @72267
26210 /* 72267 */ GIM_Try, /*On fail goto*//*Label 2250*/ GIMT_Encode4(72705),
26211 /* 72272 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
26212 /* 72277 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2254*/ GIMT_Encode4(72704),
26213 /* 72288 */ /*GILLT_v16s8*//*Label 2251*/ GIMT_Encode4(72308), GIMT_Encode4(0),
26214 /* 72296 */ /*GILLT_v8s16*//*Label 2252*/ GIMT_Encode4(72440), GIMT_Encode4(0),
26215 /* 72304 */ /*GILLT_v4s32*//*Label 2253*/ GIMT_Encode4(72572),
26216 /* 72308 */ // Label 2251: @72308
26217 /* 72308 */ GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(72439),
26218 /* 72313 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26219 /* 72316 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26220 /* 72319 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26221 /* 72322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26222 /* 72326 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26223 /* 72330 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26224 /* 72334 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2256*/ GIMT_Encode4(72386), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4955 //
26225 /* 72341 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26226 /* 72345 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3886:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26227 /* 72345 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26228 /* 72348 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26229 /* 72352 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26230 /* 72357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8),
26231 /* 72360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26232 /* 72362 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26233 /* 72364 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26234 /* 72366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26235 /* 72369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26236 /* 72375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26237 /* 72381 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26238 /* 72384 */ GIR_RootConstrainSelectedInstOperands,
26239 /* 72385 */ // GIR_Coverage, 4955,
26240 /* 72385 */ GIR_EraseRootFromParent_Done,
26241 /* 72386 */ // Label 2256: @72386
26242 /* 72386 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2257*/ GIMT_Encode4(72438), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4970 //
26243 /* 72393 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26244 /* 72397 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3886:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26245 /* 72397 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26246 /* 72400 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26247 /* 72404 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26248 /* 72409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8),
26249 /* 72412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26250 /* 72414 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26251 /* 72416 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26252 /* 72418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26253 /* 72421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26254 /* 72427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26255 /* 72433 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26256 /* 72436 */ GIR_RootConstrainSelectedInstOperands,
26257 /* 72437 */ // GIR_Coverage, 4970,
26258 /* 72437 */ GIR_EraseRootFromParent_Done,
26259 /* 72438 */ // Label 2257: @72438
26260 /* 72438 */ GIM_Reject,
26261 /* 72439 */ // Label 2255: @72439
26262 /* 72439 */ GIM_Reject,
26263 /* 72440 */ // Label 2252: @72440
26264 /* 72440 */ GIM_Try, /*On fail goto*//*Label 2258*/ GIMT_Encode4(72571),
26265 /* 72445 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26266 /* 72448 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26267 /* 72451 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26268 /* 72454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26269 /* 72458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26270 /* 72462 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26271 /* 72466 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2259*/ GIMT_Encode4(72518), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4962 //
26272 /* 72473 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26273 /* 72477 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3886:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26274 /* 72477 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26275 /* 72480 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26276 /* 72484 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26277 /* 72489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16),
26278 /* 72492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26279 /* 72494 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26280 /* 72496 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26281 /* 72498 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26282 /* 72501 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26283 /* 72507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26284 /* 72513 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26285 /* 72516 */ GIR_RootConstrainSelectedInstOperands,
26286 /* 72517 */ // GIR_Coverage, 4962,
26287 /* 72517 */ GIR_EraseRootFromParent_Done,
26288 /* 72518 */ // Label 2259: @72518
26289 /* 72518 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2260*/ GIMT_Encode4(72570), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4974 //
26290 /* 72525 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26291 /* 72529 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3886:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26292 /* 72529 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26293 /* 72532 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26294 /* 72536 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26295 /* 72541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16),
26296 /* 72544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26297 /* 72546 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26298 /* 72548 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26299 /* 72550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26300 /* 72553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26301 /* 72559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26302 /* 72565 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26303 /* 72568 */ GIR_RootConstrainSelectedInstOperands,
26304 /* 72569 */ // GIR_Coverage, 4974,
26305 /* 72569 */ GIR_EraseRootFromParent_Done,
26306 /* 72570 */ // Label 2260: @72570
26307 /* 72570 */ GIM_Reject,
26308 /* 72571 */ // Label 2258: @72571
26309 /* 72571 */ GIM_Reject,
26310 /* 72572 */ // Label 2253: @72572
26311 /* 72572 */ GIM_Try, /*On fail goto*//*Label 2261*/ GIMT_Encode4(72703),
26312 /* 72577 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26313 /* 72580 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26314 /* 72583 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26315 /* 72586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26316 /* 72590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26317 /* 72594 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26318 /* 72598 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2262*/ GIMT_Encode4(72650), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4966 //
26319 /* 72605 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26320 /* 72609 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3886:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26321 /* 72609 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26322 /* 72612 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26323 /* 72616 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26324 /* 72621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32),
26325 /* 72624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26326 /* 72626 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26327 /* 72628 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26328 /* 72630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26329 /* 72633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26330 /* 72639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26331 /* 72645 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26332 /* 72648 */ GIR_RootConstrainSelectedInstOperands,
26333 /* 72649 */ // GIR_Coverage, 4966,
26334 /* 72649 */ GIR_EraseRootFromParent_Done,
26335 /* 72650 */ // Label 2262: @72650
26336 /* 72650 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2263*/ GIMT_Encode4(72702), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4978 //
26337 /* 72657 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26338 /* 72661 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3886:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26339 /* 72661 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26340 /* 72664 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26341 /* 72668 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26342 /* 72673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32),
26343 /* 72676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26344 /* 72678 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26345 /* 72680 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26346 /* 72682 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26347 /* 72685 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26348 /* 72691 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26349 /* 72697 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26350 /* 72700 */ GIR_RootConstrainSelectedInstOperands,
26351 /* 72701 */ // GIR_Coverage, 4978,
26352 /* 72701 */ GIR_EraseRootFromParent_Done,
26353 /* 72702 */ // Label 2263: @72702
26354 /* 72702 */ GIM_Reject,
26355 /* 72703 */ // Label 2261: @72703
26356 /* 72703 */ GIM_Reject,
26357 /* 72704 */ // Label 2254: @72704
26358 /* 72704 */ GIM_Reject,
26359 /* 72705 */ // Label 2250: @72705
26360 /* 72705 */ GIM_Try, /*On fail goto*//*Label 2264*/ GIMT_Encode4(73143),
26361 /* 72710 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
26362 /* 72715 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2268*/ GIMT_Encode4(73142),
26363 /* 72726 */ /*GILLT_v16s8*//*Label 2265*/ GIMT_Encode4(72746), GIMT_Encode4(0),
26364 /* 72734 */ /*GILLT_v8s16*//*Label 2266*/ GIMT_Encode4(72878), GIMT_Encode4(0),
26365 /* 72742 */ /*GILLT_v4s32*//*Label 2267*/ GIMT_Encode4(73010),
26366 /* 72746 */ // Label 2265: @72746
26367 /* 72746 */ GIM_Try, /*On fail goto*//*Label 2269*/ GIMT_Encode4(72877),
26368 /* 72751 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26369 /* 72754 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26370 /* 72757 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26371 /* 72760 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26372 /* 72764 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26373 /* 72768 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26374 /* 72772 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2270*/ GIMT_Encode4(72824), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4979 //
26375 /* 72779 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26376 /* 72783 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3926:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26377 /* 72783 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26378 /* 72786 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26379 /* 72790 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26380 /* 72795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs8),
26381 /* 72798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26382 /* 72800 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26383 /* 72802 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26384 /* 72804 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26385 /* 72807 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26386 /* 72813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26387 /* 72819 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26388 /* 72822 */ GIR_RootConstrainSelectedInstOperands,
26389 /* 72823 */ // GIR_Coverage, 4979,
26390 /* 72823 */ GIR_EraseRootFromParent_Done,
26391 /* 72824 */ // Label 2270: @72824
26392 /* 72824 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2271*/ GIMT_Encode4(72876), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4985 //
26393 /* 72831 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26394 /* 72835 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3926:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26395 /* 72835 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26396 /* 72838 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26397 /* 72842 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26398 /* 72847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu8),
26399 /* 72850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26400 /* 72852 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26401 /* 72854 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26402 /* 72856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26403 /* 72859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26404 /* 72865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26405 /* 72871 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26406 /* 72874 */ GIR_RootConstrainSelectedInstOperands,
26407 /* 72875 */ // GIR_Coverage, 4985,
26408 /* 72875 */ GIR_EraseRootFromParent_Done,
26409 /* 72876 */ // Label 2271: @72876
26410 /* 72876 */ GIM_Reject,
26411 /* 72877 */ // Label 2269: @72877
26412 /* 72877 */ GIM_Reject,
26413 /* 72878 */ // Label 2266: @72878
26414 /* 72878 */ GIM_Try, /*On fail goto*//*Label 2272*/ GIMT_Encode4(73009),
26415 /* 72883 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26416 /* 72886 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26417 /* 72889 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26418 /* 72892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26419 /* 72896 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26420 /* 72900 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26421 /* 72904 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2273*/ GIMT_Encode4(72956), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4981 //
26422 /* 72911 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26423 /* 72915 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3926:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26424 /* 72915 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26425 /* 72918 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26426 /* 72922 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26427 /* 72927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs16),
26428 /* 72930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26429 /* 72932 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26430 /* 72934 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26431 /* 72936 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26432 /* 72939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26433 /* 72945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26434 /* 72951 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26435 /* 72954 */ GIR_RootConstrainSelectedInstOperands,
26436 /* 72955 */ // GIR_Coverage, 4981,
26437 /* 72955 */ GIR_EraseRootFromParent_Done,
26438 /* 72956 */ // Label 2273: @72956
26439 /* 72956 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2274*/ GIMT_Encode4(73008), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4987 //
26440 /* 72963 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26441 /* 72967 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3926:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26442 /* 72967 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26443 /* 72970 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26444 /* 72974 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26445 /* 72979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu16),
26446 /* 72982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26447 /* 72984 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26448 /* 72986 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26449 /* 72988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26450 /* 72991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26451 /* 72997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26452 /* 73003 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26453 /* 73006 */ GIR_RootConstrainSelectedInstOperands,
26454 /* 73007 */ // GIR_Coverage, 4987,
26455 /* 73007 */ GIR_EraseRootFromParent_Done,
26456 /* 73008 */ // Label 2274: @73008
26457 /* 73008 */ GIM_Reject,
26458 /* 73009 */ // Label 2272: @73009
26459 /* 73009 */ GIM_Reject,
26460 /* 73010 */ // Label 2267: @73010
26461 /* 73010 */ GIM_Try, /*On fail goto*//*Label 2275*/ GIMT_Encode4(73141),
26462 /* 73015 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26463 /* 73018 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26464 /* 73021 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26465 /* 73024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26466 /* 73028 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26467 /* 73032 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26468 /* 73036 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2276*/ GIMT_Encode4(73088), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4983 //
26469 /* 73043 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26470 /* 73047 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3926:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26471 /* 73047 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26472 /* 73050 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26473 /* 73054 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26474 /* 73059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs32),
26475 /* 73062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26476 /* 73064 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26477 /* 73066 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26478 /* 73068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26479 /* 73071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26480 /* 73077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26481 /* 73083 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26482 /* 73086 */ GIR_RootConstrainSelectedInstOperands,
26483 /* 73087 */ // GIR_Coverage, 4983,
26484 /* 73087 */ GIR_EraseRootFromParent_Done,
26485 /* 73088 */ // Label 2276: @73088
26486 /* 73088 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2277*/ GIMT_Encode4(73140), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4989 //
26487 /* 73095 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26488 /* 73099 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3926:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26489 /* 73099 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26490 /* 73102 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26491 /* 73106 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26492 /* 73111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu32),
26493 /* 73114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26494 /* 73116 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26495 /* 73118 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26496 /* 73120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26497 /* 73123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26498 /* 73129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26499 /* 73135 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26500 /* 73138 */ GIR_RootConstrainSelectedInstOperands,
26501 /* 73139 */ // GIR_Coverage, 4989,
26502 /* 73139 */ GIR_EraseRootFromParent_Done,
26503 /* 73140 */ // Label 2277: @73140
26504 /* 73140 */ GIM_Reject,
26505 /* 73141 */ // Label 2275: @73141
26506 /* 73141 */ GIM_Reject,
26507 /* 73142 */ // Label 2268: @73142
26508 /* 73142 */ GIM_Reject,
26509 /* 73143 */ // Label 2264: @73143
26510 /* 73143 */ GIM_Try, /*On fail goto*//*Label 2278*/ GIMT_Encode4(73252),
26511 /* 73148 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow),
26512 /* 73153 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26513 /* 73156 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26514 /* 73159 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26515 /* 73162 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26516 /* 73165 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26517 /* 73169 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26518 /* 73173 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26519 /* 73177 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2279*/ GIMT_Encode4(73214), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5040 //
26520 /* 73184 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26521 /* 73188 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3841:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf16f32bh:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
26522 /* 73188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32bh),
26523 /* 73191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26524 /* 73193 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
26525 /* 73195 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
26526 /* 73197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26527 /* 73200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26528 /* 73206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26529 /* 73212 */ GIR_RootConstrainSelectedInstOperands,
26530 /* 73213 */ // GIR_Coverage, 5040,
26531 /* 73213 */ GIR_EraseRootFromParent_Done,
26532 /* 73214 */ // Label 2279: @73214
26533 /* 73214 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2280*/ GIMT_Encode4(73251), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5046 //
26534 /* 73221 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26535 /* 73225 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3841:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf16f32th:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
26536 /* 73225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32th),
26537 /* 73228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26538 /* 73230 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
26539 /* 73232 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
26540 /* 73234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26541 /* 73237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26542 /* 73243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26543 /* 73249 */ GIR_RootConstrainSelectedInstOperands,
26544 /* 73250 */ // GIR_Coverage, 5046,
26545 /* 73250 */ GIR_EraseRootFromParent_Done,
26546 /* 73251 */ // Label 2280: @73251
26547 /* 73251 */ GIM_Reject,
26548 /* 73252 */ // Label 2278: @73252
26549 /* 73252 */ GIM_Try, /*On fail goto*//*Label 2281*/ GIMT_Encode4(73546),
26550 /* 73257 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull),
26551 /* 73262 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2284*/ GIMT_Encode4(73545),
26552 /* 73273 */ /*GILLT_v4s32*//*Label 2282*/ GIMT_Encode4(73281),
26553 /* 73277 */ /*GILLT_v2s64*//*Label 2283*/ GIMT_Encode4(73413),
26554 /* 73281 */ // Label 2282: @73281
26555 /* 73281 */ GIM_Try, /*On fail goto*//*Label 2285*/ GIMT_Encode4(73412),
26556 /* 73286 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26557 /* 73289 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26558 /* 73292 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26559 /* 73295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26560 /* 73299 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26561 /* 73303 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26562 /* 73307 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2286*/ GIMT_Encode4(73359), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5064 //
26563 /* 73314 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26564 /* 73318 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3896:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26565 /* 73318 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26566 /* 73321 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26567 /* 73325 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26568 /* 73330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16bh),
26569 /* 73333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26570 /* 73335 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26571 /* 73337 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26572 /* 73339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26573 /* 73342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26574 /* 73348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26575 /* 73354 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26576 /* 73357 */ GIR_RootConstrainSelectedInstOperands,
26577 /* 73358 */ // GIR_Coverage, 5064,
26578 /* 73358 */ GIR_EraseRootFromParent_Done,
26579 /* 73359 */ // Label 2286: @73359
26580 /* 73359 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2287*/ GIMT_Encode4(73411), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5066 //
26581 /* 73366 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26582 /* 73370 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3896:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26583 /* 73370 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26584 /* 73373 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26585 /* 73377 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26586 /* 73382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16th),
26587 /* 73385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26588 /* 73387 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26589 /* 73389 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26590 /* 73391 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26591 /* 73394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26592 /* 73400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26593 /* 73406 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26594 /* 73409 */ GIR_RootConstrainSelectedInstOperands,
26595 /* 73410 */ // GIR_Coverage, 5066,
26596 /* 73410 */ GIR_EraseRootFromParent_Done,
26597 /* 73411 */ // Label 2287: @73411
26598 /* 73411 */ GIM_Reject,
26599 /* 73412 */ // Label 2285: @73412
26600 /* 73412 */ GIM_Reject,
26601 /* 73413 */ // Label 2283: @73413
26602 /* 73413 */ GIM_Try, /*On fail goto*//*Label 2288*/ GIMT_Encode4(73544),
26603 /* 73418 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26604 /* 73421 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26605 /* 73424 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26606 /* 73427 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26607 /* 73431 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26608 /* 73435 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26609 /* 73439 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2289*/ GIMT_Encode4(73491), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5068 //
26610 /* 73446 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26611 /* 73450 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3896:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs32bh:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26612 /* 73450 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26613 /* 73453 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26614 /* 73457 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26615 /* 73462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32bh),
26616 /* 73465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26617 /* 73467 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26618 /* 73469 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26619 /* 73471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26620 /* 73474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26621 /* 73480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26622 /* 73486 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26623 /* 73489 */ GIR_RootConstrainSelectedInstOperands,
26624 /* 73490 */ // GIR_Coverage, 5068,
26625 /* 73490 */ GIR_EraseRootFromParent_Done,
26626 /* 73491 */ // Label 2289: @73491
26627 /* 73491 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2290*/ GIMT_Encode4(73543), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5070 //
26628 /* 73498 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26629 /* 73502 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3896:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs32th:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26630 /* 73502 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26631 /* 73505 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26632 /* 73509 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26633 /* 73514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32th),
26634 /* 73517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26635 /* 73519 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26636 /* 73521 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26637 /* 73523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26638 /* 73526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26639 /* 73532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26640 /* 73538 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26641 /* 73541 */ GIR_RootConstrainSelectedInstOperands,
26642 /* 73542 */ // GIR_Coverage, 5070,
26643 /* 73542 */ GIR_EraseRootFromParent_Done,
26644 /* 73543 */ // Label 2290: @73543
26645 /* 73543 */ GIM_Reject,
26646 /* 73544 */ // Label 2288: @73544
26647 /* 73544 */ GIM_Reject,
26648 /* 73545 */ // Label 2284: @73545
26649 /* 73545 */ GIM_Reject,
26650 /* 73546 */ // Label 2281: @73546
26651 /* 73546 */ GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(73736),
26652 /* 73551 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
26653 /* 73556 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2294*/ GIMT_Encode4(73735),
26654 /* 73567 */ /*GILLT_v8s16*//*Label 2292*/ GIMT_Encode4(73579), GIMT_Encode4(0),
26655 /* 73575 */ /*GILLT_v4s32*//*Label 2293*/ GIMT_Encode4(73657),
26656 /* 73579 */ // Label 2292: @73579
26657 /* 73579 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2295*/ GIMT_Encode4(73656), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4450 //
26658 /* 73586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26659 /* 73589 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26660 /* 73592 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
26661 /* 73595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26662 /* 73599 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26663 /* 73603 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
26664 /* 73607 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
26665 /* 73611 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26666 /* 73616 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26667 /* 73620 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26668 /* 73624 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26669 /* 73626 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3761:{ *:[iPTR] }, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
26670 /* 73626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
26671 /* 73629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26672 /* 73631 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
26673 /* 73633 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
26674 /* 73637 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
26675 /* 73639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26676 /* 73642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26677 /* 73648 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26678 /* 73654 */ GIR_RootConstrainSelectedInstOperands,
26679 /* 73655 */ // GIR_Coverage, 4450,
26680 /* 73655 */ GIR_EraseRootFromParent_Done,
26681 /* 73656 */ // Label 2295: @73656
26682 /* 73656 */ GIM_Reject,
26683 /* 73657 */ // Label 2293: @73657
26684 /* 73657 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2296*/ GIMT_Encode4(73734), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4436 //
26685 /* 73664 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26686 /* 73667 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26687 /* 73670 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
26688 /* 73673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26689 /* 73677 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26690 /* 73681 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
26691 /* 73685 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
26692 /* 73689 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26693 /* 73694 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26694 /* 73698 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26695 /* 73702 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26696 /* 73704 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3761:{ *:[iPTR] }, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
26697 /* 73704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
26698 /* 73707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26699 /* 73709 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
26700 /* 73711 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
26701 /* 73715 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
26702 /* 73717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26703 /* 73720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26704 /* 73726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26705 /* 73732 */ GIR_RootConstrainSelectedInstOperands,
26706 /* 73733 */ // GIR_Coverage, 4436,
26707 /* 73733 */ GIR_EraseRootFromParent_Done,
26708 /* 73734 */ // Label 2296: @73734
26709 /* 73734 */ GIM_Reject,
26710 /* 73735 */ // Label 2294: @73735
26711 /* 73735 */ GIM_Reject,
26712 /* 73736 */ // Label 2291: @73736
26713 /* 73736 */ GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(73936),
26714 /* 73741 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq),
26715 /* 73746 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2300*/ GIMT_Encode4(73935),
26716 /* 73757 */ /*GILLT_v8s16*//*Label 2298*/ GIMT_Encode4(73769), GIMT_Encode4(0),
26717 /* 73765 */ /*GILLT_v4s32*//*Label 2299*/ GIMT_Encode4(73852),
26718 /* 73769 */ // Label 2298: @73769
26719 /* 73769 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2301*/ GIMT_Encode4(73851), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4894 //
26720 /* 73776 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26721 /* 73779 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26722 /* 73782 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
26723 /* 73785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26724 /* 73789 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26725 /* 73793 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26726 /* 73797 */ // MIs[1] Operand 1
26727 /* 73797 */ // No operand predicates
26728 /* 73797 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26729 /* 73801 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26730 /* 73805 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26731 /* 73807 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3830:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
26732 /* 73807 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26733 /* 73810 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26734 /* 73814 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26735 /* 73819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf16),
26736 /* 73822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26737 /* 73824 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26738 /* 73826 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm
26739 /* 73828 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
26740 /* 73831 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26741 /* 73834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26742 /* 73840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26743 /* 73846 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26744 /* 73849 */ GIR_RootConstrainSelectedInstOperands,
26745 /* 73850 */ // GIR_Coverage, 4894,
26746 /* 73850 */ GIR_EraseRootFromParent_Done,
26747 /* 73851 */ // Label 2301: @73851
26748 /* 73851 */ GIM_Reject,
26749 /* 73852 */ // Label 2299: @73852
26750 /* 73852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2302*/ GIMT_Encode4(73934), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4896 //
26751 /* 73859 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26752 /* 73862 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26753 /* 73865 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
26754 /* 73868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26755 /* 73872 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
26756 /* 73876 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26757 /* 73880 */ // MIs[1] Operand 1
26758 /* 73880 */ // No operand predicates
26759 /* 73880 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26760 /* 73884 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26761 /* 73888 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26762 /* 73890 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3830:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
26763 /* 73890 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26764 /* 73893 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26765 /* 73897 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26766 /* 73902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf32),
26767 /* 73905 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26768 /* 73907 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26769 /* 73909 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm
26770 /* 73911 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
26771 /* 73914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26772 /* 73917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26773 /* 73923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26774 /* 73929 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26775 /* 73932 */ GIR_RootConstrainSelectedInstOperands,
26776 /* 73933 */ // GIR_Coverage, 4896,
26777 /* 73933 */ GIR_EraseRootFromParent_Done,
26778 /* 73934 */ // Label 2302: @73934
26779 /* 73934 */ GIM_Reject,
26780 /* 73935 */ // Label 2300: @73935
26781 /* 73935 */ GIM_Reject,
26782 /* 73936 */ // Label 2297: @73936
26783 /* 73936 */ GIM_Try, /*On fail goto*//*Label 2303*/ GIMT_Encode4(74126),
26784 /* 73941 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
26785 /* 73946 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2306*/ GIMT_Encode4(74125),
26786 /* 73957 */ /*GILLT_v8s16*//*Label 2304*/ GIMT_Encode4(73969), GIMT_Encode4(0),
26787 /* 73965 */ /*GILLT_v4s32*//*Label 2305*/ GIMT_Encode4(74047),
26788 /* 73969 */ // Label 2304: @73969
26789 /* 73969 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2307*/ GIMT_Encode4(74046), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4451 //
26790 /* 73976 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26791 /* 73979 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26792 /* 73982 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
26793 /* 73985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26794 /* 73989 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26795 /* 73993 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
26796 /* 73997 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
26797 /* 74001 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
26798 /* 74005 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26799 /* 74010 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26800 /* 74014 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26801 /* 74016 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3761:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$m1, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m2), MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
26802 /* 74016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
26803 /* 74019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26804 /* 74021 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
26805 /* 74023 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
26806 /* 74025 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m2
26807 /* 74029 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26808 /* 74032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26809 /* 74038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26810 /* 74044 */ GIR_RootConstrainSelectedInstOperands,
26811 /* 74045 */ // GIR_Coverage, 4451,
26812 /* 74045 */ GIR_EraseRootFromParent_Done,
26813 /* 74046 */ // Label 2307: @74046
26814 /* 74046 */ GIM_Reject,
26815 /* 74047 */ // Label 2305: @74047
26816 /* 74047 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2308*/ GIMT_Encode4(74124), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4437 //
26817 /* 74054 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26818 /* 74057 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26819 /* 74060 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
26820 /* 74063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26821 /* 74067 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26822 /* 74071 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
26823 /* 74075 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
26824 /* 74079 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
26825 /* 74083 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26826 /* 74088 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26827 /* 74092 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26828 /* 74094 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3761:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$m1, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m2), MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
26829 /* 74094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
26830 /* 74097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26831 /* 74099 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
26832 /* 74101 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
26833 /* 74103 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m2
26834 /* 74107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26835 /* 74110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26836 /* 74116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26837 /* 74122 */ GIR_RootConstrainSelectedInstOperands,
26838 /* 74123 */ // GIR_Coverage, 4437,
26839 /* 74123 */ GIR_EraseRootFromParent_Done,
26840 /* 74124 */ // Label 2308: @74124
26841 /* 74124 */ GIM_Reject,
26842 /* 74125 */ // Label 2306: @74125
26843 /* 74125 */ GIM_Reject,
26844 /* 74126 */ // Label 2303: @74126
26845 /* 74126 */ GIM_Try, /*On fail goto*//*Label 2309*/ GIMT_Encode4(74239),
26846 /* 74131 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8),
26847 /* 74136 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26848 /* 74139 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26849 /* 74142 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26850 /* 74145 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26851 /* 74148 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2310*/ GIMT_Encode4(74193), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 145 //
26852 /* 74155 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
26853 /* 74159 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
26854 /* 74163 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
26855 /* 74167 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
26856 /* 74171 */ // (intrinsic_wo_chain:{ *:[i32] } 4168:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (USADA8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
26857 /* 74171 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USADA8),
26858 /* 74174 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
26859 /* 74176 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
26860 /* 74178 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
26861 /* 74180 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
26862 /* 74182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
26863 /* 74185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26864 /* 74191 */ GIR_RootConstrainSelectedInstOperands,
26865 /* 74192 */ // GIR_Coverage, 145,
26866 /* 74192 */ GIR_EraseRootFromParent_Done,
26867 /* 74193 */ // Label 2310: @74193
26868 /* 74193 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2311*/ GIMT_Encode4(74238), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 468 //
26869 /* 74200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26870 /* 74204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26871 /* 74208 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26872 /* 74212 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26873 /* 74216 */ // (intrinsic_wo_chain:{ *:[i32] } 4168:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2USADA8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
26874 /* 74216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USADA8),
26875 /* 74219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
26876 /* 74221 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
26877 /* 74223 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
26878 /* 74225 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
26879 /* 74227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
26880 /* 74230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26881 /* 74236 */ GIR_RootConstrainSelectedInstOperands,
26882 /* 74237 */ // GIR_Coverage, 468,
26883 /* 74237 */ GIR_EraseRootFromParent_Done,
26884 /* 74238 */ // Label 2311: @74238
26885 /* 74238 */ GIM_Reject,
26886 /* 74239 */ // Label 2309: @74239
26887 /* 74239 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2312*/ GIMT_Encode4(74301), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 527 //
26888 /* 74246 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad),
26889 /* 74251 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26890 /* 74254 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26891 /* 74257 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26892 /* 74260 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26893 /* 74263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26894 /* 74267 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26895 /* 74271 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26896 /* 74275 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26897 /* 74279 */ // (intrinsic_wo_chain:{ *:[i32] } 4113:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
26898 /* 74279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAD),
26899 /* 74282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
26900 /* 74284 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
26901 /* 74286 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
26902 /* 74288 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
26903 /* 74290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
26904 /* 74293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26905 /* 74299 */ GIR_RootConstrainSelectedInstOperands,
26906 /* 74300 */ // GIR_Coverage, 527,
26907 /* 74300 */ GIR_EraseRootFromParent_Done,
26908 /* 74301 */ // Label 2312: @74301
26909 /* 74301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2313*/ GIMT_Encode4(74363), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 528 //
26910 /* 74308 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx),
26911 /* 74313 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26912 /* 74316 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26913 /* 74319 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26914 /* 74322 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26915 /* 74325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26916 /* 74329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26917 /* 74333 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26918 /* 74337 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26919 /* 74341 */ // (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
26920 /* 74341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLADX),
26921 /* 74344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
26922 /* 74346 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
26923 /* 74348 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
26924 /* 74350 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
26925 /* 74352 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
26926 /* 74355 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26927 /* 74361 */ GIR_RootConstrainSelectedInstOperands,
26928 /* 74362 */ // GIR_Coverage, 528,
26929 /* 74362 */ GIR_EraseRootFromParent_Done,
26930 /* 74363 */ // Label 2313: @74363
26931 /* 74363 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2314*/ GIMT_Encode4(74425), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 529 //
26932 /* 74370 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd),
26933 /* 74375 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26934 /* 74378 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26935 /* 74381 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26936 /* 74384 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26937 /* 74387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26938 /* 74391 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26939 /* 74395 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26940 /* 74399 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26941 /* 74403 */ // (intrinsic_wo_chain:{ *:[i32] } 4121:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
26942 /* 74403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSD),
26943 /* 74406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
26944 /* 74408 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
26945 /* 74410 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
26946 /* 74412 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
26947 /* 74414 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
26948 /* 74417 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26949 /* 74423 */ GIR_RootConstrainSelectedInstOperands,
26950 /* 74424 */ // GIR_Coverage, 529,
26951 /* 74424 */ GIR_EraseRootFromParent_Done,
26952 /* 74425 */ // Label 2314: @74425
26953 /* 74425 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2315*/ GIMT_Encode4(74487), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 530 //
26954 /* 74432 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx),
26955 /* 74437 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26956 /* 74440 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26957 /* 74443 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
26958 /* 74446 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26959 /* 74449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26960 /* 74453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26961 /* 74457 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26962 /* 74461 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26963 /* 74465 */ // (intrinsic_wo_chain:{ *:[i32] } 4122:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
26964 /* 74465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSDX),
26965 /* 74468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
26966 /* 74470 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
26967 /* 74472 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
26968 /* 74474 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
26969 /* 74476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
26970 /* 74479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26971 /* 74485 */ GIR_RootConstrainSelectedInstOperands,
26972 /* 74486 */ // GIR_Coverage, 530,
26973 /* 74486 */ GIR_EraseRootFromParent_Done,
26974 /* 74487 */ // Label 2315: @74487
26975 /* 74487 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2316*/ GIMT_Encode4(74540), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1113 //
26976 /* 74494 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot),
26977 /* 74499 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
26978 /* 74502 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
26979 /* 74505 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
26980 /* 74508 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
26981 /* 74511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
26982 /* 74515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
26983 /* 74519 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
26984 /* 74523 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
26985 /* 74527 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3974:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
26986 /* 74527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTD),
26987 /* 74530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
26988 /* 74532 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
26989 /* 74534 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
26990 /* 74536 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
26991 /* 74538 */ GIR_RootConstrainSelectedInstOperands,
26992 /* 74539 */ // GIR_Coverage, 1113,
26993 /* 74539 */ GIR_EraseRootFromParent_Done,
26994 /* 74540 */ // Label 2316: @74540
26995 /* 74540 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2317*/ GIMT_Encode4(74593), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1114 //
26996 /* 74547 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot),
26997 /* 74552 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
26998 /* 74555 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
26999 /* 74558 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
27000 /* 74561 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
27001 /* 74564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27002 /* 74568 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27003 /* 74572 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27004 /* 74576 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27005 /* 74580 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3962:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27006 /* 74580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTD),
27007 /* 74583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27008 /* 74585 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27009 /* 74587 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27010 /* 74589 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27011 /* 74591 */ GIR_RootConstrainSelectedInstOperands,
27012 /* 74592 */ // GIR_Coverage, 1114,
27013 /* 74592 */ GIR_EraseRootFromParent_Done,
27014 /* 74593 */ // Label 2317: @74593
27015 /* 74593 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2318*/ GIMT_Encode4(74646), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1115 //
27016 /* 74600 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot),
27017 /* 74605 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27018 /* 74608 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27019 /* 74611 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27020 /* 74614 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27021 /* 74617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27022 /* 74621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27023 /* 74625 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27024 /* 74629 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27025 /* 74633 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3974:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27026 /* 74633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTQ),
27027 /* 74636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27028 /* 74638 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27029 /* 74640 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27030 /* 74642 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27031 /* 74644 */ GIR_RootConstrainSelectedInstOperands,
27032 /* 74645 */ // GIR_Coverage, 1115,
27033 /* 74645 */ GIR_EraseRootFromParent_Done,
27034 /* 74646 */ // Label 2318: @74646
27035 /* 74646 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2319*/ GIMT_Encode4(74699), GIMT_Encode2(GIFBS_HasDotProd), // Rule ID 1116 //
27036 /* 74653 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot),
27037 /* 74658 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27038 /* 74661 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27039 /* 74664 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27040 /* 74667 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27041 /* 74670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27042 /* 74674 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27043 /* 74678 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27044 /* 74682 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27045 /* 74686 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3962:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27046 /* 74686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTQ),
27047 /* 74689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27048 /* 74691 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27049 /* 74693 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27050 /* 74695 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27051 /* 74697 */ GIR_RootConstrainSelectedInstOperands,
27052 /* 74698 */ // GIR_Coverage, 1116,
27053 /* 74698 */ GIR_EraseRootFromParent_Done,
27054 /* 74699 */ // Label 2319: @74699
27055 /* 74699 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2320*/ GIMT_Encode4(74752), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1117 //
27056 /* 74706 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_smmla),
27057 /* 74711 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27058 /* 74714 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27059 /* 74717 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27060 /* 74720 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27061 /* 74723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27062 /* 74727 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27063 /* 74731 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27064 /* 74735 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27065 /* 74739 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3973:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27066 /* 74739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSMMLA),
27067 /* 74742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27068 /* 74744 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27069 /* 74746 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27070 /* 74748 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27071 /* 74750 */ GIR_RootConstrainSelectedInstOperands,
27072 /* 74751 */ // GIR_Coverage, 1117,
27073 /* 74751 */ GIR_EraseRootFromParent_Done,
27074 /* 74752 */ // Label 2320: @74752
27075 /* 74752 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2321*/ GIMT_Encode4(74805), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1118 //
27076 /* 74759 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_ummla),
27077 /* 74764 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27078 /* 74767 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27079 /* 74770 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27080 /* 74773 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27081 /* 74776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27082 /* 74780 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27083 /* 74784 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27084 /* 74788 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27085 /* 74792 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3975:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27086 /* 74792 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUMMLA),
27087 /* 74795 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27088 /* 74797 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27089 /* 74799 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27090 /* 74801 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27091 /* 74803 */ GIR_RootConstrainSelectedInstOperands,
27092 /* 74804 */ // GIR_Coverage, 1118,
27093 /* 74804 */ GIR_EraseRootFromParent_Done,
27094 /* 74805 */ // Label 2321: @74805
27095 /* 74805 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2322*/ GIMT_Encode4(74858), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1119 //
27096 /* 74812 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usmmla),
27097 /* 74817 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27098 /* 74820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27099 /* 74823 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27100 /* 74826 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27101 /* 74829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27102 /* 74833 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27103 /* 74837 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27104 /* 74841 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27105 /* 74845 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3977:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27106 /* 74845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSMMLA),
27107 /* 74848 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27108 /* 74850 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27109 /* 74852 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27110 /* 74854 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27111 /* 74856 */ GIR_RootConstrainSelectedInstOperands,
27112 /* 74857 */ // GIR_Coverage, 1119,
27113 /* 74857 */ GIR_EraseRootFromParent_Done,
27114 /* 74858 */ // Label 2322: @74858
27115 /* 74858 */ GIM_Try, /*On fail goto*//*Label 2323*/ GIMT_Encode4(74980),
27116 /* 74863 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot),
27117 /* 74868 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(13), /*)*//*default:*//*Label 2326*/ GIMT_Encode4(74979),
27118 /* 74879 */ /*GILLT_v2s32*//*Label 2324*/ GIMT_Encode4(74887),
27119 /* 74883 */ /*GILLT_v4s32*//*Label 2325*/ GIMT_Encode4(74933),
27120 /* 74887 */ // Label 2324: @74887
27121 /* 74887 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2327*/ GIMT_Encode4(74932), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1120 //
27122 /* 74894 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
27123 /* 74897 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
27124 /* 74900 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
27125 /* 74903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27126 /* 74907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27127 /* 74911 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27128 /* 74915 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27129 /* 74919 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3976:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27130 /* 74919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTD),
27131 /* 74922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27132 /* 74924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27133 /* 74926 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27134 /* 74928 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27135 /* 74930 */ GIR_RootConstrainSelectedInstOperands,
27136 /* 74931 */ // GIR_Coverage, 1120,
27137 /* 74931 */ GIR_EraseRootFromParent_Done,
27138 /* 74932 */ // Label 2327: @74932
27139 /* 74932 */ GIM_Reject,
27140 /* 74933 */ // Label 2325: @74933
27141 /* 74933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2328*/ GIMT_Encode4(74978), GIMT_Encode2(GIFBS_HasMatMulInt8), // Rule ID 1121 //
27142 /* 74940 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27143 /* 74943 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27144 /* 74946 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
27145 /* 74949 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27146 /* 74953 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27147 /* 74957 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27148 /* 74961 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27149 /* 74965 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3976:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
27150 /* 74965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTQ),
27151 /* 74968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
27152 /* 74970 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
27153 /* 74972 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27154 /* 74974 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27155 /* 74976 */ GIR_RootConstrainSelectedInstOperands,
27156 /* 74977 */ // GIR_Coverage, 1121,
27157 /* 74977 */ GIR_EraseRootFromParent_Done,
27158 /* 74978 */ // Label 2328: @74978
27159 /* 74978 */ GIM_Reject,
27160 /* 74979 */ // Label 2326: @74979
27161 /* 74979 */ GIM_Reject,
27162 /* 74980 */ // Label 2323: @74980
27163 /* 74980 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2329*/ GIMT_Encode4(75042), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1852 //
27164 /* 74987 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx1),
27165 /* 74992 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
27166 /* 74995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
27167 /* 74998 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
27168 /* 75001 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
27169 /* 75004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27170 /* 75008 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27171 /* 75012 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27172 /* 75016 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27173 /* 75020 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4088:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VTBX1:{ *:[v8i8] } DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
27174 /* 75020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX1),
27175 /* 75023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27176 /* 75025 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
27177 /* 75027 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27178 /* 75029 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27179 /* 75031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27180 /* 75034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27181 /* 75040 */ GIR_RootConstrainSelectedInstOperands,
27182 /* 75041 */ // GIR_Coverage, 1852,
27183 /* 75041 */ GIR_EraseRootFromParent_Done,
27184 /* 75042 */ // Label 2329: @75042
27185 /* 75042 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2330*/ GIMT_Encode4(75095), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1907 //
27186 /* 75049 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su0),
27187 /* 75054 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27188 /* 75057 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27189 /* 75060 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27190 /* 75063 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27191 /* 75066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27192 /* 75070 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27193 /* 75074 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27194 /* 75078 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27195 /* 75082 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3967:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27196 /* 75082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU0),
27197 /* 75085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27198 /* 75087 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
27199 /* 75089 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27200 /* 75091 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27201 /* 75093 */ GIR_RootConstrainSelectedInstOperands,
27202 /* 75094 */ // GIR_Coverage, 1907,
27203 /* 75094 */ GIR_EraseRootFromParent_Done,
27204 /* 75095 */ // Label 2330: @75095
27205 /* 75095 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2331*/ GIMT_Encode4(75148), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1908 //
27206 /* 75102 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h),
27207 /* 75107 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27208 /* 75110 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27209 /* 75113 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27210 /* 75116 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27211 /* 75119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27212 /* 75123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27213 /* 75127 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27214 /* 75131 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27215 /* 75135 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3969:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27216 /* 75135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H),
27217 /* 75138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27218 /* 75140 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
27219 /* 75142 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27220 /* 75144 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27221 /* 75146 */ GIR_RootConstrainSelectedInstOperands,
27222 /* 75147 */ // GIR_Coverage, 1908,
27223 /* 75147 */ GIR_EraseRootFromParent_Done,
27224 /* 75148 */ // Label 2331: @75148
27225 /* 75148 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2332*/ GIMT_Encode4(75201), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1909 //
27226 /* 75155 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h2),
27227 /* 75160 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27228 /* 75163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27229 /* 75166 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27230 /* 75169 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27231 /* 75172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27232 /* 75176 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27233 /* 75180 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27234 /* 75184 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27235 /* 75188 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3970:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H2:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27236 /* 75188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H2),
27237 /* 75191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27238 /* 75193 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
27239 /* 75195 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27240 /* 75197 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27241 /* 75199 */ GIR_RootConstrainSelectedInstOperands,
27242 /* 75200 */ // GIR_Coverage, 1909,
27243 /* 75200 */ GIR_EraseRootFromParent_Done,
27244 /* 75201 */ // Label 2332: @75201
27245 /* 75201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2333*/ GIMT_Encode4(75254), GIMT_Encode2(GIFBS_HasSHA2_HasV8), // Rule ID 1910 //
27246 /* 75208 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su1),
27247 /* 75213 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27248 /* 75216 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27249 /* 75219 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27250 /* 75222 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27251 /* 75225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27252 /* 75229 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27253 /* 75233 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27254 /* 75237 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27255 /* 75241 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3972:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27256 /* 75241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU1),
27257 /* 75244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27258 /* 75246 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
27259 /* 75248 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27260 /* 75250 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27261 /* 75252 */ GIR_RootConstrainSelectedInstOperands,
27262 /* 75253 */ // GIR_Coverage, 1910,
27263 /* 75253 */ GIR_EraseRootFromParent_Done,
27264 /* 75254 */ // Label 2333: @75254
27265 /* 75254 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2334*/ GIMT_Encode4(75316), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2087 //
27266 /* 75261 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad),
27267 /* 75266 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27268 /* 75269 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27269 /* 75272 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27270 /* 75275 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27271 /* 75278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27272 /* 75282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27273 /* 75286 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27274 /* 75290 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27275 /* 75294 */ // (intrinsic_wo_chain:{ *:[i32] } 4113:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27276 /* 75294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAD),
27277 /* 75297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27278 /* 75299 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
27279 /* 75301 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
27280 /* 75303 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
27281 /* 75305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27282 /* 75308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27283 /* 75314 */ GIR_RootConstrainSelectedInstOperands,
27284 /* 75315 */ // GIR_Coverage, 2087,
27285 /* 75315 */ GIR_EraseRootFromParent_Done,
27286 /* 75316 */ // Label 2334: @75316
27287 /* 75316 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2335*/ GIMT_Encode4(75378), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2088 //
27288 /* 75323 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx),
27289 /* 75328 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27290 /* 75331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27291 /* 75334 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27292 /* 75337 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27293 /* 75340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27294 /* 75344 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27295 /* 75348 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27296 /* 75352 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27297 /* 75356 */ // (intrinsic_wo_chain:{ *:[i32] } 4114:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27298 /* 75356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLADX),
27299 /* 75359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27300 /* 75361 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
27301 /* 75363 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
27302 /* 75365 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
27303 /* 75367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27304 /* 75370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27305 /* 75376 */ GIR_RootConstrainSelectedInstOperands,
27306 /* 75377 */ // GIR_Coverage, 2088,
27307 /* 75377 */ GIR_EraseRootFromParent_Done,
27308 /* 75378 */ // Label 2335: @75378
27309 /* 75378 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2336*/ GIMT_Encode4(75440), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2089 //
27310 /* 75385 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd),
27311 /* 75390 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27312 /* 75393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27313 /* 75396 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27314 /* 75399 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27315 /* 75402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27316 /* 75406 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27317 /* 75410 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27318 /* 75414 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27319 /* 75418 */ // (intrinsic_wo_chain:{ *:[i32] } 4121:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27320 /* 75418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSD),
27321 /* 75421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27322 /* 75423 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
27323 /* 75425 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
27324 /* 75427 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
27325 /* 75429 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27326 /* 75432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27327 /* 75438 */ GIR_RootConstrainSelectedInstOperands,
27328 /* 75439 */ // GIR_Coverage, 2089,
27329 /* 75439 */ GIR_EraseRootFromParent_Done,
27330 /* 75440 */ // Label 2336: @75440
27331 /* 75440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2337*/ GIMT_Encode4(75502), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2090 //
27332 /* 75447 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx),
27333 /* 75452 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27334 /* 75455 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27335 /* 75458 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27336 /* 75461 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27337 /* 75464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27338 /* 75468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27339 /* 75472 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27340 /* 75476 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27341 /* 75480 */ // (intrinsic_wo_chain:{ *:[i32] } 4122:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
27342 /* 75480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSDX),
27343 /* 75483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27344 /* 75485 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
27345 /* 75487 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
27346 /* 75489 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
27347 /* 75491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27348 /* 75494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27349 /* 75500 */ GIR_RootConstrainSelectedInstOperands,
27350 /* 75501 */ // GIR_Coverage, 2090,
27351 /* 75501 */ GIR_EraseRootFromParent_Done,
27352 /* 75502 */ // Label 2337: @75502
27353 /* 75502 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2338*/ GIMT_Encode4(75564), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2185 //
27354 /* 75509 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb),
27355 /* 75514 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27356 /* 75517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27357 /* 75520 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27358 /* 75523 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27359 /* 75526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27360 /* 75530 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27361 /* 75534 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27362 /* 75538 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27363 /* 75542 */ // (intrinsic_wo_chain:{ *:[i32] } 4111:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27364 /* 75542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB),
27365 /* 75545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27366 /* 75547 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27367 /* 75549 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27368 /* 75551 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27369 /* 75553 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27370 /* 75556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27371 /* 75562 */ GIR_RootConstrainSelectedInstOperands,
27372 /* 75563 */ // GIR_Coverage, 2185,
27373 /* 75563 */ GIR_EraseRootFromParent_Done,
27374 /* 75564 */ // Label 2338: @75564
27375 /* 75564 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2339*/ GIMT_Encode4(75626), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2186 //
27376 /* 75571 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt),
27377 /* 75576 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27378 /* 75579 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27379 /* 75582 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27380 /* 75585 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27381 /* 75588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27382 /* 75592 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27383 /* 75596 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27384 /* 75600 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27385 /* 75604 */ // (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27386 /* 75604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
27387 /* 75607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27388 /* 75609 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27389 /* 75611 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27390 /* 75613 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27391 /* 75615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27392 /* 75618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27393 /* 75624 */ GIR_RootConstrainSelectedInstOperands,
27394 /* 75625 */ // GIR_Coverage, 2186,
27395 /* 75625 */ GIR_EraseRootFromParent_Done,
27396 /* 75626 */ // Label 2339: @75626
27397 /* 75626 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2340*/ GIMT_Encode4(75688), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2187 //
27398 /* 75633 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb),
27399 /* 75638 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27400 /* 75641 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27401 /* 75644 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27402 /* 75647 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27403 /* 75650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27404 /* 75654 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27405 /* 75658 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27406 /* 75662 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27407 /* 75666 */ // (intrinsic_wo_chain:{ *:[i32] } 4117:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27408 /* 75666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB),
27409 /* 75669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27410 /* 75671 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27411 /* 75673 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27412 /* 75675 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27413 /* 75677 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27414 /* 75680 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27415 /* 75686 */ GIR_RootConstrainSelectedInstOperands,
27416 /* 75687 */ // GIR_Coverage, 2187,
27417 /* 75687 */ GIR_EraseRootFromParent_Done,
27418 /* 75688 */ // Label 2340: @75688
27419 /* 75688 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2341*/ GIMT_Encode4(75750), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2188 //
27420 /* 75695 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt),
27421 /* 75700 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27422 /* 75703 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27423 /* 75706 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27424 /* 75709 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27425 /* 75712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27426 /* 75716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27427 /* 75720 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27428 /* 75724 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27429 /* 75728 */ // (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27430 /* 75728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT),
27431 /* 75731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27432 /* 75733 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27433 /* 75735 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27434 /* 75737 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27435 /* 75739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27436 /* 75742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27437 /* 75748 */ GIR_RootConstrainSelectedInstOperands,
27438 /* 75749 */ // GIR_Coverage, 2188,
27439 /* 75749 */ GIR_EraseRootFromParent_Done,
27440 /* 75750 */ // Label 2341: @75750
27441 /* 75750 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2342*/ GIMT_Encode4(75812), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2189 //
27442 /* 75757 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb),
27443 /* 75762 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27444 /* 75765 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27445 /* 75768 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27446 /* 75771 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27447 /* 75774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27448 /* 75778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27449 /* 75782 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27450 /* 75786 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27451 /* 75790 */ // (intrinsic_wo_chain:{ *:[i32] } 4119:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27452 /* 75790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWB),
27453 /* 75793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27454 /* 75795 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27455 /* 75797 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27456 /* 75799 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27457 /* 75801 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27458 /* 75804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27459 /* 75810 */ GIR_RootConstrainSelectedInstOperands,
27460 /* 75811 */ // GIR_Coverage, 2189,
27461 /* 75811 */ GIR_EraseRootFromParent_Done,
27462 /* 75812 */ // Label 2342: @75812
27463 /* 75812 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2343*/ GIMT_Encode4(75874), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2190 //
27464 /* 75819 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt),
27465 /* 75824 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27466 /* 75827 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27467 /* 75830 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27468 /* 75833 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27469 /* 75836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
27470 /* 75840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27471 /* 75844 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27472 /* 75848 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27473 /* 75852 */ // (intrinsic_wo_chain:{ *:[i32] } 4120:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27474 /* 75852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWT),
27475 /* 75855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27476 /* 75857 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27477 /* 75859 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27478 /* 75861 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27479 /* 75863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27480 /* 75866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27481 /* 75872 */ GIR_RootConstrainSelectedInstOperands,
27482 /* 75873 */ // GIR_Coverage, 2190,
27483 /* 75873 */ GIR_EraseRootFromParent_Done,
27484 /* 75874 */ // Label 2343: @75874
27485 /* 75874 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2344*/ GIMT_Encode4(75936), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2377 //
27486 /* 75881 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb),
27487 /* 75886 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27488 /* 75889 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27489 /* 75892 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27490 /* 75895 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27491 /* 75898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27492 /* 75902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27493 /* 75906 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27494 /* 75910 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27495 /* 75914 */ // (intrinsic_wo_chain:{ *:[i32] } 4111:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27496 /* 75914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB),
27497 /* 75917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27498 /* 75919 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27499 /* 75921 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27500 /* 75923 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27501 /* 75925 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27502 /* 75928 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27503 /* 75934 */ GIR_RootConstrainSelectedInstOperands,
27504 /* 75935 */ // GIR_Coverage, 2377,
27505 /* 75935 */ GIR_EraseRootFromParent_Done,
27506 /* 75936 */ // Label 2344: @75936
27507 /* 75936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2345*/ GIMT_Encode4(75998), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2378 //
27508 /* 75943 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt),
27509 /* 75948 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27510 /* 75951 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27511 /* 75954 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27512 /* 75957 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27513 /* 75960 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27514 /* 75964 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27515 /* 75968 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27516 /* 75972 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27517 /* 75976 */ // (intrinsic_wo_chain:{ *:[i32] } 4112:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27518 /* 75976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
27519 /* 75979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27520 /* 75981 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27521 /* 75983 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27522 /* 75985 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27523 /* 75987 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27524 /* 75990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27525 /* 75996 */ GIR_RootConstrainSelectedInstOperands,
27526 /* 75997 */ // GIR_Coverage, 2378,
27527 /* 75997 */ GIR_EraseRootFromParent_Done,
27528 /* 75998 */ // Label 2345: @75998
27529 /* 75998 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2346*/ GIMT_Encode4(76060), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2379 //
27530 /* 76005 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb),
27531 /* 76010 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27532 /* 76013 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27533 /* 76016 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27534 /* 76019 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27535 /* 76022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27536 /* 76026 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27537 /* 76030 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27538 /* 76034 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27539 /* 76038 */ // (intrinsic_wo_chain:{ *:[i32] } 4117:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27540 /* 76038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB),
27541 /* 76041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27542 /* 76043 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27543 /* 76045 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27544 /* 76047 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27545 /* 76049 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27546 /* 76052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27547 /* 76058 */ GIR_RootConstrainSelectedInstOperands,
27548 /* 76059 */ // GIR_Coverage, 2379,
27549 /* 76059 */ GIR_EraseRootFromParent_Done,
27550 /* 76060 */ // Label 2346: @76060
27551 /* 76060 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2347*/ GIMT_Encode4(76122), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2380 //
27552 /* 76067 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt),
27553 /* 76072 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27554 /* 76075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27555 /* 76078 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27556 /* 76081 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27557 /* 76084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27558 /* 76088 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27559 /* 76092 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27560 /* 76096 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27561 /* 76100 */ // (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27562 /* 76100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT),
27563 /* 76103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27564 /* 76105 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27565 /* 76107 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27566 /* 76109 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27567 /* 76111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27568 /* 76114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27569 /* 76120 */ GIR_RootConstrainSelectedInstOperands,
27570 /* 76121 */ // GIR_Coverage, 2380,
27571 /* 76121 */ GIR_EraseRootFromParent_Done,
27572 /* 76122 */ // Label 2347: @76122
27573 /* 76122 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2348*/ GIMT_Encode4(76184), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2381 //
27574 /* 76129 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb),
27575 /* 76134 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27576 /* 76137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27577 /* 76140 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27578 /* 76143 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27579 /* 76146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27580 /* 76150 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27581 /* 76154 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27582 /* 76158 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27583 /* 76162 */ // (intrinsic_wo_chain:{ *:[i32] } 4119:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27584 /* 76162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWB),
27585 /* 76165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27586 /* 76167 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27587 /* 76169 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27588 /* 76171 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27589 /* 76173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27590 /* 76176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27591 /* 76182 */ GIR_RootConstrainSelectedInstOperands,
27592 /* 76183 */ // GIR_Coverage, 2381,
27593 /* 76183 */ GIR_EraseRootFromParent_Done,
27594 /* 76184 */ // Label 2348: @76184
27595 /* 76184 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2349*/ GIMT_Encode4(76246), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2382 //
27596 /* 76191 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt),
27597 /* 76196 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
27598 /* 76199 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27599 /* 76202 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
27600 /* 76205 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27601 /* 76208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27602 /* 76212 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27603 /* 76216 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27604 /* 76220 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
27605 /* 76224 */ // (intrinsic_wo_chain:{ *:[i32] } 4120:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
27606 /* 76224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWT),
27607 /* 76227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
27608 /* 76229 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
27609 /* 76231 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
27610 /* 76233 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
27611 /* 76235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27612 /* 76238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27613 /* 76244 */ GIR_RootConstrainSelectedInstOperands,
27614 /* 76245 */ // GIR_Coverage, 2382,
27615 /* 76245 */ GIR_EraseRootFromParent_Done,
27616 /* 76246 */ // Label 2349: @76246
27617 /* 76246 */ GIM_Try, /*On fail goto*//*Label 2350*/ GIMT_Encode4(76504),
27618 /* 76251 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah),
27619 /* 76256 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 2355*/ GIMT_Encode4(76503),
27620 /* 76267 */ /*GILLT_v4s16*//*Label 2351*/ GIMT_Encode4(76283),
27621 /* 76271 */ /*GILLT_v8s16*//*Label 2352*/ GIMT_Encode4(76338),
27622 /* 76275 */ /*GILLT_v2s32*//*Label 2353*/ GIMT_Encode4(76393),
27623 /* 76279 */ /*GILLT_v4s32*//*Label 2354*/ GIMT_Encode4(76448),
27624 /* 76283 */ // Label 2351: @76283
27625 /* 76283 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2356*/ GIMT_Encode4(76337), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2856 //
27626 /* 76290 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
27627 /* 76293 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
27628 /* 76296 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
27629 /* 76299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27630 /* 76303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27631 /* 76307 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27632 /* 76311 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27633 /* 76315 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4046:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLAHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
27634 /* 76315 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i16),
27635 /* 76318 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27636 /* 76320 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27637 /* 76322 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27638 /* 76324 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27639 /* 76326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27640 /* 76329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27641 /* 76335 */ GIR_RootConstrainSelectedInstOperands,
27642 /* 76336 */ // GIR_Coverage, 2856,
27643 /* 76336 */ GIR_EraseRootFromParent_Done,
27644 /* 76337 */ // Label 2356: @76337
27645 /* 76337 */ GIM_Reject,
27646 /* 76338 */ // Label 2352: @76338
27647 /* 76338 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2357*/ GIMT_Encode4(76392), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2858 //
27648 /* 76345 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27649 /* 76348 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27650 /* 76351 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
27651 /* 76354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27652 /* 76358 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27653 /* 76362 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27654 /* 76366 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27655 /* 76370 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4046:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLAHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
27656 /* 76370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv8i16),
27657 /* 76373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27658 /* 76375 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27659 /* 76377 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27660 /* 76379 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27661 /* 76381 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27662 /* 76384 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27663 /* 76390 */ GIR_RootConstrainSelectedInstOperands,
27664 /* 76391 */ // GIR_Coverage, 2858,
27665 /* 76391 */ GIR_EraseRootFromParent_Done,
27666 /* 76392 */ // Label 2357: @76392
27667 /* 76392 */ GIM_Reject,
27668 /* 76393 */ // Label 2353: @76393
27669 /* 76393 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2358*/ GIMT_Encode4(76447), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2857 //
27670 /* 76400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
27671 /* 76403 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
27672 /* 76406 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
27673 /* 76409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27674 /* 76413 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27675 /* 76417 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27676 /* 76421 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27677 /* 76425 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4046:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLAHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
27678 /* 76425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv2i32),
27679 /* 76428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27680 /* 76430 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27681 /* 76432 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27682 /* 76434 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27683 /* 76436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27684 /* 76439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27685 /* 76445 */ GIR_RootConstrainSelectedInstOperands,
27686 /* 76446 */ // GIR_Coverage, 2857,
27687 /* 76446 */ GIR_EraseRootFromParent_Done,
27688 /* 76447 */ // Label 2358: @76447
27689 /* 76447 */ GIM_Reject,
27690 /* 76448 */ // Label 2354: @76448
27691 /* 76448 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2359*/ GIMT_Encode4(76502), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2859 //
27692 /* 76455 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27693 /* 76458 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27694 /* 76461 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27695 /* 76464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27696 /* 76468 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27697 /* 76472 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27698 /* 76476 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27699 /* 76480 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4046:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLAHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27700 /* 76480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i32),
27701 /* 76483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27702 /* 76485 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27703 /* 76487 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27704 /* 76489 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27705 /* 76491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27706 /* 76494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27707 /* 76500 */ GIR_RootConstrainSelectedInstOperands,
27708 /* 76501 */ // GIR_Coverage, 2859,
27709 /* 76501 */ GIR_EraseRootFromParent_Done,
27710 /* 76502 */ // Label 2359: @76502
27711 /* 76502 */ GIM_Reject,
27712 /* 76503 */ // Label 2355: @76503
27713 /* 76503 */ GIM_Reject,
27714 /* 76504 */ // Label 2350: @76504
27715 /* 76504 */ GIM_Try, /*On fail goto*//*Label 2360*/ GIMT_Encode4(76762),
27716 /* 76509 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh),
27717 /* 76514 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(13), /*)*//*default:*//*Label 2365*/ GIMT_Encode4(76761),
27718 /* 76525 */ /*GILLT_v4s16*//*Label 2361*/ GIMT_Encode4(76541),
27719 /* 76529 */ /*GILLT_v8s16*//*Label 2362*/ GIMT_Encode4(76596),
27720 /* 76533 */ /*GILLT_v2s32*//*Label 2363*/ GIMT_Encode4(76651),
27721 /* 76537 */ /*GILLT_v4s32*//*Label 2364*/ GIMT_Encode4(76706),
27722 /* 76541 */ // Label 2361: @76541
27723 /* 76541 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2366*/ GIMT_Encode4(76595), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2864 //
27724 /* 76548 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
27725 /* 76551 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
27726 /* 76554 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
27727 /* 76557 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27728 /* 76561 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27729 /* 76565 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27730 /* 76569 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27731 /* 76573 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4047:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLSHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
27732 /* 76573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i16),
27733 /* 76576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27734 /* 76578 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27735 /* 76580 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27736 /* 76582 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27737 /* 76584 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27738 /* 76587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27739 /* 76593 */ GIR_RootConstrainSelectedInstOperands,
27740 /* 76594 */ // GIR_Coverage, 2864,
27741 /* 76594 */ GIR_EraseRootFromParent_Done,
27742 /* 76595 */ // Label 2366: @76595
27743 /* 76595 */ GIM_Reject,
27744 /* 76596 */ // Label 2362: @76596
27745 /* 76596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2367*/ GIMT_Encode4(76650), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2866 //
27746 /* 76603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27747 /* 76606 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27748 /* 76609 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
27749 /* 76612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27750 /* 76616 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27751 /* 76620 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27752 /* 76624 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27753 /* 76628 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4047:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLSHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
27754 /* 76628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv8i16),
27755 /* 76631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27756 /* 76633 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27757 /* 76635 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27758 /* 76637 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27759 /* 76639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27760 /* 76642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27761 /* 76648 */ GIR_RootConstrainSelectedInstOperands,
27762 /* 76649 */ // GIR_Coverage, 2866,
27763 /* 76649 */ GIR_EraseRootFromParent_Done,
27764 /* 76650 */ // Label 2367: @76650
27765 /* 76650 */ GIM_Reject,
27766 /* 76651 */ // Label 2363: @76651
27767 /* 76651 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2368*/ GIMT_Encode4(76705), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2865 //
27768 /* 76658 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
27769 /* 76661 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
27770 /* 76664 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
27771 /* 76667 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27772 /* 76671 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27773 /* 76675 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27774 /* 76679 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
27775 /* 76683 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4047:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLSHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
27776 /* 76683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv2i32),
27777 /* 76686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27778 /* 76688 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27779 /* 76690 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27780 /* 76692 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27781 /* 76694 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27782 /* 76697 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27783 /* 76703 */ GIR_RootConstrainSelectedInstOperands,
27784 /* 76704 */ // GIR_Coverage, 2865,
27785 /* 76704 */ GIR_EraseRootFromParent_Done,
27786 /* 76705 */ // Label 2368: @76705
27787 /* 76705 */ GIM_Reject,
27788 /* 76706 */ // Label 2364: @76706
27789 /* 76706 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2369*/ GIMT_Encode4(76760), GIMT_Encode2(GIFBS_HasNEON_HasV8_1a), // Rule ID 2867 //
27790 /* 76713 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27791 /* 76716 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27792 /* 76719 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27793 /* 76722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27794 /* 76726 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27795 /* 76730 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27796 /* 76734 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
27797 /* 76738 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4047:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLSHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
27798 /* 76738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i32),
27799 /* 76741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
27800 /* 76743 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
27801 /* 76745 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
27802 /* 76747 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
27803 /* 76749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
27804 /* 76752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27805 /* 76758 */ GIR_RootConstrainSelectedInstOperands,
27806 /* 76759 */ // GIR_Coverage, 2867,
27807 /* 76759 */ GIR_EraseRootFromParent_Done,
27808 /* 76760 */ // Label 2369: @76760
27809 /* 76760 */ GIM_Reject,
27810 /* 76761 */ // Label 2365: @76761
27811 /* 76761 */ GIM_Reject,
27812 /* 76762 */ // Label 2360: @76762
27813 /* 76762 */ GIM_Try, /*On fail goto*//*Label 2370*/ GIMT_Encode4(76918),
27814 /* 76767 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
27815 /* 76772 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2373*/ GIMT_Encode4(76917),
27816 /* 76783 */ /*GILLT_v8s16*//*Label 2371*/ GIMT_Encode4(76795), GIMT_Encode4(0),
27817 /* 76791 */ /*GILLT_v4s32*//*Label 2372*/ GIMT_Encode4(76856),
27818 /* 76795 */ // Label 2371: @76795
27819 /* 76795 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2374*/ GIMT_Encode4(76855), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4446 //
27820 /* 76802 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27821 /* 76805 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27822 /* 76808 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
27823 /* 76811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27824 /* 76815 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27825 /* 76819 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27826 /* 76823 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27827 /* 76827 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3761:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
27828 /* 76827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16),
27829 /* 76830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27830 /* 76832 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
27831 /* 76834 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
27832 /* 76836 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
27833 /* 76838 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27834 /* 76841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27835 /* 76847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27836 /* 76853 */ GIR_RootConstrainSelectedInstOperands,
27837 /* 76854 */ // GIR_Coverage, 4446,
27838 /* 76854 */ GIR_EraseRootFromParent_Done,
27839 /* 76855 */ // Label 2374: @76855
27840 /* 76855 */ GIM_Reject,
27841 /* 76856 */ // Label 2372: @76856
27842 /* 76856 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2375*/ GIMT_Encode4(76916), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4442 //
27843 /* 76863 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27844 /* 76866 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27845 /* 76869 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27846 /* 76872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27847 /* 76876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27848 /* 76880 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27849 /* 76884 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27850 /* 76888 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3761:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
27851 /* 76888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32),
27852 /* 76891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27853 /* 76893 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
27854 /* 76895 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
27855 /* 76897 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
27856 /* 76899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27857 /* 76902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27858 /* 76908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27859 /* 76914 */ GIR_RootConstrainSelectedInstOperands,
27860 /* 76915 */ // GIR_Coverage, 4442,
27861 /* 76915 */ GIR_EraseRootFromParent_Done,
27862 /* 76916 */ // Label 2375: @76916
27863 /* 76916 */ GIM_Reject,
27864 /* 76917 */ // Label 2373: @76917
27865 /* 76917 */ GIM_Reject,
27866 /* 76918 */ // Label 2370: @76918
27867 /* 76918 */ GIM_Try, /*On fail goto*//*Label 2376*/ GIMT_Encode4(77143),
27868 /* 76923 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah),
27869 /* 76928 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2380*/ GIMT_Encode4(77142),
27870 /* 76939 */ /*GILLT_v16s8*//*Label 2377*/ GIMT_Encode4(76959), GIMT_Encode4(0),
27871 /* 76947 */ /*GILLT_v8s16*//*Label 2378*/ GIMT_Encode4(77020), GIMT_Encode4(0),
27872 /* 76955 */ /*GILLT_v4s32*//*Label 2379*/ GIMT_Encode4(77081),
27873 /* 76959 */ // Label 2377: @76959
27874 /* 76959 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2381*/ GIMT_Encode4(77019), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5375 //
27875 /* 76966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27876 /* 76969 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27877 /* 76972 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27878 /* 76975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27879 /* 76979 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27880 /* 76983 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27881 /* 76987 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27882 /* 76991 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3891:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
27883 /* 76991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs8),
27884 /* 76994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27885 /* 76996 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
27886 /* 76998 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
27887 /* 77000 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
27888 /* 77002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27889 /* 77005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27890 /* 77011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27891 /* 77017 */ GIR_RootConstrainSelectedInstOperands,
27892 /* 77018 */ // GIR_Coverage, 5375,
27893 /* 77018 */ GIR_EraseRootFromParent_Done,
27894 /* 77019 */ // Label 2381: @77019
27895 /* 77019 */ GIM_Reject,
27896 /* 77020 */ // Label 2378: @77020
27897 /* 77020 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2382*/ GIMT_Encode4(77080), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5377 //
27898 /* 77027 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27899 /* 77030 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27900 /* 77033 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27901 /* 77036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27902 /* 77040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27903 /* 77044 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27904 /* 77048 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27905 /* 77052 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3891:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
27906 /* 77052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs16),
27907 /* 77055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27908 /* 77057 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
27909 /* 77059 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
27910 /* 77061 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
27911 /* 77063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27912 /* 77066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27913 /* 77072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27914 /* 77078 */ GIR_RootConstrainSelectedInstOperands,
27915 /* 77079 */ // GIR_Coverage, 5377,
27916 /* 77079 */ GIR_EraseRootFromParent_Done,
27917 /* 77080 */ // Label 2382: @77080
27918 /* 77080 */ GIM_Reject,
27919 /* 77081 */ // Label 2379: @77081
27920 /* 77081 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2383*/ GIMT_Encode4(77141), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5379 //
27921 /* 77088 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27922 /* 77091 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27923 /* 77094 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27924 /* 77097 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27925 /* 77101 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27926 /* 77105 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27927 /* 77109 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27928 /* 77113 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3891:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
27929 /* 77113 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs32),
27930 /* 77116 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27931 /* 77118 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
27932 /* 77120 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
27933 /* 77122 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
27934 /* 77124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27935 /* 77127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27936 /* 77133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27937 /* 77139 */ GIR_RootConstrainSelectedInstOperands,
27938 /* 77140 */ // GIR_Coverage, 5379,
27939 /* 77140 */ GIR_EraseRootFromParent_Done,
27940 /* 77141 */ // Label 2383: @77141
27941 /* 77141 */ GIM_Reject,
27942 /* 77142 */ // Label 2380: @77142
27943 /* 77142 */ GIM_Reject,
27944 /* 77143 */ // Label 2376: @77143
27945 /* 77143 */ GIM_Try, /*On fail goto*//*Label 2384*/ GIMT_Encode4(77368),
27946 /* 77148 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah),
27947 /* 77153 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2388*/ GIMT_Encode4(77367),
27948 /* 77164 */ /*GILLT_v16s8*//*Label 2385*/ GIMT_Encode4(77184), GIMT_Encode4(0),
27949 /* 77172 */ /*GILLT_v8s16*//*Label 2386*/ GIMT_Encode4(77245), GIMT_Encode4(0),
27950 /* 77180 */ /*GILLT_v4s32*//*Label 2387*/ GIMT_Encode4(77306),
27951 /* 77184 */ // Label 2385: @77184
27952 /* 77184 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2389*/ GIMT_Encode4(77244), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5381 //
27953 /* 77191 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27954 /* 77194 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27955 /* 77197 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27956 /* 77200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27957 /* 77204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27958 /* 77208 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27959 /* 77212 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27960 /* 77216 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3900:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
27961 /* 77216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs8),
27962 /* 77219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27963 /* 77221 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
27964 /* 77223 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
27965 /* 77225 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
27966 /* 77227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27967 /* 77230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27968 /* 77236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27969 /* 77242 */ GIR_RootConstrainSelectedInstOperands,
27970 /* 77243 */ // GIR_Coverage, 5381,
27971 /* 77243 */ GIR_EraseRootFromParent_Done,
27972 /* 77244 */ // Label 2389: @77244
27973 /* 77244 */ GIM_Reject,
27974 /* 77245 */ // Label 2386: @77245
27975 /* 77245 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2390*/ GIMT_Encode4(77305), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5383 //
27976 /* 77252 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27977 /* 77255 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27978 /* 77258 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27979 /* 77261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27980 /* 77265 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27981 /* 77269 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27982 /* 77273 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
27983 /* 77277 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3900:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
27984 /* 77277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs16),
27985 /* 77280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27986 /* 77282 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
27987 /* 77284 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
27988 /* 77286 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
27989 /* 77288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27990 /* 77291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27991 /* 77297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27992 /* 77303 */ GIR_RootConstrainSelectedInstOperands,
27993 /* 77304 */ // GIR_Coverage, 5383,
27994 /* 77304 */ GIR_EraseRootFromParent_Done,
27995 /* 77305 */ // Label 2390: @77305
27996 /* 77305 */ GIM_Reject,
27997 /* 77306 */ // Label 2387: @77306
27998 /* 77306 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2391*/ GIMT_Encode4(77366), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5385 //
27999 /* 77313 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28000 /* 77316 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28001 /* 77319 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28002 /* 77322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28003 /* 77326 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28004 /* 77330 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28005 /* 77334 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28006 /* 77338 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3900:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28007 /* 77338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs32),
28008 /* 77341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28009 /* 77343 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28010 /* 77345 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28011 /* 77347 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28012 /* 77349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28013 /* 77352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28014 /* 77358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28015 /* 77364 */ GIR_RootConstrainSelectedInstOperands,
28016 /* 77365 */ // GIR_Coverage, 5385,
28017 /* 77365 */ GIR_EraseRootFromParent_Done,
28018 /* 77366 */ // Label 2391: @77366
28019 /* 77366 */ GIM_Reject,
28020 /* 77367 */ // Label 2388: @77367
28021 /* 77367 */ GIM_Reject,
28022 /* 77368 */ // Label 2384: @77368
28023 /* 77368 */ GIM_Try, /*On fail goto*//*Label 2392*/ GIMT_Encode4(77593),
28024 /* 77373 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash),
28025 /* 77378 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2396*/ GIMT_Encode4(77592),
28026 /* 77389 */ /*GILLT_v16s8*//*Label 2393*/ GIMT_Encode4(77409), GIMT_Encode4(0),
28027 /* 77397 */ /*GILLT_v8s16*//*Label 2394*/ GIMT_Encode4(77470), GIMT_Encode4(0),
28028 /* 77405 */ /*GILLT_v4s32*//*Label 2395*/ GIMT_Encode4(77531),
28029 /* 77409 */ // Label 2393: @77409
28030 /* 77409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2397*/ GIMT_Encode4(77469), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5387 //
28031 /* 77416 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28032 /* 77419 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28033 /* 77422 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28034 /* 77425 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28035 /* 77429 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28036 /* 77433 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28037 /* 77437 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28038 /* 77441 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3893:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28039 /* 77441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs8),
28040 /* 77444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28041 /* 77446 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28042 /* 77448 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28043 /* 77450 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28044 /* 77452 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28045 /* 77455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28046 /* 77461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28047 /* 77467 */ GIR_RootConstrainSelectedInstOperands,
28048 /* 77468 */ // GIR_Coverage, 5387,
28049 /* 77468 */ GIR_EraseRootFromParent_Done,
28050 /* 77469 */ // Label 2397: @77469
28051 /* 77469 */ GIM_Reject,
28052 /* 77470 */ // Label 2394: @77470
28053 /* 77470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2398*/ GIMT_Encode4(77530), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5389 //
28054 /* 77477 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28055 /* 77480 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28056 /* 77483 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28057 /* 77486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28058 /* 77490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28059 /* 77494 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28060 /* 77498 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28061 /* 77502 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3893:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28062 /* 77502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs16),
28063 /* 77505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28064 /* 77507 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28065 /* 77509 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28066 /* 77511 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28067 /* 77513 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28068 /* 77516 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28069 /* 77522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28070 /* 77528 */ GIR_RootConstrainSelectedInstOperands,
28071 /* 77529 */ // GIR_Coverage, 5389,
28072 /* 77529 */ GIR_EraseRootFromParent_Done,
28073 /* 77530 */ // Label 2398: @77530
28074 /* 77530 */ GIM_Reject,
28075 /* 77531 */ // Label 2395: @77531
28076 /* 77531 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2399*/ GIMT_Encode4(77591), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5391 //
28077 /* 77538 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28078 /* 77541 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28079 /* 77544 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28080 /* 77547 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28081 /* 77551 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28082 /* 77555 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28083 /* 77559 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28084 /* 77563 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3893:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28085 /* 77563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs32),
28086 /* 77566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28087 /* 77568 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28088 /* 77570 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28089 /* 77572 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28090 /* 77574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28091 /* 77577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28092 /* 77583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28093 /* 77589 */ GIR_RootConstrainSelectedInstOperands,
28094 /* 77590 */ // GIR_Coverage, 5391,
28095 /* 77590 */ GIR_EraseRootFromParent_Done,
28096 /* 77591 */ // Label 2399: @77591
28097 /* 77591 */ GIM_Reject,
28098 /* 77592 */ // Label 2396: @77592
28099 /* 77592 */ GIM_Reject,
28100 /* 77593 */ // Label 2392: @77593
28101 /* 77593 */ GIM_Try, /*On fail goto*//*Label 2400*/ GIMT_Encode4(77818),
28102 /* 77598 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash),
28103 /* 77603 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2404*/ GIMT_Encode4(77817),
28104 /* 77614 */ /*GILLT_v16s8*//*Label 2401*/ GIMT_Encode4(77634), GIMT_Encode4(0),
28105 /* 77622 */ /*GILLT_v8s16*//*Label 2402*/ GIMT_Encode4(77695), GIMT_Encode4(0),
28106 /* 77630 */ /*GILLT_v4s32*//*Label 2403*/ GIMT_Encode4(77756),
28107 /* 77634 */ // Label 2401: @77634
28108 /* 77634 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2405*/ GIMT_Encode4(77694), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5393 //
28109 /* 77641 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28110 /* 77644 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28111 /* 77647 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28112 /* 77650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28113 /* 77654 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28114 /* 77658 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28115 /* 77662 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28116 /* 77666 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3902:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
28117 /* 77666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs8),
28118 /* 77669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28119 /* 77671 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28120 /* 77673 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28121 /* 77675 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28122 /* 77677 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28123 /* 77680 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28124 /* 77686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28125 /* 77692 */ GIR_RootConstrainSelectedInstOperands,
28126 /* 77693 */ // GIR_Coverage, 5393,
28127 /* 77693 */ GIR_EraseRootFromParent_Done,
28128 /* 77694 */ // Label 2405: @77694
28129 /* 77694 */ GIM_Reject,
28130 /* 77695 */ // Label 2402: @77695
28131 /* 77695 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2406*/ GIMT_Encode4(77755), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5395 //
28132 /* 77702 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28133 /* 77705 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28134 /* 77708 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28135 /* 77711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28136 /* 77715 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28137 /* 77719 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28138 /* 77723 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28139 /* 77727 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3902:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
28140 /* 77727 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs16),
28141 /* 77730 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28142 /* 77732 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28143 /* 77734 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28144 /* 77736 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28145 /* 77738 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28146 /* 77741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28147 /* 77747 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28148 /* 77753 */ GIR_RootConstrainSelectedInstOperands,
28149 /* 77754 */ // GIR_Coverage, 5395,
28150 /* 77754 */ GIR_EraseRootFromParent_Done,
28151 /* 77755 */ // Label 2406: @77755
28152 /* 77755 */ GIM_Reject,
28153 /* 77756 */ // Label 2403: @77756
28154 /* 77756 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2407*/ GIMT_Encode4(77816), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5397 //
28155 /* 77763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28156 /* 77766 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28157 /* 77769 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28158 /* 77772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28159 /* 77776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28160 /* 77780 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28161 /* 77784 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28162 /* 77788 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3902:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
28163 /* 77788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs32),
28164 /* 77791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28165 /* 77793 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
28166 /* 77795 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
28167 /* 77797 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
28168 /* 77799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28169 /* 77802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28170 /* 77808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28171 /* 77814 */ GIR_RootConstrainSelectedInstOperands,
28172 /* 77815 */ // GIR_Coverage, 5397,
28173 /* 77815 */ GIR_EraseRootFromParent_Done,
28174 /* 77816 */ // Label 2407: @77816
28175 /* 77816 */ GIM_Reject,
28176 /* 77817 */ // Label 2404: @77817
28177 /* 77817 */ GIM_Reject,
28178 /* 77818 */ // Label 2400: @77818
28179 /* 77818 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2408*/ GIMT_Encode4(77931), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3083 //
28180 /* 77825 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1c),
28181 /* 77830 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28182 /* 77833 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28183 /* 77836 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28184 /* 77839 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28185 /* 77842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28186 /* 77846 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3963:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1C:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
28187 /* 77846 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
28188 /* 77849 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28189 /* 77853 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28190 /* 77858 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
28191 /* 77862 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
28192 /* 77867 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
28193 /* 77870 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28194 /* 77874 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28195 /* 77879 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
28196 /* 77881 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
28197 /* 77884 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
28198 /* 77888 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28199 /* 77893 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
28200 /* 77896 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
28201 /* 77899 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17,
28202 /* 77902 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
28203 /* 77907 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
28204 /* 77912 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
28205 /* 77917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1C),
28206 /* 77920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28207 /* 77922 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd
28208 /* 77924 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28209 /* 77927 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk
28210 /* 77929 */ GIR_RootConstrainSelectedInstOperands,
28211 /* 77930 */ // GIR_Coverage, 3083,
28212 /* 77930 */ GIR_EraseRootFromParent_Done,
28213 /* 77931 */ // Label 2408: @77931
28214 /* 77931 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2409*/ GIMT_Encode4(78044), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3084 //
28215 /* 77938 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1m),
28216 /* 77943 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28217 /* 77946 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28218 /* 77949 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28219 /* 77952 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28220 /* 77955 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28221 /* 77959 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3965:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1M:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
28222 /* 77959 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
28223 /* 77962 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28224 /* 77966 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28225 /* 77971 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
28226 /* 77975 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
28227 /* 77980 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
28228 /* 77983 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28229 /* 77987 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28230 /* 77992 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
28231 /* 77994 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
28232 /* 77997 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
28233 /* 78001 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28234 /* 78006 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
28235 /* 78009 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
28236 /* 78012 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17,
28237 /* 78015 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
28238 /* 78020 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
28239 /* 78025 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
28240 /* 78030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1M),
28241 /* 78033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28242 /* 78035 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd
28243 /* 78037 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28244 /* 78040 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk
28245 /* 78042 */ GIR_RootConstrainSelectedInstOperands,
28246 /* 78043 */ // GIR_Coverage, 3084,
28247 /* 78043 */ GIR_EraseRootFromParent_Done,
28248 /* 78044 */ // Label 2409: @78044
28249 /* 78044 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2410*/ GIMT_Encode4(78157), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3085 //
28250 /* 78051 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1p),
28251 /* 78056 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28252 /* 78059 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28253 /* 78062 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28254 /* 78065 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28255 /* 78068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28256 /* 78072 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3966:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1P:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (INSERT_SUBREG:{ *:[v16i8] } (IMPLICIT_DEF:{ *:[v16i8] }), (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
28257 /* 78072 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
28258 /* 78075 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
28259 /* 78079 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28260 /* 78084 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
28261 /* 78088 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
28262 /* 78093 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
28263 /* 78096 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28264 /* 78100 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28265 /* 78105 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
28266 /* 78107 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
28267 /* 78110 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
28268 /* 78114 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28269 /* 78119 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
28270 /* 78122 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
28271 /* 78125 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17,
28272 /* 78128 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
28273 /* 78133 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
28274 /* 78138 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
28275 /* 78143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1P),
28276 /* 78146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28277 /* 78148 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd
28278 /* 78150 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28279 /* 78153 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk
28280 /* 78155 */ GIR_RootConstrainSelectedInstOperands,
28281 /* 78156 */ // GIR_Coverage, 3085,
28282 /* 78156 */ GIR_EraseRootFromParent_Done,
28283 /* 78157 */ // Label 2410: @78157
28284 /* 78157 */ GIM_Reject,
28285 /* 78158 */ // Label 2103: @78158
28286 /* 78158 */ GIM_Try, /*On fail goto*//*Label 2411*/ GIMT_Encode4(80997),
28287 /* 78163 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
28288 /* 78166 */ GIM_Try, /*On fail goto*//*Label 2412*/ GIMT_Encode4(78686),
28289 /* 78171 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
28290 /* 78176 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2415*/ GIMT_Encode4(78685),
28291 /* 78187 */ /*GILLT_v8s16*//*Label 2413*/ GIMT_Encode4(78199), GIMT_Encode4(0),
28292 /* 78195 */ /*GILLT_v4s32*//*Label 2414*/ GIMT_Encode4(78442),
28293 /* 78199 */ // Label 2413: @78199
28294 /* 78199 */ GIM_Try, /*On fail goto*//*Label 2416*/ GIMT_Encode4(78441),
28295 /* 78204 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28296 /* 78207 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28297 /* 78210 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28298 /* 78213 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28299 /* 78216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28300 /* 78220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28301 /* 78224 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
28302 /* 78228 */ GIM_Try, /*On fail goto*//*Label 2417*/ GIMT_Encode4(78334),
28303 /* 78233 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
28304 /* 78237 */ GIM_Try, /*On fail goto*//*Label 2418*/ GIMT_Encode4(78285), // Rule ID 4130 //
28305 /* 78242 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28306 /* 78246 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3937:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28307 /* 78246 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28308 /* 78249 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28309 /* 78253 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28310 /* 78258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8bh),
28311 /* 78261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28312 /* 78263 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28313 /* 78265 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28314 /* 78268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28315 /* 78274 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28316 /* 78280 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28317 /* 78283 */ GIR_RootConstrainSelectedInstOperands,
28318 /* 78284 */ // GIR_Coverage, 4130,
28319 /* 78284 */ GIR_EraseRootFromParent_Done,
28320 /* 78285 */ // Label 2418: @78285
28321 /* 78285 */ GIM_Try, /*On fail goto*//*Label 2419*/ GIMT_Encode4(78333), // Rule ID 4134 //
28322 /* 78290 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28323 /* 78294 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3937:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28324 /* 78294 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28325 /* 78297 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28326 /* 78301 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28327 /* 78306 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8th),
28328 /* 78309 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28329 /* 78311 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28330 /* 78313 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28331 /* 78316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28332 /* 78322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28333 /* 78328 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28334 /* 78331 */ GIR_RootConstrainSelectedInstOperands,
28335 /* 78332 */ // GIR_Coverage, 4134,
28336 /* 78332 */ GIR_EraseRootFromParent_Done,
28337 /* 78333 */ // Label 2419: @78333
28338 /* 78333 */ GIM_Reject,
28339 /* 78334 */ // Label 2417: @78334
28340 /* 78334 */ GIM_Try, /*On fail goto*//*Label 2420*/ GIMT_Encode4(78440),
28341 /* 78339 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
28342 /* 78343 */ GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(78391), // Rule ID 4146 //
28343 /* 78348 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28344 /* 78352 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3937:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28345 /* 78352 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28346 /* 78355 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28347 /* 78359 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28348 /* 78364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8bh),
28349 /* 78367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28350 /* 78369 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28351 /* 78371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28352 /* 78374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28353 /* 78380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28354 /* 78386 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28355 /* 78389 */ GIR_RootConstrainSelectedInstOperands,
28356 /* 78390 */ // GIR_Coverage, 4146,
28357 /* 78390 */ GIR_EraseRootFromParent_Done,
28358 /* 78391 */ // Label 2421: @78391
28359 /* 78391 */ GIM_Try, /*On fail goto*//*Label 2422*/ GIMT_Encode4(78439), // Rule ID 4150 //
28360 /* 78396 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28361 /* 78400 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3937:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
28362 /* 78400 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28363 /* 78403 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28364 /* 78407 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28365 /* 78412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8th),
28366 /* 78415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28367 /* 78417 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28368 /* 78419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28369 /* 78422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28370 /* 78428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28371 /* 78434 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28372 /* 78437 */ GIR_RootConstrainSelectedInstOperands,
28373 /* 78438 */ // GIR_Coverage, 4150,
28374 /* 78438 */ GIR_EraseRootFromParent_Done,
28375 /* 78439 */ // Label 2422: @78439
28376 /* 78439 */ GIM_Reject,
28377 /* 78440 */ // Label 2420: @78440
28378 /* 78440 */ GIM_Reject,
28379 /* 78441 */ // Label 2416: @78441
28380 /* 78441 */ GIM_Reject,
28381 /* 78442 */ // Label 2414: @78442
28382 /* 78442 */ GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(78684),
28383 /* 78447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28384 /* 78450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28385 /* 78453 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28386 /* 78456 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28387 /* 78459 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28388 /* 78463 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28389 /* 78467 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
28390 /* 78471 */ GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(78577),
28391 /* 78476 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
28392 /* 78480 */ GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(78528), // Rule ID 4138 //
28393 /* 78485 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28394 /* 78489 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3937:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28395 /* 78489 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28396 /* 78492 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28397 /* 78496 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28398 /* 78501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16bh),
28399 /* 78504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28400 /* 78506 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28401 /* 78508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28402 /* 78511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28403 /* 78517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28404 /* 78523 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28405 /* 78526 */ GIR_RootConstrainSelectedInstOperands,
28406 /* 78527 */ // GIR_Coverage, 4138,
28407 /* 78527 */ GIR_EraseRootFromParent_Done,
28408 /* 78528 */ // Label 2425: @78528
28409 /* 78528 */ GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(78576), // Rule ID 4142 //
28410 /* 78533 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28411 /* 78537 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3937:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28412 /* 78537 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28413 /* 78540 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28414 /* 78544 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28415 /* 78549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16th),
28416 /* 78552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28417 /* 78554 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28418 /* 78556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28419 /* 78559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28420 /* 78565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28421 /* 78571 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28422 /* 78574 */ GIR_RootConstrainSelectedInstOperands,
28423 /* 78575 */ // GIR_Coverage, 4142,
28424 /* 78575 */ GIR_EraseRootFromParent_Done,
28425 /* 78576 */ // Label 2426: @78576
28426 /* 78576 */ GIM_Reject,
28427 /* 78577 */ // Label 2424: @78577
28428 /* 78577 */ GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(78683),
28429 /* 78582 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
28430 /* 78586 */ GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(78634), // Rule ID 4154 //
28431 /* 78591 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28432 /* 78595 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3937:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28433 /* 78595 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28434 /* 78598 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28435 /* 78602 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28436 /* 78607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16bh),
28437 /* 78610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28438 /* 78612 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28439 /* 78614 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28440 /* 78617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28441 /* 78623 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28442 /* 78629 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28443 /* 78632 */ GIR_RootConstrainSelectedInstOperands,
28444 /* 78633 */ // GIR_Coverage, 4154,
28445 /* 78633 */ GIR_EraseRootFromParent_Done,
28446 /* 78634 */ // Label 2428: @78634
28447 /* 78634 */ GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(78682), // Rule ID 4158 //
28448 /* 78639 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28449 /* 78643 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3937:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
28450 /* 78643 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28451 /* 78646 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28452 /* 78650 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28453 /* 78655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16th),
28454 /* 78658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28455 /* 78660 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28456 /* 78662 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28457 /* 78665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28458 /* 78671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28459 /* 78677 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28460 /* 78680 */ GIR_RootConstrainSelectedInstOperands,
28461 /* 78681 */ // GIR_Coverage, 4158,
28462 /* 78681 */ GIR_EraseRootFromParent_Done,
28463 /* 78682 */ // Label 2429: @78682
28464 /* 78682 */ GIM_Reject,
28465 /* 78683 */ // Label 2427: @78683
28466 /* 78683 */ GIM_Reject,
28467 /* 78684 */ // Label 2423: @78684
28468 /* 78684 */ GIM_Reject,
28469 /* 78685 */ // Label 2415: @78685
28470 /* 78685 */ GIM_Reject,
28471 /* 78686 */ // Label 2412: @78686
28472 /* 78686 */ GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(79501),
28473 /* 78691 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
28474 /* 78696 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 2434*/ GIMT_Encode4(79500),
28475 /* 78707 */ /*GILLT_v8s16*//*Label 2431*/ GIMT_Encode4(78723), GIMT_Encode4(0),
28476 /* 78715 */ /*GILLT_v4s32*//*Label 2432*/ GIMT_Encode4(78982),
28477 /* 78719 */ /*GILLT_v2s64*//*Label 2433*/ GIMT_Encode4(79241),
28478 /* 78723 */ // Label 2431: @78723
28479 /* 78723 */ GIM_Try, /*On fail goto*//*Label 2435*/ GIMT_Encode4(78981),
28480 /* 78728 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
28481 /* 78731 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28482 /* 78734 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28483 /* 78737 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28484 /* 78740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28485 /* 78744 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28486 /* 78748 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28487 /* 78752 */ GIM_Try, /*On fail goto*//*Label 2436*/ GIMT_Encode4(78866),
28488 /* 78757 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
28489 /* 78761 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2437*/ GIMT_Encode4(78813), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4898 //
28490 /* 78768 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28491 /* 78772 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3887:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
28492 /* 78772 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28493 /* 78775 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28494 /* 78779 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28495 /* 78784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8),
28496 /* 78787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28497 /* 78789 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28498 /* 78791 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28499 /* 78793 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28500 /* 78796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28501 /* 78802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28502 /* 78808 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28503 /* 78811 */ GIR_RootConstrainSelectedInstOperands,
28504 /* 78812 */ // GIR_Coverage, 4898,
28505 /* 78812 */ GIR_EraseRootFromParent_Done,
28506 /* 78813 */ // Label 2437: @78813
28507 /* 78813 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2438*/ GIMT_Encode4(78865), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4900 //
28508 /* 78820 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28509 /* 78824 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3887:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
28510 /* 78824 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28511 /* 78827 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28512 /* 78831 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28513 /* 78836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs8),
28514 /* 78839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28515 /* 78841 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28516 /* 78843 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28517 /* 78845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28518 /* 78848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28519 /* 78854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28520 /* 78860 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28521 /* 78863 */ GIR_RootConstrainSelectedInstOperands,
28522 /* 78864 */ // GIR_Coverage, 4900,
28523 /* 78864 */ GIR_EraseRootFromParent_Done,
28524 /* 78865 */ // Label 2438: @78865
28525 /* 78865 */ GIM_Reject,
28526 /* 78866 */ // Label 2436: @78866
28527 /* 78866 */ GIM_Try, /*On fail goto*//*Label 2439*/ GIMT_Encode4(78980),
28528 /* 78871 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
28529 /* 78875 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2440*/ GIMT_Encode4(78927), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4910 //
28530 /* 78882 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28531 /* 78886 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3887:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
28532 /* 78886 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28533 /* 78889 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28534 /* 78893 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28535 /* 78898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu8),
28536 /* 78901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28537 /* 78903 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28538 /* 78905 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28539 /* 78907 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28540 /* 78910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28541 /* 78916 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28542 /* 78922 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28543 /* 78925 */ GIR_RootConstrainSelectedInstOperands,
28544 /* 78926 */ // GIR_Coverage, 4910,
28545 /* 78926 */ GIR_EraseRootFromParent_Done,
28546 /* 78927 */ // Label 2440: @78927
28547 /* 78927 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2441*/ GIMT_Encode4(78979), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4912 //
28548 /* 78934 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28549 /* 78938 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3887:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
28550 /* 78938 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28551 /* 78941 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28552 /* 78945 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28553 /* 78950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu8),
28554 /* 78953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28555 /* 78955 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28556 /* 78957 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28557 /* 78959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28558 /* 78962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28559 /* 78968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28560 /* 78974 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28561 /* 78977 */ GIR_RootConstrainSelectedInstOperands,
28562 /* 78978 */ // GIR_Coverage, 4912,
28563 /* 78978 */ GIR_EraseRootFromParent_Done,
28564 /* 78979 */ // Label 2441: @78979
28565 /* 78979 */ GIM_Reject,
28566 /* 78980 */ // Label 2439: @78980
28567 /* 78980 */ GIM_Reject,
28568 /* 78981 */ // Label 2435: @78981
28569 /* 78981 */ GIM_Reject,
28570 /* 78982 */ // Label 2432: @78982
28571 /* 78982 */ GIM_Try, /*On fail goto*//*Label 2442*/ GIMT_Encode4(79240),
28572 /* 78987 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28573 /* 78990 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28574 /* 78993 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28575 /* 78996 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28576 /* 78999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28577 /* 79003 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28578 /* 79007 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28579 /* 79011 */ GIM_Try, /*On fail goto*//*Label 2443*/ GIMT_Encode4(79125),
28580 /* 79016 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
28581 /* 79020 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2444*/ GIMT_Encode4(79072), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4902 //
28582 /* 79027 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28583 /* 79031 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3887:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
28584 /* 79031 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28585 /* 79034 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28586 /* 79038 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28587 /* 79043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16),
28588 /* 79046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28589 /* 79048 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28590 /* 79050 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28591 /* 79052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28592 /* 79055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28593 /* 79061 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28594 /* 79067 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28595 /* 79070 */ GIR_RootConstrainSelectedInstOperands,
28596 /* 79071 */ // GIR_Coverage, 4902,
28597 /* 79071 */ GIR_EraseRootFromParent_Done,
28598 /* 79072 */ // Label 2444: @79072
28599 /* 79072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2445*/ GIMT_Encode4(79124), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4904 //
28600 /* 79079 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28601 /* 79083 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3887:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
28602 /* 79083 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28603 /* 79086 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28604 /* 79090 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28605 /* 79095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs16),
28606 /* 79098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28607 /* 79100 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28608 /* 79102 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28609 /* 79104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28610 /* 79107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28611 /* 79113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28612 /* 79119 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28613 /* 79122 */ GIR_RootConstrainSelectedInstOperands,
28614 /* 79123 */ // GIR_Coverage, 4904,
28615 /* 79123 */ GIR_EraseRootFromParent_Done,
28616 /* 79124 */ // Label 2445: @79124
28617 /* 79124 */ GIM_Reject,
28618 /* 79125 */ // Label 2443: @79125
28619 /* 79125 */ GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(79239),
28620 /* 79130 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
28621 /* 79134 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2447*/ GIMT_Encode4(79186), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4914 //
28622 /* 79141 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28623 /* 79145 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3887:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
28624 /* 79145 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28625 /* 79148 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28626 /* 79152 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28627 /* 79157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu16),
28628 /* 79160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28629 /* 79162 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28630 /* 79164 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28631 /* 79166 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28632 /* 79169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28633 /* 79175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28634 /* 79181 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28635 /* 79184 */ GIR_RootConstrainSelectedInstOperands,
28636 /* 79185 */ // GIR_Coverage, 4914,
28637 /* 79185 */ GIR_EraseRootFromParent_Done,
28638 /* 79186 */ // Label 2447: @79186
28639 /* 79186 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2448*/ GIMT_Encode4(79238), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4916 //
28640 /* 79193 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28641 /* 79197 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3887:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
28642 /* 79197 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28643 /* 79200 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28644 /* 79204 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28645 /* 79209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu16),
28646 /* 79212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28647 /* 79214 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28648 /* 79216 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28649 /* 79218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28650 /* 79221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28651 /* 79227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28652 /* 79233 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28653 /* 79236 */ GIR_RootConstrainSelectedInstOperands,
28654 /* 79237 */ // GIR_Coverage, 4916,
28655 /* 79237 */ GIR_EraseRootFromParent_Done,
28656 /* 79238 */ // Label 2448: @79238
28657 /* 79238 */ GIM_Reject,
28658 /* 79239 */ // Label 2446: @79239
28659 /* 79239 */ GIM_Reject,
28660 /* 79240 */ // Label 2442: @79240
28661 /* 79240 */ GIM_Reject,
28662 /* 79241 */ // Label 2433: @79241
28663 /* 79241 */ GIM_Try, /*On fail goto*//*Label 2449*/ GIMT_Encode4(79499),
28664 /* 79246 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28665 /* 79249 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28666 /* 79252 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28667 /* 79255 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
28668 /* 79258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28669 /* 79262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28670 /* 79266 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28671 /* 79270 */ GIM_Try, /*On fail goto*//*Label 2450*/ GIMT_Encode4(79384),
28672 /* 79275 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
28673 /* 79279 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2451*/ GIMT_Encode4(79331), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4906 //
28674 /* 79286 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28675 /* 79290 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3887:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
28676 /* 79290 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28677 /* 79293 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28678 /* 79297 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28679 /* 79302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs32),
28680 /* 79305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28681 /* 79307 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28682 /* 79309 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28683 /* 79311 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28684 /* 79314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28685 /* 79320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28686 /* 79326 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28687 /* 79329 */ GIR_RootConstrainSelectedInstOperands,
28688 /* 79330 */ // GIR_Coverage, 4906,
28689 /* 79330 */ GIR_EraseRootFromParent_Done,
28690 /* 79331 */ // Label 2451: @79331
28691 /* 79331 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2452*/ GIMT_Encode4(79383), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4908 //
28692 /* 79338 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28693 /* 79342 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3887:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
28694 /* 79342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28695 /* 79345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28696 /* 79349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28697 /* 79354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs32),
28698 /* 79357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28699 /* 79359 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28700 /* 79361 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28701 /* 79363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28702 /* 79366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28703 /* 79372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28704 /* 79378 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28705 /* 79381 */ GIR_RootConstrainSelectedInstOperands,
28706 /* 79382 */ // GIR_Coverage, 4908,
28707 /* 79382 */ GIR_EraseRootFromParent_Done,
28708 /* 79383 */ // Label 2452: @79383
28709 /* 79383 */ GIM_Reject,
28710 /* 79384 */ // Label 2450: @79384
28711 /* 79384 */ GIM_Try, /*On fail goto*//*Label 2453*/ GIMT_Encode4(79498),
28712 /* 79389 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
28713 /* 79393 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2454*/ GIMT_Encode4(79445), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4918 //
28714 /* 79400 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
28715 /* 79404 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3887:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
28716 /* 79404 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28717 /* 79407 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28718 /* 79411 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28719 /* 79416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu32),
28720 /* 79419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28721 /* 79421 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28722 /* 79423 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28723 /* 79425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28724 /* 79428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28725 /* 79434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28726 /* 79440 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28727 /* 79443 */ GIR_RootConstrainSelectedInstOperands,
28728 /* 79444 */ // GIR_Coverage, 4918,
28729 /* 79444 */ GIR_EraseRootFromParent_Done,
28730 /* 79445 */ // Label 2454: @79445
28731 /* 79445 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2455*/ GIMT_Encode4(79497), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4920 //
28732 /* 79452 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
28733 /* 79456 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3887:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
28734 /* 79456 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28735 /* 79459 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28736 /* 79463 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28737 /* 79468 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu32),
28738 /* 79471 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28739 /* 79473 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
28740 /* 79475 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
28741 /* 79477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28742 /* 79480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28743 /* 79486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28744 /* 79492 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28745 /* 79495 */ GIR_RootConstrainSelectedInstOperands,
28746 /* 79496 */ // GIR_Coverage, 4920,
28747 /* 79496 */ GIR_EraseRootFromParent_Done,
28748 /* 79497 */ // Label 2455: @79497
28749 /* 79497 */ GIM_Reject,
28750 /* 79498 */ // Label 2453: @79498
28751 /* 79498 */ GIM_Reject,
28752 /* 79499 */ // Label 2449: @79499
28753 /* 79499 */ GIM_Reject,
28754 /* 79500 */ // Label 2434: @79500
28755 /* 79500 */ GIM_Reject,
28756 /* 79501 */ // Label 2430: @79501
28757 /* 79501 */ GIM_Try, /*On fail goto*//*Label 2456*/ GIMT_Encode4(80184),
28758 /* 79506 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
28759 /* 79511 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2460*/ GIMT_Encode4(80183),
28760 /* 79522 */ /*GILLT_v16s8*//*Label 2457*/ GIMT_Encode4(79542), GIMT_Encode4(0),
28761 /* 79530 */ /*GILLT_v8s16*//*Label 2458*/ GIMT_Encode4(79711), GIMT_Encode4(0),
28762 /* 79538 */ /*GILLT_v4s32*//*Label 2459*/ GIMT_Encode4(79947),
28763 /* 79542 */ // Label 2457: @79542
28764 /* 79542 */ GIM_Try, /*On fail goto*//*Label 2461*/ GIMT_Encode4(79710),
28765 /* 79547 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28766 /* 79550 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28767 /* 79553 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
28768 /* 79556 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8,
28769 /* 79559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28770 /* 79563 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2462*/ GIMT_Encode4(79636), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5052 //
28771 /* 79570 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
28772 /* 79574 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28773 /* 79578 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28774 /* 79582 */ // MIs[1] Operand 1
28775 /* 79582 */ // No operand predicates
28776 /* 79582 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28777 /* 79586 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28778 /* 79590 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
28779 /* 79592 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3825:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VCADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
28780 /* 79592 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28781 /* 79595 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28782 /* 79599 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28783 /* 79604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi8),
28784 /* 79607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28785 /* 79609 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
28786 /* 79611 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
28787 /* 79613 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28788 /* 79616 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28789 /* 79619 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28790 /* 79625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28791 /* 79631 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28792 /* 79634 */ GIR_RootConstrainSelectedInstOperands,
28793 /* 79635 */ // GIR_Coverage, 5052,
28794 /* 79635 */ GIR_EraseRootFromParent_Done,
28795 /* 79636 */ // Label 2462: @79636
28796 /* 79636 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2463*/ GIMT_Encode4(79709), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5058 //
28797 /* 79643 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
28798 /* 79647 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28799 /* 79651 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28800 /* 79655 */ // MIs[1] Operand 1
28801 /* 79655 */ // No operand predicates
28802 /* 79655 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28803 /* 79659 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28804 /* 79663 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
28805 /* 79665 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3825:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VHCADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
28806 /* 79665 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28807 /* 79668 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28808 /* 79672 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28809 /* 79677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs8),
28810 /* 79680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28811 /* 79682 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
28812 /* 79684 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
28813 /* 79686 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28814 /* 79689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28815 /* 79692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28816 /* 79698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28817 /* 79704 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28818 /* 79707 */ GIR_RootConstrainSelectedInstOperands,
28819 /* 79708 */ // GIR_Coverage, 5058,
28820 /* 79708 */ GIR_EraseRootFromParent_Done,
28821 /* 79709 */ // Label 2463: @79709
28822 /* 79709 */ GIM_Reject,
28823 /* 79710 */ // Label 2461: @79710
28824 /* 79710 */ GIM_Reject,
28825 /* 79711 */ // Label 2458: @79711
28826 /* 79711 */ GIM_Try, /*On fail goto*//*Label 2464*/ GIMT_Encode4(79946),
28827 /* 79716 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28828 /* 79719 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28829 /* 79722 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
28830 /* 79725 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
28831 /* 79728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28832 /* 79732 */ GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(79872),
28833 /* 79737 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
28834 /* 79741 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28835 /* 79745 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28836 /* 79749 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2466*/ GIMT_Encode4(79810), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4483 //
28837 /* 79756 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28838 /* 79760 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28839 /* 79764 */ // MIs[1] Operand 1
28840 /* 79764 */ // No operand predicates
28841 /* 79764 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
28842 /* 79766 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3825:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
28843 /* 79766 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28844 /* 79769 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28845 /* 79773 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28846 /* 79778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf16),
28847 /* 79781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28848 /* 79783 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
28849 /* 79785 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
28850 /* 79787 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28851 /* 79790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28852 /* 79793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28853 /* 79799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28854 /* 79805 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28855 /* 79808 */ GIR_RootConstrainSelectedInstOperands,
28856 /* 79809 */ // GIR_Coverage, 4483,
28857 /* 79809 */ GIR_EraseRootFromParent_Done,
28858 /* 79810 */ // Label 2466: @79810
28859 /* 79810 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2467*/ GIMT_Encode4(79871), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5054 //
28860 /* 79817 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28861 /* 79821 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28862 /* 79825 */ // MIs[1] Operand 1
28863 /* 79825 */ // No operand predicates
28864 /* 79825 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
28865 /* 79827 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3825:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VCADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
28866 /* 79827 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28867 /* 79830 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28868 /* 79834 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28869 /* 79839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi16),
28870 /* 79842 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28871 /* 79844 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
28872 /* 79846 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
28873 /* 79848 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28874 /* 79851 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28875 /* 79854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28876 /* 79860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28877 /* 79866 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28878 /* 79869 */ GIR_RootConstrainSelectedInstOperands,
28879 /* 79870 */ // GIR_Coverage, 5054,
28880 /* 79870 */ GIR_EraseRootFromParent_Done,
28881 /* 79871 */ // Label 2467: @79871
28882 /* 79871 */ GIM_Reject,
28883 /* 79872 */ // Label 2465: @79872
28884 /* 79872 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2468*/ GIMT_Encode4(79945), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5060 //
28885 /* 79879 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
28886 /* 79883 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28887 /* 79887 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28888 /* 79891 */ // MIs[1] Operand 1
28889 /* 79891 */ // No operand predicates
28890 /* 79891 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28891 /* 79895 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28892 /* 79899 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
28893 /* 79901 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3825:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VHCADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
28894 /* 79901 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28895 /* 79904 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28896 /* 79908 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28897 /* 79913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs16),
28898 /* 79916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28899 /* 79918 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
28900 /* 79920 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
28901 /* 79922 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28902 /* 79925 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28903 /* 79928 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28904 /* 79934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28905 /* 79940 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28906 /* 79943 */ GIR_RootConstrainSelectedInstOperands,
28907 /* 79944 */ // GIR_Coverage, 5060,
28908 /* 79944 */ GIR_EraseRootFromParent_Done,
28909 /* 79945 */ // Label 2468: @79945
28910 /* 79945 */ GIM_Reject,
28911 /* 79946 */ // Label 2464: @79946
28912 /* 79946 */ GIM_Reject,
28913 /* 79947 */ // Label 2459: @79947
28914 /* 79947 */ GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(80182),
28915 /* 79952 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28916 /* 79955 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28917 /* 79958 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28918 /* 79961 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
28919 /* 79964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28920 /* 79968 */ GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(80108),
28921 /* 79973 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
28922 /* 79977 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28923 /* 79981 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28924 /* 79985 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2471*/ GIMT_Encode4(80046), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4485 //
28925 /* 79992 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28926 /* 79996 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28927 /* 80000 */ // MIs[1] Operand 1
28928 /* 80000 */ // No operand predicates
28929 /* 80000 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
28930 /* 80002 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3825:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
28931 /* 80002 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28932 /* 80005 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28933 /* 80009 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28934 /* 80014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf32),
28935 /* 80017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28936 /* 80019 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
28937 /* 80021 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
28938 /* 80023 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28939 /* 80026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28940 /* 80029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28941 /* 80035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28942 /* 80041 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28943 /* 80044 */ GIR_RootConstrainSelectedInstOperands,
28944 /* 80045 */ // GIR_Coverage, 4485,
28945 /* 80045 */ GIR_EraseRootFromParent_Done,
28946 /* 80046 */ // Label 2471: @80046
28947 /* 80046 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2472*/ GIMT_Encode4(80107), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5056 //
28948 /* 80053 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28949 /* 80057 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28950 /* 80061 */ // MIs[1] Operand 1
28951 /* 80061 */ // No operand predicates
28952 /* 80061 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
28953 /* 80063 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3825:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VCADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
28954 /* 80063 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28955 /* 80066 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28956 /* 80070 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28957 /* 80075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi32),
28958 /* 80078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28959 /* 80080 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
28960 /* 80082 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
28961 /* 80084 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28962 /* 80087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28963 /* 80090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28964 /* 80096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28965 /* 80102 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28966 /* 80105 */ GIR_RootConstrainSelectedInstOperands,
28967 /* 80106 */ // GIR_Coverage, 5056,
28968 /* 80106 */ GIR_EraseRootFromParent_Done,
28969 /* 80107 */ // Label 2472: @80107
28970 /* 80107 */ GIM_Reject,
28971 /* 80108 */ // Label 2470: @80108
28972 /* 80108 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2473*/ GIMT_Encode4(80181), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5062 //
28973 /* 80115 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
28974 /* 80119 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
28975 /* 80123 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
28976 /* 80127 */ // MIs[1] Operand 1
28977 /* 80127 */ // No operand predicates
28978 /* 80127 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28979 /* 80131 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28980 /* 80135 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
28981 /* 80137 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3825:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VHCADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
28982 /* 80137 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
28983 /* 80140 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
28984 /* 80144 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
28985 /* 80149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs32),
28986 /* 80152 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28987 /* 80154 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
28988 /* 80156 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
28989 /* 80158 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
28990 /* 80161 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
28991 /* 80164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28992 /* 80170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28993 /* 80176 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
28994 /* 80179 */ GIR_RootConstrainSelectedInstOperands,
28995 /* 80180 */ // GIR_Coverage, 5062,
28996 /* 80180 */ GIR_EraseRootFromParent_Done,
28997 /* 80181 */ // Label 2473: @80181
28998 /* 80181 */ GIM_Reject,
28999 /* 80182 */ // Label 2469: @80182
29000 /* 80182 */ GIM_Reject,
29001 /* 80183 */ // Label 2460: @80183
29002 /* 80183 */ GIM_Reject,
29003 /* 80184 */ // Label 2456: @80184
29004 /* 80184 */ GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(80583),
29005 /* 80189 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
29006 /* 80194 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
29007 /* 80197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29008 /* 80200 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29009 /* 80203 */ GIM_SwitchType, /*MI*/0, /*Op*/4, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2478*/ GIMT_Encode4(80582),
29010 /* 80214 */ /*GILLT_v16s8*//*Label 2475*/ GIMT_Encode4(80234), GIMT_Encode4(0),
29011 /* 80222 */ /*GILLT_v8s16*//*Label 2476*/ GIMT_Encode4(80350), GIMT_Encode4(0),
29012 /* 80230 */ /*GILLT_v4s32*//*Label 2477*/ GIMT_Encode4(80466),
29013 /* 80234 */ // Label 2475: @80234
29014 /* 80234 */ GIM_Try, /*On fail goto*//*Label 2479*/ GIMT_Encode4(80349),
29015 /* 80239 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8,
29016 /* 80242 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29017 /* 80246 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2480*/ GIMT_Encode4(80297), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3428 //
29018 /* 80253 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29019 /* 80257 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29020 /* 80261 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29021 /* 80265 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29022 /* 80269 */ // (intrinsic_wo_chain:{ *:[i32] } 3817:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
29023 /* 80269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs8),
29024 /* 80272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
29025 /* 80274 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
29026 /* 80276 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29027 /* 80278 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29028 /* 80280 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29029 /* 80283 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29030 /* 80289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29031 /* 80295 */ GIR_RootConstrainSelectedInstOperands,
29032 /* 80296 */ // GIR_Coverage, 3428,
29033 /* 80296 */ GIR_EraseRootFromParent_Done,
29034 /* 80297 */ // Label 2480: @80297
29035 /* 80297 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2481*/ GIMT_Encode4(80348), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3434 //
29036 /* 80304 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29037 /* 80308 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29038 /* 80312 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29039 /* 80316 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29040 /* 80320 */ // (intrinsic_wo_chain:{ *:[i32] } 3817:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVu8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
29041 /* 80320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu8),
29042 /* 80323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
29043 /* 80325 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
29044 /* 80327 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29045 /* 80329 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29046 /* 80331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29047 /* 80334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29048 /* 80340 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29049 /* 80346 */ GIR_RootConstrainSelectedInstOperands,
29050 /* 80347 */ // GIR_Coverage, 3434,
29051 /* 80347 */ GIR_EraseRootFromParent_Done,
29052 /* 80348 */ // Label 2481: @80348
29053 /* 80348 */ GIM_Reject,
29054 /* 80349 */ // Label 2479: @80349
29055 /* 80349 */ GIM_Reject,
29056 /* 80350 */ // Label 2476: @80350
29057 /* 80350 */ GIM_Try, /*On fail goto*//*Label 2482*/ GIMT_Encode4(80465),
29058 /* 80355 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
29059 /* 80358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29060 /* 80362 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2483*/ GIMT_Encode4(80413), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3430 //
29061 /* 80369 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29062 /* 80373 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29063 /* 80377 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29064 /* 80381 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29065 /* 80385 */ // (intrinsic_wo_chain:{ *:[i32] } 3817:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
29066 /* 80385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs16),
29067 /* 80388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
29068 /* 80390 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
29069 /* 80392 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29070 /* 80394 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29071 /* 80396 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29072 /* 80399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29073 /* 80405 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29074 /* 80411 */ GIR_RootConstrainSelectedInstOperands,
29075 /* 80412 */ // GIR_Coverage, 3430,
29076 /* 80412 */ GIR_EraseRootFromParent_Done,
29077 /* 80413 */ // Label 2483: @80413
29078 /* 80413 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2484*/ GIMT_Encode4(80464), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3436 //
29079 /* 80420 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29080 /* 80424 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29081 /* 80428 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29082 /* 80432 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29083 /* 80436 */ // (intrinsic_wo_chain:{ *:[i32] } 3817:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVu16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
29084 /* 80436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu16),
29085 /* 80439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
29086 /* 80441 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
29087 /* 80443 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29088 /* 80445 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29089 /* 80447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29090 /* 80450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29091 /* 80456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29092 /* 80462 */ GIR_RootConstrainSelectedInstOperands,
29093 /* 80463 */ // GIR_Coverage, 3436,
29094 /* 80463 */ GIR_EraseRootFromParent_Done,
29095 /* 80464 */ // Label 2484: @80464
29096 /* 80464 */ GIM_Reject,
29097 /* 80465 */ // Label 2482: @80465
29098 /* 80465 */ GIM_Reject,
29099 /* 80466 */ // Label 2477: @80466
29100 /* 80466 */ GIM_Try, /*On fail goto*//*Label 2485*/ GIMT_Encode4(80581),
29101 /* 80471 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
29102 /* 80474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29103 /* 80478 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2486*/ GIMT_Encode4(80529), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3432 //
29104 /* 80485 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
29105 /* 80489 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29106 /* 80493 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29107 /* 80497 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29108 /* 80501 */ // (intrinsic_wo_chain:{ *:[i32] } 3817:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
29109 /* 80501 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs32),
29110 /* 80504 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
29111 /* 80506 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
29112 /* 80508 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29113 /* 80510 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29114 /* 80512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29115 /* 80515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29116 /* 80521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29117 /* 80527 */ GIR_RootConstrainSelectedInstOperands,
29118 /* 80528 */ // GIR_Coverage, 3432,
29119 /* 80528 */ GIR_EraseRootFromParent_Done,
29120 /* 80529 */ // Label 2486: @80529
29121 /* 80529 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2487*/ GIMT_Encode4(80580), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3438 //
29122 /* 80536 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29123 /* 80540 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29124 /* 80544 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29125 /* 80548 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29126 /* 80552 */ // (intrinsic_wo_chain:{ *:[i32] } 3817:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVu32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
29127 /* 80552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu32),
29128 /* 80555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
29129 /* 80557 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
29130 /* 80559 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29131 /* 80561 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29132 /* 80563 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29133 /* 80566 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29134 /* 80572 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29135 /* 80578 */ GIR_RootConstrainSelectedInstOperands,
29136 /* 80579 */ // GIR_Coverage, 3438,
29137 /* 80579 */ GIR_EraseRootFromParent_Done,
29138 /* 80580 */ // Label 2487: @80580
29139 /* 80580 */ GIM_Reject,
29140 /* 80581 */ // Label 2485: @80581
29141 /* 80581 */ GIM_Reject,
29142 /* 80582 */ // Label 2478: @80582
29143 /* 80582 */ GIM_Reject,
29144 /* 80583 */ // Label 2474: @80583
29145 /* 80583 */ GIM_Try, /*On fail goto*//*Label 2488*/ GIMT_Encode4(80771),
29146 /* 80588 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq),
29147 /* 80593 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(13), /*)*//*default:*//*Label 2491*/ GIMT_Encode4(80770),
29148 /* 80604 */ /*GILLT_v8s16*//*Label 2489*/ GIMT_Encode4(80616), GIMT_Encode4(0),
29149 /* 80612 */ /*GILLT_v4s32*//*Label 2490*/ GIMT_Encode4(80693),
29150 /* 80616 */ // Label 2489: @80616
29151 /* 80616 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2492*/ GIMT_Encode4(80692), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4429 //
29152 /* 80623 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29153 /* 80626 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29154 /* 80629 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
29155 /* 80632 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
29156 /* 80635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29157 /* 80639 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
29158 /* 80643 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29159 /* 80647 */ // MIs[1] Operand 1
29160 /* 80647 */ // No operand predicates
29161 /* 80647 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29162 /* 80651 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29163 /* 80655 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29164 /* 80659 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
29165 /* 80661 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3828:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
29166 /* 80661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf16),
29167 /* 80664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29168 /* 80666 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src
29169 /* 80668 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29170 /* 80670 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29171 /* 80672 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29172 /* 80675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29173 /* 80678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29174 /* 80684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29175 /* 80690 */ GIR_RootConstrainSelectedInstOperands,
29176 /* 80691 */ // GIR_Coverage, 4429,
29177 /* 80691 */ GIR_EraseRootFromParent_Done,
29178 /* 80692 */ // Label 2492: @80692
29179 /* 80692 */ GIM_Reject,
29180 /* 80693 */ // Label 2490: @80693
29181 /* 80693 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2493*/ GIMT_Encode4(80769), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4432 //
29182 /* 80700 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29183 /* 80703 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29184 /* 80706 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
29185 /* 80709 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
29186 /* 80712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29187 /* 80716 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
29188 /* 80720 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29189 /* 80724 */ // MIs[1] Operand 1
29190 /* 80724 */ // No operand predicates
29191 /* 80724 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29192 /* 80728 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29193 /* 80732 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29194 /* 80736 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
29195 /* 80738 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3828:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
29196 /* 80738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf32),
29197 /* 80741 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29198 /* 80743 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src
29199 /* 80745 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
29200 /* 80747 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
29201 /* 80749 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
29202 /* 80752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29203 /* 80755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29204 /* 80761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29205 /* 80767 */ GIR_RootConstrainSelectedInstOperands,
29206 /* 80768 */ // GIR_Coverage, 4432,
29207 /* 80768 */ GIR_EraseRootFromParent_Done,
29208 /* 80769 */ // Label 2493: @80769
29209 /* 80769 */ GIM_Reject,
29210 /* 80770 */ // Label 2491: @80770
29211 /* 80770 */ GIM_Reject,
29212 /* 80771 */ // Label 2488: @80771
29213 /* 80771 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2494*/ GIMT_Encode4(80866), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3077 //
29214 /* 80778 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx2),
29215 /* 80783 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
29216 /* 80786 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
29217 /* 80789 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
29218 /* 80792 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
29219 /* 80795 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
29220 /* 80798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
29221 /* 80802 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4089:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vm) => (VTBX2:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v16i8] } DPair:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
29222 /* 80802 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
29223 /* 80805 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
29224 /* 80809 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29225 /* 80814 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
29226 /* 80818 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
29227 /* 80821 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
29228 /* 80825 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
29229 /* 80828 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
29230 /* 80833 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
29231 /* 80838 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
29232 /* 80843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX2),
29233 /* 80846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
29234 /* 80848 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
29235 /* 80850 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29236 /* 80853 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm
29237 /* 80855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
29238 /* 80858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29239 /* 80864 */ GIR_RootConstrainSelectedInstOperands,
29240 /* 80865 */ // GIR_Coverage, 3077,
29241 /* 80865 */ GIR_EraseRootFromParent_Done,
29242 /* 80866 */ // Label 2494: @80866
29243 /* 80866 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2495*/ GIMT_Encode4(80996), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3078 //
29244 /* 80873 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl3),
29245 /* 80878 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
29246 /* 80881 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
29247 /* 80884 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
29248 /* 80887 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
29249 /* 80890 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
29250 /* 80893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
29251 /* 80897 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4086:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBL3Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
29252 /* 80897 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
29253 /* 80900 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29254 /* 80904 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29255 /* 80909 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
29256 /* 80911 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
29257 /* 80914 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
29258 /* 80918 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29259 /* 80923 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
29260 /* 80927 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
29261 /* 80930 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
29262 /* 80934 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
29263 /* 80937 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
29264 /* 80941 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
29265 /* 80944 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
29266 /* 80947 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
29267 /* 80950 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
29268 /* 80955 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
29269 /* 80960 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
29270 /* 80965 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
29271 /* 80970 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
29272 /* 80975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL3Pseudo),
29273 /* 80978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
29274 /* 80980 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29275 /* 80983 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm
29276 /* 80985 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
29277 /* 80988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29278 /* 80994 */ GIR_RootConstrainSelectedInstOperands,
29279 /* 80995 */ // GIR_Coverage, 3078,
29280 /* 80995 */ GIR_EraseRootFromParent_Done,
29281 /* 80996 */ // Label 2495: @80996
29282 /* 80996 */ GIM_Reject,
29283 /* 80997 */ // Label 2411: @80997
29284 /* 80997 */ GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(84553),
29285 /* 81002 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
29286 /* 81005 */ GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(82523),
29287 /* 81010 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
29288 /* 81015 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2501*/ GIMT_Encode4(82522),
29289 /* 81026 */ /*GILLT_v16s8*//*Label 2498*/ GIMT_Encode4(81046), GIMT_Encode4(0),
29290 /* 81034 */ /*GILLT_v8s16*//*Label 2499*/ GIMT_Encode4(81538), GIMT_Encode4(0),
29291 /* 81042 */ /*GILLT_v4s32*//*Label 2500*/ GIMT_Encode4(82030),
29292 /* 81046 */ // Label 2498: @81046
29293 /* 81046 */ GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(81537),
29294 /* 81051 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29295 /* 81054 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29296 /* 81057 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29297 /* 81060 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29298 /* 81063 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29299 /* 81066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29300 /* 81070 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29301 /* 81074 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29302 /* 81078 */ GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(81192),
29303 /* 81083 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29304 /* 81087 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29305 /* 81091 */ GIM_Try, /*On fail goto*//*Label 2504*/ GIMT_Encode4(81141), // Rule ID 4241 //
29306 /* 81096 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29307 /* 81100 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3933:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29308 /* 81100 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29309 /* 81103 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29310 /* 81107 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29311 /* 81112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs8),
29312 /* 81115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29313 /* 81117 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29314 /* 81119 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29315 /* 81121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29316 /* 81124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29317 /* 81130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29318 /* 81136 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29319 /* 81139 */ GIR_RootConstrainSelectedInstOperands,
29320 /* 81140 */ // GIR_Coverage, 4241,
29321 /* 81140 */ GIR_EraseRootFromParent_Done,
29322 /* 81141 */ // Label 2504: @81141
29323 /* 81141 */ GIM_Try, /*On fail goto*//*Label 2505*/ GIMT_Encode4(81191), // Rule ID 4247 //
29324 /* 81146 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29325 /* 81150 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3933:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29326 /* 81150 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29327 /* 81153 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29328 /* 81157 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29329 /* 81162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu8),
29330 /* 81165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29331 /* 81167 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29332 /* 81169 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29333 /* 81171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29334 /* 81174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29335 /* 81180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29336 /* 81186 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29337 /* 81189 */ GIR_RootConstrainSelectedInstOperands,
29338 /* 81190 */ // GIR_Coverage, 4247,
29339 /* 81190 */ GIR_EraseRootFromParent_Done,
29340 /* 81191 */ // Label 2505: @81191
29341 /* 81191 */ GIM_Reject,
29342 /* 81192 */ // Label 2503: @81192
29343 /* 81192 */ GIM_Try, /*On fail goto*//*Label 2506*/ GIMT_Encode4(81422),
29344 /* 81197 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29345 /* 81201 */ GIM_Try, /*On fail goto*//*Label 2507*/ GIMT_Encode4(81311),
29346 /* 81206 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29347 /* 81210 */ GIM_Try, /*On fail goto*//*Label 2508*/ GIMT_Encode4(81260), // Rule ID 4253 //
29348 /* 81215 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29349 /* 81219 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3933:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29350 /* 81219 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29351 /* 81222 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29352 /* 81226 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29353 /* 81231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs8),
29354 /* 81234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29355 /* 81236 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29356 /* 81238 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29357 /* 81240 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29358 /* 81243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29359 /* 81249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29360 /* 81255 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29361 /* 81258 */ GIR_RootConstrainSelectedInstOperands,
29362 /* 81259 */ // GIR_Coverage, 4253,
29363 /* 81259 */ GIR_EraseRootFromParent_Done,
29364 /* 81260 */ // Label 2508: @81260
29365 /* 81260 */ GIM_Try, /*On fail goto*//*Label 2509*/ GIMT_Encode4(81310), // Rule ID 4259 //
29366 /* 81265 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29367 /* 81269 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3933:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29368 /* 81269 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29369 /* 81272 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29370 /* 81276 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29371 /* 81281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu8),
29372 /* 81284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29373 /* 81286 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29374 /* 81288 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29375 /* 81290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29376 /* 81293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29377 /* 81299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29378 /* 81305 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29379 /* 81308 */ GIR_RootConstrainSelectedInstOperands,
29380 /* 81309 */ // GIR_Coverage, 4259,
29381 /* 81309 */ GIR_EraseRootFromParent_Done,
29382 /* 81310 */ // Label 2509: @81310
29383 /* 81310 */ GIM_Reject,
29384 /* 81311 */ // Label 2507: @81311
29385 /* 81311 */ GIM_Try, /*On fail goto*//*Label 2510*/ GIMT_Encode4(81421),
29386 /* 81316 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29387 /* 81320 */ GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(81370), // Rule ID 4265 //
29388 /* 81325 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29389 /* 81329 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3933:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29390 /* 81329 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29391 /* 81332 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29392 /* 81336 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29393 /* 81341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs8),
29394 /* 81344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29395 /* 81346 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29396 /* 81348 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29397 /* 81350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29398 /* 81353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29399 /* 81359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29400 /* 81365 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29401 /* 81368 */ GIR_RootConstrainSelectedInstOperands,
29402 /* 81369 */ // GIR_Coverage, 4265,
29403 /* 81369 */ GIR_EraseRootFromParent_Done,
29404 /* 81370 */ // Label 2511: @81370
29405 /* 81370 */ GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(81420), // Rule ID 4271 //
29406 /* 81375 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29407 /* 81379 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3933:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29408 /* 81379 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29409 /* 81382 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29410 /* 81386 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29411 /* 81391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu8),
29412 /* 81394 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29413 /* 81396 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29414 /* 81398 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29415 /* 81400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29416 /* 81403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29417 /* 81409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29418 /* 81415 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29419 /* 81418 */ GIR_RootConstrainSelectedInstOperands,
29420 /* 81419 */ // GIR_Coverage, 4271,
29421 /* 81419 */ GIR_EraseRootFromParent_Done,
29422 /* 81420 */ // Label 2512: @81420
29423 /* 81420 */ GIM_Reject,
29424 /* 81421 */ // Label 2510: @81421
29425 /* 81421 */ GIM_Reject,
29426 /* 81422 */ // Label 2506: @81422
29427 /* 81422 */ GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(81536),
29428 /* 81427 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29429 /* 81431 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29430 /* 81435 */ GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(81485), // Rule ID 4277 //
29431 /* 81440 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29432 /* 81444 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3933:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29433 /* 81444 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29434 /* 81447 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29435 /* 81451 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29436 /* 81456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs8),
29437 /* 81459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29438 /* 81461 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29439 /* 81463 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29440 /* 81465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29441 /* 81468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29442 /* 81474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29443 /* 81480 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29444 /* 81483 */ GIR_RootConstrainSelectedInstOperands,
29445 /* 81484 */ // GIR_Coverage, 4277,
29446 /* 81484 */ GIR_EraseRootFromParent_Done,
29447 /* 81485 */ // Label 2514: @81485
29448 /* 81485 */ GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(81535), // Rule ID 4283 //
29449 /* 81490 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29450 /* 81494 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3933:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
29451 /* 81494 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29452 /* 81497 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29453 /* 81501 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29454 /* 81506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu8),
29455 /* 81509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29456 /* 81511 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29457 /* 81513 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29458 /* 81515 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29459 /* 81518 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29460 /* 81524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29461 /* 81530 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29462 /* 81533 */ GIR_RootConstrainSelectedInstOperands,
29463 /* 81534 */ // GIR_Coverage, 4283,
29464 /* 81534 */ GIR_EraseRootFromParent_Done,
29465 /* 81535 */ // Label 2515: @81535
29466 /* 81535 */ GIM_Reject,
29467 /* 81536 */ // Label 2513: @81536
29468 /* 81536 */ GIM_Reject,
29469 /* 81537 */ // Label 2502: @81537
29470 /* 81537 */ GIM_Reject,
29471 /* 81538 */ // Label 2499: @81538
29472 /* 81538 */ GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(82029),
29473 /* 81543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29474 /* 81546 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29475 /* 81549 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29476 /* 81552 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29477 /* 81555 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29478 /* 81558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29479 /* 81562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29480 /* 81566 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29481 /* 81570 */ GIM_Try, /*On fail goto*//*Label 2517*/ GIMT_Encode4(81684),
29482 /* 81575 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29483 /* 81579 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29484 /* 81583 */ GIM_Try, /*On fail goto*//*Label 2518*/ GIMT_Encode4(81633), // Rule ID 4243 //
29485 /* 81588 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29486 /* 81592 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3933:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29487 /* 81592 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29488 /* 81595 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29489 /* 81599 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29490 /* 81604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs16),
29491 /* 81607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29492 /* 81609 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29493 /* 81611 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29494 /* 81613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29495 /* 81616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29496 /* 81622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29497 /* 81628 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29498 /* 81631 */ GIR_RootConstrainSelectedInstOperands,
29499 /* 81632 */ // GIR_Coverage, 4243,
29500 /* 81632 */ GIR_EraseRootFromParent_Done,
29501 /* 81633 */ // Label 2518: @81633
29502 /* 81633 */ GIM_Try, /*On fail goto*//*Label 2519*/ GIMT_Encode4(81683), // Rule ID 4249 //
29503 /* 81638 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29504 /* 81642 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3933:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29505 /* 81642 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29506 /* 81645 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29507 /* 81649 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29508 /* 81654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu16),
29509 /* 81657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29510 /* 81659 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29511 /* 81661 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29512 /* 81663 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29513 /* 81666 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29514 /* 81672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29515 /* 81678 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29516 /* 81681 */ GIR_RootConstrainSelectedInstOperands,
29517 /* 81682 */ // GIR_Coverage, 4249,
29518 /* 81682 */ GIR_EraseRootFromParent_Done,
29519 /* 81683 */ // Label 2519: @81683
29520 /* 81683 */ GIM_Reject,
29521 /* 81684 */ // Label 2517: @81684
29522 /* 81684 */ GIM_Try, /*On fail goto*//*Label 2520*/ GIMT_Encode4(81914),
29523 /* 81689 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29524 /* 81693 */ GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(81803),
29525 /* 81698 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29526 /* 81702 */ GIM_Try, /*On fail goto*//*Label 2522*/ GIMT_Encode4(81752), // Rule ID 4255 //
29527 /* 81707 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29528 /* 81711 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3933:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29529 /* 81711 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29530 /* 81714 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29531 /* 81718 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29532 /* 81723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs16),
29533 /* 81726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29534 /* 81728 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29535 /* 81730 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29536 /* 81732 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29537 /* 81735 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29538 /* 81741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29539 /* 81747 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29540 /* 81750 */ GIR_RootConstrainSelectedInstOperands,
29541 /* 81751 */ // GIR_Coverage, 4255,
29542 /* 81751 */ GIR_EraseRootFromParent_Done,
29543 /* 81752 */ // Label 2522: @81752
29544 /* 81752 */ GIM_Try, /*On fail goto*//*Label 2523*/ GIMT_Encode4(81802), // Rule ID 4261 //
29545 /* 81757 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29546 /* 81761 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3933:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29547 /* 81761 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29548 /* 81764 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29549 /* 81768 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29550 /* 81773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu16),
29551 /* 81776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29552 /* 81778 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29553 /* 81780 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29554 /* 81782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29555 /* 81785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29556 /* 81791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29557 /* 81797 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29558 /* 81800 */ GIR_RootConstrainSelectedInstOperands,
29559 /* 81801 */ // GIR_Coverage, 4261,
29560 /* 81801 */ GIR_EraseRootFromParent_Done,
29561 /* 81802 */ // Label 2523: @81802
29562 /* 81802 */ GIM_Reject,
29563 /* 81803 */ // Label 2521: @81803
29564 /* 81803 */ GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(81913),
29565 /* 81808 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29566 /* 81812 */ GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(81862), // Rule ID 4267 //
29567 /* 81817 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29568 /* 81821 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3933:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29569 /* 81821 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29570 /* 81824 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29571 /* 81828 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29572 /* 81833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs16),
29573 /* 81836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29574 /* 81838 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29575 /* 81840 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29576 /* 81842 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29577 /* 81845 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29578 /* 81851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29579 /* 81857 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29580 /* 81860 */ GIR_RootConstrainSelectedInstOperands,
29581 /* 81861 */ // GIR_Coverage, 4267,
29582 /* 81861 */ GIR_EraseRootFromParent_Done,
29583 /* 81862 */ // Label 2525: @81862
29584 /* 81862 */ GIM_Try, /*On fail goto*//*Label 2526*/ GIMT_Encode4(81912), // Rule ID 4273 //
29585 /* 81867 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29586 /* 81871 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3933:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29587 /* 81871 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29588 /* 81874 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29589 /* 81878 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29590 /* 81883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu16),
29591 /* 81886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29592 /* 81888 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29593 /* 81890 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29594 /* 81892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29595 /* 81895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29596 /* 81901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29597 /* 81907 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29598 /* 81910 */ GIR_RootConstrainSelectedInstOperands,
29599 /* 81911 */ // GIR_Coverage, 4273,
29600 /* 81911 */ GIR_EraseRootFromParent_Done,
29601 /* 81912 */ // Label 2526: @81912
29602 /* 81912 */ GIM_Reject,
29603 /* 81913 */ // Label 2524: @81913
29604 /* 81913 */ GIM_Reject,
29605 /* 81914 */ // Label 2520: @81914
29606 /* 81914 */ GIM_Try, /*On fail goto*//*Label 2527*/ GIMT_Encode4(82028),
29607 /* 81919 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29608 /* 81923 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29609 /* 81927 */ GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(81977), // Rule ID 4279 //
29610 /* 81932 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29611 /* 81936 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3933:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29612 /* 81936 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29613 /* 81939 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29614 /* 81943 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29615 /* 81948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs16),
29616 /* 81951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29617 /* 81953 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29618 /* 81955 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29619 /* 81957 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29620 /* 81960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29621 /* 81966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29622 /* 81972 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29623 /* 81975 */ GIR_RootConstrainSelectedInstOperands,
29624 /* 81976 */ // GIR_Coverage, 4279,
29625 /* 81976 */ GIR_EraseRootFromParent_Done,
29626 /* 81977 */ // Label 2528: @81977
29627 /* 81977 */ GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(82027), // Rule ID 4285 //
29628 /* 81982 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29629 /* 81986 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3933:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
29630 /* 81986 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29631 /* 81989 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29632 /* 81993 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29633 /* 81998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu16),
29634 /* 82001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29635 /* 82003 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29636 /* 82005 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29637 /* 82007 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29638 /* 82010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29639 /* 82016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29640 /* 82022 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29641 /* 82025 */ GIR_RootConstrainSelectedInstOperands,
29642 /* 82026 */ // GIR_Coverage, 4285,
29643 /* 82026 */ GIR_EraseRootFromParent_Done,
29644 /* 82027 */ // Label 2529: @82027
29645 /* 82027 */ GIM_Reject,
29646 /* 82028 */ // Label 2527: @82028
29647 /* 82028 */ GIM_Reject,
29648 /* 82029 */ // Label 2516: @82029
29649 /* 82029 */ GIM_Reject,
29650 /* 82030 */ // Label 2500: @82030
29651 /* 82030 */ GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(82521),
29652 /* 82035 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29653 /* 82038 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29654 /* 82041 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29655 /* 82044 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29656 /* 82047 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29657 /* 82050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29658 /* 82054 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29659 /* 82058 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29660 /* 82062 */ GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(82176),
29661 /* 82067 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29662 /* 82071 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29663 /* 82075 */ GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(82125), // Rule ID 4245 //
29664 /* 82080 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29665 /* 82084 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3933:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29666 /* 82084 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29667 /* 82087 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29668 /* 82091 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29669 /* 82096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs32),
29670 /* 82099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29671 /* 82101 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29672 /* 82103 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29673 /* 82105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29674 /* 82108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29675 /* 82114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29676 /* 82120 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29677 /* 82123 */ GIR_RootConstrainSelectedInstOperands,
29678 /* 82124 */ // GIR_Coverage, 4245,
29679 /* 82124 */ GIR_EraseRootFromParent_Done,
29680 /* 82125 */ // Label 2532: @82125
29681 /* 82125 */ GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(82175), // Rule ID 4251 //
29682 /* 82130 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29683 /* 82134 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3933:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29684 /* 82134 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29685 /* 82137 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29686 /* 82141 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29687 /* 82146 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu32),
29688 /* 82149 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29689 /* 82151 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29690 /* 82153 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29691 /* 82155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29692 /* 82158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29693 /* 82164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29694 /* 82170 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29695 /* 82173 */ GIR_RootConstrainSelectedInstOperands,
29696 /* 82174 */ // GIR_Coverage, 4251,
29697 /* 82174 */ GIR_EraseRootFromParent_Done,
29698 /* 82175 */ // Label 2533: @82175
29699 /* 82175 */ GIM_Reject,
29700 /* 82176 */ // Label 2531: @82176
29701 /* 82176 */ GIM_Try, /*On fail goto*//*Label 2534*/ GIMT_Encode4(82406),
29702 /* 82181 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29703 /* 82185 */ GIM_Try, /*On fail goto*//*Label 2535*/ GIMT_Encode4(82295),
29704 /* 82190 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29705 /* 82194 */ GIM_Try, /*On fail goto*//*Label 2536*/ GIMT_Encode4(82244), // Rule ID 4257 //
29706 /* 82199 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29707 /* 82203 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3933:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29708 /* 82203 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29709 /* 82206 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29710 /* 82210 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29711 /* 82215 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs32),
29712 /* 82218 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29713 /* 82220 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29714 /* 82222 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29715 /* 82224 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29716 /* 82227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29717 /* 82233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29718 /* 82239 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29719 /* 82242 */ GIR_RootConstrainSelectedInstOperands,
29720 /* 82243 */ // GIR_Coverage, 4257,
29721 /* 82243 */ GIR_EraseRootFromParent_Done,
29722 /* 82244 */ // Label 2536: @82244
29723 /* 82244 */ GIM_Try, /*On fail goto*//*Label 2537*/ GIMT_Encode4(82294), // Rule ID 4263 //
29724 /* 82249 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29725 /* 82253 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3933:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29726 /* 82253 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29727 /* 82256 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29728 /* 82260 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29729 /* 82265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu32),
29730 /* 82268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29731 /* 82270 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29732 /* 82272 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29733 /* 82274 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29734 /* 82277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29735 /* 82283 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29736 /* 82289 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29737 /* 82292 */ GIR_RootConstrainSelectedInstOperands,
29738 /* 82293 */ // GIR_Coverage, 4263,
29739 /* 82293 */ GIR_EraseRootFromParent_Done,
29740 /* 82294 */ // Label 2537: @82294
29741 /* 82294 */ GIM_Reject,
29742 /* 82295 */ // Label 2535: @82295
29743 /* 82295 */ GIM_Try, /*On fail goto*//*Label 2538*/ GIMT_Encode4(82405),
29744 /* 82300 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29745 /* 82304 */ GIM_Try, /*On fail goto*//*Label 2539*/ GIMT_Encode4(82354), // Rule ID 4269 //
29746 /* 82309 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29747 /* 82313 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3933:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29748 /* 82313 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29749 /* 82316 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29750 /* 82320 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29751 /* 82325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs32),
29752 /* 82328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29753 /* 82330 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29754 /* 82332 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29755 /* 82334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29756 /* 82337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29757 /* 82343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29758 /* 82349 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29759 /* 82352 */ GIR_RootConstrainSelectedInstOperands,
29760 /* 82353 */ // GIR_Coverage, 4269,
29761 /* 82353 */ GIR_EraseRootFromParent_Done,
29762 /* 82354 */ // Label 2539: @82354
29763 /* 82354 */ GIM_Try, /*On fail goto*//*Label 2540*/ GIMT_Encode4(82404), // Rule ID 4275 //
29764 /* 82359 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29765 /* 82363 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3933:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29766 /* 82363 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29767 /* 82366 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29768 /* 82370 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29769 /* 82375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu32),
29770 /* 82378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29771 /* 82380 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29772 /* 82382 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29773 /* 82384 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29774 /* 82387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29775 /* 82393 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29776 /* 82399 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29777 /* 82402 */ GIR_RootConstrainSelectedInstOperands,
29778 /* 82403 */ // GIR_Coverage, 4275,
29779 /* 82403 */ GIR_EraseRootFromParent_Done,
29780 /* 82404 */ // Label 2540: @82404
29781 /* 82404 */ GIM_Reject,
29782 /* 82405 */ // Label 2538: @82405
29783 /* 82405 */ GIM_Reject,
29784 /* 82406 */ // Label 2534: @82406
29785 /* 82406 */ GIM_Try, /*On fail goto*//*Label 2541*/ GIMT_Encode4(82520),
29786 /* 82411 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29787 /* 82415 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29788 /* 82419 */ GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(82469), // Rule ID 4281 //
29789 /* 82424 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29790 /* 82428 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3933:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29791 /* 82428 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29792 /* 82431 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29793 /* 82435 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29794 /* 82440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs32),
29795 /* 82443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29796 /* 82445 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29797 /* 82447 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29798 /* 82449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29799 /* 82452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29800 /* 82458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29801 /* 82464 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29802 /* 82467 */ GIR_RootConstrainSelectedInstOperands,
29803 /* 82468 */ // GIR_Coverage, 4281,
29804 /* 82468 */ GIR_EraseRootFromParent_Done,
29805 /* 82469 */ // Label 2542: @82469
29806 /* 82469 */ GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(82519), // Rule ID 4287 //
29807 /* 82474 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29808 /* 82478 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3933:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
29809 /* 82478 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29810 /* 82481 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29811 /* 82485 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29812 /* 82490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu32),
29813 /* 82493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29814 /* 82495 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
29815 /* 82497 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
29816 /* 82499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29817 /* 82502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29818 /* 82508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29819 /* 82514 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29820 /* 82517 */ GIR_RootConstrainSelectedInstOperands,
29821 /* 82518 */ // GIR_Coverage, 4287,
29822 /* 82518 */ GIR_EraseRootFromParent_Done,
29823 /* 82519 */ // Label 2543: @82519
29824 /* 82519 */ GIM_Reject,
29825 /* 82520 */ // Label 2541: @82520
29826 /* 82520 */ GIM_Reject,
29827 /* 82521 */ // Label 2530: @82521
29828 /* 82521 */ GIM_Reject,
29829 /* 82522 */ // Label 2501: @82522
29830 /* 82522 */ GIM_Reject,
29831 /* 82523 */ // Label 2497: @82523
29832 /* 82523 */ GIM_Try, /*On fail goto*//*Label 2544*/ GIMT_Encode4(83133),
29833 /* 82528 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
29834 /* 82533 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 2547*/ GIMT_Encode4(83132),
29835 /* 82544 */ /*GILLT_v16s8*//*Label 2545*/ GIMT_Encode4(82556), GIMT_Encode4(0),
29836 /* 82552 */ /*GILLT_v8s16*//*Label 2546*/ GIMT_Encode4(82844),
29837 /* 82556 */ // Label 2545: @82556
29838 /* 82556 */ GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(82843),
29839 /* 82561 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29840 /* 82564 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29841 /* 82567 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29842 /* 82570 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29843 /* 82573 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29844 /* 82576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29845 /* 82580 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29846 /* 82584 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29847 /* 82588 */ GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(82672),
29848 /* 82593 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29849 /* 82597 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29850 /* 82601 */ GIM_Try, /*On fail goto*//*Label 2550*/ GIMT_Encode4(82636), // Rule ID 5004 //
29851 /* 82606 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29852 /* 82610 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3898:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29853 /* 82610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16bh),
29854 /* 82613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29855 /* 82615 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
29856 /* 82617 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
29857 /* 82619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29858 /* 82622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29859 /* 82628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29860 /* 82634 */ GIR_RootConstrainSelectedInstOperands,
29861 /* 82635 */ // GIR_Coverage, 5004,
29862 /* 82635 */ GIR_EraseRootFromParent_Done,
29863 /* 82636 */ // Label 2550: @82636
29864 /* 82636 */ GIM_Try, /*On fail goto*//*Label 2551*/ GIMT_Encode4(82671), // Rule ID 5006 //
29865 /* 82641 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29866 /* 82645 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3898:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29867 /* 82645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16th),
29868 /* 82648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29869 /* 82650 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
29870 /* 82652 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
29871 /* 82654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29872 /* 82657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29873 /* 82663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29874 /* 82669 */ GIR_RootConstrainSelectedInstOperands,
29875 /* 82670 */ // GIR_Coverage, 5006,
29876 /* 82670 */ GIR_EraseRootFromParent_Done,
29877 /* 82671 */ // Label 2551: @82671
29878 /* 82671 */ GIM_Reject,
29879 /* 82672 */ // Label 2549: @82672
29880 /* 82672 */ GIM_Try, /*On fail goto*//*Label 2552*/ GIMT_Encode4(82842),
29881 /* 82677 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29882 /* 82681 */ GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(82761),
29883 /* 82686 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29884 /* 82690 */ GIM_Try, /*On fail goto*//*Label 2554*/ GIMT_Encode4(82725), // Rule ID 5012 //
29885 /* 82695 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29886 /* 82699 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3898:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29887 /* 82699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16bh),
29888 /* 82702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29889 /* 82704 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
29890 /* 82706 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
29891 /* 82708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29892 /* 82711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29893 /* 82717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29894 /* 82723 */ GIR_RootConstrainSelectedInstOperands,
29895 /* 82724 */ // GIR_Coverage, 5012,
29896 /* 82724 */ GIR_EraseRootFromParent_Done,
29897 /* 82725 */ // Label 2554: @82725
29898 /* 82725 */ GIM_Try, /*On fail goto*//*Label 2555*/ GIMT_Encode4(82760), // Rule ID 5014 //
29899 /* 82730 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29900 /* 82734 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3898:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29901 /* 82734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16th),
29902 /* 82737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29903 /* 82739 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
29904 /* 82741 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
29905 /* 82743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29906 /* 82746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29907 /* 82752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29908 /* 82758 */ GIR_RootConstrainSelectedInstOperands,
29909 /* 82759 */ // GIR_Coverage, 5014,
29910 /* 82759 */ GIR_EraseRootFromParent_Done,
29911 /* 82760 */ // Label 2555: @82760
29912 /* 82760 */ GIM_Reject,
29913 /* 82761 */ // Label 2553: @82761
29914 /* 82761 */ GIM_Try, /*On fail goto*//*Label 2556*/ GIMT_Encode4(82841),
29915 /* 82766 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29916 /* 82770 */ GIM_Try, /*On fail goto*//*Label 2557*/ GIMT_Encode4(82805), // Rule ID 5020 //
29917 /* 82775 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29918 /* 82779 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3898:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29919 /* 82779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16bh),
29920 /* 82782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29921 /* 82784 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
29922 /* 82786 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
29923 /* 82788 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29924 /* 82791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29925 /* 82797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29926 /* 82803 */ GIR_RootConstrainSelectedInstOperands,
29927 /* 82804 */ // GIR_Coverage, 5020,
29928 /* 82804 */ GIR_EraseRootFromParent_Done,
29929 /* 82805 */ // Label 2557: @82805
29930 /* 82805 */ GIM_Try, /*On fail goto*//*Label 2558*/ GIMT_Encode4(82840), // Rule ID 5022 //
29931 /* 82810 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29932 /* 82814 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3898:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
29933 /* 82814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16th),
29934 /* 82817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29935 /* 82819 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
29936 /* 82821 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
29937 /* 82823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29938 /* 82826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29939 /* 82832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29940 /* 82838 */ GIR_RootConstrainSelectedInstOperands,
29941 /* 82839 */ // GIR_Coverage, 5022,
29942 /* 82839 */ GIR_EraseRootFromParent_Done,
29943 /* 82840 */ // Label 2558: @82840
29944 /* 82840 */ GIM_Reject,
29945 /* 82841 */ // Label 2556: @82841
29946 /* 82841 */ GIM_Reject,
29947 /* 82842 */ // Label 2552: @82842
29948 /* 82842 */ GIM_Reject,
29949 /* 82843 */ // Label 2548: @82843
29950 /* 82843 */ GIM_Reject,
29951 /* 82844 */ // Label 2546: @82844
29952 /* 82844 */ GIM_Try, /*On fail goto*//*Label 2559*/ GIMT_Encode4(83131),
29953 /* 82849 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29954 /* 82852 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29955 /* 82855 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29956 /* 82858 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29957 /* 82861 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
29958 /* 82864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29959 /* 82868 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29960 /* 82872 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29961 /* 82876 */ GIM_Try, /*On fail goto*//*Label 2560*/ GIMT_Encode4(82960),
29962 /* 82881 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29963 /* 82885 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29964 /* 82889 */ GIM_Try, /*On fail goto*//*Label 2561*/ GIMT_Encode4(82924), // Rule ID 5000 //
29965 /* 82894 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
29966 /* 82898 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3898:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
29967 /* 82898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32bh),
29968 /* 82901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29969 /* 82903 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
29970 /* 82905 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
29971 /* 82907 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29972 /* 82910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29973 /* 82916 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29974 /* 82922 */ GIR_RootConstrainSelectedInstOperands,
29975 /* 82923 */ // GIR_Coverage, 5000,
29976 /* 82923 */ GIR_EraseRootFromParent_Done,
29977 /* 82924 */ // Label 2561: @82924
29978 /* 82924 */ GIM_Try, /*On fail goto*//*Label 2562*/ GIMT_Encode4(82959), // Rule ID 5002 //
29979 /* 82929 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
29980 /* 82933 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3898:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
29981 /* 82933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32th),
29982 /* 82936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29983 /* 82938 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
29984 /* 82940 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
29985 /* 82942 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29986 /* 82945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29987 /* 82951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29988 /* 82957 */ GIR_RootConstrainSelectedInstOperands,
29989 /* 82958 */ // GIR_Coverage, 5002,
29990 /* 82958 */ GIR_EraseRootFromParent_Done,
29991 /* 82959 */ // Label 2562: @82959
29992 /* 82959 */ GIM_Reject,
29993 /* 82960 */ // Label 2560: @82960
29994 /* 82960 */ GIM_Try, /*On fail goto*//*Label 2563*/ GIMT_Encode4(83130),
29995 /* 82965 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29996 /* 82969 */ GIM_Try, /*On fail goto*//*Label 2564*/ GIMT_Encode4(83049),
29997 /* 82974 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29998 /* 82978 */ GIM_Try, /*On fail goto*//*Label 2565*/ GIMT_Encode4(83013), // Rule ID 5008 //
29999 /* 82983 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30000 /* 82987 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3898:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30001 /* 82987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32bh),
30002 /* 82990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30003 /* 82992 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
30004 /* 82994 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
30005 /* 82996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30006 /* 82999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30007 /* 83005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30008 /* 83011 */ GIR_RootConstrainSelectedInstOperands,
30009 /* 83012 */ // GIR_Coverage, 5008,
30010 /* 83012 */ GIR_EraseRootFromParent_Done,
30011 /* 83013 */ // Label 2565: @83013
30012 /* 83013 */ GIM_Try, /*On fail goto*//*Label 2566*/ GIMT_Encode4(83048), // Rule ID 5010 //
30013 /* 83018 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30014 /* 83022 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3898:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30015 /* 83022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32th),
30016 /* 83025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30017 /* 83027 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
30018 /* 83029 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
30019 /* 83031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30020 /* 83034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30021 /* 83040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30022 /* 83046 */ GIR_RootConstrainSelectedInstOperands,
30023 /* 83047 */ // GIR_Coverage, 5010,
30024 /* 83047 */ GIR_EraseRootFromParent_Done,
30025 /* 83048 */ // Label 2566: @83048
30026 /* 83048 */ GIM_Reject,
30027 /* 83049 */ // Label 2564: @83049
30028 /* 83049 */ GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(83129),
30029 /* 83054 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30030 /* 83058 */ GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(83093), // Rule ID 5016 //
30031 /* 83063 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30032 /* 83067 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3898:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30033 /* 83067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32bh),
30034 /* 83070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30035 /* 83072 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
30036 /* 83074 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
30037 /* 83076 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30038 /* 83079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30039 /* 83085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30040 /* 83091 */ GIR_RootConstrainSelectedInstOperands,
30041 /* 83092 */ // GIR_Coverage, 5016,
30042 /* 83092 */ GIR_EraseRootFromParent_Done,
30043 /* 83093 */ // Label 2568: @83093
30044 /* 83093 */ GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(83128), // Rule ID 5018 //
30045 /* 83098 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30046 /* 83102 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3898:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
30047 /* 83102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32th),
30048 /* 83105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30049 /* 83107 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
30050 /* 83109 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
30051 /* 83111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30052 /* 83114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30053 /* 83120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30054 /* 83126 */ GIR_RootConstrainSelectedInstOperands,
30055 /* 83127 */ // GIR_Coverage, 5018,
30056 /* 83127 */ GIR_EraseRootFromParent_Done,
30057 /* 83128 */ // Label 2569: @83128
30058 /* 83128 */ GIM_Reject,
30059 /* 83129 */ // Label 2567: @83129
30060 /* 83129 */ GIM_Reject,
30061 /* 83130 */ // Label 2563: @83130
30062 /* 83130 */ GIM_Reject,
30063 /* 83131 */ // Label 2559: @83131
30064 /* 83131 */ GIM_Reject,
30065 /* 83132 */ // Label 2547: @83132
30066 /* 83132 */ GIM_Reject,
30067 /* 83133 */ // Label 2544: @83133
30068 /* 83133 */ GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(84297),
30069 /* 83138 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
30070 /* 83143 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2574*/ GIMT_Encode4(84296),
30071 /* 83154 */ /*GILLT_v16s8*//*Label 2571*/ GIMT_Encode4(83174), GIMT_Encode4(0),
30072 /* 83162 */ /*GILLT_v8s16*//*Label 2572*/ GIMT_Encode4(83548), GIMT_Encode4(0),
30073 /* 83170 */ /*GILLT_v4s32*//*Label 2573*/ GIMT_Encode4(83922),
30074 /* 83174 */ // Label 2571: @83174
30075 /* 83174 */ GIM_Try, /*On fail goto*//*Label 2575*/ GIMT_Encode4(83547),
30076 /* 83179 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30077 /* 83182 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30078 /* 83185 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30079 /* 83188 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30080 /* 83191 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30081 /* 83194 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30082 /* 83198 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30083 /* 83202 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30084 /* 83206 */ GIM_Try, /*On fail goto*//*Label 2576*/ GIMT_Encode4(83376),
30085 /* 83211 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30086 /* 83215 */ GIM_Try, /*On fail goto*//*Label 2577*/ GIMT_Encode4(83295),
30087 /* 83220 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30088 /* 83224 */ GIM_Try, /*On fail goto*//*Label 2578*/ GIMT_Encode4(83259), // Rule ID 5224 //
30089 /* 83229 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30090 /* 83233 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3931:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30091 /* 83233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs8),
30092 /* 83236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30093 /* 83238 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30094 /* 83240 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30095 /* 83242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30096 /* 83245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30097 /* 83251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30098 /* 83257 */ GIR_RootConstrainSelectedInstOperands,
30099 /* 83258 */ // GIR_Coverage, 5224,
30100 /* 83258 */ GIR_EraseRootFromParent_Done,
30101 /* 83259 */ // Label 2578: @83259
30102 /* 83259 */ GIM_Try, /*On fail goto*//*Label 2579*/ GIMT_Encode4(83294), // Rule ID 5230 //
30103 /* 83264 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30104 /* 83268 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3931:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30105 /* 83268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru8),
30106 /* 83271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30107 /* 83273 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30108 /* 83275 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30109 /* 83277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30110 /* 83280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30111 /* 83286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30112 /* 83292 */ GIR_RootConstrainSelectedInstOperands,
30113 /* 83293 */ // GIR_Coverage, 5230,
30114 /* 83293 */ GIR_EraseRootFromParent_Done,
30115 /* 83294 */ // Label 2579: @83294
30116 /* 83294 */ GIM_Reject,
30117 /* 83295 */ // Label 2577: @83295
30118 /* 83295 */ GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(83375),
30119 /* 83300 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30120 /* 83304 */ GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(83339), // Rule ID 5236 //
30121 /* 83309 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30122 /* 83313 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3931:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30123 /* 83313 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs8),
30124 /* 83316 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30125 /* 83318 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30126 /* 83320 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30127 /* 83322 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30128 /* 83325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30129 /* 83331 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30130 /* 83337 */ GIR_RootConstrainSelectedInstOperands,
30131 /* 83338 */ // GIR_Coverage, 5236,
30132 /* 83338 */ GIR_EraseRootFromParent_Done,
30133 /* 83339 */ // Label 2581: @83339
30134 /* 83339 */ GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(83374), // Rule ID 5242 //
30135 /* 83344 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30136 /* 83348 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3931:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30137 /* 83348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru8),
30138 /* 83351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30139 /* 83353 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30140 /* 83355 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30141 /* 83357 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30142 /* 83360 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30143 /* 83366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30144 /* 83372 */ GIR_RootConstrainSelectedInstOperands,
30145 /* 83373 */ // GIR_Coverage, 5242,
30146 /* 83373 */ GIR_EraseRootFromParent_Done,
30147 /* 83374 */ // Label 2582: @83374
30148 /* 83374 */ GIM_Reject,
30149 /* 83375 */ // Label 2580: @83375
30150 /* 83375 */ GIM_Reject,
30151 /* 83376 */ // Label 2576: @83376
30152 /* 83376 */ GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(83546),
30153 /* 83381 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30154 /* 83385 */ GIM_Try, /*On fail goto*//*Label 2584*/ GIMT_Encode4(83465),
30155 /* 83390 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30156 /* 83394 */ GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(83429), // Rule ID 5248 //
30157 /* 83399 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30158 /* 83403 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3931:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30159 /* 83403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs8),
30160 /* 83406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30161 /* 83408 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30162 /* 83410 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30163 /* 83412 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30164 /* 83415 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30165 /* 83421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30166 /* 83427 */ GIR_RootConstrainSelectedInstOperands,
30167 /* 83428 */ // GIR_Coverage, 5248,
30168 /* 83428 */ GIR_EraseRootFromParent_Done,
30169 /* 83429 */ // Label 2585: @83429
30170 /* 83429 */ GIM_Try, /*On fail goto*//*Label 2586*/ GIMT_Encode4(83464), // Rule ID 5254 //
30171 /* 83434 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30172 /* 83438 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3931:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30173 /* 83438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru8),
30174 /* 83441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30175 /* 83443 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30176 /* 83445 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30177 /* 83447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30178 /* 83450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30179 /* 83456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30180 /* 83462 */ GIR_RootConstrainSelectedInstOperands,
30181 /* 83463 */ // GIR_Coverage, 5254,
30182 /* 83463 */ GIR_EraseRootFromParent_Done,
30183 /* 83464 */ // Label 2586: @83464
30184 /* 83464 */ GIM_Reject,
30185 /* 83465 */ // Label 2584: @83465
30186 /* 83465 */ GIM_Try, /*On fail goto*//*Label 2587*/ GIMT_Encode4(83545),
30187 /* 83470 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30188 /* 83474 */ GIM_Try, /*On fail goto*//*Label 2588*/ GIMT_Encode4(83509), // Rule ID 5260 //
30189 /* 83479 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30190 /* 83483 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3931:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30191 /* 83483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs8),
30192 /* 83486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30193 /* 83488 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30194 /* 83490 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30195 /* 83492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30196 /* 83495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30197 /* 83501 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30198 /* 83507 */ GIR_RootConstrainSelectedInstOperands,
30199 /* 83508 */ // GIR_Coverage, 5260,
30200 /* 83508 */ GIR_EraseRootFromParent_Done,
30201 /* 83509 */ // Label 2588: @83509
30202 /* 83509 */ GIM_Try, /*On fail goto*//*Label 2589*/ GIMT_Encode4(83544), // Rule ID 5266 //
30203 /* 83514 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30204 /* 83518 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3931:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
30205 /* 83518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru8),
30206 /* 83521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30207 /* 83523 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30208 /* 83525 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30209 /* 83527 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30210 /* 83530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30211 /* 83536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30212 /* 83542 */ GIR_RootConstrainSelectedInstOperands,
30213 /* 83543 */ // GIR_Coverage, 5266,
30214 /* 83543 */ GIR_EraseRootFromParent_Done,
30215 /* 83544 */ // Label 2589: @83544
30216 /* 83544 */ GIM_Reject,
30217 /* 83545 */ // Label 2587: @83545
30218 /* 83545 */ GIM_Reject,
30219 /* 83546 */ // Label 2583: @83546
30220 /* 83546 */ GIM_Reject,
30221 /* 83547 */ // Label 2575: @83547
30222 /* 83547 */ GIM_Reject,
30223 /* 83548 */ // Label 2572: @83548
30224 /* 83548 */ GIM_Try, /*On fail goto*//*Label 2590*/ GIMT_Encode4(83921),
30225 /* 83553 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30226 /* 83556 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30227 /* 83559 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30228 /* 83562 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30229 /* 83565 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30230 /* 83568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30231 /* 83572 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30232 /* 83576 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30233 /* 83580 */ GIM_Try, /*On fail goto*//*Label 2591*/ GIMT_Encode4(83750),
30234 /* 83585 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30235 /* 83589 */ GIM_Try, /*On fail goto*//*Label 2592*/ GIMT_Encode4(83669),
30236 /* 83594 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30237 /* 83598 */ GIM_Try, /*On fail goto*//*Label 2593*/ GIMT_Encode4(83633), // Rule ID 5226 //
30238 /* 83603 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30239 /* 83607 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3931:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30240 /* 83607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs16),
30241 /* 83610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30242 /* 83612 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30243 /* 83614 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30244 /* 83616 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30245 /* 83619 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30246 /* 83625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30247 /* 83631 */ GIR_RootConstrainSelectedInstOperands,
30248 /* 83632 */ // GIR_Coverage, 5226,
30249 /* 83632 */ GIR_EraseRootFromParent_Done,
30250 /* 83633 */ // Label 2593: @83633
30251 /* 83633 */ GIM_Try, /*On fail goto*//*Label 2594*/ GIMT_Encode4(83668), // Rule ID 5232 //
30252 /* 83638 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30253 /* 83642 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3931:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30254 /* 83642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru16),
30255 /* 83645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30256 /* 83647 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30257 /* 83649 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30258 /* 83651 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30259 /* 83654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30260 /* 83660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30261 /* 83666 */ GIR_RootConstrainSelectedInstOperands,
30262 /* 83667 */ // GIR_Coverage, 5232,
30263 /* 83667 */ GIR_EraseRootFromParent_Done,
30264 /* 83668 */ // Label 2594: @83668
30265 /* 83668 */ GIM_Reject,
30266 /* 83669 */ // Label 2592: @83669
30267 /* 83669 */ GIM_Try, /*On fail goto*//*Label 2595*/ GIMT_Encode4(83749),
30268 /* 83674 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30269 /* 83678 */ GIM_Try, /*On fail goto*//*Label 2596*/ GIMT_Encode4(83713), // Rule ID 5238 //
30270 /* 83683 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30271 /* 83687 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3931:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30272 /* 83687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs16),
30273 /* 83690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30274 /* 83692 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30275 /* 83694 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30276 /* 83696 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30277 /* 83699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30278 /* 83705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30279 /* 83711 */ GIR_RootConstrainSelectedInstOperands,
30280 /* 83712 */ // GIR_Coverage, 5238,
30281 /* 83712 */ GIR_EraseRootFromParent_Done,
30282 /* 83713 */ // Label 2596: @83713
30283 /* 83713 */ GIM_Try, /*On fail goto*//*Label 2597*/ GIMT_Encode4(83748), // Rule ID 5244 //
30284 /* 83718 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30285 /* 83722 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3931:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30286 /* 83722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru16),
30287 /* 83725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30288 /* 83727 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30289 /* 83729 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30290 /* 83731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30291 /* 83734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30292 /* 83740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30293 /* 83746 */ GIR_RootConstrainSelectedInstOperands,
30294 /* 83747 */ // GIR_Coverage, 5244,
30295 /* 83747 */ GIR_EraseRootFromParent_Done,
30296 /* 83748 */ // Label 2597: @83748
30297 /* 83748 */ GIM_Reject,
30298 /* 83749 */ // Label 2595: @83749
30299 /* 83749 */ GIM_Reject,
30300 /* 83750 */ // Label 2591: @83750
30301 /* 83750 */ GIM_Try, /*On fail goto*//*Label 2598*/ GIMT_Encode4(83920),
30302 /* 83755 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30303 /* 83759 */ GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(83839),
30304 /* 83764 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30305 /* 83768 */ GIM_Try, /*On fail goto*//*Label 2600*/ GIMT_Encode4(83803), // Rule ID 5250 //
30306 /* 83773 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30307 /* 83777 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3931:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30308 /* 83777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs16),
30309 /* 83780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30310 /* 83782 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30311 /* 83784 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30312 /* 83786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30313 /* 83789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30314 /* 83795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30315 /* 83801 */ GIR_RootConstrainSelectedInstOperands,
30316 /* 83802 */ // GIR_Coverage, 5250,
30317 /* 83802 */ GIR_EraseRootFromParent_Done,
30318 /* 83803 */ // Label 2600: @83803
30319 /* 83803 */ GIM_Try, /*On fail goto*//*Label 2601*/ GIMT_Encode4(83838), // Rule ID 5256 //
30320 /* 83808 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30321 /* 83812 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3931:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30322 /* 83812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru16),
30323 /* 83815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30324 /* 83817 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30325 /* 83819 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30326 /* 83821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30327 /* 83824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30328 /* 83830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30329 /* 83836 */ GIR_RootConstrainSelectedInstOperands,
30330 /* 83837 */ // GIR_Coverage, 5256,
30331 /* 83837 */ GIR_EraseRootFromParent_Done,
30332 /* 83838 */ // Label 2601: @83838
30333 /* 83838 */ GIM_Reject,
30334 /* 83839 */ // Label 2599: @83839
30335 /* 83839 */ GIM_Try, /*On fail goto*//*Label 2602*/ GIMT_Encode4(83919),
30336 /* 83844 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30337 /* 83848 */ GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(83883), // Rule ID 5262 //
30338 /* 83853 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30339 /* 83857 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3931:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30340 /* 83857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs16),
30341 /* 83860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30342 /* 83862 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30343 /* 83864 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30344 /* 83866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30345 /* 83869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30346 /* 83875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30347 /* 83881 */ GIR_RootConstrainSelectedInstOperands,
30348 /* 83882 */ // GIR_Coverage, 5262,
30349 /* 83882 */ GIR_EraseRootFromParent_Done,
30350 /* 83883 */ // Label 2603: @83883
30351 /* 83883 */ GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(83918), // Rule ID 5268 //
30352 /* 83888 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30353 /* 83892 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3931:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
30354 /* 83892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru16),
30355 /* 83895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30356 /* 83897 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30357 /* 83899 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30358 /* 83901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30359 /* 83904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30360 /* 83910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30361 /* 83916 */ GIR_RootConstrainSelectedInstOperands,
30362 /* 83917 */ // GIR_Coverage, 5268,
30363 /* 83917 */ GIR_EraseRootFromParent_Done,
30364 /* 83918 */ // Label 2604: @83918
30365 /* 83918 */ GIM_Reject,
30366 /* 83919 */ // Label 2602: @83919
30367 /* 83919 */ GIM_Reject,
30368 /* 83920 */ // Label 2598: @83920
30369 /* 83920 */ GIM_Reject,
30370 /* 83921 */ // Label 2590: @83921
30371 /* 83921 */ GIM_Reject,
30372 /* 83922 */ // Label 2573: @83922
30373 /* 83922 */ GIM_Try, /*On fail goto*//*Label 2605*/ GIMT_Encode4(84295),
30374 /* 83927 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
30375 /* 83930 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30376 /* 83933 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30377 /* 83936 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30378 /* 83939 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30379 /* 83942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30380 /* 83946 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30381 /* 83950 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30382 /* 83954 */ GIM_Try, /*On fail goto*//*Label 2606*/ GIMT_Encode4(84124),
30383 /* 83959 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30384 /* 83963 */ GIM_Try, /*On fail goto*//*Label 2607*/ GIMT_Encode4(84043),
30385 /* 83968 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30386 /* 83972 */ GIM_Try, /*On fail goto*//*Label 2608*/ GIMT_Encode4(84007), // Rule ID 5228 //
30387 /* 83977 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30388 /* 83981 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3931:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30389 /* 83981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs32),
30390 /* 83984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30391 /* 83986 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30392 /* 83988 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30393 /* 83990 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30394 /* 83993 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30395 /* 83999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30396 /* 84005 */ GIR_RootConstrainSelectedInstOperands,
30397 /* 84006 */ // GIR_Coverage, 5228,
30398 /* 84006 */ GIR_EraseRootFromParent_Done,
30399 /* 84007 */ // Label 2608: @84007
30400 /* 84007 */ GIM_Try, /*On fail goto*//*Label 2609*/ GIMT_Encode4(84042), // Rule ID 5234 //
30401 /* 84012 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30402 /* 84016 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3931:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30403 /* 84016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru32),
30404 /* 84019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30405 /* 84021 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30406 /* 84023 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30407 /* 84025 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30408 /* 84028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30409 /* 84034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30410 /* 84040 */ GIR_RootConstrainSelectedInstOperands,
30411 /* 84041 */ // GIR_Coverage, 5234,
30412 /* 84041 */ GIR_EraseRootFromParent_Done,
30413 /* 84042 */ // Label 2609: @84042
30414 /* 84042 */ GIM_Reject,
30415 /* 84043 */ // Label 2607: @84043
30416 /* 84043 */ GIM_Try, /*On fail goto*//*Label 2610*/ GIMT_Encode4(84123),
30417 /* 84048 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30418 /* 84052 */ GIM_Try, /*On fail goto*//*Label 2611*/ GIMT_Encode4(84087), // Rule ID 5240 //
30419 /* 84057 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30420 /* 84061 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3931:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30421 /* 84061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs32),
30422 /* 84064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30423 /* 84066 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30424 /* 84068 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30425 /* 84070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30426 /* 84073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30427 /* 84079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30428 /* 84085 */ GIR_RootConstrainSelectedInstOperands,
30429 /* 84086 */ // GIR_Coverage, 5240,
30430 /* 84086 */ GIR_EraseRootFromParent_Done,
30431 /* 84087 */ // Label 2611: @84087
30432 /* 84087 */ GIM_Try, /*On fail goto*//*Label 2612*/ GIMT_Encode4(84122), // Rule ID 5246 //
30433 /* 84092 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30434 /* 84096 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3931:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30435 /* 84096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru32),
30436 /* 84099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30437 /* 84101 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30438 /* 84103 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30439 /* 84105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30440 /* 84108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30441 /* 84114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30442 /* 84120 */ GIR_RootConstrainSelectedInstOperands,
30443 /* 84121 */ // GIR_Coverage, 5246,
30444 /* 84121 */ GIR_EraseRootFromParent_Done,
30445 /* 84122 */ // Label 2612: @84122
30446 /* 84122 */ GIM_Reject,
30447 /* 84123 */ // Label 2610: @84123
30448 /* 84123 */ GIM_Reject,
30449 /* 84124 */ // Label 2606: @84124
30450 /* 84124 */ GIM_Try, /*On fail goto*//*Label 2613*/ GIMT_Encode4(84294),
30451 /* 84129 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30452 /* 84133 */ GIM_Try, /*On fail goto*//*Label 2614*/ GIMT_Encode4(84213),
30453 /* 84138 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30454 /* 84142 */ GIM_Try, /*On fail goto*//*Label 2615*/ GIMT_Encode4(84177), // Rule ID 5252 //
30455 /* 84147 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30456 /* 84151 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3931:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30457 /* 84151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs32),
30458 /* 84154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30459 /* 84156 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30460 /* 84158 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30461 /* 84160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30462 /* 84163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30463 /* 84169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30464 /* 84175 */ GIR_RootConstrainSelectedInstOperands,
30465 /* 84176 */ // GIR_Coverage, 5252,
30466 /* 84176 */ GIR_EraseRootFromParent_Done,
30467 /* 84177 */ // Label 2615: @84177
30468 /* 84177 */ GIM_Try, /*On fail goto*//*Label 2616*/ GIMT_Encode4(84212), // Rule ID 5258 //
30469 /* 84182 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30470 /* 84186 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3931:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30471 /* 84186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru32),
30472 /* 84189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30473 /* 84191 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30474 /* 84193 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30475 /* 84195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30476 /* 84198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30477 /* 84204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30478 /* 84210 */ GIR_RootConstrainSelectedInstOperands,
30479 /* 84211 */ // GIR_Coverage, 5258,
30480 /* 84211 */ GIR_EraseRootFromParent_Done,
30481 /* 84212 */ // Label 2616: @84212
30482 /* 84212 */ GIM_Reject,
30483 /* 84213 */ // Label 2614: @84213
30484 /* 84213 */ GIM_Try, /*On fail goto*//*Label 2617*/ GIMT_Encode4(84293),
30485 /* 84218 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30486 /* 84222 */ GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(84257), // Rule ID 5264 //
30487 /* 84227 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30488 /* 84231 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3931:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30489 /* 84231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs32),
30490 /* 84234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30491 /* 84236 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30492 /* 84238 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30493 /* 84240 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30494 /* 84243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30495 /* 84249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30496 /* 84255 */ GIR_RootConstrainSelectedInstOperands,
30497 /* 84256 */ // GIR_Coverage, 5264,
30498 /* 84256 */ GIR_EraseRootFromParent_Done,
30499 /* 84257 */ // Label 2618: @84257
30500 /* 84257 */ GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(84292), // Rule ID 5270 //
30501 /* 84262 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30502 /* 84266 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3931:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
30503 /* 84266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru32),
30504 /* 84269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30505 /* 84271 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30506 /* 84273 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30507 /* 84275 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30508 /* 84278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30509 /* 84284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30510 /* 84290 */ GIR_RootConstrainSelectedInstOperands,
30511 /* 84291 */ // GIR_Coverage, 5270,
30512 /* 84291 */ GIR_EraseRootFromParent_Done,
30513 /* 84292 */ // Label 2619: @84292
30514 /* 84292 */ GIM_Reject,
30515 /* 84293 */ // Label 2617: @84293
30516 /* 84293 */ GIM_Reject,
30517 /* 84294 */ // Label 2613: @84294
30518 /* 84294 */ GIM_Reject,
30519 /* 84295 */ // Label 2605: @84295
30520 /* 84295 */ GIM_Reject,
30521 /* 84296 */ // Label 2574: @84296
30522 /* 84296 */ GIM_Reject,
30523 /* 84297 */ // Label 2570: @84297
30524 /* 84297 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2620*/ GIMT_Encode4(84432), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3079 //
30525 /* 84304 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx3),
30526 /* 84309 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
30527 /* 84312 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
30528 /* 84315 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
30529 /* 84318 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
30530 /* 84321 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
30531 /* 84324 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8,
30532 /* 84327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
30533 /* 84331 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4090:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBX3Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
30534 /* 84331 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
30535 /* 84334 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30536 /* 84338 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30537 /* 84343 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
30538 /* 84345 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
30539 /* 84348 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
30540 /* 84352 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30541 /* 84357 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
30542 /* 84361 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
30543 /* 84364 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
30544 /* 84368 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
30545 /* 84371 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
30546 /* 84375 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
30547 /* 84378 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
30548 /* 84381 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
30549 /* 84384 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
30550 /* 84389 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
30551 /* 84394 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
30552 /* 84399 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
30553 /* 84404 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
30554 /* 84409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX3Pseudo),
30555 /* 84412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
30556 /* 84414 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
30557 /* 84416 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30558 /* 84419 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm
30559 /* 84421 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
30560 /* 84424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30561 /* 84430 */ GIR_RootConstrainSelectedInstOperands,
30562 /* 84431 */ // GIR_Coverage, 3079,
30563 /* 84431 */ GIR_EraseRootFromParent_Done,
30564 /* 84432 */ // Label 2620: @84432
30565 /* 84432 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2621*/ GIMT_Encode4(84552), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3080 //
30566 /* 84439 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl4),
30567 /* 84444 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
30568 /* 84447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
30569 /* 84450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
30570 /* 84453 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
30571 /* 84456 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
30572 /* 84459 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8,
30573 /* 84462 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
30574 /* 84466 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4087:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBL4Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
30575 /* 84466 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
30576 /* 84469 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
30577 /* 84473 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30578 /* 84478 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
30579 /* 84482 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
30580 /* 84485 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
30581 /* 84489 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
30582 /* 84492 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
30583 /* 84496 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
30584 /* 84499 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn3
30585 /* 84503 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
30586 /* 84506 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
30587 /* 84511 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
30588 /* 84516 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
30589 /* 84521 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
30590 /* 84526 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
30591 /* 84531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL4Pseudo),
30592 /* 84534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
30593 /* 84536 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30594 /* 84539 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm
30595 /* 84541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
30596 /* 84544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30597 /* 84550 */ GIR_RootConstrainSelectedInstOperands,
30598 /* 84551 */ // GIR_Coverage, 3080,
30599 /* 84551 */ GIR_EraseRootFromParent_Done,
30600 /* 84552 */ // Label 2621: @84552
30601 /* 84552 */ GIM_Reject,
30602 /* 84553 */ // Label 2496: @84553
30603 /* 84553 */ GIM_Try, /*On fail goto*//*Label 2622*/ GIMT_Encode4(87747),
30604 /* 84558 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/8,
30605 /* 84561 */ GIM_Try, /*On fail goto*//*Label 2623*/ GIMT_Encode4(86376),
30606 /* 84566 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
30607 /* 84571 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
30608 /* 84574 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30609 /* 84577 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30610 /* 84580 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30611 /* 84583 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30612 /* 84586 */ GIM_SwitchType, /*MI*/0, /*Op*/6, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2627*/ GIMT_Encode4(86375),
30613 /* 84597 */ /*GILLT_v16s8*//*Label 2624*/ GIMT_Encode4(84617), GIMT_Encode4(0),
30614 /* 84605 */ /*GILLT_v8s16*//*Label 2625*/ GIMT_Encode4(85203), GIMT_Encode4(0),
30615 /* 84613 */ /*GILLT_v4s32*//*Label 2626*/ GIMT_Encode4(85789),
30616 /* 84617 */ // Label 2624: @84617
30617 /* 84617 */ GIM_Try, /*On fail goto*//*Label 2628*/ GIMT_Encode4(85202),
30618 /* 84622 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
30619 /* 84625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30620 /* 84629 */ GIM_Try, /*On fail goto*//*Label 2629*/ GIMT_Encode4(84741),
30621 /* 84634 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30622 /* 84638 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
30623 /* 84642 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2630*/ GIMT_Encode4(84691), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3572 //
30624 /* 84649 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30625 /* 84653 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30626 /* 84657 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30627 /* 84661 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30628 /* 84665 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30629 /* 84665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs8),
30630 /* 84668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30631 /* 84670 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30632 /* 84672 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30633 /* 84674 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30634 /* 84677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30635 /* 84683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30636 /* 84689 */ GIR_RootConstrainSelectedInstOperands,
30637 /* 84690 */ // GIR_Coverage, 3572,
30638 /* 84690 */ GIR_EraseRootFromParent_Done,
30639 /* 84691 */ // Label 2630: @84691
30640 /* 84691 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2631*/ GIMT_Encode4(84740), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3576 //
30641 /* 84698 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30642 /* 84702 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30643 /* 84706 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30644 /* 84710 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30645 /* 84714 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30646 /* 84714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs8),
30647 /* 84717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30648 /* 84719 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30649 /* 84721 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30650 /* 84723 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30651 /* 84726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30652 /* 84732 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30653 /* 84738 */ GIR_RootConstrainSelectedInstOperands,
30654 /* 84739 */ // GIR_Coverage, 3576,
30655 /* 84739 */ GIR_EraseRootFromParent_Done,
30656 /* 84740 */ // Label 2631: @84740
30657 /* 84740 */ GIM_Reject,
30658 /* 84741 */ // Label 2629: @84741
30659 /* 84741 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2632*/ GIMT_Encode4(84798), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3580 //
30660 /* 84748 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30661 /* 84752 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
30662 /* 84756 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30663 /* 84760 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30664 /* 84764 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30665 /* 84768 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30666 /* 84772 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVu8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30667 /* 84772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8),
30668 /* 84775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30669 /* 84777 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30670 /* 84779 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30671 /* 84781 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30672 /* 84784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30673 /* 84790 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30674 /* 84796 */ GIR_RootConstrainSelectedInstOperands,
30675 /* 84797 */ // GIR_Coverage, 3580,
30676 /* 84797 */ GIR_EraseRootFromParent_Done,
30677 /* 84798 */ // Label 2632: @84798
30678 /* 84798 */ GIM_Try, /*On fail goto*//*Label 2633*/ GIMT_Encode4(84910),
30679 /* 84803 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30680 /* 84807 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
30681 /* 84811 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2634*/ GIMT_Encode4(84860), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3608 //
30682 /* 84818 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30683 /* 84822 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30684 /* 84826 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30685 /* 84830 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30686 /* 84834 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30687 /* 84834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs8),
30688 /* 84837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30689 /* 84839 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30690 /* 84841 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30691 /* 84843 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30692 /* 84846 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30693 /* 84852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30694 /* 84858 */ GIR_RootConstrainSelectedInstOperands,
30695 /* 84859 */ // GIR_Coverage, 3608,
30696 /* 84859 */ GIR_EraseRootFromParent_Done,
30697 /* 84860 */ // Label 2634: @84860
30698 /* 84860 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2635*/ GIMT_Encode4(84909), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3612 //
30699 /* 84867 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30700 /* 84871 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30701 /* 84875 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30702 /* 84879 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30703 /* 84883 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30704 /* 84883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs8),
30705 /* 84886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30706 /* 84888 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30707 /* 84890 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30708 /* 84892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30709 /* 84895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30710 /* 84901 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30711 /* 84907 */ GIR_RootConstrainSelectedInstOperands,
30712 /* 84908 */ // GIR_Coverage, 3612,
30713 /* 84908 */ GIR_EraseRootFromParent_Done,
30714 /* 84909 */ // Label 2635: @84909
30715 /* 84909 */ GIM_Reject,
30716 /* 84910 */ // Label 2633: @84910
30717 /* 84910 */ GIM_Try, /*On fail goto*//*Label 2636*/ GIMT_Encode4(85026),
30718 /* 84915 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30719 /* 84919 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
30720 /* 84923 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2637*/ GIMT_Encode4(84974), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3574 //
30721 /* 84930 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30722 /* 84934 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30723 /* 84938 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30724 /* 84942 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30725 /* 84946 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30726 /* 84946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas8),
30727 /* 84949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30728 /* 84951 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
30729 /* 84953 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30730 /* 84955 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30731 /* 84957 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30732 /* 84960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30733 /* 84966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30734 /* 84972 */ GIR_RootConstrainSelectedInstOperands,
30735 /* 84973 */ // GIR_Coverage, 3574,
30736 /* 84973 */ GIR_EraseRootFromParent_Done,
30737 /* 84974 */ // Label 2637: @84974
30738 /* 84974 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2638*/ GIMT_Encode4(85025), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3578 //
30739 /* 84981 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30740 /* 84985 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30741 /* 84989 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30742 /* 84993 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30743 /* 84997 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30744 /* 84997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs8),
30745 /* 85000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30746 /* 85002 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
30747 /* 85004 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30748 /* 85006 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30749 /* 85008 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30750 /* 85011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30751 /* 85017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30752 /* 85023 */ GIR_RootConstrainSelectedInstOperands,
30753 /* 85024 */ // GIR_Coverage, 3578,
30754 /* 85024 */ GIR_EraseRootFromParent_Done,
30755 /* 85025 */ // Label 2638: @85025
30756 /* 85025 */ GIM_Reject,
30757 /* 85026 */ // Label 2636: @85026
30758 /* 85026 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2639*/ GIMT_Encode4(85085), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3582 //
30759 /* 85033 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30760 /* 85037 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
30761 /* 85041 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30762 /* 85045 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30763 /* 85049 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30764 /* 85053 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30765 /* 85057 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVau8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30766 /* 85057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8),
30767 /* 85060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30768 /* 85062 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
30769 /* 85064 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30770 /* 85066 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30771 /* 85068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30772 /* 85071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30773 /* 85077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30774 /* 85083 */ GIR_RootConstrainSelectedInstOperands,
30775 /* 85084 */ // GIR_Coverage, 3582,
30776 /* 85084 */ GIR_EraseRootFromParent_Done,
30777 /* 85085 */ // Label 2639: @85085
30778 /* 85085 */ GIM_Try, /*On fail goto*//*Label 2640*/ GIMT_Encode4(85201),
30779 /* 85090 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30780 /* 85094 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
30781 /* 85098 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2641*/ GIMT_Encode4(85149), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3610 //
30782 /* 85105 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30783 /* 85109 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30784 /* 85113 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30785 /* 85117 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30786 /* 85121 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30787 /* 85121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas8),
30788 /* 85124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30789 /* 85126 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
30790 /* 85128 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30791 /* 85130 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30792 /* 85132 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30793 /* 85135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30794 /* 85141 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30795 /* 85147 */ GIR_RootConstrainSelectedInstOperands,
30796 /* 85148 */ // GIR_Coverage, 3610,
30797 /* 85148 */ GIR_EraseRootFromParent_Done,
30798 /* 85149 */ // Label 2641: @85149
30799 /* 85149 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2642*/ GIMT_Encode4(85200), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3614 //
30800 /* 85156 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30801 /* 85160 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30802 /* 85164 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30803 /* 85168 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30804 /* 85172 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30805 /* 85172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs8),
30806 /* 85175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30807 /* 85177 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
30808 /* 85179 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30809 /* 85181 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30810 /* 85183 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30811 /* 85186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30812 /* 85192 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30813 /* 85198 */ GIR_RootConstrainSelectedInstOperands,
30814 /* 85199 */ // GIR_Coverage, 3614,
30815 /* 85199 */ GIR_EraseRootFromParent_Done,
30816 /* 85200 */ // Label 2642: @85200
30817 /* 85200 */ GIM_Reject,
30818 /* 85201 */ // Label 2640: @85201
30819 /* 85201 */ GIM_Reject,
30820 /* 85202 */ // Label 2628: @85202
30821 /* 85202 */ GIM_Reject,
30822 /* 85203 */ // Label 2625: @85203
30823 /* 85203 */ GIM_Try, /*On fail goto*//*Label 2643*/ GIMT_Encode4(85788),
30824 /* 85208 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
30825 /* 85211 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30826 /* 85215 */ GIM_Try, /*On fail goto*//*Label 2644*/ GIMT_Encode4(85327),
30827 /* 85220 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30828 /* 85224 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
30829 /* 85228 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2645*/ GIMT_Encode4(85277), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3584 //
30830 /* 85235 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30831 /* 85239 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30832 /* 85243 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30833 /* 85247 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30834 /* 85251 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30835 /* 85251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs16),
30836 /* 85254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30837 /* 85256 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30838 /* 85258 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30839 /* 85260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30840 /* 85263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30841 /* 85269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30842 /* 85275 */ GIR_RootConstrainSelectedInstOperands,
30843 /* 85276 */ // GIR_Coverage, 3584,
30844 /* 85276 */ GIR_EraseRootFromParent_Done,
30845 /* 85277 */ // Label 2645: @85277
30846 /* 85277 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2646*/ GIMT_Encode4(85326), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3588 //
30847 /* 85284 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30848 /* 85288 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30849 /* 85292 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30850 /* 85296 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30851 /* 85300 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30852 /* 85300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs16),
30853 /* 85303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30854 /* 85305 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30855 /* 85307 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30856 /* 85309 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30857 /* 85312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30858 /* 85318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30859 /* 85324 */ GIR_RootConstrainSelectedInstOperands,
30860 /* 85325 */ // GIR_Coverage, 3588,
30861 /* 85325 */ GIR_EraseRootFromParent_Done,
30862 /* 85326 */ // Label 2646: @85326
30863 /* 85326 */ GIM_Reject,
30864 /* 85327 */ // Label 2644: @85327
30865 /* 85327 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2647*/ GIMT_Encode4(85384), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3592 //
30866 /* 85334 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30867 /* 85338 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
30868 /* 85342 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30869 /* 85346 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30870 /* 85350 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30871 /* 85354 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30872 /* 85358 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVu16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30873 /* 85358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16),
30874 /* 85361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30875 /* 85363 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30876 /* 85365 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30877 /* 85367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30878 /* 85370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30879 /* 85376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30880 /* 85382 */ GIR_RootConstrainSelectedInstOperands,
30881 /* 85383 */ // GIR_Coverage, 3592,
30882 /* 85383 */ GIR_EraseRootFromParent_Done,
30883 /* 85384 */ // Label 2647: @85384
30884 /* 85384 */ GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(85496),
30885 /* 85389 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30886 /* 85393 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
30887 /* 85397 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2649*/ GIMT_Encode4(85446), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3616 //
30888 /* 85404 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30889 /* 85408 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30890 /* 85412 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30891 /* 85416 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30892 /* 85420 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30893 /* 85420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs16),
30894 /* 85423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30895 /* 85425 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30896 /* 85427 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30897 /* 85429 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30898 /* 85432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30899 /* 85438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30900 /* 85444 */ GIR_RootConstrainSelectedInstOperands,
30901 /* 85445 */ // GIR_Coverage, 3616,
30902 /* 85445 */ GIR_EraseRootFromParent_Done,
30903 /* 85446 */ // Label 2649: @85446
30904 /* 85446 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2650*/ GIMT_Encode4(85495), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3620 //
30905 /* 85453 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30906 /* 85457 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30907 /* 85461 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30908 /* 85465 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30909 /* 85469 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30910 /* 85469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs16),
30911 /* 85472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30912 /* 85474 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30913 /* 85476 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30914 /* 85478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30915 /* 85481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30916 /* 85487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30917 /* 85493 */ GIR_RootConstrainSelectedInstOperands,
30918 /* 85494 */ // GIR_Coverage, 3620,
30919 /* 85494 */ GIR_EraseRootFromParent_Done,
30920 /* 85495 */ // Label 2650: @85495
30921 /* 85495 */ GIM_Reject,
30922 /* 85496 */ // Label 2648: @85496
30923 /* 85496 */ GIM_Try, /*On fail goto*//*Label 2651*/ GIMT_Encode4(85612),
30924 /* 85501 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30925 /* 85505 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
30926 /* 85509 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2652*/ GIMT_Encode4(85560), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3586 //
30927 /* 85516 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30928 /* 85520 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30929 /* 85524 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30930 /* 85528 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30931 /* 85532 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30932 /* 85532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas16),
30933 /* 85535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30934 /* 85537 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
30935 /* 85539 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30936 /* 85541 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30937 /* 85543 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30938 /* 85546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30939 /* 85552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30940 /* 85558 */ GIR_RootConstrainSelectedInstOperands,
30941 /* 85559 */ // GIR_Coverage, 3586,
30942 /* 85559 */ GIR_EraseRootFromParent_Done,
30943 /* 85560 */ // Label 2652: @85560
30944 /* 85560 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2653*/ GIMT_Encode4(85611), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3590 //
30945 /* 85567 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30946 /* 85571 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30947 /* 85575 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30948 /* 85579 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30949 /* 85583 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30950 /* 85583 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs16),
30951 /* 85586 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30952 /* 85588 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
30953 /* 85590 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30954 /* 85592 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30955 /* 85594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30956 /* 85597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30957 /* 85603 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30958 /* 85609 */ GIR_RootConstrainSelectedInstOperands,
30959 /* 85610 */ // GIR_Coverage, 3590,
30960 /* 85610 */ GIR_EraseRootFromParent_Done,
30961 /* 85611 */ // Label 2653: @85611
30962 /* 85611 */ GIM_Reject,
30963 /* 85612 */ // Label 2651: @85612
30964 /* 85612 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2654*/ GIMT_Encode4(85671), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3594 //
30965 /* 85619 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30966 /* 85623 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
30967 /* 85627 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30968 /* 85631 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30969 /* 85635 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30970 /* 85639 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30971 /* 85643 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVau16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30972 /* 85643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16),
30973 /* 85646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30974 /* 85648 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
30975 /* 85650 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30976 /* 85652 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30977 /* 85654 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30978 /* 85657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30979 /* 85663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30980 /* 85669 */ GIR_RootConstrainSelectedInstOperands,
30981 /* 85670 */ // GIR_Coverage, 3594,
30982 /* 85670 */ GIR_EraseRootFromParent_Done,
30983 /* 85671 */ // Label 2654: @85671
30984 /* 85671 */ GIM_Try, /*On fail goto*//*Label 2655*/ GIMT_Encode4(85787),
30985 /* 85676 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30986 /* 85680 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
30987 /* 85684 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2656*/ GIMT_Encode4(85735), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3618 //
30988 /* 85691 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30989 /* 85695 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
30990 /* 85699 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30991 /* 85703 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30992 /* 85707 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30993 /* 85707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas16),
30994 /* 85710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
30995 /* 85712 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
30996 /* 85714 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
30997 /* 85716 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
30998 /* 85718 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30999 /* 85721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31000 /* 85727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31001 /* 85733 */ GIR_RootConstrainSelectedInstOperands,
31002 /* 85734 */ // GIR_Coverage, 3618,
31003 /* 85734 */ GIR_EraseRootFromParent_Done,
31004 /* 85735 */ // Label 2656: @85735
31005 /* 85735 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2657*/ GIMT_Encode4(85786), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3622 //
31006 /* 85742 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31007 /* 85746 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31008 /* 85750 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31009 /* 85754 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31010 /* 85758 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
31011 /* 85758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs16),
31012 /* 85761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31013 /* 85763 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
31014 /* 85765 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31015 /* 85767 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31016 /* 85769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31017 /* 85772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31018 /* 85778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31019 /* 85784 */ GIR_RootConstrainSelectedInstOperands,
31020 /* 85785 */ // GIR_Coverage, 3622,
31021 /* 85785 */ GIR_EraseRootFromParent_Done,
31022 /* 85786 */ // Label 2657: @85786
31023 /* 85786 */ GIM_Reject,
31024 /* 85787 */ // Label 2655: @85787
31025 /* 85787 */ GIM_Reject,
31026 /* 85788 */ // Label 2643: @85788
31027 /* 85788 */ GIM_Reject,
31028 /* 85789 */ // Label 2626: @85789
31029 /* 85789 */ GIM_Try, /*On fail goto*//*Label 2658*/ GIMT_Encode4(86374),
31030 /* 85794 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
31031 /* 85797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31032 /* 85801 */ GIM_Try, /*On fail goto*//*Label 2659*/ GIMT_Encode4(85913),
31033 /* 85806 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31034 /* 85810 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31035 /* 85814 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2660*/ GIMT_Encode4(85863), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3596 //
31036 /* 85821 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31037 /* 85825 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31038 /* 85829 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31039 /* 85833 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31040 /* 85837 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31041 /* 85837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs32),
31042 /* 85840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31043 /* 85842 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31044 /* 85844 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31045 /* 85846 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31046 /* 85849 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31047 /* 85855 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31048 /* 85861 */ GIR_RootConstrainSelectedInstOperands,
31049 /* 85862 */ // GIR_Coverage, 3596,
31050 /* 85862 */ GIR_EraseRootFromParent_Done,
31051 /* 85863 */ // Label 2660: @85863
31052 /* 85863 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2661*/ GIMT_Encode4(85912), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3600 //
31053 /* 85870 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31054 /* 85874 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31055 /* 85878 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31056 /* 85882 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31057 /* 85886 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31058 /* 85886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs32),
31059 /* 85889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31060 /* 85891 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31061 /* 85893 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31062 /* 85895 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31063 /* 85898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31064 /* 85904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31065 /* 85910 */ GIR_RootConstrainSelectedInstOperands,
31066 /* 85911 */ // GIR_Coverage, 3600,
31067 /* 85911 */ GIR_EraseRootFromParent_Done,
31068 /* 85912 */ // Label 2661: @85912
31069 /* 85912 */ GIM_Reject,
31070 /* 85913 */ // Label 2659: @85913
31071 /* 85913 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2662*/ GIMT_Encode4(85970), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3604 //
31072 /* 85920 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
31073 /* 85924 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31074 /* 85928 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31075 /* 85932 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31076 /* 85936 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31077 /* 85940 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31078 /* 85944 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVu32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31079 /* 85944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32),
31080 /* 85947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31081 /* 85949 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31082 /* 85951 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31083 /* 85953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31084 /* 85956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31085 /* 85962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31086 /* 85968 */ GIR_RootConstrainSelectedInstOperands,
31087 /* 85969 */ // GIR_Coverage, 3604,
31088 /* 85969 */ GIR_EraseRootFromParent_Done,
31089 /* 85970 */ // Label 2662: @85970
31090 /* 85970 */ GIM_Try, /*On fail goto*//*Label 2663*/ GIMT_Encode4(86082),
31091 /* 85975 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31092 /* 85979 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
31093 /* 85983 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2664*/ GIMT_Encode4(86032), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3624 //
31094 /* 85990 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31095 /* 85994 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31096 /* 85998 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31097 /* 86002 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31098 /* 86006 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31099 /* 86006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs32),
31100 /* 86009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31101 /* 86011 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31102 /* 86013 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31103 /* 86015 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31104 /* 86018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31105 /* 86024 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31106 /* 86030 */ GIR_RootConstrainSelectedInstOperands,
31107 /* 86031 */ // GIR_Coverage, 3624,
31108 /* 86031 */ GIR_EraseRootFromParent_Done,
31109 /* 86032 */ // Label 2664: @86032
31110 /* 86032 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2665*/ GIMT_Encode4(86081), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3628 //
31111 /* 86039 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31112 /* 86043 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31113 /* 86047 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31114 /* 86051 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31115 /* 86055 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31116 /* 86055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs32),
31117 /* 86058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31118 /* 86060 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31119 /* 86062 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31120 /* 86064 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31121 /* 86067 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31122 /* 86073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31123 /* 86079 */ GIR_RootConstrainSelectedInstOperands,
31124 /* 86080 */ // GIR_Coverage, 3628,
31125 /* 86080 */ GIR_EraseRootFromParent_Done,
31126 /* 86081 */ // Label 2665: @86081
31127 /* 86081 */ GIM_Reject,
31128 /* 86082 */ // Label 2663: @86082
31129 /* 86082 */ GIM_Try, /*On fail goto*//*Label 2666*/ GIMT_Encode4(86198),
31130 /* 86087 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31131 /* 86091 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31132 /* 86095 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2667*/ GIMT_Encode4(86146), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3598 //
31133 /* 86102 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31134 /* 86106 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31135 /* 86110 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31136 /* 86114 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31137 /* 86118 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31138 /* 86118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas32),
31139 /* 86121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31140 /* 86123 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
31141 /* 86125 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31142 /* 86127 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31143 /* 86129 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31144 /* 86132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31145 /* 86138 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31146 /* 86144 */ GIR_RootConstrainSelectedInstOperands,
31147 /* 86145 */ // GIR_Coverage, 3598,
31148 /* 86145 */ GIR_EraseRootFromParent_Done,
31149 /* 86146 */ // Label 2667: @86146
31150 /* 86146 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2668*/ GIMT_Encode4(86197), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3602 //
31151 /* 86153 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31152 /* 86157 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31153 /* 86161 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31154 /* 86165 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31155 /* 86169 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31156 /* 86169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs32),
31157 /* 86172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31158 /* 86174 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
31159 /* 86176 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31160 /* 86178 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31161 /* 86180 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31162 /* 86183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31163 /* 86189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31164 /* 86195 */ GIR_RootConstrainSelectedInstOperands,
31165 /* 86196 */ // GIR_Coverage, 3602,
31166 /* 86196 */ GIR_EraseRootFromParent_Done,
31167 /* 86197 */ // Label 2668: @86197
31168 /* 86197 */ GIM_Reject,
31169 /* 86198 */ // Label 2666: @86198
31170 /* 86198 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2669*/ GIMT_Encode4(86257), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3606 //
31171 /* 86205 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
31172 /* 86209 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
31173 /* 86213 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31174 /* 86217 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31175 /* 86221 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31176 /* 86225 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31177 /* 86229 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVau32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31178 /* 86229 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32),
31179 /* 86232 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31180 /* 86234 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
31181 /* 86236 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31182 /* 86238 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31183 /* 86240 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31184 /* 86243 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31185 /* 86249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31186 /* 86255 */ GIR_RootConstrainSelectedInstOperands,
31187 /* 86256 */ // GIR_Coverage, 3606,
31188 /* 86256 */ GIR_EraseRootFromParent_Done,
31189 /* 86257 */ // Label 2669: @86257
31190 /* 86257 */ GIM_Try, /*On fail goto*//*Label 2670*/ GIMT_Encode4(86373),
31191 /* 86262 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
31192 /* 86266 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
31193 /* 86270 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2671*/ GIMT_Encode4(86321), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3626 //
31194 /* 86277 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31195 /* 86281 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31196 /* 86285 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31197 /* 86289 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31198 /* 86293 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31199 /* 86293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas32),
31200 /* 86296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31201 /* 86298 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
31202 /* 86300 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31203 /* 86302 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31204 /* 86304 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31205 /* 86307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31206 /* 86313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31207 /* 86319 */ GIR_RootConstrainSelectedInstOperands,
31208 /* 86320 */ // GIR_Coverage, 3626,
31209 /* 86320 */ GIR_EraseRootFromParent_Done,
31210 /* 86321 */ // Label 2671: @86321
31211 /* 86321 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2672*/ GIMT_Encode4(86372), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3630 //
31212 /* 86328 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31213 /* 86332 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
31214 /* 86336 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31215 /* 86340 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31216 /* 86344 */ // (intrinsic_wo_chain:{ *:[i32] } 3879:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
31217 /* 86344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs32),
31218 /* 86347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
31219 /* 86349 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
31220 /* 86351 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
31221 /* 86353 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
31222 /* 86355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31223 /* 86358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31224 /* 86364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31225 /* 86370 */ GIR_RootConstrainSelectedInstOperands,
31226 /* 86371 */ // GIR_Coverage, 3630,
31227 /* 86371 */ GIR_EraseRootFromParent_Done,
31228 /* 86372 */ // Label 2672: @86372
31229 /* 86372 */ GIM_Reject,
31230 /* 86373 */ // Label 2670: @86373
31231 /* 86373 */ GIM_Reject,
31232 /* 86374 */ // Label 2658: @86374
31233 /* 86374 */ GIM_Reject,
31234 /* 86375 */ // Label 2627: @86375
31235 /* 86375 */ GIM_Reject,
31236 /* 86376 */ // Label 2623: @86376
31237 /* 86376 */ GIM_Try, /*On fail goto*//*Label 2673*/ GIMT_Encode4(87621),
31238 /* 86381 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
31239 /* 86386 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2677*/ GIMT_Encode4(87620),
31240 /* 86397 */ /*GILLT_v16s8*//*Label 2674*/ GIMT_Encode4(86417), GIMT_Encode4(0),
31241 /* 86405 */ /*GILLT_v8s16*//*Label 2675*/ GIMT_Encode4(86818), GIMT_Encode4(0),
31242 /* 86413 */ /*GILLT_v4s32*//*Label 2676*/ GIMT_Encode4(87219),
31243 /* 86417 */ // Label 2674: @86417
31244 /* 86417 */ GIM_Try, /*On fail goto*//*Label 2678*/ GIMT_Encode4(86817),
31245 /* 86422 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31246 /* 86425 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
31247 /* 86428 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
31248 /* 86431 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31249 /* 86434 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31250 /* 86437 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
31251 /* 86440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31252 /* 86444 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31253 /* 86448 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31254 /* 86452 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31255 /* 86456 */ GIM_Try, /*On fail goto*//*Label 2679*/ GIMT_Encode4(86501), // Rule ID 4846 //
31256 /* 86461 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31257 /* 86465 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31258 /* 86469 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31259 /* 86473 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3889:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31260 /* 86473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs8),
31261 /* 86476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31262 /* 86478 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31263 /* 86480 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31264 /* 86482 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31265 /* 86484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31266 /* 86487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31267 /* 86493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31268 /* 86499 */ GIR_RootConstrainSelectedInstOperands,
31269 /* 86500 */ // GIR_Coverage, 4846,
31270 /* 86500 */ GIR_EraseRootFromParent_Done,
31271 /* 86501 */ // Label 2679: @86501
31272 /* 86501 */ GIM_Try, /*On fail goto*//*Label 2680*/ GIMT_Encode4(86546), // Rule ID 4852 //
31273 /* 86506 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31274 /* 86510 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31275 /* 86514 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31276 /* 86518 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3889:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31277 /* 86518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs8),
31278 /* 86521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31279 /* 86523 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31280 /* 86525 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31281 /* 86527 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31282 /* 86529 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31283 /* 86532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31284 /* 86538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31285 /* 86544 */ GIR_RootConstrainSelectedInstOperands,
31286 /* 86545 */ // GIR_Coverage, 4852,
31287 /* 86545 */ GIR_EraseRootFromParent_Done,
31288 /* 86546 */ // Label 2680: @86546
31289 /* 86546 */ GIM_Try, /*On fail goto*//*Label 2681*/ GIMT_Encode4(86591), // Rule ID 4858 //
31290 /* 86551 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31291 /* 86555 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31292 /* 86559 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31293 /* 86563 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3889:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31294 /* 86563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs8),
31295 /* 86566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31296 /* 86568 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31297 /* 86570 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31298 /* 86572 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31299 /* 86574 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31300 /* 86577 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31301 /* 86583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31302 /* 86589 */ GIR_RootConstrainSelectedInstOperands,
31303 /* 86590 */ // GIR_Coverage, 4858,
31304 /* 86590 */ GIR_EraseRootFromParent_Done,
31305 /* 86591 */ // Label 2681: @86591
31306 /* 86591 */ GIM_Try, /*On fail goto*//*Label 2682*/ GIMT_Encode4(86636), // Rule ID 4864 //
31307 /* 86596 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31308 /* 86600 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31309 /* 86604 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31310 /* 86608 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3889:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31311 /* 86608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs8),
31312 /* 86611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31313 /* 86613 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31314 /* 86615 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31315 /* 86617 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31316 /* 86619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31317 /* 86622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31318 /* 86628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31319 /* 86634 */ GIR_RootConstrainSelectedInstOperands,
31320 /* 86635 */ // GIR_Coverage, 4864,
31321 /* 86635 */ GIR_EraseRootFromParent_Done,
31322 /* 86636 */ // Label 2682: @86636
31323 /* 86636 */ GIM_Try, /*On fail goto*//*Label 2683*/ GIMT_Encode4(86681), // Rule ID 4870 //
31324 /* 86641 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31325 /* 86645 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31326 /* 86649 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31327 /* 86653 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3889:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31328 /* 86653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs8),
31329 /* 86656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31330 /* 86658 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31331 /* 86660 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31332 /* 86662 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31333 /* 86664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31334 /* 86667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31335 /* 86673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31336 /* 86679 */ GIR_RootConstrainSelectedInstOperands,
31337 /* 86680 */ // GIR_Coverage, 4870,
31338 /* 86680 */ GIR_EraseRootFromParent_Done,
31339 /* 86681 */ // Label 2683: @86681
31340 /* 86681 */ GIM_Try, /*On fail goto*//*Label 2684*/ GIMT_Encode4(86726), // Rule ID 4876 //
31341 /* 86686 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31342 /* 86690 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31343 /* 86694 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31344 /* 86698 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3889:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31345 /* 86698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs8),
31346 /* 86701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31347 /* 86703 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31348 /* 86705 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31349 /* 86707 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31350 /* 86709 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31351 /* 86712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31352 /* 86718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31353 /* 86724 */ GIR_RootConstrainSelectedInstOperands,
31354 /* 86725 */ // GIR_Coverage, 4876,
31355 /* 86725 */ GIR_EraseRootFromParent_Done,
31356 /* 86726 */ // Label 2684: @86726
31357 /* 86726 */ GIM_Try, /*On fail goto*//*Label 2685*/ GIMT_Encode4(86771), // Rule ID 4882 //
31358 /* 86731 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31359 /* 86735 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31360 /* 86739 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31361 /* 86743 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3889:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31362 /* 86743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs8),
31363 /* 86746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31364 /* 86748 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31365 /* 86750 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31366 /* 86752 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31367 /* 86754 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31368 /* 86757 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31369 /* 86763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31370 /* 86769 */ GIR_RootConstrainSelectedInstOperands,
31371 /* 86770 */ // GIR_Coverage, 4882,
31372 /* 86770 */ GIR_EraseRootFromParent_Done,
31373 /* 86771 */ // Label 2685: @86771
31374 /* 86771 */ GIM_Try, /*On fail goto*//*Label 2686*/ GIMT_Encode4(86816), // Rule ID 4888 //
31375 /* 86776 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31376 /* 86780 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31377 /* 86784 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31378 /* 86788 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3889:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
31379 /* 86788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs8),
31380 /* 86791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31381 /* 86793 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31382 /* 86795 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31383 /* 86797 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31384 /* 86799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31385 /* 86802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31386 /* 86808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31387 /* 86814 */ GIR_RootConstrainSelectedInstOperands,
31388 /* 86815 */ // GIR_Coverage, 4888,
31389 /* 86815 */ GIR_EraseRootFromParent_Done,
31390 /* 86816 */ // Label 2686: @86816
31391 /* 86816 */ GIM_Reject,
31392 /* 86817 */ // Label 2678: @86817
31393 /* 86817 */ GIM_Reject,
31394 /* 86818 */ // Label 2675: @86818
31395 /* 86818 */ GIM_Try, /*On fail goto*//*Label 2687*/ GIMT_Encode4(87218),
31396 /* 86823 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31397 /* 86826 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31398 /* 86829 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
31399 /* 86832 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31400 /* 86835 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31401 /* 86838 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
31402 /* 86841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31403 /* 86845 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31404 /* 86849 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31405 /* 86853 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31406 /* 86857 */ GIM_Try, /*On fail goto*//*Label 2688*/ GIMT_Encode4(86902), // Rule ID 4848 //
31407 /* 86862 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31408 /* 86866 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31409 /* 86870 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31410 /* 86874 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31411 /* 86874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs16),
31412 /* 86877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31413 /* 86879 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31414 /* 86881 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31415 /* 86883 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31416 /* 86885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31417 /* 86888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31418 /* 86894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31419 /* 86900 */ GIR_RootConstrainSelectedInstOperands,
31420 /* 86901 */ // GIR_Coverage, 4848,
31421 /* 86901 */ GIR_EraseRootFromParent_Done,
31422 /* 86902 */ // Label 2688: @86902
31423 /* 86902 */ GIM_Try, /*On fail goto*//*Label 2689*/ GIMT_Encode4(86947), // Rule ID 4854 //
31424 /* 86907 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31425 /* 86911 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31426 /* 86915 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31427 /* 86919 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31428 /* 86919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs16),
31429 /* 86922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31430 /* 86924 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31431 /* 86926 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31432 /* 86928 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31433 /* 86930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31434 /* 86933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31435 /* 86939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31436 /* 86945 */ GIR_RootConstrainSelectedInstOperands,
31437 /* 86946 */ // GIR_Coverage, 4854,
31438 /* 86946 */ GIR_EraseRootFromParent_Done,
31439 /* 86947 */ // Label 2689: @86947
31440 /* 86947 */ GIM_Try, /*On fail goto*//*Label 2690*/ GIMT_Encode4(86992), // Rule ID 4860 //
31441 /* 86952 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31442 /* 86956 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31443 /* 86960 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31444 /* 86964 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31445 /* 86964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs16),
31446 /* 86967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31447 /* 86969 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31448 /* 86971 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31449 /* 86973 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31450 /* 86975 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31451 /* 86978 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31452 /* 86984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31453 /* 86990 */ GIR_RootConstrainSelectedInstOperands,
31454 /* 86991 */ // GIR_Coverage, 4860,
31455 /* 86991 */ GIR_EraseRootFromParent_Done,
31456 /* 86992 */ // Label 2690: @86992
31457 /* 86992 */ GIM_Try, /*On fail goto*//*Label 2691*/ GIMT_Encode4(87037), // Rule ID 4866 //
31458 /* 86997 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31459 /* 87001 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31460 /* 87005 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31461 /* 87009 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31462 /* 87009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs16),
31463 /* 87012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31464 /* 87014 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31465 /* 87016 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31466 /* 87018 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31467 /* 87020 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31468 /* 87023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31469 /* 87029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31470 /* 87035 */ GIR_RootConstrainSelectedInstOperands,
31471 /* 87036 */ // GIR_Coverage, 4866,
31472 /* 87036 */ GIR_EraseRootFromParent_Done,
31473 /* 87037 */ // Label 2691: @87037
31474 /* 87037 */ GIM_Try, /*On fail goto*//*Label 2692*/ GIMT_Encode4(87082), // Rule ID 4872 //
31475 /* 87042 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31476 /* 87046 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31477 /* 87050 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31478 /* 87054 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31479 /* 87054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs16),
31480 /* 87057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31481 /* 87059 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31482 /* 87061 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31483 /* 87063 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31484 /* 87065 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31485 /* 87068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31486 /* 87074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31487 /* 87080 */ GIR_RootConstrainSelectedInstOperands,
31488 /* 87081 */ // GIR_Coverage, 4872,
31489 /* 87081 */ GIR_EraseRootFromParent_Done,
31490 /* 87082 */ // Label 2692: @87082
31491 /* 87082 */ GIM_Try, /*On fail goto*//*Label 2693*/ GIMT_Encode4(87127), // Rule ID 4878 //
31492 /* 87087 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31493 /* 87091 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31494 /* 87095 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31495 /* 87099 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31496 /* 87099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs16),
31497 /* 87102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31498 /* 87104 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31499 /* 87106 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31500 /* 87108 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31501 /* 87110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31502 /* 87113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31503 /* 87119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31504 /* 87125 */ GIR_RootConstrainSelectedInstOperands,
31505 /* 87126 */ // GIR_Coverage, 4878,
31506 /* 87126 */ GIR_EraseRootFromParent_Done,
31507 /* 87127 */ // Label 2693: @87127
31508 /* 87127 */ GIM_Try, /*On fail goto*//*Label 2694*/ GIMT_Encode4(87172), // Rule ID 4884 //
31509 /* 87132 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31510 /* 87136 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31511 /* 87140 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31512 /* 87144 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31513 /* 87144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs16),
31514 /* 87147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31515 /* 87149 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31516 /* 87151 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31517 /* 87153 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31518 /* 87155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31519 /* 87158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31520 /* 87164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31521 /* 87170 */ GIR_RootConstrainSelectedInstOperands,
31522 /* 87171 */ // GIR_Coverage, 4884,
31523 /* 87171 */ GIR_EraseRootFromParent_Done,
31524 /* 87172 */ // Label 2694: @87172
31525 /* 87172 */ GIM_Try, /*On fail goto*//*Label 2695*/ GIMT_Encode4(87217), // Rule ID 4890 //
31526 /* 87177 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31527 /* 87181 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31528 /* 87185 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31529 /* 87189 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3889:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
31530 /* 87189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs16),
31531 /* 87192 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31532 /* 87194 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31533 /* 87196 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31534 /* 87198 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31535 /* 87200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31536 /* 87203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31537 /* 87209 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31538 /* 87215 */ GIR_RootConstrainSelectedInstOperands,
31539 /* 87216 */ // GIR_Coverage, 4890,
31540 /* 87216 */ GIR_EraseRootFromParent_Done,
31541 /* 87217 */ // Label 2695: @87217
31542 /* 87217 */ GIM_Reject,
31543 /* 87218 */ // Label 2687: @87218
31544 /* 87218 */ GIM_Reject,
31545 /* 87219 */ // Label 2676: @87219
31546 /* 87219 */ GIM_Try, /*On fail goto*//*Label 2696*/ GIMT_Encode4(87619),
31547 /* 87224 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31548 /* 87227 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
31549 /* 87230 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
31550 /* 87233 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31551 /* 87236 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31552 /* 87239 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
31553 /* 87242 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31554 /* 87246 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31555 /* 87250 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31556 /* 87254 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31557 /* 87258 */ GIM_Try, /*On fail goto*//*Label 2697*/ GIMT_Encode4(87303), // Rule ID 4850 //
31558 /* 87263 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31559 /* 87267 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31560 /* 87271 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31561 /* 87275 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31562 /* 87275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs32),
31563 /* 87278 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31564 /* 87280 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31565 /* 87282 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31566 /* 87284 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31567 /* 87286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31568 /* 87289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31569 /* 87295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31570 /* 87301 */ GIR_RootConstrainSelectedInstOperands,
31571 /* 87302 */ // GIR_Coverage, 4850,
31572 /* 87302 */ GIR_EraseRootFromParent_Done,
31573 /* 87303 */ // Label 2697: @87303
31574 /* 87303 */ GIM_Try, /*On fail goto*//*Label 2698*/ GIMT_Encode4(87348), // Rule ID 4856 //
31575 /* 87308 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31576 /* 87312 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31577 /* 87316 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31578 /* 87320 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31579 /* 87320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs32),
31580 /* 87323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31581 /* 87325 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31582 /* 87327 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31583 /* 87329 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31584 /* 87331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31585 /* 87334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31586 /* 87340 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31587 /* 87346 */ GIR_RootConstrainSelectedInstOperands,
31588 /* 87347 */ // GIR_Coverage, 4856,
31589 /* 87347 */ GIR_EraseRootFromParent_Done,
31590 /* 87348 */ // Label 2698: @87348
31591 /* 87348 */ GIM_Try, /*On fail goto*//*Label 2699*/ GIMT_Encode4(87393), // Rule ID 4862 //
31592 /* 87353 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31593 /* 87357 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31594 /* 87361 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31595 /* 87365 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31596 /* 87365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs32),
31597 /* 87368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31598 /* 87370 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31599 /* 87372 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31600 /* 87374 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31601 /* 87376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31602 /* 87379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31603 /* 87385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31604 /* 87391 */ GIR_RootConstrainSelectedInstOperands,
31605 /* 87392 */ // GIR_Coverage, 4862,
31606 /* 87392 */ GIR_EraseRootFromParent_Done,
31607 /* 87393 */ // Label 2699: @87393
31608 /* 87393 */ GIM_Try, /*On fail goto*//*Label 2700*/ GIMT_Encode4(87438), // Rule ID 4868 //
31609 /* 87398 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31610 /* 87402 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31611 /* 87406 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31612 /* 87410 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31613 /* 87410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs32),
31614 /* 87413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31615 /* 87415 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31616 /* 87417 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31617 /* 87419 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31618 /* 87421 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31619 /* 87424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31620 /* 87430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31621 /* 87436 */ GIR_RootConstrainSelectedInstOperands,
31622 /* 87437 */ // GIR_Coverage, 4868,
31623 /* 87437 */ GIR_EraseRootFromParent_Done,
31624 /* 87438 */ // Label 2700: @87438
31625 /* 87438 */ GIM_Try, /*On fail goto*//*Label 2701*/ GIMT_Encode4(87483), // Rule ID 4874 //
31626 /* 87443 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31627 /* 87447 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31628 /* 87451 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31629 /* 87455 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31630 /* 87455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs32),
31631 /* 87458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31632 /* 87460 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31633 /* 87462 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31634 /* 87464 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31635 /* 87466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31636 /* 87469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31637 /* 87475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31638 /* 87481 */ GIR_RootConstrainSelectedInstOperands,
31639 /* 87482 */ // GIR_Coverage, 4874,
31640 /* 87482 */ GIR_EraseRootFromParent_Done,
31641 /* 87483 */ // Label 2701: @87483
31642 /* 87483 */ GIM_Try, /*On fail goto*//*Label 2702*/ GIMT_Encode4(87528), // Rule ID 4880 //
31643 /* 87488 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31644 /* 87492 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31645 /* 87496 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31646 /* 87500 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31647 /* 87500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs32),
31648 /* 87503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31649 /* 87505 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31650 /* 87507 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31651 /* 87509 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31652 /* 87511 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31653 /* 87514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31654 /* 87520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31655 /* 87526 */ GIR_RootConstrainSelectedInstOperands,
31656 /* 87527 */ // GIR_Coverage, 4880,
31657 /* 87527 */ GIR_EraseRootFromParent_Done,
31658 /* 87528 */ // Label 2702: @87528
31659 /* 87528 */ GIM_Try, /*On fail goto*//*Label 2703*/ GIMT_Encode4(87573), // Rule ID 4886 //
31660 /* 87533 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31661 /* 87537 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31662 /* 87541 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31663 /* 87545 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31664 /* 87545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs32),
31665 /* 87548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31666 /* 87550 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31667 /* 87552 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31668 /* 87554 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31669 /* 87556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31670 /* 87559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31671 /* 87565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31672 /* 87571 */ GIR_RootConstrainSelectedInstOperands,
31673 /* 87572 */ // GIR_Coverage, 4886,
31674 /* 87572 */ GIR_EraseRootFromParent_Done,
31675 /* 87573 */ // Label 2703: @87573
31676 /* 87573 */ GIM_Try, /*On fail goto*//*Label 2704*/ GIMT_Encode4(87618), // Rule ID 4892 //
31677 /* 87578 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31678 /* 87582 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31679 /* 87586 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31680 /* 87590 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3889:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
31681 /* 87590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs32),
31682 /* 87593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31683 /* 87595 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
31684 /* 87597 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
31685 /* 87599 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
31686 /* 87601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31687 /* 87604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31688 /* 87610 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31689 /* 87616 */ GIR_RootConstrainSelectedInstOperands,
31690 /* 87617 */ // GIR_Coverage, 4892,
31691 /* 87617 */ GIR_EraseRootFromParent_Done,
31692 /* 87618 */ // Label 2704: @87618
31693 /* 87618 */ GIM_Reject,
31694 /* 87619 */ // Label 2696: @87619
31695 /* 87619 */ GIM_Reject,
31696 /* 87620 */ // Label 2677: @87620
31697 /* 87620 */ GIM_Reject,
31698 /* 87621 */ // Label 2673: @87621
31699 /* 87621 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2705*/ GIMT_Encode4(87746), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3081 //
31700 /* 87628 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx4),
31701 /* 87633 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
31702 /* 87636 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
31703 /* 87639 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
31704 /* 87642 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
31705 /* 87645 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
31706 /* 87648 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8,
31707 /* 87651 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s8,
31708 /* 87654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
31709 /* 87658 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4091:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBX4Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
31710 /* 87658 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
31711 /* 87661 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
31712 /* 87665 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
31713 /* 87670 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
31714 /* 87674 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
31715 /* 87677 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
31716 /* 87681 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
31717 /* 87684 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
31718 /* 87688 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
31719 /* 87691 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // Vn3
31720 /* 87695 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
31721 /* 87698 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
31722 /* 87703 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
31723 /* 87708 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
31724 /* 87713 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
31725 /* 87718 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
31726 /* 87723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX4Pseudo),
31727 /* 87726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
31728 /* 87728 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
31729 /* 87730 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31730 /* 87733 */ GIR_RootToRootCopy, /*OpIdx*/7, // Vm
31731 /* 87735 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
31732 /* 87738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31733 /* 87744 */ GIR_RootConstrainSelectedInstOperands,
31734 /* 87745 */ // GIR_Coverage, 3081,
31735 /* 87745 */ GIR_EraseRootFromParent_Done,
31736 /* 87746 */ // Label 2705: @87746
31737 /* 87746 */ GIM_Reject,
31738 /* 87747 */ // Label 2622: @87747
31739 /* 87747 */ GIM_Try, /*On fail goto*//*Label 2706*/ GIMT_Encode4(90366),
31740 /* 87752 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/10,
31741 /* 87755 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshrn),
31742 /* 87760 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 2709*/ GIMT_Encode4(90365),
31743 /* 87771 */ /*GILLT_v16s8*//*Label 2707*/ GIMT_Encode4(87783), GIMT_Encode4(0),
31744 /* 87779 */ /*GILLT_v8s16*//*Label 2708*/ GIMT_Encode4(89074),
31745 /* 87783 */ // Label 2707: @87783
31746 /* 87783 */ GIM_Try, /*On fail goto*//*Label 2710*/ GIMT_Encode4(89073),
31747 /* 87788 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31748 /* 87791 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31749 /* 87794 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31750 /* 87797 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31751 /* 87800 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31752 /* 87803 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
31753 /* 87806 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
31754 /* 87809 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
31755 /* 87812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31756 /* 87816 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31757 /* 87820 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31758 /* 87824 */ GIM_Try, /*On fail goto*//*Label 2711*/ GIMT_Encode4(88326),
31759 /* 87829 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31760 /* 87833 */ GIM_Try, /*On fail goto*//*Label 2712*/ GIMT_Encode4(88079),
31761 /* 87838 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31762 /* 87842 */ GIM_Try, /*On fail goto*//*Label 2713*/ GIMT_Encode4(87960),
31763 /* 87847 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31764 /* 87851 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
31765 /* 87855 */ GIM_Try, /*On fail goto*//*Label 2714*/ GIMT_Encode4(87907), // Rule ID 4161 //
31766 /* 87860 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31767 /* 87864 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31768 /* 87868 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31769 /* 87872 */ // MIs[1] Operand 1
31770 /* 87872 */ // No operand predicates
31771 /* 87872 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
31772 /* 87876 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31773 /* 87878 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31774 /* 87878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh),
31775 /* 87881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31776 /* 87883 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31777 /* 87885 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31778 /* 87887 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31779 /* 87890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31780 /* 87893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31781 /* 87899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31782 /* 87905 */ GIR_RootConstrainSelectedInstOperands,
31783 /* 87906 */ // GIR_Coverage, 4161,
31784 /* 87906 */ GIR_EraseRootFromParent_Done,
31785 /* 87907 */ // Label 2714: @87907
31786 /* 87907 */ GIM_Try, /*On fail goto*//*Label 2715*/ GIMT_Encode4(87959), // Rule ID 4163 //
31787 /* 87912 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31788 /* 87916 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31789 /* 87920 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31790 /* 87924 */ // MIs[1] Operand 1
31791 /* 87924 */ // No operand predicates
31792 /* 87924 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
31793 /* 87928 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31794 /* 87930 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31795 /* 87930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th),
31796 /* 87933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31797 /* 87935 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31798 /* 87937 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31799 /* 87939 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31800 /* 87942 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31801 /* 87945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31802 /* 87951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31803 /* 87957 */ GIR_RootConstrainSelectedInstOperands,
31804 /* 87958 */ // GIR_Coverage, 4163,
31805 /* 87958 */ GIR_EraseRootFromParent_Done,
31806 /* 87959 */ // Label 2715: @87959
31807 /* 87959 */ GIM_Reject,
31808 /* 87960 */ // Label 2713: @87960
31809 /* 87960 */ GIM_Try, /*On fail goto*//*Label 2716*/ GIMT_Encode4(88078),
31810 /* 87965 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31811 /* 87969 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
31812 /* 87973 */ GIM_Try, /*On fail goto*//*Label 2717*/ GIMT_Encode4(88025), // Rule ID 4169 //
31813 /* 87978 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31814 /* 87982 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31815 /* 87986 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31816 /* 87990 */ // MIs[1] Operand 1
31817 /* 87990 */ // No operand predicates
31818 /* 87990 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
31819 /* 87994 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31820 /* 87996 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31821 /* 87996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh),
31822 /* 87999 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31823 /* 88001 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31824 /* 88003 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31825 /* 88005 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31826 /* 88008 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31827 /* 88011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31828 /* 88017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31829 /* 88023 */ GIR_RootConstrainSelectedInstOperands,
31830 /* 88024 */ // GIR_Coverage, 4169,
31831 /* 88024 */ GIR_EraseRootFromParent_Done,
31832 /* 88025 */ // Label 2717: @88025
31833 /* 88025 */ GIM_Try, /*On fail goto*//*Label 2718*/ GIMT_Encode4(88077), // Rule ID 4171 //
31834 /* 88030 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31835 /* 88034 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31836 /* 88038 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31837 /* 88042 */ // MIs[1] Operand 1
31838 /* 88042 */ // No operand predicates
31839 /* 88042 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
31840 /* 88046 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31841 /* 88048 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31842 /* 88048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th),
31843 /* 88051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31844 /* 88053 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31845 /* 88055 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31846 /* 88057 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31847 /* 88060 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31848 /* 88063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31849 /* 88069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31850 /* 88075 */ GIR_RootConstrainSelectedInstOperands,
31851 /* 88076 */ // GIR_Coverage, 4171,
31852 /* 88076 */ GIR_EraseRootFromParent_Done,
31853 /* 88077 */ // Label 2718: @88077
31854 /* 88077 */ GIM_Reject,
31855 /* 88078 */ // Label 2716: @88078
31856 /* 88078 */ GIM_Reject,
31857 /* 88079 */ // Label 2712: @88079
31858 /* 88079 */ GIM_Try, /*On fail goto*//*Label 2719*/ GIMT_Encode4(88325),
31859 /* 88084 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31860 /* 88088 */ GIM_Try, /*On fail goto*//*Label 2720*/ GIMT_Encode4(88206),
31861 /* 88093 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31862 /* 88097 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
31863 /* 88101 */ GIM_Try, /*On fail goto*//*Label 2721*/ GIMT_Encode4(88153), // Rule ID 4177 //
31864 /* 88106 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31865 /* 88110 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31866 /* 88114 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31867 /* 88118 */ // MIs[1] Operand 1
31868 /* 88118 */ // No operand predicates
31869 /* 88118 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
31870 /* 88122 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31871 /* 88124 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31872 /* 88124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh),
31873 /* 88127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31874 /* 88129 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31875 /* 88131 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31876 /* 88133 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31877 /* 88136 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31878 /* 88139 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31879 /* 88145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31880 /* 88151 */ GIR_RootConstrainSelectedInstOperands,
31881 /* 88152 */ // GIR_Coverage, 4177,
31882 /* 88152 */ GIR_EraseRootFromParent_Done,
31883 /* 88153 */ // Label 2721: @88153
31884 /* 88153 */ GIM_Try, /*On fail goto*//*Label 2722*/ GIMT_Encode4(88205), // Rule ID 4179 //
31885 /* 88158 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31886 /* 88162 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31887 /* 88166 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31888 /* 88170 */ // MIs[1] Operand 1
31889 /* 88170 */ // No operand predicates
31890 /* 88170 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
31891 /* 88174 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31892 /* 88176 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31893 /* 88176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th),
31894 /* 88179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31895 /* 88181 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31896 /* 88183 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31897 /* 88185 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31898 /* 88188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31899 /* 88191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31900 /* 88197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31901 /* 88203 */ GIR_RootConstrainSelectedInstOperands,
31902 /* 88204 */ // GIR_Coverage, 4179,
31903 /* 88204 */ GIR_EraseRootFromParent_Done,
31904 /* 88205 */ // Label 2722: @88205
31905 /* 88205 */ GIM_Reject,
31906 /* 88206 */ // Label 2720: @88206
31907 /* 88206 */ GIM_Try, /*On fail goto*//*Label 2723*/ GIMT_Encode4(88324),
31908 /* 88211 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
31909 /* 88215 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
31910 /* 88219 */ GIM_Try, /*On fail goto*//*Label 2724*/ GIMT_Encode4(88271), // Rule ID 4185 //
31911 /* 88224 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31912 /* 88228 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31913 /* 88232 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31914 /* 88236 */ // MIs[1] Operand 1
31915 /* 88236 */ // No operand predicates
31916 /* 88236 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
31917 /* 88240 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31918 /* 88242 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31919 /* 88242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh),
31920 /* 88245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31921 /* 88247 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31922 /* 88249 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31923 /* 88251 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31924 /* 88254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31925 /* 88257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31926 /* 88263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31927 /* 88269 */ GIR_RootConstrainSelectedInstOperands,
31928 /* 88270 */ // GIR_Coverage, 4185,
31929 /* 88270 */ GIR_EraseRootFromParent_Done,
31930 /* 88271 */ // Label 2724: @88271
31931 /* 88271 */ GIM_Try, /*On fail goto*//*Label 2725*/ GIMT_Encode4(88323), // Rule ID 4187 //
31932 /* 88276 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31933 /* 88280 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31934 /* 88284 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31935 /* 88288 */ // MIs[1] Operand 1
31936 /* 88288 */ // No operand predicates
31937 /* 88288 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
31938 /* 88292 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31939 /* 88294 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31940 /* 88294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th),
31941 /* 88297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31942 /* 88299 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31943 /* 88301 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31944 /* 88303 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31945 /* 88306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31946 /* 88309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31947 /* 88315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31948 /* 88321 */ GIR_RootConstrainSelectedInstOperands,
31949 /* 88322 */ // GIR_Coverage, 4187,
31950 /* 88322 */ GIR_EraseRootFromParent_Done,
31951 /* 88323 */ // Label 2725: @88323
31952 /* 88323 */ GIM_Reject,
31953 /* 88324 */ // Label 2723: @88324
31954 /* 88324 */ GIM_Reject,
31955 /* 88325 */ // Label 2719: @88325
31956 /* 88325 */ GIM_Reject,
31957 /* 88326 */ // Label 2711: @88326
31958 /* 88326 */ GIM_Try, /*On fail goto*//*Label 2726*/ GIMT_Encode4(89072),
31959 /* 88331 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31960 /* 88335 */ GIM_Try, /*On fail goto*//*Label 2727*/ GIMT_Encode4(88581),
31961 /* 88340 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31962 /* 88344 */ GIM_Try, /*On fail goto*//*Label 2728*/ GIMT_Encode4(88462),
31963 /* 88349 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
31964 /* 88353 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
31965 /* 88357 */ GIM_Try, /*On fail goto*//*Label 2729*/ GIMT_Encode4(88409), // Rule ID 4193 //
31966 /* 88362 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31967 /* 88366 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31968 /* 88370 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31969 /* 88374 */ // MIs[1] Operand 1
31970 /* 88374 */ // No operand predicates
31971 /* 88374 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
31972 /* 88378 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31973 /* 88380 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31974 /* 88380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs16),
31975 /* 88383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31976 /* 88385 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31977 /* 88387 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31978 /* 88389 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
31979 /* 88392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31980 /* 88395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31981 /* 88401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31982 /* 88407 */ GIR_RootConstrainSelectedInstOperands,
31983 /* 88408 */ // GIR_Coverage, 4193,
31984 /* 88408 */ GIR_EraseRootFromParent_Done,
31985 /* 88409 */ // Label 2729: @88409
31986 /* 88409 */ GIM_Try, /*On fail goto*//*Label 2730*/ GIMT_Encode4(88461), // Rule ID 4195 //
31987 /* 88414 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
31988 /* 88418 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
31989 /* 88422 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
31990 /* 88426 */ // MIs[1] Operand 1
31991 /* 88426 */ // No operand predicates
31992 /* 88426 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
31993 /* 88430 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
31994 /* 88432 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
31995 /* 88432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths16),
31996 /* 88435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31997 /* 88437 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
31998 /* 88439 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31999 /* 88441 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32000 /* 88444 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32001 /* 88447 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32002 /* 88453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32003 /* 88459 */ GIR_RootConstrainSelectedInstOperands,
32004 /* 88460 */ // GIR_Coverage, 4195,
32005 /* 88460 */ GIR_EraseRootFromParent_Done,
32006 /* 88461 */ // Label 2730: @88461
32007 /* 88461 */ GIM_Reject,
32008 /* 88462 */ // Label 2728: @88462
32009 /* 88462 */ GIM_Try, /*On fail goto*//*Label 2731*/ GIMT_Encode4(88580),
32010 /* 88467 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32011 /* 88471 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
32012 /* 88475 */ GIM_Try, /*On fail goto*//*Label 2732*/ GIMT_Encode4(88527), // Rule ID 4201 //
32013 /* 88480 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32014 /* 88484 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32015 /* 88488 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32016 /* 88492 */ // MIs[1] Operand 1
32017 /* 88492 */ // No operand predicates
32018 /* 88492 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32019 /* 88496 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32020 /* 88498 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32021 /* 88498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu16),
32022 /* 88501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32023 /* 88503 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32024 /* 88505 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32025 /* 88507 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32026 /* 88510 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32027 /* 88513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32028 /* 88519 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32029 /* 88525 */ GIR_RootConstrainSelectedInstOperands,
32030 /* 88526 */ // GIR_Coverage, 4201,
32031 /* 88526 */ GIR_EraseRootFromParent_Done,
32032 /* 88527 */ // Label 2732: @88527
32033 /* 88527 */ GIM_Try, /*On fail goto*//*Label 2733*/ GIMT_Encode4(88579), // Rule ID 4203 //
32034 /* 88532 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32035 /* 88536 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32036 /* 88540 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32037 /* 88544 */ // MIs[1] Operand 1
32038 /* 88544 */ // No operand predicates
32039 /* 88544 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32040 /* 88548 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32041 /* 88550 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32042 /* 88550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu16),
32043 /* 88553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32044 /* 88555 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32045 /* 88557 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32046 /* 88559 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32047 /* 88562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32048 /* 88565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32049 /* 88571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32050 /* 88577 */ GIR_RootConstrainSelectedInstOperands,
32051 /* 88578 */ // GIR_Coverage, 4203,
32052 /* 88578 */ GIR_EraseRootFromParent_Done,
32053 /* 88579 */ // Label 2733: @88579
32054 /* 88579 */ GIM_Reject,
32055 /* 88580 */ // Label 2731: @88580
32056 /* 88580 */ GIM_Reject,
32057 /* 88581 */ // Label 2727: @88581
32058 /* 88581 */ GIM_Try, /*On fail goto*//*Label 2734*/ GIMT_Encode4(88827),
32059 /* 88586 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32060 /* 88590 */ GIM_Try, /*On fail goto*//*Label 2735*/ GIMT_Encode4(88708),
32061 /* 88595 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32062 /* 88599 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32063 /* 88603 */ GIM_Try, /*On fail goto*//*Label 2736*/ GIMT_Encode4(88655), // Rule ID 4209 //
32064 /* 88608 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32065 /* 88612 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32066 /* 88616 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32067 /* 88620 */ // MIs[1] Operand 1
32068 /* 88620 */ // No operand predicates
32069 /* 88620 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32070 /* 88624 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32071 /* 88626 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32072 /* 88626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs16),
32073 /* 88629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32074 /* 88631 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32075 /* 88633 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32076 /* 88635 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32077 /* 88638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32078 /* 88641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32079 /* 88647 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32080 /* 88653 */ GIR_RootConstrainSelectedInstOperands,
32081 /* 88654 */ // GIR_Coverage, 4209,
32082 /* 88654 */ GIR_EraseRootFromParent_Done,
32083 /* 88655 */ // Label 2736: @88655
32084 /* 88655 */ GIM_Try, /*On fail goto*//*Label 2737*/ GIMT_Encode4(88707), // Rule ID 4211 //
32085 /* 88660 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32086 /* 88664 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32087 /* 88668 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32088 /* 88672 */ // MIs[1] Operand 1
32089 /* 88672 */ // No operand predicates
32090 /* 88672 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32091 /* 88676 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32092 /* 88678 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32093 /* 88678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths16),
32094 /* 88681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32095 /* 88683 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32096 /* 88685 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32097 /* 88687 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32098 /* 88690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32099 /* 88693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32100 /* 88699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32101 /* 88705 */ GIR_RootConstrainSelectedInstOperands,
32102 /* 88706 */ // GIR_Coverage, 4211,
32103 /* 88706 */ GIR_EraseRootFromParent_Done,
32104 /* 88707 */ // Label 2737: @88707
32105 /* 88707 */ GIM_Reject,
32106 /* 88708 */ // Label 2735: @88708
32107 /* 88708 */ GIM_Try, /*On fail goto*//*Label 2738*/ GIMT_Encode4(88826),
32108 /* 88713 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32109 /* 88717 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
32110 /* 88721 */ GIM_Try, /*On fail goto*//*Label 2739*/ GIMT_Encode4(88773), // Rule ID 4217 //
32111 /* 88726 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32112 /* 88730 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32113 /* 88734 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32114 /* 88738 */ // MIs[1] Operand 1
32115 /* 88738 */ // No operand predicates
32116 /* 88738 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32117 /* 88742 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32118 /* 88744 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32119 /* 88744 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu16),
32120 /* 88747 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32121 /* 88749 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32122 /* 88751 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32123 /* 88753 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32124 /* 88756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32125 /* 88759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32126 /* 88765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32127 /* 88771 */ GIR_RootConstrainSelectedInstOperands,
32128 /* 88772 */ // GIR_Coverage, 4217,
32129 /* 88772 */ GIR_EraseRootFromParent_Done,
32130 /* 88773 */ // Label 2739: @88773
32131 /* 88773 */ GIM_Try, /*On fail goto*//*Label 2740*/ GIMT_Encode4(88825), // Rule ID 4219 //
32132 /* 88778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32133 /* 88782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32134 /* 88786 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32135 /* 88790 */ // MIs[1] Operand 1
32136 /* 88790 */ // No operand predicates
32137 /* 88790 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32138 /* 88794 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32139 /* 88796 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32140 /* 88796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu16),
32141 /* 88799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32142 /* 88801 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32143 /* 88803 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32144 /* 88805 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32145 /* 88808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32146 /* 88811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32147 /* 88817 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32148 /* 88823 */ GIR_RootConstrainSelectedInstOperands,
32149 /* 88824 */ // GIR_Coverage, 4219,
32150 /* 88824 */ GIR_EraseRootFromParent_Done,
32151 /* 88825 */ // Label 2740: @88825
32152 /* 88825 */ GIM_Reject,
32153 /* 88826 */ // Label 2738: @88826
32154 /* 88826 */ GIM_Reject,
32155 /* 88827 */ // Label 2734: @88827
32156 /* 88827 */ GIM_Try, /*On fail goto*//*Label 2741*/ GIMT_Encode4(88949),
32157 /* 88832 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32158 /* 88836 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32159 /* 88840 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32160 /* 88844 */ GIM_Try, /*On fail goto*//*Label 2742*/ GIMT_Encode4(88896), // Rule ID 4225 //
32161 /* 88849 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32162 /* 88853 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32163 /* 88857 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32164 /* 88861 */ // MIs[1] Operand 1
32165 /* 88861 */ // No operand predicates
32166 /* 88861 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32167 /* 88865 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32168 /* 88867 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32169 /* 88867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16bh),
32170 /* 88870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32171 /* 88872 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32172 /* 88874 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32173 /* 88876 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32174 /* 88879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32175 /* 88882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32176 /* 88888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32177 /* 88894 */ GIR_RootConstrainSelectedInstOperands,
32178 /* 88895 */ // GIR_Coverage, 4225,
32179 /* 88895 */ GIR_EraseRootFromParent_Done,
32180 /* 88896 */ // Label 2742: @88896
32181 /* 88896 */ GIM_Try, /*On fail goto*//*Label 2743*/ GIMT_Encode4(88948), // Rule ID 4227 //
32182 /* 88901 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32183 /* 88905 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32184 /* 88909 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32185 /* 88913 */ // MIs[1] Operand 1
32186 /* 88913 */ // No operand predicates
32187 /* 88913 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32188 /* 88917 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32189 /* 88919 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32190 /* 88919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16th),
32191 /* 88922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32192 /* 88924 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32193 /* 88926 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32194 /* 88928 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32195 /* 88931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32196 /* 88934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32197 /* 88940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32198 /* 88946 */ GIR_RootConstrainSelectedInstOperands,
32199 /* 88947 */ // GIR_Coverage, 4227,
32200 /* 88947 */ GIR_EraseRootFromParent_Done,
32201 /* 88948 */ // Label 2743: @88948
32202 /* 88948 */ GIM_Reject,
32203 /* 88949 */ // Label 2741: @88949
32204 /* 88949 */ GIM_Try, /*On fail goto*//*Label 2744*/ GIMT_Encode4(89071),
32205 /* 88954 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32206 /* 88958 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32207 /* 88962 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32208 /* 88966 */ GIM_Try, /*On fail goto*//*Label 2745*/ GIMT_Encode4(89018), // Rule ID 4233 //
32209 /* 88971 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32210 /* 88975 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32211 /* 88979 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32212 /* 88983 */ // MIs[1] Operand 1
32213 /* 88983 */ // No operand predicates
32214 /* 88983 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32215 /* 88987 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32216 /* 88989 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32217 /* 88989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16bh),
32218 /* 88992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32219 /* 88994 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32220 /* 88996 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32221 /* 88998 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32222 /* 89001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32223 /* 89004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32224 /* 89010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32225 /* 89016 */ GIR_RootConstrainSelectedInstOperands,
32226 /* 89017 */ // GIR_Coverage, 4233,
32227 /* 89017 */ GIR_EraseRootFromParent_Done,
32228 /* 89018 */ // Label 2745: @89018
32229 /* 89018 */ GIM_Try, /*On fail goto*//*Label 2746*/ GIMT_Encode4(89070), // Rule ID 4235 //
32230 /* 89023 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32231 /* 89027 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32232 /* 89031 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
32233 /* 89035 */ // MIs[1] Operand 1
32234 /* 89035 */ // No operand predicates
32235 /* 89035 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32236 /* 89039 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32237 /* 89041 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3939:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
32238 /* 89041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16th),
32239 /* 89044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32240 /* 89046 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32241 /* 89048 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32242 /* 89050 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32243 /* 89053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32244 /* 89056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32245 /* 89062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32246 /* 89068 */ GIR_RootConstrainSelectedInstOperands,
32247 /* 89069 */ // GIR_Coverage, 4235,
32248 /* 89069 */ GIR_EraseRootFromParent_Done,
32249 /* 89070 */ // Label 2746: @89070
32250 /* 89070 */ GIM_Reject,
32251 /* 89071 */ // Label 2744: @89071
32252 /* 89071 */ GIM_Reject,
32253 /* 89072 */ // Label 2726: @89072
32254 /* 89072 */ GIM_Reject,
32255 /* 89073 */ // Label 2710: @89073
32256 /* 89073 */ GIM_Reject,
32257 /* 89074 */ // Label 2708: @89074
32258 /* 89074 */ GIM_Try, /*On fail goto*//*Label 2747*/ GIMT_Encode4(90364),
32259 /* 89079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
32260 /* 89082 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
32261 /* 89085 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32262 /* 89088 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32263 /* 89091 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
32264 /* 89094 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
32265 /* 89097 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
32266 /* 89100 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
32267 /* 89103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32268 /* 89107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32269 /* 89111 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32270 /* 89115 */ GIM_Try, /*On fail goto*//*Label 2748*/ GIMT_Encode4(89617),
32271 /* 89120 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32272 /* 89124 */ GIM_Try, /*On fail goto*//*Label 2749*/ GIMT_Encode4(89370),
32273 /* 89129 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32274 /* 89133 */ GIM_Try, /*On fail goto*//*Label 2750*/ GIMT_Encode4(89251),
32275 /* 89138 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32276 /* 89142 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32277 /* 89146 */ GIM_Try, /*On fail goto*//*Label 2751*/ GIMT_Encode4(89198), // Rule ID 4165 //
32278 /* 89151 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32279 /* 89155 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32280 /* 89159 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32281 /* 89163 */ // MIs[1] Operand 1
32282 /* 89163 */ // No operand predicates
32283 /* 89163 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32284 /* 89167 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32285 /* 89169 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32286 /* 89169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh),
32287 /* 89172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32288 /* 89174 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32289 /* 89176 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32290 /* 89178 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32291 /* 89181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32292 /* 89184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32293 /* 89190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32294 /* 89196 */ GIR_RootConstrainSelectedInstOperands,
32295 /* 89197 */ // GIR_Coverage, 4165,
32296 /* 89197 */ GIR_EraseRootFromParent_Done,
32297 /* 89198 */ // Label 2751: @89198
32298 /* 89198 */ GIM_Try, /*On fail goto*//*Label 2752*/ GIMT_Encode4(89250), // Rule ID 4167 //
32299 /* 89203 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32300 /* 89207 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32301 /* 89211 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32302 /* 89215 */ // MIs[1] Operand 1
32303 /* 89215 */ // No operand predicates
32304 /* 89215 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32305 /* 89219 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32306 /* 89221 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32307 /* 89221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th),
32308 /* 89224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32309 /* 89226 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32310 /* 89228 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32311 /* 89230 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32312 /* 89233 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32313 /* 89236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32314 /* 89242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32315 /* 89248 */ GIR_RootConstrainSelectedInstOperands,
32316 /* 89249 */ // GIR_Coverage, 4167,
32317 /* 89249 */ GIR_EraseRootFromParent_Done,
32318 /* 89250 */ // Label 2752: @89250
32319 /* 89250 */ GIM_Reject,
32320 /* 89251 */ // Label 2750: @89251
32321 /* 89251 */ GIM_Try, /*On fail goto*//*Label 2753*/ GIMT_Encode4(89369),
32322 /* 89256 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32323 /* 89260 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
32324 /* 89264 */ GIM_Try, /*On fail goto*//*Label 2754*/ GIMT_Encode4(89316), // Rule ID 4173 //
32325 /* 89269 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32326 /* 89273 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32327 /* 89277 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32328 /* 89281 */ // MIs[1] Operand 1
32329 /* 89281 */ // No operand predicates
32330 /* 89281 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32331 /* 89285 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32332 /* 89287 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32333 /* 89287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh),
32334 /* 89290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32335 /* 89292 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32336 /* 89294 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32337 /* 89296 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32338 /* 89299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32339 /* 89302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32340 /* 89308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32341 /* 89314 */ GIR_RootConstrainSelectedInstOperands,
32342 /* 89315 */ // GIR_Coverage, 4173,
32343 /* 89315 */ GIR_EraseRootFromParent_Done,
32344 /* 89316 */ // Label 2754: @89316
32345 /* 89316 */ GIM_Try, /*On fail goto*//*Label 2755*/ GIMT_Encode4(89368), // Rule ID 4175 //
32346 /* 89321 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32347 /* 89325 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32348 /* 89329 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32349 /* 89333 */ // MIs[1] Operand 1
32350 /* 89333 */ // No operand predicates
32351 /* 89333 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32352 /* 89337 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32353 /* 89339 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32354 /* 89339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th),
32355 /* 89342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32356 /* 89344 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32357 /* 89346 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32358 /* 89348 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32359 /* 89351 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32360 /* 89354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32361 /* 89360 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32362 /* 89366 */ GIR_RootConstrainSelectedInstOperands,
32363 /* 89367 */ // GIR_Coverage, 4175,
32364 /* 89367 */ GIR_EraseRootFromParent_Done,
32365 /* 89368 */ // Label 2755: @89368
32366 /* 89368 */ GIM_Reject,
32367 /* 89369 */ // Label 2753: @89369
32368 /* 89369 */ GIM_Reject,
32369 /* 89370 */ // Label 2749: @89370
32370 /* 89370 */ GIM_Try, /*On fail goto*//*Label 2756*/ GIMT_Encode4(89616),
32371 /* 89375 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32372 /* 89379 */ GIM_Try, /*On fail goto*//*Label 2757*/ GIMT_Encode4(89497),
32373 /* 89384 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32374 /* 89388 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32375 /* 89392 */ GIM_Try, /*On fail goto*//*Label 2758*/ GIMT_Encode4(89444), // Rule ID 4181 //
32376 /* 89397 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32377 /* 89401 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32378 /* 89405 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32379 /* 89409 */ // MIs[1] Operand 1
32380 /* 89409 */ // No operand predicates
32381 /* 89409 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32382 /* 89413 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32383 /* 89415 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32384 /* 89415 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh),
32385 /* 89418 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32386 /* 89420 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32387 /* 89422 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32388 /* 89424 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32389 /* 89427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32390 /* 89430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32391 /* 89436 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32392 /* 89442 */ GIR_RootConstrainSelectedInstOperands,
32393 /* 89443 */ // GIR_Coverage, 4181,
32394 /* 89443 */ GIR_EraseRootFromParent_Done,
32395 /* 89444 */ // Label 2758: @89444
32396 /* 89444 */ GIM_Try, /*On fail goto*//*Label 2759*/ GIMT_Encode4(89496), // Rule ID 4183 //
32397 /* 89449 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32398 /* 89453 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32399 /* 89457 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32400 /* 89461 */ // MIs[1] Operand 1
32401 /* 89461 */ // No operand predicates
32402 /* 89461 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32403 /* 89465 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32404 /* 89467 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32405 /* 89467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th),
32406 /* 89470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32407 /* 89472 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32408 /* 89474 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32409 /* 89476 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32410 /* 89479 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32411 /* 89482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32412 /* 89488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32413 /* 89494 */ GIR_RootConstrainSelectedInstOperands,
32414 /* 89495 */ // GIR_Coverage, 4183,
32415 /* 89495 */ GIR_EraseRootFromParent_Done,
32416 /* 89496 */ // Label 2759: @89496
32417 /* 89496 */ GIM_Reject,
32418 /* 89497 */ // Label 2757: @89497
32419 /* 89497 */ GIM_Try, /*On fail goto*//*Label 2760*/ GIMT_Encode4(89615),
32420 /* 89502 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32421 /* 89506 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
32422 /* 89510 */ GIM_Try, /*On fail goto*//*Label 2761*/ GIMT_Encode4(89562), // Rule ID 4189 //
32423 /* 89515 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32424 /* 89519 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32425 /* 89523 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32426 /* 89527 */ // MIs[1] Operand 1
32427 /* 89527 */ // No operand predicates
32428 /* 89527 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32429 /* 89531 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32430 /* 89533 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32431 /* 89533 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh),
32432 /* 89536 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32433 /* 89538 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32434 /* 89540 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32435 /* 89542 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32436 /* 89545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32437 /* 89548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32438 /* 89554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32439 /* 89560 */ GIR_RootConstrainSelectedInstOperands,
32440 /* 89561 */ // GIR_Coverage, 4189,
32441 /* 89561 */ GIR_EraseRootFromParent_Done,
32442 /* 89562 */ // Label 2761: @89562
32443 /* 89562 */ GIM_Try, /*On fail goto*//*Label 2762*/ GIMT_Encode4(89614), // Rule ID 4191 //
32444 /* 89567 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32445 /* 89571 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32446 /* 89575 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32447 /* 89579 */ // MIs[1] Operand 1
32448 /* 89579 */ // No operand predicates
32449 /* 89579 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32450 /* 89583 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32451 /* 89585 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32452 /* 89585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th),
32453 /* 89588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32454 /* 89590 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32455 /* 89592 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32456 /* 89594 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32457 /* 89597 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32458 /* 89600 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32459 /* 89606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32460 /* 89612 */ GIR_RootConstrainSelectedInstOperands,
32461 /* 89613 */ // GIR_Coverage, 4191,
32462 /* 89613 */ GIR_EraseRootFromParent_Done,
32463 /* 89614 */ // Label 2762: @89614
32464 /* 89614 */ GIM_Reject,
32465 /* 89615 */ // Label 2760: @89615
32466 /* 89615 */ GIM_Reject,
32467 /* 89616 */ // Label 2756: @89616
32468 /* 89616 */ GIM_Reject,
32469 /* 89617 */ // Label 2748: @89617
32470 /* 89617 */ GIM_Try, /*On fail goto*//*Label 2763*/ GIMT_Encode4(90363),
32471 /* 89622 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32472 /* 89626 */ GIM_Try, /*On fail goto*//*Label 2764*/ GIMT_Encode4(89872),
32473 /* 89631 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32474 /* 89635 */ GIM_Try, /*On fail goto*//*Label 2765*/ GIMT_Encode4(89753),
32475 /* 89640 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32476 /* 89644 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32477 /* 89648 */ GIM_Try, /*On fail goto*//*Label 2766*/ GIMT_Encode4(89700), // Rule ID 4197 //
32478 /* 89653 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32479 /* 89657 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32480 /* 89661 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32481 /* 89665 */ // MIs[1] Operand 1
32482 /* 89665 */ // No operand predicates
32483 /* 89665 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32484 /* 89669 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32485 /* 89671 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32486 /* 89671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs32),
32487 /* 89674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32488 /* 89676 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32489 /* 89678 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32490 /* 89680 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32491 /* 89683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32492 /* 89686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32493 /* 89692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32494 /* 89698 */ GIR_RootConstrainSelectedInstOperands,
32495 /* 89699 */ // GIR_Coverage, 4197,
32496 /* 89699 */ GIR_EraseRootFromParent_Done,
32497 /* 89700 */ // Label 2766: @89700
32498 /* 89700 */ GIM_Try, /*On fail goto*//*Label 2767*/ GIMT_Encode4(89752), // Rule ID 4199 //
32499 /* 89705 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32500 /* 89709 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32501 /* 89713 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32502 /* 89717 */ // MIs[1] Operand 1
32503 /* 89717 */ // No operand predicates
32504 /* 89717 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32505 /* 89721 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32506 /* 89723 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32507 /* 89723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths32),
32508 /* 89726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32509 /* 89728 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32510 /* 89730 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32511 /* 89732 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32512 /* 89735 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32513 /* 89738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32514 /* 89744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32515 /* 89750 */ GIR_RootConstrainSelectedInstOperands,
32516 /* 89751 */ // GIR_Coverage, 4199,
32517 /* 89751 */ GIR_EraseRootFromParent_Done,
32518 /* 89752 */ // Label 2767: @89752
32519 /* 89752 */ GIM_Reject,
32520 /* 89753 */ // Label 2765: @89753
32521 /* 89753 */ GIM_Try, /*On fail goto*//*Label 2768*/ GIMT_Encode4(89871),
32522 /* 89758 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32523 /* 89762 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
32524 /* 89766 */ GIM_Try, /*On fail goto*//*Label 2769*/ GIMT_Encode4(89818), // Rule ID 4205 //
32525 /* 89771 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32526 /* 89775 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32527 /* 89779 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32528 /* 89783 */ // MIs[1] Operand 1
32529 /* 89783 */ // No operand predicates
32530 /* 89783 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32531 /* 89787 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32532 /* 89789 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32533 /* 89789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu32),
32534 /* 89792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32535 /* 89794 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32536 /* 89796 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32537 /* 89798 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32538 /* 89801 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32539 /* 89804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32540 /* 89810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32541 /* 89816 */ GIR_RootConstrainSelectedInstOperands,
32542 /* 89817 */ // GIR_Coverage, 4205,
32543 /* 89817 */ GIR_EraseRootFromParent_Done,
32544 /* 89818 */ // Label 2769: @89818
32545 /* 89818 */ GIM_Try, /*On fail goto*//*Label 2770*/ GIMT_Encode4(89870), // Rule ID 4207 //
32546 /* 89823 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32547 /* 89827 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32548 /* 89831 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32549 /* 89835 */ // MIs[1] Operand 1
32550 /* 89835 */ // No operand predicates
32551 /* 89835 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32552 /* 89839 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32553 /* 89841 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32554 /* 89841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu32),
32555 /* 89844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32556 /* 89846 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32557 /* 89848 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32558 /* 89850 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32559 /* 89853 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32560 /* 89856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32561 /* 89862 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32562 /* 89868 */ GIR_RootConstrainSelectedInstOperands,
32563 /* 89869 */ // GIR_Coverage, 4207,
32564 /* 89869 */ GIR_EraseRootFromParent_Done,
32565 /* 89870 */ // Label 2770: @89870
32566 /* 89870 */ GIM_Reject,
32567 /* 89871 */ // Label 2768: @89871
32568 /* 89871 */ GIM_Reject,
32569 /* 89872 */ // Label 2764: @89872
32570 /* 89872 */ GIM_Try, /*On fail goto*//*Label 2771*/ GIMT_Encode4(90118),
32571 /* 89877 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32572 /* 89881 */ GIM_Try, /*On fail goto*//*Label 2772*/ GIMT_Encode4(89999),
32573 /* 89886 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
32574 /* 89890 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32575 /* 89894 */ GIM_Try, /*On fail goto*//*Label 2773*/ GIMT_Encode4(89946), // Rule ID 4213 //
32576 /* 89899 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32577 /* 89903 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32578 /* 89907 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32579 /* 89911 */ // MIs[1] Operand 1
32580 /* 89911 */ // No operand predicates
32581 /* 89911 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32582 /* 89915 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32583 /* 89917 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32584 /* 89917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs32),
32585 /* 89920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32586 /* 89922 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32587 /* 89924 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32588 /* 89926 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32589 /* 89929 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32590 /* 89932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32591 /* 89938 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32592 /* 89944 */ GIR_RootConstrainSelectedInstOperands,
32593 /* 89945 */ // GIR_Coverage, 4213,
32594 /* 89945 */ GIR_EraseRootFromParent_Done,
32595 /* 89946 */ // Label 2773: @89946
32596 /* 89946 */ GIM_Try, /*On fail goto*//*Label 2774*/ GIMT_Encode4(89998), // Rule ID 4215 //
32597 /* 89951 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32598 /* 89955 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32599 /* 89959 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32600 /* 89963 */ // MIs[1] Operand 1
32601 /* 89963 */ // No operand predicates
32602 /* 89963 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32603 /* 89967 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32604 /* 89969 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32605 /* 89969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths32),
32606 /* 89972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32607 /* 89974 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32608 /* 89976 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32609 /* 89978 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32610 /* 89981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32611 /* 89984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32612 /* 89990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32613 /* 89996 */ GIR_RootConstrainSelectedInstOperands,
32614 /* 89997 */ // GIR_Coverage, 4215,
32615 /* 89997 */ GIR_EraseRootFromParent_Done,
32616 /* 89998 */ // Label 2774: @89998
32617 /* 89998 */ GIM_Reject,
32618 /* 89999 */ // Label 2772: @89999
32619 /* 89999 */ GIM_Try, /*On fail goto*//*Label 2775*/ GIMT_Encode4(90117),
32620 /* 90004 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32621 /* 90008 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
32622 /* 90012 */ GIM_Try, /*On fail goto*//*Label 2776*/ GIMT_Encode4(90064), // Rule ID 4221 //
32623 /* 90017 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32624 /* 90021 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32625 /* 90025 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32626 /* 90029 */ // MIs[1] Operand 1
32627 /* 90029 */ // No operand predicates
32628 /* 90029 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32629 /* 90033 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32630 /* 90035 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32631 /* 90035 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu32),
32632 /* 90038 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32633 /* 90040 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32634 /* 90042 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32635 /* 90044 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32636 /* 90047 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32637 /* 90050 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32638 /* 90056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32639 /* 90062 */ GIR_RootConstrainSelectedInstOperands,
32640 /* 90063 */ // GIR_Coverage, 4221,
32641 /* 90063 */ GIR_EraseRootFromParent_Done,
32642 /* 90064 */ // Label 2776: @90064
32643 /* 90064 */ GIM_Try, /*On fail goto*//*Label 2777*/ GIMT_Encode4(90116), // Rule ID 4223 //
32644 /* 90069 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32645 /* 90073 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32646 /* 90077 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32647 /* 90081 */ // MIs[1] Operand 1
32648 /* 90081 */ // No operand predicates
32649 /* 90081 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32650 /* 90085 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32651 /* 90087 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32652 /* 90087 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu32),
32653 /* 90090 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32654 /* 90092 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32655 /* 90094 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32656 /* 90096 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32657 /* 90099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32658 /* 90102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32659 /* 90108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32660 /* 90114 */ GIR_RootConstrainSelectedInstOperands,
32661 /* 90115 */ // GIR_Coverage, 4223,
32662 /* 90115 */ GIR_EraseRootFromParent_Done,
32663 /* 90116 */ // Label 2777: @90116
32664 /* 90116 */ GIM_Reject,
32665 /* 90117 */ // Label 2775: @90117
32666 /* 90117 */ GIM_Reject,
32667 /* 90118 */ // Label 2771: @90118
32668 /* 90118 */ GIM_Try, /*On fail goto*//*Label 2778*/ GIMT_Encode4(90240),
32669 /* 90123 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32670 /* 90127 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32671 /* 90131 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32672 /* 90135 */ GIM_Try, /*On fail goto*//*Label 2779*/ GIMT_Encode4(90187), // Rule ID 4229 //
32673 /* 90140 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32674 /* 90144 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32675 /* 90148 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32676 /* 90152 */ // MIs[1] Operand 1
32677 /* 90152 */ // No operand predicates
32678 /* 90152 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32679 /* 90156 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32680 /* 90158 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32681 /* 90158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32bh),
32682 /* 90161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32683 /* 90163 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32684 /* 90165 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32685 /* 90167 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32686 /* 90170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32687 /* 90173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32688 /* 90179 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32689 /* 90185 */ GIR_RootConstrainSelectedInstOperands,
32690 /* 90186 */ // GIR_Coverage, 4229,
32691 /* 90186 */ GIR_EraseRootFromParent_Done,
32692 /* 90187 */ // Label 2779: @90187
32693 /* 90187 */ GIM_Try, /*On fail goto*//*Label 2780*/ GIMT_Encode4(90239), // Rule ID 4231 //
32694 /* 90192 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32695 /* 90196 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32696 /* 90200 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32697 /* 90204 */ // MIs[1] Operand 1
32698 /* 90204 */ // No operand predicates
32699 /* 90204 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32700 /* 90208 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32701 /* 90210 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32702 /* 90210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32th),
32703 /* 90213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32704 /* 90215 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32705 /* 90217 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32706 /* 90219 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32707 /* 90222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32708 /* 90225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32709 /* 90231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32710 /* 90237 */ GIR_RootConstrainSelectedInstOperands,
32711 /* 90238 */ // GIR_Coverage, 4231,
32712 /* 90238 */ GIR_EraseRootFromParent_Done,
32713 /* 90239 */ // Label 2780: @90239
32714 /* 90239 */ GIM_Reject,
32715 /* 90240 */ // Label 2778: @90240
32716 /* 90240 */ GIM_Try, /*On fail goto*//*Label 2781*/ GIMT_Encode4(90362),
32717 /* 90245 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32718 /* 90249 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
32719 /* 90253 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
32720 /* 90257 */ GIM_Try, /*On fail goto*//*Label 2782*/ GIMT_Encode4(90309), // Rule ID 4237 //
32721 /* 90262 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32722 /* 90266 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32723 /* 90270 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32724 /* 90274 */ // MIs[1] Operand 1
32725 /* 90274 */ // No operand predicates
32726 /* 90274 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
32727 /* 90278 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32728 /* 90280 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32729 /* 90280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32bh),
32730 /* 90283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32731 /* 90285 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32732 /* 90287 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32733 /* 90289 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32734 /* 90292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32735 /* 90295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32736 /* 90301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32737 /* 90307 */ GIR_RootConstrainSelectedInstOperands,
32738 /* 90308 */ // GIR_Coverage, 4237,
32739 /* 90308 */ GIR_EraseRootFromParent_Done,
32740 /* 90309 */ // Label 2782: @90309
32741 /* 90309 */ GIM_Try, /*On fail goto*//*Label 2783*/ GIMT_Encode4(90361), // Rule ID 4239 //
32742 /* 90314 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
32743 /* 90318 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32744 /* 90322 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
32745 /* 90326 */ // MIs[1] Operand 1
32746 /* 90326 */ // No operand predicates
32747 /* 90326 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
32748 /* 90330 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32749 /* 90332 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3939:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
32750 /* 90332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32th),
32751 /* 90335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32752 /* 90337 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
32753 /* 90339 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
32754 /* 90341 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32755 /* 90344 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32756 /* 90347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32757 /* 90353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32758 /* 90359 */ GIR_RootConstrainSelectedInstOperands,
32759 /* 90360 */ // GIR_Coverage, 4239,
32760 /* 90360 */ GIR_EraseRootFromParent_Done,
32761 /* 90361 */ // Label 2783: @90361
32762 /* 90361 */ GIM_Reject,
32763 /* 90362 */ // Label 2781: @90362
32764 /* 90362 */ GIM_Reject,
32765 /* 90363 */ // Label 2763: @90363
32766 /* 90363 */ GIM_Reject,
32767 /* 90364 */ // Label 2747: @90364
32768 /* 90364 */ GIM_Reject,
32769 /* 90365 */ // Label 2709: @90365
32770 /* 90365 */ GIM_Reject,
32771 /* 90366 */ // Label 2706: @90366
32772 /* 90366 */ GIM_Reject,
32773 /* 90367 */ // Label 22: @90367
32774 /* 90367 */ GIM_Try, /*On fail goto*//*Label 2784*/ GIMT_Encode4(90422),
32775 /* 90372 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
32776 /* 90375 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_clrex),
32777 /* 90380 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2785*/ GIMT_Encode4(90396), GIMT_Encode2(GIFBS_HasV6K_IsARM), // Rule ID 244 //
32778 /* 90387 */ // (intrinsic_void 3706:{ *:[iPTR] }) => (CLREX)
32779 /* 90387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLREX),
32780 /* 90390 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32781 /* 90394 */ GIR_RootConstrainSelectedInstOperands,
32782 /* 90395 */ // GIR_Coverage, 244,
32783 /* 90395 */ GIR_EraseRootFromParent_Done,
32784 /* 90396 */ // Label 2785: @90396
32785 /* 90396 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2786*/ GIMT_Encode4(90421), GIMT_Encode2(GIFBS_HasV7Clrex_IsThumb), // Rule ID 573 //
32786 /* 90403 */ // (intrinsic_void 3706:{ *:[iPTR] }) => (t2CLREX)
32787 /* 90403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLREX),
32788 /* 90406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
32789 /* 90409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32790 /* 90415 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32791 /* 90419 */ GIR_RootConstrainSelectedInstOperands,
32792 /* 90420 */ // GIR_Coverage, 573,
32793 /* 90420 */ GIR_EraseRootFromParent_Done,
32794 /* 90421 */ // Label 2786: @90421
32795 /* 90421 */ GIM_Reject,
32796 /* 90422 */ // Label 2784: @90422
32797 /* 90422 */ GIM_Try, /*On fail goto*//*Label 2787*/ GIMT_Encode4(91205),
32798 /* 90427 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
32799 /* 90430 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2788*/ GIMT_Encode4(90465), GIMT_Encode2(GIFBS_IsThumb_IsWindows), // Rule ID 343 //
32800 /* 90437 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
32801 /* 90442 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32802 /* 90445 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/1, GIMT_Encode8(249),
32803 /* 90456 */ // (intrinsic_void 4160:{ *:[iPTR] }, 249:{ *:[i32] }) => (t__brkdiv0)
32804 /* 90456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t__brkdiv0),
32805 /* 90459 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
32806 /* 90463 */ GIR_RootConstrainSelectedInstOperands,
32807 /* 90464 */ // GIR_Coverage, 343,
32808 /* 90464 */ GIR_EraseRootFromParent_Done,
32809 /* 90465 */ // Label 2788: @90465
32810 /* 90465 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2789*/ GIMT_Encode4(90516), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2 //
32811 /* 90472 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint),
32812 /* 90477 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32813 /* 90480 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32814 /* 90484 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32815 /* 90488 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239),
32816 /* 90492 */ // MIs[1] Operand 1
32817 /* 90492 */ // No operand predicates
32818 /* 90492 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32819 /* 90494 */ // (intrinsic_void 3724:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (HINT (imm:{ *:[i32] }):$imm)
32820 /* 90494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::HINT),
32821 /* 90497 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32822 /* 90500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
32823 /* 90503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32824 /* 90509 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32825 /* 90514 */ GIR_RootConstrainSelectedInstOperands,
32826 /* 90515 */ // GIR_Coverage, 2,
32827 /* 90515 */ GIR_EraseRootFromParent_Done,
32828 /* 90516 */ // Label 2789: @90516
32829 /* 90516 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2790*/ GIMT_Encode4(90567), GIMT_Encode2(GIFBS_HasV7_IsARM), // Rule ID 10 //
32830 /* 90523 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg),
32831 /* 90528 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32832 /* 90531 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32833 /* 90535 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32834 /* 90539 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
32835 /* 90543 */ // MIs[1] Operand 1
32836 /* 90543 */ // No operand predicates
32837 /* 90543 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32838 /* 90545 */ // (intrinsic_void 3719:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DBG (imm:{ *:[i32] }):$opt)
32839 /* 90545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DBG),
32840 /* 90548 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
32841 /* 90551 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
32842 /* 90554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32843 /* 90560 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32844 /* 90565 */ GIR_RootConstrainSelectedInstOperands,
32845 /* 90566 */ // GIR_Coverage, 10,
32846 /* 90566 */ GIR_EraseRootFromParent_Done,
32847 /* 90567 */ // Label 2790: @90567
32848 /* 90567 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2791*/ GIMT_Encode4(90609), GIMT_Encode2(GIFBS_IsARM), // Rule ID 11 //
32849 /* 90574 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
32850 /* 90579 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32851 /* 90582 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32852 /* 90586 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32853 /* 90590 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
32854 /* 90594 */ // MIs[1] Operand 1
32855 /* 90594 */ // No operand predicates
32856 /* 90594 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32857 /* 90596 */ // (intrinsic_void 4160:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (UDF (imm:{ *:[i32] }):$imm16)
32858 /* 90596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF),
32859 /* 90599 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
32860 /* 90602 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32861 /* 90607 */ GIR_RootConstrainSelectedInstOperands,
32862 /* 90608 */ // GIR_Coverage, 11,
32863 /* 90608 */ GIR_EraseRootFromParent_Done,
32864 /* 90609 */ // Label 2791: @90609
32865 /* 90609 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2792*/ GIMT_Encode4(90651), GIMT_Encode2(GIFBS_HasDB_IsARM), // Rule ID 227 //
32866 /* 90616 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb),
32867 /* 90621 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32868 /* 90624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32869 /* 90628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32870 /* 90632 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
32871 /* 90636 */ // MIs[1] Operand 1
32872 /* 90636 */ // No operand predicates
32873 /* 90636 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32874 /* 90638 */ // (intrinsic_void 3720:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DMB (imm:{ *:[i32] }):$opt)
32875 /* 90638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DMB),
32876 /* 90641 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
32877 /* 90644 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32878 /* 90649 */ GIR_RootConstrainSelectedInstOperands,
32879 /* 90650 */ // GIR_Coverage, 227,
32880 /* 90650 */ GIR_EraseRootFromParent_Done,
32881 /* 90651 */ // Label 2792: @90651
32882 /* 90651 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2793*/ GIMT_Encode4(90693), GIMT_Encode2(GIFBS_HasDB_IsARM), // Rule ID 228 //
32883 /* 90658 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb),
32884 /* 90663 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32885 /* 90666 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32886 /* 90670 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32887 /* 90674 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
32888 /* 90678 */ // MIs[1] Operand 1
32889 /* 90678 */ // No operand predicates
32890 /* 90678 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32891 /* 90680 */ // (intrinsic_void 3721:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DSB (imm:{ *:[i32] }):$opt)
32892 /* 90680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DSB),
32893 /* 90683 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
32894 /* 90686 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32895 /* 90691 */ GIR_RootConstrainSelectedInstOperands,
32896 /* 90692 */ // GIR_Coverage, 228,
32897 /* 90692 */ GIR_EraseRootFromParent_Done,
32898 /* 90693 */ // Label 2793: @90693
32899 /* 90693 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2794*/ GIMT_Encode4(90735), GIMT_Encode2(GIFBS_HasDB_IsARM), // Rule ID 229 //
32900 /* 90700 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb),
32901 /* 90705 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32902 /* 90708 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32903 /* 90712 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32904 /* 90716 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
32905 /* 90720 */ // MIs[1] Operand 1
32906 /* 90720 */ // No operand predicates
32907 /* 90720 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32908 /* 90722 */ // (intrinsic_void 3725:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (ISB (imm:{ *:[i32] }):$opt)
32909 /* 90722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ISB),
32910 /* 90725 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
32911 /* 90728 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32912 /* 90733 */ GIR_RootConstrainSelectedInstOperands,
32913 /* 90734 */ // GIR_Coverage, 229,
32914 /* 90734 */ GIR_EraseRootFromParent_Done,
32915 /* 90735 */ // Label 2794: @90735
32916 /* 90735 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2795*/ GIMT_Encode4(90786), GIMT_Encode2(GIFBS_HasV6M_IsThumb), // Rule ID 275 //
32917 /* 90742 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint),
32918 /* 90747 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32919 /* 90750 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32920 /* 90754 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32921 /* 90758 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
32922 /* 90762 */ // MIs[1] Operand 1
32923 /* 90762 */ // No operand predicates
32924 /* 90762 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32925 /* 90764 */ // (intrinsic_void 3724:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (tHINT (imm:{ *:[i32] }):$imm)
32926 /* 90764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tHINT),
32927 /* 90767 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
32928 /* 90770 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
32929 /* 90773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32930 /* 90779 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32931 /* 90784 */ GIR_RootConstrainSelectedInstOperands,
32932 /* 90785 */ // GIR_Coverage, 275,
32933 /* 90785 */ GIR_EraseRootFromParent_Done,
32934 /* 90786 */ // Label 2795: @90786
32935 /* 90786 */ GIM_Try, /*On fail goto*//*Label 2796*/ GIMT_Encode4(90868),
32936 /* 90791 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
32937 /* 90796 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32938 /* 90799 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2797*/ GIMT_Encode4(90833), GIMT_Encode2(GIFBS_IsThumb), // Rule ID 342 //
32939 /* 90806 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32940 /* 90810 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32941 /* 90814 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255),
32942 /* 90818 */ // MIs[1] Operand 1
32943 /* 90818 */ // No operand predicates
32944 /* 90818 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32945 /* 90820 */ // (intrinsic_void 4160:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$imm8) => (tUDF (imm:{ *:[i32] }):$imm8)
32946 /* 90820 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF),
32947 /* 90823 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8
32948 /* 90826 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32949 /* 90831 */ GIR_RootConstrainSelectedInstOperands,
32950 /* 90832 */ // GIR_Coverage, 342,
32951 /* 90832 */ GIR_EraseRootFromParent_Done,
32952 /* 90833 */ // Label 2797: @90833
32953 /* 90833 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2798*/ GIMT_Encode4(90867), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 493 //
32954 /* 90840 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32955 /* 90844 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32956 /* 90848 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
32957 /* 90852 */ // MIs[1] Operand 1
32958 /* 90852 */ // No operand predicates
32959 /* 90852 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32960 /* 90854 */ // (intrinsic_void 4160:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (t2UDF (imm:{ *:[i32] }):$imm16)
32961 /* 90854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDF),
32962 /* 90857 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
32963 /* 90860 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32964 /* 90865 */ GIR_RootConstrainSelectedInstOperands,
32965 /* 90866 */ // GIR_Coverage, 493,
32966 /* 90866 */ GIR_EraseRootFromParent_Done,
32967 /* 90867 */ // Label 2798: @90867
32968 /* 90867 */ GIM_Reject,
32969 /* 90868 */ // Label 2796: @90868
32970 /* 90868 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2799*/ GIMT_Encode4(90919), GIMT_Encode2(GIFBS_HasDB_IsThumb), // Rule ID 558 //
32971 /* 90875 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb),
32972 /* 90880 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32973 /* 90883 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32974 /* 90887 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32975 /* 90891 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
32976 /* 90895 */ // MIs[1] Operand 1
32977 /* 90895 */ // No operand predicates
32978 /* 90895 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32979 /* 90897 */ // (intrinsic_void 3720:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DMB (imm:{ *:[i32] }):$opt)
32980 /* 90897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DMB),
32981 /* 90900 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
32982 /* 90903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
32983 /* 90906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32984 /* 90912 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
32985 /* 90917 */ GIR_RootConstrainSelectedInstOperands,
32986 /* 90918 */ // GIR_Coverage, 558,
32987 /* 90918 */ GIR_EraseRootFromParent_Done,
32988 /* 90919 */ // Label 2799: @90919
32989 /* 90919 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2800*/ GIMT_Encode4(90970), GIMT_Encode2(GIFBS_HasDB_IsThumb), // Rule ID 559 //
32990 /* 90926 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb),
32991 /* 90931 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
32992 /* 90934 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
32993 /* 90938 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
32994 /* 90942 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
32995 /* 90946 */ // MIs[1] Operand 1
32996 /* 90946 */ // No operand predicates
32997 /* 90946 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
32998 /* 90948 */ // (intrinsic_void 3721:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DSB (imm:{ *:[i32] }):$opt)
32999 /* 90948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DSB),
33000 /* 90951 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
33001 /* 90954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33002 /* 90957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33003 /* 90963 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33004 /* 90968 */ GIR_RootConstrainSelectedInstOperands,
33005 /* 90969 */ // GIR_Coverage, 559,
33006 /* 90969 */ GIR_EraseRootFromParent_Done,
33007 /* 90970 */ // Label 2800: @90970
33008 /* 90970 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2801*/ GIMT_Encode4(91021), GIMT_Encode2(GIFBS_HasDB_IsThumb), // Rule ID 560 //
33009 /* 90977 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb),
33010 /* 90982 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
33011 /* 90985 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33012 /* 90989 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33013 /* 90993 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
33014 /* 90997 */ // MIs[1] Operand 1
33015 /* 90997 */ // No operand predicates
33016 /* 90997 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33017 /* 90999 */ // (intrinsic_void 3725:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2ISB (imm:{ *:[i32] }):$opt)
33018 /* 90999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ISB),
33019 /* 91002 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
33020 /* 91005 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33021 /* 91008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33022 /* 91014 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33023 /* 91019 */ GIR_RootConstrainSelectedInstOperands,
33024 /* 91020 */ // GIR_Coverage, 560,
33025 /* 91020 */ GIR_EraseRootFromParent_Done,
33026 /* 91021 */ // Label 2801: @91021
33027 /* 91021 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2802*/ GIMT_Encode4(91072), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 578 //
33028 /* 91028 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint),
33029 /* 91033 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
33030 /* 91036 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33031 /* 91040 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33032 /* 91044 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239),
33033 /* 91048 */ // MIs[1] Operand 1
33034 /* 91048 */ // No operand predicates
33035 /* 91048 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33036 /* 91050 */ // (intrinsic_void 3724:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (t2HINT (imm:{ *:[i32] }):$imm)
33037 /* 91050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2HINT),
33038 /* 91053 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33039 /* 91056 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33040 /* 91059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33041 /* 91065 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33042 /* 91070 */ GIR_RootConstrainSelectedInstOperands,
33043 /* 91071 */ // GIR_Coverage, 578,
33044 /* 91071 */ GIR_EraseRootFromParent_Done,
33045 /* 91072 */ // Label 2802: @91072
33046 /* 91072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2803*/ GIMT_Encode4(91123), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 579 //
33047 /* 91079 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg),
33048 /* 91084 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
33049 /* 91087 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
33050 /* 91091 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33051 /* 91095 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
33052 /* 91099 */ // MIs[1] Operand 1
33053 /* 91099 */ // No operand predicates
33054 /* 91099 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33055 /* 91101 */ // (intrinsic_void 3719:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DBG (imm:{ *:[i32] }):$opt)
33056 /* 91101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DBG),
33057 /* 91104 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
33058 /* 91107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33059 /* 91110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33060 /* 91116 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33061 /* 91121 */ GIR_RootConstrainSelectedInstOperands,
33062 /* 91122 */ // GIR_Coverage, 579,
33063 /* 91122 */ GIR_EraseRootFromParent_Done,
33064 /* 91123 */ // Label 2803: @91123
33065 /* 91123 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2804*/ GIMT_Encode4(91162), GIMT_Encode2(GIFBS_HasFPRegs), // Rule ID 845 //
33066 /* 91130 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_get_fpscr),
33067 /* 91135 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33068 /* 91138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33069 /* 91142 */ // (intrinsic_w_chain:{ *:[i32] } 3722:{ *:[iPTR] }) => (VMRS:{ *:[i32] })
33070 /* 91142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS),
33071 /* 91145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
33072 /* 91147 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33073 /* 91150 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33074 /* 91156 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33075 /* 91160 */ GIR_RootConstrainSelectedInstOperands,
33076 /* 91161 */ // GIR_Coverage, 845,
33077 /* 91161 */ GIR_EraseRootFromParent_Done,
33078 /* 91162 */ // Label 2804: @91162
33079 /* 91162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2805*/ GIMT_Encode4(91204), GIMT_Encode2(GIFBS_HasFPRegs), // Rule ID 846 //
33080 /* 91169 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_set_fpscr),
33081 /* 91174 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
33082 /* 91177 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33083 /* 91181 */ // (intrinsic_void 4104:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt)
33084 /* 91181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
33085 /* 91184 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt
33086 /* 91186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33087 /* 91189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33088 /* 91195 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
33089 /* 91198 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33090 /* 91202 */ GIR_RootConstrainSelectedInstOperands,
33091 /* 91203 */ // GIR_Coverage, 846,
33092 /* 91203 */ GIR_EraseRootFromParent_Done,
33093 /* 91204 */ // Label 2805: @91204
33094 /* 91204 */ GIM_Reject,
33095 /* 91205 */ // Label 2787: @91205
33096 /* 91205 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2806*/ GIMT_Encode4(91247), GIMT_Encode2(GIFBS_HasLOB_HasV8_1MMainline_IsThumb2), // Rule ID 603 //
33097 /* 91212 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
33098 /* 91215 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::start_loop_iterations),
33099 /* 91220 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33100 /* 91223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33101 /* 91226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRlrRegClassID),
33102 /* 91230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33103 /* 91234 */ // (intrinsic_w_chain:{ *:[i32] } 369:{ *:[iPTR] }, rGPR:{ *:[i32] }:$tc) => (t2DoLoopStart:{ *:[i32] } rGPR:{ *:[i32] }:$tc)
33104 /* 91234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DoLoopStart),
33105 /* 91237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[X]
33106 /* 91239 */ GIR_RootToRootCopy, /*OpIdx*/2, // tc
33107 /* 91241 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33108 /* 91245 */ GIR_RootConstrainSelectedInstOperands,
33109 /* 91246 */ // GIR_Coverage, 603,
33110 /* 91246 */ GIR_EraseRootFromParent_Done,
33111 /* 91247 */ // Label 2806: @91247
33112 /* 91247 */ GIM_Try, /*On fail goto*//*Label 2807*/ GIMT_Encode4(93180),
33113 /* 91252 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
33114 /* 91255 */ GIM_Try, /*On fail goto*//*Label 2808*/ GIMT_Encode4(91455),
33115 /* 91260 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base),
33116 /* 91265 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2811*/ GIMT_Encode4(91454),
33117 /* 91276 */ /*GILLT_v4s32*//*Label 2809*/ GIMT_Encode4(91284),
33118 /* 91280 */ /*GILLT_v2s64*//*Label 2810*/ GIMT_Encode4(91369),
33119 /* 91284 */ // Label 2809: @91284
33120 /* 91284 */ GIM_Try, /*On fail goto*//*Label 2812*/ GIMT_Encode4(91368),
33121 /* 91289 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33122 /* 91292 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33123 /* 91295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33124 /* 91299 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33125 /* 91303 */ GIM_Try, /*On fail goto*//*Label 2813*/ GIMT_Encode4(91335), // Rule ID 5586 //
33126 /* 91308 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33127 /* 91312 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33128 /* 91316 */ // MIs[1] Operand 1
33129 /* 91316 */ // No operand predicates
33130 /* 91316 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33131 /* 91318 */ // (intrinsic_w_chain:{ *:[v4i32] } 3865:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
33132 /* 91318 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi),
33133 /* 91321 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33134 /* 91323 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33135 /* 91325 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33136 /* 91328 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33137 /* 91333 */ GIR_RootConstrainSelectedInstOperands,
33138 /* 91334 */ // GIR_Coverage, 5586,
33139 /* 91334 */ GIR_EraseRootFromParent_Done,
33140 /* 91335 */ // Label 2813: @91335
33141 /* 91335 */ GIM_Try, /*On fail goto*//*Label 2814*/ GIMT_Encode4(91367), // Rule ID 5592 //
33142 /* 91340 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33143 /* 91344 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33144 /* 91348 */ // MIs[1] Operand 1
33145 /* 91348 */ // No operand predicates
33146 /* 91348 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33147 /* 91350 */ // (intrinsic_w_chain:{ *:[v4f32] } 3865:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
33148 /* 91350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi),
33149 /* 91353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33150 /* 91355 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33151 /* 91357 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33152 /* 91360 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33153 /* 91365 */ GIR_RootConstrainSelectedInstOperands,
33154 /* 91366 */ // GIR_Coverage, 5592,
33155 /* 91366 */ GIR_EraseRootFromParent_Done,
33156 /* 91367 */ // Label 2814: @91367
33157 /* 91367 */ GIM_Reject,
33158 /* 91368 */ // Label 2812: @91368
33159 /* 91368 */ GIM_Reject,
33160 /* 91369 */ // Label 2810: @91369
33161 /* 91369 */ GIM_Try, /*On fail goto*//*Label 2815*/ GIMT_Encode4(91453),
33162 /* 91374 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
33163 /* 91377 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33164 /* 91380 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33165 /* 91384 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33166 /* 91388 */ GIM_Try, /*On fail goto*//*Label 2816*/ GIMT_Encode4(91420), // Rule ID 5594 //
33167 /* 91393 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33168 /* 91397 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33169 /* 91401 */ // MIs[1] Operand 1
33170 /* 91401 */ // No operand predicates
33171 /* 91401 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33172 /* 91403 */ // (intrinsic_w_chain:{ *:[v2i64] } 3865:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
33173 /* 91403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi),
33174 /* 91406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33175 /* 91408 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33176 /* 91410 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33177 /* 91413 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33178 /* 91418 */ GIR_RootConstrainSelectedInstOperands,
33179 /* 91419 */ // GIR_Coverage, 5594,
33180 /* 91419 */ GIR_EraseRootFromParent_Done,
33181 /* 91420 */ // Label 2816: @91420
33182 /* 91420 */ GIM_Try, /*On fail goto*//*Label 2817*/ GIMT_Encode4(91452), // Rule ID 5596 //
33183 /* 91425 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33184 /* 91429 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33185 /* 91433 */ // MIs[1] Operand 1
33186 /* 91433 */ // No operand predicates
33187 /* 91433 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33188 /* 91435 */ // (intrinsic_w_chain:{ *:[v2f64] } 3865:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
33189 /* 91435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi),
33190 /* 91438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33191 /* 91440 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33192 /* 91442 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33193 /* 91445 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33194 /* 91450 */ GIR_RootConstrainSelectedInstOperands,
33195 /* 91451 */ // GIR_Coverage, 5596,
33196 /* 91451 */ GIR_EraseRootFromParent_Done,
33197 /* 91452 */ // Label 2817: @91452
33198 /* 91452 */ GIM_Reject,
33199 /* 91453 */ // Label 2815: @91453
33200 /* 91453 */ GIM_Reject,
33201 /* 91454 */ // Label 2811: @91454
33202 /* 91454 */ GIM_Reject,
33203 /* 91455 */ // Label 2808: @91455
33204 /* 91455 */ GIM_Try, /*On fail goto*//*Label 2818*/ GIMT_Encode4(91497), // Rule ID 1927 //
33205 /* 91460 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_space),
33206 /* 91465 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33207 /* 91468 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33208 /* 91471 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33209 /* 91475 */ // MIs[0] size
33210 /* 91475 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
33211 /* 91478 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33212 /* 91482 */ // (intrinsic_w_chain:{ *:[i32] } 4135:{ *:[iPTR] }, (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) => (SPACE:{ *:[i32] } (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn)
33213 /* 91482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SPACE),
33214 /* 91485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33215 /* 91487 */ GIR_RootToRootCopy, /*OpIdx*/2, // size
33216 /* 91489 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
33217 /* 91491 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33218 /* 91495 */ GIR_RootConstrainSelectedInstOperands,
33219 /* 91496 */ // GIR_Coverage, 1927,
33220 /* 91496 */ GIR_EraseRootFromParent_Done,
33221 /* 91497 */ // Label 2818: @91497
33222 /* 91497 */ GIM_Try, /*On fail goto*//*Label 2819*/ GIMT_Encode4(91697),
33223 /* 91502 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base),
33224 /* 91507 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2822*/ GIMT_Encode4(91696),
33225 /* 91518 */ /*GILLT_v4s32*//*Label 2820*/ GIMT_Encode4(91526),
33226 /* 91522 */ /*GILLT_v2s64*//*Label 2821*/ GIMT_Encode4(91611),
33227 /* 91526 */ // Label 2820: @91526
33228 /* 91526 */ GIM_Try, /*On fail goto*//*Label 2823*/ GIMT_Encode4(91610),
33229 /* 91531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33230 /* 91534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33231 /* 91537 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33232 /* 91541 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33233 /* 91545 */ GIM_Try, /*On fail goto*//*Label 2824*/ GIMT_Encode4(91577), // Rule ID 5588 //
33234 /* 91550 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33235 /* 91554 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33236 /* 91558 */ // MIs[1] Operand 1
33237 /* 91558 */ // No operand predicates
33238 /* 91558 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33239 /* 91560 */ // (intrinsic_void 3947:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
33240 /* 91560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi),
33241 /* 91563 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
33242 /* 91565 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
33243 /* 91567 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33244 /* 91570 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33245 /* 91575 */ GIR_RootConstrainSelectedInstOperands,
33246 /* 91576 */ // GIR_Coverage, 5588,
33247 /* 91576 */ GIR_EraseRootFromParent_Done,
33248 /* 91577 */ // Label 2824: @91577
33249 /* 91577 */ GIM_Try, /*On fail goto*//*Label 2825*/ GIMT_Encode4(91609), // Rule ID 5598 //
33250 /* 91582 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33251 /* 91586 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33252 /* 91590 */ // MIs[1] Operand 1
33253 /* 91590 */ // No operand predicates
33254 /* 91590 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33255 /* 91592 */ // (intrinsic_void 3947:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
33256 /* 91592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi),
33257 /* 91595 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
33258 /* 91597 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
33259 /* 91599 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33260 /* 91602 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33261 /* 91607 */ GIR_RootConstrainSelectedInstOperands,
33262 /* 91608 */ // GIR_Coverage, 5598,
33263 /* 91608 */ GIR_EraseRootFromParent_Done,
33264 /* 91609 */ // Label 2825: @91609
33265 /* 91609 */ GIM_Reject,
33266 /* 91610 */ // Label 2823: @91610
33267 /* 91610 */ GIM_Reject,
33268 /* 91611 */ // Label 2821: @91611
33269 /* 91611 */ GIM_Try, /*On fail goto*//*Label 2826*/ GIMT_Encode4(91695),
33270 /* 91616 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33271 /* 91619 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
33272 /* 91622 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33273 /* 91626 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33274 /* 91630 */ GIM_Try, /*On fail goto*//*Label 2827*/ GIMT_Encode4(91662), // Rule ID 5602 //
33275 /* 91635 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33276 /* 91639 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33277 /* 91643 */ // MIs[1] Operand 1
33278 /* 91643 */ // No operand predicates
33279 /* 91643 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33280 /* 91645 */ // (intrinsic_void 3947:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
33281 /* 91645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi),
33282 /* 91648 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
33283 /* 91650 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
33284 /* 91652 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33285 /* 91655 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33286 /* 91660 */ GIR_RootConstrainSelectedInstOperands,
33287 /* 91661 */ // GIR_Coverage, 5602,
33288 /* 91661 */ GIR_EraseRootFromParent_Done,
33289 /* 91662 */ // Label 2827: @91662
33290 /* 91662 */ GIM_Try, /*On fail goto*//*Label 2828*/ GIMT_Encode4(91694), // Rule ID 5606 //
33291 /* 91667 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
33292 /* 91671 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33293 /* 91675 */ // MIs[1] Operand 1
33294 /* 91675 */ // No operand predicates
33295 /* 91675 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33296 /* 91677 */ // (intrinsic_void 3947:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
33297 /* 91677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi),
33298 /* 91680 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
33299 /* 91682 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
33300 /* 91684 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33301 /* 91687 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33302 /* 91692 */ GIR_RootConstrainSelectedInstOperands,
33303 /* 91693 */ // GIR_Coverage, 5606,
33304 /* 91693 */ GIR_EraseRootFromParent_Done,
33305 /* 91694 */ // Label 2828: @91694
33306 /* 91694 */ GIM_Reject,
33307 /* 91695 */ // Label 2826: @91695
33308 /* 91695 */ GIM_Reject,
33309 /* 91696 */ // Label 2822: @91696
33310 /* 91696 */ GIM_Reject,
33311 /* 91697 */ // Label 2819: @91697
33312 /* 91697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2829*/ GIMT_Encode4(91754), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 3 //
33313 /* 91704 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel),
33314 /* 91709 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33315 /* 91712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33316 /* 91715 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33317 /* 91718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33318 /* 91722 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33319 /* 91726 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33320 /* 91730 */ // (intrinsic_w_chain:{ *:[i32] } 4103:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
33321 /* 91730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SEL),
33322 /* 91733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33323 /* 91735 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33324 /* 91737 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33325 /* 91739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33326 /* 91742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33327 /* 91748 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33328 /* 91752 */ GIR_RootConstrainSelectedInstOperands,
33329 /* 91753 */ // GIR_Coverage, 3,
33330 /* 91753 */ GIR_EraseRootFromParent_Done,
33331 /* 91754 */ // Label 2829: @91754
33332 /* 91754 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2830*/ GIMT_Encode4(91811), GIMT_Encode2(GIFBS_IsARM), // Rule ID 120 //
33333 /* 91761 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx),
33334 /* 91766 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33335 /* 91769 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33336 /* 91772 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33337 /* 91775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33338 /* 91779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33339 /* 91783 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33340 /* 91787 */ // (intrinsic_w_chain:{ *:[i32] } 4102:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33341 /* 91787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SASX),
33342 /* 91790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33343 /* 91792 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33344 /* 91794 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33345 /* 91796 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33346 /* 91799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33347 /* 91805 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33348 /* 91809 */ GIR_RootConstrainSelectedInstOperands,
33349 /* 91810 */ // GIR_Coverage, 120,
33350 /* 91810 */ GIR_EraseRootFromParent_Done,
33351 /* 91811 */ // Label 2830: @91811
33352 /* 91811 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2831*/ GIMT_Encode4(91868), GIMT_Encode2(GIFBS_IsARM), // Rule ID 121 //
33353 /* 91818 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16),
33354 /* 91823 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33355 /* 91826 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33356 /* 91829 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33357 /* 91832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33358 /* 91836 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33359 /* 91840 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33360 /* 91844 */ // (intrinsic_w_chain:{ *:[i32] } 4100:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33361 /* 91844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD16),
33362 /* 91847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33363 /* 91849 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33364 /* 91851 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33365 /* 91853 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33366 /* 91856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33367 /* 91862 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33368 /* 91866 */ GIR_RootConstrainSelectedInstOperands,
33369 /* 91867 */ // GIR_Coverage, 121,
33370 /* 91867 */ GIR_EraseRootFromParent_Done,
33371 /* 91868 */ // Label 2831: @91868
33372 /* 91868 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2832*/ GIMT_Encode4(91925), GIMT_Encode2(GIFBS_IsARM), // Rule ID 122 //
33373 /* 91875 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8),
33374 /* 91880 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33375 /* 91883 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33376 /* 91886 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33377 /* 91889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33378 /* 91893 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33379 /* 91897 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33380 /* 91901 */ // (intrinsic_w_chain:{ *:[i32] } 4101:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33381 /* 91901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD8),
33382 /* 91904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33383 /* 91906 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33384 /* 91908 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33385 /* 91910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33386 /* 91913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33387 /* 91919 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33388 /* 91923 */ GIR_RootConstrainSelectedInstOperands,
33389 /* 91924 */ // GIR_Coverage, 122,
33390 /* 91924 */ GIR_EraseRootFromParent_Done,
33391 /* 91925 */ // Label 2832: @91925
33392 /* 91925 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2833*/ GIMT_Encode4(91982), GIMT_Encode2(GIFBS_IsARM), // Rule ID 123 //
33393 /* 91932 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax),
33394 /* 91937 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33395 /* 91940 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33396 /* 91943 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33397 /* 91946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33398 /* 91950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33399 /* 91954 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33400 /* 91958 */ // (intrinsic_w_chain:{ *:[i32] } 4138:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33401 /* 91958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSAX),
33402 /* 91961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33403 /* 91963 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33404 /* 91965 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33405 /* 91967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33406 /* 91970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33407 /* 91976 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33408 /* 91980 */ GIR_RootConstrainSelectedInstOperands,
33409 /* 91981 */ // GIR_Coverage, 123,
33410 /* 91981 */ GIR_EraseRootFromParent_Done,
33411 /* 91982 */ // Label 2833: @91982
33412 /* 91982 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2834*/ GIMT_Encode4(92039), GIMT_Encode2(GIFBS_IsARM), // Rule ID 124 //
33413 /* 91989 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16),
33414 /* 91994 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33415 /* 91997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33416 /* 92000 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33417 /* 92003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33418 /* 92007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33419 /* 92011 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33420 /* 92015 */ // (intrinsic_w_chain:{ *:[i32] } 4139:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33421 /* 92015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB16),
33422 /* 92018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33423 /* 92020 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33424 /* 92022 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33425 /* 92024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33426 /* 92027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33427 /* 92033 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33428 /* 92037 */ GIR_RootConstrainSelectedInstOperands,
33429 /* 92038 */ // GIR_Coverage, 124,
33430 /* 92038 */ GIR_EraseRootFromParent_Done,
33431 /* 92039 */ // Label 2834: @92039
33432 /* 92039 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2835*/ GIMT_Encode4(92096), GIMT_Encode2(GIFBS_IsARM), // Rule ID 125 //
33433 /* 92046 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8),
33434 /* 92051 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33435 /* 92054 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33436 /* 92057 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33437 /* 92060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33438 /* 92064 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33439 /* 92068 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33440 /* 92072 */ // (intrinsic_w_chain:{ *:[i32] } 4140:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33441 /* 92072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB8),
33442 /* 92075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33443 /* 92077 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33444 /* 92079 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33445 /* 92081 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33446 /* 92084 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33447 /* 92090 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33448 /* 92094 */ GIR_RootConstrainSelectedInstOperands,
33449 /* 92095 */ // GIR_Coverage, 125,
33450 /* 92095 */ GIR_EraseRootFromParent_Done,
33451 /* 92096 */ // Label 2835: @92096
33452 /* 92096 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2836*/ GIMT_Encode4(92153), GIMT_Encode2(GIFBS_IsARM), // Rule ID 126 //
33453 /* 92103 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx),
33454 /* 92108 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33455 /* 92111 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33456 /* 92114 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33457 /* 92117 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33458 /* 92121 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33459 /* 92125 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33460 /* 92129 */ // (intrinsic_w_chain:{ *:[i32] } 4153:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33461 /* 92129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UASX),
33462 /* 92132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33463 /* 92134 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33464 /* 92136 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33465 /* 92138 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33466 /* 92141 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33467 /* 92147 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33468 /* 92151 */ GIR_RootConstrainSelectedInstOperands,
33469 /* 92152 */ // GIR_Coverage, 126,
33470 /* 92152 */ GIR_EraseRootFromParent_Done,
33471 /* 92153 */ // Label 2836: @92153
33472 /* 92153 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2837*/ GIMT_Encode4(92210), GIMT_Encode2(GIFBS_IsARM), // Rule ID 127 //
33473 /* 92160 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16),
33474 /* 92165 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33475 /* 92168 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33476 /* 92171 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33477 /* 92174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33478 /* 92178 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33479 /* 92182 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33480 /* 92186 */ // (intrinsic_w_chain:{ *:[i32] } 4151:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33481 /* 92186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD16),
33482 /* 92189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33483 /* 92191 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33484 /* 92193 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33485 /* 92195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33486 /* 92198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33487 /* 92204 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33488 /* 92208 */ GIR_RootConstrainSelectedInstOperands,
33489 /* 92209 */ // GIR_Coverage, 127,
33490 /* 92209 */ GIR_EraseRootFromParent_Done,
33491 /* 92210 */ // Label 2837: @92210
33492 /* 92210 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2838*/ GIMT_Encode4(92267), GIMT_Encode2(GIFBS_IsARM), // Rule ID 128 //
33493 /* 92217 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8),
33494 /* 92222 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33495 /* 92225 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33496 /* 92228 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33497 /* 92231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33498 /* 92235 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33499 /* 92239 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33500 /* 92243 */ // (intrinsic_w_chain:{ *:[i32] } 4152:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33501 /* 92243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD8),
33502 /* 92246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33503 /* 92248 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33504 /* 92250 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33505 /* 92252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33506 /* 92255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33507 /* 92261 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33508 /* 92265 */ GIR_RootConstrainSelectedInstOperands,
33509 /* 92266 */ // GIR_Coverage, 128,
33510 /* 92266 */ GIR_EraseRootFromParent_Done,
33511 /* 92267 */ // Label 2838: @92267
33512 /* 92267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2839*/ GIMT_Encode4(92324), GIMT_Encode2(GIFBS_IsARM), // Rule ID 129 //
33513 /* 92274 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax),
33514 /* 92279 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33515 /* 92282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33516 /* 92285 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33517 /* 92288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33518 /* 92292 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33519 /* 92296 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33520 /* 92300 */ // (intrinsic_w_chain:{ *:[i32] } 4171:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33521 /* 92300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAX),
33522 /* 92303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33523 /* 92305 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33524 /* 92307 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33525 /* 92309 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33526 /* 92312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33527 /* 92318 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33528 /* 92322 */ GIR_RootConstrainSelectedInstOperands,
33529 /* 92323 */ // GIR_Coverage, 129,
33530 /* 92323 */ GIR_EraseRootFromParent_Done,
33531 /* 92324 */ // Label 2839: @92324
33532 /* 92324 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2840*/ GIMT_Encode4(92381), GIMT_Encode2(GIFBS_IsARM), // Rule ID 130 //
33533 /* 92331 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16),
33534 /* 92336 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33535 /* 92339 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33536 /* 92342 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33537 /* 92345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33538 /* 92349 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33539 /* 92353 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33540 /* 92357 */ // (intrinsic_w_chain:{ *:[i32] } 4172:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33541 /* 92357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB16),
33542 /* 92360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33543 /* 92362 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33544 /* 92364 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33545 /* 92366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33546 /* 92369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33547 /* 92375 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33548 /* 92379 */ GIR_RootConstrainSelectedInstOperands,
33549 /* 92380 */ // GIR_Coverage, 130,
33550 /* 92380 */ GIR_EraseRootFromParent_Done,
33551 /* 92381 */ // Label 2840: @92381
33552 /* 92381 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2841*/ GIMT_Encode4(92438), GIMT_Encode2(GIFBS_IsARM), // Rule ID 131 //
33553 /* 92388 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8),
33554 /* 92393 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33555 /* 92396 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33556 /* 92399 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33557 /* 92402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33558 /* 92406 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33559 /* 92410 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
33560 /* 92414 */ // (intrinsic_w_chain:{ *:[i32] } 4173:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
33561 /* 92414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB8),
33562 /* 92417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33563 /* 92419 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33564 /* 92421 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33565 /* 92423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33566 /* 92426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33567 /* 92432 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33568 /* 92436 */ GIR_RootConstrainSelectedInstOperands,
33569 /* 92437 */ // GIR_Coverage, 131,
33570 /* 92437 */ GIR_EraseRootFromParent_Done,
33571 /* 92438 */ // Label 2841: @92438
33572 /* 92438 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2842*/ GIMT_Encode4(92495), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 430 //
33573 /* 92445 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel),
33574 /* 92450 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33575 /* 92453 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33576 /* 92456 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33577 /* 92459 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33578 /* 92463 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33579 /* 92467 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33580 /* 92471 */ // (intrinsic_w_chain:{ *:[i32] } 4103:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (t2SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
33581 /* 92471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SEL),
33582 /* 92474 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33583 /* 92476 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33584 /* 92478 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33585 /* 92480 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33586 /* 92483 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33587 /* 92489 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33588 /* 92493 */ GIR_RootConstrainSelectedInstOperands,
33589 /* 92494 */ // GIR_Coverage, 430,
33590 /* 92494 */ GIR_EraseRootFromParent_Done,
33591 /* 92495 */ // Label 2842: @92495
33592 /* 92495 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2843*/ GIMT_Encode4(92552), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 443 //
33593 /* 92502 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx),
33594 /* 92507 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33595 /* 92510 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33596 /* 92513 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33597 /* 92516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33598 /* 92520 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33599 /* 92524 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33600 /* 92528 */ // (intrinsic_w_chain:{ *:[i32] } 4102:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33601 /* 92528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SASX),
33602 /* 92531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33603 /* 92533 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33604 /* 92535 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33605 /* 92537 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33606 /* 92540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33607 /* 92546 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33608 /* 92550 */ GIR_RootConstrainSelectedInstOperands,
33609 /* 92551 */ // GIR_Coverage, 443,
33610 /* 92551 */ GIR_EraseRootFromParent_Done,
33611 /* 92552 */ // Label 2843: @92552
33612 /* 92552 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2844*/ GIMT_Encode4(92609), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 444 //
33613 /* 92559 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16),
33614 /* 92564 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33615 /* 92567 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33616 /* 92570 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33617 /* 92573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33618 /* 92577 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33619 /* 92581 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33620 /* 92585 */ // (intrinsic_w_chain:{ *:[i32] } 4100:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33621 /* 92585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD16),
33622 /* 92588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33623 /* 92590 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33624 /* 92592 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33625 /* 92594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33626 /* 92597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33627 /* 92603 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33628 /* 92607 */ GIR_RootConstrainSelectedInstOperands,
33629 /* 92608 */ // GIR_Coverage, 444,
33630 /* 92608 */ GIR_EraseRootFromParent_Done,
33631 /* 92609 */ // Label 2844: @92609
33632 /* 92609 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2845*/ GIMT_Encode4(92666), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 445 //
33633 /* 92616 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8),
33634 /* 92621 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33635 /* 92624 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33636 /* 92627 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33637 /* 92630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33638 /* 92634 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33639 /* 92638 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33640 /* 92642 */ // (intrinsic_w_chain:{ *:[i32] } 4101:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33641 /* 92642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD8),
33642 /* 92645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33643 /* 92647 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33644 /* 92649 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33645 /* 92651 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33646 /* 92654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33647 /* 92660 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33648 /* 92664 */ GIR_RootConstrainSelectedInstOperands,
33649 /* 92665 */ // GIR_Coverage, 445,
33650 /* 92665 */ GIR_EraseRootFromParent_Done,
33651 /* 92666 */ // Label 2845: @92666
33652 /* 92666 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2846*/ GIMT_Encode4(92723), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 446 //
33653 /* 92673 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax),
33654 /* 92678 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33655 /* 92681 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33656 /* 92684 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33657 /* 92687 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33658 /* 92691 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33659 /* 92695 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33660 /* 92699 */ // (intrinsic_w_chain:{ *:[i32] } 4138:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33661 /* 92699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSAX),
33662 /* 92702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33663 /* 92704 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33664 /* 92706 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33665 /* 92708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33666 /* 92711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33667 /* 92717 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33668 /* 92721 */ GIR_RootConstrainSelectedInstOperands,
33669 /* 92722 */ // GIR_Coverage, 446,
33670 /* 92722 */ GIR_EraseRootFromParent_Done,
33671 /* 92723 */ // Label 2846: @92723
33672 /* 92723 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2847*/ GIMT_Encode4(92780), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 447 //
33673 /* 92730 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16),
33674 /* 92735 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33675 /* 92738 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33676 /* 92741 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33677 /* 92744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33678 /* 92748 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33679 /* 92752 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33680 /* 92756 */ // (intrinsic_w_chain:{ *:[i32] } 4139:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33681 /* 92756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB16),
33682 /* 92759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33683 /* 92761 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33684 /* 92763 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33685 /* 92765 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33686 /* 92768 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33687 /* 92774 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33688 /* 92778 */ GIR_RootConstrainSelectedInstOperands,
33689 /* 92779 */ // GIR_Coverage, 447,
33690 /* 92779 */ GIR_EraseRootFromParent_Done,
33691 /* 92780 */ // Label 2847: @92780
33692 /* 92780 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2848*/ GIMT_Encode4(92837), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 448 //
33693 /* 92787 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8),
33694 /* 92792 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33695 /* 92795 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33696 /* 92798 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33697 /* 92801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33698 /* 92805 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33699 /* 92809 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33700 /* 92813 */ // (intrinsic_w_chain:{ *:[i32] } 4140:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33701 /* 92813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB8),
33702 /* 92816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33703 /* 92818 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33704 /* 92820 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33705 /* 92822 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33706 /* 92825 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33707 /* 92831 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33708 /* 92835 */ GIR_RootConstrainSelectedInstOperands,
33709 /* 92836 */ // GIR_Coverage, 448,
33710 /* 92836 */ GIR_EraseRootFromParent_Done,
33711 /* 92837 */ // Label 2848: @92837
33712 /* 92837 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2849*/ GIMT_Encode4(92894), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 449 //
33713 /* 92844 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx),
33714 /* 92849 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33715 /* 92852 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33716 /* 92855 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33717 /* 92858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33718 /* 92862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33719 /* 92866 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33720 /* 92870 */ // (intrinsic_w_chain:{ *:[i32] } 4153:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33721 /* 92870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UASX),
33722 /* 92873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33723 /* 92875 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33724 /* 92877 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33725 /* 92879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33726 /* 92882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33727 /* 92888 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33728 /* 92892 */ GIR_RootConstrainSelectedInstOperands,
33729 /* 92893 */ // GIR_Coverage, 449,
33730 /* 92893 */ GIR_EraseRootFromParent_Done,
33731 /* 92894 */ // Label 2849: @92894
33732 /* 92894 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2850*/ GIMT_Encode4(92951), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 450 //
33733 /* 92901 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16),
33734 /* 92906 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33735 /* 92909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33736 /* 92912 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33737 /* 92915 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33738 /* 92919 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33739 /* 92923 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33740 /* 92927 */ // (intrinsic_w_chain:{ *:[i32] } 4151:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33741 /* 92927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD16),
33742 /* 92930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33743 /* 92932 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33744 /* 92934 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33745 /* 92936 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33746 /* 92939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33747 /* 92945 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33748 /* 92949 */ GIR_RootConstrainSelectedInstOperands,
33749 /* 92950 */ // GIR_Coverage, 450,
33750 /* 92950 */ GIR_EraseRootFromParent_Done,
33751 /* 92951 */ // Label 2850: @92951
33752 /* 92951 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2851*/ GIMT_Encode4(93008), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 451 //
33753 /* 92958 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8),
33754 /* 92963 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33755 /* 92966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33756 /* 92969 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33757 /* 92972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33758 /* 92976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33759 /* 92980 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33760 /* 92984 */ // (intrinsic_w_chain:{ *:[i32] } 4152:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33761 /* 92984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD8),
33762 /* 92987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33763 /* 92989 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33764 /* 92991 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33765 /* 92993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33766 /* 92996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33767 /* 93002 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33768 /* 93006 */ GIR_RootConstrainSelectedInstOperands,
33769 /* 93007 */ // GIR_Coverage, 451,
33770 /* 93007 */ GIR_EraseRootFromParent_Done,
33771 /* 93008 */ // Label 2851: @93008
33772 /* 93008 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2852*/ GIMT_Encode4(93065), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 452 //
33773 /* 93015 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax),
33774 /* 93020 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33775 /* 93023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33776 /* 93026 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33777 /* 93029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33778 /* 93033 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33779 /* 93037 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33780 /* 93041 */ // (intrinsic_w_chain:{ *:[i32] } 4171:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33781 /* 93041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAX),
33782 /* 93044 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33783 /* 93046 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33784 /* 93048 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33785 /* 93050 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33786 /* 93053 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33787 /* 93059 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33788 /* 93063 */ GIR_RootConstrainSelectedInstOperands,
33789 /* 93064 */ // GIR_Coverage, 452,
33790 /* 93064 */ GIR_EraseRootFromParent_Done,
33791 /* 93065 */ // Label 2852: @93065
33792 /* 93065 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2853*/ GIMT_Encode4(93122), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 453 //
33793 /* 93072 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16),
33794 /* 93077 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33795 /* 93080 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33796 /* 93083 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33797 /* 93086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33798 /* 93090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33799 /* 93094 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33800 /* 93098 */ // (intrinsic_w_chain:{ *:[i32] } 4172:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33801 /* 93098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB16),
33802 /* 93101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33803 /* 93103 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33804 /* 93105 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33805 /* 93107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33806 /* 93110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33807 /* 93116 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33808 /* 93120 */ GIR_RootConstrainSelectedInstOperands,
33809 /* 93121 */ // GIR_Coverage, 453,
33810 /* 93121 */ GIR_EraseRootFromParent_Done,
33811 /* 93122 */ // Label 2853: @93122
33812 /* 93122 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2854*/ GIMT_Encode4(93179), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 454 //
33813 /* 93129 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8),
33814 /* 93134 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33815 /* 93137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33816 /* 93140 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33817 /* 93143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33818 /* 93147 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33819 /* 93151 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
33820 /* 93155 */ // (intrinsic_w_chain:{ *:[i32] } 4173:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
33821 /* 93155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB8),
33822 /* 93158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
33823 /* 93160 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
33824 /* 93162 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
33825 /* 93164 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33826 /* 93167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33827 /* 93173 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33828 /* 93177 */ GIR_RootConstrainSelectedInstOperands,
33829 /* 93178 */ // GIR_Coverage, 454,
33830 /* 93178 */ GIR_EraseRootFromParent_Done,
33831 /* 93179 */ // Label 2854: @93179
33832 /* 93179 */ GIM_Reject,
33833 /* 93180 */ // Label 2807: @93180
33834 /* 93180 */ GIM_Try, /*On fail goto*//*Label 2855*/ GIMT_Encode4(93405),
33835 /* 93185 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
33836 /* 93188 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base_wb),
33837 /* 93193 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(14), /*)*//*default:*//*Label 2858*/ GIMT_Encode4(93404),
33838 /* 93204 */ /*GILLT_v4s32*//*Label 2856*/ GIMT_Encode4(93212),
33839 /* 93208 */ /*GILLT_v2s64*//*Label 2857*/ GIMT_Encode4(93308),
33840 /* 93212 */ // Label 2856: @93212
33841 /* 93212 */ GIM_Try, /*On fail goto*//*Label 2859*/ GIMT_Encode4(93307),
33842 /* 93217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33843 /* 93220 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33844 /* 93223 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33845 /* 93226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33846 /* 93230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33847 /* 93234 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33848 /* 93238 */ GIM_Try, /*On fail goto*//*Label 2860*/ GIMT_Encode4(93272), // Rule ID 5590 //
33849 /* 93243 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33850 /* 93247 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33851 /* 93251 */ // MIs[1] Operand 1
33852 /* 93251 */ // No operand predicates
33853 /* 93251 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33854 /* 93253 */ // (intrinsic_w_chain:{ *:[v4i32] } 3949:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
33855 /* 93253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre),
33856 /* 93256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
33857 /* 93258 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
33858 /* 93260 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33859 /* 93262 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33860 /* 93265 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33861 /* 93270 */ GIR_RootConstrainSelectedInstOperands,
33862 /* 93271 */ // GIR_Coverage, 5590,
33863 /* 93271 */ GIR_EraseRootFromParent_Done,
33864 /* 93272 */ // Label 2860: @93272
33865 /* 93272 */ GIM_Try, /*On fail goto*//*Label 2861*/ GIMT_Encode4(93306), // Rule ID 5600 //
33866 /* 93277 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33867 /* 93281 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33868 /* 93285 */ // MIs[1] Operand 1
33869 /* 93285 */ // No operand predicates
33870 /* 93285 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33871 /* 93287 */ // (intrinsic_w_chain:{ *:[v4i32] } 3949:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
33872 /* 93287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre),
33873 /* 93290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
33874 /* 93292 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
33875 /* 93294 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33876 /* 93296 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33877 /* 93299 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33878 /* 93304 */ GIR_RootConstrainSelectedInstOperands,
33879 /* 93305 */ // GIR_Coverage, 5600,
33880 /* 93305 */ GIR_EraseRootFromParent_Done,
33881 /* 93306 */ // Label 2861: @93306
33882 /* 93306 */ GIM_Reject,
33883 /* 93307 */ // Label 2859: @93307
33884 /* 93307 */ GIM_Reject,
33885 /* 93308 */ // Label 2857: @93308
33886 /* 93308 */ GIM_Try, /*On fail goto*//*Label 2862*/ GIMT_Encode4(93403),
33887 /* 93313 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
33888 /* 93316 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33889 /* 93319 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
33890 /* 93322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33891 /* 93326 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33892 /* 93330 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33893 /* 93334 */ GIM_Try, /*On fail goto*//*Label 2863*/ GIMT_Encode4(93368), // Rule ID 5604 //
33894 /* 93339 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33895 /* 93343 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33896 /* 93347 */ // MIs[1] Operand 1
33897 /* 93347 */ // No operand predicates
33898 /* 93347 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33899 /* 93349 */ // (intrinsic_w_chain:{ *:[v2i64] } 3949:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
33900 /* 93349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre),
33901 /* 93352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
33902 /* 93354 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
33903 /* 93356 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33904 /* 93358 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33905 /* 93361 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33906 /* 93366 */ GIR_RootConstrainSelectedInstOperands,
33907 /* 93367 */ // GIR_Coverage, 5604,
33908 /* 93367 */ GIR_EraseRootFromParent_Done,
33909 /* 93368 */ // Label 2863: @93368
33910 /* 93368 */ GIM_Try, /*On fail goto*//*Label 2864*/ GIMT_Encode4(93402), // Rule ID 5608 //
33911 /* 93373 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
33912 /* 93377 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33913 /* 93381 */ // MIs[1] Operand 1
33914 /* 93381 */ // No operand predicates
33915 /* 93381 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33916 /* 93383 */ // (intrinsic_w_chain:{ *:[v2i64] } 3949:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
33917 /* 93383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre),
33918 /* 93386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
33919 /* 93388 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
33920 /* 93390 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
33921 /* 93392 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
33922 /* 93395 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
33923 /* 93400 */ GIR_RootConstrainSelectedInstOperands,
33924 /* 93401 */ // GIR_Coverage, 5608,
33925 /* 93401 */ GIR_EraseRootFromParent_Done,
33926 /* 93402 */ // Label 2864: @93402
33927 /* 93402 */ GIM_Reject,
33928 /* 93403 */ // Label 2862: @93403
33929 /* 93403 */ GIM_Reject,
33930 /* 93404 */ // Label 2858: @93404
33931 /* 93404 */ GIM_Reject,
33932 /* 93405 */ // Label 2855: @93405
33933 /* 93405 */ GIM_Try, /*On fail goto*//*Label 2865*/ GIMT_Encode4(94241),
33934 /* 93410 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
33935 /* 93413 */ GIM_Try, /*On fail goto*//*Label 2866*/ GIMT_Encode4(93997),
33936 /* 93418 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
33937 /* 93423 */ GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 2871*/ GIMT_Encode4(93996),
33938 /* 93434 */ /*GILLT_v16s8*//*Label 2867*/ GIMT_Encode4(93458), GIMT_Encode4(0),
33939 /* 93442 */ /*GILLT_v8s16*//*Label 2868*/ GIMT_Encode4(93512), GIMT_Encode4(0),
33940 /* 93450 */ /*GILLT_v4s32*//*Label 2869*/ GIMT_Encode4(93688),
33941 /* 93454 */ /*GILLT_v2s64*//*Label 2870*/ GIMT_Encode4(93912),
33942 /* 93458 */ // Label 2867: @93458
33943 /* 93458 */ GIM_Try, /*On fail goto*//*Label 2872*/ GIMT_Encode4(93511), // Rule ID 5482 //
33944 /* 93463 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33945 /* 93466 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33946 /* 93469 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33947 /* 93472 */ // MIs[0] base
33948 /* 93472 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
33949 /* 93476 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33950 /* 93480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33951 /* 93484 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33952 /* 93488 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
33953 /* 93492 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33954 /* 93496 */ // (intrinsic_void 3951:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, MQPR:{ *:[v16i8] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB8_rq MQPR:{ *:[v16i8] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
33955 /* 93496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB8_rq),
33956 /* 93499 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
33957 /* 93501 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
33958 /* 93503 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
33959 /* 93505 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33960 /* 93509 */ GIR_RootConstrainSelectedInstOperands,
33961 /* 93510 */ // GIR_Coverage, 5482,
33962 /* 93510 */ GIR_EraseRootFromParent_Done,
33963 /* 93511 */ // Label 2872: @93511
33964 /* 93511 */ GIM_Reject,
33965 /* 93512 */ // Label 2868: @93512
33966 /* 93512 */ GIM_Try, /*On fail goto*//*Label 2873*/ GIMT_Encode4(93687),
33967 /* 93517 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33968 /* 93520 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33969 /* 93523 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33970 /* 93526 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
33971 /* 93530 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
33972 /* 93534 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33973 /* 93538 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33974 /* 93542 */ GIM_Try, /*On fail goto*//*Label 2874*/ GIMT_Encode4(93600),
33975 /* 93547 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
33976 /* 93551 */ GIM_Try, /*On fail goto*//*Label 2875*/ GIMT_Encode4(93575), // Rule ID 5478 //
33977 /* 93556 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33978 /* 93560 */ // (intrinsic_void 3951:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
33979 /* 93560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u),
33980 /* 93563 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
33981 /* 93565 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
33982 /* 93567 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
33983 /* 93569 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33984 /* 93573 */ GIR_RootConstrainSelectedInstOperands,
33985 /* 93574 */ // GIR_Coverage, 5478,
33986 /* 93574 */ GIR_EraseRootFromParent_Done,
33987 /* 93575 */ // Label 2875: @93575
33988 /* 93575 */ GIM_Try, /*On fail goto*//*Label 2876*/ GIMT_Encode4(93599), // Rule ID 5479 //
33989 /* 93580 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33990 /* 93584 */ // (intrinsic_void 3951:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
33991 /* 93584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq),
33992 /* 93587 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
33993 /* 93589 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
33994 /* 93591 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
33995 /* 93593 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
33996 /* 93597 */ GIR_RootConstrainSelectedInstOperands,
33997 /* 93598 */ // GIR_Coverage, 5479,
33998 /* 93598 */ GIR_EraseRootFromParent_Done,
33999 /* 93599 */ // Label 2876: @93599
34000 /* 93599 */ GIM_Reject,
34001 /* 93600 */ // Label 2874: @93600
34002 /* 93600 */ GIM_Try, /*On fail goto*//*Label 2877*/ GIMT_Encode4(93628), // Rule ID 5562 //
34003 /* 93605 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
34004 /* 93609 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34005 /* 93613 */ // (intrinsic_void 3951:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34006 /* 93613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB16_rq),
34007 /* 93616 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34008 /* 93618 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34009 /* 93620 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34010 /* 93622 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34011 /* 93626 */ GIR_RootConstrainSelectedInstOperands,
34012 /* 93627 */ // GIR_Coverage, 5562,
34013 /* 93627 */ GIR_EraseRootFromParent_Done,
34014 /* 93628 */ // Label 2877: @93628
34015 /* 93628 */ GIM_Try, /*On fail goto*//*Label 2878*/ GIMT_Encode4(93686),
34016 /* 93633 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
34017 /* 93637 */ GIM_Try, /*On fail goto*//*Label 2879*/ GIMT_Encode4(93661), // Rule ID 5566 //
34018 /* 93642 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34019 /* 93646 */ // (intrinsic_void 3951:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34020 /* 93646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u),
34021 /* 93649 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34022 /* 93651 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34023 /* 93653 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34024 /* 93655 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34025 /* 93659 */ GIR_RootConstrainSelectedInstOperands,
34026 /* 93660 */ // GIR_Coverage, 5566,
34027 /* 93660 */ GIR_EraseRootFromParent_Done,
34028 /* 93661 */ // Label 2879: @93661
34029 /* 93661 */ GIM_Try, /*On fail goto*//*Label 2880*/ GIMT_Encode4(93685), // Rule ID 5567 //
34030 /* 93666 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34031 /* 93670 */ // (intrinsic_void 3951:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34032 /* 93670 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq),
34033 /* 93673 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34034 /* 93675 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34035 /* 93677 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34036 /* 93679 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34037 /* 93683 */ GIR_RootConstrainSelectedInstOperands,
34038 /* 93684 */ // GIR_Coverage, 5567,
34039 /* 93684 */ GIR_EraseRootFromParent_Done,
34040 /* 93685 */ // Label 2880: @93685
34041 /* 93685 */ GIM_Reject,
34042 /* 93686 */ // Label 2878: @93686
34043 /* 93686 */ GIM_Reject,
34044 /* 93687 */ // Label 2873: @93687
34045 /* 93687 */ GIM_Reject,
34046 /* 93688 */ // Label 2869: @93688
34047 /* 93688 */ GIM_Try, /*On fail goto*//*Label 2881*/ GIMT_Encode4(93911),
34048 /* 93693 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34049 /* 93696 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34050 /* 93699 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34051 /* 93702 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
34052 /* 93706 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34053 /* 93710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34054 /* 93714 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34055 /* 93718 */ GIM_Try, /*On fail goto*//*Label 2882*/ GIMT_Encode4(93746), // Rule ID 5564 //
34056 /* 93723 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
34057 /* 93727 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34058 /* 93731 */ // (intrinsic_void 3951:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34059 /* 93731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB32_rq),
34060 /* 93734 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34061 /* 93736 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34062 /* 93738 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34063 /* 93740 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34064 /* 93744 */ GIR_RootConstrainSelectedInstOperands,
34065 /* 93745 */ // GIR_Coverage, 5564,
34066 /* 93745 */ GIR_EraseRootFromParent_Done,
34067 /* 93746 */ // Label 2882: @93746
34068 /* 93746 */ GIM_Try, /*On fail goto*//*Label 2883*/ GIMT_Encode4(93804),
34069 /* 93751 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
34070 /* 93755 */ GIM_Try, /*On fail goto*//*Label 2884*/ GIMT_Encode4(93779), // Rule ID 5570 //
34071 /* 93760 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34072 /* 93764 */ // (intrinsic_void 3951:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34073 /* 93764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq_u),
34074 /* 93767 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34075 /* 93769 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34076 /* 93771 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34077 /* 93773 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34078 /* 93777 */ GIR_RootConstrainSelectedInstOperands,
34079 /* 93778 */ // GIR_Coverage, 5570,
34080 /* 93778 */ GIR_EraseRootFromParent_Done,
34081 /* 93779 */ // Label 2884: @93779
34082 /* 93779 */ GIM_Try, /*On fail goto*//*Label 2885*/ GIMT_Encode4(93803), // Rule ID 5571 //
34083 /* 93784 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34084 /* 93788 */ // (intrinsic_void 3951:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34085 /* 93788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq),
34086 /* 93791 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34087 /* 93793 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34088 /* 93795 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34089 /* 93797 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34090 /* 93801 */ GIR_RootConstrainSelectedInstOperands,
34091 /* 93802 */ // GIR_Coverage, 5571,
34092 /* 93802 */ GIR_EraseRootFromParent_Done,
34093 /* 93803 */ // Label 2885: @93803
34094 /* 93803 */ GIM_Reject,
34095 /* 93804 */ // Label 2883: @93804
34096 /* 93804 */ GIM_Try, /*On fail goto*//*Label 2886*/ GIMT_Encode4(93910),
34097 /* 93809 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
34098 /* 93813 */ GIM_Try, /*On fail goto*//*Label 2887*/ GIMT_Encode4(93837), // Rule ID 5574 //
34099 /* 93818 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34100 /* 93822 */ // (intrinsic_void 3951:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34101 /* 93822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u),
34102 /* 93825 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34103 /* 93827 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34104 /* 93829 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34105 /* 93831 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34106 /* 93835 */ GIR_RootConstrainSelectedInstOperands,
34107 /* 93836 */ // GIR_Coverage, 5574,
34108 /* 93836 */ GIR_EraseRootFromParent_Done,
34109 /* 93837 */ // Label 2887: @93837
34110 /* 93837 */ GIM_Try, /*On fail goto*//*Label 2888*/ GIMT_Encode4(93861), // Rule ID 5575 //
34111 /* 93842 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34112 /* 93846 */ // (intrinsic_void 3951:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34113 /* 93846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq),
34114 /* 93849 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34115 /* 93851 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34116 /* 93853 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34117 /* 93855 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34118 /* 93859 */ GIR_RootConstrainSelectedInstOperands,
34119 /* 93860 */ // GIR_Coverage, 5575,
34120 /* 93860 */ GIR_EraseRootFromParent_Done,
34121 /* 93861 */ // Label 2888: @93861
34122 /* 93861 */ GIM_Try, /*On fail goto*//*Label 2889*/ GIMT_Encode4(93885), // Rule ID 5578 //
34123 /* 93866 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34124 /* 93870 */ // (intrinsic_void 3951:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34125 /* 93870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u),
34126 /* 93873 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34127 /* 93875 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34128 /* 93877 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34129 /* 93879 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34130 /* 93883 */ GIR_RootConstrainSelectedInstOperands,
34131 /* 93884 */ // GIR_Coverage, 5578,
34132 /* 93884 */ GIR_EraseRootFromParent_Done,
34133 /* 93885 */ // Label 2889: @93885
34134 /* 93885 */ GIM_Try, /*On fail goto*//*Label 2890*/ GIMT_Encode4(93909), // Rule ID 5579 //
34135 /* 93890 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34136 /* 93894 */ // (intrinsic_void 3951:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34137 /* 93894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq),
34138 /* 93897 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34139 /* 93899 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34140 /* 93901 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34141 /* 93903 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34142 /* 93907 */ GIR_RootConstrainSelectedInstOperands,
34143 /* 93908 */ // GIR_Coverage, 5579,
34144 /* 93908 */ GIR_EraseRootFromParent_Done,
34145 /* 93909 */ // Label 2890: @93909
34146 /* 93909 */ GIM_Reject,
34147 /* 93910 */ // Label 2886: @93910
34148 /* 93910 */ GIM_Reject,
34149 /* 93911 */ // Label 2881: @93911
34150 /* 93911 */ GIM_Reject,
34151 /* 93912 */ // Label 2870: @93912
34152 /* 93912 */ GIM_Try, /*On fail goto*//*Label 2891*/ GIMT_Encode4(93995),
34153 /* 93917 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
34154 /* 93920 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34155 /* 93923 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34156 /* 93926 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
34157 /* 93930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34158 /* 93934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34159 /* 93938 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34160 /* 93942 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
34161 /* 93946 */ GIM_Try, /*On fail goto*//*Label 2892*/ GIMT_Encode4(93970), // Rule ID 5582 //
34162 /* 93951 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34163 /* 93955 */ // (intrinsic_void 3951:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRD64_rq_u MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
34164 /* 93955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq_u),
34165 /* 93958 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34166 /* 93960 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34167 /* 93962 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34168 /* 93964 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34169 /* 93968 */ GIR_RootConstrainSelectedInstOperands,
34170 /* 93969 */ // GIR_Coverage, 5582,
34171 /* 93969 */ GIR_EraseRootFromParent_Done,
34172 /* 93970 */ // Label 2892: @93970
34173 /* 93970 */ GIM_Try, /*On fail goto*//*Label 2893*/ GIMT_Encode4(93994), // Rule ID 5583 //
34174 /* 93975 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
34175 /* 93979 */ // (intrinsic_void 3951:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 3:{ *:[i32] }) => (MVE_VSTRD64_rq MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
34176 /* 93979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq),
34177 /* 93982 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
34178 /* 93984 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
34179 /* 93986 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
34180 /* 93988 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34181 /* 93992 */ GIR_RootConstrainSelectedInstOperands,
34182 /* 93993 */ // GIR_Coverage, 5583,
34183 /* 93993 */ GIR_EraseRootFromParent_Done,
34184 /* 93994 */ // Label 2893: @93994
34185 /* 93994 */ GIM_Reject,
34186 /* 93995 */ // Label 2891: @93995
34187 /* 93995 */ GIM_Reject,
34188 /* 93996 */ // Label 2871: @93996
34189 /* 93996 */ GIM_Reject,
34190 /* 93997 */ // Label 2866: @93997
34191 /* 93997 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2894*/ GIMT_Encode4(94060), GIMT_Encode2(GIFBS_IsARM), // Rule ID 257 //
34192 /* 94004 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr),
34193 /* 94009 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
34194 /* 94012 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34195 /* 94015 */ // MIs[0] cop
34196 /* 94015 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34197 /* 94018 */ // MIs[0] opc1
34198 /* 94018 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34199 /* 94021 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
34200 /* 94025 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
34201 /* 94029 */ // MIs[0] CRm
34202 /* 94029 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34203 /* 94032 */ // (intrinsic_void 3736:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
34204 /* 94032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR),
34205 /* 94035 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34206 /* 94037 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34207 /* 94039 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
34208 /* 94041 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
34209 /* 94043 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34210 /* 94045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
34211 /* 94048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34212 /* 94054 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34213 /* 94058 */ GIR_RootConstrainSelectedInstOperands,
34214 /* 94059 */ // GIR_Coverage, 257,
34215 /* 94059 */ GIR_EraseRootFromParent_Done,
34216 /* 94060 */ // Label 2894: @94060
34217 /* 94060 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2895*/ GIMT_Encode4(94114), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 258 //
34218 /* 94067 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2),
34219 /* 94072 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
34220 /* 94075 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34221 /* 94078 */ // MIs[0] cop
34222 /* 94078 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34223 /* 94081 */ // MIs[0] opc1
34224 /* 94081 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34225 /* 94084 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
34226 /* 94088 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
34227 /* 94092 */ // MIs[0] CRm
34228 /* 94092 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34229 /* 94095 */ // (intrinsic_void 3737:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
34230 /* 94095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR2),
34231 /* 94098 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34232 /* 94100 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34233 /* 94102 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
34234 /* 94104 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
34235 /* 94106 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34236 /* 94108 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34237 /* 94112 */ GIR_RootConstrainSelectedInstOperands,
34238 /* 94113 */ // GIR_Coverage, 258,
34239 /* 94113 */ GIR_EraseRootFromParent_Done,
34240 /* 94114 */ // Label 2895: @94114
34241 /* 94114 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2896*/ GIMT_Encode4(94177), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 595 //
34242 /* 94121 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr),
34243 /* 94126 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
34244 /* 94129 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34245 /* 94132 */ // MIs[0] cop
34246 /* 94132 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34247 /* 94135 */ // MIs[0] opc1
34248 /* 94135 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34249 /* 94138 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34250 /* 94142 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34251 /* 94146 */ // MIs[0] CRm
34252 /* 94146 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34253 /* 94149 */ // (intrinsic_void 3736:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
34254 /* 94149 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR),
34255 /* 94152 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34256 /* 94154 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34257 /* 94156 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
34258 /* 94158 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
34259 /* 94160 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34260 /* 94162 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
34261 /* 94165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34262 /* 94171 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34263 /* 94175 */ GIR_RootConstrainSelectedInstOperands,
34264 /* 94176 */ // GIR_Coverage, 595,
34265 /* 94176 */ GIR_EraseRootFromParent_Done,
34266 /* 94177 */ // Label 2896: @94177
34267 /* 94177 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2897*/ GIMT_Encode4(94240), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 596 //
34268 /* 94184 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2),
34269 /* 94189 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
34270 /* 94192 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34271 /* 94195 */ // MIs[0] cop
34272 /* 94195 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34273 /* 94198 */ // MIs[0] opc1
34274 /* 94198 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34275 /* 94201 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34276 /* 94205 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34277 /* 94209 */ // MIs[0] CRm
34278 /* 94209 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34279 /* 94212 */ // (intrinsic_void 3737:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
34280 /* 94212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR2),
34281 /* 94215 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34282 /* 94217 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34283 /* 94219 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
34284 /* 94221 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
34285 /* 94223 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34286 /* 94225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
34287 /* 94228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34288 /* 94234 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34289 /* 94238 */ GIR_RootConstrainSelectedInstOperands,
34290 /* 94239 */ // GIR_Coverage, 596,
34291 /* 94239 */ GIR_EraseRootFromParent_Done,
34292 /* 94240 */ // Label 2897: @94240
34293 /* 94240 */ GIM_Reject,
34294 /* 94241 */ // Label 2865: @94241
34295 /* 94241 */ GIM_Try, /*On fail goto*//*Label 2898*/ GIMT_Encode4(96146),
34296 /* 94246 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
34297 /* 94249 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2899*/ GIMT_Encode4(94309), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 245 //
34298 /* 94256 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp),
34299 /* 94261 */ // MIs[0] cop
34300 /* 94261 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34301 /* 94264 */ // MIs[0] opc1
34302 /* 94264 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34303 /* 94267 */ // MIs[0] CRd
34304 /* 94267 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
34305 /* 94270 */ // MIs[0] CRn
34306 /* 94270 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
34307 /* 94273 */ // MIs[0] CRm
34308 /* 94273 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34309 /* 94276 */ // MIs[0] opc2
34310 /* 94276 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
34311 /* 94279 */ // (intrinsic_void 3704:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
34312 /* 94279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP),
34313 /* 94282 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34314 /* 94284 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34315 /* 94286 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
34316 /* 94288 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
34317 /* 94290 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34318 /* 94292 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
34319 /* 94294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
34320 /* 94297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34321 /* 94303 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34322 /* 94307 */ GIR_RootConstrainSelectedInstOperands,
34323 /* 94308 */ // GIR_Coverage, 245,
34324 /* 94308 */ GIR_EraseRootFromParent_Done,
34325 /* 94309 */ // Label 2899: @94309
34326 /* 94309 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2900*/ GIMT_Encode4(94360), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 246 //
34327 /* 94316 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2),
34328 /* 94321 */ // MIs[0] cop
34329 /* 94321 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34330 /* 94324 */ // MIs[0] opc1
34331 /* 94324 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34332 /* 94327 */ // MIs[0] CRd
34333 /* 94327 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
34334 /* 94330 */ // MIs[0] CRn
34335 /* 94330 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
34336 /* 94333 */ // MIs[0] CRm
34337 /* 94333 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34338 /* 94336 */ // MIs[0] opc2
34339 /* 94336 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
34340 /* 94339 */ // (intrinsic_void 3705:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
34341 /* 94339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP2),
34342 /* 94342 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34343 /* 94344 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34344 /* 94346 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
34345 /* 94348 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
34346 /* 94350 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34347 /* 94352 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
34348 /* 94354 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34349 /* 94358 */ GIR_RootConstrainSelectedInstOperands,
34350 /* 94359 */ // GIR_Coverage, 246,
34351 /* 94359 */ GIR_EraseRootFromParent_Done,
34352 /* 94360 */ // Label 2900: @94360
34353 /* 94360 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2901*/ GIMT_Encode4(94420), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 597 //
34354 /* 94367 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp),
34355 /* 94372 */ // MIs[0] cop
34356 /* 94372 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34357 /* 94375 */ // MIs[0] opc1
34358 /* 94375 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34359 /* 94378 */ // MIs[0] CRd
34360 /* 94378 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
34361 /* 94381 */ // MIs[0] CRn
34362 /* 94381 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
34363 /* 94384 */ // MIs[0] CRm
34364 /* 94384 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34365 /* 94387 */ // MIs[0] opc2
34366 /* 94387 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
34367 /* 94390 */ // (intrinsic_void 3704:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
34368 /* 94390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP),
34369 /* 94393 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34370 /* 94395 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34371 /* 94397 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
34372 /* 94399 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
34373 /* 94401 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34374 /* 94403 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
34375 /* 94405 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
34376 /* 94408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34377 /* 94414 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34378 /* 94418 */ GIR_RootConstrainSelectedInstOperands,
34379 /* 94419 */ // GIR_Coverage, 597,
34380 /* 94419 */ GIR_EraseRootFromParent_Done,
34381 /* 94420 */ // Label 2901: @94420
34382 /* 94420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2902*/ GIMT_Encode4(94480), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 598 //
34383 /* 94427 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2),
34384 /* 94432 */ // MIs[0] cop
34385 /* 94432 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
34386 /* 94435 */ // MIs[0] opc1
34387 /* 94435 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
34388 /* 94438 */ // MIs[0] CRd
34389 /* 94438 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
34390 /* 94441 */ // MIs[0] CRn
34391 /* 94441 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
34392 /* 94444 */ // MIs[0] CRm
34393 /* 94444 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
34394 /* 94447 */ // MIs[0] opc2
34395 /* 94447 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
34396 /* 94450 */ // (intrinsic_void 3705:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
34397 /* 94450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP2),
34398 /* 94453 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
34399 /* 94455 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
34400 /* 94457 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
34401 /* 94459 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
34402 /* 94461 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
34403 /* 94463 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
34404 /* 94465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
34405 /* 94468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34406 /* 94474 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34407 /* 94478 */ GIR_RootConstrainSelectedInstOperands,
34408 /* 94479 */ // GIR_Coverage, 598,
34409 /* 94479 */ GIR_EraseRootFromParent_Done,
34410 /* 94480 */ // Label 2902: @94480
34411 /* 94480 */ GIM_Try, /*On fail goto*//*Label 2903*/ GIMT_Encode4(95898),
34412 /* 94485 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
34413 /* 94490 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(14), /*)*//*default:*//*Label 2908*/ GIMT_Encode4(95897),
34414 /* 94501 */ /*GILLT_v16s8*//*Label 2904*/ GIMT_Encode4(94525), GIMT_Encode4(0),
34415 /* 94509 */ /*GILLT_v8s16*//*Label 2905*/ GIMT_Encode4(94616), GIMT_Encode4(0),
34416 /* 94517 */ /*GILLT_v4s32*//*Label 2906*/ GIMT_Encode4(95069),
34417 /* 94521 */ /*GILLT_v2s64*//*Label 2907*/ GIMT_Encode4(95634),
34418 /* 94525 */ // Label 2904: @94525
34419 /* 94525 */ GIM_Try, /*On fail goto*//*Label 2909*/ GIMT_Encode4(94615),
34420 /* 94530 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
34421 /* 94533 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34422 /* 94536 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34423 /* 94539 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34424 /* 94542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34425 /* 94546 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
34426 /* 94550 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34427 /* 94554 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34428 /* 94558 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
34429 /* 94562 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34430 /* 94566 */ GIM_Try, /*On fail goto*//*Label 2910*/ GIMT_Encode4(94590), // Rule ID 5476 //
34431 /* 94571 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34432 /* 94575 */ // (intrinsic_w_chain:{ *:[v16i8] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
34433 /* 94575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq),
34434 /* 94578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34435 /* 94580 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34436 /* 94582 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34437 /* 94584 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34438 /* 94588 */ GIR_RootConstrainSelectedInstOperands,
34439 /* 94589 */ // GIR_Coverage, 5476,
34440 /* 94589 */ GIR_EraseRootFromParent_Done,
34441 /* 94590 */ // Label 2910: @94590
34442 /* 94590 */ GIM_Try, /*On fail goto*//*Label 2911*/ GIMT_Encode4(94614), // Rule ID 5484 //
34443 /* 94595 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34444 /* 94599 */ // (intrinsic_w_chain:{ *:[v16i8] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
34445 /* 94599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq),
34446 /* 94602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34447 /* 94604 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34448 /* 94606 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34449 /* 94608 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34450 /* 94612 */ GIR_RootConstrainSelectedInstOperands,
34451 /* 94613 */ // GIR_Coverage, 5484,
34452 /* 94613 */ GIR_EraseRootFromParent_Done,
34453 /* 94614 */ // Label 2911: @94614
34454 /* 94614 */ GIM_Reject,
34455 /* 94615 */ // Label 2909: @94615
34456 /* 94615 */ GIM_Reject,
34457 /* 94616 */ // Label 2905: @94616
34458 /* 94616 */ GIM_Try, /*On fail goto*//*Label 2912*/ GIMT_Encode4(95068),
34459 /* 94621 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34460 /* 94624 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34461 /* 94627 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34462 /* 94630 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34463 /* 94633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34464 /* 94637 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
34465 /* 94641 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34466 /* 94645 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34467 /* 94649 */ GIM_Try, /*On fail goto*//*Label 2913*/ GIMT_Encode4(94715),
34468 /* 94654 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
34469 /* 94658 */ GIM_Try, /*On fail goto*//*Label 2914*/ GIMT_Encode4(94686), // Rule ID 5472 //
34470 /* 94663 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34471 /* 94667 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34472 /* 94671 */ // (intrinsic_w_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34473 /* 94671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
34474 /* 94674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34475 /* 94676 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34476 /* 94678 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34477 /* 94680 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34478 /* 94684 */ GIR_RootConstrainSelectedInstOperands,
34479 /* 94685 */ // GIR_Coverage, 5472,
34480 /* 94685 */ GIR_EraseRootFromParent_Done,
34481 /* 94686 */ // Label 2914: @94686
34482 /* 94686 */ GIM_Try, /*On fail goto*//*Label 2915*/ GIMT_Encode4(94714), // Rule ID 5473 //
34483 /* 94691 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34484 /* 94695 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34485 /* 94699 */ // (intrinsic_w_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34486 /* 94699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
34487 /* 94702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34488 /* 94704 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34489 /* 94706 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34490 /* 94708 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34491 /* 94712 */ GIR_RootConstrainSelectedInstOperands,
34492 /* 94713 */ // GIR_Coverage, 5473,
34493 /* 94713 */ GIR_EraseRootFromParent_Done,
34494 /* 94714 */ // Label 2915: @94714
34495 /* 94714 */ GIM_Reject,
34496 /* 94715 */ // Label 2913: @94715
34497 /* 94715 */ GIM_Try, /*On fail goto*//*Label 2916*/ GIMT_Encode4(94777),
34498 /* 94720 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
34499 /* 94724 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34500 /* 94728 */ GIM_Try, /*On fail goto*//*Label 2917*/ GIMT_Encode4(94752), // Rule ID 5486 //
34501 /* 94733 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34502 /* 94737 */ // (intrinsic_w_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34503 /* 94737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU16_rq),
34504 /* 94740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34505 /* 94742 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34506 /* 94744 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34507 /* 94746 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34508 /* 94750 */ GIR_RootConstrainSelectedInstOperands,
34509 /* 94751 */ // GIR_Coverage, 5486,
34510 /* 94751 */ GIR_EraseRootFromParent_Done,
34511 /* 94752 */ // Label 2917: @94752
34512 /* 94752 */ GIM_Try, /*On fail goto*//*Label 2918*/ GIMT_Encode4(94776), // Rule ID 5488 //
34513 /* 94757 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34514 /* 94761 */ // (intrinsic_w_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34515 /* 94761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS16_rq),
34516 /* 94764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34517 /* 94766 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34518 /* 94768 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34519 /* 94770 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34520 /* 94774 */ GIR_RootConstrainSelectedInstOperands,
34521 /* 94775 */ // GIR_Coverage, 5488,
34522 /* 94775 */ GIR_EraseRootFromParent_Done,
34523 /* 94776 */ // Label 2918: @94776
34524 /* 94776 */ GIM_Reject,
34525 /* 94777 */ // Label 2916: @94777
34526 /* 94777 */ GIM_Try, /*On fail goto*//*Label 2919*/ GIMT_Encode4(95067),
34527 /* 94782 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
34528 /* 94786 */ GIM_Try, /*On fail goto*//*Label 2920*/ GIMT_Encode4(94814), // Rule ID 5494 //
34529 /* 94791 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34530 /* 94795 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34531 /* 94799 */ // (intrinsic_w_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34532 /* 94799 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
34533 /* 94802 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34534 /* 94804 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34535 /* 94806 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34536 /* 94808 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34537 /* 94812 */ GIR_RootConstrainSelectedInstOperands,
34538 /* 94813 */ // GIR_Coverage, 5494,
34539 /* 94813 */ GIR_EraseRootFromParent_Done,
34540 /* 94814 */ // Label 2920: @94814
34541 /* 94814 */ GIM_Try, /*On fail goto*//*Label 2921*/ GIMT_Encode4(94842), // Rule ID 5495 //
34542 /* 94819 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34543 /* 94823 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34544 /* 94827 */ // (intrinsic_w_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34545 /* 94827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
34546 /* 94830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34547 /* 94832 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34548 /* 94834 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34549 /* 94836 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34550 /* 94840 */ GIR_RootConstrainSelectedInstOperands,
34551 /* 94841 */ // GIR_Coverage, 5495,
34552 /* 94841 */ GIR_EraseRootFromParent_Done,
34553 /* 94842 */ // Label 2921: @94842
34554 /* 94842 */ GIM_Try, /*On fail goto*//*Label 2922*/ GIMT_Encode4(94870), // Rule ID 5498 //
34555 /* 94847 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34556 /* 94851 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34557 /* 94855 */ // (intrinsic_w_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34558 /* 94855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
34559 /* 94858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34560 /* 94860 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34561 /* 94862 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34562 /* 94864 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34563 /* 94868 */ GIR_RootConstrainSelectedInstOperands,
34564 /* 94869 */ // GIR_Coverage, 5498,
34565 /* 94869 */ GIR_EraseRootFromParent_Done,
34566 /* 94870 */ // Label 2922: @94870
34567 /* 94870 */ GIM_Try, /*On fail goto*//*Label 2923*/ GIMT_Encode4(94898), // Rule ID 5499 //
34568 /* 94875 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34569 /* 94879 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34570 /* 94883 */ // (intrinsic_w_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34571 /* 94883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
34572 /* 94886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34573 /* 94888 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34574 /* 94890 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34575 /* 94892 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34576 /* 94896 */ GIR_RootConstrainSelectedInstOperands,
34577 /* 94897 */ // GIR_Coverage, 5499,
34578 /* 94897 */ GIR_EraseRootFromParent_Done,
34579 /* 94898 */ // Label 2923: @94898
34580 /* 94898 */ GIM_Try, /*On fail goto*//*Label 2924*/ GIMT_Encode4(94926), // Rule ID 5502 //
34581 /* 94903 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34582 /* 94907 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34583 /* 94911 */ // (intrinsic_w_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34584 /* 94911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
34585 /* 94914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34586 /* 94916 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34587 /* 94918 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34588 /* 94920 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34589 /* 94924 */ GIR_RootConstrainSelectedInstOperands,
34590 /* 94925 */ // GIR_Coverage, 5502,
34591 /* 94925 */ GIR_EraseRootFromParent_Done,
34592 /* 94926 */ // Label 2924: @94926
34593 /* 94926 */ GIM_Try, /*On fail goto*//*Label 2925*/ GIMT_Encode4(94954), // Rule ID 5503 //
34594 /* 94931 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34595 /* 94935 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34596 /* 94939 */ // (intrinsic_w_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34597 /* 94939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
34598 /* 94942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34599 /* 94944 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34600 /* 94946 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34601 /* 94948 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34602 /* 94952 */ GIR_RootConstrainSelectedInstOperands,
34603 /* 94953 */ // GIR_Coverage, 5503,
34604 /* 94953 */ GIR_EraseRootFromParent_Done,
34605 /* 94954 */ // Label 2925: @94954
34606 /* 94954 */ GIM_Try, /*On fail goto*//*Label 2926*/ GIMT_Encode4(94982), // Rule ID 5506 //
34607 /* 94959 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34608 /* 94963 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34609 /* 94967 */ // (intrinsic_w_chain:{ *:[v8f16] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34610 /* 94967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
34611 /* 94970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34612 /* 94972 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34613 /* 94974 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34614 /* 94976 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34615 /* 94980 */ GIR_RootConstrainSelectedInstOperands,
34616 /* 94981 */ // GIR_Coverage, 5506,
34617 /* 94981 */ GIR_EraseRootFromParent_Done,
34618 /* 94982 */ // Label 2926: @94982
34619 /* 94982 */ GIM_Try, /*On fail goto*//*Label 2927*/ GIMT_Encode4(95010), // Rule ID 5507 //
34620 /* 94987 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34621 /* 94991 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34622 /* 94995 */ // (intrinsic_w_chain:{ *:[v8f16] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34623 /* 94995 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
34624 /* 94998 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34625 /* 95000 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34626 /* 95002 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34627 /* 95004 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34628 /* 95008 */ GIR_RootConstrainSelectedInstOperands,
34629 /* 95009 */ // GIR_Coverage, 5507,
34630 /* 95009 */ GIR_EraseRootFromParent_Done,
34631 /* 95010 */ // Label 2927: @95010
34632 /* 95010 */ GIM_Try, /*On fail goto*//*Label 2928*/ GIMT_Encode4(95038), // Rule ID 5510 //
34633 /* 95015 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34634 /* 95019 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34635 /* 95023 */ // (intrinsic_w_chain:{ *:[v8f16] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34636 /* 95023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
34637 /* 95026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34638 /* 95028 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34639 /* 95030 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34640 /* 95032 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34641 /* 95036 */ GIR_RootConstrainSelectedInstOperands,
34642 /* 95037 */ // GIR_Coverage, 5510,
34643 /* 95037 */ GIR_EraseRootFromParent_Done,
34644 /* 95038 */ // Label 2928: @95038
34645 /* 95038 */ GIM_Try, /*On fail goto*//*Label 2929*/ GIMT_Encode4(95066), // Rule ID 5511 //
34646 /* 95043 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34647 /* 95047 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34648 /* 95051 */ // (intrinsic_w_chain:{ *:[v8f16] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
34649 /* 95051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
34650 /* 95054 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34651 /* 95056 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34652 /* 95058 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34653 /* 95060 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34654 /* 95064 */ GIR_RootConstrainSelectedInstOperands,
34655 /* 95065 */ // GIR_Coverage, 5511,
34656 /* 95065 */ GIR_EraseRootFromParent_Done,
34657 /* 95066 */ // Label 2929: @95066
34658 /* 95066 */ GIM_Reject,
34659 /* 95067 */ // Label 2919: @95067
34660 /* 95067 */ GIM_Reject,
34661 /* 95068 */ // Label 2912: @95068
34662 /* 95068 */ GIM_Reject,
34663 /* 95069 */ // Label 2906: @95069
34664 /* 95069 */ GIM_Try, /*On fail goto*//*Label 2930*/ GIMT_Encode4(95633),
34665 /* 95074 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34666 /* 95077 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34667 /* 95080 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34668 /* 95083 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34669 /* 95086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34670 /* 95090 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
34671 /* 95094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34672 /* 95098 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34673 /* 95102 */ GIM_Try, /*On fail goto*//*Label 2931*/ GIMT_Encode4(95164),
34674 /* 95107 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
34675 /* 95111 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34676 /* 95115 */ GIM_Try, /*On fail goto*//*Label 2932*/ GIMT_Encode4(95139), // Rule ID 5490 //
34677 /* 95120 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34678 /* 95124 */ // (intrinsic_w_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34679 /* 95124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU32_rq),
34680 /* 95127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34681 /* 95129 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34682 /* 95131 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34683 /* 95133 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34684 /* 95137 */ GIR_RootConstrainSelectedInstOperands,
34685 /* 95138 */ // GIR_Coverage, 5490,
34686 /* 95138 */ GIR_EraseRootFromParent_Done,
34687 /* 95139 */ // Label 2932: @95139
34688 /* 95139 */ GIM_Try, /*On fail goto*//*Label 2933*/ GIMT_Encode4(95163), // Rule ID 5492 //
34689 /* 95144 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34690 /* 95148 */ // (intrinsic_w_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34691 /* 95148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS32_rq),
34692 /* 95151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34693 /* 95153 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34694 /* 95155 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34695 /* 95157 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34696 /* 95161 */ GIR_RootConstrainSelectedInstOperands,
34697 /* 95162 */ // GIR_Coverage, 5492,
34698 /* 95162 */ GIR_EraseRootFromParent_Done,
34699 /* 95163 */ // Label 2933: @95163
34700 /* 95163 */ GIM_Reject,
34701 /* 95164 */ // Label 2931: @95164
34702 /* 95164 */ GIM_Try, /*On fail goto*//*Label 2934*/ GIMT_Encode4(95286),
34703 /* 95169 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
34704 /* 95173 */ GIM_Try, /*On fail goto*//*Label 2935*/ GIMT_Encode4(95201), // Rule ID 5514 //
34705 /* 95178 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34706 /* 95182 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34707 /* 95186 */ // (intrinsic_w_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34708 /* 95186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq_u),
34709 /* 95189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34710 /* 95191 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34711 /* 95193 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34712 /* 95195 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34713 /* 95199 */ GIR_RootConstrainSelectedInstOperands,
34714 /* 95200 */ // GIR_Coverage, 5514,
34715 /* 95200 */ GIR_EraseRootFromParent_Done,
34716 /* 95201 */ // Label 2935: @95201
34717 /* 95201 */ GIM_Try, /*On fail goto*//*Label 2936*/ GIMT_Encode4(95229), // Rule ID 5515 //
34718 /* 95206 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34719 /* 95210 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34720 /* 95214 */ // (intrinsic_w_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34721 /* 95214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq),
34722 /* 95217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34723 /* 95219 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34724 /* 95221 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34725 /* 95223 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34726 /* 95227 */ GIR_RootConstrainSelectedInstOperands,
34727 /* 95228 */ // GIR_Coverage, 5515,
34728 /* 95228 */ GIR_EraseRootFromParent_Done,
34729 /* 95229 */ // Label 2936: @95229
34730 /* 95229 */ GIM_Try, /*On fail goto*//*Label 2937*/ GIMT_Encode4(95257), // Rule ID 5518 //
34731 /* 95234 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34732 /* 95238 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34733 /* 95242 */ // (intrinsic_w_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34734 /* 95242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq_u),
34735 /* 95245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34736 /* 95247 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34737 /* 95249 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34738 /* 95251 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34739 /* 95255 */ GIR_RootConstrainSelectedInstOperands,
34740 /* 95256 */ // GIR_Coverage, 5518,
34741 /* 95256 */ GIR_EraseRootFromParent_Done,
34742 /* 95257 */ // Label 2937: @95257
34743 /* 95257 */ GIM_Try, /*On fail goto*//*Label 2938*/ GIMT_Encode4(95285), // Rule ID 5519 //
34744 /* 95262 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34745 /* 95266 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34746 /* 95270 */ // (intrinsic_w_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34747 /* 95270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq),
34748 /* 95273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34749 /* 95275 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34750 /* 95277 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34751 /* 95279 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34752 /* 95283 */ GIR_RootConstrainSelectedInstOperands,
34753 /* 95284 */ // GIR_Coverage, 5519,
34754 /* 95284 */ GIR_EraseRootFromParent_Done,
34755 /* 95285 */ // Label 2938: @95285
34756 /* 95285 */ GIM_Reject,
34757 /* 95286 */ // Label 2934: @95286
34758 /* 95286 */ GIM_Try, /*On fail goto*//*Label 2939*/ GIMT_Encode4(95632),
34759 /* 95291 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
34760 /* 95295 */ GIM_Try, /*On fail goto*//*Label 2940*/ GIMT_Encode4(95323), // Rule ID 5522 //
34761 /* 95300 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34762 /* 95304 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34763 /* 95308 */ // (intrinsic_w_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34764 /* 95308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
34765 /* 95311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34766 /* 95313 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34767 /* 95315 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34768 /* 95317 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34769 /* 95321 */ GIR_RootConstrainSelectedInstOperands,
34770 /* 95322 */ // GIR_Coverage, 5522,
34771 /* 95322 */ GIR_EraseRootFromParent_Done,
34772 /* 95323 */ // Label 2940: @95323
34773 /* 95323 */ GIM_Try, /*On fail goto*//*Label 2941*/ GIMT_Encode4(95351), // Rule ID 5523 //
34774 /* 95328 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34775 /* 95332 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34776 /* 95336 */ // (intrinsic_w_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34777 /* 95336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
34778 /* 95339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34779 /* 95341 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34780 /* 95343 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34781 /* 95345 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34782 /* 95349 */ GIR_RootConstrainSelectedInstOperands,
34783 /* 95350 */ // GIR_Coverage, 5523,
34784 /* 95350 */ GIR_EraseRootFromParent_Done,
34785 /* 95351 */ // Label 2941: @95351
34786 /* 95351 */ GIM_Try, /*On fail goto*//*Label 2942*/ GIMT_Encode4(95379), // Rule ID 5526 //
34787 /* 95356 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34788 /* 95360 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34789 /* 95364 */ // (intrinsic_w_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34790 /* 95364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
34791 /* 95367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34792 /* 95369 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34793 /* 95371 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34794 /* 95373 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34795 /* 95377 */ GIR_RootConstrainSelectedInstOperands,
34796 /* 95378 */ // GIR_Coverage, 5526,
34797 /* 95378 */ GIR_EraseRootFromParent_Done,
34798 /* 95379 */ // Label 2942: @95379
34799 /* 95379 */ GIM_Try, /*On fail goto*//*Label 2943*/ GIMT_Encode4(95407), // Rule ID 5527 //
34800 /* 95384 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34801 /* 95388 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34802 /* 95392 */ // (intrinsic_w_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34803 /* 95392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
34804 /* 95395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34805 /* 95397 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34806 /* 95399 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34807 /* 95401 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34808 /* 95405 */ GIR_RootConstrainSelectedInstOperands,
34809 /* 95406 */ // GIR_Coverage, 5527,
34810 /* 95406 */ GIR_EraseRootFromParent_Done,
34811 /* 95407 */ // Label 2943: @95407
34812 /* 95407 */ GIM_Try, /*On fail goto*//*Label 2944*/ GIMT_Encode4(95435), // Rule ID 5530 //
34813 /* 95412 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34814 /* 95416 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34815 /* 95420 */ // (intrinsic_w_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34816 /* 95420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
34817 /* 95423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34818 /* 95425 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34819 /* 95427 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34820 /* 95429 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34821 /* 95433 */ GIR_RootConstrainSelectedInstOperands,
34822 /* 95434 */ // GIR_Coverage, 5530,
34823 /* 95434 */ GIR_EraseRootFromParent_Done,
34824 /* 95435 */ // Label 2944: @95435
34825 /* 95435 */ GIM_Try, /*On fail goto*//*Label 2945*/ GIMT_Encode4(95463), // Rule ID 5531 //
34826 /* 95440 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34827 /* 95444 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34828 /* 95448 */ // (intrinsic_w_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34829 /* 95448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
34830 /* 95451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34831 /* 95453 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34832 /* 95455 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34833 /* 95457 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34834 /* 95461 */ GIR_RootConstrainSelectedInstOperands,
34835 /* 95462 */ // GIR_Coverage, 5531,
34836 /* 95462 */ GIR_EraseRootFromParent_Done,
34837 /* 95463 */ // Label 2945: @95463
34838 /* 95463 */ GIM_Try, /*On fail goto*//*Label 2946*/ GIMT_Encode4(95491), // Rule ID 5534 //
34839 /* 95468 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34840 /* 95472 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34841 /* 95476 */ // (intrinsic_w_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34842 /* 95476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
34843 /* 95479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34844 /* 95481 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34845 /* 95483 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34846 /* 95485 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34847 /* 95489 */ GIR_RootConstrainSelectedInstOperands,
34848 /* 95490 */ // GIR_Coverage, 5534,
34849 /* 95490 */ GIR_EraseRootFromParent_Done,
34850 /* 95491 */ // Label 2946: @95491
34851 /* 95491 */ GIM_Try, /*On fail goto*//*Label 2947*/ GIMT_Encode4(95519), // Rule ID 5535 //
34852 /* 95496 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34853 /* 95500 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34854 /* 95504 */ // (intrinsic_w_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34855 /* 95504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
34856 /* 95507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34857 /* 95509 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34858 /* 95511 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34859 /* 95513 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34860 /* 95517 */ GIR_RootConstrainSelectedInstOperands,
34861 /* 95518 */ // GIR_Coverage, 5535,
34862 /* 95518 */ GIR_EraseRootFromParent_Done,
34863 /* 95519 */ // Label 2947: @95519
34864 /* 95519 */ GIM_Try, /*On fail goto*//*Label 2948*/ GIMT_Encode4(95547), // Rule ID 5538 //
34865 /* 95524 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34866 /* 95528 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34867 /* 95532 */ // (intrinsic_w_chain:{ *:[v4f32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34868 /* 95532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
34869 /* 95535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34870 /* 95537 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34871 /* 95539 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34872 /* 95541 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34873 /* 95545 */ GIR_RootConstrainSelectedInstOperands,
34874 /* 95546 */ // GIR_Coverage, 5538,
34875 /* 95546 */ GIR_EraseRootFromParent_Done,
34876 /* 95547 */ // Label 2948: @95547
34877 /* 95547 */ GIM_Try, /*On fail goto*//*Label 2949*/ GIMT_Encode4(95575), // Rule ID 5539 //
34878 /* 95552 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34879 /* 95556 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34880 /* 95560 */ // (intrinsic_w_chain:{ *:[v4f32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34881 /* 95560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
34882 /* 95563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34883 /* 95565 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34884 /* 95567 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34885 /* 95569 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34886 /* 95573 */ GIR_RootConstrainSelectedInstOperands,
34887 /* 95574 */ // GIR_Coverage, 5539,
34888 /* 95574 */ GIR_EraseRootFromParent_Done,
34889 /* 95575 */ // Label 2949: @95575
34890 /* 95575 */ GIM_Try, /*On fail goto*//*Label 2950*/ GIMT_Encode4(95603), // Rule ID 5542 //
34891 /* 95580 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34892 /* 95584 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34893 /* 95588 */ // (intrinsic_w_chain:{ *:[v4f32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34894 /* 95588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
34895 /* 95591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34896 /* 95593 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34897 /* 95595 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34898 /* 95597 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34899 /* 95601 */ GIR_RootConstrainSelectedInstOperands,
34900 /* 95602 */ // GIR_Coverage, 5542,
34901 /* 95602 */ GIR_EraseRootFromParent_Done,
34902 /* 95603 */ // Label 2950: @95603
34903 /* 95603 */ GIM_Try, /*On fail goto*//*Label 2951*/ GIMT_Encode4(95631), // Rule ID 5543 //
34904 /* 95608 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
34905 /* 95612 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34906 /* 95616 */ // (intrinsic_w_chain:{ *:[v4f32] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
34907 /* 95616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
34908 /* 95619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34909 /* 95621 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34910 /* 95623 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34911 /* 95625 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34912 /* 95629 */ GIR_RootConstrainSelectedInstOperands,
34913 /* 95630 */ // GIR_Coverage, 5543,
34914 /* 95630 */ GIR_EraseRootFromParent_Done,
34915 /* 95631 */ // Label 2951: @95631
34916 /* 95631 */ GIM_Reject,
34917 /* 95632 */ // Label 2939: @95632
34918 /* 95632 */ GIM_Reject,
34919 /* 95633 */ // Label 2930: @95633
34920 /* 95633 */ GIM_Reject,
34921 /* 95634 */ // Label 2907: @95634
34922 /* 95634 */ GIM_Try, /*On fail goto*//*Label 2952*/ GIMT_Encode4(95896),
34923 /* 95639 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
34924 /* 95642 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34925 /* 95645 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34926 /* 95648 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34927 /* 95651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34928 /* 95655 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
34929 /* 95659 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
34930 /* 95663 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34931 /* 95667 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
34932 /* 95671 */ GIM_Try, /*On fail goto*//*Label 2953*/ GIMT_Encode4(95699), // Rule ID 5546 //
34933 /* 95676 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34934 /* 95680 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34935 /* 95684 */ // (intrinsic_w_chain:{ *:[v2i64] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
34936 /* 95684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
34937 /* 95687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34938 /* 95689 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34939 /* 95691 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34940 /* 95693 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34941 /* 95697 */ GIR_RootConstrainSelectedInstOperands,
34942 /* 95698 */ // GIR_Coverage, 5546,
34943 /* 95698 */ GIR_EraseRootFromParent_Done,
34944 /* 95699 */ // Label 2953: @95699
34945 /* 95699 */ GIM_Try, /*On fail goto*//*Label 2954*/ GIMT_Encode4(95727), // Rule ID 5547 //
34946 /* 95704 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
34947 /* 95708 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34948 /* 95712 */ // (intrinsic_w_chain:{ *:[v2i64] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
34949 /* 95712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
34950 /* 95715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34951 /* 95717 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34952 /* 95719 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34953 /* 95721 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34954 /* 95725 */ GIR_RootConstrainSelectedInstOperands,
34955 /* 95726 */ // GIR_Coverage, 5547,
34956 /* 95726 */ GIR_EraseRootFromParent_Done,
34957 /* 95727 */ // Label 2954: @95727
34958 /* 95727 */ GIM_Try, /*On fail goto*//*Label 2955*/ GIMT_Encode4(95755), // Rule ID 5550 //
34959 /* 95732 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34960 /* 95736 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34961 /* 95740 */ // (intrinsic_w_chain:{ *:[v2i64] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
34962 /* 95740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
34963 /* 95743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34964 /* 95745 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34965 /* 95747 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34966 /* 95749 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34967 /* 95753 */ GIR_RootConstrainSelectedInstOperands,
34968 /* 95754 */ // GIR_Coverage, 5550,
34969 /* 95754 */ GIR_EraseRootFromParent_Done,
34970 /* 95755 */ // Label 2955: @95755
34971 /* 95755 */ GIM_Try, /*On fail goto*//*Label 2956*/ GIMT_Encode4(95783), // Rule ID 5551 //
34972 /* 95760 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
34973 /* 95764 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34974 /* 95768 */ // (intrinsic_w_chain:{ *:[v2i64] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
34975 /* 95768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
34976 /* 95771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34977 /* 95773 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34978 /* 95775 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34979 /* 95777 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34980 /* 95781 */ GIR_RootConstrainSelectedInstOperands,
34981 /* 95782 */ // GIR_Coverage, 5551,
34982 /* 95782 */ GIR_EraseRootFromParent_Done,
34983 /* 95783 */ // Label 2956: @95783
34984 /* 95783 */ GIM_Try, /*On fail goto*//*Label 2957*/ GIMT_Encode4(95811), // Rule ID 5554 //
34985 /* 95788 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34986 /* 95792 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34987 /* 95796 */ // (intrinsic_w_chain:{ *:[v2i64] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
34988 /* 95796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
34989 /* 95799 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34990 /* 95801 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
34991 /* 95803 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
34992 /* 95805 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
34993 /* 95809 */ GIR_RootConstrainSelectedInstOperands,
34994 /* 95810 */ // GIR_Coverage, 5554,
34995 /* 95810 */ GIR_EraseRootFromParent_Done,
34996 /* 95811 */ // Label 2957: @95811
34997 /* 95811 */ GIM_Try, /*On fail goto*//*Label 2958*/ GIMT_Encode4(95839), // Rule ID 5555 //
34998 /* 95816 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
34999 /* 95820 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
35000 /* 95824 */ // (intrinsic_w_chain:{ *:[v2i64] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
35001 /* 95824 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
35002 /* 95827 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35003 /* 95829 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
35004 /* 95831 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
35005 /* 95833 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35006 /* 95837 */ GIR_RootConstrainSelectedInstOperands,
35007 /* 95838 */ // GIR_Coverage, 5555,
35008 /* 95838 */ GIR_EraseRootFromParent_Done,
35009 /* 95839 */ // Label 2958: @95839
35010 /* 95839 */ GIM_Try, /*On fail goto*//*Label 2959*/ GIMT_Encode4(95867), // Rule ID 5558 //
35011 /* 95844 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
35012 /* 95848 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
35013 /* 95852 */ // (intrinsic_w_chain:{ *:[v2i64] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
35014 /* 95852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
35015 /* 95855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35016 /* 95857 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
35017 /* 95859 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
35018 /* 95861 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35019 /* 95865 */ GIR_RootConstrainSelectedInstOperands,
35020 /* 95866 */ // GIR_Coverage, 5558,
35021 /* 95866 */ GIR_EraseRootFromParent_Done,
35022 /* 95867 */ // Label 2959: @95867
35023 /* 95867 */ GIM_Try, /*On fail goto*//*Label 2960*/ GIMT_Encode4(95895), // Rule ID 5559 //
35024 /* 95872 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
35025 /* 95876 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
35026 /* 95880 */ // (intrinsic_w_chain:{ *:[v2i64] } 3869:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
35027 /* 95880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
35028 /* 95883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35029 /* 95885 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
35030 /* 95887 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
35031 /* 95889 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35032 /* 95893 */ GIR_RootConstrainSelectedInstOperands,
35033 /* 95894 */ // GIR_Coverage, 5559,
35034 /* 95894 */ GIR_EraseRootFromParent_Done,
35035 /* 95895 */ // Label 2960: @95895
35036 /* 95895 */ GIM_Reject,
35037 /* 95896 */ // Label 2952: @95896
35038 /* 95896 */ GIM_Reject,
35039 /* 95897 */ // Label 2908: @95897
35040 /* 95897 */ GIM_Reject,
35041 /* 95898 */ // Label 2903: @95898
35042 /* 95898 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2961*/ GIMT_Encode4(95962), GIMT_Encode2(GIFBS_IsARM), // Rule ID 255 //
35043 /* 95905 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr),
35044 /* 95910 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35045 /* 95913 */ // MIs[0] cop
35046 /* 95913 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35047 /* 95916 */ // MIs[0] opc1
35048 /* 95916 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35049 /* 95919 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35050 /* 95923 */ // MIs[0] CRn
35051 /* 95923 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
35052 /* 95926 */ // MIs[0] CRm
35053 /* 95926 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35054 /* 95929 */ // MIs[0] opc2
35055 /* 95929 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
35056 /* 95932 */ // (intrinsic_void 3734:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
35057 /* 95932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR),
35058 /* 95935 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
35059 /* 95937 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
35060 /* 95939 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
35061 /* 95941 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
35062 /* 95943 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
35063 /* 95945 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
35064 /* 95947 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35065 /* 95950 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35066 /* 95956 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35067 /* 95960 */ GIR_RootConstrainSelectedInstOperands,
35068 /* 95961 */ // GIR_Coverage, 255,
35069 /* 95961 */ GIR_EraseRootFromParent_Done,
35070 /* 95962 */ // Label 2961: @95962
35071 /* 95962 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2962*/ GIMT_Encode4(96017), GIMT_Encode2(GIFBS_IsARM_PreV8), // Rule ID 256 //
35072 /* 95969 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2),
35073 /* 95974 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35074 /* 95977 */ // MIs[0] cop
35075 /* 95977 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35076 /* 95980 */ // MIs[0] opc1
35077 /* 95980 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35078 /* 95983 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35079 /* 95987 */ // MIs[0] CRn
35080 /* 95987 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
35081 /* 95990 */ // MIs[0] CRm
35082 /* 95990 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35083 /* 95993 */ // MIs[0] opc2
35084 /* 95993 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
35085 /* 95996 */ // (intrinsic_void 3735:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
35086 /* 95996 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR2),
35087 /* 95999 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
35088 /* 96001 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
35089 /* 96003 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
35090 /* 96005 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
35091 /* 96007 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
35092 /* 96009 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
35093 /* 96011 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35094 /* 96015 */ GIR_RootConstrainSelectedInstOperands,
35095 /* 96016 */ // GIR_Coverage, 256,
35096 /* 96016 */ GIR_EraseRootFromParent_Done,
35097 /* 96017 */ // Label 2962: @96017
35098 /* 96017 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2963*/ GIMT_Encode4(96081), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 593 //
35099 /* 96024 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr),
35100 /* 96029 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35101 /* 96032 */ // MIs[0] cop
35102 /* 96032 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35103 /* 96035 */ // MIs[0] opc1
35104 /* 96035 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35105 /* 96038 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35106 /* 96042 */ // MIs[0] CRn
35107 /* 96042 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
35108 /* 96045 */ // MIs[0] CRm
35109 /* 96045 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35110 /* 96048 */ // MIs[0] opc2
35111 /* 96048 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
35112 /* 96051 */ // (intrinsic_void 3734:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
35113 /* 96051 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR),
35114 /* 96054 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
35115 /* 96056 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
35116 /* 96058 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
35117 /* 96060 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
35118 /* 96062 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
35119 /* 96064 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
35120 /* 96066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35121 /* 96069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35122 /* 96075 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35123 /* 96079 */ GIR_RootConstrainSelectedInstOperands,
35124 /* 96080 */ // GIR_Coverage, 593,
35125 /* 96080 */ GIR_EraseRootFromParent_Done,
35126 /* 96081 */ // Label 2963: @96081
35127 /* 96081 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2964*/ GIMT_Encode4(96145), GIMT_Encode2(GIFBS_IsThumb2_PreV8), // Rule ID 594 //
35128 /* 96088 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2),
35129 /* 96093 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35130 /* 96096 */ // MIs[0] cop
35131 /* 96096 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
35132 /* 96099 */ // MIs[0] opc1
35133 /* 96099 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35134 /* 96102 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35135 /* 96106 */ // MIs[0] CRn
35136 /* 96106 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
35137 /* 96109 */ // MIs[0] CRm
35138 /* 96109 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
35139 /* 96112 */ // MIs[0] opc2
35140 /* 96112 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
35141 /* 96115 */ // (intrinsic_void 3735:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
35142 /* 96115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR2),
35143 /* 96118 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
35144 /* 96120 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
35145 /* 96122 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
35146 /* 96124 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
35147 /* 96126 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
35148 /* 96128 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
35149 /* 96130 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35150 /* 96133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35151 /* 96139 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35152 /* 96143 */ GIR_RootConstrainSelectedInstOperands,
35153 /* 96144 */ // GIR_Coverage, 594,
35154 /* 96144 */ GIR_EraseRootFromParent_Done,
35155 /* 96145 */ // Label 2964: @96145
35156 /* 96145 */ GIM_Reject,
35157 /* 96146 */ // Label 2898: @96146
35158 /* 96146 */ GIM_Reject,
35159 /* 96147 */ // Label 23: @96147
35160 /* 96147 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 2968*/ GIMT_Encode4(96285),
35161 /* 96158 */ /*GILLT_v8s16*//*Label 2965*/ GIMT_Encode4(96174), GIMT_Encode4(0),
35162 /* 96166 */ /*GILLT_v4s32*//*Label 2966*/ GIMT_Encode4(96211),
35163 /* 96170 */ /*GILLT_v2s64*//*Label 2967*/ GIMT_Encode4(96248),
35164 /* 96174 */ // Label 2965: @96174
35165 /* 96174 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2969*/ GIMT_Encode4(96210), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3055 //
35166 /* 96181 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
35167 /* 96184 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35168 /* 96188 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35169 /* 96192 */ // (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
35170 /* 96192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16),
35171 /* 96195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35172 /* 96197 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35173 /* 96199 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35174 /* 96202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35175 /* 96208 */ GIR_RootConstrainSelectedInstOperands,
35176 /* 96209 */ // GIR_Coverage, 3055,
35177 /* 96209 */ GIR_EraseRootFromParent_Done,
35178 /* 96210 */ // Label 2969: @96210
35179 /* 96210 */ GIM_Reject,
35180 /* 96211 */ // Label 2966: @96211
35181 /* 96211 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2970*/ GIMT_Encode4(96247), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3056 //
35182 /* 96218 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
35183 /* 96221 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35184 /* 96225 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35185 /* 96229 */ // (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
35186 /* 96229 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32),
35187 /* 96232 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35188 /* 96234 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35189 /* 96236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35190 /* 96239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35191 /* 96245 */ GIR_RootConstrainSelectedInstOperands,
35192 /* 96246 */ // GIR_Coverage, 3056,
35193 /* 96246 */ GIR_EraseRootFromParent_Done,
35194 /* 96247 */ // Label 2970: @96247
35195 /* 96247 */ GIM_Reject,
35196 /* 96248 */ // Label 2967: @96248
35197 /* 96248 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2971*/ GIMT_Encode4(96284), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3057 //
35198 /* 96255 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
35199 /* 96258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35200 /* 96262 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35201 /* 96266 */ // (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
35202 /* 96266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64),
35203 /* 96269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35204 /* 96271 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35205 /* 96273 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35206 /* 96276 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35207 /* 96282 */ GIR_RootConstrainSelectedInstOperands,
35208 /* 96283 */ // GIR_Coverage, 3057,
35209 /* 96283 */ GIR_EraseRootFromParent_Done,
35210 /* 96284 */ // Label 2971: @96284
35211 /* 96284 */ GIM_Reject,
35212 /* 96285 */ // Label 2968: @96285
35213 /* 96285 */ GIM_Reject,
35214 /* 96286 */ // Label 24: @96286
35215 /* 96286 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 2975*/ GIMT_Encode4(96428),
35216 /* 96297 */ /*GILLT_v8s8*//*Label 2972*/ GIMT_Encode4(96317), GIMT_Encode4(0),
35217 /* 96305 */ /*GILLT_v4s16*//*Label 2973*/ GIMT_Encode4(96354), GIMT_Encode4(0),
35218 /* 96313 */ /*GILLT_v2s32*//*Label 2974*/ GIMT_Encode4(96391),
35219 /* 96317 */ // Label 2972: @96317
35220 /* 96317 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2976*/ GIMT_Encode4(96353), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1748 //
35221 /* 96324 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
35222 /* 96327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35223 /* 96331 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35224 /* 96335 */ // (trunc:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) => (VMOVNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
35225 /* 96335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv8i8),
35226 /* 96338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35227 /* 96340 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35228 /* 96342 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35229 /* 96345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35230 /* 96351 */ GIR_RootConstrainSelectedInstOperands,
35231 /* 96352 */ // GIR_Coverage, 1748,
35232 /* 96352 */ GIR_EraseRootFromParent_Done,
35233 /* 96353 */ // Label 2976: @96353
35234 /* 96353 */ GIM_Reject,
35235 /* 96354 */ // Label 2973: @96354
35236 /* 96354 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2977*/ GIMT_Encode4(96390), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1749 //
35237 /* 96361 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
35238 /* 96364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35239 /* 96368 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35240 /* 96372 */ // (trunc:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) => (VMOVNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
35241 /* 96372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv4i16),
35242 /* 96375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35243 /* 96377 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35244 /* 96379 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35245 /* 96382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35246 /* 96388 */ GIR_RootConstrainSelectedInstOperands,
35247 /* 96389 */ // GIR_Coverage, 1749,
35248 /* 96389 */ GIR_EraseRootFromParent_Done,
35249 /* 96390 */ // Label 2977: @96390
35250 /* 96390 */ GIM_Reject,
35251 /* 96391 */ // Label 2974: @96391
35252 /* 96391 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2978*/ GIMT_Encode4(96427), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1750 //
35253 /* 96398 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
35254 /* 96401 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35255 /* 96405 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35256 /* 96409 */ // (trunc:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) => (VMOVNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
35257 /* 96409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv2i32),
35258 /* 96412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35259 /* 96414 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35260 /* 96416 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35261 /* 96419 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35262 /* 96425 */ GIR_RootConstrainSelectedInstOperands,
35263 /* 96426 */ // GIR_Coverage, 1750,
35264 /* 96426 */ GIR_EraseRootFromParent_Done,
35265 /* 96427 */ // Label 2978: @96427
35266 /* 96427 */ GIM_Reject,
35267 /* 96428 */ // Label 2975: @96428
35268 /* 96428 */ GIM_Reject,
35269 /* 96429 */ // Label 25: @96429
35270 /* 96429 */ GIM_Try, /*On fail goto*//*Label 2979*/ GIMT_Encode4(96740),
35271 /* 96434 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35272 /* 96437 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2980*/ GIMT_Encode4(96477), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 403 //
35273 /* 96444 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
35274 /* 96448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35275 /* 96452 */ // MIs[0] Operand 1
35276 /* 96452 */ // No operand predicates
35277 /* 96452 */ // (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm => (t2MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
35278 /* 96452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
35279 /* 96455 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35280 /* 96457 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
35281 /* 96460 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35282 /* 96463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35283 /* 96469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35284 /* 96475 */ GIR_RootConstrainSelectedInstOperands,
35285 /* 96476 */ // GIR_Coverage, 403,
35286 /* 96476 */ GIR_EraseRootFromParent_Done,
35287 /* 96477 */ // Label 2980: @96477
35288 /* 96477 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2981*/ GIMT_Encode4(96517), GIMT_Encode2(GIFBS_IsARM), // Rule ID 56 //
35289 /* 96484 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
35290 /* 96488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35291 /* 96492 */ // MIs[0] Operand 1
35292 /* 96492 */ // No operand predicates
35293 /* 96492 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm => (MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
35294 /* 96492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi),
35295 /* 96495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35296 /* 96497 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
35297 /* 96500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35298 /* 96503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35299 /* 96509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35300 /* 96515 */ GIR_RootConstrainSelectedInstOperands,
35301 /* 96516 */ // GIR_Coverage, 56,
35302 /* 96516 */ GIR_EraseRootFromParent_Done,
35303 /* 96517 */ // Label 2981: @96517
35304 /* 96517 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2982*/ GIMT_Encode4(96551), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 57 //
35305 /* 96524 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
35306 /* 96528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35307 /* 96532 */ // MIs[0] Operand 1
35308 /* 96532 */ // No operand predicates
35309 /* 96532 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
35310 /* 96532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi16),
35311 /* 96535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35312 /* 96537 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
35313 /* 96540 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35314 /* 96543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35315 /* 96549 */ GIR_RootConstrainSelectedInstOperands,
35316 /* 96550 */ // GIR_Coverage, 57,
35317 /* 96550 */ GIR_EraseRootFromParent_Done,
35318 /* 96551 */ // Label 2982: @96551
35319 /* 96551 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2983*/ GIMT_Encode4(96593), GIMT_Encode2(GIFBS_IsARM), // Rule ID 167 //
35320 /* 96558 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not),
35321 /* 96562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35322 /* 96566 */ // MIs[0] Operand 1
35323 /* 96566 */ // No operand predicates
35324 /* 96566 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm => (MVNi:{ *:[i32] } (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm))
35325 /* 96566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNi),
35326 /* 96569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35327 /* 96571 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm
35328 /* 96576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35329 /* 96579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35330 /* 96585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35331 /* 96591 */ GIR_RootConstrainSelectedInstOperands,
35332 /* 96592 */ // GIR_Coverage, 167,
35333 /* 96592 */ GIR_EraseRootFromParent_Done,
35334 /* 96593 */ // Label 2983: @96593
35335 /* 96593 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2984*/ GIMT_Encode4(96618), GIMT_Encode2(GIFBS_IsARM), // Rule ID 267 //
35336 /* 96600 */ GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_arm_i32imm),
35337 /* 96604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35338 /* 96608 */ // MIs[0] Operand 1
35339 /* 96608 */ // No operand predicates
35340 /* 96608 */ // (imm:{ *:[i32] })<<P:Predicate_arm_i32imm>>:$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
35341 /* 96608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi32imm),
35342 /* 96611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35343 /* 96613 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
35344 /* 96616 */ GIR_RootConstrainSelectedInstOperands,
35345 /* 96617 */ // GIR_Coverage, 267,
35346 /* 96617 */ GIR_EraseRootFromParent_Done,
35347 /* 96618 */ // Label 2984: @96618
35348 /* 96618 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2985*/ GIMT_Encode4(96658), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 321 //
35349 /* 96625 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr),
35350 /* 96629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
35351 /* 96633 */ // MIs[0] Operand 1
35352 /* 96633 */ // No operand predicates
35353 /* 96633 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8 => (tMOVi8:{ *:[i32] } (imm:{ *:[i32] }):$imm8)
35354 /* 96633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
35355 /* 96636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35356 /* 96638 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
35357 /* 96644 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm8
35358 /* 96647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35359 /* 96650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35360 /* 96656 */ GIR_RootConstrainSelectedInstOperands,
35361 /* 96657 */ // GIR_Coverage, 321,
35362 /* 96657 */ GIR_EraseRootFromParent_Done,
35363 /* 96658 */ // Label 2985: @96658
35364 /* 96658 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2986*/ GIMT_Encode4(96692), GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb), // Rule ID 404 //
35365 /* 96665 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
35366 /* 96669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35367 /* 96673 */ // MIs[0] Operand 1
35368 /* 96673 */ // No operand predicates
35369 /* 96673 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (t2MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
35370 /* 96673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16),
35371 /* 96676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35372 /* 96678 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
35373 /* 96681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35374 /* 96684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35375 /* 96690 */ GIR_RootConstrainSelectedInstOperands,
35376 /* 96691 */ // GIR_Coverage, 404,
35377 /* 96691 */ GIR_EraseRootFromParent_Done,
35378 /* 96692 */ // Label 2986: @96692
35379 /* 96692 */ GIM_Try, /*On fail goto*//*Label 2987*/ GIMT_Encode4(96739),
35380 /* 96697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35381 /* 96701 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2988*/ GIMT_Encode4(96721), GIMT_Encode2(GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only), // Rule ID 352 //
35382 /* 96708 */ // MIs[0] Operand 1
35383 /* 96708 */ // No operand predicates
35384 /* 96708 */ // (imm:{ *:[i32] }):$src => (tMOVi32imm:{ *:[i32] }:{ *:[i32] } (imm:{ *:[i32] }):$src)
35385 /* 96708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi32imm),
35386 /* 96711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35387 /* 96713 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
35388 /* 96716 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::CPSR*/0,
35389 /* 96719 */ GIR_RootConstrainSelectedInstOperands,
35390 /* 96720 */ // GIR_Coverage, 352,
35391 /* 96720 */ GIR_EraseRootFromParent_Done,
35392 /* 96721 */ // Label 2988: @96721
35393 /* 96721 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2989*/ GIMT_Encode4(96738), GIMT_Encode2(GIFBS_IsThumb_UseMovt), // Rule ID 581 //
35394 /* 96728 */ // MIs[0] Operand 1
35395 /* 96728 */ // No operand predicates
35396 /* 96728 */ // (imm:{ *:[i32] }):$src => (t2MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
35397 /* 96728 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm),
35398 /* 96731 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
35399 /* 96733 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
35400 /* 96736 */ GIR_RootConstrainSelectedInstOperands,
35401 /* 96737 */ // GIR_Coverage, 581,
35402 /* 96737 */ GIR_EraseRootFromParent_Done,
35403 /* 96738 */ // Label 2989: @96738
35404 /* 96738 */ GIM_Reject,
35405 /* 96739 */ // Label 2987: @96739
35406 /* 96739 */ GIM_Reject,
35407 /* 96740 */ // Label 2979: @96740
35408 /* 96740 */ GIM_Reject,
35409 /* 96741 */ // Label 26: @96741
35410 /* 96741 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 2992*/ GIMT_Encode4(96834),
35411 /* 96752 */ /*GILLT_s32*//*Label 2990*/ GIMT_Encode4(96760),
35412 /* 96756 */ /*GILLT_s64*//*Label 2991*/ GIMT_Encode4(96797),
35413 /* 96760 */ // Label 2990: @96760
35414 /* 96760 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2993*/ GIMT_Encode4(96796), GIMT_Encode2(GIFBS_HasVFP3), // Rule ID 848 //
35415 /* 96767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
35416 /* 96771 */ // MIs[0] Operand 1
35417 /* 96771 */ // No operand predicates
35418 /* 96771 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f32imm),
35419 /* 96775 */ // (fpimm:{ *:[f32] })<<P:Predicate_vfp_f32imm>><<X:vfp_f32imm_xform>>:$imm => (FCONSTS:{ *:[f32] } (vfp_f32imm_xform:{ *:[f32] } (fpimm:{ *:[f32] }):$imm))
35420 /* 96775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTS),
35421 /* 96778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
35422 /* 96780 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF32Imm), // imm
35423 /* 96785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35424 /* 96788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35425 /* 96794 */ GIR_RootConstrainSelectedInstOperands,
35426 /* 96795 */ // GIR_Coverage, 848,
35427 /* 96795 */ GIR_EraseRootFromParent_Done,
35428 /* 96796 */ // Label 2993: @96796
35429 /* 96796 */ GIM_Reject,
35430 /* 96797 */ // Label 2991: @96797
35431 /* 96797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2994*/ GIMT_Encode4(96833), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP3), // Rule ID 847 //
35432 /* 96804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35433 /* 96808 */ // MIs[0] Operand 1
35434 /* 96808 */ // No operand predicates
35435 /* 96808 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f64imm),
35436 /* 96812 */ // (fpimm:{ *:[f64] })<<P:Predicate_vfp_f64imm>><<X:vfp_f64imm_xform>>:$imm => (FCONSTD:{ *:[f64] } (vfp_f64imm_xform:{ *:[f64] } (fpimm:{ *:[f64] }):$imm))
35437 /* 96812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTD),
35438 /* 96815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
35439 /* 96817 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF64Imm), // imm
35440 /* 96822 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35441 /* 96825 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35442 /* 96831 */ GIR_RootConstrainSelectedInstOperands,
35443 /* 96832 */ // GIR_Coverage, 847,
35444 /* 96832 */ GIR_EraseRootFromParent_Done,
35445 /* 96833 */ // Label 2994: @96833
35446 /* 96833 */ GIM_Reject,
35447 /* 96834 */ // Label 2992: @96834
35448 /* 96834 */ GIM_Reject,
35449 /* 96835 */ // Label 27: @96835
35450 /* 96835 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 2998*/ GIMT_Encode4(96973),
35451 /* 96846 */ /*GILLT_v8s16*//*Label 2995*/ GIMT_Encode4(96862), GIMT_Encode4(0),
35452 /* 96854 */ /*GILLT_v4s32*//*Label 2996*/ GIMT_Encode4(96899),
35453 /* 96858 */ /*GILLT_v2s64*//*Label 2997*/ GIMT_Encode4(96936),
35454 /* 96862 */ // Label 2995: @96862
35455 /* 96862 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 2999*/ GIMT_Encode4(96898), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1760 //
35456 /* 96869 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
35457 /* 96872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35458 /* 96876 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35459 /* 96880 */ // (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
35460 /* 96880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv8i16),
35461 /* 96883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35462 /* 96885 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35463 /* 96887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35464 /* 96890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35465 /* 96896 */ GIR_RootConstrainSelectedInstOperands,
35466 /* 96897 */ // GIR_Coverage, 1760,
35467 /* 96897 */ GIR_EraseRootFromParent_Done,
35468 /* 96898 */ // Label 2999: @96898
35469 /* 96898 */ GIM_Reject,
35470 /* 96899 */ // Label 2996: @96899
35471 /* 96899 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3000*/ GIMT_Encode4(96935), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1761 //
35472 /* 96906 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
35473 /* 96909 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35474 /* 96913 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35475 /* 96917 */ // (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
35476 /* 96917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv4i32),
35477 /* 96920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35478 /* 96922 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35479 /* 96924 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35480 /* 96927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35481 /* 96933 */ GIR_RootConstrainSelectedInstOperands,
35482 /* 96934 */ // GIR_Coverage, 1761,
35483 /* 96934 */ GIR_EraseRootFromParent_Done,
35484 /* 96935 */ // Label 3000: @96935
35485 /* 96935 */ GIM_Reject,
35486 /* 96936 */ // Label 2997: @96936
35487 /* 96936 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3001*/ GIMT_Encode4(96972), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1762 //
35488 /* 96943 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
35489 /* 96946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35490 /* 96950 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35491 /* 96954 */ // (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
35492 /* 96954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv2i64),
35493 /* 96957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35494 /* 96959 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35495 /* 96961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35496 /* 96964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35497 /* 96970 */ GIR_RootConstrainSelectedInstOperands,
35498 /* 96971 */ // GIR_Coverage, 1762,
35499 /* 96971 */ GIR_EraseRootFromParent_Done,
35500 /* 96972 */ // Label 3001: @96972
35501 /* 96972 */ GIM_Reject,
35502 /* 96973 */ // Label 2998: @96973
35503 /* 96973 */ GIM_Reject,
35504 /* 96974 */ // Label 28: @96974
35505 /* 96974 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3005*/ GIMT_Encode4(97563),
35506 /* 96985 */ /*GILLT_s32*//*Label 3002*/ GIMT_Encode4(97033), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
35507 /* 97021 */ /*GILLT_v8s16*//*Label 3003*/ GIMT_Encode4(97313), GIMT_Encode4(0),
35508 /* 97029 */ /*GILLT_v4s32*//*Label 3004*/ GIMT_Encode4(97382),
35509 /* 97033 */ // Label 3002: @97033
35510 /* 97033 */ GIM_Try, /*On fail goto*//*Label 3006*/ GIMT_Encode4(97312),
35511 /* 97038 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35512 /* 97041 */ GIM_Try, /*On fail goto*//*Label 3007*/ GIMT_Encode4(97127),
35513 /* 97046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
35514 /* 97050 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
35515 /* 97054 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3008*/ GIMT_Encode4(97090), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 339 //
35516 /* 97061 */ // MIs[0] Operand 2
35517 /* 97061 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
35518 /* 97072 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }) => (tSXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
35519 /* 97072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTB),
35520 /* 97075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35521 /* 97077 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
35522 /* 97079 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35523 /* 97082 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35524 /* 97088 */ GIR_RootConstrainSelectedInstOperands,
35525 /* 97089 */ // GIR_Coverage, 339,
35526 /* 97089 */ GIR_EraseRootFromParent_Done,
35527 /* 97090 */ // Label 3008: @97090
35528 /* 97090 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3009*/ GIMT_Encode4(97126), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 340 //
35529 /* 97097 */ // MIs[0] Operand 2
35530 /* 97097 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
35531 /* 97108 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }) => (tSXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
35532 /* 97108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTH),
35533 /* 97111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35534 /* 97113 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
35535 /* 97115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35536 /* 97118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35537 /* 97124 */ GIR_RootConstrainSelectedInstOperands,
35538 /* 97125 */ // GIR_Coverage, 340,
35539 /* 97125 */ GIR_EraseRootFromParent_Done,
35540 /* 97126 */ // Label 3009: @97126
35541 /* 97126 */ GIM_Reject,
35542 /* 97127 */ // Label 3007: @97127
35543 /* 97127 */ GIM_Try, /*On fail goto*//*Label 3010*/ GIMT_Encode4(97219),
35544 /* 97132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35545 /* 97136 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35546 /* 97140 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3011*/ GIMT_Encode4(97179), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2197 //
35547 /* 97147 */ // MIs[0] Operand 2
35548 /* 97147 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
35549 /* 97158 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (SXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
35550 /* 97158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB),
35551 /* 97161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35552 /* 97163 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
35553 /* 97165 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35554 /* 97168 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35555 /* 97171 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35556 /* 97177 */ GIR_RootConstrainSelectedInstOperands,
35557 /* 97178 */ // GIR_Coverage, 2197,
35558 /* 97178 */ GIR_EraseRootFromParent_Done,
35559 /* 97179 */ // Label 3011: @97179
35560 /* 97179 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3012*/ GIMT_Encode4(97218), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 2198 //
35561 /* 97186 */ // MIs[0] Operand 2
35562 /* 97186 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
35563 /* 97197 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (SXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
35564 /* 97197 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTH),
35565 /* 97200 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35566 /* 97202 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
35567 /* 97204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35568 /* 97207 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35569 /* 97210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35570 /* 97216 */ GIR_RootConstrainSelectedInstOperands,
35571 /* 97217 */ // GIR_Coverage, 2198,
35572 /* 97217 */ GIR_EraseRootFromParent_Done,
35573 /* 97218 */ // Label 3012: @97218
35574 /* 97218 */ GIM_Reject,
35575 /* 97219 */ // Label 3010: @97219
35576 /* 97219 */ GIM_Try, /*On fail goto*//*Label 3013*/ GIMT_Encode4(97311),
35577 /* 97224 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35578 /* 97228 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35579 /* 97232 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3014*/ GIMT_Encode4(97271), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2441 //
35580 /* 97239 */ // MIs[0] Operand 2
35581 /* 97239 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
35582 /* 97250 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (t2SXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
35583 /* 97250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB),
35584 /* 97253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35585 /* 97255 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
35586 /* 97257 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35587 /* 97260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35588 /* 97263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35589 /* 97269 */ GIR_RootConstrainSelectedInstOperands,
35590 /* 97270 */ // GIR_Coverage, 2441,
35591 /* 97270 */ GIR_EraseRootFromParent_Done,
35592 /* 97271 */ // Label 3014: @97271
35593 /* 97271 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3015*/ GIMT_Encode4(97310), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 2442 //
35594 /* 97278 */ // MIs[0] Operand 2
35595 /* 97278 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
35596 /* 97289 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (t2SXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
35597 /* 97289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTH),
35598 /* 97292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35599 /* 97294 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
35600 /* 97296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35601 /* 97299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35602 /* 97302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35603 /* 97308 */ GIR_RootConstrainSelectedInstOperands,
35604 /* 97309 */ // GIR_Coverage, 2442,
35605 /* 97309 */ GIR_EraseRootFromParent_Done,
35606 /* 97310 */ // Label 3015: @97310
35607 /* 97310 */ GIM_Reject,
35608 /* 97311 */ // Label 3013: @97311
35609 /* 97311 */ GIM_Reject,
35610 /* 97312 */ // Label 3006: @97312
35611 /* 97312 */ GIM_Reject,
35612 /* 97313 */ // Label 3003: @97313
35613 /* 97313 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3016*/ GIMT_Encode4(97381), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4117 //
35614 /* 97320 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
35615 /* 97323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35616 /* 97327 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35617 /* 97331 */ // MIs[0] Operand 2
35618 /* 97331 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
35619 /* 97342 */ // (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, v8i8:{ *:[Other] }) => (MVE_VMOVLs8bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src)
35620 /* 97342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
35621 /* 97345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
35622 /* 97349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
35623 /* 97354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh),
35624 /* 97357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35625 /* 97359 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
35626 /* 97361 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35627 /* 97364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35628 /* 97370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35629 /* 97376 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35630 /* 97379 */ GIR_RootConstrainSelectedInstOperands,
35631 /* 97380 */ // GIR_Coverage, 4117,
35632 /* 97380 */ GIR_EraseRootFromParent_Done,
35633 /* 97381 */ // Label 3016: @97381
35634 /* 97381 */ GIM_Reject,
35635 /* 97382 */ // Label 3004: @97382
35636 /* 97382 */ GIM_Try, /*On fail goto*//*Label 3017*/ GIMT_Encode4(97562),
35637 /* 97387 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
35638 /* 97390 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35639 /* 97394 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35640 /* 97398 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3018*/ GIMT_Encode4(97455), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4116 //
35641 /* 97405 */ // MIs[0] Operand 2
35642 /* 97405 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
35643 /* 97416 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i16:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src)
35644 /* 97416 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
35645 /* 97419 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
35646 /* 97423 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
35647 /* 97428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh),
35648 /* 97431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35649 /* 97433 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
35650 /* 97435 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35651 /* 97438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35652 /* 97444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35653 /* 97450 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35654 /* 97453 */ GIR_RootConstrainSelectedInstOperands,
35655 /* 97454 */ // GIR_Coverage, 4116,
35656 /* 97454 */ GIR_EraseRootFromParent_Done,
35657 /* 97455 */ // Label 3018: @97455
35658 /* 97455 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3019*/ GIMT_Encode4(97561), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4118 //
35659 /* 97462 */ // MIs[0] Operand 2
35660 /* 97462 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
35661 /* 97473 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i8:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } (MVE_VMOVLs8bh:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src))
35662 /* 97473 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
35663 /* 97476 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
35664 /* 97480 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
35665 /* 97485 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
35666 /* 97488 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
35667 /* 97492 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
35668 /* 97497 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
35669 /* 97500 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh),
35670 /* 97504 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
35671 /* 97509 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
35672 /* 97513 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
35673 /* 97516 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35674 /* 97522 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35675 /* 97528 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
35676 /* 97531 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
35677 /* 97533 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh),
35678 /* 97536 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35679 /* 97538 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
35680 /* 97541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35681 /* 97544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35682 /* 97550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35683 /* 97556 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
35684 /* 97559 */ GIR_RootConstrainSelectedInstOperands,
35685 /* 97560 */ // GIR_Coverage, 4118,
35686 /* 97560 */ GIR_EraseRootFromParent_Done,
35687 /* 97561 */ // Label 3019: @97561
35688 /* 97561 */ GIM_Reject,
35689 /* 97562 */ // Label 3017: @97562
35690 /* 97562 */ GIM_Reject,
35691 /* 97563 */ // Label 3005: @97563
35692 /* 97563 */ GIM_Reject,
35693 /* 97564 */ // Label 29: @97564
35694 /* 97564 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(10), GIMT_Encode2(14), /*)*//*default:*//*Label 3023*/ GIMT_Encode4(98251),
35695 /* 97575 */ /*GILLT_v8s16*//*Label 3020*/ GIMT_Encode4(97591), GIMT_Encode4(0),
35696 /* 97583 */ /*GILLT_v4s32*//*Label 3021*/ GIMT_Encode4(97811),
35697 /* 97587 */ /*GILLT_v2s64*//*Label 3022*/ GIMT_Encode4(98031),
35698 /* 97591 */ // Label 3020: @97591
35699 /* 97591 */ GIM_Try, /*On fail goto*//*Label 3024*/ GIMT_Encode4(97810),
35700 /* 97596 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
35701 /* 97599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35702 /* 97603 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3025*/ GIMT_Encode4(97662), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1335 //
35703 /* 97610 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35704 /* 97614 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
35705 /* 97618 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
35706 /* 97622 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
35707 /* 97626 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35708 /* 97631 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35709 /* 97636 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35710 /* 97638 */ // (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
35711 /* 97638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv8i16),
35712 /* 97641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35713 /* 97643 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
35714 /* 97647 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
35715 /* 97651 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35716 /* 97654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35717 /* 97660 */ GIR_RootConstrainSelectedInstOperands,
35718 /* 97661 */ // GIR_Coverage, 1335,
35719 /* 97661 */ GIR_EraseRootFromParent_Done,
35720 /* 97662 */ // Label 3025: @97662
35721 /* 97662 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3026*/ GIMT_Encode4(97721), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1338 //
35722 /* 97669 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35723 /* 97673 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
35724 /* 97677 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
35725 /* 97681 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
35726 /* 97685 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35727 /* 97690 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35728 /* 97695 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35729 /* 97697 */ // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
35730 /* 97697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16),
35731 /* 97700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35732 /* 97702 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
35733 /* 97706 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
35734 /* 97710 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35735 /* 97713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35736 /* 97719 */ GIR_RootConstrainSelectedInstOperands,
35737 /* 97720 */ // GIR_Coverage, 1338,
35738 /* 97720 */ GIR_EraseRootFromParent_Done,
35739 /* 97721 */ // Label 3026: @97721
35740 /* 97721 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3027*/ GIMT_Encode4(97780), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2967 //
35741 /* 97728 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35742 /* 97732 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
35743 /* 97736 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
35744 /* 97740 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
35745 /* 97744 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35746 /* 97749 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35747 /* 97754 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35748 /* 97756 */ // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB)
35749 /* 97756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16),
35750 /* 97759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35751 /* 97761 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA
35752 /* 97765 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB
35753 /* 97769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35754 /* 97772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35755 /* 97778 */ GIR_RootConstrainSelectedInstOperands,
35756 /* 97779 */ // GIR_Coverage, 2967,
35757 /* 97779 */ GIR_EraseRootFromParent_Done,
35758 /* 97780 */ // Label 3027: @97780
35759 /* 97780 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3028*/ GIMT_Encode4(97809), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1763 //
35760 /* 97787 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35761 /* 97791 */ // (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
35762 /* 97791 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16),
35763 /* 97794 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35764 /* 97796 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35765 /* 97798 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35766 /* 97801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35767 /* 97807 */ GIR_RootConstrainSelectedInstOperands,
35768 /* 97808 */ // GIR_Coverage, 1763,
35769 /* 97808 */ GIR_EraseRootFromParent_Done,
35770 /* 97809 */ // Label 3028: @97809
35771 /* 97809 */ GIM_Reject,
35772 /* 97810 */ // Label 3024: @97810
35773 /* 97810 */ GIM_Reject,
35774 /* 97811 */ // Label 3021: @97811
35775 /* 97811 */ GIM_Try, /*On fail goto*//*Label 3029*/ GIMT_Encode4(98030),
35776 /* 97816 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
35777 /* 97819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35778 /* 97823 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3030*/ GIMT_Encode4(97882), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1336 //
35779 /* 97830 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35780 /* 97834 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
35781 /* 97838 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
35782 /* 97842 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
35783 /* 97846 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35784 /* 97851 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35785 /* 97856 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35786 /* 97858 */ // (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
35787 /* 97858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv4i32),
35788 /* 97861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35789 /* 97863 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
35790 /* 97867 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
35791 /* 97871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35792 /* 97874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35793 /* 97880 */ GIR_RootConstrainSelectedInstOperands,
35794 /* 97881 */ // GIR_Coverage, 1336,
35795 /* 97881 */ GIR_EraseRootFromParent_Done,
35796 /* 97882 */ // Label 3030: @97882
35797 /* 97882 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3031*/ GIMT_Encode4(97941), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1339 //
35798 /* 97889 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35799 /* 97893 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
35800 /* 97897 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
35801 /* 97901 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
35802 /* 97905 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35803 /* 97910 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35804 /* 97915 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35805 /* 97917 */ // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
35806 /* 97917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32),
35807 /* 97920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35808 /* 97922 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
35809 /* 97926 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
35810 /* 97930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35811 /* 97933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35812 /* 97939 */ GIR_RootConstrainSelectedInstOperands,
35813 /* 97940 */ // GIR_Coverage, 1339,
35814 /* 97940 */ GIR_EraseRootFromParent_Done,
35815 /* 97941 */ // Label 3031: @97941
35816 /* 97941 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3032*/ GIMT_Encode4(98000), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2968 //
35817 /* 97948 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35818 /* 97952 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
35819 /* 97956 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
35820 /* 97960 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
35821 /* 97964 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35822 /* 97969 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35823 /* 97974 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35824 /* 97976 */ // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB)
35825 /* 97976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32),
35826 /* 97979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35827 /* 97981 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA
35828 /* 97985 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB
35829 /* 97989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35830 /* 97992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35831 /* 97998 */ GIR_RootConstrainSelectedInstOperands,
35832 /* 97999 */ // GIR_Coverage, 2968,
35833 /* 97999 */ GIR_EraseRootFromParent_Done,
35834 /* 98000 */ // Label 3032: @98000
35835 /* 98000 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3033*/ GIMT_Encode4(98029), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1764 //
35836 /* 98007 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35837 /* 98011 */ // (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
35838 /* 98011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32),
35839 /* 98014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35840 /* 98016 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35841 /* 98018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35842 /* 98021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35843 /* 98027 */ GIR_RootConstrainSelectedInstOperands,
35844 /* 98028 */ // GIR_Coverage, 1764,
35845 /* 98028 */ GIR_EraseRootFromParent_Done,
35846 /* 98029 */ // Label 3033: @98029
35847 /* 98029 */ GIM_Reject,
35848 /* 98030 */ // Label 3029: @98030
35849 /* 98030 */ GIM_Reject,
35850 /* 98031 */ // Label 3022: @98031
35851 /* 98031 */ GIM_Try, /*On fail goto*//*Label 3034*/ GIMT_Encode4(98250),
35852 /* 98036 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
35853 /* 98039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
35854 /* 98043 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3035*/ GIMT_Encode4(98102), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1337 //
35855 /* 98050 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35856 /* 98054 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
35857 /* 98058 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
35858 /* 98062 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
35859 /* 98066 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35860 /* 98071 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35861 /* 98076 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35862 /* 98078 */ // (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
35863 /* 98078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv2i64),
35864 /* 98081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35865 /* 98083 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
35866 /* 98087 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
35867 /* 98091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35868 /* 98094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35869 /* 98100 */ GIR_RootConstrainSelectedInstOperands,
35870 /* 98101 */ // GIR_Coverage, 1337,
35871 /* 98101 */ GIR_EraseRootFromParent_Done,
35872 /* 98102 */ // Label 3035: @98102
35873 /* 98102 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3036*/ GIMT_Encode4(98161), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1340 //
35874 /* 98109 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35875 /* 98113 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
35876 /* 98117 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
35877 /* 98121 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
35878 /* 98125 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35879 /* 98130 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35880 /* 98135 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35881 /* 98137 */ // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
35882 /* 98137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv2i64),
35883 /* 98140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35884 /* 98142 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
35885 /* 98146 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
35886 /* 98150 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35887 /* 98153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35888 /* 98159 */ GIR_RootConstrainSelectedInstOperands,
35889 /* 98160 */ // GIR_Coverage, 1340,
35890 /* 98160 */ GIR_EraseRootFromParent_Done,
35891 /* 98161 */ // Label 3036: @98161
35892 /* 98161 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3037*/ GIMT_Encode4(98220), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2969 //
35893 /* 98168 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35894 /* 98172 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
35895 /* 98176 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
35896 /* 98180 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
35897 /* 98184 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35898 /* 98189 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35899 /* 98194 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35900 /* 98196 */ // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$opA, DPR:{ *:[v2i32] }:$opB)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$opA, DPR:{ *:[v2i32] }:$opB)
35901 /* 98196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv2i64),
35902 /* 98199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35903 /* 98201 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA
35904 /* 98205 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB
35905 /* 98209 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35906 /* 98212 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35907 /* 98218 */ GIR_RootConstrainSelectedInstOperands,
35908 /* 98219 */ // GIR_Coverage, 2969,
35909 /* 98219 */ GIR_EraseRootFromParent_Done,
35910 /* 98220 */ // Label 3037: @98220
35911 /* 98220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3038*/ GIMT_Encode4(98249), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1765 //
35912 /* 98227 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
35913 /* 98231 */ // (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
35914 /* 98231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64),
35915 /* 98234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
35916 /* 98236 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
35917 /* 98238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35918 /* 98241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35919 /* 98247 */ GIR_RootConstrainSelectedInstOperands,
35920 /* 98248 */ // GIR_Coverage, 1765,
35921 /* 98248 */ GIR_EraseRootFromParent_Done,
35922 /* 98249 */ // Label 3038: @98249
35923 /* 98249 */ GIM_Reject,
35924 /* 98250 */ // Label 3034: @98250
35925 /* 98250 */ GIM_Reject,
35926 /* 98251 */ // Label 3023: @98251
35927 /* 98251 */ GIM_Reject,
35928 /* 98252 */ // Label 30: @98252
35929 /* 98252 */ GIM_Try, /*On fail goto*//*Label 3039*/ GIMT_Encode4(98463),
35930 /* 98257 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35931 /* 98260 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35932 /* 98263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35933 /* 98266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3040*/ GIMT_Encode4(98322), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 469 //
35934 /* 98273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35935 /* 98277 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35936 /* 98281 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35937 /* 98285 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35938 /* 98289 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31),
35939 /* 98293 */ // MIs[1] Operand 1
35940 /* 98293 */ // No operand predicates
35941 /* 98293 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35942 /* 98295 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2LSLri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm)
35943 /* 98295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLri),
35944 /* 98298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35945 /* 98300 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
35946 /* 98302 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35947 /* 98305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35948 /* 98308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35949 /* 98314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35950 /* 98320 */ GIR_RootConstrainSelectedInstOperands,
35951 /* 98321 */ // GIR_Coverage, 469,
35952 /* 98321 */ GIR_EraseRootFromParent_Done,
35953 /* 98322 */ // Label 3040: @98322
35954 /* 98322 */ GIM_Try, /*On fail goto*//*Label 3041*/ GIMT_Encode4(98417),
35955 /* 98327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
35956 /* 98331 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
35957 /* 98335 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3042*/ GIMT_Encode4(98379), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 317 //
35958 /* 98342 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35959 /* 98346 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35960 /* 98350 */ // MIs[1] Operand 1
35961 /* 98350 */ // No operand predicates
35962 /* 98350 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35963 /* 98352 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5) => (tLSLri:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5)
35964 /* 98352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLri),
35965 /* 98355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35966 /* 98357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
35967 /* 98363 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
35968 /* 98365 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm5
35969 /* 98368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35970 /* 98371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35971 /* 98377 */ GIR_RootConstrainSelectedInstOperands,
35972 /* 98378 */ // GIR_Coverage, 317,
35973 /* 98378 */ GIR_EraseRootFromParent_Done,
35974 /* 98379 */ // Label 3042: @98379
35975 /* 98379 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3043*/ GIMT_Encode4(98416), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 318 //
35976 /* 98386 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
35977 /* 98390 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSLrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
35978 /* 98390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLrr),
35979 /* 98393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
35980 /* 98395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
35981 /* 98401 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
35982 /* 98403 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
35983 /* 98405 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35984 /* 98408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35985 /* 98414 */ GIR_RootConstrainSelectedInstOperands,
35986 /* 98415 */ // GIR_Coverage, 318,
35987 /* 98415 */ GIR_EraseRootFromParent_Done,
35988 /* 98416 */ // Label 3043: @98416
35989 /* 98416 */ GIM_Reject,
35990 /* 98417 */ // Label 3041: @98417
35991 /* 98417 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3044*/ GIMT_Encode4(98462), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 470 //
35992 /* 98424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35993 /* 98428 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35994 /* 98432 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35995 /* 98436 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSLrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
35996 /* 98436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLrr),
35997 /* 98439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35998 /* 98441 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
35999 /* 98443 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36000 /* 98445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36001 /* 98448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36002 /* 98454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36003 /* 98460 */ GIR_RootConstrainSelectedInstOperands,
36004 /* 98461 */ // GIR_Coverage, 470,
36005 /* 98461 */ GIR_EraseRootFromParent_Done,
36006 /* 98462 */ // Label 3044: @98462
36007 /* 98462 */ GIM_Reject,
36008 /* 98463 */ // Label 3039: @98463
36009 /* 98463 */ GIM_Reject,
36010 /* 98464 */ // Label 31: @98464
36011 /* 98464 */ GIM_Try, /*On fail goto*//*Label 3045*/ GIMT_Encode4(98569),
36012 /* 98469 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36013 /* 98472 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
36014 /* 98475 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36015 /* 98478 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3046*/ GIMT_Encode4(98523), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 320 //
36016 /* 98485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36017 /* 98489 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36018 /* 98493 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36019 /* 98497 */ // (srl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
36020 /* 98497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSRrr),
36021 /* 98500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
36022 /* 98502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
36023 /* 98508 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36024 /* 98510 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36025 /* 98512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36026 /* 98515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36027 /* 98521 */ GIR_RootConstrainSelectedInstOperands,
36028 /* 98522 */ // GIR_Coverage, 320,
36029 /* 98522 */ GIR_EraseRootFromParent_Done,
36030 /* 98523 */ // Label 3046: @98523
36031 /* 98523 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3047*/ GIMT_Encode4(98568), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 472 //
36032 /* 98530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36033 /* 98534 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36034 /* 98538 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36035 /* 98542 */ // (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36036 /* 98542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSRrr),
36037 /* 98545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36038 /* 98547 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36039 /* 98549 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36040 /* 98551 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36041 /* 98554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36042 /* 98560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36043 /* 98566 */ GIR_RootConstrainSelectedInstOperands,
36044 /* 98567 */ // GIR_Coverage, 472,
36045 /* 98567 */ GIR_EraseRootFromParent_Done,
36046 /* 98568 */ // Label 3047: @98568
36047 /* 98568 */ GIM_Reject,
36048 /* 98569 */ // Label 3045: @98569
36049 /* 98569 */ GIM_Reject,
36050 /* 98570 */ // Label 32: @98570
36051 /* 98570 */ GIM_Try, /*On fail goto*//*Label 3048*/ GIMT_Encode4(98837),
36052 /* 98575 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36053 /* 98578 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
36054 /* 98581 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36055 /* 98584 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3049*/ GIMT_Encode4(98638), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 200 //
36056 /* 98591 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36057 /* 98595 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36058 /* 98599 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
36059 /* 98603 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36060 /* 98607 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36061 /* 98612 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
36062 /* 98616 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36063 /* 98618 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
36064 /* 98618 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH),
36065 /* 98621 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36066 /* 98623 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
36067 /* 98627 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36068 /* 98630 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36069 /* 98636 */ GIR_RootConstrainSelectedInstOperands,
36070 /* 98637 */ // GIR_Coverage, 200,
36071 /* 98637 */ GIR_EraseRootFromParent_Done,
36072 /* 98638 */ // Label 3049: @98638
36073 /* 98638 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3050*/ GIMT_Encode4(98692), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 327 //
36074 /* 98645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36075 /* 98649 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36076 /* 98653 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
36077 /* 98657 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36078 /* 98661 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36079 /* 98666 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
36080 /* 98670 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36081 /* 98672 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREVSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
36082 /* 98672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREVSH),
36083 /* 98675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36084 /* 98677 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
36085 /* 98681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36086 /* 98684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36087 /* 98690 */ GIR_RootConstrainSelectedInstOperands,
36088 /* 98691 */ // GIR_Coverage, 327,
36089 /* 98691 */ GIR_EraseRootFromParent_Done,
36090 /* 98692 */ // Label 3050: @98692
36091 /* 98692 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3051*/ GIMT_Encode4(98746), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 537 //
36092 /* 98699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36093 /* 98703 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36094 /* 98707 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
36095 /* 98711 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36096 /* 98715 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36097 /* 98720 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
36098 /* 98724 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36099 /* 98726 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
36100 /* 98726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH),
36101 /* 98729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36102 /* 98731 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
36103 /* 98735 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36104 /* 98738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36105 /* 98744 */ GIR_RootConstrainSelectedInstOperands,
36106 /* 98745 */ // GIR_Coverage, 537,
36107 /* 98745 */ GIR_EraseRootFromParent_Done,
36108 /* 98746 */ // Label 3051: @98746
36109 /* 98746 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3052*/ GIMT_Encode4(98791), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 311 //
36110 /* 98753 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36111 /* 98757 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36112 /* 98761 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36113 /* 98765 */ // (sra:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tASRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
36114 /* 98765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tASRrr),
36115 /* 98768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
36116 /* 98770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
36117 /* 98776 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36118 /* 98778 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36119 /* 98780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36120 /* 98783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36121 /* 98789 */ GIR_RootConstrainSelectedInstOperands,
36122 /* 98790 */ // GIR_Coverage, 311,
36123 /* 98790 */ GIR_EraseRootFromParent_Done,
36124 /* 98791 */ // Label 3052: @98791
36125 /* 98791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3053*/ GIMT_Encode4(98836), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 474 //
36126 /* 98798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36127 /* 98802 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36128 /* 98806 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36129 /* 98810 */ // (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ASRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36130 /* 98810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ASRrr),
36131 /* 98813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36132 /* 98815 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36133 /* 98817 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36134 /* 98819 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36135 /* 98822 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36136 /* 98828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36137 /* 98834 */ GIR_RootConstrainSelectedInstOperands,
36138 /* 98835 */ // GIR_Coverage, 474,
36139 /* 98835 */ GIR_EraseRootFromParent_Done,
36140 /* 98836 */ // Label 3053: @98836
36141 /* 98836 */ GIM_Reject,
36142 /* 98837 */ // Label 3048: @98837
36143 /* 98837 */ GIM_Reject,
36144 /* 98838 */ // Label 33: @98838
36145 /* 98838 */ GIM_Try, /*On fail goto*//*Label 3054*/ GIMT_Encode4(99163),
36146 /* 98843 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36147 /* 98846 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
36148 /* 98849 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36149 /* 98852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3055*/ GIMT_Encode4(98906), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 199 //
36150 /* 98859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36151 /* 98863 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36152 /* 98867 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
36153 /* 98871 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36154 /* 98875 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36155 /* 98880 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
36156 /* 98884 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36157 /* 98886 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REV16:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
36158 /* 98886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV16),
36159 /* 98889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36160 /* 98891 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
36161 /* 98895 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36162 /* 98898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36163 /* 98904 */ GIR_RootConstrainSelectedInstOperands,
36164 /* 98905 */ // GIR_Coverage, 199,
36165 /* 98905 */ GIR_EraseRootFromParent_Done,
36166 /* 98906 */ // Label 3055: @98906
36167 /* 98906 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3056*/ GIMT_Encode4(98960), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 326 //
36168 /* 98913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36169 /* 98917 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36170 /* 98921 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
36171 /* 98925 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36172 /* 98929 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36173 /* 98934 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
36174 /* 98938 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36175 /* 98940 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREV16:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
36176 /* 98940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV16),
36177 /* 98943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36178 /* 98945 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
36179 /* 98949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36180 /* 98952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36181 /* 98958 */ GIR_RootConstrainSelectedInstOperands,
36182 /* 98959 */ // GIR_Coverage, 326,
36183 /* 98959 */ GIR_EraseRootFromParent_Done,
36184 /* 98960 */ // Label 3056: @98960
36185 /* 98960 */ GIM_Try, /*On fail goto*//*Label 3057*/ GIMT_Encode4(99072),
36186 /* 98965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36187 /* 98969 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3058*/ GIMT_Encode4(99019), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 536 //
36188 /* 98976 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36189 /* 98980 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
36190 /* 98984 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36191 /* 98988 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36192 /* 98993 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
36193 /* 98997 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36194 /* 98999 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REV16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
36195 /* 98999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV16),
36196 /* 99002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36197 /* 99004 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
36198 /* 99008 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36199 /* 99011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36200 /* 99017 */ GIR_RootConstrainSelectedInstOperands,
36201 /* 99018 */ // GIR_Coverage, 536,
36202 /* 99018 */ GIR_EraseRootFromParent_Done,
36203 /* 99019 */ // Label 3058: @99019
36204 /* 99019 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3059*/ GIMT_Encode4(99071), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 475 //
36205 /* 99026 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36206 /* 99030 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
36207 /* 99034 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36208 /* 99038 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31),
36209 /* 99042 */ // MIs[1] Operand 1
36210 /* 99042 */ // No operand predicates
36211 /* 99042 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36212 /* 99044 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2RORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm)
36213 /* 99044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORri),
36214 /* 99047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36215 /* 99049 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
36216 /* 99051 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
36217 /* 99054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36218 /* 99057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36219 /* 99063 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36220 /* 99069 */ GIR_RootConstrainSelectedInstOperands,
36221 /* 99070 */ // GIR_Coverage, 475,
36222 /* 99070 */ GIR_EraseRootFromParent_Done,
36223 /* 99071 */ // Label 3059: @99071
36224 /* 99071 */ GIM_Reject,
36225 /* 99072 */ // Label 3057: @99072
36226 /* 99072 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3060*/ GIMT_Encode4(99117), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 328 //
36227 /* 99079 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36228 /* 99083 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36229 /* 99087 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
36230 /* 99091 */ // (rotr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tROR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
36231 /* 99091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tROR),
36232 /* 99094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
36233 /* 99096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
36234 /* 99102 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36235 /* 99104 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36236 /* 99106 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36237 /* 99109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36238 /* 99115 */ GIR_RootConstrainSelectedInstOperands,
36239 /* 99116 */ // GIR_Coverage, 328,
36240 /* 99116 */ GIR_EraseRootFromParent_Done,
36241 /* 99117 */ // Label 3060: @99117
36242 /* 99117 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3061*/ GIMT_Encode4(99162), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 476 //
36243 /* 99124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36244 /* 99128 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36245 /* 99132 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36246 /* 99136 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2RORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36247 /* 99136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORrr),
36248 /* 99139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36249 /* 99141 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36250 /* 99143 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36251 /* 99145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36252 /* 99148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36253 /* 99154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36254 /* 99160 */ GIR_RootConstrainSelectedInstOperands,
36255 /* 99161 */ // GIR_Coverage, 476,
36256 /* 99161 */ GIR_EraseRootFromParent_Done,
36257 /* 99162 */ // Label 3061: @99162
36258 /* 99162 */ GIM_Reject,
36259 /* 99163 */ // Label 3054: @99163
36260 /* 99163 */ GIM_Reject,
36261 /* 99164 */ // Label 34: @99164
36262 /* 99164 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 3065*/ GIMT_Encode4(99396),
36263 /* 99175 */ /*GILLT_v16s8*//*Label 3062*/ GIMT_Encode4(99195), GIMT_Encode4(0),
36264 /* 99183 */ /*GILLT_v8s16*//*Label 3063*/ GIMT_Encode4(99262), GIMT_Encode4(0),
36265 /* 99191 */ /*GILLT_v4s32*//*Label 3064*/ GIMT_Encode4(99329),
36266 /* 99195 */ // Label 3062: @99195
36267 /* 99195 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3066*/ GIMT_Encode4(99261), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4967 //
36268 /* 99202 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
36269 /* 99205 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
36270 /* 99208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36271 /* 99212 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36272 /* 99216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36273 /* 99220 */ // (mulhu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
36274 /* 99220 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36275 /* 99223 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36276 /* 99227 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36277 /* 99232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8),
36278 /* 99235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36279 /* 99237 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36280 /* 99239 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36281 /* 99241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36282 /* 99244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36283 /* 99250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36284 /* 99256 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36285 /* 99259 */ GIR_RootConstrainSelectedInstOperands,
36286 /* 99260 */ // GIR_Coverage, 4967,
36287 /* 99260 */ GIR_EraseRootFromParent_Done,
36288 /* 99261 */ // Label 3066: @99261
36289 /* 99261 */ GIM_Reject,
36290 /* 99262 */ // Label 3063: @99262
36291 /* 99262 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3067*/ GIMT_Encode4(99328), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4971 //
36292 /* 99269 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
36293 /* 99272 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36294 /* 99275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36295 /* 99279 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36296 /* 99283 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36297 /* 99287 */ // (mulhu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
36298 /* 99287 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36299 /* 99290 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36300 /* 99294 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36301 /* 99299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16),
36302 /* 99302 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36303 /* 99304 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36304 /* 99306 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36305 /* 99308 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36306 /* 99311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36307 /* 99317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36308 /* 99323 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36309 /* 99326 */ GIR_RootConstrainSelectedInstOperands,
36310 /* 99327 */ // GIR_Coverage, 4971,
36311 /* 99327 */ GIR_EraseRootFromParent_Done,
36312 /* 99328 */ // Label 3067: @99328
36313 /* 99328 */ GIM_Reject,
36314 /* 99329 */ // Label 3064: @99329
36315 /* 99329 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3068*/ GIMT_Encode4(99395), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4975 //
36316 /* 99336 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
36317 /* 99339 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36318 /* 99342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36319 /* 99346 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36320 /* 99350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36321 /* 99354 */ // (mulhu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
36322 /* 99354 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36323 /* 99357 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36324 /* 99361 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36325 /* 99366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32),
36326 /* 99369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36327 /* 99371 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36328 /* 99373 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36329 /* 99375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36330 /* 99378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36331 /* 99384 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36332 /* 99390 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36333 /* 99393 */ GIR_RootConstrainSelectedInstOperands,
36334 /* 99394 */ // GIR_Coverage, 4975,
36335 /* 99394 */ GIR_EraseRootFromParent_Done,
36336 /* 99395 */ // Label 3068: @99395
36337 /* 99395 */ GIM_Reject,
36338 /* 99396 */ // Label 3065: @99396
36339 /* 99396 */ GIM_Reject,
36340 /* 99397 */ // Label 35: @99397
36341 /* 99397 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3073*/ GIMT_Encode4(99748),
36342 /* 99408 */ /*GILLT_s32*//*Label 3069*/ GIMT_Encode4(99456), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
36343 /* 99436 */ /*GILLT_v16s8*//*Label 3070*/ GIMT_Encode4(99547), GIMT_Encode4(0),
36344 /* 99444 */ /*GILLT_v8s16*//*Label 3071*/ GIMT_Encode4(99614), GIMT_Encode4(0),
36345 /* 99452 */ /*GILLT_v4s32*//*Label 3072*/ GIMT_Encode4(99681),
36346 /* 99456 */ // Label 3069: @99456
36347 /* 99456 */ GIM_Try, /*On fail goto*//*Label 3074*/ GIMT_Encode4(99546),
36348 /* 99461 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
36349 /* 99464 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36350 /* 99467 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3075*/ GIMT_Encode4(99506), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 177 //
36351 /* 99474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36352 /* 99478 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36353 /* 99482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36354 /* 99486 */ // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SMMUL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
36355 /* 99486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMUL),
36356 /* 99489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36357 /* 99491 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36358 /* 99493 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36359 /* 99495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36360 /* 99498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36361 /* 99504 */ GIR_RootConstrainSelectedInstOperands,
36362 /* 99505 */ // GIR_Coverage, 177,
36363 /* 99505 */ GIR_EraseRootFromParent_Done,
36364 /* 99506 */ // Label 3075: @99506
36365 /* 99506 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3076*/ GIMT_Encode4(99545), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 506 //
36366 /* 99513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36367 /* 99517 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36368 /* 99521 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36369 /* 99525 */ // (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMMUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36370 /* 99525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMUL),
36371 /* 99528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36372 /* 99530 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
36373 /* 99532 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36374 /* 99534 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36375 /* 99537 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36376 /* 99543 */ GIR_RootConstrainSelectedInstOperands,
36377 /* 99544 */ // GIR_Coverage, 506,
36378 /* 99544 */ GIR_EraseRootFromParent_Done,
36379 /* 99545 */ // Label 3076: @99545
36380 /* 99545 */ GIM_Reject,
36381 /* 99546 */ // Label 3074: @99546
36382 /* 99546 */ GIM_Reject,
36383 /* 99547 */ // Label 3070: @99547
36384 /* 99547 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3077*/ GIMT_Encode4(99613), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4956 //
36385 /* 99554 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
36386 /* 99557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
36387 /* 99560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36388 /* 99564 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36389 /* 99568 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36390 /* 99572 */ // (mulhs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
36391 /* 99572 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36392 /* 99575 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36393 /* 99579 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36394 /* 99584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8),
36395 /* 99587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36396 /* 99589 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36397 /* 99591 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36398 /* 99593 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36399 /* 99596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36400 /* 99602 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36401 /* 99608 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36402 /* 99611 */ GIR_RootConstrainSelectedInstOperands,
36403 /* 99612 */ // GIR_Coverage, 4956,
36404 /* 99612 */ GIR_EraseRootFromParent_Done,
36405 /* 99613 */ // Label 3077: @99613
36406 /* 99613 */ GIM_Reject,
36407 /* 99614 */ // Label 3071: @99614
36408 /* 99614 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3078*/ GIMT_Encode4(99680), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4959 //
36409 /* 99621 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
36410 /* 99624 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36411 /* 99627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36412 /* 99631 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36413 /* 99635 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36414 /* 99639 */ // (mulhs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
36415 /* 99639 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36416 /* 99642 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36417 /* 99646 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36418 /* 99651 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16),
36419 /* 99654 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36420 /* 99656 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36421 /* 99658 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36422 /* 99660 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36423 /* 99663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36424 /* 99669 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36425 /* 99675 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36426 /* 99678 */ GIR_RootConstrainSelectedInstOperands,
36427 /* 99679 */ // GIR_Coverage, 4959,
36428 /* 99679 */ GIR_EraseRootFromParent_Done,
36429 /* 99680 */ // Label 3078: @99680
36430 /* 99680 */ GIM_Reject,
36431 /* 99681 */ // Label 3072: @99681
36432 /* 99681 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3079*/ GIMT_Encode4(99747), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4963 //
36433 /* 99688 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
36434 /* 99691 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36435 /* 99694 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36436 /* 99698 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36437 /* 99702 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36438 /* 99706 */ // (mulhs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
36439 /* 99706 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36440 /* 99709 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36441 /* 99713 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36442 /* 99718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32),
36443 /* 99721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36444 /* 99723 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36445 /* 99725 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36446 /* 99727 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36447 /* 99730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36448 /* 99736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36449 /* 99742 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36450 /* 99745 */ GIR_RootConstrainSelectedInstOperands,
36451 /* 99746 */ // GIR_Coverage, 4963,
36452 /* 99746 */ GIR_EraseRootFromParent_Done,
36453 /* 99747 */ // Label 3079: @99747
36454 /* 99747 */ GIM_Reject,
36455 /* 99748 */ // Label 3073: @99748
36456 /* 99748 */ GIM_Reject,
36457 /* 99749 */ // Label 36: @99749
36458 /* 99749 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 3088*/ GIMT_Encode4(100374),
36459 /* 99760 */ /*GILLT_s64*//*Label 3080*/ GIMT_Encode4(99808), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
36460 /* 99780 */ /*GILLT_v8s8*//*Label 3081*/ GIMT_Encode4(99854),
36461 /* 99784 */ /*GILLT_v16s8*//*Label 3082*/ GIMT_Encode4(99900),
36462 /* 99788 */ /*GILLT_v4s16*//*Label 3083*/ GIMT_Encode4(100012),
36463 /* 99792 */ /*GILLT_v8s16*//*Label 3084*/ GIMT_Encode4(100058),
36464 /* 99796 */ /*GILLT_v2s32*//*Label 3085*/ GIMT_Encode4(100170),
36465 /* 99800 */ /*GILLT_v4s32*//*Label 3086*/ GIMT_Encode4(100216),
36466 /* 99804 */ /*GILLT_v2s64*//*Label 3087*/ GIMT_Encode4(100328),
36467 /* 99808 */ // Label 3080: @99808
36468 /* 99808 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3089*/ GIMT_Encode4(99853), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 950 //
36469 /* 99815 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
36470 /* 99818 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
36471 /* 99821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36472 /* 99825 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36473 /* 99829 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36474 /* 99833 */ // (uaddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
36475 /* 99833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv1i64),
36476 /* 99836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36477 /* 99838 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36478 /* 99840 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36479 /* 99842 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36480 /* 99845 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36481 /* 99851 */ GIR_RootConstrainSelectedInstOperands,
36482 /* 99852 */ // GIR_Coverage, 950,
36483 /* 99852 */ GIR_EraseRootFromParent_Done,
36484 /* 99853 */ // Label 3089: @99853
36485 /* 99853 */ GIM_Reject,
36486 /* 99854 */ // Label 3081: @99854
36487 /* 99854 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3090*/ GIMT_Encode4(99899), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 948 //
36488 /* 99861 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
36489 /* 99864 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
36490 /* 99867 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36491 /* 99871 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36492 /* 99875 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36493 /* 99879 */ // (uaddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
36494 /* 99879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i8),
36495 /* 99882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36496 /* 99884 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36497 /* 99886 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36498 /* 99888 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36499 /* 99891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36500 /* 99897 */ GIR_RootConstrainSelectedInstOperands,
36501 /* 99898 */ // GIR_Coverage, 948,
36502 /* 99898 */ GIR_EraseRootFromParent_Done,
36503 /* 99899 */ // Label 3090: @99899
36504 /* 99899 */ GIM_Reject,
36505 /* 99900 */ // Label 3082: @99900
36506 /* 99900 */ GIM_Try, /*On fail goto*//*Label 3091*/ GIMT_Encode4(100011),
36507 /* 99905 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
36508 /* 99908 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
36509 /* 99911 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3092*/ GIMT_Encode4(99950), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 949 //
36510 /* 99918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36511 /* 99922 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36512 /* 99926 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36513 /* 99930 */ // (uaddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
36514 /* 99930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv16i8),
36515 /* 99933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36516 /* 99935 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36517 /* 99937 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36518 /* 99939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36519 /* 99942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36520 /* 99948 */ GIR_RootConstrainSelectedInstOperands,
36521 /* 99949 */ // GIR_Coverage, 949,
36522 /* 99949 */ GIR_EraseRootFromParent_Done,
36523 /* 99950 */ // Label 3092: @99950
36524 /* 99950 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3093*/ GIMT_Encode4(100010), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3918 //
36525 /* 99957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36526 /* 99961 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36527 /* 99965 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36528 /* 99969 */ // (uaddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
36529 /* 99969 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36530 /* 99972 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36531 /* 99976 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36532 /* 99981 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu8),
36533 /* 99984 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36534 /* 99986 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36535 /* 99988 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36536 /* 99990 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36537 /* 99993 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36538 /* 99999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36539 /* 100005 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36540 /* 100008 */ GIR_RootConstrainSelectedInstOperands,
36541 /* 100009 */ // GIR_Coverage, 3918,
36542 /* 100009 */ GIR_EraseRootFromParent_Done,
36543 /* 100010 */ // Label 3093: @100010
36544 /* 100010 */ GIM_Reject,
36545 /* 100011 */ // Label 3091: @100011
36546 /* 100011 */ GIM_Reject,
36547 /* 100012 */ // Label 3083: @100012
36548 /* 100012 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3094*/ GIMT_Encode4(100057), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 944 //
36549 /* 100019 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
36550 /* 100022 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
36551 /* 100025 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36552 /* 100029 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36553 /* 100033 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36554 /* 100037 */ // (uaddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
36555 /* 100037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i16),
36556 /* 100040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36557 /* 100042 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36558 /* 100044 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36559 /* 100046 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36560 /* 100049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36561 /* 100055 */ GIR_RootConstrainSelectedInstOperands,
36562 /* 100056 */ // GIR_Coverage, 944,
36563 /* 100056 */ GIR_EraseRootFromParent_Done,
36564 /* 100057 */ // Label 3094: @100057
36565 /* 100057 */ GIM_Reject,
36566 /* 100058 */ // Label 3084: @100058
36567 /* 100058 */ GIM_Try, /*On fail goto*//*Label 3095*/ GIMT_Encode4(100169),
36568 /* 100063 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
36569 /* 100066 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36570 /* 100069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3096*/ GIMT_Encode4(100108), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 946 //
36571 /* 100076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36572 /* 100080 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36573 /* 100084 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36574 /* 100088 */ // (uaddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
36575 /* 100088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i16),
36576 /* 100091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36577 /* 100093 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36578 /* 100095 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36579 /* 100097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36580 /* 100100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36581 /* 100106 */ GIR_RootConstrainSelectedInstOperands,
36582 /* 100107 */ // GIR_Coverage, 946,
36583 /* 100107 */ GIR_EraseRootFromParent_Done,
36584 /* 100108 */ // Label 3096: @100108
36585 /* 100108 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3097*/ GIMT_Encode4(100168), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3921 //
36586 /* 100115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36587 /* 100119 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36588 /* 100123 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36589 /* 100127 */ // (uaddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
36590 /* 100127 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36591 /* 100130 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36592 /* 100134 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36593 /* 100139 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu16),
36594 /* 100142 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36595 /* 100144 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36596 /* 100146 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36597 /* 100148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36598 /* 100151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36599 /* 100157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36600 /* 100163 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36601 /* 100166 */ GIR_RootConstrainSelectedInstOperands,
36602 /* 100167 */ // GIR_Coverage, 3921,
36603 /* 100167 */ GIR_EraseRootFromParent_Done,
36604 /* 100168 */ // Label 3097: @100168
36605 /* 100168 */ GIM_Reject,
36606 /* 100169 */ // Label 3095: @100169
36607 /* 100169 */ GIM_Reject,
36608 /* 100170 */ // Label 3085: @100170
36609 /* 100170 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3098*/ GIMT_Encode4(100215), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 945 //
36610 /* 100177 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
36611 /* 100180 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
36612 /* 100183 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36613 /* 100187 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36614 /* 100191 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36615 /* 100195 */ // (uaddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
36616 /* 100195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i32),
36617 /* 100198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36618 /* 100200 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36619 /* 100202 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36620 /* 100204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36621 /* 100207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36622 /* 100213 */ GIR_RootConstrainSelectedInstOperands,
36623 /* 100214 */ // GIR_Coverage, 945,
36624 /* 100214 */ GIR_EraseRootFromParent_Done,
36625 /* 100215 */ // Label 3098: @100215
36626 /* 100215 */ GIM_Reject,
36627 /* 100216 */ // Label 3086: @100216
36628 /* 100216 */ GIM_Try, /*On fail goto*//*Label 3099*/ GIMT_Encode4(100327),
36629 /* 100221 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
36630 /* 100224 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36631 /* 100227 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3100*/ GIMT_Encode4(100266), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 947 //
36632 /* 100234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36633 /* 100238 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36634 /* 100242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36635 /* 100246 */ // (uaddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
36636 /* 100246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i32),
36637 /* 100249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36638 /* 100251 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36639 /* 100253 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36640 /* 100255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36641 /* 100258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36642 /* 100264 */ GIR_RootConstrainSelectedInstOperands,
36643 /* 100265 */ // GIR_Coverage, 947,
36644 /* 100265 */ GIR_EraseRootFromParent_Done,
36645 /* 100266 */ // Label 3100: @100266
36646 /* 100266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3101*/ GIMT_Encode4(100326), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3924 //
36647 /* 100273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36648 /* 100277 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36649 /* 100281 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36650 /* 100285 */ // (uaddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
36651 /* 100285 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36652 /* 100288 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36653 /* 100292 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36654 /* 100297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu32),
36655 /* 100300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36656 /* 100302 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36657 /* 100304 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36658 /* 100306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36659 /* 100309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36660 /* 100315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36661 /* 100321 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36662 /* 100324 */ GIR_RootConstrainSelectedInstOperands,
36663 /* 100325 */ // GIR_Coverage, 3924,
36664 /* 100325 */ GIR_EraseRootFromParent_Done,
36665 /* 100326 */ // Label 3101: @100326
36666 /* 100326 */ GIM_Reject,
36667 /* 100327 */ // Label 3099: @100327
36668 /* 100327 */ GIM_Reject,
36669 /* 100328 */ // Label 3087: @100328
36670 /* 100328 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3102*/ GIMT_Encode4(100373), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 951 //
36671 /* 100335 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
36672 /* 100338 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
36673 /* 100341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36674 /* 100345 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36675 /* 100349 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36676 /* 100353 */ // (uaddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
36677 /* 100353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i64),
36678 /* 100356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36679 /* 100358 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36680 /* 100360 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36681 /* 100362 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36682 /* 100365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36683 /* 100371 */ GIR_RootConstrainSelectedInstOperands,
36684 /* 100372 */ // GIR_Coverage, 951,
36685 /* 100372 */ GIR_EraseRootFromParent_Done,
36686 /* 100373 */ // Label 3102: @100373
36687 /* 100373 */ GIM_Reject,
36688 /* 100374 */ // Label 3088: @100374
36689 /* 100374 */ GIM_Reject,
36690 /* 100375 */ // Label 37: @100375
36691 /* 100375 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 3112*/ GIMT_Encode4(101647),
36692 /* 100386 */ /*GILLT_s32*//*Label 3103*/ GIMT_Encode4(100438),
36693 /* 100390 */ /*GILLT_s64*//*Label 3104*/ GIMT_Encode4(100773), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
36694 /* 100410 */ /*GILLT_v8s8*//*Label 3105*/ GIMT_Encode4(100819),
36695 /* 100414 */ /*GILLT_v16s8*//*Label 3106*/ GIMT_Encode4(100865),
36696 /* 100418 */ /*GILLT_v4s16*//*Label 3107*/ GIMT_Encode4(100977),
36697 /* 100422 */ /*GILLT_v8s16*//*Label 3108*/ GIMT_Encode4(101023),
36698 /* 100426 */ /*GILLT_v2s32*//*Label 3109*/ GIMT_Encode4(101135),
36699 /* 100430 */ /*GILLT_v4s32*//*Label 3110*/ GIMT_Encode4(101181),
36700 /* 100434 */ /*GILLT_v2s64*//*Label 3111*/ GIMT_Encode4(101447),
36701 /* 100438 */ // Label 3103: @100438
36702 /* 100438 */ GIM_Try, /*On fail goto*//*Label 3113*/ GIMT_Encode4(100772),
36703 /* 100443 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
36704 /* 100446 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36705 /* 100449 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3114*/ GIMT_Encode4(100510), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 6254 //
36706 /* 100456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36707 /* 100460 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36708 /* 100464 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
36709 /* 100468 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36710 /* 100472 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36711 /* 100477 */ // MIs[1] Rn
36712 /* 100477 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
36713 /* 100482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36714 /* 100486 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36715 /* 100488 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
36716 /* 100488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
36717 /* 100491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36718 /* 100493 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36719 /* 100495 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
36720 /* 100499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36721 /* 100502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36722 /* 100508 */ GIR_RootConstrainSelectedInstOperands,
36723 /* 100509 */ // GIR_Coverage, 6254,
36724 /* 100509 */ GIR_EraseRootFromParent_Done,
36725 /* 100510 */ // Label 3114: @100510
36726 /* 100510 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3115*/ GIMT_Encode4(100571), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 6294 //
36727 /* 100517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36728 /* 100521 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36729 /* 100525 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
36730 /* 100529 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36731 /* 100533 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36732 /* 100538 */ // MIs[1] Rn
36733 /* 100538 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
36734 /* 100543 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36735 /* 100547 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36736 /* 100549 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
36737 /* 100549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
36738 /* 100552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36739 /* 100554 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
36740 /* 100556 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
36741 /* 100560 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36742 /* 100563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36743 /* 100569 */ GIR_RootConstrainSelectedInstOperands,
36744 /* 100570 */ // GIR_Coverage, 6294,
36745 /* 100570 */ GIR_EraseRootFromParent_Done,
36746 /* 100571 */ // Label 3115: @100571
36747 /* 100571 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3116*/ GIMT_Encode4(100632), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2058 //
36748 /* 100578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36749 /* 100582 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36750 /* 100586 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
36751 /* 100590 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
36752 /* 100594 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36753 /* 100598 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36754 /* 100603 */ // MIs[1] Rn
36755 /* 100603 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
36756 /* 100608 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36757 /* 100610 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
36758 /* 100610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
36759 /* 100613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36760 /* 100615 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
36761 /* 100617 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
36762 /* 100621 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36763 /* 100624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36764 /* 100630 */ GIR_RootConstrainSelectedInstOperands,
36765 /* 100631 */ // GIR_Coverage, 2058,
36766 /* 100631 */ GIR_EraseRootFromParent_Done,
36767 /* 100632 */ // Label 3116: @100632
36768 /* 100632 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3117*/ GIMT_Encode4(100693), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2332 //
36769 /* 100639 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36770 /* 100643 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36771 /* 100647 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
36772 /* 100651 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
36773 /* 100655 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
36774 /* 100659 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36775 /* 100664 */ // MIs[1] Rn
36776 /* 100664 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
36777 /* 100669 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36778 /* 100671 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
36779 /* 100671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
36780 /* 100674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36781 /* 100676 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
36782 /* 100678 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
36783 /* 100682 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36784 /* 100685 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36785 /* 100691 */ GIR_RootConstrainSelectedInstOperands,
36786 /* 100692 */ // GIR_Coverage, 2332,
36787 /* 100692 */ GIR_EraseRootFromParent_Done,
36788 /* 100693 */ // Label 3117: @100693
36789 /* 100693 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3118*/ GIMT_Encode4(100732), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2056 //
36790 /* 100700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36791 /* 100704 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36792 /* 100708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36793 /* 100712 */ // (saddsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QADD:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
36794 /* 100712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD),
36795 /* 100715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36796 /* 100717 */ GIR_RootToRootCopy, /*OpIdx*/1, // a
36797 /* 100719 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
36798 /* 100721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36799 /* 100724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36800 /* 100730 */ GIR_RootConstrainSelectedInstOperands,
36801 /* 100731 */ // GIR_Coverage, 2056,
36802 /* 100731 */ GIR_EraseRootFromParent_Done,
36803 /* 100732 */ // Label 3118: @100732
36804 /* 100732 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3119*/ GIMT_Encode4(100771), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2330 //
36805 /* 100739 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36806 /* 100743 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36807 /* 100747 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36808 /* 100751 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
36809 /* 100751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD),
36810 /* 100754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36811 /* 100756 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
36812 /* 100758 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36813 /* 100760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36814 /* 100763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36815 /* 100769 */ GIR_RootConstrainSelectedInstOperands,
36816 /* 100770 */ // GIR_Coverage, 2330,
36817 /* 100770 */ GIR_EraseRootFromParent_Done,
36818 /* 100771 */ // Label 3119: @100771
36819 /* 100771 */ GIM_Reject,
36820 /* 100772 */ // Label 3113: @100772
36821 /* 100772 */ GIM_Reject,
36822 /* 100773 */ // Label 3104: @100773
36823 /* 100773 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3120*/ GIMT_Encode4(100818), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 942 //
36824 /* 100780 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
36825 /* 100783 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
36826 /* 100786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36827 /* 100790 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36828 /* 100794 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36829 /* 100798 */ // (saddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
36830 /* 100798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv1i64),
36831 /* 100801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36832 /* 100803 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36833 /* 100805 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36834 /* 100807 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36835 /* 100810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36836 /* 100816 */ GIR_RootConstrainSelectedInstOperands,
36837 /* 100817 */ // GIR_Coverage, 942,
36838 /* 100817 */ GIR_EraseRootFromParent_Done,
36839 /* 100818 */ // Label 3120: @100818
36840 /* 100818 */ GIM_Reject,
36841 /* 100819 */ // Label 3105: @100819
36842 /* 100819 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3121*/ GIMT_Encode4(100864), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 940 //
36843 /* 100826 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
36844 /* 100829 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
36845 /* 100832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36846 /* 100836 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36847 /* 100840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36848 /* 100844 */ // (saddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
36849 /* 100844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i8),
36850 /* 100847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36851 /* 100849 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36852 /* 100851 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36853 /* 100853 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36854 /* 100856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36855 /* 100862 */ GIR_RootConstrainSelectedInstOperands,
36856 /* 100863 */ // GIR_Coverage, 940,
36857 /* 100863 */ GIR_EraseRootFromParent_Done,
36858 /* 100864 */ // Label 3121: @100864
36859 /* 100864 */ GIM_Reject,
36860 /* 100865 */ // Label 3106: @100865
36861 /* 100865 */ GIM_Try, /*On fail goto*//*Label 3122*/ GIMT_Encode4(100976),
36862 /* 100870 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
36863 /* 100873 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
36864 /* 100876 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3123*/ GIMT_Encode4(100915), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 941 //
36865 /* 100883 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36866 /* 100887 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36867 /* 100891 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36868 /* 100895 */ // (saddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
36869 /* 100895 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv16i8),
36870 /* 100898 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36871 /* 100900 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36872 /* 100902 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36873 /* 100904 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36874 /* 100907 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36875 /* 100913 */ GIR_RootConstrainSelectedInstOperands,
36876 /* 100914 */ // GIR_Coverage, 941,
36877 /* 100914 */ GIR_EraseRootFromParent_Done,
36878 /* 100915 */ // Label 3123: @100915
36879 /* 100915 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3124*/ GIMT_Encode4(100975), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3909 //
36880 /* 100922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36881 /* 100926 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36882 /* 100930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36883 /* 100934 */ // (saddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
36884 /* 100934 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36885 /* 100937 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36886 /* 100941 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36887 /* 100946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs8),
36888 /* 100949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36889 /* 100951 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36890 /* 100953 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36891 /* 100955 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36892 /* 100958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36893 /* 100964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36894 /* 100970 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36895 /* 100973 */ GIR_RootConstrainSelectedInstOperands,
36896 /* 100974 */ // GIR_Coverage, 3909,
36897 /* 100974 */ GIR_EraseRootFromParent_Done,
36898 /* 100975 */ // Label 3124: @100975
36899 /* 100975 */ GIM_Reject,
36900 /* 100976 */ // Label 3122: @100976
36901 /* 100976 */ GIM_Reject,
36902 /* 100977 */ // Label 3107: @100977
36903 /* 100977 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3125*/ GIMT_Encode4(101022), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 936 //
36904 /* 100984 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
36905 /* 100987 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
36906 /* 100990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36907 /* 100994 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36908 /* 100998 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36909 /* 101002 */ // (saddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
36910 /* 101002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i16),
36911 /* 101005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36912 /* 101007 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36913 /* 101009 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36914 /* 101011 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36915 /* 101014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36916 /* 101020 */ GIR_RootConstrainSelectedInstOperands,
36917 /* 101021 */ // GIR_Coverage, 936,
36918 /* 101021 */ GIR_EraseRootFromParent_Done,
36919 /* 101022 */ // Label 3125: @101022
36920 /* 101022 */ GIM_Reject,
36921 /* 101023 */ // Label 3108: @101023
36922 /* 101023 */ GIM_Try, /*On fail goto*//*Label 3126*/ GIMT_Encode4(101134),
36923 /* 101028 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
36924 /* 101031 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36925 /* 101034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3127*/ GIMT_Encode4(101073), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 938 //
36926 /* 101041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36927 /* 101045 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36928 /* 101049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36929 /* 101053 */ // (saddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
36930 /* 101053 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i16),
36931 /* 101056 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36932 /* 101058 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36933 /* 101060 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36934 /* 101062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36935 /* 101065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36936 /* 101071 */ GIR_RootConstrainSelectedInstOperands,
36937 /* 101072 */ // GIR_Coverage, 938,
36938 /* 101072 */ GIR_EraseRootFromParent_Done,
36939 /* 101073 */ // Label 3127: @101073
36940 /* 101073 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3128*/ GIMT_Encode4(101133), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3912 //
36941 /* 101080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36942 /* 101084 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36943 /* 101088 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36944 /* 101092 */ // (saddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
36945 /* 101092 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
36946 /* 101095 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
36947 /* 101099 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
36948 /* 101104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs16),
36949 /* 101107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
36950 /* 101109 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
36951 /* 101111 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
36952 /* 101113 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
36953 /* 101116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36954 /* 101122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36955 /* 101128 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
36956 /* 101131 */ GIR_RootConstrainSelectedInstOperands,
36957 /* 101132 */ // GIR_Coverage, 3912,
36958 /* 101132 */ GIR_EraseRootFromParent_Done,
36959 /* 101133 */ // Label 3128: @101133
36960 /* 101133 */ GIM_Reject,
36961 /* 101134 */ // Label 3126: @101134
36962 /* 101134 */ GIM_Reject,
36963 /* 101135 */ // Label 3109: @101135
36964 /* 101135 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3129*/ GIMT_Encode4(101180), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 937 //
36965 /* 101142 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
36966 /* 101145 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
36967 /* 101148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36968 /* 101152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36969 /* 101156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36970 /* 101160 */ // (saddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
36971 /* 101160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i32),
36972 /* 101163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
36973 /* 101165 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
36974 /* 101167 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
36975 /* 101169 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36976 /* 101172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36977 /* 101178 */ GIR_RootConstrainSelectedInstOperands,
36978 /* 101179 */ // GIR_Coverage, 937,
36979 /* 101179 */ GIR_EraseRootFromParent_Done,
36980 /* 101180 */ // Label 3129: @101180
36981 /* 101180 */ GIM_Reject,
36982 /* 101181 */ // Label 3110: @101181
36983 /* 101181 */ GIM_Try, /*On fail goto*//*Label 3130*/ GIMT_Encode4(101446),
36984 /* 101186 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
36985 /* 101189 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36986 /* 101192 */ GIM_Try, /*On fail goto*//*Label 3131*/ GIMT_Encode4(101385),
36987 /* 101197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36988 /* 101201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3132*/ GIMT_Encode4(101274), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6377 //
36989 /* 101208 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
36990 /* 101212 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
36991 /* 101216 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
36992 /* 101219 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
36993 /* 101224 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
36994 /* 101228 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
36995 /* 101232 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36996 /* 101237 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
36997 /* 101242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
36998 /* 101246 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36999 /* 101248 */ // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 4041:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37000 /* 101248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32),
37001 /* 101251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37002 /* 101253 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
37003 /* 101255 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37004 /* 101259 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37005 /* 101263 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37006 /* 101266 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37007 /* 101272 */ GIR_RootConstrainSelectedInstOperands,
37008 /* 101273 */ // GIR_Coverage, 6377,
37009 /* 101273 */ GIR_EraseRootFromParent_Done,
37010 /* 101274 */ // Label 3132: @101274
37011 /* 101274 */ GIM_Try, /*On fail goto*//*Label 3133*/ GIMT_Encode4(101384),
37012 /* 101279 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37013 /* 101283 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3134*/ GIMT_Encode4(101352), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2872 //
37014 /* 101290 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37015 /* 101294 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
37016 /* 101298 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37017 /* 101301 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
37018 /* 101306 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
37019 /* 101310 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
37020 /* 101314 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37021 /* 101319 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37022 /* 101324 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37023 /* 101326 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 4041:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37024 /* 101326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32),
37025 /* 101329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37026 /* 101331 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
37027 /* 101333 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37028 /* 101337 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37029 /* 101341 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37030 /* 101344 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37031 /* 101350 */ GIR_RootConstrainSelectedInstOperands,
37032 /* 101351 */ // GIR_Coverage, 2872,
37033 /* 101351 */ GIR_EraseRootFromParent_Done,
37034 /* 101352 */ // Label 3134: @101352
37035 /* 101352 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3135*/ GIMT_Encode4(101383), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 939 //
37036 /* 101359 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37037 /* 101363 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
37038 /* 101363 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i32),
37039 /* 101366 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37040 /* 101368 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37041 /* 101370 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37042 /* 101372 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37043 /* 101375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37044 /* 101381 */ GIR_RootConstrainSelectedInstOperands,
37045 /* 101382 */ // GIR_Coverage, 939,
37046 /* 101382 */ GIR_EraseRootFromParent_Done,
37047 /* 101383 */ // Label 3135: @101383
37048 /* 101383 */ GIM_Reject,
37049 /* 101384 */ // Label 3133: @101384
37050 /* 101384 */ GIM_Reject,
37051 /* 101385 */ // Label 3131: @101385
37052 /* 101385 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3136*/ GIMT_Encode4(101445), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3915 //
37053 /* 101392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37054 /* 101396 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37055 /* 101400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37056 /* 101404 */ // (saddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
37057 /* 101404 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37058 /* 101407 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37059 /* 101411 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37060 /* 101416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs32),
37061 /* 101419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37062 /* 101421 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
37063 /* 101423 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
37064 /* 101425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
37065 /* 101428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37066 /* 101434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37067 /* 101440 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37068 /* 101443 */ GIR_RootConstrainSelectedInstOperands,
37069 /* 101444 */ // GIR_Coverage, 3915,
37070 /* 101444 */ GIR_EraseRootFromParent_Done,
37071 /* 101445 */ // Label 3136: @101445
37072 /* 101445 */ GIM_Reject,
37073 /* 101446 */ // Label 3130: @101446
37074 /* 101446 */ GIM_Reject,
37075 /* 101447 */ // Label 3111: @101447
37076 /* 101447 */ GIM_Try, /*On fail goto*//*Label 3137*/ GIMT_Encode4(101646),
37077 /* 101452 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
37078 /* 101455 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
37079 /* 101458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37080 /* 101462 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3138*/ GIMT_Encode4(101535), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 6378 //
37081 /* 101469 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37082 /* 101473 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
37083 /* 101477 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37084 /* 101480 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
37085 /* 101485 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
37086 /* 101489 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
37087 /* 101493 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37088 /* 101498 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37089 /* 101503 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37090 /* 101507 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37091 /* 101509 */ // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 4041:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$src1) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37092 /* 101509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64),
37093 /* 101512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37094 /* 101514 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
37095 /* 101516 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37096 /* 101520 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37097 /* 101524 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37098 /* 101527 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37099 /* 101533 */ GIR_RootConstrainSelectedInstOperands,
37100 /* 101534 */ // GIR_Coverage, 6378,
37101 /* 101534 */ GIR_EraseRootFromParent_Done,
37102 /* 101535 */ // Label 3138: @101535
37103 /* 101535 */ GIM_Try, /*On fail goto*//*Label 3139*/ GIMT_Encode4(101645),
37104 /* 101540 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37105 /* 101544 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3140*/ GIMT_Encode4(101613), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2873 //
37106 /* 101551 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37107 /* 101555 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
37108 /* 101559 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37109 /* 101562 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
37110 /* 101567 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
37111 /* 101571 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
37112 /* 101575 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37113 /* 101580 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37114 /* 101585 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37115 /* 101587 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 4041:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37116 /* 101587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64),
37117 /* 101590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37118 /* 101592 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
37119 /* 101594 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37120 /* 101598 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37121 /* 101602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37122 /* 101605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37123 /* 101611 */ GIR_RootConstrainSelectedInstOperands,
37124 /* 101612 */ // GIR_Coverage, 2873,
37125 /* 101612 */ GIR_EraseRootFromParent_Done,
37126 /* 101613 */ // Label 3140: @101613
37127 /* 101613 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3141*/ GIMT_Encode4(101644), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 943 //
37128 /* 101620 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37129 /* 101624 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
37130 /* 101624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i64),
37131 /* 101627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37132 /* 101629 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37133 /* 101631 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37134 /* 101633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37135 /* 101636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37136 /* 101642 */ GIR_RootConstrainSelectedInstOperands,
37137 /* 101643 */ // GIR_Coverage, 943,
37138 /* 101643 */ GIR_EraseRootFromParent_Done,
37139 /* 101644 */ // Label 3141: @101644
37140 /* 101644 */ GIM_Reject,
37141 /* 101645 */ // Label 3139: @101645
37142 /* 101645 */ GIM_Reject,
37143 /* 101646 */ // Label 3137: @101646
37144 /* 101646 */ GIM_Reject,
37145 /* 101647 */ // Label 3112: @101647
37146 /* 101647 */ GIM_Reject,
37147 /* 101648 */ // Label 38: @101648
37148 /* 101648 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(14), /*)*//*default:*//*Label 3150*/ GIMT_Encode4(102273),
37149 /* 101659 */ /*GILLT_s64*//*Label 3142*/ GIMT_Encode4(101707), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
37150 /* 101679 */ /*GILLT_v8s8*//*Label 3143*/ GIMT_Encode4(101753),
37151 /* 101683 */ /*GILLT_v16s8*//*Label 3144*/ GIMT_Encode4(101799),
37152 /* 101687 */ /*GILLT_v4s16*//*Label 3145*/ GIMT_Encode4(101911),
37153 /* 101691 */ /*GILLT_v8s16*//*Label 3146*/ GIMT_Encode4(101957),
37154 /* 101695 */ /*GILLT_v2s32*//*Label 3147*/ GIMT_Encode4(102069),
37155 /* 101699 */ /*GILLT_v4s32*//*Label 3148*/ GIMT_Encode4(102115),
37156 /* 101703 */ /*GILLT_v2s64*//*Label 3149*/ GIMT_Encode4(102227),
37157 /* 101707 */ // Label 3142: @101707
37158 /* 101707 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3151*/ GIMT_Encode4(101752), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1184 //
37159 /* 101714 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
37160 /* 101717 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
37161 /* 101720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37162 /* 101724 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37163 /* 101728 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37164 /* 101732 */ // (usubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
37165 /* 101732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv1i64),
37166 /* 101735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37167 /* 101737 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37168 /* 101739 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37169 /* 101741 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37170 /* 101744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37171 /* 101750 */ GIR_RootConstrainSelectedInstOperands,
37172 /* 101751 */ // GIR_Coverage, 1184,
37173 /* 101751 */ GIR_EraseRootFromParent_Done,
37174 /* 101752 */ // Label 3151: @101752
37175 /* 101752 */ GIM_Reject,
37176 /* 101753 */ // Label 3143: @101753
37177 /* 101753 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3152*/ GIMT_Encode4(101798), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1182 //
37178 /* 101760 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
37179 /* 101763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
37180 /* 101766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37181 /* 101770 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37182 /* 101774 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37183 /* 101778 */ // (usubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
37184 /* 101778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i8),
37185 /* 101781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37186 /* 101783 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37187 /* 101785 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37188 /* 101787 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37189 /* 101790 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37190 /* 101796 */ GIR_RootConstrainSelectedInstOperands,
37191 /* 101797 */ // GIR_Coverage, 1182,
37192 /* 101797 */ GIR_EraseRootFromParent_Done,
37193 /* 101798 */ // Label 3152: @101798
37194 /* 101798 */ GIM_Reject,
37195 /* 101799 */ // Label 3144: @101799
37196 /* 101799 */ GIM_Try, /*On fail goto*//*Label 3153*/ GIMT_Encode4(101910),
37197 /* 101804 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
37198 /* 101807 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
37199 /* 101810 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3154*/ GIMT_Encode4(101849), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1183 //
37200 /* 101817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37201 /* 101821 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37202 /* 101825 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37203 /* 101829 */ // (usubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
37204 /* 101829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv16i8),
37205 /* 101832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37206 /* 101834 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37207 /* 101836 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37208 /* 101838 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37209 /* 101841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37210 /* 101847 */ GIR_RootConstrainSelectedInstOperands,
37211 /* 101848 */ // GIR_Coverage, 1183,
37212 /* 101848 */ GIR_EraseRootFromParent_Done,
37213 /* 101849 */ // Label 3154: @101849
37214 /* 101849 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3155*/ GIMT_Encode4(101909), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3936 //
37215 /* 101856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37216 /* 101860 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37217 /* 101864 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37218 /* 101868 */ // (usubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
37219 /* 101868 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37220 /* 101871 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37221 /* 101875 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37222 /* 101880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu8),
37223 /* 101883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37224 /* 101885 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
37225 /* 101887 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
37226 /* 101889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
37227 /* 101892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37228 /* 101898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37229 /* 101904 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37230 /* 101907 */ GIR_RootConstrainSelectedInstOperands,
37231 /* 101908 */ // GIR_Coverage, 3936,
37232 /* 101908 */ GIR_EraseRootFromParent_Done,
37233 /* 101909 */ // Label 3155: @101909
37234 /* 101909 */ GIM_Reject,
37235 /* 101910 */ // Label 3153: @101910
37236 /* 101910 */ GIM_Reject,
37237 /* 101911 */ // Label 3145: @101911
37238 /* 101911 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3156*/ GIMT_Encode4(101956), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1178 //
37239 /* 101918 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
37240 /* 101921 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
37241 /* 101924 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37242 /* 101928 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37243 /* 101932 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37244 /* 101936 */ // (usubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37245 /* 101936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i16),
37246 /* 101939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37247 /* 101941 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37248 /* 101943 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37249 /* 101945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37250 /* 101948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37251 /* 101954 */ GIR_RootConstrainSelectedInstOperands,
37252 /* 101955 */ // GIR_Coverage, 1178,
37253 /* 101955 */ GIR_EraseRootFromParent_Done,
37254 /* 101956 */ // Label 3156: @101956
37255 /* 101956 */ GIM_Reject,
37256 /* 101957 */ // Label 3146: @101957
37257 /* 101957 */ GIM_Try, /*On fail goto*//*Label 3157*/ GIMT_Encode4(102068),
37258 /* 101962 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
37259 /* 101965 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
37260 /* 101968 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3158*/ GIMT_Encode4(102007), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1180 //
37261 /* 101975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37262 /* 101979 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37263 /* 101983 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37264 /* 101987 */ // (usubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
37265 /* 101987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i16),
37266 /* 101990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37267 /* 101992 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37268 /* 101994 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37269 /* 101996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37270 /* 101999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37271 /* 102005 */ GIR_RootConstrainSelectedInstOperands,
37272 /* 102006 */ // GIR_Coverage, 1180,
37273 /* 102006 */ GIR_EraseRootFromParent_Done,
37274 /* 102007 */ // Label 3158: @102007
37275 /* 102007 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3159*/ GIMT_Encode4(102067), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3939 //
37276 /* 102014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37277 /* 102018 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37278 /* 102022 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37279 /* 102026 */ // (usubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
37280 /* 102026 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37281 /* 102029 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37282 /* 102033 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37283 /* 102038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu16),
37284 /* 102041 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37285 /* 102043 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
37286 /* 102045 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
37287 /* 102047 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
37288 /* 102050 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37289 /* 102056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37290 /* 102062 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37291 /* 102065 */ GIR_RootConstrainSelectedInstOperands,
37292 /* 102066 */ // GIR_Coverage, 3939,
37293 /* 102066 */ GIR_EraseRootFromParent_Done,
37294 /* 102067 */ // Label 3159: @102067
37295 /* 102067 */ GIM_Reject,
37296 /* 102068 */ // Label 3157: @102068
37297 /* 102068 */ GIM_Reject,
37298 /* 102069 */ // Label 3147: @102069
37299 /* 102069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3160*/ GIMT_Encode4(102114), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1179 //
37300 /* 102076 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
37301 /* 102079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
37302 /* 102082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37303 /* 102086 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37304 /* 102090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37305 /* 102094 */ // (usubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37306 /* 102094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i32),
37307 /* 102097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37308 /* 102099 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37309 /* 102101 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37310 /* 102103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37311 /* 102106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37312 /* 102112 */ GIR_RootConstrainSelectedInstOperands,
37313 /* 102113 */ // GIR_Coverage, 1179,
37314 /* 102113 */ GIR_EraseRootFromParent_Done,
37315 /* 102114 */ // Label 3160: @102114
37316 /* 102114 */ GIM_Reject,
37317 /* 102115 */ // Label 3148: @102115
37318 /* 102115 */ GIM_Try, /*On fail goto*//*Label 3161*/ GIMT_Encode4(102226),
37319 /* 102120 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
37320 /* 102123 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
37321 /* 102126 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3162*/ GIMT_Encode4(102165), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1181 //
37322 /* 102133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37323 /* 102137 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37324 /* 102141 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37325 /* 102145 */ // (usubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
37326 /* 102145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i32),
37327 /* 102148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37328 /* 102150 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37329 /* 102152 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37330 /* 102154 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37331 /* 102157 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37332 /* 102163 */ GIR_RootConstrainSelectedInstOperands,
37333 /* 102164 */ // GIR_Coverage, 1181,
37334 /* 102164 */ GIR_EraseRootFromParent_Done,
37335 /* 102165 */ // Label 3162: @102165
37336 /* 102165 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3163*/ GIMT_Encode4(102225), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3942 //
37337 /* 102172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37338 /* 102176 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37339 /* 102180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37340 /* 102184 */ // (usubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
37341 /* 102184 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37342 /* 102187 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37343 /* 102191 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37344 /* 102196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu32),
37345 /* 102199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37346 /* 102201 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
37347 /* 102203 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
37348 /* 102205 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
37349 /* 102208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37350 /* 102214 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37351 /* 102220 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37352 /* 102223 */ GIR_RootConstrainSelectedInstOperands,
37353 /* 102224 */ // GIR_Coverage, 3942,
37354 /* 102224 */ GIR_EraseRootFromParent_Done,
37355 /* 102225 */ // Label 3163: @102225
37356 /* 102225 */ GIM_Reject,
37357 /* 102226 */ // Label 3161: @102226
37358 /* 102226 */ GIM_Reject,
37359 /* 102227 */ // Label 3149: @102227
37360 /* 102227 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3164*/ GIMT_Encode4(102272), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1185 //
37361 /* 102234 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
37362 /* 102237 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
37363 /* 102240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37364 /* 102244 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37365 /* 102248 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37366 /* 102252 */ // (usubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
37367 /* 102252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i64),
37368 /* 102255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37369 /* 102257 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37370 /* 102259 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37371 /* 102261 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37372 /* 102264 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37373 /* 102270 */ GIR_RootConstrainSelectedInstOperands,
37374 /* 102271 */ // GIR_Coverage, 1185,
37375 /* 102271 */ GIR_EraseRootFromParent_Done,
37376 /* 102272 */ // Label 3164: @102272
37377 /* 102272 */ GIM_Reject,
37378 /* 102273 */ // Label 3150: @102273
37379 /* 102273 */ GIM_Reject,
37380 /* 102274 */ // Label 39: @102274
37381 /* 102274 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(14), /*)*//*default:*//*Label 3174*/ GIMT_Encode4(103266),
37382 /* 102285 */ /*GILLT_s32*//*Label 3165*/ GIMT_Encode4(102337),
37383 /* 102289 */ /*GILLT_s64*//*Label 3166*/ GIMT_Encode4(102550), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
37384 /* 102309 */ /*GILLT_v8s8*//*Label 3167*/ GIMT_Encode4(102596),
37385 /* 102313 */ /*GILLT_v16s8*//*Label 3168*/ GIMT_Encode4(102642),
37386 /* 102317 */ /*GILLT_v4s16*//*Label 3169*/ GIMT_Encode4(102754),
37387 /* 102321 */ /*GILLT_v8s16*//*Label 3170*/ GIMT_Encode4(102800),
37388 /* 102325 */ /*GILLT_v2s32*//*Label 3171*/ GIMT_Encode4(102912),
37389 /* 102329 */ /*GILLT_v4s32*//*Label 3172*/ GIMT_Encode4(102958),
37390 /* 102333 */ /*GILLT_v2s64*//*Label 3173*/ GIMT_Encode4(103145),
37391 /* 102337 */ // Label 3165: @102337
37392 /* 102337 */ GIM_Try, /*On fail goto*//*Label 3175*/ GIMT_Encode4(102549),
37393 /* 102342 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
37394 /* 102345 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
37395 /* 102348 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3176*/ GIMT_Encode4(102409), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2059 //
37396 /* 102355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
37397 /* 102359 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37398 /* 102363 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37399 /* 102367 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
37400 /* 102371 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37401 /* 102375 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37402 /* 102380 */ // MIs[1] Rn
37403 /* 102380 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
37404 /* 102385 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37405 /* 102387 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
37406 /* 102387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB),
37407 /* 102390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
37408 /* 102392 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
37409 /* 102394 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
37410 /* 102398 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37411 /* 102401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37412 /* 102407 */ GIR_RootConstrainSelectedInstOperands,
37413 /* 102408 */ // GIR_Coverage, 2059,
37414 /* 102408 */ GIR_EraseRootFromParent_Done,
37415 /* 102409 */ // Label 3176: @102409
37416 /* 102409 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3177*/ GIMT_Encode4(102470), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2333 //
37417 /* 102416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37418 /* 102420 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37419 /* 102424 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37420 /* 102428 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
37421 /* 102432 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37422 /* 102436 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37423 /* 102441 */ // MIs[1] Rn
37424 /* 102441 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
37425 /* 102446 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37426 /* 102448 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
37427 /* 102448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB),
37428 /* 102451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
37429 /* 102453 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
37430 /* 102455 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
37431 /* 102459 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37432 /* 102462 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37433 /* 102468 */ GIR_RootConstrainSelectedInstOperands,
37434 /* 102469 */ // GIR_Coverage, 2333,
37435 /* 102469 */ GIR_EraseRootFromParent_Done,
37436 /* 102470 */ // Label 3177: @102470
37437 /* 102470 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3178*/ GIMT_Encode4(102509), GIMT_Encode2(GIFBS_HasV5TE_IsARM), // Rule ID 2057 //
37438 /* 102477 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
37439 /* 102481 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37440 /* 102485 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37441 /* 102489 */ // (ssubsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QSUB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
37442 /* 102489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB),
37443 /* 102492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
37444 /* 102494 */ GIR_RootToRootCopy, /*OpIdx*/1, // a
37445 /* 102496 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
37446 /* 102498 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37447 /* 102501 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37448 /* 102507 */ GIR_RootConstrainSelectedInstOperands,
37449 /* 102508 */ // GIR_Coverage, 2057,
37450 /* 102508 */ GIR_EraseRootFromParent_Done,
37451 /* 102509 */ // Label 3178: @102509
37452 /* 102509 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3179*/ GIMT_Encode4(102548), GIMT_Encode2(GIFBS_HasDSP_IsThumb2), // Rule ID 2331 //
37453 /* 102516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37454 /* 102520 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37455 /* 102524 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
37456 /* 102528 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
37457 /* 102528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB),
37458 /* 102531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
37459 /* 102533 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
37460 /* 102535 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
37461 /* 102537 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37462 /* 102540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37463 /* 102546 */ GIR_RootConstrainSelectedInstOperands,
37464 /* 102547 */ // GIR_Coverage, 2331,
37465 /* 102547 */ GIR_EraseRootFromParent_Done,
37466 /* 102548 */ // Label 3179: @102548
37467 /* 102548 */ GIM_Reject,
37468 /* 102549 */ // Label 3175: @102549
37469 /* 102549 */ GIM_Reject,
37470 /* 102550 */ // Label 3166: @102550
37471 /* 102550 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3180*/ GIMT_Encode4(102595), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1176 //
37472 /* 102557 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
37473 /* 102560 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
37474 /* 102563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37475 /* 102567 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37476 /* 102571 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37477 /* 102575 */ // (ssubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
37478 /* 102575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv1i64),
37479 /* 102578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37480 /* 102580 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37481 /* 102582 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37482 /* 102584 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37483 /* 102587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37484 /* 102593 */ GIR_RootConstrainSelectedInstOperands,
37485 /* 102594 */ // GIR_Coverage, 1176,
37486 /* 102594 */ GIR_EraseRootFromParent_Done,
37487 /* 102595 */ // Label 3180: @102595
37488 /* 102595 */ GIM_Reject,
37489 /* 102596 */ // Label 3167: @102596
37490 /* 102596 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3181*/ GIMT_Encode4(102641), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1174 //
37491 /* 102603 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
37492 /* 102606 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
37493 /* 102609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37494 /* 102613 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37495 /* 102617 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37496 /* 102621 */ // (ssubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
37497 /* 102621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i8),
37498 /* 102624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37499 /* 102626 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37500 /* 102628 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37501 /* 102630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37502 /* 102633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37503 /* 102639 */ GIR_RootConstrainSelectedInstOperands,
37504 /* 102640 */ // GIR_Coverage, 1174,
37505 /* 102640 */ GIR_EraseRootFromParent_Done,
37506 /* 102641 */ // Label 3181: @102641
37507 /* 102641 */ GIM_Reject,
37508 /* 102642 */ // Label 3168: @102642
37509 /* 102642 */ GIM_Try, /*On fail goto*//*Label 3182*/ GIMT_Encode4(102753),
37510 /* 102647 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
37511 /* 102650 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
37512 /* 102653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3183*/ GIMT_Encode4(102692), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1175 //
37513 /* 102660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37514 /* 102664 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37515 /* 102668 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37516 /* 102672 */ // (ssubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
37517 /* 102672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv16i8),
37518 /* 102675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37519 /* 102677 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37520 /* 102679 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37521 /* 102681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37522 /* 102684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37523 /* 102690 */ GIR_RootConstrainSelectedInstOperands,
37524 /* 102691 */ // GIR_Coverage, 1175,
37525 /* 102691 */ GIR_EraseRootFromParent_Done,
37526 /* 102692 */ // Label 3183: @102692
37527 /* 102692 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3184*/ GIMT_Encode4(102752), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3927 //
37528 /* 102699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37529 /* 102703 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37530 /* 102707 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37531 /* 102711 */ // (ssubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
37532 /* 102711 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37533 /* 102714 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37534 /* 102718 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37535 /* 102723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs8),
37536 /* 102726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37537 /* 102728 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
37538 /* 102730 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
37539 /* 102732 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
37540 /* 102735 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37541 /* 102741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37542 /* 102747 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37543 /* 102750 */ GIR_RootConstrainSelectedInstOperands,
37544 /* 102751 */ // GIR_Coverage, 3927,
37545 /* 102751 */ GIR_EraseRootFromParent_Done,
37546 /* 102752 */ // Label 3184: @102752
37547 /* 102752 */ GIM_Reject,
37548 /* 102753 */ // Label 3182: @102753
37549 /* 102753 */ GIM_Reject,
37550 /* 102754 */ // Label 3169: @102754
37551 /* 102754 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3185*/ GIMT_Encode4(102799), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1170 //
37552 /* 102761 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
37553 /* 102764 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
37554 /* 102767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37555 /* 102771 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37556 /* 102775 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37557 /* 102779 */ // (ssubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37558 /* 102779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i16),
37559 /* 102782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37560 /* 102784 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37561 /* 102786 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37562 /* 102788 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37563 /* 102791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37564 /* 102797 */ GIR_RootConstrainSelectedInstOperands,
37565 /* 102798 */ // GIR_Coverage, 1170,
37566 /* 102798 */ GIR_EraseRootFromParent_Done,
37567 /* 102799 */ // Label 3185: @102799
37568 /* 102799 */ GIM_Reject,
37569 /* 102800 */ // Label 3170: @102800
37570 /* 102800 */ GIM_Try, /*On fail goto*//*Label 3186*/ GIMT_Encode4(102911),
37571 /* 102805 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
37572 /* 102808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
37573 /* 102811 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3187*/ GIMT_Encode4(102850), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1172 //
37574 /* 102818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37575 /* 102822 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37576 /* 102826 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37577 /* 102830 */ // (ssubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
37578 /* 102830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i16),
37579 /* 102833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37580 /* 102835 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37581 /* 102837 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37582 /* 102839 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37583 /* 102842 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37584 /* 102848 */ GIR_RootConstrainSelectedInstOperands,
37585 /* 102849 */ // GIR_Coverage, 1172,
37586 /* 102849 */ GIR_EraseRootFromParent_Done,
37587 /* 102850 */ // Label 3187: @102850
37588 /* 102850 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3188*/ GIMT_Encode4(102910), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3930 //
37589 /* 102857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37590 /* 102861 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37591 /* 102865 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37592 /* 102869 */ // (ssubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
37593 /* 102869 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37594 /* 102872 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37595 /* 102876 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37596 /* 102881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs16),
37597 /* 102884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37598 /* 102886 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
37599 /* 102888 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
37600 /* 102890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
37601 /* 102893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37602 /* 102899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37603 /* 102905 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37604 /* 102908 */ GIR_RootConstrainSelectedInstOperands,
37605 /* 102909 */ // GIR_Coverage, 3930,
37606 /* 102909 */ GIR_EraseRootFromParent_Done,
37607 /* 102910 */ // Label 3188: @102910
37608 /* 102910 */ GIM_Reject,
37609 /* 102911 */ // Label 3186: @102911
37610 /* 102911 */ GIM_Reject,
37611 /* 102912 */ // Label 3171: @102912
37612 /* 102912 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3189*/ GIMT_Encode4(102957), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1171 //
37613 /* 102919 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
37614 /* 102922 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
37615 /* 102925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37616 /* 102929 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37617 /* 102933 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37618 /* 102937 */ // (ssubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37619 /* 102937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i32),
37620 /* 102940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37621 /* 102942 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37622 /* 102944 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37623 /* 102946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37624 /* 102949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37625 /* 102955 */ GIR_RootConstrainSelectedInstOperands,
37626 /* 102956 */ // GIR_Coverage, 1171,
37627 /* 102956 */ GIR_EraseRootFromParent_Done,
37628 /* 102957 */ // Label 3189: @102957
37629 /* 102957 */ GIM_Reject,
37630 /* 102958 */ // Label 3172: @102958
37631 /* 102958 */ GIM_Try, /*On fail goto*//*Label 3190*/ GIMT_Encode4(103144),
37632 /* 102963 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
37633 /* 102966 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
37634 /* 102969 */ GIM_Try, /*On fail goto*//*Label 3191*/ GIMT_Encode4(103083),
37635 /* 102974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37636 /* 102978 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37637 /* 102982 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3192*/ GIMT_Encode4(103051), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2882 //
37638 /* 102989 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37639 /* 102993 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
37640 /* 102997 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37641 /* 103000 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
37642 /* 103005 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
37643 /* 103009 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
37644 /* 103013 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37645 /* 103018 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37646 /* 103023 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37647 /* 103025 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 4041:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLSLv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
37648 /* 103025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv4i32),
37649 /* 103028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37650 /* 103030 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
37651 /* 103032 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37652 /* 103036 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37653 /* 103040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37654 /* 103043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37655 /* 103049 */ GIR_RootConstrainSelectedInstOperands,
37656 /* 103050 */ // GIR_Coverage, 2882,
37657 /* 103050 */ GIR_EraseRootFromParent_Done,
37658 /* 103051 */ // Label 3192: @103051
37659 /* 103051 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3193*/ GIMT_Encode4(103082), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1173 //
37660 /* 103058 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37661 /* 103062 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
37662 /* 103062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i32),
37663 /* 103065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37664 /* 103067 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37665 /* 103069 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37666 /* 103071 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37667 /* 103074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37668 /* 103080 */ GIR_RootConstrainSelectedInstOperands,
37669 /* 103081 */ // GIR_Coverage, 1173,
37670 /* 103081 */ GIR_EraseRootFromParent_Done,
37671 /* 103082 */ // Label 3193: @103082
37672 /* 103082 */ GIM_Reject,
37673 /* 103083 */ // Label 3191: @103083
37674 /* 103083 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3194*/ GIMT_Encode4(103143), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3933 //
37675 /* 103090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37676 /* 103094 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37677 /* 103098 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37678 /* 103102 */ // (ssubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
37679 /* 103102 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
37680 /* 103105 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37681 /* 103109 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37682 /* 103114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs32),
37683 /* 103117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37684 /* 103119 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
37685 /* 103121 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
37686 /* 103123 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
37687 /* 103126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37688 /* 103132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37689 /* 103138 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
37690 /* 103141 */ GIR_RootConstrainSelectedInstOperands,
37691 /* 103142 */ // GIR_Coverage, 3933,
37692 /* 103142 */ GIR_EraseRootFromParent_Done,
37693 /* 103143 */ // Label 3194: @103143
37694 /* 103143 */ GIM_Reject,
37695 /* 103144 */ // Label 3190: @103144
37696 /* 103144 */ GIM_Reject,
37697 /* 103145 */ // Label 3173: @103145
37698 /* 103145 */ GIM_Try, /*On fail goto*//*Label 3195*/ GIMT_Encode4(103265),
37699 /* 103150 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
37700 /* 103153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
37701 /* 103156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37702 /* 103160 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37703 /* 103164 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3196*/ GIMT_Encode4(103233), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 2883 //
37704 /* 103171 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37705 /* 103175 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
37706 /* 103179 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
37707 /* 103182 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
37708 /* 103187 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
37709 /* 103191 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
37710 /* 103195 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37711 /* 103200 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
37712 /* 103205 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37713 /* 103207 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 4041:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLSLv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
37714 /* 103207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv2i64),
37715 /* 103210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37716 /* 103212 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
37717 /* 103214 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
37718 /* 103218 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
37719 /* 103222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37720 /* 103225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37721 /* 103231 */ GIR_RootConstrainSelectedInstOperands,
37722 /* 103232 */ // GIR_Coverage, 2883,
37723 /* 103232 */ GIR_EraseRootFromParent_Done,
37724 /* 103233 */ // Label 3196: @103233
37725 /* 103233 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3197*/ GIMT_Encode4(103264), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1177 //
37726 /* 103240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
37727 /* 103244 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
37728 /* 103244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i64),
37729 /* 103247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
37730 /* 103249 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
37731 /* 103251 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
37732 /* 103253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37733 /* 103256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37734 /* 103262 */ GIR_RootConstrainSelectedInstOperands,
37735 /* 103263 */ // GIR_Coverage, 1177,
37736 /* 103263 */ GIR_EraseRootFromParent_Done,
37737 /* 103264 */ // Label 3197: @103264
37738 /* 103264 */ GIM_Reject,
37739 /* 103265 */ // Label 3195: @103265
37740 /* 103265 */ GIM_Reject,
37741 /* 103266 */ // Label 3174: @103266
37742 /* 103266 */ GIM_Reject,
37743 /* 103267 */ // Label 40: @103267
37744 /* 103267 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3205*/ GIMT_Encode4(105601),
37745 /* 103278 */ /*GILLT_s16*//*Label 3198*/ GIMT_Encode4(103330),
37746 /* 103282 */ /*GILLT_s32*//*Label 3199*/ GIMT_Encode4(103376),
37747 /* 103286 */ /*GILLT_s64*//*Label 3200*/ GIMT_Encode4(104963), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
37748 /* 103314 */ /*GILLT_v4s16*//*Label 3201*/ GIMT_Encode4(105009),
37749 /* 103318 */ /*GILLT_v8s16*//*Label 3202*/ GIMT_Encode4(105193),
37750 /* 103322 */ /*GILLT_v2s32*//*Label 3203*/ GIMT_Encode4(105443),
37751 /* 103326 */ /*GILLT_v4s32*//*Label 3204*/ GIMT_Encode4(105489),
37752 /* 103330 */ // Label 3198: @103330
37753 /* 103330 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3206*/ GIMT_Encode4(103375), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 621 //
37754 /* 103337 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
37755 /* 103340 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
37756 /* 103343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
37757 /* 103347 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
37758 /* 103351 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
37759 /* 103355 */ // (fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
37760 /* 103355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH),
37761 /* 103358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
37762 /* 103360 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
37763 /* 103362 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
37764 /* 103364 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37765 /* 103367 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37766 /* 103373 */ GIR_RootConstrainSelectedInstOperands,
37767 /* 103374 */ // GIR_Coverage, 621,
37768 /* 103374 */ GIR_EraseRootFromParent_Done,
37769 /* 103375 */ // Label 3206: @103375
37770 /* 103375 */ GIM_Reject,
37771 /* 103376 */ // Label 3199: @103376
37772 /* 103376 */ GIM_Try, /*On fail goto*//*Label 3207*/ GIMT_Encode4(104962),
37773 /* 103381 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
37774 /* 103384 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
37775 /* 103387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37776 /* 103391 */ GIM_Try, /*On fail goto*//*Label 3208*/ GIMT_Encode4(104047),
37777 /* 103396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37778 /* 103400 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3209*/ GIMT_Encode4(103723), GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), // Rule ID 6557 //
37779 /* 103407 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37780 /* 103411 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
37781 /* 103415 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37782 /* 103419 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
37783 /* 103423 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37784 /* 103428 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37785 /* 103433 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37786 /* 103435 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
37787 /* 103435 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
37788 /* 103438 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37789 /* 103442 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37790 /* 103447 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
37791 /* 103449 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
37792 /* 103452 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37793 /* 103456 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37794 /* 103461 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
37795 /* 103464 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37796 /* 103469 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
37797 /* 103472 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
37798 /* 103476 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37799 /* 103481 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
37800 /* 103484 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
37801 /* 103488 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
37802 /* 103491 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37803 /* 103496 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37804 /* 103501 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
37805 /* 103506 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
37806 /* 103509 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37807 /* 103513 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37808 /* 103518 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
37809 /* 103520 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
37810 /* 103523 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37811 /* 103527 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37812 /* 103532 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
37813 /* 103535 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37814 /* 103540 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
37815 /* 103543 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
37816 /* 103547 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37817 /* 103552 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
37818 /* 103555 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
37819 /* 103559 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
37820 /* 103562 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37821 /* 103567 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37822 /* 103572 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
37823 /* 103577 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
37824 /* 103580 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37825 /* 103584 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37826 /* 103589 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
37827 /* 103591 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
37828 /* 103594 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37829 /* 103598 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37830 /* 103603 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
37831 /* 103606 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37832 /* 103611 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
37833 /* 103614 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
37834 /* 103618 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37835 /* 103623 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
37836 /* 103626 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc
37837 /* 103630 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
37838 /* 103633 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37839 /* 103638 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37840 /* 103643 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
37841 /* 103648 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
37842 /* 103651 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd),
37843 /* 103655 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37844 /* 103660 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
37845 /* 103663 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
37846 /* 103666 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
37847 /* 103669 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
37848 /* 103672 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37849 /* 103678 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37850 /* 103680 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
37851 /* 103683 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37852 /* 103687 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37853 /* 103692 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
37854 /* 103695 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37855 /* 103700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37856 /* 103703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37857 /* 103705 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
37858 /* 103712 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
37859 /* 103717 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37860 /* 103722 */ // GIR_Coverage, 6557,
37861 /* 103722 */ GIR_EraseRootFromParent_Done,
37862 /* 103723 */ // Label 3209: @103723
37863 /* 103723 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3210*/ GIMT_Encode4(104046), GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), // Rule ID 6558 //
37864 /* 103730 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
37865 /* 103734 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
37866 /* 103738 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37867 /* 103742 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
37868 /* 103746 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37869 /* 103751 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37870 /* 103756 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37871 /* 103758 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
37872 /* 103758 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
37873 /* 103761 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37874 /* 103765 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37875 /* 103770 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
37876 /* 103772 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
37877 /* 103775 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37878 /* 103779 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37879 /* 103784 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
37880 /* 103787 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37881 /* 103792 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
37882 /* 103795 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
37883 /* 103799 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37884 /* 103804 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
37885 /* 103807 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
37886 /* 103811 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
37887 /* 103814 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37888 /* 103819 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37889 /* 103824 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
37890 /* 103829 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
37891 /* 103832 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37892 /* 103836 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37893 /* 103841 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
37894 /* 103843 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
37895 /* 103846 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37896 /* 103850 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37897 /* 103855 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
37898 /* 103858 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37899 /* 103863 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
37900 /* 103866 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
37901 /* 103870 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37902 /* 103875 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
37903 /* 103878 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
37904 /* 103882 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
37905 /* 103885 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37906 /* 103890 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37907 /* 103895 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
37908 /* 103900 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
37909 /* 103903 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37910 /* 103907 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37911 /* 103912 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
37912 /* 103914 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
37913 /* 103917 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37914 /* 103921 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37915 /* 103926 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
37916 /* 103929 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37917 /* 103934 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
37918 /* 103937 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
37919 /* 103941 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37920 /* 103946 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
37921 /* 103949 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc
37922 /* 103953 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
37923 /* 103956 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37924 /* 103961 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37925 /* 103966 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
37926 /* 103971 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
37927 /* 103974 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd),
37928 /* 103978 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37929 /* 103983 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
37930 /* 103986 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
37931 /* 103989 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
37932 /* 103992 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
37933 /* 103995 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37934 /* 104001 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
37935 /* 104003 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
37936 /* 104006 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37937 /* 104010 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37938 /* 104015 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
37939 /* 104018 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37940 /* 104023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37941 /* 104026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
37942 /* 104028 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
37943 /* 104035 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
37944 /* 104040 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37945 /* 104045 */ // GIR_Coverage, 6558,
37946 /* 104045 */ GIR_EraseRootFromParent_Done,
37947 /* 104046 */ // Label 3210: @104046
37948 /* 104046 */ GIM_Reject,
37949 /* 104047 */ // Label 3208: @104047
37950 /* 104047 */ GIM_Try, /*On fail goto*//*Label 3211*/ GIMT_Encode4(104961),
37951 /* 104052 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37952 /* 104056 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3212*/ GIMT_Encode4(104379), GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), // Rule ID 3089 //
37953 /* 104063 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
37954 /* 104067 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
37955 /* 104071 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
37956 /* 104075 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
37957 /* 104079 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37958 /* 104084 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
37959 /* 104089 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
37960 /* 104091 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
37961 /* 104091 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
37962 /* 104094 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37963 /* 104098 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37964 /* 104103 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
37965 /* 104105 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
37966 /* 104108 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37967 /* 104112 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37968 /* 104117 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
37969 /* 104120 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37970 /* 104125 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
37971 /* 104128 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
37972 /* 104132 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37973 /* 104137 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
37974 /* 104140 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
37975 /* 104144 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
37976 /* 104147 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37977 /* 104152 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37978 /* 104157 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
37979 /* 104162 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
37980 /* 104165 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37981 /* 104169 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37982 /* 104174 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
37983 /* 104176 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
37984 /* 104179 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
37985 /* 104183 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37986 /* 104188 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
37987 /* 104191 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37988 /* 104196 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
37989 /* 104199 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
37990 /* 104203 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
37991 /* 104208 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
37992 /* 104211 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
37993 /* 104215 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
37994 /* 104218 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37995 /* 104223 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
37996 /* 104228 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
37997 /* 104233 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
37998 /* 104236 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
37999 /* 104240 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38000 /* 104245 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
38001 /* 104247 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
38002 /* 104250 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38003 /* 104254 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38004 /* 104259 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
38005 /* 104262 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38006 /* 104267 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
38007 /* 104270 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38008 /* 104274 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38009 /* 104279 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
38010 /* 104282 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
38011 /* 104286 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
38012 /* 104289 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38013 /* 104294 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38014 /* 104299 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38015 /* 104304 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
38016 /* 104307 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd),
38017 /* 104311 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38018 /* 104316 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
38019 /* 104319 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
38020 /* 104322 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
38021 /* 104325 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
38022 /* 104328 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38023 /* 104334 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38024 /* 104336 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
38025 /* 104339 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38026 /* 104343 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38027 /* 104348 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
38028 /* 104351 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38029 /* 104356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38030 /* 104359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38031 /* 104361 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
38032 /* 104368 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
38033 /* 104373 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38034 /* 104378 */ // GIR_Coverage, 3089,
38035 /* 104378 */ GIR_EraseRootFromParent_Done,
38036 /* 104379 */ // Label 3212: @104379
38037 /* 104379 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3213*/ GIMT_Encode4(104702), GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), // Rule ID 3091 //
38038 /* 104386 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38039 /* 104390 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38040 /* 104394 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38041 /* 104398 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38042 /* 104402 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38043 /* 104407 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38044 /* 104412 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38045 /* 104414 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
38046 /* 104414 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
38047 /* 104417 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38048 /* 104421 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38049 /* 104426 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
38050 /* 104428 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
38051 /* 104431 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38052 /* 104435 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38053 /* 104440 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
38054 /* 104443 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38055 /* 104448 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
38056 /* 104451 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38057 /* 104455 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38058 /* 104460 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
38059 /* 104463 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
38060 /* 104467 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
38061 /* 104470 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38062 /* 104475 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38063 /* 104480 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38064 /* 104485 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
38065 /* 104488 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38066 /* 104492 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38067 /* 104497 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
38068 /* 104499 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
38069 /* 104502 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38070 /* 104506 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38071 /* 104511 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
38072 /* 104514 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38073 /* 104519 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
38074 /* 104522 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38075 /* 104526 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38076 /* 104531 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
38077 /* 104534 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
38078 /* 104538 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
38079 /* 104541 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38080 /* 104546 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38081 /* 104551 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38082 /* 104556 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
38083 /* 104559 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38084 /* 104563 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38085 /* 104568 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
38086 /* 104570 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
38087 /* 104573 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38088 /* 104577 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38089 /* 104582 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
38090 /* 104585 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38091 /* 104590 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
38092 /* 104593 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38093 /* 104597 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38094 /* 104602 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
38095 /* 104605 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
38096 /* 104609 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
38097 /* 104612 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38098 /* 104617 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38099 /* 104622 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38100 /* 104627 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
38101 /* 104630 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd),
38102 /* 104634 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38103 /* 104639 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
38104 /* 104642 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
38105 /* 104645 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
38106 /* 104648 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
38107 /* 104651 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38108 /* 104657 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38109 /* 104659 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
38110 /* 104662 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38111 /* 104666 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38112 /* 104671 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
38113 /* 104674 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38114 /* 104679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38115 /* 104682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38116 /* 104684 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
38117 /* 104691 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
38118 /* 104696 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38119 /* 104701 */ // GIR_Coverage, 3091,
38120 /* 104701 */ GIR_EraseRootFromParent_Done,
38121 /* 104702 */ // Label 3213: @104702
38122 /* 104702 */ GIM_Try, /*On fail goto*//*Label 3214*/ GIMT_Encode4(104960),
38123 /* 104707 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38124 /* 104711 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3215*/ GIMT_Encode4(104738), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 619 //
38125 /* 104718 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
38126 /* 104718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS),
38127 /* 104721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
38128 /* 104723 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
38129 /* 104725 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
38130 /* 104727 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38131 /* 104730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38132 /* 104736 */ GIR_RootConstrainSelectedInstOperands,
38133 /* 104737 */ // GIR_Coverage, 619,
38134 /* 104737 */ GIR_EraseRootFromParent_Done,
38135 /* 104738 */ // Label 3215: @104738
38136 /* 104738 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3216*/ GIMT_Encode4(104959), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3086 //
38137 /* 104745 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VADDfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
38138 /* 104745 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
38139 /* 104748 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38140 /* 104752 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38141 /* 104757 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
38142 /* 104759 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
38143 /* 104762 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38144 /* 104766 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38145 /* 104771 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
38146 /* 104774 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38147 /* 104779 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
38148 /* 104782 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38149 /* 104786 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38150 /* 104791 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
38151 /* 104794 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
38152 /* 104798 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
38153 /* 104801 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38154 /* 104806 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38155 /* 104811 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38156 /* 104816 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
38157 /* 104819 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38158 /* 104823 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38159 /* 104828 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
38160 /* 104830 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
38161 /* 104833 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38162 /* 104837 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38163 /* 104842 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
38164 /* 104845 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38165 /* 104850 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
38166 /* 104853 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38167 /* 104857 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38168 /* 104862 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
38169 /* 104865 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
38170 /* 104869 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
38171 /* 104872 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38172 /* 104877 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38173 /* 104882 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38174 /* 104887 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
38175 /* 104890 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VADDfd),
38176 /* 104894 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38177 /* 104899 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
38178 /* 104902 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
38179 /* 104905 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
38180 /* 104908 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38181 /* 104914 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38182 /* 104916 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
38183 /* 104919 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38184 /* 104923 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38185 /* 104928 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
38186 /* 104931 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38187 /* 104936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38188 /* 104939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38189 /* 104941 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
38190 /* 104948 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
38191 /* 104953 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38192 /* 104958 */ // GIR_Coverage, 3086,
38193 /* 104958 */ GIR_EraseRootFromParent_Done,
38194 /* 104959 */ // Label 3216: @104959
38195 /* 104959 */ GIM_Reject,
38196 /* 104960 */ // Label 3214: @104960
38197 /* 104960 */ GIM_Reject,
38198 /* 104961 */ // Label 3211: @104961
38199 /* 104961 */ GIM_Reject,
38200 /* 104962 */ // Label 3207: @104962
38201 /* 104962 */ GIM_Reject,
38202 /* 104963 */ // Label 3200: @104963
38203 /* 104963 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3217*/ GIMT_Encode4(105008), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 617 //
38204 /* 104970 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
38205 /* 104973 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
38206 /* 104976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38207 /* 104980 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38208 /* 104984 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38209 /* 104988 */ // (fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
38210 /* 104988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD),
38211 /* 104991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
38212 /* 104993 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
38213 /* 104995 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
38214 /* 104997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38215 /* 105000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38216 /* 105006 */ GIR_RootConstrainSelectedInstOperands,
38217 /* 105007 */ // GIR_Coverage, 617,
38218 /* 105007 */ GIR_EraseRootFromParent_Done,
38219 /* 105008 */ // Label 3217: @105008
38220 /* 105008 */ GIM_Reject,
38221 /* 105009 */ // Label 3201: @105009
38222 /* 105009 */ GIM_Try, /*On fail goto*//*Label 3218*/ GIMT_Encode4(105192),
38223 /* 105014 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
38224 /* 105017 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
38225 /* 105020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38226 /* 105024 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3219*/ GIMT_Encode4(105089), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 6184 //
38227 /* 105031 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38228 /* 105035 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38229 /* 105039 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
38230 /* 105043 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38231 /* 105047 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38232 /* 105052 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38233 /* 105057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38234 /* 105061 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38235 /* 105063 */ // (fadd:{ *:[v4f16] } (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm), DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
38236 /* 105063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd),
38237 /* 105066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38238 /* 105068 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
38239 /* 105070 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38240 /* 105074 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38241 /* 105078 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38242 /* 105081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38243 /* 105087 */ GIR_RootConstrainSelectedInstOperands,
38244 /* 105088 */ // GIR_Coverage, 6184,
38245 /* 105088 */ GIR_EraseRootFromParent_Done,
38246 /* 105089 */ // Label 3219: @105089
38247 /* 105089 */ GIM_Try, /*On fail goto*//*Label 3220*/ GIMT_Encode4(105191),
38248 /* 105094 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38249 /* 105098 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3221*/ GIMT_Encode4(105159), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1101 //
38250 /* 105105 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38251 /* 105109 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38252 /* 105113 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
38253 /* 105117 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38254 /* 105121 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38255 /* 105126 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38256 /* 105131 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38257 /* 105133 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
38258 /* 105133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd),
38259 /* 105136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38260 /* 105138 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
38261 /* 105140 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38262 /* 105144 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38263 /* 105148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38264 /* 105151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38265 /* 105157 */ GIR_RootConstrainSelectedInstOperands,
38266 /* 105158 */ // GIR_Coverage, 1101,
38267 /* 105158 */ GIR_EraseRootFromParent_Done,
38268 /* 105159 */ // Label 3221: @105159
38269 /* 105159 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3222*/ GIMT_Encode4(105190), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 886 //
38270 /* 105166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38271 /* 105170 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VADDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
38272 /* 105170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhd),
38273 /* 105173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38274 /* 105175 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
38275 /* 105177 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
38276 /* 105179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38277 /* 105182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38278 /* 105188 */ GIR_RootConstrainSelectedInstOperands,
38279 /* 105189 */ // GIR_Coverage, 886,
38280 /* 105189 */ GIR_EraseRootFromParent_Done,
38281 /* 105190 */ // Label 3222: @105190
38282 /* 105190 */ GIM_Reject,
38283 /* 105191 */ // Label 3220: @105191
38284 /* 105191 */ GIM_Reject,
38285 /* 105192 */ // Label 3218: @105192
38286 /* 105192 */ GIM_Reject,
38287 /* 105193 */ // Label 3202: @105193
38288 /* 105193 */ GIM_Try, /*On fail goto*//*Label 3223*/ GIMT_Encode4(105442),
38289 /* 105198 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
38290 /* 105201 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
38291 /* 105204 */ GIM_Try, /*On fail goto*//*Label 3224*/ GIMT_Encode4(105381),
38292 /* 105209 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38293 /* 105213 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3225*/ GIMT_Encode4(105278), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 6185 //
38294 /* 105220 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38295 /* 105224 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38296 /* 105228 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
38297 /* 105232 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
38298 /* 105236 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38299 /* 105241 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38300 /* 105246 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38301 /* 105250 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38302 /* 105252 */ // (fadd:{ *:[v8f16] } (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm), QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
38303 /* 105252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq),
38304 /* 105255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38305 /* 105257 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
38306 /* 105259 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38307 /* 105263 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38308 /* 105267 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38309 /* 105270 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38310 /* 105276 */ GIR_RootConstrainSelectedInstOperands,
38311 /* 105277 */ // GIR_Coverage, 6185,
38312 /* 105277 */ GIR_EraseRootFromParent_Done,
38313 /* 105278 */ // Label 3225: @105278
38314 /* 105278 */ GIM_Try, /*On fail goto*//*Label 3226*/ GIMT_Encode4(105380),
38315 /* 105283 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38316 /* 105287 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3227*/ GIMT_Encode4(105348), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1102 //
38317 /* 105294 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38318 /* 105298 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38319 /* 105302 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
38320 /* 105306 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
38321 /* 105310 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38322 /* 105315 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38323 /* 105320 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38324 /* 105322 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
38325 /* 105322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq),
38326 /* 105325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38327 /* 105327 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
38328 /* 105329 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38329 /* 105333 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38330 /* 105337 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38331 /* 105340 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38332 /* 105346 */ GIR_RootConstrainSelectedInstOperands,
38333 /* 105347 */ // GIR_Coverage, 1102,
38334 /* 105347 */ GIR_EraseRootFromParent_Done,
38335 /* 105348 */ // Label 3227: @105348
38336 /* 105348 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3228*/ GIMT_Encode4(105379), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 887 //
38337 /* 105355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38338 /* 105359 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VADDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
38339 /* 105359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhq),
38340 /* 105362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38341 /* 105364 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
38342 /* 105366 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
38343 /* 105368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38344 /* 105371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38345 /* 105377 */ GIR_RootConstrainSelectedInstOperands,
38346 /* 105378 */ // GIR_Coverage, 887,
38347 /* 105378 */ GIR_EraseRootFromParent_Done,
38348 /* 105379 */ // Label 3228: @105379
38349 /* 105379 */ GIM_Reject,
38350 /* 105380 */ // Label 3226: @105380
38351 /* 105380 */ GIM_Reject,
38352 /* 105381 */ // Label 3224: @105381
38353 /* 105381 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3229*/ GIMT_Encode4(105441), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4462 //
38354 /* 105388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38355 /* 105392 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38356 /* 105396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38357 /* 105400 */ // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
38358 /* 105400 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38359 /* 105403 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38360 /* 105407 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38361 /* 105412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16),
38362 /* 105415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38363 /* 105417 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
38364 /* 105419 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
38365 /* 105421 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38366 /* 105424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38367 /* 105430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38368 /* 105436 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38369 /* 105439 */ GIR_RootConstrainSelectedInstOperands,
38370 /* 105440 */ // GIR_Coverage, 4462,
38371 /* 105440 */ GIR_EraseRootFromParent_Done,
38372 /* 105441 */ // Label 3229: @105441
38373 /* 105441 */ GIM_Reject,
38374 /* 105442 */ // Label 3223: @105442
38375 /* 105442 */ GIM_Reject,
38376 /* 105443 */ // Label 3203: @105443
38377 /* 105443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3230*/ GIMT_Encode4(105488), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 884 //
38378 /* 105450 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
38379 /* 105453 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
38380 /* 105456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38381 /* 105460 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38382 /* 105464 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38383 /* 105468 */ // (fadd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VADDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
38384 /* 105468 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfd),
38385 /* 105471 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38386 /* 105473 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
38387 /* 105475 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
38388 /* 105477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38389 /* 105480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38390 /* 105486 */ GIR_RootConstrainSelectedInstOperands,
38391 /* 105487 */ // GIR_Coverage, 884,
38392 /* 105487 */ GIR_EraseRootFromParent_Done,
38393 /* 105488 */ // Label 3230: @105488
38394 /* 105488 */ GIM_Reject,
38395 /* 105489 */ // Label 3204: @105489
38396 /* 105489 */ GIM_Try, /*On fail goto*//*Label 3231*/ GIMT_Encode4(105600),
38397 /* 105494 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
38398 /* 105497 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
38399 /* 105500 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3232*/ GIMT_Encode4(105539), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 885 //
38400 /* 105507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38401 /* 105511 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38402 /* 105515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38403 /* 105519 */ // (fadd:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VADDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
38404 /* 105519 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfq),
38405 /* 105522 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38406 /* 105524 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
38407 /* 105526 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
38408 /* 105528 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38409 /* 105531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38410 /* 105537 */ GIR_RootConstrainSelectedInstOperands,
38411 /* 105538 */ // GIR_Coverage, 885,
38412 /* 105538 */ GIR_EraseRootFromParent_Done,
38413 /* 105539 */ // Label 3232: @105539
38414 /* 105539 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3233*/ GIMT_Encode4(105599), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4455 //
38415 /* 105546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38416 /* 105550 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38417 /* 105554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38418 /* 105558 */ // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
38419 /* 105558 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38420 /* 105561 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38421 /* 105565 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38422 /* 105570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32),
38423 /* 105573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38424 /* 105575 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
38425 /* 105577 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
38426 /* 105579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38427 /* 105582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38428 /* 105588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38429 /* 105594 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38430 /* 105597 */ GIR_RootConstrainSelectedInstOperands,
38431 /* 105598 */ // GIR_Coverage, 4455,
38432 /* 105598 */ GIR_EraseRootFromParent_Done,
38433 /* 105599 */ // Label 3233: @105599
38434 /* 105599 */ GIM_Reject,
38435 /* 105600 */ // Label 3231: @105600
38436 /* 105600 */ GIM_Reject,
38437 /* 105601 */ // Label 3205: @105601
38438 /* 105601 */ GIM_Reject,
38439 /* 105602 */ // Label 41: @105602
38440 /* 105602 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3241*/ GIMT_Encode4(107254),
38441 /* 105613 */ /*GILLT_s16*//*Label 3234*/ GIMT_Encode4(105665),
38442 /* 105617 */ /*GILLT_s32*//*Label 3235*/ GIMT_Encode4(105711),
38443 /* 105621 */ /*GILLT_s64*//*Label 3236*/ GIMT_Encode4(106636), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38444 /* 105649 */ /*GILLT_v4s16*//*Label 3237*/ GIMT_Encode4(106682),
38445 /* 105653 */ /*GILLT_v8s16*//*Label 3238*/ GIMT_Encode4(106856),
38446 /* 105657 */ /*GILLT_v2s32*//*Label 3239*/ GIMT_Encode4(107096),
38447 /* 105661 */ /*GILLT_v4s32*//*Label 3240*/ GIMT_Encode4(107142),
38448 /* 105665 */ // Label 3234: @105665
38449 /* 105665 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3242*/ GIMT_Encode4(105710), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 627 //
38450 /* 105672 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
38451 /* 105675 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
38452 /* 105678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
38453 /* 105682 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
38454 /* 105686 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
38455 /* 105690 */ // (fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
38456 /* 105690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH),
38457 /* 105693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
38458 /* 105695 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
38459 /* 105697 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
38460 /* 105699 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38461 /* 105702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38462 /* 105708 */ GIR_RootConstrainSelectedInstOperands,
38463 /* 105709 */ // GIR_Coverage, 627,
38464 /* 105709 */ GIR_EraseRootFromParent_Done,
38465 /* 105710 */ // Label 3242: @105710
38466 /* 105710 */ GIM_Reject,
38467 /* 105711 */ // Label 3235: @105711
38468 /* 105711 */ GIM_Try, /*On fail goto*//*Label 3243*/ GIMT_Encode4(106635),
38469 /* 105716 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
38470 /* 105719 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
38471 /* 105722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38472 /* 105726 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38473 /* 105730 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3244*/ GIMT_Encode4(106053), GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP), // Rule ID 3090 //
38474 /* 105737 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38475 /* 105741 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38476 /* 105745 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38477 /* 105749 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38478 /* 105753 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38479 /* 105758 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38480 /* 105763 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38481 /* 105765 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
38482 /* 105765 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
38483 /* 105768 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38484 /* 105772 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38485 /* 105777 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
38486 /* 105779 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
38487 /* 105782 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38488 /* 105786 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38489 /* 105791 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
38490 /* 105794 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38491 /* 105799 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
38492 /* 105802 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38493 /* 105806 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38494 /* 105811 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
38495 /* 105814 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
38496 /* 105818 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
38497 /* 105821 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38498 /* 105826 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38499 /* 105831 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38500 /* 105836 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
38501 /* 105839 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38502 /* 105843 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38503 /* 105848 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
38504 /* 105850 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
38505 /* 105853 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38506 /* 105857 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38507 /* 105862 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
38508 /* 105865 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38509 /* 105870 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
38510 /* 105873 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38511 /* 105877 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38512 /* 105882 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
38513 /* 105885 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
38514 /* 105889 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
38515 /* 105892 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38516 /* 105897 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38517 /* 105902 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38518 /* 105907 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
38519 /* 105910 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38520 /* 105914 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38521 /* 105919 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
38522 /* 105921 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
38523 /* 105924 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38524 /* 105928 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38525 /* 105933 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
38526 /* 105936 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38527 /* 105941 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
38528 /* 105944 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38529 /* 105948 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38530 /* 105953 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
38531 /* 105956 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
38532 /* 105960 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
38533 /* 105963 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38534 /* 105968 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38535 /* 105973 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38536 /* 105978 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
38537 /* 105981 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLSfd),
38538 /* 105985 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38539 /* 105990 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
38540 /* 105993 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
38541 /* 105996 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
38542 /* 105999 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
38543 /* 106002 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38544 /* 106008 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38545 /* 106010 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
38546 /* 106013 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38547 /* 106017 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38548 /* 106022 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
38549 /* 106025 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38550 /* 106030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38551 /* 106033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38552 /* 106035 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
38553 /* 106042 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
38554 /* 106047 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38555 /* 106052 */ // GIR_Coverage, 3090,
38556 /* 106052 */ GIR_EraseRootFromParent_Done,
38557 /* 106053 */ // Label 3244: @106053
38558 /* 106053 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3245*/ GIMT_Encode4(106376), GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP), // Rule ID 3092 //
38559 /* 106060 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38560 /* 106064 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38561 /* 106068 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38562 /* 106072 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
38563 /* 106076 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38564 /* 106081 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38565 /* 106086 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38566 /* 106088 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
38567 /* 106088 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
38568 /* 106091 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38569 /* 106095 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38570 /* 106100 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
38571 /* 106102 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
38572 /* 106105 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38573 /* 106109 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38574 /* 106114 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
38575 /* 106117 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38576 /* 106122 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
38577 /* 106125 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38578 /* 106129 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38579 /* 106134 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
38580 /* 106137 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
38581 /* 106141 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
38582 /* 106144 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38583 /* 106149 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38584 /* 106154 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38585 /* 106159 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
38586 /* 106162 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38587 /* 106166 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38588 /* 106171 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
38589 /* 106173 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
38590 /* 106176 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38591 /* 106180 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38592 /* 106185 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
38593 /* 106188 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38594 /* 106193 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
38595 /* 106196 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38596 /* 106200 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38597 /* 106205 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
38598 /* 106208 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
38599 /* 106212 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
38600 /* 106215 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38601 /* 106220 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38602 /* 106225 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38603 /* 106230 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
38604 /* 106233 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38605 /* 106237 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38606 /* 106242 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
38607 /* 106244 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
38608 /* 106247 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38609 /* 106251 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38610 /* 106256 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
38611 /* 106259 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38612 /* 106264 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
38613 /* 106267 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38614 /* 106271 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38615 /* 106276 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
38616 /* 106279 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
38617 /* 106283 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
38618 /* 106286 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38619 /* 106291 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38620 /* 106296 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38621 /* 106301 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
38622 /* 106304 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMSfd),
38623 /* 106308 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38624 /* 106313 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
38625 /* 106316 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
38626 /* 106319 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
38627 /* 106322 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
38628 /* 106325 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38629 /* 106331 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38630 /* 106333 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
38631 /* 106336 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38632 /* 106340 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38633 /* 106345 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
38634 /* 106348 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38635 /* 106353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38636 /* 106356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38637 /* 106358 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
38638 /* 106365 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
38639 /* 106370 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38640 /* 106375 */ // GIR_Coverage, 3092,
38641 /* 106375 */ GIR_EraseRootFromParent_Done,
38642 /* 106376 */ // Label 3245: @106376
38643 /* 106376 */ GIM_Try, /*On fail goto*//*Label 3246*/ GIMT_Encode4(106634),
38644 /* 106381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38645 /* 106385 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3247*/ GIMT_Encode4(106412), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 625 //
38646 /* 106392 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
38647 /* 106392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS),
38648 /* 106395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
38649 /* 106397 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
38650 /* 106399 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
38651 /* 106401 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38652 /* 106404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38653 /* 106410 */ GIR_RootConstrainSelectedInstOperands,
38654 /* 106411 */ // GIR_Coverage, 625,
38655 /* 106411 */ GIR_EraseRootFromParent_Done,
38656 /* 106412 */ // Label 3247: @106412
38657 /* 106412 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3248*/ GIMT_Encode4(106633), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3087 //
38658 /* 106419 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VSUBfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
38659 /* 106419 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
38660 /* 106422 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38661 /* 106426 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38662 /* 106431 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
38663 /* 106433 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
38664 /* 106436 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38665 /* 106440 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38666 /* 106445 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
38667 /* 106448 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38668 /* 106453 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
38669 /* 106456 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38670 /* 106460 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38671 /* 106465 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
38672 /* 106468 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
38673 /* 106472 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
38674 /* 106475 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38675 /* 106480 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38676 /* 106485 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38677 /* 106490 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
38678 /* 106493 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38679 /* 106497 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38680 /* 106502 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
38681 /* 106504 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
38682 /* 106507 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38683 /* 106511 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38684 /* 106516 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
38685 /* 106519 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38686 /* 106524 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
38687 /* 106527 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
38688 /* 106531 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38689 /* 106536 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
38690 /* 106539 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
38691 /* 106543 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
38692 /* 106546 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38693 /* 106551 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38694 /* 106556 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
38695 /* 106561 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
38696 /* 106564 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VSUBfd),
38697 /* 106568 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38698 /* 106573 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
38699 /* 106576 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
38700 /* 106579 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
38701 /* 106582 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38702 /* 106588 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
38703 /* 106590 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
38704 /* 106593 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38705 /* 106597 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38706 /* 106602 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
38707 /* 106605 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38708 /* 106610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
38709 /* 106613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38710 /* 106615 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
38711 /* 106622 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
38712 /* 106627 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
38713 /* 106632 */ // GIR_Coverage, 3087,
38714 /* 106632 */ GIR_EraseRootFromParent_Done,
38715 /* 106633 */ // Label 3248: @106633
38716 /* 106633 */ GIM_Reject,
38717 /* 106634 */ // Label 3246: @106634
38718 /* 106634 */ GIM_Reject,
38719 /* 106635 */ // Label 3243: @106635
38720 /* 106635 */ GIM_Reject,
38721 /* 106636 */ // Label 3236: @106636
38722 /* 106636 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3249*/ GIMT_Encode4(106681), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 623 //
38723 /* 106643 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
38724 /* 106646 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
38725 /* 106649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38726 /* 106653 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38727 /* 106657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38728 /* 106661 */ // (fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
38729 /* 106661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD),
38730 /* 106664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
38731 /* 106666 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
38732 /* 106668 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
38733 /* 106670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38734 /* 106673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38735 /* 106679 */ GIR_RootConstrainSelectedInstOperands,
38736 /* 106680 */ // GIR_Coverage, 623,
38737 /* 106680 */ GIR_EraseRootFromParent_Done,
38738 /* 106681 */ // Label 3249: @106681
38739 /* 106681 */ GIM_Reject,
38740 /* 106682 */ // Label 3237: @106682
38741 /* 106682 */ GIM_Try, /*On fail goto*//*Label 3250*/ GIMT_Encode4(106855),
38742 /* 106687 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
38743 /* 106690 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
38744 /* 106693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38745 /* 106697 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38746 /* 106701 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3251*/ GIMT_Encode4(106762), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx), // Rule ID 1067 //
38747 /* 106708 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38748 /* 106712 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38749 /* 106716 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
38750 /* 106720 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38751 /* 106724 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38752 /* 106729 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38753 /* 106734 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38754 /* 106736 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VMLShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
38755 /* 106736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShd),
38756 /* 106739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38757 /* 106741 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
38758 /* 106743 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38759 /* 106747 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38760 /* 106751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38761 /* 106754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38762 /* 106760 */ GIR_RootConstrainSelectedInstOperands,
38763 /* 106761 */ // GIR_Coverage, 1067,
38764 /* 106761 */ GIR_EraseRootFromParent_Done,
38765 /* 106762 */ // Label 3251: @106762
38766 /* 106762 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3252*/ GIMT_Encode4(106823), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1111 //
38767 /* 106769 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38768 /* 106773 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38769 /* 106777 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
38770 /* 106781 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38771 /* 106785 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38772 /* 106790 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38773 /* 106795 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38774 /* 106797 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
38775 /* 106797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShd),
38776 /* 106800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38777 /* 106802 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
38778 /* 106804 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38779 /* 106808 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38780 /* 106812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38781 /* 106815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38782 /* 106821 */ GIR_RootConstrainSelectedInstOperands,
38783 /* 106822 */ // GIR_Coverage, 1111,
38784 /* 106822 */ GIR_EraseRootFromParent_Done,
38785 /* 106823 */ // Label 3252: @106823
38786 /* 106823 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3253*/ GIMT_Encode4(106854), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1132 //
38787 /* 106830 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38788 /* 106834 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VSUBhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
38789 /* 106834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhd),
38790 /* 106837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38791 /* 106839 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
38792 /* 106841 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
38793 /* 106843 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38794 /* 106846 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38795 /* 106852 */ GIR_RootConstrainSelectedInstOperands,
38796 /* 106853 */ // GIR_Coverage, 1132,
38797 /* 106853 */ GIR_EraseRootFromParent_Done,
38798 /* 106854 */ // Label 3253: @106854
38799 /* 106854 */ GIM_Reject,
38800 /* 106855 */ // Label 3250: @106855
38801 /* 106855 */ GIM_Reject,
38802 /* 106856 */ // Label 3238: @106856
38803 /* 106856 */ GIM_Try, /*On fail goto*//*Label 3254*/ GIMT_Encode4(107095),
38804 /* 106861 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
38805 /* 106864 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
38806 /* 106867 */ GIM_Try, /*On fail goto*//*Label 3255*/ GIMT_Encode4(107034),
38807 /* 106872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38808 /* 106876 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38809 /* 106880 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3256*/ GIMT_Encode4(106941), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx), // Rule ID 1068 //
38810 /* 106887 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38811 /* 106891 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38812 /* 106895 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
38813 /* 106899 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
38814 /* 106903 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38815 /* 106908 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38816 /* 106913 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38817 /* 106915 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VMLShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
38818 /* 106915 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShq),
38819 /* 106918 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38820 /* 106920 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
38821 /* 106922 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38822 /* 106926 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38823 /* 106930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38824 /* 106933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38825 /* 106939 */ GIR_RootConstrainSelectedInstOperands,
38826 /* 106940 */ // GIR_Coverage, 1068,
38827 /* 106940 */ GIR_EraseRootFromParent_Done,
38828 /* 106941 */ // Label 3256: @106941
38829 /* 106941 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3257*/ GIMT_Encode4(107002), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC), // Rule ID 1112 //
38830 /* 106948 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
38831 /* 106952 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
38832 /* 106956 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
38833 /* 106960 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
38834 /* 106964 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38835 /* 106969 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38836 /* 106974 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38837 /* 106976 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
38838 /* 106976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShq),
38839 /* 106979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38840 /* 106981 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
38841 /* 106983 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38842 /* 106987 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38843 /* 106991 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38844 /* 106994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38845 /* 107000 */ GIR_RootConstrainSelectedInstOperands,
38846 /* 107001 */ // GIR_Coverage, 1112,
38847 /* 107001 */ GIR_EraseRootFromParent_Done,
38848 /* 107002 */ // Label 3257: @107002
38849 /* 107002 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3258*/ GIMT_Encode4(107033), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1133 //
38850 /* 107009 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38851 /* 107013 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VSUBhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
38852 /* 107013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhq),
38853 /* 107016 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38854 /* 107018 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
38855 /* 107020 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
38856 /* 107022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38857 /* 107025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38858 /* 107031 */ GIR_RootConstrainSelectedInstOperands,
38859 /* 107032 */ // GIR_Coverage, 1133,
38860 /* 107032 */ GIR_EraseRootFromParent_Done,
38861 /* 107033 */ // Label 3258: @107033
38862 /* 107033 */ GIM_Reject,
38863 /* 107034 */ // Label 3255: @107034
38864 /* 107034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3259*/ GIMT_Encode4(107094), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4476 //
38865 /* 107041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38866 /* 107045 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38867 /* 107049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38868 /* 107053 */ // (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
38869 /* 107053 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38870 /* 107056 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38871 /* 107060 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38872 /* 107065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16),
38873 /* 107068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38874 /* 107070 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
38875 /* 107072 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
38876 /* 107074 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38877 /* 107077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38878 /* 107083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38879 /* 107089 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38880 /* 107092 */ GIR_RootConstrainSelectedInstOperands,
38881 /* 107093 */ // GIR_Coverage, 4476,
38882 /* 107093 */ GIR_EraseRootFromParent_Done,
38883 /* 107094 */ // Label 3259: @107094
38884 /* 107094 */ GIM_Reject,
38885 /* 107095 */ // Label 3254: @107095
38886 /* 107095 */ GIM_Reject,
38887 /* 107096 */ // Label 3239: @107096
38888 /* 107096 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3260*/ GIMT_Encode4(107141), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1130 //
38889 /* 107103 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
38890 /* 107106 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
38891 /* 107109 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38892 /* 107113 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38893 /* 107117 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38894 /* 107121 */ // (fsub:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VSUBfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
38895 /* 107121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfd),
38896 /* 107124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38897 /* 107126 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
38898 /* 107128 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
38899 /* 107130 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38900 /* 107133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38901 /* 107139 */ GIR_RootConstrainSelectedInstOperands,
38902 /* 107140 */ // GIR_Coverage, 1130,
38903 /* 107140 */ GIR_EraseRootFromParent_Done,
38904 /* 107141 */ // Label 3260: @107141
38905 /* 107141 */ GIM_Reject,
38906 /* 107142 */ // Label 3240: @107142
38907 /* 107142 */ GIM_Try, /*On fail goto*//*Label 3261*/ GIMT_Encode4(107253),
38908 /* 107147 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
38909 /* 107150 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
38910 /* 107153 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3262*/ GIMT_Encode4(107192), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1131 //
38911 /* 107160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38912 /* 107164 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38913 /* 107168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38914 /* 107172 */ // (fsub:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VSUBfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
38915 /* 107172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfq),
38916 /* 107175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38917 /* 107177 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
38918 /* 107179 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
38919 /* 107181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38920 /* 107184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38921 /* 107190 */ GIR_RootConstrainSelectedInstOperands,
38922 /* 107191 */ // GIR_Coverage, 1131,
38923 /* 107191 */ GIR_EraseRootFromParent_Done,
38924 /* 107192 */ // Label 3262: @107192
38925 /* 107192 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3263*/ GIMT_Encode4(107252), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4469 //
38926 /* 107199 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38927 /* 107203 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38928 /* 107207 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38929 /* 107211 */ // (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
38930 /* 107211 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38931 /* 107214 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38932 /* 107218 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38933 /* 107223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32),
38934 /* 107226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38935 /* 107228 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
38936 /* 107230 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
38937 /* 107232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38938 /* 107235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38939 /* 107241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38940 /* 107247 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38941 /* 107250 */ GIR_RootConstrainSelectedInstOperands,
38942 /* 107251 */ // GIR_Coverage, 4469,
38943 /* 107251 */ GIR_EraseRootFromParent_Done,
38944 /* 107252 */ // Label 3263: @107252
38945 /* 107252 */ GIM_Reject,
38946 /* 107253 */ // Label 3261: @107253
38947 /* 107253 */ GIM_Reject,
38948 /* 107254 */ // Label 3241: @107254
38949 /* 107254 */ GIM_Reject,
38950 /* 107255 */ // Label 42: @107255
38951 /* 107255 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3271*/ GIMT_Encode4(108223),
38952 /* 107266 */ /*GILLT_s16*//*Label 3264*/ GIMT_Encode4(107318),
38953 /* 107270 */ /*GILLT_s32*//*Label 3265*/ GIMT_Encode4(107364),
38954 /* 107274 */ /*GILLT_s64*//*Label 3266*/ GIMT_Encode4(107749), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38955 /* 107302 */ /*GILLT_v4s16*//*Label 3267*/ GIMT_Encode4(107907),
38956 /* 107306 */ /*GILLT_v8s16*//*Label 3268*/ GIMT_Encode4(107953),
38957 /* 107310 */ /*GILLT_v2s32*//*Label 3269*/ GIMT_Encode4(108065),
38958 /* 107314 */ /*GILLT_v4s32*//*Label 3270*/ GIMT_Encode4(108111),
38959 /* 107318 */ // Label 3264: @107318
38960 /* 107318 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3272*/ GIMT_Encode4(107363), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 639 //
38961 /* 107325 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
38962 /* 107328 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
38963 /* 107331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
38964 /* 107335 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
38965 /* 107339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
38966 /* 107343 */ // (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
38967 /* 107343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH),
38968 /* 107346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
38969 /* 107348 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
38970 /* 107350 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
38971 /* 107352 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38972 /* 107355 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38973 /* 107361 */ GIR_RootConstrainSelectedInstOperands,
38974 /* 107362 */ // GIR_Coverage, 639,
38975 /* 107362 */ GIR_EraseRootFromParent_Done,
38976 /* 107363 */ // Label 3272: @107363
38977 /* 107363 */ GIM_Reject,
38978 /* 107364 */ // Label 3265: @107364
38979 /* 107364 */ GIM_Try, /*On fail goto*//*Label 3273*/ GIMT_Encode4(107748),
38980 /* 107369 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
38981 /* 107372 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
38982 /* 107375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38983 /* 107379 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3274*/ GIMT_Encode4(107431), GIMT_Encode2(GIFBS_NoHonorSignDependentRounding), // Rule ID 2502 //
38984 /* 107386 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38985 /* 107390 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
38986 /* 107394 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
38987 /* 107398 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38988 /* 107403 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38989 /* 107407 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38990 /* 107409 */ // (fmul:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
38991 /* 107409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
38992 /* 107412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
38993 /* 107414 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
38994 /* 107418 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
38995 /* 107420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38996 /* 107423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38997 /* 107429 */ GIR_RootConstrainSelectedInstOperands,
38998 /* 107430 */ // GIR_Coverage, 2502,
38999 /* 107430 */ GIR_EraseRootFromParent_Done,
39000 /* 107431 */ // Label 3274: @107431
39001 /* 107431 */ GIM_Try, /*On fail goto*//*Label 3275*/ GIMT_Encode4(107747),
39002 /* 107436 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39003 /* 107440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3276*/ GIMT_Encode4(107488), GIMT_Encode2(GIFBS_NoHonorSignDependentRounding), // Rule ID 6320 //
39004 /* 107447 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39005 /* 107451 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39006 /* 107455 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39007 /* 107459 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39008 /* 107464 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39009 /* 107466 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
39010 /* 107466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
39011 /* 107469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39012 /* 107471 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
39013 /* 107475 */ GIR_RootToRootCopy, /*OpIdx*/1, // b
39014 /* 107477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39015 /* 107480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39016 /* 107486 */ GIR_RootConstrainSelectedInstOperands,
39017 /* 107487 */ // GIR_Coverage, 6320,
39018 /* 107487 */ GIR_EraseRootFromParent_Done,
39019 /* 107488 */ // Label 3276: @107488
39020 /* 107488 */ GIM_Try, /*On fail goto*//*Label 3277*/ GIMT_Encode4(107746),
39021 /* 107493 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39022 /* 107497 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3278*/ GIMT_Encode4(107524), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 637 //
39023 /* 107504 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
39024 /* 107504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS),
39025 /* 107507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39026 /* 107509 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
39027 /* 107511 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39028 /* 107513 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39029 /* 107516 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39030 /* 107522 */ GIR_RootConstrainSelectedInstOperands,
39031 /* 107523 */ // GIR_Coverage, 637,
39032 /* 107523 */ GIR_EraseRootFromParent_Done,
39033 /* 107524 */ // Label 3278: @107524
39034 /* 107524 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3279*/ GIMT_Encode4(107745), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3088 //
39035 /* 107531 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMULfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
39036 /* 107531 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
39037 /* 107534 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39038 /* 107538 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39039 /* 107543 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
39040 /* 107545 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
39041 /* 107548 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39042 /* 107552 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39043 /* 107557 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
39044 /* 107560 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39045 /* 107565 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
39046 /* 107568 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
39047 /* 107572 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39048 /* 107577 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
39049 /* 107580 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
39050 /* 107584 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
39051 /* 107587 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39052 /* 107592 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39053 /* 107597 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
39054 /* 107602 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
39055 /* 107605 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39056 /* 107609 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39057 /* 107614 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
39058 /* 107616 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
39059 /* 107619 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39060 /* 107623 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39061 /* 107628 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
39062 /* 107631 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39063 /* 107636 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
39064 /* 107639 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
39065 /* 107643 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39066 /* 107648 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
39067 /* 107651 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
39068 /* 107655 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
39069 /* 107658 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39070 /* 107663 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39071 /* 107668 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
39072 /* 107673 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
39073 /* 107676 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMULfd),
39074 /* 107680 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39075 /* 107685 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
39076 /* 107688 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
39077 /* 107691 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
39078 /* 107694 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39079 /* 107700 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
39080 /* 107702 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
39081 /* 107705 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39082 /* 107709 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39083 /* 107714 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
39084 /* 107717 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39085 /* 107722 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
39086 /* 107725 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
39087 /* 107727 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
39088 /* 107734 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
39089 /* 107739 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
39090 /* 107744 */ // GIR_Coverage, 3088,
39091 /* 107744 */ GIR_EraseRootFromParent_Done,
39092 /* 107745 */ // Label 3279: @107745
39093 /* 107745 */ GIM_Reject,
39094 /* 107746 */ // Label 3277: @107746
39095 /* 107746 */ GIM_Reject,
39096 /* 107747 */ // Label 3275: @107747
39097 /* 107747 */ GIM_Reject,
39098 /* 107748 */ // Label 3273: @107748
39099 /* 107748 */ GIM_Reject,
39100 /* 107749 */ // Label 3266: @107749
39101 /* 107749 */ GIM_Try, /*On fail goto*//*Label 3280*/ GIMT_Encode4(107906),
39102 /* 107754 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
39103 /* 107757 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
39104 /* 107760 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39105 /* 107764 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3281*/ GIMT_Encode4(107816), GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding), // Rule ID 2501 //
39106 /* 107771 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39107 /* 107775 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39108 /* 107779 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
39109 /* 107783 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39110 /* 107788 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39111 /* 107792 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39112 /* 107794 */ // (fmul:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a), DPR:{ *:[f64] }:$b) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
39113 /* 107794 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
39114 /* 107797 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39115 /* 107799 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
39116 /* 107803 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
39117 /* 107805 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39118 /* 107808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39119 /* 107814 */ GIR_RootConstrainSelectedInstOperands,
39120 /* 107815 */ // GIR_Coverage, 2501,
39121 /* 107815 */ GIR_EraseRootFromParent_Done,
39122 /* 107816 */ // Label 3281: @107816
39123 /* 107816 */ GIM_Try, /*On fail goto*//*Label 3282*/ GIMT_Encode4(107905),
39124 /* 107821 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39125 /* 107825 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3283*/ GIMT_Encode4(107873), GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding), // Rule ID 6319 //
39126 /* 107832 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39127 /* 107836 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39128 /* 107840 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
39129 /* 107844 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39130 /* 107849 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39131 /* 107851 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$b, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
39132 /* 107851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
39133 /* 107854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39134 /* 107856 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
39135 /* 107860 */ GIR_RootToRootCopy, /*OpIdx*/1, // b
39136 /* 107862 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39137 /* 107865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39138 /* 107871 */ GIR_RootConstrainSelectedInstOperands,
39139 /* 107872 */ // GIR_Coverage, 6319,
39140 /* 107872 */ GIR_EraseRootFromParent_Done,
39141 /* 107873 */ // Label 3283: @107873
39142 /* 107873 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3284*/ GIMT_Encode4(107904), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 635 //
39143 /* 107880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39144 /* 107884 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
39145 /* 107884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD),
39146 /* 107887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39147 /* 107889 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
39148 /* 107891 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
39149 /* 107893 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39150 /* 107896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39151 /* 107902 */ GIR_RootConstrainSelectedInstOperands,
39152 /* 107903 */ // GIR_Coverage, 635,
39153 /* 107903 */ GIR_EraseRootFromParent_Done,
39154 /* 107904 */ // Label 3284: @107904
39155 /* 107904 */ GIM_Reject,
39156 /* 107905 */ // Label 3282: @107905
39157 /* 107905 */ GIM_Reject,
39158 /* 107906 */ // Label 3280: @107906
39159 /* 107906 */ GIM_Reject,
39160 /* 107907 */ // Label 3267: @107907
39161 /* 107907 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3285*/ GIMT_Encode4(107952), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 965 //
39162 /* 107914 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
39163 /* 107917 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
39164 /* 107920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39165 /* 107924 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39166 /* 107928 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39167 /* 107932 */ // (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMULhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
39168 /* 107932 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhd),
39169 /* 107935 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39170 /* 107937 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39171 /* 107939 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39172 /* 107941 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39173 /* 107944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39174 /* 107950 */ GIR_RootConstrainSelectedInstOperands,
39175 /* 107951 */ // GIR_Coverage, 965,
39176 /* 107951 */ GIR_EraseRootFromParent_Done,
39177 /* 107952 */ // Label 3285: @107952
39178 /* 107952 */ GIM_Reject,
39179 /* 107953 */ // Label 3268: @107953
39180 /* 107953 */ GIM_Try, /*On fail goto*//*Label 3286*/ GIMT_Encode4(108064),
39181 /* 107958 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
39182 /* 107961 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
39183 /* 107964 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3287*/ GIMT_Encode4(108003), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 966 //
39184 /* 107971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39185 /* 107975 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39186 /* 107979 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39187 /* 107983 */ // (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMULhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
39188 /* 107983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhq),
39189 /* 107986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39190 /* 107988 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39191 /* 107990 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39192 /* 107992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39193 /* 107995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39194 /* 108001 */ GIR_RootConstrainSelectedInstOperands,
39195 /* 108002 */ // GIR_Coverage, 966,
39196 /* 108002 */ GIR_EraseRootFromParent_Done,
39197 /* 108003 */ // Label 3287: @108003
39198 /* 108003 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3288*/ GIMT_Encode4(108063), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4422 //
39199 /* 108010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39200 /* 108014 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39201 /* 108018 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39202 /* 108022 */ // (fmul:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
39203 /* 108022 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39204 /* 108025 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39205 /* 108029 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39206 /* 108034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16),
39207 /* 108037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39208 /* 108039 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39209 /* 108041 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39210 /* 108043 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39211 /* 108046 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39212 /* 108052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39213 /* 108058 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39214 /* 108061 */ GIR_RootConstrainSelectedInstOperands,
39215 /* 108062 */ // GIR_Coverage, 4422,
39216 /* 108062 */ GIR_EraseRootFromParent_Done,
39217 /* 108063 */ // Label 3288: @108063
39218 /* 108063 */ GIM_Reject,
39219 /* 108064 */ // Label 3286: @108064
39220 /* 108064 */ GIM_Reject,
39221 /* 108065 */ // Label 3269: @108065
39222 /* 108065 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3289*/ GIMT_Encode4(108110), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 963 //
39223 /* 108072 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
39224 /* 108075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
39225 /* 108078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39226 /* 108082 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39227 /* 108086 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39228 /* 108090 */ // (fmul:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMULfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
39229 /* 108090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfd),
39230 /* 108093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39231 /* 108095 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39232 /* 108097 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39233 /* 108099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39234 /* 108102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39235 /* 108108 */ GIR_RootConstrainSelectedInstOperands,
39236 /* 108109 */ // GIR_Coverage, 963,
39237 /* 108109 */ GIR_EraseRootFromParent_Done,
39238 /* 108110 */ // Label 3289: @108110
39239 /* 108110 */ GIM_Reject,
39240 /* 108111 */ // Label 3270: @108111
39241 /* 108111 */ GIM_Try, /*On fail goto*//*Label 3290*/ GIMT_Encode4(108222),
39242 /* 108116 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
39243 /* 108119 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
39244 /* 108122 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3291*/ GIMT_Encode4(108161), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 964 //
39245 /* 108129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39246 /* 108133 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39247 /* 108137 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39248 /* 108141 */ // (fmul:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMULfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
39249 /* 108141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfq),
39250 /* 108144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39251 /* 108146 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39252 /* 108148 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39253 /* 108150 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39254 /* 108153 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39255 /* 108159 */ GIR_RootConstrainSelectedInstOperands,
39256 /* 108160 */ // GIR_Coverage, 964,
39257 /* 108160 */ GIR_EraseRootFromParent_Done,
39258 /* 108161 */ // Label 3291: @108161
39259 /* 108161 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3292*/ GIMT_Encode4(108221), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4415 //
39260 /* 108168 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39261 /* 108172 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39262 /* 108176 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39263 /* 108180 */ // (fmul:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
39264 /* 108180 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39265 /* 108183 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39266 /* 108187 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39267 /* 108192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32),
39268 /* 108195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39269 /* 108197 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39270 /* 108199 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39271 /* 108201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39272 /* 108204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39273 /* 108210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39274 /* 108216 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39275 /* 108219 */ GIR_RootConstrainSelectedInstOperands,
39276 /* 108220 */ // GIR_Coverage, 4415,
39277 /* 108220 */ GIR_EraseRootFromParent_Done,
39278 /* 108221 */ // Label 3292: @108221
39279 /* 108221 */ GIM_Reject,
39280 /* 108222 */ // Label 3290: @108222
39281 /* 108222 */ GIM_Reject,
39282 /* 108223 */ // Label 3271: @108223
39283 /* 108223 */ GIM_Reject,
39284 /* 108224 */ // Label 43: @108224
39285 /* 108224 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3300*/ GIMT_Encode4(110286),
39286 /* 108235 */ /*GILLT_s16*//*Label 3293*/ GIMT_Encode4(108287),
39287 /* 108239 */ /*GILLT_s32*//*Label 3294*/ GIMT_Encode4(108668),
39288 /* 108243 */ /*GILLT_s64*//*Label 3295*/ GIMT_Encode4(109049), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
39289 /* 108271 */ /*GILLT_v4s16*//*Label 3296*/ GIMT_Encode4(109430),
39290 /* 108275 */ /*GILLT_v8s16*//*Label 3297*/ GIMT_Encode4(109485),
39291 /* 108279 */ /*GILLT_v2s32*//*Label 3298*/ GIMT_Encode4(109735),
39292 /* 108283 */ /*GILLT_v4s32*//*Label 3299*/ GIMT_Encode4(109914),
39293 /* 108287 */ // Label 3293: @108287
39294 /* 108287 */ GIM_Try, /*On fail goto*//*Label 3301*/ GIMT_Encode4(108667),
39295 /* 108292 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
39296 /* 108295 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
39297 /* 108298 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
39298 /* 108301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39299 /* 108305 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3302*/ GIMT_Encode4(108378), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2775 //
39300 /* 108312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39301 /* 108316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39302 /* 108320 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
39303 /* 108324 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39304 /* 108329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39305 /* 108333 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
39306 /* 108337 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
39307 /* 108341 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
39308 /* 108345 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39309 /* 108350 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39310 /* 108352 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
39311 /* 108352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
39312 /* 108355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39313 /* 108357 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
39314 /* 108361 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39315 /* 108365 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39316 /* 108367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39317 /* 108370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39318 /* 108376 */ GIR_RootConstrainSelectedInstOperands,
39319 /* 108377 */ // GIR_Coverage, 2775,
39320 /* 108377 */ GIR_EraseRootFromParent_Done,
39321 /* 108378 */ // Label 3302: @108378
39322 /* 108378 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3303*/ GIMT_Encode4(108451), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6340 //
39323 /* 108385 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39324 /* 108389 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39325 /* 108393 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39326 /* 108397 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
39327 /* 108401 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39328 /* 108406 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
39329 /* 108410 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
39330 /* 108414 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
39331 /* 108418 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39332 /* 108423 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39333 /* 108425 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
39334 /* 108425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
39335 /* 108428 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39336 /* 108430 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
39337 /* 108434 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39338 /* 108438 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
39339 /* 108440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39340 /* 108443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39341 /* 108449 */ GIR_RootConstrainSelectedInstOperands,
39342 /* 108450 */ // GIR_Coverage, 6340,
39343 /* 108450 */ GIR_EraseRootFromParent_Done,
39344 /* 108451 */ // Label 3303: @108451
39345 /* 108451 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3304*/ GIMT_Encode4(108509), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2755 //
39346 /* 108458 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39347 /* 108462 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39348 /* 108466 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
39349 /* 108470 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39350 /* 108475 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39351 /* 108479 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39352 /* 108483 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39353 /* 108485 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
39354 /* 108485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
39355 /* 108488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39356 /* 108490 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
39357 /* 108492 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39358 /* 108496 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39359 /* 108498 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39360 /* 108501 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39361 /* 108507 */ GIR_RootConstrainSelectedInstOperands,
39362 /* 108508 */ // GIR_Coverage, 2755,
39363 /* 108508 */ GIR_EraseRootFromParent_Done,
39364 /* 108509 */ // Label 3304: @108509
39365 /* 108509 */ GIM_Try, /*On fail goto*//*Label 3305*/ GIMT_Encode4(108666),
39366 /* 108514 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39367 /* 108518 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3306*/ GIMT_Encode4(108572), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6334 //
39368 /* 108525 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39369 /* 108529 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39370 /* 108533 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
39371 /* 108537 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39372 /* 108542 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39373 /* 108546 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39374 /* 108548 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
39375 /* 108548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
39376 /* 108551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39377 /* 108553 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
39378 /* 108555 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39379 /* 108559 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
39380 /* 108561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39381 /* 108564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39382 /* 108570 */ GIR_RootConstrainSelectedInstOperands,
39383 /* 108571 */ // GIR_Coverage, 6334,
39384 /* 108571 */ GIR_EraseRootFromParent_Done,
39385 /* 108572 */ // Label 3306: @108572
39386 /* 108572 */ GIM_Try, /*On fail goto*//*Label 3307*/ GIMT_Encode4(108665),
39387 /* 108577 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39388 /* 108581 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3308*/ GIMT_Encode4(108631), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2789 //
39389 /* 108588 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
39390 /* 108592 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39391 /* 108596 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
39392 /* 108600 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39393 /* 108605 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39394 /* 108607 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
39395 /* 108607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
39396 /* 108610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39397 /* 108612 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
39398 /* 108616 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
39399 /* 108618 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39400 /* 108620 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39401 /* 108623 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39402 /* 108629 */ GIR_RootConstrainSelectedInstOperands,
39403 /* 108630 */ // GIR_Coverage, 2789,
39404 /* 108630 */ GIR_EraseRootFromParent_Done,
39405 /* 108631 */ // Label 3308: @108631
39406 /* 108631 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3309*/ GIMT_Encode4(108664), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2737 //
39407 /* 108638 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
39408 /* 108642 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
39409 /* 108642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH),
39410 /* 108645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39411 /* 108647 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
39412 /* 108649 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
39413 /* 108651 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39414 /* 108653 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39415 /* 108656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39416 /* 108662 */ GIR_RootConstrainSelectedInstOperands,
39417 /* 108663 */ // GIR_Coverage, 2737,
39418 /* 108663 */ GIR_EraseRootFromParent_Done,
39419 /* 108664 */ // Label 3309: @108664
39420 /* 108664 */ GIM_Reject,
39421 /* 108665 */ // Label 3307: @108665
39422 /* 108665 */ GIM_Reject,
39423 /* 108666 */ // Label 3305: @108666
39424 /* 108666 */ GIM_Reject,
39425 /* 108667 */ // Label 3301: @108667
39426 /* 108667 */ GIM_Reject,
39427 /* 108668 */ // Label 3294: @108668
39428 /* 108668 */ GIM_Try, /*On fail goto*//*Label 3310*/ GIMT_Encode4(109048),
39429 /* 108673 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
39430 /* 108676 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
39431 /* 108679 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
39432 /* 108682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39433 /* 108686 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3311*/ GIMT_Encode4(108759), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2773 //
39434 /* 108693 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39435 /* 108697 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39436 /* 108701 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39437 /* 108705 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39438 /* 108710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39439 /* 108714 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
39440 /* 108718 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
39441 /* 108722 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
39442 /* 108726 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39443 /* 108731 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39444 /* 108733 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
39445 /* 108733 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
39446 /* 108736 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39447 /* 108738 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
39448 /* 108742 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39449 /* 108746 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39450 /* 108748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39451 /* 108751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39452 /* 108757 */ GIR_RootConstrainSelectedInstOperands,
39453 /* 108758 */ // GIR_Coverage, 2773,
39454 /* 108758 */ GIR_EraseRootFromParent_Done,
39455 /* 108759 */ // Label 3311: @108759
39456 /* 108759 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3312*/ GIMT_Encode4(108832), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6338 //
39457 /* 108766 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39458 /* 108770 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39459 /* 108774 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39460 /* 108778 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39461 /* 108782 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39462 /* 108787 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
39463 /* 108791 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
39464 /* 108795 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
39465 /* 108799 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39466 /* 108804 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39467 /* 108806 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
39468 /* 108806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
39469 /* 108809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39470 /* 108811 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
39471 /* 108815 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39472 /* 108819 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
39473 /* 108821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39474 /* 108824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39475 /* 108830 */ GIR_RootConstrainSelectedInstOperands,
39476 /* 108831 */ // GIR_Coverage, 6338,
39477 /* 108831 */ GIR_EraseRootFromParent_Done,
39478 /* 108832 */ // Label 3312: @108832
39479 /* 108832 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3313*/ GIMT_Encode4(108890), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2753 //
39480 /* 108839 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39481 /* 108843 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39482 /* 108847 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39483 /* 108851 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39484 /* 108856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39485 /* 108860 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39486 /* 108864 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39487 /* 108866 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
39488 /* 108866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
39489 /* 108869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39490 /* 108871 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
39491 /* 108873 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39492 /* 108877 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39493 /* 108879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39494 /* 108882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39495 /* 108888 */ GIR_RootConstrainSelectedInstOperands,
39496 /* 108889 */ // GIR_Coverage, 2753,
39497 /* 108889 */ GIR_EraseRootFromParent_Done,
39498 /* 108890 */ // Label 3313: @108890
39499 /* 108890 */ GIM_Try, /*On fail goto*//*Label 3314*/ GIMT_Encode4(109047),
39500 /* 108895 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39501 /* 108899 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3315*/ GIMT_Encode4(108953), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6332 //
39502 /* 108906 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39503 /* 108910 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39504 /* 108914 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39505 /* 108918 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39506 /* 108923 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39507 /* 108927 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39508 /* 108929 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
39509 /* 108929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
39510 /* 108932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39511 /* 108934 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
39512 /* 108936 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
39513 /* 108940 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
39514 /* 108942 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39515 /* 108945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39516 /* 108951 */ GIR_RootConstrainSelectedInstOperands,
39517 /* 108952 */ // GIR_Coverage, 6332,
39518 /* 108952 */ GIR_EraseRootFromParent_Done,
39519 /* 108953 */ // Label 3315: @108953
39520 /* 108953 */ GIM_Try, /*On fail goto*//*Label 3316*/ GIMT_Encode4(109046),
39521 /* 108958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39522 /* 108962 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3317*/ GIMT_Encode4(109012), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2787 //
39523 /* 108969 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
39524 /* 108973 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39525 /* 108977 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39526 /* 108981 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39527 /* 108986 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39528 /* 108988 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
39529 /* 108988 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
39530 /* 108991 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39531 /* 108993 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
39532 /* 108997 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
39533 /* 108999 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39534 /* 109001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39535 /* 109004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39536 /* 109010 */ GIR_RootConstrainSelectedInstOperands,
39537 /* 109011 */ // GIR_Coverage, 2787,
39538 /* 109011 */ GIR_EraseRootFromParent_Done,
39539 /* 109012 */ // Label 3317: @109012
39540 /* 109012 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3318*/ GIMT_Encode4(109045), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2735 //
39541 /* 109019 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
39542 /* 109023 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
39543 /* 109023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS),
39544 /* 109026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
39545 /* 109028 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
39546 /* 109030 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
39547 /* 109032 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
39548 /* 109034 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39549 /* 109037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39550 /* 109043 */ GIR_RootConstrainSelectedInstOperands,
39551 /* 109044 */ // GIR_Coverage, 2735,
39552 /* 109044 */ GIR_EraseRootFromParent_Done,
39553 /* 109045 */ // Label 3318: @109045
39554 /* 109045 */ GIM_Reject,
39555 /* 109046 */ // Label 3316: @109046
39556 /* 109046 */ GIM_Reject,
39557 /* 109047 */ // Label 3314: @109047
39558 /* 109047 */ GIM_Reject,
39559 /* 109048 */ // Label 3310: @109048
39560 /* 109048 */ GIM_Reject,
39561 /* 109049 */ // Label 3295: @109049
39562 /* 109049 */ GIM_Try, /*On fail goto*//*Label 3319*/ GIMT_Encode4(109429),
39563 /* 109054 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
39564 /* 109057 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
39565 /* 109060 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
39566 /* 109063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39567 /* 109067 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3320*/ GIMT_Encode4(109140), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2771 //
39568 /* 109074 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39569 /* 109078 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39570 /* 109082 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
39571 /* 109086 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39572 /* 109091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39573 /* 109095 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
39574 /* 109099 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
39575 /* 109103 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
39576 /* 109107 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39577 /* 109112 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39578 /* 109114 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
39579 /* 109114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
39580 /* 109117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39581 /* 109119 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
39582 /* 109123 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
39583 /* 109127 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
39584 /* 109129 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39585 /* 109132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39586 /* 109138 */ GIR_RootConstrainSelectedInstOperands,
39587 /* 109139 */ // GIR_Coverage, 2771,
39588 /* 109139 */ GIR_EraseRootFromParent_Done,
39589 /* 109140 */ // Label 3320: @109140
39590 /* 109140 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3321*/ GIMT_Encode4(109213), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6336 //
39591 /* 109147 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39592 /* 109151 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39593 /* 109155 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39594 /* 109159 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
39595 /* 109163 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39596 /* 109168 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
39597 /* 109172 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
39598 /* 109176 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
39599 /* 109180 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39600 /* 109185 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
39601 /* 109187 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
39602 /* 109187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
39603 /* 109190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39604 /* 109192 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
39605 /* 109196 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
39606 /* 109200 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
39607 /* 109202 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39608 /* 109205 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39609 /* 109211 */ GIR_RootConstrainSelectedInstOperands,
39610 /* 109212 */ // GIR_Coverage, 6336,
39611 /* 109212 */ GIR_EraseRootFromParent_Done,
39612 /* 109213 */ // Label 3321: @109213
39613 /* 109213 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3322*/ GIMT_Encode4(109271), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2751 //
39614 /* 109220 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39615 /* 109224 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39616 /* 109228 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
39617 /* 109232 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39618 /* 109237 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39619 /* 109241 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39620 /* 109245 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39621 /* 109247 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
39622 /* 109247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
39623 /* 109250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39624 /* 109252 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
39625 /* 109254 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
39626 /* 109258 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
39627 /* 109260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39628 /* 109263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39629 /* 109269 */ GIR_RootConstrainSelectedInstOperands,
39630 /* 109270 */ // GIR_Coverage, 2751,
39631 /* 109270 */ GIR_EraseRootFromParent_Done,
39632 /* 109271 */ // Label 3322: @109271
39633 /* 109271 */ GIM_Try, /*On fail goto*//*Label 3323*/ GIMT_Encode4(109428),
39634 /* 109276 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39635 /* 109280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3324*/ GIMT_Encode4(109334), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6330 //
39636 /* 109287 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39637 /* 109291 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39638 /* 109295 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
39639 /* 109299 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39640 /* 109304 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39641 /* 109308 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39642 /* 109310 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
39643 /* 109310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
39644 /* 109313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39645 /* 109315 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
39646 /* 109317 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
39647 /* 109321 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
39648 /* 109323 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39649 /* 109326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39650 /* 109332 */ GIR_RootConstrainSelectedInstOperands,
39651 /* 109333 */ // GIR_Coverage, 6330,
39652 /* 109333 */ GIR_EraseRootFromParent_Done,
39653 /* 109334 */ // Label 3324: @109334
39654 /* 109334 */ GIM_Try, /*On fail goto*//*Label 3325*/ GIMT_Encode4(109427),
39655 /* 109339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39656 /* 109343 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3326*/ GIMT_Encode4(109393), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2785 //
39657 /* 109350 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
39658 /* 109354 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39659 /* 109358 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
39660 /* 109362 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39661 /* 109367 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39662 /* 109369 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
39663 /* 109369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
39664 /* 109372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39665 /* 109374 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin
39666 /* 109378 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
39667 /* 109380 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
39668 /* 109382 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39669 /* 109385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39670 /* 109391 */ GIR_RootConstrainSelectedInstOperands,
39671 /* 109392 */ // GIR_Coverage, 2785,
39672 /* 109392 */ GIR_EraseRootFromParent_Done,
39673 /* 109393 */ // Label 3326: @109393
39674 /* 109393 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3327*/ GIMT_Encode4(109426), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2733 //
39675 /* 109400 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39676 /* 109404 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
39677 /* 109404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD),
39678 /* 109407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
39679 /* 109409 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
39680 /* 109411 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
39681 /* 109413 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
39682 /* 109415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39683 /* 109418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39684 /* 109424 */ GIR_RootConstrainSelectedInstOperands,
39685 /* 109425 */ // GIR_Coverage, 2733,
39686 /* 109425 */ GIR_EraseRootFromParent_Done,
39687 /* 109426 */ // Label 3327: @109426
39688 /* 109426 */ GIM_Reject,
39689 /* 109427 */ // Label 3325: @109427
39690 /* 109427 */ GIM_Reject,
39691 /* 109428 */ // Label 3323: @109428
39692 /* 109428 */ GIM_Reject,
39693 /* 109429 */ // Label 3319: @109429
39694 /* 109429 */ GIM_Reject,
39695 /* 109430 */ // Label 3296: @109430
39696 /* 109430 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3328*/ GIMT_Encode4(109484), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 2886 //
39697 /* 109437 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
39698 /* 109440 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
39699 /* 109443 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
39700 /* 109446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39701 /* 109450 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39702 /* 109454 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39703 /* 109458 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39704 /* 109462 */ // (fma:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm, DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
39705 /* 109462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd),
39706 /* 109465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39707 /* 109467 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
39708 /* 109469 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39709 /* 109471 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39710 /* 109473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39711 /* 109476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39712 /* 109482 */ GIR_RootConstrainSelectedInstOperands,
39713 /* 109483 */ // GIR_Coverage, 2886,
39714 /* 109483 */ GIR_EraseRootFromParent_Done,
39715 /* 109484 */ // Label 3328: @109484
39716 /* 109484 */ GIM_Reject,
39717 /* 109485 */ // Label 3297: @109485
39718 /* 109485 */ GIM_Try, /*On fail goto*//*Label 3329*/ GIMT_Encode4(109734),
39719 /* 109490 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
39720 /* 109493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
39721 /* 109496 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
39722 /* 109499 */ GIM_Try, /*On fail goto*//*Label 3330*/ GIMT_Encode4(109637),
39723 /* 109504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39724 /* 109508 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3331*/ GIMT_Encode4(109572), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4449 //
39725 /* 109515 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39726 /* 109519 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39727 /* 109523 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
39728 /* 109527 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39729 /* 109532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39730 /* 109536 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39731 /* 109540 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39732 /* 109542 */ // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
39733 /* 109542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
39734 /* 109545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39735 /* 109547 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
39736 /* 109549 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
39737 /* 109553 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
39738 /* 109555 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39739 /* 109558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39740 /* 109564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39741 /* 109570 */ GIR_RootConstrainSelectedInstOperands,
39742 /* 109571 */ // GIR_Coverage, 4449,
39743 /* 109571 */ GIR_EraseRootFromParent_Done,
39744 /* 109572 */ // Label 3331: @109572
39745 /* 109572 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3332*/ GIMT_Encode4(109636), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 6676 //
39746 /* 109579 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39747 /* 109583 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39748 /* 109587 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39749 /* 109591 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
39750 /* 109595 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39751 /* 109600 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39752 /* 109604 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39753 /* 109606 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m2, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
39754 /* 109606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
39755 /* 109609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39756 /* 109611 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
39757 /* 109613 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
39758 /* 109617 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2
39759 /* 109619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39760 /* 109622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39761 /* 109628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39762 /* 109634 */ GIR_RootConstrainSelectedInstOperands,
39763 /* 109635 */ // GIR_Coverage, 6676,
39764 /* 109635 */ GIR_EraseRootFromParent_Done,
39765 /* 109636 */ // Label 3332: @109636
39766 /* 109636 */ GIM_Reject,
39767 /* 109637 */ // Label 3330: @109637
39768 /* 109637 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3333*/ GIMT_Encode4(109682), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 2887 //
39769 /* 109644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39770 /* 109648 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39771 /* 109652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39772 /* 109656 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39773 /* 109660 */ // (fma:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm, QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
39774 /* 109660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq),
39775 /* 109663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39776 /* 109665 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
39777 /* 109667 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39778 /* 109669 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39779 /* 109671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39780 /* 109674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39781 /* 109680 */ GIR_RootConstrainSelectedInstOperands,
39782 /* 109681 */ // GIR_Coverage, 2887,
39783 /* 109681 */ GIR_EraseRootFromParent_Done,
39784 /* 109682 */ // Label 3333: @109682
39785 /* 109682 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3334*/ GIMT_Encode4(109733), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4445 //
39786 /* 109689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39787 /* 109693 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39788 /* 109697 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39789 /* 109701 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39790 /* 109705 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
39791 /* 109705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16),
39792 /* 109708 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39793 /* 109710 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
39794 /* 109712 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1
39795 /* 109714 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
39796 /* 109716 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39797 /* 109719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39798 /* 109725 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39799 /* 109731 */ GIR_RootConstrainSelectedInstOperands,
39800 /* 109732 */ // GIR_Coverage, 4445,
39801 /* 109732 */ GIR_EraseRootFromParent_Done,
39802 /* 109733 */ // Label 3334: @109733
39803 /* 109733 */ GIM_Reject,
39804 /* 109734 */ // Label 3329: @109734
39805 /* 109734 */ GIM_Reject,
39806 /* 109735 */ // Label 3298: @109735
39807 /* 109735 */ GIM_Try, /*On fail goto*//*Label 3335*/ GIMT_Encode4(109913),
39808 /* 109740 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
39809 /* 109743 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
39810 /* 109746 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
39811 /* 109749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39812 /* 109753 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3336*/ GIMT_Encode4(109811), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2890 //
39813 /* 109760 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39814 /* 109764 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39815 /* 109768 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
39816 /* 109772 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39817 /* 109777 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39818 /* 109781 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39819 /* 109785 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39820 /* 109787 */ // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
39821 /* 109787 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd),
39822 /* 109790 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39823 /* 109792 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
39824 /* 109794 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
39825 /* 109798 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39826 /* 109800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39827 /* 109803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39828 /* 109809 */ GIR_RootConstrainSelectedInstOperands,
39829 /* 109810 */ // GIR_Coverage, 2890,
39830 /* 109810 */ GIR_EraseRootFromParent_Done,
39831 /* 109811 */ // Label 3336: @109811
39832 /* 109811 */ GIM_Try, /*On fail goto*//*Label 3337*/ GIMT_Encode4(109912),
39833 /* 109816 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39834 /* 109820 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3338*/ GIMT_Encode4(109874), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 6393 //
39835 /* 109827 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39836 /* 109831 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39837 /* 109835 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
39838 /* 109839 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39839 /* 109844 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39840 /* 109848 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39841 /* 109850 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm, (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
39842 /* 109850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd),
39843 /* 109853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39844 /* 109855 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
39845 /* 109857 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
39846 /* 109861 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
39847 /* 109863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39848 /* 109866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39849 /* 109872 */ GIR_RootConstrainSelectedInstOperands,
39850 /* 109873 */ // GIR_Coverage, 6393,
39851 /* 109873 */ GIR_EraseRootFromParent_Done,
39852 /* 109874 */ // Label 3338: @109874
39853 /* 109874 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3339*/ GIMT_Encode4(109911), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2888 //
39854 /* 109881 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39855 /* 109885 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39856 /* 109889 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMAfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
39857 /* 109889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfd),
39858 /* 109892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39859 /* 109894 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
39860 /* 109896 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39861 /* 109898 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39862 /* 109900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39863 /* 109903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39864 /* 109909 */ GIR_RootConstrainSelectedInstOperands,
39865 /* 109910 */ // GIR_Coverage, 2888,
39866 /* 109910 */ GIR_EraseRootFromParent_Done,
39867 /* 109911 */ // Label 3339: @109911
39868 /* 109911 */ GIM_Reject,
39869 /* 109912 */ // Label 3337: @109912
39870 /* 109912 */ GIM_Reject,
39871 /* 109913 */ // Label 3335: @109913
39872 /* 109913 */ GIM_Reject,
39873 /* 109914 */ // Label 3299: @109914
39874 /* 109914 */ GIM_Try, /*On fail goto*//*Label 3340*/ GIMT_Encode4(110285),
39875 /* 109919 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
39876 /* 109922 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
39877 /* 109925 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
39878 /* 109928 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3341*/ GIMT_Encode4(109990), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2891 //
39879 /* 109935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39880 /* 109939 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39881 /* 109943 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39882 /* 109947 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
39883 /* 109951 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39884 /* 109956 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39885 /* 109960 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39886 /* 109964 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39887 /* 109966 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
39888 /* 109966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq),
39889 /* 109969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39890 /* 109971 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
39891 /* 109973 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
39892 /* 109977 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39893 /* 109979 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39894 /* 109982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39895 /* 109988 */ GIR_RootConstrainSelectedInstOperands,
39896 /* 109989 */ // GIR_Coverage, 2891,
39897 /* 109989 */ GIR_EraseRootFromParent_Done,
39898 /* 109990 */ // Label 3341: @109990
39899 /* 109990 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3342*/ GIMT_Encode4(110058), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4435 //
39900 /* 109997 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39901 /* 110001 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39902 /* 110005 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39903 /* 110009 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
39904 /* 110013 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39905 /* 110018 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39906 /* 110022 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39907 /* 110026 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39908 /* 110028 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
39909 /* 110028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
39910 /* 110031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39911 /* 110033 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
39912 /* 110035 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
39913 /* 110039 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
39914 /* 110041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39915 /* 110044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39916 /* 110050 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39917 /* 110056 */ GIR_RootConstrainSelectedInstOperands,
39918 /* 110057 */ // GIR_Coverage, 4435,
39919 /* 110057 */ GIR_EraseRootFromParent_Done,
39920 /* 110058 */ // Label 3342: @110058
39921 /* 110058 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3343*/ GIMT_Encode4(110120), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 6394 //
39922 /* 110065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39923 /* 110069 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39924 /* 110073 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39925 /* 110077 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39926 /* 110081 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
39927 /* 110085 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39928 /* 110090 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39929 /* 110094 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39930 /* 110096 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm, (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
39931 /* 110096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq),
39932 /* 110099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39933 /* 110101 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
39934 /* 110103 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
39935 /* 110107 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
39936 /* 110109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39937 /* 110112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39938 /* 110118 */ GIR_RootConstrainSelectedInstOperands,
39939 /* 110119 */ // GIR_Coverage, 6394,
39940 /* 110119 */ GIR_EraseRootFromParent_Done,
39941 /* 110120 */ // Label 3343: @110120
39942 /* 110120 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3344*/ GIMT_Encode4(110188), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 6674 //
39943 /* 110127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39944 /* 110131 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39945 /* 110135 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39946 /* 110139 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
39947 /* 110143 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
39948 /* 110147 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39949 /* 110152 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39950 /* 110156 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39951 /* 110158 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m2, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
39952 /* 110158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
39953 /* 110161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39954 /* 110163 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
39955 /* 110165 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
39956 /* 110169 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2
39957 /* 110171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39958 /* 110174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39959 /* 110180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39960 /* 110186 */ GIR_RootConstrainSelectedInstOperands,
39961 /* 110187 */ // GIR_Coverage, 6674,
39962 /* 110187 */ GIR_EraseRootFromParent_Done,
39963 /* 110188 */ // Label 3344: @110188
39964 /* 110188 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3345*/ GIMT_Encode4(110233), GIMT_Encode2(GIFBS_HasNEON_HasVFP4), // Rule ID 2889 //
39965 /* 110195 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39966 /* 110199 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39967 /* 110203 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39968 /* 110207 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39969 /* 110211 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMAfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
39970 /* 110211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfq),
39971 /* 110214 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39972 /* 110216 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
39973 /* 110218 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39974 /* 110220 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39975 /* 110222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39976 /* 110225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39977 /* 110231 */ GIR_RootConstrainSelectedInstOperands,
39978 /* 110232 */ // GIR_Coverage, 2889,
39979 /* 110232 */ GIR_EraseRootFromParent_Done,
39980 /* 110233 */ // Label 3345: @110233
39981 /* 110233 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3346*/ GIMT_Encode4(110284), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4441 //
39982 /* 110240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39983 /* 110244 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39984 /* 110248 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39985 /* 110252 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39986 /* 110256 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
39987 /* 110256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32),
39988 /* 110259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39989 /* 110261 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
39990 /* 110263 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1
39991 /* 110265 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
39992 /* 110267 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39993 /* 110270 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39994 /* 110276 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39995 /* 110282 */ GIR_RootConstrainSelectedInstOperands,
39996 /* 110283 */ // GIR_Coverage, 4441,
39997 /* 110283 */ GIR_EraseRootFromParent_Done,
39998 /* 110284 */ // Label 3346: @110284
39999 /* 110284 */ GIM_Reject,
40000 /* 110285 */ // Label 3340: @110285
40001 /* 110285 */ GIM_Reject,
40002 /* 110286 */ // Label 3300: @110286
40003 /* 110286 */ GIM_Reject,
40004 /* 110287 */ // Label 44: @110287
40005 /* 110287 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3350*/ GIMT_Encode4(110448),
40006 /* 110298 */ /*GILLT_s16*//*Label 3347*/ GIMT_Encode4(110310),
40007 /* 110302 */ /*GILLT_s32*//*Label 3348*/ GIMT_Encode4(110356),
40008 /* 110306 */ /*GILLT_s64*//*Label 3349*/ GIMT_Encode4(110402),
40009 /* 110310 */ // Label 3347: @110310
40010 /* 110310 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3351*/ GIMT_Encode4(110355), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 633 //
40011 /* 110317 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
40012 /* 110320 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
40013 /* 110323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40014 /* 110327 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40015 /* 110331 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40016 /* 110335 */ // (fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40017 /* 110335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH),
40018 /* 110338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40019 /* 110340 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
40020 /* 110342 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
40021 /* 110344 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40022 /* 110347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40023 /* 110353 */ GIR_RootConstrainSelectedInstOperands,
40024 /* 110354 */ // GIR_Coverage, 633,
40025 /* 110354 */ GIR_EraseRootFromParent_Done,
40026 /* 110355 */ // Label 3351: @110355
40027 /* 110355 */ GIM_Reject,
40028 /* 110356 */ // Label 3348: @110356
40029 /* 110356 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3352*/ GIMT_Encode4(110401), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 631 //
40030 /* 110363 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
40031 /* 110366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
40032 /* 110369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40033 /* 110373 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40034 /* 110377 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40035 /* 110381 */ // (fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40036 /* 110381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS),
40037 /* 110384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40038 /* 110386 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
40039 /* 110388 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
40040 /* 110390 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40041 /* 110393 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40042 /* 110399 */ GIR_RootConstrainSelectedInstOperands,
40043 /* 110400 */ // GIR_Coverage, 631,
40044 /* 110400 */ GIR_EraseRootFromParent_Done,
40045 /* 110401 */ // Label 3352: @110401
40046 /* 110401 */ GIM_Reject,
40047 /* 110402 */ // Label 3349: @110402
40048 /* 110402 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3353*/ GIMT_Encode4(110447), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 629 //
40049 /* 110409 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
40050 /* 110412 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
40051 /* 110415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40052 /* 110419 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40053 /* 110423 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40054 /* 110427 */ // (fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40055 /* 110427 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD),
40056 /* 110430 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40057 /* 110432 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
40058 /* 110434 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
40059 /* 110436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40060 /* 110439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40061 /* 110445 */ GIR_RootConstrainSelectedInstOperands,
40062 /* 110446 */ // GIR_Coverage, 629,
40063 /* 110446 */ GIR_EraseRootFromParent_Done,
40064 /* 110447 */ // Label 3353: @110447
40065 /* 110447 */ GIM_Reject,
40066 /* 110448 */ // Label 3350: @110448
40067 /* 110448 */ GIM_Reject,
40068 /* 110449 */ // Label 45: @110449
40069 /* 110449 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3361*/ GIMT_Encode4(112856),
40070 /* 110460 */ /*GILLT_s16*//*Label 3354*/ GIMT_Encode4(110512),
40071 /* 110464 */ /*GILLT_s32*//*Label 3355*/ GIMT_Encode4(111153),
40072 /* 110468 */ /*GILLT_s64*//*Label 3356*/ GIMT_Encode4(111947), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
40073 /* 110496 */ /*GILLT_v4s16*//*Label 3357*/ GIMT_Encode4(112588),
40074 /* 110500 */ /*GILLT_v8s16*//*Label 3358*/ GIMT_Encode4(112625),
40075 /* 110504 */ /*GILLT_v2s32*//*Label 3359*/ GIMT_Encode4(112722),
40076 /* 110508 */ /*GILLT_v4s32*//*Label 3360*/ GIMT_Encode4(112759),
40077 /* 110512 */ // Label 3354: @110512
40078 /* 110512 */ GIM_Try, /*On fail goto*//*Label 3362*/ GIMT_Encode4(111152),
40079 /* 110517 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
40080 /* 110520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40081 /* 110524 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3363*/ GIMT_Encode4(110608), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2795 //
40082 /* 110531 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40083 /* 110535 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40084 /* 110539 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40085 /* 110543 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40086 /* 110547 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
40087 /* 110551 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
40088 /* 110555 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40089 /* 110559 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
40090 /* 110563 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40091 /* 110568 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40092 /* 110573 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40093 /* 110578 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40094 /* 110580 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40095 /* 110580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
40096 /* 110583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40097 /* 110585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40098 /* 110589 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40099 /* 110593 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40100 /* 110597 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40101 /* 110600 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40102 /* 110606 */ GIR_RootConstrainSelectedInstOperands,
40103 /* 110607 */ // GIR_Coverage, 2795,
40104 /* 110607 */ GIR_EraseRootFromParent_Done,
40105 /* 110608 */ // Label 3363: @110608
40106 /* 110608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3364*/ GIMT_Encode4(110692), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6346 //
40107 /* 110615 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40108 /* 110619 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40109 /* 110623 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40110 /* 110627 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40111 /* 110631 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
40112 /* 110635 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40113 /* 110640 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
40114 /* 110644 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40115 /* 110648 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
40116 /* 110652 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40117 /* 110657 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40118 /* 110662 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40119 /* 110664 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40120 /* 110664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
40121 /* 110667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40122 /* 110669 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40123 /* 110673 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40124 /* 110677 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
40125 /* 110681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40126 /* 110684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40127 /* 110690 */ GIR_RootConstrainSelectedInstOperands,
40128 /* 110691 */ // GIR_Coverage, 6346,
40129 /* 110691 */ GIR_EraseRootFromParent_Done,
40130 /* 110692 */ // Label 3364: @110692
40131 /* 110692 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3365*/ GIMT_Encode4(110776), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2794 //
40132 /* 110699 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40133 /* 110703 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40134 /* 110707 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40135 /* 110711 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40136 /* 110715 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
40137 /* 110719 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
40138 /* 110723 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40139 /* 110727 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
40140 /* 110731 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40141 /* 110736 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40142 /* 110741 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40143 /* 110746 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40144 /* 110748 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40145 /* 110748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
40146 /* 110751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40147 /* 110753 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40148 /* 110757 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40149 /* 110761 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40150 /* 110765 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40151 /* 110768 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40152 /* 110774 */ GIR_RootConstrainSelectedInstOperands,
40153 /* 110775 */ // GIR_Coverage, 2794,
40154 /* 110775 */ GIR_EraseRootFromParent_Done,
40155 /* 110776 */ // Label 3365: @110776
40156 /* 110776 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3366*/ GIMT_Encode4(110860), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6345 //
40157 /* 110783 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40158 /* 110787 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40159 /* 110791 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40160 /* 110795 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40161 /* 110799 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
40162 /* 110803 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40163 /* 110808 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
40164 /* 110812 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40165 /* 110816 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
40166 /* 110820 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40167 /* 110825 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40168 /* 110830 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40169 /* 110832 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40170 /* 110832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
40171 /* 110835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40172 /* 110837 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40173 /* 110841 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40174 /* 110845 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
40175 /* 110849 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40176 /* 110852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40177 /* 110858 */ GIR_RootConstrainSelectedInstOperands,
40178 /* 110859 */ // GIR_Coverage, 6345,
40179 /* 110859 */ GIR_EraseRootFromParent_Done,
40180 /* 110860 */ // Label 3366: @110860
40181 /* 110860 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3367*/ GIMT_Encode4(110932), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2769 //
40182 /* 110867 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40183 /* 110871 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40184 /* 110875 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40185 /* 110879 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40186 /* 110883 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
40187 /* 110887 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40188 /* 110892 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40189 /* 110897 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40190 /* 110902 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40191 /* 110904 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40192 /* 110904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
40193 /* 110907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40194 /* 110909 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40195 /* 110913 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40196 /* 110917 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40197 /* 110921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40198 /* 110924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40199 /* 110930 */ GIR_RootConstrainSelectedInstOperands,
40200 /* 110931 */ // GIR_Coverage, 2769,
40201 /* 110931 */ GIR_EraseRootFromParent_Done,
40202 /* 110932 */ // Label 3367: @110932
40203 /* 110932 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3368*/ GIMT_Encode4(111004), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2768 //
40204 /* 110939 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40205 /* 110943 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40206 /* 110947 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40207 /* 110951 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40208 /* 110955 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
40209 /* 110959 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40210 /* 110964 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40211 /* 110969 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40212 /* 110974 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40213 /* 110976 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40214 /* 110976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
40215 /* 110979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40216 /* 110981 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40217 /* 110985 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40218 /* 110989 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40219 /* 110993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40220 /* 110996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40221 /* 111002 */ GIR_RootConstrainSelectedInstOperands,
40222 /* 111003 */ // GIR_Coverage, 2768,
40223 /* 111003 */ GIR_EraseRootFromParent_Done,
40224 /* 111004 */ // Label 3368: @111004
40225 /* 111004 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3369*/ GIMT_Encode4(111063), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 645 //
40226 /* 111011 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40227 /* 111015 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
40228 /* 111019 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40229 /* 111023 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40230 /* 111027 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40231 /* 111032 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40232 /* 111037 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40233 /* 111039 */ // (fneg:{ *:[f16] } (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40234 /* 111039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH),
40235 /* 111042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40236 /* 111044 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40237 /* 111048 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40238 /* 111052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40239 /* 111055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40240 /* 111061 */ GIR_RootConstrainSelectedInstOperands,
40241 /* 111062 */ // GIR_Coverage, 645,
40242 /* 111062 */ GIR_EraseRootFromParent_Done,
40243 /* 111063 */ // Label 3369: @111063
40244 /* 111063 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3370*/ GIMT_Encode4(111122), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 644 //
40245 /* 111070 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40246 /* 111074 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
40247 /* 111078 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
40248 /* 111082 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
40249 /* 111086 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40250 /* 111091 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40251 /* 111096 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40252 /* 111098 */ // (fneg:{ *:[f16] } (strict_fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
40253 /* 111098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH),
40254 /* 111101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40255 /* 111103 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40256 /* 111107 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40257 /* 111111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40258 /* 111114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40259 /* 111120 */ GIR_RootConstrainSelectedInstOperands,
40260 /* 111121 */ // GIR_Coverage, 644,
40261 /* 111121 */ GIR_EraseRootFromParent_Done,
40262 /* 111122 */ // Label 3370: @111122
40263 /* 111122 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3371*/ GIMT_Encode4(111151), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 691 //
40264 /* 111129 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40265 /* 111133 */ // (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VNEGH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
40266 /* 111133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGH),
40267 /* 111136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40268 /* 111138 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
40269 /* 111140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40270 /* 111143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40271 /* 111149 */ GIR_RootConstrainSelectedInstOperands,
40272 /* 111150 */ // GIR_Coverage, 691,
40273 /* 111150 */ GIR_EraseRootFromParent_Done,
40274 /* 111151 */ // Label 3371: @111151
40275 /* 111151 */ GIM_Reject,
40276 /* 111152 */ // Label 3362: @111152
40277 /* 111152 */ GIM_Reject,
40278 /* 111153 */ // Label 3355: @111153
40279 /* 111153 */ GIM_Try, /*On fail goto*//*Label 3372*/ GIMT_Encode4(111946),
40280 /* 111158 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
40281 /* 111161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40282 /* 111165 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3373*/ GIMT_Encode4(111249), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2793 //
40283 /* 111172 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40284 /* 111176 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40285 /* 111180 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40286 /* 111184 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40287 /* 111188 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40288 /* 111192 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
40289 /* 111196 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40290 /* 111200 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
40291 /* 111204 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40292 /* 111209 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40293 /* 111214 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40294 /* 111219 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40295 /* 111221 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40296 /* 111221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
40297 /* 111224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40298 /* 111226 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40299 /* 111230 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40300 /* 111234 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40301 /* 111238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40302 /* 111241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40303 /* 111247 */ GIR_RootConstrainSelectedInstOperands,
40304 /* 111248 */ // GIR_Coverage, 2793,
40305 /* 111248 */ GIR_EraseRootFromParent_Done,
40306 /* 111249 */ // Label 3373: @111249
40307 /* 111249 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3374*/ GIMT_Encode4(111333), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6344 //
40308 /* 111256 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40309 /* 111260 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40310 /* 111264 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40311 /* 111268 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40312 /* 111272 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40313 /* 111276 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40314 /* 111281 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
40315 /* 111285 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40316 /* 111289 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
40317 /* 111293 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40318 /* 111298 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40319 /* 111303 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40320 /* 111305 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40321 /* 111305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
40322 /* 111308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40323 /* 111310 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40324 /* 111314 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40325 /* 111318 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
40326 /* 111322 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40327 /* 111325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40328 /* 111331 */ GIR_RootConstrainSelectedInstOperands,
40329 /* 111332 */ // GIR_Coverage, 6344,
40330 /* 111332 */ GIR_EraseRootFromParent_Done,
40331 /* 111333 */ // Label 3374: @111333
40332 /* 111333 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3375*/ GIMT_Encode4(111417), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2792 //
40333 /* 111340 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40334 /* 111344 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40335 /* 111348 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40336 /* 111352 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40337 /* 111356 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40338 /* 111360 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
40339 /* 111364 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40340 /* 111368 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
40341 /* 111372 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40342 /* 111377 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40343 /* 111382 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40344 /* 111387 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40345 /* 111389 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40346 /* 111389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
40347 /* 111392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40348 /* 111394 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40349 /* 111398 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40350 /* 111402 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40351 /* 111406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40352 /* 111409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40353 /* 111415 */ GIR_RootConstrainSelectedInstOperands,
40354 /* 111416 */ // GIR_Coverage, 2792,
40355 /* 111416 */ GIR_EraseRootFromParent_Done,
40356 /* 111417 */ // Label 3375: @111417
40357 /* 111417 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3376*/ GIMT_Encode4(111501), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6343 //
40358 /* 111424 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40359 /* 111428 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40360 /* 111432 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40361 /* 111436 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40362 /* 111440 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40363 /* 111444 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40364 /* 111449 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
40365 /* 111453 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40366 /* 111457 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
40367 /* 111461 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40368 /* 111466 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40369 /* 111471 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40370 /* 111473 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40371 /* 111473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
40372 /* 111476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40373 /* 111478 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40374 /* 111482 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
40375 /* 111486 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
40376 /* 111490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40377 /* 111493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40378 /* 111499 */ GIR_RootConstrainSelectedInstOperands,
40379 /* 111500 */ // GIR_Coverage, 6343,
40380 /* 111500 */ GIR_EraseRootFromParent_Done,
40381 /* 111501 */ // Label 3376: @111501
40382 /* 111501 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3377*/ GIMT_Encode4(111573), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2767 //
40383 /* 111508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40384 /* 111512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40385 /* 111516 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40386 /* 111520 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40387 /* 111524 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40388 /* 111528 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40389 /* 111533 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40390 /* 111538 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40391 /* 111543 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40392 /* 111545 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40393 /* 111545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
40394 /* 111548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40395 /* 111550 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40396 /* 111554 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40397 /* 111558 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40398 /* 111562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40399 /* 111565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40400 /* 111571 */ GIR_RootConstrainSelectedInstOperands,
40401 /* 111572 */ // GIR_Coverage, 2767,
40402 /* 111572 */ GIR_EraseRootFromParent_Done,
40403 /* 111573 */ // Label 3377: @111573
40404 /* 111573 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3378*/ GIMT_Encode4(111645), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2766 //
40405 /* 111580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40406 /* 111584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40407 /* 111588 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40408 /* 111592 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40409 /* 111596 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
40410 /* 111600 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40411 /* 111605 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40412 /* 111610 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40413 /* 111615 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40414 /* 111617 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40415 /* 111617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
40416 /* 111620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40417 /* 111622 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
40418 /* 111626 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40419 /* 111630 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40420 /* 111634 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40421 /* 111637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40422 /* 111643 */ GIR_RootConstrainSelectedInstOperands,
40423 /* 111644 */ // GIR_Coverage, 2766,
40424 /* 111644 */ GIR_EraseRootFromParent_Done,
40425 /* 111645 */ // Label 3378: @111645
40426 /* 111645 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3379*/ GIMT_Encode4(111704), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 643 //
40427 /* 111652 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40428 /* 111656 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
40429 /* 111660 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40430 /* 111664 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40431 /* 111668 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40432 /* 111673 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40433 /* 111678 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40434 /* 111680 */ // (fneg:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40435 /* 111680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
40436 /* 111683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40437 /* 111685 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40438 /* 111689 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40439 /* 111693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40440 /* 111696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40441 /* 111702 */ GIR_RootConstrainSelectedInstOperands,
40442 /* 111703 */ // GIR_Coverage, 643,
40443 /* 111703 */ GIR_EraseRootFromParent_Done,
40444 /* 111704 */ // Label 3379: @111704
40445 /* 111704 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3380*/ GIMT_Encode4(111763), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 642 //
40446 /* 111711 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40447 /* 111715 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
40448 /* 111719 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40449 /* 111723 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
40450 /* 111727 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40451 /* 111732 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40452 /* 111737 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40453 /* 111739 */ // (fneg:{ *:[f32] } (strict_fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
40454 /* 111739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
40455 /* 111742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40456 /* 111744 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
40457 /* 111748 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
40458 /* 111752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40459 /* 111755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40460 /* 111761 */ GIR_RootConstrainSelectedInstOperands,
40461 /* 111762 */ // GIR_Coverage, 642,
40462 /* 111762 */ GIR_EraseRootFromParent_Done,
40463 /* 111763 */ // Label 3380: @111763
40464 /* 111763 */ GIM_Try, /*On fail goto*//*Label 3381*/ GIMT_Encode4(111945),
40465 /* 111768 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40466 /* 111772 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3382*/ GIMT_Encode4(111797), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 690 //
40467 /* 111779 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VNEGS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
40468 /* 111779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGS),
40469 /* 111782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40470 /* 111784 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
40471 /* 111786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40472 /* 111789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40473 /* 111795 */ GIR_RootConstrainSelectedInstOperands,
40474 /* 111796 */ // GIR_Coverage, 690,
40475 /* 111796 */ GIR_EraseRootFromParent_Done,
40476 /* 111797 */ // Label 3382: @111797
40477 /* 111797 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3383*/ GIMT_Encode4(111944), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3094 //
40478 /* 111804 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VNEGfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
40479 /* 111804 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
40480 /* 111807 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40481 /* 111811 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40482 /* 111816 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
40483 /* 111818 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
40484 /* 111821 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40485 /* 111825 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40486 /* 111830 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
40487 /* 111833 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40488 /* 111838 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
40489 /* 111841 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
40490 /* 111845 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40491 /* 111850 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
40492 /* 111853 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
40493 /* 111857 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
40494 /* 111860 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40495 /* 111865 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40496 /* 111870 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
40497 /* 111875 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
40498 /* 111878 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VNEGfd),
40499 /* 111882 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40500 /* 111887 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
40501 /* 111890 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
40502 /* 111893 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40503 /* 111899 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40504 /* 111901 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
40505 /* 111904 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40506 /* 111908 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40507 /* 111913 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
40508 /* 111916 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40509 /* 111921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40510 /* 111924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40511 /* 111926 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
40512 /* 111933 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
40513 /* 111938 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
40514 /* 111943 */ // GIR_Coverage, 3094,
40515 /* 111943 */ GIR_EraseRootFromParent_Done,
40516 /* 111944 */ // Label 3383: @111944
40517 /* 111944 */ GIM_Reject,
40518 /* 111945 */ // Label 3381: @111945
40519 /* 111945 */ GIM_Reject,
40520 /* 111946 */ // Label 3372: @111946
40521 /* 111946 */ GIM_Reject,
40522 /* 111947 */ // Label 3356: @111947
40523 /* 111947 */ GIM_Try, /*On fail goto*//*Label 3384*/ GIMT_Encode4(112587),
40524 /* 111952 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
40525 /* 111955 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40526 /* 111959 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3385*/ GIMT_Encode4(112043), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2791 //
40527 /* 111966 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40528 /* 111970 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40529 /* 111974 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40530 /* 111978 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40531 /* 111982 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40532 /* 111986 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
40533 /* 111990 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40534 /* 111994 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
40535 /* 111998 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40536 /* 112003 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40537 /* 112008 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40538 /* 112013 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40539 /* 112015 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40540 /* 112015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
40541 /* 112018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40542 /* 112020 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
40543 /* 112024 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
40544 /* 112028 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
40545 /* 112032 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40546 /* 112035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40547 /* 112041 */ GIR_RootConstrainSelectedInstOperands,
40548 /* 112042 */ // GIR_Coverage, 2791,
40549 /* 112042 */ GIR_EraseRootFromParent_Done,
40550 /* 112043 */ // Label 3385: @112043
40551 /* 112043 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3386*/ GIMT_Encode4(112127), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6342 //
40552 /* 112050 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40553 /* 112054 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40554 /* 112058 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40555 /* 112062 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40556 /* 112066 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40557 /* 112070 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40558 /* 112075 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
40559 /* 112079 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40560 /* 112083 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
40561 /* 112087 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40562 /* 112092 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40563 /* 112097 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40564 /* 112099 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40565 /* 112099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
40566 /* 112102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40567 /* 112104 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
40568 /* 112108 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
40569 /* 112112 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm
40570 /* 112116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40571 /* 112119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40572 /* 112125 */ GIR_RootConstrainSelectedInstOperands,
40573 /* 112126 */ // GIR_Coverage, 6342,
40574 /* 112126 */ GIR_EraseRootFromParent_Done,
40575 /* 112127 */ // Label 3386: @112127
40576 /* 112127 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3387*/ GIMT_Encode4(112211), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2790 //
40577 /* 112134 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40578 /* 112138 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40579 /* 112142 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40580 /* 112146 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40581 /* 112150 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40582 /* 112154 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
40583 /* 112158 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40584 /* 112162 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
40585 /* 112166 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40586 /* 112171 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40587 /* 112176 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40588 /* 112181 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40589 /* 112183 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40590 /* 112183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
40591 /* 112186 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40592 /* 112188 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
40593 /* 112192 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
40594 /* 112196 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
40595 /* 112200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40596 /* 112203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40597 /* 112209 */ GIR_RootConstrainSelectedInstOperands,
40598 /* 112210 */ // GIR_Coverage, 2790,
40599 /* 112210 */ GIR_EraseRootFromParent_Done,
40600 /* 112211 */ // Label 3387: @112211
40601 /* 112211 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3388*/ GIMT_Encode4(112295), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6341 //
40602 /* 112218 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40603 /* 112222 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40604 /* 112226 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40605 /* 112230 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40606 /* 112234 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40607 /* 112238 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40608 /* 112243 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
40609 /* 112247 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
40610 /* 112251 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
40611 /* 112255 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40612 /* 112260 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40613 /* 112265 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
40614 /* 112267 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40615 /* 112267 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
40616 /* 112270 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40617 /* 112272 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
40618 /* 112276 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
40619 /* 112280 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm
40620 /* 112284 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40621 /* 112287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40622 /* 112293 */ GIR_RootConstrainSelectedInstOperands,
40623 /* 112294 */ // GIR_Coverage, 6341,
40624 /* 112294 */ GIR_EraseRootFromParent_Done,
40625 /* 112295 */ // Label 3388: @112295
40626 /* 112295 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3389*/ GIMT_Encode4(112367), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2765 //
40627 /* 112302 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40628 /* 112306 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
40629 /* 112310 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40630 /* 112314 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40631 /* 112318 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40632 /* 112322 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40633 /* 112327 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40634 /* 112332 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40635 /* 112337 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40636 /* 112339 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40637 /* 112339 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
40638 /* 112342 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40639 /* 112344 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
40640 /* 112348 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
40641 /* 112352 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
40642 /* 112356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40643 /* 112359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40644 /* 112365 */ GIR_RootConstrainSelectedInstOperands,
40645 /* 112366 */ // GIR_Coverage, 2765,
40646 /* 112366 */ GIR_EraseRootFromParent_Done,
40647 /* 112367 */ // Label 3389: @112367
40648 /* 112367 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3390*/ GIMT_Encode4(112439), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2764 //
40649 /* 112374 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40650 /* 112378 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
40651 /* 112382 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40652 /* 112386 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40653 /* 112390 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
40654 /* 112394 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40655 /* 112399 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40656 /* 112404 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40657 /* 112409 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40658 /* 112411 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40659 /* 112411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
40660 /* 112414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40661 /* 112416 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
40662 /* 112420 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
40663 /* 112424 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
40664 /* 112428 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40665 /* 112431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40666 /* 112437 */ GIR_RootConstrainSelectedInstOperands,
40667 /* 112438 */ // GIR_Coverage, 2764,
40668 /* 112438 */ GIR_EraseRootFromParent_Done,
40669 /* 112439 */ // Label 3390: @112439
40670 /* 112439 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3391*/ GIMT_Encode4(112498), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 641 //
40671 /* 112446 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40672 /* 112450 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
40673 /* 112454 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40674 /* 112458 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40675 /* 112462 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40676 /* 112467 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40677 /* 112472 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40678 /* 112474 */ // (fneg:{ *:[f64] } (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40679 /* 112474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
40680 /* 112477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40681 /* 112479 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
40682 /* 112483 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
40683 /* 112487 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40684 /* 112490 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40685 /* 112496 */ GIR_RootConstrainSelectedInstOperands,
40686 /* 112497 */ // GIR_Coverage, 641,
40687 /* 112497 */ GIR_EraseRootFromParent_Done,
40688 /* 112498 */ // Label 3391: @112498
40689 /* 112498 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3392*/ GIMT_Encode4(112557), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 640 //
40690 /* 112505 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40691 /* 112509 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
40692 /* 112513 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
40693 /* 112517 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
40694 /* 112521 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40695 /* 112526 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40696 /* 112531 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40697 /* 112533 */ // (fneg:{ *:[f64] } (strict_fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
40698 /* 112533 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
40699 /* 112536 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40700 /* 112538 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
40701 /* 112542 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
40702 /* 112546 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40703 /* 112549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40704 /* 112555 */ GIR_RootConstrainSelectedInstOperands,
40705 /* 112556 */ // GIR_Coverage, 640,
40706 /* 112556 */ GIR_EraseRootFromParent_Done,
40707 /* 112557 */ // Label 3392: @112557
40708 /* 112557 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3393*/ GIMT_Encode4(112586), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 689 //
40709 /* 112564 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40710 /* 112568 */ // (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VNEGD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
40711 /* 112568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGD),
40712 /* 112571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40713 /* 112573 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
40714 /* 112575 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40715 /* 112578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40716 /* 112584 */ GIR_RootConstrainSelectedInstOperands,
40717 /* 112585 */ // GIR_Coverage, 689,
40718 /* 112585 */ GIR_EraseRootFromParent_Done,
40719 /* 112586 */ // Label 3393: @112586
40720 /* 112586 */ GIM_Reject,
40721 /* 112587 */ // Label 3384: @112587
40722 /* 112587 */ GIM_Reject,
40723 /* 112588 */ // Label 3357: @112588
40724 /* 112588 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3394*/ GIMT_Encode4(112624), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1694 //
40725 /* 112595 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
40726 /* 112598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40727 /* 112602 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40728 /* 112606 */ // (fneg:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VNEGhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
40729 /* 112606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhd),
40730 /* 112609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40731 /* 112611 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
40732 /* 112613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40733 /* 112616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40734 /* 112622 */ GIR_RootConstrainSelectedInstOperands,
40735 /* 112623 */ // GIR_Coverage, 1694,
40736 /* 112623 */ GIR_EraseRootFromParent_Done,
40737 /* 112624 */ // Label 3394: @112624
40738 /* 112624 */ GIM_Reject,
40739 /* 112625 */ // Label 3358: @112625
40740 /* 112625 */ GIM_Try, /*On fail goto*//*Label 3395*/ GIMT_Encode4(112721),
40741 /* 112630 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
40742 /* 112633 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3396*/ GIMT_Encode4(112666), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1695 //
40743 /* 112640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40744 /* 112644 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40745 /* 112648 */ // (fneg:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VNEGhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
40746 /* 112648 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhq),
40747 /* 112651 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40748 /* 112653 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
40749 /* 112655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40750 /* 112658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40751 /* 112664 */ GIR_RootConstrainSelectedInstOperands,
40752 /* 112665 */ // GIR_Coverage, 1695,
40753 /* 112665 */ GIR_EraseRootFromParent_Done,
40754 /* 112666 */ // Label 3396: @112666
40755 /* 112666 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3397*/ GIMT_Encode4(112720), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4573 //
40756 /* 112673 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40757 /* 112677 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40758 /* 112681 */ // (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VNEGf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v)
40759 /* 112681 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40760 /* 112684 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40761 /* 112688 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40762 /* 112693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf16),
40763 /* 112696 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40764 /* 112698 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
40765 /* 112700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40766 /* 112703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40767 /* 112709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40768 /* 112715 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40769 /* 112718 */ GIR_RootConstrainSelectedInstOperands,
40770 /* 112719 */ // GIR_Coverage, 4573,
40771 /* 112719 */ GIR_EraseRootFromParent_Done,
40772 /* 112720 */ // Label 3397: @112720
40773 /* 112720 */ GIM_Reject,
40774 /* 112721 */ // Label 3395: @112721
40775 /* 112721 */ GIM_Reject,
40776 /* 112722 */ // Label 3359: @112722
40777 /* 112722 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3398*/ GIMT_Encode4(112758), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1692 //
40778 /* 112729 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
40779 /* 112732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40780 /* 112736 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40781 /* 112740 */ // (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VNEGfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
40782 /* 112740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGfd),
40783 /* 112743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40784 /* 112745 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
40785 /* 112747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40786 /* 112750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40787 /* 112756 */ GIR_RootConstrainSelectedInstOperands,
40788 /* 112757 */ // GIR_Coverage, 1692,
40789 /* 112757 */ GIR_EraseRootFromParent_Done,
40790 /* 112758 */ // Label 3398: @112758
40791 /* 112758 */ GIM_Reject,
40792 /* 112759 */ // Label 3360: @112759
40793 /* 112759 */ GIM_Try, /*On fail goto*//*Label 3399*/ GIMT_Encode4(112855),
40794 /* 112764 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
40795 /* 112767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3400*/ GIMT_Encode4(112800), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1693 //
40796 /* 112774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40797 /* 112778 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40798 /* 112782 */ // (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VNEGf32q:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
40799 /* 112782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGf32q),
40800 /* 112785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40801 /* 112787 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
40802 /* 112789 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40803 /* 112792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40804 /* 112798 */ GIR_RootConstrainSelectedInstOperands,
40805 /* 112799 */ // GIR_Coverage, 1693,
40806 /* 112799 */ GIR_EraseRootFromParent_Done,
40807 /* 112800 */ // Label 3400: @112800
40808 /* 112800 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3401*/ GIMT_Encode4(112854), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4575 //
40809 /* 112807 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40810 /* 112811 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40811 /* 112815 */ // (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VNEGf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v)
40812 /* 112815 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40813 /* 112818 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40814 /* 112822 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40815 /* 112827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf32),
40816 /* 112830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40817 /* 112832 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
40818 /* 112834 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40819 /* 112837 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40820 /* 112843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40821 /* 112849 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40822 /* 112852 */ GIR_RootConstrainSelectedInstOperands,
40823 /* 112853 */ // GIR_Coverage, 4575,
40824 /* 112853 */ GIR_EraseRootFromParent_Done,
40825 /* 112854 */ // Label 3401: @112854
40826 /* 112854 */ GIM_Reject,
40827 /* 112855 */ // Label 3399: @112855
40828 /* 112855 */ GIM_Reject,
40829 /* 112856 */ // Label 3361: @112856
40830 /* 112856 */ GIM_Reject,
40831 /* 112857 */ // Label 46: @112857
40832 /* 112857 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3405*/ GIMT_Encode4(113120),
40833 /* 112868 */ /*GILLT_s32*//*Label 3402*/ GIMT_Encode4(112916),
40834 /* 112872 */ /*GILLT_s64*//*Label 3403*/ GIMT_Encode4(112975), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
40835 /* 112912 */ /*GILLT_v4s32*//*Label 3404*/ GIMT_Encode4(113085),
40836 /* 112916 */ // Label 3402: @112916
40837 /* 112916 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3406*/ GIMT_Encode4(112974), GIMT_Encode2(GIFBS_HasFP16), // Rule ID 2504 //
40838 /* 112923 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
40839 /* 112926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40840 /* 112930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40841 /* 112934 */ // (fpextend:{ *:[f32] } HPR:{ *:[f16] }:$Sm) => (VCVTBHS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
40842 /* 112934 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
40843 /* 112937 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40844 /* 112941 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40845 /* 112946 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
40846 /* 112950 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
40847 /* 112955 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHS),
40848 /* 112958 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40849 /* 112960 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40850 /* 112963 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40851 /* 112966 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40852 /* 112972 */ GIR_RootConstrainSelectedInstOperands,
40853 /* 112973 */ // GIR_Coverage, 2504,
40854 /* 112973 */ GIR_EraseRootFromParent_Done,
40855 /* 112974 */ // Label 3406: @112974
40856 /* 112974 */ GIM_Reject,
40857 /* 112975 */ // Label 3403: @112975
40858 /* 112975 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(2), /*)*//*default:*//*Label 3409*/ GIMT_Encode4(113084),
40859 /* 112986 */ /*GILLT_s16*//*Label 3407*/ GIMT_Encode4(112994),
40860 /* 112990 */ /*GILLT_s32*//*Label 3408*/ GIMT_Encode4(113050),
40861 /* 112994 */ // Label 3407: @112994
40862 /* 112994 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3410*/ GIMT_Encode4(113049), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2524 //
40863 /* 113001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40864 /* 113005 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40865 /* 113009 */ // (fpextend:{ *:[f64] } HPR:{ *:[f16] }:$Sm) => (VCVTBHD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
40866 /* 113009 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
40867 /* 113012 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40868 /* 113016 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40869 /* 113021 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
40870 /* 113025 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
40871 /* 113030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHD),
40872 /* 113033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40873 /* 113035 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40874 /* 113038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40875 /* 113041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40876 /* 113047 */ GIR_RootConstrainSelectedInstOperands,
40877 /* 113048 */ // GIR_Coverage, 2524,
40878 /* 113048 */ GIR_EraseRootFromParent_Done,
40879 /* 113049 */ // Label 3410: @113049
40880 /* 113049 */ GIM_Reject,
40881 /* 113050 */ // Label 3408: @113050
40882 /* 113050 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3411*/ GIMT_Encode4(113083), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 686 //
40883 /* 113057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40884 /* 113061 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40885 /* 113065 */ // (fpextend:{ *:[f64] } SPR:{ *:[f32] }:$Sm) => (VCVTDS:{ *:[f64] } SPR:{ *:[f32] }:$Sm)
40886 /* 113065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTDS),
40887 /* 113068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
40888 /* 113070 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
40889 /* 113072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40890 /* 113075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40891 /* 113081 */ GIR_RootConstrainSelectedInstOperands,
40892 /* 113082 */ // GIR_Coverage, 686,
40893 /* 113082 */ GIR_EraseRootFromParent_Done,
40894 /* 113083 */ // Label 3411: @113083
40895 /* 113083 */ GIM_Reject,
40896 /* 113084 */ // Label 3409: @113084
40897 /* 113084 */ GIM_Reject,
40898 /* 113085 */ // Label 3404: @113085
40899 /* 113085 */ GIM_Try, /*On fail goto*//*Label 3412*/ GIMT_Encode4(113119), // Rule ID 3059 //
40900 /* 113090 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
40901 /* 113093 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40902 /* 113097 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40903 /* 113101 */ // (fpextend:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src)
40904 /* 113101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f),
40905 /* 113104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40906 /* 113106 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
40907 /* 113108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40908 /* 113111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40909 /* 113117 */ GIR_RootConstrainSelectedInstOperands,
40910 /* 113118 */ // GIR_Coverage, 3059,
40911 /* 113118 */ GIR_EraseRootFromParent_Done,
40912 /* 113119 */ // Label 3412: @113119
40913 /* 113119 */ GIM_Reject,
40914 /* 113120 */ // Label 3405: @113120
40915 /* 113120 */ GIM_Reject,
40916 /* 113121 */ // Label 47: @113121
40917 /* 113121 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(10), /*)*//*default:*//*Label 3416*/ GIMT_Encode4(113412),
40918 /* 113132 */ /*GILLT_s16*//*Label 3413*/ GIMT_Encode4(113172),
40919 /* 113136 */ /*GILLT_s32*//*Label 3414*/ GIMT_Encode4(113340), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
40920 /* 113168 */ /*GILLT_v4s16*//*Label 3415*/ GIMT_Encode4(113377),
40921 /* 113172 */ // Label 3413: @113172
40922 /* 113172 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 3419*/ GIMT_Encode4(113339),
40923 /* 113183 */ /*GILLT_s32*//*Label 3417*/ GIMT_Encode4(113191),
40924 /* 113187 */ /*GILLT_s64*//*Label 3418*/ GIMT_Encode4(113265),
40925 /* 113191 */ // Label 3417: @113191
40926 /* 113191 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3420*/ GIMT_Encode4(113264), GIMT_Encode2(GIFBS_HasFP16), // Rule ID 2508 //
40927 /* 113198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40928 /* 113202 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40929 /* 113206 */ // (fpround:{ *:[f16] } SPR:{ *:[f32] }:$Sm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBSH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), SPR:{ *:[f32] }:$Sm), HPR:{ *:[i32] })
40930 /* 113206 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40931 /* 113209 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40932 /* 113213 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40933 /* 113218 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40934 /* 113220 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
40935 /* 113223 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBSH),
40936 /* 113227 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40937 /* 113232 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
40938 /* 113235 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
40939 /* 113239 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
40940 /* 113242 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40941 /* 113248 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40942 /* 113250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40943 /* 113253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40944 /* 113255 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40945 /* 113258 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
40946 /* 113263 */ // GIR_Coverage, 2508,
40947 /* 113263 */ GIR_EraseRootFromParent_Done,
40948 /* 113264 */ // Label 3420: @113264
40949 /* 113264 */ GIM_Reject,
40950 /* 113265 */ // Label 3418: @113265
40951 /* 113265 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3421*/ GIMT_Encode4(113338), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2528 //
40952 /* 113272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
40953 /* 113276 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40954 /* 113280 */ // (fpround:{ *:[f16] } DPR:{ *:[f64] }:$Dm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBDH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), DPR:{ *:[f64] }:$Dm), HPR:{ *:[i32] })
40955 /* 113280 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
40956 /* 113283 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40957 /* 113287 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40958 /* 113292 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
40959 /* 113294 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
40960 /* 113297 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBDH),
40961 /* 113301 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40962 /* 113306 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
40963 /* 113309 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dm
40964 /* 113313 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
40965 /* 113316 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40966 /* 113322 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
40967 /* 113324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
40968 /* 113327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
40969 /* 113329 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40970 /* 113332 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
40971 /* 113337 */ // GIR_Coverage, 2528,
40972 /* 113337 */ GIR_EraseRootFromParent_Done,
40973 /* 113338 */ // Label 3421: @113338
40974 /* 113338 */ GIM_Reject,
40975 /* 113339 */ // Label 3419: @113339
40976 /* 113339 */ GIM_Reject,
40977 /* 113340 */ // Label 3414: @113340
40978 /* 113340 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3422*/ GIMT_Encode4(113376), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 688 //
40979 /* 113347 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
40980 /* 113350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
40981 /* 113354 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40982 /* 113358 */ // (fpround:{ *:[f32] } DPR:{ *:[f64] }:$Dm) => (VCVTSD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
40983 /* 113358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTSD),
40984 /* 113361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
40985 /* 113363 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
40986 /* 113365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40987 /* 113368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40988 /* 113374 */ GIR_RootConstrainSelectedInstOperands,
40989 /* 113375 */ // GIR_Coverage, 688,
40990 /* 113375 */ GIR_EraseRootFromParent_Done,
40991 /* 113376 */ // Label 3422: @113376
40992 /* 113376 */ GIM_Reject,
40993 /* 113377 */ // Label 3415: @113377
40994 /* 113377 */ GIM_Try, /*On fail goto*//*Label 3423*/ GIMT_Encode4(113411), // Rule ID 3058 //
40995 /* 113382 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
40996 /* 113385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40997 /* 113389 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40998 /* 113393 */ // (fpround:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src) => (VCVTf2h:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src)
40999 /* 113393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h),
41000 /* 113396 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41001 /* 113398 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
41002 /* 113400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41003 /* 113403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41004 /* 113409 */ GIR_RootConstrainSelectedInstOperands,
41005 /* 113410 */ // GIR_Coverage, 3058,
41006 /* 113410 */ GIR_EraseRootFromParent_Done,
41007 /* 113411 */ // Label 3423: @113411
41008 /* 113411 */ GIM_Reject,
41009 /* 113412 */ // Label 3416: @113412
41010 /* 113412 */ GIM_Reject,
41011 /* 113413 */ // Label 48: @113413
41012 /* 113413 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3431*/ GIMT_Encode4(114694),
41013 /* 113424 */ /*GILLT_s32*//*Label 3424*/ GIMT_Encode4(113472), GIMT_Encode4(0), GIMT_Encode4(0),
41014 /* 113436 */ /*GILLT_v4s1*//*Label 3425*/ GIMT_Encode4(114322),
41015 /* 113440 */ /*GILLT_v8s1*//*Label 3426*/ GIMT_Encode4(114374), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
41016 /* 113456 */ /*GILLT_v4s16*//*Label 3427*/ GIMT_Encode4(114426),
41017 /* 113460 */ /*GILLT_v8s16*//*Label 3428*/ GIMT_Encode4(114463),
41018 /* 113464 */ /*GILLT_v2s32*//*Label 3429*/ GIMT_Encode4(114560),
41019 /* 113468 */ /*GILLT_v4s32*//*Label 3430*/ GIMT_Encode4(114597),
41020 /* 113472 */ // Label 3424: @113472
41021 /* 113472 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3435*/ GIMT_Encode4(114321),
41022 /* 113483 */ /*GILLT_s16*//*Label 3432*/ GIMT_Encode4(113495),
41023 /* 113487 */ /*GILLT_s32*//*Label 3433*/ GIMT_Encode4(113732),
41024 /* 113491 */ /*GILLT_s64*//*Label 3434*/ GIMT_Encode4(114084),
41025 /* 113495 */ // Label 3432: @113495
41026 /* 113495 */ GIM_Try, /*On fail goto*//*Label 3436*/ GIMT_Encode4(113731),
41027 /* 113500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
41028 /* 113504 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3437*/ GIMT_Encode4(113562), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2558 //
41029 /* 113511 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41030 /* 113515 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
41031 /* 113519 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41032 /* 113523 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41033 /* 113528 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41034 /* 113530 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41035 /* 113530 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41036 /* 113533 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSH),
41037 /* 113537 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41038 /* 113542 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41039 /* 113546 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41040 /* 113548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41041 /* 113551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41042 /* 113553 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41043 /* 113556 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41044 /* 113561 */ // GIR_Coverage, 2558,
41045 /* 113561 */ GIR_EraseRootFromParent_Done,
41046 /* 113562 */ // Label 3437: @113562
41047 /* 113562 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3438*/ GIMT_Encode4(113620), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2582 //
41048 /* 113569 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41049 /* 113573 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
41050 /* 113577 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41051 /* 113581 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41052 /* 113586 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41053 /* 113588 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41054 /* 113588 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41055 /* 113591 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSH),
41056 /* 113595 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41057 /* 113600 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41058 /* 113604 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41059 /* 113606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41060 /* 113609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41061 /* 113611 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41062 /* 113614 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41063 /* 113619 */ // GIR_Coverage, 2582,
41064 /* 113619 */ GIR_EraseRootFromParent_Done,
41065 /* 113620 */ // Label 3438: @113620
41066 /* 113620 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3439*/ GIMT_Encode4(113678), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2534 //
41067 /* 113627 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41068 /* 113631 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
41069 /* 113635 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41070 /* 113639 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41071 /* 113644 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41072 /* 113646 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41073 /* 113646 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41074 /* 113649 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASH),
41075 /* 113653 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41076 /* 113658 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41077 /* 113662 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41078 /* 113664 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41079 /* 113667 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41080 /* 113669 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41081 /* 113672 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41082 /* 113677 */ // GIR_Coverage, 2534,
41083 /* 113677 */ GIR_EraseRootFromParent_Done,
41084 /* 113678 */ // Label 3439: @113678
41085 /* 113678 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3440*/ GIMT_Encode4(113730), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2643 //
41086 /* 113685 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41087 /* 113689 */ // (fp_to_sint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41088 /* 113689 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41089 /* 113692 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZH),
41090 /* 113696 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41091 /* 113701 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
41092 /* 113705 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41093 /* 113708 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41094 /* 113714 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41095 /* 113716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41096 /* 113719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41097 /* 113721 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41098 /* 113724 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41099 /* 113729 */ // GIR_Coverage, 2643,
41100 /* 113729 */ GIR_EraseRootFromParent_Done,
41101 /* 113730 */ // Label 3440: @113730
41102 /* 113730 */ GIM_Reject,
41103 /* 113731 */ // Label 3436: @113731
41104 /* 113731 */ GIM_Reject,
41105 /* 113732 */ // Label 3433: @113732
41106 /* 113732 */ GIM_Try, /*On fail goto*//*Label 3441*/ GIMT_Encode4(113968),
41107 /* 113737 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
41108 /* 113741 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3442*/ GIMT_Encode4(113799), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2566 //
41109 /* 113748 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41110 /* 113752 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
41111 /* 113756 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41112 /* 113760 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41113 /* 113765 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41114 /* 113767 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41115 /* 113767 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41116 /* 113770 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSS),
41117 /* 113774 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41118 /* 113779 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41119 /* 113783 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41120 /* 113785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41121 /* 113788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41122 /* 113790 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41123 /* 113793 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41124 /* 113798 */ // GIR_Coverage, 2566,
41125 /* 113798 */ GIR_EraseRootFromParent_Done,
41126 /* 113799 */ // Label 3442: @113799
41127 /* 113799 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3443*/ GIMT_Encode4(113857), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2590 //
41128 /* 113806 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41129 /* 113810 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
41130 /* 113814 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41131 /* 113818 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41132 /* 113823 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41133 /* 113825 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41134 /* 113825 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41135 /* 113828 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSS),
41136 /* 113832 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41137 /* 113837 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41138 /* 113841 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41139 /* 113843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41140 /* 113846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41141 /* 113848 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41142 /* 113851 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41143 /* 113856 */ // GIR_Coverage, 2590,
41144 /* 113856 */ GIR_EraseRootFromParent_Done,
41145 /* 113857 */ // Label 3443: @113857
41146 /* 113857 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3444*/ GIMT_Encode4(113915), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2542 //
41147 /* 113864 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41148 /* 113868 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
41149 /* 113872 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41150 /* 113876 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41151 /* 113881 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41152 /* 113883 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41153 /* 113883 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41154 /* 113886 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASS),
41155 /* 113890 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41156 /* 113895 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41157 /* 113899 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41158 /* 113901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41159 /* 113904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41160 /* 113906 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41161 /* 113909 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41162 /* 113914 */ // GIR_Coverage, 2542,
41163 /* 113914 */ GIR_EraseRootFromParent_Done,
41164 /* 113915 */ // Label 3444: @113915
41165 /* 113915 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3445*/ GIMT_Encode4(113967), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2637 //
41166 /* 113922 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41167 /* 113926 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41168 /* 113926 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41169 /* 113929 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZS),
41170 /* 113933 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41171 /* 113938 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
41172 /* 113942 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41173 /* 113945 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41174 /* 113951 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41175 /* 113953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41176 /* 113956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41177 /* 113958 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41178 /* 113961 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41179 /* 113966 */ // GIR_Coverage, 2637,
41180 /* 113966 */ GIR_EraseRootFromParent_Done,
41181 /* 113967 */ // Label 3445: @113967
41182 /* 113967 */ GIM_Reject,
41183 /* 113968 */ // Label 3441: @113968
41184 /* 113968 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3446*/ GIMT_Encode4(114083), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3099 //
41185 /* 113975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41186 /* 113979 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41187 /* 113983 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2sd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
41188 /* 113983 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41189 /* 113986 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41190 /* 113990 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41191 /* 113995 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41192 /* 113997 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
41193 /* 114000 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41194 /* 114004 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41195 /* 114009 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41196 /* 114012 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
41197 /* 114016 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
41198 /* 114019 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41199 /* 114024 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41200 /* 114029 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41201 /* 114034 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41202 /* 114037 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd),
41203 /* 114041 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41204 /* 114046 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41205 /* 114049 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41206 /* 114052 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41207 /* 114058 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41208 /* 114060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41209 /* 114063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41210 /* 114065 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41211 /* 114072 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41212 /* 114077 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41213 /* 114082 */ // GIR_Coverage, 3099,
41214 /* 114082 */ GIR_EraseRootFromParent_Done,
41215 /* 114083 */ // Label 3446: @114083
41216 /* 114083 */ GIM_Reject,
41217 /* 114084 */ // Label 3434: @114084
41218 /* 114084 */ GIM_Try, /*On fail goto*//*Label 3447*/ GIMT_Encode4(114320),
41219 /* 114089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
41220 /* 114093 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3448*/ GIMT_Encode4(114151), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2574 //
41221 /* 114100 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41222 /* 114104 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
41223 /* 114108 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41224 /* 114112 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41225 /* 114117 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41226 /* 114119 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41227 /* 114119 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41228 /* 114122 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSD),
41229 /* 114126 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41230 /* 114131 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41231 /* 114135 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41232 /* 114137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41233 /* 114140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41234 /* 114142 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41235 /* 114145 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41236 /* 114150 */ // GIR_Coverage, 2574,
41237 /* 114150 */ GIR_EraseRootFromParent_Done,
41238 /* 114151 */ // Label 3448: @114151
41239 /* 114151 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3449*/ GIMT_Encode4(114209), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2598 //
41240 /* 114158 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41241 /* 114162 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
41242 /* 114166 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41243 /* 114170 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41244 /* 114175 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41245 /* 114177 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41246 /* 114177 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41247 /* 114180 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSD),
41248 /* 114184 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41249 /* 114189 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41250 /* 114193 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41251 /* 114195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41252 /* 114198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41253 /* 114200 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41254 /* 114203 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41255 /* 114208 */ // GIR_Coverage, 2598,
41256 /* 114208 */ GIR_EraseRootFromParent_Done,
41257 /* 114209 */ // Label 3449: @114209
41258 /* 114209 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3450*/ GIMT_Encode4(114267), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2550 //
41259 /* 114216 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41260 /* 114220 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
41261 /* 114224 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41262 /* 114228 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41263 /* 114233 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41264 /* 114235 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41265 /* 114235 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41266 /* 114238 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASD),
41267 /* 114242 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41268 /* 114247 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41269 /* 114251 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41270 /* 114253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41271 /* 114256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41272 /* 114258 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41273 /* 114261 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41274 /* 114266 */ // GIR_Coverage, 2550,
41275 /* 114266 */ GIR_EraseRootFromParent_Done,
41276 /* 114267 */ // Label 3450: @114267
41277 /* 114267 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3451*/ GIMT_Encode4(114319), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2631 //
41278 /* 114274 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41279 /* 114278 */ // (fp_to_sint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41280 /* 114278 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41281 /* 114281 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZD),
41282 /* 114285 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41283 /* 114290 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
41284 /* 114294 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41285 /* 114297 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41286 /* 114303 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41287 /* 114305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41288 /* 114308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41289 /* 114310 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41290 /* 114313 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41291 /* 114318 */ // GIR_Coverage, 2631,
41292 /* 114318 */ GIR_EraseRootFromParent_Done,
41293 /* 114319 */ // Label 3451: @114319
41294 /* 114319 */ GIM_Reject,
41295 /* 114320 */ // Label 3447: @114320
41296 /* 114320 */ GIM_Reject,
41297 /* 114321 */ // Label 3435: @114321
41298 /* 114321 */ GIM_Reject,
41299 /* 114322 */ // Label 3425: @114322
41300 /* 114322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3452*/ GIMT_Encode4(114373), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5640 //
41301 /* 114329 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
41302 /* 114332 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
41303 /* 114336 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41304 /* 114340 */ // (fp_to_sint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
41305 /* 114340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r),
41306 /* 114343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
41307 /* 114345 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
41308 /* 114347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41309 /* 114353 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
41310 /* 114356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41311 /* 114359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41312 /* 114365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41313 /* 114371 */ GIR_RootConstrainSelectedInstOperands,
41314 /* 114372 */ // GIR_Coverage, 5640,
41315 /* 114372 */ GIR_EraseRootFromParent_Done,
41316 /* 114373 */ // Label 3452: @114373
41317 /* 114373 */ GIM_Reject,
41318 /* 114374 */ // Label 3426: @114374
41319 /* 114374 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3453*/ GIMT_Encode4(114425), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5641 //
41320 /* 114381 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
41321 /* 114384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
41322 /* 114388 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41323 /* 114392 */ // (fp_to_sint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
41324 /* 114392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r),
41325 /* 114395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
41326 /* 114397 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
41327 /* 114399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41328 /* 114405 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
41329 /* 114408 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41330 /* 114411 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41331 /* 114417 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41332 /* 114423 */ GIR_RootConstrainSelectedInstOperands,
41333 /* 114424 */ // GIR_Coverage, 5641,
41334 /* 114424 */ GIR_EraseRootFromParent_Done,
41335 /* 114425 */ // Label 3453: @114425
41336 /* 114425 */ GIM_Reject,
41337 /* 114426 */ // Label 3427: @114426
41338 /* 114426 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3454*/ GIMT_Encode4(114462), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1774 //
41339 /* 114433 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
41340 /* 114436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41341 /* 114440 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41342 /* 114444 */ // (fp_to_sint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2sd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
41343 /* 114444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sd),
41344 /* 114447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41345 /* 114449 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41346 /* 114451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41347 /* 114454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41348 /* 114460 */ GIR_RootConstrainSelectedInstOperands,
41349 /* 114461 */ // GIR_Coverage, 1774,
41350 /* 114461 */ GIR_EraseRootFromParent_Done,
41351 /* 114462 */ // Label 3454: @114462
41352 /* 114462 */ GIM_Reject,
41353 /* 114463 */ // Label 3428: @114463
41354 /* 114463 */ GIM_Try, /*On fail goto*//*Label 3455*/ GIMT_Encode4(114559),
41355 /* 114468 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
41356 /* 114471 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3456*/ GIMT_Encode4(114504), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1778 //
41357 /* 114478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41358 /* 114482 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41359 /* 114486 */ // (fp_to_sint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2sq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
41360 /* 114486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sq),
41361 /* 114489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41362 /* 114491 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41363 /* 114493 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41364 /* 114496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41365 /* 114502 */ GIR_RootConstrainSelectedInstOperands,
41366 /* 114503 */ // GIR_Coverage, 1778,
41367 /* 114503 */ GIR_EraseRootFromParent_Done,
41368 /* 114504 */ // Label 3456: @114504
41369 /* 114504 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3457*/ GIMT_Encode4(114558), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4541 //
41370 /* 114511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41371 /* 114515 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41372 /* 114519 */ // (fp_to_sint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
41373 /* 114519 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41374 /* 114522 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41375 /* 114526 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41376 /* 114531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z),
41377 /* 114534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
41378 /* 114536 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
41379 /* 114538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41380 /* 114541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41381 /* 114547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41382 /* 114553 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41383 /* 114556 */ GIR_RootConstrainSelectedInstOperands,
41384 /* 114557 */ // GIR_Coverage, 4541,
41385 /* 114557 */ GIR_EraseRootFromParent_Done,
41386 /* 114558 */ // Label 3457: @114558
41387 /* 114558 */ GIM_Reject,
41388 /* 114559 */ // Label 3455: @114559
41389 /* 114559 */ GIM_Reject,
41390 /* 114560 */ // Label 3429: @114560
41391 /* 114560 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3458*/ GIMT_Encode4(114596), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1766 //
41392 /* 114567 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
41393 /* 114570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41394 /* 114574 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41395 /* 114578 */ // (fp_to_sint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2sd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
41396 /* 114578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd),
41397 /* 114581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41398 /* 114583 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41399 /* 114585 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41400 /* 114588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41401 /* 114594 */ GIR_RootConstrainSelectedInstOperands,
41402 /* 114595 */ // GIR_Coverage, 1766,
41403 /* 114595 */ GIR_EraseRootFromParent_Done,
41404 /* 114596 */ // Label 3458: @114596
41405 /* 114596 */ GIM_Reject,
41406 /* 114597 */ // Label 3430: @114597
41407 /* 114597 */ GIM_Try, /*On fail goto*//*Label 3459*/ GIMT_Encode4(114693),
41408 /* 114602 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
41409 /* 114605 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3460*/ GIMT_Encode4(114638), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1770 //
41410 /* 114612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41411 /* 114616 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41412 /* 114620 */ // (fp_to_sint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2sq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
41413 /* 114620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sq),
41414 /* 114623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41415 /* 114625 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41416 /* 114627 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41417 /* 114630 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41418 /* 114636 */ GIR_RootConstrainSelectedInstOperands,
41419 /* 114637 */ // GIR_Coverage, 1770,
41420 /* 114637 */ GIR_EraseRootFromParent_Done,
41421 /* 114638 */ // Label 3460: @114638
41422 /* 114638 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3461*/ GIMT_Encode4(114692), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4547 //
41423 /* 114645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41424 /* 114649 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41425 /* 114653 */ // (fp_to_sint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
41426 /* 114653 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41427 /* 114656 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41428 /* 114660 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41429 /* 114665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z),
41430 /* 114668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
41431 /* 114670 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
41432 /* 114672 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41433 /* 114675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41434 /* 114681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41435 /* 114687 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41436 /* 114690 */ GIR_RootConstrainSelectedInstOperands,
41437 /* 114691 */ // GIR_Coverage, 4547,
41438 /* 114691 */ GIR_EraseRootFromParent_Done,
41439 /* 114692 */ // Label 3461: @114692
41440 /* 114692 */ GIM_Reject,
41441 /* 114693 */ // Label 3459: @114693
41442 /* 114693 */ GIM_Reject,
41443 /* 114694 */ // Label 3431: @114694
41444 /* 114694 */ GIM_Reject,
41445 /* 114695 */ // Label 49: @114695
41446 /* 114695 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3469*/ GIMT_Encode4(115976),
41447 /* 114706 */ /*GILLT_s32*//*Label 3462*/ GIMT_Encode4(114754), GIMT_Encode4(0), GIMT_Encode4(0),
41448 /* 114718 */ /*GILLT_v4s1*//*Label 3463*/ GIMT_Encode4(115604),
41449 /* 114722 */ /*GILLT_v8s1*//*Label 3464*/ GIMT_Encode4(115656), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
41450 /* 114738 */ /*GILLT_v4s16*//*Label 3465*/ GIMT_Encode4(115708),
41451 /* 114742 */ /*GILLT_v8s16*//*Label 3466*/ GIMT_Encode4(115745),
41452 /* 114746 */ /*GILLT_v2s32*//*Label 3467*/ GIMT_Encode4(115842),
41453 /* 114750 */ /*GILLT_v4s32*//*Label 3468*/ GIMT_Encode4(115879),
41454 /* 114754 */ // Label 3462: @114754
41455 /* 114754 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3473*/ GIMT_Encode4(115603),
41456 /* 114765 */ /*GILLT_s16*//*Label 3470*/ GIMT_Encode4(114777),
41457 /* 114769 */ /*GILLT_s32*//*Label 3471*/ GIMT_Encode4(115014),
41458 /* 114773 */ /*GILLT_s64*//*Label 3472*/ GIMT_Encode4(115366),
41459 /* 114777 */ // Label 3470: @114777
41460 /* 114777 */ GIM_Try, /*On fail goto*//*Label 3474*/ GIMT_Encode4(115013),
41461 /* 114782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
41462 /* 114786 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3475*/ GIMT_Encode4(114844), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2562 //
41463 /* 114793 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41464 /* 114797 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
41465 /* 114801 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41466 /* 114805 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41467 /* 114810 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41468 /* 114812 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41469 /* 114812 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41470 /* 114815 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUH),
41471 /* 114819 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41472 /* 114824 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41473 /* 114828 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41474 /* 114830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41475 /* 114833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41476 /* 114835 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41477 /* 114838 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41478 /* 114843 */ // GIR_Coverage, 2562,
41479 /* 114843 */ GIR_EraseRootFromParent_Done,
41480 /* 114844 */ // Label 3475: @114844
41481 /* 114844 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3476*/ GIMT_Encode4(114902), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2586 //
41482 /* 114851 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41483 /* 114855 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
41484 /* 114859 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41485 /* 114863 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41486 /* 114868 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41487 /* 114870 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41488 /* 114870 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41489 /* 114873 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUH),
41490 /* 114877 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41491 /* 114882 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41492 /* 114886 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41493 /* 114888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41494 /* 114891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41495 /* 114893 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41496 /* 114896 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41497 /* 114901 */ // GIR_Coverage, 2586,
41498 /* 114901 */ GIR_EraseRootFromParent_Done,
41499 /* 114902 */ // Label 3476: @114902
41500 /* 114902 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3477*/ GIMT_Encode4(114960), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2538 //
41501 /* 114909 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41502 /* 114913 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
41503 /* 114917 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
41504 /* 114921 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41505 /* 114926 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41506 /* 114928 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41507 /* 114928 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41508 /* 114931 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUH),
41509 /* 114935 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41510 /* 114940 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41511 /* 114944 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41512 /* 114946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41513 /* 114949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41514 /* 114951 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41515 /* 114954 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41516 /* 114959 */ // GIR_Coverage, 2538,
41517 /* 114959 */ GIR_EraseRootFromParent_Done,
41518 /* 114960 */ // Label 3477: @114960
41519 /* 114960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3478*/ GIMT_Encode4(115012), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2658 //
41520 /* 114967 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41521 /* 114971 */ // (fp_to_uint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
41522 /* 114971 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41523 /* 114974 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZH),
41524 /* 114978 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41525 /* 114983 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
41526 /* 114987 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41527 /* 114990 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41528 /* 114996 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41529 /* 114998 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41530 /* 115001 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41531 /* 115003 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41532 /* 115006 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41533 /* 115011 */ // GIR_Coverage, 2658,
41534 /* 115011 */ GIR_EraseRootFromParent_Done,
41535 /* 115012 */ // Label 3478: @115012
41536 /* 115012 */ GIM_Reject,
41537 /* 115013 */ // Label 3474: @115013
41538 /* 115013 */ GIM_Reject,
41539 /* 115014 */ // Label 3471: @115014
41540 /* 115014 */ GIM_Try, /*On fail goto*//*Label 3479*/ GIMT_Encode4(115250),
41541 /* 115019 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
41542 /* 115023 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3480*/ GIMT_Encode4(115081), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2570 //
41543 /* 115030 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41544 /* 115034 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
41545 /* 115038 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41546 /* 115042 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41547 /* 115047 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41548 /* 115049 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41549 /* 115049 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41550 /* 115052 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUS),
41551 /* 115056 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41552 /* 115061 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41553 /* 115065 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41554 /* 115067 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41555 /* 115070 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41556 /* 115072 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41557 /* 115075 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41558 /* 115080 */ // GIR_Coverage, 2570,
41559 /* 115080 */ GIR_EraseRootFromParent_Done,
41560 /* 115081 */ // Label 3480: @115081
41561 /* 115081 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3481*/ GIMT_Encode4(115139), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2594 //
41562 /* 115088 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41563 /* 115092 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
41564 /* 115096 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41565 /* 115100 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41566 /* 115105 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41567 /* 115107 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41568 /* 115107 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41569 /* 115110 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUS),
41570 /* 115114 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41571 /* 115119 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41572 /* 115123 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41573 /* 115125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41574 /* 115128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41575 /* 115130 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41576 /* 115133 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41577 /* 115138 */ // GIR_Coverage, 2594,
41578 /* 115138 */ GIR_EraseRootFromParent_Done,
41579 /* 115139 */ // Label 3481: @115139
41580 /* 115139 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3482*/ GIMT_Encode4(115197), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 2546 //
41581 /* 115146 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41582 /* 115150 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
41583 /* 115154 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41584 /* 115158 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41585 /* 115163 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41586 /* 115165 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41587 /* 115165 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41588 /* 115168 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUS),
41589 /* 115172 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41590 /* 115177 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41591 /* 115181 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41592 /* 115183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41593 /* 115186 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41594 /* 115188 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41595 /* 115191 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41596 /* 115196 */ // GIR_Coverage, 2546,
41597 /* 115196 */ GIR_EraseRootFromParent_Done,
41598 /* 115197 */ // Label 3482: @115197
41599 /* 115197 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3483*/ GIMT_Encode4(115249), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2652 //
41600 /* 115204 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41601 /* 115208 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
41602 /* 115208 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41603 /* 115211 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZS),
41604 /* 115215 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41605 /* 115220 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
41606 /* 115224 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41607 /* 115227 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41608 /* 115233 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41609 /* 115235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41610 /* 115238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41611 /* 115240 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41612 /* 115243 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41613 /* 115248 */ // GIR_Coverage, 2652,
41614 /* 115248 */ GIR_EraseRootFromParent_Done,
41615 /* 115249 */ // Label 3483: @115249
41616 /* 115249 */ GIM_Reject,
41617 /* 115250 */ // Label 3479: @115250
41618 /* 115250 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3484*/ GIMT_Encode4(115365), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3100 //
41619 /* 115257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41620 /* 115261 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41621 /* 115265 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2ud:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
41622 /* 115265 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41623 /* 115268 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41624 /* 115272 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41625 /* 115277 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41626 /* 115279 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
41627 /* 115282 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41628 /* 115286 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41629 /* 115291 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41630 /* 115294 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
41631 /* 115298 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
41632 /* 115301 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41633 /* 115306 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41634 /* 115311 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41635 /* 115316 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41636 /* 115319 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud),
41637 /* 115323 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41638 /* 115328 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41639 /* 115331 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41640 /* 115334 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41641 /* 115340 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41642 /* 115342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41643 /* 115345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41644 /* 115347 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41645 /* 115354 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41646 /* 115359 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41647 /* 115364 */ // GIR_Coverage, 3100,
41648 /* 115364 */ GIR_EraseRootFromParent_Done,
41649 /* 115365 */ // Label 3484: @115365
41650 /* 115365 */ GIM_Reject,
41651 /* 115366 */ // Label 3472: @115366
41652 /* 115366 */ GIM_Try, /*On fail goto*//*Label 3485*/ GIMT_Encode4(115602),
41653 /* 115371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
41654 /* 115375 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3486*/ GIMT_Encode4(115433), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2578 //
41655 /* 115382 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41656 /* 115386 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
41657 /* 115390 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41658 /* 115394 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41659 /* 115399 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41660 /* 115401 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41661 /* 115401 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41662 /* 115404 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUD),
41663 /* 115408 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41664 /* 115413 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41665 /* 115417 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41666 /* 115419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41667 /* 115422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41668 /* 115424 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41669 /* 115427 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41670 /* 115432 */ // GIR_Coverage, 2578,
41671 /* 115432 */ GIR_EraseRootFromParent_Done,
41672 /* 115433 */ // Label 3486: @115433
41673 /* 115433 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3487*/ GIMT_Encode4(115491), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2602 //
41674 /* 115440 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41675 /* 115444 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
41676 /* 115448 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41677 /* 115452 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41678 /* 115457 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41679 /* 115459 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41680 /* 115459 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41681 /* 115462 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUD),
41682 /* 115466 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41683 /* 115471 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41684 /* 115475 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41685 /* 115477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41686 /* 115480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41687 /* 115482 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41688 /* 115485 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41689 /* 115490 */ // GIR_Coverage, 2602,
41690 /* 115490 */ GIR_EraseRootFromParent_Done,
41691 /* 115491 */ // Label 3487: @115491
41692 /* 115491 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3488*/ GIMT_Encode4(115549), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 2554 //
41693 /* 115498 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41694 /* 115502 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
41695 /* 115506 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
41696 /* 115510 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41697 /* 115515 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41698 /* 115517 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41699 /* 115517 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41700 /* 115520 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUD),
41701 /* 115524 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41702 /* 115529 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
41703 /* 115533 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41704 /* 115535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41705 /* 115538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41706 /* 115540 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41707 /* 115543 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41708 /* 115548 */ // GIR_Coverage, 2554,
41709 /* 115548 */ GIR_EraseRootFromParent_Done,
41710 /* 115549 */ // Label 3488: @115549
41711 /* 115549 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3489*/ GIMT_Encode4(115601), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2646 //
41712 /* 115556 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41713 /* 115560 */ // (fp_to_uint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
41714 /* 115560 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41715 /* 115563 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZD),
41716 /* 115567 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41717 /* 115572 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
41718 /* 115576 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41719 /* 115579 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41720 /* 115585 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41721 /* 115587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41722 /* 115590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41723 /* 115592 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41724 /* 115595 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
41725 /* 115600 */ // GIR_Coverage, 2646,
41726 /* 115600 */ GIR_EraseRootFromParent_Done,
41727 /* 115601 */ // Label 3489: @115601
41728 /* 115601 */ GIM_Reject,
41729 /* 115602 */ // Label 3485: @115602
41730 /* 115602 */ GIM_Reject,
41731 /* 115603 */ // Label 3473: @115603
41732 /* 115603 */ GIM_Reject,
41733 /* 115604 */ // Label 3463: @115604
41734 /* 115604 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3490*/ GIMT_Encode4(115655), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5638 //
41735 /* 115611 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
41736 /* 115614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
41737 /* 115618 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41738 /* 115622 */ // (fp_to_uint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
41739 /* 115622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r),
41740 /* 115625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
41741 /* 115627 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
41742 /* 115629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41743 /* 115635 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
41744 /* 115638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41745 /* 115641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41746 /* 115647 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41747 /* 115653 */ GIR_RootConstrainSelectedInstOperands,
41748 /* 115654 */ // GIR_Coverage, 5638,
41749 /* 115654 */ GIR_EraseRootFromParent_Done,
41750 /* 115655 */ // Label 3490: @115655
41751 /* 115655 */ GIM_Reject,
41752 /* 115656 */ // Label 3464: @115656
41753 /* 115656 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3491*/ GIMT_Encode4(115707), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 5639 //
41754 /* 115663 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
41755 /* 115666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
41756 /* 115670 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41757 /* 115674 */ // (fp_to_uint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
41758 /* 115674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r),
41759 /* 115677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
41760 /* 115679 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
41761 /* 115681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41762 /* 115687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
41763 /* 115690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41764 /* 115693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41765 /* 115699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41766 /* 115705 */ GIR_RootConstrainSelectedInstOperands,
41767 /* 115706 */ // GIR_Coverage, 5639,
41768 /* 115706 */ GIR_EraseRootFromParent_Done,
41769 /* 115707 */ // Label 3491: @115707
41770 /* 115707 */ GIM_Reject,
41771 /* 115708 */ // Label 3465: @115708
41772 /* 115708 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3492*/ GIMT_Encode4(115744), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1775 //
41773 /* 115715 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
41774 /* 115718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41775 /* 115722 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41776 /* 115726 */ // (fp_to_uint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2ud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
41777 /* 115726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2ud),
41778 /* 115729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41779 /* 115731 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41780 /* 115733 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41781 /* 115736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41782 /* 115742 */ GIR_RootConstrainSelectedInstOperands,
41783 /* 115743 */ // GIR_Coverage, 1775,
41784 /* 115743 */ GIR_EraseRootFromParent_Done,
41785 /* 115744 */ // Label 3492: @115744
41786 /* 115744 */ GIM_Reject,
41787 /* 115745 */ // Label 3466: @115745
41788 /* 115745 */ GIM_Try, /*On fail goto*//*Label 3493*/ GIMT_Encode4(115841),
41789 /* 115750 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
41790 /* 115753 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3494*/ GIMT_Encode4(115786), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1779 //
41791 /* 115760 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41792 /* 115764 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41793 /* 115768 */ // (fp_to_uint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2uq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
41794 /* 115768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2uq),
41795 /* 115771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41796 /* 115773 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41797 /* 115775 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41798 /* 115778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41799 /* 115784 */ GIR_RootConstrainSelectedInstOperands,
41800 /* 115785 */ // GIR_Coverage, 1779,
41801 /* 115785 */ GIR_EraseRootFromParent_Done,
41802 /* 115786 */ // Label 3494: @115786
41803 /* 115786 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3495*/ GIMT_Encode4(115840), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4544 //
41804 /* 115793 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41805 /* 115797 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41806 /* 115801 */ // (fp_to_uint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
41807 /* 115801 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41808 /* 115804 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41809 /* 115808 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41810 /* 115813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z),
41811 /* 115816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
41812 /* 115818 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
41813 /* 115820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41814 /* 115823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41815 /* 115829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41816 /* 115835 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41817 /* 115838 */ GIR_RootConstrainSelectedInstOperands,
41818 /* 115839 */ // GIR_Coverage, 4544,
41819 /* 115839 */ GIR_EraseRootFromParent_Done,
41820 /* 115840 */ // Label 3495: @115840
41821 /* 115840 */ GIM_Reject,
41822 /* 115841 */ // Label 3493: @115841
41823 /* 115841 */ GIM_Reject,
41824 /* 115842 */ // Label 3467: @115842
41825 /* 115842 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3496*/ GIMT_Encode4(115878), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1767 //
41826 /* 115849 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
41827 /* 115852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41828 /* 115856 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41829 /* 115860 */ // (fp_to_uint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2ud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
41830 /* 115860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud),
41831 /* 115863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41832 /* 115865 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41833 /* 115867 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41834 /* 115870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41835 /* 115876 */ GIR_RootConstrainSelectedInstOperands,
41836 /* 115877 */ // GIR_Coverage, 1767,
41837 /* 115877 */ GIR_EraseRootFromParent_Done,
41838 /* 115878 */ // Label 3496: @115878
41839 /* 115878 */ GIM_Reject,
41840 /* 115879 */ // Label 3468: @115879
41841 /* 115879 */ GIM_Try, /*On fail goto*//*Label 3497*/ GIMT_Encode4(115975),
41842 /* 115884 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
41843 /* 115887 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3498*/ GIMT_Encode4(115920), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1771 //
41844 /* 115894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41845 /* 115898 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41846 /* 115902 */ // (fp_to_uint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2uq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
41847 /* 115902 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2uq),
41848 /* 115905 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41849 /* 115907 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41850 /* 115909 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41851 /* 115912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41852 /* 115918 */ GIR_RootConstrainSelectedInstOperands,
41853 /* 115919 */ // GIR_Coverage, 1771,
41854 /* 115919 */ GIR_EraseRootFromParent_Done,
41855 /* 115920 */ // Label 3498: @115920
41856 /* 115920 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3499*/ GIMT_Encode4(115974), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4550 //
41857 /* 115927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41858 /* 115931 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41859 /* 115935 */ // (fp_to_uint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
41860 /* 115935 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41861 /* 115938 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41862 /* 115942 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41863 /* 115947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z),
41864 /* 115950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
41865 /* 115952 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
41866 /* 115954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41867 /* 115957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41868 /* 115963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41869 /* 115969 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41870 /* 115972 */ GIR_RootConstrainSelectedInstOperands,
41871 /* 115973 */ // GIR_Coverage, 4550,
41872 /* 115973 */ GIR_EraseRootFromParent_Done,
41873 /* 115974 */ // Label 3499: @115974
41874 /* 115974 */ GIM_Reject,
41875 /* 115975 */ // Label 3497: @115975
41876 /* 115975 */ GIM_Reject,
41877 /* 115976 */ // Label 3469: @115976
41878 /* 115976 */ GIM_Reject,
41879 /* 115977 */ // Label 50: @115977
41880 /* 115977 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3507*/ GIMT_Encode4(116618),
41881 /* 115988 */ /*GILLT_s16*//*Label 3500*/ GIMT_Encode4(116040),
41882 /* 115992 */ /*GILLT_s32*//*Label 3501*/ GIMT_Encode4(116099),
41883 /* 115996 */ /*GILLT_s64*//*Label 3502*/ GIMT_Encode4(116291), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
41884 /* 116024 */ /*GILLT_v4s16*//*Label 3503*/ GIMT_Encode4(116350),
41885 /* 116028 */ /*GILLT_v8s16*//*Label 3504*/ GIMT_Encode4(116387),
41886 /* 116032 */ /*GILLT_v2s32*//*Label 3505*/ GIMT_Encode4(116484),
41887 /* 116036 */ /*GILLT_v4s32*//*Label 3506*/ GIMT_Encode4(116521),
41888 /* 116040 */ // Label 3500: @116040
41889 /* 116040 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3508*/ GIMT_Encode4(116098), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2619 //
41890 /* 116047 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
41891 /* 116050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41892 /* 116054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
41893 /* 116058 */ // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VSITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
41894 /* 116058 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41895 /* 116061 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41896 /* 116065 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41897 /* 116070 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
41898 /* 116074 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41899 /* 116079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOH),
41900 /* 116082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
41901 /* 116084 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41902 /* 116087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41903 /* 116090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41904 /* 116096 */ GIR_RootConstrainSelectedInstOperands,
41905 /* 116097 */ // GIR_Coverage, 2619,
41906 /* 116097 */ GIR_EraseRootFromParent_Done,
41907 /* 116098 */ // Label 3508: @116098
41908 /* 116098 */ GIM_Reject,
41909 /* 116099 */ // Label 3501: @116099
41910 /* 116099 */ GIM_Try, /*On fail goto*//*Label 3509*/ GIMT_Encode4(116290),
41911 /* 116104 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
41912 /* 116107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41913 /* 116111 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
41914 /* 116115 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3510*/ GIMT_Encode4(116162), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2615 //
41915 /* 116122 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VSITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
41916 /* 116122 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41917 /* 116125 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41918 /* 116129 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41919 /* 116134 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
41920 /* 116138 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41921 /* 116143 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOS),
41922 /* 116146 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
41923 /* 116148 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41924 /* 116151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41925 /* 116154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41926 /* 116160 */ GIR_RootConstrainSelectedInstOperands,
41927 /* 116161 */ // GIR_Coverage, 2615,
41928 /* 116161 */ GIR_EraseRootFromParent_Done,
41929 /* 116162 */ // Label 3510: @116162
41930 /* 116162 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3511*/ GIMT_Encode4(116289), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3101 //
41931 /* 116169 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTs2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
41932 /* 116169 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
41933 /* 116172 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41934 /* 116176 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41935 /* 116181 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a
41936 /* 116185 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41937 /* 116190 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41938 /* 116193 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41939 /* 116197 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41940 /* 116202 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
41941 /* 116204 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
41942 /* 116207 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41943 /* 116211 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41944 /* 116216 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41945 /* 116219 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
41946 /* 116222 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
41947 /* 116225 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41948 /* 116230 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41949 /* 116235 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41950 /* 116240 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41951 /* 116243 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd),
41952 /* 116247 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41953 /* 116252 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41954 /* 116255 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
41955 /* 116258 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41956 /* 116264 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
41957 /* 116266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41958 /* 116269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41959 /* 116271 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41960 /* 116278 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41961 /* 116283 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41962 /* 116288 */ // GIR_Coverage, 3101,
41963 /* 116288 */ GIR_EraseRootFromParent_Done,
41964 /* 116289 */ // Label 3511: @116289
41965 /* 116289 */ GIM_Reject,
41966 /* 116290 */ // Label 3509: @116290
41967 /* 116290 */ GIM_Reject,
41968 /* 116291 */ // Label 3502: @116291
41969 /* 116291 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3512*/ GIMT_Encode4(116349), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2611 //
41970 /* 116298 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
41971 /* 116301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41972 /* 116305 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
41973 /* 116309 */ // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VSITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
41974 /* 116309 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
41975 /* 116312 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41976 /* 116316 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41977 /* 116321 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
41978 /* 116325 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41979 /* 116330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOD),
41980 /* 116333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
41981 /* 116335 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41982 /* 116338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41983 /* 116341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41984 /* 116347 */ GIR_RootConstrainSelectedInstOperands,
41985 /* 116348 */ // GIR_Coverage, 2611,
41986 /* 116348 */ GIR_EraseRootFromParent_Done,
41987 /* 116349 */ // Label 3512: @116349
41988 /* 116349 */ GIM_Reject,
41989 /* 116350 */ // Label 3503: @116350
41990 /* 116350 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3513*/ GIMT_Encode4(116386), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1776 //
41991 /* 116357 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
41992 /* 116360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41993 /* 116364 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41994 /* 116368 */ // (sint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
41995 /* 116368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hd),
41996 /* 116371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41997 /* 116373 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
41998 /* 116375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41999 /* 116378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42000 /* 116384 */ GIR_RootConstrainSelectedInstOperands,
42001 /* 116385 */ // GIR_Coverage, 1776,
42002 /* 116385 */ GIR_EraseRootFromParent_Done,
42003 /* 116386 */ // Label 3513: @116386
42004 /* 116386 */ GIM_Reject,
42005 /* 116387 */ // Label 3504: @116387
42006 /* 116387 */ GIM_Try, /*On fail goto*//*Label 3514*/ GIMT_Encode4(116483),
42007 /* 116392 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42008 /* 116395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3515*/ GIMT_Encode4(116428), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1780 //
42009 /* 116402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42010 /* 116406 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42011 /* 116410 */ // (sint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
42012 /* 116410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hq),
42013 /* 116413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42014 /* 116415 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42015 /* 116417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42016 /* 116420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42017 /* 116426 */ GIR_RootConstrainSelectedInstOperands,
42018 /* 116427 */ // GIR_Coverage, 1780,
42019 /* 116427 */ GIR_EraseRootFromParent_Done,
42020 /* 116428 */ // Label 3515: @116428
42021 /* 116428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3516*/ GIMT_Encode4(116482), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4553 //
42022 /* 116435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42023 /* 116439 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42024 /* 116443 */ // (sint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
42025 /* 116443 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42026 /* 116446 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42027 /* 116450 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42028 /* 116455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n),
42029 /* 116458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42030 /* 116460 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42031 /* 116462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42032 /* 116465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42033 /* 116471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42034 /* 116477 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42035 /* 116480 */ GIR_RootConstrainSelectedInstOperands,
42036 /* 116481 */ // GIR_Coverage, 4553,
42037 /* 116481 */ GIR_EraseRootFromParent_Done,
42038 /* 116482 */ // Label 3516: @116482
42039 /* 116482 */ GIM_Reject,
42040 /* 116483 */ // Label 3514: @116483
42041 /* 116483 */ GIM_Reject,
42042 /* 116484 */ // Label 3505: @116484
42043 /* 116484 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3517*/ GIMT_Encode4(116520), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1768 //
42044 /* 116491 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
42045 /* 116494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42046 /* 116498 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42047 /* 116502 */ // (sint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
42048 /* 116502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd),
42049 /* 116505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42050 /* 116507 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42051 /* 116509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42052 /* 116512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42053 /* 116518 */ GIR_RootConstrainSelectedInstOperands,
42054 /* 116519 */ // GIR_Coverage, 1768,
42055 /* 116519 */ GIR_EraseRootFromParent_Done,
42056 /* 116520 */ // Label 3517: @116520
42057 /* 116520 */ GIM_Reject,
42058 /* 116521 */ // Label 3506: @116521
42059 /* 116521 */ GIM_Try, /*On fail goto*//*Label 3518*/ GIMT_Encode4(116617),
42060 /* 116526 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42061 /* 116529 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3519*/ GIMT_Encode4(116562), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1772 //
42062 /* 116536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42063 /* 116540 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42064 /* 116544 */ // (sint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
42065 /* 116544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fq),
42066 /* 116547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42067 /* 116549 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42068 /* 116551 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42069 /* 116554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42070 /* 116560 */ GIR_RootConstrainSelectedInstOperands,
42071 /* 116561 */ // GIR_Coverage, 1772,
42072 /* 116561 */ GIR_EraseRootFromParent_Done,
42073 /* 116562 */ // Label 3519: @116562
42074 /* 116562 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3520*/ GIMT_Encode4(116616), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4559 //
42075 /* 116569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42076 /* 116573 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42077 /* 116577 */ // (sint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
42078 /* 116577 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42079 /* 116580 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42080 /* 116584 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42081 /* 116589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n),
42082 /* 116592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42083 /* 116594 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42084 /* 116596 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42085 /* 116599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42086 /* 116605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42087 /* 116611 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42088 /* 116614 */ GIR_RootConstrainSelectedInstOperands,
42089 /* 116615 */ // GIR_Coverage, 4559,
42090 /* 116615 */ GIR_EraseRootFromParent_Done,
42091 /* 116616 */ // Label 3520: @116616
42092 /* 116616 */ GIM_Reject,
42093 /* 116617 */ // Label 3518: @116617
42094 /* 116617 */ GIM_Reject,
42095 /* 116618 */ // Label 3507: @116618
42096 /* 116618 */ GIM_Reject,
42097 /* 116619 */ // Label 51: @116619
42098 /* 116619 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3528*/ GIMT_Encode4(117260),
42099 /* 116630 */ /*GILLT_s16*//*Label 3521*/ GIMT_Encode4(116682),
42100 /* 116634 */ /*GILLT_s32*//*Label 3522*/ GIMT_Encode4(116741),
42101 /* 116638 */ /*GILLT_s64*//*Label 3523*/ GIMT_Encode4(116933), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
42102 /* 116666 */ /*GILLT_v4s16*//*Label 3524*/ GIMT_Encode4(116992),
42103 /* 116670 */ /*GILLT_v8s16*//*Label 3525*/ GIMT_Encode4(117029),
42104 /* 116674 */ /*GILLT_v2s32*//*Label 3526*/ GIMT_Encode4(117126),
42105 /* 116678 */ /*GILLT_v4s32*//*Label 3527*/ GIMT_Encode4(117163),
42106 /* 116682 */ // Label 3521: @116682
42107 /* 116682 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3529*/ GIMT_Encode4(116740), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2629 //
42108 /* 116689 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
42109 /* 116692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42110 /* 116696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42111 /* 116700 */ // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VUITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
42112 /* 116700 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42113 /* 116703 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42114 /* 116707 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42115 /* 116712 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42116 /* 116716 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42117 /* 116721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOH),
42118 /* 116724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42119 /* 116726 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42120 /* 116729 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42121 /* 116732 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42122 /* 116738 */ GIR_RootConstrainSelectedInstOperands,
42123 /* 116739 */ // GIR_Coverage, 2629,
42124 /* 116739 */ GIR_EraseRootFromParent_Done,
42125 /* 116740 */ // Label 3529: @116740
42126 /* 116740 */ GIM_Reject,
42127 /* 116741 */ // Label 3522: @116741
42128 /* 116741 */ GIM_Try, /*On fail goto*//*Label 3530*/ GIMT_Encode4(116932),
42129 /* 116746 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
42130 /* 116749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42131 /* 116753 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42132 /* 116757 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3531*/ GIMT_Encode4(116804), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 2625 //
42133 /* 116764 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VUITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
42134 /* 116764 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42135 /* 116767 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42136 /* 116771 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42137 /* 116776 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42138 /* 116780 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42139 /* 116785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOS),
42140 /* 116788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42141 /* 116790 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42142 /* 116793 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42143 /* 116796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42144 /* 116802 */ GIR_RootConstrainSelectedInstOperands,
42145 /* 116803 */ // GIR_Coverage, 2625,
42146 /* 116803 */ GIR_EraseRootFromParent_Done,
42147 /* 116804 */ // Label 3531: @116804
42148 /* 116804 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3532*/ GIMT_Encode4(116931), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3102 //
42149 /* 116811 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTu2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
42150 /* 116811 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
42151 /* 116814 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42152 /* 116818 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42153 /* 116823 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a
42154 /* 116827 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42155 /* 116832 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
42156 /* 116835 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42157 /* 116839 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42158 /* 116844 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
42159 /* 116846 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
42160 /* 116849 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
42161 /* 116853 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42162 /* 116858 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
42163 /* 116861 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
42164 /* 116864 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
42165 /* 116867 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42166 /* 116872 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42167 /* 116877 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
42168 /* 116882 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
42169 /* 116885 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd),
42170 /* 116889 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42171 /* 116894 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
42172 /* 116897 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
42173 /* 116900 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42174 /* 116906 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42175 /* 116908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42176 /* 116911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42177 /* 116913 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
42178 /* 116920 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42179 /* 116925 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42180 /* 116930 */ // GIR_Coverage, 3102,
42181 /* 116930 */ GIR_EraseRootFromParent_Done,
42182 /* 116931 */ // Label 3532: @116931
42183 /* 116931 */ GIM_Reject,
42184 /* 116932 */ // Label 3530: @116932
42185 /* 116932 */ GIM_Reject,
42186 /* 116933 */ // Label 3523: @116933
42187 /* 116933 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3533*/ GIMT_Encode4(116991), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2621 //
42188 /* 116940 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
42189 /* 116943 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42190 /* 116947 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42191 /* 116951 */ // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VUITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
42192 /* 116951 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42193 /* 116954 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42194 /* 116958 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42195 /* 116963 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42196 /* 116967 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42197 /* 116972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOD),
42198 /* 116975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42199 /* 116977 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42200 /* 116980 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42201 /* 116983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42202 /* 116989 */ GIR_RootConstrainSelectedInstOperands,
42203 /* 116990 */ // GIR_Coverage, 2621,
42204 /* 116990 */ GIR_EraseRootFromParent_Done,
42205 /* 116991 */ // Label 3533: @116991
42206 /* 116991 */ GIM_Reject,
42207 /* 116992 */ // Label 3524: @116992
42208 /* 116992 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3534*/ GIMT_Encode4(117028), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1777 //
42209 /* 116999 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
42210 /* 117002 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42211 /* 117006 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42212 /* 117010 */ // (uint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
42213 /* 117010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hd),
42214 /* 117013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42215 /* 117015 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42216 /* 117017 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42217 /* 117020 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42218 /* 117026 */ GIR_RootConstrainSelectedInstOperands,
42219 /* 117027 */ // GIR_Coverage, 1777,
42220 /* 117027 */ GIR_EraseRootFromParent_Done,
42221 /* 117028 */ // Label 3534: @117028
42222 /* 117028 */ GIM_Reject,
42223 /* 117029 */ // Label 3525: @117029
42224 /* 117029 */ GIM_Try, /*On fail goto*//*Label 3535*/ GIMT_Encode4(117125),
42225 /* 117034 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42226 /* 117037 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3536*/ GIMT_Encode4(117070), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1781 //
42227 /* 117044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42228 /* 117048 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42229 /* 117052 */ // (uint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
42230 /* 117052 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hq),
42231 /* 117055 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42232 /* 117057 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42233 /* 117059 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42234 /* 117062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42235 /* 117068 */ GIR_RootConstrainSelectedInstOperands,
42236 /* 117069 */ // GIR_Coverage, 1781,
42237 /* 117069 */ GIR_EraseRootFromParent_Done,
42238 /* 117070 */ // Label 3536: @117070
42239 /* 117070 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3537*/ GIMT_Encode4(117124), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4556 //
42240 /* 117077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42241 /* 117081 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42242 /* 117085 */ // (uint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
42243 /* 117085 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42244 /* 117088 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42245 /* 117092 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42246 /* 117097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n),
42247 /* 117100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42248 /* 117102 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42249 /* 117104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42250 /* 117107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42251 /* 117113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42252 /* 117119 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42253 /* 117122 */ GIR_RootConstrainSelectedInstOperands,
42254 /* 117123 */ // GIR_Coverage, 4556,
42255 /* 117123 */ GIR_EraseRootFromParent_Done,
42256 /* 117124 */ // Label 3537: @117124
42257 /* 117124 */ GIM_Reject,
42258 /* 117125 */ // Label 3535: @117125
42259 /* 117125 */ GIM_Reject,
42260 /* 117126 */ // Label 3526: @117126
42261 /* 117126 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3538*/ GIMT_Encode4(117162), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1769 //
42262 /* 117133 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
42263 /* 117136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42264 /* 117140 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42265 /* 117144 */ // (uint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
42266 /* 117144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd),
42267 /* 117147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42268 /* 117149 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42269 /* 117151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42270 /* 117154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42271 /* 117160 */ GIR_RootConstrainSelectedInstOperands,
42272 /* 117161 */ // GIR_Coverage, 1769,
42273 /* 117161 */ GIR_EraseRootFromParent_Done,
42274 /* 117162 */ // Label 3538: @117162
42275 /* 117162 */ GIM_Reject,
42276 /* 117163 */ // Label 3527: @117163
42277 /* 117163 */ GIM_Try, /*On fail goto*//*Label 3539*/ GIMT_Encode4(117259),
42278 /* 117168 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42279 /* 117171 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3540*/ GIMT_Encode4(117204), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1773 //
42280 /* 117178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42281 /* 117182 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42282 /* 117186 */ // (uint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
42283 /* 117186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fq),
42284 /* 117189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42285 /* 117191 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42286 /* 117193 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42287 /* 117196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42288 /* 117202 */ GIR_RootConstrainSelectedInstOperands,
42289 /* 117203 */ // GIR_Coverage, 1773,
42290 /* 117203 */ GIR_EraseRootFromParent_Done,
42291 /* 117204 */ // Label 3540: @117204
42292 /* 117204 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3541*/ GIMT_Encode4(117258), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4562 //
42293 /* 117211 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42294 /* 117215 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42295 /* 117219 */ // (uint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
42296 /* 117219 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42297 /* 117222 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42298 /* 117226 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42299 /* 117231 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n),
42300 /* 117234 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42301 /* 117236 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42302 /* 117238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42303 /* 117241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42304 /* 117247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42305 /* 117253 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42306 /* 117256 */ GIR_RootConstrainSelectedInstOperands,
42307 /* 117257 */ // GIR_Coverage, 4562,
42308 /* 117257 */ GIR_EraseRootFromParent_Done,
42309 /* 117258 */ // Label 3541: @117258
42310 /* 117258 */ GIM_Reject,
42311 /* 117259 */ // Label 3539: @117259
42312 /* 117259 */ GIM_Reject,
42313 /* 117260 */ // Label 3528: @117260
42314 /* 117260 */ GIM_Reject,
42315 /* 117261 */ // Label 52: @117261
42316 /* 117261 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3545*/ GIMT_Encode4(117623),
42317 /* 117272 */ /*GILLT_s32*//*Label 3542*/ GIMT_Encode4(117320), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
42318 /* 117308 */ /*GILLT_v8s16*//*Label 3543*/ GIMT_Encode4(117515), GIMT_Encode4(0),
42319 /* 117316 */ /*GILLT_v4s32*//*Label 3544*/ GIMT_Encode4(117569),
42320 /* 117320 */ // Label 3542: @117320
42321 /* 117320 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3549*/ GIMT_Encode4(117514),
42322 /* 117331 */ /*GILLT_s16*//*Label 3546*/ GIMT_Encode4(117343),
42323 /* 117335 */ /*GILLT_s32*//*Label 3547*/ GIMT_Encode4(117400),
42324 /* 117339 */ /*GILLT_s64*//*Label 3548*/ GIMT_Encode4(117457),
42325 /* 117343 */ // Label 3546: @117343
42326 /* 117343 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3550*/ GIMT_Encode4(117399), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2644 //
42327 /* 117350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42328 /* 117354 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42329 /* 117358 */ // (fp_to_sint_sat:{ *:[i32] } HPR:{ *:[f16] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
42330 /* 117358 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42331 /* 117361 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZH),
42332 /* 117365 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42333 /* 117370 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42334 /* 117374 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
42335 /* 117377 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42336 /* 117383 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42337 /* 117385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42338 /* 117388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42339 /* 117390 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42340 /* 117393 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
42341 /* 117398 */ // GIR_Coverage, 2644,
42342 /* 117398 */ GIR_EraseRootFromParent_Done,
42343 /* 117399 */ // Label 3550: @117399
42344 /* 117399 */ GIM_Reject,
42345 /* 117400 */ // Label 3547: @117400
42346 /* 117400 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3551*/ GIMT_Encode4(117456), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2638 //
42347 /* 117407 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42348 /* 117411 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42349 /* 117415 */ // (fp_to_sint_sat:{ *:[i32] } SPR:{ *:[f32] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
42350 /* 117415 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42351 /* 117418 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZS),
42352 /* 117422 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42353 /* 117427 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42354 /* 117431 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
42355 /* 117434 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42356 /* 117440 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42357 /* 117442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42358 /* 117445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42359 /* 117447 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42360 /* 117450 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
42361 /* 117455 */ // GIR_Coverage, 2638,
42362 /* 117455 */ GIR_EraseRootFromParent_Done,
42363 /* 117456 */ // Label 3551: @117456
42364 /* 117456 */ GIM_Reject,
42365 /* 117457 */ // Label 3548: @117457
42366 /* 117457 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3552*/ GIMT_Encode4(117513), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2632 //
42367 /* 117464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42368 /* 117468 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42369 /* 117472 */ // (fp_to_sint_sat:{ *:[i32] } DPR:{ *:[f64] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
42370 /* 117472 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42371 /* 117475 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZD),
42372 /* 117479 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42373 /* 117484 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42374 /* 117488 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
42375 /* 117491 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42376 /* 117497 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42377 /* 117499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42378 /* 117502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42379 /* 117504 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42380 /* 117507 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
42381 /* 117512 */ // GIR_Coverage, 2632,
42382 /* 117512 */ GIR_EraseRootFromParent_Done,
42383 /* 117513 */ // Label 3552: @117513
42384 /* 117513 */ GIM_Reject,
42385 /* 117514 */ // Label 3549: @117514
42386 /* 117514 */ GIM_Reject,
42387 /* 117515 */ // Label 3543: @117515
42388 /* 117515 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3553*/ GIMT_Encode4(117568), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4567 //
42389 /* 117522 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42390 /* 117525 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42391 /* 117529 */ // (fp_to_sint_sat:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, i16:{ *:[Other] }) => (MVE_VCVTs16f16z:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src)
42392 /* 117529 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42393 /* 117532 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42394 /* 117536 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42395 /* 117541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z),
42396 /* 117544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42397 /* 117546 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42398 /* 117548 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42399 /* 117551 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42400 /* 117557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42401 /* 117563 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42402 /* 117566 */ GIR_RootConstrainSelectedInstOperands,
42403 /* 117567 */ // GIR_Coverage, 4567,
42404 /* 117567 */ GIR_EraseRootFromParent_Done,
42405 /* 117568 */ // Label 3553: @117568
42406 /* 117568 */ GIM_Reject,
42407 /* 117569 */ // Label 3544: @117569
42408 /* 117569 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3554*/ GIMT_Encode4(117622), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4565 //
42409 /* 117576 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42410 /* 117579 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42411 /* 117583 */ // (fp_to_sint_sat:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, i32:{ *:[Other] }) => (MVE_VCVTs32f32z:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src)
42412 /* 117583 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42413 /* 117586 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42414 /* 117590 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42415 /* 117595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z),
42416 /* 117598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42417 /* 117600 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42418 /* 117602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42419 /* 117605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42420 /* 117611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42421 /* 117617 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42422 /* 117620 */ GIR_RootConstrainSelectedInstOperands,
42423 /* 117621 */ // GIR_Coverage, 4565,
42424 /* 117621 */ GIR_EraseRootFromParent_Done,
42425 /* 117622 */ // Label 3554: @117622
42426 /* 117622 */ GIM_Reject,
42427 /* 117623 */ // Label 3545: @117623
42428 /* 117623 */ GIM_Reject,
42429 /* 117624 */ // Label 53: @117624
42430 /* 117624 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3558*/ GIMT_Encode4(117986),
42431 /* 117635 */ /*GILLT_s32*//*Label 3555*/ GIMT_Encode4(117683), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
42432 /* 117671 */ /*GILLT_v8s16*//*Label 3556*/ GIMT_Encode4(117878), GIMT_Encode4(0),
42433 /* 117679 */ /*GILLT_v4s32*//*Label 3557*/ GIMT_Encode4(117932),
42434 /* 117683 */ // Label 3555: @117683
42435 /* 117683 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3562*/ GIMT_Encode4(117877),
42436 /* 117694 */ /*GILLT_s16*//*Label 3559*/ GIMT_Encode4(117706),
42437 /* 117698 */ /*GILLT_s32*//*Label 3560*/ GIMT_Encode4(117763),
42438 /* 117702 */ /*GILLT_s64*//*Label 3561*/ GIMT_Encode4(117820),
42439 /* 117706 */ // Label 3559: @117706
42440 /* 117706 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3563*/ GIMT_Encode4(117762), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2659 //
42441 /* 117713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42442 /* 117717 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42443 /* 117721 */ // (fp_to_uint_sat:{ *:[i32] } HPR:{ *:[f16] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
42444 /* 117721 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42445 /* 117724 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZH),
42446 /* 117728 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42447 /* 117733 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42448 /* 117737 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
42449 /* 117740 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42450 /* 117746 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42451 /* 117748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42452 /* 117751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42453 /* 117753 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42454 /* 117756 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
42455 /* 117761 */ // GIR_Coverage, 2659,
42456 /* 117761 */ GIR_EraseRootFromParent_Done,
42457 /* 117762 */ // Label 3563: @117762
42458 /* 117762 */ GIM_Reject,
42459 /* 117763 */ // Label 3560: @117763
42460 /* 117763 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3564*/ GIMT_Encode4(117819), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 2653 //
42461 /* 117770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42462 /* 117774 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42463 /* 117778 */ // (fp_to_uint_sat:{ *:[i32] } SPR:{ *:[f32] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
42464 /* 117778 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42465 /* 117781 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZS),
42466 /* 117785 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42467 /* 117790 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42468 /* 117794 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
42469 /* 117797 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42470 /* 117803 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42471 /* 117805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42472 /* 117808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42473 /* 117810 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42474 /* 117813 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
42475 /* 117818 */ // GIR_Coverage, 2653,
42476 /* 117818 */ GIR_EraseRootFromParent_Done,
42477 /* 117819 */ // Label 3564: @117819
42478 /* 117819 */ GIM_Reject,
42479 /* 117820 */ // Label 3561: @117820
42480 /* 117820 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3565*/ GIMT_Encode4(117876), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 2647 //
42481 /* 117827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
42482 /* 117831 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42483 /* 117835 */ // (fp_to_uint_sat:{ *:[i32] } DPR:{ *:[f64] }:$a, i32:{ *:[Other] }) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
42484 /* 117835 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
42485 /* 117838 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZD),
42486 /* 117842 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42487 /* 117847 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
42488 /* 117851 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
42489 /* 117854 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42490 /* 117860 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
42491 /* 117862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42492 /* 117865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42493 /* 117867 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42494 /* 117870 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
42495 /* 117875 */ // GIR_Coverage, 2647,
42496 /* 117875 */ GIR_EraseRootFromParent_Done,
42497 /* 117876 */ // Label 3565: @117876
42498 /* 117876 */ GIM_Reject,
42499 /* 117877 */ // Label 3562: @117877
42500 /* 117877 */ GIM_Reject,
42501 /* 117878 */ // Label 3556: @117878
42502 /* 117878 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3566*/ GIMT_Encode4(117931), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4568 //
42503 /* 117885 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42504 /* 117888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42505 /* 117892 */ // (fp_to_uint_sat:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src, i16:{ *:[Other] }) => (MVE_VCVTu16f16z:{ *:[v8i16] } v8f16:{ *:[v8f16] }:$src)
42506 /* 117892 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42507 /* 117895 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42508 /* 117899 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42509 /* 117904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z),
42510 /* 117907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42511 /* 117909 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42512 /* 117911 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42513 /* 117914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42514 /* 117920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42515 /* 117926 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42516 /* 117929 */ GIR_RootConstrainSelectedInstOperands,
42517 /* 117930 */ // GIR_Coverage, 4568,
42518 /* 117930 */ GIR_EraseRootFromParent_Done,
42519 /* 117931 */ // Label 3566: @117931
42520 /* 117931 */ GIM_Reject,
42521 /* 117932 */ // Label 3557: @117932
42522 /* 117932 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3567*/ GIMT_Encode4(117985), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4566 //
42523 /* 117939 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42524 /* 117942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42525 /* 117946 */ // (fp_to_uint_sat:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src, i32:{ *:[Other] }) => (MVE_VCVTu32f32z:{ *:[v4i32] } v4f32:{ *:[v4f32] }:$src)
42526 /* 117946 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42527 /* 117949 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42528 /* 117953 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42529 /* 117958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z),
42530 /* 117961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42531 /* 117963 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
42532 /* 117965 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42533 /* 117968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42534 /* 117974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42535 /* 117980 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42536 /* 117983 */ GIR_RootConstrainSelectedInstOperands,
42537 /* 117984 */ // GIR_Coverage, 4566,
42538 /* 117984 */ GIR_EraseRootFromParent_Done,
42539 /* 117985 */ // Label 3567: @117985
42540 /* 117985 */ GIM_Reject,
42541 /* 117986 */ // Label 3558: @117986
42542 /* 117986 */ GIM_Reject,
42543 /* 117987 */ // Label 54: @117987
42544 /* 117987 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3575*/ GIMT_Encode4(118750),
42545 /* 117998 */ /*GILLT_s16*//*Label 3568*/ GIMT_Encode4(118050),
42546 /* 118002 */ /*GILLT_s32*//*Label 3569*/ GIMT_Encode4(118087),
42547 /* 118006 */ /*GILLT_s64*//*Label 3570*/ GIMT_Encode4(118277), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
42548 /* 118034 */ /*GILLT_v4s16*//*Label 3571*/ GIMT_Encode4(118314),
42549 /* 118038 */ /*GILLT_v8s16*//*Label 3572*/ GIMT_Encode4(118351),
42550 /* 118042 */ /*GILLT_v2s32*//*Label 3573*/ GIMT_Encode4(118532),
42551 /* 118046 */ /*GILLT_v4s32*//*Label 3574*/ GIMT_Encode4(118569),
42552 /* 118050 */ // Label 3568: @118050
42553 /* 118050 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3576*/ GIMT_Encode4(118086), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 678 //
42554 /* 118057 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
42555 /* 118060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42556 /* 118064 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42557 /* 118068 */ // (fabs:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VABSH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
42558 /* 118068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSH),
42559 /* 118071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42560 /* 118073 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
42561 /* 118075 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42562 /* 118078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42563 /* 118084 */ GIR_RootConstrainSelectedInstOperands,
42564 /* 118085 */ // GIR_Coverage, 678,
42565 /* 118085 */ GIR_EraseRootFromParent_Done,
42566 /* 118086 */ // Label 3576: @118086
42567 /* 118086 */ GIM_Reject,
42568 /* 118087 */ // Label 3569: @118087
42569 /* 118087 */ GIM_Try, /*On fail goto*//*Label 3577*/ GIMT_Encode4(118276),
42570 /* 118092 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
42571 /* 118095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42572 /* 118099 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42573 /* 118103 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3578*/ GIMT_Encode4(118128), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 677 //
42574 /* 118110 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VABSS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
42575 /* 118110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSS),
42576 /* 118113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42577 /* 118115 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
42578 /* 118117 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42579 /* 118120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42580 /* 118126 */ GIR_RootConstrainSelectedInstOperands,
42581 /* 118127 */ // GIR_Coverage, 677,
42582 /* 118127 */ GIR_EraseRootFromParent_Done,
42583 /* 118128 */ // Label 3578: @118128
42584 /* 118128 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3579*/ GIMT_Encode4(118275), GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP), // Rule ID 3093 //
42585 /* 118135 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VABSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
42586 /* 118135 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
42587 /* 118138 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42588 /* 118142 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42589 /* 118147 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
42590 /* 118149 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
42591 /* 118152 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42592 /* 118156 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42593 /* 118161 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
42594 /* 118164 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42595 /* 118169 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
42596 /* 118172 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
42597 /* 118176 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42598 /* 118181 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
42599 /* 118184 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
42600 /* 118188 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
42601 /* 118191 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42602 /* 118196 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42603 /* 118201 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
42604 /* 118206 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
42605 /* 118209 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VABSfd),
42606 /* 118213 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42607 /* 118218 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
42608 /* 118221 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
42609 /* 118224 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42610 /* 118230 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42611 /* 118232 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
42612 /* 118235 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42613 /* 118239 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42614 /* 118244 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
42615 /* 118247 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42616 /* 118252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42617 /* 118255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42618 /* 118257 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
42619 /* 118264 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42620 /* 118269 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42621 /* 118274 */ // GIR_Coverage, 3093,
42622 /* 118274 */ GIR_EraseRootFromParent_Done,
42623 /* 118275 */ // Label 3579: @118275
42624 /* 118275 */ GIM_Reject,
42625 /* 118276 */ // Label 3577: @118276
42626 /* 118276 */ GIM_Reject,
42627 /* 118277 */ // Label 3570: @118277
42628 /* 118277 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3580*/ GIMT_Encode4(118313), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 676 //
42629 /* 118284 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
42630 /* 118287 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42631 /* 118291 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42632 /* 118295 */ // (fabs:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VABSD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
42633 /* 118295 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSD),
42634 /* 118298 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42635 /* 118300 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
42636 /* 118302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42637 /* 118305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42638 /* 118311 */ GIR_RootConstrainSelectedInstOperands,
42639 /* 118312 */ // GIR_Coverage, 676,
42640 /* 118312 */ GIR_EraseRootFromParent_Done,
42641 /* 118313 */ // Label 3580: @118313
42642 /* 118313 */ GIM_Reject,
42643 /* 118314 */ // Label 3571: @118314
42644 /* 118314 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3581*/ GIMT_Encode4(118350), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1678 //
42645 /* 118321 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
42646 /* 118324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42647 /* 118328 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42648 /* 118332 */ // (fabs:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VABShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
42649 /* 118332 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShd),
42650 /* 118335 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42651 /* 118337 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42652 /* 118339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42653 /* 118342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42654 /* 118348 */ GIR_RootConstrainSelectedInstOperands,
42655 /* 118349 */ // GIR_Coverage, 1678,
42656 /* 118349 */ GIR_EraseRootFromParent_Done,
42657 /* 118350 */ // Label 3581: @118350
42658 /* 118350 */ GIM_Reject,
42659 /* 118351 */ // Label 3572: @118351
42660 /* 118351 */ GIM_Try, /*On fail goto*//*Label 3582*/ GIMT_Encode4(118531),
42661 /* 118356 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42662 /* 118359 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3583*/ GIMT_Encode4(118443), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4491 //
42663 /* 118366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42664 /* 118370 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42665 /* 118374 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
42666 /* 118378 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
42667 /* 118382 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
42668 /* 118386 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42669 /* 118391 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42670 /* 118396 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42671 /* 118398 */ // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
42672 /* 118398 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42673 /* 118401 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42674 /* 118405 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42675 /* 118410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16),
42676 /* 118413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42677 /* 118415 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
42678 /* 118419 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn
42679 /* 118423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42680 /* 118426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42681 /* 118432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42682 /* 118438 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42683 /* 118441 */ GIR_RootConstrainSelectedInstOperands,
42684 /* 118442 */ // GIR_Coverage, 4491,
42685 /* 118442 */ GIR_EraseRootFromParent_Done,
42686 /* 118443 */ // Label 3583: @118443
42687 /* 118443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3584*/ GIMT_Encode4(118476), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1679 //
42688 /* 118450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42689 /* 118454 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42690 /* 118458 */ // (fabs:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VABShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
42691 /* 118458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShq),
42692 /* 118461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42693 /* 118463 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42694 /* 118465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42695 /* 118468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42696 /* 118474 */ GIR_RootConstrainSelectedInstOperands,
42697 /* 118475 */ // GIR_Coverage, 1679,
42698 /* 118475 */ GIR_EraseRootFromParent_Done,
42699 /* 118476 */ // Label 3584: @118476
42700 /* 118476 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3585*/ GIMT_Encode4(118530), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4569 //
42701 /* 118483 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42702 /* 118487 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42703 /* 118491 */ // (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VABSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v)
42704 /* 118491 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42705 /* 118494 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42706 /* 118498 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42707 /* 118503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf16),
42708 /* 118506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42709 /* 118508 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
42710 /* 118510 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42711 /* 118513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42712 /* 118519 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42713 /* 118525 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42714 /* 118528 */ GIR_RootConstrainSelectedInstOperands,
42715 /* 118529 */ // GIR_Coverage, 4569,
42716 /* 118529 */ GIR_EraseRootFromParent_Done,
42717 /* 118530 */ // Label 3585: @118530
42718 /* 118530 */ GIM_Reject,
42719 /* 118531 */ // Label 3582: @118531
42720 /* 118531 */ GIM_Reject,
42721 /* 118532 */ // Label 3573: @118532
42722 /* 118532 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3586*/ GIMT_Encode4(118568), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1676 //
42723 /* 118539 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
42724 /* 118542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42725 /* 118546 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42726 /* 118550 */ // (fabs:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VABSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
42727 /* 118550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfd),
42728 /* 118553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42729 /* 118555 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42730 /* 118557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42731 /* 118560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42732 /* 118566 */ GIR_RootConstrainSelectedInstOperands,
42733 /* 118567 */ // GIR_Coverage, 1676,
42734 /* 118567 */ GIR_EraseRootFromParent_Done,
42735 /* 118568 */ // Label 3586: @118568
42736 /* 118568 */ GIM_Reject,
42737 /* 118569 */ // Label 3574: @118569
42738 /* 118569 */ GIM_Try, /*On fail goto*//*Label 3587*/ GIMT_Encode4(118749),
42739 /* 118574 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42740 /* 118577 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3588*/ GIMT_Encode4(118661), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4492 //
42741 /* 118584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42742 /* 118588 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42743 /* 118592 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
42744 /* 118596 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
42745 /* 118600 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
42746 /* 118604 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42747 /* 118609 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42748 /* 118614 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42749 /* 118616 */ // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
42750 /* 118616 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42751 /* 118619 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42752 /* 118623 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42753 /* 118628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32),
42754 /* 118631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42755 /* 118633 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
42756 /* 118637 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn
42757 /* 118641 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42758 /* 118644 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42759 /* 118650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42760 /* 118656 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42761 /* 118659 */ GIR_RootConstrainSelectedInstOperands,
42762 /* 118660 */ // GIR_Coverage, 4492,
42763 /* 118660 */ GIR_EraseRootFromParent_Done,
42764 /* 118661 */ // Label 3588: @118661
42765 /* 118661 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3589*/ GIMT_Encode4(118694), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1677 //
42766 /* 118668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42767 /* 118672 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42768 /* 118676 */ // (fabs:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VABSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
42769 /* 118676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfq),
42770 /* 118679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42771 /* 118681 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
42772 /* 118683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42773 /* 118686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42774 /* 118692 */ GIR_RootConstrainSelectedInstOperands,
42775 /* 118693 */ // GIR_Coverage, 1677,
42776 /* 118693 */ GIR_EraseRootFromParent_Done,
42777 /* 118694 */ // Label 3589: @118694
42778 /* 118694 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3590*/ GIMT_Encode4(118748), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4571 //
42779 /* 118701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42780 /* 118705 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42781 /* 118709 */ // (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VABSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v)
42782 /* 118709 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42783 /* 118712 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42784 /* 118716 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42785 /* 118721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf32),
42786 /* 118724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42787 /* 118726 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
42788 /* 118728 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42789 /* 118731 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42790 /* 118737 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42791 /* 118743 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42792 /* 118746 */ GIR_RootConstrainSelectedInstOperands,
42793 /* 118747 */ // GIR_Coverage, 4571,
42794 /* 118747 */ GIR_EraseRootFromParent_Done,
42795 /* 118748 */ // Label 3590: @118748
42796 /* 118748 */ GIM_Reject,
42797 /* 118749 */ // Label 3587: @118749
42798 /* 118749 */ GIM_Reject,
42799 /* 118750 */ // Label 3575: @118750
42800 /* 118750 */ GIM_Reject,
42801 /* 118751 */ // Label 55: @118751
42802 /* 118751 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3598*/ GIMT_Encode4(119331),
42803 /* 118762 */ /*GILLT_s16*//*Label 3591*/ GIMT_Encode4(118814),
42804 /* 118766 */ /*GILLT_s32*//*Label 3592*/ GIMT_Encode4(118847),
42805 /* 118770 */ /*GILLT_s64*//*Label 3593*/ GIMT_Encode4(118880), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
42806 /* 118798 */ /*GILLT_v4s16*//*Label 3594*/ GIMT_Encode4(118913),
42807 /* 118802 */ /*GILLT_v8s16*//*Label 3595*/ GIMT_Encode4(118946),
42808 /* 118806 */ /*GILLT_v2s32*//*Label 3596*/ GIMT_Encode4(119122),
42809 /* 118810 */ /*GILLT_v4s32*//*Label 3597*/ GIMT_Encode4(119155),
42810 /* 118814 */ // Label 3591: @118814
42811 /* 118814 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3599*/ GIMT_Encode4(118846), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 665 //
42812 /* 118821 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
42813 /* 118824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
42814 /* 118827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42815 /* 118831 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42816 /* 118835 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42817 /* 118839 */ // (fminnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMINNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42818 /* 118839 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMH),
42819 /* 118844 */ GIR_RootConstrainSelectedInstOperands,
42820 /* 118845 */ // GIR_Coverage, 665,
42821 /* 118845 */ GIR_Done,
42822 /* 118846 */ // Label 3599: @118846
42823 /* 118846 */ GIM_Reject,
42824 /* 118847 */ // Label 3592: @118847
42825 /* 118847 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3600*/ GIMT_Encode4(118879), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 667 //
42826 /* 118854 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
42827 /* 118857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
42828 /* 118860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42829 /* 118864 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42830 /* 118868 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42831 /* 118872 */ // (fminnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMINNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42832 /* 118872 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMS),
42833 /* 118877 */ GIR_RootConstrainSelectedInstOperands,
42834 /* 118878 */ // GIR_Coverage, 667,
42835 /* 118878 */ GIR_Done,
42836 /* 118879 */ // Label 3600: @118879
42837 /* 118879 */ GIM_Reject,
42838 /* 118880 */ // Label 3593: @118880
42839 /* 118880 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3601*/ GIMT_Encode4(118912), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 669 //
42840 /* 118887 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
42841 /* 118890 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
42842 /* 118893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42843 /* 118897 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42844 /* 118901 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42845 /* 118905 */ // (fminnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMINNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42846 /* 118905 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMD),
42847 /* 118910 */ GIR_RootConstrainSelectedInstOperands,
42848 /* 118911 */ // GIR_Coverage, 669,
42849 /* 118911 */ GIR_Done,
42850 /* 118912 */ // Label 3601: @118912
42851 /* 118912 */ GIM_Reject,
42852 /* 118913 */ // Label 3594: @118913
42853 /* 118913 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3602*/ GIMT_Encode4(118945), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1397 //
42854 /* 118920 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
42855 /* 118923 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
42856 /* 118926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42857 /* 118930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42858 /* 118934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42859 /* 118938 */ // (fminnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMINNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
42860 /* 118938 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDh),
42861 /* 118943 */ GIR_RootConstrainSelectedInstOperands,
42862 /* 118944 */ // GIR_Coverage, 1397,
42863 /* 118944 */ GIR_Done,
42864 /* 118945 */ // Label 3602: @118945
42865 /* 118945 */ GIM_Reject,
42866 /* 118946 */ // Label 3595: @118946
42867 /* 118946 */ GIM_Try, /*On fail goto*//*Label 3603*/ GIMT_Encode4(119121),
42868 /* 118951 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42869 /* 118954 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
42870 /* 118957 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3604*/ GIMT_Encode4(119034), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4586 //
42871 /* 118964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42872 /* 118968 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42873 /* 118972 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
42874 /* 118976 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
42875 /* 118980 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42876 /* 118985 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
42877 /* 118989 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
42878 /* 118993 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
42879 /* 118997 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42880 /* 119002 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
42881 /* 119004 */ // (fminnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
42882 /* 119004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16),
42883 /* 119007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42884 /* 119009 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
42885 /* 119013 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
42886 /* 119017 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42887 /* 119020 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42888 /* 119026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42889 /* 119032 */ GIR_RootConstrainSelectedInstOperands,
42890 /* 119033 */ // GIR_Coverage, 4586,
42891 /* 119033 */ GIR_EraseRootFromParent_Done,
42892 /* 119034 */ // Label 3604: @119034
42893 /* 119034 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3605*/ GIMT_Encode4(119060), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1398 //
42894 /* 119041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42895 /* 119045 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42896 /* 119049 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42897 /* 119053 */ // (fminnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMINNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
42898 /* 119053 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQh),
42899 /* 119058 */ GIR_RootConstrainSelectedInstOperands,
42900 /* 119059 */ // GIR_Coverage, 1398,
42901 /* 119059 */ GIR_Done,
42902 /* 119060 */ // Label 3605: @119060
42903 /* 119060 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3606*/ GIMT_Encode4(119120), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3686 //
42904 /* 119067 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42905 /* 119071 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42906 /* 119075 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42907 /* 119079 */ // (fminnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
42908 /* 119079 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42909 /* 119082 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42910 /* 119086 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42911 /* 119091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16),
42912 /* 119094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42913 /* 119096 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
42914 /* 119098 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
42915 /* 119100 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42916 /* 119103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42917 /* 119109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42918 /* 119115 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42919 /* 119118 */ GIR_RootConstrainSelectedInstOperands,
42920 /* 119119 */ // GIR_Coverage, 3686,
42921 /* 119119 */ GIR_EraseRootFromParent_Done,
42922 /* 119120 */ // Label 3606: @119120
42923 /* 119120 */ GIM_Reject,
42924 /* 119121 */ // Label 3603: @119121
42925 /* 119121 */ GIM_Reject,
42926 /* 119122 */ // Label 3596: @119122
42927 /* 119122 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3607*/ GIMT_Encode4(119154), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1395 //
42928 /* 119129 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
42929 /* 119132 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42930 /* 119135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42931 /* 119139 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42932 /* 119143 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42933 /* 119147 */ // (fminnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMINNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
42934 /* 119147 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDf),
42935 /* 119152 */ GIR_RootConstrainSelectedInstOperands,
42936 /* 119153 */ // GIR_Coverage, 1395,
42937 /* 119153 */ GIR_Done,
42938 /* 119154 */ // Label 3607: @119154
42939 /* 119154 */ GIM_Reject,
42940 /* 119155 */ // Label 3597: @119155
42941 /* 119155 */ GIM_Try, /*On fail goto*//*Label 3608*/ GIMT_Encode4(119330),
42942 /* 119160 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42943 /* 119163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42944 /* 119166 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3609*/ GIMT_Encode4(119243), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4583 //
42945 /* 119173 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42946 /* 119177 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42947 /* 119181 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
42948 /* 119185 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
42949 /* 119189 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42950 /* 119194 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
42951 /* 119198 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
42952 /* 119202 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
42953 /* 119206 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42954 /* 119211 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
42955 /* 119213 */ // (fminnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
42956 /* 119213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32),
42957 /* 119216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42958 /* 119218 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
42959 /* 119222 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
42960 /* 119226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42961 /* 119229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42962 /* 119235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42963 /* 119241 */ GIR_RootConstrainSelectedInstOperands,
42964 /* 119242 */ // GIR_Coverage, 4583,
42965 /* 119242 */ GIR_EraseRootFromParent_Done,
42966 /* 119243 */ // Label 3609: @119243
42967 /* 119243 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3610*/ GIMT_Encode4(119269), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1396 //
42968 /* 119250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42969 /* 119254 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42970 /* 119258 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42971 /* 119262 */ // (fminnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMINNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
42972 /* 119262 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQf),
42973 /* 119267 */ GIR_RootConstrainSelectedInstOperands,
42974 /* 119268 */ // GIR_Coverage, 1396,
42975 /* 119268 */ GIR_Done,
42976 /* 119269 */ // Label 3610: @119269
42977 /* 119269 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3611*/ GIMT_Encode4(119329), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3681 //
42978 /* 119276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42979 /* 119280 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42980 /* 119284 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42981 /* 119288 */ // (fminnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
42982 /* 119288 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42983 /* 119291 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42984 /* 119295 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42985 /* 119300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32),
42986 /* 119303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42987 /* 119305 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
42988 /* 119307 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
42989 /* 119309 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42990 /* 119312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42991 /* 119318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42992 /* 119324 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42993 /* 119327 */ GIR_RootConstrainSelectedInstOperands,
42994 /* 119328 */ // GIR_Coverage, 3681,
42995 /* 119328 */ GIR_EraseRootFromParent_Done,
42996 /* 119329 */ // Label 3611: @119329
42997 /* 119329 */ GIM_Reject,
42998 /* 119330 */ // Label 3608: @119330
42999 /* 119330 */ GIM_Reject,
43000 /* 119331 */ // Label 3598: @119331
43001 /* 119331 */ GIM_Reject,
43002 /* 119332 */ // Label 56: @119332
43003 /* 119332 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3619*/ GIMT_Encode4(119912),
43004 /* 119343 */ /*GILLT_s16*//*Label 3612*/ GIMT_Encode4(119395),
43005 /* 119347 */ /*GILLT_s32*//*Label 3613*/ GIMT_Encode4(119428),
43006 /* 119351 */ /*GILLT_s64*//*Label 3614*/ GIMT_Encode4(119461), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
43007 /* 119379 */ /*GILLT_v4s16*//*Label 3615*/ GIMT_Encode4(119494),
43008 /* 119383 */ /*GILLT_v8s16*//*Label 3616*/ GIMT_Encode4(119527),
43009 /* 119387 */ /*GILLT_v2s32*//*Label 3617*/ GIMT_Encode4(119703),
43010 /* 119391 */ /*GILLT_v4s32*//*Label 3618*/ GIMT_Encode4(119736),
43011 /* 119395 */ // Label 3612: @119395
43012 /* 119395 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3620*/ GIMT_Encode4(119427), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 659 //
43013 /* 119402 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
43014 /* 119405 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
43015 /* 119408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43016 /* 119412 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43017 /* 119416 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43018 /* 119420 */ // (fmaxnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMAXNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43019 /* 119420 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMH),
43020 /* 119425 */ GIR_RootConstrainSelectedInstOperands,
43021 /* 119426 */ // GIR_Coverage, 659,
43022 /* 119426 */ GIR_Done,
43023 /* 119427 */ // Label 3620: @119427
43024 /* 119427 */ GIM_Reject,
43025 /* 119428 */ // Label 3613: @119428
43026 /* 119428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3621*/ GIMT_Encode4(119460), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 661 //
43027 /* 119435 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
43028 /* 119438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
43029 /* 119441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43030 /* 119445 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43031 /* 119449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43032 /* 119453 */ // (fmaxnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMAXNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43033 /* 119453 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMS),
43034 /* 119458 */ GIR_RootConstrainSelectedInstOperands,
43035 /* 119459 */ // GIR_Coverage, 661,
43036 /* 119459 */ GIR_Done,
43037 /* 119460 */ // Label 3621: @119460
43038 /* 119460 */ GIM_Reject,
43039 /* 119461 */ // Label 3614: @119461
43040 /* 119461 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3622*/ GIMT_Encode4(119493), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 663 //
43041 /* 119468 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
43042 /* 119471 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
43043 /* 119474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43044 /* 119478 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43045 /* 119482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43046 /* 119486 */ // (fmaxnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMAXNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43047 /* 119486 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMD),
43048 /* 119491 */ GIR_RootConstrainSelectedInstOperands,
43049 /* 119492 */ // GIR_Coverage, 663,
43050 /* 119492 */ GIR_Done,
43051 /* 119493 */ // Label 3622: @119493
43052 /* 119493 */ GIM_Reject,
43053 /* 119494 */ // Label 3615: @119494
43054 /* 119494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3623*/ GIMT_Encode4(119526), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1377 //
43055 /* 119501 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
43056 /* 119504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43057 /* 119507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43058 /* 119511 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43059 /* 119515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43060 /* 119519 */ // (fmaxnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMAXNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
43061 /* 119519 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDh),
43062 /* 119524 */ GIR_RootConstrainSelectedInstOperands,
43063 /* 119525 */ // GIR_Coverage, 1377,
43064 /* 119525 */ GIR_Done,
43065 /* 119526 */ // Label 3623: @119526
43066 /* 119526 */ GIM_Reject,
43067 /* 119527 */ // Label 3616: @119527
43068 /* 119527 */ GIM_Try, /*On fail goto*//*Label 3624*/ GIMT_Encode4(119702),
43069 /* 119532 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
43070 /* 119535 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43071 /* 119538 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3625*/ GIMT_Encode4(119615), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4580 //
43072 /* 119545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43073 /* 119549 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43074 /* 119553 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
43075 /* 119557 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
43076 /* 119561 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43077 /* 119566 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
43078 /* 119570 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
43079 /* 119574 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
43080 /* 119578 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43081 /* 119583 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43082 /* 119585 */ // (fmaxnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
43083 /* 119585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16),
43084 /* 119588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43085 /* 119590 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
43086 /* 119594 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
43087 /* 119598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43088 /* 119601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43089 /* 119607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43090 /* 119613 */ GIR_RootConstrainSelectedInstOperands,
43091 /* 119614 */ // GIR_Coverage, 4580,
43092 /* 119614 */ GIR_EraseRootFromParent_Done,
43093 /* 119615 */ // Label 3625: @119615
43094 /* 119615 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3626*/ GIMT_Encode4(119641), GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON), // Rule ID 1378 //
43095 /* 119622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43096 /* 119626 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43097 /* 119630 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43098 /* 119634 */ // (fmaxnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMAXNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
43099 /* 119634 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQh),
43100 /* 119639 */ GIR_RootConstrainSelectedInstOperands,
43101 /* 119640 */ // GIR_Coverage, 1378,
43102 /* 119640 */ GIR_Done,
43103 /* 119641 */ // Label 3626: @119641
43104 /* 119641 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3627*/ GIMT_Encode4(119701), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3676 //
43105 /* 119648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43106 /* 119652 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43107 /* 119656 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43108 /* 119660 */ // (fmaxnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
43109 /* 119660 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43110 /* 119663 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43111 /* 119667 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43112 /* 119672 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16),
43113 /* 119675 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43114 /* 119677 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
43115 /* 119679 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
43116 /* 119681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43117 /* 119684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43118 /* 119690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43119 /* 119696 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43120 /* 119699 */ GIR_RootConstrainSelectedInstOperands,
43121 /* 119700 */ // GIR_Coverage, 3676,
43122 /* 119700 */ GIR_EraseRootFromParent_Done,
43123 /* 119701 */ // Label 3627: @119701
43124 /* 119701 */ GIM_Reject,
43125 /* 119702 */ // Label 3624: @119702
43126 /* 119702 */ GIM_Reject,
43127 /* 119703 */ // Label 3617: @119703
43128 /* 119703 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3628*/ GIMT_Encode4(119735), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1375 //
43129 /* 119710 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
43130 /* 119713 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43131 /* 119716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43132 /* 119720 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43133 /* 119724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43134 /* 119728 */ // (fmaxnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMAXNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
43135 /* 119728 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDf),
43136 /* 119733 */ GIR_RootConstrainSelectedInstOperands,
43137 /* 119734 */ // GIR_Coverage, 1375,
43138 /* 119734 */ GIR_Done,
43139 /* 119735 */ // Label 3628: @119735
43140 /* 119735 */ GIM_Reject,
43141 /* 119736 */ // Label 3618: @119736
43142 /* 119736 */ GIM_Try, /*On fail goto*//*Label 3629*/ GIMT_Encode4(119911),
43143 /* 119741 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
43144 /* 119744 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43145 /* 119747 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3630*/ GIMT_Encode4(119824), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4577 //
43146 /* 119754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43147 /* 119758 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43148 /* 119762 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
43149 /* 119766 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
43150 /* 119770 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43151 /* 119775 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
43152 /* 119779 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
43153 /* 119783 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
43154 /* 119787 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43155 /* 119792 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43156 /* 119794 */ // (fmaxnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
43157 /* 119794 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32),
43158 /* 119797 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43159 /* 119799 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
43160 /* 119803 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
43161 /* 119807 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43162 /* 119810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43163 /* 119816 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43164 /* 119822 */ GIR_RootConstrainSelectedInstOperands,
43165 /* 119823 */ // GIR_Coverage, 4577,
43166 /* 119823 */ GIR_EraseRootFromParent_Done,
43167 /* 119824 */ // Label 3630: @119824
43168 /* 119824 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3631*/ GIMT_Encode4(119850), GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON), // Rule ID 1376 //
43169 /* 119831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43170 /* 119835 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43171 /* 119839 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43172 /* 119843 */ // (fmaxnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMAXNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
43173 /* 119843 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQf),
43174 /* 119848 */ GIR_RootConstrainSelectedInstOperands,
43175 /* 119849 */ // GIR_Coverage, 1376,
43176 /* 119849 */ GIR_Done,
43177 /* 119850 */ // Label 3631: @119850
43178 /* 119850 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3632*/ GIMT_Encode4(119910), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 3419 //
43179 /* 119857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43180 /* 119861 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43181 /* 119865 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43182 /* 119869 */ // (fmaxnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
43183 /* 119869 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43184 /* 119872 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43185 /* 119876 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43186 /* 119881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32),
43187 /* 119884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43188 /* 119886 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
43189 /* 119888 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
43190 /* 119890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43191 /* 119893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43192 /* 119899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43193 /* 119905 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43194 /* 119908 */ GIR_RootConstrainSelectedInstOperands,
43195 /* 119909 */ // GIR_Coverage, 3419,
43196 /* 119909 */ GIR_EraseRootFromParent_Done,
43197 /* 119910 */ // Label 3632: @119910
43198 /* 119910 */ GIM_Reject,
43199 /* 119911 */ // Label 3629: @119911
43200 /* 119911 */ GIM_Reject,
43201 /* 119912 */ // Label 3619: @119912
43202 /* 119912 */ GIM_Reject,
43203 /* 119913 */ // Label 57: @119913
43204 /* 119913 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3639*/ GIMT_Encode4(120640),
43205 /* 119924 */ /*GILLT_s16*//*Label 3633*/ GIMT_Encode4(119976),
43206 /* 119928 */ /*GILLT_s32*//*Label 3634*/ GIMT_Encode4(120216), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
43207 /* 119960 */ /*GILLT_v4s16*//*Label 3635*/ GIMT_Encode4(120456),
43208 /* 119964 */ /*GILLT_v8s16*//*Label 3636*/ GIMT_Encode4(120502),
43209 /* 119968 */ /*GILLT_v2s32*//*Label 3637*/ GIMT_Encode4(120548),
43210 /* 119972 */ /*GILLT_v4s32*//*Label 3638*/ GIMT_Encode4(120594),
43211 /* 119976 */ // Label 3633: @119976
43212 /* 119976 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3640*/ GIMT_Encode4(120215), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 3096 //
43213 /* 119983 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
43214 /* 119986 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
43215 /* 119989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43216 /* 119993 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43217 /* 119997 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43218 /* 120001 */ // (fminimum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMINhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
43219 /* 120001 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
43220 /* 120004 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43221 /* 120008 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43222 /* 120013 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
43223 /* 120015 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
43224 /* 120018 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43225 /* 120022 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43226 /* 120027 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
43227 /* 120030 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43228 /* 120035 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
43229 /* 120038 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43230 /* 120042 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43231 /* 120047 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
43232 /* 120050 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
43233 /* 120054 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
43234 /* 120057 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43235 /* 120062 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43236 /* 120067 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
43237 /* 120072 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
43238 /* 120075 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43239 /* 120079 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43240 /* 120084 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
43241 /* 120086 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
43242 /* 120089 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43243 /* 120093 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43244 /* 120098 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
43245 /* 120101 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43246 /* 120106 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
43247 /* 120109 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43248 /* 120113 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43249 /* 120118 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
43250 /* 120121 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
43251 /* 120125 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
43252 /* 120128 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43253 /* 120133 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43254 /* 120138 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
43255 /* 120143 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
43256 /* 120146 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINhd),
43257 /* 120150 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43258 /* 120155 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
43259 /* 120158 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
43260 /* 120161 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
43261 /* 120164 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43262 /* 120170 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43263 /* 120172 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
43264 /* 120175 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43265 /* 120179 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43266 /* 120184 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
43267 /* 120187 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43268 /* 120192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43269 /* 120195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43270 /* 120197 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
43271 /* 120204 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
43272 /* 120209 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43273 /* 120214 */ // GIR_Coverage, 3096,
43274 /* 120214 */ GIR_EraseRootFromParent_Done,
43275 /* 120215 */ // Label 3640: @120215
43276 /* 120215 */ GIM_Reject,
43277 /* 120216 */ // Label 3634: @120216
43278 /* 120216 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3641*/ GIMT_Encode4(120455), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3098 //
43279 /* 120223 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
43280 /* 120226 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
43281 /* 120229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43282 /* 120233 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43283 /* 120237 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43284 /* 120241 */ // (fminimum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMINfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
43285 /* 120241 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
43286 /* 120244 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43287 /* 120248 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43288 /* 120253 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
43289 /* 120255 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
43290 /* 120258 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43291 /* 120262 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43292 /* 120267 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
43293 /* 120270 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43294 /* 120275 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
43295 /* 120278 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43296 /* 120282 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43297 /* 120287 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
43298 /* 120290 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
43299 /* 120294 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
43300 /* 120297 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43301 /* 120302 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43302 /* 120307 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
43303 /* 120312 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
43304 /* 120315 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43305 /* 120319 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43306 /* 120324 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
43307 /* 120326 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
43308 /* 120329 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43309 /* 120333 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43310 /* 120338 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
43311 /* 120341 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43312 /* 120346 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
43313 /* 120349 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43314 /* 120353 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43315 /* 120358 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
43316 /* 120361 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
43317 /* 120365 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
43318 /* 120368 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43319 /* 120373 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43320 /* 120378 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
43321 /* 120383 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
43322 /* 120386 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINfd),
43323 /* 120390 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43324 /* 120395 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
43325 /* 120398 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
43326 /* 120401 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
43327 /* 120404 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43328 /* 120410 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43329 /* 120412 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
43330 /* 120415 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43331 /* 120419 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43332 /* 120424 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
43333 /* 120427 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43334 /* 120432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43335 /* 120435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43336 /* 120437 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
43337 /* 120444 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
43338 /* 120449 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43339 /* 120454 */ // GIR_Coverage, 3098,
43340 /* 120454 */ GIR_EraseRootFromParent_Done,
43341 /* 120455 */ // Label 3641: @120455
43342 /* 120455 */ GIM_Reject,
43343 /* 120456 */ // Label 3635: @120456
43344 /* 120456 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3642*/ GIMT_Encode4(120501), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1393 //
43345 /* 120463 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
43346 /* 120466 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43347 /* 120469 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43348 /* 120473 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43349 /* 120477 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43350 /* 120481 */ // (fminimum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMINhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
43351 /* 120481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhd),
43352 /* 120484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43353 /* 120486 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43354 /* 120488 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43355 /* 120490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43356 /* 120493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43357 /* 120499 */ GIR_RootConstrainSelectedInstOperands,
43358 /* 120500 */ // GIR_Coverage, 1393,
43359 /* 120500 */ GIR_EraseRootFromParent_Done,
43360 /* 120501 */ // Label 3642: @120501
43361 /* 120501 */ GIM_Reject,
43362 /* 120502 */ // Label 3636: @120502
43363 /* 120502 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3643*/ GIMT_Encode4(120547), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1394 //
43364 /* 120509 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
43365 /* 120512 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43366 /* 120515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43367 /* 120519 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43368 /* 120523 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43369 /* 120527 */ // (fminimum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMINhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
43370 /* 120527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhq),
43371 /* 120530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43372 /* 120532 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43373 /* 120534 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43374 /* 120536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43375 /* 120539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43376 /* 120545 */ GIR_RootConstrainSelectedInstOperands,
43377 /* 120546 */ // GIR_Coverage, 1394,
43378 /* 120546 */ GIR_EraseRootFromParent_Done,
43379 /* 120547 */ // Label 3643: @120547
43380 /* 120547 */ GIM_Reject,
43381 /* 120548 */ // Label 3637: @120548
43382 /* 120548 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3644*/ GIMT_Encode4(120593), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1391 //
43383 /* 120555 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
43384 /* 120558 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43385 /* 120561 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43386 /* 120565 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43387 /* 120569 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43388 /* 120573 */ // (fminimum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMINfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
43389 /* 120573 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfd),
43390 /* 120576 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43391 /* 120578 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43392 /* 120580 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43393 /* 120582 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43394 /* 120585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43395 /* 120591 */ GIR_RootConstrainSelectedInstOperands,
43396 /* 120592 */ // GIR_Coverage, 1391,
43397 /* 120592 */ GIR_EraseRootFromParent_Done,
43398 /* 120593 */ // Label 3644: @120593
43399 /* 120593 */ GIM_Reject,
43400 /* 120594 */ // Label 3638: @120594
43401 /* 120594 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3645*/ GIMT_Encode4(120639), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1392 //
43402 /* 120601 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
43403 /* 120604 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43404 /* 120607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43405 /* 120611 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43406 /* 120615 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43407 /* 120619 */ // (fminimum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMINfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
43408 /* 120619 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfq),
43409 /* 120622 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43410 /* 120624 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43411 /* 120626 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43412 /* 120628 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43413 /* 120631 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43414 /* 120637 */ GIR_RootConstrainSelectedInstOperands,
43415 /* 120638 */ // GIR_Coverage, 1392,
43416 /* 120638 */ GIR_EraseRootFromParent_Done,
43417 /* 120639 */ // Label 3645: @120639
43418 /* 120639 */ GIM_Reject,
43419 /* 120640 */ // Label 3639: @120640
43420 /* 120640 */ GIM_Reject,
43421 /* 120641 */ // Label 58: @120641
43422 /* 120641 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3652*/ GIMT_Encode4(121368),
43423 /* 120652 */ /*GILLT_s16*//*Label 3646*/ GIMT_Encode4(120704),
43424 /* 120656 */ /*GILLT_s32*//*Label 3647*/ GIMT_Encode4(120944), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
43425 /* 120688 */ /*GILLT_v4s16*//*Label 3648*/ GIMT_Encode4(121184),
43426 /* 120692 */ /*GILLT_v8s16*//*Label 3649*/ GIMT_Encode4(121230),
43427 /* 120696 */ /*GILLT_v2s32*//*Label 3650*/ GIMT_Encode4(121276),
43428 /* 120700 */ /*GILLT_v4s32*//*Label 3651*/ GIMT_Encode4(121322),
43429 /* 120704 */ // Label 3646: @120704
43430 /* 120704 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3653*/ GIMT_Encode4(120943), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 3095 //
43431 /* 120711 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
43432 /* 120714 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
43433 /* 120717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43434 /* 120721 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43435 /* 120725 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43436 /* 120729 */ // (fmaximum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMAXhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
43437 /* 120729 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
43438 /* 120732 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43439 /* 120736 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43440 /* 120741 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
43441 /* 120743 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
43442 /* 120746 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43443 /* 120750 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43444 /* 120755 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
43445 /* 120758 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43446 /* 120763 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
43447 /* 120766 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43448 /* 120770 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43449 /* 120775 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
43450 /* 120778 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
43451 /* 120782 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
43452 /* 120785 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43453 /* 120790 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43454 /* 120795 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
43455 /* 120800 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
43456 /* 120803 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43457 /* 120807 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43458 /* 120812 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
43459 /* 120814 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
43460 /* 120817 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43461 /* 120821 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43462 /* 120826 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
43463 /* 120829 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43464 /* 120834 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
43465 /* 120837 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43466 /* 120841 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43467 /* 120846 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
43468 /* 120849 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
43469 /* 120853 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
43470 /* 120856 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43471 /* 120861 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43472 /* 120866 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
43473 /* 120871 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
43474 /* 120874 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXhd),
43475 /* 120878 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43476 /* 120883 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
43477 /* 120886 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
43478 /* 120889 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
43479 /* 120892 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43480 /* 120898 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43481 /* 120900 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
43482 /* 120903 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43483 /* 120907 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43484 /* 120912 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
43485 /* 120915 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43486 /* 120920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43487 /* 120923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43488 /* 120925 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
43489 /* 120932 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
43490 /* 120937 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43491 /* 120942 */ // GIR_Coverage, 3095,
43492 /* 120942 */ GIR_EraseRootFromParent_Done,
43493 /* 120943 */ // Label 3653: @120943
43494 /* 120943 */ GIM_Reject,
43495 /* 120944 */ // Label 3647: @120944
43496 /* 120944 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3654*/ GIMT_Encode4(121183), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 3097 //
43497 /* 120951 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
43498 /* 120954 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
43499 /* 120957 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43500 /* 120961 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43501 /* 120965 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43502 /* 120969 */ // (fmaximum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMAXfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
43503 /* 120969 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
43504 /* 120972 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43505 /* 120976 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43506 /* 120981 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
43507 /* 120983 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
43508 /* 120986 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43509 /* 120990 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43510 /* 120995 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
43511 /* 120998 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43512 /* 121003 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
43513 /* 121006 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43514 /* 121010 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43515 /* 121015 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
43516 /* 121018 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
43517 /* 121022 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
43518 /* 121025 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43519 /* 121030 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43520 /* 121035 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
43521 /* 121040 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
43522 /* 121043 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43523 /* 121047 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43524 /* 121052 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
43525 /* 121054 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
43526 /* 121057 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43527 /* 121061 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43528 /* 121066 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
43529 /* 121069 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43530 /* 121074 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
43531 /* 121077 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43532 /* 121081 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43533 /* 121086 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
43534 /* 121089 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
43535 /* 121093 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
43536 /* 121096 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43537 /* 121101 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43538 /* 121106 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
43539 /* 121111 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
43540 /* 121114 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXfd),
43541 /* 121118 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43542 /* 121123 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
43543 /* 121126 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
43544 /* 121129 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
43545 /* 121132 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43546 /* 121138 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43547 /* 121140 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
43548 /* 121143 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43549 /* 121147 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43550 /* 121152 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
43551 /* 121155 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43552 /* 121160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43553 /* 121163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43554 /* 121165 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
43555 /* 121172 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
43556 /* 121177 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43557 /* 121182 */ // GIR_Coverage, 3097,
43558 /* 121182 */ GIR_EraseRootFromParent_Done,
43559 /* 121183 */ // Label 3654: @121183
43560 /* 121183 */ GIM_Reject,
43561 /* 121184 */ // Label 3648: @121184
43562 /* 121184 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3655*/ GIMT_Encode4(121229), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1373 //
43563 /* 121191 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
43564 /* 121194 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43565 /* 121197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43566 /* 121201 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43567 /* 121205 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43568 /* 121209 */ // (fmaximum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMAXhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
43569 /* 121209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhd),
43570 /* 121212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43571 /* 121214 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43572 /* 121216 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43573 /* 121218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43574 /* 121221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43575 /* 121227 */ GIR_RootConstrainSelectedInstOperands,
43576 /* 121228 */ // GIR_Coverage, 1373,
43577 /* 121228 */ GIR_EraseRootFromParent_Done,
43578 /* 121229 */ // Label 3655: @121229
43579 /* 121229 */ GIM_Reject,
43580 /* 121230 */ // Label 3649: @121230
43581 /* 121230 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3656*/ GIMT_Encode4(121275), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON), // Rule ID 1374 //
43582 /* 121237 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
43583 /* 121240 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43584 /* 121243 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43585 /* 121247 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43586 /* 121251 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43587 /* 121255 */ // (fmaximum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMAXhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
43588 /* 121255 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhq),
43589 /* 121258 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43590 /* 121260 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43591 /* 121262 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43592 /* 121264 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43593 /* 121267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43594 /* 121273 */ GIR_RootConstrainSelectedInstOperands,
43595 /* 121274 */ // GIR_Coverage, 1374,
43596 /* 121274 */ GIR_EraseRootFromParent_Done,
43597 /* 121275 */ // Label 3656: @121275
43598 /* 121275 */ GIM_Reject,
43599 /* 121276 */ // Label 3650: @121276
43600 /* 121276 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3657*/ GIMT_Encode4(121321), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1371 //
43601 /* 121283 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
43602 /* 121286 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43603 /* 121289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43604 /* 121293 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43605 /* 121297 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43606 /* 121301 */ // (fmaximum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMAXfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
43607 /* 121301 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfd),
43608 /* 121304 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43609 /* 121306 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43610 /* 121308 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43611 /* 121310 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43612 /* 121313 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43613 /* 121319 */ GIR_RootConstrainSelectedInstOperands,
43614 /* 121320 */ // GIR_Coverage, 1371,
43615 /* 121320 */ GIR_EraseRootFromParent_Done,
43616 /* 121321 */ // Label 3657: @121321
43617 /* 121321 */ GIM_Reject,
43618 /* 121322 */ // Label 3651: @121322
43619 /* 121322 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3658*/ GIMT_Encode4(121367), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1372 //
43620 /* 121329 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
43621 /* 121332 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43622 /* 121335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43623 /* 121339 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43624 /* 121343 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43625 /* 121347 */ // (fmaximum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMAXfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
43626 /* 121347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfq),
43627 /* 121350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43628 /* 121352 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43629 /* 121354 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43630 /* 121356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43631 /* 121359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43632 /* 121365 */ GIR_RootConstrainSelectedInstOperands,
43633 /* 121366 */ // GIR_Coverage, 1372,
43634 /* 121366 */ GIR_EraseRootFromParent_Done,
43635 /* 121367 */ // Label 3658: @121367
43636 /* 121367 */ GIM_Reject,
43637 /* 121368 */ // Label 3652: @121368
43638 /* 121368 */ GIM_Reject,
43639 /* 121369 */ // Label 59: @121369
43640 /* 121369 */ GIM_Try, /*On fail goto*//*Label 3659*/ GIMT_Encode4(121401), // Rule ID 2800 //
43641 /* 121374 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
43642 /* 121377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
43643 /* 121381 */ // (get_fpenv:{ *:[i32] }) => (VMRS:{ *:[i32] })
43644 /* 121381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS),
43645 /* 121384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
43646 /* 121386 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43647 /* 121389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43648 /* 121395 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
43649 /* 121399 */ GIR_RootConstrainSelectedInstOperands,
43650 /* 121400 */ // GIR_Coverage, 2800,
43651 /* 121400 */ GIR_EraseRootFromParent_Done,
43652 /* 121401 */ // Label 3659: @121401
43653 /* 121401 */ GIM_Reject,
43654 /* 121402 */ // Label 60: @121402
43655 /* 121402 */ GIM_Try, /*On fail goto*//*Label 3660*/ GIMT_Encode4(121437), // Rule ID 2801 //
43656 /* 121407 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
43657 /* 121410 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
43658 /* 121414 */ // (set_fpenv GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt)
43659 /* 121414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
43660 /* 121417 */ GIR_RootToRootCopy, /*OpIdx*/0, // Rt
43661 /* 121419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43662 /* 121422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43663 /* 121428 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
43664 /* 121431 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
43665 /* 121435 */ GIR_RootConstrainSelectedInstOperands,
43666 /* 121436 */ // GIR_Coverage, 2801,
43667 /* 121436 */ GIR_EraseRootFromParent_Done,
43668 /* 121437 */ // Label 3660: @121437
43669 /* 121437 */ GIM_Reject,
43670 /* 121438 */ // Label 61: @121438
43671 /* 121438 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3661*/ GIMT_Encode4(121501), GIMT_Encode2(GIFBS_IsARM), // Rule ID 2802 //
43672 /* 121445 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (MOVi:{ *:[i32] } 0:{ *:[i32] }))
43673 /* 121445 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43674 /* 121448 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MOVi),
43675 /* 121452 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43676 /* 121457 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
43677 /* 121460 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
43678 /* 121463 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43679 /* 121469 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43680 /* 121475 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43681 /* 121477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
43682 /* 121480 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43683 /* 121483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43684 /* 121486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43685 /* 121492 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
43686 /* 121495 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
43687 /* 121499 */ GIR_RootConstrainSelectedInstOperands,
43688 /* 121500 */ // GIR_Coverage, 2802,
43689 /* 121500 */ GIR_EraseRootFromParent_Done,
43690 /* 121501 */ // Label 3661: @121501
43691 /* 121501 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3662*/ GIMT_Encode4(121564), GIMT_Encode2(GIFBS_IsThumb), // Rule ID 2803 //
43692 /* 121508 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
43693 /* 121508 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
43694 /* 121511 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
43695 /* 121515 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43696 /* 121520 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
43697 /* 121526 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
43698 /* 121529 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
43699 /* 121532 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43700 /* 121538 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
43701 /* 121540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
43702 /* 121543 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43703 /* 121546 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43704 /* 121549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43705 /* 121555 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
43706 /* 121558 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
43707 /* 121562 */ GIR_RootConstrainSelectedInstOperands,
43708 /* 121563 */ // GIR_Coverage, 2803,
43709 /* 121563 */ GIR_EraseRootFromParent_Done,
43710 /* 121564 */ // Label 3662: @121564
43711 /* 121564 */ GIM_Reject,
43712 /* 121565 */ // Label 62: @121565
43713 /* 121565 */ GIM_Try, /*On fail goto*//*Label 3663*/ GIMT_Encode4(121597), // Rule ID 2804 //
43714 /* 121570 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
43715 /* 121573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
43716 /* 121577 */ // (get_fpmode:{ *:[i32] }) => (VMRS:{ *:[i32] })
43717 /* 121577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS),
43718 /* 121580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
43719 /* 121582 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43720 /* 121585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43721 /* 121591 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
43722 /* 121595 */ GIR_RootConstrainSelectedInstOperands,
43723 /* 121596 */ // GIR_Coverage, 2804,
43724 /* 121596 */ GIR_EraseRootFromParent_Done,
43725 /* 121597 */ // Label 3663: @121597
43726 /* 121597 */ GIM_Reject,
43727 /* 121598 */ // Label 63: @121598
43728 /* 121598 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3670*/ GIMT_Encode4(122107),
43729 /* 121609 */ /*GILLT_v8s8*//*Label 3664*/ GIMT_Encode4(121633),
43730 /* 121613 */ /*GILLT_v16s8*//*Label 3665*/ GIMT_Encode4(121679),
43731 /* 121617 */ /*GILLT_v4s16*//*Label 3666*/ GIMT_Encode4(121791),
43732 /* 121621 */ /*GILLT_v8s16*//*Label 3667*/ GIMT_Encode4(121837),
43733 /* 121625 */ /*GILLT_v2s32*//*Label 3668*/ GIMT_Encode4(121949),
43734 /* 121629 */ /*GILLT_v4s32*//*Label 3669*/ GIMT_Encode4(121995),
43735 /* 121633 */ // Label 3664: @121633
43736 /* 121633 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3671*/ GIMT_Encode4(121678), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1383 //
43737 /* 121640 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
43738 /* 121643 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
43739 /* 121646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43740 /* 121650 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43741 /* 121654 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43742 /* 121658 */ // (smin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
43743 /* 121658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i8),
43744 /* 121661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43745 /* 121663 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43746 /* 121665 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43747 /* 121667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43748 /* 121670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43749 /* 121676 */ GIR_RootConstrainSelectedInstOperands,
43750 /* 121677 */ // GIR_Coverage, 1383,
43751 /* 121677 */ GIR_EraseRootFromParent_Done,
43752 /* 121678 */ // Label 3671: @121678
43753 /* 121678 */ GIM_Reject,
43754 /* 121679 */ // Label 3665: @121679
43755 /* 121679 */ GIM_Try, /*On fail goto*//*Label 3672*/ GIMT_Encode4(121790),
43756 /* 121684 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
43757 /* 121687 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
43758 /* 121690 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3673*/ GIMT_Encode4(121729), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1384 //
43759 /* 121697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43760 /* 121701 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43761 /* 121705 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43762 /* 121709 */ // (smin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
43763 /* 121709 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv16i8),
43764 /* 121712 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43765 /* 121714 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43766 /* 121716 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43767 /* 121718 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43768 /* 121721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43769 /* 121727 */ GIR_RootConstrainSelectedInstOperands,
43770 /* 121728 */ // GIR_Coverage, 1384,
43771 /* 121728 */ GIR_EraseRootFromParent_Done,
43772 /* 121729 */ // Label 3673: @121729
43773 /* 121729 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3674*/ GIMT_Encode4(121789), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3691 //
43774 /* 121736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43775 /* 121740 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43776 /* 121744 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43777 /* 121748 */ // (smin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
43778 /* 121748 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43779 /* 121751 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43780 /* 121755 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43781 /* 121760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs8),
43782 /* 121763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43783 /* 121765 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
43784 /* 121767 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
43785 /* 121769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43786 /* 121772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43787 /* 121778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43788 /* 121784 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43789 /* 121787 */ GIR_RootConstrainSelectedInstOperands,
43790 /* 121788 */ // GIR_Coverage, 3691,
43791 /* 121788 */ GIR_EraseRootFromParent_Done,
43792 /* 121789 */ // Label 3674: @121789
43793 /* 121789 */ GIM_Reject,
43794 /* 121790 */ // Label 3672: @121790
43795 /* 121790 */ GIM_Reject,
43796 /* 121791 */ // Label 3666: @121791
43797 /* 121791 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3675*/ GIMT_Encode4(121836), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1379 //
43798 /* 121798 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
43799 /* 121801 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43800 /* 121804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43801 /* 121808 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43802 /* 121812 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43803 /* 121816 */ // (smin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
43804 /* 121816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i16),
43805 /* 121819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43806 /* 121821 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43807 /* 121823 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43808 /* 121825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43809 /* 121828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43810 /* 121834 */ GIR_RootConstrainSelectedInstOperands,
43811 /* 121835 */ // GIR_Coverage, 1379,
43812 /* 121835 */ GIR_EraseRootFromParent_Done,
43813 /* 121836 */ // Label 3675: @121836
43814 /* 121836 */ GIM_Reject,
43815 /* 121837 */ // Label 3667: @121837
43816 /* 121837 */ GIM_Try, /*On fail goto*//*Label 3676*/ GIMT_Encode4(121948),
43817 /* 121842 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
43818 /* 121845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43819 /* 121848 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3677*/ GIMT_Encode4(121887), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1381 //
43820 /* 121855 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43821 /* 121859 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43822 /* 121863 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43823 /* 121867 */ // (smin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
43824 /* 121867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i16),
43825 /* 121870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43826 /* 121872 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43827 /* 121874 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43828 /* 121876 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43829 /* 121879 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43830 /* 121885 */ GIR_RootConstrainSelectedInstOperands,
43831 /* 121886 */ // GIR_Coverage, 1381,
43832 /* 121886 */ GIR_EraseRootFromParent_Done,
43833 /* 121887 */ // Label 3677: @121887
43834 /* 121887 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3678*/ GIMT_Encode4(121947), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3694 //
43835 /* 121894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43836 /* 121898 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43837 /* 121902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43838 /* 121906 */ // (smin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
43839 /* 121906 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43840 /* 121909 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43841 /* 121913 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43842 /* 121918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs16),
43843 /* 121921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43844 /* 121923 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
43845 /* 121925 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
43846 /* 121927 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43847 /* 121930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43848 /* 121936 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43849 /* 121942 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43850 /* 121945 */ GIR_RootConstrainSelectedInstOperands,
43851 /* 121946 */ // GIR_Coverage, 3694,
43852 /* 121946 */ GIR_EraseRootFromParent_Done,
43853 /* 121947 */ // Label 3678: @121947
43854 /* 121947 */ GIM_Reject,
43855 /* 121948 */ // Label 3676: @121948
43856 /* 121948 */ GIM_Reject,
43857 /* 121949 */ // Label 3668: @121949
43858 /* 121949 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3679*/ GIMT_Encode4(121994), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1380 //
43859 /* 121956 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
43860 /* 121959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43861 /* 121962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43862 /* 121966 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43863 /* 121970 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43864 /* 121974 */ // (smin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
43865 /* 121974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv2i32),
43866 /* 121977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43867 /* 121979 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43868 /* 121981 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43869 /* 121983 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43870 /* 121986 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43871 /* 121992 */ GIR_RootConstrainSelectedInstOperands,
43872 /* 121993 */ // GIR_Coverage, 1380,
43873 /* 121993 */ GIR_EraseRootFromParent_Done,
43874 /* 121994 */ // Label 3679: @121994
43875 /* 121994 */ GIM_Reject,
43876 /* 121995 */ // Label 3669: @121995
43877 /* 121995 */ GIM_Try, /*On fail goto*//*Label 3680*/ GIMT_Encode4(122106),
43878 /* 122000 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
43879 /* 122003 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43880 /* 122006 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3681*/ GIMT_Encode4(122045), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1382 //
43881 /* 122013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43882 /* 122017 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43883 /* 122021 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43884 /* 122025 */ // (smin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
43885 /* 122025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i32),
43886 /* 122028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43887 /* 122030 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43888 /* 122032 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43889 /* 122034 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43890 /* 122037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43891 /* 122043 */ GIR_RootConstrainSelectedInstOperands,
43892 /* 122044 */ // GIR_Coverage, 1382,
43893 /* 122044 */ GIR_EraseRootFromParent_Done,
43894 /* 122045 */ // Label 3681: @122045
43895 /* 122045 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3682*/ GIMT_Encode4(122105), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3697 //
43896 /* 122052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43897 /* 122056 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43898 /* 122060 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43899 /* 122064 */ // (smin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
43900 /* 122064 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43901 /* 122067 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43902 /* 122071 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43903 /* 122076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs32),
43904 /* 122079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43905 /* 122081 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
43906 /* 122083 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
43907 /* 122085 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43908 /* 122088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43909 /* 122094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43910 /* 122100 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43911 /* 122103 */ GIR_RootConstrainSelectedInstOperands,
43912 /* 122104 */ // GIR_Coverage, 3697,
43913 /* 122104 */ GIR_EraseRootFromParent_Done,
43914 /* 122105 */ // Label 3682: @122105
43915 /* 122105 */ GIM_Reject,
43916 /* 122106 */ // Label 3680: @122106
43917 /* 122106 */ GIM_Reject,
43918 /* 122107 */ // Label 3670: @122107
43919 /* 122107 */ GIM_Reject,
43920 /* 122108 */ // Label 64: @122108
43921 /* 122108 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3689*/ GIMT_Encode4(122617),
43922 /* 122119 */ /*GILLT_v8s8*//*Label 3683*/ GIMT_Encode4(122143),
43923 /* 122123 */ /*GILLT_v16s8*//*Label 3684*/ GIMT_Encode4(122189),
43924 /* 122127 */ /*GILLT_v4s16*//*Label 3685*/ GIMT_Encode4(122301),
43925 /* 122131 */ /*GILLT_v8s16*//*Label 3686*/ GIMT_Encode4(122347),
43926 /* 122135 */ /*GILLT_v2s32*//*Label 3687*/ GIMT_Encode4(122459),
43927 /* 122139 */ /*GILLT_v4s32*//*Label 3688*/ GIMT_Encode4(122505),
43928 /* 122143 */ // Label 3683: @122143
43929 /* 122143 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3690*/ GIMT_Encode4(122188), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1363 //
43930 /* 122150 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
43931 /* 122153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
43932 /* 122156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43933 /* 122160 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43934 /* 122164 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43935 /* 122168 */ // (smax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
43936 /* 122168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i8),
43937 /* 122171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43938 /* 122173 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43939 /* 122175 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43940 /* 122177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43941 /* 122180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43942 /* 122186 */ GIR_RootConstrainSelectedInstOperands,
43943 /* 122187 */ // GIR_Coverage, 1363,
43944 /* 122187 */ GIR_EraseRootFromParent_Done,
43945 /* 122188 */ // Label 3690: @122188
43946 /* 122188 */ GIM_Reject,
43947 /* 122189 */ // Label 3684: @122189
43948 /* 122189 */ GIM_Try, /*On fail goto*//*Label 3691*/ GIMT_Encode4(122300),
43949 /* 122194 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
43950 /* 122197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
43951 /* 122200 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3692*/ GIMT_Encode4(122239), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1364 //
43952 /* 122207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43953 /* 122211 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43954 /* 122215 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43955 /* 122219 */ // (smax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
43956 /* 122219 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv16i8),
43957 /* 122222 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43958 /* 122224 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43959 /* 122226 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43960 /* 122228 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43961 /* 122231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43962 /* 122237 */ GIR_RootConstrainSelectedInstOperands,
43963 /* 122238 */ // GIR_Coverage, 1364,
43964 /* 122238 */ GIR_EraseRootFromParent_Done,
43965 /* 122239 */ // Label 3692: @122239
43966 /* 122239 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3693*/ GIMT_Encode4(122299), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3709 //
43967 /* 122246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43968 /* 122250 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43969 /* 122254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43970 /* 122258 */ // (smax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
43971 /* 122258 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
43972 /* 122261 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43973 /* 122265 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43974 /* 122270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs8),
43975 /* 122273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43976 /* 122275 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
43977 /* 122277 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
43978 /* 122279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43979 /* 122282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43980 /* 122288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43981 /* 122294 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
43982 /* 122297 */ GIR_RootConstrainSelectedInstOperands,
43983 /* 122298 */ // GIR_Coverage, 3709,
43984 /* 122298 */ GIR_EraseRootFromParent_Done,
43985 /* 122299 */ // Label 3693: @122299
43986 /* 122299 */ GIM_Reject,
43987 /* 122300 */ // Label 3691: @122300
43988 /* 122300 */ GIM_Reject,
43989 /* 122301 */ // Label 3685: @122301
43990 /* 122301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3694*/ GIMT_Encode4(122346), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1359 //
43991 /* 122308 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
43992 /* 122311 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43993 /* 122314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43994 /* 122318 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43995 /* 122322 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43996 /* 122326 */ // (smax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
43997 /* 122326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i16),
43998 /* 122329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43999 /* 122331 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44000 /* 122333 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44001 /* 122335 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44002 /* 122338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44003 /* 122344 */ GIR_RootConstrainSelectedInstOperands,
44004 /* 122345 */ // GIR_Coverage, 1359,
44005 /* 122345 */ GIR_EraseRootFromParent_Done,
44006 /* 122346 */ // Label 3694: @122346
44007 /* 122346 */ GIM_Reject,
44008 /* 122347 */ // Label 3686: @122347
44009 /* 122347 */ GIM_Try, /*On fail goto*//*Label 3695*/ GIMT_Encode4(122458),
44010 /* 122352 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
44011 /* 122355 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
44012 /* 122358 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3696*/ GIMT_Encode4(122397), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1361 //
44013 /* 122365 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44014 /* 122369 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44015 /* 122373 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44016 /* 122377 */ // (smax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
44017 /* 122377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i16),
44018 /* 122380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44019 /* 122382 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44020 /* 122384 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44021 /* 122386 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44022 /* 122389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44023 /* 122395 */ GIR_RootConstrainSelectedInstOperands,
44024 /* 122396 */ // GIR_Coverage, 1361,
44025 /* 122396 */ GIR_EraseRootFromParent_Done,
44026 /* 122397 */ // Label 3696: @122397
44027 /* 122397 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3697*/ GIMT_Encode4(122457), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3712 //
44028 /* 122404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44029 /* 122408 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44030 /* 122412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44031 /* 122416 */ // (smax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
44032 /* 122416 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44033 /* 122419 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44034 /* 122423 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44035 /* 122428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs16),
44036 /* 122431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44037 /* 122433 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44038 /* 122435 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44039 /* 122437 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44040 /* 122440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44041 /* 122446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44042 /* 122452 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44043 /* 122455 */ GIR_RootConstrainSelectedInstOperands,
44044 /* 122456 */ // GIR_Coverage, 3712,
44045 /* 122456 */ GIR_EraseRootFromParent_Done,
44046 /* 122457 */ // Label 3697: @122457
44047 /* 122457 */ GIM_Reject,
44048 /* 122458 */ // Label 3695: @122458
44049 /* 122458 */ GIM_Reject,
44050 /* 122459 */ // Label 3687: @122459
44051 /* 122459 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3698*/ GIMT_Encode4(122504), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1360 //
44052 /* 122466 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
44053 /* 122469 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
44054 /* 122472 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44055 /* 122476 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44056 /* 122480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44057 /* 122484 */ // (smax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
44058 /* 122484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv2i32),
44059 /* 122487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44060 /* 122489 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44061 /* 122491 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44062 /* 122493 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44063 /* 122496 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44064 /* 122502 */ GIR_RootConstrainSelectedInstOperands,
44065 /* 122503 */ // GIR_Coverage, 1360,
44066 /* 122503 */ GIR_EraseRootFromParent_Done,
44067 /* 122504 */ // Label 3698: @122504
44068 /* 122504 */ GIM_Reject,
44069 /* 122505 */ // Label 3688: @122505
44070 /* 122505 */ GIM_Try, /*On fail goto*//*Label 3699*/ GIMT_Encode4(122616),
44071 /* 122510 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44072 /* 122513 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
44073 /* 122516 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3700*/ GIMT_Encode4(122555), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1362 //
44074 /* 122523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44075 /* 122527 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44076 /* 122531 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44077 /* 122535 */ // (smax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
44078 /* 122535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i32),
44079 /* 122538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44080 /* 122540 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44081 /* 122542 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44082 /* 122544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44083 /* 122547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44084 /* 122553 */ GIR_RootConstrainSelectedInstOperands,
44085 /* 122554 */ // GIR_Coverage, 1362,
44086 /* 122554 */ GIR_EraseRootFromParent_Done,
44087 /* 122555 */ // Label 3700: @122555
44088 /* 122555 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3701*/ GIMT_Encode4(122615), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3715 //
44089 /* 122562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44090 /* 122566 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44091 /* 122570 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44092 /* 122574 */ // (smax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
44093 /* 122574 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44094 /* 122577 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44095 /* 122581 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44096 /* 122586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs32),
44097 /* 122589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44098 /* 122591 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44099 /* 122593 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44100 /* 122595 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44101 /* 122598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44102 /* 122604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44103 /* 122610 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44104 /* 122613 */ GIR_RootConstrainSelectedInstOperands,
44105 /* 122614 */ // GIR_Coverage, 3715,
44106 /* 122614 */ GIR_EraseRootFromParent_Done,
44107 /* 122615 */ // Label 3701: @122615
44108 /* 122615 */ GIM_Reject,
44109 /* 122616 */ // Label 3699: @122616
44110 /* 122616 */ GIM_Reject,
44111 /* 122617 */ // Label 3689: @122617
44112 /* 122617 */ GIM_Reject,
44113 /* 122618 */ // Label 65: @122618
44114 /* 122618 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3708*/ GIMT_Encode4(123505),
44115 /* 122629 */ /*GILLT_v8s8*//*Label 3702*/ GIMT_Encode4(122653),
44116 /* 122633 */ /*GILLT_v16s8*//*Label 3703*/ GIMT_Encode4(122699),
44117 /* 122637 */ /*GILLT_v4s16*//*Label 3704*/ GIMT_Encode4(122937),
44118 /* 122641 */ /*GILLT_v8s16*//*Label 3705*/ GIMT_Encode4(122983),
44119 /* 122645 */ /*GILLT_v2s32*//*Label 3706*/ GIMT_Encode4(123221),
44120 /* 122649 */ /*GILLT_v4s32*//*Label 3707*/ GIMT_Encode4(123267),
44121 /* 122653 */ // Label 3702: @122653
44122 /* 122653 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3709*/ GIMT_Encode4(122698), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1389 //
44123 /* 122660 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
44124 /* 122663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
44125 /* 122666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44126 /* 122670 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44127 /* 122674 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44128 /* 122678 */ // (umin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
44129 /* 122678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i8),
44130 /* 122681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44131 /* 122683 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44132 /* 122685 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44133 /* 122687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44134 /* 122690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44135 /* 122696 */ GIR_RootConstrainSelectedInstOperands,
44136 /* 122697 */ // GIR_Coverage, 1389,
44137 /* 122697 */ GIR_EraseRootFromParent_Done,
44138 /* 122698 */ // Label 3709: @122698
44139 /* 122698 */ GIM_Reject,
44140 /* 122699 */ // Label 3703: @122699
44141 /* 122699 */ GIM_Try, /*On fail goto*//*Label 3710*/ GIMT_Encode4(122936),
44142 /* 122704 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
44143 /* 122707 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
44144 /* 122710 */ GIM_Try, /*On fail goto*//*Label 3711*/ GIMT_Encode4(122836),
44145 /* 122715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44146 /* 122719 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3712*/ GIMT_Encode4(122777), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6661 //
44147 /* 122726 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44148 /* 122730 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44149 /* 122734 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
44150 /* 122738 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44151 /* 122743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44152 /* 122747 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44153 /* 122749 */ // (umin:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
44154 /* 122749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8),
44155 /* 122752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44156 /* 122754 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
44157 /* 122756 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44158 /* 122760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44159 /* 122763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44160 /* 122769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44161 /* 122775 */ GIR_RootConstrainSelectedInstOperands,
44162 /* 122776 */ // GIR_Coverage, 6661,
44163 /* 122776 */ GIR_EraseRootFromParent_Done,
44164 /* 122777 */ // Label 3712: @122777
44165 /* 122777 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3713*/ GIMT_Encode4(122835), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4096 //
44166 /* 122784 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44167 /* 122788 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
44168 /* 122792 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44169 /* 122796 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
44170 /* 122800 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44171 /* 122805 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44172 /* 122807 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
44173 /* 122807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8),
44174 /* 122810 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44175 /* 122812 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
44176 /* 122814 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44177 /* 122818 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44178 /* 122821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44179 /* 122827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44180 /* 122833 */ GIR_RootConstrainSelectedInstOperands,
44181 /* 122834 */ // GIR_Coverage, 4096,
44182 /* 122834 */ GIR_EraseRootFromParent_Done,
44183 /* 122835 */ // Label 3713: @122835
44184 /* 122835 */ GIM_Reject,
44185 /* 122836 */ // Label 3711: @122836
44186 /* 122836 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3714*/ GIMT_Encode4(122875), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1390 //
44187 /* 122843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44188 /* 122847 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44189 /* 122851 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44190 /* 122855 */ // (umin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
44191 /* 122855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv16i8),
44192 /* 122858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44193 /* 122860 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44194 /* 122862 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44195 /* 122864 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44196 /* 122867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44197 /* 122873 */ GIR_RootConstrainSelectedInstOperands,
44198 /* 122874 */ // GIR_Coverage, 1390,
44199 /* 122874 */ GIR_EraseRootFromParent_Done,
44200 /* 122875 */ // Label 3714: @122875
44201 /* 122875 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3715*/ GIMT_Encode4(122935), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3700 //
44202 /* 122882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44203 /* 122886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44204 /* 122890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44205 /* 122894 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
44206 /* 122894 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44207 /* 122897 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44208 /* 122901 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44209 /* 122906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu8),
44210 /* 122909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44211 /* 122911 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44212 /* 122913 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44213 /* 122915 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44214 /* 122918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44215 /* 122924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44216 /* 122930 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44217 /* 122933 */ GIR_RootConstrainSelectedInstOperands,
44218 /* 122934 */ // GIR_Coverage, 3700,
44219 /* 122934 */ GIR_EraseRootFromParent_Done,
44220 /* 122935 */ // Label 3715: @122935
44221 /* 122935 */ GIM_Reject,
44222 /* 122936 */ // Label 3710: @122936
44223 /* 122936 */ GIM_Reject,
44224 /* 122937 */ // Label 3704: @122937
44225 /* 122937 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3716*/ GIMT_Encode4(122982), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1385 //
44226 /* 122944 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
44227 /* 122947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
44228 /* 122950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44229 /* 122954 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44230 /* 122958 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44231 /* 122962 */ // (umin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
44232 /* 122962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i16),
44233 /* 122965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44234 /* 122967 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44235 /* 122969 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44236 /* 122971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44237 /* 122974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44238 /* 122980 */ GIR_RootConstrainSelectedInstOperands,
44239 /* 122981 */ // GIR_Coverage, 1385,
44240 /* 122981 */ GIR_EraseRootFromParent_Done,
44241 /* 122982 */ // Label 3716: @122982
44242 /* 122982 */ GIM_Reject,
44243 /* 122983 */ // Label 3705: @122983
44244 /* 122983 */ GIM_Try, /*On fail goto*//*Label 3717*/ GIMT_Encode4(123220),
44245 /* 122988 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
44246 /* 122991 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
44247 /* 122994 */ GIM_Try, /*On fail goto*//*Label 3718*/ GIMT_Encode4(123120),
44248 /* 122999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44249 /* 123003 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3719*/ GIMT_Encode4(123061), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6662 //
44250 /* 123010 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44251 /* 123014 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44252 /* 123018 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
44253 /* 123022 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44254 /* 123027 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44255 /* 123031 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44256 /* 123033 */ // (umin:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
44257 /* 123033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16),
44258 /* 123036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44259 /* 123038 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
44260 /* 123040 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44261 /* 123044 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44262 /* 123047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44263 /* 123053 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44264 /* 123059 */ GIR_RootConstrainSelectedInstOperands,
44265 /* 123060 */ // GIR_Coverage, 6662,
44266 /* 123060 */ GIR_EraseRootFromParent_Done,
44267 /* 123061 */ // Label 3719: @123061
44268 /* 123061 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3720*/ GIMT_Encode4(123119), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4098 //
44269 /* 123068 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44270 /* 123072 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
44271 /* 123076 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44272 /* 123080 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
44273 /* 123084 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44274 /* 123089 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44275 /* 123091 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
44276 /* 123091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16),
44277 /* 123094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44278 /* 123096 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
44279 /* 123098 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44280 /* 123102 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44281 /* 123105 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44282 /* 123111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44283 /* 123117 */ GIR_RootConstrainSelectedInstOperands,
44284 /* 123118 */ // GIR_Coverage, 4098,
44285 /* 123118 */ GIR_EraseRootFromParent_Done,
44286 /* 123119 */ // Label 3720: @123119
44287 /* 123119 */ GIM_Reject,
44288 /* 123120 */ // Label 3718: @123120
44289 /* 123120 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3721*/ GIMT_Encode4(123159), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1387 //
44290 /* 123127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44291 /* 123131 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44292 /* 123135 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44293 /* 123139 */ // (umin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
44294 /* 123139 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i16),
44295 /* 123142 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44296 /* 123144 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44297 /* 123146 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44298 /* 123148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44299 /* 123151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44300 /* 123157 */ GIR_RootConstrainSelectedInstOperands,
44301 /* 123158 */ // GIR_Coverage, 1387,
44302 /* 123158 */ GIR_EraseRootFromParent_Done,
44303 /* 123159 */ // Label 3721: @123159
44304 /* 123159 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3722*/ GIMT_Encode4(123219), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3703 //
44305 /* 123166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44306 /* 123170 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44307 /* 123174 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44308 /* 123178 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
44309 /* 123178 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44310 /* 123181 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44311 /* 123185 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44312 /* 123190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu16),
44313 /* 123193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44314 /* 123195 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44315 /* 123197 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44316 /* 123199 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44317 /* 123202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44318 /* 123208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44319 /* 123214 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44320 /* 123217 */ GIR_RootConstrainSelectedInstOperands,
44321 /* 123218 */ // GIR_Coverage, 3703,
44322 /* 123218 */ GIR_EraseRootFromParent_Done,
44323 /* 123219 */ // Label 3722: @123219
44324 /* 123219 */ GIM_Reject,
44325 /* 123220 */ // Label 3717: @123220
44326 /* 123220 */ GIM_Reject,
44327 /* 123221 */ // Label 3706: @123221
44328 /* 123221 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3723*/ GIMT_Encode4(123266), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1386 //
44329 /* 123228 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
44330 /* 123231 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
44331 /* 123234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44332 /* 123238 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44333 /* 123242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44334 /* 123246 */ // (umin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
44335 /* 123246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv2i32),
44336 /* 123249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44337 /* 123251 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44338 /* 123253 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44339 /* 123255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44340 /* 123258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44341 /* 123264 */ GIR_RootConstrainSelectedInstOperands,
44342 /* 123265 */ // GIR_Coverage, 1386,
44343 /* 123265 */ GIR_EraseRootFromParent_Done,
44344 /* 123266 */ // Label 3723: @123266
44345 /* 123266 */ GIM_Reject,
44346 /* 123267 */ // Label 3707: @123267
44347 /* 123267 */ GIM_Try, /*On fail goto*//*Label 3724*/ GIMT_Encode4(123504),
44348 /* 123272 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44349 /* 123275 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
44350 /* 123278 */ GIM_Try, /*On fail goto*//*Label 3725*/ GIMT_Encode4(123404),
44351 /* 123283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44352 /* 123287 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3726*/ GIMT_Encode4(123345), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6663 //
44353 /* 123294 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44354 /* 123298 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44355 /* 123302 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
44356 /* 123306 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44357 /* 123311 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44358 /* 123315 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44359 /* 123317 */ // (umin:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
44360 /* 123317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32),
44361 /* 123320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44362 /* 123322 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
44363 /* 123324 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44364 /* 123328 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44365 /* 123331 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44366 /* 123337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44367 /* 123343 */ GIR_RootConstrainSelectedInstOperands,
44368 /* 123344 */ // GIR_Coverage, 6663,
44369 /* 123344 */ GIR_EraseRootFromParent_Done,
44370 /* 123345 */ // Label 3726: @123345
44371 /* 123345 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3727*/ GIMT_Encode4(123403), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4100 //
44372 /* 123352 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44373 /* 123356 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
44374 /* 123360 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44375 /* 123364 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
44376 /* 123368 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44377 /* 123373 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44378 /* 123375 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
44379 /* 123375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32),
44380 /* 123378 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44381 /* 123380 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
44382 /* 123382 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44383 /* 123386 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44384 /* 123389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44385 /* 123395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44386 /* 123401 */ GIR_RootConstrainSelectedInstOperands,
44387 /* 123402 */ // GIR_Coverage, 4100,
44388 /* 123402 */ GIR_EraseRootFromParent_Done,
44389 /* 123403 */ // Label 3727: @123403
44390 /* 123403 */ GIM_Reject,
44391 /* 123404 */ // Label 3725: @123404
44392 /* 123404 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3728*/ GIMT_Encode4(123443), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1388 //
44393 /* 123411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44394 /* 123415 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44395 /* 123419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44396 /* 123423 */ // (umin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
44397 /* 123423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i32),
44398 /* 123426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44399 /* 123428 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44400 /* 123430 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44401 /* 123432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44402 /* 123435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44403 /* 123441 */ GIR_RootConstrainSelectedInstOperands,
44404 /* 123442 */ // GIR_Coverage, 1388,
44405 /* 123442 */ GIR_EraseRootFromParent_Done,
44406 /* 123443 */ // Label 3728: @123443
44407 /* 123443 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3729*/ GIMT_Encode4(123503), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3706 //
44408 /* 123450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44409 /* 123454 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44410 /* 123458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44411 /* 123462 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
44412 /* 123462 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44413 /* 123465 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44414 /* 123469 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44415 /* 123474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu32),
44416 /* 123477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44417 /* 123479 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44418 /* 123481 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44419 /* 123483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44420 /* 123486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44421 /* 123492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44422 /* 123498 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44423 /* 123501 */ GIR_RootConstrainSelectedInstOperands,
44424 /* 123502 */ // GIR_Coverage, 3706,
44425 /* 123502 */ GIR_EraseRootFromParent_Done,
44426 /* 123503 */ // Label 3729: @123503
44427 /* 123503 */ GIM_Reject,
44428 /* 123504 */ // Label 3724: @123504
44429 /* 123504 */ GIM_Reject,
44430 /* 123505 */ // Label 3708: @123505
44431 /* 123505 */ GIM_Reject,
44432 /* 123506 */ // Label 66: @123506
44433 /* 123506 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3736*/ GIMT_Encode4(124393),
44434 /* 123517 */ /*GILLT_v8s8*//*Label 3730*/ GIMT_Encode4(123541),
44435 /* 123521 */ /*GILLT_v16s8*//*Label 3731*/ GIMT_Encode4(123587),
44436 /* 123525 */ /*GILLT_v4s16*//*Label 3732*/ GIMT_Encode4(123825),
44437 /* 123529 */ /*GILLT_v8s16*//*Label 3733*/ GIMT_Encode4(123871),
44438 /* 123533 */ /*GILLT_v2s32*//*Label 3734*/ GIMT_Encode4(124109),
44439 /* 123537 */ /*GILLT_v4s32*//*Label 3735*/ GIMT_Encode4(124155),
44440 /* 123541 */ // Label 3730: @123541
44441 /* 123541 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3737*/ GIMT_Encode4(123586), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1369 //
44442 /* 123548 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
44443 /* 123551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
44444 /* 123554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44445 /* 123558 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44446 /* 123562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44447 /* 123566 */ // (umax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
44448 /* 123566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i8),
44449 /* 123569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44450 /* 123571 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44451 /* 123573 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44452 /* 123575 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44453 /* 123578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44454 /* 123584 */ GIR_RootConstrainSelectedInstOperands,
44455 /* 123585 */ // GIR_Coverage, 1369,
44456 /* 123585 */ GIR_EraseRootFromParent_Done,
44457 /* 123586 */ // Label 3737: @123586
44458 /* 123586 */ GIM_Reject,
44459 /* 123587 */ // Label 3731: @123587
44460 /* 123587 */ GIM_Try, /*On fail goto*//*Label 3738*/ GIMT_Encode4(123824),
44461 /* 123592 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
44462 /* 123595 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
44463 /* 123598 */ GIM_Try, /*On fail goto*//*Label 3739*/ GIMT_Encode4(123724),
44464 /* 123603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44465 /* 123607 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3740*/ GIMT_Encode4(123665), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6664 //
44466 /* 123614 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44467 /* 123618 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44468 /* 123622 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
44469 /* 123626 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44470 /* 123631 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44471 /* 123635 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44472 /* 123637 */ // (umax:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
44473 /* 123637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8),
44474 /* 123640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44475 /* 123642 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
44476 /* 123644 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44477 /* 123648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44478 /* 123651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44479 /* 123657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44480 /* 123663 */ GIR_RootConstrainSelectedInstOperands,
44481 /* 123664 */ // GIR_Coverage, 6664,
44482 /* 123664 */ GIR_EraseRootFromParent_Done,
44483 /* 123665 */ // Label 3740: @123665
44484 /* 123665 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3741*/ GIMT_Encode4(123723), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4102 //
44485 /* 123672 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44486 /* 123676 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
44487 /* 123680 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44488 /* 123684 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
44489 /* 123688 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44490 /* 123693 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44491 /* 123695 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
44492 /* 123695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8),
44493 /* 123698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44494 /* 123700 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
44495 /* 123702 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44496 /* 123706 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44497 /* 123709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44498 /* 123715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44499 /* 123721 */ GIR_RootConstrainSelectedInstOperands,
44500 /* 123722 */ // GIR_Coverage, 4102,
44501 /* 123722 */ GIR_EraseRootFromParent_Done,
44502 /* 123723 */ // Label 3741: @123723
44503 /* 123723 */ GIM_Reject,
44504 /* 123724 */ // Label 3739: @123724
44505 /* 123724 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3742*/ GIMT_Encode4(123763), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1370 //
44506 /* 123731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44507 /* 123735 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44508 /* 123739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44509 /* 123743 */ // (umax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
44510 /* 123743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv16i8),
44511 /* 123746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44512 /* 123748 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44513 /* 123750 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44514 /* 123752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44515 /* 123755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44516 /* 123761 */ GIR_RootConstrainSelectedInstOperands,
44517 /* 123762 */ // GIR_Coverage, 1370,
44518 /* 123762 */ GIR_EraseRootFromParent_Done,
44519 /* 123763 */ // Label 3742: @123763
44520 /* 123763 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3743*/ GIMT_Encode4(123823), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3718 //
44521 /* 123770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44522 /* 123774 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44523 /* 123778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44524 /* 123782 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
44525 /* 123782 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44526 /* 123785 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44527 /* 123789 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44528 /* 123794 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu8),
44529 /* 123797 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44530 /* 123799 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44531 /* 123801 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44532 /* 123803 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44533 /* 123806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44534 /* 123812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44535 /* 123818 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44536 /* 123821 */ GIR_RootConstrainSelectedInstOperands,
44537 /* 123822 */ // GIR_Coverage, 3718,
44538 /* 123822 */ GIR_EraseRootFromParent_Done,
44539 /* 123823 */ // Label 3743: @123823
44540 /* 123823 */ GIM_Reject,
44541 /* 123824 */ // Label 3738: @123824
44542 /* 123824 */ GIM_Reject,
44543 /* 123825 */ // Label 3732: @123825
44544 /* 123825 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3744*/ GIMT_Encode4(123870), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1365 //
44545 /* 123832 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
44546 /* 123835 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
44547 /* 123838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44548 /* 123842 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44549 /* 123846 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44550 /* 123850 */ // (umax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
44551 /* 123850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i16),
44552 /* 123853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44553 /* 123855 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44554 /* 123857 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44555 /* 123859 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44556 /* 123862 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44557 /* 123868 */ GIR_RootConstrainSelectedInstOperands,
44558 /* 123869 */ // GIR_Coverage, 1365,
44559 /* 123869 */ GIR_EraseRootFromParent_Done,
44560 /* 123870 */ // Label 3744: @123870
44561 /* 123870 */ GIM_Reject,
44562 /* 123871 */ // Label 3733: @123871
44563 /* 123871 */ GIM_Try, /*On fail goto*//*Label 3745*/ GIMT_Encode4(124108),
44564 /* 123876 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
44565 /* 123879 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
44566 /* 123882 */ GIM_Try, /*On fail goto*//*Label 3746*/ GIMT_Encode4(124008),
44567 /* 123887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44568 /* 123891 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3747*/ GIMT_Encode4(123949), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6665 //
44569 /* 123898 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44570 /* 123902 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44571 /* 123906 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
44572 /* 123910 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44573 /* 123915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44574 /* 123919 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44575 /* 123921 */ // (umax:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
44576 /* 123921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16),
44577 /* 123924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44578 /* 123926 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
44579 /* 123928 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44580 /* 123932 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44581 /* 123935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44582 /* 123941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44583 /* 123947 */ GIR_RootConstrainSelectedInstOperands,
44584 /* 123948 */ // GIR_Coverage, 6665,
44585 /* 123948 */ GIR_EraseRootFromParent_Done,
44586 /* 123949 */ // Label 3747: @123949
44587 /* 123949 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3748*/ GIMT_Encode4(124007), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4104 //
44588 /* 123956 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44589 /* 123960 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
44590 /* 123964 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44591 /* 123968 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
44592 /* 123972 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44593 /* 123977 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44594 /* 123979 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
44595 /* 123979 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16),
44596 /* 123982 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44597 /* 123984 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
44598 /* 123986 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44599 /* 123990 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44600 /* 123993 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44601 /* 123999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44602 /* 124005 */ GIR_RootConstrainSelectedInstOperands,
44603 /* 124006 */ // GIR_Coverage, 4104,
44604 /* 124006 */ GIR_EraseRootFromParent_Done,
44605 /* 124007 */ // Label 3748: @124007
44606 /* 124007 */ GIM_Reject,
44607 /* 124008 */ // Label 3746: @124008
44608 /* 124008 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3749*/ GIMT_Encode4(124047), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1367 //
44609 /* 124015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44610 /* 124019 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44611 /* 124023 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44612 /* 124027 */ // (umax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
44613 /* 124027 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i16),
44614 /* 124030 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44615 /* 124032 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44616 /* 124034 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44617 /* 124036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44618 /* 124039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44619 /* 124045 */ GIR_RootConstrainSelectedInstOperands,
44620 /* 124046 */ // GIR_Coverage, 1367,
44621 /* 124046 */ GIR_EraseRootFromParent_Done,
44622 /* 124047 */ // Label 3749: @124047
44623 /* 124047 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3750*/ GIMT_Encode4(124107), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3721 //
44624 /* 124054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44625 /* 124058 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44626 /* 124062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44627 /* 124066 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
44628 /* 124066 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44629 /* 124069 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44630 /* 124073 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44631 /* 124078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu16),
44632 /* 124081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44633 /* 124083 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44634 /* 124085 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44635 /* 124087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44636 /* 124090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44637 /* 124096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44638 /* 124102 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44639 /* 124105 */ GIR_RootConstrainSelectedInstOperands,
44640 /* 124106 */ // GIR_Coverage, 3721,
44641 /* 124106 */ GIR_EraseRootFromParent_Done,
44642 /* 124107 */ // Label 3750: @124107
44643 /* 124107 */ GIM_Reject,
44644 /* 124108 */ // Label 3745: @124108
44645 /* 124108 */ GIM_Reject,
44646 /* 124109 */ // Label 3734: @124109
44647 /* 124109 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3751*/ GIMT_Encode4(124154), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1366 //
44648 /* 124116 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
44649 /* 124119 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
44650 /* 124122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44651 /* 124126 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44652 /* 124130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44653 /* 124134 */ // (umax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
44654 /* 124134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv2i32),
44655 /* 124137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44656 /* 124139 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44657 /* 124141 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44658 /* 124143 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44659 /* 124146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44660 /* 124152 */ GIR_RootConstrainSelectedInstOperands,
44661 /* 124153 */ // GIR_Coverage, 1366,
44662 /* 124153 */ GIR_EraseRootFromParent_Done,
44663 /* 124154 */ // Label 3751: @124154
44664 /* 124154 */ GIM_Reject,
44665 /* 124155 */ // Label 3735: @124155
44666 /* 124155 */ GIM_Try, /*On fail goto*//*Label 3752*/ GIMT_Encode4(124392),
44667 /* 124160 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44668 /* 124163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
44669 /* 124166 */ GIM_Try, /*On fail goto*//*Label 3753*/ GIMT_Encode4(124292),
44670 /* 124171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44671 /* 124175 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3754*/ GIMT_Encode4(124233), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 6666 //
44672 /* 124182 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44673 /* 124186 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44674 /* 124190 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
44675 /* 124194 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44676 /* 124199 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44677 /* 124203 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44678 /* 124205 */ // (umax:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
44679 /* 124205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32),
44680 /* 124208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44681 /* 124210 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
44682 /* 124212 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44683 /* 124216 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44684 /* 124219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44685 /* 124225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44686 /* 124231 */ GIR_RootConstrainSelectedInstOperands,
44687 /* 124232 */ // GIR_Coverage, 6666,
44688 /* 124232 */ GIR_EraseRootFromParent_Done,
44689 /* 124233 */ // Label 3754: @124233
44690 /* 124233 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3755*/ GIMT_Encode4(124291), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4106 //
44691 /* 124240 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44692 /* 124244 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
44693 /* 124248 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
44694 /* 124252 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
44695 /* 124256 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44696 /* 124261 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44697 /* 124263 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
44698 /* 124263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32),
44699 /* 124266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44700 /* 124268 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
44701 /* 124270 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
44702 /* 124274 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44703 /* 124277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44704 /* 124283 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44705 /* 124289 */ GIR_RootConstrainSelectedInstOperands,
44706 /* 124290 */ // GIR_Coverage, 4106,
44707 /* 124290 */ GIR_EraseRootFromParent_Done,
44708 /* 124291 */ // Label 3755: @124291
44709 /* 124291 */ GIM_Reject,
44710 /* 124292 */ // Label 3753: @124292
44711 /* 124292 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3756*/ GIMT_Encode4(124331), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1368 //
44712 /* 124299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44713 /* 124303 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44714 /* 124307 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44715 /* 124311 */ // (umax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
44716 /* 124311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i32),
44717 /* 124314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44718 /* 124316 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
44719 /* 124318 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
44720 /* 124320 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44721 /* 124323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44722 /* 124329 */ GIR_RootConstrainSelectedInstOperands,
44723 /* 124330 */ // GIR_Coverage, 1368,
44724 /* 124330 */ GIR_EraseRootFromParent_Done,
44725 /* 124331 */ // Label 3756: @124331
44726 /* 124331 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3757*/ GIMT_Encode4(124391), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3724 //
44727 /* 124338 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44728 /* 124342 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44729 /* 124346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44730 /* 124350 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
44731 /* 124350 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44732 /* 124353 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44733 /* 124357 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44734 /* 124362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu32),
44735 /* 124365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44736 /* 124367 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
44737 /* 124369 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
44738 /* 124371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44739 /* 124374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44740 /* 124380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44741 /* 124386 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44742 /* 124389 */ GIR_RootConstrainSelectedInstOperands,
44743 /* 124390 */ // GIR_Coverage, 3724,
44744 /* 124390 */ GIR_EraseRootFromParent_Done,
44745 /* 124391 */ // Label 3757: @124391
44746 /* 124391 */ GIM_Reject,
44747 /* 124392 */ // Label 3752: @124392
44748 /* 124392 */ GIM_Reject,
44749 /* 124393 */ // Label 3736: @124393
44750 /* 124393 */ GIM_Reject,
44751 /* 124394 */ // Label 67: @124394
44752 /* 124394 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3764*/ GIMT_Encode4(124831),
44753 /* 124405 */ /*GILLT_v8s8*//*Label 3758*/ GIMT_Encode4(124429),
44754 /* 124409 */ /*GILLT_v16s8*//*Label 3759*/ GIMT_Encode4(124466),
44755 /* 124413 */ /*GILLT_v4s16*//*Label 3760*/ GIMT_Encode4(124563),
44756 /* 124417 */ /*GILLT_v8s16*//*Label 3761*/ GIMT_Encode4(124600),
44757 /* 124421 */ /*GILLT_v2s32*//*Label 3762*/ GIMT_Encode4(124697),
44758 /* 124425 */ /*GILLT_v4s32*//*Label 3763*/ GIMT_Encode4(124734),
44759 /* 124429 */ // Label 3758: @124429
44760 /* 124429 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3765*/ GIMT_Encode4(124465), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1670 //
44761 /* 124436 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
44762 /* 124439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44763 /* 124443 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44764 /* 124447 */ // (abs:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
44765 /* 124447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i8),
44766 /* 124450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44767 /* 124452 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44768 /* 124454 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44769 /* 124457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44770 /* 124463 */ GIR_RootConstrainSelectedInstOperands,
44771 /* 124464 */ // GIR_Coverage, 1670,
44772 /* 124464 */ GIR_EraseRootFromParent_Done,
44773 /* 124465 */ // Label 3765: @124465
44774 /* 124465 */ GIM_Reject,
44775 /* 124466 */ // Label 3759: @124466
44776 /* 124466 */ GIM_Try, /*On fail goto*//*Label 3766*/ GIMT_Encode4(124562),
44777 /* 124471 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
44778 /* 124474 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3767*/ GIMT_Encode4(124507), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1673 //
44779 /* 124481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44780 /* 124485 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44781 /* 124489 */ // (abs:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
44782 /* 124489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv16i8),
44783 /* 124492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44784 /* 124494 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44785 /* 124496 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44786 /* 124499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44787 /* 124505 */ GIR_RootConstrainSelectedInstOperands,
44788 /* 124506 */ // GIR_Coverage, 1673,
44789 /* 124506 */ GIR_EraseRootFromParent_Done,
44790 /* 124507 */ // Label 3767: @124507
44791 /* 124507 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3768*/ GIMT_Encode4(124561), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4057 //
44792 /* 124514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44793 /* 124518 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44794 /* 124522 */ // (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v) => (MVE_VABSs8:{ *:[v16i8] } ?:{ *:[v16i8] }:$v)
44795 /* 124522 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44796 /* 124525 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44797 /* 124529 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44798 /* 124534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs8),
44799 /* 124537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44800 /* 124539 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
44801 /* 124541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44802 /* 124544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44803 /* 124550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44804 /* 124556 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44805 /* 124559 */ GIR_RootConstrainSelectedInstOperands,
44806 /* 124560 */ // GIR_Coverage, 4057,
44807 /* 124560 */ GIR_EraseRootFromParent_Done,
44808 /* 124561 */ // Label 3768: @124561
44809 /* 124561 */ GIM_Reject,
44810 /* 124562 */ // Label 3766: @124562
44811 /* 124562 */ GIM_Reject,
44812 /* 124563 */ // Label 3760: @124563
44813 /* 124563 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3769*/ GIMT_Encode4(124599), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1671 //
44814 /* 124570 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
44815 /* 124573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44816 /* 124577 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44817 /* 124581 */ // (abs:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
44818 /* 124581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i16),
44819 /* 124584 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44820 /* 124586 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44821 /* 124588 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44822 /* 124591 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44823 /* 124597 */ GIR_RootConstrainSelectedInstOperands,
44824 /* 124598 */ // GIR_Coverage, 1671,
44825 /* 124598 */ GIR_EraseRootFromParent_Done,
44826 /* 124599 */ // Label 3769: @124599
44827 /* 124599 */ GIM_Reject,
44828 /* 124600 */ // Label 3761: @124600
44829 /* 124600 */ GIM_Try, /*On fail goto*//*Label 3770*/ GIMT_Encode4(124696),
44830 /* 124605 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
44831 /* 124608 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3771*/ GIMT_Encode4(124641), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1674 //
44832 /* 124615 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44833 /* 124619 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44834 /* 124623 */ // (abs:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
44835 /* 124623 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i16),
44836 /* 124626 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44837 /* 124628 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44838 /* 124630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44839 /* 124633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44840 /* 124639 */ GIR_RootConstrainSelectedInstOperands,
44841 /* 124640 */ // GIR_Coverage, 1674,
44842 /* 124640 */ GIR_EraseRootFromParent_Done,
44843 /* 124641 */ // Label 3771: @124641
44844 /* 124641 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3772*/ GIMT_Encode4(124695), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4063 //
44845 /* 124648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44846 /* 124652 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44847 /* 124656 */ // (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v) => (MVE_VABSs16:{ *:[v8i16] } ?:{ *:[v8i16] }:$v)
44848 /* 124656 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44849 /* 124659 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44850 /* 124663 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44851 /* 124668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs16),
44852 /* 124671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44853 /* 124673 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
44854 /* 124675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44855 /* 124678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44856 /* 124684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44857 /* 124690 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44858 /* 124693 */ GIR_RootConstrainSelectedInstOperands,
44859 /* 124694 */ // GIR_Coverage, 4063,
44860 /* 124694 */ GIR_EraseRootFromParent_Done,
44861 /* 124695 */ // Label 3772: @124695
44862 /* 124695 */ GIM_Reject,
44863 /* 124696 */ // Label 3770: @124696
44864 /* 124696 */ GIM_Reject,
44865 /* 124697 */ // Label 3762: @124697
44866 /* 124697 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3773*/ GIMT_Encode4(124733), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1672 //
44867 /* 124704 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
44868 /* 124707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44869 /* 124711 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44870 /* 124715 */ // (abs:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
44871 /* 124715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv2i32),
44872 /* 124718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44873 /* 124720 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44874 /* 124722 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44875 /* 124725 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44876 /* 124731 */ GIR_RootConstrainSelectedInstOperands,
44877 /* 124732 */ // GIR_Coverage, 1672,
44878 /* 124732 */ GIR_EraseRootFromParent_Done,
44879 /* 124733 */ // Label 3773: @124733
44880 /* 124733 */ GIM_Reject,
44881 /* 124734 */ // Label 3763: @124734
44882 /* 124734 */ GIM_Try, /*On fail goto*//*Label 3774*/ GIMT_Encode4(124830),
44883 /* 124739 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44884 /* 124742 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3775*/ GIMT_Encode4(124775), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1675 //
44885 /* 124749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44886 /* 124753 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44887 /* 124757 */ // (abs:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
44888 /* 124757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i32),
44889 /* 124760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44890 /* 124762 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44891 /* 124764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44892 /* 124767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44893 /* 124773 */ GIR_RootConstrainSelectedInstOperands,
44894 /* 124774 */ // GIR_Coverage, 1675,
44895 /* 124774 */ GIR_EraseRootFromParent_Done,
44896 /* 124775 */ // Label 3775: @124775
44897 /* 124775 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3776*/ GIMT_Encode4(124829), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4069 //
44898 /* 124782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44899 /* 124786 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44900 /* 124790 */ // (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v) => (MVE_VABSs32:{ *:[v4i32] } ?:{ *:[v4i32] }:$v)
44901 /* 124790 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44902 /* 124793 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44903 /* 124797 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44904 /* 124802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs32),
44905 /* 124805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44906 /* 124807 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
44907 /* 124809 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44908 /* 124812 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44909 /* 124818 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44910 /* 124824 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44911 /* 124827 */ GIR_RootConstrainSelectedInstOperands,
44912 /* 124828 */ // GIR_Coverage, 4069,
44913 /* 124828 */ GIR_EraseRootFromParent_Done,
44914 /* 124829 */ // Label 3776: @124829
44915 /* 124829 */ GIM_Reject,
44916 /* 124830 */ // Label 3774: @124830
44917 /* 124830 */ GIM_Reject,
44918 /* 124831 */ // Label 3764: @124831
44919 /* 124831 */ GIM_Reject,
44920 /* 124832 */ // Label 68: @124832
44921 /* 124832 */ GIM_Try, /*On fail goto*//*Label 3777*/ GIMT_Encode4(124901),
44922 /* 124837 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
44923 /* 124840 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3778*/ GIMT_Encode4(124854), GIMT_Encode2(GIFBS_IsARM), // Rule ID 31 //
44924 /* 124847 */ // (br (bb:{ *:[Other] }):$target) => (B (bb:{ *:[Other] }):$target)
44925 /* 124847 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::B),
44926 /* 124852 */ GIR_RootConstrainSelectedInstOperands,
44927 /* 124853 */ // GIR_Coverage, 31,
44928 /* 124853 */ GIR_Done,
44929 /* 124854 */ // Label 3778: @124854
44930 /* 124854 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3779*/ GIMT_Encode4(124877), GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only), // Rule ID 282 //
44931 /* 124861 */ // (br (bb:{ *:[Other] }):$target) => (tB (bb:{ *:[Other] }):$target)
44932 /* 124861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tB),
44933 /* 124864 */ GIR_RootToRootCopy, /*OpIdx*/0, // target
44934 /* 124866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44935 /* 124869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44936 /* 124875 */ GIR_RootConstrainSelectedInstOperands,
44937 /* 124876 */ // GIR_Coverage, 282,
44938 /* 124876 */ GIR_EraseRootFromParent_Done,
44939 /* 124877 */ // Label 3779: @124877
44940 /* 124877 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3780*/ GIMT_Encode4(124900), GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb), // Rule ID 576 //
44941 /* 124884 */ // (br (bb:{ *:[Other] }):$target) => (t2B (bb:{ *:[Other] }):$target)
44942 /* 124884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2B),
44943 /* 124887 */ GIR_RootToRootCopy, /*OpIdx*/0, // target
44944 /* 124889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44945 /* 124892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44946 /* 124898 */ GIR_RootConstrainSelectedInstOperands,
44947 /* 124899 */ // GIR_Coverage, 576,
44948 /* 124899 */ GIR_EraseRootFromParent_Done,
44949 /* 124900 */ // Label 3780: @124900
44950 /* 124900 */ GIM_Reject,
44951 /* 124901 */ // Label 3777: @124901
44952 /* 124901 */ GIM_Reject,
44953 /* 124902 */ // Label 69: @124902
44954 /* 124902 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(11), /*)*//*default:*//*Label 3785*/ GIMT_Encode4(125177),
44955 /* 124913 */ /*GILLT_v8s8*//*Label 3781*/ GIMT_Encode4(124929),
44956 /* 124917 */ /*GILLT_v16s8*//*Label 3782*/ GIMT_Encode4(124991),
44957 /* 124921 */ /*GILLT_v4s16*//*Label 3783*/ GIMT_Encode4(125053),
44958 /* 124925 */ /*GILLT_v8s16*//*Label 3784*/ GIMT_Encode4(125115),
44959 /* 124929 */ // Label 3781: @124929
44960 /* 124929 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3786*/ GIMT_Encode4(124990), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1733 //
44961 /* 124936 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
44962 /* 124939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
44963 /* 124942 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
44964 /* 124945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44965 /* 124949 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44966 /* 124953 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44967 /* 124957 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
44968 /* 124961 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
44969 /* 124965 */ // MIs[1] Operand 1
44970 /* 124965 */ // No operand predicates
44971 /* 124965 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44972 /* 124967 */ // (vector_insert:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane)
44973 /* 124967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi8),
44974 /* 124970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V]
44975 /* 124972 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
44976 /* 124974 */ GIR_RootToRootCopy, /*OpIdx*/2, // R
44977 /* 124976 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
44978 /* 124979 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44979 /* 124982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44980 /* 124988 */ GIR_RootConstrainSelectedInstOperands,
44981 /* 124989 */ // GIR_Coverage, 1733,
44982 /* 124989 */ GIR_EraseRootFromParent_Done,
44983 /* 124990 */ // Label 3786: @124990
44984 /* 124990 */ GIM_Reject,
44985 /* 124991 */ // Label 3782: @124991
44986 /* 124991 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3787*/ GIMT_Encode4(125052), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3832 //
44987 /* 124998 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
44988 /* 125001 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
44989 /* 125004 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
44990 /* 125007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44991 /* 125011 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44992 /* 125015 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
44993 /* 125019 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
44994 /* 125023 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
44995 /* 125027 */ // MIs[1] Operand 1
44996 /* 125027 */ // No operand predicates
44997 /* 125027 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44998 /* 125029 */ // (vector_insert:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane)
44999 /* 125029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_8),
45000 /* 125032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45001 /* 125034 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
45002 /* 125036 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2
45003 /* 125038 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
45004 /* 125041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45005 /* 125044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45006 /* 125050 */ GIR_RootConstrainSelectedInstOperands,
45007 /* 125051 */ // GIR_Coverage, 3832,
45008 /* 125051 */ GIR_EraseRootFromParent_Done,
45009 /* 125052 */ // Label 3787: @125052
45010 /* 125052 */ GIM_Reject,
45011 /* 125053 */ // Label 3783: @125053
45012 /* 125053 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3788*/ GIMT_Encode4(125114), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1734 //
45013 /* 125060 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45014 /* 125063 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
45015 /* 125066 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
45016 /* 125069 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45017 /* 125073 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45018 /* 125077 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45019 /* 125081 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
45020 /* 125085 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45021 /* 125089 */ // MIs[1] Operand 1
45022 /* 125089 */ // No operand predicates
45023 /* 125089 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45024 /* 125091 */ // (vector_insert:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane)
45025 /* 125091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi16),
45026 /* 125094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V]
45027 /* 125096 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
45028 /* 125098 */ GIR_RootToRootCopy, /*OpIdx*/2, // R
45029 /* 125100 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
45030 /* 125103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45031 /* 125106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45032 /* 125112 */ GIR_RootConstrainSelectedInstOperands,
45033 /* 125113 */ // GIR_Coverage, 1734,
45034 /* 125113 */ GIR_EraseRootFromParent_Done,
45035 /* 125114 */ // Label 3788: @125114
45036 /* 125114 */ GIM_Reject,
45037 /* 125115 */ // Label 3784: @125115
45038 /* 125115 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3789*/ GIMT_Encode4(125176), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3833 //
45039 /* 125122 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45040 /* 125125 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
45041 /* 125128 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
45042 /* 125131 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45043 /* 125135 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45044 /* 125139 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
45045 /* 125143 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
45046 /* 125147 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45047 /* 125151 */ // MIs[1] Operand 1
45048 /* 125151 */ // No operand predicates
45049 /* 125151 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45050 /* 125153 */ // (vector_insert:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane)
45051 /* 125153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_16),
45052 /* 125156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45053 /* 125158 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
45054 /* 125160 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2
45055 /* 125162 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
45056 /* 125165 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45057 /* 125168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45058 /* 125174 */ GIR_RootConstrainSelectedInstOperands,
45059 /* 125175 */ // GIR_Coverage, 3833,
45060 /* 125175 */ GIR_EraseRootFromParent_Done,
45061 /* 125176 */ // Label 3789: @125176
45062 /* 125176 */ GIM_Reject,
45063 /* 125177 */ // Label 3785: @125177
45064 /* 125177 */ GIM_Reject,
45065 /* 125178 */ // Label 70: @125178
45066 /* 125178 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3790*/ GIMT_Encode4(125233), GIMT_Encode2(GIFBS_HasFPRegs_HasFastVGETLNi32), // Rule ID 1732 //
45067 /* 125185 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
45068 /* 125188 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45069 /* 125191 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
45070 /* 125194 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45071 /* 125198 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45072 /* 125202 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
45073 /* 125206 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
45074 /* 125210 */ // MIs[1] Operand 1
45075 /* 125210 */ // No operand predicates
45076 /* 125210 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45077 /* 125212 */ // (extractelt:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane) => (VGETLNi32:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane)
45078 /* 125212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VGETLNi32),
45079 /* 125215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[R]
45080 /* 125217 */ GIR_RootToRootCopy, /*OpIdx*/1, // V
45081 /* 125219 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
45082 /* 125222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45083 /* 125225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45084 /* 125231 */ GIR_RootConstrainSelectedInstOperands,
45085 /* 125232 */ // GIR_Coverage, 1732,
45086 /* 125232 */ GIR_EraseRootFromParent_Done,
45087 /* 125233 */ // Label 3790: @125233
45088 /* 125233 */ GIM_Reject,
45089 /* 125234 */ // Label 71: @125234
45090 /* 125234 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3798*/ GIMT_Encode4(125771),
45091 /* 125245 */ /*GILLT_s32*//*Label 3791*/ GIMT_Encode4(125293), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45092 /* 125269 */ /*GILLT_v8s8*//*Label 3792*/ GIMT_Encode4(125369),
45093 /* 125273 */ /*GILLT_v16s8*//*Label 3793*/ GIMT_Encode4(125406),
45094 /* 125277 */ /*GILLT_v4s16*//*Label 3794*/ GIMT_Encode4(125503),
45095 /* 125281 */ /*GILLT_v8s16*//*Label 3795*/ GIMT_Encode4(125540),
45096 /* 125285 */ /*GILLT_v2s32*//*Label 3796*/ GIMT_Encode4(125637),
45097 /* 125289 */ /*GILLT_v4s32*//*Label 3797*/ GIMT_Encode4(125674),
45098 /* 125293 */ // Label 3791: @125293
45099 /* 125293 */ GIM_Try, /*On fail goto*//*Label 3799*/ GIMT_Encode4(125368),
45100 /* 125298 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45101 /* 125301 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3800*/ GIMT_Encode4(125334), GIMT_Encode2(GIFBS_HasV5T_IsARM), // Rule ID 196 //
45102 /* 125308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45103 /* 125312 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45104 /* 125316 */ // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
45105 /* 125316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLZ),
45106 /* 125319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45107 /* 125321 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
45108 /* 125323 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45109 /* 125326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45110 /* 125332 */ GIR_RootConstrainSelectedInstOperands,
45111 /* 125333 */ // GIR_Coverage, 196,
45112 /* 125333 */ GIR_EraseRootFromParent_Done,
45113 /* 125334 */ // Label 3800: @125334
45114 /* 125334 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3801*/ GIMT_Encode4(125367), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 533 //
45115 /* 125341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
45116 /* 125345 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
45117 /* 125349 */ // (ctlz:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2CLZ:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
45118 /* 125349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLZ),
45119 /* 125352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45120 /* 125354 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
45121 /* 125356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45122 /* 125359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45123 /* 125365 */ GIR_RootConstrainSelectedInstOperands,
45124 /* 125366 */ // GIR_Coverage, 533,
45125 /* 125366 */ GIR_EraseRootFromParent_Done,
45126 /* 125367 */ // Label 3801: @125367
45127 /* 125367 */ GIM_Reject,
45128 /* 125368 */ // Label 3799: @125368
45129 /* 125368 */ GIM_Reject,
45130 /* 125369 */ // Label 3792: @125369
45131 /* 125369 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3802*/ GIMT_Encode4(125405), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1708 //
45132 /* 125376 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
45133 /* 125379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45134 /* 125383 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45135 /* 125387 */ // (ctlz:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLZv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
45136 /* 125387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i8),
45137 /* 125390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45138 /* 125392 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45139 /* 125394 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45140 /* 125397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45141 /* 125403 */ GIR_RootConstrainSelectedInstOperands,
45142 /* 125404 */ // GIR_Coverage, 1708,
45143 /* 125404 */ GIR_EraseRootFromParent_Done,
45144 /* 125405 */ // Label 3802: @125405
45145 /* 125405 */ GIM_Reject,
45146 /* 125406 */ // Label 3793: @125406
45147 /* 125406 */ GIM_Try, /*On fail goto*//*Label 3803*/ GIMT_Encode4(125502),
45148 /* 125411 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
45149 /* 125414 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3804*/ GIMT_Encode4(125447), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1711 //
45150 /* 125421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45151 /* 125425 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45152 /* 125429 */ // (ctlz:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLZv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
45153 /* 125429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv16i8),
45154 /* 125432 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45155 /* 125434 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45156 /* 125436 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45157 /* 125439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45158 /* 125445 */ GIR_RootConstrainSelectedInstOperands,
45159 /* 125446 */ // GIR_Coverage, 1711,
45160 /* 125446 */ GIR_EraseRootFromParent_Done,
45161 /* 125447 */ // Label 3804: @125447
45162 /* 125447 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3805*/ GIMT_Encode4(125501), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4051 //
45163 /* 125454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45164 /* 125458 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45165 /* 125462 */ // (ctlz:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLZs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)
45166 /* 125462 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45167 /* 125465 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45168 /* 125469 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45169 /* 125474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs8),
45170 /* 125477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45171 /* 125479 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
45172 /* 125481 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45173 /* 125484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45174 /* 125490 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45175 /* 125496 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45176 /* 125499 */ GIR_RootConstrainSelectedInstOperands,
45177 /* 125500 */ // GIR_Coverage, 4051,
45178 /* 125500 */ GIR_EraseRootFromParent_Done,
45179 /* 125501 */ // Label 3805: @125501
45180 /* 125501 */ GIM_Reject,
45181 /* 125502 */ // Label 3803: @125502
45182 /* 125502 */ GIM_Reject,
45183 /* 125503 */ // Label 3794: @125503
45184 /* 125503 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3806*/ GIMT_Encode4(125539), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1709 //
45185 /* 125510 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45186 /* 125513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45187 /* 125517 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45188 /* 125521 */ // (ctlz:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLZv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
45189 /* 125521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i16),
45190 /* 125524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45191 /* 125526 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45192 /* 125528 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45193 /* 125531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45194 /* 125537 */ GIR_RootConstrainSelectedInstOperands,
45195 /* 125538 */ // GIR_Coverage, 1709,
45196 /* 125538 */ GIR_EraseRootFromParent_Done,
45197 /* 125539 */ // Label 3806: @125539
45198 /* 125539 */ GIM_Reject,
45199 /* 125540 */ // Label 3795: @125540
45200 /* 125540 */ GIM_Try, /*On fail goto*//*Label 3807*/ GIMT_Encode4(125636),
45201 /* 125545 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45202 /* 125548 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3808*/ GIMT_Encode4(125581), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1712 //
45203 /* 125555 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45204 /* 125559 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45205 /* 125563 */ // (ctlz:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLZv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
45206 /* 125563 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i16),
45207 /* 125566 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45208 /* 125568 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45209 /* 125570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45210 /* 125573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45211 /* 125579 */ GIR_RootConstrainSelectedInstOperands,
45212 /* 125580 */ // GIR_Coverage, 1712,
45213 /* 125580 */ GIR_EraseRootFromParent_Done,
45214 /* 125581 */ // Label 3808: @125581
45215 /* 125581 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3809*/ GIMT_Encode4(125635), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4053 //
45216 /* 125588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45217 /* 125592 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45218 /* 125596 */ // (ctlz:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLZs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)
45219 /* 125596 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45220 /* 125599 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45221 /* 125603 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45222 /* 125608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs16),
45223 /* 125611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45224 /* 125613 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
45225 /* 125615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45226 /* 125618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45227 /* 125624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45228 /* 125630 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45229 /* 125633 */ GIR_RootConstrainSelectedInstOperands,
45230 /* 125634 */ // GIR_Coverage, 4053,
45231 /* 125634 */ GIR_EraseRootFromParent_Done,
45232 /* 125635 */ // Label 3809: @125635
45233 /* 125635 */ GIM_Reject,
45234 /* 125636 */ // Label 3807: @125636
45235 /* 125636 */ GIM_Reject,
45236 /* 125637 */ // Label 3796: @125637
45237 /* 125637 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3810*/ GIMT_Encode4(125673), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1710 //
45238 /* 125644 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45239 /* 125647 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45240 /* 125651 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45241 /* 125655 */ // (ctlz:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLZv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
45242 /* 125655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv2i32),
45243 /* 125658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45244 /* 125660 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45245 /* 125662 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45246 /* 125665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45247 /* 125671 */ GIR_RootConstrainSelectedInstOperands,
45248 /* 125672 */ // GIR_Coverage, 1710,
45249 /* 125672 */ GIR_EraseRootFromParent_Done,
45250 /* 125673 */ // Label 3810: @125673
45251 /* 125673 */ GIM_Reject,
45252 /* 125674 */ // Label 3797: @125674
45253 /* 125674 */ GIM_Try, /*On fail goto*//*Label 3811*/ GIMT_Encode4(125770),
45254 /* 125679 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45255 /* 125682 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3812*/ GIMT_Encode4(125715), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1713 //
45256 /* 125689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45257 /* 125693 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45258 /* 125697 */ // (ctlz:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLZv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
45259 /* 125697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i32),
45260 /* 125700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45261 /* 125702 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45262 /* 125704 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45263 /* 125707 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45264 /* 125713 */ GIR_RootConstrainSelectedInstOperands,
45265 /* 125714 */ // GIR_Coverage, 1713,
45266 /* 125714 */ GIR_EraseRootFromParent_Done,
45267 /* 125715 */ // Label 3812: @125715
45268 /* 125715 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3813*/ GIMT_Encode4(125769), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4055 //
45269 /* 125722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45270 /* 125726 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45271 /* 125730 */ // (ctlz:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLZs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)
45272 /* 125730 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45273 /* 125733 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45274 /* 125737 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45275 /* 125742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs32),
45276 /* 125745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45277 /* 125747 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
45278 /* 125749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45279 /* 125752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45280 /* 125758 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45281 /* 125764 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45282 /* 125767 */ GIR_RootConstrainSelectedInstOperands,
45283 /* 125768 */ // GIR_Coverage, 4055,
45284 /* 125768 */ GIR_EraseRootFromParent_Done,
45285 /* 125769 */ // Label 3813: @125769
45286 /* 125769 */ GIM_Reject,
45287 /* 125770 */ // Label 3811: @125770
45288 /* 125770 */ GIM_Reject,
45289 /* 125771 */ // Label 3798: @125771
45290 /* 125771 */ GIM_Reject,
45291 /* 125772 */ // Label 72: @125772
45292 /* 125772 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(13), /*)*//*default:*//*Label 3820*/ GIMT_Encode4(126209),
45293 /* 125783 */ /*GILLT_v8s8*//*Label 3814*/ GIMT_Encode4(125807),
45294 /* 125787 */ /*GILLT_v16s8*//*Label 3815*/ GIMT_Encode4(125844),
45295 /* 125791 */ /*GILLT_v4s16*//*Label 3816*/ GIMT_Encode4(125941),
45296 /* 125795 */ /*GILLT_v8s16*//*Label 3817*/ GIMT_Encode4(125978),
45297 /* 125799 */ /*GILLT_v2s32*//*Label 3818*/ GIMT_Encode4(126075),
45298 /* 125803 */ /*GILLT_v4s32*//*Label 3819*/ GIMT_Encode4(126112),
45299 /* 125807 */ // Label 3814: @125807
45300 /* 125807 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3821*/ GIMT_Encode4(125843), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1702 //
45301 /* 125814 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
45302 /* 125817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45303 /* 125821 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45304 /* 125825 */ // (ctls:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
45305 /* 125825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i8),
45306 /* 125828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45307 /* 125830 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45308 /* 125832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45309 /* 125835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45310 /* 125841 */ GIR_RootConstrainSelectedInstOperands,
45311 /* 125842 */ // GIR_Coverage, 1702,
45312 /* 125842 */ GIR_EraseRootFromParent_Done,
45313 /* 125843 */ // Label 3821: @125843
45314 /* 125843 */ GIM_Reject,
45315 /* 125844 */ // Label 3815: @125844
45316 /* 125844 */ GIM_Try, /*On fail goto*//*Label 3822*/ GIMT_Encode4(125940),
45317 /* 125849 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
45318 /* 125852 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3823*/ GIMT_Encode4(125885), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1705 //
45319 /* 125859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45320 /* 125863 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45321 /* 125867 */ // (ctls:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
45322 /* 125867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv16i8),
45323 /* 125870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45324 /* 125872 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45325 /* 125874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45326 /* 125877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45327 /* 125883 */ GIR_RootConstrainSelectedInstOperands,
45328 /* 125884 */ // GIR_Coverage, 1705,
45329 /* 125884 */ GIR_EraseRootFromParent_Done,
45330 /* 125885 */ // Label 3823: @125885
45331 /* 125885 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3824*/ GIMT_Encode4(125939), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4045 //
45332 /* 125892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45333 /* 125896 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45334 /* 125900 */ // (ctls:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLSs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)
45335 /* 125900 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45336 /* 125903 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45337 /* 125907 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45338 /* 125912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs8),
45339 /* 125915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45340 /* 125917 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
45341 /* 125919 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45342 /* 125922 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45343 /* 125928 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45344 /* 125934 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45345 /* 125937 */ GIR_RootConstrainSelectedInstOperands,
45346 /* 125938 */ // GIR_Coverage, 4045,
45347 /* 125938 */ GIR_EraseRootFromParent_Done,
45348 /* 125939 */ // Label 3824: @125939
45349 /* 125939 */ GIM_Reject,
45350 /* 125940 */ // Label 3822: @125940
45351 /* 125940 */ GIM_Reject,
45352 /* 125941 */ // Label 3816: @125941
45353 /* 125941 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3825*/ GIMT_Encode4(125977), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1703 //
45354 /* 125948 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45355 /* 125951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45356 /* 125955 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45357 /* 125959 */ // (ctls:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
45358 /* 125959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i16),
45359 /* 125962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45360 /* 125964 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45361 /* 125966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45362 /* 125969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45363 /* 125975 */ GIR_RootConstrainSelectedInstOperands,
45364 /* 125976 */ // GIR_Coverage, 1703,
45365 /* 125976 */ GIR_EraseRootFromParent_Done,
45366 /* 125977 */ // Label 3825: @125977
45367 /* 125977 */ GIM_Reject,
45368 /* 125978 */ // Label 3817: @125978
45369 /* 125978 */ GIM_Try, /*On fail goto*//*Label 3826*/ GIMT_Encode4(126074),
45370 /* 125983 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45371 /* 125986 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3827*/ GIMT_Encode4(126019), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1706 //
45372 /* 125993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45373 /* 125997 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45374 /* 126001 */ // (ctls:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
45375 /* 126001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i16),
45376 /* 126004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45377 /* 126006 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45378 /* 126008 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45379 /* 126011 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45380 /* 126017 */ GIR_RootConstrainSelectedInstOperands,
45381 /* 126018 */ // GIR_Coverage, 1706,
45382 /* 126018 */ GIR_EraseRootFromParent_Done,
45383 /* 126019 */ // Label 3827: @126019
45384 /* 126019 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3828*/ GIMT_Encode4(126073), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4047 //
45385 /* 126026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45386 /* 126030 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45387 /* 126034 */ // (ctls:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLSs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)
45388 /* 126034 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45389 /* 126037 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45390 /* 126041 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45391 /* 126046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs16),
45392 /* 126049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45393 /* 126051 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
45394 /* 126053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45395 /* 126056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45396 /* 126062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45397 /* 126068 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45398 /* 126071 */ GIR_RootConstrainSelectedInstOperands,
45399 /* 126072 */ // GIR_Coverage, 4047,
45400 /* 126072 */ GIR_EraseRootFromParent_Done,
45401 /* 126073 */ // Label 3828: @126073
45402 /* 126073 */ GIM_Reject,
45403 /* 126074 */ // Label 3826: @126074
45404 /* 126074 */ GIM_Reject,
45405 /* 126075 */ // Label 3818: @126075
45406 /* 126075 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3829*/ GIMT_Encode4(126111), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1704 //
45407 /* 126082 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45408 /* 126085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45409 /* 126089 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45410 /* 126093 */ // (ctls:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
45411 /* 126093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv2i32),
45412 /* 126096 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45413 /* 126098 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45414 /* 126100 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45415 /* 126103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45416 /* 126109 */ GIR_RootConstrainSelectedInstOperands,
45417 /* 126110 */ // GIR_Coverage, 1704,
45418 /* 126110 */ GIR_EraseRootFromParent_Done,
45419 /* 126111 */ // Label 3829: @126111
45420 /* 126111 */ GIM_Reject,
45421 /* 126112 */ // Label 3819: @126112
45422 /* 126112 */ GIM_Try, /*On fail goto*//*Label 3830*/ GIMT_Encode4(126208),
45423 /* 126117 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45424 /* 126120 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3831*/ GIMT_Encode4(126153), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1707 //
45425 /* 126127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45426 /* 126131 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45427 /* 126135 */ // (ctls:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
45428 /* 126135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i32),
45429 /* 126138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45430 /* 126140 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45431 /* 126142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45432 /* 126145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45433 /* 126151 */ GIR_RootConstrainSelectedInstOperands,
45434 /* 126152 */ // GIR_Coverage, 1707,
45435 /* 126152 */ GIR_EraseRootFromParent_Done,
45436 /* 126153 */ // Label 3831: @126153
45437 /* 126153 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3832*/ GIMT_Encode4(126207), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 4049 //
45438 /* 126160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45439 /* 126164 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45440 /* 126168 */ // (ctls:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLSs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)
45441 /* 126168 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45442 /* 126171 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45443 /* 126175 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45444 /* 126180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs32),
45445 /* 126183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45446 /* 126185 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
45447 /* 126187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45448 /* 126190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45449 /* 126196 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45450 /* 126202 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45451 /* 126205 */ GIR_RootConstrainSelectedInstOperands,
45452 /* 126206 */ // GIR_Coverage, 4049,
45453 /* 126206 */ GIR_EraseRootFromParent_Done,
45454 /* 126207 */ // Label 3832: @126207
45455 /* 126207 */ GIM_Reject,
45456 /* 126208 */ // Label 3830: @126208
45457 /* 126208 */ GIM_Reject,
45458 /* 126209 */ // Label 3820: @126209
45459 /* 126209 */ GIM_Reject,
45460 /* 126210 */ // Label 73: @126210
45461 /* 126210 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(9), /*)*//*default:*//*Label 3835*/ GIMT_Encode4(126303),
45462 /* 126221 */ /*GILLT_v8s8*//*Label 3833*/ GIMT_Encode4(126229),
45463 /* 126225 */ /*GILLT_v16s8*//*Label 3834*/ GIMT_Encode4(126266),
45464 /* 126229 */ // Label 3833: @126229
45465 /* 126229 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3836*/ GIMT_Encode4(126265), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1714 //
45466 /* 126236 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
45467 /* 126239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45468 /* 126243 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45469 /* 126247 */ // (ctpop:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCNTd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
45470 /* 126247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTd),
45471 /* 126250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45472 /* 126252 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45473 /* 126254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45474 /* 126257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45475 /* 126263 */ GIR_RootConstrainSelectedInstOperands,
45476 /* 126264 */ // GIR_Coverage, 1714,
45477 /* 126264 */ GIR_EraseRootFromParent_Done,
45478 /* 126265 */ // Label 3836: @126265
45479 /* 126265 */ GIM_Reject,
45480 /* 126266 */ // Label 3834: @126266
45481 /* 126266 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3837*/ GIMT_Encode4(126302), GIMT_Encode2(GIFBS_HasNEON), // Rule ID 1715 //
45482 /* 126273 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
45483 /* 126276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45484 /* 126280 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45485 /* 126284 */ // (ctpop:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCNTq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
45486 /* 126284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTq),
45487 /* 126287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45488 /* 126289 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45489 /* 126291 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45490 /* 126294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45491 /* 126300 */ GIR_RootConstrainSelectedInstOperands,
45492 /* 126301 */ // GIR_Coverage, 1715,
45493 /* 126301 */ GIR_EraseRootFromParent_Done,
45494 /* 126302 */ // Label 3837: @126302
45495 /* 126302 */ GIM_Reject,
45496 /* 126303 */ // Label 3835: @126303
45497 /* 126303 */ GIM_Reject,
45498 /* 126304 */ // Label 74: @126304
45499 /* 126304 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3841*/ GIMT_Encode4(126588),
45500 /* 126315 */ /*GILLT_s32*//*Label 3838*/ GIMT_Encode4(126363), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45501 /* 126351 */ /*GILLT_v8s16*//*Label 3839*/ GIMT_Encode4(126472), GIMT_Encode4(0),
45502 /* 126359 */ /*GILLT_v4s32*//*Label 3840*/ GIMT_Encode4(126530),
45503 /* 126363 */ // Label 3838: @126363
45504 /* 126363 */ GIM_Try, /*On fail goto*//*Label 3842*/ GIMT_Encode4(126471),
45505 /* 126368 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45506 /* 126371 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3843*/ GIMT_Encode4(126404), GIMT_Encode2(GIFBS_HasV6_IsARM), // Rule ID 198 //
45507 /* 126378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45508 /* 126382 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45509 /* 126386 */ // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (REV:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
45510 /* 126386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV),
45511 /* 126389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45512 /* 126391 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
45513 /* 126393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45514 /* 126396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45515 /* 126402 */ GIR_RootConstrainSelectedInstOperands,
45516 /* 126403 */ // GIR_Coverage, 198,
45517 /* 126403 */ GIR_EraseRootFromParent_Done,
45518 /* 126404 */ // Label 3843: @126404
45519 /* 126404 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3844*/ GIMT_Encode4(126437), GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only), // Rule ID 325 //
45520 /* 126411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
45521 /* 126415 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
45522 /* 126419 */ // (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) => (tREV:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
45523 /* 126419 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV),
45524 /* 126422 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45525 /* 126424 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
45526 /* 126426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45527 /* 126429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45528 /* 126435 */ GIR_RootConstrainSelectedInstOperands,
45529 /* 126436 */ // GIR_Coverage, 325,
45530 /* 126436 */ GIR_EraseRootFromParent_Done,
45531 /* 126437 */ // Label 3844: @126437
45532 /* 126437 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3845*/ GIMT_Encode4(126470), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 535 //
45533 /* 126444 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
45534 /* 126448 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
45535 /* 126452 */ // (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2REV:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
45536 /* 126452 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV),
45537 /* 126455 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45538 /* 126457 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
45539 /* 126459 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45540 /* 126462 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45541 /* 126468 */ GIR_RootConstrainSelectedInstOperands,
45542 /* 126469 */ // GIR_Coverage, 535,
45543 /* 126469 */ GIR_EraseRootFromParent_Done,
45544 /* 126470 */ // Label 3845: @126470
45545 /* 126470 */ GIM_Reject,
45546 /* 126471 */ // Label 3842: @126471
45547 /* 126471 */ GIM_Reject,
45548 /* 126472 */ // Label 3839: @126472
45549 /* 126472 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3846*/ GIMT_Encode4(126529), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3727 //
45550 /* 126479 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45551 /* 126482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45552 /* 126486 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45553 /* 126490 */ // (bswap:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src)
45554 /* 126490 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45555 /* 126493 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45556 /* 126497 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45557 /* 126502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
45558 /* 126505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45559 /* 126507 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
45560 /* 126509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45561 /* 126512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45562 /* 126518 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45563 /* 126524 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45564 /* 126527 */ GIR_RootConstrainSelectedInstOperands,
45565 /* 126528 */ // GIR_Coverage, 3727,
45566 /* 126528 */ GIR_EraseRootFromParent_Done,
45567 /* 126529 */ // Label 3846: @126529
45568 /* 126529 */ GIM_Reject,
45569 /* 126530 */ // Label 3840: @126530
45570 /* 126530 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3847*/ GIMT_Encode4(126587), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3728 //
45571 /* 126537 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45572 /* 126540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45573 /* 126544 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45574 /* 126548 */ // (bswap:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src)
45575 /* 126548 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45576 /* 126551 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45577 /* 126555 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45578 /* 126560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
45579 /* 126563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45580 /* 126565 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
45581 /* 126567 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45582 /* 126570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45583 /* 126576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45584 /* 126582 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45585 /* 126585 */ GIR_RootConstrainSelectedInstOperands,
45586 /* 126586 */ // GIR_Coverage, 3728,
45587 /* 126586 */ GIR_EraseRootFromParent_Done,
45588 /* 126587 */ // Label 3847: @126587
45589 /* 126587 */ GIM_Reject,
45590 /* 126588 */ // Label 3841: @126588
45591 /* 126588 */ GIM_Reject,
45592 /* 126589 */ // Label 75: @126589
45593 /* 126589 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 3852*/ GIMT_Encode4(127003),
45594 /* 126600 */ /*GILLT_s32*//*Label 3848*/ GIMT_Encode4(126648), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45595 /* 126628 */ /*GILLT_v16s8*//*Label 3849*/ GIMT_Encode4(126724), GIMT_Encode4(0),
45596 /* 126636 */ /*GILLT_v8s16*//*Label 3850*/ GIMT_Encode4(126817), GIMT_Encode4(0),
45597 /* 126644 */ /*GILLT_v4s32*//*Label 3851*/ GIMT_Encode4(126910),
45598 /* 126648 */ // Label 3848: @126648
45599 /* 126648 */ GIM_Try, /*On fail goto*//*Label 3853*/ GIMT_Encode4(126723),
45600 /* 126653 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45601 /* 126656 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3854*/ GIMT_Encode4(126689), GIMT_Encode2(GIFBS_HasV6T2_IsARM), // Rule ID 197 //
45602 /* 126663 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45603 /* 126667 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45604 /* 126671 */ // (bitreverse:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (RBIT:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
45605 /* 126671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RBIT),
45606 /* 126674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45607 /* 126676 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
45608 /* 126678 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45609 /* 126681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45610 /* 126687 */ GIR_RootConstrainSelectedInstOperands,
45611 /* 126688 */ // GIR_Coverage, 197,
45612 /* 126688 */ GIR_EraseRootFromParent_Done,
45613 /* 126689 */ // Label 3854: @126689
45614 /* 126689 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3855*/ GIMT_Encode4(126722), GIMT_Encode2(GIFBS_IsThumb2), // Rule ID 534 //
45615 /* 126696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
45616 /* 126700 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
45617 /* 126704 */ // (bitreverse:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2RBIT:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
45618 /* 126704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RBIT),
45619 /* 126707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
45620 /* 126709 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
45621 /* 126711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45622 /* 126714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45623 /* 126720 */ GIR_RootConstrainSelectedInstOperands,
45624 /* 126721 */ // GIR_Coverage, 534,
45625 /* 126721 */ GIR_EraseRootFromParent_Done,
45626 /* 126722 */ // Label 3855: @126722
45627 /* 126722 */ GIM_Reject,
45628 /* 126723 */ // Label 3853: @126723
45629 /* 126723 */ GIM_Reject,
45630 /* 126724 */ // Label 3849: @126724
45631 /* 126724 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3856*/ GIMT_Encode4(126816), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5280 //
45632 /* 126731 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
45633 /* 126734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45634 /* 126738 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45635 /* 126742 */ // (bitreverse:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1, (t2MOVi:{ *:[i32] } 8:{ *:[i32] }))
45636 /* 126742 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
45637 /* 126745 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45638 /* 126749 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45639 /* 126754 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45640 /* 126757 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
45641 /* 126761 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45642 /* 126766 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
45643 /* 126769 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
45644 /* 126772 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45645 /* 126778 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45646 /* 126784 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45647 /* 126786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8),
45648 /* 126789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45649 /* 126791 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1
45650 /* 126793 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45651 /* 126796 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45652 /* 126799 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45653 /* 126805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45654 /* 126811 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
45655 /* 126814 */ GIR_RootConstrainSelectedInstOperands,
45656 /* 126815 */ // GIR_Coverage, 5280,
45657 /* 126815 */ GIR_EraseRootFromParent_Done,
45658 /* 126816 */ // Label 3856: @126816
45659 /* 126816 */ GIM_Reject,
45660 /* 126817 */ // Label 3850: @126817
45661 /* 126817 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3857*/ GIMT_Encode4(126909), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5282 //
45662 /* 126824 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45663 /* 126827 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45664 /* 126831 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45665 /* 126835 */ // (bitreverse:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1, (t2MOVi:{ *:[i32] } 16:{ *:[i32] }))
45666 /* 126835 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
45667 /* 126838 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45668 /* 126842 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45669 /* 126847 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45670 /* 126850 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
45671 /* 126854 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45672 /* 126859 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/16,
45673 /* 126862 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
45674 /* 126865 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45675 /* 126871 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45676 /* 126877 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45677 /* 126879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16),
45678 /* 126882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45679 /* 126884 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1
45680 /* 126886 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45681 /* 126889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45682 /* 126892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45683 /* 126898 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45684 /* 126904 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
45685 /* 126907 */ GIR_RootConstrainSelectedInstOperands,
45686 /* 126908 */ // GIR_Coverage, 5282,
45687 /* 126908 */ GIR_EraseRootFromParent_Done,
45688 /* 126909 */ // Label 3857: @126909
45689 /* 126909 */ GIM_Reject,
45690 /* 126910 */ // Label 3851: @126910
45691 /* 126910 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3858*/ GIMT_Encode4(127002), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 5281 //
45692 /* 126917 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45693 /* 126920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45694 /* 126924 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45695 /* 126928 */ // (bitreverse:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1, (t2MOVi:{ *:[i32] } 32:{ *:[i32] }))
45696 /* 126928 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
45697 /* 126931 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45698 /* 126935 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45699 /* 126940 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45700 /* 126943 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
45701 /* 126947 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45702 /* 126952 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/32,
45703 /* 126955 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
45704 /* 126958 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45705 /* 126964 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45706 /* 126970 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45707 /* 126972 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32),
45708 /* 126975 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45709 /* 126977 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1
45710 /* 126979 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45711 /* 126982 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45712 /* 126985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45713 /* 126991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45714 /* 126997 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
45715 /* 127000 */ GIR_RootConstrainSelectedInstOperands,
45716 /* 127001 */ // GIR_Coverage, 5281,
45717 /* 127001 */ GIR_EraseRootFromParent_Done,
45718 /* 127002 */ // Label 3858: @127002
45719 /* 127002 */ GIM_Reject,
45720 /* 127003 */ // Label 3852: @127003
45721 /* 127003 */ GIM_Reject,
45722 /* 127004 */ // Label 76: @127004
45723 /* 127004 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3866*/ GIMT_Encode4(127369),
45724 /* 127015 */ /*GILLT_s16*//*Label 3859*/ GIMT_Encode4(127067),
45725 /* 127019 */ /*GILLT_s32*//*Label 3860*/ GIMT_Encode4(127093),
45726 /* 127023 */ /*GILLT_s64*//*Label 3861*/ GIMT_Encode4(127119), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45727 /* 127051 */ /*GILLT_v4s16*//*Label 3862*/ GIMT_Encode4(127145),
45728 /* 127055 */ /*GILLT_v8s16*//*Label 3863*/ GIMT_Encode4(127171),
45729 /* 127059 */ /*GILLT_v2s32*//*Label 3864*/ GIMT_Encode4(127257),
45730 /* 127063 */ /*GILLT_v4s32*//*Label 3865*/ GIMT_Encode4(127283),
45731 /* 127067 */ // Label 3859: @127067
45732 /* 127067 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3867*/ GIMT_Encode4(127092), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 723 //
45733 /* 127074 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
45734 /* 127077 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45735 /* 127081 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45736 /* 127085 */ // (fceil:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTPH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
45737 /* 127085 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPH),
45738 /* 127090 */ GIR_RootConstrainSelectedInstOperands,
45739 /* 127091 */ // GIR_Coverage, 723,
45740 /* 127091 */ GIR_Done,
45741 /* 127092 */ // Label 3867: @127092
45742 /* 127092 */ GIM_Reject,
45743 /* 127093 */ // Label 3860: @127093
45744 /* 127093 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3868*/ GIMT_Encode4(127118), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 725 //
45745 /* 127100 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45746 /* 127103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45747 /* 127107 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45748 /* 127111 */ // (fceil:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTPS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
45749 /* 127111 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPS),
45750 /* 127116 */ GIR_RootConstrainSelectedInstOperands,
45751 /* 127117 */ // GIR_Coverage, 725,
45752 /* 127117 */ GIR_Done,
45753 /* 127118 */ // Label 3868: @127118
45754 /* 127118 */ GIM_Reject,
45755 /* 127119 */ // Label 3861: @127119
45756 /* 127119 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3869*/ GIMT_Encode4(127144), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 727 //
45757 /* 127126 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
45758 /* 127129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45759 /* 127133 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45760 /* 127137 */ // (fceil:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTPD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
45761 /* 127137 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPD),
45762 /* 127142 */ GIR_RootConstrainSelectedInstOperands,
45763 /* 127143 */ // GIR_Coverage, 727,
45764 /* 127143 */ GIR_Done,
45765 /* 127144 */ // Label 3869: @127144
45766 /* 127144 */ GIM_Reject,
45767 /* 127145 */ // Label 3862: @127145
45768 /* 127145 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3870*/ GIMT_Encode4(127170), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1898 //
45769 /* 127152 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45770 /* 127155 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45771 /* 127159 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45772 /* 127163 */ // (fceil:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTPNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
45773 /* 127163 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDh),
45774 /* 127168 */ GIR_RootConstrainSelectedInstOperands,
45775 /* 127169 */ // GIR_Coverage, 1898,
45776 /* 127169 */ GIR_Done,
45777 /* 127170 */ // Label 3870: @127170
45778 /* 127170 */ GIM_Reject,
45779 /* 127171 */ // Label 3863: @127171
45780 /* 127171 */ GIM_Try, /*On fail goto*//*Label 3871*/ GIMT_Encode4(127256),
45781 /* 127176 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45782 /* 127179 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3872*/ GIMT_Encode4(127201), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1900 //
45783 /* 127186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45784 /* 127190 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45785 /* 127194 */ // (fceil:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTPNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
45786 /* 127194 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQh),
45787 /* 127199 */ GIR_RootConstrainSelectedInstOperands,
45788 /* 127200 */ // GIR_Coverage, 1900,
45789 /* 127200 */ GIR_Done,
45790 /* 127201 */ // Label 3872: @127201
45791 /* 127201 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3873*/ GIMT_Encode4(127255), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4388 //
45792 /* 127208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45793 /* 127212 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45794 /* 127216 */ // (fceil:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
45795 /* 127216 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45796 /* 127219 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45797 /* 127223 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45798 /* 127228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P),
45799 /* 127231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45800 /* 127233 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
45801 /* 127235 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45802 /* 127238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45803 /* 127244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45804 /* 127250 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45805 /* 127253 */ GIR_RootConstrainSelectedInstOperands,
45806 /* 127254 */ // GIR_Coverage, 4388,
45807 /* 127254 */ GIR_EraseRootFromParent_Done,
45808 /* 127255 */ // Label 3873: @127255
45809 /* 127255 */ GIM_Reject,
45810 /* 127256 */ // Label 3871: @127256
45811 /* 127256 */ GIM_Reject,
45812 /* 127257 */ // Label 3864: @127257
45813 /* 127257 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3874*/ GIMT_Encode4(127282), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1894 //
45814 /* 127264 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45815 /* 127267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45816 /* 127271 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45817 /* 127275 */ // (fceil:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTPNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
45818 /* 127275 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDf),
45819 /* 127280 */ GIR_RootConstrainSelectedInstOperands,
45820 /* 127281 */ // GIR_Coverage, 1894,
45821 /* 127281 */ GIR_Done,
45822 /* 127282 */ // Label 3874: @127282
45823 /* 127282 */ GIM_Reject,
45824 /* 127283 */ // Label 3865: @127283
45825 /* 127283 */ GIM_Try, /*On fail goto*//*Label 3875*/ GIMT_Encode4(127368),
45826 /* 127288 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45827 /* 127291 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3876*/ GIMT_Encode4(127313), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1896 //
45828 /* 127298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45829 /* 127302 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45830 /* 127306 */ // (fceil:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTPNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
45831 /* 127306 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQf),
45832 /* 127311 */ GIR_RootConstrainSelectedInstOperands,
45833 /* 127312 */ // GIR_Coverage, 1896,
45834 /* 127312 */ GIR_Done,
45835 /* 127313 */ // Label 3876: @127313
45836 /* 127313 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3877*/ GIMT_Encode4(127367), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4412 //
45837 /* 127320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45838 /* 127324 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45839 /* 127328 */ // (fceil:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
45840 /* 127328 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45841 /* 127331 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45842 /* 127335 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45843 /* 127340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P),
45844 /* 127343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45845 /* 127345 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
45846 /* 127347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45847 /* 127350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45848 /* 127356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45849 /* 127362 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45850 /* 127365 */ GIR_RootConstrainSelectedInstOperands,
45851 /* 127366 */ // GIR_Coverage, 4412,
45852 /* 127366 */ GIR_EraseRootFromParent_Done,
45853 /* 127367 */ // Label 3877: @127367
45854 /* 127367 */ GIM_Reject,
45855 /* 127368 */ // Label 3875: @127368
45856 /* 127368 */ GIM_Reject,
45857 /* 127369 */ // Label 3866: @127369
45858 /* 127369 */ GIM_Reject,
45859 /* 127370 */ // Label 77: @127370
45860 /* 127370 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3881*/ GIMT_Encode4(127504),
45861 /* 127381 */ /*GILLT_s16*//*Label 3878*/ GIMT_Encode4(127393),
45862 /* 127385 */ /*GILLT_s32*//*Label 3879*/ GIMT_Encode4(127430),
45863 /* 127389 */ /*GILLT_s64*//*Label 3880*/ GIMT_Encode4(127467),
45864 /* 127393 */ // Label 3878: @127393
45865 /* 127393 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3882*/ GIMT_Encode4(127429), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 739 //
45866 /* 127400 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
45867 /* 127403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45868 /* 127407 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45869 /* 127411 */ // (fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
45870 /* 127411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH),
45871 /* 127414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
45872 /* 127416 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
45873 /* 127418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45874 /* 127421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45875 /* 127427 */ GIR_RootConstrainSelectedInstOperands,
45876 /* 127428 */ // GIR_Coverage, 739,
45877 /* 127428 */ GIR_EraseRootFromParent_Done,
45878 /* 127429 */ // Label 3882: @127429
45879 /* 127429 */ GIM_Reject,
45880 /* 127430 */ // Label 3879: @127430
45881 /* 127430 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3883*/ GIMT_Encode4(127466), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 737 //
45882 /* 127437 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45883 /* 127440 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45884 /* 127444 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45885 /* 127448 */ // (fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
45886 /* 127448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS),
45887 /* 127451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
45888 /* 127453 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
45889 /* 127455 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45890 /* 127458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45891 /* 127464 */ GIR_RootConstrainSelectedInstOperands,
45892 /* 127465 */ // GIR_Coverage, 737,
45893 /* 127465 */ GIR_EraseRootFromParent_Done,
45894 /* 127466 */ // Label 3883: @127466
45895 /* 127466 */ GIM_Reject,
45896 /* 127467 */ // Label 3880: @127467
45897 /* 127467 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3884*/ GIMT_Encode4(127503), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 735 //
45898 /* 127474 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
45899 /* 127477 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45900 /* 127481 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45901 /* 127485 */ // (fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
45902 /* 127485 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD),
45903 /* 127488 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
45904 /* 127490 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
45905 /* 127492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45906 /* 127495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45907 /* 127501 */ GIR_RootConstrainSelectedInstOperands,
45908 /* 127502 */ // GIR_Coverage, 735,
45909 /* 127502 */ GIR_EraseRootFromParent_Done,
45910 /* 127503 */ // Label 3884: @127503
45911 /* 127503 */ GIM_Reject,
45912 /* 127504 */ // Label 3881: @127504
45913 /* 127504 */ GIM_Reject,
45914 /* 127505 */ // Label 78: @127505
45915 /* 127505 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3892*/ GIMT_Encode4(127870),
45916 /* 127516 */ /*GILLT_s16*//*Label 3885*/ GIMT_Encode4(127568),
45917 /* 127520 */ /*GILLT_s32*//*Label 3886*/ GIMT_Encode4(127594),
45918 /* 127524 */ /*GILLT_s64*//*Label 3887*/ GIMT_Encode4(127620), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45919 /* 127552 */ /*GILLT_v4s16*//*Label 3888*/ GIMT_Encode4(127646),
45920 /* 127556 */ /*GILLT_v8s16*//*Label 3889*/ GIMT_Encode4(127672),
45921 /* 127560 */ /*GILLT_v2s32*//*Label 3890*/ GIMT_Encode4(127758),
45922 /* 127564 */ /*GILLT_v4s32*//*Label 3891*/ GIMT_Encode4(127784),
45923 /* 127568 */ // Label 3885: @127568
45924 /* 127568 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3893*/ GIMT_Encode4(127593), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 729 //
45925 /* 127575 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
45926 /* 127578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45927 /* 127582 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45928 /* 127586 */ // (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTMH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
45929 /* 127586 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMH),
45930 /* 127591 */ GIR_RootConstrainSelectedInstOperands,
45931 /* 127592 */ // GIR_Coverage, 729,
45932 /* 127592 */ GIR_Done,
45933 /* 127593 */ // Label 3893: @127593
45934 /* 127593 */ GIM_Reject,
45935 /* 127594 */ // Label 3886: @127594
45936 /* 127594 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3894*/ GIMT_Encode4(127619), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 731 //
45937 /* 127601 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45938 /* 127604 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45939 /* 127608 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45940 /* 127612 */ // (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTMS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
45941 /* 127612 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMS),
45942 /* 127617 */ GIR_RootConstrainSelectedInstOperands,
45943 /* 127618 */ // GIR_Coverage, 731,
45944 /* 127618 */ GIR_Done,
45945 /* 127619 */ // Label 3894: @127619
45946 /* 127619 */ GIM_Reject,
45947 /* 127620 */ // Label 3887: @127620
45948 /* 127620 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3895*/ GIMT_Encode4(127645), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 733 //
45949 /* 127627 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
45950 /* 127630 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45951 /* 127634 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45952 /* 127638 */ // (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTMD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
45953 /* 127638 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMD),
45954 /* 127643 */ GIR_RootConstrainSelectedInstOperands,
45955 /* 127644 */ // GIR_Coverage, 733,
45956 /* 127644 */ GIR_Done,
45957 /* 127645 */ // Label 3895: @127645
45958 /* 127645 */ GIM_Reject,
45959 /* 127646 */ // Label 3888: @127646
45960 /* 127646 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3896*/ GIMT_Encode4(127671), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1890 //
45961 /* 127653 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45962 /* 127656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45963 /* 127660 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45964 /* 127664 */ // (ffloor:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
45965 /* 127664 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDh),
45966 /* 127669 */ GIR_RootConstrainSelectedInstOperands,
45967 /* 127670 */ // GIR_Coverage, 1890,
45968 /* 127670 */ GIR_Done,
45969 /* 127671 */ // Label 3896: @127671
45970 /* 127671 */ GIM_Reject,
45971 /* 127672 */ // Label 3889: @127672
45972 /* 127672 */ GIM_Try, /*On fail goto*//*Label 3897*/ GIMT_Encode4(127757),
45973 /* 127677 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45974 /* 127680 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3898*/ GIMT_Encode4(127702), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1892 //
45975 /* 127687 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45976 /* 127691 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45977 /* 127695 */ // (ffloor:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
45978 /* 127695 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQh),
45979 /* 127700 */ GIR_RootConstrainSelectedInstOperands,
45980 /* 127701 */ // GIR_Coverage, 1892,
45981 /* 127701 */ GIR_Done,
45982 /* 127702 */ // Label 3898: @127702
45983 /* 127702 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3899*/ GIMT_Encode4(127756), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4384 //
45984 /* 127709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45985 /* 127713 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45986 /* 127717 */ // (ffloor:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
45987 /* 127717 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45988 /* 127720 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45989 /* 127724 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45990 /* 127729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M),
45991 /* 127732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45992 /* 127734 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
45993 /* 127736 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45994 /* 127739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45995 /* 127745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45996 /* 127751 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45997 /* 127754 */ GIR_RootConstrainSelectedInstOperands,
45998 /* 127755 */ // GIR_Coverage, 4384,
45999 /* 127755 */ GIR_EraseRootFromParent_Done,
46000 /* 127756 */ // Label 3899: @127756
46001 /* 127756 */ GIM_Reject,
46002 /* 127757 */ // Label 3897: @127757
46003 /* 127757 */ GIM_Reject,
46004 /* 127758 */ // Label 3890: @127758
46005 /* 127758 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3900*/ GIMT_Encode4(127783), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1886 //
46006 /* 127765 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
46007 /* 127768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46008 /* 127772 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46009 /* 127776 */ // (ffloor:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
46010 /* 127776 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDf),
46011 /* 127781 */ GIR_RootConstrainSelectedInstOperands,
46012 /* 127782 */ // GIR_Coverage, 1886,
46013 /* 127782 */ GIR_Done,
46014 /* 127783 */ // Label 3900: @127783
46015 /* 127783 */ GIM_Reject,
46016 /* 127784 */ // Label 3891: @127784
46017 /* 127784 */ GIM_Try, /*On fail goto*//*Label 3901*/ GIMT_Encode4(127869),
46018 /* 127789 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
46019 /* 127792 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3902*/ GIMT_Encode4(127814), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1888 //
46020 /* 127799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46021 /* 127803 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46022 /* 127807 */ // (ffloor:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
46023 /* 127807 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQf),
46024 /* 127812 */ GIR_RootConstrainSelectedInstOperands,
46025 /* 127813 */ // GIR_Coverage, 1888,
46026 /* 127813 */ GIR_Done,
46027 /* 127814 */ // Label 3902: @127814
46028 /* 127814 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3903*/ GIMT_Encode4(127868), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4408 //
46029 /* 127821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46030 /* 127825 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46031 /* 127829 */ // (ffloor:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
46032 /* 127829 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46033 /* 127832 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46034 /* 127836 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46035 /* 127841 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M),
46036 /* 127844 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46037 /* 127846 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
46038 /* 127848 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46039 /* 127851 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46040 /* 127857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46041 /* 127863 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46042 /* 127866 */ GIR_RootConstrainSelectedInstOperands,
46043 /* 127867 */ // GIR_Coverage, 4408,
46044 /* 127867 */ GIR_EraseRootFromParent_Done,
46045 /* 127868 */ // Label 3903: @127868
46046 /* 127868 */ GIM_Reject,
46047 /* 127869 */ // Label 3901: @127869
46048 /* 127869 */ GIM_Reject,
46049 /* 127870 */ // Label 3892: @127870
46050 /* 127870 */ GIM_Reject,
46051 /* 127871 */ // Label 79: @127871
46052 /* 127871 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 3911*/ GIMT_Encode4(128269),
46053 /* 127882 */ /*GILLT_s16*//*Label 3904*/ GIMT_Encode4(127934),
46054 /* 127886 */ /*GILLT_s32*//*Label 3905*/ GIMT_Encode4(127971),
46055 /* 127890 */ /*GILLT_s64*//*Label 3906*/ GIMT_Encode4(128008), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
46056 /* 127918 */ /*GILLT_v4s16*//*Label 3907*/ GIMT_Encode4(128045),
46057 /* 127922 */ /*GILLT_v8s16*//*Label 3908*/ GIMT_Encode4(128071),
46058 /* 127926 */ /*GILLT_v2s32*//*Label 3909*/ GIMT_Encode4(128157),
46059 /* 127930 */ /*GILLT_v4s32*//*Label 3910*/ GIMT_Encode4(128183),
46060 /* 127934 */ // Label 3904: @127934
46061 /* 127934 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3912*/ GIMT_Encode4(127970), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 705 //
46062 /* 127941 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46063 /* 127944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46064 /* 127948 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46065 /* 127952 */ // (frint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTXH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
46066 /* 127952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXH),
46067 /* 127955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46068 /* 127957 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46069 /* 127959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46070 /* 127962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46071 /* 127968 */ GIR_RootConstrainSelectedInstOperands,
46072 /* 127969 */ // GIR_Coverage, 705,
46073 /* 127969 */ GIR_EraseRootFromParent_Done,
46074 /* 127970 */ // Label 3912: @127970
46075 /* 127970 */ GIM_Reject,
46076 /* 127971 */ // Label 3905: @127971
46077 /* 127971 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3913*/ GIMT_Encode4(128007), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 707 //
46078 /* 127978 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46079 /* 127981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46080 /* 127985 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46081 /* 127989 */ // (frint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTXS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
46082 /* 127989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXS),
46083 /* 127992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46084 /* 127994 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46085 /* 127996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46086 /* 127999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46087 /* 128005 */ GIR_RootConstrainSelectedInstOperands,
46088 /* 128006 */ // GIR_Coverage, 707,
46089 /* 128006 */ GIR_EraseRootFromParent_Done,
46090 /* 128007 */ // Label 3913: @128007
46091 /* 128007 */ GIM_Reject,
46092 /* 128008 */ // Label 3906: @128008
46093 /* 128008 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3914*/ GIMT_Encode4(128044), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 709 //
46094 /* 128015 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46095 /* 128018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46096 /* 128022 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46097 /* 128026 */ // (frint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTXD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
46098 /* 128026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXD),
46099 /* 128029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46100 /* 128031 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
46101 /* 128033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46102 /* 128036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46103 /* 128042 */ GIR_RootConstrainSelectedInstOperands,
46104 /* 128043 */ // GIR_Coverage, 709,
46105 /* 128043 */ GIR_EraseRootFromParent_Done,
46106 /* 128044 */ // Label 3914: @128044
46107 /* 128044 */ GIM_Reject,
46108 /* 128045 */ // Label 3907: @128045
46109 /* 128045 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3915*/ GIMT_Encode4(128070), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1866 //
46110 /* 128052 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
46111 /* 128055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46112 /* 128059 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46113 /* 128063 */ // (frint:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTXNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
46114 /* 128063 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDh),
46115 /* 128068 */ GIR_RootConstrainSelectedInstOperands,
46116 /* 128069 */ // GIR_Coverage, 1866,
46117 /* 128069 */ GIR_Done,
46118 /* 128070 */ // Label 3915: @128070
46119 /* 128070 */ GIM_Reject,
46120 /* 128071 */ // Label 3908: @128071
46121 /* 128071 */ GIM_Try, /*On fail goto*//*Label 3916*/ GIMT_Encode4(128156),
46122 /* 128076 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
46123 /* 128079 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3917*/ GIMT_Encode4(128101), GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8), // Rule ID 1868 //
46124 /* 128086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46125 /* 128090 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46126 /* 128094 */ // (frint:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTXNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
46127 /* 128094 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQh),
46128 /* 128099 */ GIR_RootConstrainSelectedInstOperands,
46129 /* 128100 */ // GIR_Coverage, 1868,
46130 /* 128100 */ GIR_Done,
46131 /* 128101 */ // Label 3917: @128101
46132 /* 128101 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3918*/ GIMT_Encode4(128155), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4372 //
46133 /* 128108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46134 /* 128112 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46135 /* 128116 */ // (frint:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
46136 /* 128116 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46137 /* 128119 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46138 /* 128123 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46139 /* 128128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X),
46140 /* 128131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46141 /* 128133 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
46142 /* 128135 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46143 /* 128138 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46144 /* 128144 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46145 /* 128150 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46146 /* 128153 */ GIR_RootConstrainSelectedInstOperands,
46147 /* 128154 */ // GIR_Coverage, 4372,
46148 /* 128154 */ GIR_EraseRootFromParent_Done,
46149 /* 128155 */ // Label 3918: @128155
46150 /* 128155 */ GIM_Reject,
46151 /* 128156 */ // Label 3916: @128156
46152 /* 128156 */ GIM_Reject,
46153 /* 128157 */ // Label 3909: @128157
46154 /* 128157 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3919*/ GIMT_Encode4(128182), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1862 //
46155 /* 128164 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
46156 /* 128167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46157 /* 128171 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46158 /* 128175 */ // (frint:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTXNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
46159 /* 128175 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDf),
46160 /* 128180 */ GIR_RootConstrainSelectedInstOperands,
46161 /* 128181 */ // GIR_Coverage, 1862,
46162 /* 128181 */ GIR_Done,
46163 /* 128182 */ // Label 3919: @128182
46164 /* 128182 */ GIM_Reject,
46165 /* 128183 */ // Label 3910: @128183
46166 /* 128183 */ GIM_Try, /*On fail goto*//*Label 3920*/ GIMT_Encode4(128268),
46167 /* 128188 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
46168 /* 128191 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3921*/ GIMT_Encode4(128213), GIMT_Encode2(GIFBS_HasNEON_HasV8), // Rule ID 1864 //
46169 /* 128198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46170 /* 128202 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46171 /* 128206 */ // (frint:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTXNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
46172 /* 128206 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQf),
46173 /* 128211 */ GIR_RootConstrainSelectedInstOperands,
46174 /* 128212 */ // GIR_Coverage, 1864,
46175 /* 128212 */ GIR_Done,
46176 /* 128213 */ // Label 3921: @128213
46177 /* 128213 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3922*/ GIMT_Encode4(128267), GIMT_Encode2(GIFBS_HasMVEFloat), // Rule ID 4396 //
46178 /* 128220 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46179 /* 128224 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46180 /* 128228 */ // (frint:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
46181 /* 128228 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46182 /* 128231 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46183 /* 128235 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46184 /* 128240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X),
46185 /* 128243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46186 /* 128245 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
46187 /* 128247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46188 /* 128250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46189 /* 128256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46190 /* 128262 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46191 /* 128265 */ GIR_RootConstrainSelectedInstOperands,
46192 /* 128266 */ // GIR_Coverage, 4396,
46193 /* 128266 */ GIR_EraseRootFromParent_Done,
46194 /* 128267 */ // Label 3922: @128267
46195 /* 128267 */ GIM_Reject,
46196 /* 128268 */ // Label 3920: @128268
46197 /* 128268 */ GIM_Reject,
46198 /* 128269 */ // Label 3911: @128269
46199 /* 128269 */ GIM_Reject,
46200 /* 128270 */ // Label 80: @128270
46201 /* 128270 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3926*/ GIMT_Encode4(128404),
46202 /* 128281 */ /*GILLT_s16*//*Label 3923*/ GIMT_Encode4(128293),
46203 /* 128285 */ /*GILLT_s32*//*Label 3924*/ GIMT_Encode4(128330),
46204 /* 128289 */ /*GILLT_s64*//*Label 3925*/ GIMT_Encode4(128367),
46205 /* 128293 */ // Label 3923: @128293
46206 /* 128293 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3927*/ GIMT_Encode4(128329), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 699 //
46207 /* 128300 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46208 /* 128303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46209 /* 128307 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46210 /* 128311 */ // (fnearbyint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTRH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
46211 /* 128311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRH),
46212 /* 128314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46213 /* 128316 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46214 /* 128318 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46215 /* 128321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46216 /* 128327 */ GIR_RootConstrainSelectedInstOperands,
46217 /* 128328 */ // GIR_Coverage, 699,
46218 /* 128328 */ GIR_EraseRootFromParent_Done,
46219 /* 128329 */ // Label 3927: @128329
46220 /* 128329 */ GIM_Reject,
46221 /* 128330 */ // Label 3924: @128330
46222 /* 128330 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3928*/ GIMT_Encode4(128366), GIMT_Encode2(GIFBS_HasFPARMv8), // Rule ID 701 //
46223 /* 128337 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46224 /* 128340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46225 /* 128344 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46226 /* 128348 */ // (fnearbyint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
46227 /* 128348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRS),
46228 /* 128351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46229 /* 128353 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46230 /* 128355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46231 /* 128358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46232 /* 128364 */ GIR_RootConstrainSelectedInstOperands,
46233 /* 128365 */ // GIR_Coverage, 701,
46234 /* 128365 */ GIR_EraseRootFromParent_Done,
46235 /* 128366 */ // Label 3928: @128366
46236 /* 128366 */ GIM_Reject,
46237 /* 128367 */ // Label 3925: @128367
46238 /* 128367 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3929*/ GIMT_Encode4(128403), GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8), // Rule ID 703 //
46239 /* 128374 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46240 /* 128377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46241 /* 128381 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46242 /* 128385 */ // (fnearbyint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTRD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
46243 /* 128385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRD),
46244 /* 128388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46245 /* 128390 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
46246 /* 128392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46247 /* 128395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46248 /* 128401 */ GIR_RootConstrainSelectedInstOperands,
46249 /* 128402 */ // GIR_Coverage, 703,
46250 /* 128402 */ GIR_EraseRootFromParent_Done,
46251 /* 128403 */ // Label 3929: @128403
46252 /* 128403 */ GIM_Reject,
46253 /* 128404 */ // Label 3926: @128404
46254 /* 128404 */ GIM_Reject,
46255 /* 128405 */ // Label 81: @128405
46256 /* 128405 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3933*/ GIMT_Encode4(128566),
46257 /* 128416 */ /*GILLT_s16*//*Label 3930*/ GIMT_Encode4(128428),
46258 /* 128420 */ /*GILLT_s32*//*Label 3931*/ GIMT_Encode4(128474),
46259 /* 128424 */ /*GILLT_s64*//*Label 3932*/ GIMT_Encode4(128520),
46260 /* 128428 */ // Label 3930: @128428
46261 /* 128428 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3934*/ GIMT_Encode4(128473), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 620 //
46262 /* 128435 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46263 /* 128438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46264 /* 128441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46265 /* 128445 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46266 /* 128449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46267 /* 128453 */ // (strict_fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46268 /* 128453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH),
46269 /* 128456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46270 /* 128458 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46271 /* 128460 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46272 /* 128462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46273 /* 128465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46274 /* 128471 */ GIR_RootConstrainSelectedInstOperands,
46275 /* 128472 */ // GIR_Coverage, 620,
46276 /* 128472 */ GIR_EraseRootFromParent_Done,
46277 /* 128473 */ // Label 3934: @128473
46278 /* 128473 */ GIM_Reject,
46279 /* 128474 */ // Label 3931: @128474
46280 /* 128474 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3935*/ GIMT_Encode4(128519), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 618 //
46281 /* 128481 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46282 /* 128484 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46283 /* 128487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46284 /* 128491 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46285 /* 128495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46286 /* 128499 */ // (strict_fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46287 /* 128499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS),
46288 /* 128502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46289 /* 128504 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46290 /* 128506 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46291 /* 128508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46292 /* 128511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46293 /* 128517 */ GIR_RootConstrainSelectedInstOperands,
46294 /* 128518 */ // GIR_Coverage, 618,
46295 /* 128518 */ GIR_EraseRootFromParent_Done,
46296 /* 128519 */ // Label 3935: @128519
46297 /* 128519 */ GIM_Reject,
46298 /* 128520 */ // Label 3932: @128520
46299 /* 128520 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3936*/ GIMT_Encode4(128565), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 616 //
46300 /* 128527 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46301 /* 128530 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
46302 /* 128533 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46303 /* 128537 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46304 /* 128541 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46305 /* 128545 */ // (strict_fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46306 /* 128545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD),
46307 /* 128548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46308 /* 128550 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
46309 /* 128552 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
46310 /* 128554 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46311 /* 128557 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46312 /* 128563 */ GIR_RootConstrainSelectedInstOperands,
46313 /* 128564 */ // GIR_Coverage, 616,
46314 /* 128564 */ GIR_EraseRootFromParent_Done,
46315 /* 128565 */ // Label 3936: @128565
46316 /* 128565 */ GIM_Reject,
46317 /* 128566 */ // Label 3933: @128566
46318 /* 128566 */ GIM_Reject,
46319 /* 128567 */ // Label 82: @128567
46320 /* 128567 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3940*/ GIMT_Encode4(128728),
46321 /* 128578 */ /*GILLT_s16*//*Label 3937*/ GIMT_Encode4(128590),
46322 /* 128582 */ /*GILLT_s32*//*Label 3938*/ GIMT_Encode4(128636),
46323 /* 128586 */ /*GILLT_s64*//*Label 3939*/ GIMT_Encode4(128682),
46324 /* 128590 */ // Label 3937: @128590
46325 /* 128590 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3941*/ GIMT_Encode4(128635), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 626 //
46326 /* 128597 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46327 /* 128600 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46328 /* 128603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46329 /* 128607 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46330 /* 128611 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46331 /* 128615 */ // (strict_fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46332 /* 128615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH),
46333 /* 128618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46334 /* 128620 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46335 /* 128622 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46336 /* 128624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46337 /* 128627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46338 /* 128633 */ GIR_RootConstrainSelectedInstOperands,
46339 /* 128634 */ // GIR_Coverage, 626,
46340 /* 128634 */ GIR_EraseRootFromParent_Done,
46341 /* 128635 */ // Label 3941: @128635
46342 /* 128635 */ GIM_Reject,
46343 /* 128636 */ // Label 3938: @128636
46344 /* 128636 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3942*/ GIMT_Encode4(128681), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 624 //
46345 /* 128643 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46346 /* 128646 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46347 /* 128649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46348 /* 128653 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46349 /* 128657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46350 /* 128661 */ // (strict_fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46351 /* 128661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS),
46352 /* 128664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46353 /* 128666 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46354 /* 128668 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46355 /* 128670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46356 /* 128673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46357 /* 128679 */ GIR_RootConstrainSelectedInstOperands,
46358 /* 128680 */ // GIR_Coverage, 624,
46359 /* 128680 */ GIR_EraseRootFromParent_Done,
46360 /* 128681 */ // Label 3942: @128681
46361 /* 128681 */ GIM_Reject,
46362 /* 128682 */ // Label 3939: @128682
46363 /* 128682 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3943*/ GIMT_Encode4(128727), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 622 //
46364 /* 128689 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46365 /* 128692 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
46366 /* 128695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46367 /* 128699 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46368 /* 128703 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46369 /* 128707 */ // (strict_fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46370 /* 128707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD),
46371 /* 128710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46372 /* 128712 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
46373 /* 128714 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
46374 /* 128716 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46375 /* 128719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46376 /* 128725 */ GIR_RootConstrainSelectedInstOperands,
46377 /* 128726 */ // GIR_Coverage, 622,
46378 /* 128726 */ GIR_EraseRootFromParent_Done,
46379 /* 128727 */ // Label 3943: @128727
46380 /* 128727 */ GIM_Reject,
46381 /* 128728 */ // Label 3940: @128728
46382 /* 128728 */ GIM_Reject,
46383 /* 128729 */ // Label 83: @128729
46384 /* 128729 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3947*/ GIMT_Encode4(128890),
46385 /* 128740 */ /*GILLT_s16*//*Label 3944*/ GIMT_Encode4(128752),
46386 /* 128744 */ /*GILLT_s32*//*Label 3945*/ GIMT_Encode4(128798),
46387 /* 128748 */ /*GILLT_s64*//*Label 3946*/ GIMT_Encode4(128844),
46388 /* 128752 */ // Label 3944: @128752
46389 /* 128752 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3948*/ GIMT_Encode4(128797), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 638 //
46390 /* 128759 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46391 /* 128762 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46392 /* 128765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46393 /* 128769 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46394 /* 128773 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46395 /* 128777 */ // (strict_fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46396 /* 128777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH),
46397 /* 128780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46398 /* 128782 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46399 /* 128784 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46400 /* 128786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46401 /* 128789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46402 /* 128795 */ GIR_RootConstrainSelectedInstOperands,
46403 /* 128796 */ // GIR_Coverage, 638,
46404 /* 128796 */ GIR_EraseRootFromParent_Done,
46405 /* 128797 */ // Label 3948: @128797
46406 /* 128797 */ GIM_Reject,
46407 /* 128798 */ // Label 3945: @128798
46408 /* 128798 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3949*/ GIMT_Encode4(128843), GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2), // Rule ID 636 //
46409 /* 128805 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46410 /* 128808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46411 /* 128811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46412 /* 128815 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46413 /* 128819 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46414 /* 128823 */ // (strict_fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46415 /* 128823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS),
46416 /* 128826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46417 /* 128828 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46418 /* 128830 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46419 /* 128832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46420 /* 128835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46421 /* 128841 */ GIR_RootConstrainSelectedInstOperands,
46422 /* 128842 */ // GIR_Coverage, 636,
46423 /* 128842 */ GIR_EraseRootFromParent_Done,
46424 /* 128843 */ // Label 3949: @128843
46425 /* 128843 */ GIM_Reject,
46426 /* 128844 */ // Label 3946: @128844
46427 /* 128844 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3950*/ GIMT_Encode4(128889), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 634 //
46428 /* 128851 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46429 /* 128854 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
46430 /* 128857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46431 /* 128861 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46432 /* 128865 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46433 /* 128869 */ // (strict_fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46434 /* 128869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD),
46435 /* 128872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46436 /* 128874 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
46437 /* 128876 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
46438 /* 128878 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46439 /* 128881 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46440 /* 128887 */ GIR_RootConstrainSelectedInstOperands,
46441 /* 128888 */ // GIR_Coverage, 634,
46442 /* 128888 */ GIR_EraseRootFromParent_Done,
46443 /* 128889 */ // Label 3950: @128889
46444 /* 128889 */ GIM_Reject,
46445 /* 128890 */ // Label 3947: @128890
46446 /* 128890 */ GIM_Reject,
46447 /* 128891 */ // Label 84: @128891
46448 /* 128891 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3954*/ GIMT_Encode4(129052),
46449 /* 128902 */ /*GILLT_s16*//*Label 3951*/ GIMT_Encode4(128914),
46450 /* 128906 */ /*GILLT_s32*//*Label 3952*/ GIMT_Encode4(128960),
46451 /* 128910 */ /*GILLT_s64*//*Label 3953*/ GIMT_Encode4(129006),
46452 /* 128914 */ // Label 3951: @128914
46453 /* 128914 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3955*/ GIMT_Encode4(128959), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 632 //
46454 /* 128921 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46455 /* 128924 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46456 /* 128927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46457 /* 128931 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46458 /* 128935 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46459 /* 128939 */ // (strict_fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46460 /* 128939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH),
46461 /* 128942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46462 /* 128944 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46463 /* 128946 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46464 /* 128948 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46465 /* 128951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46466 /* 128957 */ GIR_RootConstrainSelectedInstOperands,
46467 /* 128958 */ // GIR_Coverage, 632,
46468 /* 128958 */ GIR_EraseRootFromParent_Done,
46469 /* 128959 */ // Label 3955: @128959
46470 /* 128959 */ GIM_Reject,
46471 /* 128960 */ // Label 3952: @128960
46472 /* 128960 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3956*/ GIMT_Encode4(129005), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 630 //
46473 /* 128967 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46474 /* 128970 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46475 /* 128973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46476 /* 128977 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46477 /* 128981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46478 /* 128985 */ // (strict_fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46479 /* 128985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS),
46480 /* 128988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46481 /* 128990 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46482 /* 128992 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46483 /* 128994 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46484 /* 128997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46485 /* 129003 */ GIR_RootConstrainSelectedInstOperands,
46486 /* 129004 */ // GIR_Coverage, 630,
46487 /* 129004 */ GIR_EraseRootFromParent_Done,
46488 /* 129005 */ // Label 3956: @129005
46489 /* 129005 */ GIM_Reject,
46490 /* 129006 */ // Label 3953: @129006
46491 /* 129006 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3957*/ GIMT_Encode4(129051), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 628 //
46492 /* 129013 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46493 /* 129016 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
46494 /* 129019 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46495 /* 129023 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46496 /* 129027 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46497 /* 129031 */ // (strict_fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46498 /* 129031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD),
46499 /* 129034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46500 /* 129036 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
46501 /* 129038 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
46502 /* 129040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46503 /* 129043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46504 /* 129049 */ GIR_RootConstrainSelectedInstOperands,
46505 /* 129050 */ // GIR_Coverage, 628,
46506 /* 129050 */ GIR_EraseRootFromParent_Done,
46507 /* 129051 */ // Label 3957: @129051
46508 /* 129051 */ GIM_Reject,
46509 /* 129052 */ // Label 3954: @129052
46510 /* 129052 */ GIM_Reject,
46511 /* 129053 */ // Label 85: @129053
46512 /* 129053 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3961*/ GIMT_Encode4(130219),
46513 /* 129064 */ /*GILLT_s16*//*Label 3958*/ GIMT_Encode4(129076),
46514 /* 129068 */ /*GILLT_s32*//*Label 3959*/ GIMT_Encode4(129457),
46515 /* 129072 */ /*GILLT_s64*//*Label 3960*/ GIMT_Encode4(129838),
46516 /* 129076 */ // Label 3958: @129076
46517 /* 129076 */ GIM_Try, /*On fail goto*//*Label 3962*/ GIMT_Encode4(129456),
46518 /* 129081 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46519 /* 129084 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46520 /* 129087 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
46521 /* 129090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46522 /* 129094 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3963*/ GIMT_Encode4(129167), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2774 //
46523 /* 129101 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46524 /* 129105 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46525 /* 129109 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
46526 /* 129113 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46527 /* 129118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46528 /* 129122 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
46529 /* 129126 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
46530 /* 129130 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
46531 /* 129134 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46532 /* 129139 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46533 /* 129141 */ // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46534 /* 129141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
46535 /* 129144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46536 /* 129146 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
46537 /* 129150 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46538 /* 129154 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46539 /* 129156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46540 /* 129159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46541 /* 129165 */ GIR_RootConstrainSelectedInstOperands,
46542 /* 129166 */ // GIR_Coverage, 2774,
46543 /* 129166 */ GIR_EraseRootFromParent_Done,
46544 /* 129167 */ // Label 3963: @129167
46545 /* 129167 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3964*/ GIMT_Encode4(129240), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6339 //
46546 /* 129174 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46547 /* 129178 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46548 /* 129182 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46549 /* 129186 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
46550 /* 129190 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46551 /* 129195 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
46552 /* 129199 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
46553 /* 129203 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
46554 /* 129207 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46555 /* 129212 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46556 /* 129214 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46557 /* 129214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
46558 /* 129217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46559 /* 129219 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
46560 /* 129223 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46561 /* 129227 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46562 /* 129229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46563 /* 129232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46564 /* 129238 */ GIR_RootConstrainSelectedInstOperands,
46565 /* 129239 */ // GIR_Coverage, 6339,
46566 /* 129239 */ GIR_EraseRootFromParent_Done,
46567 /* 129240 */ // Label 3964: @129240
46568 /* 129240 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3965*/ GIMT_Encode4(129298), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2754 //
46569 /* 129247 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46570 /* 129251 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46571 /* 129255 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
46572 /* 129259 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46573 /* 129264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46574 /* 129268 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46575 /* 129272 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46576 /* 129274 */ // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46577 /* 129274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
46578 /* 129277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46579 /* 129279 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
46580 /* 129281 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46581 /* 129285 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46582 /* 129287 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46583 /* 129290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46584 /* 129296 */ GIR_RootConstrainSelectedInstOperands,
46585 /* 129297 */ // GIR_Coverage, 2754,
46586 /* 129297 */ GIR_EraseRootFromParent_Done,
46587 /* 129298 */ // Label 3965: @129298
46588 /* 129298 */ GIM_Try, /*On fail goto*//*Label 3966*/ GIMT_Encode4(129455),
46589 /* 129303 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46590 /* 129307 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3967*/ GIMT_Encode4(129361), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 6333 //
46591 /* 129314 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46592 /* 129318 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46593 /* 129322 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
46594 /* 129326 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46595 /* 129331 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46596 /* 129335 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46597 /* 129337 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46598 /* 129337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
46599 /* 129340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46600 /* 129342 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
46601 /* 129344 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46602 /* 129348 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46603 /* 129350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46604 /* 129353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46605 /* 129359 */ GIR_RootConstrainSelectedInstOperands,
46606 /* 129360 */ // GIR_Coverage, 6333,
46607 /* 129360 */ GIR_EraseRootFromParent_Done,
46608 /* 129361 */ // Label 3967: @129361
46609 /* 129361 */ GIM_Try, /*On fail goto*//*Label 3968*/ GIMT_Encode4(129454),
46610 /* 129366 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46611 /* 129370 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3969*/ GIMT_Encode4(129420), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2788 //
46612 /* 129377 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
46613 /* 129381 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46614 /* 129385 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
46615 /* 129389 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46616 /* 129394 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46617 /* 129396 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46618 /* 129396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
46619 /* 129399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46620 /* 129401 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
46621 /* 129405 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46622 /* 129407 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46623 /* 129409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46624 /* 129412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46625 /* 129418 */ GIR_RootConstrainSelectedInstOperands,
46626 /* 129419 */ // GIR_Coverage, 2788,
46627 /* 129419 */ GIR_EraseRootFromParent_Done,
46628 /* 129420 */ // Label 3969: @129420
46629 /* 129420 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3970*/ GIMT_Encode4(129453), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 2736 //
46630 /* 129427 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46631 /* 129431 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46632 /* 129431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH),
46633 /* 129434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46634 /* 129436 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
46635 /* 129438 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46636 /* 129440 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46637 /* 129442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46638 /* 129445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46639 /* 129451 */ GIR_RootConstrainSelectedInstOperands,
46640 /* 129452 */ // GIR_Coverage, 2736,
46641 /* 129452 */ GIR_EraseRootFromParent_Done,
46642 /* 129453 */ // Label 3970: @129453
46643 /* 129453 */ GIM_Reject,
46644 /* 129454 */ // Label 3968: @129454
46645 /* 129454 */ GIM_Reject,
46646 /* 129455 */ // Label 3966: @129455
46647 /* 129455 */ GIM_Reject,
46648 /* 129456 */ // Label 3962: @129456
46649 /* 129456 */ GIM_Reject,
46650 /* 129457 */ // Label 3959: @129457
46651 /* 129457 */ GIM_Try, /*On fail goto*//*Label 3971*/ GIMT_Encode4(129837),
46652 /* 129462 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46653 /* 129465 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46654 /* 129468 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
46655 /* 129471 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46656 /* 129475 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3972*/ GIMT_Encode4(129548), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2772 //
46657 /* 129482 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46658 /* 129486 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46659 /* 129490 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
46660 /* 129494 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46661 /* 129499 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46662 /* 129503 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
46663 /* 129507 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
46664 /* 129511 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
46665 /* 129515 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46666 /* 129520 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46667 /* 129522 */ // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46668 /* 129522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
46669 /* 129525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46670 /* 129527 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
46671 /* 129531 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46672 /* 129535 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46673 /* 129537 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46674 /* 129540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46675 /* 129546 */ GIR_RootConstrainSelectedInstOperands,
46676 /* 129547 */ // GIR_Coverage, 2772,
46677 /* 129547 */ GIR_EraseRootFromParent_Done,
46678 /* 129548 */ // Label 3972: @129548
46679 /* 129548 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3973*/ GIMT_Encode4(129621), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6337 //
46680 /* 129555 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46681 /* 129559 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46682 /* 129563 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46683 /* 129567 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
46684 /* 129571 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46685 /* 129576 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
46686 /* 129580 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
46687 /* 129584 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
46688 /* 129588 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46689 /* 129593 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46690 /* 129595 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46691 /* 129595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
46692 /* 129598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46693 /* 129600 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
46694 /* 129604 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46695 /* 129608 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46696 /* 129610 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46697 /* 129613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46698 /* 129619 */ GIR_RootConstrainSelectedInstOperands,
46699 /* 129620 */ // GIR_Coverage, 6337,
46700 /* 129620 */ GIR_EraseRootFromParent_Done,
46701 /* 129621 */ // Label 3973: @129621
46702 /* 129621 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3974*/ GIMT_Encode4(129679), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2752 //
46703 /* 129628 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46704 /* 129632 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46705 /* 129636 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
46706 /* 129640 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46707 /* 129645 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46708 /* 129649 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46709 /* 129653 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46710 /* 129655 */ // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46711 /* 129655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
46712 /* 129658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46713 /* 129660 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
46714 /* 129662 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46715 /* 129666 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46716 /* 129668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46717 /* 129671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46718 /* 129677 */ GIR_RootConstrainSelectedInstOperands,
46719 /* 129678 */ // GIR_Coverage, 2752,
46720 /* 129678 */ GIR_EraseRootFromParent_Done,
46721 /* 129679 */ // Label 3974: @129679
46722 /* 129679 */ GIM_Try, /*On fail goto*//*Label 3975*/ GIMT_Encode4(129836),
46723 /* 129684 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46724 /* 129688 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3976*/ GIMT_Encode4(129742), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 6331 //
46725 /* 129695 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46726 /* 129699 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46727 /* 129703 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
46728 /* 129707 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46729 /* 129712 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46730 /* 129716 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46731 /* 129718 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46732 /* 129718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
46733 /* 129721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46734 /* 129723 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
46735 /* 129725 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
46736 /* 129729 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46737 /* 129731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46738 /* 129734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46739 /* 129740 */ GIR_RootConstrainSelectedInstOperands,
46740 /* 129741 */ // GIR_Coverage, 6331,
46741 /* 129741 */ GIR_EraseRootFromParent_Done,
46742 /* 129742 */ // Label 3976: @129742
46743 /* 129742 */ GIM_Try, /*On fail goto*//*Label 3977*/ GIMT_Encode4(129835),
46744 /* 129747 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46745 /* 129751 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3978*/ GIMT_Encode4(129801), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2786 //
46746 /* 129758 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
46747 /* 129762 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46748 /* 129766 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
46749 /* 129770 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46750 /* 129775 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46751 /* 129777 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46752 /* 129777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
46753 /* 129780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46754 /* 129782 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
46755 /* 129786 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46756 /* 129788 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46757 /* 129790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46758 /* 129793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46759 /* 129799 */ GIR_RootConstrainSelectedInstOperands,
46760 /* 129800 */ // GIR_Coverage, 2786,
46761 /* 129800 */ GIR_EraseRootFromParent_Done,
46762 /* 129801 */ // Label 3978: @129801
46763 /* 129801 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3979*/ GIMT_Encode4(129834), GIMT_Encode2(GIFBS_HasVFP4), // Rule ID 2734 //
46764 /* 129808 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46765 /* 129812 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46766 /* 129812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS),
46767 /* 129815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46768 /* 129817 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
46769 /* 129819 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
46770 /* 129821 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
46771 /* 129823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46772 /* 129826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46773 /* 129832 */ GIR_RootConstrainSelectedInstOperands,
46774 /* 129833 */ // GIR_Coverage, 2734,
46775 /* 129833 */ GIR_EraseRootFromParent_Done,
46776 /* 129834 */ // Label 3979: @129834
46777 /* 129834 */ GIM_Reject,
46778 /* 129835 */ // Label 3977: @129835
46779 /* 129835 */ GIM_Reject,
46780 /* 129836 */ // Label 3975: @129836
46781 /* 129836 */ GIM_Reject,
46782 /* 129837 */ // Label 3971: @129837
46783 /* 129837 */ GIM_Reject,
46784 /* 129838 */ // Label 3960: @129838
46785 /* 129838 */ GIM_Try, /*On fail goto*//*Label 3980*/ GIMT_Encode4(130218),
46786 /* 129843 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46787 /* 129846 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
46788 /* 129849 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
46789 /* 129852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46790 /* 129856 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3981*/ GIMT_Encode4(129929), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2770 //
46791 /* 129863 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46792 /* 129867 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46793 /* 129871 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
46794 /* 129875 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46795 /* 129880 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46796 /* 129884 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
46797 /* 129888 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
46798 /* 129892 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
46799 /* 129896 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46800 /* 129901 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46801 /* 129903 */ // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46802 /* 129903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
46803 /* 129906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46804 /* 129908 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
46805 /* 129912 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
46806 /* 129916 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
46807 /* 129918 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46808 /* 129921 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46809 /* 129927 */ GIR_RootConstrainSelectedInstOperands,
46810 /* 129928 */ // GIR_Coverage, 2770,
46811 /* 129928 */ GIR_EraseRootFromParent_Done,
46812 /* 129929 */ // Label 3981: @129929
46813 /* 129929 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3982*/ GIMT_Encode4(130002), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6335 //
46814 /* 129936 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46815 /* 129940 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46816 /* 129944 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46817 /* 129948 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
46818 /* 129952 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46819 /* 129957 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
46820 /* 129961 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
46821 /* 129965 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
46822 /* 129969 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46823 /* 129974 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46824 /* 129976 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46825 /* 129976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
46826 /* 129979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46827 /* 129981 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
46828 /* 129985 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
46829 /* 129989 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
46830 /* 129991 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46831 /* 129994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46832 /* 130000 */ GIR_RootConstrainSelectedInstOperands,
46833 /* 130001 */ // GIR_Coverage, 6335,
46834 /* 130001 */ GIR_EraseRootFromParent_Done,
46835 /* 130002 */ // Label 3982: @130002
46836 /* 130002 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3983*/ GIMT_Encode4(130060), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2750 //
46837 /* 130009 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46838 /* 130013 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46839 /* 130017 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
46840 /* 130021 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46841 /* 130026 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46842 /* 130030 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46843 /* 130034 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46844 /* 130036 */ // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46845 /* 130036 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
46846 /* 130039 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46847 /* 130041 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
46848 /* 130043 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
46849 /* 130047 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
46850 /* 130049 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46851 /* 130052 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46852 /* 130058 */ GIR_RootConstrainSelectedInstOperands,
46853 /* 130059 */ // GIR_Coverage, 2750,
46854 /* 130059 */ GIR_EraseRootFromParent_Done,
46855 /* 130060 */ // Label 3983: @130060
46856 /* 130060 */ GIM_Try, /*On fail goto*//*Label 3984*/ GIMT_Encode4(130217),
46857 /* 130065 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46858 /* 130069 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3985*/ GIMT_Encode4(130123), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 6329 //
46859 /* 130076 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
46860 /* 130080 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46861 /* 130084 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
46862 /* 130088 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46863 /* 130093 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46864 /* 130097 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46865 /* 130099 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46866 /* 130099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
46867 /* 130102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46868 /* 130104 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
46869 /* 130106 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
46870 /* 130110 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
46871 /* 130112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46872 /* 130115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46873 /* 130121 */ GIR_RootConstrainSelectedInstOperands,
46874 /* 130122 */ // GIR_Coverage, 6329,
46875 /* 130122 */ GIR_EraseRootFromParent_Done,
46876 /* 130123 */ // Label 3985: @130123
46877 /* 130123 */ GIM_Try, /*On fail goto*//*Label 3986*/ GIMT_Encode4(130216),
46878 /* 130128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46879 /* 130132 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3987*/ GIMT_Encode4(130182), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2784 //
46880 /* 130139 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
46881 /* 130143 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
46882 /* 130147 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
46883 /* 130151 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46884 /* 130156 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
46885 /* 130158 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46886 /* 130158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
46887 /* 130161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46888 /* 130163 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin
46889 /* 130167 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
46890 /* 130169 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
46891 /* 130171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46892 /* 130174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46893 /* 130180 */ GIR_RootConstrainSelectedInstOperands,
46894 /* 130181 */ // GIR_Coverage, 2784,
46895 /* 130181 */ GIR_EraseRootFromParent_Done,
46896 /* 130182 */ // Label 3987: @130182
46897 /* 130182 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3988*/ GIMT_Encode4(130215), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4), // Rule ID 2732 //
46898 /* 130189 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46899 /* 130193 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46900 /* 130193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD),
46901 /* 130196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46902 /* 130198 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
46903 /* 130200 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
46904 /* 130202 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
46905 /* 130204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46906 /* 130207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46907 /* 130213 */ GIR_RootConstrainSelectedInstOperands,
46908 /* 130214 */ // GIR_Coverage, 2732,
46909 /* 130214 */ GIR_EraseRootFromParent_Done,
46910 /* 130215 */ // Label 3988: @130215
46911 /* 130215 */ GIM_Reject,
46912 /* 130216 */ // Label 3986: @130216
46913 /* 130216 */ GIM_Reject,
46914 /* 130217 */ // Label 3984: @130217
46915 /* 130217 */ GIM_Reject,
46916 /* 130218 */ // Label 3980: @130218
46917 /* 130218 */ GIM_Reject,
46918 /* 130219 */ // Label 3961: @130219
46919 /* 130219 */ GIM_Reject,
46920 /* 130220 */ // Label 86: @130220
46921 /* 130220 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 3992*/ GIMT_Encode4(130354),
46922 /* 130231 */ /*GILLT_s16*//*Label 3989*/ GIMT_Encode4(130243),
46923 /* 130235 */ /*GILLT_s32*//*Label 3990*/ GIMT_Encode4(130280),
46924 /* 130239 */ /*GILLT_s64*//*Label 3991*/ GIMT_Encode4(130317),
46925 /* 130243 */ // Label 3989: @130243
46926 /* 130243 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3993*/ GIMT_Encode4(130279), GIMT_Encode2(GIFBS_HasFullFP16), // Rule ID 738 //
46927 /* 130250 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46928 /* 130253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46929 /* 130257 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46930 /* 130261 */ // (strict_fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
46931 /* 130261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH),
46932 /* 130264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46933 /* 130266 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46934 /* 130268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46935 /* 130271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46936 /* 130277 */ GIR_RootConstrainSelectedInstOperands,
46937 /* 130278 */ // GIR_Coverage, 738,
46938 /* 130278 */ GIR_EraseRootFromParent_Done,
46939 /* 130279 */ // Label 3993: @130279
46940 /* 130279 */ GIM_Reject,
46941 /* 130280 */ // Label 3990: @130280
46942 /* 130280 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3994*/ GIMT_Encode4(130316), GIMT_Encode2(GIFBS_HasVFP2), // Rule ID 736 //
46943 /* 130287 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46944 /* 130290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46945 /* 130294 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46946 /* 130298 */ // (strict_fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
46947 /* 130298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS),
46948 /* 130301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
46949 /* 130303 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
46950 /* 130305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46951 /* 130308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46952 /* 130314 */ GIR_RootConstrainSelectedInstOperands,
46953 /* 130315 */ // GIR_Coverage, 736,
46954 /* 130315 */ GIR_EraseRootFromParent_Done,
46955 /* 130316 */ // Label 3994: @130316
46956 /* 130316 */ GIM_Reject,
46957 /* 130317 */ // Label 3991: @130317
46958 /* 130317 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3995*/ GIMT_Encode4(130353), GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2), // Rule ID 734 //
46959 /* 130324 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46960 /* 130327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46961 /* 130331 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46962 /* 130335 */ // (strict_fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
46963 /* 130335 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD),
46964 /* 130338 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
46965 /* 130340 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
46966 /* 130342 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46967 /* 130345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46968 /* 130351 */ GIR_RootConstrainSelectedInstOperands,
46969 /* 130352 */ // GIR_Coverage, 734,
46970 /* 130352 */ GIR_EraseRootFromParent_Done,
46971 /* 130353 */ // Label 3995: @130353
46972 /* 130353 */ GIM_Reject,
46973 /* 130354 */ // Label 3992: @130354
46974 /* 130354 */ GIM_Reject,
46975 /* 130355 */ // Label 87: @130355
46976 /* 130355 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3996*/ GIMT_Encode4(130369), GIMT_Encode2(GIFBS_IsARM), // Rule ID 12 //
46977 /* 130362 */ // (trap) => (TRAP)
46978 /* 130362 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::TRAP),
46979 /* 130367 */ GIR_RootConstrainSelectedInstOperands,
46980 /* 130368 */ // GIR_Coverage, 12,
46981 /* 130368 */ GIR_Done,
46982 /* 130369 */ // Label 3996: @130369
46983 /* 130369 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3997*/ GIMT_Encode4(130383), GIMT_Encode2(GIFBS_IsThumb), // Rule ID 284 //
46984 /* 130376 */ // (trap) => (tTRAP)
46985 /* 130376 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tTRAP),
46986 /* 130381 */ GIR_RootConstrainSelectedInstOperands,
46987 /* 130382 */ // GIR_Coverage, 284,
46988 /* 130382 */ GIR_Done,
46989 /* 130383 */ // Label 3997: @130383
46990 /* 130383 */ GIM_Reject,
46991 /* 130384 */ // Label 88: @130384
46992 /* 130384 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3998*/ GIMT_Encode4(130399), GIMT_Encode2(GIFBS_HasV5T_IsARM), // Rule ID 2026 //
46993 /* 130391 */ // (debugtrap) => (BKPT 0:{ *:[i32] })
46994 /* 130391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BKPT),
46995 /* 130394 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46996 /* 130397 */ GIR_RootConstrainSelectedInstOperands,
46997 /* 130398 */ // GIR_Coverage, 2026,
46998 /* 130398 */ GIR_EraseRootFromParent_Done,
46999 /* 130399 */ // Label 3998: @130399
47000 /* 130399 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 3999*/ GIMT_Encode4(130425), GIMT_Encode2(GIFBS_IsARM_NoV5T), // Rule ID 2027 //
47001 /* 130406 */ // (debugtrap) => (UDF 254:{ *:[i32] })
47002 /* 130406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF),
47003 /* 130409 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254),
47004 /* 130419 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
47005 /* 130423 */ GIR_RootConstrainSelectedInstOperands,
47006 /* 130424 */ // GIR_Coverage, 2027,
47007 /* 130424 */ GIR_EraseRootFromParent_Done,
47008 /* 130425 */ // Label 3999: @130425
47009 /* 130425 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4000*/ GIMT_Encode4(130440), GIMT_Encode2(GIFBS_HasV5T_IsThumb), // Rule ID 2219 //
47010 /* 130432 */ // (debugtrap) => (tBKPT 0:{ *:[i32] })
47011 /* 130432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBKPT),
47012 /* 130435 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47013 /* 130438 */ GIR_RootConstrainSelectedInstOperands,
47014 /* 130439 */ // GIR_Coverage, 2219,
47015 /* 130439 */ GIR_EraseRootFromParent_Done,
47016 /* 130440 */ // Label 4000: @130440
47017 /* 130440 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4001*/ GIMT_Encode4(130466), GIMT_Encode2(GIFBS_IsThumb_NoV5T), // Rule ID 2220 //
47018 /* 130447 */ // (debugtrap) => (tUDF 254:{ *:[i32] })
47019 /* 130447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF),
47020 /* 130450 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254),
47021 /* 130460 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
47022 /* 130464 */ GIR_RootConstrainSelectedInstOperands,
47023 /* 130465 */ // GIR_Coverage, 2220,
47024 /* 130465 */ GIR_EraseRootFromParent_Done,
47025 /* 130466 */ // Label 4001: @130466
47026 /* 130466 */ GIM_Reject,
47027 /* 130467 */ // Label 89: @130467
47028 /* 130467 */ GIM_Try, /*On fail goto*//*Label 4002*/ GIMT_Encode4(130840),
47029 /* 130472 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
47030 /* 130475 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4006*/ GIMT_Encode4(130839),
47031 /* 130486 */ /*GILLT_v16s8*//*Label 4003*/ GIMT_Encode4(130506), GIMT_Encode4(0),
47032 /* 130494 */ /*GILLT_v8s16*//*Label 4004*/ GIMT_Encode4(130617), GIMT_Encode4(0),
47033 /* 130502 */ /*GILLT_v4s32*//*Label 4005*/ GIMT_Encode4(130728),
47034 /* 130506 */ // Label 4003: @130506
47035 /* 130506 */ GIM_Try, /*On fail goto*//*Label 4007*/ GIMT_Encode4(130616),
47036 /* 130511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
47037 /* 130515 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4008*/ GIMT_Encode4(130580), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3636 //
47038 /* 130522 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47039 /* 130526 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
47040 /* 130530 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
47041 /* 130534 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
47042 /* 130538 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47043 /* 130543 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47044 /* 130548 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47045 /* 130550 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)) => (MVE_VMLADAVu8:{ *:[i32] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
47046 /* 130550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8),
47047 /* 130553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47048 /* 130555 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
47049 /* 130559 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
47050 /* 130563 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47051 /* 130566 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47052 /* 130572 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47053 /* 130578 */ GIR_RootConstrainSelectedInstOperands,
47054 /* 130579 */ // GIR_Coverage, 3636,
47055 /* 130579 */ GIR_EraseRootFromParent_Done,
47056 /* 130580 */ // Label 4008: @130580
47057 /* 130580 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4009*/ GIMT_Encode4(130615), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3440 //
47058 /* 130587 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47059 /* 130591 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec) => (MVE_VADDVu8no_acc:{ *:[i32] } ?:{ *:[v16i8] }:$vec)
47060 /* 130591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8no_acc),
47061 /* 130594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
47062 /* 130596 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec
47063 /* 130598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47064 /* 130601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47065 /* 130607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47066 /* 130613 */ GIR_RootConstrainSelectedInstOperands,
47067 /* 130614 */ // GIR_Coverage, 3440,
47068 /* 130614 */ GIR_EraseRootFromParent_Done,
47069 /* 130615 */ // Label 4009: @130615
47070 /* 130615 */ GIM_Reject,
47071 /* 130616 */ // Label 4007: @130616
47072 /* 130616 */ GIM_Reject,
47073 /* 130617 */ // Label 4004: @130617
47074 /* 130617 */ GIM_Try, /*On fail goto*//*Label 4010*/ GIMT_Encode4(130727),
47075 /* 130622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
47076 /* 130626 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4011*/ GIMT_Encode4(130691), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3633 //
47077 /* 130633 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47078 /* 130637 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
47079 /* 130641 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47080 /* 130645 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
47081 /* 130649 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47082 /* 130654 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47083 /* 130659 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47084 /* 130661 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)) => (MVE_VMLADAVu16:{ *:[i32] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
47085 /* 130661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16),
47086 /* 130664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47087 /* 130666 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
47088 /* 130670 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
47089 /* 130674 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47090 /* 130677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47091 /* 130683 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47092 /* 130689 */ GIR_RootConstrainSelectedInstOperands,
47093 /* 130690 */ // GIR_Coverage, 3633,
47094 /* 130690 */ GIR_EraseRootFromParent_Done,
47095 /* 130691 */ // Label 4011: @130691
47096 /* 130691 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4012*/ GIMT_Encode4(130726), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3468 //
47097 /* 130698 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47098 /* 130702 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec) => (MVE_VADDVu16no_acc:{ *:[i32] } ?:{ *:[v8i16] }:$vec)
47099 /* 130702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16no_acc),
47100 /* 130705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
47101 /* 130707 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec
47102 /* 130709 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47103 /* 130712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47104 /* 130718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47105 /* 130724 */ GIR_RootConstrainSelectedInstOperands,
47106 /* 130725 */ // GIR_Coverage, 3468,
47107 /* 130725 */ GIR_EraseRootFromParent_Done,
47108 /* 130726 */ // Label 4012: @130726
47109 /* 130726 */ GIM_Reject,
47110 /* 130727 */ // Label 4010: @130727
47111 /* 130727 */ GIM_Reject,
47112 /* 130728 */ // Label 4005: @130728
47113 /* 130728 */ GIM_Try, /*On fail goto*//*Label 4013*/ GIMT_Encode4(130838),
47114 /* 130733 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
47115 /* 130737 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4014*/ GIMT_Encode4(130802), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3632 //
47116 /* 130744 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47117 /* 130748 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
47118 /* 130752 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47119 /* 130756 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
47120 /* 130760 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47121 /* 130765 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47122 /* 130770 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47123 /* 130772 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)) => (MVE_VMLADAVu32:{ *:[i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
47124 /* 130772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32),
47125 /* 130775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47126 /* 130777 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
47127 /* 130781 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
47128 /* 130785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47129 /* 130788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47130 /* 130794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47131 /* 130800 */ GIR_RootConstrainSelectedInstOperands,
47132 /* 130801 */ // GIR_Coverage, 3632,
47133 /* 130801 */ GIR_EraseRootFromParent_Done,
47134 /* 130802 */ // Label 4014: @130802
47135 /* 130802 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4015*/ GIMT_Encode4(130837), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3478 //
47136 /* 130809 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47137 /* 130813 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec) => (MVE_VADDVu32no_acc:{ *:[i32] } ?:{ *:[v4i32] }:$vec)
47138 /* 130813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32no_acc),
47139 /* 130816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
47140 /* 130818 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec
47141 /* 130820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47142 /* 130823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47143 /* 130829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47144 /* 130835 */ GIR_RootConstrainSelectedInstOperands,
47145 /* 130836 */ // GIR_Coverage, 3478,
47146 /* 130836 */ GIR_EraseRootFromParent_Done,
47147 /* 130837 */ // Label 4015: @130837
47148 /* 130837 */ GIM_Reject,
47149 /* 130838 */ // Label 4013: @130838
47150 /* 130838 */ GIM_Reject,
47151 /* 130839 */ // Label 4006: @130839
47152 /* 130839 */ GIM_Reject,
47153 /* 130840 */ // Label 4002: @130840
47154 /* 130840 */ GIM_Reject,
47155 /* 130841 */ // Label 90: @130841
47156 /* 130841 */ GIM_Try, /*On fail goto*//*Label 4016*/ GIMT_Encode4(131105),
47157 /* 130846 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
47158 /* 130849 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4020*/ GIMT_Encode4(131104),
47159 /* 130860 */ /*GILLT_v16s8*//*Label 4017*/ GIMT_Encode4(130880), GIMT_Encode4(0),
47160 /* 130868 */ /*GILLT_v8s16*//*Label 4018*/ GIMT_Encode4(130955), GIMT_Encode4(0),
47161 /* 130876 */ /*GILLT_v4s32*//*Label 4019*/ GIMT_Encode4(131022),
47162 /* 130880 */ // Label 4017: @130880
47163 /* 130880 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4021*/ GIMT_Encode4(130954), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3536 //
47164 /* 130887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47165 /* 130891 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47166 /* 130895 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVs8:{ *:[i32] } (t2MVNi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
47167 /* 130895 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47168 /* 130898 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
47169 /* 130902 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47170 /* 130907 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127,
47171 /* 130910 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47172 /* 130913 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47173 /* 130919 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47174 /* 130925 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47175 /* 130927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8),
47176 /* 130930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47177 /* 130932 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47178 /* 130935 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47179 /* 130937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47180 /* 130940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47181 /* 130946 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47182 /* 130952 */ GIR_RootConstrainSelectedInstOperands,
47183 /* 130953 */ // GIR_Coverage, 3536,
47184 /* 130953 */ GIR_EraseRootFromParent_Done,
47185 /* 130954 */ // Label 4021: @130954
47186 /* 130954 */ GIM_Reject,
47187 /* 130955 */ // Label 4018: @130955
47188 /* 130955 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4022*/ GIMT_Encode4(131021), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3537 //
47189 /* 130962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47190 /* 130966 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47191 /* 130970 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVs16:{ *:[i32] } (t2MOVi32imm:{ *:[i32] } -32768:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
47192 /* 130970 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47193 /* 130973 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm),
47194 /* 130977 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47195 /* 130982 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744073709518848u),
47196 /* 130992 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47197 /* 130994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16),
47198 /* 130997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47199 /* 130999 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47200 /* 131002 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47201 /* 131004 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47202 /* 131007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47203 /* 131013 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47204 /* 131019 */ GIR_RootConstrainSelectedInstOperands,
47205 /* 131020 */ // GIR_Coverage, 3537,
47206 /* 131020 */ GIR_EraseRootFromParent_Done,
47207 /* 131021 */ // Label 4022: @131021
47208 /* 131021 */ GIM_Reject,
47209 /* 131022 */ // Label 4019: @131022
47210 /* 131022 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4023*/ GIMT_Encode4(131103), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3538 //
47211 /* 131029 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47212 /* 131033 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47213 /* 131037 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVs32:{ *:[i32] } (t2MOVi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
47214 /* 131037 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47215 /* 131040 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
47216 /* 131044 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47217 /* 131049 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744071562067968u),
47218 /* 131059 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47219 /* 131062 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47220 /* 131068 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47221 /* 131074 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47222 /* 131076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32),
47223 /* 131079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47224 /* 131081 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47225 /* 131084 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47226 /* 131086 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47227 /* 131089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47228 /* 131095 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47229 /* 131101 */ GIR_RootConstrainSelectedInstOperands,
47230 /* 131102 */ // GIR_Coverage, 3538,
47231 /* 131102 */ GIR_EraseRootFromParent_Done,
47232 /* 131103 */ // Label 4023: @131103
47233 /* 131103 */ GIM_Reject,
47234 /* 131104 */ // Label 4020: @131104
47235 /* 131104 */ GIM_Reject,
47236 /* 131105 */ // Label 4016: @131105
47237 /* 131105 */ GIM_Reject,
47238 /* 131106 */ // Label 91: @131106
47239 /* 131106 */ GIM_Try, /*On fail goto*//*Label 4024*/ GIMT_Encode4(131379),
47240 /* 131111 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
47241 /* 131114 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4028*/ GIMT_Encode4(131378),
47242 /* 131125 */ /*GILLT_v16s8*//*Label 4025*/ GIMT_Encode4(131145), GIMT_Encode4(0),
47243 /* 131133 */ /*GILLT_v8s16*//*Label 4026*/ GIMT_Encode4(131220), GIMT_Encode4(0),
47244 /* 131141 */ /*GILLT_v4s32*//*Label 4027*/ GIMT_Encode4(131296),
47245 /* 131145 */ // Label 4025: @131145
47246 /* 131145 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4029*/ GIMT_Encode4(131219), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3542 //
47247 /* 131152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47248 /* 131156 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47249 /* 131160 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVs8:{ *:[i32] } (t2MOVi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
47250 /* 131160 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47251 /* 131163 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
47252 /* 131167 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47253 /* 131172 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127,
47254 /* 131175 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47255 /* 131178 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47256 /* 131184 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47257 /* 131190 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47258 /* 131192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8),
47259 /* 131195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47260 /* 131197 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47261 /* 131200 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47262 /* 131202 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47263 /* 131205 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47264 /* 131211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47265 /* 131217 */ GIR_RootConstrainSelectedInstOperands,
47266 /* 131218 */ // GIR_Coverage, 3542,
47267 /* 131218 */ GIR_EraseRootFromParent_Done,
47268 /* 131219 */ // Label 4029: @131219
47269 /* 131219 */ GIM_Reject,
47270 /* 131220 */ // Label 4026: @131220
47271 /* 131220 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4030*/ GIMT_Encode4(131295), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3543 //
47272 /* 131227 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47273 /* 131231 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47274 /* 131235 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVs16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 32767:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
47275 /* 131235 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47276 /* 131238 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16),
47277 /* 131242 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47278 /* 131247 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767),
47279 /* 131257 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47280 /* 131260 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47281 /* 131266 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47282 /* 131268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16),
47283 /* 131271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47284 /* 131273 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47285 /* 131276 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47286 /* 131278 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47287 /* 131281 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47288 /* 131287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47289 /* 131293 */ GIR_RootConstrainSelectedInstOperands,
47290 /* 131294 */ // GIR_Coverage, 3543,
47291 /* 131294 */ GIR_EraseRootFromParent_Done,
47292 /* 131295 */ // Label 4030: @131295
47293 /* 131295 */ GIM_Reject,
47294 /* 131296 */ // Label 4027: @131296
47295 /* 131296 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4031*/ GIMT_Encode4(131377), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3544 //
47296 /* 131303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47297 /* 131307 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47298 /* 131311 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVs32:{ *:[i32] } (t2MVNi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
47299 /* 131311 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47300 /* 131314 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
47301 /* 131318 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47302 /* 131323 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744071562067968u),
47303 /* 131333 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47304 /* 131336 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47305 /* 131342 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47306 /* 131348 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47307 /* 131350 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32),
47308 /* 131353 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47309 /* 131355 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47310 /* 131358 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47311 /* 131360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47312 /* 131363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47313 /* 131369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47314 /* 131375 */ GIR_RootConstrainSelectedInstOperands,
47315 /* 131376 */ // GIR_Coverage, 3544,
47316 /* 131376 */ GIR_EraseRootFromParent_Done,
47317 /* 131377 */ // Label 4031: @131377
47318 /* 131377 */ GIM_Reject,
47319 /* 131378 */ // Label 4028: @131378
47320 /* 131378 */ GIM_Reject,
47321 /* 131379 */ // Label 4024: @131379
47322 /* 131379 */ GIM_Reject,
47323 /* 131380 */ // Label 92: @131380
47324 /* 131380 */ GIM_Try, /*On fail goto*//*Label 4032*/ GIMT_Encode4(131645),
47325 /* 131385 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
47326 /* 131388 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4036*/ GIMT_Encode4(131644),
47327 /* 131399 */ /*GILLT_v16s8*//*Label 4033*/ GIMT_Encode4(131419), GIMT_Encode4(0),
47328 /* 131407 */ /*GILLT_v8s16*//*Label 4034*/ GIMT_Encode4(131494), GIMT_Encode4(0),
47329 /* 131415 */ /*GILLT_v4s32*//*Label 4035*/ GIMT_Encode4(131569),
47330 /* 131419 */ // Label 4033: @131419
47331 /* 131419 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4037*/ GIMT_Encode4(131493), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3539 //
47332 /* 131426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47333 /* 131430 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47334 /* 131434 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
47335 /* 131434 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47336 /* 131437 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
47337 /* 131441 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47338 /* 131446 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
47339 /* 131449 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47340 /* 131452 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47341 /* 131458 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47342 /* 131464 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47343 /* 131466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8),
47344 /* 131469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47345 /* 131471 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47346 /* 131474 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47347 /* 131476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47348 /* 131479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47349 /* 131485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47350 /* 131491 */ GIR_RootConstrainSelectedInstOperands,
47351 /* 131492 */ // GIR_Coverage, 3539,
47352 /* 131492 */ GIR_EraseRootFromParent_Done,
47353 /* 131493 */ // Label 4037: @131493
47354 /* 131493 */ GIM_Reject,
47355 /* 131494 */ // Label 4034: @131494
47356 /* 131494 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4038*/ GIMT_Encode4(131568), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3540 //
47357 /* 131501 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47358 /* 131505 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47359 /* 131509 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVu16:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
47360 /* 131509 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47361 /* 131512 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
47362 /* 131516 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47363 /* 131521 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
47364 /* 131524 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47365 /* 131527 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47366 /* 131533 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47367 /* 131539 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47368 /* 131541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16),
47369 /* 131544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47370 /* 131546 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47371 /* 131549 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47372 /* 131551 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47373 /* 131554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47374 /* 131560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47375 /* 131566 */ GIR_RootConstrainSelectedInstOperands,
47376 /* 131567 */ // GIR_Coverage, 3540,
47377 /* 131567 */ GIR_EraseRootFromParent_Done,
47378 /* 131568 */ // Label 4038: @131568
47379 /* 131568 */ GIM_Reject,
47380 /* 131569 */ // Label 4035: @131569
47381 /* 131569 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4039*/ GIMT_Encode4(131643), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3541 //
47382 /* 131576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47383 /* 131580 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47384 /* 131584 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
47385 /* 131584 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47386 /* 131587 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
47387 /* 131591 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47388 /* 131596 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
47389 /* 131599 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47390 /* 131602 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47391 /* 131608 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47392 /* 131614 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47393 /* 131616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32),
47394 /* 131619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47395 /* 131621 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47396 /* 131624 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47397 /* 131626 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47398 /* 131629 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47399 /* 131635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47400 /* 131641 */ GIR_RootConstrainSelectedInstOperands,
47401 /* 131642 */ // GIR_Coverage, 3541,
47402 /* 131642 */ GIR_EraseRootFromParent_Done,
47403 /* 131643 */ // Label 4039: @131643
47404 /* 131643 */ GIM_Reject,
47405 /* 131644 */ // Label 4036: @131644
47406 /* 131644 */ GIM_Reject,
47407 /* 131645 */ // Label 4032: @131645
47408 /* 131645 */ GIM_Reject,
47409 /* 131646 */ // Label 93: @131646
47410 /* 131646 */ GIM_Try, /*On fail goto*//*Label 4040*/ GIMT_Encode4(131926),
47411 /* 131651 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
47412 /* 131654 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4044*/ GIMT_Encode4(131925),
47413 /* 131665 */ /*GILLT_v16s8*//*Label 4041*/ GIMT_Encode4(131685), GIMT_Encode4(0),
47414 /* 131673 */ /*GILLT_v8s16*//*Label 4042*/ GIMT_Encode4(131767), GIMT_Encode4(0),
47415 /* 131681 */ /*GILLT_v4s32*//*Label 4043*/ GIMT_Encode4(131843),
47416 /* 131685 */ // Label 4041: @131685
47417 /* 131685 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4045*/ GIMT_Encode4(131766), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3545 //
47418 /* 131692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47419 /* 131696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47420 /* 131700 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 255:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
47421 /* 131700 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47422 /* 131703 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
47423 /* 131707 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47424 /* 131712 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(255),
47425 /* 131722 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47426 /* 131725 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47427 /* 131731 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47428 /* 131737 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47429 /* 131739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8),
47430 /* 131742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47431 /* 131744 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47432 /* 131747 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47433 /* 131749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47434 /* 131752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47435 /* 131758 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47436 /* 131764 */ GIR_RootConstrainSelectedInstOperands,
47437 /* 131765 */ // GIR_Coverage, 3545,
47438 /* 131765 */ GIR_EraseRootFromParent_Done,
47439 /* 131766 */ // Label 4045: @131766
47440 /* 131766 */ GIM_Reject,
47441 /* 131767 */ // Label 4042: @131767
47442 /* 131767 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4046*/ GIMT_Encode4(131842), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3546 //
47443 /* 131774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47444 /* 131778 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47445 /* 131782 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVu16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 65535:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
47446 /* 131782 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47447 /* 131785 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16),
47448 /* 131789 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47449 /* 131794 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
47450 /* 131804 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47451 /* 131807 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47452 /* 131813 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47453 /* 131815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16),
47454 /* 131818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47455 /* 131820 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47456 /* 131823 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47457 /* 131825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47458 /* 131828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47459 /* 131834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47460 /* 131840 */ GIR_RootConstrainSelectedInstOperands,
47461 /* 131841 */ // GIR_Coverage, 3546,
47462 /* 131841 */ GIR_EraseRootFromParent_Done,
47463 /* 131842 */ // Label 4046: @131842
47464 /* 131842 */ GIM_Reject,
47465 /* 131843 */ // Label 4043: @131843
47466 /* 131843 */ GIM_Try_CheckFeatures, /*On fail goto*//*Label 4047*/ GIMT_Encode4(131924), GIMT_Encode2(GIFBS_HasMVEInt), // Rule ID 3547 //
47467 /* 131850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
47468 /* 131854 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47469 /* 131858 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 4294967295:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
47470 /* 131858 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
47471 /* 131861 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
47472 /* 131865 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47473 /* 131870 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(4294967295),
47474 /* 131880 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
47475 /* 131883 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47476 /* 131889 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47477 /* 131895 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
47478 /* 131897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32),
47479 /* 131900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
47480 /* 131902 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47481 /* 131905 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
47482 /* 131907 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47483 /* 131910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47484 /* 131916 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47485 /* 131922 */ GIR_RootConstrainSelectedInstOperands,
47486 /* 131923 */ // GIR_Coverage, 3547,
47487 /* 131923 */ GIR_EraseRootFromParent_Done,
47488 /* 131924 */ // Label 4047: @131924
47489 /* 131924 */ GIM_Reject,
47490 /* 131925 */ // Label 4044: @131925
47491 /* 131925 */ GIM_Reject,
47492 /* 131926 */ // Label 4040: @131926
47493 /* 131926 */ GIM_Reject,
47494 /* 131927 */ // Label 94: @131927
47495 /* 131927 */ GIM_Reject,
47496 /* 131928 */ }; // Size: 131928 bytes
47497 return MatchTable0;
47498}
47499#undef GIMT_Encode2
47500#undef GIMT_Encode4
47501#undef GIMT_Encode8
47502
47503
47504#endif // GET_GLOBALISEL_IMPL
47505
47506#ifdef GET_GLOBALISEL_PREDICATES_DECL
47507
47508PredicateBitset AvailableModuleFeatures;
47509mutable PredicateBitset AvailableFunctionFeatures;
47510PredicateBitset getAvailableFeatures() const {
47511 return AvailableModuleFeatures | AvailableFunctionFeatures;
47512}
47513PredicateBitset
47514computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const;
47515PredicateBitset
47516computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget,
47517 const MachineFunction *MF) const;
47518void setupGeneratedPerFunctionState(MachineFunction &MF) override;
47519
47520#endif // GET_GLOBALISEL_PREDICATES_DECL
47521
47522#ifdef GET_GLOBALISEL_PREDICATES_INIT
47523
47524AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
47525AvailableFunctionFeatures()
47526
47527#endif // GET_GLOBALISEL_PREDICATES_INIT
47528
47529