1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|* *|
3|* Global Instruction Selector for the ARM target *|
4|* *|
5|* Automatically generated file, do not edit! *|
6|* *|
7\*===----------------------------------------------------------------------===*/
8
9#ifdef GET_GLOBALISEL_PREDICATE_BITSET
10const unsigned MAX_SUBTARGET_PREDICATES = 83;
11using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>;
12#endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET
13
14#ifdef GET_GLOBALISEL_TEMPORARIES_DECL
15 mutable MatcherState State;
16 typedef ComplexRendererFns(ARMInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const;
17 typedef void(ARMInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const;
18 const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo;
19 static ARMInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[];
20 static ARMInstructionSelector::CustomRendererFn CustomRenderers[];
21 bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override;
22 bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override;
23 bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override;
24 const uint8_t *getMatchTable() const override;
25 bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override;
26 bool testMOPredicate_MO(unsigned PredicateID, const MachineOperand &MO, const MatcherState &State) const override;
27 bool testSimplePredicate(unsigned PredicateID) const override;
28 bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override;
29#endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL
30
31#ifdef GET_GLOBALISEL_TEMPORARIES_INIT
32, State(0),
33ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers)
34#endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT
35
36#ifdef GET_GLOBALISEL_IMPL
37// LLT Objects.
38enum {
39 GILLT_s16,
40 GILLT_s32,
41 GILLT_s64,
42 GILLT_v2s1,
43 GILLT_v2s32,
44 GILLT_v2s64,
45 GILLT_v4s1,
46 GILLT_v4s16,
47 GILLT_v4s32,
48 GILLT_v4s64,
49 GILLT_v8s1,
50 GILLT_v8s8,
51 GILLT_v8s16,
52 GILLT_v8s64,
53 GILLT_v16s1,
54 GILLT_v16s8,
55};
56const static size_t NumTypeObjects = 16;
57const static LLT TypeObjects[] = {
58 LLT::scalar(16),
59 LLT::scalar(32),
60 LLT::scalar(64),
61 LLT::vector(ElementCount::getFixed(2), 1),
62 LLT::vector(ElementCount::getFixed(2), 32),
63 LLT::vector(ElementCount::getFixed(2), 64),
64 LLT::vector(ElementCount::getFixed(4), 1),
65 LLT::vector(ElementCount::getFixed(4), 16),
66 LLT::vector(ElementCount::getFixed(4), 32),
67 LLT::vector(ElementCount::getFixed(4), 64),
68 LLT::vector(ElementCount::getFixed(8), 1),
69 LLT::vector(ElementCount::getFixed(8), 8),
70 LLT::vector(ElementCount::getFixed(8), 16),
71 LLT::vector(ElementCount::getFixed(8), 64),
72 LLT::vector(ElementCount::getFixed(16), 1),
73 LLT::vector(ElementCount::getFixed(16), 8),
74};
75
76// Bits for subtarget features that participate in instruction matching.
77enum SubtargetFeatureBits : uint8_t {
78 Feature_NoHonorSignDependentRoundingBit = 73,
79 Feature_HasV4TBit = 4,
80 Feature_NoV4TBit = 5,
81 Feature_HasV5TBit = 11,
82 Feature_NoV5TBit = 63,
83 Feature_HasV5TEBit = 9,
84 Feature_HasV6Bit = 0,
85 Feature_NoV6Bit = 7,
86 Feature_HasV6MBit = 26,
87 Feature_HasV8MBaselineBit = 33,
88 Feature_HasV8_1MMainlineBit = 39,
89 Feature_HasMVEIntBit = 61,
90 Feature_HasMVEFloatBit = 62,
91 Feature_HasCDEBit = 82,
92 Feature_HasFPRegsBit = 40,
93 Feature_HasFPRegs16Bit = 41,
94 Feature_HasFPRegs64Bit = 74,
95 Feature_HasV6T2Bit = 6,
96 Feature_HasV6KBit = 16,
97 Feature_HasV7Bit = 3,
98 Feature_HasV8Bit = 53,
99 Feature_PreV8Bit = 17,
100 Feature_HasV8_1aBit = 76,
101 Feature_HasV8_3aBit = 77,
102 Feature_NoVFPBit = 20,
103 Feature_HasVFP2Bit = 19,
104 Feature_HasVFP3Bit = 50,
105 Feature_HasVFP4Bit = 48,
106 Feature_HasDPVFPBit = 42,
107 Feature_HasFPARMv8Bit = 45,
108 Feature_HasNEONBit = 51,
109 Feature_HasSHA2Bit = 60,
110 Feature_HasAESBit = 52,
111 Feature_HasDotProdBit = 54,
112 Feature_HasCRCBit = 12,
113 Feature_HasLOBBit = 38,
114 Feature_HasFP16Bit = 59,
115 Feature_HasFullFP16Bit = 44,
116 Feature_HasMatMulInt8Bit = 55,
117 Feature_HasDivideInThumbBit = 35,
118 Feature_HasDivideInARMBit = 10,
119 Feature_HasDSPBit = 34,
120 Feature_HasDBBit = 13,
121 Feature_HasV7ClrexBit = 15,
122 Feature_HasAcquireReleaseBit = 14,
123 Feature_HasMPBit = 2,
124 Feature_Has8MSecExtBit = 27,
125 Feature_HasZCZBit = 56,
126 Feature_UseNEONForFPBit = 80,
127 Feature_DontUseNEONForFPBit = 43,
128 Feature_IsThumbBit = 24,
129 Feature_IsThumb1OnlyBit = 25,
130 Feature_IsThumb2Bit = 32,
131 Feature_IsNotMClassBit = 36,
132 Feature_IsARMBit = 1,
133 Feature_IsWindowsBit = 28,
134 Feature_IsNotWindowsBit = 29,
135 Feature_IsReadTPTPIDRURWBit = 66,
136 Feature_IsReadTPTPIDRUROBit = 67,
137 Feature_IsReadTPTPIDRPRWBit = 68,
138 Feature_IsReadTPSoftBit = 18,
139 Feature_UseMovtBit = 37,
140 Feature_DontUseMovtBit = 21,
141 Feature_UseMovtInPicBit = 22,
142 Feature_DontUseMovtInPicBit = 23,
143 Feature_UseFPVMLxBit = 47,
144 Feature_SLSBLRMitigationBit = 65,
145 Feature_NoSLSBLRMitigationBit = 64,
146 Feature_UseMulOpsBit = 8,
147 Feature_UseFusedMACBit = 49,
148 Feature_HasFastVGETLNi32Bit = 57,
149 Feature_HasSlowVGETLNi32Bit = 78,
150 Feature_HasFastVDUP32Bit = 58,
151 Feature_HasSlowVDUP32Bit = 79,
152 Feature_UseVMOVSRBit = 46,
153 Feature_DontUseVMOVSRBit = 81,
154 Feature_IsLEBit = 72,
155 Feature_IsBEBit = 75,
156 Feature_GenExecuteOnlyBit = 31,
157 Feature_DontGenExecuteOnlyBit = 30,
158 Feature_GenT1ExecuteOnlyBit = 71,
159 Feature_SignRetAddrBit = 70,
160 Feature_NoSignRetAddrBit = 69,
161};
162
163PredicateBitset ARMInstructionSelector::
164computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const {
165 PredicateBitset Features{};
166 if (!TM.Options.HonorSignDependentRoundingFPMath())
167 Features.set(Feature_NoHonorSignDependentRoundingBit);
168 if (Subtarget->hasV4TOps())
169 Features.set(Feature_HasV4TBit);
170 if (!Subtarget->hasV4TOps())
171 Features.set(Feature_NoV4TBit);
172 if (Subtarget->hasV5TOps())
173 Features.set(Feature_HasV5TBit);
174 if (!Subtarget->hasV5TOps())
175 Features.set(Feature_NoV5TBit);
176 if (Subtarget->hasV5TEOps())
177 Features.set(Feature_HasV5TEBit);
178 if (Subtarget->hasV6Ops())
179 Features.set(Feature_HasV6Bit);
180 if (!Subtarget->hasV6Ops())
181 Features.set(Feature_NoV6Bit);
182 if (Subtarget->hasV6MOps())
183 Features.set(Feature_HasV6MBit);
184 if (Subtarget->hasV8MBaselineOps())
185 Features.set(Feature_HasV8MBaselineBit);
186 if (Subtarget->hasV8_1MMainlineOps())
187 Features.set(Feature_HasV8_1MMainlineBit);
188 if (Subtarget->hasMVEIntegerOps())
189 Features.set(Feature_HasMVEIntBit);
190 if (Subtarget->hasMVEFloatOps())
191 Features.set(Feature_HasMVEFloatBit);
192 if (Subtarget->hasCDEOps())
193 Features.set(Feature_HasCDEBit);
194 if (Subtarget->hasFPRegs())
195 Features.set(Feature_HasFPRegsBit);
196 if (Subtarget->hasFPRegs16())
197 Features.set(Feature_HasFPRegs16Bit);
198 if (Subtarget->hasFPRegs64())
199 Features.set(Feature_HasFPRegs64Bit);
200 if (Subtarget->hasV6T2Ops())
201 Features.set(Feature_HasV6T2Bit);
202 if (Subtarget->hasV6KOps())
203 Features.set(Feature_HasV6KBit);
204 if (Subtarget->hasV7Ops())
205 Features.set(Feature_HasV7Bit);
206 if (Subtarget->hasV8Ops())
207 Features.set(Feature_HasV8Bit);
208 if (!Subtarget->hasV8Ops())
209 Features.set(Feature_PreV8Bit);
210 if (Subtarget->hasV8_1aOps())
211 Features.set(Feature_HasV8_1aBit);
212 if (Subtarget->hasV8_3aOps())
213 Features.set(Feature_HasV8_3aBit);
214 if (!Subtarget->hasVFP2Base())
215 Features.set(Feature_NoVFPBit);
216 if (Subtarget->hasVFP2Base())
217 Features.set(Feature_HasVFP2Bit);
218 if (Subtarget->hasVFP3Base())
219 Features.set(Feature_HasVFP3Bit);
220 if (Subtarget->hasVFP4Base())
221 Features.set(Feature_HasVFP4Bit);
222 if (Subtarget->hasFP64())
223 Features.set(Feature_HasDPVFPBit);
224 if (Subtarget->hasFPARMv8Base())
225 Features.set(Feature_HasFPARMv8Bit);
226 if (Subtarget->hasNEON())
227 Features.set(Feature_HasNEONBit);
228 if (Subtarget->hasSHA2())
229 Features.set(Feature_HasSHA2Bit);
230 if (Subtarget->hasAES())
231 Features.set(Feature_HasAESBit);
232 if (Subtarget->hasDotProd())
233 Features.set(Feature_HasDotProdBit);
234 if (Subtarget->hasCRC())
235 Features.set(Feature_HasCRCBit);
236 if (Subtarget->hasLOB())
237 Features.set(Feature_HasLOBBit);
238 if (Subtarget->hasFP16())
239 Features.set(Feature_HasFP16Bit);
240 if (Subtarget->hasFullFP16())
241 Features.set(Feature_HasFullFP16Bit);
242 if (Subtarget->hasMatMulInt8())
243 Features.set(Feature_HasMatMulInt8Bit);
244 if (Subtarget->hasDivideInThumbMode())
245 Features.set(Feature_HasDivideInThumbBit);
246 if (Subtarget->hasDivideInARMMode())
247 Features.set(Feature_HasDivideInARMBit);
248 if (Subtarget->hasDSP())
249 Features.set(Feature_HasDSPBit);
250 if (Subtarget->hasDataBarrier())
251 Features.set(Feature_HasDBBit);
252 if (Subtarget->hasV7Clrex())
253 Features.set(Feature_HasV7ClrexBit);
254 if (Subtarget->hasAcquireRelease())
255 Features.set(Feature_HasAcquireReleaseBit);
256 if (Subtarget->hasMPExtension())
257 Features.set(Feature_HasMPBit);
258 if (Subtarget->has8MSecExt())
259 Features.set(Feature_Has8MSecExtBit);
260 if (Subtarget->hasZeroCycleZeroing())
261 Features.set(Feature_HasZCZBit);
262 if (Subtarget->useNEONForSinglePrecisionFP())
263 Features.set(Feature_UseNEONForFPBit);
264 if (!Subtarget->useNEONForSinglePrecisionFP())
265 Features.set(Feature_DontUseNEONForFPBit);
266 if (Subtarget->isThumb())
267 Features.set(Feature_IsThumbBit);
268 if (Subtarget->isThumb1Only())
269 Features.set(Feature_IsThumb1OnlyBit);
270 if (Subtarget->isThumb2())
271 Features.set(Feature_IsThumb2Bit);
272 if (!Subtarget->isMClass())
273 Features.set(Feature_IsNotMClassBit);
274 if (!Subtarget->isThumb())
275 Features.set(Feature_IsARMBit);
276 if (Subtarget->isTargetWindows())
277 Features.set(Feature_IsWindowsBit);
278 if (!Subtarget->isTargetWindows())
279 Features.set(Feature_IsNotWindowsBit);
280 if (Subtarget->isReadTPTPIDRURW())
281 Features.set(Feature_IsReadTPTPIDRURWBit);
282 if (Subtarget->isReadTPTPIDRURO())
283 Features.set(Feature_IsReadTPTPIDRUROBit);
284 if (Subtarget->isReadTPTPIDRPRW())
285 Features.set(Feature_IsReadTPTPIDRPRWBit);
286 if (Subtarget->isReadTPSoft())
287 Features.set(Feature_IsReadTPSoftBit);
288 if (Subtarget->useMulOps())
289 Features.set(Feature_UseMulOpsBit);
290 if (TM.Options.AllowFPOpFusion == FPOpFusion::Fast && Subtarget->useFPVFMx())
291 Features.set(Feature_UseFusedMACBit);
292 if (!Subtarget->hasSlowVGETLNi32())
293 Features.set(Feature_HasFastVGETLNi32Bit);
294 if (Subtarget->hasSlowVGETLNi32())
295 Features.set(Feature_HasSlowVGETLNi32Bit);
296 if (!Subtarget->hasSlowVDUP32())
297 Features.set(Feature_HasFastVDUP32Bit);
298 if (Subtarget->hasSlowVDUP32())
299 Features.set(Feature_HasSlowVDUP32Bit);
300 if (Subtarget->preferVMOVSR() ||!Subtarget->useNEONForSinglePrecisionFP())
301 Features.set(Feature_UseVMOVSRBit);
302 if (!Subtarget->preferVMOVSR() &&Subtarget->useNEONForSinglePrecisionFP())
303 Features.set(Feature_DontUseVMOVSRBit);
304 if (Subtarget->genExecuteOnly())
305 Features.set(Feature_GenExecuteOnlyBit);
306 if (!Subtarget->genExecuteOnly())
307 Features.set(Feature_DontGenExecuteOnlyBit);
308 if (Subtarget->genExecuteOnly() && Subtarget->isThumb1Only() && !Subtarget->hasV8MBaselineOps())
309 Features.set(Feature_GenT1ExecuteOnlyBit);
310 return Features;
311}
312
313void ARMInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) {
314 AvailableFunctionFeatures = computeAvailableFunctionFeatures((const ARMSubtarget *)&MF.getSubtarget(), &MF);
315}
316PredicateBitset ARMInstructionSelector::
317computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget, const MachineFunction *MF) const {
318 PredicateBitset Features{};
319 if (Subtarget->useMovt())
320 Features.set(Feature_UseMovtBit);
321 if (!Subtarget->useMovt())
322 Features.set(Feature_DontUseMovtBit);
323 if (Subtarget->useMovt() && Subtarget->allowPositionIndependentMovt())
324 Features.set(Feature_UseMovtInPicBit);
325 if (!Subtarget->useMovt() || !Subtarget->allowPositionIndependentMovt())
326 Features.set(Feature_DontUseMovtInPicBit);
327 if (((Subtarget->useFPVMLx() && TM.Options.AllowFPOpFusion != FPOpFusion::Fast) ||Subtarget->hasMinSize()))
328 Features.set(Feature_UseFPVMLxBit);
329 if ( MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
330 Features.set(Feature_SLSBLRMitigationBit);
331 if ( !MF->getSubtarget<ARMSubtarget>().hardenSlsBlr() )
332 Features.set(Feature_NoSLSBLRMitigationBit);
333 if (MF->getDataLayout().isLittleEndian())
334 Features.set(Feature_IsLEBit);
335 if (MF->getDataLayout().isBigEndian())
336 Features.set(Feature_IsBEBit);
337 if ( MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) )
338 Features.set(Feature_SignRetAddrBit);
339 if ( !MF->getInfo<ARMFunctionInfo>()->shouldSignReturnAddress(true) )
340 Features.set(Feature_NoSignRetAddrBit);
341 return Features;
342}
343
344// Feature bitsets.
345enum {
346 GIFBS_Invalid,
347 GIFBS_HasDotProd,
348 GIFBS_HasFP16,
349 GIFBS_HasFPARMv8,
350 GIFBS_HasFPRegs,
351 GIFBS_HasFullFP16,
352 GIFBS_HasMVEFloat,
353 GIFBS_HasMVEInt,
354 GIFBS_HasMatMulInt8,
355 GIFBS_HasNEON,
356 GIFBS_HasVFP2,
357 GIFBS_HasVFP3,
358 GIFBS_HasVFP4,
359 GIFBS_IsARM,
360 GIFBS_IsThumb,
361 GIFBS_IsThumb2,
362 GIFBS_NoHonorSignDependentRounding,
363 GIFBS_DontUseNEONForFP_HasVFP2,
364 GIFBS_DontUseVMOVSR_HasNEON,
365 GIFBS_Has8MSecExt_IsThumb,
366 GIFBS_HasAES_HasV8,
367 GIFBS_HasCRC_IsARM,
368 GIFBS_HasCRC_IsThumb2,
369 GIFBS_HasDB_IsARM,
370 GIFBS_HasDB_IsThumb,
371 GIFBS_HasDPVFP_HasFPARMv8,
372 GIFBS_HasDPVFP_HasVFP2,
373 GIFBS_HasDPVFP_HasVFP3,
374 GIFBS_HasDPVFP_HasVFP4,
375 GIFBS_HasDPVFP_NoHonorSignDependentRounding,
376 GIFBS_HasDSP_IsThumb2,
377 GIFBS_HasDivideInARM_IsARM,
378 GIFBS_HasFP16_HasNEON,
379 GIFBS_HasFPARMv8_HasNEON,
380 GIFBS_HasFPRegs_HasFastVGETLNi32,
381 GIFBS_HasFPRegs_UseVMOVSR,
382 GIFBS_HasFullFP16_HasNEON,
383 GIFBS_HasMVEInt_HasV8_1MMainline,
384 GIFBS_HasMVEInt_IsBE,
385 GIFBS_HasMVEInt_IsLE,
386 GIFBS_HasNEON_HasV8,
387 GIFBS_HasNEON_HasV8_1a,
388 GIFBS_HasNEON_HasV8_3a,
389 GIFBS_HasNEON_HasVFP4,
390 GIFBS_HasNEON_IsBE,
391 GIFBS_HasNEON_IsLE,
392 GIFBS_HasNEON_UseNEONForFP,
393 GIFBS_HasSHA2_HasV8,
394 GIFBS_HasV5T_IsARM,
395 GIFBS_HasV5T_IsThumb,
396 GIFBS_HasV5TE_IsARM,
397 GIFBS_HasV6_IsARM,
398 GIFBS_HasV6K_IsARM,
399 GIFBS_HasV6M_IsThumb,
400 GIFBS_HasV6T2_IsARM,
401 GIFBS_HasV7_IsARM,
402 GIFBS_HasV7Clrex_IsThumb,
403 GIFBS_HasV8MBaseline_IsThumb,
404 GIFBS_IsARM_NoV5T,
405 GIFBS_IsARM_NoV6,
406 GIFBS_IsARM_PreV8,
407 GIFBS_IsThumb_IsThumb1Only,
408 GIFBS_IsThumb_IsWindows,
409 GIFBS_IsThumb_NoV5T,
410 GIFBS_IsThumb_UseMovt,
411 GIFBS_IsThumb2_PreV8,
412 GIFBS_IsThumb2_UseMulOps,
413 GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only,
414 GIFBS_HasDSP_IsThumb2_UseMulOps,
415 GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb,
416 GIFBS_HasFPARMv8_HasFullFP16_HasNEON,
417 GIFBS_HasFullFP16_HasNEON_HasV8,
418 GIFBS_HasFullFP16_HasNEON_HasV8_3a,
419 GIFBS_HasFullFP16_HasNEON_UseFPVMLx,
420 GIFBS_HasFullFP16_HasNEON_UseFusedMAC,
421 GIFBS_HasLOB_HasV8_1MMainline_IsThumb2,
422 GIFBS_HasNEON_UseFPVMLx_UseNEONForFP,
423 GIFBS_HasV5TE_IsARM_UseMulOps,
424 GIFBS_HasV6_IsARM_UseMulOps,
425 GIFBS_HasV6_IsThumb_IsThumb1Only,
426 GIFBS_HasV6T2_IsARM_UseMulOps,
427 GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP,
428 GIFBS_IsARM_NoV6_UseMulOps,
429};
430constexpr static PredicateBitset FeatureBitsets[] {
431 {}, // GIFBS_Invalid
432 {Feature_HasDotProdBit, },
433 {Feature_HasFP16Bit, },
434 {Feature_HasFPARMv8Bit, },
435 {Feature_HasFPRegsBit, },
436 {Feature_HasFullFP16Bit, },
437 {Feature_HasMVEFloatBit, },
438 {Feature_HasMVEIntBit, },
439 {Feature_HasMatMulInt8Bit, },
440 {Feature_HasNEONBit, },
441 {Feature_HasVFP2Bit, },
442 {Feature_HasVFP3Bit, },
443 {Feature_HasVFP4Bit, },
444 {Feature_IsARMBit, },
445 {Feature_IsThumbBit, },
446 {Feature_IsThumb2Bit, },
447 {Feature_NoHonorSignDependentRoundingBit, },
448 {Feature_DontUseNEONForFPBit, Feature_HasVFP2Bit, },
449 {Feature_DontUseVMOVSRBit, Feature_HasNEONBit, },
450 {Feature_Has8MSecExtBit, Feature_IsThumbBit, },
451 {Feature_HasAESBit, Feature_HasV8Bit, },
452 {Feature_HasCRCBit, Feature_IsARMBit, },
453 {Feature_HasCRCBit, Feature_IsThumb2Bit, },
454 {Feature_HasDBBit, Feature_IsARMBit, },
455 {Feature_HasDBBit, Feature_IsThumbBit, },
456 {Feature_HasDPVFPBit, Feature_HasFPARMv8Bit, },
457 {Feature_HasDPVFPBit, Feature_HasVFP2Bit, },
458 {Feature_HasDPVFPBit, Feature_HasVFP3Bit, },
459 {Feature_HasDPVFPBit, Feature_HasVFP4Bit, },
460 {Feature_HasDPVFPBit, Feature_NoHonorSignDependentRoundingBit, },
461 {Feature_HasDSPBit, Feature_IsThumb2Bit, },
462 {Feature_HasDivideInARMBit, Feature_IsARMBit, },
463 {Feature_HasFP16Bit, Feature_HasNEONBit, },
464 {Feature_HasFPARMv8Bit, Feature_HasNEONBit, },
465 {Feature_HasFPRegsBit, Feature_HasFastVGETLNi32Bit, },
466 {Feature_HasFPRegsBit, Feature_UseVMOVSRBit, },
467 {Feature_HasFullFP16Bit, Feature_HasNEONBit, },
468 {Feature_HasMVEIntBit, Feature_HasV8_1MMainlineBit, },
469 {Feature_HasMVEIntBit, Feature_IsBEBit, },
470 {Feature_HasMVEIntBit, Feature_IsLEBit, },
471 {Feature_HasNEONBit, Feature_HasV8Bit, },
472 {Feature_HasNEONBit, Feature_HasV8_1aBit, },
473 {Feature_HasNEONBit, Feature_HasV8_3aBit, },
474 {Feature_HasNEONBit, Feature_HasVFP4Bit, },
475 {Feature_HasNEONBit, Feature_IsBEBit, },
476 {Feature_HasNEONBit, Feature_IsLEBit, },
477 {Feature_HasNEONBit, Feature_UseNEONForFPBit, },
478 {Feature_HasSHA2Bit, Feature_HasV8Bit, },
479 {Feature_HasV5TBit, Feature_IsARMBit, },
480 {Feature_HasV5TBit, Feature_IsThumbBit, },
481 {Feature_HasV5TEBit, Feature_IsARMBit, },
482 {Feature_HasV6Bit, Feature_IsARMBit, },
483 {Feature_HasV6KBit, Feature_IsARMBit, },
484 {Feature_HasV6MBit, Feature_IsThumbBit, },
485 {Feature_HasV6T2Bit, Feature_IsARMBit, },
486 {Feature_HasV7Bit, Feature_IsARMBit, },
487 {Feature_HasV7ClrexBit, Feature_IsThumbBit, },
488 {Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
489 {Feature_IsARMBit, Feature_NoV5TBit, },
490 {Feature_IsARMBit, Feature_NoV6Bit, },
491 {Feature_IsARMBit, Feature_PreV8Bit, },
492 {Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
493 {Feature_IsThumbBit, Feature_IsWindowsBit, },
494 {Feature_IsThumbBit, Feature_NoV5TBit, },
495 {Feature_IsThumbBit, Feature_UseMovtBit, },
496 {Feature_IsThumb2Bit, Feature_PreV8Bit, },
497 {Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
498 {Feature_DontUseMovtBit, Feature_GenExecuteOnlyBit, Feature_IsThumb1OnlyBit, },
499 {Feature_HasDSPBit, Feature_IsThumb2Bit, Feature_UseMulOpsBit, },
500 {Feature_HasDivideInThumbBit, Feature_HasV8MBaselineBit, Feature_IsThumbBit, },
501 {Feature_HasFPARMv8Bit, Feature_HasFullFP16Bit, Feature_HasNEONBit, },
502 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8Bit, },
503 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_HasV8_3aBit, },
504 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFPVMLxBit, },
505 {Feature_HasFullFP16Bit, Feature_HasNEONBit, Feature_UseFusedMACBit, },
506 {Feature_HasLOBBit, Feature_HasV8_1MMainlineBit, Feature_IsThumb2Bit, },
507 {Feature_HasNEONBit, Feature_UseFPVMLxBit, Feature_UseNEONForFPBit, },
508 {Feature_HasV5TEBit, Feature_IsARMBit, Feature_UseMulOpsBit, },
509 {Feature_HasV6Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
510 {Feature_HasV6Bit, Feature_IsThumbBit, Feature_IsThumb1OnlyBit, },
511 {Feature_HasV6T2Bit, Feature_IsARMBit, Feature_UseMulOpsBit, },
512 {Feature_HasVFP4Bit, Feature_UseFusedMACBit, Feature_UseNEONForFPBit, },
513 {Feature_IsARMBit, Feature_NoV6Bit, Feature_UseMulOpsBit, },
514};
515
516// ComplexPattern predicates.
517enum {
518 GICP_Invalid,
519};
520// See constructor for table contents
521
522ARMInstructionSelector::ComplexMatcherMemFn
523ARMInstructionSelector::ComplexPredicateFns[] = {
524 nullptr, // GICP_Invalid
525};
526
527// PatFrag predicates.
528enum {
529 GICXXPred_MI_Predicate_bf_inv_mask_imm = GICXXPred_Invalid + 1,
530 GICXXPred_MI_Predicate_ffloor_nnan,
531 GICXXPred_MI_Predicate_or_disjoint,
532 GICXXPred_MI_Predicate_vfp_f32imm,
533 GICXXPred_MI_Predicate_vfp_f64imm,
534};
535bool ARMInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const {
536 const MachineFunction &MF = *MI.getParent()->getParent();
537 const MachineRegisterInfo &MRI = MF.getRegInfo();
538 const auto &Operands = State.RecordedOperands;
539 (void)Operands;
540 (void)MRI;
541 switch (PredicateID) {
542 case GICXXPred_MI_Predicate_bf_inv_mask_imm: {
543
544 // There's better methods of implementing this check. IntImmLeaf<> would be
545 // equivalent and have less boilerplate but we need a test for C++
546 // predicates and this one causes new rules to be imported into GlobalISel
547 // without requiring additional features first.
548 const auto &MO = MI.getOperand(1);
549 if (!MO.isCImm())
550 return false;
551 return ARM::isBitFieldInvertedMask(MO.getCImm()->getZExtValue());
552
553 llvm_unreachable("bf_inv_mask_imm should have returned");
554 }
555 case GICXXPred_MI_Predicate_ffloor_nnan: {
556
557 return MI.getFlag(MachineInstr::FmNoNans);
558
559 }
560 case GICXXPred_MI_Predicate_or_disjoint: {
561
562 return MI.getFlag(MachineInstr::Disjoint);
563
564 }
565 case GICXXPred_MI_Predicate_vfp_f32imm: {
566
567 const auto &MO = MI.getOperand(1);
568 if (!MO.isFPImm())
569 return false;
570 return ARM_AM::getFP32Imm(MO.getFPImm()->getValueAPF()) != -1;
571
572 llvm_unreachable("vfp_f32imm should have returned");
573 }
574 case GICXXPred_MI_Predicate_vfp_f64imm: {
575
576 const auto &MO = MI.getOperand(1);
577 if (!MO.isFPImm())
578 return false;
579 return ARM_AM::getFP64Imm(MO.getFPImm()->getValueAPF()) != -1;
580
581 llvm_unreachable("vfp_f64imm should have returned");
582 }
583 }
584 llvm_unreachable("Unknown predicate");
585 return false;
586}
587// PatFrag predicates.
588bool ARMInstructionSelector::testMOPredicate_MO(unsigned PredicateID, const MachineOperand & MO, const MatcherState &State) const {
589 const auto &Operands = State.RecordedOperands;
590 Register Reg = MO.getReg();
591 (void)Operands;
592 (void)Reg;
593 llvm_unreachable("Unknown predicate");
594 return false;
595}
596// PatFrag predicates.
597enum {
598 GICXXPred_I64_Predicate_VectorIndex8 = GICXXPred_Invalid + 1,
599 GICXXPred_I64_Predicate_VectorIndex16,
600 GICXXPred_I64_Predicate_VectorIndex32,
601 GICXXPred_I64_Predicate_VectorIndex32_Hi,
602 GICXXPred_I64_Predicate_VectorIndex64,
603 GICXXPred_I64_Predicate_asr_imm,
604 GICXXPred_I64_Predicate_imm0_7,
605 GICXXPred_I64_Predicate_imm0_15,
606 GICXXPred_I64_Predicate_imm0_31,
607 GICXXPred_I64_Predicate_imm0_32,
608 GICXXPred_I64_Predicate_imm0_63,
609 GICXXPred_I64_Predicate_imm0_239,
610 GICXXPred_I64_Predicate_imm0_255,
611 GICXXPred_I64_Predicate_imm0_255_expr,
612 GICXXPred_I64_Predicate_imm0_4095,
613 GICXXPred_I64_Predicate_imm0_65535,
614 GICXXPred_I64_Predicate_imm0_65535_expr,
615 GICXXPred_I64_Predicate_imm0_65535_neg,
616 GICXXPred_I64_Predicate_imm1_7,
617 GICXXPred_I64_Predicate_imm1_15,
618 GICXXPred_I64_Predicate_imm1_16,
619 GICXXPred_I64_Predicate_imm1_31,
620 GICXXPred_I64_Predicate_imm8,
621 GICXXPred_I64_Predicate_imm8_255,
622 GICXXPred_I64_Predicate_imm8_or_16,
623 GICXXPred_I64_Predicate_imm16,
624 GICXXPred_I64_Predicate_imm16_31,
625 GICXXPred_I64_Predicate_imm24b,
626 GICXXPred_I64_Predicate_imm32,
627 GICXXPred_I64_Predicate_imm256_510,
628 GICXXPred_I64_Predicate_imm_3b,
629 GICXXPred_I64_Predicate_imm_4b,
630 GICXXPred_I64_Predicate_imm_6b,
631 GICXXPred_I64_Predicate_imm_7b,
632 GICXXPred_I64_Predicate_imm_9b,
633 GICXXPred_I64_Predicate_imm_11b,
634 GICXXPred_I64_Predicate_imm_12b,
635 GICXXPred_I64_Predicate_imm_13b,
636 GICXXPred_I64_Predicate_imm_even,
637 GICXXPred_I64_Predicate_imm_odd,
638 GICXXPred_I64_Predicate_imm_sr,
639 GICXXPred_I64_Predicate_long_shift,
640 GICXXPred_I64_Predicate_mod_imm,
641 GICXXPred_I64_Predicate_mod_imm_not,
642 GICXXPred_I64_Predicate_pkh_asr_amt,
643 GICXXPred_I64_Predicate_pkh_lsl_amt,
644 GICXXPred_I64_Predicate_shr_imm8,
645 GICXXPred_I64_Predicate_shr_imm16,
646 GICXXPred_I64_Predicate_shr_imm32,
647 GICXXPred_I64_Predicate_shr_imm64,
648 GICXXPred_I64_Predicate_t2_so_imm,
649 GICXXPred_I64_Predicate_t2_so_imm_neg,
650};
651bool ARMInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const {
652 switch (PredicateID) {
653 case GICXXPred_I64_Predicate_VectorIndex8: {
654
655 return ((uint64_t)Imm) < 8;
656
657 }
658 case GICXXPred_I64_Predicate_VectorIndex16: {
659
660 return ((uint64_t)Imm) < 4;
661
662 }
663 case GICXXPred_I64_Predicate_VectorIndex32: {
664
665 return ((uint64_t)Imm) < 2;
666
667 }
668 case GICXXPred_I64_Predicate_VectorIndex32_Hi: {
669
670 return ((uint64_t)Imm) >= 2 && ((uint64_t)Imm) < 4;
671
672 }
673 case GICXXPred_I64_Predicate_VectorIndex64: {
674
675 return ((uint64_t)Imm) < 1;
676
677 }
678 case GICXXPred_I64_Predicate_asr_imm: {
679 return Imm > 0 && Imm <= 32;
680 }
681 case GICXXPred_I64_Predicate_imm0_7: {
682
683 return Imm >= 0 && Imm < 8;
684
685 }
686 case GICXXPred_I64_Predicate_imm0_15: {
687
688 return Imm >= 0 && Imm < 16;
689
690 }
691 case GICXXPred_I64_Predicate_imm0_31: {
692
693 return Imm >= 0 && Imm < 32;
694
695 }
696 case GICXXPred_I64_Predicate_imm0_32: {
697
698 return Imm >= 0 && Imm < 33;
699
700 }
701 case GICXXPred_I64_Predicate_imm0_63: {
702
703 return Imm >= 0 && Imm < 64;
704
705 }
706 case GICXXPred_I64_Predicate_imm0_239: {
707 return Imm >= 0 && Imm < 240;
708 }
709 case GICXXPred_I64_Predicate_imm0_255: {
710 return Imm >= 0 && Imm < 256;
711 }
712 case GICXXPred_I64_Predicate_imm0_255_expr: {
713 return Imm >= 0 && Imm < 256;
714 }
715 case GICXXPred_I64_Predicate_imm0_4095: {
716
717 return Imm >= 0 && Imm < 4096;
718
719 }
720 case GICXXPred_I64_Predicate_imm0_65535: {
721
722 return Imm >= 0 && Imm < 65536;
723
724 }
725 case GICXXPred_I64_Predicate_imm0_65535_expr: {
726
727 return Imm >= 0 && Imm < 65536;
728
729 }
730 case GICXXPred_I64_Predicate_imm0_65535_neg: {
731
732 return -Imm >= 0 && -Imm < 65536;
733
734 }
735 case GICXXPred_I64_Predicate_imm1_7: {
736 return Imm > 0 && Imm < 8;
737 }
738 case GICXXPred_I64_Predicate_imm1_15: {
739 return Imm > 0 && Imm < 16;
740 }
741 case GICXXPred_I64_Predicate_imm1_16: {
742
743 return Imm > 0 && Imm <= 16;
744
745 }
746 case GICXXPred_I64_Predicate_imm1_31: {
747 return Imm > 0 && Imm < 32;
748 }
749 case GICXXPred_I64_Predicate_imm8: {
750 return Imm == 8;
751 }
752 case GICXXPred_I64_Predicate_imm8_255: {
753
754 return Imm >= 8 && Imm < 256;
755
756 }
757 case GICXXPred_I64_Predicate_imm8_or_16: {
758 return Imm == 8 || Imm == 16;
759 }
760 case GICXXPred_I64_Predicate_imm16: {
761 return Imm == 16;
762 }
763 case GICXXPred_I64_Predicate_imm16_31: {
764
765 return (int32_t)Imm >= 16 && (int32_t)Imm < 32;
766
767 }
768 case GICXXPred_I64_Predicate_imm24b: {
769
770 return Imm >= 0 && Imm <= 0xffffff;
771
772 }
773 case GICXXPred_I64_Predicate_imm32: {
774 return Imm == 32;
775 }
776 case GICXXPred_I64_Predicate_imm256_510: {
777
778 return Imm >= 256 && Imm < 511;
779
780 }
781 case GICXXPred_I64_Predicate_imm_3b: {
782 { return Imm >= 0 && Imm < (1 << 3); }
783 llvm_unreachable("imm_3b should have returned");
784 }
785 case GICXXPred_I64_Predicate_imm_4b: {
786 { return Imm >= 0 && Imm < (1 << 4); }
787 llvm_unreachable("imm_4b should have returned");
788 }
789 case GICXXPred_I64_Predicate_imm_6b: {
790 { return Imm >= 0 && Imm < (1 << 6); }
791 llvm_unreachable("imm_6b should have returned");
792 }
793 case GICXXPred_I64_Predicate_imm_7b: {
794 { return Imm >= 0 && Imm < (1 << 7); }
795 llvm_unreachable("imm_7b should have returned");
796 }
797 case GICXXPred_I64_Predicate_imm_9b: {
798 { return Imm >= 0 && Imm < (1 << 9); }
799 llvm_unreachable("imm_9b should have returned");
800 }
801 case GICXXPred_I64_Predicate_imm_11b: {
802 { return Imm >= 0 && Imm < (1 << 11); }
803 llvm_unreachable("imm_11b should have returned");
804 }
805 case GICXXPred_I64_Predicate_imm_12b: {
806 { return Imm >= 0 && Imm < (1 << 12); }
807 llvm_unreachable("imm_12b should have returned");
808 }
809 case GICXXPred_I64_Predicate_imm_13b: {
810 { return Imm >= 0 && Imm < (1 << 13); }
811 llvm_unreachable("imm_13b should have returned");
812 }
813 case GICXXPred_I64_Predicate_imm_even: {
814 return (Imm & 1) == 0;
815 }
816 case GICXXPred_I64_Predicate_imm_odd: {
817 return (Imm & 1) == 1;
818 }
819 case GICXXPred_I64_Predicate_imm_sr: {
820
821 return Imm > 0 && Imm <= 32;
822
823 }
824 case GICXXPred_I64_Predicate_long_shift: {
825 return Imm > 0 && Imm <= 32;
826 }
827 case GICXXPred_I64_Predicate_mod_imm: {
828
829 return ARM_AM::getSOImmVal(Imm) != -1;
830
831 }
832 case GICXXPred_I64_Predicate_mod_imm_not: {
833
834 return ARM_AM::getSOImmVal(~(uint32_t)Imm) != -1;
835
836 }
837 case GICXXPred_I64_Predicate_pkh_asr_amt: {
838 return Imm > 0 && Imm <= 32;
839 }
840 case GICXXPred_I64_Predicate_pkh_lsl_amt: {
841 return Imm >= 0 && Imm < 32;
842 }
843 case GICXXPred_I64_Predicate_shr_imm8: {
844 return Imm > 0 && Imm <= 8;
845 }
846 case GICXXPred_I64_Predicate_shr_imm16: {
847 return Imm > 0 && Imm <= 16;
848 }
849 case GICXXPred_I64_Predicate_shr_imm32: {
850 return Imm > 0 && Imm <= 32;
851 }
852 case GICXXPred_I64_Predicate_shr_imm64: {
853 return Imm > 0 && Imm <= 64;
854 }
855 case GICXXPred_I64_Predicate_t2_so_imm: {
856
857 return ARM_AM::getT2SOImmVal(Imm) != -1;
858
859 }
860 case GICXXPred_I64_Predicate_t2_so_imm_neg: {
861
862 return Imm && ARM_AM::getT2SOImmVal(-(uint32_t)Imm) != -1;
863
864 }
865 }
866 llvm_unreachable("Unknown predicate");
867 return false;
868}
869// PatFrag predicates.
870bool ARMInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const {
871 llvm_unreachable("Unknown predicate");
872 return false;
873}
874// PatFrag predicates.
875enum {
876 GICXXPred_APInt_Predicate_arm_i32imm = GICXXPred_Invalid + 1,
877};
878bool ARMInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const {
879 switch (PredicateID) {
880 case GICXXPred_APInt_Predicate_arm_i32imm: {
881
882 if (Subtarget->useMovt())
883 return true;
884 if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue()))
885 return true;
886 return ARM_AM::isSOImmTwoPartValNeg(Imm.getZExtValue());
887
888 llvm_unreachable("arm_i32imm should have returned");
889 }
890 }
891 llvm_unreachable("Unknown predicate");
892 return false;
893}
894bool ARMInstructionSelector::testSimplePredicate(unsigned) const {
895 llvm_unreachable("ARMInstructionSelector does not support simple predicates!");
896 return false;
897}
898// Custom renderers.
899enum {
900 GICR_Invalid,
901 GICR_renderInvertedImm,
902 GICR_renderVFPF32Imm,
903 GICR_renderVFPF64Imm,
904};
905ARMInstructionSelector::CustomRendererFn
906ARMInstructionSelector::CustomRenderers[] = {
907 nullptr, // GICR_Invalid
908 &ARMInstructionSelector::renderInvertedImm,
909 &ARMInstructionSelector::renderVFPF32Imm,
910 &ARMInstructionSelector::renderVFPF64Imm,
911};
912
913bool ARMInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const {
914 const PredicateBitset AvailableFeatures = getAvailableFeatures();
915 MachineIRBuilder B(I);
916 State.MIs.clear();
917 State.MIs.push_back(&I);
918
919 if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) {
920 return true;
921 }
922
923 return false;
924}
925
926bool ARMInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const {
927 llvm_unreachable("ARMInstructionSelector does not support custom C++ actions!");
928}
929#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
930#define GIMT_Encode2(Val) uint8_t(Val), uint8_t((Val) >> 8)
931#define GIMT_Encode4(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24)
932#define GIMT_Encode8(Val) uint8_t(Val), uint8_t((Val) >> 8), uint8_t((Val) >> 16), uint8_t((Val) >> 24), uint8_t(uint64_t(Val) >> 32), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 56)
933#else
934#define GIMT_Encode2(Val) uint8_t((Val) >> 8), uint8_t(Val)
935#define GIMT_Encode4(Val) uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
936#define GIMT_Encode8(Val) uint8_t(uint64_t(Val) >> 56), uint8_t(uint64_t(Val) >> 48), uint8_t(uint64_t(Val) >> 40), uint8_t(uint64_t(Val) >> 32), uint8_t((Val) >> 24), uint8_t((Val) >> 16), uint8_t((Val) >> 8), uint8_t(Val)
937#endif
938const uint8_t *ARMInstructionSelector::getMatchTable() const {
939 constexpr static uint8_t MatchTable0[] = {
940 /* 0 */ GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(55), GIMT_Encode2(321), /*)*//*default:*//*Label 91*/ GIMT_Encode4(142606),
941 /* 10 */ /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(1074),
942 /* 14 */ /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(13001),
943 /* 18 */ /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(16245),
944 /* 22 */ /*TargetOpcode::G_SDIV*//*Label 3*/ GIMT_Encode4(17949),
945 /* 26 */ /*TargetOpcode::G_UDIV*//*Label 4*/ GIMT_Encode4(18045), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
946 /* 46 */ /*TargetOpcode::G_AND*//*Label 5*/ GIMT_Encode4(18141),
947 /* 50 */ /*TargetOpcode::G_OR*//*Label 6*/ GIMT_Encode4(21321),
948 /* 54 */ /*TargetOpcode::G_XOR*//*Label 7*/ GIMT_Encode4(27130),
949 /* 58 */ /*TargetOpcode::G_ABDS*//*Label 8*/ GIMT_Encode4(28825),
950 /* 62 */ /*TargetOpcode::G_ABDU*//*Label 9*/ GIMT_Encode4(29368),
951 /* 66 */ /*TargetOpcode::G_UAVGFLOOR*//*Label 10*/ GIMT_Encode4(29911),
952 /* 70 */ /*TargetOpcode::G_UAVGCEIL*//*Label 11*/ GIMT_Encode4(30150),
953 /* 74 */ /*TargetOpcode::G_SAVGFLOOR*//*Label 12*/ GIMT_Encode4(30389),
954 /* 78 */ /*TargetOpcode::G_SAVGCEIL*//*Label 13*/ GIMT_Encode4(30628), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
955 /* 130 */ /*TargetOpcode::G_CONCAT_VECTORS*//*Label 14*/ GIMT_Encode4(30867), GIMT_Encode4(0), GIMT_Encode4(0),
956 /* 142 */ /*TargetOpcode::G_BITCAST*//*Label 15*/ GIMT_Encode4(31254), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
957 /* 158 */ /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 16*/ GIMT_Encode4(40266),
958 /* 162 */ /*TargetOpcode::G_INTRINSIC_ROUND*//*Label 17*/ GIMT_Encode4(40674), GIMT_Encode4(0), GIMT_Encode4(0),
959 /* 174 */ /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 18*/ GIMT_Encode4(41049), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
960 /* 190 */ /*TargetOpcode::G_SEXTLOAD*//*Label 19*/ GIMT_Encode4(41424), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
961 /* 310 */ /*TargetOpcode::G_FENCE*//*Label 20*/ GIMT_Encode4(41587), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
962 /* 330 */ /*TargetOpcode::G_INTRINSIC*//*Label 21*/ GIMT_Encode4(41608),
963 /* 334 */ /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 22*/ GIMT_Encode4(99408), GIMT_Encode4(0), GIMT_Encode4(0),
964 /* 346 */ /*TargetOpcode::G_ANYEXT*//*Label 23*/ GIMT_Encode4(107070),
965 /* 350 */ /*TargetOpcode::G_TRUNC*//*Label 24*/ GIMT_Encode4(107228), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
966 /* 366 */ /*TargetOpcode::G_CONSTANT*//*Label 25*/ GIMT_Encode4(107386),
967 /* 370 */ /*TargetOpcode::G_FCONSTANT*//*Label 26*/ GIMT_Encode4(107707), GIMT_Encode4(0), GIMT_Encode4(0),
968 /* 382 */ /*TargetOpcode::G_SEXT*//*Label 27*/ GIMT_Encode4(107803),
969 /* 386 */ /*TargetOpcode::G_SEXT_INREG*//*Label 28*/ GIMT_Encode4(107961),
970 /* 390 */ /*TargetOpcode::G_ZEXT*//*Label 29*/ GIMT_Encode4(108566),
971 /* 394 */ /*TargetOpcode::G_SHL*//*Label 30*/ GIMT_Encode4(109282),
972 /* 398 */ /*TargetOpcode::G_LSHR*//*Label 31*/ GIMT_Encode4(109498),
973 /* 402 */ /*TargetOpcode::G_ASHR*//*Label 32*/ GIMT_Encode4(109606), GIMT_Encode4(0), GIMT_Encode4(0),
974 /* 414 */ /*TargetOpcode::G_ROTR*//*Label 33*/ GIMT_Encode4(109879), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
975 /* 482 */ /*TargetOpcode::G_UMULH*//*Label 34*/ GIMT_Encode4(110211),
976 /* 486 */ /*TargetOpcode::G_SMULH*//*Label 35*/ GIMT_Encode4(110459),
977 /* 490 */ /*TargetOpcode::G_UADDSAT*//*Label 36*/ GIMT_Encode4(110828),
978 /* 494 */ /*TargetOpcode::G_SADDSAT*//*Label 37*/ GIMT_Encode4(111473),
979 /* 498 */ /*TargetOpcode::G_USUBSAT*//*Label 38*/ GIMT_Encode4(112773),
980 /* 502 */ /*TargetOpcode::G_SSUBSAT*//*Label 39*/ GIMT_Encode4(113418), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
981 /* 546 */ /*TargetOpcode::G_FADD*//*Label 40*/ GIMT_Encode4(114438),
982 /* 550 */ /*TargetOpcode::G_FSUB*//*Label 41*/ GIMT_Encode4(116791),
983 /* 554 */ /*TargetOpcode::G_FMUL*//*Label 42*/ GIMT_Encode4(118468),
984 /* 558 */ /*TargetOpcode::G_FMA*//*Label 43*/ GIMT_Encode4(119449), GIMT_Encode4(0),
985 /* 566 */ /*TargetOpcode::G_FDIV*//*Label 44*/ GIMT_Encode4(121540), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
986 /* 618 */ /*TargetOpcode::G_FNEG*//*Label 45*/ GIMT_Encode4(121705),
987 /* 622 */ /*TargetOpcode::G_FPEXT*//*Label 46*/ GIMT_Encode4(124145),
988 /* 626 */ /*TargetOpcode::G_FPTRUNC*//*Label 47*/ GIMT_Encode4(124381),
989 /* 630 */ /*TargetOpcode::G_FPTOSI*//*Label 48*/ GIMT_Encode4(124653),
990 /* 634 */ /*TargetOpcode::G_FPTOUI*//*Label 49*/ GIMT_Encode4(125987),
991 /* 638 */ /*TargetOpcode::G_SITOFP*//*Label 50*/ GIMT_Encode4(127321),
992 /* 642 */ /*TargetOpcode::G_UITOFP*//*Label 51*/ GIMT_Encode4(127973), GIMT_Encode4(0), GIMT_Encode4(0),
993 /* 654 */ /*TargetOpcode::G_FABS*//*Label 52*/ GIMT_Encode4(128625), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
994 /* 670 */ /*TargetOpcode::G_FMINNUM*//*Label 53*/ GIMT_Encode4(129401),
995 /* 674 */ /*TargetOpcode::G_FMAXNUM*//*Label 54*/ GIMT_Encode4(129993), GIMT_Encode4(0), GIMT_Encode4(0),
996 /* 686 */ /*TargetOpcode::G_FMINIMUM*//*Label 55*/ GIMT_Encode4(130585),
997 /* 690 */ /*TargetOpcode::G_FMAXIMUM*//*Label 56*/ GIMT_Encode4(131319), GIMT_Encode4(0), GIMT_Encode4(0),
998 /* 702 */ /*TargetOpcode::G_GET_FPENV*//*Label 57*/ GIMT_Encode4(132053),
999 /* 706 */ /*TargetOpcode::G_SET_FPENV*//*Label 58*/ GIMT_Encode4(132086),
1000 /* 710 */ /*TargetOpcode::G_RESET_FPENV*//*Label 59*/ GIMT_Encode4(132122),
1001 /* 714 */ /*TargetOpcode::G_GET_FPMODE*//*Label 60*/ GIMT_Encode4(132251), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1002 /* 742 */ /*TargetOpcode::G_SMIN*//*Label 61*/ GIMT_Encode4(132284),
1003 /* 746 */ /*TargetOpcode::G_SMAX*//*Label 62*/ GIMT_Encode4(132827),
1004 /* 750 */ /*TargetOpcode::G_UMIN*//*Label 63*/ GIMT_Encode4(133370),
1005 /* 754 */ /*TargetOpcode::G_UMAX*//*Label 64*/ GIMT_Encode4(134291),
1006 /* 758 */ /*TargetOpcode::G_ABS*//*Label 65*/ GIMT_Encode4(135212), GIMT_Encode4(0), GIMT_Encode4(0),
1007 /* 770 */ /*TargetOpcode::G_BR*//*Label 66*/ GIMT_Encode4(135683), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1008 /* 790 */ /*TargetOpcode::G_INSERT_VECTOR_ELT*//*Label 67*/ GIMT_Encode4(135756),
1009 /* 794 */ /*TargetOpcode::G_EXTRACT_VECTOR_ELT*//*Label 68*/ GIMT_Encode4(136056), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1010 /* 822 */ /*TargetOpcode::G_CTLZ*//*Label 69*/ GIMT_Encode4(136113), GIMT_Encode4(0), GIMT_Encode4(0),
1011 /* 834 */ /*TargetOpcode::G_CTPOP*//*Label 70*/ GIMT_Encode4(136674),
1012 /* 838 */ /*TargetOpcode::G_BSWAP*//*Label 71*/ GIMT_Encode4(136782),
1013 /* 842 */ /*TargetOpcode::G_BITREVERSE*//*Label 72*/ GIMT_Encode4(137072),
1014 /* 846 */ /*TargetOpcode::G_FCEIL*//*Label 73*/ GIMT_Encode4(137504), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1015 /* 894 */ /*TargetOpcode::G_FSQRT*//*Label 74*/ GIMT_Encode4(137879),
1016 /* 898 */ /*TargetOpcode::G_FFLOOR*//*Label 75*/ GIMT_Encode4(138017),
1017 /* 902 */ /*TargetOpcode::G_FRINT*//*Label 76*/ GIMT_Encode4(138392),
1018 /* 906 */ /*TargetOpcode::G_FNEARBYINT*//*Label 77*/ GIMT_Encode4(138800), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1019 /* 934 */ /*TargetOpcode::G_STRICT_FADD*//*Label 78*/ GIMT_Encode4(138938),
1020 /* 938 */ /*TargetOpcode::G_STRICT_FSUB*//*Label 79*/ GIMT_Encode4(139103),
1021 /* 942 */ /*TargetOpcode::G_STRICT_FMUL*//*Label 80*/ GIMT_Encode4(139268),
1022 /* 946 */ /*TargetOpcode::G_STRICT_FDIV*//*Label 81*/ GIMT_Encode4(139433), GIMT_Encode4(0),
1023 /* 954 */ /*TargetOpcode::G_STRICT_FMA*//*Label 82*/ GIMT_Encode4(139598),
1024 /* 958 */ /*TargetOpcode::G_STRICT_FSQRT*//*Label 83*/ GIMT_Encode4(140783), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1025 /* 994 */ /*TargetOpcode::G_TRAP*//*Label 84*/ GIMT_Encode4(140921),
1026 /* 998 */ /*TargetOpcode::G_DEBUGTRAP*//*Label 85*/ GIMT_Encode4(140952), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1027 /* 1038 */ /*TargetOpcode::G_VECREDUCE_ADD*//*Label 86*/ GIMT_Encode4(141039), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
1028 /* 1058 */ /*TargetOpcode::G_VECREDUCE_SMAX*//*Label 87*/ GIMT_Encode4(141460),
1029 /* 1062 */ /*TargetOpcode::G_VECREDUCE_SMIN*//*Label 88*/ GIMT_Encode4(141740),
1030 /* 1066 */ /*TargetOpcode::G_VECREDUCE_UMAX*//*Label 89*/ GIMT_Encode4(142029),
1031 /* 1070 */ /*TargetOpcode::G_VECREDUCE_UMIN*//*Label 90*/ GIMT_Encode4(142310),
1032 /* 1074 */ // Label 0: @1074
1033 /* 1074 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 101*/ GIMT_Encode4(13000),
1034 /* 1085 */ /*GILLT_s32*//*Label 92*/ GIMT_Encode4(1145),
1035 /* 1089 */ /*GILLT_s64*//*Label 93*/ GIMT_Encode4(6921), GIMT_Encode4(0),
1036 /* 1097 */ /*GILLT_v2s32*//*Label 94*/ GIMT_Encode4(6968),
1037 /* 1101 */ /*GILLT_v2s64*//*Label 95*/ GIMT_Encode4(7417), GIMT_Encode4(0),
1038 /* 1109 */ /*GILLT_v4s16*//*Label 96*/ GIMT_Encode4(8440),
1039 /* 1113 */ /*GILLT_v4s32*//*Label 97*/ GIMT_Encode4(8889), GIMT_Encode4(0), GIMT_Encode4(0),
1040 /* 1125 */ /*GILLT_v8s8*//*Label 98*/ GIMT_Encode4(10453),
1041 /* 1129 */ /*GILLT_v8s16*//*Label 99*/ GIMT_Encode4(10902), GIMT_Encode4(0), GIMT_Encode4(0),
1042 /* 1141 */ /*GILLT_v16s8*//*Label 100*/ GIMT_Encode4(12466),
1043 /* 1145 */ // Label 92: @1145
1044 /* 1145 */ GIM_Try, /*On fail goto*//*Label 102*/ GIMT_Encode4(6920),
1045 /* 1150 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
1046 /* 1153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
1047 /* 1156 */ GIM_Try, /*On fail goto*//*Label 103*/ GIMT_Encode4(1231), // Rule ID 6214 //
1048 /* 1161 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
1049 /* 1164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1050 /* 1168 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1051 /* 1172 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1052 /* 1176 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1053 /* 1180 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1054 /* 1184 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1055 /* 1189 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1056 /* 1200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1057 /* 1204 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1058 /* 1206 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1059 /* 1206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB),
1060 /* 1209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1061 /* 1211 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1062 /* 1213 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1063 /* 1217 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1064 /* 1220 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1065 /* 1223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1066 /* 1229 */ GIR_RootConstrainSelectedInstOperands,
1067 /* 1230 */ // GIR_Coverage, 6214,
1068 /* 1230 */ GIR_EraseRootFromParent_Done,
1069 /* 1231 */ // Label 103: @1231
1070 /* 1231 */ GIM_Try, /*On fail goto*//*Label 104*/ GIMT_Encode4(1306), // Rule ID 6215 //
1071 /* 1236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
1072 /* 1239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1073 /* 1243 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1074 /* 1247 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1075 /* 1251 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1076 /* 1255 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1077 /* 1259 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1078 /* 1264 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1079 /* 1275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1080 /* 1279 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1081 /* 1281 */ // (add:{ *:[i32] } (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1082 /* 1281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH),
1083 /* 1284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1084 /* 1286 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1085 /* 1288 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1086 /* 1292 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1087 /* 1295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1088 /* 1298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1089 /* 1304 */ GIR_RootConstrainSelectedInstOperands,
1090 /* 1305 */ // GIR_Coverage, 6215,
1091 /* 1305 */ GIR_EraseRootFromParent_Done,
1092 /* 1306 */ // Label 104: @1306
1093 /* 1306 */ GIM_Try, /*On fail goto*//*Label 105*/ GIMT_Encode4(1381), // Rule ID 6249 //
1094 /* 1311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1095 /* 1314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1096 /* 1318 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1097 /* 1322 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1098 /* 1326 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1099 /* 1330 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1100 /* 1334 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1101 /* 1339 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1102 /* 1350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1103 /* 1354 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1104 /* 1356 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1105 /* 1356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB),
1106 /* 1359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1107 /* 1361 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1108 /* 1363 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1109 /* 1367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1110 /* 1370 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1111 /* 1373 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1112 /* 1379 */ GIR_RootConstrainSelectedInstOperands,
1113 /* 1380 */ // GIR_Coverage, 6249,
1114 /* 1380 */ GIR_EraseRootFromParent_Done,
1115 /* 1381 */ // Label 105: @1381
1116 /* 1381 */ GIM_Try, /*On fail goto*//*Label 106*/ GIMT_Encode4(1456), // Rule ID 6250 //
1117 /* 1386 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1118 /* 1389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1119 /* 1393 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1120 /* 1397 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1121 /* 1401 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1122 /* 1405 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1123 /* 1409 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1124 /* 1414 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1125 /* 1425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1126 /* 1429 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1127 /* 1431 */ // (add:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1128 /* 1431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH),
1129 /* 1434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1130 /* 1436 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1131 /* 1438 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1132 /* 1442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1133 /* 1445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1134 /* 1448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1135 /* 1454 */ GIR_RootConstrainSelectedInstOperands,
1136 /* 1455 */ // GIR_Coverage, 6250,
1137 /* 1455 */ GIR_EraseRootFromParent_Done,
1138 /* 1456 */ // Label 106: @1456
1139 /* 1456 */ GIM_Try, /*On fail goto*//*Label 107*/ GIMT_Encode4(1531), // Rule ID 2161 //
1140 /* 1461 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
1141 /* 1464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1142 /* 1468 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1143 /* 1472 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1144 /* 1476 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1145 /* 1480 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1146 /* 1484 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1147 /* 1488 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1148 /* 1493 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1149 /* 1504 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1150 /* 1506 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (UXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1151 /* 1506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB),
1152 /* 1509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1153 /* 1511 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1154 /* 1513 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1155 /* 1517 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1156 /* 1520 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1157 /* 1523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1158 /* 1529 */ GIR_RootConstrainSelectedInstOperands,
1159 /* 1530 */ // GIR_Coverage, 2161,
1160 /* 1530 */ GIR_EraseRootFromParent_Done,
1161 /* 1531 */ // Label 107: @1531
1162 /* 1531 */ GIM_Try, /*On fail goto*//*Label 108*/ GIMT_Encode4(1606), // Rule ID 2162 //
1163 /* 1536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
1164 /* 1539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1165 /* 1543 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1166 /* 1547 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1167 /* 1551 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1168 /* 1555 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1169 /* 1559 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1170 /* 1563 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1171 /* 1568 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1172 /* 1579 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1173 /* 1581 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (UXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1174 /* 1581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAH),
1175 /* 1584 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1176 /* 1586 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1177 /* 1588 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1178 /* 1592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1179 /* 1595 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1180 /* 1598 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1181 /* 1604 */ GIR_RootConstrainSelectedInstOperands,
1182 /* 1605 */ // GIR_Coverage, 2162,
1183 /* 1605 */ GIR_EraseRootFromParent_Done,
1184 /* 1606 */ // Label 108: @1606
1185 /* 1606 */ GIM_Try, /*On fail goto*//*Label 109*/ GIMT_Encode4(1681), // Rule ID 2400 //
1186 /* 1611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1187 /* 1614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1188 /* 1618 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1189 /* 1622 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1190 /* 1626 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1191 /* 1630 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1192 /* 1634 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1193 /* 1638 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1194 /* 1643 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
1195 /* 1654 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1196 /* 1656 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] })) => (t2UXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1197 /* 1656 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB),
1198 /* 1659 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1199 /* 1661 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1200 /* 1663 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1201 /* 1667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1202 /* 1670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1203 /* 1673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1204 /* 1679 */ GIR_RootConstrainSelectedInstOperands,
1205 /* 1680 */ // GIR_Coverage, 2400,
1206 /* 1680 */ GIR_EraseRootFromParent_Done,
1207 /* 1681 */ // Label 109: @1681
1208 /* 1681 */ GIM_Try, /*On fail goto*//*Label 110*/ GIMT_Encode4(1756), // Rule ID 2401 //
1209 /* 1686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1210 /* 1689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1211 /* 1693 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1212 /* 1697 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1213 /* 1701 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
1214 /* 1705 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1215 /* 1709 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1216 /* 1713 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1217 /* 1718 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
1218 /* 1729 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
1219 /* 1731 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] })) => (t2UXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
1220 /* 1731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAH),
1221 /* 1734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1222 /* 1736 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1223 /* 1738 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
1224 /* 1742 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1225 /* 1745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1226 /* 1748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1227 /* 1754 */ GIR_RootConstrainSelectedInstOperands,
1228 /* 1755 */ // GIR_Coverage, 2401,
1229 /* 1755 */ GIR_EraseRootFromParent_Done,
1230 /* 1756 */ // Label 110: @1756
1231 /* 1756 */ GIM_Try, /*On fail goto*//*Label 111*/ GIMT_Encode4(1884), // Rule ID 6225 //
1232 /* 1761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1233 /* 1764 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1234 /* 1768 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1235 /* 1772 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1236 /* 1776 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1237 /* 1780 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1238 /* 1784 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1239 /* 1788 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1240 /* 1792 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1241 /* 1796 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1242 /* 1800 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
1243 /* 1804 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1244 /* 1808 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1245 /* 1812 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1246 /* 1817 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
1247 /* 1821 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1248 /* 1825 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
1249 /* 1829 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1250 /* 1833 */ // MIs[4] Rm
1251 /* 1833 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1252 /* 1838 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
1253 /* 1842 */ // MIs[1] Operand 2
1254 /* 1842 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1255 /* 1853 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1256 /* 1857 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1257 /* 1859 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1258 /* 1859 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1259 /* 1862 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1260 /* 1864 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1261 /* 1866 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1262 /* 1870 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1263 /* 1873 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1264 /* 1876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1265 /* 1882 */ GIR_RootConstrainSelectedInstOperands,
1266 /* 1883 */ // GIR_Coverage, 6225,
1267 /* 1883 */ GIR_EraseRootFromParent_Done,
1268 /* 1884 */ // Label 111: @1884
1269 /* 1884 */ GIM_Try, /*On fail goto*//*Label 112*/ GIMT_Encode4(2012), // Rule ID 6226 //
1270 /* 1889 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1271 /* 1892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1272 /* 1896 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1273 /* 1900 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1274 /* 1904 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1275 /* 1908 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1276 /* 1912 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1277 /* 1916 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1278 /* 1920 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1279 /* 1924 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1280 /* 1928 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
1281 /* 1932 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1282 /* 1936 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1283 /* 1940 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1284 /* 1945 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8,
1285 /* 1949 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1286 /* 1953 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
1287 /* 1957 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1288 /* 1961 */ // MIs[4] Rm
1289 /* 1961 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1290 /* 1966 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
1291 /* 1970 */ // MIs[1] Operand 2
1292 /* 1970 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1293 /* 1981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1294 /* 1985 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1295 /* 1987 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1296 /* 1987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1297 /* 1990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1298 /* 1992 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1299 /* 1994 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1300 /* 1998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1301 /* 2001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1302 /* 2004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1303 /* 2010 */ GIR_RootConstrainSelectedInstOperands,
1304 /* 2011 */ // GIR_Coverage, 6226,
1305 /* 2011 */ GIR_EraseRootFromParent_Done,
1306 /* 2012 */ // Label 112: @2012
1307 /* 2012 */ GIM_Try, /*On fail goto*//*Label 113*/ GIMT_Encode4(2140), // Rule ID 2267 //
1308 /* 2017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1309 /* 2020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1310 /* 2024 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1311 /* 2028 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1312 /* 2032 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1313 /* 2036 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1314 /* 2040 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1315 /* 2044 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1316 /* 2048 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1317 /* 2052 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1318 /* 2056 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1319 /* 2060 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
1320 /* 2064 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1321 /* 2068 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1322 /* 2072 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1323 /* 2077 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 24,
1324 /* 2081 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1325 /* 2085 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
1326 /* 2089 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1327 /* 2093 */ // MIs[4] Rm
1328 /* 2093 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1329 /* 2098 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
1330 /* 2102 */ // MIs[1] Operand 2
1331 /* 2102 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1332 /* 2113 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1333 /* 2115 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1334 /* 2115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1335 /* 2118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1336 /* 2120 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1337 /* 2122 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1338 /* 2126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1339 /* 2129 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1340 /* 2132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1341 /* 2138 */ GIR_RootConstrainSelectedInstOperands,
1342 /* 2139 */ // GIR_Coverage, 2267,
1343 /* 2139 */ GIR_EraseRootFromParent_Done,
1344 /* 2140 */ // Label 113: @2140
1345 /* 2140 */ GIM_Try, /*On fail goto*//*Label 114*/ GIMT_Encode4(2268), // Rule ID 6224 //
1346 /* 2145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1347 /* 2148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1348 /* 2152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1349 /* 2156 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1350 /* 2160 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1351 /* 2164 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1352 /* 2168 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1353 /* 2172 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR),
1354 /* 2176 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1355 /* 2180 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1356 /* 2184 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
1357 /* 2188 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
1358 /* 2192 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1359 /* 2196 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1360 /* 2200 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1361 /* 2205 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 8,
1362 /* 2209 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/2, /*OpIdx*/2, // MIs[4]
1363 /* 2213 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
1364 /* 2217 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
1365 /* 2221 */ // MIs[4] Rm
1366 /* 2221 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/3, /*OtherOpIdx*/1,
1367 /* 2226 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
1368 /* 2230 */ // MIs[1] Operand 2
1369 /* 2230 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1370 /* 2241 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
1371 /* 2243 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] })), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1372 /* 2243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1373 /* 2246 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1374 /* 2248 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1375 /* 2250 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1376 /* 2254 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1377 /* 2257 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1378 /* 2260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1379 /* 2266 */ GIR_RootConstrainSelectedInstOperands,
1380 /* 2267 */ // GIR_Coverage, 6224,
1381 /* 2267 */ GIR_EraseRootFromParent_Done,
1382 /* 2268 */ // Label 114: @2268
1383 /* 2268 */ GIM_Try, /*On fail goto*//*Label 115*/ GIMT_Encode4(2378), // Rule ID 5927 //
1384 /* 2273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1385 /* 2276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1386 /* 2280 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1387 /* 2284 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1388 /* 2288 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1389 /* 2292 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1390 /* 2296 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1391 /* 2300 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1392 /* 2304 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1393 /* 2308 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1394 /* 2312 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1395 /* 2317 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1396 /* 2321 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1397 /* 2325 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1398 /* 2329 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1399 /* 2333 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1400 /* 2337 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1401 /* 2342 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1402 /* 2346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1403 /* 2350 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1404 /* 2352 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1405 /* 2352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT),
1406 /* 2355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1407 /* 2357 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1408 /* 2361 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1409 /* 2365 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1410 /* 2367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1411 /* 2370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1412 /* 2376 */ GIR_RootConstrainSelectedInstOperands,
1413 /* 2377 */ // GIR_Coverage, 5927,
1414 /* 2377 */ GIR_EraseRootFromParent_Done,
1415 /* 2378 */ // Label 115: @2378
1416 /* 2378 */ GIM_Try, /*On fail goto*//*Label 116*/ GIMT_Encode4(2488), // Rule ID 5964 //
1417 /* 2383 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1418 /* 2386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1419 /* 2390 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1420 /* 2394 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1421 /* 2398 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1422 /* 2402 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1423 /* 2406 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1424 /* 2410 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1425 /* 2414 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1426 /* 2418 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1427 /* 2422 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1428 /* 2427 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1429 /* 2431 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1430 /* 2435 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1431 /* 2439 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1432 /* 2443 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1433 /* 2447 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1434 /* 2452 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1435 /* 2456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1436 /* 2460 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1437 /* 2462 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1438 /* 2462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT),
1439 /* 2465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1440 /* 2467 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1441 /* 2471 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1442 /* 2475 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1443 /* 2477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1444 /* 2480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1445 /* 2486 */ GIR_RootConstrainSelectedInstOperands,
1446 /* 2487 */ // GIR_Coverage, 5964,
1447 /* 2487 */ GIR_EraseRootFromParent_Done,
1448 /* 2488 */ // Label 116: @2488
1449 /* 2488 */ GIM_Try, /*On fail goto*//*Label 117*/ GIMT_Encode4(2598), // Rule ID 191 //
1450 /* 2493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1451 /* 2496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1452 /* 2500 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1453 /* 2504 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1454 /* 2508 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1455 /* 2512 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1456 /* 2516 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1457 /* 2520 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1458 /* 2524 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1459 /* 2528 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1460 /* 2532 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1461 /* 2536 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1462 /* 2541 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1463 /* 2545 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1464 /* 2549 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1465 /* 2553 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1466 /* 2557 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1467 /* 2561 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1468 /* 2566 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1469 /* 2570 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1470 /* 2572 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLATT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1471 /* 2572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT),
1472 /* 2575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1473 /* 2577 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1474 /* 2581 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1475 /* 2585 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1476 /* 2587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1477 /* 2590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1478 /* 2596 */ GIR_RootConstrainSelectedInstOperands,
1479 /* 2597 */ // GIR_Coverage, 191,
1480 /* 2597 */ GIR_EraseRootFromParent_Done,
1481 /* 2598 */ // Label 117: @2598
1482 /* 2598 */ GIM_Try, /*On fail goto*//*Label 118*/ GIMT_Encode4(2708), // Rule ID 520 //
1483 /* 2603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1484 /* 2606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1485 /* 2610 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1486 /* 2614 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1487 /* 2618 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1488 /* 2622 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1489 /* 2626 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1490 /* 2630 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1491 /* 2634 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1492 /* 2638 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1493 /* 2642 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1494 /* 2646 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1495 /* 2651 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1496 /* 2655 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1497 /* 2659 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1498 /* 2663 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1499 /* 2667 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1500 /* 2671 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1501 /* 2676 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1502 /* 2680 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1503 /* 2682 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLATT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1504 /* 2682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT),
1505 /* 2685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1506 /* 2687 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1507 /* 2691 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1508 /* 2695 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1509 /* 2697 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1510 /* 2700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1511 /* 2706 */ GIR_RootConstrainSelectedInstOperands,
1512 /* 2707 */ // GIR_Coverage, 520,
1513 /* 2707 */ GIR_EraseRootFromParent_Done,
1514 /* 2708 */ // Label 118: @2708
1515 /* 2708 */ GIM_Try, /*On fail goto*//*Label 119*/ GIMT_Encode4(2821), // Rule ID 5926 //
1516 /* 2713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1517 /* 2716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1518 /* 2720 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1519 /* 2724 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1520 /* 2728 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1521 /* 2732 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1522 /* 2736 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1523 /* 2740 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1524 /* 2744 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1525 /* 2748 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1526 /* 2752 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1527 /* 2757 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1528 /* 2761 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1529 /* 2765 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1530 /* 2769 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1531 /* 2773 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1532 /* 2778 */ // MIs[3] Operand 2
1533 /* 2778 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1534 /* 2789 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1535 /* 2793 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1536 /* 2795 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1537 /* 2795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
1538 /* 2798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1539 /* 2800 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
1540 /* 2804 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1541 /* 2808 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1542 /* 2810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1543 /* 2813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1544 /* 2819 */ GIR_RootConstrainSelectedInstOperands,
1545 /* 2820 */ // GIR_Coverage, 5926,
1546 /* 2820 */ GIR_EraseRootFromParent_Done,
1547 /* 2821 */ // Label 119: @2821
1548 /* 2821 */ GIM_Try, /*On fail goto*//*Label 120*/ GIMT_Encode4(2934), // Rule ID 5963 //
1549 /* 2826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1550 /* 2829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1551 /* 2833 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1552 /* 2837 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1553 /* 2841 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1554 /* 2845 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1555 /* 2849 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1556 /* 2853 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1557 /* 2857 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1558 /* 2861 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1559 /* 2865 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1560 /* 2870 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1561 /* 2874 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1562 /* 2878 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1563 /* 2882 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1564 /* 2886 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1565 /* 2891 */ // MIs[3] Operand 2
1566 /* 2891 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1567 /* 2902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1568 /* 2906 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1569 /* 2908 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1570 /* 2908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
1571 /* 2911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1572 /* 2913 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
1573 /* 2917 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1574 /* 2921 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1575 /* 2923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1576 /* 2926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1577 /* 2932 */ GIR_RootConstrainSelectedInstOperands,
1578 /* 2933 */ // GIR_Coverage, 5963,
1579 /* 2933 */ GIR_EraseRootFromParent_Done,
1580 /* 2934 */ // Label 120: @2934
1581 /* 2934 */ GIM_Try, /*On fail goto*//*Label 121*/ GIMT_Encode4(3047), // Rule ID 5925 //
1582 /* 2939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1583 /* 2942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1584 /* 2946 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1585 /* 2950 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1586 /* 2954 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1587 /* 2958 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1588 /* 2962 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1589 /* 2966 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1590 /* 2970 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1591 /* 2974 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1592 /* 2979 */ // MIs[2] Operand 2
1593 /* 2979 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1594 /* 2990 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1595 /* 2994 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1596 /* 2998 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1597 /* 3002 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1598 /* 3006 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1599 /* 3011 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1600 /* 3015 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1601 /* 3019 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1602 /* 3021 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] })), GPR:{ *:[i32] }:$Ra) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1603 /* 3021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
1604 /* 3024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1605 /* 3026 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1606 /* 3030 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1607 /* 3034 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1608 /* 3036 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1609 /* 3039 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1610 /* 3045 */ GIR_RootConstrainSelectedInstOperands,
1611 /* 3046 */ // GIR_Coverage, 5925,
1612 /* 3046 */ GIR_EraseRootFromParent_Done,
1613 /* 3047 */ // Label 121: @3047
1614 /* 3047 */ GIM_Try, /*On fail goto*//*Label 122*/ GIMT_Encode4(3160), // Rule ID 5962 //
1615 /* 3052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1616 /* 3055 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1617 /* 3059 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1618 /* 3063 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1619 /* 3067 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1620 /* 3071 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1621 /* 3075 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1622 /* 3079 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1623 /* 3083 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1624 /* 3087 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1625 /* 3092 */ // MIs[2] Operand 2
1626 /* 3092 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1627 /* 3103 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1628 /* 3107 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1629 /* 3111 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1630 /* 3115 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1631 /* 3119 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1632 /* 3124 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1633 /* 3128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1634 /* 3132 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1635 /* 3134 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1636 /* 3134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
1637 /* 3137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1638 /* 3139 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1639 /* 3143 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1640 /* 3147 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1641 /* 3149 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1642 /* 3152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1643 /* 3158 */ GIR_RootConstrainSelectedInstOperands,
1644 /* 3159 */ // GIR_Coverage, 5962,
1645 /* 3159 */ GIR_EraseRootFromParent_Done,
1646 /* 3160 */ // Label 122: @3160
1647 /* 3160 */ GIM_Try, /*On fail goto*//*Label 123*/ GIMT_Encode4(3273), // Rule ID 190 //
1648 /* 3165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1649 /* 3168 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1650 /* 3172 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1651 /* 3176 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1652 /* 3180 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1653 /* 3184 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1654 /* 3188 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1655 /* 3192 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1656 /* 3196 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1657 /* 3200 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1658 /* 3204 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1659 /* 3208 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1660 /* 3213 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1661 /* 3217 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1662 /* 3221 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1663 /* 3225 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1664 /* 3229 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1665 /* 3234 */ // MIs[3] Operand 2
1666 /* 3234 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1667 /* 3245 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1668 /* 3247 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLATB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1669 /* 3247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB),
1670 /* 3250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1671 /* 3252 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1672 /* 3256 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1673 /* 3260 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1674 /* 3262 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1675 /* 3265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1676 /* 3271 */ GIR_RootConstrainSelectedInstOperands,
1677 /* 3272 */ // GIR_Coverage, 190,
1678 /* 3272 */ GIR_EraseRootFromParent_Done,
1679 /* 3273 */ // Label 123: @3273
1680 /* 3273 */ GIM_Try, /*On fail goto*//*Label 124*/ GIMT_Encode4(3386), // Rule ID 519 //
1681 /* 3278 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1682 /* 3281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1683 /* 3285 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1684 /* 3289 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1685 /* 3293 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1686 /* 3297 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1687 /* 3301 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1688 /* 3305 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1689 /* 3309 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
1690 /* 3313 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1691 /* 3317 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1692 /* 3321 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1693 /* 3326 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
1694 /* 3330 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1695 /* 3334 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1696 /* 3338 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1697 /* 3342 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1698 /* 3347 */ // MIs[3] Operand 2
1699 /* 3347 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1700 /* 3358 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1701 /* 3360 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLATB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1702 /* 3360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB),
1703 /* 3363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1704 /* 3365 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1705 /* 3369 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1706 /* 3373 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1707 /* 3375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1708 /* 3378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1709 /* 3384 */ GIR_RootConstrainSelectedInstOperands,
1710 /* 3385 */ // GIR_Coverage, 519,
1711 /* 3385 */ GIR_EraseRootFromParent_Done,
1712 /* 3386 */ // Label 124: @3386
1713 /* 3386 */ GIM_Try, /*On fail goto*//*Label 125*/ GIMT_Encode4(3499), // Rule ID 189 //
1714 /* 3391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1715 /* 3394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1716 /* 3398 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1717 /* 3402 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1718 /* 3406 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1719 /* 3410 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1720 /* 3414 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1721 /* 3418 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1722 /* 3422 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1723 /* 3426 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1724 /* 3430 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1725 /* 3435 */ // MIs[2] Operand 2
1726 /* 3435 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1727 /* 3446 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1728 /* 3450 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1729 /* 3454 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1730 /* 3458 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1731 /* 3462 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1732 /* 3467 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1733 /* 3471 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1734 /* 3473 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (SMLABT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1735 /* 3473 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
1736 /* 3476 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1737 /* 3478 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1738 /* 3482 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1739 /* 3486 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1740 /* 3488 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1741 /* 3491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1742 /* 3497 */ GIR_RootConstrainSelectedInstOperands,
1743 /* 3498 */ // GIR_Coverage, 189,
1744 /* 3498 */ GIR_EraseRootFromParent_Done,
1745 /* 3499 */ // Label 125: @3499
1746 /* 3499 */ GIM_Try, /*On fail goto*//*Label 126*/ GIMT_Encode4(3612), // Rule ID 518 //
1747 /* 3504 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1748 /* 3507 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1749 /* 3511 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1750 /* 3515 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1751 /* 3519 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1752 /* 3523 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1753 /* 3527 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1754 /* 3531 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1755 /* 3535 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1756 /* 3539 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1757 /* 3543 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1758 /* 3548 */ // MIs[2] Operand 2
1759 /* 3548 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1760 /* 3559 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1761 /* 3563 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
1762 /* 3567 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1763 /* 3571 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
1764 /* 3575 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1765 /* 3580 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
1766 /* 3584 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1767 /* 3586 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] }))) => (t2SMLABT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1768 /* 3586 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
1769 /* 3589 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1770 /* 3591 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1771 /* 3595 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1772 /* 3599 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1773 /* 3601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1774 /* 3604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1775 /* 3610 */ GIR_RootConstrainSelectedInstOperands,
1776 /* 3611 */ // GIR_Coverage, 518,
1777 /* 3611 */ GIR_EraseRootFromParent_Done,
1778 /* 3612 */ // Label 126: @3612
1779 /* 3612 */ GIM_Try, /*On fail goto*//*Label 127*/ GIMT_Encode4(3703), // Rule ID 6223 //
1780 /* 3617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1781 /* 3620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1782 /* 3624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1783 /* 3628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1784 /* 3632 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1785 /* 3636 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1786 /* 3640 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR),
1787 /* 3644 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1788 /* 3648 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1789 /* 3652 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1790 /* 3657 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
1791 /* 3661 */ // MIs[1] Operand 2
1792 /* 3661 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1793 /* 3672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1794 /* 3676 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
1795 /* 3678 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1796 /* 3678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1797 /* 3681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1798 /* 3683 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
1799 /* 3685 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1800 /* 3689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1801 /* 3692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1802 /* 3695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1803 /* 3701 */ GIR_RootConstrainSelectedInstOperands,
1804 /* 3702 */ // GIR_Coverage, 6223,
1805 /* 3702 */ GIR_EraseRootFromParent_Done,
1806 /* 3703 */ // Label 127: @3703
1807 /* 3703 */ GIM_Try, /*On fail goto*//*Label 128*/ GIMT_Encode4(3794), // Rule ID 2266 //
1808 /* 3708 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
1809 /* 3711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1810 /* 3715 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1811 /* 3719 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1812 /* 3723 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1813 /* 3727 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1814 /* 3731 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1815 /* 3735 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ROTR),
1816 /* 3739 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1817 /* 3743 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
1818 /* 3747 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1819 /* 3752 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
1820 /* 3756 */ // MIs[1] Operand 2
1821 /* 3756 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
1822 /* 3767 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
1823 /* 3769 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 3:{ *:[i32] })
1824 /* 3769 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
1825 /* 3772 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1826 /* 3774 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
1827 /* 3776 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
1828 /* 3780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/3,
1829 /* 3783 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1830 /* 3786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1831 /* 3792 */ GIR_RootConstrainSelectedInstOperands,
1832 /* 3793 */ // GIR_Coverage, 2266,
1833 /* 3793 */ GIR_EraseRootFromParent_Done,
1834 /* 3794 */ // Label 128: @3794
1835 /* 3794 */ GIM_Try, /*On fail goto*//*Label 129*/ GIMT_Encode4(3910), // Rule ID 5924 //
1836 /* 3799 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1837 /* 3802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1838 /* 3806 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1839 /* 3810 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1840 /* 3814 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1841 /* 3818 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1842 /* 3822 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1843 /* 3826 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1844 /* 3830 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1845 /* 3834 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1846 /* 3839 */ // MIs[2] Operand 2
1847 /* 3839 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1848 /* 3850 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1849 /* 3854 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1850 /* 3858 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1851 /* 3862 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1852 /* 3867 */ // MIs[3] Operand 2
1853 /* 3867 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1854 /* 3878 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1855 /* 3882 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1856 /* 3884 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })), GPR:{ *:[i32] }:$Ra) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1857 /* 3884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB),
1858 /* 3887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1859 /* 3889 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1860 /* 3893 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1861 /* 3897 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1862 /* 3899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1863 /* 3902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1864 /* 3908 */ GIR_RootConstrainSelectedInstOperands,
1865 /* 3909 */ // GIR_Coverage, 5924,
1866 /* 3909 */ GIR_EraseRootFromParent_Done,
1867 /* 3910 */ // Label 129: @3910
1868 /* 3910 */ GIM_Try, /*On fail goto*//*Label 130*/ GIMT_Encode4(4026), // Rule ID 5961 //
1869 /* 3915 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1870 /* 3918 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1871 /* 3922 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1872 /* 3926 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1873 /* 3930 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1874 /* 3934 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1875 /* 3938 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1876 /* 3942 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1877 /* 3946 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1878 /* 3950 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1879 /* 3955 */ // MIs[2] Operand 2
1880 /* 3955 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1881 /* 3966 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1882 /* 3970 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1883 /* 3974 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1884 /* 3978 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1885 /* 3983 */ // MIs[3] Operand 2
1886 /* 3983 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1887 /* 3994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1888 /* 3998 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1889 /* 4000 */ // (add:{ *:[i32] } (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })), rGPR:{ *:[i32] }:$Ra) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1890 /* 4000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB),
1891 /* 4003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1892 /* 4005 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1893 /* 4009 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1894 /* 4013 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
1895 /* 4015 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1896 /* 4018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1897 /* 4024 */ GIR_RootConstrainSelectedInstOperands,
1898 /* 4025 */ // GIR_Coverage, 5961,
1899 /* 4025 */ GIR_EraseRootFromParent_Done,
1900 /* 4026 */ // Label 130: @4026
1901 /* 4026 */ GIM_Try, /*On fail goto*//*Label 131*/ GIMT_Encode4(4142), // Rule ID 188 //
1902 /* 4031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM_UseMulOps),
1903 /* 4034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1904 /* 4038 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
1905 /* 4042 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1906 /* 4046 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1907 /* 4050 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1908 /* 4054 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1909 /* 4058 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1910 /* 4062 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1911 /* 4066 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1912 /* 4070 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1913 /* 4075 */ // MIs[2] Operand 2
1914 /* 4075 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1915 /* 4086 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1916 /* 4090 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1917 /* 4094 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1918 /* 4098 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
1919 /* 4103 */ // MIs[3] Operand 2
1920 /* 4103 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1921 /* 4114 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1922 /* 4116 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (SMLABB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
1923 /* 4116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB),
1924 /* 4119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1925 /* 4121 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1926 /* 4125 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1927 /* 4129 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1928 /* 4131 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1929 /* 4134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1930 /* 4140 */ GIR_RootConstrainSelectedInstOperands,
1931 /* 4141 */ // GIR_Coverage, 188,
1932 /* 4141 */ GIR_EraseRootFromParent_Done,
1933 /* 4142 */ // Label 131: @4142
1934 /* 4142 */ GIM_Try, /*On fail goto*//*Label 132*/ GIMT_Encode4(4258), // Rule ID 517 //
1935 /* 4147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
1936 /* 4150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1937 /* 4154 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1938 /* 4158 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1939 /* 4162 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
1940 /* 4166 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
1941 /* 4170 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
1942 /* 4174 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1943 /* 4178 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1944 /* 4182 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
1945 /* 4186 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1946 /* 4191 */ // MIs[2] Operand 2
1947 /* 4191 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
1948 /* 4202 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
1949 /* 4206 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
1950 /* 4210 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
1951 /* 4214 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
1952 /* 4219 */ // MIs[3] Operand 2
1953 /* 4219 */ GIM_CheckLiteralInt, /*MI*/3, /*Op*/2, GIMT_Encode8(16),
1954 /* 4230 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
1955 /* 4232 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }))) => (t2SMLABB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
1956 /* 4232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB),
1957 /* 4235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
1958 /* 4237 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
1959 /* 4241 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
1960 /* 4245 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
1961 /* 4247 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
1962 /* 4250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1963 /* 4256 */ GIR_RootConstrainSelectedInstOperands,
1964 /* 4257 */ // GIR_Coverage, 517,
1965 /* 4257 */ GIR_EraseRootFromParent_Done,
1966 /* 4258 */ // Label 132: @4258
1967 /* 4258 */ GIM_Try, /*On fail goto*//*Label 133*/ GIMT_Encode4(4346), // Rule ID 3600 //
1968 /* 4263 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
1969 /* 4266 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
1970 /* 4270 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1971 /* 4274 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
1972 /* 4278 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
1973 /* 4282 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
1974 /* 4286 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
1975 /* 4290 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
1976 /* 4294 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
1977 /* 4298 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
1978 /* 4303 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
1979 /* 4308 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
1980 /* 4312 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
1981 /* 4314 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
1982 /* 4314 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32),
1983 /* 4317 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
1984 /* 4319 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3
1985 /* 4321 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
1986 /* 4325 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
1987 /* 4329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
1988 /* 4332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1989 /* 4338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
1990 /* 4344 */ GIR_RootConstrainSelectedInstOperands,
1991 /* 4345 */ // GIR_Coverage, 3600,
1992 /* 4345 */ GIR_EraseRootFromParent_Done,
1993 /* 4346 */ // Label 133: @4346
1994 /* 4346 */ GIM_Try, /*On fail goto*//*Label 134*/ GIMT_Encode4(4434), // Rule ID 3601 //
1995 /* 4351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
1996 /* 4354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
1997 /* 4358 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
1998 /* 4362 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
1999 /* 4366 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2000 /* 4370 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2001 /* 4374 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2002 /* 4378 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
2003 /* 4382 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
2004 /* 4386 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2005 /* 4391 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2006 /* 4396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2007 /* 4400 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2008 /* 4402 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
2009 /* 4402 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16),
2010 /* 4405 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2011 /* 4407 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3
2012 /* 4409 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2013 /* 4413 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2014 /* 4417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2015 /* 4420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2016 /* 4426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2017 /* 4432 */ GIR_RootConstrainSelectedInstOperands,
2018 /* 4433 */ // GIR_Coverage, 3601,
2019 /* 4433 */ GIR_EraseRootFromParent_Done,
2020 /* 4434 */ // Label 134: @4434
2021 /* 4434 */ GIM_Try, /*On fail goto*//*Label 135*/ GIMT_Encode4(4522), // Rule ID 3604 //
2022 /* 4439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2023 /* 4442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2024 /* 4446 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2025 /* 4450 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2026 /* 4454 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2027 /* 4458 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2028 /* 4462 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2029 /* 4466 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
2030 /* 4470 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
2031 /* 4474 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2032 /* 4479 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2033 /* 4484 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2034 /* 4488 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2035 /* 4490 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)), tGPREven:{ *:[i32] }:$src3) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
2036 /* 4490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8),
2037 /* 4493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2038 /* 4495 */ GIR_RootToRootCopy, /*OpIdx*/2, // src3
2039 /* 4497 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2040 /* 4501 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2041 /* 4505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2042 /* 4508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2043 /* 4514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2044 /* 4520 */ GIR_RootConstrainSelectedInstOperands,
2045 /* 4521 */ // GIR_Coverage, 3604,
2046 /* 4521 */ GIR_EraseRootFromParent_Done,
2047 /* 4522 */ // Label 135: @4522
2048 /* 4522 */ GIM_Try, /*On fail goto*//*Label 136*/ GIMT_Encode4(4610), // Rule ID 6521 //
2049 /* 4527 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2050 /* 4530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2051 /* 4534 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2052 /* 4538 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2053 /* 4542 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2054 /* 4546 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2055 /* 4550 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2056 /* 4554 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2057 /* 4558 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
2058 /* 4562 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s32,
2059 /* 4566 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2060 /* 4571 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2061 /* 4576 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2062 /* 4578 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2))) => (MVE_VMLADAVau32:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
2063 /* 4578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32),
2064 /* 4581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2065 /* 4583 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3
2066 /* 4585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2067 /* 4589 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2068 /* 4593 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2069 /* 4596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2070 /* 4602 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2071 /* 4608 */ GIR_RootConstrainSelectedInstOperands,
2072 /* 4609 */ // GIR_Coverage, 6521,
2073 /* 4609 */ GIR_EraseRootFromParent_Done,
2074 /* 4610 */ // Label 136: @4610
2075 /* 4610 */ GIM_Try, /*On fail goto*//*Label 137*/ GIMT_Encode4(4698), // Rule ID 6522 //
2076 /* 4615 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2077 /* 4618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2078 /* 4622 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2079 /* 4626 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2080 /* 4630 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2081 /* 4634 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2082 /* 4638 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2083 /* 4642 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2084 /* 4646 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
2085 /* 4650 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s16,
2086 /* 4654 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2087 /* 4659 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2088 /* 4664 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2089 /* 4666 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2))) => (MVE_VMLADAVau16:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
2090 /* 4666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16),
2091 /* 4669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2092 /* 4671 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3
2093 /* 4673 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2094 /* 4677 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2095 /* 4681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2096 /* 4684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2097 /* 4690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2098 /* 4696 */ GIR_RootConstrainSelectedInstOperands,
2099 /* 4697 */ // GIR_Coverage, 6522,
2100 /* 4697 */ GIR_EraseRootFromParent_Done,
2101 /* 4698 */ // Label 137: @4698
2102 /* 4698 */ GIM_Try, /*On fail goto*//*Label 138*/ GIMT_Encode4(4786), // Rule ID 6525 //
2103 /* 4703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2104 /* 4706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2105 /* 4710 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2106 /* 4714 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2107 /* 4718 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2108 /* 4722 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2109 /* 4726 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
2110 /* 4730 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL),
2111 /* 4734 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v16s8,
2112 /* 4738 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v16s8,
2113 /* 4742 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2114 /* 4747 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2115 /* 4752 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
2116 /* 4754 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$src3, (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2))) => (MVE_VMLADAVau8:{ *:[i32] } ?:{ *:[i32] }:$src3, ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
2117 /* 4754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8),
2118 /* 4757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
2119 /* 4759 */ GIR_RootToRootCopy, /*OpIdx*/1, // src3
2120 /* 4761 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
2121 /* 4765 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2
2122 /* 4769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2123 /* 4772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2124 /* 4778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2125 /* 4784 */ GIR_RootConstrainSelectedInstOperands,
2126 /* 4785 */ // GIR_Coverage, 6525,
2127 /* 4785 */ GIR_EraseRootFromParent_Done,
2128 /* 4786 */ // Label 138: @4786
2129 /* 4786 */ GIM_Try, /*On fail goto*//*Label 139*/ GIMT_Encode4(4843), // Rule ID 71 //
2130 /* 4791 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
2131 /* 4794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2132 /* 4798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2133 /* 4802 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2134 /* 4806 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2135 /* 4810 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
2136 /* 4814 */ // MIs[1] Operand 1
2137 /* 4814 */ // No operand predicates
2138 /* 4814 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2139 /* 4816 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ADDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
2140 /* 4816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDri),
2141 /* 4819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2142 /* 4821 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2143 /* 4823 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2144 /* 4826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2145 /* 4829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2146 /* 4835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2147 /* 4841 */ GIR_RootConstrainSelectedInstOperands,
2148 /* 4842 */ // GIR_Coverage, 71,
2149 /* 4842 */ GIR_EraseRootFromParent_Done,
2150 /* 4843 */ // Label 139: @4843
2151 /* 4843 */ GIM_Try, /*On fail goto*//*Label 140*/ GIMT_Encode4(4900), // Rule ID 302 //
2152 /* 4848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
2153 /* 4851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2154 /* 4855 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2155 /* 4859 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2156 /* 4863 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2157 /* 4867 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
2158 /* 4871 */ // MIs[1] Operand 1
2159 /* 4871 */ // No operand predicates
2160 /* 4871 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2161 /* 4873 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm3) => (tADDi3:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm3)
2162 /* 4873 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi3),
2163 /* 4876 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2164 /* 4878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
2165 /* 4884 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
2166 /* 4886 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm3
2167 /* 4889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2168 /* 4892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2169 /* 4898 */ GIR_RootConstrainSelectedInstOperands,
2170 /* 4899 */ // GIR_Coverage, 302,
2171 /* 4899 */ GIR_EraseRootFromParent_Done,
2172 /* 4900 */ // Label 140: @4900
2173 /* 4900 */ GIM_Try, /*On fail goto*//*Label 141*/ GIMT_Encode4(4957), // Rule ID 303 //
2174 /* 4905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
2175 /* 4908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2176 /* 4912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2177 /* 4916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2178 /* 4920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2179 /* 4924 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr),
2180 /* 4928 */ // MIs[1] Operand 1
2181 /* 4928 */ // No operand predicates
2182 /* 4928 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2183 /* 4930 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8) => (tADDi8:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm8)
2184 /* 4930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDi8),
2185 /* 4933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
2186 /* 4935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
2187 /* 4941 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2188 /* 4943 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8
2189 /* 4946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2190 /* 4949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2191 /* 4955 */ GIR_RootConstrainSelectedInstOperands,
2192 /* 4956 */ // GIR_Coverage, 303,
2193 /* 4956 */ GIR_EraseRootFromParent_Done,
2194 /* 4957 */ // Label 141: @4957
2195 /* 4957 */ GIM_Try, /*On fail goto*//*Label 142*/ GIMT_Encode4(5014), // Rule ID 406 //
2196 /* 4962 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
2197 /* 4965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2198 /* 4969 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2199 /* 4973 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2200 /* 4977 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2201 /* 4981 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
2202 /* 4985 */ // MIs[1] Operand 1
2203 /* 4985 */ // No operand predicates
2204 /* 4985 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2205 /* 4987 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ADDri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
2206 /* 4987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri),
2207 /* 4990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2208 /* 4992 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2209 /* 4994 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2210 /* 4997 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2211 /* 5000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2212 /* 5006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2213 /* 5012 */ GIR_RootConstrainSelectedInstOperands,
2214 /* 5013 */ // GIR_Coverage, 406,
2215 /* 5013 */ GIR_EraseRootFromParent_Done,
2216 /* 5014 */ // Label 142: @5014
2217 /* 5014 */ GIM_Try, /*On fail goto*//*Label 143*/ GIMT_Encode4(5065), // Rule ID 407 //
2218 /* 5019 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
2219 /* 5022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2220 /* 5026 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2221 /* 5030 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2222 /* 5034 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
2223 /* 5038 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095),
2224 /* 5042 */ // MIs[1] Operand 1
2225 /* 5042 */ // No operand predicates
2226 /* 5042 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2227 /* 5044 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2ADDri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
2228 /* 5044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDri12),
2229 /* 5047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2230 /* 5049 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2231 /* 5051 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
2232 /* 5054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2233 /* 5057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2234 /* 5063 */ GIR_RootConstrainSelectedInstOperands,
2235 /* 5064 */ // GIR_Coverage, 407,
2236 /* 5064 */ GIR_EraseRootFromParent_Done,
2237 /* 5065 */ // Label 143: @5065
2238 /* 5065 */ GIM_Try, /*On fail goto*//*Label 144*/ GIMT_Encode4(5141), // Rule ID 170 //
2239 /* 5070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps),
2240 /* 5073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2241 /* 5077 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2242 /* 5081 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2243 /* 5085 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2244 /* 5089 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2245 /* 5093 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2246 /* 5098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2247 /* 5103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2248 /* 5107 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2249 /* 5109 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2250 /* 5109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA),
2251 /* 5112 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2252 /* 5114 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2253 /* 5118 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2254 /* 5122 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2255 /* 5124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2256 /* 5127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2257 /* 5133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2258 /* 5139 */ GIR_RootConstrainSelectedInstOperands,
2259 /* 5140 */ // GIR_Coverage, 170,
2260 /* 5140 */ GIR_EraseRootFromParent_Done,
2261 /* 5141 */ // Label 144: @5141
2262 /* 5141 */ GIM_Try, /*On fail goto*//*Label 145*/ GIMT_Encode4(5217), // Rule ID 171 //
2263 /* 5146 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6),
2264 /* 5149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2265 /* 5153 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2266 /* 5157 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2267 /* 5161 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2268 /* 5165 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2269 /* 5169 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2270 /* 5174 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2271 /* 5179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2272 /* 5183 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2273 /* 5185 */ // (add:{ *:[i32] } (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm), GPRnopc:{ *:[i32] }:$Ra) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2274 /* 5185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5),
2275 /* 5188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2276 /* 5190 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2277 /* 5194 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2278 /* 5198 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2279 /* 5200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2280 /* 5203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2281 /* 5209 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2282 /* 5215 */ GIR_RootConstrainSelectedInstOperands,
2283 /* 5216 */ // GIR_Coverage, 171,
2284 /* 5216 */ GIR_EraseRootFromParent_Done,
2285 /* 5217 */ // Label 145: @5217
2286 /* 5217 */ GIM_Try, /*On fail goto*//*Label 146*/ GIMT_Encode4(5287), // Rule ID 502 //
2287 /* 5222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps),
2288 /* 5225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2289 /* 5229 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2290 /* 5233 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2291 /* 5237 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2292 /* 5241 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2293 /* 5245 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2294 /* 5250 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2295 /* 5255 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2296 /* 5259 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2297 /* 5261 */ // (add:{ *:[i32] } (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm), rGPR:{ *:[i32] }:$Ra) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2298 /* 5261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA),
2299 /* 5264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2300 /* 5266 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2301 /* 5270 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2302 /* 5274 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2303 /* 5276 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2304 /* 5279 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2305 /* 5285 */ GIR_RootConstrainSelectedInstOperands,
2306 /* 5286 */ // GIR_Coverage, 502,
2307 /* 5286 */ GIR_EraseRootFromParent_Done,
2308 /* 5287 */ // Label 146: @5287
2309 /* 5287 */ GIM_Try, /*On fail goto*//*Label 147*/ GIMT_Encode4(5358), // Rule ID 6216 //
2310 /* 5292 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
2311 /* 5295 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2312 /* 5299 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2313 /* 5303 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2314 /* 5307 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2315 /* 5311 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2316 /* 5316 */ // MIs[1] Operand 2
2317 /* 5316 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2318 /* 5327 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2319 /* 5331 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2320 /* 5333 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2321 /* 5333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB),
2322 /* 5336 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2323 /* 5338 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2324 /* 5340 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2325 /* 5344 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2326 /* 5347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2327 /* 5350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2328 /* 5356 */ GIR_RootConstrainSelectedInstOperands,
2329 /* 5357 */ // GIR_Coverage, 6216,
2330 /* 5357 */ GIR_EraseRootFromParent_Done,
2331 /* 5358 */ // Label 147: @5358
2332 /* 5358 */ GIM_Try, /*On fail goto*//*Label 148*/ GIMT_Encode4(5429), // Rule ID 6217 //
2333 /* 5363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
2334 /* 5366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2335 /* 5370 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2336 /* 5374 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2337 /* 5378 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2338 /* 5382 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2339 /* 5387 */ // MIs[1] Operand 2
2340 /* 5387 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2341 /* 5398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2342 /* 5402 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2343 /* 5404 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] }), GPR:{ *:[i32] }:$Rn) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2344 /* 5404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH),
2345 /* 5407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2346 /* 5409 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2347 /* 5411 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2348 /* 5415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2349 /* 5418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2350 /* 5421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2351 /* 5427 */ GIR_RootConstrainSelectedInstOperands,
2352 /* 5428 */ // GIR_Coverage, 6217,
2353 /* 5428 */ GIR_EraseRootFromParent_Done,
2354 /* 5429 */ // Label 148: @5429
2355 /* 5429 */ GIM_Try, /*On fail goto*//*Label 149*/ GIMT_Encode4(5500), // Rule ID 6251 //
2356 /* 5434 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
2357 /* 5437 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2358 /* 5441 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2359 /* 5445 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2360 /* 5449 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2361 /* 5453 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2362 /* 5458 */ // MIs[1] Operand 2
2363 /* 5458 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2364 /* 5469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2365 /* 5473 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2366 /* 5475 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2367 /* 5475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB),
2368 /* 5478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2369 /* 5480 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2370 /* 5482 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2371 /* 5486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2372 /* 5489 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2373 /* 5492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2374 /* 5498 */ GIR_RootConstrainSelectedInstOperands,
2375 /* 5499 */ // GIR_Coverage, 6251,
2376 /* 5499 */ GIR_EraseRootFromParent_Done,
2377 /* 5500 */ // Label 149: @5500
2378 /* 5500 */ GIM_Try, /*On fail goto*//*Label 150*/ GIMT_Encode4(5571), // Rule ID 6252 //
2379 /* 5505 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
2380 /* 5508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2381 /* 5512 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2382 /* 5516 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2383 /* 5520 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2384 /* 5524 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2385 /* 5529 */ // MIs[1] Operand 2
2386 /* 5529 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2387 /* 5540 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2388 /* 5544 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2389 /* 5546 */ // (add:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }), rGPR:{ *:[i32] }:$Rn) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2390 /* 5546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
2391 /* 5549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2392 /* 5551 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2393 /* 5553 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2394 /* 5557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2395 /* 5560 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2396 /* 5563 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2397 /* 5569 */ GIR_RootConstrainSelectedInstOperands,
2398 /* 5570 */ // GIR_Coverage, 6252,
2399 /* 5570 */ GIR_EraseRootFromParent_Done,
2400 /* 5571 */ // Label 150: @5571
2401 /* 5571 */ GIM_Try, /*On fail goto*//*Label 151*/ GIMT_Encode4(5641), // Rule ID 179 //
2402 /* 5576 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps),
2403 /* 5579 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2404 /* 5583 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2405 /* 5587 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2406 /* 5591 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2407 /* 5595 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2408 /* 5599 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2409 /* 5604 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2410 /* 5609 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2411 /* 5613 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2412 /* 5615 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm), GPR:{ *:[i32] }:$Ra) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
2413 /* 5615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA),
2414 /* 5618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2415 /* 5620 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2416 /* 5624 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2417 /* 5628 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2418 /* 5630 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2419 /* 5633 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2420 /* 5639 */ GIR_RootConstrainSelectedInstOperands,
2421 /* 5640 */ // GIR_Coverage, 179,
2422 /* 5640 */ GIR_EraseRootFromParent_Done,
2423 /* 5641 */ // Label 151: @5641
2424 /* 5641 */ GIM_Try, /*On fail goto*//*Label 152*/ GIMT_Encode4(5711), // Rule ID 508 //
2425 /* 5646 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
2426 /* 5649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2427 /* 5653 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2428 /* 5657 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2429 /* 5661 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2430 /* 5665 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2431 /* 5669 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2432 /* 5674 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2433 /* 5679 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2434 /* 5683 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2435 /* 5685 */ // (add:{ *:[i32] } (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Ra) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2436 /* 5685 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA),
2437 /* 5688 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2438 /* 5690 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2439 /* 5694 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2440 /* 5698 */ GIR_RootToRootCopy, /*OpIdx*/2, // Ra
2441 /* 5700 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2442 /* 5703 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2443 /* 5709 */ GIR_RootConstrainSelectedInstOperands,
2444 /* 5710 */ // GIR_Coverage, 508,
2445 /* 5710 */ GIR_EraseRootFromParent_Done,
2446 /* 5711 */ // Label 152: @5711
2447 /* 5711 */ GIM_Try, /*On fail goto*//*Label 153*/ GIMT_Encode4(5774), // Rule ID 3405 //
2448 /* 5716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2449 /* 5719 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2450 /* 5723 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2451 /* 5727 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2452 /* 5731 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2453 /* 5735 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2454 /* 5740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2455 /* 5744 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2456 /* 5746 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec)
2457 /* 5746 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc),
2458 /* 5749 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2459 /* 5751 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc
2460 /* 5753 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2461 /* 5757 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2462 /* 5760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2463 /* 5766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2464 /* 5772 */ GIR_RootConstrainSelectedInstOperands,
2465 /* 5773 */ // GIR_Coverage, 3405,
2466 /* 5773 */ GIR_EraseRootFromParent_Done,
2467 /* 5774 */ // Label 153: @5774
2468 /* 5774 */ GIM_Try, /*On fail goto*//*Label 154*/ GIMT_Encode4(5837), // Rule ID 3433 //
2469 /* 5779 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2470 /* 5782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2471 /* 5786 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2472 /* 5790 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2473 /* 5794 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2474 /* 5798 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2475 /* 5803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2476 /* 5807 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2477 /* 5809 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec)
2478 /* 5809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc),
2479 /* 5812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2480 /* 5814 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc
2481 /* 5816 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2482 /* 5820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2483 /* 5823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2484 /* 5829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2485 /* 5835 */ GIR_RootConstrainSelectedInstOperands,
2486 /* 5836 */ // GIR_Coverage, 3433,
2487 /* 5836 */ GIR_EraseRootFromParent_Done,
2488 /* 5837 */ // Label 154: @5837
2489 /* 5837 */ GIM_Try, /*On fail goto*//*Label 155*/ GIMT_Encode4(5900), // Rule ID 3443 //
2490 /* 5842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2491 /* 5845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2492 /* 5849 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2493 /* 5853 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2494 /* 5857 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2495 /* 5861 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2496 /* 5866 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2497 /* 5870 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2498 /* 5872 */ // (add:{ *:[i32] } (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec), tGPREven:{ *:[i32] }:$acc) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec)
2499 /* 5872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc),
2500 /* 5875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2501 /* 5877 */ GIR_RootToRootCopy, /*OpIdx*/2, // acc
2502 /* 5879 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2503 /* 5883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2504 /* 5886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2505 /* 5892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2506 /* 5898 */ GIR_RootConstrainSelectedInstOperands,
2507 /* 5899 */ // GIR_Coverage, 3443,
2508 /* 5899 */ GIR_EraseRootFromParent_Done,
2509 /* 5900 */ // Label 155: @5900
2510 /* 5900 */ GIM_Try, /*On fail goto*//*Label 156*/ GIMT_Encode4(5976), // Rule ID 5921 //
2511 /* 5905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps),
2512 /* 5908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2513 /* 5912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2514 /* 5916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2515 /* 5920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2516 /* 5924 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2517 /* 5928 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2518 /* 5932 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2519 /* 5937 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2520 /* 5942 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2521 /* 5944 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2522 /* 5944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLA),
2523 /* 5947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2524 /* 5949 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2525 /* 5953 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2526 /* 5957 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2527 /* 5959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2528 /* 5962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2529 /* 5968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2530 /* 5974 */ GIR_RootConstrainSelectedInstOperands,
2531 /* 5975 */ // GIR_Coverage, 5921,
2532 /* 5975 */ GIR_EraseRootFromParent_Done,
2533 /* 5976 */ // Label 156: @5976
2534 /* 5976 */ GIM_Try, /*On fail goto*//*Label 157*/ GIMT_Encode4(6052), // Rule ID 5922 //
2535 /* 5981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6),
2536 /* 5984 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2537 /* 5988 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2538 /* 5992 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2539 /* 5996 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2540 /* 6000 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2541 /* 6004 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2542 /* 6008 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2543 /* 6013 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2544 /* 6018 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2545 /* 6020 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)) => (MLAv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
2546 /* 6020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLAv5),
2547 /* 6023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2548 /* 6025 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2549 /* 6029 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2550 /* 6033 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2551 /* 6035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2552 /* 6038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2553 /* 6044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2554 /* 6050 */ GIR_RootConstrainSelectedInstOperands,
2555 /* 6051 */ // GIR_Coverage, 5922,
2556 /* 6051 */ GIR_EraseRootFromParent_Done,
2557 /* 6052 */ // Label 157: @6052
2558 /* 6052 */ GIM_Try, /*On fail goto*//*Label 158*/ GIMT_Encode4(6122), // Rule ID 5959 //
2559 /* 6057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps),
2560 /* 6060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2561 /* 6064 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2562 /* 6068 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2563 /* 6072 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2564 /* 6076 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2565 /* 6080 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2566 /* 6084 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2567 /* 6089 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2568 /* 6094 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2569 /* 6096 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2570 /* 6096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLA),
2571 /* 6099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2572 /* 6101 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2573 /* 6105 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2574 /* 6109 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2575 /* 6111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2576 /* 6114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2577 /* 6120 */ GIR_RootConstrainSelectedInstOperands,
2578 /* 6121 */ // GIR_Coverage, 5959,
2579 /* 6121 */ GIR_EraseRootFromParent_Done,
2580 /* 6122 */ // Label 158: @6122
2581 /* 6122 */ GIM_Try, /*On fail goto*//*Label 159*/ GIMT_Encode4(6193), // Rule ID 2165 //
2582 /* 6127 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
2583 /* 6130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2584 /* 6134 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2585 /* 6138 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2586 /* 6142 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2587 /* 6146 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2588 /* 6150 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2589 /* 6155 */ // MIs[1] Operand 2
2590 /* 6155 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2591 /* 6166 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2592 /* 6168 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (SXTAB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2593 /* 6168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB),
2594 /* 6171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2595 /* 6173 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2596 /* 6175 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2597 /* 6179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2598 /* 6182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2599 /* 6185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2600 /* 6191 */ GIR_RootConstrainSelectedInstOperands,
2601 /* 6192 */ // GIR_Coverage, 2165,
2602 /* 6192 */ GIR_EraseRootFromParent_Done,
2603 /* 6193 */ // Label 159: @6193
2604 /* 6193 */ GIM_Try, /*On fail goto*//*Label 160*/ GIMT_Encode4(6264), // Rule ID 2166 //
2605 /* 6198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
2606 /* 6201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2607 /* 6205 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2608 /* 6209 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2609 /* 6213 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2610 /* 6217 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2611 /* 6221 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2612 /* 6226 */ // MIs[1] Operand 2
2613 /* 6226 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2614 /* 6237 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2615 /* 6239 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SXTAH:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2616 /* 6239 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAH),
2617 /* 6242 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2618 /* 6244 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2619 /* 6246 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2620 /* 6250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2621 /* 6253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2622 /* 6256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2623 /* 6262 */ GIR_RootConstrainSelectedInstOperands,
2624 /* 6263 */ // GIR_Coverage, 2166,
2625 /* 6263 */ GIR_EraseRootFromParent_Done,
2626 /* 6264 */ // Label 160: @6264
2627 /* 6264 */ GIM_Try, /*On fail goto*//*Label 161*/ GIMT_Encode4(6335), // Rule ID 2404 //
2628 /* 6269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
2629 /* 6272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2630 /* 6276 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2631 /* 6280 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2632 /* 6284 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2633 /* 6288 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2634 /* 6292 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2635 /* 6297 */ // MIs[1] Operand 2
2636 /* 6297 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
2637 /* 6308 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2638 /* 6310 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] })) => (t2SXTAB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2639 /* 6310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB),
2640 /* 6313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2641 /* 6315 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2642 /* 6317 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2643 /* 6321 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2644 /* 6324 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2645 /* 6327 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2646 /* 6333 */ GIR_RootConstrainSelectedInstOperands,
2647 /* 6334 */ // GIR_Coverage, 2404,
2648 /* 6334 */ GIR_EraseRootFromParent_Done,
2649 /* 6335 */ // Label 161: @6335
2650 /* 6335 */ GIM_Try, /*On fail goto*//*Label 162*/ GIMT_Encode4(6406), // Rule ID 2405 //
2651 /* 6340 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
2652 /* 6343 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2653 /* 6347 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2654 /* 6351 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2655 /* 6355 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
2656 /* 6359 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2657 /* 6363 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2658 /* 6368 */ // MIs[1] Operand 2
2659 /* 6368 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
2660 /* 6379 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2661 /* 6381 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SXTAH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
2662 /* 6381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAH),
2663 /* 6384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2664 /* 6386 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2665 /* 6388 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2666 /* 6392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2667 /* 6395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2668 /* 6398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2669 /* 6404 */ GIR_RootConstrainSelectedInstOperands,
2670 /* 6405 */ // GIR_Coverage, 2405,
2671 /* 6405 */ GIR_EraseRootFromParent_Done,
2672 /* 6406 */ // Label 162: @6406
2673 /* 6406 */ GIM_Try, /*On fail goto*//*Label 163*/ GIMT_Encode4(6476), // Rule ID 5923 //
2674 /* 6411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM_UseMulOps),
2675 /* 6414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2676 /* 6418 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2677 /* 6422 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2678 /* 6426 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2679 /* 6430 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2680 /* 6434 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2681 /* 6438 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2682 /* 6443 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2683 /* 6448 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2684 /* 6450 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (SMMLA:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
2685 /* 6450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMLA),
2686 /* 6453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2687 /* 6455 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
2688 /* 6459 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
2689 /* 6463 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2690 /* 6465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2691 /* 6468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2692 /* 6474 */ GIR_RootConstrainSelectedInstOperands,
2693 /* 6475 */ // GIR_Coverage, 5923,
2694 /* 6475 */ GIR_EraseRootFromParent_Done,
2695 /* 6476 */ // Label 163: @6476
2696 /* 6476 */ GIM_Try, /*On fail goto*//*Label 164*/ GIMT_Encode4(6546), // Rule ID 5960 //
2697 /* 6481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2_UseMulOps),
2698 /* 6484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2699 /* 6488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2700 /* 6492 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2701 /* 6496 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMULH),
2702 /* 6500 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
2703 /* 6504 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
2704 /* 6508 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2705 /* 6513 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2706 /* 6518 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2707 /* 6520 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)) => (t2SMMLA:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
2708 /* 6520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMLA),
2709 /* 6523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2710 /* 6525 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
2711 /* 6529 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
2712 /* 6533 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
2713 /* 6535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2714 /* 6538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2715 /* 6544 */ GIR_RootConstrainSelectedInstOperands,
2716 /* 6545 */ // GIR_Coverage, 5960,
2717 /* 6545 */ GIR_EraseRootFromParent_Done,
2718 /* 6546 */ // Label 164: @6546
2719 /* 6546 */ GIM_Try, /*On fail goto*//*Label 165*/ GIMT_Encode4(6609), // Rule ID 6497 //
2720 /* 6551 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2721 /* 6554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2722 /* 6558 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2723 /* 6562 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2724 /* 6566 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2725 /* 6570 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
2726 /* 6574 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2727 /* 6579 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2728 /* 6581 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec)) => (MVE_VADDVu8acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v16i8] }:$vec)
2729 /* 6581 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8acc),
2730 /* 6584 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2731 /* 6586 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc
2732 /* 6588 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2733 /* 6592 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2734 /* 6595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2735 /* 6601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2736 /* 6607 */ GIR_RootConstrainSelectedInstOperands,
2737 /* 6608 */ // GIR_Coverage, 6497,
2738 /* 6608 */ GIR_EraseRootFromParent_Done,
2739 /* 6609 */ // Label 165: @6609
2740 /* 6609 */ GIM_Try, /*On fail goto*//*Label 166*/ GIMT_Encode4(6672), // Rule ID 6511 //
2741 /* 6614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2742 /* 6617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2743 /* 6621 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2744 /* 6625 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2745 /* 6629 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2746 /* 6633 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
2747 /* 6637 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2748 /* 6642 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2749 /* 6644 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec)) => (MVE_VADDVu16acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v8i16] }:$vec)
2750 /* 6644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16acc),
2751 /* 6647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2752 /* 6649 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc
2753 /* 6651 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2754 /* 6655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2755 /* 6658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2756 /* 6664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2757 /* 6670 */ GIR_RootConstrainSelectedInstOperands,
2758 /* 6671 */ // GIR_Coverage, 6511,
2759 /* 6671 */ GIR_EraseRootFromParent_Done,
2760 /* 6672 */ // Label 166: @6672
2761 /* 6672 */ GIM_Try, /*On fail goto*//*Label 167*/ GIMT_Encode4(6735), // Rule ID 6516 //
2762 /* 6677 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
2763 /* 6680 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2764 /* 6684 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
2765 /* 6688 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2766 /* 6692 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_VECREDUCE_ADD),
2767 /* 6696 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
2768 /* 6700 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
2769 /* 6705 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2770 /* 6707 */ // (add:{ *:[i32] } tGPREven:{ *:[i32] }:$acc, (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec)) => (MVE_VADDVu32acc:{ *:[i32] } ?:{ *:[i32] }:$acc, ?:{ *:[v4i32] }:$vec)
2771 /* 6707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32acc),
2772 /* 6710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
2773 /* 6712 */ GIR_RootToRootCopy, /*OpIdx*/1, // acc
2774 /* 6714 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // vec
2775 /* 6718 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
2776 /* 6721 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2777 /* 6727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2778 /* 6733 */ GIR_RootConstrainSelectedInstOperands,
2779 /* 6734 */ // GIR_Coverage, 6516,
2780 /* 6734 */ GIR_EraseRootFromParent_Done,
2781 /* 6735 */ // Label 167: @6735
2782 /* 6735 */ GIM_Try, /*On fail goto*//*Label 168*/ GIMT_Encode4(6781), // Rule ID 72 //
2783 /* 6740 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
2784 /* 6743 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2785 /* 6747 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2786 /* 6751 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
2787 /* 6755 */ // (add:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ADDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
2788 /* 6755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ADDrr),
2789 /* 6758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2790 /* 6760 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2791 /* 6762 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
2792 /* 6764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2793 /* 6767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2794 /* 6773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2795 /* 6779 */ GIR_RootConstrainSelectedInstOperands,
2796 /* 6780 */ // GIR_Coverage, 72,
2797 /* 6780 */ GIR_EraseRootFromParent_Done,
2798 /* 6781 */ // Label 168: @6781
2799 /* 6781 */ GIM_Try, /*On fail goto*//*Label 169*/ GIMT_Encode4(6827), // Rule ID 304 //
2800 /* 6786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
2801 /* 6789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2802 /* 6793 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2803 /* 6797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
2804 /* 6801 */ // (add:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tADDrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
2805 /* 6801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tADDrr),
2806 /* 6804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2807 /* 6806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
2808 /* 6812 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2809 /* 6814 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
2810 /* 6816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2811 /* 6819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2812 /* 6825 */ GIR_RootConstrainSelectedInstOperands,
2813 /* 6826 */ // GIR_Coverage, 304,
2814 /* 6826 */ GIR_EraseRootFromParent_Done,
2815 /* 6827 */ // Label 169: @6827
2816 /* 6827 */ GIM_Try, /*On fail goto*//*Label 170*/ GIMT_Encode4(6873), // Rule ID 408 //
2817 /* 6832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
2818 /* 6835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2819 /* 6839 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2820 /* 6843 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2821 /* 6847 */ // (add:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
2822 /* 6847 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr),
2823 /* 6850 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2824 /* 6852 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
2825 /* 6854 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
2826 /* 6856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2827 /* 6859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2828 /* 6865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2829 /* 6871 */ GIR_RootConstrainSelectedInstOperands,
2830 /* 6872 */ // GIR_Coverage, 408,
2831 /* 6872 */ GIR_EraseRootFromParent_Done,
2832 /* 6873 */ // Label 170: @6873
2833 /* 6873 */ GIM_Try, /*On fail goto*//*Label 171*/ GIMT_Encode4(6919), // Rule ID 5941 //
2834 /* 6878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
2835 /* 6881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2836 /* 6885 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
2837 /* 6889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
2838 /* 6893 */ // (add:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (t2ADDrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
2839 /* 6893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ADDrr),
2840 /* 6896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
2841 /* 6898 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
2842 /* 6900 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
2843 /* 6902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2844 /* 6905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2845 /* 6911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2846 /* 6917 */ GIR_RootConstrainSelectedInstOperands,
2847 /* 6918 */ // GIR_Coverage, 5941,
2848 /* 6918 */ GIR_EraseRootFromParent_Done,
2849 /* 6919 */ // Label 171: @6919
2850 /* 6919 */ GIM_Reject,
2851 /* 6920 */ // Label 102: @6920
2852 /* 6920 */ GIM_Reject,
2853 /* 6921 */ // Label 93: @6921
2854 /* 6921 */ GIM_Try, /*On fail goto*//*Label 172*/ GIMT_Encode4(6967), // Rule ID 881 //
2855 /* 6926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2856 /* 6929 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
2857 /* 6932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
2858 /* 6935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2859 /* 6939 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2860 /* 6943 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2861 /* 6947 */ // (add:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VADDv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
2862 /* 6947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv1i64),
2863 /* 6950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2864 /* 6952 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
2865 /* 6954 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
2866 /* 6956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2867 /* 6959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2868 /* 6965 */ GIR_RootConstrainSelectedInstOperands,
2869 /* 6966 */ // GIR_Coverage, 881,
2870 /* 6966 */ GIR_EraseRootFromParent_Done,
2871 /* 6967 */ // Label 172: @6967
2872 /* 6967 */ GIM_Reject,
2873 /* 6968 */ // Label 94: @6968
2874 /* 6968 */ GIM_Try, /*On fail goto*//*Label 173*/ GIMT_Encode4(7416),
2875 /* 6973 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
2876 /* 6976 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
2877 /* 6979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2878 /* 6983 */ GIM_Try, /*On fail goto*//*Label 174*/ GIMT_Encode4(7049), // Rule ID 6146 //
2879 /* 6988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2880 /* 6991 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2881 /* 6995 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
2882 /* 6999 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2883 /* 7003 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
2884 /* 7007 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2885 /* 7012 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2886 /* 7017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2887 /* 7021 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2888 /* 7023 */ // (add:{ *:[v2i32] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2889 /* 7023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32),
2890 /* 7026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2891 /* 7028 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
2892 /* 7030 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2893 /* 7034 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2894 /* 7038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2895 /* 7041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2896 /* 7047 */ GIR_RootConstrainSelectedInstOperands,
2897 /* 7048 */ // GIR_Coverage, 6146,
2898 /* 7048 */ GIR_EraseRootFromParent_Done,
2899 /* 7049 */ // Label 174: @7049
2900 /* 7049 */ GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(7115), // Rule ID 6152 //
2901 /* 7054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2902 /* 7057 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2903 /* 7061 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
2904 /* 7065 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2905 /* 7069 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
2906 /* 7073 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2907 /* 7078 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2908 /* 7083 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2909 /* 7087 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2910 /* 7089 */ // (add:{ *:[v2i32] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2911 /* 7089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32),
2912 /* 7092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2913 /* 7094 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
2914 /* 7096 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2915 /* 7100 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2916 /* 7104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2917 /* 7107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2918 /* 7113 */ GIR_RootConstrainSelectedInstOperands,
2919 /* 7114 */ // GIR_Coverage, 6152,
2920 /* 7114 */ GIR_EraseRootFromParent_Done,
2921 /* 7115 */ // Label 175: @7115
2922 /* 7115 */ GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(7181), // Rule ID 6034 //
2923 /* 7120 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2924 /* 7123 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
2925 /* 7127 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2926 /* 7131 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2927 /* 7135 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
2928 /* 7139 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2929 /* 7144 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2930 /* 7149 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2931 /* 7153 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2932 /* 7155 */ // (add:{ *:[v2i32] } (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), DPR:{ *:[v2i32] }:$src1) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2933 /* 7155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32),
2934 /* 7158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2935 /* 7160 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
2936 /* 7162 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2937 /* 7166 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2938 /* 7170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2939 /* 7173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2940 /* 7179 */ GIR_RootConstrainSelectedInstOperands,
2941 /* 7180 */ // GIR_Coverage, 6034,
2942 /* 7180 */ GIR_EraseRootFromParent_Done,
2943 /* 7181 */ // Label 176: @7181
2944 /* 7181 */ GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(7247), // Rule ID 1342 //
2945 /* 7186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2946 /* 7189 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2947 /* 7193 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2948 /* 7197 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
2949 /* 7201 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2950 /* 7205 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
2951 /* 7209 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2952 /* 7214 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2953 /* 7219 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2954 /* 7221 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2955 /* 7221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv2i32),
2956 /* 7224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2957 /* 7226 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
2958 /* 7228 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2959 /* 7232 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2960 /* 7236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2961 /* 7239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2962 /* 7245 */ GIR_RootConstrainSelectedInstOperands,
2963 /* 7246 */ // GIR_Coverage, 1342,
2964 /* 7246 */ GIR_EraseRootFromParent_Done,
2965 /* 7247 */ // Label 177: @7247
2966 /* 7247 */ GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(7313), // Rule ID 1348 //
2967 /* 7252 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2968 /* 7255 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2969 /* 7259 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2970 /* 7263 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
2971 /* 7267 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2972 /* 7271 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
2973 /* 7275 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2974 /* 7280 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2975 /* 7285 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2976 /* 7287 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABAuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2977 /* 7287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv2i32),
2978 /* 7290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
2979 /* 7292 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
2980 /* 7294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
2981 /* 7298 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
2982 /* 7302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
2983 /* 7305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
2984 /* 7311 */ GIR_RootConstrainSelectedInstOperands,
2985 /* 7312 */ // GIR_Coverage, 1348,
2986 /* 7312 */ GIR_EraseRootFromParent_Done,
2987 /* 7313 */ // Label 178: @7313
2988 /* 7313 */ GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(7379), // Rule ID 1008 //
2989 /* 7318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
2990 /* 7321 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2991 /* 7325 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
2992 /* 7329 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
2993 /* 7333 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
2994 /* 7337 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
2995 /* 7341 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2996 /* 7346 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
2997 /* 7351 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
2998 /* 7353 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLAv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
2999 /* 7353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv2i32),
3000 /* 7356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3001 /* 7358 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3002 /* 7360 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3003 /* 7364 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3004 /* 7368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3005 /* 7371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3006 /* 7377 */ GIR_RootConstrainSelectedInstOperands,
3007 /* 7378 */ // GIR_Coverage, 1008,
3008 /* 7378 */ GIR_EraseRootFromParent_Done,
3009 /* 7379 */ // Label 179: @7379
3010 /* 7379 */ GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(7415), // Rule ID 877 //
3011 /* 7384 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3012 /* 7387 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3013 /* 7391 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3014 /* 7395 */ // (add:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VADDv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3015 /* 7395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i32),
3016 /* 7398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3017 /* 7400 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3018 /* 7402 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3019 /* 7404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3020 /* 7407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3021 /* 7413 */ GIR_RootConstrainSelectedInstOperands,
3022 /* 7414 */ // GIR_Coverage, 877,
3023 /* 7414 */ GIR_EraseRootFromParent_Done,
3024 /* 7415 */ // Label 180: @7415
3025 /* 7415 */ GIM_Reject,
3026 /* 7416 */ // Label 173: @7416
3027 /* 7416 */ GIM_Reject,
3028 /* 7417 */ // Label 95: @7417
3029 /* 7417 */ GIM_Try, /*On fail goto*//*Label 181*/ GIMT_Encode4(8439),
3030 /* 7422 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
3031 /* 7425 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
3032 /* 7428 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3033 /* 7432 */ GIM_Try, /*On fail goto*//*Label 182*/ GIMT_Encode4(7500), // Rule ID 901 //
3034 /* 7437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3035 /* 7440 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3036 /* 7444 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3037 /* 7448 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3038 /* 7452 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3039 /* 7457 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3040 /* 7461 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3041 /* 7465 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3042 /* 7469 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3043 /* 7474 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3044 /* 7476 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3045 /* 7476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
3046 /* 7479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3047 /* 7481 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3048 /* 7485 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3049 /* 7489 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3050 /* 7492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3051 /* 7498 */ GIR_RootConstrainSelectedInstOperands,
3052 /* 7499 */ // GIR_Coverage, 901,
3053 /* 7499 */ GIR_EraseRootFromParent_Done,
3054 /* 7500 */ // Label 182: @7500
3055 /* 7500 */ GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(7568), // Rule ID 900 //
3056 /* 7505 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3057 /* 7508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3058 /* 7512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3059 /* 7516 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3060 /* 7520 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3061 /* 7525 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3062 /* 7529 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3063 /* 7533 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3064 /* 7537 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3065 /* 7542 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3066 /* 7544 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3067 /* 7544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
3068 /* 7547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3069 /* 7549 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3070 /* 7553 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3071 /* 7557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3072 /* 7560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3073 /* 7566 */ GIR_RootConstrainSelectedInstOperands,
3074 /* 7567 */ // GIR_Coverage, 900,
3075 /* 7567 */ GIR_EraseRootFromParent_Done,
3076 /* 7568 */ // Label 183: @7568
3077 /* 7568 */ GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(7636), // Rule ID 889 //
3078 /* 7573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3079 /* 7576 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3080 /* 7580 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3081 /* 7584 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3082 /* 7588 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3083 /* 7593 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3084 /* 7597 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
3085 /* 7601 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3086 /* 7605 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3087 /* 7610 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3088 /* 7612 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3089 /* 7612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv2i64),
3090 /* 7615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3091 /* 7617 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3092 /* 7621 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3093 /* 7625 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3094 /* 7628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3095 /* 7634 */ GIR_RootConstrainSelectedInstOperands,
3096 /* 7635 */ // GIR_Coverage, 889,
3097 /* 7635 */ GIR_EraseRootFromParent_Done,
3098 /* 7636 */ // Label 184: @7636
3099 /* 7636 */ GIM_Try, /*On fail goto*//*Label 185*/ GIMT_Encode4(7714), // Rule ID 6158 //
3100 /* 7641 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3101 /* 7644 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3102 /* 7648 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3103 /* 7652 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3104 /* 7656 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3105 /* 7660 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
3106 /* 7664 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3107 /* 7668 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
3108 /* 7672 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3109 /* 7677 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3110 /* 7682 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3111 /* 7686 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3112 /* 7688 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3113 /* 7688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64),
3114 /* 7691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3115 /* 7693 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3116 /* 7695 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3117 /* 7699 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3118 /* 7703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3119 /* 7706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3120 /* 7712 */ GIR_RootConstrainSelectedInstOperands,
3121 /* 7713 */ // GIR_Coverage, 6158,
3122 /* 7713 */ GIR_EraseRootFromParent_Done,
3123 /* 7714 */ // Label 185: @7714
3124 /* 7714 */ GIM_Try, /*On fail goto*//*Label 186*/ GIMT_Encode4(7792), // Rule ID 6161 //
3125 /* 7719 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3126 /* 7722 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3127 /* 7726 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3128 /* 7730 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3129 /* 7734 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3130 /* 7738 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
3131 /* 7742 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3132 /* 7746 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
3133 /* 7750 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3134 /* 7755 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3135 /* 7760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3136 /* 7764 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3137 /* 7766 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)), QPR:{ *:[v2i64] }:$src1) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3138 /* 7766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64),
3139 /* 7769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3140 /* 7771 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3141 /* 7773 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3142 /* 7777 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3143 /* 7781 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3144 /* 7784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3145 /* 7790 */ GIR_RootConstrainSelectedInstOperands,
3146 /* 7791 */ // GIR_Coverage, 6161,
3147 /* 7791 */ GIR_EraseRootFromParent_Done,
3148 /* 7792 */ // Label 186: @7792
3149 /* 7792 */ GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(7860), // Rule ID 899 //
3150 /* 7797 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3151 /* 7800 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3152 /* 7804 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3153 /* 7808 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3154 /* 7812 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3155 /* 7817 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3156 /* 7821 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3157 /* 7825 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3158 /* 7829 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3159 /* 7834 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3160 /* 7836 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3161 /* 7836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
3162 /* 7839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3163 /* 7841 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3164 /* 7845 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3165 /* 7849 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3166 /* 7852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3167 /* 7858 */ GIR_RootConstrainSelectedInstOperands,
3168 /* 7859 */ // GIR_Coverage, 899,
3169 /* 7859 */ GIR_EraseRootFromParent_Done,
3170 /* 7860 */ // Label 187: @7860
3171 /* 7860 */ GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(7928), // Rule ID 898 //
3172 /* 7865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3173 /* 7868 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3174 /* 7872 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3175 /* 7876 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3176 /* 7880 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3177 /* 7885 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3178 /* 7889 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3179 /* 7893 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3180 /* 7897 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3181 /* 7902 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3182 /* 7904 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3183 /* 7904 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv2i64),
3184 /* 7907 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3185 /* 7909 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3186 /* 7913 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3187 /* 7917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3188 /* 7920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3189 /* 7926 */ GIR_RootConstrainSelectedInstOperands,
3190 /* 7927 */ // GIR_Coverage, 898,
3191 /* 7927 */ GIR_EraseRootFromParent_Done,
3192 /* 7928 */ // Label 188: @7928
3193 /* 7928 */ GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(8006), // Rule ID 1354 //
3194 /* 7933 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3195 /* 7936 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3196 /* 7940 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3197 /* 7944 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3198 /* 7948 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3199 /* 7952 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3200 /* 7956 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
3201 /* 7960 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3202 /* 7964 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
3203 /* 7968 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3204 /* 7973 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3205 /* 7978 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3206 /* 7980 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3207 /* 7980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv2i64),
3208 /* 7983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3209 /* 7985 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3210 /* 7987 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3211 /* 7991 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3212 /* 7995 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3213 /* 7998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3214 /* 8004 */ GIR_RootConstrainSelectedInstOperands,
3215 /* 8005 */ // GIR_Coverage, 1354,
3216 /* 8005 */ GIR_EraseRootFromParent_Done,
3217 /* 8006 */ // Label 189: @8006
3218 /* 8006 */ GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(8084), // Rule ID 1357 //
3219 /* 8011 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3220 /* 8014 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3221 /* 8018 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3222 /* 8022 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3223 /* 8026 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3224 /* 8030 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3225 /* 8034 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
3226 /* 8038 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
3227 /* 8042 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v2s32,
3228 /* 8046 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3229 /* 8051 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3230 /* 8056 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3231 /* 8058 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm))) => (VABALuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3232 /* 8058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv2i64),
3233 /* 8061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3234 /* 8063 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3235 /* 8065 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3236 /* 8069 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3237 /* 8073 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3238 /* 8076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3239 /* 8082 */ GIR_RootConstrainSelectedInstOperands,
3240 /* 8083 */ // GIR_Coverage, 1357,
3241 /* 8083 */ GIR_EraseRootFromParent_Done,
3242 /* 8084 */ // Label 190: @8084
3243 /* 8084 */ GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(8137), // Rule ID 6013 //
3244 /* 8089 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3245 /* 8092 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3246 /* 8096 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3247 /* 8100 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3248 /* 8104 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3249 /* 8109 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3250 /* 8113 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3251 /* 8115 */ // (add:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3252 /* 8115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
3253 /* 8118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3254 /* 8120 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
3255 /* 8122 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3256 /* 8126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3257 /* 8129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3258 /* 8135 */ GIR_RootConstrainSelectedInstOperands,
3259 /* 8136 */ // GIR_Coverage, 6013,
3260 /* 8136 */ GIR_EraseRootFromParent_Done,
3261 /* 8137 */ // Label 191: @8137
3262 /* 8137 */ GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(8190), // Rule ID 6007 //
3263 /* 8142 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3264 /* 8145 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3265 /* 8149 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3266 /* 8153 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3267 /* 8157 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3268 /* 8162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3269 /* 8166 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3270 /* 8168 */ // (add:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3271 /* 8168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64),
3272 /* 8171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3273 /* 8173 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
3274 /* 8175 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3275 /* 8179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3276 /* 8182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3277 /* 8188 */ GIR_RootConstrainSelectedInstOperands,
3278 /* 8189 */ // GIR_Coverage, 6007,
3279 /* 8189 */ GIR_EraseRootFromParent_Done,
3280 /* 8190 */ // Label 192: @8190
3281 /* 8190 */ GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(8243), // Rule ID 6012 //
3282 /* 8195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3283 /* 8198 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3284 /* 8202 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3285 /* 8206 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3286 /* 8210 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3287 /* 8215 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3288 /* 8219 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3289 /* 8221 */ // (add:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$Vn) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3290 /* 8221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
3291 /* 8224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3292 /* 8226 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
3293 /* 8228 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3294 /* 8232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3295 /* 8235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3296 /* 8241 */ GIR_RootConstrainSelectedInstOperands,
3297 /* 8242 */ // GIR_Coverage, 6012,
3298 /* 8242 */ GIR_EraseRootFromParent_Done,
3299 /* 8243 */ // Label 193: @8243
3300 /* 8243 */ GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(8296), // Rule ID 910 //
3301 /* 8248 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3302 /* 8251 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3303 /* 8255 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3304 /* 8259 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3305 /* 8263 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3306 /* 8267 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3307 /* 8272 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3308 /* 8274 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3309 /* 8274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
3310 /* 8277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3311 /* 8279 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3312 /* 8281 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3313 /* 8285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3314 /* 8288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3315 /* 8294 */ GIR_RootConstrainSelectedInstOperands,
3316 /* 8295 */ // GIR_Coverage, 910,
3317 /* 8295 */ GIR_EraseRootFromParent_Done,
3318 /* 8296 */ // Label 194: @8296
3319 /* 8296 */ GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(8349), // Rule ID 904 //
3320 /* 8301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3321 /* 8304 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3322 /* 8308 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3323 /* 8312 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3324 /* 8316 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3325 /* 8320 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3326 /* 8325 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3327 /* 8327 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3328 /* 8327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv2i64),
3329 /* 8330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3330 /* 8332 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3331 /* 8334 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3332 /* 8338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3333 /* 8341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3334 /* 8347 */ GIR_RootConstrainSelectedInstOperands,
3335 /* 8348 */ // GIR_Coverage, 904,
3336 /* 8348 */ GIR_EraseRootFromParent_Done,
3337 /* 8349 */ // Label 195: @8349
3338 /* 8349 */ GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(8402), // Rule ID 909 //
3339 /* 8354 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3340 /* 8357 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3341 /* 8361 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3342 /* 8365 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3343 /* 8369 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
3344 /* 8373 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3345 /* 8378 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3346 /* 8380 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VADDWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
3347 /* 8380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv2i64),
3348 /* 8383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3349 /* 8385 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3350 /* 8387 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3351 /* 8391 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3352 /* 8394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3353 /* 8400 */ GIR_RootConstrainSelectedInstOperands,
3354 /* 8401 */ // GIR_Coverage, 909,
3355 /* 8401 */ GIR_EraseRootFromParent_Done,
3356 /* 8402 */ // Label 196: @8402
3357 /* 8402 */ GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(8438), // Rule ID 882 //
3358 /* 8407 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3359 /* 8410 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3360 /* 8414 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3361 /* 8418 */ // (add:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VADDv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
3362 /* 8418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv2i64),
3363 /* 8421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3364 /* 8423 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3365 /* 8425 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3366 /* 8427 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3367 /* 8430 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3368 /* 8436 */ GIR_RootConstrainSelectedInstOperands,
3369 /* 8437 */ // GIR_Coverage, 882,
3370 /* 8437 */ GIR_EraseRootFromParent_Done,
3371 /* 8438 */ // Label 197: @8438
3372 /* 8438 */ GIM_Reject,
3373 /* 8439 */ // Label 181: @8439
3374 /* 8439 */ GIM_Reject,
3375 /* 8440 */ // Label 96: @8440
3376 /* 8440 */ GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(8888),
3377 /* 8445 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
3378 /* 8448 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
3379 /* 8451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3380 /* 8455 */ GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(8521), // Rule ID 6145 //
3381 /* 8460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3382 /* 8463 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3383 /* 8467 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3384 /* 8471 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3385 /* 8475 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3386 /* 8479 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3387 /* 8484 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3388 /* 8489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3389 /* 8493 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3390 /* 8495 */ // (add:{ *:[v4i16] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3391 /* 8495 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16),
3392 /* 8498 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3393 /* 8500 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3394 /* 8502 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3395 /* 8506 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3396 /* 8510 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3397 /* 8513 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3398 /* 8519 */ GIR_RootConstrainSelectedInstOperands,
3399 /* 8520 */ // GIR_Coverage, 6145,
3400 /* 8520 */ GIR_EraseRootFromParent_Done,
3401 /* 8521 */ // Label 199: @8521
3402 /* 8521 */ GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(8587), // Rule ID 6151 //
3403 /* 8526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3404 /* 8529 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3405 /* 8533 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3406 /* 8537 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3407 /* 8541 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3408 /* 8545 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3409 /* 8550 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3410 /* 8555 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3411 /* 8559 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3412 /* 8561 */ // (add:{ *:[v4i16] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3413 /* 8561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16),
3414 /* 8564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3415 /* 8566 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3416 /* 8568 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3417 /* 8572 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3418 /* 8576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3419 /* 8579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3420 /* 8585 */ GIR_RootConstrainSelectedInstOperands,
3421 /* 8586 */ // GIR_Coverage, 6151,
3422 /* 8586 */ GIR_EraseRootFromParent_Done,
3423 /* 8587 */ // Label 200: @8587
3424 /* 8587 */ GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(8653), // Rule ID 6033 //
3425 /* 8592 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3426 /* 8595 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3427 /* 8599 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3428 /* 8603 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3429 /* 8607 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3430 /* 8611 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3431 /* 8616 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3432 /* 8621 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3433 /* 8625 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3434 /* 8627 */ // (add:{ *:[v4i16] } (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), DPR:{ *:[v4i16] }:$src1) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3435 /* 8627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16),
3436 /* 8630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3437 /* 8632 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3438 /* 8634 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3439 /* 8638 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3440 /* 8642 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3441 /* 8645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3442 /* 8651 */ GIR_RootConstrainSelectedInstOperands,
3443 /* 8652 */ // GIR_Coverage, 6033,
3444 /* 8652 */ GIR_EraseRootFromParent_Done,
3445 /* 8653 */ // Label 201: @8653
3446 /* 8653 */ GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(8719), // Rule ID 1341 //
3447 /* 8658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3448 /* 8661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3449 /* 8665 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3450 /* 8669 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3451 /* 8673 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3452 /* 8677 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3453 /* 8681 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3454 /* 8686 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3455 /* 8691 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3456 /* 8693 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3457 /* 8693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i16),
3458 /* 8696 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3459 /* 8698 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3460 /* 8700 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3461 /* 8704 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3462 /* 8708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3463 /* 8711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3464 /* 8717 */ GIR_RootConstrainSelectedInstOperands,
3465 /* 8718 */ // GIR_Coverage, 1341,
3466 /* 8718 */ GIR_EraseRootFromParent_Done,
3467 /* 8719 */ // Label 202: @8719
3468 /* 8719 */ GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(8785), // Rule ID 1347 //
3469 /* 8724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3470 /* 8727 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3471 /* 8731 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3472 /* 8735 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3473 /* 8739 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3474 /* 8743 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3475 /* 8747 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3476 /* 8752 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3477 /* 8757 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3478 /* 8759 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABAuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3479 /* 8759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i16),
3480 /* 8762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3481 /* 8764 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3482 /* 8766 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3483 /* 8770 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3484 /* 8774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3485 /* 8777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3486 /* 8783 */ GIR_RootConstrainSelectedInstOperands,
3487 /* 8784 */ // GIR_Coverage, 1347,
3488 /* 8784 */ GIR_EraseRootFromParent_Done,
3489 /* 8785 */ // Label 203: @8785
3490 /* 8785 */ GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(8851), // Rule ID 1007 //
3491 /* 8790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3492 /* 8793 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3493 /* 8797 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3494 /* 8801 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3495 /* 8805 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3496 /* 8809 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
3497 /* 8813 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3498 /* 8818 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3499 /* 8823 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3500 /* 8825 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLAv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3501 /* 8825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i16),
3502 /* 8828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3503 /* 8830 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3504 /* 8832 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3505 /* 8836 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3506 /* 8840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3507 /* 8843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3508 /* 8849 */ GIR_RootConstrainSelectedInstOperands,
3509 /* 8850 */ // GIR_Coverage, 1007,
3510 /* 8850 */ GIR_EraseRootFromParent_Done,
3511 /* 8851 */ // Label 204: @8851
3512 /* 8851 */ GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(8887), // Rule ID 876 //
3513 /* 8856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3514 /* 8859 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3515 /* 8863 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3516 /* 8867 */ // (add:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VADDv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3517 /* 8867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i16),
3518 /* 8870 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3519 /* 8872 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3520 /* 8874 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
3521 /* 8876 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3522 /* 8879 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3523 /* 8885 */ GIR_RootConstrainSelectedInstOperands,
3524 /* 8886 */ // GIR_Coverage, 876,
3525 /* 8886 */ GIR_EraseRootFromParent_Done,
3526 /* 8887 */ // Label 205: @8887
3527 /* 8887 */ GIM_Reject,
3528 /* 8888 */ // Label 198: @8888
3529 /* 8888 */ GIM_Reject,
3530 /* 8889 */ // Label 97: @8889
3531 /* 8889 */ GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(10452),
3532 /* 8894 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
3533 /* 8897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
3534 /* 8900 */ GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(8972), // Rule ID 897 //
3535 /* 8905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3536 /* 8908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3537 /* 8912 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3538 /* 8916 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3539 /* 8920 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3540 /* 8924 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3541 /* 8929 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3542 /* 8933 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3543 /* 8937 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3544 /* 8941 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3545 /* 8946 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3546 /* 8948 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3547 /* 8948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
3548 /* 8951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3549 /* 8953 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3550 /* 8957 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3551 /* 8961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3552 /* 8964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3553 /* 8970 */ GIR_RootConstrainSelectedInstOperands,
3554 /* 8971 */ // GIR_Coverage, 897,
3555 /* 8971 */ GIR_EraseRootFromParent_Done,
3556 /* 8972 */ // Label 207: @8972
3557 /* 8972 */ GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(9044), // Rule ID 896 //
3558 /* 8977 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3559 /* 8980 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3560 /* 8984 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3561 /* 8988 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3562 /* 8992 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3563 /* 8996 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3564 /* 9001 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3565 /* 9005 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3566 /* 9009 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3567 /* 9013 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3568 /* 9018 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3569 /* 9020 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3570 /* 9020 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
3571 /* 9023 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3572 /* 9025 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3573 /* 9029 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3574 /* 9033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3575 /* 9036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3576 /* 9042 */ GIR_RootConstrainSelectedInstOperands,
3577 /* 9043 */ // GIR_Coverage, 896,
3578 /* 9043 */ GIR_EraseRootFromParent_Done,
3579 /* 9044 */ // Label 208: @9044
3580 /* 9044 */ GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(9116), // Rule ID 888 //
3581 /* 9049 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3582 /* 9052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3583 /* 9056 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3584 /* 9060 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3585 /* 9064 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3586 /* 9068 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3587 /* 9073 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3588 /* 9077 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
3589 /* 9081 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3590 /* 9085 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3591 /* 9090 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3592 /* 9092 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3593 /* 9092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv4i32),
3594 /* 9095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3595 /* 9097 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3596 /* 9101 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3597 /* 9105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3598 /* 9108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3599 /* 9114 */ GIR_RootConstrainSelectedInstOperands,
3600 /* 9115 */ // GIR_Coverage, 888,
3601 /* 9115 */ GIR_EraseRootFromParent_Done,
3602 /* 9116 */ // Label 209: @9116
3603 /* 9116 */ GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(9198), // Rule ID 6157 //
3604 /* 9121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3605 /* 9124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3606 /* 9128 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3607 /* 9132 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3608 /* 9136 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3609 /* 9140 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3610 /* 9144 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
3611 /* 9148 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3612 /* 9152 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
3613 /* 9156 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3614 /* 9161 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3615 /* 9166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3616 /* 9170 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3617 /* 9172 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3618 /* 9172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32),
3619 /* 9175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3620 /* 9177 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3621 /* 9179 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3622 /* 9183 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3623 /* 9187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3624 /* 9190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3625 /* 9196 */ GIR_RootConstrainSelectedInstOperands,
3626 /* 9197 */ // GIR_Coverage, 6157,
3627 /* 9197 */ GIR_EraseRootFromParent_Done,
3628 /* 9198 */ // Label 210: @9198
3629 /* 9198 */ GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(9280), // Rule ID 6160 //
3630 /* 9203 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3631 /* 9206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3632 /* 9210 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3633 /* 9214 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3634 /* 9218 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3635 /* 9222 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3636 /* 9226 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
3637 /* 9230 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3638 /* 9234 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
3639 /* 9238 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3640 /* 9243 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3641 /* 9248 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3642 /* 9252 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3643 /* 9254 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)), QPR:{ *:[v4i32] }:$src1) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3644 /* 9254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32),
3645 /* 9257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3646 /* 9259 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3647 /* 9261 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3648 /* 9265 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3649 /* 9269 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3650 /* 9272 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3651 /* 9278 */ GIR_RootConstrainSelectedInstOperands,
3652 /* 9279 */ // GIR_Coverage, 6160,
3653 /* 9279 */ GIR_EraseRootFromParent_Done,
3654 /* 9280 */ // Label 211: @9280
3655 /* 9280 */ GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(9352), // Rule ID 895 //
3656 /* 9285 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3657 /* 9288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3658 /* 9292 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3659 /* 9296 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3660 /* 9300 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3661 /* 9304 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3662 /* 9309 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3663 /* 9313 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3664 /* 9317 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3665 /* 9321 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3666 /* 9326 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3667 /* 9328 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3668 /* 9328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
3669 /* 9331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3670 /* 9333 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3671 /* 9337 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3672 /* 9341 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3673 /* 9344 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3674 /* 9350 */ GIR_RootConstrainSelectedInstOperands,
3675 /* 9351 */ // GIR_Coverage, 895,
3676 /* 9351 */ GIR_EraseRootFromParent_Done,
3677 /* 9352 */ // Label 212: @9352
3678 /* 9352 */ GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(9424), // Rule ID 894 //
3679 /* 9357 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3680 /* 9360 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3681 /* 9364 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3682 /* 9368 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3683 /* 9372 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3684 /* 9376 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3685 /* 9381 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
3686 /* 9385 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
3687 /* 9389 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3688 /* 9393 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3689 /* 9398 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3690 /* 9400 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3691 /* 9400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv4i32),
3692 /* 9403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3693 /* 9405 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3694 /* 9409 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
3695 /* 9413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3696 /* 9416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3697 /* 9422 */ GIR_RootConstrainSelectedInstOperands,
3698 /* 9423 */ // GIR_Coverage, 894,
3699 /* 9423 */ GIR_EraseRootFromParent_Done,
3700 /* 9424 */ // Label 213: @9424
3701 /* 9424 */ GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(9506), // Rule ID 1353 //
3702 /* 9429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3703 /* 9432 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3704 /* 9436 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3705 /* 9440 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3706 /* 9444 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3707 /* 9448 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3708 /* 9452 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3709 /* 9456 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
3710 /* 9460 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3711 /* 9464 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
3712 /* 9468 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3713 /* 9473 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3714 /* 9478 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3715 /* 9480 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3716 /* 9480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv4i32),
3717 /* 9483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3718 /* 9485 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3719 /* 9487 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3720 /* 9491 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3721 /* 9495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3722 /* 9498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3723 /* 9504 */ GIR_RootConstrainSelectedInstOperands,
3724 /* 9505 */ // GIR_Coverage, 1353,
3725 /* 9505 */ GIR_EraseRootFromParent_Done,
3726 /* 9506 */ // Label 214: @9506
3727 /* 9506 */ GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(9588), // Rule ID 1356 //
3728 /* 9511 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3729 /* 9514 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3730 /* 9518 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3731 /* 9522 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3732 /* 9526 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3733 /* 9530 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3734 /* 9534 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
3735 /* 9538 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
3736 /* 9542 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
3737 /* 9546 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v4s16,
3738 /* 9550 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3739 /* 9555 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3740 /* 9560 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
3741 /* 9562 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm))) => (VABALuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3742 /* 9562 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv4i32),
3743 /* 9565 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3744 /* 9567 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3745 /* 9569 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
3746 /* 9573 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
3747 /* 9577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3748 /* 9580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3749 /* 9586 */ GIR_RootConstrainSelectedInstOperands,
3750 /* 9587 */ // GIR_Coverage, 1356,
3751 /* 9587 */ GIR_EraseRootFromParent_Done,
3752 /* 9588 */ // Label 215: @9588
3753 /* 9588 */ GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(9658), // Rule ID 6149 //
3754 /* 9593 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3755 /* 9596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3756 /* 9600 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3757 /* 9604 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3758 /* 9608 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3759 /* 9612 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3760 /* 9616 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3761 /* 9621 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3762 /* 9626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3763 /* 9630 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3764 /* 9632 */ // (add:{ *:[v4i32] } (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
3765 /* 9632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32),
3766 /* 9635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3767 /* 9637 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3768 /* 9639 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3769 /* 9643 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3770 /* 9647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3771 /* 9650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3772 /* 9656 */ GIR_RootConstrainSelectedInstOperands,
3773 /* 9657 */ // GIR_Coverage, 6149,
3774 /* 9657 */ GIR_EraseRootFromParent_Done,
3775 /* 9658 */ // Label 216: @9658
3776 /* 9658 */ GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(9728), // Rule ID 6155 //
3777 /* 9663 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3778 /* 9666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3779 /* 9670 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3780 /* 9674 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3781 /* 9678 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3782 /* 9682 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3783 /* 9686 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3784 /* 9691 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3785 /* 9696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3786 /* 9700 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3787 /* 9702 */ // (add:{ *:[v4i32] } (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
3788 /* 9702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32),
3789 /* 9705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3790 /* 9707 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3791 /* 9709 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3792 /* 9713 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3793 /* 9717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3794 /* 9720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3795 /* 9726 */ GIR_RootConstrainSelectedInstOperands,
3796 /* 9727 */ // GIR_Coverage, 6155,
3797 /* 9727 */ GIR_EraseRootFromParent_Done,
3798 /* 9728 */ // Label 217: @9728
3799 /* 9728 */ GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(9798), // Rule ID 6037 //
3800 /* 9733 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3801 /* 9736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3802 /* 9740 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3803 /* 9744 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3804 /* 9748 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3805 /* 9752 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3806 /* 9756 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3807 /* 9761 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3808 /* 9766 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3809 /* 9770 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3810 /* 9772 */ // (add:{ *:[v4i32] } (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
3811 /* 9772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32),
3812 /* 9775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3813 /* 9777 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
3814 /* 9779 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3815 /* 9783 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3816 /* 9787 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3817 /* 9790 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3818 /* 9796 */ GIR_RootConstrainSelectedInstOperands,
3819 /* 9797 */ // GIR_Coverage, 6037,
3820 /* 9797 */ GIR_EraseRootFromParent_Done,
3821 /* 9798 */ // Label 218: @9798
3822 /* 9798 */ GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(9855), // Rule ID 6011 //
3823 /* 9803 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3824 /* 9806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3825 /* 9810 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3826 /* 9814 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3827 /* 9818 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3828 /* 9822 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3829 /* 9827 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3830 /* 9831 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3831 /* 9833 */ // (add:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3832 /* 9833 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
3833 /* 9836 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3834 /* 9838 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
3835 /* 9840 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3836 /* 9844 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3837 /* 9847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3838 /* 9853 */ GIR_RootConstrainSelectedInstOperands,
3839 /* 9854 */ // GIR_Coverage, 6011,
3840 /* 9854 */ GIR_EraseRootFromParent_Done,
3841 /* 9855 */ // Label 219: @9855
3842 /* 9855 */ GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(9912), // Rule ID 6006 //
3843 /* 9860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3844 /* 9863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3845 /* 9867 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3846 /* 9871 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3847 /* 9875 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3848 /* 9879 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3849 /* 9884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3850 /* 9888 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3851 /* 9890 */ // (add:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3852 /* 9890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32),
3853 /* 9893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3854 /* 9895 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
3855 /* 9897 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3856 /* 9901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3857 /* 9904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3858 /* 9910 */ GIR_RootConstrainSelectedInstOperands,
3859 /* 9911 */ // GIR_Coverage, 6006,
3860 /* 9911 */ GIR_EraseRootFromParent_Done,
3861 /* 9912 */ // Label 220: @9912
3862 /* 9912 */ GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(9969), // Rule ID 6010 //
3863 /* 9917 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3864 /* 9920 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3865 /* 9924 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
3866 /* 9928 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3867 /* 9932 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3868 /* 9936 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3869 /* 9941 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3870 /* 9945 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3871 /* 9947 */ // (add:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$Vn) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3872 /* 9947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
3873 /* 9950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3874 /* 9952 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
3875 /* 9954 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3876 /* 9958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3877 /* 9961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3878 /* 9967 */ GIR_RootConstrainSelectedInstOperands,
3879 /* 9968 */ // GIR_Coverage, 6010,
3880 /* 9968 */ GIR_EraseRootFromParent_Done,
3881 /* 9969 */ // Label 221: @9969
3882 /* 9969 */ GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(10039), // Rule ID 1345 //
3883 /* 9974 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3884 /* 9977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3885 /* 9981 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3886 /* 9985 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3887 /* 9989 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
3888 /* 9993 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3889 /* 9997 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3890 /* 10001 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3891 /* 10006 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3892 /* 10011 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3893 /* 10013 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
3894 /* 10013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv4i32),
3895 /* 10016 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3896 /* 10018 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3897 /* 10020 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3898 /* 10024 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3899 /* 10028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3900 /* 10031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3901 /* 10037 */ GIR_RootConstrainSelectedInstOperands,
3902 /* 10038 */ // GIR_Coverage, 1345,
3903 /* 10038 */ GIR_EraseRootFromParent_Done,
3904 /* 10039 */ // Label 222: @10039
3905 /* 10039 */ GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(10109), // Rule ID 1351 //
3906 /* 10044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3907 /* 10047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3908 /* 10051 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3909 /* 10055 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3910 /* 10059 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
3911 /* 10063 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3912 /* 10067 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3913 /* 10071 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3914 /* 10076 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3915 /* 10081 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3916 /* 10083 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VABAuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
3917 /* 10083 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv4i32),
3918 /* 10086 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3919 /* 10088 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3920 /* 10090 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3921 /* 10094 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3922 /* 10098 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3923 /* 10101 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3924 /* 10107 */ GIR_RootConstrainSelectedInstOperands,
3925 /* 10108 */ // GIR_Coverage, 1351,
3926 /* 10108 */ GIR_EraseRootFromParent_Done,
3927 /* 10109 */ // Label 223: @10109
3928 /* 10109 */ GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(10179), // Rule ID 1011 //
3929 /* 10114 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3930 /* 10117 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3931 /* 10121 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3932 /* 10125 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3933 /* 10129 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
3934 /* 10133 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
3935 /* 10137 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
3936 /* 10141 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3937 /* 10146 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3938 /* 10151 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3939 /* 10153 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLAv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
3940 /* 10153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv4i32),
3941 /* 10156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3942 /* 10158 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
3943 /* 10160 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
3944 /* 10164 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
3945 /* 10168 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3946 /* 10171 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3947 /* 10177 */ GIR_RootConstrainSelectedInstOperands,
3948 /* 10178 */ // GIR_Coverage, 1011,
3949 /* 10178 */ GIR_EraseRootFromParent_Done,
3950 /* 10179 */ // Label 224: @10179
3951 /* 10179 */ GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(10236), // Rule ID 908 //
3952 /* 10184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3953 /* 10187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3954 /* 10191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3955 /* 10195 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3956 /* 10199 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
3957 /* 10203 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3958 /* 10207 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3959 /* 10212 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3960 /* 10214 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3961 /* 10214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
3962 /* 10217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3963 /* 10219 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3964 /* 10221 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3965 /* 10225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3966 /* 10228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3967 /* 10234 */ GIR_RootConstrainSelectedInstOperands,
3968 /* 10235 */ // GIR_Coverage, 908,
3969 /* 10235 */ GIR_EraseRootFromParent_Done,
3970 /* 10236 */ // Label 225: @10236
3971 /* 10236 */ GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(10293), // Rule ID 903 //
3972 /* 10241 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3973 /* 10244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3974 /* 10248 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3975 /* 10252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3976 /* 10256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
3977 /* 10260 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3978 /* 10264 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3979 /* 10269 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
3980 /* 10271 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
3981 /* 10271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv4i32),
3982 /* 10274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
3983 /* 10276 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
3984 /* 10278 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
3985 /* 10282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
3986 /* 10285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
3987 /* 10291 */ GIR_RootConstrainSelectedInstOperands,
3988 /* 10292 */ // GIR_Coverage, 903,
3989 /* 10292 */ GIR_EraseRootFromParent_Done,
3990 /* 10293 */ // Label 226: @10293
3991 /* 10293 */ GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(10350), // Rule ID 907 //
3992 /* 10298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
3993 /* 10301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3994 /* 10305 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
3995 /* 10309 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
3996 /* 10313 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
3997 /* 10317 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
3998 /* 10321 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
3999 /* 10326 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4000 /* 10328 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VADDWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
4001 /* 10328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv4i32),
4002 /* 10331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4003 /* 10333 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4004 /* 10335 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4005 /* 10339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4006 /* 10342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4007 /* 10348 */ GIR_RootConstrainSelectedInstOperands,
4008 /* 10349 */ // GIR_Coverage, 907,
4009 /* 10349 */ GIR_EraseRootFromParent_Done,
4010 /* 10350 */ // Label 227: @10350
4011 /* 10350 */ GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(10390), // Rule ID 880 //
4012 /* 10355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4013 /* 10358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4014 /* 10362 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4015 /* 10366 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4016 /* 10370 */ // (add:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VADDv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
4017 /* 10370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv4i32),
4018 /* 10373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4019 /* 10375 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4020 /* 10377 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
4021 /* 10379 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4022 /* 10382 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4023 /* 10388 */ GIR_RootConstrainSelectedInstOperands,
4024 /* 10389 */ // GIR_Coverage, 880,
4025 /* 10389 */ GIR_EraseRootFromParent_Done,
4026 /* 10390 */ // Label 228: @10390
4027 /* 10390 */ GIM_Try, /*On fail goto*//*Label 229*/ GIMT_Encode4(10451), // Rule ID 3854 //
4028 /* 10395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
4029 /* 10398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4030 /* 10402 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4031 /* 10406 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4032 /* 10410 */ // (add:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
4033 /* 10410 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4034 /* 10413 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
4035 /* 10417 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4036 /* 10422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi32),
4037 /* 10425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
4038 /* 10427 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
4039 /* 10429 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
4040 /* 10431 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
4041 /* 10434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4042 /* 10440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4043 /* 10446 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4044 /* 10449 */ GIR_RootConstrainSelectedInstOperands,
4045 /* 10450 */ // GIR_Coverage, 3854,
4046 /* 10450 */ GIR_EraseRootFromParent_Done,
4047 /* 10451 */ // Label 229: @10451
4048 /* 10451 */ GIM_Reject,
4049 /* 10452 */ // Label 206: @10452
4050 /* 10452 */ GIM_Reject,
4051 /* 10453 */ // Label 98: @10453
4052 /* 10453 */ GIM_Try, /*On fail goto*//*Label 230*/ GIMT_Encode4(10901),
4053 /* 10458 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
4054 /* 10461 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
4055 /* 10464 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4056 /* 10468 */ GIM_Try, /*On fail goto*//*Label 231*/ GIMT_Encode4(10534), // Rule ID 6144 //
4057 /* 10473 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4058 /* 10476 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4059 /* 10480 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
4060 /* 10484 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4061 /* 10488 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4062 /* 10492 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4063 /* 10497 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4064 /* 10502 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4065 /* 10506 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4066 /* 10508 */ // (add:{ *:[v8i8] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4067 /* 10508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8),
4068 /* 10511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4069 /* 10513 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4070 /* 10515 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4071 /* 10519 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4072 /* 10523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4073 /* 10526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4074 /* 10532 */ GIR_RootConstrainSelectedInstOperands,
4075 /* 10533 */ // GIR_Coverage, 6144,
4076 /* 10533 */ GIR_EraseRootFromParent_Done,
4077 /* 10534 */ // Label 231: @10534
4078 /* 10534 */ GIM_Try, /*On fail goto*//*Label 232*/ GIMT_Encode4(10600), // Rule ID 6150 //
4079 /* 10539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4080 /* 10542 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4081 /* 10546 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
4082 /* 10550 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4083 /* 10554 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4084 /* 10558 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4085 /* 10563 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4086 /* 10568 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4087 /* 10572 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4088 /* 10574 */ // (add:{ *:[v8i8] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4089 /* 10574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8),
4090 /* 10577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4091 /* 10579 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4092 /* 10581 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4093 /* 10585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4094 /* 10589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4095 /* 10592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4096 /* 10598 */ GIR_RootConstrainSelectedInstOperands,
4097 /* 10599 */ // GIR_Coverage, 6150,
4098 /* 10599 */ GIR_EraseRootFromParent_Done,
4099 /* 10600 */ // Label 232: @10600
4100 /* 10600 */ GIM_Try, /*On fail goto*//*Label 233*/ GIMT_Encode4(10666), // Rule ID 6032 //
4101 /* 10605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4102 /* 10608 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4103 /* 10612 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4104 /* 10616 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4105 /* 10620 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4106 /* 10624 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4107 /* 10629 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4108 /* 10634 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4109 /* 10638 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4110 /* 10640 */ // (add:{ *:[v8i8] } (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm), DPR:{ *:[v8i8] }:$src1) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4111 /* 10640 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8),
4112 /* 10643 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4113 /* 10645 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4114 /* 10647 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4115 /* 10651 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4116 /* 10655 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4117 /* 10658 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4118 /* 10664 */ GIR_RootConstrainSelectedInstOperands,
4119 /* 10665 */ // GIR_Coverage, 6032,
4120 /* 10665 */ GIR_EraseRootFromParent_Done,
4121 /* 10666 */ // Label 233: @10666
4122 /* 10666 */ GIM_Try, /*On fail goto*//*Label 234*/ GIMT_Encode4(10732), // Rule ID 1340 //
4123 /* 10671 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4124 /* 10674 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4125 /* 10678 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4126 /* 10682 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
4127 /* 10686 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4128 /* 10690 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4129 /* 10694 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4130 /* 10699 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4131 /* 10704 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4132 /* 10706 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4133 /* 10706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i8),
4134 /* 10709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4135 /* 10711 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4136 /* 10713 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4137 /* 10717 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4138 /* 10721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4139 /* 10724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4140 /* 10730 */ GIR_RootConstrainSelectedInstOperands,
4141 /* 10731 */ // GIR_Coverage, 1340,
4142 /* 10731 */ GIR_EraseRootFromParent_Done,
4143 /* 10732 */ // Label 234: @10732
4144 /* 10732 */ GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(10798), // Rule ID 1346 //
4145 /* 10737 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4146 /* 10740 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4147 /* 10744 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4148 /* 10748 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
4149 /* 10752 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4150 /* 10756 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4151 /* 10760 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4152 /* 10765 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4153 /* 10770 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4154 /* 10772 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABAuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4155 /* 10772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i8),
4156 /* 10775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4157 /* 10777 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4158 /* 10779 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4159 /* 10783 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4160 /* 10787 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4161 /* 10790 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4162 /* 10796 */ GIR_RootConstrainSelectedInstOperands,
4163 /* 10797 */ // GIR_Coverage, 1346,
4164 /* 10797 */ GIR_EraseRootFromParent_Done,
4165 /* 10798 */ // Label 235: @10798
4166 /* 10798 */ GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(10864), // Rule ID 1006 //
4167 /* 10803 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4168 /* 10806 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4169 /* 10810 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4170 /* 10814 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4171 /* 10818 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4172 /* 10822 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
4173 /* 10826 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4174 /* 10831 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4175 /* 10836 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4176 /* 10838 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLAv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4177 /* 10838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i8),
4178 /* 10841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4179 /* 10843 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4180 /* 10845 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4181 /* 10849 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4182 /* 10853 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4183 /* 10856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4184 /* 10862 */ GIR_RootConstrainSelectedInstOperands,
4185 /* 10863 */ // GIR_Coverage, 1006,
4186 /* 10863 */ GIR_EraseRootFromParent_Done,
4187 /* 10864 */ // Label 236: @10864
4188 /* 10864 */ GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(10900), // Rule ID 875 //
4189 /* 10869 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4190 /* 10872 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4191 /* 10876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4192 /* 10880 */ // (add:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VADDv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4193 /* 10880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i8),
4194 /* 10883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4195 /* 10885 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4196 /* 10887 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
4197 /* 10889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4198 /* 10892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4199 /* 10898 */ GIR_RootConstrainSelectedInstOperands,
4200 /* 10899 */ // GIR_Coverage, 875,
4201 /* 10899 */ GIR_EraseRootFromParent_Done,
4202 /* 10900 */ // Label 237: @10900
4203 /* 10900 */ GIM_Reject,
4204 /* 10901 */ // Label 230: @10901
4205 /* 10901 */ GIM_Reject,
4206 /* 10902 */ // Label 99: @10902
4207 /* 10902 */ GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(12465),
4208 /* 10907 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
4209 /* 10910 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
4210 /* 10913 */ GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(10985), // Rule ID 893 //
4211 /* 10918 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4212 /* 10921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4213 /* 10925 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4214 /* 10929 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4215 /* 10933 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4216 /* 10937 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4217 /* 10942 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4218 /* 10946 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4219 /* 10950 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4220 /* 10954 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4221 /* 10959 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4222 /* 10961 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4223 /* 10961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
4224 /* 10964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4225 /* 10966 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4226 /* 10970 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4227 /* 10974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4228 /* 10977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4229 /* 10983 */ GIR_RootConstrainSelectedInstOperands,
4230 /* 10984 */ // GIR_Coverage, 893,
4231 /* 10984 */ GIR_EraseRootFromParent_Done,
4232 /* 10985 */ // Label 239: @10985
4233 /* 10985 */ GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(11057), // Rule ID 892 //
4234 /* 10990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4235 /* 10993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4236 /* 10997 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4237 /* 11001 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4238 /* 11005 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4239 /* 11009 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4240 /* 11014 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4241 /* 11018 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4242 /* 11022 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4243 /* 11026 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4244 /* 11031 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4245 /* 11033 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4246 /* 11033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
4247 /* 11036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4248 /* 11038 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4249 /* 11042 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4250 /* 11046 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4251 /* 11049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4252 /* 11055 */ GIR_RootConstrainSelectedInstOperands,
4253 /* 11056 */ // GIR_Coverage, 892,
4254 /* 11056 */ GIR_EraseRootFromParent_Done,
4255 /* 11057 */ // Label 240: @11057
4256 /* 11057 */ GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(11129), // Rule ID 887 //
4257 /* 11062 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4258 /* 11065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4259 /* 11069 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4260 /* 11073 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4261 /* 11077 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4262 /* 11081 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4263 /* 11086 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4264 /* 11090 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
4265 /* 11094 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4266 /* 11098 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4267 /* 11103 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4268 /* 11105 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4269 /* 11105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLsv8i16),
4270 /* 11108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4271 /* 11110 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4272 /* 11114 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4273 /* 11118 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4274 /* 11121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4275 /* 11127 */ GIR_RootConstrainSelectedInstOperands,
4276 /* 11128 */ // GIR_Coverage, 887,
4277 /* 11128 */ GIR_EraseRootFromParent_Done,
4278 /* 11129 */ // Label 241: @11129
4279 /* 11129 */ GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(11211), // Rule ID 6156 //
4280 /* 11134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4281 /* 11137 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4282 /* 11141 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4283 /* 11145 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4284 /* 11149 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4285 /* 11153 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4286 /* 11157 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
4287 /* 11161 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4288 /* 11165 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
4289 /* 11169 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4290 /* 11174 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4291 /* 11179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4292 /* 11183 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4293 /* 11185 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4294 /* 11185 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16),
4295 /* 11188 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4296 /* 11190 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4297 /* 11192 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4298 /* 11196 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4299 /* 11200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4300 /* 11203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4301 /* 11209 */ GIR_RootConstrainSelectedInstOperands,
4302 /* 11210 */ // GIR_Coverage, 6156,
4303 /* 11210 */ GIR_EraseRootFromParent_Done,
4304 /* 11211 */ // Label 242: @11211
4305 /* 11211 */ GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(11293), // Rule ID 6159 //
4306 /* 11216 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4307 /* 11219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4308 /* 11223 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4309 /* 11227 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4310 /* 11231 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4311 /* 11235 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4312 /* 11239 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
4313 /* 11243 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4314 /* 11247 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
4315 /* 11251 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4316 /* 11256 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4317 /* 11261 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4318 /* 11265 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4319 /* 11267 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)), QPR:{ *:[v8i16] }:$src1) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4320 /* 11267 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16),
4321 /* 11270 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4322 /* 11272 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4323 /* 11274 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4324 /* 11278 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4325 /* 11282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4326 /* 11285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4327 /* 11291 */ GIR_RootConstrainSelectedInstOperands,
4328 /* 11292 */ // GIR_Coverage, 6159,
4329 /* 11292 */ GIR_EraseRootFromParent_Done,
4330 /* 11293 */ // Label 243: @11293
4331 /* 11293 */ GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(11365), // Rule ID 891 //
4332 /* 11298 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4333 /* 11301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4334 /* 11305 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4335 /* 11309 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4336 /* 11313 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4337 /* 11317 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4338 /* 11322 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4339 /* 11326 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4340 /* 11330 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4341 /* 11334 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4342 /* 11339 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4343 /* 11341 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4344 /* 11341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
4345 /* 11344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4346 /* 11346 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4347 /* 11350 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4348 /* 11354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4349 /* 11357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4350 /* 11363 */ GIR_RootConstrainSelectedInstOperands,
4351 /* 11364 */ // GIR_Coverage, 891,
4352 /* 11364 */ GIR_EraseRootFromParent_Done,
4353 /* 11365 */ // Label 244: @11365
4354 /* 11365 */ GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(11437), // Rule ID 890 //
4355 /* 11370 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4356 /* 11373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4357 /* 11377 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4358 /* 11381 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4359 /* 11385 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4360 /* 11389 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4361 /* 11394 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
4362 /* 11398 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
4363 /* 11402 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4364 /* 11406 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4365 /* 11411 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4366 /* 11413 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4367 /* 11413 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDLuv8i16),
4368 /* 11416 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4369 /* 11418 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4370 /* 11422 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
4371 /* 11426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4372 /* 11429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4373 /* 11435 */ GIR_RootConstrainSelectedInstOperands,
4374 /* 11436 */ // GIR_Coverage, 890,
4375 /* 11436 */ GIR_EraseRootFromParent_Done,
4376 /* 11437 */ // Label 245: @11437
4377 /* 11437 */ GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(11519), // Rule ID 1352 //
4378 /* 11442 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4379 /* 11445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4380 /* 11449 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4381 /* 11453 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4382 /* 11457 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4383 /* 11461 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4384 /* 11465 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4385 /* 11469 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDS),
4386 /* 11473 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4387 /* 11477 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
4388 /* 11481 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4389 /* 11486 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4390 /* 11491 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4391 /* 11493 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4392 /* 11493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALsv8i16),
4393 /* 11496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4394 /* 11498 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4395 /* 11500 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4396 /* 11504 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4397 /* 11508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4398 /* 11511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4399 /* 11517 */ GIR_RootConstrainSelectedInstOperands,
4400 /* 11518 */ // GIR_Coverage, 1352,
4401 /* 11518 */ GIR_EraseRootFromParent_Done,
4402 /* 11519 */ // Label 246: @11519
4403 /* 11519 */ GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(11601), // Rule ID 1355 //
4404 /* 11524 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4405 /* 11527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4406 /* 11531 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4407 /* 11535 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4408 /* 11539 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4409 /* 11543 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4410 /* 11547 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
4411 /* 11551 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ABDU),
4412 /* 11555 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
4413 /* 11559 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_v8s8,
4414 /* 11563 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4415 /* 11568 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4416 /* 11573 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
4417 /* 11575 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm))) => (VABALuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4418 /* 11575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABALuv8i16),
4419 /* 11578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4420 /* 11580 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4421 /* 11582 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vn
4422 /* 11586 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // Vm
4423 /* 11590 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4424 /* 11593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4425 /* 11599 */ GIR_RootConstrainSelectedInstOperands,
4426 /* 11600 */ // GIR_Coverage, 1355,
4427 /* 11600 */ GIR_EraseRootFromParent_Done,
4428 /* 11601 */ // Label 247: @11601
4429 /* 11601 */ GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(11671), // Rule ID 6148 //
4430 /* 11606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4431 /* 11609 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4432 /* 11613 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4433 /* 11617 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
4434 /* 11621 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
4435 /* 11625 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
4436 /* 11629 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4437 /* 11634 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4438 /* 11639 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4439 /* 11643 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4440 /* 11645 */ // (add:{ *:[v8i16] } (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4441 /* 11645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16),
4442 /* 11648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4443 /* 11650 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4444 /* 11652 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4445 /* 11656 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4446 /* 11660 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4447 /* 11663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4448 /* 11669 */ GIR_RootConstrainSelectedInstOperands,
4449 /* 11670 */ // GIR_Coverage, 6148,
4450 /* 11670 */ GIR_EraseRootFromParent_Done,
4451 /* 11671 */ // Label 248: @11671
4452 /* 11671 */ GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(11741), // Rule ID 6154 //
4453 /* 11676 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4454 /* 11679 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4455 /* 11683 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4456 /* 11687 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
4457 /* 11691 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
4458 /* 11695 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
4459 /* 11699 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4460 /* 11704 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4461 /* 11709 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4462 /* 11713 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4463 /* 11715 */ // (add:{ *:[v8i16] } (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4464 /* 11715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16),
4465 /* 11718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4466 /* 11720 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4467 /* 11722 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4468 /* 11726 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4469 /* 11730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4470 /* 11733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4471 /* 11739 */ GIR_RootConstrainSelectedInstOperands,
4472 /* 11740 */ // GIR_Coverage, 6154,
4473 /* 11740 */ GIR_EraseRootFromParent_Done,
4474 /* 11741 */ // Label 249: @11741
4475 /* 11741 */ GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(11811), // Rule ID 6036 //
4476 /* 11746 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4477 /* 11749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4478 /* 11753 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4479 /* 11757 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4480 /* 11761 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
4481 /* 11765 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
4482 /* 11769 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4483 /* 11774 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4484 /* 11779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4485 /* 11783 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4486 /* 11785 */ // (add:{ *:[v8i16] } (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm), QPR:{ *:[v8i16] }:$src1) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4487 /* 11785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16),
4488 /* 11788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4489 /* 11790 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4490 /* 11792 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4491 /* 11796 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4492 /* 11800 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4493 /* 11803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4494 /* 11809 */ GIR_RootConstrainSelectedInstOperands,
4495 /* 11810 */ // GIR_Coverage, 6036,
4496 /* 11810 */ GIR_EraseRootFromParent_Done,
4497 /* 11811 */ // Label 250: @11811
4498 /* 11811 */ GIM_Try, /*On fail goto*//*Label 251*/ GIMT_Encode4(11868), // Rule ID 6009 //
4499 /* 11816 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4500 /* 11819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4501 /* 11823 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4502 /* 11827 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4503 /* 11831 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4504 /* 11835 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4505 /* 11840 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4506 /* 11844 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4507 /* 11846 */ // (add:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4508 /* 11846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
4509 /* 11849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4510 /* 11851 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4511 /* 11853 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4512 /* 11857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4513 /* 11860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4514 /* 11866 */ GIR_RootConstrainSelectedInstOperands,
4515 /* 11867 */ // GIR_Coverage, 6009,
4516 /* 11867 */ GIR_EraseRootFromParent_Done,
4517 /* 11868 */ // Label 251: @11868
4518 /* 11868 */ GIM_Try, /*On fail goto*//*Label 252*/ GIMT_Encode4(11925), // Rule ID 6005 //
4519 /* 11873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4520 /* 11876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4521 /* 11880 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4522 /* 11884 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4523 /* 11888 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4524 /* 11892 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4525 /* 11897 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4526 /* 11901 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4527 /* 11903 */ // (add:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4528 /* 11903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16),
4529 /* 11906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4530 /* 11908 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4531 /* 11910 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4532 /* 11914 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4533 /* 11917 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4534 /* 11923 */ GIR_RootConstrainSelectedInstOperands,
4535 /* 11924 */ // GIR_Coverage, 6005,
4536 /* 11924 */ GIR_EraseRootFromParent_Done,
4537 /* 11925 */ // Label 252: @11925
4538 /* 11925 */ GIM_Try, /*On fail goto*//*Label 253*/ GIMT_Encode4(11982), // Rule ID 6008 //
4539 /* 11930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4540 /* 11933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4541 /* 11937 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4542 /* 11941 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4543 /* 11945 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4544 /* 11949 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4545 /* 11954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4546 /* 11958 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4547 /* 11960 */ // (add:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm), QPR:{ *:[v8i16] }:$Vn) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4548 /* 11960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
4549 /* 11963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4550 /* 11965 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
4551 /* 11967 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4552 /* 11971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4553 /* 11974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4554 /* 11980 */ GIR_RootConstrainSelectedInstOperands,
4555 /* 11981 */ // GIR_Coverage, 6008,
4556 /* 11981 */ GIR_EraseRootFromParent_Done,
4557 /* 11982 */ // Label 253: @11982
4558 /* 11982 */ GIM_Try, /*On fail goto*//*Label 254*/ GIMT_Encode4(12052), // Rule ID 1344 //
4559 /* 11987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4560 /* 11990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4561 /* 11994 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4562 /* 11998 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4563 /* 12002 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
4564 /* 12006 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
4565 /* 12010 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
4566 /* 12014 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4567 /* 12019 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4568 /* 12024 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4569 /* 12026 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4570 /* 12026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv8i16),
4571 /* 12029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4572 /* 12031 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4573 /* 12033 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4574 /* 12037 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4575 /* 12041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4576 /* 12044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4577 /* 12050 */ GIR_RootConstrainSelectedInstOperands,
4578 /* 12051 */ // GIR_Coverage, 1344,
4579 /* 12051 */ GIR_EraseRootFromParent_Done,
4580 /* 12052 */ // Label 254: @12052
4581 /* 12052 */ GIM_Try, /*On fail goto*//*Label 255*/ GIMT_Encode4(12122), // Rule ID 1350 //
4582 /* 12057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4583 /* 12060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4584 /* 12064 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4585 /* 12068 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4586 /* 12072 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
4587 /* 12076 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
4588 /* 12080 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
4589 /* 12084 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4590 /* 12089 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4591 /* 12094 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4592 /* 12096 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VABAuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4593 /* 12096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv8i16),
4594 /* 12099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4595 /* 12101 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4596 /* 12103 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4597 /* 12107 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4598 /* 12111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4599 /* 12114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4600 /* 12120 */ GIR_RootConstrainSelectedInstOperands,
4601 /* 12121 */ // GIR_Coverage, 1350,
4602 /* 12121 */ GIR_EraseRootFromParent_Done,
4603 /* 12122 */ // Label 255: @12122
4604 /* 12122 */ GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(12192), // Rule ID 1010 //
4605 /* 12127 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4606 /* 12130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4607 /* 12134 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4608 /* 12138 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4609 /* 12142 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4610 /* 12146 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
4611 /* 12150 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
4612 /* 12154 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4613 /* 12159 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4614 /* 12164 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4615 /* 12166 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLAv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4616 /* 12166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv8i16),
4617 /* 12169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4618 /* 12171 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4619 /* 12173 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4620 /* 12177 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4621 /* 12181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4622 /* 12184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4623 /* 12190 */ GIR_RootConstrainSelectedInstOperands,
4624 /* 12191 */ // GIR_Coverage, 1010,
4625 /* 12191 */ GIR_EraseRootFromParent_Done,
4626 /* 12192 */ // Label 256: @12192
4627 /* 12192 */ GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(12249), // Rule ID 906 //
4628 /* 12197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4629 /* 12200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4630 /* 12204 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4631 /* 12208 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4632 /* 12212 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
4633 /* 12216 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4634 /* 12220 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4635 /* 12225 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4636 /* 12227 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4637 /* 12227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
4638 /* 12230 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4639 /* 12232 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4640 /* 12234 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4641 /* 12238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4642 /* 12241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4643 /* 12247 */ GIR_RootConstrainSelectedInstOperands,
4644 /* 12248 */ // GIR_Coverage, 906,
4645 /* 12248 */ GIR_EraseRootFromParent_Done,
4646 /* 12249 */ // Label 257: @12249
4647 /* 12249 */ GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(12306), // Rule ID 902 //
4648 /* 12254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4649 /* 12257 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4650 /* 12261 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4651 /* 12265 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4652 /* 12269 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
4653 /* 12273 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4654 /* 12277 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4655 /* 12282 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4656 /* 12284 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4657 /* 12284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWsv8i16),
4658 /* 12287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4659 /* 12289 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4660 /* 12291 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4661 /* 12295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4662 /* 12298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4663 /* 12304 */ GIR_RootConstrainSelectedInstOperands,
4664 /* 12305 */ // GIR_Coverage, 902,
4665 /* 12305 */ GIR_EraseRootFromParent_Done,
4666 /* 12306 */ // Label 258: @12306
4667 /* 12306 */ GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(12363), // Rule ID 905 //
4668 /* 12311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4669 /* 12314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4670 /* 12318 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4671 /* 12322 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4672 /* 12326 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
4673 /* 12330 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
4674 /* 12334 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
4675 /* 12339 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4676 /* 12341 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VADDWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
4677 /* 12341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDWuv8i16),
4678 /* 12344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4679 /* 12346 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4680 /* 12348 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
4681 /* 12352 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4682 /* 12355 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4683 /* 12361 */ GIR_RootConstrainSelectedInstOperands,
4684 /* 12362 */ // GIR_Coverage, 905,
4685 /* 12362 */ GIR_EraseRootFromParent_Done,
4686 /* 12363 */ // Label 259: @12363
4687 /* 12363 */ GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(12403), // Rule ID 879 //
4688 /* 12368 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4689 /* 12371 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4690 /* 12375 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4691 /* 12379 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4692 /* 12383 */ // (add:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VADDv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
4693 /* 12383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv8i16),
4694 /* 12386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4695 /* 12388 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4696 /* 12390 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
4697 /* 12392 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4698 /* 12395 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4699 /* 12401 */ GIR_RootConstrainSelectedInstOperands,
4700 /* 12402 */ // GIR_Coverage, 879,
4701 /* 12402 */ GIR_EraseRootFromParent_Done,
4702 /* 12403 */ // Label 260: @12403
4703 /* 12403 */ GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(12464), // Rule ID 3850 //
4704 /* 12408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
4705 /* 12411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4706 /* 12415 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4707 /* 12419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4708 /* 12423 */ // (add:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
4709 /* 12423 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4710 /* 12426 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
4711 /* 12430 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4712 /* 12435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi16),
4713 /* 12438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
4714 /* 12440 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
4715 /* 12442 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
4716 /* 12444 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
4717 /* 12447 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4718 /* 12453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4719 /* 12459 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4720 /* 12462 */ GIR_RootConstrainSelectedInstOperands,
4721 /* 12463 */ // GIR_Coverage, 3850,
4722 /* 12463 */ GIR_EraseRootFromParent_Done,
4723 /* 12464 */ // Label 261: @12464
4724 /* 12464 */ GIM_Reject,
4725 /* 12465 */ // Label 238: @12465
4726 /* 12465 */ GIM_Reject,
4727 /* 12466 */ // Label 100: @12466
4728 /* 12466 */ GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(12999),
4729 /* 12471 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
4730 /* 12474 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
4731 /* 12477 */ GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(12547), // Rule ID 6147 //
4732 /* 12482 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4733 /* 12485 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4734 /* 12489 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4735 /* 12493 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
4736 /* 12497 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
4737 /* 12501 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
4738 /* 12505 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4739 /* 12510 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4740 /* 12515 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4741 /* 12519 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4742 /* 12521 */ // (add:{ *:[v16i8] } (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
4743 /* 12521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8),
4744 /* 12524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4745 /* 12526 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4746 /* 12528 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4747 /* 12532 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4748 /* 12536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4749 /* 12539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4750 /* 12545 */ GIR_RootConstrainSelectedInstOperands,
4751 /* 12546 */ // GIR_Coverage, 6147,
4752 /* 12546 */ GIR_EraseRootFromParent_Done,
4753 /* 12547 */ // Label 263: @12547
4754 /* 12547 */ GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(12617), // Rule ID 6153 //
4755 /* 12552 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4756 /* 12555 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4757 /* 12559 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4758 /* 12563 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
4759 /* 12567 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
4760 /* 12571 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
4761 /* 12575 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4762 /* 12580 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4763 /* 12585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4764 /* 12589 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4765 /* 12591 */ // (add:{ *:[v16i8] } (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
4766 /* 12591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8),
4767 /* 12594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4768 /* 12596 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4769 /* 12598 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4770 /* 12602 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4771 /* 12606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4772 /* 12609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4773 /* 12615 */ GIR_RootConstrainSelectedInstOperands,
4774 /* 12616 */ // GIR_Coverage, 6153,
4775 /* 12616 */ GIR_EraseRootFromParent_Done,
4776 /* 12617 */ // Label 264: @12617
4777 /* 12617 */ GIM_Try, /*On fail goto*//*Label 265*/ GIMT_Encode4(12687), // Rule ID 6035 //
4778 /* 12622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4779 /* 12625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4780 /* 12629 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4781 /* 12633 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4782 /* 12637 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
4783 /* 12641 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
4784 /* 12645 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4785 /* 12650 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4786 /* 12655 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4787 /* 12659 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4788 /* 12661 */ // (add:{ *:[v16i8] } (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm), QPR:{ *:[v16i8] }:$src1) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
4789 /* 12661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8),
4790 /* 12664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4791 /* 12666 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
4792 /* 12668 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4793 /* 12672 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4794 /* 12676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4795 /* 12679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4796 /* 12685 */ GIR_RootConstrainSelectedInstOperands,
4797 /* 12686 */ // GIR_Coverage, 6035,
4798 /* 12686 */ GIR_EraseRootFromParent_Done,
4799 /* 12687 */ // Label 265: @12687
4800 /* 12687 */ GIM_Try, /*On fail goto*//*Label 266*/ GIMT_Encode4(12757), // Rule ID 1343 //
4801 /* 12692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4802 /* 12695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4803 /* 12699 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4804 /* 12703 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4805 /* 12707 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
4806 /* 12711 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
4807 /* 12715 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
4808 /* 12719 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4809 /* 12724 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4810 /* 12729 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4811 /* 12731 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
4812 /* 12731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAsv16i8),
4813 /* 12734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4814 /* 12736 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4815 /* 12738 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4816 /* 12742 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4817 /* 12746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4818 /* 12749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4819 /* 12755 */ GIR_RootConstrainSelectedInstOperands,
4820 /* 12756 */ // GIR_Coverage, 1343,
4821 /* 12756 */ GIR_EraseRootFromParent_Done,
4822 /* 12757 */ // Label 266: @12757
4823 /* 12757 */ GIM_Try, /*On fail goto*//*Label 267*/ GIMT_Encode4(12827), // Rule ID 1349 //
4824 /* 12762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4825 /* 12765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4826 /* 12769 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4827 /* 12773 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4828 /* 12777 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
4829 /* 12781 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
4830 /* 12785 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
4831 /* 12789 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4832 /* 12794 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4833 /* 12799 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4834 /* 12801 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VABAuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
4835 /* 12801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABAuv16i8),
4836 /* 12804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4837 /* 12806 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4838 /* 12808 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4839 /* 12812 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4840 /* 12816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4841 /* 12819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4842 /* 12825 */ GIR_RootConstrainSelectedInstOperands,
4843 /* 12826 */ // GIR_Coverage, 1349,
4844 /* 12826 */ GIR_EraseRootFromParent_Done,
4845 /* 12827 */ // Label 267: @12827
4846 /* 12827 */ GIM_Try, /*On fail goto*//*Label 268*/ GIMT_Encode4(12897), // Rule ID 1009 //
4847 /* 12832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4848 /* 12835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4849 /* 12839 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4850 /* 12843 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4851 /* 12847 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
4852 /* 12851 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
4853 /* 12855 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
4854 /* 12859 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4855 /* 12864 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4856 /* 12869 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4857 /* 12871 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLAv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
4858 /* 12871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLAv16i8),
4859 /* 12874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4860 /* 12876 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
4861 /* 12878 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
4862 /* 12882 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
4863 /* 12886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4864 /* 12889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4865 /* 12895 */ GIR_RootConstrainSelectedInstOperands,
4866 /* 12896 */ // GIR_Coverage, 1009,
4867 /* 12896 */ GIR_EraseRootFromParent_Done,
4868 /* 12897 */ // Label 268: @12897
4869 /* 12897 */ GIM_Try, /*On fail goto*//*Label 269*/ GIMT_Encode4(12937), // Rule ID 878 //
4870 /* 12902 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
4871 /* 12905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4872 /* 12909 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4873 /* 12913 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
4874 /* 12917 */ // (add:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VADDv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
4875 /* 12917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDv16i8),
4876 /* 12920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
4877 /* 12922 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
4878 /* 12924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
4879 /* 12926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4880 /* 12929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4881 /* 12935 */ GIR_RootConstrainSelectedInstOperands,
4882 /* 12936 */ // GIR_Coverage, 878,
4883 /* 12936 */ GIR_EraseRootFromParent_Done,
4884 /* 12937 */ // Label 269: @12937
4885 /* 12937 */ GIM_Try, /*On fail goto*//*Label 270*/ GIMT_Encode4(12998), // Rule ID 3846 //
4886 /* 12942 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
4887 /* 12945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4888 /* 12949 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4889 /* 12953 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
4890 /* 12957 */ // (add:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
4891 /* 12957 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
4892 /* 12960 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
4893 /* 12964 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
4894 /* 12969 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDi8),
4895 /* 12972 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
4896 /* 12974 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
4897 /* 12976 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
4898 /* 12978 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
4899 /* 12981 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4900 /* 12987 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4901 /* 12993 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
4902 /* 12996 */ GIR_RootConstrainSelectedInstOperands,
4903 /* 12997 */ // GIR_Coverage, 3846,
4904 /* 12997 */ GIR_EraseRootFromParent_Done,
4905 /* 12998 */ // Label 270: @12998
4906 /* 12998 */ GIM_Reject,
4907 /* 12999 */ // Label 262: @12999
4908 /* 12999 */ GIM_Reject,
4909 /* 13000 */ // Label 101: @13000
4910 /* 13000 */ GIM_Reject,
4911 /* 13001 */ // Label 1: @13001
4912 /* 13001 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 280*/ GIMT_Encode4(16244),
4913 /* 13012 */ /*GILLT_s32*//*Label 271*/ GIMT_Encode4(13072),
4914 /* 13016 */ /*GILLT_s64*//*Label 272*/ GIMT_Encode4(13686), GIMT_Encode4(0),
4915 /* 13024 */ /*GILLT_v2s32*//*Label 273*/ GIMT_Encode4(13733),
4916 /* 13028 */ /*GILLT_v2s64*//*Label 274*/ GIMT_Encode4(13848), GIMT_Encode4(0),
4917 /* 13036 */ /*GILLT_v4s16*//*Label 275*/ GIMT_Encode4(14400),
4918 /* 13040 */ /*GILLT_v4s32*//*Label 276*/ GIMT_Encode4(14515), GIMT_Encode4(0), GIMT_Encode4(0),
4919 /* 13052 */ /*GILLT_v8s8*//*Label 277*/ GIMT_Encode4(15230),
4920 /* 13056 */ /*GILLT_v8s16*//*Label 278*/ GIMT_Encode4(15345), GIMT_Encode4(0), GIMT_Encode4(0),
4921 /* 13068 */ /*GILLT_v16s8*//*Label 279*/ GIMT_Encode4(16060),
4922 /* 13072 */ // Label 271: @13072
4923 /* 13072 */ GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(13685),
4924 /* 13077 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
4925 /* 13080 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
4926 /* 13083 */ GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(13127), // Rule ID 329 //
4927 /* 13088 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
4928 /* 13091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
4929 /* 13095 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
4930 /* 13099 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
4931 /* 13103 */ // (sub:{ *:[i32] } 0:{ *:[i32] }, tGPR:{ *:[i32] }:$Rn) => (tRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)
4932 /* 13103 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tRSB),
4933 /* 13106 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4934 /* 13108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
4935 /* 13114 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4936 /* 13116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4937 /* 13119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4938 /* 13125 */ GIR_RootConstrainSelectedInstOperands,
4939 /* 13126 */ // GIR_Coverage, 329,
4940 /* 13126 */ GIR_EraseRootFromParent_Done,
4941 /* 13127 */ // Label 282: @13127
4942 /* 13127 */ GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(13184), // Rule ID 95 //
4943 /* 13132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
4944 /* 13135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4945 /* 13139 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4946 /* 13143 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4947 /* 13147 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
4948 /* 13151 */ // MIs[1] Operand 1
4949 /* 13151 */ // No operand predicates
4950 /* 13151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4951 /* 13155 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4952 /* 13157 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, GPR:{ *:[i32] }:$Rn) => (RSBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4953 /* 13157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RSBri),
4954 /* 13160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4955 /* 13162 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4956 /* 13164 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4957 /* 13167 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4958 /* 13170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4959 /* 13176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4960 /* 13182 */ GIR_RootConstrainSelectedInstOperands,
4961 /* 13183 */ // GIR_Coverage, 95,
4962 /* 13183 */ GIR_EraseRootFromParent_Done,
4963 /* 13184 */ // Label 283: @13184
4964 /* 13184 */ GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(13241), // Rule ID 426 //
4965 /* 13189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
4966 /* 13192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4967 /* 13196 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
4968 /* 13200 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4969 /* 13204 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
4970 /* 13208 */ // MIs[1] Operand 1
4971 /* 13208 */ // No operand predicates
4972 /* 13208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
4973 /* 13212 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4974 /* 13214 */ // (sub:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, rGPR:{ *:[i32] }:$Rn) => (t2RSBri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4975 /* 13214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RSBri),
4976 /* 13217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4977 /* 13219 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
4978 /* 13221 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
4979 /* 13224 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
4980 /* 13227 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4981 /* 13233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
4982 /* 13239 */ GIR_RootConstrainSelectedInstOperands,
4983 /* 13240 */ // GIR_Coverage, 426,
4984 /* 13240 */ GIR_EraseRootFromParent_Done,
4985 /* 13241 */ // Label 284: @13241
4986 /* 13241 */ GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(13298), // Rule ID 75 //
4987 /* 13246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
4988 /* 13249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4989 /* 13253 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
4990 /* 13257 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
4991 /* 13261 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
4992 /* 13265 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
4993 /* 13269 */ // MIs[1] Operand 1
4994 /* 13269 */ // No operand predicates
4995 /* 13269 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
4996 /* 13271 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (SUBri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
4997 /* 13271 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBri),
4998 /* 13274 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
4999 /* 13276 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5000 /* 13278 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
5001 /* 13281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5002 /* 13284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5003 /* 13290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5004 /* 13296 */ GIR_RootConstrainSelectedInstOperands,
5005 /* 13297 */ // GIR_Coverage, 75,
5006 /* 13297 */ GIR_EraseRootFromParent_Done,
5007 /* 13298 */ // Label 285: @13298
5008 /* 13298 */ GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(13355), // Rule ID 410 //
5009 /* 13303 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
5010 /* 13306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5011 /* 13310 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5012 /* 13314 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5013 /* 13318 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5014 /* 13322 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
5015 /* 13326 */ // MIs[1] Operand 1
5016 /* 13326 */ // No operand predicates
5017 /* 13326 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5018 /* 13328 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2SUBri:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5019 /* 13328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri),
5020 /* 13331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5021 /* 13333 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5022 /* 13335 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
5023 /* 13338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5024 /* 13341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5025 /* 13347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5026 /* 13353 */ GIR_RootConstrainSelectedInstOperands,
5027 /* 13354 */ // GIR_Coverage, 410,
5028 /* 13354 */ GIR_EraseRootFromParent_Done,
5029 /* 13355 */ // Label 286: @13355
5030 /* 13355 */ GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(13406), // Rule ID 411 //
5031 /* 13360 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
5032 /* 13363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5033 /* 13367 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5034 /* 13371 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5035 /* 13375 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
5036 /* 13379 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_4095),
5037 /* 13383 */ // MIs[1] Operand 1
5038 /* 13383 */ // No operand predicates
5039 /* 13383 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5040 /* 13385 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_imm0_4095>>:$imm) => (t2SUBri12:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
5041 /* 13385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBri12),
5042 /* 13388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5043 /* 13390 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5044 /* 13392 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
5045 /* 13395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5046 /* 13398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5047 /* 13404 */ GIR_RootConstrainSelectedInstOperands,
5048 /* 13405 */ // GIR_Coverage, 411,
5049 /* 13405 */ GIR_EraseRootFromParent_Done,
5050 /* 13406 */ // Label 287: @13406
5051 /* 13406 */ GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(13476), // Rule ID 172 //
5052 /* 13411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM_UseMulOps),
5053 /* 13414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5054 /* 13418 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5055 /* 13422 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5056 /* 13426 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5057 /* 13430 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5058 /* 13434 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5059 /* 13438 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5060 /* 13443 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5061 /* 13448 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5062 /* 13450 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)) => (MLS:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
5063 /* 13450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MLS),
5064 /* 13453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5065 /* 13455 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5066 /* 13459 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
5067 /* 13463 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
5068 /* 13465 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5069 /* 13468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5070 /* 13474 */ GIR_RootConstrainSelectedInstOperands,
5071 /* 13475 */ // GIR_Coverage, 172,
5072 /* 13475 */ GIR_EraseRootFromParent_Done,
5073 /* 13476 */ // Label 288: @13476
5074 /* 13476 */ GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(13546), // Rule ID 503 //
5075 /* 13481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_UseMulOps),
5076 /* 13484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5077 /* 13488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5078 /* 13492 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5079 /* 13496 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5080 /* 13500 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
5081 /* 13504 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
5082 /* 13508 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5083 /* 13513 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5084 /* 13518 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5085 /* 13520 */ // (sub:{ *:[i32] } rGPR:{ *:[i32] }:$Ra, (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)) => (t2MLS:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
5086 /* 13520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MLS),
5087 /* 13523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5088 /* 13525 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
5089 /* 13529 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rm
5090 /* 13533 */ GIR_RootToRootCopy, /*OpIdx*/1, // Ra
5091 /* 13535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5092 /* 13538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5093 /* 13544 */ GIR_RootConstrainSelectedInstOperands,
5094 /* 13545 */ // GIR_Coverage, 503,
5095 /* 13545 */ GIR_EraseRootFromParent_Done,
5096 /* 13546 */ // Label 289: @13546
5097 /* 13546 */ GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(13592), // Rule ID 76 //
5098 /* 13551 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
5099 /* 13554 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5100 /* 13558 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5101 /* 13562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
5102 /* 13566 */ // (sub:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SUBrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
5103 /* 13566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SUBrr),
5104 /* 13569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5105 /* 13571 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5106 /* 13573 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
5107 /* 13575 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5108 /* 13578 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5109 /* 13584 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5110 /* 13590 */ GIR_RootConstrainSelectedInstOperands,
5111 /* 13591 */ // GIR_Coverage, 76,
5112 /* 13591 */ GIR_EraseRootFromParent_Done,
5113 /* 13592 */ // Label 290: @13592
5114 /* 13592 */ GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(13638), // Rule ID 332 //
5115 /* 13597 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
5116 /* 13600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
5117 /* 13604 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
5118 /* 13608 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
5119 /* 13612 */ // (sub:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tSUBrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
5120 /* 13612 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSUBrr),
5121 /* 13615 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5122 /* 13617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
5123 /* 13623 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5124 /* 13625 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
5125 /* 13627 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5126 /* 13630 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5127 /* 13636 */ GIR_RootConstrainSelectedInstOperands,
5128 /* 13637 */ // GIR_Coverage, 332,
5129 /* 13637 */ GIR_EraseRootFromParent_Done,
5130 /* 13638 */ // Label 291: @13638
5131 /* 13638 */ GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(13684), // Rule ID 412 //
5132 /* 13643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
5133 /* 13646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5134 /* 13650 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
5135 /* 13654 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
5136 /* 13658 */ // (sub:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SUBrr:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
5137 /* 13658 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SUBrr),
5138 /* 13661 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
5139 /* 13663 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
5140 /* 13665 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
5141 /* 13667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5142 /* 13670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5143 /* 13676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5144 /* 13682 */ GIR_RootConstrainSelectedInstOperands,
5145 /* 13683 */ // GIR_Coverage, 412,
5146 /* 13683 */ GIR_EraseRootFromParent_Done,
5147 /* 13684 */ // Label 292: @13684
5148 /* 13684 */ GIM_Reject,
5149 /* 13685 */ // Label 281: @13685
5150 /* 13685 */ GIM_Reject,
5151 /* 13686 */ // Label 272: @13686
5152 /* 13686 */ GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(13732), // Rule ID 1127 //
5153 /* 13691 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5154 /* 13694 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
5155 /* 13697 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
5156 /* 13700 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5157 /* 13704 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5158 /* 13708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5159 /* 13712 */ // (sub:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VSUBv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
5160 /* 13712 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv1i64),
5161 /* 13715 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5162 /* 13717 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5163 /* 13719 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5164 /* 13721 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5165 /* 13724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5166 /* 13730 */ GIR_RootConstrainSelectedInstOperands,
5167 /* 13731 */ // GIR_Coverage, 1127,
5168 /* 13731 */ GIR_EraseRootFromParent_Done,
5169 /* 13732 */ // Label 293: @13732
5170 /* 13732 */ GIM_Reject,
5171 /* 13733 */ // Label 273: @13733
5172 /* 13733 */ GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(13847),
5173 /* 13738 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
5174 /* 13741 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
5175 /* 13744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5176 /* 13748 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5177 /* 13752 */ GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(13814), // Rule ID 1054 //
5178 /* 13757 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5179 /* 13760 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5180 /* 13764 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5181 /* 13768 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5182 /* 13772 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
5183 /* 13776 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5184 /* 13781 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5185 /* 13786 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5186 /* 13788 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VMLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5187 /* 13788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv2i32),
5188 /* 13791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5189 /* 13793 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5190 /* 13795 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5191 /* 13799 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5192 /* 13803 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5193 /* 13806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5194 /* 13812 */ GIR_RootConstrainSelectedInstOperands,
5195 /* 13813 */ // GIR_Coverage, 1054,
5196 /* 13813 */ GIR_EraseRootFromParent_Done,
5197 /* 13814 */ // Label 295: @13814
5198 /* 13814 */ GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(13846), // Rule ID 1123 //
5199 /* 13819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5200 /* 13822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5201 /* 13826 */ // (sub:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VSUBv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5202 /* 13826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i32),
5203 /* 13829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5204 /* 13831 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5205 /* 13833 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5206 /* 13835 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5207 /* 13838 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5208 /* 13844 */ GIR_RootConstrainSelectedInstOperands,
5209 /* 13845 */ // GIR_Coverage, 1123,
5210 /* 13845 */ GIR_EraseRootFromParent_Done,
5211 /* 13846 */ // Label 296: @13846
5212 /* 13846 */ GIM_Reject,
5213 /* 13847 */ // Label 294: @13847
5214 /* 13847 */ GIM_Reject,
5215 /* 13848 */ // Label 274: @13848
5216 /* 13848 */ GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(14399),
5217 /* 13853 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
5218 /* 13856 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
5219 /* 13859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5220 /* 13863 */ GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(13931), // Rule ID 1147 //
5221 /* 13868 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5222 /* 13871 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5223 /* 13875 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5224 /* 13879 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5225 /* 13883 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5226 /* 13888 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5227 /* 13892 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5228 /* 13896 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5229 /* 13900 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5230 /* 13905 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5231 /* 13907 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5232 /* 13907 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5233 /* 13910 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5234 /* 13912 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5235 /* 13916 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5236 /* 13920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5237 /* 13923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5238 /* 13929 */ GIR_RootConstrainSelectedInstOperands,
5239 /* 13930 */ // GIR_Coverage, 1147,
5240 /* 13930 */ GIR_EraseRootFromParent_Done,
5241 /* 13931 */ // Label 298: @13931
5242 /* 13931 */ GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(13999), // Rule ID 1146 //
5243 /* 13936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5244 /* 13939 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5245 /* 13943 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5246 /* 13947 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5247 /* 13951 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5248 /* 13956 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5249 /* 13960 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5250 /* 13964 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5251 /* 13968 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5252 /* 13973 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5253 /* 13975 */ // (sub:{ *:[v2i64] } (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5254 /* 13975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5255 /* 13978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5256 /* 13980 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5257 /* 13984 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5258 /* 13988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5259 /* 13991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5260 /* 13997 */ GIR_RootConstrainSelectedInstOperands,
5261 /* 13998 */ // GIR_Coverage, 1146,
5262 /* 13998 */ GIR_EraseRootFromParent_Done,
5263 /* 13999 */ // Label 299: @13999
5264 /* 13999 */ GIM_Try, /*On fail goto*//*Label 300*/ GIMT_Encode4(14067), // Rule ID 1135 //
5265 /* 14004 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5266 /* 14007 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5267 /* 14011 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5268 /* 14015 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5269 /* 14019 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5270 /* 14024 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5271 /* 14028 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
5272 /* 14032 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5273 /* 14036 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5274 /* 14041 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5275 /* 14043 */ // (sub:{ *:[v2i64] } (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5276 /* 14043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv2i64),
5277 /* 14046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5278 /* 14048 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5279 /* 14052 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5280 /* 14056 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5281 /* 14059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5282 /* 14065 */ GIR_RootConstrainSelectedInstOperands,
5283 /* 14066 */ // GIR_Coverage, 1135,
5284 /* 14066 */ GIR_EraseRootFromParent_Done,
5285 /* 14067 */ // Label 300: @14067
5286 /* 14067 */ GIM_Try, /*On fail goto*//*Label 301*/ GIMT_Encode4(14135), // Rule ID 1145 //
5287 /* 14072 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5288 /* 14075 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5289 /* 14079 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5290 /* 14083 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5291 /* 14087 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5292 /* 14092 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5293 /* 14096 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5294 /* 14100 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5295 /* 14104 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5296 /* 14109 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5297 /* 14111 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5298 /* 14111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5299 /* 14114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5300 /* 14116 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5301 /* 14120 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5302 /* 14124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5303 /* 14127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5304 /* 14133 */ GIR_RootConstrainSelectedInstOperands,
5305 /* 14134 */ // GIR_Coverage, 1145,
5306 /* 14134 */ GIR_EraseRootFromParent_Done,
5307 /* 14135 */ // Label 301: @14135
5308 /* 14135 */ GIM_Try, /*On fail goto*//*Label 302*/ GIMT_Encode4(14203), // Rule ID 1144 //
5309 /* 14140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5310 /* 14143 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5311 /* 14147 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5312 /* 14151 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5313 /* 14155 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5314 /* 14160 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5315 /* 14164 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5316 /* 14168 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v2s32,
5317 /* 14172 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5318 /* 14177 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5319 /* 14179 */ // (sub:{ *:[v2i64] } (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn), (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5320 /* 14179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv2i64),
5321 /* 14182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5322 /* 14184 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5323 /* 14188 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5324 /* 14192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5325 /* 14195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5326 /* 14201 */ GIR_RootConstrainSelectedInstOperands,
5327 /* 14202 */ // GIR_Coverage, 1144,
5328 /* 14202 */ GIR_EraseRootFromParent_Done,
5329 /* 14203 */ // Label 302: @14203
5330 /* 14203 */ GIM_Try, /*On fail goto*//*Label 303*/ GIMT_Encode4(14256), // Rule ID 1156 //
5331 /* 14208 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5332 /* 14211 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5333 /* 14215 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5334 /* 14219 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5335 /* 14223 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5336 /* 14227 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5337 /* 14232 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5338 /* 14234 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5339 /* 14234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64),
5340 /* 14237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5341 /* 14239 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5342 /* 14241 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5343 /* 14245 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5344 /* 14248 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5345 /* 14254 */ GIR_RootConstrainSelectedInstOperands,
5346 /* 14255 */ // GIR_Coverage, 1156,
5347 /* 14255 */ GIR_EraseRootFromParent_Done,
5348 /* 14256 */ // Label 303: @14256
5349 /* 14256 */ GIM_Try, /*On fail goto*//*Label 304*/ GIMT_Encode4(14309), // Rule ID 1150 //
5350 /* 14261 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5351 /* 14264 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5352 /* 14268 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5353 /* 14272 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5354 /* 14276 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5355 /* 14280 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5356 /* 14285 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5357 /* 14287 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5358 /* 14287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv2i64),
5359 /* 14290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5360 /* 14292 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5361 /* 14294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5362 /* 14298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5363 /* 14301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5364 /* 14307 */ GIR_RootConstrainSelectedInstOperands,
5365 /* 14308 */ // GIR_Coverage, 1150,
5366 /* 14308 */ GIR_EraseRootFromParent_Done,
5367 /* 14309 */ // Label 304: @14309
5368 /* 14309 */ GIM_Try, /*On fail goto*//*Label 305*/ GIMT_Encode4(14362), // Rule ID 1155 //
5369 /* 14314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5370 /* 14317 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5371 /* 14321 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5372 /* 14325 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5373 /* 14329 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
5374 /* 14333 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5375 /* 14338 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5376 /* 14340 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)) => (VSUBWuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
5377 /* 14340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv2i64),
5378 /* 14343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5379 /* 14345 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5380 /* 14347 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5381 /* 14351 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5382 /* 14354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5383 /* 14360 */ GIR_RootConstrainSelectedInstOperands,
5384 /* 14361 */ // GIR_Coverage, 1155,
5385 /* 14361 */ GIR_EraseRootFromParent_Done,
5386 /* 14362 */ // Label 305: @14362
5387 /* 14362 */ GIM_Try, /*On fail goto*//*Label 306*/ GIMT_Encode4(14398), // Rule ID 1128 //
5388 /* 14367 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5389 /* 14370 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5390 /* 14374 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5391 /* 14378 */ // (sub:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VSUBv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
5392 /* 14378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv2i64),
5393 /* 14381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5394 /* 14383 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5395 /* 14385 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5396 /* 14387 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5397 /* 14390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5398 /* 14396 */ GIR_RootConstrainSelectedInstOperands,
5399 /* 14397 */ // GIR_Coverage, 1128,
5400 /* 14397 */ GIR_EraseRootFromParent_Done,
5401 /* 14398 */ // Label 306: @14398
5402 /* 14398 */ GIM_Reject,
5403 /* 14399 */ // Label 297: @14399
5404 /* 14399 */ GIM_Reject,
5405 /* 14400 */ // Label 275: @14400
5406 /* 14400 */ GIM_Try, /*On fail goto*//*Label 307*/ GIMT_Encode4(14514),
5407 /* 14405 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
5408 /* 14408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
5409 /* 14411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5410 /* 14415 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5411 /* 14419 */ GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(14481), // Rule ID 1053 //
5412 /* 14424 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5413 /* 14427 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5414 /* 14431 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5415 /* 14435 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5416 /* 14439 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
5417 /* 14443 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5418 /* 14448 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5419 /* 14453 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5420 /* 14455 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VMLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5421 /* 14455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i16),
5422 /* 14458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5423 /* 14460 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5424 /* 14462 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5425 /* 14466 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5426 /* 14470 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5427 /* 14473 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5428 /* 14479 */ GIR_RootConstrainSelectedInstOperands,
5429 /* 14480 */ // GIR_Coverage, 1053,
5430 /* 14480 */ GIR_EraseRootFromParent_Done,
5431 /* 14481 */ // Label 308: @14481
5432 /* 14481 */ GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(14513), // Rule ID 1122 //
5433 /* 14486 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5434 /* 14489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5435 /* 14493 */ // (sub:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VSUBv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5436 /* 14493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i16),
5437 /* 14496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5438 /* 14498 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5439 /* 14500 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5440 /* 14502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5441 /* 14505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5442 /* 14511 */ GIR_RootConstrainSelectedInstOperands,
5443 /* 14512 */ // GIR_Coverage, 1122,
5444 /* 14512 */ GIR_EraseRootFromParent_Done,
5445 /* 14513 */ // Label 309: @14513
5446 /* 14513 */ GIM_Reject,
5447 /* 14514 */ // Label 307: @14514
5448 /* 14514 */ GIM_Reject,
5449 /* 14515 */ // Label 276: @14515
5450 /* 14515 */ GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(15229),
5451 /* 14520 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
5452 /* 14523 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
5453 /* 14526 */ GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(14598), // Rule ID 1143 //
5454 /* 14531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5455 /* 14534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5456 /* 14538 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5457 /* 14542 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5458 /* 14546 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5459 /* 14550 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5460 /* 14555 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5461 /* 14559 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5462 /* 14563 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5463 /* 14567 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5464 /* 14572 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5465 /* 14574 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5466 /* 14574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5467 /* 14577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5468 /* 14579 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5469 /* 14583 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5470 /* 14587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5471 /* 14590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5472 /* 14596 */ GIR_RootConstrainSelectedInstOperands,
5473 /* 14597 */ // GIR_Coverage, 1143,
5474 /* 14597 */ GIR_EraseRootFromParent_Done,
5475 /* 14598 */ // Label 311: @14598
5476 /* 14598 */ GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(14670), // Rule ID 1142 //
5477 /* 14603 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5478 /* 14606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5479 /* 14610 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5480 /* 14614 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5481 /* 14618 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5482 /* 14622 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5483 /* 14627 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5484 /* 14631 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5485 /* 14635 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5486 /* 14639 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5487 /* 14644 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5488 /* 14646 */ // (sub:{ *:[v4i32] } (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5489 /* 14646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5490 /* 14649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5491 /* 14651 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5492 /* 14655 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5493 /* 14659 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5494 /* 14662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5495 /* 14668 */ GIR_RootConstrainSelectedInstOperands,
5496 /* 14669 */ // GIR_Coverage, 1142,
5497 /* 14669 */ GIR_EraseRootFromParent_Done,
5498 /* 14670 */ // Label 312: @14670
5499 /* 14670 */ GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(14742), // Rule ID 1134 //
5500 /* 14675 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5501 /* 14678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5502 /* 14682 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5503 /* 14686 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5504 /* 14690 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5505 /* 14694 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5506 /* 14699 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5507 /* 14703 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
5508 /* 14707 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5509 /* 14711 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5510 /* 14716 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5511 /* 14718 */ // (sub:{ *:[v4i32] } (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5512 /* 14718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv4i32),
5513 /* 14721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5514 /* 14723 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5515 /* 14727 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5516 /* 14731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5517 /* 14734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5518 /* 14740 */ GIR_RootConstrainSelectedInstOperands,
5519 /* 14741 */ // GIR_Coverage, 1134,
5520 /* 14741 */ GIR_EraseRootFromParent_Done,
5521 /* 14742 */ // Label 313: @14742
5522 /* 14742 */ GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(14814), // Rule ID 1141 //
5523 /* 14747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5524 /* 14750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5525 /* 14754 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5526 /* 14758 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5527 /* 14762 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5528 /* 14766 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5529 /* 14771 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5530 /* 14775 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5531 /* 14779 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5532 /* 14783 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5533 /* 14788 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5534 /* 14790 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5535 /* 14790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5536 /* 14793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5537 /* 14795 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5538 /* 14799 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5539 /* 14803 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5540 /* 14806 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5541 /* 14812 */ GIR_RootConstrainSelectedInstOperands,
5542 /* 14813 */ // GIR_Coverage, 1141,
5543 /* 14813 */ GIR_EraseRootFromParent_Done,
5544 /* 14814 */ // Label 314: @14814
5545 /* 14814 */ GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(14886), // Rule ID 1140 //
5546 /* 14819 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5547 /* 14822 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5548 /* 14826 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5549 /* 14830 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5550 /* 14834 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5551 /* 14838 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5552 /* 14843 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5553 /* 14847 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5554 /* 14851 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s16,
5555 /* 14855 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5556 /* 14860 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5557 /* 14862 */ // (sub:{ *:[v4i32] } (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn), (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5558 /* 14862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv4i32),
5559 /* 14865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5560 /* 14867 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5561 /* 14871 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5562 /* 14875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5563 /* 14878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5564 /* 14884 */ GIR_RootConstrainSelectedInstOperands,
5565 /* 14885 */ // GIR_Coverage, 1140,
5566 /* 14885 */ GIR_EraseRootFromParent_Done,
5567 /* 14886 */ // Label 315: @14886
5568 /* 14886 */ GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(14956), // Rule ID 1057 //
5569 /* 14891 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5570 /* 14894 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5571 /* 14898 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5572 /* 14902 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5573 /* 14906 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5574 /* 14910 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
5575 /* 14914 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
5576 /* 14918 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5577 /* 14923 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5578 /* 14928 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5579 /* 14930 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)) => (VMLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
5580 /* 14930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv4i32),
5581 /* 14933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5582 /* 14935 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5583 /* 14937 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5584 /* 14941 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5585 /* 14945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5586 /* 14948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5587 /* 14954 */ GIR_RootConstrainSelectedInstOperands,
5588 /* 14955 */ // GIR_Coverage, 1057,
5589 /* 14955 */ GIR_EraseRootFromParent_Done,
5590 /* 14956 */ // Label 316: @14956
5591 /* 14956 */ GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(15013), // Rule ID 1154 //
5592 /* 14961 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5593 /* 14964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5594 /* 14968 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5595 /* 14972 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5596 /* 14976 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5597 /* 14980 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5598 /* 14984 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5599 /* 14989 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5600 /* 14991 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5601 /* 14991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32),
5602 /* 14994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5603 /* 14996 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5604 /* 14998 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5605 /* 15002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5606 /* 15005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5607 /* 15011 */ GIR_RootConstrainSelectedInstOperands,
5608 /* 15012 */ // GIR_Coverage, 1154,
5609 /* 15012 */ GIR_EraseRootFromParent_Done,
5610 /* 15013 */ // Label 317: @15013
5611 /* 15013 */ GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(15070), // Rule ID 1149 //
5612 /* 15018 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5613 /* 15021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5614 /* 15025 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5615 /* 15029 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5616 /* 15033 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5617 /* 15037 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5618 /* 15041 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5619 /* 15046 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5620 /* 15048 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5621 /* 15048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv4i32),
5622 /* 15051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5623 /* 15053 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5624 /* 15055 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5625 /* 15059 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5626 /* 15062 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5627 /* 15068 */ GIR_RootConstrainSelectedInstOperands,
5628 /* 15069 */ // GIR_Coverage, 1149,
5629 /* 15069 */ GIR_EraseRootFromParent_Done,
5630 /* 15070 */ // Label 318: @15070
5631 /* 15070 */ GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(15127), // Rule ID 1153 //
5632 /* 15075 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5633 /* 15078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5634 /* 15082 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5635 /* 15086 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5636 /* 15090 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5637 /* 15094 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
5638 /* 15098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5639 /* 15103 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5640 /* 15105 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)) => (VSUBWuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
5641 /* 15105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv4i32),
5642 /* 15108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5643 /* 15110 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5644 /* 15112 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5645 /* 15116 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5646 /* 15119 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5647 /* 15125 */ GIR_RootConstrainSelectedInstOperands,
5648 /* 15126 */ // GIR_Coverage, 1153,
5649 /* 15126 */ GIR_EraseRootFromParent_Done,
5650 /* 15127 */ // Label 319: @15127
5651 /* 15127 */ GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(15167), // Rule ID 1126 //
5652 /* 15132 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5653 /* 15135 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5654 /* 15139 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5655 /* 15143 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5656 /* 15147 */ // (sub:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VSUBv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
5657 /* 15147 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv4i32),
5658 /* 15150 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5659 /* 15152 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5660 /* 15154 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5661 /* 15156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5662 /* 15159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5663 /* 15165 */ GIR_RootConstrainSelectedInstOperands,
5664 /* 15166 */ // GIR_Coverage, 1126,
5665 /* 15166 */ GIR_EraseRootFromParent_Done,
5666 /* 15167 */ // Label 320: @15167
5667 /* 15167 */ GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(15228), // Rule ID 3866 //
5668 /* 15172 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
5669 /* 15175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5670 /* 15179 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5671 /* 15183 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5672 /* 15187 */ // (sub:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VSUBi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
5673 /* 15187 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5674 /* 15190 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5675 /* 15194 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
5676 /* 15199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi32),
5677 /* 15202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
5678 /* 15204 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
5679 /* 15206 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
5680 /* 15208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5681 /* 15211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5682 /* 15217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5683 /* 15223 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5684 /* 15226 */ GIR_RootConstrainSelectedInstOperands,
5685 /* 15227 */ // GIR_Coverage, 3866,
5686 /* 15227 */ GIR_EraseRootFromParent_Done,
5687 /* 15228 */ // Label 321: @15228
5688 /* 15228 */ GIM_Reject,
5689 /* 15229 */ // Label 310: @15229
5690 /* 15229 */ GIM_Reject,
5691 /* 15230 */ // Label 277: @15230
5692 /* 15230 */ GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(15344),
5693 /* 15235 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
5694 /* 15238 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
5695 /* 15241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5696 /* 15245 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5697 /* 15249 */ GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(15311), // Rule ID 1052 //
5698 /* 15254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5699 /* 15257 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5700 /* 15261 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5701 /* 15265 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5702 /* 15269 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
5703 /* 15273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5704 /* 15278 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5705 /* 15283 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5706 /* 15285 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VMLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5707 /* 15285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i8),
5708 /* 15288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5709 /* 15290 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5710 /* 15292 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5711 /* 15296 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5712 /* 15300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5713 /* 15303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5714 /* 15309 */ GIR_RootConstrainSelectedInstOperands,
5715 /* 15310 */ // GIR_Coverage, 1052,
5716 /* 15310 */ GIR_EraseRootFromParent_Done,
5717 /* 15311 */ // Label 323: @15311
5718 /* 15311 */ GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(15343), // Rule ID 1121 //
5719 /* 15316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5720 /* 15319 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5721 /* 15323 */ // (sub:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSUBv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5722 /* 15323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i8),
5723 /* 15326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5724 /* 15328 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5725 /* 15330 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5726 /* 15332 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5727 /* 15335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5728 /* 15341 */ GIR_RootConstrainSelectedInstOperands,
5729 /* 15342 */ // GIR_Coverage, 1121,
5730 /* 15342 */ GIR_EraseRootFromParent_Done,
5731 /* 15343 */ // Label 324: @15343
5732 /* 15343 */ GIM_Reject,
5733 /* 15344 */ // Label 322: @15344
5734 /* 15344 */ GIM_Reject,
5735 /* 15345 */ // Label 278: @15345
5736 /* 15345 */ GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(16059),
5737 /* 15350 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
5738 /* 15353 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
5739 /* 15356 */ GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(15428), // Rule ID 1139 //
5740 /* 15361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5741 /* 15364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5742 /* 15368 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5743 /* 15372 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5744 /* 15376 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5745 /* 15380 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5746 /* 15385 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5747 /* 15389 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5748 /* 15393 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5749 /* 15397 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5750 /* 15402 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5751 /* 15404 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5752 /* 15404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5753 /* 15407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5754 /* 15409 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5755 /* 15413 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5756 /* 15417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5757 /* 15420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5758 /* 15426 */ GIR_RootConstrainSelectedInstOperands,
5759 /* 15427 */ // GIR_Coverage, 1139,
5760 /* 15427 */ GIR_EraseRootFromParent_Done,
5761 /* 15428 */ // Label 326: @15428
5762 /* 15428 */ GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(15500), // Rule ID 1138 //
5763 /* 15433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5764 /* 15436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5765 /* 15440 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5766 /* 15444 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5767 /* 15448 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5768 /* 15452 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5769 /* 15457 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5770 /* 15461 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5771 /* 15465 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5772 /* 15469 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5773 /* 15474 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5774 /* 15476 */ // (sub:{ *:[v8i16] } (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5775 /* 15476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5776 /* 15479 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5777 /* 15481 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5778 /* 15485 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5779 /* 15489 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5780 /* 15492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5781 /* 15498 */ GIR_RootConstrainSelectedInstOperands,
5782 /* 15499 */ // GIR_Coverage, 1138,
5783 /* 15499 */ GIR_EraseRootFromParent_Done,
5784 /* 15500 */ // Label 327: @15500
5785 /* 15500 */ GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(15572), // Rule ID 1133 //
5786 /* 15505 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5787 /* 15508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5788 /* 15512 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5789 /* 15516 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5790 /* 15520 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5791 /* 15524 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5792 /* 15529 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5793 /* 15533 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT),
5794 /* 15537 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5795 /* 15541 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5796 /* 15546 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5797 /* 15548 */ // (sub:{ *:[v8i16] } (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5798 /* 15548 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLsv8i16),
5799 /* 15551 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5800 /* 15553 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5801 /* 15557 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5802 /* 15561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5803 /* 15564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5804 /* 15570 */ GIR_RootConstrainSelectedInstOperands,
5805 /* 15571 */ // GIR_Coverage, 1133,
5806 /* 15571 */ GIR_EraseRootFromParent_Done,
5807 /* 15572 */ // Label 328: @15572
5808 /* 15572 */ GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(15644), // Rule ID 1137 //
5809 /* 15577 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5810 /* 15580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5811 /* 15584 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5812 /* 15588 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5813 /* 15592 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5814 /* 15596 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5815 /* 15601 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5816 /* 15605 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5817 /* 15609 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5818 /* 15613 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5819 /* 15618 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5820 /* 15620 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5821 /* 15620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5822 /* 15623 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5823 /* 15625 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5824 /* 15629 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5825 /* 15633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5826 /* 15636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5827 /* 15642 */ GIR_RootConstrainSelectedInstOperands,
5828 /* 15643 */ // GIR_Coverage, 1137,
5829 /* 15643 */ GIR_EraseRootFromParent_Done,
5830 /* 15644 */ // Label 329: @15644
5831 /* 15644 */ GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(15716), // Rule ID 1136 //
5832 /* 15649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5833 /* 15652 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5834 /* 15656 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
5835 /* 15660 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5836 /* 15664 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5837 /* 15668 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5838 /* 15673 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
5839 /* 15677 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ZEXT),
5840 /* 15681 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s8,
5841 /* 15685 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5842 /* 15690 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
5843 /* 15692 */ // (sub:{ *:[v8i16] } (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn), (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5844 /* 15692 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBLuv8i16),
5845 /* 15695 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5846 /* 15697 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5847 /* 15701 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Vm
5848 /* 15705 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5849 /* 15708 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5850 /* 15714 */ GIR_RootConstrainSelectedInstOperands,
5851 /* 15715 */ // GIR_Coverage, 1136,
5852 /* 15715 */ GIR_EraseRootFromParent_Done,
5853 /* 15716 */ // Label 330: @15716
5854 /* 15716 */ GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(15786), // Rule ID 1056 //
5855 /* 15721 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5856 /* 15724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5857 /* 15728 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5858 /* 15732 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5859 /* 15736 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5860 /* 15740 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
5861 /* 15744 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
5862 /* 15748 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5863 /* 15753 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5864 /* 15758 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5865 /* 15760 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)) => (VMLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
5866 /* 15760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv8i16),
5867 /* 15763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5868 /* 15765 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5869 /* 15767 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5870 /* 15771 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5871 /* 15775 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5872 /* 15778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5873 /* 15784 */ GIR_RootConstrainSelectedInstOperands,
5874 /* 15785 */ // GIR_Coverage, 1056,
5875 /* 15785 */ GIR_EraseRootFromParent_Done,
5876 /* 15786 */ // Label 331: @15786
5877 /* 15786 */ GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(15843), // Rule ID 1152 //
5878 /* 15791 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5879 /* 15794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5880 /* 15798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5881 /* 15802 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5882 /* 15806 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ANYEXT),
5883 /* 15810 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5884 /* 15814 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5885 /* 15819 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5886 /* 15821 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5887 /* 15821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16),
5888 /* 15824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5889 /* 15826 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5890 /* 15828 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5891 /* 15832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5892 /* 15835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5893 /* 15841 */ GIR_RootConstrainSelectedInstOperands,
5894 /* 15842 */ // GIR_Coverage, 1152,
5895 /* 15842 */ GIR_EraseRootFromParent_Done,
5896 /* 15843 */ // Label 332: @15843
5897 /* 15843 */ GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(15900), // Rule ID 1148 //
5898 /* 15848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5899 /* 15851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5900 /* 15855 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5901 /* 15859 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5902 /* 15863 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT),
5903 /* 15867 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5904 /* 15871 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5905 /* 15876 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5906 /* 15878 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5907 /* 15878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWsv8i16),
5908 /* 15881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5909 /* 15883 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5910 /* 15885 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5911 /* 15889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5912 /* 15892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5913 /* 15898 */ GIR_RootConstrainSelectedInstOperands,
5914 /* 15899 */ // GIR_Coverage, 1148,
5915 /* 15899 */ GIR_EraseRootFromParent_Done,
5916 /* 15900 */ // Label 333: @15900
5917 /* 15900 */ GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(15957), // Rule ID 1151 //
5918 /* 15905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5919 /* 15908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5920 /* 15912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5921 /* 15916 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5922 /* 15920 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ZEXT),
5923 /* 15924 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
5924 /* 15928 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
5925 /* 15933 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5926 /* 15935 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)) => (VSUBWuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
5927 /* 15935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBWuv8i16),
5928 /* 15938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5929 /* 15940 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5930 /* 15942 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vm
5931 /* 15946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5932 /* 15949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5933 /* 15955 */ GIR_RootConstrainSelectedInstOperands,
5934 /* 15956 */ // GIR_Coverage, 1151,
5935 /* 15956 */ GIR_EraseRootFromParent_Done,
5936 /* 15957 */ // Label 334: @15957
5937 /* 15957 */ GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(15997), // Rule ID 1125 //
5938 /* 15962 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5939 /* 15965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5940 /* 15969 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5941 /* 15973 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5942 /* 15977 */ // (sub:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VSUBv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
5943 /* 15977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv8i16),
5944 /* 15980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5945 /* 15982 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
5946 /* 15984 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
5947 /* 15986 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5948 /* 15989 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5949 /* 15995 */ GIR_RootConstrainSelectedInstOperands,
5950 /* 15996 */ // GIR_Coverage, 1125,
5951 /* 15996 */ GIR_EraseRootFromParent_Done,
5952 /* 15997 */ // Label 335: @15997
5953 /* 15997 */ GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(16058), // Rule ID 3862 //
5954 /* 16002 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
5955 /* 16005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5956 /* 16009 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5957 /* 16013 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
5958 /* 16017 */ // (sub:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VSUBi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
5959 /* 16017 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
5960 /* 16020 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
5961 /* 16024 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
5962 /* 16029 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi16),
5963 /* 16032 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
5964 /* 16034 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
5965 /* 16036 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
5966 /* 16038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
5967 /* 16041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5968 /* 16047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
5969 /* 16053 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
5970 /* 16056 */ GIR_RootConstrainSelectedInstOperands,
5971 /* 16057 */ // GIR_Coverage, 3862,
5972 /* 16057 */ GIR_EraseRootFromParent_Done,
5973 /* 16058 */ // Label 336: @16058
5974 /* 16058 */ GIM_Reject,
5975 /* 16059 */ // Label 325: @16059
5976 /* 16059 */ GIM_Reject,
5977 /* 16060 */ // Label 279: @16060
5978 /* 16060 */ GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(16243),
5979 /* 16065 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
5980 /* 16068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
5981 /* 16071 */ GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(16141), // Rule ID 1055 //
5982 /* 16076 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
5983 /* 16079 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5984 /* 16083 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5985 /* 16087 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
5986 /* 16091 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
5987 /* 16095 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
5988 /* 16099 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
5989 /* 16103 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5990 /* 16108 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
5991 /* 16113 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
5992 /* 16115 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)) => (VMLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src1, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
5993 /* 16115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLSv16i8),
5994 /* 16118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
5995 /* 16120 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
5996 /* 16122 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
5997 /* 16126 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
5998 /* 16130 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
5999 /* 16133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6000 /* 16139 */ GIR_RootConstrainSelectedInstOperands,
6001 /* 16140 */ // GIR_Coverage, 1055,
6002 /* 16140 */ GIR_EraseRootFromParent_Done,
6003 /* 16141 */ // Label 338: @16141
6004 /* 16141 */ GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(16181), // Rule ID 1124 //
6005 /* 16146 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6006 /* 16149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6007 /* 16153 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6008 /* 16157 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6009 /* 16161 */ // (sub:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSUBv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
6010 /* 16161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBv16i8),
6011 /* 16164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6012 /* 16166 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6013 /* 16168 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6014 /* 16170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6015 /* 16173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6016 /* 16179 */ GIR_RootConstrainSelectedInstOperands,
6017 /* 16180 */ // GIR_Coverage, 1124,
6018 /* 16180 */ GIR_EraseRootFromParent_Done,
6019 /* 16181 */ // Label 339: @16181
6020 /* 16181 */ GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(16242), // Rule ID 3858 //
6021 /* 16186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6022 /* 16189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6023 /* 16193 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6024 /* 16197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6025 /* 16201 */ // (sub:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VSUBi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
6026 /* 16201 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6027 /* 16204 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6028 /* 16208 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6029 /* 16213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBi8),
6030 /* 16216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6031 /* 16218 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
6032 /* 16220 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
6033 /* 16222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6034 /* 16225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6035 /* 16231 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6036 /* 16237 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6037 /* 16240 */ GIR_RootConstrainSelectedInstOperands,
6038 /* 16241 */ // GIR_Coverage, 3858,
6039 /* 16241 */ GIR_EraseRootFromParent_Done,
6040 /* 16242 */ // Label 340: @16242
6041 /* 16242 */ GIM_Reject,
6042 /* 16243 */ // Label 337: @16243
6043 /* 16243 */ GIM_Reject,
6044 /* 16244 */ // Label 280: @16244
6045 /* 16244 */ GIM_Reject,
6046 /* 16245 */ // Label 2: @16245
6047 /* 16245 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 348*/ GIMT_Encode4(17948),
6048 /* 16256 */ /*GILLT_s32*//*Label 341*/ GIMT_Encode4(16316), GIMT_Encode4(0), GIMT_Encode4(0),
6049 /* 16268 */ /*GILLT_v2s32*//*Label 342*/ GIMT_Encode4(17235), GIMT_Encode4(0), GIMT_Encode4(0),
6050 /* 16280 */ /*GILLT_v4s16*//*Label 343*/ GIMT_Encode4(17282),
6051 /* 16284 */ /*GILLT_v4s32*//*Label 344*/ GIMT_Encode4(17329), GIMT_Encode4(0), GIMT_Encode4(0),
6052 /* 16296 */ /*GILLT_v8s8*//*Label 345*/ GIMT_Encode4(17558),
6053 /* 16300 */ /*GILLT_v8s16*//*Label 346*/ GIMT_Encode4(17605), GIMT_Encode4(0), GIMT_Encode4(0),
6054 /* 16312 */ /*GILLT_v16s8*//*Label 347*/ GIMT_Encode4(17834),
6055 /* 16316 */ // Label 341: @16316
6056 /* 16316 */ GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(17234),
6057 /* 16321 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
6058 /* 16324 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6059 /* 16327 */ GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(16415), // Rule ID 185 //
6060 /* 16332 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
6061 /* 16335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6062 /* 16339 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6063 /* 16343 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
6064 /* 16347 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6065 /* 16351 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6066 /* 16355 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6067 /* 16360 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
6068 /* 16364 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6069 /* 16368 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
6070 /* 16372 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6071 /* 16376 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6072 /* 16380 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6073 /* 16385 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
6074 /* 16389 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6075 /* 16391 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6076 /* 16391 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT),
6077 /* 16394 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6078 /* 16396 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6079 /* 16400 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6080 /* 16404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6081 /* 16407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6082 /* 16413 */ GIR_RootConstrainSelectedInstOperands,
6083 /* 16414 */ // GIR_Coverage, 185,
6084 /* 16414 */ GIR_EraseRootFromParent_Done,
6085 /* 16415 */ // Label 350: @16415
6086 /* 16415 */ GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(16503), // Rule ID 514 //
6087 /* 16420 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
6088 /* 16423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6089 /* 16427 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6090 /* 16431 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
6091 /* 16435 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6092 /* 16439 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6093 /* 16443 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6094 /* 16448 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
6095 /* 16452 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6096 /* 16456 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
6097 /* 16460 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6098 /* 16464 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6099 /* 16468 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6100 /* 16473 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
6101 /* 16477 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6102 /* 16479 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6103 /* 16479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT),
6104 /* 16482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6105 /* 16484 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6106 /* 16488 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6107 /* 16492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6108 /* 16495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6109 /* 16501 */ GIR_RootConstrainSelectedInstOperands,
6110 /* 16502 */ // GIR_Coverage, 514,
6111 /* 16502 */ GIR_EraseRootFromParent_Done,
6112 /* 16503 */ // Label 351: @16503
6113 /* 16503 */ GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(16594), // Rule ID 184 //
6114 /* 16508 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
6115 /* 16511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6116 /* 16515 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6117 /* 16519 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
6118 /* 16523 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6119 /* 16527 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6120 /* 16531 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6121 /* 16536 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
6122 /* 16540 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6123 /* 16544 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6124 /* 16548 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6125 /* 16552 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6126 /* 16557 */ // MIs[2] Operand 2
6127 /* 16557 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6128 /* 16568 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6129 /* 16570 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6130 /* 16570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB),
6131 /* 16573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6132 /* 16575 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6133 /* 16579 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6134 /* 16583 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6135 /* 16586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6136 /* 16592 */ GIR_RootConstrainSelectedInstOperands,
6137 /* 16593 */ // GIR_Coverage, 184,
6138 /* 16593 */ GIR_EraseRootFromParent_Done,
6139 /* 16594 */ // Label 352: @16594
6140 /* 16594 */ GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(16685), // Rule ID 513 //
6141 /* 16599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
6142 /* 16602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6143 /* 16606 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6144 /* 16610 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
6145 /* 16614 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6146 /* 16618 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6147 /* 16622 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6148 /* 16627 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
6149 /* 16631 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6150 /* 16635 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6151 /* 16639 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6152 /* 16643 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6153 /* 16648 */ // MIs[2] Operand 2
6154 /* 16648 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6155 /* 16659 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6156 /* 16661 */ // (mul:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 16:{ *:[i32] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6157 /* 16661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB),
6158 /* 16664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6159 /* 16666 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6160 /* 16670 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6161 /* 16674 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6162 /* 16677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6163 /* 16683 */ GIR_RootConstrainSelectedInstOperands,
6164 /* 16684 */ // GIR_Coverage, 513,
6165 /* 16684 */ GIR_EraseRootFromParent_Done,
6166 /* 16685 */ // Label 353: @16685
6167 /* 16685 */ GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(16776), // Rule ID 183 //
6168 /* 16690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
6169 /* 16693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6170 /* 16697 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6171 /* 16701 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6172 /* 16705 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6173 /* 16709 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6174 /* 16714 */ // MIs[1] Operand 2
6175 /* 16714 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6176 /* 16725 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6177 /* 16729 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
6178 /* 16733 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6179 /* 16737 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6180 /* 16741 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6181 /* 16746 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
6182 /* 16750 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6183 /* 16752 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6184 /* 16752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT),
6185 /* 16755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6186 /* 16757 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6187 /* 16761 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6188 /* 16765 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6189 /* 16768 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6190 /* 16774 */ GIR_RootConstrainSelectedInstOperands,
6191 /* 16775 */ // GIR_Coverage, 183,
6192 /* 16775 */ GIR_EraseRootFromParent_Done,
6193 /* 16776 */ // Label 354: @16776
6194 /* 16776 */ GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(16867), // Rule ID 512 //
6195 /* 16781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
6196 /* 16784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6197 /* 16788 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6198 /* 16792 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6199 /* 16796 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6200 /* 16800 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6201 /* 16805 */ // MIs[1] Operand 2
6202 /* 16805 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6203 /* 16816 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6204 /* 16820 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
6205 /* 16824 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6206 /* 16828 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
6207 /* 16832 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6208 /* 16837 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16,
6209 /* 16841 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6210 /* 16843 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16:{ *:[i32] })) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6211 /* 16843 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT),
6212 /* 16846 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6213 /* 16848 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6214 /* 16852 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6215 /* 16856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6216 /* 16859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6217 /* 16865 */ GIR_RootConstrainSelectedInstOperands,
6218 /* 16866 */ // GIR_Coverage, 512,
6219 /* 16866 */ GIR_EraseRootFromParent_Done,
6220 /* 16867 */ // Label 355: @16867
6221 /* 16867 */ GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(16961), // Rule ID 182 //
6222 /* 16872 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
6223 /* 16875 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6224 /* 16879 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6225 /* 16883 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6226 /* 16887 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6227 /* 16891 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6228 /* 16896 */ // MIs[1] Operand 2
6229 /* 16896 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6230 /* 16907 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6231 /* 16911 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6232 /* 16915 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6233 /* 16919 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6234 /* 16924 */ // MIs[2] Operand 2
6235 /* 16924 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6236 /* 16935 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6237 /* 16937 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6238 /* 16937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB),
6239 /* 16940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6240 /* 16942 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6241 /* 16946 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6242 /* 16950 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6243 /* 16953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6244 /* 16959 */ GIR_RootConstrainSelectedInstOperands,
6245 /* 16960 */ // GIR_Coverage, 182,
6246 /* 16960 */ GIR_EraseRootFromParent_Done,
6247 /* 16961 */ // Label 356: @16961
6248 /* 16961 */ GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(17055), // Rule ID 511 //
6249 /* 16966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
6250 /* 16969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6251 /* 16973 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6252 /* 16977 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6253 /* 16981 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6254 /* 16985 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6255 /* 16990 */ // MIs[1] Operand 2
6256 /* 16990 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6257 /* 17001 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6258 /* 17005 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6259 /* 17009 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
6260 /* 17013 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6261 /* 17018 */ // MIs[2] Operand 2
6262 /* 17018 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6263 /* 17029 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6264 /* 17031 */ // (mul:{ *:[i32] } (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, i16:{ *:[Other] }), (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] })) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6265 /* 17031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB),
6266 /* 17034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6267 /* 17036 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
6268 /* 17040 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
6269 /* 17044 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6270 /* 17047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6271 /* 17053 */ GIR_RootConstrainSelectedInstOperands,
6272 /* 17054 */ // GIR_Coverage, 511,
6273 /* 17054 */ GIR_EraseRootFromParent_Done,
6274 /* 17055 */ // Label 357: @17055
6275 /* 17055 */ GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(17101), // Rule ID 168 //
6276 /* 17060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
6277 /* 17063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6278 /* 17067 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6279 /* 17071 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6280 /* 17075 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MUL:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
6281 /* 17075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MUL),
6282 /* 17078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6283 /* 17080 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6284 /* 17082 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6285 /* 17084 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6286 /* 17087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6287 /* 17093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6288 /* 17099 */ GIR_RootConstrainSelectedInstOperands,
6289 /* 17100 */ // GIR_Coverage, 168,
6290 /* 17100 */ GIR_EraseRootFromParent_Done,
6291 /* 17101 */ // Label 358: @17101
6292 /* 17101 */ GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(17147), // Rule ID 169 //
6293 /* 17106 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV6_UseMulOps),
6294 /* 17109 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6295 /* 17113 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6296 /* 17117 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6297 /* 17121 */ // (mul:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (MULv5:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
6298 /* 17121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MULv5),
6299 /* 17124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6300 /* 17126 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6301 /* 17128 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6302 /* 17130 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6303 /* 17133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6304 /* 17139 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6305 /* 17145 */ GIR_RootConstrainSelectedInstOperands,
6306 /* 17146 */ // GIR_Coverage, 169,
6307 /* 17146 */ GIR_EraseRootFromParent_Done,
6308 /* 17147 */ // Label 359: @17147
6309 /* 17147 */ GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(17193), // Rule ID 322 //
6310 /* 17152 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
6311 /* 17155 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6312 /* 17159 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6313 /* 17163 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
6314 /* 17167 */ // (mul:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tMUL:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
6315 /* 17167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMUL),
6316 /* 17170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6317 /* 17172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
6318 /* 17178 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6319 /* 17180 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6320 /* 17182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6321 /* 17185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6322 /* 17191 */ GIR_RootConstrainSelectedInstOperands,
6323 /* 17192 */ // GIR_Coverage, 322,
6324 /* 17192 */ GIR_EraseRootFromParent_Done,
6325 /* 17193 */ // Label 360: @17193
6326 /* 17193 */ GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(17233), // Rule ID 501 //
6327 /* 17198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6328 /* 17201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6329 /* 17205 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6330 /* 17209 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6331 /* 17213 */ // (mul:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2MUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6332 /* 17213 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MUL),
6333 /* 17216 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6334 /* 17218 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6335 /* 17220 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6336 /* 17222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6337 /* 17225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6338 /* 17231 */ GIR_RootConstrainSelectedInstOperands,
6339 /* 17232 */ // GIR_Coverage, 501,
6340 /* 17232 */ GIR_EraseRootFromParent_Done,
6341 /* 17233 */ // Label 361: @17233
6342 /* 17233 */ GIM_Reject,
6343 /* 17234 */ // Label 349: @17234
6344 /* 17234 */ GIM_Reject,
6345 /* 17235 */ // Label 342: @17235
6346 /* 17235 */ GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(17281), // Rule ID 956 //
6347 /* 17240 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6348 /* 17243 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
6349 /* 17246 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
6350 /* 17249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6351 /* 17253 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6352 /* 17257 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6353 /* 17261 */ // (mul:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMULv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
6354 /* 17261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv2i32),
6355 /* 17264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6356 /* 17266 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6357 /* 17268 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6358 /* 17270 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6359 /* 17273 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6360 /* 17279 */ GIR_RootConstrainSelectedInstOperands,
6361 /* 17280 */ // GIR_Coverage, 956,
6362 /* 17280 */ GIR_EraseRootFromParent_Done,
6363 /* 17281 */ // Label 362: @17281
6364 /* 17281 */ GIM_Reject,
6365 /* 17282 */ // Label 343: @17282
6366 /* 17282 */ GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(17328), // Rule ID 955 //
6367 /* 17287 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6368 /* 17290 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
6369 /* 17293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
6370 /* 17296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6371 /* 17300 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6372 /* 17304 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6373 /* 17308 */ // (mul:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMULv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
6374 /* 17308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i16),
6375 /* 17311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6376 /* 17313 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6377 /* 17315 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6378 /* 17317 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6379 /* 17320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6380 /* 17326 */ GIR_RootConstrainSelectedInstOperands,
6381 /* 17327 */ // GIR_Coverage, 955,
6382 /* 17327 */ GIR_EraseRootFromParent_Done,
6383 /* 17328 */ // Label 363: @17328
6384 /* 17328 */ GIM_Reject,
6385 /* 17329 */ // Label 344: @17329
6386 /* 17329 */ GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(17557),
6387 /* 17334 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
6388 /* 17337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
6389 /* 17340 */ GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(17455), // Rule ID 4875 //
6390 /* 17345 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6391 /* 17348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6392 /* 17352 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6393 /* 17356 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6394 /* 17360 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
6395 /* 17364 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6396 /* 17369 */ // MIs[1] Operand 2
6397 /* 17369 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(16),
6398 /* 17380 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6399 /* 17384 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6400 /* 17388 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
6401 /* 17392 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6402 /* 17397 */ // MIs[2] Operand 2
6403 /* 17397 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(16),
6404 /* 17408 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6405 /* 17410 */ // (mul:{ *:[v4i32] } (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, v4i16:{ *:[Other] }), (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src2, v4i16:{ *:[Other] })) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)
6406 /* 17410 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6407 /* 17413 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6408 /* 17417 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6409 /* 17422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16),
6410 /* 17425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6411 /* 17427 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6412 /* 17431 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6413 /* 17435 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6414 /* 17438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6415 /* 17444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6416 /* 17450 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6417 /* 17453 */ GIR_RootConstrainSelectedInstOperands,
6418 /* 17454 */ // GIR_Coverage, 4875,
6419 /* 17454 */ GIR_EraseRootFromParent_Done,
6420 /* 17455 */ // Label 365: @17455
6421 /* 17455 */ GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(17495), // Rule ID 959 //
6422 /* 17460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6423 /* 17463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6424 /* 17467 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6425 /* 17471 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6426 /* 17475 */ // (mul:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMULv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
6427 /* 17475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv4i32),
6428 /* 17478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6429 /* 17480 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6430 /* 17482 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6431 /* 17484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6432 /* 17487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6433 /* 17493 */ GIR_RootConstrainSelectedInstOperands,
6434 /* 17494 */ // GIR_Coverage, 959,
6435 /* 17494 */ GIR_EraseRootFromParent_Done,
6436 /* 17495 */ // Label 366: @17495
6437 /* 17495 */ GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(17556), // Rule ID 3824 //
6438 /* 17500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6439 /* 17503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6440 /* 17507 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6441 /* 17511 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6442 /* 17515 */ // (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
6443 /* 17515 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6444 /* 17518 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6445 /* 17522 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6446 /* 17527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi32),
6447 /* 17530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6448 /* 17532 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
6449 /* 17534 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
6450 /* 17536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6451 /* 17539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6452 /* 17545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6453 /* 17551 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6454 /* 17554 */ GIR_RootConstrainSelectedInstOperands,
6455 /* 17555 */ // GIR_Coverage, 3824,
6456 /* 17555 */ GIR_EraseRootFromParent_Done,
6457 /* 17556 */ // Label 367: @17556
6458 /* 17556 */ GIM_Reject,
6459 /* 17557 */ // Label 364: @17557
6460 /* 17557 */ GIM_Reject,
6461 /* 17558 */ // Label 345: @17558
6462 /* 17558 */ GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(17604), // Rule ID 954 //
6463 /* 17563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6464 /* 17566 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
6465 /* 17569 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
6466 /* 17572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6467 /* 17576 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6468 /* 17580 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
6469 /* 17584 */ // (mul:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
6470 /* 17584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i8),
6471 /* 17587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6472 /* 17589 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6473 /* 17591 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6474 /* 17593 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6475 /* 17596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6476 /* 17602 */ GIR_RootConstrainSelectedInstOperands,
6477 /* 17603 */ // GIR_Coverage, 954,
6478 /* 17603 */ GIR_EraseRootFromParent_Done,
6479 /* 17604 */ // Label 368: @17604
6480 /* 17604 */ GIM_Reject,
6481 /* 17605 */ // Label 346: @17605
6482 /* 17605 */ GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(17833),
6483 /* 17610 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
6484 /* 17613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
6485 /* 17616 */ GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(17731), // Rule ID 4880 //
6486 /* 17621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6487 /* 17624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6488 /* 17628 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6489 /* 17632 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6490 /* 17636 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
6491 /* 17640 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6492 /* 17645 */ // MIs[1] Operand 2
6493 /* 17645 */ GIM_CheckLiteralInt, /*MI*/1, /*Op*/2, GIMT_Encode8(8),
6494 /* 17656 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
6495 /* 17660 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SEXT_INREG),
6496 /* 17664 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
6497 /* 17668 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6498 /* 17673 */ // MIs[2] Operand 2
6499 /* 17673 */ GIM_CheckLiteralInt, /*MI*/2, /*Op*/2, GIMT_Encode8(8),
6500 /* 17684 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6501 /* 17686 */ // (mul:{ *:[v8i16] } (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, v8i8:{ *:[Other] }), (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src2, v8i8:{ *:[Other] })) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)
6502 /* 17686 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6503 /* 17689 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6504 /* 17693 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6505 /* 17698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8),
6506 /* 17701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6507 /* 17703 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
6508 /* 17707 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
6509 /* 17711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6510 /* 17714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6511 /* 17720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6512 /* 17726 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6513 /* 17729 */ GIR_RootConstrainSelectedInstOperands,
6514 /* 17730 */ // GIR_Coverage, 4880,
6515 /* 17730 */ GIR_EraseRootFromParent_Done,
6516 /* 17731 */ // Label 370: @17731
6517 /* 17731 */ GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(17771), // Rule ID 958 //
6518 /* 17736 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6519 /* 17739 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6520 /* 17743 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6521 /* 17747 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6522 /* 17751 */ // (mul:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMULv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
6523 /* 17751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv8i16),
6524 /* 17754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6525 /* 17756 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6526 /* 17758 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6527 /* 17760 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6528 /* 17763 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6529 /* 17769 */ GIR_RootConstrainSelectedInstOperands,
6530 /* 17770 */ // GIR_Coverage, 958,
6531 /* 17770 */ GIR_EraseRootFromParent_Done,
6532 /* 17771 */ // Label 371: @17771
6533 /* 17771 */ GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(17832), // Rule ID 3820 //
6534 /* 17776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6535 /* 17779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6536 /* 17783 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6537 /* 17787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6538 /* 17791 */ // (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
6539 /* 17791 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6540 /* 17794 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6541 /* 17798 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6542 /* 17803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi16),
6543 /* 17806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6544 /* 17808 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
6545 /* 17810 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
6546 /* 17812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6547 /* 17815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6548 /* 17821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6549 /* 17827 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6550 /* 17830 */ GIR_RootConstrainSelectedInstOperands,
6551 /* 17831 */ // GIR_Coverage, 3820,
6552 /* 17831 */ GIR_EraseRootFromParent_Done,
6553 /* 17832 */ // Label 372: @17832
6554 /* 17832 */ GIM_Reject,
6555 /* 17833 */ // Label 369: @17833
6556 /* 17833 */ GIM_Reject,
6557 /* 17834 */ // Label 347: @17834
6558 /* 17834 */ GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(17947),
6559 /* 17839 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
6560 /* 17842 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
6561 /* 17845 */ GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(17885), // Rule ID 957 //
6562 /* 17850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
6563 /* 17853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6564 /* 17857 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6565 /* 17861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
6566 /* 17865 */ // (mul:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
6567 /* 17865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULv16i8),
6568 /* 17868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
6569 /* 17870 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
6570 /* 17872 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
6571 /* 17874 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6572 /* 17877 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6573 /* 17883 */ GIR_RootConstrainSelectedInstOperands,
6574 /* 17884 */ // GIR_Coverage, 957,
6575 /* 17884 */ GIR_EraseRootFromParent_Done,
6576 /* 17885 */ // Label 374: @17885
6577 /* 17885 */ GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(17946), // Rule ID 3816 //
6578 /* 17890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
6579 /* 17893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6580 /* 17897 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6581 /* 17901 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
6582 /* 17905 */ // (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
6583 /* 17905 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
6584 /* 17908 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
6585 /* 17912 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
6586 /* 17917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULi8),
6587 /* 17920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
6588 /* 17922 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
6589 /* 17924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
6590 /* 17926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6591 /* 17929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6592 /* 17935 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6593 /* 17941 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
6594 /* 17944 */ GIR_RootConstrainSelectedInstOperands,
6595 /* 17945 */ // GIR_Coverage, 3816,
6596 /* 17945 */ GIR_EraseRootFromParent_Done,
6597 /* 17946 */ // Label 375: @17946
6598 /* 17946 */ GIM_Reject,
6599 /* 17947 */ // Label 373: @17947
6600 /* 17947 */ GIM_Reject,
6601 /* 17948 */ // Label 348: @17948
6602 /* 17948 */ GIM_Reject,
6603 /* 17949 */ // Label 3: @17949
6604 /* 17949 */ GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(18044),
6605 /* 17954 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
6606 /* 17957 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
6607 /* 17960 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6608 /* 17963 */ GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(18003), // Rule ID 194 //
6609 /* 17968 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInARM_IsARM),
6610 /* 17971 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6611 /* 17975 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6612 /* 17979 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6613 /* 17983 */ // (sdiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6614 /* 17983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SDIV),
6615 /* 17986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6616 /* 17988 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6617 /* 17990 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6618 /* 17992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6619 /* 17995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6620 /* 18001 */ GIR_RootConstrainSelectedInstOperands,
6621 /* 18002 */ // GIR_Coverage, 194,
6622 /* 18002 */ GIR_EraseRootFromParent_Done,
6623 /* 18003 */ // Label 377: @18003
6624 /* 18003 */ GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(18043), // Rule ID 531 //
6625 /* 18008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb),
6626 /* 18011 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6627 /* 18015 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6628 /* 18019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6629 /* 18023 */ // (sdiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6630 /* 18023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SDIV),
6631 /* 18026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6632 /* 18028 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6633 /* 18030 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6634 /* 18032 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6635 /* 18035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6636 /* 18041 */ GIR_RootConstrainSelectedInstOperands,
6637 /* 18042 */ // GIR_Coverage, 531,
6638 /* 18042 */ GIR_EraseRootFromParent_Done,
6639 /* 18043 */ // Label 378: @18043
6640 /* 18043 */ GIM_Reject,
6641 /* 18044 */ // Label 376: @18044
6642 /* 18044 */ GIM_Reject,
6643 /* 18045 */ // Label 4: @18045
6644 /* 18045 */ GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(18140),
6645 /* 18050 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
6646 /* 18053 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
6647 /* 18056 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6648 /* 18059 */ GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(18099), // Rule ID 195 //
6649 /* 18064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInARM_IsARM),
6650 /* 18067 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6651 /* 18071 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6652 /* 18075 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6653 /* 18079 */ // (udiv:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (UDIV:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
6654 /* 18079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDIV),
6655 /* 18082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6656 /* 18084 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6657 /* 18086 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6658 /* 18088 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6659 /* 18091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6660 /* 18097 */ GIR_RootConstrainSelectedInstOperands,
6661 /* 18098 */ // GIR_Coverage, 195,
6662 /* 18098 */ GIR_EraseRootFromParent_Done,
6663 /* 18099 */ // Label 380: @18099
6664 /* 18099 */ GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(18139), // Rule ID 532 //
6665 /* 18104 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDivideInThumb_HasV8MBaseline_IsThumb),
6666 /* 18107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6667 /* 18111 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6668 /* 18115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6669 /* 18119 */ // (udiv:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UDIV:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
6670 /* 18119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDIV),
6671 /* 18122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6672 /* 18124 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6673 /* 18126 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
6674 /* 18128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6675 /* 18131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6676 /* 18137 */ GIR_RootConstrainSelectedInstOperands,
6677 /* 18138 */ // GIR_Coverage, 532,
6678 /* 18138 */ GIR_EraseRootFromParent_Done,
6679 /* 18139 */ // Label 381: @18139
6680 /* 18139 */ GIM_Reject,
6681 /* 18140 */ // Label 379: @18140
6682 /* 18140 */ GIM_Reject,
6683 /* 18141 */ // Label 5: @18141
6684 /* 18141 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 395*/ GIMT_Encode4(21320),
6685 /* 18152 */ /*GILLT_s32*//*Label 382*/ GIMT_Encode4(18212),
6686 /* 18156 */ /*GILLT_s64*//*Label 383*/ GIMT_Encode4(20204),
6687 /* 18160 */ /*GILLT_v2s1*//*Label 384*/ GIMT_Encode4(20251),
6688 /* 18164 */ /*GILLT_v2s32*//*Label 385*/ GIMT_Encode4(20369),
6689 /* 18168 */ /*GILLT_v2s64*//*Label 386*/ GIMT_Encode4(20416),
6690 /* 18172 */ /*GILLT_v4s1*//*Label 387*/ GIMT_Encode4(20530),
6691 /* 18176 */ /*GILLT_v4s16*//*Label 388*/ GIMT_Encode4(20648),
6692 /* 18180 */ /*GILLT_v4s32*//*Label 389*/ GIMT_Encode4(20695), GIMT_Encode4(0),
6693 /* 18188 */ /*GILLT_v8s1*//*Label 390*/ GIMT_Encode4(20809),
6694 /* 18192 */ /*GILLT_v8s8*//*Label 391*/ GIMT_Encode4(20927),
6695 /* 18196 */ /*GILLT_v8s16*//*Label 392*/ GIMT_Encode4(20974), GIMT_Encode4(0),
6696 /* 18204 */ /*GILLT_v16s1*//*Label 393*/ GIMT_Encode4(21088),
6697 /* 18208 */ /*GILLT_v16s8*//*Label 394*/ GIMT_Encode4(21206),
6698 /* 18212 */ // Label 382: @18212
6699 /* 18212 */ GIM_Try, /*On fail goto*//*Label 396*/ GIMT_Encode4(20203),
6700 /* 18217 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
6701 /* 18220 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
6702 /* 18223 */ GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(18296), // Rule ID 2016 //
6703 /* 18228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
6704 /* 18231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6705 /* 18235 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6706 /* 18239 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
6707 /* 18243 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6708 /* 18247 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6709 /* 18251 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6710 /* 18256 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8,
6711 /* 18260 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6712 /* 18271 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6713 /* 18273 */ // (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
6714 /* 18273 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16),
6715 /* 18276 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6716 /* 18278 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
6717 /* 18282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
6718 /* 18285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6719 /* 18288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6720 /* 18294 */ GIR_RootConstrainSelectedInstOperands,
6721 /* 18295 */ // GIR_Coverage, 2016,
6722 /* 18295 */ GIR_EraseRootFromParent_Done,
6723 /* 18296 */ // Label 397: @18296
6724 /* 18296 */ GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(18369), // Rule ID 2273 //
6725 /* 18301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
6726 /* 18304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6727 /* 18308 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6728 /* 18312 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
6729 /* 18316 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6730 /* 18320 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6731 /* 18324 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6732 /* 18329 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 8,
6733 /* 18333 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6734 /* 18344 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
6735 /* 18346 */ // (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 8:{ *:[i32] }), 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 1:{ *:[i32] })
6736 /* 18346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16),
6737 /* 18349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6738 /* 18351 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Src
6739 /* 18355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
6740 /* 18358 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6741 /* 18361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6742 /* 18367 */ GIR_RootConstrainSelectedInstOperands,
6743 /* 18368 */ // GIR_Coverage, 2273,
6744 /* 18368 */ GIR_EraseRootFromParent_Done,
6745 /* 18369 */ // Label 398: @18369
6746 /* 18369 */ GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(18417), // Rule ID 2158 //
6747 /* 18374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
6748 /* 18377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6749 /* 18381 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6750 /* 18385 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
6751 /* 18396 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 255:{ *:[i32] }) => (UXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
6752 /* 18396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB),
6753 /* 18399 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6754 /* 18401 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
6755 /* 18403 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6756 /* 18406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6757 /* 18409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6758 /* 18415 */ GIR_RootConstrainSelectedInstOperands,
6759 /* 18416 */ // GIR_Coverage, 2158,
6760 /* 18416 */ GIR_EraseRootFromParent_Done,
6761 /* 18417 */ // Label 399: @18417
6762 /* 18417 */ GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(18465), // Rule ID 2159 //
6763 /* 18422 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
6764 /* 18425 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6765 /* 18429 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6766 /* 18433 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
6767 /* 18444 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 65535:{ *:[i32] }) => (UXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
6768 /* 18444 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTH),
6769 /* 18447 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6770 /* 18449 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
6771 /* 18451 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6772 /* 18454 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6773 /* 18457 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6774 /* 18463 */ GIR_RootConstrainSelectedInstOperands,
6775 /* 18464 */ // GIR_Coverage, 2159,
6776 /* 18464 */ GIR_EraseRootFromParent_Done,
6777 /* 18465 */ // Label 400: @18465
6778 /* 18465 */ GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(18513), // Rule ID 2160 //
6779 /* 18470 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
6780 /* 18473 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
6781 /* 18477 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6782 /* 18481 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6783 /* 18492 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Src, 16711935:{ *:[i32] }) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
6784 /* 18492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16),
6785 /* 18495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6786 /* 18497 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
6787 /* 18499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6788 /* 18502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6789 /* 18505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6790 /* 18511 */ GIR_RootConstrainSelectedInstOperands,
6791 /* 18512 */ // GIR_Coverage, 2160,
6792 /* 18512 */ GIR_EraseRootFromParent_Done,
6793 /* 18513 */ // Label 401: @18513
6794 /* 18513 */ GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(18561), // Rule ID 2397 //
6795 /* 18518 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6796 /* 18521 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6797 /* 18525 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6798 /* 18529 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
6799 /* 18540 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (t2UXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
6800 /* 18540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB),
6801 /* 18543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6802 /* 18545 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6803 /* 18547 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6804 /* 18550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6805 /* 18553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6806 /* 18559 */ GIR_RootConstrainSelectedInstOperands,
6807 /* 18560 */ // GIR_Coverage, 2397,
6808 /* 18560 */ GIR_EraseRootFromParent_Done,
6809 /* 18561 */ // Label 402: @18561
6810 /* 18561 */ GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(18609), // Rule ID 2398 //
6811 /* 18566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6812 /* 18569 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6813 /* 18573 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6814 /* 18577 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
6815 /* 18588 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (t2UXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
6816 /* 18588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTH),
6817 /* 18591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6818 /* 18593 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6819 /* 18595 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6820 /* 18598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6821 /* 18601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6822 /* 18607 */ GIR_RootConstrainSelectedInstOperands,
6823 /* 18608 */ // GIR_Coverage, 2398,
6824 /* 18608 */ GIR_EraseRootFromParent_Done,
6825 /* 18609 */ // Label 403: @18609
6826 /* 18609 */ GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(18657), // Rule ID 2399 //
6827 /* 18614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
6828 /* 18617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6829 /* 18621 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6830 /* 18625 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16711935),
6831 /* 18636 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 16711935:{ *:[i32] }) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
6832 /* 18636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16),
6833 /* 18639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6834 /* 18641 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
6835 /* 18643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
6836 /* 18646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6837 /* 18649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6838 /* 18655 */ GIR_RootConstrainSelectedInstOperands,
6839 /* 18656 */ // GIR_Coverage, 2399,
6840 /* 18656 */ GIR_EraseRootFromParent_Done,
6841 /* 18657 */ // Label 404: @18657
6842 /* 18657 */ GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(18734), // Rule ID 5917 //
6843 /* 18662 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
6844 /* 18665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6845 /* 18669 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6846 /* 18673 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6847 /* 18677 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6848 /* 18681 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6849 /* 18685 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6850 /* 18689 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6851 /* 18693 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6852 /* 18697 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6853 /* 18701 */ // MIs[2] Operand 1
6854 /* 18701 */ // No operand predicates
6855 /* 18701 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6856 /* 18705 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6857 /* 18707 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6858 /* 18707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6859 /* 18710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6860 /* 18712 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6861 /* 18714 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6862 /* 18717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6863 /* 18720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6864 /* 18726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6865 /* 18732 */ GIR_RootConstrainSelectedInstOperands,
6866 /* 18733 */ // GIR_Coverage, 5917,
6867 /* 18733 */ GIR_EraseRootFromParent_Done,
6868 /* 18734 */ // Label 405: @18734
6869 /* 18734 */ GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(18811), // Rule ID 5950 //
6870 /* 18739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6871 /* 18742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6872 /* 18746 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6873 /* 18750 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6874 /* 18754 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6875 /* 18758 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6876 /* 18762 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6877 /* 18766 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6878 /* 18770 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6879 /* 18774 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
6880 /* 18778 */ // MIs[2] Operand 1
6881 /* 18778 */ // No operand predicates
6882 /* 18778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6883 /* 18782 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6884 /* 18784 */ // (and:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6885 /* 18784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
6886 /* 18787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6887 /* 18789 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6888 /* 18791 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6889 /* 18794 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6890 /* 18797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6891 /* 18803 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6892 /* 18809 */ GIR_RootConstrainSelectedInstOperands,
6893 /* 18810 */ // GIR_Coverage, 5950,
6894 /* 18810 */ GIR_EraseRootFromParent_Done,
6895 /* 18811 */ // Label 406: @18811
6896 /* 18811 */ GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(18888), // Rule ID 5916 //
6897 /* 18816 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
6898 /* 18819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6899 /* 18823 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6900 /* 18827 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6901 /* 18831 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6902 /* 18835 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6903 /* 18839 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6904 /* 18843 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6905 /* 18847 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6906 /* 18851 */ // MIs[2] Operand 1
6907 /* 18851 */ // No operand predicates
6908 /* 18851 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6909 /* 18855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6910 /* 18859 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6911 /* 18861 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6912 /* 18861 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6913 /* 18864 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6914 /* 18866 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6915 /* 18868 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6916 /* 18871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6917 /* 18874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6918 /* 18880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6919 /* 18886 */ GIR_RootConstrainSelectedInstOperands,
6920 /* 18887 */ // GIR_Coverage, 5916,
6921 /* 18887 */ GIR_EraseRootFromParent_Done,
6922 /* 18888 */ // Label 407: @18888
6923 /* 18888 */ GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(18965), // Rule ID 5949 //
6924 /* 18893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6925 /* 18896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6926 /* 18900 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
6927 /* 18904 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6928 /* 18908 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6929 /* 18912 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6930 /* 18916 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
6931 /* 18920 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6932 /* 18924 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
6933 /* 18928 */ // MIs[2] Operand 1
6934 /* 18928 */ // No operand predicates
6935 /* 18928 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
6936 /* 18932 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6937 /* 18936 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6938 /* 18938 */ // (and:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6939 /* 18938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
6940 /* 18941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6941 /* 18943 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
6942 /* 18945 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6943 /* 18948 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6944 /* 18951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6945 /* 18957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6946 /* 18963 */ GIR_RootConstrainSelectedInstOperands,
6947 /* 18964 */ // GIR_Coverage, 5949,
6948 /* 18964 */ GIR_EraseRootFromParent_Done,
6949 /* 18965 */ // Label 408: @18965
6950 /* 18965 */ GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(19042), // Rule ID 5915 //
6951 /* 18970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
6952 /* 18973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6953 /* 18977 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
6954 /* 18981 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6955 /* 18985 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6956 /* 18989 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6957 /* 18993 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6958 /* 18997 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6959 /* 19001 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6960 /* 19005 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6961 /* 19009 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
6962 /* 19013 */ // MIs[2] Operand 1
6963 /* 19013 */ // No operand predicates
6964 /* 19013 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6965 /* 19015 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm)) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6966 /* 19015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
6967 /* 19018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6968 /* 19020 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6969 /* 19022 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6970 /* 19025 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6971 /* 19028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6972 /* 19034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6973 /* 19040 */ GIR_RootConstrainSelectedInstOperands,
6974 /* 19041 */ // GIR_Coverage, 5915,
6975 /* 19041 */ GIR_EraseRootFromParent_Done,
6976 /* 19042 */ // Label 409: @19042
6977 /* 19042 */ GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(19119), // Rule ID 5948 //
6978 /* 19047 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
6979 /* 19050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6980 /* 19054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
6981 /* 19058 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
6982 /* 19062 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
6983 /* 19066 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
6984 /* 19070 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
6985 /* 19074 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
6986 /* 19078 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
6987 /* 19082 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
6988 /* 19086 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
6989 /* 19090 */ // MIs[2] Operand 1
6990 /* 19090 */ // No operand predicates
6991 /* 19090 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
6992 /* 19092 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
6993 /* 19092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
6994 /* 19095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
6995 /* 19097 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
6996 /* 19099 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
6997 /* 19102 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
6998 /* 19105 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
6999 /* 19111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7000 /* 19117 */ GIR_RootConstrainSelectedInstOperands,
7001 /* 19118 */ // GIR_Coverage, 5948,
7002 /* 19118 */ GIR_EraseRootFromParent_Done,
7003 /* 19119 */ // Label 410: @19119
7004 /* 19119 */ GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(19196), // Rule ID 158 //
7005 /* 19124 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
7006 /* 19127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7007 /* 19131 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7008 /* 19135 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7009 /* 19139 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7010 /* 19143 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7011 /* 19147 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7012 /* 19151 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7013 /* 19155 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7014 /* 19159 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
7015 /* 19163 */ // MIs[2] Operand 1
7016 /* 19163 */ // No operand predicates
7017 /* 19163 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7018 /* 19167 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
7019 /* 19169 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm, -1:{ *:[i32] })) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7020 /* 19169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
7021 /* 19172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7022 /* 19174 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7023 /* 19176 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7024 /* 19179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7025 /* 19182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7026 /* 19188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7027 /* 19194 */ GIR_RootConstrainSelectedInstOperands,
7028 /* 19195 */ // GIR_Coverage, 158,
7029 /* 19195 */ GIR_EraseRootFromParent_Done,
7030 /* 19196 */ // Label 411: @19196
7031 /* 19196 */ GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(19273), // Rule ID 489 //
7032 /* 19201 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7033 /* 19204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7034 /* 19208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7035 /* 19212 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7036 /* 19216 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7037 /* 19220 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7038 /* 19224 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7039 /* 19228 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7040 /* 19232 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7041 /* 19236 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
7042 /* 19240 */ // MIs[2] Operand 1
7043 /* 19240 */ // No operand predicates
7044 /* 19240 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7045 /* 19244 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
7046 /* 19246 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2BICri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7047 /* 19246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICri),
7048 /* 19249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7049 /* 19251 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7050 /* 19253 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
7051 /* 19256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7052 /* 19259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7053 /* 19265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7054 /* 19271 */ GIR_RootConstrainSelectedInstOperands,
7055 /* 19272 */ // GIR_Coverage, 489,
7056 /* 19272 */ GIR_EraseRootFromParent_Done,
7057 /* 19273 */ // Label 412: @19273
7058 /* 19273 */ GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(19344), // Rule ID 5918 //
7059 /* 19278 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
7060 /* 19281 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7061 /* 19285 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7062 /* 19289 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7063 /* 19293 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7064 /* 19297 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7065 /* 19301 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7066 /* 19306 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7067 /* 19310 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7068 /* 19314 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7069 /* 19316 */ // (and:{ *:[i32] } (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), GPR:{ *:[i32] }:$Rn) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
7070 /* 19316 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr),
7071 /* 19319 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7072 /* 19321 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
7073 /* 19323 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7074 /* 19327 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7075 /* 19330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7076 /* 19336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7077 /* 19342 */ GIR_RootConstrainSelectedInstOperands,
7078 /* 19343 */ // GIR_Coverage, 5918,
7079 /* 19343 */ GIR_EraseRootFromParent_Done,
7080 /* 19344 */ // Label 413: @19344
7081 /* 19344 */ GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(19415), // Rule ID 5939 //
7082 /* 19349 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
7083 /* 19352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7084 /* 19356 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7085 /* 19360 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7086 /* 19364 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7087 /* 19368 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7088 /* 19372 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7089 /* 19377 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7090 /* 19381 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7091 /* 19385 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7092 /* 19387 */ // (and:{ *:[i32] } (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), tGPR:{ *:[i32] }:$Rn) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
7093 /* 19387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC),
7094 /* 19390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
7095 /* 19392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
7096 /* 19398 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
7097 /* 19400 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7098 /* 19404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7099 /* 19407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7100 /* 19413 */ GIR_RootConstrainSelectedInstOperands,
7101 /* 19414 */ // GIR_Coverage, 5939,
7102 /* 19414 */ GIR_EraseRootFromParent_Done,
7103 /* 19415 */ // Label 414: @19415
7104 /* 19415 */ GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(19486), // Rule ID 5951 //
7105 /* 19420 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7106 /* 19423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7107 /* 19427 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7108 /* 19431 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7109 /* 19435 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7110 /* 19439 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7111 /* 19443 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7112 /* 19448 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7113 /* 19452 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7114 /* 19456 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7115 /* 19458 */ // (and:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7116 /* 19458 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr),
7117 /* 19461 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7118 /* 19463 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
7119 /* 19465 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7120 /* 19469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7121 /* 19472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7122 /* 19478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7123 /* 19484 */ GIR_RootConstrainSelectedInstOperands,
7124 /* 19485 */ // GIR_Coverage, 5951,
7125 /* 19485 */ GIR_EraseRootFromParent_Done,
7126 /* 19486 */ // Label 415: @19486
7127 /* 19486 */ GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(19557), // Rule ID 159 //
7128 /* 19491 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
7129 /* 19494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7130 /* 19498 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7131 /* 19502 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7132 /* 19506 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7133 /* 19510 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7134 /* 19514 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7135 /* 19518 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7136 /* 19523 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7137 /* 19527 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7138 /* 19529 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (BICrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
7139 /* 19529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICrr),
7140 /* 19532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7141 /* 19534 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7142 /* 19536 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7143 /* 19540 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7144 /* 19543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7145 /* 19549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7146 /* 19555 */ GIR_RootConstrainSelectedInstOperands,
7147 /* 19556 */ // GIR_Coverage, 159,
7148 /* 19556 */ GIR_EraseRootFromParent_Done,
7149 /* 19557 */ // Label 416: @19557
7150 /* 19557 */ GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(19628), // Rule ID 312 //
7151 /* 19562 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
7152 /* 19565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7153 /* 19569 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7154 /* 19573 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7155 /* 19577 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7156 /* 19581 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7157 /* 19585 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7158 /* 19589 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7159 /* 19594 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7160 /* 19598 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7161 /* 19600 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (tBIC:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
7162 /* 19600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBIC),
7163 /* 19603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
7164 /* 19605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
7165 /* 19611 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7166 /* 19613 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7167 /* 19617 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7168 /* 19620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7169 /* 19626 */ GIR_RootConstrainSelectedInstOperands,
7170 /* 19627 */ // GIR_Coverage, 312,
7171 /* 19627 */ GIR_EraseRootFromParent_Done,
7172 /* 19628 */ // Label 417: @19628
7173 /* 19628 */ GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(19699), // Rule ID 490 //
7174 /* 19633 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7175 /* 19636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7176 /* 19640 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7177 /* 19644 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7178 /* 19648 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
7179 /* 19652 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7180 /* 19656 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7181 /* 19660 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7182 /* 19665 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
7183 /* 19669 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7184 /* 19671 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2BICrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7185 /* 19671 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BICrr),
7186 /* 19674 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7187 /* 19676 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7188 /* 19678 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
7189 /* 19682 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7190 /* 19685 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7191 /* 19691 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7192 /* 19697 */ GIR_RootConstrainSelectedInstOperands,
7193 /* 19698 */ // GIR_Coverage, 490,
7194 /* 19698 */ GIR_EraseRootFromParent_Done,
7195 /* 19699 */ // Label 418: @19699
7196 /* 19699 */ GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(19744), // Rule ID 344 //
7197 /* 19704 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
7198 /* 19707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7199 /* 19711 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7200 /* 19715 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(255),
7201 /* 19726 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 255:{ *:[i32] }) => (tUXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
7202 /* 19726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTB),
7203 /* 19729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7204 /* 19731 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
7205 /* 19733 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7206 /* 19736 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7207 /* 19742 */ GIR_RootConstrainSelectedInstOperands,
7208 /* 19743 */ // GIR_Coverage, 344,
7209 /* 19743 */ GIR_EraseRootFromParent_Done,
7210 /* 19744 */ // Label 419: @19744
7211 /* 19744 */ GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(19789), // Rule ID 345 //
7212 /* 19749 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
7213 /* 19752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7214 /* 19756 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7215 /* 19760 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(65535),
7216 /* 19771 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, 65535:{ *:[i32] }) => (tUXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
7217 /* 19771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUXTH),
7218 /* 19774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7219 /* 19776 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
7220 /* 19778 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7221 /* 19781 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7222 /* 19787 */ GIR_RootConstrainSelectedInstOperands,
7223 /* 19788 */ // GIR_Coverage, 345,
7224 /* 19788 */ GIR_EraseRootFromParent_Done,
7225 /* 19789 */ // Label 420: @19789
7226 /* 19789 */ GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(19848), // Rule ID 2055 //
7227 /* 19794 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
7228 /* 19797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7229 /* 19801 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7230 /* 19805 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7231 /* 19809 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7232 /* 19813 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not),
7233 /* 19817 */ // MIs[1] Operand 1
7234 /* 19817 */ // No operand predicates
7235 /* 19817 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7236 /* 19819 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm) => (BICri:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>>:$imm))
7237 /* 19819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BICri),
7238 /* 19822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7239 /* 19824 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
7240 /* 19826 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm
7241 /* 19831 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7242 /* 19834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7243 /* 19840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7244 /* 19846 */ GIR_RootConstrainSelectedInstOperands,
7245 /* 19847 */ // GIR_Coverage, 2055,
7246 /* 19847 */ GIR_EraseRootFromParent_Done,
7247 /* 19848 */ // Label 421: @19848
7248 /* 19848 */ GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(19905), // Rule ID 146 //
7249 /* 19853 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
7250 /* 19856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7251 /* 19860 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7252 /* 19864 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7253 /* 19868 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7254 /* 19872 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
7255 /* 19876 */ // MIs[1] Operand 1
7256 /* 19876 */ // No operand predicates
7257 /* 19876 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7258 /* 19878 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ANDri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7259 /* 19878 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDri),
7260 /* 19881 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7261 /* 19883 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7262 /* 19885 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7263 /* 19888 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7264 /* 19891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7265 /* 19897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7266 /* 19903 */ GIR_RootConstrainSelectedInstOperands,
7267 /* 19904 */ // GIR_Coverage, 146,
7268 /* 19904 */ GIR_EraseRootFromParent_Done,
7269 /* 19905 */ // Label 422: @19905
7270 /* 19905 */ GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(19962), // Rule ID 480 //
7271 /* 19910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7272 /* 19913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7273 /* 19917 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7274 /* 19921 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7275 /* 19925 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7276 /* 19929 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
7277 /* 19933 */ // MIs[1] Operand 1
7278 /* 19933 */ // No operand predicates
7279 /* 19933 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7280 /* 19935 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ANDri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
7281 /* 19935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDri),
7282 /* 19938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7283 /* 19940 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7284 /* 19942 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7285 /* 19945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7286 /* 19948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7287 /* 19954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7288 /* 19960 */ GIR_RootConstrainSelectedInstOperands,
7289 /* 19961 */ // GIR_Coverage, 480,
7290 /* 19961 */ GIR_EraseRootFromParent_Done,
7291 /* 19962 */ // Label 423: @19962
7292 /* 19962 */ GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(20013), // Rule ID 162 //
7293 /* 19967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM),
7294 /* 19970 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7295 /* 19974 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7296 /* 19978 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7297 /* 19982 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7298 /* 19986 */ // MIs[1] Operand 1
7299 /* 19986 */ // No operand predicates
7300 /* 19986 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm),
7301 /* 19990 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7302 /* 19992 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (BFC:{ *:[i32] } GPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
7303 /* 19992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BFC),
7304 /* 19995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7305 /* 19997 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
7306 /* 19999 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7307 /* 20002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7308 /* 20005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7309 /* 20011 */ GIR_RootConstrainSelectedInstOperands,
7310 /* 20012 */ // GIR_Coverage, 162,
7311 /* 20012 */ GIR_EraseRootFromParent_Done,
7312 /* 20013 */ // Label 424: @20013
7313 /* 20013 */ GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(20064), // Rule ID 492 //
7314 /* 20018 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7315 /* 20021 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7316 /* 20025 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7317 /* 20029 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
7318 /* 20033 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7319 /* 20037 */ // MIs[1] Operand 1
7320 /* 20037 */ // No operand predicates
7321 /* 20037 */ GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_bf_inv_mask_imm),
7322 /* 20041 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
7323 /* 20043 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_bf_inv_mask_imm>>:$imm) => (t2BFC:{ *:[i32] } rGPR:{ *:[i32] }:$src, (imm:{ *:[i32] }):$imm)
7324 /* 20043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2BFC),
7325 /* 20046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7326 /* 20048 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
7327 /* 20050 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
7328 /* 20053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7329 /* 20056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7330 /* 20062 */ GIR_RootConstrainSelectedInstOperands,
7331 /* 20063 */ // GIR_Coverage, 492,
7332 /* 20063 */ GIR_EraseRootFromParent_Done,
7333 /* 20064 */ // Label 425: @20064
7334 /* 20064 */ GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(20110), // Rule ID 147 //
7335 /* 20069 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
7336 /* 20072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7337 /* 20076 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7338 /* 20080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7339 /* 20084 */ // (and:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ANDrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
7340 /* 20084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ANDrr),
7341 /* 20087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7342 /* 20089 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7343 /* 20091 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
7344 /* 20093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7345 /* 20096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7346 /* 20102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7347 /* 20108 */ GIR_RootConstrainSelectedInstOperands,
7348 /* 20109 */ // GIR_Coverage, 147,
7349 /* 20109 */ GIR_EraseRootFromParent_Done,
7350 /* 20110 */ // Label 426: @20110
7351 /* 20110 */ GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(20156), // Rule ID 309 //
7352 /* 20115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
7353 /* 20118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7354 /* 20122 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7355 /* 20126 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
7356 /* 20130 */ // (and:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tAND:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
7357 /* 20130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tAND),
7358 /* 20133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
7359 /* 20135 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
7360 /* 20141 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7361 /* 20143 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
7362 /* 20145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7363 /* 20148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7364 /* 20154 */ GIR_RootConstrainSelectedInstOperands,
7365 /* 20155 */ // GIR_Coverage, 309,
7366 /* 20155 */ GIR_EraseRootFromParent_Done,
7367 /* 20156 */ // Label 427: @20156
7368 /* 20156 */ GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(20202), // Rule ID 481 //
7369 /* 20161 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7370 /* 20164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7371 /* 20168 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7372 /* 20172 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7373 /* 20176 */ // (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ANDrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
7374 /* 20176 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7375 /* 20179 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7376 /* 20181 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
7377 /* 20183 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
7378 /* 20185 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7379 /* 20188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7380 /* 20194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7381 /* 20200 */ GIR_RootConstrainSelectedInstOperands,
7382 /* 20201 */ // GIR_Coverage, 481,
7383 /* 20201 */ GIR_EraseRootFromParent_Done,
7384 /* 20202 */ // Label 428: @20202
7385 /* 20202 */ GIM_Reject,
7386 /* 20203 */ // Label 396: @20203
7387 /* 20203 */ GIM_Reject,
7388 /* 20204 */ // Label 383: @20204
7389 /* 20204 */ GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(20250), // Rule ID 2876 //
7390 /* 20209 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7391 /* 20212 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
7392 /* 20215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
7393 /* 20218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7394 /* 20222 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7395 /* 20226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7396 /* 20230 */ // (and:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VANDd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
7397 /* 20230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7398 /* 20233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7399 /* 20235 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7400 /* 20237 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7401 /* 20239 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7402 /* 20242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7403 /* 20248 */ GIR_RootConstrainSelectedInstOperands,
7404 /* 20249 */ // GIR_Coverage, 2876,
7405 /* 20249 */ GIR_EraseRootFromParent_Done,
7406 /* 20250 */ // Label 429: @20250
7407 /* 20250 */ GIM_Reject,
7408 /* 20251 */ // Label 384: @20251
7409 /* 20251 */ GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(20368), // Rule ID 1987 //
7410 /* 20256 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7411 /* 20259 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1,
7412 /* 20262 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1,
7413 /* 20265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7414 /* 20269 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7415 /* 20273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7416 /* 20277 */ // (and:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7417 /* 20277 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7418 /* 20280 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7419 /* 20284 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7420 /* 20289 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7421 /* 20293 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7422 /* 20298 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7423 /* 20301 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7424 /* 20305 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7425 /* 20310 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7426 /* 20314 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7427 /* 20319 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7428 /* 20322 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7429 /* 20326 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7430 /* 20331 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7431 /* 20334 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7432 /* 20337 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7433 /* 20340 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7434 /* 20346 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7435 /* 20352 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7436 /* 20354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7437 /* 20357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7438 /* 20359 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7439 /* 20362 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7440 /* 20367 */ // GIR_Coverage, 1987,
7441 /* 20367 */ GIR_EraseRootFromParent_Done,
7442 /* 20368 */ // Label 430: @20368
7443 /* 20368 */ GIM_Reject,
7444 /* 20369 */ // Label 385: @20369
7445 /* 20369 */ GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(20415), // Rule ID 1294 //
7446 /* 20374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7447 /* 20377 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
7448 /* 20380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
7449 /* 20383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7450 /* 20387 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7451 /* 20391 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7452 /* 20395 */ // (and:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VANDd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
7453 /* 20395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7454 /* 20398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7455 /* 20400 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
7456 /* 20402 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
7457 /* 20404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7458 /* 20407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7459 /* 20413 */ GIR_RootConstrainSelectedInstOperands,
7460 /* 20414 */ // GIR_Coverage, 1294,
7461 /* 20414 */ GIR_EraseRootFromParent_Done,
7462 /* 20415 */ // Label 431: @20415
7463 /* 20415 */ GIM_Reject,
7464 /* 20416 */ // Label 386: @20416
7465 /* 20416 */ GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(20529),
7466 /* 20421 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
7467 /* 20424 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
7468 /* 20427 */ GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(20467), // Rule ID 2879 //
7469 /* 20432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7470 /* 20435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7471 /* 20439 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7472 /* 20443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7473 /* 20447 */ // (and:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VANDq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
7474 /* 20447 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7475 /* 20450 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7476 /* 20452 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7477 /* 20454 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7478 /* 20456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7479 /* 20459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7480 /* 20465 */ GIR_RootConstrainSelectedInstOperands,
7481 /* 20466 */ // GIR_Coverage, 2879,
7482 /* 20466 */ GIR_EraseRootFromParent_Done,
7483 /* 20467 */ // Label 433: @20467
7484 /* 20467 */ GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(20528), // Rule ID 3728 //
7485 /* 20472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7486 /* 20475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7487 /* 20479 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7488 /* 20483 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7489 /* 20487 */ // (and:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VAND:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
7490 /* 20487 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7491 /* 20490 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7492 /* 20494 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7493 /* 20499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7494 /* 20502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7495 /* 20504 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7496 /* 20506 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7497 /* 20508 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7498 /* 20511 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7499 /* 20517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7500 /* 20523 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7501 /* 20526 */ GIR_RootConstrainSelectedInstOperands,
7502 /* 20527 */ // GIR_Coverage, 3728,
7503 /* 20527 */ GIR_EraseRootFromParent_Done,
7504 /* 20528 */ // Label 434: @20528
7505 /* 20528 */ GIM_Reject,
7506 /* 20529 */ // Label 432: @20529
7507 /* 20529 */ GIM_Reject,
7508 /* 20530 */ // Label 387: @20530
7509 /* 20530 */ GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(20647), // Rule ID 1988 //
7510 /* 20535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7511 /* 20538 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1,
7512 /* 20541 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1,
7513 /* 20544 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7514 /* 20548 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7515 /* 20552 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7516 /* 20556 */ // (and:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7517 /* 20556 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7518 /* 20559 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7519 /* 20563 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7520 /* 20568 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7521 /* 20572 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7522 /* 20577 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7523 /* 20580 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7524 /* 20584 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7525 /* 20589 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7526 /* 20593 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7527 /* 20598 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7528 /* 20601 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7529 /* 20605 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7530 /* 20610 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7531 /* 20613 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7532 /* 20616 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7533 /* 20619 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7534 /* 20625 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7535 /* 20631 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7536 /* 20633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7537 /* 20636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7538 /* 20638 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7539 /* 20641 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7540 /* 20646 */ // GIR_Coverage, 1988,
7541 /* 20646 */ GIR_EraseRootFromParent_Done,
7542 /* 20647 */ // Label 435: @20647
7543 /* 20647 */ GIM_Reject,
7544 /* 20648 */ // Label 388: @20648
7545 /* 20648 */ GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(20694), // Rule ID 2875 //
7546 /* 20653 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7547 /* 20656 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
7548 /* 20659 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
7549 /* 20662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7550 /* 20666 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7551 /* 20670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7552 /* 20674 */ // (and:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VANDd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
7553 /* 20674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7554 /* 20677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7555 /* 20679 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7556 /* 20681 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7557 /* 20683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7558 /* 20686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7559 /* 20692 */ GIR_RootConstrainSelectedInstOperands,
7560 /* 20693 */ // GIR_Coverage, 2875,
7561 /* 20693 */ GIR_EraseRootFromParent_Done,
7562 /* 20694 */ // Label 436: @20694
7563 /* 20694 */ GIM_Reject,
7564 /* 20695 */ // Label 389: @20695
7565 /* 20695 */ GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(20808),
7566 /* 20700 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
7567 /* 20703 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
7568 /* 20706 */ GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(20746), // Rule ID 1295 //
7569 /* 20711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7570 /* 20714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7571 /* 20718 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7572 /* 20722 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7573 /* 20726 */ // (and:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VANDq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
7574 /* 20726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7575 /* 20729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7576 /* 20731 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
7577 /* 20733 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
7578 /* 20735 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7579 /* 20738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7580 /* 20744 */ GIR_RootConstrainSelectedInstOperands,
7581 /* 20745 */ // GIR_Coverage, 1295,
7582 /* 20745 */ GIR_EraseRootFromParent_Done,
7583 /* 20746 */ // Label 438: @20746
7584 /* 20746 */ GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(20807), // Rule ID 3724 //
7585 /* 20751 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7586 /* 20754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7587 /* 20758 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7588 /* 20762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7589 /* 20766 */ // (and:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VAND:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
7590 /* 20766 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7591 /* 20769 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7592 /* 20773 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7593 /* 20778 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7594 /* 20781 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7595 /* 20783 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7596 /* 20785 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7597 /* 20787 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7598 /* 20790 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7599 /* 20796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7600 /* 20802 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7601 /* 20805 */ GIR_RootConstrainSelectedInstOperands,
7602 /* 20806 */ // GIR_Coverage, 3724,
7603 /* 20806 */ GIR_EraseRootFromParent_Done,
7604 /* 20807 */ // Label 439: @20807
7605 /* 20807 */ GIM_Reject,
7606 /* 20808 */ // Label 437: @20808
7607 /* 20808 */ GIM_Reject,
7608 /* 20809 */ // Label 390: @20809
7609 /* 20809 */ GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(20926), // Rule ID 1989 //
7610 /* 20814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7611 /* 20817 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1,
7612 /* 20820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1,
7613 /* 20823 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7614 /* 20827 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7615 /* 20831 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7616 /* 20835 */ // (and:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7617 /* 20835 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7618 /* 20838 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7619 /* 20842 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7620 /* 20847 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7621 /* 20851 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7622 /* 20856 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7623 /* 20859 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7624 /* 20863 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7625 /* 20868 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7626 /* 20872 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7627 /* 20877 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7628 /* 20880 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7629 /* 20884 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7630 /* 20889 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7631 /* 20892 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7632 /* 20895 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7633 /* 20898 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7634 /* 20904 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7635 /* 20910 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7636 /* 20912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7637 /* 20915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7638 /* 20917 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7639 /* 20920 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7640 /* 20925 */ // GIR_Coverage, 1989,
7641 /* 20925 */ GIR_EraseRootFromParent_Done,
7642 /* 20926 */ // Label 440: @20926
7643 /* 20926 */ GIM_Reject,
7644 /* 20927 */ // Label 391: @20927
7645 /* 20927 */ GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(20973), // Rule ID 2874 //
7646 /* 20932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7647 /* 20935 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
7648 /* 20938 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
7649 /* 20941 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7650 /* 20945 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7651 /* 20949 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
7652 /* 20953 */ // (and:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VANDd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
7653 /* 20953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDd),
7654 /* 20956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7655 /* 20958 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7656 /* 20960 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7657 /* 20962 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7658 /* 20965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7659 /* 20971 */ GIR_RootConstrainSelectedInstOperands,
7660 /* 20972 */ // GIR_Coverage, 2874,
7661 /* 20972 */ GIR_EraseRootFromParent_Done,
7662 /* 20973 */ // Label 441: @20973
7663 /* 20973 */ GIM_Reject,
7664 /* 20974 */ // Label 392: @20974
7665 /* 20974 */ GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(21087),
7666 /* 20979 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
7667 /* 20982 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
7668 /* 20985 */ GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(21025), // Rule ID 2878 //
7669 /* 20990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7670 /* 20993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7671 /* 20997 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7672 /* 21001 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7673 /* 21005 */ // (and:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VANDq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
7674 /* 21005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7675 /* 21008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7676 /* 21010 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7677 /* 21012 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7678 /* 21014 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7679 /* 21017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7680 /* 21023 */ GIR_RootConstrainSelectedInstOperands,
7681 /* 21024 */ // GIR_Coverage, 2878,
7682 /* 21024 */ GIR_EraseRootFromParent_Done,
7683 /* 21025 */ // Label 443: @21025
7684 /* 21025 */ GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(21086), // Rule ID 3720 //
7685 /* 21030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7686 /* 21033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7687 /* 21037 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7688 /* 21041 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7689 /* 21045 */ // (and:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VAND:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
7690 /* 21045 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7691 /* 21048 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7692 /* 21052 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7693 /* 21057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7694 /* 21060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7695 /* 21062 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7696 /* 21064 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7697 /* 21066 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7698 /* 21069 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7699 /* 21075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7700 /* 21081 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7701 /* 21084 */ GIR_RootConstrainSelectedInstOperands,
7702 /* 21085 */ // GIR_Coverage, 3720,
7703 /* 21085 */ GIR_EraseRootFromParent_Done,
7704 /* 21086 */ // Label 444: @21086
7705 /* 21086 */ GIM_Reject,
7706 /* 21087 */ // Label 442: @21087
7707 /* 21087 */ GIM_Reject,
7708 /* 21088 */ // Label 393: @21088
7709 /* 21088 */ GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(21205), // Rule ID 1990 //
7710 /* 21093 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7711 /* 21096 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1,
7712 /* 21099 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1,
7713 /* 21102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7714 /* 21106 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7715 /* 21110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
7716 /* 21114 */ // (and:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ANDrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
7717 /* 21114 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
7718 /* 21117 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7719 /* 21121 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7720 /* 21126 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
7721 /* 21130 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7722 /* 21135 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
7723 /* 21138 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7724 /* 21142 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7725 /* 21147 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
7726 /* 21151 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
7727 /* 21156 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
7728 /* 21159 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ANDrr),
7729 /* 21163 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7730 /* 21168 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
7731 /* 21171 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
7732 /* 21174 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
7733 /* 21177 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7734 /* 21183 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7735 /* 21189 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
7736 /* 21191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
7737 /* 21194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
7738 /* 21196 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7739 /* 21199 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
7740 /* 21204 */ // GIR_Coverage, 1990,
7741 /* 21204 */ GIR_EraseRootFromParent_Done,
7742 /* 21205 */ // Label 445: @21205
7743 /* 21205 */ GIM_Reject,
7744 /* 21206 */ // Label 394: @21206
7745 /* 21206 */ GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(21319),
7746 /* 21211 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
7747 /* 21214 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
7748 /* 21217 */ GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(21257), // Rule ID 2877 //
7749 /* 21222 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
7750 /* 21225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7751 /* 21229 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7752 /* 21233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
7753 /* 21237 */ // (and:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VANDq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
7754 /* 21237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VANDq),
7755 /* 21240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
7756 /* 21242 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
7757 /* 21244 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
7758 /* 21246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7759 /* 21249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7760 /* 21255 */ GIR_RootConstrainSelectedInstOperands,
7761 /* 21256 */ // GIR_Coverage, 2877,
7762 /* 21256 */ GIR_EraseRootFromParent_Done,
7763 /* 21257 */ // Label 447: @21257
7764 /* 21257 */ GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(21318), // Rule ID 3716 //
7765 /* 21262 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
7766 /* 21265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7767 /* 21269 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7768 /* 21273 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
7769 /* 21277 */ // (and:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VAND:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
7770 /* 21277 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
7771 /* 21280 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
7772 /* 21284 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
7773 /* 21289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VAND),
7774 /* 21292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
7775 /* 21294 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
7776 /* 21296 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
7777 /* 21298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
7778 /* 21301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7779 /* 21307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7780 /* 21313 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
7781 /* 21316 */ GIR_RootConstrainSelectedInstOperands,
7782 /* 21317 */ // GIR_Coverage, 3716,
7783 /* 21317 */ GIR_EraseRootFromParent_Done,
7784 /* 21318 */ // Label 448: @21318
7785 /* 21318 */ GIM_Reject,
7786 /* 21319 */ // Label 446: @21319
7787 /* 21319 */ GIM_Reject,
7788 /* 21320 */ // Label 395: @21320
7789 /* 21320 */ GIM_Reject,
7790 /* 21321 */ // Label 6: @21321
7791 /* 21321 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 462*/ GIMT_Encode4(27129),
7792 /* 21332 */ /*GILLT_s32*//*Label 449*/ GIMT_Encode4(21392),
7793 /* 21336 */ /*GILLT_s64*//*Label 450*/ GIMT_Encode4(26013),
7794 /* 21340 */ /*GILLT_v2s1*//*Label 451*/ GIMT_Encode4(26060),
7795 /* 21344 */ /*GILLT_v2s32*//*Label 452*/ GIMT_Encode4(26178),
7796 /* 21348 */ /*GILLT_v2s64*//*Label 453*/ GIMT_Encode4(26225),
7797 /* 21352 */ /*GILLT_v4s1*//*Label 454*/ GIMT_Encode4(26339),
7798 /* 21356 */ /*GILLT_v4s16*//*Label 455*/ GIMT_Encode4(26457),
7799 /* 21360 */ /*GILLT_v4s32*//*Label 456*/ GIMT_Encode4(26504), GIMT_Encode4(0),
7800 /* 21368 */ /*GILLT_v8s1*//*Label 457*/ GIMT_Encode4(26618),
7801 /* 21372 */ /*GILLT_v8s8*//*Label 458*/ GIMT_Encode4(26736),
7802 /* 21376 */ /*GILLT_v8s16*//*Label 459*/ GIMT_Encode4(26783), GIMT_Encode4(0),
7803 /* 21384 */ /*GILLT_v16s1*//*Label 460*/ GIMT_Encode4(26897),
7804 /* 21388 */ /*GILLT_v16s8*//*Label 461*/ GIMT_Encode4(27015),
7805 /* 21392 */ // Label 449: @21392
7806 /* 21392 */ GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(26012),
7807 /* 21397 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
7808 /* 21400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
7809 /* 21403 */ GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(21530), // Rule ID 6199 //
7810 /* 21408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7811 /* 21411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7812 /* 21415 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7813 /* 21419 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7814 /* 21423 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7815 /* 21427 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7816 /* 21431 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7817 /* 21435 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
7818 /* 21439 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7819 /* 21443 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7820 /* 21447 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7821 /* 21452 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
7822 /* 21456 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
7823 /* 21467 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7824 /* 21471 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
7825 /* 21475 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7826 /* 21479 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7827 /* 21483 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7828 /* 21487 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
7829 /* 21491 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7830 /* 21495 */ // MIs[4] Rm
7831 /* 21495 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7832 /* 21500 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
7833 /* 21504 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
7834 /* 21508 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7835 /* 21510 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
7836 /* 21510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH),
7837 /* 21513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7838 /* 21515 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7839 /* 21519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7840 /* 21522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7841 /* 21528 */ GIR_RootConstrainSelectedInstOperands,
7842 /* 21529 */ // GIR_Coverage, 6199,
7843 /* 21529 */ GIR_EraseRootFromParent_Done,
7844 /* 21530 */ // Label 464: @21530
7845 /* 21530 */ GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(21657), // Rule ID 6241 //
7846 /* 21535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7847 /* 21538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7848 /* 21542 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7849 /* 21546 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7850 /* 21550 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7851 /* 21554 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7852 /* 21558 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7853 /* 21562 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
7854 /* 21566 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7855 /* 21570 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7856 /* 21574 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7857 /* 21579 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 8,
7858 /* 21583 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(255),
7859 /* 21594 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7860 /* 21598 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
7861 /* 21602 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7862 /* 21606 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7863 /* 21610 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7864 /* 21614 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_SHL),
7865 /* 21618 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7866 /* 21622 */ // MIs[4] Rm
7867 /* 21622 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7868 /* 21627 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 24,
7869 /* 21631 */ GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16,
7870 /* 21635 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7871 /* 21637 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] }), (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
7872 /* 21637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH),
7873 /* 21640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7874 /* 21642 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7875 /* 21646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7876 /* 21649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7877 /* 21655 */ GIR_RootConstrainSelectedInstOperands,
7878 /* 21656 */ // GIR_Coverage, 6241,
7879 /* 21656 */ GIR_EraseRootFromParent_Done,
7880 /* 21657 */ // Label 465: @21657
7881 /* 21657 */ GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(21784), // Rule ID 2075 //
7882 /* 21662 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7883 /* 21665 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7884 /* 21669 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7885 /* 21673 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
7886 /* 21677 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7887 /* 21681 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7888 /* 21685 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7889 /* 21689 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
7890 /* 21693 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7891 /* 21697 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7892 /* 21701 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
7893 /* 21706 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
7894 /* 21710 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
7895 /* 21714 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7896 /* 21718 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
7897 /* 21722 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7898 /* 21726 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7899 /* 21730 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7900 /* 21734 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
7901 /* 21738 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7902 /* 21742 */ // MIs[4] Rm
7903 /* 21742 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7904 /* 21747 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
7905 /* 21751 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255),
7906 /* 21762 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7907 /* 21764 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
7908 /* 21764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH),
7909 /* 21767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7910 /* 21769 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7911 /* 21773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7912 /* 21776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7913 /* 21782 */ GIR_RootConstrainSelectedInstOperands,
7914 /* 21783 */ // GIR_Coverage, 2075,
7915 /* 21783 */ GIR_EraseRootFromParent_Done,
7916 /* 21784 */ // Label 466: @21784
7917 /* 21784 */ GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(21911), // Rule ID 2357 //
7918 /* 21789 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
7919 /* 21792 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7920 /* 21796 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7921 /* 21800 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
7922 /* 21804 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7923 /* 21808 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7924 /* 21812 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7925 /* 21816 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
7926 /* 21820 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7927 /* 21824 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7928 /* 21828 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7929 /* 21833 */ GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 24,
7930 /* 21837 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16,
7931 /* 21841 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
7932 /* 21845 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
7933 /* 21849 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
7934 /* 21853 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
7935 /* 21857 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4]
7936 /* 21861 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR),
7937 /* 21865 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7938 /* 21869 */ // MIs[4] Rm
7939 /* 21869 */ GIM_CheckIsSameOperand, /*MI*/4, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1,
7940 /* 21874 */ GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 8,
7941 /* 21878 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(255),
7942 /* 21889 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7943 /* 21891 */ // (or:{ *:[i32] } (sra:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 24:{ *:[i32] }), 16:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 8:{ *:[i32] }), 255:{ *:[i32] })) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
7944 /* 21891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH),
7945 /* 21894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7946 /* 21896 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7947 /* 21900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7948 /* 21903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7949 /* 21909 */ GIR_RootConstrainSelectedInstOperands,
7950 /* 21910 */ // GIR_Coverage, 2357,
7951 /* 21910 */ GIR_EraseRootFromParent_Done,
7952 /* 21911 */ // Label 467: @21911
7953 /* 21911 */ GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(22044), // Rule ID 5931 //
7954 /* 21916 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
7955 /* 21919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7956 /* 21923 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7957 /* 21927 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7958 /* 21931 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7959 /* 21935 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7960 /* 21939 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7961 /* 21943 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
7962 /* 21947 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
7963 /* 21951 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
7964 /* 21955 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7965 /* 21960 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
7966 /* 21964 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
7967 /* 21968 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
7968 /* 21972 */ // MIs[3] Operand 1
7969 /* 21972 */ // No operand predicates
7970 /* 21972 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
7971 /* 21983 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
7972 /* 21987 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
7973 /* 21991 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
7974 /* 21995 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
7975 /* 21999 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
7976 /* 22004 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
7977 /* 22015 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
7978 /* 22017 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
7979 /* 22017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
7980 /* 22020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
7981 /* 22022 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
7982 /* 22026 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
7983 /* 22030 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
7984 /* 22033 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
7985 /* 22036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
7986 /* 22042 */ GIR_RootConstrainSelectedInstOperands,
7987 /* 22043 */ // GIR_Coverage, 5931,
7988 /* 22043 */ GIR_EraseRootFromParent_Done,
7989 /* 22044 */ // Label 468: @22044
7990 /* 22044 */ GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(22177), // Rule ID 5968 //
7991 /* 22049 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
7992 /* 22052 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
7993 /* 22056 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
7994 /* 22060 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
7995 /* 22064 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
7996 /* 22068 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
7997 /* 22072 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
7998 /* 22076 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
7999 /* 22080 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8000 /* 22084 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8001 /* 22088 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8002 /* 22093 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8003 /* 22097 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8004 /* 22101 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
8005 /* 22105 */ // MIs[3] Operand 1
8006 /* 22105 */ // No operand predicates
8007 /* 22105 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8008 /* 22116 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
8009 /* 22120 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
8010 /* 22124 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
8011 /* 22128 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
8012 /* 22132 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8013 /* 22137 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
8014 /* 22148 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8015 /* 22150 */ // (or:{ *:[i32] } (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8016 /* 22150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8017 /* 22153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8018 /* 22155 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
8019 /* 22159 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
8020 /* 22163 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8021 /* 22166 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8022 /* 22169 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8023 /* 22175 */ GIR_RootConstrainSelectedInstOperands,
8024 /* 22176 */ // GIR_Coverage, 5968,
8025 /* 22176 */ GIR_EraseRootFromParent_Done,
8026 /* 22177 */ // Label 469: @22177
8027 /* 22177 */ GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(22310), // Rule ID 6204 //
8028 /* 22182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8029 /* 22185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8030 /* 22189 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8031 /* 22193 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8032 /* 22197 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8033 /* 22201 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8034 /* 22205 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8035 /* 22209 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
8036 /* 22213 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8037 /* 22217 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8038 /* 22221 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8039 /* 22226 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8040 /* 22230 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8041 /* 22234 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
8042 /* 22238 */ // MIs[3] Operand 1
8043 /* 22238 */ // No operand predicates
8044 /* 22238 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8045 /* 22249 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
8046 /* 22253 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
8047 /* 22257 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
8048 /* 22261 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
8049 /* 22265 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8050 /* 22270 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
8051 /* 22281 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8052 /* 22283 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
8053 /* 22283 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8054 /* 22286 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8055 /* 22288 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
8056 /* 22292 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8057 /* 22296 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8058 /* 22299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8059 /* 22302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8060 /* 22308 */ GIR_RootConstrainSelectedInstOperands,
8061 /* 22309 */ // GIR_Coverage, 6204,
8062 /* 22309 */ GIR_EraseRootFromParent_Done,
8063 /* 22310 */ // Label 470: @22310
8064 /* 22310 */ GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(22443), // Rule ID 6246 //
8065 /* 22315 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8066 /* 22318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8067 /* 22322 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8068 /* 22326 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8069 /* 22330 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8070 /* 22334 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8071 /* 22338 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8072 /* 22342 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
8073 /* 22346 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8074 /* 22350 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8075 /* 22354 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8076 /* 22359 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8077 /* 22363 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8078 /* 22367 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
8079 /* 22371 */ // MIs[3] Operand 1
8080 /* 22371 */ // No operand predicates
8081 /* 22371 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8082 /* 22382 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
8083 /* 22386 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
8084 /* 22390 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
8085 /* 22394 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
8086 /* 22398 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8087 /* 22403 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(4294901760),
8088 /* 22414 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8089 /* 22416 */ // (or:{ *:[i32] } (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
8090 /* 22416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8091 /* 22419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8092 /* 22421 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1
8093 /* 22425 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8094 /* 22429 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8095 /* 22432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8096 /* 22435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8097 /* 22441 */ GIR_RootConstrainSelectedInstOperands,
8098 /* 22442 */ // GIR_Coverage, 6246,
8099 /* 22442 */ GIR_EraseRootFromParent_Done,
8100 /* 22443 */ // Label 471: @22443
8101 /* 22443 */ GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(22576), // Rule ID 5930 //
8102 /* 22448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8103 /* 22451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8104 /* 22455 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8105 /* 22459 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8106 /* 22463 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8107 /* 22467 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8108 /* 22471 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8109 /* 22475 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
8110 /* 22479 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8111 /* 22483 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8112 /* 22487 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8113 /* 22492 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8114 /* 22496 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8115 /* 22500 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
8116 /* 22504 */ // MIs[3] Operand 1
8117 /* 22504 */ // No operand predicates
8118 /* 22504 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8119 /* 22515 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
8120 /* 22519 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
8121 /* 22523 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
8122 /* 22527 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
8123 /* 22531 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8124 /* 22536 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535),
8125 /* 22547 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8126 /* 22549 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8127 /* 22549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8128 /* 22552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8129 /* 22554 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
8130 /* 22558 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
8131 /* 22562 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8132 /* 22565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8133 /* 22568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8134 /* 22574 */ GIR_RootConstrainSelectedInstOperands,
8135 /* 22575 */ // GIR_Coverage, 5930,
8136 /* 22575 */ GIR_EraseRootFromParent_Done,
8137 /* 22576 */ // Label 472: @22576
8138 /* 22576 */ GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(22709), // Rule ID 5967 //
8139 /* 22581 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8140 /* 22584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8141 /* 22588 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8142 /* 22592 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8143 /* 22596 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8144 /* 22600 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8145 /* 22604 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8146 /* 22608 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
8147 /* 22612 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8148 /* 22616 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8149 /* 22620 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8150 /* 22625 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8151 /* 22629 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8152 /* 22633 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
8153 /* 22637 */ // MIs[3] Operand 1
8154 /* 22637 */ // No operand predicates
8155 /* 22637 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8156 /* 22648 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4]
8157 /* 22652 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_AND),
8158 /* 22656 */ GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32,
8159 /* 22660 */ GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32,
8160 /* 22664 */ GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8161 /* 22669 */ GIM_CheckConstantInt, /*MI*/4, /*Op*/2, GIMT_Encode8(65535),
8162 /* 22680 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8163 /* 22682 */ // (or:{ *:[i32] } (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8164 /* 22682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8165 /* 22685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8166 /* 22687 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // Rn
8167 /* 22691 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
8168 /* 22695 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8169 /* 22698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8170 /* 22701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8171 /* 22707 */ GIR_RootConstrainSelectedInstOperands,
8172 /* 22708 */ // GIR_Coverage, 5967,
8173 /* 22708 */ GIR_EraseRootFromParent_Done,
8174 /* 22709 */ // Label 473: @22709
8175 /* 22709 */ GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(22842), // Rule ID 202 //
8176 /* 22714 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8177 /* 22717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8178 /* 22721 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8179 /* 22725 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8180 /* 22729 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8181 /* 22733 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8182 /* 22737 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8183 /* 22742 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8184 /* 22753 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8185 /* 22757 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8186 /* 22761 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8187 /* 22765 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8188 /* 22769 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8189 /* 22773 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
8190 /* 22777 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8191 /* 22781 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8192 /* 22785 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8193 /* 22790 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8194 /* 22794 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8195 /* 22798 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
8196 /* 22802 */ // MIs[4] Operand 1
8197 /* 22802 */ // No operand predicates
8198 /* 22802 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8199 /* 22813 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8200 /* 22815 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8201 /* 22815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8202 /* 22818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8203 /* 22820 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8204 /* 22824 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8205 /* 22828 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8206 /* 22831 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8207 /* 22834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8208 /* 22840 */ GIR_RootConstrainSelectedInstOperands,
8209 /* 22841 */ // GIR_Coverage, 202,
8210 /* 22841 */ GIR_EraseRootFromParent_Done,
8211 /* 22842 */ // Label 474: @22842
8212 /* 22842 */ GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(22975), // Rule ID 539 //
8213 /* 22847 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8214 /* 22850 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8215 /* 22854 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8216 /* 22858 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8217 /* 22862 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8218 /* 22866 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8219 /* 22870 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8220 /* 22875 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8221 /* 22886 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8222 /* 22890 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8223 /* 22894 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8224 /* 22898 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8225 /* 22902 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8226 /* 22906 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_ASHR),
8227 /* 22910 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8228 /* 22914 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8229 /* 22918 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8230 /* 22923 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8231 /* 22927 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8232 /* 22931 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_asr_amt),
8233 /* 22935 */ // MIs[4] Operand 1
8234 /* 22935 */ // No operand predicates
8235 /* 22935 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8236 /* 22946 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8237 /* 22948 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_asr_amt>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8238 /* 22948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8239 /* 22951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8240 /* 22953 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8241 /* 22957 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8242 /* 22961 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8243 /* 22964 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8244 /* 22967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8245 /* 22973 */ GIR_RootConstrainSelectedInstOperands,
8246 /* 22974 */ // GIR_Coverage, 539,
8247 /* 22974 */ GIR_EraseRootFromParent_Done,
8248 /* 22975 */ // Label 475: @22975
8249 /* 22975 */ GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(23108), // Rule ID 2080 //
8250 /* 22980 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8251 /* 22983 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8252 /* 22987 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8253 /* 22991 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8254 /* 22995 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8255 /* 22999 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8256 /* 23003 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8257 /* 23008 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8258 /* 23019 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8259 /* 23023 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8260 /* 23027 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8261 /* 23031 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8262 /* 23035 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8263 /* 23039 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
8264 /* 23043 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8265 /* 23047 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8266 /* 23051 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8267 /* 23056 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8268 /* 23060 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8269 /* 23064 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
8270 /* 23068 */ // MIs[4] Operand 1
8271 /* 23068 */ // No operand predicates
8272 /* 23068 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8273 /* 23079 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8274 /* 23081 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
8275 /* 23081 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8276 /* 23084 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8277 /* 23086 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8278 /* 23090 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
8279 /* 23094 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8280 /* 23097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8281 /* 23100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8282 /* 23106 */ GIR_RootConstrainSelectedInstOperands,
8283 /* 23107 */ // GIR_Coverage, 2080,
8284 /* 23107 */ GIR_EraseRootFromParent_Done,
8285 /* 23108 */ // Label 476: @23108
8286 /* 23108 */ GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(23241), // Rule ID 2362 //
8287 /* 23113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8288 /* 23116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8289 /* 23120 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8290 /* 23124 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8291 /* 23128 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8292 /* 23132 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8293 /* 23136 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8294 /* 23141 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8295 /* 23152 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8296 /* 23156 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8297 /* 23160 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8298 /* 23164 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8299 /* 23168 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8300 /* 23172 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR),
8301 /* 23176 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8302 /* 23180 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8303 /* 23184 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8304 /* 23189 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8305 /* 23193 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8306 /* 23197 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_15),
8307 /* 23201 */ // MIs[4] Operand 1
8308 /* 23201 */ // No operand predicates
8309 /* 23201 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8310 /* 23212 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8311 /* 23214 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (and:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh), 65535:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm1_15>>:$sh)
8312 /* 23214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8313 /* 23217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8314 /* 23219 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8315 /* 23223 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src2
8316 /* 23227 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8317 /* 23230 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8318 /* 23233 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8319 /* 23239 */ GIR_RootConstrainSelectedInstOperands,
8320 /* 23240 */ // GIR_Coverage, 2362,
8321 /* 23240 */ GIR_EraseRootFromParent_Done,
8322 /* 23241 */ // Label 477: @23241
8323 /* 23241 */ GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(23374), // Rule ID 201 //
8324 /* 23246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8325 /* 23249 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8326 /* 23253 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8327 /* 23257 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8328 /* 23261 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8329 /* 23265 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8330 /* 23269 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8331 /* 23274 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8332 /* 23285 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8333 /* 23289 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8334 /* 23293 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8335 /* 23297 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8336 /* 23301 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8337 /* 23305 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
8338 /* 23309 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8339 /* 23313 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8340 /* 23317 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8341 /* 23322 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8342 /* 23326 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8343 /* 23330 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
8344 /* 23334 */ // MIs[4] Operand 1
8345 /* 23334 */ // No operand predicates
8346 /* 23334 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8347 /* 23345 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8348 /* 23347 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8349 /* 23347 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8350 /* 23350 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8351 /* 23352 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8352 /* 23356 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8353 /* 23360 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8354 /* 23363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8355 /* 23366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8356 /* 23372 */ GIR_RootConstrainSelectedInstOperands,
8357 /* 23373 */ // GIR_Coverage, 201,
8358 /* 23373 */ GIR_EraseRootFromParent_Done,
8359 /* 23374 */ // Label 478: @23374
8360 /* 23374 */ GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(23507), // Rule ID 538 //
8361 /* 23379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8362 /* 23382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8363 /* 23386 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8364 /* 23390 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8365 /* 23394 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8366 /* 23398 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8367 /* 23402 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8368 /* 23407 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8369 /* 23418 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8370 /* 23422 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8371 /* 23426 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8372 /* 23430 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8373 /* 23434 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3]
8374 /* 23438 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SHL),
8375 /* 23442 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8376 /* 23446 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8377 /* 23450 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8378 /* 23455 */ GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/2, // MIs[4]
8379 /* 23459 */ GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8380 /* 23463 */ GIM_CheckI64ImmPredicate, /*MI*/4, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_pkh_lsl_amt),
8381 /* 23467 */ // MIs[4] Operand 1
8382 /* 23467 */ // No operand predicates
8383 /* 23467 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8384 /* 23478 */ GIM_CheckIsSafeToFold, /*NumInsns*/4,
8385 /* 23480 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_pkh_lsl_amt>>:$sh), 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$sh)
8386 /* 23480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8387 /* 23483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8388 /* 23485 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8389 /* 23489 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rm
8390 /* 23493 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/4, // sh
8391 /* 23496 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8392 /* 23499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8393 /* 23505 */ GIR_RootConstrainSelectedInstOperands,
8394 /* 23506 */ // GIR_Coverage, 538,
8395 /* 23506 */ GIR_EraseRootFromParent_Done,
8396 /* 23507 */ // Label 479: @23507
8397 /* 23507 */ GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(23612), // Rule ID 2076 //
8398 /* 23512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8399 /* 23515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8400 /* 23519 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8401 /* 23523 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8402 /* 23527 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8403 /* 23531 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8404 /* 23535 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8405 /* 23540 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8406 /* 23551 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8407 /* 23555 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8408 /* 23559 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8409 /* 23563 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8410 /* 23567 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8411 /* 23572 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8412 /* 23583 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8413 /* 23585 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
8414 /* 23585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8415 /* 23588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8416 /* 23590 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8417 /* 23594 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
8418 /* 23598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8419 /* 23601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8420 /* 23604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8421 /* 23610 */ GIR_RootConstrainSelectedInstOperands,
8422 /* 23611 */ // GIR_Coverage, 2076,
8423 /* 23611 */ GIR_EraseRootFromParent_Done,
8424 /* 23612 */ // Label 480: @23612
8425 /* 23612 */ GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(23717), // Rule ID 2358 //
8426 /* 23617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8427 /* 23620 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8428 /* 23624 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8429 /* 23628 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8430 /* 23632 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8431 /* 23636 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8432 /* 23640 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8433 /* 23645 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8434 /* 23656 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8435 /* 23660 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8436 /* 23664 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8437 /* 23668 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8438 /* 23672 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8439 /* 23677 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(4294901760),
8440 /* 23688 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8441 /* 23690 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
8442 /* 23690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8443 /* 23693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8444 /* 23695 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8445 /* 23699 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8446 /* 23703 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8447 /* 23706 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8448 /* 23709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8449 /* 23715 */ GIR_RootConstrainSelectedInstOperands,
8450 /* 23716 */ // GIR_Coverage, 2358,
8451 /* 23716 */ GIR_EraseRootFromParent_Done,
8452 /* 23717 */ // Label 481: @23717
8453 /* 23717 */ GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(23822), // Rule ID 6200 //
8454 /* 23722 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8455 /* 23725 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8456 /* 23729 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8457 /* 23733 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8458 /* 23737 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8459 /* 23741 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8460 /* 23745 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8461 /* 23750 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8462 /* 23761 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8463 /* 23765 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8464 /* 23769 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8465 /* 23773 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8466 /* 23777 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8467 /* 23782 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8468 /* 23793 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8469 /* 23795 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, 4294901760:{ *:[i32] }), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, 0:{ *:[i32] })
8470 /* 23795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8471 /* 23798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8472 /* 23800 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rn
8473 /* 23804 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
8474 /* 23808 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8475 /* 23811 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8476 /* 23814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8477 /* 23820 */ GIR_RootConstrainSelectedInstOperands,
8478 /* 23821 */ // GIR_Coverage, 6200,
8479 /* 23821 */ GIR_EraseRootFromParent_Done,
8480 /* 23822 */ // Label 482: @23822
8481 /* 23822 */ GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(23927), // Rule ID 6242 //
8482 /* 23827 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8483 /* 23830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8484 /* 23834 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8485 /* 23838 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8486 /* 23842 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8487 /* 23846 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8488 /* 23850 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8489 /* 23855 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8490 /* 23866 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8491 /* 23870 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND),
8492 /* 23874 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8493 /* 23878 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8494 /* 23882 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8495 /* 23887 */ GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(65535),
8496 /* 23898 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8497 /* 23900 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src2, 4294901760:{ *:[i32] }), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, 0:{ *:[i32] })
8498 /* 23900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8499 /* 23903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8500 /* 23905 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1
8501 /* 23909 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8502 /* 23913 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
8503 /* 23916 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8504 /* 23919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8505 /* 23925 */ GIR_RootConstrainSelectedInstOperands,
8506 /* 23926 */ // GIR_Coverage, 6242,
8507 /* 23926 */ GIR_EraseRootFromParent_Done,
8508 /* 23927 */ // Label 483: @23927
8509 /* 23927 */ GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(24033), // Rule ID 2079 //
8510 /* 23932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8511 /* 23935 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8512 /* 23939 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8513 /* 23943 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8514 /* 23947 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8515 /* 23951 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8516 /* 23955 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8517 /* 23960 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8518 /* 23971 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8519 /* 23975 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
8520 /* 23979 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8521 /* 23983 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8522 /* 23987 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8523 /* 23992 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8524 /* 23996 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8525 /* 24000 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8526 /* 24004 */ // MIs[3] Operand 1
8527 /* 24004 */ // No operand predicates
8528 /* 24004 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8529 /* 24006 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8530 /* 24006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8531 /* 24009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8532 /* 24011 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8533 /* 24015 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8534 /* 24019 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8535 /* 24022 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8536 /* 24025 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8537 /* 24031 */ GIR_RootConstrainSelectedInstOperands,
8538 /* 24032 */ // GIR_Coverage, 2079,
8539 /* 24032 */ GIR_EraseRootFromParent_Done,
8540 /* 24033 */ // Label 484: @24033
8541 /* 24033 */ GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(24139), // Rule ID 2361 //
8542 /* 24038 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8543 /* 24041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8544 /* 24045 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8545 /* 24049 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8546 /* 24053 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8547 /* 24057 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8548 /* 24061 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8549 /* 24066 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8550 /* 24077 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8551 /* 24081 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_ASHR),
8552 /* 24085 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8553 /* 24089 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8554 /* 24093 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8555 /* 24098 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8556 /* 24102 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8557 /* 24106 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8558 /* 24110 */ // MIs[3] Operand 1
8559 /* 24110 */ // No operand predicates
8560 /* 24110 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8561 /* 24112 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8562 /* 24112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8563 /* 24115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8564 /* 24117 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8565 /* 24121 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8566 /* 24125 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8567 /* 24128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8568 /* 24131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8569 /* 24137 */ GIR_RootConstrainSelectedInstOperands,
8570 /* 24138 */ // GIR_Coverage, 2361,
8571 /* 24138 */ GIR_EraseRootFromParent_Done,
8572 /* 24139 */ // Label 485: @24139
8573 /* 24139 */ GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(24245), // Rule ID 2078 //
8574 /* 24144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8575 /* 24147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8576 /* 24151 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8577 /* 24155 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8578 /* 24159 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8579 /* 24163 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8580 /* 24167 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8581 /* 24172 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8582 /* 24183 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8583 /* 24187 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
8584 /* 24191 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8585 /* 24195 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8586 /* 24199 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8587 /* 24204 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8588 /* 24208 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8589 /* 24212 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8590 /* 24216 */ // MIs[3] Operand 1
8591 /* 24216 */ // No operand predicates
8592 /* 24216 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8593 /* 24218 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8594 /* 24218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8595 /* 24221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8596 /* 24223 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8597 /* 24227 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8598 /* 24231 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8599 /* 24234 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8600 /* 24237 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8601 /* 24243 */ GIR_RootConstrainSelectedInstOperands,
8602 /* 24244 */ // GIR_Coverage, 2078,
8603 /* 24244 */ GIR_EraseRootFromParent_Done,
8604 /* 24245 */ // Label 486: @24245
8605 /* 24245 */ GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(24351), // Rule ID 2360 //
8606 /* 24250 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8607 /* 24253 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8608 /* 24257 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8609 /* 24261 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8610 /* 24265 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8611 /* 24269 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8612 /* 24273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8613 /* 24278 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(4294901760),
8614 /* 24289 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8615 /* 24293 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR),
8616 /* 24297 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8617 /* 24301 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8618 /* 24305 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8619 /* 24310 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8620 /* 24314 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8621 /* 24318 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8622 /* 24322 */ // MIs[3] Operand 1
8623 /* 24322 */ // No operand predicates
8624 /* 24322 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8625 /* 24324 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] }), (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8626 /* 24324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8627 /* 24327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8628 /* 24329 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8629 /* 24333 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8630 /* 24337 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8631 /* 24340 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8632 /* 24343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8633 /* 24349 */ GIR_RootConstrainSelectedInstOperands,
8634 /* 24350 */ // GIR_Coverage, 2360,
8635 /* 24350 */ GIR_EraseRootFromParent_Done,
8636 /* 24351 */ // Label 487: @24351
8637 /* 24351 */ GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(24457), // Rule ID 2077 //
8638 /* 24356 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8639 /* 24359 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8640 /* 24363 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8641 /* 24367 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8642 /* 24371 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8643 /* 24375 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8644 /* 24379 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8645 /* 24384 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8646 /* 24395 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8647 /* 24399 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
8648 /* 24403 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8649 /* 24407 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8650 /* 24411 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8651 /* 24416 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8652 /* 24420 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8653 /* 24424 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8654 /* 24428 */ // MIs[3] Operand 1
8655 /* 24428 */ // No operand predicates
8656 /* 24428 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8657 /* 24430 */ // (or:{ *:[i32] } (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] }), (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8658 /* 24430 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8659 /* 24433 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8660 /* 24435 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
8661 /* 24439 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Rm
8662 /* 24443 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8663 /* 24446 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8664 /* 24449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8665 /* 24455 */ GIR_RootConstrainSelectedInstOperands,
8666 /* 24456 */ // GIR_Coverage, 2077,
8667 /* 24456 */ GIR_EraseRootFromParent_Done,
8668 /* 24457 */ // Label 488: @24457
8669 /* 24457 */ GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(24563), // Rule ID 2359 //
8670 /* 24462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8671 /* 24465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8672 /* 24469 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8673 /* 24473 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND),
8674 /* 24477 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8675 /* 24481 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8676 /* 24485 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8677 /* 24490 */ GIM_CheckConstantInt, /*MI*/1, /*Op*/2, GIMT_Encode8(65535),
8678 /* 24501 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
8679 /* 24505 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SHL),
8680 /* 24509 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
8681 /* 24513 */ GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32,
8682 /* 24517 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8683 /* 24522 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3]
8684 /* 24526 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8685 /* 24530 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8686 /* 24534 */ // MIs[3] Operand 1
8687 /* 24534 */ // No operand predicates
8688 /* 24534 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8689 /* 24536 */ // (or:{ *:[i32] } (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] }), (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8690 /* 24536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8691 /* 24539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8692 /* 24541 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
8693 /* 24545 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2
8694 /* 24549 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // sh
8695 /* 24552 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8696 /* 24555 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8697 /* 24561 */ GIR_RootConstrainSelectedInstOperands,
8698 /* 24562 */ // GIR_Coverage, 2359,
8699 /* 24562 */ GIR_EraseRootFromParent_Done,
8700 /* 24563 */ // Label 489: @24563
8701 /* 24563 */ GIM_Try, /*On fail goto*//*Label 490*/ GIMT_Encode4(24669), // Rule ID 6203 //
8702 /* 24568 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8703 /* 24571 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8704 /* 24575 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8705 /* 24579 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
8706 /* 24583 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8707 /* 24587 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8708 /* 24591 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8709 /* 24596 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8710 /* 24600 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8711 /* 24604 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8712 /* 24608 */ // MIs[2] Operand 1
8713 /* 24608 */ // No operand predicates
8714 /* 24608 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8715 /* 24612 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8716 /* 24616 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8717 /* 24620 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8718 /* 24624 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8719 /* 24629 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8720 /* 24640 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8721 /* 24642 */ // (or:{ *:[i32] } (sra:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8722 /* 24642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8723 /* 24645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8724 /* 24647 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8725 /* 24651 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8726 /* 24655 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8727 /* 24658 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8728 /* 24661 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8729 /* 24667 */ GIR_RootConstrainSelectedInstOperands,
8730 /* 24668 */ // GIR_Coverage, 6203,
8731 /* 24668 */ GIR_EraseRootFromParent_Done,
8732 /* 24669 */ // Label 490: @24669
8733 /* 24669 */ GIM_Try, /*On fail goto*//*Label 491*/ GIMT_Encode4(24775), // Rule ID 6245 //
8734 /* 24674 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8735 /* 24677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8736 /* 24681 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8737 /* 24685 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR),
8738 /* 24689 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8739 /* 24693 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8740 /* 24697 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8741 /* 24702 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8742 /* 24706 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8743 /* 24710 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8744 /* 24714 */ // MIs[2] Operand 1
8745 /* 24714 */ // No operand predicates
8746 /* 24714 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8747 /* 24718 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8748 /* 24722 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8749 /* 24726 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8750 /* 24730 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8751 /* 24735 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8752 /* 24746 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8753 /* 24748 */ // (or:{ *:[i32] } (sra:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8754 /* 24748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8755 /* 24751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8756 /* 24753 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8757 /* 24757 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8758 /* 24761 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8759 /* 24764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8760 /* 24767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8761 /* 24773 */ GIR_RootConstrainSelectedInstOperands,
8762 /* 24774 */ // GIR_Coverage, 6245,
8763 /* 24774 */ GIR_EraseRootFromParent_Done,
8764 /* 24775 */ // Label 491: @24775
8765 /* 24775 */ GIM_Try, /*On fail goto*//*Label 492*/ GIMT_Encode4(24881), // Rule ID 6202 //
8766 /* 24780 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8767 /* 24783 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8768 /* 24787 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8769 /* 24791 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
8770 /* 24795 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8771 /* 24799 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8772 /* 24803 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8773 /* 24808 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8774 /* 24812 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8775 /* 24816 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8776 /* 24820 */ // MIs[2] Operand 1
8777 /* 24820 */ // No operand predicates
8778 /* 24820 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8779 /* 24824 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8780 /* 24828 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8781 /* 24832 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8782 /* 24836 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8783 /* 24841 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8784 /* 24852 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8785 /* 24854 */ // (or:{ *:[i32] } (srl:{ *:[i32] } GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (PKHTB:{ *:[i32] } GPRnopc:{ *:[i32] }:$src1, GPRnopc:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8786 /* 24854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHTB),
8787 /* 24857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8788 /* 24859 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8789 /* 24863 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8790 /* 24867 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8791 /* 24870 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8792 /* 24873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8793 /* 24879 */ GIR_RootConstrainSelectedInstOperands,
8794 /* 24880 */ // GIR_Coverage, 6202,
8795 /* 24880 */ GIR_EraseRootFromParent_Done,
8796 /* 24881 */ // Label 492: @24881
8797 /* 24881 */ GIM_Try, /*On fail goto*//*Label 493*/ GIMT_Encode4(24987), // Rule ID 6244 //
8798 /* 24886 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8799 /* 24889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8800 /* 24893 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8801 /* 24897 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR),
8802 /* 24901 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8803 /* 24905 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8804 /* 24909 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8805 /* 24914 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8806 /* 24918 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8807 /* 24922 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16),
8808 /* 24926 */ // MIs[2] Operand 1
8809 /* 24926 */ // No operand predicates
8810 /* 24926 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8811 /* 24930 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8812 /* 24934 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8813 /* 24938 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8814 /* 24942 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8815 /* 24947 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(4294901760),
8816 /* 24958 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8817 /* 24960 */ // (or:{ *:[i32] } (srl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 4294901760:{ *:[i32] })) => (t2PKHTB:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16>>:$sh)
8818 /* 24960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHTB),
8819 /* 24963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8820 /* 24965 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8821 /* 24969 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8822 /* 24973 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8823 /* 24976 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8824 /* 24979 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8825 /* 24985 */ GIR_RootConstrainSelectedInstOperands,
8826 /* 24986 */ // GIR_Coverage, 6244,
8827 /* 24986 */ GIR_EraseRootFromParent_Done,
8828 /* 24987 */ // Label 493: @24987
8829 /* 24987 */ GIM_Try, /*On fail goto*//*Label 494*/ GIMT_Encode4(25093), // Rule ID 6201 //
8830 /* 24992 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
8831 /* 24995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8832 /* 24999 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8833 /* 25003 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
8834 /* 25007 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8835 /* 25011 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8836 /* 25015 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8837 /* 25020 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8838 /* 25024 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8839 /* 25028 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8840 /* 25032 */ // MIs[2] Operand 1
8841 /* 25032 */ // No operand predicates
8842 /* 25032 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8843 /* 25036 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8844 /* 25040 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8845 /* 25044 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8846 /* 25048 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
8847 /* 25053 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535),
8848 /* 25064 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8849 /* 25066 */ // (or:{ *:[i32] } (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, 65535:{ *:[i32] })) => (PKHBT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8850 /* 25066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::PKHBT),
8851 /* 25069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8852 /* 25071 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // Rn
8853 /* 25075 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
8854 /* 25079 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8855 /* 25082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8856 /* 25085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8857 /* 25091 */ GIR_RootConstrainSelectedInstOperands,
8858 /* 25092 */ // GIR_Coverage, 6201,
8859 /* 25092 */ GIR_EraseRootFromParent_Done,
8860 /* 25093 */ // Label 494: @25093
8861 /* 25093 */ GIM_Try, /*On fail goto*//*Label 495*/ GIMT_Encode4(25199), // Rule ID 6243 //
8862 /* 25098 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
8863 /* 25101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8864 /* 25105 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8865 /* 25109 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
8866 /* 25113 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8867 /* 25117 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8868 /* 25121 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8869 /* 25126 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8870 /* 25130 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8871 /* 25134 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm16_31),
8872 /* 25138 */ // MIs[2] Operand 1
8873 /* 25138 */ // No operand predicates
8874 /* 25138 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3]
8875 /* 25142 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND),
8876 /* 25146 */ GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32,
8877 /* 25150 */ GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32,
8878 /* 25154 */ GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8879 /* 25159 */ GIM_CheckConstantInt, /*MI*/3, /*Op*/2, GIMT_Encode8(65535),
8880 /* 25170 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
8881 /* 25172 */ // (or:{ *:[i32] } (shl:{ *:[i32] } rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh), (and:{ *:[i32] } rGPR:{ *:[i32] }:$src1, 65535:{ *:[i32] })) => (t2PKHBT:{ *:[i32] } rGPR:{ *:[i32] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] })<<P:Predicate_imm16_31>>:$sh)
8882 /* 25172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2PKHBT),
8883 /* 25175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8884 /* 25177 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // src1
8885 /* 25181 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2
8886 /* 25185 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // sh
8887 /* 25188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8888 /* 25191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8889 /* 25197 */ GIR_RootConstrainSelectedInstOperands,
8890 /* 25198 */ // GIR_Coverage, 6243,
8891 /* 25198 */ GIR_EraseRootFromParent_Done,
8892 /* 25199 */ // Label 495: @25199
8893 /* 25199 */ GIM_Try, /*On fail goto*//*Label 496*/ GIMT_Encode4(25276), // Rule ID 5955 //
8894 /* 25204 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
8895 /* 25207 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8896 /* 25211 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8897 /* 25215 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8898 /* 25219 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8899 /* 25223 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8900 /* 25227 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
8901 /* 25231 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8902 /* 25235 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8903 /* 25239 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8904 /* 25243 */ // MIs[2] Operand 1
8905 /* 25243 */ // No operand predicates
8906 /* 25243 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8907 /* 25247 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8908 /* 25249 */ // (or:{ *:[i32] } (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8909 /* 25249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8910 /* 25252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8911 /* 25254 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
8912 /* 25256 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8913 /* 25259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8914 /* 25262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8915 /* 25268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8916 /* 25274 */ GIR_RootConstrainSelectedInstOperands,
8917 /* 25275 */ // GIR_Coverage, 5955,
8918 /* 25275 */ GIR_EraseRootFromParent_Done,
8919 /* 25276 */ // Label 496: @25276
8920 /* 25276 */ GIM_Try, /*On fail goto*//*Label 497*/ GIMT_Encode4(25353), // Rule ID 5954 //
8921 /* 25281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
8922 /* 25284 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8923 /* 25288 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
8924 /* 25292 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8925 /* 25296 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8926 /* 25300 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8927 /* 25304 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8928 /* 25308 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8929 /* 25312 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8930 /* 25316 */ // MIs[2] Operand 1
8931 /* 25316 */ // No operand predicates
8932 /* 25316 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
8933 /* 25320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8934 /* 25324 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8935 /* 25326 */ // (or:{ *:[i32] } (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8936 /* 25326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8937 /* 25329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8938 /* 25331 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
8939 /* 25333 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8940 /* 25336 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8941 /* 25339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8942 /* 25345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8943 /* 25351 */ GIR_RootConstrainSelectedInstOperands,
8944 /* 25352 */ // GIR_Coverage, 5954,
8945 /* 25352 */ GIR_EraseRootFromParent_Done,
8946 /* 25353 */ // Label 497: @25353
8947 /* 25353 */ GIM_Try, /*On fail goto*//*Label 498*/ GIMT_Encode4(25430), // Rule ID 5953 //
8948 /* 25358 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
8949 /* 25361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8950 /* 25365 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8951 /* 25369 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8952 /* 25373 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8953 /* 25377 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8954 /* 25381 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8955 /* 25385 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 255,
8956 /* 25389 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
8957 /* 25393 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8958 /* 25397 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8959 /* 25401 */ // MIs[2] Operand 1
8960 /* 25401 */ // No operand predicates
8961 /* 25401 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8962 /* 25403 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm)) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8963 /* 25403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8964 /* 25406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8965 /* 25408 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8966 /* 25410 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8967 /* 25413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8968 /* 25416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8969 /* 25422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8970 /* 25428 */ GIR_RootConstrainSelectedInstOperands,
8971 /* 25429 */ // GIR_Coverage, 5953,
8972 /* 25429 */ GIR_EraseRootFromParent_Done,
8973 /* 25430 */ // Label 498: @25430
8974 /* 25430 */ GIM_Try, /*On fail goto*//*Label 499*/ GIMT_Encode4(25507), // Rule ID 495 //
8975 /* 25435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
8976 /* 25438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8977 /* 25442 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
8978 /* 25446 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
8979 /* 25450 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
8980 /* 25454 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
8981 /* 25458 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
8982 /* 25462 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
8983 /* 25466 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
8984 /* 25470 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
8985 /* 25474 */ // MIs[2] Operand 1
8986 /* 25474 */ // No operand predicates
8987 /* 25474 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
8988 /* 25478 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
8989 /* 25480 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] })) => (t2ORNri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
8990 /* 25480 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNri),
8991 /* 25483 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
8992 /* 25485 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
8993 /* 25487 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // imm
8994 /* 25490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
8995 /* 25493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8996 /* 25499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
8997 /* 25505 */ GIR_RootConstrainSelectedInstOperands,
8998 /* 25506 */ // GIR_Coverage, 495,
8999 /* 25506 */ GIR_EraseRootFromParent_Done,
9000 /* 25507 */ // Label 499: @25507
9001 /* 25507 */ GIM_Try, /*On fail goto*//*Label 500*/ GIMT_Encode4(25578), // Rule ID 5956 //
9002 /* 25512 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9003 /* 25515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9004 /* 25519 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9005 /* 25523 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9006 /* 25527 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
9007 /* 25531 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
9008 /* 25535 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9009 /* 25540 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
9010 /* 25544 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9011 /* 25548 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9012 /* 25550 */ // (or:{ *:[i32] } (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }), rGPR:{ *:[i32] }:$Rn) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
9013 /* 25550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr),
9014 /* 25553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9015 /* 25555 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
9016 /* 25557 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
9017 /* 25561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9018 /* 25564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9019 /* 25570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9020 /* 25576 */ GIR_RootConstrainSelectedInstOperands,
9021 /* 25577 */ // GIR_Coverage, 5956,
9022 /* 25577 */ GIR_EraseRootFromParent_Done,
9023 /* 25578 */ // Label 500: @25578
9024 /* 25578 */ GIM_Try, /*On fail goto*//*Label 501*/ GIMT_Encode4(25649), // Rule ID 496 //
9025 /* 25583 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9026 /* 25586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9027 /* 25590 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9028 /* 25594 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9029 /* 25598 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR),
9030 /* 25602 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
9031 /* 25606 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
9032 /* 25610 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9033 /* 25615 */ GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 255,
9034 /* 25619 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9035 /* 25621 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] })) => (t2ORNrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
9036 /* 25621 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORNrr),
9037 /* 25624 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9038 /* 25626 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9039 /* 25628 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
9040 /* 25632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9041 /* 25635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9042 /* 25641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9043 /* 25647 */ GIR_RootConstrainSelectedInstOperands,
9044 /* 25648 */ // GIR_Coverage, 496,
9045 /* 25648 */ GIR_EraseRootFromParent_Done,
9046 /* 25649 */ // Label 501: @25649
9047 /* 25649 */ GIM_Try, /*On fail goto*//*Label 502*/ GIMT_Encode4(25704), // Rule ID 2009 //
9048 /* 25654 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM),
9049 /* 25657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
9050 /* 25661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9051 /* 25665 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760),
9052 /* 25676 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (MOVTi16:{ *:[i32] } GPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
9053 /* 25676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVTi16),
9054 /* 25679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9055 /* 25681 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
9056 /* 25683 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535),
9057 /* 25693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9058 /* 25696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9059 /* 25702 */ GIR_RootConstrainSelectedInstOperands,
9060 /* 25703 */ // GIR_Coverage, 2009,
9061 /* 25703 */ GIR_EraseRootFromParent_Done,
9062 /* 25704 */ // Label 502: @25704
9063 /* 25704 */ GIM_Try, /*On fail goto*//*Label 503*/ GIMT_Encode4(25759), // Rule ID 2255 //
9064 /* 25709 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9065 /* 25712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9066 /* 25716 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9067 /* 25720 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/2, GIMT_Encode8(4294901760),
9068 /* 25731 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$src, 4294901760:{ *:[i32] }) => (t2MOVTi16:{ *:[i32] } rGPR:{ *:[i32] }:$src, 65535:{ *:[i32] })
9069 /* 25731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVTi16),
9070 /* 25734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9071 /* 25736 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
9072 /* 25738 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(65535),
9073 /* 25748 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9074 /* 25751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9075 /* 25757 */ GIR_RootConstrainSelectedInstOperands,
9076 /* 25758 */ // GIR_Coverage, 2255,
9077 /* 25758 */ GIR_EraseRootFromParent_Done,
9078 /* 25759 */ // Label 503: @25759
9079 /* 25759 */ GIM_Try, /*On fail goto*//*Label 504*/ GIMT_Encode4(25816), // Rule ID 150 //
9080 /* 25764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
9081 /* 25767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9082 /* 25771 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9083 /* 25775 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9084 /* 25779 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9085 /* 25783 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
9086 /* 25787 */ // MIs[1] Operand 1
9087 /* 25787 */ // No operand predicates
9088 /* 25787 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9089 /* 25789 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (ORRri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
9090 /* 25789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRri),
9091 /* 25792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9092 /* 25794 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9093 /* 25796 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9094 /* 25799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9095 /* 25802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9096 /* 25808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9097 /* 25814 */ GIR_RootConstrainSelectedInstOperands,
9098 /* 25815 */ // GIR_Coverage, 150,
9099 /* 25815 */ GIR_EraseRootFromParent_Done,
9100 /* 25816 */ // Label 504: @25816
9101 /* 25816 */ GIM_Try, /*On fail goto*//*Label 505*/ GIMT_Encode4(25873), // Rule ID 483 //
9102 /* 25821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9103 /* 25824 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9104 /* 25828 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9105 /* 25832 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9106 /* 25836 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9107 /* 25840 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
9108 /* 25844 */ // MIs[1] Operand 1
9109 /* 25844 */ // No operand predicates
9110 /* 25844 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9111 /* 25846 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2ORRri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
9112 /* 25846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRri),
9113 /* 25849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9114 /* 25851 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9115 /* 25853 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9116 /* 25856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9117 /* 25859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9118 /* 25865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9119 /* 25871 */ GIR_RootConstrainSelectedInstOperands,
9120 /* 25872 */ // GIR_Coverage, 483,
9121 /* 25872 */ GIR_EraseRootFromParent_Done,
9122 /* 25873 */ // Label 505: @25873
9123 /* 25873 */ GIM_Try, /*On fail goto*//*Label 506*/ GIMT_Encode4(25919), // Rule ID 151 //
9124 /* 25878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
9125 /* 25881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9126 /* 25885 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9127 /* 25889 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9128 /* 25893 */ // (or:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (ORRrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
9129 /* 25893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ORRrr),
9130 /* 25896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9131 /* 25898 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9132 /* 25900 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9133 /* 25902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9134 /* 25905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9135 /* 25911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9136 /* 25917 */ GIR_RootConstrainSelectedInstOperands,
9137 /* 25918 */ // GIR_Coverage, 151,
9138 /* 25918 */ GIR_EraseRootFromParent_Done,
9139 /* 25919 */ // Label 506: @25919
9140 /* 25919 */ GIM_Try, /*On fail goto*//*Label 507*/ GIMT_Encode4(25965), // Rule ID 324 //
9141 /* 25924 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
9142 /* 25927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9143 /* 25931 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9144 /* 25935 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9145 /* 25939 */ // (or:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tORR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
9146 /* 25939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tORR),
9147 /* 25942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
9148 /* 25944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
9149 /* 25950 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9150 /* 25952 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9151 /* 25954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9152 /* 25957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9153 /* 25963 */ GIR_RootConstrainSelectedInstOperands,
9154 /* 25964 */ // GIR_Coverage, 324,
9155 /* 25964 */ GIR_EraseRootFromParent_Done,
9156 /* 25965 */ // Label 507: @25965
9157 /* 25965 */ GIM_Try, /*On fail goto*//*Label 508*/ GIMT_Encode4(26011), // Rule ID 484 //
9158 /* 25970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9159 /* 25973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9160 /* 25977 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9161 /* 25981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9162 /* 25985 */ // (or:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ORRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
9163 /* 25985 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
9164 /* 25988 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9165 /* 25990 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9166 /* 25992 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9167 /* 25994 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9168 /* 25997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9169 /* 26003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9170 /* 26009 */ GIR_RootConstrainSelectedInstOperands,
9171 /* 26010 */ // GIR_Coverage, 484,
9172 /* 26010 */ GIR_EraseRootFromParent_Done,
9173 /* 26011 */ // Label 508: @26011
9174 /* 26011 */ GIM_Reject,
9175 /* 26012 */ // Label 463: @26012
9176 /* 26012 */ GIM_Reject,
9177 /* 26013 */ // Label 450: @26013
9178 /* 26013 */ GIM_Try, /*On fail goto*//*Label 509*/ GIMT_Encode4(26059), // Rule ID 2882 //
9179 /* 26018 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9180 /* 26021 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
9181 /* 26024 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
9182 /* 26027 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9183 /* 26031 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9184 /* 26035 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9185 /* 26039 */ // (or:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VORRd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
9186 /* 26039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
9187 /* 26042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9188 /* 26044 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9189 /* 26046 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9190 /* 26048 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9191 /* 26051 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9192 /* 26057 */ GIR_RootConstrainSelectedInstOperands,
9193 /* 26058 */ // GIR_Coverage, 2882,
9194 /* 26058 */ GIR_EraseRootFromParent_Done,
9195 /* 26059 */ // Label 509: @26059
9196 /* 26059 */ GIM_Reject,
9197 /* 26060 */ // Label 451: @26060
9198 /* 26060 */ GIM_Try, /*On fail goto*//*Label 510*/ GIMT_Encode4(26177), // Rule ID 1995 //
9199 /* 26065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9200 /* 26068 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1,
9201 /* 26071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1,
9202 /* 26074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9203 /* 26078 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9204 /* 26082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9205 /* 26086 */ // (or:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9206 /* 26086 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9207 /* 26089 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9208 /* 26093 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9209 /* 26098 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9210 /* 26102 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9211 /* 26107 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9212 /* 26110 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9213 /* 26114 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9214 /* 26119 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9215 /* 26123 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9216 /* 26128 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9217 /* 26131 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
9218 /* 26135 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9219 /* 26140 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9220 /* 26143 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9221 /* 26146 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9222 /* 26149 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9223 /* 26155 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9224 /* 26161 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9225 /* 26163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9226 /* 26166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9227 /* 26168 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9228 /* 26171 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9229 /* 26176 */ // GIR_Coverage, 1995,
9230 /* 26176 */ GIR_EraseRootFromParent_Done,
9231 /* 26177 */ // Label 510: @26177
9232 /* 26177 */ GIM_Reject,
9233 /* 26178 */ // Label 452: @26178
9234 /* 26178 */ GIM_Try, /*On fail goto*//*Label 511*/ GIMT_Encode4(26224), // Rule ID 1298 //
9235 /* 26183 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9236 /* 26186 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
9237 /* 26189 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
9238 /* 26192 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9239 /* 26196 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9240 /* 26200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9241 /* 26204 */ // (or:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VORRd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
9242 /* 26204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
9243 /* 26207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9244 /* 26209 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9245 /* 26211 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9246 /* 26213 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9247 /* 26216 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9248 /* 26222 */ GIR_RootConstrainSelectedInstOperands,
9249 /* 26223 */ // GIR_Coverage, 1298,
9250 /* 26223 */ GIR_EraseRootFromParent_Done,
9251 /* 26224 */ // Label 511: @26224
9252 /* 26224 */ GIM_Reject,
9253 /* 26225 */ // Label 453: @26225
9254 /* 26225 */ GIM_Try, /*On fail goto*//*Label 512*/ GIMT_Encode4(26338),
9255 /* 26230 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
9256 /* 26233 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9257 /* 26236 */ GIM_Try, /*On fail goto*//*Label 513*/ GIMT_Encode4(26276), // Rule ID 2885 //
9258 /* 26241 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9259 /* 26244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9260 /* 26248 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9261 /* 26252 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9262 /* 26256 */ // (or:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VORRq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
9263 /* 26256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9264 /* 26259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9265 /* 26261 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9266 /* 26263 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9267 /* 26265 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9268 /* 26268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9269 /* 26274 */ GIR_RootConstrainSelectedInstOperands,
9270 /* 26275 */ // GIR_Coverage, 2885,
9271 /* 26275 */ GIR_EraseRootFromParent_Done,
9272 /* 26276 */ // Label 513: @26276
9273 /* 26276 */ GIM_Try, /*On fail goto*//*Label 514*/ GIMT_Encode4(26337), // Rule ID 3742 //
9274 /* 26281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9275 /* 26284 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9276 /* 26288 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9277 /* 26292 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9278 /* 26296 */ // (or:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VORR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
9279 /* 26296 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9280 /* 26299 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9281 /* 26303 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9282 /* 26308 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9283 /* 26311 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9284 /* 26313 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9285 /* 26315 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9286 /* 26317 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9287 /* 26320 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9288 /* 26326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9289 /* 26332 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9290 /* 26335 */ GIR_RootConstrainSelectedInstOperands,
9291 /* 26336 */ // GIR_Coverage, 3742,
9292 /* 26336 */ GIR_EraseRootFromParent_Done,
9293 /* 26337 */ // Label 514: @26337
9294 /* 26337 */ GIM_Reject,
9295 /* 26338 */ // Label 512: @26338
9296 /* 26338 */ GIM_Reject,
9297 /* 26339 */ // Label 454: @26339
9298 /* 26339 */ GIM_Try, /*On fail goto*//*Label 515*/ GIMT_Encode4(26456), // Rule ID 1996 //
9299 /* 26344 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9300 /* 26347 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1,
9301 /* 26350 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1,
9302 /* 26353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9303 /* 26357 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9304 /* 26361 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9305 /* 26365 */ // (or:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9306 /* 26365 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9307 /* 26368 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9308 /* 26372 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9309 /* 26377 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9310 /* 26381 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9311 /* 26386 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9312 /* 26389 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9313 /* 26393 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9314 /* 26398 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9315 /* 26402 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9316 /* 26407 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9317 /* 26410 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
9318 /* 26414 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9319 /* 26419 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9320 /* 26422 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9321 /* 26425 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9322 /* 26428 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9323 /* 26434 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9324 /* 26440 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9325 /* 26442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9326 /* 26445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9327 /* 26447 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9328 /* 26450 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9329 /* 26455 */ // GIR_Coverage, 1996,
9330 /* 26455 */ GIR_EraseRootFromParent_Done,
9331 /* 26456 */ // Label 515: @26456
9332 /* 26456 */ GIM_Reject,
9333 /* 26457 */ // Label 455: @26457
9334 /* 26457 */ GIM_Try, /*On fail goto*//*Label 516*/ GIMT_Encode4(26503), // Rule ID 2881 //
9335 /* 26462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9336 /* 26465 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
9337 /* 26468 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
9338 /* 26471 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9339 /* 26475 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9340 /* 26479 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9341 /* 26483 */ // (or:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VORRd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
9342 /* 26483 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
9343 /* 26486 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9344 /* 26488 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9345 /* 26490 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9346 /* 26492 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9347 /* 26495 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9348 /* 26501 */ GIR_RootConstrainSelectedInstOperands,
9349 /* 26502 */ // GIR_Coverage, 2881,
9350 /* 26502 */ GIR_EraseRootFromParent_Done,
9351 /* 26503 */ // Label 516: @26503
9352 /* 26503 */ GIM_Reject,
9353 /* 26504 */ // Label 456: @26504
9354 /* 26504 */ GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(26617),
9355 /* 26509 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
9356 /* 26512 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9357 /* 26515 */ GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(26555), // Rule ID 1299 //
9358 /* 26520 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9359 /* 26523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9360 /* 26527 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9361 /* 26531 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9362 /* 26535 */ // (or:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VORRq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
9363 /* 26535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9364 /* 26538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9365 /* 26540 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9366 /* 26542 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9367 /* 26544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9368 /* 26547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9369 /* 26553 */ GIR_RootConstrainSelectedInstOperands,
9370 /* 26554 */ // GIR_Coverage, 1299,
9371 /* 26554 */ GIR_EraseRootFromParent_Done,
9372 /* 26555 */ // Label 518: @26555
9373 /* 26555 */ GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(26616), // Rule ID 3738 //
9374 /* 26560 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9375 /* 26563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9376 /* 26567 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9377 /* 26571 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9378 /* 26575 */ // (or:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VORR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
9379 /* 26575 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9380 /* 26578 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9381 /* 26582 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9382 /* 26587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9383 /* 26590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9384 /* 26592 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9385 /* 26594 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9386 /* 26596 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9387 /* 26599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9388 /* 26605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9389 /* 26611 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9390 /* 26614 */ GIR_RootConstrainSelectedInstOperands,
9391 /* 26615 */ // GIR_Coverage, 3738,
9392 /* 26615 */ GIR_EraseRootFromParent_Done,
9393 /* 26616 */ // Label 519: @26616
9394 /* 26616 */ GIM_Reject,
9395 /* 26617 */ // Label 517: @26617
9396 /* 26617 */ GIM_Reject,
9397 /* 26618 */ // Label 457: @26618
9398 /* 26618 */ GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(26735), // Rule ID 1997 //
9399 /* 26623 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9400 /* 26626 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1,
9401 /* 26629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1,
9402 /* 26632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9403 /* 26636 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9404 /* 26640 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9405 /* 26644 */ // (or:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9406 /* 26644 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9407 /* 26647 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9408 /* 26651 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9409 /* 26656 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9410 /* 26660 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9411 /* 26665 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9412 /* 26668 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9413 /* 26672 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9414 /* 26677 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9415 /* 26681 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9416 /* 26686 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9417 /* 26689 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
9418 /* 26693 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9419 /* 26698 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9420 /* 26701 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9421 /* 26704 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9422 /* 26707 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9423 /* 26713 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9424 /* 26719 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9425 /* 26721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9426 /* 26724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9427 /* 26726 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9428 /* 26729 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9429 /* 26734 */ // GIR_Coverage, 1997,
9430 /* 26734 */ GIR_EraseRootFromParent_Done,
9431 /* 26735 */ // Label 520: @26735
9432 /* 26735 */ GIM_Reject,
9433 /* 26736 */ // Label 458: @26736
9434 /* 26736 */ GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(26782), // Rule ID 2880 //
9435 /* 26741 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9436 /* 26744 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
9437 /* 26747 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
9438 /* 26750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9439 /* 26754 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9440 /* 26758 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9441 /* 26762 */ // (or:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VORRd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
9442 /* 26762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRd),
9443 /* 26765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9444 /* 26767 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9445 /* 26769 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9446 /* 26771 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9447 /* 26774 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9448 /* 26780 */ GIR_RootConstrainSelectedInstOperands,
9449 /* 26781 */ // GIR_Coverage, 2880,
9450 /* 26781 */ GIR_EraseRootFromParent_Done,
9451 /* 26782 */ // Label 521: @26782
9452 /* 26782 */ GIM_Reject,
9453 /* 26783 */ // Label 459: @26783
9454 /* 26783 */ GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(26896),
9455 /* 26788 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
9456 /* 26791 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
9457 /* 26794 */ GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(26834), // Rule ID 2884 //
9458 /* 26799 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9459 /* 26802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9460 /* 26806 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9461 /* 26810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9462 /* 26814 */ // (or:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VORRq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
9463 /* 26814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9464 /* 26817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9465 /* 26819 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9466 /* 26821 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9467 /* 26823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9468 /* 26826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9469 /* 26832 */ GIR_RootConstrainSelectedInstOperands,
9470 /* 26833 */ // GIR_Coverage, 2884,
9471 /* 26833 */ GIR_EraseRootFromParent_Done,
9472 /* 26834 */ // Label 523: @26834
9473 /* 26834 */ GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(26895), // Rule ID 3734 //
9474 /* 26839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9475 /* 26842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9476 /* 26846 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9477 /* 26850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9478 /* 26854 */ // (or:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VORR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
9479 /* 26854 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9480 /* 26857 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9481 /* 26861 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9482 /* 26866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9483 /* 26869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9484 /* 26871 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9485 /* 26873 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9486 /* 26875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9487 /* 26878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9488 /* 26884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9489 /* 26890 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9490 /* 26893 */ GIR_RootConstrainSelectedInstOperands,
9491 /* 26894 */ // GIR_Coverage, 3734,
9492 /* 26894 */ GIR_EraseRootFromParent_Done,
9493 /* 26895 */ // Label 524: @26895
9494 /* 26895 */ GIM_Reject,
9495 /* 26896 */ // Label 522: @26896
9496 /* 26896 */ GIM_Reject,
9497 /* 26897 */ // Label 460: @26897
9498 /* 26897 */ GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(27014), // Rule ID 1998 //
9499 /* 26902 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9500 /* 26905 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1,
9501 /* 26908 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1,
9502 /* 26911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9503 /* 26915 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9504 /* 26919 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9505 /* 26923 */ // (or:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2ORRrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9506 /* 26923 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9507 /* 26926 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9508 /* 26930 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9509 /* 26935 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9510 /* 26939 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9511 /* 26944 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9512 /* 26947 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9513 /* 26951 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9514 /* 26956 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9515 /* 26960 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9516 /* 26965 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9517 /* 26968 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2ORRrr),
9518 /* 26972 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9519 /* 26977 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9520 /* 26980 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9521 /* 26983 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9522 /* 26986 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9523 /* 26992 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9524 /* 26998 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9525 /* 27000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9526 /* 27003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9527 /* 27005 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9528 /* 27008 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9529 /* 27013 */ // GIR_Coverage, 1998,
9530 /* 27013 */ GIR_EraseRootFromParent_Done,
9531 /* 27014 */ // Label 525: @27014
9532 /* 27014 */ GIM_Reject,
9533 /* 27015 */ // Label 461: @27015
9534 /* 27015 */ GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(27128),
9535 /* 27020 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
9536 /* 27023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
9537 /* 27026 */ GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(27066), // Rule ID 2883 //
9538 /* 27031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9539 /* 27034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9540 /* 27038 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9541 /* 27042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9542 /* 27046 */ // (or:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VORRq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
9543 /* 27046 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VORRq),
9544 /* 27049 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9545 /* 27051 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9546 /* 27053 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9547 /* 27055 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9548 /* 27058 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9549 /* 27064 */ GIR_RootConstrainSelectedInstOperands,
9550 /* 27065 */ // GIR_Coverage, 2883,
9551 /* 27065 */ GIR_EraseRootFromParent_Done,
9552 /* 27066 */ // Label 527: @27066
9553 /* 27066 */ GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(27127), // Rule ID 3730 //
9554 /* 27071 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9555 /* 27074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9556 /* 27078 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9557 /* 27082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9558 /* 27086 */ // (or:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VORR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
9559 /* 27086 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9560 /* 27089 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9561 /* 27093 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9562 /* 27098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VORR),
9563 /* 27101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9564 /* 27103 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9565 /* 27105 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9566 /* 27107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9567 /* 27110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9568 /* 27116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9569 /* 27122 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9570 /* 27125 */ GIR_RootConstrainSelectedInstOperands,
9571 /* 27126 */ // GIR_Coverage, 3730,
9572 /* 27126 */ GIR_EraseRootFromParent_Done,
9573 /* 27127 */ // Label 528: @27127
9574 /* 27127 */ GIM_Reject,
9575 /* 27128 */ // Label 526: @27128
9576 /* 27128 */ GIM_Reject,
9577 /* 27129 */ // Label 462: @27129
9578 /* 27129 */ GIM_Reject,
9579 /* 27130 */ // Label 7: @27130
9580 /* 27130 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 542*/ GIMT_Encode4(28824),
9581 /* 27141 */ /*GILLT_s32*//*Label 529*/ GIMT_Encode4(27201),
9582 /* 27145 */ /*GILLT_s64*//*Label 530*/ GIMT_Encode4(27708),
9583 /* 27149 */ /*GILLT_v2s1*//*Label 531*/ GIMT_Encode4(27755),
9584 /* 27153 */ /*GILLT_v2s32*//*Label 532*/ GIMT_Encode4(27873),
9585 /* 27157 */ /*GILLT_v2s64*//*Label 533*/ GIMT_Encode4(27920),
9586 /* 27161 */ /*GILLT_v4s1*//*Label 534*/ GIMT_Encode4(28034),
9587 /* 27165 */ /*GILLT_v4s16*//*Label 535*/ GIMT_Encode4(28152),
9588 /* 27169 */ /*GILLT_v4s32*//*Label 536*/ GIMT_Encode4(28199), GIMT_Encode4(0),
9589 /* 27177 */ /*GILLT_v8s1*//*Label 537*/ GIMT_Encode4(28313),
9590 /* 27181 */ /*GILLT_v8s8*//*Label 538*/ GIMT_Encode4(28431),
9591 /* 27185 */ /*GILLT_v8s16*//*Label 539*/ GIMT_Encode4(28478), GIMT_Encode4(0),
9592 /* 27193 */ /*GILLT_v16s1*//*Label 540*/ GIMT_Encode4(28592),
9593 /* 27197 */ /*GILLT_v16s8*//*Label 541*/ GIMT_Encode4(28710),
9594 /* 27201 */ // Label 529: @27201
9595 /* 27201 */ GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(27707),
9596 /* 27206 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
9597 /* 27209 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
9598 /* 27212 */ GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(27267), // Rule ID 5958 //
9599 /* 27217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9600 /* 27220 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9601 /* 27224 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 255,
9602 /* 27228 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9603 /* 27232 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9604 /* 27236 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
9605 /* 27240 */ // MIs[1] Operand 1
9606 /* 27240 */ // No operand predicates
9607 /* 27240 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9608 /* 27242 */ // (xor:{ *:[i32] } -1:{ *:[i32] }, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
9609 /* 27242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
9610 /* 27245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9611 /* 27247 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9612 /* 27250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9613 /* 27253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9614 /* 27259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9615 /* 27265 */ GIR_RootConstrainSelectedInstOperands,
9616 /* 27266 */ // GIR_Coverage, 5958,
9617 /* 27266 */ GIR_EraseRootFromParent_Done,
9618 /* 27267 */ // Label 544: @27267
9619 /* 27267 */ GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(27322), // Rule ID 498 //
9620 /* 27272 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9621 /* 27275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9622 /* 27279 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
9623 /* 27283 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9624 /* 27287 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
9625 /* 27291 */ // MIs[1] Operand 1
9626 /* 27291 */ // No operand predicates
9627 /* 27291 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9628 /* 27295 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9629 /* 27297 */ // (xor:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm, -1:{ *:[i32] }) => (t2MVNi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
9630 /* 27297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
9631 /* 27300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9632 /* 27302 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9633 /* 27305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9634 /* 27308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9635 /* 27314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9636 /* 27320 */ GIR_RootConstrainSelectedInstOperands,
9637 /* 27321 */ // GIR_Coverage, 498,
9638 /* 27321 */ GIR_EraseRootFromParent_Done,
9639 /* 27322 */ // Label 545: @27322
9640 /* 27322 */ GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(27366), // Rule ID 499 //
9641 /* 27327 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9642 /* 27330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9643 /* 27334 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9644 /* 27338 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9645 /* 27342 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (t2MVNr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
9646 /* 27342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MVNr),
9647 /* 27345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9648 /* 27347 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
9649 /* 27349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9650 /* 27352 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9651 /* 27358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9652 /* 27364 */ GIR_RootConstrainSelectedInstOperands,
9653 /* 27365 */ // GIR_Coverage, 499,
9654 /* 27365 */ GIR_EraseRootFromParent_Done,
9655 /* 27366 */ // Label 546: @27366
9656 /* 27366 */ GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(27410), // Rule ID 164 //
9657 /* 27371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
9658 /* 27374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9659 /* 27378 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9660 /* 27382 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9661 /* 27386 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rm, -1:{ *:[i32] }) => (MVNr:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
9662 /* 27386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNr),
9663 /* 27389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9664 /* 27391 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
9665 /* 27393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9666 /* 27396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9667 /* 27402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9668 /* 27408 */ GIR_RootConstrainSelectedInstOperands,
9669 /* 27409 */ // GIR_Coverage, 164,
9670 /* 27409 */ GIR_EraseRootFromParent_Done,
9671 /* 27410 */ // Label 547: @27410
9672 /* 27410 */ GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(27454), // Rule ID 323 //
9673 /* 27415 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
9674 /* 27418 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9675 /* 27422 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9676 /* 27426 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 255,
9677 /* 27430 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, -1:{ *:[i32] }) => (tMVN:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)
9678 /* 27430 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMVN),
9679 /* 27433 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9680 /* 27435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
9681 /* 27441 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9682 /* 27443 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9683 /* 27446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9684 /* 27452 */ GIR_RootConstrainSelectedInstOperands,
9685 /* 27453 */ // GIR_Coverage, 323,
9686 /* 27453 */ GIR_EraseRootFromParent_Done,
9687 /* 27454 */ // Label 548: @27454
9688 /* 27454 */ GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(27511), // Rule ID 154 //
9689 /* 27459 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
9690 /* 27462 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9691 /* 27466 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9692 /* 27470 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9693 /* 27474 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9694 /* 27478 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
9695 /* 27482 */ // MIs[1] Operand 1
9696 /* 27482 */ // No operand predicates
9697 /* 27482 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9698 /* 27484 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm) => (EORri:{ *:[i32] } GPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
9699 /* 27484 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORri),
9700 /* 27487 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9701 /* 27489 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9702 /* 27491 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9703 /* 27494 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9704 /* 27497 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9705 /* 27503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9706 /* 27509 */ GIR_RootConstrainSelectedInstOperands,
9707 /* 27510 */ // GIR_Coverage, 154,
9708 /* 27510 */ GIR_EraseRootFromParent_Done,
9709 /* 27511 */ // Label 549: @27511
9710 /* 27511 */ GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(27568), // Rule ID 486 //
9711 /* 27516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9712 /* 27519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9713 /* 27523 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9714 /* 27527 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
9715 /* 27531 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
9716 /* 27535 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
9717 /* 27539 */ // MIs[1] Operand 1
9718 /* 27539 */ // No operand predicates
9719 /* 27539 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
9720 /* 27541 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm) => (t2EORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, (imm:{ *:[i32] }):$imm)
9721 /* 27541 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORri),
9722 /* 27544 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9723 /* 27546 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9724 /* 27548 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
9725 /* 27551 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9726 /* 27554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9727 /* 27560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9728 /* 27566 */ GIR_RootConstrainSelectedInstOperands,
9729 /* 27567 */ // GIR_Coverage, 486,
9730 /* 27567 */ GIR_EraseRootFromParent_Done,
9731 /* 27568 */ // Label 550: @27568
9732 /* 27568 */ GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(27614), // Rule ID 155 //
9733 /* 27573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
9734 /* 27576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9735 /* 27580 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9736 /* 27584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
9737 /* 27588 */ // (xor:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (EORrr:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
9738 /* 27588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::EORrr),
9739 /* 27591 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9740 /* 27593 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9741 /* 27595 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9742 /* 27597 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9743 /* 27600 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9744 /* 27606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9745 /* 27612 */ GIR_RootConstrainSelectedInstOperands,
9746 /* 27613 */ // GIR_Coverage, 155,
9747 /* 27613 */ GIR_EraseRootFromParent_Done,
9748 /* 27614 */ // Label 551: @27614
9749 /* 27614 */ GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(27660), // Rule ID 316 //
9750 /* 27619 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
9751 /* 27622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9752 /* 27626 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9753 /* 27630 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
9754 /* 27634 */ // (xor:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tEOR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
9755 /* 27634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tEOR),
9756 /* 27637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
9757 /* 27639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
9758 /* 27645 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9759 /* 27647 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9760 /* 27649 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9761 /* 27652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9762 /* 27658 */ GIR_RootConstrainSelectedInstOperands,
9763 /* 27659 */ // GIR_Coverage, 316,
9764 /* 27659 */ GIR_EraseRootFromParent_Done,
9765 /* 27660 */ // Label 552: @27660
9766 /* 27660 */ GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(27706), // Rule ID 487 //
9767 /* 27665 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
9768 /* 27668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9769 /* 27672 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9770 /* 27676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
9771 /* 27680 */ // (xor:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2EORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
9772 /* 27680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9773 /* 27683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
9774 /* 27685 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
9775 /* 27687 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
9776 /* 27689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9777 /* 27692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9778 /* 27698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9779 /* 27704 */ GIR_RootConstrainSelectedInstOperands,
9780 /* 27705 */ // GIR_Coverage, 487,
9781 /* 27705 */ GIR_EraseRootFromParent_Done,
9782 /* 27706 */ // Label 553: @27706
9783 /* 27706 */ GIM_Reject,
9784 /* 27707 */ // Label 543: @27707
9785 /* 27707 */ GIM_Reject,
9786 /* 27708 */ // Label 530: @27708
9787 /* 27708 */ GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(27754), // Rule ID 2888 //
9788 /* 27713 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9789 /* 27716 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
9790 /* 27719 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
9791 /* 27722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9792 /* 27726 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9793 /* 27730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9794 /* 27734 */ // (xor:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS) => (VEORd:{ *:[v1i64] } DPR:{ *:[v1i64] }:$LHS, DPR:{ *:[v1i64] }:$RHS)
9795 /* 27734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
9796 /* 27737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9797 /* 27739 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9798 /* 27741 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9799 /* 27743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9800 /* 27746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9801 /* 27752 */ GIR_RootConstrainSelectedInstOperands,
9802 /* 27753 */ // GIR_Coverage, 2888,
9803 /* 27753 */ GIR_EraseRootFromParent_Done,
9804 /* 27754 */ // Label 554: @27754
9805 /* 27754 */ GIM_Reject,
9806 /* 27755 */ // Label 531: @27755
9807 /* 27755 */ GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(27872), // Rule ID 1991 //
9808 /* 27760 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9809 /* 27763 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s1,
9810 /* 27766 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s1,
9811 /* 27769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9812 /* 27773 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9813 /* 27777 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9814 /* 27781 */ // (xor:{ *:[v2i1] } VCCR:{ *:[v2i1] }:$p1, VCCR:{ *:[v2i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v2i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v2i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9815 /* 27781 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9816 /* 27784 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9817 /* 27788 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9818 /* 27793 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9819 /* 27797 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9820 /* 27802 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9821 /* 27805 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9822 /* 27809 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9823 /* 27814 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9824 /* 27818 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9825 /* 27823 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9826 /* 27826 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9827 /* 27830 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9828 /* 27835 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9829 /* 27838 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9830 /* 27841 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9831 /* 27844 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9832 /* 27850 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9833 /* 27856 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9834 /* 27858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9835 /* 27861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9836 /* 27863 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9837 /* 27866 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9838 /* 27871 */ // GIR_Coverage, 1991,
9839 /* 27871 */ GIR_EraseRootFromParent_Done,
9840 /* 27872 */ // Label 555: @27872
9841 /* 27872 */ GIM_Reject,
9842 /* 27873 */ // Label 532: @27873
9843 /* 27873 */ GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(27919), // Rule ID 1296 //
9844 /* 27878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9845 /* 27881 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
9846 /* 27884 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
9847 /* 27887 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9848 /* 27891 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9849 /* 27895 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9850 /* 27899 */ // (xor:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VEORd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
9851 /* 27899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
9852 /* 27902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9853 /* 27904 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9854 /* 27906 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9855 /* 27908 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9856 /* 27911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9857 /* 27917 */ GIR_RootConstrainSelectedInstOperands,
9858 /* 27918 */ // GIR_Coverage, 1296,
9859 /* 27918 */ GIR_EraseRootFromParent_Done,
9860 /* 27919 */ // Label 556: @27919
9861 /* 27919 */ GIM_Reject,
9862 /* 27920 */ // Label 533: @27920
9863 /* 27920 */ GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(28033),
9864 /* 27925 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
9865 /* 27928 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
9866 /* 27931 */ GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(27971), // Rule ID 2891 //
9867 /* 27936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9868 /* 27939 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9869 /* 27943 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9870 /* 27947 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9871 /* 27951 */ // (xor:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS) => (VEORq:{ *:[v2i64] } QPR:{ *:[v2i64] }:$LHS, QPR:{ *:[v2i64] }:$RHS)
9872 /* 27951 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
9873 /* 27954 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9874 /* 27956 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9875 /* 27958 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9876 /* 27960 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9877 /* 27963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9878 /* 27969 */ GIR_RootConstrainSelectedInstOperands,
9879 /* 27970 */ // GIR_Coverage, 2891,
9880 /* 27970 */ GIR_EraseRootFromParent_Done,
9881 /* 27971 */ // Label 558: @27971
9882 /* 27971 */ GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(28032), // Rule ID 3756 //
9883 /* 27976 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9884 /* 27979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9885 /* 27983 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9886 /* 27987 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9887 /* 27991 */ // (xor:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn) => (MVE_VEOR:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$Qm, MQPR:{ *:[v2i64] }:$Qn)
9888 /* 27991 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9889 /* 27994 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9890 /* 27998 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9891 /* 28003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
9892 /* 28006 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9893 /* 28008 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9894 /* 28010 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9895 /* 28012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9896 /* 28015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9897 /* 28021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9898 /* 28027 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9899 /* 28030 */ GIR_RootConstrainSelectedInstOperands,
9900 /* 28031 */ // GIR_Coverage, 3756,
9901 /* 28031 */ GIR_EraseRootFromParent_Done,
9902 /* 28032 */ // Label 559: @28032
9903 /* 28032 */ GIM_Reject,
9904 /* 28033 */ // Label 557: @28033
9905 /* 28033 */ GIM_Reject,
9906 /* 28034 */ // Label 534: @28034
9907 /* 28034 */ GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(28151), // Rule ID 1992 //
9908 /* 28039 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9909 /* 28042 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s1,
9910 /* 28045 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s1,
9911 /* 28048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9912 /* 28052 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9913 /* 28056 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
9914 /* 28060 */ // (xor:{ *:[v4i1] } VCCR:{ *:[v4i1] }:$p1, VCCR:{ *:[v4i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v4i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v4i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
9915 /* 28060 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
9916 /* 28063 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9917 /* 28067 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9918 /* 28072 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
9919 /* 28076 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9920 /* 28081 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
9921 /* 28084 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9922 /* 28088 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9923 /* 28093 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
9924 /* 28097 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
9925 /* 28102 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
9926 /* 28105 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
9927 /* 28109 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9928 /* 28114 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
9929 /* 28117 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
9930 /* 28120 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
9931 /* 28123 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9932 /* 28129 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9933 /* 28135 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
9934 /* 28137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
9935 /* 28140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
9936 /* 28142 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9937 /* 28145 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
9938 /* 28150 */ // GIR_Coverage, 1992,
9939 /* 28150 */ GIR_EraseRootFromParent_Done,
9940 /* 28151 */ // Label 560: @28151
9941 /* 28151 */ GIM_Reject,
9942 /* 28152 */ // Label 535: @28152
9943 /* 28152 */ GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(28198), // Rule ID 2887 //
9944 /* 28157 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9945 /* 28160 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
9946 /* 28163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
9947 /* 28166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9948 /* 28170 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9949 /* 28174 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
9950 /* 28178 */ // (xor:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS) => (VEORd:{ *:[v4i16] } DPR:{ *:[v4i16] }:$LHS, DPR:{ *:[v4i16] }:$RHS)
9951 /* 28178 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
9952 /* 28181 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9953 /* 28183 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
9954 /* 28185 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
9955 /* 28187 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9956 /* 28190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9957 /* 28196 */ GIR_RootConstrainSelectedInstOperands,
9958 /* 28197 */ // GIR_Coverage, 2887,
9959 /* 28197 */ GIR_EraseRootFromParent_Done,
9960 /* 28198 */ // Label 561: @28198
9961 /* 28198 */ GIM_Reject,
9962 /* 28199 */ // Label 536: @28199
9963 /* 28199 */ GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(28312),
9964 /* 28204 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
9965 /* 28207 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
9966 /* 28210 */ GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(28250), // Rule ID 1297 //
9967 /* 28215 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
9968 /* 28218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9969 /* 28222 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9970 /* 28226 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
9971 /* 28230 */ // (xor:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VEORq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
9972 /* 28230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
9973 /* 28233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
9974 /* 28235 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
9975 /* 28237 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
9976 /* 28239 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
9977 /* 28242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9978 /* 28248 */ GIR_RootConstrainSelectedInstOperands,
9979 /* 28249 */ // GIR_Coverage, 1297,
9980 /* 28249 */ GIR_EraseRootFromParent_Done,
9981 /* 28250 */ // Label 563: @28250
9982 /* 28250 */ GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(28311), // Rule ID 3752 //
9983 /* 28255 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
9984 /* 28258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9985 /* 28262 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9986 /* 28266 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
9987 /* 28270 */ // (xor:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VEOR:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
9988 /* 28270 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
9989 /* 28273 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
9990 /* 28277 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
9991 /* 28282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
9992 /* 28285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
9993 /* 28287 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
9994 /* 28289 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
9995 /* 28291 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
9996 /* 28294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9997 /* 28300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
9998 /* 28306 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
9999 /* 28309 */ GIR_RootConstrainSelectedInstOperands,
10000 /* 28310 */ // GIR_Coverage, 3752,
10001 /* 28310 */ GIR_EraseRootFromParent_Done,
10002 /* 28311 */ // Label 564: @28311
10003 /* 28311 */ GIM_Reject,
10004 /* 28312 */ // Label 562: @28312
10005 /* 28312 */ GIM_Reject,
10006 /* 28313 */ // Label 537: @28313
10007 /* 28313 */ GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(28430), // Rule ID 1993 //
10008 /* 28318 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10009 /* 28321 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s1,
10010 /* 28324 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s1,
10011 /* 28327 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
10012 /* 28331 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
10013 /* 28335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
10014 /* 28339 */ // (xor:{ *:[v8i1] } VCCR:{ *:[v8i1] }:$p1, VCCR:{ *:[v8i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v8i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v8i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
10015 /* 28339 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
10016 /* 28342 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10017 /* 28346 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10018 /* 28351 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
10019 /* 28355 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
10020 /* 28360 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
10021 /* 28363 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10022 /* 28367 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10023 /* 28372 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
10024 /* 28376 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
10025 /* 28381 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
10026 /* 28384 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
10027 /* 28388 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10028 /* 28393 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
10029 /* 28396 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
10030 /* 28399 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
10031 /* 28402 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10032 /* 28408 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10033 /* 28414 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
10034 /* 28416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10035 /* 28419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10036 /* 28421 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10037 /* 28424 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
10038 /* 28429 */ // GIR_Coverage, 1993,
10039 /* 28429 */ GIR_EraseRootFromParent_Done,
10040 /* 28430 */ // Label 565: @28430
10041 /* 28430 */ GIM_Reject,
10042 /* 28431 */ // Label 538: @28431
10043 /* 28431 */ GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(28477), // Rule ID 2886 //
10044 /* 28436 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10045 /* 28439 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
10046 /* 28442 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
10047 /* 28445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10048 /* 28449 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10049 /* 28453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10050 /* 28457 */ // (xor:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS) => (VEORd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$LHS, DPR:{ *:[v8i8] }:$RHS)
10051 /* 28457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORd),
10052 /* 28460 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10053 /* 28462 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
10054 /* 28464 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
10055 /* 28466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10056 /* 28469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10057 /* 28475 */ GIR_RootConstrainSelectedInstOperands,
10058 /* 28476 */ // GIR_Coverage, 2886,
10059 /* 28476 */ GIR_EraseRootFromParent_Done,
10060 /* 28477 */ // Label 566: @28477
10061 /* 28477 */ GIM_Reject,
10062 /* 28478 */ // Label 539: @28478
10063 /* 28478 */ GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(28591),
10064 /* 28483 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10065 /* 28486 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10066 /* 28489 */ GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(28529), // Rule ID 2890 //
10067 /* 28494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10068 /* 28497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10069 /* 28501 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10070 /* 28505 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10071 /* 28509 */ // (xor:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS) => (VEORq:{ *:[v8i16] } QPR:{ *:[v8i16] }:$LHS, QPR:{ *:[v8i16] }:$RHS)
10072 /* 28509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
10073 /* 28512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10074 /* 28514 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
10075 /* 28516 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
10076 /* 28518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10077 /* 28521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10078 /* 28527 */ GIR_RootConstrainSelectedInstOperands,
10079 /* 28528 */ // GIR_Coverage, 2890,
10080 /* 28528 */ GIR_EraseRootFromParent_Done,
10081 /* 28529 */ // Label 568: @28529
10082 /* 28529 */ GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(28590), // Rule ID 3748 //
10083 /* 28534 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10084 /* 28537 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10085 /* 28541 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10086 /* 28545 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10087 /* 28549 */ // (xor:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VEOR:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10088 /* 28549 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10089 /* 28552 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10090 /* 28556 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10091 /* 28561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
10092 /* 28564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10093 /* 28566 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10094 /* 28568 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10095 /* 28570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10096 /* 28573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10097 /* 28579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10098 /* 28585 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10099 /* 28588 */ GIR_RootConstrainSelectedInstOperands,
10100 /* 28589 */ // GIR_Coverage, 3748,
10101 /* 28589 */ GIR_EraseRootFromParent_Done,
10102 /* 28590 */ // Label 569: @28590
10103 /* 28590 */ GIM_Reject,
10104 /* 28591 */ // Label 567: @28591
10105 /* 28591 */ GIM_Reject,
10106 /* 28592 */ // Label 540: @28592
10107 /* 28592 */ GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(28709), // Rule ID 1994 //
10108 /* 28597 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10109 /* 28600 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s1,
10110 /* 28603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s1,
10111 /* 28606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
10112 /* 28610 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
10113 /* 28614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
10114 /* 28618 */ // (xor:{ *:[v16i1] } VCCR:{ *:[v16i1] }:$p1, VCCR:{ *:[v16i1] }:$p2) => (COPY_TO_REGCLASS:{ *:[v16i1] } (t2EORrr:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p1, rGPR:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i32] } VCCR:{ *:[v16i1] }:$p2, rGPR:{ *:[i32] })), VCCR:{ *:[i32] })
10115 /* 28618 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32,
10116 /* 28621 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10117 /* 28625 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10118 /* 28630 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // p2
10119 /* 28634 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
10120 /* 28639 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
10121 /* 28642 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10122 /* 28646 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10123 /* 28651 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // p1
10124 /* 28655 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
10125 /* 28660 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
10126 /* 28663 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2EORrr),
10127 /* 28667 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10128 /* 28672 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
10129 /* 28675 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2,
10130 /* 28678 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
10131 /* 28681 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10132 /* 28687 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10133 /* 28693 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
10134 /* 28695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
10135 /* 28698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10136 /* 28700 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10137 /* 28703 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::VCCRRegClassID),
10138 /* 28708 */ // GIR_Coverage, 1994,
10139 /* 28708 */ GIR_EraseRootFromParent_Done,
10140 /* 28709 */ // Label 570: @28709
10141 /* 28709 */ GIM_Reject,
10142 /* 28710 */ // Label 541: @28710
10143 /* 28710 */ GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(28823),
10144 /* 28715 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10145 /* 28718 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10146 /* 28721 */ GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(28761), // Rule ID 2889 //
10147 /* 28726 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10148 /* 28729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10149 /* 28733 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10150 /* 28737 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10151 /* 28741 */ // (xor:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS) => (VEORq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$LHS, QPR:{ *:[v16i8] }:$RHS)
10152 /* 28741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VEORq),
10153 /* 28744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10154 /* 28746 */ GIR_RootToRootCopy, /*OpIdx*/1, // LHS
10155 /* 28748 */ GIR_RootToRootCopy, /*OpIdx*/2, // RHS
10156 /* 28750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10157 /* 28753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10158 /* 28759 */ GIR_RootConstrainSelectedInstOperands,
10159 /* 28760 */ // GIR_Coverage, 2889,
10160 /* 28760 */ GIR_EraseRootFromParent_Done,
10161 /* 28761 */ // Label 572: @28761
10162 /* 28761 */ GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(28822), // Rule ID 3744 //
10163 /* 28766 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10164 /* 28769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10165 /* 28773 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10166 /* 28777 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10167 /* 28781 */ // (xor:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VEOR:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10168 /* 28781 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10169 /* 28784 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10170 /* 28788 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10171 /* 28793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VEOR),
10172 /* 28796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10173 /* 28798 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10174 /* 28800 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10175 /* 28802 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10176 /* 28805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10177 /* 28811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10178 /* 28817 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10179 /* 28820 */ GIR_RootConstrainSelectedInstOperands,
10180 /* 28821 */ // GIR_Coverage, 3744,
10181 /* 28821 */ GIR_EraseRootFromParent_Done,
10182 /* 28822 */ // Label 573: @28822
10183 /* 28822 */ GIM_Reject,
10184 /* 28823 */ // Label 571: @28823
10185 /* 28823 */ GIM_Reject,
10186 /* 28824 */ // Label 542: @28824
10187 /* 28824 */ GIM_Reject,
10188 /* 28825 */ // Label 8: @28825
10189 /* 28825 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 580*/ GIMT_Encode4(29367),
10190 /* 28836 */ /*GILLT_v2s32*//*Label 574*/ GIMT_Encode4(28884), GIMT_Encode4(0), GIMT_Encode4(0),
10191 /* 28848 */ /*GILLT_v4s16*//*Label 575*/ GIMT_Encode4(28931),
10192 /* 28852 */ /*GILLT_v4s32*//*Label 576*/ GIMT_Encode4(28978), GIMT_Encode4(0), GIMT_Encode4(0),
10193 /* 28864 */ /*GILLT_v8s8*//*Label 577*/ GIMT_Encode4(29092),
10194 /* 28868 */ /*GILLT_v8s16*//*Label 578*/ GIMT_Encode4(29139), GIMT_Encode4(0), GIMT_Encode4(0),
10195 /* 28880 */ /*GILLT_v16s8*//*Label 579*/ GIMT_Encode4(29253),
10196 /* 28884 */ // Label 574: @28884
10197 /* 28884 */ GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(28930), // Rule ID 1319 //
10198 /* 28889 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10199 /* 28892 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
10200 /* 28895 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
10201 /* 28898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10202 /* 28902 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10203 /* 28906 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10204 /* 28910 */ // (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
10205 /* 28910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv2i32),
10206 /* 28913 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10207 /* 28915 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10208 /* 28917 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10209 /* 28919 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10210 /* 28922 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10211 /* 28928 */ GIR_RootConstrainSelectedInstOperands,
10212 /* 28929 */ // GIR_Coverage, 1319,
10213 /* 28929 */ GIR_EraseRootFromParent_Done,
10214 /* 28930 */ // Label 581: @28930
10215 /* 28930 */ GIM_Reject,
10216 /* 28931 */ // Label 575: @28931
10217 /* 28931 */ GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(28977), // Rule ID 1318 //
10218 /* 28936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10219 /* 28939 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
10220 /* 28942 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
10221 /* 28945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10222 /* 28949 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10223 /* 28953 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10224 /* 28957 */ // (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
10225 /* 28957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i16),
10226 /* 28960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10227 /* 28962 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10228 /* 28964 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10229 /* 28966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10230 /* 28969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10231 /* 28975 */ GIR_RootConstrainSelectedInstOperands,
10232 /* 28976 */ // GIR_Coverage, 1318,
10233 /* 28976 */ GIR_EraseRootFromParent_Done,
10234 /* 28977 */ // Label 582: @28977
10235 /* 28977 */ GIM_Reject,
10236 /* 28978 */ // Label 576: @28978
10237 /* 28978 */ GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(29091),
10238 /* 28983 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10239 /* 28986 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10240 /* 28989 */ GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(29029), // Rule ID 1321 //
10241 /* 28994 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10242 /* 28997 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10243 /* 29001 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10244 /* 29005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10245 /* 29009 */ // (abds:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
10246 /* 29009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv4i32),
10247 /* 29012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10248 /* 29014 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10249 /* 29016 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10250 /* 29018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10251 /* 29021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10252 /* 29027 */ GIR_RootConstrainSelectedInstOperands,
10253 /* 29028 */ // GIR_Coverage, 1321,
10254 /* 29028 */ GIR_EraseRootFromParent_Done,
10255 /* 29029 */ // Label 584: @29029
10256 /* 29029 */ GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(29090), // Rule ID 3914 //
10257 /* 29034 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10258 /* 29037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10259 /* 29041 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10260 /* 29045 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10261 /* 29049 */ // (abds:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10262 /* 29049 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10263 /* 29052 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10264 /* 29056 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10265 /* 29061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32),
10266 /* 29064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10267 /* 29066 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10268 /* 29068 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10269 /* 29070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10270 /* 29073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10271 /* 29079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10272 /* 29085 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10273 /* 29088 */ GIR_RootConstrainSelectedInstOperands,
10274 /* 29089 */ // GIR_Coverage, 3914,
10275 /* 29089 */ GIR_EraseRootFromParent_Done,
10276 /* 29090 */ // Label 585: @29090
10277 /* 29090 */ GIM_Reject,
10278 /* 29091 */ // Label 583: @29091
10279 /* 29091 */ GIM_Reject,
10280 /* 29092 */ // Label 577: @29092
10281 /* 29092 */ GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(29138), // Rule ID 1322 //
10282 /* 29097 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10283 /* 29100 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
10284 /* 29103 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
10285 /* 29106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10286 /* 29110 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10287 /* 29114 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10288 /* 29118 */ // (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
10289 /* 29118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i8),
10290 /* 29121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10291 /* 29123 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10292 /* 29125 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10293 /* 29127 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10294 /* 29130 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10295 /* 29136 */ GIR_RootConstrainSelectedInstOperands,
10296 /* 29137 */ // GIR_Coverage, 1322,
10297 /* 29137 */ GIR_EraseRootFromParent_Done,
10298 /* 29138 */ // Label 586: @29138
10299 /* 29138 */ GIM_Reject,
10300 /* 29139 */ // Label 578: @29139
10301 /* 29139 */ GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(29252),
10302 /* 29144 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10303 /* 29147 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10304 /* 29150 */ GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(29190), // Rule ID 1320 //
10305 /* 29155 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10306 /* 29158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10307 /* 29162 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10308 /* 29166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10309 /* 29170 */ // (abds:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
10310 /* 29170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv8i16),
10311 /* 29173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10312 /* 29175 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10313 /* 29177 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10314 /* 29179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10315 /* 29182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10316 /* 29188 */ GIR_RootConstrainSelectedInstOperands,
10317 /* 29189 */ // GIR_Coverage, 1320,
10318 /* 29189 */ GIR_EraseRootFromParent_Done,
10319 /* 29190 */ // Label 588: @29190
10320 /* 29190 */ GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(29251), // Rule ID 3910 //
10321 /* 29195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10322 /* 29198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10323 /* 29202 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10324 /* 29206 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10325 /* 29210 */ // (abds:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10326 /* 29210 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10327 /* 29213 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10328 /* 29217 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10329 /* 29222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16),
10330 /* 29225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10331 /* 29227 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10332 /* 29229 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10333 /* 29231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10334 /* 29234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10335 /* 29240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10336 /* 29246 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10337 /* 29249 */ GIR_RootConstrainSelectedInstOperands,
10338 /* 29250 */ // GIR_Coverage, 3910,
10339 /* 29250 */ GIR_EraseRootFromParent_Done,
10340 /* 29251 */ // Label 589: @29251
10341 /* 29251 */ GIM_Reject,
10342 /* 29252 */ // Label 587: @29252
10343 /* 29252 */ GIM_Reject,
10344 /* 29253 */ // Label 579: @29253
10345 /* 29253 */ GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(29366),
10346 /* 29258 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10347 /* 29261 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10348 /* 29264 */ GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(29304), // Rule ID 1323 //
10349 /* 29269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10350 /* 29272 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10351 /* 29276 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10352 /* 29280 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10353 /* 29284 */ // (abds:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
10354 /* 29284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDsv16i8),
10355 /* 29287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10356 /* 29289 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10357 /* 29291 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10358 /* 29293 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10359 /* 29296 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10360 /* 29302 */ GIR_RootConstrainSelectedInstOperands,
10361 /* 29303 */ // GIR_Coverage, 1323,
10362 /* 29303 */ GIR_EraseRootFromParent_Done,
10363 /* 29304 */ // Label 591: @29304
10364 /* 29304 */ GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(29365), // Rule ID 3907 //
10365 /* 29309 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10366 /* 29312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10367 /* 29316 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10368 /* 29320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10369 /* 29324 */ // (abds:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10370 /* 29324 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10371 /* 29327 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10372 /* 29331 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10373 /* 29336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8),
10374 /* 29339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10375 /* 29341 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10376 /* 29343 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10377 /* 29345 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10378 /* 29348 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10379 /* 29354 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10380 /* 29360 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10381 /* 29363 */ GIR_RootConstrainSelectedInstOperands,
10382 /* 29364 */ // GIR_Coverage, 3907,
10383 /* 29364 */ GIR_EraseRootFromParent_Done,
10384 /* 29365 */ // Label 592: @29365
10385 /* 29365 */ GIM_Reject,
10386 /* 29366 */ // Label 590: @29366
10387 /* 29366 */ GIM_Reject,
10388 /* 29367 */ // Label 580: @29367
10389 /* 29367 */ GIM_Reject,
10390 /* 29368 */ // Label 9: @29368
10391 /* 29368 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 599*/ GIMT_Encode4(29910),
10392 /* 29379 */ /*GILLT_v2s32*//*Label 593*/ GIMT_Encode4(29427), GIMT_Encode4(0), GIMT_Encode4(0),
10393 /* 29391 */ /*GILLT_v4s16*//*Label 594*/ GIMT_Encode4(29474),
10394 /* 29395 */ /*GILLT_v4s32*//*Label 595*/ GIMT_Encode4(29521), GIMT_Encode4(0), GIMT_Encode4(0),
10395 /* 29407 */ /*GILLT_v8s8*//*Label 596*/ GIMT_Encode4(29635),
10396 /* 29411 */ /*GILLT_v8s16*//*Label 597*/ GIMT_Encode4(29682), GIMT_Encode4(0), GIMT_Encode4(0),
10397 /* 29423 */ /*GILLT_v16s8*//*Label 598*/ GIMT_Encode4(29796),
10398 /* 29427 */ // Label 593: @29427
10399 /* 29427 */ GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(29473), // Rule ID 1325 //
10400 /* 29432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10401 /* 29435 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
10402 /* 29438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
10403 /* 29441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10404 /* 29445 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10405 /* 29449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10406 /* 29453 */ // (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VABDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
10407 /* 29453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv2i32),
10408 /* 29456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10409 /* 29458 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10410 /* 29460 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10411 /* 29462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10412 /* 29465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10413 /* 29471 */ GIR_RootConstrainSelectedInstOperands,
10414 /* 29472 */ // GIR_Coverage, 1325,
10415 /* 29472 */ GIR_EraseRootFromParent_Done,
10416 /* 29473 */ // Label 600: @29473
10417 /* 29473 */ GIM_Reject,
10418 /* 29474 */ // Label 594: @29474
10419 /* 29474 */ GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(29520), // Rule ID 1324 //
10420 /* 29479 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10421 /* 29482 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
10422 /* 29485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
10423 /* 29488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10424 /* 29492 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10425 /* 29496 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10426 /* 29500 */ // (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VABDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
10427 /* 29500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i16),
10428 /* 29503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10429 /* 29505 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10430 /* 29507 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10431 /* 29509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10432 /* 29512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10433 /* 29518 */ GIR_RootConstrainSelectedInstOperands,
10434 /* 29519 */ // GIR_Coverage, 1324,
10435 /* 29519 */ GIR_EraseRootFromParent_Done,
10436 /* 29520 */ // Label 601: @29520
10437 /* 29520 */ GIM_Reject,
10438 /* 29521 */ // Label 595: @29521
10439 /* 29521 */ GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(29634),
10440 /* 29526 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10441 /* 29529 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10442 /* 29532 */ GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(29572), // Rule ID 1327 //
10443 /* 29537 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10444 /* 29540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10445 /* 29544 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10446 /* 29548 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10447 /* 29552 */ // (abdu:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VABDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
10448 /* 29552 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv4i32),
10449 /* 29555 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10450 /* 29557 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10451 /* 29559 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10452 /* 29561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10453 /* 29564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10454 /* 29570 */ GIR_RootConstrainSelectedInstOperands,
10455 /* 29571 */ // GIR_Coverage, 1327,
10456 /* 29571 */ GIR_EraseRootFromParent_Done,
10457 /* 29572 */ // Label 603: @29572
10458 /* 29572 */ GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(29633), // Rule ID 3926 //
10459 /* 29577 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10460 /* 29580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10461 /* 29584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10462 /* 29588 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10463 /* 29592 */ // (abdu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10464 /* 29592 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10465 /* 29595 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10466 /* 29599 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10467 /* 29604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32),
10468 /* 29607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10469 /* 29609 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10470 /* 29611 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10471 /* 29613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10472 /* 29616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10473 /* 29622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10474 /* 29628 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10475 /* 29631 */ GIR_RootConstrainSelectedInstOperands,
10476 /* 29632 */ // GIR_Coverage, 3926,
10477 /* 29632 */ GIR_EraseRootFromParent_Done,
10478 /* 29633 */ // Label 604: @29633
10479 /* 29633 */ GIM_Reject,
10480 /* 29634 */ // Label 602: @29634
10481 /* 29634 */ GIM_Reject,
10482 /* 29635 */ // Label 596: @29635
10483 /* 29635 */ GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(29681), // Rule ID 1328 //
10484 /* 29640 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10485 /* 29643 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
10486 /* 29646 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
10487 /* 29649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10488 /* 29653 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10489 /* 29657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10490 /* 29661 */ // (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VABDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
10491 /* 29661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i8),
10492 /* 29664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10493 /* 29666 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10494 /* 29668 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10495 /* 29670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10496 /* 29673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10497 /* 29679 */ GIR_RootConstrainSelectedInstOperands,
10498 /* 29680 */ // GIR_Coverage, 1328,
10499 /* 29680 */ GIR_EraseRootFromParent_Done,
10500 /* 29681 */ // Label 605: @29681
10501 /* 29681 */ GIM_Reject,
10502 /* 29682 */ // Label 597: @29682
10503 /* 29682 */ GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(29795),
10504 /* 29687 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10505 /* 29690 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10506 /* 29693 */ GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(29733), // Rule ID 1326 //
10507 /* 29698 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10508 /* 29701 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10509 /* 29705 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10510 /* 29709 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10511 /* 29713 */ // (abdu:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VABDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
10512 /* 29713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv8i16),
10513 /* 29716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10514 /* 29718 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10515 /* 29720 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10516 /* 29722 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10517 /* 29725 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10518 /* 29731 */ GIR_RootConstrainSelectedInstOperands,
10519 /* 29732 */ // GIR_Coverage, 1326,
10520 /* 29732 */ GIR_EraseRootFromParent_Done,
10521 /* 29733 */ // Label 607: @29733
10522 /* 29733 */ GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(29794), // Rule ID 3922 //
10523 /* 29738 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10524 /* 29741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10525 /* 29745 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10526 /* 29749 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10527 /* 29753 */ // (abdu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10528 /* 29753 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10529 /* 29756 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10530 /* 29760 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10531 /* 29765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16),
10532 /* 29768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10533 /* 29770 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10534 /* 29772 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10535 /* 29774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10536 /* 29777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10537 /* 29783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10538 /* 29789 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10539 /* 29792 */ GIR_RootConstrainSelectedInstOperands,
10540 /* 29793 */ // GIR_Coverage, 3922,
10541 /* 29793 */ GIR_EraseRootFromParent_Done,
10542 /* 29794 */ // Label 608: @29794
10543 /* 29794 */ GIM_Reject,
10544 /* 29795 */ // Label 606: @29795
10545 /* 29795 */ GIM_Reject,
10546 /* 29796 */ // Label 598: @29796
10547 /* 29796 */ GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(29909),
10548 /* 29801 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10549 /* 29804 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10550 /* 29807 */ GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(29847), // Rule ID 1329 //
10551 /* 29812 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10552 /* 29815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10553 /* 29819 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10554 /* 29823 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10555 /* 29827 */ // (abdu:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VABDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
10556 /* 29827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDuv16i8),
10557 /* 29830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
10558 /* 29832 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
10559 /* 29834 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
10560 /* 29836 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
10561 /* 29839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10562 /* 29845 */ GIR_RootConstrainSelectedInstOperands,
10563 /* 29846 */ // GIR_Coverage, 1329,
10564 /* 29846 */ GIR_EraseRootFromParent_Done,
10565 /* 29847 */ // Label 610: @29847
10566 /* 29847 */ GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(29908), // Rule ID 3918 //
10567 /* 29852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
10568 /* 29855 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10569 /* 29859 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10570 /* 29863 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10571 /* 29867 */ // (abdu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10572 /* 29867 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10573 /* 29870 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10574 /* 29874 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10575 /* 29879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8),
10576 /* 29882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10577 /* 29884 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10578 /* 29886 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10579 /* 29888 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10580 /* 29891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10581 /* 29897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10582 /* 29903 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10583 /* 29906 */ GIR_RootConstrainSelectedInstOperands,
10584 /* 29907 */ // GIR_Coverage, 3918,
10585 /* 29907 */ GIR_EraseRootFromParent_Done,
10586 /* 29908 */ // Label 611: @29908
10587 /* 29908 */ GIM_Reject,
10588 /* 29909 */ // Label 609: @29909
10589 /* 29909 */ GIM_Reject,
10590 /* 29910 */ // Label 599: @29910
10591 /* 29910 */ GIM_Reject,
10592 /* 29911 */ // Label 10: @29911
10593 /* 29911 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 615*/ GIMT_Encode4(30149),
10594 /* 29922 */ /*GILLT_v4s32*//*Label 612*/ GIMT_Encode4(29954), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
10595 /* 29938 */ /*GILLT_v8s16*//*Label 613*/ GIMT_Encode4(30019), GIMT_Encode4(0), GIMT_Encode4(0),
10596 /* 29950 */ /*GILLT_v16s8*//*Label 614*/ GIMT_Encode4(30084),
10597 /* 29954 */ // Label 612: @29954
10598 /* 29954 */ GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(30018), // Rule ID 3974 //
10599 /* 29959 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10600 /* 29962 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10601 /* 29965 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10602 /* 29969 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10603 /* 29973 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10604 /* 29977 */ // (avgflooru:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10605 /* 29977 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10606 /* 29980 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10607 /* 29984 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10608 /* 29989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32),
10609 /* 29992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10610 /* 29994 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10611 /* 29996 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10612 /* 29998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10613 /* 30001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10614 /* 30007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10615 /* 30013 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10616 /* 30016 */ GIR_RootConstrainSelectedInstOperands,
10617 /* 30017 */ // GIR_Coverage, 3974,
10618 /* 30017 */ GIR_EraseRootFromParent_Done,
10619 /* 30018 */ // Label 616: @30018
10620 /* 30018 */ GIM_Reject,
10621 /* 30019 */ // Label 613: @30019
10622 /* 30019 */ GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(30083), // Rule ID 3970 //
10623 /* 30024 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10624 /* 30027 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10625 /* 30030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10626 /* 30034 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10627 /* 30038 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10628 /* 30042 */ // (avgflooru:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10629 /* 30042 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10630 /* 30045 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10631 /* 30049 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10632 /* 30054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16),
10633 /* 30057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10634 /* 30059 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10635 /* 30061 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10636 /* 30063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10637 /* 30066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10638 /* 30072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10639 /* 30078 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10640 /* 30081 */ GIR_RootConstrainSelectedInstOperands,
10641 /* 30082 */ // GIR_Coverage, 3970,
10642 /* 30082 */ GIR_EraseRootFromParent_Done,
10643 /* 30083 */ // Label 617: @30083
10644 /* 30083 */ GIM_Reject,
10645 /* 30084 */ // Label 614: @30084
10646 /* 30084 */ GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(30148), // Rule ID 3966 //
10647 /* 30089 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10648 /* 30092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10649 /* 30095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10650 /* 30099 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10651 /* 30103 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10652 /* 30107 */ // (avgflooru:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10653 /* 30107 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10654 /* 30110 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10655 /* 30114 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10656 /* 30119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8),
10657 /* 30122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10658 /* 30124 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10659 /* 30126 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10660 /* 30128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10661 /* 30131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10662 /* 30137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10663 /* 30143 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10664 /* 30146 */ GIR_RootConstrainSelectedInstOperands,
10665 /* 30147 */ // GIR_Coverage, 3966,
10666 /* 30147 */ GIR_EraseRootFromParent_Done,
10667 /* 30148 */ // Label 618: @30148
10668 /* 30148 */ GIM_Reject,
10669 /* 30149 */ // Label 615: @30149
10670 /* 30149 */ GIM_Reject,
10671 /* 30150 */ // Label 11: @30150
10672 /* 30150 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 622*/ GIMT_Encode4(30388),
10673 /* 30161 */ /*GILLT_v4s32*//*Label 619*/ GIMT_Encode4(30193), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
10674 /* 30177 */ /*GILLT_v8s16*//*Label 620*/ GIMT_Encode4(30258), GIMT_Encode4(0), GIMT_Encode4(0),
10675 /* 30189 */ /*GILLT_v16s8*//*Label 621*/ GIMT_Encode4(30323),
10676 /* 30193 */ // Label 619: @30193
10677 /* 30193 */ GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(30257), // Rule ID 3950 //
10678 /* 30198 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10679 /* 30201 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10680 /* 30204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10681 /* 30208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10682 /* 30212 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10683 /* 30216 */ // (avgceilu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10684 /* 30216 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10685 /* 30219 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10686 /* 30223 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10687 /* 30228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32),
10688 /* 30231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10689 /* 30233 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10690 /* 30235 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10691 /* 30237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10692 /* 30240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10693 /* 30246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10694 /* 30252 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10695 /* 30255 */ GIR_RootConstrainSelectedInstOperands,
10696 /* 30256 */ // GIR_Coverage, 3950,
10697 /* 30256 */ GIR_EraseRootFromParent_Done,
10698 /* 30257 */ // Label 623: @30257
10699 /* 30257 */ GIM_Reject,
10700 /* 30258 */ // Label 620: @30258
10701 /* 30258 */ GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(30322), // Rule ID 3946 //
10702 /* 30263 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10703 /* 30266 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10704 /* 30269 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10705 /* 30273 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10706 /* 30277 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10707 /* 30281 */ // (avgceilu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10708 /* 30281 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10709 /* 30284 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10710 /* 30288 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10711 /* 30293 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16),
10712 /* 30296 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10713 /* 30298 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10714 /* 30300 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10715 /* 30302 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10716 /* 30305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10717 /* 30311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10718 /* 30317 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10719 /* 30320 */ GIR_RootConstrainSelectedInstOperands,
10720 /* 30321 */ // GIR_Coverage, 3946,
10721 /* 30321 */ GIR_EraseRootFromParent_Done,
10722 /* 30322 */ // Label 624: @30322
10723 /* 30322 */ GIM_Reject,
10724 /* 30323 */ // Label 621: @30323
10725 /* 30323 */ GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(30387), // Rule ID 3942 //
10726 /* 30328 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10727 /* 30331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10728 /* 30334 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10729 /* 30338 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10730 /* 30342 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10731 /* 30346 */ // (avgceilu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10732 /* 30346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10733 /* 30349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10734 /* 30353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10735 /* 30358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8),
10736 /* 30361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10737 /* 30363 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10738 /* 30365 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10739 /* 30367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10740 /* 30370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10741 /* 30376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10742 /* 30382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10743 /* 30385 */ GIR_RootConstrainSelectedInstOperands,
10744 /* 30386 */ // GIR_Coverage, 3942,
10745 /* 30386 */ GIR_EraseRootFromParent_Done,
10746 /* 30387 */ // Label 625: @30387
10747 /* 30387 */ GIM_Reject,
10748 /* 30388 */ // Label 622: @30388
10749 /* 30388 */ GIM_Reject,
10750 /* 30389 */ // Label 12: @30389
10751 /* 30389 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 629*/ GIMT_Encode4(30627),
10752 /* 30400 */ /*GILLT_v4s32*//*Label 626*/ GIMT_Encode4(30432), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
10753 /* 30416 */ /*GILLT_v8s16*//*Label 627*/ GIMT_Encode4(30497), GIMT_Encode4(0), GIMT_Encode4(0),
10754 /* 30428 */ /*GILLT_v16s8*//*Label 628*/ GIMT_Encode4(30562),
10755 /* 30432 */ // Label 626: @30432
10756 /* 30432 */ GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(30496), // Rule ID 3962 //
10757 /* 30437 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10758 /* 30440 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10759 /* 30443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10760 /* 30447 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10761 /* 30451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10762 /* 30455 */ // (avgfloors:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10763 /* 30455 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10764 /* 30458 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10765 /* 30462 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10766 /* 30467 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32),
10767 /* 30470 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10768 /* 30472 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10769 /* 30474 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10770 /* 30476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10771 /* 30479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10772 /* 30485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10773 /* 30491 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10774 /* 30494 */ GIR_RootConstrainSelectedInstOperands,
10775 /* 30495 */ // GIR_Coverage, 3962,
10776 /* 30495 */ GIR_EraseRootFromParent_Done,
10777 /* 30496 */ // Label 630: @30496
10778 /* 30496 */ GIM_Reject,
10779 /* 30497 */ // Label 627: @30497
10780 /* 30497 */ GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(30561), // Rule ID 3958 //
10781 /* 30502 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10782 /* 30505 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10783 /* 30508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10784 /* 30512 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10785 /* 30516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10786 /* 30520 */ // (avgfloors:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10787 /* 30520 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10788 /* 30523 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10789 /* 30527 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10790 /* 30532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16),
10791 /* 30535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10792 /* 30537 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10793 /* 30539 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10794 /* 30541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10795 /* 30544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10796 /* 30550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10797 /* 30556 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10798 /* 30559 */ GIR_RootConstrainSelectedInstOperands,
10799 /* 30560 */ // GIR_Coverage, 3958,
10800 /* 30560 */ GIR_EraseRootFromParent_Done,
10801 /* 30561 */ // Label 631: @30561
10802 /* 30561 */ GIM_Reject,
10803 /* 30562 */ // Label 628: @30562
10804 /* 30562 */ GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(30626), // Rule ID 3955 //
10805 /* 30567 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10806 /* 30570 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10807 /* 30573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10808 /* 30577 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10809 /* 30581 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10810 /* 30585 */ // (avgfloors:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10811 /* 30585 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10812 /* 30588 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10813 /* 30592 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10814 /* 30597 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8),
10815 /* 30600 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10816 /* 30602 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10817 /* 30604 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10818 /* 30606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10819 /* 30609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10820 /* 30615 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10821 /* 30621 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10822 /* 30624 */ GIR_RootConstrainSelectedInstOperands,
10823 /* 30625 */ // GIR_Coverage, 3955,
10824 /* 30625 */ GIR_EraseRootFromParent_Done,
10825 /* 30626 */ // Label 632: @30626
10826 /* 30626 */ GIM_Reject,
10827 /* 30627 */ // Label 629: @30627
10828 /* 30627 */ GIM_Reject,
10829 /* 30628 */ // Label 13: @30628
10830 /* 30628 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 636*/ GIMT_Encode4(30866),
10831 /* 30639 */ /*GILLT_v4s32*//*Label 633*/ GIMT_Encode4(30671), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
10832 /* 30655 */ /*GILLT_v8s16*//*Label 634*/ GIMT_Encode4(30736), GIMT_Encode4(0), GIMT_Encode4(0),
10833 /* 30667 */ /*GILLT_v16s8*//*Label 635*/ GIMT_Encode4(30801),
10834 /* 30671 */ // Label 633: @30671
10835 /* 30671 */ GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(30735), // Rule ID 3938 //
10836 /* 30676 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
10837 /* 30679 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
10838 /* 30682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10839 /* 30686 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10840 /* 30690 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10841 /* 30694 */ // (avgceils:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
10842 /* 30694 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10843 /* 30697 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10844 /* 30701 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10845 /* 30706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32),
10846 /* 30709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10847 /* 30711 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10848 /* 30713 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10849 /* 30715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10850 /* 30718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10851 /* 30724 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10852 /* 30730 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10853 /* 30733 */ GIR_RootConstrainSelectedInstOperands,
10854 /* 30734 */ // GIR_Coverage, 3938,
10855 /* 30734 */ GIR_EraseRootFromParent_Done,
10856 /* 30735 */ // Label 637: @30735
10857 /* 30735 */ GIM_Reject,
10858 /* 30736 */ // Label 634: @30736
10859 /* 30736 */ GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(30800), // Rule ID 3934 //
10860 /* 30741 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
10861 /* 30744 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
10862 /* 30747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10863 /* 30751 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10864 /* 30755 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10865 /* 30759 */ // (avgceils:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
10866 /* 30759 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10867 /* 30762 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10868 /* 30766 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10869 /* 30771 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16),
10870 /* 30774 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10871 /* 30776 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10872 /* 30778 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10873 /* 30780 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10874 /* 30783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10875 /* 30789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10876 /* 30795 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10877 /* 30798 */ GIR_RootConstrainSelectedInstOperands,
10878 /* 30799 */ // GIR_Coverage, 3934,
10879 /* 30799 */ GIR_EraseRootFromParent_Done,
10880 /* 30800 */ // Label 638: @30800
10881 /* 30800 */ GIM_Reject,
10882 /* 30801 */ // Label 635: @30801
10883 /* 30801 */ GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(30865), // Rule ID 3931 //
10884 /* 30806 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
10885 /* 30809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
10886 /* 30812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10887 /* 30816 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10888 /* 30820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
10889 /* 30824 */ // (avgceils:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
10890 /* 30824 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
10891 /* 30827 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
10892 /* 30831 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
10893 /* 30836 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8),
10894 /* 30839 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
10895 /* 30841 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
10896 /* 30843 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
10897 /* 30845 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
10898 /* 30848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10899 /* 30854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
10900 /* 30860 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
10901 /* 30863 */ GIR_RootConstrainSelectedInstOperands,
10902 /* 30864 */ // GIR_Coverage, 3931,
10903 /* 30864 */ GIR_EraseRootFromParent_Done,
10904 /* 30865 */ // Label 639: @30865
10905 /* 30865 */ GIM_Reject,
10906 /* 30866 */ // Label 636: @30866
10907 /* 30866 */ GIM_Reject,
10908 /* 30867 */ // Label 14: @30867
10909 /* 30867 */ GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(31253),
10910 /* 30872 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
10911 /* 30875 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(16), /*)*//*default:*//*Label 645*/ GIMT_Encode4(31252),
10912 /* 30886 */ /*GILLT_v2s64*//*Label 641*/ GIMT_Encode4(30930), GIMT_Encode4(0), GIMT_Encode4(0),
10913 /* 30898 */ /*GILLT_v4s32*//*Label 642*/ GIMT_Encode4(30988), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
10914 /* 30914 */ /*GILLT_v8s16*//*Label 643*/ GIMT_Encode4(31091), GIMT_Encode4(0), GIMT_Encode4(0),
10915 /* 30926 */ /*GILLT_v16s8*//*Label 644*/ GIMT_Encode4(31194),
10916 /* 30930 */ // Label 641: @30930
10917 /* 30930 */ GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(30987), // Rule ID 3374 //
10918 /* 30935 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10919 /* 30938 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
10920 /* 30941 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
10921 /* 30944 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10922 /* 30948 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10923 /* 30952 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10924 /* 30956 */ // (concat_vectors:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Dn, DPR:{ *:[v1i64] }:$Dm) => (REG_SEQUENCE:{ *:[v2i64] } QPR:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v1i64] }:$Dm, dsub_1:{ *:[i32] })
10925 /* 30956 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
10926 /* 30959 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10927 /* 30961 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
10928 /* 30963 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
10929 /* 30966 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10930 /* 30968 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
10931 /* 30971 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10932 /* 30976 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
10933 /* 30981 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
10934 /* 30986 */ // GIR_Coverage, 3374,
10935 /* 30986 */ GIR_EraseRootFromParent_Done,
10936 /* 30987 */ // Label 646: @30987
10937 /* 30987 */ GIM_Reject,
10938 /* 30988 */ // Label 642: @30988
10939 /* 30988 */ GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(31090),
10940 /* 30993 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
10941 /* 30996 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
10942 /* 30999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10943 /* 31003 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10944 /* 31007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10945 /* 31011 */ GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(31050), // Rule ID 3375 //
10946 /* 31016 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10947 /* 31019 */ // (concat_vectors:{ *:[v4i32] } DPR:{ *:[v2i32] }:$Dn, DPR:{ *:[v2i32] }:$Dm) => (REG_SEQUENCE:{ *:[v4i32] } QPR:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2i32] }:$Dm, dsub_1:{ *:[i32] })
10948 /* 31019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
10949 /* 31022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10950 /* 31024 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
10951 /* 31026 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
10952 /* 31029 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10953 /* 31031 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
10954 /* 31034 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10955 /* 31039 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
10956 /* 31044 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
10957 /* 31049 */ // GIR_Coverage, 3375,
10958 /* 31049 */ GIR_EraseRootFromParent_Done,
10959 /* 31050 */ // Label 648: @31050
10960 /* 31050 */ GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(31089), // Rule ID 3378 //
10961 /* 31055 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10962 /* 31058 */ // (concat_vectors:{ *:[v4f32] } DPR:{ *:[v2f32] }:$Dn, DPR:{ *:[v2f32] }:$Dm) => (REG_SEQUENCE:{ *:[v4f32] } QPR:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v2f32] }:$Dm, dsub_1:{ *:[i32] })
10963 /* 31058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
10964 /* 31061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10965 /* 31063 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
10966 /* 31065 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
10967 /* 31068 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10968 /* 31070 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
10969 /* 31073 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10970 /* 31078 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
10971 /* 31083 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
10972 /* 31088 */ // GIR_Coverage, 3378,
10973 /* 31088 */ GIR_EraseRootFromParent_Done,
10974 /* 31089 */ // Label 649: @31089
10975 /* 31089 */ GIM_Reject,
10976 /* 31090 */ // Label 647: @31090
10977 /* 31090 */ GIM_Reject,
10978 /* 31091 */ // Label 643: @31091
10979 /* 31091 */ GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(31193),
10980 /* 31096 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
10981 /* 31099 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
10982 /* 31102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
10983 /* 31106 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10984 /* 31110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
10985 /* 31114 */ GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(31153), // Rule ID 3376 //
10986 /* 31119 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
10987 /* 31122 */ // (concat_vectors:{ *:[v8i16] } DPR:{ *:[v4i16] }:$Dn, DPR:{ *:[v4i16] }:$Dm) => (REG_SEQUENCE:{ *:[v8i16] } QPR:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4i16] }:$Dm, dsub_1:{ *:[i32] })
10988 /* 31122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
10989 /* 31125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
10990 /* 31127 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
10991 /* 31129 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
10992 /* 31132 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
10993 /* 31134 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
10994 /* 31137 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
10995 /* 31142 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
10996 /* 31147 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
10997 /* 31152 */ // GIR_Coverage, 3376,
10998 /* 31152 */ GIR_EraseRootFromParent_Done,
10999 /* 31153 */ // Label 651: @31153
11000 /* 31153 */ GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(31192), // Rule ID 3379 //
11001 /* 31158 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11002 /* 31161 */ // (concat_vectors:{ *:[v8f16] } DPR:{ *:[v4f16] }:$Dn, DPR:{ *:[v4f16] }:$Dm) => (REG_SEQUENCE:{ *:[v8f16] } QPR:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v4f16] }:$Dm, dsub_1:{ *:[i32] })
11003 /* 31161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
11004 /* 31164 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
11005 /* 31166 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
11006 /* 31168 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
11007 /* 31171 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
11008 /* 31173 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
11009 /* 31176 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11010 /* 31181 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
11011 /* 31186 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
11012 /* 31191 */ // GIR_Coverage, 3379,
11013 /* 31191 */ GIR_EraseRootFromParent_Done,
11014 /* 31192 */ // Label 652: @31192
11015 /* 31192 */ GIM_Reject,
11016 /* 31193 */ // Label 650: @31193
11017 /* 31193 */ GIM_Reject,
11018 /* 31194 */ // Label 644: @31194
11019 /* 31194 */ GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(31251), // Rule ID 3377 //
11020 /* 31199 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11021 /* 31202 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
11022 /* 31205 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
11023 /* 31208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11024 /* 31212 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11025 /* 31216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11026 /* 31220 */ // (concat_vectors:{ *:[v16i8] } DPR:{ *:[v8i8] }:$Dn, DPR:{ *:[v8i8] }:$Dm) => (REG_SEQUENCE:{ *:[v16i8] } QPR:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dn, dsub_0:{ *:[i32] }, DPR:{ *:[v8i8] }:$Dm, dsub_1:{ *:[i32] })
11027 /* 31220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
11028 /* 31223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
11029 /* 31225 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
11030 /* 31227 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1,
11031 /* 31230 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
11032 /* 31232 */ GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/2,
11033 /* 31235 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11034 /* 31240 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
11035 /* 31245 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
11036 /* 31250 */ // GIR_Coverage, 3377,
11037 /* 31250 */ GIR_EraseRootFromParent_Done,
11038 /* 31251 */ // Label 653: @31251
11039 /* 31251 */ GIM_Reject,
11040 /* 31252 */ // Label 645: @31252
11041 /* 31252 */ GIM_Reject,
11042 /* 31253 */ // Label 640: @31253
11043 /* 31253 */ GIM_Reject,
11044 /* 31254 */ // Label 15: @31254
11045 /* 31254 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 663*/ GIMT_Encode4(40265),
11046 /* 31265 */ /*GILLT_s32*//*Label 654*/ GIMT_Encode4(31325),
11047 /* 31269 */ /*GILLT_s64*//*Label 655*/ GIMT_Encode4(31473), GIMT_Encode4(0),
11048 /* 31277 */ /*GILLT_v2s32*//*Label 656*/ GIMT_Encode4(32228),
11049 /* 31281 */ /*GILLT_v2s64*//*Label 657*/ GIMT_Encode4(32983), GIMT_Encode4(0),
11050 /* 31289 */ /*GILLT_v4s16*//*Label 658*/ GIMT_Encode4(34702),
11051 /* 31293 */ /*GILLT_v4s32*//*Label 659*/ GIMT_Encode4(35457), GIMT_Encode4(0), GIMT_Encode4(0),
11052 /* 31305 */ /*GILLT_v8s8*//*Label 660*/ GIMT_Encode4(37176),
11053 /* 31309 */ /*GILLT_v8s16*//*Label 661*/ GIMT_Encode4(37591), GIMT_Encode4(0), GIMT_Encode4(0),
11054 /* 31321 */ /*GILLT_v16s8*//*Label 662*/ GIMT_Encode4(39310),
11055 /* 31325 */ // Label 654: @31325
11056 /* 31325 */ GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(31472),
11057 /* 31330 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
11058 /* 31333 */ GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(31367), // Rule ID 739 //
11059 /* 31338 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs),
11060 /* 31341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
11061 /* 31345 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
11062 /* 31349 */ // (bitconvert:{ *:[i32] } SPR:{ *:[f32] }:$Sn) => (VMOVRS:{ *:[i32] } SPR:{ *:[f32] }:$Sn)
11063 /* 31349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVRS),
11064 /* 31352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
11065 /* 31354 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
11066 /* 31356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11067 /* 31359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11068 /* 31365 */ GIR_RootConstrainSelectedInstOperands,
11069 /* 31366 */ // GIR_Coverage, 739,
11070 /* 31366 */ GIR_EraseRootFromParent_Done,
11071 /* 31367 */ // Label 665: @31367
11072 /* 31367 */ GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(31401), // Rule ID 740 //
11073 /* 31372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs_UseVMOVSR),
11074 /* 31375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
11075 /* 31379 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
11076 /* 31383 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$Rt) => (VMOVSR:{ *:[f32] } GPR:{ *:[i32] }:$Rt)
11077 /* 31383 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVSR),
11078 /* 31386 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sn]
11079 /* 31388 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt
11080 /* 31390 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11081 /* 31393 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11082 /* 31399 */ GIR_RootConstrainSelectedInstOperands,
11083 /* 31400 */ // GIR_Coverage, 740,
11084 /* 31400 */ GIR_EraseRootFromParent_Done,
11085 /* 31401 */ // Label 666: @31401
11086 /* 31401 */ GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(31471), // Rule ID 3068 //
11087 /* 31406 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseVMOVSR_HasNEON),
11088 /* 31409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
11089 /* 31413 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
11090 /* 31417 */ // (bitconvert:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VMOVDRR:{ *:[f64] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$a), ssub_0:{ *:[i32] })
11091 /* 31417 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64,
11092 /* 31420 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VMOVDRR),
11093 /* 31424 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
11094 /* 31429 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
11095 /* 31433 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
11096 /* 31437 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
11097 /* 31440 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11098 /* 31446 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
11099 /* 31448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11100 /* 31451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
11101 /* 31453 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
11102 /* 31460 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
11103 /* 31465 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
11104 /* 31470 */ // GIR_Coverage, 3068,
11105 /* 31470 */ GIR_EraseRootFromParent_Done,
11106 /* 31471 */ // Label 667: @31471
11107 /* 31471 */ GIM_Reject,
11108 /* 31472 */ // Label 664: @31472
11109 /* 31472 */ GIM_Reject,
11110 /* 31473 */ // Label 655: @31473
11111 /* 31473 */ GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(31505), // Rule ID 3070 //
11112 /* 31478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11113 /* 31481 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11114 /* 31484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11115 /* 31488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11116 /* 31492 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[f64] }:$src
11117 /* 31492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11118 /* 31495 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11119 /* 31497 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11120 /* 31499 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11121 /* 31504 */ // GIR_Coverage, 3070,
11122 /* 31504 */ GIR_EraseRootFromParent_Done,
11123 /* 31505 */ // Label 668: @31505
11124 /* 31505 */ GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(31537), // Rule ID 3071 //
11125 /* 31510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11126 /* 31513 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11127 /* 31516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11128 /* 31520 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11129 /* 31524 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v1i64] }:$src
11130 /* 31524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11131 /* 31527 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11132 /* 31529 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11133 /* 31531 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11134 /* 31536 */ // GIR_Coverage, 3071,
11135 /* 31536 */ GIR_EraseRootFromParent_Done,
11136 /* 31537 */ // Label 669: @31537
11137 /* 31537 */ GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(31569), // Rule ID 3082 //
11138 /* 31542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11139 /* 31545 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11140 /* 31548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11141 /* 31552 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11142 /* 31556 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[f64] }:$src
11143 /* 31556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11144 /* 31559 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11145 /* 31561 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11146 /* 31563 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11147 /* 31568 */ // GIR_Coverage, 3082,
11148 /* 31568 */ GIR_EraseRootFromParent_Done,
11149 /* 31569 */ // Label 670: @31569
11150 /* 31569 */ GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(31601), // Rule ID 3083 //
11151 /* 31574 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11152 /* 31577 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11153 /* 31580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11154 /* 31584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11155 /* 31588 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[f64] }:$src
11156 /* 31588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11157 /* 31591 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11158 /* 31593 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11159 /* 31595 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11160 /* 31600 */ // GIR_Coverage, 3083,
11161 /* 31600 */ GIR_EraseRootFromParent_Done,
11162 /* 31601 */ // Label 671: @31601
11163 /* 31601 */ GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(31633), // Rule ID 3084 //
11164 /* 31606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11165 /* 31609 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11166 /* 31612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11167 /* 31616 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11168 /* 31620 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[f64] }:$src
11169 /* 31620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11170 /* 31623 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11171 /* 31625 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11172 /* 31627 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11173 /* 31632 */ // GIR_Coverage, 3084,
11174 /* 31632 */ GIR_EraseRootFromParent_Done,
11175 /* 31633 */ // Label 672: @31633
11176 /* 31633 */ GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(31665), // Rule ID 3085 //
11177 /* 31638 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11178 /* 31641 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11179 /* 31644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11180 /* 31648 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11181 /* 31652 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[f64] }:$src
11182 /* 31652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11183 /* 31655 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11184 /* 31657 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11185 /* 31659 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11186 /* 31664 */ // GIR_Coverage, 3085,
11187 /* 31664 */ GIR_EraseRootFromParent_Done,
11188 /* 31665 */ // Label 673: @31665
11189 /* 31665 */ GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(31697), // Rule ID 3086 //
11190 /* 31670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11191 /* 31673 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
11192 /* 31676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11193 /* 31680 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11194 /* 31684 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[f64] }:$src
11195 /* 31684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11196 /* 31687 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11197 /* 31689 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11198 /* 31691 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11199 /* 31696 */ // GIR_Coverage, 3086,
11200 /* 31696 */ GIR_EraseRootFromParent_Done,
11201 /* 31697 */ // Label 674: @31697
11202 /* 31697 */ GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(31729), // Rule ID 3087 //
11203 /* 31702 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11204 /* 31705 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11205 /* 31708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11206 /* 31712 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11207 /* 31716 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v1i64] }:$src
11208 /* 31716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11209 /* 31719 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11210 /* 31721 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11211 /* 31723 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11212 /* 31728 */ // GIR_Coverage, 3087,
11213 /* 31728 */ GIR_EraseRootFromParent_Done,
11214 /* 31729 */ // Label 675: @31729
11215 /* 31729 */ GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(31761), // Rule ID 3088 //
11216 /* 31734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11217 /* 31737 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11218 /* 31740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11219 /* 31744 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11220 /* 31748 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v1i64] }:$src
11221 /* 31748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11222 /* 31751 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11223 /* 31753 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11224 /* 31755 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11225 /* 31760 */ // GIR_Coverage, 3088,
11226 /* 31760 */ GIR_EraseRootFromParent_Done,
11227 /* 31761 */ // Label 676: @31761
11228 /* 31761 */ GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(31793), // Rule ID 3089 //
11229 /* 31766 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11230 /* 31769 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11231 /* 31772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11232 /* 31776 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11233 /* 31780 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v1i64] }:$src
11234 /* 31780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11235 /* 31783 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11236 /* 31785 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11237 /* 31787 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11238 /* 31792 */ // GIR_Coverage, 3089,
11239 /* 31792 */ GIR_EraseRootFromParent_Done,
11240 /* 31793 */ // Label 677: @31793
11241 /* 31793 */ GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(31825), // Rule ID 3090 //
11242 /* 31798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11243 /* 31801 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11244 /* 31804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11245 /* 31808 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11246 /* 31812 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v1i64] }:$src
11247 /* 31812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11248 /* 31815 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11249 /* 31817 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11250 /* 31819 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11251 /* 31824 */ // GIR_Coverage, 3090,
11252 /* 31824 */ GIR_EraseRootFromParent_Done,
11253 /* 31825 */ // Label 678: @31825
11254 /* 31825 */ GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(31857), // Rule ID 3091 //
11255 /* 31830 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11256 /* 31833 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
11257 /* 31836 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11258 /* 31840 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11259 /* 31844 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v1i64] }:$src
11260 /* 31844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11261 /* 31847 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11262 /* 31849 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11263 /* 31851 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11264 /* 31856 */ // GIR_Coverage, 3091,
11265 /* 31856 */ GIR_EraseRootFromParent_Done,
11266 /* 31857 */ // Label 679: @31857
11267 /* 31857 */ GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(31894), // Rule ID 3154 //
11268 /* 31862 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11269 /* 31865 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11270 /* 31868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11271 /* 31872 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11272 /* 31876 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2f32] }:$src)
11273 /* 31876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11274 /* 31879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11275 /* 31881 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11276 /* 31883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11277 /* 31886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11278 /* 31892 */ GIR_RootConstrainSelectedInstOperands,
11279 /* 31893 */ // GIR_Coverage, 3154,
11280 /* 31893 */ GIR_EraseRootFromParent_Done,
11281 /* 31894 */ // Label 680: @31894
11282 /* 31894 */ GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(31931), // Rule ID 3155 //
11283 /* 31899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11284 /* 31902 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11285 /* 31905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11286 /* 31909 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11287 /* 31913 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[f64] } DPR:{ *:[v2i32] }:$src)
11288 /* 31913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11289 /* 31916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11290 /* 31918 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11291 /* 31920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11292 /* 31923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11293 /* 31929 */ GIR_RootConstrainSelectedInstOperands,
11294 /* 31930 */ // GIR_Coverage, 3155,
11295 /* 31930 */ GIR_EraseRootFromParent_Done,
11296 /* 31931 */ // Label 681: @31931
11297 /* 31931 */ GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(31968), // Rule ID 3156 //
11298 /* 31936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11299 /* 31939 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11300 /* 31942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11301 /* 31946 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11302 /* 31950 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4f16] }:$src)
11303 /* 31950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11304 /* 31953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11305 /* 31955 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11306 /* 31957 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11307 /* 31960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11308 /* 31966 */ GIR_RootConstrainSelectedInstOperands,
11309 /* 31967 */ // GIR_Coverage, 3156,
11310 /* 31967 */ GIR_EraseRootFromParent_Done,
11311 /* 31968 */ // Label 682: @31968
11312 /* 31968 */ GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(32005), // Rule ID 3157 //
11313 /* 31973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11314 /* 31976 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11315 /* 31979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11316 /* 31983 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11317 /* 31987 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[f64] } DPR:{ *:[v4i16] }:$src)
11318 /* 31987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11319 /* 31990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11320 /* 31992 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11321 /* 31994 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11322 /* 31997 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11323 /* 32003 */ GIR_RootConstrainSelectedInstOperands,
11324 /* 32004 */ // GIR_Coverage, 3157,
11325 /* 32004 */ GIR_EraseRootFromParent_Done,
11326 /* 32005 */ // Label 683: @32005
11327 /* 32005 */ GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(32042), // Rule ID 3158 //
11328 /* 32010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11329 /* 32013 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
11330 /* 32016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11331 /* 32020 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11332 /* 32024 */ // (bitconvert:{ *:[f64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[f64] } DPR:{ *:[v8i8] }:$src)
11333 /* 32024 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
11334 /* 32027 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11335 /* 32029 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11336 /* 32031 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11337 /* 32034 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11338 /* 32040 */ GIR_RootConstrainSelectedInstOperands,
11339 /* 32041 */ // GIR_Coverage, 3158,
11340 /* 32041 */ GIR_EraseRootFromParent_Done,
11341 /* 32042 */ // Label 684: @32042
11342 /* 32042 */ GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(32079), // Rule ID 3159 //
11343 /* 32047 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11344 /* 32050 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11345 /* 32053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11346 /* 32057 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11347 /* 32061 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2f32] }:$src)
11348 /* 32061 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11349 /* 32064 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11350 /* 32066 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11351 /* 32068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11352 /* 32071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11353 /* 32077 */ GIR_RootConstrainSelectedInstOperands,
11354 /* 32078 */ // GIR_Coverage, 3159,
11355 /* 32078 */ GIR_EraseRootFromParent_Done,
11356 /* 32079 */ // Label 685: @32079
11357 /* 32079 */ GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(32116), // Rule ID 3160 //
11358 /* 32084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11359 /* 32087 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11360 /* 32090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11361 /* 32094 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11362 /* 32098 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src) => (VREV64d32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$src)
11363 /* 32098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11364 /* 32101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11365 /* 32103 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11366 /* 32105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11367 /* 32108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11368 /* 32114 */ GIR_RootConstrainSelectedInstOperands,
11369 /* 32115 */ // GIR_Coverage, 3160,
11370 /* 32115 */ GIR_EraseRootFromParent_Done,
11371 /* 32116 */ // Label 686: @32116
11372 /* 32116 */ GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(32153), // Rule ID 3161 //
11373 /* 32121 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11374 /* 32124 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11375 /* 32127 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11376 /* 32131 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11377 /* 32135 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4f16] }:$src)
11378 /* 32135 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11379 /* 32138 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11380 /* 32140 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11381 /* 32142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11382 /* 32145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11383 /* 32151 */ GIR_RootConstrainSelectedInstOperands,
11384 /* 32152 */ // GIR_Coverage, 3161,
11385 /* 32152 */ GIR_EraseRootFromParent_Done,
11386 /* 32153 */ // Label 687: @32153
11387 /* 32153 */ GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(32190), // Rule ID 3162 //
11388 /* 32158 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11389 /* 32161 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11390 /* 32164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11391 /* 32168 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11392 /* 32172 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src) => (VREV64d16:{ *:[v1i64] } DPR:{ *:[v4i16] }:$src)
11393 /* 32172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
11394 /* 32175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11395 /* 32177 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11396 /* 32179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11397 /* 32182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11398 /* 32188 */ GIR_RootConstrainSelectedInstOperands,
11399 /* 32189 */ // GIR_Coverage, 3162,
11400 /* 32189 */ GIR_EraseRootFromParent_Done,
11401 /* 32190 */ // Label 688: @32190
11402 /* 32190 */ GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(32227), // Rule ID 3163 //
11403 /* 32195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11404 /* 32198 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
11405 /* 32201 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11406 /* 32205 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11407 /* 32209 */ // (bitconvert:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src) => (VREV64d8:{ *:[v1i64] } DPR:{ *:[v8i8] }:$src)
11408 /* 32209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
11409 /* 32212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11410 /* 32214 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11411 /* 32216 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11412 /* 32219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11413 /* 32225 */ GIR_RootConstrainSelectedInstOperands,
11414 /* 32226 */ // GIR_Coverage, 3163,
11415 /* 32226 */ GIR_EraseRootFromParent_Done,
11416 /* 32227 */ // Label 689: @32227
11417 /* 32227 */ GIM_Reject,
11418 /* 32228 */ // Label 656: @32228
11419 /* 32228 */ GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(32260), // Rule ID 3072 //
11420 /* 32233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11421 /* 32236 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11422 /* 32239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11423 /* 32243 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11424 /* 32247 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v2f32] }:$src
11425 /* 32247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11426 /* 32250 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11427 /* 32252 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11428 /* 32254 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11429 /* 32259 */ // GIR_Coverage, 3072,
11430 /* 32259 */ GIR_EraseRootFromParent_Done,
11431 /* 32260 */ // Label 690: @32260
11432 /* 32260 */ GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(32292), // Rule ID 3073 //
11433 /* 32265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11434 /* 32268 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
11435 /* 32271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11436 /* 32275 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11437 /* 32279 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v2i32] }:$src
11438 /* 32279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11439 /* 32282 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11440 /* 32284 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11441 /* 32286 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11442 /* 32291 */ // GIR_Coverage, 3073,
11443 /* 32291 */ GIR_EraseRootFromParent_Done,
11444 /* 32292 */ // Label 691: @32292
11445 /* 32292 */ GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(32324), // Rule ID 3092 //
11446 /* 32297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11447 /* 32300 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11448 /* 32303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11449 /* 32307 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11450 /* 32311 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2f32] }:$src
11451 /* 32311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11452 /* 32314 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11453 /* 32316 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11454 /* 32318 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11455 /* 32323 */ // GIR_Coverage, 3092,
11456 /* 32323 */ GIR_EraseRootFromParent_Done,
11457 /* 32324 */ // Label 692: @32324
11458 /* 32324 */ GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(32356), // Rule ID 3093 //
11459 /* 32329 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11460 /* 32332 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11461 /* 32335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11462 /* 32339 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11463 /* 32343 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2f32] }:$src
11464 /* 32343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11465 /* 32346 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11466 /* 32348 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11467 /* 32350 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11468 /* 32355 */ // GIR_Coverage, 3093,
11469 /* 32355 */ GIR_EraseRootFromParent_Done,
11470 /* 32356 */ // Label 693: @32356
11471 /* 32356 */ GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(32388), // Rule ID 3094 //
11472 /* 32361 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11473 /* 32364 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11474 /* 32367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11475 /* 32371 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11476 /* 32375 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2f32] }:$src
11477 /* 32375 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11478 /* 32378 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11479 /* 32380 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11480 /* 32382 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11481 /* 32387 */ // GIR_Coverage, 3094,
11482 /* 32387 */ GIR_EraseRootFromParent_Done,
11483 /* 32388 */ // Label 694: @32388
11484 /* 32388 */ GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(32420), // Rule ID 3095 //
11485 /* 32393 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11486 /* 32396 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11487 /* 32399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11488 /* 32403 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11489 /* 32407 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2f32] }:$src
11490 /* 32407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11491 /* 32410 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11492 /* 32412 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11493 /* 32414 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11494 /* 32419 */ // GIR_Coverage, 3095,
11495 /* 32419 */ GIR_EraseRootFromParent_Done,
11496 /* 32420 */ // Label 695: @32420
11497 /* 32420 */ GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(32452), // Rule ID 3096 //
11498 /* 32425 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11499 /* 32428 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
11500 /* 32431 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11501 /* 32435 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11502 /* 32439 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2f32] }:$src
11503 /* 32439 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11504 /* 32442 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11505 /* 32444 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11506 /* 32446 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11507 /* 32451 */ // GIR_Coverage, 3096,
11508 /* 32451 */ GIR_EraseRootFromParent_Done,
11509 /* 32452 */ // Label 696: @32452
11510 /* 32452 */ GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(32484), // Rule ID 3097 //
11511 /* 32457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11512 /* 32460 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11513 /* 32463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11514 /* 32467 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11515 /* 32471 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v2i32] }:$src
11516 /* 32471 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11517 /* 32474 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11518 /* 32476 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11519 /* 32478 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11520 /* 32483 */ // GIR_Coverage, 3097,
11521 /* 32483 */ GIR_EraseRootFromParent_Done,
11522 /* 32484 */ // Label 697: @32484
11523 /* 32484 */ GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(32516), // Rule ID 3098 //
11524 /* 32489 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11525 /* 32492 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11526 /* 32495 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11527 /* 32499 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11528 /* 32503 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v2i32] }:$src
11529 /* 32503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11530 /* 32506 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11531 /* 32508 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11532 /* 32510 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11533 /* 32515 */ // GIR_Coverage, 3098,
11534 /* 32515 */ GIR_EraseRootFromParent_Done,
11535 /* 32516 */ // Label 698: @32516
11536 /* 32516 */ GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(32548), // Rule ID 3099 //
11537 /* 32521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11538 /* 32524 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11539 /* 32527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11540 /* 32531 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11541 /* 32535 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v2i32] }:$src
11542 /* 32535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11543 /* 32538 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11544 /* 32540 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11545 /* 32542 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11546 /* 32547 */ // GIR_Coverage, 3099,
11547 /* 32547 */ GIR_EraseRootFromParent_Done,
11548 /* 32548 */ // Label 699: @32548
11549 /* 32548 */ GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(32580), // Rule ID 3100 //
11550 /* 32553 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11551 /* 32556 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11552 /* 32559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11553 /* 32563 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11554 /* 32567 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v2i32] }:$src
11555 /* 32567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11556 /* 32570 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11557 /* 32572 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11558 /* 32574 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11559 /* 32579 */ // GIR_Coverage, 3100,
11560 /* 32579 */ GIR_EraseRootFromParent_Done,
11561 /* 32580 */ // Label 700: @32580
11562 /* 32580 */ GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(32612), // Rule ID 3101 //
11563 /* 32585 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11564 /* 32588 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
11565 /* 32591 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11566 /* 32595 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11567 /* 32599 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v2i32] }:$src
11568 /* 32599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11569 /* 32602 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11570 /* 32604 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11571 /* 32606 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
11572 /* 32611 */ // GIR_Coverage, 3101,
11573 /* 32611 */ GIR_EraseRootFromParent_Done,
11574 /* 32612 */ // Label 701: @32612
11575 /* 32612 */ GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(32649), // Rule ID 3164 //
11576 /* 32617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11577 /* 32620 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11578 /* 32623 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11579 /* 32627 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11580 /* 32631 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[f64] }:$src)
11581 /* 32631 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11582 /* 32634 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11583 /* 32636 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11584 /* 32638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11585 /* 32641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11586 /* 32647 */ GIR_RootConstrainSelectedInstOperands,
11587 /* 32648 */ // GIR_Coverage, 3164,
11588 /* 32648 */ GIR_EraseRootFromParent_Done,
11589 /* 32649 */ // Label 702: @32649
11590 /* 32649 */ GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(32686), // Rule ID 3165 //
11591 /* 32654 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11592 /* 32657 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11593 /* 32660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11594 /* 32664 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11595 /* 32668 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2f32] } DPR:{ *:[v1i64] }:$src)
11596 /* 32668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11597 /* 32671 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11598 /* 32673 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11599 /* 32675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11600 /* 32678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11601 /* 32684 */ GIR_RootConstrainSelectedInstOperands,
11602 /* 32685 */ // GIR_Coverage, 3165,
11603 /* 32685 */ GIR_EraseRootFromParent_Done,
11604 /* 32686 */ // Label 703: @32686
11605 /* 32686 */ GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(32723), // Rule ID 3166 //
11606 /* 32691 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11607 /* 32694 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11608 /* 32697 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11609 /* 32701 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11610 /* 32705 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4f16] }:$src)
11611 /* 32705 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11612 /* 32708 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11613 /* 32710 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11614 /* 32712 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11615 /* 32715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11616 /* 32721 */ GIR_RootConstrainSelectedInstOperands,
11617 /* 32722 */ // GIR_Coverage, 3166,
11618 /* 32722 */ GIR_EraseRootFromParent_Done,
11619 /* 32723 */ // Label 704: @32723
11620 /* 32723 */ GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(32760), // Rule ID 3167 //
11621 /* 32728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11622 /* 32731 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11623 /* 32734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11624 /* 32738 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11625 /* 32742 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2f32] } DPR:{ *:[v4i16] }:$src)
11626 /* 32742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11627 /* 32745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11628 /* 32747 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11629 /* 32749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11630 /* 32752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11631 /* 32758 */ GIR_RootConstrainSelectedInstOperands,
11632 /* 32759 */ // GIR_Coverage, 3167,
11633 /* 32759 */ GIR_EraseRootFromParent_Done,
11634 /* 32760 */ // Label 705: @32760
11635 /* 32760 */ GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(32797), // Rule ID 3168 //
11636 /* 32765 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11637 /* 32768 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
11638 /* 32771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11639 /* 32775 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11640 /* 32779 */ // (bitconvert:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2f32] } DPR:{ *:[v8i8] }:$src)
11641 /* 32779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
11642 /* 32782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11643 /* 32784 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11644 /* 32786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11645 /* 32789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11646 /* 32795 */ GIR_RootConstrainSelectedInstOperands,
11647 /* 32796 */ // GIR_Coverage, 3168,
11648 /* 32796 */ GIR_EraseRootFromParent_Done,
11649 /* 32797 */ // Label 706: @32797
11650 /* 32797 */ GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(32834), // Rule ID 3169 //
11651 /* 32802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11652 /* 32805 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11653 /* 32808 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11654 /* 32812 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11655 /* 32816 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[f64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[f64] }:$src)
11656 /* 32816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11657 /* 32819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11658 /* 32821 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11659 /* 32823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11660 /* 32826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11661 /* 32832 */ GIR_RootConstrainSelectedInstOperands,
11662 /* 32833 */ // GIR_Coverage, 3169,
11663 /* 32833 */ GIR_EraseRootFromParent_Done,
11664 /* 32834 */ // Label 707: @32834
11665 /* 32834 */ GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(32871), // Rule ID 3170 //
11666 /* 32839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11667 /* 32842 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
11668 /* 32845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11669 /* 32849 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11670 /* 32853 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src) => (VREV64d32:{ *:[v2i32] } DPR:{ *:[v1i64] }:$src)
11671 /* 32853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d32),
11672 /* 32856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11673 /* 32858 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11674 /* 32860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11675 /* 32863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11676 /* 32869 */ GIR_RootConstrainSelectedInstOperands,
11677 /* 32870 */ // GIR_Coverage, 3170,
11678 /* 32870 */ GIR_EraseRootFromParent_Done,
11679 /* 32871 */ // Label 708: @32871
11680 /* 32871 */ GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(32908), // Rule ID 3171 //
11681 /* 32876 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11682 /* 32879 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11683 /* 32882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11684 /* 32886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11685 /* 32890 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4f16] }:$src)
11686 /* 32890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11687 /* 32893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11688 /* 32895 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11689 /* 32897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11690 /* 32900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11691 /* 32906 */ GIR_RootConstrainSelectedInstOperands,
11692 /* 32907 */ // GIR_Coverage, 3171,
11693 /* 32907 */ GIR_EraseRootFromParent_Done,
11694 /* 32908 */ // Label 709: @32908
11695 /* 32908 */ GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(32945), // Rule ID 3172 //
11696 /* 32913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11697 /* 32916 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
11698 /* 32919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11699 /* 32923 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11700 /* 32927 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src) => (VREV32d16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$src)
11701 /* 32927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
11702 /* 32930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11703 /* 32932 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11704 /* 32934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11705 /* 32937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11706 /* 32943 */ GIR_RootConstrainSelectedInstOperands,
11707 /* 32944 */ // GIR_Coverage, 3172,
11708 /* 32944 */ GIR_EraseRootFromParent_Done,
11709 /* 32945 */ // Label 710: @32945
11710 /* 32945 */ GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(32982), // Rule ID 3173 //
11711 /* 32950 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11712 /* 32953 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
11713 /* 32956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11714 /* 32960 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
11715 /* 32964 */ // (bitconvert:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src) => (VREV32d8:{ *:[v2i32] } DPR:{ *:[v8i8] }:$src)
11716 /* 32964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
11717 /* 32967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11718 /* 32969 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11719 /* 32971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11720 /* 32974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11721 /* 32980 */ GIR_RootConstrainSelectedInstOperands,
11722 /* 32981 */ // GIR_Coverage, 3173,
11723 /* 32981 */ GIR_EraseRootFromParent_Done,
11724 /* 32982 */ // Label 711: @32982
11725 /* 32982 */ GIM_Reject,
11726 /* 32983 */ // Label 657: @32983
11727 /* 32983 */ GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(33015), // Rule ID 3076 //
11728 /* 32988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11729 /* 32991 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
11730 /* 32994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11731 /* 32998 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11732 /* 33002 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v2f64] }:$src
11733 /* 33002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11734 /* 33005 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11735 /* 33007 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11736 /* 33009 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11737 /* 33014 */ // GIR_Coverage, 3076,
11738 /* 33014 */ GIR_EraseRootFromParent_Done,
11739 /* 33015 */ // Label 712: @33015
11740 /* 33015 */ GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(33047), // Rule ID 3077 //
11741 /* 33020 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
11742 /* 33023 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
11743 /* 33026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11744 /* 33030 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11745 /* 33034 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v2i64] }:$src
11746 /* 33034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11747 /* 33037 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11748 /* 33039 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11749 /* 33041 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11750 /* 33046 */ // GIR_Coverage, 3077,
11751 /* 33046 */ GIR_EraseRootFromParent_Done,
11752 /* 33047 */ // Label 713: @33047
11753 /* 33047 */ GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(33079), // Rule ID 3118 //
11754 /* 33052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11755 /* 33055 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11756 /* 33058 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11757 /* 33062 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11758 /* 33066 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2f64] }:$src
11759 /* 33066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11760 /* 33069 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11761 /* 33071 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11762 /* 33073 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11763 /* 33078 */ // GIR_Coverage, 3118,
11764 /* 33078 */ GIR_EraseRootFromParent_Done,
11765 /* 33079 */ // Label 714: @33079
11766 /* 33079 */ GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(33111), // Rule ID 3119 //
11767 /* 33084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11768 /* 33087 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11769 /* 33090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11770 /* 33094 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11771 /* 33098 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2f64] }:$src
11772 /* 33098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11773 /* 33101 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11774 /* 33103 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11775 /* 33105 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11776 /* 33110 */ // GIR_Coverage, 3119,
11777 /* 33110 */ GIR_EraseRootFromParent_Done,
11778 /* 33111 */ // Label 715: @33111
11779 /* 33111 */ GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(33143), // Rule ID 3120 //
11780 /* 33116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11781 /* 33119 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11782 /* 33122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11783 /* 33126 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11784 /* 33130 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2f64] }:$src
11785 /* 33130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11786 /* 33133 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11787 /* 33135 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11788 /* 33137 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11789 /* 33142 */ // GIR_Coverage, 3120,
11790 /* 33142 */ GIR_EraseRootFromParent_Done,
11791 /* 33143 */ // Label 716: @33143
11792 /* 33143 */ GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(33175), // Rule ID 3121 //
11793 /* 33148 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11794 /* 33151 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11795 /* 33154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11796 /* 33158 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11797 /* 33162 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2f64] }:$src
11798 /* 33162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11799 /* 33165 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11800 /* 33167 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11801 /* 33169 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11802 /* 33174 */ // GIR_Coverage, 3121,
11803 /* 33174 */ GIR_EraseRootFromParent_Done,
11804 /* 33175 */ // Label 717: @33175
11805 /* 33175 */ GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(33207), // Rule ID 3122 //
11806 /* 33180 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11807 /* 33183 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
11808 /* 33186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11809 /* 33190 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11810 /* 33194 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2f64] }:$src
11811 /* 33194 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11812 /* 33197 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11813 /* 33199 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11814 /* 33201 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11815 /* 33206 */ // GIR_Coverage, 3122,
11816 /* 33206 */ GIR_EraseRootFromParent_Done,
11817 /* 33207 */ // Label 718: @33207
11818 /* 33207 */ GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(33239), // Rule ID 3123 //
11819 /* 33212 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11820 /* 33215 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11821 /* 33218 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11822 /* 33222 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11823 /* 33226 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v2i64] }:$src
11824 /* 33226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11825 /* 33229 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11826 /* 33231 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11827 /* 33233 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11828 /* 33238 */ // GIR_Coverage, 3123,
11829 /* 33238 */ GIR_EraseRootFromParent_Done,
11830 /* 33239 */ // Label 719: @33239
11831 /* 33239 */ GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(33271), // Rule ID 3124 //
11832 /* 33244 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11833 /* 33247 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11834 /* 33250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11835 /* 33254 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11836 /* 33258 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v2i64] }:$src
11837 /* 33258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11838 /* 33261 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11839 /* 33263 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11840 /* 33265 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11841 /* 33270 */ // GIR_Coverage, 3124,
11842 /* 33270 */ GIR_EraseRootFromParent_Done,
11843 /* 33271 */ // Label 720: @33271
11844 /* 33271 */ GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(33303), // Rule ID 3125 //
11845 /* 33276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11846 /* 33279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11847 /* 33282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11848 /* 33286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11849 /* 33290 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v2i64] }:$src
11850 /* 33290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11851 /* 33293 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11852 /* 33295 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11853 /* 33297 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11854 /* 33302 */ // GIR_Coverage, 3125,
11855 /* 33302 */ GIR_EraseRootFromParent_Done,
11856 /* 33303 */ // Label 721: @33303
11857 /* 33303 */ GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(33335), // Rule ID 3126 //
11858 /* 33308 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11859 /* 33311 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11860 /* 33314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11861 /* 33318 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11862 /* 33322 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v2i64] }:$src
11863 /* 33322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11864 /* 33325 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11865 /* 33327 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11866 /* 33329 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11867 /* 33334 */ // GIR_Coverage, 3126,
11868 /* 33334 */ GIR_EraseRootFromParent_Done,
11869 /* 33335 */ // Label 722: @33335
11870 /* 33335 */ GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(33367), // Rule ID 3127 //
11871 /* 33340 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
11872 /* 33343 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
11873 /* 33346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11874 /* 33350 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11875 /* 33354 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v2i64] }:$src
11876 /* 33354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
11877 /* 33357 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
11878 /* 33359 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11879 /* 33361 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
11880 /* 33366 */ // GIR_Coverage, 3127,
11881 /* 33366 */ GIR_EraseRootFromParent_Done,
11882 /* 33367 */ // Label 723: @33367
11883 /* 33367 */ GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(33404), // Rule ID 3190 //
11884 /* 33372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11885 /* 33375 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11886 /* 33378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11887 /* 33382 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11888 /* 33386 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4f32] }:$src)
11889 /* 33386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
11890 /* 33389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11891 /* 33391 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11892 /* 33393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11893 /* 33396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11894 /* 33402 */ GIR_RootConstrainSelectedInstOperands,
11895 /* 33403 */ // GIR_Coverage, 3190,
11896 /* 33403 */ GIR_EraseRootFromParent_Done,
11897 /* 33404 */ // Label 724: @33404
11898 /* 33404 */ GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(33441), // Rule ID 3191 //
11899 /* 33409 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11900 /* 33412 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11901 /* 33415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11902 /* 33419 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11903 /* 33423 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2f64] } QPR:{ *:[v4i32] }:$src)
11904 /* 33423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
11905 /* 33426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11906 /* 33428 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11907 /* 33430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11908 /* 33433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11909 /* 33439 */ GIR_RootConstrainSelectedInstOperands,
11910 /* 33440 */ // GIR_Coverage, 3191,
11911 /* 33440 */ GIR_EraseRootFromParent_Done,
11912 /* 33441 */ // Label 725: @33441
11913 /* 33441 */ GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(33478), // Rule ID 3192 //
11914 /* 33446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11915 /* 33449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11916 /* 33452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11917 /* 33456 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11918 /* 33460 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8f16] }:$src)
11919 /* 33460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
11920 /* 33463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11921 /* 33465 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11922 /* 33467 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11923 /* 33470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11924 /* 33476 */ GIR_RootConstrainSelectedInstOperands,
11925 /* 33477 */ // GIR_Coverage, 3192,
11926 /* 33477 */ GIR_EraseRootFromParent_Done,
11927 /* 33478 */ // Label 726: @33478
11928 /* 33478 */ GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(33515), // Rule ID 3193 //
11929 /* 33483 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11930 /* 33486 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11931 /* 33489 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11932 /* 33493 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11933 /* 33497 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2f64] } QPR:{ *:[v8i16] }:$src)
11934 /* 33497 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
11935 /* 33500 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11936 /* 33502 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11937 /* 33504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11938 /* 33507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11939 /* 33513 */ GIR_RootConstrainSelectedInstOperands,
11940 /* 33514 */ // GIR_Coverage, 3193,
11941 /* 33514 */ GIR_EraseRootFromParent_Done,
11942 /* 33515 */ // Label 727: @33515
11943 /* 33515 */ GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(33552), // Rule ID 3194 //
11944 /* 33520 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11945 /* 33523 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
11946 /* 33526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11947 /* 33530 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11948 /* 33534 */ // (bitconvert:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2f64] } QPR:{ *:[v16i8] }:$src)
11949 /* 33534 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
11950 /* 33537 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11951 /* 33539 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11952 /* 33541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11953 /* 33544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11954 /* 33550 */ GIR_RootConstrainSelectedInstOperands,
11955 /* 33551 */ // GIR_Coverage, 3194,
11956 /* 33551 */ GIR_EraseRootFromParent_Done,
11957 /* 33552 */ // Label 728: @33552
11958 /* 33552 */ GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(33589), // Rule ID 3195 //
11959 /* 33557 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11960 /* 33560 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11961 /* 33563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11962 /* 33567 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11963 /* 33571 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4f32] }:$src)
11964 /* 33571 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
11965 /* 33574 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11966 /* 33576 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11967 /* 33578 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11968 /* 33581 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11969 /* 33587 */ GIR_RootConstrainSelectedInstOperands,
11970 /* 33588 */ // GIR_Coverage, 3195,
11971 /* 33588 */ GIR_EraseRootFromParent_Done,
11972 /* 33589 */ // Label 729: @33589
11973 /* 33589 */ GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(33626), // Rule ID 3196 //
11974 /* 33594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11975 /* 33597 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
11976 /* 33600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11977 /* 33604 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11978 /* 33608 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src) => (VREV64q32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$src)
11979 /* 33608 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
11980 /* 33611 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11981 /* 33613 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11982 /* 33615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11983 /* 33618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11984 /* 33624 */ GIR_RootConstrainSelectedInstOperands,
11985 /* 33625 */ // GIR_Coverage, 3196,
11986 /* 33625 */ GIR_EraseRootFromParent_Done,
11987 /* 33626 */ // Label 730: @33626
11988 /* 33626 */ GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(33663), // Rule ID 3197 //
11989 /* 33631 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
11990 /* 33634 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
11991 /* 33637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11992 /* 33641 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
11993 /* 33645 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8f16] }:$src)
11994 /* 33645 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
11995 /* 33648 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
11996 /* 33650 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
11997 /* 33652 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
11998 /* 33655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
11999 /* 33661 */ GIR_RootConstrainSelectedInstOperands,
12000 /* 33662 */ // GIR_Coverage, 3197,
12001 /* 33662 */ GIR_EraseRootFromParent_Done,
12002 /* 33663 */ // Label 731: @33663
12003 /* 33663 */ GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(33700), // Rule ID 3198 //
12004 /* 33668 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12005 /* 33671 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12006 /* 33674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12007 /* 33678 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12008 /* 33682 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src) => (VREV64q16:{ *:[v2i64] } QPR:{ *:[v8i16] }:$src)
12009 /* 33682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
12010 /* 33685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12011 /* 33687 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12012 /* 33689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12013 /* 33692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12014 /* 33698 */ GIR_RootConstrainSelectedInstOperands,
12015 /* 33699 */ // GIR_Coverage, 3198,
12016 /* 33699 */ GIR_EraseRootFromParent_Done,
12017 /* 33700 */ // Label 732: @33700
12018 /* 33700 */ GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(33737), // Rule ID 3199 //
12019 /* 33705 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12020 /* 33708 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12021 /* 33711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12022 /* 33715 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12023 /* 33719 */ // (bitconvert:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src) => (VREV64q8:{ *:[v2i64] } QPR:{ *:[v16i8] }:$src)
12024 /* 33719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
12025 /* 33722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12026 /* 33724 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12027 /* 33726 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12028 /* 33729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12029 /* 33735 */ GIR_RootConstrainSelectedInstOperands,
12030 /* 33736 */ // GIR_Coverage, 3199,
12031 /* 33736 */ GIR_EraseRootFromParent_Done,
12032 /* 33737 */ // Label 733: @33737
12033 /* 33737 */ GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(33769), // Rule ID 5761 //
12034 /* 33742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
12035 /* 33745 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12036 /* 33748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12037 /* 33752 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12038 /* 33756 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v2f64] }:$src
12039 /* 33756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12040 /* 33759 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12041 /* 33761 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12042 /* 33763 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12043 /* 33768 */ // GIR_Coverage, 5761,
12044 /* 33768 */ GIR_EraseRootFromParent_Done,
12045 /* 33769 */ // Label 734: @33769
12046 /* 33769 */ GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(33801), // Rule ID 5762 //
12047 /* 33774 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
12048 /* 33777 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12049 /* 33780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12050 /* 33784 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12051 /* 33788 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v2i64] }:$src
12052 /* 33788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12053 /* 33791 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12054 /* 33793 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12055 /* 33795 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12056 /* 33800 */ // GIR_Coverage, 5762,
12057 /* 33800 */ GIR_EraseRootFromParent_Done,
12058 /* 33801 */ // Label 735: @33801
12059 /* 33801 */ GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(33833), // Rule ID 5767 //
12060 /* 33806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12061 /* 33809 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12062 /* 33812 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12063 /* 33816 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12064 /* 33820 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2f64] }:$src
12065 /* 33820 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12066 /* 33823 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12067 /* 33825 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12068 /* 33827 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12069 /* 33832 */ // GIR_Coverage, 5767,
12070 /* 33832 */ GIR_EraseRootFromParent_Done,
12071 /* 33833 */ // Label 736: @33833
12072 /* 33833 */ GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(33865), // Rule ID 5768 //
12073 /* 33838 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12074 /* 33841 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12075 /* 33844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12076 /* 33848 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12077 /* 33852 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2f64] }:$src
12078 /* 33852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12079 /* 33855 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12080 /* 33857 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12081 /* 33859 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12082 /* 33864 */ // GIR_Coverage, 5768,
12083 /* 33864 */ GIR_EraseRootFromParent_Done,
12084 /* 33865 */ // Label 737: @33865
12085 /* 33865 */ GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(33897), // Rule ID 5769 //
12086 /* 33870 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12087 /* 33873 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12088 /* 33876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12089 /* 33880 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12090 /* 33884 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2f64] }:$src
12091 /* 33884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12092 /* 33887 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12093 /* 33889 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12094 /* 33891 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12095 /* 33896 */ // GIR_Coverage, 5769,
12096 /* 33896 */ GIR_EraseRootFromParent_Done,
12097 /* 33897 */ // Label 738: @33897
12098 /* 33897 */ GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(33929), // Rule ID 5770 //
12099 /* 33902 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12100 /* 33905 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12101 /* 33908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12102 /* 33912 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12103 /* 33916 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2f64] }:$src
12104 /* 33916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12105 /* 33919 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12106 /* 33921 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12107 /* 33923 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12108 /* 33928 */ // GIR_Coverage, 5770,
12109 /* 33928 */ GIR_EraseRootFromParent_Done,
12110 /* 33929 */ // Label 739: @33929
12111 /* 33929 */ GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(33961), // Rule ID 5771 //
12112 /* 33934 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12113 /* 33937 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12114 /* 33940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12115 /* 33944 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12116 /* 33948 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2f64] }:$src
12117 /* 33948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12118 /* 33951 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12119 /* 33953 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12120 /* 33955 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12121 /* 33960 */ // GIR_Coverage, 5771,
12122 /* 33960 */ GIR_EraseRootFromParent_Done,
12123 /* 33961 */ // Label 740: @33961
12124 /* 33961 */ GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(33993), // Rule ID 5772 //
12125 /* 33966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12126 /* 33969 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12127 /* 33972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12128 /* 33976 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12129 /* 33980 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v2i64] }:$src
12130 /* 33980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12131 /* 33983 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12132 /* 33985 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12133 /* 33987 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12134 /* 33992 */ // GIR_Coverage, 5772,
12135 /* 33992 */ GIR_EraseRootFromParent_Done,
12136 /* 33993 */ // Label 741: @33993
12137 /* 33993 */ GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(34025), // Rule ID 5773 //
12138 /* 33998 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12139 /* 34001 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12140 /* 34004 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12141 /* 34008 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12142 /* 34012 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v2i64] }:$src
12143 /* 34012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12144 /* 34015 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12145 /* 34017 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12146 /* 34019 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12147 /* 34024 */ // GIR_Coverage, 5773,
12148 /* 34024 */ GIR_EraseRootFromParent_Done,
12149 /* 34025 */ // Label 742: @34025
12150 /* 34025 */ GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(34057), // Rule ID 5774 //
12151 /* 34030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12152 /* 34033 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12153 /* 34036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12154 /* 34040 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12155 /* 34044 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v2i64] }:$src
12156 /* 34044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12157 /* 34047 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12158 /* 34049 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12159 /* 34051 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12160 /* 34056 */ // GIR_Coverage, 5774,
12161 /* 34056 */ GIR_EraseRootFromParent_Done,
12162 /* 34057 */ // Label 743: @34057
12163 /* 34057 */ GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(34089), // Rule ID 5775 //
12164 /* 34062 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12165 /* 34065 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12166 /* 34068 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12167 /* 34072 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12168 /* 34076 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v2i64] }:$src
12169 /* 34076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12170 /* 34079 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12171 /* 34081 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12172 /* 34083 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12173 /* 34088 */ // GIR_Coverage, 5775,
12174 /* 34088 */ GIR_EraseRootFromParent_Done,
12175 /* 34089 */ // Label 744: @34089
12176 /* 34089 */ GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(34121), // Rule ID 5776 //
12177 /* 34094 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
12178 /* 34097 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12179 /* 34100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12180 /* 34104 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12181 /* 34108 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v2i64] }:$src
12182 /* 34108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12183 /* 34111 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12184 /* 34113 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12185 /* 34115 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
12186 /* 34120 */ // GIR_Coverage, 5776,
12187 /* 34120 */ GIR_EraseRootFromParent_Done,
12188 /* 34121 */ // Label 745: @34121
12189 /* 34121 */ GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(34179), // Rule ID 5803 //
12190 /* 34126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12191 /* 34129 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12192 /* 34132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12193 /* 34136 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12194 /* 34140 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4f32] }:$src)
12195 /* 34140 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12196 /* 34143 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12197 /* 34147 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12198 /* 34152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
12199 /* 34155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12200 /* 34157 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12201 /* 34159 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12202 /* 34162 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12203 /* 34168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12204 /* 34174 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12205 /* 34177 */ GIR_RootConstrainSelectedInstOperands,
12206 /* 34178 */ // GIR_Coverage, 5803,
12207 /* 34178 */ GIR_EraseRootFromParent_Done,
12208 /* 34179 */ // Label 746: @34179
12209 /* 34179 */ GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(34237), // Rule ID 5804 //
12210 /* 34184 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12211 /* 34187 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12212 /* 34190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12213 /* 34194 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12214 /* 34198 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2f64] } MQPR:{ *:[v4i32] }:$src)
12215 /* 34198 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12216 /* 34201 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12217 /* 34205 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12218 /* 34210 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
12219 /* 34213 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12220 /* 34215 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12221 /* 34217 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12222 /* 34220 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12223 /* 34226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12224 /* 34232 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12225 /* 34235 */ GIR_RootConstrainSelectedInstOperands,
12226 /* 34236 */ // GIR_Coverage, 5804,
12227 /* 34236 */ GIR_EraseRootFromParent_Done,
12228 /* 34237 */ // Label 747: @34237
12229 /* 34237 */ GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(34295), // Rule ID 5805 //
12230 /* 34242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12231 /* 34245 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12232 /* 34248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12233 /* 34252 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12234 /* 34256 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8f16] }:$src)
12235 /* 34256 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12236 /* 34259 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12237 /* 34263 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12238 /* 34268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12239 /* 34271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12240 /* 34273 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12241 /* 34275 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12242 /* 34278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12243 /* 34284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12244 /* 34290 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12245 /* 34293 */ GIR_RootConstrainSelectedInstOperands,
12246 /* 34294 */ // GIR_Coverage, 5805,
12247 /* 34294 */ GIR_EraseRootFromParent_Done,
12248 /* 34295 */ // Label 748: @34295
12249 /* 34295 */ GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(34353), // Rule ID 5806 //
12250 /* 34300 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12251 /* 34303 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12252 /* 34306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12253 /* 34310 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12254 /* 34314 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2f64] } MQPR:{ *:[v8i16] }:$src)
12255 /* 34314 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12256 /* 34317 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12257 /* 34321 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12258 /* 34326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12259 /* 34329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12260 /* 34331 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12261 /* 34333 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12262 /* 34336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12263 /* 34342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12264 /* 34348 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12265 /* 34351 */ GIR_RootConstrainSelectedInstOperands,
12266 /* 34352 */ // GIR_Coverage, 5806,
12267 /* 34352 */ GIR_EraseRootFromParent_Done,
12268 /* 34353 */ // Label 749: @34353
12269 /* 34353 */ GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(34411), // Rule ID 5807 //
12270 /* 34358 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12271 /* 34361 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12272 /* 34364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12273 /* 34368 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12274 /* 34372 */ // (bitconvert:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2f64] } MQPR:{ *:[v16i8] }:$src)
12275 /* 34372 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12276 /* 34375 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12277 /* 34379 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12278 /* 34384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
12279 /* 34387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12280 /* 34389 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12281 /* 34391 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12282 /* 34394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12283 /* 34400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12284 /* 34406 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12285 /* 34409 */ GIR_RootConstrainSelectedInstOperands,
12286 /* 34410 */ // GIR_Coverage, 5807,
12287 /* 34410 */ GIR_EraseRootFromParent_Done,
12288 /* 34411 */ // Label 750: @34411
12289 /* 34411 */ GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(34469), // Rule ID 5808 //
12290 /* 34416 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12291 /* 34419 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12292 /* 34422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12293 /* 34426 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12294 /* 34430 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4f32] }:$src)
12295 /* 34430 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12296 /* 34433 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12297 /* 34437 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12298 /* 34442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
12299 /* 34445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12300 /* 34447 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12301 /* 34449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12302 /* 34452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12303 /* 34458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12304 /* 34464 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12305 /* 34467 */ GIR_RootConstrainSelectedInstOperands,
12306 /* 34468 */ // GIR_Coverage, 5808,
12307 /* 34468 */ GIR_EraseRootFromParent_Done,
12308 /* 34469 */ // Label 751: @34469
12309 /* 34469 */ GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(34527), // Rule ID 5809 //
12310 /* 34474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12311 /* 34477 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12312 /* 34480 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12313 /* 34484 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12314 /* 34488 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV64_32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$src)
12315 /* 34488 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12316 /* 34491 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12317 /* 34495 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12318 /* 34500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
12319 /* 34503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12320 /* 34505 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12321 /* 34507 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12322 /* 34510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12323 /* 34516 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12324 /* 34522 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12325 /* 34525 */ GIR_RootConstrainSelectedInstOperands,
12326 /* 34526 */ // GIR_Coverage, 5809,
12327 /* 34526 */ GIR_EraseRootFromParent_Done,
12328 /* 34527 */ // Label 752: @34527
12329 /* 34527 */ GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(34585), // Rule ID 5810 //
12330 /* 34532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12331 /* 34535 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12332 /* 34538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12333 /* 34542 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12334 /* 34546 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8f16] }:$src)
12335 /* 34546 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12336 /* 34549 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12337 /* 34553 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12338 /* 34558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12339 /* 34561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12340 /* 34563 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12341 /* 34565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12342 /* 34568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12343 /* 34574 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12344 /* 34580 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12345 /* 34583 */ GIR_RootConstrainSelectedInstOperands,
12346 /* 34584 */ // GIR_Coverage, 5810,
12347 /* 34584 */ GIR_EraseRootFromParent_Done,
12348 /* 34585 */ // Label 753: @34585
12349 /* 34585 */ GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(34643), // Rule ID 5811 //
12350 /* 34590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12351 /* 34593 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12352 /* 34596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12353 /* 34600 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12354 /* 34604 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV64_16:{ *:[v2i64] } MQPR:{ *:[v8i16] }:$src)
12355 /* 34604 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12356 /* 34607 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12357 /* 34611 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12358 /* 34616 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
12359 /* 34619 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12360 /* 34621 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12361 /* 34623 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12362 /* 34626 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12363 /* 34632 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12364 /* 34638 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12365 /* 34641 */ GIR_RootConstrainSelectedInstOperands,
12366 /* 34642 */ // GIR_Coverage, 5811,
12367 /* 34642 */ GIR_EraseRootFromParent_Done,
12368 /* 34643 */ // Label 754: @34643
12369 /* 34643 */ GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(34701), // Rule ID 5812 //
12370 /* 34648 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
12371 /* 34651 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12372 /* 34654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12373 /* 34658 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
12374 /* 34662 */ // (bitconvert:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV64_8:{ *:[v2i64] } MQPR:{ *:[v16i8] }:$src)
12375 /* 34662 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
12376 /* 34665 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
12377 /* 34669 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
12378 /* 34674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
12379 /* 34677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
12380 /* 34679 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12381 /* 34681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
12382 /* 34684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12383 /* 34690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12384 /* 34696 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
12385 /* 34699 */ GIR_RootConstrainSelectedInstOperands,
12386 /* 34700 */ // GIR_Coverage, 5812,
12387 /* 34700 */ GIR_EraseRootFromParent_Done,
12388 /* 34701 */ // Label 755: @34701
12389 /* 34701 */ GIM_Reject,
12390 /* 34702 */ // Label 658: @34702
12391 /* 34702 */ GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(34734), // Rule ID 3074 //
12392 /* 34707 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12393 /* 34710 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
12394 /* 34713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12395 /* 34717 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12396 /* 34721 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v4i16] }:$src
12397 /* 34721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12398 /* 34724 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12399 /* 34726 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12400 /* 34728 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12401 /* 34733 */ // GIR_Coverage, 3074,
12402 /* 34733 */ GIR_EraseRootFromParent_Done,
12403 /* 34734 */ // Label 756: @34734
12404 /* 34734 */ GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(34766), // Rule ID 3075 //
12405 /* 34739 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12406 /* 34742 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
12407 /* 34745 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12408 /* 34749 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12409 /* 34753 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v4f16] }:$src
12410 /* 34753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12411 /* 34756 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12412 /* 34758 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12413 /* 34760 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12414 /* 34765 */ // GIR_Coverage, 3075,
12415 /* 34765 */ GIR_EraseRootFromParent_Done,
12416 /* 34766 */ // Label 757: @34766
12417 /* 34766 */ GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(34798), // Rule ID 3102 //
12418 /* 34771 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12419 /* 34774 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12420 /* 34777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12421 /* 34781 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12422 /* 34785 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4f16] }:$src
12423 /* 34785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12424 /* 34788 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12425 /* 34790 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12426 /* 34792 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12427 /* 34797 */ // GIR_Coverage, 3102,
12428 /* 34797 */ GIR_EraseRootFromParent_Done,
12429 /* 34798 */ // Label 758: @34798
12430 /* 34798 */ GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(34830), // Rule ID 3103 //
12431 /* 34803 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12432 /* 34806 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12433 /* 34809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12434 /* 34813 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12435 /* 34817 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4f16] }:$src
12436 /* 34817 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12437 /* 34820 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12438 /* 34822 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12439 /* 34824 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12440 /* 34829 */ // GIR_Coverage, 3103,
12441 /* 34829 */ GIR_EraseRootFromParent_Done,
12442 /* 34830 */ // Label 759: @34830
12443 /* 34830 */ GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(34862), // Rule ID 3104 //
12444 /* 34835 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12445 /* 34838 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12446 /* 34841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12447 /* 34845 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12448 /* 34849 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4f16] }:$src
12449 /* 34849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12450 /* 34852 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12451 /* 34854 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12452 /* 34856 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12453 /* 34861 */ // GIR_Coverage, 3104,
12454 /* 34861 */ GIR_EraseRootFromParent_Done,
12455 /* 34862 */ // Label 760: @34862
12456 /* 34862 */ GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(34894), // Rule ID 3105 //
12457 /* 34867 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12458 /* 34870 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12459 /* 34873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12460 /* 34877 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12461 /* 34881 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4f16] }:$src
12462 /* 34881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12463 /* 34884 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12464 /* 34886 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12465 /* 34888 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12466 /* 34893 */ // GIR_Coverage, 3105,
12467 /* 34893 */ GIR_EraseRootFromParent_Done,
12468 /* 34894 */ // Label 761: @34894
12469 /* 34894 */ GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(34926), // Rule ID 3106 //
12470 /* 34899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12471 /* 34902 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
12472 /* 34905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12473 /* 34909 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12474 /* 34913 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4f16] }:$src
12475 /* 34913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12476 /* 34916 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12477 /* 34918 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12478 /* 34920 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12479 /* 34925 */ // GIR_Coverage, 3106,
12480 /* 34925 */ GIR_EraseRootFromParent_Done,
12481 /* 34926 */ // Label 762: @34926
12482 /* 34926 */ GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(34958), // Rule ID 3107 //
12483 /* 34931 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12484 /* 34934 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12485 /* 34937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12486 /* 34941 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12487 /* 34945 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v4i16] }:$src
12488 /* 34945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12489 /* 34948 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12490 /* 34950 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12491 /* 34952 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12492 /* 34957 */ // GIR_Coverage, 3107,
12493 /* 34957 */ GIR_EraseRootFromParent_Done,
12494 /* 34958 */ // Label 763: @34958
12495 /* 34958 */ GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(34990), // Rule ID 3108 //
12496 /* 34963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12497 /* 34966 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12498 /* 34969 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12499 /* 34973 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12500 /* 34977 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v4i16] }:$src
12501 /* 34977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12502 /* 34980 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12503 /* 34982 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12504 /* 34984 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12505 /* 34989 */ // GIR_Coverage, 3108,
12506 /* 34989 */ GIR_EraseRootFromParent_Done,
12507 /* 34990 */ // Label 764: @34990
12508 /* 34990 */ GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(35022), // Rule ID 3109 //
12509 /* 34995 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12510 /* 34998 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12511 /* 35001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12512 /* 35005 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12513 /* 35009 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v4i16] }:$src
12514 /* 35009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12515 /* 35012 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12516 /* 35014 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12517 /* 35016 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12518 /* 35021 */ // GIR_Coverage, 3109,
12519 /* 35021 */ GIR_EraseRootFromParent_Done,
12520 /* 35022 */ // Label 765: @35022
12521 /* 35022 */ GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(35054), // Rule ID 3110 //
12522 /* 35027 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12523 /* 35030 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12524 /* 35033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12525 /* 35037 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12526 /* 35041 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v4i16] }:$src
12527 /* 35041 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12528 /* 35044 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12529 /* 35046 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12530 /* 35048 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12531 /* 35053 */ // GIR_Coverage, 3110,
12532 /* 35053 */ GIR_EraseRootFromParent_Done,
12533 /* 35054 */ // Label 766: @35054
12534 /* 35054 */ GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(35086), // Rule ID 3111 //
12535 /* 35059 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12536 /* 35062 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
12537 /* 35065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12538 /* 35069 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12539 /* 35073 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => DPR:{ *:[v4i16] }:$src
12540 /* 35073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12541 /* 35076 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12542 /* 35078 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12543 /* 35080 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
12544 /* 35085 */ // GIR_Coverage, 3111,
12545 /* 35085 */ GIR_EraseRootFromParent_Done,
12546 /* 35086 */ // Label 767: @35086
12547 /* 35086 */ GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(35123), // Rule ID 3174 //
12548 /* 35091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12549 /* 35094 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12550 /* 35097 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12551 /* 35101 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12552 /* 35105 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[f64] }:$src)
12553 /* 35105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
12554 /* 35108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12555 /* 35110 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12556 /* 35112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12557 /* 35115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12558 /* 35121 */ GIR_RootConstrainSelectedInstOperands,
12559 /* 35122 */ // GIR_Coverage, 3174,
12560 /* 35122 */ GIR_EraseRootFromParent_Done,
12561 /* 35123 */ // Label 768: @35123
12562 /* 35123 */ GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(35160), // Rule ID 3175 //
12563 /* 35128 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12564 /* 35131 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12565 /* 35134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12566 /* 35138 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12567 /* 35142 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4f16] } DPR:{ *:[v1i64] }:$src)
12568 /* 35142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
12569 /* 35145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12570 /* 35147 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12571 /* 35149 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12572 /* 35152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12573 /* 35158 */ GIR_RootConstrainSelectedInstOperands,
12574 /* 35159 */ // GIR_Coverage, 3175,
12575 /* 35159 */ GIR_EraseRootFromParent_Done,
12576 /* 35160 */ // Label 769: @35160
12577 /* 35160 */ GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(35197), // Rule ID 3176 //
12578 /* 35165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12579 /* 35168 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12580 /* 35171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12581 /* 35175 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12582 /* 35179 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2f32] }:$src)
12583 /* 35179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12584 /* 35182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12585 /* 35184 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12586 /* 35186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12587 /* 35189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12588 /* 35195 */ GIR_RootConstrainSelectedInstOperands,
12589 /* 35196 */ // GIR_Coverage, 3176,
12590 /* 35196 */ GIR_EraseRootFromParent_Done,
12591 /* 35197 */ // Label 770: @35197
12592 /* 35197 */ GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(35234), // Rule ID 3177 //
12593 /* 35202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12594 /* 35205 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12595 /* 35208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12596 /* 35212 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12597 /* 35216 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4f16] } DPR:{ *:[v2i32] }:$src)
12598 /* 35216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12599 /* 35219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12600 /* 35221 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12601 /* 35223 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12602 /* 35226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12603 /* 35232 */ GIR_RootConstrainSelectedInstOperands,
12604 /* 35233 */ // GIR_Coverage, 3177,
12605 /* 35233 */ GIR_EraseRootFromParent_Done,
12606 /* 35234 */ // Label 771: @35234
12607 /* 35234 */ GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(35271), // Rule ID 3178 //
12608 /* 35239 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12609 /* 35242 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
12610 /* 35245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12611 /* 35249 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12612 /* 35253 */ // (bitconvert:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4f16] } DPR:{ *:[v8i8] }:$src)
12613 /* 35253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
12614 /* 35256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12615 /* 35258 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12616 /* 35260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12617 /* 35263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12618 /* 35269 */ GIR_RootConstrainSelectedInstOperands,
12619 /* 35270 */ // GIR_Coverage, 3178,
12620 /* 35270 */ GIR_EraseRootFromParent_Done,
12621 /* 35271 */ // Label 772: @35271
12622 /* 35271 */ GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(35308), // Rule ID 3179 //
12623 /* 35276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12624 /* 35279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12625 /* 35282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12626 /* 35286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12627 /* 35290 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[f64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[f64] }:$src)
12628 /* 35290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
12629 /* 35293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12630 /* 35295 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12631 /* 35297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12632 /* 35300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12633 /* 35306 */ GIR_RootConstrainSelectedInstOperands,
12634 /* 35307 */ // GIR_Coverage, 3179,
12635 /* 35307 */ GIR_EraseRootFromParent_Done,
12636 /* 35308 */ // Label 773: @35308
12637 /* 35308 */ GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(35345), // Rule ID 3180 //
12638 /* 35313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12639 /* 35316 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
12640 /* 35319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12641 /* 35323 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12642 /* 35327 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src) => (VREV64d16:{ *:[v4i16] } DPR:{ *:[v1i64] }:$src)
12643 /* 35327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d16),
12644 /* 35330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12645 /* 35332 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12646 /* 35334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12647 /* 35337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12648 /* 35343 */ GIR_RootConstrainSelectedInstOperands,
12649 /* 35344 */ // GIR_Coverage, 3180,
12650 /* 35344 */ GIR_EraseRootFromParent_Done,
12651 /* 35345 */ // Label 774: @35345
12652 /* 35345 */ GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(35382), // Rule ID 3181 //
12653 /* 35350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12654 /* 35353 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12655 /* 35356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12656 /* 35360 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12657 /* 35364 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2f32] }:$src)
12658 /* 35364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12659 /* 35367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12660 /* 35369 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12661 /* 35371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12662 /* 35374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12663 /* 35380 */ GIR_RootConstrainSelectedInstOperands,
12664 /* 35381 */ // GIR_Coverage, 3181,
12665 /* 35381 */ GIR_EraseRootFromParent_Done,
12666 /* 35382 */ // Label 775: @35382
12667 /* 35382 */ GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(35419), // Rule ID 3182 //
12668 /* 35387 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12669 /* 35390 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
12670 /* 35393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12671 /* 35397 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12672 /* 35401 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src) => (VREV32d16:{ *:[v4i16] } DPR:{ *:[v2i32] }:$src)
12673 /* 35401 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d16),
12674 /* 35404 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12675 /* 35406 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12676 /* 35408 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12677 /* 35411 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12678 /* 35417 */ GIR_RootConstrainSelectedInstOperands,
12679 /* 35418 */ // GIR_Coverage, 3182,
12680 /* 35418 */ GIR_EraseRootFromParent_Done,
12681 /* 35419 */ // Label 776: @35419
12682 /* 35419 */ GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(35456), // Rule ID 3183 //
12683 /* 35424 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12684 /* 35427 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
12685 /* 35430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12686 /* 35434 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
12687 /* 35438 */ // (bitconvert:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src) => (VREV16d8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$src)
12688 /* 35438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
12689 /* 35441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12690 /* 35443 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12691 /* 35445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12692 /* 35448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12693 /* 35454 */ GIR_RootConstrainSelectedInstOperands,
12694 /* 35455 */ // GIR_Coverage, 3183,
12695 /* 35455 */ GIR_EraseRootFromParent_Done,
12696 /* 35456 */ // Label 777: @35456
12697 /* 35456 */ GIM_Reject,
12698 /* 35457 */ // Label 659: @35457
12699 /* 35457 */ GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(35489), // Rule ID 3078 //
12700 /* 35462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12701 /* 35465 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12702 /* 35468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12703 /* 35472 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12704 /* 35476 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v4i32] }:$src
12705 /* 35476 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12706 /* 35479 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12707 /* 35481 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12708 /* 35483 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12709 /* 35488 */ // GIR_Coverage, 3078,
12710 /* 35488 */ GIR_EraseRootFromParent_Done,
12711 /* 35489 */ // Label 778: @35489
12712 /* 35489 */ GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(35521), // Rule ID 3079 //
12713 /* 35494 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
12714 /* 35497 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
12715 /* 35500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12716 /* 35504 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12717 /* 35508 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v4f32] }:$src
12718 /* 35508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12719 /* 35511 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12720 /* 35513 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12721 /* 35515 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12722 /* 35520 */ // GIR_Coverage, 3079,
12723 /* 35520 */ GIR_EraseRootFromParent_Done,
12724 /* 35521 */ // Label 779: @35521
12725 /* 35521 */ GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(35553), // Rule ID 3128 //
12726 /* 35526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12727 /* 35529 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12728 /* 35532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12729 /* 35536 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12730 /* 35540 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4f32] }:$src
12731 /* 35540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12732 /* 35543 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12733 /* 35545 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12734 /* 35547 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12735 /* 35552 */ // GIR_Coverage, 3128,
12736 /* 35552 */ GIR_EraseRootFromParent_Done,
12737 /* 35553 */ // Label 780: @35553
12738 /* 35553 */ GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(35585), // Rule ID 3129 //
12739 /* 35558 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12740 /* 35561 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12741 /* 35564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12742 /* 35568 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12743 /* 35572 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4f32] }:$src
12744 /* 35572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12745 /* 35575 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12746 /* 35577 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12747 /* 35579 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12748 /* 35584 */ // GIR_Coverage, 3129,
12749 /* 35584 */ GIR_EraseRootFromParent_Done,
12750 /* 35585 */ // Label 781: @35585
12751 /* 35585 */ GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(35617), // Rule ID 3130 //
12752 /* 35590 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12753 /* 35593 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12754 /* 35596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12755 /* 35600 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12756 /* 35604 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4f32] }:$src
12757 /* 35604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12758 /* 35607 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12759 /* 35609 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12760 /* 35611 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12761 /* 35616 */ // GIR_Coverage, 3130,
12762 /* 35616 */ GIR_EraseRootFromParent_Done,
12763 /* 35617 */ // Label 782: @35617
12764 /* 35617 */ GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(35649), // Rule ID 3131 //
12765 /* 35622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12766 /* 35625 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12767 /* 35628 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12768 /* 35632 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12769 /* 35636 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4f32] }:$src
12770 /* 35636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12771 /* 35639 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12772 /* 35641 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12773 /* 35643 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12774 /* 35648 */ // GIR_Coverage, 3131,
12775 /* 35648 */ GIR_EraseRootFromParent_Done,
12776 /* 35649 */ // Label 783: @35649
12777 /* 35649 */ GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(35681), // Rule ID 3132 //
12778 /* 35654 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12779 /* 35657 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12780 /* 35660 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12781 /* 35664 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12782 /* 35668 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4f32] }:$src
12783 /* 35668 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12784 /* 35671 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12785 /* 35673 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12786 /* 35675 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12787 /* 35680 */ // GIR_Coverage, 3132,
12788 /* 35680 */ GIR_EraseRootFromParent_Done,
12789 /* 35681 */ // Label 784: @35681
12790 /* 35681 */ GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(35713), // Rule ID 3133 //
12791 /* 35686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12792 /* 35689 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12793 /* 35692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12794 /* 35696 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12795 /* 35700 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v4i32] }:$src
12796 /* 35700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12797 /* 35703 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12798 /* 35705 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12799 /* 35707 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12800 /* 35712 */ // GIR_Coverage, 3133,
12801 /* 35712 */ GIR_EraseRootFromParent_Done,
12802 /* 35713 */ // Label 785: @35713
12803 /* 35713 */ GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(35745), // Rule ID 3134 //
12804 /* 35718 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12805 /* 35721 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12806 /* 35724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12807 /* 35728 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12808 /* 35732 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v4i32] }:$src
12809 /* 35732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12810 /* 35735 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12811 /* 35737 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12812 /* 35739 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12813 /* 35744 */ // GIR_Coverage, 3134,
12814 /* 35744 */ GIR_EraseRootFromParent_Done,
12815 /* 35745 */ // Label 786: @35745
12816 /* 35745 */ GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(35777), // Rule ID 3135 //
12817 /* 35750 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12818 /* 35753 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12819 /* 35756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12820 /* 35760 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12821 /* 35764 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v4i32] }:$src
12822 /* 35764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12823 /* 35767 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12824 /* 35769 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12825 /* 35771 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12826 /* 35776 */ // GIR_Coverage, 3135,
12827 /* 35776 */ GIR_EraseRootFromParent_Done,
12828 /* 35777 */ // Label 787: @35777
12829 /* 35777 */ GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(35809), // Rule ID 3136 //
12830 /* 35782 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12831 /* 35785 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12832 /* 35788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12833 /* 35792 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12834 /* 35796 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v4i32] }:$src
12835 /* 35796 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12836 /* 35799 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12837 /* 35801 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12838 /* 35803 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12839 /* 35808 */ // GIR_Coverage, 3136,
12840 /* 35808 */ GIR_EraseRootFromParent_Done,
12841 /* 35809 */ // Label 788: @35809
12842 /* 35809 */ GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(35841), // Rule ID 3137 //
12843 /* 35814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
12844 /* 35817 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12845 /* 35820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12846 /* 35824 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12847 /* 35828 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v4i32] }:$src
12848 /* 35828 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
12849 /* 35831 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
12850 /* 35833 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12851 /* 35835 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
12852 /* 35840 */ // GIR_Coverage, 3137,
12853 /* 35840 */ GIR_EraseRootFromParent_Done,
12854 /* 35841 */ // Label 789: @35841
12855 /* 35841 */ GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(35878), // Rule ID 3200 //
12856 /* 35846 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12857 /* 35849 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12858 /* 35852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12859 /* 35856 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12860 /* 35860 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2f64] }:$src)
12861 /* 35860 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
12862 /* 35863 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12863 /* 35865 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12864 /* 35867 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12865 /* 35870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12866 /* 35876 */ GIR_RootConstrainSelectedInstOperands,
12867 /* 35877 */ // GIR_Coverage, 3200,
12868 /* 35877 */ GIR_EraseRootFromParent_Done,
12869 /* 35878 */ // Label 790: @35878
12870 /* 35878 */ GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(35915), // Rule ID 3201 //
12871 /* 35883 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12872 /* 35886 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12873 /* 35889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12874 /* 35893 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12875 /* 35897 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4f32] } QPR:{ *:[v2i64] }:$src)
12876 /* 35897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
12877 /* 35900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12878 /* 35902 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12879 /* 35904 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12880 /* 35907 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12881 /* 35913 */ GIR_RootConstrainSelectedInstOperands,
12882 /* 35914 */ // GIR_Coverage, 3201,
12883 /* 35914 */ GIR_EraseRootFromParent_Done,
12884 /* 35915 */ // Label 791: @35915
12885 /* 35915 */ GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(35952), // Rule ID 3202 //
12886 /* 35920 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12887 /* 35923 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12888 /* 35926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12889 /* 35930 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12890 /* 35934 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8f16] }:$src)
12891 /* 35934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12892 /* 35937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12893 /* 35939 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12894 /* 35941 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12895 /* 35944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12896 /* 35950 */ GIR_RootConstrainSelectedInstOperands,
12897 /* 35951 */ // GIR_Coverage, 3202,
12898 /* 35951 */ GIR_EraseRootFromParent_Done,
12899 /* 35952 */ // Label 792: @35952
12900 /* 35952 */ GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(35989), // Rule ID 3203 //
12901 /* 35957 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12902 /* 35960 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12903 /* 35963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12904 /* 35967 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12905 /* 35971 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4f32] } QPR:{ *:[v8i16] }:$src)
12906 /* 35971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12907 /* 35974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12908 /* 35976 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12909 /* 35978 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12910 /* 35981 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12911 /* 35987 */ GIR_RootConstrainSelectedInstOperands,
12912 /* 35988 */ // GIR_Coverage, 3203,
12913 /* 35988 */ GIR_EraseRootFromParent_Done,
12914 /* 35989 */ // Label 793: @35989
12915 /* 35989 */ GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(36026), // Rule ID 3204 //
12916 /* 35994 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12917 /* 35997 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12918 /* 36000 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12919 /* 36004 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12920 /* 36008 */ // (bitconvert:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4f32] } QPR:{ *:[v16i8] }:$src)
12921 /* 36008 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
12922 /* 36011 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12923 /* 36013 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12924 /* 36015 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12925 /* 36018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12926 /* 36024 */ GIR_RootConstrainSelectedInstOperands,
12927 /* 36025 */ // GIR_Coverage, 3204,
12928 /* 36025 */ GIR_EraseRootFromParent_Done,
12929 /* 36026 */ // Label 794: @36026
12930 /* 36026 */ GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(36063), // Rule ID 3205 //
12931 /* 36031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12932 /* 36034 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12933 /* 36037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12934 /* 36041 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12935 /* 36045 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2f64] }:$src)
12936 /* 36045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
12937 /* 36048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12938 /* 36050 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12939 /* 36052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12940 /* 36055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12941 /* 36061 */ GIR_RootConstrainSelectedInstOperands,
12942 /* 36062 */ // GIR_Coverage, 3205,
12943 /* 36062 */ GIR_EraseRootFromParent_Done,
12944 /* 36063 */ // Label 795: @36063
12945 /* 36063 */ GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(36100), // Rule ID 3206 //
12946 /* 36068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12947 /* 36071 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
12948 /* 36074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12949 /* 36078 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12950 /* 36082 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src) => (VREV64q32:{ *:[v4i32] } QPR:{ *:[v2i64] }:$src)
12951 /* 36082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q32),
12952 /* 36085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12953 /* 36087 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12954 /* 36089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12955 /* 36092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12956 /* 36098 */ GIR_RootConstrainSelectedInstOperands,
12957 /* 36099 */ // GIR_Coverage, 3206,
12958 /* 36099 */ GIR_EraseRootFromParent_Done,
12959 /* 36100 */ // Label 796: @36100
12960 /* 36100 */ GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(36137), // Rule ID 3207 //
12961 /* 36105 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12962 /* 36108 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12963 /* 36111 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12964 /* 36115 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12965 /* 36119 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8f16] }:$src)
12966 /* 36119 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12967 /* 36122 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12968 /* 36124 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12969 /* 36126 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12970 /* 36129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12971 /* 36135 */ GIR_RootConstrainSelectedInstOperands,
12972 /* 36136 */ // GIR_Coverage, 3207,
12973 /* 36136 */ GIR_EraseRootFromParent_Done,
12974 /* 36137 */ // Label 797: @36137
12975 /* 36137 */ GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(36174), // Rule ID 3208 //
12976 /* 36142 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12977 /* 36145 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
12978 /* 36148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12979 /* 36152 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12980 /* 36156 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src) => (VREV32q16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$src)
12981 /* 36156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
12982 /* 36159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12983 /* 36161 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12984 /* 36163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
12985 /* 36166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
12986 /* 36172 */ GIR_RootConstrainSelectedInstOperands,
12987 /* 36173 */ // GIR_Coverage, 3208,
12988 /* 36173 */ GIR_EraseRootFromParent_Done,
12989 /* 36174 */ // Label 798: @36174
12990 /* 36174 */ GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(36211), // Rule ID 3209 //
12991 /* 36179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
12992 /* 36182 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
12993 /* 36185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12994 /* 36189 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
12995 /* 36193 */ // (bitconvert:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src) => (VREV32q8:{ *:[v4i32] } QPR:{ *:[v16i8] }:$src)
12996 /* 36193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
12997 /* 36196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
12998 /* 36198 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
12999 /* 36200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13000 /* 36203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13001 /* 36209 */ GIR_RootConstrainSelectedInstOperands,
13002 /* 36210 */ // GIR_Coverage, 3209,
13003 /* 36210 */ GIR_EraseRootFromParent_Done,
13004 /* 36211 */ // Label 799: @36211
13005 /* 36211 */ GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(36243), // Rule ID 5763 //
13006 /* 36216 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
13007 /* 36219 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13008 /* 36222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13009 /* 36226 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13010 /* 36230 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v4i32] }:$src
13011 /* 36230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13012 /* 36233 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13013 /* 36235 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13014 /* 36237 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13015 /* 36242 */ // GIR_Coverage, 5763,
13016 /* 36242 */ GIR_EraseRootFromParent_Done,
13017 /* 36243 */ // Label 800: @36243
13018 /* 36243 */ GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(36275), // Rule ID 5764 //
13019 /* 36248 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
13020 /* 36251 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13021 /* 36254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13022 /* 36258 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13023 /* 36262 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v4f32] }:$src
13024 /* 36262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13025 /* 36265 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13026 /* 36267 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13027 /* 36269 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13028 /* 36274 */ // GIR_Coverage, 5764,
13029 /* 36274 */ GIR_EraseRootFromParent_Done,
13030 /* 36275 */ // Label 801: @36275
13031 /* 36275 */ GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(36307), // Rule ID 5777 //
13032 /* 36280 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13033 /* 36283 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13034 /* 36286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13035 /* 36290 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13036 /* 36294 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4f32] }:$src
13037 /* 36294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13038 /* 36297 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13039 /* 36299 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13040 /* 36301 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13041 /* 36306 */ // GIR_Coverage, 5777,
13042 /* 36306 */ GIR_EraseRootFromParent_Done,
13043 /* 36307 */ // Label 802: @36307
13044 /* 36307 */ GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(36339), // Rule ID 5778 //
13045 /* 36312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13046 /* 36315 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13047 /* 36318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13048 /* 36322 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13049 /* 36326 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4f32] }:$src
13050 /* 36326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13051 /* 36329 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13052 /* 36331 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13053 /* 36333 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13054 /* 36338 */ // GIR_Coverage, 5778,
13055 /* 36338 */ GIR_EraseRootFromParent_Done,
13056 /* 36339 */ // Label 803: @36339
13057 /* 36339 */ GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(36371), // Rule ID 5779 //
13058 /* 36344 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13059 /* 36347 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13060 /* 36350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13061 /* 36354 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13062 /* 36358 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4f32] }:$src
13063 /* 36358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13064 /* 36361 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13065 /* 36363 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13066 /* 36365 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13067 /* 36370 */ // GIR_Coverage, 5779,
13068 /* 36370 */ GIR_EraseRootFromParent_Done,
13069 /* 36371 */ // Label 804: @36371
13070 /* 36371 */ GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(36403), // Rule ID 5780 //
13071 /* 36376 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13072 /* 36379 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13073 /* 36382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13074 /* 36386 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13075 /* 36390 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4f32] }:$src
13076 /* 36390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13077 /* 36393 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13078 /* 36395 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13079 /* 36397 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13080 /* 36402 */ // GIR_Coverage, 5780,
13081 /* 36402 */ GIR_EraseRootFromParent_Done,
13082 /* 36403 */ // Label 805: @36403
13083 /* 36403 */ GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(36435), // Rule ID 5781 //
13084 /* 36408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13085 /* 36411 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13086 /* 36414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13087 /* 36418 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13088 /* 36422 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4f32] }:$src
13089 /* 36422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13090 /* 36425 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13091 /* 36427 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13092 /* 36429 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13093 /* 36434 */ // GIR_Coverage, 5781,
13094 /* 36434 */ GIR_EraseRootFromParent_Done,
13095 /* 36435 */ // Label 806: @36435
13096 /* 36435 */ GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(36467), // Rule ID 5782 //
13097 /* 36440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13098 /* 36443 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13099 /* 36446 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13100 /* 36450 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13101 /* 36454 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v4i32] }:$src
13102 /* 36454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13103 /* 36457 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13104 /* 36459 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13105 /* 36461 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13106 /* 36466 */ // GIR_Coverage, 5782,
13107 /* 36466 */ GIR_EraseRootFromParent_Done,
13108 /* 36467 */ // Label 807: @36467
13109 /* 36467 */ GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(36499), // Rule ID 5783 //
13110 /* 36472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13111 /* 36475 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13112 /* 36478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13113 /* 36482 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13114 /* 36486 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v4i32] }:$src
13115 /* 36486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13116 /* 36489 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13117 /* 36491 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13118 /* 36493 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13119 /* 36498 */ // GIR_Coverage, 5783,
13120 /* 36498 */ GIR_EraseRootFromParent_Done,
13121 /* 36499 */ // Label 808: @36499
13122 /* 36499 */ GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(36531), // Rule ID 5784 //
13123 /* 36504 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13124 /* 36507 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13125 /* 36510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13126 /* 36514 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13127 /* 36518 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v4i32] }:$src
13128 /* 36518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13129 /* 36521 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13130 /* 36523 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13131 /* 36525 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13132 /* 36530 */ // GIR_Coverage, 5784,
13133 /* 36530 */ GIR_EraseRootFromParent_Done,
13134 /* 36531 */ // Label 809: @36531
13135 /* 36531 */ GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(36563), // Rule ID 5785 //
13136 /* 36536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13137 /* 36539 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13138 /* 36542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13139 /* 36546 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13140 /* 36550 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v4i32] }:$src
13141 /* 36550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13142 /* 36553 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13143 /* 36555 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13144 /* 36557 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13145 /* 36562 */ // GIR_Coverage, 5785,
13146 /* 36562 */ GIR_EraseRootFromParent_Done,
13147 /* 36563 */ // Label 810: @36563
13148 /* 36563 */ GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(36595), // Rule ID 5786 //
13149 /* 36568 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13150 /* 36571 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13151 /* 36574 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13152 /* 36578 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13153 /* 36582 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v4i32] }:$src
13154 /* 36582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13155 /* 36585 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13156 /* 36587 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13157 /* 36589 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13158 /* 36594 */ // GIR_Coverage, 5786,
13159 /* 36594 */ GIR_EraseRootFromParent_Done,
13160 /* 36595 */ // Label 811: @36595
13161 /* 36595 */ GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(36653), // Rule ID 5813 //
13162 /* 36600 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13163 /* 36603 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13164 /* 36606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13165 /* 36610 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13166 /* 36614 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2f64] }:$src)
13167 /* 36614 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13168 /* 36617 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13169 /* 36621 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13170 /* 36626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13171 /* 36629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13172 /* 36631 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13173 /* 36633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13174 /* 36636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13175 /* 36642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13176 /* 36648 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13177 /* 36651 */ GIR_RootConstrainSelectedInstOperands,
13178 /* 36652 */ // GIR_Coverage, 5813,
13179 /* 36652 */ GIR_EraseRootFromParent_Done,
13180 /* 36653 */ // Label 812: @36653
13181 /* 36653 */ GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(36711), // Rule ID 5814 //
13182 /* 36658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13183 /* 36661 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13184 /* 36664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13185 /* 36668 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13186 /* 36672 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4f32] } MQPR:{ *:[v2i64] }:$src)
13187 /* 36672 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13188 /* 36675 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13189 /* 36679 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13190 /* 36684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13191 /* 36687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13192 /* 36689 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13193 /* 36691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13194 /* 36694 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13195 /* 36700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13196 /* 36706 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13197 /* 36709 */ GIR_RootConstrainSelectedInstOperands,
13198 /* 36710 */ // GIR_Coverage, 5814,
13199 /* 36710 */ GIR_EraseRootFromParent_Done,
13200 /* 36711 */ // Label 813: @36711
13201 /* 36711 */ GIM_Try, /*On fail goto*//*Label 814*/ GIMT_Encode4(36769), // Rule ID 5815 //
13202 /* 36716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13203 /* 36719 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13204 /* 36722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13205 /* 36726 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13206 /* 36730 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$src)
13207 /* 36730 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13208 /* 36733 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13209 /* 36737 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13210 /* 36742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
13211 /* 36745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13212 /* 36747 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13213 /* 36749 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13214 /* 36752 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13215 /* 36758 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13216 /* 36764 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13217 /* 36767 */ GIR_RootConstrainSelectedInstOperands,
13218 /* 36768 */ // GIR_Coverage, 5815,
13219 /* 36768 */ GIR_EraseRootFromParent_Done,
13220 /* 36769 */ // Label 814: @36769
13221 /* 36769 */ GIM_Try, /*On fail goto*//*Label 815*/ GIMT_Encode4(36827), // Rule ID 5816 //
13222 /* 36774 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13223 /* 36777 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13224 /* 36780 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13225 /* 36784 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13226 /* 36788 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4f32] } MQPR:{ *:[v8i16] }:$src)
13227 /* 36788 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13228 /* 36791 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13229 /* 36795 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13230 /* 36800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
13231 /* 36803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13232 /* 36805 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13233 /* 36807 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13234 /* 36810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13235 /* 36816 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13236 /* 36822 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13237 /* 36825 */ GIR_RootConstrainSelectedInstOperands,
13238 /* 36826 */ // GIR_Coverage, 5816,
13239 /* 36826 */ GIR_EraseRootFromParent_Done,
13240 /* 36827 */ // Label 815: @36827
13241 /* 36827 */ GIM_Try, /*On fail goto*//*Label 816*/ GIMT_Encode4(36885), // Rule ID 5817 //
13242 /* 36832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13243 /* 36835 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13244 /* 36838 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13245 /* 36842 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13246 /* 36846 */ // (bitconvert:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4f32] } MQPR:{ *:[v16i8] }:$src)
13247 /* 36846 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13248 /* 36849 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13249 /* 36853 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13250 /* 36858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
13251 /* 36861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13252 /* 36863 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13253 /* 36865 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13254 /* 36868 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13255 /* 36874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13256 /* 36880 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13257 /* 36883 */ GIR_RootConstrainSelectedInstOperands,
13258 /* 36884 */ // GIR_Coverage, 5817,
13259 /* 36884 */ GIR_EraseRootFromParent_Done,
13260 /* 36885 */ // Label 816: @36885
13261 /* 36885 */ GIM_Try, /*On fail goto*//*Label 817*/ GIMT_Encode4(36943), // Rule ID 5818 //
13262 /* 36890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13263 /* 36893 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13264 /* 36896 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13265 /* 36900 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13266 /* 36904 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2f64] }:$src)
13267 /* 36904 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13268 /* 36907 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13269 /* 36911 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13270 /* 36916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13271 /* 36919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13272 /* 36921 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13273 /* 36923 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13274 /* 36926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13275 /* 36932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13276 /* 36938 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13277 /* 36941 */ GIR_RootConstrainSelectedInstOperands,
13278 /* 36942 */ // GIR_Coverage, 5818,
13279 /* 36942 */ GIR_EraseRootFromParent_Done,
13280 /* 36943 */ // Label 817: @36943
13281 /* 36943 */ GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(37001), // Rule ID 5819 //
13282 /* 36948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13283 /* 36951 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13284 /* 36954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13285 /* 36958 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13286 /* 36962 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_32:{ *:[v4i32] } MQPR:{ *:[v2i64] }:$src)
13287 /* 36962 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13288 /* 36965 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13289 /* 36969 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13290 /* 36974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_32),
13291 /* 36977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13292 /* 36979 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13293 /* 36981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13294 /* 36984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13295 /* 36990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13296 /* 36996 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13297 /* 36999 */ GIR_RootConstrainSelectedInstOperands,
13298 /* 37000 */ // GIR_Coverage, 5819,
13299 /* 37000 */ GIR_EraseRootFromParent_Done,
13300 /* 37001 */ // Label 818: @37001
13301 /* 37001 */ GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(37059), // Rule ID 5820 //
13302 /* 37006 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13303 /* 37009 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13304 /* 37012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13305 /* 37016 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13306 /* 37020 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8f16] }:$src)
13307 /* 37020 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13308 /* 37023 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13309 /* 37027 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13310 /* 37032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
13311 /* 37035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13312 /* 37037 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13313 /* 37039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13314 /* 37042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13315 /* 37048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13316 /* 37054 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13317 /* 37057 */ GIR_RootConstrainSelectedInstOperands,
13318 /* 37058 */ // GIR_Coverage, 5820,
13319 /* 37058 */ GIR_EraseRootFromParent_Done,
13320 /* 37059 */ // Label 819: @37059
13321 /* 37059 */ GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(37117), // Rule ID 5821 //
13322 /* 37064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13323 /* 37067 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13324 /* 37070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13325 /* 37074 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13326 /* 37078 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV32_16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
13327 /* 37078 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13328 /* 37081 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13329 /* 37085 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13330 /* 37090 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
13331 /* 37093 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13332 /* 37095 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13333 /* 37097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13334 /* 37100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13335 /* 37106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13336 /* 37112 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13337 /* 37115 */ GIR_RootConstrainSelectedInstOperands,
13338 /* 37116 */ // GIR_Coverage, 5821,
13339 /* 37116 */ GIR_EraseRootFromParent_Done,
13340 /* 37117 */ // Label 820: @37117
13341 /* 37117 */ GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(37175), // Rule ID 5822 //
13342 /* 37122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13343 /* 37125 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13344 /* 37128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13345 /* 37132 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13346 /* 37136 */ // (bitconvert:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v16i8] }:$src)
13347 /* 37136 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
13348 /* 37139 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
13349 /* 37143 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
13350 /* 37148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
13351 /* 37151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
13352 /* 37153 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13353 /* 37155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
13354 /* 37158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13355 /* 37164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13356 /* 37170 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
13357 /* 37173 */ GIR_RootConstrainSelectedInstOperands,
13358 /* 37174 */ // GIR_Coverage, 5822,
13359 /* 37174 */ GIR_EraseRootFromParent_Done,
13360 /* 37175 */ // Label 821: @37175
13361 /* 37175 */ GIM_Reject,
13362 /* 37176 */ // Label 660: @37176
13363 /* 37176 */ GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(37208), // Rule ID 3112 //
13364 /* 37181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13365 /* 37184 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13366 /* 37187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13367 /* 37191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13368 /* 37195 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => DPR:{ *:[v8i8] }:$src
13369 /* 37195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13370 /* 37198 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13371 /* 37200 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13372 /* 37202 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
13373 /* 37207 */ // GIR_Coverage, 3112,
13374 /* 37207 */ GIR_EraseRootFromParent_Done,
13375 /* 37208 */ // Label 822: @37208
13376 /* 37208 */ GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(37240), // Rule ID 3113 //
13377 /* 37213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13378 /* 37216 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13379 /* 37219 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13380 /* 37223 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13381 /* 37227 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => DPR:{ *:[v8i8] }:$src
13382 /* 37227 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13383 /* 37230 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13384 /* 37232 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13385 /* 37234 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
13386 /* 37239 */ // GIR_Coverage, 3113,
13387 /* 37239 */ GIR_EraseRootFromParent_Done,
13388 /* 37240 */ // Label 823: @37240
13389 /* 37240 */ GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(37272), // Rule ID 3114 //
13390 /* 37245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13391 /* 37248 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
13392 /* 37251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13393 /* 37255 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13394 /* 37259 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => DPR:{ *:[v8i8] }:$src
13395 /* 37259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13396 /* 37262 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13397 /* 37264 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13398 /* 37266 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
13399 /* 37271 */ // GIR_Coverage, 3114,
13400 /* 37271 */ GIR_EraseRootFromParent_Done,
13401 /* 37272 */ // Label 824: @37272
13402 /* 37272 */ GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(37304), // Rule ID 3115 //
13403 /* 37277 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13404 /* 37280 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
13405 /* 37283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13406 /* 37287 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13407 /* 37291 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => DPR:{ *:[v8i8] }:$src
13408 /* 37291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13409 /* 37294 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13410 /* 37296 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13411 /* 37298 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
13412 /* 37303 */ // GIR_Coverage, 3115,
13413 /* 37303 */ GIR_EraseRootFromParent_Done,
13414 /* 37304 */ // Label 825: @37304
13415 /* 37304 */ GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(37336), // Rule ID 3116 //
13416 /* 37309 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13417 /* 37312 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13418 /* 37315 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13419 /* 37319 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13420 /* 37323 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => DPR:{ *:[v8i8] }:$src
13421 /* 37323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13422 /* 37326 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13423 /* 37328 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13424 /* 37330 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
13425 /* 37335 */ // GIR_Coverage, 3116,
13426 /* 37335 */ GIR_EraseRootFromParent_Done,
13427 /* 37336 */ // Label 826: @37336
13428 /* 37336 */ GIM_Try, /*On fail goto*//*Label 827*/ GIMT_Encode4(37368), // Rule ID 3117 //
13429 /* 37341 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13430 /* 37344 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13431 /* 37347 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13432 /* 37351 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13433 /* 37355 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => DPR:{ *:[v8i8] }:$src
13434 /* 37355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13435 /* 37358 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13436 /* 37360 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13437 /* 37362 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::DPRRegClassID),
13438 /* 37367 */ // GIR_Coverage, 3117,
13439 /* 37367 */ GIR_EraseRootFromParent_Done,
13440 /* 37368 */ // Label 827: @37368
13441 /* 37368 */ GIM_Try, /*On fail goto*//*Label 828*/ GIMT_Encode4(37405), // Rule ID 3184 //
13442 /* 37373 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13443 /* 37376 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13444 /* 37379 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13445 /* 37383 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13446 /* 37387 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[f64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[f64] }:$src)
13447 /* 37387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
13448 /* 37390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13449 /* 37392 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13450 /* 37394 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13451 /* 37397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13452 /* 37403 */ GIR_RootConstrainSelectedInstOperands,
13453 /* 37404 */ // GIR_Coverage, 3184,
13454 /* 37404 */ GIR_EraseRootFromParent_Done,
13455 /* 37405 */ // Label 828: @37405
13456 /* 37405 */ GIM_Try, /*On fail goto*//*Label 829*/ GIMT_Encode4(37442), // Rule ID 3185 //
13457 /* 37410 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13458 /* 37413 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
13459 /* 37416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13460 /* 37420 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13461 /* 37424 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src) => (VREV64d8:{ *:[v8i8] } DPR:{ *:[v1i64] }:$src)
13462 /* 37424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64d8),
13463 /* 37427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13464 /* 37429 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13465 /* 37431 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13466 /* 37434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13467 /* 37440 */ GIR_RootConstrainSelectedInstOperands,
13468 /* 37441 */ // GIR_Coverage, 3185,
13469 /* 37441 */ GIR_EraseRootFromParent_Done,
13470 /* 37442 */ // Label 829: @37442
13471 /* 37442 */ GIM_Try, /*On fail goto*//*Label 830*/ GIMT_Encode4(37479), // Rule ID 3186 //
13472 /* 37447 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13473 /* 37450 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
13474 /* 37453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13475 /* 37457 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13476 /* 37461 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2f32] }:$src)
13477 /* 37461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
13478 /* 37464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13479 /* 37466 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13480 /* 37468 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13481 /* 37471 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13482 /* 37477 */ GIR_RootConstrainSelectedInstOperands,
13483 /* 37478 */ // GIR_Coverage, 3186,
13484 /* 37478 */ GIR_EraseRootFromParent_Done,
13485 /* 37479 */ // Label 830: @37479
13486 /* 37479 */ GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(37516), // Rule ID 3187 //
13487 /* 37484 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13488 /* 37487 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
13489 /* 37490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13490 /* 37494 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13491 /* 37498 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src) => (VREV32d8:{ *:[v8i8] } DPR:{ *:[v2i32] }:$src)
13492 /* 37498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32d8),
13493 /* 37501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13494 /* 37503 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13495 /* 37505 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13496 /* 37508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13497 /* 37514 */ GIR_RootConstrainSelectedInstOperands,
13498 /* 37515 */ // GIR_Coverage, 3187,
13499 /* 37515 */ GIR_EraseRootFromParent_Done,
13500 /* 37516 */ // Label 831: @37516
13501 /* 37516 */ GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(37553), // Rule ID 3188 //
13502 /* 37521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13503 /* 37524 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13504 /* 37527 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13505 /* 37531 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13506 /* 37535 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4f16] }:$src)
13507 /* 37535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
13508 /* 37538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13509 /* 37540 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13510 /* 37542 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13511 /* 37545 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13512 /* 37551 */ GIR_RootConstrainSelectedInstOperands,
13513 /* 37552 */ // GIR_Coverage, 3188,
13514 /* 37552 */ GIR_EraseRootFromParent_Done,
13515 /* 37553 */ // Label 832: @37553
13516 /* 37553 */ GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(37590), // Rule ID 3189 //
13517 /* 37558 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13518 /* 37561 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
13519 /* 37564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13520 /* 37568 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
13521 /* 37572 */ // (bitconvert:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src) => (VREV16d8:{ *:[v8i8] } DPR:{ *:[v4i16] }:$src)
13522 /* 37572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16d8),
13523 /* 37575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13524 /* 37577 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13525 /* 37579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13526 /* 37582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13527 /* 37588 */ GIR_RootConstrainSelectedInstOperands,
13528 /* 37589 */ // GIR_Coverage, 3189,
13529 /* 37589 */ GIR_EraseRootFromParent_Done,
13530 /* 37590 */ // Label 833: @37590
13531 /* 37590 */ GIM_Reject,
13532 /* 37591 */ // Label 661: @37591
13533 /* 37591 */ GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(37623), // Rule ID 3080 //
13534 /* 37596 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13535 /* 37599 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13536 /* 37602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13537 /* 37606 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13538 /* 37610 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v8i16] }:$src
13539 /* 37610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13540 /* 37613 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13541 /* 37615 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13542 /* 37617 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13543 /* 37622 */ // GIR_Coverage, 3080,
13544 /* 37622 */ GIR_EraseRootFromParent_Done,
13545 /* 37623 */ // Label 834: @37623
13546 /* 37623 */ GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(37655), // Rule ID 3081 //
13547 /* 37628 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
13548 /* 37631 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13549 /* 37634 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13550 /* 37638 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13551 /* 37642 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v8f16] }:$src
13552 /* 37642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13553 /* 37645 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13554 /* 37647 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13555 /* 37649 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13556 /* 37654 */ // GIR_Coverage, 3081,
13557 /* 37654 */ GIR_EraseRootFromParent_Done,
13558 /* 37655 */ // Label 835: @37655
13559 /* 37655 */ GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(37687), // Rule ID 3138 //
13560 /* 37660 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13561 /* 37663 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13562 /* 37666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13563 /* 37670 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13564 /* 37674 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8f16] }:$src
13565 /* 37674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13566 /* 37677 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13567 /* 37679 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13568 /* 37681 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13569 /* 37686 */ // GIR_Coverage, 3138,
13570 /* 37686 */ GIR_EraseRootFromParent_Done,
13571 /* 37687 */ // Label 836: @37687
13572 /* 37687 */ GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(37719), // Rule ID 3139 //
13573 /* 37692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13574 /* 37695 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13575 /* 37698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13576 /* 37702 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13577 /* 37706 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8f16] }:$src
13578 /* 37706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13579 /* 37709 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13580 /* 37711 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13581 /* 37713 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13582 /* 37718 */ // GIR_Coverage, 3139,
13583 /* 37718 */ GIR_EraseRootFromParent_Done,
13584 /* 37719 */ // Label 837: @37719
13585 /* 37719 */ GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(37751), // Rule ID 3140 //
13586 /* 37724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13587 /* 37727 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13588 /* 37730 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13589 /* 37734 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13590 /* 37738 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8f16] }:$src
13591 /* 37738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13592 /* 37741 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13593 /* 37743 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13594 /* 37745 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13595 /* 37750 */ // GIR_Coverage, 3140,
13596 /* 37750 */ GIR_EraseRootFromParent_Done,
13597 /* 37751 */ // Label 838: @37751
13598 /* 37751 */ GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(37783), // Rule ID 3141 //
13599 /* 37756 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13600 /* 37759 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13601 /* 37762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13602 /* 37766 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13603 /* 37770 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8f16] }:$src
13604 /* 37770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13605 /* 37773 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13606 /* 37775 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13607 /* 37777 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13608 /* 37782 */ // GIR_Coverage, 3141,
13609 /* 37782 */ GIR_EraseRootFromParent_Done,
13610 /* 37783 */ // Label 839: @37783
13611 /* 37783 */ GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(37815), // Rule ID 3142 //
13612 /* 37788 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13613 /* 37791 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13614 /* 37794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13615 /* 37798 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13616 /* 37802 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8f16] }:$src
13617 /* 37802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13618 /* 37805 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13619 /* 37807 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13620 /* 37809 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13621 /* 37814 */ // GIR_Coverage, 3142,
13622 /* 37814 */ GIR_EraseRootFromParent_Done,
13623 /* 37815 */ // Label 840: @37815
13624 /* 37815 */ GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(37847), // Rule ID 3143 //
13625 /* 37820 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13626 /* 37823 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13627 /* 37826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13628 /* 37830 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13629 /* 37834 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v8i16] }:$src
13630 /* 37834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13631 /* 37837 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13632 /* 37839 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13633 /* 37841 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13634 /* 37846 */ // GIR_Coverage, 3143,
13635 /* 37846 */ GIR_EraseRootFromParent_Done,
13636 /* 37847 */ // Label 841: @37847
13637 /* 37847 */ GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(37879), // Rule ID 3144 //
13638 /* 37852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13639 /* 37855 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13640 /* 37858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13641 /* 37862 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13642 /* 37866 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v8i16] }:$src
13643 /* 37866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13644 /* 37869 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13645 /* 37871 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13646 /* 37873 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13647 /* 37878 */ // GIR_Coverage, 3144,
13648 /* 37878 */ GIR_EraseRootFromParent_Done,
13649 /* 37879 */ // Label 842: @37879
13650 /* 37879 */ GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(37911), // Rule ID 3145 //
13651 /* 37884 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13652 /* 37887 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13653 /* 37890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13654 /* 37894 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13655 /* 37898 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v8i16] }:$src
13656 /* 37898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13657 /* 37901 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13658 /* 37903 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13659 /* 37905 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13660 /* 37910 */ // GIR_Coverage, 3145,
13661 /* 37910 */ GIR_EraseRootFromParent_Done,
13662 /* 37911 */ // Label 843: @37911
13663 /* 37911 */ GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(37943), // Rule ID 3146 //
13664 /* 37916 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13665 /* 37919 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13666 /* 37922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13667 /* 37926 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13668 /* 37930 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v8i16] }:$src
13669 /* 37930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13670 /* 37933 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13671 /* 37935 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13672 /* 37937 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13673 /* 37942 */ // GIR_Coverage, 3146,
13674 /* 37942 */ GIR_EraseRootFromParent_Done,
13675 /* 37943 */ // Label 844: @37943
13676 /* 37943 */ GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(37975), // Rule ID 3147 //
13677 /* 37948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
13678 /* 37951 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13679 /* 37954 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13680 /* 37958 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13681 /* 37962 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => QPR:{ *:[v8i16] }:$src
13682 /* 37962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13683 /* 37965 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13684 /* 37967 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13685 /* 37969 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
13686 /* 37974 */ // GIR_Coverage, 3147,
13687 /* 37974 */ GIR_EraseRootFromParent_Done,
13688 /* 37975 */ // Label 845: @37975
13689 /* 37975 */ GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(38012), // Rule ID 3210 //
13690 /* 37980 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13691 /* 37983 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13692 /* 37986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13693 /* 37990 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13694 /* 37994 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2f64] }:$src)
13695 /* 37994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
13696 /* 37997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13697 /* 37999 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13698 /* 38001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13699 /* 38004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13700 /* 38010 */ GIR_RootConstrainSelectedInstOperands,
13701 /* 38011 */ // GIR_Coverage, 3210,
13702 /* 38011 */ GIR_EraseRootFromParent_Done,
13703 /* 38012 */ // Label 846: @38012
13704 /* 38012 */ GIM_Try, /*On fail goto*//*Label 847*/ GIMT_Encode4(38049), // Rule ID 3211 //
13705 /* 38017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13706 /* 38020 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13707 /* 38023 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13708 /* 38027 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13709 /* 38031 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8f16] } QPR:{ *:[v2i64] }:$src)
13710 /* 38031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
13711 /* 38034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13712 /* 38036 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13713 /* 38038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13714 /* 38041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13715 /* 38047 */ GIR_RootConstrainSelectedInstOperands,
13716 /* 38048 */ // GIR_Coverage, 3211,
13717 /* 38048 */ GIR_EraseRootFromParent_Done,
13718 /* 38049 */ // Label 847: @38049
13719 /* 38049 */ GIM_Try, /*On fail goto*//*Label 848*/ GIMT_Encode4(38086), // Rule ID 3212 //
13720 /* 38054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13721 /* 38057 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13722 /* 38060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13723 /* 38064 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13724 /* 38068 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4f32] }:$src)
13725 /* 38068 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
13726 /* 38071 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13727 /* 38073 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13728 /* 38075 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13729 /* 38078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13730 /* 38084 */ GIR_RootConstrainSelectedInstOperands,
13731 /* 38085 */ // GIR_Coverage, 3212,
13732 /* 38085 */ GIR_EraseRootFromParent_Done,
13733 /* 38086 */ // Label 848: @38086
13734 /* 38086 */ GIM_Try, /*On fail goto*//*Label 849*/ GIMT_Encode4(38123), // Rule ID 3213 //
13735 /* 38091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13736 /* 38094 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13737 /* 38097 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13738 /* 38101 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13739 /* 38105 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8f16] } QPR:{ *:[v4i32] }:$src)
13740 /* 38105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
13741 /* 38108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13742 /* 38110 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13743 /* 38112 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13744 /* 38115 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13745 /* 38121 */ GIR_RootConstrainSelectedInstOperands,
13746 /* 38122 */ // GIR_Coverage, 3213,
13747 /* 38122 */ GIR_EraseRootFromParent_Done,
13748 /* 38123 */ // Label 849: @38123
13749 /* 38123 */ GIM_Try, /*On fail goto*//*Label 850*/ GIMT_Encode4(38160), // Rule ID 3214 //
13750 /* 38128 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13751 /* 38131 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13752 /* 38134 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13753 /* 38138 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13754 /* 38142 */ // (bitconvert:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8f16] } QPR:{ *:[v16i8] }:$src)
13755 /* 38142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
13756 /* 38145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13757 /* 38147 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13758 /* 38149 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13759 /* 38152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13760 /* 38158 */ GIR_RootConstrainSelectedInstOperands,
13761 /* 38159 */ // GIR_Coverage, 3214,
13762 /* 38159 */ GIR_EraseRootFromParent_Done,
13763 /* 38160 */ // Label 850: @38160
13764 /* 38160 */ GIM_Try, /*On fail goto*//*Label 851*/ GIMT_Encode4(38197), // Rule ID 3215 //
13765 /* 38165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13766 /* 38168 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13767 /* 38171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13768 /* 38175 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13769 /* 38179 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2f64] }:$src)
13770 /* 38179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
13771 /* 38182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13772 /* 38184 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13773 /* 38186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13774 /* 38189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13775 /* 38195 */ GIR_RootConstrainSelectedInstOperands,
13776 /* 38196 */ // GIR_Coverage, 3215,
13777 /* 38196 */ GIR_EraseRootFromParent_Done,
13778 /* 38197 */ // Label 851: @38197
13779 /* 38197 */ GIM_Try, /*On fail goto*//*Label 852*/ GIMT_Encode4(38234), // Rule ID 3216 //
13780 /* 38202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13781 /* 38205 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13782 /* 38208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13783 /* 38212 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13784 /* 38216 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src) => (VREV64q16:{ *:[v8i16] } QPR:{ *:[v2i64] }:$src)
13785 /* 38216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q16),
13786 /* 38219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13787 /* 38221 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13788 /* 38223 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13789 /* 38226 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13790 /* 38232 */ GIR_RootConstrainSelectedInstOperands,
13791 /* 38233 */ // GIR_Coverage, 3216,
13792 /* 38233 */ GIR_EraseRootFromParent_Done,
13793 /* 38234 */ // Label 852: @38234
13794 /* 38234 */ GIM_Try, /*On fail goto*//*Label 853*/ GIMT_Encode4(38271), // Rule ID 3217 //
13795 /* 38239 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13796 /* 38242 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13797 /* 38245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13798 /* 38249 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13799 /* 38253 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4f32] }:$src)
13800 /* 38253 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
13801 /* 38256 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13802 /* 38258 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13803 /* 38260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13804 /* 38263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13805 /* 38269 */ GIR_RootConstrainSelectedInstOperands,
13806 /* 38270 */ // GIR_Coverage, 3217,
13807 /* 38270 */ GIR_EraseRootFromParent_Done,
13808 /* 38271 */ // Label 853: @38271
13809 /* 38271 */ GIM_Try, /*On fail goto*//*Label 854*/ GIMT_Encode4(38308), // Rule ID 3218 //
13810 /* 38276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13811 /* 38279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13812 /* 38282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13813 /* 38286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13814 /* 38290 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src) => (VREV32q16:{ *:[v8i16] } QPR:{ *:[v4i32] }:$src)
13815 /* 38290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q16),
13816 /* 38293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13817 /* 38295 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13818 /* 38297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13819 /* 38300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13820 /* 38306 */ GIR_RootConstrainSelectedInstOperands,
13821 /* 38307 */ // GIR_Coverage, 3218,
13822 /* 38307 */ GIR_EraseRootFromParent_Done,
13823 /* 38308 */ // Label 854: @38308
13824 /* 38308 */ GIM_Try, /*On fail goto*//*Label 855*/ GIMT_Encode4(38345), // Rule ID 3219 //
13825 /* 38313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
13826 /* 38316 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13827 /* 38319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13828 /* 38323 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
13829 /* 38327 */ // (bitconvert:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src) => (VREV16q8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$src)
13830 /* 38327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
13831 /* 38330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
13832 /* 38332 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13833 /* 38334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
13834 /* 38337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
13835 /* 38343 */ GIR_RootConstrainSelectedInstOperands,
13836 /* 38344 */ // GIR_Coverage, 3219,
13837 /* 38344 */ GIR_EraseRootFromParent_Done,
13838 /* 38345 */ // Label 855: @38345
13839 /* 38345 */ GIM_Try, /*On fail goto*//*Label 856*/ GIMT_Encode4(38377), // Rule ID 5765 //
13840 /* 38350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
13841 /* 38353 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13842 /* 38356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13843 /* 38360 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13844 /* 38364 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v8i16] }:$src
13845 /* 38364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13846 /* 38367 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13847 /* 38369 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13848 /* 38371 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13849 /* 38376 */ // GIR_Coverage, 5765,
13850 /* 38376 */ GIR_EraseRootFromParent_Done,
13851 /* 38377 */ // Label 856: @38377
13852 /* 38377 */ GIM_Try, /*On fail goto*//*Label 857*/ GIMT_Encode4(38409), // Rule ID 5766 //
13853 /* 38382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
13854 /* 38385 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
13855 /* 38388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13856 /* 38392 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13857 /* 38396 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v8f16] }:$src
13858 /* 38396 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13859 /* 38399 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13860 /* 38401 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13861 /* 38403 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13862 /* 38408 */ // GIR_Coverage, 5766,
13863 /* 38408 */ GIR_EraseRootFromParent_Done,
13864 /* 38409 */ // Label 857: @38409
13865 /* 38409 */ GIM_Try, /*On fail goto*//*Label 858*/ GIMT_Encode4(38441), // Rule ID 5787 //
13866 /* 38414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13867 /* 38417 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13868 /* 38420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13869 /* 38424 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13870 /* 38428 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8f16] }:$src
13871 /* 38428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13872 /* 38431 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13873 /* 38433 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13874 /* 38435 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13875 /* 38440 */ // GIR_Coverage, 5787,
13876 /* 38440 */ GIR_EraseRootFromParent_Done,
13877 /* 38441 */ // Label 858: @38441
13878 /* 38441 */ GIM_Try, /*On fail goto*//*Label 859*/ GIMT_Encode4(38473), // Rule ID 5788 //
13879 /* 38446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13880 /* 38449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13881 /* 38452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13882 /* 38456 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13883 /* 38460 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8f16] }:$src
13884 /* 38460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13885 /* 38463 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13886 /* 38465 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13887 /* 38467 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13888 /* 38472 */ // GIR_Coverage, 5788,
13889 /* 38472 */ GIR_EraseRootFromParent_Done,
13890 /* 38473 */ // Label 859: @38473
13891 /* 38473 */ GIM_Try, /*On fail goto*//*Label 860*/ GIMT_Encode4(38505), // Rule ID 5789 //
13892 /* 38478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13893 /* 38481 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13894 /* 38484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13895 /* 38488 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13896 /* 38492 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8f16] }:$src
13897 /* 38492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13898 /* 38495 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13899 /* 38497 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13900 /* 38499 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13901 /* 38504 */ // GIR_Coverage, 5789,
13902 /* 38504 */ GIR_EraseRootFromParent_Done,
13903 /* 38505 */ // Label 860: @38505
13904 /* 38505 */ GIM_Try, /*On fail goto*//*Label 861*/ GIMT_Encode4(38537), // Rule ID 5790 //
13905 /* 38510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13906 /* 38513 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13907 /* 38516 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13908 /* 38520 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13909 /* 38524 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8f16] }:$src
13910 /* 38524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13911 /* 38527 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13912 /* 38529 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13913 /* 38531 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13914 /* 38536 */ // GIR_Coverage, 5790,
13915 /* 38536 */ GIR_EraseRootFromParent_Done,
13916 /* 38537 */ // Label 861: @38537
13917 /* 38537 */ GIM_Try, /*On fail goto*//*Label 862*/ GIMT_Encode4(38569), // Rule ID 5791 //
13918 /* 38542 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13919 /* 38545 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13920 /* 38548 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13921 /* 38552 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13922 /* 38556 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8f16] }:$src
13923 /* 38556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13924 /* 38559 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13925 /* 38561 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13926 /* 38563 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13927 /* 38568 */ // GIR_Coverage, 5791,
13928 /* 38568 */ GIR_EraseRootFromParent_Done,
13929 /* 38569 */ // Label 862: @38569
13930 /* 38569 */ GIM_Try, /*On fail goto*//*Label 863*/ GIMT_Encode4(38601), // Rule ID 5792 //
13931 /* 38574 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13932 /* 38577 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13933 /* 38580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13934 /* 38584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13935 /* 38588 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v8i16] }:$src
13936 /* 38588 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13937 /* 38591 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13938 /* 38593 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13939 /* 38595 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13940 /* 38600 */ // GIR_Coverage, 5792,
13941 /* 38600 */ GIR_EraseRootFromParent_Done,
13942 /* 38601 */ // Label 863: @38601
13943 /* 38601 */ GIM_Try, /*On fail goto*//*Label 864*/ GIMT_Encode4(38633), // Rule ID 5793 //
13944 /* 38606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13945 /* 38609 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13946 /* 38612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13947 /* 38616 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13948 /* 38620 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v8i16] }:$src
13949 /* 38620 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13950 /* 38623 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13951 /* 38625 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13952 /* 38627 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13953 /* 38632 */ // GIR_Coverage, 5793,
13954 /* 38632 */ GIR_EraseRootFromParent_Done,
13955 /* 38633 */ // Label 864: @38633
13956 /* 38633 */ GIM_Try, /*On fail goto*//*Label 865*/ GIMT_Encode4(38665), // Rule ID 5794 //
13957 /* 38638 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13958 /* 38641 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13959 /* 38644 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13960 /* 38648 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13961 /* 38652 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v8i16] }:$src
13962 /* 38652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13963 /* 38655 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13964 /* 38657 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13965 /* 38659 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13966 /* 38664 */ // GIR_Coverage, 5794,
13967 /* 38664 */ GIR_EraseRootFromParent_Done,
13968 /* 38665 */ // Label 865: @38665
13969 /* 38665 */ GIM_Try, /*On fail goto*//*Label 866*/ GIMT_Encode4(38697), // Rule ID 5795 //
13970 /* 38670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13971 /* 38673 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
13972 /* 38676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13973 /* 38680 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13974 /* 38684 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v8i16] }:$src
13975 /* 38684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13976 /* 38687 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13977 /* 38689 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13978 /* 38691 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13979 /* 38696 */ // GIR_Coverage, 5795,
13980 /* 38696 */ GIR_EraseRootFromParent_Done,
13981 /* 38697 */ // Label 866: @38697
13982 /* 38697 */ GIM_Try, /*On fail goto*//*Label 867*/ GIMT_Encode4(38729), // Rule ID 5796 //
13983 /* 38702 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
13984 /* 38705 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
13985 /* 38708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13986 /* 38712 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13987 /* 38716 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => MQPR:{ *:[v8i16] }:$src
13988 /* 38716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
13989 /* 38719 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
13990 /* 38721 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
13991 /* 38723 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
13992 /* 38728 */ // GIR_Coverage, 5796,
13993 /* 38728 */ GIR_EraseRootFromParent_Done,
13994 /* 38729 */ // Label 867: @38729
13995 /* 38729 */ GIM_Try, /*On fail goto*//*Label 868*/ GIMT_Encode4(38787), // Rule ID 5823 //
13996 /* 38734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
13997 /* 38737 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
13998 /* 38740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
13999 /* 38744 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14000 /* 38748 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2f64] }:$src)
14001 /* 38748 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14002 /* 38751 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14003 /* 38755 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14004 /* 38760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
14005 /* 38763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14006 /* 38765 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14007 /* 38767 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14008 /* 38770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14009 /* 38776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14010 /* 38782 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14011 /* 38785 */ GIR_RootConstrainSelectedInstOperands,
14012 /* 38786 */ // GIR_Coverage, 5823,
14013 /* 38786 */ GIR_EraseRootFromParent_Done,
14014 /* 38787 */ // Label 868: @38787
14015 /* 38787 */ GIM_Try, /*On fail goto*//*Label 869*/ GIMT_Encode4(38845), // Rule ID 5824 //
14016 /* 38792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14017 /* 38795 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14018 /* 38798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14019 /* 38802 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14020 /* 38806 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8f16] } MQPR:{ *:[v2i64] }:$src)
14021 /* 38806 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14022 /* 38809 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14023 /* 38813 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14024 /* 38818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
14025 /* 38821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14026 /* 38823 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14027 /* 38825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14028 /* 38828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14029 /* 38834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14030 /* 38840 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14031 /* 38843 */ GIR_RootConstrainSelectedInstOperands,
14032 /* 38844 */ // GIR_Coverage, 5824,
14033 /* 38844 */ GIR_EraseRootFromParent_Done,
14034 /* 38845 */ // Label 869: @38845
14035 /* 38845 */ GIM_Try, /*On fail goto*//*Label 870*/ GIMT_Encode4(38903), // Rule ID 5825 //
14036 /* 38850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14037 /* 38853 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14038 /* 38856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14039 /* 38860 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14040 /* 38864 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4f32] }:$src)
14041 /* 38864 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14042 /* 38867 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14043 /* 38871 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14044 /* 38876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
14045 /* 38879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14046 /* 38881 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14047 /* 38883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14048 /* 38886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14049 /* 38892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14050 /* 38898 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14051 /* 38901 */ GIR_RootConstrainSelectedInstOperands,
14052 /* 38902 */ // GIR_Coverage, 5825,
14053 /* 38902 */ GIR_EraseRootFromParent_Done,
14054 /* 38903 */ // Label 870: @38903
14055 /* 38903 */ GIM_Try, /*On fail goto*//*Label 871*/ GIMT_Encode4(38961), // Rule ID 5826 //
14056 /* 38908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14057 /* 38911 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14058 /* 38914 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14059 /* 38918 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14060 /* 38922 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8f16] } MQPR:{ *:[v4i32] }:$src)
14061 /* 38922 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14062 /* 38925 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14063 /* 38929 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14064 /* 38934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
14065 /* 38937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14066 /* 38939 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14067 /* 38941 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14068 /* 38944 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14069 /* 38950 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14070 /* 38956 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14071 /* 38959 */ GIR_RootConstrainSelectedInstOperands,
14072 /* 38960 */ // GIR_Coverage, 5826,
14073 /* 38960 */ GIR_EraseRootFromParent_Done,
14074 /* 38961 */ // Label 871: @38961
14075 /* 38961 */ GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(39019), // Rule ID 5827 //
14076 /* 38966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14077 /* 38969 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
14078 /* 38972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14079 /* 38976 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14080 /* 38980 */ // (bitconvert:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8f16] } MQPR:{ *:[v16i8] }:$src)
14081 /* 38980 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14082 /* 38983 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14083 /* 38987 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14084 /* 38992 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
14085 /* 38995 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14086 /* 38997 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14087 /* 38999 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14088 /* 39002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14089 /* 39008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14090 /* 39014 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14091 /* 39017 */ GIR_RootConstrainSelectedInstOperands,
14092 /* 39018 */ // GIR_Coverage, 5827,
14093 /* 39018 */ GIR_EraseRootFromParent_Done,
14094 /* 39019 */ // Label 872: @39019
14095 /* 39019 */ GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(39077), // Rule ID 5828 //
14096 /* 39024 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14097 /* 39027 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14098 /* 39030 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14099 /* 39034 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14100 /* 39038 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2f64] }:$src)
14101 /* 39038 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14102 /* 39041 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14103 /* 39045 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14104 /* 39050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
14105 /* 39053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14106 /* 39055 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14107 /* 39057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14108 /* 39060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14109 /* 39066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14110 /* 39072 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14111 /* 39075 */ GIR_RootConstrainSelectedInstOperands,
14112 /* 39076 */ // GIR_Coverage, 5828,
14113 /* 39076 */ GIR_EraseRootFromParent_Done,
14114 /* 39077 */ // Label 873: @39077
14115 /* 39077 */ GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(39135), // Rule ID 5829 //
14116 /* 39082 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14117 /* 39085 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14118 /* 39088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14119 /* 39092 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14120 /* 39096 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_16:{ *:[v8i16] } MQPR:{ *:[v2i64] }:$src)
14121 /* 39096 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14122 /* 39099 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14123 /* 39103 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14124 /* 39108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_16),
14125 /* 39111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14126 /* 39113 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14127 /* 39115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14128 /* 39118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14129 /* 39124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14130 /* 39130 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14131 /* 39133 */ GIR_RootConstrainSelectedInstOperands,
14132 /* 39134 */ // GIR_Coverage, 5829,
14133 /* 39134 */ GIR_EraseRootFromParent_Done,
14134 /* 39135 */ // Label 874: @39135
14135 /* 39135 */ GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(39193), // Rule ID 5830 //
14136 /* 39140 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14137 /* 39143 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14138 /* 39146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14139 /* 39150 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14140 /* 39154 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4f32] }:$src)
14141 /* 39154 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14142 /* 39157 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14143 /* 39161 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14144 /* 39166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
14145 /* 39169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14146 /* 39171 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14147 /* 39173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14148 /* 39176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14149 /* 39182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14150 /* 39188 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14151 /* 39191 */ GIR_RootConstrainSelectedInstOperands,
14152 /* 39192 */ // GIR_Coverage, 5830,
14153 /* 39192 */ GIR_EraseRootFromParent_Done,
14154 /* 39193 */ // Label 875: @39193
14155 /* 39193 */ GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(39251), // Rule ID 5831 //
14156 /* 39198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14157 /* 39201 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14158 /* 39204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14159 /* 39208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14160 /* 39212 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_16:{ *:[v8i16] } MQPR:{ *:[v4i32] }:$src)
14161 /* 39212 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14162 /* 39215 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14163 /* 39219 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14164 /* 39224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_16),
14165 /* 39227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14166 /* 39229 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14167 /* 39231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14168 /* 39234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14169 /* 39240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14170 /* 39246 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14171 /* 39249 */ GIR_RootConstrainSelectedInstOperands,
14172 /* 39250 */ // GIR_Coverage, 5831,
14173 /* 39250 */ GIR_EraseRootFromParent_Done,
14174 /* 39251 */ // Label 876: @39251
14175 /* 39251 */ GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(39309), // Rule ID 5832 //
14176 /* 39256 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14177 /* 39259 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
14178 /* 39262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14179 /* 39266 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14180 /* 39270 */ // (bitconvert:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
14181 /* 39270 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14182 /* 39273 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14183 /* 39277 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14184 /* 39282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
14185 /* 39285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14186 /* 39287 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14187 /* 39289 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14188 /* 39292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14189 /* 39298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14190 /* 39304 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14191 /* 39307 */ GIR_RootConstrainSelectedInstOperands,
14192 /* 39308 */ // GIR_Coverage, 5832,
14193 /* 39308 */ GIR_EraseRootFromParent_Done,
14194 /* 39309 */ // Label 877: @39309
14195 /* 39309 */ GIM_Reject,
14196 /* 39310 */ // Label 662: @39310
14197 /* 39310 */ GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(39342), // Rule ID 3148 //
14198 /* 39315 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
14199 /* 39318 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14200 /* 39321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14201 /* 39325 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14202 /* 39329 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => QPR:{ *:[v16i8] }:$src
14203 /* 39329 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14204 /* 39332 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14205 /* 39334 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14206 /* 39336 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
14207 /* 39341 */ // GIR_Coverage, 3148,
14208 /* 39341 */ GIR_EraseRootFromParent_Done,
14209 /* 39342 */ // Label 878: @39342
14210 /* 39342 */ GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(39374), // Rule ID 3149 //
14211 /* 39347 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
14212 /* 39350 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14213 /* 39353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14214 /* 39357 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14215 /* 39361 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => QPR:{ *:[v16i8] }:$src
14216 /* 39361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14217 /* 39364 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14218 /* 39366 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14219 /* 39368 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
14220 /* 39373 */ // GIR_Coverage, 3149,
14221 /* 39373 */ GIR_EraseRootFromParent_Done,
14222 /* 39374 */ // Label 879: @39374
14223 /* 39374 */ GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(39406), // Rule ID 3150 //
14224 /* 39379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
14225 /* 39382 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14226 /* 39385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14227 /* 39389 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14228 /* 39393 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => QPR:{ *:[v16i8] }:$src
14229 /* 39393 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14230 /* 39396 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14231 /* 39398 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14232 /* 39400 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
14233 /* 39405 */ // GIR_Coverage, 3150,
14234 /* 39405 */ GIR_EraseRootFromParent_Done,
14235 /* 39406 */ // Label 880: @39406
14236 /* 39406 */ GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(39438), // Rule ID 3151 //
14237 /* 39411 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
14238 /* 39414 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14239 /* 39417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14240 /* 39421 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14241 /* 39425 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => QPR:{ *:[v16i8] }:$src
14242 /* 39425 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14243 /* 39428 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14244 /* 39430 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14245 /* 39432 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
14246 /* 39437 */ // GIR_Coverage, 3151,
14247 /* 39437 */ GIR_EraseRootFromParent_Done,
14248 /* 39438 */ // Label 881: @39438
14249 /* 39438 */ GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(39470), // Rule ID 3152 //
14250 /* 39443 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
14251 /* 39446 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14252 /* 39449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14253 /* 39453 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14254 /* 39457 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => QPR:{ *:[v16i8] }:$src
14255 /* 39457 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14256 /* 39460 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14257 /* 39462 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14258 /* 39464 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
14259 /* 39469 */ // GIR_Coverage, 3152,
14260 /* 39469 */ GIR_EraseRootFromParent_Done,
14261 /* 39470 */ // Label 882: @39470
14262 /* 39470 */ GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(39502), // Rule ID 3153 //
14263 /* 39475 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsLE),
14264 /* 39478 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14265 /* 39481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14266 /* 39485 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14267 /* 39489 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => QPR:{ *:[v16i8] }:$src
14268 /* 39489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14269 /* 39492 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14270 /* 39494 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14271 /* 39496 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::QPRRegClassID),
14272 /* 39501 */ // GIR_Coverage, 3153,
14273 /* 39501 */ GIR_EraseRootFromParent_Done,
14274 /* 39502 */ // Label 883: @39502
14275 /* 39502 */ GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(39539), // Rule ID 3220 //
14276 /* 39507 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14277 /* 39510 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14278 /* 39513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14279 /* 39517 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14280 /* 39521 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2f64] }:$src)
14281 /* 39521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
14282 /* 39524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14283 /* 39526 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14284 /* 39528 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14285 /* 39531 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14286 /* 39537 */ GIR_RootConstrainSelectedInstOperands,
14287 /* 39538 */ // GIR_Coverage, 3220,
14288 /* 39538 */ GIR_EraseRootFromParent_Done,
14289 /* 39539 */ // Label 884: @39539
14290 /* 39539 */ GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(39576), // Rule ID 3221 //
14291 /* 39544 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14292 /* 39547 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14293 /* 39550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14294 /* 39554 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14295 /* 39558 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src) => (VREV64q8:{ *:[v16i8] } QPR:{ *:[v2i64] }:$src)
14296 /* 39558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV64q8),
14297 /* 39561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14298 /* 39563 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14299 /* 39565 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14300 /* 39568 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14301 /* 39574 */ GIR_RootConstrainSelectedInstOperands,
14302 /* 39575 */ // GIR_Coverage, 3221,
14303 /* 39575 */ GIR_EraseRootFromParent_Done,
14304 /* 39576 */ // Label 885: @39576
14305 /* 39576 */ GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(39613), // Rule ID 3222 //
14306 /* 39581 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14307 /* 39584 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14308 /* 39587 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14309 /* 39591 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14310 /* 39595 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4f32] }:$src)
14311 /* 39595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
14312 /* 39598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14313 /* 39600 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14314 /* 39602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14315 /* 39605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14316 /* 39611 */ GIR_RootConstrainSelectedInstOperands,
14317 /* 39612 */ // GIR_Coverage, 3222,
14318 /* 39612 */ GIR_EraseRootFromParent_Done,
14319 /* 39613 */ // Label 886: @39613
14320 /* 39613 */ GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(39650), // Rule ID 3223 //
14321 /* 39618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14322 /* 39621 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14323 /* 39624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14324 /* 39628 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14325 /* 39632 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src) => (VREV32q8:{ *:[v16i8] } QPR:{ *:[v4i32] }:$src)
14326 /* 39632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV32q8),
14327 /* 39635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14328 /* 39637 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14329 /* 39639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14330 /* 39642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14331 /* 39648 */ GIR_RootConstrainSelectedInstOperands,
14332 /* 39649 */ // GIR_Coverage, 3223,
14333 /* 39649 */ GIR_EraseRootFromParent_Done,
14334 /* 39650 */ // Label 887: @39650
14335 /* 39650 */ GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(39687), // Rule ID 3224 //
14336 /* 39655 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14337 /* 39658 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14338 /* 39661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14339 /* 39665 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14340 /* 39669 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8f16] }:$src)
14341 /* 39669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
14342 /* 39672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14343 /* 39674 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14344 /* 39676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14345 /* 39679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14346 /* 39685 */ GIR_RootConstrainSelectedInstOperands,
14347 /* 39686 */ // GIR_Coverage, 3224,
14348 /* 39686 */ GIR_EraseRootFromParent_Done,
14349 /* 39687 */ // Label 888: @39687
14350 /* 39687 */ GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(39724), // Rule ID 3225 //
14351 /* 39692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_IsBE),
14352 /* 39695 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14353 /* 39698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14354 /* 39702 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14355 /* 39706 */ // (bitconvert:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src) => (VREV16q8:{ *:[v16i8] } QPR:{ *:[v8i16] }:$src)
14356 /* 39706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VREV16q8),
14357 /* 39709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
14358 /* 39711 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14359 /* 39713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14360 /* 39716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14361 /* 39722 */ GIR_RootConstrainSelectedInstOperands,
14362 /* 39723 */ // GIR_Coverage, 3225,
14363 /* 39723 */ GIR_EraseRootFromParent_Done,
14364 /* 39724 */ // Label 889: @39724
14365 /* 39724 */ GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(39756), // Rule ID 5797 //
14366 /* 39729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14367 /* 39732 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14368 /* 39735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14369 /* 39739 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14370 /* 39743 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => MQPR:{ *:[v16i8] }:$src
14371 /* 39743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14372 /* 39746 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14373 /* 39748 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14374 /* 39750 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14375 /* 39755 */ // GIR_Coverage, 5797,
14376 /* 39755 */ GIR_EraseRootFromParent_Done,
14377 /* 39756 */ // Label 890: @39756
14378 /* 39756 */ GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(39788), // Rule ID 5798 //
14379 /* 39761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14380 /* 39764 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14381 /* 39767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14382 /* 39771 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14383 /* 39775 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => MQPR:{ *:[v16i8] }:$src
14384 /* 39775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14385 /* 39778 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14386 /* 39780 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14387 /* 39782 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14388 /* 39787 */ // GIR_Coverage, 5798,
14389 /* 39787 */ GIR_EraseRootFromParent_Done,
14390 /* 39788 */ // Label 891: @39788
14391 /* 39788 */ GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(39820), // Rule ID 5799 //
14392 /* 39793 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14393 /* 39796 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14394 /* 39799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14395 /* 39803 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14396 /* 39807 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => MQPR:{ *:[v16i8] }:$src
14397 /* 39807 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14398 /* 39810 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14399 /* 39812 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14400 /* 39814 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14401 /* 39819 */ // GIR_Coverage, 5799,
14402 /* 39819 */ GIR_EraseRootFromParent_Done,
14403 /* 39820 */ // Label 892: @39820
14404 /* 39820 */ GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(39852), // Rule ID 5800 //
14405 /* 39825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14406 /* 39828 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14407 /* 39831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14408 /* 39835 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14409 /* 39839 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => MQPR:{ *:[v16i8] }:$src
14410 /* 39839 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14411 /* 39842 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14412 /* 39844 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14413 /* 39846 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14414 /* 39851 */ // GIR_Coverage, 5800,
14415 /* 39851 */ GIR_EraseRootFromParent_Done,
14416 /* 39852 */ // Label 893: @39852
14417 /* 39852 */ GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(39884), // Rule ID 5801 //
14418 /* 39857 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14419 /* 39860 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14420 /* 39863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14421 /* 39867 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14422 /* 39871 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => MQPR:{ *:[v16i8] }:$src
14423 /* 39871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14424 /* 39874 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14425 /* 39876 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14426 /* 39878 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14427 /* 39883 */ // GIR_Coverage, 5801,
14428 /* 39883 */ GIR_EraseRootFromParent_Done,
14429 /* 39884 */ // Label 894: @39884
14430 /* 39884 */ GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(39916), // Rule ID 5802 //
14431 /* 39889 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsLE),
14432 /* 39892 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14433 /* 39895 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14434 /* 39899 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14435 /* 39903 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => MQPR:{ *:[v16i8] }:$src
14436 /* 39903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
14437 /* 39906 */ GIR_RootToRootCopy, /*OpIdx*/0, // dst
14438 /* 39908 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14439 /* 39910 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::MQPRRegClassID),
14440 /* 39915 */ // GIR_Coverage, 5802,
14441 /* 39915 */ GIR_EraseRootFromParent_Done,
14442 /* 39916 */ // Label 895: @39916
14443 /* 39916 */ GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(39974), // Rule ID 5833 //
14444 /* 39921 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14445 /* 39924 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14446 /* 39927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14447 /* 39931 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14448 /* 39935 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2f64] }:$src)
14449 /* 39935 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14450 /* 39938 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14451 /* 39942 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14452 /* 39947 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
14453 /* 39950 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14454 /* 39952 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14455 /* 39954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14456 /* 39957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14457 /* 39963 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14458 /* 39969 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14459 /* 39972 */ GIR_RootConstrainSelectedInstOperands,
14460 /* 39973 */ // GIR_Coverage, 5833,
14461 /* 39973 */ GIR_EraseRootFromParent_Done,
14462 /* 39974 */ // Label 896: @39974
14463 /* 39974 */ GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(40032), // Rule ID 5834 //
14464 /* 39979 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14465 /* 39982 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
14466 /* 39985 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14467 /* 39989 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14468 /* 39993 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src) => (MVE_VREV64_8:{ *:[v16i8] } MQPR:{ *:[v2i64] }:$src)
14469 /* 39993 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14470 /* 39996 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14471 /* 40000 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14472 /* 40005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV64_8),
14473 /* 40008 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14474 /* 40010 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14475 /* 40012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14476 /* 40015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14477 /* 40021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14478 /* 40027 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14479 /* 40030 */ GIR_RootConstrainSelectedInstOperands,
14480 /* 40031 */ // GIR_Coverage, 5834,
14481 /* 40031 */ GIR_EraseRootFromParent_Done,
14482 /* 40032 */ // Label 897: @40032
14483 /* 40032 */ GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(40090), // Rule ID 5835 //
14484 /* 40037 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14485 /* 40040 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14486 /* 40043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14487 /* 40047 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14488 /* 40051 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4f32] }:$src)
14489 /* 40051 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14490 /* 40054 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14491 /* 40058 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14492 /* 40063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
14493 /* 40066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14494 /* 40068 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14495 /* 40070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14496 /* 40073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14497 /* 40079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14498 /* 40085 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14499 /* 40088 */ GIR_RootConstrainSelectedInstOperands,
14500 /* 40089 */ // GIR_Coverage, 5835,
14501 /* 40089 */ GIR_EraseRootFromParent_Done,
14502 /* 40090 */ // Label 898: @40090
14503 /* 40090 */ GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(40148), // Rule ID 5836 //
14504 /* 40095 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14505 /* 40098 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14506 /* 40101 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14507 /* 40105 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14508 /* 40109 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src)
14509 /* 40109 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14510 /* 40112 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14511 /* 40116 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14512 /* 40121 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
14513 /* 40124 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14514 /* 40126 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14515 /* 40128 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14516 /* 40131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14517 /* 40137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14518 /* 40143 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14519 /* 40146 */ GIR_RootConstrainSelectedInstOperands,
14520 /* 40147 */ // GIR_Coverage, 5836,
14521 /* 40147 */ GIR_EraseRootFromParent_Done,
14522 /* 40148 */ // Label 899: @40148
14523 /* 40148 */ GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(40206), // Rule ID 5837 //
14524 /* 40153 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14525 /* 40156 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14526 /* 40159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14527 /* 40163 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14528 /* 40167 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8f16] }:$src)
14529 /* 40167 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14530 /* 40170 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14531 /* 40174 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14532 /* 40179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
14533 /* 40182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14534 /* 40184 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14535 /* 40186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14536 /* 40189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14537 /* 40195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14538 /* 40201 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14539 /* 40204 */ GIR_RootConstrainSelectedInstOperands,
14540 /* 40205 */ // GIR_Coverage, 5837,
14541 /* 40205 */ GIR_EraseRootFromParent_Done,
14542 /* 40206 */ // Label 900: @40206
14543 /* 40206 */ GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(40264), // Rule ID 5838 //
14544 /* 40211 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_IsBE),
14545 /* 40214 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14546 /* 40217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14547 /* 40221 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14548 /* 40225 */ // (bitconvert:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v16i8] } MQPR:{ *:[v8i16] }:$src)
14549 /* 40225 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14550 /* 40228 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14551 /* 40232 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14552 /* 40237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
14553 /* 40240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14554 /* 40242 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
14555 /* 40244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14556 /* 40247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14557 /* 40253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14558 /* 40259 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14559 /* 40262 */ GIR_RootConstrainSelectedInstOperands,
14560 /* 40263 */ // GIR_Coverage, 5838,
14561 /* 40263 */ GIR_EraseRootFromParent_Done,
14562 /* 40264 */ // Label 901: @40264
14563 /* 40264 */ GIM_Reject,
14564 /* 40265 */ // Label 663: @40265
14565 /* 40265 */ GIM_Reject,
14566 /* 40266 */ // Label 16: @40266
14567 /* 40266 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 909*/ GIMT_Encode4(40673),
14568 /* 40277 */ /*GILLT_s16*//*Label 902*/ GIMT_Encode4(40329),
14569 /* 40281 */ /*GILLT_s32*//*Label 903*/ GIMT_Encode4(40367),
14570 /* 40285 */ /*GILLT_s64*//*Label 904*/ GIMT_Encode4(40405), GIMT_Encode4(0),
14571 /* 40293 */ /*GILLT_v2s32*//*Label 905*/ GIMT_Encode4(40443), GIMT_Encode4(0), GIMT_Encode4(0),
14572 /* 40305 */ /*GILLT_v4s16*//*Label 906*/ GIMT_Encode4(40470),
14573 /* 40309 */ /*GILLT_v4s32*//*Label 907*/ GIMT_Encode4(40497), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
14574 /* 40325 */ /*GILLT_v8s16*//*Label 908*/ GIMT_Encode4(40585),
14575 /* 40329 */ // Label 902: @40329
14576 /* 40329 */ GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(40366), // Rule ID 692 //
14577 /* 40334 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
14578 /* 40337 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
14579 /* 40340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
14580 /* 40344 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
14581 /* 40348 */ // (ftrunc:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTZH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
14582 /* 40348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZH),
14583 /* 40351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
14584 /* 40353 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
14585 /* 40355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14586 /* 40358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14587 /* 40364 */ GIR_RootConstrainSelectedInstOperands,
14588 /* 40365 */ // GIR_Coverage, 692,
14589 /* 40365 */ GIR_EraseRootFromParent_Done,
14590 /* 40366 */ // Label 910: @40366
14591 /* 40366 */ GIM_Reject,
14592 /* 40367 */ // Label 903: @40367
14593 /* 40367 */ GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(40404), // Rule ID 694 //
14594 /* 40372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
14595 /* 40375 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14596 /* 40378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14597 /* 40382 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14598 /* 40386 */ // (ftrunc:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTZS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14599 /* 40386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZS),
14600 /* 40389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
14601 /* 40391 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
14602 /* 40393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14603 /* 40396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14604 /* 40402 */ GIR_RootConstrainSelectedInstOperands,
14605 /* 40403 */ // GIR_Coverage, 694,
14606 /* 40403 */ GIR_EraseRootFromParent_Done,
14607 /* 40404 */ // Label 911: @40404
14608 /* 40404 */ GIM_Reject,
14609 /* 40405 */ // Label 904: @40405
14610 /* 40405 */ GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(40442), // Rule ID 696 //
14611 /* 40410 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
14612 /* 40413 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
14613 /* 40416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14614 /* 40420 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14615 /* 40424 */ // (ftrunc:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTZD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
14616 /* 40424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTZD),
14617 /* 40427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
14618 /* 40429 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
14619 /* 40431 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
14620 /* 40434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14621 /* 40440 */ GIR_RootConstrainSelectedInstOperands,
14622 /* 40441 */ // GIR_Coverage, 696,
14623 /* 40441 */ GIR_EraseRootFromParent_Done,
14624 /* 40442 */ // Label 912: @40442
14625 /* 40442 */ GIM_Reject,
14626 /* 40443 */ // Label 905: @40443
14627 /* 40443 */ GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(40469), // Rule ID 1864 //
14628 /* 40448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
14629 /* 40451 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
14630 /* 40454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14631 /* 40458 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14632 /* 40462 */ // (ftrunc:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTZNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14633 /* 40462 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDf),
14634 /* 40467 */ GIR_RootConstrainSelectedInstOperands,
14635 /* 40468 */ // GIR_Coverage, 1864,
14636 /* 40468 */ GIR_Done,
14637 /* 40469 */ // Label 913: @40469
14638 /* 40469 */ GIM_Reject,
14639 /* 40470 */ // Label 906: @40470
14640 /* 40470 */ GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(40496), // Rule ID 1866 //
14641 /* 40475 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
14642 /* 40478 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
14643 /* 40481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14644 /* 40485 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14645 /* 40489 */ // (ftrunc:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTZNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
14646 /* 40489 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNDh),
14647 /* 40494 */ GIR_RootConstrainSelectedInstOperands,
14648 /* 40495 */ // GIR_Coverage, 1866,
14649 /* 40495 */ GIR_Done,
14650 /* 40496 */ // Label 914: @40496
14651 /* 40496 */ GIM_Reject,
14652 /* 40497 */ // Label 907: @40497
14653 /* 40497 */ GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(40584),
14654 /* 40502 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14655 /* 40505 */ GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(40528), // Rule ID 1865 //
14656 /* 40510 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
14657 /* 40513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14658 /* 40517 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14659 /* 40521 */ // (ftrunc:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTZNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14660 /* 40521 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQf),
14661 /* 40526 */ GIR_RootConstrainSelectedInstOperands,
14662 /* 40527 */ // GIR_Coverage, 1865,
14663 /* 40527 */ GIR_Done,
14664 /* 40528 */ // Label 916: @40528
14665 /* 40528 */ GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(40583), // Rule ID 4349 //
14666 /* 40533 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
14667 /* 40536 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14668 /* 40540 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14669 /* 40544 */ // (ftrunc:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
14670 /* 40544 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14671 /* 40547 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14672 /* 40551 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14673 /* 40556 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z),
14674 /* 40559 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14675 /* 40561 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
14676 /* 40563 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14677 /* 40566 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14678 /* 40572 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14679 /* 40578 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14680 /* 40581 */ GIR_RootConstrainSelectedInstOperands,
14681 /* 40582 */ // GIR_Coverage, 4349,
14682 /* 40582 */ GIR_EraseRootFromParent_Done,
14683 /* 40583 */ // Label 917: @40583
14684 /* 40583 */ GIM_Reject,
14685 /* 40584 */ // Label 915: @40584
14686 /* 40584 */ GIM_Reject,
14687 /* 40585 */ // Label 908: @40585
14688 /* 40585 */ GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(40672),
14689 /* 40590 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14690 /* 40593 */ GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(40616), // Rule ID 1867 //
14691 /* 40598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
14692 /* 40601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14693 /* 40605 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14694 /* 40609 */ // (ftrunc:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTZNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
14695 /* 40609 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTZNQh),
14696 /* 40614 */ GIR_RootConstrainSelectedInstOperands,
14697 /* 40615 */ // GIR_Coverage, 1867,
14698 /* 40615 */ GIR_Done,
14699 /* 40616 */ // Label 919: @40616
14700 /* 40616 */ GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(40671), // Rule ID 4331 //
14701 /* 40621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
14702 /* 40624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14703 /* 40628 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14704 /* 40632 */ // (ftrunc:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
14705 /* 40632 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14706 /* 40635 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14707 /* 40639 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14708 /* 40644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z),
14709 /* 40647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14710 /* 40649 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
14711 /* 40651 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14712 /* 40654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14713 /* 40660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14714 /* 40666 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14715 /* 40669 */ GIR_RootConstrainSelectedInstOperands,
14716 /* 40670 */ // GIR_Coverage, 4331,
14717 /* 40670 */ GIR_EraseRootFromParent_Done,
14718 /* 40671 */ // Label 920: @40671
14719 /* 40671 */ GIM_Reject,
14720 /* 40672 */ // Label 918: @40672
14721 /* 40672 */ GIM_Reject,
14722 /* 40673 */ // Label 909: @40673
14723 /* 40673 */ GIM_Reject,
14724 /* 40674 */ // Label 17: @40674
14725 /* 40674 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 928*/ GIMT_Encode4(41048),
14726 /* 40685 */ /*GILLT_s16*//*Label 921*/ GIMT_Encode4(40737),
14727 /* 40689 */ /*GILLT_s32*//*Label 922*/ GIMT_Encode4(40764),
14728 /* 40693 */ /*GILLT_s64*//*Label 923*/ GIMT_Encode4(40791), GIMT_Encode4(0),
14729 /* 40701 */ /*GILLT_v2s32*//*Label 924*/ GIMT_Encode4(40818), GIMT_Encode4(0), GIMT_Encode4(0),
14730 /* 40713 */ /*GILLT_v4s16*//*Label 925*/ GIMT_Encode4(40845),
14731 /* 40717 */ /*GILLT_v4s32*//*Label 926*/ GIMT_Encode4(40872), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
14732 /* 40733 */ /*GILLT_v8s16*//*Label 927*/ GIMT_Encode4(40960),
14733 /* 40737 */ // Label 921: @40737
14734 /* 40737 */ GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(40763), // Rule ID 710 //
14735 /* 40742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
14736 /* 40745 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
14737 /* 40748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
14738 /* 40752 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
14739 /* 40756 */ // (fround:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTAH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
14740 /* 40756 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAH),
14741 /* 40761 */ GIR_RootConstrainSelectedInstOperands,
14742 /* 40762 */ // GIR_Coverage, 710,
14743 /* 40762 */ GIR_Done,
14744 /* 40763 */ // Label 929: @40763
14745 /* 40763 */ GIM_Reject,
14746 /* 40764 */ // Label 922: @40764
14747 /* 40764 */ GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(40790), // Rule ID 712 //
14748 /* 40769 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
14749 /* 40772 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14750 /* 40775 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14751 /* 40779 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14752 /* 40783 */ // (fround:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTAS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14753 /* 40783 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAS),
14754 /* 40788 */ GIR_RootConstrainSelectedInstOperands,
14755 /* 40789 */ // GIR_Coverage, 712,
14756 /* 40789 */ GIR_Done,
14757 /* 40790 */ // Label 930: @40790
14758 /* 40790 */ GIM_Reject,
14759 /* 40791 */ // Label 923: @40791
14760 /* 40791 */ GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(40817), // Rule ID 714 //
14761 /* 40796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
14762 /* 40799 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
14763 /* 40802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14764 /* 40806 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14765 /* 40810 */ // (fround:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTAD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
14766 /* 40810 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTAD),
14767 /* 40815 */ GIR_RootConstrainSelectedInstOperands,
14768 /* 40816 */ // GIR_Coverage, 714,
14769 /* 40816 */ GIR_Done,
14770 /* 40817 */ // Label 931: @40817
14771 /* 40817 */ GIM_Reject,
14772 /* 40818 */ // Label 924: @40818
14773 /* 40818 */ GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(40844), // Rule ID 1860 //
14774 /* 40823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
14775 /* 40826 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
14776 /* 40829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14777 /* 40833 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14778 /* 40837 */ // (fround:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTANDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14779 /* 40837 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDf),
14780 /* 40842 */ GIR_RootConstrainSelectedInstOperands,
14781 /* 40843 */ // GIR_Coverage, 1860,
14782 /* 40843 */ GIR_Done,
14783 /* 40844 */ // Label 932: @40844
14784 /* 40844 */ GIM_Reject,
14785 /* 40845 */ // Label 925: @40845
14786 /* 40845 */ GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(40871), // Rule ID 1862 //
14787 /* 40850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
14788 /* 40853 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
14789 /* 40856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14790 /* 40860 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14791 /* 40864 */ // (fround:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTANDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
14792 /* 40864 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANDh),
14793 /* 40869 */ GIR_RootConstrainSelectedInstOperands,
14794 /* 40870 */ // GIR_Coverage, 1862,
14795 /* 40870 */ GIR_Done,
14796 /* 40871 */ // Label 933: @40871
14797 /* 40871 */ GIM_Reject,
14798 /* 40872 */ // Label 926: @40872
14799 /* 40872 */ GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(40959),
14800 /* 40877 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14801 /* 40880 */ GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(40903), // Rule ID 1861 //
14802 /* 40885 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
14803 /* 40888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14804 /* 40892 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14805 /* 40896 */ // (fround:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTANQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14806 /* 40896 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQf),
14807 /* 40901 */ GIR_RootConstrainSelectedInstOperands,
14808 /* 40902 */ // GIR_Coverage, 1861,
14809 /* 40902 */ GIR_Done,
14810 /* 40903 */ // Label 935: @40903
14811 /* 40903 */ GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(40958), // Rule ID 4346 //
14812 /* 40908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
14813 /* 40911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14814 /* 40915 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14815 /* 40919 */ // (fround:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
14816 /* 40919 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14817 /* 40922 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14818 /* 40926 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14819 /* 40931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A),
14820 /* 40934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14821 /* 40936 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
14822 /* 40938 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14823 /* 40941 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14824 /* 40947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14825 /* 40953 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14826 /* 40956 */ GIR_RootConstrainSelectedInstOperands,
14827 /* 40957 */ // GIR_Coverage, 4346,
14828 /* 40957 */ GIR_EraseRootFromParent_Done,
14829 /* 40958 */ // Label 936: @40958
14830 /* 40958 */ GIM_Reject,
14831 /* 40959 */ // Label 934: @40959
14832 /* 40959 */ GIM_Reject,
14833 /* 40960 */ // Label 927: @40960
14834 /* 40960 */ GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(41047),
14835 /* 40965 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14836 /* 40968 */ GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(40991), // Rule ID 1863 //
14837 /* 40973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
14838 /* 40976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14839 /* 40980 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14840 /* 40984 */ // (fround:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTANQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
14841 /* 40984 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTANQh),
14842 /* 40989 */ GIR_RootConstrainSelectedInstOperands,
14843 /* 40990 */ // GIR_Coverage, 1863,
14844 /* 40990 */ GIR_Done,
14845 /* 40991 */ // Label 938: @40991
14846 /* 40991 */ GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(41046), // Rule ID 4328 //
14847 /* 40996 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
14848 /* 40999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14849 /* 41003 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14850 /* 41007 */ // (fround:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
14851 /* 41007 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14852 /* 41010 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14853 /* 41014 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14854 /* 41019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A),
14855 /* 41022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14856 /* 41024 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
14857 /* 41026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14858 /* 41029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14859 /* 41035 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14860 /* 41041 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14861 /* 41044 */ GIR_RootConstrainSelectedInstOperands,
14862 /* 41045 */ // GIR_Coverage, 4328,
14863 /* 41045 */ GIR_EraseRootFromParent_Done,
14864 /* 41046 */ // Label 939: @41046
14865 /* 41046 */ GIM_Reject,
14866 /* 41047 */ // Label 937: @41047
14867 /* 41047 */ GIM_Reject,
14868 /* 41048 */ // Label 928: @41048
14869 /* 41048 */ GIM_Reject,
14870 /* 41049 */ // Label 18: @41049
14871 /* 41049 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 947*/ GIMT_Encode4(41423),
14872 /* 41060 */ /*GILLT_s16*//*Label 940*/ GIMT_Encode4(41112),
14873 /* 41064 */ /*GILLT_s32*//*Label 941*/ GIMT_Encode4(41139),
14874 /* 41068 */ /*GILLT_s64*//*Label 942*/ GIMT_Encode4(41166), GIMT_Encode4(0),
14875 /* 41076 */ /*GILLT_v2s32*//*Label 943*/ GIMT_Encode4(41193), GIMT_Encode4(0), GIMT_Encode4(0),
14876 /* 41088 */ /*GILLT_v4s16*//*Label 944*/ GIMT_Encode4(41220),
14877 /* 41092 */ /*GILLT_v4s32*//*Label 945*/ GIMT_Encode4(41247), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
14878 /* 41108 */ /*GILLT_v8s16*//*Label 946*/ GIMT_Encode4(41335),
14879 /* 41112 */ // Label 940: @41112
14880 /* 41112 */ GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(41138), // Rule ID 716 //
14881 /* 41117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
14882 /* 41120 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
14883 /* 41123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
14884 /* 41127 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
14885 /* 41131 */ // (froundeven:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTNH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
14886 /* 41131 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNH),
14887 /* 41136 */ GIR_RootConstrainSelectedInstOperands,
14888 /* 41137 */ // GIR_Coverage, 716,
14889 /* 41137 */ GIR_Done,
14890 /* 41138 */ // Label 948: @41138
14891 /* 41138 */ GIM_Reject,
14892 /* 41139 */ // Label 941: @41139
14893 /* 41139 */ GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(41165), // Rule ID 718 //
14894 /* 41144 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
14895 /* 41147 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
14896 /* 41150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14897 /* 41154 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
14898 /* 41158 */ // (froundeven:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTNS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
14899 /* 41158 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNS),
14900 /* 41163 */ GIR_RootConstrainSelectedInstOperands,
14901 /* 41164 */ // GIR_Coverage, 718,
14902 /* 41164 */ GIR_Done,
14903 /* 41165 */ // Label 949: @41165
14904 /* 41165 */ GIM_Reject,
14905 /* 41166 */ // Label 942: @41166
14906 /* 41166 */ GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(41192), // Rule ID 720 //
14907 /* 41171 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
14908 /* 41174 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
14909 /* 41177 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14910 /* 41181 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14911 /* 41185 */ // (froundeven:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTND:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
14912 /* 41185 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTND),
14913 /* 41190 */ GIR_RootConstrainSelectedInstOperands,
14914 /* 41191 */ // GIR_Coverage, 720,
14915 /* 41191 */ GIR_Done,
14916 /* 41192 */ // Label 950: @41192
14917 /* 41192 */ GIM_Reject,
14918 /* 41193 */ // Label 943: @41193
14919 /* 41193 */ GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(41219), // Rule ID 1852 //
14920 /* 41198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
14921 /* 41201 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
14922 /* 41204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14923 /* 41208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14924 /* 41212 */ // (froundeven:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTNNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
14925 /* 41212 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDf),
14926 /* 41217 */ GIR_RootConstrainSelectedInstOperands,
14927 /* 41218 */ // GIR_Coverage, 1852,
14928 /* 41218 */ GIR_Done,
14929 /* 41219 */ // Label 951: @41219
14930 /* 41219 */ GIM_Reject,
14931 /* 41220 */ // Label 944: @41220
14932 /* 41220 */ GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(41246), // Rule ID 1854 //
14933 /* 41225 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
14934 /* 41228 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
14935 /* 41231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14936 /* 41235 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
14937 /* 41239 */ // (froundeven:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTNNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
14938 /* 41239 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNDh),
14939 /* 41244 */ GIR_RootConstrainSelectedInstOperands,
14940 /* 41245 */ // GIR_Coverage, 1854,
14941 /* 41245 */ GIR_Done,
14942 /* 41246 */ // Label 952: @41246
14943 /* 41246 */ GIM_Reject,
14944 /* 41247 */ // Label 945: @41247
14945 /* 41247 */ GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(41334),
14946 /* 41252 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
14947 /* 41255 */ GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(41278), // Rule ID 1853 //
14948 /* 41260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
14949 /* 41263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14950 /* 41267 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14951 /* 41271 */ // (froundeven:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTNNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
14952 /* 41271 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQf),
14953 /* 41276 */ GIR_RootConstrainSelectedInstOperands,
14954 /* 41277 */ // GIR_Coverage, 1853,
14955 /* 41277 */ GIR_Done,
14956 /* 41278 */ // Label 954: @41278
14957 /* 41278 */ GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(41333), // Rule ID 4340 //
14958 /* 41283 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
14959 /* 41286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14960 /* 41290 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14961 /* 41294 */ // (froundeven:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
14962 /* 41294 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14963 /* 41297 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14964 /* 41301 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
14965 /* 41306 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N),
14966 /* 41309 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
14967 /* 41311 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
14968 /* 41313 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
14969 /* 41316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14970 /* 41322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
14971 /* 41328 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
14972 /* 41331 */ GIR_RootConstrainSelectedInstOperands,
14973 /* 41332 */ // GIR_Coverage, 4340,
14974 /* 41332 */ GIR_EraseRootFromParent_Done,
14975 /* 41333 */ // Label 955: @41333
14976 /* 41333 */ GIM_Reject,
14977 /* 41334 */ // Label 953: @41334
14978 /* 41334 */ GIM_Reject,
14979 /* 41335 */ // Label 946: @41335
14980 /* 41335 */ GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(41422),
14981 /* 41340 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
14982 /* 41343 */ GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(41366), // Rule ID 1855 //
14983 /* 41348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
14984 /* 41351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14985 /* 41355 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
14986 /* 41359 */ // (froundeven:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTNNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
14987 /* 41359 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTNNQh),
14988 /* 41364 */ GIR_RootConstrainSelectedInstOperands,
14989 /* 41365 */ // GIR_Coverage, 1855,
14990 /* 41365 */ GIR_Done,
14991 /* 41366 */ // Label 957: @41366
14992 /* 41366 */ GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(41421), // Rule ID 4322 //
14993 /* 41371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
14994 /* 41374 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14995 /* 41378 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
14996 /* 41382 */ // (froundeven:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
14997 /* 41382 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
14998 /* 41385 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
14999 /* 41389 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15000 /* 41394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N),
15001 /* 41397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
15002 /* 41399 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
15003 /* 41401 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15004 /* 41404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15005 /* 41410 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15006 /* 41416 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15007 /* 41419 */ GIR_RootConstrainSelectedInstOperands,
15008 /* 41420 */ // GIR_Coverage, 4322,
15009 /* 41420 */ GIR_EraseRootFromParent_Done,
15010 /* 41421 */ // Label 958: @41421
15011 /* 41421 */ GIM_Reject,
15012 /* 41422 */ // Label 956: @41422
15013 /* 41422 */ GIM_Reject,
15014 /* 41423 */ // Label 947: @41423
15015 /* 41423 */ GIM_Reject,
15016 /* 41424 */ // Label 19: @41424
15017 /* 41424 */ GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(41586),
15018 /* 41429 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15019 /* 41432 */ GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic,
15020 /* 41435 */ GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(41510), // Rule ID 2214 //
15021 /* 41440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
15022 /* 41443 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1),
15023 /* 41450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
15024 /* 41454 */ // MIs[0] Rn
15025 /* 41454 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
15026 /* 41458 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
15027 /* 41462 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>> => (tLDRSB:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
15028 /* 41462 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15029 /* 41465 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
15030 /* 41469 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15031 /* 41474 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
15032 /* 41480 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
15033 /* 41483 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
15034 /* 41486 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15035 /* 41492 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15036 /* 41494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSB),
15037 /* 41497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
15038 /* 41499 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
15039 /* 41501 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15040 /* 41504 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15041 /* 41508 */ GIR_RootConstrainSelectedInstOperands,
15042 /* 41509 */ // GIR_Coverage, 2214,
15043 /* 41509 */ GIR_EraseRootFromParent_Done,
15044 /* 41510 */ // Label 960: @41510
15045 /* 41510 */ GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(41585), // Rule ID 2215 //
15046 /* 41515 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
15047 /* 41518 */ GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2),
15048 /* 41525 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
15049 /* 41529 */ // MIs[0] Rn
15050 /* 41529 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
15051 /* 41533 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
15052 /* 41537 */ // (ld:{ *:[i32] } tGPR:{ *:[i32] }:$Rn)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>> => (tLDRSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
15053 /* 41537 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
15054 /* 41540 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
15055 /* 41544 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
15056 /* 41549 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
15057 /* 41555 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
15058 /* 41558 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
15059 /* 41561 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15060 /* 41567 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
15061 /* 41569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLDRSH),
15062 /* 41572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
15063 /* 41574 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
15064 /* 41576 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
15065 /* 41579 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
15066 /* 41583 */ GIR_RootConstrainSelectedInstOperands,
15067 /* 41584 */ // GIR_Coverage, 2215,
15068 /* 41584 */ GIR_EraseRootFromParent_Done,
15069 /* 41585 */ // Label 961: @41585
15070 /* 41585 */ GIM_Reject,
15071 /* 41586 */ // Label 959: @41586
15072 /* 41586 */ GIM_Reject,
15073 /* 41587 */ // Label 20: @41587
15074 /* 41587 */ GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(41607), // Rule ID 5899 //
15075 /* 41592 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
15076 /* 41595 */ // MIs[0] Operand 0
15077 /* 41595 */ GIM_CheckIsImm, /*MI*/0, /*Op*/0,
15078 /* 41598 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0,
15079 /* 41602 */ // (atomic_fence (timm:{ *:[i32] }), 0:{ *:[i32] }) => (MEMBARRIER)
15080 /* 41602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::MEMBARRIER),
15081 /* 41605 */ GIR_RootConstrainSelectedInstOperands,
15082 /* 41606 */ // GIR_Coverage, 5899,
15083 /* 41606 */ GIR_EraseRootFromParent_Done,
15084 /* 41607 */ // Label 962: @41607
15085 /* 41607 */ GIM_Reject,
15086 /* 41608 */ // Label 21: @41608
15087 /* 41608 */ GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(47111),
15088 /* 41613 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
15089 /* 41616 */ GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(41664), // Rule ID 2017 //
15090 /* 41621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
15091 /* 41624 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16),
15092 /* 41629 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15093 /* 41632 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15094 /* 41635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
15095 /* 41639 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
15096 /* 41643 */ // (intrinsic_wo_chain:{ *:[i32] } 4186:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (UXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
15097 /* 41643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTB16),
15098 /* 41646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
15099 /* 41648 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src
15100 /* 41650 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15101 /* 41653 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15102 /* 41656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15103 /* 41662 */ GIR_RootConstrainSelectedInstOperands,
15104 /* 41663 */ // GIR_Coverage, 2017,
15105 /* 41663 */ GIR_EraseRootFromParent_Done,
15106 /* 41664 */ // Label 964: @41664
15107 /* 41664 */ GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(41712), // Rule ID 2271 //
15108 /* 41669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
15109 /* 41672 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtb16),
15110 /* 41677 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15111 /* 41680 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15112 /* 41683 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
15113 /* 41687 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
15114 /* 41691 */ // (intrinsic_wo_chain:{ *:[i32] } 4186:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm) => (t2UXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
15115 /* 41691 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTB16),
15116 /* 41694 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
15117 /* 41696 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
15118 /* 41698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
15119 /* 41701 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15120 /* 41704 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15121 /* 41710 */ GIR_RootConstrainSelectedInstOperands,
15122 /* 41711 */ // GIR_Coverage, 2271,
15123 /* 41711 */ GIR_EraseRootFromParent_Done,
15124 /* 41712 */ // Label 965: @41712
15125 /* 41712 */ GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(41757), // Rule ID 743 //
15126 /* 41717 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
15127 /* 41720 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr),
15128 /* 41725 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15129 /* 41728 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
15130 /* 41731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
15131 /* 41735 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15132 /* 41739 */ // (intrinsic_wo_chain:{ *:[f32] } 4187:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOSIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
15133 /* 41739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRD),
15134 /* 41742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
15135 /* 41744 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
15136 /* 41746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15137 /* 41749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15138 /* 41755 */ GIR_RootConstrainSelectedInstOperands,
15139 /* 41756 */ // GIR_Coverage, 743,
15140 /* 41756 */ GIR_EraseRootFromParent_Done,
15141 /* 41757 */ // Label 966: @41757
15142 /* 41757 */ GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(41802), // Rule ID 744 //
15143 /* 41762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
15144 /* 41765 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtr),
15145 /* 41770 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15146 /* 41773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15147 /* 41776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
15148 /* 41780 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
15149 /* 41784 */ // (intrinsic_wo_chain:{ *:[f32] } 4187:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOSIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
15150 /* 41784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOSIRS),
15151 /* 41787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
15152 /* 41789 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
15153 /* 41791 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15154 /* 41794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15155 /* 41800 */ GIR_RootConstrainSelectedInstOperands,
15156 /* 41801 */ // GIR_Coverage, 744,
15157 /* 41801 */ GIR_EraseRootFromParent_Done,
15158 /* 41802 */ // Label 967: @41802
15159 /* 41802 */ GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(41847), // Rule ID 745 //
15160 /* 41807 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
15161 /* 41810 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru),
15162 /* 41815 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15163 /* 41818 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
15164 /* 41821 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
15165 /* 41825 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15166 /* 41829 */ // (intrinsic_wo_chain:{ *:[f32] } 4188:{ *:[iPTR] }, DPR:{ *:[f64] }:$Dm) => (VTOUIRD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
15167 /* 41829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRD),
15168 /* 41832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
15169 /* 41834 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
15170 /* 41836 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15171 /* 41839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15172 /* 41845 */ GIR_RootConstrainSelectedInstOperands,
15173 /* 41846 */ // GIR_Coverage, 745,
15174 /* 41846 */ GIR_EraseRootFromParent_Done,
15175 /* 41847 */ // Label 968: @41847
15176 /* 41847 */ GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(41892), // Rule ID 746 //
15177 /* 41852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
15178 /* 41855 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_vcvtru),
15179 /* 41860 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
15180 /* 41863 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
15181 /* 41866 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
15182 /* 41870 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
15183 /* 41874 */ // (intrinsic_wo_chain:{ *:[f32] } 4188:{ *:[iPTR] }, SPR:{ *:[f32] }:$Sm) => (VTOUIRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
15184 /* 41874 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTOUIRS),
15185 /* 41877 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
15186 /* 41879 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
15187 /* 41881 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15188 /* 41884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15189 /* 41890 */ GIR_RootConstrainSelectedInstOperands,
15190 /* 41891 */ // GIR_Coverage, 746,
15191 /* 41891 */ GIR_EraseRootFromParent_Done,
15192 /* 41892 */ // Label 969: @41892
15193 /* 41892 */ GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(41937), // Rule ID 1403 //
15194 /* 41897 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15195 /* 41900 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
15196 /* 41905 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15197 /* 41908 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
15198 /* 41911 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15199 /* 41915 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15200 /* 41919 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4044:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLsv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
15201 /* 41919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i8),
15202 /* 41922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15203 /* 41924 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15204 /* 41926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15205 /* 41929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15206 /* 41935 */ GIR_RootConstrainSelectedInstOperands,
15207 /* 41936 */ // GIR_Coverage, 1403,
15208 /* 41936 */ GIR_EraseRootFromParent_Done,
15209 /* 41937 */ // Label 970: @41937
15210 /* 41937 */ GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(41982), // Rule ID 1404 //
15211 /* 41942 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15212 /* 41945 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
15213 /* 41950 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15214 /* 41953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15215 /* 41956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15216 /* 41960 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15217 /* 41964 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4044:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLsv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
15218 /* 41964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i16),
15219 /* 41967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15220 /* 41969 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15221 /* 41971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15222 /* 41974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15223 /* 41980 */ GIR_RootConstrainSelectedInstOperands,
15224 /* 41981 */ // GIR_Coverage, 1404,
15225 /* 41981 */ GIR_EraseRootFromParent_Done,
15226 /* 41982 */ // Label 971: @41982
15227 /* 41982 */ GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(42027), // Rule ID 1405 //
15228 /* 41987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15229 /* 41990 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
15230 /* 41995 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
15231 /* 41998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15232 /* 42001 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15233 /* 42005 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15234 /* 42009 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4044:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLsv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
15235 /* 42009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv2i32),
15236 /* 42012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15237 /* 42014 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15238 /* 42016 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15239 /* 42019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15240 /* 42025 */ GIR_RootConstrainSelectedInstOperands,
15241 /* 42026 */ // GIR_Coverage, 1405,
15242 /* 42026 */ GIR_EraseRootFromParent_Done,
15243 /* 42027 */ // Label 972: @42027
15244 /* 42027 */ GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(42072), // Rule ID 1406 //
15245 /* 42032 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15246 /* 42035 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
15247 /* 42040 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15248 /* 42043 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15249 /* 42046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15250 /* 42050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15251 /* 42054 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4044:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLsv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
15252 /* 42054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv16i8),
15253 /* 42057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15254 /* 42059 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15255 /* 42061 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15256 /* 42064 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15257 /* 42070 */ GIR_RootConstrainSelectedInstOperands,
15258 /* 42071 */ // GIR_Coverage, 1406,
15259 /* 42071 */ GIR_EraseRootFromParent_Done,
15260 /* 42072 */ // Label 973: @42072
15261 /* 42072 */ GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(42117), // Rule ID 1407 //
15262 /* 42077 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15263 /* 42080 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
15264 /* 42085 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15265 /* 42088 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15266 /* 42091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15267 /* 42095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15268 /* 42099 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4044:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLsv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
15269 /* 42099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv8i16),
15270 /* 42102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15271 /* 42104 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15272 /* 42106 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15273 /* 42109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15274 /* 42115 */ GIR_RootConstrainSelectedInstOperands,
15275 /* 42116 */ // GIR_Coverage, 1407,
15276 /* 42116 */ GIR_EraseRootFromParent_Done,
15277 /* 42117 */ // Label 974: @42117
15278 /* 42117 */ GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(42162), // Rule ID 1408 //
15279 /* 42122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15280 /* 42125 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddls),
15281 /* 42130 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
15282 /* 42133 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15283 /* 42136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15284 /* 42140 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15285 /* 42144 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4044:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLsv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
15286 /* 42144 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLsv4i32),
15287 /* 42147 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15288 /* 42149 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15289 /* 42151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15290 /* 42154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15291 /* 42160 */ GIR_RootConstrainSelectedInstOperands,
15292 /* 42161 */ // GIR_Coverage, 1408,
15293 /* 42161 */ GIR_EraseRootFromParent_Done,
15294 /* 42162 */ // Label 975: @42162
15295 /* 42162 */ GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(42207), // Rule ID 1409 //
15296 /* 42167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15297 /* 42170 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
15298 /* 42175 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15299 /* 42178 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
15300 /* 42181 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15301 /* 42185 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15302 /* 42189 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4045:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VPADDLuv8i8:{ *:[v4i16] } DPR:{ *:[v8i8] }:$Vm)
15303 /* 42189 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i8),
15304 /* 42192 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15305 /* 42194 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15306 /* 42196 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15307 /* 42199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15308 /* 42205 */ GIR_RootConstrainSelectedInstOperands,
15309 /* 42206 */ // GIR_Coverage, 1409,
15310 /* 42206 */ GIR_EraseRootFromParent_Done,
15311 /* 42207 */ // Label 976: @42207
15312 /* 42207 */ GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(42252), // Rule ID 1410 //
15313 /* 42212 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15314 /* 42215 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
15315 /* 42220 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15316 /* 42223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15317 /* 42226 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15318 /* 42230 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15319 /* 42234 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4045:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VPADDLuv4i16:{ *:[v2i32] } DPR:{ *:[v4i16] }:$Vm)
15320 /* 42234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i16),
15321 /* 42237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15322 /* 42239 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15323 /* 42241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15324 /* 42244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15325 /* 42250 */ GIR_RootConstrainSelectedInstOperands,
15326 /* 42251 */ // GIR_Coverage, 1410,
15327 /* 42251 */ GIR_EraseRootFromParent_Done,
15328 /* 42252 */ // Label 977: @42252
15329 /* 42252 */ GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(42297), // Rule ID 1411 //
15330 /* 42257 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15331 /* 42260 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
15332 /* 42265 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
15333 /* 42268 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15334 /* 42271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15335 /* 42275 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15336 /* 42279 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4045:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VPADDLuv2i32:{ *:[v1i64] } DPR:{ *:[v2i32] }:$Vm)
15337 /* 42279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv2i32),
15338 /* 42282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15339 /* 42284 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15340 /* 42286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15341 /* 42289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15342 /* 42295 */ GIR_RootConstrainSelectedInstOperands,
15343 /* 42296 */ // GIR_Coverage, 1411,
15344 /* 42296 */ GIR_EraseRootFromParent_Done,
15345 /* 42297 */ // Label 978: @42297
15346 /* 42297 */ GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(42342), // Rule ID 1412 //
15347 /* 42302 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15348 /* 42305 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
15349 /* 42310 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15350 /* 42313 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15351 /* 42316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15352 /* 42320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15353 /* 42324 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4045:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VPADDLuv16i8:{ *:[v8i16] } QPR:{ *:[v16i8] }:$Vm)
15354 /* 42324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv16i8),
15355 /* 42327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15356 /* 42329 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15357 /* 42331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15358 /* 42334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15359 /* 42340 */ GIR_RootConstrainSelectedInstOperands,
15360 /* 42341 */ // GIR_Coverage, 1412,
15361 /* 42341 */ GIR_EraseRootFromParent_Done,
15362 /* 42342 */ // Label 979: @42342
15363 /* 42342 */ GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(42387), // Rule ID 1413 //
15364 /* 42347 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15365 /* 42350 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
15366 /* 42355 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15367 /* 42358 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15368 /* 42361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15369 /* 42365 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15370 /* 42369 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4045:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VPADDLuv8i16:{ *:[v4i32] } QPR:{ *:[v8i16] }:$Vm)
15371 /* 42369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv8i16),
15372 /* 42372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15373 /* 42374 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15374 /* 42376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15375 /* 42379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15376 /* 42385 */ GIR_RootConstrainSelectedInstOperands,
15377 /* 42386 */ // GIR_Coverage, 1413,
15378 /* 42386 */ GIR_EraseRootFromParent_Done,
15379 /* 42387 */ // Label 980: @42387
15380 /* 42387 */ GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(42432), // Rule ID 1414 //
15381 /* 42392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15382 /* 42395 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpaddlu),
15383 /* 42400 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
15384 /* 42403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15385 /* 42406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15386 /* 42410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15387 /* 42414 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4045:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VPADDLuv4i32:{ *:[v2i64] } QPR:{ *:[v4i32] }:$Vm)
15388 /* 42414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDLuv4i32),
15389 /* 42417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15390 /* 42419 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15391 /* 42421 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15392 /* 42424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15393 /* 42430 */ GIR_RootConstrainSelectedInstOperands,
15394 /* 42431 */ // GIR_Coverage, 1414,
15395 /* 42431 */ GIR_EraseRootFromParent_Done,
15396 /* 42432 */ // Label 981: @42432
15397 /* 42432 */ GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(42477), // Rule ID 1443 //
15398 /* 42437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15399 /* 42440 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
15400 /* 42445 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15401 /* 42448 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15402 /* 42451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15403 /* 42455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15404 /* 42459 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4072:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRECPEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
15405 /* 42459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEd),
15406 /* 42462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15407 /* 42464 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15408 /* 42466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15409 /* 42469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15410 /* 42475 */ GIR_RootConstrainSelectedInstOperands,
15411 /* 42476 */ // GIR_Coverage, 1443,
15412 /* 42476 */ GIR_EraseRootFromParent_Done,
15413 /* 42477 */ // Label 982: @42477
15414 /* 42477 */ GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(42522), // Rule ID 1444 //
15415 /* 42482 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15416 /* 42485 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
15417 /* 42490 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15418 /* 42493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15419 /* 42496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15420 /* 42500 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15421 /* 42504 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4072:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRECPEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
15422 /* 42504 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEq),
15423 /* 42507 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15424 /* 42509 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15425 /* 42511 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15426 /* 42514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15427 /* 42520 */ GIR_RootConstrainSelectedInstOperands,
15428 /* 42521 */ // GIR_Coverage, 1444,
15429 /* 42521 */ GIR_EraseRootFromParent_Done,
15430 /* 42522 */ // Label 983: @42522
15431 /* 42522 */ GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(42567), // Rule ID 1445 //
15432 /* 42527 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15433 /* 42530 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
15434 /* 42535 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15435 /* 42538 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15436 /* 42541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15437 /* 42545 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15438 /* 42549 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4072:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRECPEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15439 /* 42549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfd),
15440 /* 42552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15441 /* 42554 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15442 /* 42556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15443 /* 42559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15444 /* 42565 */ GIR_RootConstrainSelectedInstOperands,
15445 /* 42566 */ // GIR_Coverage, 1445,
15446 /* 42566 */ GIR_EraseRootFromParent_Done,
15447 /* 42567 */ // Label 984: @42567
15448 /* 42567 */ GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(42612), // Rule ID 1446 //
15449 /* 42572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15450 /* 42575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
15451 /* 42580 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15452 /* 42583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15453 /* 42586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15454 /* 42590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15455 /* 42594 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4072:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRECPEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15456 /* 42594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEfq),
15457 /* 42597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15458 /* 42599 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15459 /* 42601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15460 /* 42604 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15461 /* 42610 */ GIR_RootConstrainSelectedInstOperands,
15462 /* 42611 */ // GIR_Coverage, 1446,
15463 /* 42611 */ GIR_EraseRootFromParent_Done,
15464 /* 42612 */ // Label 985: @42612
15465 /* 42612 */ GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(42657), // Rule ID 1447 //
15466 /* 42617 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
15467 /* 42620 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
15468 /* 42625 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15469 /* 42628 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15470 /* 42631 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15471 /* 42635 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15472 /* 42639 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4072:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRECPEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15473 /* 42639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhd),
15474 /* 42642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15475 /* 42644 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15476 /* 42646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15477 /* 42649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15478 /* 42655 */ GIR_RootConstrainSelectedInstOperands,
15479 /* 42656 */ // GIR_Coverage, 1447,
15480 /* 42656 */ GIR_EraseRootFromParent_Done,
15481 /* 42657 */ // Label 986: @42657
15482 /* 42657 */ GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(42702), // Rule ID 1448 //
15483 /* 42662 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
15484 /* 42665 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecpe),
15485 /* 42670 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15486 /* 42673 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15487 /* 42676 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15488 /* 42680 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15489 /* 42684 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4072:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRECPEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15490 /* 42684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPEhq),
15491 /* 42687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15492 /* 42689 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15493 /* 42691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15494 /* 42694 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15495 /* 42700 */ GIR_RootConstrainSelectedInstOperands,
15496 /* 42701 */ // GIR_Coverage, 1448,
15497 /* 42701 */ GIR_EraseRootFromParent_Done,
15498 /* 42702 */ // Label 987: @42702
15499 /* 42702 */ GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(42747), // Rule ID 1453 //
15500 /* 42707 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15501 /* 42710 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
15502 /* 42715 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15503 /* 42718 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15504 /* 42721 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15505 /* 42725 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15506 /* 42729 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4079:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VRSQRTEd:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
15507 /* 42729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEd),
15508 /* 42732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15509 /* 42734 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15510 /* 42736 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15511 /* 42739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15512 /* 42745 */ GIR_RootConstrainSelectedInstOperands,
15513 /* 42746 */ // GIR_Coverage, 1453,
15514 /* 42746 */ GIR_EraseRootFromParent_Done,
15515 /* 42747 */ // Label 988: @42747
15516 /* 42747 */ GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(42792), // Rule ID 1454 //
15517 /* 42752 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15518 /* 42755 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
15519 /* 42760 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15520 /* 42763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15521 /* 42766 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15522 /* 42770 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15523 /* 42774 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4079:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VRSQRTEq:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
15524 /* 42774 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEq),
15525 /* 42777 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15526 /* 42779 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15527 /* 42781 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15528 /* 42784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15529 /* 42790 */ GIR_RootConstrainSelectedInstOperands,
15530 /* 42791 */ // GIR_Coverage, 1454,
15531 /* 42791 */ GIR_EraseRootFromParent_Done,
15532 /* 42792 */ // Label 989: @42792
15533 /* 42792 */ GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(42837), // Rule ID 1455 //
15534 /* 42797 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15535 /* 42800 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
15536 /* 42805 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15537 /* 42808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15538 /* 42811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15539 /* 42815 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15540 /* 42819 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4079:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTEfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
15541 /* 42819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfd),
15542 /* 42822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15543 /* 42824 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15544 /* 42826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15545 /* 42829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15546 /* 42835 */ GIR_RootConstrainSelectedInstOperands,
15547 /* 42836 */ // GIR_Coverage, 1455,
15548 /* 42836 */ GIR_EraseRootFromParent_Done,
15549 /* 42837 */ // Label 990: @42837
15550 /* 42837 */ GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(42882), // Rule ID 1456 //
15551 /* 42842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15552 /* 42845 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
15553 /* 42850 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15554 /* 42853 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15555 /* 42856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15556 /* 42860 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15557 /* 42864 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4079:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTEfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
15558 /* 42864 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEfq),
15559 /* 42867 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15560 /* 42869 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15561 /* 42871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15562 /* 42874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15563 /* 42880 */ GIR_RootConstrainSelectedInstOperands,
15564 /* 42881 */ // GIR_Coverage, 1456,
15565 /* 42881 */ GIR_EraseRootFromParent_Done,
15566 /* 42882 */ // Label 991: @42882
15567 /* 42882 */ GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(42927), // Rule ID 1457 //
15568 /* 42887 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
15569 /* 42890 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
15570 /* 42895 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15571 /* 42898 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15572 /* 42901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15573 /* 42905 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15574 /* 42909 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4079:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTEhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
15575 /* 42909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhd),
15576 /* 42912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15577 /* 42914 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15578 /* 42916 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15579 /* 42919 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15580 /* 42925 */ GIR_RootConstrainSelectedInstOperands,
15581 /* 42926 */ // GIR_Coverage, 1457,
15582 /* 42926 */ GIR_EraseRootFromParent_Done,
15583 /* 42927 */ // Label 992: @42927
15584 /* 42927 */ GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(42972), // Rule ID 1458 //
15585 /* 42932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
15586 /* 42935 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrte),
15587 /* 42940 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15588 /* 42943 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15589 /* 42946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15590 /* 42950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15591 /* 42954 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4079:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTEhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
15592 /* 42954 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTEhq),
15593 /* 42957 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15594 /* 42959 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15595 /* 42961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15596 /* 42964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15597 /* 42970 */ GIR_RootConstrainSelectedInstOperands,
15598 /* 42971 */ // GIR_Coverage, 1458,
15599 /* 42971 */ GIR_EraseRootFromParent_Done,
15600 /* 42972 */ // Label 993: @42972
15601 /* 42972 */ GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(43017), // Rule ID 1679 //
15602 /* 42977 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15603 /* 42980 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
15604 /* 42985 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
15605 /* 42988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
15606 /* 42991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15607 /* 42995 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15608 /* 42999 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4050:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
15609 /* 42999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i8),
15610 /* 43002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15611 /* 43004 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15612 /* 43006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15613 /* 43009 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15614 /* 43015 */ GIR_RootConstrainSelectedInstOperands,
15615 /* 43016 */ // GIR_Coverage, 1679,
15616 /* 43016 */ GIR_EraseRootFromParent_Done,
15617 /* 43017 */ // Label 994: @43017
15618 /* 43017 */ GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(43062), // Rule ID 1680 //
15619 /* 43022 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15620 /* 43025 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
15621 /* 43030 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15622 /* 43033 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15623 /* 43036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15624 /* 43040 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15625 /* 43044 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4050:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
15626 /* 43044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i16),
15627 /* 43047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15628 /* 43049 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15629 /* 43051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15630 /* 43054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15631 /* 43060 */ GIR_RootConstrainSelectedInstOperands,
15632 /* 43061 */ // GIR_Coverage, 1680,
15633 /* 43061 */ GIR_EraseRootFromParent_Done,
15634 /* 43062 */ // Label 995: @43062
15635 /* 43062 */ GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(43107), // Rule ID 1681 //
15636 /* 43067 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15637 /* 43070 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
15638 /* 43075 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15639 /* 43078 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15640 /* 43081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15641 /* 43085 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15642 /* 43089 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4050:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
15643 /* 43089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv2i32),
15644 /* 43092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15645 /* 43094 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15646 /* 43096 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15647 /* 43099 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15648 /* 43105 */ GIR_RootConstrainSelectedInstOperands,
15649 /* 43106 */ // GIR_Coverage, 1681,
15650 /* 43106 */ GIR_EraseRootFromParent_Done,
15651 /* 43107 */ // Label 996: @43107
15652 /* 43107 */ GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(43152), // Rule ID 1682 //
15653 /* 43112 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15654 /* 43115 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
15655 /* 43120 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
15656 /* 43123 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15657 /* 43126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15658 /* 43130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15659 /* 43134 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4050:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
15660 /* 43134 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv16i8),
15661 /* 43137 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15662 /* 43139 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15663 /* 43141 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15664 /* 43144 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15665 /* 43150 */ GIR_RootConstrainSelectedInstOperands,
15666 /* 43151 */ // GIR_Coverage, 1682,
15667 /* 43151 */ GIR_EraseRootFromParent_Done,
15668 /* 43152 */ // Label 997: @43152
15669 /* 43152 */ GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(43197), // Rule ID 1683 //
15670 /* 43157 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15671 /* 43160 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
15672 /* 43165 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15673 /* 43168 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15674 /* 43171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15675 /* 43175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15676 /* 43179 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4050:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
15677 /* 43179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv8i16),
15678 /* 43182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15679 /* 43184 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15680 /* 43186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15681 /* 43189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15682 /* 43195 */ GIR_RootConstrainSelectedInstOperands,
15683 /* 43196 */ // GIR_Coverage, 1683,
15684 /* 43196 */ GIR_EraseRootFromParent_Done,
15685 /* 43197 */ // Label 998: @43197
15686 /* 43197 */ GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(43242), // Rule ID 1684 //
15687 /* 43202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15688 /* 43205 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqabs),
15689 /* 43210 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15690 /* 43213 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15691 /* 43216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15692 /* 43220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15693 /* 43224 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4050:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
15694 /* 43224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQABSv4i32),
15695 /* 43227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15696 /* 43229 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15697 /* 43231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15698 /* 43234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15699 /* 43240 */ GIR_RootConstrainSelectedInstOperands,
15700 /* 43241 */ // GIR_Coverage, 1684,
15701 /* 43241 */ GIR_EraseRootFromParent_Done,
15702 /* 43242 */ // Label 999: @43242
15703 /* 43242 */ GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(43287), // Rule ID 1695 //
15704 /* 43247 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15705 /* 43250 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
15706 /* 43255 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
15707 /* 43258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
15708 /* 43261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15709 /* 43265 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15710 /* 43269 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4056:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VQNEGv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
15711 /* 43269 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i8),
15712 /* 43272 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15713 /* 43274 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15714 /* 43276 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15715 /* 43279 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15716 /* 43285 */ GIR_RootConstrainSelectedInstOperands,
15717 /* 43286 */ // GIR_Coverage, 1695,
15718 /* 43286 */ GIR_EraseRootFromParent_Done,
15719 /* 43287 */ // Label 1000: @43287
15720 /* 43287 */ GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(43332), // Rule ID 1696 //
15721 /* 43292 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15722 /* 43295 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
15723 /* 43300 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15724 /* 43303 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15725 /* 43306 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15726 /* 43310 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15727 /* 43314 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4056:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VQNEGv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
15728 /* 43314 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i16),
15729 /* 43317 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15730 /* 43319 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15731 /* 43321 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15732 /* 43324 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15733 /* 43330 */ GIR_RootConstrainSelectedInstOperands,
15734 /* 43331 */ // GIR_Coverage, 1696,
15735 /* 43331 */ GIR_EraseRootFromParent_Done,
15736 /* 43332 */ // Label 1001: @43332
15737 /* 43332 */ GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(43377), // Rule ID 1697 //
15738 /* 43337 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15739 /* 43340 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
15740 /* 43345 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15741 /* 43348 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15742 /* 43351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15743 /* 43355 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15744 /* 43359 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4056:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VQNEGv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
15745 /* 43359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv2i32),
15746 /* 43362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15747 /* 43364 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15748 /* 43366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15749 /* 43369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15750 /* 43375 */ GIR_RootConstrainSelectedInstOperands,
15751 /* 43376 */ // GIR_Coverage, 1697,
15752 /* 43376 */ GIR_EraseRootFromParent_Done,
15753 /* 43377 */ // Label 1002: @43377
15754 /* 43377 */ GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(43422), // Rule ID 1698 //
15755 /* 43382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15756 /* 43385 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
15757 /* 43390 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
15758 /* 43393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15759 /* 43396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15760 /* 43400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15761 /* 43404 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4056:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VQNEGv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
15762 /* 43404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv16i8),
15763 /* 43407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15764 /* 43409 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15765 /* 43411 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15766 /* 43414 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15767 /* 43420 */ GIR_RootConstrainSelectedInstOperands,
15768 /* 43421 */ // GIR_Coverage, 1698,
15769 /* 43421 */ GIR_EraseRootFromParent_Done,
15770 /* 43422 */ // Label 1003: @43422
15771 /* 43422 */ GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(43467), // Rule ID 1699 //
15772 /* 43427 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15773 /* 43430 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
15774 /* 43435 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15775 /* 43438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15776 /* 43441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15777 /* 43445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15778 /* 43449 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4056:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQNEGv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
15779 /* 43449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv8i16),
15780 /* 43452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15781 /* 43454 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15782 /* 43456 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15783 /* 43459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15784 /* 43465 */ GIR_RootConstrainSelectedInstOperands,
15785 /* 43466 */ // GIR_Coverage, 1699,
15786 /* 43466 */ GIR_EraseRootFromParent_Done,
15787 /* 43467 */ // Label 1004: @43467
15788 /* 43467 */ GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(43512), // Rule ID 1700 //
15789 /* 43472 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15790 /* 43475 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqneg),
15791 /* 43480 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15792 /* 43483 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15793 /* 43486 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15794 /* 43490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15795 /* 43494 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4056:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQNEGv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
15796 /* 43494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQNEGv4i32),
15797 /* 43497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15798 /* 43499 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15799 /* 43501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15800 /* 43504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15801 /* 43510 */ GIR_RootConstrainSelectedInstOperands,
15802 /* 43511 */ // GIR_Coverage, 1700,
15803 /* 43511 */ GIR_EraseRootFromParent_Done,
15804 /* 43512 */ // Label 1005: @43512
15805 /* 43512 */ GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(43557), // Rule ID 1701 //
15806 /* 43517 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15807 /* 43520 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls),
15808 /* 43525 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
15809 /* 43528 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
15810 /* 43531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15811 /* 43535 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15812 /* 43539 */ // (intrinsic_wo_chain:{ *:[v8i8] } 3997:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm) => (VCLSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
15813 /* 43539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i8),
15814 /* 43542 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15815 /* 43544 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15816 /* 43546 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15817 /* 43549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15818 /* 43555 */ GIR_RootConstrainSelectedInstOperands,
15819 /* 43556 */ // GIR_Coverage, 1701,
15820 /* 43556 */ GIR_EraseRootFromParent_Done,
15821 /* 43557 */ // Label 1006: @43557
15822 /* 43557 */ GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(43602), // Rule ID 1702 //
15823 /* 43562 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15824 /* 43565 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls),
15825 /* 43570 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15826 /* 43573 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
15827 /* 43576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15828 /* 43580 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15829 /* 43584 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3997:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCLSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
15830 /* 43584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i16),
15831 /* 43587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15832 /* 43589 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15833 /* 43591 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15834 /* 43594 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15835 /* 43600 */ GIR_RootConstrainSelectedInstOperands,
15836 /* 43601 */ // GIR_Coverage, 1702,
15837 /* 43601 */ GIR_EraseRootFromParent_Done,
15838 /* 43602 */ // Label 1007: @43602
15839 /* 43602 */ GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(43647), // Rule ID 1703 //
15840 /* 43607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15841 /* 43610 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls),
15842 /* 43615 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15843 /* 43618 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
15844 /* 43621 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15845 /* 43625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15846 /* 43629 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3997:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm) => (VCLSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
15847 /* 43629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv2i32),
15848 /* 43632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15849 /* 43634 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15850 /* 43636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15851 /* 43639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15852 /* 43645 */ GIR_RootConstrainSelectedInstOperands,
15853 /* 43646 */ // GIR_Coverage, 1703,
15854 /* 43646 */ GIR_EraseRootFromParent_Done,
15855 /* 43647 */ // Label 1008: @43647
15856 /* 43647 */ GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(43692), // Rule ID 1704 //
15857 /* 43652 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15858 /* 43655 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls),
15859 /* 43660 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
15860 /* 43663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
15861 /* 43666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15862 /* 43670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15863 /* 43674 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3997:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (VCLSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
15864 /* 43674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv16i8),
15865 /* 43677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15866 /* 43679 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15867 /* 43681 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15868 /* 43684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15869 /* 43690 */ GIR_RootConstrainSelectedInstOperands,
15870 /* 43691 */ // GIR_Coverage, 1704,
15871 /* 43691 */ GIR_EraseRootFromParent_Done,
15872 /* 43692 */ // Label 1009: @43692
15873 /* 43692 */ GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(43737), // Rule ID 1705 //
15874 /* 43697 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15875 /* 43700 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls),
15876 /* 43705 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
15877 /* 43708 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15878 /* 43711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15879 /* 43715 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15880 /* 43719 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3997:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VCLSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
15881 /* 43719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv8i16),
15882 /* 43722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15883 /* 43724 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15884 /* 43726 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15885 /* 43729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15886 /* 43735 */ GIR_RootConstrainSelectedInstOperands,
15887 /* 43736 */ // GIR_Coverage, 1705,
15888 /* 43736 */ GIR_EraseRootFromParent_Done,
15889 /* 43737 */ // Label 1010: @43737
15890 /* 43737 */ GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(43782), // Rule ID 1706 //
15891 /* 43742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15892 /* 43745 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcls),
15893 /* 43750 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
15894 /* 43753 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15895 /* 43756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15896 /* 43760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15897 /* 43764 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3997:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VCLSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
15898 /* 43764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLSv4i32),
15899 /* 43767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15900 /* 43769 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15901 /* 43771 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15902 /* 43774 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15903 /* 43780 */ GIR_RootConstrainSelectedInstOperands,
15904 /* 43781 */ // GIR_Coverage, 1706,
15905 /* 43781 */ GIR_EraseRootFromParent_Done,
15906 /* 43782 */ // Label 1011: @43782
15907 /* 43782 */ GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(43827), // Rule ID 1750 //
15908 /* 43787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15909 /* 43790 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns),
15910 /* 43795 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
15911 /* 43798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15912 /* 43801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15913 /* 43805 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15914 /* 43809 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4053:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
15915 /* 43809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv8i8),
15916 /* 43812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15917 /* 43814 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15918 /* 43816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15919 /* 43819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15920 /* 43825 */ GIR_RootConstrainSelectedInstOperands,
15921 /* 43826 */ // GIR_Coverage, 1750,
15922 /* 43826 */ GIR_EraseRootFromParent_Done,
15923 /* 43827 */ // Label 1012: @43827
15924 /* 43827 */ GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(43872), // Rule ID 1751 //
15925 /* 43832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15926 /* 43835 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns),
15927 /* 43840 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15928 /* 43843 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15929 /* 43846 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15930 /* 43850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15931 /* 43854 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4053:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
15932 /* 43854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv4i16),
15933 /* 43857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15934 /* 43859 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15935 /* 43861 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15936 /* 43864 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15937 /* 43870 */ GIR_RootConstrainSelectedInstOperands,
15938 /* 43871 */ // GIR_Coverage, 1751,
15939 /* 43871 */ GIR_EraseRootFromParent_Done,
15940 /* 43872 */ // Label 1013: @43872
15941 /* 43872 */ GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(43917), // Rule ID 1752 //
15942 /* 43877 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15943 /* 43880 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovns),
15944 /* 43885 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15945 /* 43888 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
15946 /* 43891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15947 /* 43895 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15948 /* 43899 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4053:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
15949 /* 43899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsv2i32),
15950 /* 43902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15951 /* 43904 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15952 /* 43906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15953 /* 43909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15954 /* 43915 */ GIR_RootConstrainSelectedInstOperands,
15955 /* 43916 */ // GIR_Coverage, 1752,
15956 /* 43916 */ GIR_EraseRootFromParent_Done,
15957 /* 43917 */ // Label 1014: @43917
15958 /* 43917 */ GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(43962), // Rule ID 1753 //
15959 /* 43922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15960 /* 43925 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu),
15961 /* 43930 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
15962 /* 43933 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
15963 /* 43936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15964 /* 43940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15965 /* 43944 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4055:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
15966 /* 43944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv8i8),
15967 /* 43947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15968 /* 43949 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15969 /* 43951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15970 /* 43954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15971 /* 43960 */ GIR_RootConstrainSelectedInstOperands,
15972 /* 43961 */ // GIR_Coverage, 1753,
15973 /* 43961 */ GIR_EraseRootFromParent_Done,
15974 /* 43962 */ // Label 1015: @43962
15975 /* 43962 */ GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(44007), // Rule ID 1754 //
15976 /* 43967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15977 /* 43970 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu),
15978 /* 43975 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
15979 /* 43978 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
15980 /* 43981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15981 /* 43985 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15982 /* 43989 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4055:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
15983 /* 43989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv4i16),
15984 /* 43992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
15985 /* 43994 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
15986 /* 43996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
15987 /* 43999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
15988 /* 44005 */ GIR_RootConstrainSelectedInstOperands,
15989 /* 44006 */ // GIR_Coverage, 1754,
15990 /* 44006 */ GIR_EraseRootFromParent_Done,
15991 /* 44007 */ // Label 1016: @44007
15992 /* 44007 */ GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(44052), // Rule ID 1755 //
15993 /* 44012 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
15994 /* 44015 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnu),
15995 /* 44020 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
15996 /* 44023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
15997 /* 44026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
15998 /* 44030 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
15999 /* 44034 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4055:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
16000 /* 44034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNuv2i32),
16001 /* 44037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16002 /* 44039 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16003 /* 44041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16004 /* 44044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16005 /* 44050 */ GIR_RootConstrainSelectedInstOperands,
16006 /* 44051 */ // GIR_Coverage, 1755,
16007 /* 44051 */ GIR_EraseRootFromParent_Done,
16008 /* 44052 */ // Label 1017: @44052
16009 /* 44052 */ GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(44097), // Rule ID 1756 //
16010 /* 44057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16011 /* 44060 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu),
16012 /* 44065 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
16013 /* 44068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16014 /* 44071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16015 /* 44075 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16016 /* 44079 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4054:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm) => (VQMOVNsuv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
16017 /* 44079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv8i8),
16018 /* 44082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16019 /* 44084 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16020 /* 44086 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16021 /* 44089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16022 /* 44095 */ GIR_RootConstrainSelectedInstOperands,
16023 /* 44096 */ // GIR_Coverage, 1756,
16024 /* 44096 */ GIR_EraseRootFromParent_Done,
16025 /* 44097 */ // Label 1018: @44097
16026 /* 44097 */ GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(44142), // Rule ID 1757 //
16027 /* 44102 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16028 /* 44105 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu),
16029 /* 44110 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16030 /* 44113 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16031 /* 44116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16032 /* 44120 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16033 /* 44124 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4054:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm) => (VQMOVNsuv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
16034 /* 44124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv4i16),
16035 /* 44127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16036 /* 44129 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16037 /* 44131 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16038 /* 44134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16039 /* 44140 */ GIR_RootConstrainSelectedInstOperands,
16040 /* 44141 */ // GIR_Coverage, 1757,
16041 /* 44141 */ GIR_EraseRootFromParent_Done,
16042 /* 44142 */ // Label 1019: @44142
16043 /* 44142 */ GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(44187), // Rule ID 1758 //
16044 /* 44147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
16045 /* 44150 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqmovnsu),
16046 /* 44155 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16047 /* 44158 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
16048 /* 44161 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16049 /* 44165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16050 /* 44169 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4054:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm) => (VQMOVNsuv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
16051 /* 44169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQMOVNsuv2i32),
16052 /* 44172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16053 /* 44174 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16054 /* 44176 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16055 /* 44179 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16056 /* 44185 */ GIR_RootConstrainSelectedInstOperands,
16057 /* 44186 */ // GIR_Coverage, 1758,
16058 /* 44186 */ GIR_EraseRootFromParent_Done,
16059 /* 44187 */ // Label 1020: @44187
16060 /* 44187 */ GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(44223), // Rule ID 1781 //
16061 /* 44192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16062 /* 44195 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
16063 /* 44200 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16064 /* 44203 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
16065 /* 44206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16066 /* 44210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16067 /* 44214 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3998:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
16068 /* 44214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDf),
16069 /* 44217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16070 /* 44219 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16071 /* 44221 */ GIR_RootConstrainSelectedInstOperands,
16072 /* 44222 */ // GIR_Coverage, 1781,
16073 /* 44222 */ GIR_EraseRootFromParent_Done,
16074 /* 44223 */ // Label 1021: @44223
16075 /* 44223 */ GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(44259), // Rule ID 1782 //
16076 /* 44228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16077 /* 44231 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
16078 /* 44236 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16079 /* 44239 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16080 /* 44242 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16081 /* 44246 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16082 /* 44250 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3998:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
16083 /* 44250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQf),
16084 /* 44253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16085 /* 44255 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16086 /* 44257 */ GIR_RootConstrainSelectedInstOperands,
16087 /* 44258 */ // GIR_Coverage, 1782,
16088 /* 44258 */ GIR_EraseRootFromParent_Done,
16089 /* 44259 */ // Label 1022: @44259
16090 /* 44259 */ GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(44295), // Rule ID 1783 //
16091 /* 44264 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16092 /* 44267 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
16093 /* 44272 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16094 /* 44275 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
16095 /* 44278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16096 /* 44282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16097 /* 44286 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3999:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTANUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
16098 /* 44286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDf),
16099 /* 44289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16100 /* 44291 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16101 /* 44293 */ GIR_RootConstrainSelectedInstOperands,
16102 /* 44294 */ // GIR_Coverage, 1783,
16103 /* 44294 */ GIR_EraseRootFromParent_Done,
16104 /* 44295 */ // Label 1023: @44295
16105 /* 44295 */ GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(44331), // Rule ID 1784 //
16106 /* 44300 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16107 /* 44303 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
16108 /* 44308 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16109 /* 44311 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16110 /* 44314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16111 /* 44318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16112 /* 44322 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3999:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTANUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
16113 /* 44322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQf),
16114 /* 44325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16115 /* 44327 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16116 /* 44329 */ GIR_RootConstrainSelectedInstOperands,
16117 /* 44330 */ // GIR_Coverage, 1784,
16118 /* 44330 */ GIR_EraseRootFromParent_Done,
16119 /* 44331 */ // Label 1024: @44331
16120 /* 44331 */ GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(44367), // Rule ID 1785 //
16121 /* 44336 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16122 /* 44339 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
16123 /* 44344 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16124 /* 44347 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16125 /* 44350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16126 /* 44354 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16127 /* 44358 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3998:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16128 /* 44358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSDh),
16129 /* 44361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16130 /* 44363 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16131 /* 44365 */ GIR_RootConstrainSelectedInstOperands,
16132 /* 44366 */ // GIR_Coverage, 1785,
16133 /* 44366 */ GIR_EraseRootFromParent_Done,
16134 /* 44367 */ // Label 1025: @44367
16135 /* 44367 */ GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(44403), // Rule ID 1786 //
16136 /* 44372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16137 /* 44375 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtas),
16138 /* 44380 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16139 /* 44383 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16140 /* 44386 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16141 /* 44390 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16142 /* 44394 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3998:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16143 /* 44394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANSQh),
16144 /* 44397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16145 /* 44399 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16146 /* 44401 */ GIR_RootConstrainSelectedInstOperands,
16147 /* 44402 */ // GIR_Coverage, 1786,
16148 /* 44402 */ GIR_EraseRootFromParent_Done,
16149 /* 44403 */ // Label 1026: @44403
16150 /* 44403 */ GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(44439), // Rule ID 1787 //
16151 /* 44408 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16152 /* 44411 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
16153 /* 44416 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16154 /* 44419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16155 /* 44422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16156 /* 44426 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16157 /* 44430 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3999:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTANUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16158 /* 44430 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUDh),
16159 /* 44433 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16160 /* 44435 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16161 /* 44437 */ GIR_RootConstrainSelectedInstOperands,
16162 /* 44438 */ // GIR_Coverage, 1787,
16163 /* 44438 */ GIR_EraseRootFromParent_Done,
16164 /* 44439 */ // Label 1027: @44439
16165 /* 44439 */ GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(44475), // Rule ID 1788 //
16166 /* 44444 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16167 /* 44447 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtau),
16168 /* 44452 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16169 /* 44455 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16170 /* 44458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16171 /* 44462 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16172 /* 44466 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3999:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTANUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16173 /* 44466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTANUQh),
16174 /* 44469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16175 /* 44471 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16176 /* 44473 */ GIR_RootConstrainSelectedInstOperands,
16177 /* 44474 */ // GIR_Coverage, 1788,
16178 /* 44474 */ GIR_EraseRootFromParent_Done,
16179 /* 44475 */ // Label 1028: @44475
16180 /* 44475 */ GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(44511), // Rule ID 1789 //
16181 /* 44480 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16182 /* 44483 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
16183 /* 44488 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16184 /* 44491 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
16185 /* 44494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16186 /* 44498 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16187 /* 44502 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4010:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
16188 /* 44502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDf),
16189 /* 44505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16190 /* 44507 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16191 /* 44509 */ GIR_RootConstrainSelectedInstOperands,
16192 /* 44510 */ // GIR_Coverage, 1789,
16193 /* 44510 */ GIR_EraseRootFromParent_Done,
16194 /* 44511 */ // Label 1029: @44511
16195 /* 44511 */ GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(44547), // Rule ID 1790 //
16196 /* 44516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16197 /* 44519 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
16198 /* 44524 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16199 /* 44527 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16200 /* 44530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16201 /* 44534 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16202 /* 44538 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4010:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
16203 /* 44538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQf),
16204 /* 44541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16205 /* 44543 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16206 /* 44545 */ GIR_RootConstrainSelectedInstOperands,
16207 /* 44546 */ // GIR_Coverage, 1790,
16208 /* 44546 */ GIR_EraseRootFromParent_Done,
16209 /* 44547 */ // Label 1030: @44547
16210 /* 44547 */ GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(44583), // Rule ID 1791 //
16211 /* 44552 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16212 /* 44555 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
16213 /* 44560 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16214 /* 44563 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
16215 /* 44566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16216 /* 44570 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16217 /* 44574 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4011:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTNNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
16218 /* 44574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDf),
16219 /* 44577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16220 /* 44579 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16221 /* 44581 */ GIR_RootConstrainSelectedInstOperands,
16222 /* 44582 */ // GIR_Coverage, 1791,
16223 /* 44582 */ GIR_EraseRootFromParent_Done,
16224 /* 44583 */ // Label 1031: @44583
16225 /* 44583 */ GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(44619), // Rule ID 1792 //
16226 /* 44588 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16227 /* 44591 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
16228 /* 44596 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16229 /* 44599 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16230 /* 44602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16231 /* 44606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16232 /* 44610 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4011:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTNNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
16233 /* 44610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQf),
16234 /* 44613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16235 /* 44615 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16236 /* 44617 */ GIR_RootConstrainSelectedInstOperands,
16237 /* 44618 */ // GIR_Coverage, 1792,
16238 /* 44618 */ GIR_EraseRootFromParent_Done,
16239 /* 44619 */ // Label 1032: @44619
16240 /* 44619 */ GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(44655), // Rule ID 1793 //
16241 /* 44624 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16242 /* 44627 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
16243 /* 44632 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16244 /* 44635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16245 /* 44638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16246 /* 44642 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16247 /* 44646 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4010:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16248 /* 44646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSDh),
16249 /* 44649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16250 /* 44651 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16251 /* 44653 */ GIR_RootConstrainSelectedInstOperands,
16252 /* 44654 */ // GIR_Coverage, 1793,
16253 /* 44654 */ GIR_EraseRootFromParent_Done,
16254 /* 44655 */ // Label 1033: @44655
16255 /* 44655 */ GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(44691), // Rule ID 1794 //
16256 /* 44660 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16257 /* 44663 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtns),
16258 /* 44668 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16259 /* 44671 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16260 /* 44674 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16261 /* 44678 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16262 /* 44682 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4010:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16263 /* 44682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNSQh),
16264 /* 44685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16265 /* 44687 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16266 /* 44689 */ GIR_RootConstrainSelectedInstOperands,
16267 /* 44690 */ // GIR_Coverage, 1794,
16268 /* 44690 */ GIR_EraseRootFromParent_Done,
16269 /* 44691 */ // Label 1034: @44691
16270 /* 44691 */ GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(44727), // Rule ID 1795 //
16271 /* 44696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16272 /* 44699 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
16273 /* 44704 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16274 /* 44707 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16275 /* 44710 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16276 /* 44714 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16277 /* 44718 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4011:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTNNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16278 /* 44718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUDh),
16279 /* 44721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16280 /* 44723 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16281 /* 44725 */ GIR_RootConstrainSelectedInstOperands,
16282 /* 44726 */ // GIR_Coverage, 1795,
16283 /* 44726 */ GIR_EraseRootFromParent_Done,
16284 /* 44727 */ // Label 1035: @44727
16285 /* 44727 */ GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(44763), // Rule ID 1796 //
16286 /* 44732 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16287 /* 44735 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtnu),
16288 /* 44740 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16289 /* 44743 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16290 /* 44746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16291 /* 44750 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16292 /* 44754 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4011:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTNNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16293 /* 44754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTNNUQh),
16294 /* 44757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16295 /* 44759 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16296 /* 44761 */ GIR_RootConstrainSelectedInstOperands,
16297 /* 44762 */ // GIR_Coverage, 1796,
16298 /* 44762 */ GIR_EraseRootFromParent_Done,
16299 /* 44763 */ // Label 1036: @44763
16300 /* 44763 */ GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(44799), // Rule ID 1797 //
16301 /* 44768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16302 /* 44771 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
16303 /* 44776 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16304 /* 44779 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
16305 /* 44782 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16306 /* 44786 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16307 /* 44790 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4012:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
16308 /* 44790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDf),
16309 /* 44793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16310 /* 44795 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16311 /* 44797 */ GIR_RootConstrainSelectedInstOperands,
16312 /* 44798 */ // GIR_Coverage, 1797,
16313 /* 44798 */ GIR_EraseRootFromParent_Done,
16314 /* 44799 */ // Label 1037: @44799
16315 /* 44799 */ GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(44835), // Rule ID 1798 //
16316 /* 44804 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16317 /* 44807 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
16318 /* 44812 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16319 /* 44815 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16320 /* 44818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16321 /* 44822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16322 /* 44826 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4012:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
16323 /* 44826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQf),
16324 /* 44829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16325 /* 44831 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16326 /* 44833 */ GIR_RootConstrainSelectedInstOperands,
16327 /* 44834 */ // GIR_Coverage, 1798,
16328 /* 44834 */ GIR_EraseRootFromParent_Done,
16329 /* 44835 */ // Label 1038: @44835
16330 /* 44835 */ GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(44871), // Rule ID 1799 //
16331 /* 44840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16332 /* 44843 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
16333 /* 44848 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16334 /* 44851 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
16335 /* 44854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16336 /* 44858 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16337 /* 44862 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4013:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTPNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
16338 /* 44862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDf),
16339 /* 44865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16340 /* 44867 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16341 /* 44869 */ GIR_RootConstrainSelectedInstOperands,
16342 /* 44870 */ // GIR_Coverage, 1799,
16343 /* 44870 */ GIR_EraseRootFromParent_Done,
16344 /* 44871 */ // Label 1039: @44871
16345 /* 44871 */ GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(44907), // Rule ID 1800 //
16346 /* 44876 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16347 /* 44879 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
16348 /* 44884 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16349 /* 44887 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16350 /* 44890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16351 /* 44894 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16352 /* 44898 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4013:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTPNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
16353 /* 44898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQf),
16354 /* 44901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16355 /* 44903 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16356 /* 44905 */ GIR_RootConstrainSelectedInstOperands,
16357 /* 44906 */ // GIR_Coverage, 1800,
16358 /* 44906 */ GIR_EraseRootFromParent_Done,
16359 /* 44907 */ // Label 1040: @44907
16360 /* 44907 */ GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(44943), // Rule ID 1801 //
16361 /* 44912 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16362 /* 44915 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
16363 /* 44920 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16364 /* 44923 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16365 /* 44926 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16366 /* 44930 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16367 /* 44934 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4012:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16368 /* 44934 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSDh),
16369 /* 44937 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16370 /* 44939 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16371 /* 44941 */ GIR_RootConstrainSelectedInstOperands,
16372 /* 44942 */ // GIR_Coverage, 1801,
16373 /* 44942 */ GIR_EraseRootFromParent_Done,
16374 /* 44943 */ // Label 1041: @44943
16375 /* 44943 */ GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(44979), // Rule ID 1802 //
16376 /* 44948 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16377 /* 44951 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtps),
16378 /* 44956 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16379 /* 44959 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16380 /* 44962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16381 /* 44966 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16382 /* 44970 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4012:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16383 /* 44970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNSQh),
16384 /* 44973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16385 /* 44975 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16386 /* 44977 */ GIR_RootConstrainSelectedInstOperands,
16387 /* 44978 */ // GIR_Coverage, 1802,
16388 /* 44978 */ GIR_EraseRootFromParent_Done,
16389 /* 44979 */ // Label 1042: @44979
16390 /* 44979 */ GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(45015), // Rule ID 1803 //
16391 /* 44984 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16392 /* 44987 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
16393 /* 44992 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16394 /* 44995 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16395 /* 44998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16396 /* 45002 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16397 /* 45006 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4013:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTPNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16398 /* 45006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUDh),
16399 /* 45009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16400 /* 45011 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16401 /* 45013 */ GIR_RootConstrainSelectedInstOperands,
16402 /* 45014 */ // GIR_Coverage, 1803,
16403 /* 45014 */ GIR_EraseRootFromParent_Done,
16404 /* 45015 */ // Label 1043: @45015
16405 /* 45015 */ GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(45051), // Rule ID 1804 //
16406 /* 45020 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16407 /* 45023 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtpu),
16408 /* 45028 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16409 /* 45031 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16410 /* 45034 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16411 /* 45038 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16412 /* 45042 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4013:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTPNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16413 /* 45042 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTPNUQh),
16414 /* 45045 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16415 /* 45047 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16416 /* 45049 */ GIR_RootConstrainSelectedInstOperands,
16417 /* 45050 */ // GIR_Coverage, 1804,
16418 /* 45050 */ GIR_EraseRootFromParent_Done,
16419 /* 45051 */ // Label 1044: @45051
16420 /* 45051 */ GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(45087), // Rule ID 1805 //
16421 /* 45056 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16422 /* 45059 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
16423 /* 45064 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16424 /* 45067 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
16425 /* 45070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16426 /* 45074 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16427 /* 45078 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4008:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNSDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
16428 /* 45078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDf),
16429 /* 45081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16430 /* 45083 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16431 /* 45085 */ GIR_RootConstrainSelectedInstOperands,
16432 /* 45086 */ // GIR_Coverage, 1805,
16433 /* 45086 */ GIR_EraseRootFromParent_Done,
16434 /* 45087 */ // Label 1045: @45087
16435 /* 45087 */ GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(45123), // Rule ID 1806 //
16436 /* 45092 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16437 /* 45095 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
16438 /* 45100 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16439 /* 45103 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16440 /* 45106 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16441 /* 45110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16442 /* 45114 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4008:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNSQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
16443 /* 45114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQf),
16444 /* 45117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16445 /* 45119 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16446 /* 45121 */ GIR_RootConstrainSelectedInstOperands,
16447 /* 45122 */ // GIR_Coverage, 1806,
16448 /* 45122 */ GIR_EraseRootFromParent_Done,
16449 /* 45123 */ // Label 1046: @45123
16450 /* 45123 */ GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(45159), // Rule ID 1807 //
16451 /* 45128 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16452 /* 45131 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
16453 /* 45136 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
16454 /* 45139 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
16455 /* 45142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16456 /* 45146 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16457 /* 45150 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4009:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm) => (VCVTMNUDf:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
16458 /* 45150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDf),
16459 /* 45153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16460 /* 45155 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16461 /* 45157 */ GIR_RootConstrainSelectedInstOperands,
16462 /* 45158 */ // GIR_Coverage, 1807,
16463 /* 45158 */ GIR_EraseRootFromParent_Done,
16464 /* 45159 */ // Label 1047: @45159
16465 /* 45159 */ GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(45195), // Rule ID 1808 //
16466 /* 45164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
16467 /* 45167 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
16468 /* 45172 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16469 /* 45175 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16470 /* 45178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16471 /* 45182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16472 /* 45186 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4009:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTMNUQf:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
16473 /* 45186 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQf),
16474 /* 45189 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16475 /* 45191 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16476 /* 45193 */ GIR_RootConstrainSelectedInstOperands,
16477 /* 45194 */ // GIR_Coverage, 1808,
16478 /* 45194 */ GIR_EraseRootFromParent_Done,
16479 /* 45195 */ // Label 1048: @45195
16480 /* 45195 */ GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(45231), // Rule ID 1809 //
16481 /* 45200 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16482 /* 45203 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
16483 /* 45208 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16484 /* 45211 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16485 /* 45214 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16486 /* 45218 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16487 /* 45222 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4008:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNSDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16488 /* 45222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSDh),
16489 /* 45225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16490 /* 45227 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16491 /* 45229 */ GIR_RootConstrainSelectedInstOperands,
16492 /* 45230 */ // GIR_Coverage, 1809,
16493 /* 45230 */ GIR_EraseRootFromParent_Done,
16494 /* 45231 */ // Label 1049: @45231
16495 /* 45231 */ GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(45267), // Rule ID 1810 //
16496 /* 45236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16497 /* 45239 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtms),
16498 /* 45244 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16499 /* 45247 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16500 /* 45250 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16501 /* 45254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16502 /* 45258 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4008:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNSQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16503 /* 45258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNSQh),
16504 /* 45261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16505 /* 45263 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16506 /* 45265 */ GIR_RootConstrainSelectedInstOperands,
16507 /* 45266 */ // GIR_Coverage, 1810,
16508 /* 45266 */ GIR_EraseRootFromParent_Done,
16509 /* 45267 */ // Label 1050: @45267
16510 /* 45267 */ GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(45303), // Rule ID 1811 //
16511 /* 45272 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16512 /* 45275 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
16513 /* 45280 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16514 /* 45283 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16515 /* 45286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16516 /* 45290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16517 /* 45294 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4009:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm) => (VCVTMNUDh:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
16518 /* 45294 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUDh),
16519 /* 45297 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16520 /* 45299 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16521 /* 45301 */ GIR_RootConstrainSelectedInstOperands,
16522 /* 45302 */ // GIR_Coverage, 1811,
16523 /* 45302 */ GIR_EraseRootFromParent_Done,
16524 /* 45303 */ // Label 1051: @45303
16525 /* 45303 */ GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(45339), // Rule ID 1812 //
16526 /* 45308 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
16527 /* 45311 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtmu),
16528 /* 45316 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16529 /* 45319 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16530 /* 45322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16531 /* 45326 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16532 /* 45330 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4009:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm) => (VCVTMNUQh:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
16533 /* 45330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTMNUQh),
16534 /* 45333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16535 /* 45335 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16536 /* 45337 */ GIR_RootConstrainSelectedInstOperands,
16537 /* 45338 */ // GIR_Coverage, 1812,
16538 /* 45338 */ GIR_EraseRootFromParent_Done,
16539 /* 45339 */ // Label 1052: @45339
16540 /* 45339 */ GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(45384), // Rule ID 1829 //
16541 /* 45344 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16_HasNEON),
16542 /* 45347 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2hf),
16543 /* 45352 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
16544 /* 45355 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16545 /* 45358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16546 /* 45362 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16547 /* 45366 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4004:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm) => (VCVTf2h:{ *:[v4i16] } QPR:{ *:[v4f32] }:$Vm)
16548 /* 45366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h),
16549 /* 45369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16550 /* 45371 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16551 /* 45373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16552 /* 45376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16553 /* 45382 */ GIR_RootConstrainSelectedInstOperands,
16554 /* 45383 */ // GIR_Coverage, 1829,
16555 /* 45383 */ GIR_EraseRootFromParent_Done,
16556 /* 45384 */ // Label 1053: @45384
16557 /* 45384 */ GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(45429), // Rule ID 1830 //
16558 /* 45389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16_HasNEON),
16559 /* 45392 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvthf2fp),
16560 /* 45397 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16561 /* 45400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
16562 /* 45403 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16563 /* 45407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
16564 /* 45411 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4007:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4i16] }:$Vm)
16565 /* 45411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f),
16566 /* 45414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16567 /* 45416 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16568 /* 45418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16569 /* 45421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16570 /* 45427 */ GIR_RootConstrainSelectedInstOperands,
16571 /* 45428 */ // GIR_Coverage, 1830,
16572 /* 45428 */ GIR_EraseRootFromParent_Done,
16573 /* 45429 */ // Label 1054: @45429
16574 /* 45429 */ GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(45465), // Rule ID 1878 //
16575 /* 45434 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8),
16576 /* 45437 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesimc),
16577 /* 45442 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
16578 /* 45445 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
16579 /* 45448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16580 /* 45452 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16581 /* 45456 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3967:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESIMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
16582 /* 45456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESIMC),
16583 /* 45459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16584 /* 45461 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16585 /* 45463 */ GIR_RootConstrainSelectedInstOperands,
16586 /* 45464 */ // GIR_Coverage, 1878,
16587 /* 45464 */ GIR_EraseRootFromParent_Done,
16588 /* 45465 */ // Label 1055: @45465
16589 /* 45465 */ GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(45501), // Rule ID 1879 //
16590 /* 45470 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8),
16591 /* 45473 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesmc),
16592 /* 45478 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
16593 /* 45481 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
16594 /* 45484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16595 /* 45488 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
16596 /* 45492 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3968:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm) => (AESMC:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
16597 /* 45492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESMC),
16598 /* 45495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
16599 /* 45497 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
16600 /* 45499 */ GIR_RootConstrainSelectedInstOperands,
16601 /* 45500 */ // GIR_Coverage, 1879,
16602 /* 45500 */ GIR_EraseRootFromParent_Done,
16603 /* 45501 */ // Label 1056: @45501
16604 /* 45501 */ GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(45549), // Rule ID 2012 //
16605 /* 45506 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
16606 /* 45509 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16),
16607 /* 45514 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16608 /* 45517 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16609 /* 45520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
16610 /* 45524 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
16611 /* 45528 */ // (intrinsic_wo_chain:{ *:[i32] } 4161:{ *:[iPTR] }, GPR:{ *:[i32] }:$Src) => (SXTB16:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
16612 /* 45528 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB16),
16613 /* 45531 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16614 /* 45533 */ GIR_RootToRootCopy, /*OpIdx*/2, // Src
16615 /* 45535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16616 /* 45538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16617 /* 45541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16618 /* 45547 */ GIR_RootConstrainSelectedInstOperands,
16619 /* 45548 */ // GIR_Coverage, 2012,
16620 /* 45548 */ GIR_EraseRootFromParent_Done,
16621 /* 45549 */ // Label 1057: @45549
16622 /* 45549 */ GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(45597), // Rule ID 2260 //
16623 /* 45554 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
16624 /* 45557 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtb16),
16625 /* 45562 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
16626 /* 45565 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16627 /* 45568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16628 /* 45572 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16629 /* 45576 */ // (intrinsic_wo_chain:{ *:[i32] } 4161:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (t2SXTB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, 0:{ *:[i32] })
16630 /* 45576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB16),
16631 /* 45579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
16632 /* 45581 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16633 /* 45583 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16634 /* 45586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
16635 /* 45589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16636 /* 45595 */ GIR_RootConstrainSelectedInstOperands,
16637 /* 45596 */ // GIR_Coverage, 2260,
16638 /* 45596 */ GIR_EraseRootFromParent_Done,
16639 /* 45597 */ // Label 1058: @45597
16640 /* 45597 */ GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(45663), // Rule ID 4006 //
16641 /* 45602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16642 /* 45605 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcls),
16643 /* 45610 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
16644 /* 45613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
16645 /* 45616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16646 /* 45620 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16647 /* 45624 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3838:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$val) => (MVE_VCLSs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)
16648 /* 45624 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16649 /* 45627 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16650 /* 45631 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16651 /* 45636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs8),
16652 /* 45639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16653 /* 45641 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16654 /* 45643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16655 /* 45646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16656 /* 45652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16657 /* 45658 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16658 /* 45661 */ GIR_RootConstrainSelectedInstOperands,
16659 /* 45662 */ // GIR_Coverage, 4006,
16660 /* 45662 */ GIR_EraseRootFromParent_Done,
16661 /* 45663 */ // Label 1059: @45663
16662 /* 45663 */ GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(45729), // Rule ID 4008 //
16663 /* 45668 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16664 /* 45671 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcls),
16665 /* 45676 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16666 /* 45679 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16667 /* 45682 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16668 /* 45686 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16669 /* 45690 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3838:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$val) => (MVE_VCLSs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)
16670 /* 45690 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16671 /* 45693 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16672 /* 45697 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16673 /* 45702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs16),
16674 /* 45705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16675 /* 45707 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16676 /* 45709 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16677 /* 45712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16678 /* 45718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16679 /* 45724 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16680 /* 45727 */ GIR_RootConstrainSelectedInstOperands,
16681 /* 45728 */ // GIR_Coverage, 4008,
16682 /* 45728 */ GIR_EraseRootFromParent_Done,
16683 /* 45729 */ // Label 1060: @45729
16684 /* 45729 */ GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(45795), // Rule ID 4010 //
16685 /* 45734 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16686 /* 45737 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcls),
16687 /* 45742 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16688 /* 45745 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16689 /* 45748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16690 /* 45752 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16691 /* 45756 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3838:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$val) => (MVE_VCLSs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)
16692 /* 45756 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16693 /* 45759 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16694 /* 45763 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16695 /* 45768 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLSs32),
16696 /* 45771 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16697 /* 45773 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16698 /* 45775 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16699 /* 45778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16700 /* 45784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16701 /* 45790 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16702 /* 45793 */ GIR_RootConstrainSelectedInstOperands,
16703 /* 45794 */ // GIR_Coverage, 4010,
16704 /* 45794 */ GIR_EraseRootFromParent_Done,
16705 /* 45795 */ // Label 1061: @45795
16706 /* 45795 */ GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(45861), // Rule ID 4323 //
16707 /* 45800 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16708 /* 45803 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn),
16709 /* 45808 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16710 /* 45811 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16711 /* 45814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16712 /* 45818 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16713 /* 45822 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3927:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16N:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
16714 /* 45822 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16715 /* 45825 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16716 /* 45829 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16717 /* 45834 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16N),
16718 /* 45837 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16719 /* 45839 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16720 /* 45841 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16721 /* 45844 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16722 /* 45850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16723 /* 45856 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16724 /* 45859 */ GIR_RootConstrainSelectedInstOperands,
16725 /* 45860 */ // GIR_Coverage, 4323,
16726 /* 45860 */ GIR_EraseRootFromParent_Done,
16727 /* 45861 */ // Label 1062: @45861
16728 /* 45861 */ GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(45927), // Rule ID 4326 //
16729 /* 45866 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16730 /* 45869 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintx),
16731 /* 45874 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16732 /* 45877 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16733 /* 45880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16734 /* 45884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16735 /* 45888 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3931:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
16736 /* 45888 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16737 /* 45891 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16738 /* 45895 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16739 /* 45900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X),
16740 /* 45903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16741 /* 45905 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16742 /* 45907 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16743 /* 45910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16744 /* 45916 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16745 /* 45922 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16746 /* 45925 */ GIR_RootConstrainSelectedInstOperands,
16747 /* 45926 */ // GIR_Coverage, 4326,
16748 /* 45926 */ GIR_EraseRootFromParent_Done,
16749 /* 45927 */ // Label 1063: @45927
16750 /* 45927 */ GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(45993), // Rule ID 4329 //
16751 /* 45932 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16752 /* 45935 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrinta),
16753 /* 45940 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16754 /* 45943 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16755 /* 45946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16756 /* 45950 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16757 /* 45954 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3923:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16A:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
16758 /* 45954 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16759 /* 45957 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16760 /* 45961 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16761 /* 45966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16A),
16762 /* 45969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16763 /* 45971 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16764 /* 45973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16765 /* 45976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16766 /* 45982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16767 /* 45988 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16768 /* 45991 */ GIR_RootConstrainSelectedInstOperands,
16769 /* 45992 */ // GIR_Coverage, 4329,
16770 /* 45992 */ GIR_EraseRootFromParent_Done,
16771 /* 45993 */ // Label 1064: @45993
16772 /* 45993 */ GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(46059), // Rule ID 4332 //
16773 /* 45998 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16774 /* 46001 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintz),
16775 /* 46006 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16776 /* 46009 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16777 /* 46012 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16778 /* 46016 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16779 /* 46020 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3933:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16Z:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
16780 /* 46020 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16781 /* 46023 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16782 /* 46027 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16783 /* 46032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16Z),
16784 /* 46035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16785 /* 46037 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16786 /* 46039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16787 /* 46042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16788 /* 46048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16789 /* 46054 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16790 /* 46057 */ GIR_RootConstrainSelectedInstOperands,
16791 /* 46058 */ // GIR_Coverage, 4332,
16792 /* 46058 */ GIR_EraseRootFromParent_Done,
16793 /* 46059 */ // Label 1065: @46059
16794 /* 46059 */ GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(46125), // Rule ID 4335 //
16795 /* 46064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16796 /* 46067 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintm),
16797 /* 46072 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16798 /* 46075 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16799 /* 46078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16800 /* 46082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16801 /* 46086 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3925:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
16802 /* 46086 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16803 /* 46089 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16804 /* 46093 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16805 /* 46098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M),
16806 /* 46101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16807 /* 46103 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16808 /* 46105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16809 /* 46108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16810 /* 46114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16811 /* 46120 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16812 /* 46123 */ GIR_RootConstrainSelectedInstOperands,
16813 /* 46124 */ // GIR_Coverage, 4335,
16814 /* 46124 */ GIR_EraseRootFromParent_Done,
16815 /* 46125 */ // Label 1066: @46125
16816 /* 46125 */ GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(46191), // Rule ID 4338 //
16817 /* 46130 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16818 /* 46133 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintp),
16819 /* 46138 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
16820 /* 46141 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
16821 /* 46144 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16822 /* 46148 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16823 /* 46152 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3929:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
16824 /* 46152 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16825 /* 46155 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16826 /* 46159 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16827 /* 46164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P),
16828 /* 46167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16829 /* 46169 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16830 /* 46171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16831 /* 46174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16832 /* 46180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16833 /* 46186 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16834 /* 46189 */ GIR_RootConstrainSelectedInstOperands,
16835 /* 46190 */ // GIR_Coverage, 4338,
16836 /* 46190 */ GIR_EraseRootFromParent_Done,
16837 /* 46191 */ // Label 1067: @46191
16838 /* 46191 */ GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(46257), // Rule ID 4341 //
16839 /* 46196 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16840 /* 46199 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintn),
16841 /* 46204 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16842 /* 46207 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16843 /* 46210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16844 /* 46214 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16845 /* 46218 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3927:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32N:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
16846 /* 46218 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16847 /* 46221 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16848 /* 46225 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16849 /* 46230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32N),
16850 /* 46233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16851 /* 46235 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16852 /* 46237 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16853 /* 46240 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16854 /* 46246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16855 /* 46252 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16856 /* 46255 */ GIR_RootConstrainSelectedInstOperands,
16857 /* 46256 */ // GIR_Coverage, 4341,
16858 /* 46256 */ GIR_EraseRootFromParent_Done,
16859 /* 46257 */ // Label 1068: @46257
16860 /* 46257 */ GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(46323), // Rule ID 4344 //
16861 /* 46262 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16862 /* 46265 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintx),
16863 /* 46270 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16864 /* 46273 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16865 /* 46276 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16866 /* 46280 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16867 /* 46284 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3931:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
16868 /* 46284 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16869 /* 46287 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16870 /* 46291 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16871 /* 46296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X),
16872 /* 46299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16873 /* 46301 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16874 /* 46303 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16875 /* 46306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16876 /* 46312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16877 /* 46318 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16878 /* 46321 */ GIR_RootConstrainSelectedInstOperands,
16879 /* 46322 */ // GIR_Coverage, 4344,
16880 /* 46322 */ GIR_EraseRootFromParent_Done,
16881 /* 46323 */ // Label 1069: @46323
16882 /* 46323 */ GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(46389), // Rule ID 4347 //
16883 /* 46328 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16884 /* 46331 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrinta),
16885 /* 46336 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16886 /* 46339 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16887 /* 46342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16888 /* 46346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16889 /* 46350 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3923:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32A:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
16890 /* 46350 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16891 /* 46353 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16892 /* 46357 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16893 /* 46362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32A),
16894 /* 46365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16895 /* 46367 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16896 /* 46369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16897 /* 46372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16898 /* 46378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16899 /* 46384 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16900 /* 46387 */ GIR_RootConstrainSelectedInstOperands,
16901 /* 46388 */ // GIR_Coverage, 4347,
16902 /* 46388 */ GIR_EraseRootFromParent_Done,
16903 /* 46389 */ // Label 1070: @46389
16904 /* 46389 */ GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(46455), // Rule ID 4350 //
16905 /* 46394 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16906 /* 46397 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintz),
16907 /* 46402 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16908 /* 46405 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16909 /* 46408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16910 /* 46412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16911 /* 46416 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3933:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32Z:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
16912 /* 46416 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16913 /* 46419 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16914 /* 46423 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16915 /* 46428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32Z),
16916 /* 46431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16917 /* 46433 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16918 /* 46435 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16919 /* 46438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16920 /* 46444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16921 /* 46450 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16922 /* 46453 */ GIR_RootConstrainSelectedInstOperands,
16923 /* 46454 */ // GIR_Coverage, 4350,
16924 /* 46454 */ GIR_EraseRootFromParent_Done,
16925 /* 46455 */ // Label 1071: @46455
16926 /* 46455 */ GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(46521), // Rule ID 4353 //
16927 /* 46460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16928 /* 46463 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintm),
16929 /* 46468 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16930 /* 46471 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16931 /* 46474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16932 /* 46478 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16933 /* 46482 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3925:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
16934 /* 46482 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16935 /* 46485 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16936 /* 46489 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16937 /* 46494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M),
16938 /* 46497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16939 /* 46499 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16940 /* 46501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16941 /* 46504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16942 /* 46510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16943 /* 46516 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16944 /* 46519 */ GIR_RootConstrainSelectedInstOperands,
16945 /* 46520 */ // GIR_Coverage, 4353,
16946 /* 46520 */ GIR_EraseRootFromParent_Done,
16947 /* 46521 */ // Label 1072: @46521
16948 /* 46521 */ GIM_Try, /*On fail goto*//*Label 1073*/ GIMT_Encode4(46587), // Rule ID 4356 //
16949 /* 46526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
16950 /* 46529 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrintp),
16951 /* 46534 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
16952 /* 46537 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
16953 /* 46540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16954 /* 46544 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
16955 /* 46548 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3929:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
16956 /* 46548 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
16957 /* 46551 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
16958 /* 46555 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
16959 /* 46560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P),
16960 /* 46563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
16961 /* 46565 */ GIR_RootToRootCopy, /*OpIdx*/2, // val
16962 /* 46567 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16963 /* 46570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16964 /* 46576 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16965 /* 46582 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
16966 /* 46585 */ GIR_RootConstrainSelectedInstOperands,
16967 /* 46586 */ // GIR_Coverage, 4356,
16968 /* 46586 */ GIR_EraseRootFromParent_Done,
16969 /* 46587 */ // Label 1073: @46587
16970 /* 46587 */ GIM_Try, /*On fail goto*//*Label 1074*/ GIMT_Encode4(46638), // Rule ID 5342 //
16971 /* 46592 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16972 /* 46595 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp8),
16973 /* 46600 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s1,
16974 /* 46603 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16975 /* 46606 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16976 /* 46610 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16977 /* 46614 */ // (intrinsic_wo_chain:{ *:[v16i1] } 3846:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP8:{ *:[v16i1] } rGPR:{ *:[i32] }:$Rn)
16978 /* 46614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP8),
16979 /* 46617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
16980 /* 46619 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16981 /* 46621 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
16982 /* 46624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16983 /* 46630 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
16984 /* 46636 */ GIR_RootConstrainSelectedInstOperands,
16985 /* 46637 */ // GIR_Coverage, 5342,
16986 /* 46637 */ GIR_EraseRootFromParent_Done,
16987 /* 46638 */ // Label 1074: @46638
16988 /* 46638 */ GIM_Try, /*On fail goto*//*Label 1075*/ GIMT_Encode4(46689), // Rule ID 5344 //
16989 /* 46643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
16990 /* 46646 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp16),
16991 /* 46651 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
16992 /* 46654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
16993 /* 46657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
16994 /* 46661 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
16995 /* 46665 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3843:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP16:{ *:[v8i1] } rGPR:{ *:[i32] }:$Rn)
16996 /* 46665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP16),
16997 /* 46668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
16998 /* 46670 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
16999 /* 46672 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17000 /* 46675 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17001 /* 46681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17002 /* 46687 */ GIR_RootConstrainSelectedInstOperands,
17003 /* 46688 */ // GIR_Coverage, 5344,
17004 /* 46688 */ GIR_EraseRootFromParent_Done,
17005 /* 46689 */ // Label 1075: @46689
17006 /* 46689 */ GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(46740), // Rule ID 5346 //
17007 /* 46694 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
17008 /* 46697 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp32),
17009 /* 46702 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
17010 /* 46705 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17011 /* 46708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
17012 /* 46712 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17013 /* 46716 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3844:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP32:{ *:[v4i1] } rGPR:{ *:[i32] }:$Rn)
17014 /* 46716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP32),
17015 /* 46719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
17016 /* 46721 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17017 /* 46723 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17018 /* 46726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17019 /* 46732 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17020 /* 46738 */ GIR_RootConstrainSelectedInstOperands,
17021 /* 46739 */ // GIR_Coverage, 5346,
17022 /* 46739 */ GIR_EraseRootFromParent_Done,
17023 /* 46740 */ // Label 1076: @46740
17024 /* 46740 */ GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(46791), // Rule ID 5348 //
17025 /* 46745 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
17026 /* 46748 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vctp64),
17027 /* 46753 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s1,
17028 /* 46756 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17029 /* 46759 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
17030 /* 46763 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17031 /* 46767 */ // (intrinsic_wo_chain:{ *:[v2i1] } 3845:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn) => (MVE_VCTP64:{ *:[v2i1] } rGPR:{ *:[i32] }:$Rn)
17032 /* 46767 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCTP64),
17033 /* 46770 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
17034 /* 46772 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17035 /* 46774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17036 /* 46777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17037 /* 46783 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17038 /* 46789 */ GIR_RootConstrainSelectedInstOperands,
17039 /* 46790 */ // GIR_Coverage, 5348,
17040 /* 46790 */ GIR_EraseRootFromParent_Done,
17041 /* 46791 */ // Label 1077: @46791
17042 /* 46791 */ GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(46837), // Rule ID 599 //
17043 /* 46796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb),
17044 /* 46799 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tt),
17045 /* 46804 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17046 /* 46807 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17047 /* 46811 */ // MIs[0] Rn
17048 /* 46811 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
17049 /* 46815 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17050 /* 46819 */ // (intrinsic_wo_chain:{ *:[i32] } 3720:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
17051 /* 46819 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TT),
17052 /* 46822 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
17053 /* 46824 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17054 /* 46826 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17055 /* 46829 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17056 /* 46835 */ GIR_RootConstrainSelectedInstOperands,
17057 /* 46836 */ // GIR_Coverage, 599,
17058 /* 46836 */ GIR_EraseRootFromParent_Done,
17059 /* 46837 */ // Label 1078: @46837
17060 /* 46837 */ GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(46883), // Rule ID 600 //
17061 /* 46842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb),
17062 /* 46845 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttt),
17063 /* 46850 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17064 /* 46853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17065 /* 46857 */ // MIs[0] Rn
17066 /* 46857 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
17067 /* 46861 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17068 /* 46865 */ // (intrinsic_wo_chain:{ *:[i32] } 3723:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
17069 /* 46865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTT),
17070 /* 46868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
17071 /* 46870 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17072 /* 46872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17073 /* 46875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17074 /* 46881 */ GIR_RootConstrainSelectedInstOperands,
17075 /* 46882 */ // GIR_Coverage, 600,
17076 /* 46882 */ GIR_EraseRootFromParent_Done,
17077 /* 46883 */ // Label 1079: @46883
17078 /* 46883 */ GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(46929), // Rule ID 601 //
17079 /* 46888 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb),
17080 /* 46891 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_tta),
17081 /* 46896 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17082 /* 46899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17083 /* 46903 */ // MIs[0] Rn
17084 /* 46903 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
17085 /* 46907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17086 /* 46911 */ // (intrinsic_wo_chain:{ *:[i32] } 3721:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTA:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
17087 /* 46911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTA),
17088 /* 46914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
17089 /* 46916 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17090 /* 46918 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17091 /* 46921 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17092 /* 46927 */ GIR_RootConstrainSelectedInstOperands,
17093 /* 46928 */ // GIR_Coverage, 601,
17094 /* 46928 */ GIR_EraseRootFromParent_Done,
17095 /* 46929 */ // Label 1080: @46929
17096 /* 46929 */ GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(46975), // Rule ID 602 //
17097 /* 46934 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has8MSecExt_IsThumb),
17098 /* 46937 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_cmse_ttat),
17099 /* 46942 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17100 /* 46945 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17101 /* 46949 */ // MIs[0] Rn
17102 /* 46949 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
17103 /* 46953 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17104 /* 46957 */ // (intrinsic_wo_chain:{ *:[i32] } 3722:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn) => (t2TTAT:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn)
17105 /* 46957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2TTAT),
17106 /* 46960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
17107 /* 46962 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17108 /* 46964 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17109 /* 46967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17110 /* 46973 */ GIR_RootConstrainSelectedInstOperands,
17111 /* 46974 */ // GIR_Coverage, 602,
17112 /* 46974 */ GIR_EraseRootFromParent_Done,
17113 /* 46975 */ // Label 1081: @46975
17114 /* 46975 */ GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(47110), // Rule ID 3043 //
17115 /* 46980 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
17116 /* 46983 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1h),
17117 /* 46988 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17118 /* 46991 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17119 /* 46994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
17120 /* 46998 */ // (intrinsic_wo_chain:{ *:[i32] } 3975:{ *:[iPTR] }, i32:{ *:[i32] }:$Rn) => (COPY_TO_REGCLASS:{ *:[i32] } (EXTRACT_SUBREG:{ *:[f32] } (SHA1H:{ *:[v16i8] } (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$Rn, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] }), GPR:{ *:[i32] })
17121 /* 46998 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
17122 /* 47001 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
17123 /* 47005 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17124 /* 47010 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/2, // Rn
17125 /* 47014 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
17126 /* 47019 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v16s8,
17127 /* 47022 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
17128 /* 47026 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17129 /* 47031 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/0,
17130 /* 47034 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
17131 /* 47037 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
17132 /* 47040 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
17133 /* 47045 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
17134 /* 47050 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v16s8,
17135 /* 47053 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::SHA1H),
17136 /* 47057 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17137 /* 47062 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
17138 /* 47065 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
17139 /* 47067 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
17140 /* 47070 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
17141 /* 47074 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17142 /* 47079 */ GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
17143 /* 47086 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
17144 /* 47091 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::MQPRRegClassID),
17145 /* 47096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
17146 /* 47099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
17147 /* 47101 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17148 /* 47104 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
17149 /* 47109 */ // GIR_Coverage, 3043,
17150 /* 47109 */ GIR_EraseRootFromParent_Done,
17151 /* 47110 */ // Label 1082: @47110
17152 /* 47110 */ GIM_Reject,
17153 /* 47111 */ // Label 963: @47111
17154 /* 47111 */ GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(70123),
17155 /* 47116 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
17156 /* 47119 */ GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(47176), // Rule ID 2278 //
17157 /* 47124 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
17158 /* 47127 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16),
17159 /* 47132 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17160 /* 47135 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17161 /* 47138 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17162 /* 47141 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17163 /* 47145 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17164 /* 47149 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17165 /* 47153 */ // (intrinsic_wo_chain:{ *:[i32] } 4185:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
17166 /* 47153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UXTAB16),
17167 /* 47156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17168 /* 47158 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
17169 /* 47160 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17170 /* 47162 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17171 /* 47165 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17172 /* 47168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17173 /* 47174 */ GIR_RootConstrainSelectedInstOperands,
17174 /* 47175 */ // GIR_Coverage, 2278,
17175 /* 47175 */ GIR_EraseRootFromParent_Done,
17176 /* 47176 */ // Label 1084: @47176
17177 /* 47176 */ GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(47275), // Rule ID 2049 //
17178 /* 47181 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
17179 /* 47184 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
17180 /* 47189 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17181 /* 47192 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17182 /* 47195 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17183 /* 47198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17184 /* 47202 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17185 /* 47206 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
17186 /* 47210 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
17187 /* 47214 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17188 /* 47218 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17189 /* 47223 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17190 /* 47227 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17191 /* 47231 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17192 /* 47235 */ // MIs[2] Operand 1
17193 /* 47235 */ // No operand predicates
17194 /* 47235 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
17195 /* 47239 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17196 /* 47243 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17197 /* 47247 */ // MIs[3] Operand 1
17198 /* 47247 */ // No operand predicates
17199 /* 47247 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17200 /* 47249 */ // (intrinsic_wo_chain:{ *:[i32] } 4180:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft)
17201 /* 47249 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT),
17202 /* 47252 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17203 /* 47254 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos
17204 /* 47257 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
17205 /* 47261 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft
17206 /* 47264 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17207 /* 47267 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17208 /* 47273 */ GIR_RootConstrainSelectedInstOperands,
17209 /* 47274 */ // GIR_Coverage, 2049,
17210 /* 47274 */ GIR_EraseRootFromParent_Done,
17211 /* 47275 */ // Label 1085: @47275
17212 /* 47275 */ GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(47374), // Rule ID 2315 //
17213 /* 47280 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
17214 /* 47283 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
17215 /* 47288 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17216 /* 47291 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17217 /* 47294 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17218 /* 47297 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17219 /* 47301 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17220 /* 47305 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL),
17221 /* 47309 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
17222 /* 47313 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17223 /* 47317 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17224 /* 47322 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
17225 /* 47326 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17226 /* 47330 */ GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17227 /* 47334 */ // MIs[2] Operand 1
17228 /* 47334 */ // No operand predicates
17229 /* 47334 */ GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/3, // MIs[3]
17230 /* 47338 */ GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT),
17231 /* 47342 */ GIM_CheckI64ImmPredicate, /*MI*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
17232 /* 47346 */ // MIs[3] Operand 1
17233 /* 47346 */ // No operand predicates
17234 /* 47346 */ GIM_CheckIsSafeToFold, /*NumInsns*/3,
17235 /* 47348 */ // (intrinsic_wo_chain:{ *:[i32] } 4180:{ *:[iPTR] }, (shl:{ *:[i32] } GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft), (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$shft)
17236 /* 47348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT),
17237 /* 47351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17238 /* 47353 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/3, // pos
17239 /* 47356 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
17240 /* 47360 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // shft
17241 /* 47363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17242 /* 47366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17243 /* 47372 */ GIR_RootConstrainSelectedInstOperands,
17244 /* 47373 */ // GIR_Coverage, 2315,
17245 /* 47373 */ GIR_EraseRootFromParent_Done,
17246 /* 47374 */ // Label 1086: @47374
17247 /* 47374 */ GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(47458), // Rule ID 5908 //
17248 /* 47379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17249 /* 47382 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17250 /* 47387 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17251 /* 47390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17252 /* 47393 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17253 /* 47396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17254 /* 47400 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17255 /* 47404 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
17256 /* 47408 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
17257 /* 47411 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17258 /* 47416 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17259 /* 47420 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17260 /* 47425 */ // MIs[1] Rn
17261 /* 47425 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
17262 /* 47430 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17263 /* 47434 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17264 /* 47436 */ // (intrinsic_wo_chain:{ *:[i32] } 4103:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 4103:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn), GPRnopc:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17265 /* 47436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
17266 /* 47439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17267 /* 47441 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17268 /* 47443 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
17269 /* 47447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17270 /* 47450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17271 /* 47456 */ GIR_RootConstrainSelectedInstOperands,
17272 /* 47457 */ // GIR_Coverage, 5908,
17273 /* 47457 */ GIR_EraseRootFromParent_Done,
17274 /* 47458 */ // Label 1087: @47458
17275 /* 47458 */ GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(47542), // Rule ID 6231 //
17276 /* 47463 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
17277 /* 47466 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17278 /* 47471 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17279 /* 47474 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17280 /* 47477 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17281 /* 47480 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17282 /* 47484 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17283 /* 47488 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
17284 /* 47492 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
17285 /* 47495 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17286 /* 47500 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17287 /* 47504 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17288 /* 47509 */ // MIs[1] Rn
17289 /* 47509 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
17290 /* 47514 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17291 /* 47518 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17292 /* 47520 */ // (intrinsic_wo_chain:{ *:[i32] } 4103:{ *:[iPTR] }, (intrinsic_wo_chain:{ *:[i32] } 4103:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
17293 /* 47520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
17294 /* 47523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17295 /* 47525 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
17296 /* 47527 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
17297 /* 47531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17298 /* 47534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17299 /* 47540 */ GIR_RootConstrainSelectedInstOperands,
17300 /* 47541 */ // GIR_Coverage, 6231,
17301 /* 47541 */ GIR_EraseRootFromParent_Done,
17302 /* 47542 */ // Label 1088: @47542
17303 /* 47542 */ GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(47626), // Rule ID 108 //
17304 /* 47547 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17305 /* 47550 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17306 /* 47555 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17307 /* 47558 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17308 /* 47561 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17309 /* 47564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17310 /* 47568 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17311 /* 47572 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17312 /* 47576 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
17313 /* 47580 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
17314 /* 47583 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17315 /* 47588 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17316 /* 47592 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17317 /* 47597 */ // MIs[1] Rn
17318 /* 47597 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
17319 /* 47602 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17320 /* 47604 */ // (intrinsic_wo_chain:{ *:[i32] } 4103:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4103:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17321 /* 47604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
17322 /* 47607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17323 /* 47609 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
17324 /* 47611 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
17325 /* 47615 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17326 /* 47618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17327 /* 47624 */ GIR_RootConstrainSelectedInstOperands,
17328 /* 47625 */ // GIR_Coverage, 108,
17329 /* 47625 */ GIR_EraseRootFromParent_Done,
17330 /* 47626 */ // Label 1089: @47626
17331 /* 47626 */ GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(47710), // Rule ID 109 //
17332 /* 47631 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
17333 /* 47634 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
17334 /* 47639 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17335 /* 47642 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17336 /* 47645 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17337 /* 47648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17338 /* 47652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17339 /* 47656 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17340 /* 47660 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
17341 /* 47664 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
17342 /* 47667 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17343 /* 47672 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17344 /* 47676 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
17345 /* 47681 */ // MIs[1] Rn
17346 /* 47681 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
17347 /* 47686 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17348 /* 47688 */ // (intrinsic_wo_chain:{ *:[i32] } 4108:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4103:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
17349 /* 47688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB),
17350 /* 47691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17351 /* 47693 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
17352 /* 47695 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
17353 /* 47699 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17354 /* 47702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17355 /* 47708 */ GIR_RootConstrainSelectedInstOperands,
17356 /* 47709 */ // GIR_Coverage, 109,
17357 /* 47709 */ GIR_EraseRootFromParent_Done,
17358 /* 47710 */ // Label 1090: @47710
17359 /* 47710 */ GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(47794), // Rule ID 2293 //
17360 /* 47715 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
17361 /* 47718 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17362 /* 47723 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17363 /* 47726 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17364 /* 47729 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17365 /* 47732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17366 /* 47736 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17367 /* 47740 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17368 /* 47744 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
17369 /* 47748 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
17370 /* 47751 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17371 /* 47756 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17372 /* 47760 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17373 /* 47765 */ // MIs[1] Rn
17374 /* 47765 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
17375 /* 47770 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17376 /* 47772 */ // (intrinsic_wo_chain:{ *:[i32] } 4103:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4103:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
17377 /* 47772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
17378 /* 47775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17379 /* 47777 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
17380 /* 47779 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
17381 /* 47783 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17382 /* 47786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17383 /* 47792 */ GIR_RootConstrainSelectedInstOperands,
17384 /* 47793 */ // GIR_Coverage, 2293,
17385 /* 47793 */ GIR_EraseRootFromParent_Done,
17386 /* 47794 */ // Label 1091: @47794
17387 /* 47794 */ GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(47878), // Rule ID 2294 //
17388 /* 47799 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
17389 /* 47802 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
17390 /* 47807 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
17391 /* 47810 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17392 /* 47813 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17393 /* 47816 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17394 /* 47820 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17395 /* 47824 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
17396 /* 47828 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
17397 /* 47832 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
17398 /* 47835 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
17399 /* 47840 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
17400 /* 47844 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
17401 /* 47849 */ // MIs[1] Rn
17402 /* 47849 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/3, /*OtherMI*/1, /*OtherOpIdx*/2,
17403 /* 47854 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
17404 /* 47856 */ // (intrinsic_wo_chain:{ *:[i32] } 4108:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, (intrinsic_wo_chain:{ *:[i32] } 4103:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
17405 /* 47856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB),
17406 /* 47859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
17407 /* 47861 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
17408 /* 47863 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Rn
17409 /* 47867 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
17410 /* 47870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17411 /* 47876 */ GIR_RootConstrainSelectedInstOperands,
17412 /* 47877 */ // GIR_Coverage, 2294,
17413 /* 47877 */ GIR_EraseRootFromParent_Done,
17414 /* 47878 */ // Label 1092: @47878
17415 /* 47878 */ GIM_Try, /*On fail goto*//*Label 1093*/ GIMT_Encode4(47970), // Rule ID 4521 //
17416 /* 47883 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
17417 /* 47886 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm),
17418 /* 47891 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17419 /* 47894 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17420 /* 47897 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17421 /* 47900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17422 /* 47904 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17423 /* 47908 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
17424 /* 47912 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17425 /* 47916 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17426 /* 47921 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
17427 /* 47925 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
17428 /* 47929 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17429 /* 47933 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17430 /* 47938 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17431 /* 47940 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3883:{ *:[iPTR] }, (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
17432 /* 47940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32),
17433 /* 47943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17434 /* 47945 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
17435 /* 47949 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
17436 /* 47953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17437 /* 47956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17438 /* 47962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17439 /* 47968 */ GIR_RootConstrainSelectedInstOperands,
17440 /* 47969 */ // GIR_Coverage, 4521,
17441 /* 47969 */ GIR_EraseRootFromParent_Done,
17442 /* 47970 */ // Label 1093: @47970
17443 /* 47970 */ GIM_Try, /*On fail goto*//*Label 1094*/ GIMT_Encode4(48062), // Rule ID 4524 //
17444 /* 47975 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
17445 /* 47978 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm),
17446 /* 47983 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17447 /* 47986 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17448 /* 47989 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17449 /* 47992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17450 /* 47996 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17451 /* 48000 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
17452 /* 48004 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17453 /* 48008 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17454 /* 48013 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
17455 /* 48017 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
17456 /* 48021 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
17457 /* 48025 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17458 /* 48030 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17459 /* 48032 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3883:{ *:[iPTR] }, (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
17460 /* 48032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16),
17461 /* 48035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17462 /* 48037 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
17463 /* 48041 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
17464 /* 48045 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17465 /* 48048 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17466 /* 48054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17467 /* 48060 */ GIR_RootConstrainSelectedInstOperands,
17468 /* 48061 */ // GIR_Coverage, 4524,
17469 /* 48061 */ GIR_EraseRootFromParent_Done,
17470 /* 48062 */ // Label 1094: @48062
17471 /* 48062 */ GIM_Try, /*On fail goto*//*Label 1095*/ GIMT_Encode4(48154), // Rule ID 4527 //
17472 /* 48067 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
17473 /* 48070 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm),
17474 /* 48075 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17475 /* 48078 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17476 /* 48081 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17477 /* 48084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17478 /* 48088 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17479 /* 48092 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
17480 /* 48096 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
17481 /* 48100 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17482 /* 48105 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
17483 /* 48109 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
17484 /* 48113 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
17485 /* 48117 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17486 /* 48122 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17487 /* 48124 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3886:{ *:[iPTR] }, (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
17488 /* 48124 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32),
17489 /* 48127 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17490 /* 48129 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
17491 /* 48133 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
17492 /* 48137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17493 /* 48140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17494 /* 48146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17495 /* 48152 */ GIR_RootConstrainSelectedInstOperands,
17496 /* 48153 */ // GIR_Coverage, 4527,
17497 /* 48153 */ GIR_EraseRootFromParent_Done,
17498 /* 48154 */ // Label 1095: @48154
17499 /* 48154 */ GIM_Try, /*On fail goto*//*Label 1096*/ GIMT_Encode4(48246), // Rule ID 4530 //
17500 /* 48159 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
17501 /* 48162 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm),
17502 /* 48167 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17503 /* 48170 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17504 /* 48173 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17505 /* 48176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17506 /* 48180 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
17507 /* 48184 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
17508 /* 48188 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
17509 /* 48192 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17510 /* 48197 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
17511 /* 48201 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
17512 /* 48205 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
17513 /* 48209 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17514 /* 48214 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
17515 /* 48216 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3886:{ *:[iPTR] }, (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
17516 /* 48216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16),
17517 /* 48219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17518 /* 48221 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
17519 /* 48225 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
17520 /* 48229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17521 /* 48232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17522 /* 48238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17523 /* 48244 */ GIR_RootConstrainSelectedInstOperands,
17524 /* 48245 */ // GIR_Coverage, 4530,
17525 /* 48245 */ GIR_EraseRootFromParent_Done,
17526 /* 48246 */ // Label 1096: @48246
17527 /* 48246 */ GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(48319), // Rule ID 4452 //
17528 /* 48251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17529 /* 48254 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
17530 /* 48259 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17531 /* 48262 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17532 /* 48265 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17533 /* 48268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17534 /* 48272 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17535 /* 48276 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17536 /* 48280 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3856:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17537 /* 48280 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17538 /* 48283 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17539 /* 48287 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17540 /* 48292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16a),
17541 /* 48295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17542 /* 48297 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17543 /* 48299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17544 /* 48302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17545 /* 48308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17546 /* 48314 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17547 /* 48317 */ GIR_RootConstrainSelectedInstOperands,
17548 /* 48318 */ // GIR_Coverage, 4452,
17549 /* 48318 */ GIR_EraseRootFromParent_Done,
17550 /* 48319 */ // Label 1097: @48319
17551 /* 48319 */ GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(48392), // Rule ID 4454 //
17552 /* 48324 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17553 /* 48327 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
17554 /* 48332 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17555 /* 48335 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17556 /* 48338 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17557 /* 48341 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17558 /* 48345 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17559 /* 48349 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17560 /* 48353 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3860:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17561 /* 48353 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17562 /* 48356 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17563 /* 48360 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17564 /* 48365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16n),
17565 /* 48368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17566 /* 48370 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17567 /* 48372 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17568 /* 48375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17569 /* 48381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17570 /* 48387 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17571 /* 48390 */ GIR_RootConstrainSelectedInstOperands,
17572 /* 48391 */ // GIR_Coverage, 4454,
17573 /* 48391 */ GIR_EraseRootFromParent_Done,
17574 /* 48392 */ // Label 1098: @48392
17575 /* 48392 */ GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(48465), // Rule ID 4456 //
17576 /* 48397 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17577 /* 48400 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
17578 /* 48405 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17579 /* 48408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17580 /* 48411 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17581 /* 48414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17582 /* 48418 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17583 /* 48422 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17584 /* 48426 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3862:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17585 /* 48426 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17586 /* 48429 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17587 /* 48433 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17588 /* 48438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16p),
17589 /* 48441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17590 /* 48443 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17591 /* 48445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17592 /* 48448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17593 /* 48454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17594 /* 48460 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17595 /* 48463 */ GIR_RootConstrainSelectedInstOperands,
17596 /* 48464 */ // GIR_Coverage, 4456,
17597 /* 48464 */ GIR_EraseRootFromParent_Done,
17598 /* 48465 */ // Label 1099: @48465
17599 /* 48465 */ GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(48538), // Rule ID 4458 //
17600 /* 48470 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17601 /* 48473 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
17602 /* 48478 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17603 /* 48481 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17604 /* 48484 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17605 /* 48487 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17606 /* 48491 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17607 /* 48495 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17608 /* 48499 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3858:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTs16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17609 /* 48499 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17610 /* 48502 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17611 /* 48506 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17612 /* 48511 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16m),
17613 /* 48514 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17614 /* 48516 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17615 /* 48518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17616 /* 48521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17617 /* 48527 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17618 /* 48533 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17619 /* 48536 */ GIR_RootConstrainSelectedInstOperands,
17620 /* 48537 */ // GIR_Coverage, 4458,
17621 /* 48537 */ GIR_EraseRootFromParent_Done,
17622 /* 48538 */ // Label 1100: @48538
17623 /* 48538 */ GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(48611), // Rule ID 4460 //
17624 /* 48543 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17625 /* 48546 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
17626 /* 48551 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17627 /* 48554 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17628 /* 48557 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17629 /* 48560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17630 /* 48564 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17631 /* 48568 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17632 /* 48572 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3856:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16a:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17633 /* 48572 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17634 /* 48575 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17635 /* 48579 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17636 /* 48584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16a),
17637 /* 48587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17638 /* 48589 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17639 /* 48591 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17640 /* 48594 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17641 /* 48600 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17642 /* 48606 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17643 /* 48609 */ GIR_RootConstrainSelectedInstOperands,
17644 /* 48610 */ // GIR_Coverage, 4460,
17645 /* 48610 */ GIR_EraseRootFromParent_Done,
17646 /* 48611 */ // Label 1101: @48611
17647 /* 48611 */ GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(48684), // Rule ID 4462 //
17648 /* 48616 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17649 /* 48619 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
17650 /* 48624 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17651 /* 48627 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17652 /* 48630 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17653 /* 48633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17654 /* 48637 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17655 /* 48641 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17656 /* 48645 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3860:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16n:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17657 /* 48645 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17658 /* 48648 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17659 /* 48652 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17660 /* 48657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16n),
17661 /* 48660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17662 /* 48662 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17663 /* 48664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17664 /* 48667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17665 /* 48673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17666 /* 48679 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17667 /* 48682 */ GIR_RootConstrainSelectedInstOperands,
17668 /* 48683 */ // GIR_Coverage, 4462,
17669 /* 48683 */ GIR_EraseRootFromParent_Done,
17670 /* 48684 */ // Label 1102: @48684
17671 /* 48684 */ GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(48757), // Rule ID 4464 //
17672 /* 48689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17673 /* 48692 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
17674 /* 48697 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17675 /* 48700 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17676 /* 48703 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17677 /* 48706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17678 /* 48710 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17679 /* 48714 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17680 /* 48718 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3862:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16p:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17681 /* 48718 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17682 /* 48721 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17683 /* 48725 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17684 /* 48730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16p),
17685 /* 48733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17686 /* 48735 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17687 /* 48737 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17688 /* 48740 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17689 /* 48746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17690 /* 48752 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17691 /* 48755 */ GIR_RootConstrainSelectedInstOperands,
17692 /* 48756 */ // GIR_Coverage, 4464,
17693 /* 48756 */ GIR_EraseRootFromParent_Done,
17694 /* 48757 */ // Label 1103: @48757
17695 /* 48757 */ GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(48830), // Rule ID 4466 //
17696 /* 48762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17697 /* 48765 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
17698 /* 48770 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17699 /* 48773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17700 /* 48776 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
17701 /* 48779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17702 /* 48783 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17703 /* 48787 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17704 /* 48791 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3858:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$in) => (MVE_VCVTu16f16m:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$in)
17705 /* 48791 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17706 /* 48794 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17707 /* 48798 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17708 /* 48803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16m),
17709 /* 48806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17710 /* 48808 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17711 /* 48810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17712 /* 48813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17713 /* 48819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17714 /* 48825 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17715 /* 48828 */ GIR_RootConstrainSelectedInstOperands,
17716 /* 48829 */ // GIR_Coverage, 4466,
17717 /* 48829 */ GIR_EraseRootFromParent_Done,
17718 /* 48830 */ // Label 1104: @48830
17719 /* 48830 */ GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(48903), // Rule ID 4468 //
17720 /* 48835 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17721 /* 48838 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
17722 /* 48843 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17723 /* 48846 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17724 /* 48849 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17725 /* 48852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17726 /* 48856 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17727 /* 48860 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17728 /* 48864 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3856:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17729 /* 48864 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17730 /* 48867 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17731 /* 48871 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17732 /* 48876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32a),
17733 /* 48879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17734 /* 48881 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17735 /* 48883 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17736 /* 48886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17737 /* 48892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17738 /* 48898 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17739 /* 48901 */ GIR_RootConstrainSelectedInstOperands,
17740 /* 48902 */ // GIR_Coverage, 4468,
17741 /* 48902 */ GIR_EraseRootFromParent_Done,
17742 /* 48903 */ // Label 1105: @48903
17743 /* 48903 */ GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(48976), // Rule ID 4470 //
17744 /* 48908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17745 /* 48911 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
17746 /* 48916 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17747 /* 48919 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17748 /* 48922 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17749 /* 48925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17750 /* 48929 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17751 /* 48933 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17752 /* 48937 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3860:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17753 /* 48937 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17754 /* 48940 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17755 /* 48944 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17756 /* 48949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32n),
17757 /* 48952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17758 /* 48954 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17759 /* 48956 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17760 /* 48959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17761 /* 48965 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17762 /* 48971 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17763 /* 48974 */ GIR_RootConstrainSelectedInstOperands,
17764 /* 48975 */ // GIR_Coverage, 4470,
17765 /* 48975 */ GIR_EraseRootFromParent_Done,
17766 /* 48976 */ // Label 1106: @48976
17767 /* 48976 */ GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(49049), // Rule ID 4472 //
17768 /* 48981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17769 /* 48984 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
17770 /* 48989 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17771 /* 48992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17772 /* 48995 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17773 /* 48998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17774 /* 49002 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17775 /* 49006 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17776 /* 49010 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3862:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17777 /* 49010 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17778 /* 49013 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17779 /* 49017 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17780 /* 49022 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32p),
17781 /* 49025 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17782 /* 49027 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17783 /* 49029 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17784 /* 49032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17785 /* 49038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17786 /* 49044 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17787 /* 49047 */ GIR_RootConstrainSelectedInstOperands,
17788 /* 49048 */ // GIR_Coverage, 4472,
17789 /* 49048 */ GIR_EraseRootFromParent_Done,
17790 /* 49049 */ // Label 1107: @49049
17791 /* 49049 */ GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(49122), // Rule ID 4474 //
17792 /* 49054 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17793 /* 49057 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
17794 /* 49062 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17795 /* 49065 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17796 /* 49068 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17797 /* 49071 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17798 /* 49075 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
17799 /* 49079 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17800 /* 49083 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3858:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTs32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17801 /* 49083 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17802 /* 49086 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17803 /* 49090 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17804 /* 49095 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32m),
17805 /* 49098 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17806 /* 49100 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17807 /* 49102 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17808 /* 49105 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17809 /* 49111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17810 /* 49117 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17811 /* 49120 */ GIR_RootConstrainSelectedInstOperands,
17812 /* 49121 */ // GIR_Coverage, 4474,
17813 /* 49121 */ GIR_EraseRootFromParent_Done,
17814 /* 49122 */ // Label 1108: @49122
17815 /* 49122 */ GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(49195), // Rule ID 4476 //
17816 /* 49127 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17817 /* 49130 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvta),
17818 /* 49135 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17819 /* 49138 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17820 /* 49141 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17821 /* 49144 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17822 /* 49148 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17823 /* 49152 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17824 /* 49156 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3856:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32a:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17825 /* 49156 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17826 /* 49159 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17827 /* 49163 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17828 /* 49168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32a),
17829 /* 49171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17830 /* 49173 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17831 /* 49175 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17832 /* 49178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17833 /* 49184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17834 /* 49190 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17835 /* 49193 */ GIR_RootConstrainSelectedInstOperands,
17836 /* 49194 */ // GIR_Coverage, 4476,
17837 /* 49194 */ GIR_EraseRootFromParent_Done,
17838 /* 49195 */ // Label 1109: @49195
17839 /* 49195 */ GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(49268), // Rule ID 4478 //
17840 /* 49200 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17841 /* 49203 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtn),
17842 /* 49208 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17843 /* 49211 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17844 /* 49214 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17845 /* 49217 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17846 /* 49221 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17847 /* 49225 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17848 /* 49229 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3860:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32n:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17849 /* 49229 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17850 /* 49232 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17851 /* 49236 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17852 /* 49241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32n),
17853 /* 49244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17854 /* 49246 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17855 /* 49248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17856 /* 49251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17857 /* 49257 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17858 /* 49263 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17859 /* 49266 */ GIR_RootConstrainSelectedInstOperands,
17860 /* 49267 */ // GIR_Coverage, 4478,
17861 /* 49267 */ GIR_EraseRootFromParent_Done,
17862 /* 49268 */ // Label 1110: @49268
17863 /* 49268 */ GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(49341), // Rule ID 4480 //
17864 /* 49273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17865 /* 49276 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtp),
17866 /* 49281 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17867 /* 49284 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17868 /* 49287 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17869 /* 49290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17870 /* 49294 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17871 /* 49298 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17872 /* 49302 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3862:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32p:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17873 /* 49302 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17874 /* 49305 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17875 /* 49309 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17876 /* 49314 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32p),
17877 /* 49317 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17878 /* 49319 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17879 /* 49321 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17880 /* 49324 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17881 /* 49330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17882 /* 49336 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17883 /* 49339 */ GIR_RootConstrainSelectedInstOperands,
17884 /* 49340 */ // GIR_Coverage, 4480,
17885 /* 49340 */ GIR_EraseRootFromParent_Done,
17886 /* 49341 */ // Label 1111: @49341
17887 /* 49341 */ GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(49414), // Rule ID 4482 //
17888 /* 49346 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17889 /* 49349 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvtm),
17890 /* 49354 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17891 /* 49357 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
17892 /* 49360 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
17893 /* 49363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17894 /* 49367 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
17895 /* 49371 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17896 /* 49375 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3858:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$in) => (MVE_VCVTu32f32m:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$in)
17897 /* 49375 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17898 /* 49378 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17899 /* 49382 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17900 /* 49387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32m),
17901 /* 49390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17902 /* 49392 */ GIR_RootToRootCopy, /*OpIdx*/3, // in
17903 /* 49394 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17904 /* 49397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17905 /* 49403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17906 /* 49409 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17907 /* 49412 */ GIR_RootConstrainSelectedInstOperands,
17908 /* 49413 */ // GIR_Coverage, 4482,
17909 /* 49413 */ GIR_EraseRootFromParent_Done,
17910 /* 49414 */ // Label 1112: @49414
17911 /* 49414 */ GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(49487), // Rule ID 4485 //
17912 /* 49419 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17913 /* 49422 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp),
17914 /* 49427 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17915 /* 49430 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17916 /* 49433 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17917 /* 49436 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17918 /* 49440 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17919 /* 49444 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17920 /* 49448 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3851:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$src, 0:{ *:[i32] }) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
17921 /* 49448 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17922 /* 49451 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17923 /* 49455 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17924 /* 49460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z),
17925 /* 49463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17926 /* 49465 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17927 /* 49467 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17928 /* 49470 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17929 /* 49476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17930 /* 49482 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17931 /* 49485 */ GIR_RootConstrainSelectedInstOperands,
17932 /* 49486 */ // GIR_Coverage, 4485,
17933 /* 49486 */ GIR_EraseRootFromParent_Done,
17934 /* 49487 */ // Label 1113: @49487
17935 /* 49487 */ GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(49560), // Rule ID 4488 //
17936 /* 49492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17937 /* 49495 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp),
17938 /* 49500 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
17939 /* 49503 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
17940 /* 49506 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17941 /* 49509 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17942 /* 49513 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17943 /* 49517 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
17944 /* 49521 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3851:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$src, 1:{ *:[i32] }) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
17945 /* 49521 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17946 /* 49524 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17947 /* 49528 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17948 /* 49533 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z),
17949 /* 49536 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17950 /* 49538 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17951 /* 49540 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17952 /* 49543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17953 /* 49549 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17954 /* 49555 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17955 /* 49558 */ GIR_RootConstrainSelectedInstOperands,
17956 /* 49559 */ // GIR_Coverage, 4488,
17957 /* 49559 */ GIR_EraseRootFromParent_Done,
17958 /* 49560 */ // Label 1114: @49560
17959 /* 49560 */ GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(49633), // Rule ID 4491 //
17960 /* 49565 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17961 /* 49568 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp),
17962 /* 49573 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17963 /* 49576 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17964 /* 49579 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17965 /* 49582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17966 /* 49586 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17967 /* 49590 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
17968 /* 49594 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3851:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$src, 0:{ *:[i32] }) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
17969 /* 49594 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17970 /* 49597 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17971 /* 49601 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17972 /* 49606 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z),
17973 /* 49609 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17974 /* 49611 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17975 /* 49613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
17976 /* 49616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17977 /* 49622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
17978 /* 49628 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
17979 /* 49631 */ GIR_RootConstrainSelectedInstOperands,
17980 /* 49632 */ // GIR_Coverage, 4491,
17981 /* 49632 */ GIR_EraseRootFromParent_Done,
17982 /* 49633 */ // Label 1115: @49633
17983 /* 49633 */ GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(49706), // Rule ID 4494 //
17984 /* 49638 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
17985 /* 49641 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_int_fp),
17986 /* 49646 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
17987 /* 49649 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
17988 /* 49652 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
17989 /* 49655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17990 /* 49659 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
17991 /* 49663 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
17992 /* 49667 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3851:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$src, 1:{ *:[i32] }) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
17993 /* 49667 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
17994 /* 49670 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
17995 /* 49674 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
17996 /* 49679 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z),
17997 /* 49682 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
17998 /* 49684 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
17999 /* 49686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18000 /* 49689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18001 /* 49695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18002 /* 49701 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18003 /* 49704 */ GIR_RootConstrainSelectedInstOperands,
18004 /* 49705 */ // GIR_Coverage, 4494,
18005 /* 49705 */ GIR_EraseRootFromParent_Done,
18006 /* 49706 */ // Label 1116: @49706
18007 /* 49706 */ GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(49779), // Rule ID 4497 //
18008 /* 49711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
18009 /* 49714 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int),
18010 /* 49719 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
18011 /* 49722 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18012 /* 49725 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18013 /* 49728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18014 /* 49732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18015 /* 49736 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18016 /* 49740 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3849:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 0:{ *:[i32] }) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
18017 /* 49740 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18018 /* 49743 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18019 /* 49747 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18020 /* 49752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n),
18021 /* 49755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
18022 /* 49757 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
18023 /* 49759 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18024 /* 49762 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18025 /* 49768 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18026 /* 49774 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18027 /* 49777 */ GIR_RootConstrainSelectedInstOperands,
18028 /* 49778 */ // GIR_Coverage, 4497,
18029 /* 49778 */ GIR_EraseRootFromParent_Done,
18030 /* 49779 */ // Label 1117: @49779
18031 /* 49779 */ GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(49852), // Rule ID 4500 //
18032 /* 49784 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
18033 /* 49787 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int),
18034 /* 49792 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
18035 /* 49795 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18036 /* 49798 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18037 /* 49801 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18038 /* 49805 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18039 /* 49809 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
18040 /* 49813 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3849:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 1:{ *:[i32] }) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
18041 /* 49813 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18042 /* 49816 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18043 /* 49820 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18044 /* 49825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n),
18045 /* 49828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
18046 /* 49830 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
18047 /* 49832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18048 /* 49835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18049 /* 49841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18050 /* 49847 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18051 /* 49850 */ GIR_RootConstrainSelectedInstOperands,
18052 /* 49851 */ // GIR_Coverage, 4500,
18053 /* 49851 */ GIR_EraseRootFromParent_Done,
18054 /* 49852 */ // Label 1118: @49852
18055 /* 49852 */ GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(49925), // Rule ID 4503 //
18056 /* 49857 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
18057 /* 49860 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int),
18058 /* 49865 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
18059 /* 49868 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
18060 /* 49871 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18061 /* 49874 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18062 /* 49878 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18063 /* 49882 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18064 /* 49886 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3849:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, 0:{ *:[i32] }) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
18065 /* 49886 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18066 /* 49889 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18067 /* 49893 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18068 /* 49898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n),
18069 /* 49901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
18070 /* 49903 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
18071 /* 49905 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18072 /* 49908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18073 /* 49914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18074 /* 49920 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18075 /* 49923 */ GIR_RootConstrainSelectedInstOperands,
18076 /* 49924 */ // GIR_Coverage, 4503,
18077 /* 49924 */ GIR_EraseRootFromParent_Done,
18078 /* 49925 */ // Label 1119: @49925
18079 /* 49925 */ GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(49998), // Rule ID 4506 //
18080 /* 49930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
18081 /* 49933 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fp_int),
18082 /* 49938 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
18083 /* 49941 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
18084 /* 49944 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18085 /* 49947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18086 /* 49951 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18087 /* 49955 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
18088 /* 49959 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3849:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, 1:{ *:[i32] }) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
18089 /* 49959 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18090 /* 49962 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18091 /* 49966 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18092 /* 49971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n),
18093 /* 49974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
18094 /* 49976 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
18095 /* 49978 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18096 /* 49981 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18097 /* 49987 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18098 /* 49993 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18099 /* 49996 */ GIR_RootConstrainSelectedInstOperands,
18100 /* 49997 */ // GIR_Coverage, 4506,
18101 /* 49997 */ GIR_EraseRootFromParent_Done,
18102 /* 49998 */ // Label 1120: @49998
18103 /* 49998 */ GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(50071), // Rule ID 4986 //
18104 /* 50003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
18105 /* 50006 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen),
18106 /* 50011 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
18107 /* 50014 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18108 /* 50017 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18109 /* 50020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18110 /* 50024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18111 /* 50028 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
18112 /* 50032 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3854:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf32f16bh:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm)
18113 /* 50032 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18114 /* 50035 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18115 /* 50039 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18116 /* 50044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16bh),
18117 /* 50047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
18118 /* 50049 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
18119 /* 50051 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18120 /* 50054 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18121 /* 50060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18122 /* 50066 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18123 /* 50069 */ GIR_RootConstrainSelectedInstOperands,
18124 /* 50070 */ // GIR_Coverage, 4986,
18125 /* 50070 */ GIR_EraseRootFromParent_Done,
18126 /* 50071 */ // Label 1121: @50071
18127 /* 50071 */ GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(50144), // Rule ID 4992 //
18128 /* 50076 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
18129 /* 50079 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_widen),
18130 /* 50084 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
18131 /* 50087 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18132 /* 50090 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18133 /* 50093 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18134 /* 50097 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18135 /* 50101 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
18136 /* 50105 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3854:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf32f16th:{ *:[v4f32] } MQPR:{ *:[v8f16] }:$Qm)
18137 /* 50105 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18138 /* 50108 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18139 /* 50112 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18140 /* 50117 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32f16th),
18141 /* 50120 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
18142 /* 50122 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
18143 /* 50124 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18144 /* 50127 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18145 /* 50133 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18146 /* 50139 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18147 /* 50142 */ GIR_RootConstrainSelectedInstOperands,
18148 /* 50143 */ // GIR_Coverage, 4992,
18149 /* 50143 */ GIR_EraseRootFromParent_Done,
18150 /* 50144 */ // Label 1122: @50144
18151 /* 50144 */ GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(50212), // Rule ID 2042 //
18152 /* 50149 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
18153 /* 50152 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
18154 /* 50157 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18155 /* 50160 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18156 /* 50163 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18157 /* 50166 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18158 /* 50170 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18159 /* 50174 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18160 /* 50178 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18161 /* 50182 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
18162 /* 50186 */ // MIs[1] Operand 1
18163 /* 50186 */ // No operand predicates
18164 /* 50186 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18165 /* 50188 */ // (intrinsic_wo_chain:{ *:[i32] } 4180:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPRnopc:{ *:[i32] }:$a, 0:{ *:[i32] })
18166 /* 50188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT),
18167 /* 50191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18168 /* 50193 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
18169 /* 50196 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
18170 /* 50198 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18171 /* 50201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18172 /* 50204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18173 /* 50210 */ GIR_RootConstrainSelectedInstOperands,
18174 /* 50211 */ // GIR_Coverage, 2042,
18175 /* 50211 */ GIR_EraseRootFromParent_Done,
18176 /* 50212 */ // Label 1123: @50212
18177 /* 50212 */ GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(50277), // Rule ID 2046 //
18178 /* 50217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
18179 /* 50220 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16),
18180 /* 50225 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18181 /* 50228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18182 /* 50231 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18183 /* 50234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18184 /* 50238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18185 /* 50242 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18186 /* 50246 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18187 /* 50250 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
18188 /* 50254 */ // MIs[1] Operand 1
18189 /* 50254 */ // No operand predicates
18190 /* 50254 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18191 /* 50256 */ // (intrinsic_wo_chain:{ *:[i32] } 4181:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPRnopc:{ *:[i32] }:$a)
18192 /* 50256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAT16),
18193 /* 50259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18194 /* 50261 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
18195 /* 50264 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
18196 /* 50266 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18197 /* 50269 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18198 /* 50275 */ GIR_RootConstrainSelectedInstOperands,
18199 /* 50276 */ // GIR_Coverage, 2046,
18200 /* 50276 */ GIR_EraseRootFromParent_Done,
18201 /* 50277 */ // Label 1124: @50277
18202 /* 50277 */ GIM_Try, /*On fail goto*//*Label 1125*/ GIMT_Encode4(50345), // Rule ID 2310 //
18203 /* 50282 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
18204 /* 50285 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat),
18205 /* 50290 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18206 /* 50293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18207 /* 50296 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18208 /* 50299 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18209 /* 50303 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
18210 /* 50307 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18211 /* 50311 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18212 /* 50315 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
18213 /* 50319 */ // MIs[1] Operand 1
18214 /* 50319 */ // No operand predicates
18215 /* 50319 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18216 /* 50321 */ // (intrinsic_wo_chain:{ *:[i32] } 4180:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos) => (t2USAT:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$pos, GPR:{ *:[i32] }:$a, 0:{ *:[i32] })
18217 /* 50321 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT),
18218 /* 50324 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18219 /* 50326 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
18220 /* 50329 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
18221 /* 50331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18222 /* 50334 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18223 /* 50337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18224 /* 50343 */ GIR_RootConstrainSelectedInstOperands,
18225 /* 50344 */ // GIR_Coverage, 2310,
18226 /* 50344 */ GIR_EraseRootFromParent_Done,
18227 /* 50345 */ // Label 1125: @50345
18228 /* 50345 */ GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(50410), // Rule ID 2312 //
18229 /* 50350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
18230 /* 50353 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usat16),
18231 /* 50358 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18232 /* 50361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18233 /* 50364 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18234 /* 50367 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18235 /* 50371 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
18236 /* 50375 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18237 /* 50379 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18238 /* 50383 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
18239 /* 50387 */ // MIs[1] Operand 1
18240 /* 50387 */ // No operand predicates
18241 /* 50387 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18242 /* 50389 */ // (intrinsic_wo_chain:{ *:[i32] } 4181:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos) => (t2USAT16:{ *:[i32] } (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$pos, GPR:{ *:[i32] }:$a)
18243 /* 50389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAT16),
18244 /* 50392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18245 /* 50394 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // pos
18246 /* 50397 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
18247 /* 50399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18248 /* 50402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18249 /* 50408 */ GIR_RootConstrainSelectedInstOperands,
18250 /* 50409 */ // GIR_Coverage, 2312,
18251 /* 50409 */ GIR_EraseRootFromParent_Done,
18252 /* 50410 */ // Label 1126: @50410
18253 /* 50410 */ GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(50493), // Rule ID 4286 //
18254 /* 50415 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm),
18255 /* 50420 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
18256 /* 50423 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
18257 /* 50426 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18258 /* 50429 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18259 /* 50433 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18260 /* 50437 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18261 /* 50441 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18262 /* 50445 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
18263 /* 50449 */ // MIs[1] Operand 1
18264 /* 50449 */ // No operand predicates
18265 /* 50449 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18266 /* 50451 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3918:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) => (MVE_VQSHLU_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
18267 /* 50451 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18268 /* 50454 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18269 /* 50458 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18270 /* 50463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms8),
18271 /* 50466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
18272 /* 50468 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
18273 /* 50470 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
18274 /* 50473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18275 /* 50476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18276 /* 50482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18277 /* 50488 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18278 /* 50491 */ GIR_RootConstrainSelectedInstOperands,
18279 /* 50492 */ // GIR_Coverage, 4286,
18280 /* 50492 */ GIR_EraseRootFromParent_Done,
18281 /* 50493 */ // Label 1127: @50493
18282 /* 50493 */ GIM_Try, /*On fail goto*//*Label 1128*/ GIMT_Encode4(50576), // Rule ID 4288 //
18283 /* 50498 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm),
18284 /* 50503 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
18285 /* 50506 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18286 /* 50509 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18287 /* 50512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18288 /* 50516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18289 /* 50520 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18290 /* 50524 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18291 /* 50528 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
18292 /* 50532 */ // MIs[1] Operand 1
18293 /* 50532 */ // No operand predicates
18294 /* 50532 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18295 /* 50534 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3918:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (MVE_VQSHLU_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
18296 /* 50534 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18297 /* 50537 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18298 /* 50541 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18299 /* 50546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms16),
18300 /* 50549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
18301 /* 50551 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
18302 /* 50553 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
18303 /* 50556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18304 /* 50559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18305 /* 50565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18306 /* 50571 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18307 /* 50574 */ GIR_RootConstrainSelectedInstOperands,
18308 /* 50575 */ // GIR_Coverage, 4288,
18309 /* 50575 */ GIR_EraseRootFromParent_Done,
18310 /* 50576 */ // Label 1128: @50576
18311 /* 50576 */ GIM_Try, /*On fail goto*//*Label 1129*/ GIMT_Encode4(50659), // Rule ID 4290 //
18312 /* 50581 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshlu_imm),
18313 /* 50586 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
18314 /* 50589 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
18315 /* 50592 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18316 /* 50595 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18317 /* 50599 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
18318 /* 50603 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18319 /* 50607 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18320 /* 50611 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
18321 /* 50615 */ // MIs[1] Operand 1
18322 /* 50615 */ // No operand predicates
18323 /* 50615 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18324 /* 50617 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3918:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) => (MVE_VQSHLU_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
18325 /* 50617 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
18326 /* 50620 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
18327 /* 50624 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
18328 /* 50629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLU_imms32),
18329 /* 50632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
18330 /* 50634 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
18331 /* 50636 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
18332 /* 50639 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
18333 /* 50642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18334 /* 50648 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18335 /* 50654 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
18336 /* 50657 */ GIR_RootConstrainSelectedInstOperands,
18337 /* 50658 */ // GIR_Coverage, 4290,
18338 /* 50658 */ GIR_EraseRootFromParent_Done,
18339 /* 50659 */ // Label 1129: @50659
18340 /* 50659 */ GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(50720), // Rule ID 1813 //
18341 /* 50664 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18342 /* 50667 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
18343 /* 50672 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
18344 /* 50675 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
18345 /* 50678 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18346 /* 50681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18347 /* 50685 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18348 /* 50689 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18349 /* 50693 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18350 /* 50697 */ // MIs[1] Operand 1
18351 /* 50697 */ // No operand predicates
18352 /* 50697 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18353 /* 50699 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4002:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18354 /* 50699 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsd),
18355 /* 50702 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18356 /* 50704 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18357 /* 50706 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18358 /* 50709 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18359 /* 50712 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18360 /* 50718 */ GIR_RootConstrainSelectedInstOperands,
18361 /* 50719 */ // GIR_Coverage, 1813,
18362 /* 50719 */ GIR_EraseRootFromParent_Done,
18363 /* 50720 */ // Label 1130: @50720
18364 /* 50720 */ GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(50781), // Rule ID 1814 //
18365 /* 50725 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18366 /* 50728 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
18367 /* 50733 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
18368 /* 50736 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
18369 /* 50739 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18370 /* 50742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18371 /* 50746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18372 /* 50750 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18373 /* 50754 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18374 /* 50758 */ // MIs[1] Operand 1
18375 /* 50758 */ // No operand predicates
18376 /* 50758 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18377 /* 50760 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4003:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18378 /* 50760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xud),
18379 /* 50763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18380 /* 50765 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18381 /* 50767 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18382 /* 50770 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18383 /* 50773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18384 /* 50779 */ GIR_RootConstrainSelectedInstOperands,
18385 /* 50780 */ // GIR_Coverage, 1814,
18386 /* 50780 */ GIR_EraseRootFromParent_Done,
18387 /* 50781 */ // Label 1131: @50781
18388 /* 50781 */ GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(50842), // Rule ID 1815 //
18389 /* 50786 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18390 /* 50789 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
18391 /* 50794 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
18392 /* 50797 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
18393 /* 50800 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18394 /* 50803 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18395 /* 50807 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18396 /* 50811 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18397 /* 50815 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18398 /* 50819 */ // MIs[1] Operand 1
18399 /* 50819 */ // No operand predicates
18400 /* 50819 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18401 /* 50821 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4005:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18402 /* 50821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fd),
18403 /* 50824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18404 /* 50826 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18405 /* 50828 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18406 /* 50831 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18407 /* 50834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18408 /* 50840 */ GIR_RootConstrainSelectedInstOperands,
18409 /* 50841 */ // GIR_Coverage, 1815,
18410 /* 50841 */ GIR_EraseRootFromParent_Done,
18411 /* 50842 */ // Label 1132: @50842
18412 /* 50842 */ GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(50903), // Rule ID 1816 //
18413 /* 50847 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18414 /* 50850 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
18415 /* 50855 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
18416 /* 50858 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
18417 /* 50861 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18418 /* 50864 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18419 /* 50868 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18420 /* 50872 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18421 /* 50876 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18422 /* 50880 */ // MIs[1] Operand 1
18423 /* 50880 */ // No operand predicates
18424 /* 50880 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18425 /* 50882 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4006:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18426 /* 50882 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fd),
18427 /* 50885 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18428 /* 50887 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18429 /* 50889 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18430 /* 50892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18431 /* 50895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18432 /* 50901 */ GIR_RootConstrainSelectedInstOperands,
18433 /* 50902 */ // GIR_Coverage, 1816,
18434 /* 50902 */ GIR_EraseRootFromParent_Done,
18435 /* 50903 */ // Label 1133: @50903
18436 /* 50903 */ GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(50964), // Rule ID 1817 //
18437 /* 50908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18438 /* 50911 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
18439 /* 50916 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
18440 /* 50919 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
18441 /* 50922 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18442 /* 50925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18443 /* 50929 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18444 /* 50933 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18445 /* 50937 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18446 /* 50941 */ // MIs[1] Operand 1
18447 /* 50941 */ // No operand predicates
18448 /* 50941 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18449 /* 50943 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4002:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18450 /* 50943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsd),
18451 /* 50946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18452 /* 50948 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18453 /* 50950 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18454 /* 50953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18455 /* 50956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18456 /* 50962 */ GIR_RootConstrainSelectedInstOperands,
18457 /* 50963 */ // GIR_Coverage, 1817,
18458 /* 50963 */ GIR_EraseRootFromParent_Done,
18459 /* 50964 */ // Label 1134: @50964
18460 /* 50964 */ GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(51025), // Rule ID 1818 //
18461 /* 50969 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18462 /* 50972 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
18463 /* 50977 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
18464 /* 50980 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
18465 /* 50983 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18466 /* 50986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18467 /* 50990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18468 /* 50994 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18469 /* 50998 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18470 /* 51002 */ // MIs[1] Operand 1
18471 /* 51002 */ // No operand predicates
18472 /* 51002 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18473 /* 51004 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4003:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18474 /* 51004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xud),
18475 /* 51007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18476 /* 51009 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18477 /* 51011 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18478 /* 51014 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18479 /* 51017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18480 /* 51023 */ GIR_RootConstrainSelectedInstOperands,
18481 /* 51024 */ // GIR_Coverage, 1818,
18482 /* 51024 */ GIR_EraseRootFromParent_Done,
18483 /* 51025 */ // Label 1135: @51025
18484 /* 51025 */ GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(51086), // Rule ID 1819 //
18485 /* 51030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18486 /* 51033 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
18487 /* 51038 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
18488 /* 51041 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
18489 /* 51044 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18490 /* 51047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18491 /* 51051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18492 /* 51055 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18493 /* 51059 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18494 /* 51063 */ // MIs[1] Operand 1
18495 /* 51063 */ // No operand predicates
18496 /* 51063 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18497 /* 51065 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4005:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18498 /* 51065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hd),
18499 /* 51068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18500 /* 51070 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18501 /* 51072 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18502 /* 51075 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18503 /* 51078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18504 /* 51084 */ GIR_RootConstrainSelectedInstOperands,
18505 /* 51085 */ // GIR_Coverage, 1819,
18506 /* 51085 */ GIR_EraseRootFromParent_Done,
18507 /* 51086 */ // Label 1136: @51086
18508 /* 51086 */ GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(51147), // Rule ID 1820 //
18509 /* 51091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18510 /* 51094 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
18511 /* 51099 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
18512 /* 51102 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
18513 /* 51105 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18514 /* 51108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18515 /* 51112 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
18516 /* 51116 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18517 /* 51120 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18518 /* 51124 */ // MIs[1] Operand 1
18519 /* 51124 */ // No operand predicates
18520 /* 51124 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18521 /* 51126 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4006:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18522 /* 51126 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hd),
18523 /* 51129 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18524 /* 51131 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18525 /* 51133 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18526 /* 51136 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18527 /* 51139 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18528 /* 51145 */ GIR_RootConstrainSelectedInstOperands,
18529 /* 51146 */ // GIR_Coverage, 1820,
18530 /* 51146 */ GIR_EraseRootFromParent_Done,
18531 /* 51147 */ // Label 1137: @51147
18532 /* 51147 */ GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(51208), // Rule ID 1821 //
18533 /* 51152 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18534 /* 51155 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
18535 /* 51160 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
18536 /* 51163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
18537 /* 51166 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18538 /* 51169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18539 /* 51173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18540 /* 51177 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18541 /* 51181 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18542 /* 51185 */ // MIs[1] Operand 1
18543 /* 51185 */ // No operand predicates
18544 /* 51185 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18545 /* 51187 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4002:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xsq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18546 /* 51187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xsq),
18547 /* 51190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18548 /* 51192 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18549 /* 51194 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18550 /* 51197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18551 /* 51200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18552 /* 51206 */ GIR_RootConstrainSelectedInstOperands,
18553 /* 51207 */ // GIR_Coverage, 1821,
18554 /* 51207 */ GIR_EraseRootFromParent_Done,
18555 /* 51208 */ // Label 1138: @51208
18556 /* 51208 */ GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(51269), // Rule ID 1822 //
18557 /* 51213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18558 /* 51216 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
18559 /* 51221 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
18560 /* 51224 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
18561 /* 51227 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18562 /* 51230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18563 /* 51234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18564 /* 51238 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18565 /* 51242 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18566 /* 51246 */ // MIs[1] Operand 1
18567 /* 51246 */ // No operand predicates
18568 /* 51246 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18569 /* 51248 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4003:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTf2xuq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18570 /* 51248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2xuq),
18571 /* 51251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18572 /* 51253 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18573 /* 51255 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18574 /* 51258 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18575 /* 51261 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18576 /* 51267 */ GIR_RootConstrainSelectedInstOperands,
18577 /* 51268 */ // GIR_Coverage, 1822,
18578 /* 51268 */ GIR_EraseRootFromParent_Done,
18579 /* 51269 */ // Label 1139: @51269
18580 /* 51269 */ GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(51330), // Rule ID 1823 //
18581 /* 51274 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18582 /* 51277 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
18583 /* 51282 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
18584 /* 51285 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
18585 /* 51288 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18586 /* 51291 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18587 /* 51295 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18588 /* 51299 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18589 /* 51303 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18590 /* 51307 */ // MIs[1] Operand 1
18591 /* 51307 */ // No operand predicates
18592 /* 51307 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18593 /* 51309 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4005:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18594 /* 51309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2fq),
18595 /* 51312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18596 /* 51314 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18597 /* 51316 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18598 /* 51319 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18599 /* 51322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18600 /* 51328 */ GIR_RootConstrainSelectedInstOperands,
18601 /* 51329 */ // GIR_Coverage, 1823,
18602 /* 51329 */ GIR_EraseRootFromParent_Done,
18603 /* 51330 */ // Label 1140: @51330
18604 /* 51330 */ GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(51391), // Rule ID 1824 //
18605 /* 51335 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
18606 /* 51338 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
18607 /* 51343 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
18608 /* 51346 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
18609 /* 51349 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18610 /* 51352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18611 /* 51356 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18612 /* 51360 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18613 /* 51364 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18614 /* 51368 */ // MIs[1] Operand 1
18615 /* 51368 */ // No operand predicates
18616 /* 51368 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18617 /* 51370 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4006:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18618 /* 51370 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2fq),
18619 /* 51373 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18620 /* 51375 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18621 /* 51377 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18622 /* 51380 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18623 /* 51383 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18624 /* 51389 */ GIR_RootConstrainSelectedInstOperands,
18625 /* 51390 */ // GIR_Coverage, 1824,
18626 /* 51390 */ GIR_EraseRootFromParent_Done,
18627 /* 51391 */ // Label 1141: @51391
18628 /* 51391 */ GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(51452), // Rule ID 1825 //
18629 /* 51396 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18630 /* 51399 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxs),
18631 /* 51404 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
18632 /* 51407 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18633 /* 51410 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18634 /* 51413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18635 /* 51417 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18636 /* 51421 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18637 /* 51425 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18638 /* 51429 */ // MIs[1] Operand 1
18639 /* 51429 */ // No operand predicates
18640 /* 51429 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18641 /* 51431 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4002:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xsq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18642 /* 51431 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xsq),
18643 /* 51434 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18644 /* 51436 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18645 /* 51438 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18646 /* 51441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18647 /* 51444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18648 /* 51450 */ GIR_RootConstrainSelectedInstOperands,
18649 /* 51451 */ // GIR_Coverage, 1825,
18650 /* 51451 */ GIR_EraseRootFromParent_Done,
18651 /* 51452 */ // Label 1142: @51452
18652 /* 51452 */ GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(51513), // Rule ID 1826 //
18653 /* 51457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18654 /* 51460 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfp2fxu),
18655 /* 51465 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
18656 /* 51468 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18657 /* 51471 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18658 /* 51474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18659 /* 51478 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18660 /* 51482 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18661 /* 51486 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18662 /* 51490 */ // MIs[1] Operand 1
18663 /* 51490 */ // No operand predicates
18664 /* 51490 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18665 /* 51492 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4003:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTh2xuq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18666 /* 51492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2xuq),
18667 /* 51495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18668 /* 51497 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18669 /* 51499 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18670 /* 51502 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18671 /* 51505 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18672 /* 51511 */ GIR_RootConstrainSelectedInstOperands,
18673 /* 51512 */ // GIR_Coverage, 1826,
18674 /* 51512 */ GIR_EraseRootFromParent_Done,
18675 /* 51513 */ // Label 1143: @51513
18676 /* 51513 */ GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(51574), // Rule ID 1827 //
18677 /* 51518 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18678 /* 51521 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxs2fp),
18679 /* 51526 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
18680 /* 51529 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18681 /* 51532 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18682 /* 51535 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18683 /* 51539 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18684 /* 51543 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18685 /* 51547 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18686 /* 51551 */ // MIs[1] Operand 1
18687 /* 51551 */ // No operand predicates
18688 /* 51551 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18689 /* 51553 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4005:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18690 /* 51553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxs2hq),
18691 /* 51556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18692 /* 51558 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18693 /* 51560 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18694 /* 51563 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18695 /* 51566 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18696 /* 51572 */ GIR_RootConstrainSelectedInstOperands,
18697 /* 51573 */ // GIR_Coverage, 1827,
18698 /* 51573 */ GIR_EraseRootFromParent_Done,
18699 /* 51574 */ // Label 1144: @51574
18700 /* 51574 */ GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(51635), // Rule ID 1828 //
18701 /* 51579 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
18702 /* 51582 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcvtfxu2fp),
18703 /* 51587 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
18704 /* 51590 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
18705 /* 51593 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18706 /* 51596 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18707 /* 51600 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
18708 /* 51604 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18709 /* 51608 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18710 /* 51612 */ // MIs[1] Operand 1
18711 /* 51612 */ // No operand predicates
18712 /* 51612 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18713 /* 51614 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4006:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM) => (VCVTxu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm, (imm:{ *:[i32] }):$SIMM)
18714 /* 51614 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTxu2hq),
18715 /* 51617 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
18716 /* 51619 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
18717 /* 51621 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // SIMM
18718 /* 51624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18719 /* 51627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18720 /* 51633 */ GIR_RootConstrainSelectedInstOperands,
18721 /* 51634 */ // GIR_Coverage, 1828,
18722 /* 51634 */ GIR_EraseRootFromParent_Done,
18723 /* 51635 */ // Label 1145: @51635
18724 /* 51635 */ GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(51696), // Rule ID 1886 //
18725 /* 51640 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
18726 /* 51643 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqshl),
18727 /* 51648 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18728 /* 51651 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18729 /* 51654 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18730 /* 51657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18731 /* 51661 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18732 /* 51665 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18733 /* 51669 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18734 /* 51673 */ // MIs[1] Operand 1
18735 /* 51673 */ // No operand predicates
18736 /* 51673 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18737 /* 51675 */ // (intrinsic_wo_chain:{ *:[i32] } 3817:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
18738 /* 51675 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQSHL),
18739 /* 51678 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
18740 /* 51680 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
18741 /* 51682 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
18742 /* 51685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18743 /* 51688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18744 /* 51694 */ GIR_RootConstrainSelectedInstOperands,
18745 /* 51695 */ // GIR_Coverage, 1886,
18746 /* 51695 */ GIR_EraseRootFromParent_Done,
18747 /* 51696 */ // Label 1146: @51696
18748 /* 51696 */ GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(51757), // Rule ID 1887 //
18749 /* 51701 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
18750 /* 51704 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_srshr),
18751 /* 51709 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18752 /* 51712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18753 /* 51715 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18754 /* 51718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18755 /* 51722 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18756 /* 51726 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18757 /* 51730 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18758 /* 51734 */ // MIs[1] Operand 1
18759 /* 51734 */ // No operand predicates
18760 /* 51734 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18761 /* 51736 */ // (intrinsic_wo_chain:{ *:[i32] } 3819:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_SRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
18762 /* 51736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SRSHR),
18763 /* 51739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
18764 /* 51741 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
18765 /* 51743 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
18766 /* 51746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18767 /* 51749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18768 /* 51755 */ GIR_RootConstrainSelectedInstOperands,
18769 /* 51756 */ // GIR_Coverage, 1887,
18770 /* 51756 */ GIR_EraseRootFromParent_Done,
18771 /* 51757 */ // Label 1147: @51757
18772 /* 51757 */ GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(51818), // Rule ID 1888 //
18773 /* 51762 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
18774 /* 51765 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqshl),
18775 /* 51770 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18776 /* 51773 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18777 /* 51776 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18778 /* 51779 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18779 /* 51783 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18780 /* 51787 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18781 /* 51791 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18782 /* 51795 */ // MIs[1] Operand 1
18783 /* 51795 */ // No operand predicates
18784 /* 51795 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18785 /* 51797 */ // (intrinsic_wo_chain:{ *:[i32] } 3824:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_UQSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
18786 /* 51797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQSHL),
18787 /* 51800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
18788 /* 51802 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
18789 /* 51804 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
18790 /* 51807 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18791 /* 51810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18792 /* 51816 */ GIR_RootConstrainSelectedInstOperands,
18793 /* 51817 */ // GIR_Coverage, 1888,
18794 /* 51817 */ GIR_EraseRootFromParent_Done,
18795 /* 51818 */ // Label 1148: @51818
18796 /* 51818 */ GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(51879), // Rule ID 1889 //
18797 /* 51823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
18798 /* 51826 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_urshr),
18799 /* 51831 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18800 /* 51834 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18801 /* 51837 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18802 /* 51840 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18803 /* 51844 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
18804 /* 51848 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
18805 /* 51852 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
18806 /* 51856 */ // MIs[1] Operand 1
18807 /* 51856 */ // No operand predicates
18808 /* 51856 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
18809 /* 51858 */ // (intrinsic_wo_chain:{ *:[i32] } 3826:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm) => (MVE_URSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, (imm:{ *:[i32] }):$imm)
18810 /* 51858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_URSHR),
18811 /* 51861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
18812 /* 51863 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
18813 /* 51865 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
18814 /* 51868 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18815 /* 51871 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18816 /* 51877 */ GIR_RootConstrainSelectedInstOperands,
18817 /* 51878 */ // GIR_Coverage, 1889,
18818 /* 51878 */ GIR_EraseRootFromParent_Done,
18819 /* 51879 */ // Label 1149: @51879
18820 /* 51879 */ GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(51933), // Rule ID 104 //
18821 /* 51884 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18822 /* 51887 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8),
18823 /* 51892 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18824 /* 51895 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18825 /* 51898 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18826 /* 51901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18827 /* 51905 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18828 /* 51909 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18829 /* 51913 */ // (intrinsic_wo_chain:{ *:[i32] } 4105:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18830 /* 51913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD8),
18831 /* 51916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18832 /* 51918 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18833 /* 51920 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18834 /* 51922 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18835 /* 51925 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18836 /* 51931 */ GIR_RootConstrainSelectedInstOperands,
18837 /* 51932 */ // GIR_Coverage, 104,
18838 /* 51932 */ GIR_EraseRootFromParent_Done,
18839 /* 51933 */ // Label 1150: @51933
18840 /* 51933 */ GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(51987), // Rule ID 105 //
18841 /* 51938 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18842 /* 51941 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16),
18843 /* 51946 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18844 /* 51949 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18845 /* 51952 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18846 /* 51955 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18847 /* 51959 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18848 /* 51963 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18849 /* 51967 */ // (intrinsic_wo_chain:{ *:[i32] } 4104:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18850 /* 51967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD16),
18851 /* 51970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18852 /* 51972 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18853 /* 51974 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18854 /* 51976 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18855 /* 51979 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18856 /* 51985 */ GIR_RootConstrainSelectedInstOperands,
18857 /* 51986 */ // GIR_Coverage, 105,
18858 /* 51986 */ GIR_EraseRootFromParent_Done,
18859 /* 51987 */ // Label 1151: @51987
18860 /* 51987 */ GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(52041), // Rule ID 106 //
18861 /* 51992 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18862 /* 51995 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16),
18863 /* 52000 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18864 /* 52003 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18865 /* 52006 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18866 /* 52009 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18867 /* 52013 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18868 /* 52017 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18869 /* 52021 */ // (intrinsic_wo_chain:{ *:[i32] } 4109:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18870 /* 52021 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB16),
18871 /* 52024 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18872 /* 52026 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18873 /* 52028 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18874 /* 52030 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18875 /* 52033 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18876 /* 52039 */ GIR_RootConstrainSelectedInstOperands,
18877 /* 52040 */ // GIR_Coverage, 106,
18878 /* 52040 */ GIR_EraseRootFromParent_Done,
18879 /* 52041 */ // Label 1152: @52041
18880 /* 52041 */ GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(52095), // Rule ID 107 //
18881 /* 52046 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18882 /* 52049 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8),
18883 /* 52054 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18884 /* 52057 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18885 /* 52060 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18886 /* 52063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18887 /* 52067 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18888 /* 52071 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18889 /* 52075 */ // (intrinsic_wo_chain:{ *:[i32] } 4110:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18890 /* 52075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB8),
18891 /* 52078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18892 /* 52080 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18893 /* 52082 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18894 /* 52084 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18895 /* 52087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18896 /* 52093 */ GIR_RootConstrainSelectedInstOperands,
18897 /* 52094 */ // GIR_Coverage, 107,
18898 /* 52094 */ GIR_EraseRootFromParent_Done,
18899 /* 52095 */ // Label 1153: @52095
18900 /* 52095 */ GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(52149), // Rule ID 110 //
18901 /* 52100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18902 /* 52103 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
18903 /* 52108 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18904 /* 52111 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18905 /* 52114 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18906 /* 52117 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18907 /* 52121 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18908 /* 52125 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18909 /* 52129 */ // (intrinsic_wo_chain:{ *:[i32] } 4108:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QSUB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
18910 /* 52129 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB),
18911 /* 52132 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18912 /* 52134 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
18913 /* 52136 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
18914 /* 52138 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18915 /* 52141 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18916 /* 52147 */ GIR_RootConstrainSelectedInstOperands,
18917 /* 52148 */ // GIR_Coverage, 110,
18918 /* 52148 */ GIR_EraseRootFromParent_Done,
18919 /* 52149 */ // Label 1154: @52149
18920 /* 52149 */ GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(52203), // Rule ID 111 //
18921 /* 52154 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18922 /* 52157 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
18923 /* 52162 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18924 /* 52165 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18925 /* 52168 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18926 /* 52171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18927 /* 52175 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18928 /* 52179 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18929 /* 52183 */ // (intrinsic_wo_chain:{ *:[i32] } 4103:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn) => (QADD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Rn)
18930 /* 52183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD),
18931 /* 52186 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18932 /* 52188 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
18933 /* 52190 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
18934 /* 52192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18935 /* 52195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18936 /* 52201 */ GIR_RootConstrainSelectedInstOperands,
18937 /* 52202 */ // GIR_Coverage, 111,
18938 /* 52202 */ GIR_EraseRootFromParent_Done,
18939 /* 52203 */ // Label 1155: @52203
18940 /* 52203 */ GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(52257), // Rule ID 112 //
18941 /* 52208 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18942 /* 52211 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16),
18943 /* 52216 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18944 /* 52219 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18945 /* 52222 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18946 /* 52225 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18947 /* 52229 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18948 /* 52233 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18949 /* 52237 */ // (intrinsic_wo_chain:{ *:[i32] } 4172:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18950 /* 52237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD16),
18951 /* 52240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18952 /* 52242 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18953 /* 52244 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18954 /* 52246 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18955 /* 52249 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18956 /* 52255 */ GIR_RootConstrainSelectedInstOperands,
18957 /* 52256 */ // GIR_Coverage, 112,
18958 /* 52256 */ GIR_EraseRootFromParent_Done,
18959 /* 52257 */ // Label 1156: @52257
18960 /* 52257 */ GIM_Try, /*On fail goto*//*Label 1157*/ GIMT_Encode4(52311), // Rule ID 113 //
18961 /* 52262 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18962 /* 52265 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8),
18963 /* 52270 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18964 /* 52273 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18965 /* 52276 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18966 /* 52279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18967 /* 52283 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18968 /* 52287 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18969 /* 52291 */ // (intrinsic_wo_chain:{ *:[i32] } 4173:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18970 /* 52291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQADD8),
18971 /* 52294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18972 /* 52296 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18973 /* 52298 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18974 /* 52300 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18975 /* 52303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18976 /* 52309 */ GIR_RootConstrainSelectedInstOperands,
18977 /* 52310 */ // GIR_Coverage, 113,
18978 /* 52310 */ GIR_EraseRootFromParent_Done,
18979 /* 52311 */ // Label 1157: @52311
18980 /* 52311 */ GIM_Try, /*On fail goto*//*Label 1158*/ GIMT_Encode4(52365), // Rule ID 114 //
18981 /* 52316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
18982 /* 52319 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16),
18983 /* 52324 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
18984 /* 52327 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
18985 /* 52330 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
18986 /* 52333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18987 /* 52337 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18988 /* 52341 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
18989 /* 52345 */ // (intrinsic_wo_chain:{ *:[i32] } 4176:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
18990 /* 52345 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB16),
18991 /* 52348 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
18992 /* 52350 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
18993 /* 52352 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
18994 /* 52354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
18995 /* 52357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
18996 /* 52363 */ GIR_RootConstrainSelectedInstOperands,
18997 /* 52364 */ // GIR_Coverage, 114,
18998 /* 52364 */ GIR_EraseRootFromParent_Done,
18999 /* 52365 */ // Label 1158: @52365
19000 /* 52365 */ GIM_Try, /*On fail goto*//*Label 1159*/ GIMT_Encode4(52419), // Rule ID 115 //
19001 /* 52370 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19002 /* 52373 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8),
19003 /* 52378 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19004 /* 52381 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19005 /* 52384 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19006 /* 52387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19007 /* 52391 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19008 /* 52395 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19009 /* 52399 */ // (intrinsic_wo_chain:{ *:[i32] } 4177:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19010 /* 52399 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSUB8),
19011 /* 52402 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19012 /* 52404 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19013 /* 52406 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19014 /* 52408 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19015 /* 52411 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19016 /* 52417 */ GIR_RootConstrainSelectedInstOperands,
19017 /* 52418 */ // GIR_Coverage, 115,
19018 /* 52418 */ GIR_EraseRootFromParent_Done,
19019 /* 52419 */ // Label 1159: @52419
19020 /* 52419 */ GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(52473), // Rule ID 116 //
19021 /* 52424 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19022 /* 52427 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx),
19023 /* 52432 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19024 /* 52435 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19025 /* 52438 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19026 /* 52441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19027 /* 52445 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19028 /* 52449 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19029 /* 52453 */ // (intrinsic_wo_chain:{ *:[i32] } 4106:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19030 /* 52453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QASX),
19031 /* 52456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19032 /* 52458 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19033 /* 52460 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19034 /* 52462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19035 /* 52465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19036 /* 52471 */ GIR_RootConstrainSelectedInstOperands,
19037 /* 52472 */ // GIR_Coverage, 116,
19038 /* 52472 */ GIR_EraseRootFromParent_Done,
19039 /* 52473 */ // Label 1160: @52473
19040 /* 52473 */ GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(52527), // Rule ID 117 //
19041 /* 52478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19042 /* 52481 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax),
19043 /* 52486 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19044 /* 52489 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19045 /* 52492 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19046 /* 52495 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19047 /* 52499 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19048 /* 52503 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19049 /* 52507 */ // (intrinsic_wo_chain:{ *:[i32] } 4107:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (QSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19050 /* 52507 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSAX),
19051 /* 52510 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19052 /* 52512 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19053 /* 52514 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19054 /* 52516 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19055 /* 52519 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19056 /* 52525 */ GIR_RootConstrainSelectedInstOperands,
19057 /* 52526 */ // GIR_Coverage, 117,
19058 /* 52526 */ GIR_EraseRootFromParent_Done,
19059 /* 52527 */ // Label 1161: @52527
19060 /* 52527 */ GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(52581), // Rule ID 118 //
19061 /* 52532 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19062 /* 52535 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx),
19063 /* 52540 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19064 /* 52543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19065 /* 52546 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19066 /* 52549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19067 /* 52553 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19068 /* 52557 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19069 /* 52561 */ // (intrinsic_wo_chain:{ *:[i32] } 4174:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19070 /* 52561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQASX),
19071 /* 52564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19072 /* 52566 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19073 /* 52568 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19074 /* 52570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19075 /* 52573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19076 /* 52579 */ GIR_RootConstrainSelectedInstOperands,
19077 /* 52580 */ // GIR_Coverage, 118,
19078 /* 52580 */ GIR_EraseRootFromParent_Done,
19079 /* 52581 */ // Label 1162: @52581
19080 /* 52581 */ GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(52635), // Rule ID 119 //
19081 /* 52586 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19082 /* 52589 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax),
19083 /* 52594 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19084 /* 52597 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19085 /* 52600 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19086 /* 52603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19087 /* 52607 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19088 /* 52611 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19089 /* 52615 */ // (intrinsic_wo_chain:{ *:[i32] } 4175:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UQSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19090 /* 52615 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UQSAX),
19091 /* 52618 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19092 /* 52620 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19093 /* 52622 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19094 /* 52624 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19095 /* 52627 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19096 /* 52633 */ GIR_RootConstrainSelectedInstOperands,
19097 /* 52634 */ // GIR_Coverage, 119,
19098 /* 52634 */ GIR_EraseRootFromParent_Done,
19099 /* 52635 */ // Label 1163: @52635
19100 /* 52635 */ GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(52689), // Rule ID 132 //
19101 /* 52640 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19102 /* 52643 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx),
19103 /* 52648 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19104 /* 52651 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19105 /* 52654 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19106 /* 52657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19107 /* 52661 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19108 /* 52665 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19109 /* 52669 */ // (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19110 /* 52669 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHASX),
19111 /* 52672 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19112 /* 52674 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19113 /* 52676 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19114 /* 52678 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19115 /* 52681 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19116 /* 52687 */ GIR_RootConstrainSelectedInstOperands,
19117 /* 52688 */ // GIR_Coverage, 132,
19118 /* 52688 */ GIR_EraseRootFromParent_Done,
19119 /* 52689 */ // Label 1164: @52689
19120 /* 52689 */ GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(52743), // Rule ID 133 //
19121 /* 52694 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19122 /* 52697 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16),
19123 /* 52702 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19124 /* 52705 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19125 /* 52708 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19126 /* 52711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19127 /* 52715 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19128 /* 52719 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19129 /* 52723 */ // (intrinsic_wo_chain:{ *:[i32] } 4116:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19130 /* 52723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD16),
19131 /* 52726 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19132 /* 52728 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19133 /* 52730 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19134 /* 52732 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19135 /* 52735 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19136 /* 52741 */ GIR_RootConstrainSelectedInstOperands,
19137 /* 52742 */ // GIR_Coverage, 133,
19138 /* 52742 */ GIR_EraseRootFromParent_Done,
19139 /* 52743 */ // Label 1165: @52743
19140 /* 52743 */ GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(52797), // Rule ID 134 //
19141 /* 52748 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19142 /* 52751 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8),
19143 /* 52756 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19144 /* 52759 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19145 /* 52762 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19146 /* 52765 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19147 /* 52769 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19148 /* 52773 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19149 /* 52777 */ // (intrinsic_wo_chain:{ *:[i32] } 4117:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19150 /* 52777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHADD8),
19151 /* 52780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19152 /* 52782 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19153 /* 52784 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19154 /* 52786 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19155 /* 52789 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19156 /* 52795 */ GIR_RootConstrainSelectedInstOperands,
19157 /* 52796 */ // GIR_Coverage, 134,
19158 /* 52796 */ GIR_EraseRootFromParent_Done,
19159 /* 52797 */ // Label 1166: @52797
19160 /* 52797 */ GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(52851), // Rule ID 135 //
19161 /* 52802 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19162 /* 52805 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax),
19163 /* 52810 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19164 /* 52813 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19165 /* 52816 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19166 /* 52819 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19167 /* 52823 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19168 /* 52827 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19169 /* 52831 */ // (intrinsic_wo_chain:{ *:[i32] } 4119:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19170 /* 52831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSAX),
19171 /* 52834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19172 /* 52836 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19173 /* 52838 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19174 /* 52840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19175 /* 52843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19176 /* 52849 */ GIR_RootConstrainSelectedInstOperands,
19177 /* 52850 */ // GIR_Coverage, 135,
19178 /* 52850 */ GIR_EraseRootFromParent_Done,
19179 /* 52851 */ // Label 1167: @52851
19180 /* 52851 */ GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(52905), // Rule ID 136 //
19181 /* 52856 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19182 /* 52859 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16),
19183 /* 52864 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19184 /* 52867 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19185 /* 52870 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19186 /* 52873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19187 /* 52877 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19188 /* 52881 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19189 /* 52885 */ // (intrinsic_wo_chain:{ *:[i32] } 4120:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19190 /* 52885 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB16),
19191 /* 52888 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19192 /* 52890 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19193 /* 52892 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19194 /* 52894 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19195 /* 52897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19196 /* 52903 */ GIR_RootConstrainSelectedInstOperands,
19197 /* 52904 */ // GIR_Coverage, 136,
19198 /* 52904 */ GIR_EraseRootFromParent_Done,
19199 /* 52905 */ // Label 1168: @52905
19200 /* 52905 */ GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(52959), // Rule ID 137 //
19201 /* 52910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19202 /* 52913 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8),
19203 /* 52918 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19204 /* 52921 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19205 /* 52924 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19206 /* 52927 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19207 /* 52931 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19208 /* 52935 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19209 /* 52939 */ // (intrinsic_wo_chain:{ *:[i32] } 4121:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19210 /* 52939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHSUB8),
19211 /* 52942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19212 /* 52944 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19213 /* 52946 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19214 /* 52948 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19215 /* 52951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19216 /* 52957 */ GIR_RootConstrainSelectedInstOperands,
19217 /* 52958 */ // GIR_Coverage, 137,
19218 /* 52958 */ GIR_EraseRootFromParent_Done,
19219 /* 52959 */ // Label 1169: @52959
19220 /* 52959 */ GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(53013), // Rule ID 138 //
19221 /* 52964 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19222 /* 52967 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx),
19223 /* 52972 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19224 /* 52975 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19225 /* 52978 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19226 /* 52981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19227 /* 52985 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19228 /* 52989 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19229 /* 52993 */ // (intrinsic_wo_chain:{ *:[i32] } 4167:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19230 /* 52993 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHASX),
19231 /* 52996 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19232 /* 52998 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19233 /* 53000 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19234 /* 53002 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19235 /* 53005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19236 /* 53011 */ GIR_RootConstrainSelectedInstOperands,
19237 /* 53012 */ // GIR_Coverage, 138,
19238 /* 53012 */ GIR_EraseRootFromParent_Done,
19239 /* 53013 */ // Label 1170: @53013
19240 /* 53013 */ GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(53067), // Rule ID 139 //
19241 /* 53018 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19242 /* 53021 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16),
19243 /* 53026 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19244 /* 53029 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19245 /* 53032 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19246 /* 53035 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19247 /* 53039 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19248 /* 53043 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19249 /* 53047 */ // (intrinsic_wo_chain:{ *:[i32] } 4165:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19250 /* 53047 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD16),
19251 /* 53050 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19252 /* 53052 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19253 /* 53054 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19254 /* 53056 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19255 /* 53059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19256 /* 53065 */ GIR_RootConstrainSelectedInstOperands,
19257 /* 53066 */ // GIR_Coverage, 139,
19258 /* 53066 */ GIR_EraseRootFromParent_Done,
19259 /* 53067 */ // Label 1171: @53067
19260 /* 53067 */ GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(53121), // Rule ID 140 //
19261 /* 53072 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19262 /* 53075 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8),
19263 /* 53080 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19264 /* 53083 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19265 /* 53086 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19266 /* 53089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19267 /* 53093 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19268 /* 53097 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19269 /* 53101 */ // (intrinsic_wo_chain:{ *:[i32] } 4166:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19270 /* 53101 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHADD8),
19271 /* 53104 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19272 /* 53106 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19273 /* 53108 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19274 /* 53110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19275 /* 53113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19276 /* 53119 */ GIR_RootConstrainSelectedInstOperands,
19277 /* 53120 */ // GIR_Coverage, 140,
19278 /* 53120 */ GIR_EraseRootFromParent_Done,
19279 /* 53121 */ // Label 1172: @53121
19280 /* 53121 */ GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(53175), // Rule ID 141 //
19281 /* 53126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19282 /* 53129 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax),
19283 /* 53134 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19284 /* 53137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19285 /* 53140 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19286 /* 53143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19287 /* 53147 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19288 /* 53151 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19289 /* 53155 */ // (intrinsic_wo_chain:{ *:[i32] } 4168:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19290 /* 53155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSAX),
19291 /* 53158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19292 /* 53160 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19293 /* 53162 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19294 /* 53164 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19295 /* 53167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19296 /* 53173 */ GIR_RootConstrainSelectedInstOperands,
19297 /* 53174 */ // GIR_Coverage, 141,
19298 /* 53174 */ GIR_EraseRootFromParent_Done,
19299 /* 53175 */ // Label 1173: @53175
19300 /* 53175 */ GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(53229), // Rule ID 142 //
19301 /* 53180 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19302 /* 53183 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16),
19303 /* 53188 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19304 /* 53191 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19305 /* 53194 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19306 /* 53197 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19307 /* 53201 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19308 /* 53205 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19309 /* 53209 */ // (intrinsic_wo_chain:{ *:[i32] } 4169:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19310 /* 53209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB16),
19311 /* 53212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19312 /* 53214 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19313 /* 53216 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19314 /* 53218 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19315 /* 53221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19316 /* 53227 */ GIR_RootConstrainSelectedInstOperands,
19317 /* 53228 */ // GIR_Coverage, 142,
19318 /* 53228 */ GIR_EraseRootFromParent_Done,
19319 /* 53229 */ // Label 1174: @53229
19320 /* 53229 */ GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(53283), // Rule ID 143 //
19321 /* 53234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
19322 /* 53237 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8),
19323 /* 53242 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19324 /* 53245 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19325 /* 53248 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19326 /* 53251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19327 /* 53255 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19328 /* 53259 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19329 /* 53263 */ // (intrinsic_wo_chain:{ *:[i32] } 4170:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UHSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19330 /* 53263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UHSUB8),
19331 /* 53266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19332 /* 53268 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19333 /* 53270 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19334 /* 53272 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19335 /* 53275 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19336 /* 53281 */ GIR_RootConstrainSelectedInstOperands,
19337 /* 53282 */ // GIR_Coverage, 143,
19338 /* 53282 */ GIR_EraseRootFromParent_Done,
19339 /* 53283 */ // Label 1175: @53283
19340 /* 53283 */ GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(53337), // Rule ID 144 //
19341 /* 53288 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
19342 /* 53291 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8),
19343 /* 53296 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19344 /* 53299 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19345 /* 53302 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19346 /* 53305 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
19347 /* 53309 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
19348 /* 53313 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
19349 /* 53317 */ // (intrinsic_wo_chain:{ *:[i32] } 4178:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (USAD8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
19350 /* 53317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAD8),
19351 /* 53320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19352 /* 53322 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19353 /* 53324 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19354 /* 53326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19355 /* 53329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19356 /* 53335 */ GIR_RootConstrainSelectedInstOperands,
19357 /* 53336 */ // GIR_Coverage, 144,
19358 /* 53336 */ GIR_EraseRootFromParent_Done,
19359 /* 53337 */ // Label 1176: @53337
19360 /* 53337 */ GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(53382), // Rule ID 203 //
19361 /* 53342 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
19362 /* 53345 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b),
19363 /* 53350 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19364 /* 53353 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19365 /* 53356 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19366 /* 53359 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19367 /* 53363 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19368 /* 53367 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19369 /* 53371 */ // (intrinsic_wo_chain:{ *:[i32] } 3724:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32B:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19370 /* 53371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32B),
19371 /* 53374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19372 /* 53376 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19373 /* 53378 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19374 /* 53380 */ GIR_RootConstrainSelectedInstOperands,
19375 /* 53381 */ // GIR_Coverage, 203,
19376 /* 53381 */ GIR_EraseRootFromParent_Done,
19377 /* 53382 */ // Label 1177: @53382
19378 /* 53382 */ GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(53427), // Rule ID 204 //
19379 /* 53387 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
19380 /* 53390 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb),
19381 /* 53395 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19382 /* 53398 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19383 /* 53401 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19384 /* 53404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19385 /* 53408 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19386 /* 53412 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19387 /* 53416 */ // (intrinsic_wo_chain:{ *:[i32] } 3725:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CB:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19388 /* 53416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CB),
19389 /* 53419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19390 /* 53421 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19391 /* 53423 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19392 /* 53425 */ GIR_RootConstrainSelectedInstOperands,
19393 /* 53426 */ // GIR_Coverage, 204,
19394 /* 53426 */ GIR_EraseRootFromParent_Done,
19395 /* 53427 */ // Label 1178: @53427
19396 /* 53427 */ GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(53472), // Rule ID 205 //
19397 /* 53432 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
19398 /* 53435 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h),
19399 /* 53440 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19400 /* 53443 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19401 /* 53446 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19402 /* 53449 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19403 /* 53453 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19404 /* 53457 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19405 /* 53461 */ // (intrinsic_wo_chain:{ *:[i32] } 3728:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32H:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19406 /* 53461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32H),
19407 /* 53464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19408 /* 53466 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19409 /* 53468 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19410 /* 53470 */ GIR_RootConstrainSelectedInstOperands,
19411 /* 53471 */ // GIR_Coverage, 205,
19412 /* 53471 */ GIR_EraseRootFromParent_Done,
19413 /* 53472 */ // Label 1179: @53472
19414 /* 53472 */ GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(53517), // Rule ID 206 //
19415 /* 53477 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
19416 /* 53480 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch),
19417 /* 53485 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19418 /* 53488 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19419 /* 53491 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19420 /* 53494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19421 /* 53498 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19422 /* 53502 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19423 /* 53506 */ // (intrinsic_wo_chain:{ *:[i32] } 3726:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CH:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19424 /* 53506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CH),
19425 /* 53509 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19426 /* 53511 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19427 /* 53513 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19428 /* 53515 */ GIR_RootConstrainSelectedInstOperands,
19429 /* 53516 */ // GIR_Coverage, 206,
19430 /* 53516 */ GIR_EraseRootFromParent_Done,
19431 /* 53517 */ // Label 1180: @53517
19432 /* 53517 */ GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(53562), // Rule ID 207 //
19433 /* 53522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
19434 /* 53525 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w),
19435 /* 53530 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19436 /* 53533 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19437 /* 53536 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19438 /* 53539 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19439 /* 53543 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19440 /* 53547 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19441 /* 53551 */ // (intrinsic_wo_chain:{ *:[i32] } 3729:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32W:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19442 /* 53551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32W),
19443 /* 53554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19444 /* 53556 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19445 /* 53558 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19446 /* 53560 */ GIR_RootConstrainSelectedInstOperands,
19447 /* 53561 */ // GIR_Coverage, 207,
19448 /* 53561 */ GIR_EraseRootFromParent_Done,
19449 /* 53562 */ // Label 1181: @53562
19450 /* 53562 */ GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(53607), // Rule ID 208 //
19451 /* 53567 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsARM),
19452 /* 53570 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw),
19453 /* 53575 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19454 /* 53578 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19455 /* 53581 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19456 /* 53584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19457 /* 53588 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19458 /* 53592 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
19459 /* 53596 */ // (intrinsic_wo_chain:{ *:[i32] } 3727:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (CRC32CW:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
19460 /* 53596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CRC32CW),
19461 /* 53599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19462 /* 53601 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19463 /* 53603 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19464 /* 53605 */ GIR_RootConstrainSelectedInstOperands,
19465 /* 53606 */ // GIR_Coverage, 208,
19466 /* 53606 */ GIR_EraseRootFromParent_Done,
19467 /* 53607 */ // Label 1182: @53607
19468 /* 53607 */ GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(53661), // Rule ID 431 //
19469 /* 53612 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19470 /* 53615 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd16),
19471 /* 53620 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19472 /* 53623 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19473 /* 53626 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19474 /* 53629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19475 /* 53633 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19476 /* 53637 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19477 /* 53641 */ // (intrinsic_wo_chain:{ *:[i32] } 4104:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19478 /* 53641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD16),
19479 /* 53644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19480 /* 53646 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19481 /* 53648 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19482 /* 53650 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19483 /* 53653 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19484 /* 53659 */ GIR_RootConstrainSelectedInstOperands,
19485 /* 53660 */ // GIR_Coverage, 431,
19486 /* 53660 */ GIR_EraseRootFromParent_Done,
19487 /* 53661 */ // Label 1183: @53661
19488 /* 53661 */ GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(53715), // Rule ID 432 //
19489 /* 53666 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19490 /* 53669 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd8),
19491 /* 53674 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19492 /* 53677 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19493 /* 53680 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19494 /* 53683 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19495 /* 53687 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19496 /* 53691 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19497 /* 53695 */ // (intrinsic_wo_chain:{ *:[i32] } 4105:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19498 /* 53695 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD8),
19499 /* 53698 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19500 /* 53700 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19501 /* 53702 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19502 /* 53704 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19503 /* 53707 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19504 /* 53713 */ GIR_RootConstrainSelectedInstOperands,
19505 /* 53714 */ // GIR_Coverage, 432,
19506 /* 53714 */ GIR_EraseRootFromParent_Done,
19507 /* 53715 */ // Label 1184: @53715
19508 /* 53715 */ GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(53769), // Rule ID 433 //
19509 /* 53720 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19510 /* 53723 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qasx),
19511 /* 53728 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19512 /* 53731 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19513 /* 53734 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19514 /* 53737 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19515 /* 53741 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19516 /* 53745 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19517 /* 53749 */ // (intrinsic_wo_chain:{ *:[i32] } 4106:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19518 /* 53749 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QASX),
19519 /* 53752 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19520 /* 53754 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19521 /* 53756 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19522 /* 53758 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19523 /* 53761 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19524 /* 53767 */ GIR_RootConstrainSelectedInstOperands,
19525 /* 53768 */ // GIR_Coverage, 433,
19526 /* 53768 */ GIR_EraseRootFromParent_Done,
19527 /* 53769 */ // Label 1185: @53769
19528 /* 53769 */ GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(53823), // Rule ID 434 //
19529 /* 53774 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19530 /* 53777 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub8),
19531 /* 53782 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19532 /* 53785 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19533 /* 53788 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19534 /* 53791 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19535 /* 53795 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19536 /* 53799 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19537 /* 53803 */ // (intrinsic_wo_chain:{ *:[i32] } 4177:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19538 /* 53803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB8),
19539 /* 53806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19540 /* 53808 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19541 /* 53810 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19542 /* 53812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19543 /* 53815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19544 /* 53821 */ GIR_RootConstrainSelectedInstOperands,
19545 /* 53822 */ // GIR_Coverage, 434,
19546 /* 53822 */ GIR_EraseRootFromParent_Done,
19547 /* 53823 */ // Label 1186: @53823
19548 /* 53823 */ GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(53877), // Rule ID 435 //
19549 /* 53828 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19550 /* 53831 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsax),
19551 /* 53836 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19552 /* 53839 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19553 /* 53842 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19554 /* 53845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19555 /* 53849 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19556 /* 53853 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19557 /* 53857 */ // (intrinsic_wo_chain:{ *:[i32] } 4107:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19558 /* 53857 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSAX),
19559 /* 53860 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19560 /* 53862 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19561 /* 53864 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19562 /* 53866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19563 /* 53869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19564 /* 53875 */ GIR_RootConstrainSelectedInstOperands,
19565 /* 53876 */ // GIR_Coverage, 435,
19566 /* 53876 */ GIR_EraseRootFromParent_Done,
19567 /* 53877 */ // Label 1187: @53877
19568 /* 53877 */ GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(53931), // Rule ID 436 //
19569 /* 53882 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19570 /* 53885 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub16),
19571 /* 53890 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19572 /* 53893 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19573 /* 53896 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19574 /* 53899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19575 /* 53903 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19576 /* 53907 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19577 /* 53911 */ // (intrinsic_wo_chain:{ *:[i32] } 4109:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19578 /* 53911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB16),
19579 /* 53914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19580 /* 53916 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19581 /* 53918 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19582 /* 53920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19583 /* 53923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19584 /* 53929 */ GIR_RootConstrainSelectedInstOperands,
19585 /* 53930 */ // GIR_Coverage, 436,
19586 /* 53930 */ GIR_EraseRootFromParent_Done,
19587 /* 53931 */ // Label 1188: @53931
19588 /* 53931 */ GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(53985), // Rule ID 437 //
19589 /* 53936 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19590 /* 53939 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub8),
19591 /* 53944 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19592 /* 53947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19593 /* 53950 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19594 /* 53953 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19595 /* 53957 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19596 /* 53961 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19597 /* 53965 */ // (intrinsic_wo_chain:{ *:[i32] } 4110:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2QSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19598 /* 53965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB8),
19599 /* 53968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19600 /* 53970 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19601 /* 53972 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19602 /* 53974 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19603 /* 53977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19604 /* 53983 */ GIR_RootConstrainSelectedInstOperands,
19605 /* 53984 */ // GIR_Coverage, 437,
19606 /* 53984 */ GIR_EraseRootFromParent_Done,
19607 /* 53985 */ // Label 1189: @53985
19608 /* 53985 */ GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(54039), // Rule ID 438 //
19609 /* 53990 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19610 /* 53993 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd16),
19611 /* 53998 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19612 /* 54001 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19613 /* 54004 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19614 /* 54007 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19615 /* 54011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19616 /* 54015 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19617 /* 54019 */ // (intrinsic_wo_chain:{ *:[i32] } 4172:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19618 /* 54019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD16),
19619 /* 54022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19620 /* 54024 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19621 /* 54026 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19622 /* 54028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19623 /* 54031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19624 /* 54037 */ GIR_RootConstrainSelectedInstOperands,
19625 /* 54038 */ // GIR_Coverage, 438,
19626 /* 54038 */ GIR_EraseRootFromParent_Done,
19627 /* 54039 */ // Label 1190: @54039
19628 /* 54039 */ GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(54093), // Rule ID 439 //
19629 /* 54044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19630 /* 54047 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqadd8),
19631 /* 54052 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19632 /* 54055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19633 /* 54058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19634 /* 54061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19635 /* 54065 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19636 /* 54069 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19637 /* 54073 */ // (intrinsic_wo_chain:{ *:[i32] } 4173:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19638 /* 54073 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQADD8),
19639 /* 54076 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19640 /* 54078 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19641 /* 54080 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19642 /* 54082 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19643 /* 54085 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19644 /* 54091 */ GIR_RootConstrainSelectedInstOperands,
19645 /* 54092 */ // GIR_Coverage, 439,
19646 /* 54092 */ GIR_EraseRootFromParent_Done,
19647 /* 54093 */ // Label 1191: @54093
19648 /* 54093 */ GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(54147), // Rule ID 440 //
19649 /* 54098 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19650 /* 54101 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqasx),
19651 /* 54106 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19652 /* 54109 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19653 /* 54112 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19654 /* 54115 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19655 /* 54119 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19656 /* 54123 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19657 /* 54127 */ // (intrinsic_wo_chain:{ *:[i32] } 4174:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19658 /* 54127 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQASX),
19659 /* 54130 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19660 /* 54132 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19661 /* 54134 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19662 /* 54136 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19663 /* 54139 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19664 /* 54145 */ GIR_RootConstrainSelectedInstOperands,
19665 /* 54146 */ // GIR_Coverage, 440,
19666 /* 54146 */ GIR_EraseRootFromParent_Done,
19667 /* 54147 */ // Label 1192: @54147
19668 /* 54147 */ GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(54201), // Rule ID 441 //
19669 /* 54152 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19670 /* 54155 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsax),
19671 /* 54160 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19672 /* 54163 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19673 /* 54166 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19674 /* 54169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19675 /* 54173 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19676 /* 54177 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19677 /* 54181 */ // (intrinsic_wo_chain:{ *:[i32] } 4175:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19678 /* 54181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSAX),
19679 /* 54184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19680 /* 54186 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19681 /* 54188 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19682 /* 54190 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19683 /* 54193 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19684 /* 54199 */ GIR_RootConstrainSelectedInstOperands,
19685 /* 54200 */ // GIR_Coverage, 441,
19686 /* 54200 */ GIR_EraseRootFromParent_Done,
19687 /* 54201 */ // Label 1193: @54201
19688 /* 54201 */ GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(54255), // Rule ID 442 //
19689 /* 54206 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19690 /* 54209 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uqsub16),
19691 /* 54214 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19692 /* 54217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19693 /* 54220 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19694 /* 54223 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19695 /* 54227 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19696 /* 54231 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19697 /* 54235 */ // (intrinsic_wo_chain:{ *:[i32] } 4176:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UQSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19698 /* 54235 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UQSUB16),
19699 /* 54238 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19700 /* 54240 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19701 /* 54242 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19702 /* 54244 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19703 /* 54247 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19704 /* 54253 */ GIR_RootConstrainSelectedInstOperands,
19705 /* 54254 */ // GIR_Coverage, 442,
19706 /* 54254 */ GIR_EraseRootFromParent_Done,
19707 /* 54255 */ // Label 1194: @54255
19708 /* 54255 */ GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(54309), // Rule ID 455 //
19709 /* 54260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19710 /* 54263 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shasx),
19711 /* 54268 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19712 /* 54271 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19713 /* 54274 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19714 /* 54277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19715 /* 54281 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19716 /* 54285 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19717 /* 54289 */ // (intrinsic_wo_chain:{ *:[i32] } 4118:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19718 /* 54289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHASX),
19719 /* 54292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19720 /* 54294 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19721 /* 54296 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19722 /* 54298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19723 /* 54301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19724 /* 54307 */ GIR_RootConstrainSelectedInstOperands,
19725 /* 54308 */ // GIR_Coverage, 455,
19726 /* 54308 */ GIR_EraseRootFromParent_Done,
19727 /* 54309 */ // Label 1195: @54309
19728 /* 54309 */ GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(54363), // Rule ID 456 //
19729 /* 54314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19730 /* 54317 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd16),
19731 /* 54322 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19732 /* 54325 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19733 /* 54328 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19734 /* 54331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19735 /* 54335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19736 /* 54339 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19737 /* 54343 */ // (intrinsic_wo_chain:{ *:[i32] } 4116:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19738 /* 54343 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD16),
19739 /* 54346 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19740 /* 54348 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19741 /* 54350 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19742 /* 54352 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19743 /* 54355 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19744 /* 54361 */ GIR_RootConstrainSelectedInstOperands,
19745 /* 54362 */ // GIR_Coverage, 456,
19746 /* 54362 */ GIR_EraseRootFromParent_Done,
19747 /* 54363 */ // Label 1196: @54363
19748 /* 54363 */ GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(54417), // Rule ID 457 //
19749 /* 54368 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19750 /* 54371 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shadd8),
19751 /* 54376 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19752 /* 54379 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19753 /* 54382 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19754 /* 54385 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19755 /* 54389 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19756 /* 54393 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19757 /* 54397 */ // (intrinsic_wo_chain:{ *:[i32] } 4117:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19758 /* 54397 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHADD8),
19759 /* 54400 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19760 /* 54402 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19761 /* 54404 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19762 /* 54406 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19763 /* 54409 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19764 /* 54415 */ GIR_RootConstrainSelectedInstOperands,
19765 /* 54416 */ // GIR_Coverage, 457,
19766 /* 54416 */ GIR_EraseRootFromParent_Done,
19767 /* 54417 */ // Label 1197: @54417
19768 /* 54417 */ GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(54471), // Rule ID 458 //
19769 /* 54422 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19770 /* 54425 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsax),
19771 /* 54430 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19772 /* 54433 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19773 /* 54436 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19774 /* 54439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19775 /* 54443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19776 /* 54447 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19777 /* 54451 */ // (intrinsic_wo_chain:{ *:[i32] } 4119:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19778 /* 54451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSAX),
19779 /* 54454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19780 /* 54456 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19781 /* 54458 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19782 /* 54460 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19783 /* 54463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19784 /* 54469 */ GIR_RootConstrainSelectedInstOperands,
19785 /* 54470 */ // GIR_Coverage, 458,
19786 /* 54470 */ GIR_EraseRootFromParent_Done,
19787 /* 54471 */ // Label 1198: @54471
19788 /* 54471 */ GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(54525), // Rule ID 459 //
19789 /* 54476 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19790 /* 54479 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub16),
19791 /* 54484 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19792 /* 54487 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19793 /* 54490 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19794 /* 54493 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19795 /* 54497 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19796 /* 54501 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19797 /* 54505 */ // (intrinsic_wo_chain:{ *:[i32] } 4120:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19798 /* 54505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB16),
19799 /* 54508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19800 /* 54510 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19801 /* 54512 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19802 /* 54514 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19803 /* 54517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19804 /* 54523 */ GIR_RootConstrainSelectedInstOperands,
19805 /* 54524 */ // GIR_Coverage, 459,
19806 /* 54524 */ GIR_EraseRootFromParent_Done,
19807 /* 54525 */ // Label 1199: @54525
19808 /* 54525 */ GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(54579), // Rule ID 460 //
19809 /* 54530 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19810 /* 54533 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_shsub8),
19811 /* 54538 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19812 /* 54541 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19813 /* 54544 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19814 /* 54547 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19815 /* 54551 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19816 /* 54555 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19817 /* 54559 */ // (intrinsic_wo_chain:{ *:[i32] } 4121:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19818 /* 54559 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SHSUB8),
19819 /* 54562 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19820 /* 54564 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19821 /* 54566 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19822 /* 54568 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19823 /* 54571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19824 /* 54577 */ GIR_RootConstrainSelectedInstOperands,
19825 /* 54578 */ // GIR_Coverage, 460,
19826 /* 54578 */ GIR_EraseRootFromParent_Done,
19827 /* 54579 */ // Label 1200: @54579
19828 /* 54579 */ GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(54633), // Rule ID 461 //
19829 /* 54584 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19830 /* 54587 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhasx),
19831 /* 54592 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19832 /* 54595 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19833 /* 54598 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19834 /* 54601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19835 /* 54605 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19836 /* 54609 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19837 /* 54613 */ // (intrinsic_wo_chain:{ *:[i32] } 4167:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19838 /* 54613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHASX),
19839 /* 54616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19840 /* 54618 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19841 /* 54620 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19842 /* 54622 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19843 /* 54625 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19844 /* 54631 */ GIR_RootConstrainSelectedInstOperands,
19845 /* 54632 */ // GIR_Coverage, 461,
19846 /* 54632 */ GIR_EraseRootFromParent_Done,
19847 /* 54633 */ // Label 1201: @54633
19848 /* 54633 */ GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(54687), // Rule ID 462 //
19849 /* 54638 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19850 /* 54641 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd16),
19851 /* 54646 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19852 /* 54649 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19853 /* 54652 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19854 /* 54655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19855 /* 54659 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19856 /* 54663 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19857 /* 54667 */ // (intrinsic_wo_chain:{ *:[i32] } 4165:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19858 /* 54667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD16),
19859 /* 54670 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19860 /* 54672 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19861 /* 54674 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19862 /* 54676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19863 /* 54679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19864 /* 54685 */ GIR_RootConstrainSelectedInstOperands,
19865 /* 54686 */ // GIR_Coverage, 462,
19866 /* 54686 */ GIR_EraseRootFromParent_Done,
19867 /* 54687 */ // Label 1202: @54687
19868 /* 54687 */ GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(54741), // Rule ID 463 //
19869 /* 54692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19870 /* 54695 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhadd8),
19871 /* 54700 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19872 /* 54703 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19873 /* 54706 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19874 /* 54709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19875 /* 54713 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19876 /* 54717 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19877 /* 54721 */ // (intrinsic_wo_chain:{ *:[i32] } 4166:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19878 /* 54721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHADD8),
19879 /* 54724 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19880 /* 54726 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19881 /* 54728 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19882 /* 54730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19883 /* 54733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19884 /* 54739 */ GIR_RootConstrainSelectedInstOperands,
19885 /* 54740 */ // GIR_Coverage, 463,
19886 /* 54740 */ GIR_EraseRootFromParent_Done,
19887 /* 54741 */ // Label 1203: @54741
19888 /* 54741 */ GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(54795), // Rule ID 464 //
19889 /* 54746 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19890 /* 54749 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsax),
19891 /* 54754 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19892 /* 54757 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19893 /* 54760 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19894 /* 54763 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19895 /* 54767 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19896 /* 54771 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19897 /* 54775 */ // (intrinsic_wo_chain:{ *:[i32] } 4168:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19898 /* 54775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSAX),
19899 /* 54778 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19900 /* 54780 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19901 /* 54782 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19902 /* 54784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19903 /* 54787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19904 /* 54793 */ GIR_RootConstrainSelectedInstOperands,
19905 /* 54794 */ // GIR_Coverage, 464,
19906 /* 54794 */ GIR_EraseRootFromParent_Done,
19907 /* 54795 */ // Label 1204: @54795
19908 /* 54795 */ GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(54849), // Rule ID 465 //
19909 /* 54800 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19910 /* 54803 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub16),
19911 /* 54808 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19912 /* 54811 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19913 /* 54814 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19914 /* 54817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19915 /* 54821 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19916 /* 54825 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19917 /* 54829 */ // (intrinsic_wo_chain:{ *:[i32] } 4169:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19918 /* 54829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB16),
19919 /* 54832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19920 /* 54834 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19921 /* 54836 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19922 /* 54838 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19923 /* 54841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19924 /* 54847 */ GIR_RootConstrainSelectedInstOperands,
19925 /* 54848 */ // GIR_Coverage, 465,
19926 /* 54848 */ GIR_EraseRootFromParent_Done,
19927 /* 54849 */ // Label 1205: @54849
19928 /* 54849 */ GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(54903), // Rule ID 466 //
19929 /* 54854 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19930 /* 54857 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uhsub8),
19931 /* 54862 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19932 /* 54865 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19933 /* 54868 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19934 /* 54871 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19935 /* 54875 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19936 /* 54879 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19937 /* 54883 */ // (intrinsic_wo_chain:{ *:[i32] } 4170:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UHSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19938 /* 54883 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UHSUB8),
19939 /* 54886 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19940 /* 54888 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19941 /* 54890 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19942 /* 54892 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19943 /* 54895 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19944 /* 54901 */ GIR_RootConstrainSelectedInstOperands,
19945 /* 54902 */ // GIR_Coverage, 466,
19946 /* 54902 */ GIR_EraseRootFromParent_Done,
19947 /* 54903 */ // Label 1206: @54903
19948 /* 54903 */ GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(54957), // Rule ID 467 //
19949 /* 54908 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19950 /* 54911 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usad8),
19951 /* 54916 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19952 /* 54919 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19953 /* 54922 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19954 /* 54925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19955 /* 54929 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19956 /* 54933 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19957 /* 54937 */ // (intrinsic_wo_chain:{ *:[i32] } 4178:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19958 /* 54937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAD8),
19959 /* 54940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19960 /* 54942 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19961 /* 54944 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19962 /* 54946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19963 /* 54949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19964 /* 54955 */ GIR_RootConstrainSelectedInstOperands,
19965 /* 54956 */ // GIR_Coverage, 467,
19966 /* 54956 */ GIR_EraseRootFromParent_Done,
19967 /* 54957 */ // Label 1207: @54957
19968 /* 54957 */ GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(55011), // Rule ID 523 //
19969 /* 54962 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19970 /* 54965 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad),
19971 /* 54970 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19972 /* 54973 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19973 /* 54976 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19974 /* 54979 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19975 /* 54983 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19976 /* 54987 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19977 /* 54991 */ // (intrinsic_wo_chain:{ *:[i32] } 4136:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19978 /* 54991 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUAD),
19979 /* 54994 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
19980 /* 54996 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
19981 /* 54998 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
19982 /* 55000 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
19983 /* 55003 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
19984 /* 55009 */ GIR_RootConstrainSelectedInstOperands,
19985 /* 55010 */ // GIR_Coverage, 523,
19986 /* 55010 */ GIR_EraseRootFromParent_Done,
19987 /* 55011 */ // Label 1208: @55011
19988 /* 55011 */ GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(55065), // Rule ID 524 //
19989 /* 55016 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
19990 /* 55019 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx),
19991 /* 55024 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
19992 /* 55027 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
19993 /* 55030 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
19994 /* 55033 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19995 /* 55037 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19996 /* 55041 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
19997 /* 55045 */ // (intrinsic_wo_chain:{ *:[i32] } 4137:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
19998 /* 55045 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUADX),
19999 /* 55048 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
20000 /* 55050 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
20001 /* 55052 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
20002 /* 55054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20003 /* 55057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20004 /* 55063 */ GIR_RootConstrainSelectedInstOperands,
20005 /* 55064 */ // GIR_Coverage, 524,
20006 /* 55064 */ GIR_EraseRootFromParent_Done,
20007 /* 55065 */ // Label 1209: @55065
20008 /* 55065 */ GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(55119), // Rule ID 525 //
20009 /* 55070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
20010 /* 55073 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd),
20011 /* 55078 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20012 /* 55081 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20013 /* 55084 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20014 /* 55087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20015 /* 55091 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20016 /* 55095 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20017 /* 55099 */ // (intrinsic_wo_chain:{ *:[i32] } 4144:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20018 /* 55099 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSD),
20019 /* 55102 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
20020 /* 55104 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
20021 /* 55106 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
20022 /* 55108 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20023 /* 55111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20024 /* 55117 */ GIR_RootConstrainSelectedInstOperands,
20025 /* 55118 */ // GIR_Coverage, 525,
20026 /* 55118 */ GIR_EraseRootFromParent_Done,
20027 /* 55119 */ // Label 1210: @55119
20028 /* 55119 */ GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(55173), // Rule ID 526 //
20029 /* 55124 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
20030 /* 55127 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx),
20031 /* 55132 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20032 /* 55135 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20033 /* 55138 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20034 /* 55141 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20035 /* 55145 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20036 /* 55149 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20037 /* 55153 */ // (intrinsic_wo_chain:{ *:[i32] } 4145:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMUSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20038 /* 55153 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMUSDX),
20039 /* 55156 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
20040 /* 55158 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
20041 /* 55160 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
20042 /* 55162 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20043 /* 55165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20044 /* 55171 */ GIR_RootConstrainSelectedInstOperands,
20045 /* 55172 */ // GIR_Coverage, 526,
20046 /* 55172 */ GIR_EraseRootFromParent_Done,
20047 /* 55173 */ // Label 1211: @55173
20048 /* 55173 */ GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(55218), // Rule ID 540 //
20049 /* 55178 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
20050 /* 55181 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32b),
20051 /* 55186 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20052 /* 55189 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20053 /* 55192 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20054 /* 55195 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20055 /* 55199 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20056 /* 55203 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20057 /* 55207 */ // (intrinsic_wo_chain:{ *:[i32] } 3724:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32B:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20058 /* 55207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32B),
20059 /* 55210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
20060 /* 55212 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
20061 /* 55214 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
20062 /* 55216 */ GIR_RootConstrainSelectedInstOperands,
20063 /* 55217 */ // GIR_Coverage, 540,
20064 /* 55217 */ GIR_EraseRootFromParent_Done,
20065 /* 55218 */ // Label 1212: @55218
20066 /* 55218 */ GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(55263), // Rule ID 541 //
20067 /* 55223 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
20068 /* 55226 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cb),
20069 /* 55231 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20070 /* 55234 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20071 /* 55237 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20072 /* 55240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20073 /* 55244 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20074 /* 55248 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20075 /* 55252 */ // (intrinsic_wo_chain:{ *:[i32] } 3725:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20076 /* 55252 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CB),
20077 /* 55255 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
20078 /* 55257 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
20079 /* 55259 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
20080 /* 55261 */ GIR_RootConstrainSelectedInstOperands,
20081 /* 55262 */ // GIR_Coverage, 541,
20082 /* 55262 */ GIR_EraseRootFromParent_Done,
20083 /* 55263 */ // Label 1213: @55263
20084 /* 55263 */ GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(55308), // Rule ID 542 //
20085 /* 55268 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
20086 /* 55271 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32h),
20087 /* 55276 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20088 /* 55279 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20089 /* 55282 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20090 /* 55285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20091 /* 55289 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20092 /* 55293 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20093 /* 55297 */ // (intrinsic_wo_chain:{ *:[i32] } 3728:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32H:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20094 /* 55297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32H),
20095 /* 55300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
20096 /* 55302 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
20097 /* 55304 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
20098 /* 55306 */ GIR_RootConstrainSelectedInstOperands,
20099 /* 55307 */ // GIR_Coverage, 542,
20100 /* 55307 */ GIR_EraseRootFromParent_Done,
20101 /* 55308 */ // Label 1214: @55308
20102 /* 55308 */ GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(55353), // Rule ID 543 //
20103 /* 55313 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
20104 /* 55316 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32ch),
20105 /* 55321 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20106 /* 55324 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20107 /* 55327 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20108 /* 55330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20109 /* 55334 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20110 /* 55338 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20111 /* 55342 */ // (intrinsic_wo_chain:{ *:[i32] } 3726:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CH:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20112 /* 55342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CH),
20113 /* 55345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
20114 /* 55347 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
20115 /* 55349 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
20116 /* 55351 */ GIR_RootConstrainSelectedInstOperands,
20117 /* 55352 */ // GIR_Coverage, 543,
20118 /* 55352 */ GIR_EraseRootFromParent_Done,
20119 /* 55353 */ // Label 1215: @55353
20120 /* 55353 */ GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(55398), // Rule ID 544 //
20121 /* 55358 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
20122 /* 55361 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32w),
20123 /* 55366 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20124 /* 55369 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20125 /* 55372 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20126 /* 55375 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20127 /* 55379 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20128 /* 55383 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20129 /* 55387 */ // (intrinsic_wo_chain:{ *:[i32] } 3729:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32W:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20130 /* 55387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32W),
20131 /* 55390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
20132 /* 55392 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
20133 /* 55394 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
20134 /* 55396 */ GIR_RootConstrainSelectedInstOperands,
20135 /* 55397 */ // GIR_Coverage, 544,
20136 /* 55397 */ GIR_EraseRootFromParent_Done,
20137 /* 55398 */ // Label 1216: @55398
20138 /* 55398 */ GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(55443), // Rule ID 545 //
20139 /* 55403 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCRC_IsThumb2),
20140 /* 55406 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_crc32cw),
20141 /* 55411 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
20142 /* 55414 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
20143 /* 55417 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
20144 /* 55420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20145 /* 55424 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20146 /* 55428 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
20147 /* 55432 */ // (intrinsic_wo_chain:{ *:[i32] } 3727:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2CRC32CW:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
20148 /* 55432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CRC32CW),
20149 /* 55435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
20150 /* 55437 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
20151 /* 55439 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
20152 /* 55441 */ GIR_RootConstrainSelectedInstOperands,
20153 /* 55442 */ // GIR_Coverage, 545,
20154 /* 55442 */ GIR_EraseRootFromParent_Done,
20155 /* 55443 */ // Label 1217: @55443
20156 /* 55443 */ GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(55497), // Rule ID 911 //
20157 /* 55448 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20158 /* 55451 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
20159 /* 55456 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20160 /* 55459 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20161 /* 55462 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20162 /* 55465 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20163 /* 55469 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20164 /* 55473 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20165 /* 55477 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4014:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20166 /* 55477 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i16),
20167 /* 55480 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20168 /* 55482 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20169 /* 55484 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20170 /* 55486 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20171 /* 55489 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20172 /* 55495 */ GIR_RootConstrainSelectedInstOperands,
20173 /* 55496 */ // GIR_Coverage, 911,
20174 /* 55496 */ GIR_EraseRootFromParent_Done,
20175 /* 55497 */ // Label 1218: @55497
20176 /* 55497 */ GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(55551), // Rule ID 912 //
20177 /* 55502 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20178 /* 55505 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
20179 /* 55510 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20180 /* 55513 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20181 /* 55516 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20182 /* 55519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20183 /* 55523 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20184 /* 55527 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20185 /* 55531 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4014:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20186 /* 55531 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv2i32),
20187 /* 55534 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20188 /* 55536 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20189 /* 55538 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20190 /* 55540 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20191 /* 55543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20192 /* 55549 */ GIR_RootConstrainSelectedInstOperands,
20193 /* 55550 */ // GIR_Coverage, 912,
20194 /* 55550 */ GIR_EraseRootFromParent_Done,
20195 /* 55551 */ // Label 1219: @55551
20196 /* 55551 */ GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(55605), // Rule ID 913 //
20197 /* 55556 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20198 /* 55559 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
20199 /* 55564 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20200 /* 55567 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20201 /* 55570 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20202 /* 55573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20203 /* 55577 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20204 /* 55581 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20205 /* 55585 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4014:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20206 /* 55585 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i16),
20207 /* 55588 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20208 /* 55590 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20209 /* 55592 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20210 /* 55594 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20211 /* 55597 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20212 /* 55603 */ GIR_RootConstrainSelectedInstOperands,
20213 /* 55604 */ // GIR_Coverage, 913,
20214 /* 55604 */ GIR_EraseRootFromParent_Done,
20215 /* 55605 */ // Label 1220: @55605
20216 /* 55605 */ GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(55659), // Rule ID 914 //
20217 /* 55610 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20218 /* 55613 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
20219 /* 55618 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20220 /* 55621 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20221 /* 55624 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20222 /* 55627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20223 /* 55631 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20224 /* 55635 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20225 /* 55639 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4014:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20226 /* 55639 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv4i32),
20227 /* 55642 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20228 /* 55644 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20229 /* 55646 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20230 /* 55648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20231 /* 55651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20232 /* 55657 */ GIR_RootConstrainSelectedInstOperands,
20233 /* 55658 */ // GIR_Coverage, 914,
20234 /* 55658 */ GIR_EraseRootFromParent_Done,
20235 /* 55659 */ // Label 1221: @55659
20236 /* 55659 */ GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(55713), // Rule ID 915 //
20237 /* 55664 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20238 /* 55667 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
20239 /* 55672 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
20240 /* 55675 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20241 /* 55678 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20242 /* 55681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20243 /* 55685 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20244 /* 55689 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20245 /* 55693 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4014:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20246 /* 55693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv8i8),
20247 /* 55696 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20248 /* 55698 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20249 /* 55700 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20250 /* 55702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20251 /* 55705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20252 /* 55711 */ GIR_RootConstrainSelectedInstOperands,
20253 /* 55712 */ // GIR_Coverage, 915,
20254 /* 55712 */ GIR_EraseRootFromParent_Done,
20255 /* 55713 */ // Label 1222: @55713
20256 /* 55713 */ GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(55767), // Rule ID 916 //
20257 /* 55718 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20258 /* 55721 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhadds),
20259 /* 55726 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20260 /* 55729 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20261 /* 55732 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20262 /* 55735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20263 /* 55739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20264 /* 55743 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20265 /* 55747 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4014:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20266 /* 55747 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDsv16i8),
20267 /* 55750 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20268 /* 55752 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20269 /* 55754 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20270 /* 55756 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20271 /* 55759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20272 /* 55765 */ GIR_RootConstrainSelectedInstOperands,
20273 /* 55766 */ // GIR_Coverage, 916,
20274 /* 55766 */ GIR_EraseRootFromParent_Done,
20275 /* 55767 */ // Label 1223: @55767
20276 /* 55767 */ GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(55821), // Rule ID 917 //
20277 /* 55772 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20278 /* 55775 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
20279 /* 55780 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20280 /* 55783 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20281 /* 55786 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20282 /* 55789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20283 /* 55793 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20284 /* 55797 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20285 /* 55801 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4015:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20286 /* 55801 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i16),
20287 /* 55804 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20288 /* 55806 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20289 /* 55808 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20290 /* 55810 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20291 /* 55813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20292 /* 55819 */ GIR_RootConstrainSelectedInstOperands,
20293 /* 55820 */ // GIR_Coverage, 917,
20294 /* 55820 */ GIR_EraseRootFromParent_Done,
20295 /* 55821 */ // Label 1224: @55821
20296 /* 55821 */ GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(55875), // Rule ID 918 //
20297 /* 55826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20298 /* 55829 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
20299 /* 55834 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20300 /* 55837 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20301 /* 55840 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20302 /* 55843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20303 /* 55847 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20304 /* 55851 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20305 /* 55855 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4015:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20306 /* 55855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv2i32),
20307 /* 55858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20308 /* 55860 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20309 /* 55862 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20310 /* 55864 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20311 /* 55867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20312 /* 55873 */ GIR_RootConstrainSelectedInstOperands,
20313 /* 55874 */ // GIR_Coverage, 918,
20314 /* 55874 */ GIR_EraseRootFromParent_Done,
20315 /* 55875 */ // Label 1225: @55875
20316 /* 55875 */ GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(55929), // Rule ID 919 //
20317 /* 55880 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20318 /* 55883 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
20319 /* 55888 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20320 /* 55891 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20321 /* 55894 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20322 /* 55897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20323 /* 55901 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20324 /* 55905 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20325 /* 55909 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4015:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20326 /* 55909 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i16),
20327 /* 55912 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20328 /* 55914 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20329 /* 55916 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20330 /* 55918 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20331 /* 55921 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20332 /* 55927 */ GIR_RootConstrainSelectedInstOperands,
20333 /* 55928 */ // GIR_Coverage, 919,
20334 /* 55928 */ GIR_EraseRootFromParent_Done,
20335 /* 55929 */ // Label 1226: @55929
20336 /* 55929 */ GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(55983), // Rule ID 920 //
20337 /* 55934 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20338 /* 55937 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
20339 /* 55942 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20340 /* 55945 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20341 /* 55948 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20342 /* 55951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20343 /* 55955 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20344 /* 55959 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20345 /* 55963 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4015:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20346 /* 55963 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv4i32),
20347 /* 55966 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20348 /* 55968 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20349 /* 55970 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20350 /* 55972 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20351 /* 55975 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20352 /* 55981 */ GIR_RootConstrainSelectedInstOperands,
20353 /* 55982 */ // GIR_Coverage, 920,
20354 /* 55982 */ GIR_EraseRootFromParent_Done,
20355 /* 55983 */ // Label 1227: @55983
20356 /* 55983 */ GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(56037), // Rule ID 921 //
20357 /* 55988 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20358 /* 55991 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
20359 /* 55996 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
20360 /* 55999 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20361 /* 56002 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20362 /* 56005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20363 /* 56009 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20364 /* 56013 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20365 /* 56017 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4015:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20366 /* 56017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv8i8),
20367 /* 56020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20368 /* 56022 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20369 /* 56024 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20370 /* 56026 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20371 /* 56029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20372 /* 56035 */ GIR_RootConstrainSelectedInstOperands,
20373 /* 56036 */ // GIR_Coverage, 921,
20374 /* 56036 */ GIR_EraseRootFromParent_Done,
20375 /* 56037 */ // Label 1228: @56037
20376 /* 56037 */ GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(56091), // Rule ID 922 //
20377 /* 56042 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20378 /* 56045 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhaddu),
20379 /* 56050 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20380 /* 56053 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20381 /* 56056 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20382 /* 56059 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20383 /* 56063 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20384 /* 56067 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20385 /* 56071 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4015:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20386 /* 56071 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHADDuv16i8),
20387 /* 56074 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20388 /* 56076 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20389 /* 56078 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20390 /* 56080 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20391 /* 56083 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20392 /* 56089 */ GIR_RootConstrainSelectedInstOperands,
20393 /* 56090 */ // GIR_Coverage, 922,
20394 /* 56090 */ GIR_EraseRootFromParent_Done,
20395 /* 56091 */ // Label 1229: @56091
20396 /* 56091 */ GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(56145), // Rule ID 923 //
20397 /* 56096 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20398 /* 56099 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
20399 /* 56104 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20400 /* 56107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20401 /* 56110 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20402 /* 56113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20403 /* 56117 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20404 /* 56121 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20405 /* 56125 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4074:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20406 /* 56125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i16),
20407 /* 56128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20408 /* 56130 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20409 /* 56132 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20410 /* 56134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20411 /* 56137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20412 /* 56143 */ GIR_RootConstrainSelectedInstOperands,
20413 /* 56144 */ // GIR_Coverage, 923,
20414 /* 56144 */ GIR_EraseRootFromParent_Done,
20415 /* 56145 */ // Label 1230: @56145
20416 /* 56145 */ GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(56199), // Rule ID 924 //
20417 /* 56150 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20418 /* 56153 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
20419 /* 56158 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20420 /* 56161 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20421 /* 56164 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20422 /* 56167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20423 /* 56171 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20424 /* 56175 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20425 /* 56179 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4074:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20426 /* 56179 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv2i32),
20427 /* 56182 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20428 /* 56184 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20429 /* 56186 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20430 /* 56188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20431 /* 56191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20432 /* 56197 */ GIR_RootConstrainSelectedInstOperands,
20433 /* 56198 */ // GIR_Coverage, 924,
20434 /* 56198 */ GIR_EraseRootFromParent_Done,
20435 /* 56199 */ // Label 1231: @56199
20436 /* 56199 */ GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(56253), // Rule ID 925 //
20437 /* 56204 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20438 /* 56207 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
20439 /* 56212 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20440 /* 56215 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20441 /* 56218 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20442 /* 56221 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20443 /* 56225 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20444 /* 56229 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20445 /* 56233 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4074:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20446 /* 56233 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i16),
20447 /* 56236 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20448 /* 56238 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20449 /* 56240 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20450 /* 56242 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20451 /* 56245 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20452 /* 56251 */ GIR_RootConstrainSelectedInstOperands,
20453 /* 56252 */ // GIR_Coverage, 925,
20454 /* 56252 */ GIR_EraseRootFromParent_Done,
20455 /* 56253 */ // Label 1232: @56253
20456 /* 56253 */ GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(56307), // Rule ID 926 //
20457 /* 56258 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20458 /* 56261 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
20459 /* 56266 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20460 /* 56269 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20461 /* 56272 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20462 /* 56275 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20463 /* 56279 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20464 /* 56283 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20465 /* 56287 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4074:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20466 /* 56287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv4i32),
20467 /* 56290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20468 /* 56292 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20469 /* 56294 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20470 /* 56296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20471 /* 56299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20472 /* 56305 */ GIR_RootConstrainSelectedInstOperands,
20473 /* 56306 */ // GIR_Coverage, 926,
20474 /* 56306 */ GIR_EraseRootFromParent_Done,
20475 /* 56307 */ // Label 1233: @56307
20476 /* 56307 */ GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(56361), // Rule ID 927 //
20477 /* 56312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20478 /* 56315 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
20479 /* 56320 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
20480 /* 56323 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20481 /* 56326 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20482 /* 56329 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20483 /* 56333 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20484 /* 56337 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20485 /* 56341 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4074:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20486 /* 56341 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv8i8),
20487 /* 56344 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20488 /* 56346 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20489 /* 56348 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20490 /* 56350 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20491 /* 56353 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20492 /* 56359 */ GIR_RootConstrainSelectedInstOperands,
20493 /* 56360 */ // GIR_Coverage, 927,
20494 /* 56360 */ GIR_EraseRootFromParent_Done,
20495 /* 56361 */ // Label 1234: @56361
20496 /* 56361 */ GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(56415), // Rule ID 928 //
20497 /* 56366 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20498 /* 56369 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhadds),
20499 /* 56374 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20500 /* 56377 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20501 /* 56380 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20502 /* 56383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20503 /* 56387 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20504 /* 56391 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20505 /* 56395 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4074:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20506 /* 56395 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDsv16i8),
20507 /* 56398 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20508 /* 56400 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20509 /* 56402 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20510 /* 56404 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20511 /* 56407 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20512 /* 56413 */ GIR_RootConstrainSelectedInstOperands,
20513 /* 56414 */ // GIR_Coverage, 928,
20514 /* 56414 */ GIR_EraseRootFromParent_Done,
20515 /* 56415 */ // Label 1235: @56415
20516 /* 56415 */ GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(56469), // Rule ID 929 //
20517 /* 56420 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20518 /* 56423 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
20519 /* 56428 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20520 /* 56431 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20521 /* 56434 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20522 /* 56437 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20523 /* 56441 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20524 /* 56445 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20525 /* 56449 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4075:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VRHADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20526 /* 56449 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i16),
20527 /* 56452 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20528 /* 56454 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20529 /* 56456 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20530 /* 56458 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20531 /* 56461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20532 /* 56467 */ GIR_RootConstrainSelectedInstOperands,
20533 /* 56468 */ // GIR_Coverage, 929,
20534 /* 56468 */ GIR_EraseRootFromParent_Done,
20535 /* 56469 */ // Label 1236: @56469
20536 /* 56469 */ GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(56523), // Rule ID 930 //
20537 /* 56474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20538 /* 56477 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
20539 /* 56482 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20540 /* 56485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20541 /* 56488 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20542 /* 56491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20543 /* 56495 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20544 /* 56499 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20545 /* 56503 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4075:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VRHADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20546 /* 56503 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv2i32),
20547 /* 56506 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20548 /* 56508 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20549 /* 56510 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20550 /* 56512 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20551 /* 56515 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20552 /* 56521 */ GIR_RootConstrainSelectedInstOperands,
20553 /* 56522 */ // GIR_Coverage, 930,
20554 /* 56522 */ GIR_EraseRootFromParent_Done,
20555 /* 56523 */ // Label 1237: @56523
20556 /* 56523 */ GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(56577), // Rule ID 931 //
20557 /* 56528 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20558 /* 56531 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
20559 /* 56536 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20560 /* 56539 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20561 /* 56542 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20562 /* 56545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20563 /* 56549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20564 /* 56553 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20565 /* 56557 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4075:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRHADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20566 /* 56557 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i16),
20567 /* 56560 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20568 /* 56562 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20569 /* 56564 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20570 /* 56566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20571 /* 56569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20572 /* 56575 */ GIR_RootConstrainSelectedInstOperands,
20573 /* 56576 */ // GIR_Coverage, 931,
20574 /* 56576 */ GIR_EraseRootFromParent_Done,
20575 /* 56577 */ // Label 1238: @56577
20576 /* 56577 */ GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(56631), // Rule ID 932 //
20577 /* 56582 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20578 /* 56585 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
20579 /* 56590 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20580 /* 56593 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20581 /* 56596 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20582 /* 56599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20583 /* 56603 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20584 /* 56607 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20585 /* 56611 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4075:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRHADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20586 /* 56611 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv4i32),
20587 /* 56614 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20588 /* 56616 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20589 /* 56618 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20590 /* 56620 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20591 /* 56623 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20592 /* 56629 */ GIR_RootConstrainSelectedInstOperands,
20593 /* 56630 */ // GIR_Coverage, 932,
20594 /* 56630 */ GIR_EraseRootFromParent_Done,
20595 /* 56631 */ // Label 1239: @56631
20596 /* 56631 */ GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(56685), // Rule ID 933 //
20597 /* 56636 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20598 /* 56639 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
20599 /* 56644 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
20600 /* 56647 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20601 /* 56650 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20602 /* 56653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20603 /* 56657 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20604 /* 56661 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20605 /* 56665 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4075:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VRHADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20606 /* 56665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv8i8),
20607 /* 56668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20608 /* 56670 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20609 /* 56672 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20610 /* 56674 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20611 /* 56677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20612 /* 56683 */ GIR_RootConstrainSelectedInstOperands,
20613 /* 56684 */ // GIR_Coverage, 933,
20614 /* 56684 */ GIR_EraseRootFromParent_Done,
20615 /* 56685 */ // Label 1240: @56685
20616 /* 56685 */ GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(56739), // Rule ID 934 //
20617 /* 56690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20618 /* 56693 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrhaddu),
20619 /* 56698 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20620 /* 56701 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20621 /* 56704 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20622 /* 56707 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20623 /* 56711 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20624 /* 56715 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20625 /* 56719 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4075:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VRHADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20626 /* 56719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRHADDuv16i8),
20627 /* 56722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20628 /* 56724 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20629 /* 56726 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20630 /* 56728 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20631 /* 56731 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20632 /* 56737 */ GIR_RootConstrainSelectedInstOperands,
20633 /* 56738 */ // GIR_Coverage, 934,
20634 /* 56738 */ GIR_EraseRootFromParent_Done,
20635 /* 56739 */ // Label 1241: @56739
20636 /* 56739 */ GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(56793), // Rule ID 951 //
20637 /* 56744 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20638 /* 56747 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn),
20639 /* 56752 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
20640 /* 56755 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20641 /* 56758 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20642 /* 56761 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20643 /* 56765 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20644 /* 56769 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20645 /* 56773 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4071:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRADDHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20646 /* 56773 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv8i8),
20647 /* 56776 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20648 /* 56778 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20649 /* 56780 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20650 /* 56782 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20651 /* 56785 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20652 /* 56791 */ GIR_RootConstrainSelectedInstOperands,
20653 /* 56792 */ // GIR_Coverage, 951,
20654 /* 56792 */ GIR_EraseRootFromParent_Done,
20655 /* 56793 */ // Label 1242: @56793
20656 /* 56793 */ GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(56847), // Rule ID 952 //
20657 /* 56798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20658 /* 56801 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn),
20659 /* 56806 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20660 /* 56809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20661 /* 56812 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20662 /* 56815 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20663 /* 56819 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20664 /* 56823 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20665 /* 56827 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4071:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRADDHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20666 /* 56827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv4i16),
20667 /* 56830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20668 /* 56832 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20669 /* 56834 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20670 /* 56836 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20671 /* 56839 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20672 /* 56845 */ GIR_RootConstrainSelectedInstOperands,
20673 /* 56846 */ // GIR_Coverage, 952,
20674 /* 56846 */ GIR_EraseRootFromParent_Done,
20675 /* 56847 */ // Label 1243: @56847
20676 /* 56847 */ GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(56901), // Rule ID 953 //
20677 /* 56852 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20678 /* 56855 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vraddhn),
20679 /* 56860 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20680 /* 56863 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
20681 /* 56866 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
20682 /* 56869 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20683 /* 56873 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20684 /* 56877 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20685 /* 56881 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4071:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRADDHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
20686 /* 56881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRADDHNv2i32),
20687 /* 56884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20688 /* 56886 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20689 /* 56888 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20690 /* 56890 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20691 /* 56893 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20692 /* 56899 */ GIR_RootConstrainSelectedInstOperands,
20693 /* 56900 */ // GIR_Coverage, 953,
20694 /* 56900 */ GIR_EraseRootFromParent_Done,
20695 /* 56901 */ // Label 1244: @56901
20696 /* 56901 */ GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(56955), // Rule ID 960 //
20697 /* 56906 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20698 /* 56909 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp),
20699 /* 56914 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
20700 /* 56917 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20701 /* 56920 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20702 /* 56923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20703 /* 56927 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20704 /* 56931 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20705 /* 56935 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4040:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULpd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20706 /* 56935 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpd),
20707 /* 56938 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20708 /* 56940 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20709 /* 56942 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20710 /* 56944 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20711 /* 56947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20712 /* 56953 */ GIR_RootConstrainSelectedInstOperands,
20713 /* 56954 */ // GIR_Coverage, 960,
20714 /* 56954 */ GIR_EraseRootFromParent_Done,
20715 /* 56955 */ // Label 1245: @56955
20716 /* 56955 */ GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(57009), // Rule ID 961 //
20717 /* 56960 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20718 /* 56963 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmulp),
20719 /* 56968 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
20720 /* 56971 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
20721 /* 56974 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
20722 /* 56977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20723 /* 56981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20724 /* 56985 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20725 /* 56989 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4040:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMULpq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
20726 /* 56989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULpq),
20727 /* 56992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20728 /* 56994 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20729 /* 56996 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20730 /* 56998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20731 /* 57001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20732 /* 57007 */ GIR_RootConstrainSelectedInstOperands,
20733 /* 57008 */ // GIR_Coverage, 961,
20734 /* 57008 */ GIR_EraseRootFromParent_Done,
20735 /* 57009 */ // Label 1246: @57009
20736 /* 57009 */ GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(57063), // Rule ID 974 //
20737 /* 57014 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20738 /* 57017 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh),
20739 /* 57022 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20740 /* 57025 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20741 /* 57028 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20742 /* 57031 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20743 /* 57035 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20744 /* 57039 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20745 /* 57043 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4051:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20746 /* 57043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i16),
20747 /* 57046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20748 /* 57048 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20749 /* 57050 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20750 /* 57052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20751 /* 57055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20752 /* 57061 */ GIR_RootConstrainSelectedInstOperands,
20753 /* 57062 */ // GIR_Coverage, 974,
20754 /* 57062 */ GIR_EraseRootFromParent_Done,
20755 /* 57063 */ // Label 1247: @57063
20756 /* 57063 */ GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(57117), // Rule ID 975 //
20757 /* 57068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20758 /* 57071 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh),
20759 /* 57076 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20760 /* 57079 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20761 /* 57082 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20762 /* 57085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20763 /* 57089 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20764 /* 57093 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20765 /* 57097 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4051:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20766 /* 57097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv2i32),
20767 /* 57100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20768 /* 57102 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20769 /* 57104 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20770 /* 57106 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20771 /* 57109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20772 /* 57115 */ GIR_RootConstrainSelectedInstOperands,
20773 /* 57116 */ // GIR_Coverage, 975,
20774 /* 57116 */ GIR_EraseRootFromParent_Done,
20775 /* 57117 */ // Label 1248: @57117
20776 /* 57117 */ GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(57171), // Rule ID 976 //
20777 /* 57122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20778 /* 57125 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh),
20779 /* 57130 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20780 /* 57133 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20781 /* 57136 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20782 /* 57139 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20783 /* 57143 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20784 /* 57147 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20785 /* 57151 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4051:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20786 /* 57151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv8i16),
20787 /* 57154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20788 /* 57156 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20789 /* 57158 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20790 /* 57160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20791 /* 57163 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20792 /* 57169 */ GIR_RootConstrainSelectedInstOperands,
20793 /* 57170 */ // GIR_Coverage, 976,
20794 /* 57170 */ GIR_EraseRootFromParent_Done,
20795 /* 57171 */ // Label 1249: @57171
20796 /* 57171 */ GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(57225), // Rule ID 977 //
20797 /* 57176 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20798 /* 57179 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmulh),
20799 /* 57184 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20800 /* 57187 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20801 /* 57190 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20802 /* 57193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20803 /* 57197 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20804 /* 57201 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20805 /* 57205 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4051:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20806 /* 57205 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULHv4i32),
20807 /* 57208 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20808 /* 57210 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20809 /* 57212 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20810 /* 57214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20811 /* 57217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20812 /* 57223 */ GIR_RootConstrainSelectedInstOperands,
20813 /* 57224 */ // GIR_Coverage, 977,
20814 /* 57224 */ GIR_EraseRootFromParent_Done,
20815 /* 57225 */ // Label 1250: @57225
20816 /* 57225 */ GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(57279), // Rule ID 982 //
20817 /* 57230 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20818 /* 57233 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh),
20819 /* 57238 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20820 /* 57241 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20821 /* 57244 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20822 /* 57247 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20823 /* 57251 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20824 /* 57255 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20825 /* 57259 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4059:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMULHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20826 /* 57259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i16),
20827 /* 57262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20828 /* 57264 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20829 /* 57266 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20830 /* 57268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20831 /* 57271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20832 /* 57277 */ GIR_RootConstrainSelectedInstOperands,
20833 /* 57278 */ // GIR_Coverage, 982,
20834 /* 57278 */ GIR_EraseRootFromParent_Done,
20835 /* 57279 */ // Label 1251: @57279
20836 /* 57279 */ GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(57333), // Rule ID 983 //
20837 /* 57284 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20838 /* 57287 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh),
20839 /* 57292 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20840 /* 57295 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20841 /* 57298 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20842 /* 57301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20843 /* 57305 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20844 /* 57309 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20845 /* 57313 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4059:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMULHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20846 /* 57313 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv2i32),
20847 /* 57316 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20848 /* 57318 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20849 /* 57320 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20850 /* 57322 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20851 /* 57325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20852 /* 57331 */ GIR_RootConstrainSelectedInstOperands,
20853 /* 57332 */ // GIR_Coverage, 983,
20854 /* 57332 */ GIR_EraseRootFromParent_Done,
20855 /* 57333 */ // Label 1252: @57333
20856 /* 57333 */ GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(57387), // Rule ID 984 //
20857 /* 57338 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20858 /* 57341 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh),
20859 /* 57346 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20860 /* 57349 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
20861 /* 57352 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
20862 /* 57355 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20863 /* 57359 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20864 /* 57363 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20865 /* 57367 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4059:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMULHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
20866 /* 57367 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv8i16),
20867 /* 57370 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20868 /* 57372 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20869 /* 57374 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20870 /* 57376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20871 /* 57379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20872 /* 57385 */ GIR_RootConstrainSelectedInstOperands,
20873 /* 57386 */ // GIR_Coverage, 984,
20874 /* 57386 */ GIR_EraseRootFromParent_Done,
20875 /* 57387 */ // Label 1253: @57387
20876 /* 57387 */ GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(57441), // Rule ID 985 //
20877 /* 57392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20878 /* 57395 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmulh),
20879 /* 57400 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20880 /* 57403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
20881 /* 57406 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
20882 /* 57409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20883 /* 57413 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20884 /* 57417 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20885 /* 57421 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4059:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMULHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
20886 /* 57421 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMULHv4i32),
20887 /* 57424 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20888 /* 57426 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20889 /* 57428 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20890 /* 57430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20891 /* 57433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20892 /* 57439 */ GIR_RootConstrainSelectedInstOperands,
20893 /* 57440 */ // GIR_Coverage, 985,
20894 /* 57440 */ GIR_EraseRootFromParent_Done,
20895 /* 57441 */ // Label 1254: @57441
20896 /* 57441 */ GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(57495), // Rule ID 996 //
20897 /* 57446 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20898 /* 57449 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp),
20899 /* 57454 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
20900 /* 57457 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
20901 /* 57460 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
20902 /* 57463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20903 /* 57467 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20904 /* 57471 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20905 /* 57475 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4037:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMULLp8:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
20906 /* 57475 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp8),
20907 /* 57478 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20908 /* 57480 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20909 /* 57482 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20910 /* 57484 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20911 /* 57487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20912 /* 57493 */ GIR_RootConstrainSelectedInstOperands,
20913 /* 57494 */ // GIR_Coverage, 996,
20914 /* 57494 */ GIR_EraseRootFromParent_Done,
20915 /* 57495 */ // Label 1255: @57495
20916 /* 57495 */ GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(57540), // Rule ID 997 //
20917 /* 57500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8),
20918 /* 57503 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vmullp),
20919 /* 57508 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20920 /* 57511 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
20921 /* 57514 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
20922 /* 57517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20923 /* 57521 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20924 /* 57525 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20925 /* 57529 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4037:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VMULLp64:{ *:[v2i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
20926 /* 57529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULLp64),
20927 /* 57532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20928 /* 57534 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20929 /* 57536 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20930 /* 57538 */ GIR_RootConstrainSelectedInstOperands,
20931 /* 57539 */ // GIR_Coverage, 997,
20932 /* 57539 */ GIR_EraseRootFromParent_Done,
20933 /* 57540 */ // Label 1256: @57540
20934 /* 57540 */ GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(57594), // Rule ID 1002 //
20935 /* 57545 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20936 /* 57548 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
20937 /* 57553 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
20938 /* 57556 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20939 /* 57559 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20940 /* 57562 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20941 /* 57566 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20942 /* 57570 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20943 /* 57574 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4052:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQDMULLv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20944 /* 57574 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv4i32),
20945 /* 57577 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20946 /* 57579 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20947 /* 57581 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20948 /* 57583 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20949 /* 57586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20950 /* 57592 */ GIR_RootConstrainSelectedInstOperands,
20951 /* 57593 */ // GIR_Coverage, 1002,
20952 /* 57593 */ GIR_EraseRootFromParent_Done,
20953 /* 57594 */ // Label 1257: @57594
20954 /* 57594 */ GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(57648), // Rule ID 1003 //
20955 /* 57599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20956 /* 57602 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
20957 /* 57607 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
20958 /* 57610 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20959 /* 57613 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
20960 /* 57616 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
20961 /* 57620 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20962 /* 57624 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20963 /* 57628 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4052:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQDMULLv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
20964 /* 57628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMULLv2i64),
20965 /* 57631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20966 /* 57633 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20967 /* 57635 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20968 /* 57637 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20969 /* 57640 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20970 /* 57646 */ GIR_RootConstrainSelectedInstOperands,
20971 /* 57647 */ // GIR_Coverage, 1003,
20972 /* 57647 */ GIR_EraseRootFromParent_Done,
20973 /* 57648 */ // Label 1258: @57648
20974 /* 57648 */ GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(57702), // Rule ID 1157 //
20975 /* 57653 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20976 /* 57656 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
20977 /* 57661 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
20978 /* 57664 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
20979 /* 57667 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
20980 /* 57670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20981 /* 57674 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20982 /* 57678 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
20983 /* 57682 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4016:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
20984 /* 57682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i16),
20985 /* 57685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
20986 /* 57687 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
20987 /* 57689 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
20988 /* 57691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
20989 /* 57694 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
20990 /* 57700 */ GIR_RootConstrainSelectedInstOperands,
20991 /* 57701 */ // GIR_Coverage, 1157,
20992 /* 57701 */ GIR_EraseRootFromParent_Done,
20993 /* 57702 */ // Label 1259: @57702
20994 /* 57702 */ GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(57756), // Rule ID 1158 //
20995 /* 57707 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
20996 /* 57710 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
20997 /* 57715 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
20998 /* 57718 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
20999 /* 57721 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21000 /* 57724 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21001 /* 57728 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21002 /* 57732 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21003 /* 57736 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4016:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21004 /* 57736 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv2i32),
21005 /* 57739 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21006 /* 57741 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21007 /* 57743 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21008 /* 57745 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21009 /* 57748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21010 /* 57754 */ GIR_RootConstrainSelectedInstOperands,
21011 /* 57755 */ // GIR_Coverage, 1158,
21012 /* 57755 */ GIR_EraseRootFromParent_Done,
21013 /* 57756 */ // Label 1260: @57756
21014 /* 57756 */ GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(57810), // Rule ID 1159 //
21015 /* 57761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21016 /* 57764 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
21017 /* 57769 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21018 /* 57772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21019 /* 57775 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21020 /* 57778 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21021 /* 57782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21022 /* 57786 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21023 /* 57790 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4016:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
21024 /* 57790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i16),
21025 /* 57793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21026 /* 57795 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21027 /* 57797 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21028 /* 57799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21029 /* 57802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21030 /* 57808 */ GIR_RootConstrainSelectedInstOperands,
21031 /* 57809 */ // GIR_Coverage, 1159,
21032 /* 57809 */ GIR_EraseRootFromParent_Done,
21033 /* 57810 */ // Label 1261: @57810
21034 /* 57810 */ GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(57864), // Rule ID 1160 //
21035 /* 57815 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21036 /* 57818 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
21037 /* 57823 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21038 /* 57826 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21039 /* 57829 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21040 /* 57832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21041 /* 57836 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21042 /* 57840 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21043 /* 57844 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4016:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
21044 /* 57844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv4i32),
21045 /* 57847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21046 /* 57849 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21047 /* 57851 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21048 /* 57853 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21049 /* 57856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21050 /* 57862 */ GIR_RootConstrainSelectedInstOperands,
21051 /* 57863 */ // GIR_Coverage, 1160,
21052 /* 57863 */ GIR_EraseRootFromParent_Done,
21053 /* 57864 */ // Label 1262: @57864
21054 /* 57864 */ GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(57918), // Rule ID 1161 //
21055 /* 57869 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21056 /* 57872 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
21057 /* 57877 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
21058 /* 57880 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21059 /* 57883 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21060 /* 57886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21061 /* 57890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21062 /* 57894 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21063 /* 57898 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4016:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21064 /* 57898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv8i8),
21065 /* 57901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21066 /* 57903 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21067 /* 57905 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21068 /* 57907 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21069 /* 57910 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21070 /* 57916 */ GIR_RootConstrainSelectedInstOperands,
21071 /* 57917 */ // GIR_Coverage, 1161,
21072 /* 57917 */ GIR_EraseRootFromParent_Done,
21073 /* 57918 */ // Label 1263: @57918
21074 /* 57918 */ GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(57972), // Rule ID 1162 //
21075 /* 57923 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21076 /* 57926 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubs),
21077 /* 57931 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
21078 /* 57934 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21079 /* 57937 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
21080 /* 57940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21081 /* 57944 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21082 /* 57948 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21083 /* 57952 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4016:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
21084 /* 57952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBsv16i8),
21085 /* 57955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21086 /* 57957 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21087 /* 57959 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21088 /* 57961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21089 /* 57964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21090 /* 57970 */ GIR_RootConstrainSelectedInstOperands,
21091 /* 57971 */ // GIR_Coverage, 1162,
21092 /* 57971 */ GIR_EraseRootFromParent_Done,
21093 /* 57972 */ // Label 1264: @57972
21094 /* 57972 */ GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(58026), // Rule ID 1163 //
21095 /* 57977 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21096 /* 57980 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
21097 /* 57985 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21098 /* 57988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21099 /* 57991 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21100 /* 57994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21101 /* 57998 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21102 /* 58002 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21103 /* 58006 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4017:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VHSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21104 /* 58006 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i16),
21105 /* 58009 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21106 /* 58011 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21107 /* 58013 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21108 /* 58015 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21109 /* 58018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21110 /* 58024 */ GIR_RootConstrainSelectedInstOperands,
21111 /* 58025 */ // GIR_Coverage, 1163,
21112 /* 58025 */ GIR_EraseRootFromParent_Done,
21113 /* 58026 */ // Label 1265: @58026
21114 /* 58026 */ GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(58080), // Rule ID 1164 //
21115 /* 58031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21116 /* 58034 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
21117 /* 58039 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21118 /* 58042 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21119 /* 58045 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21120 /* 58048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21121 /* 58052 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21122 /* 58056 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21123 /* 58060 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4017:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VHSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21124 /* 58060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv2i32),
21125 /* 58063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21126 /* 58065 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21127 /* 58067 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21128 /* 58069 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21129 /* 58072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21130 /* 58078 */ GIR_RootConstrainSelectedInstOperands,
21131 /* 58079 */ // GIR_Coverage, 1164,
21132 /* 58079 */ GIR_EraseRootFromParent_Done,
21133 /* 58080 */ // Label 1266: @58080
21134 /* 58080 */ GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(58134), // Rule ID 1165 //
21135 /* 58085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21136 /* 58088 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
21137 /* 58093 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21138 /* 58096 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21139 /* 58099 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21140 /* 58102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21141 /* 58106 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21142 /* 58110 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21143 /* 58114 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4017:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VHSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
21144 /* 58114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i16),
21145 /* 58117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21146 /* 58119 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21147 /* 58121 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21148 /* 58123 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21149 /* 58126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21150 /* 58132 */ GIR_RootConstrainSelectedInstOperands,
21151 /* 58133 */ // GIR_Coverage, 1165,
21152 /* 58133 */ GIR_EraseRootFromParent_Done,
21153 /* 58134 */ // Label 1267: @58134
21154 /* 58134 */ GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(58188), // Rule ID 1166 //
21155 /* 58139 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21156 /* 58142 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
21157 /* 58147 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21158 /* 58150 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21159 /* 58153 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21160 /* 58156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21161 /* 58160 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21162 /* 58164 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21163 /* 58168 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4017:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VHSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
21164 /* 58168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv4i32),
21165 /* 58171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21166 /* 58173 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21167 /* 58175 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21168 /* 58177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21169 /* 58180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21170 /* 58186 */ GIR_RootConstrainSelectedInstOperands,
21171 /* 58187 */ // GIR_Coverage, 1166,
21172 /* 58187 */ GIR_EraseRootFromParent_Done,
21173 /* 58188 */ // Label 1268: @58188
21174 /* 58188 */ GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(58242), // Rule ID 1167 //
21175 /* 58193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21176 /* 58196 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
21177 /* 58201 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
21178 /* 58204 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21179 /* 58207 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21180 /* 58210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21181 /* 58214 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21182 /* 58218 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21183 /* 58222 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4017:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VHSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21184 /* 58222 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv8i8),
21185 /* 58225 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21186 /* 58227 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21187 /* 58229 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21188 /* 58231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21189 /* 58234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21190 /* 58240 */ GIR_RootConstrainSelectedInstOperands,
21191 /* 58241 */ // GIR_Coverage, 1167,
21192 /* 58241 */ GIR_EraseRootFromParent_Done,
21193 /* 58242 */ // Label 1269: @58242
21194 /* 58242 */ GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(58296), // Rule ID 1168 //
21195 /* 58247 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21196 /* 58250 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vhsubu),
21197 /* 58255 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
21198 /* 58258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
21199 /* 58261 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
21200 /* 58264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21201 /* 58268 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21202 /* 58272 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21203 /* 58276 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4017:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VHSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
21204 /* 58276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VHSUBuv16i8),
21205 /* 58279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21206 /* 58281 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21207 /* 58283 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21208 /* 58285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21209 /* 58288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21210 /* 58294 */ GIR_RootConstrainSelectedInstOperands,
21211 /* 58295 */ // GIR_Coverage, 1168,
21212 /* 58295 */ GIR_EraseRootFromParent_Done,
21213 /* 58296 */ // Label 1270: @58296
21214 /* 58296 */ GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(58350), // Rule ID 1185 //
21215 /* 58301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21216 /* 58304 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn),
21217 /* 58309 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
21218 /* 58312 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21219 /* 58315 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21220 /* 58318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21221 /* 58322 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21222 /* 58326 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21223 /* 58330 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4081:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VRSUBHNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
21224 /* 58330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv8i8),
21225 /* 58333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21226 /* 58335 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21227 /* 58337 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21228 /* 58339 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21229 /* 58342 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21230 /* 58348 */ GIR_RootConstrainSelectedInstOperands,
21231 /* 58349 */ // GIR_Coverage, 1185,
21232 /* 58349 */ GIR_EraseRootFromParent_Done,
21233 /* 58350 */ // Label 1271: @58350
21234 /* 58350 */ GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(58404), // Rule ID 1186 //
21235 /* 58355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21236 /* 58358 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn),
21237 /* 58363 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21238 /* 58366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21239 /* 58369 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21240 /* 58372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21241 /* 58376 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21242 /* 58380 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21243 /* 58384 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4081:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VRSUBHNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
21244 /* 58384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv4i16),
21245 /* 58387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21246 /* 58389 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21247 /* 58391 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21248 /* 58393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21249 /* 58396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21250 /* 58402 */ GIR_RootConstrainSelectedInstOperands,
21251 /* 58403 */ // GIR_Coverage, 1186,
21252 /* 58403 */ GIR_EraseRootFromParent_Done,
21253 /* 58404 */ // Label 1272: @58404
21254 /* 58404 */ GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(58458), // Rule ID 1187 //
21255 /* 58409 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21256 /* 58412 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsubhn),
21257 /* 58417 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21258 /* 58420 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21259 /* 58423 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
21260 /* 58426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21261 /* 58430 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21262 /* 58434 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21263 /* 58438 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4081:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VRSUBHNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
21264 /* 58438 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSUBHNv2i32),
21265 /* 58441 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21266 /* 58443 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21267 /* 58445 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21268 /* 58447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21269 /* 58450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21270 /* 58456 */ GIR_RootConstrainSelectedInstOperands,
21271 /* 58457 */ // GIR_Coverage, 1187,
21272 /* 58457 */ GIR_EraseRootFromParent_Done,
21273 /* 58458 */ // Label 1273: @58458
21274 /* 58458 */ GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(58512), // Rule ID 1280 //
21275 /* 58463 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21276 /* 58466 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge),
21277 /* 58471 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21278 /* 58474 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21279 /* 58477 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21280 /* 58480 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21281 /* 58484 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21282 /* 58488 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21283 /* 58492 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3992:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGEfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21284 /* 58492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfd),
21285 /* 58495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21286 /* 58497 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21287 /* 58499 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21288 /* 58501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21289 /* 58504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21290 /* 58510 */ GIR_RootConstrainSelectedInstOperands,
21291 /* 58511 */ // GIR_Coverage, 1280,
21292 /* 58511 */ GIR_EraseRootFromParent_Done,
21293 /* 58512 */ // Label 1274: @58512
21294 /* 58512 */ GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(58566), // Rule ID 1281 //
21295 /* 58517 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21296 /* 58520 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge),
21297 /* 58525 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21298 /* 58528 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21299 /* 58531 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21300 /* 58534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21301 /* 58538 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21302 /* 58542 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21303 /* 58546 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3992:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGEfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21304 /* 58546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEfq),
21305 /* 58549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21306 /* 58551 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21307 /* 58553 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21308 /* 58555 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21309 /* 58558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21310 /* 58564 */ GIR_RootConstrainSelectedInstOperands,
21311 /* 58565 */ // GIR_Coverage, 1281,
21312 /* 58565 */ GIR_EraseRootFromParent_Done,
21313 /* 58566 */ // Label 1275: @58566
21314 /* 58566 */ GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(58620), // Rule ID 1282 //
21315 /* 58571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21316 /* 58574 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge),
21317 /* 58579 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21318 /* 58582 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21319 /* 58585 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21320 /* 58588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21321 /* 58592 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21322 /* 58596 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21323 /* 58600 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3992:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGEhd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21324 /* 58600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhd),
21325 /* 58603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21326 /* 58605 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21327 /* 58607 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21328 /* 58609 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21329 /* 58612 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21330 /* 58618 */ GIR_RootConstrainSelectedInstOperands,
21331 /* 58619 */ // GIR_Coverage, 1282,
21332 /* 58619 */ GIR_EraseRootFromParent_Done,
21333 /* 58620 */ // Label 1276: @58620
21334 /* 58620 */ GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(58674), // Rule ID 1283 //
21335 /* 58625 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21336 /* 58628 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacge),
21337 /* 58633 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21338 /* 58636 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21339 /* 58639 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21340 /* 58642 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21341 /* 58646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21342 /* 58650 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21343 /* 58654 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3992:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGEhq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21344 /* 58654 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGEhq),
21345 /* 58657 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21346 /* 58659 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21347 /* 58661 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21348 /* 58663 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21349 /* 58666 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21350 /* 58672 */ GIR_RootConstrainSelectedInstOperands,
21351 /* 58673 */ // GIR_Coverage, 1283,
21352 /* 58673 */ GIR_EraseRootFromParent_Done,
21353 /* 58674 */ // Label 1277: @58674
21354 /* 58674 */ GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(58728), // Rule ID 1284 //
21355 /* 58679 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21356 /* 58682 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt),
21357 /* 58687 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21358 /* 58690 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21359 /* 58693 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21360 /* 58696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21361 /* 58700 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21362 /* 58704 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21363 /* 58708 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3993:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VACGTfd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21364 /* 58708 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfd),
21365 /* 58711 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21366 /* 58713 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21367 /* 58715 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21368 /* 58717 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21369 /* 58720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21370 /* 58726 */ GIR_RootConstrainSelectedInstOperands,
21371 /* 58727 */ // GIR_Coverage, 1284,
21372 /* 58727 */ GIR_EraseRootFromParent_Done,
21373 /* 58728 */ // Label 1278: @58728
21374 /* 58728 */ GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(58782), // Rule ID 1285 //
21375 /* 58733 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21376 /* 58736 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt),
21377 /* 58741 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21378 /* 58744 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21379 /* 58747 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21380 /* 58750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21381 /* 58754 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21382 /* 58758 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21383 /* 58762 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3993:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VACGTfq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21384 /* 58762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGTfq),
21385 /* 58765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21386 /* 58767 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21387 /* 58769 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21388 /* 58771 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21389 /* 58774 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21390 /* 58780 */ GIR_RootConstrainSelectedInstOperands,
21391 /* 58781 */ // GIR_Coverage, 1285,
21392 /* 58781 */ GIR_EraseRootFromParent_Done,
21393 /* 58782 */ // Label 1279: @58782
21394 /* 58782 */ GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(58836), // Rule ID 1286 //
21395 /* 58787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21396 /* 58790 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt),
21397 /* 58795 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21398 /* 58798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21399 /* 58801 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21400 /* 58804 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21401 /* 58808 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21402 /* 58812 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21403 /* 58816 */ // (intrinsic_wo_chain:{ *:[v4i16] } 3993:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VACGThd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21404 /* 58816 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThd),
21405 /* 58819 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21406 /* 58821 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21407 /* 58823 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21408 /* 58825 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21409 /* 58828 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21410 /* 58834 */ GIR_RootConstrainSelectedInstOperands,
21411 /* 58835 */ // GIR_Coverage, 1286,
21412 /* 58835 */ GIR_EraseRootFromParent_Done,
21413 /* 58836 */ // Label 1280: @58836
21414 /* 58836 */ GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(58890), // Rule ID 1287 //
21415 /* 58841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21416 /* 58844 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vacgt),
21417 /* 58849 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21418 /* 58852 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21419 /* 58855 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21420 /* 58858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21421 /* 58862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21422 /* 58866 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21423 /* 58870 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3993:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VACGThq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21424 /* 58870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VACGThq),
21425 /* 58873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21426 /* 58875 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21427 /* 58877 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21428 /* 58879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21429 /* 58882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21430 /* 58888 */ GIR_RootConstrainSelectedInstOperands,
21431 /* 58889 */ // GIR_Coverage, 1287,
21432 /* 58889 */ GIR_EraseRootFromParent_Done,
21433 /* 58890 */ // Label 1281: @58890
21434 /* 58890 */ GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(58944), // Rule ID 1330 //
21435 /* 58895 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21436 /* 58898 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
21437 /* 58903 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21438 /* 58906 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21439 /* 58909 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21440 /* 58912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21441 /* 58916 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21442 /* 58920 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21443 /* 58924 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3989:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VABDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21444 /* 58924 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfd),
21445 /* 58927 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21446 /* 58929 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21447 /* 58931 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21448 /* 58933 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21449 /* 58936 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21450 /* 58942 */ GIR_RootConstrainSelectedInstOperands,
21451 /* 58943 */ // GIR_Coverage, 1330,
21452 /* 58943 */ GIR_EraseRootFromParent_Done,
21453 /* 58944 */ // Label 1282: @58944
21454 /* 58944 */ GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(58998), // Rule ID 1331 //
21455 /* 58949 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21456 /* 58952 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
21457 /* 58957 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21458 /* 58960 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21459 /* 58963 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21460 /* 58966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21461 /* 58970 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21462 /* 58974 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21463 /* 58978 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3989:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VABDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
21464 /* 58978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDfq),
21465 /* 58981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21466 /* 58983 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21467 /* 58985 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21468 /* 58987 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21469 /* 58990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21470 /* 58996 */ GIR_RootConstrainSelectedInstOperands,
21471 /* 58997 */ // GIR_Coverage, 1331,
21472 /* 58997 */ GIR_EraseRootFromParent_Done,
21473 /* 58998 */ // Label 1283: @58998
21474 /* 58998 */ GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(59052), // Rule ID 1332 //
21475 /* 59003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21476 /* 59006 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
21477 /* 59011 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21478 /* 59014 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21479 /* 59017 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21480 /* 59020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21481 /* 59024 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21482 /* 59028 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21483 /* 59032 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3989:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VABDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21484 /* 59032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhd),
21485 /* 59035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21486 /* 59037 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21487 /* 59039 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21488 /* 59041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21489 /* 59044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21490 /* 59050 */ GIR_RootConstrainSelectedInstOperands,
21491 /* 59051 */ // GIR_Coverage, 1332,
21492 /* 59051 */ GIR_EraseRootFromParent_Done,
21493 /* 59052 */ // Label 1284: @59052
21494 /* 59052 */ GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(59106), // Rule ID 1333 //
21495 /* 59057 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21496 /* 59060 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vabds),
21497 /* 59065 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21498 /* 59068 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21499 /* 59071 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21500 /* 59074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21501 /* 59078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21502 /* 59082 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21503 /* 59086 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3989:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VABDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
21504 /* 59086 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDhq),
21505 /* 59089 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21506 /* 59091 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21507 /* 59093 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21508 /* 59095 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21509 /* 59098 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21510 /* 59104 */ GIR_RootConstrainSelectedInstOperands,
21511 /* 59105 */ // GIR_Coverage, 1333,
21512 /* 59105 */ GIR_EraseRootFromParent_Done,
21513 /* 59106 */ // Label 1285: @59106
21514 /* 59106 */ GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(59160), // Rule ID 1398 //
21515 /* 59111 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21516 /* 59114 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
21517 /* 59119 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
21518 /* 59122 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21519 /* 59125 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21520 /* 59128 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21521 /* 59132 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21522 /* 59136 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21523 /* 59140 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4043:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPADDi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21524 /* 59140 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi8),
21525 /* 59143 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21526 /* 59145 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21527 /* 59147 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21528 /* 59149 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21529 /* 59152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21530 /* 59158 */ GIR_RootConstrainSelectedInstOperands,
21531 /* 59159 */ // GIR_Coverage, 1398,
21532 /* 59159 */ GIR_EraseRootFromParent_Done,
21533 /* 59160 */ // Label 1286: @59160
21534 /* 59160 */ GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(59214), // Rule ID 1399 //
21535 /* 59165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21536 /* 59168 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
21537 /* 59173 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21538 /* 59176 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21539 /* 59179 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21540 /* 59182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21541 /* 59186 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21542 /* 59190 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21543 /* 59194 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4043:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPADDi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21544 /* 59194 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi16),
21545 /* 59197 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21546 /* 59199 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21547 /* 59201 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21548 /* 59203 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21549 /* 59206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21550 /* 59212 */ GIR_RootConstrainSelectedInstOperands,
21551 /* 59213 */ // GIR_Coverage, 1399,
21552 /* 59213 */ GIR_EraseRootFromParent_Done,
21553 /* 59214 */ // Label 1287: @59214
21554 /* 59214 */ GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(59268), // Rule ID 1400 //
21555 /* 59219 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21556 /* 59222 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
21557 /* 59227 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21558 /* 59230 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21559 /* 59233 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21560 /* 59236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21561 /* 59240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21562 /* 59244 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21563 /* 59248 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4043:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPADDi32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21564 /* 59248 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDi32),
21565 /* 59251 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21566 /* 59253 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21567 /* 59255 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21568 /* 59257 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21569 /* 59260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21570 /* 59266 */ GIR_RootConstrainSelectedInstOperands,
21571 /* 59267 */ // GIR_Coverage, 1400,
21572 /* 59267 */ GIR_EraseRootFromParent_Done,
21573 /* 59268 */ // Label 1288: @59268
21574 /* 59268 */ GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(59322), // Rule ID 1401 //
21575 /* 59273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21576 /* 59276 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
21577 /* 59281 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21578 /* 59284 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21579 /* 59287 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21580 /* 59290 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21581 /* 59294 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21582 /* 59298 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21583 /* 59302 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4043:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPADDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21584 /* 59302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDf),
21585 /* 59305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21586 /* 59307 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21587 /* 59309 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21588 /* 59311 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21589 /* 59314 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21590 /* 59320 */ GIR_RootConstrainSelectedInstOperands,
21591 /* 59321 */ // GIR_Coverage, 1401,
21592 /* 59321 */ GIR_EraseRootFromParent_Done,
21593 /* 59322 */ // Label 1289: @59322
21594 /* 59322 */ GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(59376), // Rule ID 1402 //
21595 /* 59327 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21596 /* 59330 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadd),
21597 /* 59335 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21598 /* 59338 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21599 /* 59341 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21600 /* 59344 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21601 /* 59348 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21602 /* 59352 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21603 /* 59356 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4043:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPADDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
21604 /* 59356 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADDh),
21605 /* 59359 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21606 /* 59361 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21607 /* 59363 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21608 /* 59365 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21609 /* 59368 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21610 /* 59374 */ GIR_RootConstrainSelectedInstOperands,
21611 /* 59375 */ // GIR_Coverage, 1402,
21612 /* 59375 */ GIR_EraseRootFromParent_Done,
21613 /* 59376 */ // Label 1290: @59376
21614 /* 59376 */ GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(59430), // Rule ID 1415 //
21615 /* 59381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21616 /* 59384 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21617 /* 59389 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21618 /* 59392 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21619 /* 59395 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21620 /* 59398 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21621 /* 59402 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21622 /* 59406 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21623 /* 59410 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4041:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALsv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
21624 /* 59410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i8),
21625 /* 59413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21626 /* 59415 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21627 /* 59417 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21628 /* 59419 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21629 /* 59422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21630 /* 59428 */ GIR_RootConstrainSelectedInstOperands,
21631 /* 59429 */ // GIR_Coverage, 1415,
21632 /* 59429 */ GIR_EraseRootFromParent_Done,
21633 /* 59430 */ // Label 1291: @59430
21634 /* 59430 */ GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(59484), // Rule ID 1416 //
21635 /* 59435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21636 /* 59438 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21637 /* 59443 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21638 /* 59446 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21639 /* 59449 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21640 /* 59452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21641 /* 59456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21642 /* 59460 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21643 /* 59464 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4041:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALsv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
21644 /* 59464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i16),
21645 /* 59467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21646 /* 59469 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21647 /* 59471 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21648 /* 59473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21649 /* 59476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21650 /* 59482 */ GIR_RootConstrainSelectedInstOperands,
21651 /* 59483 */ // GIR_Coverage, 1416,
21652 /* 59483 */ GIR_EraseRootFromParent_Done,
21653 /* 59484 */ // Label 1292: @59484
21654 /* 59484 */ GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(59538), // Rule ID 1417 //
21655 /* 59489 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21656 /* 59492 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21657 /* 59497 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21658 /* 59500 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21659 /* 59503 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21660 /* 59506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21661 /* 59510 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21662 /* 59514 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21663 /* 59518 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4041:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALsv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
21664 /* 59518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv2i32),
21665 /* 59521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21666 /* 59523 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21667 /* 59525 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21668 /* 59527 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21669 /* 59530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21670 /* 59536 */ GIR_RootConstrainSelectedInstOperands,
21671 /* 59537 */ // GIR_Coverage, 1417,
21672 /* 59537 */ GIR_EraseRootFromParent_Done,
21673 /* 59538 */ // Label 1293: @59538
21674 /* 59538 */ GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(59592), // Rule ID 1418 //
21675 /* 59543 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21676 /* 59546 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21677 /* 59551 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21678 /* 59554 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21679 /* 59557 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
21680 /* 59560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21681 /* 59564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21682 /* 59568 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21683 /* 59572 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4041:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALsv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
21684 /* 59572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv16i8),
21685 /* 59575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21686 /* 59577 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21687 /* 59579 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21688 /* 59581 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21689 /* 59584 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21690 /* 59590 */ GIR_RootConstrainSelectedInstOperands,
21691 /* 59591 */ // GIR_Coverage, 1418,
21692 /* 59591 */ GIR_EraseRootFromParent_Done,
21693 /* 59592 */ // Label 1294: @59592
21694 /* 59592 */ GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(59646), // Rule ID 1419 //
21695 /* 59597 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21696 /* 59600 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21697 /* 59605 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21698 /* 59608 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21699 /* 59611 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21700 /* 59614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21701 /* 59618 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21702 /* 59622 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21703 /* 59626 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4041:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALsv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
21704 /* 59626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv8i16),
21705 /* 59629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21706 /* 59631 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21707 /* 59633 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21708 /* 59635 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21709 /* 59638 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21710 /* 59644 */ GIR_RootConstrainSelectedInstOperands,
21711 /* 59645 */ // GIR_Coverage, 1419,
21712 /* 59645 */ GIR_EraseRootFromParent_Done,
21713 /* 59646 */ // Label 1295: @59646
21714 /* 59646 */ GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(59700), // Rule ID 1420 //
21715 /* 59651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21716 /* 59654 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadals),
21717 /* 59659 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
21718 /* 59662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21719 /* 59665 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21720 /* 59668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21721 /* 59672 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21722 /* 59676 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21723 /* 59680 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4041:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALsv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
21724 /* 59680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALsv4i32),
21725 /* 59683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21726 /* 59685 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21727 /* 59687 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21728 /* 59689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21729 /* 59692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21730 /* 59698 */ GIR_RootConstrainSelectedInstOperands,
21731 /* 59699 */ // GIR_Coverage, 1420,
21732 /* 59699 */ GIR_EraseRootFromParent_Done,
21733 /* 59700 */ // Label 1296: @59700
21734 /* 59700 */ GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(59754), // Rule ID 1421 //
21735 /* 59705 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21736 /* 59708 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21737 /* 59713 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21738 /* 59716 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21739 /* 59719 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21740 /* 59722 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21741 /* 59726 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21742 /* 59730 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21743 /* 59734 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4042:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm) => (VPADALuv8i8:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v8i8] }:$Vm)
21744 /* 59734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i8),
21745 /* 59737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21746 /* 59739 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21747 /* 59741 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21748 /* 59743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21749 /* 59746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21750 /* 59752 */ GIR_RootConstrainSelectedInstOperands,
21751 /* 59753 */ // GIR_Coverage, 1421,
21752 /* 59753 */ GIR_EraseRootFromParent_Done,
21753 /* 59754 */ // Label 1297: @59754
21754 /* 59754 */ GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(59808), // Rule ID 1422 //
21755 /* 59759 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21756 /* 59762 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21757 /* 59767 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21758 /* 59770 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21759 /* 59773 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21760 /* 59776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21761 /* 59780 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21762 /* 59784 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21763 /* 59788 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4042:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm) => (VPADALuv4i16:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v4i16] }:$Vm)
21764 /* 59788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i16),
21765 /* 59791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21766 /* 59793 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21767 /* 59795 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21768 /* 59797 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21769 /* 59800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21770 /* 59806 */ GIR_RootConstrainSelectedInstOperands,
21771 /* 59807 */ // GIR_Coverage, 1422,
21772 /* 59807 */ GIR_EraseRootFromParent_Done,
21773 /* 59808 */ // Label 1298: @59808
21774 /* 59808 */ GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(59862), // Rule ID 1423 //
21775 /* 59813 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21776 /* 59816 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21777 /* 59821 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
21778 /* 59824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
21779 /* 59827 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21780 /* 59830 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21781 /* 59834 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21782 /* 59838 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21783 /* 59842 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4042:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm) => (VPADALuv2i32:{ *:[v1i64] } DPR:{ *:[v1i64] }:$src1, DPR:{ *:[v2i32] }:$Vm)
21784 /* 59842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv2i32),
21785 /* 59845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21786 /* 59847 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21787 /* 59849 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21788 /* 59851 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21789 /* 59854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21790 /* 59860 */ GIR_RootConstrainSelectedInstOperands,
21791 /* 59861 */ // GIR_Coverage, 1423,
21792 /* 59861 */ GIR_EraseRootFromParent_Done,
21793 /* 59862 */ // Label 1299: @59862
21794 /* 59862 */ GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(59916), // Rule ID 1424 //
21795 /* 59867 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21796 /* 59870 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21797 /* 59875 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
21798 /* 59878 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
21799 /* 59881 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
21800 /* 59884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21801 /* 59888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21802 /* 59892 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21803 /* 59896 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4042:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm) => (VPADALuv16i8:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v16i8] }:$Vm)
21804 /* 59896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv16i8),
21805 /* 59899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21806 /* 59901 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21807 /* 59903 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21808 /* 59905 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21809 /* 59908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21810 /* 59914 */ GIR_RootConstrainSelectedInstOperands,
21811 /* 59915 */ // GIR_Coverage, 1424,
21812 /* 59915 */ GIR_EraseRootFromParent_Done,
21813 /* 59916 */ // Label 1300: @59916
21814 /* 59916 */ GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(59970), // Rule ID 1425 //
21815 /* 59921 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21816 /* 59924 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21817 /* 59929 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
21818 /* 59932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
21819 /* 59935 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
21820 /* 59938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21821 /* 59942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21822 /* 59946 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21823 /* 59950 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4042:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm) => (VPADALuv8i16:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v8i16] }:$Vm)
21824 /* 59950 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv8i16),
21825 /* 59953 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21826 /* 59955 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21827 /* 59957 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21828 /* 59959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21829 /* 59962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21830 /* 59968 */ GIR_RootConstrainSelectedInstOperands,
21831 /* 59969 */ // GIR_Coverage, 1425,
21832 /* 59969 */ GIR_EraseRootFromParent_Done,
21833 /* 59970 */ // Label 1301: @59970
21834 /* 59970 */ GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(60024), // Rule ID 1426 //
21835 /* 59975 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21836 /* 59978 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpadalu),
21837 /* 59983 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
21838 /* 59986 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
21839 /* 59989 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
21840 /* 59992 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21841 /* 59996 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21842 /* 60000 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
21843 /* 60004 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4042:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm) => (VPADALuv4i32:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, QPR:{ *:[v4i32] }:$Vm)
21844 /* 60004 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPADALuv4i32),
21845 /* 60007 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21846 /* 60009 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
21847 /* 60011 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21848 /* 60013 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21849 /* 60016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21850 /* 60022 */ GIR_RootConstrainSelectedInstOperands,
21851 /* 60023 */ // GIR_Coverage, 1426,
21852 /* 60023 */ GIR_EraseRootFromParent_Done,
21853 /* 60024 */ // Label 1302: @60024
21854 /* 60024 */ GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(60078), // Rule ID 1427 //
21855 /* 60029 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21856 /* 60032 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21857 /* 60037 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
21858 /* 60040 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21859 /* 60043 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21860 /* 60046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21861 /* 60050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21862 /* 60054 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21863 /* 60058 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4046:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21864 /* 60058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs8),
21865 /* 60061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21866 /* 60063 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21867 /* 60065 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21868 /* 60067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21869 /* 60070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21870 /* 60076 */ GIR_RootConstrainSelectedInstOperands,
21871 /* 60077 */ // GIR_Coverage, 1427,
21872 /* 60077 */ GIR_EraseRootFromParent_Done,
21873 /* 60078 */ // Label 1303: @60078
21874 /* 60078 */ GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(60132), // Rule ID 1428 //
21875 /* 60083 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21876 /* 60086 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21877 /* 60091 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21878 /* 60094 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21879 /* 60097 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21880 /* 60100 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21881 /* 60104 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21882 /* 60108 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21883 /* 60112 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4046:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21884 /* 60112 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs16),
21885 /* 60115 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21886 /* 60117 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21887 /* 60119 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21888 /* 60121 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21889 /* 60124 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21890 /* 60130 */ GIR_RootConstrainSelectedInstOperands,
21891 /* 60131 */ // GIR_Coverage, 1428,
21892 /* 60131 */ GIR_EraseRootFromParent_Done,
21893 /* 60132 */ // Label 1304: @60132
21894 /* 60132 */ GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(60186), // Rule ID 1429 //
21895 /* 60137 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21896 /* 60140 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21897 /* 60145 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21898 /* 60148 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21899 /* 60151 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21900 /* 60154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21901 /* 60158 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21902 /* 60162 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21903 /* 60166 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4046:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21904 /* 60166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXs32),
21905 /* 60169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21906 /* 60171 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21907 /* 60173 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21908 /* 60175 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21909 /* 60178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21910 /* 60184 */ GIR_RootConstrainSelectedInstOperands,
21911 /* 60185 */ // GIR_Coverage, 1429,
21912 /* 60185 */ GIR_EraseRootFromParent_Done,
21913 /* 60186 */ // Label 1305: @60186
21914 /* 60186 */ GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(60240), // Rule ID 1430 //
21915 /* 60191 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21916 /* 60194 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu),
21917 /* 60199 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
21918 /* 60202 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
21919 /* 60205 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
21920 /* 60208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21921 /* 60212 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21922 /* 60216 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21923 /* 60220 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4047:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMAXu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
21924 /* 60220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu8),
21925 /* 60223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21926 /* 60225 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21927 /* 60227 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21928 /* 60229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21929 /* 60232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21930 /* 60238 */ GIR_RootConstrainSelectedInstOperands,
21931 /* 60239 */ // GIR_Coverage, 1430,
21932 /* 60239 */ GIR_EraseRootFromParent_Done,
21933 /* 60240 */ // Label 1306: @60240
21934 /* 60240 */ GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(60294), // Rule ID 1431 //
21935 /* 60245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21936 /* 60248 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu),
21937 /* 60253 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21938 /* 60256 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21939 /* 60259 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
21940 /* 60262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21941 /* 60266 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21942 /* 60270 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21943 /* 60274 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4047:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMAXu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
21944 /* 60274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu16),
21945 /* 60277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21946 /* 60279 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21947 /* 60281 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21948 /* 60283 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21949 /* 60286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21950 /* 60292 */ GIR_RootConstrainSelectedInstOperands,
21951 /* 60293 */ // GIR_Coverage, 1431,
21952 /* 60293 */ GIR_EraseRootFromParent_Done,
21953 /* 60294 */ // Label 1307: @60294
21954 /* 60294 */ GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(60348), // Rule ID 1432 //
21955 /* 60299 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21956 /* 60302 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxu),
21957 /* 60307 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21958 /* 60310 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21959 /* 60313 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21960 /* 60316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21961 /* 60320 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21962 /* 60324 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21963 /* 60328 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4047:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMAXu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
21964 /* 60328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXu32),
21965 /* 60331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21966 /* 60333 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21967 /* 60335 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21968 /* 60337 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21969 /* 60340 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21970 /* 60346 */ GIR_RootConstrainSelectedInstOperands,
21971 /* 60347 */ // GIR_Coverage, 1432,
21972 /* 60347 */ GIR_EraseRootFromParent_Done,
21973 /* 60348 */ // Label 1308: @60348
21974 /* 60348 */ GIM_Try, /*On fail goto*//*Label 1309*/ GIMT_Encode4(60402), // Rule ID 1433 //
21975 /* 60353 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
21976 /* 60356 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21977 /* 60361 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
21978 /* 60364 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
21979 /* 60367 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
21980 /* 60370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21981 /* 60374 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21982 /* 60378 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
21983 /* 60382 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4046:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMAXf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
21984 /* 60382 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXf),
21985 /* 60385 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
21986 /* 60387 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
21987 /* 60389 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
21988 /* 60391 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
21989 /* 60394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
21990 /* 60400 */ GIR_RootConstrainSelectedInstOperands,
21991 /* 60401 */ // GIR_Coverage, 1433,
21992 /* 60401 */ GIR_EraseRootFromParent_Done,
21993 /* 60402 */ // Label 1309: @60402
21994 /* 60402 */ GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(60456), // Rule ID 1434 //
21995 /* 60407 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
21996 /* 60410 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmaxs),
21997 /* 60415 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
21998 /* 60418 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
21999 /* 60421 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22000 /* 60424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22001 /* 60428 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22002 /* 60432 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22003 /* 60436 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4046:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMAXh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
22004 /* 60436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMAXh),
22005 /* 60439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22006 /* 60441 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22007 /* 60443 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22008 /* 60445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22009 /* 60448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22010 /* 60454 */ GIR_RootConstrainSelectedInstOperands,
22011 /* 60455 */ // GIR_Coverage, 1434,
22012 /* 60455 */ GIR_EraseRootFromParent_Done,
22013 /* 60456 */ // Label 1310: @60456
22014 /* 60456 */ GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(60510), // Rule ID 1435 //
22015 /* 60461 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22016 /* 60464 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
22017 /* 60469 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
22018 /* 60472 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22019 /* 60475 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22020 /* 60478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22021 /* 60482 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22022 /* 60486 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22023 /* 60490 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4048:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINs8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
22024 /* 60490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs8),
22025 /* 60493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22026 /* 60495 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22027 /* 60497 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22028 /* 60499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22029 /* 60502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22030 /* 60508 */ GIR_RootConstrainSelectedInstOperands,
22031 /* 60509 */ // GIR_Coverage, 1435,
22032 /* 60509 */ GIR_EraseRootFromParent_Done,
22033 /* 60510 */ // Label 1311: @60510
22034 /* 60510 */ GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(60564), // Rule ID 1436 //
22035 /* 60515 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22036 /* 60518 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
22037 /* 60523 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22038 /* 60526 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22039 /* 60529 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22040 /* 60532 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22041 /* 60536 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22042 /* 60540 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22043 /* 60544 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4048:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINs16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
22044 /* 60544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs16),
22045 /* 60547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22046 /* 60549 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22047 /* 60551 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22048 /* 60553 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22049 /* 60556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22050 /* 60562 */ GIR_RootConstrainSelectedInstOperands,
22051 /* 60563 */ // GIR_Coverage, 1436,
22052 /* 60563 */ GIR_EraseRootFromParent_Done,
22053 /* 60564 */ // Label 1312: @60564
22054 /* 60564 */ GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(60618), // Rule ID 1437 //
22055 /* 60569 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22056 /* 60572 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
22057 /* 60577 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22058 /* 60580 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22059 /* 60583 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22060 /* 60586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22061 /* 60590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22062 /* 60594 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22063 /* 60598 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4048:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINs32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
22064 /* 60598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINs32),
22065 /* 60601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22066 /* 60603 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22067 /* 60605 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22068 /* 60607 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22069 /* 60610 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22070 /* 60616 */ GIR_RootConstrainSelectedInstOperands,
22071 /* 60617 */ // GIR_Coverage, 1437,
22072 /* 60617 */ GIR_EraseRootFromParent_Done,
22073 /* 60618 */ // Label 1313: @60618
22074 /* 60618 */ GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(60672), // Rule ID 1438 //
22075 /* 60623 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22076 /* 60626 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu),
22077 /* 60631 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
22078 /* 60634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22079 /* 60637 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22080 /* 60640 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22081 /* 60644 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22082 /* 60648 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22083 /* 60652 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4049:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VPMINu8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
22084 /* 60652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu8),
22085 /* 60655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22086 /* 60657 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22087 /* 60659 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22088 /* 60661 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22089 /* 60664 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22090 /* 60670 */ GIR_RootConstrainSelectedInstOperands,
22091 /* 60671 */ // GIR_Coverage, 1438,
22092 /* 60671 */ GIR_EraseRootFromParent_Done,
22093 /* 60672 */ // Label 1314: @60672
22094 /* 60672 */ GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(60726), // Rule ID 1439 //
22095 /* 60677 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22096 /* 60680 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu),
22097 /* 60685 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22098 /* 60688 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22099 /* 60691 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22100 /* 60694 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22101 /* 60698 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22102 /* 60702 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22103 /* 60706 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4049:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VPMINu16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
22104 /* 60706 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu16),
22105 /* 60709 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22106 /* 60711 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22107 /* 60713 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22108 /* 60715 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22109 /* 60718 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22110 /* 60724 */ GIR_RootConstrainSelectedInstOperands,
22111 /* 60725 */ // GIR_Coverage, 1439,
22112 /* 60725 */ GIR_EraseRootFromParent_Done,
22113 /* 60726 */ // Label 1315: @60726
22114 /* 60726 */ GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(60780), // Rule ID 1440 //
22115 /* 60731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22116 /* 60734 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpminu),
22117 /* 60739 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22118 /* 60742 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22119 /* 60745 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22120 /* 60748 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22121 /* 60752 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22122 /* 60756 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22123 /* 60760 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4049:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VPMINu32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
22124 /* 60760 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINu32),
22125 /* 60763 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22126 /* 60765 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22127 /* 60767 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22128 /* 60769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22129 /* 60772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22130 /* 60778 */ GIR_RootConstrainSelectedInstOperands,
22131 /* 60779 */ // GIR_Coverage, 1440,
22132 /* 60779 */ GIR_EraseRootFromParent_Done,
22133 /* 60780 */ // Label 1316: @60780
22134 /* 60780 */ GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(60834), // Rule ID 1441 //
22135 /* 60785 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22136 /* 60788 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
22137 /* 60793 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22138 /* 60796 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22139 /* 60799 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22140 /* 60802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22141 /* 60806 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22142 /* 60810 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22143 /* 60814 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4048:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VPMINf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
22144 /* 60814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINf),
22145 /* 60817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22146 /* 60819 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22147 /* 60821 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22148 /* 60823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22149 /* 60826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22150 /* 60832 */ GIR_RootConstrainSelectedInstOperands,
22151 /* 60833 */ // GIR_Coverage, 1441,
22152 /* 60833 */ GIR_EraseRootFromParent_Done,
22153 /* 60834 */ // Label 1317: @60834
22154 /* 60834 */ GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(60888), // Rule ID 1442 //
22155 /* 60839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
22156 /* 60842 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vpmins),
22157 /* 60847 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22158 /* 60850 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22159 /* 60853 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22160 /* 60856 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22161 /* 60860 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22162 /* 60864 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22163 /* 60868 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4048:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VPMINh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
22164 /* 60868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VPMINh),
22165 /* 60871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22166 /* 60873 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22167 /* 60875 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22168 /* 60877 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22169 /* 60880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22170 /* 60886 */ GIR_RootConstrainSelectedInstOperands,
22171 /* 60887 */ // GIR_Coverage, 1442,
22172 /* 60887 */ GIR_EraseRootFromParent_Done,
22173 /* 60888 */ // Label 1318: @60888
22174 /* 60888 */ GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(60942), // Rule ID 1449 //
22175 /* 60893 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22176 /* 60896 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps),
22177 /* 60901 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22178 /* 60904 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22179 /* 60907 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22180 /* 60910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22181 /* 60914 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22182 /* 60918 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22183 /* 60922 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4073:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRECPSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
22184 /* 60922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfd),
22185 /* 60925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22186 /* 60927 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22187 /* 60929 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22188 /* 60931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22189 /* 60934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22190 /* 60940 */ GIR_RootConstrainSelectedInstOperands,
22191 /* 60941 */ // GIR_Coverage, 1449,
22192 /* 60941 */ GIR_EraseRootFromParent_Done,
22193 /* 60942 */ // Label 1319: @60942
22194 /* 60942 */ GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(60996), // Rule ID 1450 //
22195 /* 60947 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22196 /* 60950 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps),
22197 /* 60955 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22198 /* 60958 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22199 /* 60961 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22200 /* 60964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22201 /* 60968 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22202 /* 60972 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22203 /* 60976 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4073:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRECPSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
22204 /* 60976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPSfq),
22205 /* 60979 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22206 /* 60981 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22207 /* 60983 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22208 /* 60985 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22209 /* 60988 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22210 /* 60994 */ GIR_RootConstrainSelectedInstOperands,
22211 /* 60995 */ // GIR_Coverage, 1450,
22212 /* 60995 */ GIR_EraseRootFromParent_Done,
22213 /* 60996 */ // Label 1320: @60996
22214 /* 60996 */ GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(61050), // Rule ID 1451 //
22215 /* 61001 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
22216 /* 61004 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps),
22217 /* 61009 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22218 /* 61012 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22219 /* 61015 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22220 /* 61018 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22221 /* 61022 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22222 /* 61026 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22223 /* 61030 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4073:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRECPShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
22224 /* 61030 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShd),
22225 /* 61033 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22226 /* 61035 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22227 /* 61037 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22228 /* 61039 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22229 /* 61042 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22230 /* 61048 */ GIR_RootConstrainSelectedInstOperands,
22231 /* 61049 */ // GIR_Coverage, 1451,
22232 /* 61049 */ GIR_EraseRootFromParent_Done,
22233 /* 61050 */ // Label 1321: @61050
22234 /* 61050 */ GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(61104), // Rule ID 1452 //
22235 /* 61055 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
22236 /* 61058 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrecps),
22237 /* 61063 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22238 /* 61066 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22239 /* 61069 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22240 /* 61072 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22241 /* 61076 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22242 /* 61080 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22243 /* 61084 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4073:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRECPShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
22244 /* 61084 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRECPShq),
22245 /* 61087 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22246 /* 61089 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22247 /* 61091 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22248 /* 61093 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22249 /* 61096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22250 /* 61102 */ GIR_RootConstrainSelectedInstOperands,
22251 /* 61103 */ // GIR_Coverage, 1452,
22252 /* 61103 */ GIR_EraseRootFromParent_Done,
22253 /* 61104 */ // Label 1322: @61104
22254 /* 61104 */ GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(61158), // Rule ID 1459 //
22255 /* 61109 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22256 /* 61112 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts),
22257 /* 61117 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22258 /* 61120 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22259 /* 61123 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22260 /* 61126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22261 /* 61130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22262 /* 61134 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22263 /* 61138 */ // (intrinsic_wo_chain:{ *:[v2f32] } 4080:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VRSQRTSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
22264 /* 61138 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfd),
22265 /* 61141 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22266 /* 61143 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22267 /* 61145 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22268 /* 61147 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22269 /* 61150 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22270 /* 61156 */ GIR_RootConstrainSelectedInstOperands,
22271 /* 61157 */ // GIR_Coverage, 1459,
22272 /* 61157 */ GIR_EraseRootFromParent_Done,
22273 /* 61158 */ // Label 1323: @61158
22274 /* 61158 */ GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(61212), // Rule ID 1460 //
22275 /* 61163 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22276 /* 61166 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts),
22277 /* 61171 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22278 /* 61174 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22279 /* 61177 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22280 /* 61180 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22281 /* 61184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22282 /* 61188 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22283 /* 61192 */ // (intrinsic_wo_chain:{ *:[v4f32] } 4080:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VRSQRTSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
22284 /* 61192 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTSfq),
22285 /* 61195 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22286 /* 61197 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22287 /* 61199 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22288 /* 61201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22289 /* 61204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22290 /* 61210 */ GIR_RootConstrainSelectedInstOperands,
22291 /* 61211 */ // GIR_Coverage, 1460,
22292 /* 61211 */ GIR_EraseRootFromParent_Done,
22293 /* 61212 */ // Label 1324: @61212
22294 /* 61212 */ GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(61266), // Rule ID 1461 //
22295 /* 61217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
22296 /* 61220 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts),
22297 /* 61225 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22298 /* 61228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22299 /* 61231 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22300 /* 61234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22301 /* 61238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22302 /* 61242 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22303 /* 61246 */ // (intrinsic_wo_chain:{ *:[v4f16] } 4080:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VRSQRTShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
22304 /* 61246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShd),
22305 /* 61249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22306 /* 61251 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22307 /* 61253 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22308 /* 61255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22309 /* 61258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22310 /* 61264 */ GIR_RootConstrainSelectedInstOperands,
22311 /* 61265 */ // GIR_Coverage, 1461,
22312 /* 61265 */ GIR_EraseRootFromParent_Done,
22313 /* 61266 */ // Label 1325: @61266
22314 /* 61266 */ GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(61320), // Rule ID 1462 //
22315 /* 61271 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
22316 /* 61274 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrsqrts),
22317 /* 61279 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22318 /* 61282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22319 /* 61285 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22320 /* 61288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22321 /* 61292 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22322 /* 61296 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22323 /* 61300 */ // (intrinsic_wo_chain:{ *:[v8f16] } 4080:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VRSQRTShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
22324 /* 61300 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSQRTShq),
22325 /* 61303 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22326 /* 61305 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vn
22327 /* 61307 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
22328 /* 61309 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22329 /* 61312 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22330 /* 61318 */ GIR_RootConstrainSelectedInstOperands,
22331 /* 61319 */ // GIR_Coverage, 1462,
22332 /* 61319 */ GIR_EraseRootFromParent_Done,
22333 /* 61320 */ // Label 1326: @61320
22334 /* 61320 */ GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(61374), // Rule ID 1463 //
22335 /* 61325 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22336 /* 61328 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22337 /* 61333 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22338 /* 61336 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22339 /* 61339 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22340 /* 61342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22341 /* 61346 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22342 /* 61350 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22343 /* 61354 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4083:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22344 /* 61354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i16),
22345 /* 61357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22346 /* 61359 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22347 /* 61361 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22348 /* 61363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22349 /* 61366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22350 /* 61372 */ GIR_RootConstrainSelectedInstOperands,
22351 /* 61373 */ // GIR_Coverage, 1463,
22352 /* 61373 */ GIR_EraseRootFromParent_Done,
22353 /* 61374 */ // Label 1327: @61374
22354 /* 61374 */ GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(61428), // Rule ID 1464 //
22355 /* 61379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22356 /* 61382 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22357 /* 61387 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22358 /* 61390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22359 /* 61393 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22360 /* 61396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22361 /* 61400 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22362 /* 61404 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22363 /* 61408 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4083:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22364 /* 61408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i32),
22365 /* 61411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22366 /* 61413 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22367 /* 61415 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22368 /* 61417 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22369 /* 61420 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22370 /* 61426 */ GIR_RootConstrainSelectedInstOperands,
22371 /* 61427 */ // GIR_Coverage, 1464,
22372 /* 61427 */ GIR_EraseRootFromParent_Done,
22373 /* 61428 */ // Label 1328: @61428
22374 /* 61428 */ GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(61482), // Rule ID 1465 //
22375 /* 61433 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22376 /* 61436 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22377 /* 61441 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22378 /* 61444 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22379 /* 61447 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22380 /* 61450 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22381 /* 61454 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22382 /* 61458 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22383 /* 61462 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4083:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22384 /* 61462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i16),
22385 /* 61465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22386 /* 61467 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22387 /* 61469 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22388 /* 61471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22389 /* 61474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22390 /* 61480 */ GIR_RootConstrainSelectedInstOperands,
22391 /* 61481 */ // GIR_Coverage, 1465,
22392 /* 61481 */ GIR_EraseRootFromParent_Done,
22393 /* 61482 */ // Label 1329: @61482
22394 /* 61482 */ GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(61536), // Rule ID 1466 //
22395 /* 61487 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22396 /* 61490 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22397 /* 61495 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22398 /* 61498 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22399 /* 61501 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22400 /* 61504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22401 /* 61508 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22402 /* 61512 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22403 /* 61516 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4083:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22404 /* 61516 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv4i32),
22405 /* 61519 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22406 /* 61521 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22407 /* 61523 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22408 /* 61525 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22409 /* 61528 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22410 /* 61534 */ GIR_RootConstrainSelectedInstOperands,
22411 /* 61535 */ // GIR_Coverage, 1466,
22412 /* 61535 */ GIR_EraseRootFromParent_Done,
22413 /* 61536 */ // Label 1330: @61536
22414 /* 61536 */ GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(61590), // Rule ID 1467 //
22415 /* 61541 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22416 /* 61544 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22417 /* 61549 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
22418 /* 61552 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22419 /* 61555 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22420 /* 61558 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22421 /* 61562 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22422 /* 61566 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22423 /* 61570 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4083:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22424 /* 61570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv8i8),
22425 /* 61573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22426 /* 61575 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22427 /* 61577 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22428 /* 61579 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22429 /* 61582 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22430 /* 61588 */ GIR_RootConstrainSelectedInstOperands,
22431 /* 61589 */ // GIR_Coverage, 1467,
22432 /* 61589 */ GIR_EraseRootFromParent_Done,
22433 /* 61590 */ // Label 1331: @61590
22434 /* 61590 */ GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(61644), // Rule ID 1468 //
22435 /* 61595 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22436 /* 61598 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22437 /* 61603 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22438 /* 61606 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22439 /* 61609 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22440 /* 61612 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22441 /* 61616 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22442 /* 61620 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22443 /* 61624 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4083:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22444 /* 61624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv16i8),
22445 /* 61627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22446 /* 61629 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22447 /* 61631 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22448 /* 61633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22449 /* 61636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22450 /* 61642 */ GIR_RootConstrainSelectedInstOperands,
22451 /* 61643 */ // GIR_Coverage, 1468,
22452 /* 61643 */ GIR_EraseRootFromParent_Done,
22453 /* 61644 */ // Label 1332: @61644
22454 /* 61644 */ GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(61698), // Rule ID 1469 //
22455 /* 61649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22456 /* 61652 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22457 /* 61657 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22458 /* 61660 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22459 /* 61663 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22460 /* 61666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22461 /* 61670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22462 /* 61674 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22463 /* 61678 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4083:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22464 /* 61678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv1i64),
22465 /* 61681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22466 /* 61683 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22467 /* 61685 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22468 /* 61687 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22469 /* 61690 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22470 /* 61696 */ GIR_RootConstrainSelectedInstOperands,
22471 /* 61697 */ // GIR_Coverage, 1469,
22472 /* 61697 */ GIR_EraseRootFromParent_Done,
22473 /* 61698 */ // Label 1333: @61698
22474 /* 61698 */ GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(61752), // Rule ID 1470 //
22475 /* 61703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22476 /* 61706 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshifts),
22477 /* 61711 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
22478 /* 61714 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22479 /* 61717 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22480 /* 61720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22481 /* 61724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22482 /* 61728 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22483 /* 61732 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4083:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22484 /* 61732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLsv2i64),
22485 /* 61735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22486 /* 61737 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22487 /* 61739 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22488 /* 61741 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22489 /* 61744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22490 /* 61750 */ GIR_RootConstrainSelectedInstOperands,
22491 /* 61751 */ // GIR_Coverage, 1470,
22492 /* 61751 */ GIR_EraseRootFromParent_Done,
22493 /* 61752 */ // Label 1334: @61752
22494 /* 61752 */ GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(61806), // Rule ID 1471 //
22495 /* 61757 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22496 /* 61760 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22497 /* 61765 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22498 /* 61768 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22499 /* 61771 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22500 /* 61774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22501 /* 61778 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22502 /* 61782 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22503 /* 61786 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4084:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22504 /* 61786 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i16),
22505 /* 61789 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22506 /* 61791 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22507 /* 61793 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22508 /* 61795 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22509 /* 61798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22510 /* 61804 */ GIR_RootConstrainSelectedInstOperands,
22511 /* 61805 */ // GIR_Coverage, 1471,
22512 /* 61805 */ GIR_EraseRootFromParent_Done,
22513 /* 61806 */ // Label 1335: @61806
22514 /* 61806 */ GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(61860), // Rule ID 1472 //
22515 /* 61811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22516 /* 61814 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22517 /* 61819 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22518 /* 61822 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22519 /* 61825 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22520 /* 61828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22521 /* 61832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22522 /* 61836 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22523 /* 61840 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4084:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22524 /* 61840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i32),
22525 /* 61843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22526 /* 61845 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22527 /* 61847 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22528 /* 61849 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22529 /* 61852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22530 /* 61858 */ GIR_RootConstrainSelectedInstOperands,
22531 /* 61859 */ // GIR_Coverage, 1472,
22532 /* 61859 */ GIR_EraseRootFromParent_Done,
22533 /* 61860 */ // Label 1336: @61860
22534 /* 61860 */ GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(61914), // Rule ID 1473 //
22535 /* 61865 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22536 /* 61868 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22537 /* 61873 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22538 /* 61876 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22539 /* 61879 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22540 /* 61882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22541 /* 61886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22542 /* 61890 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22543 /* 61894 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4084:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22544 /* 61894 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i16),
22545 /* 61897 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22546 /* 61899 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22547 /* 61901 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22548 /* 61903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22549 /* 61906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22550 /* 61912 */ GIR_RootConstrainSelectedInstOperands,
22551 /* 61913 */ // GIR_Coverage, 1473,
22552 /* 61913 */ GIR_EraseRootFromParent_Done,
22553 /* 61914 */ // Label 1337: @61914
22554 /* 61914 */ GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(61968), // Rule ID 1474 //
22555 /* 61919 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22556 /* 61922 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22557 /* 61927 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22558 /* 61930 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22559 /* 61933 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22560 /* 61936 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22561 /* 61940 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22562 /* 61944 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22563 /* 61948 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4084:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22564 /* 61948 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv4i32),
22565 /* 61951 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22566 /* 61953 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22567 /* 61955 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22568 /* 61957 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22569 /* 61960 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22570 /* 61966 */ GIR_RootConstrainSelectedInstOperands,
22571 /* 61967 */ // GIR_Coverage, 1474,
22572 /* 61967 */ GIR_EraseRootFromParent_Done,
22573 /* 61968 */ // Label 1338: @61968
22574 /* 61968 */ GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(62022), // Rule ID 1475 //
22575 /* 61973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22576 /* 61976 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22577 /* 61981 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
22578 /* 61984 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22579 /* 61987 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22580 /* 61990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22581 /* 61994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22582 /* 61998 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22583 /* 62002 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4084:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22584 /* 62002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv8i8),
22585 /* 62005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22586 /* 62007 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22587 /* 62009 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22588 /* 62011 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22589 /* 62014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22590 /* 62020 */ GIR_RootConstrainSelectedInstOperands,
22591 /* 62021 */ // GIR_Coverage, 1475,
22592 /* 62021 */ GIR_EraseRootFromParent_Done,
22593 /* 62022 */ // Label 1339: @62022
22594 /* 62022 */ GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(62076), // Rule ID 1476 //
22595 /* 62027 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22596 /* 62030 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22597 /* 62035 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22598 /* 62038 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22599 /* 62041 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22600 /* 62044 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22601 /* 62048 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22602 /* 62052 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22603 /* 62056 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4084:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22604 /* 62056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv16i8),
22605 /* 62059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22606 /* 62061 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22607 /* 62063 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22608 /* 62065 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22609 /* 62068 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22610 /* 62074 */ GIR_RootConstrainSelectedInstOperands,
22611 /* 62075 */ // GIR_Coverage, 1476,
22612 /* 62075 */ GIR_EraseRootFromParent_Done,
22613 /* 62076 */ // Label 1340: @62076
22614 /* 62076 */ GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(62130), // Rule ID 1477 //
22615 /* 62081 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22616 /* 62084 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22617 /* 62089 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22618 /* 62092 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22619 /* 62095 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22620 /* 62098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22621 /* 62102 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22622 /* 62106 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22623 /* 62110 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4084:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22624 /* 62110 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv1i64),
22625 /* 62113 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22626 /* 62115 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22627 /* 62117 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22628 /* 62119 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22629 /* 62122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22630 /* 62128 */ GIR_RootConstrainSelectedInstOperands,
22631 /* 62129 */ // GIR_Coverage, 1477,
22632 /* 62129 */ GIR_EraseRootFromParent_Done,
22633 /* 62130 */ // Label 1341: @62130
22634 /* 62130 */ GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(62184), // Rule ID 1478 //
22635 /* 62135 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22636 /* 62138 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vshiftu),
22637 /* 62143 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
22638 /* 62146 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22639 /* 62149 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22640 /* 62152 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22641 /* 62156 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22642 /* 62160 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22643 /* 62164 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4084:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22644 /* 62164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSHLuv2i64),
22645 /* 62167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22646 /* 62169 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22647 /* 62171 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22648 /* 62173 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22649 /* 62176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22650 /* 62182 */ GIR_RootConstrainSelectedInstOperands,
22651 /* 62183 */ // GIR_Coverage, 1478,
22652 /* 62183 */ GIR_EraseRootFromParent_Done,
22653 /* 62184 */ // Label 1342: @62184
22654 /* 62184 */ GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(62238), // Rule ID 1512 //
22655 /* 62189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22656 /* 62192 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22657 /* 62197 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22658 /* 62200 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22659 /* 62203 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22660 /* 62206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22661 /* 62210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22662 /* 62214 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22663 /* 62218 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4077:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22664 /* 62218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i16),
22665 /* 62221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22666 /* 62223 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22667 /* 62225 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22668 /* 62227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22669 /* 62230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22670 /* 62236 */ GIR_RootConstrainSelectedInstOperands,
22671 /* 62237 */ // GIR_Coverage, 1512,
22672 /* 62237 */ GIR_EraseRootFromParent_Done,
22673 /* 62238 */ // Label 1343: @62238
22674 /* 62238 */ GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(62292), // Rule ID 1513 //
22675 /* 62243 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22676 /* 62246 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22677 /* 62251 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22678 /* 62254 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22679 /* 62257 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22680 /* 62260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22681 /* 62264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22682 /* 62268 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22683 /* 62272 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4077:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22684 /* 62272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i32),
22685 /* 62275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22686 /* 62277 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22687 /* 62279 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22688 /* 62281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22689 /* 62284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22690 /* 62290 */ GIR_RootConstrainSelectedInstOperands,
22691 /* 62291 */ // GIR_Coverage, 1513,
22692 /* 62291 */ GIR_EraseRootFromParent_Done,
22693 /* 62292 */ // Label 1344: @62292
22694 /* 62292 */ GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(62346), // Rule ID 1514 //
22695 /* 62297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22696 /* 62300 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22697 /* 62305 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22698 /* 62308 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22699 /* 62311 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22700 /* 62314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22701 /* 62318 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22702 /* 62322 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22703 /* 62326 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4077:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22704 /* 62326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i16),
22705 /* 62329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22706 /* 62331 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22707 /* 62333 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22708 /* 62335 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22709 /* 62338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22710 /* 62344 */ GIR_RootConstrainSelectedInstOperands,
22711 /* 62345 */ // GIR_Coverage, 1514,
22712 /* 62345 */ GIR_EraseRootFromParent_Done,
22713 /* 62346 */ // Label 1345: @62346
22714 /* 62346 */ GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(62400), // Rule ID 1515 //
22715 /* 62351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22716 /* 62354 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22717 /* 62359 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22718 /* 62362 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22719 /* 62365 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22720 /* 62368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22721 /* 62372 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22722 /* 62376 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22723 /* 62380 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4077:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22724 /* 62380 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv4i32),
22725 /* 62383 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22726 /* 62385 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22727 /* 62387 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22728 /* 62389 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22729 /* 62392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22730 /* 62398 */ GIR_RootConstrainSelectedInstOperands,
22731 /* 62399 */ // GIR_Coverage, 1515,
22732 /* 62399 */ GIR_EraseRootFromParent_Done,
22733 /* 62400 */ // Label 1346: @62400
22734 /* 62400 */ GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(62454), // Rule ID 1516 //
22735 /* 62405 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22736 /* 62408 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22737 /* 62413 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
22738 /* 62416 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22739 /* 62419 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22740 /* 62422 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22741 /* 62426 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22742 /* 62430 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22743 /* 62434 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4077:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22744 /* 62434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv8i8),
22745 /* 62437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22746 /* 62439 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22747 /* 62441 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22748 /* 62443 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22749 /* 62446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22750 /* 62452 */ GIR_RootConstrainSelectedInstOperands,
22751 /* 62453 */ // GIR_Coverage, 1516,
22752 /* 62453 */ GIR_EraseRootFromParent_Done,
22753 /* 62454 */ // Label 1347: @62454
22754 /* 62454 */ GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(62508), // Rule ID 1517 //
22755 /* 62459 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22756 /* 62462 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22757 /* 62467 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22758 /* 62470 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22759 /* 62473 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22760 /* 62476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22761 /* 62480 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22762 /* 62484 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22763 /* 62488 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4077:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22764 /* 62488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv16i8),
22765 /* 62491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22766 /* 62493 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22767 /* 62495 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22768 /* 62497 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22769 /* 62500 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22770 /* 62506 */ GIR_RootConstrainSelectedInstOperands,
22771 /* 62507 */ // GIR_Coverage, 1517,
22772 /* 62507 */ GIR_EraseRootFromParent_Done,
22773 /* 62508 */ // Label 1348: @62508
22774 /* 62508 */ GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(62562), // Rule ID 1518 //
22775 /* 62513 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22776 /* 62516 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22777 /* 62521 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22778 /* 62524 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22779 /* 62527 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22780 /* 62530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22781 /* 62534 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22782 /* 62538 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22783 /* 62542 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4077:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22784 /* 62542 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv1i64),
22785 /* 62545 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22786 /* 62547 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22787 /* 62549 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22788 /* 62551 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22789 /* 62554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22790 /* 62560 */ GIR_RootConstrainSelectedInstOperands,
22791 /* 62561 */ // GIR_Coverage, 1518,
22792 /* 62561 */ GIR_EraseRootFromParent_Done,
22793 /* 62562 */ // Label 1349: @62562
22794 /* 62562 */ GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(62616), // Rule ID 1519 //
22795 /* 62567 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22796 /* 62570 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshifts),
22797 /* 62575 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
22798 /* 62578 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22799 /* 62581 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22800 /* 62584 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22801 /* 62588 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22802 /* 62592 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22803 /* 62596 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4077:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22804 /* 62596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLsv2i64),
22805 /* 62599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22806 /* 62601 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22807 /* 62603 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22808 /* 62605 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22809 /* 62608 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22810 /* 62614 */ GIR_RootConstrainSelectedInstOperands,
22811 /* 62615 */ // GIR_Coverage, 1519,
22812 /* 62615 */ GIR_EraseRootFromParent_Done,
22813 /* 62616 */ // Label 1350: @62616
22814 /* 62616 */ GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(62670), // Rule ID 1520 //
22815 /* 62621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22816 /* 62624 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22817 /* 62629 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22818 /* 62632 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22819 /* 62635 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22820 /* 62638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22821 /* 62642 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22822 /* 62646 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22823 /* 62650 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4078:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22824 /* 62650 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i16),
22825 /* 62653 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22826 /* 62655 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22827 /* 62657 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22828 /* 62659 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22829 /* 62662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22830 /* 62668 */ GIR_RootConstrainSelectedInstOperands,
22831 /* 62669 */ // GIR_Coverage, 1520,
22832 /* 62669 */ GIR_EraseRootFromParent_Done,
22833 /* 62670 */ // Label 1351: @62670
22834 /* 62670 */ GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(62724), // Rule ID 1521 //
22835 /* 62675 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22836 /* 62678 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22837 /* 62683 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22838 /* 62686 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22839 /* 62689 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
22840 /* 62692 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22841 /* 62696 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22842 /* 62700 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22843 /* 62704 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4078:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
22844 /* 62704 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i32),
22845 /* 62707 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22846 /* 62709 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22847 /* 62711 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22848 /* 62713 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22849 /* 62716 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22850 /* 62722 */ GIR_RootConstrainSelectedInstOperands,
22851 /* 62723 */ // GIR_Coverage, 1521,
22852 /* 62723 */ GIR_EraseRootFromParent_Done,
22853 /* 62724 */ // Label 1352: @62724
22854 /* 62724 */ GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(62778), // Rule ID 1522 //
22855 /* 62729 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22856 /* 62732 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22857 /* 62737 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
22858 /* 62740 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
22859 /* 62743 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
22860 /* 62746 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22861 /* 62750 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22862 /* 62754 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22863 /* 62758 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4078:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
22864 /* 62758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i16),
22865 /* 62761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22866 /* 62763 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22867 /* 62765 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22868 /* 62767 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22869 /* 62770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22870 /* 62776 */ GIR_RootConstrainSelectedInstOperands,
22871 /* 62777 */ // GIR_Coverage, 1522,
22872 /* 62777 */ GIR_EraseRootFromParent_Done,
22873 /* 62778 */ // Label 1353: @62778
22874 /* 62778 */ GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(62832), // Rule ID 1523 //
22875 /* 62783 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22876 /* 62786 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22877 /* 62791 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
22878 /* 62794 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
22879 /* 62797 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
22880 /* 62800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22881 /* 62804 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22882 /* 62808 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22883 /* 62812 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4078:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
22884 /* 62812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv4i32),
22885 /* 62815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22886 /* 62817 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22887 /* 62819 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22888 /* 62821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22889 /* 62824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22890 /* 62830 */ GIR_RootConstrainSelectedInstOperands,
22891 /* 62831 */ // GIR_Coverage, 1523,
22892 /* 62831 */ GIR_EraseRootFromParent_Done,
22893 /* 62832 */ // Label 1354: @62832
22894 /* 62832 */ GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(62886), // Rule ID 1524 //
22895 /* 62837 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22896 /* 62840 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22897 /* 62845 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
22898 /* 62848 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
22899 /* 62851 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
22900 /* 62854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22901 /* 62858 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22902 /* 62862 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22903 /* 62866 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4078:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
22904 /* 62866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv8i8),
22905 /* 62869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22906 /* 62871 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22907 /* 62873 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22908 /* 62875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22909 /* 62878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22910 /* 62884 */ GIR_RootConstrainSelectedInstOperands,
22911 /* 62885 */ // GIR_Coverage, 1524,
22912 /* 62885 */ GIR_EraseRootFromParent_Done,
22913 /* 62886 */ // Label 1355: @62886
22914 /* 62886 */ GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(62940), // Rule ID 1525 //
22915 /* 62891 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22916 /* 62894 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22917 /* 62899 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
22918 /* 62902 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
22919 /* 62905 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
22920 /* 62908 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22921 /* 62912 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22922 /* 62916 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22923 /* 62920 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4078:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
22924 /* 62920 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv16i8),
22925 /* 62923 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22926 /* 62925 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22927 /* 62927 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22928 /* 62929 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22929 /* 62932 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22930 /* 62938 */ GIR_RootConstrainSelectedInstOperands,
22931 /* 62939 */ // GIR_Coverage, 1525,
22932 /* 62939 */ GIR_EraseRootFromParent_Done,
22933 /* 62940 */ // Label 1356: @62940
22934 /* 62940 */ GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(62994), // Rule ID 1526 //
22935 /* 62945 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22936 /* 62948 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22937 /* 62953 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
22938 /* 62956 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
22939 /* 62959 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
22940 /* 62962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22941 /* 62966 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22942 /* 62970 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22943 /* 62974 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4078:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
22944 /* 62974 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv1i64),
22945 /* 62977 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22946 /* 62979 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22947 /* 62981 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22948 /* 62983 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22949 /* 62986 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22950 /* 62992 */ GIR_RootConstrainSelectedInstOperands,
22951 /* 62993 */ // GIR_Coverage, 1526,
22952 /* 62993 */ GIR_EraseRootFromParent_Done,
22953 /* 62994 */ // Label 1357: @62994
22954 /* 62994 */ GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(63048), // Rule ID 1527 //
22955 /* 62999 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22956 /* 63002 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vrshiftu),
22957 /* 63007 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
22958 /* 63010 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
22959 /* 63013 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
22960 /* 63016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22961 /* 63020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22962 /* 63024 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
22963 /* 63028 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4078:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
22964 /* 63028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRSHLuv2i64),
22965 /* 63031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22966 /* 63033 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22967 /* 63035 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22968 /* 63037 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22969 /* 63040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22970 /* 63046 */ GIR_RootConstrainSelectedInstOperands,
22971 /* 63047 */ // GIR_Coverage, 1527,
22972 /* 63047 */ GIR_EraseRootFromParent_Done,
22973 /* 63048 */ // Label 1358: @63048
22974 /* 63048 */ GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(63102), // Rule ID 1547 //
22975 /* 63053 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22976 /* 63056 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22977 /* 63061 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
22978 /* 63064 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
22979 /* 63067 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
22980 /* 63070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22981 /* 63074 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22982 /* 63078 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
22983 /* 63082 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4068:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
22984 /* 63082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i16),
22985 /* 63085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
22986 /* 63087 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
22987 /* 63089 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
22988 /* 63091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
22989 /* 63094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
22990 /* 63100 */ GIR_RootConstrainSelectedInstOperands,
22991 /* 63101 */ // GIR_Coverage, 1547,
22992 /* 63101 */ GIR_EraseRootFromParent_Done,
22993 /* 63102 */ // Label 1359: @63102
22994 /* 63102 */ GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(63156), // Rule ID 1548 //
22995 /* 63107 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
22996 /* 63110 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
22997 /* 63115 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
22998 /* 63118 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
22999 /* 63121 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
23000 /* 63124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23001 /* 63128 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23002 /* 63132 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23003 /* 63136 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4068:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
23004 /* 63136 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i32),
23005 /* 63139 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23006 /* 63141 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23007 /* 63143 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23008 /* 63145 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23009 /* 63148 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23010 /* 63154 */ GIR_RootConstrainSelectedInstOperands,
23011 /* 63155 */ // GIR_Coverage, 1548,
23012 /* 63155 */ GIR_EraseRootFromParent_Done,
23013 /* 63156 */ // Label 1360: @63156
23014 /* 63156 */ GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(63210), // Rule ID 1549 //
23015 /* 63161 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23016 /* 63164 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
23017 /* 63169 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23018 /* 63172 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23019 /* 63175 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23020 /* 63178 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23021 /* 63182 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23022 /* 63186 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23023 /* 63190 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4068:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
23024 /* 63190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i16),
23025 /* 63193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23026 /* 63195 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23027 /* 63197 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23028 /* 63199 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23029 /* 63202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23030 /* 63208 */ GIR_RootConstrainSelectedInstOperands,
23031 /* 63209 */ // GIR_Coverage, 1549,
23032 /* 63209 */ GIR_EraseRootFromParent_Done,
23033 /* 63210 */ // Label 1361: @63210
23034 /* 63210 */ GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(63264), // Rule ID 1550 //
23035 /* 63215 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23036 /* 63218 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
23037 /* 63223 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23038 /* 63226 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23039 /* 63229 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23040 /* 63232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23041 /* 63236 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23042 /* 63240 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23043 /* 63244 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4068:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
23044 /* 63244 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv4i32),
23045 /* 63247 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23046 /* 63249 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23047 /* 63251 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23048 /* 63253 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23049 /* 63256 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23050 /* 63262 */ GIR_RootConstrainSelectedInstOperands,
23051 /* 63263 */ // GIR_Coverage, 1550,
23052 /* 63263 */ GIR_EraseRootFromParent_Done,
23053 /* 63264 */ // Label 1362: @63264
23054 /* 63264 */ GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(63318), // Rule ID 1551 //
23055 /* 63269 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23056 /* 63272 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
23057 /* 63277 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
23058 /* 63280 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
23059 /* 63283 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
23060 /* 63286 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23061 /* 63290 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23062 /* 63294 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23063 /* 63298 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4068:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
23064 /* 63298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv8i8),
23065 /* 63301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23066 /* 63303 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23067 /* 63305 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23068 /* 63307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23069 /* 63310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23070 /* 63316 */ GIR_RootConstrainSelectedInstOperands,
23071 /* 63317 */ // GIR_Coverage, 1551,
23072 /* 63317 */ GIR_EraseRootFromParent_Done,
23073 /* 63318 */ // Label 1363: @63318
23074 /* 63318 */ GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(63372), // Rule ID 1552 //
23075 /* 63323 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23076 /* 63326 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
23077 /* 63331 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23078 /* 63334 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23079 /* 63337 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23080 /* 63340 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23081 /* 63344 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23082 /* 63348 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23083 /* 63352 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4068:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
23084 /* 63352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv16i8),
23085 /* 63355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23086 /* 63357 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23087 /* 63359 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23088 /* 63361 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23089 /* 63364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23090 /* 63370 */ GIR_RootConstrainSelectedInstOperands,
23091 /* 63371 */ // GIR_Coverage, 1552,
23092 /* 63371 */ GIR_EraseRootFromParent_Done,
23093 /* 63372 */ // Label 1364: @63372
23094 /* 63372 */ GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(63426), // Rule ID 1553 //
23095 /* 63377 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23096 /* 63380 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
23097 /* 63385 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
23098 /* 63388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23099 /* 63391 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23100 /* 63394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23101 /* 63398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23102 /* 63402 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23103 /* 63406 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4068:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
23104 /* 63406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv1i64),
23105 /* 63409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23106 /* 63411 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23107 /* 63413 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23108 /* 63415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23109 /* 63418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23110 /* 63424 */ GIR_RootConstrainSelectedInstOperands,
23111 /* 63425 */ // GIR_Coverage, 1553,
23112 /* 63425 */ GIR_EraseRootFromParent_Done,
23113 /* 63426 */ // Label 1365: @63426
23114 /* 63426 */ GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(63480), // Rule ID 1554 //
23115 /* 63431 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23116 /* 63434 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshifts),
23117 /* 63439 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23118 /* 63442 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23119 /* 63445 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23120 /* 63448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23121 /* 63452 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23122 /* 63456 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23123 /* 63460 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4068:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
23124 /* 63460 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLsv2i64),
23125 /* 63463 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23126 /* 63465 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23127 /* 63467 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23128 /* 63469 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23129 /* 63472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23130 /* 63478 */ GIR_RootConstrainSelectedInstOperands,
23131 /* 63479 */ // GIR_Coverage, 1554,
23132 /* 63479 */ GIR_EraseRootFromParent_Done,
23133 /* 63480 */ // Label 1366: @63480
23134 /* 63480 */ GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(63534), // Rule ID 1555 //
23135 /* 63485 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23136 /* 63488 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
23137 /* 63493 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
23138 /* 63496 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
23139 /* 63499 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
23140 /* 63502 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23141 /* 63506 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23142 /* 63510 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23143 /* 63514 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4070:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
23144 /* 63514 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i16),
23145 /* 63517 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23146 /* 63519 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23147 /* 63521 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23148 /* 63523 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23149 /* 63526 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23150 /* 63532 */ GIR_RootConstrainSelectedInstOperands,
23151 /* 63533 */ // GIR_Coverage, 1555,
23152 /* 63533 */ GIR_EraseRootFromParent_Done,
23153 /* 63534 */ // Label 1367: @63534
23154 /* 63534 */ GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(63588), // Rule ID 1556 //
23155 /* 63539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23156 /* 63542 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
23157 /* 63547 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
23158 /* 63550 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
23159 /* 63553 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
23160 /* 63556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23161 /* 63560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23162 /* 63564 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23163 /* 63568 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4070:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
23164 /* 63568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i32),
23165 /* 63571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23166 /* 63573 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23167 /* 63575 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23168 /* 63577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23169 /* 63580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23170 /* 63586 */ GIR_RootConstrainSelectedInstOperands,
23171 /* 63587 */ // GIR_Coverage, 1556,
23172 /* 63587 */ GIR_EraseRootFromParent_Done,
23173 /* 63588 */ // Label 1368: @63588
23174 /* 63588 */ GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(63642), // Rule ID 1557 //
23175 /* 63593 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23176 /* 63596 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
23177 /* 63601 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23178 /* 63604 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23179 /* 63607 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23180 /* 63610 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23181 /* 63614 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23182 /* 63618 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23183 /* 63622 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4070:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
23184 /* 63622 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i16),
23185 /* 63625 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23186 /* 63627 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23187 /* 63629 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23188 /* 63631 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23189 /* 63634 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23190 /* 63640 */ GIR_RootConstrainSelectedInstOperands,
23191 /* 63641 */ // GIR_Coverage, 1557,
23192 /* 63641 */ GIR_EraseRootFromParent_Done,
23193 /* 63642 */ // Label 1369: @63642
23194 /* 63642 */ GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(63696), // Rule ID 1558 //
23195 /* 63647 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23196 /* 63650 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
23197 /* 63655 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23198 /* 63658 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23199 /* 63661 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23200 /* 63664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23201 /* 63668 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23202 /* 63672 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23203 /* 63676 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4070:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
23204 /* 63676 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv4i32),
23205 /* 63679 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23206 /* 63681 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23207 /* 63683 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23208 /* 63685 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23209 /* 63688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23210 /* 63694 */ GIR_RootConstrainSelectedInstOperands,
23211 /* 63695 */ // GIR_Coverage, 1558,
23212 /* 63695 */ GIR_EraseRootFromParent_Done,
23213 /* 63696 */ // Label 1370: @63696
23214 /* 63696 */ GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(63750), // Rule ID 1559 //
23215 /* 63701 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23216 /* 63704 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
23217 /* 63709 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
23218 /* 63712 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
23219 /* 63715 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
23220 /* 63718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23221 /* 63722 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23222 /* 63726 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23223 /* 63730 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4070:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
23224 /* 63730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv8i8),
23225 /* 63733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23226 /* 63735 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23227 /* 63737 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23228 /* 63739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23229 /* 63742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23230 /* 63748 */ GIR_RootConstrainSelectedInstOperands,
23231 /* 63749 */ // GIR_Coverage, 1559,
23232 /* 63749 */ GIR_EraseRootFromParent_Done,
23233 /* 63750 */ // Label 1371: @63750
23234 /* 63750 */ GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(63804), // Rule ID 1560 //
23235 /* 63755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23236 /* 63758 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
23237 /* 63763 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23238 /* 63766 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23239 /* 63769 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23240 /* 63772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23241 /* 63776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23242 /* 63780 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23243 /* 63784 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4070:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
23244 /* 63784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv16i8),
23245 /* 63787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23246 /* 63789 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23247 /* 63791 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23248 /* 63793 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23249 /* 63796 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23250 /* 63802 */ GIR_RootConstrainSelectedInstOperands,
23251 /* 63803 */ // GIR_Coverage, 1560,
23252 /* 63803 */ GIR_EraseRootFromParent_Done,
23253 /* 63804 */ // Label 1372: @63804
23254 /* 63804 */ GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(63858), // Rule ID 1561 //
23255 /* 63809 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23256 /* 63812 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
23257 /* 63817 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
23258 /* 63820 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23259 /* 63823 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23260 /* 63826 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23261 /* 63830 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23262 /* 63834 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23263 /* 63838 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4070:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
23264 /* 63838 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv1i64),
23265 /* 63841 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23266 /* 63843 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23267 /* 63845 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23268 /* 63847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23269 /* 63850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23270 /* 63856 */ GIR_RootConstrainSelectedInstOperands,
23271 /* 63857 */ // GIR_Coverage, 1561,
23272 /* 63857 */ GIR_EraseRootFromParent_Done,
23273 /* 63858 */ // Label 1373: @63858
23274 /* 63858 */ GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(63912), // Rule ID 1562 //
23275 /* 63863 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23276 /* 63866 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqshiftu),
23277 /* 63871 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23278 /* 63874 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23279 /* 63877 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23280 /* 63880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23281 /* 63884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23282 /* 63888 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23283 /* 63892 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4070:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
23284 /* 63892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSHLuv2i64),
23285 /* 63895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23286 /* 63897 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23287 /* 63899 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23288 /* 63901 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23289 /* 63904 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23290 /* 63910 */ GIR_RootConstrainSelectedInstOperands,
23291 /* 63911 */ // GIR_Coverage, 1562,
23292 /* 63911 */ GIR_EraseRootFromParent_Done,
23293 /* 63912 */ // Label 1374: @63912
23294 /* 63912 */ GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(63966), // Rule ID 1596 //
23295 /* 63917 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23296 /* 63920 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23297 /* 63925 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
23298 /* 63928 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
23299 /* 63931 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
23300 /* 63934 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23301 /* 63938 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23302 /* 63942 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23303 /* 63946 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4063:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
23304 /* 63946 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i16),
23305 /* 63949 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23306 /* 63951 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23307 /* 63953 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23308 /* 63955 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23309 /* 63958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23310 /* 63964 */ GIR_RootConstrainSelectedInstOperands,
23311 /* 63965 */ // GIR_Coverage, 1596,
23312 /* 63965 */ GIR_EraseRootFromParent_Done,
23313 /* 63966 */ // Label 1375: @63966
23314 /* 63966 */ GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(64020), // Rule ID 1597 //
23315 /* 63971 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23316 /* 63974 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23317 /* 63979 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
23318 /* 63982 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
23319 /* 63985 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
23320 /* 63988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23321 /* 63992 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23322 /* 63996 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23323 /* 64000 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4063:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
23324 /* 64000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i32),
23325 /* 64003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23326 /* 64005 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23327 /* 64007 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23328 /* 64009 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23329 /* 64012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23330 /* 64018 */ GIR_RootConstrainSelectedInstOperands,
23331 /* 64019 */ // GIR_Coverage, 1597,
23332 /* 64019 */ GIR_EraseRootFromParent_Done,
23333 /* 64020 */ // Label 1376: @64020
23334 /* 64020 */ GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(64074), // Rule ID 1598 //
23335 /* 64025 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23336 /* 64028 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23337 /* 64033 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23338 /* 64036 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23339 /* 64039 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23340 /* 64042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23341 /* 64046 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23342 /* 64050 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23343 /* 64054 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4063:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
23344 /* 64054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i16),
23345 /* 64057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23346 /* 64059 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23347 /* 64061 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23348 /* 64063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23349 /* 64066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23350 /* 64072 */ GIR_RootConstrainSelectedInstOperands,
23351 /* 64073 */ // GIR_Coverage, 1598,
23352 /* 64073 */ GIR_EraseRootFromParent_Done,
23353 /* 64074 */ // Label 1377: @64074
23354 /* 64074 */ GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(64128), // Rule ID 1599 //
23355 /* 64079 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23356 /* 64082 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23357 /* 64087 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23358 /* 64090 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23359 /* 64093 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23360 /* 64096 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23361 /* 64100 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23362 /* 64104 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23363 /* 64108 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4063:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
23364 /* 64108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv4i32),
23365 /* 64111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23366 /* 64113 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23367 /* 64115 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23368 /* 64117 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23369 /* 64120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23370 /* 64126 */ GIR_RootConstrainSelectedInstOperands,
23371 /* 64127 */ // GIR_Coverage, 1599,
23372 /* 64127 */ GIR_EraseRootFromParent_Done,
23373 /* 64128 */ // Label 1378: @64128
23374 /* 64128 */ GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(64182), // Rule ID 1600 //
23375 /* 64133 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23376 /* 64136 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23377 /* 64141 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
23378 /* 64144 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
23379 /* 64147 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
23380 /* 64150 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23381 /* 64154 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23382 /* 64158 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23383 /* 64162 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4063:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
23384 /* 64162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv8i8),
23385 /* 64165 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23386 /* 64167 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23387 /* 64169 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23388 /* 64171 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23389 /* 64174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23390 /* 64180 */ GIR_RootConstrainSelectedInstOperands,
23391 /* 64181 */ // GIR_Coverage, 1600,
23392 /* 64181 */ GIR_EraseRootFromParent_Done,
23393 /* 64182 */ // Label 1379: @64182
23394 /* 64182 */ GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(64236), // Rule ID 1601 //
23395 /* 64187 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23396 /* 64190 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23397 /* 64195 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23398 /* 64198 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23399 /* 64201 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23400 /* 64204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23401 /* 64208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23402 /* 64212 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23403 /* 64216 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4063:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
23404 /* 64216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv16i8),
23405 /* 64219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23406 /* 64221 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23407 /* 64223 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23408 /* 64225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23409 /* 64228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23410 /* 64234 */ GIR_RootConstrainSelectedInstOperands,
23411 /* 64235 */ // GIR_Coverage, 1601,
23412 /* 64235 */ GIR_EraseRootFromParent_Done,
23413 /* 64236 */ // Label 1380: @64236
23414 /* 64236 */ GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(64290), // Rule ID 1602 //
23415 /* 64241 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23416 /* 64244 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23417 /* 64249 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
23418 /* 64252 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23419 /* 64255 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23420 /* 64258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23421 /* 64262 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23422 /* 64266 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23423 /* 64270 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4063:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
23424 /* 64270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv1i64),
23425 /* 64273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23426 /* 64275 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23427 /* 64277 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23428 /* 64279 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23429 /* 64282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23430 /* 64288 */ GIR_RootConstrainSelectedInstOperands,
23431 /* 64289 */ // GIR_Coverage, 1602,
23432 /* 64289 */ GIR_EraseRootFromParent_Done,
23433 /* 64290 */ // Label 1381: @64290
23434 /* 64290 */ GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(64344), // Rule ID 1603 //
23435 /* 64295 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23436 /* 64298 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshifts),
23437 /* 64303 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23438 /* 64306 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23439 /* 64309 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23440 /* 64312 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23441 /* 64316 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23442 /* 64320 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23443 /* 64324 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4063:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
23444 /* 64324 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLsv2i64),
23445 /* 64327 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23446 /* 64329 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23447 /* 64331 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23448 /* 64333 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23449 /* 64336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23450 /* 64342 */ GIR_RootConstrainSelectedInstOperands,
23451 /* 64343 */ // GIR_Coverage, 1603,
23452 /* 64343 */ GIR_EraseRootFromParent_Done,
23453 /* 64344 */ // Label 1382: @64344
23454 /* 64344 */ GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(64398), // Rule ID 1604 //
23455 /* 64349 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23456 /* 64352 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23457 /* 64357 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
23458 /* 64360 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
23459 /* 64363 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
23460 /* 64366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23461 /* 64370 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23462 /* 64374 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23463 /* 64378 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4064:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn) => (VQRSHLuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm, DPR:{ *:[v4i16] }:$Vn)
23464 /* 64378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i16),
23465 /* 64381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23466 /* 64383 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23467 /* 64385 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23468 /* 64387 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23469 /* 64390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23470 /* 64396 */ GIR_RootConstrainSelectedInstOperands,
23471 /* 64397 */ // GIR_Coverage, 1604,
23472 /* 64397 */ GIR_EraseRootFromParent_Done,
23473 /* 64398 */ // Label 1383: @64398
23474 /* 64398 */ GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(64452), // Rule ID 1605 //
23475 /* 64403 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23476 /* 64406 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23477 /* 64411 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
23478 /* 64414 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
23479 /* 64417 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
23480 /* 64420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23481 /* 64424 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23482 /* 64428 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23483 /* 64432 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4064:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn) => (VQRSHLuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm, DPR:{ *:[v2i32] }:$Vn)
23484 /* 64432 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i32),
23485 /* 64435 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23486 /* 64437 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23487 /* 64439 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23488 /* 64441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23489 /* 64444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23490 /* 64450 */ GIR_RootConstrainSelectedInstOperands,
23491 /* 64451 */ // GIR_Coverage, 1605,
23492 /* 64451 */ GIR_EraseRootFromParent_Done,
23493 /* 64452 */ // Label 1384: @64452
23494 /* 64452 */ GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(64506), // Rule ID 1606 //
23495 /* 64457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23496 /* 64460 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23497 /* 64465 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
23498 /* 64468 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
23499 /* 64471 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
23500 /* 64474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23501 /* 64478 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23502 /* 64482 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23503 /* 64486 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4064:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn) => (VQRSHLuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm, QPR:{ *:[v8i16] }:$Vn)
23504 /* 64486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i16),
23505 /* 64489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23506 /* 64491 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23507 /* 64493 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23508 /* 64495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23509 /* 64498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23510 /* 64504 */ GIR_RootConstrainSelectedInstOperands,
23511 /* 64505 */ // GIR_Coverage, 1606,
23512 /* 64505 */ GIR_EraseRootFromParent_Done,
23513 /* 64506 */ // Label 1385: @64506
23514 /* 64506 */ GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(64560), // Rule ID 1607 //
23515 /* 64511 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23516 /* 64514 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23517 /* 64519 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23518 /* 64522 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23519 /* 64525 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23520 /* 64528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23521 /* 64532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23522 /* 64536 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23523 /* 64540 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4064:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn) => (VQRSHLuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm, QPR:{ *:[v4i32] }:$Vn)
23524 /* 64540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv4i32),
23525 /* 64543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23526 /* 64545 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23527 /* 64547 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23528 /* 64549 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23529 /* 64552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23530 /* 64558 */ GIR_RootConstrainSelectedInstOperands,
23531 /* 64559 */ // GIR_Coverage, 1607,
23532 /* 64559 */ GIR_EraseRootFromParent_Done,
23533 /* 64560 */ // Label 1386: @64560
23534 /* 64560 */ GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(64614), // Rule ID 1608 //
23535 /* 64565 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23536 /* 64568 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23537 /* 64573 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
23538 /* 64576 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
23539 /* 64579 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
23540 /* 64582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23541 /* 64586 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23542 /* 64590 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23543 /* 64594 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4064:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn) => (VQRSHLuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm, DPR:{ *:[v8i8] }:$Vn)
23544 /* 64594 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv8i8),
23545 /* 64597 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23546 /* 64599 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23547 /* 64601 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23548 /* 64603 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23549 /* 64606 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23550 /* 64612 */ GIR_RootConstrainSelectedInstOperands,
23551 /* 64613 */ // GIR_Coverage, 1608,
23552 /* 64613 */ GIR_EraseRootFromParent_Done,
23553 /* 64614 */ // Label 1387: @64614
23554 /* 64614 */ GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(64668), // Rule ID 1609 //
23555 /* 64619 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23556 /* 64622 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23557 /* 64627 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23558 /* 64630 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23559 /* 64633 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23560 /* 64636 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23561 /* 64640 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23562 /* 64644 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23563 /* 64648 */ // (intrinsic_wo_chain:{ *:[v16i8] } 4064:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn) => (VQRSHLuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm, QPR:{ *:[v16i8] }:$Vn)
23564 /* 64648 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv16i8),
23565 /* 64651 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23566 /* 64653 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23567 /* 64655 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23568 /* 64657 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23569 /* 64660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23570 /* 64666 */ GIR_RootConstrainSelectedInstOperands,
23571 /* 64667 */ // GIR_Coverage, 1609,
23572 /* 64667 */ GIR_EraseRootFromParent_Done,
23573 /* 64668 */ // Label 1388: @64668
23574 /* 64668 */ GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(64722), // Rule ID 1610 //
23575 /* 64673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23576 /* 64676 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23577 /* 64681 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64,
23578 /* 64684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
23579 /* 64687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
23580 /* 64690 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23581 /* 64694 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23582 /* 64698 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
23583 /* 64702 */ // (intrinsic_wo_chain:{ *:[v1i64] } 4064:{ *:[iPTR] }, DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn) => (VQRSHLuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vm, DPR:{ *:[v1i64] }:$Vn)
23584 /* 64702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv1i64),
23585 /* 64705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23586 /* 64707 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23587 /* 64709 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23588 /* 64711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23589 /* 64714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23590 /* 64720 */ GIR_RootConstrainSelectedInstOperands,
23591 /* 64721 */ // GIR_Coverage, 1610,
23592 /* 64721 */ GIR_EraseRootFromParent_Done,
23593 /* 64722 */ // Label 1389: @64722
23594 /* 64722 */ GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(64776), // Rule ID 1611 //
23595 /* 64727 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
23596 /* 64730 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrshiftu),
23597 /* 64735 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
23598 /* 64738 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
23599 /* 64741 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
23600 /* 64744 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23601 /* 64748 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23602 /* 64752 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23603 /* 64756 */ // (intrinsic_wo_chain:{ *:[v2i64] } 4064:{ *:[iPTR] }, QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn) => (VQRSHLuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vm, QPR:{ *:[v2i64] }:$Vn)
23604 /* 64756 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRSHLuv2i64),
23605 /* 64759 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23606 /* 64761 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
23607 /* 64763 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
23608 /* 64765 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23609 /* 64768 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23610 /* 64774 */ GIR_RootConstrainSelectedInstOperands,
23611 /* 64775 */ // GIR_Coverage, 1611,
23612 /* 64775 */ GIR_EraseRootFromParent_Done,
23613 /* 64776 */ // Label 1390: @64776
23614 /* 64776 */ GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(64821), // Rule ID 1876 //
23615 /* 64781 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8),
23616 /* 64784 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aesd),
23617 /* 64789 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23618 /* 64792 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23619 /* 64795 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23620 /* 64798 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23621 /* 64802 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23622 /* 64806 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23623 /* 64810 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3965:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESD:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
23624 /* 64810 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESD),
23625 /* 64813 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23626 /* 64815 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
23627 /* 64817 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
23628 /* 64819 */ GIR_RootConstrainSelectedInstOperands,
23629 /* 64820 */ // GIR_Coverage, 1876,
23630 /* 64820 */ GIR_EraseRootFromParent_Done,
23631 /* 64821 */ // Label 1391: @64821
23632 /* 64821 */ GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(64866), // Rule ID 1877 //
23633 /* 64826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAES_HasV8),
23634 /* 64829 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_aese),
23635 /* 64834 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
23636 /* 64837 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
23637 /* 64840 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
23638 /* 64843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23639 /* 64847 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23640 /* 64851 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23641 /* 64855 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3966:{ *:[iPTR] }, QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm) => (AESE:{ *:[v16i8] } QPR:{ *:[v16i8] }:$src, QPR:{ *:[v16i8] }:$Vm)
23642 /* 64855 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::AESE),
23643 /* 64858 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23644 /* 64860 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
23645 /* 64862 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
23646 /* 64864 */ GIR_RootConstrainSelectedInstOperands,
23647 /* 64865 */ // GIR_Coverage, 1877,
23648 /* 64865 */ GIR_EraseRootFromParent_Done,
23649 /* 64866 */ // Label 1392: @64866
23650 /* 64866 */ GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(64911), // Rule ID 1880 //
23651 /* 64871 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
23652 /* 64874 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su1),
23653 /* 64879 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23654 /* 64882 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23655 /* 64885 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23656 /* 64888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23657 /* 64892 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23658 /* 64896 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23659 /* 64900 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3979:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
23660 /* 64900 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU1),
23661 /* 64903 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23662 /* 64905 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
23663 /* 64907 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
23664 /* 64909 */ GIR_RootConstrainSelectedInstOperands,
23665 /* 64910 */ // GIR_Coverage, 1880,
23666 /* 64910 */ GIR_EraseRootFromParent_Done,
23667 /* 64911 */ // Label 1393: @64911
23668 /* 64911 */ GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(64956), // Rule ID 1881 //
23669 /* 64916 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
23670 /* 64919 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su0),
23671 /* 64924 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
23672 /* 64927 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
23673 /* 64930 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
23674 /* 64933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23675 /* 64937 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23676 /* 64941 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
23677 /* 64945 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3982:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vm)
23678 /* 64945 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU0),
23679 /* 64948 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
23680 /* 64950 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
23681 /* 64952 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vm
23682 /* 64954 */ GIR_RootConstrainSelectedInstOperands,
23683 /* 64955 */ // GIR_Coverage, 1881,
23684 /* 64955 */ GIR_EraseRootFromParent_Done,
23685 /* 64956 */ // Label 1394: @64956
23686 /* 64956 */ GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(65010), // Rule ID 1890 //
23687 /* 64961 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
23688 /* 64964 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_sqrshr),
23689 /* 64969 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23690 /* 64972 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23691 /* 64975 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23692 /* 64978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23693 /* 64982 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23694 /* 64986 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23695 /* 64990 */ // (intrinsic_wo_chain:{ *:[i32] } 3815:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_SQRSHR:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
23696 /* 64990 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_SQRSHR),
23697 /* 64993 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23698 /* 64995 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
23699 /* 64997 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23700 /* 64999 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23701 /* 65002 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23702 /* 65008 */ GIR_RootConstrainSelectedInstOperands,
23703 /* 65009 */ // GIR_Coverage, 1890,
23704 /* 65009 */ GIR_EraseRootFromParent_Done,
23705 /* 65010 */ // Label 1395: @65010
23706 /* 65010 */ GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(65064), // Rule ID 1891 //
23707 /* 65015 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt_HasV8_1MMainline),
23708 /* 65018 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_uqrshl),
23709 /* 65023 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23710 /* 65026 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23711 /* 65029 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23712 /* 65032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23713 /* 65036 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23714 /* 65040 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23715 /* 65044 */ // (intrinsic_wo_chain:{ *:[i32] } 3822:{ *:[iPTR] }, rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm) => (MVE_UQRSHL:{ *:[i32] } rGPR:{ *:[i32] }:$RdaSrc, rGPR:{ *:[i32] }:$Rm)
23716 /* 65044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_UQRSHL),
23717 /* 65047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
23718 /* 65049 */ GIR_RootToRootCopy, /*OpIdx*/2, // RdaSrc
23719 /* 65051 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23720 /* 65053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23721 /* 65056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23722 /* 65062 */ GIR_RootConstrainSelectedInstOperands,
23723 /* 65063 */ // GIR_Coverage, 1891,
23724 /* 65063 */ GIR_EraseRootFromParent_Done,
23725 /* 65064 */ // Label 1396: @65064
23726 /* 65064 */ GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(65121), // Rule ID 2014 //
23727 /* 65069 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23728 /* 65072 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16),
23729 /* 65077 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23730 /* 65080 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23731 /* 65083 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23732 /* 65086 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23733 /* 65090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23734 /* 65094 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23735 /* 65098 */ // (intrinsic_wo_chain:{ *:[i32] } 4160:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (SXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
23736 /* 65098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTAB16),
23737 /* 65101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23738 /* 65103 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS
23739 /* 65105 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS
23740 /* 65107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23741 /* 65110 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23742 /* 65113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23743 /* 65119 */ GIR_RootConstrainSelectedInstOperands,
23744 /* 65120 */ // GIR_Coverage, 2014,
23745 /* 65120 */ GIR_EraseRootFromParent_Done,
23746 /* 65121 */ // Label 1397: @65121
23747 /* 65121 */ GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(65178), // Rule ID 2021 //
23748 /* 65126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23749 /* 65129 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uxtab16),
23750 /* 65134 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23751 /* 65137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23752 /* 65140 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23753 /* 65143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23754 /* 65147 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23755 /* 65151 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23756 /* 65155 */ // (intrinsic_wo_chain:{ *:[i32] } 4185:{ *:[iPTR] }, GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS) => (UXTAB16:{ *:[i32] } GPR:{ *:[i32] }:$LHS, GPR:{ *:[i32] }:$RHS, 0:{ *:[i32] })
23757 /* 65155 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UXTAB16),
23758 /* 65158 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23759 /* 65160 */ GIR_RootToRootCopy, /*OpIdx*/2, // LHS
23760 /* 65162 */ GIR_RootToRootCopy, /*OpIdx*/3, // RHS
23761 /* 65164 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23762 /* 65167 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23763 /* 65170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23764 /* 65176 */ GIR_RootConstrainSelectedInstOperands,
23765 /* 65177 */ // GIR_Coverage, 2021,
23766 /* 65177 */ GIR_EraseRootFromParent_Done,
23767 /* 65178 */ // Label 1398: @65178
23768 /* 65178 */ GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(65232), // Rule ID 2068 //
23769 /* 65183 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23770 /* 65186 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuad),
23771 /* 65191 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23772 /* 65194 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23773 /* 65197 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23774 /* 65200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23775 /* 65204 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23776 /* 65208 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23777 /* 65212 */ // (intrinsic_wo_chain:{ *:[i32] } 4136:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23778 /* 65212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUAD),
23779 /* 65215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23780 /* 65217 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23781 /* 65219 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23782 /* 65221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23783 /* 65224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23784 /* 65230 */ GIR_RootConstrainSelectedInstOperands,
23785 /* 65231 */ // GIR_Coverage, 2068,
23786 /* 65231 */ GIR_EraseRootFromParent_Done,
23787 /* 65232 */ // Label 1399: @65232
23788 /* 65232 */ GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(65286), // Rule ID 2069 //
23789 /* 65237 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23790 /* 65240 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smuadx),
23791 /* 65245 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23792 /* 65248 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23793 /* 65251 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23794 /* 65254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23795 /* 65258 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23796 /* 65262 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23797 /* 65266 */ // (intrinsic_wo_chain:{ *:[i32] } 4137:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23798 /* 65266 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUADX),
23799 /* 65269 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23800 /* 65271 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23801 /* 65273 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23802 /* 65275 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23803 /* 65278 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23804 /* 65284 */ GIR_RootConstrainSelectedInstOperands,
23805 /* 65285 */ // GIR_Coverage, 2069,
23806 /* 65285 */ GIR_EraseRootFromParent_Done,
23807 /* 65286 */ // Label 1400: @65286
23808 /* 65286 */ GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(65340), // Rule ID 2070 //
23809 /* 65291 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23810 /* 65294 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusd),
23811 /* 65299 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23812 /* 65302 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23813 /* 65305 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23814 /* 65308 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23815 /* 65312 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23816 /* 65316 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23817 /* 65320 */ // (intrinsic_wo_chain:{ *:[i32] } 4144:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23818 /* 65320 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSD),
23819 /* 65323 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23820 /* 65325 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23821 /* 65327 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23822 /* 65329 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23823 /* 65332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23824 /* 65338 */ GIR_RootConstrainSelectedInstOperands,
23825 /* 65339 */ // GIR_Coverage, 2070,
23826 /* 65339 */ GIR_EraseRootFromParent_Done,
23827 /* 65340 */ // Label 1401: @65340
23828 /* 65340 */ GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(65394), // Rule ID 2071 //
23829 /* 65345 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
23830 /* 65348 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smusdx),
23831 /* 65353 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23832 /* 65356 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23833 /* 65359 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23834 /* 65362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23835 /* 65366 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23836 /* 65370 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
23837 /* 65374 */ // (intrinsic_wo_chain:{ *:[i32] } 4145:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SMUSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
23838 /* 65374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMUSDX),
23839 /* 65377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23840 /* 65379 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23841 /* 65381 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23842 /* 65383 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23843 /* 65386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23844 /* 65392 */ GIR_RootConstrainSelectedInstOperands,
23845 /* 65393 */ // GIR_Coverage, 2071,
23846 /* 65393 */ GIR_EraseRootFromParent_Done,
23847 /* 65394 */ // Label 1402: @65394
23848 /* 65394 */ GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(65448), // Rule ID 2145 //
23849 /* 65399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23850 /* 65402 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb),
23851 /* 65407 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23852 /* 65410 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23853 /* 65413 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23854 /* 65416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23855 /* 65420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23856 /* 65424 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23857 /* 65428 */ // (intrinsic_wo_chain:{ *:[i32] } 4138:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23858 /* 65428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBB),
23859 /* 65431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23860 /* 65433 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23861 /* 65435 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23862 /* 65437 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23863 /* 65440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23864 /* 65446 */ GIR_RootConstrainSelectedInstOperands,
23865 /* 65447 */ // GIR_Coverage, 2145,
23866 /* 65447 */ GIR_EraseRootFromParent_Done,
23867 /* 65448 */ // Label 1403: @65448
23868 /* 65448 */ GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(65502), // Rule ID 2146 //
23869 /* 65453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23870 /* 65456 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt),
23871 /* 65461 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23872 /* 65464 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23873 /* 65467 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23874 /* 65470 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23875 /* 65474 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23876 /* 65478 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23877 /* 65482 */ // (intrinsic_wo_chain:{ *:[i32] } 4139:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULBT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23878 /* 65482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULBT),
23879 /* 65485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23880 /* 65487 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23881 /* 65489 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23882 /* 65491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23883 /* 65494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23884 /* 65500 */ GIR_RootConstrainSelectedInstOperands,
23885 /* 65501 */ // GIR_Coverage, 2146,
23886 /* 65501 */ GIR_EraseRootFromParent_Done,
23887 /* 65502 */ // Label 1404: @65502
23888 /* 65502 */ GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(65556), // Rule ID 2147 //
23889 /* 65507 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23890 /* 65510 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb),
23891 /* 65515 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23892 /* 65518 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23893 /* 65521 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23894 /* 65524 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23895 /* 65528 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23896 /* 65532 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23897 /* 65536 */ // (intrinsic_wo_chain:{ *:[i32] } 4140:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23898 /* 65536 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTB),
23899 /* 65539 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23900 /* 65541 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23901 /* 65543 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23902 /* 65545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23903 /* 65548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23904 /* 65554 */ GIR_RootConstrainSelectedInstOperands,
23905 /* 65555 */ // GIR_Coverage, 2147,
23906 /* 65555 */ GIR_EraseRootFromParent_Done,
23907 /* 65556 */ // Label 1405: @65556
23908 /* 65556 */ GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(65610), // Rule ID 2148 //
23909 /* 65561 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23910 /* 65564 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt),
23911 /* 65569 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23912 /* 65572 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23913 /* 65575 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23914 /* 65578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23915 /* 65582 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23916 /* 65586 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23917 /* 65590 */ // (intrinsic_wo_chain:{ *:[i32] } 4141:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULTT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23918 /* 65590 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULTT),
23919 /* 65593 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23920 /* 65595 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23921 /* 65597 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23922 /* 65599 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23923 /* 65602 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23924 /* 65608 */ GIR_RootConstrainSelectedInstOperands,
23925 /* 65609 */ // GIR_Coverage, 2148,
23926 /* 65609 */ GIR_EraseRootFromParent_Done,
23927 /* 65610 */ // Label 1406: @65610
23928 /* 65610 */ GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(65664), // Rule ID 2149 //
23929 /* 65615 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23930 /* 65618 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb),
23931 /* 65623 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23932 /* 65626 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23933 /* 65629 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23934 /* 65632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23935 /* 65636 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23936 /* 65640 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23937 /* 65644 */ // (intrinsic_wo_chain:{ *:[i32] } 4142:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23938 /* 65644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWB),
23939 /* 65647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23940 /* 65649 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23941 /* 65651 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23942 /* 65653 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23943 /* 65656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23944 /* 65662 */ GIR_RootConstrainSelectedInstOperands,
23945 /* 65663 */ // GIR_Coverage, 2149,
23946 /* 65663 */ GIR_EraseRootFromParent_Done,
23947 /* 65664 */ // Label 1407: @65664
23948 /* 65664 */ GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(65718), // Rule ID 2150 //
23949 /* 65669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
23950 /* 65672 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt),
23951 /* 65677 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23952 /* 65680 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23953 /* 65683 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23954 /* 65686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23955 /* 65690 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23956 /* 65694 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
23957 /* 65698 */ // (intrinsic_wo_chain:{ *:[i32] } 4143:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (SMULWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
23958 /* 65698 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMULWT),
23959 /* 65701 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23960 /* 65703 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
23961 /* 65705 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
23962 /* 65707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23963 /* 65710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23964 /* 65716 */ GIR_RootConstrainSelectedInstOperands,
23965 /* 65717 */ // GIR_Coverage, 2150,
23966 /* 65717 */ GIR_EraseRootFromParent_Done,
23967 /* 65718 */ // Label 1408: @65718
23968 /* 65718 */ GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(65775), // Rule ID 2261 //
23969 /* 65723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23970 /* 65726 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sxtab16),
23971 /* 65731 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23972 /* 65734 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23973 /* 65737 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23974 /* 65740 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23975 /* 65744 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23976 /* 65748 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23977 /* 65752 */ // (intrinsic_wo_chain:{ *:[i32] } 4160:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SXTAB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, 0:{ *:[i32] })
23978 /* 65752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTAB16),
23979 /* 65755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
23980 /* 65757 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
23981 /* 65759 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
23982 /* 65761 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
23983 /* 65764 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
23984 /* 65767 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
23985 /* 65773 */ GIR_RootConstrainSelectedInstOperands,
23986 /* 65774 */ // GIR_Coverage, 2261,
23987 /* 65774 */ GIR_EraseRootFromParent_Done,
23988 /* 65775 */ // Label 1409: @65775
23989 /* 65775 */ GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(65829), // Rule ID 2291 //
23990 /* 65780 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
23991 /* 65783 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qadd),
23992 /* 65788 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
23993 /* 65791 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
23994 /* 65794 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
23995 /* 65797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23996 /* 65801 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23997 /* 65805 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
23998 /* 65809 */ // (intrinsic_wo_chain:{ *:[i32] } 4103:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
23999 /* 65809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD),
24000 /* 65812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
24001 /* 65814 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
24002 /* 65816 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
24003 /* 65818 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
24004 /* 65821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24005 /* 65827 */ GIR_RootConstrainSelectedInstOperands,
24006 /* 65828 */ // GIR_Coverage, 2291,
24007 /* 65828 */ GIR_EraseRootFromParent_Done,
24008 /* 65829 */ // Label 1410: @65829
24009 /* 65829 */ GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(65883), // Rule ID 2292 //
24010 /* 65834 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
24011 /* 65837 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_qsub),
24012 /* 65842 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24013 /* 65845 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24014 /* 65848 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24015 /* 65851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24016 /* 65855 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24017 /* 65859 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24018 /* 65863 */ // (intrinsic_wo_chain:{ *:[i32] } 4108:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
24019 /* 65863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB),
24020 /* 65866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
24021 /* 65868 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
24022 /* 65870 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
24023 /* 65872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
24024 /* 65875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24025 /* 65881 */ GIR_RootConstrainSelectedInstOperands,
24026 /* 65882 */ // GIR_Coverage, 2292,
24027 /* 65882 */ GIR_EraseRootFromParent_Done,
24028 /* 65883 */ // Label 1411: @65883
24029 /* 65883 */ GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(65937), // Rule ID 2332 //
24030 /* 65888 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
24031 /* 65891 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbb),
24032 /* 65896 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24033 /* 65899 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24034 /* 65902 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24035 /* 65905 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24036 /* 65909 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24037 /* 65913 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24038 /* 65917 */ // (intrinsic_wo_chain:{ *:[i32] } 4138:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
24039 /* 65917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBB),
24040 /* 65920 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
24041 /* 65922 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24042 /* 65924 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24043 /* 65926 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
24044 /* 65929 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24045 /* 65935 */ GIR_RootConstrainSelectedInstOperands,
24046 /* 65936 */ // GIR_Coverage, 2332,
24047 /* 65936 */ GIR_EraseRootFromParent_Done,
24048 /* 65937 */ // Label 1412: @65937
24049 /* 65937 */ GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(65991), // Rule ID 2333 //
24050 /* 65942 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
24051 /* 65945 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulbt),
24052 /* 65950 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24053 /* 65953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24054 /* 65956 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24055 /* 65959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24056 /* 65963 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24057 /* 65967 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24058 /* 65971 */ // (intrinsic_wo_chain:{ *:[i32] } 4139:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULBT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
24059 /* 65971 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULBT),
24060 /* 65974 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
24061 /* 65976 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24062 /* 65978 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24063 /* 65980 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
24064 /* 65983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24065 /* 65989 */ GIR_RootConstrainSelectedInstOperands,
24066 /* 65990 */ // GIR_Coverage, 2333,
24067 /* 65990 */ GIR_EraseRootFromParent_Done,
24068 /* 65991 */ // Label 1413: @65991
24069 /* 65991 */ GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(66045), // Rule ID 2334 //
24070 /* 65996 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
24071 /* 65999 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultb),
24072 /* 66004 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24073 /* 66007 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24074 /* 66010 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24075 /* 66013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24076 /* 66017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24077 /* 66021 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24078 /* 66025 */ // (intrinsic_wo_chain:{ *:[i32] } 4140:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
24079 /* 66025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTB),
24080 /* 66028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
24081 /* 66030 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24082 /* 66032 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24083 /* 66034 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
24084 /* 66037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24085 /* 66043 */ GIR_RootConstrainSelectedInstOperands,
24086 /* 66044 */ // GIR_Coverage, 2334,
24087 /* 66044 */ GIR_EraseRootFromParent_Done,
24088 /* 66045 */ // Label 1414: @66045
24089 /* 66045 */ GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(66099), // Rule ID 2335 //
24090 /* 66050 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
24091 /* 66053 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smultt),
24092 /* 66058 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24093 /* 66061 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24094 /* 66064 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24095 /* 66067 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24096 /* 66071 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24097 /* 66075 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24098 /* 66079 */ // (intrinsic_wo_chain:{ *:[i32] } 4141:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULTT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
24099 /* 66079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULTT),
24100 /* 66082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
24101 /* 66084 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24102 /* 66086 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24103 /* 66088 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
24104 /* 66091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24105 /* 66097 */ GIR_RootConstrainSelectedInstOperands,
24106 /* 66098 */ // GIR_Coverage, 2335,
24107 /* 66098 */ GIR_EraseRootFromParent_Done,
24108 /* 66099 */ // Label 1415: @66099
24109 /* 66099 */ GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(66153), // Rule ID 2336 //
24110 /* 66104 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
24111 /* 66107 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwb),
24112 /* 66112 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24113 /* 66115 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24114 /* 66118 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24115 /* 66121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24116 /* 66125 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24117 /* 66129 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24118 /* 66133 */ // (intrinsic_wo_chain:{ *:[i32] } 4142:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWB:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
24119 /* 66133 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWB),
24120 /* 66136 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
24121 /* 66138 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24122 /* 66140 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24123 /* 66142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
24124 /* 66145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24125 /* 66151 */ GIR_RootConstrainSelectedInstOperands,
24126 /* 66152 */ // GIR_Coverage, 2336,
24127 /* 66152 */ GIR_EraseRootFromParent_Done,
24128 /* 66153 */ // Label 1416: @66153
24129 /* 66153 */ GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(66207), // Rule ID 2337 //
24130 /* 66158 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
24131 /* 66161 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smulwt),
24132 /* 66166 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24133 /* 66169 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24134 /* 66172 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
24135 /* 66175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24136 /* 66179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24137 /* 66183 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24138 /* 66187 */ // (intrinsic_wo_chain:{ *:[i32] } 4143:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMULWT:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
24139 /* 66187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMULWT),
24140 /* 66190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
24141 /* 66192 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24142 /* 66194 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24143 /* 66196 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
24144 /* 66199 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24145 /* 66205 */ GIR_RootConstrainSelectedInstOperands,
24146 /* 66206 */ // GIR_Coverage, 2337,
24147 /* 66206 */ GIR_EraseRootFromParent_Done,
24148 /* 66207 */ // Label 1417: @66207
24149 /* 66207 */ GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(66255), // Rule ID 2863 //
24150 /* 66212 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a),
24151 /* 66215 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
24152 /* 66220 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
24153 /* 66223 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
24154 /* 66226 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
24155 /* 66229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24156 /* 66233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24157 /* 66237 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24158 /* 66241 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3996:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 0:{ *:[i32] })
24159 /* 66241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16),
24160 /* 66244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24161 /* 66246 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24162 /* 66248 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24163 /* 66250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24164 /* 66253 */ GIR_RootConstrainSelectedInstOperands,
24165 /* 66254 */ // GIR_Coverage, 2863,
24166 /* 66254 */ GIR_EraseRootFromParent_Done,
24167 /* 66255 */ // Label 1418: @66255
24168 /* 66255 */ GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(66303), // Rule ID 2864 //
24169 /* 66260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a),
24170 /* 66263 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
24171 /* 66268 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
24172 /* 66271 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
24173 /* 66274 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
24174 /* 66277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24175 /* 66281 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24176 /* 66285 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24177 /* 66289 */ // (intrinsic_wo_chain:{ *:[v4f16] } 3995:{ *:[iPTR] }, DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm) => (VCADDv4f16:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Rn, DPR:{ *:[v4f16] }:$Rm, 1:{ *:[i32] })
24178 /* 66289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f16),
24179 /* 66292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24180 /* 66294 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24181 /* 66296 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24182 /* 66298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
24183 /* 66301 */ GIR_RootConstrainSelectedInstOperands,
24184 /* 66302 */ // GIR_Coverage, 2864,
24185 /* 66302 */ GIR_EraseRootFromParent_Done,
24186 /* 66303 */ // Label 1419: @66303
24187 /* 66303 */ GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(66351), // Rule ID 2865 //
24188 /* 66308 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a),
24189 /* 66311 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
24190 /* 66316 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24191 /* 66319 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24192 /* 66322 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24193 /* 66325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24194 /* 66329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24195 /* 66333 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24196 /* 66337 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3996:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 0:{ *:[i32] })
24197 /* 66337 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16),
24198 /* 66340 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24199 /* 66342 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24200 /* 66344 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24201 /* 66346 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24202 /* 66349 */ GIR_RootConstrainSelectedInstOperands,
24203 /* 66350 */ // GIR_Coverage, 2865,
24204 /* 66350 */ GIR_EraseRootFromParent_Done,
24205 /* 66351 */ // Label 1420: @66351
24206 /* 66351 */ GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(66399), // Rule ID 2866 //
24207 /* 66356 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8_3a),
24208 /* 66359 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
24209 /* 66364 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24210 /* 66367 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24211 /* 66370 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24212 /* 66373 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24213 /* 66377 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24214 /* 66381 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24215 /* 66385 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3995:{ *:[iPTR] }, QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm) => (VCADDv8f16:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Rn, QPR:{ *:[v8f16] }:$Rm, 1:{ *:[i32] })
24216 /* 66385 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv8f16),
24217 /* 66388 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24218 /* 66390 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24219 /* 66392 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24220 /* 66394 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
24221 /* 66397 */ GIR_RootConstrainSelectedInstOperands,
24222 /* 66398 */ // GIR_Coverage, 2866,
24223 /* 66398 */ GIR_EraseRootFromParent_Done,
24224 /* 66399 */ // Label 1421: @66399
24225 /* 66399 */ GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(66447), // Rule ID 2867 //
24226 /* 66404 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a),
24227 /* 66407 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
24228 /* 66412 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
24229 /* 66415 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
24230 /* 66418 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
24231 /* 66421 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24232 /* 66425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24233 /* 66429 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24234 /* 66433 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3996:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 0:{ *:[i32] })
24235 /* 66433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32),
24236 /* 66436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24237 /* 66438 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24238 /* 66440 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24239 /* 66442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24240 /* 66445 */ GIR_RootConstrainSelectedInstOperands,
24241 /* 66446 */ // GIR_Coverage, 2867,
24242 /* 66446 */ GIR_EraseRootFromParent_Done,
24243 /* 66447 */ // Label 1422: @66447
24244 /* 66447 */ GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(66495), // Rule ID 2868 //
24245 /* 66452 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a),
24246 /* 66455 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
24247 /* 66460 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
24248 /* 66463 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
24249 /* 66466 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
24250 /* 66469 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24251 /* 66473 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24252 /* 66477 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
24253 /* 66481 */ // (intrinsic_wo_chain:{ *:[v2f32] } 3995:{ *:[iPTR] }, DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm) => (VCADDv2f32:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Rn, DPR:{ *:[v2f32] }:$Rm, 1:{ *:[i32] })
24254 /* 66481 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv2f32),
24255 /* 66484 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24256 /* 66486 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24257 /* 66488 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24258 /* 66490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
24259 /* 66493 */ GIR_RootConstrainSelectedInstOperands,
24260 /* 66494 */ // GIR_Coverage, 2868,
24261 /* 66494 */ GIR_EraseRootFromParent_Done,
24262 /* 66495 */ // Label 1423: @66495
24263 /* 66495 */ GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(66543), // Rule ID 2869 //
24264 /* 66500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a),
24265 /* 66503 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot90),
24266 /* 66508 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24267 /* 66511 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24268 /* 66514 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24269 /* 66517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24270 /* 66521 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24271 /* 66525 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24272 /* 66529 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3996:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 0:{ *:[i32] })
24273 /* 66529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32),
24274 /* 66532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24275 /* 66534 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24276 /* 66536 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24277 /* 66538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24278 /* 66541 */ GIR_RootConstrainSelectedInstOperands,
24279 /* 66542 */ // GIR_Coverage, 2869,
24280 /* 66542 */ GIR_EraseRootFromParent_Done,
24281 /* 66543 */ // Label 1424: @66543
24282 /* 66543 */ GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(66591), // Rule ID 2870 //
24283 /* 66548 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_3a),
24284 /* 66551 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vcadd_rot270),
24285 /* 66556 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24286 /* 66559 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24287 /* 66562 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24288 /* 66565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24289 /* 66569 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24290 /* 66573 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
24291 /* 66577 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3995:{ *:[iPTR] }, QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm) => (VCADDv4f32:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Rn, QPR:{ *:[v4f32] }:$Rm, 1:{ *:[i32] })
24292 /* 66577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCADDv4f32),
24293 /* 66580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
24294 /* 66582 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
24295 /* 66584 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
24296 /* 66586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
24297 /* 66589 */ GIR_RootConstrainSelectedInstOperands,
24298 /* 66590 */ // GIR_Coverage, 2870,
24299 /* 66590 */ GIR_EraseRootFromParent_Done,
24300 /* 66591 */ // Label 1425: @66591
24301 /* 66591 */ GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(66666), // Rule ID 3381 //
24302 /* 66596 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24303 /* 66599 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm),
24304 /* 66604 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24305 /* 66607 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24306 /* 66610 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24307 /* 66613 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24308 /* 66617 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24309 /* 66621 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24310 /* 66625 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3883:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
24311 /* 66625 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24312 /* 66628 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24313 /* 66632 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24314 /* 66637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32),
24315 /* 66640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24316 /* 66642 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24317 /* 66644 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24318 /* 66646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24319 /* 66649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24320 /* 66655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24321 /* 66661 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24322 /* 66664 */ GIR_RootConstrainSelectedInstOperands,
24323 /* 66665 */ // GIR_Coverage, 3381,
24324 /* 66665 */ GIR_EraseRootFromParent_Done,
24325 /* 66666 */ // Label 1426: @66666
24326 /* 66666 */ GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(66771), // Rule ID 3457 //
24327 /* 66671 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24328 /* 66674 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv),
24329 /* 66679 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24330 /* 66682 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24331 /* 66685 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24332 /* 66688 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24333 /* 66692 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24334 /* 66696 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24335 /* 66700 */ // (intrinsic_wo_chain:{ *:[f32] } 3791:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
24336 /* 66700 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24337 /* 66703 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24338 /* 66707 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24339 /* 66712 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24340 /* 66716 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24341 /* 66721 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24342 /* 66724 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf32),
24343 /* 66728 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24344 /* 66733 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24345 /* 66736 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24346 /* 66740 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24347 /* 66743 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24348 /* 66749 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24349 /* 66755 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24350 /* 66757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24351 /* 66760 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24352 /* 66762 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24353 /* 66765 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
24354 /* 66770 */ // GIR_Coverage, 3457,
24355 /* 66770 */ GIR_EraseRootFromParent_Done,
24356 /* 66771 */ // Label 1427: @66771
24357 /* 66771 */ GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(66876), // Rule ID 3459 //
24358 /* 66776 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24359 /* 66779 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmv),
24360 /* 66784 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
24361 /* 66787 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
24362 /* 66790 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24363 /* 66793 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24364 /* 66797 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24365 /* 66801 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24366 /* 66805 */ // (intrinsic_wo_chain:{ *:[f16] } 3791:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
24367 /* 66805 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24368 /* 66808 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24369 /* 66812 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24370 /* 66817 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24371 /* 66821 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24372 /* 66826 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24373 /* 66829 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMVf16),
24374 /* 66833 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24375 /* 66838 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24376 /* 66841 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24377 /* 66845 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24378 /* 66848 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24379 /* 66854 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24380 /* 66860 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24381 /* 66862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24382 /* 66865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24383 /* 66867 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24384 /* 66870 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
24385 /* 66875 */ // GIR_Coverage, 3459,
24386 /* 66875 */ GIR_EraseRootFromParent_Done,
24387 /* 66876 */ // Label 1428: @66876
24388 /* 66876 */ GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(66981), // Rule ID 3461 //
24389 /* 66881 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24390 /* 66884 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv),
24391 /* 66889 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24392 /* 66892 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24393 /* 66895 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24394 /* 66898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24395 /* 66902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24396 /* 66906 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24397 /* 66910 */ // (intrinsic_wo_chain:{ *:[f32] } 3782:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
24398 /* 66910 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24399 /* 66913 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24400 /* 66917 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24401 /* 66922 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24402 /* 66926 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24403 /* 66931 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24404 /* 66934 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf32),
24405 /* 66938 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24406 /* 66943 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24407 /* 66946 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24408 /* 66950 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24409 /* 66953 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24410 /* 66959 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24411 /* 66965 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24412 /* 66967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24413 /* 66970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24414 /* 66972 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24415 /* 66975 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
24416 /* 66980 */ // GIR_Coverage, 3461,
24417 /* 66980 */ GIR_EraseRootFromParent_Done,
24418 /* 66981 */ // Label 1429: @66981
24419 /* 66981 */ GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(67086), // Rule ID 3463 //
24420 /* 66986 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24421 /* 66989 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmv),
24422 /* 66994 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
24423 /* 66997 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
24424 /* 67000 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24425 /* 67003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24426 /* 67007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24427 /* 67011 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24428 /* 67015 */ // (intrinsic_wo_chain:{ *:[f16] } 3782:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
24429 /* 67015 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24430 /* 67018 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24431 /* 67022 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24432 /* 67027 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24433 /* 67031 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24434 /* 67036 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24435 /* 67039 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMVf16),
24436 /* 67043 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24437 /* 67048 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24438 /* 67051 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24439 /* 67055 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24440 /* 67058 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24441 /* 67064 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24442 /* 67070 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24443 /* 67072 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24444 /* 67075 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24445 /* 67077 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24446 /* 67080 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
24447 /* 67085 */ // GIR_Coverage, 3463,
24448 /* 67085 */ GIR_EraseRootFromParent_Done,
24449 /* 67086 */ // Label 1430: @67086
24450 /* 67086 */ GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(67191), // Rule ID 3465 //
24451 /* 67091 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24452 /* 67094 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav),
24453 /* 67099 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24454 /* 67102 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24455 /* 67105 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24456 /* 67108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24457 /* 67112 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24458 /* 67116 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24459 /* 67120 */ // (intrinsic_wo_chain:{ *:[f32] } 3789:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMINNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
24460 /* 67120 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24461 /* 67123 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24462 /* 67127 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24463 /* 67132 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24464 /* 67136 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24465 /* 67141 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24466 /* 67144 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf32),
24467 /* 67148 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24468 /* 67153 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24469 /* 67156 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24470 /* 67160 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24471 /* 67163 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24472 /* 67169 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24473 /* 67175 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24474 /* 67177 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24475 /* 67180 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24476 /* 67182 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24477 /* 67185 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
24478 /* 67190 */ // GIR_Coverage, 3465,
24479 /* 67190 */ GIR_EraseRootFromParent_Done,
24480 /* 67191 */ // Label 1431: @67191
24481 /* 67191 */ GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(67296), // Rule ID 3467 //
24482 /* 67196 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24483 /* 67199 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minnmav),
24484 /* 67204 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
24485 /* 67207 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
24486 /* 67210 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24487 /* 67213 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24488 /* 67217 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24489 /* 67221 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24490 /* 67225 */ // (intrinsic_wo_chain:{ *:[f16] } 3789:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMINNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
24491 /* 67225 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24492 /* 67228 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24493 /* 67232 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24494 /* 67237 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24495 /* 67241 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24496 /* 67246 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24497 /* 67249 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAVf16),
24498 /* 67253 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24499 /* 67258 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24500 /* 67261 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24501 /* 67265 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24502 /* 67268 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24503 /* 67274 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24504 /* 67280 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24505 /* 67282 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24506 /* 67285 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24507 /* 67287 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24508 /* 67290 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
24509 /* 67295 */ // GIR_Coverage, 3467,
24510 /* 67295 */ GIR_EraseRootFromParent_Done,
24511 /* 67296 */ // Label 1432: @67296
24512 /* 67296 */ GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(67401), // Rule ID 3469 //
24513 /* 67301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24514 /* 67304 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav),
24515 /* 67309 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24516 /* 67312 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24517 /* 67315 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24518 /* 67318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24519 /* 67322 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
24520 /* 67326 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24521 /* 67330 */ // (intrinsic_wo_chain:{ *:[f32] } 3780:{ *:[iPTR] }, SPR:{ *:[f32] }:$prev, MQPR:{ *:[v4f32] }:$vec) => (COPY_TO_REGCLASS:{ *:[f32] } (MVE_VMAXNMAVf32:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SPR:{ *:[f32] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v4f32] }:$vec), SPR:{ *:[i32] })
24522 /* 67330 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24523 /* 67333 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24524 /* 67337 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24525 /* 67342 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24526 /* 67346 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24527 /* 67351 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24528 /* 67354 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf32),
24529 /* 67358 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24530 /* 67363 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24531 /* 67366 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24532 /* 67370 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24533 /* 67373 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24534 /* 67379 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24535 /* 67385 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24536 /* 67387 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24537 /* 67390 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24538 /* 67392 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24539 /* 67395 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
24540 /* 67400 */ // GIR_Coverage, 3469,
24541 /* 67400 */ GIR_EraseRootFromParent_Done,
24542 /* 67401 */ // Label 1433: @67401
24543 /* 67401 */ GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(67506), // Rule ID 3471 //
24544 /* 67406 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24545 /* 67409 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxnmav),
24546 /* 67414 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16,
24547 /* 67417 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
24548 /* 67420 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24549 /* 67423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24550 /* 67427 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
24551 /* 67431 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24552 /* 67435 */ // (intrinsic_wo_chain:{ *:[f16] } 3780:{ *:[iPTR] }, HPR:{ *:[f16] }:$prev, MQPR:{ *:[v8f16] }:$vec) => (COPY_TO_REGCLASS:{ *:[f16] } (MVE_VMAXNMAVf16:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } HPR:{ *:[f16] }:$prev, rGPR:{ *:[i32] }), MQPR:{ *:[v8f16] }:$vec), HPR:{ *:[i32] })
24553 /* 67435 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
24554 /* 67438 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24555 /* 67442 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24556 /* 67447 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // prev
24557 /* 67451 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::rGPRRegClassID),
24558 /* 67456 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
24559 /* 67459 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAVf16),
24560 /* 67463 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24561 /* 67468 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
24562 /* 67471 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vec
24563 /* 67475 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
24564 /* 67478 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24565 /* 67484 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24566 /* 67490 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
24567 /* 67492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
24568 /* 67495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
24569 /* 67497 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24570 /* 67500 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
24571 /* 67505 */ // GIR_Coverage, 3471,
24572 /* 67505 */ GIR_EraseRootFromParent_Done,
24573 /* 67506 */ // Label 1434: @67506
24574 /* 67506 */ GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(67566), // Rule ID 3521 //
24575 /* 67511 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24576 /* 67514 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav),
24577 /* 67519 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24578 /* 67522 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24579 /* 67525 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24580 /* 67528 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24581 /* 67532 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24582 /* 67536 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24583 /* 67540 */ // (intrinsic_wo_chain:{ *:[i32] } 3787:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMINAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
24584 /* 67540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs8),
24585 /* 67543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
24586 /* 67545 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
24587 /* 67547 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
24588 /* 67549 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24589 /* 67552 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24590 /* 67558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24591 /* 67564 */ GIR_RootConstrainSelectedInstOperands,
24592 /* 67565 */ // GIR_Coverage, 3521,
24593 /* 67565 */ GIR_EraseRootFromParent_Done,
24594 /* 67566 */ // Label 1435: @67566
24595 /* 67566 */ GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(67626), // Rule ID 3523 //
24596 /* 67571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24597 /* 67574 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav),
24598 /* 67579 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24599 /* 67582 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24600 /* 67585 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24601 /* 67588 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24602 /* 67592 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24603 /* 67596 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24604 /* 67600 */ // (intrinsic_wo_chain:{ *:[i32] } 3787:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMINAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
24605 /* 67600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs16),
24606 /* 67603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
24607 /* 67605 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
24608 /* 67607 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
24609 /* 67609 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24610 /* 67612 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24611 /* 67618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24612 /* 67624 */ GIR_RootConstrainSelectedInstOperands,
24613 /* 67625 */ // GIR_Coverage, 3523,
24614 /* 67625 */ GIR_EraseRootFromParent_Done,
24615 /* 67626 */ // Label 1436: @67626
24616 /* 67626 */ GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(67686), // Rule ID 3525 //
24617 /* 67631 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24618 /* 67634 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minav),
24619 /* 67639 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24620 /* 67642 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24621 /* 67645 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24622 /* 67648 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24623 /* 67652 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24624 /* 67656 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24625 /* 67660 */ // (intrinsic_wo_chain:{ *:[i32] } 3787:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMINAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
24626 /* 67660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAVs32),
24627 /* 67663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
24628 /* 67665 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
24629 /* 67667 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
24630 /* 67669 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24631 /* 67672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24632 /* 67678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24633 /* 67684 */ GIR_RootConstrainSelectedInstOperands,
24634 /* 67685 */ // GIR_Coverage, 3525,
24635 /* 67685 */ GIR_EraseRootFromParent_Done,
24636 /* 67686 */ // Label 1437: @67686
24637 /* 67686 */ GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(67746), // Rule ID 3527 //
24638 /* 67691 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24639 /* 67694 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav),
24640 /* 67699 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24641 /* 67702 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24642 /* 67705 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24643 /* 67708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24644 /* 67712 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24645 /* 67716 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24646 /* 67720 */ // (intrinsic_wo_chain:{ *:[i32] } 3778:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec) => (MVE_VMAXAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
24647 /* 67720 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs8),
24648 /* 67723 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
24649 /* 67725 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
24650 /* 67727 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
24651 /* 67729 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24652 /* 67732 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24653 /* 67738 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24654 /* 67744 */ GIR_RootConstrainSelectedInstOperands,
24655 /* 67745 */ // GIR_Coverage, 3527,
24656 /* 67745 */ GIR_EraseRootFromParent_Done,
24657 /* 67746 */ // Label 1438: @67746
24658 /* 67746 */ GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(67806), // Rule ID 3529 //
24659 /* 67751 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24660 /* 67754 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav),
24661 /* 67759 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24662 /* 67762 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24663 /* 67765 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24664 /* 67768 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24665 /* 67772 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24666 /* 67776 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24667 /* 67780 */ // (intrinsic_wo_chain:{ *:[i32] } 3778:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec) => (MVE_VMAXAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
24668 /* 67780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs16),
24669 /* 67783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
24670 /* 67785 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
24671 /* 67787 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
24672 /* 67789 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24673 /* 67792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24674 /* 67798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24675 /* 67804 */ GIR_RootConstrainSelectedInstOperands,
24676 /* 67805 */ // GIR_Coverage, 3529,
24677 /* 67805 */ GIR_EraseRootFromParent_Done,
24678 /* 67806 */ // Label 1439: @67806
24679 /* 67806 */ GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(67866), // Rule ID 3531 //
24680 /* 67811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24681 /* 67814 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxav),
24682 /* 67819 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
24683 /* 67822 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
24684 /* 67825 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24685 /* 67828 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24686 /* 67832 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
24687 /* 67836 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24688 /* 67840 */ // (intrinsic_wo_chain:{ *:[i32] } 3778:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec) => (MVE_VMAXAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
24689 /* 67840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAVs32),
24690 /* 67843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
24691 /* 67845 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
24692 /* 67847 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
24693 /* 67849 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24694 /* 67852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24695 /* 67858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24696 /* 67864 */ GIR_RootConstrainSelectedInstOperands,
24697 /* 67865 */ // GIR_Coverage, 3531,
24698 /* 67865 */ GIR_EraseRootFromParent_Done,
24699 /* 67866 */ // Label 1440: @67866
24700 /* 67866 */ GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(67941), // Rule ID 3638 //
24701 /* 67871 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24702 /* 67874 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmaxnm),
24703 /* 67879 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24704 /* 67882 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24705 /* 67885 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24706 /* 67888 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24707 /* 67892 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24708 /* 67896 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24709 /* 67900 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3883:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
24710 /* 67900 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24711 /* 67903 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24712 /* 67907 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24713 /* 67912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16),
24714 /* 67915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24715 /* 67917 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24716 /* 67919 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24717 /* 67921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24718 /* 67924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24719 /* 67930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24720 /* 67936 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24721 /* 67939 */ GIR_RootConstrainSelectedInstOperands,
24722 /* 67940 */ // GIR_Coverage, 3638,
24723 /* 67940 */ GIR_EraseRootFromParent_Done,
24724 /* 67941 */ // Label 1441: @67941
24725 /* 67941 */ GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(68016), // Rule ID 3643 //
24726 /* 67946 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24727 /* 67949 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm),
24728 /* 67954 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24729 /* 67957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24730 /* 67960 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24731 /* 67963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24732 /* 67967 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24733 /* 67971 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24734 /* 67975 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3886:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
24735 /* 67975 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24736 /* 67978 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24737 /* 67982 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24738 /* 67987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32),
24739 /* 67990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24740 /* 67992 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24741 /* 67994 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24742 /* 67996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24743 /* 67999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24744 /* 68005 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24745 /* 68011 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24746 /* 68014 */ GIR_RootConstrainSelectedInstOperands,
24747 /* 68015 */ // GIR_Coverage, 3643,
24748 /* 68015 */ GIR_EraseRootFromParent_Done,
24749 /* 68016 */ // Label 1442: @68016
24750 /* 68016 */ GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(68091), // Rule ID 3648 //
24751 /* 68021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24752 /* 68024 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vminnm),
24753 /* 68029 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24754 /* 68032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24755 /* 68035 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24756 /* 68038 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24757 /* 68042 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24758 /* 68046 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24759 /* 68050 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3886:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
24760 /* 68050 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24761 /* 68053 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24762 /* 68057 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24763 /* 68062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16),
24764 /* 68065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24765 /* 68067 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24766 /* 68069 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24767 /* 68071 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24768 /* 68074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24769 /* 68080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24770 /* 68086 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24771 /* 68089 */ GIR_RootConstrainSelectedInstOperands,
24772 /* 68090 */ // GIR_Coverage, 3648,
24773 /* 68090 */ GIR_EraseRootFromParent_Done,
24774 /* 68091 */ // Label 1443: @68091
24775 /* 68091 */ GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(68166), // Rule ID 3828 //
24776 /* 68096 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24777 /* 68099 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh),
24778 /* 68104 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
24779 /* 68107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24780 /* 68110 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24781 /* 68113 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24782 /* 68117 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24783 /* 68121 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24784 /* 68125 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3906:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24785 /* 68125 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24786 /* 68128 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24787 /* 68132 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24788 /* 68137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi8),
24789 /* 68140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24790 /* 68142 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24791 /* 68144 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24792 /* 68146 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24793 /* 68149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24794 /* 68155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24795 /* 68161 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24796 /* 68164 */ GIR_RootConstrainSelectedInstOperands,
24797 /* 68165 */ // GIR_Coverage, 3828,
24798 /* 68165 */ GIR_EraseRootFromParent_Done,
24799 /* 68166 */ // Label 1444: @68166
24800 /* 68166 */ GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(68241), // Rule ID 3835 //
24801 /* 68171 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24802 /* 68174 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh),
24803 /* 68179 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24804 /* 68182 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24805 /* 68185 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24806 /* 68188 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24807 /* 68192 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24808 /* 68196 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24809 /* 68200 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3906:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24810 /* 68200 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24811 /* 68203 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24812 /* 68207 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24813 /* 68212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi16),
24814 /* 68215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24815 /* 68217 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24816 /* 68219 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24817 /* 68221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24818 /* 68224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24819 /* 68230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24820 /* 68236 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24821 /* 68239 */ GIR_RootConstrainSelectedInstOperands,
24822 /* 68240 */ // GIR_Coverage, 3835,
24823 /* 68240 */ GIR_EraseRootFromParent_Done,
24824 /* 68241 */ // Label 1445: @68241
24825 /* 68241 */ GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(68316), // Rule ID 3839 //
24826 /* 68246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24827 /* 68249 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmulh),
24828 /* 68254 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24829 /* 68257 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24830 /* 68260 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24831 /* 68263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24832 /* 68267 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24833 /* 68271 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24834 /* 68275 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3906:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24835 /* 68275 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24836 /* 68278 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24837 /* 68282 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24838 /* 68287 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULHi32),
24839 /* 68290 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24840 /* 68292 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24841 /* 68294 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24842 /* 68296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24843 /* 68299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24844 /* 68305 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24845 /* 68311 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24846 /* 68314 */ GIR_RootConstrainSelectedInstOperands,
24847 /* 68315 */ // GIR_Coverage, 3839,
24848 /* 68315 */ GIR_EraseRootFromParent_Done,
24849 /* 68316 */ // Label 1446: @68316
24850 /* 68316 */ GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(68391), // Rule ID 3841 //
24851 /* 68321 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24852 /* 68324 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh),
24853 /* 68329 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
24854 /* 68332 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
24855 /* 68335 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
24856 /* 68338 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24857 /* 68342 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24858 /* 68346 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24859 /* 68350 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3915:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQRDMULHi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
24860 /* 68350 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24861 /* 68353 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24862 /* 68357 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24863 /* 68362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi8),
24864 /* 68365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24865 /* 68367 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24866 /* 68369 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24867 /* 68371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24868 /* 68374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24869 /* 68380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24870 /* 68386 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24871 /* 68389 */ GIR_RootConstrainSelectedInstOperands,
24872 /* 68390 */ // GIR_Coverage, 3841,
24873 /* 68390 */ GIR_EraseRootFromParent_Done,
24874 /* 68391 */ // Label 1447: @68391
24875 /* 68391 */ GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(68466), // Rule ID 3843 //
24876 /* 68396 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24877 /* 68399 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh),
24878 /* 68404 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24879 /* 68407 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24880 /* 68410 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24881 /* 68413 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24882 /* 68417 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24883 /* 68421 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24884 /* 68425 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3915:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQRDMULHi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
24885 /* 68425 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24886 /* 68428 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24887 /* 68432 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24888 /* 68437 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi16),
24889 /* 68440 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24890 /* 68442 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24891 /* 68444 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24892 /* 68446 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24893 /* 68449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24894 /* 68455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24895 /* 68461 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24896 /* 68464 */ GIR_RootConstrainSelectedInstOperands,
24897 /* 68465 */ // GIR_Coverage, 3843,
24898 /* 68465 */ GIR_EraseRootFromParent_Done,
24899 /* 68466 */ // Label 1448: @68466
24900 /* 68466 */ GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(68541), // Rule ID 3845 //
24901 /* 68471 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
24902 /* 68474 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmulh),
24903 /* 68479 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24904 /* 68482 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24905 /* 68485 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24906 /* 68488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24907 /* 68492 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24908 /* 68496 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24909 /* 68500 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3915:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQRDMULHi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
24910 /* 68500 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24911 /* 68503 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24912 /* 68507 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24913 /* 68512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMULHi32),
24914 /* 68515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24915 /* 68517 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24916 /* 68519 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24917 /* 68521 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24918 /* 68524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24919 /* 68530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24920 /* 68536 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24921 /* 68539 */ GIR_RootConstrainSelectedInstOperands,
24922 /* 68540 */ // GIR_Coverage, 3845,
24923 /* 68540 */ GIR_EraseRootFromParent_Done,
24924 /* 68541 */ // Label 1449: @68541
24925 /* 68541 */ GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(68616), // Rule ID 4359 //
24926 /* 68546 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24927 /* 68549 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmul),
24928 /* 68554 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24929 /* 68557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24930 /* 68560 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24931 /* 68563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24932 /* 68567 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24933 /* 68571 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24934 /* 68575 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3896:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
24935 /* 68575 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24936 /* 68578 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24937 /* 68582 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24938 /* 68587 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32),
24939 /* 68590 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24940 /* 68592 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24941 /* 68594 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24942 /* 68596 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24943 /* 68599 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24944 /* 68605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24945 /* 68611 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24946 /* 68614 */ GIR_RootConstrainSelectedInstOperands,
24947 /* 68615 */ // GIR_Coverage, 4359,
24948 /* 68615 */ GIR_EraseRootFromParent_Done,
24949 /* 68616 */ // Label 1450: @68616
24950 /* 68616 */ GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(68691), // Rule ID 4366 //
24951 /* 68621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24952 /* 68624 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmul),
24953 /* 68629 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
24954 /* 68632 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
24955 /* 68635 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
24956 /* 68638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24957 /* 68642 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24958 /* 68646 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24959 /* 68650 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3896:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
24960 /* 68650 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24961 /* 68653 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24962 /* 68657 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24963 /* 68662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16),
24964 /* 68665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24965 /* 68667 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24966 /* 68669 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24967 /* 68671 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24968 /* 68674 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24969 /* 68680 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24970 /* 68686 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24971 /* 68689 */ GIR_RootConstrainSelectedInstOperands,
24972 /* 68690 */ // GIR_Coverage, 4366,
24973 /* 68690 */ GIR_EraseRootFromParent_Done,
24974 /* 68691 */ // Label 1451: @68691
24975 /* 68691 */ GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(68766), // Rule ID 4399 //
24976 /* 68696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
24977 /* 68699 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vadd),
24978 /* 68704 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
24979 /* 68707 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
24980 /* 68710 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
24981 /* 68713 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24982 /* 68717 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24983 /* 68721 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
24984 /* 68725 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3833:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
24985 /* 68725 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
24986 /* 68728 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
24987 /* 68732 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
24988 /* 68737 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32),
24989 /* 68740 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
24990 /* 68742 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
24991 /* 68744 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
24992 /* 68746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
24993 /* 68749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24994 /* 68755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
24995 /* 68761 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
24996 /* 68764 */ GIR_RootConstrainSelectedInstOperands,
24997 /* 68765 */ // GIR_Coverage, 4399,
24998 /* 68765 */ GIR_EraseRootFromParent_Done,
24999 /* 68766 */ // Label 1452: @68766
25000 /* 68766 */ GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(68841), // Rule ID 4406 //
25001 /* 68771 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25002 /* 68774 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vadd),
25003 /* 68779 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25004 /* 68782 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25005 /* 68785 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25006 /* 68788 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25007 /* 68792 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25008 /* 68796 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25009 /* 68800 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3833:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
25010 /* 68800 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25011 /* 68803 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25012 /* 68807 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25013 /* 68812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16),
25014 /* 68815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25015 /* 68817 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25016 /* 68819 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25017 /* 68821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25018 /* 68824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25019 /* 68830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25020 /* 68836 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25021 /* 68839 */ GIR_RootConstrainSelectedInstOperands,
25022 /* 68840 */ // GIR_Coverage, 4406,
25023 /* 68840 */ GIR_EraseRootFromParent_Done,
25024 /* 68841 */ // Label 1453: @68841
25025 /* 68841 */ GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(68916), // Rule ID 4413 //
25026 /* 68846 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25027 /* 68849 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsub),
25028 /* 68854 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25029 /* 68857 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25030 /* 68860 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25031 /* 68863 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25032 /* 68867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25033 /* 68871 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25034 /* 68875 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3964:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
25035 /* 68875 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25036 /* 68878 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25037 /* 68882 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25038 /* 68887 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32),
25039 /* 68890 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25040 /* 68892 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25041 /* 68894 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25042 /* 68896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25043 /* 68899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25044 /* 68905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25045 /* 68911 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25046 /* 68914 */ GIR_RootConstrainSelectedInstOperands,
25047 /* 68915 */ // GIR_Coverage, 4413,
25048 /* 68915 */ GIR_EraseRootFromParent_Done,
25049 /* 68916 */ // Label 1454: @68916
25050 /* 68916 */ GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(68991), // Rule ID 4420 //
25051 /* 68921 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25052 /* 68924 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsub),
25053 /* 68929 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25054 /* 68932 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25055 /* 68935 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25056 /* 68938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25057 /* 68942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25058 /* 68946 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25059 /* 68950 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3964:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
25060 /* 68950 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25061 /* 68953 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25062 /* 68957 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25063 /* 68962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16),
25064 /* 68965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25065 /* 68967 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
25066 /* 68969 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
25067 /* 68971 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25068 /* 68974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25069 /* 68980 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25070 /* 68986 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25071 /* 68989 */ GIR_RootConstrainSelectedInstOperands,
25072 /* 68990 */ // GIR_Coverage, 4420,
25073 /* 68990 */ GIR_EraseRootFromParent_Done,
25074 /* 68991 */ // Label 1455: @68991
25075 /* 68991 */ GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(69054), // Rule ID 4544 //
25076 /* 68996 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25077 /* 68999 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_eq),
25078 /* 69004 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
25079 /* 69007 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25080 /* 69010 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25081 /* 69013 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25082 /* 69017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25083 /* 69021 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25084 /* 69025 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3765:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 0:{ *:[i32] })
25085 /* 69025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
25086 /* 69028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25087 /* 69030 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25088 /* 69032 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25089 /* 69034 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25090 /* 69037 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25091 /* 69040 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25092 /* 69046 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25093 /* 69052 */ GIR_RootConstrainSelectedInstOperands,
25094 /* 69053 */ // GIR_Coverage, 4544,
25095 /* 69053 */ GIR_EraseRootFromParent_Done,
25096 /* 69054 */ // Label 1456: @69054
25097 /* 69054 */ GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(69117), // Rule ID 4546 //
25098 /* 69059 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25099 /* 69062 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_eq),
25100 /* 69067 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
25101 /* 69070 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25102 /* 69073 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25103 /* 69076 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25104 /* 69080 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25105 /* 69084 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25106 /* 69088 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3765:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 0:{ *:[i32] })
25107 /* 69088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
25108 /* 69091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25109 /* 69093 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25110 /* 69095 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25111 /* 69097 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25112 /* 69100 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25113 /* 69103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25114 /* 69109 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25115 /* 69115 */ GIR_RootConstrainSelectedInstOperands,
25116 /* 69116 */ // GIR_Coverage, 4546,
25117 /* 69116 */ GIR_EraseRootFromParent_Done,
25118 /* 69117 */ // Label 1457: @69117
25119 /* 69117 */ GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(69180), // Rule ID 4633 //
25120 /* 69122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25121 /* 69125 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ne),
25122 /* 69130 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
25123 /* 69133 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25124 /* 69136 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25125 /* 69139 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25126 /* 69143 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25127 /* 69147 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25128 /* 69151 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3770:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 1:{ *:[i32] })
25129 /* 69151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
25130 /* 69154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25131 /* 69156 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25132 /* 69158 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25133 /* 69160 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
25134 /* 69163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25135 /* 69166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25136 /* 69172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25137 /* 69178 */ GIR_RootConstrainSelectedInstOperands,
25138 /* 69179 */ // GIR_Coverage, 4633,
25139 /* 69179 */ GIR_EraseRootFromParent_Done,
25140 /* 69180 */ // Label 1458: @69180
25141 /* 69180 */ GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(69243), // Rule ID 4635 //
25142 /* 69185 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25143 /* 69188 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ne),
25144 /* 69193 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
25145 /* 69196 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25146 /* 69199 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25147 /* 69202 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25148 /* 69206 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25149 /* 69210 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25150 /* 69214 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3770:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 1:{ *:[i32] })
25151 /* 69214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
25152 /* 69217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25153 /* 69219 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25154 /* 69221 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25155 /* 69223 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
25156 /* 69226 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25157 /* 69229 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25158 /* 69235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25159 /* 69241 */ GIR_RootConstrainSelectedInstOperands,
25160 /* 69242 */ // GIR_Coverage, 4635,
25161 /* 69242 */ GIR_EraseRootFromParent_Done,
25162 /* 69243 */ // Label 1459: @69243
25163 /* 69243 */ GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(69306), // Rule ID 4649 //
25164 /* 69248 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25165 /* 69251 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ge),
25166 /* 69256 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
25167 /* 69259 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25168 /* 69262 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25169 /* 69265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25170 /* 69269 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25171 /* 69273 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25172 /* 69277 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3766:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 10:{ *:[i32] })
25173 /* 69277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
25174 /* 69280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25175 /* 69282 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25176 /* 69284 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25177 /* 69286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/10,
25178 /* 69289 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25179 /* 69292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25180 /* 69298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25181 /* 69304 */ GIR_RootConstrainSelectedInstOperands,
25182 /* 69305 */ // GIR_Coverage, 4649,
25183 /* 69305 */ GIR_EraseRootFromParent_Done,
25184 /* 69306 */ // Label 1460: @69306
25185 /* 69306 */ GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(69369), // Rule ID 4651 //
25186 /* 69311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25187 /* 69314 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_ge),
25188 /* 69319 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
25189 /* 69322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25190 /* 69325 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25191 /* 69328 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25192 /* 69332 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25193 /* 69336 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25194 /* 69340 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3766:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 10:{ *:[i32] })
25195 /* 69340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
25196 /* 69343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25197 /* 69345 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25198 /* 69347 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25199 /* 69349 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/10,
25200 /* 69352 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25201 /* 69355 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25202 /* 69361 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25203 /* 69367 */ GIR_RootConstrainSelectedInstOperands,
25204 /* 69368 */ // GIR_Coverage, 4651,
25205 /* 69368 */ GIR_EraseRootFromParent_Done,
25206 /* 69369 */ // Label 1461: @69369
25207 /* 69369 */ GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(69432), // Rule ID 4665 //
25208 /* 69374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25209 /* 69377 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_lt),
25210 /* 69382 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
25211 /* 69385 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25212 /* 69388 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25213 /* 69391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25214 /* 69395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25215 /* 69399 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25216 /* 69403 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3769:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 11:{ *:[i32] })
25217 /* 69403 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
25218 /* 69406 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25219 /* 69408 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25220 /* 69410 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25221 /* 69412 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/11,
25222 /* 69415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25223 /* 69418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25224 /* 69424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25225 /* 69430 */ GIR_RootConstrainSelectedInstOperands,
25226 /* 69431 */ // GIR_Coverage, 4665,
25227 /* 69431 */ GIR_EraseRootFromParent_Done,
25228 /* 69432 */ // Label 1462: @69432
25229 /* 69432 */ GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(69495), // Rule ID 4667 //
25230 /* 69437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25231 /* 69440 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_lt),
25232 /* 69445 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
25233 /* 69448 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25234 /* 69451 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25235 /* 69454 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25236 /* 69458 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25237 /* 69462 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25238 /* 69466 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3769:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 11:{ *:[i32] })
25239 /* 69466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
25240 /* 69469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25241 /* 69471 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25242 /* 69473 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25243 /* 69475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/11,
25244 /* 69478 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25245 /* 69481 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25246 /* 69487 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25247 /* 69493 */ GIR_RootConstrainSelectedInstOperands,
25248 /* 69494 */ // GIR_Coverage, 4667,
25249 /* 69494 */ GIR_EraseRootFromParent_Done,
25250 /* 69495 */ // Label 1463: @69495
25251 /* 69495 */ GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(69558), // Rule ID 4681 //
25252 /* 69500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25253 /* 69503 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_gt),
25254 /* 69508 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
25255 /* 69511 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25256 /* 69514 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25257 /* 69517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25258 /* 69521 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25259 /* 69525 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25260 /* 69529 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3767:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 12:{ *:[i32] })
25261 /* 69529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
25262 /* 69532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25263 /* 69534 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25264 /* 69536 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25265 /* 69538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/12,
25266 /* 69541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25267 /* 69544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25268 /* 69550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25269 /* 69556 */ GIR_RootConstrainSelectedInstOperands,
25270 /* 69557 */ // GIR_Coverage, 4681,
25271 /* 69557 */ GIR_EraseRootFromParent_Done,
25272 /* 69558 */ // Label 1464: @69558
25273 /* 69558 */ GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(69621), // Rule ID 4683 //
25274 /* 69563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25275 /* 69566 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_gt),
25276 /* 69571 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
25277 /* 69574 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25278 /* 69577 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25279 /* 69580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25280 /* 69584 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25281 /* 69588 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25282 /* 69592 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3767:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 12:{ *:[i32] })
25283 /* 69592 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
25284 /* 69595 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25285 /* 69597 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25286 /* 69599 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25287 /* 69601 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/12,
25288 /* 69604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25289 /* 69607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25290 /* 69613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25291 /* 69619 */ GIR_RootConstrainSelectedInstOperands,
25292 /* 69620 */ // GIR_Coverage, 4683,
25293 /* 69620 */ GIR_EraseRootFromParent_Done,
25294 /* 69621 */ // Label 1465: @69621
25295 /* 69621 */ GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(69684), // Rule ID 4697 //
25296 /* 69626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25297 /* 69629 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_le),
25298 /* 69634 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s1,
25299 /* 69637 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25300 /* 69640 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25301 /* 69643 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25302 /* 69647 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25303 /* 69651 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25304 /* 69655 */ // (intrinsic_wo_chain:{ *:[v8i1] } 3768:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2) => (MVE_VCMPf16:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, MQPR:{ *:[v8f16] }:$v2, 13:{ *:[i32] })
25305 /* 69655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16),
25306 /* 69658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25307 /* 69660 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25308 /* 69662 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25309 /* 69664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/13,
25310 /* 69667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25311 /* 69670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25312 /* 69676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25313 /* 69682 */ GIR_RootConstrainSelectedInstOperands,
25314 /* 69683 */ // GIR_Coverage, 4697,
25315 /* 69683 */ GIR_EraseRootFromParent_Done,
25316 /* 69684 */ // Label 1466: @69684
25317 /* 69684 */ GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(69747), // Rule ID 4699 //
25318 /* 69689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25319 /* 69692 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_cmp_le),
25320 /* 69697 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s1,
25321 /* 69700 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25322 /* 69703 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25323 /* 69706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
25324 /* 69710 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25325 /* 69714 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25326 /* 69718 */ // (intrinsic_wo_chain:{ *:[v4i1] } 3768:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2) => (MVE_VCMPf32:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, MQPR:{ *:[v4f32] }:$v2, 13:{ *:[i32] })
25327 /* 69718 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32),
25328 /* 69721 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
25329 /* 69723 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
25330 /* 69725 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
25331 /* 69727 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/13,
25332 /* 69730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25333 /* 69733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25334 /* 69739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25335 /* 69745 */ GIR_RootConstrainSelectedInstOperands,
25336 /* 69746 */ // GIR_Coverage, 4699,
25337 /* 69746 */ GIR_EraseRootFromParent_Done,
25338 /* 69747 */ // Label 1467: @69747
25339 /* 69747 */ GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(69822), // Rule ID 5221 //
25340 /* 69752 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25341 /* 69755 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
25342 /* 69760 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25343 /* 69763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25344 /* 69766 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25345 /* 69769 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25346 /* 69773 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25347 /* 69777 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25348 /* 69781 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3834:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, rGPR:{ *:[i32] }:$Rm)
25349 /* 69781 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25350 /* 69784 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25351 /* 69788 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25352 /* 69793 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8),
25353 /* 69796 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25354 /* 69798 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
25355 /* 69800 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
25356 /* 69802 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25357 /* 69805 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25358 /* 69811 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25359 /* 69817 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25360 /* 69820 */ GIR_RootConstrainSelectedInstOperands,
25361 /* 69821 */ // GIR_Coverage, 5221,
25362 /* 69821 */ GIR_EraseRootFromParent_Done,
25363 /* 69822 */ // Label 1468: @69822
25364 /* 69822 */ GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(69897), // Rule ID 5226 //
25365 /* 69827 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25366 /* 69830 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
25367 /* 69835 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25368 /* 69838 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25369 /* 69841 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25370 /* 69844 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25371 /* 69848 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25372 /* 69852 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25373 /* 69856 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3834:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, rGPR:{ *:[i32] }:$Rm)
25374 /* 69856 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25375 /* 69859 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25376 /* 69863 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25377 /* 69868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16),
25378 /* 69871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25379 /* 69873 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
25380 /* 69875 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
25381 /* 69877 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25382 /* 69880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25383 /* 69886 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25384 /* 69892 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25385 /* 69895 */ GIR_RootConstrainSelectedInstOperands,
25386 /* 69896 */ // GIR_Coverage, 5226,
25387 /* 69896 */ GIR_EraseRootFromParent_Done,
25388 /* 69897 */ // Label 1469: @69897
25389 /* 69897 */ GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(69972), // Rule ID 5228 //
25390 /* 69902 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
25391 /* 69905 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
25392 /* 69910 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25393 /* 69913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25394 /* 69916 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25395 /* 69919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25396 /* 69923 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25397 /* 69927 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25398 /* 69931 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3834:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, rGPR:{ *:[i32] }:$Rm)
25399 /* 69931 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25400 /* 69934 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25401 /* 69938 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25402 /* 69943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32),
25403 /* 69946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25404 /* 69948 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
25405 /* 69950 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
25406 /* 69952 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25407 /* 69955 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25408 /* 69961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25409 /* 69967 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25410 /* 69970 */ GIR_RootConstrainSelectedInstOperands,
25411 /* 69971 */ // GIR_Coverage, 5228,
25412 /* 69971 */ GIR_EraseRootFromParent_Done,
25413 /* 69972 */ // Label 1470: @69972
25414 /* 69972 */ GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(70047), // Rule ID 5230 //
25415 /* 69977 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25416 /* 69980 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
25417 /* 69985 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25418 /* 69988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25419 /* 69991 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25420 /* 69994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25421 /* 69998 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25422 /* 70002 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25423 /* 70006 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3834:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, rGPR:{ *:[i32] }:$Rm)
25424 /* 70006 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25425 /* 70009 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25426 /* 70013 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25427 /* 70018 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16),
25428 /* 70021 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25429 /* 70023 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
25430 /* 70025 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
25431 /* 70027 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25432 /* 70030 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25433 /* 70036 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25434 /* 70042 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25435 /* 70045 */ GIR_RootConstrainSelectedInstOperands,
25436 /* 70046 */ // GIR_Coverage, 5230,
25437 /* 70046 */ GIR_EraseRootFromParent_Done,
25438 /* 70047 */ // Label 1471: @70047
25439 /* 70047 */ GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(70122), // Rule ID 5232 //
25440 /* 70052 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25441 /* 70055 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vbrsr),
25442 /* 70060 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25443 /* 70063 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25444 /* 70066 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25445 /* 70069 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25446 /* 70073 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25447 /* 70077 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
25448 /* 70081 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3834:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm) => (MVE_VBRSR32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, rGPR:{ *:[i32] }:$Rm)
25449 /* 70081 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25450 /* 70084 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25451 /* 70088 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25452 /* 70093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32),
25453 /* 70096 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25454 /* 70098 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
25455 /* 70100 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
25456 /* 70102 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25457 /* 70105 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25458 /* 70111 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25459 /* 70117 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25460 /* 70120 */ GIR_RootConstrainSelectedInstOperands,
25461 /* 70121 */ // GIR_Coverage, 5232,
25462 /* 70121 */ GIR_EraseRootFromParent_Done,
25463 /* 70122 */ // Label 1472: @70122
25464 /* 70122 */ GIM_Reject,
25465 /* 70123 */ // Label 1083: @70123
25466 /* 70123 */ GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(81528),
25467 /* 70128 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
25468 /* 70131 */ GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(70221), // Rule ID 4274 //
25469 /* 70136 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
25470 /* 70141 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25471 /* 70144 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25472 /* 70147 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25473 /* 70150 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25474 /* 70153 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25475 /* 70157 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25476 /* 70161 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25477 /* 70165 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25478 /* 70169 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
25479 /* 70173 */ // MIs[1] Operand 1
25480 /* 70173 */ // No operand predicates
25481 /* 70173 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25482 /* 70177 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25483 /* 70179 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3916:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
25484 /* 70179 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25485 /* 70182 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25486 /* 70186 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25487 /* 70191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms8),
25488 /* 70194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25489 /* 70196 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25490 /* 70198 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25491 /* 70201 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25492 /* 70204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25493 /* 70210 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25494 /* 70216 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25495 /* 70219 */ GIR_RootConstrainSelectedInstOperands,
25496 /* 70220 */ // GIR_Coverage, 4274,
25497 /* 70220 */ GIR_EraseRootFromParent_Done,
25498 /* 70221 */ // Label 1474: @70221
25499 /* 70221 */ GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(70311), // Rule ID 4276 //
25500 /* 70226 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
25501 /* 70231 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25502 /* 70234 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25503 /* 70237 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25504 /* 70240 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25505 /* 70243 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25506 /* 70247 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25507 /* 70251 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25508 /* 70255 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25509 /* 70259 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
25510 /* 70263 */ // MIs[1] Operand 1
25511 /* 70263 */ // No operand predicates
25512 /* 70263 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25513 /* 70267 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25514 /* 70269 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3916:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
25515 /* 70269 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25516 /* 70272 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25517 /* 70276 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25518 /* 70281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu8),
25519 /* 70284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25520 /* 70286 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25521 /* 70288 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25522 /* 70291 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25523 /* 70294 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25524 /* 70300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25525 /* 70306 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25526 /* 70309 */ GIR_RootConstrainSelectedInstOperands,
25527 /* 70310 */ // GIR_Coverage, 4276,
25528 /* 70310 */ GIR_EraseRootFromParent_Done,
25529 /* 70311 */ // Label 1475: @70311
25530 /* 70311 */ GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(70401), // Rule ID 4278 //
25531 /* 70316 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
25532 /* 70321 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25533 /* 70324 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25534 /* 70327 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25535 /* 70330 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25536 /* 70333 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25537 /* 70337 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25538 /* 70341 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25539 /* 70345 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25540 /* 70349 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
25541 /* 70353 */ // MIs[1] Operand 1
25542 /* 70353 */ // No operand predicates
25543 /* 70353 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25544 /* 70357 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25545 /* 70359 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3916:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
25546 /* 70359 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25547 /* 70362 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25548 /* 70366 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25549 /* 70371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms16),
25550 /* 70374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25551 /* 70376 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25552 /* 70378 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25553 /* 70381 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25554 /* 70384 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25555 /* 70390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25556 /* 70396 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25557 /* 70399 */ GIR_RootConstrainSelectedInstOperands,
25558 /* 70400 */ // GIR_Coverage, 4278,
25559 /* 70400 */ GIR_EraseRootFromParent_Done,
25560 /* 70401 */ // Label 1476: @70401
25561 /* 70401 */ GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(70491), // Rule ID 4280 //
25562 /* 70406 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
25563 /* 70411 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25564 /* 70414 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25565 /* 70417 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25566 /* 70420 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25567 /* 70423 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25568 /* 70427 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25569 /* 70431 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25570 /* 70435 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25571 /* 70439 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
25572 /* 70443 */ // MIs[1] Operand 1
25573 /* 70443 */ // No operand predicates
25574 /* 70443 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25575 /* 70447 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25576 /* 70449 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3916:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
25577 /* 70449 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25578 /* 70452 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25579 /* 70456 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25580 /* 70461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu16),
25581 /* 70464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25582 /* 70466 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25583 /* 70468 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25584 /* 70471 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25585 /* 70474 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25586 /* 70480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25587 /* 70486 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25588 /* 70489 */ GIR_RootConstrainSelectedInstOperands,
25589 /* 70490 */ // GIR_Coverage, 4280,
25590 /* 70490 */ GIR_EraseRootFromParent_Done,
25591 /* 70491 */ // Label 1477: @70491
25592 /* 70491 */ GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(70581), // Rule ID 4282 //
25593 /* 70496 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
25594 /* 70501 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25595 /* 70504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25596 /* 70507 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25597 /* 70510 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25598 /* 70513 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25599 /* 70517 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25600 /* 70521 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25601 /* 70525 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25602 /* 70529 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
25603 /* 70533 */ // MIs[1] Operand 1
25604 /* 70533 */ // No operand predicates
25605 /* 70533 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25606 /* 70537 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25607 /* 70539 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3916:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 0:{ *:[i32] }) => (MVE_VQSHLimms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
25608 /* 70539 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25609 /* 70542 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25610 /* 70546 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25611 /* 70551 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimms32),
25612 /* 70554 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25613 /* 70556 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25614 /* 70558 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25615 /* 70561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25616 /* 70564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25617 /* 70570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25618 /* 70576 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25619 /* 70579 */ GIR_RootConstrainSelectedInstOperands,
25620 /* 70580 */ // GIR_Coverage, 4282,
25621 /* 70580 */ GIR_EraseRootFromParent_Done,
25622 /* 70581 */ // Label 1478: @70581
25623 /* 70581 */ GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(70671), // Rule ID 4284 //
25624 /* 70586 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqshl_imm),
25625 /* 70591 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25626 /* 70594 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25627 /* 70597 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25628 /* 70600 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25629 /* 70603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25630 /* 70607 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25631 /* 70611 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25632 /* 70615 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25633 /* 70619 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
25634 /* 70623 */ // MIs[1] Operand 1
25635 /* 70623 */ // No operand predicates
25636 /* 70623 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25637 /* 70627 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25638 /* 70629 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3916:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm, 1:{ *:[i32] }) => (MVE_VQSHLimmu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
25639 /* 70629 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25640 /* 70632 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25641 /* 70636 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25642 /* 70641 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHLimmu32),
25643 /* 70644 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25644 /* 70646 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25645 /* 70648 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25646 /* 70651 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25647 /* 70654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25648 /* 70660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25649 /* 70666 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25650 /* 70669 */ GIR_RootConstrainSelectedInstOperands,
25651 /* 70670 */ // GIR_Coverage, 4284,
25652 /* 70670 */ GIR_EraseRootFromParent_Done,
25653 /* 70671 */ // Label 1479: @70671
25654 /* 70671 */ GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(70761), // Rule ID 4292 //
25655 /* 70676 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
25656 /* 70681 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25657 /* 70684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25658 /* 70687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25659 /* 70690 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25660 /* 70693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25661 /* 70697 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25662 /* 70701 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25663 /* 70705 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25664 /* 70709 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
25665 /* 70713 */ // MIs[1] Operand 1
25666 /* 70713 */ // No operand predicates
25667 /* 70713 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25668 /* 70717 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25669 /* 70719 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3938:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
25670 /* 70719 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25671 /* 70722 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25672 /* 70726 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25673 /* 70731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms8),
25674 /* 70734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25675 /* 70736 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25676 /* 70738 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25677 /* 70741 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25678 /* 70744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25679 /* 70750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25680 /* 70756 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25681 /* 70759 */ GIR_RootConstrainSelectedInstOperands,
25682 /* 70760 */ // GIR_Coverage, 4292,
25683 /* 70760 */ GIR_EraseRootFromParent_Done,
25684 /* 70761 */ // Label 1480: @70761
25685 /* 70761 */ GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(70851), // Rule ID 4294 //
25686 /* 70766 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
25687 /* 70771 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
25688 /* 70774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
25689 /* 70777 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25690 /* 70780 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25691 /* 70783 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25692 /* 70787 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25693 /* 70791 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25694 /* 70795 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25695 /* 70799 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
25696 /* 70803 */ // MIs[1] Operand 1
25697 /* 70803 */ // No operand predicates
25698 /* 70803 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25699 /* 70807 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25700 /* 70809 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3938:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
25701 /* 70809 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25702 /* 70812 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25703 /* 70816 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25704 /* 70821 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu8),
25705 /* 70824 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25706 /* 70826 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25707 /* 70828 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25708 /* 70831 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25709 /* 70834 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25710 /* 70840 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25711 /* 70846 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25712 /* 70849 */ GIR_RootConstrainSelectedInstOperands,
25713 /* 70850 */ // GIR_Coverage, 4294,
25714 /* 70850 */ GIR_EraseRootFromParent_Done,
25715 /* 70851 */ // Label 1481: @70851
25716 /* 70851 */ GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(70941), // Rule ID 4296 //
25717 /* 70856 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
25718 /* 70861 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25719 /* 70864 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25720 /* 70867 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25721 /* 70870 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25722 /* 70873 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25723 /* 70877 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25724 /* 70881 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25725 /* 70885 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25726 /* 70889 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
25727 /* 70893 */ // MIs[1] Operand 1
25728 /* 70893 */ // No operand predicates
25729 /* 70893 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25730 /* 70897 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25731 /* 70899 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3938:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
25732 /* 70899 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25733 /* 70902 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25734 /* 70906 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25735 /* 70911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms16),
25736 /* 70914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25737 /* 70916 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25738 /* 70918 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25739 /* 70921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25740 /* 70924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25741 /* 70930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25742 /* 70936 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25743 /* 70939 */ GIR_RootConstrainSelectedInstOperands,
25744 /* 70940 */ // GIR_Coverage, 4296,
25745 /* 70940 */ GIR_EraseRootFromParent_Done,
25746 /* 70941 */ // Label 1482: @70941
25747 /* 70941 */ GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(71031), // Rule ID 4298 //
25748 /* 70946 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
25749 /* 70951 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25750 /* 70954 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
25751 /* 70957 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25752 /* 70960 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25753 /* 70963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25754 /* 70967 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25755 /* 70971 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25756 /* 70975 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25757 /* 70979 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
25758 /* 70983 */ // MIs[1] Operand 1
25759 /* 70983 */ // No operand predicates
25760 /* 70983 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25761 /* 70987 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25762 /* 70989 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3938:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
25763 /* 70989 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25764 /* 70992 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25765 /* 70996 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25766 /* 71001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu16),
25767 /* 71004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25768 /* 71006 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25769 /* 71008 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25770 /* 71011 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25771 /* 71014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25772 /* 71020 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25773 /* 71026 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25774 /* 71029 */ GIR_RootConstrainSelectedInstOperands,
25775 /* 71030 */ // GIR_Coverage, 4298,
25776 /* 71030 */ GIR_EraseRootFromParent_Done,
25777 /* 71031 */ // Label 1483: @71031
25778 /* 71031 */ GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(71121), // Rule ID 4300 //
25779 /* 71036 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
25780 /* 71041 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25781 /* 71044 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25782 /* 71047 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25783 /* 71050 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25784 /* 71053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25785 /* 71057 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25786 /* 71061 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25787 /* 71065 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25788 /* 71069 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32),
25789 /* 71073 */ // MIs[1] Operand 1
25790 /* 71073 */ // No operand predicates
25791 /* 71073 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
25792 /* 71077 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25793 /* 71079 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3938:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 0:{ *:[i32] }) => (MVE_VRSHR_imms32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
25794 /* 71079 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25795 /* 71082 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25796 /* 71086 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25797 /* 71091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_imms32),
25798 /* 71094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25799 /* 71096 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25800 /* 71098 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25801 /* 71101 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25802 /* 71104 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25803 /* 71110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25804 /* 71116 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25805 /* 71119 */ GIR_RootConstrainSelectedInstOperands,
25806 /* 71120 */ // GIR_Coverage, 4300,
25807 /* 71120 */ GIR_EraseRootFromParent_Done,
25808 /* 71121 */ // Label 1484: @71121
25809 /* 71121 */ GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(71211), // Rule ID 4302 //
25810 /* 71126 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrshr_imm),
25811 /* 71131 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25812 /* 71134 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
25813 /* 71137 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
25814 /* 71140 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25815 /* 71143 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25816 /* 71147 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25817 /* 71151 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
25818 /* 71155 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25819 /* 71159 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32),
25820 /* 71163 */ // MIs[1] Operand 1
25821 /* 71163 */ // No operand predicates
25822 /* 71163 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
25823 /* 71167 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25824 /* 71169 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3938:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm, 1:{ *:[i32] }) => (MVE_VRSHR_immu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
25825 /* 71169 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25826 /* 71172 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25827 /* 71176 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25828 /* 71181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHR_immu32),
25829 /* 71184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25830 /* 71186 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
25831 /* 71188 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
25832 /* 71191 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25833 /* 71194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25834 /* 71200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25835 /* 71206 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25836 /* 71209 */ GIR_RootConstrainSelectedInstOperands,
25837 /* 71210 */ // GIR_Coverage, 4302,
25838 /* 71210 */ GIR_EraseRootFromParent_Done,
25839 /* 71211 */ // Label 1485: @71211
25840 /* 71211 */ GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(71300), // Rule ID 4436 //
25841 /* 71216 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25842 /* 71219 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25843 /* 71224 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25844 /* 71227 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25845 /* 71230 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25846 /* 71233 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25847 /* 71236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25848 /* 71240 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
25849 /* 71244 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25850 /* 71248 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25851 /* 71252 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25852 /* 71256 */ // MIs[1] Operand 1
25853 /* 71256 */ // No operand predicates
25854 /* 71256 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25855 /* 71258 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3847:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16s16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)
25856 /* 71258 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25857 /* 71261 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25858 /* 71265 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25859 /* 71270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16_fix),
25860 /* 71273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25861 /* 71275 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25862 /* 71277 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25863 /* 71280 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25864 /* 71283 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25865 /* 71289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25866 /* 71295 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25867 /* 71298 */ GIR_RootConstrainSelectedInstOperands,
25868 /* 71299 */ // GIR_Coverage, 4436,
25869 /* 71299 */ GIR_EraseRootFromParent_Done,
25870 /* 71300 */ // Label 1486: @71300
25871 /* 71300 */ GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(71389), // Rule ID 4438 //
25872 /* 71305 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25873 /* 71308 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25874 /* 71313 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25875 /* 71316 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25876 /* 71319 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25877 /* 71322 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25878 /* 71325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25879 /* 71329 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
25880 /* 71333 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25881 /* 71337 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25882 /* 71341 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25883 /* 71345 */ // MIs[1] Operand 1
25884 /* 71345 */ // No operand predicates
25885 /* 71345 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25886 /* 71347 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3847:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)
25887 /* 71347 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25888 /* 71350 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25889 /* 71354 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25890 /* 71359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16_fix),
25891 /* 71362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25892 /* 71364 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25893 /* 71366 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25894 /* 71369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25895 /* 71372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25896 /* 71378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25897 /* 71384 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25898 /* 71387 */ GIR_RootConstrainSelectedInstOperands,
25899 /* 71388 */ // GIR_Coverage, 4438,
25900 /* 71388 */ GIR_EraseRootFromParent_Done,
25901 /* 71389 */ // Label 1487: @71389
25902 /* 71389 */ GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(71478), // Rule ID 4440 //
25903 /* 71394 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25904 /* 71397 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25905 /* 71402 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25906 /* 71405 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25907 /* 71408 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25908 /* 71411 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25909 /* 71414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25910 /* 71418 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
25911 /* 71422 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25912 /* 71426 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25913 /* 71430 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25914 /* 71434 */ // MIs[1] Operand 1
25915 /* 71434 */ // No operand predicates
25916 /* 71434 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25917 /* 71436 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3847:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf16u16_fix:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$scale)
25918 /* 71436 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25919 /* 71439 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25920 /* 71443 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25921 /* 71448 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16_fix),
25922 /* 71451 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25923 /* 71453 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25924 /* 71455 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25925 /* 71458 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25926 /* 71461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25927 /* 71467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25928 /* 71473 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25929 /* 71476 */ GIR_RootConstrainSelectedInstOperands,
25930 /* 71477 */ // GIR_Coverage, 4440,
25931 /* 71477 */ GIR_EraseRootFromParent_Done,
25932 /* 71478 */ // Label 1488: @71478
25933 /* 71478 */ GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(71567), // Rule ID 4442 //
25934 /* 71483 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25935 /* 71486 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25936 /* 71491 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
25937 /* 71494 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25938 /* 71497 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
25939 /* 71500 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25940 /* 71503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25941 /* 71507 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
25942 /* 71511 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25943 /* 71515 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25944 /* 71519 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25945 /* 71523 */ // MIs[1] Operand 1
25946 /* 71523 */ // No operand predicates
25947 /* 71523 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25948 /* 71525 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3847:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu16f16_fix:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$scale)
25949 /* 71525 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25950 /* 71528 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25951 /* 71532 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25952 /* 71537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16_fix),
25953 /* 71540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25954 /* 71542 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25955 /* 71544 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25956 /* 71547 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25957 /* 71550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25958 /* 71556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25959 /* 71562 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25960 /* 71565 */ GIR_RootConstrainSelectedInstOperands,
25961 /* 71566 */ // GIR_Coverage, 4442,
25962 /* 71566 */ GIR_EraseRootFromParent_Done,
25963 /* 71567 */ // Label 1489: @71567
25964 /* 71567 */ GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(71656), // Rule ID 4444 //
25965 /* 71572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25966 /* 71575 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25967 /* 71580 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25968 /* 71583 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
25969 /* 71586 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
25970 /* 71589 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
25971 /* 71592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25972 /* 71596 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
25973 /* 71600 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
25974 /* 71604 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
25975 /* 71608 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
25976 /* 71612 */ // MIs[1] Operand 1
25977 /* 71612 */ // No operand predicates
25978 /* 71612 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
25979 /* 71614 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3847:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32s32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)
25980 /* 71614 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
25981 /* 71617 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
25982 /* 71621 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
25983 /* 71626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32_fix),
25984 /* 71629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
25985 /* 71631 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
25986 /* 71633 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
25987 /* 71636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
25988 /* 71639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25989 /* 71645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
25990 /* 71651 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
25991 /* 71654 */ GIR_RootConstrainSelectedInstOperands,
25992 /* 71655 */ // GIR_Coverage, 4444,
25993 /* 71655 */ GIR_EraseRootFromParent_Done,
25994 /* 71656 */ // Label 1490: @71656
25995 /* 71656 */ GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(71745), // Rule ID 4446 //
25996 /* 71661 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
25997 /* 71664 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
25998 /* 71669 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
25999 /* 71672 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26000 /* 71675 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26001 /* 71678 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26002 /* 71681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26003 /* 71685 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
26004 /* 71689 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26005 /* 71693 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26006 /* 71697 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26007 /* 71701 */ // MIs[1] Operand 1
26008 /* 71701 */ // No operand predicates
26009 /* 71701 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26010 /* 71703 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3847:{ *:[iPTR] }, 0:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTs32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)
26011 /* 71703 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26012 /* 71706 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26013 /* 71710 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26014 /* 71715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32_fix),
26015 /* 71718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26016 /* 71720 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
26017 /* 71722 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
26018 /* 71725 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26019 /* 71728 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26020 /* 71734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26021 /* 71740 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26022 /* 71743 */ GIR_RootConstrainSelectedInstOperands,
26023 /* 71744 */ // GIR_Coverage, 4446,
26024 /* 71744 */ GIR_EraseRootFromParent_Done,
26025 /* 71745 */ // Label 1491: @71745
26026 /* 71745 */ GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(71834), // Rule ID 4448 //
26027 /* 71750 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
26028 /* 71753 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
26029 /* 71758 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26030 /* 71761 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26031 /* 71764 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26032 /* 71767 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26033 /* 71770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26034 /* 71774 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
26035 /* 71778 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26036 /* 71782 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26037 /* 71786 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26038 /* 71790 */ // MIs[1] Operand 1
26039 /* 71790 */ // No operand predicates
26040 /* 71790 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26041 /* 71792 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3847:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTf32u32_fix:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$scale)
26042 /* 71792 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26043 /* 71795 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26044 /* 71799 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26045 /* 71804 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32_fix),
26046 /* 71807 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26047 /* 71809 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
26048 /* 71811 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
26049 /* 71814 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26050 /* 71817 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26051 /* 71823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26052 /* 71829 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26053 /* 71832 */ GIR_RootConstrainSelectedInstOperands,
26054 /* 71833 */ // GIR_Coverage, 4448,
26055 /* 71833 */ GIR_EraseRootFromParent_Done,
26056 /* 71834 */ // Label 1492: @71834
26057 /* 71834 */ GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(71923), // Rule ID 4450 //
26058 /* 71839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
26059 /* 71842 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_fix),
26060 /* 71847 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26061 /* 71850 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26062 /* 71853 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26063 /* 71856 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26064 /* 71859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26065 /* 71863 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
26066 /* 71867 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26067 /* 71871 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
26068 /* 71875 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
26069 /* 71879 */ // MIs[1] Operand 1
26070 /* 71879 */ // No operand predicates
26071 /* 71879 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
26072 /* 71881 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3847:{ *:[iPTR] }, 1:{ *:[i32] }, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale) => (MVE_VCVTu32f32_fix:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$scale)
26073 /* 71881 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26074 /* 71884 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26075 /* 71888 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26076 /* 71893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32_fix),
26077 /* 71896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26078 /* 71898 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
26079 /* 71900 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // scale
26080 /* 71903 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26081 /* 71906 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26082 /* 71912 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26083 /* 71918 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26084 /* 71921 */ GIR_RootConstrainSelectedInstOperands,
26085 /* 71922 */ // GIR_Coverage, 4450,
26086 /* 71922 */ GIR_EraseRootFromParent_Done,
26087 /* 71923 */ // Label 1493: @71923
26088 /* 71923 */ GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(71990), // Rule ID 3473 //
26089 /* 71928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26090 /* 71931 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
26091 /* 71936 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26092 /* 71939 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26093 /* 71942 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26094 /* 71945 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26095 /* 71948 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26096 /* 71952 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26097 /* 71956 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26098 /* 71960 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26099 /* 71964 */ // (intrinsic_wo_chain:{ *:[i32] } 3793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
26100 /* 71964 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8),
26101 /* 71967 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26102 /* 71969 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26103 /* 71971 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26104 /* 71973 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26105 /* 71976 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26106 /* 71982 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26107 /* 71988 */ GIR_RootConstrainSelectedInstOperands,
26108 /* 71989 */ // GIR_Coverage, 3473,
26109 /* 71989 */ GIR_EraseRootFromParent_Done,
26110 /* 71990 */ // Label 1494: @71990
26111 /* 71990 */ GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(72057), // Rule ID 3475 //
26112 /* 71995 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26113 /* 71998 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
26114 /* 72003 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26115 /* 72006 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26116 /* 72009 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26117 /* 72012 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26118 /* 72015 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26119 /* 72019 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26120 /* 72023 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26121 /* 72027 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26122 /* 72031 */ // (intrinsic_wo_chain:{ *:[i32] } 3793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
26123 /* 72031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16),
26124 /* 72034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26125 /* 72036 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26126 /* 72038 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26127 /* 72040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26128 /* 72043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26129 /* 72049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26130 /* 72055 */ GIR_RootConstrainSelectedInstOperands,
26131 /* 72056 */ // GIR_Coverage, 3475,
26132 /* 72056 */ GIR_EraseRootFromParent_Done,
26133 /* 72057 */ // Label 1495: @72057
26134 /* 72057 */ GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(72124), // Rule ID 3477 //
26135 /* 72062 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26136 /* 72065 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
26137 /* 72070 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26138 /* 72073 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26139 /* 72076 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26140 /* 72079 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26141 /* 72082 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26142 /* 72086 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26143 /* 72090 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26144 /* 72094 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26145 /* 72098 */ // (intrinsic_wo_chain:{ *:[i32] } 3793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMINVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
26146 /* 72098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32),
26147 /* 72101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26148 /* 72103 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26149 /* 72105 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26150 /* 72107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26151 /* 72110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26152 /* 72116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26153 /* 72122 */ GIR_RootConstrainSelectedInstOperands,
26154 /* 72123 */ // GIR_Coverage, 3477,
26155 /* 72123 */ GIR_EraseRootFromParent_Done,
26156 /* 72124 */ // Label 1496: @72124
26157 /* 72124 */ GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(72191), // Rule ID 3479 //
26158 /* 72129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26159 /* 72132 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
26160 /* 72137 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26161 /* 72140 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26162 /* 72143 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26163 /* 72146 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26164 /* 72149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26165 /* 72153 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26166 /* 72157 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26167 /* 72161 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26168 /* 72165 */ // (intrinsic_wo_chain:{ *:[i32] } 3793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
26169 /* 72165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8),
26170 /* 72168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26171 /* 72170 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26172 /* 72172 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26173 /* 72174 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26174 /* 72177 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26175 /* 72183 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26176 /* 72189 */ GIR_RootConstrainSelectedInstOperands,
26177 /* 72190 */ // GIR_Coverage, 3479,
26178 /* 72190 */ GIR_EraseRootFromParent_Done,
26179 /* 72191 */ // Label 1497: @72191
26180 /* 72191 */ GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(72258), // Rule ID 3481 //
26181 /* 72196 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26182 /* 72199 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
26183 /* 72204 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26184 /* 72207 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26185 /* 72210 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26186 /* 72213 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26187 /* 72216 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26188 /* 72220 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26189 /* 72224 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26190 /* 72228 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26191 /* 72232 */ // (intrinsic_wo_chain:{ *:[i32] } 3793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
26192 /* 72232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16),
26193 /* 72235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26194 /* 72237 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26195 /* 72239 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26196 /* 72241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26197 /* 72244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26198 /* 72250 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26199 /* 72256 */ GIR_RootConstrainSelectedInstOperands,
26200 /* 72257 */ // GIR_Coverage, 3481,
26201 /* 72257 */ GIR_EraseRootFromParent_Done,
26202 /* 72258 */ // Label 1498: @72258
26203 /* 72258 */ GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(72325), // Rule ID 3483 //
26204 /* 72263 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26205 /* 72266 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_minv),
26206 /* 72271 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26207 /* 72274 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26208 /* 72277 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26209 /* 72280 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26210 /* 72283 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26211 /* 72287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26212 /* 72291 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26213 /* 72295 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26214 /* 72299 */ // (intrinsic_wo_chain:{ *:[i32] } 3793:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMINVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
26215 /* 72299 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32),
26216 /* 72302 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26217 /* 72304 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26218 /* 72306 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26219 /* 72308 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26220 /* 72311 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26221 /* 72317 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26222 /* 72323 */ GIR_RootConstrainSelectedInstOperands,
26223 /* 72324 */ // GIR_Coverage, 3483,
26224 /* 72324 */ GIR_EraseRootFromParent_Done,
26225 /* 72325 */ // Label 1499: @72325
26226 /* 72325 */ GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(72392), // Rule ID 3485 //
26227 /* 72330 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26228 /* 72333 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
26229 /* 72338 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26230 /* 72341 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26231 /* 72344 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26232 /* 72347 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26233 /* 72350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26234 /* 72354 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26235 /* 72358 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26236 /* 72362 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26237 /* 72366 */ // (intrinsic_wo_chain:{ *:[i32] } 3784:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
26238 /* 72366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8),
26239 /* 72369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26240 /* 72371 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26241 /* 72373 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26242 /* 72375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26243 /* 72378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26244 /* 72384 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26245 /* 72390 */ GIR_RootConstrainSelectedInstOperands,
26246 /* 72391 */ // GIR_Coverage, 3485,
26247 /* 72391 */ GIR_EraseRootFromParent_Done,
26248 /* 72392 */ // Label 1500: @72392
26249 /* 72392 */ GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(72459), // Rule ID 3487 //
26250 /* 72397 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26251 /* 72400 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
26252 /* 72405 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26253 /* 72408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26254 /* 72411 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26255 /* 72414 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26256 /* 72417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26257 /* 72421 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26258 /* 72425 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26259 /* 72429 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26260 /* 72433 */ // (intrinsic_wo_chain:{ *:[i32] } 3784:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
26261 /* 72433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16),
26262 /* 72436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26263 /* 72438 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26264 /* 72440 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26265 /* 72442 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26266 /* 72445 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26267 /* 72451 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26268 /* 72457 */ GIR_RootConstrainSelectedInstOperands,
26269 /* 72458 */ // GIR_Coverage, 3487,
26270 /* 72458 */ GIR_EraseRootFromParent_Done,
26271 /* 72459 */ // Label 1501: @72459
26272 /* 72459 */ GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(72526), // Rule ID 3489 //
26273 /* 72464 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26274 /* 72467 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
26275 /* 72472 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26276 /* 72475 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26277 /* 72478 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26278 /* 72481 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26279 /* 72484 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26280 /* 72488 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26281 /* 72492 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26282 /* 72496 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26283 /* 72500 */ // (intrinsic_wo_chain:{ *:[i32] } 3784:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 0:{ *:[i32] }) => (MVE_VMAXVs32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
26284 /* 72500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32),
26285 /* 72503 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26286 /* 72505 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26287 /* 72507 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26288 /* 72509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26289 /* 72512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26290 /* 72518 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26291 /* 72524 */ GIR_RootConstrainSelectedInstOperands,
26292 /* 72525 */ // GIR_Coverage, 3489,
26293 /* 72525 */ GIR_EraseRootFromParent_Done,
26294 /* 72526 */ // Label 1502: @72526
26295 /* 72526 */ GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(72593), // Rule ID 3491 //
26296 /* 72531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26297 /* 72534 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
26298 /* 72539 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26299 /* 72542 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26300 /* 72545 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26301 /* 72548 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26302 /* 72551 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26303 /* 72555 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26304 /* 72559 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26305 /* 72563 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26306 /* 72567 */ // (intrinsic_wo_chain:{ *:[i32] } 3784:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu8:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v16i8] }:$vec)
26307 /* 72567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8),
26308 /* 72570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26309 /* 72572 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26310 /* 72574 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26311 /* 72576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26312 /* 72579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26313 /* 72585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26314 /* 72591 */ GIR_RootConstrainSelectedInstOperands,
26315 /* 72592 */ // GIR_Coverage, 3491,
26316 /* 72592 */ GIR_EraseRootFromParent_Done,
26317 /* 72593 */ // Label 1503: @72593
26318 /* 72593 */ GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(72660), // Rule ID 3493 //
26319 /* 72598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26320 /* 72601 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
26321 /* 72606 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26322 /* 72609 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26323 /* 72612 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26324 /* 72615 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26325 /* 72618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26326 /* 72622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26327 /* 72626 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26328 /* 72630 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26329 /* 72634 */ // (intrinsic_wo_chain:{ *:[i32] } 3784:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu16:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v8i16] }:$vec)
26330 /* 72634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16),
26331 /* 72637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26332 /* 72639 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26333 /* 72641 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26334 /* 72643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26335 /* 72646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26336 /* 72652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26337 /* 72658 */ GIR_RootConstrainSelectedInstOperands,
26338 /* 72659 */ // GIR_Coverage, 3493,
26339 /* 72659 */ GIR_EraseRootFromParent_Done,
26340 /* 72660 */ // Label 1504: @72660
26341 /* 72660 */ GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(72727), // Rule ID 3495 //
26342 /* 72665 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26343 /* 72668 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_maxv),
26344 /* 72673 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
26345 /* 72676 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
26346 /* 72679 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26347 /* 72682 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26348 /* 72685 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26349 /* 72689 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
26350 /* 72693 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26351 /* 72697 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26352 /* 72701 */ // (intrinsic_wo_chain:{ *:[i32] } 3784:{ *:[iPTR] }, rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec, 1:{ *:[i32] }) => (MVE_VMAXVu32:{ *:[i32] } rGPR:{ *:[i32] }:$prev, MQPR:{ *:[v4i32] }:$vec)
26353 /* 72701 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32),
26354 /* 72704 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
26355 /* 72706 */ GIR_RootToRootCopy, /*OpIdx*/2, // prev
26356 /* 72708 */ GIR_RootToRootCopy, /*OpIdx*/3, // vec
26357 /* 72710 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26358 /* 72713 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26359 /* 72719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26360 /* 72725 */ GIR_RootConstrainSelectedInstOperands,
26361 /* 72726 */ // GIR_Coverage, 3495,
26362 /* 72726 */ GIR_EraseRootFromParent_Done,
26363 /* 72727 */ // Label 1505: @72727
26364 /* 72727 */ GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(72809), // Rule ID 3906 //
26365 /* 72732 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26366 /* 72735 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26367 /* 72740 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26368 /* 72743 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26369 /* 72746 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26370 /* 72749 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26371 /* 72752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26372 /* 72756 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26373 /* 72760 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26374 /* 72764 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26375 /* 72768 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3830:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26376 /* 72768 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26377 /* 72771 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26378 /* 72775 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26379 /* 72780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs8),
26380 /* 72783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26381 /* 72785 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26382 /* 72787 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26383 /* 72789 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26384 /* 72792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26385 /* 72798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26386 /* 72804 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26387 /* 72807 */ GIR_RootConstrainSelectedInstOperands,
26388 /* 72808 */ // GIR_Coverage, 3906,
26389 /* 72808 */ GIR_EraseRootFromParent_Done,
26390 /* 72809 */ // Label 1506: @72809
26391 /* 72809 */ GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(72891), // Rule ID 3913 //
26392 /* 72814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26393 /* 72817 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26394 /* 72822 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26395 /* 72825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26396 /* 72828 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26397 /* 72831 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26398 /* 72834 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26399 /* 72838 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26400 /* 72842 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26401 /* 72846 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26402 /* 72850 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3830:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26403 /* 72850 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26404 /* 72853 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26405 /* 72857 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26406 /* 72862 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs16),
26407 /* 72865 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26408 /* 72867 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26409 /* 72869 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26410 /* 72871 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26411 /* 72874 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26412 /* 72880 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26413 /* 72886 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26414 /* 72889 */ GIR_RootConstrainSelectedInstOperands,
26415 /* 72890 */ // GIR_Coverage, 3913,
26416 /* 72890 */ GIR_EraseRootFromParent_Done,
26417 /* 72891 */ // Label 1507: @72891
26418 /* 72891 */ GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(72973), // Rule ID 3917 //
26419 /* 72896 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26420 /* 72899 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26421 /* 72904 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26422 /* 72907 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26423 /* 72910 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26424 /* 72913 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26425 /* 72916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26426 /* 72920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26427 /* 72924 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26428 /* 72928 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26429 /* 72932 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3830:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26430 /* 72932 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26431 /* 72935 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26432 /* 72939 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26433 /* 72944 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDs32),
26434 /* 72947 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26435 /* 72949 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26436 /* 72951 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26437 /* 72953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26438 /* 72956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26439 /* 72962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26440 /* 72968 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26441 /* 72971 */ GIR_RootConstrainSelectedInstOperands,
26442 /* 72972 */ // GIR_Coverage, 3917,
26443 /* 72972 */ GIR_EraseRootFromParent_Done,
26444 /* 72973 */ // Label 1508: @72973
26445 /* 72973 */ GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(73055), // Rule ID 3921 //
26446 /* 72978 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26447 /* 72981 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26448 /* 72986 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26449 /* 72989 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26450 /* 72992 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26451 /* 72995 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26452 /* 72998 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26453 /* 73002 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26454 /* 73006 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26455 /* 73010 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26456 /* 73014 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3830:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26457 /* 73014 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26458 /* 73017 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26459 /* 73021 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26460 /* 73026 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu8),
26461 /* 73029 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26462 /* 73031 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26463 /* 73033 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26464 /* 73035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26465 /* 73038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26466 /* 73044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26467 /* 73050 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26468 /* 73053 */ GIR_RootConstrainSelectedInstOperands,
26469 /* 73054 */ // GIR_Coverage, 3921,
26470 /* 73054 */ GIR_EraseRootFromParent_Done,
26471 /* 73055 */ // Label 1509: @73055
26472 /* 73055 */ GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(73137), // Rule ID 3925 //
26473 /* 73060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26474 /* 73063 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26475 /* 73068 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26476 /* 73071 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26477 /* 73074 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26478 /* 73077 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26479 /* 73080 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26480 /* 73084 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26481 /* 73088 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26482 /* 73092 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26483 /* 73096 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3830:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26484 /* 73096 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26485 /* 73099 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26486 /* 73103 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26487 /* 73108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu16),
26488 /* 73111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26489 /* 73113 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26490 /* 73115 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26491 /* 73117 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26492 /* 73120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26493 /* 73126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26494 /* 73132 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26495 /* 73135 */ GIR_RootConstrainSelectedInstOperands,
26496 /* 73136 */ // GIR_Coverage, 3925,
26497 /* 73136 */ GIR_EraseRootFromParent_Done,
26498 /* 73137 */ // Label 1510: @73137
26499 /* 73137 */ GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(73219), // Rule ID 3929 //
26500 /* 73142 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26501 /* 73145 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
26502 /* 73150 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26503 /* 73153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26504 /* 73156 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26505 /* 73159 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26506 /* 73162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26507 /* 73166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26508 /* 73170 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26509 /* 73174 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26510 /* 73178 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3830:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VABDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26511 /* 73178 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26512 /* 73181 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26513 /* 73185 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26514 /* 73190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDu32),
26515 /* 73193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26516 /* 73195 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26517 /* 73197 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26518 /* 73199 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26519 /* 73202 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26520 /* 73208 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26521 /* 73214 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26522 /* 73217 */ GIR_RootConstrainSelectedInstOperands,
26523 /* 73218 */ // GIR_Coverage, 3929,
26524 /* 73218 */ GIR_EraseRootFromParent_Done,
26525 /* 73219 */ // Label 1511: @73219
26526 /* 73219 */ GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(73301), // Rule ID 3930 //
26527 /* 73224 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26528 /* 73227 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
26529 /* 73232 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26530 /* 73235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26531 /* 73238 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26532 /* 73241 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26533 /* 73244 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26534 /* 73248 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26535 /* 73252 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26536 /* 73256 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26537 /* 73260 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3922:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26538 /* 73260 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26539 /* 73263 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26540 /* 73267 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26541 /* 73272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs8),
26542 /* 73275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26543 /* 73277 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26544 /* 73279 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26545 /* 73281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26546 /* 73284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26547 /* 73290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26548 /* 73296 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26549 /* 73299 */ GIR_RootConstrainSelectedInstOperands,
26550 /* 73300 */ // GIR_Coverage, 3930,
26551 /* 73300 */ GIR_EraseRootFromParent_Done,
26552 /* 73301 */ // Label 1512: @73301
26553 /* 73301 */ GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(73383), // Rule ID 3937 //
26554 /* 73306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26555 /* 73309 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
26556 /* 73314 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26557 /* 73317 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26558 /* 73320 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26559 /* 73323 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26560 /* 73326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26561 /* 73330 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26562 /* 73334 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26563 /* 73338 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26564 /* 73342 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3922:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26565 /* 73342 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26566 /* 73345 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26567 /* 73349 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26568 /* 73354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs16),
26569 /* 73357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26570 /* 73359 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26571 /* 73361 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26572 /* 73363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26573 /* 73366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26574 /* 73372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26575 /* 73378 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26576 /* 73381 */ GIR_RootConstrainSelectedInstOperands,
26577 /* 73382 */ // GIR_Coverage, 3937,
26578 /* 73382 */ GIR_EraseRootFromParent_Done,
26579 /* 73383 */ // Label 1513: @73383
26580 /* 73383 */ GIM_Try, /*On fail goto*//*Label 1514*/ GIMT_Encode4(73465), // Rule ID 3941 //
26581 /* 73388 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26582 /* 73391 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
26583 /* 73396 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26584 /* 73399 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26585 /* 73402 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26586 /* 73405 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26587 /* 73408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26588 /* 73412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26589 /* 73416 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26590 /* 73420 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26591 /* 73424 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3922:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26592 /* 73424 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26593 /* 73427 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26594 /* 73431 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26595 /* 73436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDs32),
26596 /* 73439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26597 /* 73441 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26598 /* 73443 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26599 /* 73445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26600 /* 73448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26601 /* 73454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26602 /* 73460 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26603 /* 73463 */ GIR_RootConstrainSelectedInstOperands,
26604 /* 73464 */ // GIR_Coverage, 3941,
26605 /* 73464 */ GIR_EraseRootFromParent_Done,
26606 /* 73465 */ // Label 1514: @73465
26607 /* 73465 */ GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(73547), // Rule ID 3945 //
26608 /* 73470 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26609 /* 73473 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
26610 /* 73478 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26611 /* 73481 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26612 /* 73484 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26613 /* 73487 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26614 /* 73490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26615 /* 73494 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26616 /* 73498 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26617 /* 73502 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26618 /* 73506 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3922:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26619 /* 73506 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26620 /* 73509 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26621 /* 73513 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26622 /* 73518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu8),
26623 /* 73521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26624 /* 73523 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26625 /* 73525 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26626 /* 73527 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26627 /* 73530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26628 /* 73536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26629 /* 73542 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26630 /* 73545 */ GIR_RootConstrainSelectedInstOperands,
26631 /* 73546 */ // GIR_Coverage, 3945,
26632 /* 73546 */ GIR_EraseRootFromParent_Done,
26633 /* 73547 */ // Label 1515: @73547
26634 /* 73547 */ GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(73629), // Rule ID 3949 //
26635 /* 73552 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26636 /* 73555 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
26637 /* 73560 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26638 /* 73563 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26639 /* 73566 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26640 /* 73569 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26641 /* 73572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26642 /* 73576 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26643 /* 73580 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26644 /* 73584 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26645 /* 73588 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3922:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26646 /* 73588 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26647 /* 73591 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26648 /* 73595 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26649 /* 73600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu16),
26650 /* 73603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26651 /* 73605 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26652 /* 73607 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26653 /* 73609 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26654 /* 73612 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26655 /* 73618 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26656 /* 73624 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26657 /* 73627 */ GIR_RootConstrainSelectedInstOperands,
26658 /* 73628 */ // GIR_Coverage, 3949,
26659 /* 73628 */ GIR_EraseRootFromParent_Done,
26660 /* 73629 */ // Label 1516: @73629
26661 /* 73629 */ GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(73711), // Rule ID 3953 //
26662 /* 73634 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26663 /* 73637 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrhadd),
26664 /* 73642 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26665 /* 73645 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26666 /* 73648 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26667 /* 73651 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26668 /* 73654 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26669 /* 73658 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26670 /* 73662 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26671 /* 73666 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26672 /* 73670 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3922:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26673 /* 73670 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26674 /* 73673 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26675 /* 73677 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26676 /* 73682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRHADDu32),
26677 /* 73685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26678 /* 73687 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26679 /* 73689 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26680 /* 73691 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26681 /* 73694 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26682 /* 73700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26683 /* 73706 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26684 /* 73709 */ GIR_RootConstrainSelectedInstOperands,
26685 /* 73710 */ // GIR_Coverage, 3953,
26686 /* 73710 */ GIR_EraseRootFromParent_Done,
26687 /* 73711 */ // Label 1517: @73711
26688 /* 73711 */ GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(73793), // Rule ID 3954 //
26689 /* 73716 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26690 /* 73719 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
26691 /* 73724 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26692 /* 73727 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26693 /* 73730 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26694 /* 73733 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26695 /* 73736 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26696 /* 73740 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26697 /* 73744 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26698 /* 73748 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26699 /* 73752 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3868:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26700 /* 73752 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26701 /* 73755 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26702 /* 73759 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26703 /* 73764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs8),
26704 /* 73767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26705 /* 73769 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26706 /* 73771 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26707 /* 73773 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26708 /* 73776 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26709 /* 73782 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26710 /* 73788 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26711 /* 73791 */ GIR_RootConstrainSelectedInstOperands,
26712 /* 73792 */ // GIR_Coverage, 3954,
26713 /* 73792 */ GIR_EraseRootFromParent_Done,
26714 /* 73793 */ // Label 1518: @73793
26715 /* 73793 */ GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(73875), // Rule ID 3961 //
26716 /* 73798 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26717 /* 73801 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
26718 /* 73806 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26719 /* 73809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26720 /* 73812 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26721 /* 73815 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26722 /* 73818 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26723 /* 73822 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26724 /* 73826 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26725 /* 73830 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26726 /* 73834 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3868:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26727 /* 73834 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26728 /* 73837 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26729 /* 73841 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26730 /* 73846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs16),
26731 /* 73849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26732 /* 73851 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26733 /* 73853 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26734 /* 73855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26735 /* 73858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26736 /* 73864 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26737 /* 73870 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26738 /* 73873 */ GIR_RootConstrainSelectedInstOperands,
26739 /* 73874 */ // GIR_Coverage, 3961,
26740 /* 73874 */ GIR_EraseRootFromParent_Done,
26741 /* 73875 */ // Label 1519: @73875
26742 /* 73875 */ GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(73957), // Rule ID 3965 //
26743 /* 73880 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26744 /* 73883 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
26745 /* 73888 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26746 /* 73891 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26747 /* 73894 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26748 /* 73897 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26749 /* 73900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26750 /* 73904 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26751 /* 73908 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26752 /* 73912 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26753 /* 73916 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3868:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26754 /* 73916 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26755 /* 73919 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26756 /* 73923 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26757 /* 73928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDs32),
26758 /* 73931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26759 /* 73933 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26760 /* 73935 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26761 /* 73937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26762 /* 73940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26763 /* 73946 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26764 /* 73952 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26765 /* 73955 */ GIR_RootConstrainSelectedInstOperands,
26766 /* 73956 */ // GIR_Coverage, 3965,
26767 /* 73956 */ GIR_EraseRootFromParent_Done,
26768 /* 73957 */ // Label 1520: @73957
26769 /* 73957 */ GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(74039), // Rule ID 3969 //
26770 /* 73962 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26771 /* 73965 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
26772 /* 73970 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26773 /* 73973 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26774 /* 73976 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26775 /* 73979 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26776 /* 73982 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26777 /* 73986 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26778 /* 73990 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26779 /* 73994 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26780 /* 73998 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3868:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26781 /* 73998 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26782 /* 74001 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26783 /* 74005 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26784 /* 74010 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu8),
26785 /* 74013 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26786 /* 74015 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26787 /* 74017 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26788 /* 74019 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26789 /* 74022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26790 /* 74028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26791 /* 74034 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26792 /* 74037 */ GIR_RootConstrainSelectedInstOperands,
26793 /* 74038 */ // GIR_Coverage, 3969,
26794 /* 74038 */ GIR_EraseRootFromParent_Done,
26795 /* 74039 */ // Label 1521: @74039
26796 /* 74039 */ GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(74121), // Rule ID 3973 //
26797 /* 74044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26798 /* 74047 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
26799 /* 74052 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26800 /* 74055 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26801 /* 74058 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26802 /* 74061 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26803 /* 74064 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26804 /* 74068 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26805 /* 74072 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26806 /* 74076 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26807 /* 74080 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3868:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26808 /* 74080 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26809 /* 74083 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26810 /* 74087 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26811 /* 74092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu16),
26812 /* 74095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26813 /* 74097 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26814 /* 74099 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26815 /* 74101 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26816 /* 74104 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26817 /* 74110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26818 /* 74116 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26819 /* 74119 */ GIR_RootConstrainSelectedInstOperands,
26820 /* 74120 */ // GIR_Coverage, 3973,
26821 /* 74120 */ GIR_EraseRootFromParent_Done,
26822 /* 74121 */ // Label 1522: @74121
26823 /* 74121 */ GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(74203), // Rule ID 3977 //
26824 /* 74126 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26825 /* 74129 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhadd),
26826 /* 74134 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26827 /* 74137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26828 /* 74140 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26829 /* 74143 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26830 /* 74146 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26831 /* 74150 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26832 /* 74154 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26833 /* 74158 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26834 /* 74162 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3868:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26835 /* 74162 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26836 /* 74165 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26837 /* 74169 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26838 /* 74174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHADDu32),
26839 /* 74177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26840 /* 74179 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26841 /* 74181 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26842 /* 74183 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26843 /* 74186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26844 /* 74192 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26845 /* 74198 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26846 /* 74201 */ GIR_RootConstrainSelectedInstOperands,
26847 /* 74202 */ // GIR_Coverage, 3977,
26848 /* 74202 */ GIR_EraseRootFromParent_Done,
26849 /* 74203 */ // Label 1523: @74203
26850 /* 74203 */ GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(74285), // Rule ID 3978 //
26851 /* 74208 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26852 /* 74211 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
26853 /* 74216 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26854 /* 74219 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26855 /* 74222 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26856 /* 74225 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26857 /* 74228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26858 /* 74232 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26859 /* 74236 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26860 /* 74240 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26861 /* 74244 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3869:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26862 /* 74244 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26863 /* 74247 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26864 /* 74251 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26865 /* 74256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs8),
26866 /* 74259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26867 /* 74261 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26868 /* 74263 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26869 /* 74265 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26870 /* 74268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26871 /* 74274 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26872 /* 74280 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26873 /* 74283 */ GIR_RootConstrainSelectedInstOperands,
26874 /* 74284 */ // GIR_Coverage, 3978,
26875 /* 74284 */ GIR_EraseRootFromParent_Done,
26876 /* 74285 */ // Label 1524: @74285
26877 /* 74285 */ GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(74367), // Rule ID 3981 //
26878 /* 74290 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26879 /* 74293 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
26880 /* 74298 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26881 /* 74301 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26882 /* 74304 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26883 /* 74307 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26884 /* 74310 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26885 /* 74314 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26886 /* 74318 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26887 /* 74322 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26888 /* 74326 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26889 /* 74326 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26890 /* 74329 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26891 /* 74333 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26892 /* 74338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs16),
26893 /* 74341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26894 /* 74343 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26895 /* 74345 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26896 /* 74347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26897 /* 74350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26898 /* 74356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26899 /* 74362 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26900 /* 74365 */ GIR_RootConstrainSelectedInstOperands,
26901 /* 74366 */ // GIR_Coverage, 3981,
26902 /* 74366 */ GIR_EraseRootFromParent_Done,
26903 /* 74367 */ // Label 1525: @74367
26904 /* 74367 */ GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(74449), // Rule ID 3984 //
26905 /* 74372 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26906 /* 74375 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
26907 /* 74380 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26908 /* 74383 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26909 /* 74386 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26910 /* 74389 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26911 /* 74392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26912 /* 74396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26913 /* 74400 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26914 /* 74404 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
26915 /* 74408 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VHSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26916 /* 74408 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26917 /* 74411 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26918 /* 74415 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26919 /* 74420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBs32),
26920 /* 74423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26921 /* 74425 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26922 /* 74427 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26923 /* 74429 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26924 /* 74432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26925 /* 74438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26926 /* 74444 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26927 /* 74447 */ GIR_RootConstrainSelectedInstOperands,
26928 /* 74448 */ // GIR_Coverage, 3984,
26929 /* 74448 */ GIR_EraseRootFromParent_Done,
26930 /* 74449 */ // Label 1526: @74449
26931 /* 74449 */ GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(74531), // Rule ID 3987 //
26932 /* 74454 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26933 /* 74457 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
26934 /* 74462 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
26935 /* 74465 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
26936 /* 74468 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
26937 /* 74471 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26938 /* 74474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26939 /* 74478 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26940 /* 74482 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26941 /* 74486 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26942 /* 74490 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3869:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
26943 /* 74490 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26944 /* 74493 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26945 /* 74497 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26946 /* 74502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu8),
26947 /* 74505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26948 /* 74507 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26949 /* 74509 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26950 /* 74511 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26951 /* 74514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26952 /* 74520 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26953 /* 74526 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26954 /* 74529 */ GIR_RootConstrainSelectedInstOperands,
26955 /* 74530 */ // GIR_Coverage, 3987,
26956 /* 74530 */ GIR_EraseRootFromParent_Done,
26957 /* 74531 */ // Label 1527: @74531
26958 /* 74531 */ GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(74613), // Rule ID 3990 //
26959 /* 74536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26960 /* 74539 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
26961 /* 74544 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
26962 /* 74547 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
26963 /* 74550 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
26964 /* 74553 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26965 /* 74556 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26966 /* 74560 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26967 /* 74564 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26968 /* 74568 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26969 /* 74572 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3869:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
26970 /* 74572 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26971 /* 74575 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26972 /* 74579 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
26973 /* 74584 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu16),
26974 /* 74587 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
26975 /* 74589 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
26976 /* 74591 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
26977 /* 74593 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
26978 /* 74596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26979 /* 74602 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
26980 /* 74608 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
26981 /* 74611 */ GIR_RootConstrainSelectedInstOperands,
26982 /* 74612 */ // GIR_Coverage, 3990,
26983 /* 74612 */ GIR_EraseRootFromParent_Done,
26984 /* 74613 */ // Label 1528: @74613
26985 /* 74613 */ GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(74695), // Rule ID 3993 //
26986 /* 74618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
26987 /* 74621 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vhsub),
26988 /* 74626 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
26989 /* 74629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
26990 /* 74632 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
26991 /* 74635 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
26992 /* 74638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26993 /* 74642 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26994 /* 74646 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
26995 /* 74650 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
26996 /* 74654 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3869:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VHSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
26997 /* 74654 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
26998 /* 74657 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
26999 /* 74661 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27000 /* 74666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHSUBu32),
27001 /* 74669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27002 /* 74671 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27003 /* 74673 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27004 /* 74675 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27005 /* 74678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27006 /* 74684 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27007 /* 74690 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27008 /* 74693 */ GIR_RootConstrainSelectedInstOperands,
27009 /* 74694 */ // GIR_Coverage, 3993,
27010 /* 74694 */ GIR_EraseRootFromParent_Done,
27011 /* 74695 */ // Label 1529: @74695
27012 /* 74695 */ GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(74777), // Rule ID 4430 //
27013 /* 74700 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27014 /* 74703 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
27015 /* 74708 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27016 /* 74711 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27017 /* 74714 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27018 /* 74717 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27019 /* 74720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27020 /* 74724 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27021 /* 74728 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27022 /* 74732 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27023 /* 74736 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3830:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
27024 /* 74736 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27025 /* 74739 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27026 /* 74743 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27027 /* 74748 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32),
27028 /* 74751 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27029 /* 74753 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27030 /* 74755 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27031 /* 74757 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27032 /* 74760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27033 /* 74766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27034 /* 74772 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27035 /* 74775 */ GIR_RootConstrainSelectedInstOperands,
27036 /* 74776 */ // GIR_Coverage, 4430,
27037 /* 74776 */ GIR_EraseRootFromParent_Done,
27038 /* 74777 */ // Label 1530: @74777
27039 /* 74777 */ GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(74859), // Rule ID 4432 //
27040 /* 74782 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27041 /* 74785 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabd),
27042 /* 74790 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27043 /* 74793 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27044 /* 74796 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27045 /* 74799 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27046 /* 74802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27047 /* 74806 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27048 /* 74810 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27049 /* 74814 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27050 /* 74818 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3830:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn, 0:{ *:[i32] }) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
27051 /* 74818 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27052 /* 74821 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27053 /* 74825 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27054 /* 74830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16),
27055 /* 74833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27056 /* 74835 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27057 /* 74837 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27058 /* 74839 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27059 /* 74842 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27060 /* 74848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27061 /* 74854 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27062 /* 74857 */ GIR_RootConstrainSelectedInstOperands,
27063 /* 74858 */ // GIR_Coverage, 4432,
27064 /* 74858 */ GIR_EraseRootFromParent_Done,
27065 /* 74859 */ // Label 1531: @74859
27066 /* 74859 */ GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(74941), // Rule ID 4865 //
27067 /* 74864 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27068 /* 74867 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly),
27069 /* 74872 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27070 /* 74875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27071 /* 74878 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27072 /* 74881 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27073 /* 74884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27074 /* 74888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27075 /* 74892 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27076 /* 74896 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27077 /* 74900 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3899:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
27078 /* 74900 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27079 /* 74903 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27080 /* 74907 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27081 /* 74912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp8),
27082 /* 74915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27083 /* 74917 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27084 /* 74919 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27085 /* 74921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27086 /* 74924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27087 /* 74930 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27088 /* 74936 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27089 /* 74939 */ GIR_RootConstrainSelectedInstOperands,
27090 /* 74940 */ // GIR_Coverage, 4865,
27091 /* 74940 */ GIR_EraseRootFromParent_Done,
27092 /* 74941 */ // Label 1532: @74941
27093 /* 74941 */ GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(75023), // Rule ID 4867 //
27094 /* 74946 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27095 /* 74949 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly),
27096 /* 74954 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27097 /* 74957 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27098 /* 74960 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27099 /* 74963 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27100 /* 74966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27101 /* 74970 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27102 /* 74974 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27103 /* 74978 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27104 /* 74982 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3899:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
27105 /* 74982 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27106 /* 74985 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27107 /* 74989 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27108 /* 74994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp8),
27109 /* 74997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27110 /* 74999 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27111 /* 75001 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27112 /* 75003 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27113 /* 75006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27114 /* 75012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27115 /* 75018 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27116 /* 75021 */ GIR_RootConstrainSelectedInstOperands,
27117 /* 75022 */ // GIR_Coverage, 4867,
27118 /* 75022 */ GIR_EraseRootFromParent_Done,
27119 /* 75023 */ // Label 1533: @75023
27120 /* 75023 */ GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(75105), // Rule ID 4869 //
27121 /* 75028 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27122 /* 75031 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly),
27123 /* 75036 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27124 /* 75039 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27125 /* 75042 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27126 /* 75045 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27127 /* 75048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27128 /* 75052 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27129 /* 75056 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27130 /* 75060 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27131 /* 75064 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3899:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULLBp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
27132 /* 75064 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27133 /* 75067 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27134 /* 75071 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27135 /* 75076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBp16),
27136 /* 75079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27137 /* 75081 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27138 /* 75083 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27139 /* 75085 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27140 /* 75088 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27141 /* 75094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27142 /* 75100 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27143 /* 75103 */ GIR_RootConstrainSelectedInstOperands,
27144 /* 75104 */ // GIR_Coverage, 4869,
27145 /* 75104 */ GIR_EraseRootFromParent_Done,
27146 /* 75105 */ // Label 1534: @75105
27147 /* 75105 */ GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(75187), // Rule ID 4871 //
27148 /* 75110 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27149 /* 75113 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull_poly),
27150 /* 75118 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27151 /* 75121 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27152 /* 75124 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27153 /* 75127 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27154 /* 75130 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27155 /* 75134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27156 /* 75138 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27157 /* 75142 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27158 /* 75146 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3899:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULLTp16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
27159 /* 75146 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27160 /* 75149 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27161 /* 75153 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27162 /* 75158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTp16),
27163 /* 75161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27164 /* 75163 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27165 /* 75165 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27166 /* 75167 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27167 /* 75170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27168 /* 75176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27169 /* 75182 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27170 /* 75185 */ GIR_RootConstrainSelectedInstOperands,
27171 /* 75186 */ // GIR_Coverage, 4871,
27172 /* 75186 */ GIR_EraseRootFromParent_Done,
27173 /* 75187 */ // Label 1535: @75187
27174 /* 75187 */ GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(75269), // Rule ID 4898 //
27175 /* 75192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27176 /* 75195 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
27177 /* 75200 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
27178 /* 75203 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27179 /* 75206 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27180 /* 75209 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27181 /* 75212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27182 /* 75216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27183 /* 75220 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27184 /* 75224 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27185 /* 75228 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3897:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
27186 /* 75228 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27187 /* 75231 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27188 /* 75235 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27189 /* 75240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8),
27190 /* 75243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27191 /* 75245 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27192 /* 75247 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27193 /* 75249 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27194 /* 75252 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27195 /* 75258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27196 /* 75264 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27197 /* 75267 */ GIR_RootConstrainSelectedInstOperands,
27198 /* 75268 */ // GIR_Coverage, 4898,
27199 /* 75268 */ GIR_EraseRootFromParent_Done,
27200 /* 75269 */ // Label 1536: @75269
27201 /* 75269 */ GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(75351), // Rule ID 4905 //
27202 /* 75274 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27203 /* 75277 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
27204 /* 75282 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27205 /* 75285 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27206 /* 75288 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27207 /* 75291 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27208 /* 75294 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27209 /* 75298 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27210 /* 75302 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27211 /* 75306 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27212 /* 75310 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3897:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
27213 /* 75310 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27214 /* 75313 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27215 /* 75317 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27216 /* 75322 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16),
27217 /* 75325 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27218 /* 75327 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27219 /* 75329 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27220 /* 75331 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27221 /* 75334 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27222 /* 75340 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27223 /* 75346 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27224 /* 75349 */ GIR_RootConstrainSelectedInstOperands,
27225 /* 75350 */ // GIR_Coverage, 4905,
27226 /* 75350 */ GIR_EraseRootFromParent_Done,
27227 /* 75351 */ // Label 1537: @75351
27228 /* 75351 */ GIM_Try, /*On fail goto*//*Label 1538*/ GIMT_Encode4(75433), // Rule ID 4909 //
27229 /* 75356 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27230 /* 75359 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
27231 /* 75364 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27232 /* 75367 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27233 /* 75370 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27234 /* 75373 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27235 /* 75376 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27236 /* 75380 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27237 /* 75384 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27238 /* 75388 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27239 /* 75392 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3897:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
27240 /* 75392 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27241 /* 75395 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27242 /* 75399 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27243 /* 75404 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32),
27244 /* 75407 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27245 /* 75409 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27246 /* 75411 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27247 /* 75413 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27248 /* 75416 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27249 /* 75422 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27250 /* 75428 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27251 /* 75431 */ GIR_RootConstrainSelectedInstOperands,
27252 /* 75432 */ // GIR_Coverage, 4909,
27253 /* 75432 */ GIR_EraseRootFromParent_Done,
27254 /* 75433 */ // Label 1538: @75433
27255 /* 75433 */ GIM_Try, /*On fail goto*//*Label 1539*/ GIMT_Encode4(75515), // Rule ID 4913 //
27256 /* 75438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27257 /* 75441 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
27258 /* 75446 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
27259 /* 75449 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27260 /* 75452 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27261 /* 75455 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27262 /* 75458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27263 /* 75462 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27264 /* 75466 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27265 /* 75470 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27266 /* 75474 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3897:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
27267 /* 75474 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27268 /* 75477 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27269 /* 75481 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27270 /* 75486 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8),
27271 /* 75489 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27272 /* 75491 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27273 /* 75493 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27274 /* 75495 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27275 /* 75498 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27276 /* 75504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27277 /* 75510 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27278 /* 75513 */ GIR_RootConstrainSelectedInstOperands,
27279 /* 75514 */ // GIR_Coverage, 4913,
27280 /* 75514 */ GIR_EraseRootFromParent_Done,
27281 /* 75515 */ // Label 1539: @75515
27282 /* 75515 */ GIM_Try, /*On fail goto*//*Label 1540*/ GIMT_Encode4(75597), // Rule ID 4917 //
27283 /* 75520 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27284 /* 75523 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
27285 /* 75528 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27286 /* 75531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27287 /* 75534 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27288 /* 75537 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27289 /* 75540 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27290 /* 75544 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27291 /* 75548 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27292 /* 75552 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27293 /* 75556 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3897:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
27294 /* 75556 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27295 /* 75559 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27296 /* 75563 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27297 /* 75568 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16),
27298 /* 75571 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27299 /* 75573 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27300 /* 75575 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27301 /* 75577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27302 /* 75580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27303 /* 75586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27304 /* 75592 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27305 /* 75595 */ GIR_RootConstrainSelectedInstOperands,
27306 /* 75596 */ // GIR_Coverage, 4917,
27307 /* 75596 */ GIR_EraseRootFromParent_Done,
27308 /* 75597 */ // Label 1540: @75597
27309 /* 75597 */ GIM_Try, /*On fail goto*//*Label 1541*/ GIMT_Encode4(75679), // Rule ID 4921 //
27310 /* 75602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27311 /* 75605 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmulh),
27312 /* 75610 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27313 /* 75613 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27314 /* 75616 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27315 /* 75619 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27316 /* 75622 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27317 /* 75626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27318 /* 75630 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27319 /* 75634 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27320 /* 75638 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3897:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
27321 /* 75638 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27322 /* 75641 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27323 /* 75645 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27324 /* 75650 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32),
27325 /* 75653 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27326 /* 75655 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27327 /* 75657 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27328 /* 75659 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27329 /* 75662 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27330 /* 75668 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27331 /* 75674 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27332 /* 75677 */ GIR_RootConstrainSelectedInstOperands,
27333 /* 75678 */ // GIR_Coverage, 4921,
27334 /* 75678 */ GIR_EraseRootFromParent_Done,
27335 /* 75679 */ // Label 1541: @75679
27336 /* 75679 */ GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(75761), // Rule ID 4922 //
27337 /* 75684 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27338 /* 75687 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
27339 /* 75692 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
27340 /* 75695 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27341 /* 75698 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27342 /* 75701 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27343 /* 75704 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27344 /* 75708 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27345 /* 75712 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27346 /* 75716 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27347 /* 75720 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3937:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
27348 /* 75720 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27349 /* 75723 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27350 /* 75727 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27351 /* 75732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs8),
27352 /* 75735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27353 /* 75737 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27354 /* 75739 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27355 /* 75741 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27356 /* 75744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27357 /* 75750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27358 /* 75756 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27359 /* 75759 */ GIR_RootConstrainSelectedInstOperands,
27360 /* 75760 */ // GIR_Coverage, 4922,
27361 /* 75760 */ GIR_EraseRootFromParent_Done,
27362 /* 75761 */ // Label 1542: @75761
27363 /* 75761 */ GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(75843), // Rule ID 4924 //
27364 /* 75766 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27365 /* 75769 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
27366 /* 75774 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27367 /* 75777 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27368 /* 75780 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27369 /* 75783 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27370 /* 75786 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27371 /* 75790 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27372 /* 75794 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27373 /* 75798 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27374 /* 75802 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3937:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
27375 /* 75802 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27376 /* 75805 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27377 /* 75809 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27378 /* 75814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs16),
27379 /* 75817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27380 /* 75819 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27381 /* 75821 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27382 /* 75823 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27383 /* 75826 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27384 /* 75832 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27385 /* 75838 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27386 /* 75841 */ GIR_RootConstrainSelectedInstOperands,
27387 /* 75842 */ // GIR_Coverage, 4924,
27388 /* 75842 */ GIR_EraseRootFromParent_Done,
27389 /* 75843 */ // Label 1543: @75843
27390 /* 75843 */ GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(75925), // Rule ID 4926 //
27391 /* 75848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27392 /* 75851 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
27393 /* 75856 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27394 /* 75859 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27395 /* 75862 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27396 /* 75865 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27397 /* 75868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27398 /* 75872 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27399 /* 75876 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27400 /* 75880 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27401 /* 75884 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3937:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VRMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
27402 /* 75884 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27403 /* 75887 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27404 /* 75891 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27405 /* 75896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHs32),
27406 /* 75899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27407 /* 75901 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27408 /* 75903 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27409 /* 75905 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27410 /* 75908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27411 /* 75914 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27412 /* 75920 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27413 /* 75923 */ GIR_RootConstrainSelectedInstOperands,
27414 /* 75924 */ // GIR_Coverage, 4926,
27415 /* 75924 */ GIR_EraseRootFromParent_Done,
27416 /* 75925 */ // Label 1544: @75925
27417 /* 75925 */ GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(76007), // Rule ID 4928 //
27418 /* 75930 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27419 /* 75933 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
27420 /* 75938 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
27421 /* 75941 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27422 /* 75944 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27423 /* 75947 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27424 /* 75950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27425 /* 75954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27426 /* 75958 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27427 /* 75962 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27428 /* 75966 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3937:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
27429 /* 75966 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27430 /* 75969 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27431 /* 75973 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27432 /* 75978 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu8),
27433 /* 75981 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27434 /* 75983 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27435 /* 75985 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27436 /* 75987 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27437 /* 75990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27438 /* 75996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27439 /* 76002 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27440 /* 76005 */ GIR_RootConstrainSelectedInstOperands,
27441 /* 76006 */ // GIR_Coverage, 4928,
27442 /* 76006 */ GIR_EraseRootFromParent_Done,
27443 /* 76007 */ // Label 1545: @76007
27444 /* 76007 */ GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(76089), // Rule ID 4930 //
27445 /* 76012 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27446 /* 76015 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
27447 /* 76020 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27448 /* 76023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27449 /* 76026 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27450 /* 76029 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27451 /* 76032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27452 /* 76036 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27453 /* 76040 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27454 /* 76044 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27455 /* 76048 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3937:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
27456 /* 76048 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27457 /* 76051 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27458 /* 76055 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27459 /* 76060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu16),
27460 /* 76063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27461 /* 76065 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27462 /* 76067 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27463 /* 76069 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27464 /* 76072 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27465 /* 76078 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27466 /* 76084 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27467 /* 76087 */ GIR_RootConstrainSelectedInstOperands,
27468 /* 76088 */ // GIR_Coverage, 4930,
27469 /* 76088 */ GIR_EraseRootFromParent_Done,
27470 /* 76089 */ // Label 1546: @76089
27471 /* 76089 */ GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(76171), // Rule ID 4932 //
27472 /* 76094 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27473 /* 76097 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vrmulh),
27474 /* 76102 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27475 /* 76105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27476 /* 76108 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27477 /* 76111 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27478 /* 76114 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27479 /* 76118 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27480 /* 76122 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27481 /* 76126 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27482 /* 76130 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3937:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VRMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
27483 /* 76130 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27484 /* 76133 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27485 /* 76137 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27486 /* 76142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRMULHu32),
27487 /* 76145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27488 /* 76147 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27489 /* 76149 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27490 /* 76151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27491 /* 76154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27492 /* 76160 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27493 /* 76166 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27494 /* 76169 */ GIR_RootConstrainSelectedInstOperands,
27495 /* 76170 */ // GIR_Coverage, 4932,
27496 /* 76170 */ GIR_EraseRootFromParent_Done,
27497 /* 76171 */ // Label 1547: @76171
27498 /* 76171 */ GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(76238), // Rule ID 4983 //
27499 /* 76176 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27500 /* 76179 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow),
27501 /* 76184 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27502 /* 76187 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27503 /* 76190 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27504 /* 76193 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27505 /* 76196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27506 /* 76200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27507 /* 76204 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27508 /* 76208 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27509 /* 76212 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3852:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 0:{ *:[i32] }) => (MVE_VCVTf16f32bh:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
27510 /* 76212 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32bh),
27511 /* 76215 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27512 /* 76217 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
27513 /* 76219 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
27514 /* 76221 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27515 /* 76224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27516 /* 76230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27517 /* 76236 */ GIR_RootConstrainSelectedInstOperands,
27518 /* 76237 */ // GIR_Coverage, 4983,
27519 /* 76237 */ GIR_EraseRootFromParent_Done,
27520 /* 76238 */ // Label 1548: @76238
27521 /* 76238 */ GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(76305), // Rule ID 4989 //
27522 /* 76243 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27523 /* 76246 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcvt_narrow),
27524 /* 76251 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27525 /* 76254 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27526 /* 76257 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27527 /* 76260 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27528 /* 76263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27529 /* 76267 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27530 /* 76271 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27531 /* 76275 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27532 /* 76279 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3852:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm, 1:{ *:[i32] }) => (MVE_VCVTf16f32th:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qm)
27533 /* 76279 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16f32th),
27534 /* 76282 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27535 /* 76284 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
27536 /* 76286 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
27537 /* 76288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27538 /* 76291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27539 /* 76297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27540 /* 76303 */ GIR_RootConstrainSelectedInstOperands,
27541 /* 76304 */ // GIR_Coverage, 4989,
27542 /* 76304 */ GIR_EraseRootFromParent_Done,
27543 /* 76305 */ // Label 1549: @76305
27544 /* 76305 */ GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(76387), // Rule ID 5007 //
27545 /* 76310 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27546 /* 76313 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull),
27547 /* 76318 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27548 /* 76321 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27549 /* 76324 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27550 /* 76327 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27551 /* 76330 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27552 /* 76334 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27553 /* 76338 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27554 /* 76342 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27555 /* 76346 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3907:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
27556 /* 76346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27557 /* 76349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27558 /* 76353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27559 /* 76358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16bh),
27560 /* 76361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27561 /* 76363 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27562 /* 76365 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27563 /* 76367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27564 /* 76370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27565 /* 76376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27566 /* 76382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27567 /* 76385 */ GIR_RootConstrainSelectedInstOperands,
27568 /* 76386 */ // GIR_Coverage, 5007,
27569 /* 76386 */ GIR_EraseRootFromParent_Done,
27570 /* 76387 */ // Label 1550: @76387
27571 /* 76387 */ GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(76469), // Rule ID 5009 //
27572 /* 76392 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27573 /* 76395 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull),
27574 /* 76400 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27575 /* 76403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27576 /* 76406 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27577 /* 76409 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27578 /* 76412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27579 /* 76416 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27580 /* 76420 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27581 /* 76424 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27582 /* 76428 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3907:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
27583 /* 76428 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27584 /* 76431 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27585 /* 76435 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27586 /* 76440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs16th),
27587 /* 76443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27588 /* 76445 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27589 /* 76447 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27590 /* 76449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27591 /* 76452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27592 /* 76458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27593 /* 76464 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27594 /* 76467 */ GIR_RootConstrainSelectedInstOperands,
27595 /* 76468 */ // GIR_Coverage, 5009,
27596 /* 76468 */ GIR_EraseRootFromParent_Done,
27597 /* 76469 */ // Label 1551: @76469
27598 /* 76469 */ GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(76551), // Rule ID 5011 //
27599 /* 76474 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27600 /* 76477 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull),
27601 /* 76482 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
27602 /* 76485 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27603 /* 76488 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27604 /* 76491 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27605 /* 76494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27606 /* 76498 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27607 /* 76502 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27608 /* 76506 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
27609 /* 76510 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3907:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }) => (MVE_VQDMULLs32bh:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
27610 /* 76510 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27611 /* 76513 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27612 /* 76517 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27613 /* 76522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32bh),
27614 /* 76525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27615 /* 76527 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27616 /* 76529 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27617 /* 76531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27618 /* 76534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27619 /* 76540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27620 /* 76546 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27621 /* 76549 */ GIR_RootConstrainSelectedInstOperands,
27622 /* 76550 */ // GIR_Coverage, 5011,
27623 /* 76550 */ GIR_EraseRootFromParent_Done,
27624 /* 76551 */ // Label 1552: @76551
27625 /* 76551 */ GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(76633), // Rule ID 5013 //
27626 /* 76556 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
27627 /* 76559 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmull),
27628 /* 76564 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
27629 /* 76567 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27630 /* 76570 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27631 /* 76573 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27632 /* 76576 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27633 /* 76580 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27634 /* 76584 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27635 /* 76588 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
27636 /* 76592 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3907:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }) => (MVE_VQDMULLs32th:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
27637 /* 76592 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27638 /* 76595 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27639 /* 76599 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27640 /* 76604 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMULLs32th),
27641 /* 76607 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27642 /* 76609 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
27643 /* 76611 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27644 /* 76613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27645 /* 76616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27646 /* 76622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27647 /* 76628 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27648 /* 76631 */ GIR_RootConstrainSelectedInstOperands,
27649 /* 76632 */ // GIR_Coverage, 5013,
27650 /* 76632 */ GIR_EraseRootFromParent_Done,
27651 /* 76633 */ // Label 1553: @76633
27652 /* 76633 */ GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(76710), // Rule ID 4262 //
27653 /* 76638 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsli),
27654 /* 76643 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
27655 /* 76646 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27656 /* 76649 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27657 /* 76652 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27658 /* 76655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27659 /* 76659 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27660 /* 76663 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27661 /* 76667 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27662 /* 76671 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27663 /* 76675 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_7),
27664 /* 76679 */ // MIs[1] Operand 1
27665 /* 76679 */ // No operand predicates
27666 /* 76679 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27667 /* 76681 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3952:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm) => (MVE_VSLIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_7>>:$imm)
27668 /* 76681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSLIimm8),
27669 /* 76684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27670 /* 76686 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
27671 /* 76688 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
27672 /* 76690 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
27673 /* 76693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27674 /* 76696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27675 /* 76702 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27676 /* 76708 */ GIR_RootConstrainSelectedInstOperands,
27677 /* 76709 */ // GIR_Coverage, 4262,
27678 /* 76709 */ GIR_EraseRootFromParent_Done,
27679 /* 76710 */ // Label 1554: @76710
27680 /* 76710 */ GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(76787), // Rule ID 4264 //
27681 /* 76715 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsli),
27682 /* 76720 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27683 /* 76723 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27684 /* 76726 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27685 /* 76729 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27686 /* 76732 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27687 /* 76736 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27688 /* 76740 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27689 /* 76744 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27690 /* 76748 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27691 /* 76752 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
27692 /* 76756 */ // MIs[1] Operand 1
27693 /* 76756 */ // No operand predicates
27694 /* 76756 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27695 /* 76758 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3952:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (MVE_VSLIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm)
27696 /* 76758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSLIimm16),
27697 /* 76761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27698 /* 76763 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
27699 /* 76765 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
27700 /* 76767 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
27701 /* 76770 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27702 /* 76773 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27703 /* 76779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27704 /* 76785 */ GIR_RootConstrainSelectedInstOperands,
27705 /* 76786 */ // GIR_Coverage, 4264,
27706 /* 76786 */ GIR_EraseRootFromParent_Done,
27707 /* 76787 */ // Label 1555: @76787
27708 /* 76787 */ GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(76864), // Rule ID 4266 //
27709 /* 76792 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsli),
27710 /* 76797 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27711 /* 76800 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27712 /* 76803 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27713 /* 76806 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27714 /* 76809 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27715 /* 76813 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27716 /* 76817 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27717 /* 76821 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27718 /* 76825 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27719 /* 76829 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_31),
27720 /* 76833 */ // MIs[1] Operand 1
27721 /* 76833 */ // No operand predicates
27722 /* 76833 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27723 /* 76835 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3952:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm) => (MVE_VSLIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_imm0_31>>:$imm)
27724 /* 76835 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSLIimm32),
27725 /* 76838 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27726 /* 76840 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
27727 /* 76842 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
27728 /* 76844 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
27729 /* 76847 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27730 /* 76850 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27731 /* 76856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27732 /* 76862 */ GIR_RootConstrainSelectedInstOperands,
27733 /* 76863 */ // GIR_Coverage, 4266,
27734 /* 76863 */ GIR_EraseRootFromParent_Done,
27735 /* 76864 */ // Label 1556: @76864
27736 /* 76864 */ GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(76941), // Rule ID 4268 //
27737 /* 76869 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsri),
27738 /* 76874 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
27739 /* 76877 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
27740 /* 76880 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
27741 /* 76883 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27742 /* 76886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27743 /* 76890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27744 /* 76894 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27745 /* 76898 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27746 /* 76902 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27747 /* 76906 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
27748 /* 76910 */ // MIs[1] Operand 1
27749 /* 76910 */ // No operand predicates
27750 /* 76910 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27751 /* 76912 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3954:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm) => (MVE_VSRIimm8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm)
27752 /* 76912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSRIimm8),
27753 /* 76915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27754 /* 76917 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
27755 /* 76919 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
27756 /* 76921 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
27757 /* 76924 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27758 /* 76927 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27759 /* 76933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27760 /* 76939 */ GIR_RootConstrainSelectedInstOperands,
27761 /* 76940 */ // GIR_Coverage, 4268,
27762 /* 76940 */ GIR_EraseRootFromParent_Done,
27763 /* 76941 */ // Label 1557: @76941
27764 /* 76941 */ GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(77018), // Rule ID 4270 //
27765 /* 76946 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsri),
27766 /* 76951 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27767 /* 76954 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27768 /* 76957 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27769 /* 76960 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27770 /* 76963 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27771 /* 76967 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27772 /* 76971 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27773 /* 76975 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27774 /* 76979 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27775 /* 76983 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
27776 /* 76987 */ // MIs[1] Operand 1
27777 /* 76987 */ // No operand predicates
27778 /* 76987 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27779 /* 76989 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3954:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm) => (MVE_VSRIimm16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm)
27780 /* 76989 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSRIimm16),
27781 /* 76992 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27782 /* 76994 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
27783 /* 76996 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
27784 /* 76998 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
27785 /* 77001 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27786 /* 77004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27787 /* 77010 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27788 /* 77016 */ GIR_RootConstrainSelectedInstOperands,
27789 /* 77017 */ // GIR_Coverage, 4270,
27790 /* 77017 */ GIR_EraseRootFromParent_Done,
27791 /* 77018 */ // Label 1558: @77018
27792 /* 77018 */ GIM_Try, /*On fail goto*//*Label 1559*/ GIMT_Encode4(77095), // Rule ID 4272 //
27793 /* 77023 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vsri),
27794 /* 77028 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27795 /* 77031 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27796 /* 77034 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27797 /* 77037 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
27798 /* 77040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27799 /* 77044 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27800 /* 77048 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27801 /* 77052 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
27802 /* 77056 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27803 /* 77060 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm32),
27804 /* 77064 */ // MIs[1] Operand 1
27805 /* 77064 */ // No operand predicates
27806 /* 77064 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27807 /* 77066 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3954:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm) => (MVE_VSRIimm32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm32>>:$imm)
27808 /* 77066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSRIimm32),
27809 /* 77069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27810 /* 77071 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
27811 /* 77073 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
27812 /* 77075 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
27813 /* 77078 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27814 /* 77081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27815 /* 77087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27816 /* 77093 */ GIR_RootConstrainSelectedInstOperands,
27817 /* 77094 */ // GIR_Coverage, 4272,
27818 /* 77094 */ GIR_EraseRootFromParent_Done,
27819 /* 77095 */ // Label 1559: @77095
27820 /* 77095 */ GIM_Try, /*On fail goto*//*Label 1560*/ GIMT_Encode4(77181), // Rule ID 4379 //
27821 /* 77100 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27822 /* 77103 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
27823 /* 77108 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27824 /* 77111 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27825 /* 77114 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27826 /* 77117 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27827 /* 77120 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27828 /* 77124 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27829 /* 77128 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
27830 /* 77132 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
27831 /* 77136 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27832 /* 77141 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27833 /* 77145 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27834 /* 77149 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27835 /* 77151 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3772:{ *:[iPTR] }, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
27836 /* 77151 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
27837 /* 77154 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27838 /* 77156 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
27839 /* 77158 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
27840 /* 77162 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
27841 /* 77164 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27842 /* 77167 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27843 /* 77173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27844 /* 77179 */ GIR_RootConstrainSelectedInstOperands,
27845 /* 77180 */ // GIR_Coverage, 4379,
27846 /* 77180 */ GIR_EraseRootFromParent_Done,
27847 /* 77181 */ // Label 1560: @77181
27848 /* 77181 */ GIM_Try, /*On fail goto*//*Label 1561*/ GIMT_Encode4(77267), // Rule ID 4393 //
27849 /* 77186 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27850 /* 77189 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
27851 /* 77194 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27852 /* 77197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27853 /* 77200 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27854 /* 77203 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
27855 /* 77206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27856 /* 77210 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27857 /* 77214 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
27858 /* 77218 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
27859 /* 77222 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27860 /* 77227 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27861 /* 77231 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27862 /* 77235 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27863 /* 77237 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3772:{ *:[iPTR] }, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
27864 /* 77237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
27865 /* 77240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27866 /* 77242 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
27867 /* 77244 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
27868 /* 77248 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
27869 /* 77250 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27870 /* 77253 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27871 /* 77259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27872 /* 77265 */ GIR_RootConstrainSelectedInstOperands,
27873 /* 77266 */ // GIR_Coverage, 4393,
27874 /* 77266 */ GIR_EraseRootFromParent_Done,
27875 /* 77267 */ // Label 1561: @77267
27876 /* 77267 */ GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(77358), // Rule ID 4837 //
27877 /* 77272 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27878 /* 77275 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq),
27879 /* 77280 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27880 /* 77283 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27881 /* 77286 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27882 /* 77289 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
27883 /* 77292 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27884 /* 77296 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27885 /* 77300 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27886 /* 77304 */ // MIs[1] Operand 1
27887 /* 77304 */ // No operand predicates
27888 /* 77304 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27889 /* 77308 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27890 /* 77312 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27891 /* 77314 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3841:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
27892 /* 77314 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27893 /* 77317 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27894 /* 77321 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27895 /* 77326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf16),
27896 /* 77329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27897 /* 77331 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27898 /* 77333 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm
27899 /* 77335 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
27900 /* 77338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27901 /* 77341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27902 /* 77347 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27903 /* 77353 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27904 /* 77356 */ GIR_RootConstrainSelectedInstOperands,
27905 /* 77357 */ // GIR_Coverage, 4837,
27906 /* 77357 */ GIR_EraseRootFromParent_Done,
27907 /* 77358 */ // Label 1562: @77358
27908 /* 77358 */ GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(77449), // Rule ID 4839 //
27909 /* 77363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27910 /* 77366 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmulq),
27911 /* 77371 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27912 /* 77374 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
27913 /* 77377 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27914 /* 77380 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27915 /* 77383 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27916 /* 77387 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
27917 /* 77391 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
27918 /* 77395 */ // MIs[1] Operand 1
27919 /* 77395 */ // No operand predicates
27920 /* 77395 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27921 /* 77399 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27922 /* 77403 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27923 /* 77405 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3841:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
27924 /* 77405 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
27925 /* 77408 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
27926 /* 77412 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
27927 /* 77417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMULf32),
27928 /* 77420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27929 /* 77422 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
27930 /* 77424 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qm
27931 /* 77426 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
27932 /* 77429 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27933 /* 77432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27934 /* 77438 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27935 /* 77444 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
27936 /* 77447 */ GIR_RootConstrainSelectedInstOperands,
27937 /* 77448 */ // GIR_Coverage, 4839,
27938 /* 77448 */ GIR_EraseRootFromParent_Done,
27939 /* 77449 */ // Label 1563: @77449
27940 /* 77449 */ GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(77535), // Rule ID 4380 //
27941 /* 77454 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27942 /* 77457 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
27943 /* 77462 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
27944 /* 77465 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
27945 /* 77468 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
27946 /* 77471 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
27947 /* 77474 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27948 /* 77478 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27949 /* 77482 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
27950 /* 77486 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
27951 /* 77490 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
27952 /* 77494 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27953 /* 77499 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27954 /* 77503 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27955 /* 77505 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3772:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$m1, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m2), MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
27956 /* 77505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
27957 /* 77508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27958 /* 77510 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
27959 /* 77512 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
27960 /* 77514 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m2
27961 /* 77518 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27962 /* 77521 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27963 /* 77527 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27964 /* 77533 */ GIR_RootConstrainSelectedInstOperands,
27965 /* 77534 */ // GIR_Coverage, 4380,
27966 /* 77534 */ GIR_EraseRootFromParent_Done,
27967 /* 77535 */ // Label 1564: @77535
27968 /* 77535 */ GIM_Try, /*On fail goto*//*Label 1565*/ GIMT_Encode4(77621), // Rule ID 4394 //
27969 /* 77540 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
27970 /* 77543 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
27971 /* 77548 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
27972 /* 77551 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
27973 /* 77554 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
27974 /* 77557 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
27975 /* 77560 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27976 /* 77564 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27977 /* 77568 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
27978 /* 77572 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
27979 /* 77576 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
27980 /* 77580 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27981 /* 77585 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
27982 /* 77589 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
27983 /* 77591 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3772:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$m1, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m2), MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
27984 /* 77591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
27985 /* 77594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
27986 /* 77596 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
27987 /* 77598 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
27988 /* 77600 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m2
27989 /* 77604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
27990 /* 77607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27991 /* 77613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
27992 /* 77619 */ GIR_RootConstrainSelectedInstOperands,
27993 /* 77620 */ // GIR_Coverage, 4394,
27994 /* 77620 */ GIR_EraseRootFromParent_Done,
27995 /* 77621 */ // Label 1565: @77621
27996 /* 77621 */ GIM_Try, /*On fail goto*//*Label 1566*/ GIMT_Encode4(77684), // Rule ID 145 //
27997 /* 77626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
27998 /* 77629 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8),
27999 /* 77634 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28000 /* 77637 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28001 /* 77640 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28002 /* 77643 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28003 /* 77646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28004 /* 77650 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28005 /* 77654 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28006 /* 77658 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28007 /* 77662 */ // (intrinsic_wo_chain:{ *:[i32] } 4179:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (USADA8:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra)
28008 /* 77662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USADA8),
28009 /* 77665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28010 /* 77667 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
28011 /* 77669 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
28012 /* 77671 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
28013 /* 77673 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28014 /* 77676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28015 /* 77682 */ GIR_RootConstrainSelectedInstOperands,
28016 /* 77683 */ // GIR_Coverage, 145,
28017 /* 77683 */ GIR_EraseRootFromParent_Done,
28018 /* 77684 */ // Label 1566: @77684
28019 /* 77684 */ GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(77747), // Rule ID 468 //
28020 /* 77689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28021 /* 77692 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usada8),
28022 /* 77697 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28023 /* 77700 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28024 /* 77703 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28025 /* 77706 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28026 /* 77709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28027 /* 77713 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28028 /* 77717 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28029 /* 77721 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28030 /* 77725 */ // (intrinsic_wo_chain:{ *:[i32] } 4179:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2USADA8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
28031 /* 77725 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USADA8),
28032 /* 77728 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28033 /* 77730 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
28034 /* 77732 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
28035 /* 77734 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
28036 /* 77736 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28037 /* 77739 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28038 /* 77745 */ GIR_RootConstrainSelectedInstOperands,
28039 /* 77746 */ // GIR_Coverage, 468,
28040 /* 77746 */ GIR_EraseRootFromParent_Done,
28041 /* 77747 */ // Label 1567: @77747
28042 /* 77747 */ GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(77810), // Rule ID 527 //
28043 /* 77752 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28044 /* 77755 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad),
28045 /* 77760 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28046 /* 77763 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28047 /* 77766 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28048 /* 77769 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28049 /* 77772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28050 /* 77776 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28051 /* 77780 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28052 /* 77784 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28053 /* 77788 */ // (intrinsic_wo_chain:{ *:[i32] } 4124:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLAD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
28054 /* 77788 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAD),
28055 /* 77791 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28056 /* 77793 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
28057 /* 77795 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
28058 /* 77797 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
28059 /* 77799 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28060 /* 77802 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28061 /* 77808 */ GIR_RootConstrainSelectedInstOperands,
28062 /* 77809 */ // GIR_Coverage, 527,
28063 /* 77809 */ GIR_EraseRootFromParent_Done,
28064 /* 77810 */ // Label 1568: @77810
28065 /* 77810 */ GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(77873), // Rule ID 528 //
28066 /* 77815 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28067 /* 77818 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx),
28068 /* 77823 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28069 /* 77826 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28070 /* 77829 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28071 /* 77832 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28072 /* 77835 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28073 /* 77839 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28074 /* 77843 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28075 /* 77847 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28076 /* 77851 */ // (intrinsic_wo_chain:{ *:[i32] } 4125:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLADX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
28077 /* 77851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLADX),
28078 /* 77854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28079 /* 77856 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
28080 /* 77858 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
28081 /* 77860 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
28082 /* 77862 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28083 /* 77865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28084 /* 77871 */ GIR_RootConstrainSelectedInstOperands,
28085 /* 77872 */ // GIR_Coverage, 528,
28086 /* 77872 */ GIR_EraseRootFromParent_Done,
28087 /* 77873 */ // Label 1569: @77873
28088 /* 77873 */ GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(77936), // Rule ID 529 //
28089 /* 77878 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28090 /* 77881 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd),
28091 /* 77886 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28092 /* 77889 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28093 /* 77892 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28094 /* 77895 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28095 /* 77898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28096 /* 77902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28097 /* 77906 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28098 /* 77910 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28099 /* 77914 */ // (intrinsic_wo_chain:{ *:[i32] } 4132:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSD:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
28100 /* 77914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSD),
28101 /* 77917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28102 /* 77919 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
28103 /* 77921 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
28104 /* 77923 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
28105 /* 77925 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28106 /* 77928 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28107 /* 77934 */ GIR_RootConstrainSelectedInstOperands,
28108 /* 77935 */ // GIR_Coverage, 529,
28109 /* 77935 */ GIR_EraseRootFromParent_Done,
28110 /* 77936 */ // Label 1570: @77936
28111 /* 77936 */ GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(77999), // Rule ID 530 //
28112 /* 77941 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28113 /* 77944 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx),
28114 /* 77949 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28115 /* 77952 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28116 /* 77955 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28117 /* 77958 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28118 /* 77961 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28119 /* 77965 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28120 /* 77969 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28121 /* 77973 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28122 /* 77977 */ // (intrinsic_wo_chain:{ *:[i32] } 4133:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra) => (t2SMLSDX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Ra)
28123 /* 77977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLSDX),
28124 /* 77980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28125 /* 77982 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
28126 /* 77984 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
28127 /* 77986 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
28128 /* 77988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28129 /* 77991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28130 /* 77997 */ GIR_RootConstrainSelectedInstOperands,
28131 /* 77998 */ // GIR_Coverage, 530,
28132 /* 77998 */ GIR_EraseRootFromParent_Done,
28133 /* 77999 */ // Label 1571: @77999
28134 /* 77999 */ GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(78053), // Rule ID 1112 //
28135 /* 78004 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
28136 /* 78007 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot),
28137 /* 78012 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
28138 /* 78015 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
28139 /* 78018 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
28140 /* 78021 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
28141 /* 78024 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28142 /* 78028 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28143 /* 78032 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28144 /* 78036 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28145 /* 78040 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3985:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
28146 /* 78040 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTD),
28147 /* 78043 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28148 /* 78045 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
28149 /* 78047 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28150 /* 78049 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28151 /* 78051 */ GIR_RootConstrainSelectedInstOperands,
28152 /* 78052 */ // GIR_Coverage, 1112,
28153 /* 78052 */ GIR_EraseRootFromParent_Done,
28154 /* 78053 */ // Label 1572: @78053
28155 /* 78053 */ GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(78107), // Rule ID 1113 //
28156 /* 78058 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
28157 /* 78061 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot),
28158 /* 78066 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
28159 /* 78069 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
28160 /* 78072 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
28161 /* 78075 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
28162 /* 78078 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28163 /* 78082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28164 /* 78086 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28165 /* 78090 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28166 /* 78094 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3973:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
28167 /* 78094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTD),
28168 /* 78097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28169 /* 78099 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
28170 /* 78101 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28171 /* 78103 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28172 /* 78105 */ GIR_RootConstrainSelectedInstOperands,
28173 /* 78106 */ // GIR_Coverage, 1113,
28174 /* 78106 */ GIR_EraseRootFromParent_Done,
28175 /* 78107 */ // Label 1573: @78107
28176 /* 78107 */ GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(78161), // Rule ID 1114 //
28177 /* 78112 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
28178 /* 78115 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_udot),
28179 /* 78120 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28180 /* 78123 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28181 /* 78126 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28182 /* 78129 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
28183 /* 78132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28184 /* 78136 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28185 /* 78140 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28186 /* 78144 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28187 /* 78148 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3985:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
28188 /* 78148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUDOTQ),
28189 /* 78151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28190 /* 78153 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
28191 /* 78155 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28192 /* 78157 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28193 /* 78159 */ GIR_RootConstrainSelectedInstOperands,
28194 /* 78160 */ // GIR_Coverage, 1114,
28195 /* 78160 */ GIR_EraseRootFromParent_Done,
28196 /* 78161 */ // Label 1574: @78161
28197 /* 78161 */ GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(78215), // Rule ID 1115 //
28198 /* 78166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDotProd),
28199 /* 78169 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sdot),
28200 /* 78174 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28201 /* 78177 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28202 /* 78180 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28203 /* 78183 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
28204 /* 78186 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28205 /* 78190 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28206 /* 78194 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28207 /* 78198 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28208 /* 78202 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3973:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
28209 /* 78202 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSDOTQ),
28210 /* 78205 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28211 /* 78207 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
28212 /* 78209 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28213 /* 78211 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28214 /* 78213 */ GIR_RootConstrainSelectedInstOperands,
28215 /* 78214 */ // GIR_Coverage, 1115,
28216 /* 78214 */ GIR_EraseRootFromParent_Done,
28217 /* 78215 */ // Label 1575: @78215
28218 /* 78215 */ GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(78269), // Rule ID 1116 //
28219 /* 78220 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
28220 /* 78223 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_smmla),
28221 /* 78228 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28222 /* 78231 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28223 /* 78234 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28224 /* 78237 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
28225 /* 78240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28226 /* 78244 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28227 /* 78248 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28228 /* 78252 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28229 /* 78256 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3984:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
28230 /* 78256 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSMMLA),
28231 /* 78259 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28232 /* 78261 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
28233 /* 78263 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28234 /* 78265 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28235 /* 78267 */ GIR_RootConstrainSelectedInstOperands,
28236 /* 78268 */ // GIR_Coverage, 1116,
28237 /* 78268 */ GIR_EraseRootFromParent_Done,
28238 /* 78269 */ // Label 1576: @78269
28239 /* 78269 */ GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(78323), // Rule ID 1117 //
28240 /* 78274 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
28241 /* 78277 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_ummla),
28242 /* 78282 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28243 /* 78285 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28244 /* 78288 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28245 /* 78291 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
28246 /* 78294 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28247 /* 78298 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28248 /* 78302 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28249 /* 78306 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28250 /* 78310 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3986:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
28251 /* 78310 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUMMLA),
28252 /* 78313 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28253 /* 78315 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
28254 /* 78317 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28255 /* 78319 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28256 /* 78321 */ GIR_RootConstrainSelectedInstOperands,
28257 /* 78322 */ // GIR_Coverage, 1117,
28258 /* 78322 */ GIR_EraseRootFromParent_Done,
28259 /* 78323 */ // Label 1577: @78323
28260 /* 78323 */ GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(78377), // Rule ID 1118 //
28261 /* 78328 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
28262 /* 78331 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usmmla),
28263 /* 78336 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28264 /* 78339 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28265 /* 78342 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28266 /* 78345 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
28267 /* 78348 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28268 /* 78352 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28269 /* 78356 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28270 /* 78360 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28271 /* 78364 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3988:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSMMLA:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
28272 /* 78364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSMMLA),
28273 /* 78367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28274 /* 78369 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
28275 /* 78371 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28276 /* 78373 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28277 /* 78375 */ GIR_RootConstrainSelectedInstOperands,
28278 /* 78376 */ // GIR_Coverage, 1118,
28279 /* 78376 */ GIR_EraseRootFromParent_Done,
28280 /* 78377 */ // Label 1578: @78377
28281 /* 78377 */ GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(78431), // Rule ID 1119 //
28282 /* 78382 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
28283 /* 78385 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot),
28284 /* 78390 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
28285 /* 78393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
28286 /* 78396 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
28287 /* 78399 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
28288 /* 78402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28289 /* 78406 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28290 /* 78410 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28291 /* 78414 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28292 /* 78418 */ // (intrinsic_wo_chain:{ *:[v2i32] } 3987:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VUSDOTD:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vd, DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
28293 /* 78418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTD),
28294 /* 78421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28295 /* 78423 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
28296 /* 78425 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28297 /* 78427 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28298 /* 78429 */ GIR_RootConstrainSelectedInstOperands,
28299 /* 78430 */ // GIR_Coverage, 1119,
28300 /* 78430 */ GIR_EraseRootFromParent_Done,
28301 /* 78431 */ // Label 1579: @78431
28302 /* 78431 */ GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(78485), // Rule ID 1120 //
28303 /* 78436 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMatMulInt8),
28304 /* 78439 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_usdot),
28305 /* 78444 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28306 /* 78447 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28307 /* 78450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
28308 /* 78453 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
28309 /* 78456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28310 /* 78460 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28311 /* 78464 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28312 /* 78468 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28313 /* 78472 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3987:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VUSDOTQ:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vd, QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
28314 /* 78472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUSDOTQ),
28315 /* 78475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
28316 /* 78477 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vd
28317 /* 78479 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28318 /* 78481 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28319 /* 78483 */ GIR_RootConstrainSelectedInstOperands,
28320 /* 78484 */ // GIR_Coverage, 1120,
28321 /* 78484 */ GIR_EraseRootFromParent_Done,
28322 /* 78485 */ // Label 1580: @78485
28323 /* 78485 */ GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(78548), // Rule ID 1851 //
28324 /* 78490 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
28325 /* 78493 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx1),
28326 /* 78498 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
28327 /* 78501 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
28328 /* 78504 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
28329 /* 78507 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
28330 /* 78510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28331 /* 78514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28332 /* 78518 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28333 /* 78522 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28334 /* 78526 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4099:{ *:[iPTR] }, DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VTBX1:{ *:[v8i8] } DPR:{ *:[v8i8] }:$orig, VecListOneD:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
28335 /* 78526 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX1),
28336 /* 78529 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28337 /* 78531 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
28338 /* 78533 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28339 /* 78535 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28340 /* 78537 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28341 /* 78540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28342 /* 78546 */ GIR_RootConstrainSelectedInstOperands,
28343 /* 78547 */ // GIR_Coverage, 1851,
28344 /* 78547 */ GIR_EraseRootFromParent_Done,
28345 /* 78548 */ // Label 1581: @78548
28346 /* 78548 */ GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(78602), // Rule ID 1882 //
28347 /* 78553 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
28348 /* 78556 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1su0),
28349 /* 78561 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28350 /* 78564 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28351 /* 78567 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28352 /* 78570 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28353 /* 78573 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28354 /* 78577 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28355 /* 78581 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28356 /* 78585 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28357 /* 78589 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3978:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA1SU0:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28358 /* 78589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1SU0),
28359 /* 78592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28360 /* 78594 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28361 /* 78596 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28362 /* 78598 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28363 /* 78600 */ GIR_RootConstrainSelectedInstOperands,
28364 /* 78601 */ // GIR_Coverage, 1882,
28365 /* 78601 */ GIR_EraseRootFromParent_Done,
28366 /* 78602 */ // Label 1582: @78602
28367 /* 78602 */ GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(78656), // Rule ID 1883 //
28368 /* 78607 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
28369 /* 78610 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h),
28370 /* 78615 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28371 /* 78618 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28372 /* 78621 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28373 /* 78624 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28374 /* 78627 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28375 /* 78631 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28376 /* 78635 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28377 /* 78639 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28378 /* 78643 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3980:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28379 /* 78643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H),
28380 /* 78646 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28381 /* 78648 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28382 /* 78650 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28383 /* 78652 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28384 /* 78654 */ GIR_RootConstrainSelectedInstOperands,
28385 /* 78655 */ // GIR_Coverage, 1883,
28386 /* 78655 */ GIR_EraseRootFromParent_Done,
28387 /* 78656 */ // Label 1583: @78656
28388 /* 78656 */ GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(78710), // Rule ID 1884 //
28389 /* 78661 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
28390 /* 78664 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256h2),
28391 /* 78669 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28392 /* 78672 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28393 /* 78675 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28394 /* 78678 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28395 /* 78681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28396 /* 78685 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28397 /* 78689 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28398 /* 78693 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28399 /* 78697 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3981:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256H2:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28400 /* 78697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256H2),
28401 /* 78700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28402 /* 78702 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28403 /* 78704 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28404 /* 78706 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28405 /* 78708 */ GIR_RootConstrainSelectedInstOperands,
28406 /* 78709 */ // GIR_Coverage, 1884,
28407 /* 78709 */ GIR_EraseRootFromParent_Done,
28408 /* 78710 */ // Label 1584: @78710
28409 /* 78710 */ GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(78764), // Rule ID 1885 //
28410 /* 78715 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSHA2_HasV8),
28411 /* 78718 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha256su1),
28412 /* 78723 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28413 /* 78726 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28414 /* 78729 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28415 /* 78732 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28416 /* 78735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28417 /* 78739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28418 /* 78743 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28419 /* 78747 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28420 /* 78751 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3983:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (SHA256SU1:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28421 /* 78751 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA256SU1),
28422 /* 78754 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28423 /* 78756 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
28424 /* 78758 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28425 /* 78760 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28426 /* 78762 */ GIR_RootConstrainSelectedInstOperands,
28427 /* 78763 */ // GIR_Coverage, 1885,
28428 /* 78763 */ GIR_EraseRootFromParent_Done,
28429 /* 78764 */ // Label 1585: @78764
28430 /* 78764 */ GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(78827), // Rule ID 2060 //
28431 /* 78769 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
28432 /* 78772 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlad),
28433 /* 78777 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28434 /* 78780 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28435 /* 78783 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28436 /* 78786 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28437 /* 78789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28438 /* 78793 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28439 /* 78797 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28440 /* 78801 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28441 /* 78805 */ // (intrinsic_wo_chain:{ *:[i32] } 4124:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLAD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
28442 /* 78805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAD),
28443 /* 78808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28444 /* 78810 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
28445 /* 78812 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
28446 /* 78814 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
28447 /* 78816 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28448 /* 78819 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28449 /* 78825 */ GIR_RootConstrainSelectedInstOperands,
28450 /* 78826 */ // GIR_Coverage, 2060,
28451 /* 78826 */ GIR_EraseRootFromParent_Done,
28452 /* 78827 */ // Label 1586: @78827
28453 /* 78827 */ GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(78890), // Rule ID 2061 //
28454 /* 78832 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
28455 /* 78835 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smladx),
28456 /* 78840 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28457 /* 78843 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28458 /* 78846 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28459 /* 78849 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28460 /* 78852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28461 /* 78856 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28462 /* 78860 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28463 /* 78864 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28464 /* 78868 */ // (intrinsic_wo_chain:{ *:[i32] } 4125:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLADX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
28465 /* 78868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLADX),
28466 /* 78871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28467 /* 78873 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
28468 /* 78875 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
28469 /* 78877 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
28470 /* 78879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28471 /* 78882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28472 /* 78888 */ GIR_RootConstrainSelectedInstOperands,
28473 /* 78889 */ // GIR_Coverage, 2061,
28474 /* 78889 */ GIR_EraseRootFromParent_Done,
28475 /* 78890 */ // Label 1587: @78890
28476 /* 78890 */ GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(78953), // Rule ID 2062 //
28477 /* 78895 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
28478 /* 78898 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsd),
28479 /* 78903 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28480 /* 78906 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28481 /* 78909 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28482 /* 78912 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28483 /* 78915 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28484 /* 78919 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28485 /* 78923 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28486 /* 78927 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28487 /* 78931 */ // (intrinsic_wo_chain:{ *:[i32] } 4132:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSD:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
28488 /* 78931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSD),
28489 /* 78934 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28490 /* 78936 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
28491 /* 78938 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
28492 /* 78940 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
28493 /* 78942 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28494 /* 78945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28495 /* 78951 */ GIR_RootConstrainSelectedInstOperands,
28496 /* 78952 */ // GIR_Coverage, 2062,
28497 /* 78952 */ GIR_EraseRootFromParent_Done,
28498 /* 78953 */ // Label 1588: @78953
28499 /* 78953 */ GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(79016), // Rule ID 2063 //
28500 /* 78958 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
28501 /* 78961 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlsdx),
28502 /* 78966 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28503 /* 78969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28504 /* 78972 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28505 /* 78975 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28506 /* 78978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28507 /* 78982 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28508 /* 78986 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28509 /* 78990 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28510 /* 78994 */ // (intrinsic_wo_chain:{ *:[i32] } 4133:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPR:{ *:[i32] }:$Ra) => (SMLSDX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm, GPRnopc:{ *:[i32] }:$Ra)
28511 /* 78994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLSDX),
28512 /* 78997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28513 /* 78999 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
28514 /* 79001 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
28515 /* 79003 */ GIR_RootToRootCopy, /*OpIdx*/4, // Ra
28516 /* 79005 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28517 /* 79008 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28518 /* 79014 */ GIR_RootConstrainSelectedInstOperands,
28519 /* 79015 */ // GIR_Coverage, 2063,
28520 /* 79015 */ GIR_EraseRootFromParent_Done,
28521 /* 79016 */ // Label 1589: @79016
28522 /* 79016 */ GIM_Try, /*On fail goto*//*Label 1590*/ GIMT_Encode4(79079), // Rule ID 2151 //
28523 /* 79021 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
28524 /* 79024 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb),
28525 /* 79029 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28526 /* 79032 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28527 /* 79035 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28528 /* 79038 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28529 /* 79041 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28530 /* 79045 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28531 /* 79049 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28532 /* 79053 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28533 /* 79057 */ // (intrinsic_wo_chain:{ *:[i32] } 4122:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28534 /* 79057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABB),
28535 /* 79060 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28536 /* 79062 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28537 /* 79064 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28538 /* 79066 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28539 /* 79068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28540 /* 79071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28541 /* 79077 */ GIR_RootConstrainSelectedInstOperands,
28542 /* 79078 */ // GIR_Coverage, 2151,
28543 /* 79078 */ GIR_EraseRootFromParent_Done,
28544 /* 79079 */ // Label 1590: @79079
28545 /* 79079 */ GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(79142), // Rule ID 2152 //
28546 /* 79084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
28547 /* 79087 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt),
28548 /* 79092 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28549 /* 79095 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28550 /* 79098 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28551 /* 79101 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28552 /* 79104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28553 /* 79108 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28554 /* 79112 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28555 /* 79116 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28556 /* 79120 */ // (intrinsic_wo_chain:{ *:[i32] } 4123:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28557 /* 79120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLABT),
28558 /* 79123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28559 /* 79125 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28560 /* 79127 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28561 /* 79129 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28562 /* 79131 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28563 /* 79134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28564 /* 79140 */ GIR_RootConstrainSelectedInstOperands,
28565 /* 79141 */ // GIR_Coverage, 2152,
28566 /* 79141 */ GIR_EraseRootFromParent_Done,
28567 /* 79142 */ // Label 1591: @79142
28568 /* 79142 */ GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(79205), // Rule ID 2153 //
28569 /* 79147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
28570 /* 79150 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb),
28571 /* 79155 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28572 /* 79158 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28573 /* 79161 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28574 /* 79164 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28575 /* 79167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28576 /* 79171 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28577 /* 79175 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28578 /* 79179 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28579 /* 79183 */ // (intrinsic_wo_chain:{ *:[i32] } 4128:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28580 /* 79183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATB),
28581 /* 79186 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28582 /* 79188 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28583 /* 79190 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28584 /* 79192 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28585 /* 79194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28586 /* 79197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28587 /* 79203 */ GIR_RootConstrainSelectedInstOperands,
28588 /* 79204 */ // GIR_Coverage, 2153,
28589 /* 79204 */ GIR_EraseRootFromParent_Done,
28590 /* 79205 */ // Label 1592: @79205
28591 /* 79205 */ GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(79268), // Rule ID 2154 //
28592 /* 79210 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
28593 /* 79213 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt),
28594 /* 79218 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28595 /* 79221 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28596 /* 79224 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28597 /* 79227 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28598 /* 79230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28599 /* 79234 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28600 /* 79238 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28601 /* 79242 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28602 /* 79246 */ // (intrinsic_wo_chain:{ *:[i32] } 4129:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28603 /* 79246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLATT),
28604 /* 79249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28605 /* 79251 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28606 /* 79253 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28607 /* 79255 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28608 /* 79257 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28609 /* 79260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28610 /* 79266 */ GIR_RootConstrainSelectedInstOperands,
28611 /* 79267 */ // GIR_Coverage, 2154,
28612 /* 79267 */ GIR_EraseRootFromParent_Done,
28613 /* 79268 */ // Label 1593: @79268
28614 /* 79268 */ GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(79331), // Rule ID 2155 //
28615 /* 79273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
28616 /* 79276 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb),
28617 /* 79281 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28618 /* 79284 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28619 /* 79287 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28620 /* 79290 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28621 /* 79293 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28622 /* 79297 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28623 /* 79301 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28624 /* 79305 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28625 /* 79309 */ // (intrinsic_wo_chain:{ *:[i32] } 4130:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28626 /* 79309 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWB),
28627 /* 79312 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28628 /* 79314 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28629 /* 79316 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28630 /* 79318 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28631 /* 79320 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28632 /* 79323 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28633 /* 79329 */ GIR_RootConstrainSelectedInstOperands,
28634 /* 79330 */ // GIR_Coverage, 2155,
28635 /* 79330 */ GIR_EraseRootFromParent_Done,
28636 /* 79331 */ // Label 1594: @79331
28637 /* 79331 */ GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(79394), // Rule ID 2156 //
28638 /* 79336 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
28639 /* 79339 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt),
28640 /* 79344 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28641 /* 79347 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28642 /* 79350 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28643 /* 79353 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28644 /* 79356 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
28645 /* 79360 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28646 /* 79364 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28647 /* 79368 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28648 /* 79372 */ // (intrinsic_wo_chain:{ *:[i32] } 4131:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28649 /* 79372 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMLAWT),
28650 /* 79375 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28651 /* 79377 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28652 /* 79379 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28653 /* 79381 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28654 /* 79383 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28655 /* 79386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28656 /* 79392 */ GIR_RootConstrainSelectedInstOperands,
28657 /* 79393 */ // GIR_Coverage, 2156,
28658 /* 79393 */ GIR_EraseRootFromParent_Done,
28659 /* 79394 */ // Label 1595: @79394
28660 /* 79394 */ GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(79457), // Rule ID 2342 //
28661 /* 79399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28662 /* 79402 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabb),
28663 /* 79407 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28664 /* 79410 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28665 /* 79413 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28666 /* 79416 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28667 /* 79419 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28668 /* 79423 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28669 /* 79427 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28670 /* 79431 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28671 /* 79435 */ // (intrinsic_wo_chain:{ *:[i32] } 4122:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28672 /* 79435 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABB),
28673 /* 79438 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28674 /* 79440 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28675 /* 79442 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28676 /* 79444 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28677 /* 79446 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28678 /* 79449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28679 /* 79455 */ GIR_RootConstrainSelectedInstOperands,
28680 /* 79456 */ // GIR_Coverage, 2342,
28681 /* 79456 */ GIR_EraseRootFromParent_Done,
28682 /* 79457 */ // Label 1596: @79457
28683 /* 79457 */ GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(79520), // Rule ID 2343 //
28684 /* 79462 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28685 /* 79465 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlabt),
28686 /* 79470 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28687 /* 79473 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28688 /* 79476 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28689 /* 79479 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28690 /* 79482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28691 /* 79486 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28692 /* 79490 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28693 /* 79494 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28694 /* 79498 */ // (intrinsic_wo_chain:{ *:[i32] } 4123:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLABT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28695 /* 79498 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLABT),
28696 /* 79501 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28697 /* 79503 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28698 /* 79505 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28699 /* 79507 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28700 /* 79509 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28701 /* 79512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28702 /* 79518 */ GIR_RootConstrainSelectedInstOperands,
28703 /* 79519 */ // GIR_Coverage, 2343,
28704 /* 79519 */ GIR_EraseRootFromParent_Done,
28705 /* 79520 */ // Label 1597: @79520
28706 /* 79520 */ GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(79583), // Rule ID 2344 //
28707 /* 79525 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28708 /* 79528 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatb),
28709 /* 79533 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28710 /* 79536 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28711 /* 79539 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28712 /* 79542 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28713 /* 79545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28714 /* 79549 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28715 /* 79553 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28716 /* 79557 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28717 /* 79561 */ // (intrinsic_wo_chain:{ *:[i32] } 4128:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28718 /* 79561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATB),
28719 /* 79564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28720 /* 79566 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28721 /* 79568 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28722 /* 79570 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28723 /* 79572 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28724 /* 79575 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28725 /* 79581 */ GIR_RootConstrainSelectedInstOperands,
28726 /* 79582 */ // GIR_Coverage, 2344,
28727 /* 79582 */ GIR_EraseRootFromParent_Done,
28728 /* 79583 */ // Label 1598: @79583
28729 /* 79583 */ GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(79646), // Rule ID 2345 //
28730 /* 79588 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28731 /* 79591 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlatt),
28732 /* 79596 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28733 /* 79599 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28734 /* 79602 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28735 /* 79605 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28736 /* 79608 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28737 /* 79612 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28738 /* 79616 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28739 /* 79620 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28740 /* 79624 */ // (intrinsic_wo_chain:{ *:[i32] } 4129:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLATT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28741 /* 79624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLATT),
28742 /* 79627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28743 /* 79629 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28744 /* 79631 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28745 /* 79633 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28746 /* 79635 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28747 /* 79638 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28748 /* 79644 */ GIR_RootConstrainSelectedInstOperands,
28749 /* 79645 */ // GIR_Coverage, 2345,
28750 /* 79645 */ GIR_EraseRootFromParent_Done,
28751 /* 79646 */ // Label 1599: @79646
28752 /* 79646 */ GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(79709), // Rule ID 2346 //
28753 /* 79651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28754 /* 79654 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawb),
28755 /* 79659 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28756 /* 79662 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28757 /* 79665 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28758 /* 79668 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28759 /* 79671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28760 /* 79675 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28761 /* 79679 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28762 /* 79683 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28763 /* 79687 */ // (intrinsic_wo_chain:{ *:[i32] } 4130:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28764 /* 79687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWB),
28765 /* 79690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28766 /* 79692 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28767 /* 79694 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28768 /* 79696 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28769 /* 79698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28770 /* 79701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28771 /* 79707 */ GIR_RootConstrainSelectedInstOperands,
28772 /* 79708 */ // GIR_Coverage, 2346,
28773 /* 79708 */ GIR_EraseRootFromParent_Done,
28774 /* 79709 */ // Label 1600: @79709
28775 /* 79709 */ GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(79772), // Rule ID 2347 //
28776 /* 79714 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
28777 /* 79717 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_smlawt),
28778 /* 79722 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
28779 /* 79725 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
28780 /* 79728 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
28781 /* 79731 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
28782 /* 79734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
28783 /* 79738 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28784 /* 79742 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28785 /* 79746 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
28786 /* 79750 */ // (intrinsic_wo_chain:{ *:[i32] } 4131:{ *:[iPTR] }, GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc) => (t2SMLAWT:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b, GPR:{ *:[i32] }:$acc)
28787 /* 79750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMLAWT),
28788 /* 79753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
28789 /* 79755 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
28790 /* 79757 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
28791 /* 79759 */ GIR_RootToRootCopy, /*OpIdx*/4, // acc
28792 /* 79761 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28793 /* 79764 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28794 /* 79770 */ GIR_RootConstrainSelectedInstOperands,
28795 /* 79771 */ // GIR_Coverage, 2347,
28796 /* 79771 */ GIR_EraseRootFromParent_Done,
28797 /* 79772 */ // Label 1601: @79772
28798 /* 79772 */ GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(79835), // Rule ID 2817 //
28799 /* 79777 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28800 /* 79780 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah),
28801 /* 79785 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
28802 /* 79788 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
28803 /* 79791 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
28804 /* 79794 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
28805 /* 79797 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28806 /* 79801 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28807 /* 79805 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28808 /* 79809 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28809 /* 79813 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4057:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLAHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
28810 /* 79813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i16),
28811 /* 79816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28812 /* 79818 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28813 /* 79820 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28814 /* 79822 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28815 /* 79824 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28816 /* 79827 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28817 /* 79833 */ GIR_RootConstrainSelectedInstOperands,
28818 /* 79834 */ // GIR_Coverage, 2817,
28819 /* 79834 */ GIR_EraseRootFromParent_Done,
28820 /* 79835 */ // Label 1602: @79835
28821 /* 79835 */ GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(79898), // Rule ID 2818 //
28822 /* 79840 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28823 /* 79843 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah),
28824 /* 79848 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
28825 /* 79851 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
28826 /* 79854 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
28827 /* 79857 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
28828 /* 79860 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28829 /* 79864 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28830 /* 79868 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28831 /* 79872 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28832 /* 79876 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4057:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLAHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
28833 /* 79876 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv2i32),
28834 /* 79879 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28835 /* 79881 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28836 /* 79883 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28837 /* 79885 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28838 /* 79887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28839 /* 79890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28840 /* 79896 */ GIR_RootConstrainSelectedInstOperands,
28841 /* 79897 */ // GIR_Coverage, 2818,
28842 /* 79897 */ GIR_EraseRootFromParent_Done,
28843 /* 79898 */ // Label 1603: @79898
28844 /* 79898 */ GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(79961), // Rule ID 2819 //
28845 /* 79903 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28846 /* 79906 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah),
28847 /* 79911 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
28848 /* 79914 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28849 /* 79917 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28850 /* 79920 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
28851 /* 79923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28852 /* 79927 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28853 /* 79931 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28854 /* 79935 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28855 /* 79939 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4057:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLAHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
28856 /* 79939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv8i16),
28857 /* 79942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28858 /* 79944 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28859 /* 79946 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28860 /* 79948 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28861 /* 79950 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28862 /* 79953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28863 /* 79959 */ GIR_RootConstrainSelectedInstOperands,
28864 /* 79960 */ // GIR_Coverage, 2819,
28865 /* 79960 */ GIR_EraseRootFromParent_Done,
28866 /* 79961 */ // Label 1604: @79961
28867 /* 79961 */ GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(80024), // Rule ID 2820 //
28868 /* 79966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28869 /* 79969 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlah),
28870 /* 79974 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28871 /* 79977 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28872 /* 79980 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28873 /* 79983 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28874 /* 79986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28875 /* 79990 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28876 /* 79994 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28877 /* 79998 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28878 /* 80002 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4057:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLAHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28879 /* 80002 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLAHv4i32),
28880 /* 80005 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28881 /* 80007 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28882 /* 80009 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28883 /* 80011 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28884 /* 80013 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28885 /* 80016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28886 /* 80022 */ GIR_RootConstrainSelectedInstOperands,
28887 /* 80023 */ // GIR_Coverage, 2820,
28888 /* 80023 */ GIR_EraseRootFromParent_Done,
28889 /* 80024 */ // Label 1605: @80024
28890 /* 80024 */ GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(80087), // Rule ID 2825 //
28891 /* 80029 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28892 /* 80032 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh),
28893 /* 80037 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16,
28894 /* 80040 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
28895 /* 80043 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
28896 /* 80046 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16,
28897 /* 80049 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28898 /* 80053 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28899 /* 80057 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28900 /* 80061 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28901 /* 80065 */ // (intrinsic_wo_chain:{ *:[v4i16] } 4058:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQRDMLSHv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
28902 /* 80065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i16),
28903 /* 80068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28904 /* 80070 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28905 /* 80072 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28906 /* 80074 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28907 /* 80076 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28908 /* 80079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28909 /* 80085 */ GIR_RootConstrainSelectedInstOperands,
28910 /* 80086 */ // GIR_Coverage, 2825,
28911 /* 80086 */ GIR_EraseRootFromParent_Done,
28912 /* 80087 */ // Label 1606: @80087
28913 /* 80087 */ GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(80150), // Rule ID 2826 //
28914 /* 80092 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28915 /* 80095 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh),
28916 /* 80100 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32,
28917 /* 80103 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
28918 /* 80106 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
28919 /* 80109 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s32,
28920 /* 80112 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28921 /* 80116 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28922 /* 80120 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28923 /* 80124 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
28924 /* 80128 */ // (intrinsic_wo_chain:{ *:[v2i32] } 4058:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQRDMLSHv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
28925 /* 80128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv2i32),
28926 /* 80131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28927 /* 80133 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28928 /* 80135 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28929 /* 80137 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28930 /* 80139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28931 /* 80142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28932 /* 80148 */ GIR_RootConstrainSelectedInstOperands,
28933 /* 80149 */ // GIR_Coverage, 2826,
28934 /* 80149 */ GIR_EraseRootFromParent_Done,
28935 /* 80150 */ // Label 1607: @80150
28936 /* 80150 */ GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(80213), // Rule ID 2827 //
28937 /* 80155 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28938 /* 80158 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh),
28939 /* 80163 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
28940 /* 80166 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
28941 /* 80169 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
28942 /* 80172 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
28943 /* 80175 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28944 /* 80179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28945 /* 80183 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28946 /* 80187 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28947 /* 80191 */ // (intrinsic_wo_chain:{ *:[v8i16] } 4058:{ *:[iPTR] }, QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQRDMLSHv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$src1, QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
28948 /* 80191 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv8i16),
28949 /* 80194 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28950 /* 80196 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28951 /* 80198 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28952 /* 80200 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28953 /* 80202 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28954 /* 80205 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28955 /* 80211 */ GIR_RootConstrainSelectedInstOperands,
28956 /* 80212 */ // GIR_Coverage, 2827,
28957 /* 80212 */ GIR_EraseRootFromParent_Done,
28958 /* 80213 */ // Label 1608: @80213
28959 /* 80213 */ GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(80276), // Rule ID 2828 //
28960 /* 80218 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8_1a),
28961 /* 80221 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqrdmlsh),
28962 /* 80226 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28963 /* 80229 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28964 /* 80232 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28965 /* 80235 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28966 /* 80238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28967 /* 80242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28968 /* 80246 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28969 /* 80250 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
28970 /* 80254 */ // (intrinsic_wo_chain:{ *:[v4i32] } 4058:{ *:[iPTR] }, QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQRDMLSHv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
28971 /* 80254 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQRDMLSHv4i32),
28972 /* 80257 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
28973 /* 80259 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
28974 /* 80261 */ GIR_RootToRootCopy, /*OpIdx*/3, // Vn
28975 /* 80263 */ GIR_RootToRootCopy, /*OpIdx*/4, // Vm
28976 /* 80265 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
28977 /* 80268 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
28978 /* 80274 */ GIR_RootConstrainSelectedInstOperands,
28979 /* 80275 */ // GIR_Coverage, 2828,
28980 /* 80275 */ GIR_EraseRootFromParent_Done,
28981 /* 80276 */ // Label 1609: @80276
28982 /* 80276 */ GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(80345), // Rule ID 4385 //
28983 /* 80281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
28984 /* 80284 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
28985 /* 80289 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
28986 /* 80292 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
28987 /* 80295 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
28988 /* 80298 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
28989 /* 80301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28990 /* 80305 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28991 /* 80309 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28992 /* 80313 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
28993 /* 80317 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3772:{ *:[iPTR] }, MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
28994 /* 80317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32),
28995 /* 80320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
28996 /* 80322 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
28997 /* 80324 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
28998 /* 80326 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
28999 /* 80328 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29000 /* 80331 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29001 /* 80337 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29002 /* 80343 */ GIR_RootConstrainSelectedInstOperands,
29003 /* 80344 */ // GIR_Coverage, 4385,
29004 /* 80344 */ GIR_EraseRootFromParent_Done,
29005 /* 80345 */ // Label 1610: @80345
29006 /* 80345 */ GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(80414), // Rule ID 4389 //
29007 /* 80350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
29008 /* 80353 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_fma),
29009 /* 80358 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29010 /* 80361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29011 /* 80364 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29012 /* 80367 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
29013 /* 80370 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29014 /* 80374 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29015 /* 80378 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29016 /* 80382 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29017 /* 80386 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3772:{ *:[iPTR] }, MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
29018 /* 80386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16),
29019 /* 80389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29020 /* 80391 */ GIR_RootToRootCopy, /*OpIdx*/4, // add
29021 /* 80393 */ GIR_RootToRootCopy, /*OpIdx*/2, // m1
29022 /* 80395 */ GIR_RootToRootCopy, /*OpIdx*/3, // m2
29023 /* 80397 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29024 /* 80400 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29025 /* 80406 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29026 /* 80412 */ GIR_RootConstrainSelectedInstOperands,
29027 /* 80413 */ // GIR_Coverage, 4389,
29028 /* 80413 */ GIR_EraseRootFromParent_Done,
29029 /* 80414 */ // Label 1611: @80414
29030 /* 80414 */ GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(80483), // Rule ID 5318 //
29031 /* 80419 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29032 /* 80422 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah),
29033 /* 80427 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
29034 /* 80430 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29035 /* 80433 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29036 /* 80436 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29037 /* 80439 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29038 /* 80443 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29039 /* 80447 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29040 /* 80451 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29041 /* 80455 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3902:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
29042 /* 80455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs8),
29043 /* 80458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29044 /* 80460 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
29045 /* 80462 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
29046 /* 80464 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
29047 /* 80466 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29048 /* 80469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29049 /* 80475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29050 /* 80481 */ GIR_RootConstrainSelectedInstOperands,
29051 /* 80482 */ // GIR_Coverage, 5318,
29052 /* 80482 */ GIR_EraseRootFromParent_Done,
29053 /* 80483 */ // Label 1612: @80483
29054 /* 80483 */ GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(80552), // Rule ID 5320 //
29055 /* 80488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29056 /* 80491 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah),
29057 /* 80496 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29058 /* 80499 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29059 /* 80502 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29060 /* 80505 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29061 /* 80508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29062 /* 80512 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29063 /* 80516 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29064 /* 80520 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29065 /* 80524 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3902:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
29066 /* 80524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs16),
29067 /* 80527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29068 /* 80529 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
29069 /* 80531 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
29070 /* 80533 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
29071 /* 80535 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29072 /* 80538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29073 /* 80544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29074 /* 80550 */ GIR_RootConstrainSelectedInstOperands,
29075 /* 80551 */ // GIR_Coverage, 5320,
29076 /* 80551 */ GIR_EraseRootFromParent_Done,
29077 /* 80552 */ // Label 1613: @80552
29078 /* 80552 */ GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(80621), // Rule ID 5322 //
29079 /* 80557 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29080 /* 80560 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlah),
29081 /* 80565 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29082 /* 80568 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29083 /* 80571 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29084 /* 80574 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29085 /* 80577 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29086 /* 80581 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29087 /* 80585 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29088 /* 80589 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29089 /* 80593 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3902:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
29090 /* 80593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLAH_qrs32),
29091 /* 80596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29092 /* 80598 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
29093 /* 80600 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
29094 /* 80602 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
29095 /* 80604 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29096 /* 80607 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29097 /* 80613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29098 /* 80619 */ GIR_RootConstrainSelectedInstOperands,
29099 /* 80620 */ // GIR_Coverage, 5322,
29100 /* 80620 */ GIR_EraseRootFromParent_Done,
29101 /* 80621 */ // Label 1614: @80621
29102 /* 80621 */ GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(80690), // Rule ID 5324 //
29103 /* 80626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29104 /* 80629 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah),
29105 /* 80634 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
29106 /* 80637 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29107 /* 80640 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29108 /* 80643 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29109 /* 80646 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29110 /* 80650 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29111 /* 80654 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29112 /* 80658 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29113 /* 80662 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3911:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
29114 /* 80662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs8),
29115 /* 80665 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29116 /* 80667 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
29117 /* 80669 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
29118 /* 80671 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
29119 /* 80673 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29120 /* 80676 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29121 /* 80682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29122 /* 80688 */ GIR_RootConstrainSelectedInstOperands,
29123 /* 80689 */ // GIR_Coverage, 5324,
29124 /* 80689 */ GIR_EraseRootFromParent_Done,
29125 /* 80690 */ // Label 1615: @80690
29126 /* 80690 */ GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(80759), // Rule ID 5326 //
29127 /* 80695 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29128 /* 80698 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah),
29129 /* 80703 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29130 /* 80706 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29131 /* 80709 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29132 /* 80712 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29133 /* 80715 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29134 /* 80719 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29135 /* 80723 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29136 /* 80727 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29137 /* 80731 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3911:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
29138 /* 80731 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs16),
29139 /* 80734 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29140 /* 80736 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
29141 /* 80738 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
29142 /* 80740 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
29143 /* 80742 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29144 /* 80745 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29145 /* 80751 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29146 /* 80757 */ GIR_RootConstrainSelectedInstOperands,
29147 /* 80758 */ // GIR_Coverage, 5326,
29148 /* 80758 */ GIR_EraseRootFromParent_Done,
29149 /* 80759 */ // Label 1616: @80759
29150 /* 80759 */ GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(80828), // Rule ID 5328 //
29151 /* 80764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29152 /* 80767 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlah),
29153 /* 80772 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29154 /* 80775 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29155 /* 80778 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29156 /* 80781 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29157 /* 80784 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29158 /* 80788 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29159 /* 80792 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29160 /* 80796 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29161 /* 80800 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3911:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLAH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
29162 /* 80800 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLAH_qrs32),
29163 /* 80803 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29164 /* 80805 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
29165 /* 80807 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
29166 /* 80809 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
29167 /* 80811 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29168 /* 80814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29169 /* 80820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29170 /* 80826 */ GIR_RootConstrainSelectedInstOperands,
29171 /* 80827 */ // GIR_Coverage, 5328,
29172 /* 80827 */ GIR_EraseRootFromParent_Done,
29173 /* 80828 */ // Label 1617: @80828
29174 /* 80828 */ GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(80897), // Rule ID 5330 //
29175 /* 80833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29176 /* 80836 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash),
29177 /* 80841 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
29178 /* 80844 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29179 /* 80847 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29180 /* 80850 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29181 /* 80853 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29182 /* 80857 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29183 /* 80861 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29184 /* 80865 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29185 /* 80869 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3904:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
29186 /* 80869 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs8),
29187 /* 80872 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29188 /* 80874 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
29189 /* 80876 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
29190 /* 80878 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
29191 /* 80880 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29192 /* 80883 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29193 /* 80889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29194 /* 80895 */ GIR_RootConstrainSelectedInstOperands,
29195 /* 80896 */ // GIR_Coverage, 5330,
29196 /* 80896 */ GIR_EraseRootFromParent_Done,
29197 /* 80897 */ // Label 1618: @80897
29198 /* 80897 */ GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(80966), // Rule ID 5332 //
29199 /* 80902 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29200 /* 80905 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash),
29201 /* 80910 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29202 /* 80913 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29203 /* 80916 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29204 /* 80919 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29205 /* 80922 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29206 /* 80926 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29207 /* 80930 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29208 /* 80934 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29209 /* 80938 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3904:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
29210 /* 80938 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs16),
29211 /* 80941 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29212 /* 80943 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
29213 /* 80945 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
29214 /* 80947 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
29215 /* 80949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29216 /* 80952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29217 /* 80958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29218 /* 80964 */ GIR_RootConstrainSelectedInstOperands,
29219 /* 80965 */ // GIR_Coverage, 5332,
29220 /* 80965 */ GIR_EraseRootFromParent_Done,
29221 /* 80966 */ // Label 1619: @80966
29222 /* 80966 */ GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(81035), // Rule ID 5334 //
29223 /* 80971 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29224 /* 80974 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlash),
29225 /* 80979 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29226 /* 80982 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29227 /* 80985 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29228 /* 80988 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29229 /* 80991 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29230 /* 80995 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29231 /* 80999 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29232 /* 81003 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29233 /* 81007 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3904:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
29234 /* 81007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLASH_qrs32),
29235 /* 81010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29236 /* 81012 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
29237 /* 81014 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
29238 /* 81016 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
29239 /* 81018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29240 /* 81021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29241 /* 81027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29242 /* 81033 */ GIR_RootConstrainSelectedInstOperands,
29243 /* 81034 */ // GIR_Coverage, 5334,
29244 /* 81034 */ GIR_EraseRootFromParent_Done,
29245 /* 81035 */ // Label 1620: @81035
29246 /* 81035 */ GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(81104), // Rule ID 5336 //
29247 /* 81040 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29248 /* 81043 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash),
29249 /* 81048 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
29250 /* 81051 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29251 /* 81054 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29252 /* 81057 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29253 /* 81060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29254 /* 81064 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29255 /* 81068 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29256 /* 81072 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29257 /* 81076 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3913:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v1, MQPR:{ *:[v16i8] }:$v2, rGPR:{ *:[i32] }:$s)
29258 /* 81076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs8),
29259 /* 81079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29260 /* 81081 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
29261 /* 81083 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
29262 /* 81085 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
29263 /* 81087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29264 /* 81090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29265 /* 81096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29266 /* 81102 */ GIR_RootConstrainSelectedInstOperands,
29267 /* 81103 */ // GIR_Coverage, 5336,
29268 /* 81103 */ GIR_EraseRootFromParent_Done,
29269 /* 81104 */ // Label 1621: @81104
29270 /* 81104 */ GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(81173), // Rule ID 5338 //
29271 /* 81109 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29272 /* 81112 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash),
29273 /* 81117 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29274 /* 81120 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29275 /* 81123 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29276 /* 81126 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29277 /* 81129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29278 /* 81133 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29279 /* 81137 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29280 /* 81141 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29281 /* 81145 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3913:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v1, MQPR:{ *:[v8i16] }:$v2, rGPR:{ *:[i32] }:$s)
29282 /* 81145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs16),
29283 /* 81148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29284 /* 81150 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
29285 /* 81152 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
29286 /* 81154 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
29287 /* 81156 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29288 /* 81159 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29289 /* 81165 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29290 /* 81171 */ GIR_RootConstrainSelectedInstOperands,
29291 /* 81172 */ // GIR_Coverage, 5338,
29292 /* 81172 */ GIR_EraseRootFromParent_Done,
29293 /* 81173 */ // Label 1622: @81173
29294 /* 81173 */ GIM_Try, /*On fail goto*//*Label 1623*/ GIMT_Encode4(81242), // Rule ID 5340 //
29295 /* 81178 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29296 /* 81181 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqrdmlash),
29297 /* 81186 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29298 /* 81189 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29299 /* 81192 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29300 /* 81195 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29301 /* 81198 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29302 /* 81202 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29303 /* 81206 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29304 /* 81210 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
29305 /* 81214 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3913:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s) => (MVE_VQRDMLASH_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v1, MQPR:{ *:[v4i32] }:$v2, rGPR:{ *:[i32] }:$s)
29306 /* 81214 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLASH_qrs32),
29307 /* 81217 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29308 /* 81219 */ GIR_RootToRootCopy, /*OpIdx*/2, // v1
29309 /* 81221 */ GIR_RootToRootCopy, /*OpIdx*/3, // v2
29310 /* 81223 */ GIR_RootToRootCopy, /*OpIdx*/4, // s
29311 /* 81225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29312 /* 81228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29313 /* 81234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29314 /* 81240 */ GIR_RootConstrainSelectedInstOperands,
29315 /* 81241 */ // GIR_Coverage, 5340,
29316 /* 81241 */ GIR_EraseRootFromParent_Done,
29317 /* 81242 */ // Label 1623: @81242
29318 /* 81242 */ GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(81337), // Rule ID 3044 //
29319 /* 81247 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
29320 /* 81250 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1c),
29321 /* 81255 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29322 /* 81258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29323 /* 81261 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29324 /* 81264 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
29325 /* 81267 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
29326 /* 81271 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3974:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1C:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
29327 /* 81271 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
29328 /* 81274 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29329 /* 81278 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29330 /* 81283 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
29331 /* 81287 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
29332 /* 81292 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
29333 /* 81295 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
29334 /* 81299 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29335 /* 81304 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
29336 /* 81307 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
29337 /* 81310 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17,
29338 /* 81313 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
29339 /* 81318 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
29340 /* 81323 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1C),
29341 /* 81326 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
29342 /* 81328 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd
29343 /* 81330 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29344 /* 81333 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk
29345 /* 81335 */ GIR_RootConstrainSelectedInstOperands,
29346 /* 81336 */ // GIR_Coverage, 3044,
29347 /* 81336 */ GIR_EraseRootFromParent_Done,
29348 /* 81337 */ // Label 1624: @81337
29349 /* 81337 */ GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(81432), // Rule ID 3045 //
29350 /* 81342 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
29351 /* 81345 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1m),
29352 /* 81350 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29353 /* 81353 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29354 /* 81356 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29355 /* 81359 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
29356 /* 81362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
29357 /* 81366 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3976:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1M:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
29358 /* 81366 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
29359 /* 81369 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29360 /* 81373 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29361 /* 81378 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
29362 /* 81382 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
29363 /* 81387 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
29364 /* 81390 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
29365 /* 81394 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29366 /* 81399 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
29367 /* 81402 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
29368 /* 81405 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17,
29369 /* 81408 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
29370 /* 81413 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
29371 /* 81418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1M),
29372 /* 81421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
29373 /* 81423 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd
29374 /* 81425 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29375 /* 81428 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk
29376 /* 81430 */ GIR_RootConstrainSelectedInstOperands,
29377 /* 81431 */ // GIR_Coverage, 3045,
29378 /* 81431 */ GIR_EraseRootFromParent_Done,
29379 /* 81432 */ // Label 1625: @81432
29380 /* 81432 */ GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(81527), // Rule ID 3046 //
29381 /* 81437 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
29382 /* 81440 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_sha1p),
29383 /* 81445 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29384 /* 81448 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29385 /* 81451 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29386 /* 81454 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
29387 /* 81457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
29388 /* 81461 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3977:{ *:[iPTR] }, v4i32:{ *:[v4i32] }:$hash_abcd, i32:{ *:[i32] }:$hash_e, v4i32:{ *:[v4i32] }:$wk) => (SHA1P:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$hash_abcd, (SUBREG_TO_REG:{ *:[v16i8] } 0:{ *:[i64] }, (COPY_TO_REGCLASS:{ *:[f32] } i32:{ *:[i32] }:$hash_e, SPR:{ *:[i32] }), ssub_0:{ *:[i32] }), v4i32:{ *:[v4i32] }:$wk)
29389 /* 81461 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
29390 /* 81464 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
29391 /* 81468 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29392 /* 81473 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // hash_e
29393 /* 81477 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
29394 /* 81482 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
29395 /* 81485 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG),
29396 /* 81489 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29397 /* 81494 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
29398 /* 81497 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
29399 /* 81500 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/17,
29400 /* 81503 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPair_with_ssub_0RegClassID),
29401 /* 81508 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
29402 /* 81513 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SHA1P),
29403 /* 81516 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
29404 /* 81518 */ GIR_RootToRootCopy, /*OpIdx*/2, // hash_abcd
29405 /* 81520 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29406 /* 81523 */ GIR_RootToRootCopy, /*OpIdx*/4, // wk
29407 /* 81525 */ GIR_RootConstrainSelectedInstOperands,
29408 /* 81526 */ // GIR_Coverage, 3046,
29409 /* 81526 */ GIR_EraseRootFromParent_Done,
29410 /* 81527 */ // Label 1626: @81527
29411 /* 81527 */ GIM_Reject,
29412 /* 81528 */ // Label 1473: @81528
29413 /* 81528 */ GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(84914),
29414 /* 81533 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
29415 /* 81536 */ GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(81620), // Rule ID 4085 //
29416 /* 81541 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29417 /* 81546 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29418 /* 81549 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29419 /* 81552 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29420 /* 81555 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29421 /* 81558 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29422 /* 81561 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29423 /* 81565 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29424 /* 81569 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
29425 /* 81573 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29426 /* 81577 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29427 /* 81581 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3948:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
29428 /* 81581 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29429 /* 81584 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29430 /* 81588 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29431 /* 81593 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8bh),
29432 /* 81596 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29433 /* 81598 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29434 /* 81600 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29435 /* 81603 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29436 /* 81609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29437 /* 81615 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29438 /* 81618 */ GIR_RootConstrainSelectedInstOperands,
29439 /* 81619 */ // GIR_Coverage, 4085,
29440 /* 81619 */ GIR_EraseRootFromParent_Done,
29441 /* 81620 */ // Label 1628: @81620
29442 /* 81620 */ GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(81704), // Rule ID 4089 //
29443 /* 81625 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29444 /* 81630 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29445 /* 81633 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29446 /* 81636 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29447 /* 81639 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29448 /* 81642 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29449 /* 81645 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29450 /* 81649 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29451 /* 81653 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
29452 /* 81657 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29453 /* 81661 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29454 /* 81665 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3948:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
29455 /* 81665 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29456 /* 81668 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29457 /* 81672 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29458 /* 81677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws8th),
29459 /* 81680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29460 /* 81682 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29461 /* 81684 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29462 /* 81687 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29463 /* 81693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29464 /* 81699 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29465 /* 81702 */ GIR_RootConstrainSelectedInstOperands,
29466 /* 81703 */ // GIR_Coverage, 4089,
29467 /* 81703 */ GIR_EraseRootFromParent_Done,
29468 /* 81704 */ // Label 1629: @81704
29469 /* 81704 */ GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(81788), // Rule ID 4093 //
29470 /* 81709 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29471 /* 81714 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29472 /* 81717 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29473 /* 81720 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29474 /* 81723 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29475 /* 81726 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29476 /* 81729 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29477 /* 81733 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29478 /* 81737 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
29479 /* 81741 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29480 /* 81745 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29481 /* 81749 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3948:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lws16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
29482 /* 81749 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29483 /* 81752 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29484 /* 81756 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29485 /* 81761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16bh),
29486 /* 81764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29487 /* 81766 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29488 /* 81768 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29489 /* 81771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29490 /* 81777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29491 /* 81783 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29492 /* 81786 */ GIR_RootConstrainSelectedInstOperands,
29493 /* 81787 */ // GIR_Coverage, 4093,
29494 /* 81787 */ GIR_EraseRootFromParent_Done,
29495 /* 81788 */ // Label 1630: @81788
29496 /* 81788 */ GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(81872), // Rule ID 4097 //
29497 /* 81793 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29498 /* 81798 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29499 /* 81801 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29500 /* 81804 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29501 /* 81807 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29502 /* 81810 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29503 /* 81813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29504 /* 81817 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29505 /* 81821 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
29506 /* 81825 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29507 /* 81829 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29508 /* 81833 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3948:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lws16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
29509 /* 81833 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29510 /* 81836 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29511 /* 81840 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29512 /* 81845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lws16th),
29513 /* 81848 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29514 /* 81850 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29515 /* 81852 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29516 /* 81855 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29517 /* 81861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29518 /* 81867 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29519 /* 81870 */ GIR_RootConstrainSelectedInstOperands,
29520 /* 81871 */ // GIR_Coverage, 4097,
29521 /* 81871 */ GIR_EraseRootFromParent_Done,
29522 /* 81872 */ // Label 1631: @81872
29523 /* 81872 */ GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(81956), // Rule ID 4101 //
29524 /* 81877 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29525 /* 81882 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29526 /* 81885 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29527 /* 81888 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29528 /* 81891 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29529 /* 81894 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29530 /* 81897 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29531 /* 81901 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29532 /* 81905 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
29533 /* 81909 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29534 /* 81913 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29535 /* 81917 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3948:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu8bh:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
29536 /* 81917 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29537 /* 81920 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29538 /* 81924 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29539 /* 81929 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8bh),
29540 /* 81932 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29541 /* 81934 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29542 /* 81936 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29543 /* 81939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29544 /* 81945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29545 /* 81951 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29546 /* 81954 */ GIR_RootConstrainSelectedInstOperands,
29547 /* 81955 */ // GIR_Coverage, 4101,
29548 /* 81955 */ GIR_EraseRootFromParent_Done,
29549 /* 81956 */ // Label 1632: @81956
29550 /* 81956 */ GIM_Try, /*On fail goto*//*Label 1633*/ GIMT_Encode4(82040), // Rule ID 4105 //
29551 /* 81961 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29552 /* 81966 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29553 /* 81969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29554 /* 81972 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29555 /* 81975 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29556 /* 81978 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29557 /* 81981 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29558 /* 81985 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29559 /* 81989 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 8,
29560 /* 81993 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29561 /* 81997 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29562 /* 82001 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3948:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$src, 8:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu8th:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$src)
29563 /* 82001 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29564 /* 82004 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29565 /* 82008 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29566 /* 82013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu8th),
29567 /* 82016 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29568 /* 82018 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29569 /* 82020 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29570 /* 82023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29571 /* 82029 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29572 /* 82035 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29573 /* 82038 */ GIR_RootConstrainSelectedInstOperands,
29574 /* 82039 */ // GIR_Coverage, 4105,
29575 /* 82039 */ GIR_EraseRootFromParent_Done,
29576 /* 82040 */ // Label 1633: @82040
29577 /* 82040 */ GIM_Try, /*On fail goto*//*Label 1634*/ GIMT_Encode4(82124), // Rule ID 4109 //
29578 /* 82045 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29579 /* 82050 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29580 /* 82053 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29581 /* 82056 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29582 /* 82059 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29583 /* 82062 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29584 /* 82065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29585 /* 82069 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29586 /* 82073 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
29587 /* 82077 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29588 /* 82081 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29589 /* 82085 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3948:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHLL_lwu16bh:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
29590 /* 82085 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29591 /* 82088 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29592 /* 82092 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29593 /* 82097 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16bh),
29594 /* 82100 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29595 /* 82102 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29596 /* 82104 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29597 /* 82107 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29598 /* 82113 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29599 /* 82119 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29600 /* 82122 */ GIR_RootConstrainSelectedInstOperands,
29601 /* 82123 */ // GIR_Coverage, 4109,
29602 /* 82123 */ GIR_EraseRootFromParent_Done,
29603 /* 82124 */ // Label 1634: @82124
29604 /* 82124 */ GIM_Try, /*On fail goto*//*Label 1635*/ GIMT_Encode4(82208), // Rule ID 4113 //
29605 /* 82129 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshll_imm),
29606 /* 82134 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29607 /* 82137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29608 /* 82140 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29609 /* 82143 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29610 /* 82146 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29611 /* 82149 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29612 /* 82153 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29613 /* 82157 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 16,
29614 /* 82161 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29615 /* 82165 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29616 /* 82169 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3948:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$src, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHLL_lwu16th:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$src)
29617 /* 82169 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29618 /* 82172 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29619 /* 82176 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29620 /* 82181 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHLL_lwu16th),
29621 /* 82184 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29622 /* 82186 */ GIR_RootToRootCopy, /*OpIdx*/2, // src
29623 /* 82188 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29624 /* 82191 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29625 /* 82197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29626 /* 82203 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29627 /* 82206 */ GIR_RootConstrainSelectedInstOperands,
29628 /* 82207 */ // GIR_Coverage, 4113,
29629 /* 82207 */ GIR_EraseRootFromParent_Done,
29630 /* 82208 */ // Label 1635: @82208
29631 /* 82208 */ GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(82297), // Rule ID 4841 //
29632 /* 82213 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29633 /* 82216 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29634 /* 82221 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29635 /* 82224 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29636 /* 82227 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29637 /* 82230 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29638 /* 82233 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29639 /* 82236 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29640 /* 82240 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29641 /* 82244 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29642 /* 82248 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29643 /* 82252 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29644 /* 82256 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3898:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
29645 /* 82256 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29646 /* 82259 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29647 /* 82263 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29648 /* 82268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs8),
29649 /* 82271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29650 /* 82273 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29651 /* 82275 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29652 /* 82277 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29653 /* 82280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29654 /* 82286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29655 /* 82292 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29656 /* 82295 */ GIR_RootConstrainSelectedInstOperands,
29657 /* 82296 */ // GIR_Coverage, 4841,
29658 /* 82296 */ GIR_EraseRootFromParent_Done,
29659 /* 82297 */ // Label 1636: @82297
29660 /* 82297 */ GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(82386), // Rule ID 4843 //
29661 /* 82302 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29662 /* 82305 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29663 /* 82310 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29664 /* 82313 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29665 /* 82316 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29666 /* 82319 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29667 /* 82322 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29668 /* 82325 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29669 /* 82329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29670 /* 82333 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29671 /* 82337 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29672 /* 82341 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29673 /* 82345 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3898:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
29674 /* 82345 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29675 /* 82348 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29676 /* 82352 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29677 /* 82357 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs8),
29678 /* 82360 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29679 /* 82362 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29680 /* 82364 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29681 /* 82366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29682 /* 82369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29683 /* 82375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29684 /* 82381 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29685 /* 82384 */ GIR_RootConstrainSelectedInstOperands,
29686 /* 82385 */ // GIR_Coverage, 4843,
29687 /* 82385 */ GIR_EraseRootFromParent_Done,
29688 /* 82386 */ // Label 1637: @82386
29689 /* 82386 */ GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(82475), // Rule ID 4845 //
29690 /* 82391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29691 /* 82394 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29692 /* 82399 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29693 /* 82402 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29694 /* 82405 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29695 /* 82408 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29696 /* 82411 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29697 /* 82414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29698 /* 82418 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29699 /* 82422 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29700 /* 82426 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29701 /* 82430 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29702 /* 82434 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3898:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29703 /* 82434 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29704 /* 82437 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29705 /* 82441 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29706 /* 82446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs16),
29707 /* 82449 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29708 /* 82451 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29709 /* 82453 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29710 /* 82455 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29711 /* 82458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29712 /* 82464 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29713 /* 82470 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29714 /* 82473 */ GIR_RootConstrainSelectedInstOperands,
29715 /* 82474 */ // GIR_Coverage, 4845,
29716 /* 82474 */ GIR_EraseRootFromParent_Done,
29717 /* 82475 */ // Label 1638: @82475
29718 /* 82475 */ GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(82564), // Rule ID 4847 //
29719 /* 82480 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29720 /* 82483 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29721 /* 82488 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29722 /* 82491 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29723 /* 82494 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29724 /* 82497 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29725 /* 82500 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29726 /* 82503 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29727 /* 82507 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29728 /* 82511 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29729 /* 82515 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29730 /* 82519 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29731 /* 82523 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3898:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29732 /* 82523 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29733 /* 82526 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29734 /* 82530 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29735 /* 82535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs16),
29736 /* 82538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29737 /* 82540 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29738 /* 82542 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29739 /* 82544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29740 /* 82547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29741 /* 82553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29742 /* 82559 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29743 /* 82562 */ GIR_RootConstrainSelectedInstOperands,
29744 /* 82563 */ // GIR_Coverage, 4847,
29745 /* 82563 */ GIR_EraseRootFromParent_Done,
29746 /* 82564 */ // Label 1639: @82564
29747 /* 82564 */ GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(82653), // Rule ID 4849 //
29748 /* 82569 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29749 /* 82572 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29750 /* 82577 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
29751 /* 82580 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29752 /* 82583 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29753 /* 82586 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29754 /* 82589 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29755 /* 82592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29756 /* 82596 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29757 /* 82600 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29758 /* 82604 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29759 /* 82608 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29760 /* 82612 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3898:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29761 /* 82612 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29762 /* 82615 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29763 /* 82619 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29764 /* 82624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBs32),
29765 /* 82627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29766 /* 82629 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29767 /* 82631 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29768 /* 82633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29769 /* 82636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29770 /* 82642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29771 /* 82648 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29772 /* 82651 */ GIR_RootConstrainSelectedInstOperands,
29773 /* 82652 */ // GIR_Coverage, 4849,
29774 /* 82652 */ GIR_EraseRootFromParent_Done,
29775 /* 82653 */ // Label 1640: @82653
29776 /* 82653 */ GIM_Try, /*On fail goto*//*Label 1641*/ GIMT_Encode4(82742), // Rule ID 4851 //
29777 /* 82658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29778 /* 82661 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29779 /* 82666 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
29780 /* 82669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29781 /* 82672 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29782 /* 82675 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29783 /* 82678 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29784 /* 82681 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29785 /* 82685 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29786 /* 82689 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29787 /* 82693 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
29788 /* 82697 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29789 /* 82701 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3898:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTs32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29790 /* 82701 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29791 /* 82704 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29792 /* 82708 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29793 /* 82713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTs32),
29794 /* 82716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29795 /* 82718 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29796 /* 82720 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29797 /* 82722 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29798 /* 82725 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29799 /* 82731 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29800 /* 82737 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29801 /* 82740 */ GIR_RootConstrainSelectedInstOperands,
29802 /* 82741 */ // GIR_Coverage, 4851,
29803 /* 82741 */ GIR_EraseRootFromParent_Done,
29804 /* 82742 */ // Label 1641: @82742
29805 /* 82742 */ GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(82831), // Rule ID 4853 //
29806 /* 82747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29807 /* 82750 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29808 /* 82755 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29809 /* 82758 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29810 /* 82761 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29811 /* 82764 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29812 /* 82767 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29813 /* 82770 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29814 /* 82774 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29815 /* 82778 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29816 /* 82782 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29817 /* 82786 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29818 /* 82790 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3898:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
29819 /* 82790 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29820 /* 82793 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29821 /* 82797 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29822 /* 82802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu8),
29823 /* 82805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29824 /* 82807 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29825 /* 82809 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29826 /* 82811 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29827 /* 82814 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29828 /* 82820 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29829 /* 82826 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29830 /* 82829 */ GIR_RootConstrainSelectedInstOperands,
29831 /* 82830 */ // GIR_Coverage, 4853,
29832 /* 82830 */ GIR_EraseRootFromParent_Done,
29833 /* 82831 */ // Label 1642: @82831
29834 /* 82831 */ GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(82920), // Rule ID 4855 //
29835 /* 82836 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29836 /* 82839 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29837 /* 82844 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29838 /* 82847 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
29839 /* 82850 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
29840 /* 82853 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29841 /* 82856 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29842 /* 82859 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29843 /* 82863 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29844 /* 82867 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29845 /* 82871 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29846 /* 82875 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29847 /* 82879 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3898:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu8:{ *:[v8i16] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
29848 /* 82879 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29849 /* 82882 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29850 /* 82886 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29851 /* 82891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu8),
29852 /* 82894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29853 /* 82896 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29854 /* 82898 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29855 /* 82900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29856 /* 82903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29857 /* 82909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29858 /* 82915 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29859 /* 82918 */ GIR_RootConstrainSelectedInstOperands,
29860 /* 82919 */ // GIR_Coverage, 4855,
29861 /* 82919 */ GIR_EraseRootFromParent_Done,
29862 /* 82920 */ // Label 1643: @82920
29863 /* 82920 */ GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(83009), // Rule ID 4857 //
29864 /* 82925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29865 /* 82928 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29866 /* 82933 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29867 /* 82936 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29868 /* 82939 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29869 /* 82942 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29870 /* 82945 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29871 /* 82948 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29872 /* 82952 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29873 /* 82956 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29874 /* 82960 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29875 /* 82964 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29876 /* 82968 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3898:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29877 /* 82968 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29878 /* 82971 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29879 /* 82975 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29880 /* 82980 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu16),
29881 /* 82983 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29882 /* 82985 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29883 /* 82987 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29884 /* 82989 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29885 /* 82992 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29886 /* 82998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29887 /* 83004 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29888 /* 83007 */ GIR_RootConstrainSelectedInstOperands,
29889 /* 83008 */ // GIR_Coverage, 4857,
29890 /* 83008 */ GIR_EraseRootFromParent_Done,
29891 /* 83009 */ // Label 1644: @83009
29892 /* 83009 */ GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(83098), // Rule ID 4859 //
29893 /* 83014 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29894 /* 83017 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29895 /* 83022 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
29896 /* 83025 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
29897 /* 83028 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
29898 /* 83031 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29899 /* 83034 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29900 /* 83037 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29901 /* 83041 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29902 /* 83045 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29903 /* 83049 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29904 /* 83053 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29905 /* 83057 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3898:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu16:{ *:[v4i32] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
29906 /* 83057 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29907 /* 83060 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29908 /* 83064 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29909 /* 83069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu16),
29910 /* 83072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29911 /* 83074 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29912 /* 83076 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29913 /* 83078 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29914 /* 83081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29915 /* 83087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29916 /* 83093 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29917 /* 83096 */ GIR_RootConstrainSelectedInstOperands,
29918 /* 83097 */ // GIR_Coverage, 4859,
29919 /* 83097 */ GIR_EraseRootFromParent_Done,
29920 /* 83098 */ // Label 1645: @83098
29921 /* 83098 */ GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(83187), // Rule ID 4861 //
29922 /* 83103 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29923 /* 83106 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29924 /* 83111 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
29925 /* 83114 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29926 /* 83117 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29927 /* 83120 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29928 /* 83123 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29929 /* 83126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29930 /* 83130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29931 /* 83134 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29932 /* 83138 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29933 /* 83142 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
29934 /* 83146 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3898:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VMULLBu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29935 /* 83146 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29936 /* 83149 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29937 /* 83153 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29938 /* 83158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLBu32),
29939 /* 83161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29940 /* 83163 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29941 /* 83165 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29942 /* 83167 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29943 /* 83170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29944 /* 83176 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29945 /* 83182 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29946 /* 83185 */ GIR_RootConstrainSelectedInstOperands,
29947 /* 83186 */ // GIR_Coverage, 4861,
29948 /* 83186 */ GIR_EraseRootFromParent_Done,
29949 /* 83187 */ // Label 1646: @83187
29950 /* 83187 */ GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(83276), // Rule ID 4863 //
29951 /* 83192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
29952 /* 83195 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmull),
29953 /* 83200 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
29954 /* 83203 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
29955 /* 83206 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
29956 /* 83209 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
29957 /* 83212 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
29958 /* 83215 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29959 /* 83219 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29960 /* 83223 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29961 /* 83227 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
29962 /* 83231 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
29963 /* 83235 */ // (intrinsic_wo_chain:{ *:[v2i64] } 3898:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VMULLTu32:{ *:[v2i64] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
29964 /* 83235 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29965 /* 83238 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29966 /* 83242 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
29967 /* 83247 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULLTu32),
29968 /* 83250 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
29969 /* 83252 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qm
29970 /* 83254 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qn
29971 /* 83256 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
29972 /* 83259 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29973 /* 83265 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
29974 /* 83271 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
29975 /* 83274 */ GIR_RootConstrainSelectedInstOperands,
29976 /* 83275 */ // GIR_Coverage, 4863,
29977 /* 83275 */ GIR_EraseRootFromParent_Done,
29978 /* 83276 */ // Label 1647: @83276
29979 /* 83276 */ GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(83374), // Rule ID 4426 //
29980 /* 83281 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
29981 /* 83284 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
29982 /* 83289 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
29983 /* 83292 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
29984 /* 83295 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
29985 /* 83298 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
29986 /* 83301 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
29987 /* 83304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29988 /* 83308 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
29989 /* 83312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
29990 /* 83316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
29991 /* 83320 */ // MIs[1] Operand 1
29992 /* 83320 */ // No operand predicates
29993 /* 83320 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29994 /* 83324 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
29995 /* 83328 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
29996 /* 83330 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3836:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
29997 /* 83330 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
29998 /* 83333 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
29999 /* 83337 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30000 /* 83342 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf16),
30001 /* 83345 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30002 /* 83347 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30003 /* 83349 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30004 /* 83351 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
30005 /* 83354 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30006 /* 83357 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30007 /* 83363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30008 /* 83369 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30009 /* 83372 */ GIR_RootConstrainSelectedInstOperands,
30010 /* 83373 */ // GIR_Coverage, 4426,
30011 /* 83373 */ GIR_EraseRootFromParent_Done,
30012 /* 83374 */ // Label 1648: @83374
30013 /* 83374 */ GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(83472), // Rule ID 4428 //
30014 /* 83379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
30015 /* 83382 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
30016 /* 83387 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30017 /* 83390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30018 /* 83393 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30019 /* 83396 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
30020 /* 83399 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
30021 /* 83402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30022 /* 83406 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30023 /* 83410 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
30024 /* 83414 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30025 /* 83418 */ // MIs[1] Operand 1
30026 /* 83418 */ // No operand predicates
30027 /* 83418 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30028 /* 83422 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30029 /* 83426 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
30030 /* 83428 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3836:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
30031 /* 83428 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30032 /* 83431 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30033 /* 83435 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30034 /* 83440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDf32),
30035 /* 83443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30036 /* 83445 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30037 /* 83447 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30038 /* 83449 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
30039 /* 83452 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30040 /* 83455 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30041 /* 83461 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30042 /* 83467 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30043 /* 83470 */ GIR_RootConstrainSelectedInstOperands,
30044 /* 83471 */ // GIR_Coverage, 4428,
30045 /* 83471 */ GIR_EraseRootFromParent_Done,
30046 /* 83472 */ // Label 1649: @83472
30047 /* 83472 */ GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(83570), // Rule ID 4995 //
30048 /* 83477 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
30049 /* 83480 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
30050 /* 83485 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30051 /* 83488 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30052 /* 83491 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30053 /* 83494 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30054 /* 83497 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8,
30055 /* 83500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30056 /* 83504 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30057 /* 83508 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
30058 /* 83512 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30059 /* 83516 */ // MIs[1] Operand 1
30060 /* 83516 */ // No operand predicates
30061 /* 83516 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30062 /* 83520 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30063 /* 83524 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
30064 /* 83526 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3836:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VCADDi8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
30065 /* 83526 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30066 /* 83529 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30067 /* 83533 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30068 /* 83538 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi8),
30069 /* 83541 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30070 /* 83543 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30071 /* 83545 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30072 /* 83547 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
30073 /* 83550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30074 /* 83553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30075 /* 83559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30076 /* 83565 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30077 /* 83568 */ GIR_RootConstrainSelectedInstOperands,
30078 /* 83569 */ // GIR_Coverage, 4995,
30079 /* 83569 */ GIR_EraseRootFromParent_Done,
30080 /* 83570 */ // Label 1650: @83570
30081 /* 83570 */ GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(83668), // Rule ID 4997 //
30082 /* 83575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
30083 /* 83578 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
30084 /* 83583 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30085 /* 83586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30086 /* 83589 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30087 /* 83592 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
30088 /* 83595 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
30089 /* 83598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30090 /* 83602 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30091 /* 83606 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
30092 /* 83610 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30093 /* 83614 */ // MIs[1] Operand 1
30094 /* 83614 */ // No operand predicates
30095 /* 83614 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30096 /* 83618 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30097 /* 83622 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
30098 /* 83624 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3836:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VCADDi16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
30099 /* 83624 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30100 /* 83627 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30101 /* 83631 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30102 /* 83636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi16),
30103 /* 83639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30104 /* 83641 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30105 /* 83643 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30106 /* 83645 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
30107 /* 83648 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30108 /* 83651 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30109 /* 83657 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30110 /* 83663 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30111 /* 83666 */ GIR_RootConstrainSelectedInstOperands,
30112 /* 83667 */ // GIR_Coverage, 4997,
30113 /* 83667 */ GIR_EraseRootFromParent_Done,
30114 /* 83668 */ // Label 1651: @83668
30115 /* 83668 */ GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(83766), // Rule ID 4999 //
30116 /* 83673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
30117 /* 83676 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
30118 /* 83681 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30119 /* 83684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30120 /* 83687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30121 /* 83690 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
30122 /* 83693 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
30123 /* 83696 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30124 /* 83700 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30125 /* 83704 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
30126 /* 83708 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30127 /* 83712 */ // MIs[1] Operand 1
30128 /* 83712 */ // No operand predicates
30129 /* 83712 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30130 /* 83716 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30131 /* 83720 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
30132 /* 83722 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3836:{ *:[iPTR] }, 1:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VCADDi32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
30133 /* 83722 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30134 /* 83725 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30135 /* 83729 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30136 /* 83734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCADDi32),
30137 /* 83737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30138 /* 83739 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30139 /* 83741 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30140 /* 83743 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
30141 /* 83746 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30142 /* 83749 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30143 /* 83755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30144 /* 83761 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30145 /* 83764 */ GIR_RootConstrainSelectedInstOperands,
30146 /* 83765 */ // GIR_Coverage, 4999,
30147 /* 83765 */ GIR_EraseRootFromParent_Done,
30148 /* 83766 */ // Label 1652: @83766
30149 /* 83766 */ GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(83864), // Rule ID 5001 //
30150 /* 83771 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
30151 /* 83774 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
30152 /* 83779 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30153 /* 83782 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30154 /* 83785 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30155 /* 83788 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30156 /* 83791 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8,
30157 /* 83794 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30158 /* 83798 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30159 /* 83802 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
30160 /* 83806 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30161 /* 83810 */ // MIs[1] Operand 1
30162 /* 83810 */ // No operand predicates
30163 /* 83810 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30164 /* 83814 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30165 /* 83818 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
30166 /* 83820 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3836:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VHCADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm, (imm:{ *:[i32] }):$rot)
30167 /* 83820 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30168 /* 83823 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30169 /* 83827 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30170 /* 83832 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs8),
30171 /* 83835 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30172 /* 83837 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30173 /* 83839 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30174 /* 83841 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
30175 /* 83844 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30176 /* 83847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30177 /* 83853 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30178 /* 83859 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30179 /* 83862 */ GIR_RootConstrainSelectedInstOperands,
30180 /* 83863 */ // GIR_Coverage, 5001,
30181 /* 83863 */ GIR_EraseRootFromParent_Done,
30182 /* 83864 */ // Label 1653: @83864
30183 /* 83864 */ GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(83962), // Rule ID 5003 //
30184 /* 83869 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
30185 /* 83872 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
30186 /* 83877 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30187 /* 83880 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30188 /* 83883 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30189 /* 83886 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
30190 /* 83889 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
30191 /* 83892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30192 /* 83896 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30193 /* 83900 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
30194 /* 83904 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30195 /* 83908 */ // MIs[1] Operand 1
30196 /* 83908 */ // No operand predicates
30197 /* 83908 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30198 /* 83912 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30199 /* 83916 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
30200 /* 83918 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3836:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VHCADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$rot)
30201 /* 83918 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30202 /* 83921 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30203 /* 83925 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30204 /* 83930 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs16),
30205 /* 83933 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30206 /* 83935 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30207 /* 83937 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30208 /* 83939 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
30209 /* 83942 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30210 /* 83945 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30211 /* 83951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30212 /* 83957 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30213 /* 83960 */ GIR_RootConstrainSelectedInstOperands,
30214 /* 83961 */ // GIR_Coverage, 5003,
30215 /* 83961 */ GIR_EraseRootFromParent_Done,
30216 /* 83962 */ // Label 1654: @83962
30217 /* 83962 */ GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(84060), // Rule ID 5005 //
30218 /* 83967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
30219 /* 83970 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcaddq),
30220 /* 83975 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30221 /* 83978 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30222 /* 83981 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30223 /* 83984 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
30224 /* 83987 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
30225 /* 83990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30226 /* 83994 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30227 /* 83998 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
30228 /* 84002 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30229 /* 84006 */ // MIs[1] Operand 1
30230 /* 84006 */ // No operand predicates
30231 /* 84006 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30232 /* 84010 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30233 /* 84014 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
30234 /* 84016 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3836:{ *:[iPTR] }, 0:{ *:[i32] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VHCADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$rot)
30235 /* 84016 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30236 /* 84019 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30237 /* 84023 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30238 /* 84028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VHCADDs32),
30239 /* 84031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30240 /* 84033 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30241 /* 84035 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30242 /* 84037 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
30243 /* 84040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30244 /* 84043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30245 /* 84049 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30246 /* 84055 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30247 /* 84058 */ GIR_RootConstrainSelectedInstOperands,
30248 /* 84059 */ // GIR_Coverage, 5005,
30249 /* 84059 */ GIR_EraseRootFromParent_Done,
30250 /* 84060 */ // Label 1655: @84060
30251 /* 84060 */ GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(84136), // Rule ID 3389 //
30252 /* 84065 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
30253 /* 84068 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
30254 /* 84073 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
30255 /* 84076 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30256 /* 84079 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30257 /* 84082 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30258 /* 84085 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8,
30259 /* 84088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30260 /* 84092 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30261 /* 84096 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30262 /* 84100 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30263 /* 84104 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30264 /* 84108 */ // (intrinsic_wo_chain:{ *:[i32] } 3828:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVs8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30265 /* 84108 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs8),
30266 /* 84111 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
30267 /* 84113 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
30268 /* 84115 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30269 /* 84117 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30270 /* 84119 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30271 /* 84122 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30272 /* 84128 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30273 /* 84134 */ GIR_RootConstrainSelectedInstOperands,
30274 /* 84135 */ // GIR_Coverage, 3389,
30275 /* 84135 */ GIR_EraseRootFromParent_Done,
30276 /* 84136 */ // Label 1656: @84136
30277 /* 84136 */ GIM_Try, /*On fail goto*//*Label 1657*/ GIMT_Encode4(84212), // Rule ID 3391 //
30278 /* 84141 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
30279 /* 84144 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
30280 /* 84149 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
30281 /* 84152 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30282 /* 84155 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30283 /* 84158 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
30284 /* 84161 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
30285 /* 84164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30286 /* 84168 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30287 /* 84172 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30288 /* 84176 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30289 /* 84180 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30290 /* 84184 */ // (intrinsic_wo_chain:{ *:[i32] } 3828:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVs16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30291 /* 84184 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs16),
30292 /* 84187 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
30293 /* 84189 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
30294 /* 84191 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30295 /* 84193 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30296 /* 84195 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30297 /* 84198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30298 /* 84204 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30299 /* 84210 */ GIR_RootConstrainSelectedInstOperands,
30300 /* 84211 */ // GIR_Coverage, 3391,
30301 /* 84211 */ GIR_EraseRootFromParent_Done,
30302 /* 84212 */ // Label 1657: @84212
30303 /* 84212 */ GIM_Try, /*On fail goto*//*Label 1658*/ GIMT_Encode4(84288), // Rule ID 3393 //
30304 /* 84217 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
30305 /* 84220 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
30306 /* 84225 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
30307 /* 84228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30308 /* 84231 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30309 /* 84234 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
30310 /* 84237 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
30311 /* 84240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30312 /* 84244 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
30313 /* 84248 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30314 /* 84252 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30315 /* 84256 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30316 /* 84260 */ // (intrinsic_wo_chain:{ *:[i32] } 3828:{ *:[iPTR] }, 0:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVs32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
30317 /* 84260 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVs32),
30318 /* 84263 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
30319 /* 84265 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
30320 /* 84267 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30321 /* 84269 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30322 /* 84271 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30323 /* 84274 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30324 /* 84280 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30325 /* 84286 */ GIR_RootConstrainSelectedInstOperands,
30326 /* 84287 */ // GIR_Coverage, 3393,
30327 /* 84287 */ GIR_EraseRootFromParent_Done,
30328 /* 84288 */ // Label 1658: @84288
30329 /* 84288 */ GIM_Try, /*On fail goto*//*Label 1659*/ GIMT_Encode4(84364), // Rule ID 3395 //
30330 /* 84293 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
30331 /* 84296 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
30332 /* 84301 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
30333 /* 84304 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30334 /* 84307 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30335 /* 84310 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
30336 /* 84313 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v16s8,
30337 /* 84316 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30338 /* 84320 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30339 /* 84324 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30340 /* 84328 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30341 /* 84332 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30342 /* 84336 */ // (intrinsic_wo_chain:{ *:[i32] } 3828:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VABAVu8:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
30343 /* 84336 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu8),
30344 /* 84339 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
30345 /* 84341 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
30346 /* 84343 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30347 /* 84345 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30348 /* 84347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30349 /* 84350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30350 /* 84356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30351 /* 84362 */ GIR_RootConstrainSelectedInstOperands,
30352 /* 84363 */ // GIR_Coverage, 3395,
30353 /* 84363 */ GIR_EraseRootFromParent_Done,
30354 /* 84364 */ // Label 1659: @84364
30355 /* 84364 */ GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(84440), // Rule ID 3397 //
30356 /* 84369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
30357 /* 84372 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
30358 /* 84377 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
30359 /* 84380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30360 /* 84383 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30361 /* 84386 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
30362 /* 84389 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
30363 /* 84392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30364 /* 84396 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30365 /* 84400 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30366 /* 84404 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30367 /* 84408 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30368 /* 84412 */ // (intrinsic_wo_chain:{ *:[i32] } 3828:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VABAVu16:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
30369 /* 84412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu16),
30370 /* 84415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
30371 /* 84417 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
30372 /* 84419 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30373 /* 84421 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30374 /* 84423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30375 /* 84426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30376 /* 84432 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30377 /* 84438 */ GIR_RootConstrainSelectedInstOperands,
30378 /* 84439 */ // GIR_Coverage, 3397,
30379 /* 84439 */ GIR_EraseRootFromParent_Done,
30380 /* 84440 */ // Label 1660: @84440
30381 /* 84440 */ GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(84516), // Rule ID 3399 //
30382 /* 84445 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
30383 /* 84448 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vabav),
30384 /* 84453 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
30385 /* 84456 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30386 /* 84459 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
30387 /* 84462 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
30388 /* 84465 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
30389 /* 84468 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30390 /* 84472 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
30391 /* 84476 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
30392 /* 84480 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30393 /* 84484 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30394 /* 84488 */ // (intrinsic_wo_chain:{ *:[i32] } 3828:{ *:[iPTR] }, 1:{ *:[i32] }, rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VABAVu32:{ *:[i32] } rGPR:{ *:[i32] }:$Rda_src, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
30395 /* 84488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABAVu32),
30396 /* 84491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
30397 /* 84493 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rda_src
30398 /* 84495 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30399 /* 84497 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30400 /* 84499 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30401 /* 84502 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30402 /* 84508 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30403 /* 84514 */ GIR_RootConstrainSelectedInstOperands,
30404 /* 84515 */ // GIR_Coverage, 3399,
30405 /* 84515 */ GIR_EraseRootFromParent_Done,
30406 /* 84516 */ // Label 1661: @84516
30407 /* 84516 */ GIM_Try, /*On fail goto*//*Label 1662*/ GIMT_Encode4(84601), // Rule ID 4372 //
30408 /* 84521 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
30409 /* 84524 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq),
30410 /* 84529 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30411 /* 84532 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30412 /* 84535 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
30413 /* 84538 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
30414 /* 84541 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s16,
30415 /* 84544 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30416 /* 84548 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
30417 /* 84552 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30418 /* 84556 */ // MIs[1] Operand 1
30419 /* 84556 */ // No operand predicates
30420 /* 84556 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30421 /* 84560 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30422 /* 84564 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30423 /* 84568 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
30424 /* 84570 */ // (intrinsic_wo_chain:{ *:[v8f16] } 3839:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm) => (MVE_VCMLAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd_src, MQPR:{ *:[v8f16] }:$Qn, MQPR:{ *:[v8f16] }:$Qm, (imm:{ *:[i32] }):$rot)
30425 /* 84570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf16),
30426 /* 84573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30427 /* 84575 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src
30428 /* 84577 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30429 /* 84579 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30430 /* 84581 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
30431 /* 84584 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30432 /* 84587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30433 /* 84593 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30434 /* 84599 */ GIR_RootConstrainSelectedInstOperands,
30435 /* 84600 */ // GIR_Coverage, 4372,
30436 /* 84600 */ GIR_EraseRootFromParent_Done,
30437 /* 84601 */ // Label 1662: @84601
30438 /* 84601 */ GIM_Try, /*On fail goto*//*Label 1663*/ GIMT_Encode4(84686), // Rule ID 4375 //
30439 /* 84606 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
30440 /* 84609 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vcmlaq),
30441 /* 84614 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30442 /* 84617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
30443 /* 84620 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30444 /* 84623 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
30445 /* 84626 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32,
30446 /* 84629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30447 /* 84633 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
30448 /* 84637 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
30449 /* 84641 */ // MIs[1] Operand 1
30450 /* 84641 */ // No operand predicates
30451 /* 84641 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30452 /* 84645 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30453 /* 84649 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30454 /* 84653 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
30455 /* 84655 */ // (intrinsic_wo_chain:{ *:[v4f32] } 3839:{ *:[iPTR] }, (imm:{ *:[i32] }):$rot, MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm) => (MVE_VCMLAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd_src, MQPR:{ *:[v4f32] }:$Qn, MQPR:{ *:[v4f32] }:$Qm, (imm:{ *:[i32] }):$rot)
30456 /* 84655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMLAf32),
30457 /* 84658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30458 /* 84660 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qd_src
30459 /* 84662 */ GIR_RootToRootCopy, /*OpIdx*/4, // Qn
30460 /* 84664 */ GIR_RootToRootCopy, /*OpIdx*/5, // Qm
30461 /* 84666 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // rot
30462 /* 84669 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30463 /* 84672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30464 /* 84678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30465 /* 84684 */ GIR_RootConstrainSelectedInstOperands,
30466 /* 84685 */ // GIR_Coverage, 4375,
30467 /* 84685 */ GIR_EraseRootFromParent_Done,
30468 /* 84686 */ // Label 1663: @84686
30469 /* 84686 */ GIM_Try, /*On fail goto*//*Label 1664*/ GIMT_Encode4(84782), // Rule ID 3038 //
30470 /* 84691 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
30471 /* 84694 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx2),
30472 /* 84699 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
30473 /* 84702 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
30474 /* 84705 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
30475 /* 84708 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
30476 /* 84711 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
30477 /* 84714 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
30478 /* 84718 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4100:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vm) => (VTBX2:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v16i8] } DPair:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
30479 /* 84718 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
30480 /* 84721 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
30481 /* 84725 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30482 /* 84730 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
30483 /* 84734 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
30484 /* 84737 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
30485 /* 84741 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
30486 /* 84744 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPairRegClassID),
30487 /* 84749 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
30488 /* 84754 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
30489 /* 84759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX2),
30490 /* 84762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
30491 /* 84764 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
30492 /* 84766 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30493 /* 84769 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm
30494 /* 84771 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
30495 /* 84774 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30496 /* 84780 */ GIR_RootConstrainSelectedInstOperands,
30497 /* 84781 */ // GIR_Coverage, 3038,
30498 /* 84781 */ GIR_EraseRootFromParent_Done,
30499 /* 84782 */ // Label 1664: @84782
30500 /* 84782 */ GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(84913), // Rule ID 3039 //
30501 /* 84787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
30502 /* 84790 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl3),
30503 /* 84795 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
30504 /* 84798 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
30505 /* 84801 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
30506 /* 84804 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
30507 /* 84807 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
30508 /* 84810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
30509 /* 84814 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4097:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBL3Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
30510 /* 84814 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
30511 /* 84817 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30512 /* 84821 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30513 /* 84826 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
30514 /* 84828 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
30515 /* 84831 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
30516 /* 84835 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30517 /* 84840 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
30518 /* 84844 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
30519 /* 84847 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
30520 /* 84851 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
30521 /* 84854 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
30522 /* 84858 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
30523 /* 84861 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
30524 /* 84864 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
30525 /* 84867 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
30526 /* 84872 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
30527 /* 84877 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
30528 /* 84882 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
30529 /* 84887 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
30530 /* 84892 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL3Pseudo),
30531 /* 84895 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
30532 /* 84897 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30533 /* 84900 */ GIR_RootToRootCopy, /*OpIdx*/5, // Vm
30534 /* 84902 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
30535 /* 84905 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30536 /* 84911 */ GIR_RootConstrainSelectedInstOperands,
30537 /* 84912 */ // GIR_Coverage, 3039,
30538 /* 84912 */ GIR_EraseRootFromParent_Done,
30539 /* 84913 */ // Label 1665: @84913
30540 /* 84913 */ GIM_Reject,
30541 /* 84914 */ // Label 1627: @84914
30542 /* 84914 */ GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(90220),
30543 /* 84919 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
30544 /* 84922 */ GIM_Try, /*On fail goto*//*Label 1667*/ GIMT_Encode4(85015), // Rule ID 4196 //
30545 /* 84927 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30546 /* 84932 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30547 /* 84935 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30548 /* 84938 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30549 /* 84941 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30550 /* 84944 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30551 /* 84947 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30552 /* 84950 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30553 /* 84954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30554 /* 84958 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30555 /* 84962 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30556 /* 84966 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30557 /* 84970 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30558 /* 84974 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3944:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30559 /* 84974 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30560 /* 84977 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30561 /* 84981 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30562 /* 84986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs8),
30563 /* 84989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30564 /* 84991 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30565 /* 84993 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30566 /* 84995 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30567 /* 84998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30568 /* 85004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30569 /* 85010 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30570 /* 85013 */ GIR_RootConstrainSelectedInstOperands,
30571 /* 85014 */ // GIR_Coverage, 4196,
30572 /* 85014 */ GIR_EraseRootFromParent_Done,
30573 /* 85015 */ // Label 1667: @85015
30574 /* 85015 */ GIM_Try, /*On fail goto*//*Label 1668*/ GIMT_Encode4(85108), // Rule ID 4198 //
30575 /* 85020 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30576 /* 85025 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30577 /* 85028 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30578 /* 85031 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
30579 /* 85034 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30580 /* 85037 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30581 /* 85040 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30582 /* 85043 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30583 /* 85047 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30584 /* 85051 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30585 /* 85055 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30586 /* 85059 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30587 /* 85063 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30588 /* 85067 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3944:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30589 /* 85067 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30590 /* 85070 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30591 /* 85074 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30592 /* 85079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs16),
30593 /* 85082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30594 /* 85084 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30595 /* 85086 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30596 /* 85088 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30597 /* 85091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30598 /* 85097 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30599 /* 85103 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30600 /* 85106 */ GIR_RootConstrainSelectedInstOperands,
30601 /* 85107 */ // GIR_Coverage, 4198,
30602 /* 85107 */ GIR_EraseRootFromParent_Done,
30603 /* 85108 */ // Label 1668: @85108
30604 /* 85108 */ GIM_Try, /*On fail goto*//*Label 1669*/ GIMT_Encode4(85201), // Rule ID 4200 //
30605 /* 85113 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30606 /* 85118 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30607 /* 85121 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
30608 /* 85124 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30609 /* 85127 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30610 /* 85130 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30611 /* 85133 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30612 /* 85136 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30613 /* 85140 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30614 /* 85144 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30615 /* 85148 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30616 /* 85152 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30617 /* 85156 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30618 /* 85160 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3944:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30619 /* 85160 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30620 /* 85163 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30621 /* 85167 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30622 /* 85172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecs32),
30623 /* 85175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30624 /* 85177 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30625 /* 85179 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30626 /* 85181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30627 /* 85184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30628 /* 85190 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30629 /* 85196 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30630 /* 85199 */ GIR_RootConstrainSelectedInstOperands,
30631 /* 85200 */ // GIR_Coverage, 4200,
30632 /* 85200 */ GIR_EraseRootFromParent_Done,
30633 /* 85201 */ // Label 1669: @85201
30634 /* 85201 */ GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(85294), // Rule ID 4202 //
30635 /* 85206 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30636 /* 85211 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30637 /* 85214 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30638 /* 85217 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30639 /* 85220 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30640 /* 85223 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30641 /* 85226 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30642 /* 85229 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30643 /* 85233 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30644 /* 85237 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30645 /* 85241 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30646 /* 85245 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30647 /* 85249 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30648 /* 85253 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3944:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30649 /* 85253 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30650 /* 85256 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30651 /* 85260 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30652 /* 85265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu8),
30653 /* 85268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30654 /* 85270 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30655 /* 85272 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30656 /* 85274 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30657 /* 85277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30658 /* 85283 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30659 /* 85289 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30660 /* 85292 */ GIR_RootConstrainSelectedInstOperands,
30661 /* 85293 */ // GIR_Coverage, 4202,
30662 /* 85293 */ GIR_EraseRootFromParent_Done,
30663 /* 85294 */ // Label 1670: @85294
30664 /* 85294 */ GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(85387), // Rule ID 4204 //
30665 /* 85299 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30666 /* 85304 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30667 /* 85307 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30668 /* 85310 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
30669 /* 85313 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30670 /* 85316 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30671 /* 85319 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30672 /* 85322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30673 /* 85326 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30674 /* 85330 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30675 /* 85334 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30676 /* 85338 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30677 /* 85342 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30678 /* 85346 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3944:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30679 /* 85346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30680 /* 85349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30681 /* 85353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30682 /* 85358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu16),
30683 /* 85361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30684 /* 85363 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30685 /* 85365 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30686 /* 85367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30687 /* 85370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30688 /* 85376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30689 /* 85382 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30690 /* 85385 */ GIR_RootConstrainSelectedInstOperands,
30691 /* 85386 */ // GIR_Coverage, 4204,
30692 /* 85386 */ GIR_EraseRootFromParent_Done,
30693 /* 85387 */ // Label 1671: @85387
30694 /* 85387 */ GIM_Try, /*On fail goto*//*Label 1672*/ GIMT_Encode4(85480), // Rule ID 4206 //
30695 /* 85392 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30696 /* 85397 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30697 /* 85400 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
30698 /* 85403 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30699 /* 85406 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30700 /* 85409 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30701 /* 85412 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30702 /* 85415 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30703 /* 85419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30704 /* 85423 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30705 /* 85427 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
30706 /* 85431 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30707 /* 85435 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30708 /* 85439 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3944:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30709 /* 85439 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30710 /* 85442 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30711 /* 85446 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30712 /* 85451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_by_vecu32),
30713 /* 85454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30714 /* 85456 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30715 /* 85458 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30716 /* 85460 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30717 /* 85463 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30718 /* 85469 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30719 /* 85475 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30720 /* 85478 */ GIR_RootConstrainSelectedInstOperands,
30721 /* 85479 */ // GIR_Coverage, 4206,
30722 /* 85479 */ GIR_EraseRootFromParent_Done,
30723 /* 85480 */ // Label 1672: @85480
30724 /* 85480 */ GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(85573), // Rule ID 4208 //
30725 /* 85485 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30726 /* 85490 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30727 /* 85493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30728 /* 85496 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30729 /* 85499 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30730 /* 85502 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30731 /* 85505 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30732 /* 85508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30733 /* 85512 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30734 /* 85516 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30735 /* 85520 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30736 /* 85524 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30737 /* 85528 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30738 /* 85532 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3944:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30739 /* 85532 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30740 /* 85535 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30741 /* 85539 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30742 /* 85544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs8),
30743 /* 85547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30744 /* 85549 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30745 /* 85551 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30746 /* 85553 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30747 /* 85556 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30748 /* 85562 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30749 /* 85568 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30750 /* 85571 */ GIR_RootConstrainSelectedInstOperands,
30751 /* 85572 */ // GIR_Coverage, 4208,
30752 /* 85572 */ GIR_EraseRootFromParent_Done,
30753 /* 85573 */ // Label 1673: @85573
30754 /* 85573 */ GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(85666), // Rule ID 4210 //
30755 /* 85578 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30756 /* 85583 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30757 /* 85586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30758 /* 85589 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
30759 /* 85592 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30760 /* 85595 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30761 /* 85598 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30762 /* 85601 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30763 /* 85605 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30764 /* 85609 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30765 /* 85613 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30766 /* 85617 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30767 /* 85621 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30768 /* 85625 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3944:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30769 /* 85625 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30770 /* 85628 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30771 /* 85632 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30772 /* 85637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs16),
30773 /* 85640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30774 /* 85642 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30775 /* 85644 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30776 /* 85646 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30777 /* 85649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30778 /* 85655 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30779 /* 85661 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30780 /* 85664 */ GIR_RootConstrainSelectedInstOperands,
30781 /* 85665 */ // GIR_Coverage, 4210,
30782 /* 85665 */ GIR_EraseRootFromParent_Done,
30783 /* 85666 */ // Label 1674: @85666
30784 /* 85666 */ GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(85759), // Rule ID 4212 //
30785 /* 85671 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30786 /* 85676 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30787 /* 85679 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
30788 /* 85682 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30789 /* 85685 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30790 /* 85688 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30791 /* 85691 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30792 /* 85694 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30793 /* 85698 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30794 /* 85702 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30795 /* 85706 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30796 /* 85710 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30797 /* 85714 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30798 /* 85718 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3944:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30799 /* 85718 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30800 /* 85721 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30801 /* 85725 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30802 /* 85730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecs32),
30803 /* 85733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30804 /* 85735 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30805 /* 85737 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30806 /* 85739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30807 /* 85742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30808 /* 85748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30809 /* 85754 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30810 /* 85757 */ GIR_RootConstrainSelectedInstOperands,
30811 /* 85758 */ // GIR_Coverage, 4212,
30812 /* 85758 */ GIR_EraseRootFromParent_Done,
30813 /* 85759 */ // Label 1675: @85759
30814 /* 85759 */ GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(85852), // Rule ID 4214 //
30815 /* 85764 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30816 /* 85769 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30817 /* 85772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30818 /* 85775 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30819 /* 85778 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30820 /* 85781 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30821 /* 85784 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30822 /* 85787 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30823 /* 85791 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30824 /* 85795 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30825 /* 85799 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30826 /* 85803 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30827 /* 85807 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30828 /* 85811 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3944:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30829 /* 85811 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30830 /* 85814 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30831 /* 85818 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30832 /* 85823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu8),
30833 /* 85826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30834 /* 85828 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30835 /* 85830 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30836 /* 85832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30837 /* 85835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30838 /* 85841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30839 /* 85847 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30840 /* 85850 */ GIR_RootConstrainSelectedInstOperands,
30841 /* 85851 */ // GIR_Coverage, 4214,
30842 /* 85851 */ GIR_EraseRootFromParent_Done,
30843 /* 85852 */ // Label 1676: @85852
30844 /* 85852 */ GIM_Try, /*On fail goto*//*Label 1677*/ GIMT_Encode4(85945), // Rule ID 4216 //
30845 /* 85857 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30846 /* 85862 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30847 /* 85865 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30848 /* 85868 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
30849 /* 85871 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30850 /* 85874 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30851 /* 85877 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30852 /* 85880 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30853 /* 85884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30854 /* 85888 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30855 /* 85892 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30856 /* 85896 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30857 /* 85900 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30858 /* 85904 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3944:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30859 /* 85904 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30860 /* 85907 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30861 /* 85911 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30862 /* 85916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu16),
30863 /* 85919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30864 /* 85921 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30865 /* 85923 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30866 /* 85925 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30867 /* 85928 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30868 /* 85934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30869 /* 85940 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30870 /* 85943 */ GIR_RootConstrainSelectedInstOperands,
30871 /* 85944 */ // GIR_Coverage, 4216,
30872 /* 85944 */ GIR_EraseRootFromParent_Done,
30873 /* 85945 */ // Label 1677: @85945
30874 /* 85945 */ GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(86038), // Rule ID 4218 //
30875 /* 85950 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30876 /* 85955 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30877 /* 85958 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
30878 /* 85961 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30879 /* 85964 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30880 /* 85967 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30881 /* 85970 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30882 /* 85973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30883 /* 85977 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30884 /* 85981 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30885 /* 85985 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30886 /* 85989 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
30887 /* 85993 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
30888 /* 85997 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3944:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30889 /* 85997 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30890 /* 86000 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30891 /* 86004 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30892 /* 86009 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_by_vecu32),
30893 /* 86012 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30894 /* 86014 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30895 /* 86016 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30896 /* 86018 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30897 /* 86021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30898 /* 86027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30899 /* 86033 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30900 /* 86036 */ GIR_RootConstrainSelectedInstOperands,
30901 /* 86037 */ // GIR_Coverage, 4218,
30902 /* 86037 */ GIR_EraseRootFromParent_Done,
30903 /* 86038 */ // Label 1678: @86038
30904 /* 86038 */ GIM_Try, /*On fail goto*//*Label 1679*/ GIMT_Encode4(86131), // Rule ID 4220 //
30905 /* 86043 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30906 /* 86048 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30907 /* 86051 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30908 /* 86054 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30909 /* 86057 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30910 /* 86060 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30911 /* 86063 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30912 /* 86066 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30913 /* 86070 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30914 /* 86074 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30915 /* 86078 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30916 /* 86082 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30917 /* 86086 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30918 /* 86090 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3944:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
30919 /* 86090 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30920 /* 86093 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30921 /* 86097 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30922 /* 86102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs8),
30923 /* 86105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30924 /* 86107 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30925 /* 86109 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30926 /* 86111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30927 /* 86114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30928 /* 86120 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30929 /* 86126 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30930 /* 86129 */ GIR_RootConstrainSelectedInstOperands,
30931 /* 86130 */ // GIR_Coverage, 4220,
30932 /* 86130 */ GIR_EraseRootFromParent_Done,
30933 /* 86131 */ // Label 1679: @86131
30934 /* 86131 */ GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(86224), // Rule ID 4222 //
30935 /* 86136 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30936 /* 86141 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
30937 /* 86144 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
30938 /* 86147 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
30939 /* 86150 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30940 /* 86153 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30941 /* 86156 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30942 /* 86159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30943 /* 86163 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30944 /* 86167 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30945 /* 86171 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30946 /* 86175 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30947 /* 86179 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30948 /* 86183 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3944:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
30949 /* 86183 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30950 /* 86186 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30951 /* 86190 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30952 /* 86195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs16),
30953 /* 86198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30954 /* 86200 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30955 /* 86202 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30956 /* 86204 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30957 /* 86207 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30958 /* 86213 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30959 /* 86219 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30960 /* 86222 */ GIR_RootConstrainSelectedInstOperands,
30961 /* 86223 */ // GIR_Coverage, 4222,
30962 /* 86223 */ GIR_EraseRootFromParent_Done,
30963 /* 86224 */ // Label 1680: @86224
30964 /* 86224 */ GIM_Try, /*On fail goto*//*Label 1681*/ GIMT_Encode4(86317), // Rule ID 4224 //
30965 /* 86229 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30966 /* 86234 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
30967 /* 86237 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
30968 /* 86240 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
30969 /* 86243 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
30970 /* 86246 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
30971 /* 86249 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
30972 /* 86252 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30973 /* 86256 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30974 /* 86260 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
30975 /* 86264 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
30976 /* 86268 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
30977 /* 86272 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
30978 /* 86276 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3944:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
30979 /* 86276 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
30980 /* 86279 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
30981 /* 86283 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
30982 /* 86288 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecs32),
30983 /* 86291 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
30984 /* 86293 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
30985 /* 86295 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
30986 /* 86297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
30987 /* 86300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30988 /* 86306 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
30989 /* 86312 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
30990 /* 86315 */ GIR_RootConstrainSelectedInstOperands,
30991 /* 86316 */ // GIR_Coverage, 4224,
30992 /* 86316 */ GIR_EraseRootFromParent_Done,
30993 /* 86317 */ // Label 1681: @86317
30994 /* 86317 */ GIM_Try, /*On fail goto*//*Label 1682*/ GIMT_Encode4(86410), // Rule ID 4226 //
30995 /* 86322 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
30996 /* 86327 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
30997 /* 86330 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
30998 /* 86333 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
30999 /* 86336 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31000 /* 86339 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31001 /* 86342 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31002 /* 86345 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31003 /* 86349 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31004 /* 86353 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31005 /* 86357 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31006 /* 86361 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31007 /* 86365 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31008 /* 86369 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3944:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
31009 /* 86369 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
31010 /* 86372 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
31011 /* 86376 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
31012 /* 86381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu8),
31013 /* 86384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31014 /* 86386 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31015 /* 86388 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31016 /* 86390 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31017 /* 86393 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31018 /* 86399 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31019 /* 86405 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31020 /* 86408 */ GIR_RootConstrainSelectedInstOperands,
31021 /* 86409 */ // GIR_Coverage, 4226,
31022 /* 86409 */ GIR_EraseRootFromParent_Done,
31023 /* 86410 */ // Label 1682: @86410
31024 /* 86410 */ GIM_Try, /*On fail goto*//*Label 1683*/ GIMT_Encode4(86503), // Rule ID 4228 //
31025 /* 86415 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
31026 /* 86420 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31027 /* 86423 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31028 /* 86426 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31029 /* 86429 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31030 /* 86432 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31031 /* 86435 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31032 /* 86438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31033 /* 86442 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31034 /* 86446 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31035 /* 86450 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31036 /* 86454 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31037 /* 86458 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31038 /* 86462 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3944:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
31039 /* 86462 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
31040 /* 86465 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
31041 /* 86469 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
31042 /* 86474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu16),
31043 /* 86477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31044 /* 86479 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31045 /* 86481 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31046 /* 86483 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31047 /* 86486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31048 /* 86492 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31049 /* 86498 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31050 /* 86501 */ GIR_RootConstrainSelectedInstOperands,
31051 /* 86502 */ // GIR_Coverage, 4228,
31052 /* 86502 */ GIR_EraseRootFromParent_Done,
31053 /* 86503 */ // Label 1683: @86503
31054 /* 86503 */ GIM_Try, /*On fail goto*//*Label 1684*/ GIMT_Encode4(86596), // Rule ID 4230 //
31055 /* 86508 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
31056 /* 86513 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31057 /* 86516 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31058 /* 86519 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
31059 /* 86522 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31060 /* 86525 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31061 /* 86528 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31062 /* 86531 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31063 /* 86535 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31064 /* 86539 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31065 /* 86543 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31066 /* 86547 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31067 /* 86551 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31068 /* 86555 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3944:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
31069 /* 86555 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
31070 /* 86558 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
31071 /* 86562 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
31072 /* 86567 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_by_vecu32),
31073 /* 86570 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31074 /* 86572 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31075 /* 86574 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31076 /* 86576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31077 /* 86579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31078 /* 86585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31079 /* 86591 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31080 /* 86594 */ GIR_RootConstrainSelectedInstOperands,
31081 /* 86595 */ // GIR_Coverage, 4230,
31082 /* 86595 */ GIR_EraseRootFromParent_Done,
31083 /* 86596 */ // Label 1684: @86596
31084 /* 86596 */ GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(86689), // Rule ID 4232 //
31085 /* 86601 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
31086 /* 86606 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31087 /* 86609 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31088 /* 86612 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
31089 /* 86615 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31090 /* 86618 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31091 /* 86621 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31092 /* 86624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31093 /* 86628 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31094 /* 86632 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31095 /* 86636 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31096 /* 86640 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31097 /* 86644 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31098 /* 86648 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3944:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
31099 /* 86648 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
31100 /* 86651 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
31101 /* 86655 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
31102 /* 86660 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs8),
31103 /* 86663 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31104 /* 86665 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31105 /* 86667 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31106 /* 86669 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31107 /* 86672 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31108 /* 86678 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31109 /* 86684 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31110 /* 86687 */ GIR_RootConstrainSelectedInstOperands,
31111 /* 86688 */ // GIR_Coverage, 4232,
31112 /* 86688 */ GIR_EraseRootFromParent_Done,
31113 /* 86689 */ // Label 1685: @86689
31114 /* 86689 */ GIM_Try, /*On fail goto*//*Label 1686*/ GIMT_Encode4(86782), // Rule ID 4234 //
31115 /* 86694 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
31116 /* 86699 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31117 /* 86702 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31118 /* 86705 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31119 /* 86708 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31120 /* 86711 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31121 /* 86714 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31122 /* 86717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31123 /* 86721 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31124 /* 86725 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31125 /* 86729 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31126 /* 86733 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31127 /* 86737 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31128 /* 86741 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3944:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
31129 /* 86741 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
31130 /* 86744 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
31131 /* 86748 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
31132 /* 86753 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs16),
31133 /* 86756 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31134 /* 86758 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31135 /* 86760 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31136 /* 86762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31137 /* 86765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31138 /* 86771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31139 /* 86777 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31140 /* 86780 */ GIR_RootConstrainSelectedInstOperands,
31141 /* 86781 */ // GIR_Coverage, 4234,
31142 /* 86781 */ GIR_EraseRootFromParent_Done,
31143 /* 86782 */ // Label 1686: @86782
31144 /* 86782 */ GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(86875), // Rule ID 4236 //
31145 /* 86787 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
31146 /* 86792 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31147 /* 86795 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31148 /* 86798 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
31149 /* 86801 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31150 /* 86804 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31151 /* 86807 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31152 /* 86810 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31153 /* 86814 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31154 /* 86818 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31155 /* 86822 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31156 /* 86826 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31157 /* 86830 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31158 /* 86834 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3944:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_by_vecs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
31159 /* 86834 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
31160 /* 86837 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
31161 /* 86841 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
31162 /* 86846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecs32),
31163 /* 86849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31164 /* 86851 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31165 /* 86853 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31166 /* 86855 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31167 /* 86858 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31168 /* 86864 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31169 /* 86870 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31170 /* 86873 */ GIR_RootConstrainSelectedInstOperands,
31171 /* 86874 */ // GIR_Coverage, 4236,
31172 /* 86874 */ GIR_EraseRootFromParent_Done,
31173 /* 86875 */ // Label 1687: @86875
31174 /* 86875 */ GIM_Try, /*On fail goto*//*Label 1688*/ GIMT_Encode4(86968), // Rule ID 4238 //
31175 /* 86880 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
31176 /* 86885 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31177 /* 86888 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31178 /* 86891 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
31179 /* 86894 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31180 /* 86897 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31181 /* 86900 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31182 /* 86903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31183 /* 86907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31184 /* 86911 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31185 /* 86915 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31186 /* 86919 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31187 /* 86923 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31188 /* 86927 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3944:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, MQPR:{ *:[v16i8] }:$sh)
31189 /* 86927 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
31190 /* 86930 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
31191 /* 86934 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
31192 /* 86939 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu8),
31193 /* 86942 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31194 /* 86944 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31195 /* 86946 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31196 /* 86948 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31197 /* 86951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31198 /* 86957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31199 /* 86963 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31200 /* 86966 */ GIR_RootConstrainSelectedInstOperands,
31201 /* 86967 */ // GIR_Coverage, 4238,
31202 /* 86967 */ GIR_EraseRootFromParent_Done,
31203 /* 86968 */ // Label 1688: @86968
31204 /* 86968 */ GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(87061), // Rule ID 4240 //
31205 /* 86973 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
31206 /* 86978 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31207 /* 86981 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31208 /* 86984 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31209 /* 86987 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31210 /* 86990 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31211 /* 86993 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31212 /* 86996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31213 /* 87000 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31214 /* 87004 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31215 /* 87008 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31216 /* 87012 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31217 /* 87016 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31218 /* 87020 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3944:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, MQPR:{ *:[v8i16] }:$sh)
31219 /* 87020 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
31220 /* 87023 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
31221 /* 87027 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
31222 /* 87032 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu16),
31223 /* 87035 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31224 /* 87037 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31225 /* 87039 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31226 /* 87041 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31227 /* 87044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31228 /* 87050 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31229 /* 87056 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31230 /* 87059 */ GIR_RootConstrainSelectedInstOperands,
31231 /* 87060 */ // GIR_Coverage, 4240,
31232 /* 87060 */ GIR_EraseRootFromParent_Done,
31233 /* 87061 */ // Label 1689: @87061
31234 /* 87061 */ GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(87154), // Rule ID 4242 //
31235 /* 87066 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_vector),
31236 /* 87071 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31237 /* 87074 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31238 /* 87077 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
31239 /* 87080 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31240 /* 87083 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31241 /* 87086 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31242 /* 87089 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31243 /* 87093 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31244 /* 87097 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31245 /* 87101 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31246 /* 87105 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31247 /* 87109 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31248 /* 87113 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3944:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_by_vecu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, MQPR:{ *:[v4i32] }:$sh)
31249 /* 87113 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
31250 /* 87116 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
31251 /* 87120 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
31252 /* 87125 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_by_vecu32),
31253 /* 87128 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31254 /* 87130 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31255 /* 87132 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31256 /* 87134 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31257 /* 87137 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31258 /* 87143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31259 /* 87149 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
31260 /* 87152 */ GIR_RootConstrainSelectedInstOperands,
31261 /* 87153 */ // GIR_Coverage, 4242,
31262 /* 87153 */ GIR_EraseRootFromParent_Done,
31263 /* 87154 */ // Label 1690: @87154
31264 /* 87154 */ GIM_Try, /*On fail goto*//*Label 1691*/ GIMT_Encode4(87232), // Rule ID 4943 //
31265 /* 87159 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31266 /* 87164 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31267 /* 87167 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31268 /* 87170 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
31269 /* 87173 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31270 /* 87176 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31271 /* 87179 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31272 /* 87182 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31273 /* 87186 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31274 /* 87190 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31275 /* 87194 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31276 /* 87198 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31277 /* 87202 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31278 /* 87206 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
31279 /* 87206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32bh),
31280 /* 87209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31281 /* 87211 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31282 /* 87213 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31283 /* 87215 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31284 /* 87218 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31285 /* 87224 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31286 /* 87230 */ GIR_RootConstrainSelectedInstOperands,
31287 /* 87231 */ // GIR_Coverage, 4943,
31288 /* 87231 */ GIR_EraseRootFromParent_Done,
31289 /* 87232 */ // Label 1691: @87232
31290 /* 87232 */ GIM_Try, /*On fail goto*//*Label 1692*/ GIMT_Encode4(87310), // Rule ID 4945 //
31291 /* 87237 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31292 /* 87242 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31293 /* 87245 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31294 /* 87248 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
31295 /* 87251 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31296 /* 87254 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31297 /* 87257 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31298 /* 87260 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31299 /* 87264 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31300 /* 87268 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31301 /* 87272 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31302 /* 87276 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31303 /* 87280 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31304 /* 87284 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
31305 /* 87284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs32th),
31306 /* 87287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31307 /* 87289 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31308 /* 87291 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31309 /* 87293 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31310 /* 87296 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31311 /* 87302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31312 /* 87308 */ GIR_RootConstrainSelectedInstOperands,
31313 /* 87309 */ // GIR_Coverage, 4945,
31314 /* 87309 */ GIR_EraseRootFromParent_Done,
31315 /* 87310 */ // Label 1692: @87310
31316 /* 87310 */ GIM_Try, /*On fail goto*//*Label 1693*/ GIMT_Encode4(87388), // Rule ID 4947 //
31317 /* 87315 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31318 /* 87320 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31319 /* 87323 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31320 /* 87326 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31321 /* 87329 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31322 /* 87332 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31323 /* 87335 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31324 /* 87338 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31325 /* 87342 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31326 /* 87346 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31327 /* 87350 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31328 /* 87354 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31329 /* 87358 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31330 /* 87362 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
31331 /* 87362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16bh),
31332 /* 87365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31333 /* 87367 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31334 /* 87369 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31335 /* 87371 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31336 /* 87374 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31337 /* 87380 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31338 /* 87386 */ GIR_RootConstrainSelectedInstOperands,
31339 /* 87387 */ // GIR_Coverage, 4947,
31340 /* 87387 */ GIR_EraseRootFromParent_Done,
31341 /* 87388 */ // Label 1693: @87388
31342 /* 87388 */ GIM_Try, /*On fail goto*//*Label 1694*/ GIMT_Encode4(87466), // Rule ID 4949 //
31343 /* 87393 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31344 /* 87398 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31345 /* 87401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31346 /* 87404 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31347 /* 87407 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31348 /* 87410 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31349 /* 87413 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31350 /* 87416 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31351 /* 87420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31352 /* 87424 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31353 /* 87428 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31354 /* 87432 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31355 /* 87436 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31356 /* 87440 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
31357 /* 87440 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNs16th),
31358 /* 87443 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31359 /* 87445 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31360 /* 87447 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31361 /* 87449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31362 /* 87452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31363 /* 87458 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31364 /* 87464 */ GIR_RootConstrainSelectedInstOperands,
31365 /* 87465 */ // GIR_Coverage, 4949,
31366 /* 87465 */ GIR_EraseRootFromParent_Done,
31367 /* 87466 */ // Label 1694: @87466
31368 /* 87466 */ GIM_Try, /*On fail goto*//*Label 1695*/ GIMT_Encode4(87544), // Rule ID 4951 //
31369 /* 87471 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31370 /* 87476 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31371 /* 87479 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31372 /* 87482 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
31373 /* 87485 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31374 /* 87488 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31375 /* 87491 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31376 /* 87494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31377 /* 87498 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31378 /* 87502 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31379 /* 87506 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31380 /* 87510 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31381 /* 87514 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31382 /* 87518 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
31383 /* 87518 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32bh),
31384 /* 87521 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31385 /* 87523 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31386 /* 87525 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31387 /* 87527 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31388 /* 87530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31389 /* 87536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31390 /* 87542 */ GIR_RootConstrainSelectedInstOperands,
31391 /* 87543 */ // GIR_Coverage, 4951,
31392 /* 87543 */ GIR_EraseRootFromParent_Done,
31393 /* 87544 */ // Label 1695: @87544
31394 /* 87544 */ GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(87622), // Rule ID 4953 //
31395 /* 87549 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31396 /* 87554 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31397 /* 87557 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31398 /* 87560 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
31399 /* 87563 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31400 /* 87566 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31401 /* 87569 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31402 /* 87572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31403 /* 87576 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31404 /* 87580 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31405 /* 87584 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31406 /* 87588 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31407 /* 87592 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31408 /* 87596 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
31409 /* 87596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu32th),
31410 /* 87599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31411 /* 87601 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31412 /* 87603 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31413 /* 87605 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31414 /* 87608 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31415 /* 87614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31416 /* 87620 */ GIR_RootConstrainSelectedInstOperands,
31417 /* 87621 */ // GIR_Coverage, 4953,
31418 /* 87621 */ GIR_EraseRootFromParent_Done,
31419 /* 87622 */ // Label 1696: @87622
31420 /* 87622 */ GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(87700), // Rule ID 4955 //
31421 /* 87627 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31422 /* 87632 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31423 /* 87635 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31424 /* 87638 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31425 /* 87641 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31426 /* 87644 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31427 /* 87647 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31428 /* 87650 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31429 /* 87654 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31430 /* 87658 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31431 /* 87662 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31432 /* 87666 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31433 /* 87670 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31434 /* 87674 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVNu16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
31435 /* 87674 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16bh),
31436 /* 87677 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31437 /* 87679 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31438 /* 87681 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31439 /* 87683 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31440 /* 87686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31441 /* 87692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31442 /* 87698 */ GIR_RootConstrainSelectedInstOperands,
31443 /* 87699 */ // GIR_Coverage, 4955,
31444 /* 87699 */ GIR_EraseRootFromParent_Done,
31445 /* 87700 */ // Label 1697: @87700
31446 /* 87700 */ GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(87778), // Rule ID 4957 //
31447 /* 87705 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31448 /* 87710 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31449 /* 87713 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31450 /* 87716 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31451 /* 87719 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31452 /* 87722 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31453 /* 87725 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31454 /* 87728 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31455 /* 87732 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31456 /* 87736 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31457 /* 87740 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31458 /* 87744 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31459 /* 87748 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31460 /* 87752 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVNu16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
31461 /* 87752 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVNu16th),
31462 /* 87755 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31463 /* 87757 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31464 /* 87759 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31465 /* 87761 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31466 /* 87764 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31467 /* 87770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31468 /* 87776 */ GIR_RootConstrainSelectedInstOperands,
31469 /* 87777 */ // GIR_Coverage, 4957,
31470 /* 87777 */ GIR_EraseRootFromParent_Done,
31471 /* 87778 */ // Label 1698: @87778
31472 /* 87778 */ GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(87856), // Rule ID 4959 //
31473 /* 87783 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31474 /* 87788 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31475 /* 87791 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31476 /* 87794 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
31477 /* 87797 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31478 /* 87800 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31479 /* 87803 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31480 /* 87806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31481 /* 87810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31482 /* 87814 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31483 /* 87818 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31484 /* 87822 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31485 /* 87826 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31486 /* 87830 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
31487 /* 87830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32bh),
31488 /* 87833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31489 /* 87835 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31490 /* 87837 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31491 /* 87839 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31492 /* 87842 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31493 /* 87848 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31494 /* 87854 */ GIR_RootConstrainSelectedInstOperands,
31495 /* 87855 */ // GIR_Coverage, 4959,
31496 /* 87855 */ GIR_EraseRootFromParent_Done,
31497 /* 87856 */ // Label 1699: @87856
31498 /* 87856 */ GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(87934), // Rule ID 4961 //
31499 /* 87861 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31500 /* 87866 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31501 /* 87869 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31502 /* 87872 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
31503 /* 87875 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31504 /* 87878 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31505 /* 87881 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31506 /* 87884 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31507 /* 87888 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31508 /* 87892 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31509 /* 87896 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31510 /* 87900 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31511 /* 87904 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31512 /* 87908 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3909:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd_src, MQPR:{ *:[v4i32] }:$Qm)
31513 /* 87908 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs32th),
31514 /* 87911 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31515 /* 87913 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31516 /* 87915 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31517 /* 87917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31518 /* 87920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31519 /* 87926 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31520 /* 87932 */ GIR_RootConstrainSelectedInstOperands,
31521 /* 87933 */ // GIR_Coverage, 4961,
31522 /* 87933 */ GIR_EraseRootFromParent_Done,
31523 /* 87934 */ // Label 1700: @87934
31524 /* 87934 */ GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(88012), // Rule ID 4963 //
31525 /* 87939 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31526 /* 87944 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31527 /* 87947 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31528 /* 87950 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31529 /* 87953 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31530 /* 87956 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31531 /* 87959 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31532 /* 87962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31533 /* 87966 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31534 /* 87970 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31535 /* 87974 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31536 /* 87978 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31537 /* 87982 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31538 /* 87986 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQMOVUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
31539 /* 87986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16bh),
31540 /* 87989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31541 /* 87991 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31542 /* 87993 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31543 /* 87995 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31544 /* 87998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31545 /* 88004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31546 /* 88010 */ GIR_RootConstrainSelectedInstOperands,
31547 /* 88011 */ // GIR_Coverage, 4963,
31548 /* 88011 */ GIR_EraseRootFromParent_Done,
31549 /* 88012 */ // Label 1701: @88012
31550 /* 88012 */ GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(88090), // Rule ID 4965 //
31551 /* 88017 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqmovn),
31552 /* 88022 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31553 /* 88025 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31554 /* 88028 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
31555 /* 88031 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31556 /* 88034 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31557 /* 88037 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31558 /* 88040 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31559 /* 88044 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31560 /* 88048 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31561 /* 88052 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31562 /* 88056 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31563 /* 88060 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31564 /* 88064 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3909:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQMOVUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd_src, MQPR:{ *:[v8i16] }:$Qm)
31565 /* 88064 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQMOVUNs16th),
31566 /* 88067 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31567 /* 88069 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd_src
31568 /* 88071 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
31569 /* 88073 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31570 /* 88076 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31571 /* 88082 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31572 /* 88088 */ GIR_RootConstrainSelectedInstOperands,
31573 /* 88089 */ // GIR_Coverage, 4965,
31574 /* 88089 */ GIR_EraseRootFromParent_Done,
31575 /* 88090 */ // Label 1702: @88090
31576 /* 88090 */ GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(88168), // Rule ID 5167 //
31577 /* 88095 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31578 /* 88100 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31579 /* 88103 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31580 /* 88106 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31581 /* 88109 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31582 /* 88112 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31583 /* 88115 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31584 /* 88118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31585 /* 88122 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31586 /* 88126 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31587 /* 88130 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31588 /* 88134 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31589 /* 88138 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31590 /* 88142 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31591 /* 88142 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs8),
31592 /* 88145 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31593 /* 88147 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31594 /* 88149 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31595 /* 88151 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31596 /* 88154 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31597 /* 88160 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31598 /* 88166 */ GIR_RootConstrainSelectedInstOperands,
31599 /* 88167 */ // GIR_Coverage, 5167,
31600 /* 88167 */ GIR_EraseRootFromParent_Done,
31601 /* 88168 */ // Label 1703: @88168
31602 /* 88168 */ GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(88246), // Rule ID 5169 //
31603 /* 88173 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31604 /* 88178 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31605 /* 88181 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31606 /* 88184 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31607 /* 88187 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31608 /* 88190 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31609 /* 88193 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31610 /* 88196 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31611 /* 88200 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31612 /* 88204 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31613 /* 88208 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31614 /* 88212 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31615 /* 88216 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31616 /* 88220 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31617 /* 88220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs16),
31618 /* 88223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31619 /* 88225 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31620 /* 88227 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31621 /* 88229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31622 /* 88232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31623 /* 88238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31624 /* 88244 */ GIR_RootConstrainSelectedInstOperands,
31625 /* 88245 */ // GIR_Coverage, 5169,
31626 /* 88245 */ GIR_EraseRootFromParent_Done,
31627 /* 88246 */ // Label 1704: @88246
31628 /* 88246 */ GIM_Try, /*On fail goto*//*Label 1705*/ GIMT_Encode4(88324), // Rule ID 5171 //
31629 /* 88251 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31630 /* 88256 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31631 /* 88259 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31632 /* 88262 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31633 /* 88265 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31634 /* 88268 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31635 /* 88271 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31636 /* 88274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31637 /* 88278 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31638 /* 88282 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31639 /* 88286 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31640 /* 88290 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31641 /* 88294 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31642 /* 88298 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3942:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31643 /* 88298 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qrs32),
31644 /* 88301 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31645 /* 88303 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31646 /* 88305 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31647 /* 88307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31648 /* 88310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31649 /* 88316 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31650 /* 88322 */ GIR_RootConstrainSelectedInstOperands,
31651 /* 88323 */ // GIR_Coverage, 5171,
31652 /* 88323 */ GIR_EraseRootFromParent_Done,
31653 /* 88324 */ // Label 1705: @88324
31654 /* 88324 */ GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(88402), // Rule ID 5173 //
31655 /* 88329 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31656 /* 88334 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31657 /* 88337 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31658 /* 88340 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31659 /* 88343 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31660 /* 88346 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31661 /* 88349 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31662 /* 88352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31663 /* 88356 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31664 /* 88360 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31665 /* 88364 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31666 /* 88368 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31667 /* 88372 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31668 /* 88376 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31669 /* 88376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru8),
31670 /* 88379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31671 /* 88381 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31672 /* 88383 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31673 /* 88385 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31674 /* 88388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31675 /* 88394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31676 /* 88400 */ GIR_RootConstrainSelectedInstOperands,
31677 /* 88401 */ // GIR_Coverage, 5173,
31678 /* 88401 */ GIR_EraseRootFromParent_Done,
31679 /* 88402 */ // Label 1706: @88402
31680 /* 88402 */ GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(88480), // Rule ID 5175 //
31681 /* 88407 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31682 /* 88412 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31683 /* 88415 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31684 /* 88418 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31685 /* 88421 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31686 /* 88424 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31687 /* 88427 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31688 /* 88430 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31689 /* 88434 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31690 /* 88438 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31691 /* 88442 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31692 /* 88446 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31693 /* 88450 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31694 /* 88454 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31695 /* 88454 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru16),
31696 /* 88457 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31697 /* 88459 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31698 /* 88461 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31699 /* 88463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31700 /* 88466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31701 /* 88472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31702 /* 88478 */ GIR_RootConstrainSelectedInstOperands,
31703 /* 88479 */ // GIR_Coverage, 5175,
31704 /* 88479 */ GIR_EraseRootFromParent_Done,
31705 /* 88480 */ // Label 1707: @88480
31706 /* 88480 */ GIM_Try, /*On fail goto*//*Label 1708*/ GIMT_Encode4(88558), // Rule ID 5177 //
31707 /* 88485 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31708 /* 88490 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31709 /* 88493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31710 /* 88496 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31711 /* 88499 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31712 /* 88502 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31713 /* 88505 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31714 /* 88508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31715 /* 88512 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31716 /* 88516 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31717 /* 88520 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31718 /* 88524 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31719 /* 88528 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31720 /* 88532 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3942:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31721 /* 88532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHL_qru32),
31722 /* 88535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31723 /* 88537 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31724 /* 88539 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31725 /* 88541 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31726 /* 88544 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31727 /* 88550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31728 /* 88556 */ GIR_RootConstrainSelectedInstOperands,
31729 /* 88557 */ // GIR_Coverage, 5177,
31730 /* 88557 */ GIR_EraseRootFromParent_Done,
31731 /* 88558 */ // Label 1708: @88558
31732 /* 88558 */ GIM_Try, /*On fail goto*//*Label 1709*/ GIMT_Encode4(88636), // Rule ID 5179 //
31733 /* 88563 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31734 /* 88568 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31735 /* 88571 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31736 /* 88574 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31737 /* 88577 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31738 /* 88580 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31739 /* 88583 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31740 /* 88586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31741 /* 88590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31742 /* 88594 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31743 /* 88598 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31744 /* 88602 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31745 /* 88606 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31746 /* 88610 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31747 /* 88610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs8),
31748 /* 88613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31749 /* 88615 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31750 /* 88617 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31751 /* 88619 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31752 /* 88622 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31753 /* 88628 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31754 /* 88634 */ GIR_RootConstrainSelectedInstOperands,
31755 /* 88635 */ // GIR_Coverage, 5179,
31756 /* 88635 */ GIR_EraseRootFromParent_Done,
31757 /* 88636 */ // Label 1709: @88636
31758 /* 88636 */ GIM_Try, /*On fail goto*//*Label 1710*/ GIMT_Encode4(88714), // Rule ID 5181 //
31759 /* 88641 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31760 /* 88646 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31761 /* 88649 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31762 /* 88652 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31763 /* 88655 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31764 /* 88658 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31765 /* 88661 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31766 /* 88664 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31767 /* 88668 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31768 /* 88672 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31769 /* 88676 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31770 /* 88680 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31771 /* 88684 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31772 /* 88688 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31773 /* 88688 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs16),
31774 /* 88691 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31775 /* 88693 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31776 /* 88695 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31777 /* 88697 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31778 /* 88700 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31779 /* 88706 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31780 /* 88712 */ GIR_RootConstrainSelectedInstOperands,
31781 /* 88713 */ // GIR_Coverage, 5181,
31782 /* 88713 */ GIR_EraseRootFromParent_Done,
31783 /* 88714 */ // Label 1710: @88714
31784 /* 88714 */ GIM_Try, /*On fail goto*//*Label 1711*/ GIMT_Encode4(88792), // Rule ID 5183 //
31785 /* 88719 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31786 /* 88724 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31787 /* 88727 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31788 /* 88730 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31789 /* 88733 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31790 /* 88736 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31791 /* 88739 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31792 /* 88742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31793 /* 88746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31794 /* 88750 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31795 /* 88754 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31796 /* 88758 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31797 /* 88762 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31798 /* 88766 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3942:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31799 /* 88766 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qrs32),
31800 /* 88769 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31801 /* 88771 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31802 /* 88773 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31803 /* 88775 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31804 /* 88778 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31805 /* 88784 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31806 /* 88790 */ GIR_RootConstrainSelectedInstOperands,
31807 /* 88791 */ // GIR_Coverage, 5183,
31808 /* 88791 */ GIR_EraseRootFromParent_Done,
31809 /* 88792 */ // Label 1711: @88792
31810 /* 88792 */ GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(88870), // Rule ID 5185 //
31811 /* 88797 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31812 /* 88802 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31813 /* 88805 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31814 /* 88808 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31815 /* 88811 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31816 /* 88814 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31817 /* 88817 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31818 /* 88820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31819 /* 88824 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31820 /* 88828 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31821 /* 88832 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31822 /* 88836 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31823 /* 88840 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31824 /* 88844 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31825 /* 88844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru8),
31826 /* 88847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31827 /* 88849 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31828 /* 88851 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31829 /* 88853 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31830 /* 88856 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31831 /* 88862 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31832 /* 88868 */ GIR_RootConstrainSelectedInstOperands,
31833 /* 88869 */ // GIR_Coverage, 5185,
31834 /* 88869 */ GIR_EraseRootFromParent_Done,
31835 /* 88870 */ // Label 1712: @88870
31836 /* 88870 */ GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(88948), // Rule ID 5187 //
31837 /* 88875 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31838 /* 88880 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31839 /* 88883 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31840 /* 88886 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31841 /* 88889 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31842 /* 88892 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31843 /* 88895 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31844 /* 88898 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31845 /* 88902 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31846 /* 88906 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31847 /* 88910 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31848 /* 88914 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31849 /* 88918 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31850 /* 88922 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31851 /* 88922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru16),
31852 /* 88925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31853 /* 88927 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31854 /* 88929 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31855 /* 88931 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31856 /* 88934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31857 /* 88940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31858 /* 88946 */ GIR_RootConstrainSelectedInstOperands,
31859 /* 88947 */ // GIR_Coverage, 5187,
31860 /* 88947 */ GIR_EraseRootFromParent_Done,
31861 /* 88948 */ // Label 1713: @88948
31862 /* 88948 */ GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(89026), // Rule ID 5189 //
31863 /* 88953 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31864 /* 88958 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31865 /* 88961 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31866 /* 88964 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31867 /* 88967 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31868 /* 88970 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31869 /* 88973 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31870 /* 88976 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31871 /* 88980 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31872 /* 88984 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31873 /* 88988 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
31874 /* 88992 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
31875 /* 88996 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31876 /* 89000 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3942:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31877 /* 89000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHL_qru32),
31878 /* 89003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31879 /* 89005 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31880 /* 89007 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31881 /* 89009 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31882 /* 89012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31883 /* 89018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31884 /* 89024 */ GIR_RootConstrainSelectedInstOperands,
31885 /* 89025 */ // GIR_Coverage, 5189,
31886 /* 89025 */ GIR_EraseRootFromParent_Done,
31887 /* 89026 */ // Label 1714: @89026
31888 /* 89026 */ GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(89104), // Rule ID 5191 //
31889 /* 89031 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31890 /* 89036 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31891 /* 89039 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31892 /* 89042 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31893 /* 89045 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31894 /* 89048 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31895 /* 89051 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31896 /* 89054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31897 /* 89058 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31898 /* 89062 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31899 /* 89066 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31900 /* 89070 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31901 /* 89074 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31902 /* 89078 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31903 /* 89078 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs8),
31904 /* 89081 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31905 /* 89083 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31906 /* 89085 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31907 /* 89087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31908 /* 89090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31909 /* 89096 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31910 /* 89102 */ GIR_RootConstrainSelectedInstOperands,
31911 /* 89103 */ // GIR_Coverage, 5191,
31912 /* 89103 */ GIR_EraseRootFromParent_Done,
31913 /* 89104 */ // Label 1715: @89104
31914 /* 89104 */ GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(89182), // Rule ID 5193 //
31915 /* 89109 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31916 /* 89114 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31917 /* 89117 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31918 /* 89120 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31919 /* 89123 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31920 /* 89126 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31921 /* 89129 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31922 /* 89132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31923 /* 89136 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31924 /* 89140 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31925 /* 89144 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31926 /* 89148 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31927 /* 89152 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31928 /* 89156 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
31929 /* 89156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs16),
31930 /* 89159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31931 /* 89161 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31932 /* 89163 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31933 /* 89165 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31934 /* 89168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31935 /* 89174 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31936 /* 89180 */ GIR_RootConstrainSelectedInstOperands,
31937 /* 89181 */ // GIR_Coverage, 5193,
31938 /* 89181 */ GIR_EraseRootFromParent_Done,
31939 /* 89182 */ // Label 1716: @89182
31940 /* 89182 */ GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(89260), // Rule ID 5195 //
31941 /* 89187 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31942 /* 89192 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
31943 /* 89195 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
31944 /* 89198 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31945 /* 89201 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31946 /* 89204 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31947 /* 89207 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31948 /* 89210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31949 /* 89214 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31950 /* 89218 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31951 /* 89222 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31952 /* 89226 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31953 /* 89230 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
31954 /* 89234 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3942:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
31955 /* 89234 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qrs32),
31956 /* 89237 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31957 /* 89239 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31958 /* 89241 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31959 /* 89243 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31960 /* 89246 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31961 /* 89252 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31962 /* 89258 */ GIR_RootConstrainSelectedInstOperands,
31963 /* 89259 */ // GIR_Coverage, 5195,
31964 /* 89259 */ GIR_EraseRootFromParent_Done,
31965 /* 89260 */ // Label 1717: @89260
31966 /* 89260 */ GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(89338), // Rule ID 5197 //
31967 /* 89265 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31968 /* 89270 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
31969 /* 89273 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
31970 /* 89276 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31971 /* 89279 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31972 /* 89282 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31973 /* 89285 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
31974 /* 89288 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31975 /* 89292 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
31976 /* 89296 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
31977 /* 89300 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
31978 /* 89304 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
31979 /* 89308 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
31980 /* 89312 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
31981 /* 89312 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru8),
31982 /* 89315 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
31983 /* 89317 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
31984 /* 89319 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
31985 /* 89321 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
31986 /* 89324 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31987 /* 89330 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
31988 /* 89336 */ GIR_RootConstrainSelectedInstOperands,
31989 /* 89337 */ // GIR_Coverage, 5197,
31990 /* 89337 */ GIR_EraseRootFromParent_Done,
31991 /* 89338 */ // Label 1718: @89338
31992 /* 89338 */ GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(89416), // Rule ID 5199 //
31993 /* 89343 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
31994 /* 89348 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
31995 /* 89351 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
31996 /* 89354 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
31997 /* 89357 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
31998 /* 89360 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
31999 /* 89363 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
32000 /* 89366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32001 /* 89370 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32002 /* 89374 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
32003 /* 89378 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32004 /* 89382 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32005 /* 89386 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32006 /* 89390 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
32007 /* 89390 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru16),
32008 /* 89393 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32009 /* 89395 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
32010 /* 89397 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
32011 /* 89399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32012 /* 89402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32013 /* 89408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32014 /* 89414 */ GIR_RootConstrainSelectedInstOperands,
32015 /* 89415 */ // GIR_Coverage, 5199,
32016 /* 89415 */ GIR_EraseRootFromParent_Done,
32017 /* 89416 */ // Label 1719: @89416
32018 /* 89416 */ GIM_Try, /*On fail goto*//*Label 1720*/ GIMT_Encode4(89494), // Rule ID 5201 //
32019 /* 89421 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
32020 /* 89426 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
32021 /* 89429 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
32022 /* 89432 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32023 /* 89435 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32024 /* 89438 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32025 /* 89441 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
32026 /* 89444 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32027 /* 89448 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32028 /* 89452 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
32029 /* 89456 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32030 /* 89460 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32031 /* 89464 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32032 /* 89468 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3942:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
32033 /* 89468 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHL_qru32),
32034 /* 89471 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32035 /* 89473 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
32036 /* 89475 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
32037 /* 89477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32038 /* 89480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32039 /* 89486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32040 /* 89492 */ GIR_RootConstrainSelectedInstOperands,
32041 /* 89493 */ // GIR_Coverage, 5201,
32042 /* 89493 */ GIR_EraseRootFromParent_Done,
32043 /* 89494 */ // Label 1720: @89494
32044 /* 89494 */ GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(89572), // Rule ID 5203 //
32045 /* 89499 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
32046 /* 89504 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
32047 /* 89507 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
32048 /* 89510 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32049 /* 89513 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32050 /* 89516 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32051 /* 89519 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
32052 /* 89522 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32053 /* 89526 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32054 /* 89530 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
32055 /* 89534 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32056 /* 89538 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32057 /* 89542 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32058 /* 89546 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
32059 /* 89546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs8),
32060 /* 89549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32061 /* 89551 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
32062 /* 89553 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
32063 /* 89555 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32064 /* 89558 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32065 /* 89564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32066 /* 89570 */ GIR_RootConstrainSelectedInstOperands,
32067 /* 89571 */ // GIR_Coverage, 5203,
32068 /* 89571 */ GIR_EraseRootFromParent_Done,
32069 /* 89572 */ // Label 1721: @89572
32070 /* 89572 */ GIM_Try, /*On fail goto*//*Label 1722*/ GIMT_Encode4(89650), // Rule ID 5205 //
32071 /* 89577 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
32072 /* 89582 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
32073 /* 89585 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
32074 /* 89588 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32075 /* 89591 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32076 /* 89594 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32077 /* 89597 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
32078 /* 89600 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32079 /* 89604 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32080 /* 89608 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
32081 /* 89612 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32082 /* 89616 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32083 /* 89620 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32084 /* 89624 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
32085 /* 89624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs16),
32086 /* 89627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32087 /* 89629 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
32088 /* 89631 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
32089 /* 89633 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32090 /* 89636 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32091 /* 89642 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32092 /* 89648 */ GIR_RootConstrainSelectedInstOperands,
32093 /* 89649 */ // GIR_Coverage, 5205,
32094 /* 89649 */ GIR_EraseRootFromParent_Done,
32095 /* 89650 */ // Label 1722: @89650
32096 /* 89650 */ GIM_Try, /*On fail goto*//*Label 1723*/ GIMT_Encode4(89728), // Rule ID 5207 //
32097 /* 89655 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
32098 /* 89660 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
32099 /* 89663 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
32100 /* 89666 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32101 /* 89669 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32102 /* 89672 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32103 /* 89675 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
32104 /* 89678 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32105 /* 89682 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32106 /* 89686 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
32107 /* 89690 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32108 /* 89694 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32109 /* 89698 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
32110 /* 89702 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3942:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHL_qrs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
32111 /* 89702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qrs32),
32112 /* 89705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32113 /* 89707 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
32114 /* 89709 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
32115 /* 89711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32116 /* 89714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32117 /* 89720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32118 /* 89726 */ GIR_RootConstrainSelectedInstOperands,
32119 /* 89727 */ // GIR_Coverage, 5207,
32120 /* 89727 */ GIR_EraseRootFromParent_Done,
32121 /* 89728 */ // Label 1723: @89728
32122 /* 89728 */ GIM_Try, /*On fail goto*//*Label 1724*/ GIMT_Encode4(89806), // Rule ID 5209 //
32123 /* 89733 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
32124 /* 89738 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
32125 /* 89741 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
32126 /* 89744 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32127 /* 89747 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32128 /* 89750 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32129 /* 89753 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
32130 /* 89756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32131 /* 89760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32132 /* 89764 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
32133 /* 89768 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32134 /* 89772 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32135 /* 89776 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32136 /* 89780 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3942:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$in, rGPR:{ *:[i32] }:$sh)
32137 /* 89780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru8),
32138 /* 89783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32139 /* 89785 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
32140 /* 89787 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
32141 /* 89789 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32142 /* 89792 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32143 /* 89798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32144 /* 89804 */ GIR_RootConstrainSelectedInstOperands,
32145 /* 89805 */ // GIR_Coverage, 5209,
32146 /* 89805 */ GIR_EraseRootFromParent_Done,
32147 /* 89806 */ // Label 1724: @89806
32148 /* 89806 */ GIM_Try, /*On fail goto*//*Label 1725*/ GIMT_Encode4(89884), // Rule ID 5211 //
32149 /* 89811 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
32150 /* 89816 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
32151 /* 89819 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
32152 /* 89822 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32153 /* 89825 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32154 /* 89828 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32155 /* 89831 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
32156 /* 89834 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32157 /* 89838 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32158 /* 89842 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
32159 /* 89846 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32160 /* 89850 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32161 /* 89854 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32162 /* 89858 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3942:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$in, rGPR:{ *:[i32] }:$sh)
32163 /* 89858 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru16),
32164 /* 89861 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32165 /* 89863 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
32166 /* 89865 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
32167 /* 89867 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32168 /* 89870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32169 /* 89876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32170 /* 89882 */ GIR_RootConstrainSelectedInstOperands,
32171 /* 89883 */ // GIR_Coverage, 5211,
32172 /* 89883 */ GIR_EraseRootFromParent_Done,
32173 /* 89884 */ // Label 1725: @89884
32174 /* 89884 */ GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(89962), // Rule ID 5213 //
32175 /* 89889 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshl_scalar),
32176 /* 89894 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
32177 /* 89897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
32178 /* 89900 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32179 /* 89903 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32180 /* 89906 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32181 /* 89909 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
32182 /* 89912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32183 /* 89916 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32184 /* 89920 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
32185 /* 89924 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32186 /* 89928 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
32187 /* 89932 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
32188 /* 89936 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3942:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHL_qru32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$in, rGPR:{ *:[i32] }:$sh)
32189 /* 89936 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHL_qru32),
32190 /* 89939 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
32191 /* 89941 */ GIR_RootToRootCopy, /*OpIdx*/2, // in
32192 /* 89943 */ GIR_RootToRootCopy, /*OpIdx*/3, // sh
32193 /* 89945 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32194 /* 89948 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32195 /* 89954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32196 /* 89960 */ GIR_RootConstrainSelectedInstOperands,
32197 /* 89961 */ // GIR_Coverage, 5213,
32198 /* 89961 */ GIR_EraseRootFromParent_Done,
32199 /* 89962 */ // Label 1726: @89962
32200 /* 89962 */ GIM_Try, /*On fail goto*//*Label 1727*/ GIMT_Encode4(90098), // Rule ID 3040 //
32201 /* 89967 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
32202 /* 89970 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx3),
32203 /* 89975 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
32204 /* 89978 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
32205 /* 89981 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
32206 /* 89984 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
32207 /* 89987 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
32208 /* 89990 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8,
32209 /* 89993 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
32210 /* 89997 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4101:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vm) => (VTBX3Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, (IMPLICIT_DEF:{ *:[v8i8] }), dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
32211 /* 89997 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s8,
32212 /* 90000 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
32213 /* 90004 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
32214 /* 90009 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
32215 /* 90011 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
32216 /* 90014 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
32217 /* 90018 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
32218 /* 90023 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
32219 /* 90027 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
32220 /* 90030 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
32221 /* 90034 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
32222 /* 90037 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
32223 /* 90041 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
32224 /* 90044 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
32225 /* 90047 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
32226 /* 90050 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
32227 /* 90055 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
32228 /* 90060 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
32229 /* 90065 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
32230 /* 90070 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
32231 /* 90075 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX3Pseudo),
32232 /* 90078 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
32233 /* 90080 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
32234 /* 90082 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32235 /* 90085 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm
32236 /* 90087 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
32237 /* 90090 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32238 /* 90096 */ GIR_RootConstrainSelectedInstOperands,
32239 /* 90097 */ // GIR_Coverage, 3040,
32240 /* 90097 */ GIR_EraseRootFromParent_Done,
32241 /* 90098 */ // Label 1727: @90098
32242 /* 90098 */ GIM_Try, /*On fail goto*//*Label 1728*/ GIMT_Encode4(90219), // Rule ID 3041 //
32243 /* 90103 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
32244 /* 90106 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbl4),
32245 /* 90111 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
32246 /* 90114 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
32247 /* 90117 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
32248 /* 90120 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
32249 /* 90123 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
32250 /* 90126 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8,
32251 /* 90129 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
32252 /* 90133 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4098:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBL4Pseudo:{ *:[v8i8] } (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
32253 /* 90133 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
32254 /* 90136 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
32255 /* 90140 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
32256 /* 90145 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // Vn0
32257 /* 90149 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
32258 /* 90152 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn1
32259 /* 90156 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
32260 /* 90159 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn2
32261 /* 90163 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
32262 /* 90166 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn3
32263 /* 90170 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
32264 /* 90173 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
32265 /* 90178 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
32266 /* 90183 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
32267 /* 90188 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
32268 /* 90193 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
32269 /* 90198 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBL4Pseudo),
32270 /* 90201 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
32271 /* 90203 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
32272 /* 90206 */ GIR_RootToRootCopy, /*OpIdx*/6, // Vm
32273 /* 90208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
32274 /* 90211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32275 /* 90217 */ GIR_RootConstrainSelectedInstOperands,
32276 /* 90218 */ // GIR_Coverage, 3041,
32277 /* 90218 */ GIR_EraseRootFromParent_Done,
32278 /* 90219 */ // Label 1728: @90219
32279 /* 90219 */ GIM_Reject,
32280 /* 90220 */ // Label 1666: @90220
32281 /* 90220 */ GIM_Try, /*On fail goto*//*Label 1729*/ GIMT_Encode4(95113),
32282 /* 90225 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/8,
32283 /* 90228 */ GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(90316), // Rule ID 3533 //
32284 /* 90233 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32285 /* 90236 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32286 /* 90241 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32287 /* 90244 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32288 /* 90247 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32289 /* 90250 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32290 /* 90253 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32291 /* 90256 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32292 /* 90259 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32293 /* 90262 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32294 /* 90266 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32295 /* 90270 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32296 /* 90274 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32297 /* 90278 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32298 /* 90282 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32299 /* 90286 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32300 /* 90290 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32301 /* 90290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs8),
32302 /* 90293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32303 /* 90295 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32304 /* 90297 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32305 /* 90299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32306 /* 90302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32307 /* 90308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32308 /* 90314 */ GIR_RootConstrainSelectedInstOperands,
32309 /* 90315 */ // GIR_Coverage, 3533,
32310 /* 90315 */ GIR_EraseRootFromParent_Done,
32311 /* 90316 */ // Label 1730: @90316
32312 /* 90316 */ GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(90404), // Rule ID 3537 //
32313 /* 90321 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32314 /* 90324 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32315 /* 90329 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32316 /* 90332 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32317 /* 90335 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32318 /* 90338 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32319 /* 90341 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32320 /* 90344 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32321 /* 90347 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32322 /* 90350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32323 /* 90354 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32324 /* 90358 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32325 /* 90362 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32326 /* 90366 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32327 /* 90370 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32328 /* 90374 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32329 /* 90378 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32330 /* 90378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs8),
32331 /* 90381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32332 /* 90383 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32333 /* 90385 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32334 /* 90387 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32335 /* 90390 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32336 /* 90396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32337 /* 90402 */ GIR_RootConstrainSelectedInstOperands,
32338 /* 90403 */ // GIR_Coverage, 3537,
32339 /* 90403 */ GIR_EraseRootFromParent_Done,
32340 /* 90404 */ // Label 1731: @90404
32341 /* 90404 */ GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(90492), // Rule ID 3541 //
32342 /* 90409 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32343 /* 90412 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32344 /* 90417 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32345 /* 90420 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32346 /* 90423 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32347 /* 90426 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32348 /* 90429 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32349 /* 90432 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32350 /* 90435 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32351 /* 90438 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32352 /* 90442 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
32353 /* 90446 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32354 /* 90450 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32355 /* 90454 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32356 /* 90458 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32357 /* 90462 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32358 /* 90466 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVu8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32359 /* 90466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8),
32360 /* 90469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32361 /* 90471 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32362 /* 90473 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32363 /* 90475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32364 /* 90478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32365 /* 90484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32366 /* 90490 */ GIR_RootConstrainSelectedInstOperands,
32367 /* 90491 */ // GIR_Coverage, 3541,
32368 /* 90491 */ GIR_EraseRootFromParent_Done,
32369 /* 90492 */ // Label 1732: @90492
32370 /* 90492 */ GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(90580), // Rule ID 3545 //
32371 /* 90497 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32372 /* 90500 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32373 /* 90505 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32374 /* 90508 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32375 /* 90511 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32376 /* 90514 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32377 /* 90517 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32378 /* 90520 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32379 /* 90523 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32380 /* 90526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32381 /* 90530 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32382 /* 90534 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32383 /* 90538 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32384 /* 90542 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32385 /* 90546 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32386 /* 90550 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32387 /* 90554 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32388 /* 90554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs16),
32389 /* 90557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32390 /* 90559 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32391 /* 90561 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32392 /* 90563 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32393 /* 90566 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32394 /* 90572 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32395 /* 90578 */ GIR_RootConstrainSelectedInstOperands,
32396 /* 90579 */ // GIR_Coverage, 3545,
32397 /* 90579 */ GIR_EraseRootFromParent_Done,
32398 /* 90580 */ // Label 1733: @90580
32399 /* 90580 */ GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(90668), // Rule ID 3549 //
32400 /* 90585 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32401 /* 90588 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32402 /* 90593 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32403 /* 90596 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32404 /* 90599 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32405 /* 90602 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32406 /* 90605 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32407 /* 90608 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32408 /* 90611 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32409 /* 90614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32410 /* 90618 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32411 /* 90622 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32412 /* 90626 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32413 /* 90630 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32414 /* 90634 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32415 /* 90638 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32416 /* 90642 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32417 /* 90642 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs16),
32418 /* 90645 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32419 /* 90647 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32420 /* 90649 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32421 /* 90651 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32422 /* 90654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32423 /* 90660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32424 /* 90666 */ GIR_RootConstrainSelectedInstOperands,
32425 /* 90667 */ // GIR_Coverage, 3549,
32426 /* 90667 */ GIR_EraseRootFromParent_Done,
32427 /* 90668 */ // Label 1734: @90668
32428 /* 90668 */ GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(90756), // Rule ID 3553 //
32429 /* 90673 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32430 /* 90676 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32431 /* 90681 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32432 /* 90684 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32433 /* 90687 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32434 /* 90690 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32435 /* 90693 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32436 /* 90696 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32437 /* 90699 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32438 /* 90702 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32439 /* 90706 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
32440 /* 90710 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32441 /* 90714 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32442 /* 90718 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32443 /* 90722 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32444 /* 90726 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32445 /* 90730 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVu16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32446 /* 90730 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16),
32447 /* 90733 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32448 /* 90735 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32449 /* 90737 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32450 /* 90739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32451 /* 90742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32452 /* 90748 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32453 /* 90754 */ GIR_RootConstrainSelectedInstOperands,
32454 /* 90755 */ // GIR_Coverage, 3553,
32455 /* 90755 */ GIR_EraseRootFromParent_Done,
32456 /* 90756 */ // Label 1735: @90756
32457 /* 90756 */ GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(90844), // Rule ID 3557 //
32458 /* 90761 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32459 /* 90764 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32460 /* 90769 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32461 /* 90772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32462 /* 90775 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32463 /* 90778 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32464 /* 90781 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32465 /* 90784 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32466 /* 90787 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32467 /* 90790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32468 /* 90794 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32469 /* 90798 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32470 /* 90802 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32471 /* 90806 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32472 /* 90810 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32473 /* 90814 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32474 /* 90818 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32475 /* 90818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVs32),
32476 /* 90821 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32477 /* 90823 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32478 /* 90825 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32479 /* 90827 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32480 /* 90830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32481 /* 90836 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32482 /* 90842 */ GIR_RootConstrainSelectedInstOperands,
32483 /* 90843 */ // GIR_Coverage, 3557,
32484 /* 90843 */ GIR_EraseRootFromParent_Done,
32485 /* 90844 */ // Label 1736: @90844
32486 /* 90844 */ GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(90932), // Rule ID 3561 //
32487 /* 90849 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32488 /* 90852 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32489 /* 90857 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32490 /* 90860 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32491 /* 90863 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32492 /* 90866 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32493 /* 90869 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32494 /* 90872 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32495 /* 90875 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32496 /* 90878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32497 /* 90882 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32498 /* 90886 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32499 /* 90890 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32500 /* 90894 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32501 /* 90898 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32502 /* 90902 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32503 /* 90906 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32504 /* 90906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVxs32),
32505 /* 90909 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32506 /* 90911 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32507 /* 90913 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32508 /* 90915 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32509 /* 90918 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32510 /* 90924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32511 /* 90930 */ GIR_RootConstrainSelectedInstOperands,
32512 /* 90931 */ // GIR_Coverage, 3561,
32513 /* 90931 */ GIR_EraseRootFromParent_Done,
32514 /* 90932 */ // Label 1737: @90932
32515 /* 90932 */ GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(91020), // Rule ID 3565 //
32516 /* 90937 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32517 /* 90940 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32518 /* 90945 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32519 /* 90948 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32520 /* 90951 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32521 /* 90954 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32522 /* 90957 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32523 /* 90960 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32524 /* 90963 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32525 /* 90966 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32526 /* 90970 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
32527 /* 90974 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32528 /* 90978 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32529 /* 90982 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32530 /* 90986 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32531 /* 90990 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32532 /* 90994 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVu32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32533 /* 90994 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32),
32534 /* 90997 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32535 /* 90999 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32536 /* 91001 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32537 /* 91003 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32538 /* 91006 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32539 /* 91012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32540 /* 91018 */ GIR_RootConstrainSelectedInstOperands,
32541 /* 91019 */ // GIR_Coverage, 3565,
32542 /* 91019 */ GIR_EraseRootFromParent_Done,
32543 /* 91020 */ // Label 1738: @91020
32544 /* 91020 */ GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(91108), // Rule ID 3569 //
32545 /* 91025 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32546 /* 91028 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32547 /* 91033 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32548 /* 91036 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32549 /* 91039 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32550 /* 91042 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32551 /* 91045 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32552 /* 91048 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32553 /* 91051 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32554 /* 91054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32555 /* 91058 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32556 /* 91062 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32557 /* 91066 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32558 /* 91070 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32559 /* 91074 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32560 /* 91078 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32561 /* 91082 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32562 /* 91082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs8),
32563 /* 91085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32564 /* 91087 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32565 /* 91089 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32566 /* 91091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32567 /* 91094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32568 /* 91100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32569 /* 91106 */ GIR_RootConstrainSelectedInstOperands,
32570 /* 91107 */ // GIR_Coverage, 3569,
32571 /* 91107 */ GIR_EraseRootFromParent_Done,
32572 /* 91108 */ // Label 1739: @91108
32573 /* 91108 */ GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(91196), // Rule ID 3573 //
32574 /* 91113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32575 /* 91116 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32576 /* 91121 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32577 /* 91124 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32578 /* 91127 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32579 /* 91130 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32580 /* 91133 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32581 /* 91136 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32582 /* 91139 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32583 /* 91142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32584 /* 91146 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32585 /* 91150 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32586 /* 91154 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32587 /* 91158 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32588 /* 91162 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32589 /* 91166 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32590 /* 91170 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVxs8:{ *:[i32] } MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32591 /* 91170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs8),
32592 /* 91173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32593 /* 91175 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32594 /* 91177 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32595 /* 91179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32596 /* 91182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32597 /* 91188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32598 /* 91194 */ GIR_RootConstrainSelectedInstOperands,
32599 /* 91195 */ // GIR_Coverage, 3573,
32600 /* 91195 */ GIR_EraseRootFromParent_Done,
32601 /* 91196 */ // Label 1740: @91196
32602 /* 91196 */ GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(91284), // Rule ID 3577 //
32603 /* 91201 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32604 /* 91204 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32605 /* 91209 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32606 /* 91212 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32607 /* 91215 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32608 /* 91218 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32609 /* 91221 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32610 /* 91224 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32611 /* 91227 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32612 /* 91230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32613 /* 91234 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32614 /* 91238 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32615 /* 91242 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32616 /* 91246 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32617 /* 91250 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32618 /* 91254 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32619 /* 91258 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32620 /* 91258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs16),
32621 /* 91261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32622 /* 91263 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32623 /* 91265 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32624 /* 91267 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32625 /* 91270 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32626 /* 91276 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32627 /* 91282 */ GIR_RootConstrainSelectedInstOperands,
32628 /* 91283 */ // GIR_Coverage, 3577,
32629 /* 91283 */ GIR_EraseRootFromParent_Done,
32630 /* 91284 */ // Label 1741: @91284
32631 /* 91284 */ GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(91372), // Rule ID 3581 //
32632 /* 91289 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32633 /* 91292 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32634 /* 91297 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32635 /* 91300 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32636 /* 91303 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32637 /* 91306 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32638 /* 91309 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32639 /* 91312 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32640 /* 91315 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32641 /* 91318 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32642 /* 91322 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32643 /* 91326 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32644 /* 91330 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32645 /* 91334 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32646 /* 91338 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32647 /* 91342 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32648 /* 91346 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVxs16:{ *:[i32] } MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32649 /* 91346 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs16),
32650 /* 91349 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32651 /* 91351 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32652 /* 91353 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32653 /* 91355 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32654 /* 91358 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32655 /* 91364 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32656 /* 91370 */ GIR_RootConstrainSelectedInstOperands,
32657 /* 91371 */ // GIR_Coverage, 3581,
32658 /* 91371 */ GIR_EraseRootFromParent_Done,
32659 /* 91372 */ // Label 1742: @91372
32660 /* 91372 */ GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(91460), // Rule ID 3585 //
32661 /* 91377 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32662 /* 91380 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32663 /* 91385 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32664 /* 91388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32665 /* 91391 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32666 /* 91394 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32667 /* 91397 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32668 /* 91400 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32669 /* 91403 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32670 /* 91406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32671 /* 91410 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32672 /* 91414 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32673 /* 91418 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32674 /* 91422 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32675 /* 91426 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32676 /* 91430 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32677 /* 91434 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32678 /* 91434 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVs32),
32679 /* 91437 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32680 /* 91439 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32681 /* 91441 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32682 /* 91443 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32683 /* 91446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32684 /* 91452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32685 /* 91458 */ GIR_RootConstrainSelectedInstOperands,
32686 /* 91459 */ // GIR_Coverage, 3585,
32687 /* 91459 */ GIR_EraseRootFromParent_Done,
32688 /* 91460 */ // Label 1743: @91460
32689 /* 91460 */ GIM_Try, /*On fail goto*//*Label 1744*/ GIMT_Encode4(91548), // Rule ID 3589 //
32690 /* 91465 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32691 /* 91468 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32692 /* 91473 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32693 /* 91476 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32694 /* 91479 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32695 /* 91482 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32696 /* 91485 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32697 /* 91488 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32698 /* 91491 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32699 /* 91494 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32700 /* 91498 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32701 /* 91502 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
32702 /* 91506 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32703 /* 91510 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
32704 /* 91514 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32705 /* 91518 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32706 /* 91522 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVxs32:{ *:[i32] } MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32707 /* 91522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVxs32),
32708 /* 91525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32709 /* 91527 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32710 /* 91529 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32711 /* 91531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32712 /* 91534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32713 /* 91540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32714 /* 91546 */ GIR_RootConstrainSelectedInstOperands,
32715 /* 91547 */ // GIR_Coverage, 3589,
32716 /* 91547 */ GIR_EraseRootFromParent_Done,
32717 /* 91548 */ // Label 1744: @91548
32718 /* 91548 */ GIM_Try, /*On fail goto*//*Label 1745*/ GIMT_Encode4(91638), // Rule ID 3535 //
32719 /* 91553 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32720 /* 91556 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32721 /* 91561 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32722 /* 91564 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32723 /* 91567 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32724 /* 91570 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32725 /* 91573 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32726 /* 91576 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32727 /* 91579 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32728 /* 91582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32729 /* 91586 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32730 /* 91590 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32731 /* 91594 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32732 /* 91598 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32733 /* 91602 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32734 /* 91606 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32735 /* 91610 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32736 /* 91610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas8),
32737 /* 91613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32738 /* 91615 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32739 /* 91617 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32740 /* 91619 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32741 /* 91621 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32742 /* 91624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32743 /* 91630 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32744 /* 91636 */ GIR_RootConstrainSelectedInstOperands,
32745 /* 91637 */ // GIR_Coverage, 3535,
32746 /* 91637 */ GIR_EraseRootFromParent_Done,
32747 /* 91638 */ // Label 1745: @91638
32748 /* 91638 */ GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(91728), // Rule ID 3539 //
32749 /* 91643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32750 /* 91646 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32751 /* 91651 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32752 /* 91654 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32753 /* 91657 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32754 /* 91660 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32755 /* 91663 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32756 /* 91666 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32757 /* 91669 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32758 /* 91672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32759 /* 91676 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32760 /* 91680 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32761 /* 91684 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32762 /* 91688 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32763 /* 91692 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32764 /* 91696 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32765 /* 91700 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32766 /* 91700 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs8),
32767 /* 91703 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32768 /* 91705 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32769 /* 91707 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32770 /* 91709 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32771 /* 91711 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32772 /* 91714 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32773 /* 91720 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32774 /* 91726 */ GIR_RootConstrainSelectedInstOperands,
32775 /* 91727 */ // GIR_Coverage, 3539,
32776 /* 91727 */ GIR_EraseRootFromParent_Done,
32777 /* 91728 */ // Label 1746: @91728
32778 /* 91728 */ GIM_Try, /*On fail goto*//*Label 1747*/ GIMT_Encode4(91818), // Rule ID 3543 //
32779 /* 91733 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32780 /* 91736 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32781 /* 91741 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32782 /* 91744 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32783 /* 91747 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32784 /* 91750 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32785 /* 91753 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32786 /* 91756 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32787 /* 91759 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32788 /* 91762 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32789 /* 91766 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
32790 /* 91770 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32791 /* 91774 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32792 /* 91778 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32793 /* 91782 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32794 /* 91786 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32795 /* 91790 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLADAVau8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
32796 /* 91790 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau8),
32797 /* 91793 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32798 /* 91795 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32799 /* 91797 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32800 /* 91799 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32801 /* 91801 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32802 /* 91804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32803 /* 91810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32804 /* 91816 */ GIR_RootConstrainSelectedInstOperands,
32805 /* 91817 */ // GIR_Coverage, 3543,
32806 /* 91817 */ GIR_EraseRootFromParent_Done,
32807 /* 91818 */ // Label 1747: @91818
32808 /* 91818 */ GIM_Try, /*On fail goto*//*Label 1748*/ GIMT_Encode4(91908), // Rule ID 3547 //
32809 /* 91823 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32810 /* 91826 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32811 /* 91831 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32812 /* 91834 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32813 /* 91837 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32814 /* 91840 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32815 /* 91843 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32816 /* 91846 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32817 /* 91849 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32818 /* 91852 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32819 /* 91856 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32820 /* 91860 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32821 /* 91864 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32822 /* 91868 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32823 /* 91872 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32824 /* 91876 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32825 /* 91880 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32826 /* 91880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas16),
32827 /* 91883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32828 /* 91885 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32829 /* 91887 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32830 /* 91889 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32831 /* 91891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32832 /* 91894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32833 /* 91900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32834 /* 91906 */ GIR_RootConstrainSelectedInstOperands,
32835 /* 91907 */ // GIR_Coverage, 3547,
32836 /* 91907 */ GIR_EraseRootFromParent_Done,
32837 /* 91908 */ // Label 1748: @91908
32838 /* 91908 */ GIM_Try, /*On fail goto*//*Label 1749*/ GIMT_Encode4(91998), // Rule ID 3551 //
32839 /* 91913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32840 /* 91916 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32841 /* 91921 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32842 /* 91924 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32843 /* 91927 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32844 /* 91930 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32845 /* 91933 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32846 /* 91936 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32847 /* 91939 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32848 /* 91942 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32849 /* 91946 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32850 /* 91950 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32851 /* 91954 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32852 /* 91958 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32853 /* 91962 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32854 /* 91966 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32855 /* 91970 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32856 /* 91970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs16),
32857 /* 91973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32858 /* 91975 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32859 /* 91977 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32860 /* 91979 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32861 /* 91981 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32862 /* 91984 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32863 /* 91990 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32864 /* 91996 */ GIR_RootConstrainSelectedInstOperands,
32865 /* 91997 */ // GIR_Coverage, 3551,
32866 /* 91997 */ GIR_EraseRootFromParent_Done,
32867 /* 91998 */ // Label 1749: @91998
32868 /* 91998 */ GIM_Try, /*On fail goto*//*Label 1750*/ GIMT_Encode4(92088), // Rule ID 3555 //
32869 /* 92003 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32870 /* 92006 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32871 /* 92011 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32872 /* 92014 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32873 /* 92017 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32874 /* 92020 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32875 /* 92023 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32876 /* 92026 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
32877 /* 92029 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
32878 /* 92032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32879 /* 92036 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
32880 /* 92040 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32881 /* 92044 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32882 /* 92048 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32883 /* 92052 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32884 /* 92056 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32885 /* 92060 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLADAVau16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
32886 /* 92060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau16),
32887 /* 92063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32888 /* 92065 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32889 /* 92067 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32890 /* 92069 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32891 /* 92071 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32892 /* 92074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32893 /* 92080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32894 /* 92086 */ GIR_RootConstrainSelectedInstOperands,
32895 /* 92087 */ // GIR_Coverage, 3555,
32896 /* 92087 */ GIR_EraseRootFromParent_Done,
32897 /* 92088 */ // Label 1750: @92088
32898 /* 92088 */ GIM_Try, /*On fail goto*//*Label 1751*/ GIMT_Encode4(92178), // Rule ID 3559 //
32899 /* 92093 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32900 /* 92096 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32901 /* 92101 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32902 /* 92104 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32903 /* 92107 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32904 /* 92110 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32905 /* 92113 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32906 /* 92116 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32907 /* 92119 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32908 /* 92122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32909 /* 92126 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32910 /* 92130 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32911 /* 92134 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32912 /* 92138 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32913 /* 92142 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32914 /* 92146 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32915 /* 92150 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32916 /* 92150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVas32),
32917 /* 92153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32918 /* 92155 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32919 /* 92157 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32920 /* 92159 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32921 /* 92161 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32922 /* 92164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32923 /* 92170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32924 /* 92176 */ GIR_RootConstrainSelectedInstOperands,
32925 /* 92177 */ // GIR_Coverage, 3559,
32926 /* 92177 */ GIR_EraseRootFromParent_Done,
32927 /* 92178 */ // Label 1751: @92178
32928 /* 92178 */ GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(92268), // Rule ID 3563 //
32929 /* 92183 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32930 /* 92186 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32931 /* 92191 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32932 /* 92194 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32933 /* 92197 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32934 /* 92200 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32935 /* 92203 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32936 /* 92206 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32937 /* 92209 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32938 /* 92212 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32939 /* 92216 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
32940 /* 92220 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32941 /* 92224 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
32942 /* 92228 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32943 /* 92232 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32944 /* 92236 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32945 /* 92240 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32946 /* 92240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVaxs32),
32947 /* 92243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32948 /* 92245 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32949 /* 92247 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32950 /* 92249 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32951 /* 92251 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32952 /* 92254 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32953 /* 92260 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32954 /* 92266 */ GIR_RootConstrainSelectedInstOperands,
32955 /* 92267 */ // GIR_Coverage, 3563,
32956 /* 92267 */ GIR_EraseRootFromParent_Done,
32957 /* 92268 */ // Label 1752: @92268
32958 /* 92268 */ GIM_Try, /*On fail goto*//*Label 1753*/ GIMT_Encode4(92358), // Rule ID 3567 //
32959 /* 92273 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32960 /* 92276 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32961 /* 92281 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32962 /* 92284 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32963 /* 92287 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32964 /* 92290 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32965 /* 92293 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32966 /* 92296 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
32967 /* 92299 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
32968 /* 92302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32969 /* 92306 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 1,
32970 /* 92310 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0,
32971 /* 92314 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
32972 /* 92318 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32973 /* 92322 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32974 /* 92326 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
32975 /* 92330 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLADAVau32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
32976 /* 92330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVau32),
32977 /* 92333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
32978 /* 92335 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
32979 /* 92337 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
32980 /* 92339 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
32981 /* 92341 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
32982 /* 92344 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32983 /* 92350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
32984 /* 92356 */ GIR_RootConstrainSelectedInstOperands,
32985 /* 92357 */ // GIR_Coverage, 3567,
32986 /* 92357 */ GIR_EraseRootFromParent_Done,
32987 /* 92358 */ // Label 1753: @92358
32988 /* 92358 */ GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(92448), // Rule ID 3571 //
32989 /* 92363 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
32990 /* 92366 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
32991 /* 92371 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
32992 /* 92374 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
32993 /* 92377 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
32994 /* 92380 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
32995 /* 92383 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
32996 /* 92386 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
32997 /* 92389 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
32998 /* 92392 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
32999 /* 92396 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
33000 /* 92400 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
33001 /* 92404 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
33002 /* 92408 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
33003 /* 92412 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33004 /* 92416 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33005 /* 92420 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVas8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
33006 /* 92420 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas8),
33007 /* 92423 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
33008 /* 92425 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
33009 /* 92427 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
33010 /* 92429 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
33011 /* 92431 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33012 /* 92434 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33013 /* 92440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33014 /* 92446 */ GIR_RootConstrainSelectedInstOperands,
33015 /* 92447 */ // GIR_Coverage, 3571,
33016 /* 92447 */ GIR_EraseRootFromParent_Done,
33017 /* 92448 */ // Label 1754: @92448
33018 /* 92448 */ GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(92538), // Rule ID 3575 //
33019 /* 92453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
33020 /* 92456 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
33021 /* 92461 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33022 /* 92464 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33023 /* 92467 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33024 /* 92470 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33025 /* 92473 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33026 /* 92476 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v16s8,
33027 /* 92479 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v16s8,
33028 /* 92482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
33029 /* 92486 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
33030 /* 92490 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
33031 /* 92494 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
33032 /* 92498 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
33033 /* 92502 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33034 /* 92506 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33035 /* 92510 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm) => (MVE_VMLSDAVaxs8:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v16i8] }:$Qn, MQPR:{ *:[v16i8] }:$Qm)
33036 /* 92510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs8),
33037 /* 92513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
33038 /* 92515 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
33039 /* 92517 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
33040 /* 92519 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
33041 /* 92521 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33042 /* 92524 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33043 /* 92530 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33044 /* 92536 */ GIR_RootConstrainSelectedInstOperands,
33045 /* 92537 */ // GIR_Coverage, 3575,
33046 /* 92537 */ GIR_EraseRootFromParent_Done,
33047 /* 92538 */ // Label 1755: @92538
33048 /* 92538 */ GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(92628), // Rule ID 3579 //
33049 /* 92543 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
33050 /* 92546 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
33051 /* 92551 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33052 /* 92554 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33053 /* 92557 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33054 /* 92560 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33055 /* 92563 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33056 /* 92566 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
33057 /* 92569 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
33058 /* 92572 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
33059 /* 92576 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
33060 /* 92580 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
33061 /* 92584 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
33062 /* 92588 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
33063 /* 92592 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33064 /* 92596 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33065 /* 92600 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVas16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
33066 /* 92600 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas16),
33067 /* 92603 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
33068 /* 92605 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
33069 /* 92607 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
33070 /* 92609 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
33071 /* 92611 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33072 /* 92614 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33073 /* 92620 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33074 /* 92626 */ GIR_RootConstrainSelectedInstOperands,
33075 /* 92627 */ // GIR_Coverage, 3579,
33076 /* 92627 */ GIR_EraseRootFromParent_Done,
33077 /* 92628 */ // Label 1756: @92628
33078 /* 92628 */ GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(92718), // Rule ID 3583 //
33079 /* 92633 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
33080 /* 92636 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
33081 /* 92641 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33082 /* 92644 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33083 /* 92647 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33084 /* 92650 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33085 /* 92653 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33086 /* 92656 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s16,
33087 /* 92659 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s16,
33088 /* 92662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
33089 /* 92666 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
33090 /* 92670 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
33091 /* 92674 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
33092 /* 92678 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
33093 /* 92682 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33094 /* 92686 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33095 /* 92690 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm) => (MVE_VMLSDAVaxs16:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v8i16] }:$Qn, MQPR:{ *:[v8i16] }:$Qm)
33096 /* 92690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs16),
33097 /* 92693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
33098 /* 92695 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
33099 /* 92697 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
33100 /* 92699 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
33101 /* 92701 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33102 /* 92704 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33103 /* 92710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33104 /* 92716 */ GIR_RootConstrainSelectedInstOperands,
33105 /* 92717 */ // GIR_Coverage, 3583,
33106 /* 92717 */ GIR_EraseRootFromParent_Done,
33107 /* 92718 */ // Label 1757: @92718
33108 /* 92718 */ GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(92808), // Rule ID 3587 //
33109 /* 92723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
33110 /* 92726 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
33111 /* 92731 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33112 /* 92734 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33113 /* 92737 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33114 /* 92740 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33115 /* 92743 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33116 /* 92746 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
33117 /* 92749 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
33118 /* 92752 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
33119 /* 92756 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
33120 /* 92760 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
33121 /* 92764 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0,
33122 /* 92768 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
33123 /* 92772 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33124 /* 92776 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33125 /* 92780 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVas32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
33126 /* 92780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVas32),
33127 /* 92783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
33128 /* 92785 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
33129 /* 92787 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
33130 /* 92789 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
33131 /* 92791 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33132 /* 92794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33133 /* 92800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33134 /* 92806 */ GIR_RootConstrainSelectedInstOperands,
33135 /* 92807 */ // GIR_Coverage, 3587,
33136 /* 92807 */ GIR_EraseRootFromParent_Done,
33137 /* 92808 */ // Label 1758: @92808
33138 /* 92808 */ GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(92898), // Rule ID 3591 //
33139 /* 92813 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
33140 /* 92816 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vmldava),
33141 /* 92821 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
33142 /* 92824 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
33143 /* 92827 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
33144 /* 92830 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33145 /* 92833 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33146 /* 92836 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32,
33147 /* 92839 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v4s32,
33148 /* 92842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
33149 /* 92846 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0,
33150 /* 92850 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 1,
33151 /* 92854 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 1,
33152 /* 92858 */ GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
33153 /* 92862 */ GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33154 /* 92866 */ GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33155 /* 92870 */ // (intrinsic_wo_chain:{ *:[i32] } 3890:{ *:[iPTR] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm) => (MVE_VMLSDAVaxs32:{ *:[i32] } tGPREven:{ *:[i32] }:$RdaSrc, MQPR:{ *:[v4i32] }:$Qn, MQPR:{ *:[v4i32] }:$Qm)
33156 /* 92870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLSDAVaxs32),
33157 /* 92873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
33158 /* 92875 */ GIR_RootToRootCopy, /*OpIdx*/5, // RdaSrc
33159 /* 92877 */ GIR_RootToRootCopy, /*OpIdx*/6, // Qn
33160 /* 92879 */ GIR_RootToRootCopy, /*OpIdx*/7, // Qm
33161 /* 92881 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33162 /* 92884 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33163 /* 92890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33164 /* 92896 */ GIR_RootConstrainSelectedInstOperands,
33165 /* 92897 */ // GIR_Coverage, 3591,
33166 /* 92897 */ GIR_EraseRootFromParent_Done,
33167 /* 92898 */ // Label 1759: @92898
33168 /* 92898 */ GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(92985), // Rule ID 4789 //
33169 /* 92903 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33170 /* 92908 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33171 /* 92911 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33172 /* 92914 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33173 /* 92917 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
33174 /* 92920 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33175 /* 92923 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33176 /* 92926 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33177 /* 92929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33178 /* 92933 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33179 /* 92937 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33180 /* 92941 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33181 /* 92945 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33182 /* 92949 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33183 /* 92953 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33184 /* 92957 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3900:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33185 /* 92957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs8),
33186 /* 92960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33187 /* 92962 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33188 /* 92964 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33189 /* 92966 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33190 /* 92968 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33191 /* 92971 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33192 /* 92977 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33193 /* 92983 */ GIR_RootConstrainSelectedInstOperands,
33194 /* 92984 */ // GIR_Coverage, 4789,
33195 /* 92984 */ GIR_EraseRootFromParent_Done,
33196 /* 92985 */ // Label 1760: @92985
33197 /* 92985 */ GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(93072), // Rule ID 4791 //
33198 /* 92990 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33199 /* 92995 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33200 /* 92998 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33201 /* 93001 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33202 /* 93004 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
33203 /* 93007 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33204 /* 93010 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33205 /* 93013 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33206 /* 93016 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33207 /* 93020 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33208 /* 93024 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33209 /* 93028 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33210 /* 93032 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33211 /* 93036 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33212 /* 93040 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33213 /* 93044 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3900:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33214 /* 93044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs16),
33215 /* 93047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33216 /* 93049 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33217 /* 93051 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33218 /* 93053 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33219 /* 93055 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33220 /* 93058 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33221 /* 93064 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33222 /* 93070 */ GIR_RootConstrainSelectedInstOperands,
33223 /* 93071 */ // GIR_Coverage, 4791,
33224 /* 93071 */ GIR_EraseRootFromParent_Done,
33225 /* 93072 */ // Label 1761: @93072
33226 /* 93072 */ GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(93159), // Rule ID 4793 //
33227 /* 93077 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33228 /* 93082 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
33229 /* 93085 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33230 /* 93088 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33231 /* 93091 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33232 /* 93094 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33233 /* 93097 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33234 /* 93100 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33235 /* 93103 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33236 /* 93107 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33237 /* 93111 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33238 /* 93115 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33239 /* 93119 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33240 /* 93123 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33241 /* 93127 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33242 /* 93131 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3900:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33243 /* 93131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHs32),
33244 /* 93134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33245 /* 93136 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33246 /* 93138 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33247 /* 93140 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33248 /* 93142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33249 /* 93145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33250 /* 93151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33251 /* 93157 */ GIR_RootConstrainSelectedInstOperands,
33252 /* 93158 */ // GIR_Coverage, 4793,
33253 /* 93158 */ GIR_EraseRootFromParent_Done,
33254 /* 93159 */ // Label 1762: @93159
33255 /* 93159 */ GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(93246), // Rule ID 4795 //
33256 /* 93164 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33257 /* 93169 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33258 /* 93172 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33259 /* 93175 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33260 /* 93178 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
33261 /* 93181 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33262 /* 93184 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33263 /* 93187 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33264 /* 93190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33265 /* 93194 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33266 /* 93198 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33267 /* 93202 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33268 /* 93206 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33269 /* 93210 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33270 /* 93214 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33271 /* 93218 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3900:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33272 /* 93218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs8),
33273 /* 93221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33274 /* 93223 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33275 /* 93225 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33276 /* 93227 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33277 /* 93229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33278 /* 93232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33279 /* 93238 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33280 /* 93244 */ GIR_RootConstrainSelectedInstOperands,
33281 /* 93245 */ // GIR_Coverage, 4795,
33282 /* 93245 */ GIR_EraseRootFromParent_Done,
33283 /* 93246 */ // Label 1763: @93246
33284 /* 93246 */ GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(93333), // Rule ID 4797 //
33285 /* 93251 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33286 /* 93256 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33287 /* 93259 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33288 /* 93262 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33289 /* 93265 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
33290 /* 93268 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33291 /* 93271 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33292 /* 93274 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33293 /* 93277 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33294 /* 93281 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33295 /* 93285 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33296 /* 93289 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33297 /* 93293 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33298 /* 93297 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33299 /* 93301 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33300 /* 93305 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3900:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33301 /* 93305 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs16),
33302 /* 93308 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33303 /* 93310 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33304 /* 93312 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33305 /* 93314 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33306 /* 93316 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33307 /* 93319 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33308 /* 93325 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33309 /* 93331 */ GIR_RootConstrainSelectedInstOperands,
33310 /* 93332 */ // GIR_Coverage, 4797,
33311 /* 93332 */ GIR_EraseRootFromParent_Done,
33312 /* 93333 */ // Label 1764: @93333
33313 /* 93333 */ GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(93420), // Rule ID 4799 //
33314 /* 93338 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33315 /* 93343 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
33316 /* 93346 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33317 /* 93349 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33318 /* 93352 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33319 /* 93355 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33320 /* 93358 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33321 /* 93361 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33322 /* 93364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33323 /* 93368 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33324 /* 93372 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33325 /* 93376 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33326 /* 93380 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33327 /* 93384 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33328 /* 93388 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33329 /* 93392 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3900:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33330 /* 93392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLADHXs32),
33331 /* 93395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33332 /* 93397 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33333 /* 93399 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33334 /* 93401 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33335 /* 93403 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33336 /* 93406 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33337 /* 93412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33338 /* 93418 */ GIR_RootConstrainSelectedInstOperands,
33339 /* 93419 */ // GIR_Coverage, 4799,
33340 /* 93419 */ GIR_EraseRootFromParent_Done,
33341 /* 93420 */ // Label 1765: @93420
33342 /* 93420 */ GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(93507), // Rule ID 4801 //
33343 /* 93425 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33344 /* 93430 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33345 /* 93433 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33346 /* 93436 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33347 /* 93439 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
33348 /* 93442 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33349 /* 93445 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33350 /* 93448 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33351 /* 93451 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33352 /* 93455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33353 /* 93459 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33354 /* 93463 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33355 /* 93467 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33356 /* 93471 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33357 /* 93475 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33358 /* 93479 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3900:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33359 /* 93479 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs8),
33360 /* 93482 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33361 /* 93484 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33362 /* 93486 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33363 /* 93488 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33364 /* 93490 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33365 /* 93493 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33366 /* 93499 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33367 /* 93505 */ GIR_RootConstrainSelectedInstOperands,
33368 /* 93506 */ // GIR_Coverage, 4801,
33369 /* 93506 */ GIR_EraseRootFromParent_Done,
33370 /* 93507 */ // Label 1766: @93507
33371 /* 93507 */ GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(93594), // Rule ID 4803 //
33372 /* 93512 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33373 /* 93517 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33374 /* 93520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33375 /* 93523 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33376 /* 93526 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
33377 /* 93529 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33378 /* 93532 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33379 /* 93535 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33380 /* 93538 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33381 /* 93542 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33382 /* 93546 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33383 /* 93550 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33384 /* 93554 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33385 /* 93558 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33386 /* 93562 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33387 /* 93566 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3900:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33388 /* 93566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs16),
33389 /* 93569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33390 /* 93571 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33391 /* 93573 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33392 /* 93575 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33393 /* 93577 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33394 /* 93580 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33395 /* 93586 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33396 /* 93592 */ GIR_RootConstrainSelectedInstOperands,
33397 /* 93593 */ // GIR_Coverage, 4803,
33398 /* 93593 */ GIR_EraseRootFromParent_Done,
33399 /* 93594 */ // Label 1767: @93594
33400 /* 93594 */ GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(93681), // Rule ID 4805 //
33401 /* 93599 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33402 /* 93604 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
33403 /* 93607 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33404 /* 93610 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33405 /* 93613 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33406 /* 93616 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33407 /* 93619 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33408 /* 93622 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33409 /* 93625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33410 /* 93629 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33411 /* 93633 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33412 /* 93637 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33413 /* 93641 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33414 /* 93645 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33415 /* 93649 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33416 /* 93653 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3900:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33417 /* 93653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHs32),
33418 /* 93656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33419 /* 93658 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33420 /* 93660 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33421 /* 93662 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33422 /* 93664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33423 /* 93667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33424 /* 93673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33425 /* 93679 */ GIR_RootConstrainSelectedInstOperands,
33426 /* 93680 */ // GIR_Coverage, 4805,
33427 /* 93680 */ GIR_EraseRootFromParent_Done,
33428 /* 93681 */ // Label 1768: @93681
33429 /* 93681 */ GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(93768), // Rule ID 4807 //
33430 /* 93686 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33431 /* 93691 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33432 /* 93694 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33433 /* 93697 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33434 /* 93700 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
33435 /* 93703 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33436 /* 93706 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33437 /* 93709 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33438 /* 93712 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33439 /* 93716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33440 /* 93720 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33441 /* 93724 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33442 /* 93728 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33443 /* 93732 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33444 /* 93736 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33445 /* 93740 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3900:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33446 /* 93740 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs8),
33447 /* 93743 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33448 /* 93745 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33449 /* 93747 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33450 /* 93749 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33451 /* 93751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33452 /* 93754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33453 /* 93760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33454 /* 93766 */ GIR_RootConstrainSelectedInstOperands,
33455 /* 93767 */ // GIR_Coverage, 4807,
33456 /* 93767 */ GIR_EraseRootFromParent_Done,
33457 /* 93768 */ // Label 1769: @93768
33458 /* 93768 */ GIM_Try, /*On fail goto*//*Label 1770*/ GIMT_Encode4(93855), // Rule ID 4809 //
33459 /* 93773 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33460 /* 93778 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33461 /* 93781 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33462 /* 93784 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33463 /* 93787 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
33464 /* 93790 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33465 /* 93793 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33466 /* 93796 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33467 /* 93799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33468 /* 93803 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33469 /* 93807 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33470 /* 93811 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33471 /* 93815 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33472 /* 93819 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33473 /* 93823 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33474 /* 93827 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3900:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33475 /* 93827 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs16),
33476 /* 93830 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33477 /* 93832 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33478 /* 93834 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33479 /* 93836 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33480 /* 93838 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33481 /* 93841 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33482 /* 93847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33483 /* 93853 */ GIR_RootConstrainSelectedInstOperands,
33484 /* 93854 */ // GIR_Coverage, 4809,
33485 /* 93854 */ GIR_EraseRootFromParent_Done,
33486 /* 93855 */ // Label 1770: @93855
33487 /* 93855 */ GIM_Try, /*On fail goto*//*Label 1771*/ GIMT_Encode4(93942), // Rule ID 4811 //
33488 /* 93860 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33489 /* 93865 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
33490 /* 93868 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33491 /* 93871 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33492 /* 93874 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33493 /* 93877 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33494 /* 93880 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33495 /* 93883 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33496 /* 93886 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33497 /* 93890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33498 /* 93894 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33499 /* 93898 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33500 /* 93902 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33501 /* 93906 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33502 /* 93910 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33503 /* 93914 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3900:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRDMLADHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33504 /* 93914 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLADHXs32),
33505 /* 93917 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33506 /* 93919 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33507 /* 93921 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33508 /* 93923 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33509 /* 93925 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33510 /* 93928 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33511 /* 93934 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33512 /* 93940 */ GIR_RootConstrainSelectedInstOperands,
33513 /* 93941 */ // GIR_Coverage, 4811,
33514 /* 93941 */ GIR_EraseRootFromParent_Done,
33515 /* 93942 */ // Label 1771: @93942
33516 /* 93942 */ GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(94029), // Rule ID 4813 //
33517 /* 93947 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33518 /* 93952 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33519 /* 93955 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33520 /* 93958 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33521 /* 93961 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
33522 /* 93964 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33523 /* 93967 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33524 /* 93970 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33525 /* 93973 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33526 /* 93977 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33527 /* 93981 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33528 /* 93985 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33529 /* 93989 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33530 /* 93993 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33531 /* 93997 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33532 /* 94001 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3900:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33533 /* 94001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs8),
33534 /* 94004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33535 /* 94006 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33536 /* 94008 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33537 /* 94010 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33538 /* 94012 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33539 /* 94015 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33540 /* 94021 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33541 /* 94027 */ GIR_RootConstrainSelectedInstOperands,
33542 /* 94028 */ // GIR_Coverage, 4813,
33543 /* 94028 */ GIR_EraseRootFromParent_Done,
33544 /* 94029 */ // Label 1772: @94029
33545 /* 94029 */ GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(94116), // Rule ID 4815 //
33546 /* 94034 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33547 /* 94039 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33548 /* 94042 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33549 /* 94045 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33550 /* 94048 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
33551 /* 94051 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33552 /* 94054 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33553 /* 94057 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33554 /* 94060 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33555 /* 94064 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33556 /* 94068 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33557 /* 94072 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33558 /* 94076 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33559 /* 94080 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33560 /* 94084 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33561 /* 94088 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3900:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33562 /* 94088 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs16),
33563 /* 94091 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33564 /* 94093 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33565 /* 94095 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33566 /* 94097 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33567 /* 94099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33568 /* 94102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33569 /* 94108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33570 /* 94114 */ GIR_RootConstrainSelectedInstOperands,
33571 /* 94115 */ // GIR_Coverage, 4815,
33572 /* 94115 */ GIR_EraseRootFromParent_Done,
33573 /* 94116 */ // Label 1773: @94116
33574 /* 94116 */ GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(94203), // Rule ID 4817 //
33575 /* 94121 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33576 /* 94126 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
33577 /* 94129 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33578 /* 94132 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33579 /* 94135 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33580 /* 94138 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33581 /* 94141 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33582 /* 94144 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33583 /* 94147 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33584 /* 94151 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33585 /* 94155 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33586 /* 94159 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33587 /* 94163 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33588 /* 94167 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33589 /* 94171 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33590 /* 94175 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3900:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33591 /* 94175 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHs32),
33592 /* 94178 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33593 /* 94180 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33594 /* 94182 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33595 /* 94184 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33596 /* 94186 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33597 /* 94189 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33598 /* 94195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33599 /* 94201 */ GIR_RootConstrainSelectedInstOperands,
33600 /* 94202 */ // GIR_Coverage, 4817,
33601 /* 94202 */ GIR_EraseRootFromParent_Done,
33602 /* 94203 */ // Label 1774: @94203
33603 /* 94203 */ GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(94290), // Rule ID 4819 //
33604 /* 94208 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33605 /* 94213 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33606 /* 94216 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33607 /* 94219 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33608 /* 94222 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
33609 /* 94225 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33610 /* 94228 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33611 /* 94231 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33612 /* 94234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33613 /* 94238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33614 /* 94242 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33615 /* 94246 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33616 /* 94250 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33617 /* 94254 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33618 /* 94258 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33619 /* 94262 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3900:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33620 /* 94262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs8),
33621 /* 94265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33622 /* 94267 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33623 /* 94269 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33624 /* 94271 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33625 /* 94273 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33626 /* 94276 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33627 /* 94282 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33628 /* 94288 */ GIR_RootConstrainSelectedInstOperands,
33629 /* 94289 */ // GIR_Coverage, 4819,
33630 /* 94289 */ GIR_EraseRootFromParent_Done,
33631 /* 94290 */ // Label 1775: @94290
33632 /* 94290 */ GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(94377), // Rule ID 4821 //
33633 /* 94295 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33634 /* 94300 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33635 /* 94303 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33636 /* 94306 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33637 /* 94309 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
33638 /* 94312 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33639 /* 94315 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33640 /* 94318 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33641 /* 94321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33642 /* 94325 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33643 /* 94329 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33644 /* 94333 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33645 /* 94337 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33646 /* 94341 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33647 /* 94345 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33648 /* 94349 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3900:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33649 /* 94349 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs16),
33650 /* 94352 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33651 /* 94354 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33652 /* 94356 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33653 /* 94358 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33654 /* 94360 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33655 /* 94363 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33656 /* 94369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33657 /* 94375 */ GIR_RootConstrainSelectedInstOperands,
33658 /* 94376 */ // GIR_Coverage, 4821,
33659 /* 94376 */ GIR_EraseRootFromParent_Done,
33660 /* 94377 */ // Label 1776: @94377
33661 /* 94377 */ GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(94464), // Rule ID 4823 //
33662 /* 94382 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33663 /* 94387 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
33664 /* 94390 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33665 /* 94393 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33666 /* 94396 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33667 /* 94399 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33668 /* 94402 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33669 /* 94405 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33670 /* 94408 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33671 /* 94412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33672 /* 94416 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33673 /* 94420 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33674 /* 94424 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33675 /* 94428 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33676 /* 94432 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33677 /* 94436 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3900:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33678 /* 94436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQDMLSDHXs32),
33679 /* 94439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33680 /* 94441 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33681 /* 94443 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33682 /* 94445 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33683 /* 94447 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33684 /* 94450 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33685 /* 94456 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33686 /* 94462 */ GIR_RootConstrainSelectedInstOperands,
33687 /* 94463 */ // GIR_Coverage, 4823,
33688 /* 94463 */ GIR_EraseRootFromParent_Done,
33689 /* 94464 */ // Label 1777: @94464
33690 /* 94464 */ GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(94551), // Rule ID 4825 //
33691 /* 94469 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33692 /* 94474 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33693 /* 94477 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33694 /* 94480 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33695 /* 94483 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
33696 /* 94486 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33697 /* 94489 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33698 /* 94492 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33699 /* 94495 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33700 /* 94499 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33701 /* 94503 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33702 /* 94507 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33703 /* 94511 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33704 /* 94515 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33705 /* 94519 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33706 /* 94523 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3900:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33707 /* 94523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs8),
33708 /* 94526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33709 /* 94528 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33710 /* 94530 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33711 /* 94532 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33712 /* 94534 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33713 /* 94537 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33714 /* 94543 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33715 /* 94549 */ GIR_RootConstrainSelectedInstOperands,
33716 /* 94550 */ // GIR_Coverage, 4825,
33717 /* 94550 */ GIR_EraseRootFromParent_Done,
33718 /* 94551 */ // Label 1778: @94551
33719 /* 94551 */ GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(94638), // Rule ID 4827 //
33720 /* 94556 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33721 /* 94561 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33722 /* 94564 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33723 /* 94567 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33724 /* 94570 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
33725 /* 94573 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33726 /* 94576 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33727 /* 94579 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33728 /* 94582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33729 /* 94586 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33730 /* 94590 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33731 /* 94594 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33732 /* 94598 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33733 /* 94602 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33734 /* 94606 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33735 /* 94610 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3900:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33736 /* 94610 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs16),
33737 /* 94613 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33738 /* 94615 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33739 /* 94617 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33740 /* 94619 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33741 /* 94621 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33742 /* 94624 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33743 /* 94630 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33744 /* 94636 */ GIR_RootConstrainSelectedInstOperands,
33745 /* 94637 */ // GIR_Coverage, 4827,
33746 /* 94637 */ GIR_EraseRootFromParent_Done,
33747 /* 94638 */ // Label 1779: @94638
33748 /* 94638 */ GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(94725), // Rule ID 4829 //
33749 /* 94643 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33750 /* 94648 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
33751 /* 94651 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33752 /* 94654 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33753 /* 94657 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33754 /* 94660 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33755 /* 94663 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33756 /* 94666 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33757 /* 94669 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33758 /* 94673 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33759 /* 94677 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33760 /* 94681 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33761 /* 94685 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33762 /* 94689 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33763 /* 94693 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33764 /* 94697 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3900:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33765 /* 94697 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHs32),
33766 /* 94700 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33767 /* 94702 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33768 /* 94704 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33769 /* 94706 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33770 /* 94708 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33771 /* 94711 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33772 /* 94717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33773 /* 94723 */ GIR_RootConstrainSelectedInstOperands,
33774 /* 94724 */ // GIR_Coverage, 4829,
33775 /* 94724 */ GIR_EraseRootFromParent_Done,
33776 /* 94725 */ // Label 1780: @94725
33777 /* 94725 */ GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(94812), // Rule ID 4831 //
33778 /* 94730 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33779 /* 94735 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33780 /* 94738 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33781 /* 94741 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
33782 /* 94744 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s8,
33783 /* 94747 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33784 /* 94750 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33785 /* 94753 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33786 /* 94756 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33787 /* 94760 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33788 /* 94764 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33789 /* 94768 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33790 /* 94772 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33791 /* 94776 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33792 /* 94780 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33793 /* 94784 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3900:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$a, MQPR:{ *:[v16i8] }:$b, MQPR:{ *:[v16i8] }:$c)
33794 /* 94784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs8),
33795 /* 94787 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33796 /* 94789 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33797 /* 94791 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33798 /* 94793 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33799 /* 94795 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33800 /* 94798 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33801 /* 94804 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33802 /* 94810 */ GIR_RootConstrainSelectedInstOperands,
33803 /* 94811 */ // GIR_Coverage, 4831,
33804 /* 94811 */ GIR_EraseRootFromParent_Done,
33805 /* 94812 */ // Label 1781: @94812
33806 /* 94812 */ GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(94899), // Rule ID 4833 //
33807 /* 94817 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33808 /* 94822 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33809 /* 94825 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33810 /* 94828 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33811 /* 94831 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16,
33812 /* 94834 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33813 /* 94837 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33814 /* 94840 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33815 /* 94843 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33816 /* 94847 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33817 /* 94851 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33818 /* 94855 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33819 /* 94859 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33820 /* 94863 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33821 /* 94867 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33822 /* 94871 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3900:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$a, MQPR:{ *:[v8i16] }:$b, MQPR:{ *:[v8i16] }:$c)
33823 /* 94871 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs16),
33824 /* 94874 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33825 /* 94876 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33826 /* 94878 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33827 /* 94880 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33828 /* 94882 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33829 /* 94885 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33830 /* 94891 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33831 /* 94897 */ GIR_RootConstrainSelectedInstOperands,
33832 /* 94898 */ // GIR_Coverage, 4833,
33833 /* 94898 */ GIR_EraseRootFromParent_Done,
33834 /* 94899 */ // Label 1782: @94899
33835 /* 94899 */ GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(94986), // Rule ID 4835 //
33836 /* 94904 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vqdmlad),
33837 /* 94909 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
33838 /* 94912 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
33839 /* 94915 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33840 /* 94918 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
33841 /* 94921 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33842 /* 94924 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33843 /* 94927 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33844 /* 94930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33845 /* 94934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33846 /* 94938 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33847 /* 94942 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33848 /* 94946 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
33849 /* 94950 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
33850 /* 94954 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
33851 /* 94958 */ // (intrinsic_wo_chain:{ *:[v4i32] } 3900:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRDMLSDHXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$a, MQPR:{ *:[v4i32] }:$b, MQPR:{ *:[v4i32] }:$c)
33852 /* 94958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRDMLSDHXs32),
33853 /* 94961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33854 /* 94963 */ GIR_RootToRootCopy, /*OpIdx*/2, // a
33855 /* 94965 */ GIR_RootToRootCopy, /*OpIdx*/3, // b
33856 /* 94967 */ GIR_RootToRootCopy, /*OpIdx*/4, // c
33857 /* 94969 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33858 /* 94972 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33859 /* 94978 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33860 /* 94984 */ GIR_RootConstrainSelectedInstOperands,
33861 /* 94985 */ // GIR_Coverage, 4835,
33862 /* 94985 */ GIR_EraseRootFromParent_Done,
33863 /* 94986 */ // Label 1783: @94986
33864 /* 94986 */ GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(95112), // Rule ID 3042 //
33865 /* 94991 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
33866 /* 94994 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vtbx4),
33867 /* 94999 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s8,
33868 /* 95002 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
33869 /* 95005 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s8,
33870 /* 95008 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s8,
33871 /* 95011 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v8s8,
33872 /* 95014 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s8,
33873 /* 95017 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_v8s8,
33874 /* 95020 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
33875 /* 95024 */ // (intrinsic_wo_chain:{ *:[v8i8] } 4102:{ *:[iPTR] }, v8i8:{ *:[v8i8] }:$orig, v8i8:{ *:[v8i8] }:$Vn0, v8i8:{ *:[v8i8] }:$Vn1, v8i8:{ *:[v8i8] }:$Vn2, v8i8:{ *:[v8i8] }:$Vn3, v8i8:{ *:[v8i8] }:$Vm) => (VTBX4Pseudo:{ *:[v8i8] } v8i8:{ *:[v8i8] }:$orig, (REG_SEQUENCE:{ *:[v4i64] } QQPR:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn0, dsub_0:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn1, dsub_1:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn2, dsub_2:{ *:[i32] }, v8i8:{ *:[v8i8] }:$Vn3, dsub_3:{ *:[i32] }), v8i8:{ *:[v8i8] }:$Vm)
33876 /* 95024 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s64,
33877 /* 95027 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE),
33878 /* 95031 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
33879 /* 95036 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // Vn0
33880 /* 95040 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/1,
33881 /* 95043 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // Vn1
33882 /* 95047 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/2,
33883 /* 95050 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // Vn2
33884 /* 95054 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3,
33885 /* 95057 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // Vn3
33886 /* 95061 */ GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4,
33887 /* 95064 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::QQPRRegClassID),
33888 /* 95069 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(ARM::DPRRegClassID),
33889 /* 95074 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(ARM::DPRRegClassID),
33890 /* 95079 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/5, GIMT_Encode2(ARM::DPRRegClassID),
33891 /* 95084 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/7, GIMT_Encode2(ARM::DPRRegClassID),
33892 /* 95089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VTBX4Pseudo),
33893 /* 95092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
33894 /* 95094 */ GIR_RootToRootCopy, /*OpIdx*/2, // orig
33895 /* 95096 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
33896 /* 95099 */ GIR_RootToRootCopy, /*OpIdx*/7, // Vm
33897 /* 95101 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
33898 /* 95104 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33899 /* 95110 */ GIR_RootConstrainSelectedInstOperands,
33900 /* 95111 */ // GIR_Coverage, 3042,
33901 /* 95111 */ GIR_EraseRootFromParent_Done,
33902 /* 95112 */ // Label 1784: @95112
33903 /* 95112 */ GIM_Reject,
33904 /* 95113 */ // Label 1729: @95113
33905 /* 95113 */ GIM_Try, /*On fail goto*//*Label 1785*/ GIMT_Encode4(99407),
33906 /* 95118 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/10,
33907 /* 95121 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vshrn),
33908 /* 95126 */ GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(95233), // Rule ID 4116 //
33909 /* 95131 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33910 /* 95134 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33911 /* 95137 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33912 /* 95140 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33913 /* 95143 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33914 /* 95146 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33915 /* 95149 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33916 /* 95152 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
33917 /* 95155 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
33918 /* 95158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33919 /* 95162 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33920 /* 95166 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33921 /* 95170 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33922 /* 95174 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33923 /* 95178 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33924 /* 95182 */ // MIs[1] Operand 1
33925 /* 95182 */ // No operand predicates
33926 /* 95182 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33927 /* 95186 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33928 /* 95190 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33929 /* 95194 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33930 /* 95198 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
33931 /* 95202 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33932 /* 95204 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33933 /* 95204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh),
33934 /* 95207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33935 /* 95209 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
33936 /* 95211 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
33937 /* 95213 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33938 /* 95216 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33939 /* 95219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33940 /* 95225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33941 /* 95231 */ GIR_RootConstrainSelectedInstOperands,
33942 /* 95232 */ // GIR_Coverage, 4116,
33943 /* 95232 */ GIR_EraseRootFromParent_Done,
33944 /* 95233 */ // Label 1786: @95233
33945 /* 95233 */ GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(95340), // Rule ID 4118 //
33946 /* 95238 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
33947 /* 95241 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
33948 /* 95244 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
33949 /* 95247 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33950 /* 95250 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33951 /* 95253 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33952 /* 95256 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33953 /* 95259 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
33954 /* 95262 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
33955 /* 95265 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33956 /* 95269 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33957 /* 95273 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33958 /* 95277 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33959 /* 95281 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33960 /* 95285 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
33961 /* 95289 */ // MIs[1] Operand 1
33962 /* 95289 */ // No operand predicates
33963 /* 95289 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
33964 /* 95293 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
33965 /* 95297 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
33966 /* 95301 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
33967 /* 95305 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
33968 /* 95309 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
33969 /* 95311 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
33970 /* 95311 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th),
33971 /* 95314 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
33972 /* 95316 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
33973 /* 95318 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
33974 /* 95320 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
33975 /* 95323 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
33976 /* 95326 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33977 /* 95332 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
33978 /* 95338 */ GIR_RootConstrainSelectedInstOperands,
33979 /* 95339 */ // GIR_Coverage, 4118,
33980 /* 95339 */ GIR_EraseRootFromParent_Done,
33981 /* 95340 */ // Label 1787: @95340
33982 /* 95340 */ GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(95447), // Rule ID 4120 //
33983 /* 95345 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
33984 /* 95348 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
33985 /* 95351 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
33986 /* 95354 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
33987 /* 95357 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
33988 /* 95360 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
33989 /* 95363 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
33990 /* 95366 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
33991 /* 95369 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
33992 /* 95372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33993 /* 95376 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33994 /* 95380 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
33995 /* 95384 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
33996 /* 95388 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
33997 /* 95392 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
33998 /* 95396 */ // MIs[1] Operand 1
33999 /* 95396 */ // No operand predicates
34000 /* 95396 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34001 /* 95400 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34002 /* 95404 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34003 /* 95408 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34004 /* 95412 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34005 /* 95416 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34006 /* 95418 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34007 /* 95418 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh),
34008 /* 95421 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34009 /* 95423 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34010 /* 95425 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34011 /* 95427 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34012 /* 95430 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34013 /* 95433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34014 /* 95439 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34015 /* 95445 */ GIR_RootConstrainSelectedInstOperands,
34016 /* 95446 */ // GIR_Coverage, 4120,
34017 /* 95446 */ GIR_EraseRootFromParent_Done,
34018 /* 95447 */ // Label 1788: @95447
34019 /* 95447 */ GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(95554), // Rule ID 4122 //
34020 /* 95452 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34021 /* 95455 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34022 /* 95458 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34023 /* 95461 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34024 /* 95464 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34025 /* 95467 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34026 /* 95470 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34027 /* 95473 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34028 /* 95476 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34029 /* 95479 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34030 /* 95483 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34031 /* 95487 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34032 /* 95491 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34033 /* 95495 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34034 /* 95499 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34035 /* 95503 */ // MIs[1] Operand 1
34036 /* 95503 */ // No operand predicates
34037 /* 95503 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34038 /* 95507 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34039 /* 95511 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34040 /* 95515 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34041 /* 95519 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34042 /* 95523 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34043 /* 95525 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34044 /* 95525 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th),
34045 /* 95528 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34046 /* 95530 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34047 /* 95532 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34048 /* 95534 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34049 /* 95537 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34050 /* 95540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34051 /* 95546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34052 /* 95552 */ GIR_RootConstrainSelectedInstOperands,
34053 /* 95553 */ // GIR_Coverage, 4122,
34054 /* 95553 */ GIR_EraseRootFromParent_Done,
34055 /* 95554 */ // Label 1789: @95554
34056 /* 95554 */ GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(95661), // Rule ID 4124 //
34057 /* 95559 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34058 /* 95562 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34059 /* 95565 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34060 /* 95568 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34061 /* 95571 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34062 /* 95574 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34063 /* 95577 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34064 /* 95580 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34065 /* 95583 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34066 /* 95586 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34067 /* 95590 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34068 /* 95594 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34069 /* 95598 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34070 /* 95602 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34071 /* 95606 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34072 /* 95610 */ // MIs[1] Operand 1
34073 /* 95610 */ // No operand predicates
34074 /* 95610 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34075 /* 95614 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34076 /* 95618 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34077 /* 95622 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34078 /* 95626 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34079 /* 95630 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34080 /* 95632 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34081 /* 95632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16bh),
34082 /* 95635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34083 /* 95637 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34084 /* 95639 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34085 /* 95641 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34086 /* 95644 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34087 /* 95647 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34088 /* 95653 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34089 /* 95659 */ GIR_RootConstrainSelectedInstOperands,
34090 /* 95660 */ // GIR_Coverage, 4124,
34091 /* 95660 */ GIR_EraseRootFromParent_Done,
34092 /* 95661 */ // Label 1790: @95661
34093 /* 95661 */ GIM_Try, /*On fail goto*//*Label 1791*/ GIMT_Encode4(95768), // Rule ID 4126 //
34094 /* 95666 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34095 /* 95669 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34096 /* 95672 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34097 /* 95675 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34098 /* 95678 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34099 /* 95681 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34100 /* 95684 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34101 /* 95687 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34102 /* 95690 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34103 /* 95693 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34104 /* 95697 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34105 /* 95701 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34106 /* 95705 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34107 /* 95709 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34108 /* 95713 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34109 /* 95717 */ // MIs[1] Operand 1
34110 /* 95717 */ // No operand predicates
34111 /* 95717 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34112 /* 95721 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34113 /* 95725 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34114 /* 95729 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34115 /* 95733 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34116 /* 95737 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34117 /* 95739 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34118 /* 95739 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi16th),
34119 /* 95742 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34120 /* 95744 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34121 /* 95746 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34122 /* 95748 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34123 /* 95751 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34124 /* 95754 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34125 /* 95760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34126 /* 95766 */ GIR_RootConstrainSelectedInstOperands,
34127 /* 95767 */ // GIR_Coverage, 4126,
34128 /* 95767 */ GIR_EraseRootFromParent_Done,
34129 /* 95768 */ // Label 1791: @95768
34130 /* 95768 */ GIM_Try, /*On fail goto*//*Label 1792*/ GIMT_Encode4(95875), // Rule ID 4128 //
34131 /* 95773 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34132 /* 95776 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34133 /* 95779 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34134 /* 95782 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34135 /* 95785 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34136 /* 95788 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34137 /* 95791 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34138 /* 95794 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34139 /* 95797 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34140 /* 95800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34141 /* 95804 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34142 /* 95808 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34143 /* 95812 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34144 /* 95816 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34145 /* 95820 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34146 /* 95824 */ // MIs[1] Operand 1
34147 /* 95824 */ // No operand predicates
34148 /* 95824 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34149 /* 95828 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34150 /* 95832 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34151 /* 95836 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34152 /* 95840 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34153 /* 95844 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34154 /* 95846 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34155 /* 95846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32bh),
34156 /* 95849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34157 /* 95851 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34158 /* 95853 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34159 /* 95855 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34160 /* 95858 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34161 /* 95861 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34162 /* 95867 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34163 /* 95873 */ GIR_RootConstrainSelectedInstOperands,
34164 /* 95874 */ // GIR_Coverage, 4128,
34165 /* 95874 */ GIR_EraseRootFromParent_Done,
34166 /* 95875 */ // Label 1792: @95875
34167 /* 95875 */ GIM_Try, /*On fail goto*//*Label 1793*/ GIMT_Encode4(95982), // Rule ID 4130 //
34168 /* 95880 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34169 /* 95883 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34170 /* 95886 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34171 /* 95889 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34172 /* 95892 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34173 /* 95895 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34174 /* 95898 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34175 /* 95901 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34176 /* 95904 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34177 /* 95907 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34178 /* 95911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34179 /* 95915 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34180 /* 95919 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34181 /* 95923 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34182 /* 95927 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34183 /* 95931 */ // MIs[1] Operand 1
34184 /* 95931 */ // No operand predicates
34185 /* 95931 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34186 /* 95935 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34187 /* 95939 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34188 /* 95943 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34189 /* 95947 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34190 /* 95951 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34191 /* 95953 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34192 /* 95953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSHRNi32th),
34193 /* 95956 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34194 /* 95958 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34195 /* 95960 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34196 /* 95962 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34197 /* 95965 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34198 /* 95968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34199 /* 95974 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34200 /* 95980 */ GIR_RootConstrainSelectedInstOperands,
34201 /* 95981 */ // GIR_Coverage, 4130,
34202 /* 95981 */ GIR_EraseRootFromParent_Done,
34203 /* 95982 */ // Label 1793: @95982
34204 /* 95982 */ GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(96089), // Rule ID 4132 //
34205 /* 95987 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34206 /* 95990 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34207 /* 95993 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34208 /* 95996 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34209 /* 95999 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34210 /* 96002 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34211 /* 96005 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34212 /* 96008 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34213 /* 96011 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34214 /* 96014 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34215 /* 96018 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34216 /* 96022 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34217 /* 96026 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34218 /* 96030 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34219 /* 96034 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34220 /* 96038 */ // MIs[1] Operand 1
34221 /* 96038 */ // No operand predicates
34222 /* 96038 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34223 /* 96042 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34224 /* 96046 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34225 /* 96050 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34226 /* 96054 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34227 /* 96058 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34228 /* 96060 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34229 /* 96060 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh),
34230 /* 96063 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34231 /* 96065 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34232 /* 96067 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34233 /* 96069 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34234 /* 96072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34235 /* 96075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34236 /* 96081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34237 /* 96087 */ GIR_RootConstrainSelectedInstOperands,
34238 /* 96088 */ // GIR_Coverage, 4132,
34239 /* 96088 */ GIR_EraseRootFromParent_Done,
34240 /* 96089 */ // Label 1794: @96089
34241 /* 96089 */ GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(96196), // Rule ID 4134 //
34242 /* 96094 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34243 /* 96097 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34244 /* 96100 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34245 /* 96103 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34246 /* 96106 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34247 /* 96109 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34248 /* 96112 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34249 /* 96115 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34250 /* 96118 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34251 /* 96121 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34252 /* 96125 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34253 /* 96129 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34254 /* 96133 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34255 /* 96137 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34256 /* 96141 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34257 /* 96145 */ // MIs[1] Operand 1
34258 /* 96145 */ // No operand predicates
34259 /* 96145 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34260 /* 96149 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34261 /* 96153 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34262 /* 96157 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34263 /* 96161 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34264 /* 96165 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34265 /* 96167 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34266 /* 96167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th),
34267 /* 96170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34268 /* 96172 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34269 /* 96174 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34270 /* 96176 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34271 /* 96179 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34272 /* 96182 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34273 /* 96188 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34274 /* 96194 */ GIR_RootConstrainSelectedInstOperands,
34275 /* 96195 */ // GIR_Coverage, 4134,
34276 /* 96195 */ GIR_EraseRootFromParent_Done,
34277 /* 96196 */ // Label 1795: @96196
34278 /* 96196 */ GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(96303), // Rule ID 4136 //
34279 /* 96201 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34280 /* 96204 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34281 /* 96207 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34282 /* 96210 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34283 /* 96213 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34284 /* 96216 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34285 /* 96219 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34286 /* 96222 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34287 /* 96225 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34288 /* 96228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34289 /* 96232 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34290 /* 96236 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34291 /* 96240 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34292 /* 96244 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34293 /* 96248 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34294 /* 96252 */ // MIs[1] Operand 1
34295 /* 96252 */ // No operand predicates
34296 /* 96252 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34297 /* 96256 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34298 /* 96260 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34299 /* 96264 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34300 /* 96268 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34301 /* 96272 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34302 /* 96274 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34303 /* 96274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh),
34304 /* 96277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34305 /* 96279 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34306 /* 96281 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34307 /* 96283 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34308 /* 96286 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34309 /* 96289 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34310 /* 96295 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34311 /* 96301 */ GIR_RootConstrainSelectedInstOperands,
34312 /* 96302 */ // GIR_Coverage, 4136,
34313 /* 96302 */ GIR_EraseRootFromParent_Done,
34314 /* 96303 */ // Label 1796: @96303
34315 /* 96303 */ GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(96410), // Rule ID 4138 //
34316 /* 96308 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34317 /* 96311 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34318 /* 96314 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34319 /* 96317 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34320 /* 96320 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34321 /* 96323 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34322 /* 96326 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34323 /* 96329 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34324 /* 96332 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34325 /* 96335 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34326 /* 96339 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34327 /* 96343 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34328 /* 96347 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34329 /* 96351 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34330 /* 96355 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34331 /* 96359 */ // MIs[1] Operand 1
34332 /* 96359 */ // No operand predicates
34333 /* 96359 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34334 /* 96363 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34335 /* 96367 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34336 /* 96371 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34337 /* 96375 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34338 /* 96379 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34339 /* 96381 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34340 /* 96381 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th),
34341 /* 96384 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34342 /* 96386 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34343 /* 96388 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34344 /* 96390 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34345 /* 96393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34346 /* 96396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34347 /* 96402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34348 /* 96408 */ GIR_RootConstrainSelectedInstOperands,
34349 /* 96409 */ // GIR_Coverage, 4138,
34350 /* 96409 */ GIR_EraseRootFromParent_Done,
34351 /* 96410 */ // Label 1797: @96410
34352 /* 96410 */ GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(96517), // Rule ID 4140 //
34353 /* 96415 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34354 /* 96418 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34355 /* 96421 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34356 /* 96424 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34357 /* 96427 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34358 /* 96430 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34359 /* 96433 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34360 /* 96436 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34361 /* 96439 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34362 /* 96442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34363 /* 96446 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34364 /* 96450 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34365 /* 96454 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34366 /* 96458 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34367 /* 96462 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34368 /* 96466 */ // MIs[1] Operand 1
34369 /* 96466 */ // No operand predicates
34370 /* 96466 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34371 /* 96470 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34372 /* 96474 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34373 /* 96478 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34374 /* 96482 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34375 /* 96486 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34376 /* 96488 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34377 /* 96488 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16bh),
34378 /* 96491 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34379 /* 96493 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34380 /* 96495 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34381 /* 96497 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34382 /* 96500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34383 /* 96503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34384 /* 96509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34385 /* 96515 */ GIR_RootConstrainSelectedInstOperands,
34386 /* 96516 */ // GIR_Coverage, 4140,
34387 /* 96516 */ GIR_EraseRootFromParent_Done,
34388 /* 96517 */ // Label 1798: @96517
34389 /* 96517 */ GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(96624), // Rule ID 4142 //
34390 /* 96522 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34391 /* 96525 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34392 /* 96528 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34393 /* 96531 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34394 /* 96534 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34395 /* 96537 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34396 /* 96540 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34397 /* 96543 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34398 /* 96546 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34399 /* 96549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34400 /* 96553 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34401 /* 96557 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34402 /* 96561 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34403 /* 96565 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34404 /* 96569 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34405 /* 96573 */ // MIs[1] Operand 1
34406 /* 96573 */ // No operand predicates
34407 /* 96573 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34408 /* 96577 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34409 /* 96581 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34410 /* 96585 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34411 /* 96589 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34412 /* 96593 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34413 /* 96595 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34414 /* 96595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi16th),
34415 /* 96598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34416 /* 96600 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34417 /* 96602 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34418 /* 96604 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34419 /* 96607 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34420 /* 96610 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34421 /* 96616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34422 /* 96622 */ GIR_RootConstrainSelectedInstOperands,
34423 /* 96623 */ // GIR_Coverage, 4142,
34424 /* 96623 */ GIR_EraseRootFromParent_Done,
34425 /* 96624 */ // Label 1799: @96624
34426 /* 96624 */ GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(96731), // Rule ID 4144 //
34427 /* 96629 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34428 /* 96632 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34429 /* 96635 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34430 /* 96638 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34431 /* 96641 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34432 /* 96644 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34433 /* 96647 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34434 /* 96650 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34435 /* 96653 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34436 /* 96656 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34437 /* 96660 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34438 /* 96664 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34439 /* 96668 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34440 /* 96672 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34441 /* 96676 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34442 /* 96680 */ // MIs[1] Operand 1
34443 /* 96680 */ // No operand predicates
34444 /* 96680 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34445 /* 96684 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34446 /* 96688 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34447 /* 96692 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34448 /* 96696 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34449 /* 96700 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34450 /* 96702 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VRSHRNi32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34451 /* 96702 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32bh),
34452 /* 96705 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34453 /* 96707 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34454 /* 96709 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34455 /* 96711 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34456 /* 96714 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34457 /* 96717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34458 /* 96723 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34459 /* 96729 */ GIR_RootConstrainSelectedInstOperands,
34460 /* 96730 */ // GIR_Coverage, 4144,
34461 /* 96730 */ GIR_EraseRootFromParent_Done,
34462 /* 96731 */ // Label 1800: @96731
34463 /* 96731 */ GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(96838), // Rule ID 4146 //
34464 /* 96736 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34465 /* 96739 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34466 /* 96742 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34467 /* 96745 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34468 /* 96748 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34469 /* 96751 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34470 /* 96754 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34471 /* 96757 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34472 /* 96760 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34473 /* 96763 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34474 /* 96767 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34475 /* 96771 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34476 /* 96775 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34477 /* 96779 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34478 /* 96783 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34479 /* 96787 */ // MIs[1] Operand 1
34480 /* 96787 */ // No operand predicates
34481 /* 96787 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
34482 /* 96791 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34483 /* 96795 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34484 /* 96799 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34485 /* 96803 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34486 /* 96807 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34487 /* 96809 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VRSHRNi32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34488 /* 96809 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRSHRNi32th),
34489 /* 96812 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34490 /* 96814 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34491 /* 96816 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34492 /* 96818 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34493 /* 96821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34494 /* 96824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34495 /* 96830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34496 /* 96836 */ GIR_RootConstrainSelectedInstOperands,
34497 /* 96837 */ // GIR_Coverage, 4146,
34498 /* 96837 */ GIR_EraseRootFromParent_Done,
34499 /* 96838 */ // Label 1801: @96838
34500 /* 96838 */ GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(96945), // Rule ID 4148 //
34501 /* 96843 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34502 /* 96846 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34503 /* 96849 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34504 /* 96852 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34505 /* 96855 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34506 /* 96858 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34507 /* 96861 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34508 /* 96864 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34509 /* 96867 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34510 /* 96870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34511 /* 96874 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34512 /* 96878 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34513 /* 96882 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34514 /* 96886 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34515 /* 96890 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34516 /* 96894 */ // MIs[1] Operand 1
34517 /* 96894 */ // No operand predicates
34518 /* 96894 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34519 /* 96898 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34520 /* 96902 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34521 /* 96906 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34522 /* 96910 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34523 /* 96914 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34524 /* 96916 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34525 /* 96916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs16),
34526 /* 96919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34527 /* 96921 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34528 /* 96923 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34529 /* 96925 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34530 /* 96928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34531 /* 96931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34532 /* 96937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34533 /* 96943 */ GIR_RootConstrainSelectedInstOperands,
34534 /* 96944 */ // GIR_Coverage, 4148,
34535 /* 96944 */ GIR_EraseRootFromParent_Done,
34536 /* 96945 */ // Label 1802: @96945
34537 /* 96945 */ GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(97052), // Rule ID 4150 //
34538 /* 96950 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34539 /* 96953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34540 /* 96956 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34541 /* 96959 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34542 /* 96962 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34543 /* 96965 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34544 /* 96968 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34545 /* 96971 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34546 /* 96974 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34547 /* 96977 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34548 /* 96981 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34549 /* 96985 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34550 /* 96989 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34551 /* 96993 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34552 /* 96997 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34553 /* 97001 */ // MIs[1] Operand 1
34554 /* 97001 */ // No operand predicates
34555 /* 97001 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34556 /* 97005 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34557 /* 97009 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34558 /* 97013 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34559 /* 97017 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34560 /* 97021 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34561 /* 97023 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34562 /* 97023 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths16),
34563 /* 97026 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34564 /* 97028 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34565 /* 97030 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34566 /* 97032 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34567 /* 97035 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34568 /* 97038 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34569 /* 97044 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34570 /* 97050 */ GIR_RootConstrainSelectedInstOperands,
34571 /* 97051 */ // GIR_Coverage, 4150,
34572 /* 97051 */ GIR_EraseRootFromParent_Done,
34573 /* 97052 */ // Label 1803: @97052
34574 /* 97052 */ GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(97159), // Rule ID 4152 //
34575 /* 97057 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34576 /* 97060 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34577 /* 97063 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34578 /* 97066 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34579 /* 97069 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34580 /* 97072 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34581 /* 97075 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34582 /* 97078 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34583 /* 97081 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34584 /* 97084 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34585 /* 97088 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34586 /* 97092 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34587 /* 97096 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34588 /* 97100 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34589 /* 97104 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34590 /* 97108 */ // MIs[1] Operand 1
34591 /* 97108 */ // No operand predicates
34592 /* 97108 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34593 /* 97112 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34594 /* 97116 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34595 /* 97120 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34596 /* 97124 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34597 /* 97128 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34598 /* 97130 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34599 /* 97130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhs32),
34600 /* 97133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34601 /* 97135 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34602 /* 97137 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34603 /* 97139 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34604 /* 97142 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34605 /* 97145 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34606 /* 97151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34607 /* 97157 */ GIR_RootConstrainSelectedInstOperands,
34608 /* 97158 */ // GIR_Coverage, 4152,
34609 /* 97158 */ GIR_EraseRootFromParent_Done,
34610 /* 97159 */ // Label 1804: @97159
34611 /* 97159 */ GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(97266), // Rule ID 4154 //
34612 /* 97164 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34613 /* 97167 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34614 /* 97170 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34615 /* 97173 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34616 /* 97176 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34617 /* 97179 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34618 /* 97182 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34619 /* 97185 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34620 /* 97188 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34621 /* 97191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34622 /* 97195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34623 /* 97199 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34624 /* 97203 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34625 /* 97207 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34626 /* 97211 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34627 /* 97215 */ // MIs[1] Operand 1
34628 /* 97215 */ // No operand predicates
34629 /* 97215 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34630 /* 97219 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34631 /* 97223 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34632 /* 97227 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34633 /* 97231 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34634 /* 97235 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34635 /* 97237 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34636 /* 97237 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNths32),
34637 /* 97240 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34638 /* 97242 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34639 /* 97244 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34640 /* 97246 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34641 /* 97249 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34642 /* 97252 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34643 /* 97258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34644 /* 97264 */ GIR_RootConstrainSelectedInstOperands,
34645 /* 97265 */ // GIR_Coverage, 4154,
34646 /* 97265 */ GIR_EraseRootFromParent_Done,
34647 /* 97266 */ // Label 1805: @97266
34648 /* 97266 */ GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(97373), // Rule ID 4156 //
34649 /* 97271 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34650 /* 97274 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34651 /* 97277 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34652 /* 97280 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34653 /* 97283 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34654 /* 97286 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34655 /* 97289 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34656 /* 97292 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34657 /* 97295 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34658 /* 97298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34659 /* 97302 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34660 /* 97306 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34661 /* 97310 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34662 /* 97314 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34663 /* 97318 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34664 /* 97322 */ // MIs[1] Operand 1
34665 /* 97322 */ // No operand predicates
34666 /* 97322 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34667 /* 97326 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34668 /* 97330 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34669 /* 97334 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34670 /* 97338 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34671 /* 97342 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34672 /* 97344 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34673 /* 97344 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu16),
34674 /* 97347 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34675 /* 97349 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34676 /* 97351 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34677 /* 97353 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34678 /* 97356 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34679 /* 97359 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34680 /* 97365 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34681 /* 97371 */ GIR_RootConstrainSelectedInstOperands,
34682 /* 97372 */ // GIR_Coverage, 4156,
34683 /* 97372 */ GIR_EraseRootFromParent_Done,
34684 /* 97373 */ // Label 1806: @97373
34685 /* 97373 */ GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(97480), // Rule ID 4158 //
34686 /* 97378 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34687 /* 97381 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34688 /* 97384 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34689 /* 97387 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34690 /* 97390 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34691 /* 97393 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34692 /* 97396 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34693 /* 97399 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34694 /* 97402 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34695 /* 97405 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34696 /* 97409 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34697 /* 97413 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34698 /* 97417 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34699 /* 97421 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34700 /* 97425 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34701 /* 97429 */ // MIs[1] Operand 1
34702 /* 97429 */ // No operand predicates
34703 /* 97429 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34704 /* 97433 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34705 /* 97437 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34706 /* 97441 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34707 /* 97445 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34708 /* 97449 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34709 /* 97451 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34710 /* 97451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu16),
34711 /* 97454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34712 /* 97456 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34713 /* 97458 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34714 /* 97460 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34715 /* 97463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34716 /* 97466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34717 /* 97472 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34718 /* 97478 */ GIR_RootConstrainSelectedInstOperands,
34719 /* 97479 */ // GIR_Coverage, 4158,
34720 /* 97479 */ GIR_EraseRootFromParent_Done,
34721 /* 97480 */ // Label 1807: @97480
34722 /* 97480 */ GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(97587), // Rule ID 4160 //
34723 /* 97485 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34724 /* 97488 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34725 /* 97491 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34726 /* 97494 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34727 /* 97497 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34728 /* 97500 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34729 /* 97503 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34730 /* 97506 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34731 /* 97509 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34732 /* 97512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34733 /* 97516 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34734 /* 97520 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34735 /* 97524 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34736 /* 97528 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34737 /* 97532 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34738 /* 97536 */ // MIs[1] Operand 1
34739 /* 97536 */ // No operand predicates
34740 /* 97536 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34741 /* 97540 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34742 /* 97544 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34743 /* 97548 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34744 /* 97552 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34745 /* 97556 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34746 /* 97558 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34747 /* 97558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNbhu32),
34748 /* 97561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34749 /* 97563 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34750 /* 97565 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34751 /* 97567 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34752 /* 97570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34753 /* 97573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34754 /* 97579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34755 /* 97585 */ GIR_RootConstrainSelectedInstOperands,
34756 /* 97586 */ // GIR_Coverage, 4160,
34757 /* 97586 */ GIR_EraseRootFromParent_Done,
34758 /* 97587 */ // Label 1808: @97587
34759 /* 97587 */ GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(97694), // Rule ID 4162 //
34760 /* 97592 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34761 /* 97595 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34762 /* 97598 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34763 /* 97601 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34764 /* 97604 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34765 /* 97607 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34766 /* 97610 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34767 /* 97613 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34768 /* 97616 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34769 /* 97619 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34770 /* 97623 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34771 /* 97627 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34772 /* 97631 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34773 /* 97635 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34774 /* 97639 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34775 /* 97643 */ // MIs[1] Operand 1
34776 /* 97643 */ // No operand predicates
34777 /* 97643 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34778 /* 97647 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
34779 /* 97651 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34780 /* 97655 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34781 /* 97659 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34782 /* 97663 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34783 /* 97665 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34784 /* 97665 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRNthu32),
34785 /* 97668 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34786 /* 97670 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34787 /* 97672 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34788 /* 97674 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34789 /* 97677 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34790 /* 97680 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34791 /* 97686 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34792 /* 97692 */ GIR_RootConstrainSelectedInstOperands,
34793 /* 97693 */ // GIR_Coverage, 4162,
34794 /* 97693 */ GIR_EraseRootFromParent_Done,
34795 /* 97694 */ // Label 1809: @97694
34796 /* 97694 */ GIM_Try, /*On fail goto*//*Label 1810*/ GIMT_Encode4(97801), // Rule ID 4164 //
34797 /* 97699 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34798 /* 97702 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34799 /* 97705 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34800 /* 97708 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34801 /* 97711 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34802 /* 97714 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34803 /* 97717 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34804 /* 97720 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34805 /* 97723 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34806 /* 97726 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34807 /* 97730 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34808 /* 97734 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34809 /* 97738 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34810 /* 97742 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34811 /* 97746 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34812 /* 97750 */ // MIs[1] Operand 1
34813 /* 97750 */ // No operand predicates
34814 /* 97750 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34815 /* 97754 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34816 /* 97758 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34817 /* 97762 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34818 /* 97766 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34819 /* 97770 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34820 /* 97772 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34821 /* 97772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs16),
34822 /* 97775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34823 /* 97777 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34824 /* 97779 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34825 /* 97781 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34826 /* 97784 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34827 /* 97787 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34828 /* 97793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34829 /* 97799 */ GIR_RootConstrainSelectedInstOperands,
34830 /* 97800 */ // GIR_Coverage, 4164,
34831 /* 97800 */ GIR_EraseRootFromParent_Done,
34832 /* 97801 */ // Label 1810: @97801
34833 /* 97801 */ GIM_Try, /*On fail goto*//*Label 1811*/ GIMT_Encode4(97908), // Rule ID 4166 //
34834 /* 97806 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34835 /* 97809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34836 /* 97812 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34837 /* 97815 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34838 /* 97818 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34839 /* 97821 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34840 /* 97824 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34841 /* 97827 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34842 /* 97830 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34843 /* 97833 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34844 /* 97837 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34845 /* 97841 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34846 /* 97845 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34847 /* 97849 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34848 /* 97853 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34849 /* 97857 */ // MIs[1] Operand 1
34850 /* 97857 */ // No operand predicates
34851 /* 97857 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34852 /* 97861 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34853 /* 97865 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34854 /* 97869 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34855 /* 97873 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34856 /* 97877 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34857 /* 97879 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34858 /* 97879 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths16),
34859 /* 97882 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34860 /* 97884 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34861 /* 97886 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34862 /* 97888 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34863 /* 97891 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34864 /* 97894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34865 /* 97900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34866 /* 97906 */ GIR_RootConstrainSelectedInstOperands,
34867 /* 97907 */ // GIR_Coverage, 4166,
34868 /* 97907 */ GIR_EraseRootFromParent_Done,
34869 /* 97908 */ // Label 1811: @97908
34870 /* 97908 */ GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(98015), // Rule ID 4168 //
34871 /* 97913 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34872 /* 97916 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34873 /* 97919 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34874 /* 97922 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34875 /* 97925 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34876 /* 97928 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34877 /* 97931 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34878 /* 97934 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34879 /* 97937 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34880 /* 97940 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34881 /* 97944 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34882 /* 97948 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34883 /* 97952 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34884 /* 97956 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34885 /* 97960 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34886 /* 97964 */ // MIs[1] Operand 1
34887 /* 97964 */ // No operand predicates
34888 /* 97964 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34889 /* 97968 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34890 /* 97972 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34891 /* 97976 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34892 /* 97980 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34893 /* 97984 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34894 /* 97986 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhs32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34895 /* 97986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhs32),
34896 /* 97989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34897 /* 97991 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34898 /* 97993 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34899 /* 97995 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34900 /* 97998 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34901 /* 98001 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34902 /* 98007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34903 /* 98013 */ GIR_RootConstrainSelectedInstOperands,
34904 /* 98014 */ // GIR_Coverage, 4168,
34905 /* 98014 */ GIR_EraseRootFromParent_Done,
34906 /* 98015 */ // Label 1812: @98015
34907 /* 98015 */ GIM_Try, /*On fail goto*//*Label 1813*/ GIMT_Encode4(98122), // Rule ID 4170 //
34908 /* 98020 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
34909 /* 98023 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
34910 /* 98026 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
34911 /* 98029 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34912 /* 98032 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34913 /* 98035 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34914 /* 98038 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34915 /* 98041 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34916 /* 98044 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34917 /* 98047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34918 /* 98051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34919 /* 98055 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34920 /* 98059 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34921 /* 98063 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34922 /* 98067 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
34923 /* 98071 */ // MIs[1] Operand 1
34924 /* 98071 */ // No operand predicates
34925 /* 98071 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34926 /* 98075 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34927 /* 98079 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 0,
34928 /* 98083 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
34929 /* 98087 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
34930 /* 98091 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34931 /* 98093 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNths32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
34932 /* 98093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNths32),
34933 /* 98096 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34934 /* 98098 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34935 /* 98100 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34936 /* 98102 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34937 /* 98105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34938 /* 98108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34939 /* 98114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34940 /* 98120 */ GIR_RootConstrainSelectedInstOperands,
34941 /* 98121 */ // GIR_Coverage, 4170,
34942 /* 98121 */ GIR_EraseRootFromParent_Done,
34943 /* 98122 */ // Label 1813: @98122
34944 /* 98122 */ GIM_Try, /*On fail goto*//*Label 1814*/ GIMT_Encode4(98229), // Rule ID 4172 //
34945 /* 98127 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34946 /* 98130 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34947 /* 98133 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34948 /* 98136 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34949 /* 98139 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34950 /* 98142 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34951 /* 98145 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34952 /* 98148 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34953 /* 98151 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34954 /* 98154 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34955 /* 98158 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34956 /* 98162 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34957 /* 98166 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34958 /* 98170 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34959 /* 98174 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34960 /* 98178 */ // MIs[1] Operand 1
34961 /* 98178 */ // No operand predicates
34962 /* 98178 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
34963 /* 98182 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
34964 /* 98186 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
34965 /* 98190 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
34966 /* 98194 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
34967 /* 98198 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
34968 /* 98200 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
34969 /* 98200 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu16),
34970 /* 98203 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
34971 /* 98205 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
34972 /* 98207 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
34973 /* 98209 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
34974 /* 98212 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
34975 /* 98215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34976 /* 98221 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
34977 /* 98227 */ GIR_RootConstrainSelectedInstOperands,
34978 /* 98228 */ // GIR_Coverage, 4172,
34979 /* 98228 */ GIR_EraseRootFromParent_Done,
34980 /* 98229 */ // Label 1814: @98229
34981 /* 98229 */ GIM_Try, /*On fail goto*//*Label 1815*/ GIMT_Encode4(98336), // Rule ID 4174 //
34982 /* 98234 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
34983 /* 98237 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
34984 /* 98240 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
34985 /* 98243 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
34986 /* 98246 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
34987 /* 98249 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
34988 /* 98252 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
34989 /* 98255 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
34990 /* 98258 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
34991 /* 98261 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34992 /* 98265 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34993 /* 98269 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
34994 /* 98273 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
34995 /* 98277 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
34996 /* 98281 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
34997 /* 98285 */ // MIs[1] Operand 1
34998 /* 98285 */ // No operand predicates
34999 /* 98285 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
35000 /* 98289 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
35001 /* 98293 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
35002 /* 98297 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
35003 /* 98301 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
35004 /* 98305 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35005 /* 98307 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu16:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
35006 /* 98307 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu16),
35007 /* 98310 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35008 /* 98312 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
35009 /* 98314 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
35010 /* 98316 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35011 /* 98319 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35012 /* 98322 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35013 /* 98328 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35014 /* 98334 */ GIR_RootConstrainSelectedInstOperands,
35015 /* 98335 */ // GIR_Coverage, 4174,
35016 /* 98335 */ GIR_EraseRootFromParent_Done,
35017 /* 98336 */ // Label 1815: @98336
35018 /* 98336 */ GIM_Try, /*On fail goto*//*Label 1816*/ GIMT_Encode4(98443), // Rule ID 4176 //
35019 /* 98341 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
35020 /* 98344 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
35021 /* 98347 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
35022 /* 98350 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
35023 /* 98353 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
35024 /* 98356 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
35025 /* 98359 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
35026 /* 98362 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
35027 /* 98365 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
35028 /* 98368 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35029 /* 98372 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35030 /* 98376 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35031 /* 98380 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
35032 /* 98384 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35033 /* 98388 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
35034 /* 98392 */ // MIs[1] Operand 1
35035 /* 98392 */ // No operand predicates
35036 /* 98392 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
35037 /* 98396 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
35038 /* 98400 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
35039 /* 98404 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
35040 /* 98408 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
35041 /* 98412 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35042 /* 98414 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRNbhu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
35043 /* 98414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNbhu32),
35044 /* 98417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35045 /* 98419 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
35046 /* 98421 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
35047 /* 98423 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35048 /* 98426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35049 /* 98429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35050 /* 98435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35051 /* 98441 */ GIR_RootConstrainSelectedInstOperands,
35052 /* 98442 */ // GIR_Coverage, 4176,
35053 /* 98442 */ GIR_EraseRootFromParent_Done,
35054 /* 98443 */ // Label 1816: @98443
35055 /* 98443 */ GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(98550), // Rule ID 4178 //
35056 /* 98448 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
35057 /* 98451 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
35058 /* 98454 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
35059 /* 98457 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
35060 /* 98460 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
35061 /* 98463 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
35062 /* 98466 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
35063 /* 98469 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
35064 /* 98472 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
35065 /* 98475 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35066 /* 98479 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35067 /* 98483 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35068 /* 98487 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
35069 /* 98491 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35070 /* 98495 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
35071 /* 98499 */ // MIs[1] Operand 1
35072 /* 98499 */ // No operand predicates
35073 /* 98499 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
35074 /* 98503 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
35075 /* 98507 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
35076 /* 98511 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 1,
35077 /* 98515 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
35078 /* 98519 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35079 /* 98521 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRNthu32:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
35080 /* 98521 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRNthu32),
35081 /* 98524 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35082 /* 98526 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
35083 /* 98528 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
35084 /* 98530 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35085 /* 98533 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35086 /* 98536 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35087 /* 98542 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35088 /* 98548 */ GIR_RootConstrainSelectedInstOperands,
35089 /* 98549 */ // GIR_Coverage, 4178,
35090 /* 98549 */ GIR_EraseRootFromParent_Done,
35091 /* 98550 */ // Label 1817: @98550
35092 /* 98550 */ GIM_Try, /*On fail goto*//*Label 1818*/ GIMT_Encode4(98657), // Rule ID 4180 //
35093 /* 98555 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
35094 /* 98558 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
35095 /* 98561 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
35096 /* 98564 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
35097 /* 98567 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
35098 /* 98570 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
35099 /* 98573 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
35100 /* 98576 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
35101 /* 98579 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
35102 /* 98582 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35103 /* 98586 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35104 /* 98590 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35105 /* 98594 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
35106 /* 98598 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35107 /* 98602 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
35108 /* 98606 */ // MIs[1] Operand 1
35109 /* 98606 */ // No operand predicates
35110 /* 98606 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
35111 /* 98610 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
35112 /* 98614 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
35113 /* 98618 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
35114 /* 98622 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
35115 /* 98626 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35116 /* 98628 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
35117 /* 98628 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16bh),
35118 /* 98631 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35119 /* 98633 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
35120 /* 98635 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
35121 /* 98637 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35122 /* 98640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35123 /* 98643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35124 /* 98649 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35125 /* 98655 */ GIR_RootConstrainSelectedInstOperands,
35126 /* 98656 */ // GIR_Coverage, 4180,
35127 /* 98656 */ GIR_EraseRootFromParent_Done,
35128 /* 98657 */ // Label 1818: @98657
35129 /* 98657 */ GIM_Try, /*On fail goto*//*Label 1819*/ GIMT_Encode4(98764), // Rule ID 4182 //
35130 /* 98662 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
35131 /* 98665 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
35132 /* 98668 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
35133 /* 98671 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
35134 /* 98674 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
35135 /* 98677 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
35136 /* 98680 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
35137 /* 98683 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
35138 /* 98686 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
35139 /* 98689 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35140 /* 98693 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35141 /* 98697 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35142 /* 98701 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
35143 /* 98705 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35144 /* 98709 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
35145 /* 98713 */ // MIs[1] Operand 1
35146 /* 98713 */ // No operand predicates
35147 /* 98713 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
35148 /* 98717 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
35149 /* 98721 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
35150 /* 98725 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
35151 /* 98729 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
35152 /* 98733 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35153 /* 98735 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
35154 /* 98735 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs16th),
35155 /* 98738 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35156 /* 98740 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
35157 /* 98742 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
35158 /* 98744 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35159 /* 98747 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35160 /* 98750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35161 /* 98756 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35162 /* 98762 */ GIR_RootConstrainSelectedInstOperands,
35163 /* 98763 */ // GIR_Coverage, 4182,
35164 /* 98763 */ GIR_EraseRootFromParent_Done,
35165 /* 98764 */ // Label 1819: @98764
35166 /* 98764 */ GIM_Try, /*On fail goto*//*Label 1820*/ GIMT_Encode4(98871), // Rule ID 4184 //
35167 /* 98769 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
35168 /* 98772 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
35169 /* 98775 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
35170 /* 98778 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
35171 /* 98781 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
35172 /* 98784 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
35173 /* 98787 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
35174 /* 98790 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
35175 /* 98793 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
35176 /* 98796 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35177 /* 98800 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35178 /* 98804 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35179 /* 98808 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
35180 /* 98812 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35181 /* 98816 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
35182 /* 98820 */ // MIs[1] Operand 1
35183 /* 98820 */ // No operand predicates
35184 /* 98820 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
35185 /* 98824 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
35186 /* 98828 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
35187 /* 98832 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
35188 /* 98836 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
35189 /* 98840 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35190 /* 98842 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
35191 /* 98842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32bh),
35192 /* 98845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35193 /* 98847 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
35194 /* 98849 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
35195 /* 98851 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35196 /* 98854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35197 /* 98857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35198 /* 98863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35199 /* 98869 */ GIR_RootConstrainSelectedInstOperands,
35200 /* 98870 */ // GIR_Coverage, 4184,
35201 /* 98870 */ GIR_EraseRootFromParent_Done,
35202 /* 98871 */ // Label 1820: @98871
35203 /* 98871 */ GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(98978), // Rule ID 4186 //
35204 /* 98876 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
35205 /* 98879 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
35206 /* 98882 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
35207 /* 98885 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
35208 /* 98888 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
35209 /* 98891 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
35210 /* 98894 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
35211 /* 98897 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
35212 /* 98900 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
35213 /* 98903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35214 /* 98907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35215 /* 98911 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35216 /* 98915 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
35217 /* 98919 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35218 /* 98923 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
35219 /* 98927 */ // MIs[1] Operand 1
35220 /* 98927 */ // No operand predicates
35221 /* 98927 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
35222 /* 98931 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
35223 /* 98935 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
35224 /* 98939 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
35225 /* 98943 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
35226 /* 98947 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35227 /* 98949 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
35228 /* 98949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSHRUNs32th),
35229 /* 98952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35230 /* 98954 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
35231 /* 98956 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
35232 /* 98958 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35233 /* 98961 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35234 /* 98964 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35235 /* 98970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35236 /* 98976 */ GIR_RootConstrainSelectedInstOperands,
35237 /* 98977 */ // GIR_Coverage, 4186,
35238 /* 98977 */ GIR_EraseRootFromParent_Done,
35239 /* 98978 */ // Label 1821: @98978
35240 /* 98978 */ GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(99085), // Rule ID 4188 //
35241 /* 98983 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
35242 /* 98986 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
35243 /* 98989 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
35244 /* 98992 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
35245 /* 98995 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
35246 /* 98998 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
35247 /* 99001 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
35248 /* 99004 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
35249 /* 99007 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
35250 /* 99010 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35251 /* 99014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35252 /* 99018 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35253 /* 99022 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
35254 /* 99026 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35255 /* 99030 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
35256 /* 99034 */ // MIs[1] Operand 1
35257 /* 99034 */ // No operand predicates
35258 /* 99034 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
35259 /* 99038 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
35260 /* 99042 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
35261 /* 99046 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
35262 /* 99050 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
35263 /* 99054 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35264 /* 99056 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs16bh:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
35265 /* 99056 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16bh),
35266 /* 99059 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35267 /* 99061 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
35268 /* 99063 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
35269 /* 99065 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35270 /* 99068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35271 /* 99071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35272 /* 99077 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35273 /* 99083 */ GIR_RootConstrainSelectedInstOperands,
35274 /* 99084 */ // GIR_Coverage, 4188,
35275 /* 99084 */ GIR_EraseRootFromParent_Done,
35276 /* 99085 */ // Label 1822: @99085
35277 /* 99085 */ GIM_Try, /*On fail goto*//*Label 1823*/ GIMT_Encode4(99192), // Rule ID 4190 //
35278 /* 99090 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
35279 /* 99093 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
35280 /* 99096 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
35281 /* 99099 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
35282 /* 99102 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
35283 /* 99105 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
35284 /* 99108 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
35285 /* 99111 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
35286 /* 99114 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
35287 /* 99117 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35288 /* 99121 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35289 /* 99125 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35290 /* 99129 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
35291 /* 99133 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35292 /* 99137 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm8),
35293 /* 99141 */ // MIs[1] Operand 1
35294 /* 99141 */ // No operand predicates
35295 /* 99141 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
35296 /* 99145 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
35297 /* 99149 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
35298 /* 99153 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
35299 /* 99157 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
35300 /* 99161 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35301 /* 99163 */ // (intrinsic_wo_chain:{ *:[v16i8] } 3950:{ *:[iPTR] }, MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm8>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs16th:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$QdSrc, MQPR:{ *:[v8i16] }:$Qm, (imm:{ *:[i32] }):$imm)
35302 /* 99163 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs16th),
35303 /* 99166 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35304 /* 99168 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
35305 /* 99170 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
35306 /* 99172 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35307 /* 99175 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35308 /* 99178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35309 /* 99184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35310 /* 99190 */ GIR_RootConstrainSelectedInstOperands,
35311 /* 99191 */ // GIR_Coverage, 4190,
35312 /* 99191 */ GIR_EraseRootFromParent_Done,
35313 /* 99192 */ // Label 1823: @99192
35314 /* 99192 */ GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(99299), // Rule ID 4192 //
35315 /* 99197 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
35316 /* 99200 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
35317 /* 99203 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
35318 /* 99206 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
35319 /* 99209 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
35320 /* 99212 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
35321 /* 99215 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
35322 /* 99218 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
35323 /* 99221 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
35324 /* 99224 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35325 /* 99228 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35326 /* 99232 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35327 /* 99236 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
35328 /* 99240 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35329 /* 99244 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
35330 /* 99248 */ // MIs[1] Operand 1
35331 /* 99248 */ // No operand predicates
35332 /* 99248 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
35333 /* 99252 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
35334 /* 99256 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
35335 /* 99260 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
35336 /* 99264 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 0,
35337 /* 99268 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35338 /* 99270 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VQRSHRUNs32bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
35339 /* 99270 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32bh),
35340 /* 99273 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35341 /* 99275 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
35342 /* 99277 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
35343 /* 99279 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35344 /* 99282 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35345 /* 99285 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35346 /* 99291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35347 /* 99297 */ GIR_RootConstrainSelectedInstOperands,
35348 /* 99298 */ // GIR_Coverage, 4192,
35349 /* 99298 */ GIR_EraseRootFromParent_Done,
35350 /* 99299 */ // Label 1824: @99299
35351 /* 99299 */ GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(99406), // Rule ID 4194 //
35352 /* 99304 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
35353 /* 99307 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
35354 /* 99310 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
35355 /* 99313 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
35356 /* 99316 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
35357 /* 99319 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
35358 /* 99322 */ GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32,
35359 /* 99325 */ GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32,
35360 /* 99328 */ GIM_RootCheckType, /*Op*/9, /*Type*/GILLT_s32,
35361 /* 99331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35362 /* 99335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35363 /* 99339 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35364 /* 99343 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/4, // MIs[1]
35365 /* 99347 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35366 /* 99351 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_shr_imm16),
35367 /* 99355 */ // MIs[1] Operand 1
35368 /* 99355 */ // No operand predicates
35369 /* 99355 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
35370 /* 99359 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
35371 /* 99363 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/7, 1,
35372 /* 99367 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/8, 0,
35373 /* 99371 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/9, 1,
35374 /* 99375 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35375 /* 99377 */ // (intrinsic_wo_chain:{ *:[v8i16] } 3950:{ *:[iPTR] }, MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] })<<P:Predicate_shr_imm16>>:$imm, 1:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VQRSHRUNs32th:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$QdSrc, MQPR:{ *:[v4i32] }:$Qm, (imm:{ *:[i32] }):$imm)
35376 /* 99377 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQRSHRUNs32th),
35377 /* 99380 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35378 /* 99382 */ GIR_RootToRootCopy, /*OpIdx*/2, // QdSrc
35379 /* 99384 */ GIR_RootToRootCopy, /*OpIdx*/3, // Qm
35380 /* 99386 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35381 /* 99389 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
35382 /* 99392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35383 /* 99398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35384 /* 99404 */ GIR_RootConstrainSelectedInstOperands,
35385 /* 99405 */ // GIR_Coverage, 4194,
35386 /* 99405 */ GIR_EraseRootFromParent_Done,
35387 /* 99406 */ // Label 1825: @99406
35388 /* 99406 */ GIM_Reject,
35389 /* 99407 */ // Label 1785: @99407
35390 /* 99407 */ GIM_Reject,
35391 /* 99408 */ // Label 22: @99408
35392 /* 99408 */ GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(99465),
35393 /* 99413 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/1,
35394 /* 99416 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_clrex),
35395 /* 99421 */ GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(99438), // Rule ID 244 //
35396 /* 99426 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6K_IsARM),
35397 /* 99429 */ // (intrinsic_void 3717:{ *:[iPTR] }) => (CLREX)
35398 /* 99429 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLREX),
35399 /* 99432 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35400 /* 99436 */ GIR_RootConstrainSelectedInstOperands,
35401 /* 99437 */ // GIR_Coverage, 244,
35402 /* 99437 */ GIR_EraseRootFromParent_Done,
35403 /* 99438 */ // Label 1827: @99438
35404 /* 99438 */ GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(99464), // Rule ID 573 //
35405 /* 99443 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV7Clrex_IsThumb),
35406 /* 99446 */ // (intrinsic_void 3717:{ *:[iPTR] }) => (t2CLREX)
35407 /* 99446 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLREX),
35408 /* 99449 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35409 /* 99452 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35410 /* 99458 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35411 /* 99462 */ GIR_RootConstrainSelectedInstOperands,
35412 /* 99463 */ // GIR_Coverage, 573,
35413 /* 99463 */ GIR_EraseRootFromParent_Done,
35414 /* 99464 */ // Label 1828: @99464
35415 /* 99464 */ GIM_Reject,
35416 /* 99465 */ // Label 1826: @99465
35417 /* 99465 */ GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(100267),
35418 /* 99470 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/2,
35419 /* 99473 */ GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(99509), // Rule ID 343 //
35420 /* 99478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsWindows),
35421 /* 99481 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
35422 /* 99486 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35423 /* 99489 */ GIM_CheckConstantInt, /*MI*/0, /*Op*/1, GIMT_Encode8(249),
35424 /* 99500 */ // (intrinsic_void 4171:{ *:[iPTR] }, 249:{ *:[i32] }) => (t__brkdiv0)
35425 /* 99500 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t__brkdiv0),
35426 /* 99503 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35427 /* 99507 */ GIR_RootConstrainSelectedInstOperands,
35428 /* 99508 */ // GIR_Coverage, 343,
35429 /* 99508 */ GIR_EraseRootFromParent_Done,
35430 /* 99509 */ // Label 1830: @99509
35431 /* 99509 */ GIM_Try, /*On fail goto*//*Label 1831*/ GIMT_Encode4(99561), // Rule ID 2 //
35432 /* 99514 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
35433 /* 99517 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint),
35434 /* 99522 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35435 /* 99525 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35436 /* 99529 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35437 /* 99533 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239),
35438 /* 99537 */ // MIs[1] Operand 1
35439 /* 99537 */ // No operand predicates
35440 /* 99537 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35441 /* 99539 */ // (intrinsic_void 3735:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (HINT (imm:{ *:[i32] }):$imm)
35442 /* 99539 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::HINT),
35443 /* 99542 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35444 /* 99545 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35445 /* 99548 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35446 /* 99554 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35447 /* 99559 */ GIR_RootConstrainSelectedInstOperands,
35448 /* 99560 */ // GIR_Coverage, 2,
35449 /* 99560 */ GIR_EraseRootFromParent_Done,
35450 /* 99561 */ // Label 1831: @99561
35451 /* 99561 */ GIM_Try, /*On fail goto*//*Label 1832*/ GIMT_Encode4(99613), // Rule ID 10 //
35452 /* 99566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV7_IsARM),
35453 /* 99569 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg),
35454 /* 99574 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35455 /* 99577 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35456 /* 99581 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35457 /* 99585 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35458 /* 99589 */ // MIs[1] Operand 1
35459 /* 99589 */ // No operand predicates
35460 /* 99589 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35461 /* 99591 */ // (intrinsic_void 3730:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DBG (imm:{ *:[i32] }):$opt)
35462 /* 99591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DBG),
35463 /* 99594 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35464 /* 99597 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35465 /* 99600 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35466 /* 99606 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35467 /* 99611 */ GIR_RootConstrainSelectedInstOperands,
35468 /* 99612 */ // GIR_Coverage, 10,
35469 /* 99612 */ GIR_EraseRootFromParent_Done,
35470 /* 99613 */ // Label 1832: @99613
35471 /* 99613 */ GIM_Try, /*On fail goto*//*Label 1833*/ GIMT_Encode4(99656), // Rule ID 11 //
35472 /* 99618 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35473 /* 99621 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
35474 /* 99626 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35475 /* 99629 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35476 /* 99633 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35477 /* 99637 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
35478 /* 99641 */ // MIs[1] Operand 1
35479 /* 99641 */ // No operand predicates
35480 /* 99641 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35481 /* 99643 */ // (intrinsic_void 4171:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (UDF (imm:{ *:[i32] }):$imm16)
35482 /* 99643 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF),
35483 /* 99646 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
35484 /* 99649 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35485 /* 99654 */ GIR_RootConstrainSelectedInstOperands,
35486 /* 99655 */ // GIR_Coverage, 11,
35487 /* 99655 */ GIR_EraseRootFromParent_Done,
35488 /* 99656 */ // Label 1833: @99656
35489 /* 99656 */ GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(99699), // Rule ID 227 //
35490 /* 99661 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM),
35491 /* 99664 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb),
35492 /* 99669 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35493 /* 99672 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35494 /* 99676 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35495 /* 99680 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35496 /* 99684 */ // MIs[1] Operand 1
35497 /* 99684 */ // No operand predicates
35498 /* 99684 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35499 /* 99686 */ // (intrinsic_void 3731:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DMB (imm:{ *:[i32] }):$opt)
35500 /* 99686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DMB),
35501 /* 99689 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35502 /* 99692 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35503 /* 99697 */ GIR_RootConstrainSelectedInstOperands,
35504 /* 99698 */ // GIR_Coverage, 227,
35505 /* 99698 */ GIR_EraseRootFromParent_Done,
35506 /* 99699 */ // Label 1834: @99699
35507 /* 99699 */ GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(99742), // Rule ID 228 //
35508 /* 99704 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM),
35509 /* 99707 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb),
35510 /* 99712 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35511 /* 99715 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35512 /* 99719 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35513 /* 99723 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35514 /* 99727 */ // MIs[1] Operand 1
35515 /* 99727 */ // No operand predicates
35516 /* 99727 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35517 /* 99729 */ // (intrinsic_void 3732:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (DSB (imm:{ *:[i32] }):$opt)
35518 /* 99729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::DSB),
35519 /* 99732 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35520 /* 99735 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35521 /* 99740 */ GIR_RootConstrainSelectedInstOperands,
35522 /* 99741 */ // GIR_Coverage, 228,
35523 /* 99741 */ GIR_EraseRootFromParent_Done,
35524 /* 99742 */ // Label 1835: @99742
35525 /* 99742 */ GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(99785), // Rule ID 229 //
35526 /* 99747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsARM),
35527 /* 99750 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb),
35528 /* 99755 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35529 /* 99758 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35530 /* 99762 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35531 /* 99766 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35532 /* 99770 */ // MIs[1] Operand 1
35533 /* 99770 */ // No operand predicates
35534 /* 99770 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35535 /* 99772 */ // (intrinsic_void 3736:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (ISB (imm:{ *:[i32] }):$opt)
35536 /* 99772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::ISB),
35537 /* 99775 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35538 /* 99778 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35539 /* 99783 */ GIR_RootConstrainSelectedInstOperands,
35540 /* 99784 */ // GIR_Coverage, 229,
35541 /* 99784 */ GIR_EraseRootFromParent_Done,
35542 /* 99785 */ // Label 1836: @99785
35543 /* 99785 */ GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(99837), // Rule ID 275 //
35544 /* 99790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6M_IsThumb),
35545 /* 99793 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint),
35546 /* 99798 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35547 /* 99801 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35548 /* 99805 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35549 /* 99809 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35550 /* 99813 */ // MIs[1] Operand 1
35551 /* 99813 */ // No operand predicates
35552 /* 99813 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35553 /* 99815 */ // (intrinsic_void 3735:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$imm) => (tHINT (imm:{ *:[i32] }):$imm)
35554 /* 99815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tHINT),
35555 /* 99818 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35556 /* 99821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35557 /* 99824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35558 /* 99830 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35559 /* 99835 */ GIR_RootConstrainSelectedInstOperands,
35560 /* 99836 */ // GIR_Coverage, 275,
35561 /* 99836 */ GIR_EraseRootFromParent_Done,
35562 /* 99837 */ // Label 1837: @99837
35563 /* 99837 */ GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(99880), // Rule ID 342 //
35564 /* 99842 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb),
35565 /* 99845 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
35566 /* 99850 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35567 /* 99853 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35568 /* 99857 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35569 /* 99861 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255),
35570 /* 99865 */ // MIs[1] Operand 1
35571 /* 99865 */ // No operand predicates
35572 /* 99865 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35573 /* 99867 */ // (intrinsic_void 4171:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_255>>:$imm8) => (tUDF (imm:{ *:[i32] }):$imm8)
35574 /* 99867 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF),
35575 /* 99870 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm8
35576 /* 99873 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35577 /* 99878 */ GIR_RootConstrainSelectedInstOperands,
35578 /* 99879 */ // GIR_Coverage, 342,
35579 /* 99879 */ GIR_EraseRootFromParent_Done,
35580 /* 99880 */ // Label 1838: @99880
35581 /* 99880 */ GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(99923), // Rule ID 493 //
35582 /* 99885 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
35583 /* 99888 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_undefined),
35584 /* 99893 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35585 /* 99896 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35586 /* 99900 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35587 /* 99904 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
35588 /* 99908 */ // MIs[1] Operand 1
35589 /* 99908 */ // No operand predicates
35590 /* 99908 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35591 /* 99910 */ // (intrinsic_void 4171:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm16) => (t2UDF (imm:{ *:[i32] }):$imm16)
35592 /* 99910 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UDF),
35593 /* 99913 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm16
35594 /* 99916 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35595 /* 99921 */ GIR_RootConstrainSelectedInstOperands,
35596 /* 99922 */ // GIR_Coverage, 493,
35597 /* 99922 */ GIR_EraseRootFromParent_Done,
35598 /* 99923 */ // Label 1839: @99923
35599 /* 99923 */ GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(99975), // Rule ID 558 //
35600 /* 99928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb),
35601 /* 99931 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dmb),
35602 /* 99936 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35603 /* 99939 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35604 /* 99943 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35605 /* 99947 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35606 /* 99951 */ // MIs[1] Operand 1
35607 /* 99951 */ // No operand predicates
35608 /* 99951 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35609 /* 99953 */ // (intrinsic_void 3731:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DMB (imm:{ *:[i32] }):$opt)
35610 /* 99953 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DMB),
35611 /* 99956 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35612 /* 99959 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35613 /* 99962 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35614 /* 99968 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35615 /* 99973 */ GIR_RootConstrainSelectedInstOperands,
35616 /* 99974 */ // GIR_Coverage, 558,
35617 /* 99974 */ GIR_EraseRootFromParent_Done,
35618 /* 99975 */ // Label 1840: @99975
35619 /* 99975 */ GIM_Try, /*On fail goto*//*Label 1841*/ GIMT_Encode4(100027), // Rule ID 559 //
35620 /* 99980 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb),
35621 /* 99983 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dsb),
35622 /* 99988 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35623 /* 99991 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35624 /* 99995 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35625 /* 99999 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35626 /* 100003 */ // MIs[1] Operand 1
35627 /* 100003 */ // No operand predicates
35628 /* 100003 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35629 /* 100005 */ // (intrinsic_void 3732:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DSB (imm:{ *:[i32] }):$opt)
35630 /* 100005 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DSB),
35631 /* 100008 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35632 /* 100011 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35633 /* 100014 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35634 /* 100020 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35635 /* 100025 */ GIR_RootConstrainSelectedInstOperands,
35636 /* 100026 */ // GIR_Coverage, 559,
35637 /* 100026 */ GIR_EraseRootFromParent_Done,
35638 /* 100027 */ // Label 1841: @100027
35639 /* 100027 */ GIM_Try, /*On fail goto*//*Label 1842*/ GIMT_Encode4(100079), // Rule ID 560 //
35640 /* 100032 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDB_IsThumb),
35641 /* 100035 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_isb),
35642 /* 100040 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35643 /* 100043 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35644 /* 100047 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35645 /* 100051 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35646 /* 100055 */ // MIs[1] Operand 1
35647 /* 100055 */ // No operand predicates
35648 /* 100055 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35649 /* 100057 */ // (intrinsic_void 3736:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2ISB (imm:{ *:[i32] }):$opt)
35650 /* 100057 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ISB),
35651 /* 100060 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35652 /* 100063 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35653 /* 100066 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35654 /* 100072 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35655 /* 100077 */ GIR_RootConstrainSelectedInstOperands,
35656 /* 100078 */ // GIR_Coverage, 560,
35657 /* 100078 */ GIR_EraseRootFromParent_Done,
35658 /* 100079 */ // Label 1842: @100079
35659 /* 100079 */ GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(100131), // Rule ID 578 //
35660 /* 100084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
35661 /* 100087 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_hint),
35662 /* 100092 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35663 /* 100095 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35664 /* 100099 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35665 /* 100103 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_239),
35666 /* 100107 */ // MIs[1] Operand 1
35667 /* 100107 */ // No operand predicates
35668 /* 100107 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35669 /* 100109 */ // (intrinsic_void 3735:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_239>>:$imm) => (t2HINT (imm:{ *:[i32] }):$imm)
35670 /* 100109 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2HINT),
35671 /* 100112 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
35672 /* 100115 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35673 /* 100118 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35674 /* 100124 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35675 /* 100129 */ GIR_RootConstrainSelectedInstOperands,
35676 /* 100130 */ // GIR_Coverage, 578,
35677 /* 100130 */ GIR_EraseRootFromParent_Done,
35678 /* 100131 */ // Label 1843: @100131
35679 /* 100131 */ GIM_Try, /*On fail goto*//*Label 1844*/ GIMT_Encode4(100183), // Rule ID 579 //
35680 /* 100136 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
35681 /* 100139 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_dbg),
35682 /* 100144 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35683 /* 100147 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
35684 /* 100151 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35685 /* 100155 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_15),
35686 /* 100159 */ // MIs[1] Operand 1
35687 /* 100159 */ // No operand predicates
35688 /* 100159 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35689 /* 100161 */ // (intrinsic_void 3730:{ *:[iPTR] }, (imm:{ *:[i32] })<<P:Predicate_imm0_15>>:$opt) => (t2DBG (imm:{ *:[i32] }):$opt)
35690 /* 100161 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DBG),
35691 /* 100164 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // opt
35692 /* 100167 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35693 /* 100170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35694 /* 100176 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35695 /* 100181 */ GIR_RootConstrainSelectedInstOperands,
35696 /* 100182 */ // GIR_Coverage, 579,
35697 /* 100182 */ GIR_EraseRootFromParent_Done,
35698 /* 100183 */ // Label 1844: @100183
35699 /* 100183 */ GIM_Try, /*On fail goto*//*Label 1845*/ GIMT_Encode4(100223), // Rule ID 844 //
35700 /* 100188 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs),
35701 /* 100191 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_get_fpscr),
35702 /* 100196 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35703 /* 100199 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35704 /* 100203 */ // (intrinsic_w_chain:{ *:[i32] } 3733:{ *:[iPTR] }) => (VMRS:{ *:[i32] })
35705 /* 100203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS),
35706 /* 100206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
35707 /* 100208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35708 /* 100211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35709 /* 100217 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35710 /* 100221 */ GIR_RootConstrainSelectedInstOperands,
35711 /* 100222 */ // GIR_Coverage, 844,
35712 /* 100222 */ GIR_EraseRootFromParent_Done,
35713 /* 100223 */ // Label 1845: @100223
35714 /* 100223 */ GIM_Try, /*On fail goto*//*Label 1846*/ GIMT_Encode4(100266), // Rule ID 845 //
35715 /* 100228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs),
35716 /* 100231 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_set_fpscr),
35717 /* 100236 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
35718 /* 100239 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35719 /* 100243 */ // (intrinsic_void 4115:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt)
35720 /* 100243 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
35721 /* 100246 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rt
35722 /* 100248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35723 /* 100251 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35724 /* 100257 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
35725 /* 100260 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35726 /* 100264 */ GIR_RootConstrainSelectedInstOperands,
35727 /* 100265 */ // GIR_Coverage, 845,
35728 /* 100265 */ GIR_EraseRootFromParent_Done,
35729 /* 100266 */ // Label 1846: @100266
35730 /* 100266 */ GIM_Reject,
35731 /* 100267 */ // Label 1829: @100267
35732 /* 100267 */ GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(100310), // Rule ID 603 //
35733 /* 100272 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLOB_HasV8_1MMainline_IsThumb2),
35734 /* 100275 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/3,
35735 /* 100278 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::start_loop_iterations),
35736 /* 100283 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35737 /* 100286 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35738 /* 100289 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRlrRegClassID),
35739 /* 100293 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
35740 /* 100297 */ // (intrinsic_w_chain:{ *:[i32] } 359:{ *:[iPTR] }, rGPR:{ *:[i32] }:$tc) => (t2DoLoopStart:{ *:[i32] } rGPR:{ *:[i32] }:$tc)
35741 /* 100297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2DoLoopStart),
35742 /* 100300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[X]
35743 /* 100302 */ GIR_RootToRootCopy, /*OpIdx*/2, // tc
35744 /* 100304 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35745 /* 100308 */ GIR_RootConstrainSelectedInstOperands,
35746 /* 100309 */ // GIR_Coverage, 603,
35747 /* 100309 */ GIR_EraseRootFromParent_Done,
35748 /* 100310 */ // Label 1847: @100310
35749 /* 100310 */ GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(102301),
35750 /* 100315 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
35751 /* 100318 */ GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(100372), // Rule ID 5529 //
35752 /* 100323 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base),
35753 /* 100328 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
35754 /* 100331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
35755 /* 100334 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35756 /* 100337 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35757 /* 100341 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35758 /* 100345 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35759 /* 100349 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35760 /* 100353 */ // MIs[1] Operand 1
35761 /* 100353 */ // No operand predicates
35762 /* 100353 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35763 /* 100355 */ // (intrinsic_w_chain:{ *:[v4i32] } 3876:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35764 /* 100355 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi),
35765 /* 100358 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35766 /* 100360 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
35767 /* 100362 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35768 /* 100365 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35769 /* 100370 */ GIR_RootConstrainSelectedInstOperands,
35770 /* 100371 */ // GIR_Coverage, 5529,
35771 /* 100371 */ GIR_EraseRootFromParent_Done,
35772 /* 100372 */ // Label 1849: @100372
35773 /* 100372 */ GIM_Try, /*On fail goto*//*Label 1850*/ GIMT_Encode4(100426), // Rule ID 5535 //
35774 /* 100377 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base),
35775 /* 100382 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
35776 /* 100385 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
35777 /* 100388 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35778 /* 100391 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35779 /* 100395 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35780 /* 100399 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35781 /* 100403 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35782 /* 100407 */ // MIs[1] Operand 1
35783 /* 100407 */ // No operand predicates
35784 /* 100407 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35785 /* 100409 */ // (intrinsic_w_chain:{ *:[v4f32] } 3876:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRWU32_qi:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35786 /* 100409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_qi),
35787 /* 100412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35788 /* 100414 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
35789 /* 100416 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35790 /* 100419 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35791 /* 100424 */ GIR_RootConstrainSelectedInstOperands,
35792 /* 100425 */ // GIR_Coverage, 5535,
35793 /* 100425 */ GIR_EraseRootFromParent_Done,
35794 /* 100426 */ // Label 1850: @100426
35795 /* 100426 */ GIM_Try, /*On fail goto*//*Label 1851*/ GIMT_Encode4(100480), // Rule ID 5537 //
35796 /* 100431 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base),
35797 /* 100436 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
35798 /* 100439 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
35799 /* 100442 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35800 /* 100445 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35801 /* 100449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35802 /* 100453 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35803 /* 100457 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35804 /* 100461 */ // MIs[1] Operand 1
35805 /* 100461 */ // No operand predicates
35806 /* 100461 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35807 /* 100463 */ // (intrinsic_w_chain:{ *:[v2i64] } 3876:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35808 /* 100463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi),
35809 /* 100466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35810 /* 100468 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
35811 /* 100470 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35812 /* 100473 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35813 /* 100478 */ GIR_RootConstrainSelectedInstOperands,
35814 /* 100479 */ // GIR_Coverage, 5537,
35815 /* 100479 */ GIR_EraseRootFromParent_Done,
35816 /* 100480 */ // Label 1851: @100480
35817 /* 100480 */ GIM_Try, /*On fail goto*//*Label 1852*/ GIMT_Encode4(100534), // Rule ID 5539 //
35818 /* 100485 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_base),
35819 /* 100490 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
35820 /* 100493 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
35821 /* 100496 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35822 /* 100499 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35823 /* 100503 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35824 /* 100507 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
35825 /* 100511 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35826 /* 100515 */ // MIs[1] Operand 1
35827 /* 100515 */ // No operand predicates
35828 /* 100515 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35829 /* 100517 */ // (intrinsic_w_chain:{ *:[v2f64] } 3876:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset) => (MVE_VLDRDU64_qi:{ *:[v2f64] } MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35830 /* 100517 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_qi),
35831 /* 100520 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
35832 /* 100522 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
35833 /* 100524 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35834 /* 100527 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35835 /* 100532 */ GIR_RootConstrainSelectedInstOperands,
35836 /* 100533 */ // GIR_Coverage, 5539,
35837 /* 100533 */ GIR_EraseRootFromParent_Done,
35838 /* 100534 */ // Label 1852: @100534
35839 /* 100534 */ GIM_Try, /*On fail goto*//*Label 1853*/ GIMT_Encode4(100576), // Rule ID 1902 //
35840 /* 100539 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_space),
35841 /* 100544 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35842 /* 100547 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35843 /* 100550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35844 /* 100554 */ // MIs[0] size
35845 /* 100554 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
35846 /* 100557 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35847 /* 100561 */ // (intrinsic_w_chain:{ *:[i32] } 4146:{ *:[iPTR] }, (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn) => (SPACE:{ *:[i32] } (timm:{ *:[i32] }):$size, GPR:{ *:[i32] }:$Rn)
35848 /* 100561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SPACE),
35849 /* 100564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35850 /* 100566 */ GIR_RootToRootCopy, /*OpIdx*/2, // size
35851 /* 100568 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rn
35852 /* 100570 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35853 /* 100574 */ GIR_RootConstrainSelectedInstOperands,
35854 /* 100575 */ // GIR_Coverage, 1902,
35855 /* 100575 */ GIR_EraseRootFromParent_Done,
35856 /* 100576 */ // Label 1853: @100576
35857 /* 100576 */ GIM_Try, /*On fail goto*//*Label 1854*/ GIMT_Encode4(100630), // Rule ID 5531 //
35858 /* 100581 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base),
35859 /* 100586 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
35860 /* 100589 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35861 /* 100592 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
35862 /* 100595 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35863 /* 100599 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35864 /* 100603 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35865 /* 100607 */ // MIs[1] Operand 1
35866 /* 100607 */ // No operand predicates
35867 /* 100607 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35868 /* 100611 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35869 /* 100613 */ // (intrinsic_void 3958:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35870 /* 100613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi),
35871 /* 100616 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
35872 /* 100618 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
35873 /* 100620 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35874 /* 100623 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35875 /* 100628 */ GIR_RootConstrainSelectedInstOperands,
35876 /* 100629 */ // GIR_Coverage, 5531,
35877 /* 100629 */ GIR_EraseRootFromParent_Done,
35878 /* 100630 */ // Label 1854: @100630
35879 /* 100630 */ GIM_Try, /*On fail goto*//*Label 1855*/ GIMT_Encode4(100684), // Rule ID 5541 //
35880 /* 100635 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base),
35881 /* 100640 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
35882 /* 100643 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35883 /* 100646 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
35884 /* 100649 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35885 /* 100653 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35886 /* 100657 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35887 /* 100661 */ // MIs[1] Operand 1
35888 /* 100661 */ // No operand predicates
35889 /* 100661 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35890 /* 100665 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35891 /* 100667 */ // (intrinsic_void 3958:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
35892 /* 100667 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi),
35893 /* 100670 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
35894 /* 100672 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
35895 /* 100674 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35896 /* 100677 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35897 /* 100682 */ GIR_RootConstrainSelectedInstOperands,
35898 /* 100683 */ // GIR_Coverage, 5541,
35899 /* 100683 */ GIR_EraseRootFromParent_Done,
35900 /* 100684 */ // Label 1855: @100684
35901 /* 100684 */ GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(100738), // Rule ID 5545 //
35902 /* 100689 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base),
35903 /* 100694 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
35904 /* 100697 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35905 /* 100700 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
35906 /* 100703 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35907 /* 100707 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35908 /* 100711 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35909 /* 100715 */ // MIs[1] Operand 1
35910 /* 100715 */ // No operand predicates
35911 /* 100715 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35912 /* 100719 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35913 /* 100721 */ // (intrinsic_void 3958:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35914 /* 100721 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi),
35915 /* 100724 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
35916 /* 100726 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
35917 /* 100728 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35918 /* 100731 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35919 /* 100736 */ GIR_RootConstrainSelectedInstOperands,
35920 /* 100737 */ // GIR_Coverage, 5545,
35921 /* 100737 */ GIR_EraseRootFromParent_Done,
35922 /* 100738 */ // Label 1856: @100738
35923 /* 100738 */ GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(100792), // Rule ID 5549 //
35924 /* 100743 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base),
35925 /* 100748 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
35926 /* 100751 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35927 /* 100754 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
35928 /* 100757 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35929 /* 100761 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
35930 /* 100765 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
35931 /* 100769 */ // MIs[1] Operand 1
35932 /* 100769 */ // No operand predicates
35933 /* 100769 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
35934 /* 100773 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
35935 /* 100775 */ // (intrinsic_void 3958:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
35936 /* 100775 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi),
35937 /* 100778 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
35938 /* 100780 */ GIR_RootToRootCopy, /*OpIdx*/1, // addr
35939 /* 100782 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
35940 /* 100785 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
35941 /* 100790 */ GIR_RootConstrainSelectedInstOperands,
35942 /* 100791 */ // GIR_Coverage, 5549,
35943 /* 100791 */ GIR_EraseRootFromParent_Done,
35944 /* 100792 */ // Label 1857: @100792
35945 /* 100792 */ GIM_Try, /*On fail goto*//*Label 1858*/ GIMT_Encode4(100850), // Rule ID 3 //
35946 /* 100797 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
35947 /* 100800 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel),
35948 /* 100805 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35949 /* 100808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35950 /* 100811 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35951 /* 100814 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35952 /* 100818 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35953 /* 100822 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
35954 /* 100826 */ // (intrinsic_w_chain:{ *:[i32] } 4114:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
35955 /* 100826 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SEL),
35956 /* 100829 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35957 /* 100831 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35958 /* 100833 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35959 /* 100835 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35960 /* 100838 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35961 /* 100844 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35962 /* 100848 */ GIR_RootConstrainSelectedInstOperands,
35963 /* 100849 */ // GIR_Coverage, 3,
35964 /* 100849 */ GIR_EraseRootFromParent_Done,
35965 /* 100850 */ // Label 1858: @100850
35966 /* 100850 */ GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(100908), // Rule ID 120 //
35967 /* 100855 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35968 /* 100858 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx),
35969 /* 100863 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35970 /* 100866 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35971 /* 100869 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35972 /* 100872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35973 /* 100876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35974 /* 100880 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35975 /* 100884 */ // (intrinsic_w_chain:{ *:[i32] } 4113:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35976 /* 100884 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SASX),
35977 /* 100887 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35978 /* 100889 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
35979 /* 100891 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
35980 /* 100893 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
35981 /* 100896 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
35982 /* 100902 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
35983 /* 100906 */ GIR_RootConstrainSelectedInstOperands,
35984 /* 100907 */ // GIR_Coverage, 120,
35985 /* 100907 */ GIR_EraseRootFromParent_Done,
35986 /* 100908 */ // Label 1859: @100908
35987 /* 100908 */ GIM_Try, /*On fail goto*//*Label 1860*/ GIMT_Encode4(100966), // Rule ID 121 //
35988 /* 100913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
35989 /* 100916 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16),
35990 /* 100921 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
35991 /* 100924 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
35992 /* 100927 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
35993 /* 100930 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35994 /* 100934 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35995 /* 100938 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
35996 /* 100942 */ // (intrinsic_w_chain:{ *:[i32] } 4111:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
35997 /* 100942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD16),
35998 /* 100945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
35999 /* 100947 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36000 /* 100949 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36001 /* 100951 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36002 /* 100954 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36003 /* 100960 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36004 /* 100964 */ GIR_RootConstrainSelectedInstOperands,
36005 /* 100965 */ // GIR_Coverage, 121,
36006 /* 100965 */ GIR_EraseRootFromParent_Done,
36007 /* 100966 */ // Label 1860: @100966
36008 /* 100966 */ GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(101024), // Rule ID 122 //
36009 /* 100971 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
36010 /* 100974 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8),
36011 /* 100979 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36012 /* 100982 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36013 /* 100985 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36014 /* 100988 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36015 /* 100992 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36016 /* 100996 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36017 /* 101000 */ // (intrinsic_w_chain:{ *:[i32] } 4112:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
36018 /* 101000 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SADD8),
36019 /* 101003 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36020 /* 101005 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36021 /* 101007 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36022 /* 101009 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36023 /* 101012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36024 /* 101018 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36025 /* 101022 */ GIR_RootConstrainSelectedInstOperands,
36026 /* 101023 */ // GIR_Coverage, 122,
36027 /* 101023 */ GIR_EraseRootFromParent_Done,
36028 /* 101024 */ // Label 1861: @101024
36029 /* 101024 */ GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(101082), // Rule ID 123 //
36030 /* 101029 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
36031 /* 101032 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax),
36032 /* 101037 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36033 /* 101040 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36034 /* 101043 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36035 /* 101046 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36036 /* 101050 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36037 /* 101054 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36038 /* 101058 */ // (intrinsic_w_chain:{ *:[i32] } 4149:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
36039 /* 101058 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSAX),
36040 /* 101061 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36041 /* 101063 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36042 /* 101065 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36043 /* 101067 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36044 /* 101070 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36045 /* 101076 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36046 /* 101080 */ GIR_RootConstrainSelectedInstOperands,
36047 /* 101081 */ // GIR_Coverage, 123,
36048 /* 101081 */ GIR_EraseRootFromParent_Done,
36049 /* 101082 */ // Label 1862: @101082
36050 /* 101082 */ GIM_Try, /*On fail goto*//*Label 1863*/ GIMT_Encode4(101140), // Rule ID 124 //
36051 /* 101087 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
36052 /* 101090 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16),
36053 /* 101095 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36054 /* 101098 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36055 /* 101101 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36056 /* 101104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36057 /* 101108 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36058 /* 101112 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36059 /* 101116 */ // (intrinsic_w_chain:{ *:[i32] } 4150:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
36060 /* 101116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB16),
36061 /* 101119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36062 /* 101121 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36063 /* 101123 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36064 /* 101125 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36065 /* 101128 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36066 /* 101134 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36067 /* 101138 */ GIR_RootConstrainSelectedInstOperands,
36068 /* 101139 */ // GIR_Coverage, 124,
36069 /* 101139 */ GIR_EraseRootFromParent_Done,
36070 /* 101140 */ // Label 1863: @101140
36071 /* 101140 */ GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(101198), // Rule ID 125 //
36072 /* 101145 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
36073 /* 101148 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8),
36074 /* 101153 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36075 /* 101156 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36076 /* 101159 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36077 /* 101162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36078 /* 101166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36079 /* 101170 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36080 /* 101174 */ // (intrinsic_w_chain:{ *:[i32] } 4151:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (SSUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
36081 /* 101174 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SSUB8),
36082 /* 101177 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36083 /* 101179 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36084 /* 101181 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36085 /* 101183 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36086 /* 101186 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36087 /* 101192 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36088 /* 101196 */ GIR_RootConstrainSelectedInstOperands,
36089 /* 101197 */ // GIR_Coverage, 125,
36090 /* 101197 */ GIR_EraseRootFromParent_Done,
36091 /* 101198 */ // Label 1864: @101198
36092 /* 101198 */ GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(101256), // Rule ID 126 //
36093 /* 101203 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
36094 /* 101206 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx),
36095 /* 101211 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36096 /* 101214 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36097 /* 101217 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36098 /* 101220 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36099 /* 101224 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36100 /* 101228 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36101 /* 101232 */ // (intrinsic_w_chain:{ *:[i32] } 4164:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UASX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
36102 /* 101232 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UASX),
36103 /* 101235 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36104 /* 101237 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36105 /* 101239 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36106 /* 101241 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36107 /* 101244 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36108 /* 101250 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36109 /* 101254 */ GIR_RootConstrainSelectedInstOperands,
36110 /* 101255 */ // GIR_Coverage, 126,
36111 /* 101255 */ GIR_EraseRootFromParent_Done,
36112 /* 101256 */ // Label 1865: @101256
36113 /* 101256 */ GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(101314), // Rule ID 127 //
36114 /* 101261 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
36115 /* 101264 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16),
36116 /* 101269 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36117 /* 101272 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36118 /* 101275 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36119 /* 101278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36120 /* 101282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36121 /* 101286 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36122 /* 101290 */ // (intrinsic_w_chain:{ *:[i32] } 4162:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
36123 /* 101290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD16),
36124 /* 101293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36125 /* 101295 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36126 /* 101297 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36127 /* 101299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36128 /* 101302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36129 /* 101308 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36130 /* 101312 */ GIR_RootConstrainSelectedInstOperands,
36131 /* 101313 */ // GIR_Coverage, 127,
36132 /* 101313 */ GIR_EraseRootFromParent_Done,
36133 /* 101314 */ // Label 1866: @101314
36134 /* 101314 */ GIM_Try, /*On fail goto*//*Label 1867*/ GIMT_Encode4(101372), // Rule ID 128 //
36135 /* 101319 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
36136 /* 101322 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8),
36137 /* 101327 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36138 /* 101330 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36139 /* 101333 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36140 /* 101336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36141 /* 101340 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36142 /* 101344 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36143 /* 101348 */ // (intrinsic_w_chain:{ *:[i32] } 4163:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (UADD8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
36144 /* 101348 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UADD8),
36145 /* 101351 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36146 /* 101353 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36147 /* 101355 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36148 /* 101357 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36149 /* 101360 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36150 /* 101366 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36151 /* 101370 */ GIR_RootConstrainSelectedInstOperands,
36152 /* 101371 */ // GIR_Coverage, 128,
36153 /* 101371 */ GIR_EraseRootFromParent_Done,
36154 /* 101372 */ // Label 1867: @101372
36155 /* 101372 */ GIM_Try, /*On fail goto*//*Label 1868*/ GIMT_Encode4(101430), // Rule ID 129 //
36156 /* 101377 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
36157 /* 101380 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax),
36158 /* 101385 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36159 /* 101388 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36160 /* 101391 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36161 /* 101394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36162 /* 101398 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36163 /* 101402 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36164 /* 101406 */ // (intrinsic_w_chain:{ *:[i32] } 4182:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USAX:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
36165 /* 101406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USAX),
36166 /* 101409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36167 /* 101411 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36168 /* 101413 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36169 /* 101415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36170 /* 101418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36171 /* 101424 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36172 /* 101428 */ GIR_RootConstrainSelectedInstOperands,
36173 /* 101429 */ // GIR_Coverage, 129,
36174 /* 101429 */ GIR_EraseRootFromParent_Done,
36175 /* 101430 */ // Label 1868: @101430
36176 /* 101430 */ GIM_Try, /*On fail goto*//*Label 1869*/ GIMT_Encode4(101488), // Rule ID 130 //
36177 /* 101435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
36178 /* 101438 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16),
36179 /* 101443 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36180 /* 101446 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36181 /* 101449 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36182 /* 101452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36183 /* 101456 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36184 /* 101460 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36185 /* 101464 */ // (intrinsic_w_chain:{ *:[i32] } 4183:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB16:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
36186 /* 101464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB16),
36187 /* 101467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36188 /* 101469 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36189 /* 101471 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36190 /* 101473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36191 /* 101476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36192 /* 101482 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36193 /* 101486 */ GIR_RootConstrainSelectedInstOperands,
36194 /* 101487 */ // GIR_Coverage, 130,
36195 /* 101487 */ GIR_EraseRootFromParent_Done,
36196 /* 101488 */ // Label 1869: @101488
36197 /* 101488 */ GIM_Try, /*On fail goto*//*Label 1870*/ GIMT_Encode4(101546), // Rule ID 131 //
36198 /* 101493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
36199 /* 101496 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8),
36200 /* 101501 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36201 /* 101504 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36202 /* 101507 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36203 /* 101510 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36204 /* 101514 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36205 /* 101518 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36206 /* 101522 */ // (intrinsic_w_chain:{ *:[i32] } 4184:{ *:[iPTR] }, GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm) => (USUB8:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rn, GPRnopc:{ *:[i32] }:$Rm)
36207 /* 101522 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::USUB8),
36208 /* 101525 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36209 /* 101527 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36210 /* 101529 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36211 /* 101531 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36212 /* 101534 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36213 /* 101540 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36214 /* 101544 */ GIR_RootConstrainSelectedInstOperands,
36215 /* 101545 */ // GIR_Coverage, 131,
36216 /* 101545 */ GIR_EraseRootFromParent_Done,
36217 /* 101546 */ // Label 1870: @101546
36218 /* 101546 */ GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(101604), // Rule ID 430 //
36219 /* 101551 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36220 /* 101554 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sel),
36221 /* 101559 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36222 /* 101562 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36223 /* 101565 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36224 /* 101568 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36225 /* 101572 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36226 /* 101576 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36227 /* 101580 */ // (intrinsic_w_chain:{ *:[i32] } 4114:{ *:[iPTR] }, GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (t2SEL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
36228 /* 101580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SEL),
36229 /* 101583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36230 /* 101585 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36231 /* 101587 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36232 /* 101589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36233 /* 101592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36234 /* 101598 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36235 /* 101602 */ GIR_RootConstrainSelectedInstOperands,
36236 /* 101603 */ // GIR_Coverage, 430,
36237 /* 101603 */ GIR_EraseRootFromParent_Done,
36238 /* 101604 */ // Label 1871: @101604
36239 /* 101604 */ GIM_Try, /*On fail goto*//*Label 1872*/ GIMT_Encode4(101662), // Rule ID 443 //
36240 /* 101609 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36241 /* 101612 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sasx),
36242 /* 101617 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36243 /* 101620 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36244 /* 101623 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36245 /* 101626 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36246 /* 101630 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36247 /* 101634 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36248 /* 101638 */ // (intrinsic_w_chain:{ *:[i32] } 4113:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36249 /* 101638 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SASX),
36250 /* 101641 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36251 /* 101643 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36252 /* 101645 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36253 /* 101647 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36254 /* 101650 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36255 /* 101656 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36256 /* 101660 */ GIR_RootConstrainSelectedInstOperands,
36257 /* 101661 */ // GIR_Coverage, 443,
36258 /* 101661 */ GIR_EraseRootFromParent_Done,
36259 /* 101662 */ // Label 1872: @101662
36260 /* 101662 */ GIM_Try, /*On fail goto*//*Label 1873*/ GIMT_Encode4(101720), // Rule ID 444 //
36261 /* 101667 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36262 /* 101670 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd16),
36263 /* 101675 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36264 /* 101678 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36265 /* 101681 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36266 /* 101684 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36267 /* 101688 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36268 /* 101692 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36269 /* 101696 */ // (intrinsic_w_chain:{ *:[i32] } 4111:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36270 /* 101696 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD16),
36271 /* 101699 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36272 /* 101701 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36273 /* 101703 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36274 /* 101705 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36275 /* 101708 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36276 /* 101714 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36277 /* 101718 */ GIR_RootConstrainSelectedInstOperands,
36278 /* 101719 */ // GIR_Coverage, 444,
36279 /* 101719 */ GIR_EraseRootFromParent_Done,
36280 /* 101720 */ // Label 1873: @101720
36281 /* 101720 */ GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(101778), // Rule ID 445 //
36282 /* 101725 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36283 /* 101728 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_sadd8),
36284 /* 101733 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36285 /* 101736 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36286 /* 101739 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36287 /* 101742 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36288 /* 101746 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36289 /* 101750 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36290 /* 101754 */ // (intrinsic_w_chain:{ *:[i32] } 4112:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36291 /* 101754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SADD8),
36292 /* 101757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36293 /* 101759 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36294 /* 101761 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36295 /* 101763 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36296 /* 101766 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36297 /* 101772 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36298 /* 101776 */ GIR_RootConstrainSelectedInstOperands,
36299 /* 101777 */ // GIR_Coverage, 445,
36300 /* 101777 */ GIR_EraseRootFromParent_Done,
36301 /* 101778 */ // Label 1874: @101778
36302 /* 101778 */ GIM_Try, /*On fail goto*//*Label 1875*/ GIMT_Encode4(101836), // Rule ID 446 //
36303 /* 101783 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36304 /* 101786 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssax),
36305 /* 101791 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36306 /* 101794 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36307 /* 101797 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36308 /* 101800 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36309 /* 101804 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36310 /* 101808 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36311 /* 101812 */ // (intrinsic_w_chain:{ *:[i32] } 4149:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36312 /* 101812 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSAX),
36313 /* 101815 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36314 /* 101817 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36315 /* 101819 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36316 /* 101821 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36317 /* 101824 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36318 /* 101830 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36319 /* 101834 */ GIR_RootConstrainSelectedInstOperands,
36320 /* 101835 */ // GIR_Coverage, 446,
36321 /* 101835 */ GIR_EraseRootFromParent_Done,
36322 /* 101836 */ // Label 1875: @101836
36323 /* 101836 */ GIM_Try, /*On fail goto*//*Label 1876*/ GIMT_Encode4(101894), // Rule ID 447 //
36324 /* 101841 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36325 /* 101844 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub16),
36326 /* 101849 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36327 /* 101852 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36328 /* 101855 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36329 /* 101858 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36330 /* 101862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36331 /* 101866 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36332 /* 101870 */ // (intrinsic_w_chain:{ *:[i32] } 4150:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36333 /* 101870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB16),
36334 /* 101873 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36335 /* 101875 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36336 /* 101877 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36337 /* 101879 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36338 /* 101882 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36339 /* 101888 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36340 /* 101892 */ GIR_RootConstrainSelectedInstOperands,
36341 /* 101893 */ // GIR_Coverage, 447,
36342 /* 101893 */ GIR_EraseRootFromParent_Done,
36343 /* 101894 */ // Label 1876: @101894
36344 /* 101894 */ GIM_Try, /*On fail goto*//*Label 1877*/ GIMT_Encode4(101952), // Rule ID 448 //
36345 /* 101899 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36346 /* 101902 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_ssub8),
36347 /* 101907 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36348 /* 101910 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36349 /* 101913 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36350 /* 101916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36351 /* 101920 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36352 /* 101924 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36353 /* 101928 */ // (intrinsic_w_chain:{ *:[i32] } 4151:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SSUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36354 /* 101928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SSUB8),
36355 /* 101931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36356 /* 101933 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36357 /* 101935 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36358 /* 101937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36359 /* 101940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36360 /* 101946 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36361 /* 101950 */ GIR_RootConstrainSelectedInstOperands,
36362 /* 101951 */ // GIR_Coverage, 448,
36363 /* 101951 */ GIR_EraseRootFromParent_Done,
36364 /* 101952 */ // Label 1877: @101952
36365 /* 101952 */ GIM_Try, /*On fail goto*//*Label 1878*/ GIMT_Encode4(102010), // Rule ID 449 //
36366 /* 101957 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36367 /* 101960 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uasx),
36368 /* 101965 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36369 /* 101968 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36370 /* 101971 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36371 /* 101974 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36372 /* 101978 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36373 /* 101982 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36374 /* 101986 */ // (intrinsic_w_chain:{ *:[i32] } 4164:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UASX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36375 /* 101986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UASX),
36376 /* 101989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36377 /* 101991 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36378 /* 101993 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36379 /* 101995 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36380 /* 101998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36381 /* 102004 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36382 /* 102008 */ GIR_RootConstrainSelectedInstOperands,
36383 /* 102009 */ // GIR_Coverage, 449,
36384 /* 102009 */ GIR_EraseRootFromParent_Done,
36385 /* 102010 */ // Label 1878: @102010
36386 /* 102010 */ GIM_Try, /*On fail goto*//*Label 1879*/ GIMT_Encode4(102068), // Rule ID 450 //
36387 /* 102015 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36388 /* 102018 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd16),
36389 /* 102023 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36390 /* 102026 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36391 /* 102029 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36392 /* 102032 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36393 /* 102036 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36394 /* 102040 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36395 /* 102044 */ // (intrinsic_w_chain:{ *:[i32] } 4162:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36396 /* 102044 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD16),
36397 /* 102047 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36398 /* 102049 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36399 /* 102051 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36400 /* 102053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36401 /* 102056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36402 /* 102062 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36403 /* 102066 */ GIR_RootConstrainSelectedInstOperands,
36404 /* 102067 */ // GIR_Coverage, 450,
36405 /* 102067 */ GIR_EraseRootFromParent_Done,
36406 /* 102068 */ // Label 1879: @102068
36407 /* 102068 */ GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(102126), // Rule ID 451 //
36408 /* 102073 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36409 /* 102076 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_uadd8),
36410 /* 102081 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36411 /* 102084 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36412 /* 102087 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36413 /* 102090 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36414 /* 102094 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36415 /* 102098 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36416 /* 102102 */ // (intrinsic_w_chain:{ *:[i32] } 4163:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2UADD8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36417 /* 102102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2UADD8),
36418 /* 102105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36419 /* 102107 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36420 /* 102109 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36421 /* 102111 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36422 /* 102114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36423 /* 102120 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36424 /* 102124 */ GIR_RootConstrainSelectedInstOperands,
36425 /* 102125 */ // GIR_Coverage, 451,
36426 /* 102125 */ GIR_EraseRootFromParent_Done,
36427 /* 102126 */ // Label 1880: @102126
36428 /* 102126 */ GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(102184), // Rule ID 452 //
36429 /* 102131 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36430 /* 102134 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usax),
36431 /* 102139 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36432 /* 102142 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36433 /* 102145 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36434 /* 102148 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36435 /* 102152 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36436 /* 102156 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36437 /* 102160 */ // (intrinsic_w_chain:{ *:[i32] } 4182:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USAX:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36438 /* 102160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USAX),
36439 /* 102163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36440 /* 102165 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36441 /* 102167 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36442 /* 102169 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36443 /* 102172 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36444 /* 102178 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36445 /* 102182 */ GIR_RootConstrainSelectedInstOperands,
36446 /* 102183 */ // GIR_Coverage, 452,
36447 /* 102183 */ GIR_EraseRootFromParent_Done,
36448 /* 102184 */ // Label 1881: @102184
36449 /* 102184 */ GIM_Try, /*On fail goto*//*Label 1882*/ GIMT_Encode4(102242), // Rule ID 453 //
36450 /* 102189 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36451 /* 102192 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub16),
36452 /* 102197 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36453 /* 102200 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36454 /* 102203 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36455 /* 102206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36456 /* 102210 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36457 /* 102214 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36458 /* 102218 */ // (intrinsic_w_chain:{ *:[i32] } 4183:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB16:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36459 /* 102218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB16),
36460 /* 102221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36461 /* 102223 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36462 /* 102225 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36463 /* 102227 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36464 /* 102230 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36465 /* 102236 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36466 /* 102240 */ GIR_RootConstrainSelectedInstOperands,
36467 /* 102241 */ // GIR_Coverage, 453,
36468 /* 102241 */ GIR_EraseRootFromParent_Done,
36469 /* 102242 */ // Label 1882: @102242
36470 /* 102242 */ GIM_Try, /*On fail goto*//*Label 1883*/ GIMT_Encode4(102300), // Rule ID 454 //
36471 /* 102247 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
36472 /* 102250 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_usub8),
36473 /* 102255 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
36474 /* 102258 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
36475 /* 102261 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36476 /* 102264 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36477 /* 102268 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36478 /* 102272 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
36479 /* 102276 */ // (intrinsic_w_chain:{ *:[i32] } 4184:{ *:[iPTR] }, rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2USUB8:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
36480 /* 102276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2USUB8),
36481 /* 102279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
36482 /* 102281 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
36483 /* 102283 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rm
36484 /* 102285 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36485 /* 102288 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36486 /* 102294 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36487 /* 102298 */ GIR_RootConstrainSelectedInstOperands,
36488 /* 102299 */ // GIR_Coverage, 454,
36489 /* 102299 */ GIR_EraseRootFromParent_Done,
36490 /* 102300 */ // Label 1883: @102300
36491 /* 102300 */ GIM_Reject,
36492 /* 102301 */ // Label 1848: @102301
36493 /* 102301 */ GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(102547),
36494 /* 102306 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/5,
36495 /* 102309 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_base_wb),
36496 /* 102314 */ GIM_Try, /*On fail goto*//*Label 1885*/ GIMT_Encode4(102372), // Rule ID 5533 //
36497 /* 102319 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
36498 /* 102322 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36499 /* 102325 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36500 /* 102328 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
36501 /* 102331 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36502 /* 102335 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36503 /* 102339 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36504 /* 102343 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36505 /* 102347 */ // MIs[1] Operand 1
36506 /* 102347 */ // No operand predicates
36507 /* 102347 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36508 /* 102351 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36509 /* 102353 */ // (intrinsic_w_chain:{ *:[v4i32] } 3960:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4i32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
36510 /* 102353 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre),
36511 /* 102356 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
36512 /* 102358 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
36513 /* 102360 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
36514 /* 102362 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36515 /* 102365 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
36516 /* 102370 */ GIR_RootConstrainSelectedInstOperands,
36517 /* 102371 */ // GIR_Coverage, 5533,
36518 /* 102371 */ GIR_EraseRootFromParent_Done,
36519 /* 102372 */ // Label 1885: @102372
36520 /* 102372 */ GIM_Try, /*On fail goto*//*Label 1886*/ GIMT_Encode4(102430), // Rule ID 5543 //
36521 /* 102377 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
36522 /* 102380 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36523 /* 102383 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36524 /* 102386 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32,
36525 /* 102389 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36526 /* 102393 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36527 /* 102397 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36528 /* 102401 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36529 /* 102405 */ // MIs[1] Operand 1
36530 /* 102405 */ // No operand predicates
36531 /* 102405 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36532 /* 102409 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36533 /* 102411 */ // (intrinsic_w_chain:{ *:[v4i32] } 3960:{ *:[iPTR] }, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v4f32] }:$data) => (MVE_VSTRW32_qi_pre:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$data, MQPR:{ *:[v4i32] }:$addr, (imm:{ *:[i32] }):$offset)
36534 /* 102411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_qi_pre),
36535 /* 102414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
36536 /* 102416 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
36537 /* 102418 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
36538 /* 102420 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36539 /* 102423 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
36540 /* 102428 */ GIR_RootConstrainSelectedInstOperands,
36541 /* 102429 */ // GIR_Coverage, 5543,
36542 /* 102429 */ GIR_EraseRootFromParent_Done,
36543 /* 102430 */ // Label 1886: @102430
36544 /* 102430 */ GIM_Try, /*On fail goto*//*Label 1887*/ GIMT_Encode4(102488), // Rule ID 5547 //
36545 /* 102435 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
36546 /* 102438 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
36547 /* 102441 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36548 /* 102444 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
36549 /* 102447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36550 /* 102451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36551 /* 102455 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36552 /* 102459 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36553 /* 102463 */ // MIs[1] Operand 1
36554 /* 102463 */ // No operand predicates
36555 /* 102463 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36556 /* 102467 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36557 /* 102469 */ // (intrinsic_w_chain:{ *:[v2i64] } 3960:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2i64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2i64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
36558 /* 102469 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre),
36559 /* 102472 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
36560 /* 102474 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
36561 /* 102476 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
36562 /* 102478 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36563 /* 102481 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
36564 /* 102486 */ GIR_RootConstrainSelectedInstOperands,
36565 /* 102487 */ // GIR_Coverage, 5547,
36566 /* 102487 */ GIR_EraseRootFromParent_Done,
36567 /* 102488 */ // Label 1887: @102488
36568 /* 102488 */ GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(102546), // Rule ID 5551 //
36569 /* 102493 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
36570 /* 102496 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
36571 /* 102499 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36572 /* 102502 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s64,
36573 /* 102505 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36574 /* 102509 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36575 /* 102513 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
36576 /* 102517 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
36577 /* 102521 */ // MIs[1] Operand 1
36578 /* 102521 */ // No operand predicates
36579 /* 102521 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36580 /* 102525 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
36581 /* 102527 */ // (intrinsic_w_chain:{ *:[v2i64] } 3960:{ *:[iPTR] }, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset, MQPR:{ *:[v2f64] }:$data) => (MVE_VSTRD64_qi_pre:{ *:[v2i64] } MQPR:{ *:[v2f64] }:$data, MQPR:{ *:[v2i64] }:$addr, (imm:{ *:[i32] }):$offset)
36582 /* 102527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_qi_pre),
36583 /* 102530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[wb]
36584 /* 102532 */ GIR_RootToRootCopy, /*OpIdx*/4, // data
36585 /* 102534 */ GIR_RootToRootCopy, /*OpIdx*/2, // addr
36586 /* 102536 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // offset
36587 /* 102539 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1,
36588 /* 102544 */ GIR_RootConstrainSelectedInstOperands,
36589 /* 102545 */ // GIR_Coverage, 5551,
36590 /* 102545 */ GIR_EraseRootFromParent_Done,
36591 /* 102546 */ // Label 1888: @102546
36592 /* 102546 */ GIM_Reject,
36593 /* 102547 */ // Label 1884: @102547
36594 /* 102547 */ GIM_Try, /*On fail goto*//*Label 1889*/ GIMT_Encode4(103718),
36595 /* 102552 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/6,
36596 /* 102555 */ GIM_Try, /*On fail goto*//*Label 1890*/ GIMT_Encode4(102616), // Rule ID 5421 //
36597 /* 102560 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36598 /* 102565 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36599 /* 102568 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
36600 /* 102571 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36601 /* 102574 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36602 /* 102577 */ // MIs[0] base
36603 /* 102577 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36604 /* 102581 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36605 /* 102585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36606 /* 102589 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36607 /* 102593 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36608 /* 102597 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36609 /* 102601 */ // (intrinsic_void 3962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36610 /* 102601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u),
36611 /* 102604 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36612 /* 102606 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36613 /* 102608 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36614 /* 102610 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36615 /* 102614 */ GIR_RootConstrainSelectedInstOperands,
36616 /* 102615 */ // GIR_Coverage, 5421,
36617 /* 102615 */ GIR_EraseRootFromParent_Done,
36618 /* 102616 */ // Label 1890: @102616
36619 /* 102616 */ GIM_Try, /*On fail goto*//*Label 1891*/ GIMT_Encode4(102677), // Rule ID 5422 //
36620 /* 102621 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36621 /* 102626 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36622 /* 102629 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
36623 /* 102632 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36624 /* 102635 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36625 /* 102638 */ // MIs[0] base
36626 /* 102638 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36627 /* 102642 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36628 /* 102646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36629 /* 102650 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36630 /* 102654 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36631 /* 102658 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
36632 /* 102662 */ // (intrinsic_void 3962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36633 /* 102662 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq),
36634 /* 102665 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36635 /* 102667 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36636 /* 102669 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36637 /* 102671 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36638 /* 102675 */ GIR_RootConstrainSelectedInstOperands,
36639 /* 102676 */ // GIR_Coverage, 5422,
36640 /* 102676 */ GIR_EraseRootFromParent_Done,
36641 /* 102677 */ // Label 1891: @102677
36642 /* 102677 */ GIM_Try, /*On fail goto*//*Label 1892*/ GIMT_Encode4(102738), // Rule ID 5425 //
36643 /* 102682 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36644 /* 102687 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
36645 /* 102690 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
36646 /* 102693 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36647 /* 102696 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36648 /* 102699 */ // MIs[0] base
36649 /* 102699 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36650 /* 102703 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36651 /* 102707 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36652 /* 102711 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36653 /* 102715 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36654 /* 102719 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36655 /* 102723 */ // (intrinsic_void 3962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, MQPR:{ *:[v16i8] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB8_rq MQPR:{ *:[v16i8] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
36656 /* 102723 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB8_rq),
36657 /* 102726 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36658 /* 102728 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36659 /* 102730 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36660 /* 102732 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36661 /* 102736 */ GIR_RootConstrainSelectedInstOperands,
36662 /* 102737 */ // GIR_Coverage, 5425,
36663 /* 102737 */ GIR_EraseRootFromParent_Done,
36664 /* 102738 */ // Label 1892: @102738
36665 /* 102738 */ GIM_Try, /*On fail goto*//*Label 1893*/ GIMT_Encode4(102799), // Rule ID 5505 //
36666 /* 102743 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36667 /* 102748 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36668 /* 102751 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
36669 /* 102754 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36670 /* 102757 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36671 /* 102760 */ // MIs[0] base
36672 /* 102760 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36673 /* 102764 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36674 /* 102768 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36675 /* 102772 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36676 /* 102776 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36677 /* 102780 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36678 /* 102784 */ // (intrinsic_void 3962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8i16] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB16_rq MQPR:{ *:[v8i16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36679 /* 102784 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB16_rq),
36680 /* 102787 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36681 /* 102789 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36682 /* 102791 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36683 /* 102793 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36684 /* 102797 */ GIR_RootConstrainSelectedInstOperands,
36685 /* 102798 */ // GIR_Coverage, 5505,
36686 /* 102798 */ GIR_EraseRootFromParent_Done,
36687 /* 102799 */ // Label 1893: @102799
36688 /* 102799 */ GIM_Try, /*On fail goto*//*Label 1894*/ GIMT_Encode4(102860), // Rule ID 5507 //
36689 /* 102804 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36690 /* 102809 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36691 /* 102812 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
36692 /* 102815 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36693 /* 102818 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36694 /* 102821 */ // MIs[0] base
36695 /* 102821 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36696 /* 102825 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36697 /* 102829 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36698 /* 102833 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36699 /* 102837 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
36700 /* 102841 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36701 /* 102845 */ // (intrinsic_void 3962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 8:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRB32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36702 /* 102845 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRB32_rq),
36703 /* 102848 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36704 /* 102850 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36705 /* 102852 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36706 /* 102854 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36707 /* 102858 */ GIR_RootConstrainSelectedInstOperands,
36708 /* 102859 */ // GIR_Coverage, 5507,
36709 /* 102859 */ GIR_EraseRootFromParent_Done,
36710 /* 102860 */ // Label 1894: @102860
36711 /* 102860 */ GIM_Try, /*On fail goto*//*Label 1895*/ GIMT_Encode4(102921), // Rule ID 5509 //
36712 /* 102865 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36713 /* 102870 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36714 /* 102873 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
36715 /* 102876 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36716 /* 102879 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36717 /* 102882 */ // MIs[0] base
36718 /* 102882 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36719 /* 102886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36720 /* 102890 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36721 /* 102894 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36722 /* 102898 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36723 /* 102902 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36724 /* 102906 */ // (intrinsic_void 3962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH16_rq_u MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36725 /* 102906 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq_u),
36726 /* 102909 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36727 /* 102911 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36728 /* 102913 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36729 /* 102915 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36730 /* 102919 */ GIR_RootConstrainSelectedInstOperands,
36731 /* 102920 */ // GIR_Coverage, 5509,
36732 /* 102920 */ GIR_EraseRootFromParent_Done,
36733 /* 102921 */ // Label 1895: @102921
36734 /* 102921 */ GIM_Try, /*On fail goto*//*Label 1896*/ GIMT_Encode4(102982), // Rule ID 5510 //
36735 /* 102926 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36736 /* 102931 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
36737 /* 102934 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
36738 /* 102937 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36739 /* 102940 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36740 /* 102943 */ // MIs[0] base
36741 /* 102943 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36742 /* 102947 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36743 /* 102951 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36744 /* 102955 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36745 /* 102959 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36746 /* 102963 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
36747 /* 102967 */ // (intrinsic_void 3962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, MQPR:{ *:[v8f16] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH16_rq MQPR:{ *:[v8f16] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
36748 /* 102967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH16_rq),
36749 /* 102970 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36750 /* 102972 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36751 /* 102974 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36752 /* 102976 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36753 /* 102980 */ GIR_RootConstrainSelectedInstOperands,
36754 /* 102981 */ // GIR_Coverage, 5510,
36755 /* 102981 */ GIR_EraseRootFromParent_Done,
36756 /* 102982 */ // Label 1896: @102982
36757 /* 102982 */ GIM_Try, /*On fail goto*//*Label 1897*/ GIMT_Encode4(103043), // Rule ID 5513 //
36758 /* 102987 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36759 /* 102992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36760 /* 102995 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
36761 /* 102998 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36762 /* 103001 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36763 /* 103004 */ // MIs[0] base
36764 /* 103004 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36765 /* 103008 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36766 /* 103012 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36767 /* 103016 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36768 /* 103020 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36769 /* 103024 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36770 /* 103028 */ // (intrinsic_void 3962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRH32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36771 /* 103028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq_u),
36772 /* 103031 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36773 /* 103033 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36774 /* 103035 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36775 /* 103037 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36776 /* 103041 */ GIR_RootConstrainSelectedInstOperands,
36777 /* 103042 */ // GIR_Coverage, 5513,
36778 /* 103042 */ GIR_EraseRootFromParent_Done,
36779 /* 103043 */ // Label 1897: @103043
36780 /* 103043 */ GIM_Try, /*On fail goto*//*Label 1898*/ GIMT_Encode4(103104), // Rule ID 5514 //
36781 /* 103048 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36782 /* 103053 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36783 /* 103056 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
36784 /* 103059 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36785 /* 103062 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36786 /* 103065 */ // MIs[0] base
36787 /* 103065 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36788 /* 103069 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36789 /* 103073 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36790 /* 103077 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36791 /* 103081 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
36792 /* 103085 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
36793 /* 103089 */ // (intrinsic_void 3962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 16:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VSTRH32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36794 /* 103089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRH32_rq),
36795 /* 103092 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36796 /* 103094 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36797 /* 103096 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36798 /* 103098 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36799 /* 103102 */ GIR_RootConstrainSelectedInstOperands,
36800 /* 103103 */ // GIR_Coverage, 5514,
36801 /* 103103 */ GIR_EraseRootFromParent_Done,
36802 /* 103104 */ // Label 1898: @103104
36803 /* 103104 */ GIM_Try, /*On fail goto*//*Label 1899*/ GIMT_Encode4(103165), // Rule ID 5517 //
36804 /* 103109 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36805 /* 103114 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36806 /* 103117 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
36807 /* 103120 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36808 /* 103123 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36809 /* 103126 */ // MIs[0] base
36810 /* 103126 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36811 /* 103130 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36812 /* 103134 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36813 /* 103138 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36814 /* 103142 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
36815 /* 103146 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36816 /* 103150 */ // (intrinsic_void 3962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36817 /* 103150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u),
36818 /* 103153 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36819 /* 103155 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36820 /* 103157 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36821 /* 103159 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36822 /* 103163 */ GIR_RootConstrainSelectedInstOperands,
36823 /* 103164 */ // GIR_Coverage, 5517,
36824 /* 103164 */ GIR_EraseRootFromParent_Done,
36825 /* 103165 */ // Label 1899: @103165
36826 /* 103165 */ GIM_Try, /*On fail goto*//*Label 1900*/ GIMT_Encode4(103226), // Rule ID 5518 //
36827 /* 103170 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36828 /* 103175 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36829 /* 103178 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
36830 /* 103181 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36831 /* 103184 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36832 /* 103187 */ // MIs[0] base
36833 /* 103187 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36834 /* 103191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36835 /* 103195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36836 /* 103199 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36837 /* 103203 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
36838 /* 103207 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
36839 /* 103211 */ // (intrinsic_void 3962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4i32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4i32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36840 /* 103211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq),
36841 /* 103214 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36842 /* 103216 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36843 /* 103218 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36844 /* 103220 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36845 /* 103224 */ GIR_RootConstrainSelectedInstOperands,
36846 /* 103225 */ // GIR_Coverage, 5518,
36847 /* 103225 */ GIR_EraseRootFromParent_Done,
36848 /* 103226 */ // Label 1900: @103226
36849 /* 103226 */ GIM_Try, /*On fail goto*//*Label 1901*/ GIMT_Encode4(103287), // Rule ID 5521 //
36850 /* 103231 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36851 /* 103236 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36852 /* 103239 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
36853 /* 103242 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36854 /* 103245 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36855 /* 103248 */ // MIs[0] base
36856 /* 103248 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36857 /* 103252 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36858 /* 103256 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36859 /* 103260 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36860 /* 103264 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
36861 /* 103268 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36862 /* 103272 */ // (intrinsic_void 3962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRW32_rq_u MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36863 /* 103272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq_u),
36864 /* 103275 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36865 /* 103277 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36866 /* 103279 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36867 /* 103281 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36868 /* 103285 */ GIR_RootConstrainSelectedInstOperands,
36869 /* 103286 */ // GIR_Coverage, 5521,
36870 /* 103286 */ GIR_EraseRootFromParent_Done,
36871 /* 103287 */ // Label 1901: @103287
36872 /* 103287 */ GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(103348), // Rule ID 5522 //
36873 /* 103292 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36874 /* 103297 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
36875 /* 103300 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
36876 /* 103303 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36877 /* 103306 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36878 /* 103309 */ // MIs[0] base
36879 /* 103309 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36880 /* 103313 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36881 /* 103317 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36882 /* 103321 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36883 /* 103325 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
36884 /* 103329 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
36885 /* 103333 */ // (intrinsic_void 3962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, MQPR:{ *:[v4f32] }:$data, 32:{ *:[i32] }, 2:{ *:[i32] }) => (MVE_VSTRW32_rq MQPR:{ *:[v4f32] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
36886 /* 103333 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRW32_rq),
36887 /* 103336 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36888 /* 103338 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36889 /* 103340 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36890 /* 103342 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36891 /* 103346 */ GIR_RootConstrainSelectedInstOperands,
36892 /* 103347 */ // GIR_Coverage, 5522,
36893 /* 103347 */ GIR_EraseRootFromParent_Done,
36894 /* 103348 */ // Label 1902: @103348
36895 /* 103348 */ GIM_Try, /*On fail goto*//*Label 1903*/ GIMT_Encode4(103409), // Rule ID 5525 //
36896 /* 103353 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36897 /* 103358 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
36898 /* 103361 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
36899 /* 103364 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36900 /* 103367 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36901 /* 103370 */ // MIs[0] base
36902 /* 103370 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36903 /* 103374 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36904 /* 103378 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36905 /* 103382 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36906 /* 103386 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
36907 /* 103390 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
36908 /* 103394 */ // (intrinsic_void 3962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VSTRD64_rq_u MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36909 /* 103394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq_u),
36910 /* 103397 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36911 /* 103399 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36912 /* 103401 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36913 /* 103403 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36914 /* 103407 */ GIR_RootConstrainSelectedInstOperands,
36915 /* 103408 */ // GIR_Coverage, 5525,
36916 /* 103408 */ GIR_EraseRootFromParent_Done,
36917 /* 103409 */ // Label 1903: @103409
36918 /* 103409 */ GIM_Try, /*On fail goto*//*Label 1904*/ GIMT_Encode4(103470), // Rule ID 5526 //
36919 /* 103414 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mve_vstr_scatter_offset),
36920 /* 103419 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
36921 /* 103422 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
36922 /* 103425 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36923 /* 103428 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
36924 /* 103431 */ // MIs[0] base
36925 /* 103431 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32,
36926 /* 103435 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
36927 /* 103439 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36928 /* 103443 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
36929 /* 103447 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
36930 /* 103451 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
36931 /* 103455 */ // (intrinsic_void 3962:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, MQPR:{ *:[v2i64] }:$data, 64:{ *:[i32] }, 3:{ *:[i32] }) => (MVE_VSTRD64_rq MQPR:{ *:[v2i64] }:$data, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
36932 /* 103455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSTRD64_rq),
36933 /* 103458 */ GIR_RootToRootCopy, /*OpIdx*/3, // data
36934 /* 103460 */ GIR_RootToRootCopy, /*OpIdx*/1, // base
36935 /* 103462 */ GIR_RootToRootCopy, /*OpIdx*/2, // offsets
36936 /* 103464 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36937 /* 103468 */ GIR_RootConstrainSelectedInstOperands,
36938 /* 103469 */ // GIR_Coverage, 5526,
36939 /* 103469 */ GIR_EraseRootFromParent_Done,
36940 /* 103470 */ // Label 1904: @103470
36941 /* 103470 */ GIM_Try, /*On fail goto*//*Label 1905*/ GIMT_Encode4(103534), // Rule ID 257 //
36942 /* 103475 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
36943 /* 103478 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr),
36944 /* 103483 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36945 /* 103486 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36946 /* 103489 */ // MIs[0] cop
36947 /* 103489 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36948 /* 103492 */ // MIs[0] opc1
36949 /* 103492 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36950 /* 103495 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36951 /* 103499 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36952 /* 103503 */ // MIs[0] CRm
36953 /* 103503 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36954 /* 103506 */ // (intrinsic_void 3747:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
36955 /* 103506 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR),
36956 /* 103509 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
36957 /* 103511 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
36958 /* 103513 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
36959 /* 103515 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
36960 /* 103517 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
36961 /* 103519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
36962 /* 103522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
36963 /* 103528 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36964 /* 103532 */ GIR_RootConstrainSelectedInstOperands,
36965 /* 103533 */ // GIR_Coverage, 257,
36966 /* 103533 */ GIR_EraseRootFromParent_Done,
36967 /* 103534 */ // Label 1905: @103534
36968 /* 103534 */ GIM_Try, /*On fail goto*//*Label 1906*/ GIMT_Encode4(103589), // Rule ID 258 //
36969 /* 103539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8),
36970 /* 103542 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2),
36971 /* 103547 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36972 /* 103550 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36973 /* 103553 */ // MIs[0] cop
36974 /* 103553 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
36975 /* 103556 */ // MIs[0] opc1
36976 /* 103556 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
36977 /* 103559 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36978 /* 103563 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
36979 /* 103567 */ // MIs[0] CRm
36980 /* 103567 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
36981 /* 103570 */ // (intrinsic_void 3748:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
36982 /* 103570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCRR2),
36983 /* 103573 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
36984 /* 103575 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
36985 /* 103577 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
36986 /* 103579 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
36987 /* 103581 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
36988 /* 103583 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
36989 /* 103587 */ GIR_RootConstrainSelectedInstOperands,
36990 /* 103588 */ // GIR_Coverage, 258,
36991 /* 103588 */ GIR_EraseRootFromParent_Done,
36992 /* 103589 */ // Label 1906: @103589
36993 /* 103589 */ GIM_Try, /*On fail goto*//*Label 1907*/ GIMT_Encode4(103653), // Rule ID 595 //
36994 /* 103594 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
36995 /* 103597 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr),
36996 /* 103602 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
36997 /* 103605 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
36998 /* 103608 */ // MIs[0] cop
36999 /* 103608 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37000 /* 103611 */ // MIs[0] opc1
37001 /* 103611 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37002 /* 103614 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37003 /* 103618 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37004 /* 103622 */ // MIs[0] CRm
37005 /* 103622 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37006 /* 103625 */ // (intrinsic_void 3747:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
37007 /* 103625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR),
37008 /* 103628 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
37009 /* 103630 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
37010 /* 103632 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
37011 /* 103634 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
37012 /* 103636 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
37013 /* 103638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37014 /* 103641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37015 /* 103647 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37016 /* 103651 */ GIR_RootConstrainSelectedInstOperands,
37017 /* 103652 */ // GIR_Coverage, 595,
37018 /* 103652 */ GIR_EraseRootFromParent_Done,
37019 /* 103653 */ // Label 1907: @103653
37020 /* 103653 */ GIM_Try, /*On fail goto*//*Label 1908*/ GIMT_Encode4(103717), // Rule ID 596 //
37021 /* 103658 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8),
37022 /* 103661 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcrr2),
37023 /* 103666 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
37024 /* 103669 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37025 /* 103672 */ // MIs[0] cop
37026 /* 103672 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37027 /* 103675 */ // MIs[0] opc1
37028 /* 103675 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37029 /* 103678 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37030 /* 103682 */ GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37031 /* 103686 */ // MIs[0] CRm
37032 /* 103686 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37033 /* 103689 */ // (intrinsic_void 3748:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm) => (t2MCRR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (timm:{ *:[i32] }):$CRm)
37034 /* 103689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCRR2),
37035 /* 103692 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
37036 /* 103694 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
37037 /* 103696 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
37038 /* 103698 */ GIR_RootToRootCopy, /*OpIdx*/4, // Rt2
37039 /* 103700 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
37040 /* 103702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37041 /* 103705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37042 /* 103711 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37043 /* 103715 */ GIR_RootConstrainSelectedInstOperands,
37044 /* 103716 */ // GIR_Coverage, 596,
37045 /* 103716 */ GIR_EraseRootFromParent_Done,
37046 /* 103717 */ // Label 1908: @103717
37047 /* 103717 */ GIM_Reject,
37048 /* 103718 */ // Label 1889: @103718
37049 /* 103718 */ GIM_Try, /*On fail goto*//*Label 1909*/ GIMT_Encode4(107069),
37050 /* 103723 */ GIM_CheckNumOperands, /*MI*/0, /*Expected*/7,
37051 /* 103726 */ GIM_Try, /*On fail goto*//*Label 1910*/ GIMT_Encode4(103787), // Rule ID 245 //
37052 /* 103731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8),
37053 /* 103734 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp),
37054 /* 103739 */ // MIs[0] cop
37055 /* 103739 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37056 /* 103742 */ // MIs[0] opc1
37057 /* 103742 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37058 /* 103745 */ // MIs[0] CRd
37059 /* 103745 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
37060 /* 103748 */ // MIs[0] CRn
37061 /* 103748 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
37062 /* 103751 */ // MIs[0] CRm
37063 /* 103751 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37064 /* 103754 */ // MIs[0] opc2
37065 /* 103754 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
37066 /* 103757 */ // (intrinsic_void 3715:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
37067 /* 103757 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP),
37068 /* 103760 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
37069 /* 103762 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
37070 /* 103764 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
37071 /* 103766 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
37072 /* 103768 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
37073 /* 103770 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
37074 /* 103772 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37075 /* 103775 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37076 /* 103781 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37077 /* 103785 */ GIR_RootConstrainSelectedInstOperands,
37078 /* 103786 */ // GIR_Coverage, 245,
37079 /* 103786 */ GIR_EraseRootFromParent_Done,
37080 /* 103787 */ // Label 1910: @103787
37081 /* 103787 */ GIM_Try, /*On fail goto*//*Label 1911*/ GIMT_Encode4(103839), // Rule ID 246 //
37082 /* 103792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8),
37083 /* 103795 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2),
37084 /* 103800 */ // MIs[0] cop
37085 /* 103800 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37086 /* 103803 */ // MIs[0] opc1
37087 /* 103803 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37088 /* 103806 */ // MIs[0] CRd
37089 /* 103806 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
37090 /* 103809 */ // MIs[0] CRn
37091 /* 103809 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
37092 /* 103812 */ // MIs[0] CRm
37093 /* 103812 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37094 /* 103815 */ // MIs[0] opc2
37095 /* 103815 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
37096 /* 103818 */ // (intrinsic_void 3716:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
37097 /* 103818 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CDP2),
37098 /* 103821 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
37099 /* 103823 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
37100 /* 103825 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
37101 /* 103827 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
37102 /* 103829 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
37103 /* 103831 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
37104 /* 103833 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37105 /* 103837 */ GIR_RootConstrainSelectedInstOperands,
37106 /* 103838 */ // GIR_Coverage, 246,
37107 /* 103838 */ GIR_EraseRootFromParent_Done,
37108 /* 103839 */ // Label 1911: @103839
37109 /* 103839 */ GIM_Try, /*On fail goto*//*Label 1912*/ GIMT_Encode4(103900), // Rule ID 597 //
37110 /* 103844 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8),
37111 /* 103847 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp),
37112 /* 103852 */ // MIs[0] cop
37113 /* 103852 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37114 /* 103855 */ // MIs[0] opc1
37115 /* 103855 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37116 /* 103858 */ // MIs[0] CRd
37117 /* 103858 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
37118 /* 103861 */ // MIs[0] CRn
37119 /* 103861 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
37120 /* 103864 */ // MIs[0] CRm
37121 /* 103864 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37122 /* 103867 */ // MIs[0] opc2
37123 /* 103867 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
37124 /* 103870 */ // (intrinsic_void 3715:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
37125 /* 103870 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP),
37126 /* 103873 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
37127 /* 103875 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
37128 /* 103877 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
37129 /* 103879 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
37130 /* 103881 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
37131 /* 103883 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
37132 /* 103885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37133 /* 103888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37134 /* 103894 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37135 /* 103898 */ GIR_RootConstrainSelectedInstOperands,
37136 /* 103899 */ // GIR_Coverage, 597,
37137 /* 103899 */ GIR_EraseRootFromParent_Done,
37138 /* 103900 */ // Label 1912: @103900
37139 /* 103900 */ GIM_Try, /*On fail goto*//*Label 1913*/ GIMT_Encode4(103961), // Rule ID 598 //
37140 /* 103905 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8),
37141 /* 103908 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_cdp2),
37142 /* 103913 */ // MIs[0] cop
37143 /* 103913 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
37144 /* 103916 */ // MIs[0] opc1
37145 /* 103916 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
37146 /* 103919 */ // MIs[0] CRd
37147 /* 103919 */ GIM_CheckIsImm, /*MI*/0, /*Op*/3,
37148 /* 103922 */ // MIs[0] CRn
37149 /* 103922 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
37150 /* 103925 */ // MIs[0] CRm
37151 /* 103925 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
37152 /* 103928 */ // MIs[0] opc2
37153 /* 103928 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
37154 /* 103931 */ // (intrinsic_void 3716:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2CDP2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, (timm:{ *:[i32] }):$CRd, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
37155 /* 103931 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CDP2),
37156 /* 103934 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
37157 /* 103936 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
37158 /* 103938 */ GIR_RootToRootCopy, /*OpIdx*/3, // CRd
37159 /* 103940 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
37160 /* 103942 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
37161 /* 103944 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
37162 /* 103946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
37163 /* 103949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
37164 /* 103955 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37165 /* 103959 */ GIR_RootConstrainSelectedInstOperands,
37166 /* 103960 */ // GIR_Coverage, 598,
37167 /* 103960 */ GIR_EraseRootFromParent_Done,
37168 /* 103961 */ // Label 1913: @103961
37169 /* 103961 */ GIM_Try, /*On fail goto*//*Label 1914*/ GIMT_Encode4(104029), // Rule ID 5415 //
37170 /* 103966 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37171 /* 103971 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37172 /* 103974 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37173 /* 103977 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37174 /* 103980 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37175 /* 103983 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37176 /* 103986 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37177 /* 103990 */ // MIs[0] base
37178 /* 103990 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37179 /* 103994 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37180 /* 103998 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37181 /* 104002 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37182 /* 104006 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37183 /* 104010 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37184 /* 104014 */ // (intrinsic_w_chain:{ *:[v8i16] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37185 /* 104014 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
37186 /* 104017 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37187 /* 104019 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37188 /* 104021 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37189 /* 104023 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37190 /* 104027 */ GIR_RootConstrainSelectedInstOperands,
37191 /* 104028 */ // GIR_Coverage, 5415,
37192 /* 104028 */ GIR_EraseRootFromParent_Done,
37193 /* 104029 */ // Label 1914: @104029
37194 /* 104029 */ GIM_Try, /*On fail goto*//*Label 1915*/ GIMT_Encode4(104097), // Rule ID 5416 //
37195 /* 104034 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37196 /* 104039 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37197 /* 104042 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37198 /* 104045 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37199 /* 104048 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37200 /* 104051 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37201 /* 104054 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37202 /* 104058 */ // MIs[0] base
37203 /* 104058 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37204 /* 104062 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37205 /* 104066 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37206 /* 104070 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37207 /* 104074 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37208 /* 104078 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37209 /* 104082 */ // (intrinsic_w_chain:{ *:[v8i16] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37210 /* 104082 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37211 /* 104085 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37212 /* 104087 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37213 /* 104089 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37214 /* 104091 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37215 /* 104095 */ GIR_RootConstrainSelectedInstOperands,
37216 /* 104096 */ // GIR_Coverage, 5416,
37217 /* 104096 */ GIR_EraseRootFromParent_Done,
37218 /* 104097 */ // Label 1915: @104097
37219 /* 104097 */ GIM_Try, /*On fail goto*//*Label 1916*/ GIMT_Encode4(104165), // Rule ID 5419 //
37220 /* 104102 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37221 /* 104107 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
37222 /* 104110 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
37223 /* 104113 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37224 /* 104116 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37225 /* 104119 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37226 /* 104122 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37227 /* 104126 */ // MIs[0] base
37228 /* 104126 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37229 /* 104130 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37230 /* 104134 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37231 /* 104138 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
37232 /* 104142 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37233 /* 104146 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37234 /* 104150 */ // (intrinsic_w_chain:{ *:[v16i8] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
37235 /* 104150 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq),
37236 /* 104153 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37237 /* 104155 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37238 /* 104157 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37239 /* 104159 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37240 /* 104163 */ GIR_RootConstrainSelectedInstOperands,
37241 /* 104164 */ // GIR_Coverage, 5419,
37242 /* 104164 */ GIR_EraseRootFromParent_Done,
37243 /* 104165 */ // Label 1916: @104165
37244 /* 104165 */ GIM_Try, /*On fail goto*//*Label 1917*/ GIMT_Encode4(104233), // Rule ID 5427 //
37245 /* 104170 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37246 /* 104175 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s8,
37247 /* 104178 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s8,
37248 /* 104181 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37249 /* 104184 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37250 /* 104187 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37251 /* 104190 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37252 /* 104194 */ // MIs[0] base
37253 /* 104194 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37254 /* 104198 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37255 /* 104202 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37256 /* 104206 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
37257 /* 104210 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37258 /* 104214 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37259 /* 104218 */ // (intrinsic_w_chain:{ *:[v16i8] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBU8_rq:{ *:[v16i8] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v16i8] }:$offsets)
37260 /* 104218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU8_rq),
37261 /* 104221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37262 /* 104223 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37263 /* 104225 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37264 /* 104227 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37265 /* 104231 */ GIR_RootConstrainSelectedInstOperands,
37266 /* 104232 */ // GIR_Coverage, 5427,
37267 /* 104232 */ GIR_EraseRootFromParent_Done,
37268 /* 104233 */ // Label 1917: @104233
37269 /* 104233 */ GIM_Try, /*On fail goto*//*Label 1918*/ GIMT_Encode4(104301), // Rule ID 5429 //
37270 /* 104238 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37271 /* 104243 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37272 /* 104246 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37273 /* 104249 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37274 /* 104252 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37275 /* 104255 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37276 /* 104258 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37277 /* 104262 */ // MIs[0] base
37278 /* 104262 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37279 /* 104266 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37280 /* 104270 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37281 /* 104274 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
37282 /* 104278 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37283 /* 104282 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37284 /* 104286 */ // (intrinsic_w_chain:{ *:[v8i16] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37285 /* 104286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU16_rq),
37286 /* 104289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37287 /* 104291 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37288 /* 104293 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37289 /* 104295 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37290 /* 104299 */ GIR_RootConstrainSelectedInstOperands,
37291 /* 104300 */ // GIR_Coverage, 5429,
37292 /* 104300 */ GIR_EraseRootFromParent_Done,
37293 /* 104301 */ // Label 1918: @104301
37294 /* 104301 */ GIM_Try, /*On fail goto*//*Label 1919*/ GIMT_Encode4(104369), // Rule ID 5431 //
37295 /* 104306 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37296 /* 104311 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37297 /* 104314 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37298 /* 104317 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37299 /* 104320 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37300 /* 104323 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37301 /* 104326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37302 /* 104330 */ // MIs[0] base
37303 /* 104330 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37304 /* 104334 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37305 /* 104338 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37306 /* 104342 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
37307 /* 104346 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37308 /* 104350 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37309 /* 104354 */ // (intrinsic_w_chain:{ *:[v8i16] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37310 /* 104354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS16_rq),
37311 /* 104357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37312 /* 104359 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37313 /* 104361 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37314 /* 104363 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37315 /* 104367 */ GIR_RootConstrainSelectedInstOperands,
37316 /* 104368 */ // GIR_Coverage, 5431,
37317 /* 104368 */ GIR_EraseRootFromParent_Done,
37318 /* 104369 */ // Label 1919: @104369
37319 /* 104369 */ GIM_Try, /*On fail goto*//*Label 1920*/ GIMT_Encode4(104437), // Rule ID 5433 //
37320 /* 104374 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37321 /* 104379 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37322 /* 104382 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37323 /* 104385 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37324 /* 104388 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37325 /* 104391 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37326 /* 104394 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37327 /* 104398 */ // MIs[0] base
37328 /* 104398 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37329 /* 104402 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37330 /* 104406 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37331 /* 104410 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
37332 /* 104414 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37333 /* 104418 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37334 /* 104422 */ // (intrinsic_w_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRBU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37335 /* 104422 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBU32_rq),
37336 /* 104425 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37337 /* 104427 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37338 /* 104429 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37339 /* 104431 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37340 /* 104435 */ GIR_RootConstrainSelectedInstOperands,
37341 /* 104436 */ // GIR_Coverage, 5433,
37342 /* 104436 */ GIR_EraseRootFromParent_Done,
37343 /* 104437 */ // Label 1920: @104437
37344 /* 104437 */ GIM_Try, /*On fail goto*//*Label 1921*/ GIMT_Encode4(104505), // Rule ID 5435 //
37345 /* 104442 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37346 /* 104447 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37347 /* 104450 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37348 /* 104453 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37349 /* 104456 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37350 /* 104459 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37351 /* 104462 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37352 /* 104466 */ // MIs[0] base
37353 /* 104466 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37354 /* 104470 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37355 /* 104474 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37356 /* 104478 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 8,
37357 /* 104482 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37358 /* 104486 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37359 /* 104490 */ // (intrinsic_w_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 8:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRBS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37360 /* 104490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRBS32_rq),
37361 /* 104493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37362 /* 104495 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37363 /* 104497 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37364 /* 104499 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37365 /* 104503 */ GIR_RootConstrainSelectedInstOperands,
37366 /* 104504 */ // GIR_Coverage, 5435,
37367 /* 104504 */ GIR_EraseRootFromParent_Done,
37368 /* 104505 */ // Label 1921: @104505
37369 /* 104505 */ GIM_Try, /*On fail goto*//*Label 1922*/ GIMT_Encode4(104573), // Rule ID 5437 //
37370 /* 104510 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37371 /* 104515 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37372 /* 104518 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37373 /* 104521 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37374 /* 104524 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37375 /* 104527 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37376 /* 104530 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37377 /* 104534 */ // MIs[0] base
37378 /* 104534 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37379 /* 104538 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37380 /* 104542 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37381 /* 104546 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37382 /* 104550 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37383 /* 104554 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37384 /* 104558 */ // (intrinsic_w_chain:{ *:[v8i16] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37385 /* 104558 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
37386 /* 104561 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37387 /* 104563 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37388 /* 104565 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37389 /* 104567 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37390 /* 104571 */ GIR_RootConstrainSelectedInstOperands,
37391 /* 104572 */ // GIR_Coverage, 5437,
37392 /* 104572 */ GIR_EraseRootFromParent_Done,
37393 /* 104573 */ // Label 1922: @104573
37394 /* 104573 */ GIM_Try, /*On fail goto*//*Label 1923*/ GIMT_Encode4(104641), // Rule ID 5438 //
37395 /* 104578 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37396 /* 104583 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37397 /* 104586 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37398 /* 104589 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37399 /* 104592 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37400 /* 104595 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37401 /* 104598 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37402 /* 104602 */ // MIs[0] base
37403 /* 104602 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37404 /* 104606 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37405 /* 104610 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37406 /* 104614 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37407 /* 104618 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37408 /* 104622 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37409 /* 104626 */ // (intrinsic_w_chain:{ *:[v8i16] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37410 /* 104626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37411 /* 104629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37412 /* 104631 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37413 /* 104633 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37414 /* 104635 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37415 /* 104639 */ GIR_RootConstrainSelectedInstOperands,
37416 /* 104640 */ // GIR_Coverage, 5438,
37417 /* 104640 */ GIR_EraseRootFromParent_Done,
37418 /* 104641 */ // Label 1923: @104641
37419 /* 104641 */ GIM_Try, /*On fail goto*//*Label 1924*/ GIMT_Encode4(104709), // Rule ID 5441 //
37420 /* 104646 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37421 /* 104651 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37422 /* 104654 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37423 /* 104657 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37424 /* 104660 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37425 /* 104663 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37426 /* 104666 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37427 /* 104670 */ // MIs[0] base
37428 /* 104670 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37429 /* 104674 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37430 /* 104678 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37431 /* 104682 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37432 /* 104686 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37433 /* 104690 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37434 /* 104694 */ // (intrinsic_w_chain:{ *:[v8i16] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37435 /* 104694 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
37436 /* 104697 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37437 /* 104699 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37438 /* 104701 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37439 /* 104703 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37440 /* 104707 */ GIR_RootConstrainSelectedInstOperands,
37441 /* 104708 */ // GIR_Coverage, 5441,
37442 /* 104708 */ GIR_EraseRootFromParent_Done,
37443 /* 104709 */ // Label 1924: @104709
37444 /* 104709 */ GIM_Try, /*On fail goto*//*Label 1925*/ GIMT_Encode4(104777), // Rule ID 5442 //
37445 /* 104714 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37446 /* 104719 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37447 /* 104722 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37448 /* 104725 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37449 /* 104728 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37450 /* 104731 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37451 /* 104734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37452 /* 104738 */ // MIs[0] base
37453 /* 104738 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37454 /* 104742 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37455 /* 104746 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37456 /* 104750 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37457 /* 104754 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37458 /* 104758 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37459 /* 104762 */ // (intrinsic_w_chain:{ *:[v8i16] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37460 /* 104762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37461 /* 104765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37462 /* 104767 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37463 /* 104769 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37464 /* 104771 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37465 /* 104775 */ GIR_RootConstrainSelectedInstOperands,
37466 /* 104776 */ // GIR_Coverage, 5442,
37467 /* 104776 */ GIR_EraseRootFromParent_Done,
37468 /* 104777 */ // Label 1925: @104777
37469 /* 104777 */ GIM_Try, /*On fail goto*//*Label 1926*/ GIMT_Encode4(104845), // Rule ID 5445 //
37470 /* 104782 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37471 /* 104787 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37472 /* 104790 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37473 /* 104793 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37474 /* 104796 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37475 /* 104799 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37476 /* 104802 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37477 /* 104806 */ // MIs[0] base
37478 /* 104806 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37479 /* 104810 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37480 /* 104814 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37481 /* 104818 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37482 /* 104822 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37483 /* 104826 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37484 /* 104830 */ // (intrinsic_w_chain:{ *:[v8i16] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37485 /* 104830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
37486 /* 104833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37487 /* 104835 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37488 /* 104837 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37489 /* 104839 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37490 /* 104843 */ GIR_RootConstrainSelectedInstOperands,
37491 /* 104844 */ // GIR_Coverage, 5445,
37492 /* 104844 */ GIR_EraseRootFromParent_Done,
37493 /* 104845 */ // Label 1926: @104845
37494 /* 104845 */ GIM_Try, /*On fail goto*//*Label 1927*/ GIMT_Encode4(104913), // Rule ID 5446 //
37495 /* 104850 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37496 /* 104855 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37497 /* 104858 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37498 /* 104861 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37499 /* 104864 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37500 /* 104867 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37501 /* 104870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37502 /* 104874 */ // MIs[0] base
37503 /* 104874 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37504 /* 104878 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37505 /* 104882 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37506 /* 104886 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37507 /* 104890 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37508 /* 104894 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37509 /* 104898 */ // (intrinsic_w_chain:{ *:[v8i16] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8i16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37510 /* 104898 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37511 /* 104901 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37512 /* 104903 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37513 /* 104905 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37514 /* 104907 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37515 /* 104911 */ GIR_RootConstrainSelectedInstOperands,
37516 /* 104912 */ // GIR_Coverage, 5446,
37517 /* 104912 */ GIR_EraseRootFromParent_Done,
37518 /* 104913 */ // Label 1927: @104913
37519 /* 104913 */ GIM_Try, /*On fail goto*//*Label 1928*/ GIMT_Encode4(104981), // Rule ID 5449 //
37520 /* 104918 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37521 /* 104923 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37522 /* 104926 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37523 /* 104929 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37524 /* 104932 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37525 /* 104935 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37526 /* 104938 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37527 /* 104942 */ // MIs[0] base
37528 /* 104942 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37529 /* 104946 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37530 /* 104950 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37531 /* 104954 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37532 /* 104958 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37533 /* 104962 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37534 /* 104966 */ // (intrinsic_w_chain:{ *:[v8f16] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37535 /* 104966 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
37536 /* 104969 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37537 /* 104971 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37538 /* 104973 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37539 /* 104975 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37540 /* 104979 */ GIR_RootConstrainSelectedInstOperands,
37541 /* 104980 */ // GIR_Coverage, 5449,
37542 /* 104980 */ GIR_EraseRootFromParent_Done,
37543 /* 104981 */ // Label 1928: @104981
37544 /* 104981 */ GIM_Try, /*On fail goto*//*Label 1929*/ GIMT_Encode4(105049), // Rule ID 5450 //
37545 /* 104986 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37546 /* 104991 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37547 /* 104994 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37548 /* 104997 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37549 /* 105000 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37550 /* 105003 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37551 /* 105006 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37552 /* 105010 */ // MIs[0] base
37553 /* 105010 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37554 /* 105014 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37555 /* 105018 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37556 /* 105022 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37557 /* 105026 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37558 /* 105030 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37559 /* 105034 */ // (intrinsic_w_chain:{ *:[v8f16] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37560 /* 105034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37561 /* 105037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37562 /* 105039 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37563 /* 105041 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37564 /* 105043 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37565 /* 105047 */ GIR_RootConstrainSelectedInstOperands,
37566 /* 105048 */ // GIR_Coverage, 5450,
37567 /* 105048 */ GIR_EraseRootFromParent_Done,
37568 /* 105049 */ // Label 1929: @105049
37569 /* 105049 */ GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(105117), // Rule ID 5453 //
37570 /* 105054 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37571 /* 105059 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37572 /* 105062 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37573 /* 105065 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37574 /* 105068 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37575 /* 105071 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37576 /* 105074 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37577 /* 105078 */ // MIs[0] base
37578 /* 105078 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37579 /* 105082 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37580 /* 105086 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37581 /* 105090 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37582 /* 105094 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37583 /* 105098 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37584 /* 105102 */ // (intrinsic_w_chain:{ *:[v8f16] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq_u:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37585 /* 105102 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq_u),
37586 /* 105105 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37587 /* 105107 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37588 /* 105109 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37589 /* 105111 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37590 /* 105115 */ GIR_RootConstrainSelectedInstOperands,
37591 /* 105116 */ // GIR_Coverage, 5453,
37592 /* 105116 */ GIR_EraseRootFromParent_Done,
37593 /* 105117 */ // Label 1930: @105117
37594 /* 105117 */ GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(105185), // Rule ID 5454 //
37595 /* 105122 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37596 /* 105127 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16,
37597 /* 105130 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
37598 /* 105133 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37599 /* 105136 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37600 /* 105139 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37601 /* 105142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37602 /* 105146 */ // MIs[0] base
37603 /* 105146 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37604 /* 105150 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37605 /* 105154 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37606 /* 105158 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37607 /* 105162 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37608 /* 105166 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37609 /* 105170 */ // (intrinsic_w_chain:{ *:[v8f16] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU16_rq:{ *:[v8f16] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v8i16] }:$offsets)
37610 /* 105170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU16_rq),
37611 /* 105173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37612 /* 105175 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37613 /* 105177 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37614 /* 105179 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37615 /* 105183 */ GIR_RootConstrainSelectedInstOperands,
37616 /* 105184 */ // GIR_Coverage, 5454,
37617 /* 105184 */ GIR_EraseRootFromParent_Done,
37618 /* 105185 */ // Label 1931: @105185
37619 /* 105185 */ GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(105253), // Rule ID 5457 //
37620 /* 105190 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37621 /* 105195 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37622 /* 105198 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37623 /* 105201 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37624 /* 105204 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37625 /* 105207 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37626 /* 105210 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37627 /* 105214 */ // MIs[0] base
37628 /* 105214 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37629 /* 105218 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37630 /* 105222 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37631 /* 105226 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37632 /* 105230 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37633 /* 105234 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37634 /* 105238 */ // (intrinsic_w_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37635 /* 105238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq_u),
37636 /* 105241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37637 /* 105243 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37638 /* 105245 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37639 /* 105247 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37640 /* 105251 */ GIR_RootConstrainSelectedInstOperands,
37641 /* 105252 */ // GIR_Coverage, 5457,
37642 /* 105252 */ GIR_EraseRootFromParent_Done,
37643 /* 105253 */ // Label 1932: @105253
37644 /* 105253 */ GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(105321), // Rule ID 5458 //
37645 /* 105258 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37646 /* 105263 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37647 /* 105266 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37648 /* 105269 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37649 /* 105272 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37650 /* 105275 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37651 /* 105278 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37652 /* 105282 */ // MIs[0] base
37653 /* 105282 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37654 /* 105286 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37655 /* 105290 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37656 /* 105294 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37657 /* 105298 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37658 /* 105302 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37659 /* 105306 */ // (intrinsic_w_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRHU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37660 /* 105306 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHU32_rq),
37661 /* 105309 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37662 /* 105311 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37663 /* 105313 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37664 /* 105315 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37665 /* 105319 */ GIR_RootConstrainSelectedInstOperands,
37666 /* 105320 */ // GIR_Coverage, 5458,
37667 /* 105320 */ GIR_EraseRootFromParent_Done,
37668 /* 105321 */ // Label 1933: @105321
37669 /* 105321 */ GIM_Try, /*On fail goto*//*Label 1934*/ GIMT_Encode4(105389), // Rule ID 5461 //
37670 /* 105326 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37671 /* 105331 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37672 /* 105334 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37673 /* 105337 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37674 /* 105340 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37675 /* 105343 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37676 /* 105346 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37677 /* 105350 */ // MIs[0] base
37678 /* 105350 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37679 /* 105354 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37680 /* 105358 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37681 /* 105362 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37682 /* 105366 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37683 /* 105370 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37684 /* 105374 */ // (intrinsic_w_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37685 /* 105374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq_u),
37686 /* 105377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37687 /* 105379 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37688 /* 105381 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37689 /* 105383 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37690 /* 105387 */ GIR_RootConstrainSelectedInstOperands,
37691 /* 105388 */ // GIR_Coverage, 5461,
37692 /* 105388 */ GIR_EraseRootFromParent_Done,
37693 /* 105389 */ // Label 1934: @105389
37694 /* 105389 */ GIM_Try, /*On fail goto*//*Label 1935*/ GIMT_Encode4(105457), // Rule ID 5462 //
37695 /* 105394 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37696 /* 105399 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37697 /* 105402 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37698 /* 105405 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37699 /* 105408 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37700 /* 105411 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37701 /* 105414 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37702 /* 105418 */ // MIs[0] base
37703 /* 105418 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37704 /* 105422 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37705 /* 105426 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37706 /* 105430 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 16,
37707 /* 105434 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 1,
37708 /* 105438 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37709 /* 105442 */ // (intrinsic_w_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 16:{ *:[i32] }, 1:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRHS32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37710 /* 105442 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRHS32_rq),
37711 /* 105445 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37712 /* 105447 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37713 /* 105449 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37714 /* 105451 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37715 /* 105455 */ GIR_RootConstrainSelectedInstOperands,
37716 /* 105456 */ // GIR_Coverage, 5462,
37717 /* 105456 */ GIR_EraseRootFromParent_Done,
37718 /* 105457 */ // Label 1935: @105457
37719 /* 105457 */ GIM_Try, /*On fail goto*//*Label 1936*/ GIMT_Encode4(105525), // Rule ID 5465 //
37720 /* 105462 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37721 /* 105467 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37722 /* 105470 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37723 /* 105473 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37724 /* 105476 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37725 /* 105479 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37726 /* 105482 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37727 /* 105486 */ // MIs[0] base
37728 /* 105486 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37729 /* 105490 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37730 /* 105494 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37731 /* 105498 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37732 /* 105502 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37733 /* 105506 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37734 /* 105510 */ // (intrinsic_w_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37735 /* 105510 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37736 /* 105513 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37737 /* 105515 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37738 /* 105517 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37739 /* 105519 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37740 /* 105523 */ GIR_RootConstrainSelectedInstOperands,
37741 /* 105524 */ // GIR_Coverage, 5465,
37742 /* 105524 */ GIR_EraseRootFromParent_Done,
37743 /* 105525 */ // Label 1936: @105525
37744 /* 105525 */ GIM_Try, /*On fail goto*//*Label 1937*/ GIMT_Encode4(105593), // Rule ID 5466 //
37745 /* 105530 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37746 /* 105535 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37747 /* 105538 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37748 /* 105541 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37749 /* 105544 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37750 /* 105547 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37751 /* 105550 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37752 /* 105554 */ // MIs[0] base
37753 /* 105554 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37754 /* 105558 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37755 /* 105562 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37756 /* 105566 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37757 /* 105570 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37758 /* 105574 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37759 /* 105578 */ // (intrinsic_w_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37760 /* 105578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37761 /* 105581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37762 /* 105583 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37763 /* 105585 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37764 /* 105587 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37765 /* 105591 */ GIR_RootConstrainSelectedInstOperands,
37766 /* 105592 */ // GIR_Coverage, 5466,
37767 /* 105592 */ GIR_EraseRootFromParent_Done,
37768 /* 105593 */ // Label 1937: @105593
37769 /* 105593 */ GIM_Try, /*On fail goto*//*Label 1938*/ GIMT_Encode4(105661), // Rule ID 5469 //
37770 /* 105598 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37771 /* 105603 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37772 /* 105606 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37773 /* 105609 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37774 /* 105612 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37775 /* 105615 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37776 /* 105618 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37777 /* 105622 */ // MIs[0] base
37778 /* 105622 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37779 /* 105626 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37780 /* 105630 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37781 /* 105634 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37782 /* 105638 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37783 /* 105642 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37784 /* 105646 */ // (intrinsic_w_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37785 /* 105646 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37786 /* 105649 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37787 /* 105651 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37788 /* 105653 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37789 /* 105655 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37790 /* 105659 */ GIR_RootConstrainSelectedInstOperands,
37791 /* 105660 */ // GIR_Coverage, 5469,
37792 /* 105660 */ GIR_EraseRootFromParent_Done,
37793 /* 105661 */ // Label 1938: @105661
37794 /* 105661 */ GIM_Try, /*On fail goto*//*Label 1939*/ GIMT_Encode4(105729), // Rule ID 5470 //
37795 /* 105666 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37796 /* 105671 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37797 /* 105674 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37798 /* 105677 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37799 /* 105680 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37800 /* 105683 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37801 /* 105686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37802 /* 105690 */ // MIs[0] base
37803 /* 105690 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37804 /* 105694 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37805 /* 105698 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37806 /* 105702 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37807 /* 105706 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37808 /* 105710 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37809 /* 105714 */ // (intrinsic_w_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37810 /* 105714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37811 /* 105717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37812 /* 105719 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37813 /* 105721 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37814 /* 105723 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37815 /* 105727 */ GIR_RootConstrainSelectedInstOperands,
37816 /* 105728 */ // GIR_Coverage, 5470,
37817 /* 105728 */ GIR_EraseRootFromParent_Done,
37818 /* 105729 */ // Label 1939: @105729
37819 /* 105729 */ GIM_Try, /*On fail goto*//*Label 1940*/ GIMT_Encode4(105797), // Rule ID 5473 //
37820 /* 105734 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37821 /* 105739 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37822 /* 105742 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37823 /* 105745 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37824 /* 105748 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37825 /* 105751 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37826 /* 105754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37827 /* 105758 */ // MIs[0] base
37828 /* 105758 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37829 /* 105762 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37830 /* 105766 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37831 /* 105770 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37832 /* 105774 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37833 /* 105778 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37834 /* 105782 */ // (intrinsic_w_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37835 /* 105782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37836 /* 105785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37837 /* 105787 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37838 /* 105789 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37839 /* 105791 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37840 /* 105795 */ GIR_RootConstrainSelectedInstOperands,
37841 /* 105796 */ // GIR_Coverage, 5473,
37842 /* 105796 */ GIR_EraseRootFromParent_Done,
37843 /* 105797 */ // Label 1940: @105797
37844 /* 105797 */ GIM_Try, /*On fail goto*//*Label 1941*/ GIMT_Encode4(105865), // Rule ID 5474 //
37845 /* 105802 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37846 /* 105807 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37847 /* 105810 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37848 /* 105813 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37849 /* 105816 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37850 /* 105819 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37851 /* 105822 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37852 /* 105826 */ // MIs[0] base
37853 /* 105826 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37854 /* 105830 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37855 /* 105834 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37856 /* 105838 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37857 /* 105842 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37858 /* 105846 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37859 /* 105850 */ // (intrinsic_w_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37860 /* 105850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37861 /* 105853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37862 /* 105855 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37863 /* 105857 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37864 /* 105859 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37865 /* 105863 */ GIR_RootConstrainSelectedInstOperands,
37866 /* 105864 */ // GIR_Coverage, 5474,
37867 /* 105864 */ GIR_EraseRootFromParent_Done,
37868 /* 105865 */ // Label 1941: @105865
37869 /* 105865 */ GIM_Try, /*On fail goto*//*Label 1942*/ GIMT_Encode4(105933), // Rule ID 5477 //
37870 /* 105870 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37871 /* 105875 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37872 /* 105878 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37873 /* 105881 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37874 /* 105884 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37875 /* 105887 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37876 /* 105890 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37877 /* 105894 */ // MIs[0] base
37878 /* 105894 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37879 /* 105898 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37880 /* 105902 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37881 /* 105906 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37882 /* 105910 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37883 /* 105914 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37884 /* 105918 */ // (intrinsic_w_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37885 /* 105918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37886 /* 105921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37887 /* 105923 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37888 /* 105925 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37889 /* 105927 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37890 /* 105931 */ GIR_RootConstrainSelectedInstOperands,
37891 /* 105932 */ // GIR_Coverage, 5477,
37892 /* 105932 */ GIR_EraseRootFromParent_Done,
37893 /* 105933 */ // Label 1942: @105933
37894 /* 105933 */ GIM_Try, /*On fail goto*//*Label 1943*/ GIMT_Encode4(106001), // Rule ID 5478 //
37895 /* 105938 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37896 /* 105943 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37897 /* 105946 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37898 /* 105949 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37899 /* 105952 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37900 /* 105955 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37901 /* 105958 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37902 /* 105962 */ // MIs[0] base
37903 /* 105962 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37904 /* 105966 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37905 /* 105970 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37906 /* 105974 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37907 /* 105978 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37908 /* 105982 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37909 /* 105986 */ // (intrinsic_w_chain:{ *:[v4i32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4i32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37910 /* 105986 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37911 /* 105989 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37912 /* 105991 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37913 /* 105993 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37914 /* 105995 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37915 /* 105999 */ GIR_RootConstrainSelectedInstOperands,
37916 /* 106000 */ // GIR_Coverage, 5478,
37917 /* 106000 */ GIR_EraseRootFromParent_Done,
37918 /* 106001 */ // Label 1943: @106001
37919 /* 106001 */ GIM_Try, /*On fail goto*//*Label 1944*/ GIMT_Encode4(106069), // Rule ID 5481 //
37920 /* 106006 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37921 /* 106011 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37922 /* 106014 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37923 /* 106017 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37924 /* 106020 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37925 /* 106023 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37926 /* 106026 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37927 /* 106030 */ // MIs[0] base
37928 /* 106030 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37929 /* 106034 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37930 /* 106038 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37931 /* 106042 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37932 /* 106046 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37933 /* 106050 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37934 /* 106054 */ // (intrinsic_w_chain:{ *:[v4f32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37935 /* 106054 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37936 /* 106057 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37937 /* 106059 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37938 /* 106061 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37939 /* 106063 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37940 /* 106067 */ GIR_RootConstrainSelectedInstOperands,
37941 /* 106068 */ // GIR_Coverage, 5481,
37942 /* 106068 */ GIR_EraseRootFromParent_Done,
37943 /* 106069 */ // Label 1944: @106069
37944 /* 106069 */ GIM_Try, /*On fail goto*//*Label 1945*/ GIMT_Encode4(106137), // Rule ID 5482 //
37945 /* 106074 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37946 /* 106079 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37947 /* 106082 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37948 /* 106085 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37949 /* 106088 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37950 /* 106091 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37951 /* 106094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37952 /* 106098 */ // MIs[0] base
37953 /* 106098 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37954 /* 106102 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37955 /* 106106 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37956 /* 106110 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37957 /* 106114 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
37958 /* 106118 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
37959 /* 106122 */ // (intrinsic_w_chain:{ *:[v4f32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37960 /* 106122 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
37961 /* 106125 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37962 /* 106127 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37963 /* 106129 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37964 /* 106131 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37965 /* 106135 */ GIR_RootConstrainSelectedInstOperands,
37966 /* 106136 */ // GIR_Coverage, 5482,
37967 /* 106136 */ GIR_EraseRootFromParent_Done,
37968 /* 106137 */ // Label 1945: @106137
37969 /* 106137 */ GIM_Try, /*On fail goto*//*Label 1946*/ GIMT_Encode4(106205), // Rule ID 5485 //
37970 /* 106142 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37971 /* 106147 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37972 /* 106150 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37973 /* 106153 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37974 /* 106156 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
37975 /* 106159 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
37976 /* 106162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37977 /* 106166 */ // MIs[0] base
37978 /* 106166 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
37979 /* 106170 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
37980 /* 106174 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
37981 /* 106178 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
37982 /* 106182 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
37983 /* 106186 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
37984 /* 106190 */ // (intrinsic_w_chain:{ *:[v4f32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq_u:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
37985 /* 106190 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq_u),
37986 /* 106193 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
37987 /* 106195 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
37988 /* 106197 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
37989 /* 106199 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
37990 /* 106203 */ GIR_RootConstrainSelectedInstOperands,
37991 /* 106204 */ // GIR_Coverage, 5485,
37992 /* 106204 */ GIR_EraseRootFromParent_Done,
37993 /* 106205 */ // Label 1946: @106205
37994 /* 106205 */ GIM_Try, /*On fail goto*//*Label 1947*/ GIMT_Encode4(106273), // Rule ID 5486 //
37995 /* 106210 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
37996 /* 106215 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32,
37997 /* 106218 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
37998 /* 106221 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
37999 /* 106224 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
38000 /* 106227 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
38001 /* 106230 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38002 /* 106234 */ // MIs[0] base
38003 /* 106234 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
38004 /* 106238 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38005 /* 106242 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38006 /* 106246 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 32,
38007 /* 106250 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 2,
38008 /* 106254 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
38009 /* 106258 */ // (intrinsic_w_chain:{ *:[v4f32] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets, 32:{ *:[i32] }, 2:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRWU32_rq:{ *:[v4f32] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v4i32] }:$offsets)
38010 /* 106258 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRWU32_rq),
38011 /* 106261 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38012 /* 106263 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
38013 /* 106265 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
38014 /* 106267 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38015 /* 106271 */ GIR_RootConstrainSelectedInstOperands,
38016 /* 106272 */ // GIR_Coverage, 5486,
38017 /* 106272 */ GIR_EraseRootFromParent_Done,
38018 /* 106273 */ // Label 1947: @106273
38019 /* 106273 */ GIM_Try, /*On fail goto*//*Label 1948*/ GIMT_Encode4(106341), // Rule ID 5489 //
38020 /* 106278 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
38021 /* 106283 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
38022 /* 106286 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
38023 /* 106289 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
38024 /* 106292 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
38025 /* 106295 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
38026 /* 106298 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38027 /* 106302 */ // MIs[0] base
38028 /* 106302 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
38029 /* 106306 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38030 /* 106310 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38031 /* 106314 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
38032 /* 106318 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
38033 /* 106322 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
38034 /* 106326 */ // (intrinsic_w_chain:{ *:[v2i64] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
38035 /* 106326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
38036 /* 106329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38037 /* 106331 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
38038 /* 106333 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
38039 /* 106335 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38040 /* 106339 */ GIR_RootConstrainSelectedInstOperands,
38041 /* 106340 */ // GIR_Coverage, 5489,
38042 /* 106340 */ GIR_EraseRootFromParent_Done,
38043 /* 106341 */ // Label 1948: @106341
38044 /* 106341 */ GIM_Try, /*On fail goto*//*Label 1949*/ GIMT_Encode4(106409), // Rule ID 5490 //
38045 /* 106346 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
38046 /* 106351 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
38047 /* 106354 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
38048 /* 106357 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
38049 /* 106360 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
38050 /* 106363 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
38051 /* 106366 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38052 /* 106370 */ // MIs[0] base
38053 /* 106370 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
38054 /* 106374 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38055 /* 106378 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38056 /* 106382 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
38057 /* 106386 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
38058 /* 106390 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
38059 /* 106394 */ // (intrinsic_w_chain:{ *:[v2i64] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
38060 /* 106394 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
38061 /* 106397 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38062 /* 106399 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
38063 /* 106401 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
38064 /* 106403 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38065 /* 106407 */ GIR_RootConstrainSelectedInstOperands,
38066 /* 106408 */ // GIR_Coverage, 5490,
38067 /* 106408 */ GIR_EraseRootFromParent_Done,
38068 /* 106409 */ // Label 1949: @106409
38069 /* 106409 */ GIM_Try, /*On fail goto*//*Label 1950*/ GIMT_Encode4(106477), // Rule ID 5493 //
38070 /* 106414 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
38071 /* 106419 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
38072 /* 106422 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
38073 /* 106425 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
38074 /* 106428 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
38075 /* 106431 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
38076 /* 106434 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38077 /* 106438 */ // MIs[0] base
38078 /* 106438 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
38079 /* 106442 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38080 /* 106446 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38081 /* 106450 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
38082 /* 106454 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
38083 /* 106458 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
38084 /* 106462 */ // (intrinsic_w_chain:{ *:[v2i64] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
38085 /* 106462 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
38086 /* 106465 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38087 /* 106467 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
38088 /* 106469 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
38089 /* 106471 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38090 /* 106475 */ GIR_RootConstrainSelectedInstOperands,
38091 /* 106476 */ // GIR_Coverage, 5493,
38092 /* 106476 */ GIR_EraseRootFromParent_Done,
38093 /* 106477 */ // Label 1950: @106477
38094 /* 106477 */ GIM_Try, /*On fail goto*//*Label 1951*/ GIMT_Encode4(106545), // Rule ID 5494 //
38095 /* 106482 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
38096 /* 106487 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
38097 /* 106490 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
38098 /* 106493 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
38099 /* 106496 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
38100 /* 106499 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
38101 /* 106502 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38102 /* 106506 */ // MIs[0] base
38103 /* 106506 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
38104 /* 106510 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38105 /* 106514 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38106 /* 106518 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
38107 /* 106522 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
38108 /* 106526 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
38109 /* 106530 */ // (intrinsic_w_chain:{ *:[v2i64] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
38110 /* 106530 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
38111 /* 106533 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38112 /* 106535 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
38113 /* 106537 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
38114 /* 106539 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38115 /* 106543 */ GIR_RootConstrainSelectedInstOperands,
38116 /* 106544 */ // GIR_Coverage, 5494,
38117 /* 106544 */ GIR_EraseRootFromParent_Done,
38118 /* 106545 */ // Label 1951: @106545
38119 /* 106545 */ GIM_Try, /*On fail goto*//*Label 1952*/ GIMT_Encode4(106613), // Rule ID 5497 //
38120 /* 106550 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
38121 /* 106555 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
38122 /* 106558 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
38123 /* 106561 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
38124 /* 106564 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
38125 /* 106567 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
38126 /* 106570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38127 /* 106574 */ // MIs[0] base
38128 /* 106574 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
38129 /* 106578 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38130 /* 106582 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38131 /* 106586 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
38132 /* 106590 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
38133 /* 106594 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
38134 /* 106598 */ // (intrinsic_w_chain:{ *:[v2i64] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
38135 /* 106598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
38136 /* 106601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38137 /* 106603 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
38138 /* 106605 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
38139 /* 106607 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38140 /* 106611 */ GIR_RootConstrainSelectedInstOperands,
38141 /* 106612 */ // GIR_Coverage, 5497,
38142 /* 106612 */ GIR_EraseRootFromParent_Done,
38143 /* 106613 */ // Label 1952: @106613
38144 /* 106613 */ GIM_Try, /*On fail goto*//*Label 1953*/ GIMT_Encode4(106681), // Rule ID 5498 //
38145 /* 106618 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
38146 /* 106623 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
38147 /* 106626 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
38148 /* 106629 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
38149 /* 106632 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
38150 /* 106635 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
38151 /* 106638 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38152 /* 106642 */ // MIs[0] base
38153 /* 106642 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
38154 /* 106646 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38155 /* 106650 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38156 /* 106654 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
38157 /* 106658 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
38158 /* 106662 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 0,
38159 /* 106666 */ // (intrinsic_w_chain:{ *:[v2i64] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 0:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
38160 /* 106666 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
38161 /* 106669 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38162 /* 106671 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
38163 /* 106673 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
38164 /* 106675 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38165 /* 106679 */ GIR_RootConstrainSelectedInstOperands,
38166 /* 106680 */ // GIR_Coverage, 5498,
38167 /* 106680 */ GIR_EraseRootFromParent_Done,
38168 /* 106681 */ // Label 1953: @106681
38169 /* 106681 */ GIM_Try, /*On fail goto*//*Label 1954*/ GIMT_Encode4(106749), // Rule ID 5501 //
38170 /* 106686 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
38171 /* 106691 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
38172 /* 106694 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
38173 /* 106697 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
38174 /* 106700 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
38175 /* 106703 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
38176 /* 106706 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38177 /* 106710 */ // MIs[0] base
38178 /* 106710 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
38179 /* 106714 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38180 /* 106718 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38181 /* 106722 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
38182 /* 106726 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0,
38183 /* 106730 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
38184 /* 106734 */ // (intrinsic_w_chain:{ *:[v2i64] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq_u:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
38185 /* 106734 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq_u),
38186 /* 106737 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38187 /* 106739 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
38188 /* 106741 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
38189 /* 106743 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38190 /* 106747 */ GIR_RootConstrainSelectedInstOperands,
38191 /* 106748 */ // GIR_Coverage, 5501,
38192 /* 106748 */ GIR_EraseRootFromParent_Done,
38193 /* 106749 */ // Label 1954: @106749
38194 /* 106749 */ GIM_Try, /*On fail goto*//*Label 1955*/ GIMT_Encode4(106817), // Rule ID 5502 //
38195 /* 106754 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::arm_mve_vldr_gather_offset),
38196 /* 106759 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s64,
38197 /* 106762 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s64,
38198 /* 106765 */ GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32,
38199 /* 106768 */ GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32,
38200 /* 106771 */ GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32,
38201 /* 106774 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38202 /* 106778 */ // MIs[0] base
38203 /* 106778 */ GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
38204 /* 106782 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38205 /* 106786 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38206 /* 106790 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 64,
38207 /* 106794 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 3,
38208 /* 106798 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/6, 1,
38209 /* 106802 */ // (intrinsic_w_chain:{ *:[v2i64] } 3880:{ *:[iPTR] }, GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets, 64:{ *:[i32] }, 3:{ *:[i32] }, 1:{ *:[i32] }) => (MVE_VLDRDU64_rq:{ *:[v2i64] } GPR:{ *:[i32] }:$base, MQPR:{ *:[v2i64] }:$offsets)
38210 /* 106802 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VLDRDU64_rq),
38211 /* 106805 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38212 /* 106807 */ GIR_RootToRootCopy, /*OpIdx*/2, // base
38213 /* 106809 */ GIR_RootToRootCopy, /*OpIdx*/3, // offsets
38214 /* 106811 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38215 /* 106815 */ GIR_RootConstrainSelectedInstOperands,
38216 /* 106816 */ // GIR_Coverage, 5502,
38217 /* 106816 */ GIR_EraseRootFromParent_Done,
38218 /* 106817 */ // Label 1955: @106817
38219 /* 106817 */ GIM_Try, /*On fail goto*//*Label 1956*/ GIMT_Encode4(106882), // Rule ID 255 //
38220 /* 106822 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
38221 /* 106825 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr),
38222 /* 106830 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
38223 /* 106833 */ // MIs[0] cop
38224 /* 106833 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
38225 /* 106836 */ // MIs[0] opc1
38226 /* 106836 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
38227 /* 106839 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38228 /* 106843 */ // MIs[0] CRn
38229 /* 106843 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
38230 /* 106846 */ // MIs[0] CRm
38231 /* 106846 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
38232 /* 106849 */ // MIs[0] opc2
38233 /* 106849 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
38234 /* 106852 */ // (intrinsic_void 3745:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
38235 /* 106852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR),
38236 /* 106855 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
38237 /* 106857 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
38238 /* 106859 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
38239 /* 106861 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
38240 /* 106863 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
38241 /* 106865 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
38242 /* 106867 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38243 /* 106870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38244 /* 106876 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38245 /* 106880 */ GIR_RootConstrainSelectedInstOperands,
38246 /* 106881 */ // GIR_Coverage, 255,
38247 /* 106881 */ GIR_EraseRootFromParent_Done,
38248 /* 106882 */ // Label 1956: @106882
38249 /* 106882 */ GIM_Try, /*On fail goto*//*Label 1957*/ GIMT_Encode4(106938), // Rule ID 256 //
38250 /* 106887 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_PreV8),
38251 /* 106890 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2),
38252 /* 106895 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
38253 /* 106898 */ // MIs[0] cop
38254 /* 106898 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
38255 /* 106901 */ // MIs[0] opc1
38256 /* 106901 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
38257 /* 106904 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38258 /* 106908 */ // MIs[0] CRn
38259 /* 106908 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
38260 /* 106911 */ // MIs[0] CRm
38261 /* 106911 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
38262 /* 106914 */ // MIs[0] opc2
38263 /* 106914 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
38264 /* 106917 */ // (intrinsic_void 3746:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
38265 /* 106917 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MCR2),
38266 /* 106920 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
38267 /* 106922 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
38268 /* 106924 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
38269 /* 106926 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
38270 /* 106928 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
38271 /* 106930 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
38272 /* 106932 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38273 /* 106936 */ GIR_RootConstrainSelectedInstOperands,
38274 /* 106937 */ // GIR_Coverage, 256,
38275 /* 106937 */ GIR_EraseRootFromParent_Done,
38276 /* 106938 */ // Label 1957: @106938
38277 /* 106938 */ GIM_Try, /*On fail goto*//*Label 1958*/ GIMT_Encode4(107003), // Rule ID 593 //
38278 /* 106943 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38279 /* 106946 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr),
38280 /* 106951 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
38281 /* 106954 */ // MIs[0] cop
38282 /* 106954 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
38283 /* 106957 */ // MIs[0] opc1
38284 /* 106957 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
38285 /* 106960 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38286 /* 106964 */ // MIs[0] CRn
38287 /* 106964 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
38288 /* 106967 */ // MIs[0] CRm
38289 /* 106967 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
38290 /* 106970 */ // MIs[0] opc2
38291 /* 106970 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
38292 /* 106973 */ // (intrinsic_void 3745:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
38293 /* 106973 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR),
38294 /* 106976 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
38295 /* 106978 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
38296 /* 106980 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
38297 /* 106982 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
38298 /* 106984 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
38299 /* 106986 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
38300 /* 106988 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38301 /* 106991 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38302 /* 106997 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38303 /* 107001 */ GIR_RootConstrainSelectedInstOperands,
38304 /* 107002 */ // GIR_Coverage, 593,
38305 /* 107002 */ GIR_EraseRootFromParent_Done,
38306 /* 107003 */ // Label 1958: @107003
38307 /* 107003 */ GIM_Try, /*On fail goto*//*Label 1959*/ GIMT_Encode4(107068), // Rule ID 594 //
38308 /* 107008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2_PreV8),
38309 /* 107011 */ GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::arm_mcr2),
38310 /* 107016 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
38311 /* 107019 */ // MIs[0] cop
38312 /* 107019 */ GIM_CheckIsImm, /*MI*/0, /*Op*/1,
38313 /* 107022 */ // MIs[0] opc1
38314 /* 107022 */ GIM_CheckIsImm, /*MI*/0, /*Op*/2,
38315 /* 107025 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38316 /* 107029 */ // MIs[0] CRn
38317 /* 107029 */ GIM_CheckIsImm, /*MI*/0, /*Op*/4,
38318 /* 107032 */ // MIs[0] CRm
38319 /* 107032 */ GIM_CheckIsImm, /*MI*/0, /*Op*/5,
38320 /* 107035 */ // MIs[0] opc2
38321 /* 107035 */ GIM_CheckIsImm, /*MI*/0, /*Op*/6,
38322 /* 107038 */ // (intrinsic_void 3746:{ *:[iPTR] }, (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2) => (t2MCR2 (timm:{ *:[i32] }):$cop, (timm:{ *:[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, (timm:{ *:[i32] }):$CRn, (timm:{ *:[i32] }):$CRm, (timm:{ *:[i32] }):$opc2)
38323 /* 107038 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MCR2),
38324 /* 107041 */ GIR_RootToRootCopy, /*OpIdx*/1, // cop
38325 /* 107043 */ GIR_RootToRootCopy, /*OpIdx*/2, // opc1
38326 /* 107045 */ GIR_RootToRootCopy, /*OpIdx*/3, // Rt
38327 /* 107047 */ GIR_RootToRootCopy, /*OpIdx*/4, // CRn
38328 /* 107049 */ GIR_RootToRootCopy, /*OpIdx*/5, // CRm
38329 /* 107051 */ GIR_RootToRootCopy, /*OpIdx*/6, // opc2
38330 /* 107053 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38331 /* 107056 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38332 /* 107062 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
38333 /* 107066 */ GIR_RootConstrainSelectedInstOperands,
38334 /* 107067 */ // GIR_Coverage, 594,
38335 /* 107067 */ GIR_EraseRootFromParent_Done,
38336 /* 107068 */ // Label 1959: @107068
38337 /* 107068 */ GIM_Reject,
38338 /* 107069 */ // Label 1909: @107069
38339 /* 107069 */ GIM_Reject,
38340 /* 107070 */ // Label 23: @107070
38341 /* 107070 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(13), /*)*//*default:*//*Label 1963*/ GIMT_Encode4(107227),
38342 /* 107081 */ /*GILLT_v2s64*//*Label 1960*/ GIMT_Encode4(107113), GIMT_Encode4(0), GIMT_Encode4(0),
38343 /* 107093 */ /*GILLT_v4s32*//*Label 1961*/ GIMT_Encode4(107151), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38344 /* 107109 */ /*GILLT_v8s16*//*Label 1962*/ GIMT_Encode4(107189),
38345 /* 107113 */ // Label 1960: @107113
38346 /* 107113 */ GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(107150), // Rule ID 3018 //
38347 /* 107118 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38348 /* 107121 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
38349 /* 107124 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38350 /* 107128 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38351 /* 107132 */ // (anyext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
38352 /* 107132 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64),
38353 /* 107135 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38354 /* 107137 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38355 /* 107139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38356 /* 107142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38357 /* 107148 */ GIR_RootConstrainSelectedInstOperands,
38358 /* 107149 */ // GIR_Coverage, 3018,
38359 /* 107149 */ GIR_EraseRootFromParent_Done,
38360 /* 107150 */ // Label 1964: @107150
38361 /* 107150 */ GIM_Reject,
38362 /* 107151 */ // Label 1961: @107151
38363 /* 107151 */ GIM_Try, /*On fail goto*//*Label 1965*/ GIMT_Encode4(107188), // Rule ID 3017 //
38364 /* 107156 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38365 /* 107159 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
38366 /* 107162 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38367 /* 107166 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38368 /* 107170 */ // (anyext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
38369 /* 107170 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32),
38370 /* 107173 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38371 /* 107175 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38372 /* 107177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38373 /* 107180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38374 /* 107186 */ GIR_RootConstrainSelectedInstOperands,
38375 /* 107187 */ // GIR_Coverage, 3017,
38376 /* 107187 */ GIR_EraseRootFromParent_Done,
38377 /* 107188 */ // Label 1965: @107188
38378 /* 107188 */ GIM_Reject,
38379 /* 107189 */ // Label 1962: @107189
38380 /* 107189 */ GIM_Try, /*On fail goto*//*Label 1966*/ GIMT_Encode4(107226), // Rule ID 3016 //
38381 /* 107194 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38382 /* 107197 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
38383 /* 107200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38384 /* 107204 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38385 /* 107208 */ // (anyext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
38386 /* 107208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16),
38387 /* 107211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38388 /* 107213 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38389 /* 107215 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38390 /* 107218 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38391 /* 107224 */ GIR_RootConstrainSelectedInstOperands,
38392 /* 107225 */ // GIR_Coverage, 3016,
38393 /* 107225 */ GIR_EraseRootFromParent_Done,
38394 /* 107226 */ // Label 1966: @107226
38395 /* 107226 */ GIM_Reject,
38396 /* 107227 */ // Label 1963: @107227
38397 /* 107227 */ GIM_Reject,
38398 /* 107228 */ // Label 24: @107228
38399 /* 107228 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(12), /*)*//*default:*//*Label 1970*/ GIMT_Encode4(107385),
38400 /* 107239 */ /*GILLT_v2s32*//*Label 1967*/ GIMT_Encode4(107271), GIMT_Encode4(0), GIMT_Encode4(0),
38401 /* 107251 */ /*GILLT_v4s16*//*Label 1968*/ GIMT_Encode4(107309), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38402 /* 107267 */ /*GILLT_v8s8*//*Label 1969*/ GIMT_Encode4(107347),
38403 /* 107271 */ // Label 1967: @107271
38404 /* 107271 */ GIM_Try, /*On fail goto*//*Label 1971*/ GIMT_Encode4(107308), // Rule ID 1749 //
38405 /* 107276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38406 /* 107279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
38407 /* 107282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38408 /* 107286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38409 /* 107290 */ // (trunc:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm) => (VMOVNv2i32:{ *:[v2i32] } QPR:{ *:[v2i64] }:$Vm)
38410 /* 107290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv2i32),
38411 /* 107293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38412 /* 107295 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38413 /* 107297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38414 /* 107300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38415 /* 107306 */ GIR_RootConstrainSelectedInstOperands,
38416 /* 107307 */ // GIR_Coverage, 1749,
38417 /* 107307 */ GIR_EraseRootFromParent_Done,
38418 /* 107308 */ // Label 1971: @107308
38419 /* 107308 */ GIM_Reject,
38420 /* 107309 */ // Label 1968: @107309
38421 /* 107309 */ GIM_Try, /*On fail goto*//*Label 1972*/ GIMT_Encode4(107346), // Rule ID 1748 //
38422 /* 107314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38423 /* 107317 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
38424 /* 107320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38425 /* 107324 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38426 /* 107328 */ // (trunc:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm) => (VMOVNv4i16:{ *:[v4i16] } QPR:{ *:[v4i32] }:$Vm)
38427 /* 107328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv4i16),
38428 /* 107331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38429 /* 107333 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38430 /* 107335 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38431 /* 107338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38432 /* 107344 */ GIR_RootConstrainSelectedInstOperands,
38433 /* 107345 */ // GIR_Coverage, 1748,
38434 /* 107345 */ GIR_EraseRootFromParent_Done,
38435 /* 107346 */ // Label 1972: @107346
38436 /* 107346 */ GIM_Reject,
38437 /* 107347 */ // Label 1969: @107347
38438 /* 107347 */ GIM_Try, /*On fail goto*//*Label 1973*/ GIMT_Encode4(107384), // Rule ID 1747 //
38439 /* 107352 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38440 /* 107355 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
38441 /* 107358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38442 /* 107362 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38443 /* 107366 */ // (trunc:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm) => (VMOVNv8i8:{ *:[v8i8] } QPR:{ *:[v8i16] }:$Vm)
38444 /* 107366 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVNv8i8),
38445 /* 107369 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38446 /* 107371 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38447 /* 107373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38448 /* 107376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38449 /* 107382 */ GIR_RootConstrainSelectedInstOperands,
38450 /* 107383 */ // GIR_Coverage, 1747,
38451 /* 107383 */ GIR_EraseRootFromParent_Done,
38452 /* 107384 */ // Label 1973: @107384
38453 /* 107384 */ GIM_Reject,
38454 /* 107385 */ // Label 1970: @107385
38455 /* 107385 */ GIM_Reject,
38456 /* 107386 */ // Label 25: @107386
38457 /* 107386 */ GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(107706),
38458 /* 107391 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
38459 /* 107394 */ GIM_Try, /*On fail goto*//*Label 1975*/ GIMT_Encode4(107435), // Rule ID 403 //
38460 /* 107399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38461 /* 107402 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_t2_so_imm),
38462 /* 107406 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38463 /* 107410 */ // MIs[0] Operand 1
38464 /* 107410 */ // No operand predicates
38465 /* 107410 */ // (imm:{ *:[i32] })<<P:Predicate_t2_so_imm>>:$imm => (t2MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38466 /* 107410 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
38467 /* 107413 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38468 /* 107415 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38469 /* 107418 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38470 /* 107421 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38471 /* 107427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38472 /* 107433 */ GIR_RootConstrainSelectedInstOperands,
38473 /* 107434 */ // GIR_Coverage, 403,
38474 /* 107434 */ GIR_EraseRootFromParent_Done,
38475 /* 107435 */ // Label 1975: @107435
38476 /* 107435 */ GIM_Try, /*On fail goto*//*Label 1976*/ GIMT_Encode4(107476), // Rule ID 56 //
38477 /* 107440 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
38478 /* 107443 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm),
38479 /* 107447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38480 /* 107451 */ // MIs[0] Operand 1
38481 /* 107451 */ // No operand predicates
38482 /* 107451 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm>>:$imm => (MOVi:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38483 /* 107451 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi),
38484 /* 107454 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38485 /* 107456 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38486 /* 107459 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38487 /* 107462 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38488 /* 107468 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38489 /* 107474 */ GIR_RootConstrainSelectedInstOperands,
38490 /* 107475 */ // GIR_Coverage, 56,
38491 /* 107475 */ GIR_EraseRootFromParent_Done,
38492 /* 107476 */ // Label 1976: @107476
38493 /* 107476 */ GIM_Try, /*On fail goto*//*Label 1977*/ GIMT_Encode4(107511), // Rule ID 57 //
38494 /* 107481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM),
38495 /* 107484 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
38496 /* 107488 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38497 /* 107492 */ // MIs[0] Operand 1
38498 /* 107492 */ // No operand predicates
38499 /* 107492 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38500 /* 107492 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi16),
38501 /* 107495 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38502 /* 107497 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38503 /* 107500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38504 /* 107503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38505 /* 107509 */ GIR_RootConstrainSelectedInstOperands,
38506 /* 107510 */ // GIR_Coverage, 57,
38507 /* 107510 */ GIR_EraseRootFromParent_Done,
38508 /* 107511 */ // Label 1977: @107511
38509 /* 107511 */ GIM_Try, /*On fail goto*//*Label 1978*/ GIMT_Encode4(107554), // Rule ID 167 //
38510 /* 107516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
38511 /* 107519 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_mod_imm_not),
38512 /* 107523 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38513 /* 107527 */ // MIs[0] Operand 1
38514 /* 107527 */ // No operand predicates
38515 /* 107527 */ // (imm:{ *:[i32] })<<P:Predicate_mod_imm_not>><<X:imm_not_XFORM>>:$imm => (MVNi:{ *:[i32] } (imm_not_XFORM:{ *:[i32] } (imm:{ *:[i32] }):$imm))
38516 /* 107527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVNi),
38517 /* 107530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38518 /* 107532 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderInvertedImm), // imm
38519 /* 107537 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38520 /* 107540 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38521 /* 107546 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38522 /* 107552 */ GIR_RootConstrainSelectedInstOperands,
38523 /* 107553 */ // GIR_Coverage, 167,
38524 /* 107553 */ GIR_EraseRootFromParent_Done,
38525 /* 107554 */ // Label 1978: @107554
38526 /* 107554 */ GIM_Try, /*On fail goto*//*Label 1979*/ GIMT_Encode4(107580), // Rule ID 267 //
38527 /* 107559 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
38528 /* 107562 */ GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_arm_i32imm),
38529 /* 107566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38530 /* 107570 */ // MIs[0] Operand 1
38531 /* 107570 */ // No operand predicates
38532 /* 107570 */ // (imm:{ *:[i32] })<<P:Predicate_arm_i32imm>>:$src => (MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
38533 /* 107570 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MOVi32imm),
38534 /* 107573 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38535 /* 107575 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
38536 /* 107578 */ GIR_RootConstrainSelectedInstOperands,
38537 /* 107579 */ // GIR_Coverage, 267,
38538 /* 107579 */ GIR_EraseRootFromParent_Done,
38539 /* 107580 */ // Label 1979: @107580
38540 /* 107580 */ GIM_Try, /*On fail goto*//*Label 1980*/ GIMT_Encode4(107621), // Rule ID 321 //
38541 /* 107585 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
38542 /* 107588 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_255_expr),
38543 /* 107592 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38544 /* 107596 */ // MIs[0] Operand 1
38545 /* 107596 */ // No operand predicates
38546 /* 107596 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_255_expr>>:$imm8 => (tMOVi8:{ *:[i32] } (imm:{ *:[i32] }):$imm8)
38547 /* 107596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
38548 /* 107599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38549 /* 107601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
38550 /* 107607 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm8
38551 /* 107610 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38552 /* 107613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38553 /* 107619 */ GIR_RootConstrainSelectedInstOperands,
38554 /* 107620 */ // GIR_Coverage, 321,
38555 /* 107620 */ GIR_EraseRootFromParent_Done,
38556 /* 107621 */ // Label 1980: @107621
38557 /* 107621 */ GIM_Try, /*On fail goto*//*Label 1981*/ GIMT_Encode4(107656), // Rule ID 404 //
38558 /* 107626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb),
38559 /* 107629 */ GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm0_65535),
38560 /* 107633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38561 /* 107637 */ // MIs[0] Operand 1
38562 /* 107637 */ // No operand predicates
38563 /* 107637 */ // (imm:{ *:[i32] })<<P:Predicate_imm0_65535>>:$imm => (t2MOVi16:{ *:[i32] } (imm:{ *:[i32] }):$imm)
38564 /* 107637 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16),
38565 /* 107640 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38566 /* 107642 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm
38567 /* 107645 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38568 /* 107648 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38569 /* 107654 */ GIR_RootConstrainSelectedInstOperands,
38570 /* 107655 */ // GIR_Coverage, 404,
38571 /* 107655 */ GIR_EraseRootFromParent_Done,
38572 /* 107656 */ // Label 1981: @107656
38573 /* 107656 */ GIM_Try, /*On fail goto*//*Label 1982*/ GIMT_Encode4(107705),
38574 /* 107661 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38575 /* 107665 */ GIM_Try, /*On fail goto*//*Label 1983*/ GIMT_Encode4(107686), // Rule ID 352 //
38576 /* 107670 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseMovt_GenExecuteOnly_IsThumb1Only),
38577 /* 107673 */ // MIs[0] Operand 1
38578 /* 107673 */ // No operand predicates
38579 /* 107673 */ // (imm:{ *:[i32] }):$src => (tMOVi32imm:{ *:[i32] }:{ *:[i32] } (imm:{ *:[i32] }):$src)
38580 /* 107673 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tMOVi32imm),
38581 /* 107676 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38582 /* 107678 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
38583 /* 107681 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::CPSR*/0,
38584 /* 107684 */ GIR_RootConstrainSelectedInstOperands,
38585 /* 107685 */ // GIR_Coverage, 352,
38586 /* 107685 */ GIR_EraseRootFromParent_Done,
38587 /* 107686 */ // Label 1983: @107686
38588 /* 107686 */ GIM_Try, /*On fail goto*//*Label 1984*/ GIMT_Encode4(107704), // Rule ID 581 //
38589 /* 107691 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_UseMovt),
38590 /* 107694 */ // MIs[0] Operand 1
38591 /* 107694 */ // No operand predicates
38592 /* 107694 */ // (imm:{ *:[i32] }):$src => (t2MOVi32imm:{ *:[i32] } (imm:{ *:[i32] }):$src)
38593 /* 107694 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm),
38594 /* 107697 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
38595 /* 107699 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // src
38596 /* 107702 */ GIR_RootConstrainSelectedInstOperands,
38597 /* 107703 */ // GIR_Coverage, 581,
38598 /* 107703 */ GIR_EraseRootFromParent_Done,
38599 /* 107704 */ // Label 1984: @107704
38600 /* 107704 */ GIM_Reject,
38601 /* 107705 */ // Label 1982: @107705
38602 /* 107705 */ GIM_Reject,
38603 /* 107706 */ // Label 1974: @107706
38604 /* 107706 */ GIM_Reject,
38605 /* 107707 */ // Label 26: @107707
38606 /* 107707 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(3), /*)*//*default:*//*Label 1987*/ GIMT_Encode4(107802),
38607 /* 107718 */ /*GILLT_s32*//*Label 1985*/ GIMT_Encode4(107726),
38608 /* 107722 */ /*GILLT_s64*//*Label 1986*/ GIMT_Encode4(107764),
38609 /* 107726 */ // Label 1985: @107726
38610 /* 107726 */ GIM_Try, /*On fail goto*//*Label 1988*/ GIMT_Encode4(107763), // Rule ID 847 //
38611 /* 107731 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP3),
38612 /* 107734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
38613 /* 107738 */ // MIs[0] Operand 1
38614 /* 107738 */ // No operand predicates
38615 /* 107738 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f32imm),
38616 /* 107742 */ // (fpimm:{ *:[f32] })<<P:Predicate_vfp_f32imm>><<X:vfp_f32imm_xform>>:$imm => (FCONSTS:{ *:[f32] } (vfp_f32imm_xform:{ *:[f32] } (fpimm:{ *:[f32] }):$imm))
38617 /* 107742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTS),
38618 /* 107745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
38619 /* 107747 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF32Imm), // imm
38620 /* 107752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38621 /* 107755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38622 /* 107761 */ GIR_RootConstrainSelectedInstOperands,
38623 /* 107762 */ // GIR_Coverage, 847,
38624 /* 107762 */ GIR_EraseRootFromParent_Done,
38625 /* 107763 */ // Label 1988: @107763
38626 /* 107763 */ GIM_Reject,
38627 /* 107764 */ // Label 1986: @107764
38628 /* 107764 */ GIM_Try, /*On fail goto*//*Label 1989*/ GIMT_Encode4(107801), // Rule ID 846 //
38629 /* 107769 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP3),
38630 /* 107772 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38631 /* 107776 */ // MIs[0] Operand 1
38632 /* 107776 */ // No operand predicates
38633 /* 107776 */ GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_vfp_f64imm),
38634 /* 107780 */ // (fpimm:{ *:[f64] })<<P:Predicate_vfp_f64imm>><<X:vfp_f64imm_xform>>:$imm => (FCONSTD:{ *:[f64] } (vfp_f64imm_xform:{ *:[f64] } (fpimm:{ *:[f64] }):$imm))
38635 /* 107780 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::FCONSTD),
38636 /* 107783 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
38637 /* 107785 */ GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderVFPF64Imm), // imm
38638 /* 107790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38639 /* 107793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38640 /* 107799 */ GIR_RootConstrainSelectedInstOperands,
38641 /* 107800 */ // GIR_Coverage, 846,
38642 /* 107800 */ GIR_EraseRootFromParent_Done,
38643 /* 107801 */ // Label 1989: @107801
38644 /* 107801 */ GIM_Reject,
38645 /* 107802 */ // Label 1987: @107802
38646 /* 107802 */ GIM_Reject,
38647 /* 107803 */ // Label 27: @107803
38648 /* 107803 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(13), /*)*//*default:*//*Label 1993*/ GIMT_Encode4(107960),
38649 /* 107814 */ /*GILLT_v2s64*//*Label 1990*/ GIMT_Encode4(107846), GIMT_Encode4(0), GIMT_Encode4(0),
38650 /* 107826 */ /*GILLT_v4s32*//*Label 1991*/ GIMT_Encode4(107884), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38651 /* 107842 */ /*GILLT_v8s16*//*Label 1992*/ GIMT_Encode4(107922),
38652 /* 107846 */ // Label 1990: @107846
38653 /* 107846 */ GIM_Try, /*On fail goto*//*Label 1994*/ GIMT_Encode4(107883), // Rule ID 1761 //
38654 /* 107851 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38655 /* 107854 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
38656 /* 107857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38657 /* 107861 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38658 /* 107865 */ // (sext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
38659 /* 107865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv2i64),
38660 /* 107868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38661 /* 107870 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38662 /* 107872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38663 /* 107875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38664 /* 107881 */ GIR_RootConstrainSelectedInstOperands,
38665 /* 107882 */ // GIR_Coverage, 1761,
38666 /* 107882 */ GIR_EraseRootFromParent_Done,
38667 /* 107883 */ // Label 1994: @107883
38668 /* 107883 */ GIM_Reject,
38669 /* 107884 */ // Label 1991: @107884
38670 /* 107884 */ GIM_Try, /*On fail goto*//*Label 1995*/ GIMT_Encode4(107921), // Rule ID 1760 //
38671 /* 107889 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38672 /* 107892 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
38673 /* 107895 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38674 /* 107899 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38675 /* 107903 */ // (sext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
38676 /* 107903 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv4i32),
38677 /* 107906 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38678 /* 107908 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38679 /* 107910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38680 /* 107913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38681 /* 107919 */ GIR_RootConstrainSelectedInstOperands,
38682 /* 107920 */ // GIR_Coverage, 1760,
38683 /* 107920 */ GIR_EraseRootFromParent_Done,
38684 /* 107921 */ // Label 1995: @107921
38685 /* 107921 */ GIM_Reject,
38686 /* 107922 */ // Label 1992: @107922
38687 /* 107922 */ GIM_Try, /*On fail goto*//*Label 1996*/ GIMT_Encode4(107959), // Rule ID 1759 //
38688 /* 107927 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38689 /* 107930 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
38690 /* 107933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38691 /* 107937 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38692 /* 107941 */ // (sext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
38693 /* 107941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLsv8i16),
38694 /* 107944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38695 /* 107946 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38696 /* 107948 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38697 /* 107951 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38698 /* 107957 */ GIR_RootConstrainSelectedInstOperands,
38699 /* 107958 */ // GIR_Coverage, 1759,
38700 /* 107958 */ GIR_EraseRootFromParent_Done,
38701 /* 107959 */ // Label 1996: @107959
38702 /* 107959 */ GIM_Reject,
38703 /* 107960 */ // Label 1993: @107960
38704 /* 107960 */ GIM_Reject,
38705 /* 107961 */ // Label 28: @107961
38706 /* 107961 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2000*/ GIMT_Encode4(108565),
38707 /* 107972 */ /*GILLT_s32*//*Label 1997*/ GIMT_Encode4(108020), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38708 /* 108000 */ /*GILLT_v4s32*//*Label 1998*/ GIMT_Encode4(108312), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38709 /* 108016 */ /*GILLT_v8s16*//*Label 1999*/ GIMT_Encode4(108495),
38710 /* 108020 */ // Label 1997: @108020
38711 /* 108020 */ GIM_Try, /*On fail goto*//*Label 2001*/ GIMT_Encode4(108311),
38712 /* 108025 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
38713 /* 108028 */ GIM_Try, /*On fail goto*//*Label 2002*/ GIMT_Encode4(108073), // Rule ID 339 //
38714 /* 108033 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
38715 /* 108036 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38716 /* 108040 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38717 /* 108044 */ // MIs[0] Operand 2
38718 /* 108044 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
38719 /* 108055 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i8:{ *:[Other] }) => (tSXTB:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
38720 /* 108055 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTB),
38721 /* 108058 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38722 /* 108060 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
38723 /* 108062 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38724 /* 108065 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38725 /* 108071 */ GIR_RootConstrainSelectedInstOperands,
38726 /* 108072 */ // GIR_Coverage, 339,
38727 /* 108072 */ GIR_EraseRootFromParent_Done,
38728 /* 108073 */ // Label 2002: @108073
38729 /* 108073 */ GIM_Try, /*On fail goto*//*Label 2003*/ GIMT_Encode4(108118), // Rule ID 340 //
38730 /* 108078 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
38731 /* 108081 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38732 /* 108085 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
38733 /* 108089 */ // MIs[0] Operand 2
38734 /* 108089 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
38735 /* 108100 */ // (sext_inreg:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, i16:{ *:[Other] }) => (tSXTH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
38736 /* 108100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tSXTH),
38737 /* 108103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38738 /* 108105 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
38739 /* 108107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38740 /* 108110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38741 /* 108116 */ GIR_RootConstrainSelectedInstOperands,
38742 /* 108117 */ // GIR_Coverage, 340,
38743 /* 108117 */ GIR_EraseRootFromParent_Done,
38744 /* 108118 */ // Label 2003: @108118
38745 /* 108118 */ GIM_Try, /*On fail goto*//*Label 2004*/ GIMT_Encode4(108166), // Rule ID 2163 //
38746 /* 108123 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
38747 /* 108126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
38748 /* 108130 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38749 /* 108134 */ // MIs[0] Operand 2
38750 /* 108134 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
38751 /* 108145 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (SXTB:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
38752 /* 108145 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTB),
38753 /* 108148 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38754 /* 108150 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
38755 /* 108152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38756 /* 108155 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38757 /* 108158 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38758 /* 108164 */ GIR_RootConstrainSelectedInstOperands,
38759 /* 108165 */ // GIR_Coverage, 2163,
38760 /* 108165 */ GIR_EraseRootFromParent_Done,
38761 /* 108166 */ // Label 2004: @108166
38762 /* 108166 */ GIM_Try, /*On fail goto*//*Label 2005*/ GIMT_Encode4(108214), // Rule ID 2164 //
38763 /* 108171 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
38764 /* 108174 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
38765 /* 108178 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
38766 /* 108182 */ // MIs[0] Operand 2
38767 /* 108182 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
38768 /* 108193 */ // (sext_inreg:{ *:[i32] } GPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (SXTH:{ *:[i32] } GPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
38769 /* 108193 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SXTH),
38770 /* 108196 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38771 /* 108198 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
38772 /* 108200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38773 /* 108203 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38774 /* 108206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38775 /* 108212 */ GIR_RootConstrainSelectedInstOperands,
38776 /* 108213 */ // GIR_Coverage, 2164,
38777 /* 108213 */ GIR_EraseRootFromParent_Done,
38778 /* 108214 */ // Label 2005: @108214
38779 /* 108214 */ GIM_Try, /*On fail goto*//*Label 2006*/ GIMT_Encode4(108262), // Rule ID 2402 //
38780 /* 108219 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38781 /* 108222 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38782 /* 108226 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38783 /* 108230 */ // MIs[0] Operand 2
38784 /* 108230 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
38785 /* 108241 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i8:{ *:[Other] }) => (t2SXTB:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
38786 /* 108241 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTB),
38787 /* 108244 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38788 /* 108246 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
38789 /* 108248 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38790 /* 108251 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38791 /* 108254 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38792 /* 108260 */ GIR_RootConstrainSelectedInstOperands,
38793 /* 108261 */ // GIR_Coverage, 2402,
38794 /* 108261 */ GIR_EraseRootFromParent_Done,
38795 /* 108262 */ // Label 2006: @108262
38796 /* 108262 */ GIM_Try, /*On fail goto*//*Label 2007*/ GIMT_Encode4(108310), // Rule ID 2403 //
38797 /* 108267 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
38798 /* 108270 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38799 /* 108274 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
38800 /* 108278 */ // MIs[0] Operand 2
38801 /* 108278 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
38802 /* 108289 */ // (sext_inreg:{ *:[i32] } rGPR:{ *:[i32] }:$Src, i16:{ *:[Other] }) => (t2SXTH:{ *:[i32] } rGPR:{ *:[i32] }:$Src, 0:{ *:[i32] })
38803 /* 108289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SXTH),
38804 /* 108292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
38805 /* 108294 */ GIR_RootToRootCopy, /*OpIdx*/1, // Src
38806 /* 108296 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38807 /* 108299 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38808 /* 108302 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38809 /* 108308 */ GIR_RootConstrainSelectedInstOperands,
38810 /* 108309 */ // GIR_Coverage, 2403,
38811 /* 108309 */ GIR_EraseRootFromParent_Done,
38812 /* 108310 */ // Label 2007: @108310
38813 /* 108310 */ GIM_Reject,
38814 /* 108311 */ // Label 2001: @108311
38815 /* 108311 */ GIM_Reject,
38816 /* 108312 */ // Label 1998: @108312
38817 /* 108312 */ GIM_Try, /*On fail goto*//*Label 2008*/ GIMT_Encode4(108494),
38818 /* 108317 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
38819 /* 108320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38820 /* 108324 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38821 /* 108328 */ GIM_Try, /*On fail goto*//*Label 2009*/ GIMT_Encode4(108386), // Rule ID 4071 //
38822 /* 108333 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
38823 /* 108336 */ // MIs[0] Operand 2
38824 /* 108336 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(16),
38825 /* 108347 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i16:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src)
38826 /* 108347 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38827 /* 108350 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38828 /* 108354 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38829 /* 108359 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh),
38830 /* 108362 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38831 /* 108364 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
38832 /* 108366 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38833 /* 108369 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38834 /* 108375 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38835 /* 108381 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38836 /* 108384 */ GIR_RootConstrainSelectedInstOperands,
38837 /* 108385 */ // GIR_Coverage, 4071,
38838 /* 108385 */ GIR_EraseRootFromParent_Done,
38839 /* 108386 */ // Label 2009: @108386
38840 /* 108386 */ GIM_Try, /*On fail goto*//*Label 2010*/ GIMT_Encode4(108493), // Rule ID 4073 //
38841 /* 108391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
38842 /* 108394 */ // MIs[0] Operand 2
38843 /* 108394 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
38844 /* 108405 */ // (sext_inreg:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src, v4i8:{ *:[Other] }) => (MVE_VMOVLs16bh:{ *:[v4i32] } (MVE_VMOVLs8bh:{ *:[v16i8] } MQPR:{ *:[v4i32] }:$src))
38845 /* 108405 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
38846 /* 108408 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38847 /* 108412 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38848 /* 108417 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s32,
38849 /* 108420 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38850 /* 108424 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38851 /* 108429 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v16s8,
38852 /* 108432 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh),
38853 /* 108436 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38854 /* 108441 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
38855 /* 108445 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
38856 /* 108448 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38857 /* 108454 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38858 /* 108460 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
38859 /* 108463 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
38860 /* 108465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs16bh),
38861 /* 108468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38862 /* 108470 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38863 /* 108473 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38864 /* 108476 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38865 /* 108482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38866 /* 108488 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2,
38867 /* 108491 */ GIR_RootConstrainSelectedInstOperands,
38868 /* 108492 */ // GIR_Coverage, 4073,
38869 /* 108492 */ GIR_EraseRootFromParent_Done,
38870 /* 108493 */ // Label 2010: @108493
38871 /* 108493 */ GIM_Reject,
38872 /* 108494 */ // Label 2008: @108494
38873 /* 108494 */ GIM_Reject,
38874 /* 108495 */ // Label 1999: @108495
38875 /* 108495 */ GIM_Try, /*On fail goto*//*Label 2011*/ GIMT_Encode4(108564), // Rule ID 4072 //
38876 /* 108500 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
38877 /* 108503 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
38878 /* 108506 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38879 /* 108510 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
38880 /* 108514 */ // MIs[0] Operand 2
38881 /* 108514 */ GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(8),
38882 /* 108525 */ // (sext_inreg:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src, v8i8:{ *:[Other] }) => (MVE_VMOVLs8bh:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src)
38883 /* 108525 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
38884 /* 108528 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
38885 /* 108532 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
38886 /* 108537 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOVLs8bh),
38887 /* 108540 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
38888 /* 108542 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
38889 /* 108544 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
38890 /* 108547 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38891 /* 108553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38892 /* 108559 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
38893 /* 108562 */ GIR_RootConstrainSelectedInstOperands,
38894 /* 108563 */ // GIR_Coverage, 4072,
38895 /* 108563 */ GIR_EraseRootFromParent_Done,
38896 /* 108564 */ // Label 2011: @108564
38897 /* 108564 */ GIM_Reject,
38898 /* 108565 */ // Label 2000: @108565
38899 /* 108565 */ GIM_Reject,
38900 /* 108566 */ // Label 29: @108566
38901 /* 108566 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(5), GIMT_Encode2(13), /*)*//*default:*//*Label 2015*/ GIMT_Encode4(109281),
38902 /* 108577 */ /*GILLT_v2s64*//*Label 2012*/ GIMT_Encode4(108609), GIMT_Encode4(0), GIMT_Encode4(0),
38903 /* 108589 */ /*GILLT_v4s32*//*Label 2013*/ GIMT_Encode4(108833), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
38904 /* 108605 */ /*GILLT_v8s16*//*Label 2014*/ GIMT_Encode4(109057),
38905 /* 108609 */ // Label 2012: @108609
38906 /* 108609 */ GIM_Try, /*On fail goto*//*Label 2016*/ GIMT_Encode4(108832),
38907 /* 108614 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
38908 /* 108617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38909 /* 108621 */ GIM_Try, /*On fail goto*//*Label 2017*/ GIMT_Encode4(108681), // Rule ID 1336 //
38910 /* 108626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38911 /* 108629 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38912 /* 108633 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
38913 /* 108637 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
38914 /* 108641 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38915 /* 108645 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38916 /* 108650 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38917 /* 108655 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38918 /* 108657 */ // (zext:{ *:[v2i64] } (abds:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLsv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38919 /* 108657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv2i64),
38920 /* 108660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38921 /* 108662 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38922 /* 108666 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38923 /* 108670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38924 /* 108673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38925 /* 108679 */ GIR_RootConstrainSelectedInstOperands,
38926 /* 108680 */ // GIR_Coverage, 1336,
38927 /* 108680 */ GIR_EraseRootFromParent_Done,
38928 /* 108681 */ // Label 2017: @108681
38929 /* 108681 */ GIM_Try, /*On fail goto*//*Label 2018*/ GIMT_Encode4(108741), // Rule ID 1339 //
38930 /* 108686 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38931 /* 108689 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38932 /* 108693 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
38933 /* 108697 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
38934 /* 108701 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38935 /* 108705 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38936 /* 108710 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38937 /* 108715 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38938 /* 108717 */ // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
38939 /* 108717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv2i64),
38940 /* 108720 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38941 /* 108722 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
38942 /* 108726 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
38943 /* 108730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38944 /* 108733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38945 /* 108739 */ GIR_RootConstrainSelectedInstOperands,
38946 /* 108740 */ // GIR_Coverage, 1339,
38947 /* 108740 */ GIR_EraseRootFromParent_Done,
38948 /* 108741 */ // Label 2018: @108741
38949 /* 108741 */ GIM_Try, /*On fail goto*//*Label 2019*/ GIMT_Encode4(108801), // Rule ID 2930 //
38950 /* 108746 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38951 /* 108749 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38952 /* 108753 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
38953 /* 108757 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
38954 /* 108761 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
38955 /* 108765 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38956 /* 108770 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38957 /* 108775 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38958 /* 108777 */ // (zext:{ *:[v2i64] } (abdu:{ *:[v2i32] } DPR:{ *:[v2i32] }:$opA, DPR:{ *:[v2i32] }:$opB)) => (VABDLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$opA, DPR:{ *:[v2i32] }:$opB)
38959 /* 108777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv2i64),
38960 /* 108780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38961 /* 108782 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA
38962 /* 108786 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB
38963 /* 108790 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38964 /* 108793 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38965 /* 108799 */ GIR_RootConstrainSelectedInstOperands,
38966 /* 108800 */ // GIR_Coverage, 2930,
38967 /* 108800 */ GIR_EraseRootFromParent_Done,
38968 /* 108801 */ // Label 2019: @108801
38969 /* 108801 */ GIM_Try, /*On fail goto*//*Label 2020*/ GIMT_Encode4(108831), // Rule ID 1764 //
38970 /* 108806 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38971 /* 108809 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38972 /* 108813 */ // (zext:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm) => (VMOVLuv2i64:{ *:[v2i64] } DPR:{ *:[v2i32] }:$Vm)
38973 /* 108813 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv2i64),
38974 /* 108816 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
38975 /* 108818 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
38976 /* 108820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
38977 /* 108823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
38978 /* 108829 */ GIR_RootConstrainSelectedInstOperands,
38979 /* 108830 */ // GIR_Coverage, 1764,
38980 /* 108830 */ GIR_EraseRootFromParent_Done,
38981 /* 108831 */ // Label 2020: @108831
38982 /* 108831 */ GIM_Reject,
38983 /* 108832 */ // Label 2016: @108832
38984 /* 108832 */ GIM_Reject,
38985 /* 108833 */ // Label 2013: @108833
38986 /* 108833 */ GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(109056),
38987 /* 108838 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
38988 /* 108841 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
38989 /* 108845 */ GIM_Try, /*On fail goto*//*Label 2022*/ GIMT_Encode4(108905), // Rule ID 1335 //
38990 /* 108850 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
38991 /* 108853 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
38992 /* 108857 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
38993 /* 108861 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
38994 /* 108865 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
38995 /* 108869 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38996 /* 108874 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
38997 /* 108879 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
38998 /* 108881 */ // (zext:{ *:[v4i32] } (abds:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLsv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
38999 /* 108881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv4i32),
39000 /* 108884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39001 /* 108886 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
39002 /* 108890 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
39003 /* 108894 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39004 /* 108897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39005 /* 108903 */ GIR_RootConstrainSelectedInstOperands,
39006 /* 108904 */ // GIR_Coverage, 1335,
39007 /* 108904 */ GIR_EraseRootFromParent_Done,
39008 /* 108905 */ // Label 2022: @108905
39009 /* 108905 */ GIM_Try, /*On fail goto*//*Label 2023*/ GIMT_Encode4(108965), // Rule ID 1338 //
39010 /* 108910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39011 /* 108913 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39012 /* 108917 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
39013 /* 108921 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
39014 /* 108925 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
39015 /* 108929 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39016 /* 108934 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39017 /* 108939 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39018 /* 108941 */ // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39019 /* 108941 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32),
39020 /* 108944 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39021 /* 108946 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
39022 /* 108950 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
39023 /* 108954 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39024 /* 108957 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39025 /* 108963 */ GIR_RootConstrainSelectedInstOperands,
39026 /* 108964 */ // GIR_Coverage, 1338,
39027 /* 108964 */ GIR_EraseRootFromParent_Done,
39028 /* 108965 */ // Label 2023: @108965
39029 /* 108965 */ GIM_Try, /*On fail goto*//*Label 2024*/ GIMT_Encode4(109025), // Rule ID 2929 //
39030 /* 108970 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39031 /* 108973 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39032 /* 108977 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
39033 /* 108981 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
39034 /* 108985 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
39035 /* 108989 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39036 /* 108994 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39037 /* 108999 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39038 /* 109001 */ // (zext:{ *:[v4i32] } (abdu:{ *:[v4i16] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB)) => (VABDLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$opA, DPR:{ *:[v4i16] }:$opB)
39039 /* 109001 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv4i32),
39040 /* 109004 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39041 /* 109006 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA
39042 /* 109010 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB
39043 /* 109014 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39044 /* 109017 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39045 /* 109023 */ GIR_RootConstrainSelectedInstOperands,
39046 /* 109024 */ // GIR_Coverage, 2929,
39047 /* 109024 */ GIR_EraseRootFromParent_Done,
39048 /* 109025 */ // Label 2024: @109025
39049 /* 109025 */ GIM_Try, /*On fail goto*//*Label 2025*/ GIMT_Encode4(109055), // Rule ID 1763 //
39050 /* 109030 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39051 /* 109033 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39052 /* 109037 */ // (zext:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm) => (VMOVLuv4i32:{ *:[v4i32] } DPR:{ *:[v4i16] }:$Vm)
39053 /* 109037 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv4i32),
39054 /* 109040 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39055 /* 109042 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
39056 /* 109044 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39057 /* 109047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39058 /* 109053 */ GIR_RootConstrainSelectedInstOperands,
39059 /* 109054 */ // GIR_Coverage, 1763,
39060 /* 109054 */ GIR_EraseRootFromParent_Done,
39061 /* 109055 */ // Label 2025: @109055
39062 /* 109055 */ GIM_Reject,
39063 /* 109056 */ // Label 2021: @109056
39064 /* 109056 */ GIM_Reject,
39065 /* 109057 */ // Label 2014: @109057
39066 /* 109057 */ GIM_Try, /*On fail goto*//*Label 2026*/ GIMT_Encode4(109280),
39067 /* 109062 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
39068 /* 109065 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39069 /* 109069 */ GIM_Try, /*On fail goto*//*Label 2027*/ GIMT_Encode4(109129), // Rule ID 1334 //
39070 /* 109074 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39071 /* 109077 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39072 /* 109081 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDS),
39073 /* 109085 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
39074 /* 109089 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
39075 /* 109093 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39076 /* 109098 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39077 /* 109103 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39078 /* 109105 */ // (zext:{ *:[v8i16] } (abds:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLsv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
39079 /* 109105 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLsv8i16),
39080 /* 109108 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39081 /* 109110 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
39082 /* 109114 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
39083 /* 109118 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39084 /* 109121 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39085 /* 109127 */ GIR_RootConstrainSelectedInstOperands,
39086 /* 109128 */ // GIR_Coverage, 1334,
39087 /* 109128 */ GIR_EraseRootFromParent_Done,
39088 /* 109129 */ // Label 2027: @109129
39089 /* 109129 */ GIM_Try, /*On fail goto*//*Label 2028*/ GIMT_Encode4(109189), // Rule ID 1337 //
39090 /* 109134 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39091 /* 109137 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39092 /* 109141 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
39093 /* 109145 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
39094 /* 109149 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
39095 /* 109153 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39096 /* 109158 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39097 /* 109163 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39098 /* 109165 */ // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
39099 /* 109165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16),
39100 /* 109168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39101 /* 109170 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
39102 /* 109174 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
39103 /* 109178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39104 /* 109181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39105 /* 109187 */ GIR_RootConstrainSelectedInstOperands,
39106 /* 109188 */ // GIR_Coverage, 1337,
39107 /* 109188 */ GIR_EraseRootFromParent_Done,
39108 /* 109189 */ // Label 2028: @109189
39109 /* 109189 */ GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(109249), // Rule ID 2928 //
39110 /* 109194 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39111 /* 109197 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39112 /* 109201 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABDU),
39113 /* 109205 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s8,
39114 /* 109209 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s8,
39115 /* 109213 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39116 /* 109218 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39117 /* 109223 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39118 /* 109225 */ // (zext:{ *:[v8i16] } (abdu:{ *:[v8i8] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB)) => (VABDLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$opA, DPR:{ *:[v8i8] }:$opB)
39119 /* 109225 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABDLuv8i16),
39120 /* 109228 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39121 /* 109230 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // opA
39122 /* 109234 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // opB
39123 /* 109238 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39124 /* 109241 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39125 /* 109247 */ GIR_RootConstrainSelectedInstOperands,
39126 /* 109248 */ // GIR_Coverage, 2928,
39127 /* 109248 */ GIR_EraseRootFromParent_Done,
39128 /* 109249 */ // Label 2029: @109249
39129 /* 109249 */ GIM_Try, /*On fail goto*//*Label 2030*/ GIMT_Encode4(109279), // Rule ID 1762 //
39130 /* 109254 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39131 /* 109257 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39132 /* 109261 */ // (zext:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm) => (VMOVLuv8i16:{ *:[v8i16] } DPR:{ *:[v8i8] }:$Vm)
39133 /* 109261 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMOVLuv8i16),
39134 /* 109264 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39135 /* 109266 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
39136 /* 109268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39137 /* 109271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39138 /* 109277 */ GIR_RootConstrainSelectedInstOperands,
39139 /* 109278 */ // GIR_Coverage, 1762,
39140 /* 109278 */ GIR_EraseRootFromParent_Done,
39141 /* 109279 */ // Label 2030: @109279
39142 /* 109279 */ GIM_Reject,
39143 /* 109280 */ // Label 2026: @109280
39144 /* 109280 */ GIM_Reject,
39145 /* 109281 */ // Label 2015: @109281
39146 /* 109281 */ GIM_Reject,
39147 /* 109282 */ // Label 30: @109282
39148 /* 109282 */ GIM_Try, /*On fail goto*//*Label 2031*/ GIMT_Encode4(109497),
39149 /* 109287 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
39150 /* 109290 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
39151 /* 109293 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
39152 /* 109296 */ GIM_Try, /*On fail goto*//*Label 2032*/ GIMT_Encode4(109353), // Rule ID 469 //
39153 /* 109301 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
39154 /* 109304 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39155 /* 109308 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39156 /* 109312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39157 /* 109316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39158 /* 109320 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31),
39159 /* 109324 */ // MIs[1] Operand 1
39160 /* 109324 */ // No operand predicates
39161 /* 109324 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39162 /* 109326 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2LSLri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm)
39163 /* 109326 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLri),
39164 /* 109329 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39165 /* 109331 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
39166 /* 109333 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
39167 /* 109336 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39168 /* 109339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39169 /* 109345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39170 /* 109351 */ GIR_RootConstrainSelectedInstOperands,
39171 /* 109352 */ // GIR_Coverage, 469,
39172 /* 109352 */ GIR_EraseRootFromParent_Done,
39173 /* 109353 */ // Label 2032: @109353
39174 /* 109353 */ GIM_Try, /*On fail goto*//*Label 2033*/ GIMT_Encode4(109450),
39175 /* 109358 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39176 /* 109362 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39177 /* 109366 */ GIM_Try, /*On fail goto*//*Label 2034*/ GIMT_Encode4(109411), // Rule ID 317 //
39178 /* 109371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
39179 /* 109374 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39180 /* 109378 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39181 /* 109382 */ // MIs[1] Operand 1
39182 /* 109382 */ // No operand predicates
39183 /* 109382 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39184 /* 109384 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5) => (tLSLri:{ *:[i32] } tGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm5)
39185 /* 109384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLri),
39186 /* 109387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39187 /* 109389 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
39188 /* 109395 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
39189 /* 109397 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm5
39190 /* 109400 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39191 /* 109403 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39192 /* 109409 */ GIR_RootConstrainSelectedInstOperands,
39193 /* 109410 */ // GIR_Coverage, 317,
39194 /* 109410 */ GIR_EraseRootFromParent_Done,
39195 /* 109411 */ // Label 2034: @109411
39196 /* 109411 */ GIM_Try, /*On fail goto*//*Label 2035*/ GIMT_Encode4(109449), // Rule ID 318 //
39197 /* 109416 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
39198 /* 109419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39199 /* 109423 */ // (shl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSLrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
39200 /* 109423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSLrr),
39201 /* 109426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
39202 /* 109428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
39203 /* 109434 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39204 /* 109436 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39205 /* 109438 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39206 /* 109441 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39207 /* 109447 */ GIR_RootConstrainSelectedInstOperands,
39208 /* 109448 */ // GIR_Coverage, 318,
39209 /* 109448 */ GIR_EraseRootFromParent_Done,
39210 /* 109449 */ // Label 2035: @109449
39211 /* 109449 */ GIM_Reject,
39212 /* 109450 */ // Label 2033: @109450
39213 /* 109450 */ GIM_Try, /*On fail goto*//*Label 2036*/ GIMT_Encode4(109496), // Rule ID 470 //
39214 /* 109455 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
39215 /* 109458 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39216 /* 109462 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39217 /* 109466 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39218 /* 109470 */ // (shl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSLrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
39219 /* 109470 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSLrr),
39220 /* 109473 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39221 /* 109475 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39222 /* 109477 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39223 /* 109479 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39224 /* 109482 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39225 /* 109488 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39226 /* 109494 */ GIR_RootConstrainSelectedInstOperands,
39227 /* 109495 */ // GIR_Coverage, 470,
39228 /* 109495 */ GIR_EraseRootFromParent_Done,
39229 /* 109496 */ // Label 2036: @109496
39230 /* 109496 */ GIM_Reject,
39231 /* 109497 */ // Label 2031: @109497
39232 /* 109497 */ GIM_Reject,
39233 /* 109498 */ // Label 31: @109498
39234 /* 109498 */ GIM_Try, /*On fail goto*//*Label 2037*/ GIMT_Encode4(109605),
39235 /* 109503 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
39236 /* 109506 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
39237 /* 109509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
39238 /* 109512 */ GIM_Try, /*On fail goto*//*Label 2038*/ GIMT_Encode4(109558), // Rule ID 320 //
39239 /* 109517 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
39240 /* 109520 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39241 /* 109524 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39242 /* 109528 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39243 /* 109532 */ // (srl:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tLSRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
39244 /* 109532 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tLSRrr),
39245 /* 109535 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
39246 /* 109537 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
39247 /* 109543 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39248 /* 109545 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39249 /* 109547 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39250 /* 109550 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39251 /* 109556 */ GIR_RootConstrainSelectedInstOperands,
39252 /* 109557 */ // GIR_Coverage, 320,
39253 /* 109557 */ GIR_EraseRootFromParent_Done,
39254 /* 109558 */ // Label 2038: @109558
39255 /* 109558 */ GIM_Try, /*On fail goto*//*Label 2039*/ GIMT_Encode4(109604), // Rule ID 472 //
39256 /* 109563 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
39257 /* 109566 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39258 /* 109570 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39259 /* 109574 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39260 /* 109578 */ // (srl:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2LSRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
39261 /* 109578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2LSRrr),
39262 /* 109581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39263 /* 109583 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39264 /* 109585 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39265 /* 109587 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39266 /* 109590 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39267 /* 109596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39268 /* 109602 */ GIR_RootConstrainSelectedInstOperands,
39269 /* 109603 */ // GIR_Coverage, 472,
39270 /* 109603 */ GIR_EraseRootFromParent_Done,
39271 /* 109604 */ // Label 2039: @109604
39272 /* 109604 */ GIM_Reject,
39273 /* 109605 */ // Label 2037: @109605
39274 /* 109605 */ GIM_Reject,
39275 /* 109606 */ // Label 32: @109606
39276 /* 109606 */ GIM_Try, /*On fail goto*//*Label 2040*/ GIMT_Encode4(109878),
39277 /* 109611 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
39278 /* 109614 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
39279 /* 109617 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
39280 /* 109620 */ GIM_Try, /*On fail goto*//*Label 2041*/ GIMT_Encode4(109675), // Rule ID 200 //
39281 /* 109625 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
39282 /* 109628 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39283 /* 109632 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39284 /* 109636 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
39285 /* 109640 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39286 /* 109644 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39287 /* 109649 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
39288 /* 109653 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39289 /* 109655 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REVSH:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
39290 /* 109655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REVSH),
39291 /* 109658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39292 /* 109660 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
39293 /* 109664 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39294 /* 109667 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39295 /* 109673 */ GIR_RootConstrainSelectedInstOperands,
39296 /* 109674 */ // GIR_Coverage, 200,
39297 /* 109674 */ GIR_EraseRootFromParent_Done,
39298 /* 109675 */ // Label 2041: @109675
39299 /* 109675 */ GIM_Try, /*On fail goto*//*Label 2042*/ GIMT_Encode4(109730), // Rule ID 327 //
39300 /* 109680 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
39301 /* 109683 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39302 /* 109687 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39303 /* 109691 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
39304 /* 109695 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39305 /* 109699 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39306 /* 109704 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
39307 /* 109708 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39308 /* 109710 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREVSH:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
39309 /* 109710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREVSH),
39310 /* 109713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39311 /* 109715 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
39312 /* 109719 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39313 /* 109722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39314 /* 109728 */ GIR_RootConstrainSelectedInstOperands,
39315 /* 109729 */ // GIR_Coverage, 327,
39316 /* 109729 */ GIR_EraseRootFromParent_Done,
39317 /* 109730 */ // Label 2042: @109730
39318 /* 109730 */ GIM_Try, /*On fail goto*//*Label 2043*/ GIMT_Encode4(109785), // Rule ID 537 //
39319 /* 109735 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
39320 /* 109738 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39321 /* 109742 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39322 /* 109746 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
39323 /* 109750 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39324 /* 109754 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39325 /* 109759 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
39326 /* 109763 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39327 /* 109765 */ // (sra:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REVSH:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
39328 /* 109765 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REVSH),
39329 /* 109768 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39330 /* 109770 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
39331 /* 109774 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39332 /* 109777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39333 /* 109783 */ GIR_RootConstrainSelectedInstOperands,
39334 /* 109784 */ // GIR_Coverage, 537,
39335 /* 109784 */ GIR_EraseRootFromParent_Done,
39336 /* 109785 */ // Label 2043: @109785
39337 /* 109785 */ GIM_Try, /*On fail goto*//*Label 2044*/ GIMT_Encode4(109831), // Rule ID 311 //
39338 /* 109790 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
39339 /* 109793 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39340 /* 109797 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39341 /* 109801 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39342 /* 109805 */ // (sra:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tASRrr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
39343 /* 109805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tASRrr),
39344 /* 109808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
39345 /* 109810 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
39346 /* 109816 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39347 /* 109818 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39348 /* 109820 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39349 /* 109823 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39350 /* 109829 */ GIR_RootConstrainSelectedInstOperands,
39351 /* 109830 */ // GIR_Coverage, 311,
39352 /* 109830 */ GIR_EraseRootFromParent_Done,
39353 /* 109831 */ // Label 2044: @109831
39354 /* 109831 */ GIM_Try, /*On fail goto*//*Label 2045*/ GIMT_Encode4(109877), // Rule ID 474 //
39355 /* 109836 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
39356 /* 109839 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39357 /* 109843 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39358 /* 109847 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39359 /* 109851 */ // (sra:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2ASRrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
39360 /* 109851 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2ASRrr),
39361 /* 109854 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39362 /* 109856 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39363 /* 109858 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39364 /* 109860 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39365 /* 109863 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39366 /* 109869 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39367 /* 109875 */ GIR_RootConstrainSelectedInstOperands,
39368 /* 109876 */ // GIR_Coverage, 474,
39369 /* 109876 */ GIR_EraseRootFromParent_Done,
39370 /* 109877 */ // Label 2045: @109877
39371 /* 109877 */ GIM_Reject,
39372 /* 109878 */ // Label 2040: @109878
39373 /* 109878 */ GIM_Reject,
39374 /* 109879 */ // Label 33: @109879
39375 /* 109879 */ GIM_Try, /*On fail goto*//*Label 2046*/ GIMT_Encode4(110210),
39376 /* 109884 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
39377 /* 109887 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
39378 /* 109890 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
39379 /* 109893 */ GIM_Try, /*On fail goto*//*Label 2047*/ GIMT_Encode4(109948), // Rule ID 199 //
39380 /* 109898 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
39381 /* 109901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39382 /* 109905 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39383 /* 109909 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
39384 /* 109913 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39385 /* 109917 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39386 /* 109922 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
39387 /* 109926 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39388 /* 109928 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (REV16:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
39389 /* 109928 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV16),
39390 /* 109931 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39391 /* 109933 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
39392 /* 109937 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39393 /* 109940 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39394 /* 109946 */ GIR_RootConstrainSelectedInstOperands,
39395 /* 109947 */ // GIR_Coverage, 199,
39396 /* 109947 */ GIR_EraseRootFromParent_Done,
39397 /* 109948 */ // Label 2047: @109948
39398 /* 109948 */ GIM_Try, /*On fail goto*//*Label 2048*/ GIMT_Encode4(110003), // Rule ID 326 //
39399 /* 109953 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
39400 /* 109956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39401 /* 109960 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39402 /* 109964 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
39403 /* 109968 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39404 /* 109972 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39405 /* 109977 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
39406 /* 109981 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39407 /* 109983 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (tREV16:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
39408 /* 109983 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV16),
39409 /* 109986 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39410 /* 109988 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
39411 /* 109992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39412 /* 109995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39413 /* 110001 */ GIR_RootConstrainSelectedInstOperands,
39414 /* 110002 */ // GIR_Coverage, 326,
39415 /* 110002 */ GIR_EraseRootFromParent_Done,
39416 /* 110003 */ // Label 2048: @110003
39417 /* 110003 */ GIM_Try, /*On fail goto*//*Label 2049*/ GIMT_Encode4(110117),
39418 /* 110008 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39419 /* 110012 */ GIM_Try, /*On fail goto*//*Label 2050*/ GIMT_Encode4(110063), // Rule ID 536 //
39420 /* 110017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
39421 /* 110020 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39422 /* 110024 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP),
39423 /* 110028 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39424 /* 110032 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39425 /* 110037 */ GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 16,
39426 /* 110041 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39427 /* 110043 */ // (rotr:{ *:[i32] } (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm), 16:{ *:[i32] }) => (t2REV16:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
39428 /* 110043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV16),
39429 /* 110046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39430 /* 110048 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rm
39431 /* 110052 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39432 /* 110055 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39433 /* 110061 */ GIR_RootConstrainSelectedInstOperands,
39434 /* 110062 */ // GIR_Coverage, 536,
39435 /* 110062 */ GIR_EraseRootFromParent_Done,
39436 /* 110063 */ // Label 2050: @110063
39437 /* 110063 */ GIM_Try, /*On fail goto*//*Label 2051*/ GIMT_Encode4(110116), // Rule ID 475 //
39438 /* 110068 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
39439 /* 110071 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39440 /* 110075 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
39441 /* 110079 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
39442 /* 110083 */ GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_imm1_31),
39443 /* 110087 */ // MIs[1] Operand 1
39444 /* 110087 */ // No operand predicates
39445 /* 110087 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39446 /* 110089 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] })<<P:Predicate_imm1_31>>:$imm) => (t2RORri:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (imm:{ *:[i32] }):$imm)
39447 /* 110089 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORri),
39448 /* 110092 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39449 /* 110094 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
39450 /* 110096 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // imm
39451 /* 110099 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39452 /* 110102 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39453 /* 110108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39454 /* 110114 */ GIR_RootConstrainSelectedInstOperands,
39455 /* 110115 */ // GIR_Coverage, 475,
39456 /* 110115 */ GIR_EraseRootFromParent_Done,
39457 /* 110116 */ // Label 2051: @110116
39458 /* 110116 */ GIM_Reject,
39459 /* 110117 */ // Label 2049: @110117
39460 /* 110117 */ GIM_Try, /*On fail goto*//*Label 2052*/ GIMT_Encode4(110163), // Rule ID 328 //
39461 /* 110122 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
39462 /* 110125 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39463 /* 110129 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39464 /* 110133 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
39465 /* 110137 */ // (rotr:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm) => (tROR:{ *:[i32] } tGPR:{ *:[i32] }:$Rn, tGPR:{ *:[i32] }:$Rm)
39466 /* 110137 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tROR),
39467 /* 110140 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rdn]
39468 /* 110142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
39469 /* 110148 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39470 /* 110150 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39471 /* 110152 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39472 /* 110155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39473 /* 110161 */ GIR_RootConstrainSelectedInstOperands,
39474 /* 110162 */ // GIR_Coverage, 328,
39475 /* 110162 */ GIR_EraseRootFromParent_Done,
39476 /* 110163 */ // Label 2052: @110163
39477 /* 110163 */ GIM_Try, /*On fail goto*//*Label 2053*/ GIMT_Encode4(110209), // Rule ID 476 //
39478 /* 110168 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
39479 /* 110171 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39480 /* 110175 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39481 /* 110179 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39482 /* 110183 */ // (rotr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2RORrr:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
39483 /* 110183 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RORrr),
39484 /* 110186 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39485 /* 110188 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39486 /* 110190 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39487 /* 110192 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39488 /* 110195 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39489 /* 110201 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39490 /* 110207 */ GIR_RootConstrainSelectedInstOperands,
39491 /* 110208 */ // GIR_Coverage, 476,
39492 /* 110208 */ GIR_EraseRootFromParent_Done,
39493 /* 110209 */ // Label 2053: @110209
39494 /* 110209 */ GIM_Reject,
39495 /* 110210 */ // Label 2046: @110210
39496 /* 110210 */ GIM_Reject,
39497 /* 110211 */ // Label 34: @110211
39498 /* 110211 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2057*/ GIMT_Encode4(110458),
39499 /* 110222 */ /*GILLT_v4s32*//*Label 2054*/ GIMT_Encode4(110254), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
39500 /* 110238 */ /*GILLT_v8s16*//*Label 2055*/ GIMT_Encode4(110322), GIMT_Encode4(0), GIMT_Encode4(0),
39501 /* 110250 */ /*GILLT_v16s8*//*Label 2056*/ GIMT_Encode4(110390),
39502 /* 110254 */ // Label 2054: @110254
39503 /* 110254 */ GIM_Try, /*On fail goto*//*Label 2058*/ GIMT_Encode4(110321), // Rule ID 4918 //
39504 /* 110259 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39505 /* 110262 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
39506 /* 110265 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
39507 /* 110268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39508 /* 110272 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39509 /* 110276 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39510 /* 110280 */ // (mulhu:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
39511 /* 110280 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39512 /* 110283 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39513 /* 110287 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39514 /* 110292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu32),
39515 /* 110295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39516 /* 110297 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39517 /* 110299 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39518 /* 110301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39519 /* 110304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39520 /* 110310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39521 /* 110316 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39522 /* 110319 */ GIR_RootConstrainSelectedInstOperands,
39523 /* 110320 */ // GIR_Coverage, 4918,
39524 /* 110320 */ GIR_EraseRootFromParent_Done,
39525 /* 110321 */ // Label 2058: @110321
39526 /* 110321 */ GIM_Reject,
39527 /* 110322 */ // Label 2055: @110322
39528 /* 110322 */ GIM_Try, /*On fail goto*//*Label 2059*/ GIMT_Encode4(110389), // Rule ID 4914 //
39529 /* 110327 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39530 /* 110330 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
39531 /* 110333 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
39532 /* 110336 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39533 /* 110340 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39534 /* 110344 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39535 /* 110348 */ // (mulhu:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
39536 /* 110348 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39537 /* 110351 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39538 /* 110355 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39539 /* 110360 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu16),
39540 /* 110363 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39541 /* 110365 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39542 /* 110367 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39543 /* 110369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39544 /* 110372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39545 /* 110378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39546 /* 110384 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39547 /* 110387 */ GIR_RootConstrainSelectedInstOperands,
39548 /* 110388 */ // GIR_Coverage, 4914,
39549 /* 110388 */ GIR_EraseRootFromParent_Done,
39550 /* 110389 */ // Label 2059: @110389
39551 /* 110389 */ GIM_Reject,
39552 /* 110390 */ // Label 2056: @110390
39553 /* 110390 */ GIM_Try, /*On fail goto*//*Label 2060*/ GIMT_Encode4(110457), // Rule ID 4910 //
39554 /* 110395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39555 /* 110398 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
39556 /* 110401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
39557 /* 110404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39558 /* 110408 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39559 /* 110412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39560 /* 110416 */ // (mulhu:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
39561 /* 110416 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39562 /* 110419 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39563 /* 110423 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39564 /* 110428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHu8),
39565 /* 110431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39566 /* 110433 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39567 /* 110435 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39568 /* 110437 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39569 /* 110440 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39570 /* 110446 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39571 /* 110452 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39572 /* 110455 */ GIR_RootConstrainSelectedInstOperands,
39573 /* 110456 */ // GIR_Coverage, 4910,
39574 /* 110456 */ GIR_EraseRootFromParent_Done,
39575 /* 110457 */ // Label 2060: @110457
39576 /* 110457 */ GIM_Reject,
39577 /* 110458 */ // Label 2057: @110458
39578 /* 110458 */ GIM_Reject,
39579 /* 110459 */ // Label 35: @110459
39580 /* 110459 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2065*/ GIMT_Encode4(110827),
39581 /* 110470 */ /*GILLT_s32*//*Label 2061*/ GIMT_Encode4(110530), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
39582 /* 110498 */ /*GILLT_v4s32*//*Label 2062*/ GIMT_Encode4(110623), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
39583 /* 110514 */ /*GILLT_v8s16*//*Label 2063*/ GIMT_Encode4(110691), GIMT_Encode4(0), GIMT_Encode4(0),
39584 /* 110526 */ /*GILLT_v16s8*//*Label 2064*/ GIMT_Encode4(110759),
39585 /* 110530 */ // Label 2061: @110530
39586 /* 110530 */ GIM_Try, /*On fail goto*//*Label 2066*/ GIMT_Encode4(110622),
39587 /* 110535 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
39588 /* 110538 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
39589 /* 110541 */ GIM_Try, /*On fail goto*//*Label 2067*/ GIMT_Encode4(110581), // Rule ID 177 //
39590 /* 110546 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
39591 /* 110549 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39592 /* 110553 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39593 /* 110557 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
39594 /* 110561 */ // (mulhs:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm) => (SMMUL:{ *:[i32] } GPR:{ *:[i32] }:$Rn, GPR:{ *:[i32] }:$Rm)
39595 /* 110561 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::SMMUL),
39596 /* 110564 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39597 /* 110566 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39598 /* 110568 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39599 /* 110570 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39600 /* 110573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39601 /* 110579 */ GIR_RootConstrainSelectedInstOperands,
39602 /* 110580 */ // GIR_Coverage, 177,
39603 /* 110580 */ GIR_EraseRootFromParent_Done,
39604 /* 110581 */ // Label 2067: @110581
39605 /* 110581 */ GIM_Try, /*On fail goto*//*Label 2068*/ GIMT_Encode4(110621), // Rule ID 506 //
39606 /* 110586 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
39607 /* 110589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39608 /* 110593 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39609 /* 110597 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39610 /* 110601 */ // (mulhs:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm) => (t2SMMUL:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rm)
39611 /* 110601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2SMMUL),
39612 /* 110604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39613 /* 110606 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rn
39614 /* 110608 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39615 /* 110610 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39616 /* 110613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39617 /* 110619 */ GIR_RootConstrainSelectedInstOperands,
39618 /* 110620 */ // GIR_Coverage, 506,
39619 /* 110620 */ GIR_EraseRootFromParent_Done,
39620 /* 110621 */ // Label 2068: @110621
39621 /* 110621 */ GIM_Reject,
39622 /* 110622 */ // Label 2066: @110622
39623 /* 110622 */ GIM_Reject,
39624 /* 110623 */ // Label 2062: @110623
39625 /* 110623 */ GIM_Try, /*On fail goto*//*Label 2069*/ GIMT_Encode4(110690), // Rule ID 4906 //
39626 /* 110628 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39627 /* 110631 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
39628 /* 110634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
39629 /* 110637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39630 /* 110641 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39631 /* 110645 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39632 /* 110649 */ // (mulhs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMULHs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
39633 /* 110649 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39634 /* 110652 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39635 /* 110656 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39636 /* 110661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs32),
39637 /* 110664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39638 /* 110666 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39639 /* 110668 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39640 /* 110670 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39641 /* 110673 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39642 /* 110679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39643 /* 110685 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39644 /* 110688 */ GIR_RootConstrainSelectedInstOperands,
39645 /* 110689 */ // GIR_Coverage, 4906,
39646 /* 110689 */ GIR_EraseRootFromParent_Done,
39647 /* 110690 */ // Label 2069: @110690
39648 /* 110690 */ GIM_Reject,
39649 /* 110691 */ // Label 2063: @110691
39650 /* 110691 */ GIM_Try, /*On fail goto*//*Label 2070*/ GIMT_Encode4(110758), // Rule ID 4902 //
39651 /* 110696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39652 /* 110699 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
39653 /* 110702 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
39654 /* 110705 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39655 /* 110709 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39656 /* 110713 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39657 /* 110717 */ // (mulhs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMULHs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
39658 /* 110717 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39659 /* 110720 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39660 /* 110724 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39661 /* 110729 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs16),
39662 /* 110732 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39663 /* 110734 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39664 /* 110736 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39665 /* 110738 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39666 /* 110741 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39667 /* 110747 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39668 /* 110753 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39669 /* 110756 */ GIR_RootConstrainSelectedInstOperands,
39670 /* 110757 */ // GIR_Coverage, 4902,
39671 /* 110757 */ GIR_EraseRootFromParent_Done,
39672 /* 110758 */ // Label 2070: @110758
39673 /* 110758 */ GIM_Reject,
39674 /* 110759 */ // Label 2064: @110759
39675 /* 110759 */ GIM_Try, /*On fail goto*//*Label 2071*/ GIMT_Encode4(110826), // Rule ID 4899 //
39676 /* 110764 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39677 /* 110767 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
39678 /* 110770 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
39679 /* 110773 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39680 /* 110777 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39681 /* 110781 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39682 /* 110785 */ // (mulhs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMULHs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
39683 /* 110785 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39684 /* 110788 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39685 /* 110792 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39686 /* 110797 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULHs8),
39687 /* 110800 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39688 /* 110802 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39689 /* 110804 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39690 /* 110806 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39691 /* 110809 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39692 /* 110815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39693 /* 110821 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39694 /* 110824 */ GIR_RootConstrainSelectedInstOperands,
39695 /* 110825 */ // GIR_Coverage, 4899,
39696 /* 110825 */ GIR_EraseRootFromParent_Done,
39697 /* 110826 */ // Label 2071: @110826
39698 /* 110826 */ GIM_Reject,
39699 /* 110827 */ // Label 2065: @110827
39700 /* 110827 */ GIM_Reject,
39701 /* 110828 */ // Label 36: @110828
39702 /* 110828 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(16), /*)*//*default:*//*Label 2080*/ GIMT_Encode4(111472),
39703 /* 110839 */ /*GILLT_s64*//*Label 2072*/ GIMT_Encode4(110895), GIMT_Encode4(0),
39704 /* 110847 */ /*GILLT_v2s32*//*Label 2073*/ GIMT_Encode4(110942),
39705 /* 110851 */ /*GILLT_v2s64*//*Label 2074*/ GIMT_Encode4(110989), GIMT_Encode4(0),
39706 /* 110859 */ /*GILLT_v4s16*//*Label 2075*/ GIMT_Encode4(111036),
39707 /* 110863 */ /*GILLT_v4s32*//*Label 2076*/ GIMT_Encode4(111083), GIMT_Encode4(0), GIMT_Encode4(0),
39708 /* 110875 */ /*GILLT_v8s8*//*Label 2077*/ GIMT_Encode4(111197),
39709 /* 110879 */ /*GILLT_v8s16*//*Label 2078*/ GIMT_Encode4(111244), GIMT_Encode4(0), GIMT_Encode4(0),
39710 /* 110891 */ /*GILLT_v16s8*//*Label 2079*/ GIMT_Encode4(111358),
39711 /* 110895 */ // Label 2072: @110895
39712 /* 110895 */ GIM_Try, /*On fail goto*//*Label 2081*/ GIMT_Encode4(110941), // Rule ID 949 //
39713 /* 110900 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39714 /* 110903 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
39715 /* 110906 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
39716 /* 110909 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39717 /* 110913 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39718 /* 110917 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39719 /* 110921 */ // (uaddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
39720 /* 110921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv1i64),
39721 /* 110924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39722 /* 110926 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39723 /* 110928 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39724 /* 110930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39725 /* 110933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39726 /* 110939 */ GIR_RootConstrainSelectedInstOperands,
39727 /* 110940 */ // GIR_Coverage, 949,
39728 /* 110940 */ GIR_EraseRootFromParent_Done,
39729 /* 110941 */ // Label 2081: @110941
39730 /* 110941 */ GIM_Reject,
39731 /* 110942 */ // Label 2073: @110942
39732 /* 110942 */ GIM_Try, /*On fail goto*//*Label 2082*/ GIMT_Encode4(110988), // Rule ID 944 //
39733 /* 110947 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39734 /* 110950 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
39735 /* 110953 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
39736 /* 110956 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39737 /* 110960 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39738 /* 110964 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39739 /* 110968 */ // (uaddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
39740 /* 110968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i32),
39741 /* 110971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39742 /* 110973 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39743 /* 110975 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39744 /* 110977 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39745 /* 110980 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39746 /* 110986 */ GIR_RootConstrainSelectedInstOperands,
39747 /* 110987 */ // GIR_Coverage, 944,
39748 /* 110987 */ GIR_EraseRootFromParent_Done,
39749 /* 110988 */ // Label 2082: @110988
39750 /* 110988 */ GIM_Reject,
39751 /* 110989 */ // Label 2074: @110989
39752 /* 110989 */ GIM_Try, /*On fail goto*//*Label 2083*/ GIMT_Encode4(111035), // Rule ID 950 //
39753 /* 110994 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39754 /* 110997 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
39755 /* 111000 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
39756 /* 111003 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39757 /* 111007 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39758 /* 111011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39759 /* 111015 */ // (uaddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
39760 /* 111015 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv2i64),
39761 /* 111018 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39762 /* 111020 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39763 /* 111022 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39764 /* 111024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39765 /* 111027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39766 /* 111033 */ GIR_RootConstrainSelectedInstOperands,
39767 /* 111034 */ // GIR_Coverage, 950,
39768 /* 111034 */ GIR_EraseRootFromParent_Done,
39769 /* 111035 */ // Label 2083: @111035
39770 /* 111035 */ GIM_Reject,
39771 /* 111036 */ // Label 2075: @111036
39772 /* 111036 */ GIM_Try, /*On fail goto*//*Label 2084*/ GIMT_Encode4(111082), // Rule ID 943 //
39773 /* 111041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39774 /* 111044 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
39775 /* 111047 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
39776 /* 111050 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39777 /* 111054 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39778 /* 111058 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39779 /* 111062 */ // (uaddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
39780 /* 111062 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i16),
39781 /* 111065 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39782 /* 111067 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39783 /* 111069 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39784 /* 111071 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39785 /* 111074 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39786 /* 111080 */ GIR_RootConstrainSelectedInstOperands,
39787 /* 111081 */ // GIR_Coverage, 943,
39788 /* 111081 */ GIR_EraseRootFromParent_Done,
39789 /* 111082 */ // Label 2084: @111082
39790 /* 111082 */ GIM_Reject,
39791 /* 111083 */ // Label 2076: @111083
39792 /* 111083 */ GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(111196),
39793 /* 111088 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
39794 /* 111091 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
39795 /* 111094 */ GIM_Try, /*On fail goto*//*Label 2086*/ GIMT_Encode4(111134), // Rule ID 946 //
39796 /* 111099 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39797 /* 111102 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39798 /* 111106 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39799 /* 111110 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39800 /* 111114 */ // (uaddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
39801 /* 111114 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv4i32),
39802 /* 111117 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39803 /* 111119 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39804 /* 111121 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39805 /* 111123 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39806 /* 111126 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39807 /* 111132 */ GIR_RootConstrainSelectedInstOperands,
39808 /* 111133 */ // GIR_Coverage, 946,
39809 /* 111133 */ GIR_EraseRootFromParent_Done,
39810 /* 111134 */ // Label 2086: @111134
39811 /* 111134 */ GIM_Try, /*On fail goto*//*Label 2087*/ GIMT_Encode4(111195), // Rule ID 3885 //
39812 /* 111139 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39813 /* 111142 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39814 /* 111146 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39815 /* 111150 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39816 /* 111154 */ // (uaddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
39817 /* 111154 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39818 /* 111157 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39819 /* 111161 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39820 /* 111166 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu32),
39821 /* 111169 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39822 /* 111171 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39823 /* 111173 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39824 /* 111175 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39825 /* 111178 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39826 /* 111184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39827 /* 111190 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39828 /* 111193 */ GIR_RootConstrainSelectedInstOperands,
39829 /* 111194 */ // GIR_Coverage, 3885,
39830 /* 111194 */ GIR_EraseRootFromParent_Done,
39831 /* 111195 */ // Label 2087: @111195
39832 /* 111195 */ GIM_Reject,
39833 /* 111196 */ // Label 2085: @111196
39834 /* 111196 */ GIM_Reject,
39835 /* 111197 */ // Label 2077: @111197
39836 /* 111197 */ GIM_Try, /*On fail goto*//*Label 2088*/ GIMT_Encode4(111243), // Rule ID 947 //
39837 /* 111202 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39838 /* 111205 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
39839 /* 111208 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
39840 /* 111211 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39841 /* 111215 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39842 /* 111219 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
39843 /* 111223 */ // (uaddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
39844 /* 111223 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i8),
39845 /* 111226 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39846 /* 111228 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39847 /* 111230 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39848 /* 111232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39849 /* 111235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39850 /* 111241 */ GIR_RootConstrainSelectedInstOperands,
39851 /* 111242 */ // GIR_Coverage, 947,
39852 /* 111242 */ GIR_EraseRootFromParent_Done,
39853 /* 111243 */ // Label 2088: @111243
39854 /* 111243 */ GIM_Reject,
39855 /* 111244 */ // Label 2078: @111244
39856 /* 111244 */ GIM_Try, /*On fail goto*//*Label 2089*/ GIMT_Encode4(111357),
39857 /* 111249 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
39858 /* 111252 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
39859 /* 111255 */ GIM_Try, /*On fail goto*//*Label 2090*/ GIMT_Encode4(111295), // Rule ID 945 //
39860 /* 111260 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39861 /* 111263 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39862 /* 111267 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39863 /* 111271 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39864 /* 111275 */ // (uaddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
39865 /* 111275 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv8i16),
39866 /* 111278 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39867 /* 111280 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39868 /* 111282 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39869 /* 111284 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39870 /* 111287 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39871 /* 111293 */ GIR_RootConstrainSelectedInstOperands,
39872 /* 111294 */ // GIR_Coverage, 945,
39873 /* 111294 */ GIR_EraseRootFromParent_Done,
39874 /* 111295 */ // Label 2090: @111295
39875 /* 111295 */ GIM_Try, /*On fail goto*//*Label 2091*/ GIMT_Encode4(111356), // Rule ID 3882 //
39876 /* 111300 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39877 /* 111303 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39878 /* 111307 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39879 /* 111311 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39880 /* 111315 */ // (uaddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
39881 /* 111315 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39882 /* 111318 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39883 /* 111322 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39884 /* 111327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu16),
39885 /* 111330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39886 /* 111332 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39887 /* 111334 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39888 /* 111336 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39889 /* 111339 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39890 /* 111345 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39891 /* 111351 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39892 /* 111354 */ GIR_RootConstrainSelectedInstOperands,
39893 /* 111355 */ // GIR_Coverage, 3882,
39894 /* 111355 */ GIR_EraseRootFromParent_Done,
39895 /* 111356 */ // Label 2091: @111356
39896 /* 111356 */ GIM_Reject,
39897 /* 111357 */ // Label 2089: @111357
39898 /* 111357 */ GIM_Reject,
39899 /* 111358 */ // Label 2079: @111358
39900 /* 111358 */ GIM_Try, /*On fail goto*//*Label 2092*/ GIMT_Encode4(111471),
39901 /* 111363 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
39902 /* 111366 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
39903 /* 111369 */ GIM_Try, /*On fail goto*//*Label 2093*/ GIMT_Encode4(111409), // Rule ID 948 //
39904 /* 111374 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
39905 /* 111377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39906 /* 111381 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39907 /* 111385 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
39908 /* 111389 */ // (uaddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
39909 /* 111389 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDuv16i8),
39910 /* 111392 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
39911 /* 111394 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
39912 /* 111396 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
39913 /* 111398 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39914 /* 111401 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39915 /* 111407 */ GIR_RootConstrainSelectedInstOperands,
39916 /* 111408 */ // GIR_Coverage, 948,
39917 /* 111408 */ GIR_EraseRootFromParent_Done,
39918 /* 111409 */ // Label 2093: @111409
39919 /* 111409 */ GIM_Try, /*On fail goto*//*Label 2094*/ GIMT_Encode4(111470), // Rule ID 3879 //
39920 /* 111414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
39921 /* 111417 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39922 /* 111421 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39923 /* 111425 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
39924 /* 111429 */ // (uaddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
39925 /* 111429 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
39926 /* 111432 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
39927 /* 111436 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
39928 /* 111441 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDu8),
39929 /* 111444 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
39930 /* 111446 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
39931 /* 111448 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
39932 /* 111450 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
39933 /* 111453 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39934 /* 111459 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39935 /* 111465 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
39936 /* 111468 */ GIR_RootConstrainSelectedInstOperands,
39937 /* 111469 */ // GIR_Coverage, 3879,
39938 /* 111469 */ GIR_EraseRootFromParent_Done,
39939 /* 111470 */ // Label 2094: @111470
39940 /* 111470 */ GIM_Reject,
39941 /* 111471 */ // Label 2092: @111471
39942 /* 111471 */ GIM_Reject,
39943 /* 111472 */ // Label 2080: @111472
39944 /* 111472 */ GIM_Reject,
39945 /* 111473 */ // Label 37: @111473
39946 /* 111473 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2104*/ GIMT_Encode4(112772),
39947 /* 111484 */ /*GILLT_s32*//*Label 2095*/ GIMT_Encode4(111544),
39948 /* 111488 */ /*GILLT_s64*//*Label 2096*/ GIMT_Encode4(111885), GIMT_Encode4(0),
39949 /* 111496 */ /*GILLT_v2s32*//*Label 2097*/ GIMT_Encode4(111932),
39950 /* 111500 */ /*GILLT_v2s64*//*Label 2098*/ GIMT_Encode4(111979), GIMT_Encode4(0),
39951 /* 111508 */ /*GILLT_v4s16*//*Label 2099*/ GIMT_Encode4(112180),
39952 /* 111512 */ /*GILLT_v4s32*//*Label 2100*/ GIMT_Encode4(112227), GIMT_Encode4(0), GIMT_Encode4(0),
39953 /* 111524 */ /*GILLT_v8s8*//*Label 2101*/ GIMT_Encode4(112497),
39954 /* 111528 */ /*GILLT_v8s16*//*Label 2102*/ GIMT_Encode4(112544), GIMT_Encode4(0), GIMT_Encode4(0),
39955 /* 111540 */ /*GILLT_v16s8*//*Label 2103*/ GIMT_Encode4(112658),
39956 /* 111544 */ // Label 2095: @111544
39957 /* 111544 */ GIM_Try, /*On fail goto*//*Label 2105*/ GIMT_Encode4(111884),
39958 /* 111549 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
39959 /* 111552 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
39960 /* 111555 */ GIM_Try, /*On fail goto*//*Label 2106*/ GIMT_Encode4(111617), // Rule ID 6198 //
39961 /* 111560 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
39962 /* 111563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
39963 /* 111567 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39964 /* 111571 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
39965 /* 111575 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39966 /* 111579 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39967 /* 111584 */ // MIs[1] Rn
39968 /* 111584 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
39969 /* 111589 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39970 /* 111593 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39971 /* 111595 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39972 /* 111595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
39973 /* 111598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39974 /* 111600 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39975 /* 111602 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
39976 /* 111606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39977 /* 111609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
39978 /* 111615 */ GIR_RootConstrainSelectedInstOperands,
39979 /* 111616 */ // GIR_Coverage, 6198,
39980 /* 111616 */ GIR_EraseRootFromParent_Done,
39981 /* 111617 */ // Label 2106: @111617
39982 /* 111617 */ GIM_Try, /*On fail goto*//*Label 2107*/ GIMT_Encode4(111679), // Rule ID 6232 //
39983 /* 111622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
39984 /* 111625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39985 /* 111629 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
39986 /* 111633 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
39987 /* 111637 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
39988 /* 111641 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39989 /* 111646 */ // MIs[1] Rn
39990 /* 111646 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
39991 /* 111651 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
39992 /* 111655 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
39993 /* 111657 */ // (saddsat:{ *:[i32] } (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn), rGPR:{ *:[i32] }:$Rm) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
39994 /* 111657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
39995 /* 111660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
39996 /* 111662 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rm
39997 /* 111664 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
39998 /* 111668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
39999 /* 111671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40000 /* 111677 */ GIR_RootConstrainSelectedInstOperands,
40001 /* 111678 */ // GIR_Coverage, 6232,
40002 /* 111678 */ GIR_EraseRootFromParent_Done,
40003 /* 111679 */ // Label 2107: @111679
40004 /* 111679 */ GIM_Try, /*On fail goto*//*Label 2108*/ GIMT_Encode4(111741), // Rule ID 2031 //
40005 /* 111684 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
40006 /* 111687 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
40007 /* 111691 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40008 /* 111695 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40009 /* 111699 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
40010 /* 111703 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40011 /* 111707 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40012 /* 111712 */ // MIs[1] Rn
40013 /* 111712 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
40014 /* 111717 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40015 /* 111719 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
40016 /* 111719 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDADD),
40017 /* 111722 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
40018 /* 111724 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
40019 /* 111726 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
40020 /* 111730 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40021 /* 111733 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40022 /* 111739 */ GIR_RootConstrainSelectedInstOperands,
40023 /* 111740 */ // GIR_Coverage, 2031,
40024 /* 111740 */ GIR_EraseRootFromParent_Done,
40025 /* 111741 */ // Label 2108: @111741
40026 /* 111741 */ GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(111803), // Rule ID 2297 //
40027 /* 111746 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
40028 /* 111749 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40029 /* 111753 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40030 /* 111757 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40031 /* 111761 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
40032 /* 111765 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40033 /* 111769 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40034 /* 111774 */ // MIs[1] Rn
40035 /* 111774 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
40036 /* 111779 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40037 /* 111781 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
40038 /* 111781 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDADD),
40039 /* 111784 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
40040 /* 111786 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
40041 /* 111788 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
40042 /* 111792 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40043 /* 111795 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40044 /* 111801 */ GIR_RootConstrainSelectedInstOperands,
40045 /* 111802 */ // GIR_Coverage, 2297,
40046 /* 111802 */ GIR_EraseRootFromParent_Done,
40047 /* 111803 */ // Label 2109: @111803
40048 /* 111803 */ GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(111843), // Rule ID 2029 //
40049 /* 111808 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
40050 /* 111811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
40051 /* 111815 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
40052 /* 111819 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
40053 /* 111823 */ // (saddsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QADD:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
40054 /* 111823 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QADD),
40055 /* 111826 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
40056 /* 111828 */ GIR_RootToRootCopy, /*OpIdx*/1, // a
40057 /* 111830 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
40058 /* 111832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40059 /* 111835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40060 /* 111841 */ GIR_RootConstrainSelectedInstOperands,
40061 /* 111842 */ // GIR_Coverage, 2029,
40062 /* 111842 */ GIR_EraseRootFromParent_Done,
40063 /* 111843 */ // Label 2110: @111843
40064 /* 111843 */ GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(111883), // Rule ID 2295 //
40065 /* 111848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
40066 /* 111851 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40067 /* 111855 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40068 /* 111859 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40069 /* 111863 */ // (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QADD:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
40070 /* 111863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QADD),
40071 /* 111866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
40072 /* 111868 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
40073 /* 111870 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
40074 /* 111872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40075 /* 111875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40076 /* 111881 */ GIR_RootConstrainSelectedInstOperands,
40077 /* 111882 */ // GIR_Coverage, 2295,
40078 /* 111882 */ GIR_EraseRootFromParent_Done,
40079 /* 111883 */ // Label 2111: @111883
40080 /* 111883 */ GIM_Reject,
40081 /* 111884 */ // Label 2105: @111884
40082 /* 111884 */ GIM_Reject,
40083 /* 111885 */ // Label 2096: @111885
40084 /* 111885 */ GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(111931), // Rule ID 941 //
40085 /* 111890 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40086 /* 111893 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
40087 /* 111896 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
40088 /* 111899 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40089 /* 111903 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40090 /* 111907 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40091 /* 111911 */ // (saddsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQADDsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
40092 /* 111911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv1i64),
40093 /* 111914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40094 /* 111916 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40095 /* 111918 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40096 /* 111920 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40097 /* 111923 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40098 /* 111929 */ GIR_RootConstrainSelectedInstOperands,
40099 /* 111930 */ // GIR_Coverage, 941,
40100 /* 111930 */ GIR_EraseRootFromParent_Done,
40101 /* 111931 */ // Label 2112: @111931
40102 /* 111931 */ GIM_Reject,
40103 /* 111932 */ // Label 2097: @111932
40104 /* 111932 */ GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(111978), // Rule ID 936 //
40105 /* 111937 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40106 /* 111940 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
40107 /* 111943 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
40108 /* 111946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40109 /* 111950 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40110 /* 111954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40111 /* 111958 */ // (saddsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQADDsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
40112 /* 111958 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i32),
40113 /* 111961 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40114 /* 111963 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40115 /* 111965 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40116 /* 111967 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40117 /* 111970 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40118 /* 111976 */ GIR_RootConstrainSelectedInstOperands,
40119 /* 111977 */ // GIR_Coverage, 936,
40120 /* 111977 */ GIR_EraseRootFromParent_Done,
40121 /* 111978 */ // Label 2113: @111978
40122 /* 111978 */ GIM_Reject,
40123 /* 111979 */ // Label 2098: @111979
40124 /* 111979 */ GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(112179),
40125 /* 111984 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
40126 /* 111987 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
40127 /* 111990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40128 /* 111994 */ GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(112068), // Rule ID 6313 //
40129 /* 111999 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40130 /* 112002 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40131 /* 112006 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
40132 /* 112010 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
40133 /* 112013 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
40134 /* 112018 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
40135 /* 112022 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
40136 /* 112026 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40137 /* 112031 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40138 /* 112036 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40139 /* 112040 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40140 /* 112042 */ // (saddsat:{ *:[v2i64] } (intrinsic_wo_chain:{ *:[v2i64] } 4052:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm), QPR:{ *:[v2i64] }:$src1) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
40141 /* 112042 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64),
40142 /* 112045 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40143 /* 112047 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
40144 /* 112049 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
40145 /* 112053 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
40146 /* 112057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40147 /* 112060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40148 /* 112066 */ GIR_RootConstrainSelectedInstOperands,
40149 /* 112067 */ // GIR_Coverage, 6313,
40150 /* 112067 */ GIR_EraseRootFromParent_Done,
40151 /* 112068 */ // Label 2115: @112068
40152 /* 112068 */ GIM_Try, /*On fail goto*//*Label 2116*/ GIMT_Encode4(112142), // Rule ID 2834 //
40153 /* 112073 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40154 /* 112076 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40155 /* 112080 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40156 /* 112084 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
40157 /* 112088 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
40158 /* 112091 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
40159 /* 112096 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
40160 /* 112100 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
40161 /* 112104 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40162 /* 112109 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40163 /* 112114 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40164 /* 112116 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 4052:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLALv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
40165 /* 112116 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv2i64),
40166 /* 112119 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40167 /* 112121 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
40168 /* 112123 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
40169 /* 112127 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
40170 /* 112131 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40171 /* 112134 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40172 /* 112140 */ GIR_RootConstrainSelectedInstOperands,
40173 /* 112141 */ // GIR_Coverage, 2834,
40174 /* 112141 */ GIR_EraseRootFromParent_Done,
40175 /* 112142 */ // Label 2116: @112142
40176 /* 112142 */ GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(112178), // Rule ID 942 //
40177 /* 112147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40178 /* 112150 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40179 /* 112154 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40180 /* 112158 */ // (saddsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQADDsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
40181 /* 112158 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv2i64),
40182 /* 112161 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40183 /* 112163 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40184 /* 112165 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40185 /* 112167 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40186 /* 112170 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40187 /* 112176 */ GIR_RootConstrainSelectedInstOperands,
40188 /* 112177 */ // GIR_Coverage, 942,
40189 /* 112177 */ GIR_EraseRootFromParent_Done,
40190 /* 112178 */ // Label 2117: @112178
40191 /* 112178 */ GIM_Reject,
40192 /* 112179 */ // Label 2114: @112179
40193 /* 112179 */ GIM_Reject,
40194 /* 112180 */ // Label 2099: @112180
40195 /* 112180 */ GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(112226), // Rule ID 935 //
40196 /* 112185 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40197 /* 112188 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
40198 /* 112191 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
40199 /* 112194 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40200 /* 112198 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40201 /* 112202 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40202 /* 112206 */ // (saddsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQADDsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
40203 /* 112206 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i16),
40204 /* 112209 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40205 /* 112211 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40206 /* 112213 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40207 /* 112215 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40208 /* 112218 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40209 /* 112224 */ GIR_RootConstrainSelectedInstOperands,
40210 /* 112225 */ // GIR_Coverage, 935,
40211 /* 112225 */ GIR_EraseRootFromParent_Done,
40212 /* 112226 */ // Label 2118: @112226
40213 /* 112226 */ GIM_Reject,
40214 /* 112227 */ // Label 2100: @112227
40215 /* 112227 */ GIM_Try, /*On fail goto*//*Label 2119*/ GIMT_Encode4(112496),
40216 /* 112232 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
40217 /* 112235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
40218 /* 112238 */ GIM_Try, /*On fail goto*//*Label 2120*/ GIMT_Encode4(112316), // Rule ID 6312 //
40219 /* 112243 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40220 /* 112246 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40221 /* 112250 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
40222 /* 112254 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
40223 /* 112258 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
40224 /* 112261 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
40225 /* 112266 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
40226 /* 112270 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
40227 /* 112274 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40228 /* 112279 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40229 /* 112284 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40230 /* 112288 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40231 /* 112290 */ // (saddsat:{ *:[v4i32] } (intrinsic_wo_chain:{ *:[v4i32] } 4052:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm), QPR:{ *:[v4i32] }:$src1) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
40232 /* 112290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32),
40233 /* 112293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40234 /* 112295 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
40235 /* 112297 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
40236 /* 112301 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
40237 /* 112305 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40238 /* 112308 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40239 /* 112314 */ GIR_RootConstrainSelectedInstOperands,
40240 /* 112315 */ // GIR_Coverage, 6312,
40241 /* 112315 */ GIR_EraseRootFromParent_Done,
40242 /* 112316 */ // Label 2120: @112316
40243 /* 112316 */ GIM_Try, /*On fail goto*//*Label 2121*/ GIMT_Encode4(112394), // Rule ID 2833 //
40244 /* 112321 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40245 /* 112324 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40246 /* 112328 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40247 /* 112332 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40248 /* 112336 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
40249 /* 112340 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
40250 /* 112343 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
40251 /* 112348 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
40252 /* 112352 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
40253 /* 112356 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40254 /* 112361 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40255 /* 112366 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40256 /* 112368 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 4052:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLALv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
40257 /* 112368 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLALv4i32),
40258 /* 112371 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40259 /* 112373 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
40260 /* 112375 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
40261 /* 112379 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
40262 /* 112383 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40263 /* 112386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40264 /* 112392 */ GIR_RootConstrainSelectedInstOperands,
40265 /* 112393 */ // GIR_Coverage, 2833,
40266 /* 112393 */ GIR_EraseRootFromParent_Done,
40267 /* 112394 */ // Label 2121: @112394
40268 /* 112394 */ GIM_Try, /*On fail goto*//*Label 2122*/ GIMT_Encode4(112434), // Rule ID 938 //
40269 /* 112399 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40270 /* 112402 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40271 /* 112406 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40272 /* 112410 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40273 /* 112414 */ // (saddsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQADDsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
40274 /* 112414 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv4i32),
40275 /* 112417 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40276 /* 112419 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40277 /* 112421 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40278 /* 112423 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40279 /* 112426 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40280 /* 112432 */ GIR_RootConstrainSelectedInstOperands,
40281 /* 112433 */ // GIR_Coverage, 938,
40282 /* 112433 */ GIR_EraseRootFromParent_Done,
40283 /* 112434 */ // Label 2122: @112434
40284 /* 112434 */ GIM_Try, /*On fail goto*//*Label 2123*/ GIMT_Encode4(112495), // Rule ID 3876 //
40285 /* 112439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40286 /* 112442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40287 /* 112446 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40288 /* 112450 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40289 /* 112454 */ // (saddsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQADDs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
40290 /* 112454 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40291 /* 112457 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40292 /* 112461 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40293 /* 112466 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs32),
40294 /* 112469 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40295 /* 112471 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
40296 /* 112473 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
40297 /* 112475 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40298 /* 112478 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40299 /* 112484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40300 /* 112490 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40301 /* 112493 */ GIR_RootConstrainSelectedInstOperands,
40302 /* 112494 */ // GIR_Coverage, 3876,
40303 /* 112494 */ GIR_EraseRootFromParent_Done,
40304 /* 112495 */ // Label 2123: @112495
40305 /* 112495 */ GIM_Reject,
40306 /* 112496 */ // Label 2119: @112496
40307 /* 112496 */ GIM_Reject,
40308 /* 112497 */ // Label 2101: @112497
40309 /* 112497 */ GIM_Try, /*On fail goto*//*Label 2124*/ GIMT_Encode4(112543), // Rule ID 939 //
40310 /* 112502 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40311 /* 112505 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
40312 /* 112508 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
40313 /* 112511 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40314 /* 112515 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40315 /* 112519 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40316 /* 112523 */ // (saddsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQADDsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
40317 /* 112523 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i8),
40318 /* 112526 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40319 /* 112528 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40320 /* 112530 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40321 /* 112532 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40322 /* 112535 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40323 /* 112541 */ GIR_RootConstrainSelectedInstOperands,
40324 /* 112542 */ // GIR_Coverage, 939,
40325 /* 112542 */ GIR_EraseRootFromParent_Done,
40326 /* 112543 */ // Label 2124: @112543
40327 /* 112543 */ GIM_Reject,
40328 /* 112544 */ // Label 2102: @112544
40329 /* 112544 */ GIM_Try, /*On fail goto*//*Label 2125*/ GIMT_Encode4(112657),
40330 /* 112549 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
40331 /* 112552 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
40332 /* 112555 */ GIM_Try, /*On fail goto*//*Label 2126*/ GIMT_Encode4(112595), // Rule ID 937 //
40333 /* 112560 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40334 /* 112563 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40335 /* 112567 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40336 /* 112571 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40337 /* 112575 */ // (saddsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQADDsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
40338 /* 112575 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv8i16),
40339 /* 112578 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40340 /* 112580 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40341 /* 112582 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40342 /* 112584 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40343 /* 112587 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40344 /* 112593 */ GIR_RootConstrainSelectedInstOperands,
40345 /* 112594 */ // GIR_Coverage, 937,
40346 /* 112594 */ GIR_EraseRootFromParent_Done,
40347 /* 112595 */ // Label 2126: @112595
40348 /* 112595 */ GIM_Try, /*On fail goto*//*Label 2127*/ GIMT_Encode4(112656), // Rule ID 3873 //
40349 /* 112600 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40350 /* 112603 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40351 /* 112607 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40352 /* 112611 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40353 /* 112615 */ // (saddsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQADDs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
40354 /* 112615 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40355 /* 112618 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40356 /* 112622 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40357 /* 112627 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs16),
40358 /* 112630 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40359 /* 112632 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
40360 /* 112634 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
40361 /* 112636 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40362 /* 112639 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40363 /* 112645 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40364 /* 112651 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40365 /* 112654 */ GIR_RootConstrainSelectedInstOperands,
40366 /* 112655 */ // GIR_Coverage, 3873,
40367 /* 112655 */ GIR_EraseRootFromParent_Done,
40368 /* 112656 */ // Label 2127: @112656
40369 /* 112656 */ GIM_Reject,
40370 /* 112657 */ // Label 2125: @112657
40371 /* 112657 */ GIM_Reject,
40372 /* 112658 */ // Label 2103: @112658
40373 /* 112658 */ GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(112771),
40374 /* 112663 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
40375 /* 112666 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
40376 /* 112669 */ GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(112709), // Rule ID 940 //
40377 /* 112674 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40378 /* 112677 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40379 /* 112681 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40380 /* 112685 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40381 /* 112689 */ // (saddsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQADDsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
40382 /* 112689 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQADDsv16i8),
40383 /* 112692 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40384 /* 112694 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40385 /* 112696 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40386 /* 112698 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40387 /* 112701 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40388 /* 112707 */ GIR_RootConstrainSelectedInstOperands,
40389 /* 112708 */ // GIR_Coverage, 940,
40390 /* 112708 */ GIR_EraseRootFromParent_Done,
40391 /* 112709 */ // Label 2129: @112709
40392 /* 112709 */ GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(112770), // Rule ID 3870 //
40393 /* 112714 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40394 /* 112717 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40395 /* 112721 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40396 /* 112725 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40397 /* 112729 */ // (saddsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQADDs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
40398 /* 112729 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40399 /* 112732 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40400 /* 112736 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40401 /* 112741 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQADDs8),
40402 /* 112744 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40403 /* 112746 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
40404 /* 112748 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
40405 /* 112750 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40406 /* 112753 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40407 /* 112759 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40408 /* 112765 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40409 /* 112768 */ GIR_RootConstrainSelectedInstOperands,
40410 /* 112769 */ // GIR_Coverage, 3870,
40411 /* 112769 */ GIR_EraseRootFromParent_Done,
40412 /* 112770 */ // Label 2130: @112770
40413 /* 112770 */ GIM_Reject,
40414 /* 112771 */ // Label 2128: @112771
40415 /* 112771 */ GIM_Reject,
40416 /* 112772 */ // Label 2104: @112772
40417 /* 112772 */ GIM_Reject,
40418 /* 112773 */ // Label 38: @112773
40419 /* 112773 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(2), GIMT_Encode2(16), /*)*//*default:*//*Label 2139*/ GIMT_Encode4(113417),
40420 /* 112784 */ /*GILLT_s64*//*Label 2131*/ GIMT_Encode4(112840), GIMT_Encode4(0),
40421 /* 112792 */ /*GILLT_v2s32*//*Label 2132*/ GIMT_Encode4(112887),
40422 /* 112796 */ /*GILLT_v2s64*//*Label 2133*/ GIMT_Encode4(112934), GIMT_Encode4(0),
40423 /* 112804 */ /*GILLT_v4s16*//*Label 2134*/ GIMT_Encode4(112981),
40424 /* 112808 */ /*GILLT_v4s32*//*Label 2135*/ GIMT_Encode4(113028), GIMT_Encode4(0), GIMT_Encode4(0),
40425 /* 112820 */ /*GILLT_v8s8*//*Label 2136*/ GIMT_Encode4(113142),
40426 /* 112824 */ /*GILLT_v8s16*//*Label 2137*/ GIMT_Encode4(113189), GIMT_Encode4(0), GIMT_Encode4(0),
40427 /* 112836 */ /*GILLT_v16s8*//*Label 2138*/ GIMT_Encode4(113303),
40428 /* 112840 */ // Label 2131: @112840
40429 /* 112840 */ GIM_Try, /*On fail goto*//*Label 2140*/ GIMT_Encode4(112886), // Rule ID 1183 //
40430 /* 112845 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40431 /* 112848 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
40432 /* 112851 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
40433 /* 112854 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40434 /* 112858 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40435 /* 112862 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40436 /* 112866 */ // (usubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBuv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
40437 /* 112866 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv1i64),
40438 /* 112869 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40439 /* 112871 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40440 /* 112873 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40441 /* 112875 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40442 /* 112878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40443 /* 112884 */ GIR_RootConstrainSelectedInstOperands,
40444 /* 112885 */ // GIR_Coverage, 1183,
40445 /* 112885 */ GIR_EraseRootFromParent_Done,
40446 /* 112886 */ // Label 2140: @112886
40447 /* 112886 */ GIM_Reject,
40448 /* 112887 */ // Label 2132: @112887
40449 /* 112887 */ GIM_Try, /*On fail goto*//*Label 2141*/ GIMT_Encode4(112933), // Rule ID 1178 //
40450 /* 112892 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40451 /* 112895 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
40452 /* 112898 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
40453 /* 112901 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40454 /* 112905 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40455 /* 112909 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40456 /* 112913 */ // (usubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
40457 /* 112913 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i32),
40458 /* 112916 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40459 /* 112918 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40460 /* 112920 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40461 /* 112922 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40462 /* 112925 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40463 /* 112931 */ GIR_RootConstrainSelectedInstOperands,
40464 /* 112932 */ // GIR_Coverage, 1178,
40465 /* 112932 */ GIR_EraseRootFromParent_Done,
40466 /* 112933 */ // Label 2141: @112933
40467 /* 112933 */ GIM_Reject,
40468 /* 112934 */ // Label 2133: @112934
40469 /* 112934 */ GIM_Try, /*On fail goto*//*Label 2142*/ GIMT_Encode4(112980), // Rule ID 1184 //
40470 /* 112939 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40471 /* 112942 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
40472 /* 112945 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
40473 /* 112948 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40474 /* 112952 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40475 /* 112956 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40476 /* 112960 */ // (usubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBuv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
40477 /* 112960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv2i64),
40478 /* 112963 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40479 /* 112965 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40480 /* 112967 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40481 /* 112969 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40482 /* 112972 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40483 /* 112978 */ GIR_RootConstrainSelectedInstOperands,
40484 /* 112979 */ // GIR_Coverage, 1184,
40485 /* 112979 */ GIR_EraseRootFromParent_Done,
40486 /* 112980 */ // Label 2142: @112980
40487 /* 112980 */ GIM_Reject,
40488 /* 112981 */ // Label 2134: @112981
40489 /* 112981 */ GIM_Try, /*On fail goto*//*Label 2143*/ GIMT_Encode4(113027), // Rule ID 1177 //
40490 /* 112986 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40491 /* 112989 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
40492 /* 112992 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
40493 /* 112995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40494 /* 112999 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40495 /* 113003 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40496 /* 113007 */ // (usubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
40497 /* 113007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i16),
40498 /* 113010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40499 /* 113012 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40500 /* 113014 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40501 /* 113016 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40502 /* 113019 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40503 /* 113025 */ GIR_RootConstrainSelectedInstOperands,
40504 /* 113026 */ // GIR_Coverage, 1177,
40505 /* 113026 */ GIR_EraseRootFromParent_Done,
40506 /* 113027 */ // Label 2143: @113027
40507 /* 113027 */ GIM_Reject,
40508 /* 113028 */ // Label 2135: @113028
40509 /* 113028 */ GIM_Try, /*On fail goto*//*Label 2144*/ GIMT_Encode4(113141),
40510 /* 113033 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
40511 /* 113036 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
40512 /* 113039 */ GIM_Try, /*On fail goto*//*Label 2145*/ GIMT_Encode4(113079), // Rule ID 1180 //
40513 /* 113044 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40514 /* 113047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40515 /* 113051 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40516 /* 113055 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40517 /* 113059 */ // (usubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
40518 /* 113059 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv4i32),
40519 /* 113062 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40520 /* 113064 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40521 /* 113066 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40522 /* 113068 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40523 /* 113071 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40524 /* 113077 */ GIR_RootConstrainSelectedInstOperands,
40525 /* 113078 */ // GIR_Coverage, 1180,
40526 /* 113078 */ GIR_EraseRootFromParent_Done,
40527 /* 113079 */ // Label 2145: @113079
40528 /* 113079 */ GIM_Try, /*On fail goto*//*Label 2146*/ GIMT_Encode4(113140), // Rule ID 3903 //
40529 /* 113084 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40530 /* 113087 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40531 /* 113091 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40532 /* 113095 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40533 /* 113099 */ // (usubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
40534 /* 113099 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40535 /* 113102 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40536 /* 113106 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40537 /* 113111 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu32),
40538 /* 113114 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40539 /* 113116 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
40540 /* 113118 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
40541 /* 113120 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40542 /* 113123 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40543 /* 113129 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40544 /* 113135 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40545 /* 113138 */ GIR_RootConstrainSelectedInstOperands,
40546 /* 113139 */ // GIR_Coverage, 3903,
40547 /* 113139 */ GIR_EraseRootFromParent_Done,
40548 /* 113140 */ // Label 2146: @113140
40549 /* 113140 */ GIM_Reject,
40550 /* 113141 */ // Label 2144: @113141
40551 /* 113141 */ GIM_Reject,
40552 /* 113142 */ // Label 2136: @113142
40553 /* 113142 */ GIM_Try, /*On fail goto*//*Label 2147*/ GIMT_Encode4(113188), // Rule ID 1181 //
40554 /* 113147 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40555 /* 113150 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
40556 /* 113153 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
40557 /* 113156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40558 /* 113160 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40559 /* 113164 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40560 /* 113168 */ // (usubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
40561 /* 113168 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i8),
40562 /* 113171 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40563 /* 113173 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40564 /* 113175 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40565 /* 113177 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40566 /* 113180 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40567 /* 113186 */ GIR_RootConstrainSelectedInstOperands,
40568 /* 113187 */ // GIR_Coverage, 1181,
40569 /* 113187 */ GIR_EraseRootFromParent_Done,
40570 /* 113188 */ // Label 2147: @113188
40571 /* 113188 */ GIM_Reject,
40572 /* 113189 */ // Label 2137: @113189
40573 /* 113189 */ GIM_Try, /*On fail goto*//*Label 2148*/ GIMT_Encode4(113302),
40574 /* 113194 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
40575 /* 113197 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
40576 /* 113200 */ GIM_Try, /*On fail goto*//*Label 2149*/ GIMT_Encode4(113240), // Rule ID 1179 //
40577 /* 113205 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40578 /* 113208 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40579 /* 113212 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40580 /* 113216 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40581 /* 113220 */ // (usubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
40582 /* 113220 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv8i16),
40583 /* 113223 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40584 /* 113225 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40585 /* 113227 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40586 /* 113229 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40587 /* 113232 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40588 /* 113238 */ GIR_RootConstrainSelectedInstOperands,
40589 /* 113239 */ // GIR_Coverage, 1179,
40590 /* 113239 */ GIR_EraseRootFromParent_Done,
40591 /* 113240 */ // Label 2149: @113240
40592 /* 113240 */ GIM_Try, /*On fail goto*//*Label 2150*/ GIMT_Encode4(113301), // Rule ID 3900 //
40593 /* 113245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40594 /* 113248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40595 /* 113252 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40596 /* 113256 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40597 /* 113260 */ // (usubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
40598 /* 113260 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40599 /* 113263 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40600 /* 113267 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40601 /* 113272 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu16),
40602 /* 113275 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40603 /* 113277 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
40604 /* 113279 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
40605 /* 113281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40606 /* 113284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40607 /* 113290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40608 /* 113296 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40609 /* 113299 */ GIR_RootConstrainSelectedInstOperands,
40610 /* 113300 */ // GIR_Coverage, 3900,
40611 /* 113300 */ GIR_EraseRootFromParent_Done,
40612 /* 113301 */ // Label 2150: @113301
40613 /* 113301 */ GIM_Reject,
40614 /* 113302 */ // Label 2148: @113302
40615 /* 113302 */ GIM_Reject,
40616 /* 113303 */ // Label 2138: @113303
40617 /* 113303 */ GIM_Try, /*On fail goto*//*Label 2151*/ GIMT_Encode4(113416),
40618 /* 113308 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
40619 /* 113311 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
40620 /* 113314 */ GIM_Try, /*On fail goto*//*Label 2152*/ GIMT_Encode4(113354), // Rule ID 1182 //
40621 /* 113319 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40622 /* 113322 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40623 /* 113326 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40624 /* 113330 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40625 /* 113334 */ // (usubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
40626 /* 113334 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBuv16i8),
40627 /* 113337 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40628 /* 113339 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40629 /* 113341 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40630 /* 113343 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40631 /* 113346 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40632 /* 113352 */ GIR_RootConstrainSelectedInstOperands,
40633 /* 113353 */ // GIR_Coverage, 1182,
40634 /* 113353 */ GIR_EraseRootFromParent_Done,
40635 /* 113354 */ // Label 2152: @113354
40636 /* 113354 */ GIM_Try, /*On fail goto*//*Label 2153*/ GIMT_Encode4(113415), // Rule ID 3897 //
40637 /* 113359 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40638 /* 113362 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40639 /* 113366 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40640 /* 113370 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40641 /* 113374 */ // (usubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
40642 /* 113374 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40643 /* 113377 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40644 /* 113381 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40645 /* 113386 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBu8),
40646 /* 113389 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40647 /* 113391 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
40648 /* 113393 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
40649 /* 113395 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40650 /* 113398 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40651 /* 113404 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40652 /* 113410 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40653 /* 113413 */ GIR_RootConstrainSelectedInstOperands,
40654 /* 113414 */ // GIR_Coverage, 3897,
40655 /* 113414 */ GIR_EraseRootFromParent_Done,
40656 /* 113415 */ // Label 2153: @113415
40657 /* 113415 */ GIM_Reject,
40658 /* 113416 */ // Label 2151: @113416
40659 /* 113416 */ GIM_Reject,
40660 /* 113417 */ // Label 2139: @113417
40661 /* 113417 */ GIM_Reject,
40662 /* 113418 */ // Label 39: @113418
40663 /* 113418 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2163*/ GIMT_Encode4(114437),
40664 /* 113429 */ /*GILLT_s32*//*Label 2154*/ GIMT_Encode4(113489),
40665 /* 113433 */ /*GILLT_s64*//*Label 2155*/ GIMT_Encode4(113706), GIMT_Encode4(0),
40666 /* 113441 */ /*GILLT_v2s32*//*Label 2156*/ GIMT_Encode4(113753),
40667 /* 113445 */ /*GILLT_v2s64*//*Label 2157*/ GIMT_Encode4(113800), GIMT_Encode4(0),
40668 /* 113453 */ /*GILLT_v4s16*//*Label 2158*/ GIMT_Encode4(113923),
40669 /* 113457 */ /*GILLT_v4s32*//*Label 2159*/ GIMT_Encode4(113970), GIMT_Encode4(0), GIMT_Encode4(0),
40670 /* 113469 */ /*GILLT_v8s8*//*Label 2160*/ GIMT_Encode4(114162),
40671 /* 113473 */ /*GILLT_v8s16*//*Label 2161*/ GIMT_Encode4(114209), GIMT_Encode4(0), GIMT_Encode4(0),
40672 /* 113485 */ /*GILLT_v16s8*//*Label 2162*/ GIMT_Encode4(114323),
40673 /* 113489 */ // Label 2154: @113489
40674 /* 113489 */ GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(113705),
40675 /* 113494 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
40676 /* 113497 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
40677 /* 113500 */ GIM_Try, /*On fail goto*//*Label 2165*/ GIMT_Encode4(113562), // Rule ID 2032 //
40678 /* 113505 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
40679 /* 113508 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
40680 /* 113512 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40681 /* 113516 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40682 /* 113520 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
40683 /* 113524 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40684 /* 113528 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40685 /* 113533 */ // MIs[1] Rn
40686 /* 113533 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
40687 /* 113538 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40688 /* 113540 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
40689 /* 113540 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QDSUB),
40690 /* 113543 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
40691 /* 113545 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
40692 /* 113547 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
40693 /* 113551 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40694 /* 113554 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40695 /* 113560 */ GIR_RootConstrainSelectedInstOperands,
40696 /* 113561 */ // GIR_Coverage, 2032,
40697 /* 113561 */ GIR_EraseRootFromParent_Done,
40698 /* 113562 */ // Label 2165: @113562
40699 /* 113562 */ GIM_Try, /*On fail goto*//*Label 2166*/ GIMT_Encode4(113624), // Rule ID 2298 //
40700 /* 113567 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
40701 /* 113570 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40702 /* 113574 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40703 /* 113578 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40704 /* 113582 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SADDSAT),
40705 /* 113586 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
40706 /* 113590 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40707 /* 113595 */ // MIs[1] Rn
40708 /* 113595 */ GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1,
40709 /* 113600 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40710 /* 113602 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, (saddsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rn, rGPR:{ *:[i32] }:$Rn)) => (t2QDSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
40711 /* 113602 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QDSUB),
40712 /* 113605 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
40713 /* 113607 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
40714 /* 113609 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Rn
40715 /* 113613 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40716 /* 113616 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40717 /* 113622 */ GIR_RootConstrainSelectedInstOperands,
40718 /* 113623 */ // GIR_Coverage, 2298,
40719 /* 113623 */ GIR_EraseRootFromParent_Done,
40720 /* 113624 */ // Label 2166: @113624
40721 /* 113624 */ GIM_Try, /*On fail goto*//*Label 2167*/ GIMT_Encode4(113664), // Rule ID 2030 //
40722 /* 113629 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5TE_IsARM),
40723 /* 113632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
40724 /* 113636 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
40725 /* 113640 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
40726 /* 113644 */ // (ssubsat:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b) => (QSUB:{ *:[i32] } GPR:{ *:[i32] }:$a, GPR:{ *:[i32] }:$b)
40727 /* 113644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::QSUB),
40728 /* 113647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
40729 /* 113649 */ GIR_RootToRootCopy, /*OpIdx*/1, // a
40730 /* 113651 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
40731 /* 113653 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40732 /* 113656 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40733 /* 113662 */ GIR_RootConstrainSelectedInstOperands,
40734 /* 113663 */ // GIR_Coverage, 2030,
40735 /* 113663 */ GIR_EraseRootFromParent_Done,
40736 /* 113664 */ // Label 2167: @113664
40737 /* 113664 */ GIM_Try, /*On fail goto*//*Label 2168*/ GIMT_Encode4(113704), // Rule ID 2296 //
40738 /* 113669 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDSP_IsThumb2),
40739 /* 113672 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40740 /* 113676 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40741 /* 113680 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
40742 /* 113684 */ // (ssubsat:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn) => (t2QSUB:{ *:[i32] } rGPR:{ *:[i32] }:$Rm, rGPR:{ *:[i32] }:$Rn)
40743 /* 113684 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2QSUB),
40744 /* 113687 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
40745 /* 113689 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
40746 /* 113691 */ GIR_RootToRootCopy, /*OpIdx*/2, // Rn
40747 /* 113693 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40748 /* 113696 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40749 /* 113702 */ GIR_RootConstrainSelectedInstOperands,
40750 /* 113703 */ // GIR_Coverage, 2296,
40751 /* 113703 */ GIR_EraseRootFromParent_Done,
40752 /* 113704 */ // Label 2168: @113704
40753 /* 113704 */ GIM_Reject,
40754 /* 113705 */ // Label 2164: @113705
40755 /* 113705 */ GIM_Reject,
40756 /* 113706 */ // Label 2155: @113706
40757 /* 113706 */ GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(113752), // Rule ID 1175 //
40758 /* 113711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40759 /* 113714 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
40760 /* 113717 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
40761 /* 113720 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40762 /* 113724 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40763 /* 113728 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40764 /* 113732 */ // (ssubsat:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm) => (VQSUBsv1i64:{ *:[v1i64] } DPR:{ *:[v1i64] }:$Vn, DPR:{ *:[v1i64] }:$Vm)
40765 /* 113732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv1i64),
40766 /* 113735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40767 /* 113737 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40768 /* 113739 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40769 /* 113741 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40770 /* 113744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40771 /* 113750 */ GIR_RootConstrainSelectedInstOperands,
40772 /* 113751 */ // GIR_Coverage, 1175,
40773 /* 113751 */ GIR_EraseRootFromParent_Done,
40774 /* 113752 */ // Label 2169: @113752
40775 /* 113752 */ GIM_Reject,
40776 /* 113753 */ // Label 2156: @113753
40777 /* 113753 */ GIM_Try, /*On fail goto*//*Label 2170*/ GIMT_Encode4(113799), // Rule ID 1170 //
40778 /* 113758 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40779 /* 113761 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
40780 /* 113764 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
40781 /* 113767 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40782 /* 113771 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40783 /* 113775 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40784 /* 113779 */ // (ssubsat:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VQSUBsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
40785 /* 113779 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i32),
40786 /* 113782 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40787 /* 113784 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40788 /* 113786 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40789 /* 113788 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40790 /* 113791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40791 /* 113797 */ GIR_RootConstrainSelectedInstOperands,
40792 /* 113798 */ // GIR_Coverage, 1170,
40793 /* 113798 */ GIR_EraseRootFromParent_Done,
40794 /* 113799 */ // Label 2170: @113799
40795 /* 113799 */ GIM_Reject,
40796 /* 113800 */ // Label 2157: @113800
40797 /* 113800 */ GIM_Try, /*On fail goto*//*Label 2171*/ GIMT_Encode4(113922),
40798 /* 113805 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64,
40799 /* 113808 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64,
40800 /* 113811 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40801 /* 113815 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40802 /* 113819 */ GIM_Try, /*On fail goto*//*Label 2172*/ GIMT_Encode4(113889), // Rule ID 2844 //
40803 /* 113824 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40804 /* 113827 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40805 /* 113831 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
40806 /* 113835 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
40807 /* 113838 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
40808 /* 113843 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32,
40809 /* 113847 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v2s32,
40810 /* 113851 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40811 /* 113856 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40812 /* 113861 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40813 /* 113863 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, (intrinsic_wo_chain:{ *:[v2i64] } 4052:{ *:[iPTR] }, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)) => (VQDMLSLv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$src1, DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
40814 /* 113863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv2i64),
40815 /* 113866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40816 /* 113868 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
40817 /* 113870 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
40818 /* 113874 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
40819 /* 113878 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40820 /* 113881 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40821 /* 113887 */ GIR_RootConstrainSelectedInstOperands,
40822 /* 113888 */ // GIR_Coverage, 2844,
40823 /* 113888 */ GIR_EraseRootFromParent_Done,
40824 /* 113889 */ // Label 2172: @113889
40825 /* 113889 */ GIM_Try, /*On fail goto*//*Label 2173*/ GIMT_Encode4(113921), // Rule ID 1176 //
40826 /* 113894 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40827 /* 113897 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40828 /* 113901 */ // (ssubsat:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm) => (VQSUBsv2i64:{ *:[v2i64] } QPR:{ *:[v2i64] }:$Vn, QPR:{ *:[v2i64] }:$Vm)
40829 /* 113901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv2i64),
40830 /* 113904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40831 /* 113906 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40832 /* 113908 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40833 /* 113910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40834 /* 113913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40835 /* 113919 */ GIR_RootConstrainSelectedInstOperands,
40836 /* 113920 */ // GIR_Coverage, 1176,
40837 /* 113920 */ GIR_EraseRootFromParent_Done,
40838 /* 113921 */ // Label 2173: @113921
40839 /* 113921 */ GIM_Reject,
40840 /* 113922 */ // Label 2171: @113922
40841 /* 113922 */ GIM_Reject,
40842 /* 113923 */ // Label 2158: @113923
40843 /* 113923 */ GIM_Try, /*On fail goto*//*Label 2174*/ GIMT_Encode4(113969), // Rule ID 1169 //
40844 /* 113928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40845 /* 113931 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
40846 /* 113934 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
40847 /* 113937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40848 /* 113941 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40849 /* 113945 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40850 /* 113949 */ // (ssubsat:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VQSUBsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
40851 /* 113949 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i16),
40852 /* 113952 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40853 /* 113954 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40854 /* 113956 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40855 /* 113958 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40856 /* 113961 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40857 /* 113967 */ GIR_RootConstrainSelectedInstOperands,
40858 /* 113968 */ // GIR_Coverage, 1169,
40859 /* 113968 */ GIR_EraseRootFromParent_Done,
40860 /* 113969 */ // Label 2174: @113969
40861 /* 113969 */ GIM_Reject,
40862 /* 113970 */ // Label 2159: @113970
40863 /* 113970 */ GIM_Try, /*On fail goto*//*Label 2175*/ GIMT_Encode4(114161),
40864 /* 113975 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
40865 /* 113978 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
40866 /* 113981 */ GIM_Try, /*On fail goto*//*Label 2176*/ GIMT_Encode4(114059), // Rule ID 2843 //
40867 /* 113986 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40868 /* 113989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40869 /* 113993 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40870 /* 113997 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
40871 /* 114001 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC),
40872 /* 114005 */ GIM_CheckNumOperands, /*MI*/1, /*Expected*/4,
40873 /* 114008 */ GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::arm_neon_vqdmull),
40874 /* 114013 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
40875 /* 114017 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_v4s16,
40876 /* 114021 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40877 /* 114026 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40878 /* 114031 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
40879 /* 114033 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, (intrinsic_wo_chain:{ *:[v4i32] } 4052:{ *:[iPTR] }, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)) => (VQDMLSLv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$src1, DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
40880 /* 114033 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQDMLSLv4i32),
40881 /* 114036 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40882 /* 114038 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
40883 /* 114040 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vn
40884 /* 114044 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Vm
40885 /* 114048 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40886 /* 114051 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40887 /* 114057 */ GIR_RootConstrainSelectedInstOperands,
40888 /* 114058 */ // GIR_Coverage, 2843,
40889 /* 114058 */ GIR_EraseRootFromParent_Done,
40890 /* 114059 */ // Label 2176: @114059
40891 /* 114059 */ GIM_Try, /*On fail goto*//*Label 2177*/ GIMT_Encode4(114099), // Rule ID 1172 //
40892 /* 114064 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40893 /* 114067 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40894 /* 114071 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40895 /* 114075 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40896 /* 114079 */ // (ssubsat:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VQSUBsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
40897 /* 114079 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv4i32),
40898 /* 114082 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40899 /* 114084 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40900 /* 114086 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40901 /* 114088 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40902 /* 114091 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40903 /* 114097 */ GIR_RootConstrainSelectedInstOperands,
40904 /* 114098 */ // GIR_Coverage, 1172,
40905 /* 114098 */ GIR_EraseRootFromParent_Done,
40906 /* 114099 */ // Label 2177: @114099
40907 /* 114099 */ GIM_Try, /*On fail goto*//*Label 2178*/ GIMT_Encode4(114160), // Rule ID 3894 //
40908 /* 114104 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40909 /* 114107 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40910 /* 114111 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40911 /* 114115 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40912 /* 114119 */ // (ssubsat:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VQSUBs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
40913 /* 114119 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40914 /* 114122 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40915 /* 114126 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40916 /* 114131 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs32),
40917 /* 114134 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40918 /* 114136 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
40919 /* 114138 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
40920 /* 114140 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40921 /* 114143 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40922 /* 114149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40923 /* 114155 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40924 /* 114158 */ GIR_RootConstrainSelectedInstOperands,
40925 /* 114159 */ // GIR_Coverage, 3894,
40926 /* 114159 */ GIR_EraseRootFromParent_Done,
40927 /* 114160 */ // Label 2178: @114160
40928 /* 114160 */ GIM_Reject,
40929 /* 114161 */ // Label 2175: @114161
40930 /* 114161 */ GIM_Reject,
40931 /* 114162 */ // Label 2160: @114162
40932 /* 114162 */ GIM_Try, /*On fail goto*//*Label 2179*/ GIMT_Encode4(114208), // Rule ID 1173 //
40933 /* 114167 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40934 /* 114170 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
40935 /* 114173 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
40936 /* 114176 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40937 /* 114180 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40938 /* 114184 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
40939 /* 114188 */ // (ssubsat:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VQSUBsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
40940 /* 114188 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i8),
40941 /* 114191 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40942 /* 114193 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40943 /* 114195 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40944 /* 114197 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40945 /* 114200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40946 /* 114206 */ GIR_RootConstrainSelectedInstOperands,
40947 /* 114207 */ // GIR_Coverage, 1173,
40948 /* 114207 */ GIR_EraseRootFromParent_Done,
40949 /* 114208 */ // Label 2179: @114208
40950 /* 114208 */ GIM_Reject,
40951 /* 114209 */ // Label 2161: @114209
40952 /* 114209 */ GIM_Try, /*On fail goto*//*Label 2180*/ GIMT_Encode4(114322),
40953 /* 114214 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
40954 /* 114217 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
40955 /* 114220 */ GIM_Try, /*On fail goto*//*Label 2181*/ GIMT_Encode4(114260), // Rule ID 1171 //
40956 /* 114225 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
40957 /* 114228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40958 /* 114232 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40959 /* 114236 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
40960 /* 114240 */ // (ssubsat:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VQSUBsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
40961 /* 114240 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv8i16),
40962 /* 114243 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
40963 /* 114245 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
40964 /* 114247 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
40965 /* 114249 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
40966 /* 114252 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40967 /* 114258 */ GIR_RootConstrainSelectedInstOperands,
40968 /* 114259 */ // GIR_Coverage, 1171,
40969 /* 114259 */ GIR_EraseRootFromParent_Done,
40970 /* 114260 */ // Label 2181: @114260
40971 /* 114260 */ GIM_Try, /*On fail goto*//*Label 2182*/ GIMT_Encode4(114321), // Rule ID 3891 //
40972 /* 114265 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
40973 /* 114268 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40974 /* 114272 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40975 /* 114276 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
40976 /* 114280 */ // (ssubsat:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VQSUBs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
40977 /* 114280 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
40978 /* 114283 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
40979 /* 114287 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
40980 /* 114292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs16),
40981 /* 114295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
40982 /* 114297 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
40983 /* 114299 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
40984 /* 114301 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
40985 /* 114304 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40986 /* 114310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
40987 /* 114316 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
40988 /* 114319 */ GIR_RootConstrainSelectedInstOperands,
40989 /* 114320 */ // GIR_Coverage, 3891,
40990 /* 114320 */ GIR_EraseRootFromParent_Done,
40991 /* 114321 */ // Label 2182: @114321
40992 /* 114321 */ GIM_Reject,
40993 /* 114322 */ // Label 2180: @114322
40994 /* 114322 */ GIM_Reject,
40995 /* 114323 */ // Label 2162: @114323
40996 /* 114323 */ GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(114436),
40997 /* 114328 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
40998 /* 114331 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
40999 /* 114334 */ GIM_Try, /*On fail goto*//*Label 2184*/ GIMT_Encode4(114374), // Rule ID 1174 //
41000 /* 114339 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
41001 /* 114342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41002 /* 114346 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41003 /* 114350 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41004 /* 114354 */ // (ssubsat:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VQSUBsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
41005 /* 114354 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VQSUBsv16i8),
41006 /* 114357 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41007 /* 114359 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
41008 /* 114361 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
41009 /* 114363 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41010 /* 114366 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41011 /* 114372 */ GIR_RootConstrainSelectedInstOperands,
41012 /* 114373 */ // GIR_Coverage, 1174,
41013 /* 114373 */ GIR_EraseRootFromParent_Done,
41014 /* 114374 */ // Label 2184: @114374
41015 /* 114374 */ GIM_Try, /*On fail goto*//*Label 2185*/ GIMT_Encode4(114435), // Rule ID 3888 //
41016 /* 114379 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
41017 /* 114382 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41018 /* 114386 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41019 /* 114390 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41020 /* 114394 */ // (ssubsat:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VQSUBs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
41021 /* 114394 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41022 /* 114397 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41023 /* 114401 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41024 /* 114406 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VQSUBs8),
41025 /* 114409 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
41026 /* 114411 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
41027 /* 114413 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
41028 /* 114415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41029 /* 114418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41030 /* 114424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41031 /* 114430 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41032 /* 114433 */ GIR_RootConstrainSelectedInstOperands,
41033 /* 114434 */ // GIR_Coverage, 3888,
41034 /* 114434 */ GIR_EraseRootFromParent_Done,
41035 /* 114435 */ // Label 2185: @114435
41036 /* 114435 */ GIM_Reject,
41037 /* 114436 */ // Label 2183: @114436
41038 /* 114436 */ GIM_Reject,
41039 /* 114437 */ // Label 2163: @114437
41040 /* 114437 */ GIM_Reject,
41041 /* 114438 */ // Label 40: @114438
41042 /* 114438 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2193*/ GIMT_Encode4(116790),
41043 /* 114449 */ /*GILLT_s16*//*Label 2186*/ GIMT_Encode4(114501),
41044 /* 114453 */ /*GILLT_s32*//*Label 2187*/ GIMT_Encode4(114548),
41045 /* 114457 */ /*GILLT_s64*//*Label 2188*/ GIMT_Encode4(116143), GIMT_Encode4(0),
41046 /* 114465 */ /*GILLT_v2s32*//*Label 2189*/ GIMT_Encode4(116190), GIMT_Encode4(0), GIMT_Encode4(0),
41047 /* 114477 */ /*GILLT_v4s16*//*Label 2190*/ GIMT_Encode4(116237),
41048 /* 114481 */ /*GILLT_v4s32*//*Label 2191*/ GIMT_Encode4(116422), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
41049 /* 114497 */ /*GILLT_v8s16*//*Label 2192*/ GIMT_Encode4(116536),
41050 /* 114501 */ // Label 2186: @114501
41051 /* 114501 */ GIM_Try, /*On fail goto*//*Label 2194*/ GIMT_Encode4(114547), // Rule ID 620 //
41052 /* 114506 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41053 /* 114509 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
41054 /* 114512 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41055 /* 114515 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41056 /* 114519 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41057 /* 114523 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41058 /* 114527 */ // (fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41059 /* 114527 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH),
41060 /* 114530 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
41061 /* 114532 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
41062 /* 114534 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
41063 /* 114536 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41064 /* 114539 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41065 /* 114545 */ GIR_RootConstrainSelectedInstOperands,
41066 /* 114546 */ // GIR_Coverage, 620,
41067 /* 114546 */ GIR_EraseRootFromParent_Done,
41068 /* 114547 */ // Label 2194: @114547
41069 /* 114547 */ GIM_Reject,
41070 /* 114548 */ // Label 2187: @114548
41071 /* 114548 */ GIM_Try, /*On fail goto*//*Label 2195*/ GIMT_Encode4(116142),
41072 /* 114553 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
41073 /* 114556 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41074 /* 114559 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41075 /* 114563 */ GIM_Try, /*On fail goto*//*Label 2196*/ GIMT_Encode4(114891), // Rule ID 6492 //
41076 /* 114568 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP),
41077 /* 114571 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41078 /* 114575 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41079 /* 114579 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41080 /* 114583 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41081 /* 114587 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41082 /* 114592 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41083 /* 114597 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41084 /* 114601 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41085 /* 114603 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41086 /* 114603 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
41087 /* 114606 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41088 /* 114610 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41089 /* 114615 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
41090 /* 114617 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
41091 /* 114620 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41092 /* 114624 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41093 /* 114629 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
41094 /* 114632 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41095 /* 114637 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
41096 /* 114640 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41097 /* 114644 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41098 /* 114649 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
41099 /* 114652 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
41100 /* 114656 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
41101 /* 114659 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41102 /* 114664 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41103 /* 114669 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41104 /* 114674 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41105 /* 114677 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41106 /* 114681 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41107 /* 114686 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41108 /* 114688 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41109 /* 114691 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41110 /* 114695 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41111 /* 114700 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41112 /* 114703 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41113 /* 114708 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41114 /* 114711 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41115 /* 114715 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41116 /* 114720 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41117 /* 114723 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
41118 /* 114727 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41119 /* 114730 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41120 /* 114735 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41121 /* 114740 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41122 /* 114745 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41123 /* 114748 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41124 /* 114752 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41125 /* 114757 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41126 /* 114759 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41127 /* 114762 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41128 /* 114766 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41129 /* 114771 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41130 /* 114774 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41131 /* 114779 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41132 /* 114782 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41133 /* 114786 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41134 /* 114791 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41135 /* 114794 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc
41136 /* 114798 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41137 /* 114801 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41138 /* 114806 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41139 /* 114811 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41140 /* 114816 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41141 /* 114819 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd),
41142 /* 114823 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41143 /* 114828 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41144 /* 114831 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41145 /* 114834 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
41146 /* 114837 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41147 /* 114840 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41148 /* 114846 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41149 /* 114848 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41150 /* 114851 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41151 /* 114855 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41152 /* 114860 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41153 /* 114863 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41154 /* 114868 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41155 /* 114871 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41156 /* 114873 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41157 /* 114880 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41158 /* 114885 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41159 /* 114890 */ // GIR_Coverage, 6492,
41160 /* 114890 */ GIR_EraseRootFromParent_Done,
41161 /* 114891 */ // Label 2196: @114891
41162 /* 114891 */ GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(115219), // Rule ID 6493 //
41163 /* 114896 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP),
41164 /* 114899 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41165 /* 114903 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41166 /* 114907 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41167 /* 114911 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41168 /* 114915 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41169 /* 114920 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41170 /* 114925 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41171 /* 114929 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41172 /* 114931 */ // (fadd:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b), SPR:{ *:[f32] }:$acc) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41173 /* 114931 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
41174 /* 114934 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41175 /* 114938 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41176 /* 114943 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
41177 /* 114945 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
41178 /* 114948 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41179 /* 114952 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41180 /* 114957 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
41181 /* 114960 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41182 /* 114965 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
41183 /* 114968 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41184 /* 114972 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41185 /* 114977 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
41186 /* 114980 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
41187 /* 114984 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
41188 /* 114987 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41189 /* 114992 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41190 /* 114997 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41191 /* 115002 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41192 /* 115005 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41193 /* 115009 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41194 /* 115014 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41195 /* 115016 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41196 /* 115019 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41197 /* 115023 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41198 /* 115028 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41199 /* 115031 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41200 /* 115036 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41201 /* 115039 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41202 /* 115043 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41203 /* 115048 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41204 /* 115051 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
41205 /* 115055 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41206 /* 115058 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41207 /* 115063 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41208 /* 115068 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41209 /* 115073 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41210 /* 115076 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41211 /* 115080 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41212 /* 115085 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41213 /* 115087 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41214 /* 115090 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41215 /* 115094 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41216 /* 115099 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41217 /* 115102 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41218 /* 115107 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41219 /* 115110 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41220 /* 115114 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41221 /* 115119 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41222 /* 115122 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/2, // acc
41223 /* 115126 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41224 /* 115129 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41225 /* 115134 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41226 /* 115139 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41227 /* 115144 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41228 /* 115147 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd),
41229 /* 115151 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41230 /* 115156 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41231 /* 115159 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41232 /* 115162 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
41233 /* 115165 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41234 /* 115168 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41235 /* 115174 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41236 /* 115176 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41237 /* 115179 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41238 /* 115183 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41239 /* 115188 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41240 /* 115191 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41241 /* 115196 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41242 /* 115199 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41243 /* 115201 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41244 /* 115208 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41245 /* 115213 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41246 /* 115218 */ // GIR_Coverage, 6493,
41247 /* 115218 */ GIR_EraseRootFromParent_Done,
41248 /* 115219 */ // Label 2197: @115219
41249 /* 115219 */ GIM_Try, /*On fail goto*//*Label 2198*/ GIMT_Encode4(115547), // Rule ID 3050 //
41250 /* 115224 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP),
41251 /* 115227 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41252 /* 115231 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41253 /* 115235 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41254 /* 115239 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41255 /* 115243 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41256 /* 115247 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41257 /* 115252 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41258 /* 115257 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41259 /* 115259 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41260 /* 115259 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
41261 /* 115262 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41262 /* 115266 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41263 /* 115271 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
41264 /* 115273 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
41265 /* 115276 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41266 /* 115280 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41267 /* 115285 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
41268 /* 115288 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41269 /* 115293 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
41270 /* 115296 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41271 /* 115300 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41272 /* 115305 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
41273 /* 115308 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
41274 /* 115312 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
41275 /* 115315 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41276 /* 115320 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41277 /* 115325 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41278 /* 115330 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41279 /* 115333 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41280 /* 115337 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41281 /* 115342 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41282 /* 115344 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41283 /* 115347 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41284 /* 115351 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41285 /* 115356 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41286 /* 115359 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41287 /* 115364 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41288 /* 115367 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41289 /* 115371 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41290 /* 115376 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41291 /* 115379 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
41292 /* 115383 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41293 /* 115386 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41294 /* 115391 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41295 /* 115396 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41296 /* 115401 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41297 /* 115404 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41298 /* 115408 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41299 /* 115413 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41300 /* 115415 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41301 /* 115418 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41302 /* 115422 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41303 /* 115427 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41304 /* 115430 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41305 /* 115435 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41306 /* 115438 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41307 /* 115442 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41308 /* 115447 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41309 /* 115450 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
41310 /* 115454 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41311 /* 115457 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41312 /* 115462 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41313 /* 115467 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41314 /* 115472 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41315 /* 115475 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLAfd),
41316 /* 115479 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41317 /* 115484 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41318 /* 115487 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41319 /* 115490 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
41320 /* 115493 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41321 /* 115496 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41322 /* 115502 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41323 /* 115504 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41324 /* 115507 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41325 /* 115511 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41326 /* 115516 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41327 /* 115519 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41328 /* 115524 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41329 /* 115527 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41330 /* 115529 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41331 /* 115536 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41332 /* 115541 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41333 /* 115546 */ // GIR_Coverage, 3050,
41334 /* 115546 */ GIR_EraseRootFromParent_Done,
41335 /* 115547 */ // Label 2198: @115547
41336 /* 115547 */ GIM_Try, /*On fail goto*//*Label 2199*/ GIMT_Encode4(115875), // Rule ID 3052 //
41337 /* 115552 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP),
41338 /* 115555 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41339 /* 115559 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41340 /* 115563 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41341 /* 115567 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41342 /* 115571 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41343 /* 115575 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41344 /* 115580 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41345 /* 115585 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41346 /* 115587 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMAfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41347 /* 115587 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
41348 /* 115590 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41349 /* 115594 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41350 /* 115599 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
41351 /* 115601 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
41352 /* 115604 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41353 /* 115608 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41354 /* 115613 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
41355 /* 115616 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41356 /* 115621 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
41357 /* 115624 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41358 /* 115628 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41359 /* 115633 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
41360 /* 115636 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
41361 /* 115640 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
41362 /* 115643 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41363 /* 115648 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41364 /* 115653 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41365 /* 115658 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41366 /* 115661 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41367 /* 115665 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41368 /* 115670 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41369 /* 115672 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41370 /* 115675 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41371 /* 115679 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41372 /* 115684 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41373 /* 115687 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41374 /* 115692 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41375 /* 115695 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41376 /* 115699 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41377 /* 115704 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41378 /* 115707 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
41379 /* 115711 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41380 /* 115714 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41381 /* 115719 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41382 /* 115724 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41383 /* 115729 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41384 /* 115732 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41385 /* 115736 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41386 /* 115741 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41387 /* 115743 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41388 /* 115746 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41389 /* 115750 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41390 /* 115755 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41391 /* 115758 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41392 /* 115763 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41393 /* 115766 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41394 /* 115770 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41395 /* 115775 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41396 /* 115778 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
41397 /* 115782 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41398 /* 115785 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41399 /* 115790 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41400 /* 115795 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41401 /* 115800 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41402 /* 115803 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMAfd),
41403 /* 115807 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41404 /* 115812 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41405 /* 115815 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41406 /* 115818 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
41407 /* 115821 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41408 /* 115824 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41409 /* 115830 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41410 /* 115832 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41411 /* 115835 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41412 /* 115839 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41413 /* 115844 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41414 /* 115847 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41415 /* 115852 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41416 /* 115855 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41417 /* 115857 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41418 /* 115864 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41419 /* 115869 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41420 /* 115874 */ // GIR_Coverage, 3052,
41421 /* 115874 */ GIR_EraseRootFromParent_Done,
41422 /* 115875 */ // Label 2199: @115875
41423 /* 115875 */ GIM_Try, /*On fail goto*//*Label 2200*/ GIMT_Encode4(115911), // Rule ID 618 //
41424 /* 115880 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
41425 /* 115883 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41426 /* 115887 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41427 /* 115891 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41428 /* 115891 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS),
41429 /* 115894 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
41430 /* 115896 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
41431 /* 115898 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
41432 /* 115900 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41433 /* 115903 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41434 /* 115909 */ GIR_RootConstrainSelectedInstOperands,
41435 /* 115910 */ // GIR_Coverage, 618,
41436 /* 115910 */ GIR_EraseRootFromParent_Done,
41437 /* 115911 */ // Label 2200: @115911
41438 /* 115911 */ GIM_Try, /*On fail goto*//*Label 2201*/ GIMT_Encode4(116141), // Rule ID 3047 //
41439 /* 115916 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
41440 /* 115919 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41441 /* 115923 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41442 /* 115927 */ // (fadd:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VADDfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41443 /* 115927 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41444 /* 115930 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41445 /* 115934 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41446 /* 115939 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41447 /* 115941 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41448 /* 115944 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41449 /* 115948 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41450 /* 115953 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41451 /* 115956 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41452 /* 115961 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41453 /* 115964 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41454 /* 115968 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41455 /* 115973 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41456 /* 115976 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
41457 /* 115980 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41458 /* 115983 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41459 /* 115988 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41460 /* 115993 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41461 /* 115998 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41462 /* 116001 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41463 /* 116005 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41464 /* 116010 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41465 /* 116012 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41466 /* 116015 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41467 /* 116019 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41468 /* 116024 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41469 /* 116027 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41470 /* 116032 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41471 /* 116035 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41472 /* 116039 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41473 /* 116044 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41474 /* 116047 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
41475 /* 116051 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41476 /* 116054 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41477 /* 116059 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41478 /* 116064 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41479 /* 116069 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41480 /* 116072 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VADDfd),
41481 /* 116076 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41482 /* 116081 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41483 /* 116084 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41484 /* 116087 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41485 /* 116090 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41486 /* 116096 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41487 /* 116098 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41488 /* 116101 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41489 /* 116105 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41490 /* 116110 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41491 /* 116113 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41492 /* 116118 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41493 /* 116121 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41494 /* 116123 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41495 /* 116130 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41496 /* 116135 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41497 /* 116140 */ // GIR_Coverage, 3047,
41498 /* 116140 */ GIR_EraseRootFromParent_Done,
41499 /* 116141 */ // Label 2201: @116141
41500 /* 116141 */ GIM_Reject,
41501 /* 116142 */ // Label 2195: @116142
41502 /* 116142 */ GIM_Reject,
41503 /* 116143 */ // Label 2188: @116143
41504 /* 116143 */ GIM_Try, /*On fail goto*//*Label 2202*/ GIMT_Encode4(116189), // Rule ID 616 //
41505 /* 116148 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
41506 /* 116151 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
41507 /* 116154 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
41508 /* 116157 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41509 /* 116161 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41510 /* 116165 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41511 /* 116169 */ // (fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
41512 /* 116169 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD),
41513 /* 116172 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
41514 /* 116174 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
41515 /* 116176 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
41516 /* 116178 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41517 /* 116181 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41518 /* 116187 */ GIR_RootConstrainSelectedInstOperands,
41519 /* 116188 */ // GIR_Coverage, 616,
41520 /* 116188 */ GIR_EraseRootFromParent_Done,
41521 /* 116189 */ // Label 2202: @116189
41522 /* 116189 */ GIM_Reject,
41523 /* 116190 */ // Label 2189: @116190
41524 /* 116190 */ GIM_Try, /*On fail goto*//*Label 2203*/ GIMT_Encode4(116236), // Rule ID 883 //
41525 /* 116195 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
41526 /* 116198 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
41527 /* 116201 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
41528 /* 116204 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41529 /* 116208 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41530 /* 116212 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41531 /* 116216 */ // (fadd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VADDfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
41532 /* 116216 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfd),
41533 /* 116219 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41534 /* 116221 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
41535 /* 116223 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
41536 /* 116225 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41537 /* 116228 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41538 /* 116234 */ GIR_RootConstrainSelectedInstOperands,
41539 /* 116235 */ // GIR_Coverage, 883,
41540 /* 116235 */ GIR_EraseRootFromParent_Done,
41541 /* 116236 */ // Label 2203: @116236
41542 /* 116236 */ GIM_Reject,
41543 /* 116237 */ // Label 2190: @116237
41544 /* 116237 */ GIM_Try, /*On fail goto*//*Label 2204*/ GIMT_Encode4(116421),
41545 /* 116242 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
41546 /* 116245 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
41547 /* 116248 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41548 /* 116252 */ GIM_Try, /*On fail goto*//*Label 2205*/ GIMT_Encode4(116318), // Rule ID 6128 //
41549 /* 116257 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
41550 /* 116260 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41551 /* 116264 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41552 /* 116268 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
41553 /* 116272 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
41554 /* 116276 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41555 /* 116281 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41556 /* 116286 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41557 /* 116290 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41558 /* 116292 */ // (fadd:{ *:[v4f16] } (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm), DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41559 /* 116292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd),
41560 /* 116295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41561 /* 116297 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
41562 /* 116299 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41563 /* 116303 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41564 /* 116307 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41565 /* 116310 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41566 /* 116316 */ GIR_RootConstrainSelectedInstOperands,
41567 /* 116317 */ // GIR_Coverage, 6128,
41568 /* 116317 */ GIR_EraseRootFromParent_Done,
41569 /* 116318 */ // Label 2205: @116318
41570 /* 116318 */ GIM_Try, /*On fail goto*//*Label 2206*/ GIMT_Encode4(116384), // Rule ID 1100 //
41571 /* 116323 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
41572 /* 116326 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41573 /* 116330 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41574 /* 116334 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41575 /* 116338 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
41576 /* 116342 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
41577 /* 116346 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41578 /* 116351 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41579 /* 116356 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41580 /* 116358 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41581 /* 116358 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd),
41582 /* 116361 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41583 /* 116363 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
41584 /* 116365 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41585 /* 116369 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41586 /* 116373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41587 /* 116376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41588 /* 116382 */ GIR_RootConstrainSelectedInstOperands,
41589 /* 116383 */ // GIR_Coverage, 1100,
41590 /* 116383 */ GIR_EraseRootFromParent_Done,
41591 /* 116384 */ // Label 2206: @116384
41592 /* 116384 */ GIM_Try, /*On fail goto*//*Label 2207*/ GIMT_Encode4(116420), // Rule ID 885 //
41593 /* 116389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
41594 /* 116392 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41595 /* 116396 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
41596 /* 116400 */ // (fadd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VADDhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
41597 /* 116400 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhd),
41598 /* 116403 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41599 /* 116405 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
41600 /* 116407 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
41601 /* 116409 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41602 /* 116412 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41603 /* 116418 */ GIR_RootConstrainSelectedInstOperands,
41604 /* 116419 */ // GIR_Coverage, 885,
41605 /* 116419 */ GIR_EraseRootFromParent_Done,
41606 /* 116420 */ // Label 2207: @116420
41607 /* 116420 */ GIM_Reject,
41608 /* 116421 */ // Label 2204: @116421
41609 /* 116421 */ GIM_Reject,
41610 /* 116422 */ // Label 2191: @116422
41611 /* 116422 */ GIM_Try, /*On fail goto*//*Label 2208*/ GIMT_Encode4(116535),
41612 /* 116427 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
41613 /* 116430 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
41614 /* 116433 */ GIM_Try, /*On fail goto*//*Label 2209*/ GIMT_Encode4(116473), // Rule ID 884 //
41615 /* 116438 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
41616 /* 116441 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41617 /* 116445 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41618 /* 116449 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41619 /* 116453 */ // (fadd:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VADDfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
41620 /* 116453 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDfq),
41621 /* 116456 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41622 /* 116458 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
41623 /* 116460 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
41624 /* 116462 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41625 /* 116465 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41626 /* 116471 */ GIR_RootConstrainSelectedInstOperands,
41627 /* 116472 */ // GIR_Coverage, 884,
41628 /* 116472 */ GIR_EraseRootFromParent_Done,
41629 /* 116473 */ // Label 2209: @116473
41630 /* 116473 */ GIM_Try, /*On fail goto*//*Label 2210*/ GIMT_Encode4(116534), // Rule ID 4398 //
41631 /* 116478 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
41632 /* 116481 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41633 /* 116485 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41634 /* 116489 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41635 /* 116493 */ // (fadd:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VADDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
41636 /* 116493 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41637 /* 116496 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41638 /* 116500 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41639 /* 116505 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf32),
41640 /* 116508 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
41641 /* 116510 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
41642 /* 116512 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
41643 /* 116514 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41644 /* 116517 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41645 /* 116523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41646 /* 116529 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41647 /* 116532 */ GIR_RootConstrainSelectedInstOperands,
41648 /* 116533 */ // GIR_Coverage, 4398,
41649 /* 116533 */ GIR_EraseRootFromParent_Done,
41650 /* 116534 */ // Label 2210: @116534
41651 /* 116534 */ GIM_Reject,
41652 /* 116535 */ // Label 2208: @116535
41653 /* 116535 */ GIM_Reject,
41654 /* 116536 */ // Label 2192: @116536
41655 /* 116536 */ GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(116789),
41656 /* 116541 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
41657 /* 116544 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
41658 /* 116547 */ GIM_Try, /*On fail goto*//*Label 2212*/ GIMT_Encode4(116617), // Rule ID 6129 //
41659 /* 116552 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
41660 /* 116555 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41661 /* 116559 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
41662 /* 116563 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41663 /* 116567 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
41664 /* 116571 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
41665 /* 116575 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41666 /* 116580 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41667 /* 116585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41668 /* 116589 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41669 /* 116591 */ // (fadd:{ *:[v8f16] } (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm), QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41670 /* 116591 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq),
41671 /* 116594 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41672 /* 116596 */ GIR_RootToRootCopy, /*OpIdx*/2, // src1
41673 /* 116598 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41674 /* 116602 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41675 /* 116606 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41676 /* 116609 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41677 /* 116615 */ GIR_RootConstrainSelectedInstOperands,
41678 /* 116616 */ // GIR_Coverage, 6129,
41679 /* 116616 */ GIR_EraseRootFromParent_Done,
41680 /* 116617 */ // Label 2212: @116617
41681 /* 116617 */ GIM_Try, /*On fail goto*//*Label 2213*/ GIMT_Encode4(116687), // Rule ID 1101 //
41682 /* 116622 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
41683 /* 116625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41684 /* 116629 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41685 /* 116633 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41686 /* 116637 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41687 /* 116641 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
41688 /* 116645 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
41689 /* 116649 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41690 /* 116654 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41691 /* 116659 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41692 /* 116661 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41693 /* 116661 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq),
41694 /* 116664 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41695 /* 116666 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
41696 /* 116668 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
41697 /* 116672 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
41698 /* 116676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41699 /* 116679 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41700 /* 116685 */ GIR_RootConstrainSelectedInstOperands,
41701 /* 116686 */ // GIR_Coverage, 1101,
41702 /* 116686 */ GIR_EraseRootFromParent_Done,
41703 /* 116687 */ // Label 2213: @116687
41704 /* 116687 */ GIM_Try, /*On fail goto*//*Label 2214*/ GIMT_Encode4(116727), // Rule ID 886 //
41705 /* 116692 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
41706 /* 116695 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41707 /* 116699 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41708 /* 116703 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
41709 /* 116707 */ // (fadd:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VADDhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
41710 /* 116707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDhq),
41711 /* 116710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
41712 /* 116712 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
41713 /* 116714 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
41714 /* 116716 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41715 /* 116719 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41716 /* 116725 */ GIR_RootConstrainSelectedInstOperands,
41717 /* 116726 */ // GIR_Coverage, 886,
41718 /* 116726 */ GIR_EraseRootFromParent_Done,
41719 /* 116727 */ // Label 2214: @116727
41720 /* 116727 */ GIM_Try, /*On fail goto*//*Label 2215*/ GIMT_Encode4(116788), // Rule ID 4405 //
41721 /* 116732 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
41722 /* 116735 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41723 /* 116739 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41724 /* 116743 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
41725 /* 116747 */ // (fadd:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VADDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
41726 /* 116747 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
41727 /* 116750 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41728 /* 116754 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41729 /* 116759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDf16),
41730 /* 116762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
41731 /* 116764 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
41732 /* 116766 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
41733 /* 116768 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
41734 /* 116771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41735 /* 116777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41736 /* 116783 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
41737 /* 116786 */ GIR_RootConstrainSelectedInstOperands,
41738 /* 116787 */ // GIR_Coverage, 4405,
41739 /* 116787 */ GIR_EraseRootFromParent_Done,
41740 /* 116788 */ // Label 2215: @116788
41741 /* 116788 */ GIM_Reject,
41742 /* 116789 */ // Label 2211: @116789
41743 /* 116789 */ GIM_Reject,
41744 /* 116790 */ // Label 2193: @116790
41745 /* 116790 */ GIM_Reject,
41746 /* 116791 */ // Label 41: @116791
41747 /* 116791 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2223*/ GIMT_Encode4(118467),
41748 /* 116802 */ /*GILLT_s16*//*Label 2216*/ GIMT_Encode4(116854),
41749 /* 116806 */ /*GILLT_s32*//*Label 2217*/ GIMT_Encode4(116901),
41750 /* 116810 */ /*GILLT_s64*//*Label 2218*/ GIMT_Encode4(117828), GIMT_Encode4(0),
41751 /* 116818 */ /*GILLT_v2s32*//*Label 2219*/ GIMT_Encode4(117875), GIMT_Encode4(0), GIMT_Encode4(0),
41752 /* 116830 */ /*GILLT_v4s16*//*Label 2220*/ GIMT_Encode4(117922),
41753 /* 116834 */ /*GILLT_v4s32*//*Label 2221*/ GIMT_Encode4(118099), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
41754 /* 116850 */ /*GILLT_v8s16*//*Label 2222*/ GIMT_Encode4(118213),
41755 /* 116854 */ // Label 2216: @116854
41756 /* 116854 */ GIM_Try, /*On fail goto*//*Label 2224*/ GIMT_Encode4(116900), // Rule ID 626 //
41757 /* 116859 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
41758 /* 116862 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
41759 /* 116865 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
41760 /* 116868 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41761 /* 116872 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41762 /* 116876 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
41763 /* 116880 */ // (fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
41764 /* 116880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH),
41765 /* 116883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
41766 /* 116885 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
41767 /* 116887 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
41768 /* 116889 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41769 /* 116892 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41770 /* 116898 */ GIR_RootConstrainSelectedInstOperands,
41771 /* 116899 */ // GIR_Coverage, 626,
41772 /* 116899 */ GIR_EraseRootFromParent_Done,
41773 /* 116900 */ // Label 2224: @116900
41774 /* 116900 */ GIM_Reject,
41775 /* 116901 */ // Label 2217: @116901
41776 /* 116901 */ GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(117827),
41777 /* 116906 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
41778 /* 116909 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
41779 /* 116912 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41780 /* 116916 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41781 /* 116920 */ GIM_Try, /*On fail goto*//*Label 2226*/ GIMT_Encode4(117244), // Rule ID 3051 //
41782 /* 116925 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseFPVMLx_UseNEONForFP),
41783 /* 116928 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41784 /* 116932 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41785 /* 116936 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41786 /* 116940 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41787 /* 116944 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41788 /* 116949 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41789 /* 116954 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41790 /* 116956 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMLSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41791 /* 116956 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
41792 /* 116959 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41793 /* 116963 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41794 /* 116968 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
41795 /* 116970 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
41796 /* 116973 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41797 /* 116977 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41798 /* 116982 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
41799 /* 116985 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41800 /* 116990 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
41801 /* 116993 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41802 /* 116997 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41803 /* 117002 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
41804 /* 117005 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
41805 /* 117009 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
41806 /* 117012 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41807 /* 117017 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41808 /* 117022 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41809 /* 117027 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41810 /* 117030 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41811 /* 117034 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41812 /* 117039 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41813 /* 117041 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41814 /* 117044 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41815 /* 117048 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41816 /* 117053 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41817 /* 117056 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41818 /* 117061 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41819 /* 117064 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41820 /* 117068 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41821 /* 117073 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41822 /* 117076 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
41823 /* 117080 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41824 /* 117083 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41825 /* 117088 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41826 /* 117093 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41827 /* 117098 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41828 /* 117101 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41829 /* 117105 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41830 /* 117110 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41831 /* 117112 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41832 /* 117115 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41833 /* 117119 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41834 /* 117124 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41835 /* 117127 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41836 /* 117132 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41837 /* 117135 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41838 /* 117139 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41839 /* 117144 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41840 /* 117147 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
41841 /* 117151 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41842 /* 117154 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41843 /* 117159 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41844 /* 117164 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41845 /* 117169 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41846 /* 117172 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMLSfd),
41847 /* 117176 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41848 /* 117181 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41849 /* 117184 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41850 /* 117187 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
41851 /* 117190 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41852 /* 117193 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41853 /* 117199 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41854 /* 117201 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41855 /* 117204 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41856 /* 117208 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41857 /* 117213 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41858 /* 117216 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41859 /* 117221 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41860 /* 117224 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41861 /* 117226 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41862 /* 117233 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41863 /* 117238 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41864 /* 117243 */ // GIR_Coverage, 3051,
41865 /* 117243 */ GIR_EraseRootFromParent_Done,
41866 /* 117244 */ // Label 2226: @117244
41867 /* 117244 */ GIM_Try, /*On fail goto*//*Label 2227*/ GIMT_Encode4(117568), // Rule ID 3053 //
41868 /* 117249 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4_UseFusedMAC_UseNEONForFP),
41869 /* 117252 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
41870 /* 117256 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
41871 /* 117260 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
41872 /* 117264 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
41873 /* 117268 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41874 /* 117273 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41875 /* 117278 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
41876 /* 117280 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$acc, (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VFMSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$acc, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41877 /* 117280 */ GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_v2s32,
41878 /* 117283 */ GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41879 /* 117287 */ GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41880 /* 117292 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/11,
41881 /* 117294 */ GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_v2s32,
41882 /* 117297 */ GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41883 /* 117301 */ GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41884 /* 117306 */ GIR_AddSimpleTempRegister, /*InsnID*/10, /*TempRegID*/10,
41885 /* 117309 */ GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41886 /* 117314 */ GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_v2s32,
41887 /* 117317 */ GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41888 /* 117321 */ GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41889 /* 117326 */ GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9,
41890 /* 117329 */ GIR_Copy, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, // b
41891 /* 117333 */ GIR_AddImm8, /*InsnID*/9, /*Imm*/17,
41892 /* 117336 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41893 /* 117341 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41894 /* 117346 */ GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41895 /* 117351 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41896 /* 117354 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41897 /* 117358 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41898 /* 117363 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41899 /* 117365 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41900 /* 117368 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41901 /* 117372 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41902 /* 117377 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41903 /* 117380 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41904 /* 117385 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41905 /* 117388 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41906 /* 117392 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41907 /* 117397 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41908 /* 117400 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, // a
41909 /* 117404 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41910 /* 117407 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41911 /* 117412 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41912 /* 117417 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41913 /* 117422 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41914 /* 117425 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41915 /* 117429 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41916 /* 117434 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41917 /* 117436 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41918 /* 117439 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41919 /* 117443 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41920 /* 117448 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41921 /* 117451 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41922 /* 117456 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41923 /* 117459 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41924 /* 117463 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41925 /* 117468 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
41926 /* 117471 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // acc
41927 /* 117475 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
41928 /* 117478 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41929 /* 117483 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41930 /* 117488 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41931 /* 117493 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
41932 /* 117496 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VFMSfd),
41933 /* 117500 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41934 /* 117505 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
41935 /* 117508 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
41936 /* 117511 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/8,
41937 /* 117514 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
41938 /* 117517 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41939 /* 117523 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
41940 /* 117525 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
41941 /* 117528 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41942 /* 117532 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41943 /* 117537 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
41944 /* 117540 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41945 /* 117545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41946 /* 117548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
41947 /* 117550 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
41948 /* 117557 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
41949 /* 117562 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41950 /* 117567 */ // GIR_Coverage, 3053,
41951 /* 117567 */ GIR_EraseRootFromParent_Done,
41952 /* 117568 */ // Label 2227: @117568
41953 /* 117568 */ GIM_Try, /*On fail goto*//*Label 2228*/ GIMT_Encode4(117600), // Rule ID 624 //
41954 /* 117573 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
41955 /* 117576 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41956 /* 117580 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
41957 /* 117580 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS),
41958 /* 117583 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
41959 /* 117585 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
41960 /* 117587 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
41961 /* 117589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
41962 /* 117592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
41963 /* 117598 */ GIR_RootConstrainSelectedInstOperands,
41964 /* 117599 */ // GIR_Coverage, 624,
41965 /* 117599 */ GIR_EraseRootFromParent_Done,
41966 /* 117600 */ // Label 2228: @117600
41967 /* 117600 */ GIM_Try, /*On fail goto*//*Label 2229*/ GIMT_Encode4(117826), // Rule ID 3048 //
41968 /* 117605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
41969 /* 117608 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
41970 /* 117612 */ // (fsub:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VSUBfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
41971 /* 117612 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
41972 /* 117615 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41973 /* 117619 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41974 /* 117624 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
41975 /* 117626 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
41976 /* 117629 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41977 /* 117633 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41978 /* 117638 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
41979 /* 117641 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41980 /* 117646 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
41981 /* 117649 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
41982 /* 117653 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41983 /* 117658 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
41984 /* 117661 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
41985 /* 117665 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
41986 /* 117668 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41987 /* 117673 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41988 /* 117678 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
41989 /* 117683 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
41990 /* 117686 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
41991 /* 117690 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41992 /* 117695 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
41993 /* 117697 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
41994 /* 117700 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
41995 /* 117704 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
41996 /* 117709 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
41997 /* 117712 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
41998 /* 117717 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
41999 /* 117720 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
42000 /* 117724 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42001 /* 117729 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
42002 /* 117732 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
42003 /* 117736 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
42004 /* 117739 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42005 /* 117744 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42006 /* 117749 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
42007 /* 117754 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
42008 /* 117757 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VSUBfd),
42009 /* 117761 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42010 /* 117766 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
42011 /* 117769 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
42012 /* 117772 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
42013 /* 117775 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42014 /* 117781 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42015 /* 117783 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
42016 /* 117786 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42017 /* 117790 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42018 /* 117795 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
42019 /* 117798 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42020 /* 117803 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42021 /* 117806 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42022 /* 117808 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
42023 /* 117815 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42024 /* 117820 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42025 /* 117825 */ // GIR_Coverage, 3048,
42026 /* 117825 */ GIR_EraseRootFromParent_Done,
42027 /* 117826 */ // Label 2229: @117826
42028 /* 117826 */ GIM_Reject,
42029 /* 117827 */ // Label 2225: @117827
42030 /* 117827 */ GIM_Reject,
42031 /* 117828 */ // Label 2218: @117828
42032 /* 117828 */ GIM_Try, /*On fail goto*//*Label 2230*/ GIMT_Encode4(117874), // Rule ID 622 //
42033 /* 117833 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
42034 /* 117836 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
42035 /* 117839 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
42036 /* 117842 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42037 /* 117846 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42038 /* 117850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42039 /* 117854 */ // (fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42040 /* 117854 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD),
42041 /* 117857 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42042 /* 117859 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
42043 /* 117861 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
42044 /* 117863 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42045 /* 117866 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42046 /* 117872 */ GIR_RootConstrainSelectedInstOperands,
42047 /* 117873 */ // GIR_Coverage, 622,
42048 /* 117873 */ GIR_EraseRootFromParent_Done,
42049 /* 117874 */ // Label 2230: @117874
42050 /* 117874 */ GIM_Reject,
42051 /* 117875 */ // Label 2219: @117875
42052 /* 117875 */ GIM_Try, /*On fail goto*//*Label 2231*/ GIMT_Encode4(117921), // Rule ID 1129 //
42053 /* 117880 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42054 /* 117883 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
42055 /* 117886 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42056 /* 117889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42057 /* 117893 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42058 /* 117897 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42059 /* 117901 */ // (fsub:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VSUBfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
42060 /* 117901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfd),
42061 /* 117904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42062 /* 117906 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
42063 /* 117908 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42064 /* 117910 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42065 /* 117913 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42066 /* 117919 */ GIR_RootConstrainSelectedInstOperands,
42067 /* 117920 */ // GIR_Coverage, 1129,
42068 /* 117920 */ GIR_EraseRootFromParent_Done,
42069 /* 117921 */ // Label 2231: @117921
42070 /* 117921 */ GIM_Reject,
42071 /* 117922 */ // Label 2220: @117922
42072 /* 117922 */ GIM_Try, /*On fail goto*//*Label 2232*/ GIMT_Encode4(118098),
42073 /* 117927 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
42074 /* 117930 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
42075 /* 117933 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42076 /* 117937 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42077 /* 117941 */ GIM_Try, /*On fail goto*//*Label 2233*/ GIMT_Encode4(118003), // Rule ID 1066 //
42078 /* 117946 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx),
42079 /* 117949 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42080 /* 117953 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
42081 /* 117957 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
42082 /* 117961 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
42083 /* 117965 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42084 /* 117970 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42085 /* 117975 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42086 /* 117977 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VMLShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
42087 /* 117977 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShd),
42088 /* 117980 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42089 /* 117982 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
42090 /* 117984 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42091 /* 117988 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
42092 /* 117992 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42093 /* 117995 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42094 /* 118001 */ GIR_RootConstrainSelectedInstOperands,
42095 /* 118002 */ // GIR_Coverage, 1066,
42096 /* 118002 */ GIR_EraseRootFromParent_Done,
42097 /* 118003 */ // Label 2233: @118003
42098 /* 118003 */ GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(118065), // Rule ID 1110 //
42099 /* 118008 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
42100 /* 118011 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42101 /* 118015 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
42102 /* 118019 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16,
42103 /* 118023 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16,
42104 /* 118027 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42105 /* 118032 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42106 /* 118037 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42107 /* 118039 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)) => (VFMShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
42108 /* 118039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShd),
42109 /* 118042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42110 /* 118044 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
42111 /* 118046 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42112 /* 118050 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
42113 /* 118054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42114 /* 118057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42115 /* 118063 */ GIR_RootConstrainSelectedInstOperands,
42116 /* 118064 */ // GIR_Coverage, 1110,
42117 /* 118064 */ GIR_EraseRootFromParent_Done,
42118 /* 118065 */ // Label 2234: @118065
42119 /* 118065 */ GIM_Try, /*On fail goto*//*Label 2235*/ GIMT_Encode4(118097), // Rule ID 1131 //
42120 /* 118070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42121 /* 118073 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42122 /* 118077 */ // (fsub:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VSUBhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
42123 /* 118077 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhd),
42124 /* 118080 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42125 /* 118082 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
42126 /* 118084 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42127 /* 118086 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42128 /* 118089 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42129 /* 118095 */ GIR_RootConstrainSelectedInstOperands,
42130 /* 118096 */ // GIR_Coverage, 1131,
42131 /* 118096 */ GIR_EraseRootFromParent_Done,
42132 /* 118097 */ // Label 2235: @118097
42133 /* 118097 */ GIM_Reject,
42134 /* 118098 */ // Label 2232: @118098
42135 /* 118098 */ GIM_Reject,
42136 /* 118099 */ // Label 2221: @118099
42137 /* 118099 */ GIM_Try, /*On fail goto*//*Label 2236*/ GIMT_Encode4(118212),
42138 /* 118104 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42139 /* 118107 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42140 /* 118110 */ GIM_Try, /*On fail goto*//*Label 2237*/ GIMT_Encode4(118150), // Rule ID 1130 //
42141 /* 118115 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42142 /* 118118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42143 /* 118122 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42144 /* 118126 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42145 /* 118130 */ // (fsub:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VSUBfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
42146 /* 118130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBfq),
42147 /* 118133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42148 /* 118135 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
42149 /* 118137 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42150 /* 118139 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42151 /* 118142 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42152 /* 118148 */ GIR_RootConstrainSelectedInstOperands,
42153 /* 118149 */ // GIR_Coverage, 1130,
42154 /* 118149 */ GIR_EraseRootFromParent_Done,
42155 /* 118150 */ // Label 2237: @118150
42156 /* 118150 */ GIM_Try, /*On fail goto*//*Label 2238*/ GIMT_Encode4(118211), // Rule ID 4412 //
42157 /* 118155 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
42158 /* 118158 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42159 /* 118162 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42160 /* 118166 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42161 /* 118170 */ // (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VSUBf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
42162 /* 118170 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42163 /* 118173 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42164 /* 118177 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42165 /* 118182 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf32),
42166 /* 118185 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42167 /* 118187 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
42168 /* 118189 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
42169 /* 118191 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42170 /* 118194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42171 /* 118200 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42172 /* 118206 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42173 /* 118209 */ GIR_RootConstrainSelectedInstOperands,
42174 /* 118210 */ // GIR_Coverage, 4412,
42175 /* 118210 */ GIR_EraseRootFromParent_Done,
42176 /* 118211 */ // Label 2238: @118211
42177 /* 118211 */ GIM_Reject,
42178 /* 118212 */ // Label 2236: @118212
42179 /* 118212 */ GIM_Reject,
42180 /* 118213 */ // Label 2222: @118213
42181 /* 118213 */ GIM_Try, /*On fail goto*//*Label 2239*/ GIMT_Encode4(118466),
42182 /* 118218 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42183 /* 118221 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
42184 /* 118224 */ GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(118294), // Rule ID 1067 //
42185 /* 118229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFPVMLx),
42186 /* 118232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42187 /* 118236 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42188 /* 118240 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42189 /* 118244 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
42190 /* 118248 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
42191 /* 118252 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
42192 /* 118256 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42193 /* 118261 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42194 /* 118266 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42195 /* 118268 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VMLShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
42196 /* 118268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMLShq),
42197 /* 118271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42198 /* 118273 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
42199 /* 118275 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42200 /* 118279 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
42201 /* 118283 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42202 /* 118286 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42203 /* 118292 */ GIR_RootConstrainSelectedInstOperands,
42204 /* 118293 */ // GIR_Coverage, 1067,
42205 /* 118293 */ GIR_EraseRootFromParent_Done,
42206 /* 118294 */ // Label 2240: @118294
42207 /* 118294 */ GIM_Try, /*On fail goto*//*Label 2241*/ GIMT_Encode4(118364), // Rule ID 1111 //
42208 /* 118299 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_UseFusedMAC),
42209 /* 118302 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42210 /* 118306 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42211 /* 118310 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42212 /* 118314 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
42213 /* 118318 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
42214 /* 118322 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
42215 /* 118326 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42216 /* 118331 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42217 /* 118336 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42218 /* 118338 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)) => (VFMShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
42219 /* 118338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMShq),
42220 /* 118341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42221 /* 118343 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
42222 /* 118345 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
42223 /* 118349 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Vm
42224 /* 118353 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42225 /* 118356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42226 /* 118362 */ GIR_RootConstrainSelectedInstOperands,
42227 /* 118363 */ // GIR_Coverage, 1111,
42228 /* 118363 */ GIR_EraseRootFromParent_Done,
42229 /* 118364 */ // Label 2241: @118364
42230 /* 118364 */ GIM_Try, /*On fail goto*//*Label 2242*/ GIMT_Encode4(118404), // Rule ID 1132 //
42231 /* 118369 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42232 /* 118372 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42233 /* 118376 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42234 /* 118380 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42235 /* 118384 */ // (fsub:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VSUBhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
42236 /* 118384 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBhq),
42237 /* 118387 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42238 /* 118389 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
42239 /* 118391 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42240 /* 118393 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42241 /* 118396 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42242 /* 118402 */ GIR_RootConstrainSelectedInstOperands,
42243 /* 118403 */ // GIR_Coverage, 1132,
42244 /* 118403 */ GIR_EraseRootFromParent_Done,
42245 /* 118404 */ // Label 2242: @118404
42246 /* 118404 */ GIM_Try, /*On fail goto*//*Label 2243*/ GIMT_Encode4(118465), // Rule ID 4419 //
42247 /* 118409 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
42248 /* 118412 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42249 /* 118416 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42250 /* 118420 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42251 /* 118424 */ // (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VSUBf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
42252 /* 118424 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42253 /* 118427 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42254 /* 118431 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42255 /* 118436 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VSUBf16),
42256 /* 118439 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42257 /* 118441 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
42258 /* 118443 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
42259 /* 118445 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42260 /* 118448 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42261 /* 118454 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42262 /* 118460 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42263 /* 118463 */ GIR_RootConstrainSelectedInstOperands,
42264 /* 118464 */ // GIR_Coverage, 4419,
42265 /* 118464 */ GIR_EraseRootFromParent_Done,
42266 /* 118465 */ // Label 2243: @118465
42267 /* 118465 */ GIM_Reject,
42268 /* 118466 */ // Label 2239: @118466
42269 /* 118466 */ GIM_Reject,
42270 /* 118467 */ // Label 2223: @118467
42271 /* 118467 */ GIM_Reject,
42272 /* 118468 */ // Label 42: @118468
42273 /* 118468 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2251*/ GIMT_Encode4(119448),
42274 /* 118479 */ /*GILLT_s16*//*Label 2244*/ GIMT_Encode4(118531),
42275 /* 118483 */ /*GILLT_s32*//*Label 2245*/ GIMT_Encode4(118578),
42276 /* 118487 */ /*GILLT_s64*//*Label 2246*/ GIMT_Encode4(118967), GIMT_Encode4(0),
42277 /* 118495 */ /*GILLT_v2s32*//*Label 2247*/ GIMT_Encode4(119126), GIMT_Encode4(0), GIMT_Encode4(0),
42278 /* 118507 */ /*GILLT_v4s16*//*Label 2248*/ GIMT_Encode4(119173),
42279 /* 118511 */ /*GILLT_v4s32*//*Label 2249*/ GIMT_Encode4(119220), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
42280 /* 118527 */ /*GILLT_v8s16*//*Label 2250*/ GIMT_Encode4(119334),
42281 /* 118531 */ // Label 2244: @118531
42282 /* 118531 */ GIM_Try, /*On fail goto*//*Label 2252*/ GIMT_Encode4(118577), // Rule ID 638 //
42283 /* 118536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42284 /* 118539 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
42285 /* 118542 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
42286 /* 118545 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42287 /* 118549 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42288 /* 118553 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42289 /* 118557 */ // (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42290 /* 118557 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH),
42291 /* 118560 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42292 /* 118562 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
42293 /* 118564 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42294 /* 118566 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42295 /* 118569 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42296 /* 118575 */ GIR_RootConstrainSelectedInstOperands,
42297 /* 118576 */ // GIR_Coverage, 638,
42298 /* 118576 */ GIR_EraseRootFromParent_Done,
42299 /* 118577 */ // Label 2252: @118577
42300 /* 118577 */ GIM_Reject,
42301 /* 118578 */ // Label 2245: @118578
42302 /* 118578 */ GIM_Try, /*On fail goto*//*Label 2253*/ GIMT_Encode4(118966),
42303 /* 118583 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
42304 /* 118586 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
42305 /* 118589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42306 /* 118593 */ GIM_Try, /*On fail goto*//*Label 2254*/ GIMT_Encode4(118646), // Rule ID 2463 //
42307 /* 118598 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NoHonorSignDependentRounding),
42308 /* 118601 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42309 /* 118605 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42310 /* 118609 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42311 /* 118613 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42312 /* 118618 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42313 /* 118622 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42314 /* 118624 */ // (fmul:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a), SPR:{ *:[f32] }:$b) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
42315 /* 118624 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
42316 /* 118627 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42317 /* 118629 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
42318 /* 118633 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
42319 /* 118635 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42320 /* 118638 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42321 /* 118644 */ GIR_RootConstrainSelectedInstOperands,
42322 /* 118645 */ // GIR_Coverage, 2463,
42323 /* 118645 */ GIR_EraseRootFromParent_Done,
42324 /* 118646 */ // Label 2254: @118646
42325 /* 118646 */ GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(118699), // Rule ID 6255 //
42326 /* 118651 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_NoHonorSignDependentRounding),
42327 /* 118654 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42328 /* 118658 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42329 /* 118662 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42330 /* 118666 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42331 /* 118670 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42332 /* 118675 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42333 /* 118677 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$b, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b)
42334 /* 118677 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
42335 /* 118680 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42336 /* 118682 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
42337 /* 118686 */ GIR_RootToRootCopy, /*OpIdx*/1, // b
42338 /* 118688 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42339 /* 118691 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42340 /* 118697 */ GIR_RootConstrainSelectedInstOperands,
42341 /* 118698 */ // GIR_Coverage, 6255,
42342 /* 118698 */ GIR_EraseRootFromParent_Done,
42343 /* 118699 */ // Label 2255: @118699
42344 /* 118699 */ GIM_Try, /*On fail goto*//*Label 2256*/ GIMT_Encode4(118735), // Rule ID 636 //
42345 /* 118704 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
42346 /* 118707 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42347 /* 118711 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42348 /* 118715 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42349 /* 118715 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS),
42350 /* 118718 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42351 /* 118720 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
42352 /* 118722 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42353 /* 118724 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42354 /* 118727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42355 /* 118733 */ GIR_RootConstrainSelectedInstOperands,
42356 /* 118734 */ // GIR_Coverage, 636,
42357 /* 118734 */ GIR_EraseRootFromParent_Done,
42358 /* 118735 */ // Label 2256: @118735
42359 /* 118735 */ GIM_Try, /*On fail goto*//*Label 2257*/ GIMT_Encode4(118965), // Rule ID 3049 //
42360 /* 118740 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
42361 /* 118743 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42362 /* 118747 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42363 /* 118751 */ // (fmul:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMULfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
42364 /* 118751 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
42365 /* 118754 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42366 /* 118758 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42367 /* 118763 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
42368 /* 118765 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
42369 /* 118768 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42370 /* 118772 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42371 /* 118777 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
42372 /* 118780 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42373 /* 118785 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
42374 /* 118788 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
42375 /* 118792 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42376 /* 118797 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
42377 /* 118800 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
42378 /* 118804 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
42379 /* 118807 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42380 /* 118812 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42381 /* 118817 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
42382 /* 118822 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
42383 /* 118825 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42384 /* 118829 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42385 /* 118834 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
42386 /* 118836 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
42387 /* 118839 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42388 /* 118843 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42389 /* 118848 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
42390 /* 118851 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42391 /* 118856 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
42392 /* 118859 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
42393 /* 118863 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42394 /* 118868 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
42395 /* 118871 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
42396 /* 118875 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
42397 /* 118878 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42398 /* 118883 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42399 /* 118888 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
42400 /* 118893 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
42401 /* 118896 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMULfd),
42402 /* 118900 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42403 /* 118905 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
42404 /* 118908 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
42405 /* 118911 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
42406 /* 118914 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42407 /* 118920 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
42408 /* 118922 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
42409 /* 118925 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42410 /* 118929 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42411 /* 118934 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
42412 /* 118937 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42413 /* 118942 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
42414 /* 118945 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
42415 /* 118947 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
42416 /* 118954 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
42417 /* 118959 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
42418 /* 118964 */ // GIR_Coverage, 3049,
42419 /* 118964 */ GIR_EraseRootFromParent_Done,
42420 /* 118965 */ // Label 2257: @118965
42421 /* 118965 */ GIM_Reject,
42422 /* 118966 */ // Label 2253: @118966
42423 /* 118966 */ GIM_Reject,
42424 /* 118967 */ // Label 2246: @118967
42425 /* 118967 */ GIM_Try, /*On fail goto*//*Label 2258*/ GIMT_Encode4(119125),
42426 /* 118972 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
42427 /* 118975 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
42428 /* 118978 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42429 /* 118982 */ GIM_Try, /*On fail goto*//*Label 2259*/ GIMT_Encode4(119035), // Rule ID 2462 //
42430 /* 118987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding),
42431 /* 118990 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42432 /* 118994 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42433 /* 118998 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42434 /* 119002 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42435 /* 119007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42436 /* 119011 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42437 /* 119013 */ // (fmul:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a), DPR:{ *:[f64] }:$b) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
42438 /* 119013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
42439 /* 119016 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42440 /* 119018 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
42441 /* 119022 */ GIR_RootToRootCopy, /*OpIdx*/2, // b
42442 /* 119024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42443 /* 119027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42444 /* 119033 */ GIR_RootConstrainSelectedInstOperands,
42445 /* 119034 */ // GIR_Coverage, 2462,
42446 /* 119034 */ GIR_EraseRootFromParent_Done,
42447 /* 119035 */ // Label 2259: @119035
42448 /* 119035 */ GIM_Try, /*On fail goto*//*Label 2260*/ GIMT_Encode4(119088), // Rule ID 6254 //
42449 /* 119040 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_NoHonorSignDependentRounding),
42450 /* 119043 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42451 /* 119047 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42452 /* 119051 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42453 /* 119055 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42454 /* 119059 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42455 /* 119064 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42456 /* 119066 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$b, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$a, DPR:{ *:[f64] }:$b)
42457 /* 119066 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
42458 /* 119069 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42459 /* 119071 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a
42460 /* 119075 */ GIR_RootToRootCopy, /*OpIdx*/1, // b
42461 /* 119077 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42462 /* 119080 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42463 /* 119086 */ GIR_RootConstrainSelectedInstOperands,
42464 /* 119087 */ // GIR_Coverage, 6254,
42465 /* 119087 */ GIR_EraseRootFromParent_Done,
42466 /* 119088 */ // Label 2260: @119088
42467 /* 119088 */ GIM_Try, /*On fail goto*//*Label 2261*/ GIMT_Encode4(119124), // Rule ID 634 //
42468 /* 119093 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
42469 /* 119096 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42470 /* 119100 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42471 /* 119104 */ // (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42472 /* 119104 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD),
42473 /* 119107 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42474 /* 119109 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
42475 /* 119111 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
42476 /* 119113 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42477 /* 119116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42478 /* 119122 */ GIR_RootConstrainSelectedInstOperands,
42479 /* 119123 */ // GIR_Coverage, 634,
42480 /* 119123 */ GIR_EraseRootFromParent_Done,
42481 /* 119124 */ // Label 2261: @119124
42482 /* 119124 */ GIM_Reject,
42483 /* 119125 */ // Label 2258: @119125
42484 /* 119125 */ GIM_Reject,
42485 /* 119126 */ // Label 2247: @119126
42486 /* 119126 */ GIM_Try, /*On fail goto*//*Label 2262*/ GIMT_Encode4(119172), // Rule ID 962 //
42487 /* 119131 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42488 /* 119134 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
42489 /* 119137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
42490 /* 119140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42491 /* 119144 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42492 /* 119148 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42493 /* 119152 */ // (fmul:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMULfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
42494 /* 119152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfd),
42495 /* 119155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42496 /* 119157 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
42497 /* 119159 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42498 /* 119161 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42499 /* 119164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42500 /* 119170 */ GIR_RootConstrainSelectedInstOperands,
42501 /* 119171 */ // GIR_Coverage, 962,
42502 /* 119171 */ GIR_EraseRootFromParent_Done,
42503 /* 119172 */ // Label 2262: @119172
42504 /* 119172 */ GIM_Reject,
42505 /* 119173 */ // Label 2248: @119173
42506 /* 119173 */ GIM_Try, /*On fail goto*//*Label 2263*/ GIMT_Encode4(119219), // Rule ID 964 //
42507 /* 119178 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42508 /* 119181 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
42509 /* 119184 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
42510 /* 119187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42511 /* 119191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42512 /* 119195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42513 /* 119199 */ // (fmul:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMULhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
42514 /* 119199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhd),
42515 /* 119202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42516 /* 119204 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
42517 /* 119206 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42518 /* 119208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42519 /* 119211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42520 /* 119217 */ GIR_RootConstrainSelectedInstOperands,
42521 /* 119218 */ // GIR_Coverage, 964,
42522 /* 119218 */ GIR_EraseRootFromParent_Done,
42523 /* 119219 */ // Label 2263: @119219
42524 /* 119219 */ GIM_Reject,
42525 /* 119220 */ // Label 2249: @119220
42526 /* 119220 */ GIM_Try, /*On fail goto*//*Label 2264*/ GIMT_Encode4(119333),
42527 /* 119225 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
42528 /* 119228 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
42529 /* 119231 */ GIM_Try, /*On fail goto*//*Label 2265*/ GIMT_Encode4(119271), // Rule ID 963 //
42530 /* 119236 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
42531 /* 119239 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42532 /* 119243 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42533 /* 119247 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42534 /* 119251 */ // (fmul:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMULfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
42535 /* 119251 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULfq),
42536 /* 119254 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42537 /* 119256 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
42538 /* 119258 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42539 /* 119260 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42540 /* 119263 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42541 /* 119269 */ GIR_RootConstrainSelectedInstOperands,
42542 /* 119270 */ // GIR_Coverage, 963,
42543 /* 119270 */ GIR_EraseRootFromParent_Done,
42544 /* 119271 */ // Label 2265: @119271
42545 /* 119271 */ GIM_Try, /*On fail goto*//*Label 2266*/ GIMT_Encode4(119332), // Rule ID 4358 //
42546 /* 119276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
42547 /* 119279 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42548 /* 119283 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42549 /* 119287 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42550 /* 119291 */ // (fmul:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMULf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
42551 /* 119291 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42552 /* 119294 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42553 /* 119298 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42554 /* 119303 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf32),
42555 /* 119306 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42556 /* 119308 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
42557 /* 119310 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
42558 /* 119312 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42559 /* 119315 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42560 /* 119321 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42561 /* 119327 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42562 /* 119330 */ GIR_RootConstrainSelectedInstOperands,
42563 /* 119331 */ // GIR_Coverage, 4358,
42564 /* 119331 */ GIR_EraseRootFromParent_Done,
42565 /* 119332 */ // Label 2266: @119332
42566 /* 119332 */ GIM_Reject,
42567 /* 119333 */ // Label 2264: @119333
42568 /* 119333 */ GIM_Reject,
42569 /* 119334 */ // Label 2250: @119334
42570 /* 119334 */ GIM_Try, /*On fail goto*//*Label 2267*/ GIMT_Encode4(119447),
42571 /* 119339 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
42572 /* 119342 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
42573 /* 119345 */ GIM_Try, /*On fail goto*//*Label 2268*/ GIMT_Encode4(119385), // Rule ID 965 //
42574 /* 119350 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
42575 /* 119353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42576 /* 119357 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42577 /* 119361 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
42578 /* 119365 */ // (fmul:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMULhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
42579 /* 119365 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULhq),
42580 /* 119368 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
42581 /* 119370 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
42582 /* 119372 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
42583 /* 119374 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42584 /* 119377 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42585 /* 119383 */ GIR_RootConstrainSelectedInstOperands,
42586 /* 119384 */ // GIR_Coverage, 965,
42587 /* 119384 */ GIR_EraseRootFromParent_Done,
42588 /* 119385 */ // Label 2268: @119385
42589 /* 119385 */ GIM_Try, /*On fail goto*//*Label 2269*/ GIMT_Encode4(119446), // Rule ID 4365 //
42590 /* 119390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
42591 /* 119393 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42592 /* 119397 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42593 /* 119401 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
42594 /* 119405 */ // (fmul:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMULf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
42595 /* 119405 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
42596 /* 119408 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
42597 /* 119412 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
42598 /* 119417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMULf16),
42599 /* 119420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
42600 /* 119422 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
42601 /* 119424 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
42602 /* 119426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
42603 /* 119429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42604 /* 119435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42605 /* 119441 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
42606 /* 119444 */ GIR_RootConstrainSelectedInstOperands,
42607 /* 119445 */ // GIR_Coverage, 4365,
42608 /* 119445 */ GIR_EraseRootFromParent_Done,
42609 /* 119446 */ // Label 2269: @119446
42610 /* 119446 */ GIM_Reject,
42611 /* 119447 */ // Label 2267: @119447
42612 /* 119447 */ GIM_Reject,
42613 /* 119448 */ // Label 2251: @119448
42614 /* 119448 */ GIM_Reject,
42615 /* 119449 */ // Label 43: @119449
42616 /* 119449 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2277*/ GIMT_Encode4(121539),
42617 /* 119460 */ /*GILLT_s16*//*Label 2270*/ GIMT_Encode4(119512),
42618 /* 119464 */ /*GILLT_s32*//*Label 2271*/ GIMT_Encode4(119899),
42619 /* 119468 */ /*GILLT_s64*//*Label 2272*/ GIMT_Encode4(120286), GIMT_Encode4(0),
42620 /* 119476 */ /*GILLT_v2s32*//*Label 2273*/ GIMT_Encode4(120673), GIMT_Encode4(0), GIMT_Encode4(0),
42621 /* 119488 */ /*GILLT_v4s16*//*Label 2274*/ GIMT_Encode4(120853),
42622 /* 119492 */ /*GILLT_v4s32*//*Label 2275*/ GIMT_Encode4(120909), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
42623 /* 119508 */ /*GILLT_v8s16*//*Label 2276*/ GIMT_Encode4(121287),
42624 /* 119512 */ // Label 2270: @119512
42625 /* 119512 */ GIM_Try, /*On fail goto*//*Label 2278*/ GIMT_Encode4(119898),
42626 /* 119517 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
42627 /* 119520 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
42628 /* 119523 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
42629 /* 119526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42630 /* 119530 */ GIM_Try, /*On fail goto*//*Label 2279*/ GIMT_Encode4(119604), // Rule ID 2736 //
42631 /* 119535 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42632 /* 119538 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42633 /* 119542 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42634 /* 119546 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42635 /* 119550 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42636 /* 119555 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42637 /* 119559 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42638 /* 119563 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42639 /* 119567 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
42640 /* 119571 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42641 /* 119576 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
42642 /* 119578 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42643 /* 119578 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
42644 /* 119581 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42645 /* 119583 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42646 /* 119587 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42647 /* 119591 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42648 /* 119593 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42649 /* 119596 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42650 /* 119602 */ GIR_RootConstrainSelectedInstOperands,
42651 /* 119603 */ // GIR_Coverage, 2736,
42652 /* 119603 */ GIR_EraseRootFromParent_Done,
42653 /* 119604 */ // Label 2279: @119604
42654 /* 119604 */ GIM_Try, /*On fail goto*//*Label 2280*/ GIMT_Encode4(119678), // Rule ID 6275 //
42655 /* 119609 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42656 /* 119612 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42657 /* 119616 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42658 /* 119620 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42659 /* 119624 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42660 /* 119628 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42661 /* 119633 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42662 /* 119637 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42663 /* 119641 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
42664 /* 119645 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42665 /* 119650 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
42666 /* 119652 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42667 /* 119652 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
42668 /* 119655 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42669 /* 119657 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42670 /* 119661 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42671 /* 119665 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
42672 /* 119667 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42673 /* 119670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42674 /* 119676 */ GIR_RootConstrainSelectedInstOperands,
42675 /* 119677 */ // GIR_Coverage, 6275,
42676 /* 119677 */ GIR_EraseRootFromParent_Done,
42677 /* 119678 */ // Label 2280: @119678
42678 /* 119678 */ GIM_Try, /*On fail goto*//*Label 2281*/ GIMT_Encode4(119737), // Rule ID 2716 //
42679 /* 119683 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42680 /* 119686 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42681 /* 119690 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42682 /* 119694 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42683 /* 119698 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42684 /* 119703 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42685 /* 119707 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42686 /* 119711 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42687 /* 119713 */ // (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42688 /* 119713 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
42689 /* 119716 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42690 /* 119718 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
42691 /* 119720 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42692 /* 119724 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42693 /* 119726 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42694 /* 119729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42695 /* 119735 */ GIR_RootConstrainSelectedInstOperands,
42696 /* 119736 */ // GIR_Coverage, 2716,
42697 /* 119736 */ GIR_EraseRootFromParent_Done,
42698 /* 119737 */ // Label 2281: @119737
42699 /* 119737 */ GIM_Try, /*On fail goto*//*Label 2282*/ GIMT_Encode4(119796), // Rule ID 6269 //
42700 /* 119742 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42701 /* 119745 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42702 /* 119749 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42703 /* 119753 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42704 /* 119757 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42705 /* 119761 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42706 /* 119766 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42707 /* 119770 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42708 /* 119772 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42709 /* 119772 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
42710 /* 119775 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42711 /* 119777 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
42712 /* 119779 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42713 /* 119783 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
42714 /* 119785 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42715 /* 119788 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42716 /* 119794 */ GIR_RootConstrainSelectedInstOperands,
42717 /* 119795 */ // GIR_Coverage, 6269,
42718 /* 119795 */ GIR_EraseRootFromParent_Done,
42719 /* 119796 */ // Label 2282: @119796
42720 /* 119796 */ GIM_Try, /*On fail goto*//*Label 2283*/ GIMT_Encode4(119855), // Rule ID 2750 //
42721 /* 119801 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42722 /* 119804 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42723 /* 119808 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42724 /* 119812 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
42725 /* 119816 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42726 /* 119820 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
42727 /* 119824 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42728 /* 119829 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42729 /* 119831 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42730 /* 119831 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
42731 /* 119834 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42732 /* 119836 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
42733 /* 119840 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
42734 /* 119842 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42735 /* 119844 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42736 /* 119847 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42737 /* 119853 */ GIR_RootConstrainSelectedInstOperands,
42738 /* 119854 */ // GIR_Coverage, 2750,
42739 /* 119854 */ GIR_EraseRootFromParent_Done,
42740 /* 119855 */ // Label 2283: @119855
42741 /* 119855 */ GIM_Try, /*On fail goto*//*Label 2284*/ GIMT_Encode4(119897), // Rule ID 2698 //
42742 /* 119860 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
42743 /* 119863 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42744 /* 119867 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42745 /* 119871 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
42746 /* 119875 */ // (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
42747 /* 119875 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH),
42748 /* 119878 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42749 /* 119880 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
42750 /* 119882 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
42751 /* 119884 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42752 /* 119886 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42753 /* 119889 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42754 /* 119895 */ GIR_RootConstrainSelectedInstOperands,
42755 /* 119896 */ // GIR_Coverage, 2698,
42756 /* 119896 */ GIR_EraseRootFromParent_Done,
42757 /* 119897 */ // Label 2284: @119897
42758 /* 119897 */ GIM_Reject,
42759 /* 119898 */ // Label 2278: @119898
42760 /* 119898 */ GIM_Reject,
42761 /* 119899 */ // Label 2271: @119899
42762 /* 119899 */ GIM_Try, /*On fail goto*//*Label 2285*/ GIMT_Encode4(120285),
42763 /* 119904 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
42764 /* 119907 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
42765 /* 119910 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
42766 /* 119913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42767 /* 119917 */ GIM_Try, /*On fail goto*//*Label 2286*/ GIMT_Encode4(119991), // Rule ID 2734 //
42768 /* 119922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42769 /* 119925 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42770 /* 119929 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42771 /* 119933 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42772 /* 119937 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42773 /* 119942 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42774 /* 119946 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42775 /* 119950 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42776 /* 119954 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
42777 /* 119958 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42778 /* 119963 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
42779 /* 119965 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42780 /* 119965 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
42781 /* 119968 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42782 /* 119970 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42783 /* 119974 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42784 /* 119978 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42785 /* 119980 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42786 /* 119983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42787 /* 119989 */ GIR_RootConstrainSelectedInstOperands,
42788 /* 119990 */ // GIR_Coverage, 2734,
42789 /* 119990 */ GIR_EraseRootFromParent_Done,
42790 /* 119991 */ // Label 2286: @119991
42791 /* 119991 */ GIM_Try, /*On fail goto*//*Label 2287*/ GIMT_Encode4(120065), // Rule ID 6273 //
42792 /* 119996 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42793 /* 119999 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42794 /* 120003 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42795 /* 120007 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42796 /* 120011 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42797 /* 120015 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42798 /* 120020 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42799 /* 120024 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42800 /* 120028 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
42801 /* 120032 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42802 /* 120037 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
42803 /* 120039 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42804 /* 120039 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
42805 /* 120042 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42806 /* 120044 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
42807 /* 120048 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42808 /* 120052 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
42809 /* 120054 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42810 /* 120057 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42811 /* 120063 */ GIR_RootConstrainSelectedInstOperands,
42812 /* 120064 */ // GIR_Coverage, 6273,
42813 /* 120064 */ GIR_EraseRootFromParent_Done,
42814 /* 120065 */ // Label 2287: @120065
42815 /* 120065 */ GIM_Try, /*On fail goto*//*Label 2288*/ GIMT_Encode4(120124), // Rule ID 2714 //
42816 /* 120070 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42817 /* 120073 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42818 /* 120077 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42819 /* 120081 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42820 /* 120085 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42821 /* 120090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42822 /* 120094 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42823 /* 120098 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42824 /* 120100 */ // (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42825 /* 120100 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
42826 /* 120103 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42827 /* 120105 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
42828 /* 120107 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42829 /* 120111 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42830 /* 120113 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42831 /* 120116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42832 /* 120122 */ GIR_RootConstrainSelectedInstOperands,
42833 /* 120123 */ // GIR_Coverage, 2714,
42834 /* 120123 */ GIR_EraseRootFromParent_Done,
42835 /* 120124 */ // Label 2288: @120124
42836 /* 120124 */ GIM_Try, /*On fail goto*//*Label 2289*/ GIMT_Encode4(120183), // Rule ID 6267 //
42837 /* 120129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42838 /* 120132 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42839 /* 120136 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42840 /* 120140 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42841 /* 120144 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42842 /* 120148 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42843 /* 120153 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42844 /* 120157 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42845 /* 120159 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42846 /* 120159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
42847 /* 120162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42848 /* 120164 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
42849 /* 120166 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
42850 /* 120170 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
42851 /* 120172 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42852 /* 120175 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42853 /* 120181 */ GIR_RootConstrainSelectedInstOperands,
42854 /* 120182 */ // GIR_Coverage, 6267,
42855 /* 120182 */ GIR_EraseRootFromParent_Done,
42856 /* 120183 */ // Label 2289: @120183
42857 /* 120183 */ GIM_Try, /*On fail goto*//*Label 2290*/ GIMT_Encode4(120242), // Rule ID 2748 //
42858 /* 120188 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42859 /* 120191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42860 /* 120195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42861 /* 120199 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
42862 /* 120203 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42863 /* 120207 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
42864 /* 120211 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42865 /* 120216 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42866 /* 120218 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42867 /* 120218 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
42868 /* 120221 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42869 /* 120223 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
42870 /* 120227 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
42871 /* 120229 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42872 /* 120231 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42873 /* 120234 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42874 /* 120240 */ GIR_RootConstrainSelectedInstOperands,
42875 /* 120241 */ // GIR_Coverage, 2748,
42876 /* 120241 */ GIR_EraseRootFromParent_Done,
42877 /* 120242 */ // Label 2290: @120242
42878 /* 120242 */ GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(120284), // Rule ID 2696 //
42879 /* 120247 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
42880 /* 120250 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42881 /* 120254 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42882 /* 120258 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
42883 /* 120262 */ // (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
42884 /* 120262 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS),
42885 /* 120265 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
42886 /* 120267 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
42887 /* 120269 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
42888 /* 120271 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
42889 /* 120273 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42890 /* 120276 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42891 /* 120282 */ GIR_RootConstrainSelectedInstOperands,
42892 /* 120283 */ // GIR_Coverage, 2696,
42893 /* 120283 */ GIR_EraseRootFromParent_Done,
42894 /* 120284 */ // Label 2291: @120284
42895 /* 120284 */ GIM_Reject,
42896 /* 120285 */ // Label 2285: @120285
42897 /* 120285 */ GIM_Reject,
42898 /* 120286 */ // Label 2272: @120286
42899 /* 120286 */ GIM_Try, /*On fail goto*//*Label 2292*/ GIMT_Encode4(120672),
42900 /* 120291 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
42901 /* 120294 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
42902 /* 120297 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
42903 /* 120300 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42904 /* 120304 */ GIM_Try, /*On fail goto*//*Label 2293*/ GIMT_Encode4(120378), // Rule ID 2732 //
42905 /* 120309 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42906 /* 120312 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42907 /* 120316 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42908 /* 120320 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42909 /* 120324 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42910 /* 120329 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42911 /* 120333 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42912 /* 120337 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42913 /* 120341 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
42914 /* 120345 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42915 /* 120350 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
42916 /* 120352 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42917 /* 120352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
42918 /* 120355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42919 /* 120357 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
42920 /* 120361 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42921 /* 120365 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
42922 /* 120367 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42923 /* 120370 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42924 /* 120376 */ GIR_RootConstrainSelectedInstOperands,
42925 /* 120377 */ // GIR_Coverage, 2732,
42926 /* 120377 */ GIR_EraseRootFromParent_Done,
42927 /* 120378 */ // Label 2293: @120378
42928 /* 120378 */ GIM_Try, /*On fail goto*//*Label 2294*/ GIMT_Encode4(120452), // Rule ID 6271 //
42929 /* 120383 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42930 /* 120386 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42931 /* 120390 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42932 /* 120394 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42933 /* 120398 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42934 /* 120402 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42935 /* 120407 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
42936 /* 120411 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
42937 /* 120415 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
42938 /* 120419 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42939 /* 120424 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
42940 /* 120426 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42941 /* 120426 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
42942 /* 120429 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42943 /* 120431 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
42944 /* 120435 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42945 /* 120439 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
42946 /* 120441 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42947 /* 120444 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42948 /* 120450 */ GIR_RootConstrainSelectedInstOperands,
42949 /* 120451 */ // GIR_Coverage, 6271,
42950 /* 120451 */ GIR_EraseRootFromParent_Done,
42951 /* 120452 */ // Label 2294: @120452
42952 /* 120452 */ GIM_Try, /*On fail goto*//*Label 2295*/ GIMT_Encode4(120511), // Rule ID 2712 //
42953 /* 120457 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42954 /* 120460 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
42955 /* 120464 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42956 /* 120468 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42957 /* 120472 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42958 /* 120477 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42959 /* 120481 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42960 /* 120485 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42961 /* 120487 */ // (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42962 /* 120487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
42963 /* 120490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42964 /* 120492 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
42965 /* 120494 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42966 /* 120498 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
42967 /* 120500 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42968 /* 120503 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42969 /* 120509 */ GIR_RootConstrainSelectedInstOperands,
42970 /* 120510 */ // GIR_Coverage, 2712,
42971 /* 120510 */ GIR_EraseRootFromParent_Done,
42972 /* 120511 */ // Label 2295: @120511
42973 /* 120511 */ GIM_Try, /*On fail goto*//*Label 2296*/ GIMT_Encode4(120570), // Rule ID 6265 //
42974 /* 120516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42975 /* 120519 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42976 /* 120523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
42977 /* 120527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
42978 /* 120531 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
42979 /* 120535 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42980 /* 120540 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42981 /* 120544 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
42982 /* 120546 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
42983 /* 120546 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
42984 /* 120549 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
42985 /* 120551 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
42986 /* 120553 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
42987 /* 120557 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
42988 /* 120559 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
42989 /* 120562 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
42990 /* 120568 */ GIR_RootConstrainSelectedInstOperands,
42991 /* 120569 */ // GIR_Coverage, 6265,
42992 /* 120569 */ GIR_EraseRootFromParent_Done,
42993 /* 120570 */ // Label 2296: @120570
42994 /* 120570 */ GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(120629), // Rule ID 2746 //
42995 /* 120575 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
42996 /* 120578 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42997 /* 120582 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
42998 /* 120586 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
42999 /* 120590 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
43000 /* 120594 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43001 /* 120598 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43002 /* 120603 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43003 /* 120605 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43004 /* 120605 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
43005 /* 120608 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43006 /* 120610 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin
43007 /* 120614 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
43008 /* 120616 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
43009 /* 120618 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43010 /* 120621 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43011 /* 120627 */ GIR_RootConstrainSelectedInstOperands,
43012 /* 120628 */ // GIR_Coverage, 2746,
43013 /* 120628 */ GIR_EraseRootFromParent_Done,
43014 /* 120629 */ // Label 2297: @120629
43015 /* 120629 */ GIM_Try, /*On fail goto*//*Label 2298*/ GIMT_Encode4(120671), // Rule ID 2694 //
43016 /* 120634 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
43017 /* 120637 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43018 /* 120641 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43019 /* 120645 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43020 /* 120649 */ // (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43021 /* 120649 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD),
43022 /* 120652 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43023 /* 120654 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
43024 /* 120656 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
43025 /* 120658 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
43026 /* 120660 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43027 /* 120663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43028 /* 120669 */ GIR_RootConstrainSelectedInstOperands,
43029 /* 120670 */ // GIR_Coverage, 2694,
43030 /* 120670 */ GIR_EraseRootFromParent_Done,
43031 /* 120671 */ // Label 2298: @120671
43032 /* 120671 */ GIM_Reject,
43033 /* 120672 */ // Label 2292: @120672
43034 /* 120672 */ GIM_Reject,
43035 /* 120673 */ // Label 2273: @120673
43036 /* 120673 */ GIM_Try, /*On fail goto*//*Label 2299*/ GIMT_Encode4(120852),
43037 /* 120678 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
43038 /* 120681 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
43039 /* 120684 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32,
43040 /* 120687 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43041 /* 120691 */ GIM_Try, /*On fail goto*//*Label 2300*/ GIMT_Encode4(120750), // Rule ID 2851 //
43042 /* 120696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
43043 /* 120699 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43044 /* 120703 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
43045 /* 120707 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
43046 /* 120711 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43047 /* 120716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43048 /* 120720 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43049 /* 120724 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43050 /* 120726 */ // (fma:{ *:[v2f32] } (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
43051 /* 120726 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd),
43052 /* 120729 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43053 /* 120731 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
43054 /* 120733 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
43055 /* 120737 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43056 /* 120739 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43057 /* 120742 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43058 /* 120748 */ GIR_RootConstrainSelectedInstOperands,
43059 /* 120749 */ // GIR_Coverage, 2851,
43060 /* 120749 */ GIR_EraseRootFromParent_Done,
43061 /* 120750 */ // Label 2300: @120750
43062 /* 120750 */ GIM_Try, /*On fail goto*//*Label 2301*/ GIMT_Encode4(120809), // Rule ID 6328 //
43063 /* 120755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
43064 /* 120758 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43065 /* 120762 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
43066 /* 120766 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
43067 /* 120770 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32,
43068 /* 120774 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43069 /* 120779 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43070 /* 120783 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43071 /* 120785 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm, (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn), DPR:{ *:[v2f32] }:$src1) => (VFMSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
43072 /* 120785 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfd),
43073 /* 120788 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43074 /* 120790 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
43075 /* 120792 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
43076 /* 120796 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
43077 /* 120798 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43078 /* 120801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43079 /* 120807 */ GIR_RootConstrainSelectedInstOperands,
43080 /* 120808 */ // GIR_Coverage, 6328,
43081 /* 120808 */ GIR_EraseRootFromParent_Done,
43082 /* 120809 */ // Label 2301: @120809
43083 /* 120809 */ GIM_Try, /*On fail goto*//*Label 2302*/ GIMT_Encode4(120851), // Rule ID 2849 //
43084 /* 120814 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
43085 /* 120817 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43086 /* 120821 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43087 /* 120825 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43088 /* 120829 */ // (fma:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm, DPR:{ *:[v2f32] }:$src1) => (VFMAfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$src1, DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
43089 /* 120829 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfd),
43090 /* 120832 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43091 /* 120834 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
43092 /* 120836 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43093 /* 120838 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43094 /* 120840 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43095 /* 120843 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43096 /* 120849 */ GIR_RootConstrainSelectedInstOperands,
43097 /* 120850 */ // GIR_Coverage, 2849,
43098 /* 120850 */ GIR_EraseRootFromParent_Done,
43099 /* 120851 */ // Label 2302: @120851
43100 /* 120851 */ GIM_Reject,
43101 /* 120852 */ // Label 2299: @120852
43102 /* 120852 */ GIM_Reject,
43103 /* 120853 */ // Label 2274: @120853
43104 /* 120853 */ GIM_Try, /*On fail goto*//*Label 2303*/ GIMT_Encode4(120908), // Rule ID 2847 //
43105 /* 120858 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43106 /* 120861 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
43107 /* 120864 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
43108 /* 120867 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16,
43109 /* 120870 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43110 /* 120874 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43111 /* 120878 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43112 /* 120882 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43113 /* 120886 */ // (fma:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm, DPR:{ *:[v4f16] }:$src1) => (VFMAhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$src1, DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
43114 /* 120886 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhd),
43115 /* 120889 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43116 /* 120891 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
43117 /* 120893 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43118 /* 120895 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43119 /* 120897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43120 /* 120900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43121 /* 120906 */ GIR_RootConstrainSelectedInstOperands,
43122 /* 120907 */ // GIR_Coverage, 2847,
43123 /* 120907 */ GIR_EraseRootFromParent_Done,
43124 /* 120908 */ // Label 2303: @120908
43125 /* 120908 */ GIM_Reject,
43126 /* 120909 */ // Label 2275: @120909
43127 /* 120909 */ GIM_Try, /*On fail goto*//*Label 2304*/ GIMT_Encode4(121286),
43128 /* 120914 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
43129 /* 120917 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
43130 /* 120920 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32,
43131 /* 120923 */ GIM_Try, /*On fail goto*//*Label 2305*/ GIMT_Encode4(120986), // Rule ID 2852 //
43132 /* 120928 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
43133 /* 120931 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43134 /* 120935 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43135 /* 120939 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
43136 /* 120943 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
43137 /* 120947 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43138 /* 120952 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43139 /* 120956 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43140 /* 120960 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43141 /* 120962 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
43142 /* 120962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq),
43143 /* 120965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43144 /* 120967 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
43145 /* 120969 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
43146 /* 120973 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43147 /* 120975 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43148 /* 120978 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43149 /* 120984 */ GIR_RootConstrainSelectedInstOperands,
43150 /* 120985 */ // GIR_Coverage, 2852,
43151 /* 120985 */ GIR_EraseRootFromParent_Done,
43152 /* 120986 */ // Label 2305: @120986
43153 /* 120986 */ GIM_Try, /*On fail goto*//*Label 2306*/ GIMT_Encode4(121055), // Rule ID 4378 //
43154 /* 120991 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
43155 /* 120994 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43156 /* 120998 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43157 /* 121002 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
43158 /* 121006 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
43159 /* 121010 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43160 /* 121015 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43161 /* 121019 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43162 /* 121023 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43163 /* 121025 */ // (fma:{ *:[v4f32] } (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
43164 /* 121025 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
43165 /* 121028 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43166 /* 121030 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
43167 /* 121032 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
43168 /* 121036 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
43169 /* 121038 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43170 /* 121041 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43171 /* 121047 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43172 /* 121053 */ GIR_RootConstrainSelectedInstOperands,
43173 /* 121054 */ // GIR_Coverage, 4378,
43174 /* 121054 */ GIR_EraseRootFromParent_Done,
43175 /* 121055 */ // Label 2306: @121055
43176 /* 121055 */ GIM_Try, /*On fail goto*//*Label 2307*/ GIMT_Encode4(121118), // Rule ID 6329 //
43177 /* 121060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
43178 /* 121063 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43179 /* 121067 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43180 /* 121071 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
43181 /* 121075 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
43182 /* 121079 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
43183 /* 121083 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43184 /* 121088 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43185 /* 121092 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43186 /* 121094 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm, (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn), QPR:{ *:[v4f32] }:$src1) => (VFMSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
43187 /* 121094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSfq),
43188 /* 121097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43189 /* 121099 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
43190 /* 121101 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Vn
43191 /* 121105 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
43192 /* 121107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43193 /* 121110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43194 /* 121116 */ GIR_RootConstrainSelectedInstOperands,
43195 /* 121117 */ // GIR_Coverage, 6329,
43196 /* 121117 */ GIR_EraseRootFromParent_Done,
43197 /* 121118 */ // Label 2307: @121118
43198 /* 121118 */ GIM_Try, /*On fail goto*//*Label 2308*/ GIMT_Encode4(121187), // Rule ID 6609 //
43199 /* 121123 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
43200 /* 121126 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43201 /* 121130 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43202 /* 121134 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
43203 /* 121138 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
43204 /* 121142 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
43205 /* 121146 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43206 /* 121151 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43207 /* 121155 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43208 /* 121157 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m2, (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1), MQPR:{ *:[v4f32] }:$add) => (MVE_VFMSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
43209 /* 121157 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf32),
43210 /* 121160 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43211 /* 121162 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
43212 /* 121164 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
43213 /* 121168 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2
43214 /* 121170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43215 /* 121173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43216 /* 121179 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43217 /* 121185 */ GIR_RootConstrainSelectedInstOperands,
43218 /* 121186 */ // GIR_Coverage, 6609,
43219 /* 121186 */ GIR_EraseRootFromParent_Done,
43220 /* 121187 */ // Label 2308: @121187
43221 /* 121187 */ GIM_Try, /*On fail goto*//*Label 2309*/ GIMT_Encode4(121233), // Rule ID 2850 //
43222 /* 121192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasVFP4),
43223 /* 121195 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43224 /* 121199 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43225 /* 121203 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43226 /* 121207 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43227 /* 121211 */ // (fma:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm, QPR:{ *:[v4f32] }:$src1) => (VFMAfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$src1, QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
43228 /* 121211 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAfq),
43229 /* 121214 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43230 /* 121216 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
43231 /* 121218 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43232 /* 121220 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43233 /* 121222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43234 /* 121225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43235 /* 121231 */ GIR_RootConstrainSelectedInstOperands,
43236 /* 121232 */ // GIR_Coverage, 2850,
43237 /* 121232 */ GIR_EraseRootFromParent_Done,
43238 /* 121233 */ // Label 2309: @121233
43239 /* 121233 */ GIM_Try, /*On fail goto*//*Label 2310*/ GIMT_Encode4(121285), // Rule ID 4384 //
43240 /* 121238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
43241 /* 121241 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43242 /* 121245 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43243 /* 121249 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43244 /* 121253 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43245 /* 121257 */ // (fma:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$m1, MQPR:{ *:[v4f32] }:$m2, MQPR:{ *:[v4f32] }:$add) => (MVE_VFMAf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$add, ?:{ *:[v4f32] }:$m1, ?:{ *:[v4f32] }:$m2)
43246 /* 121257 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf32),
43247 /* 121260 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43248 /* 121262 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
43249 /* 121264 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1
43250 /* 121266 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
43251 /* 121268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43252 /* 121271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43253 /* 121277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43254 /* 121283 */ GIR_RootConstrainSelectedInstOperands,
43255 /* 121284 */ // GIR_Coverage, 4384,
43256 /* 121284 */ GIR_EraseRootFromParent_Done,
43257 /* 121285 */ // Label 2310: @121285
43258 /* 121285 */ GIM_Reject,
43259 /* 121286 */ // Label 2304: @121286
43260 /* 121286 */ GIM_Reject,
43261 /* 121287 */ // Label 2276: @121287
43262 /* 121287 */ GIM_Try, /*On fail goto*//*Label 2311*/ GIMT_Encode4(121538),
43263 /* 121292 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
43264 /* 121295 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
43265 /* 121298 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16,
43266 /* 121301 */ GIM_Try, /*On fail goto*//*Label 2312*/ GIMT_Encode4(121370), // Rule ID 4392 //
43267 /* 121306 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
43268 /* 121309 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43269 /* 121313 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43270 /* 121317 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
43271 /* 121321 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
43272 /* 121325 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43273 /* 121330 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43274 /* 121334 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43275 /* 121338 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43276 /* 121340 */ // (fma:{ *:[v8f16] } (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
43277 /* 121340 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
43278 /* 121343 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43279 /* 121345 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
43280 /* 121347 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
43281 /* 121351 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
43282 /* 121353 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43283 /* 121356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43284 /* 121362 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43285 /* 121368 */ GIR_RootConstrainSelectedInstOperands,
43286 /* 121369 */ // GIR_Coverage, 4392,
43287 /* 121369 */ GIR_EraseRootFromParent_Done,
43288 /* 121370 */ // Label 2312: @121370
43289 /* 121370 */ GIM_Try, /*On fail goto*//*Label 2313*/ GIMT_Encode4(121439), // Rule ID 6611 //
43290 /* 121375 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
43291 /* 121378 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43292 /* 121382 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43293 /* 121386 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
43294 /* 121390 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
43295 /* 121394 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
43296 /* 121398 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43297 /* 121403 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43298 /* 121407 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43299 /* 121409 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m2, (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1), MQPR:{ *:[v8f16] }:$add) => (MVE_VFMSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
43300 /* 121409 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMSf16),
43301 /* 121412 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43302 /* 121414 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
43303 /* 121416 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // m1
43304 /* 121420 */ GIR_RootToRootCopy, /*OpIdx*/1, // m2
43305 /* 121422 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43306 /* 121425 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43307 /* 121431 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43308 /* 121437 */ GIR_RootConstrainSelectedInstOperands,
43309 /* 121438 */ // GIR_Coverage, 6611,
43310 /* 121438 */ GIR_EraseRootFromParent_Done,
43311 /* 121439 */ // Label 2313: @121439
43312 /* 121439 */ GIM_Try, /*On fail goto*//*Label 2314*/ GIMT_Encode4(121485), // Rule ID 2848 //
43313 /* 121444 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
43314 /* 121447 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43315 /* 121451 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43316 /* 121455 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43317 /* 121459 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
43318 /* 121463 */ // (fma:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm, QPR:{ *:[v8f16] }:$src1) => (VFMAhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$src1, QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
43319 /* 121463 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAhq),
43320 /* 121466 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
43321 /* 121468 */ GIR_RootToRootCopy, /*OpIdx*/3, // src1
43322 /* 121470 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
43323 /* 121472 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
43324 /* 121474 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43325 /* 121477 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43326 /* 121483 */ GIR_RootConstrainSelectedInstOperands,
43327 /* 121484 */ // GIR_Coverage, 2848,
43328 /* 121484 */ GIR_EraseRootFromParent_Done,
43329 /* 121485 */ // Label 2314: @121485
43330 /* 121485 */ GIM_Try, /*On fail goto*//*Label 2315*/ GIMT_Encode4(121537), // Rule ID 4388 //
43331 /* 121490 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
43332 /* 121493 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43333 /* 121497 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43334 /* 121501 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43335 /* 121505 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
43336 /* 121509 */ // (fma:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$m1, MQPR:{ *:[v8f16] }:$m2, MQPR:{ *:[v8f16] }:$add) => (MVE_VFMAf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$add, ?:{ *:[v8f16] }:$m1, ?:{ *:[v8f16] }:$m2)
43337 /* 121509 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VFMAf16),
43338 /* 121512 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
43339 /* 121514 */ GIR_RootToRootCopy, /*OpIdx*/3, // add
43340 /* 121516 */ GIR_RootToRootCopy, /*OpIdx*/1, // m1
43341 /* 121518 */ GIR_RootToRootCopy, /*OpIdx*/2, // m2
43342 /* 121520 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
43343 /* 121523 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43344 /* 121529 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43345 /* 121535 */ GIR_RootConstrainSelectedInstOperands,
43346 /* 121536 */ // GIR_Coverage, 4388,
43347 /* 121536 */ GIR_EraseRootFromParent_Done,
43348 /* 121537 */ // Label 2315: @121537
43349 /* 121537 */ GIM_Reject,
43350 /* 121538 */ // Label 2311: @121538
43351 /* 121538 */ GIM_Reject,
43352 /* 121539 */ // Label 2277: @121539
43353 /* 121539 */ GIM_Reject,
43354 /* 121540 */ // Label 44: @121540
43355 /* 121540 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2319*/ GIMT_Encode4(121704),
43356 /* 121551 */ /*GILLT_s16*//*Label 2316*/ GIMT_Encode4(121563),
43357 /* 121555 */ /*GILLT_s32*//*Label 2317*/ GIMT_Encode4(121610),
43358 /* 121559 */ /*GILLT_s64*//*Label 2318*/ GIMT_Encode4(121657),
43359 /* 121563 */ // Label 2316: @121563
43360 /* 121563 */ GIM_Try, /*On fail goto*//*Label 2320*/ GIMT_Encode4(121609), // Rule ID 632 //
43361 /* 121568 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43362 /* 121571 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
43363 /* 121574 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
43364 /* 121577 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43365 /* 121581 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43366 /* 121585 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43367 /* 121589 */ // (fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43368 /* 121589 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH),
43369 /* 121592 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43370 /* 121594 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
43371 /* 121596 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
43372 /* 121598 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43373 /* 121601 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43374 /* 121607 */ GIR_RootConstrainSelectedInstOperands,
43375 /* 121608 */ // GIR_Coverage, 632,
43376 /* 121608 */ GIR_EraseRootFromParent_Done,
43377 /* 121609 */ // Label 2320: @121609
43378 /* 121609 */ GIM_Reject,
43379 /* 121610 */ // Label 2317: @121610
43380 /* 121610 */ GIM_Try, /*On fail goto*//*Label 2321*/ GIMT_Encode4(121656), // Rule ID 630 //
43381 /* 121615 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2),
43382 /* 121618 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
43383 /* 121621 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
43384 /* 121624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43385 /* 121628 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43386 /* 121632 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43387 /* 121636 */ // (fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43388 /* 121636 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS),
43389 /* 121639 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43390 /* 121641 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
43391 /* 121643 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
43392 /* 121645 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43393 /* 121648 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43394 /* 121654 */ GIR_RootConstrainSelectedInstOperands,
43395 /* 121655 */ // GIR_Coverage, 630,
43396 /* 121655 */ GIR_EraseRootFromParent_Done,
43397 /* 121656 */ // Label 2321: @121656
43398 /* 121656 */ GIM_Reject,
43399 /* 121657 */ // Label 2318: @121657
43400 /* 121657 */ GIM_Try, /*On fail goto*//*Label 2322*/ GIMT_Encode4(121703), // Rule ID 628 //
43401 /* 121662 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
43402 /* 121665 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
43403 /* 121668 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
43404 /* 121671 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43405 /* 121675 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43406 /* 121679 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43407 /* 121683 */ // (fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43408 /* 121683 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD),
43409 /* 121686 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43410 /* 121688 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
43411 /* 121690 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
43412 /* 121692 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43413 /* 121695 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43414 /* 121701 */ GIR_RootConstrainSelectedInstOperands,
43415 /* 121702 */ // GIR_Coverage, 628,
43416 /* 121702 */ GIR_EraseRootFromParent_Done,
43417 /* 121703 */ // Label 2322: @121703
43418 /* 121703 */ GIM_Reject,
43419 /* 121704 */ // Label 2319: @121704
43420 /* 121704 */ GIM_Reject,
43421 /* 121705 */ // Label 45: @121705
43422 /* 121705 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2330*/ GIMT_Encode4(124144),
43423 /* 121716 */ /*GILLT_s16*//*Label 2323*/ GIMT_Encode4(121768),
43424 /* 121720 */ /*GILLT_s32*//*Label 2324*/ GIMT_Encode4(122418),
43425 /* 121724 */ /*GILLT_s64*//*Label 2325*/ GIMT_Encode4(123220), GIMT_Encode4(0),
43426 /* 121732 */ /*GILLT_v2s32*//*Label 2326*/ GIMT_Encode4(123870), GIMT_Encode4(0), GIMT_Encode4(0),
43427 /* 121744 */ /*GILLT_v4s16*//*Label 2327*/ GIMT_Encode4(123908),
43428 /* 121748 */ /*GILLT_v4s32*//*Label 2328*/ GIMT_Encode4(123946), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
43429 /* 121764 */ /*GILLT_v8s16*//*Label 2329*/ GIMT_Encode4(124045),
43430 /* 121768 */ // Label 2323: @121768
43431 /* 121768 */ GIM_Try, /*On fail goto*//*Label 2331*/ GIMT_Encode4(122417),
43432 /* 121773 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
43433 /* 121776 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43434 /* 121780 */ GIM_Try, /*On fail goto*//*Label 2332*/ GIMT_Encode4(121865), // Rule ID 2756 //
43435 /* 121785 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43436 /* 121788 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43437 /* 121792 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43438 /* 121796 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43439 /* 121800 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43440 /* 121804 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
43441 /* 121808 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
43442 /* 121812 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43443 /* 121816 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
43444 /* 121820 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43445 /* 121825 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43446 /* 121830 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43447 /* 121835 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43448 /* 121837 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43449 /* 121837 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
43450 /* 121840 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43451 /* 121842 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43452 /* 121846 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43453 /* 121850 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43454 /* 121854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43455 /* 121857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43456 /* 121863 */ GIR_RootConstrainSelectedInstOperands,
43457 /* 121864 */ // GIR_Coverage, 2756,
43458 /* 121864 */ GIR_EraseRootFromParent_Done,
43459 /* 121865 */ // Label 2332: @121865
43460 /* 121865 */ GIM_Try, /*On fail goto*//*Label 2333*/ GIMT_Encode4(121950), // Rule ID 6281 //
43461 /* 121870 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43462 /* 121873 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43463 /* 121877 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43464 /* 121881 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43465 /* 121885 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43466 /* 121889 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
43467 /* 121893 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43468 /* 121898 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
43469 /* 121902 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43470 /* 121906 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
43471 /* 121910 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43472 /* 121915 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43473 /* 121920 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43474 /* 121922 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43475 /* 121922 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
43476 /* 121925 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43477 /* 121927 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43478 /* 121931 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43479 /* 121935 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
43480 /* 121939 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43481 /* 121942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43482 /* 121948 */ GIR_RootConstrainSelectedInstOperands,
43483 /* 121949 */ // GIR_Coverage, 6281,
43484 /* 121949 */ GIR_EraseRootFromParent_Done,
43485 /* 121950 */ // Label 2333: @121950
43486 /* 121950 */ GIM_Try, /*On fail goto*//*Label 2334*/ GIMT_Encode4(122035), // Rule ID 2755 //
43487 /* 121955 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43488 /* 121958 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43489 /* 121962 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43490 /* 121966 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43491 /* 121970 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43492 /* 121974 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
43493 /* 121978 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
43494 /* 121982 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43495 /* 121986 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
43496 /* 121990 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43497 /* 121995 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43498 /* 122000 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43499 /* 122005 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43500 /* 122007 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43501 /* 122007 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
43502 /* 122010 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43503 /* 122012 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43504 /* 122016 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43505 /* 122020 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43506 /* 122024 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43507 /* 122027 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43508 /* 122033 */ GIR_RootConstrainSelectedInstOperands,
43509 /* 122034 */ // GIR_Coverage, 2755,
43510 /* 122034 */ GIR_EraseRootFromParent_Done,
43511 /* 122035 */ // Label 2334: @122035
43512 /* 122035 */ GIM_Try, /*On fail goto*//*Label 2335*/ GIMT_Encode4(122120), // Rule ID 6280 //
43513 /* 122040 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43514 /* 122043 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43515 /* 122047 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43516 /* 122051 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43517 /* 122055 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43518 /* 122059 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
43519 /* 122063 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43520 /* 122068 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
43521 /* 122072 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43522 /* 122076 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
43523 /* 122080 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43524 /* 122085 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43525 /* 122090 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43526 /* 122092 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43527 /* 122092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
43528 /* 122095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43529 /* 122097 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43530 /* 122101 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43531 /* 122105 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
43532 /* 122109 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43533 /* 122112 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43534 /* 122118 */ GIR_RootConstrainSelectedInstOperands,
43535 /* 122119 */ // GIR_Coverage, 6280,
43536 /* 122119 */ GIR_EraseRootFromParent_Done,
43537 /* 122120 */ // Label 2335: @122120
43538 /* 122120 */ GIM_Try, /*On fail goto*//*Label 2336*/ GIMT_Encode4(122193), // Rule ID 2730 //
43539 /* 122125 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43540 /* 122128 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43541 /* 122132 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43542 /* 122136 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43543 /* 122140 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43544 /* 122144 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
43545 /* 122148 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43546 /* 122153 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43547 /* 122158 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43548 /* 122163 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43549 /* 122165 */ // (fneg:{ *:[f16] } (fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43550 /* 122165 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
43551 /* 122168 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43552 /* 122170 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43553 /* 122174 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43554 /* 122178 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43555 /* 122182 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43556 /* 122185 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43557 /* 122191 */ GIR_RootConstrainSelectedInstOperands,
43558 /* 122192 */ // GIR_Coverage, 2730,
43559 /* 122192 */ GIR_EraseRootFromParent_Done,
43560 /* 122193 */ // Label 2336: @122193
43561 /* 122193 */ GIM_Try, /*On fail goto*//*Label 2337*/ GIMT_Encode4(122266), // Rule ID 2729 //
43562 /* 122198 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43563 /* 122201 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43564 /* 122205 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43565 /* 122209 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43566 /* 122213 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43567 /* 122217 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s16,
43568 /* 122221 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43569 /* 122226 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43570 /* 122231 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43571 /* 122236 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43572 /* 122238 */ // (fneg:{ *:[f16] } (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43573 /* 122238 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
43574 /* 122241 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43575 /* 122243 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43576 /* 122247 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43577 /* 122251 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43578 /* 122255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43579 /* 122258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43580 /* 122264 */ GIR_RootConstrainSelectedInstOperands,
43581 /* 122265 */ // GIR_Coverage, 2729,
43582 /* 122265 */ GIR_EraseRootFromParent_Done,
43583 /* 122266 */ // Label 2337: @122266
43584 /* 122266 */ GIM_Try, /*On fail goto*//*Label 2338*/ GIMT_Encode4(122326), // Rule ID 644 //
43585 /* 122271 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43586 /* 122274 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43587 /* 122278 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
43588 /* 122282 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43589 /* 122286 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43590 /* 122290 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43591 /* 122295 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43592 /* 122300 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43593 /* 122302 */ // (fneg:{ *:[f16] } (fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43594 /* 122302 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH),
43595 /* 122305 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43596 /* 122307 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43597 /* 122311 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43598 /* 122315 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43599 /* 122318 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43600 /* 122324 */ GIR_RootConstrainSelectedInstOperands,
43601 /* 122325 */ // GIR_Coverage, 644,
43602 /* 122325 */ GIR_EraseRootFromParent_Done,
43603 /* 122326 */ // Label 2338: @122326
43604 /* 122326 */ GIM_Try, /*On fail goto*//*Label 2339*/ GIMT_Encode4(122386), // Rule ID 643 //
43605 /* 122331 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43606 /* 122334 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43607 /* 122338 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
43608 /* 122342 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
43609 /* 122346 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16,
43610 /* 122350 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43611 /* 122355 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43612 /* 122360 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43613 /* 122362 */ // (fneg:{ *:[f16] } (strict_fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)) => (VNMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
43614 /* 122362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULH),
43615 /* 122365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43616 /* 122367 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43617 /* 122371 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43618 /* 122375 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43619 /* 122378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43620 /* 122384 */ GIR_RootConstrainSelectedInstOperands,
43621 /* 122385 */ // GIR_Coverage, 643,
43622 /* 122385 */ GIR_EraseRootFromParent_Done,
43623 /* 122386 */ // Label 2339: @122386
43624 /* 122386 */ GIM_Try, /*On fail goto*//*Label 2340*/ GIMT_Encode4(122416), // Rule ID 690 //
43625 /* 122391 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
43626 /* 122394 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
43627 /* 122398 */ // (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VNEGH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
43628 /* 122398 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGH),
43629 /* 122401 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43630 /* 122403 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
43631 /* 122405 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43632 /* 122408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43633 /* 122414 */ GIR_RootConstrainSelectedInstOperands,
43634 /* 122415 */ // GIR_Coverage, 690,
43635 /* 122415 */ GIR_EraseRootFromParent_Done,
43636 /* 122416 */ // Label 2340: @122416
43637 /* 122416 */ GIM_Reject,
43638 /* 122417 */ // Label 2331: @122417
43639 /* 122417 */ GIM_Reject,
43640 /* 122418 */ // Label 2324: @122418
43641 /* 122418 */ GIM_Try, /*On fail goto*//*Label 2341*/ GIMT_Encode4(123219),
43642 /* 122423 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
43643 /* 122426 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43644 /* 122430 */ GIM_Try, /*On fail goto*//*Label 2342*/ GIMT_Encode4(122515), // Rule ID 2754 //
43645 /* 122435 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
43646 /* 122438 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43647 /* 122442 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43648 /* 122446 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43649 /* 122450 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43650 /* 122454 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43651 /* 122458 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
43652 /* 122462 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43653 /* 122466 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
43654 /* 122470 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43655 /* 122475 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43656 /* 122480 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43657 /* 122485 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43658 /* 122487 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43659 /* 122487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
43660 /* 122490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43661 /* 122492 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43662 /* 122496 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43663 /* 122500 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43664 /* 122504 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43665 /* 122507 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43666 /* 122513 */ GIR_RootConstrainSelectedInstOperands,
43667 /* 122514 */ // GIR_Coverage, 2754,
43668 /* 122514 */ GIR_EraseRootFromParent_Done,
43669 /* 122515 */ // Label 2342: @122515
43670 /* 122515 */ GIM_Try, /*On fail goto*//*Label 2343*/ GIMT_Encode4(122600), // Rule ID 6279 //
43671 /* 122520 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
43672 /* 122523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43673 /* 122527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43674 /* 122531 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43675 /* 122535 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43676 /* 122539 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43677 /* 122543 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43678 /* 122548 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
43679 /* 122552 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43680 /* 122556 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
43681 /* 122560 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43682 /* 122565 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43683 /* 122570 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43684 /* 122572 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43685 /* 122572 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
43686 /* 122575 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43687 /* 122577 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43688 /* 122581 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43689 /* 122585 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
43690 /* 122589 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43691 /* 122592 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43692 /* 122598 */ GIR_RootConstrainSelectedInstOperands,
43693 /* 122599 */ // GIR_Coverage, 6279,
43694 /* 122599 */ GIR_EraseRootFromParent_Done,
43695 /* 122600 */ // Label 2343: @122600
43696 /* 122600 */ GIM_Try, /*On fail goto*//*Label 2344*/ GIMT_Encode4(122685), // Rule ID 2753 //
43697 /* 122605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
43698 /* 122608 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43699 /* 122612 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43700 /* 122616 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43701 /* 122620 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43702 /* 122624 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43703 /* 122628 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
43704 /* 122632 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43705 /* 122636 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
43706 /* 122640 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43707 /* 122645 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43708 /* 122650 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43709 /* 122655 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43710 /* 122657 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43711 /* 122657 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
43712 /* 122660 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43713 /* 122662 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43714 /* 122666 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43715 /* 122670 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43716 /* 122674 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43717 /* 122677 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43718 /* 122683 */ GIR_RootConstrainSelectedInstOperands,
43719 /* 122684 */ // GIR_Coverage, 2753,
43720 /* 122684 */ GIR_EraseRootFromParent_Done,
43721 /* 122685 */ // Label 2344: @122685
43722 /* 122685 */ GIM_Try, /*On fail goto*//*Label 2345*/ GIMT_Encode4(122770), // Rule ID 6278 //
43723 /* 122690 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
43724 /* 122693 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43725 /* 122697 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43726 /* 122701 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43727 /* 122705 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43728 /* 122709 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43729 /* 122713 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43730 /* 122718 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
43731 /* 122722 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43732 /* 122726 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
43733 /* 122730 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43734 /* 122735 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43735 /* 122740 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43736 /* 122742 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43737 /* 122742 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
43738 /* 122745 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43739 /* 122747 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43740 /* 122751 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sn
43741 /* 122755 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sm
43742 /* 122759 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43743 /* 122762 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43744 /* 122768 */ GIR_RootConstrainSelectedInstOperands,
43745 /* 122769 */ // GIR_Coverage, 6278,
43746 /* 122769 */ GIR_EraseRootFromParent_Done,
43747 /* 122770 */ // Label 2345: @122770
43748 /* 122770 */ GIM_Try, /*On fail goto*//*Label 2346*/ GIMT_Encode4(122843), // Rule ID 2728 //
43749 /* 122775 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
43750 /* 122778 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43751 /* 122782 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43752 /* 122786 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43753 /* 122790 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43754 /* 122794 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43755 /* 122798 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43756 /* 122803 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43757 /* 122808 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43758 /* 122813 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43759 /* 122815 */ // (fneg:{ *:[f32] } (fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43760 /* 122815 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
43761 /* 122818 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43762 /* 122820 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43763 /* 122824 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43764 /* 122828 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43765 /* 122832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43766 /* 122835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43767 /* 122841 */ GIR_RootConstrainSelectedInstOperands,
43768 /* 122842 */ // GIR_Coverage, 2728,
43769 /* 122842 */ GIR_EraseRootFromParent_Done,
43770 /* 122843 */ // Label 2346: @122843
43771 /* 122843 */ GIM_Try, /*On fail goto*//*Label 2347*/ GIMT_Encode4(122916), // Rule ID 2727 //
43772 /* 122848 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
43773 /* 122851 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43774 /* 122855 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43775 /* 122859 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43776 /* 122863 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43777 /* 122867 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32,
43778 /* 122871 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43779 /* 122876 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43780 /* 122881 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43781 /* 122886 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43782 /* 122888 */ // (fneg:{ *:[f32] } (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43783 /* 122888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
43784 /* 122891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43785 /* 122893 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Sdin
43786 /* 122897 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43787 /* 122901 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43788 /* 122905 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43789 /* 122908 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43790 /* 122914 */ GIR_RootConstrainSelectedInstOperands,
43791 /* 122915 */ // GIR_Coverage, 2727,
43792 /* 122915 */ GIR_EraseRootFromParent_Done,
43793 /* 122916 */ // Label 2347: @122916
43794 /* 122916 */ GIM_Try, /*On fail goto*//*Label 2348*/ GIMT_Encode4(122976), // Rule ID 642 //
43795 /* 122921 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2),
43796 /* 122924 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43797 /* 122928 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
43798 /* 122932 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43799 /* 122936 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43800 /* 122940 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43801 /* 122945 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43802 /* 122950 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43803 /* 122952 */ // (fneg:{ *:[f32] } (fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43804 /* 122952 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
43805 /* 122955 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43806 /* 122957 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43807 /* 122961 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43808 /* 122965 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43809 /* 122968 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43810 /* 122974 */ GIR_RootConstrainSelectedInstOperands,
43811 /* 122975 */ // GIR_Coverage, 642,
43812 /* 122975 */ GIR_EraseRootFromParent_Done,
43813 /* 122976 */ // Label 2348: @122976
43814 /* 122976 */ GIM_Try, /*On fail goto*//*Label 2349*/ GIMT_Encode4(123036), // Rule ID 641 //
43815 /* 122981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2),
43816 /* 122984 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43817 /* 122988 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
43818 /* 122992 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
43819 /* 122996 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32,
43820 /* 123000 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43821 /* 123005 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43822 /* 123010 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
43823 /* 123012 */ // (fneg:{ *:[f32] } (strict_fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)) => (VNMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
43824 /* 123012 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULS),
43825 /* 123015 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43826 /* 123017 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
43827 /* 123021 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Sm
43828 /* 123025 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43829 /* 123028 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43830 /* 123034 */ GIR_RootConstrainSelectedInstOperands,
43831 /* 123035 */ // GIR_Coverage, 641,
43832 /* 123035 */ GIR_EraseRootFromParent_Done,
43833 /* 123036 */ // Label 2349: @123036
43834 /* 123036 */ GIM_Try, /*On fail goto*//*Label 2350*/ GIMT_Encode4(123066), // Rule ID 689 //
43835 /* 123041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
43836 /* 123044 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43837 /* 123048 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VNEGS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
43838 /* 123048 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGS),
43839 /* 123051 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
43840 /* 123053 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
43841 /* 123055 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43842 /* 123058 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43843 /* 123064 */ GIR_RootConstrainSelectedInstOperands,
43844 /* 123065 */ // GIR_Coverage, 689,
43845 /* 123065 */ GIR_EraseRootFromParent_Done,
43846 /* 123066 */ // Label 2350: @123066
43847 /* 123066 */ GIM_Try, /*On fail goto*//*Label 2351*/ GIMT_Encode4(123218), // Rule ID 3055 //
43848 /* 123071 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
43849 /* 123074 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
43850 /* 123078 */ // (fneg:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VNEGfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
43851 /* 123078 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
43852 /* 123081 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
43853 /* 123085 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43854 /* 123090 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
43855 /* 123092 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
43856 /* 123095 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43857 /* 123099 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43858 /* 123104 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
43859 /* 123107 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43860 /* 123112 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
43861 /* 123115 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
43862 /* 123119 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43863 /* 123124 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
43864 /* 123127 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
43865 /* 123131 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
43866 /* 123134 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43867 /* 123139 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43868 /* 123144 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
43869 /* 123149 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
43870 /* 123152 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VNEGfd),
43871 /* 123156 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43872 /* 123161 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
43873 /* 123164 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
43874 /* 123167 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43875 /* 123173 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
43876 /* 123175 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
43877 /* 123178 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43878 /* 123182 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
43879 /* 123187 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
43880 /* 123190 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43881 /* 123195 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
43882 /* 123198 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
43883 /* 123200 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
43884 /* 123207 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
43885 /* 123212 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
43886 /* 123217 */ // GIR_Coverage, 3055,
43887 /* 123217 */ GIR_EraseRootFromParent_Done,
43888 /* 123218 */ // Label 2351: @123218
43889 /* 123218 */ GIM_Reject,
43890 /* 123219 */ // Label 2341: @123219
43891 /* 123219 */ GIM_Reject,
43892 /* 123220 */ // Label 2325: @123220
43893 /* 123220 */ GIM_Try, /*On fail goto*//*Label 2352*/ GIMT_Encode4(123869),
43894 /* 123225 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
43895 /* 123228 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43896 /* 123232 */ GIM_Try, /*On fail goto*//*Label 2353*/ GIMT_Encode4(123317), // Rule ID 2752 //
43897 /* 123237 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
43898 /* 123240 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43899 /* 123244 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43900 /* 123248 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43901 /* 123252 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43902 /* 123256 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43903 /* 123260 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
43904 /* 123264 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43905 /* 123268 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
43906 /* 123272 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43907 /* 123277 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43908 /* 123282 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43909 /* 123287 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43910 /* 123289 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43911 /* 123289 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
43912 /* 123292 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43913 /* 123294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43914 /* 123298 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
43915 /* 123302 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
43916 /* 123306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43917 /* 123309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43918 /* 123315 */ GIR_RootConstrainSelectedInstOperands,
43919 /* 123316 */ // GIR_Coverage, 2752,
43920 /* 123316 */ GIR_EraseRootFromParent_Done,
43921 /* 123317 */ // Label 2353: @123317
43922 /* 123317 */ GIM_Try, /*On fail goto*//*Label 2354*/ GIMT_Encode4(123402), // Rule ID 6277 //
43923 /* 123322 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
43924 /* 123325 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43925 /* 123329 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
43926 /* 123333 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43927 /* 123337 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43928 /* 123341 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43929 /* 123345 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43930 /* 123350 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
43931 /* 123354 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43932 /* 123358 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
43933 /* 123362 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43934 /* 123367 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43935 /* 123372 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43936 /* 123374 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43937 /* 123374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
43938 /* 123377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43939 /* 123379 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43940 /* 123383 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
43941 /* 123387 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm
43942 /* 123391 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43943 /* 123394 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43944 /* 123400 */ GIR_RootConstrainSelectedInstOperands,
43945 /* 123401 */ // GIR_Coverage, 6277,
43946 /* 123401 */ GIR_EraseRootFromParent_Done,
43947 /* 123402 */ // Label 2354: @123402
43948 /* 123402 */ GIM_Try, /*On fail goto*//*Label 2355*/ GIMT_Encode4(123487), // Rule ID 2751 //
43949 /* 123407 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
43950 /* 123410 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43951 /* 123414 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43952 /* 123418 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43953 /* 123422 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43954 /* 123426 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43955 /* 123430 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
43956 /* 123434 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43957 /* 123438 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
43958 /* 123442 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43959 /* 123447 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43960 /* 123452 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43961 /* 123457 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43962 /* 123459 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43963 /* 123459 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
43964 /* 123462 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43965 /* 123464 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43966 /* 123468 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
43967 /* 123472 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
43968 /* 123476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43969 /* 123479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43970 /* 123485 */ GIR_RootConstrainSelectedInstOperands,
43971 /* 123486 */ // GIR_Coverage, 2751,
43972 /* 123486 */ GIR_EraseRootFromParent_Done,
43973 /* 123487 */ // Label 2355: @123487
43974 /* 123487 */ GIM_Try, /*On fail goto*//*Label 2356*/ GIMT_Encode4(123572), // Rule ID 6276 //
43975 /* 123492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
43976 /* 123495 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
43977 /* 123499 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
43978 /* 123503 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
43979 /* 123507 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
43980 /* 123511 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
43981 /* 123515 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43982 /* 123520 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
43983 /* 123524 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
43984 /* 123528 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
43985 /* 123532 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43986 /* 123537 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
43987 /* 123542 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
43988 /* 123544 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
43989 /* 123544 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
43990 /* 123547 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
43991 /* 123549 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
43992 /* 123553 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Dn
43993 /* 123557 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dm
43994 /* 123561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
43995 /* 123564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
43996 /* 123570 */ GIR_RootConstrainSelectedInstOperands,
43997 /* 123571 */ // GIR_Coverage, 6276,
43998 /* 123571 */ GIR_EraseRootFromParent_Done,
43999 /* 123572 */ // Label 2356: @123572
44000 /* 123572 */ GIM_Try, /*On fail goto*//*Label 2357*/ GIMT_Encode4(123645), // Rule ID 2726 //
44001 /* 123577 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
44002 /* 123580 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44003 /* 123584 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA),
44004 /* 123588 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44005 /* 123592 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44006 /* 123596 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44007 /* 123600 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44008 /* 123605 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44009 /* 123610 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44010 /* 123615 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44011 /* 123617 */ // (fneg:{ *:[f64] } (fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
44012 /* 123617 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
44013 /* 123620 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
44014 /* 123622 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
44015 /* 123626 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
44016 /* 123630 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
44017 /* 123634 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44018 /* 123637 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44019 /* 123643 */ GIR_RootConstrainSelectedInstOperands,
44020 /* 123644 */ // GIR_Coverage, 2726,
44021 /* 123644 */ GIR_EraseRootFromParent_Done,
44022 /* 123645 */ // Label 2357: @123645
44023 /* 123645 */ GIM_Try, /*On fail goto*//*Label 2358*/ GIMT_Encode4(123718), // Rule ID 2725 //
44024 /* 123650 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
44025 /* 123653 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44026 /* 123657 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMA),
44027 /* 123661 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44028 /* 123665 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44029 /* 123669 */ GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s64,
44030 /* 123673 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44031 /* 123678 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44032 /* 123683 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44033 /* 123688 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44034 /* 123690 */ // (fneg:{ *:[f64] } (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
44035 /* 123690 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
44036 /* 123693 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
44037 /* 123695 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/3, // Ddin
44038 /* 123699 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
44039 /* 123703 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
44040 /* 123707 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44041 /* 123710 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44042 /* 123716 */ GIR_RootConstrainSelectedInstOperands,
44043 /* 123717 */ // GIR_Coverage, 2725,
44044 /* 123717 */ GIR_EraseRootFromParent_Done,
44045 /* 123718 */ // Label 2358: @123718
44046 /* 123718 */ GIM_Try, /*On fail goto*//*Label 2359*/ GIMT_Encode4(123778), // Rule ID 640 //
44047 /* 123723 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
44048 /* 123726 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44049 /* 123730 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL),
44050 /* 123734 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44051 /* 123738 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44052 /* 123742 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44053 /* 123747 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44054 /* 123752 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44055 /* 123754 */ // (fneg:{ *:[f64] } (fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
44056 /* 123754 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
44057 /* 123757 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
44058 /* 123759 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
44059 /* 123763 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
44060 /* 123767 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44061 /* 123770 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44062 /* 123776 */ GIR_RootConstrainSelectedInstOperands,
44063 /* 123777 */ // GIR_Coverage, 640,
44064 /* 123777 */ GIR_EraseRootFromParent_Done,
44065 /* 123778 */ // Label 2359: @123778
44066 /* 123778 */ GIM_Try, /*On fail goto*//*Label 2360*/ GIMT_Encode4(123838), // Rule ID 639 //
44067 /* 123783 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
44068 /* 123786 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44069 /* 123790 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_STRICT_FMUL),
44070 /* 123794 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44071 /* 123798 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64,
44072 /* 123802 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44073 /* 123807 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44074 /* 123812 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44075 /* 123814 */ // (fneg:{ *:[f64] } (strict_fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)) => (VNMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
44076 /* 123814 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNMULD),
44077 /* 123817 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
44078 /* 123819 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
44079 /* 123823 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Dm
44080 /* 123827 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44081 /* 123830 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44082 /* 123836 */ GIR_RootConstrainSelectedInstOperands,
44083 /* 123837 */ // GIR_Coverage, 639,
44084 /* 123837 */ GIR_EraseRootFromParent_Done,
44085 /* 123838 */ // Label 2360: @123838
44086 /* 123838 */ GIM_Try, /*On fail goto*//*Label 2361*/ GIMT_Encode4(123868), // Rule ID 688 //
44087 /* 123843 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
44088 /* 123846 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44089 /* 123850 */ // (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VNEGD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
44090 /* 123850 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGD),
44091 /* 123853 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
44092 /* 123855 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
44093 /* 123857 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44094 /* 123860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44095 /* 123866 */ GIR_RootConstrainSelectedInstOperands,
44096 /* 123867 */ // GIR_Coverage, 688,
44097 /* 123867 */ GIR_EraseRootFromParent_Done,
44098 /* 123868 */ // Label 2361: @123868
44099 /* 123868 */ GIM_Reject,
44100 /* 123869 */ // Label 2352: @123869
44101 /* 123869 */ GIM_Reject,
44102 /* 123870 */ // Label 2326: @123870
44103 /* 123870 */ GIM_Try, /*On fail goto*//*Label 2362*/ GIMT_Encode4(123907), // Rule ID 1691 //
44104 /* 123875 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44105 /* 123878 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
44106 /* 123881 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44107 /* 123885 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44108 /* 123889 */ // (fneg:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VNEGfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
44109 /* 123889 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGfd),
44110 /* 123892 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44111 /* 123894 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44112 /* 123896 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44113 /* 123899 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44114 /* 123905 */ GIR_RootConstrainSelectedInstOperands,
44115 /* 123906 */ // GIR_Coverage, 1691,
44116 /* 123906 */ GIR_EraseRootFromParent_Done,
44117 /* 123907 */ // Label 2362: @123907
44118 /* 123907 */ GIM_Reject,
44119 /* 123908 */ // Label 2327: @123908
44120 /* 123908 */ GIM_Try, /*On fail goto*//*Label 2363*/ GIMT_Encode4(123945), // Rule ID 1693 //
44121 /* 123913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44122 /* 123916 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
44123 /* 123919 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44124 /* 123923 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44125 /* 123927 */ // (fneg:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VNEGhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
44126 /* 123927 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhd),
44127 /* 123930 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44128 /* 123932 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44129 /* 123934 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44130 /* 123937 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44131 /* 123943 */ GIR_RootConstrainSelectedInstOperands,
44132 /* 123944 */ // GIR_Coverage, 1693,
44133 /* 123944 */ GIR_EraseRootFromParent_Done,
44134 /* 123945 */ // Label 2363: @123945
44135 /* 123945 */ GIM_Reject,
44136 /* 123946 */ // Label 2328: @123946
44137 /* 123946 */ GIM_Try, /*On fail goto*//*Label 2364*/ GIMT_Encode4(124044),
44138 /* 123951 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44139 /* 123954 */ GIM_Try, /*On fail goto*//*Label 2365*/ GIMT_Encode4(123988), // Rule ID 1692 //
44140 /* 123959 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44141 /* 123962 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44142 /* 123966 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44143 /* 123970 */ // (fneg:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VNEGf32q:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
44144 /* 123970 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGf32q),
44145 /* 123973 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44146 /* 123975 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44147 /* 123977 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44148 /* 123980 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44149 /* 123986 */ GIR_RootConstrainSelectedInstOperands,
44150 /* 123987 */ // GIR_Coverage, 1692,
44151 /* 123987 */ GIR_EraseRootFromParent_Done,
44152 /* 123988 */ // Label 2365: @123988
44153 /* 123988 */ GIM_Try, /*On fail goto*//*Label 2366*/ GIMT_Encode4(124043), // Rule ID 4518 //
44154 /* 123993 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
44155 /* 123996 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44156 /* 124000 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44157 /* 124004 */ // (fneg:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VNEGf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v)
44158 /* 124004 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44159 /* 124007 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44160 /* 124011 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44161 /* 124016 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf32),
44162 /* 124019 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44163 /* 124021 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
44164 /* 124023 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44165 /* 124026 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44166 /* 124032 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44167 /* 124038 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44168 /* 124041 */ GIR_RootConstrainSelectedInstOperands,
44169 /* 124042 */ // GIR_Coverage, 4518,
44170 /* 124042 */ GIR_EraseRootFromParent_Done,
44171 /* 124043 */ // Label 2366: @124043
44172 /* 124043 */ GIM_Reject,
44173 /* 124044 */ // Label 2364: @124044
44174 /* 124044 */ GIM_Reject,
44175 /* 124045 */ // Label 2329: @124045
44176 /* 124045 */ GIM_Try, /*On fail goto*//*Label 2367*/ GIMT_Encode4(124143),
44177 /* 124050 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
44178 /* 124053 */ GIM_Try, /*On fail goto*//*Label 2368*/ GIMT_Encode4(124087), // Rule ID 1694 //
44179 /* 124058 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44180 /* 124061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44181 /* 124065 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44182 /* 124069 */ // (fneg:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VNEGhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
44183 /* 124069 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VNEGhq),
44184 /* 124072 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44185 /* 124074 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44186 /* 124076 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44187 /* 124079 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44188 /* 124085 */ GIR_RootConstrainSelectedInstOperands,
44189 /* 124086 */ // GIR_Coverage, 1694,
44190 /* 124086 */ GIR_EraseRootFromParent_Done,
44191 /* 124087 */ // Label 2368: @124087
44192 /* 124087 */ GIM_Try, /*On fail goto*//*Label 2369*/ GIMT_Encode4(124142), // Rule ID 4516 //
44193 /* 124092 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
44194 /* 124095 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44195 /* 124099 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44196 /* 124103 */ // (fneg:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VNEGf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v)
44197 /* 124103 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44198 /* 124106 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44199 /* 124110 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44200 /* 124115 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VNEGf16),
44201 /* 124118 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44202 /* 124120 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
44203 /* 124122 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44204 /* 124125 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44205 /* 124131 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44206 /* 124137 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44207 /* 124140 */ GIR_RootConstrainSelectedInstOperands,
44208 /* 124141 */ // GIR_Coverage, 4516,
44209 /* 124141 */ GIR_EraseRootFromParent_Done,
44210 /* 124142 */ // Label 2369: @124142
44211 /* 124142 */ GIM_Reject,
44212 /* 124143 */ // Label 2367: @124143
44213 /* 124143 */ GIM_Reject,
44214 /* 124144 */ // Label 2330: @124144
44215 /* 124144 */ GIM_Reject,
44216 /* 124145 */ // Label 46: @124145
44217 /* 124145 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(9), /*)*//*default:*//*Label 2373*/ GIMT_Encode4(124380),
44218 /* 124156 */ /*GILLT_s32*//*Label 2370*/ GIMT_Encode4(124188),
44219 /* 124160 */ /*GILLT_s64*//*Label 2371*/ GIMT_Encode4(124248), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
44220 /* 124184 */ /*GILLT_v4s32*//*Label 2372*/ GIMT_Encode4(124345),
44221 /* 124188 */ // Label 2370: @124188
44222 /* 124188 */ GIM_Try, /*On fail goto*//*Label 2374*/ GIMT_Encode4(124247), // Rule ID 2465 //
44223 /* 124193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16),
44224 /* 124196 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44225 /* 124199 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44226 /* 124203 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44227 /* 124207 */ // (fpextend:{ *:[f32] } HPR:{ *:[f16] }:$Sm) => (VCVTBHS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
44228 /* 124207 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44229 /* 124210 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44230 /* 124214 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44231 /* 124219 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
44232 /* 124223 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
44233 /* 124228 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHS),
44234 /* 124231 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
44235 /* 124233 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44236 /* 124236 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44237 /* 124239 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44238 /* 124245 */ GIR_RootConstrainSelectedInstOperands,
44239 /* 124246 */ // GIR_Coverage, 2465,
44240 /* 124246 */ GIR_EraseRootFromParent_Done,
44241 /* 124247 */ // Label 2374: @124247
44242 /* 124247 */ GIM_Reject,
44243 /* 124248 */ // Label 2371: @124248
44244 /* 124248 */ GIM_Try, /*On fail goto*//*Label 2375*/ GIMT_Encode4(124285), // Rule ID 685 //
44245 /* 124253 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
44246 /* 124256 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44247 /* 124259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44248 /* 124263 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44249 /* 124267 */ // (fpextend:{ *:[f64] } SPR:{ *:[f32] }:$Sm) => (VCVTDS:{ *:[f64] } SPR:{ *:[f32] }:$Sm)
44250 /* 124267 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTDS),
44251 /* 124270 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
44252 /* 124272 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
44253 /* 124274 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44254 /* 124277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44255 /* 124283 */ GIR_RootConstrainSelectedInstOperands,
44256 /* 124284 */ // GIR_Coverage, 685,
44257 /* 124284 */ GIR_EraseRootFromParent_Done,
44258 /* 124285 */ // Label 2375: @124285
44259 /* 124285 */ GIM_Try, /*On fail goto*//*Label 2376*/ GIMT_Encode4(124344), // Rule ID 2485 //
44260 /* 124290 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44261 /* 124293 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44262 /* 124296 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44263 /* 124300 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44264 /* 124304 */ // (fpextend:{ *:[f64] } HPR:{ *:[f16] }:$Sm) => (VCVTBHD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } HPR:{ *:[f16] }:$Sm, SPR:{ *:[i32] }))
44265 /* 124304 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44266 /* 124307 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44267 /* 124311 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44268 /* 124316 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
44269 /* 124320 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
44270 /* 124325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTBHD),
44271 /* 124328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
44272 /* 124330 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44273 /* 124333 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44274 /* 124336 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44275 /* 124342 */ GIR_RootConstrainSelectedInstOperands,
44276 /* 124343 */ // GIR_Coverage, 2485,
44277 /* 124343 */ GIR_EraseRootFromParent_Done,
44278 /* 124344 */ // Label 2376: @124344
44279 /* 124344 */ GIM_Reject,
44280 /* 124345 */ // Label 2372: @124345
44281 /* 124345 */ GIM_Try, /*On fail goto*//*Label 2377*/ GIMT_Encode4(124379), // Rule ID 3020 //
44282 /* 124350 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
44283 /* 124353 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44284 /* 124357 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44285 /* 124361 */ // (fpextend:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src) => (VCVTh2f:{ *:[v4f32] } DPR:{ *:[v4f16] }:$src)
44286 /* 124361 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2f),
44287 /* 124364 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44288 /* 124366 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
44289 /* 124368 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44290 /* 124371 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44291 /* 124377 */ GIR_RootConstrainSelectedInstOperands,
44292 /* 124378 */ // GIR_Coverage, 3020,
44293 /* 124378 */ GIR_EraseRootFromParent_Done,
44294 /* 124379 */ // Label 2377: @124379
44295 /* 124379 */ GIM_Reject,
44296 /* 124380 */ // Label 2373: @124380
44297 /* 124380 */ GIM_Reject,
44298 /* 124381 */ // Label 47: @124381
44299 /* 124381 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(8), /*)*//*default:*//*Label 2381*/ GIMT_Encode4(124652),
44300 /* 124392 */ /*GILLT_s16*//*Label 2378*/ GIMT_Encode4(124424),
44301 /* 124396 */ /*GILLT_s32*//*Label 2379*/ GIMT_Encode4(124579), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
44302 /* 124420 */ /*GILLT_v4s16*//*Label 2380*/ GIMT_Encode4(124617),
44303 /* 124424 */ // Label 2378: @124424
44304 /* 124424 */ GIM_Try, /*On fail goto*//*Label 2382*/ GIMT_Encode4(124501), // Rule ID 2469 //
44305 /* 124429 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP16),
44306 /* 124432 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44307 /* 124435 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44308 /* 124439 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44309 /* 124443 */ // (fpround:{ *:[f16] } SPR:{ *:[f32] }:$Sm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBSH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), SPR:{ *:[f32] }:$Sm), HPR:{ *:[i32] })
44310 /* 124443 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44311 /* 124446 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44312 /* 124450 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44313 /* 124455 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44314 /* 124457 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44315 /* 124460 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBSH),
44316 /* 124464 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44317 /* 124469 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44318 /* 124472 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Sm
44319 /* 124476 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44320 /* 124479 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44321 /* 124485 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44322 /* 124487 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44323 /* 124490 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44324 /* 124492 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44325 /* 124495 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
44326 /* 124500 */ // GIR_Coverage, 2469,
44327 /* 124500 */ GIR_EraseRootFromParent_Done,
44328 /* 124501 */ // Label 2382: @124501
44329 /* 124501 */ GIM_Try, /*On fail goto*//*Label 2383*/ GIMT_Encode4(124578), // Rule ID 2489 //
44330 /* 124506 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44331 /* 124509 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44332 /* 124512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44333 /* 124516 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44334 /* 124520 */ // (fpround:{ *:[f16] } DPR:{ *:[f64] }:$Dm) => (COPY_TO_REGCLASS:{ *:[f16] } (VCVTBDH:{ *:[f32] } (IMPLICIT_DEF:{ *:[f32] }), DPR:{ *:[f64] }:$Dm), HPR:{ *:[i32] })
44335 /* 124520 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32,
44336 /* 124523 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44337 /* 124527 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44338 /* 124532 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
44339 /* 124534 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44340 /* 124537 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTBDH),
44341 /* 124541 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44342 /* 124546 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44343 /* 124549 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // Dm
44344 /* 124553 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44345 /* 124556 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44346 /* 124562 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44347 /* 124564 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44348 /* 124567 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44349 /* 124569 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44350 /* 124572 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::HPRRegClassID),
44351 /* 124577 */ // GIR_Coverage, 2489,
44352 /* 124577 */ GIR_EraseRootFromParent_Done,
44353 /* 124578 */ // Label 2383: @124578
44354 /* 124578 */ GIM_Reject,
44355 /* 124579 */ // Label 2379: @124579
44356 /* 124579 */ GIM_Try, /*On fail goto*//*Label 2384*/ GIMT_Encode4(124616), // Rule ID 687 //
44357 /* 124584 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
44358 /* 124587 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44359 /* 124590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44360 /* 124594 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44361 /* 124598 */ // (fpround:{ *:[f32] } DPR:{ *:[f64] }:$Dm) => (VCVTSD:{ *:[f32] } DPR:{ *:[f64] }:$Dm)
44362 /* 124598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTSD),
44363 /* 124601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
44364 /* 124603 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
44365 /* 124605 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44366 /* 124608 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44367 /* 124614 */ GIR_RootConstrainSelectedInstOperands,
44368 /* 124615 */ // GIR_Coverage, 687,
44369 /* 124615 */ GIR_EraseRootFromParent_Done,
44370 /* 124616 */ // Label 2384: @124616
44371 /* 124616 */ GIM_Reject,
44372 /* 124617 */ // Label 2380: @124617
44373 /* 124617 */ GIM_Try, /*On fail goto*//*Label 2385*/ GIMT_Encode4(124651), // Rule ID 3019 //
44374 /* 124622 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44375 /* 124625 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44376 /* 124629 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44377 /* 124633 */ // (fpround:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src) => (VCVTf2h:{ *:[v4f16] } QPR:{ *:[v4f32] }:$src)
44378 /* 124633 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2h),
44379 /* 124636 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44380 /* 124638 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
44381 /* 124640 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44382 /* 124643 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44383 /* 124649 */ GIR_RootConstrainSelectedInstOperands,
44384 /* 124650 */ // GIR_Coverage, 3019,
44385 /* 124650 */ GIR_EraseRootFromParent_Done,
44386 /* 124651 */ // Label 2385: @124651
44387 /* 124651 */ GIM_Reject,
44388 /* 124652 */ // Label 2381: @124652
44389 /* 124652 */ GIM_Reject,
44390 /* 124653 */ // Label 48: @124653
44391 /* 124653 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2393*/ GIMT_Encode4(125986),
44392 /* 124664 */ /*GILLT_s32*//*Label 2386*/ GIMT_Encode4(124712), GIMT_Encode4(0), GIMT_Encode4(0),
44393 /* 124676 */ /*GILLT_v2s32*//*Label 2387*/ GIMT_Encode4(125606), GIMT_Encode4(0),
44394 /* 124684 */ /*GILLT_v4s1*//*Label 2388*/ GIMT_Encode4(125644),
44395 /* 124688 */ /*GILLT_v4s16*//*Label 2389*/ GIMT_Encode4(125697),
44396 /* 124692 */ /*GILLT_v4s32*//*Label 2390*/ GIMT_Encode4(125735), GIMT_Encode4(0),
44397 /* 124700 */ /*GILLT_v8s1*//*Label 2391*/ GIMT_Encode4(125834), GIMT_Encode4(0),
44398 /* 124708 */ /*GILLT_v8s16*//*Label 2392*/ GIMT_Encode4(125887),
44399 /* 124712 */ // Label 2386: @124712
44400 /* 124712 */ GIM_Try, /*On fail goto*//*Label 2394*/ GIMT_Encode4(124778), // Rule ID 2519 //
44401 /* 124717 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44402 /* 124720 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44403 /* 124723 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44404 /* 124727 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44405 /* 124731 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
44406 /* 124735 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44407 /* 124739 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44408 /* 124744 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44409 /* 124746 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44410 /* 124746 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44411 /* 124749 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSH),
44412 /* 124753 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44413 /* 124758 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44414 /* 124762 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44415 /* 124764 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44416 /* 124767 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44417 /* 124769 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44418 /* 124772 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44419 /* 124777 */ // GIR_Coverage, 2519,
44420 /* 124777 */ GIR_EraseRootFromParent_Done,
44421 /* 124778 */ // Label 2394: @124778
44422 /* 124778 */ GIM_Try, /*On fail goto*//*Label 2395*/ GIMT_Encode4(124844), // Rule ID 2527 //
44423 /* 124783 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
44424 /* 124786 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44425 /* 124789 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44426 /* 124793 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44427 /* 124797 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
44428 /* 124801 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44429 /* 124805 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44430 /* 124810 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44431 /* 124812 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44432 /* 124812 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44433 /* 124815 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSS),
44434 /* 124819 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44435 /* 124824 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44436 /* 124828 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44437 /* 124830 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44438 /* 124833 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44439 /* 124835 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44440 /* 124838 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44441 /* 124843 */ // GIR_Coverage, 2527,
44442 /* 124843 */ GIR_EraseRootFromParent_Done,
44443 /* 124844 */ // Label 2395: @124844
44444 /* 124844 */ GIM_Try, /*On fail goto*//*Label 2396*/ GIMT_Encode4(124910), // Rule ID 2535 //
44445 /* 124849 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44446 /* 124852 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44447 /* 124855 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44448 /* 124859 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44449 /* 124863 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
44450 /* 124867 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44451 /* 124871 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44452 /* 124876 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44453 /* 124878 */ // (fp_to_sint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44454 /* 124878 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44455 /* 124881 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPSD),
44456 /* 124885 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44457 /* 124890 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44458 /* 124894 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44459 /* 124896 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44460 /* 124899 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44461 /* 124901 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44462 /* 124904 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44463 /* 124909 */ // GIR_Coverage, 2535,
44464 /* 124909 */ GIR_EraseRootFromParent_Done,
44465 /* 124910 */ // Label 2396: @124910
44466 /* 124910 */ GIM_Try, /*On fail goto*//*Label 2397*/ GIMT_Encode4(124976), // Rule ID 2543 //
44467 /* 124915 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44468 /* 124918 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44469 /* 124921 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44470 /* 124925 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44471 /* 124929 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
44472 /* 124933 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44473 /* 124937 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44474 /* 124942 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44475 /* 124944 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44476 /* 124944 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44477 /* 124947 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSH),
44478 /* 124951 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44479 /* 124956 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44480 /* 124960 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44481 /* 124962 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44482 /* 124965 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44483 /* 124967 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44484 /* 124970 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44485 /* 124975 */ // GIR_Coverage, 2543,
44486 /* 124975 */ GIR_EraseRootFromParent_Done,
44487 /* 124976 */ // Label 2397: @124976
44488 /* 124976 */ GIM_Try, /*On fail goto*//*Label 2398*/ GIMT_Encode4(125042), // Rule ID 2551 //
44489 /* 124981 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
44490 /* 124984 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44491 /* 124987 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44492 /* 124991 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44493 /* 124995 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
44494 /* 124999 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44495 /* 125003 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44496 /* 125008 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44497 /* 125010 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44498 /* 125010 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44499 /* 125013 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSS),
44500 /* 125017 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44501 /* 125022 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44502 /* 125026 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44503 /* 125028 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44504 /* 125031 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44505 /* 125033 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44506 /* 125036 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44507 /* 125041 */ // GIR_Coverage, 2551,
44508 /* 125041 */ GIR_EraseRootFromParent_Done,
44509 /* 125042 */ // Label 2398: @125042
44510 /* 125042 */ GIM_Try, /*On fail goto*//*Label 2399*/ GIMT_Encode4(125108), // Rule ID 2559 //
44511 /* 125047 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44512 /* 125050 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44513 /* 125053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44514 /* 125057 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44515 /* 125061 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
44516 /* 125065 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44517 /* 125069 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44518 /* 125074 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44519 /* 125076 */ // (fp_to_sint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMSD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44520 /* 125076 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44521 /* 125079 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMSD),
44522 /* 125083 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44523 /* 125088 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44524 /* 125092 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44525 /* 125094 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44526 /* 125097 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44527 /* 125099 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44528 /* 125102 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44529 /* 125107 */ // GIR_Coverage, 2559,
44530 /* 125107 */ GIR_EraseRootFromParent_Done,
44531 /* 125108 */ // Label 2399: @125108
44532 /* 125108 */ GIM_Try, /*On fail goto*//*Label 2400*/ GIMT_Encode4(125174), // Rule ID 2495 //
44533 /* 125113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44534 /* 125116 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44535 /* 125119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44536 /* 125123 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44537 /* 125127 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
44538 /* 125131 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44539 /* 125135 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44540 /* 125140 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44541 /* 125142 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44542 /* 125142 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44543 /* 125145 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASH),
44544 /* 125149 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44545 /* 125154 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44546 /* 125158 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44547 /* 125160 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44548 /* 125163 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44549 /* 125165 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44550 /* 125168 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44551 /* 125173 */ // GIR_Coverage, 2495,
44552 /* 125173 */ GIR_EraseRootFromParent_Done,
44553 /* 125174 */ // Label 2400: @125174
44554 /* 125174 */ GIM_Try, /*On fail goto*//*Label 2401*/ GIMT_Encode4(125240), // Rule ID 2503 //
44555 /* 125179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
44556 /* 125182 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44557 /* 125185 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44558 /* 125189 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44559 /* 125193 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
44560 /* 125197 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44561 /* 125201 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44562 /* 125206 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44563 /* 125208 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44564 /* 125208 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44565 /* 125211 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASS),
44566 /* 125215 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44567 /* 125220 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44568 /* 125224 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44569 /* 125226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44570 /* 125229 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44571 /* 125231 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44572 /* 125234 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44573 /* 125239 */ // GIR_Coverage, 2503,
44574 /* 125239 */ GIR_EraseRootFromParent_Done,
44575 /* 125240 */ // Label 2401: @125240
44576 /* 125240 */ GIM_Try, /*On fail goto*//*Label 2402*/ GIMT_Encode4(125306), // Rule ID 2511 //
44577 /* 125245 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44578 /* 125248 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44579 /* 125251 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44580 /* 125255 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44581 /* 125259 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
44582 /* 125263 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44583 /* 125267 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44584 /* 125272 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44585 /* 125274 */ // (fp_to_sint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTASD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44586 /* 125274 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44587 /* 125277 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTASD),
44588 /* 125281 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44589 /* 125286 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44590 /* 125290 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44591 /* 125292 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44592 /* 125295 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44593 /* 125297 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44594 /* 125300 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44595 /* 125305 */ // GIR_Coverage, 2511,
44596 /* 125305 */ GIR_EraseRootFromParent_Done,
44597 /* 125306 */ // Label 2402: @125306
44598 /* 125306 */ GIM_Try, /*On fail goto*//*Label 2403*/ GIMT_Encode4(125366), // Rule ID 2592 //
44599 /* 125311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
44600 /* 125314 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44601 /* 125317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44602 /* 125321 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44603 /* 125325 */ // (fp_to_sint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44604 /* 125325 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44605 /* 125328 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZD),
44606 /* 125332 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44607 /* 125337 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44608 /* 125341 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44609 /* 125344 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44610 /* 125350 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44611 /* 125352 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44612 /* 125355 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44613 /* 125357 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44614 /* 125360 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44615 /* 125365 */ // GIR_Coverage, 2592,
44616 /* 125365 */ GIR_EraseRootFromParent_Done,
44617 /* 125366 */ // Label 2403: @125366
44618 /* 125366 */ GIM_Try, /*On fail goto*//*Label 2404*/ GIMT_Encode4(125426), // Rule ID 2598 //
44619 /* 125371 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
44620 /* 125374 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44621 /* 125377 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44622 /* 125381 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44623 /* 125385 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44624 /* 125385 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44625 /* 125388 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZS),
44626 /* 125392 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44627 /* 125397 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44628 /* 125401 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44629 /* 125404 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44630 /* 125410 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44631 /* 125412 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44632 /* 125415 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44633 /* 125417 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44634 /* 125420 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44635 /* 125425 */ // GIR_Coverage, 2598,
44636 /* 125425 */ GIR_EraseRootFromParent_Done,
44637 /* 125426 */ // Label 2404: @125426
44638 /* 125426 */ GIM_Try, /*On fail goto*//*Label 2405*/ GIMT_Encode4(125486), // Rule ID 2604 //
44639 /* 125431 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
44640 /* 125434 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44641 /* 125437 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44642 /* 125441 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44643 /* 125445 */ // (fp_to_sint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOSIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44644 /* 125445 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44645 /* 125448 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOSIZH),
44646 /* 125452 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44647 /* 125457 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
44648 /* 125461 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44649 /* 125464 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44650 /* 125470 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44651 /* 125472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44652 /* 125475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44653 /* 125477 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44654 /* 125480 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44655 /* 125485 */ // GIR_Coverage, 2604,
44656 /* 125485 */ GIR_EraseRootFromParent_Done,
44657 /* 125486 */ // Label 2405: @125486
44658 /* 125486 */ GIM_Try, /*On fail goto*//*Label 2406*/ GIMT_Encode4(125605), // Rule ID 3060 //
44659 /* 125491 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
44660 /* 125494 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44661 /* 125497 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44662 /* 125501 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44663 /* 125505 */ // (fp_to_sint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2sd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
44664 /* 125505 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
44665 /* 125508 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44666 /* 125512 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44667 /* 125517 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
44668 /* 125519 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
44669 /* 125522 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
44670 /* 125526 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44671 /* 125531 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
44672 /* 125534 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
44673 /* 125538 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
44674 /* 125541 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44675 /* 125546 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44676 /* 125551 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
44677 /* 125556 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
44678 /* 125559 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd),
44679 /* 125563 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44680 /* 125568 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
44681 /* 125571 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
44682 /* 125574 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44683 /* 125580 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44684 /* 125582 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44685 /* 125585 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44686 /* 125587 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
44687 /* 125594 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
44688 /* 125599 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
44689 /* 125604 */ // GIR_Coverage, 3060,
44690 /* 125604 */ GIR_EraseRootFromParent_Done,
44691 /* 125605 */ // Label 2406: @125605
44692 /* 125605 */ GIM_Reject,
44693 /* 125606 */ // Label 2387: @125606
44694 /* 125606 */ GIM_Try, /*On fail goto*//*Label 2407*/ GIMT_Encode4(125643), // Rule ID 1765 //
44695 /* 125611 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44696 /* 125614 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
44697 /* 125617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44698 /* 125621 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44699 /* 125625 */ // (fp_to_sint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2sd:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
44700 /* 125625 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sd),
44701 /* 125628 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44702 /* 125630 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44703 /* 125632 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44704 /* 125635 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44705 /* 125641 */ GIR_RootConstrainSelectedInstOperands,
44706 /* 125642 */ // GIR_Coverage, 1765,
44707 /* 125642 */ GIR_EraseRootFromParent_Done,
44708 /* 125643 */ // Label 2407: @125643
44709 /* 125643 */ GIM_Reject,
44710 /* 125644 */ // Label 2388: @125644
44711 /* 125644 */ GIM_Try, /*On fail goto*//*Label 2408*/ GIMT_Encode4(125696), // Rule ID 5583 //
44712 /* 125649 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44713 /* 125652 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44714 /* 125655 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
44715 /* 125659 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44716 /* 125663 */ // (fp_to_sint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
44717 /* 125663 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r),
44718 /* 125666 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
44719 /* 125668 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
44720 /* 125670 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44721 /* 125676 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44722 /* 125679 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44723 /* 125682 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44724 /* 125688 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44725 /* 125694 */ GIR_RootConstrainSelectedInstOperands,
44726 /* 125695 */ // GIR_Coverage, 5583,
44727 /* 125695 */ GIR_EraseRootFromParent_Done,
44728 /* 125696 */ // Label 2408: @125696
44729 /* 125696 */ GIM_Reject,
44730 /* 125697 */ // Label 2389: @125697
44731 /* 125697 */ GIM_Try, /*On fail goto*//*Label 2409*/ GIMT_Encode4(125734), // Rule ID 1773 //
44732 /* 125702 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44733 /* 125705 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
44734 /* 125708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44735 /* 125712 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44736 /* 125716 */ // (fp_to_sint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2sd:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
44737 /* 125716 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sd),
44738 /* 125719 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44739 /* 125721 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44740 /* 125723 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44741 /* 125726 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44742 /* 125732 */ GIR_RootConstrainSelectedInstOperands,
44743 /* 125733 */ // GIR_Coverage, 1773,
44744 /* 125733 */ GIR_EraseRootFromParent_Done,
44745 /* 125734 */ // Label 2409: @125734
44746 /* 125734 */ GIM_Reject,
44747 /* 125735 */ // Label 2390: @125735
44748 /* 125735 */ GIM_Try, /*On fail goto*//*Label 2410*/ GIMT_Encode4(125833),
44749 /* 125740 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
44750 /* 125743 */ GIM_Try, /*On fail goto*//*Label 2411*/ GIMT_Encode4(125777), // Rule ID 1769 //
44751 /* 125748 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
44752 /* 125751 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44753 /* 125755 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44754 /* 125759 */ // (fp_to_sint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2sq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
44755 /* 125759 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2sq),
44756 /* 125762 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44757 /* 125764 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44758 /* 125766 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44759 /* 125769 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44760 /* 125775 */ GIR_RootConstrainSelectedInstOperands,
44761 /* 125776 */ // GIR_Coverage, 1769,
44762 /* 125776 */ GIR_EraseRootFromParent_Done,
44763 /* 125777 */ // Label 2411: @125777
44764 /* 125777 */ GIM_Try, /*On fail goto*//*Label 2412*/ GIMT_Encode4(125832), // Rule ID 4490 //
44765 /* 125782 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44766 /* 125785 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44767 /* 125789 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44768 /* 125793 */ // (fp_to_sint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTs32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
44769 /* 125793 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44770 /* 125796 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44771 /* 125800 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44772 /* 125805 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs32f32z),
44773 /* 125808 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44774 /* 125810 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
44775 /* 125812 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44776 /* 125815 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44777 /* 125821 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44778 /* 125827 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44779 /* 125830 */ GIR_RootConstrainSelectedInstOperands,
44780 /* 125831 */ // GIR_Coverage, 4490,
44781 /* 125831 */ GIR_EraseRootFromParent_Done,
44782 /* 125832 */ // Label 2412: @125832
44783 /* 125832 */ GIM_Reject,
44784 /* 125833 */ // Label 2410: @125833
44785 /* 125833 */ GIM_Reject,
44786 /* 125834 */ // Label 2391: @125834
44787 /* 125834 */ GIM_Try, /*On fail goto*//*Label 2413*/ GIMT_Encode4(125886), // Rule ID 5584 //
44788 /* 125839 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44789 /* 125842 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
44790 /* 125845 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
44791 /* 125849 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44792 /* 125853 */ // (fp_to_sint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
44793 /* 125853 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r),
44794 /* 125856 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
44795 /* 125858 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
44796 /* 125860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44797 /* 125866 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
44798 /* 125869 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44799 /* 125872 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44800 /* 125878 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44801 /* 125884 */ GIR_RootConstrainSelectedInstOperands,
44802 /* 125885 */ // GIR_Coverage, 5584,
44803 /* 125885 */ GIR_EraseRootFromParent_Done,
44804 /* 125886 */ // Label 2413: @125886
44805 /* 125886 */ GIM_Reject,
44806 /* 125887 */ // Label 2392: @125887
44807 /* 125887 */ GIM_Try, /*On fail goto*//*Label 2414*/ GIMT_Encode4(125985),
44808 /* 125892 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
44809 /* 125895 */ GIM_Try, /*On fail goto*//*Label 2415*/ GIMT_Encode4(125929), // Rule ID 1777 //
44810 /* 125900 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
44811 /* 125903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44812 /* 125907 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
44813 /* 125911 */ // (fp_to_sint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2sq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
44814 /* 125911 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2sq),
44815 /* 125914 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
44816 /* 125916 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
44817 /* 125918 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
44818 /* 125921 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44819 /* 125927 */ GIR_RootConstrainSelectedInstOperands,
44820 /* 125928 */ // GIR_Coverage, 1777,
44821 /* 125928 */ GIR_EraseRootFromParent_Done,
44822 /* 125929 */ // Label 2415: @125929
44823 /* 125929 */ GIM_Try, /*On fail goto*//*Label 2416*/ GIMT_Encode4(125984), // Rule ID 4484 //
44824 /* 125934 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
44825 /* 125937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44826 /* 125941 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
44827 /* 125945 */ // (fp_to_sint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTs16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
44828 /* 125945 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
44829 /* 125948 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
44830 /* 125952 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44831 /* 125957 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTs16f16z),
44832 /* 125960 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
44833 /* 125962 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
44834 /* 125964 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
44835 /* 125967 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44836 /* 125973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
44837 /* 125979 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44838 /* 125982 */ GIR_RootConstrainSelectedInstOperands,
44839 /* 125983 */ // GIR_Coverage, 4484,
44840 /* 125983 */ GIR_EraseRootFromParent_Done,
44841 /* 125984 */ // Label 2416: @125984
44842 /* 125984 */ GIM_Reject,
44843 /* 125985 */ // Label 2414: @125985
44844 /* 125985 */ GIM_Reject,
44845 /* 125986 */ // Label 2393: @125986
44846 /* 125986 */ GIM_Reject,
44847 /* 125987 */ // Label 49: @125987
44848 /* 125987 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2424*/ GIMT_Encode4(127320),
44849 /* 125998 */ /*GILLT_s32*//*Label 2417*/ GIMT_Encode4(126046), GIMT_Encode4(0), GIMT_Encode4(0),
44850 /* 126010 */ /*GILLT_v2s32*//*Label 2418*/ GIMT_Encode4(126940), GIMT_Encode4(0),
44851 /* 126018 */ /*GILLT_v4s1*//*Label 2419*/ GIMT_Encode4(126978),
44852 /* 126022 */ /*GILLT_v4s16*//*Label 2420*/ GIMT_Encode4(127031),
44853 /* 126026 */ /*GILLT_v4s32*//*Label 2421*/ GIMT_Encode4(127069), GIMT_Encode4(0),
44854 /* 126034 */ /*GILLT_v8s1*//*Label 2422*/ GIMT_Encode4(127168), GIMT_Encode4(0),
44855 /* 126042 */ /*GILLT_v8s16*//*Label 2423*/ GIMT_Encode4(127221),
44856 /* 126046 */ // Label 2417: @126046
44857 /* 126046 */ GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(126112), // Rule ID 2523 //
44858 /* 126051 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44859 /* 126054 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44860 /* 126057 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44861 /* 126061 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44862 /* 126065 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
44863 /* 126069 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44864 /* 126073 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44865 /* 126078 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44866 /* 126080 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44867 /* 126080 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44868 /* 126083 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUH),
44869 /* 126087 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44870 /* 126092 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44871 /* 126096 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44872 /* 126098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44873 /* 126101 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44874 /* 126103 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44875 /* 126106 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44876 /* 126111 */ // GIR_Coverage, 2523,
44877 /* 126111 */ GIR_EraseRootFromParent_Done,
44878 /* 126112 */ // Label 2425: @126112
44879 /* 126112 */ GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(126178), // Rule ID 2531 //
44880 /* 126117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
44881 /* 126120 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44882 /* 126123 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44883 /* 126127 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44884 /* 126131 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
44885 /* 126135 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44886 /* 126139 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44887 /* 126144 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44888 /* 126146 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44889 /* 126146 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44890 /* 126149 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUS),
44891 /* 126153 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44892 /* 126158 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44893 /* 126162 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44894 /* 126164 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44895 /* 126167 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44896 /* 126169 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44897 /* 126172 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44898 /* 126177 */ // GIR_Coverage, 2531,
44899 /* 126177 */ GIR_EraseRootFromParent_Done,
44900 /* 126178 */ // Label 2426: @126178
44901 /* 126178 */ GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(126244), // Rule ID 2539 //
44902 /* 126183 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44903 /* 126186 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44904 /* 126189 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44905 /* 126193 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44906 /* 126197 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCEIL),
44907 /* 126201 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44908 /* 126205 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44909 /* 126210 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44910 /* 126212 */ // (fp_to_uint:{ *:[i32] } (fceil:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTPUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44911 /* 126212 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44912 /* 126215 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTPUD),
44913 /* 126219 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44914 /* 126224 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44915 /* 126228 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44916 /* 126230 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44917 /* 126233 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44918 /* 126235 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44919 /* 126238 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44920 /* 126243 */ // GIR_Coverage, 2539,
44921 /* 126243 */ GIR_EraseRootFromParent_Done,
44922 /* 126244 */ // Label 2427: @126244
44923 /* 126244 */ GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(126310), // Rule ID 2547 //
44924 /* 126249 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44925 /* 126252 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44926 /* 126255 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44927 /* 126259 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44928 /* 126263 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
44929 /* 126267 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44930 /* 126271 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44931 /* 126276 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44932 /* 126278 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44933 /* 126278 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44934 /* 126281 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUH),
44935 /* 126285 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44936 /* 126290 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44937 /* 126294 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44938 /* 126296 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44939 /* 126299 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44940 /* 126301 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44941 /* 126304 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44942 /* 126309 */ // GIR_Coverage, 2547,
44943 /* 126309 */ GIR_EraseRootFromParent_Done,
44944 /* 126310 */ // Label 2428: @126310
44945 /* 126310 */ GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(126376), // Rule ID 2555 //
44946 /* 126315 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
44947 /* 126318 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
44948 /* 126321 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44949 /* 126325 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44950 /* 126329 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
44951 /* 126333 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
44952 /* 126337 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
44953 /* 126342 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44954 /* 126344 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
44955 /* 126344 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44956 /* 126347 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUS),
44957 /* 126351 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44958 /* 126356 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44959 /* 126360 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44960 /* 126362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44961 /* 126365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44962 /* 126367 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44963 /* 126370 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44964 /* 126375 */ // GIR_Coverage, 2555,
44965 /* 126375 */ GIR_EraseRootFromParent_Done,
44966 /* 126376 */ // Label 2429: @126376
44967 /* 126376 */ GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(126442), // Rule ID 2563 //
44968 /* 126381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
44969 /* 126384 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
44970 /* 126387 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44971 /* 126391 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44972 /* 126395 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FFLOOR),
44973 /* 126399 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
44974 /* 126403 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
44975 /* 126408 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44976 /* 126410 */ // (fp_to_uint:{ *:[i32] } (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTMUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
44977 /* 126410 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
44978 /* 126413 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTMUD),
44979 /* 126417 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
44980 /* 126422 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
44981 /* 126426 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
44982 /* 126428 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
44983 /* 126431 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
44984 /* 126433 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
44985 /* 126436 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
44986 /* 126441 */ // GIR_Coverage, 2563,
44987 /* 126441 */ GIR_EraseRootFromParent_Done,
44988 /* 126442 */ // Label 2430: @126442
44989 /* 126442 */ GIM_Try, /*On fail goto*//*Label 2431*/ GIMT_Encode4(126508), // Rule ID 2499 //
44990 /* 126447 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
44991 /* 126450 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
44992 /* 126453 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
44993 /* 126457 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
44994 /* 126461 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
44995 /* 126465 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
44996 /* 126469 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
44997 /* 126474 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
44998 /* 126476 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f16] } HPR:{ *:[f16] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
44999 /* 126476 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45000 /* 126479 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUH),
45001 /* 126483 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45002 /* 126488 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
45003 /* 126492 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45004 /* 126494 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45005 /* 126497 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45006 /* 126499 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45007 /* 126502 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
45008 /* 126507 */ // GIR_Coverage, 2499,
45009 /* 126507 */ GIR_EraseRootFromParent_Done,
45010 /* 126508 */ // Label 2431: @126508
45011 /* 126508 */ GIM_Try, /*On fail goto*//*Label 2432*/ GIMT_Encode4(126574), // Rule ID 2507 //
45012 /* 126513 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
45013 /* 126516 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45014 /* 126519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45015 /* 126523 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45016 /* 126527 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
45017 /* 126531 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
45018 /* 126535 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45019 /* 126540 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45020 /* 126542 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f32] } SPR:{ *:[f32] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
45021 /* 126542 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45022 /* 126545 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUS),
45023 /* 126549 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45024 /* 126554 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
45025 /* 126558 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45026 /* 126560 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45027 /* 126563 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45028 /* 126565 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45029 /* 126568 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
45030 /* 126573 */ // GIR_Coverage, 2507,
45031 /* 126573 */ GIR_EraseRootFromParent_Done,
45032 /* 126574 */ // Label 2432: @126574
45033 /* 126574 */ GIM_Try, /*On fail goto*//*Label 2433*/ GIMT_Encode4(126640), // Rule ID 2515 //
45034 /* 126579 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
45035 /* 126582 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
45036 /* 126585 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45037 /* 126589 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45038 /* 126593 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND),
45039 /* 126597 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
45040 /* 126601 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45041 /* 126606 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45042 /* 126608 */ // (fp_to_uint:{ *:[i32] } (fround:{ *:[f64] } DPR:{ *:[f64] }:$a)) => (COPY_TO_REGCLASS:{ *:[i32] } (VCVTAUD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
45043 /* 126608 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45044 /* 126611 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTAUD),
45045 /* 126615 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45046 /* 126620 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // a
45047 /* 126624 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45048 /* 126626 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45049 /* 126629 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45050 /* 126631 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45051 /* 126634 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
45052 /* 126639 */ // GIR_Coverage, 2515,
45053 /* 126639 */ GIR_EraseRootFromParent_Done,
45054 /* 126640 */ // Label 2433: @126640
45055 /* 126640 */ GIM_Try, /*On fail goto*//*Label 2434*/ GIMT_Encode4(126700), // Rule ID 2607 //
45056 /* 126645 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
45057 /* 126648 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
45058 /* 126651 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45059 /* 126655 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45060 /* 126659 */ // (fp_to_uint:{ *:[i32] } DPR:{ *:[f64] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZD:{ *:[f32] } DPR:{ *:[f64] }:$a), GPR:{ *:[i32] })
45061 /* 126659 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45062 /* 126662 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZD),
45063 /* 126666 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45064 /* 126671 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
45065 /* 126675 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
45066 /* 126678 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45067 /* 126684 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45068 /* 126686 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45069 /* 126689 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45070 /* 126691 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45071 /* 126694 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
45072 /* 126699 */ // GIR_Coverage, 2607,
45073 /* 126699 */ GIR_EraseRootFromParent_Done,
45074 /* 126700 */ // Label 2434: @126700
45075 /* 126700 */ GIM_Try, /*On fail goto*//*Label 2435*/ GIMT_Encode4(126760), // Rule ID 2613 //
45076 /* 126705 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
45077 /* 126708 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45078 /* 126711 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45079 /* 126715 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45080 /* 126719 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZS:{ *:[f32] } SPR:{ *:[f32] }:$a), GPR:{ *:[i32] })
45081 /* 126719 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45082 /* 126722 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZS),
45083 /* 126726 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45084 /* 126731 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
45085 /* 126735 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
45086 /* 126738 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45087 /* 126744 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45088 /* 126746 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45089 /* 126749 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45090 /* 126751 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45091 /* 126754 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
45092 /* 126759 */ // GIR_Coverage, 2613,
45093 /* 126759 */ GIR_EraseRootFromParent_Done,
45094 /* 126760 */ // Label 2435: @126760
45095 /* 126760 */ GIM_Try, /*On fail goto*//*Label 2436*/ GIMT_Encode4(126820), // Rule ID 2619 //
45096 /* 126765 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
45097 /* 126768 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
45098 /* 126771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45099 /* 126775 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45100 /* 126779 */ // (fp_to_uint:{ *:[i32] } HPR:{ *:[f16] }:$a) => (COPY_TO_REGCLASS:{ *:[i32] } (VTOUIZH:{ *:[f32] } HPR:{ *:[f16] }:$a), GPR:{ *:[i32] })
45101 /* 126779 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45102 /* 126782 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VTOUIZH),
45103 /* 126786 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45104 /* 126791 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
45105 /* 126795 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
45106 /* 126798 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45107 /* 126804 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45108 /* 126806 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45109 /* 126809 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45110 /* 126811 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45111 /* 126814 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::GPRRegClassID),
45112 /* 126819 */ // GIR_Coverage, 2619,
45113 /* 126819 */ GIR_EraseRootFromParent_Done,
45114 /* 126820 */ // Label 2436: @126820
45115 /* 126820 */ GIM_Try, /*On fail goto*//*Label 2437*/ GIMT_Encode4(126939), // Rule ID 3061 //
45116 /* 126825 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
45117 /* 126828 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45118 /* 126831 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45119 /* 126835 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45120 /* 126839 */ // (fp_to_uint:{ *:[i32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[i32] } (VCVTf2ud:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
45121 /* 126839 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
45122 /* 126842 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45123 /* 126846 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45124 /* 126851 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45125 /* 126853 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
45126 /* 126856 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45127 /* 126860 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45128 /* 126865 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
45129 /* 126868 */ GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a
45130 /* 126872 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
45131 /* 126875 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45132 /* 126880 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45133 /* 126885 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
45134 /* 126890 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
45135 /* 126893 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud),
45136 /* 126897 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45137 /* 126902 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45138 /* 126905 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
45139 /* 126908 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45140 /* 126914 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45141 /* 126916 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45142 /* 126919 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45143 /* 126921 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
45144 /* 126928 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45145 /* 126933 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45146 /* 126938 */ // GIR_Coverage, 3061,
45147 /* 126938 */ GIR_EraseRootFromParent_Done,
45148 /* 126939 */ // Label 2437: @126939
45149 /* 126939 */ GIM_Reject,
45150 /* 126940 */ // Label 2418: @126940
45151 /* 126940 */ GIM_Try, /*On fail goto*//*Label 2438*/ GIMT_Encode4(126977), // Rule ID 1766 //
45152 /* 126945 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45153 /* 126948 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45154 /* 126951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45155 /* 126955 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45156 /* 126959 */ // (fp_to_uint:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm) => (VCVTf2ud:{ *:[v2i32] } DPR:{ *:[v2f32] }:$Vm)
45157 /* 126959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2ud),
45158 /* 126962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45159 /* 126964 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45160 /* 126966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45161 /* 126969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45162 /* 126975 */ GIR_RootConstrainSelectedInstOperands,
45163 /* 126976 */ // GIR_Coverage, 1766,
45164 /* 126976 */ GIR_EraseRootFromParent_Done,
45165 /* 126977 */ // Label 2438: @126977
45166 /* 126977 */ GIM_Reject,
45167 /* 126978 */ // Label 2419: @126978
45168 /* 126978 */ GIM_Try, /*On fail goto*//*Label 2439*/ GIMT_Encode4(127030), // Rule ID 5581 //
45169 /* 126983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45170 /* 126986 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45171 /* 126989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
45172 /* 126993 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45173 /* 126997 */ // (fp_to_uint:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1) => (MVE_VCMPf32r:{ *:[v4i1] } MQPR:{ *:[v4f32] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
45174 /* 126997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf32r),
45175 /* 127000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
45176 /* 127002 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
45177 /* 127004 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45178 /* 127010 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
45179 /* 127013 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45180 /* 127016 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45181 /* 127022 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45182 /* 127028 */ GIR_RootConstrainSelectedInstOperands,
45183 /* 127029 */ // GIR_Coverage, 5581,
45184 /* 127029 */ GIR_EraseRootFromParent_Done,
45185 /* 127030 */ // Label 2439: @127030
45186 /* 127030 */ GIM_Reject,
45187 /* 127031 */ // Label 2420: @127031
45188 /* 127031 */ GIM_Try, /*On fail goto*//*Label 2440*/ GIMT_Encode4(127068), // Rule ID 1774 //
45189 /* 127036 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45190 /* 127039 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45191 /* 127042 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45192 /* 127046 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45193 /* 127050 */ // (fp_to_uint:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm) => (VCVTh2ud:{ *:[v4i16] } DPR:{ *:[v4f16] }:$Vm)
45194 /* 127050 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2ud),
45195 /* 127053 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45196 /* 127055 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45197 /* 127057 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45198 /* 127060 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45199 /* 127066 */ GIR_RootConstrainSelectedInstOperands,
45200 /* 127067 */ // GIR_Coverage, 1774,
45201 /* 127067 */ GIR_EraseRootFromParent_Done,
45202 /* 127068 */ // Label 2440: @127068
45203 /* 127068 */ GIM_Reject,
45204 /* 127069 */ // Label 2421: @127069
45205 /* 127069 */ GIM_Try, /*On fail goto*//*Label 2441*/ GIMT_Encode4(127167),
45206 /* 127074 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45207 /* 127077 */ GIM_Try, /*On fail goto*//*Label 2442*/ GIMT_Encode4(127111), // Rule ID 1770 //
45208 /* 127082 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45209 /* 127085 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45210 /* 127089 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45211 /* 127093 */ // (fp_to_uint:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm) => (VCVTf2uq:{ *:[v4i32] } QPR:{ *:[v4f32] }:$Vm)
45212 /* 127093 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTf2uq),
45213 /* 127096 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45214 /* 127098 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45215 /* 127100 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45216 /* 127103 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45217 /* 127109 */ GIR_RootConstrainSelectedInstOperands,
45218 /* 127110 */ // GIR_Coverage, 1770,
45219 /* 127110 */ GIR_EraseRootFromParent_Done,
45220 /* 127111 */ // Label 2442: @127111
45221 /* 127111 */ GIM_Try, /*On fail goto*//*Label 2443*/ GIMT_Encode4(127166), // Rule ID 4493 //
45222 /* 127116 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45223 /* 127119 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45224 /* 127123 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45225 /* 127127 */ // (fp_to_uint:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src) => (MVE_VCVTu32f32z:{ *:[v4i32] } MQPR:{ *:[v4f32] }:$src)
45226 /* 127127 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45227 /* 127130 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45228 /* 127134 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45229 /* 127139 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu32f32z),
45230 /* 127142 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45231 /* 127144 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
45232 /* 127146 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45233 /* 127149 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45234 /* 127155 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45235 /* 127161 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45236 /* 127164 */ GIR_RootConstrainSelectedInstOperands,
45237 /* 127165 */ // GIR_Coverage, 4493,
45238 /* 127165 */ GIR_EraseRootFromParent_Done,
45239 /* 127166 */ // Label 2443: @127166
45240 /* 127166 */ GIM_Reject,
45241 /* 127167 */ // Label 2441: @127167
45242 /* 127167 */ GIM_Reject,
45243 /* 127168 */ // Label 2422: @127168
45244 /* 127168 */ GIM_Try, /*On fail goto*//*Label 2444*/ GIMT_Encode4(127220), // Rule ID 5582 //
45245 /* 127173 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45246 /* 127176 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45247 /* 127179 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::VCCRRegClassID),
45248 /* 127183 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45249 /* 127187 */ // (fp_to_uint:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1) => (MVE_VCMPf16r:{ *:[v8i1] } MQPR:{ *:[v8f16] }:$v1, ZR:{ *:[i32] }, 1:{ *:[i32] })
45250 /* 127187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCMPf16r),
45251 /* 127190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[P0]
45252 /* 127192 */ GIR_RootToRootCopy, /*OpIdx*/1, // v1
45253 /* 127194 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::ZR), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45254 /* 127200 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/1,
45255 /* 127203 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45256 /* 127206 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45257 /* 127212 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45258 /* 127218 */ GIR_RootConstrainSelectedInstOperands,
45259 /* 127219 */ // GIR_Coverage, 5582,
45260 /* 127219 */ GIR_EraseRootFromParent_Done,
45261 /* 127220 */ // Label 2444: @127220
45262 /* 127220 */ GIM_Reject,
45263 /* 127221 */ // Label 2423: @127221
45264 /* 127221 */ GIM_Try, /*On fail goto*//*Label 2445*/ GIMT_Encode4(127319),
45265 /* 127226 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45266 /* 127229 */ GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(127263), // Rule ID 1778 //
45267 /* 127234 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45268 /* 127237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45269 /* 127241 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45270 /* 127245 */ // (fp_to_uint:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm) => (VCVTh2uq:{ *:[v8i16] } QPR:{ *:[v8f16] }:$Vm)
45271 /* 127245 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTh2uq),
45272 /* 127248 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45273 /* 127250 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45274 /* 127252 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45275 /* 127255 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45276 /* 127261 */ GIR_RootConstrainSelectedInstOperands,
45277 /* 127262 */ // GIR_Coverage, 1778,
45278 /* 127262 */ GIR_EraseRootFromParent_Done,
45279 /* 127263 */ // Label 2446: @127263
45280 /* 127263 */ GIM_Try, /*On fail goto*//*Label 2447*/ GIMT_Encode4(127318), // Rule ID 4487 //
45281 /* 127268 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45282 /* 127271 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45283 /* 127275 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45284 /* 127279 */ // (fp_to_uint:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src) => (MVE_VCVTu16f16z:{ *:[v8i16] } MQPR:{ *:[v8f16] }:$src)
45285 /* 127279 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45286 /* 127282 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45287 /* 127286 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45288 /* 127291 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTu16f16z),
45289 /* 127294 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45290 /* 127296 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
45291 /* 127298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45292 /* 127301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45293 /* 127307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45294 /* 127313 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45295 /* 127316 */ GIR_RootConstrainSelectedInstOperands,
45296 /* 127317 */ // GIR_Coverage, 4487,
45297 /* 127317 */ GIR_EraseRootFromParent_Done,
45298 /* 127318 */ // Label 2447: @127318
45299 /* 127318 */ GIM_Reject,
45300 /* 127319 */ // Label 2445: @127319
45301 /* 127319 */ GIM_Reject,
45302 /* 127320 */ // Label 2424: @127320
45303 /* 127320 */ GIM_Reject,
45304 /* 127321 */ // Label 50: @127321
45305 /* 127321 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2455*/ GIMT_Encode4(127972),
45306 /* 127332 */ /*GILLT_s16*//*Label 2448*/ GIMT_Encode4(127384),
45307 /* 127336 */ /*GILLT_s32*//*Label 2449*/ GIMT_Encode4(127444),
45308 /* 127340 */ /*GILLT_s64*//*Label 2450*/ GIMT_Encode4(127638), GIMT_Encode4(0),
45309 /* 127348 */ /*GILLT_v2s32*//*Label 2451*/ GIMT_Encode4(127698), GIMT_Encode4(0), GIMT_Encode4(0),
45310 /* 127360 */ /*GILLT_v4s16*//*Label 2452*/ GIMT_Encode4(127736),
45311 /* 127364 */ /*GILLT_v4s32*//*Label 2453*/ GIMT_Encode4(127774), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45312 /* 127380 */ /*GILLT_v8s16*//*Label 2454*/ GIMT_Encode4(127873),
45313 /* 127384 */ // Label 2448: @127384
45314 /* 127384 */ GIM_Try, /*On fail goto*//*Label 2456*/ GIMT_Encode4(127443), // Rule ID 2580 //
45315 /* 127389 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
45316 /* 127392 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45317 /* 127395 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45318 /* 127399 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45319 /* 127403 */ // (sint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VSITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
45320 /* 127403 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45321 /* 127406 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45322 /* 127410 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45323 /* 127415 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
45324 /* 127419 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45325 /* 127424 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOH),
45326 /* 127427 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
45327 /* 127429 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45328 /* 127432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45329 /* 127435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45330 /* 127441 */ GIR_RootConstrainSelectedInstOperands,
45331 /* 127442 */ // GIR_Coverage, 2580,
45332 /* 127442 */ GIR_EraseRootFromParent_Done,
45333 /* 127443 */ // Label 2456: @127443
45334 /* 127443 */ GIM_Reject,
45335 /* 127444 */ // Label 2449: @127444
45336 /* 127444 */ GIM_Try, /*On fail goto*//*Label 2457*/ GIMT_Encode4(127637),
45337 /* 127449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45338 /* 127452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45339 /* 127456 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45340 /* 127460 */ GIM_Try, /*On fail goto*//*Label 2458*/ GIMT_Encode4(127508), // Rule ID 2576 //
45341 /* 127465 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
45342 /* 127468 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VSITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
45343 /* 127468 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45344 /* 127471 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45345 /* 127475 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45346 /* 127480 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
45347 /* 127484 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45348 /* 127489 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOS),
45349 /* 127492 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
45350 /* 127494 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45351 /* 127497 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45352 /* 127500 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45353 /* 127506 */ GIR_RootConstrainSelectedInstOperands,
45354 /* 127507 */ // GIR_Coverage, 2576,
45355 /* 127507 */ GIR_EraseRootFromParent_Done,
45356 /* 127508 */ // Label 2458: @127508
45357 /* 127508 */ GIM_Try, /*On fail goto*//*Label 2459*/ GIMT_Encode4(127636), // Rule ID 3062 //
45358 /* 127513 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
45359 /* 127516 */ // (sint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTs2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
45360 /* 127516 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
45361 /* 127519 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45362 /* 127523 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45363 /* 127528 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a
45364 /* 127532 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45365 /* 127537 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
45366 /* 127540 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45367 /* 127544 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45368 /* 127549 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45369 /* 127551 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
45370 /* 127554 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45371 /* 127558 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45372 /* 127563 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
45373 /* 127566 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
45374 /* 127569 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
45375 /* 127572 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45376 /* 127577 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45377 /* 127582 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
45378 /* 127587 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
45379 /* 127590 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd),
45380 /* 127594 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45381 /* 127599 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45382 /* 127602 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
45383 /* 127605 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45384 /* 127611 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45385 /* 127613 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45386 /* 127616 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45387 /* 127618 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
45388 /* 127625 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45389 /* 127630 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45390 /* 127635 */ // GIR_Coverage, 3062,
45391 /* 127635 */ GIR_EraseRootFromParent_Done,
45392 /* 127636 */ // Label 2459: @127636
45393 /* 127636 */ GIM_Reject,
45394 /* 127637 */ // Label 2457: @127637
45395 /* 127637 */ GIM_Reject,
45396 /* 127638 */ // Label 2450: @127638
45397 /* 127638 */ GIM_Try, /*On fail goto*//*Label 2460*/ GIMT_Encode4(127697), // Rule ID 2572 //
45398 /* 127643 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
45399 /* 127646 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45400 /* 127649 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45401 /* 127653 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45402 /* 127657 */ // (sint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VSITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
45403 /* 127657 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45404 /* 127660 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45405 /* 127664 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45406 /* 127669 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
45407 /* 127673 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45408 /* 127678 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSITOD),
45409 /* 127681 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
45410 /* 127683 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45411 /* 127686 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45412 /* 127689 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45413 /* 127695 */ GIR_RootConstrainSelectedInstOperands,
45414 /* 127696 */ // GIR_Coverage, 2572,
45415 /* 127696 */ GIR_EraseRootFromParent_Done,
45416 /* 127697 */ // Label 2460: @127697
45417 /* 127697 */ GIM_Reject,
45418 /* 127698 */ // Label 2451: @127698
45419 /* 127698 */ GIM_Try, /*On fail goto*//*Label 2461*/ GIMT_Encode4(127735), // Rule ID 1767 //
45420 /* 127703 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45421 /* 127706 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45422 /* 127709 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45423 /* 127713 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45424 /* 127717 */ // (sint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTs2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
45425 /* 127717 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fd),
45426 /* 127720 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45427 /* 127722 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45428 /* 127724 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45429 /* 127727 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45430 /* 127733 */ GIR_RootConstrainSelectedInstOperands,
45431 /* 127734 */ // GIR_Coverage, 1767,
45432 /* 127734 */ GIR_EraseRootFromParent_Done,
45433 /* 127735 */ // Label 2461: @127735
45434 /* 127735 */ GIM_Reject,
45435 /* 127736 */ // Label 2452: @127736
45436 /* 127736 */ GIM_Try, /*On fail goto*//*Label 2462*/ GIMT_Encode4(127773), // Rule ID 1775 //
45437 /* 127741 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45438 /* 127744 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45439 /* 127747 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45440 /* 127751 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45441 /* 127755 */ // (sint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTs2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
45442 /* 127755 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hd),
45443 /* 127758 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45444 /* 127760 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45445 /* 127762 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45446 /* 127765 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45447 /* 127771 */ GIR_RootConstrainSelectedInstOperands,
45448 /* 127772 */ // GIR_Coverage, 1775,
45449 /* 127772 */ GIR_EraseRootFromParent_Done,
45450 /* 127773 */ // Label 2462: @127773
45451 /* 127773 */ GIM_Reject,
45452 /* 127774 */ // Label 2453: @127774
45453 /* 127774 */ GIM_Try, /*On fail goto*//*Label 2463*/ GIMT_Encode4(127872),
45454 /* 127779 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45455 /* 127782 */ GIM_Try, /*On fail goto*//*Label 2464*/ GIMT_Encode4(127816), // Rule ID 1771 //
45456 /* 127787 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45457 /* 127790 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45458 /* 127794 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45459 /* 127798 */ // (sint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTs2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
45460 /* 127798 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2fq),
45461 /* 127801 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45462 /* 127803 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45463 /* 127805 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45464 /* 127808 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45465 /* 127814 */ GIR_RootConstrainSelectedInstOperands,
45466 /* 127815 */ // GIR_Coverage, 1771,
45467 /* 127815 */ GIR_EraseRootFromParent_Done,
45468 /* 127816 */ // Label 2464: @127816
45469 /* 127816 */ GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(127871), // Rule ID 4502 //
45470 /* 127821 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45471 /* 127824 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45472 /* 127828 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45473 /* 127832 */ // (sint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32s32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
45474 /* 127832 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45475 /* 127835 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45476 /* 127839 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45477 /* 127844 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32s32n),
45478 /* 127847 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45479 /* 127849 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
45480 /* 127851 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45481 /* 127854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45482 /* 127860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45483 /* 127866 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45484 /* 127869 */ GIR_RootConstrainSelectedInstOperands,
45485 /* 127870 */ // GIR_Coverage, 4502,
45486 /* 127870 */ GIR_EraseRootFromParent_Done,
45487 /* 127871 */ // Label 2465: @127871
45488 /* 127871 */ GIM_Reject,
45489 /* 127872 */ // Label 2463: @127872
45490 /* 127872 */ GIM_Reject,
45491 /* 127873 */ // Label 2454: @127873
45492 /* 127873 */ GIM_Try, /*On fail goto*//*Label 2466*/ GIMT_Encode4(127971),
45493 /* 127878 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45494 /* 127881 */ GIM_Try, /*On fail goto*//*Label 2467*/ GIMT_Encode4(127915), // Rule ID 1779 //
45495 /* 127886 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45496 /* 127889 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45497 /* 127893 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45498 /* 127897 */ // (sint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTs2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
45499 /* 127897 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTs2hq),
45500 /* 127900 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45501 /* 127902 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45502 /* 127904 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45503 /* 127907 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45504 /* 127913 */ GIR_RootConstrainSelectedInstOperands,
45505 /* 127914 */ // GIR_Coverage, 1779,
45506 /* 127914 */ GIR_EraseRootFromParent_Done,
45507 /* 127915 */ // Label 2467: @127915
45508 /* 127915 */ GIM_Try, /*On fail goto*//*Label 2468*/ GIMT_Encode4(127970), // Rule ID 4496 //
45509 /* 127920 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45510 /* 127923 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45511 /* 127927 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45512 /* 127931 */ // (sint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16s16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
45513 /* 127931 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45514 /* 127934 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45515 /* 127938 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45516 /* 127943 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16s16n),
45517 /* 127946 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45518 /* 127948 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
45519 /* 127950 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45520 /* 127953 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45521 /* 127959 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45522 /* 127965 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45523 /* 127968 */ GIR_RootConstrainSelectedInstOperands,
45524 /* 127969 */ // GIR_Coverage, 4496,
45525 /* 127969 */ GIR_EraseRootFromParent_Done,
45526 /* 127970 */ // Label 2468: @127970
45527 /* 127970 */ GIM_Reject,
45528 /* 127971 */ // Label 2466: @127971
45529 /* 127971 */ GIM_Reject,
45530 /* 127972 */ // Label 2455: @127972
45531 /* 127972 */ GIM_Reject,
45532 /* 127973 */ // Label 51: @127973
45533 /* 127973 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2476*/ GIMT_Encode4(128624),
45534 /* 127984 */ /*GILLT_s16*//*Label 2469*/ GIMT_Encode4(128036),
45535 /* 127988 */ /*GILLT_s32*//*Label 2470*/ GIMT_Encode4(128096),
45536 /* 127992 */ /*GILLT_s64*//*Label 2471*/ GIMT_Encode4(128290), GIMT_Encode4(0),
45537 /* 128000 */ /*GILLT_v2s32*//*Label 2472*/ GIMT_Encode4(128350), GIMT_Encode4(0), GIMT_Encode4(0),
45538 /* 128012 */ /*GILLT_v4s16*//*Label 2473*/ GIMT_Encode4(128388),
45539 /* 128016 */ /*GILLT_v4s32*//*Label 2474*/ GIMT_Encode4(128426), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45540 /* 128032 */ /*GILLT_v8s16*//*Label 2475*/ GIMT_Encode4(128525),
45541 /* 128036 */ // Label 2469: @128036
45542 /* 128036 */ GIM_Try, /*On fail goto*//*Label 2477*/ GIMT_Encode4(128095), // Rule ID 2590 //
45543 /* 128041 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
45544 /* 128044 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45545 /* 128047 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45546 /* 128051 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45547 /* 128055 */ // (uint_to_fp:{ *:[f16] } GPR:{ *:[i32] }:$a) => (VUITOH:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
45548 /* 128055 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45549 /* 128058 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45550 /* 128062 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45551 /* 128067 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
45552 /* 128071 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45553 /* 128076 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOH),
45554 /* 128079 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
45555 /* 128081 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45556 /* 128084 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45557 /* 128087 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45558 /* 128093 */ GIR_RootConstrainSelectedInstOperands,
45559 /* 128094 */ // GIR_Coverage, 2590,
45560 /* 128094 */ GIR_EraseRootFromParent_Done,
45561 /* 128095 */ // Label 2477: @128095
45562 /* 128095 */ GIM_Reject,
45563 /* 128096 */ // Label 2470: @128096
45564 /* 128096 */ GIM_Try, /*On fail goto*//*Label 2478*/ GIMT_Encode4(128289),
45565 /* 128101 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45566 /* 128104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45567 /* 128108 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45568 /* 128112 */ GIM_Try, /*On fail goto*//*Label 2479*/ GIMT_Encode4(128160), // Rule ID 2586 //
45569 /* 128117 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
45570 /* 128120 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (VUITOS:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
45571 /* 128120 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45572 /* 128123 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45573 /* 128127 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45574 /* 128132 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
45575 /* 128136 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45576 /* 128141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOS),
45577 /* 128144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
45578 /* 128146 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45579 /* 128149 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45580 /* 128152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45581 /* 128158 */ GIR_RootConstrainSelectedInstOperands,
45582 /* 128159 */ // GIR_Coverage, 2586,
45583 /* 128159 */ GIR_EraseRootFromParent_Done,
45584 /* 128160 */ // Label 2479: @128160
45585 /* 128160 */ GIM_Try, /*On fail goto*//*Label 2480*/ GIMT_Encode4(128288), // Rule ID 3063 //
45586 /* 128165 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
45587 /* 128168 */ // (uint_to_fp:{ *:[f32] } GPR:{ *:[i32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (VCVTu2fd:{ *:[v2f32] } (INSERT_SUBREG:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), (COPY_TO_REGCLASS:{ *:[i32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }), ssub_0:{ *:[i32] })), ssub_0:{ *:[i32] })
45588 /* 128168 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32,
45589 /* 128171 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45590 /* 128175 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45591 /* 128180 */ GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // a
45592 /* 128184 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45593 /* 128189 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
45594 /* 128192 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45595 /* 128196 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45596 /* 128201 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/3,
45597 /* 128203 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v2s32,
45598 /* 128206 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45599 /* 128210 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45600 /* 128215 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
45601 /* 128218 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3,
45602 /* 128221 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/17,
45603 /* 128224 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45604 /* 128229 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45605 /* 128234 */ GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
45606 /* 128239 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
45607 /* 128242 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd),
45608 /* 128246 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45609 /* 128251 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45610 /* 128254 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
45611 /* 128257 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45612 /* 128263 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
45613 /* 128265 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45614 /* 128268 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45615 /* 128270 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
45616 /* 128277 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45617 /* 128282 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45618 /* 128287 */ // GIR_Coverage, 3063,
45619 /* 128287 */ GIR_EraseRootFromParent_Done,
45620 /* 128288 */ // Label 2480: @128288
45621 /* 128288 */ GIM_Reject,
45622 /* 128289 */ // Label 2478: @128289
45623 /* 128289 */ GIM_Reject,
45624 /* 128290 */ // Label 2471: @128290
45625 /* 128290 */ GIM_Try, /*On fail goto*//*Label 2481*/ GIMT_Encode4(128349), // Rule ID 2582 //
45626 /* 128295 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
45627 /* 128298 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45628 /* 128301 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45629 /* 128305 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
45630 /* 128309 */ // (uint_to_fp:{ *:[f64] } GPR:{ *:[i32] }:$a) => (VUITOD:{ *:[f64] } (COPY_TO_REGCLASS:{ *:[f32] } GPR:{ *:[i32] }:$a, SPR:{ *:[i32] }))
45631 /* 128309 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
45632 /* 128312 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45633 /* 128316 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45634 /* 128321 */ GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a
45635 /* 128325 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45636 /* 128330 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VUITOD),
45637 /* 128333 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
45638 /* 128335 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45639 /* 128338 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45640 /* 128341 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45641 /* 128347 */ GIR_RootConstrainSelectedInstOperands,
45642 /* 128348 */ // GIR_Coverage, 2582,
45643 /* 128348 */ GIR_EraseRootFromParent_Done,
45644 /* 128349 */ // Label 2481: @128349
45645 /* 128349 */ GIM_Reject,
45646 /* 128350 */ // Label 2472: @128350
45647 /* 128350 */ GIM_Try, /*On fail goto*//*Label 2482*/ GIMT_Encode4(128387), // Rule ID 1768 //
45648 /* 128355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45649 /* 128358 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45650 /* 128361 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45651 /* 128365 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45652 /* 128369 */ // (uint_to_fp:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm) => (VCVTu2fd:{ *:[v2f32] } DPR:{ *:[v2i32] }:$Vm)
45653 /* 128369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fd),
45654 /* 128372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45655 /* 128374 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45656 /* 128376 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45657 /* 128379 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45658 /* 128385 */ GIR_RootConstrainSelectedInstOperands,
45659 /* 128386 */ // GIR_Coverage, 1768,
45660 /* 128386 */ GIR_EraseRootFromParent_Done,
45661 /* 128387 */ // Label 2482: @128387
45662 /* 128387 */ GIM_Reject,
45663 /* 128388 */ // Label 2473: @128388
45664 /* 128388 */ GIM_Try, /*On fail goto*//*Label 2483*/ GIMT_Encode4(128425), // Rule ID 1776 //
45665 /* 128393 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45666 /* 128396 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45667 /* 128399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45668 /* 128403 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45669 /* 128407 */ // (uint_to_fp:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm) => (VCVTu2hd:{ *:[v4f16] } DPR:{ *:[v4i16] }:$Vm)
45670 /* 128407 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hd),
45671 /* 128410 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45672 /* 128412 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45673 /* 128414 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45674 /* 128417 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45675 /* 128423 */ GIR_RootConstrainSelectedInstOperands,
45676 /* 128424 */ // GIR_Coverage, 1776,
45677 /* 128424 */ GIR_EraseRootFromParent_Done,
45678 /* 128425 */ // Label 2483: @128425
45679 /* 128425 */ GIM_Reject,
45680 /* 128426 */ // Label 2474: @128426
45681 /* 128426 */ GIM_Try, /*On fail goto*//*Label 2484*/ GIMT_Encode4(128524),
45682 /* 128431 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45683 /* 128434 */ GIM_Try, /*On fail goto*//*Label 2485*/ GIMT_Encode4(128468), // Rule ID 1772 //
45684 /* 128439 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45685 /* 128442 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45686 /* 128446 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45687 /* 128450 */ // (uint_to_fp:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm) => (VCVTu2fq:{ *:[v4f32] } QPR:{ *:[v4i32] }:$Vm)
45688 /* 128450 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2fq),
45689 /* 128453 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45690 /* 128455 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45691 /* 128457 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45692 /* 128460 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45693 /* 128466 */ GIR_RootConstrainSelectedInstOperands,
45694 /* 128467 */ // GIR_Coverage, 1772,
45695 /* 128467 */ GIR_EraseRootFromParent_Done,
45696 /* 128468 */ // Label 2485: @128468
45697 /* 128468 */ GIM_Try, /*On fail goto*//*Label 2486*/ GIMT_Encode4(128523), // Rule ID 4505 //
45698 /* 128473 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45699 /* 128476 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45700 /* 128480 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45701 /* 128484 */ // (uint_to_fp:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VCVTf32u32n:{ *:[v4f32] } MQPR:{ *:[v4i32] }:$src)
45702 /* 128484 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45703 /* 128487 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45704 /* 128491 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45705 /* 128496 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf32u32n),
45706 /* 128499 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45707 /* 128501 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
45708 /* 128503 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45709 /* 128506 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45710 /* 128512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45711 /* 128518 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45712 /* 128521 */ GIR_RootConstrainSelectedInstOperands,
45713 /* 128522 */ // GIR_Coverage, 4505,
45714 /* 128522 */ GIR_EraseRootFromParent_Done,
45715 /* 128523 */ // Label 2486: @128523
45716 /* 128523 */ GIM_Reject,
45717 /* 128524 */ // Label 2484: @128524
45718 /* 128524 */ GIM_Reject,
45719 /* 128525 */ // Label 2475: @128525
45720 /* 128525 */ GIM_Try, /*On fail goto*//*Label 2487*/ GIMT_Encode4(128623),
45721 /* 128530 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45722 /* 128533 */ GIM_Try, /*On fail goto*//*Label 2488*/ GIMT_Encode4(128567), // Rule ID 1780 //
45723 /* 128538 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45724 /* 128541 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45725 /* 128545 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45726 /* 128549 */ // (uint_to_fp:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm) => (VCVTu2hq:{ *:[v8f16] } QPR:{ *:[v8i16] }:$Vm)
45727 /* 128549 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCVTu2hq),
45728 /* 128552 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45729 /* 128554 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45730 /* 128556 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45731 /* 128559 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45732 /* 128565 */ GIR_RootConstrainSelectedInstOperands,
45733 /* 128566 */ // GIR_Coverage, 1780,
45734 /* 128566 */ GIR_EraseRootFromParent_Done,
45735 /* 128567 */ // Label 2488: @128567
45736 /* 128567 */ GIM_Try, /*On fail goto*//*Label 2489*/ GIMT_Encode4(128622), // Rule ID 4499 //
45737 /* 128572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45738 /* 128575 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45739 /* 128579 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45740 /* 128583 */ // (uint_to_fp:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VCVTf16u16n:{ *:[v8f16] } MQPR:{ *:[v8i16] }:$src)
45741 /* 128583 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45742 /* 128586 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45743 /* 128590 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45744 /* 128595 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCVTf16u16n),
45745 /* 128598 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45746 /* 128600 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
45747 /* 128602 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45748 /* 128605 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45749 /* 128611 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45750 /* 128617 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45751 /* 128620 */ GIR_RootConstrainSelectedInstOperands,
45752 /* 128621 */ // GIR_Coverage, 4499,
45753 /* 128621 */ GIR_EraseRootFromParent_Done,
45754 /* 128622 */ // Label 2489: @128622
45755 /* 128622 */ GIM_Reject,
45756 /* 128623 */ // Label 2487: @128623
45757 /* 128623 */ GIM_Reject,
45758 /* 128624 */ // Label 2476: @128624
45759 /* 128624 */ GIM_Reject,
45760 /* 128625 */ // Label 52: @128625
45761 /* 128625 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2497*/ GIMT_Encode4(129400),
45762 /* 128636 */ /*GILLT_s16*//*Label 2490*/ GIMT_Encode4(128688),
45763 /* 128640 */ /*GILLT_s32*//*Label 2491*/ GIMT_Encode4(128726),
45764 /* 128644 */ /*GILLT_s64*//*Label 2492*/ GIMT_Encode4(128918), GIMT_Encode4(0),
45765 /* 128652 */ /*GILLT_v2s32*//*Label 2493*/ GIMT_Encode4(128956), GIMT_Encode4(0), GIMT_Encode4(0),
45766 /* 128664 */ /*GILLT_v4s16*//*Label 2494*/ GIMT_Encode4(128994),
45767 /* 128668 */ /*GILLT_v4s32*//*Label 2495*/ GIMT_Encode4(129032), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
45768 /* 128684 */ /*GILLT_v8s16*//*Label 2496*/ GIMT_Encode4(129216),
45769 /* 128688 */ // Label 2490: @128688
45770 /* 128688 */ GIM_Try, /*On fail goto*//*Label 2498*/ GIMT_Encode4(128725), // Rule ID 677 //
45771 /* 128693 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
45772 /* 128696 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
45773 /* 128699 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45774 /* 128703 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
45775 /* 128707 */ // (fabs:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VABSH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
45776 /* 128707 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSH),
45777 /* 128710 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
45778 /* 128712 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
45779 /* 128714 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45780 /* 128717 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45781 /* 128723 */ GIR_RootConstrainSelectedInstOperands,
45782 /* 128724 */ // GIR_Coverage, 677,
45783 /* 128724 */ GIR_EraseRootFromParent_Done,
45784 /* 128725 */ // Label 2498: @128725
45785 /* 128725 */ GIM_Reject,
45786 /* 128726 */ // Label 2491: @128726
45787 /* 128726 */ GIM_Try, /*On fail goto*//*Label 2499*/ GIMT_Encode4(128917),
45788 /* 128731 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
45789 /* 128734 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45790 /* 128738 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
45791 /* 128742 */ GIM_Try, /*On fail goto*//*Label 2500*/ GIMT_Encode4(128768), // Rule ID 676 //
45792 /* 128747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
45793 /* 128750 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VABSS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
45794 /* 128750 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSS),
45795 /* 128753 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
45796 /* 128755 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
45797 /* 128757 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45798 /* 128760 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45799 /* 128766 */ GIR_RootConstrainSelectedInstOperands,
45800 /* 128767 */ // GIR_Coverage, 676,
45801 /* 128767 */ GIR_EraseRootFromParent_Done,
45802 /* 128768 */ // Label 2500: @128768
45803 /* 128768 */ GIM_Try, /*On fail goto*//*Label 2501*/ GIMT_Encode4(128916), // Rule ID 3054 //
45804 /* 128773 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_UseNEONForFP),
45805 /* 128776 */ // (fabs:{ *:[f32] } SPR:{ *:[f32] }:$a) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VABSfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
45806 /* 128776 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
45807 /* 128779 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45808 /* 128783 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45809 /* 128788 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
45810 /* 128790 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
45811 /* 128793 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45812 /* 128797 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45813 /* 128802 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
45814 /* 128805 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45815 /* 128810 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
45816 /* 128813 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
45817 /* 128817 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45818 /* 128822 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
45819 /* 128825 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
45820 /* 128829 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
45821 /* 128832 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45822 /* 128837 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45823 /* 128842 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
45824 /* 128847 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
45825 /* 128850 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VABSfd),
45826 /* 128854 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45827 /* 128859 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
45828 /* 128862 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
45829 /* 128865 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45830 /* 128871 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
45831 /* 128873 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
45832 /* 128876 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45833 /* 128880 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45834 /* 128885 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
45835 /* 128888 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45836 /* 128893 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
45837 /* 128896 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
45838 /* 128898 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
45839 /* 128905 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
45840 /* 128910 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
45841 /* 128915 */ // GIR_Coverage, 3054,
45842 /* 128915 */ GIR_EraseRootFromParent_Done,
45843 /* 128916 */ // Label 2501: @128916
45844 /* 128916 */ GIM_Reject,
45845 /* 128917 */ // Label 2499: @128917
45846 /* 128917 */ GIM_Reject,
45847 /* 128918 */ // Label 2492: @128918
45848 /* 128918 */ GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(128955), // Rule ID 675 //
45849 /* 128923 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
45850 /* 128926 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
45851 /* 128929 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45852 /* 128933 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45853 /* 128937 */ // (fabs:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VABSD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
45854 /* 128937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSD),
45855 /* 128940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
45856 /* 128942 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
45857 /* 128944 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45858 /* 128947 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45859 /* 128953 */ GIR_RootConstrainSelectedInstOperands,
45860 /* 128954 */ // GIR_Coverage, 675,
45861 /* 128954 */ GIR_EraseRootFromParent_Done,
45862 /* 128955 */ // Label 2502: @128955
45863 /* 128955 */ GIM_Reject,
45864 /* 128956 */ // Label 2493: @128956
45865 /* 128956 */ GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(128993), // Rule ID 1675 //
45866 /* 128961 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45867 /* 128964 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
45868 /* 128967 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45869 /* 128971 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45870 /* 128975 */ // (fabs:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VABSfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
45871 /* 128975 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfd),
45872 /* 128978 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45873 /* 128980 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45874 /* 128982 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45875 /* 128985 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45876 /* 128991 */ GIR_RootConstrainSelectedInstOperands,
45877 /* 128992 */ // GIR_Coverage, 1675,
45878 /* 128992 */ GIR_EraseRootFromParent_Done,
45879 /* 128993 */ // Label 2503: @128993
45880 /* 128993 */ GIM_Reject,
45881 /* 128994 */ // Label 2494: @128994
45882 /* 128994 */ GIM_Try, /*On fail goto*//*Label 2504*/ GIMT_Encode4(129031), // Rule ID 1677 //
45883 /* 128999 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45884 /* 129002 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
45885 /* 129005 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45886 /* 129009 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
45887 /* 129013 */ // (fabs:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VABShd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
45888 /* 129013 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShd),
45889 /* 129016 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45890 /* 129018 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45891 /* 129020 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45892 /* 129023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45893 /* 129029 */ GIR_RootConstrainSelectedInstOperands,
45894 /* 129030 */ // GIR_Coverage, 1677,
45895 /* 129030 */ GIR_EraseRootFromParent_Done,
45896 /* 129031 */ // Label 2504: @129031
45897 /* 129031 */ GIM_Reject,
45898 /* 129032 */ // Label 2495: @129032
45899 /* 129032 */ GIM_Try, /*On fail goto*//*Label 2505*/ GIMT_Encode4(129215),
45900 /* 129037 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
45901 /* 129040 */ GIM_Try, /*On fail goto*//*Label 2506*/ GIMT_Encode4(129125), // Rule ID 4435 //
45902 /* 129045 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45903 /* 129048 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45904 /* 129052 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45905 /* 129056 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
45906 /* 129060 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
45907 /* 129064 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
45908 /* 129068 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45909 /* 129073 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45910 /* 129078 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45911 /* 129080 */ // (fabs:{ *:[v4f32] } (fsub:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)) => (MVE_VABDf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
45912 /* 129080 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45913 /* 129083 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45914 /* 129087 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45915 /* 129092 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf32),
45916 /* 129095 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45917 /* 129097 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45918 /* 129101 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn
45919 /* 129105 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45920 /* 129108 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45921 /* 129114 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45922 /* 129120 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45923 /* 129123 */ GIR_RootConstrainSelectedInstOperands,
45924 /* 129124 */ // GIR_Coverage, 4435,
45925 /* 129124 */ GIR_EraseRootFromParent_Done,
45926 /* 129125 */ // Label 2506: @129125
45927 /* 129125 */ GIM_Try, /*On fail goto*//*Label 2507*/ GIMT_Encode4(129159), // Rule ID 1676 //
45928 /* 129130 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
45929 /* 129133 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45930 /* 129137 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45931 /* 129141 */ // (fabs:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VABSfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
45932 /* 129141 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSfq),
45933 /* 129144 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45934 /* 129146 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
45935 /* 129148 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
45936 /* 129151 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45937 /* 129157 */ GIR_RootConstrainSelectedInstOperands,
45938 /* 129158 */ // GIR_Coverage, 1676,
45939 /* 129158 */ GIR_EraseRootFromParent_Done,
45940 /* 129159 */ // Label 2507: @129159
45941 /* 129159 */ GIM_Try, /*On fail goto*//*Label 2508*/ GIMT_Encode4(129214), // Rule ID 4514 //
45942 /* 129164 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
45943 /* 129167 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45944 /* 129171 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45945 /* 129175 */ // (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$v) => (MVE_VABSf32:{ *:[v4f32] } ?:{ *:[v4f32] }:$v)
45946 /* 129175 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45947 /* 129178 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45948 /* 129182 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45949 /* 129187 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf32),
45950 /* 129190 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45951 /* 129192 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
45952 /* 129194 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45953 /* 129197 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45954 /* 129203 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45955 /* 129209 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45956 /* 129212 */ GIR_RootConstrainSelectedInstOperands,
45957 /* 129213 */ // GIR_Coverage, 4514,
45958 /* 129213 */ GIR_EraseRootFromParent_Done,
45959 /* 129214 */ // Label 2508: @129214
45960 /* 129214 */ GIM_Reject,
45961 /* 129215 */ // Label 2505: @129215
45962 /* 129215 */ GIM_Reject,
45963 /* 129216 */ // Label 2496: @129216
45964 /* 129216 */ GIM_Try, /*On fail goto*//*Label 2509*/ GIMT_Encode4(129399),
45965 /* 129221 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
45966 /* 129224 */ GIM_Try, /*On fail goto*//*Label 2510*/ GIMT_Encode4(129309), // Rule ID 4434 //
45967 /* 129229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
45968 /* 129232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45969 /* 129236 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
45970 /* 129240 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FSUB),
45971 /* 129244 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
45972 /* 129248 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
45973 /* 129252 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45974 /* 129257 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
45975 /* 129262 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
45976 /* 129264 */ // (fabs:{ *:[v8f16] } (fsub:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)) => (MVE_VABDf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
45977 /* 129264 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
45978 /* 129267 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
45979 /* 129271 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
45980 /* 129276 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABDf16),
45981 /* 129279 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
45982 /* 129281 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
45983 /* 129285 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // Qn
45984 /* 129289 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
45985 /* 129292 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45986 /* 129298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
45987 /* 129304 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
45988 /* 129307 */ GIR_RootConstrainSelectedInstOperands,
45989 /* 129308 */ // GIR_Coverage, 4434,
45990 /* 129308 */ GIR_EraseRootFromParent_Done,
45991 /* 129309 */ // Label 2510: @129309
45992 /* 129309 */ GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(129343), // Rule ID 1678 //
45993 /* 129314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
45994 /* 129317 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45995 /* 129321 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
45996 /* 129325 */ // (fabs:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VABShq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
45997 /* 129325 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABShq),
45998 /* 129328 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
45999 /* 129330 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
46000 /* 129332 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46001 /* 129335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46002 /* 129341 */ GIR_RootConstrainSelectedInstOperands,
46003 /* 129342 */ // GIR_Coverage, 1678,
46004 /* 129342 */ GIR_EraseRootFromParent_Done,
46005 /* 129343 */ // Label 2511: @129343
46006 /* 129343 */ GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(129398), // Rule ID 4512 //
46007 /* 129348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46008 /* 129351 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46009 /* 129355 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46010 /* 129359 */ // (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$v) => (MVE_VABSf16:{ *:[v8f16] } ?:{ *:[v8f16] }:$v)
46011 /* 129359 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46012 /* 129362 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46013 /* 129366 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46014 /* 129371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSf16),
46015 /* 129374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46016 /* 129376 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
46017 /* 129378 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46018 /* 129381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46019 /* 129387 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46020 /* 129393 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46021 /* 129396 */ GIR_RootConstrainSelectedInstOperands,
46022 /* 129397 */ // GIR_Coverage, 4512,
46023 /* 129397 */ GIR_EraseRootFromParent_Done,
46024 /* 129398 */ // Label 2512: @129398
46025 /* 129398 */ GIM_Reject,
46026 /* 129399 */ // Label 2509: @129399
46027 /* 129399 */ GIM_Reject,
46028 /* 129400 */ // Label 2497: @129400
46029 /* 129400 */ GIM_Reject,
46030 /* 129401 */ // Label 53: @129401
46031 /* 129401 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2520*/ GIMT_Encode4(129992),
46032 /* 129412 */ /*GILLT_s16*//*Label 2513*/ GIMT_Encode4(129464),
46033 /* 129416 */ /*GILLT_s32*//*Label 2514*/ GIMT_Encode4(129498),
46034 /* 129420 */ /*GILLT_s64*//*Label 2515*/ GIMT_Encode4(129532), GIMT_Encode4(0),
46035 /* 129428 */ /*GILLT_v2s32*//*Label 2516*/ GIMT_Encode4(129566), GIMT_Encode4(0), GIMT_Encode4(0),
46036 /* 129440 */ /*GILLT_v4s16*//*Label 2517*/ GIMT_Encode4(129600),
46037 /* 129444 */ /*GILLT_v4s32*//*Label 2518*/ GIMT_Encode4(129634), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
46038 /* 129460 */ /*GILLT_v8s16*//*Label 2519*/ GIMT_Encode4(129813),
46039 /* 129464 */ // Label 2513: @129464
46040 /* 129464 */ GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(129497), // Rule ID 664 //
46041 /* 129469 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
46042 /* 129472 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46043 /* 129475 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46044 /* 129478 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46045 /* 129482 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46046 /* 129486 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46047 /* 129490 */ // (fminnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMINNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46048 /* 129490 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMH),
46049 /* 129495 */ GIR_RootConstrainSelectedInstOperands,
46050 /* 129496 */ // GIR_Coverage, 664,
46051 /* 129496 */ GIR_Done,
46052 /* 129497 */ // Label 2521: @129497
46053 /* 129497 */ GIM_Reject,
46054 /* 129498 */ // Label 2514: @129498
46055 /* 129498 */ GIM_Try, /*On fail goto*//*Label 2522*/ GIMT_Encode4(129531), // Rule ID 666 //
46056 /* 129503 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
46057 /* 129506 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46058 /* 129509 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46059 /* 129512 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46060 /* 129516 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46061 /* 129520 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46062 /* 129524 */ // (fminnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMINNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46063 /* 129524 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMS),
46064 /* 129529 */ GIR_RootConstrainSelectedInstOperands,
46065 /* 129530 */ // GIR_Coverage, 666,
46066 /* 129530 */ GIR_Done,
46067 /* 129531 */ // Label 2522: @129531
46068 /* 129531 */ GIM_Reject,
46069 /* 129532 */ // Label 2515: @129532
46070 /* 129532 */ GIM_Try, /*On fail goto*//*Label 2523*/ GIMT_Encode4(129565), // Rule ID 668 //
46071 /* 129537 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
46072 /* 129540 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46073 /* 129543 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
46074 /* 129546 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46075 /* 129550 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46076 /* 129554 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46077 /* 129558 */ // (fminnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMINNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46078 /* 129558 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMINNMD),
46079 /* 129563 */ GIR_RootConstrainSelectedInstOperands,
46080 /* 129564 */ // GIR_Coverage, 668,
46081 /* 129564 */ GIR_Done,
46082 /* 129565 */ // Label 2523: @129565
46083 /* 129565 */ GIM_Reject,
46084 /* 129566 */ // Label 2516: @129566
46085 /* 129566 */ GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(129599), // Rule ID 1394 //
46086 /* 129571 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON),
46087 /* 129574 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
46088 /* 129577 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
46089 /* 129580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46090 /* 129584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46091 /* 129588 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46092 /* 129592 */ // (fminnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMINNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
46093 /* 129592 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDf),
46094 /* 129597 */ GIR_RootConstrainSelectedInstOperands,
46095 /* 129598 */ // GIR_Coverage, 1394,
46096 /* 129598 */ GIR_Done,
46097 /* 129599 */ // Label 2524: @129599
46098 /* 129599 */ GIM_Reject,
46099 /* 129600 */ // Label 2517: @129600
46100 /* 129600 */ GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(129633), // Rule ID 1396 //
46101 /* 129605 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON),
46102 /* 129608 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
46103 /* 129611 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
46104 /* 129614 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46105 /* 129618 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46106 /* 129622 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46107 /* 129626 */ // (fminnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMINNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
46108 /* 129626 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNDh),
46109 /* 129631 */ GIR_RootConstrainSelectedInstOperands,
46110 /* 129632 */ // GIR_Coverage, 1396,
46111 /* 129632 */ GIR_Done,
46112 /* 129633 */ // Label 2525: @129633
46113 /* 129633 */ GIM_Reject,
46114 /* 129634 */ // Label 2518: @129634
46115 /* 129634 */ GIM_Try, /*On fail goto*//*Label 2526*/ GIMT_Encode4(129812),
46116 /* 129639 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
46117 /* 129642 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
46118 /* 129645 */ GIM_Try, /*On fail goto*//*Label 2527*/ GIMT_Encode4(129723), // Rule ID 4526 //
46119 /* 129650 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46120 /* 129653 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46121 /* 129657 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46122 /* 129661 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
46123 /* 129665 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
46124 /* 129669 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46125 /* 129674 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
46126 /* 129678 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
46127 /* 129682 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
46128 /* 129686 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46129 /* 129691 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46130 /* 129693 */ // (fminnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMINNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
46131 /* 129693 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf32),
46132 /* 129696 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46133 /* 129698 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
46134 /* 129702 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
46135 /* 129706 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46136 /* 129709 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46137 /* 129715 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46138 /* 129721 */ GIR_RootConstrainSelectedInstOperands,
46139 /* 129722 */ // GIR_Coverage, 4526,
46140 /* 129722 */ GIR_EraseRootFromParent_Done,
46141 /* 129723 */ // Label 2527: @129723
46142 /* 129723 */ GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(129750), // Rule ID 1395 //
46143 /* 129728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON),
46144 /* 129731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46145 /* 129735 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46146 /* 129739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46147 /* 129743 */ // (fminnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMINNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
46148 /* 129743 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQf),
46149 /* 129748 */ GIR_RootConstrainSelectedInstOperands,
46150 /* 129749 */ // GIR_Coverage, 1395,
46151 /* 129749 */ GIR_Done,
46152 /* 129750 */ // Label 2528: @129750
46153 /* 129750 */ GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(129811), // Rule ID 3642 //
46154 /* 129755 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
46155 /* 129758 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46156 /* 129762 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46157 /* 129766 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46158 /* 129770 */ // (fminnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMINNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
46159 /* 129770 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46160 /* 129773 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46161 /* 129777 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46162 /* 129782 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf32),
46163 /* 129785 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46164 /* 129787 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
46165 /* 129789 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
46166 /* 129791 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46167 /* 129794 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46168 /* 129800 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46169 /* 129806 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46170 /* 129809 */ GIR_RootConstrainSelectedInstOperands,
46171 /* 129810 */ // GIR_Coverage, 3642,
46172 /* 129810 */ GIR_EraseRootFromParent_Done,
46173 /* 129811 */ // Label 2529: @129811
46174 /* 129811 */ GIM_Reject,
46175 /* 129812 */ // Label 2526: @129812
46176 /* 129812 */ GIM_Reject,
46177 /* 129813 */ // Label 2519: @129813
46178 /* 129813 */ GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(129991),
46179 /* 129818 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
46180 /* 129821 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
46181 /* 129824 */ GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(129902), // Rule ID 4529 //
46182 /* 129829 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46183 /* 129832 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46184 /* 129836 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46185 /* 129840 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
46186 /* 129844 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
46187 /* 129848 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46188 /* 129853 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
46189 /* 129857 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
46190 /* 129861 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
46191 /* 129865 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46192 /* 129870 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46193 /* 129872 */ // (fminnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMINNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
46194 /* 129872 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMAf16),
46195 /* 129875 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46196 /* 129877 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
46197 /* 129881 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
46198 /* 129885 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46199 /* 129888 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46200 /* 129894 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46201 /* 129900 */ GIR_RootConstrainSelectedInstOperands,
46202 /* 129901 */ // GIR_Coverage, 4529,
46203 /* 129901 */ GIR_EraseRootFromParent_Done,
46204 /* 129902 */ // Label 2531: @129902
46205 /* 129902 */ GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(129929), // Rule ID 1397 //
46206 /* 129907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON),
46207 /* 129910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46208 /* 129914 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46209 /* 129918 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46210 /* 129922 */ // (fminnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMINNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
46211 /* 129922 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMINNMNQh),
46212 /* 129927 */ GIR_RootConstrainSelectedInstOperands,
46213 /* 129928 */ // GIR_Coverage, 1397,
46214 /* 129928 */ GIR_Done,
46215 /* 129929 */ // Label 2532: @129929
46216 /* 129929 */ GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(129990), // Rule ID 3647 //
46217 /* 129934 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
46218 /* 129937 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46219 /* 129941 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46220 /* 129945 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46221 /* 129949 */ // (fminnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMINNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
46222 /* 129949 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46223 /* 129952 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46224 /* 129956 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46225 /* 129961 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINNMf16),
46226 /* 129964 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46227 /* 129966 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
46228 /* 129968 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
46229 /* 129970 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46230 /* 129973 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46231 /* 129979 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46232 /* 129985 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46233 /* 129988 */ GIR_RootConstrainSelectedInstOperands,
46234 /* 129989 */ // GIR_Coverage, 3647,
46235 /* 129989 */ GIR_EraseRootFromParent_Done,
46236 /* 129990 */ // Label 2533: @129990
46237 /* 129990 */ GIM_Reject,
46238 /* 129991 */ // Label 2530: @129991
46239 /* 129991 */ GIM_Reject,
46240 /* 129992 */ // Label 2520: @129992
46241 /* 129992 */ GIM_Reject,
46242 /* 129993 */ // Label 54: @129993
46243 /* 129993 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2541*/ GIMT_Encode4(130584),
46244 /* 130004 */ /*GILLT_s16*//*Label 2534*/ GIMT_Encode4(130056),
46245 /* 130008 */ /*GILLT_s32*//*Label 2535*/ GIMT_Encode4(130090),
46246 /* 130012 */ /*GILLT_s64*//*Label 2536*/ GIMT_Encode4(130124), GIMT_Encode4(0),
46247 /* 130020 */ /*GILLT_v2s32*//*Label 2537*/ GIMT_Encode4(130158), GIMT_Encode4(0), GIMT_Encode4(0),
46248 /* 130032 */ /*GILLT_v4s16*//*Label 2538*/ GIMT_Encode4(130192),
46249 /* 130036 */ /*GILLT_v4s32*//*Label 2539*/ GIMT_Encode4(130226), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
46250 /* 130052 */ /*GILLT_v8s16*//*Label 2540*/ GIMT_Encode4(130405),
46251 /* 130056 */ // Label 2534: @130056
46252 /* 130056 */ GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(130089), // Rule ID 658 //
46253 /* 130061 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
46254 /* 130064 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46255 /* 130067 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46256 /* 130070 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46257 /* 130074 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46258 /* 130078 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46259 /* 130082 */ // (fmaxnum:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VFP_VMAXNMH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
46260 /* 130082 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMH),
46261 /* 130087 */ GIR_RootConstrainSelectedInstOperands,
46262 /* 130088 */ // GIR_Coverage, 658,
46263 /* 130088 */ GIR_Done,
46264 /* 130089 */ // Label 2542: @130089
46265 /* 130089 */ GIM_Reject,
46266 /* 130090 */ // Label 2535: @130090
46267 /* 130090 */ GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(130123), // Rule ID 660 //
46268 /* 130095 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
46269 /* 130098 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46270 /* 130101 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46271 /* 130104 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46272 /* 130108 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46273 /* 130112 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46274 /* 130116 */ // (fmaxnum:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VFP_VMAXNMS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
46275 /* 130116 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMS),
46276 /* 130121 */ GIR_RootConstrainSelectedInstOperands,
46277 /* 130122 */ // GIR_Coverage, 660,
46278 /* 130122 */ GIR_Done,
46279 /* 130123 */ // Label 2543: @130123
46280 /* 130123 */ GIM_Reject,
46281 /* 130124 */ // Label 2536: @130124
46282 /* 130124 */ GIM_Try, /*On fail goto*//*Label 2544*/ GIMT_Encode4(130157), // Rule ID 662 //
46283 /* 130129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
46284 /* 130132 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
46285 /* 130135 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
46286 /* 130138 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46287 /* 130142 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46288 /* 130146 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46289 /* 130150 */ // (fmaxnum:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VFP_VMAXNMD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
46290 /* 130150 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VFP_VMAXNMD),
46291 /* 130155 */ GIR_RootConstrainSelectedInstOperands,
46292 /* 130156 */ // GIR_Coverage, 662,
46293 /* 130156 */ GIR_Done,
46294 /* 130157 */ // Label 2544: @130157
46295 /* 130157 */ GIM_Reject,
46296 /* 130158 */ // Label 2537: @130158
46297 /* 130158 */ GIM_Try, /*On fail goto*//*Label 2545*/ GIMT_Encode4(130191), // Rule ID 1374 //
46298 /* 130163 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON),
46299 /* 130166 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
46300 /* 130169 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
46301 /* 130172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46302 /* 130176 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46303 /* 130180 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46304 /* 130184 */ // (fmaxnum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (NEON_VMAXNMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
46305 /* 130184 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDf),
46306 /* 130189 */ GIR_RootConstrainSelectedInstOperands,
46307 /* 130190 */ // GIR_Coverage, 1374,
46308 /* 130190 */ GIR_Done,
46309 /* 130191 */ // Label 2545: @130191
46310 /* 130191 */ GIM_Reject,
46311 /* 130192 */ // Label 2538: @130192
46312 /* 130192 */ GIM_Try, /*On fail goto*//*Label 2546*/ GIMT_Encode4(130225), // Rule ID 1376 //
46313 /* 130197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON),
46314 /* 130200 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
46315 /* 130203 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
46316 /* 130206 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46317 /* 130210 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46318 /* 130214 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46319 /* 130218 */ // (fmaxnum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (NEON_VMAXNMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
46320 /* 130218 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNDh),
46321 /* 130223 */ GIR_RootConstrainSelectedInstOperands,
46322 /* 130224 */ // GIR_Coverage, 1376,
46323 /* 130224 */ GIR_Done,
46324 /* 130225 */ // Label 2546: @130225
46325 /* 130225 */ GIM_Reject,
46326 /* 130226 */ // Label 2539: @130226
46327 /* 130226 */ GIM_Try, /*On fail goto*//*Label 2547*/ GIMT_Encode4(130404),
46328 /* 130231 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
46329 /* 130234 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
46330 /* 130237 */ GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(130315), // Rule ID 4520 //
46331 /* 130242 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46332 /* 130245 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46333 /* 130249 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46334 /* 130253 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
46335 /* 130257 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
46336 /* 130261 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46337 /* 130266 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
46338 /* 130270 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
46339 /* 130274 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v4s32,
46340 /* 130278 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46341 /* 130283 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46342 /* 130285 */ // (fmaxnum:{ *:[v4f32] } (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd), (fabs:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm)) => (MVE_VMAXNMAf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qd, MQPR:{ *:[v4f32] }:$Qm)
46343 /* 130285 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf32),
46344 /* 130288 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46345 /* 130290 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
46346 /* 130294 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
46347 /* 130298 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46348 /* 130301 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46349 /* 130307 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46350 /* 130313 */ GIR_RootConstrainSelectedInstOperands,
46351 /* 130314 */ // GIR_Coverage, 4520,
46352 /* 130314 */ GIR_EraseRootFromParent_Done,
46353 /* 130315 */ // Label 2548: @130315
46354 /* 130315 */ GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(130342), // Rule ID 1375 //
46355 /* 130320 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasNEON),
46356 /* 130323 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46357 /* 130327 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46358 /* 130331 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46359 /* 130335 */ // (fmaxnum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (NEON_VMAXNMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
46360 /* 130335 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQf),
46361 /* 130340 */ GIR_RootConstrainSelectedInstOperands,
46362 /* 130341 */ // GIR_Coverage, 1375,
46363 /* 130341 */ GIR_Done,
46364 /* 130342 */ // Label 2549: @130342
46365 /* 130342 */ GIM_Try, /*On fail goto*//*Label 2550*/ GIMT_Encode4(130403), // Rule ID 3380 //
46366 /* 130347 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
46367 /* 130350 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46368 /* 130354 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46369 /* 130358 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46370 /* 130362 */ // (fmaxnum:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn) => (MVE_VMAXNMf32:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$Qm, MQPR:{ *:[v4f32] }:$Qn)
46371 /* 130362 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46372 /* 130365 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46373 /* 130369 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46374 /* 130374 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf32),
46375 /* 130377 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46376 /* 130379 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
46377 /* 130381 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
46378 /* 130383 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46379 /* 130386 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46380 /* 130392 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46381 /* 130398 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46382 /* 130401 */ GIR_RootConstrainSelectedInstOperands,
46383 /* 130402 */ // GIR_Coverage, 3380,
46384 /* 130402 */ GIR_EraseRootFromParent_Done,
46385 /* 130403 */ // Label 2550: @130403
46386 /* 130403 */ GIM_Reject,
46387 /* 130404 */ // Label 2547: @130404
46388 /* 130404 */ GIM_Reject,
46389 /* 130405 */ // Label 2540: @130405
46390 /* 130405 */ GIM_Try, /*On fail goto*//*Label 2551*/ GIMT_Encode4(130583),
46391 /* 130410 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
46392 /* 130413 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
46393 /* 130416 */ GIM_Try, /*On fail goto*//*Label 2552*/ GIMT_Encode4(130494), // Rule ID 4523 //
46394 /* 130421 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
46395 /* 130424 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46396 /* 130428 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
46397 /* 130432 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS),
46398 /* 130436 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
46399 /* 130440 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46400 /* 130445 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2]
46401 /* 130449 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS),
46402 /* 130453 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_v8s16,
46403 /* 130457 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46404 /* 130462 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
46405 /* 130464 */ // (fmaxnum:{ *:[v8f16] } (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd), (fabs:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm)) => (MVE_VMAXNMAf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qd, MQPR:{ *:[v8f16] }:$Qm)
46406 /* 130464 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMAf16),
46407 /* 130467 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46408 /* 130469 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qd
46409 /* 130473 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Qm
46410 /* 130477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46411 /* 130480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46412 /* 130486 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46413 /* 130492 */ GIR_RootConstrainSelectedInstOperands,
46414 /* 130493 */ // GIR_Coverage, 4523,
46415 /* 130493 */ GIR_EraseRootFromParent_Done,
46416 /* 130494 */ // Label 2552: @130494
46417 /* 130494 */ GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(130521), // Rule ID 1377 //
46418 /* 130499 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8_HasFullFP16_HasNEON),
46419 /* 130502 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46420 /* 130506 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46421 /* 130510 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46422 /* 130514 */ // (fmaxnum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (NEON_VMAXNMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
46423 /* 130514 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::NEON_VMAXNMNQh),
46424 /* 130519 */ GIR_RootConstrainSelectedInstOperands,
46425 /* 130520 */ // GIR_Coverage, 1377,
46426 /* 130520 */ GIR_Done,
46427 /* 130521 */ // Label 2553: @130521
46428 /* 130521 */ GIM_Try, /*On fail goto*//*Label 2554*/ GIMT_Encode4(130582), // Rule ID 3637 //
46429 /* 130526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
46430 /* 130529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46431 /* 130533 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46432 /* 130537 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
46433 /* 130541 */ // (fmaxnum:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn) => (MVE_VMAXNMf16:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$Qm, MQPR:{ *:[v8f16] }:$Qn)
46434 /* 130541 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
46435 /* 130544 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46436 /* 130548 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46437 /* 130553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXNMf16),
46438 /* 130556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
46439 /* 130558 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
46440 /* 130560 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
46441 /* 130562 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
46442 /* 130565 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46443 /* 130571 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46444 /* 130577 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46445 /* 130580 */ GIR_RootConstrainSelectedInstOperands,
46446 /* 130581 */ // GIR_Coverage, 3637,
46447 /* 130581 */ GIR_EraseRootFromParent_Done,
46448 /* 130582 */ // Label 2554: @130582
46449 /* 130582 */ GIM_Reject,
46450 /* 130583 */ // Label 2551: @130583
46451 /* 130583 */ GIM_Reject,
46452 /* 130584 */ // Label 2541: @130584
46453 /* 130584 */ GIM_Reject,
46454 /* 130585 */ // Label 55: @130585
46455 /* 130585 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2561*/ GIMT_Encode4(131318),
46456 /* 130596 */ /*GILLT_s16*//*Label 2555*/ GIMT_Encode4(130648),
46457 /* 130600 */ /*GILLT_s32*//*Label 2556*/ GIMT_Encode4(130889), GIMT_Encode4(0), GIMT_Encode4(0),
46458 /* 130612 */ /*GILLT_v2s32*//*Label 2557*/ GIMT_Encode4(131130), GIMT_Encode4(0), GIMT_Encode4(0),
46459 /* 130624 */ /*GILLT_v4s16*//*Label 2558*/ GIMT_Encode4(131177),
46460 /* 130628 */ /*GILLT_v4s32*//*Label 2559*/ GIMT_Encode4(131224), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
46461 /* 130644 */ /*GILLT_v8s16*//*Label 2560*/ GIMT_Encode4(131271),
46462 /* 130648 */ // Label 2555: @130648
46463 /* 130648 */ GIM_Try, /*On fail goto*//*Label 2562*/ GIMT_Encode4(130888), // Rule ID 3057 //
46464 /* 130653 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
46465 /* 130656 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46466 /* 130659 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46467 /* 130662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46468 /* 130666 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46469 /* 130670 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46470 /* 130674 */ // (fminimum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMINhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
46471 /* 130674 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
46472 /* 130677 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46473 /* 130681 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46474 /* 130686 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
46475 /* 130688 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
46476 /* 130691 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46477 /* 130695 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46478 /* 130700 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
46479 /* 130703 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46480 /* 130708 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
46481 /* 130711 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46482 /* 130715 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46483 /* 130720 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
46484 /* 130723 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
46485 /* 130727 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
46486 /* 130730 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46487 /* 130735 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46488 /* 130740 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
46489 /* 130745 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
46490 /* 130748 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46491 /* 130752 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46492 /* 130757 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
46493 /* 130759 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
46494 /* 130762 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46495 /* 130766 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46496 /* 130771 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
46497 /* 130774 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46498 /* 130779 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
46499 /* 130782 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46500 /* 130786 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46501 /* 130791 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
46502 /* 130794 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
46503 /* 130798 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
46504 /* 130801 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46505 /* 130806 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46506 /* 130811 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
46507 /* 130816 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
46508 /* 130819 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINhd),
46509 /* 130823 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46510 /* 130828 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
46511 /* 130831 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
46512 /* 130834 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
46513 /* 130837 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46514 /* 130843 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46515 /* 130845 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
46516 /* 130848 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46517 /* 130852 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46518 /* 130857 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
46519 /* 130860 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46520 /* 130865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46521 /* 130868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46522 /* 130870 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
46523 /* 130877 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
46524 /* 130882 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46525 /* 130887 */ // GIR_Coverage, 3057,
46526 /* 130887 */ GIR_EraseRootFromParent_Done,
46527 /* 130888 */ // Label 2562: @130888
46528 /* 130888 */ GIM_Reject,
46529 /* 130889 */ // Label 2556: @130889
46530 /* 130889 */ GIM_Try, /*On fail goto*//*Label 2563*/ GIMT_Encode4(131129), // Rule ID 3059 //
46531 /* 130894 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46532 /* 130897 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46533 /* 130900 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46534 /* 130903 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46535 /* 130907 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46536 /* 130911 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46537 /* 130915 */ // (fminimum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMINfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
46538 /* 130915 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
46539 /* 130918 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46540 /* 130922 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46541 /* 130927 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
46542 /* 130929 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
46543 /* 130932 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46544 /* 130936 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46545 /* 130941 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
46546 /* 130944 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46547 /* 130949 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
46548 /* 130952 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46549 /* 130956 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46550 /* 130961 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
46551 /* 130964 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
46552 /* 130968 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
46553 /* 130971 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46554 /* 130976 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46555 /* 130981 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
46556 /* 130986 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
46557 /* 130989 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46558 /* 130993 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46559 /* 130998 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
46560 /* 131000 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
46561 /* 131003 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46562 /* 131007 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46563 /* 131012 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
46564 /* 131015 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46565 /* 131020 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
46566 /* 131023 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46567 /* 131027 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46568 /* 131032 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
46569 /* 131035 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
46570 /* 131039 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
46571 /* 131042 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46572 /* 131047 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46573 /* 131052 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
46574 /* 131057 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
46575 /* 131060 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMINfd),
46576 /* 131064 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46577 /* 131069 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
46578 /* 131072 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
46579 /* 131075 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
46580 /* 131078 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46581 /* 131084 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46582 /* 131086 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
46583 /* 131089 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46584 /* 131093 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46585 /* 131098 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
46586 /* 131101 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46587 /* 131106 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46588 /* 131109 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46589 /* 131111 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
46590 /* 131118 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
46591 /* 131123 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46592 /* 131128 */ // GIR_Coverage, 3059,
46593 /* 131128 */ GIR_EraseRootFromParent_Done,
46594 /* 131129 */ // Label 2563: @131129
46595 /* 131129 */ GIM_Reject,
46596 /* 131130 */ // Label 2557: @131130
46597 /* 131130 */ GIM_Try, /*On fail goto*//*Label 2564*/ GIMT_Encode4(131176), // Rule ID 1390 //
46598 /* 131135 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46599 /* 131138 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
46600 /* 131141 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
46601 /* 131144 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46602 /* 131148 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46603 /* 131152 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46604 /* 131156 */ // (fminimum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMINfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
46605 /* 131156 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfd),
46606 /* 131159 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46607 /* 131161 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46608 /* 131163 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46609 /* 131165 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46610 /* 131168 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46611 /* 131174 */ GIR_RootConstrainSelectedInstOperands,
46612 /* 131175 */ // GIR_Coverage, 1390,
46613 /* 131175 */ GIR_EraseRootFromParent_Done,
46614 /* 131176 */ // Label 2564: @131176
46615 /* 131176 */ GIM_Reject,
46616 /* 131177 */ // Label 2558: @131177
46617 /* 131177 */ GIM_Try, /*On fail goto*//*Label 2565*/ GIMT_Encode4(131223), // Rule ID 1392 //
46618 /* 131182 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
46619 /* 131185 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
46620 /* 131188 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
46621 /* 131191 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46622 /* 131195 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46623 /* 131199 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46624 /* 131203 */ // (fminimum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMINhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
46625 /* 131203 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhd),
46626 /* 131206 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46627 /* 131208 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46628 /* 131210 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46629 /* 131212 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46630 /* 131215 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46631 /* 131221 */ GIR_RootConstrainSelectedInstOperands,
46632 /* 131222 */ // GIR_Coverage, 1392,
46633 /* 131222 */ GIR_EraseRootFromParent_Done,
46634 /* 131223 */ // Label 2565: @131223
46635 /* 131223 */ GIM_Reject,
46636 /* 131224 */ // Label 2559: @131224
46637 /* 131224 */ GIM_Try, /*On fail goto*//*Label 2566*/ GIMT_Encode4(131270), // Rule ID 1391 //
46638 /* 131229 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46639 /* 131232 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
46640 /* 131235 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
46641 /* 131238 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46642 /* 131242 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46643 /* 131246 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46644 /* 131250 */ // (fminimum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMINfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
46645 /* 131250 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINfq),
46646 /* 131253 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46647 /* 131255 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46648 /* 131257 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46649 /* 131259 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46650 /* 131262 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46651 /* 131268 */ GIR_RootConstrainSelectedInstOperands,
46652 /* 131269 */ // GIR_Coverage, 1391,
46653 /* 131269 */ GIR_EraseRootFromParent_Done,
46654 /* 131270 */ // Label 2566: @131270
46655 /* 131270 */ GIM_Reject,
46656 /* 131271 */ // Label 2560: @131271
46657 /* 131271 */ GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(131317), // Rule ID 1393 //
46658 /* 131276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
46659 /* 131279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
46660 /* 131282 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
46661 /* 131285 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46662 /* 131289 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46663 /* 131293 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46664 /* 131297 */ // (fminimum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMINhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
46665 /* 131297 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINhq),
46666 /* 131300 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46667 /* 131302 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46668 /* 131304 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46669 /* 131306 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46670 /* 131309 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46671 /* 131315 */ GIR_RootConstrainSelectedInstOperands,
46672 /* 131316 */ // GIR_Coverage, 1393,
46673 /* 131316 */ GIR_EraseRootFromParent_Done,
46674 /* 131317 */ // Label 2567: @131317
46675 /* 131317 */ GIM_Reject,
46676 /* 131318 */ // Label 2561: @131318
46677 /* 131318 */ GIM_Reject,
46678 /* 131319 */ // Label 56: @131319
46679 /* 131319 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2574*/ GIMT_Encode4(132052),
46680 /* 131330 */ /*GILLT_s16*//*Label 2568*/ GIMT_Encode4(131382),
46681 /* 131334 */ /*GILLT_s32*//*Label 2569*/ GIMT_Encode4(131623), GIMT_Encode4(0), GIMT_Encode4(0),
46682 /* 131346 */ /*GILLT_v2s32*//*Label 2570*/ GIMT_Encode4(131864), GIMT_Encode4(0), GIMT_Encode4(0),
46683 /* 131358 */ /*GILLT_v4s16*//*Label 2571*/ GIMT_Encode4(131911),
46684 /* 131362 */ /*GILLT_v4s32*//*Label 2572*/ GIMT_Encode4(131958), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
46685 /* 131378 */ /*GILLT_v8s16*//*Label 2573*/ GIMT_Encode4(132005),
46686 /* 131382 */ // Label 2568: @131382
46687 /* 131382 */ GIM_Try, /*On fail goto*//*Label 2575*/ GIMT_Encode4(131622), // Rule ID 3056 //
46688 /* 131387 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
46689 /* 131390 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
46690 /* 131393 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
46691 /* 131396 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46692 /* 131400 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46693 /* 131404 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
46694 /* 131408 */ // (fmaximum:{ *:[f16] } HPR:{ *:[f16] }:$a, HPR:{ *:[f16] }:$b) => (EXTRACT_SUBREG:{ *:[f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (VMAXhd:{ *:[f64] } (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v4f16] } (COPY_TO_REGCLASS:{ *:[v4f16] } (IMPLICIT_DEF:{ *:[v4f16] }), DPR_VFP2:{ *:[i32] }), HPR:{ *:[f16] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
46695 /* 131408 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v4s16,
46696 /* 131411 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46697 /* 131415 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46698 /* 131420 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
46699 /* 131422 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v4s16,
46700 /* 131425 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46701 /* 131429 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46702 /* 131434 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
46703 /* 131437 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46704 /* 131442 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v4s16,
46705 /* 131445 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46706 /* 131449 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46707 /* 131454 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
46708 /* 131457 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
46709 /* 131461 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
46710 /* 131464 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46711 /* 131469 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46712 /* 131474 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
46713 /* 131479 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v4s16,
46714 /* 131482 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46715 /* 131486 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46716 /* 131491 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
46717 /* 131493 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v4s16,
46718 /* 131496 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46719 /* 131500 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46720 /* 131505 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
46721 /* 131508 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46722 /* 131513 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v4s16,
46723 /* 131516 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46724 /* 131520 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46725 /* 131525 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
46726 /* 131528 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
46727 /* 131532 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
46728 /* 131535 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46729 /* 131540 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46730 /* 131545 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::HPRRegClassID),
46731 /* 131550 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
46732 /* 131553 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXhd),
46733 /* 131557 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46734 /* 131562 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
46735 /* 131565 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
46736 /* 131568 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
46737 /* 131571 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46738 /* 131577 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46739 /* 131579 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s16,
46740 /* 131582 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46741 /* 131586 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46742 /* 131591 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
46743 /* 131594 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46744 /* 131599 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46745 /* 131602 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46746 /* 131604 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
46747 /* 131611 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
46748 /* 131616 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46749 /* 131621 */ // GIR_Coverage, 3056,
46750 /* 131621 */ GIR_EraseRootFromParent_Done,
46751 /* 131622 */ // Label 2575: @131622
46752 /* 131622 */ GIM_Reject,
46753 /* 131623 */ // Label 2569: @131623
46754 /* 131623 */ GIM_Try, /*On fail goto*//*Label 2576*/ GIMT_Encode4(131863), // Rule ID 3058 //
46755 /* 131628 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46756 /* 131631 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
46757 /* 131634 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
46758 /* 131637 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46759 /* 131641 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46760 /* 131645 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
46761 /* 131649 */ // (fmaximum:{ *:[f32] } SPR:{ *:[f32] }:$a, SPR:{ *:[f32] }:$b) => (EXTRACT_SUBREG:{ *:[f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (VMAXfd:{ *:[f64] } (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$a, ssub_0:{ *:[i32] }), (INSERT_SUBREG:{ *:[v2f32] } (COPY_TO_REGCLASS:{ *:[v2f32] } (IMPLICIT_DEF:{ *:[v2f32] }), DPR_VFP2:{ *:[i32] }), SPR:{ *:[f32] }:$b, ssub_0:{ *:[i32] })), DPR_VFP2:{ *:[i32] }), ssub_0:{ *:[i32] })
46762 /* 131649 */ GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_v2s32,
46763 /* 131652 */ GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46764 /* 131656 */ GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46765 /* 131661 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/8,
46766 /* 131663 */ GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_v2s32,
46767 /* 131666 */ GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46768 /* 131670 */ GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46769 /* 131675 */ GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7,
46770 /* 131678 */ GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46771 /* 131683 */ GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_v2s32,
46772 /* 131686 */ GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46773 /* 131690 */ GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46774 /* 131695 */ GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6,
46775 /* 131698 */ GIR_Copy, /*NewInsnID*/6, /*OldInsnID*/0, /*OpIdx*/2, // b
46776 /* 131702 */ GIR_AddImm8, /*InsnID*/6, /*Imm*/17,
46777 /* 131705 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46778 /* 131710 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46779 /* 131715 */ GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
46780 /* 131720 */ GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_v2s32,
46781 /* 131723 */ GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
46782 /* 131727 */ GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46783 /* 131732 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/5,
46784 /* 131734 */ GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_v2s32,
46785 /* 131737 */ GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46786 /* 131741 */ GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46787 /* 131746 */ GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4,
46788 /* 131749 */ GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46789 /* 131754 */ GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_v2s32,
46790 /* 131757 */ GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG),
46791 /* 131761 */ GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46792 /* 131766 */ GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3,
46793 /* 131769 */ GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a
46794 /* 131773 */ GIR_AddImm8, /*InsnID*/3, /*Imm*/17,
46795 /* 131776 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46796 /* 131781 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46797 /* 131786 */ GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/2, GIMT_Encode2(ARM::SPRRegClassID),
46798 /* 131791 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64,
46799 /* 131794 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(ARM::VMAXfd),
46800 /* 131798 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46801 /* 131803 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2,
46802 /* 131806 */ GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/5,
46803 /* 131809 */ GIR_AddImm8, /*InsnID*/2, /*Imm*/14,
46804 /* 131812 */ GIR_AddRegister, /*InsnID*/2, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46805 /* 131818 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/2,
46806 /* 131820 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v2s32,
46807 /* 131823 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46808 /* 131827 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46809 /* 131832 */ GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
46810 /* 131835 */ GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46811 /* 131840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY),
46812 /* 131843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst]
46813 /* 131845 */ GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(ARM::ssub_0),
46814 /* 131852 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(ARM::SPRRegClassID),
46815 /* 131857 */ GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(ARM::DPR_VFP2RegClassID),
46816 /* 131862 */ // GIR_Coverage, 3058,
46817 /* 131862 */ GIR_EraseRootFromParent_Done,
46818 /* 131863 */ // Label 2576: @131863
46819 /* 131863 */ GIM_Reject,
46820 /* 131864 */ // Label 2570: @131864
46821 /* 131864 */ GIM_Try, /*On fail goto*//*Label 2577*/ GIMT_Encode4(131910), // Rule ID 1370 //
46822 /* 131869 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46823 /* 131872 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
46824 /* 131875 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
46825 /* 131878 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46826 /* 131882 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46827 /* 131886 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46828 /* 131890 */ // (fmaximum:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm) => (VMAXfd:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vn, DPR:{ *:[v2f32] }:$Vm)
46829 /* 131890 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfd),
46830 /* 131893 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46831 /* 131895 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46832 /* 131897 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46833 /* 131899 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46834 /* 131902 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46835 /* 131908 */ GIR_RootConstrainSelectedInstOperands,
46836 /* 131909 */ // GIR_Coverage, 1370,
46837 /* 131909 */ GIR_EraseRootFromParent_Done,
46838 /* 131910 */ // Label 2577: @131910
46839 /* 131910 */ GIM_Reject,
46840 /* 131911 */ // Label 2571: @131911
46841 /* 131911 */ GIM_Try, /*On fail goto*//*Label 2578*/ GIMT_Encode4(131957), // Rule ID 1372 //
46842 /* 131916 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
46843 /* 131919 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
46844 /* 131922 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
46845 /* 131925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46846 /* 131929 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46847 /* 131933 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
46848 /* 131937 */ // (fmaximum:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm) => (VMAXhd:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vn, DPR:{ *:[v4f16] }:$Vm)
46849 /* 131937 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhd),
46850 /* 131940 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46851 /* 131942 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46852 /* 131944 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46853 /* 131946 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46854 /* 131949 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46855 /* 131955 */ GIR_RootConstrainSelectedInstOperands,
46856 /* 131956 */ // GIR_Coverage, 1372,
46857 /* 131956 */ GIR_EraseRootFromParent_Done,
46858 /* 131957 */ // Label 2578: @131957
46859 /* 131957 */ GIM_Reject,
46860 /* 131958 */ // Label 2572: @131958
46861 /* 131958 */ GIM_Try, /*On fail goto*//*Label 2579*/ GIMT_Encode4(132004), // Rule ID 1371 //
46862 /* 131963 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
46863 /* 131966 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
46864 /* 131969 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
46865 /* 131972 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46866 /* 131976 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46867 /* 131980 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46868 /* 131984 */ // (fmaximum:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm) => (VMAXfq:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vn, QPR:{ *:[v4f32] }:$Vm)
46869 /* 131984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXfq),
46870 /* 131987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46871 /* 131989 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46872 /* 131991 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46873 /* 131993 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46874 /* 131996 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46875 /* 132002 */ GIR_RootConstrainSelectedInstOperands,
46876 /* 132003 */ // GIR_Coverage, 1371,
46877 /* 132003 */ GIR_EraseRootFromParent_Done,
46878 /* 132004 */ // Label 2579: @132004
46879 /* 132004 */ GIM_Reject,
46880 /* 132005 */ // Label 2573: @132005
46881 /* 132005 */ GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(132051), // Rule ID 1373 //
46882 /* 132010 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON),
46883 /* 132013 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
46884 /* 132016 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
46885 /* 132019 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46886 /* 132023 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46887 /* 132027 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
46888 /* 132031 */ // (fmaximum:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm) => (VMAXhq:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vn, QPR:{ *:[v8f16] }:$Vm)
46889 /* 132031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXhq),
46890 /* 132034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
46891 /* 132036 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
46892 /* 132038 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
46893 /* 132040 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46894 /* 132043 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46895 /* 132049 */ GIR_RootConstrainSelectedInstOperands,
46896 /* 132050 */ // GIR_Coverage, 1373,
46897 /* 132050 */ GIR_EraseRootFromParent_Done,
46898 /* 132051 */ // Label 2580: @132051
46899 /* 132051 */ GIM_Reject,
46900 /* 132052 */ // Label 2574: @132052
46901 /* 132052 */ GIM_Reject,
46902 /* 132053 */ // Label 57: @132053
46903 /* 132053 */ GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(132085), // Rule ID 2761 //
46904 /* 132058 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46905 /* 132061 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
46906 /* 132065 */ // (get_fpenv:{ *:[i32] }) => (VMRS:{ *:[i32] })
46907 /* 132065 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS),
46908 /* 132068 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
46909 /* 132070 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46910 /* 132073 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46911 /* 132079 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
46912 /* 132083 */ GIR_RootConstrainSelectedInstOperands,
46913 /* 132084 */ // GIR_Coverage, 2761,
46914 /* 132084 */ GIR_EraseRootFromParent_Done,
46915 /* 132085 */ // Label 2581: @132085
46916 /* 132085 */ GIM_Reject,
46917 /* 132086 */ // Label 58: @132086
46918 /* 132086 */ GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(132121), // Rule ID 2762 //
46919 /* 132091 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46920 /* 132094 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
46921 /* 132098 */ // (set_fpenv GPRnopc:{ *:[i32] }:$Rt) => (VMSR:{ *:[i32] } GPRnopc:{ *:[i32] }:$Rt)
46922 /* 132098 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
46923 /* 132101 */ GIR_RootToRootCopy, /*OpIdx*/0, // Rt
46924 /* 132103 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46925 /* 132106 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46926 /* 132112 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
46927 /* 132115 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
46928 /* 132119 */ GIR_RootConstrainSelectedInstOperands,
46929 /* 132120 */ // GIR_Coverage, 2762,
46930 /* 132120 */ GIR_EraseRootFromParent_Done,
46931 /* 132121 */ // Label 2582: @132121
46932 /* 132121 */ GIM_Reject,
46933 /* 132122 */ // Label 59: @132122
46934 /* 132122 */ GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(132186), // Rule ID 2763 //
46935 /* 132127 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
46936 /* 132130 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (MOVi:{ *:[i32] } 0:{ *:[i32] }))
46937 /* 132130 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
46938 /* 132133 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::MOVi),
46939 /* 132137 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46940 /* 132142 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
46941 /* 132145 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
46942 /* 132148 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46943 /* 132154 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46944 /* 132160 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
46945 /* 132162 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
46946 /* 132165 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46947 /* 132168 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46948 /* 132171 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46949 /* 132177 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
46950 /* 132180 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
46951 /* 132184 */ GIR_RootConstrainSelectedInstOperands,
46952 /* 132185 */ // GIR_Coverage, 2763,
46953 /* 132185 */ GIR_EraseRootFromParent_Done,
46954 /* 132186 */ // Label 2583: @132186
46955 /* 132186 */ GIM_Try, /*On fail goto*//*Label 2584*/ GIMT_Encode4(132250), // Rule ID 2764 //
46956 /* 132191 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb),
46957 /* 132194 */ // (reset_fpenv) => (VMSR:{ *:[i32] } (tMOVi8:{ *:[i32] } 0:{ *:[i32] }))
46958 /* 132194 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
46959 /* 132197 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::tMOVi8),
46960 /* 132201 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
46961 /* 132206 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::CPSR), /*AddRegisterRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define|RegState::Dead)),
46962 /* 132212 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
46963 /* 132215 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
46964 /* 132218 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46965 /* 132224 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
46966 /* 132226 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMSR),
46967 /* 132229 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
46968 /* 132232 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46969 /* 132235 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46970 /* 132241 */ GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for ARM::FPSCR*/0,
46971 /* 132244 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
46972 /* 132248 */ GIR_RootConstrainSelectedInstOperands,
46973 /* 132249 */ // GIR_Coverage, 2764,
46974 /* 132249 */ GIR_EraseRootFromParent_Done,
46975 /* 132250 */ // Label 2584: @132250
46976 /* 132250 */ GIM_Reject,
46977 /* 132251 */ // Label 60: @132251
46978 /* 132251 */ GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(132283), // Rule ID 2765 //
46979 /* 132256 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
46980 /* 132259 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRnopcRegClassID),
46981 /* 132263 */ // (get_fpmode:{ *:[i32] }) => (VMRS:{ *:[i32] })
46982 /* 132263 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMRS),
46983 /* 132266 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rt]
46984 /* 132268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
46985 /* 132271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
46986 /* 132277 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
46987 /* 132281 */ GIR_RootConstrainSelectedInstOperands,
46988 /* 132282 */ // GIR_Coverage, 2765,
46989 /* 132282 */ GIR_EraseRootFromParent_Done,
46990 /* 132283 */ // Label 2585: @132283
46991 /* 132283 */ GIM_Reject,
46992 /* 132284 */ // Label 61: @132284
46993 /* 132284 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2592*/ GIMT_Encode4(132826),
46994 /* 132295 */ /*GILLT_v2s32*//*Label 2586*/ GIMT_Encode4(132343), GIMT_Encode4(0), GIMT_Encode4(0),
46995 /* 132307 */ /*GILLT_v4s16*//*Label 2587*/ GIMT_Encode4(132390),
46996 /* 132311 */ /*GILLT_v4s32*//*Label 2588*/ GIMT_Encode4(132437), GIMT_Encode4(0), GIMT_Encode4(0),
46997 /* 132323 */ /*GILLT_v8s8*//*Label 2589*/ GIMT_Encode4(132551),
46998 /* 132327 */ /*GILLT_v8s16*//*Label 2590*/ GIMT_Encode4(132598), GIMT_Encode4(0), GIMT_Encode4(0),
46999 /* 132339 */ /*GILLT_v16s8*//*Label 2591*/ GIMT_Encode4(132712),
47000 /* 132343 */ // Label 2586: @132343
47001 /* 132343 */ GIM_Try, /*On fail goto*//*Label 2593*/ GIMT_Encode4(132389), // Rule ID 1379 //
47002 /* 132348 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47003 /* 132351 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
47004 /* 132354 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
47005 /* 132357 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47006 /* 132361 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47007 /* 132365 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47008 /* 132369 */ // (smin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
47009 /* 132369 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv2i32),
47010 /* 132372 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47011 /* 132374 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47012 /* 132376 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47013 /* 132378 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47014 /* 132381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47015 /* 132387 */ GIR_RootConstrainSelectedInstOperands,
47016 /* 132388 */ // GIR_Coverage, 1379,
47017 /* 132388 */ GIR_EraseRootFromParent_Done,
47018 /* 132389 */ // Label 2593: @132389
47019 /* 132389 */ GIM_Reject,
47020 /* 132390 */ // Label 2587: @132390
47021 /* 132390 */ GIM_Try, /*On fail goto*//*Label 2594*/ GIMT_Encode4(132436), // Rule ID 1378 //
47022 /* 132395 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47023 /* 132398 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
47024 /* 132401 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
47025 /* 132404 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47026 /* 132408 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47027 /* 132412 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47028 /* 132416 */ // (smin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
47029 /* 132416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i16),
47030 /* 132419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47031 /* 132421 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47032 /* 132423 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47033 /* 132425 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47034 /* 132428 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47035 /* 132434 */ GIR_RootConstrainSelectedInstOperands,
47036 /* 132435 */ // GIR_Coverage, 1378,
47037 /* 132435 */ GIR_EraseRootFromParent_Done,
47038 /* 132436 */ // Label 2594: @132436
47039 /* 132436 */ GIM_Reject,
47040 /* 132437 */ // Label 2588: @132437
47041 /* 132437 */ GIM_Try, /*On fail goto*//*Label 2595*/ GIMT_Encode4(132550),
47042 /* 132442 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
47043 /* 132445 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
47044 /* 132448 */ GIM_Try, /*On fail goto*//*Label 2596*/ GIMT_Encode4(132488), // Rule ID 1381 //
47045 /* 132453 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47046 /* 132456 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47047 /* 132460 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47048 /* 132464 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47049 /* 132468 */ // (smin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
47050 /* 132468 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv4i32),
47051 /* 132471 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47052 /* 132473 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47053 /* 132475 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47054 /* 132477 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47055 /* 132480 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47056 /* 132486 */ GIR_RootConstrainSelectedInstOperands,
47057 /* 132487 */ // GIR_Coverage, 1381,
47058 /* 132487 */ GIR_EraseRootFromParent_Done,
47059 /* 132488 */ // Label 2596: @132488
47060 /* 132488 */ GIM_Try, /*On fail goto*//*Label 2597*/ GIMT_Encode4(132549), // Rule ID 3658 //
47061 /* 132493 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47062 /* 132496 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47063 /* 132500 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47064 /* 132504 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47065 /* 132508 */ // (smin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
47066 /* 132508 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47067 /* 132511 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47068 /* 132515 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47069 /* 132520 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs32),
47070 /* 132523 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47071 /* 132525 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47072 /* 132527 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47073 /* 132529 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47074 /* 132532 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47075 /* 132538 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47076 /* 132544 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47077 /* 132547 */ GIR_RootConstrainSelectedInstOperands,
47078 /* 132548 */ // GIR_Coverage, 3658,
47079 /* 132548 */ GIR_EraseRootFromParent_Done,
47080 /* 132549 */ // Label 2597: @132549
47081 /* 132549 */ GIM_Reject,
47082 /* 132550 */ // Label 2595: @132550
47083 /* 132550 */ GIM_Reject,
47084 /* 132551 */ // Label 2589: @132551
47085 /* 132551 */ GIM_Try, /*On fail goto*//*Label 2598*/ GIMT_Encode4(132597), // Rule ID 1382 //
47086 /* 132556 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47087 /* 132559 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
47088 /* 132562 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
47089 /* 132565 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47090 /* 132569 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47091 /* 132573 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47092 /* 132577 */ // (smin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
47093 /* 132577 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i8),
47094 /* 132580 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47095 /* 132582 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47096 /* 132584 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47097 /* 132586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47098 /* 132589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47099 /* 132595 */ GIR_RootConstrainSelectedInstOperands,
47100 /* 132596 */ // GIR_Coverage, 1382,
47101 /* 132596 */ GIR_EraseRootFromParent_Done,
47102 /* 132597 */ // Label 2598: @132597
47103 /* 132597 */ GIM_Reject,
47104 /* 132598 */ // Label 2590: @132598
47105 /* 132598 */ GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(132711),
47106 /* 132603 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
47107 /* 132606 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
47108 /* 132609 */ GIM_Try, /*On fail goto*//*Label 2600*/ GIMT_Encode4(132649), // Rule ID 1380 //
47109 /* 132614 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47110 /* 132617 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47111 /* 132621 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47112 /* 132625 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47113 /* 132629 */ // (smin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
47114 /* 132629 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv8i16),
47115 /* 132632 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47116 /* 132634 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47117 /* 132636 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47118 /* 132638 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47119 /* 132641 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47120 /* 132647 */ GIR_RootConstrainSelectedInstOperands,
47121 /* 132648 */ // GIR_Coverage, 1380,
47122 /* 132648 */ GIR_EraseRootFromParent_Done,
47123 /* 132649 */ // Label 2600: @132649
47124 /* 132649 */ GIM_Try, /*On fail goto*//*Label 2601*/ GIMT_Encode4(132710), // Rule ID 3655 //
47125 /* 132654 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47126 /* 132657 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47127 /* 132661 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47128 /* 132665 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47129 /* 132669 */ // (smin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
47130 /* 132669 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47131 /* 132672 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47132 /* 132676 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47133 /* 132681 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs16),
47134 /* 132684 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47135 /* 132686 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47136 /* 132688 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47137 /* 132690 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47138 /* 132693 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47139 /* 132699 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47140 /* 132705 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47141 /* 132708 */ GIR_RootConstrainSelectedInstOperands,
47142 /* 132709 */ // GIR_Coverage, 3655,
47143 /* 132709 */ GIR_EraseRootFromParent_Done,
47144 /* 132710 */ // Label 2601: @132710
47145 /* 132710 */ GIM_Reject,
47146 /* 132711 */ // Label 2599: @132711
47147 /* 132711 */ GIM_Reject,
47148 /* 132712 */ // Label 2591: @132712
47149 /* 132712 */ GIM_Try, /*On fail goto*//*Label 2602*/ GIMT_Encode4(132825),
47150 /* 132717 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
47151 /* 132720 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
47152 /* 132723 */ GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(132763), // Rule ID 1383 //
47153 /* 132728 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47154 /* 132731 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47155 /* 132735 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47156 /* 132739 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47157 /* 132743 */ // (smin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
47158 /* 132743 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINsv16i8),
47159 /* 132746 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47160 /* 132748 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47161 /* 132750 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47162 /* 132752 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47163 /* 132755 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47164 /* 132761 */ GIR_RootConstrainSelectedInstOperands,
47165 /* 132762 */ // GIR_Coverage, 1383,
47166 /* 132762 */ GIR_EraseRootFromParent_Done,
47167 /* 132763 */ // Label 2603: @132763
47168 /* 132763 */ GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(132824), // Rule ID 3652 //
47169 /* 132768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47170 /* 132771 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47171 /* 132775 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47172 /* 132779 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47173 /* 132783 */ // (smin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
47174 /* 132783 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47175 /* 132786 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47176 /* 132790 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47177 /* 132795 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINs8),
47178 /* 132798 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47179 /* 132800 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47180 /* 132802 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47181 /* 132804 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47182 /* 132807 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47183 /* 132813 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47184 /* 132819 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47185 /* 132822 */ GIR_RootConstrainSelectedInstOperands,
47186 /* 132823 */ // GIR_Coverage, 3652,
47187 /* 132823 */ GIR_EraseRootFromParent_Done,
47188 /* 132824 */ // Label 2604: @132824
47189 /* 132824 */ GIM_Reject,
47190 /* 132825 */ // Label 2602: @132825
47191 /* 132825 */ GIM_Reject,
47192 /* 132826 */ // Label 2592: @132826
47193 /* 132826 */ GIM_Reject,
47194 /* 132827 */ // Label 62: @132827
47195 /* 132827 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2611*/ GIMT_Encode4(133369),
47196 /* 132838 */ /*GILLT_v2s32*//*Label 2605*/ GIMT_Encode4(132886), GIMT_Encode4(0), GIMT_Encode4(0),
47197 /* 132850 */ /*GILLT_v4s16*//*Label 2606*/ GIMT_Encode4(132933),
47198 /* 132854 */ /*GILLT_v4s32*//*Label 2607*/ GIMT_Encode4(132980), GIMT_Encode4(0), GIMT_Encode4(0),
47199 /* 132866 */ /*GILLT_v8s8*//*Label 2608*/ GIMT_Encode4(133094),
47200 /* 132870 */ /*GILLT_v8s16*//*Label 2609*/ GIMT_Encode4(133141), GIMT_Encode4(0), GIMT_Encode4(0),
47201 /* 132882 */ /*GILLT_v16s8*//*Label 2610*/ GIMT_Encode4(133255),
47202 /* 132886 */ // Label 2605: @132886
47203 /* 132886 */ GIM_Try, /*On fail goto*//*Label 2612*/ GIMT_Encode4(132932), // Rule ID 1359 //
47204 /* 132891 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47205 /* 132894 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
47206 /* 132897 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
47207 /* 132900 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47208 /* 132904 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47209 /* 132908 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47210 /* 132912 */ // (smax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXsv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
47211 /* 132912 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv2i32),
47212 /* 132915 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47213 /* 132917 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47214 /* 132919 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47215 /* 132921 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47216 /* 132924 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47217 /* 132930 */ GIR_RootConstrainSelectedInstOperands,
47218 /* 132931 */ // GIR_Coverage, 1359,
47219 /* 132931 */ GIR_EraseRootFromParent_Done,
47220 /* 132932 */ // Label 2612: @132932
47221 /* 132932 */ GIM_Reject,
47222 /* 132933 */ // Label 2606: @132933
47223 /* 132933 */ GIM_Try, /*On fail goto*//*Label 2613*/ GIMT_Encode4(132979), // Rule ID 1358 //
47224 /* 132938 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47225 /* 132941 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
47226 /* 132944 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
47227 /* 132947 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47228 /* 132951 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47229 /* 132955 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47230 /* 132959 */ // (smax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXsv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
47231 /* 132959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i16),
47232 /* 132962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47233 /* 132964 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47234 /* 132966 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47235 /* 132968 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47236 /* 132971 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47237 /* 132977 */ GIR_RootConstrainSelectedInstOperands,
47238 /* 132978 */ // GIR_Coverage, 1358,
47239 /* 132978 */ GIR_EraseRootFromParent_Done,
47240 /* 132979 */ // Label 2613: @132979
47241 /* 132979 */ GIM_Reject,
47242 /* 132980 */ // Label 2607: @132980
47243 /* 132980 */ GIM_Try, /*On fail goto*//*Label 2614*/ GIMT_Encode4(133093),
47244 /* 132985 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
47245 /* 132988 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
47246 /* 132991 */ GIM_Try, /*On fail goto*//*Label 2615*/ GIMT_Encode4(133031), // Rule ID 1361 //
47247 /* 132996 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47248 /* 132999 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47249 /* 133003 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47250 /* 133007 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47251 /* 133011 */ // (smax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXsv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
47252 /* 133011 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv4i32),
47253 /* 133014 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47254 /* 133016 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47255 /* 133018 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47256 /* 133020 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47257 /* 133023 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47258 /* 133029 */ GIR_RootConstrainSelectedInstOperands,
47259 /* 133030 */ // GIR_Coverage, 1361,
47260 /* 133030 */ GIR_EraseRootFromParent_Done,
47261 /* 133031 */ // Label 2615: @133031
47262 /* 133031 */ GIM_Try, /*On fail goto*//*Label 2616*/ GIMT_Encode4(133092), // Rule ID 3676 //
47263 /* 133036 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47264 /* 133039 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47265 /* 133043 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47266 /* 133047 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47267 /* 133051 */ // (smax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
47268 /* 133051 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47269 /* 133054 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47270 /* 133058 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47271 /* 133063 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs32),
47272 /* 133066 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47273 /* 133068 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47274 /* 133070 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47275 /* 133072 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47276 /* 133075 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47277 /* 133081 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47278 /* 133087 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47279 /* 133090 */ GIR_RootConstrainSelectedInstOperands,
47280 /* 133091 */ // GIR_Coverage, 3676,
47281 /* 133091 */ GIR_EraseRootFromParent_Done,
47282 /* 133092 */ // Label 2616: @133092
47283 /* 133092 */ GIM_Reject,
47284 /* 133093 */ // Label 2614: @133093
47285 /* 133093 */ GIM_Reject,
47286 /* 133094 */ // Label 2608: @133094
47287 /* 133094 */ GIM_Try, /*On fail goto*//*Label 2617*/ GIMT_Encode4(133140), // Rule ID 1362 //
47288 /* 133099 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47289 /* 133102 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
47290 /* 133105 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
47291 /* 133108 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47292 /* 133112 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47293 /* 133116 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47294 /* 133120 */ // (smax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXsv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
47295 /* 133120 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i8),
47296 /* 133123 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47297 /* 133125 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47298 /* 133127 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47299 /* 133129 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47300 /* 133132 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47301 /* 133138 */ GIR_RootConstrainSelectedInstOperands,
47302 /* 133139 */ // GIR_Coverage, 1362,
47303 /* 133139 */ GIR_EraseRootFromParent_Done,
47304 /* 133140 */ // Label 2617: @133140
47305 /* 133140 */ GIM_Reject,
47306 /* 133141 */ // Label 2609: @133141
47307 /* 133141 */ GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(133254),
47308 /* 133146 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
47309 /* 133149 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
47310 /* 133152 */ GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(133192), // Rule ID 1360 //
47311 /* 133157 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47312 /* 133160 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47313 /* 133164 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47314 /* 133168 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47315 /* 133172 */ // (smax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXsv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
47316 /* 133172 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv8i16),
47317 /* 133175 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47318 /* 133177 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47319 /* 133179 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47320 /* 133181 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47321 /* 133184 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47322 /* 133190 */ GIR_RootConstrainSelectedInstOperands,
47323 /* 133191 */ // GIR_Coverage, 1360,
47324 /* 133191 */ GIR_EraseRootFromParent_Done,
47325 /* 133192 */ // Label 2619: @133192
47326 /* 133192 */ GIM_Try, /*On fail goto*//*Label 2620*/ GIMT_Encode4(133253), // Rule ID 3673 //
47327 /* 133197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47328 /* 133200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47329 /* 133204 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47330 /* 133208 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47331 /* 133212 */ // (smax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
47332 /* 133212 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47333 /* 133215 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47334 /* 133219 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47335 /* 133224 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs16),
47336 /* 133227 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47337 /* 133229 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47338 /* 133231 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47339 /* 133233 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47340 /* 133236 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47341 /* 133242 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47342 /* 133248 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47343 /* 133251 */ GIR_RootConstrainSelectedInstOperands,
47344 /* 133252 */ // GIR_Coverage, 3673,
47345 /* 133252 */ GIR_EraseRootFromParent_Done,
47346 /* 133253 */ // Label 2620: @133253
47347 /* 133253 */ GIM_Reject,
47348 /* 133254 */ // Label 2618: @133254
47349 /* 133254 */ GIM_Reject,
47350 /* 133255 */ // Label 2610: @133255
47351 /* 133255 */ GIM_Try, /*On fail goto*//*Label 2621*/ GIMT_Encode4(133368),
47352 /* 133260 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
47353 /* 133263 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
47354 /* 133266 */ GIM_Try, /*On fail goto*//*Label 2622*/ GIMT_Encode4(133306), // Rule ID 1363 //
47355 /* 133271 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47356 /* 133274 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47357 /* 133278 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47358 /* 133282 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47359 /* 133286 */ // (smax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXsv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
47360 /* 133286 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXsv16i8),
47361 /* 133289 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47362 /* 133291 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47363 /* 133293 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47364 /* 133295 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47365 /* 133298 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47366 /* 133304 */ GIR_RootConstrainSelectedInstOperands,
47367 /* 133305 */ // GIR_Coverage, 1363,
47368 /* 133305 */ GIR_EraseRootFromParent_Done,
47369 /* 133306 */ // Label 2622: @133306
47370 /* 133306 */ GIM_Try, /*On fail goto*//*Label 2623*/ GIMT_Encode4(133367), // Rule ID 3670 //
47371 /* 133311 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47372 /* 133314 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47373 /* 133318 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47374 /* 133322 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47375 /* 133326 */ // (smax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
47376 /* 133326 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47377 /* 133329 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47378 /* 133333 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47379 /* 133338 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXs8),
47380 /* 133341 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47381 /* 133343 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47382 /* 133345 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47383 /* 133347 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47384 /* 133350 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47385 /* 133356 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47386 /* 133362 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47387 /* 133365 */ GIR_RootConstrainSelectedInstOperands,
47388 /* 133366 */ // GIR_Coverage, 3670,
47389 /* 133366 */ GIR_EraseRootFromParent_Done,
47390 /* 133367 */ // Label 2623: @133367
47391 /* 133367 */ GIM_Reject,
47392 /* 133368 */ // Label 2621: @133368
47393 /* 133368 */ GIM_Reject,
47394 /* 133369 */ // Label 2611: @133369
47395 /* 133369 */ GIM_Reject,
47396 /* 133370 */ // Label 63: @133370
47397 /* 133370 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2630*/ GIMT_Encode4(134290),
47398 /* 133381 */ /*GILLT_v2s32*//*Label 2624*/ GIMT_Encode4(133429), GIMT_Encode4(0), GIMT_Encode4(0),
47399 /* 133393 */ /*GILLT_v4s16*//*Label 2625*/ GIMT_Encode4(133476),
47400 /* 133397 */ /*GILLT_v4s32*//*Label 2626*/ GIMT_Encode4(133523), GIMT_Encode4(0), GIMT_Encode4(0),
47401 /* 133409 */ /*GILLT_v8s8*//*Label 2627*/ GIMT_Encode4(133763),
47402 /* 133413 */ /*GILLT_v8s16*//*Label 2628*/ GIMT_Encode4(133810), GIMT_Encode4(0), GIMT_Encode4(0),
47403 /* 133425 */ /*GILLT_v16s8*//*Label 2629*/ GIMT_Encode4(134050),
47404 /* 133429 */ // Label 2624: @133429
47405 /* 133429 */ GIM_Try, /*On fail goto*//*Label 2631*/ GIMT_Encode4(133475), // Rule ID 1385 //
47406 /* 133434 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47407 /* 133437 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
47408 /* 133440 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
47409 /* 133443 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47410 /* 133447 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47411 /* 133451 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47412 /* 133455 */ // (umin:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMINuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
47413 /* 133455 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv2i32),
47414 /* 133458 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47415 /* 133460 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47416 /* 133462 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47417 /* 133464 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47418 /* 133467 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47419 /* 133473 */ GIR_RootConstrainSelectedInstOperands,
47420 /* 133474 */ // GIR_Coverage, 1385,
47421 /* 133474 */ GIR_EraseRootFromParent_Done,
47422 /* 133475 */ // Label 2631: @133475
47423 /* 133475 */ GIM_Reject,
47424 /* 133476 */ // Label 2625: @133476
47425 /* 133476 */ GIM_Try, /*On fail goto*//*Label 2632*/ GIMT_Encode4(133522), // Rule ID 1384 //
47426 /* 133481 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47427 /* 133484 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
47428 /* 133487 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
47429 /* 133490 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47430 /* 133494 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47431 /* 133498 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47432 /* 133502 */ // (umin:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMINuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
47433 /* 133502 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i16),
47434 /* 133505 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47435 /* 133507 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47436 /* 133509 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47437 /* 133511 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47438 /* 133514 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47439 /* 133520 */ GIR_RootConstrainSelectedInstOperands,
47440 /* 133521 */ // GIR_Coverage, 1384,
47441 /* 133521 */ GIR_EraseRootFromParent_Done,
47442 /* 133522 */ // Label 2632: @133522
47443 /* 133522 */ GIM_Reject,
47444 /* 133523 */ // Label 2626: @133523
47445 /* 133523 */ GIM_Try, /*On fail goto*//*Label 2633*/ GIMT_Encode4(133762),
47446 /* 133528 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
47447 /* 133531 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
47448 /* 133534 */ GIM_Try, /*On fail goto*//*Label 2634*/ GIMT_Encode4(133597), // Rule ID 6598 //
47449 /* 133539 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47450 /* 133542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47451 /* 133546 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47452 /* 133550 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47453 /* 133554 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47454 /* 133558 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47455 /* 133563 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47456 /* 133567 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47457 /* 133569 */ // (umin:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
47458 /* 133569 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32),
47459 /* 133572 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47460 /* 133574 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
47461 /* 133576 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47462 /* 133580 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47463 /* 133583 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47464 /* 133589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47465 /* 133595 */ GIR_RootConstrainSelectedInstOperands,
47466 /* 133596 */ // GIR_Coverage, 6598,
47467 /* 133596 */ GIR_EraseRootFromParent_Done,
47468 /* 133597 */ // Label 2634: @133597
47469 /* 133597 */ GIM_Try, /*On fail goto*//*Label 2635*/ GIMT_Encode4(133660), // Rule ID 4055 //
47470 /* 133602 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47471 /* 133605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47472 /* 133609 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47473 /* 133613 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47474 /* 133617 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47475 /* 133621 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47476 /* 133625 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47477 /* 133630 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47478 /* 133632 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMINAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
47479 /* 133632 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs32),
47480 /* 133635 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47481 /* 133637 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
47482 /* 133639 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47483 /* 133643 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47484 /* 133646 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47485 /* 133652 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47486 /* 133658 */ GIR_RootConstrainSelectedInstOperands,
47487 /* 133659 */ // GIR_Coverage, 4055,
47488 /* 133659 */ GIR_EraseRootFromParent_Done,
47489 /* 133660 */ // Label 2635: @133660
47490 /* 133660 */ GIM_Try, /*On fail goto*//*Label 2636*/ GIMT_Encode4(133700), // Rule ID 1387 //
47491 /* 133665 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47492 /* 133668 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47493 /* 133672 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47494 /* 133676 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47495 /* 133680 */ // (umin:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMINuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
47496 /* 133680 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv4i32),
47497 /* 133683 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47498 /* 133685 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47499 /* 133687 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47500 /* 133689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47501 /* 133692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47502 /* 133698 */ GIR_RootConstrainSelectedInstOperands,
47503 /* 133699 */ // GIR_Coverage, 1387,
47504 /* 133699 */ GIR_EraseRootFromParent_Done,
47505 /* 133700 */ // Label 2636: @133700
47506 /* 133700 */ GIM_Try, /*On fail goto*//*Label 2637*/ GIMT_Encode4(133761), // Rule ID 3667 //
47507 /* 133705 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47508 /* 133708 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47509 /* 133712 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47510 /* 133716 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47511 /* 133720 */ // (umin:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMINu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
47512 /* 133720 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47513 /* 133723 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47514 /* 133727 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47515 /* 133732 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu32),
47516 /* 133735 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47517 /* 133737 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47518 /* 133739 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47519 /* 133741 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47520 /* 133744 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47521 /* 133750 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47522 /* 133756 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47523 /* 133759 */ GIR_RootConstrainSelectedInstOperands,
47524 /* 133760 */ // GIR_Coverage, 3667,
47525 /* 133760 */ GIR_EraseRootFromParent_Done,
47526 /* 133761 */ // Label 2637: @133761
47527 /* 133761 */ GIM_Reject,
47528 /* 133762 */ // Label 2633: @133762
47529 /* 133762 */ GIM_Reject,
47530 /* 133763 */ // Label 2627: @133763
47531 /* 133763 */ GIM_Try, /*On fail goto*//*Label 2638*/ GIMT_Encode4(133809), // Rule ID 1388 //
47532 /* 133768 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47533 /* 133771 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
47534 /* 133774 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
47535 /* 133777 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47536 /* 133781 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47537 /* 133785 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47538 /* 133789 */ // (umin:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMINuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
47539 /* 133789 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i8),
47540 /* 133792 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47541 /* 133794 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47542 /* 133796 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47543 /* 133798 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47544 /* 133801 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47545 /* 133807 */ GIR_RootConstrainSelectedInstOperands,
47546 /* 133808 */ // GIR_Coverage, 1388,
47547 /* 133808 */ GIR_EraseRootFromParent_Done,
47548 /* 133809 */ // Label 2638: @133809
47549 /* 133809 */ GIM_Reject,
47550 /* 133810 */ // Label 2628: @133810
47551 /* 133810 */ GIM_Try, /*On fail goto*//*Label 2639*/ GIMT_Encode4(134049),
47552 /* 133815 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
47553 /* 133818 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
47554 /* 133821 */ GIM_Try, /*On fail goto*//*Label 2640*/ GIMT_Encode4(133884), // Rule ID 6597 //
47555 /* 133826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47556 /* 133829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47557 /* 133833 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47558 /* 133837 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47559 /* 133841 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47560 /* 133845 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47561 /* 133850 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47562 /* 133854 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47563 /* 133856 */ // (umin:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
47564 /* 133856 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16),
47565 /* 133859 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47566 /* 133861 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
47567 /* 133863 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47568 /* 133867 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47569 /* 133870 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47570 /* 133876 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47571 /* 133882 */ GIR_RootConstrainSelectedInstOperands,
47572 /* 133883 */ // GIR_Coverage, 6597,
47573 /* 133883 */ GIR_EraseRootFromParent_Done,
47574 /* 133884 */ // Label 2640: @133884
47575 /* 133884 */ GIM_Try, /*On fail goto*//*Label 2641*/ GIMT_Encode4(133947), // Rule ID 4053 //
47576 /* 133889 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47577 /* 133892 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47578 /* 133896 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47579 /* 133900 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47580 /* 133904 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47581 /* 133908 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47582 /* 133912 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47583 /* 133917 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47584 /* 133919 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMINAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
47585 /* 133919 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs16),
47586 /* 133922 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47587 /* 133924 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
47588 /* 133926 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47589 /* 133930 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47590 /* 133933 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47591 /* 133939 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47592 /* 133945 */ GIR_RootConstrainSelectedInstOperands,
47593 /* 133946 */ // GIR_Coverage, 4053,
47594 /* 133946 */ GIR_EraseRootFromParent_Done,
47595 /* 133947 */ // Label 2641: @133947
47596 /* 133947 */ GIM_Try, /*On fail goto*//*Label 2642*/ GIMT_Encode4(133987), // Rule ID 1386 //
47597 /* 133952 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47598 /* 133955 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47599 /* 133959 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47600 /* 133963 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47601 /* 133967 */ // (umin:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMINuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
47602 /* 133967 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv8i16),
47603 /* 133970 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47604 /* 133972 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47605 /* 133974 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47606 /* 133976 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47607 /* 133979 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47608 /* 133985 */ GIR_RootConstrainSelectedInstOperands,
47609 /* 133986 */ // GIR_Coverage, 1386,
47610 /* 133986 */ GIR_EraseRootFromParent_Done,
47611 /* 133987 */ // Label 2642: @133987
47612 /* 133987 */ GIM_Try, /*On fail goto*//*Label 2643*/ GIMT_Encode4(134048), // Rule ID 3664 //
47613 /* 133992 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47614 /* 133995 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47615 /* 133999 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47616 /* 134003 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47617 /* 134007 */ // (umin:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMINu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
47618 /* 134007 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47619 /* 134010 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47620 /* 134014 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47621 /* 134019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu16),
47622 /* 134022 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47623 /* 134024 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47624 /* 134026 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47625 /* 134028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47626 /* 134031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47627 /* 134037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47628 /* 134043 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47629 /* 134046 */ GIR_RootConstrainSelectedInstOperands,
47630 /* 134047 */ // GIR_Coverage, 3664,
47631 /* 134047 */ GIR_EraseRootFromParent_Done,
47632 /* 134048 */ // Label 2643: @134048
47633 /* 134048 */ GIM_Reject,
47634 /* 134049 */ // Label 2639: @134049
47635 /* 134049 */ GIM_Reject,
47636 /* 134050 */ // Label 2629: @134050
47637 /* 134050 */ GIM_Try, /*On fail goto*//*Label 2644*/ GIMT_Encode4(134289),
47638 /* 134055 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
47639 /* 134058 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
47640 /* 134061 */ GIM_Try, /*On fail goto*//*Label 2645*/ GIMT_Encode4(134124), // Rule ID 6596 //
47641 /* 134066 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47642 /* 134069 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47643 /* 134073 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47644 /* 134077 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47645 /* 134081 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
47646 /* 134085 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47647 /* 134090 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47648 /* 134094 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47649 /* 134096 */ // (umin:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
47650 /* 134096 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8),
47651 /* 134099 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47652 /* 134101 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
47653 /* 134103 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47654 /* 134107 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47655 /* 134110 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47656 /* 134116 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47657 /* 134122 */ GIR_RootConstrainSelectedInstOperands,
47658 /* 134123 */ // GIR_Coverage, 6596,
47659 /* 134123 */ GIR_EraseRootFromParent_Done,
47660 /* 134124 */ // Label 2645: @134124
47661 /* 134124 */ GIM_Try, /*On fail goto*//*Label 2646*/ GIMT_Encode4(134187), // Rule ID 4051 //
47662 /* 134129 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47663 /* 134132 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47664 /* 134136 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47665 /* 134140 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47666 /* 134144 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47667 /* 134148 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
47668 /* 134152 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47669 /* 134157 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47670 /* 134159 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMINAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
47671 /* 134159 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINAs8),
47672 /* 134162 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47673 /* 134164 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
47674 /* 134166 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47675 /* 134170 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47676 /* 134173 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47677 /* 134179 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47678 /* 134185 */ GIR_RootConstrainSelectedInstOperands,
47679 /* 134186 */ // GIR_Coverage, 4051,
47680 /* 134186 */ GIR_EraseRootFromParent_Done,
47681 /* 134187 */ // Label 2646: @134187
47682 /* 134187 */ GIM_Try, /*On fail goto*//*Label 2647*/ GIMT_Encode4(134227), // Rule ID 1389 //
47683 /* 134192 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47684 /* 134195 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47685 /* 134199 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47686 /* 134203 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47687 /* 134207 */ // (umin:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMINuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
47688 /* 134207 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMINuv16i8),
47689 /* 134210 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47690 /* 134212 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47691 /* 134214 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47692 /* 134216 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47693 /* 134219 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47694 /* 134225 */ GIR_RootConstrainSelectedInstOperands,
47695 /* 134226 */ // GIR_Coverage, 1389,
47696 /* 134226 */ GIR_EraseRootFromParent_Done,
47697 /* 134227 */ // Label 2647: @134227
47698 /* 134227 */ GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(134288), // Rule ID 3661 //
47699 /* 134232 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47700 /* 134235 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47701 /* 134239 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47702 /* 134243 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47703 /* 134247 */ // (umin:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMINu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
47704 /* 134247 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47705 /* 134250 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47706 /* 134254 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47707 /* 134259 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINu8),
47708 /* 134262 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47709 /* 134264 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47710 /* 134266 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47711 /* 134268 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47712 /* 134271 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47713 /* 134277 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47714 /* 134283 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47715 /* 134286 */ GIR_RootConstrainSelectedInstOperands,
47716 /* 134287 */ // GIR_Coverage, 3661,
47717 /* 134287 */ GIR_EraseRootFromParent_Done,
47718 /* 134288 */ // Label 2648: @134288
47719 /* 134288 */ GIM_Reject,
47720 /* 134289 */ // Label 2644: @134289
47721 /* 134289 */ GIM_Reject,
47722 /* 134290 */ // Label 2630: @134290
47723 /* 134290 */ GIM_Reject,
47724 /* 134291 */ // Label 64: @134291
47725 /* 134291 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2655*/ GIMT_Encode4(135211),
47726 /* 134302 */ /*GILLT_v2s32*//*Label 2649*/ GIMT_Encode4(134350), GIMT_Encode4(0), GIMT_Encode4(0),
47727 /* 134314 */ /*GILLT_v4s16*//*Label 2650*/ GIMT_Encode4(134397),
47728 /* 134318 */ /*GILLT_v4s32*//*Label 2651*/ GIMT_Encode4(134444), GIMT_Encode4(0), GIMT_Encode4(0),
47729 /* 134330 */ /*GILLT_v8s8*//*Label 2652*/ GIMT_Encode4(134684),
47730 /* 134334 */ /*GILLT_v8s16*//*Label 2653*/ GIMT_Encode4(134731), GIMT_Encode4(0), GIMT_Encode4(0),
47731 /* 134346 */ /*GILLT_v16s8*//*Label 2654*/ GIMT_Encode4(134971),
47732 /* 134350 */ // Label 2649: @134350
47733 /* 134350 */ GIM_Try, /*On fail goto*//*Label 2656*/ GIMT_Encode4(134396), // Rule ID 1365 //
47734 /* 134355 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47735 /* 134358 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
47736 /* 134361 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32,
47737 /* 134364 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47738 /* 134368 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47739 /* 134372 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47740 /* 134376 */ // (umax:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm) => (VMAXuv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vn, DPR:{ *:[v2i32] }:$Vm)
47741 /* 134376 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv2i32),
47742 /* 134379 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47743 /* 134381 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47744 /* 134383 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47745 /* 134385 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47746 /* 134388 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47747 /* 134394 */ GIR_RootConstrainSelectedInstOperands,
47748 /* 134395 */ // GIR_Coverage, 1365,
47749 /* 134395 */ GIR_EraseRootFromParent_Done,
47750 /* 134396 */ // Label 2656: @134396
47751 /* 134396 */ GIM_Reject,
47752 /* 134397 */ // Label 2650: @134397
47753 /* 134397 */ GIM_Try, /*On fail goto*//*Label 2657*/ GIMT_Encode4(134443), // Rule ID 1364 //
47754 /* 134402 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47755 /* 134405 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
47756 /* 134408 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16,
47757 /* 134411 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47758 /* 134415 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47759 /* 134419 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47760 /* 134423 */ // (umax:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm) => (VMAXuv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vn, DPR:{ *:[v4i16] }:$Vm)
47761 /* 134423 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i16),
47762 /* 134426 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47763 /* 134428 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47764 /* 134430 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47765 /* 134432 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47766 /* 134435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47767 /* 134441 */ GIR_RootConstrainSelectedInstOperands,
47768 /* 134442 */ // GIR_Coverage, 1364,
47769 /* 134442 */ GIR_EraseRootFromParent_Done,
47770 /* 134443 */ // Label 2657: @134443
47771 /* 134443 */ GIM_Reject,
47772 /* 134444 */ // Label 2651: @134444
47773 /* 134444 */ GIM_Try, /*On fail goto*//*Label 2658*/ GIMT_Encode4(134683),
47774 /* 134449 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
47775 /* 134452 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32,
47776 /* 134455 */ GIM_Try, /*On fail goto*//*Label 2659*/ GIMT_Encode4(134518), // Rule ID 6601 //
47777 /* 134460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47778 /* 134463 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47779 /* 134467 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47780 /* 134471 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47781 /* 134475 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47782 /* 134479 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47783 /* 134484 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47784 /* 134488 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47785 /* 134490 */ // (umax:{ *:[v4i32] } (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm), MQPR:{ *:[v4i32] }:$Qd) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
47786 /* 134490 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32),
47787 /* 134493 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47788 /* 134495 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
47789 /* 134497 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47790 /* 134501 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47791 /* 134504 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47792 /* 134510 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47793 /* 134516 */ GIR_RootConstrainSelectedInstOperands,
47794 /* 134517 */ // GIR_Coverage, 6601,
47795 /* 134517 */ GIR_EraseRootFromParent_Done,
47796 /* 134518 */ // Label 2659: @134518
47797 /* 134518 */ GIM_Try, /*On fail goto*//*Label 2660*/ GIMT_Encode4(134581), // Rule ID 4061 //
47798 /* 134523 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47799 /* 134526 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47800 /* 134530 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47801 /* 134534 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47802 /* 134538 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47803 /* 134542 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
47804 /* 134546 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47805 /* 134551 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47806 /* 134553 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm)) => (MVE_VMAXAs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qd, MQPR:{ *:[v4i32] }:$Qm)
47807 /* 134553 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs32),
47808 /* 134556 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47809 /* 134558 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
47810 /* 134560 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47811 /* 134564 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47812 /* 134567 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47813 /* 134573 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47814 /* 134579 */ GIR_RootConstrainSelectedInstOperands,
47815 /* 134580 */ // GIR_Coverage, 4061,
47816 /* 134580 */ GIR_EraseRootFromParent_Done,
47817 /* 134581 */ // Label 2660: @134581
47818 /* 134581 */ GIM_Try, /*On fail goto*//*Label 2661*/ GIMT_Encode4(134621), // Rule ID 1367 //
47819 /* 134586 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47820 /* 134589 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47821 /* 134593 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47822 /* 134597 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47823 /* 134601 */ // (umax:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm) => (VMAXuv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vn, QPR:{ *:[v4i32] }:$Vm)
47824 /* 134601 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv4i32),
47825 /* 134604 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47826 /* 134606 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47827 /* 134608 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47828 /* 134610 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47829 /* 134613 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47830 /* 134619 */ GIR_RootConstrainSelectedInstOperands,
47831 /* 134620 */ // GIR_Coverage, 1367,
47832 /* 134620 */ GIR_EraseRootFromParent_Done,
47833 /* 134621 */ // Label 2661: @134621
47834 /* 134621 */ GIM_Try, /*On fail goto*//*Label 2662*/ GIMT_Encode4(134682), // Rule ID 3685 //
47835 /* 134626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47836 /* 134629 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47837 /* 134633 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47838 /* 134637 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47839 /* 134641 */ // (umax:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn) => (MVE_VMAXu32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$Qm, MQPR:{ *:[v4i32] }:$Qn)
47840 /* 134641 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47841 /* 134644 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47842 /* 134648 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47843 /* 134653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu32),
47844 /* 134656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47845 /* 134658 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47846 /* 134660 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47847 /* 134662 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47848 /* 134665 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47849 /* 134671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47850 /* 134677 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47851 /* 134680 */ GIR_RootConstrainSelectedInstOperands,
47852 /* 134681 */ // GIR_Coverage, 3685,
47853 /* 134681 */ GIR_EraseRootFromParent_Done,
47854 /* 134682 */ // Label 2662: @134682
47855 /* 134682 */ GIM_Reject,
47856 /* 134683 */ // Label 2658: @134683
47857 /* 134683 */ GIM_Reject,
47858 /* 134684 */ // Label 2652: @134684
47859 /* 134684 */ GIM_Try, /*On fail goto*//*Label 2663*/ GIMT_Encode4(134730), // Rule ID 1368 //
47860 /* 134689 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47861 /* 134692 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
47862 /* 134695 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s8,
47863 /* 134698 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47864 /* 134702 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47865 /* 134706 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
47866 /* 134710 */ // (umax:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm) => (VMAXuv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vn, DPR:{ *:[v8i8] }:$Vm)
47867 /* 134710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i8),
47868 /* 134713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47869 /* 134715 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47870 /* 134717 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47871 /* 134719 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47872 /* 134722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47873 /* 134728 */ GIR_RootConstrainSelectedInstOperands,
47874 /* 134729 */ // GIR_Coverage, 1368,
47875 /* 134729 */ GIR_EraseRootFromParent_Done,
47876 /* 134730 */ // Label 2663: @134730
47877 /* 134730 */ GIM_Reject,
47878 /* 134731 */ // Label 2653: @134731
47879 /* 134731 */ GIM_Try, /*On fail goto*//*Label 2664*/ GIMT_Encode4(134970),
47880 /* 134736 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
47881 /* 134739 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16,
47882 /* 134742 */ GIM_Try, /*On fail goto*//*Label 2665*/ GIMT_Encode4(134805), // Rule ID 6600 //
47883 /* 134747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47884 /* 134750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47885 /* 134754 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47886 /* 134758 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47887 /* 134762 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47888 /* 134766 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47889 /* 134771 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47890 /* 134775 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47891 /* 134777 */ // (umax:{ *:[v8i16] } (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm), MQPR:{ *:[v8i16] }:$Qd) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
47892 /* 134777 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16),
47893 /* 134780 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47894 /* 134782 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
47895 /* 134784 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47896 /* 134788 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47897 /* 134791 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47898 /* 134797 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47899 /* 134803 */ GIR_RootConstrainSelectedInstOperands,
47900 /* 134804 */ // GIR_Coverage, 6600,
47901 /* 134804 */ GIR_EraseRootFromParent_Done,
47902 /* 134805 */ // Label 2665: @134805
47903 /* 134805 */ GIM_Try, /*On fail goto*//*Label 2666*/ GIMT_Encode4(134868), // Rule ID 4059 //
47904 /* 134810 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47905 /* 134813 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47906 /* 134817 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47907 /* 134821 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47908 /* 134825 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47909 /* 134829 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
47910 /* 134833 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47911 /* 134838 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47912 /* 134840 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm)) => (MVE_VMAXAs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qd, MQPR:{ *:[v8i16] }:$Qm)
47913 /* 134840 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs16),
47914 /* 134843 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47915 /* 134845 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
47916 /* 134847 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47917 /* 134851 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47918 /* 134854 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47919 /* 134860 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47920 /* 134866 */ GIR_RootConstrainSelectedInstOperands,
47921 /* 134867 */ // GIR_Coverage, 4059,
47922 /* 134867 */ GIR_EraseRootFromParent_Done,
47923 /* 134868 */ // Label 2666: @134868
47924 /* 134868 */ GIM_Try, /*On fail goto*//*Label 2667*/ GIMT_Encode4(134908), // Rule ID 1366 //
47925 /* 134873 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
47926 /* 134876 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47927 /* 134880 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47928 /* 134884 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
47929 /* 134888 */ // (umax:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm) => (VMAXuv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vn, QPR:{ *:[v8i16] }:$Vm)
47930 /* 134888 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv8i16),
47931 /* 134891 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
47932 /* 134893 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
47933 /* 134895 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
47934 /* 134897 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
47935 /* 134900 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47936 /* 134906 */ GIR_RootConstrainSelectedInstOperands,
47937 /* 134907 */ // GIR_Coverage, 1366,
47938 /* 134907 */ GIR_EraseRootFromParent_Done,
47939 /* 134908 */ // Label 2667: @134908
47940 /* 134908 */ GIM_Try, /*On fail goto*//*Label 2668*/ GIMT_Encode4(134969), // Rule ID 3682 //
47941 /* 134913 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47942 /* 134916 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47943 /* 134920 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47944 /* 134924 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47945 /* 134928 */ // (umax:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn) => (MVE_VMAXu16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$Qm, MQPR:{ *:[v8i16] }:$Qn)
47946 /* 134928 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
47947 /* 134931 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
47948 /* 134935 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
47949 /* 134940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu16),
47950 /* 134943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47951 /* 134945 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
47952 /* 134947 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
47953 /* 134949 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47954 /* 134952 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47955 /* 134958 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47956 /* 134964 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
47957 /* 134967 */ GIR_RootConstrainSelectedInstOperands,
47958 /* 134968 */ // GIR_Coverage, 3682,
47959 /* 134968 */ GIR_EraseRootFromParent_Done,
47960 /* 134969 */ // Label 2668: @134969
47961 /* 134969 */ GIM_Reject,
47962 /* 134970 */ // Label 2664: @134970
47963 /* 134970 */ GIM_Reject,
47964 /* 134971 */ // Label 2654: @134971
47965 /* 134971 */ GIM_Try, /*On fail goto*//*Label 2669*/ GIMT_Encode4(135210),
47966 /* 134976 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
47967 /* 134979 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s8,
47968 /* 134982 */ GIM_Try, /*On fail goto*//*Label 2670*/ GIMT_Encode4(135045), // Rule ID 6599 //
47969 /* 134987 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47970 /* 134990 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47971 /* 134994 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
47972 /* 134998 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47973 /* 135002 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
47974 /* 135006 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47975 /* 135011 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47976 /* 135015 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47977 /* 135017 */ // (umax:{ *:[v16i8] } (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm), MQPR:{ *:[v16i8] }:$Qd) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
47978 /* 135017 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8),
47979 /* 135020 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
47980 /* 135022 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qd
47981 /* 135024 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
47982 /* 135028 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
47983 /* 135031 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47984 /* 135037 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
47985 /* 135043 */ GIR_RootConstrainSelectedInstOperands,
47986 /* 135044 */ // GIR_Coverage, 6599,
47987 /* 135044 */ GIR_EraseRootFromParent_Done,
47988 /* 135045 */ // Label 2670: @135045
47989 /* 135045 */ GIM_Try, /*On fail goto*//*Label 2671*/ GIMT_Encode4(135108), // Rule ID 4057 //
47990 /* 135050 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
47991 /* 135053 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47992 /* 135057 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47993 /* 135061 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
47994 /* 135065 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ABS),
47995 /* 135069 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
47996 /* 135073 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
47997 /* 135078 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
47998 /* 135080 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm)) => (MVE_VMAXAs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qd, MQPR:{ *:[v16i8] }:$Qm)
47999 /* 135080 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXAs8),
48000 /* 135083 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48001 /* 135085 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qd
48002 /* 135087 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Qm
48003 /* 135091 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48004 /* 135094 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48005 /* 135100 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48006 /* 135106 */ GIR_RootConstrainSelectedInstOperands,
48007 /* 135107 */ // GIR_Coverage, 4057,
48008 /* 135107 */ GIR_EraseRootFromParent_Done,
48009 /* 135108 */ // Label 2671: @135108
48010 /* 135108 */ GIM_Try, /*On fail goto*//*Label 2672*/ GIMT_Encode4(135148), // Rule ID 1369 //
48011 /* 135113 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48012 /* 135116 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48013 /* 135120 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48014 /* 135124 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48015 /* 135128 */ // (umax:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm) => (VMAXuv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vn, QPR:{ *:[v16i8] }:$Vm)
48016 /* 135128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMAXuv16i8),
48017 /* 135131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48018 /* 135133 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vn
48019 /* 135135 */ GIR_RootToRootCopy, /*OpIdx*/2, // Vm
48020 /* 135137 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48021 /* 135140 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48022 /* 135146 */ GIR_RootConstrainSelectedInstOperands,
48023 /* 135147 */ // GIR_Coverage, 1369,
48024 /* 135147 */ GIR_EraseRootFromParent_Done,
48025 /* 135148 */ // Label 2672: @135148
48026 /* 135148 */ GIM_Try, /*On fail goto*//*Label 2673*/ GIMT_Encode4(135209), // Rule ID 3679 //
48027 /* 135153 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48028 /* 135156 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48029 /* 135160 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48030 /* 135164 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48031 /* 135168 */ // (umax:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn) => (MVE_VMAXu8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$Qm, MQPR:{ *:[v16i8] }:$Qn)
48032 /* 135168 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48033 /* 135171 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48034 /* 135175 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48035 /* 135180 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXu8),
48036 /* 135183 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48037 /* 135185 */ GIR_RootToRootCopy, /*OpIdx*/1, // Qm
48038 /* 135187 */ GIR_RootToRootCopy, /*OpIdx*/2, // Qn
48039 /* 135189 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48040 /* 135192 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48041 /* 135198 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48042 /* 135204 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48043 /* 135207 */ GIR_RootConstrainSelectedInstOperands,
48044 /* 135208 */ // GIR_Coverage, 3679,
48045 /* 135208 */ GIR_EraseRootFromParent_Done,
48046 /* 135209 */ // Label 2673: @135209
48047 /* 135209 */ GIM_Reject,
48048 /* 135210 */ // Label 2669: @135210
48049 /* 135210 */ GIM_Reject,
48050 /* 135211 */ // Label 2655: @135211
48051 /* 135211 */ GIM_Reject,
48052 /* 135212 */ // Label 65: @135212
48053 /* 135212 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(4), GIMT_Encode2(16), /*)*//*default:*//*Label 2680*/ GIMT_Encode4(135682),
48054 /* 135223 */ /*GILLT_v2s32*//*Label 2674*/ GIMT_Encode4(135271), GIMT_Encode4(0), GIMT_Encode4(0),
48055 /* 135235 */ /*GILLT_v4s16*//*Label 2675*/ GIMT_Encode4(135309),
48056 /* 135239 */ /*GILLT_v4s32*//*Label 2676*/ GIMT_Encode4(135347), GIMT_Encode4(0), GIMT_Encode4(0),
48057 /* 135251 */ /*GILLT_v8s8*//*Label 2677*/ GIMT_Encode4(135446),
48058 /* 135255 */ /*GILLT_v8s16*//*Label 2678*/ GIMT_Encode4(135484), GIMT_Encode4(0), GIMT_Encode4(0),
48059 /* 135267 */ /*GILLT_v16s8*//*Label 2679*/ GIMT_Encode4(135583),
48060 /* 135271 */ // Label 2674: @135271
48061 /* 135271 */ GIM_Try, /*On fail goto*//*Label 2681*/ GIMT_Encode4(135308), // Rule ID 1671 //
48062 /* 135276 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48063 /* 135279 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
48064 /* 135282 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48065 /* 135286 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48066 /* 135290 */ // (abs:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VABSv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
48067 /* 135290 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv2i32),
48068 /* 135293 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48069 /* 135295 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48070 /* 135297 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48071 /* 135300 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48072 /* 135306 */ GIR_RootConstrainSelectedInstOperands,
48073 /* 135307 */ // GIR_Coverage, 1671,
48074 /* 135307 */ GIR_EraseRootFromParent_Done,
48075 /* 135308 */ // Label 2681: @135308
48076 /* 135308 */ GIM_Reject,
48077 /* 135309 */ // Label 2675: @135309
48078 /* 135309 */ GIM_Try, /*On fail goto*//*Label 2682*/ GIMT_Encode4(135346), // Rule ID 1670 //
48079 /* 135314 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48080 /* 135317 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
48081 /* 135320 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48082 /* 135324 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48083 /* 135328 */ // (abs:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VABSv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
48084 /* 135328 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i16),
48085 /* 135331 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48086 /* 135333 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48087 /* 135335 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48088 /* 135338 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48089 /* 135344 */ GIR_RootConstrainSelectedInstOperands,
48090 /* 135345 */ // GIR_Coverage, 1670,
48091 /* 135345 */ GIR_EraseRootFromParent_Done,
48092 /* 135346 */ // Label 2682: @135346
48093 /* 135346 */ GIM_Reject,
48094 /* 135347 */ // Label 2676: @135347
48095 /* 135347 */ GIM_Try, /*On fail goto*//*Label 2683*/ GIMT_Encode4(135445),
48096 /* 135352 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
48097 /* 135355 */ GIM_Try, /*On fail goto*//*Label 2684*/ GIMT_Encode4(135389), // Rule ID 1674 //
48098 /* 135360 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48099 /* 135363 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48100 /* 135367 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48101 /* 135371 */ // (abs:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VABSv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
48102 /* 135371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv4i32),
48103 /* 135374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48104 /* 135376 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48105 /* 135378 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48106 /* 135381 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48107 /* 135387 */ GIR_RootConstrainSelectedInstOperands,
48108 /* 135388 */ // GIR_Coverage, 1674,
48109 /* 135388 */ GIR_EraseRootFromParent_Done,
48110 /* 135389 */ // Label 2684: @135389
48111 /* 135389 */ GIM_Try, /*On fail goto*//*Label 2685*/ GIMT_Encode4(135444), // Rule ID 4030 //
48112 /* 135394 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48113 /* 135397 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48114 /* 135401 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48115 /* 135405 */ // (abs:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$v) => (MVE_VABSs32:{ *:[v4i32] } ?:{ *:[v4i32] }:$v)
48116 /* 135405 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48117 /* 135408 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48118 /* 135412 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48119 /* 135417 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs32),
48120 /* 135420 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48121 /* 135422 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
48122 /* 135424 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48123 /* 135427 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48124 /* 135433 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48125 /* 135439 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48126 /* 135442 */ GIR_RootConstrainSelectedInstOperands,
48127 /* 135443 */ // GIR_Coverage, 4030,
48128 /* 135443 */ GIR_EraseRootFromParent_Done,
48129 /* 135444 */ // Label 2685: @135444
48130 /* 135444 */ GIM_Reject,
48131 /* 135445 */ // Label 2683: @135445
48132 /* 135445 */ GIM_Reject,
48133 /* 135446 */ // Label 2677: @135446
48134 /* 135446 */ GIM_Try, /*On fail goto*//*Label 2686*/ GIMT_Encode4(135483), // Rule ID 1669 //
48135 /* 135451 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48136 /* 135454 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
48137 /* 135457 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48138 /* 135461 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48139 /* 135465 */ // (abs:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VABSv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
48140 /* 135465 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i8),
48141 /* 135468 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48142 /* 135470 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48143 /* 135472 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48144 /* 135475 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48145 /* 135481 */ GIR_RootConstrainSelectedInstOperands,
48146 /* 135482 */ // GIR_Coverage, 1669,
48147 /* 135482 */ GIR_EraseRootFromParent_Done,
48148 /* 135483 */ // Label 2686: @135483
48149 /* 135483 */ GIM_Reject,
48150 /* 135484 */ // Label 2678: @135484
48151 /* 135484 */ GIM_Try, /*On fail goto*//*Label 2687*/ GIMT_Encode4(135582),
48152 /* 135489 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
48153 /* 135492 */ GIM_Try, /*On fail goto*//*Label 2688*/ GIMT_Encode4(135526), // Rule ID 1673 //
48154 /* 135497 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48155 /* 135500 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48156 /* 135504 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48157 /* 135508 */ // (abs:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VABSv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
48158 /* 135508 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv8i16),
48159 /* 135511 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48160 /* 135513 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48161 /* 135515 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48162 /* 135518 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48163 /* 135524 */ GIR_RootConstrainSelectedInstOperands,
48164 /* 135525 */ // GIR_Coverage, 1673,
48165 /* 135525 */ GIR_EraseRootFromParent_Done,
48166 /* 135526 */ // Label 2688: @135526
48167 /* 135526 */ GIM_Try, /*On fail goto*//*Label 2689*/ GIMT_Encode4(135581), // Rule ID 4024 //
48168 /* 135531 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48169 /* 135534 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48170 /* 135538 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48171 /* 135542 */ // (abs:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$v) => (MVE_VABSs16:{ *:[v8i16] } ?:{ *:[v8i16] }:$v)
48172 /* 135542 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48173 /* 135545 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48174 /* 135549 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48175 /* 135554 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs16),
48176 /* 135557 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48177 /* 135559 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
48178 /* 135561 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48179 /* 135564 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48180 /* 135570 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48181 /* 135576 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48182 /* 135579 */ GIR_RootConstrainSelectedInstOperands,
48183 /* 135580 */ // GIR_Coverage, 4024,
48184 /* 135580 */ GIR_EraseRootFromParent_Done,
48185 /* 135581 */ // Label 2689: @135581
48186 /* 135581 */ GIM_Reject,
48187 /* 135582 */ // Label 2687: @135582
48188 /* 135582 */ GIM_Reject,
48189 /* 135583 */ // Label 2679: @135583
48190 /* 135583 */ GIM_Try, /*On fail goto*//*Label 2690*/ GIMT_Encode4(135681),
48191 /* 135588 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
48192 /* 135591 */ GIM_Try, /*On fail goto*//*Label 2691*/ GIMT_Encode4(135625), // Rule ID 1672 //
48193 /* 135596 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48194 /* 135599 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48195 /* 135603 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48196 /* 135607 */ // (abs:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VABSv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
48197 /* 135607 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VABSv16i8),
48198 /* 135610 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48199 /* 135612 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48200 /* 135614 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48201 /* 135617 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48202 /* 135623 */ GIR_RootConstrainSelectedInstOperands,
48203 /* 135624 */ // GIR_Coverage, 1672,
48204 /* 135624 */ GIR_EraseRootFromParent_Done,
48205 /* 135625 */ // Label 2691: @135625
48206 /* 135625 */ GIM_Try, /*On fail goto*//*Label 2692*/ GIMT_Encode4(135680), // Rule ID 4018 //
48207 /* 135630 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48208 /* 135633 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48209 /* 135637 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48210 /* 135641 */ // (abs:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$v) => (MVE_VABSs8:{ *:[v16i8] } ?:{ *:[v16i8] }:$v)
48211 /* 135641 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48212 /* 135644 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48213 /* 135648 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48214 /* 135653 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VABSs8),
48215 /* 135656 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48216 /* 135658 */ GIR_RootToRootCopy, /*OpIdx*/1, // v
48217 /* 135660 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48218 /* 135663 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48219 /* 135669 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48220 /* 135675 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48221 /* 135678 */ GIR_RootConstrainSelectedInstOperands,
48222 /* 135679 */ // GIR_Coverage, 4018,
48223 /* 135679 */ GIR_EraseRootFromParent_Done,
48224 /* 135680 */ // Label 2692: @135680
48225 /* 135680 */ GIM_Reject,
48226 /* 135681 */ // Label 2690: @135681
48227 /* 135681 */ GIM_Reject,
48228 /* 135682 */ // Label 2680: @135682
48229 /* 135682 */ GIM_Reject,
48230 /* 135683 */ // Label 66: @135683
48231 /* 135683 */ GIM_Try, /*On fail goto*//*Label 2693*/ GIMT_Encode4(135755),
48232 /* 135688 */ GIM_CheckIsMBB, /*MI*/0, /*Op*/0,
48233 /* 135691 */ GIM_Try, /*On fail goto*//*Label 2694*/ GIMT_Encode4(135706), // Rule ID 31 //
48234 /* 135696 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
48235 /* 135699 */ // (br (bb:{ *:[Other] }):$target) => (B (bb:{ *:[Other] }):$target)
48236 /* 135699 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::B),
48237 /* 135704 */ GIR_RootConstrainSelectedInstOperands,
48238 /* 135705 */ // GIR_Coverage, 31,
48239 /* 135705 */ GIR_Done,
48240 /* 135706 */ // Label 2694: @135706
48241 /* 135706 */ GIM_Try, /*On fail goto*//*Label 2695*/ GIMT_Encode4(135730), // Rule ID 282 //
48242 /* 135711 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_IsThumb1Only),
48243 /* 135714 */ // (br (bb:{ *:[Other] }):$target) => (tB (bb:{ *:[Other] }):$target)
48244 /* 135714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tB),
48245 /* 135717 */ GIR_RootToRootCopy, /*OpIdx*/0, // target
48246 /* 135719 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48247 /* 135722 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48248 /* 135728 */ GIR_RootConstrainSelectedInstOperands,
48249 /* 135729 */ // GIR_Coverage, 282,
48250 /* 135729 */ GIR_EraseRootFromParent_Done,
48251 /* 135730 */ // Label 2695: @135730
48252 /* 135730 */ GIM_Try, /*On fail goto*//*Label 2696*/ GIMT_Encode4(135754), // Rule ID 576 //
48253 /* 135735 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV8MBaseline_IsThumb),
48254 /* 135738 */ // (br (bb:{ *:[Other] }):$target) => (t2B (bb:{ *:[Other] }):$target)
48255 /* 135738 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2B),
48256 /* 135741 */ GIR_RootToRootCopy, /*OpIdx*/0, // target
48257 /* 135743 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48258 /* 135746 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48259 /* 135752 */ GIR_RootConstrainSelectedInstOperands,
48260 /* 135753 */ // GIR_Coverage, 576,
48261 /* 135753 */ GIR_EraseRootFromParent_Done,
48262 /* 135754 */ // Label 2696: @135754
48263 /* 135754 */ GIM_Reject,
48264 /* 135755 */ // Label 2693: @135755
48265 /* 135755 */ GIM_Reject,
48266 /* 135756 */ // Label 67: @135756
48267 /* 135756 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(16), /*)*//*default:*//*Label 2701*/ GIMT_Encode4(136055),
48268 /* 135767 */ /*GILLT_v4s16*//*Label 2697*/ GIMT_Encode4(135803), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48269 /* 135783 */ /*GILLT_v8s8*//*Label 2698*/ GIMT_Encode4(135866),
48270 /* 135787 */ /*GILLT_v8s16*//*Label 2699*/ GIMT_Encode4(135929), GIMT_Encode4(0), GIMT_Encode4(0),
48271 /* 135799 */ /*GILLT_v16s8*//*Label 2700*/ GIMT_Encode4(135992),
48272 /* 135803 */ // Label 2697: @135803
48273 /* 135803 */ GIM_Try, /*On fail goto*//*Label 2702*/ GIMT_Encode4(135865), // Rule ID 1733 //
48274 /* 135808 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48275 /* 135811 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
48276 /* 135814 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
48277 /* 135817 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48278 /* 135820 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48279 /* 135824 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48280 /* 135828 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48281 /* 135832 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48282 /* 135836 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48283 /* 135840 */ // MIs[1] Operand 1
48284 /* 135840 */ // No operand predicates
48285 /* 135840 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48286 /* 135842 */ // (vector_insert:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane)
48287 /* 135842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi16),
48288 /* 135845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V]
48289 /* 135847 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
48290 /* 135849 */ GIR_RootToRootCopy, /*OpIdx*/2, // R
48291 /* 135851 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
48292 /* 135854 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48293 /* 135857 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48294 /* 135863 */ GIR_RootConstrainSelectedInstOperands,
48295 /* 135864 */ // GIR_Coverage, 1733,
48296 /* 135864 */ GIR_EraseRootFromParent_Done,
48297 /* 135865 */ // Label 2702: @135865
48298 /* 135865 */ GIM_Reject,
48299 /* 135866 */ // Label 2698: @135866
48300 /* 135866 */ GIM_Try, /*On fail goto*//*Label 2703*/ GIMT_Encode4(135928), // Rule ID 1732 //
48301 /* 135871 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48302 /* 135874 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
48303 /* 135877 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
48304 /* 135880 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48305 /* 135883 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48306 /* 135887 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48307 /* 135891 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48308 /* 135895 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48309 /* 135899 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48310 /* 135903 */ // MIs[1] Operand 1
48311 /* 135903 */ // No operand predicates
48312 /* 135903 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48313 /* 135905 */ // (vector_insert:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane) => (VSETLNi8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$src1, GPR:{ *:[i32] }:$R, (imm:{ *:[i32] }):$lane)
48314 /* 135905 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSETLNi8),
48315 /* 135908 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[V]
48316 /* 135910 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
48317 /* 135912 */ GIR_RootToRootCopy, /*OpIdx*/2, // R
48318 /* 135914 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
48319 /* 135917 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48320 /* 135920 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48321 /* 135926 */ GIR_RootConstrainSelectedInstOperands,
48322 /* 135927 */ // GIR_Coverage, 1732,
48323 /* 135927 */ GIR_EraseRootFromParent_Done,
48324 /* 135928 */ // Label 2703: @135928
48325 /* 135928 */ GIM_Reject,
48326 /* 135929 */ // Label 2699: @135929
48327 /* 135929 */ GIM_Try, /*On fail goto*//*Label 2704*/ GIMT_Encode4(135991), // Rule ID 3794 //
48328 /* 135934 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48329 /* 135937 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
48330 /* 135940 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
48331 /* 135943 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48332 /* 135946 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48333 /* 135950 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48334 /* 135954 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48335 /* 135958 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48336 /* 135962 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48337 /* 135966 */ // MIs[1] Operand 1
48338 /* 135966 */ // No operand predicates
48339 /* 135966 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48340 /* 135968 */ // (vector_insert:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane)
48341 /* 135968 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_16),
48342 /* 135971 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48343 /* 135973 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
48344 /* 135975 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2
48345 /* 135977 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
48346 /* 135980 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48347 /* 135983 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48348 /* 135989 */ GIR_RootConstrainSelectedInstOperands,
48349 /* 135990 */ // GIR_Coverage, 3794,
48350 /* 135990 */ GIR_EraseRootFromParent_Done,
48351 /* 135991 */ // Label 2704: @135991
48352 /* 135991 */ GIM_Reject,
48353 /* 135992 */ // Label 2700: @135992
48354 /* 135992 */ GIM_Try, /*On fail goto*//*Label 2705*/ GIMT_Encode4(136054), // Rule ID 3793 //
48355 /* 135997 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48356 /* 136000 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
48357 /* 136003 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
48358 /* 136006 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
48359 /* 136009 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48360 /* 136013 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48361 /* 136017 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48362 /* 136021 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
48363 /* 136025 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48364 /* 136029 */ // MIs[1] Operand 1
48365 /* 136029 */ // No operand predicates
48366 /* 136029 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48367 /* 136031 */ // (vector_insert:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane) => (MVE_VMOV_to_lane_8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, rGPR:{ *:[i32] }:$src2, (imm:{ *:[i32] }):$lane)
48368 /* 136031 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMOV_to_lane_8),
48369 /* 136034 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48370 /* 136036 */ GIR_RootToRootCopy, /*OpIdx*/1, // src1
48371 /* 136038 */ GIR_RootToRootCopy, /*OpIdx*/2, // src2
48372 /* 136040 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
48373 /* 136043 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48374 /* 136046 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48375 /* 136052 */ GIR_RootConstrainSelectedInstOperands,
48376 /* 136053 */ // GIR_Coverage, 3793,
48377 /* 136053 */ GIR_EraseRootFromParent_Done,
48378 /* 136054 */ // Label 2705: @136054
48379 /* 136054 */ GIM_Reject,
48380 /* 136055 */ // Label 2701: @136055
48381 /* 136055 */ GIM_Reject,
48382 /* 136056 */ // Label 68: @136056
48383 /* 136056 */ GIM_Try, /*On fail goto*//*Label 2706*/ GIMT_Encode4(136112), // Rule ID 1731 //
48384 /* 136061 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPRegs_HasFastVGETLNi32),
48385 /* 136064 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
48386 /* 136067 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
48387 /* 136070 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
48388 /* 136073 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48389 /* 136077 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48390 /* 136081 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
48391 /* 136085 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT),
48392 /* 136089 */ // MIs[1] Operand 1
48393 /* 136089 */ // No operand predicates
48394 /* 136089 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
48395 /* 136091 */ // (extractelt:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane) => (VGETLNi32:{ *:[i32] } DPR:{ *:[v2i32] }:$V, (imm:{ *:[i32] }):$lane)
48396 /* 136091 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VGETLNi32),
48397 /* 136094 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[R]
48398 /* 136096 */ GIR_RootToRootCopy, /*OpIdx*/1, // V
48399 /* 136098 */ GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/1, // lane
48400 /* 136101 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48401 /* 136104 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48402 /* 136110 */ GIR_RootConstrainSelectedInstOperands,
48403 /* 136111 */ // GIR_Coverage, 1731,
48404 /* 136111 */ GIR_EraseRootFromParent_Done,
48405 /* 136112 */ // Label 2706: @136112
48406 /* 136112 */ GIM_Reject,
48407 /* 136113 */ // Label 69: @136113
48408 /* 136113 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2714*/ GIMT_Encode4(136673),
48409 /* 136124 */ /*GILLT_s32*//*Label 2707*/ GIMT_Encode4(136184), GIMT_Encode4(0), GIMT_Encode4(0),
48410 /* 136136 */ /*GILLT_v2s32*//*Label 2708*/ GIMT_Encode4(136262), GIMT_Encode4(0), GIMT_Encode4(0),
48411 /* 136148 */ /*GILLT_v4s16*//*Label 2709*/ GIMT_Encode4(136300),
48412 /* 136152 */ /*GILLT_v4s32*//*Label 2710*/ GIMT_Encode4(136338), GIMT_Encode4(0), GIMT_Encode4(0),
48413 /* 136164 */ /*GILLT_v8s8*//*Label 2711*/ GIMT_Encode4(136437),
48414 /* 136168 */ /*GILLT_v8s16*//*Label 2712*/ GIMT_Encode4(136475), GIMT_Encode4(0), GIMT_Encode4(0),
48415 /* 136180 */ /*GILLT_v16s8*//*Label 2713*/ GIMT_Encode4(136574),
48416 /* 136184 */ // Label 2707: @136184
48417 /* 136184 */ GIM_Try, /*On fail goto*//*Label 2715*/ GIMT_Encode4(136261),
48418 /* 136189 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
48419 /* 136192 */ GIM_Try, /*On fail goto*//*Label 2716*/ GIMT_Encode4(136226), // Rule ID 196 //
48420 /* 136197 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsARM),
48421 /* 136200 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48422 /* 136204 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48423 /* 136208 */ // (ctlz:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (CLZ:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
48424 /* 136208 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::CLZ),
48425 /* 136211 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48426 /* 136213 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
48427 /* 136215 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48428 /* 136218 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48429 /* 136224 */ GIR_RootConstrainSelectedInstOperands,
48430 /* 136225 */ // GIR_Coverage, 196,
48431 /* 136225 */ GIR_EraseRootFromParent_Done,
48432 /* 136226 */ // Label 2716: @136226
48433 /* 136226 */ GIM_Try, /*On fail goto*//*Label 2717*/ GIMT_Encode4(136260), // Rule ID 533 //
48434 /* 136231 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
48435 /* 136234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48436 /* 136238 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48437 /* 136242 */ // (ctlz:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2CLZ:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
48438 /* 136242 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2CLZ),
48439 /* 136245 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48440 /* 136247 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
48441 /* 136249 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48442 /* 136252 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48443 /* 136258 */ GIR_RootConstrainSelectedInstOperands,
48444 /* 136259 */ // GIR_Coverage, 533,
48445 /* 136259 */ GIR_EraseRootFromParent_Done,
48446 /* 136260 */ // Label 2717: @136260
48447 /* 136260 */ GIM_Reject,
48448 /* 136261 */ // Label 2715: @136261
48449 /* 136261 */ GIM_Reject,
48450 /* 136262 */ // Label 2708: @136262
48451 /* 136262 */ GIM_Try, /*On fail goto*//*Label 2718*/ GIMT_Encode4(136299), // Rule ID 1709 //
48452 /* 136267 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48453 /* 136270 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
48454 /* 136273 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48455 /* 136277 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48456 /* 136281 */ // (ctlz:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm) => (VCLZv2i32:{ *:[v2i32] } DPR:{ *:[v2i32] }:$Vm)
48457 /* 136281 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv2i32),
48458 /* 136284 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48459 /* 136286 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48460 /* 136288 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48461 /* 136291 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48462 /* 136297 */ GIR_RootConstrainSelectedInstOperands,
48463 /* 136298 */ // GIR_Coverage, 1709,
48464 /* 136298 */ GIR_EraseRootFromParent_Done,
48465 /* 136299 */ // Label 2718: @136299
48466 /* 136299 */ GIM_Reject,
48467 /* 136300 */ // Label 2709: @136300
48468 /* 136300 */ GIM_Try, /*On fail goto*//*Label 2719*/ GIMT_Encode4(136337), // Rule ID 1708 //
48469 /* 136305 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48470 /* 136308 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
48471 /* 136311 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48472 /* 136315 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48473 /* 136319 */ // (ctlz:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm) => (VCLZv4i16:{ *:[v4i16] } DPR:{ *:[v4i16] }:$Vm)
48474 /* 136319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i16),
48475 /* 136322 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48476 /* 136324 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48477 /* 136326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48478 /* 136329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48479 /* 136335 */ GIR_RootConstrainSelectedInstOperands,
48480 /* 136336 */ // GIR_Coverage, 1708,
48481 /* 136336 */ GIR_EraseRootFromParent_Done,
48482 /* 136337 */ // Label 2719: @136337
48483 /* 136337 */ GIM_Reject,
48484 /* 136338 */ // Label 2710: @136338
48485 /* 136338 */ GIM_Try, /*On fail goto*//*Label 2720*/ GIMT_Encode4(136436),
48486 /* 136343 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
48487 /* 136346 */ GIM_Try, /*On fail goto*//*Label 2721*/ GIMT_Encode4(136380), // Rule ID 1712 //
48488 /* 136351 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48489 /* 136354 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48490 /* 136358 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48491 /* 136362 */ // (ctlz:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm) => (VCLZv4i32:{ *:[v4i32] } QPR:{ *:[v4i32] }:$Vm)
48492 /* 136362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv4i32),
48493 /* 136365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48494 /* 136367 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48495 /* 136369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48496 /* 136372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48497 /* 136378 */ GIR_RootConstrainSelectedInstOperands,
48498 /* 136379 */ // GIR_Coverage, 1712,
48499 /* 136379 */ GIR_EraseRootFromParent_Done,
48500 /* 136380 */ // Label 2721: @136380
48501 /* 136380 */ GIM_Try, /*On fail goto*//*Label 2722*/ GIMT_Encode4(136435), // Rule ID 4016 //
48502 /* 136385 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48503 /* 136388 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48504 /* 136392 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48505 /* 136396 */ // (ctlz:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val) => (MVE_VCLZs32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val)
48506 /* 136396 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48507 /* 136399 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48508 /* 136403 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48509 /* 136408 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs32),
48510 /* 136411 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48511 /* 136413 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
48512 /* 136415 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48513 /* 136418 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48514 /* 136424 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48515 /* 136430 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48516 /* 136433 */ GIR_RootConstrainSelectedInstOperands,
48517 /* 136434 */ // GIR_Coverage, 4016,
48518 /* 136434 */ GIR_EraseRootFromParent_Done,
48519 /* 136435 */ // Label 2722: @136435
48520 /* 136435 */ GIM_Reject,
48521 /* 136436 */ // Label 2720: @136436
48522 /* 136436 */ GIM_Reject,
48523 /* 136437 */ // Label 2711: @136437
48524 /* 136437 */ GIM_Try, /*On fail goto*//*Label 2723*/ GIMT_Encode4(136474), // Rule ID 1707 //
48525 /* 136442 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48526 /* 136445 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
48527 /* 136448 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48528 /* 136452 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48529 /* 136456 */ // (ctlz:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCLZv8i8:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
48530 /* 136456 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i8),
48531 /* 136459 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48532 /* 136461 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48533 /* 136463 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48534 /* 136466 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48535 /* 136472 */ GIR_RootConstrainSelectedInstOperands,
48536 /* 136473 */ // GIR_Coverage, 1707,
48537 /* 136473 */ GIR_EraseRootFromParent_Done,
48538 /* 136474 */ // Label 2723: @136474
48539 /* 136474 */ GIM_Reject,
48540 /* 136475 */ // Label 2712: @136475
48541 /* 136475 */ GIM_Try, /*On fail goto*//*Label 2724*/ GIMT_Encode4(136573),
48542 /* 136480 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
48543 /* 136483 */ GIM_Try, /*On fail goto*//*Label 2725*/ GIMT_Encode4(136517), // Rule ID 1711 //
48544 /* 136488 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48545 /* 136491 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48546 /* 136495 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48547 /* 136499 */ // (ctlz:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm) => (VCLZv8i16:{ *:[v8i16] } QPR:{ *:[v8i16] }:$Vm)
48548 /* 136499 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv8i16),
48549 /* 136502 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48550 /* 136504 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48551 /* 136506 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48552 /* 136509 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48553 /* 136515 */ GIR_RootConstrainSelectedInstOperands,
48554 /* 136516 */ // GIR_Coverage, 1711,
48555 /* 136516 */ GIR_EraseRootFromParent_Done,
48556 /* 136517 */ // Label 2725: @136517
48557 /* 136517 */ GIM_Try, /*On fail goto*//*Label 2726*/ GIMT_Encode4(136572), // Rule ID 4014 //
48558 /* 136522 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48559 /* 136525 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48560 /* 136529 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48561 /* 136533 */ // (ctlz:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val) => (MVE_VCLZs16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val)
48562 /* 136533 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48563 /* 136536 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48564 /* 136540 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48565 /* 136545 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs16),
48566 /* 136548 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48567 /* 136550 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
48568 /* 136552 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48569 /* 136555 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48570 /* 136561 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48571 /* 136567 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48572 /* 136570 */ GIR_RootConstrainSelectedInstOperands,
48573 /* 136571 */ // GIR_Coverage, 4014,
48574 /* 136571 */ GIR_EraseRootFromParent_Done,
48575 /* 136572 */ // Label 2726: @136572
48576 /* 136572 */ GIM_Reject,
48577 /* 136573 */ // Label 2724: @136573
48578 /* 136573 */ GIM_Reject,
48579 /* 136574 */ // Label 2713: @136574
48580 /* 136574 */ GIM_Try, /*On fail goto*//*Label 2727*/ GIMT_Encode4(136672),
48581 /* 136579 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
48582 /* 136582 */ GIM_Try, /*On fail goto*//*Label 2728*/ GIMT_Encode4(136616), // Rule ID 1710 //
48583 /* 136587 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48584 /* 136590 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48585 /* 136594 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48586 /* 136598 */ // (ctlz:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCLZv16i8:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
48587 /* 136598 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCLZv16i8),
48588 /* 136601 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48589 /* 136603 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48590 /* 136605 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48591 /* 136608 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48592 /* 136614 */ GIR_RootConstrainSelectedInstOperands,
48593 /* 136615 */ // GIR_Coverage, 1710,
48594 /* 136615 */ GIR_EraseRootFromParent_Done,
48595 /* 136616 */ // Label 2728: @136616
48596 /* 136616 */ GIM_Try, /*On fail goto*//*Label 2729*/ GIMT_Encode4(136671), // Rule ID 4012 //
48597 /* 136621 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48598 /* 136624 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48599 /* 136628 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48600 /* 136632 */ // (ctlz:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val) => (MVE_VCLZs8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val)
48601 /* 136632 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48602 /* 136635 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48603 /* 136639 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48604 /* 136644 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VCLZs8),
48605 /* 136647 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48606 /* 136649 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
48607 /* 136651 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48608 /* 136654 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48609 /* 136660 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48610 /* 136666 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48611 /* 136669 */ GIR_RootConstrainSelectedInstOperands,
48612 /* 136670 */ // GIR_Coverage, 4012,
48613 /* 136670 */ GIR_EraseRootFromParent_Done,
48614 /* 136671 */ // Label 2729: @136671
48615 /* 136671 */ GIM_Reject,
48616 /* 136672 */ // Label 2727: @136672
48617 /* 136672 */ GIM_Reject,
48618 /* 136673 */ // Label 2714: @136673
48619 /* 136673 */ GIM_Reject,
48620 /* 136674 */ // Label 70: @136674
48621 /* 136674 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(11), GIMT_Encode2(16), /*)*//*default:*//*Label 2732*/ GIMT_Encode4(136781),
48622 /* 136685 */ /*GILLT_v8s8*//*Label 2730*/ GIMT_Encode4(136705), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48623 /* 136701 */ /*GILLT_v16s8*//*Label 2731*/ GIMT_Encode4(136743),
48624 /* 136705 */ // Label 2730: @136705
48625 /* 136705 */ GIM_Try, /*On fail goto*//*Label 2733*/ GIMT_Encode4(136742), // Rule ID 1713 //
48626 /* 136710 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48627 /* 136713 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s8,
48628 /* 136716 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48629 /* 136720 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48630 /* 136724 */ // (ctpop:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm) => (VCNTd:{ *:[v8i8] } DPR:{ *:[v8i8] }:$Vm)
48631 /* 136724 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTd),
48632 /* 136727 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48633 /* 136729 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48634 /* 136731 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48635 /* 136734 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48636 /* 136740 */ GIR_RootConstrainSelectedInstOperands,
48637 /* 136741 */ // GIR_Coverage, 1713,
48638 /* 136741 */ GIR_EraseRootFromParent_Done,
48639 /* 136742 */ // Label 2733: @136742
48640 /* 136742 */ GIM_Reject,
48641 /* 136743 */ // Label 2731: @136743
48642 /* 136743 */ GIM_Try, /*On fail goto*//*Label 2734*/ GIMT_Encode4(136780), // Rule ID 1714 //
48643 /* 136748 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON),
48644 /* 136751 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
48645 /* 136754 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48646 /* 136758 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48647 /* 136762 */ // (ctpop:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm) => (VCNTq:{ *:[v16i8] } QPR:{ *:[v16i8] }:$Vm)
48648 /* 136762 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VCNTq),
48649 /* 136765 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Vd]
48650 /* 136767 */ GIR_RootToRootCopy, /*OpIdx*/1, // Vm
48651 /* 136769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48652 /* 136772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48653 /* 136778 */ GIR_RootConstrainSelectedInstOperands,
48654 /* 136779 */ // GIR_Coverage, 1714,
48655 /* 136779 */ GIR_EraseRootFromParent_Done,
48656 /* 136780 */ // Label 2734: @136780
48657 /* 136780 */ GIM_Reject,
48658 /* 136781 */ // Label 2732: @136781
48659 /* 136781 */ GIM_Reject,
48660 /* 136782 */ // Label 71: @136782
48661 /* 136782 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(13), /*)*//*default:*//*Label 2738*/ GIMT_Encode4(137071),
48662 /* 136793 */ /*GILLT_s32*//*Label 2735*/ GIMT_Encode4(136841), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48663 /* 136821 */ /*GILLT_v4s32*//*Label 2736*/ GIMT_Encode4(136953), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48664 /* 136837 */ /*GILLT_v8s16*//*Label 2737*/ GIMT_Encode4(137012),
48665 /* 136841 */ // Label 2735: @136841
48666 /* 136841 */ GIM_Try, /*On fail goto*//*Label 2739*/ GIMT_Encode4(136952),
48667 /* 136846 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
48668 /* 136849 */ GIM_Try, /*On fail goto*//*Label 2740*/ GIMT_Encode4(136883), // Rule ID 198 //
48669 /* 136854 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsARM),
48670 /* 136857 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48671 /* 136861 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48672 /* 136865 */ // (bswap:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (REV:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
48673 /* 136865 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::REV),
48674 /* 136868 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48675 /* 136870 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
48676 /* 136872 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48677 /* 136875 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48678 /* 136881 */ GIR_RootConstrainSelectedInstOperands,
48679 /* 136882 */ // GIR_Coverage, 198,
48680 /* 136882 */ GIR_EraseRootFromParent_Done,
48681 /* 136883 */ // Label 2740: @136883
48682 /* 136883 */ GIM_Try, /*On fail goto*//*Label 2741*/ GIMT_Encode4(136917), // Rule ID 325 //
48683 /* 136888 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6_IsThumb_IsThumb1Only),
48684 /* 136891 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
48685 /* 136895 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::tGPRRegClassID),
48686 /* 136899 */ // (bswap:{ *:[i32] } tGPR:{ *:[i32] }:$Rm) => (tREV:{ *:[i32] } tGPR:{ *:[i32] }:$Rm)
48687 /* 136899 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tREV),
48688 /* 136902 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48689 /* 136904 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
48690 /* 136906 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48691 /* 136909 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48692 /* 136915 */ GIR_RootConstrainSelectedInstOperands,
48693 /* 136916 */ // GIR_Coverage, 325,
48694 /* 136916 */ GIR_EraseRootFromParent_Done,
48695 /* 136917 */ // Label 2741: @136917
48696 /* 136917 */ GIM_Try, /*On fail goto*//*Label 2742*/ GIMT_Encode4(136951), // Rule ID 535 //
48697 /* 136922 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
48698 /* 136925 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48699 /* 136929 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48700 /* 136933 */ // (bswap:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2REV:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
48701 /* 136933 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2REV),
48702 /* 136936 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48703 /* 136938 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
48704 /* 136940 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48705 /* 136943 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48706 /* 136949 */ GIR_RootConstrainSelectedInstOperands,
48707 /* 136950 */ // GIR_Coverage, 535,
48708 /* 136950 */ GIR_EraseRootFromParent_Done,
48709 /* 136951 */ // Label 2742: @136951
48710 /* 136951 */ GIM_Reject,
48711 /* 136952 */ // Label 2739: @136952
48712 /* 136952 */ GIM_Reject,
48713 /* 136953 */ // Label 2736: @136953
48714 /* 136953 */ GIM_Try, /*On fail goto*//*Label 2743*/ GIMT_Encode4(137011), // Rule ID 3689 //
48715 /* 136958 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48716 /* 136961 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
48717 /* 136964 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48718 /* 136968 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48719 /* 136972 */ // (bswap:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VREV32_8:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src)
48720 /* 136972 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48721 /* 136975 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48722 /* 136979 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48723 /* 136984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV32_8),
48724 /* 136987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48725 /* 136989 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
48726 /* 136991 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48727 /* 136994 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48728 /* 137000 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48729 /* 137006 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48730 /* 137009 */ GIR_RootConstrainSelectedInstOperands,
48731 /* 137010 */ // GIR_Coverage, 3689,
48732 /* 137010 */ GIR_EraseRootFromParent_Done,
48733 /* 137011 */ // Label 2743: @137011
48734 /* 137011 */ GIM_Reject,
48735 /* 137012 */ // Label 2737: @137012
48736 /* 137012 */ GIM_Try, /*On fail goto*//*Label 2744*/ GIMT_Encode4(137070), // Rule ID 3688 //
48737 /* 137017 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48738 /* 137020 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
48739 /* 137023 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48740 /* 137027 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48741 /* 137031 */ // (bswap:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src) => (MVE_VREV16_8:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src)
48742 /* 137031 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48743 /* 137034 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48744 /* 137038 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48745 /* 137043 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VREV16_8),
48746 /* 137046 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48747 /* 137048 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
48748 /* 137050 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48749 /* 137053 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48750 /* 137059 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48751 /* 137065 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48752 /* 137068 */ GIR_RootConstrainSelectedInstOperands,
48753 /* 137069 */ // GIR_Coverage, 3688,
48754 /* 137069 */ GIR_EraseRootFromParent_Done,
48755 /* 137070 */ // Label 2744: @137070
48756 /* 137070 */ GIM_Reject,
48757 /* 137071 */ // Label 2738: @137071
48758 /* 137071 */ GIM_Reject,
48759 /* 137072 */ // Label 72: @137072
48760 /* 137072 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(1), GIMT_Encode2(16), /*)*//*default:*//*Label 2749*/ GIMT_Encode4(137503),
48761 /* 137083 */ /*GILLT_s32*//*Label 2745*/ GIMT_Encode4(137143), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48762 /* 137111 */ /*GILLT_v4s32*//*Label 2746*/ GIMT_Encode4(137221), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48763 /* 137127 */ /*GILLT_v8s16*//*Label 2747*/ GIMT_Encode4(137315), GIMT_Encode4(0), GIMT_Encode4(0),
48764 /* 137139 */ /*GILLT_v16s8*//*Label 2748*/ GIMT_Encode4(137409),
48765 /* 137143 */ // Label 2745: @137143
48766 /* 137143 */ GIM_Try, /*On fail goto*//*Label 2750*/ GIMT_Encode4(137220),
48767 /* 137148 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
48768 /* 137151 */ GIM_Try, /*On fail goto*//*Label 2751*/ GIMT_Encode4(137185), // Rule ID 197 //
48769 /* 137156 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV6T2_IsARM),
48770 /* 137159 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48771 /* 137163 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::GPRRegClassID),
48772 /* 137167 */ // (bitreverse:{ *:[i32] } GPR:{ *:[i32] }:$Rm) => (RBIT:{ *:[i32] } GPR:{ *:[i32] }:$Rm)
48773 /* 137167 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::RBIT),
48774 /* 137170 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48775 /* 137172 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
48776 /* 137174 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48777 /* 137177 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48778 /* 137183 */ GIR_RootConstrainSelectedInstOperands,
48779 /* 137184 */ // GIR_Coverage, 197,
48780 /* 137184 */ GIR_EraseRootFromParent_Done,
48781 /* 137185 */ // Label 2751: @137185
48782 /* 137185 */ GIM_Try, /*On fail goto*//*Label 2752*/ GIMT_Encode4(137219), // Rule ID 534 //
48783 /* 137190 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb2),
48784 /* 137193 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48785 /* 137197 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
48786 /* 137201 */ // (bitreverse:{ *:[i32] } rGPR:{ *:[i32] }:$Rm) => (t2RBIT:{ *:[i32] } rGPR:{ *:[i32] }:$Rm)
48787 /* 137201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::t2RBIT),
48788 /* 137204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rd]
48789 /* 137206 */ GIR_RootToRootCopy, /*OpIdx*/1, // Rm
48790 /* 137208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
48791 /* 137211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48792 /* 137217 */ GIR_RootConstrainSelectedInstOperands,
48793 /* 137218 */ // GIR_Coverage, 534,
48794 /* 137218 */ GIR_EraseRootFromParent_Done,
48795 /* 137219 */ // Label 2752: @137219
48796 /* 137219 */ GIM_Reject,
48797 /* 137220 */ // Label 2750: @137220
48798 /* 137220 */ GIM_Reject,
48799 /* 137221 */ // Label 2746: @137221
48800 /* 137221 */ GIM_Try, /*On fail goto*//*Label 2753*/ GIMT_Encode4(137314), // Rule ID 5224 //
48801 /* 137226 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48802 /* 137229 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
48803 /* 137232 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48804 /* 137236 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48805 /* 137240 */ // (bitreverse:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1) => (MVE_VBRSR32:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$val1, (t2MOVi:{ *:[i32] } 32:{ *:[i32] }))
48806 /* 137240 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
48807 /* 137243 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48808 /* 137247 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48809 /* 137252 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48810 /* 137255 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
48811 /* 137259 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48812 /* 137264 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/32,
48813 /* 137267 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48814 /* 137270 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48815 /* 137276 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48816 /* 137282 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48817 /* 137284 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR32),
48818 /* 137287 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48819 /* 137289 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1
48820 /* 137291 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48821 /* 137294 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48822 /* 137297 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48823 /* 137303 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48824 /* 137309 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
48825 /* 137312 */ GIR_RootConstrainSelectedInstOperands,
48826 /* 137313 */ // GIR_Coverage, 5224,
48827 /* 137313 */ GIR_EraseRootFromParent_Done,
48828 /* 137314 */ // Label 2753: @137314
48829 /* 137314 */ GIM_Reject,
48830 /* 137315 */ // Label 2747: @137315
48831 /* 137315 */ GIM_Try, /*On fail goto*//*Label 2754*/ GIMT_Encode4(137408), // Rule ID 5225 //
48832 /* 137320 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48833 /* 137323 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
48834 /* 137326 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48835 /* 137330 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48836 /* 137334 */ // (bitreverse:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1) => (MVE_VBRSR16:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$val1, (t2MOVi:{ *:[i32] } 16:{ *:[i32] }))
48837 /* 137334 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
48838 /* 137337 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48839 /* 137341 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48840 /* 137346 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48841 /* 137349 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
48842 /* 137353 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48843 /* 137358 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/16,
48844 /* 137361 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48845 /* 137364 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48846 /* 137370 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48847 /* 137376 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48848 /* 137378 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR16),
48849 /* 137381 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48850 /* 137383 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1
48851 /* 137385 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48852 /* 137388 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48853 /* 137391 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48854 /* 137397 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48855 /* 137403 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
48856 /* 137406 */ GIR_RootConstrainSelectedInstOperands,
48857 /* 137407 */ // GIR_Coverage, 5225,
48858 /* 137407 */ GIR_EraseRootFromParent_Done,
48859 /* 137408 */ // Label 2754: @137408
48860 /* 137408 */ GIM_Reject,
48861 /* 137409 */ // Label 2748: @137409
48862 /* 137409 */ GIM_Try, /*On fail goto*//*Label 2755*/ GIMT_Encode4(137502), // Rule ID 5223 //
48863 /* 137414 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
48864 /* 137417 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s8,
48865 /* 137420 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48866 /* 137424 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48867 /* 137428 */ // (bitreverse:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1) => (MVE_VBRSR8:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$val1, (t2MOVi:{ *:[i32] } 8:{ *:[i32] }))
48868 /* 137428 */ GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v4s32,
48869 /* 137431 */ GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48870 /* 137435 */ GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48871 /* 137440 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
48872 /* 137443 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
48873 /* 137447 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48874 /* 137452 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/8,
48875 /* 137455 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
48876 /* 137458 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48877 /* 137464 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48878 /* 137470 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
48879 /* 137472 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VBRSR8),
48880 /* 137475 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48881 /* 137477 */ GIR_RootToRootCopy, /*OpIdx*/1, // val1
48882 /* 137479 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48883 /* 137482 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48884 /* 137485 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48885 /* 137491 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48886 /* 137497 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1,
48887 /* 137500 */ GIR_RootConstrainSelectedInstOperands,
48888 /* 137501 */ // GIR_Coverage, 5223,
48889 /* 137501 */ GIR_EraseRootFromParent_Done,
48890 /* 137502 */ // Label 2755: @137502
48891 /* 137502 */ GIM_Reject,
48892 /* 137503 */ // Label 2749: @137503
48893 /* 137503 */ GIM_Reject,
48894 /* 137504 */ // Label 73: @137504
48895 /* 137504 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2763*/ GIMT_Encode4(137878),
48896 /* 137515 */ /*GILLT_s16*//*Label 2756*/ GIMT_Encode4(137567),
48897 /* 137519 */ /*GILLT_s32*//*Label 2757*/ GIMT_Encode4(137594),
48898 /* 137523 */ /*GILLT_s64*//*Label 2758*/ GIMT_Encode4(137621), GIMT_Encode4(0),
48899 /* 137531 */ /*GILLT_v2s32*//*Label 2759*/ GIMT_Encode4(137648), GIMT_Encode4(0), GIMT_Encode4(0),
48900 /* 137543 */ /*GILLT_v4s16*//*Label 2760*/ GIMT_Encode4(137675),
48901 /* 137547 */ /*GILLT_v4s32*//*Label 2761*/ GIMT_Encode4(137702), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
48902 /* 137563 */ /*GILLT_v8s16*//*Label 2762*/ GIMT_Encode4(137790),
48903 /* 137567 */ // Label 2756: @137567
48904 /* 137567 */ GIM_Try, /*On fail goto*//*Label 2764*/ GIMT_Encode4(137593), // Rule ID 722 //
48905 /* 137572 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
48906 /* 137575 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
48907 /* 137578 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48908 /* 137582 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
48909 /* 137586 */ // (fceil:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTPH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
48910 /* 137586 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPH),
48911 /* 137591 */ GIR_RootConstrainSelectedInstOperands,
48912 /* 137592 */ // GIR_Coverage, 722,
48913 /* 137592 */ GIR_Done,
48914 /* 137593 */ // Label 2764: @137593
48915 /* 137593 */ GIM_Reject,
48916 /* 137594 */ // Label 2757: @137594
48917 /* 137594 */ GIM_Try, /*On fail goto*//*Label 2765*/ GIMT_Encode4(137620), // Rule ID 724 //
48918 /* 137599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
48919 /* 137602 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
48920 /* 137605 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48921 /* 137609 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
48922 /* 137613 */ // (fceil:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTPS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
48923 /* 137613 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPS),
48924 /* 137618 */ GIR_RootConstrainSelectedInstOperands,
48925 /* 137619 */ // GIR_Coverage, 724,
48926 /* 137619 */ GIR_Done,
48927 /* 137620 */ // Label 2765: @137620
48928 /* 137620 */ GIM_Reject,
48929 /* 137621 */ // Label 2758: @137621
48930 /* 137621 */ GIM_Try, /*On fail goto*//*Label 2766*/ GIMT_Encode4(137647), // Rule ID 726 //
48931 /* 137626 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
48932 /* 137629 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
48933 /* 137632 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48934 /* 137636 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48935 /* 137640 */ // (fceil:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTPD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
48936 /* 137640 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPD),
48937 /* 137645 */ GIR_RootConstrainSelectedInstOperands,
48938 /* 137646 */ // GIR_Coverage, 726,
48939 /* 137646 */ GIR_Done,
48940 /* 137647 */ // Label 2766: @137647
48941 /* 137647 */ GIM_Reject,
48942 /* 137648 */ // Label 2759: @137648
48943 /* 137648 */ GIM_Try, /*On fail goto*//*Label 2767*/ GIMT_Encode4(137674), // Rule ID 1872 //
48944 /* 137653 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
48945 /* 137656 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
48946 /* 137659 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48947 /* 137663 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48948 /* 137667 */ // (fceil:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTPNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
48949 /* 137667 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDf),
48950 /* 137672 */ GIR_RootConstrainSelectedInstOperands,
48951 /* 137673 */ // GIR_Coverage, 1872,
48952 /* 137673 */ GIR_Done,
48953 /* 137674 */ // Label 2767: @137674
48954 /* 137674 */ GIM_Reject,
48955 /* 137675 */ // Label 2760: @137675
48956 /* 137675 */ GIM_Try, /*On fail goto*//*Label 2768*/ GIMT_Encode4(137701), // Rule ID 1874 //
48957 /* 137680 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
48958 /* 137683 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
48959 /* 137686 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48960 /* 137690 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
48961 /* 137694 */ // (fceil:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTPNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
48962 /* 137694 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNDh),
48963 /* 137699 */ GIR_RootConstrainSelectedInstOperands,
48964 /* 137700 */ // GIR_Coverage, 1874,
48965 /* 137700 */ GIR_Done,
48966 /* 137701 */ // Label 2768: @137701
48967 /* 137701 */ GIM_Reject,
48968 /* 137702 */ // Label 2761: @137702
48969 /* 137702 */ GIM_Try, /*On fail goto*//*Label 2769*/ GIMT_Encode4(137789),
48970 /* 137707 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
48971 /* 137710 */ GIM_Try, /*On fail goto*//*Label 2770*/ GIMT_Encode4(137733), // Rule ID 1873 //
48972 /* 137715 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
48973 /* 137718 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48974 /* 137722 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
48975 /* 137726 */ // (fceil:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTPNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
48976 /* 137726 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQf),
48977 /* 137731 */ GIR_RootConstrainSelectedInstOperands,
48978 /* 137732 */ // GIR_Coverage, 1873,
48979 /* 137732 */ GIR_Done,
48980 /* 137733 */ // Label 2770: @137733
48981 /* 137733 */ GIM_Try, /*On fail goto*//*Label 2771*/ GIMT_Encode4(137788), // Rule ID 4355 //
48982 /* 137738 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
48983 /* 137741 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48984 /* 137745 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
48985 /* 137749 */ // (fceil:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32P:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
48986 /* 137749 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
48987 /* 137752 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
48988 /* 137756 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
48989 /* 137761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32P),
48990 /* 137764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
48991 /* 137766 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
48992 /* 137768 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
48993 /* 137771 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48994 /* 137777 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
48995 /* 137783 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
48996 /* 137786 */ GIR_RootConstrainSelectedInstOperands,
48997 /* 137787 */ // GIR_Coverage, 4355,
48998 /* 137787 */ GIR_EraseRootFromParent_Done,
48999 /* 137788 */ // Label 2771: @137788
49000 /* 137788 */ GIM_Reject,
49001 /* 137789 */ // Label 2769: @137789
49002 /* 137789 */ GIM_Reject,
49003 /* 137790 */ // Label 2762: @137790
49004 /* 137790 */ GIM_Try, /*On fail goto*//*Label 2772*/ GIMT_Encode4(137877),
49005 /* 137795 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
49006 /* 137798 */ GIM_Try, /*On fail goto*//*Label 2773*/ GIMT_Encode4(137821), // Rule ID 1875 //
49007 /* 137803 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
49008 /* 137806 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49009 /* 137810 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49010 /* 137814 */ // (fceil:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTPNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
49011 /* 137814 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTPNQh),
49012 /* 137819 */ GIR_RootConstrainSelectedInstOperands,
49013 /* 137820 */ // GIR_Coverage, 1875,
49014 /* 137820 */ GIR_Done,
49015 /* 137821 */ // Label 2773: @137821
49016 /* 137821 */ GIM_Try, /*On fail goto*//*Label 2774*/ GIMT_Encode4(137876), // Rule ID 4337 //
49017 /* 137826 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
49018 /* 137829 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49019 /* 137833 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49020 /* 137837 */ // (fceil:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16P:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
49021 /* 137837 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
49022 /* 137840 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
49023 /* 137844 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
49024 /* 137849 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16P),
49025 /* 137852 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
49026 /* 137854 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
49027 /* 137856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
49028 /* 137859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49029 /* 137865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49030 /* 137871 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49031 /* 137874 */ GIR_RootConstrainSelectedInstOperands,
49032 /* 137875 */ // GIR_Coverage, 4337,
49033 /* 137875 */ GIR_EraseRootFromParent_Done,
49034 /* 137876 */ // Label 2774: @137876
49035 /* 137876 */ GIM_Reject,
49036 /* 137877 */ // Label 2772: @137877
49037 /* 137877 */ GIM_Reject,
49038 /* 137878 */ // Label 2763: @137878
49039 /* 137878 */ GIM_Reject,
49040 /* 137879 */ // Label 74: @137879
49041 /* 137879 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2778*/ GIMT_Encode4(138016),
49042 /* 137890 */ /*GILLT_s16*//*Label 2775*/ GIMT_Encode4(137902),
49043 /* 137894 */ /*GILLT_s32*//*Label 2776*/ GIMT_Encode4(137940),
49044 /* 137898 */ /*GILLT_s64*//*Label 2777*/ GIMT_Encode4(137978),
49045 /* 137902 */ // Label 2775: @137902
49046 /* 137902 */ GIM_Try, /*On fail goto*//*Label 2779*/ GIMT_Encode4(137939), // Rule ID 738 //
49047 /* 137907 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49048 /* 137910 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49049 /* 137913 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49050 /* 137917 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49051 /* 137921 */ // (fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
49052 /* 137921 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH),
49053 /* 137924 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49054 /* 137926 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49055 /* 137928 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49056 /* 137931 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49057 /* 137937 */ GIR_RootConstrainSelectedInstOperands,
49058 /* 137938 */ // GIR_Coverage, 738,
49059 /* 137938 */ GIR_EraseRootFromParent_Done,
49060 /* 137939 */ // Label 2779: @137939
49061 /* 137939 */ GIM_Reject,
49062 /* 137940 */ // Label 2776: @137940
49063 /* 137940 */ GIM_Try, /*On fail goto*//*Label 2780*/ GIMT_Encode4(137977), // Rule ID 736 //
49064 /* 137945 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2),
49065 /* 137948 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49066 /* 137951 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49067 /* 137955 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49068 /* 137959 */ // (fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
49069 /* 137959 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS),
49070 /* 137962 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49071 /* 137964 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49072 /* 137966 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49073 /* 137969 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49074 /* 137975 */ GIR_RootConstrainSelectedInstOperands,
49075 /* 137976 */ // GIR_Coverage, 736,
49076 /* 137976 */ GIR_EraseRootFromParent_Done,
49077 /* 137977 */ // Label 2780: @137977
49078 /* 137977 */ GIM_Reject,
49079 /* 137978 */ // Label 2777: @137978
49080 /* 137978 */ GIM_Try, /*On fail goto*//*Label 2781*/ GIMT_Encode4(138015), // Rule ID 734 //
49081 /* 137983 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
49082 /* 137986 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49083 /* 137989 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49084 /* 137993 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49085 /* 137997 */ // (fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
49086 /* 137997 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD),
49087 /* 138000 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49088 /* 138002 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
49089 /* 138004 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49090 /* 138007 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49091 /* 138013 */ GIR_RootConstrainSelectedInstOperands,
49092 /* 138014 */ // GIR_Coverage, 734,
49093 /* 138014 */ GIR_EraseRootFromParent_Done,
49094 /* 138015 */ // Label 2781: @138015
49095 /* 138015 */ GIM_Reject,
49096 /* 138016 */ // Label 2778: @138016
49097 /* 138016 */ GIM_Reject,
49098 /* 138017 */ // Label 75: @138017
49099 /* 138017 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2789*/ GIMT_Encode4(138391),
49100 /* 138028 */ /*GILLT_s16*//*Label 2782*/ GIMT_Encode4(138080),
49101 /* 138032 */ /*GILLT_s32*//*Label 2783*/ GIMT_Encode4(138107),
49102 /* 138036 */ /*GILLT_s64*//*Label 2784*/ GIMT_Encode4(138134), GIMT_Encode4(0),
49103 /* 138044 */ /*GILLT_v2s32*//*Label 2785*/ GIMT_Encode4(138161), GIMT_Encode4(0), GIMT_Encode4(0),
49104 /* 138056 */ /*GILLT_v4s16*//*Label 2786*/ GIMT_Encode4(138188),
49105 /* 138060 */ /*GILLT_v4s32*//*Label 2787*/ GIMT_Encode4(138215), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
49106 /* 138076 */ /*GILLT_v8s16*//*Label 2788*/ GIMT_Encode4(138303),
49107 /* 138080 */ // Label 2782: @138080
49108 /* 138080 */ GIM_Try, /*On fail goto*//*Label 2790*/ GIMT_Encode4(138106), // Rule ID 728 //
49109 /* 138085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49110 /* 138088 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49111 /* 138091 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49112 /* 138095 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49113 /* 138099 */ // (ffloor:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTMH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
49114 /* 138099 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMH),
49115 /* 138104 */ GIR_RootConstrainSelectedInstOperands,
49116 /* 138105 */ // GIR_Coverage, 728,
49117 /* 138105 */ GIR_Done,
49118 /* 138106 */ // Label 2790: @138106
49119 /* 138106 */ GIM_Reject,
49120 /* 138107 */ // Label 2783: @138107
49121 /* 138107 */ GIM_Try, /*On fail goto*//*Label 2791*/ GIMT_Encode4(138133), // Rule ID 730 //
49122 /* 138112 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
49123 /* 138115 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49124 /* 138118 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49125 /* 138122 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49126 /* 138126 */ // (ffloor:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTMS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
49127 /* 138126 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMS),
49128 /* 138131 */ GIR_RootConstrainSelectedInstOperands,
49129 /* 138132 */ // GIR_Coverage, 730,
49130 /* 138132 */ GIR_Done,
49131 /* 138133 */ // Label 2791: @138133
49132 /* 138133 */ GIM_Reject,
49133 /* 138134 */ // Label 2784: @138134
49134 /* 138134 */ GIM_Try, /*On fail goto*//*Label 2792*/ GIMT_Encode4(138160), // Rule ID 732 //
49135 /* 138139 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
49136 /* 138142 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49137 /* 138145 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49138 /* 138149 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49139 /* 138153 */ // (ffloor:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTMD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
49140 /* 138153 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMD),
49141 /* 138158 */ GIR_RootConstrainSelectedInstOperands,
49142 /* 138159 */ // GIR_Coverage, 732,
49143 /* 138159 */ GIR_Done,
49144 /* 138160 */ // Label 2792: @138160
49145 /* 138160 */ GIM_Reject,
49146 /* 138161 */ // Label 2785: @138161
49147 /* 138161 */ GIM_Try, /*On fail goto*//*Label 2793*/ GIMT_Encode4(138187), // Rule ID 1868 //
49148 /* 138166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
49149 /* 138169 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
49150 /* 138172 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49151 /* 138176 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49152 /* 138180 */ // (ffloor:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTMNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
49153 /* 138180 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDf),
49154 /* 138185 */ GIR_RootConstrainSelectedInstOperands,
49155 /* 138186 */ // GIR_Coverage, 1868,
49156 /* 138186 */ GIR_Done,
49157 /* 138187 */ // Label 2793: @138187
49158 /* 138187 */ GIM_Reject,
49159 /* 138188 */ // Label 2786: @138188
49160 /* 138188 */ GIM_Try, /*On fail goto*//*Label 2794*/ GIMT_Encode4(138214), // Rule ID 1870 //
49161 /* 138193 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
49162 /* 138196 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
49163 /* 138199 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49164 /* 138203 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49165 /* 138207 */ // (ffloor:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTMNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
49166 /* 138207 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNDh),
49167 /* 138212 */ GIR_RootConstrainSelectedInstOperands,
49168 /* 138213 */ // GIR_Coverage, 1870,
49169 /* 138213 */ GIR_Done,
49170 /* 138214 */ // Label 2794: @138214
49171 /* 138214 */ GIM_Reject,
49172 /* 138215 */ // Label 2787: @138215
49173 /* 138215 */ GIM_Try, /*On fail goto*//*Label 2795*/ GIMT_Encode4(138302),
49174 /* 138220 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
49175 /* 138223 */ GIM_Try, /*On fail goto*//*Label 2796*/ GIMT_Encode4(138246), // Rule ID 1869 //
49176 /* 138228 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
49177 /* 138231 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49178 /* 138235 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49179 /* 138239 */ // (ffloor:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTMNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
49180 /* 138239 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQf),
49181 /* 138244 */ GIR_RootConstrainSelectedInstOperands,
49182 /* 138245 */ // GIR_Coverage, 1869,
49183 /* 138245 */ GIR_Done,
49184 /* 138246 */ // Label 2796: @138246
49185 /* 138246 */ GIM_Try, /*On fail goto*//*Label 2797*/ GIMT_Encode4(138301), // Rule ID 4352 //
49186 /* 138251 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
49187 /* 138254 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49188 /* 138258 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49189 /* 138262 */ // (ffloor:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32M:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
49190 /* 138262 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
49191 /* 138265 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
49192 /* 138269 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
49193 /* 138274 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32M),
49194 /* 138277 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
49195 /* 138279 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
49196 /* 138281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
49197 /* 138284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49198 /* 138290 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49199 /* 138296 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49200 /* 138299 */ GIR_RootConstrainSelectedInstOperands,
49201 /* 138300 */ // GIR_Coverage, 4352,
49202 /* 138300 */ GIR_EraseRootFromParent_Done,
49203 /* 138301 */ // Label 2797: @138301
49204 /* 138301 */ GIM_Reject,
49205 /* 138302 */ // Label 2795: @138302
49206 /* 138302 */ GIM_Reject,
49207 /* 138303 */ // Label 2788: @138303
49208 /* 138303 */ GIM_Try, /*On fail goto*//*Label 2798*/ GIMT_Encode4(138390),
49209 /* 138308 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
49210 /* 138311 */ GIM_Try, /*On fail goto*//*Label 2799*/ GIMT_Encode4(138334), // Rule ID 1871 //
49211 /* 138316 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
49212 /* 138319 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49213 /* 138323 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49214 /* 138327 */ // (ffloor:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTMNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
49215 /* 138327 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTMNQh),
49216 /* 138332 */ GIR_RootConstrainSelectedInstOperands,
49217 /* 138333 */ // GIR_Coverage, 1871,
49218 /* 138333 */ GIR_Done,
49219 /* 138334 */ // Label 2799: @138334
49220 /* 138334 */ GIM_Try, /*On fail goto*//*Label 2800*/ GIMT_Encode4(138389), // Rule ID 4334 //
49221 /* 138339 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
49222 /* 138342 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49223 /* 138346 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49224 /* 138350 */ // (ffloor:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16M:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
49225 /* 138350 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
49226 /* 138353 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
49227 /* 138357 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
49228 /* 138362 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16M),
49229 /* 138365 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
49230 /* 138367 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
49231 /* 138369 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
49232 /* 138372 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49233 /* 138378 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49234 /* 138384 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49235 /* 138387 */ GIR_RootConstrainSelectedInstOperands,
49236 /* 138388 */ // GIR_Coverage, 4334,
49237 /* 138388 */ GIR_EraseRootFromParent_Done,
49238 /* 138389 */ // Label 2800: @138389
49239 /* 138389 */ GIM_Reject,
49240 /* 138390 */ // Label 2798: @138390
49241 /* 138390 */ GIM_Reject,
49242 /* 138391 */ // Label 2789: @138391
49243 /* 138391 */ GIM_Reject,
49244 /* 138392 */ // Label 76: @138392
49245 /* 138392 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(13), /*)*//*default:*//*Label 2808*/ GIMT_Encode4(138799),
49246 /* 138403 */ /*GILLT_s16*//*Label 2801*/ GIMT_Encode4(138455),
49247 /* 138407 */ /*GILLT_s32*//*Label 2802*/ GIMT_Encode4(138493),
49248 /* 138411 */ /*GILLT_s64*//*Label 2803*/ GIMT_Encode4(138531), GIMT_Encode4(0),
49249 /* 138419 */ /*GILLT_v2s32*//*Label 2804*/ GIMT_Encode4(138569), GIMT_Encode4(0), GIMT_Encode4(0),
49250 /* 138431 */ /*GILLT_v4s16*//*Label 2805*/ GIMT_Encode4(138596),
49251 /* 138435 */ /*GILLT_v4s32*//*Label 2806*/ GIMT_Encode4(138623), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
49252 /* 138451 */ /*GILLT_v8s16*//*Label 2807*/ GIMT_Encode4(138711),
49253 /* 138455 */ // Label 2801: @138455
49254 /* 138455 */ GIM_Try, /*On fail goto*//*Label 2809*/ GIMT_Encode4(138492), // Rule ID 704 //
49255 /* 138460 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49256 /* 138463 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49257 /* 138466 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49258 /* 138470 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49259 /* 138474 */ // (frint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTXH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
49260 /* 138474 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXH),
49261 /* 138477 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49262 /* 138479 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49263 /* 138481 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49264 /* 138484 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49265 /* 138490 */ GIR_RootConstrainSelectedInstOperands,
49266 /* 138491 */ // GIR_Coverage, 704,
49267 /* 138491 */ GIR_EraseRootFromParent_Done,
49268 /* 138492 */ // Label 2809: @138492
49269 /* 138492 */ GIM_Reject,
49270 /* 138493 */ // Label 2802: @138493
49271 /* 138493 */ GIM_Try, /*On fail goto*//*Label 2810*/ GIMT_Encode4(138530), // Rule ID 706 //
49272 /* 138498 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
49273 /* 138501 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49274 /* 138504 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49275 /* 138508 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49276 /* 138512 */ // (frint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTXS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
49277 /* 138512 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXS),
49278 /* 138515 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49279 /* 138517 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49280 /* 138519 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49281 /* 138522 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49282 /* 138528 */ GIR_RootConstrainSelectedInstOperands,
49283 /* 138529 */ // GIR_Coverage, 706,
49284 /* 138529 */ GIR_EraseRootFromParent_Done,
49285 /* 138530 */ // Label 2810: @138530
49286 /* 138530 */ GIM_Reject,
49287 /* 138531 */ // Label 2803: @138531
49288 /* 138531 */ GIM_Try, /*On fail goto*//*Label 2811*/ GIMT_Encode4(138568), // Rule ID 708 //
49289 /* 138536 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
49290 /* 138539 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49291 /* 138542 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49292 /* 138546 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49293 /* 138550 */ // (frint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTXD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
49294 /* 138550 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTXD),
49295 /* 138553 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49296 /* 138555 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
49297 /* 138557 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49298 /* 138560 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49299 /* 138566 */ GIR_RootConstrainSelectedInstOperands,
49300 /* 138567 */ // GIR_Coverage, 708,
49301 /* 138567 */ GIR_EraseRootFromParent_Done,
49302 /* 138568 */ // Label 2811: @138568
49303 /* 138568 */ GIM_Reject,
49304 /* 138569 */ // Label 2804: @138569
49305 /* 138569 */ GIM_Try, /*On fail goto*//*Label 2812*/ GIMT_Encode4(138595), // Rule ID 1856 //
49306 /* 138574 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
49307 /* 138577 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32,
49308 /* 138580 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49309 /* 138584 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49310 /* 138588 */ // (frint:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm) => (VRINTXNDf:{ *:[v2f32] } DPR:{ *:[v2f32] }:$Vm)
49311 /* 138588 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDf),
49312 /* 138593 */ GIR_RootConstrainSelectedInstOperands,
49313 /* 138594 */ // GIR_Coverage, 1856,
49314 /* 138594 */ GIR_Done,
49315 /* 138595 */ // Label 2812: @138595
49316 /* 138595 */ GIM_Reject,
49317 /* 138596 */ // Label 2805: @138596
49318 /* 138596 */ GIM_Try, /*On fail goto*//*Label 2813*/ GIMT_Encode4(138622), // Rule ID 1858 //
49319 /* 138601 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
49320 /* 138604 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16,
49321 /* 138607 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49322 /* 138611 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49323 /* 138615 */ // (frint:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm) => (VRINTXNDh:{ *:[v4f16] } DPR:{ *:[v4f16] }:$Vm)
49324 /* 138615 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNDh),
49325 /* 138620 */ GIR_RootConstrainSelectedInstOperands,
49326 /* 138621 */ // GIR_Coverage, 1858,
49327 /* 138621 */ GIR_Done,
49328 /* 138622 */ // Label 2813: @138622
49329 /* 138622 */ GIM_Reject,
49330 /* 138623 */ // Label 2806: @138623
49331 /* 138623 */ GIM_Try, /*On fail goto*//*Label 2814*/ GIMT_Encode4(138710),
49332 /* 138628 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32,
49333 /* 138631 */ GIM_Try, /*On fail goto*//*Label 2815*/ GIMT_Encode4(138654), // Rule ID 1857 //
49334 /* 138636 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNEON_HasV8),
49335 /* 138639 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49336 /* 138643 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49337 /* 138647 */ // (frint:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm) => (VRINTXNQf:{ *:[v4f32] } QPR:{ *:[v4f32] }:$Vm)
49338 /* 138647 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQf),
49339 /* 138652 */ GIR_RootConstrainSelectedInstOperands,
49340 /* 138653 */ // GIR_Coverage, 1857,
49341 /* 138653 */ GIR_Done,
49342 /* 138654 */ // Label 2815: @138654
49343 /* 138654 */ GIM_Try, /*On fail goto*//*Label 2816*/ GIMT_Encode4(138709), // Rule ID 4343 //
49344 /* 138659 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
49345 /* 138662 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49346 /* 138666 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49347 /* 138670 */ // (frint:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val) => (MVE_VRINTf32X:{ *:[v4f32] } MQPR:{ *:[v4f32] }:$val)
49348 /* 138670 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
49349 /* 138673 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
49350 /* 138677 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
49351 /* 138682 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf32X),
49352 /* 138685 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
49353 /* 138687 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
49354 /* 138689 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
49355 /* 138692 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49356 /* 138698 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49357 /* 138704 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49358 /* 138707 */ GIR_RootConstrainSelectedInstOperands,
49359 /* 138708 */ // GIR_Coverage, 4343,
49360 /* 138708 */ GIR_EraseRootFromParent_Done,
49361 /* 138709 */ // Label 2816: @138709
49362 /* 138709 */ GIM_Reject,
49363 /* 138710 */ // Label 2814: @138710
49364 /* 138710 */ GIM_Reject,
49365 /* 138711 */ // Label 2807: @138711
49366 /* 138711 */ GIM_Try, /*On fail goto*//*Label 2817*/ GIMT_Encode4(138798),
49367 /* 138716 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16,
49368 /* 138719 */ GIM_Try, /*On fail goto*//*Label 2818*/ GIMT_Encode4(138742), // Rule ID 1859 //
49369 /* 138724 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16_HasNEON_HasV8),
49370 /* 138727 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49371 /* 138731 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::QPRRegClassID),
49372 /* 138735 */ // (frint:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm) => (VRINTXNQh:{ *:[v8f16] } QPR:{ *:[v8f16] }:$Vm)
49373 /* 138735 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::VRINTXNQh),
49374 /* 138740 */ GIR_RootConstrainSelectedInstOperands,
49375 /* 138741 */ // GIR_Coverage, 1859,
49376 /* 138741 */ GIR_Done,
49377 /* 138742 */ // Label 2818: @138742
49378 /* 138742 */ GIM_Try, /*On fail goto*//*Label 2819*/ GIMT_Encode4(138797), // Rule ID 4325 //
49379 /* 138747 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEFloat),
49380 /* 138750 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49381 /* 138754 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
49382 /* 138758 */ // (frint:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val) => (MVE_VRINTf16X:{ *:[v8f16] } MQPR:{ *:[v8f16] }:$val)
49383 /* 138758 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v4s32,
49384 /* 138761 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF),
49385 /* 138765 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
49386 /* 138770 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VRINTf16X),
49387 /* 138773 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Qd]
49388 /* 138775 */ GIR_RootToRootCopy, /*OpIdx*/1, // val
49389 /* 138777 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
49390 /* 138780 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49391 /* 138786 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49392 /* 138792 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
49393 /* 138795 */ GIR_RootConstrainSelectedInstOperands,
49394 /* 138796 */ // GIR_Coverage, 4325,
49395 /* 138796 */ GIR_EraseRootFromParent_Done,
49396 /* 138797 */ // Label 2819: @138797
49397 /* 138797 */ GIM_Reject,
49398 /* 138798 */ // Label 2817: @138798
49399 /* 138798 */ GIM_Reject,
49400 /* 138799 */ // Label 2808: @138799
49401 /* 138799 */ GIM_Reject,
49402 /* 138800 */ // Label 77: @138800
49403 /* 138800 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2823*/ GIMT_Encode4(138937),
49404 /* 138811 */ /*GILLT_s16*//*Label 2820*/ GIMT_Encode4(138823),
49405 /* 138815 */ /*GILLT_s32*//*Label 2821*/ GIMT_Encode4(138861),
49406 /* 138819 */ /*GILLT_s64*//*Label 2822*/ GIMT_Encode4(138899),
49407 /* 138823 */ // Label 2820: @138823
49408 /* 138823 */ GIM_Try, /*On fail goto*//*Label 2824*/ GIMT_Encode4(138860), // Rule ID 698 //
49409 /* 138828 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49410 /* 138831 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49411 /* 138834 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49412 /* 138838 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49413 /* 138842 */ // (fnearbyint:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VRINTRH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
49414 /* 138842 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRH),
49415 /* 138845 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49416 /* 138847 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49417 /* 138849 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49418 /* 138852 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49419 /* 138858 */ GIR_RootConstrainSelectedInstOperands,
49420 /* 138859 */ // GIR_Coverage, 698,
49421 /* 138859 */ GIR_EraseRootFromParent_Done,
49422 /* 138860 */ // Label 2824: @138860
49423 /* 138860 */ GIM_Reject,
49424 /* 138861 */ // Label 2821: @138861
49425 /* 138861 */ GIM_Try, /*On fail goto*//*Label 2825*/ GIMT_Encode4(138898), // Rule ID 700 //
49426 /* 138866 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFPARMv8),
49427 /* 138869 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49428 /* 138872 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49429 /* 138876 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49430 /* 138880 */ // (fnearbyint:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VRINTRS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
49431 /* 138880 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRS),
49432 /* 138883 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49433 /* 138885 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49434 /* 138887 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49435 /* 138890 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49436 /* 138896 */ GIR_RootConstrainSelectedInstOperands,
49437 /* 138897 */ // GIR_Coverage, 700,
49438 /* 138897 */ GIR_EraseRootFromParent_Done,
49439 /* 138898 */ // Label 2825: @138898
49440 /* 138898 */ GIM_Reject,
49441 /* 138899 */ // Label 2822: @138899
49442 /* 138899 */ GIM_Try, /*On fail goto*//*Label 2826*/ GIMT_Encode4(138936), // Rule ID 702 //
49443 /* 138904 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasFPARMv8),
49444 /* 138907 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49445 /* 138910 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49446 /* 138914 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49447 /* 138918 */ // (fnearbyint:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VRINTRD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
49448 /* 138918 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VRINTRD),
49449 /* 138921 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49450 /* 138923 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
49451 /* 138925 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49452 /* 138928 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49453 /* 138934 */ GIR_RootConstrainSelectedInstOperands,
49454 /* 138935 */ // GIR_Coverage, 702,
49455 /* 138935 */ GIR_EraseRootFromParent_Done,
49456 /* 138936 */ // Label 2826: @138936
49457 /* 138936 */ GIM_Reject,
49458 /* 138937 */ // Label 2823: @138937
49459 /* 138937 */ GIM_Reject,
49460 /* 138938 */ // Label 78: @138938
49461 /* 138938 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2830*/ GIMT_Encode4(139102),
49462 /* 138949 */ /*GILLT_s16*//*Label 2827*/ GIMT_Encode4(138961),
49463 /* 138953 */ /*GILLT_s32*//*Label 2828*/ GIMT_Encode4(139008),
49464 /* 138957 */ /*GILLT_s64*//*Label 2829*/ GIMT_Encode4(139055),
49465 /* 138961 */ // Label 2827: @138961
49466 /* 138961 */ GIM_Try, /*On fail goto*//*Label 2831*/ GIMT_Encode4(139007), // Rule ID 619 //
49467 /* 138966 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49468 /* 138969 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49469 /* 138972 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
49470 /* 138975 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49471 /* 138979 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49472 /* 138983 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49473 /* 138987 */ // (strict_fadd:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VADDH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49474 /* 138987 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDH),
49475 /* 138990 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49476 /* 138992 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49477 /* 138994 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49478 /* 138996 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49479 /* 138999 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49480 /* 139005 */ GIR_RootConstrainSelectedInstOperands,
49481 /* 139006 */ // GIR_Coverage, 619,
49482 /* 139006 */ GIR_EraseRootFromParent_Done,
49483 /* 139007 */ // Label 2831: @139007
49484 /* 139007 */ GIM_Reject,
49485 /* 139008 */ // Label 2828: @139008
49486 /* 139008 */ GIM_Try, /*On fail goto*//*Label 2832*/ GIMT_Encode4(139054), // Rule ID 617 //
49487 /* 139013 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
49488 /* 139016 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49489 /* 139019 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49490 /* 139022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49491 /* 139026 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49492 /* 139030 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49493 /* 139034 */ // (strict_fadd:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VADDS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49494 /* 139034 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDS),
49495 /* 139037 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49496 /* 139039 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49497 /* 139041 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49498 /* 139043 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49499 /* 139046 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49500 /* 139052 */ GIR_RootConstrainSelectedInstOperands,
49501 /* 139053 */ // GIR_Coverage, 617,
49502 /* 139053 */ GIR_EraseRootFromParent_Done,
49503 /* 139054 */ // Label 2832: @139054
49504 /* 139054 */ GIM_Reject,
49505 /* 139055 */ // Label 2829: @139055
49506 /* 139055 */ GIM_Try, /*On fail goto*//*Label 2833*/ GIMT_Encode4(139101), // Rule ID 615 //
49507 /* 139060 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
49508 /* 139063 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49509 /* 139066 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49510 /* 139069 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49511 /* 139073 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49512 /* 139077 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49513 /* 139081 */ // (strict_fadd:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VADDD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
49514 /* 139081 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VADDD),
49515 /* 139084 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49516 /* 139086 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
49517 /* 139088 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
49518 /* 139090 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49519 /* 139093 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49520 /* 139099 */ GIR_RootConstrainSelectedInstOperands,
49521 /* 139100 */ // GIR_Coverage, 615,
49522 /* 139100 */ GIR_EraseRootFromParent_Done,
49523 /* 139101 */ // Label 2833: @139101
49524 /* 139101 */ GIM_Reject,
49525 /* 139102 */ // Label 2830: @139102
49526 /* 139102 */ GIM_Reject,
49527 /* 139103 */ // Label 79: @139103
49528 /* 139103 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2837*/ GIMT_Encode4(139267),
49529 /* 139114 */ /*GILLT_s16*//*Label 2834*/ GIMT_Encode4(139126),
49530 /* 139118 */ /*GILLT_s32*//*Label 2835*/ GIMT_Encode4(139173),
49531 /* 139122 */ /*GILLT_s64*//*Label 2836*/ GIMT_Encode4(139220),
49532 /* 139126 */ // Label 2834: @139126
49533 /* 139126 */ GIM_Try, /*On fail goto*//*Label 2838*/ GIMT_Encode4(139172), // Rule ID 625 //
49534 /* 139131 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49535 /* 139134 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49536 /* 139137 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
49537 /* 139140 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49538 /* 139144 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49539 /* 139148 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49540 /* 139152 */ // (strict_fsub:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VSUBH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49541 /* 139152 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBH),
49542 /* 139155 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49543 /* 139157 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49544 /* 139159 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49545 /* 139161 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49546 /* 139164 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49547 /* 139170 */ GIR_RootConstrainSelectedInstOperands,
49548 /* 139171 */ // GIR_Coverage, 625,
49549 /* 139171 */ GIR_EraseRootFromParent_Done,
49550 /* 139172 */ // Label 2838: @139172
49551 /* 139172 */ GIM_Reject,
49552 /* 139173 */ // Label 2835: @139173
49553 /* 139173 */ GIM_Try, /*On fail goto*//*Label 2839*/ GIMT_Encode4(139219), // Rule ID 623 //
49554 /* 139178 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
49555 /* 139181 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49556 /* 139184 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49557 /* 139187 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49558 /* 139191 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49559 /* 139195 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49560 /* 139199 */ // (strict_fsub:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VSUBS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49561 /* 139199 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBS),
49562 /* 139202 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49563 /* 139204 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49564 /* 139206 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49565 /* 139208 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49566 /* 139211 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49567 /* 139217 */ GIR_RootConstrainSelectedInstOperands,
49568 /* 139218 */ // GIR_Coverage, 623,
49569 /* 139218 */ GIR_EraseRootFromParent_Done,
49570 /* 139219 */ // Label 2839: @139219
49571 /* 139219 */ GIM_Reject,
49572 /* 139220 */ // Label 2836: @139220
49573 /* 139220 */ GIM_Try, /*On fail goto*//*Label 2840*/ GIMT_Encode4(139266), // Rule ID 621 //
49574 /* 139225 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
49575 /* 139228 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49576 /* 139231 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49577 /* 139234 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49578 /* 139238 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49579 /* 139242 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49580 /* 139246 */ // (strict_fsub:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VSUBD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
49581 /* 139246 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSUBD),
49582 /* 139249 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49583 /* 139251 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
49584 /* 139253 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
49585 /* 139255 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49586 /* 139258 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49587 /* 139264 */ GIR_RootConstrainSelectedInstOperands,
49588 /* 139265 */ // GIR_Coverage, 621,
49589 /* 139265 */ GIR_EraseRootFromParent_Done,
49590 /* 139266 */ // Label 2840: @139266
49591 /* 139266 */ GIM_Reject,
49592 /* 139267 */ // Label 2837: @139267
49593 /* 139267 */ GIM_Reject,
49594 /* 139268 */ // Label 80: @139268
49595 /* 139268 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2844*/ GIMT_Encode4(139432),
49596 /* 139279 */ /*GILLT_s16*//*Label 2841*/ GIMT_Encode4(139291),
49597 /* 139283 */ /*GILLT_s32*//*Label 2842*/ GIMT_Encode4(139338),
49598 /* 139287 */ /*GILLT_s64*//*Label 2843*/ GIMT_Encode4(139385),
49599 /* 139291 */ // Label 2841: @139291
49600 /* 139291 */ GIM_Try, /*On fail goto*//*Label 2845*/ GIMT_Encode4(139337), // Rule ID 637 //
49601 /* 139296 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49602 /* 139299 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49603 /* 139302 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
49604 /* 139305 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49605 /* 139309 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49606 /* 139313 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49607 /* 139317 */ // (strict_fmul:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VMULH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49608 /* 139317 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULH),
49609 /* 139320 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49610 /* 139322 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49611 /* 139324 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49612 /* 139326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49613 /* 139329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49614 /* 139335 */ GIR_RootConstrainSelectedInstOperands,
49615 /* 139336 */ // GIR_Coverage, 637,
49616 /* 139336 */ GIR_EraseRootFromParent_Done,
49617 /* 139337 */ // Label 2845: @139337
49618 /* 139337 */ GIM_Reject,
49619 /* 139338 */ // Label 2842: @139338
49620 /* 139338 */ GIM_Try, /*On fail goto*//*Label 2846*/ GIMT_Encode4(139384), // Rule ID 635 //
49621 /* 139343 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_DontUseNEONForFP_HasVFP2),
49622 /* 139346 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49623 /* 139349 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49624 /* 139352 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49625 /* 139356 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49626 /* 139360 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49627 /* 139364 */ // (strict_fmul:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VMULS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49628 /* 139364 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULS),
49629 /* 139367 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49630 /* 139369 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49631 /* 139371 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49632 /* 139373 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49633 /* 139376 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49634 /* 139382 */ GIR_RootConstrainSelectedInstOperands,
49635 /* 139383 */ // GIR_Coverage, 635,
49636 /* 139383 */ GIR_EraseRootFromParent_Done,
49637 /* 139384 */ // Label 2846: @139384
49638 /* 139384 */ GIM_Reject,
49639 /* 139385 */ // Label 2843: @139385
49640 /* 139385 */ GIM_Try, /*On fail goto*//*Label 2847*/ GIMT_Encode4(139431), // Rule ID 633 //
49641 /* 139390 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
49642 /* 139393 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49643 /* 139396 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49644 /* 139399 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49645 /* 139403 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49646 /* 139407 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49647 /* 139411 */ // (strict_fmul:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VMULD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
49648 /* 139411 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VMULD),
49649 /* 139414 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49650 /* 139416 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
49651 /* 139418 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
49652 /* 139420 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49653 /* 139423 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49654 /* 139429 */ GIR_RootConstrainSelectedInstOperands,
49655 /* 139430 */ // GIR_Coverage, 633,
49656 /* 139430 */ GIR_EraseRootFromParent_Done,
49657 /* 139431 */ // Label 2847: @139431
49658 /* 139431 */ GIM_Reject,
49659 /* 139432 */ // Label 2844: @139432
49660 /* 139432 */ GIM_Reject,
49661 /* 139433 */ // Label 81: @139433
49662 /* 139433 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2851*/ GIMT_Encode4(139597),
49663 /* 139444 */ /*GILLT_s16*//*Label 2848*/ GIMT_Encode4(139456),
49664 /* 139448 */ /*GILLT_s32*//*Label 2849*/ GIMT_Encode4(139503),
49665 /* 139452 */ /*GILLT_s64*//*Label 2850*/ GIMT_Encode4(139550),
49666 /* 139456 */ // Label 2848: @139456
49667 /* 139456 */ GIM_Try, /*On fail goto*//*Label 2852*/ GIMT_Encode4(139502), // Rule ID 631 //
49668 /* 139461 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49669 /* 139464 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49670 /* 139467 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
49671 /* 139470 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49672 /* 139474 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49673 /* 139478 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49674 /* 139482 */ // (strict_fdiv:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm) => (VDIVH:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49675 /* 139482 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVH),
49676 /* 139485 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49677 /* 139487 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49678 /* 139489 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49679 /* 139491 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49680 /* 139494 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49681 /* 139500 */ GIR_RootConstrainSelectedInstOperands,
49682 /* 139501 */ // GIR_Coverage, 631,
49683 /* 139501 */ GIR_EraseRootFromParent_Done,
49684 /* 139502 */ // Label 2852: @139502
49685 /* 139502 */ GIM_Reject,
49686 /* 139503 */ // Label 2849: @139503
49687 /* 139503 */ GIM_Try, /*On fail goto*//*Label 2853*/ GIMT_Encode4(139549), // Rule ID 629 //
49688 /* 139508 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2),
49689 /* 139511 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49690 /* 139514 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49691 /* 139517 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49692 /* 139521 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49693 /* 139525 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49694 /* 139529 */ // (strict_fdiv:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm) => (VDIVS:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49695 /* 139529 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVS),
49696 /* 139532 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49697 /* 139534 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49698 /* 139536 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49699 /* 139538 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49700 /* 139541 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49701 /* 139547 */ GIR_RootConstrainSelectedInstOperands,
49702 /* 139548 */ // GIR_Coverage, 629,
49703 /* 139548 */ GIR_EraseRootFromParent_Done,
49704 /* 139549 */ // Label 2853: @139549
49705 /* 139549 */ GIM_Reject,
49706 /* 139550 */ // Label 2850: @139550
49707 /* 139550 */ GIM_Try, /*On fail goto*//*Label 2854*/ GIMT_Encode4(139596), // Rule ID 627 //
49708 /* 139555 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
49709 /* 139558 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
49710 /* 139561 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
49711 /* 139564 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49712 /* 139568 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49713 /* 139572 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
49714 /* 139576 */ // (strict_fdiv:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm) => (VDIVD:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
49715 /* 139576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VDIVD),
49716 /* 139579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
49717 /* 139581 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
49718 /* 139583 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
49719 /* 139585 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49720 /* 139588 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49721 /* 139594 */ GIR_RootConstrainSelectedInstOperands,
49722 /* 139595 */ // GIR_Coverage, 627,
49723 /* 139595 */ GIR_EraseRootFromParent_Done,
49724 /* 139596 */ // Label 2854: @139596
49725 /* 139596 */ GIM_Reject,
49726 /* 139597 */ // Label 2851: @139597
49727 /* 139597 */ GIM_Reject,
49728 /* 139598 */ // Label 82: @139598
49729 /* 139598 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2858*/ GIMT_Encode4(140782),
49730 /* 139609 */ /*GILLT_s16*//*Label 2855*/ GIMT_Encode4(139621),
49731 /* 139613 */ /*GILLT_s32*//*Label 2856*/ GIMT_Encode4(140008),
49732 /* 139617 */ /*GILLT_s64*//*Label 2857*/ GIMT_Encode4(140395),
49733 /* 139621 */ // Label 2855: @139621
49734 /* 139621 */ GIM_Try, /*On fail goto*//*Label 2859*/ GIMT_Encode4(140007),
49735 /* 139626 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
49736 /* 139629 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16,
49737 /* 139632 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16,
49738 /* 139635 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49739 /* 139639 */ GIM_Try, /*On fail goto*//*Label 2860*/ GIMT_Encode4(139713), // Rule ID 2735 //
49740 /* 139644 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49741 /* 139647 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49742 /* 139651 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49743 /* 139655 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
49744 /* 139659 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49745 /* 139664 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49746 /* 139668 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
49747 /* 139672 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
49748 /* 139676 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
49749 /* 139680 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49750 /* 139685 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
49751 /* 139687 */ // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49752 /* 139687 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
49753 /* 139690 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49754 /* 139692 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
49755 /* 139696 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49756 /* 139700 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49757 /* 139702 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49758 /* 139705 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49759 /* 139711 */ GIR_RootConstrainSelectedInstOperands,
49760 /* 139712 */ // GIR_Coverage, 2735,
49761 /* 139712 */ GIR_EraseRootFromParent_Done,
49762 /* 139713 */ // Label 2860: @139713
49763 /* 139713 */ GIM_Try, /*On fail goto*//*Label 2861*/ GIMT_Encode4(139787), // Rule ID 6274 //
49764 /* 139718 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49765 /* 139721 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49766 /* 139725 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
49767 /* 139729 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49768 /* 139733 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
49769 /* 139737 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49770 /* 139742 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
49771 /* 139746 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
49772 /* 139750 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16,
49773 /* 139754 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49774 /* 139759 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
49775 /* 139761 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49776 /* 139761 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAH),
49777 /* 139764 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49778 /* 139766 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
49779 /* 139770 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49780 /* 139774 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49781 /* 139776 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49782 /* 139779 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49783 /* 139785 */ GIR_RootConstrainSelectedInstOperands,
49784 /* 139786 */ // GIR_Coverage, 6274,
49785 /* 139786 */ GIR_EraseRootFromParent_Done,
49786 /* 139787 */ // Label 2861: @139787
49787 /* 139787 */ GIM_Try, /*On fail goto*//*Label 2862*/ GIMT_Encode4(139846), // Rule ID 2715 //
49788 /* 139792 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49789 /* 139795 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49790 /* 139799 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49791 /* 139803 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
49792 /* 139807 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49793 /* 139812 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49794 /* 139816 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49795 /* 139820 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49796 /* 139822 */ // (strict_fma:{ *:[f16] } (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49797 /* 139822 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
49798 /* 139825 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49799 /* 139827 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
49800 /* 139829 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49801 /* 139833 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49802 /* 139835 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49803 /* 139838 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49804 /* 139844 */ GIR_RootConstrainSelectedInstOperands,
49805 /* 139845 */ // GIR_Coverage, 2715,
49806 /* 139845 */ GIR_EraseRootFromParent_Done,
49807 /* 139846 */ // Label 2862: @139846
49808 /* 139846 */ GIM_Try, /*On fail goto*//*Label 2863*/ GIMT_Encode4(139905), // Rule ID 6268 //
49809 /* 139851 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49810 /* 139854 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49811 /* 139858 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
49812 /* 139862 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49813 /* 139866 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
49814 /* 139870 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49815 /* 139875 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49816 /* 139879 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49817 /* 139881 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sn), HPR:{ *:[f16] }:$Sdin) => (VFMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49818 /* 139881 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSH),
49819 /* 139884 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49820 /* 139886 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
49821 /* 139888 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49822 /* 139892 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49823 /* 139894 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49824 /* 139897 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49825 /* 139903 */ GIR_RootConstrainSelectedInstOperands,
49826 /* 139904 */ // GIR_Coverage, 6268,
49827 /* 139904 */ GIR_EraseRootFromParent_Done,
49828 /* 139905 */ // Label 2863: @139905
49829 /* 139905 */ GIM_Try, /*On fail goto*//*Label 2864*/ GIMT_Encode4(139964), // Rule ID 2749 //
49830 /* 139910 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49831 /* 139913 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49832 /* 139917 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49833 /* 139921 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49834 /* 139925 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49835 /* 139929 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16,
49836 /* 139933 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49837 /* 139938 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49838 /* 139940 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, (fneg:{ *:[f16] } HPR:{ *:[f16] }:$Sdin)) => (VFNMSH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49839 /* 139940 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSH),
49840 /* 139943 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49841 /* 139945 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
49842 /* 139949 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49843 /* 139951 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49844 /* 139953 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49845 /* 139956 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49846 /* 139962 */ GIR_RootConstrainSelectedInstOperands,
49847 /* 139963 */ // GIR_Coverage, 2749,
49848 /* 139963 */ GIR_EraseRootFromParent_Done,
49849 /* 139964 */ // Label 2864: @139964
49850 /* 139964 */ GIM_Try, /*On fail goto*//*Label 2865*/ GIMT_Encode4(140006), // Rule ID 2697 //
49851 /* 139969 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
49852 /* 139972 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49853 /* 139976 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49854 /* 139980 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
49855 /* 139984 */ // (strict_fma:{ *:[f16] } HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm, HPR:{ *:[f16] }:$Sdin) => (VFMAH:{ *:[f16] } HPR:{ *:[f16] }:$Sdin, HPR:{ *:[f16] }:$Sn, HPR:{ *:[f16] }:$Sm)
49856 /* 139984 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAH),
49857 /* 139987 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49858 /* 139989 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
49859 /* 139991 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49860 /* 139993 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49861 /* 139995 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49862 /* 139998 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49863 /* 140004 */ GIR_RootConstrainSelectedInstOperands,
49864 /* 140005 */ // GIR_Coverage, 2697,
49865 /* 140005 */ GIR_EraseRootFromParent_Done,
49866 /* 140006 */ // Label 2865: @140006
49867 /* 140006 */ GIM_Reject,
49868 /* 140007 */ // Label 2859: @140007
49869 /* 140007 */ GIM_Reject,
49870 /* 140008 */ // Label 2856: @140008
49871 /* 140008 */ GIM_Try, /*On fail goto*//*Label 2866*/ GIMT_Encode4(140394),
49872 /* 140013 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
49873 /* 140016 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32,
49874 /* 140019 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32,
49875 /* 140022 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49876 /* 140026 */ GIM_Try, /*On fail goto*//*Label 2867*/ GIMT_Encode4(140100), // Rule ID 2733 //
49877 /* 140031 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
49878 /* 140034 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49879 /* 140038 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49880 /* 140042 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
49881 /* 140046 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49882 /* 140051 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49883 /* 140055 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
49884 /* 140059 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
49885 /* 140063 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
49886 /* 140067 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49887 /* 140072 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
49888 /* 140074 */ // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49889 /* 140074 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
49890 /* 140077 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49891 /* 140079 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
49892 /* 140083 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49893 /* 140087 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49894 /* 140089 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49895 /* 140092 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49896 /* 140098 */ GIR_RootConstrainSelectedInstOperands,
49897 /* 140099 */ // GIR_Coverage, 2733,
49898 /* 140099 */ GIR_EraseRootFromParent_Done,
49899 /* 140100 */ // Label 2867: @140100
49900 /* 140100 */ GIM_Try, /*On fail goto*//*Label 2868*/ GIMT_Encode4(140174), // Rule ID 6272 //
49901 /* 140105 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
49902 /* 140108 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49903 /* 140112 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
49904 /* 140116 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49905 /* 140120 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
49906 /* 140124 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49907 /* 140129 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
49908 /* 140133 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
49909 /* 140137 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32,
49910 /* 140141 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49911 /* 140146 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
49912 /* 140148 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49913 /* 140148 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAS),
49914 /* 140151 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49915 /* 140153 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Sdin
49916 /* 140157 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49917 /* 140161 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49918 /* 140163 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49919 /* 140166 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49920 /* 140172 */ GIR_RootConstrainSelectedInstOperands,
49921 /* 140173 */ // GIR_Coverage, 6272,
49922 /* 140173 */ GIR_EraseRootFromParent_Done,
49923 /* 140174 */ // Label 2868: @140174
49924 /* 140174 */ GIM_Try, /*On fail goto*//*Label 2869*/ GIMT_Encode4(140233), // Rule ID 2713 //
49925 /* 140179 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
49926 /* 140182 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
49927 /* 140186 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49928 /* 140190 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
49929 /* 140194 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49930 /* 140199 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49931 /* 140203 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49932 /* 140207 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49933 /* 140209 */ // (strict_fma:{ *:[f32] } (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49934 /* 140209 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
49935 /* 140212 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49936 /* 140214 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
49937 /* 140216 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49938 /* 140220 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49939 /* 140222 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49940 /* 140225 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49941 /* 140231 */ GIR_RootConstrainSelectedInstOperands,
49942 /* 140232 */ // GIR_Coverage, 2713,
49943 /* 140232 */ GIR_EraseRootFromParent_Done,
49944 /* 140233 */ // Label 2869: @140233
49945 /* 140233 */ GIM_Try, /*On fail goto*//*Label 2870*/ GIMT_Encode4(140292), // Rule ID 6266 //
49946 /* 140238 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
49947 /* 140241 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49948 /* 140245 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
49949 /* 140249 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49950 /* 140253 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
49951 /* 140257 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49952 /* 140262 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49953 /* 140266 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49954 /* 140268 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sn), SPR:{ *:[f32] }:$Sdin) => (VFMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49955 /* 140268 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSS),
49956 /* 140271 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49957 /* 140273 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
49958 /* 140275 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sn
49959 /* 140279 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
49960 /* 140281 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49961 /* 140284 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49962 /* 140290 */ GIR_RootConstrainSelectedInstOperands,
49963 /* 140291 */ // GIR_Coverage, 6266,
49964 /* 140291 */ GIR_EraseRootFromParent_Done,
49965 /* 140292 */ // Label 2870: @140292
49966 /* 140292 */ GIM_Try, /*On fail goto*//*Label 2871*/ GIMT_Encode4(140351), // Rule ID 2747 //
49967 /* 140297 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
49968 /* 140300 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49969 /* 140304 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49970 /* 140308 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
49971 /* 140312 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
49972 /* 140316 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32,
49973 /* 140320 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49974 /* 140325 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
49975 /* 140327 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, (fneg:{ *:[f32] } SPR:{ *:[f32] }:$Sdin)) => (VFNMSS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49976 /* 140327 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSS),
49977 /* 140330 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49978 /* 140332 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Sdin
49979 /* 140336 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49980 /* 140338 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49981 /* 140340 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49982 /* 140343 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
49983 /* 140349 */ GIR_RootConstrainSelectedInstOperands,
49984 /* 140350 */ // GIR_Coverage, 2747,
49985 /* 140350 */ GIR_EraseRootFromParent_Done,
49986 /* 140351 */ // Label 2871: @140351
49987 /* 140351 */ GIM_Try, /*On fail goto*//*Label 2872*/ GIMT_Encode4(140393), // Rule ID 2695 //
49988 /* 140356 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP4),
49989 /* 140359 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49990 /* 140363 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49991 /* 140367 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
49992 /* 140371 */ // (strict_fma:{ *:[f32] } SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm, SPR:{ *:[f32] }:$Sdin) => (VFMAS:{ *:[f32] } SPR:{ *:[f32] }:$Sdin, SPR:{ *:[f32] }:$Sn, SPR:{ *:[f32] }:$Sm)
49993 /* 140371 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAS),
49994 /* 140374 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
49995 /* 140376 */ GIR_RootToRootCopy, /*OpIdx*/3, // Sdin
49996 /* 140378 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sn
49997 /* 140380 */ GIR_RootToRootCopy, /*OpIdx*/2, // Sm
49998 /* 140382 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
49999 /* 140385 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50000 /* 140391 */ GIR_RootConstrainSelectedInstOperands,
50001 /* 140392 */ // GIR_Coverage, 2695,
50002 /* 140392 */ GIR_EraseRootFromParent_Done,
50003 /* 140393 */ // Label 2872: @140393
50004 /* 140393 */ GIM_Reject,
50005 /* 140394 */ // Label 2866: @140394
50006 /* 140394 */ GIM_Reject,
50007 /* 140395 */ // Label 2857: @140395
50008 /* 140395 */ GIM_Try, /*On fail goto*//*Label 2873*/ GIMT_Encode4(140781),
50009 /* 140400 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
50010 /* 140403 */ GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64,
50011 /* 140406 */ GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64,
50012 /* 140409 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50013 /* 140413 */ GIM_Try, /*On fail goto*//*Label 2874*/ GIMT_Encode4(140487), // Rule ID 2731 //
50014 /* 140418 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
50015 /* 140421 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50016 /* 140425 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
50017 /* 140429 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
50018 /* 140433 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50019 /* 140438 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50020 /* 140442 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
50021 /* 140446 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
50022 /* 140450 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
50023 /* 140454 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50024 /* 140459 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
50025 /* 140461 */ // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
50026 /* 140461 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
50027 /* 140464 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
50028 /* 140466 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
50029 /* 140470 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
50030 /* 140474 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
50031 /* 140476 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
50032 /* 140479 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50033 /* 140485 */ GIR_RootConstrainSelectedInstOperands,
50034 /* 140486 */ // GIR_Coverage, 2731,
50035 /* 140486 */ GIR_EraseRootFromParent_Done,
50036 /* 140487 */ // Label 2874: @140487
50037 /* 140487 */ GIM_Try, /*On fail goto*//*Label 2875*/ GIMT_Encode4(140561), // Rule ID 6270 //
50038 /* 140492 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
50039 /* 140495 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50040 /* 140499 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
50041 /* 140503 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
50042 /* 140507 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
50043 /* 140511 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50044 /* 140516 */ GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/3, // MIs[2]
50045 /* 140520 */ GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FNEG),
50046 /* 140524 */ GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64,
50047 /* 140528 */ GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50048 /* 140533 */ GIM_CheckIsSafeToFold, /*NumInsns*/2,
50049 /* 140535 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
50050 /* 140535 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMAD),
50051 /* 140538 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
50052 /* 140540 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // Ddin
50053 /* 140544 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
50054 /* 140548 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
50055 /* 140550 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
50056 /* 140553 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50057 /* 140559 */ GIR_RootConstrainSelectedInstOperands,
50058 /* 140560 */ // GIR_Coverage, 6270,
50059 /* 140560 */ GIR_EraseRootFromParent_Done,
50060 /* 140561 */ // Label 2875: @140561
50061 /* 140561 */ GIM_Try, /*On fail goto*//*Label 2876*/ GIMT_Encode4(140620), // Rule ID 2711 //
50062 /* 140566 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
50063 /* 140569 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50064 /* 140573 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
50065 /* 140577 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
50066 /* 140581 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50067 /* 140586 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50068 /* 140590 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50069 /* 140594 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50070 /* 140596 */ // (strict_fma:{ *:[f64] } (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
50071 /* 140596 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
50072 /* 140599 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
50073 /* 140601 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
50074 /* 140603 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
50075 /* 140607 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
50076 /* 140609 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
50077 /* 140612 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50078 /* 140618 */ GIR_RootConstrainSelectedInstOperands,
50079 /* 140619 */ // GIR_Coverage, 2711,
50080 /* 140619 */ GIR_EraseRootFromParent_Done,
50081 /* 140620 */ // Label 2876: @140620
50082 /* 140620 */ GIM_Try, /*On fail goto*//*Label 2877*/ GIMT_Encode4(140679), // Rule ID 6264 //
50083 /* 140625 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
50084 /* 140628 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50085 /* 140632 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
50086 /* 140636 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
50087 /* 140640 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
50088 /* 140644 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50089 /* 140649 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50090 /* 140653 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50091 /* 140655 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Dn), DPR:{ *:[f64] }:$Ddin) => (VFMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
50092 /* 140655 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMSD),
50093 /* 140658 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
50094 /* 140660 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
50095 /* 140662 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Dn
50096 /* 140666 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
50097 /* 140668 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
50098 /* 140671 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50099 /* 140677 */ GIR_RootConstrainSelectedInstOperands,
50100 /* 140678 */ // GIR_Coverage, 6264,
50101 /* 140678 */ GIR_EraseRootFromParent_Done,
50102 /* 140679 */ // Label 2877: @140679
50103 /* 140679 */ GIM_Try, /*On fail goto*//*Label 2878*/ GIMT_Encode4(140738), // Rule ID 2745 //
50104 /* 140684 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
50105 /* 140687 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50106 /* 140691 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50107 /* 140695 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
50108 /* 140699 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG),
50109 /* 140703 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64,
50110 /* 140707 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50111 /* 140712 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50112 /* 140714 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, (fneg:{ *:[f64] } DPR:{ *:[f64] }:$Ddin)) => (VFNMSD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
50113 /* 140714 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFNMSD),
50114 /* 140717 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
50115 /* 140719 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // Ddin
50116 /* 140723 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
50117 /* 140725 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
50118 /* 140727 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
50119 /* 140730 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50120 /* 140736 */ GIR_RootConstrainSelectedInstOperands,
50121 /* 140737 */ // GIR_Coverage, 2745,
50122 /* 140737 */ GIR_EraseRootFromParent_Done,
50123 /* 140738 */ // Label 2878: @140738
50124 /* 140738 */ GIM_Try, /*On fail goto*//*Label 2879*/ GIMT_Encode4(140780), // Rule ID 2693 //
50125 /* 140743 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP4),
50126 /* 140746 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50127 /* 140750 */ GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50128 /* 140754 */ GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50129 /* 140758 */ // (strict_fma:{ *:[f64] } DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm, DPR:{ *:[f64] }:$Ddin) => (VFMAD:{ *:[f64] } DPR:{ *:[f64] }:$Ddin, DPR:{ *:[f64] }:$Dn, DPR:{ *:[f64] }:$Dm)
50130 /* 140758 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VFMAD),
50131 /* 140761 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
50132 /* 140763 */ GIR_RootToRootCopy, /*OpIdx*/3, // Ddin
50133 /* 140765 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dn
50134 /* 140767 */ GIR_RootToRootCopy, /*OpIdx*/2, // Dm
50135 /* 140769 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
50136 /* 140772 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50137 /* 140778 */ GIR_RootConstrainSelectedInstOperands,
50138 /* 140779 */ // GIR_Coverage, 2693,
50139 /* 140779 */ GIR_EraseRootFromParent_Done,
50140 /* 140780 */ // Label 2879: @140780
50141 /* 140780 */ GIM_Reject,
50142 /* 140781 */ // Label 2873: @140781
50143 /* 140781 */ GIM_Reject,
50144 /* 140782 */ // Label 2858: @140782
50145 /* 140782 */ GIM_Reject,
50146 /* 140783 */ // Label 83: @140783
50147 /* 140783 */ GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(3), /*)*//*default:*//*Label 2883*/ GIMT_Encode4(140920),
50148 /* 140794 */ /*GILLT_s16*//*Label 2880*/ GIMT_Encode4(140806),
50149 /* 140798 */ /*GILLT_s32*//*Label 2881*/ GIMT_Encode4(140844),
50150 /* 140802 */ /*GILLT_s64*//*Label 2882*/ GIMT_Encode4(140882),
50151 /* 140806 */ // Label 2880: @140806
50152 /* 140806 */ GIM_Try, /*On fail goto*//*Label 2884*/ GIMT_Encode4(140843), // Rule ID 737 //
50153 /* 140811 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFullFP16),
50154 /* 140814 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16,
50155 /* 140817 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
50156 /* 140821 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::HPRRegClassID),
50157 /* 140825 */ // (strict_fsqrt:{ *:[f16] } HPR:{ *:[f16] }:$Sm) => (VSQRTH:{ *:[f16] } HPR:{ *:[f16] }:$Sm)
50158 /* 140825 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTH),
50159 /* 140828 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
50160 /* 140830 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
50161 /* 140832 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
50162 /* 140835 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50163 /* 140841 */ GIR_RootConstrainSelectedInstOperands,
50164 /* 140842 */ // GIR_Coverage, 737,
50165 /* 140842 */ GIR_EraseRootFromParent_Done,
50166 /* 140843 */ // Label 2884: @140843
50167 /* 140843 */ GIM_Reject,
50168 /* 140844 */ // Label 2881: @140844
50169 /* 140844 */ GIM_Try, /*On fail goto*//*Label 2885*/ GIMT_Encode4(140881), // Rule ID 735 //
50170 /* 140849 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVFP2),
50171 /* 140852 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32,
50172 /* 140855 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
50173 /* 140859 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::SPRRegClassID),
50174 /* 140863 */ // (strict_fsqrt:{ *:[f32] } SPR:{ *:[f32] }:$Sm) => (VSQRTS:{ *:[f32] } SPR:{ *:[f32] }:$Sm)
50175 /* 140863 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTS),
50176 /* 140866 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Sd]
50177 /* 140868 */ GIR_RootToRootCopy, /*OpIdx*/1, // Sm
50178 /* 140870 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
50179 /* 140873 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50180 /* 140879 */ GIR_RootConstrainSelectedInstOperands,
50181 /* 140880 */ // GIR_Coverage, 735,
50182 /* 140880 */ GIR_EraseRootFromParent_Done,
50183 /* 140881 */ // Label 2885: @140881
50184 /* 140881 */ GIM_Reject,
50185 /* 140882 */ // Label 2882: @140882
50186 /* 140882 */ GIM_Try, /*On fail goto*//*Label 2886*/ GIMT_Encode4(140919), // Rule ID 733 //
50187 /* 140887 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDPVFP_HasVFP2),
50188 /* 140890 */ GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64,
50189 /* 140893 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50190 /* 140897 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::DPRRegClassID),
50191 /* 140901 */ // (strict_fsqrt:{ *:[f64] } DPR:{ *:[f64] }:$Dm) => (VSQRTD:{ *:[f64] } DPR:{ *:[f64] }:$Dm)
50192 /* 140901 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::VSQRTD),
50193 /* 140904 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Dd]
50194 /* 140906 */ GIR_RootToRootCopy, /*OpIdx*/1, // Dm
50195 /* 140908 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/14,
50196 /* 140911 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50197 /* 140917 */ GIR_RootConstrainSelectedInstOperands,
50198 /* 140918 */ // GIR_Coverage, 733,
50199 /* 140918 */ GIR_EraseRootFromParent_Done,
50200 /* 140919 */ // Label 2886: @140919
50201 /* 140919 */ GIM_Reject,
50202 /* 140920 */ // Label 2883: @140920
50203 /* 140920 */ GIM_Reject,
50204 /* 140921 */ // Label 84: @140921
50205 /* 140921 */ GIM_Try, /*On fail goto*//*Label 2887*/ GIMT_Encode4(140936), // Rule ID 12 //
50206 /* 140926 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM),
50207 /* 140929 */ // (trap) => (TRAP)
50208 /* 140929 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::TRAP),
50209 /* 140934 */ GIR_RootConstrainSelectedInstOperands,
50210 /* 140935 */ // GIR_Coverage, 12,
50211 /* 140935 */ GIR_Done,
50212 /* 140936 */ // Label 2887: @140936
50213 /* 140936 */ GIM_Try, /*On fail goto*//*Label 2888*/ GIMT_Encode4(140951), // Rule ID 284 //
50214 /* 140941 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb),
50215 /* 140944 */ // (trap) => (tTRAP)
50216 /* 140944 */ GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(ARM::tTRAP),
50217 /* 140949 */ GIR_RootConstrainSelectedInstOperands,
50218 /* 140950 */ // GIR_Coverage, 284,
50219 /* 140950 */ GIR_Done,
50220 /* 140951 */ // Label 2888: @140951
50221 /* 140951 */ GIM_Reject,
50222 /* 140952 */ // Label 85: @140952
50223 /* 140952 */ GIM_Try, /*On fail goto*//*Label 2889*/ GIMT_Encode4(140968), // Rule ID 1999 //
50224 /* 140957 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsARM),
50225 /* 140960 */ // (debugtrap) => (BKPT 0:{ *:[i32] })
50226 /* 140960 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::BKPT),
50227 /* 140963 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50228 /* 140966 */ GIR_RootConstrainSelectedInstOperands,
50229 /* 140967 */ // GIR_Coverage, 1999,
50230 /* 140967 */ GIR_EraseRootFromParent_Done,
50231 /* 140968 */ // Label 2889: @140968
50232 /* 140968 */ GIM_Try, /*On fail goto*//*Label 2890*/ GIMT_Encode4(140995), // Rule ID 2000 //
50233 /* 140973 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsARM_NoV5T),
50234 /* 140976 */ // (debugtrap) => (UDF 254:{ *:[i32] })
50235 /* 140976 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::UDF),
50236 /* 140979 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254),
50237 /* 140989 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
50238 /* 140993 */ GIR_RootConstrainSelectedInstOperands,
50239 /* 140994 */ // GIR_Coverage, 2000,
50240 /* 140994 */ GIR_EraseRootFromParent_Done,
50241 /* 140995 */ // Label 2890: @140995
50242 /* 140995 */ GIM_Try, /*On fail goto*//*Label 2891*/ GIMT_Encode4(141011), // Rule ID 2185 //
50243 /* 141000 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasV5T_IsThumb),
50244 /* 141003 */ // (debugtrap) => (tBKPT 0:{ *:[i32] })
50245 /* 141003 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tBKPT),
50246 /* 141006 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50247 /* 141009 */ GIR_RootConstrainSelectedInstOperands,
50248 /* 141010 */ // GIR_Coverage, 2185,
50249 /* 141010 */ GIR_EraseRootFromParent_Done,
50250 /* 141011 */ // Label 2891: @141011
50251 /* 141011 */ GIM_Try, /*On fail goto*//*Label 2892*/ GIMT_Encode4(141038), // Rule ID 2186 //
50252 /* 141016 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_IsThumb_NoV5T),
50253 /* 141019 */ // (debugtrap) => (tUDF 254:{ *:[i32] })
50254 /* 141019 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::tUDF),
50255 /* 141022 */ GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(254),
50256 /* 141032 */ GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0,
50257 /* 141036 */ GIR_RootConstrainSelectedInstOperands,
50258 /* 141037 */ // GIR_Coverage, 2186,
50259 /* 141037 */ GIR_EraseRootFromParent_Done,
50260 /* 141038 */ // Label 2892: @141038
50261 /* 141038 */ GIM_Reject,
50262 /* 141039 */ // Label 86: @141039
50263 /* 141039 */ GIM_Try, /*On fail goto*//*Label 2893*/ GIMT_Encode4(141459),
50264 /* 141044 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
50265 /* 141047 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2897*/ GIMT_Encode4(141345),
50266 /* 141058 */ /*GILLT_v4s32*//*Label 2894*/ GIMT_Encode4(141090), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
50267 /* 141074 */ /*GILLT_v8s16*//*Label 2895*/ GIMT_Encode4(141161), GIMT_Encode4(0), GIMT_Encode4(0),
50268 /* 141086 */ /*GILLT_v16s8*//*Label 2896*/ GIMT_Encode4(141232),
50269 /* 141090 */ // Label 2894: @141090
50270 /* 141090 */ GIM_Try, /*On fail goto*//*Label 2898*/ GIMT_Encode4(141160), // Rule ID 3593 //
50271 /* 141095 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50272 /* 141098 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
50273 /* 141102 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50274 /* 141106 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
50275 /* 141110 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s32,
50276 /* 141114 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s32,
50277 /* 141118 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50278 /* 141123 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50279 /* 141128 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50280 /* 141130 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v4i32] } MQPR:{ *:[v4i32] }:$src1, MQPR:{ *:[v4i32] }:$src2)) => (MVE_VMLADAVu32:{ *:[i32] } ?:{ *:[v4i32] }:$src1, ?:{ *:[v4i32] }:$src2)
50281 /* 141130 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu32),
50282 /* 141133 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50283 /* 141135 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
50284 /* 141139 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
50285 /* 141143 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50286 /* 141146 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50287 /* 141152 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50288 /* 141158 */ GIR_RootConstrainSelectedInstOperands,
50289 /* 141159 */ // GIR_Coverage, 3593,
50290 /* 141159 */ GIR_EraseRootFromParent_Done,
50291 /* 141160 */ // Label 2898: @141160
50292 /* 141160 */ GIM_Reject,
50293 /* 141161 */ // Label 2895: @141161
50294 /* 141161 */ GIM_Try, /*On fail goto*//*Label 2899*/ GIMT_Encode4(141231), // Rule ID 3594 //
50295 /* 141166 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50296 /* 141169 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
50297 /* 141173 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50298 /* 141177 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
50299 /* 141181 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v8s16,
50300 /* 141185 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v8s16,
50301 /* 141189 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50302 /* 141194 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50303 /* 141199 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50304 /* 141201 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v8i16] } MQPR:{ *:[v8i16] }:$src1, MQPR:{ *:[v8i16] }:$src2)) => (MVE_VMLADAVu16:{ *:[i32] } ?:{ *:[v8i16] }:$src1, ?:{ *:[v8i16] }:$src2)
50305 /* 141201 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu16),
50306 /* 141204 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50307 /* 141206 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
50308 /* 141210 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
50309 /* 141214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50310 /* 141217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50311 /* 141223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50312 /* 141229 */ GIR_RootConstrainSelectedInstOperands,
50313 /* 141230 */ // GIR_Coverage, 3594,
50314 /* 141230 */ GIR_EraseRootFromParent_Done,
50315 /* 141231 */ // Label 2899: @141231
50316 /* 141231 */ GIM_Reject,
50317 /* 141232 */ // Label 2896: @141232
50318 /* 141232 */ GIM_Try, /*On fail goto*//*Label 2900*/ GIMT_Encode4(141344),
50319 /* 141237 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
50320 /* 141241 */ GIM_Try, /*On fail goto*//*Label 2901*/ GIMT_Encode4(141307), // Rule ID 3597 //
50321 /* 141246 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50322 /* 141249 */ GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
50323 /* 141253 */ GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL),
50324 /* 141257 */ GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v16s8,
50325 /* 141261 */ GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v16s8,
50326 /* 141265 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50327 /* 141270 */ GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50328 /* 141275 */ GIM_CheckIsSafeToFold, /*NumInsns*/1,
50329 /* 141277 */ // (vecreduce_add:{ *:[i32] } (mul:{ *:[v16i8] } MQPR:{ *:[v16i8] }:$src1, MQPR:{ *:[v16i8] }:$src2)) => (MVE_VMLADAVu8:{ *:[i32] } ?:{ *:[v16i8] }:$src1, ?:{ *:[v16i8] }:$src2)
50330 /* 141277 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMLADAVu8),
50331 /* 141280 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50332 /* 141282 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1
50333 /* 141286 */ GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2
50334 /* 141290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50335 /* 141293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50336 /* 141299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50337 /* 141305 */ GIR_RootConstrainSelectedInstOperands,
50338 /* 141306 */ // GIR_Coverage, 3597,
50339 /* 141306 */ GIR_EraseRootFromParent_Done,
50340 /* 141307 */ // Label 2901: @141307
50341 /* 141307 */ GIM_Try, /*On fail goto*//*Label 2902*/ GIMT_Encode4(141343), // Rule ID 3401 //
50342 /* 141312 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50343 /* 141315 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50344 /* 141319 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v16i8] }:$vec) => (MVE_VADDVu8no_acc:{ *:[i32] } ?:{ *:[v16i8] }:$vec)
50345 /* 141319 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu8no_acc),
50346 /* 141322 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
50347 /* 141324 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec
50348 /* 141326 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50349 /* 141329 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50350 /* 141335 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50351 /* 141341 */ GIR_RootConstrainSelectedInstOperands,
50352 /* 141342 */ // GIR_Coverage, 3401,
50353 /* 141342 */ GIR_EraseRootFromParent_Done,
50354 /* 141343 */ // Label 2902: @141343
50355 /* 141343 */ GIM_Reject,
50356 /* 141344 */ // Label 2900: @141344
50357 /* 141344 */ GIM_Reject,
50358 /* 141345 */ // Label 2897: @141345
50359 /* 141345 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 2905*/ GIMT_Encode4(141458),
50360 /* 141356 */ /*GILLT_v4s32*//*Label 2903*/ GIMT_Encode4(141376), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
50361 /* 141372 */ /*GILLT_v8s16*//*Label 2904*/ GIMT_Encode4(141417),
50362 /* 141376 */ // Label 2903: @141376
50363 /* 141376 */ GIM_Try, /*On fail goto*//*Label 2906*/ GIMT_Encode4(141416), // Rule ID 3439 //
50364 /* 141381 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50365 /* 141384 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
50366 /* 141388 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50367 /* 141392 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v4i32] }:$vec) => (MVE_VADDVu32no_acc:{ *:[i32] } ?:{ *:[v4i32] }:$vec)
50368 /* 141392 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu32no_acc),
50369 /* 141395 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
50370 /* 141397 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec
50371 /* 141399 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50372 /* 141402 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50373 /* 141408 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50374 /* 141414 */ GIR_RootConstrainSelectedInstOperands,
50375 /* 141415 */ // GIR_Coverage, 3439,
50376 /* 141415 */ GIR_EraseRootFromParent_Done,
50377 /* 141416 */ // Label 2906: @141416
50378 /* 141416 */ GIM_Reject,
50379 /* 141417 */ // Label 2904: @141417
50380 /* 141417 */ GIM_Try, /*On fail goto*//*Label 2907*/ GIMT_Encode4(141457), // Rule ID 3429 //
50381 /* 141422 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50382 /* 141425 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::tGPREvenRegClassID),
50383 /* 141429 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50384 /* 141433 */ // (vecreduce_add:{ *:[i32] } MQPR:{ *:[v8i16] }:$vec) => (MVE_VADDVu16no_acc:{ *:[i32] } ?:{ *:[v8i16] }:$vec)
50385 /* 141433 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VADDVu16no_acc),
50386 /* 141436 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[Rda]
50387 /* 141438 */ GIR_RootToRootCopy, /*OpIdx*/1, // vec
50388 /* 141440 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50389 /* 141443 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50390 /* 141449 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50391 /* 141455 */ GIR_RootConstrainSelectedInstOperands,
50392 /* 141456 */ // GIR_Coverage, 3429,
50393 /* 141456 */ GIR_EraseRootFromParent_Done,
50394 /* 141457 */ // Label 2907: @141457
50395 /* 141457 */ GIM_Reject,
50396 /* 141458 */ // Label 2905: @141458
50397 /* 141458 */ GIM_Reject,
50398 /* 141459 */ // Label 2893: @141459
50399 /* 141459 */ GIM_Reject,
50400 /* 141460 */ // Label 87: @141460
50401 /* 141460 */ GIM_Try, /*On fail goto*//*Label 2908*/ GIMT_Encode4(141739),
50402 /* 141465 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
50403 /* 141468 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2912*/ GIMT_Encode4(141738),
50404 /* 141479 */ /*GILLT_v4s32*//*Label 2909*/ GIMT_Encode4(141511), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
50405 /* 141495 */ /*GILLT_v8s16*//*Label 2910*/ GIMT_Encode4(141594), GIMT_Encode4(0), GIMT_Encode4(0),
50406 /* 141507 */ /*GILLT_v16s8*//*Label 2911*/ GIMT_Encode4(141662),
50407 /* 141511 */ // Label 2909: @141511
50408 /* 141511 */ GIM_Try, /*On fail goto*//*Label 2913*/ GIMT_Encode4(141593), // Rule ID 3499 //
50409 /* 141516 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50410 /* 141519 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50411 /* 141523 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50412 /* 141527 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVs32:{ *:[i32] } (t2MOVi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
50413 /* 141527 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50414 /* 141530 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
50415 /* 141534 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50416 /* 141539 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744071562067968u),
50417 /* 141549 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50418 /* 141552 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50419 /* 141558 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50420 /* 141564 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50421 /* 141566 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs32),
50422 /* 141569 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50423 /* 141571 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50424 /* 141574 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50425 /* 141576 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50426 /* 141579 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50427 /* 141585 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50428 /* 141591 */ GIR_RootConstrainSelectedInstOperands,
50429 /* 141592 */ // GIR_Coverage, 3499,
50430 /* 141592 */ GIR_EraseRootFromParent_Done,
50431 /* 141593 */ // Label 2913: @141593
50432 /* 141593 */ GIM_Reject,
50433 /* 141594 */ // Label 2910: @141594
50434 /* 141594 */ GIM_Try, /*On fail goto*//*Label 2914*/ GIMT_Encode4(141661), // Rule ID 3498 //
50435 /* 141599 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50436 /* 141602 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50437 /* 141606 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50438 /* 141610 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVs16:{ *:[i32] } (t2MOVi32imm:{ *:[i32] } -32768:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
50439 /* 141610 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50440 /* 141613 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi32imm),
50441 /* 141617 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50442 /* 141622 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744073709518848u),
50443 /* 141632 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50444 /* 141634 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs16),
50445 /* 141637 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50446 /* 141639 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50447 /* 141642 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50448 /* 141644 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50449 /* 141647 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50450 /* 141653 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50451 /* 141659 */ GIR_RootConstrainSelectedInstOperands,
50452 /* 141660 */ // GIR_Coverage, 3498,
50453 /* 141660 */ GIR_EraseRootFromParent_Done,
50454 /* 141661 */ // Label 2914: @141661
50455 /* 141661 */ GIM_Reject,
50456 /* 141662 */ // Label 2911: @141662
50457 /* 141662 */ GIM_Try, /*On fail goto*//*Label 2915*/ GIMT_Encode4(141737), // Rule ID 3497 //
50458 /* 141667 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50459 /* 141670 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50460 /* 141674 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50461 /* 141678 */ // (vecreduce_smax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVs8:{ *:[i32] } (t2MVNi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
50462 /* 141678 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50463 /* 141681 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
50464 /* 141685 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50465 /* 141690 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127,
50466 /* 141693 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50467 /* 141696 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50468 /* 141702 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50469 /* 141708 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50470 /* 141710 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVs8),
50471 /* 141713 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50472 /* 141715 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50473 /* 141718 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50474 /* 141720 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50475 /* 141723 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50476 /* 141729 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50477 /* 141735 */ GIR_RootConstrainSelectedInstOperands,
50478 /* 141736 */ // GIR_Coverage, 3497,
50479 /* 141736 */ GIR_EraseRootFromParent_Done,
50480 /* 141737 */ // Label 2915: @141737
50481 /* 141737 */ GIM_Reject,
50482 /* 141738 */ // Label 2912: @141738
50483 /* 141738 */ GIM_Reject,
50484 /* 141739 */ // Label 2908: @141739
50485 /* 141739 */ GIM_Reject,
50486 /* 141740 */ // Label 88: @141740
50487 /* 141740 */ GIM_Try, /*On fail goto*//*Label 2916*/ GIMT_Encode4(142028),
50488 /* 141745 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
50489 /* 141748 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2920*/ GIMT_Encode4(142027),
50490 /* 141759 */ /*GILLT_v4s32*//*Label 2917*/ GIMT_Encode4(141791), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
50491 /* 141775 */ /*GILLT_v8s16*//*Label 2918*/ GIMT_Encode4(141874), GIMT_Encode4(0), GIMT_Encode4(0),
50492 /* 141787 */ /*GILLT_v16s8*//*Label 2919*/ GIMT_Encode4(141951),
50493 /* 141791 */ // Label 2917: @141791
50494 /* 141791 */ GIM_Try, /*On fail goto*//*Label 2921*/ GIMT_Encode4(141873), // Rule ID 3505 //
50495 /* 141796 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50496 /* 141799 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50497 /* 141803 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50498 /* 141807 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVs32:{ *:[i32] } (t2MVNi:{ *:[i32] } -2147483648:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
50499 /* 141807 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50500 /* 141810 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MVNi),
50501 /* 141814 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50502 /* 141819 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(18446744071562067968u),
50503 /* 141829 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50504 /* 141832 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50505 /* 141838 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50506 /* 141844 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50507 /* 141846 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs32),
50508 /* 141849 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50509 /* 141851 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50510 /* 141854 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50511 /* 141856 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50512 /* 141859 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50513 /* 141865 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50514 /* 141871 */ GIR_RootConstrainSelectedInstOperands,
50515 /* 141872 */ // GIR_Coverage, 3505,
50516 /* 141872 */ GIR_EraseRootFromParent_Done,
50517 /* 141873 */ // Label 2921: @141873
50518 /* 141873 */ GIM_Reject,
50519 /* 141874 */ // Label 2918: @141874
50520 /* 141874 */ GIM_Try, /*On fail goto*//*Label 2922*/ GIMT_Encode4(141950), // Rule ID 3504 //
50521 /* 141879 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50522 /* 141882 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50523 /* 141886 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50524 /* 141890 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVs16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 32767:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
50525 /* 141890 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50526 /* 141893 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16),
50527 /* 141897 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50528 /* 141902 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767),
50529 /* 141912 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50530 /* 141915 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50531 /* 141921 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50532 /* 141923 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs16),
50533 /* 141926 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50534 /* 141928 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50535 /* 141931 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50536 /* 141933 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50537 /* 141936 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50538 /* 141942 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50539 /* 141948 */ GIR_RootConstrainSelectedInstOperands,
50540 /* 141949 */ // GIR_Coverage, 3504,
50541 /* 141949 */ GIR_EraseRootFromParent_Done,
50542 /* 141950 */ // Label 2922: @141950
50543 /* 141950 */ GIM_Reject,
50544 /* 141951 */ // Label 2919: @141951
50545 /* 141951 */ GIM_Try, /*On fail goto*//*Label 2923*/ GIMT_Encode4(142026), // Rule ID 3503 //
50546 /* 141956 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50547 /* 141959 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50548 /* 141963 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50549 /* 141967 */ // (vecreduce_smin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVs8:{ *:[i32] } (t2MOVi:{ *:[i32] } 127:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
50550 /* 141967 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50551 /* 141970 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
50552 /* 141974 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50553 /* 141979 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/127,
50554 /* 141982 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50555 /* 141985 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50556 /* 141991 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50557 /* 141997 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50558 /* 141999 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVs8),
50559 /* 142002 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50560 /* 142004 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50561 /* 142007 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50562 /* 142009 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50563 /* 142012 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50564 /* 142018 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50565 /* 142024 */ GIR_RootConstrainSelectedInstOperands,
50566 /* 142025 */ // GIR_Coverage, 3503,
50567 /* 142025 */ GIR_EraseRootFromParent_Done,
50568 /* 142026 */ // Label 2923: @142026
50569 /* 142026 */ GIM_Reject,
50570 /* 142027 */ // Label 2920: @142027
50571 /* 142027 */ GIM_Reject,
50572 /* 142028 */ // Label 2916: @142028
50573 /* 142028 */ GIM_Reject,
50574 /* 142029 */ // Label 89: @142029
50575 /* 142029 */ GIM_Try, /*On fail goto*//*Label 2924*/ GIMT_Encode4(142309),
50576 /* 142034 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
50577 /* 142037 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2928*/ GIMT_Encode4(142308),
50578 /* 142048 */ /*GILLT_v4s32*//*Label 2925*/ GIMT_Encode4(142080), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
50579 /* 142064 */ /*GILLT_v8s16*//*Label 2926*/ GIMT_Encode4(142156), GIMT_Encode4(0), GIMT_Encode4(0),
50580 /* 142076 */ /*GILLT_v16s8*//*Label 2927*/ GIMT_Encode4(142232),
50581 /* 142080 */ // Label 2925: @142080
50582 /* 142080 */ GIM_Try, /*On fail goto*//*Label 2929*/ GIMT_Encode4(142155), // Rule ID 3502 //
50583 /* 142085 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50584 /* 142088 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50585 /* 142092 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50586 /* 142096 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMAXVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
50587 /* 142096 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50588 /* 142099 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
50589 /* 142103 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50590 /* 142108 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
50591 /* 142111 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50592 /* 142114 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50593 /* 142120 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50594 /* 142126 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50595 /* 142128 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu32),
50596 /* 142131 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50597 /* 142133 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50598 /* 142136 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50599 /* 142138 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50600 /* 142141 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50601 /* 142147 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50602 /* 142153 */ GIR_RootConstrainSelectedInstOperands,
50603 /* 142154 */ // GIR_Coverage, 3502,
50604 /* 142154 */ GIR_EraseRootFromParent_Done,
50605 /* 142155 */ // Label 2929: @142155
50606 /* 142155 */ GIM_Reject,
50607 /* 142156 */ // Label 2926: @142156
50608 /* 142156 */ GIM_Try, /*On fail goto*//*Label 2930*/ GIMT_Encode4(142231), // Rule ID 3501 //
50609 /* 142161 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50610 /* 142164 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50611 /* 142168 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50612 /* 142172 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMAXVu16:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
50613 /* 142172 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50614 /* 142175 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
50615 /* 142179 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50616 /* 142184 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
50617 /* 142187 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50618 /* 142190 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50619 /* 142196 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50620 /* 142202 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50621 /* 142204 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu16),
50622 /* 142207 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50623 /* 142209 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50624 /* 142212 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50625 /* 142214 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50626 /* 142217 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50627 /* 142223 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50628 /* 142229 */ GIR_RootConstrainSelectedInstOperands,
50629 /* 142230 */ // GIR_Coverage, 3501,
50630 /* 142230 */ GIR_EraseRootFromParent_Done,
50631 /* 142231 */ // Label 2930: @142231
50632 /* 142231 */ GIM_Reject,
50633 /* 142232 */ // Label 2927: @142232
50634 /* 142232 */ GIM_Try, /*On fail goto*//*Label 2931*/ GIMT_Encode4(142307), // Rule ID 3500 //
50635 /* 142237 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50636 /* 142240 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50637 /* 142244 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50638 /* 142248 */ // (vecreduce_umax:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMAXVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 0:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
50639 /* 142248 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50640 /* 142251 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
50641 /* 142255 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50642 /* 142260 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/0,
50643 /* 142263 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50644 /* 142266 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50645 /* 142272 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50646 /* 142278 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50647 /* 142280 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMAXVu8),
50648 /* 142283 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50649 /* 142285 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50650 /* 142288 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50651 /* 142290 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50652 /* 142293 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50653 /* 142299 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50654 /* 142305 */ GIR_RootConstrainSelectedInstOperands,
50655 /* 142306 */ // GIR_Coverage, 3500,
50656 /* 142306 */ GIR_EraseRootFromParent_Done,
50657 /* 142307 */ // Label 2931: @142307
50658 /* 142307 */ GIM_Reject,
50659 /* 142308 */ // Label 2928: @142308
50660 /* 142308 */ GIM_Reject,
50661 /* 142309 */ // Label 2924: @142309
50662 /* 142309 */ GIM_Reject,
50663 /* 142310 */ // Label 90: @142310
50664 /* 142310 */ GIM_Try, /*On fail goto*//*Label 2932*/ GIMT_Encode4(142605),
50665 /* 142315 */ GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32,
50666 /* 142318 */ GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(16), /*)*//*default:*//*Label 2936*/ GIMT_Encode4(142604),
50667 /* 142329 */ /*GILLT_v4s32*//*Label 2933*/ GIMT_Encode4(142361), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0),
50668 /* 142345 */ /*GILLT_v8s16*//*Label 2934*/ GIMT_Encode4(142444), GIMT_Encode4(0), GIMT_Encode4(0),
50669 /* 142357 */ /*GILLT_v16s8*//*Label 2935*/ GIMT_Encode4(142521),
50670 /* 142361 */ // Label 2933: @142361
50671 /* 142361 */ GIM_Try, /*On fail goto*//*Label 2937*/ GIMT_Encode4(142443), // Rule ID 3508 //
50672 /* 142366 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50673 /* 142369 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50674 /* 142373 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50675 /* 142377 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v4i32] }:$src) => (MVE_VMINVu32:{ *:[i32] } (t2MOVi:{ *:[i32] } 4294967295:{ *:[i32] }), ?:{ *:[v4i32] }:$src)
50676 /* 142377 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50677 /* 142380 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
50678 /* 142384 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50679 /* 142389 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(4294967295),
50680 /* 142399 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50681 /* 142402 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50682 /* 142408 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50683 /* 142414 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50684 /* 142416 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu32),
50685 /* 142419 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50686 /* 142421 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50687 /* 142424 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50688 /* 142426 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50689 /* 142429 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50690 /* 142435 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50691 /* 142441 */ GIR_RootConstrainSelectedInstOperands,
50692 /* 142442 */ // GIR_Coverage, 3508,
50693 /* 142442 */ GIR_EraseRootFromParent_Done,
50694 /* 142443 */ // Label 2937: @142443
50695 /* 142443 */ GIM_Reject,
50696 /* 142444 */ // Label 2934: @142444
50697 /* 142444 */ GIM_Try, /*On fail goto*//*Label 2938*/ GIMT_Encode4(142520), // Rule ID 3507 //
50698 /* 142449 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50699 /* 142452 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50700 /* 142456 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50701 /* 142460 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v8i16] }:$src) => (MVE_VMINVu16:{ *:[i32] } (t2MOVi16:{ *:[i32] } 65535:{ *:[i32] }), ?:{ *:[v8i16] }:$src)
50702 /* 142460 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50703 /* 142463 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi16),
50704 /* 142467 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50705 /* 142472 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535),
50706 /* 142482 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50707 /* 142485 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50708 /* 142491 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50709 /* 142493 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu16),
50710 /* 142496 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50711 /* 142498 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50712 /* 142501 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50713 /* 142503 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50714 /* 142506 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50715 /* 142512 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50716 /* 142518 */ GIR_RootConstrainSelectedInstOperands,
50717 /* 142519 */ // GIR_Coverage, 3507,
50718 /* 142519 */ GIR_EraseRootFromParent_Done,
50719 /* 142520 */ // Label 2938: @142520
50720 /* 142520 */ GIM_Reject,
50721 /* 142521 */ // Label 2935: @142521
50722 /* 142521 */ GIM_Try, /*On fail goto*//*Label 2939*/ GIMT_Encode4(142603), // Rule ID 3506 //
50723 /* 142526 */ GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMVEInt),
50724 /* 142529 */ GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(ARM::rGPRRegClassID),
50725 /* 142533 */ GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(ARM::MQPRRegClassID),
50726 /* 142537 */ // (vecreduce_umin:{ *:[i32] } MQPR:{ *:[v16i8] }:$src) => (MVE_VMINVu8:{ *:[i32] } (t2MOVi:{ *:[i32] } 255:{ *:[i32] }), ?:{ *:[v16i8] }:$src)
50727 /* 142537 */ GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32,
50728 /* 142540 */ GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(ARM::t2MOVi),
50729 /* 142544 */ GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
50730 /* 142549 */ GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(255),
50731 /* 142559 */ GIR_AddImm8, /*InsnID*/1, /*Imm*/14,
50732 /* 142562 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50733 /* 142568 */ GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50734 /* 142574 */ GIR_ConstrainSelectedInstOperands, /*InsnID*/1,
50735 /* 142576 */ GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(ARM::MVE_VMINVu8),
50736 /* 142579 */ GIR_RootToRootCopy, /*OpIdx*/0, // DstI[RdaDest]
50737 /* 142581 */ GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0,
50738 /* 142584 */ GIR_RootToRootCopy, /*OpIdx*/1, // src
50739 /* 142586 */ GIR_AddImm8, /*InsnID*/0, /*Imm*/0,
50740 /* 142589 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50741 /* 142595 */ GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(ARM::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0),
50742 /* 142601 */ GIR_RootConstrainSelectedInstOperands,
50743 /* 142602 */ // GIR_Coverage, 3506,
50744 /* 142602 */ GIR_EraseRootFromParent_Done,
50745 /* 142603 */ // Label 2939: @142603
50746 /* 142603 */ GIM_Reject,
50747 /* 142604 */ // Label 2936: @142604
50748 /* 142604 */ GIM_Reject,
50749 /* 142605 */ // Label 2932: @142605
50750 /* 142605 */ GIM_Reject,
50751 /* 142606 */ // Label 91: @142606
50752 /* 142606 */ GIM_Reject,
50753 /* 142607 */ }; // Size: 142607 bytes
50754 return MatchTable0;
50755}
50756#undef GIMT_Encode2
50757#undef GIMT_Encode4
50758#undef GIMT_Encode8
50759
50760#endif // ifdef GET_GLOBALISEL_IMPL
50761
50762#ifdef GET_GLOBALISEL_PREDICATES_DECL
50763PredicateBitset AvailableModuleFeatures;
50764mutable PredicateBitset AvailableFunctionFeatures;
50765PredicateBitset getAvailableFeatures() const {
50766 return AvailableModuleFeatures | AvailableFunctionFeatures;
50767}
50768PredicateBitset
50769computeAvailableModuleFeatures(const ARMSubtarget *Subtarget) const;
50770PredicateBitset
50771computeAvailableFunctionFeatures(const ARMSubtarget *Subtarget,
50772 const MachineFunction *MF) const;
50773void setupGeneratedPerFunctionState(MachineFunction &MF) override;
50774#endif // ifdef GET_GLOBALISEL_PREDICATES_DECL
50775#ifdef GET_GLOBALISEL_PREDICATES_INIT
50776AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)),
50777AvailableFunctionFeatures()
50778#endif // ifdef GET_GLOBALISEL_PREDICATES_INIT
50779